1 /* 2 * Copyright (c) 2013-2015, Mellanox Technologies, Ltd. All rights reserved. 3 * 4 * This software is available to you under a choice of one of two 5 * licenses. You may choose to be licensed under the terms of the GNU 6 * General Public License (GPL) Version 2, available from the file 7 * COPYING in the main directory of this source tree, or the 8 * OpenIB.org BSD license below: 9 * 10 * Redistribution and use in source and binary forms, with or 11 * without modification, are permitted provided that the following 12 * conditions are met: 13 * 14 * - Redistributions of source code must retain the above 15 * copyright notice, this list of conditions and the following 16 * disclaimer. 17 * 18 * - Redistributions in binary form must reproduce the above 19 * copyright notice, this list of conditions and the following 20 * disclaimer in the documentation and/or other materials 21 * provided with the distribution. 22 * 23 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, 24 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF 25 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND 26 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS 27 * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN 28 * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN 29 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE 30 * SOFTWARE. 31 */ 32 #ifndef MLX5_IFC_H 33 #define MLX5_IFC_H 34 35 #include "mlx5_ifc_fpga.h" 36 37 enum { 38 MLX5_EVENT_TYPE_CODING_COMPLETION_EVENTS = 0x0, 39 MLX5_EVENT_TYPE_CODING_PATH_MIGRATED_SUCCEEDED = 0x1, 40 MLX5_EVENT_TYPE_CODING_COMMUNICATION_ESTABLISHED = 0x2, 41 MLX5_EVENT_TYPE_CODING_SEND_QUEUE_DRAINED = 0x3, 42 MLX5_EVENT_TYPE_CODING_LAST_WQE_REACHED = 0x13, 43 MLX5_EVENT_TYPE_CODING_SRQ_LIMIT = 0x14, 44 MLX5_EVENT_TYPE_CODING_DCT_ALL_CONNECTIONS_CLOSED = 0x1c, 45 MLX5_EVENT_TYPE_CODING_DCT_ACCESS_KEY_VIOLATION = 0x1d, 46 MLX5_EVENT_TYPE_CODING_CQ_ERROR = 0x4, 47 MLX5_EVENT_TYPE_CODING_LOCAL_WQ_CATASTROPHIC_ERROR = 0x5, 48 MLX5_EVENT_TYPE_CODING_PATH_MIGRATION_FAILED = 0x7, 49 MLX5_EVENT_TYPE_CODING_PAGE_FAULT_EVENT = 0xc, 50 MLX5_EVENT_TYPE_CODING_INVALID_REQUEST_LOCAL_WQ_ERROR = 0x10, 51 MLX5_EVENT_TYPE_CODING_LOCAL_ACCESS_VIOLATION_WQ_ERROR = 0x11, 52 MLX5_EVENT_TYPE_CODING_LOCAL_SRQ_CATASTROPHIC_ERROR = 0x12, 53 MLX5_EVENT_TYPE_CODING_INTERNAL_ERROR = 0x8, 54 MLX5_EVENT_TYPE_CODING_PORT_STATE_CHANGE = 0x9, 55 MLX5_EVENT_TYPE_CODING_GPIO_EVENT = 0x15, 56 MLX5_EVENT_TYPE_CODING_REMOTE_CONFIGURATION_PROTOCOL_EVENT = 0x19, 57 MLX5_EVENT_TYPE_CODING_DOORBELL_BLUEFLAME_CONGESTION_EVENT = 0x1a, 58 MLX5_EVENT_TYPE_CODING_STALL_VL_EVENT = 0x1b, 59 MLX5_EVENT_TYPE_CODING_DROPPED_PACKET_LOGGED_EVENT = 0x1f, 60 MLX5_EVENT_TYPE_CODING_COMMAND_INTERFACE_COMPLETION = 0xa, 61 MLX5_EVENT_TYPE_CODING_PAGE_REQUEST = 0xb, 62 MLX5_EVENT_TYPE_CODING_FPGA_ERROR = 0x20, 63 MLX5_EVENT_TYPE_CODING_FPGA_QP_ERROR = 0x21 64 }; 65 66 enum { 67 MLX5_SET_HCA_CAP_OP_MOD_GENERAL_DEVICE = 0x0, 68 MLX5_SET_HCA_CAP_OP_MOD_ETHERNET_OFFLOADS = 0x1, 69 MLX5_SET_HCA_CAP_OP_MOD_ODP = 0x2, 70 MLX5_SET_HCA_CAP_OP_MOD_ATOMIC = 0x3, 71 MLX5_SET_HCA_CAP_OP_MOD_ROCE = 0x4, 72 MLX5_SET_HCA_CAP_OP_MOD_IPSEC = 0x15, 73 MLX5_SET_HCA_CAP_OP_MOD_GENERAL_DEVICE2 = 0x20, 74 MLX5_SET_HCA_CAP_OP_MOD_PORT_SELECTION = 0x25, 75 }; 76 77 enum { 78 MLX5_SHARED_RESOURCE_UID = 0xffff, 79 }; 80 81 enum { 82 MLX5_OBJ_TYPE_SW_ICM = 0x0008, 83 MLX5_OBJ_TYPE_GENEVE_TLV_OPT = 0x000b, 84 MLX5_OBJ_TYPE_VIRTIO_NET_Q = 0x000d, 85 MLX5_OBJ_TYPE_VIRTIO_Q_COUNTERS = 0x001c, 86 MLX5_OBJ_TYPE_MATCH_DEFINER = 0x0018, 87 MLX5_OBJ_TYPE_HEADER_MODIFY_ARGUMENT = 0x23, 88 MLX5_OBJ_TYPE_STC = 0x0040, 89 MLX5_OBJ_TYPE_RTC = 0x0041, 90 MLX5_OBJ_TYPE_STE = 0x0042, 91 MLX5_OBJ_TYPE_MODIFY_HDR_PATTERN = 0x0043, 92 MLX5_OBJ_TYPE_PAGE_TRACK = 0x46, 93 MLX5_OBJ_TYPE_MKEY = 0xff01, 94 MLX5_OBJ_TYPE_QP = 0xff02, 95 MLX5_OBJ_TYPE_PSV = 0xff03, 96 MLX5_OBJ_TYPE_RMP = 0xff04, 97 MLX5_OBJ_TYPE_XRC_SRQ = 0xff05, 98 MLX5_OBJ_TYPE_RQ = 0xff06, 99 MLX5_OBJ_TYPE_SQ = 0xff07, 100 MLX5_OBJ_TYPE_TIR = 0xff08, 101 MLX5_OBJ_TYPE_TIS = 0xff09, 102 MLX5_OBJ_TYPE_DCT = 0xff0a, 103 MLX5_OBJ_TYPE_XRQ = 0xff0b, 104 MLX5_OBJ_TYPE_RQT = 0xff0e, 105 MLX5_OBJ_TYPE_FLOW_COUNTER = 0xff0f, 106 MLX5_OBJ_TYPE_CQ = 0xff10, 107 MLX5_OBJ_TYPE_FT_ALIAS = 0xff15, 108 }; 109 110 enum { 111 MLX5_GENERAL_OBJ_TYPES_CAP_SW_ICM = (1ULL << MLX5_OBJ_TYPE_SW_ICM), 112 MLX5_GENERAL_OBJ_TYPES_CAP_GENEVE_TLV_OPT = (1ULL << 11), 113 MLX5_GENERAL_OBJ_TYPES_CAP_VIRTIO_NET_Q = (1ULL << 13), 114 MLX5_GENERAL_OBJ_TYPES_CAP_HEADER_MODIFY_ARGUMENT = 115 (1ULL << MLX5_OBJ_TYPE_HEADER_MODIFY_ARGUMENT), 116 MLX5_GENERAL_OBJ_TYPES_CAP_MACSEC_OFFLOAD = (1ULL << 39), 117 }; 118 119 enum { 120 MLX5_CMD_OP_QUERY_HCA_CAP = 0x100, 121 MLX5_CMD_OP_QUERY_ADAPTER = 0x101, 122 MLX5_CMD_OP_INIT_HCA = 0x102, 123 MLX5_CMD_OP_TEARDOWN_HCA = 0x103, 124 MLX5_CMD_OP_ENABLE_HCA = 0x104, 125 MLX5_CMD_OP_DISABLE_HCA = 0x105, 126 MLX5_CMD_OP_QUERY_PAGES = 0x107, 127 MLX5_CMD_OP_MANAGE_PAGES = 0x108, 128 MLX5_CMD_OP_SET_HCA_CAP = 0x109, 129 MLX5_CMD_OP_QUERY_ISSI = 0x10a, 130 MLX5_CMD_OP_SET_ISSI = 0x10b, 131 MLX5_CMD_OP_SET_DRIVER_VERSION = 0x10d, 132 MLX5_CMD_OP_QUERY_SF_PARTITION = 0x111, 133 MLX5_CMD_OP_ALLOC_SF = 0x113, 134 MLX5_CMD_OP_DEALLOC_SF = 0x114, 135 MLX5_CMD_OP_SUSPEND_VHCA = 0x115, 136 MLX5_CMD_OP_RESUME_VHCA = 0x116, 137 MLX5_CMD_OP_QUERY_VHCA_MIGRATION_STATE = 0x117, 138 MLX5_CMD_OP_SAVE_VHCA_STATE = 0x118, 139 MLX5_CMD_OP_LOAD_VHCA_STATE = 0x119, 140 MLX5_CMD_OP_CREATE_MKEY = 0x200, 141 MLX5_CMD_OP_QUERY_MKEY = 0x201, 142 MLX5_CMD_OP_DESTROY_MKEY = 0x202, 143 MLX5_CMD_OP_QUERY_SPECIAL_CONTEXTS = 0x203, 144 MLX5_CMD_OP_PAGE_FAULT_RESUME = 0x204, 145 MLX5_CMD_OP_ALLOC_MEMIC = 0x205, 146 MLX5_CMD_OP_DEALLOC_MEMIC = 0x206, 147 MLX5_CMD_OP_MODIFY_MEMIC = 0x207, 148 MLX5_CMD_OP_CREATE_EQ = 0x301, 149 MLX5_CMD_OP_DESTROY_EQ = 0x302, 150 MLX5_CMD_OP_QUERY_EQ = 0x303, 151 MLX5_CMD_OP_GEN_EQE = 0x304, 152 MLX5_CMD_OP_CREATE_CQ = 0x400, 153 MLX5_CMD_OP_DESTROY_CQ = 0x401, 154 MLX5_CMD_OP_QUERY_CQ = 0x402, 155 MLX5_CMD_OP_MODIFY_CQ = 0x403, 156 MLX5_CMD_OP_CREATE_QP = 0x500, 157 MLX5_CMD_OP_DESTROY_QP = 0x501, 158 MLX5_CMD_OP_RST2INIT_QP = 0x502, 159 MLX5_CMD_OP_INIT2RTR_QP = 0x503, 160 MLX5_CMD_OP_RTR2RTS_QP = 0x504, 161 MLX5_CMD_OP_RTS2RTS_QP = 0x505, 162 MLX5_CMD_OP_SQERR2RTS_QP = 0x506, 163 MLX5_CMD_OP_2ERR_QP = 0x507, 164 MLX5_CMD_OP_2RST_QP = 0x50a, 165 MLX5_CMD_OP_QUERY_QP = 0x50b, 166 MLX5_CMD_OP_SQD_RTS_QP = 0x50c, 167 MLX5_CMD_OP_INIT2INIT_QP = 0x50e, 168 MLX5_CMD_OP_CREATE_PSV = 0x600, 169 MLX5_CMD_OP_DESTROY_PSV = 0x601, 170 MLX5_CMD_OP_CREATE_SRQ = 0x700, 171 MLX5_CMD_OP_DESTROY_SRQ = 0x701, 172 MLX5_CMD_OP_QUERY_SRQ = 0x702, 173 MLX5_CMD_OP_ARM_RQ = 0x703, 174 MLX5_CMD_OP_CREATE_XRC_SRQ = 0x705, 175 MLX5_CMD_OP_DESTROY_XRC_SRQ = 0x706, 176 MLX5_CMD_OP_QUERY_XRC_SRQ = 0x707, 177 MLX5_CMD_OP_ARM_XRC_SRQ = 0x708, 178 MLX5_CMD_OP_CREATE_DCT = 0x710, 179 MLX5_CMD_OP_DESTROY_DCT = 0x711, 180 MLX5_CMD_OP_DRAIN_DCT = 0x712, 181 MLX5_CMD_OP_QUERY_DCT = 0x713, 182 MLX5_CMD_OP_ARM_DCT_FOR_KEY_VIOLATION = 0x714, 183 MLX5_CMD_OP_CREATE_XRQ = 0x717, 184 MLX5_CMD_OP_DESTROY_XRQ = 0x718, 185 MLX5_CMD_OP_QUERY_XRQ = 0x719, 186 MLX5_CMD_OP_ARM_XRQ = 0x71a, 187 MLX5_CMD_OP_QUERY_XRQ_DC_PARAMS_ENTRY = 0x725, 188 MLX5_CMD_OP_SET_XRQ_DC_PARAMS_ENTRY = 0x726, 189 MLX5_CMD_OP_QUERY_XRQ_ERROR_PARAMS = 0x727, 190 MLX5_CMD_OP_RELEASE_XRQ_ERROR = 0x729, 191 MLX5_CMD_OP_MODIFY_XRQ = 0x72a, 192 MLX5_CMD_OP_QUERY_ESW_FUNCTIONS = 0x740, 193 MLX5_CMD_OP_QUERY_VPORT_STATE = 0x750, 194 MLX5_CMD_OP_MODIFY_VPORT_STATE = 0x751, 195 MLX5_CMD_OP_QUERY_ESW_VPORT_CONTEXT = 0x752, 196 MLX5_CMD_OP_MODIFY_ESW_VPORT_CONTEXT = 0x753, 197 MLX5_CMD_OP_QUERY_NIC_VPORT_CONTEXT = 0x754, 198 MLX5_CMD_OP_MODIFY_NIC_VPORT_CONTEXT = 0x755, 199 MLX5_CMD_OP_QUERY_ROCE_ADDRESS = 0x760, 200 MLX5_CMD_OP_SET_ROCE_ADDRESS = 0x761, 201 MLX5_CMD_OP_QUERY_HCA_VPORT_CONTEXT = 0x762, 202 MLX5_CMD_OP_MODIFY_HCA_VPORT_CONTEXT = 0x763, 203 MLX5_CMD_OP_QUERY_HCA_VPORT_GID = 0x764, 204 MLX5_CMD_OP_QUERY_HCA_VPORT_PKEY = 0x765, 205 MLX5_CMD_OP_QUERY_VNIC_ENV = 0x76f, 206 MLX5_CMD_OP_QUERY_VPORT_COUNTER = 0x770, 207 MLX5_CMD_OP_ALLOC_Q_COUNTER = 0x771, 208 MLX5_CMD_OP_DEALLOC_Q_COUNTER = 0x772, 209 MLX5_CMD_OP_QUERY_Q_COUNTER = 0x773, 210 MLX5_CMD_OP_SET_MONITOR_COUNTER = 0x774, 211 MLX5_CMD_OP_ARM_MONITOR_COUNTER = 0x775, 212 MLX5_CMD_OP_SET_PP_RATE_LIMIT = 0x780, 213 MLX5_CMD_OP_QUERY_RATE_LIMIT = 0x781, 214 MLX5_CMD_OP_CREATE_SCHEDULING_ELEMENT = 0x782, 215 MLX5_CMD_OP_DESTROY_SCHEDULING_ELEMENT = 0x783, 216 MLX5_CMD_OP_QUERY_SCHEDULING_ELEMENT = 0x784, 217 MLX5_CMD_OP_MODIFY_SCHEDULING_ELEMENT = 0x785, 218 MLX5_CMD_OP_CREATE_QOS_PARA_VPORT = 0x786, 219 MLX5_CMD_OP_DESTROY_QOS_PARA_VPORT = 0x787, 220 MLX5_CMD_OP_ALLOC_PD = 0x800, 221 MLX5_CMD_OP_DEALLOC_PD = 0x801, 222 MLX5_CMD_OP_ALLOC_UAR = 0x802, 223 MLX5_CMD_OP_DEALLOC_UAR = 0x803, 224 MLX5_CMD_OP_CONFIG_INT_MODERATION = 0x804, 225 MLX5_CMD_OP_ACCESS_REG = 0x805, 226 MLX5_CMD_OP_ATTACH_TO_MCG = 0x806, 227 MLX5_CMD_OP_DETACH_FROM_MCG = 0x807, 228 MLX5_CMD_OP_GET_DROPPED_PACKET_LOG = 0x80a, 229 MLX5_CMD_OP_MAD_IFC = 0x50d, 230 MLX5_CMD_OP_QUERY_MAD_DEMUX = 0x80b, 231 MLX5_CMD_OP_SET_MAD_DEMUX = 0x80c, 232 MLX5_CMD_OP_NOP = 0x80d, 233 MLX5_CMD_OP_ALLOC_XRCD = 0x80e, 234 MLX5_CMD_OP_DEALLOC_XRCD = 0x80f, 235 MLX5_CMD_OP_ALLOC_TRANSPORT_DOMAIN = 0x816, 236 MLX5_CMD_OP_DEALLOC_TRANSPORT_DOMAIN = 0x817, 237 MLX5_CMD_OP_QUERY_CONG_STATUS = 0x822, 238 MLX5_CMD_OP_MODIFY_CONG_STATUS = 0x823, 239 MLX5_CMD_OP_QUERY_CONG_PARAMS = 0x824, 240 MLX5_CMD_OP_MODIFY_CONG_PARAMS = 0x825, 241 MLX5_CMD_OP_QUERY_CONG_STATISTICS = 0x826, 242 MLX5_CMD_OP_ADD_VXLAN_UDP_DPORT = 0x827, 243 MLX5_CMD_OP_DELETE_VXLAN_UDP_DPORT = 0x828, 244 MLX5_CMD_OP_SET_L2_TABLE_ENTRY = 0x829, 245 MLX5_CMD_OP_QUERY_L2_TABLE_ENTRY = 0x82a, 246 MLX5_CMD_OP_DELETE_L2_TABLE_ENTRY = 0x82b, 247 MLX5_CMD_OP_SET_WOL_ROL = 0x830, 248 MLX5_CMD_OP_QUERY_WOL_ROL = 0x831, 249 MLX5_CMD_OP_CREATE_LAG = 0x840, 250 MLX5_CMD_OP_MODIFY_LAG = 0x841, 251 MLX5_CMD_OP_QUERY_LAG = 0x842, 252 MLX5_CMD_OP_DESTROY_LAG = 0x843, 253 MLX5_CMD_OP_CREATE_VPORT_LAG = 0x844, 254 MLX5_CMD_OP_DESTROY_VPORT_LAG = 0x845, 255 MLX5_CMD_OP_CREATE_TIR = 0x900, 256 MLX5_CMD_OP_MODIFY_TIR = 0x901, 257 MLX5_CMD_OP_DESTROY_TIR = 0x902, 258 MLX5_CMD_OP_QUERY_TIR = 0x903, 259 MLX5_CMD_OP_CREATE_SQ = 0x904, 260 MLX5_CMD_OP_MODIFY_SQ = 0x905, 261 MLX5_CMD_OP_DESTROY_SQ = 0x906, 262 MLX5_CMD_OP_QUERY_SQ = 0x907, 263 MLX5_CMD_OP_CREATE_RQ = 0x908, 264 MLX5_CMD_OP_MODIFY_RQ = 0x909, 265 MLX5_CMD_OP_SET_DELAY_DROP_PARAMS = 0x910, 266 MLX5_CMD_OP_DESTROY_RQ = 0x90a, 267 MLX5_CMD_OP_QUERY_RQ = 0x90b, 268 MLX5_CMD_OP_CREATE_RMP = 0x90c, 269 MLX5_CMD_OP_MODIFY_RMP = 0x90d, 270 MLX5_CMD_OP_DESTROY_RMP = 0x90e, 271 MLX5_CMD_OP_QUERY_RMP = 0x90f, 272 MLX5_CMD_OP_CREATE_TIS = 0x912, 273 MLX5_CMD_OP_MODIFY_TIS = 0x913, 274 MLX5_CMD_OP_DESTROY_TIS = 0x914, 275 MLX5_CMD_OP_QUERY_TIS = 0x915, 276 MLX5_CMD_OP_CREATE_RQT = 0x916, 277 MLX5_CMD_OP_MODIFY_RQT = 0x917, 278 MLX5_CMD_OP_DESTROY_RQT = 0x918, 279 MLX5_CMD_OP_QUERY_RQT = 0x919, 280 MLX5_CMD_OP_SET_FLOW_TABLE_ROOT = 0x92f, 281 MLX5_CMD_OP_CREATE_FLOW_TABLE = 0x930, 282 MLX5_CMD_OP_DESTROY_FLOW_TABLE = 0x931, 283 MLX5_CMD_OP_QUERY_FLOW_TABLE = 0x932, 284 MLX5_CMD_OP_CREATE_FLOW_GROUP = 0x933, 285 MLX5_CMD_OP_DESTROY_FLOW_GROUP = 0x934, 286 MLX5_CMD_OP_QUERY_FLOW_GROUP = 0x935, 287 MLX5_CMD_OP_SET_FLOW_TABLE_ENTRY = 0x936, 288 MLX5_CMD_OP_QUERY_FLOW_TABLE_ENTRY = 0x937, 289 MLX5_CMD_OP_DELETE_FLOW_TABLE_ENTRY = 0x938, 290 MLX5_CMD_OP_ALLOC_FLOW_COUNTER = 0x939, 291 MLX5_CMD_OP_DEALLOC_FLOW_COUNTER = 0x93a, 292 MLX5_CMD_OP_QUERY_FLOW_COUNTER = 0x93b, 293 MLX5_CMD_OP_MODIFY_FLOW_TABLE = 0x93c, 294 MLX5_CMD_OP_ALLOC_PACKET_REFORMAT_CONTEXT = 0x93d, 295 MLX5_CMD_OP_DEALLOC_PACKET_REFORMAT_CONTEXT = 0x93e, 296 MLX5_CMD_OP_QUERY_PACKET_REFORMAT_CONTEXT = 0x93f, 297 MLX5_CMD_OP_ALLOC_MODIFY_HEADER_CONTEXT = 0x940, 298 MLX5_CMD_OP_DEALLOC_MODIFY_HEADER_CONTEXT = 0x941, 299 MLX5_CMD_OP_QUERY_MODIFY_HEADER_CONTEXT = 0x942, 300 MLX5_CMD_OP_FPGA_CREATE_QP = 0x960, 301 MLX5_CMD_OP_FPGA_MODIFY_QP = 0x961, 302 MLX5_CMD_OP_FPGA_QUERY_QP = 0x962, 303 MLX5_CMD_OP_FPGA_DESTROY_QP = 0x963, 304 MLX5_CMD_OP_FPGA_QUERY_QP_COUNTERS = 0x964, 305 MLX5_CMD_OP_CREATE_GENERAL_OBJECT = 0xa00, 306 MLX5_CMD_OP_MODIFY_GENERAL_OBJECT = 0xa01, 307 MLX5_CMD_OP_QUERY_GENERAL_OBJECT = 0xa02, 308 MLX5_CMD_OP_DESTROY_GENERAL_OBJECT = 0xa03, 309 MLX5_CMD_OP_CREATE_UCTX = 0xa04, 310 MLX5_CMD_OP_DESTROY_UCTX = 0xa06, 311 MLX5_CMD_OP_CREATE_UMEM = 0xa08, 312 MLX5_CMD_OP_DESTROY_UMEM = 0xa0a, 313 MLX5_CMD_OP_SYNC_STEERING = 0xb00, 314 MLX5_CMD_OP_QUERY_VHCA_STATE = 0xb0d, 315 MLX5_CMD_OP_MODIFY_VHCA_STATE = 0xb0e, 316 MLX5_CMD_OP_SYNC_CRYPTO = 0xb12, 317 MLX5_CMD_OP_ALLOW_OTHER_VHCA_ACCESS = 0xb16, 318 MLX5_CMD_OP_GENERATE_WQE = 0xb17, 319 MLX5_CMD_OPCODE_QUERY_VUID = 0xb22, 320 MLX5_CMD_OP_MAX 321 }; 322 323 /* Valid range for general commands that don't work over an object */ 324 enum { 325 MLX5_CMD_OP_GENERAL_START = 0xb00, 326 MLX5_CMD_OP_GENERAL_END = 0xd00, 327 }; 328 329 enum { 330 MLX5_FT_NIC_RX_2_NIC_RX_RDMA = BIT(0), 331 MLX5_FT_NIC_TX_RDMA_2_NIC_TX = BIT(1), 332 }; 333 334 enum { 335 MLX5_CMD_OP_MOD_UPDATE_HEADER_MODIFY_ARGUMENT = 0x1, 336 }; 337 338 struct mlx5_ifc_flow_table_fields_supported_bits { 339 u8 outer_dmac[0x1]; 340 u8 outer_smac[0x1]; 341 u8 outer_ether_type[0x1]; 342 u8 outer_ip_version[0x1]; 343 u8 outer_first_prio[0x1]; 344 u8 outer_first_cfi[0x1]; 345 u8 outer_first_vid[0x1]; 346 u8 outer_ipv4_ttl[0x1]; 347 u8 outer_second_prio[0x1]; 348 u8 outer_second_cfi[0x1]; 349 u8 outer_second_vid[0x1]; 350 u8 reserved_at_b[0x1]; 351 u8 outer_sip[0x1]; 352 u8 outer_dip[0x1]; 353 u8 outer_frag[0x1]; 354 u8 outer_ip_protocol[0x1]; 355 u8 outer_ip_ecn[0x1]; 356 u8 outer_ip_dscp[0x1]; 357 u8 outer_udp_sport[0x1]; 358 u8 outer_udp_dport[0x1]; 359 u8 outer_tcp_sport[0x1]; 360 u8 outer_tcp_dport[0x1]; 361 u8 outer_tcp_flags[0x1]; 362 u8 outer_gre_protocol[0x1]; 363 u8 outer_gre_key[0x1]; 364 u8 outer_vxlan_vni[0x1]; 365 u8 outer_geneve_vni[0x1]; 366 u8 outer_geneve_oam[0x1]; 367 u8 outer_geneve_protocol_type[0x1]; 368 u8 outer_geneve_opt_len[0x1]; 369 u8 source_vhca_port[0x1]; 370 u8 source_eswitch_port[0x1]; 371 372 u8 inner_dmac[0x1]; 373 u8 inner_smac[0x1]; 374 u8 inner_ether_type[0x1]; 375 u8 inner_ip_version[0x1]; 376 u8 inner_first_prio[0x1]; 377 u8 inner_first_cfi[0x1]; 378 u8 inner_first_vid[0x1]; 379 u8 reserved_at_27[0x1]; 380 u8 inner_second_prio[0x1]; 381 u8 inner_second_cfi[0x1]; 382 u8 inner_second_vid[0x1]; 383 u8 reserved_at_2b[0x1]; 384 u8 inner_sip[0x1]; 385 u8 inner_dip[0x1]; 386 u8 inner_frag[0x1]; 387 u8 inner_ip_protocol[0x1]; 388 u8 inner_ip_ecn[0x1]; 389 u8 inner_ip_dscp[0x1]; 390 u8 inner_udp_sport[0x1]; 391 u8 inner_udp_dport[0x1]; 392 u8 inner_tcp_sport[0x1]; 393 u8 inner_tcp_dport[0x1]; 394 u8 inner_tcp_flags[0x1]; 395 u8 reserved_at_37[0x9]; 396 397 u8 geneve_tlv_option_0_data[0x1]; 398 u8 geneve_tlv_option_0_exist[0x1]; 399 u8 reserved_at_42[0x3]; 400 u8 outer_first_mpls_over_udp[0x4]; 401 u8 outer_first_mpls_over_gre[0x4]; 402 u8 inner_first_mpls[0x4]; 403 u8 outer_first_mpls[0x4]; 404 u8 reserved_at_55[0x2]; 405 u8 outer_esp_spi[0x1]; 406 u8 reserved_at_58[0x2]; 407 u8 bth_dst_qp[0x1]; 408 u8 reserved_at_5b[0x5]; 409 410 u8 reserved_at_60[0x18]; 411 u8 metadata_reg_c_7[0x1]; 412 u8 metadata_reg_c_6[0x1]; 413 u8 metadata_reg_c_5[0x1]; 414 u8 metadata_reg_c_4[0x1]; 415 u8 metadata_reg_c_3[0x1]; 416 u8 metadata_reg_c_2[0x1]; 417 u8 metadata_reg_c_1[0x1]; 418 u8 metadata_reg_c_0[0x1]; 419 }; 420 421 /* Table 2170 - Flow Table Fields Supported 2 Format */ 422 struct mlx5_ifc_flow_table_fields_supported_2_bits { 423 u8 reserved_at_0[0x2]; 424 u8 inner_l4_type[0x1]; 425 u8 outer_l4_type[0x1]; 426 u8 reserved_at_4[0xa]; 427 u8 bth_opcode[0x1]; 428 u8 reserved_at_f[0x1]; 429 u8 tunnel_header_0_1[0x1]; 430 u8 reserved_at_11[0xf]; 431 432 u8 reserved_at_20[0x60]; 433 }; 434 435 struct mlx5_ifc_flow_table_prop_layout_bits { 436 u8 ft_support[0x1]; 437 u8 reserved_at_1[0x1]; 438 u8 flow_counter[0x1]; 439 u8 flow_modify_en[0x1]; 440 u8 modify_root[0x1]; 441 u8 identified_miss_table_mode[0x1]; 442 u8 flow_table_modify[0x1]; 443 u8 reformat[0x1]; 444 u8 decap[0x1]; 445 u8 reset_root_to_default[0x1]; 446 u8 pop_vlan[0x1]; 447 u8 push_vlan[0x1]; 448 u8 reserved_at_c[0x1]; 449 u8 pop_vlan_2[0x1]; 450 u8 push_vlan_2[0x1]; 451 u8 reformat_and_vlan_action[0x1]; 452 u8 reserved_at_10[0x1]; 453 u8 sw_owner[0x1]; 454 u8 reformat_l3_tunnel_to_l2[0x1]; 455 u8 reformat_l2_to_l3_tunnel[0x1]; 456 u8 reformat_and_modify_action[0x1]; 457 u8 ignore_flow_level[0x1]; 458 u8 reserved_at_16[0x1]; 459 u8 table_miss_action_domain[0x1]; 460 u8 termination_table[0x1]; 461 u8 reformat_and_fwd_to_table[0x1]; 462 u8 reserved_at_1a[0x2]; 463 u8 ipsec_encrypt[0x1]; 464 u8 ipsec_decrypt[0x1]; 465 u8 sw_owner_v2[0x1]; 466 u8 reserved_at_1f[0x1]; 467 468 u8 termination_table_raw_traffic[0x1]; 469 u8 reserved_at_21[0x1]; 470 u8 log_max_ft_size[0x6]; 471 u8 log_max_modify_header_context[0x8]; 472 u8 max_modify_header_actions[0x8]; 473 u8 max_ft_level[0x8]; 474 475 u8 reformat_add_esp_trasport[0x1]; 476 u8 reformat_l2_to_l3_esp_tunnel[0x1]; 477 u8 reformat_add_esp_transport_over_udp[0x1]; 478 u8 reformat_del_esp_trasport[0x1]; 479 u8 reformat_l3_esp_tunnel_to_l2[0x1]; 480 u8 reformat_del_esp_transport_over_udp[0x1]; 481 u8 execute_aso[0x1]; 482 u8 reserved_at_47[0x19]; 483 484 u8 reserved_at_60[0x2]; 485 u8 reformat_insert[0x1]; 486 u8 reformat_remove[0x1]; 487 u8 macsec_encrypt[0x1]; 488 u8 macsec_decrypt[0x1]; 489 u8 reserved_at_66[0x2]; 490 u8 reformat_add_macsec[0x1]; 491 u8 reformat_remove_macsec[0x1]; 492 u8 reparse[0x1]; 493 u8 reserved_at_6b[0x1]; 494 u8 cross_vhca_object[0x1]; 495 u8 reformat_l2_to_l3_audp_tunnel[0x1]; 496 u8 reformat_l3_audp_tunnel_to_l2[0x1]; 497 u8 ignore_flow_level_rtc_valid[0x1]; 498 u8 reserved_at_70[0x8]; 499 u8 log_max_ft_num[0x8]; 500 501 u8 reserved_at_80[0x10]; 502 u8 log_max_flow_counter[0x8]; 503 u8 log_max_destination[0x8]; 504 505 u8 reserved_at_a0[0x18]; 506 u8 log_max_flow[0x8]; 507 508 u8 reserved_at_c0[0x40]; 509 510 struct mlx5_ifc_flow_table_fields_supported_bits ft_field_support; 511 512 struct mlx5_ifc_flow_table_fields_supported_bits ft_field_bitmask_support; 513 }; 514 515 struct mlx5_ifc_odp_per_transport_service_cap_bits { 516 u8 send[0x1]; 517 u8 receive[0x1]; 518 u8 write[0x1]; 519 u8 read[0x1]; 520 u8 atomic[0x1]; 521 u8 srq_receive[0x1]; 522 u8 reserved_at_6[0x1a]; 523 }; 524 525 struct mlx5_ifc_ipv4_layout_bits { 526 u8 reserved_at_0[0x60]; 527 528 u8 ipv4[0x20]; 529 }; 530 531 struct mlx5_ifc_ipv6_layout_bits { 532 u8 ipv6[16][0x8]; 533 }; 534 535 struct mlx5_ifc_ipv6_simple_layout_bits { 536 u8 ipv6_127_96[0x20]; 537 u8 ipv6_95_64[0x20]; 538 u8 ipv6_63_32[0x20]; 539 u8 ipv6_31_0[0x20]; 540 }; 541 542 union mlx5_ifc_ipv6_layout_ipv4_layout_auto_bits { 543 struct mlx5_ifc_ipv6_simple_layout_bits ipv6_simple_layout; 544 struct mlx5_ifc_ipv6_layout_bits ipv6_layout; 545 struct mlx5_ifc_ipv4_layout_bits ipv4_layout; 546 u8 reserved_at_0[0x80]; 547 }; 548 549 enum { 550 MLX5_PACKET_L4_TYPE_NONE, 551 MLX5_PACKET_L4_TYPE_TCP, 552 MLX5_PACKET_L4_TYPE_UDP, 553 }; 554 555 struct mlx5_ifc_fte_match_set_lyr_2_4_bits { 556 u8 smac_47_16[0x20]; 557 558 u8 smac_15_0[0x10]; 559 u8 ethertype[0x10]; 560 561 u8 dmac_47_16[0x20]; 562 563 u8 dmac_15_0[0x10]; 564 u8 first_prio[0x3]; 565 u8 first_cfi[0x1]; 566 u8 first_vid[0xc]; 567 568 u8 ip_protocol[0x8]; 569 u8 ip_dscp[0x6]; 570 u8 ip_ecn[0x2]; 571 u8 cvlan_tag[0x1]; 572 u8 svlan_tag[0x1]; 573 u8 frag[0x1]; 574 u8 ip_version[0x4]; 575 u8 tcp_flags[0x9]; 576 577 u8 tcp_sport[0x10]; 578 u8 tcp_dport[0x10]; 579 580 u8 l4_type[0x2]; 581 u8 reserved_at_c2[0xe]; 582 u8 ipv4_ihl[0x4]; 583 u8 reserved_at_c4[0x4]; 584 585 u8 ttl_hoplimit[0x8]; 586 587 u8 udp_sport[0x10]; 588 u8 udp_dport[0x10]; 589 590 union mlx5_ifc_ipv6_layout_ipv4_layout_auto_bits src_ipv4_src_ipv6; 591 592 union mlx5_ifc_ipv6_layout_ipv4_layout_auto_bits dst_ipv4_dst_ipv6; 593 }; 594 595 struct mlx5_ifc_nvgre_key_bits { 596 u8 hi[0x18]; 597 u8 lo[0x8]; 598 }; 599 600 union mlx5_ifc_gre_key_bits { 601 struct mlx5_ifc_nvgre_key_bits nvgre; 602 u8 key[0x20]; 603 }; 604 605 struct mlx5_ifc_fte_match_set_misc_bits { 606 u8 gre_c_present[0x1]; 607 u8 reserved_at_1[0x1]; 608 u8 gre_k_present[0x1]; 609 u8 gre_s_present[0x1]; 610 u8 source_vhca_port[0x4]; 611 u8 source_sqn[0x18]; 612 613 u8 source_eswitch_owner_vhca_id[0x10]; 614 u8 source_port[0x10]; 615 616 u8 outer_second_prio[0x3]; 617 u8 outer_second_cfi[0x1]; 618 u8 outer_second_vid[0xc]; 619 u8 inner_second_prio[0x3]; 620 u8 inner_second_cfi[0x1]; 621 u8 inner_second_vid[0xc]; 622 623 u8 outer_second_cvlan_tag[0x1]; 624 u8 inner_second_cvlan_tag[0x1]; 625 u8 outer_second_svlan_tag[0x1]; 626 u8 inner_second_svlan_tag[0x1]; 627 u8 reserved_at_64[0xc]; 628 u8 gre_protocol[0x10]; 629 630 union mlx5_ifc_gre_key_bits gre_key; 631 632 u8 vxlan_vni[0x18]; 633 u8 bth_opcode[0x8]; 634 635 u8 geneve_vni[0x18]; 636 u8 reserved_at_d8[0x6]; 637 u8 geneve_tlv_option_0_exist[0x1]; 638 u8 geneve_oam[0x1]; 639 640 u8 reserved_at_e0[0xc]; 641 u8 outer_ipv6_flow_label[0x14]; 642 643 u8 reserved_at_100[0xc]; 644 u8 inner_ipv6_flow_label[0x14]; 645 646 u8 reserved_at_120[0xa]; 647 u8 geneve_opt_len[0x6]; 648 u8 geneve_protocol_type[0x10]; 649 650 u8 reserved_at_140[0x8]; 651 u8 bth_dst_qp[0x18]; 652 u8 inner_esp_spi[0x20]; 653 u8 outer_esp_spi[0x20]; 654 u8 reserved_at_1a0[0x60]; 655 }; 656 657 struct mlx5_ifc_fte_match_mpls_bits { 658 u8 mpls_label[0x14]; 659 u8 mpls_exp[0x3]; 660 u8 mpls_s_bos[0x1]; 661 u8 mpls_ttl[0x8]; 662 }; 663 664 struct mlx5_ifc_fte_match_set_misc2_bits { 665 struct mlx5_ifc_fte_match_mpls_bits outer_first_mpls; 666 667 struct mlx5_ifc_fte_match_mpls_bits inner_first_mpls; 668 669 struct mlx5_ifc_fte_match_mpls_bits outer_first_mpls_over_gre; 670 671 struct mlx5_ifc_fte_match_mpls_bits outer_first_mpls_over_udp; 672 673 u8 metadata_reg_c_7[0x20]; 674 675 u8 metadata_reg_c_6[0x20]; 676 677 u8 metadata_reg_c_5[0x20]; 678 679 u8 metadata_reg_c_4[0x20]; 680 681 u8 metadata_reg_c_3[0x20]; 682 683 u8 metadata_reg_c_2[0x20]; 684 685 u8 metadata_reg_c_1[0x20]; 686 687 u8 metadata_reg_c_0[0x20]; 688 689 u8 metadata_reg_a[0x20]; 690 691 u8 reserved_at_1a0[0x8]; 692 693 u8 macsec_syndrome[0x8]; 694 u8 ipsec_syndrome[0x8]; 695 u8 reserved_at_1b8[0x8]; 696 697 u8 reserved_at_1c0[0x40]; 698 }; 699 700 struct mlx5_ifc_fte_match_set_misc3_bits { 701 u8 inner_tcp_seq_num[0x20]; 702 703 u8 outer_tcp_seq_num[0x20]; 704 705 u8 inner_tcp_ack_num[0x20]; 706 707 u8 outer_tcp_ack_num[0x20]; 708 709 u8 reserved_at_80[0x8]; 710 u8 outer_vxlan_gpe_vni[0x18]; 711 712 u8 outer_vxlan_gpe_next_protocol[0x8]; 713 u8 outer_vxlan_gpe_flags[0x8]; 714 u8 reserved_at_b0[0x10]; 715 716 u8 icmp_header_data[0x20]; 717 718 u8 icmpv6_header_data[0x20]; 719 720 u8 icmp_type[0x8]; 721 u8 icmp_code[0x8]; 722 u8 icmpv6_type[0x8]; 723 u8 icmpv6_code[0x8]; 724 725 u8 geneve_tlv_option_0_data[0x20]; 726 727 u8 gtpu_teid[0x20]; 728 729 u8 gtpu_msg_type[0x8]; 730 u8 gtpu_msg_flags[0x8]; 731 u8 reserved_at_170[0x10]; 732 733 u8 gtpu_dw_2[0x20]; 734 735 u8 gtpu_first_ext_dw_0[0x20]; 736 737 u8 gtpu_dw_0[0x20]; 738 739 u8 reserved_at_1e0[0x20]; 740 }; 741 742 struct mlx5_ifc_fte_match_set_misc4_bits { 743 u8 prog_sample_field_value_0[0x20]; 744 745 u8 prog_sample_field_id_0[0x20]; 746 747 u8 prog_sample_field_value_1[0x20]; 748 749 u8 prog_sample_field_id_1[0x20]; 750 751 u8 prog_sample_field_value_2[0x20]; 752 753 u8 prog_sample_field_id_2[0x20]; 754 755 u8 prog_sample_field_value_3[0x20]; 756 757 u8 prog_sample_field_id_3[0x20]; 758 759 u8 reserved_at_100[0x100]; 760 }; 761 762 struct mlx5_ifc_fte_match_set_misc5_bits { 763 u8 macsec_tag_0[0x20]; 764 765 u8 macsec_tag_1[0x20]; 766 767 u8 macsec_tag_2[0x20]; 768 769 u8 macsec_tag_3[0x20]; 770 771 u8 tunnel_header_0[0x20]; 772 773 u8 tunnel_header_1[0x20]; 774 775 u8 tunnel_header_2[0x20]; 776 777 u8 tunnel_header_3[0x20]; 778 779 u8 reserved_at_100[0x100]; 780 }; 781 782 struct mlx5_ifc_cmd_pas_bits { 783 u8 pa_h[0x20]; 784 785 u8 pa_l[0x14]; 786 u8 reserved_at_34[0xc]; 787 }; 788 789 struct mlx5_ifc_uint64_bits { 790 u8 hi[0x20]; 791 792 u8 lo[0x20]; 793 }; 794 795 enum { 796 MLX5_ADS_STAT_RATE_NO_LIMIT = 0x0, 797 MLX5_ADS_STAT_RATE_2_5GBPS = 0x7, 798 MLX5_ADS_STAT_RATE_10GBPS = 0x8, 799 MLX5_ADS_STAT_RATE_30GBPS = 0x9, 800 MLX5_ADS_STAT_RATE_5GBPS = 0xa, 801 MLX5_ADS_STAT_RATE_20GBPS = 0xb, 802 MLX5_ADS_STAT_RATE_40GBPS = 0xc, 803 MLX5_ADS_STAT_RATE_60GBPS = 0xd, 804 MLX5_ADS_STAT_RATE_80GBPS = 0xe, 805 MLX5_ADS_STAT_RATE_120GBPS = 0xf, 806 }; 807 808 struct mlx5_ifc_ads_bits { 809 u8 fl[0x1]; 810 u8 free_ar[0x1]; 811 u8 reserved_at_2[0xe]; 812 u8 pkey_index[0x10]; 813 814 u8 plane_index[0x8]; 815 u8 grh[0x1]; 816 u8 mlid[0x7]; 817 u8 rlid[0x10]; 818 819 u8 ack_timeout[0x5]; 820 u8 reserved_at_45[0x3]; 821 u8 src_addr_index[0x8]; 822 u8 reserved_at_50[0x4]; 823 u8 stat_rate[0x4]; 824 u8 hop_limit[0x8]; 825 826 u8 reserved_at_60[0x4]; 827 u8 tclass[0x8]; 828 u8 flow_label[0x14]; 829 830 u8 rgid_rip[16][0x8]; 831 832 u8 reserved_at_100[0x4]; 833 u8 f_dscp[0x1]; 834 u8 f_ecn[0x1]; 835 u8 reserved_at_106[0x1]; 836 u8 f_eth_prio[0x1]; 837 u8 ecn[0x2]; 838 u8 dscp[0x6]; 839 u8 udp_sport[0x10]; 840 841 u8 dei_cfi[0x1]; 842 u8 eth_prio[0x3]; 843 u8 sl[0x4]; 844 u8 vhca_port_num[0x8]; 845 u8 rmac_47_32[0x10]; 846 847 u8 rmac_31_0[0x20]; 848 }; 849 850 struct mlx5_ifc_flow_table_nic_cap_bits { 851 u8 nic_rx_multi_path_tirs[0x1]; 852 u8 nic_rx_multi_path_tirs_fts[0x1]; 853 u8 allow_sniffer_and_nic_rx_shared_tir[0x1]; 854 u8 reserved_at_3[0x4]; 855 u8 sw_owner_reformat_supported[0x1]; 856 u8 reserved_at_8[0x18]; 857 858 u8 encap_general_header[0x1]; 859 u8 reserved_at_21[0xa]; 860 u8 log_max_packet_reformat_context[0x5]; 861 u8 reserved_at_30[0x6]; 862 u8 max_encap_header_size[0xa]; 863 u8 reserved_at_40[0x1c0]; 864 865 struct mlx5_ifc_flow_table_prop_layout_bits flow_table_properties_nic_receive; 866 867 struct mlx5_ifc_flow_table_prop_layout_bits flow_table_properties_nic_receive_rdma; 868 869 struct mlx5_ifc_flow_table_prop_layout_bits flow_table_properties_nic_receive_sniffer; 870 871 struct mlx5_ifc_flow_table_prop_layout_bits flow_table_properties_nic_transmit; 872 873 struct mlx5_ifc_flow_table_prop_layout_bits flow_table_properties_nic_transmit_rdma; 874 875 struct mlx5_ifc_flow_table_prop_layout_bits flow_table_properties_nic_transmit_sniffer; 876 877 u8 reserved_at_e00[0x600]; 878 879 struct mlx5_ifc_flow_table_fields_supported_2_bits ft_field_support_2_nic_receive; 880 881 u8 reserved_at_1480[0x80]; 882 883 struct mlx5_ifc_flow_table_fields_supported_2_bits ft_field_support_2_nic_receive_rdma; 884 885 u8 reserved_at_1580[0x280]; 886 887 struct mlx5_ifc_flow_table_fields_supported_2_bits ft_field_support_2_nic_transmit_rdma; 888 889 u8 reserved_at_1880[0x780]; 890 891 u8 sw_steering_nic_rx_action_drop_icm_address[0x40]; 892 893 u8 sw_steering_nic_tx_action_drop_icm_address[0x40]; 894 895 u8 sw_steering_nic_tx_action_allow_icm_address[0x40]; 896 897 u8 reserved_at_20c0[0x5f40]; 898 }; 899 900 struct mlx5_ifc_port_selection_cap_bits { 901 u8 reserved_at_0[0x10]; 902 u8 port_select_flow_table[0x1]; 903 u8 reserved_at_11[0x1]; 904 u8 port_select_flow_table_bypass[0x1]; 905 u8 reserved_at_13[0xd]; 906 907 u8 reserved_at_20[0x1e0]; 908 909 struct mlx5_ifc_flow_table_prop_layout_bits flow_table_properties_port_selection; 910 911 struct mlx5_ifc_flow_table_fields_supported_2_bits ft_field_support_2_port_selection; 912 913 u8 reserved_at_480[0x7b80]; 914 }; 915 916 enum { 917 MLX5_FDB_TO_VPORT_REG_C_0 = 0x01, 918 MLX5_FDB_TO_VPORT_REG_C_1 = 0x02, 919 MLX5_FDB_TO_VPORT_REG_C_2 = 0x04, 920 MLX5_FDB_TO_VPORT_REG_C_3 = 0x08, 921 MLX5_FDB_TO_VPORT_REG_C_4 = 0x10, 922 MLX5_FDB_TO_VPORT_REG_C_5 = 0x20, 923 MLX5_FDB_TO_VPORT_REG_C_6 = 0x40, 924 MLX5_FDB_TO_VPORT_REG_C_7 = 0x80, 925 }; 926 927 struct mlx5_ifc_flow_table_eswitch_cap_bits { 928 u8 fdb_to_vport_reg_c_id[0x8]; 929 u8 reserved_at_8[0x5]; 930 u8 fdb_uplink_hairpin[0x1]; 931 u8 fdb_multi_path_any_table_limit_regc[0x1]; 932 u8 reserved_at_f[0x1]; 933 u8 fdb_dynamic_tunnel[0x1]; 934 u8 reserved_at_11[0x1]; 935 u8 fdb_multi_path_any_table[0x1]; 936 u8 reserved_at_13[0x2]; 937 u8 fdb_modify_header_fwd_to_table[0x1]; 938 u8 fdb_ipv4_ttl_modify[0x1]; 939 u8 flow_source[0x1]; 940 u8 reserved_at_18[0x2]; 941 u8 multi_fdb_encap[0x1]; 942 u8 egress_acl_forward_to_vport[0x1]; 943 u8 fdb_multi_path_to_table[0x1]; 944 u8 reserved_at_1d[0x3]; 945 946 u8 reserved_at_20[0x1e0]; 947 948 struct mlx5_ifc_flow_table_prop_layout_bits flow_table_properties_nic_esw_fdb; 949 950 struct mlx5_ifc_flow_table_prop_layout_bits flow_table_properties_esw_acl_ingress; 951 952 struct mlx5_ifc_flow_table_prop_layout_bits flow_table_properties_esw_acl_egress; 953 954 u8 reserved_at_800[0xC00]; 955 956 struct mlx5_ifc_flow_table_fields_supported_2_bits ft_field_support_2_esw_fdb; 957 958 struct mlx5_ifc_flow_table_fields_supported_2_bits ft_field_bitmask_support_2_esw_fdb; 959 960 u8 reserved_at_1500[0x300]; 961 962 u8 sw_steering_fdb_action_drop_icm_address_rx[0x40]; 963 964 u8 sw_steering_fdb_action_drop_icm_address_tx[0x40]; 965 966 u8 sw_steering_uplink_icm_address_rx[0x40]; 967 968 u8 sw_steering_uplink_icm_address_tx[0x40]; 969 970 u8 reserved_at_1900[0x6700]; 971 }; 972 973 struct mlx5_ifc_wqe_based_flow_table_cap_bits { 974 u8 reserved_at_0[0x3]; 975 u8 log_max_num_ste[0x5]; 976 u8 reserved_at_8[0x3]; 977 u8 log_max_num_stc[0x5]; 978 u8 reserved_at_10[0x3]; 979 u8 log_max_num_rtc[0x5]; 980 u8 reserved_at_18[0x3]; 981 u8 log_max_num_header_modify_pattern[0x5]; 982 983 u8 rtc_hash_split_table[0x1]; 984 u8 rtc_linear_lookup_table[0x1]; 985 u8 reserved_at_22[0x1]; 986 u8 stc_alloc_log_granularity[0x5]; 987 u8 reserved_at_28[0x3]; 988 u8 stc_alloc_log_max[0x5]; 989 u8 reserved_at_30[0x3]; 990 u8 ste_alloc_log_granularity[0x5]; 991 u8 reserved_at_38[0x3]; 992 u8 ste_alloc_log_max[0x5]; 993 994 u8 reserved_at_40[0xb]; 995 u8 rtc_reparse_mode[0x5]; 996 u8 reserved_at_50[0x3]; 997 u8 rtc_index_mode[0x5]; 998 u8 reserved_at_58[0x3]; 999 u8 rtc_log_depth_max[0x5]; 1000 1001 u8 reserved_at_60[0x10]; 1002 u8 ste_format[0x10]; 1003 1004 u8 stc_action_type[0x80]; 1005 1006 u8 header_insert_type[0x10]; 1007 u8 header_remove_type[0x10]; 1008 1009 u8 trivial_match_definer[0x20]; 1010 1011 u8 reserved_at_140[0x1b]; 1012 u8 rtc_max_num_hash_definer_gen_wqe[0x5]; 1013 1014 u8 reserved_at_160[0x18]; 1015 u8 access_index_mode[0x8]; 1016 1017 u8 reserved_at_180[0x10]; 1018 u8 ste_format_gen_wqe[0x10]; 1019 1020 u8 linear_match_definer_reg_c3[0x20]; 1021 1022 u8 fdb_jump_to_tir_stc[0x1]; 1023 u8 reserved_at_1c1[0x1f]; 1024 }; 1025 1026 struct mlx5_ifc_esw_cap_bits { 1027 u8 reserved_at_0[0x1d]; 1028 u8 merged_eswitch[0x1]; 1029 u8 reserved_at_1e[0x2]; 1030 1031 u8 reserved_at_20[0x40]; 1032 1033 u8 esw_manager_vport_number_valid[0x1]; 1034 u8 reserved_at_61[0xf]; 1035 u8 esw_manager_vport_number[0x10]; 1036 1037 u8 reserved_at_80[0x780]; 1038 }; 1039 1040 enum { 1041 MLX5_COUNTER_SOURCE_ESWITCH = 0x0, 1042 MLX5_COUNTER_FLOW_ESWITCH = 0x1, 1043 }; 1044 1045 struct mlx5_ifc_e_switch_cap_bits { 1046 u8 vport_svlan_strip[0x1]; 1047 u8 vport_cvlan_strip[0x1]; 1048 u8 vport_svlan_insert[0x1]; 1049 u8 vport_cvlan_insert_if_not_exist[0x1]; 1050 u8 vport_cvlan_insert_overwrite[0x1]; 1051 u8 reserved_at_5[0x1]; 1052 u8 vport_cvlan_insert_always[0x1]; 1053 u8 esw_shared_ingress_acl[0x1]; 1054 u8 esw_uplink_ingress_acl[0x1]; 1055 u8 root_ft_on_other_esw[0x1]; 1056 u8 reserved_at_a[0xf]; 1057 u8 esw_functions_changed[0x1]; 1058 u8 reserved_at_1a[0x1]; 1059 u8 ecpf_vport_exists[0x1]; 1060 u8 counter_eswitch_affinity[0x1]; 1061 u8 merged_eswitch[0x1]; 1062 u8 nic_vport_node_guid_modify[0x1]; 1063 u8 nic_vport_port_guid_modify[0x1]; 1064 1065 u8 vxlan_encap_decap[0x1]; 1066 u8 nvgre_encap_decap[0x1]; 1067 u8 reserved_at_22[0x1]; 1068 u8 log_max_fdb_encap_uplink[0x5]; 1069 u8 reserved_at_21[0x3]; 1070 u8 log_max_packet_reformat_context[0x5]; 1071 u8 reserved_2b[0x6]; 1072 u8 max_encap_header_size[0xa]; 1073 1074 u8 reserved_at_40[0xb]; 1075 u8 log_max_esw_sf[0x5]; 1076 u8 esw_sf_base_id[0x10]; 1077 1078 u8 reserved_at_60[0x7a0]; 1079 1080 }; 1081 1082 struct mlx5_ifc_qos_cap_bits { 1083 u8 packet_pacing[0x1]; 1084 u8 esw_scheduling[0x1]; 1085 u8 esw_bw_share[0x1]; 1086 u8 esw_rate_limit[0x1]; 1087 u8 reserved_at_4[0x1]; 1088 u8 packet_pacing_burst_bound[0x1]; 1089 u8 packet_pacing_typical_size[0x1]; 1090 u8 reserved_at_7[0x1]; 1091 u8 nic_sq_scheduling[0x1]; 1092 u8 nic_bw_share[0x1]; 1093 u8 nic_rate_limit[0x1]; 1094 u8 packet_pacing_uid[0x1]; 1095 u8 log_esw_max_sched_depth[0x4]; 1096 u8 reserved_at_10[0x10]; 1097 1098 u8 reserved_at_20[0x9]; 1099 u8 esw_cross_esw_sched[0x1]; 1100 u8 reserved_at_2a[0x1]; 1101 u8 log_max_qos_nic_queue_group[0x5]; 1102 u8 reserved_at_30[0x10]; 1103 1104 u8 packet_pacing_max_rate[0x20]; 1105 1106 u8 packet_pacing_min_rate[0x20]; 1107 1108 u8 reserved_at_80[0xb]; 1109 u8 log_esw_max_rate_limit[0x5]; 1110 u8 packet_pacing_rate_table_size[0x10]; 1111 1112 u8 esw_element_type[0x10]; 1113 u8 esw_tsar_type[0x10]; 1114 1115 u8 reserved_at_c0[0x10]; 1116 u8 max_qos_para_vport[0x10]; 1117 1118 u8 max_tsar_bw_share[0x20]; 1119 1120 u8 nic_element_type[0x10]; 1121 u8 nic_tsar_type[0x10]; 1122 1123 u8 reserved_at_120[0x3]; 1124 u8 log_meter_aso_granularity[0x5]; 1125 u8 reserved_at_128[0x3]; 1126 u8 log_meter_aso_max_alloc[0x5]; 1127 u8 reserved_at_130[0x3]; 1128 u8 log_max_num_meter_aso[0x5]; 1129 u8 reserved_at_138[0x8]; 1130 1131 u8 reserved_at_140[0x6c0]; 1132 }; 1133 1134 struct mlx5_ifc_debug_cap_bits { 1135 u8 core_dump_general[0x1]; 1136 u8 core_dump_qp[0x1]; 1137 u8 reserved_at_2[0x7]; 1138 u8 resource_dump[0x1]; 1139 u8 reserved_at_a[0x16]; 1140 1141 u8 reserved_at_20[0x2]; 1142 u8 stall_detect[0x1]; 1143 u8 reserved_at_23[0x1d]; 1144 1145 u8 reserved_at_40[0x7c0]; 1146 }; 1147 1148 struct mlx5_ifc_per_protocol_networking_offload_caps_bits { 1149 u8 csum_cap[0x1]; 1150 u8 vlan_cap[0x1]; 1151 u8 lro_cap[0x1]; 1152 u8 lro_psh_flag[0x1]; 1153 u8 lro_time_stamp[0x1]; 1154 u8 reserved_at_5[0x2]; 1155 u8 wqe_vlan_insert[0x1]; 1156 u8 self_lb_en_modifiable[0x1]; 1157 u8 reserved_at_9[0x2]; 1158 u8 max_lso_cap[0x5]; 1159 u8 multi_pkt_send_wqe[0x2]; 1160 u8 wqe_inline_mode[0x2]; 1161 u8 rss_ind_tbl_cap[0x4]; 1162 u8 reg_umr_sq[0x1]; 1163 u8 scatter_fcs[0x1]; 1164 u8 enhanced_multi_pkt_send_wqe[0x1]; 1165 u8 tunnel_lso_const_out_ip_id[0x1]; 1166 u8 tunnel_lro_gre[0x1]; 1167 u8 tunnel_lro_vxlan[0x1]; 1168 u8 tunnel_stateless_gre[0x1]; 1169 u8 tunnel_stateless_vxlan[0x1]; 1170 1171 u8 swp[0x1]; 1172 u8 swp_csum[0x1]; 1173 u8 swp_lso[0x1]; 1174 u8 cqe_checksum_full[0x1]; 1175 u8 tunnel_stateless_geneve_tx[0x1]; 1176 u8 tunnel_stateless_mpls_over_udp[0x1]; 1177 u8 tunnel_stateless_mpls_over_gre[0x1]; 1178 u8 tunnel_stateless_vxlan_gpe[0x1]; 1179 u8 tunnel_stateless_ipv4_over_vxlan[0x1]; 1180 u8 tunnel_stateless_ip_over_ip[0x1]; 1181 u8 insert_trailer[0x1]; 1182 u8 reserved_at_2b[0x1]; 1183 u8 tunnel_stateless_ip_over_ip_rx[0x1]; 1184 u8 tunnel_stateless_ip_over_ip_tx[0x1]; 1185 u8 reserved_at_2e[0x2]; 1186 u8 max_vxlan_udp_ports[0x8]; 1187 u8 swp_csum_l4_partial[0x1]; 1188 u8 reserved_at_39[0x5]; 1189 u8 max_geneve_opt_len[0x1]; 1190 u8 tunnel_stateless_geneve_rx[0x1]; 1191 1192 u8 reserved_at_40[0x10]; 1193 u8 lro_min_mss_size[0x10]; 1194 1195 u8 reserved_at_60[0x120]; 1196 1197 u8 lro_timer_supported_periods[4][0x20]; 1198 1199 u8 reserved_at_200[0x600]; 1200 }; 1201 1202 enum { 1203 MLX5_TIMESTAMP_FORMAT_CAP_FREE_RUNNING = 0x0, 1204 MLX5_TIMESTAMP_FORMAT_CAP_REAL_TIME = 0x1, 1205 MLX5_TIMESTAMP_FORMAT_CAP_FREE_RUNNING_AND_REAL_TIME = 0x2, 1206 }; 1207 1208 struct mlx5_ifc_roce_cap_bits { 1209 u8 roce_apm[0x1]; 1210 u8 reserved_at_1[0x3]; 1211 u8 sw_r_roce_src_udp_port[0x1]; 1212 u8 fl_rc_qp_when_roce_disabled[0x1]; 1213 u8 fl_rc_qp_when_roce_enabled[0x1]; 1214 u8 roce_cc_general[0x1]; 1215 u8 qp_ooo_transmit_default[0x1]; 1216 u8 reserved_at_9[0x15]; 1217 u8 qp_ts_format[0x2]; 1218 1219 u8 reserved_at_20[0x60]; 1220 1221 u8 reserved_at_80[0xc]; 1222 u8 l3_type[0x4]; 1223 u8 reserved_at_90[0x8]; 1224 u8 roce_version[0x8]; 1225 1226 u8 reserved_at_a0[0x10]; 1227 u8 r_roce_dest_udp_port[0x10]; 1228 1229 u8 r_roce_max_src_udp_port[0x10]; 1230 u8 r_roce_min_src_udp_port[0x10]; 1231 1232 u8 reserved_at_e0[0x10]; 1233 u8 roce_address_table_size[0x10]; 1234 1235 u8 reserved_at_100[0x700]; 1236 }; 1237 1238 struct mlx5_ifc_sync_steering_in_bits { 1239 u8 opcode[0x10]; 1240 u8 uid[0x10]; 1241 1242 u8 reserved_at_20[0x10]; 1243 u8 op_mod[0x10]; 1244 1245 u8 reserved_at_40[0xc0]; 1246 }; 1247 1248 struct mlx5_ifc_sync_steering_out_bits { 1249 u8 status[0x8]; 1250 u8 reserved_at_8[0x18]; 1251 1252 u8 syndrome[0x20]; 1253 1254 u8 reserved_at_40[0x40]; 1255 }; 1256 1257 struct mlx5_ifc_sync_crypto_in_bits { 1258 u8 opcode[0x10]; 1259 u8 uid[0x10]; 1260 1261 u8 reserved_at_20[0x10]; 1262 u8 op_mod[0x10]; 1263 1264 u8 reserved_at_40[0x20]; 1265 1266 u8 reserved_at_60[0x10]; 1267 u8 crypto_type[0x10]; 1268 1269 u8 reserved_at_80[0x80]; 1270 }; 1271 1272 struct mlx5_ifc_sync_crypto_out_bits { 1273 u8 status[0x8]; 1274 u8 reserved_at_8[0x18]; 1275 1276 u8 syndrome[0x20]; 1277 1278 u8 reserved_at_40[0x40]; 1279 }; 1280 1281 struct mlx5_ifc_device_mem_cap_bits { 1282 u8 memic[0x1]; 1283 u8 reserved_at_1[0x1f]; 1284 1285 u8 reserved_at_20[0xb]; 1286 u8 log_min_memic_alloc_size[0x5]; 1287 u8 reserved_at_30[0x8]; 1288 u8 log_max_memic_addr_alignment[0x8]; 1289 1290 u8 memic_bar_start_addr[0x40]; 1291 1292 u8 memic_bar_size[0x20]; 1293 1294 u8 max_memic_size[0x20]; 1295 1296 u8 steering_sw_icm_start_address[0x40]; 1297 1298 u8 reserved_at_100[0x8]; 1299 u8 log_header_modify_sw_icm_size[0x8]; 1300 u8 reserved_at_110[0x2]; 1301 u8 log_sw_icm_alloc_granularity[0x6]; 1302 u8 log_steering_sw_icm_size[0x8]; 1303 1304 u8 log_indirect_encap_sw_icm_size[0x8]; 1305 u8 reserved_at_128[0x10]; 1306 u8 log_header_modify_pattern_sw_icm_size[0x8]; 1307 1308 u8 header_modify_sw_icm_start_address[0x40]; 1309 1310 u8 reserved_at_180[0x40]; 1311 1312 u8 header_modify_pattern_sw_icm_start_address[0x40]; 1313 1314 u8 memic_operations[0x20]; 1315 1316 u8 reserved_at_220[0x20]; 1317 1318 u8 indirect_encap_sw_icm_start_address[0x40]; 1319 1320 u8 reserved_at_280[0x580]; 1321 }; 1322 1323 struct mlx5_ifc_device_event_cap_bits { 1324 u8 user_affiliated_events[4][0x40]; 1325 1326 u8 user_unaffiliated_events[4][0x40]; 1327 }; 1328 1329 struct mlx5_ifc_virtio_emulation_cap_bits { 1330 u8 desc_tunnel_offload_type[0x1]; 1331 u8 eth_frame_offload_type[0x1]; 1332 u8 virtio_version_1_0[0x1]; 1333 u8 device_features_bits_mask[0xd]; 1334 u8 event_mode[0x8]; 1335 u8 virtio_queue_type[0x8]; 1336 1337 u8 max_tunnel_desc[0x10]; 1338 u8 reserved_at_30[0x3]; 1339 u8 log_doorbell_stride[0x5]; 1340 u8 reserved_at_38[0x3]; 1341 u8 log_doorbell_bar_size[0x5]; 1342 1343 u8 doorbell_bar_offset[0x40]; 1344 1345 u8 max_emulated_devices[0x8]; 1346 u8 max_num_virtio_queues[0x18]; 1347 1348 u8 reserved_at_a0[0x20]; 1349 1350 u8 reserved_at_c0[0x13]; 1351 u8 desc_group_mkey_supported[0x1]; 1352 u8 freeze_to_rdy_supported[0x1]; 1353 u8 reserved_at_d5[0xb]; 1354 1355 u8 reserved_at_e0[0x20]; 1356 1357 u8 umem_1_buffer_param_a[0x20]; 1358 1359 u8 umem_1_buffer_param_b[0x20]; 1360 1361 u8 umem_2_buffer_param_a[0x20]; 1362 1363 u8 umem_2_buffer_param_b[0x20]; 1364 1365 u8 umem_3_buffer_param_a[0x20]; 1366 1367 u8 umem_3_buffer_param_b[0x20]; 1368 1369 u8 reserved_at_1c0[0x640]; 1370 }; 1371 1372 enum { 1373 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_QP_1_BYTE = 0x0, 1374 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_QP_2_BYTES = 0x2, 1375 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_QP_4_BYTES = 0x4, 1376 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_QP_8_BYTES = 0x8, 1377 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_QP_16_BYTES = 0x10, 1378 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_QP_32_BYTES = 0x20, 1379 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_QP_64_BYTES = 0x40, 1380 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_QP_128_BYTES = 0x80, 1381 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_QP_256_BYTES = 0x100, 1382 }; 1383 1384 enum { 1385 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_DC_1_BYTE = 0x1, 1386 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_DC_2_BYTES = 0x2, 1387 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_DC_4_BYTES = 0x4, 1388 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_DC_8_BYTES = 0x8, 1389 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_DC_16_BYTES = 0x10, 1390 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_DC_32_BYTES = 0x20, 1391 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_DC_64_BYTES = 0x40, 1392 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_DC_128_BYTES = 0x80, 1393 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_DC_256_BYTES = 0x100, 1394 }; 1395 1396 struct mlx5_ifc_atomic_caps_bits { 1397 u8 reserved_at_0[0x40]; 1398 1399 u8 atomic_req_8B_endianness_mode[0x2]; 1400 u8 reserved_at_42[0x4]; 1401 u8 supported_atomic_req_8B_endianness_mode_1[0x1]; 1402 1403 u8 reserved_at_47[0x19]; 1404 1405 u8 reserved_at_60[0x20]; 1406 1407 u8 reserved_at_80[0x10]; 1408 u8 atomic_operations[0x10]; 1409 1410 u8 reserved_at_a0[0x10]; 1411 u8 atomic_size_qp[0x10]; 1412 1413 u8 reserved_at_c0[0x10]; 1414 u8 atomic_size_dc[0x10]; 1415 1416 u8 reserved_at_e0[0x720]; 1417 }; 1418 1419 struct mlx5_ifc_odp_scheme_cap_bits { 1420 u8 reserved_at_0[0x40]; 1421 1422 u8 sig[0x1]; 1423 u8 reserved_at_41[0x4]; 1424 u8 page_prefetch[0x1]; 1425 u8 reserved_at_46[0x1a]; 1426 1427 u8 reserved_at_60[0x20]; 1428 1429 struct mlx5_ifc_odp_per_transport_service_cap_bits rc_odp_caps; 1430 1431 struct mlx5_ifc_odp_per_transport_service_cap_bits uc_odp_caps; 1432 1433 struct mlx5_ifc_odp_per_transport_service_cap_bits ud_odp_caps; 1434 1435 struct mlx5_ifc_odp_per_transport_service_cap_bits xrc_odp_caps; 1436 1437 struct mlx5_ifc_odp_per_transport_service_cap_bits dc_odp_caps; 1438 1439 u8 reserved_at_120[0xe0]; 1440 }; 1441 1442 struct mlx5_ifc_odp_cap_bits { 1443 struct mlx5_ifc_odp_scheme_cap_bits transport_page_fault_scheme_cap; 1444 1445 struct mlx5_ifc_odp_scheme_cap_bits memory_page_fault_scheme_cap; 1446 1447 u8 reserved_at_400[0x200]; 1448 1449 u8 mem_page_fault[0x1]; 1450 u8 reserved_at_601[0x1f]; 1451 1452 u8 reserved_at_620[0x1e0]; 1453 }; 1454 1455 struct mlx5_ifc_tls_cap_bits { 1456 u8 tls_1_2_aes_gcm_128[0x1]; 1457 u8 tls_1_3_aes_gcm_128[0x1]; 1458 u8 tls_1_2_aes_gcm_256[0x1]; 1459 u8 tls_1_3_aes_gcm_256[0x1]; 1460 u8 reserved_at_4[0x1c]; 1461 1462 u8 reserved_at_20[0x7e0]; 1463 }; 1464 1465 struct mlx5_ifc_ipsec_cap_bits { 1466 u8 ipsec_full_offload[0x1]; 1467 u8 ipsec_crypto_offload[0x1]; 1468 u8 ipsec_esn[0x1]; 1469 u8 ipsec_crypto_esp_aes_gcm_256_encrypt[0x1]; 1470 u8 ipsec_crypto_esp_aes_gcm_128_encrypt[0x1]; 1471 u8 ipsec_crypto_esp_aes_gcm_256_decrypt[0x1]; 1472 u8 ipsec_crypto_esp_aes_gcm_128_decrypt[0x1]; 1473 u8 reserved_at_7[0x4]; 1474 u8 log_max_ipsec_offload[0x5]; 1475 u8 reserved_at_10[0x10]; 1476 1477 u8 min_log_ipsec_full_replay_window[0x8]; 1478 u8 max_log_ipsec_full_replay_window[0x8]; 1479 u8 reserved_at_30[0x7d0]; 1480 }; 1481 1482 struct mlx5_ifc_macsec_cap_bits { 1483 u8 macsec_epn[0x1]; 1484 u8 reserved_at_1[0x2]; 1485 u8 macsec_crypto_esp_aes_gcm_256_encrypt[0x1]; 1486 u8 macsec_crypto_esp_aes_gcm_128_encrypt[0x1]; 1487 u8 macsec_crypto_esp_aes_gcm_256_decrypt[0x1]; 1488 u8 macsec_crypto_esp_aes_gcm_128_decrypt[0x1]; 1489 u8 reserved_at_7[0x4]; 1490 u8 log_max_macsec_offload[0x5]; 1491 u8 reserved_at_10[0x10]; 1492 1493 u8 min_log_macsec_full_replay_window[0x8]; 1494 u8 max_log_macsec_full_replay_window[0x8]; 1495 u8 reserved_at_30[0x10]; 1496 1497 u8 reserved_at_40[0x7c0]; 1498 }; 1499 1500 enum { 1501 MLX5_WQ_TYPE_LINKED_LIST = 0x0, 1502 MLX5_WQ_TYPE_CYCLIC = 0x1, 1503 MLX5_WQ_TYPE_LINKED_LIST_STRIDING_RQ = 0x2, 1504 MLX5_WQ_TYPE_CYCLIC_STRIDING_RQ = 0x3, 1505 }; 1506 1507 enum { 1508 MLX5_WQ_END_PAD_MODE_NONE = 0x0, 1509 MLX5_WQ_END_PAD_MODE_ALIGN = 0x1, 1510 }; 1511 1512 enum { 1513 MLX5_CMD_HCA_CAP_GID_TABLE_SIZE_8_GID_ENTRIES = 0x0, 1514 MLX5_CMD_HCA_CAP_GID_TABLE_SIZE_16_GID_ENTRIES = 0x1, 1515 MLX5_CMD_HCA_CAP_GID_TABLE_SIZE_32_GID_ENTRIES = 0x2, 1516 MLX5_CMD_HCA_CAP_GID_TABLE_SIZE_64_GID_ENTRIES = 0x3, 1517 MLX5_CMD_HCA_CAP_GID_TABLE_SIZE_128_GID_ENTRIES = 0x4, 1518 }; 1519 1520 enum { 1521 MLX5_CMD_HCA_CAP_PKEY_TABLE_SIZE_128_ENTRIES = 0x0, 1522 MLX5_CMD_HCA_CAP_PKEY_TABLE_SIZE_256_ENTRIES = 0x1, 1523 MLX5_CMD_HCA_CAP_PKEY_TABLE_SIZE_512_ENTRIES = 0x2, 1524 MLX5_CMD_HCA_CAP_PKEY_TABLE_SIZE_1K_ENTRIES = 0x3, 1525 MLX5_CMD_HCA_CAP_PKEY_TABLE_SIZE_2K_ENTRIES = 0x4, 1526 MLX5_CMD_HCA_CAP_PKEY_TABLE_SIZE_4K_ENTRIES = 0x5, 1527 }; 1528 1529 enum { 1530 MLX5_CMD_HCA_CAP_PORT_TYPE_IB = 0x0, 1531 MLX5_CMD_HCA_CAP_PORT_TYPE_ETHERNET = 0x1, 1532 }; 1533 1534 enum { 1535 MLX5_CMD_HCA_CAP_CMDIF_CHECKSUM_DISABLED = 0x0, 1536 MLX5_CMD_HCA_CAP_CMDIF_CHECKSUM_INITIAL_STATE = 0x1, 1537 MLX5_CMD_HCA_CAP_CMDIF_CHECKSUM_ENABLED = 0x3, 1538 }; 1539 1540 enum { 1541 MLX5_CAP_PORT_TYPE_IB = 0x0, 1542 MLX5_CAP_PORT_TYPE_ETH = 0x1, 1543 }; 1544 1545 enum { 1546 MLX5_CAP_UMR_FENCE_STRONG = 0x0, 1547 MLX5_CAP_UMR_FENCE_SMALL = 0x1, 1548 MLX5_CAP_UMR_FENCE_NONE = 0x2, 1549 }; 1550 1551 enum { 1552 MLX5_FLEX_IPV4_OVER_VXLAN_ENABLED = 1 << 0, 1553 MLX5_FLEX_IPV6_OVER_VXLAN_ENABLED = 1 << 1, 1554 MLX5_FLEX_IPV6_OVER_IP_ENABLED = 1 << 2, 1555 MLX5_FLEX_PARSER_GENEVE_ENABLED = 1 << 3, 1556 MLX5_FLEX_PARSER_MPLS_OVER_GRE_ENABLED = 1 << 4, 1557 MLX5_FLEX_PARSER_MPLS_OVER_UDP_ENABLED = 1 << 5, 1558 MLX5_FLEX_P_BIT_VXLAN_GPE_ENABLED = 1 << 6, 1559 MLX5_FLEX_PARSER_VXLAN_GPE_ENABLED = 1 << 7, 1560 MLX5_FLEX_PARSER_ICMP_V4_ENABLED = 1 << 8, 1561 MLX5_FLEX_PARSER_ICMP_V6_ENABLED = 1 << 9, 1562 MLX5_FLEX_PARSER_GENEVE_TLV_OPTION_0_ENABLED = 1 << 10, 1563 MLX5_FLEX_PARSER_GTPU_ENABLED = 1 << 11, 1564 MLX5_FLEX_PARSER_GTPU_DW_2_ENABLED = 1 << 16, 1565 MLX5_FLEX_PARSER_GTPU_FIRST_EXT_DW_0_ENABLED = 1 << 17, 1566 MLX5_FLEX_PARSER_GTPU_DW_0_ENABLED = 1 << 18, 1567 MLX5_FLEX_PARSER_GTPU_TEID_ENABLED = 1 << 19, 1568 }; 1569 1570 enum { 1571 MLX5_UCTX_CAP_RAW_TX = 1UL << 0, 1572 MLX5_UCTX_CAP_INTERNAL_DEV_RES = 1UL << 1, 1573 MLX5_UCTX_CAP_RDMA_CTRL = 1UL << 3, 1574 MLX5_UCTX_CAP_RDMA_CTRL_OTHER_VHCA = 1UL << 4, 1575 }; 1576 1577 #define MLX5_FC_BULK_SIZE_FACTOR 128 1578 1579 enum mlx5_fc_bulk_alloc_bitmask { 1580 MLX5_FC_BULK_128 = (1 << 0), 1581 MLX5_FC_BULK_256 = (1 << 1), 1582 MLX5_FC_BULK_512 = (1 << 2), 1583 MLX5_FC_BULK_1024 = (1 << 3), 1584 MLX5_FC_BULK_2048 = (1 << 4), 1585 MLX5_FC_BULK_4096 = (1 << 5), 1586 MLX5_FC_BULK_8192 = (1 << 6), 1587 MLX5_FC_BULK_16384 = (1 << 7), 1588 }; 1589 1590 #define MLX5_FC_BULK_NUM_FCS(fc_enum) (MLX5_FC_BULK_SIZE_FACTOR * (fc_enum)) 1591 1592 #define MLX5_FT_MAX_MULTIPATH_LEVEL 63 1593 1594 enum { 1595 MLX5_STEERING_FORMAT_CONNECTX_5 = 0, 1596 MLX5_STEERING_FORMAT_CONNECTX_6DX = 1, 1597 MLX5_STEERING_FORMAT_CONNECTX_7 = 2, 1598 MLX5_STEERING_FORMAT_CONNECTX_8 = 3, 1599 }; 1600 1601 struct mlx5_ifc_cmd_hca_cap_bits { 1602 u8 reserved_at_0[0x6]; 1603 u8 page_request_disable[0x1]; 1604 u8 abs_native_port_num[0x1]; 1605 u8 reserved_at_8[0x8]; 1606 u8 shared_object_to_user_object_allowed[0x1]; 1607 u8 reserved_at_13[0xe]; 1608 u8 vhca_resource_manager[0x1]; 1609 1610 u8 hca_cap_2[0x1]; 1611 u8 create_lag_when_not_master_up[0x1]; 1612 u8 dtor[0x1]; 1613 u8 event_on_vhca_state_teardown_request[0x1]; 1614 u8 event_on_vhca_state_in_use[0x1]; 1615 u8 event_on_vhca_state_active[0x1]; 1616 u8 event_on_vhca_state_allocated[0x1]; 1617 u8 event_on_vhca_state_invalid[0x1]; 1618 u8 reserved_at_28[0x8]; 1619 u8 vhca_id[0x10]; 1620 1621 u8 reserved_at_40[0x40]; 1622 1623 u8 log_max_srq_sz[0x8]; 1624 u8 log_max_qp_sz[0x8]; 1625 u8 event_cap[0x1]; 1626 u8 reserved_at_91[0x2]; 1627 u8 isolate_vl_tc_new[0x1]; 1628 u8 reserved_at_94[0x4]; 1629 u8 prio_tag_required[0x1]; 1630 u8 reserved_at_99[0x2]; 1631 u8 log_max_qp[0x5]; 1632 1633 u8 reserved_at_a0[0x3]; 1634 u8 ece_support[0x1]; 1635 u8 reserved_at_a4[0x5]; 1636 u8 reg_c_preserve[0x1]; 1637 u8 reserved_at_aa[0x1]; 1638 u8 log_max_srq[0x5]; 1639 u8 reserved_at_b0[0x1]; 1640 u8 uplink_follow[0x1]; 1641 u8 ts_cqe_to_dest_cqn[0x1]; 1642 u8 reserved_at_b3[0x6]; 1643 u8 go_back_n[0x1]; 1644 u8 reserved_at_ba[0x6]; 1645 1646 u8 max_sgl_for_optimized_performance[0x8]; 1647 u8 log_max_cq_sz[0x8]; 1648 u8 relaxed_ordering_write_umr[0x1]; 1649 u8 relaxed_ordering_read_umr[0x1]; 1650 u8 reserved_at_d2[0x7]; 1651 u8 virtio_net_device_emualtion_manager[0x1]; 1652 u8 virtio_blk_device_emualtion_manager[0x1]; 1653 u8 log_max_cq[0x5]; 1654 1655 u8 log_max_eq_sz[0x8]; 1656 u8 relaxed_ordering_write[0x1]; 1657 u8 relaxed_ordering_read_pci_enabled[0x1]; 1658 u8 log_max_mkey[0x6]; 1659 u8 reserved_at_f0[0x6]; 1660 u8 terminate_scatter_list_mkey[0x1]; 1661 u8 repeated_mkey[0x1]; 1662 u8 dump_fill_mkey[0x1]; 1663 u8 reserved_at_f9[0x2]; 1664 u8 fast_teardown[0x1]; 1665 u8 log_max_eq[0x4]; 1666 1667 u8 max_indirection[0x8]; 1668 u8 fixed_buffer_size[0x1]; 1669 u8 log_max_mrw_sz[0x7]; 1670 u8 force_teardown[0x1]; 1671 u8 reserved_at_111[0x1]; 1672 u8 log_max_bsf_list_size[0x6]; 1673 u8 umr_extended_translation_offset[0x1]; 1674 u8 null_mkey[0x1]; 1675 u8 log_max_klm_list_size[0x6]; 1676 1677 u8 reserved_at_120[0x2]; 1678 u8 qpc_extension[0x1]; 1679 u8 reserved_at_123[0x7]; 1680 u8 log_max_ra_req_dc[0x6]; 1681 u8 reserved_at_130[0x2]; 1682 u8 eth_wqe_too_small[0x1]; 1683 u8 reserved_at_133[0x6]; 1684 u8 vnic_env_cq_overrun[0x1]; 1685 u8 log_max_ra_res_dc[0x6]; 1686 1687 u8 reserved_at_140[0x5]; 1688 u8 release_all_pages[0x1]; 1689 u8 must_not_use[0x1]; 1690 u8 reserved_at_147[0x2]; 1691 u8 roce_accl[0x1]; 1692 u8 log_max_ra_req_qp[0x6]; 1693 u8 reserved_at_150[0xa]; 1694 u8 log_max_ra_res_qp[0x6]; 1695 1696 u8 end_pad[0x1]; 1697 u8 cc_query_allowed[0x1]; 1698 u8 cc_modify_allowed[0x1]; 1699 u8 start_pad[0x1]; 1700 u8 cache_line_128byte[0x1]; 1701 u8 reserved_at_165[0x4]; 1702 u8 rts2rts_qp_counters_set_id[0x1]; 1703 u8 reserved_at_16a[0x2]; 1704 u8 vnic_env_int_rq_oob[0x1]; 1705 u8 sbcam_reg[0x1]; 1706 u8 reserved_at_16e[0x1]; 1707 u8 qcam_reg[0x1]; 1708 u8 gid_table_size[0x10]; 1709 1710 u8 out_of_seq_cnt[0x1]; 1711 u8 vport_counters[0x1]; 1712 u8 retransmission_q_counters[0x1]; 1713 u8 debug[0x1]; 1714 u8 modify_rq_counter_set_id[0x1]; 1715 u8 rq_delay_drop[0x1]; 1716 u8 max_qp_cnt[0xa]; 1717 u8 pkey_table_size[0x10]; 1718 1719 u8 vport_group_manager[0x1]; 1720 u8 vhca_group_manager[0x1]; 1721 u8 ib_virt[0x1]; 1722 u8 eth_virt[0x1]; 1723 u8 vnic_env_queue_counters[0x1]; 1724 u8 ets[0x1]; 1725 u8 nic_flow_table[0x1]; 1726 u8 eswitch_manager[0x1]; 1727 u8 device_memory[0x1]; 1728 u8 mcam_reg[0x1]; 1729 u8 pcam_reg[0x1]; 1730 u8 local_ca_ack_delay[0x5]; 1731 u8 port_module_event[0x1]; 1732 u8 enhanced_error_q_counters[0x1]; 1733 u8 ports_check[0x1]; 1734 u8 reserved_at_1b3[0x1]; 1735 u8 disable_link_up[0x1]; 1736 u8 beacon_led[0x1]; 1737 u8 port_type[0x2]; 1738 u8 num_ports[0x8]; 1739 1740 u8 reserved_at_1c0[0x1]; 1741 u8 pps[0x1]; 1742 u8 pps_modify[0x1]; 1743 u8 log_max_msg[0x5]; 1744 u8 reserved_at_1c8[0x4]; 1745 u8 max_tc[0x4]; 1746 u8 temp_warn_event[0x1]; 1747 u8 dcbx[0x1]; 1748 u8 general_notification_event[0x1]; 1749 u8 reserved_at_1d3[0x2]; 1750 u8 fpga[0x1]; 1751 u8 rol_s[0x1]; 1752 u8 rol_g[0x1]; 1753 u8 reserved_at_1d8[0x1]; 1754 u8 wol_s[0x1]; 1755 u8 wol_g[0x1]; 1756 u8 wol_a[0x1]; 1757 u8 wol_b[0x1]; 1758 u8 wol_m[0x1]; 1759 u8 wol_u[0x1]; 1760 u8 wol_p[0x1]; 1761 1762 u8 stat_rate_support[0x10]; 1763 u8 reserved_at_1f0[0x1]; 1764 u8 pci_sync_for_fw_update_event[0x1]; 1765 u8 reserved_at_1f2[0x6]; 1766 u8 init2_lag_tx_port_affinity[0x1]; 1767 u8 reserved_at_1fa[0x2]; 1768 u8 wqe_based_flow_table_update_cap[0x1]; 1769 u8 cqe_version[0x4]; 1770 1771 u8 compact_address_vector[0x1]; 1772 u8 striding_rq[0x1]; 1773 u8 reserved_at_202[0x1]; 1774 u8 ipoib_enhanced_offloads[0x1]; 1775 u8 ipoib_basic_offloads[0x1]; 1776 u8 reserved_at_205[0x1]; 1777 u8 repeated_block_disabled[0x1]; 1778 u8 umr_modify_entity_size_disabled[0x1]; 1779 u8 umr_modify_atomic_disabled[0x1]; 1780 u8 umr_indirect_mkey_disabled[0x1]; 1781 u8 umr_fence[0x2]; 1782 u8 dc_req_scat_data_cqe[0x1]; 1783 u8 reserved_at_20d[0x2]; 1784 u8 drain_sigerr[0x1]; 1785 u8 cmdif_checksum[0x2]; 1786 u8 sigerr_cqe[0x1]; 1787 u8 reserved_at_213[0x1]; 1788 u8 wq_signature[0x1]; 1789 u8 sctr_data_cqe[0x1]; 1790 u8 reserved_at_216[0x1]; 1791 u8 sho[0x1]; 1792 u8 tph[0x1]; 1793 u8 rf[0x1]; 1794 u8 dct[0x1]; 1795 u8 qos[0x1]; 1796 u8 eth_net_offloads[0x1]; 1797 u8 roce[0x1]; 1798 u8 atomic[0x1]; 1799 u8 reserved_at_21f[0x1]; 1800 1801 u8 cq_oi[0x1]; 1802 u8 cq_resize[0x1]; 1803 u8 cq_moderation[0x1]; 1804 u8 cq_period_mode_modify[0x1]; 1805 u8 reserved_at_224[0x2]; 1806 u8 cq_eq_remap[0x1]; 1807 u8 pg[0x1]; 1808 u8 block_lb_mc[0x1]; 1809 u8 reserved_at_229[0x1]; 1810 u8 scqe_break_moderation[0x1]; 1811 u8 cq_period_start_from_cqe[0x1]; 1812 u8 cd[0x1]; 1813 u8 reserved_at_22d[0x1]; 1814 u8 apm[0x1]; 1815 u8 vector_calc[0x1]; 1816 u8 umr_ptr_rlky[0x1]; 1817 u8 imaicl[0x1]; 1818 u8 qp_packet_based[0x1]; 1819 u8 reserved_at_233[0x3]; 1820 u8 qkv[0x1]; 1821 u8 pkv[0x1]; 1822 u8 set_deth_sqpn[0x1]; 1823 u8 reserved_at_239[0x3]; 1824 u8 xrc[0x1]; 1825 u8 ud[0x1]; 1826 u8 uc[0x1]; 1827 u8 rc[0x1]; 1828 1829 u8 uar_4k[0x1]; 1830 u8 reserved_at_241[0x7]; 1831 u8 fl_rc_qp_when_roce_disabled[0x1]; 1832 u8 regexp_params[0x1]; 1833 u8 uar_sz[0x6]; 1834 u8 port_selection_cap[0x1]; 1835 u8 nic_cap_reg[0x1]; 1836 u8 umem_uid_0[0x1]; 1837 u8 reserved_at_253[0x5]; 1838 u8 log_pg_sz[0x8]; 1839 1840 u8 bf[0x1]; 1841 u8 driver_version[0x1]; 1842 u8 pad_tx_eth_packet[0x1]; 1843 u8 reserved_at_263[0x3]; 1844 u8 mkey_by_name[0x1]; 1845 u8 reserved_at_267[0x4]; 1846 1847 u8 log_bf_reg_size[0x5]; 1848 1849 u8 reserved_at_270[0x3]; 1850 u8 qp_error_syndrome[0x1]; 1851 u8 reserved_at_274[0x2]; 1852 u8 lag_dct[0x2]; 1853 u8 lag_tx_port_affinity[0x1]; 1854 u8 lag_native_fdb_selection[0x1]; 1855 u8 reserved_at_27a[0x1]; 1856 u8 lag_master[0x1]; 1857 u8 num_lag_ports[0x4]; 1858 1859 u8 reserved_at_280[0x10]; 1860 u8 max_wqe_sz_sq[0x10]; 1861 1862 u8 reserved_at_2a0[0xb]; 1863 u8 shampo[0x1]; 1864 u8 reserved_at_2ac[0x4]; 1865 u8 max_wqe_sz_rq[0x10]; 1866 1867 u8 max_flow_counter_31_16[0x10]; 1868 u8 max_wqe_sz_sq_dc[0x10]; 1869 1870 u8 reserved_at_2e0[0x7]; 1871 u8 max_qp_mcg[0x19]; 1872 1873 u8 reserved_at_300[0x10]; 1874 u8 flow_counter_bulk_alloc[0x8]; 1875 u8 log_max_mcg[0x8]; 1876 1877 u8 reserved_at_320[0x3]; 1878 u8 log_max_transport_domain[0x5]; 1879 u8 reserved_at_328[0x2]; 1880 u8 relaxed_ordering_read[0x1]; 1881 u8 log_max_pd[0x5]; 1882 u8 dp_ordering_ooo_all_ud[0x1]; 1883 u8 dp_ordering_ooo_all_uc[0x1]; 1884 u8 dp_ordering_ooo_all_xrc[0x1]; 1885 u8 dp_ordering_ooo_all_dc[0x1]; 1886 u8 dp_ordering_ooo_all_rc[0x1]; 1887 u8 pcie_reset_using_hotreset_method[0x1]; 1888 u8 pci_sync_for_fw_update_with_driver_unload[0x1]; 1889 u8 vnic_env_cnt_steering_fail[0x1]; 1890 u8 vport_counter_local_loopback[0x1]; 1891 u8 q_counter_aggregation[0x1]; 1892 u8 q_counter_other_vport[0x1]; 1893 u8 log_max_xrcd[0x5]; 1894 1895 u8 nic_receive_steering_discard[0x1]; 1896 u8 receive_discard_vport_down[0x1]; 1897 u8 transmit_discard_vport_down[0x1]; 1898 u8 eq_overrun_count[0x1]; 1899 u8 reserved_at_344[0x1]; 1900 u8 invalid_command_count[0x1]; 1901 u8 quota_exceeded_count[0x1]; 1902 u8 reserved_at_347[0x1]; 1903 u8 log_max_flow_counter_bulk[0x8]; 1904 u8 max_flow_counter_15_0[0x10]; 1905 1906 1907 u8 reserved_at_360[0x3]; 1908 u8 log_max_rq[0x5]; 1909 u8 reserved_at_368[0x3]; 1910 u8 log_max_sq[0x5]; 1911 u8 reserved_at_370[0x3]; 1912 u8 log_max_tir[0x5]; 1913 u8 reserved_at_378[0x3]; 1914 u8 log_max_tis[0x5]; 1915 1916 u8 basic_cyclic_rcv_wqe[0x1]; 1917 u8 reserved_at_381[0x2]; 1918 u8 log_max_rmp[0x5]; 1919 u8 reserved_at_388[0x3]; 1920 u8 log_max_rqt[0x5]; 1921 u8 reserved_at_390[0x3]; 1922 u8 log_max_rqt_size[0x5]; 1923 u8 reserved_at_398[0x3]; 1924 u8 log_max_tis_per_sq[0x5]; 1925 1926 u8 ext_stride_num_range[0x1]; 1927 u8 roce_rw_supported[0x1]; 1928 u8 log_max_current_uc_list_wr_supported[0x1]; 1929 u8 log_max_stride_sz_rq[0x5]; 1930 u8 reserved_at_3a8[0x3]; 1931 u8 log_min_stride_sz_rq[0x5]; 1932 u8 reserved_at_3b0[0x3]; 1933 u8 log_max_stride_sz_sq[0x5]; 1934 u8 reserved_at_3b8[0x3]; 1935 u8 log_min_stride_sz_sq[0x5]; 1936 1937 u8 hairpin[0x1]; 1938 u8 reserved_at_3c1[0x2]; 1939 u8 log_max_hairpin_queues[0x5]; 1940 u8 reserved_at_3c8[0x3]; 1941 u8 log_max_hairpin_wq_data_sz[0x5]; 1942 u8 reserved_at_3d0[0x3]; 1943 u8 log_max_hairpin_num_packets[0x5]; 1944 u8 reserved_at_3d8[0x3]; 1945 u8 log_max_wq_sz[0x5]; 1946 1947 u8 nic_vport_change_event[0x1]; 1948 u8 disable_local_lb_uc[0x1]; 1949 u8 disable_local_lb_mc[0x1]; 1950 u8 log_min_hairpin_wq_data_sz[0x5]; 1951 u8 reserved_at_3e8[0x1]; 1952 u8 silent_mode[0x1]; 1953 u8 vhca_state[0x1]; 1954 u8 log_max_vlan_list[0x5]; 1955 u8 reserved_at_3f0[0x3]; 1956 u8 log_max_current_mc_list[0x5]; 1957 u8 reserved_at_3f8[0x3]; 1958 u8 log_max_current_uc_list[0x5]; 1959 1960 u8 general_obj_types[0x40]; 1961 1962 u8 sq_ts_format[0x2]; 1963 u8 rq_ts_format[0x2]; 1964 u8 steering_format_version[0x4]; 1965 u8 create_qp_start_hint[0x18]; 1966 1967 u8 reserved_at_460[0x1]; 1968 u8 ats[0x1]; 1969 u8 cross_vhca_rqt[0x1]; 1970 u8 log_max_uctx[0x5]; 1971 u8 reserved_at_468[0x1]; 1972 u8 crypto[0x1]; 1973 u8 ipsec_offload[0x1]; 1974 u8 log_max_umem[0x5]; 1975 u8 max_num_eqs[0x10]; 1976 1977 u8 reserved_at_480[0x1]; 1978 u8 tls_tx[0x1]; 1979 u8 tls_rx[0x1]; 1980 u8 log_max_l2_table[0x5]; 1981 u8 reserved_at_488[0x8]; 1982 u8 log_uar_page_sz[0x10]; 1983 1984 u8 reserved_at_4a0[0x20]; 1985 u8 device_frequency_mhz[0x20]; 1986 u8 device_frequency_khz[0x20]; 1987 1988 u8 reserved_at_500[0x20]; 1989 u8 num_of_uars_per_page[0x20]; 1990 1991 u8 flex_parser_protocols[0x20]; 1992 1993 u8 max_geneve_tlv_options[0x8]; 1994 u8 reserved_at_568[0x3]; 1995 u8 max_geneve_tlv_option_data_len[0x5]; 1996 u8 reserved_at_570[0x1]; 1997 u8 adv_rdma[0x1]; 1998 u8 reserved_at_572[0x7]; 1999 u8 adv_virtualization[0x1]; 2000 u8 reserved_at_57a[0x6]; 2001 2002 u8 reserved_at_580[0xb]; 2003 u8 log_max_dci_stream_channels[0x5]; 2004 u8 reserved_at_590[0x3]; 2005 u8 log_max_dci_errored_streams[0x5]; 2006 u8 reserved_at_598[0x8]; 2007 2008 u8 reserved_at_5a0[0x10]; 2009 u8 enhanced_cqe_compression[0x1]; 2010 u8 reserved_at_5b1[0x1]; 2011 u8 crossing_vhca_mkey[0x1]; 2012 u8 log_max_dek[0x5]; 2013 u8 reserved_at_5b8[0x4]; 2014 u8 mini_cqe_resp_stride_index[0x1]; 2015 u8 cqe_128_always[0x1]; 2016 u8 cqe_compression_128[0x1]; 2017 u8 cqe_compression[0x1]; 2018 2019 u8 cqe_compression_timeout[0x10]; 2020 u8 cqe_compression_max_num[0x10]; 2021 2022 u8 reserved_at_5e0[0x8]; 2023 u8 flex_parser_id_gtpu_dw_0[0x4]; 2024 u8 reserved_at_5ec[0x4]; 2025 u8 tag_matching[0x1]; 2026 u8 rndv_offload_rc[0x1]; 2027 u8 rndv_offload_dc[0x1]; 2028 u8 log_tag_matching_list_sz[0x5]; 2029 u8 reserved_at_5f8[0x3]; 2030 u8 log_max_xrq[0x5]; 2031 2032 u8 affiliate_nic_vport_criteria[0x8]; 2033 u8 native_port_num[0x8]; 2034 u8 num_vhca_ports[0x8]; 2035 u8 flex_parser_id_gtpu_teid[0x4]; 2036 u8 reserved_at_61c[0x2]; 2037 u8 sw_owner_id[0x1]; 2038 u8 reserved_at_61f[0x1]; 2039 2040 u8 max_num_of_monitor_counters[0x10]; 2041 u8 num_ppcnt_monitor_counters[0x10]; 2042 2043 u8 max_num_sf[0x10]; 2044 u8 num_q_monitor_counters[0x10]; 2045 2046 u8 reserved_at_660[0x20]; 2047 2048 u8 sf[0x1]; 2049 u8 sf_set_partition[0x1]; 2050 u8 reserved_at_682[0x1]; 2051 u8 log_max_sf[0x5]; 2052 u8 apu[0x1]; 2053 u8 reserved_at_689[0x4]; 2054 u8 migration[0x1]; 2055 u8 reserved_at_68e[0x2]; 2056 u8 log_min_sf_size[0x8]; 2057 u8 max_num_sf_partitions[0x8]; 2058 2059 u8 uctx_cap[0x20]; 2060 2061 u8 reserved_at_6c0[0x4]; 2062 u8 flex_parser_id_geneve_tlv_option_0[0x4]; 2063 u8 flex_parser_id_icmp_dw1[0x4]; 2064 u8 flex_parser_id_icmp_dw0[0x4]; 2065 u8 flex_parser_id_icmpv6_dw1[0x4]; 2066 u8 flex_parser_id_icmpv6_dw0[0x4]; 2067 u8 flex_parser_id_outer_first_mpls_over_gre[0x4]; 2068 u8 flex_parser_id_outer_first_mpls_over_udp_label[0x4]; 2069 2070 u8 max_num_match_definer[0x10]; 2071 u8 sf_base_id[0x10]; 2072 2073 u8 flex_parser_id_gtpu_dw_2[0x4]; 2074 u8 flex_parser_id_gtpu_first_ext_dw_0[0x4]; 2075 u8 num_total_dynamic_vf_msix[0x18]; 2076 u8 reserved_at_720[0x14]; 2077 u8 dynamic_msix_table_size[0xc]; 2078 u8 reserved_at_740[0xc]; 2079 u8 min_dynamic_vf_msix_table_size[0x4]; 2080 u8 reserved_at_750[0x2]; 2081 u8 data_direct[0x1]; 2082 u8 reserved_at_753[0x1]; 2083 u8 max_dynamic_vf_msix_table_size[0xc]; 2084 2085 u8 reserved_at_760[0x3]; 2086 u8 log_max_num_header_modify_argument[0x5]; 2087 u8 log_header_modify_argument_granularity_offset[0x4]; 2088 u8 log_header_modify_argument_granularity[0x4]; 2089 u8 reserved_at_770[0x3]; 2090 u8 log_header_modify_argument_max_alloc[0x5]; 2091 u8 reserved_at_778[0x8]; 2092 2093 u8 vhca_tunnel_commands[0x40]; 2094 u8 match_definer_format_supported[0x40]; 2095 }; 2096 2097 enum { 2098 MLX5_CROSS_VHCA_OBJ_TO_OBJ_SUPPORTED_LOCAL_FLOW_TABLE_TO_REMOTE_FLOW_TABLE_MISS = 0x80000, 2099 MLX5_CROSS_VHCA_OBJ_TO_OBJ_SUPPORTED_LOCAL_FLOW_TABLE_ROOT_TO_REMOTE_FLOW_TABLE = (1ULL << 20), 2100 }; 2101 2102 enum { 2103 MLX5_ALLOWED_OBJ_FOR_OTHER_VHCA_ACCESS_FLOW_TABLE = 0x200, 2104 }; 2105 2106 struct mlx5_ifc_cmd_hca_cap_2_bits { 2107 u8 reserved_at_0[0x80]; 2108 2109 u8 migratable[0x1]; 2110 u8 reserved_at_81[0x7]; 2111 u8 dp_ordering_force[0x1]; 2112 u8 reserved_at_89[0x9]; 2113 u8 query_vuid[0x1]; 2114 u8 reserved_at_93[0x5]; 2115 u8 umr_log_entity_size_5[0x1]; 2116 u8 reserved_at_99[0x7]; 2117 2118 u8 max_reformat_insert_size[0x8]; 2119 u8 max_reformat_insert_offset[0x8]; 2120 u8 max_reformat_remove_size[0x8]; 2121 u8 max_reformat_remove_offset[0x8]; 2122 2123 u8 reserved_at_c0[0x8]; 2124 u8 migration_multi_load[0x1]; 2125 u8 migration_tracking_state[0x1]; 2126 u8 multiplane_qp_ud[0x1]; 2127 u8 reserved_at_cb[0x5]; 2128 u8 migration_in_chunks[0x1]; 2129 u8 reserved_at_d1[0x1]; 2130 u8 sf_eq_usage[0x1]; 2131 u8 reserved_at_d3[0x5]; 2132 u8 multiplane[0x1]; 2133 u8 reserved_at_d9[0x7]; 2134 2135 u8 cross_vhca_object_to_object_supported[0x20]; 2136 2137 u8 allowed_object_for_other_vhca_access[0x40]; 2138 2139 u8 reserved_at_140[0x60]; 2140 2141 u8 flow_table_type_2_type[0x8]; 2142 u8 reserved_at_1a8[0x2]; 2143 u8 format_select_dw_8_6_ext[0x1]; 2144 u8 log_min_mkey_entity_size[0x5]; 2145 u8 reserved_at_1b0[0x10]; 2146 2147 u8 general_obj_types_127_64[0x40]; 2148 u8 reserved_at_200[0x20]; 2149 2150 u8 reserved_at_220[0x1]; 2151 u8 sw_vhca_id_valid[0x1]; 2152 u8 sw_vhca_id[0xe]; 2153 u8 reserved_at_230[0x10]; 2154 2155 u8 reserved_at_240[0xb]; 2156 u8 ts_cqe_metadata_size2wqe_counter[0x5]; 2157 u8 reserved_at_250[0x10]; 2158 2159 u8 reserved_at_260[0x20]; 2160 2161 u8 format_select_dw_gtpu_dw_0[0x8]; 2162 u8 format_select_dw_gtpu_dw_1[0x8]; 2163 u8 format_select_dw_gtpu_dw_2[0x8]; 2164 u8 format_select_dw_gtpu_first_ext_dw_0[0x8]; 2165 2166 u8 generate_wqe_type[0x20]; 2167 2168 u8 reserved_at_2c0[0xc0]; 2169 2170 u8 reserved_at_380[0xb]; 2171 u8 min_mkey_log_entity_size_fixed_buffer[0x5]; 2172 u8 ec_vf_vport_base[0x10]; 2173 2174 u8 reserved_at_3a0[0x2]; 2175 u8 max_mkey_log_entity_size_fixed_buffer[0x6]; 2176 u8 reserved_at_3a8[0x2]; 2177 u8 max_mkey_log_entity_size_mtt[0x6]; 2178 u8 max_rqt_vhca_id[0x10]; 2179 2180 u8 reserved_at_3c0[0x20]; 2181 2182 u8 reserved_at_3e0[0x10]; 2183 u8 pcc_ifa2[0x1]; 2184 u8 reserved_at_3f1[0xf]; 2185 2186 u8 reserved_at_400[0x1]; 2187 u8 min_mkey_log_entity_size_fixed_buffer_valid[0x1]; 2188 u8 reserved_at_402[0xe]; 2189 u8 return_reg_id[0x10]; 2190 2191 u8 reserved_at_420[0x1c]; 2192 u8 flow_table_hash_type[0x4]; 2193 2194 u8 reserved_at_440[0x8]; 2195 u8 max_num_eqs_24b[0x18]; 2196 u8 reserved_at_460[0x3a0]; 2197 }; 2198 2199 enum mlx5_ifc_flow_destination_type { 2200 MLX5_IFC_FLOW_DESTINATION_TYPE_VPORT = 0x0, 2201 MLX5_IFC_FLOW_DESTINATION_TYPE_FLOW_TABLE = 0x1, 2202 MLX5_IFC_FLOW_DESTINATION_TYPE_TIR = 0x2, 2203 MLX5_IFC_FLOW_DESTINATION_TYPE_FLOW_SAMPLER = 0x6, 2204 MLX5_IFC_FLOW_DESTINATION_TYPE_UPLINK = 0x8, 2205 MLX5_IFC_FLOW_DESTINATION_TYPE_TABLE_TYPE = 0xA, 2206 }; 2207 2208 enum mlx5_flow_table_miss_action { 2209 MLX5_FLOW_TABLE_MISS_ACTION_DEF, 2210 MLX5_FLOW_TABLE_MISS_ACTION_FWD, 2211 MLX5_FLOW_TABLE_MISS_ACTION_SWITCH_DOMAIN, 2212 }; 2213 2214 struct mlx5_ifc_dest_format_struct_bits { 2215 u8 destination_type[0x8]; 2216 u8 destination_id[0x18]; 2217 2218 u8 destination_eswitch_owner_vhca_id_valid[0x1]; 2219 u8 packet_reformat[0x1]; 2220 u8 reserved_at_22[0x6]; 2221 u8 destination_table_type[0x8]; 2222 u8 destination_eswitch_owner_vhca_id[0x10]; 2223 }; 2224 2225 struct mlx5_ifc_flow_counter_list_bits { 2226 u8 flow_counter_id[0x20]; 2227 2228 u8 reserved_at_20[0x20]; 2229 }; 2230 2231 struct mlx5_ifc_extended_dest_format_bits { 2232 struct mlx5_ifc_dest_format_struct_bits destination_entry; 2233 2234 u8 packet_reformat_id[0x20]; 2235 2236 u8 reserved_at_60[0x20]; 2237 }; 2238 2239 union mlx5_ifc_dest_format_flow_counter_list_auto_bits { 2240 struct mlx5_ifc_extended_dest_format_bits extended_dest_format; 2241 struct mlx5_ifc_flow_counter_list_bits flow_counter_list; 2242 }; 2243 2244 struct mlx5_ifc_fte_match_param_bits { 2245 struct mlx5_ifc_fte_match_set_lyr_2_4_bits outer_headers; 2246 2247 struct mlx5_ifc_fte_match_set_misc_bits misc_parameters; 2248 2249 struct mlx5_ifc_fte_match_set_lyr_2_4_bits inner_headers; 2250 2251 struct mlx5_ifc_fte_match_set_misc2_bits misc_parameters_2; 2252 2253 struct mlx5_ifc_fte_match_set_misc3_bits misc_parameters_3; 2254 2255 struct mlx5_ifc_fte_match_set_misc4_bits misc_parameters_4; 2256 2257 struct mlx5_ifc_fte_match_set_misc5_bits misc_parameters_5; 2258 2259 u8 reserved_at_e00[0x200]; 2260 }; 2261 2262 enum { 2263 MLX5_RX_HASH_FIELD_SELECT_SELECTED_FIELDS_SRC_IP = 0x0, 2264 MLX5_RX_HASH_FIELD_SELECT_SELECTED_FIELDS_DST_IP = 0x1, 2265 MLX5_RX_HASH_FIELD_SELECT_SELECTED_FIELDS_L4_SPORT = 0x2, 2266 MLX5_RX_HASH_FIELD_SELECT_SELECTED_FIELDS_L4_DPORT = 0x3, 2267 MLX5_RX_HASH_FIELD_SELECT_SELECTED_FIELDS_IPSEC_SPI = 0x4, 2268 }; 2269 2270 struct mlx5_ifc_rx_hash_field_select_bits { 2271 u8 l3_prot_type[0x1]; 2272 u8 l4_prot_type[0x1]; 2273 u8 selected_fields[0x1e]; 2274 }; 2275 2276 enum { 2277 MLX5_WQ_WQ_TYPE_WQ_LINKED_LIST = 0x0, 2278 MLX5_WQ_WQ_TYPE_WQ_CYCLIC = 0x1, 2279 }; 2280 2281 enum { 2282 MLX5_WQ_END_PADDING_MODE_END_PAD_NONE = 0x0, 2283 MLX5_WQ_END_PADDING_MODE_END_PAD_ALIGN = 0x1, 2284 }; 2285 2286 struct mlx5_ifc_wq_bits { 2287 u8 wq_type[0x4]; 2288 u8 wq_signature[0x1]; 2289 u8 end_padding_mode[0x2]; 2290 u8 cd_slave[0x1]; 2291 u8 reserved_at_8[0x18]; 2292 2293 u8 hds_skip_first_sge[0x1]; 2294 u8 log2_hds_buf_size[0x3]; 2295 u8 reserved_at_24[0x7]; 2296 u8 page_offset[0x5]; 2297 u8 lwm[0x10]; 2298 2299 u8 reserved_at_40[0x8]; 2300 u8 pd[0x18]; 2301 2302 u8 reserved_at_60[0x8]; 2303 u8 uar_page[0x18]; 2304 2305 u8 dbr_addr[0x40]; 2306 2307 u8 hw_counter[0x20]; 2308 2309 u8 sw_counter[0x20]; 2310 2311 u8 reserved_at_100[0xc]; 2312 u8 log_wq_stride[0x4]; 2313 u8 reserved_at_110[0x3]; 2314 u8 log_wq_pg_sz[0x5]; 2315 u8 reserved_at_118[0x3]; 2316 u8 log_wq_sz[0x5]; 2317 2318 u8 dbr_umem_valid[0x1]; 2319 u8 wq_umem_valid[0x1]; 2320 u8 reserved_at_122[0x1]; 2321 u8 log_hairpin_num_packets[0x5]; 2322 u8 reserved_at_128[0x3]; 2323 u8 log_hairpin_data_sz[0x5]; 2324 2325 u8 reserved_at_130[0x4]; 2326 u8 log_wqe_num_of_strides[0x4]; 2327 u8 two_byte_shift_en[0x1]; 2328 u8 reserved_at_139[0x4]; 2329 u8 log_wqe_stride_size[0x3]; 2330 2331 u8 dbr_umem_id[0x20]; 2332 u8 wq_umem_id[0x20]; 2333 2334 u8 wq_umem_offset[0x40]; 2335 2336 u8 headers_mkey[0x20]; 2337 2338 u8 shampo_enable[0x1]; 2339 u8 reserved_at_1e1[0x1]; 2340 u8 shampo_mode[0x2]; 2341 u8 reserved_at_1e4[0x1]; 2342 u8 log_reservation_size[0x3]; 2343 u8 reserved_at_1e8[0x5]; 2344 u8 log_max_num_of_packets_per_reservation[0x3]; 2345 u8 reserved_at_1f0[0x6]; 2346 u8 log_headers_entry_size[0x2]; 2347 u8 reserved_at_1f8[0x4]; 2348 u8 log_headers_buffer_entry_num[0x4]; 2349 2350 u8 reserved_at_200[0x400]; 2351 2352 struct mlx5_ifc_cmd_pas_bits pas[]; 2353 }; 2354 2355 struct mlx5_ifc_rq_num_bits { 2356 u8 reserved_at_0[0x8]; 2357 u8 rq_num[0x18]; 2358 }; 2359 2360 struct mlx5_ifc_rq_vhca_bits { 2361 u8 reserved_at_0[0x8]; 2362 u8 rq_num[0x18]; 2363 u8 reserved_at_20[0x10]; 2364 u8 rq_vhca_id[0x10]; 2365 }; 2366 2367 struct mlx5_ifc_mac_address_layout_bits { 2368 u8 reserved_at_0[0x10]; 2369 u8 mac_addr_47_32[0x10]; 2370 2371 u8 mac_addr_31_0[0x20]; 2372 }; 2373 2374 struct mlx5_ifc_vlan_layout_bits { 2375 u8 reserved_at_0[0x14]; 2376 u8 vlan[0x0c]; 2377 2378 u8 reserved_at_20[0x20]; 2379 }; 2380 2381 struct mlx5_ifc_cong_control_r_roce_ecn_np_bits { 2382 u8 reserved_at_0[0xa0]; 2383 2384 u8 min_time_between_cnps[0x20]; 2385 2386 u8 reserved_at_c0[0x12]; 2387 u8 cnp_dscp[0x6]; 2388 u8 reserved_at_d8[0x4]; 2389 u8 cnp_prio_mode[0x1]; 2390 u8 cnp_802p_prio[0x3]; 2391 2392 u8 reserved_at_e0[0x720]; 2393 }; 2394 2395 struct mlx5_ifc_cong_control_r_roce_ecn_rp_bits { 2396 u8 reserved_at_0[0x60]; 2397 2398 u8 reserved_at_60[0x4]; 2399 u8 clamp_tgt_rate[0x1]; 2400 u8 reserved_at_65[0x3]; 2401 u8 clamp_tgt_rate_after_time_inc[0x1]; 2402 u8 reserved_at_69[0x17]; 2403 2404 u8 reserved_at_80[0x20]; 2405 2406 u8 rpg_time_reset[0x20]; 2407 2408 u8 rpg_byte_reset[0x20]; 2409 2410 u8 rpg_threshold[0x20]; 2411 2412 u8 rpg_max_rate[0x20]; 2413 2414 u8 rpg_ai_rate[0x20]; 2415 2416 u8 rpg_hai_rate[0x20]; 2417 2418 u8 rpg_gd[0x20]; 2419 2420 u8 rpg_min_dec_fac[0x20]; 2421 2422 u8 rpg_min_rate[0x20]; 2423 2424 u8 reserved_at_1c0[0xe0]; 2425 2426 u8 rate_to_set_on_first_cnp[0x20]; 2427 2428 u8 dce_tcp_g[0x20]; 2429 2430 u8 dce_tcp_rtt[0x20]; 2431 2432 u8 rate_reduce_monitor_period[0x20]; 2433 2434 u8 reserved_at_320[0x20]; 2435 2436 u8 initial_alpha_value[0x20]; 2437 2438 u8 reserved_at_360[0x4a0]; 2439 }; 2440 2441 struct mlx5_ifc_cong_control_r_roce_general_bits { 2442 u8 reserved_at_0[0x80]; 2443 2444 u8 reserved_at_80[0x10]; 2445 u8 rtt_resp_dscp_valid[0x1]; 2446 u8 reserved_at_91[0x9]; 2447 u8 rtt_resp_dscp[0x6]; 2448 2449 u8 reserved_at_a0[0x760]; 2450 }; 2451 2452 struct mlx5_ifc_cong_control_802_1qau_rp_bits { 2453 u8 reserved_at_0[0x80]; 2454 2455 u8 rppp_max_rps[0x20]; 2456 2457 u8 rpg_time_reset[0x20]; 2458 2459 u8 rpg_byte_reset[0x20]; 2460 2461 u8 rpg_threshold[0x20]; 2462 2463 u8 rpg_max_rate[0x20]; 2464 2465 u8 rpg_ai_rate[0x20]; 2466 2467 u8 rpg_hai_rate[0x20]; 2468 2469 u8 rpg_gd[0x20]; 2470 2471 u8 rpg_min_dec_fac[0x20]; 2472 2473 u8 rpg_min_rate[0x20]; 2474 2475 u8 reserved_at_1c0[0x640]; 2476 }; 2477 2478 enum { 2479 MLX5_RESIZE_FIELD_SELECT_RESIZE_FIELD_SELECT_LOG_CQ_SIZE = 0x1, 2480 MLX5_RESIZE_FIELD_SELECT_RESIZE_FIELD_SELECT_PAGE_OFFSET = 0x2, 2481 MLX5_RESIZE_FIELD_SELECT_RESIZE_FIELD_SELECT_LOG_PAGE_SIZE = 0x4, 2482 }; 2483 2484 struct mlx5_ifc_resize_field_select_bits { 2485 u8 resize_field_select[0x20]; 2486 }; 2487 2488 struct mlx5_ifc_resource_dump_bits { 2489 u8 more_dump[0x1]; 2490 u8 inline_dump[0x1]; 2491 u8 reserved_at_2[0xa]; 2492 u8 seq_num[0x4]; 2493 u8 segment_type[0x10]; 2494 2495 u8 reserved_at_20[0x10]; 2496 u8 vhca_id[0x10]; 2497 2498 u8 index1[0x20]; 2499 2500 u8 index2[0x20]; 2501 2502 u8 num_of_obj1[0x10]; 2503 u8 num_of_obj2[0x10]; 2504 2505 u8 reserved_at_a0[0x20]; 2506 2507 u8 device_opaque[0x40]; 2508 2509 u8 mkey[0x20]; 2510 2511 u8 size[0x20]; 2512 2513 u8 address[0x40]; 2514 2515 u8 inline_data[52][0x20]; 2516 }; 2517 2518 struct mlx5_ifc_resource_dump_menu_record_bits { 2519 u8 reserved_at_0[0x4]; 2520 u8 num_of_obj2_supports_active[0x1]; 2521 u8 num_of_obj2_supports_all[0x1]; 2522 u8 must_have_num_of_obj2[0x1]; 2523 u8 support_num_of_obj2[0x1]; 2524 u8 num_of_obj1_supports_active[0x1]; 2525 u8 num_of_obj1_supports_all[0x1]; 2526 u8 must_have_num_of_obj1[0x1]; 2527 u8 support_num_of_obj1[0x1]; 2528 u8 must_have_index2[0x1]; 2529 u8 support_index2[0x1]; 2530 u8 must_have_index1[0x1]; 2531 u8 support_index1[0x1]; 2532 u8 segment_type[0x10]; 2533 2534 u8 segment_name[4][0x20]; 2535 2536 u8 index1_name[4][0x20]; 2537 2538 u8 index2_name[4][0x20]; 2539 }; 2540 2541 struct mlx5_ifc_resource_dump_segment_header_bits { 2542 u8 length_dw[0x10]; 2543 u8 segment_type[0x10]; 2544 }; 2545 2546 struct mlx5_ifc_resource_dump_command_segment_bits { 2547 struct mlx5_ifc_resource_dump_segment_header_bits segment_header; 2548 2549 u8 segment_called[0x10]; 2550 u8 vhca_id[0x10]; 2551 2552 u8 index1[0x20]; 2553 2554 u8 index2[0x20]; 2555 2556 u8 num_of_obj1[0x10]; 2557 u8 num_of_obj2[0x10]; 2558 }; 2559 2560 struct mlx5_ifc_resource_dump_error_segment_bits { 2561 struct mlx5_ifc_resource_dump_segment_header_bits segment_header; 2562 2563 u8 reserved_at_20[0x10]; 2564 u8 syndrome_id[0x10]; 2565 2566 u8 reserved_at_40[0x40]; 2567 2568 u8 error[8][0x20]; 2569 }; 2570 2571 struct mlx5_ifc_resource_dump_info_segment_bits { 2572 struct mlx5_ifc_resource_dump_segment_header_bits segment_header; 2573 2574 u8 reserved_at_20[0x18]; 2575 u8 dump_version[0x8]; 2576 2577 u8 hw_version[0x20]; 2578 2579 u8 fw_version[0x20]; 2580 }; 2581 2582 struct mlx5_ifc_resource_dump_menu_segment_bits { 2583 struct mlx5_ifc_resource_dump_segment_header_bits segment_header; 2584 2585 u8 reserved_at_20[0x10]; 2586 u8 num_of_records[0x10]; 2587 2588 struct mlx5_ifc_resource_dump_menu_record_bits record[]; 2589 }; 2590 2591 struct mlx5_ifc_resource_dump_resource_segment_bits { 2592 struct mlx5_ifc_resource_dump_segment_header_bits segment_header; 2593 2594 u8 reserved_at_20[0x20]; 2595 2596 u8 index1[0x20]; 2597 2598 u8 index2[0x20]; 2599 2600 u8 payload[][0x20]; 2601 }; 2602 2603 struct mlx5_ifc_resource_dump_terminate_segment_bits { 2604 struct mlx5_ifc_resource_dump_segment_header_bits segment_header; 2605 }; 2606 2607 struct mlx5_ifc_menu_resource_dump_response_bits { 2608 struct mlx5_ifc_resource_dump_info_segment_bits info; 2609 struct mlx5_ifc_resource_dump_command_segment_bits cmd; 2610 struct mlx5_ifc_resource_dump_menu_segment_bits menu; 2611 struct mlx5_ifc_resource_dump_terminate_segment_bits terminate; 2612 }; 2613 2614 enum { 2615 MLX5_MODIFY_FIELD_SELECT_MODIFY_FIELD_SELECT_CQ_PERIOD = 0x1, 2616 MLX5_MODIFY_FIELD_SELECT_MODIFY_FIELD_SELECT_CQ_MAX_COUNT = 0x2, 2617 MLX5_MODIFY_FIELD_SELECT_MODIFY_FIELD_SELECT_OI = 0x4, 2618 MLX5_MODIFY_FIELD_SELECT_MODIFY_FIELD_SELECT_C_EQN = 0x8, 2619 }; 2620 2621 struct mlx5_ifc_modify_field_select_bits { 2622 u8 modify_field_select[0x20]; 2623 }; 2624 2625 struct mlx5_ifc_field_select_r_roce_np_bits { 2626 u8 field_select_r_roce_np[0x20]; 2627 }; 2628 2629 struct mlx5_ifc_field_select_r_roce_rp_bits { 2630 u8 field_select_r_roce_rp[0x20]; 2631 }; 2632 2633 enum { 2634 MLX5_FIELD_SELECT_802_1QAU_RP_FIELD_SELECT_8021QAURP_RPPP_MAX_RPS = 0x4, 2635 MLX5_FIELD_SELECT_802_1QAU_RP_FIELD_SELECT_8021QAURP_RPG_TIME_RESET = 0x8, 2636 MLX5_FIELD_SELECT_802_1QAU_RP_FIELD_SELECT_8021QAURP_RPG_BYTE_RESET = 0x10, 2637 MLX5_FIELD_SELECT_802_1QAU_RP_FIELD_SELECT_8021QAURP_RPG_THRESHOLD = 0x20, 2638 MLX5_FIELD_SELECT_802_1QAU_RP_FIELD_SELECT_8021QAURP_RPG_MAX_RATE = 0x40, 2639 MLX5_FIELD_SELECT_802_1QAU_RP_FIELD_SELECT_8021QAURP_RPG_AI_RATE = 0x80, 2640 MLX5_FIELD_SELECT_802_1QAU_RP_FIELD_SELECT_8021QAURP_RPG_HAI_RATE = 0x100, 2641 MLX5_FIELD_SELECT_802_1QAU_RP_FIELD_SELECT_8021QAURP_RPG_GD = 0x200, 2642 MLX5_FIELD_SELECT_802_1QAU_RP_FIELD_SELECT_8021QAURP_RPG_MIN_DEC_FAC = 0x400, 2643 MLX5_FIELD_SELECT_802_1QAU_RP_FIELD_SELECT_8021QAURP_RPG_MIN_RATE = 0x800, 2644 }; 2645 2646 struct mlx5_ifc_field_select_802_1qau_rp_bits { 2647 u8 field_select_8021qaurp[0x20]; 2648 }; 2649 2650 struct mlx5_ifc_phys_layer_recovery_cntrs_bits { 2651 u8 total_successful_recovery_events[0x20]; 2652 2653 u8 reserved_at_20[0x7a0]; 2654 }; 2655 2656 struct mlx5_ifc_phys_layer_cntrs_bits { 2657 u8 time_since_last_clear_high[0x20]; 2658 2659 u8 time_since_last_clear_low[0x20]; 2660 2661 u8 symbol_errors_high[0x20]; 2662 2663 u8 symbol_errors_low[0x20]; 2664 2665 u8 sync_headers_errors_high[0x20]; 2666 2667 u8 sync_headers_errors_low[0x20]; 2668 2669 u8 edpl_bip_errors_lane0_high[0x20]; 2670 2671 u8 edpl_bip_errors_lane0_low[0x20]; 2672 2673 u8 edpl_bip_errors_lane1_high[0x20]; 2674 2675 u8 edpl_bip_errors_lane1_low[0x20]; 2676 2677 u8 edpl_bip_errors_lane2_high[0x20]; 2678 2679 u8 edpl_bip_errors_lane2_low[0x20]; 2680 2681 u8 edpl_bip_errors_lane3_high[0x20]; 2682 2683 u8 edpl_bip_errors_lane3_low[0x20]; 2684 2685 u8 fc_fec_corrected_blocks_lane0_high[0x20]; 2686 2687 u8 fc_fec_corrected_blocks_lane0_low[0x20]; 2688 2689 u8 fc_fec_corrected_blocks_lane1_high[0x20]; 2690 2691 u8 fc_fec_corrected_blocks_lane1_low[0x20]; 2692 2693 u8 fc_fec_corrected_blocks_lane2_high[0x20]; 2694 2695 u8 fc_fec_corrected_blocks_lane2_low[0x20]; 2696 2697 u8 fc_fec_corrected_blocks_lane3_high[0x20]; 2698 2699 u8 fc_fec_corrected_blocks_lane3_low[0x20]; 2700 2701 u8 fc_fec_uncorrectable_blocks_lane0_high[0x20]; 2702 2703 u8 fc_fec_uncorrectable_blocks_lane0_low[0x20]; 2704 2705 u8 fc_fec_uncorrectable_blocks_lane1_high[0x20]; 2706 2707 u8 fc_fec_uncorrectable_blocks_lane1_low[0x20]; 2708 2709 u8 fc_fec_uncorrectable_blocks_lane2_high[0x20]; 2710 2711 u8 fc_fec_uncorrectable_blocks_lane2_low[0x20]; 2712 2713 u8 fc_fec_uncorrectable_blocks_lane3_high[0x20]; 2714 2715 u8 fc_fec_uncorrectable_blocks_lane3_low[0x20]; 2716 2717 u8 rs_fec_corrected_blocks_high[0x20]; 2718 2719 u8 rs_fec_corrected_blocks_low[0x20]; 2720 2721 u8 rs_fec_uncorrectable_blocks_high[0x20]; 2722 2723 u8 rs_fec_uncorrectable_blocks_low[0x20]; 2724 2725 u8 rs_fec_no_errors_blocks_high[0x20]; 2726 2727 u8 rs_fec_no_errors_blocks_low[0x20]; 2728 2729 u8 rs_fec_single_error_blocks_high[0x20]; 2730 2731 u8 rs_fec_single_error_blocks_low[0x20]; 2732 2733 u8 rs_fec_corrected_symbols_total_high[0x20]; 2734 2735 u8 rs_fec_corrected_symbols_total_low[0x20]; 2736 2737 u8 rs_fec_corrected_symbols_lane0_high[0x20]; 2738 2739 u8 rs_fec_corrected_symbols_lane0_low[0x20]; 2740 2741 u8 rs_fec_corrected_symbols_lane1_high[0x20]; 2742 2743 u8 rs_fec_corrected_symbols_lane1_low[0x20]; 2744 2745 u8 rs_fec_corrected_symbols_lane2_high[0x20]; 2746 2747 u8 rs_fec_corrected_symbols_lane2_low[0x20]; 2748 2749 u8 rs_fec_corrected_symbols_lane3_high[0x20]; 2750 2751 u8 rs_fec_corrected_symbols_lane3_low[0x20]; 2752 2753 u8 link_down_events[0x20]; 2754 2755 u8 successful_recovery_events[0x20]; 2756 2757 u8 reserved_at_640[0x180]; 2758 }; 2759 2760 struct mlx5_ifc_phys_layer_statistical_cntrs_bits { 2761 u8 time_since_last_clear_high[0x20]; 2762 2763 u8 time_since_last_clear_low[0x20]; 2764 2765 u8 phy_received_bits_high[0x20]; 2766 2767 u8 phy_received_bits_low[0x20]; 2768 2769 u8 phy_symbol_errors_high[0x20]; 2770 2771 u8 phy_symbol_errors_low[0x20]; 2772 2773 u8 phy_corrected_bits_high[0x20]; 2774 2775 u8 phy_corrected_bits_low[0x20]; 2776 2777 u8 phy_corrected_bits_lane0_high[0x20]; 2778 2779 u8 phy_corrected_bits_lane0_low[0x20]; 2780 2781 u8 phy_corrected_bits_lane1_high[0x20]; 2782 2783 u8 phy_corrected_bits_lane1_low[0x20]; 2784 2785 u8 phy_corrected_bits_lane2_high[0x20]; 2786 2787 u8 phy_corrected_bits_lane2_low[0x20]; 2788 2789 u8 phy_corrected_bits_lane3_high[0x20]; 2790 2791 u8 phy_corrected_bits_lane3_low[0x20]; 2792 2793 u8 reserved_at_200[0x5c0]; 2794 }; 2795 2796 struct mlx5_ifc_ib_port_cntrs_grp_data_layout_bits { 2797 u8 symbol_error_counter[0x10]; 2798 2799 u8 link_error_recovery_counter[0x8]; 2800 2801 u8 link_downed_counter[0x8]; 2802 2803 u8 port_rcv_errors[0x10]; 2804 2805 u8 port_rcv_remote_physical_errors[0x10]; 2806 2807 u8 port_rcv_switch_relay_errors[0x10]; 2808 2809 u8 port_xmit_discards[0x10]; 2810 2811 u8 port_xmit_constraint_errors[0x8]; 2812 2813 u8 port_rcv_constraint_errors[0x8]; 2814 2815 u8 reserved_at_70[0x8]; 2816 2817 u8 link_overrun_errors[0x8]; 2818 2819 u8 reserved_at_80[0x10]; 2820 2821 u8 vl_15_dropped[0x10]; 2822 2823 u8 reserved_at_a0[0x80]; 2824 2825 u8 port_xmit_wait[0x20]; 2826 }; 2827 2828 struct mlx5_ifc_ib_ext_port_cntrs_grp_data_layout_bits { 2829 u8 reserved_at_0[0x300]; 2830 2831 u8 port_xmit_data_high[0x20]; 2832 2833 u8 port_xmit_data_low[0x20]; 2834 2835 u8 port_rcv_data_high[0x20]; 2836 2837 u8 port_rcv_data_low[0x20]; 2838 2839 u8 port_xmit_pkts_high[0x20]; 2840 2841 u8 port_xmit_pkts_low[0x20]; 2842 2843 u8 port_rcv_pkts_high[0x20]; 2844 2845 u8 port_rcv_pkts_low[0x20]; 2846 2847 u8 reserved_at_400[0x80]; 2848 2849 u8 port_unicast_xmit_pkts_high[0x20]; 2850 2851 u8 port_unicast_xmit_pkts_low[0x20]; 2852 2853 u8 port_multicast_xmit_pkts_high[0x20]; 2854 2855 u8 port_multicast_xmit_pkts_low[0x20]; 2856 2857 u8 port_unicast_rcv_pkts_high[0x20]; 2858 2859 u8 port_unicast_rcv_pkts_low[0x20]; 2860 2861 u8 port_multicast_rcv_pkts_high[0x20]; 2862 2863 u8 port_multicast_rcv_pkts_low[0x20]; 2864 2865 u8 reserved_at_580[0x240]; 2866 }; 2867 2868 struct mlx5_ifc_eth_per_tc_prio_grp_data_layout_bits { 2869 u8 transmit_queue_high[0x20]; 2870 2871 u8 transmit_queue_low[0x20]; 2872 2873 u8 no_buffer_discard_uc_high[0x20]; 2874 2875 u8 no_buffer_discard_uc_low[0x20]; 2876 2877 u8 reserved_at_80[0x740]; 2878 }; 2879 2880 struct mlx5_ifc_eth_per_tc_congest_prio_grp_data_layout_bits { 2881 u8 wred_discard_high[0x20]; 2882 2883 u8 wred_discard_low[0x20]; 2884 2885 u8 ecn_marked_tc_high[0x20]; 2886 2887 u8 ecn_marked_tc_low[0x20]; 2888 2889 u8 reserved_at_80[0x740]; 2890 }; 2891 2892 struct mlx5_ifc_eth_per_prio_grp_data_layout_bits { 2893 u8 rx_octets_high[0x20]; 2894 2895 u8 rx_octets_low[0x20]; 2896 2897 u8 reserved_at_40[0xc0]; 2898 2899 u8 rx_frames_high[0x20]; 2900 2901 u8 rx_frames_low[0x20]; 2902 2903 u8 tx_octets_high[0x20]; 2904 2905 u8 tx_octets_low[0x20]; 2906 2907 u8 reserved_at_180[0xc0]; 2908 2909 u8 tx_frames_high[0x20]; 2910 2911 u8 tx_frames_low[0x20]; 2912 2913 u8 rx_pause_high[0x20]; 2914 2915 u8 rx_pause_low[0x20]; 2916 2917 u8 rx_pause_duration_high[0x20]; 2918 2919 u8 rx_pause_duration_low[0x20]; 2920 2921 u8 tx_pause_high[0x20]; 2922 2923 u8 tx_pause_low[0x20]; 2924 2925 u8 tx_pause_duration_high[0x20]; 2926 2927 u8 tx_pause_duration_low[0x20]; 2928 2929 u8 rx_pause_transition_high[0x20]; 2930 2931 u8 rx_pause_transition_low[0x20]; 2932 2933 u8 rx_discards_high[0x20]; 2934 2935 u8 rx_discards_low[0x20]; 2936 2937 u8 device_stall_minor_watermark_cnt_high[0x20]; 2938 2939 u8 device_stall_minor_watermark_cnt_low[0x20]; 2940 2941 u8 device_stall_critical_watermark_cnt_high[0x20]; 2942 2943 u8 device_stall_critical_watermark_cnt_low[0x20]; 2944 2945 u8 reserved_at_480[0x340]; 2946 }; 2947 2948 struct mlx5_ifc_eth_extended_cntrs_grp_data_layout_bits { 2949 u8 port_transmit_wait_high[0x20]; 2950 2951 u8 port_transmit_wait_low[0x20]; 2952 2953 u8 reserved_at_40[0x100]; 2954 2955 u8 rx_buffer_almost_full_high[0x20]; 2956 2957 u8 rx_buffer_almost_full_low[0x20]; 2958 2959 u8 rx_buffer_full_high[0x20]; 2960 2961 u8 rx_buffer_full_low[0x20]; 2962 2963 u8 rx_icrc_encapsulated_high[0x20]; 2964 2965 u8 rx_icrc_encapsulated_low[0x20]; 2966 2967 u8 reserved_at_200[0x5c0]; 2968 }; 2969 2970 struct mlx5_ifc_eth_3635_cntrs_grp_data_layout_bits { 2971 u8 dot3stats_alignment_errors_high[0x20]; 2972 2973 u8 dot3stats_alignment_errors_low[0x20]; 2974 2975 u8 dot3stats_fcs_errors_high[0x20]; 2976 2977 u8 dot3stats_fcs_errors_low[0x20]; 2978 2979 u8 dot3stats_single_collision_frames_high[0x20]; 2980 2981 u8 dot3stats_single_collision_frames_low[0x20]; 2982 2983 u8 dot3stats_multiple_collision_frames_high[0x20]; 2984 2985 u8 dot3stats_multiple_collision_frames_low[0x20]; 2986 2987 u8 dot3stats_sqe_test_errors_high[0x20]; 2988 2989 u8 dot3stats_sqe_test_errors_low[0x20]; 2990 2991 u8 dot3stats_deferred_transmissions_high[0x20]; 2992 2993 u8 dot3stats_deferred_transmissions_low[0x20]; 2994 2995 u8 dot3stats_late_collisions_high[0x20]; 2996 2997 u8 dot3stats_late_collisions_low[0x20]; 2998 2999 u8 dot3stats_excessive_collisions_high[0x20]; 3000 3001 u8 dot3stats_excessive_collisions_low[0x20]; 3002 3003 u8 dot3stats_internal_mac_transmit_errors_high[0x20]; 3004 3005 u8 dot3stats_internal_mac_transmit_errors_low[0x20]; 3006 3007 u8 dot3stats_carrier_sense_errors_high[0x20]; 3008 3009 u8 dot3stats_carrier_sense_errors_low[0x20]; 3010 3011 u8 dot3stats_frame_too_longs_high[0x20]; 3012 3013 u8 dot3stats_frame_too_longs_low[0x20]; 3014 3015 u8 dot3stats_internal_mac_receive_errors_high[0x20]; 3016 3017 u8 dot3stats_internal_mac_receive_errors_low[0x20]; 3018 3019 u8 dot3stats_symbol_errors_high[0x20]; 3020 3021 u8 dot3stats_symbol_errors_low[0x20]; 3022 3023 u8 dot3control_in_unknown_opcodes_high[0x20]; 3024 3025 u8 dot3control_in_unknown_opcodes_low[0x20]; 3026 3027 u8 dot3in_pause_frames_high[0x20]; 3028 3029 u8 dot3in_pause_frames_low[0x20]; 3030 3031 u8 dot3out_pause_frames_high[0x20]; 3032 3033 u8 dot3out_pause_frames_low[0x20]; 3034 3035 u8 reserved_at_400[0x3c0]; 3036 }; 3037 3038 struct mlx5_ifc_eth_2819_cntrs_grp_data_layout_bits { 3039 u8 ether_stats_drop_events_high[0x20]; 3040 3041 u8 ether_stats_drop_events_low[0x20]; 3042 3043 u8 ether_stats_octets_high[0x20]; 3044 3045 u8 ether_stats_octets_low[0x20]; 3046 3047 u8 ether_stats_pkts_high[0x20]; 3048 3049 u8 ether_stats_pkts_low[0x20]; 3050 3051 u8 ether_stats_broadcast_pkts_high[0x20]; 3052 3053 u8 ether_stats_broadcast_pkts_low[0x20]; 3054 3055 u8 ether_stats_multicast_pkts_high[0x20]; 3056 3057 u8 ether_stats_multicast_pkts_low[0x20]; 3058 3059 u8 ether_stats_crc_align_errors_high[0x20]; 3060 3061 u8 ether_stats_crc_align_errors_low[0x20]; 3062 3063 u8 ether_stats_undersize_pkts_high[0x20]; 3064 3065 u8 ether_stats_undersize_pkts_low[0x20]; 3066 3067 u8 ether_stats_oversize_pkts_high[0x20]; 3068 3069 u8 ether_stats_oversize_pkts_low[0x20]; 3070 3071 u8 ether_stats_fragments_high[0x20]; 3072 3073 u8 ether_stats_fragments_low[0x20]; 3074 3075 u8 ether_stats_jabbers_high[0x20]; 3076 3077 u8 ether_stats_jabbers_low[0x20]; 3078 3079 u8 ether_stats_collisions_high[0x20]; 3080 3081 u8 ether_stats_collisions_low[0x20]; 3082 3083 u8 ether_stats_pkts64octets_high[0x20]; 3084 3085 u8 ether_stats_pkts64octets_low[0x20]; 3086 3087 u8 ether_stats_pkts65to127octets_high[0x20]; 3088 3089 u8 ether_stats_pkts65to127octets_low[0x20]; 3090 3091 u8 ether_stats_pkts128to255octets_high[0x20]; 3092 3093 u8 ether_stats_pkts128to255octets_low[0x20]; 3094 3095 u8 ether_stats_pkts256to511octets_high[0x20]; 3096 3097 u8 ether_stats_pkts256to511octets_low[0x20]; 3098 3099 u8 ether_stats_pkts512to1023octets_high[0x20]; 3100 3101 u8 ether_stats_pkts512to1023octets_low[0x20]; 3102 3103 u8 ether_stats_pkts1024to1518octets_high[0x20]; 3104 3105 u8 ether_stats_pkts1024to1518octets_low[0x20]; 3106 3107 u8 ether_stats_pkts1519to2047octets_high[0x20]; 3108 3109 u8 ether_stats_pkts1519to2047octets_low[0x20]; 3110 3111 u8 ether_stats_pkts2048to4095octets_high[0x20]; 3112 3113 u8 ether_stats_pkts2048to4095octets_low[0x20]; 3114 3115 u8 ether_stats_pkts4096to8191octets_high[0x20]; 3116 3117 u8 ether_stats_pkts4096to8191octets_low[0x20]; 3118 3119 u8 ether_stats_pkts8192to10239octets_high[0x20]; 3120 3121 u8 ether_stats_pkts8192to10239octets_low[0x20]; 3122 3123 u8 reserved_at_540[0x280]; 3124 }; 3125 3126 struct mlx5_ifc_eth_2863_cntrs_grp_data_layout_bits { 3127 u8 if_in_octets_high[0x20]; 3128 3129 u8 if_in_octets_low[0x20]; 3130 3131 u8 if_in_ucast_pkts_high[0x20]; 3132 3133 u8 if_in_ucast_pkts_low[0x20]; 3134 3135 u8 if_in_discards_high[0x20]; 3136 3137 u8 if_in_discards_low[0x20]; 3138 3139 u8 if_in_errors_high[0x20]; 3140 3141 u8 if_in_errors_low[0x20]; 3142 3143 u8 if_in_unknown_protos_high[0x20]; 3144 3145 u8 if_in_unknown_protos_low[0x20]; 3146 3147 u8 if_out_octets_high[0x20]; 3148 3149 u8 if_out_octets_low[0x20]; 3150 3151 u8 if_out_ucast_pkts_high[0x20]; 3152 3153 u8 if_out_ucast_pkts_low[0x20]; 3154 3155 u8 if_out_discards_high[0x20]; 3156 3157 u8 if_out_discards_low[0x20]; 3158 3159 u8 if_out_errors_high[0x20]; 3160 3161 u8 if_out_errors_low[0x20]; 3162 3163 u8 if_in_multicast_pkts_high[0x20]; 3164 3165 u8 if_in_multicast_pkts_low[0x20]; 3166 3167 u8 if_in_broadcast_pkts_high[0x20]; 3168 3169 u8 if_in_broadcast_pkts_low[0x20]; 3170 3171 u8 if_out_multicast_pkts_high[0x20]; 3172 3173 u8 if_out_multicast_pkts_low[0x20]; 3174 3175 u8 if_out_broadcast_pkts_high[0x20]; 3176 3177 u8 if_out_broadcast_pkts_low[0x20]; 3178 3179 u8 reserved_at_340[0x480]; 3180 }; 3181 3182 struct mlx5_ifc_eth_802_3_cntrs_grp_data_layout_bits { 3183 u8 a_frames_transmitted_ok_high[0x20]; 3184 3185 u8 a_frames_transmitted_ok_low[0x20]; 3186 3187 u8 a_frames_received_ok_high[0x20]; 3188 3189 u8 a_frames_received_ok_low[0x20]; 3190 3191 u8 a_frame_check_sequence_errors_high[0x20]; 3192 3193 u8 a_frame_check_sequence_errors_low[0x20]; 3194 3195 u8 a_alignment_errors_high[0x20]; 3196 3197 u8 a_alignment_errors_low[0x20]; 3198 3199 u8 a_octets_transmitted_ok_high[0x20]; 3200 3201 u8 a_octets_transmitted_ok_low[0x20]; 3202 3203 u8 a_octets_received_ok_high[0x20]; 3204 3205 u8 a_octets_received_ok_low[0x20]; 3206 3207 u8 a_multicast_frames_xmitted_ok_high[0x20]; 3208 3209 u8 a_multicast_frames_xmitted_ok_low[0x20]; 3210 3211 u8 a_broadcast_frames_xmitted_ok_high[0x20]; 3212 3213 u8 a_broadcast_frames_xmitted_ok_low[0x20]; 3214 3215 u8 a_multicast_frames_received_ok_high[0x20]; 3216 3217 u8 a_multicast_frames_received_ok_low[0x20]; 3218 3219 u8 a_broadcast_frames_received_ok_high[0x20]; 3220 3221 u8 a_broadcast_frames_received_ok_low[0x20]; 3222 3223 u8 a_in_range_length_errors_high[0x20]; 3224 3225 u8 a_in_range_length_errors_low[0x20]; 3226 3227 u8 a_out_of_range_length_field_high[0x20]; 3228 3229 u8 a_out_of_range_length_field_low[0x20]; 3230 3231 u8 a_frame_too_long_errors_high[0x20]; 3232 3233 u8 a_frame_too_long_errors_low[0x20]; 3234 3235 u8 a_symbol_error_during_carrier_high[0x20]; 3236 3237 u8 a_symbol_error_during_carrier_low[0x20]; 3238 3239 u8 a_mac_control_frames_transmitted_high[0x20]; 3240 3241 u8 a_mac_control_frames_transmitted_low[0x20]; 3242 3243 u8 a_mac_control_frames_received_high[0x20]; 3244 3245 u8 a_mac_control_frames_received_low[0x20]; 3246 3247 u8 a_unsupported_opcodes_received_high[0x20]; 3248 3249 u8 a_unsupported_opcodes_received_low[0x20]; 3250 3251 u8 a_pause_mac_ctrl_frames_received_high[0x20]; 3252 3253 u8 a_pause_mac_ctrl_frames_received_low[0x20]; 3254 3255 u8 a_pause_mac_ctrl_frames_transmitted_high[0x20]; 3256 3257 u8 a_pause_mac_ctrl_frames_transmitted_low[0x20]; 3258 3259 u8 reserved_at_4c0[0x300]; 3260 }; 3261 3262 struct mlx5_ifc_pcie_perf_cntrs_grp_data_layout_bits { 3263 u8 life_time_counter_high[0x20]; 3264 3265 u8 life_time_counter_low[0x20]; 3266 3267 u8 rx_errors[0x20]; 3268 3269 u8 tx_errors[0x20]; 3270 3271 u8 l0_to_recovery_eieos[0x20]; 3272 3273 u8 l0_to_recovery_ts[0x20]; 3274 3275 u8 l0_to_recovery_framing[0x20]; 3276 3277 u8 l0_to_recovery_retrain[0x20]; 3278 3279 u8 crc_error_dllp[0x20]; 3280 3281 u8 crc_error_tlp[0x20]; 3282 3283 u8 tx_overflow_buffer_pkt_high[0x20]; 3284 3285 u8 tx_overflow_buffer_pkt_low[0x20]; 3286 3287 u8 outbound_stalled_reads[0x20]; 3288 3289 u8 outbound_stalled_writes[0x20]; 3290 3291 u8 outbound_stalled_reads_events[0x20]; 3292 3293 u8 outbound_stalled_writes_events[0x20]; 3294 3295 u8 reserved_at_200[0x5c0]; 3296 }; 3297 3298 struct mlx5_ifc_cmd_inter_comp_event_bits { 3299 u8 command_completion_vector[0x20]; 3300 3301 u8 reserved_at_20[0xc0]; 3302 }; 3303 3304 struct mlx5_ifc_stall_vl_event_bits { 3305 u8 reserved_at_0[0x18]; 3306 u8 port_num[0x1]; 3307 u8 reserved_at_19[0x3]; 3308 u8 vl[0x4]; 3309 3310 u8 reserved_at_20[0xa0]; 3311 }; 3312 3313 struct mlx5_ifc_db_bf_congestion_event_bits { 3314 u8 event_subtype[0x8]; 3315 u8 reserved_at_8[0x8]; 3316 u8 congestion_level[0x8]; 3317 u8 reserved_at_18[0x8]; 3318 3319 u8 reserved_at_20[0xa0]; 3320 }; 3321 3322 struct mlx5_ifc_gpio_event_bits { 3323 u8 reserved_at_0[0x60]; 3324 3325 u8 gpio_event_hi[0x20]; 3326 3327 u8 gpio_event_lo[0x20]; 3328 3329 u8 reserved_at_a0[0x40]; 3330 }; 3331 3332 struct mlx5_ifc_port_state_change_event_bits { 3333 u8 reserved_at_0[0x40]; 3334 3335 u8 port_num[0x4]; 3336 u8 reserved_at_44[0x1c]; 3337 3338 u8 reserved_at_60[0x80]; 3339 }; 3340 3341 struct mlx5_ifc_dropped_packet_logged_bits { 3342 u8 reserved_at_0[0xe0]; 3343 }; 3344 3345 struct mlx5_ifc_nic_cap_reg_bits { 3346 u8 reserved_at_0[0x1a]; 3347 u8 vhca_icm_ctrl[0x1]; 3348 u8 reserved_at_1b[0x5]; 3349 3350 u8 reserved_at_20[0x60]; 3351 }; 3352 3353 struct mlx5_ifc_default_timeout_bits { 3354 u8 to_multiplier[0x3]; 3355 u8 reserved_at_3[0x9]; 3356 u8 to_value[0x14]; 3357 }; 3358 3359 struct mlx5_ifc_dtor_reg_bits { 3360 u8 reserved_at_0[0x20]; 3361 3362 struct mlx5_ifc_default_timeout_bits pcie_toggle_to; 3363 3364 u8 reserved_at_40[0x60]; 3365 3366 struct mlx5_ifc_default_timeout_bits health_poll_to; 3367 3368 struct mlx5_ifc_default_timeout_bits full_crdump_to; 3369 3370 struct mlx5_ifc_default_timeout_bits fw_reset_to; 3371 3372 struct mlx5_ifc_default_timeout_bits flush_on_err_to; 3373 3374 struct mlx5_ifc_default_timeout_bits pci_sync_update_to; 3375 3376 struct mlx5_ifc_default_timeout_bits tear_down_to; 3377 3378 struct mlx5_ifc_default_timeout_bits fsm_reactivate_to; 3379 3380 struct mlx5_ifc_default_timeout_bits reclaim_pages_to; 3381 3382 struct mlx5_ifc_default_timeout_bits reclaim_vfs_pages_to; 3383 3384 struct mlx5_ifc_default_timeout_bits reset_unload_to; 3385 3386 u8 reserved_at_1c0[0x20]; 3387 }; 3388 3389 struct mlx5_ifc_vhca_icm_ctrl_reg_bits { 3390 u8 vhca_id_valid[0x1]; 3391 u8 reserved_at_1[0xf]; 3392 u8 vhca_id[0x10]; 3393 3394 u8 reserved_at_20[0xa0]; 3395 3396 u8 cur_alloc_icm[0x20]; 3397 3398 u8 reserved_at_e0[0x120]; 3399 }; 3400 3401 enum { 3402 MLX5_CQ_ERROR_SYNDROME_CQ_OVERRUN = 0x1, 3403 MLX5_CQ_ERROR_SYNDROME_CQ_ACCESS_VIOLATION_ERROR = 0x2, 3404 }; 3405 3406 struct mlx5_ifc_cq_error_bits { 3407 u8 reserved_at_0[0x8]; 3408 u8 cqn[0x18]; 3409 3410 u8 reserved_at_20[0x20]; 3411 3412 u8 reserved_at_40[0x18]; 3413 u8 syndrome[0x8]; 3414 3415 u8 reserved_at_60[0x80]; 3416 }; 3417 3418 struct mlx5_ifc_rdma_page_fault_event_bits { 3419 u8 bytes_committed[0x20]; 3420 3421 u8 r_key[0x20]; 3422 3423 u8 reserved_at_40[0x10]; 3424 u8 packet_len[0x10]; 3425 3426 u8 rdma_op_len[0x20]; 3427 3428 u8 rdma_va[0x40]; 3429 3430 u8 reserved_at_c0[0x5]; 3431 u8 rdma[0x1]; 3432 u8 write[0x1]; 3433 u8 requestor[0x1]; 3434 u8 qp_number[0x18]; 3435 }; 3436 3437 struct mlx5_ifc_wqe_associated_page_fault_event_bits { 3438 u8 bytes_committed[0x20]; 3439 3440 u8 reserved_at_20[0x10]; 3441 u8 wqe_index[0x10]; 3442 3443 u8 reserved_at_40[0x10]; 3444 u8 len[0x10]; 3445 3446 u8 reserved_at_60[0x60]; 3447 3448 u8 reserved_at_c0[0x5]; 3449 u8 rdma[0x1]; 3450 u8 write_read[0x1]; 3451 u8 requestor[0x1]; 3452 u8 qpn[0x18]; 3453 }; 3454 3455 struct mlx5_ifc_qp_events_bits { 3456 u8 reserved_at_0[0xa0]; 3457 3458 u8 type[0x8]; 3459 u8 reserved_at_a8[0x18]; 3460 3461 u8 reserved_at_c0[0x8]; 3462 u8 qpn_rqn_sqn[0x18]; 3463 }; 3464 3465 struct mlx5_ifc_dct_events_bits { 3466 u8 reserved_at_0[0xc0]; 3467 3468 u8 reserved_at_c0[0x8]; 3469 u8 dct_number[0x18]; 3470 }; 3471 3472 struct mlx5_ifc_comp_event_bits { 3473 u8 reserved_at_0[0xc0]; 3474 3475 u8 reserved_at_c0[0x8]; 3476 u8 cq_number[0x18]; 3477 }; 3478 3479 enum { 3480 MLX5_QPC_STATE_RST = 0x0, 3481 MLX5_QPC_STATE_INIT = 0x1, 3482 MLX5_QPC_STATE_RTR = 0x2, 3483 MLX5_QPC_STATE_RTS = 0x3, 3484 MLX5_QPC_STATE_SQER = 0x4, 3485 MLX5_QPC_STATE_ERR = 0x6, 3486 MLX5_QPC_STATE_SQD = 0x7, 3487 MLX5_QPC_STATE_SUSPENDED = 0x9, 3488 }; 3489 3490 enum { 3491 MLX5_QPC_ST_RC = 0x0, 3492 MLX5_QPC_ST_UC = 0x1, 3493 MLX5_QPC_ST_UD = 0x2, 3494 MLX5_QPC_ST_XRC = 0x3, 3495 MLX5_QPC_ST_DCI = 0x5, 3496 MLX5_QPC_ST_QP0 = 0x7, 3497 MLX5_QPC_ST_QP1 = 0x8, 3498 MLX5_QPC_ST_RAW_DATAGRAM = 0x9, 3499 MLX5_QPC_ST_REG_UMR = 0xc, 3500 }; 3501 3502 enum { 3503 MLX5_QPC_PM_STATE_ARMED = 0x0, 3504 MLX5_QPC_PM_STATE_REARM = 0x1, 3505 MLX5_QPC_PM_STATE_RESERVED = 0x2, 3506 MLX5_QPC_PM_STATE_MIGRATED = 0x3, 3507 }; 3508 3509 enum { 3510 MLX5_QPC_OFFLOAD_TYPE_RNDV = 0x1, 3511 }; 3512 3513 enum { 3514 MLX5_QPC_END_PADDING_MODE_SCATTER_AS_IS = 0x0, 3515 MLX5_QPC_END_PADDING_MODE_PAD_TO_CACHE_LINE_ALIGNMENT = 0x1, 3516 }; 3517 3518 enum { 3519 MLX5_QPC_MTU_256_BYTES = 0x1, 3520 MLX5_QPC_MTU_512_BYTES = 0x2, 3521 MLX5_QPC_MTU_1K_BYTES = 0x3, 3522 MLX5_QPC_MTU_2K_BYTES = 0x4, 3523 MLX5_QPC_MTU_4K_BYTES = 0x5, 3524 MLX5_QPC_MTU_RAW_ETHERNET_QP = 0x7, 3525 }; 3526 3527 enum { 3528 MLX5_QPC_ATOMIC_MODE_IB_SPEC = 0x1, 3529 MLX5_QPC_ATOMIC_MODE_ONLY_8B = 0x2, 3530 MLX5_QPC_ATOMIC_MODE_UP_TO_8B = 0x3, 3531 MLX5_QPC_ATOMIC_MODE_UP_TO_16B = 0x4, 3532 MLX5_QPC_ATOMIC_MODE_UP_TO_32B = 0x5, 3533 MLX5_QPC_ATOMIC_MODE_UP_TO_64B = 0x6, 3534 MLX5_QPC_ATOMIC_MODE_UP_TO_128B = 0x7, 3535 MLX5_QPC_ATOMIC_MODE_UP_TO_256B = 0x8, 3536 }; 3537 3538 enum { 3539 MLX5_QPC_CS_REQ_DISABLE = 0x0, 3540 MLX5_QPC_CS_REQ_UP_TO_32B = 0x11, 3541 MLX5_QPC_CS_REQ_UP_TO_64B = 0x22, 3542 }; 3543 3544 enum { 3545 MLX5_QPC_CS_RES_DISABLE = 0x0, 3546 MLX5_QPC_CS_RES_UP_TO_32B = 0x1, 3547 MLX5_QPC_CS_RES_UP_TO_64B = 0x2, 3548 }; 3549 3550 enum { 3551 MLX5_TIMESTAMP_FORMAT_FREE_RUNNING = 0x0, 3552 MLX5_TIMESTAMP_FORMAT_DEFAULT = 0x1, 3553 MLX5_TIMESTAMP_FORMAT_REAL_TIME = 0x2, 3554 }; 3555 3556 struct mlx5_ifc_qpc_bits { 3557 u8 state[0x4]; 3558 u8 lag_tx_port_affinity[0x4]; 3559 u8 st[0x8]; 3560 u8 reserved_at_10[0x2]; 3561 u8 isolate_vl_tc[0x1]; 3562 u8 pm_state[0x2]; 3563 u8 reserved_at_15[0x1]; 3564 u8 req_e2e_credit_mode[0x2]; 3565 u8 offload_type[0x4]; 3566 u8 end_padding_mode[0x2]; 3567 u8 reserved_at_1e[0x2]; 3568 3569 u8 wq_signature[0x1]; 3570 u8 block_lb_mc[0x1]; 3571 u8 atomic_like_write_en[0x1]; 3572 u8 latency_sensitive[0x1]; 3573 u8 reserved_at_24[0x1]; 3574 u8 drain_sigerr[0x1]; 3575 u8 reserved_at_26[0x1]; 3576 u8 dp_ordering_force[0x1]; 3577 u8 pd[0x18]; 3578 3579 u8 mtu[0x3]; 3580 u8 log_msg_max[0x5]; 3581 u8 reserved_at_48[0x1]; 3582 u8 log_rq_size[0x4]; 3583 u8 log_rq_stride[0x3]; 3584 u8 no_sq[0x1]; 3585 u8 log_sq_size[0x4]; 3586 u8 reserved_at_55[0x1]; 3587 u8 retry_mode[0x2]; 3588 u8 ts_format[0x2]; 3589 u8 reserved_at_5a[0x1]; 3590 u8 rlky[0x1]; 3591 u8 ulp_stateless_offload_mode[0x4]; 3592 3593 u8 counter_set_id[0x8]; 3594 u8 uar_page[0x18]; 3595 3596 u8 reserved_at_80[0x8]; 3597 u8 user_index[0x18]; 3598 3599 u8 reserved_at_a0[0x3]; 3600 u8 log_page_size[0x5]; 3601 u8 remote_qpn[0x18]; 3602 3603 struct mlx5_ifc_ads_bits primary_address_path; 3604 3605 struct mlx5_ifc_ads_bits secondary_address_path; 3606 3607 u8 log_ack_req_freq[0x4]; 3608 u8 reserved_at_384[0x4]; 3609 u8 log_sra_max[0x3]; 3610 u8 reserved_at_38b[0x2]; 3611 u8 retry_count[0x3]; 3612 u8 rnr_retry[0x3]; 3613 u8 reserved_at_393[0x1]; 3614 u8 fre[0x1]; 3615 u8 cur_rnr_retry[0x3]; 3616 u8 cur_retry_count[0x3]; 3617 u8 reserved_at_39b[0x5]; 3618 3619 u8 reserved_at_3a0[0x20]; 3620 3621 u8 reserved_at_3c0[0x8]; 3622 u8 next_send_psn[0x18]; 3623 3624 u8 reserved_at_3e0[0x3]; 3625 u8 log_num_dci_stream_channels[0x5]; 3626 u8 cqn_snd[0x18]; 3627 3628 u8 reserved_at_400[0x3]; 3629 u8 log_num_dci_errored_streams[0x5]; 3630 u8 deth_sqpn[0x18]; 3631 3632 u8 reserved_at_420[0x20]; 3633 3634 u8 reserved_at_440[0x8]; 3635 u8 last_acked_psn[0x18]; 3636 3637 u8 reserved_at_460[0x8]; 3638 u8 ssn[0x18]; 3639 3640 u8 reserved_at_480[0x8]; 3641 u8 log_rra_max[0x3]; 3642 u8 reserved_at_48b[0x1]; 3643 u8 atomic_mode[0x4]; 3644 u8 rre[0x1]; 3645 u8 rwe[0x1]; 3646 u8 rae[0x1]; 3647 u8 reserved_at_493[0x1]; 3648 u8 page_offset[0x6]; 3649 u8 reserved_at_49a[0x2]; 3650 u8 dp_ordering_1[0x1]; 3651 u8 cd_slave_receive[0x1]; 3652 u8 cd_slave_send[0x1]; 3653 u8 cd_master[0x1]; 3654 3655 u8 reserved_at_4a0[0x3]; 3656 u8 min_rnr_nak[0x5]; 3657 u8 next_rcv_psn[0x18]; 3658 3659 u8 reserved_at_4c0[0x8]; 3660 u8 xrcd[0x18]; 3661 3662 u8 reserved_at_4e0[0x8]; 3663 u8 cqn_rcv[0x18]; 3664 3665 u8 dbr_addr[0x40]; 3666 3667 u8 q_key[0x20]; 3668 3669 u8 reserved_at_560[0x5]; 3670 u8 rq_type[0x3]; 3671 u8 srqn_rmpn_xrqn[0x18]; 3672 3673 u8 reserved_at_580[0x8]; 3674 u8 rmsn[0x18]; 3675 3676 u8 hw_sq_wqebb_counter[0x10]; 3677 u8 sw_sq_wqebb_counter[0x10]; 3678 3679 u8 hw_rq_counter[0x20]; 3680 3681 u8 sw_rq_counter[0x20]; 3682 3683 u8 reserved_at_600[0x20]; 3684 3685 u8 reserved_at_620[0xf]; 3686 u8 cgs[0x1]; 3687 u8 cs_req[0x8]; 3688 u8 cs_res[0x8]; 3689 3690 u8 dc_access_key[0x40]; 3691 3692 u8 reserved_at_680[0x3]; 3693 u8 dbr_umem_valid[0x1]; 3694 3695 u8 reserved_at_684[0xbc]; 3696 }; 3697 3698 struct mlx5_ifc_roce_addr_layout_bits { 3699 u8 source_l3_address[16][0x8]; 3700 3701 u8 reserved_at_80[0x3]; 3702 u8 vlan_valid[0x1]; 3703 u8 vlan_id[0xc]; 3704 u8 source_mac_47_32[0x10]; 3705 3706 u8 source_mac_31_0[0x20]; 3707 3708 u8 reserved_at_c0[0x14]; 3709 u8 roce_l3_type[0x4]; 3710 u8 roce_version[0x8]; 3711 3712 u8 reserved_at_e0[0x20]; 3713 }; 3714 3715 struct mlx5_ifc_crypto_cap_bits { 3716 u8 reserved_at_0[0x3]; 3717 u8 synchronize_dek[0x1]; 3718 u8 int_kek_manual[0x1]; 3719 u8 int_kek_auto[0x1]; 3720 u8 reserved_at_6[0x1a]; 3721 3722 u8 reserved_at_20[0x3]; 3723 u8 log_dek_max_alloc[0x5]; 3724 u8 reserved_at_28[0x3]; 3725 u8 log_max_num_deks[0x5]; 3726 u8 reserved_at_30[0x10]; 3727 3728 u8 reserved_at_40[0x20]; 3729 3730 u8 reserved_at_60[0x3]; 3731 u8 log_dek_granularity[0x5]; 3732 u8 reserved_at_68[0x3]; 3733 u8 log_max_num_int_kek[0x5]; 3734 u8 sw_wrapped_dek[0x10]; 3735 3736 u8 reserved_at_80[0x780]; 3737 }; 3738 3739 struct mlx5_ifc_shampo_cap_bits { 3740 u8 reserved_at_0[0x3]; 3741 u8 shampo_log_max_reservation_size[0x5]; 3742 u8 reserved_at_8[0x3]; 3743 u8 shampo_log_min_reservation_size[0x5]; 3744 u8 shampo_min_mss_size[0x10]; 3745 3746 u8 shampo_header_split[0x1]; 3747 u8 shampo_header_split_data_merge[0x1]; 3748 u8 reserved_at_22[0x1]; 3749 u8 shampo_log_max_headers_entry_size[0x5]; 3750 u8 reserved_at_28[0x18]; 3751 3752 u8 reserved_at_40[0x7c0]; 3753 }; 3754 3755 union mlx5_ifc_hca_cap_union_bits { 3756 struct mlx5_ifc_cmd_hca_cap_bits cmd_hca_cap; 3757 struct mlx5_ifc_cmd_hca_cap_2_bits cmd_hca_cap_2; 3758 struct mlx5_ifc_odp_cap_bits odp_cap; 3759 struct mlx5_ifc_atomic_caps_bits atomic_caps; 3760 struct mlx5_ifc_roce_cap_bits roce_cap; 3761 struct mlx5_ifc_per_protocol_networking_offload_caps_bits per_protocol_networking_offload_caps; 3762 struct mlx5_ifc_flow_table_nic_cap_bits flow_table_nic_cap; 3763 struct mlx5_ifc_flow_table_eswitch_cap_bits flow_table_eswitch_cap; 3764 struct mlx5_ifc_wqe_based_flow_table_cap_bits wqe_based_flow_table_cap; 3765 struct mlx5_ifc_esw_cap_bits esw_cap; 3766 struct mlx5_ifc_e_switch_cap_bits e_switch_cap; 3767 struct mlx5_ifc_port_selection_cap_bits port_selection_cap; 3768 struct mlx5_ifc_qos_cap_bits qos_cap; 3769 struct mlx5_ifc_debug_cap_bits debug_cap; 3770 struct mlx5_ifc_fpga_cap_bits fpga_cap; 3771 struct mlx5_ifc_tls_cap_bits tls_cap; 3772 struct mlx5_ifc_device_mem_cap_bits device_mem_cap; 3773 struct mlx5_ifc_virtio_emulation_cap_bits virtio_emulation_cap; 3774 struct mlx5_ifc_macsec_cap_bits macsec_cap; 3775 struct mlx5_ifc_crypto_cap_bits crypto_cap; 3776 struct mlx5_ifc_ipsec_cap_bits ipsec_cap; 3777 u8 reserved_at_0[0x8000]; 3778 }; 3779 3780 enum { 3781 MLX5_FLOW_CONTEXT_ACTION_ALLOW = 0x1, 3782 MLX5_FLOW_CONTEXT_ACTION_DROP = 0x2, 3783 MLX5_FLOW_CONTEXT_ACTION_FWD_DEST = 0x4, 3784 MLX5_FLOW_CONTEXT_ACTION_COUNT = 0x8, 3785 MLX5_FLOW_CONTEXT_ACTION_PACKET_REFORMAT = 0x10, 3786 MLX5_FLOW_CONTEXT_ACTION_DECAP = 0x20, 3787 MLX5_FLOW_CONTEXT_ACTION_MOD_HDR = 0x40, 3788 MLX5_FLOW_CONTEXT_ACTION_VLAN_POP = 0x80, 3789 MLX5_FLOW_CONTEXT_ACTION_VLAN_PUSH = 0x100, 3790 MLX5_FLOW_CONTEXT_ACTION_VLAN_POP_2 = 0x400, 3791 MLX5_FLOW_CONTEXT_ACTION_VLAN_PUSH_2 = 0x800, 3792 MLX5_FLOW_CONTEXT_ACTION_CRYPTO_DECRYPT = 0x1000, 3793 MLX5_FLOW_CONTEXT_ACTION_CRYPTO_ENCRYPT = 0x2000, 3794 MLX5_FLOW_CONTEXT_ACTION_EXECUTE_ASO = 0x4000, 3795 }; 3796 3797 enum { 3798 MLX5_FLOW_CONTEXT_FLOW_SOURCE_ANY_VPORT = 0x0, 3799 MLX5_FLOW_CONTEXT_FLOW_SOURCE_UPLINK = 0x1, 3800 MLX5_FLOW_CONTEXT_FLOW_SOURCE_LOCAL_VPORT = 0x2, 3801 }; 3802 3803 enum { 3804 MLX5_FLOW_CONTEXT_ENCRYPT_DECRYPT_TYPE_IPSEC = 0x0, 3805 MLX5_FLOW_CONTEXT_ENCRYPT_DECRYPT_TYPE_MACSEC = 0x1, 3806 }; 3807 3808 struct mlx5_ifc_vlan_bits { 3809 u8 ethtype[0x10]; 3810 u8 prio[0x3]; 3811 u8 cfi[0x1]; 3812 u8 vid[0xc]; 3813 }; 3814 3815 enum { 3816 MLX5_FLOW_METER_COLOR_RED = 0x0, 3817 MLX5_FLOW_METER_COLOR_YELLOW = 0x1, 3818 MLX5_FLOW_METER_COLOR_GREEN = 0x2, 3819 MLX5_FLOW_METER_COLOR_UNDEFINED = 0x3, 3820 }; 3821 3822 enum { 3823 MLX5_EXE_ASO_FLOW_METER = 0x2, 3824 }; 3825 3826 struct mlx5_ifc_exe_aso_ctrl_flow_meter_bits { 3827 u8 return_reg_id[0x4]; 3828 u8 aso_type[0x4]; 3829 u8 reserved_at_8[0x14]; 3830 u8 action[0x1]; 3831 u8 init_color[0x2]; 3832 u8 meter_id[0x1]; 3833 }; 3834 3835 union mlx5_ifc_exe_aso_ctrl { 3836 struct mlx5_ifc_exe_aso_ctrl_flow_meter_bits exe_aso_ctrl_flow_meter; 3837 }; 3838 3839 struct mlx5_ifc_execute_aso_bits { 3840 u8 valid[0x1]; 3841 u8 reserved_at_1[0x7]; 3842 u8 aso_object_id[0x18]; 3843 3844 union mlx5_ifc_exe_aso_ctrl exe_aso_ctrl; 3845 }; 3846 3847 struct mlx5_ifc_flow_context_bits { 3848 struct mlx5_ifc_vlan_bits push_vlan; 3849 3850 u8 group_id[0x20]; 3851 3852 u8 reserved_at_40[0x8]; 3853 u8 flow_tag[0x18]; 3854 3855 u8 reserved_at_60[0x10]; 3856 u8 action[0x10]; 3857 3858 u8 extended_destination[0x1]; 3859 u8 uplink_hairpin_en[0x1]; 3860 u8 flow_source[0x2]; 3861 u8 encrypt_decrypt_type[0x4]; 3862 u8 destination_list_size[0x18]; 3863 3864 u8 reserved_at_a0[0x8]; 3865 u8 flow_counter_list_size[0x18]; 3866 3867 u8 packet_reformat_id[0x20]; 3868 3869 u8 modify_header_id[0x20]; 3870 3871 struct mlx5_ifc_vlan_bits push_vlan_2; 3872 3873 u8 encrypt_decrypt_obj_id[0x20]; 3874 u8 reserved_at_140[0xc0]; 3875 3876 struct mlx5_ifc_fte_match_param_bits match_value; 3877 3878 struct mlx5_ifc_execute_aso_bits execute_aso[4]; 3879 3880 u8 reserved_at_1300[0x500]; 3881 3882 union mlx5_ifc_dest_format_flow_counter_list_auto_bits destination[]; 3883 }; 3884 3885 enum { 3886 MLX5_XRC_SRQC_STATE_GOOD = 0x0, 3887 MLX5_XRC_SRQC_STATE_ERROR = 0x1, 3888 }; 3889 3890 struct mlx5_ifc_xrc_srqc_bits { 3891 u8 state[0x4]; 3892 u8 log_xrc_srq_size[0x4]; 3893 u8 reserved_at_8[0x18]; 3894 3895 u8 wq_signature[0x1]; 3896 u8 cont_srq[0x1]; 3897 u8 reserved_at_22[0x1]; 3898 u8 rlky[0x1]; 3899 u8 basic_cyclic_rcv_wqe[0x1]; 3900 u8 log_rq_stride[0x3]; 3901 u8 xrcd[0x18]; 3902 3903 u8 page_offset[0x6]; 3904 u8 reserved_at_46[0x1]; 3905 u8 dbr_umem_valid[0x1]; 3906 u8 cqn[0x18]; 3907 3908 u8 reserved_at_60[0x20]; 3909 3910 u8 user_index_equal_xrc_srqn[0x1]; 3911 u8 reserved_at_81[0x1]; 3912 u8 log_page_size[0x6]; 3913 u8 user_index[0x18]; 3914 3915 u8 reserved_at_a0[0x20]; 3916 3917 u8 reserved_at_c0[0x8]; 3918 u8 pd[0x18]; 3919 3920 u8 lwm[0x10]; 3921 u8 wqe_cnt[0x10]; 3922 3923 u8 reserved_at_100[0x40]; 3924 3925 u8 db_record_addr_h[0x20]; 3926 3927 u8 db_record_addr_l[0x1e]; 3928 u8 reserved_at_17e[0x2]; 3929 3930 u8 reserved_at_180[0x80]; 3931 }; 3932 3933 struct mlx5_ifc_vnic_diagnostic_statistics_bits { 3934 u8 counter_error_queues[0x20]; 3935 3936 u8 total_error_queues[0x20]; 3937 3938 u8 send_queue_priority_update_flow[0x20]; 3939 3940 u8 reserved_at_60[0x20]; 3941 3942 u8 nic_receive_steering_discard[0x40]; 3943 3944 u8 receive_discard_vport_down[0x40]; 3945 3946 u8 transmit_discard_vport_down[0x40]; 3947 3948 u8 async_eq_overrun[0x20]; 3949 3950 u8 comp_eq_overrun[0x20]; 3951 3952 u8 reserved_at_180[0x20]; 3953 3954 u8 invalid_command[0x20]; 3955 3956 u8 quota_exceeded_command[0x20]; 3957 3958 u8 internal_rq_out_of_buffer[0x20]; 3959 3960 u8 cq_overrun[0x20]; 3961 3962 u8 eth_wqe_too_small[0x20]; 3963 3964 u8 reserved_at_220[0xc0]; 3965 3966 u8 generated_pkt_steering_fail[0x40]; 3967 3968 u8 handled_pkt_steering_fail[0x40]; 3969 3970 u8 reserved_at_360[0xc80]; 3971 }; 3972 3973 struct mlx5_ifc_traffic_counter_bits { 3974 u8 packets[0x40]; 3975 3976 u8 octets[0x40]; 3977 }; 3978 3979 struct mlx5_ifc_tisc_bits { 3980 u8 strict_lag_tx_port_affinity[0x1]; 3981 u8 tls_en[0x1]; 3982 u8 reserved_at_2[0x2]; 3983 u8 lag_tx_port_affinity[0x04]; 3984 3985 u8 reserved_at_8[0x4]; 3986 u8 prio[0x4]; 3987 u8 reserved_at_10[0x10]; 3988 3989 u8 reserved_at_20[0x100]; 3990 3991 u8 reserved_at_120[0x8]; 3992 u8 transport_domain[0x18]; 3993 3994 u8 reserved_at_140[0x8]; 3995 u8 underlay_qpn[0x18]; 3996 3997 u8 reserved_at_160[0x8]; 3998 u8 pd[0x18]; 3999 4000 u8 reserved_at_180[0x380]; 4001 }; 4002 4003 enum { 4004 MLX5_TIRC_DISP_TYPE_DIRECT = 0x0, 4005 MLX5_TIRC_DISP_TYPE_INDIRECT = 0x1, 4006 }; 4007 4008 enum { 4009 MLX5_TIRC_PACKET_MERGE_MASK_IPV4_LRO = BIT(0), 4010 MLX5_TIRC_PACKET_MERGE_MASK_IPV6_LRO = BIT(1), 4011 }; 4012 4013 enum { 4014 MLX5_RX_HASH_FN_NONE = 0x0, 4015 MLX5_RX_HASH_FN_INVERTED_XOR8 = 0x1, 4016 MLX5_RX_HASH_FN_TOEPLITZ = 0x2, 4017 }; 4018 4019 enum { 4020 MLX5_TIRC_SELF_LB_BLOCK_BLOCK_UNICAST = 0x1, 4021 MLX5_TIRC_SELF_LB_BLOCK_BLOCK_MULTICAST = 0x2, 4022 }; 4023 4024 struct mlx5_ifc_tirc_bits { 4025 u8 reserved_at_0[0x20]; 4026 4027 u8 disp_type[0x4]; 4028 u8 tls_en[0x1]; 4029 u8 reserved_at_25[0x1b]; 4030 4031 u8 reserved_at_40[0x40]; 4032 4033 u8 reserved_at_80[0x4]; 4034 u8 lro_timeout_period_usecs[0x10]; 4035 u8 packet_merge_mask[0x4]; 4036 u8 lro_max_ip_payload_size[0x8]; 4037 4038 u8 reserved_at_a0[0x40]; 4039 4040 u8 reserved_at_e0[0x8]; 4041 u8 inline_rqn[0x18]; 4042 4043 u8 rx_hash_symmetric[0x1]; 4044 u8 reserved_at_101[0x1]; 4045 u8 tunneled_offload_en[0x1]; 4046 u8 reserved_at_103[0x5]; 4047 u8 indirect_table[0x18]; 4048 4049 u8 rx_hash_fn[0x4]; 4050 u8 reserved_at_124[0x2]; 4051 u8 self_lb_block[0x2]; 4052 u8 transport_domain[0x18]; 4053 4054 u8 rx_hash_toeplitz_key[10][0x20]; 4055 4056 struct mlx5_ifc_rx_hash_field_select_bits rx_hash_field_selector_outer; 4057 4058 struct mlx5_ifc_rx_hash_field_select_bits rx_hash_field_selector_inner; 4059 4060 u8 reserved_at_2c0[0x4c0]; 4061 }; 4062 4063 enum { 4064 MLX5_SRQC_STATE_GOOD = 0x0, 4065 MLX5_SRQC_STATE_ERROR = 0x1, 4066 }; 4067 4068 struct mlx5_ifc_srqc_bits { 4069 u8 state[0x4]; 4070 u8 log_srq_size[0x4]; 4071 u8 reserved_at_8[0x18]; 4072 4073 u8 wq_signature[0x1]; 4074 u8 cont_srq[0x1]; 4075 u8 reserved_at_22[0x1]; 4076 u8 rlky[0x1]; 4077 u8 reserved_at_24[0x1]; 4078 u8 log_rq_stride[0x3]; 4079 u8 xrcd[0x18]; 4080 4081 u8 page_offset[0x6]; 4082 u8 reserved_at_46[0x2]; 4083 u8 cqn[0x18]; 4084 4085 u8 reserved_at_60[0x20]; 4086 4087 u8 reserved_at_80[0x2]; 4088 u8 log_page_size[0x6]; 4089 u8 reserved_at_88[0x18]; 4090 4091 u8 reserved_at_a0[0x20]; 4092 4093 u8 reserved_at_c0[0x8]; 4094 u8 pd[0x18]; 4095 4096 u8 lwm[0x10]; 4097 u8 wqe_cnt[0x10]; 4098 4099 u8 reserved_at_100[0x40]; 4100 4101 u8 dbr_addr[0x40]; 4102 4103 u8 reserved_at_180[0x80]; 4104 }; 4105 4106 enum { 4107 MLX5_SQC_STATE_RST = 0x0, 4108 MLX5_SQC_STATE_RDY = 0x1, 4109 MLX5_SQC_STATE_ERR = 0x3, 4110 }; 4111 4112 struct mlx5_ifc_sqc_bits { 4113 u8 rlky[0x1]; 4114 u8 cd_master[0x1]; 4115 u8 fre[0x1]; 4116 u8 flush_in_error_en[0x1]; 4117 u8 allow_multi_pkt_send_wqe[0x1]; 4118 u8 min_wqe_inline_mode[0x3]; 4119 u8 state[0x4]; 4120 u8 reg_umr[0x1]; 4121 u8 allow_swp[0x1]; 4122 u8 hairpin[0x1]; 4123 u8 non_wire[0x1]; 4124 u8 reserved_at_10[0xa]; 4125 u8 ts_format[0x2]; 4126 u8 reserved_at_1c[0x4]; 4127 4128 u8 reserved_at_20[0x8]; 4129 u8 user_index[0x18]; 4130 4131 u8 reserved_at_40[0x8]; 4132 u8 cqn[0x18]; 4133 4134 u8 reserved_at_60[0x8]; 4135 u8 hairpin_peer_rq[0x18]; 4136 4137 u8 reserved_at_80[0x10]; 4138 u8 hairpin_peer_vhca[0x10]; 4139 4140 u8 reserved_at_a0[0x20]; 4141 4142 u8 reserved_at_c0[0x8]; 4143 u8 ts_cqe_to_dest_cqn[0x18]; 4144 4145 u8 reserved_at_e0[0x10]; 4146 u8 packet_pacing_rate_limit_index[0x10]; 4147 u8 tis_lst_sz[0x10]; 4148 u8 qos_queue_group_id[0x10]; 4149 4150 u8 reserved_at_120[0x40]; 4151 4152 u8 reserved_at_160[0x8]; 4153 u8 tis_num_0[0x18]; 4154 4155 struct mlx5_ifc_wq_bits wq; 4156 }; 4157 4158 enum { 4159 SCHEDULING_CONTEXT_ELEMENT_TYPE_TSAR = 0x0, 4160 SCHEDULING_CONTEXT_ELEMENT_TYPE_VPORT = 0x1, 4161 SCHEDULING_CONTEXT_ELEMENT_TYPE_VPORT_TC = 0x2, 4162 SCHEDULING_CONTEXT_ELEMENT_TYPE_PARA_VPORT_TC = 0x3, 4163 SCHEDULING_CONTEXT_ELEMENT_TYPE_QUEUE_GROUP = 0x4, 4164 SCHEDULING_CONTEXT_ELEMENT_TYPE_RATE_LIMIT = 0x5, 4165 }; 4166 4167 enum { 4168 ELEMENT_TYPE_CAP_MASK_TSAR = 1 << 0, 4169 ELEMENT_TYPE_CAP_MASK_VPORT = 1 << 1, 4170 ELEMENT_TYPE_CAP_MASK_VPORT_TC = 1 << 2, 4171 ELEMENT_TYPE_CAP_MASK_PARA_VPORT_TC = 1 << 3, 4172 ELEMENT_TYPE_CAP_MASK_QUEUE_GROUP = 1 << 4, 4173 ELEMENT_TYPE_CAP_MASK_RATE_LIMIT = 1 << 5, 4174 }; 4175 4176 enum { 4177 TSAR_ELEMENT_TSAR_TYPE_DWRR = 0x0, 4178 TSAR_ELEMENT_TSAR_TYPE_ROUND_ROBIN = 0x1, 4179 TSAR_ELEMENT_TSAR_TYPE_ETS = 0x2, 4180 TSAR_ELEMENT_TSAR_TYPE_TC_ARB = 0x3, 4181 }; 4182 4183 enum { 4184 TSAR_TYPE_CAP_MASK_DWRR = 1 << 0, 4185 TSAR_TYPE_CAP_MASK_ROUND_ROBIN = 1 << 1, 4186 TSAR_TYPE_CAP_MASK_ETS = 1 << 2, 4187 TSAR_TYPE_CAP_MASK_TC_ARB = 1 << 3, 4188 }; 4189 4190 struct mlx5_ifc_tsar_element_bits { 4191 u8 traffic_class[0x4]; 4192 u8 reserved_at_4[0x4]; 4193 u8 tsar_type[0x8]; 4194 u8 reserved_at_10[0x10]; 4195 }; 4196 4197 struct mlx5_ifc_vport_element_bits { 4198 u8 reserved_at_0[0x4]; 4199 u8 eswitch_owner_vhca_id_valid[0x1]; 4200 u8 eswitch_owner_vhca_id[0xb]; 4201 u8 vport_number[0x10]; 4202 }; 4203 4204 struct mlx5_ifc_vport_tc_element_bits { 4205 u8 traffic_class[0x4]; 4206 u8 eswitch_owner_vhca_id_valid[0x1]; 4207 u8 eswitch_owner_vhca_id[0xb]; 4208 u8 vport_number[0x10]; 4209 }; 4210 4211 union mlx5_ifc_element_attributes_bits { 4212 struct mlx5_ifc_tsar_element_bits tsar; 4213 struct mlx5_ifc_vport_element_bits vport; 4214 struct mlx5_ifc_vport_tc_element_bits vport_tc; 4215 u8 reserved_at_0[0x20]; 4216 }; 4217 4218 struct mlx5_ifc_scheduling_context_bits { 4219 u8 element_type[0x8]; 4220 u8 reserved_at_8[0x18]; 4221 4222 union mlx5_ifc_element_attributes_bits element_attributes; 4223 4224 u8 parent_element_id[0x20]; 4225 4226 u8 reserved_at_60[0x40]; 4227 4228 u8 bw_share[0x20]; 4229 4230 u8 max_average_bw[0x20]; 4231 4232 u8 max_bw_obj_id[0x20]; 4233 4234 u8 reserved_at_100[0x100]; 4235 }; 4236 4237 struct mlx5_ifc_rqtc_bits { 4238 u8 reserved_at_0[0xa0]; 4239 4240 u8 reserved_at_a0[0x5]; 4241 u8 list_q_type[0x3]; 4242 u8 reserved_at_a8[0x8]; 4243 u8 rqt_max_size[0x10]; 4244 4245 u8 rq_vhca_id_format[0x1]; 4246 u8 reserved_at_c1[0xf]; 4247 u8 rqt_actual_size[0x10]; 4248 4249 u8 reserved_at_e0[0x6a0]; 4250 4251 union { 4252 DECLARE_FLEX_ARRAY(struct mlx5_ifc_rq_num_bits, rq_num); 4253 DECLARE_FLEX_ARRAY(struct mlx5_ifc_rq_vhca_bits, rq_vhca); 4254 }; 4255 }; 4256 4257 enum { 4258 MLX5_RQC_MEM_RQ_TYPE_MEMORY_RQ_INLINE = 0x0, 4259 MLX5_RQC_MEM_RQ_TYPE_MEMORY_RQ_RMP = 0x1, 4260 }; 4261 4262 enum { 4263 MLX5_RQC_STATE_RST = 0x0, 4264 MLX5_RQC_STATE_RDY = 0x1, 4265 MLX5_RQC_STATE_ERR = 0x3, 4266 }; 4267 4268 enum { 4269 MLX5_RQC_SHAMPO_NO_MATCH_ALIGNMENT_GRANULARITY_BYTE = 0x0, 4270 MLX5_RQC_SHAMPO_NO_MATCH_ALIGNMENT_GRANULARITY_STRIDE = 0x1, 4271 MLX5_RQC_SHAMPO_NO_MATCH_ALIGNMENT_GRANULARITY_PAGE = 0x2, 4272 }; 4273 4274 enum { 4275 MLX5_RQC_SHAMPO_MATCH_CRITERIA_TYPE_NO_MATCH = 0x0, 4276 MLX5_RQC_SHAMPO_MATCH_CRITERIA_TYPE_EXTENDED = 0x1, 4277 MLX5_RQC_SHAMPO_MATCH_CRITERIA_TYPE_FIVE_TUPLE = 0x2, 4278 }; 4279 4280 struct mlx5_ifc_rqc_bits { 4281 u8 rlky[0x1]; 4282 u8 delay_drop_en[0x1]; 4283 u8 scatter_fcs[0x1]; 4284 u8 vsd[0x1]; 4285 u8 mem_rq_type[0x4]; 4286 u8 state[0x4]; 4287 u8 reserved_at_c[0x1]; 4288 u8 flush_in_error_en[0x1]; 4289 u8 hairpin[0x1]; 4290 u8 reserved_at_f[0xb]; 4291 u8 ts_format[0x2]; 4292 u8 reserved_at_1c[0x4]; 4293 4294 u8 reserved_at_20[0x8]; 4295 u8 user_index[0x18]; 4296 4297 u8 reserved_at_40[0x8]; 4298 u8 cqn[0x18]; 4299 4300 u8 counter_set_id[0x8]; 4301 u8 reserved_at_68[0x18]; 4302 4303 u8 reserved_at_80[0x8]; 4304 u8 rmpn[0x18]; 4305 4306 u8 reserved_at_a0[0x8]; 4307 u8 hairpin_peer_sq[0x18]; 4308 4309 u8 reserved_at_c0[0x10]; 4310 u8 hairpin_peer_vhca[0x10]; 4311 4312 u8 reserved_at_e0[0x46]; 4313 u8 shampo_no_match_alignment_granularity[0x2]; 4314 u8 reserved_at_128[0x6]; 4315 u8 shampo_match_criteria_type[0x2]; 4316 u8 reservation_timeout[0x10]; 4317 4318 u8 reserved_at_140[0x40]; 4319 4320 struct mlx5_ifc_wq_bits wq; 4321 }; 4322 4323 enum { 4324 MLX5_RMPC_STATE_RDY = 0x1, 4325 MLX5_RMPC_STATE_ERR = 0x3, 4326 }; 4327 4328 struct mlx5_ifc_rmpc_bits { 4329 u8 reserved_at_0[0x8]; 4330 u8 state[0x4]; 4331 u8 reserved_at_c[0x14]; 4332 4333 u8 basic_cyclic_rcv_wqe[0x1]; 4334 u8 reserved_at_21[0x1f]; 4335 4336 u8 reserved_at_40[0x140]; 4337 4338 struct mlx5_ifc_wq_bits wq; 4339 }; 4340 4341 enum { 4342 VHCA_ID_TYPE_HW = 0, 4343 VHCA_ID_TYPE_SW = 1, 4344 }; 4345 4346 struct mlx5_ifc_nic_vport_context_bits { 4347 u8 reserved_at_0[0x5]; 4348 u8 min_wqe_inline_mode[0x3]; 4349 u8 reserved_at_8[0x15]; 4350 u8 disable_mc_local_lb[0x1]; 4351 u8 disable_uc_local_lb[0x1]; 4352 u8 roce_en[0x1]; 4353 4354 u8 arm_change_event[0x1]; 4355 u8 reserved_at_21[0x1a]; 4356 u8 event_on_mtu[0x1]; 4357 u8 event_on_promisc_change[0x1]; 4358 u8 event_on_vlan_change[0x1]; 4359 u8 event_on_mc_address_change[0x1]; 4360 u8 event_on_uc_address_change[0x1]; 4361 4362 u8 vhca_id_type[0x1]; 4363 u8 reserved_at_41[0xb]; 4364 u8 affiliation_criteria[0x4]; 4365 u8 affiliated_vhca_id[0x10]; 4366 4367 u8 reserved_at_60[0xa0]; 4368 4369 u8 reserved_at_100[0x1]; 4370 u8 sd_group[0x3]; 4371 u8 reserved_at_104[0x1c]; 4372 4373 u8 reserved_at_120[0x10]; 4374 u8 mtu[0x10]; 4375 4376 u8 system_image_guid[0x40]; 4377 u8 port_guid[0x40]; 4378 u8 node_guid[0x40]; 4379 4380 u8 reserved_at_200[0x140]; 4381 u8 qkey_violation_counter[0x10]; 4382 u8 reserved_at_350[0x430]; 4383 4384 u8 promisc_uc[0x1]; 4385 u8 promisc_mc[0x1]; 4386 u8 promisc_all[0x1]; 4387 u8 reserved_at_783[0x2]; 4388 u8 allowed_list_type[0x3]; 4389 u8 reserved_at_788[0xc]; 4390 u8 allowed_list_size[0xc]; 4391 4392 struct mlx5_ifc_mac_address_layout_bits permanent_address; 4393 4394 u8 reserved_at_7e0[0x20]; 4395 4396 u8 current_uc_mac_address[][0x40]; 4397 }; 4398 4399 enum { 4400 MLX5_MKC_ACCESS_MODE_PA = 0x0, 4401 MLX5_MKC_ACCESS_MODE_MTT = 0x1, 4402 MLX5_MKC_ACCESS_MODE_KLMS = 0x2, 4403 MLX5_MKC_ACCESS_MODE_KSM = 0x3, 4404 MLX5_MKC_ACCESS_MODE_SW_ICM = 0x4, 4405 MLX5_MKC_ACCESS_MODE_MEMIC = 0x5, 4406 MLX5_MKC_ACCESS_MODE_CROSSING = 0x6, 4407 }; 4408 4409 struct mlx5_ifc_mkc_bits { 4410 u8 reserved_at_0[0x1]; 4411 u8 free[0x1]; 4412 u8 reserved_at_2[0x1]; 4413 u8 access_mode_4_2[0x3]; 4414 u8 reserved_at_6[0x7]; 4415 u8 relaxed_ordering_write[0x1]; 4416 u8 reserved_at_e[0x1]; 4417 u8 small_fence_on_rdma_read_response[0x1]; 4418 u8 umr_en[0x1]; 4419 u8 a[0x1]; 4420 u8 rw[0x1]; 4421 u8 rr[0x1]; 4422 u8 lw[0x1]; 4423 u8 lr[0x1]; 4424 u8 access_mode_1_0[0x2]; 4425 u8 reserved_at_18[0x2]; 4426 u8 ma_translation_mode[0x2]; 4427 u8 reserved_at_1c[0x4]; 4428 4429 u8 qpn[0x18]; 4430 u8 mkey_7_0[0x8]; 4431 4432 u8 reserved_at_40[0x20]; 4433 4434 u8 length64[0x1]; 4435 u8 bsf_en[0x1]; 4436 u8 sync_umr[0x1]; 4437 u8 reserved_at_63[0x2]; 4438 u8 expected_sigerr_count[0x1]; 4439 u8 reserved_at_66[0x1]; 4440 u8 en_rinval[0x1]; 4441 u8 pd[0x18]; 4442 4443 u8 start_addr[0x40]; 4444 4445 u8 len[0x40]; 4446 4447 u8 bsf_octword_size[0x20]; 4448 4449 u8 reserved_at_120[0x60]; 4450 4451 u8 crossing_target_vhca_id[0x10]; 4452 u8 reserved_at_190[0x10]; 4453 4454 u8 translations_octword_size[0x20]; 4455 4456 u8 reserved_at_1c0[0x19]; 4457 u8 relaxed_ordering_read[0x1]; 4458 u8 log_page_size[0x6]; 4459 4460 u8 reserved_at_1e0[0x20]; 4461 }; 4462 4463 struct mlx5_ifc_pkey_bits { 4464 u8 reserved_at_0[0x10]; 4465 u8 pkey[0x10]; 4466 }; 4467 4468 struct mlx5_ifc_array128_auto_bits { 4469 u8 array128_auto[16][0x8]; 4470 }; 4471 4472 struct mlx5_ifc_hca_vport_context_bits { 4473 u8 field_select[0x20]; 4474 4475 u8 reserved_at_20[0xe0]; 4476 4477 u8 sm_virt_aware[0x1]; 4478 u8 has_smi[0x1]; 4479 u8 has_raw[0x1]; 4480 u8 grh_required[0x1]; 4481 u8 reserved_at_104[0x4]; 4482 u8 num_port_plane[0x8]; 4483 u8 port_physical_state[0x4]; 4484 u8 vport_state_policy[0x4]; 4485 u8 port_state[0x4]; 4486 u8 vport_state[0x4]; 4487 4488 u8 reserved_at_120[0x20]; 4489 4490 u8 system_image_guid[0x40]; 4491 4492 u8 port_guid[0x40]; 4493 4494 u8 node_guid[0x40]; 4495 4496 u8 cap_mask1[0x20]; 4497 4498 u8 cap_mask1_field_select[0x20]; 4499 4500 u8 cap_mask2[0x20]; 4501 4502 u8 cap_mask2_field_select[0x20]; 4503 4504 u8 reserved_at_280[0x80]; 4505 4506 u8 lid[0x10]; 4507 u8 reserved_at_310[0x4]; 4508 u8 init_type_reply[0x4]; 4509 u8 lmc[0x3]; 4510 u8 subnet_timeout[0x5]; 4511 4512 u8 sm_lid[0x10]; 4513 u8 sm_sl[0x4]; 4514 u8 reserved_at_334[0xc]; 4515 4516 u8 qkey_violation_counter[0x10]; 4517 u8 pkey_violation_counter[0x10]; 4518 4519 u8 reserved_at_360[0xca0]; 4520 }; 4521 4522 struct mlx5_ifc_esw_vport_context_bits { 4523 u8 fdb_to_vport_reg_c[0x1]; 4524 u8 reserved_at_1[0x2]; 4525 u8 vport_svlan_strip[0x1]; 4526 u8 vport_cvlan_strip[0x1]; 4527 u8 vport_svlan_insert[0x1]; 4528 u8 vport_cvlan_insert[0x2]; 4529 u8 fdb_to_vport_reg_c_id[0x8]; 4530 u8 reserved_at_10[0x10]; 4531 4532 u8 reserved_at_20[0x20]; 4533 4534 u8 svlan_cfi[0x1]; 4535 u8 svlan_pcp[0x3]; 4536 u8 svlan_id[0xc]; 4537 u8 cvlan_cfi[0x1]; 4538 u8 cvlan_pcp[0x3]; 4539 u8 cvlan_id[0xc]; 4540 4541 u8 reserved_at_60[0x720]; 4542 4543 u8 sw_steering_vport_icm_address_rx[0x40]; 4544 4545 u8 sw_steering_vport_icm_address_tx[0x40]; 4546 }; 4547 4548 enum { 4549 MLX5_EQC_STATUS_OK = 0x0, 4550 MLX5_EQC_STATUS_EQ_WRITE_FAILURE = 0xa, 4551 }; 4552 4553 enum { 4554 MLX5_EQC_ST_ARMED = 0x9, 4555 MLX5_EQC_ST_FIRED = 0xa, 4556 }; 4557 4558 struct mlx5_ifc_eqc_bits { 4559 u8 status[0x4]; 4560 u8 reserved_at_4[0x9]; 4561 u8 ec[0x1]; 4562 u8 oi[0x1]; 4563 u8 reserved_at_f[0x5]; 4564 u8 st[0x4]; 4565 u8 reserved_at_18[0x8]; 4566 4567 u8 reserved_at_20[0x20]; 4568 4569 u8 reserved_at_40[0x14]; 4570 u8 page_offset[0x6]; 4571 u8 reserved_at_5a[0x6]; 4572 4573 u8 reserved_at_60[0x3]; 4574 u8 log_eq_size[0x5]; 4575 u8 uar_page[0x18]; 4576 4577 u8 reserved_at_80[0x20]; 4578 4579 u8 reserved_at_a0[0x14]; 4580 u8 intr[0xc]; 4581 4582 u8 reserved_at_c0[0x3]; 4583 u8 log_page_size[0x5]; 4584 u8 reserved_at_c8[0x18]; 4585 4586 u8 reserved_at_e0[0x60]; 4587 4588 u8 reserved_at_140[0x8]; 4589 u8 consumer_counter[0x18]; 4590 4591 u8 reserved_at_160[0x8]; 4592 u8 producer_counter[0x18]; 4593 4594 u8 reserved_at_180[0x80]; 4595 }; 4596 4597 enum { 4598 MLX5_DCTC_STATE_ACTIVE = 0x0, 4599 MLX5_DCTC_STATE_DRAINING = 0x1, 4600 MLX5_DCTC_STATE_DRAINED = 0x2, 4601 }; 4602 4603 enum { 4604 MLX5_DCTC_CS_RES_DISABLE = 0x0, 4605 MLX5_DCTC_CS_RES_NA = 0x1, 4606 MLX5_DCTC_CS_RES_UP_TO_64B = 0x2, 4607 }; 4608 4609 enum { 4610 MLX5_DCTC_MTU_256_BYTES = 0x1, 4611 MLX5_DCTC_MTU_512_BYTES = 0x2, 4612 MLX5_DCTC_MTU_1K_BYTES = 0x3, 4613 MLX5_DCTC_MTU_2K_BYTES = 0x4, 4614 MLX5_DCTC_MTU_4K_BYTES = 0x5, 4615 }; 4616 4617 struct mlx5_ifc_dctc_bits { 4618 u8 reserved_at_0[0x4]; 4619 u8 state[0x4]; 4620 u8 reserved_at_8[0x18]; 4621 4622 u8 reserved_at_20[0x7]; 4623 u8 dp_ordering_force[0x1]; 4624 u8 user_index[0x18]; 4625 4626 u8 reserved_at_40[0x8]; 4627 u8 cqn[0x18]; 4628 4629 u8 counter_set_id[0x8]; 4630 u8 atomic_mode[0x4]; 4631 u8 rre[0x1]; 4632 u8 rwe[0x1]; 4633 u8 rae[0x1]; 4634 u8 atomic_like_write_en[0x1]; 4635 u8 latency_sensitive[0x1]; 4636 u8 rlky[0x1]; 4637 u8 free_ar[0x1]; 4638 u8 reserved_at_73[0x1]; 4639 u8 dp_ordering_1[0x1]; 4640 u8 reserved_at_75[0xb]; 4641 4642 u8 reserved_at_80[0x8]; 4643 u8 cs_res[0x8]; 4644 u8 reserved_at_90[0x3]; 4645 u8 min_rnr_nak[0x5]; 4646 u8 reserved_at_98[0x8]; 4647 4648 u8 reserved_at_a0[0x8]; 4649 u8 srqn_xrqn[0x18]; 4650 4651 u8 reserved_at_c0[0x8]; 4652 u8 pd[0x18]; 4653 4654 u8 tclass[0x8]; 4655 u8 reserved_at_e8[0x4]; 4656 u8 flow_label[0x14]; 4657 4658 u8 dc_access_key[0x40]; 4659 4660 u8 reserved_at_140[0x5]; 4661 u8 mtu[0x3]; 4662 u8 port[0x8]; 4663 u8 pkey_index[0x10]; 4664 4665 u8 reserved_at_160[0x8]; 4666 u8 my_addr_index[0x8]; 4667 u8 reserved_at_170[0x8]; 4668 u8 hop_limit[0x8]; 4669 4670 u8 dc_access_key_violation_count[0x20]; 4671 4672 u8 reserved_at_1a0[0x14]; 4673 u8 dei_cfi[0x1]; 4674 u8 eth_prio[0x3]; 4675 u8 ecn[0x2]; 4676 u8 dscp[0x6]; 4677 4678 u8 reserved_at_1c0[0x20]; 4679 u8 ece[0x20]; 4680 }; 4681 4682 enum { 4683 MLX5_CQC_STATUS_OK = 0x0, 4684 MLX5_CQC_STATUS_CQ_OVERFLOW = 0x9, 4685 MLX5_CQC_STATUS_CQ_WRITE_FAIL = 0xa, 4686 }; 4687 4688 enum { 4689 MLX5_CQC_CQE_SZ_64_BYTES = 0x0, 4690 MLX5_CQC_CQE_SZ_128_BYTES = 0x1, 4691 }; 4692 4693 enum { 4694 MLX5_CQC_ST_SOLICITED_NOTIFICATION_REQUEST_ARMED = 0x6, 4695 MLX5_CQC_ST_NOTIFICATION_REQUEST_ARMED = 0x9, 4696 MLX5_CQC_ST_FIRED = 0xa, 4697 }; 4698 4699 enum mlx5_cq_period_mode { 4700 MLX5_CQ_PERIOD_MODE_START_FROM_EQE = 0x0, 4701 MLX5_CQ_PERIOD_MODE_START_FROM_CQE = 0x1, 4702 MLX5_CQ_PERIOD_NUM_MODES, 4703 }; 4704 4705 struct mlx5_ifc_cqc_bits { 4706 u8 status[0x4]; 4707 u8 reserved_at_4[0x2]; 4708 u8 dbr_umem_valid[0x1]; 4709 u8 apu_cq[0x1]; 4710 u8 cqe_sz[0x3]; 4711 u8 cc[0x1]; 4712 u8 reserved_at_c[0x1]; 4713 u8 scqe_break_moderation_en[0x1]; 4714 u8 oi[0x1]; 4715 u8 cq_period_mode[0x2]; 4716 u8 cqe_comp_en[0x1]; 4717 u8 mini_cqe_res_format[0x2]; 4718 u8 st[0x4]; 4719 u8 reserved_at_18[0x6]; 4720 u8 cqe_compression_layout[0x2]; 4721 4722 u8 reserved_at_20[0x20]; 4723 4724 u8 reserved_at_40[0x14]; 4725 u8 page_offset[0x6]; 4726 u8 reserved_at_5a[0x6]; 4727 4728 u8 reserved_at_60[0x3]; 4729 u8 log_cq_size[0x5]; 4730 u8 uar_page[0x18]; 4731 4732 u8 reserved_at_80[0x4]; 4733 u8 cq_period[0xc]; 4734 u8 cq_max_count[0x10]; 4735 4736 u8 c_eqn_or_apu_element[0x20]; 4737 4738 u8 reserved_at_c0[0x3]; 4739 u8 log_page_size[0x5]; 4740 u8 reserved_at_c8[0x18]; 4741 4742 u8 reserved_at_e0[0x20]; 4743 4744 u8 reserved_at_100[0x8]; 4745 u8 last_notified_index[0x18]; 4746 4747 u8 reserved_at_120[0x8]; 4748 u8 last_solicit_index[0x18]; 4749 4750 u8 reserved_at_140[0x8]; 4751 u8 consumer_counter[0x18]; 4752 4753 u8 reserved_at_160[0x8]; 4754 u8 producer_counter[0x18]; 4755 4756 u8 reserved_at_180[0x40]; 4757 4758 u8 dbr_addr[0x40]; 4759 }; 4760 4761 union mlx5_ifc_cong_control_roce_ecn_auto_bits { 4762 struct mlx5_ifc_cong_control_802_1qau_rp_bits cong_control_802_1qau_rp; 4763 struct mlx5_ifc_cong_control_r_roce_ecn_rp_bits cong_control_r_roce_ecn_rp; 4764 struct mlx5_ifc_cong_control_r_roce_ecn_np_bits cong_control_r_roce_ecn_np; 4765 struct mlx5_ifc_cong_control_r_roce_general_bits cong_control_r_roce_general; 4766 u8 reserved_at_0[0x800]; 4767 }; 4768 4769 struct mlx5_ifc_query_adapter_param_block_bits { 4770 u8 reserved_at_0[0xc0]; 4771 4772 u8 reserved_at_c0[0x8]; 4773 u8 ieee_vendor_id[0x18]; 4774 4775 u8 reserved_at_e0[0x10]; 4776 u8 vsd_vendor_id[0x10]; 4777 4778 u8 vsd[208][0x8]; 4779 4780 u8 vsd_contd_psid[16][0x8]; 4781 }; 4782 4783 enum { 4784 MLX5_XRQC_STATE_GOOD = 0x0, 4785 MLX5_XRQC_STATE_ERROR = 0x1, 4786 }; 4787 4788 enum { 4789 MLX5_XRQC_TOPOLOGY_NO_SPECIAL_TOPOLOGY = 0x0, 4790 MLX5_XRQC_TOPOLOGY_TAG_MATCHING = 0x1, 4791 }; 4792 4793 enum { 4794 MLX5_XRQC_OFFLOAD_RNDV = 0x1, 4795 }; 4796 4797 struct mlx5_ifc_tag_matching_topology_context_bits { 4798 u8 log_matching_list_sz[0x4]; 4799 u8 reserved_at_4[0xc]; 4800 u8 append_next_index[0x10]; 4801 4802 u8 sw_phase_cnt[0x10]; 4803 u8 hw_phase_cnt[0x10]; 4804 4805 u8 reserved_at_40[0x40]; 4806 }; 4807 4808 struct mlx5_ifc_xrqc_bits { 4809 u8 state[0x4]; 4810 u8 rlkey[0x1]; 4811 u8 reserved_at_5[0xf]; 4812 u8 topology[0x4]; 4813 u8 reserved_at_18[0x4]; 4814 u8 offload[0x4]; 4815 4816 u8 reserved_at_20[0x8]; 4817 u8 user_index[0x18]; 4818 4819 u8 reserved_at_40[0x8]; 4820 u8 cqn[0x18]; 4821 4822 u8 reserved_at_60[0xa0]; 4823 4824 struct mlx5_ifc_tag_matching_topology_context_bits tag_matching_topology_context; 4825 4826 u8 reserved_at_180[0x280]; 4827 4828 struct mlx5_ifc_wq_bits wq; 4829 }; 4830 4831 union mlx5_ifc_modify_field_select_resize_field_select_auto_bits { 4832 struct mlx5_ifc_modify_field_select_bits modify_field_select; 4833 struct mlx5_ifc_resize_field_select_bits resize_field_select; 4834 u8 reserved_at_0[0x20]; 4835 }; 4836 4837 union mlx5_ifc_field_select_802_1_r_roce_auto_bits { 4838 struct mlx5_ifc_field_select_802_1qau_rp_bits field_select_802_1qau_rp; 4839 struct mlx5_ifc_field_select_r_roce_rp_bits field_select_r_roce_rp; 4840 struct mlx5_ifc_field_select_r_roce_np_bits field_select_r_roce_np; 4841 u8 reserved_at_0[0x20]; 4842 }; 4843 4844 union mlx5_ifc_eth_cntrs_grp_data_layout_auto_bits { 4845 struct mlx5_ifc_eth_802_3_cntrs_grp_data_layout_bits eth_802_3_cntrs_grp_data_layout; 4846 struct mlx5_ifc_eth_2863_cntrs_grp_data_layout_bits eth_2863_cntrs_grp_data_layout; 4847 struct mlx5_ifc_eth_2819_cntrs_grp_data_layout_bits eth_2819_cntrs_grp_data_layout; 4848 struct mlx5_ifc_eth_3635_cntrs_grp_data_layout_bits eth_3635_cntrs_grp_data_layout; 4849 struct mlx5_ifc_eth_extended_cntrs_grp_data_layout_bits eth_extended_cntrs_grp_data_layout; 4850 struct mlx5_ifc_eth_per_prio_grp_data_layout_bits eth_per_prio_grp_data_layout; 4851 struct mlx5_ifc_eth_per_tc_prio_grp_data_layout_bits eth_per_tc_prio_grp_data_layout; 4852 struct mlx5_ifc_eth_per_tc_congest_prio_grp_data_layout_bits eth_per_tc_congest_prio_grp_data_layout; 4853 struct mlx5_ifc_ib_port_cntrs_grp_data_layout_bits ib_port_cntrs_grp_data_layout; 4854 struct mlx5_ifc_ib_ext_port_cntrs_grp_data_layout_bits ib_ext_port_cntrs_grp_data_layout; 4855 struct mlx5_ifc_phys_layer_cntrs_bits phys_layer_cntrs; 4856 struct mlx5_ifc_phys_layer_statistical_cntrs_bits phys_layer_statistical_cntrs; 4857 struct mlx5_ifc_phys_layer_recovery_cntrs_bits phys_layer_recovery_cntrs; 4858 u8 reserved_at_0[0x7c0]; 4859 }; 4860 4861 union mlx5_ifc_pcie_cntrs_grp_data_layout_auto_bits { 4862 struct mlx5_ifc_pcie_perf_cntrs_grp_data_layout_bits pcie_perf_cntrs_grp_data_layout; 4863 u8 reserved_at_0[0x7c0]; 4864 }; 4865 4866 union mlx5_ifc_event_auto_bits { 4867 struct mlx5_ifc_comp_event_bits comp_event; 4868 struct mlx5_ifc_dct_events_bits dct_events; 4869 struct mlx5_ifc_qp_events_bits qp_events; 4870 struct mlx5_ifc_wqe_associated_page_fault_event_bits wqe_associated_page_fault_event; 4871 struct mlx5_ifc_rdma_page_fault_event_bits rdma_page_fault_event; 4872 struct mlx5_ifc_cq_error_bits cq_error; 4873 struct mlx5_ifc_dropped_packet_logged_bits dropped_packet_logged; 4874 struct mlx5_ifc_port_state_change_event_bits port_state_change_event; 4875 struct mlx5_ifc_gpio_event_bits gpio_event; 4876 struct mlx5_ifc_db_bf_congestion_event_bits db_bf_congestion_event; 4877 struct mlx5_ifc_stall_vl_event_bits stall_vl_event; 4878 struct mlx5_ifc_cmd_inter_comp_event_bits cmd_inter_comp_event; 4879 u8 reserved_at_0[0xe0]; 4880 }; 4881 4882 struct mlx5_ifc_health_buffer_bits { 4883 u8 reserved_at_0[0x100]; 4884 4885 u8 assert_existptr[0x20]; 4886 4887 u8 assert_callra[0x20]; 4888 4889 u8 reserved_at_140[0x20]; 4890 4891 u8 time[0x20]; 4892 4893 u8 fw_version[0x20]; 4894 4895 u8 hw_id[0x20]; 4896 4897 u8 rfr[0x1]; 4898 u8 reserved_at_1c1[0x3]; 4899 u8 valid[0x1]; 4900 u8 severity[0x3]; 4901 u8 reserved_at_1c8[0x18]; 4902 4903 u8 irisc_index[0x8]; 4904 u8 synd[0x8]; 4905 u8 ext_synd[0x10]; 4906 }; 4907 4908 struct mlx5_ifc_register_loopback_control_bits { 4909 u8 no_lb[0x1]; 4910 u8 reserved_at_1[0x7]; 4911 u8 port[0x8]; 4912 u8 reserved_at_10[0x10]; 4913 4914 u8 reserved_at_20[0x60]; 4915 }; 4916 4917 enum { 4918 MLX5_TEARDOWN_HCA_OUT_FORCE_STATE_SUCCESS = 0x0, 4919 MLX5_TEARDOWN_HCA_OUT_FORCE_STATE_FAIL = 0x1, 4920 }; 4921 4922 struct mlx5_ifc_teardown_hca_out_bits { 4923 u8 status[0x8]; 4924 u8 reserved_at_8[0x18]; 4925 4926 u8 syndrome[0x20]; 4927 4928 u8 reserved_at_40[0x3f]; 4929 4930 u8 state[0x1]; 4931 }; 4932 4933 enum { 4934 MLX5_TEARDOWN_HCA_IN_PROFILE_GRACEFUL_CLOSE = 0x0, 4935 MLX5_TEARDOWN_HCA_IN_PROFILE_FORCE_CLOSE = 0x1, 4936 MLX5_TEARDOWN_HCA_IN_PROFILE_PREPARE_FAST_TEARDOWN = 0x2, 4937 }; 4938 4939 struct mlx5_ifc_teardown_hca_in_bits { 4940 u8 opcode[0x10]; 4941 u8 reserved_at_10[0x10]; 4942 4943 u8 reserved_at_20[0x10]; 4944 u8 op_mod[0x10]; 4945 4946 u8 reserved_at_40[0x10]; 4947 u8 profile[0x10]; 4948 4949 u8 reserved_at_60[0x20]; 4950 }; 4951 4952 struct mlx5_ifc_sqerr2rts_qp_out_bits { 4953 u8 status[0x8]; 4954 u8 reserved_at_8[0x18]; 4955 4956 u8 syndrome[0x20]; 4957 4958 u8 reserved_at_40[0x40]; 4959 }; 4960 4961 struct mlx5_ifc_sqerr2rts_qp_in_bits { 4962 u8 opcode[0x10]; 4963 u8 uid[0x10]; 4964 4965 u8 reserved_at_20[0x10]; 4966 u8 op_mod[0x10]; 4967 4968 u8 reserved_at_40[0x8]; 4969 u8 qpn[0x18]; 4970 4971 u8 reserved_at_60[0x20]; 4972 4973 u8 opt_param_mask[0x20]; 4974 4975 u8 reserved_at_a0[0x20]; 4976 4977 struct mlx5_ifc_qpc_bits qpc; 4978 4979 u8 reserved_at_800[0x80]; 4980 }; 4981 4982 struct mlx5_ifc_sqd2rts_qp_out_bits { 4983 u8 status[0x8]; 4984 u8 reserved_at_8[0x18]; 4985 4986 u8 syndrome[0x20]; 4987 4988 u8 reserved_at_40[0x40]; 4989 }; 4990 4991 struct mlx5_ifc_sqd2rts_qp_in_bits { 4992 u8 opcode[0x10]; 4993 u8 uid[0x10]; 4994 4995 u8 reserved_at_20[0x10]; 4996 u8 op_mod[0x10]; 4997 4998 u8 reserved_at_40[0x8]; 4999 u8 qpn[0x18]; 5000 5001 u8 reserved_at_60[0x20]; 5002 5003 u8 opt_param_mask[0x20]; 5004 5005 u8 reserved_at_a0[0x20]; 5006 5007 struct mlx5_ifc_qpc_bits qpc; 5008 5009 u8 reserved_at_800[0x80]; 5010 }; 5011 5012 struct mlx5_ifc_set_roce_address_out_bits { 5013 u8 status[0x8]; 5014 u8 reserved_at_8[0x18]; 5015 5016 u8 syndrome[0x20]; 5017 5018 u8 reserved_at_40[0x40]; 5019 }; 5020 5021 struct mlx5_ifc_set_roce_address_in_bits { 5022 u8 opcode[0x10]; 5023 u8 reserved_at_10[0x10]; 5024 5025 u8 reserved_at_20[0x10]; 5026 u8 op_mod[0x10]; 5027 5028 u8 roce_address_index[0x10]; 5029 u8 reserved_at_50[0xc]; 5030 u8 vhca_port_num[0x4]; 5031 5032 u8 reserved_at_60[0x20]; 5033 5034 struct mlx5_ifc_roce_addr_layout_bits roce_address; 5035 }; 5036 5037 struct mlx5_ifc_set_mad_demux_out_bits { 5038 u8 status[0x8]; 5039 u8 reserved_at_8[0x18]; 5040 5041 u8 syndrome[0x20]; 5042 5043 u8 reserved_at_40[0x40]; 5044 }; 5045 5046 enum { 5047 MLX5_SET_MAD_DEMUX_IN_DEMUX_MODE_PASS_ALL = 0x0, 5048 MLX5_SET_MAD_DEMUX_IN_DEMUX_MODE_SELECTIVE = 0x2, 5049 }; 5050 5051 struct mlx5_ifc_set_mad_demux_in_bits { 5052 u8 opcode[0x10]; 5053 u8 reserved_at_10[0x10]; 5054 5055 u8 reserved_at_20[0x10]; 5056 u8 op_mod[0x10]; 5057 5058 u8 reserved_at_40[0x20]; 5059 5060 u8 reserved_at_60[0x6]; 5061 u8 demux_mode[0x2]; 5062 u8 reserved_at_68[0x18]; 5063 }; 5064 5065 struct mlx5_ifc_set_l2_table_entry_out_bits { 5066 u8 status[0x8]; 5067 u8 reserved_at_8[0x18]; 5068 5069 u8 syndrome[0x20]; 5070 5071 u8 reserved_at_40[0x40]; 5072 }; 5073 5074 struct mlx5_ifc_set_l2_table_entry_in_bits { 5075 u8 opcode[0x10]; 5076 u8 reserved_at_10[0x10]; 5077 5078 u8 reserved_at_20[0x10]; 5079 u8 op_mod[0x10]; 5080 5081 u8 reserved_at_40[0x60]; 5082 5083 u8 reserved_at_a0[0x8]; 5084 u8 table_index[0x18]; 5085 5086 u8 reserved_at_c0[0x20]; 5087 5088 u8 reserved_at_e0[0x10]; 5089 u8 silent_mode_valid[0x1]; 5090 u8 silent_mode[0x1]; 5091 u8 reserved_at_f2[0x1]; 5092 u8 vlan_valid[0x1]; 5093 u8 vlan[0xc]; 5094 5095 struct mlx5_ifc_mac_address_layout_bits mac_address; 5096 5097 u8 reserved_at_140[0xc0]; 5098 }; 5099 5100 struct mlx5_ifc_set_issi_out_bits { 5101 u8 status[0x8]; 5102 u8 reserved_at_8[0x18]; 5103 5104 u8 syndrome[0x20]; 5105 5106 u8 reserved_at_40[0x40]; 5107 }; 5108 5109 struct mlx5_ifc_set_issi_in_bits { 5110 u8 opcode[0x10]; 5111 u8 reserved_at_10[0x10]; 5112 5113 u8 reserved_at_20[0x10]; 5114 u8 op_mod[0x10]; 5115 5116 u8 reserved_at_40[0x10]; 5117 u8 current_issi[0x10]; 5118 5119 u8 reserved_at_60[0x20]; 5120 }; 5121 5122 struct mlx5_ifc_set_hca_cap_out_bits { 5123 u8 status[0x8]; 5124 u8 reserved_at_8[0x18]; 5125 5126 u8 syndrome[0x20]; 5127 5128 u8 reserved_at_40[0x40]; 5129 }; 5130 5131 struct mlx5_ifc_set_hca_cap_in_bits { 5132 u8 opcode[0x10]; 5133 u8 reserved_at_10[0x10]; 5134 5135 u8 reserved_at_20[0x10]; 5136 u8 op_mod[0x10]; 5137 5138 u8 other_function[0x1]; 5139 u8 ec_vf_function[0x1]; 5140 u8 reserved_at_42[0xe]; 5141 u8 function_id[0x10]; 5142 5143 u8 reserved_at_60[0x20]; 5144 5145 union mlx5_ifc_hca_cap_union_bits capability; 5146 }; 5147 5148 enum { 5149 MLX5_SET_FTE_MODIFY_ENABLE_MASK_ACTION = 0x0, 5150 MLX5_SET_FTE_MODIFY_ENABLE_MASK_FLOW_TAG = 0x1, 5151 MLX5_SET_FTE_MODIFY_ENABLE_MASK_DESTINATION_LIST = 0x2, 5152 MLX5_SET_FTE_MODIFY_ENABLE_MASK_FLOW_COUNTERS = 0x3, 5153 MLX5_SET_FTE_MODIFY_ENABLE_MASK_IPSEC_OBJ_ID = 0x4 5154 }; 5155 5156 struct mlx5_ifc_set_fte_out_bits { 5157 u8 status[0x8]; 5158 u8 reserved_at_8[0x18]; 5159 5160 u8 syndrome[0x20]; 5161 5162 u8 reserved_at_40[0x40]; 5163 }; 5164 5165 struct mlx5_ifc_set_fte_in_bits { 5166 u8 opcode[0x10]; 5167 u8 reserved_at_10[0x10]; 5168 5169 u8 reserved_at_20[0x10]; 5170 u8 op_mod[0x10]; 5171 5172 u8 other_vport[0x1]; 5173 u8 reserved_at_41[0xf]; 5174 u8 vport_number[0x10]; 5175 5176 u8 reserved_at_60[0x20]; 5177 5178 u8 table_type[0x8]; 5179 u8 reserved_at_88[0x18]; 5180 5181 u8 reserved_at_a0[0x8]; 5182 u8 table_id[0x18]; 5183 5184 u8 ignore_flow_level[0x1]; 5185 u8 reserved_at_c1[0x17]; 5186 u8 modify_enable_mask[0x8]; 5187 5188 u8 reserved_at_e0[0x20]; 5189 5190 u8 flow_index[0x20]; 5191 5192 u8 reserved_at_120[0xe0]; 5193 5194 struct mlx5_ifc_flow_context_bits flow_context; 5195 }; 5196 5197 struct mlx5_ifc_dest_format_bits { 5198 u8 destination_type[0x8]; 5199 u8 destination_id[0x18]; 5200 5201 u8 destination_eswitch_owner_vhca_id_valid[0x1]; 5202 u8 packet_reformat[0x1]; 5203 u8 reserved_at_22[0xe]; 5204 u8 destination_eswitch_owner_vhca_id[0x10]; 5205 }; 5206 5207 struct mlx5_ifc_rts2rts_qp_out_bits { 5208 u8 status[0x8]; 5209 u8 reserved_at_8[0x18]; 5210 5211 u8 syndrome[0x20]; 5212 5213 u8 reserved_at_40[0x20]; 5214 u8 ece[0x20]; 5215 }; 5216 5217 struct mlx5_ifc_rts2rts_qp_in_bits { 5218 u8 opcode[0x10]; 5219 u8 uid[0x10]; 5220 5221 u8 reserved_at_20[0x10]; 5222 u8 op_mod[0x10]; 5223 5224 u8 reserved_at_40[0x8]; 5225 u8 qpn[0x18]; 5226 5227 u8 reserved_at_60[0x20]; 5228 5229 u8 opt_param_mask[0x20]; 5230 5231 u8 ece[0x20]; 5232 5233 struct mlx5_ifc_qpc_bits qpc; 5234 5235 u8 reserved_at_800[0x80]; 5236 }; 5237 5238 struct mlx5_ifc_rtr2rts_qp_out_bits { 5239 u8 status[0x8]; 5240 u8 reserved_at_8[0x18]; 5241 5242 u8 syndrome[0x20]; 5243 5244 u8 reserved_at_40[0x20]; 5245 u8 ece[0x20]; 5246 }; 5247 5248 struct mlx5_ifc_rtr2rts_qp_in_bits { 5249 u8 opcode[0x10]; 5250 u8 uid[0x10]; 5251 5252 u8 reserved_at_20[0x10]; 5253 u8 op_mod[0x10]; 5254 5255 u8 reserved_at_40[0x8]; 5256 u8 qpn[0x18]; 5257 5258 u8 reserved_at_60[0x20]; 5259 5260 u8 opt_param_mask[0x20]; 5261 5262 u8 ece[0x20]; 5263 5264 struct mlx5_ifc_qpc_bits qpc; 5265 5266 u8 reserved_at_800[0x80]; 5267 }; 5268 5269 struct mlx5_ifc_rst2init_qp_out_bits { 5270 u8 status[0x8]; 5271 u8 reserved_at_8[0x18]; 5272 5273 u8 syndrome[0x20]; 5274 5275 u8 reserved_at_40[0x20]; 5276 u8 ece[0x20]; 5277 }; 5278 5279 struct mlx5_ifc_rst2init_qp_in_bits { 5280 u8 opcode[0x10]; 5281 u8 uid[0x10]; 5282 5283 u8 reserved_at_20[0x10]; 5284 u8 op_mod[0x10]; 5285 5286 u8 reserved_at_40[0x8]; 5287 u8 qpn[0x18]; 5288 5289 u8 reserved_at_60[0x20]; 5290 5291 u8 opt_param_mask[0x20]; 5292 5293 u8 ece[0x20]; 5294 5295 struct mlx5_ifc_qpc_bits qpc; 5296 5297 u8 reserved_at_800[0x80]; 5298 }; 5299 5300 struct mlx5_ifc_query_xrq_out_bits { 5301 u8 status[0x8]; 5302 u8 reserved_at_8[0x18]; 5303 5304 u8 syndrome[0x20]; 5305 5306 u8 reserved_at_40[0x40]; 5307 5308 struct mlx5_ifc_xrqc_bits xrq_context; 5309 }; 5310 5311 struct mlx5_ifc_query_xrq_in_bits { 5312 u8 opcode[0x10]; 5313 u8 reserved_at_10[0x10]; 5314 5315 u8 reserved_at_20[0x10]; 5316 u8 op_mod[0x10]; 5317 5318 u8 reserved_at_40[0x8]; 5319 u8 xrqn[0x18]; 5320 5321 u8 reserved_at_60[0x20]; 5322 }; 5323 5324 struct mlx5_ifc_query_xrc_srq_out_bits { 5325 u8 status[0x8]; 5326 u8 reserved_at_8[0x18]; 5327 5328 u8 syndrome[0x20]; 5329 5330 u8 reserved_at_40[0x40]; 5331 5332 struct mlx5_ifc_xrc_srqc_bits xrc_srq_context_entry; 5333 5334 u8 reserved_at_280[0x600]; 5335 5336 u8 pas[][0x40]; 5337 }; 5338 5339 struct mlx5_ifc_query_xrc_srq_in_bits { 5340 u8 opcode[0x10]; 5341 u8 reserved_at_10[0x10]; 5342 5343 u8 reserved_at_20[0x10]; 5344 u8 op_mod[0x10]; 5345 5346 u8 reserved_at_40[0x8]; 5347 u8 xrc_srqn[0x18]; 5348 5349 u8 reserved_at_60[0x20]; 5350 }; 5351 5352 enum { 5353 MLX5_QUERY_VPORT_STATE_OUT_STATE_DOWN = 0x0, 5354 MLX5_QUERY_VPORT_STATE_OUT_STATE_UP = 0x1, 5355 }; 5356 5357 struct mlx5_ifc_query_vport_state_out_bits { 5358 u8 status[0x8]; 5359 u8 reserved_at_8[0x18]; 5360 5361 u8 syndrome[0x20]; 5362 5363 u8 reserved_at_40[0x20]; 5364 5365 u8 reserved_at_60[0x18]; 5366 u8 admin_state[0x4]; 5367 u8 state[0x4]; 5368 }; 5369 5370 struct mlx5_ifc_array1024_auto_bits { 5371 u8 array1024_auto[32][0x20]; 5372 }; 5373 5374 struct mlx5_ifc_query_vuid_in_bits { 5375 u8 opcode[0x10]; 5376 u8 uid[0x10]; 5377 5378 u8 reserved_at_20[0x40]; 5379 5380 u8 query_vfs_vuid[0x1]; 5381 u8 data_direct[0x1]; 5382 u8 reserved_at_62[0xe]; 5383 u8 vhca_id[0x10]; 5384 }; 5385 5386 struct mlx5_ifc_query_vuid_out_bits { 5387 u8 status[0x8]; 5388 u8 reserved_at_8[0x18]; 5389 5390 u8 syndrome[0x20]; 5391 5392 u8 reserved_at_40[0x1a0]; 5393 5394 u8 reserved_at_1e0[0x10]; 5395 u8 num_of_entries[0x10]; 5396 5397 struct mlx5_ifc_array1024_auto_bits vuid[]; 5398 }; 5399 5400 enum { 5401 MLX5_VPORT_STATE_OP_MOD_VNIC_VPORT = 0x0, 5402 MLX5_VPORT_STATE_OP_MOD_ESW_VPORT = 0x1, 5403 MLX5_VPORT_STATE_OP_MOD_UPLINK = 0x2, 5404 }; 5405 5406 struct mlx5_ifc_arm_monitor_counter_in_bits { 5407 u8 opcode[0x10]; 5408 u8 uid[0x10]; 5409 5410 u8 reserved_at_20[0x10]; 5411 u8 op_mod[0x10]; 5412 5413 u8 reserved_at_40[0x20]; 5414 5415 u8 reserved_at_60[0x20]; 5416 }; 5417 5418 struct mlx5_ifc_arm_monitor_counter_out_bits { 5419 u8 status[0x8]; 5420 u8 reserved_at_8[0x18]; 5421 5422 u8 syndrome[0x20]; 5423 5424 u8 reserved_at_40[0x40]; 5425 }; 5426 5427 enum { 5428 MLX5_QUERY_MONITOR_CNT_TYPE_PPCNT = 0x0, 5429 MLX5_QUERY_MONITOR_CNT_TYPE_Q_COUNTER = 0x1, 5430 }; 5431 5432 enum mlx5_monitor_counter_ppcnt { 5433 MLX5_QUERY_MONITOR_PPCNT_IN_RANGE_LENGTH_ERRORS = 0x0, 5434 MLX5_QUERY_MONITOR_PPCNT_OUT_OF_RANGE_LENGTH_FIELD = 0x1, 5435 MLX5_QUERY_MONITOR_PPCNT_FRAME_TOO_LONG_ERRORS = 0x2, 5436 MLX5_QUERY_MONITOR_PPCNT_FRAME_CHECK_SEQUENCE_ERRORS = 0x3, 5437 MLX5_QUERY_MONITOR_PPCNT_ALIGNMENT_ERRORS = 0x4, 5438 MLX5_QUERY_MONITOR_PPCNT_IF_OUT_DISCARDS = 0x5, 5439 }; 5440 5441 enum { 5442 MLX5_QUERY_MONITOR_Q_COUNTER_RX_OUT_OF_BUFFER = 0x4, 5443 }; 5444 5445 struct mlx5_ifc_monitor_counter_output_bits { 5446 u8 reserved_at_0[0x4]; 5447 u8 type[0x4]; 5448 u8 reserved_at_8[0x8]; 5449 u8 counter[0x10]; 5450 5451 u8 counter_group_id[0x20]; 5452 }; 5453 5454 #define MLX5_CMD_SET_MONITOR_NUM_PPCNT_COUNTER_SET1 (6) 5455 #define MLX5_CMD_SET_MONITOR_NUM_Q_COUNTERS_SET1 (1) 5456 #define MLX5_CMD_SET_MONITOR_NUM_COUNTER (MLX5_CMD_SET_MONITOR_NUM_PPCNT_COUNTER_SET1 +\ 5457 MLX5_CMD_SET_MONITOR_NUM_Q_COUNTERS_SET1) 5458 5459 struct mlx5_ifc_set_monitor_counter_in_bits { 5460 u8 opcode[0x10]; 5461 u8 uid[0x10]; 5462 5463 u8 reserved_at_20[0x10]; 5464 u8 op_mod[0x10]; 5465 5466 u8 reserved_at_40[0x10]; 5467 u8 num_of_counters[0x10]; 5468 5469 u8 reserved_at_60[0x20]; 5470 5471 struct mlx5_ifc_monitor_counter_output_bits monitor_counter[MLX5_CMD_SET_MONITOR_NUM_COUNTER]; 5472 }; 5473 5474 struct mlx5_ifc_set_monitor_counter_out_bits { 5475 u8 status[0x8]; 5476 u8 reserved_at_8[0x18]; 5477 5478 u8 syndrome[0x20]; 5479 5480 u8 reserved_at_40[0x40]; 5481 }; 5482 5483 struct mlx5_ifc_query_vport_state_in_bits { 5484 u8 opcode[0x10]; 5485 u8 reserved_at_10[0x10]; 5486 5487 u8 reserved_at_20[0x10]; 5488 u8 op_mod[0x10]; 5489 5490 u8 other_vport[0x1]; 5491 u8 reserved_at_41[0xf]; 5492 u8 vport_number[0x10]; 5493 5494 u8 reserved_at_60[0x20]; 5495 }; 5496 5497 struct mlx5_ifc_query_vnic_env_out_bits { 5498 u8 status[0x8]; 5499 u8 reserved_at_8[0x18]; 5500 5501 u8 syndrome[0x20]; 5502 5503 u8 reserved_at_40[0x40]; 5504 5505 struct mlx5_ifc_vnic_diagnostic_statistics_bits vport_env; 5506 }; 5507 5508 enum { 5509 MLX5_QUERY_VNIC_ENV_IN_OP_MOD_VPORT_DIAG_STATISTICS = 0x0, 5510 }; 5511 5512 struct mlx5_ifc_query_vnic_env_in_bits { 5513 u8 opcode[0x10]; 5514 u8 reserved_at_10[0x10]; 5515 5516 u8 reserved_at_20[0x10]; 5517 u8 op_mod[0x10]; 5518 5519 u8 other_vport[0x1]; 5520 u8 reserved_at_41[0xf]; 5521 u8 vport_number[0x10]; 5522 5523 u8 reserved_at_60[0x20]; 5524 }; 5525 5526 struct mlx5_ifc_query_vport_counter_out_bits { 5527 u8 status[0x8]; 5528 u8 reserved_at_8[0x18]; 5529 5530 u8 syndrome[0x20]; 5531 5532 u8 reserved_at_40[0x40]; 5533 5534 struct mlx5_ifc_traffic_counter_bits received_errors; 5535 5536 struct mlx5_ifc_traffic_counter_bits transmit_errors; 5537 5538 struct mlx5_ifc_traffic_counter_bits received_ib_unicast; 5539 5540 struct mlx5_ifc_traffic_counter_bits transmitted_ib_unicast; 5541 5542 struct mlx5_ifc_traffic_counter_bits received_ib_multicast; 5543 5544 struct mlx5_ifc_traffic_counter_bits transmitted_ib_multicast; 5545 5546 struct mlx5_ifc_traffic_counter_bits received_eth_broadcast; 5547 5548 struct mlx5_ifc_traffic_counter_bits transmitted_eth_broadcast; 5549 5550 struct mlx5_ifc_traffic_counter_bits received_eth_unicast; 5551 5552 struct mlx5_ifc_traffic_counter_bits transmitted_eth_unicast; 5553 5554 struct mlx5_ifc_traffic_counter_bits received_eth_multicast; 5555 5556 struct mlx5_ifc_traffic_counter_bits transmitted_eth_multicast; 5557 5558 struct mlx5_ifc_traffic_counter_bits local_loopback; 5559 5560 u8 reserved_at_700[0x980]; 5561 }; 5562 5563 enum { 5564 MLX5_QUERY_VPORT_COUNTER_IN_OP_MOD_VPORT_COUNTERS = 0x0, 5565 }; 5566 5567 struct mlx5_ifc_query_vport_counter_in_bits { 5568 u8 opcode[0x10]; 5569 u8 reserved_at_10[0x10]; 5570 5571 u8 reserved_at_20[0x10]; 5572 u8 op_mod[0x10]; 5573 5574 u8 other_vport[0x1]; 5575 u8 reserved_at_41[0xb]; 5576 u8 port_num[0x4]; 5577 u8 vport_number[0x10]; 5578 5579 u8 reserved_at_60[0x60]; 5580 5581 u8 clear[0x1]; 5582 u8 reserved_at_c1[0x1f]; 5583 5584 u8 reserved_at_e0[0x20]; 5585 }; 5586 5587 struct mlx5_ifc_query_tis_out_bits { 5588 u8 status[0x8]; 5589 u8 reserved_at_8[0x18]; 5590 5591 u8 syndrome[0x20]; 5592 5593 u8 reserved_at_40[0x40]; 5594 5595 struct mlx5_ifc_tisc_bits tis_context; 5596 }; 5597 5598 struct mlx5_ifc_query_tis_in_bits { 5599 u8 opcode[0x10]; 5600 u8 reserved_at_10[0x10]; 5601 5602 u8 reserved_at_20[0x10]; 5603 u8 op_mod[0x10]; 5604 5605 u8 reserved_at_40[0x8]; 5606 u8 tisn[0x18]; 5607 5608 u8 reserved_at_60[0x20]; 5609 }; 5610 5611 struct mlx5_ifc_query_tir_out_bits { 5612 u8 status[0x8]; 5613 u8 reserved_at_8[0x18]; 5614 5615 u8 syndrome[0x20]; 5616 5617 u8 reserved_at_40[0xc0]; 5618 5619 struct mlx5_ifc_tirc_bits tir_context; 5620 }; 5621 5622 struct mlx5_ifc_query_tir_in_bits { 5623 u8 opcode[0x10]; 5624 u8 reserved_at_10[0x10]; 5625 5626 u8 reserved_at_20[0x10]; 5627 u8 op_mod[0x10]; 5628 5629 u8 reserved_at_40[0x8]; 5630 u8 tirn[0x18]; 5631 5632 u8 reserved_at_60[0x20]; 5633 }; 5634 5635 struct mlx5_ifc_query_srq_out_bits { 5636 u8 status[0x8]; 5637 u8 reserved_at_8[0x18]; 5638 5639 u8 syndrome[0x20]; 5640 5641 u8 reserved_at_40[0x40]; 5642 5643 struct mlx5_ifc_srqc_bits srq_context_entry; 5644 5645 u8 reserved_at_280[0x600]; 5646 5647 u8 pas[][0x40]; 5648 }; 5649 5650 struct mlx5_ifc_query_srq_in_bits { 5651 u8 opcode[0x10]; 5652 u8 reserved_at_10[0x10]; 5653 5654 u8 reserved_at_20[0x10]; 5655 u8 op_mod[0x10]; 5656 5657 u8 reserved_at_40[0x8]; 5658 u8 srqn[0x18]; 5659 5660 u8 reserved_at_60[0x20]; 5661 }; 5662 5663 struct mlx5_ifc_query_sq_out_bits { 5664 u8 status[0x8]; 5665 u8 reserved_at_8[0x18]; 5666 5667 u8 syndrome[0x20]; 5668 5669 u8 reserved_at_40[0xc0]; 5670 5671 struct mlx5_ifc_sqc_bits sq_context; 5672 }; 5673 5674 struct mlx5_ifc_query_sq_in_bits { 5675 u8 opcode[0x10]; 5676 u8 reserved_at_10[0x10]; 5677 5678 u8 reserved_at_20[0x10]; 5679 u8 op_mod[0x10]; 5680 5681 u8 reserved_at_40[0x8]; 5682 u8 sqn[0x18]; 5683 5684 u8 reserved_at_60[0x20]; 5685 }; 5686 5687 struct mlx5_ifc_query_special_contexts_out_bits { 5688 u8 status[0x8]; 5689 u8 reserved_at_8[0x18]; 5690 5691 u8 syndrome[0x20]; 5692 5693 u8 dump_fill_mkey[0x20]; 5694 5695 u8 resd_lkey[0x20]; 5696 5697 u8 null_mkey[0x20]; 5698 5699 u8 terminate_scatter_list_mkey[0x20]; 5700 5701 u8 repeated_mkey[0x20]; 5702 5703 u8 reserved_at_a0[0x20]; 5704 }; 5705 5706 struct mlx5_ifc_query_special_contexts_in_bits { 5707 u8 opcode[0x10]; 5708 u8 reserved_at_10[0x10]; 5709 5710 u8 reserved_at_20[0x10]; 5711 u8 op_mod[0x10]; 5712 5713 u8 reserved_at_40[0x40]; 5714 }; 5715 5716 struct mlx5_ifc_query_scheduling_element_out_bits { 5717 u8 opcode[0x10]; 5718 u8 reserved_at_10[0x10]; 5719 5720 u8 reserved_at_20[0x10]; 5721 u8 op_mod[0x10]; 5722 5723 u8 reserved_at_40[0xc0]; 5724 5725 struct mlx5_ifc_scheduling_context_bits scheduling_context; 5726 5727 u8 reserved_at_300[0x100]; 5728 }; 5729 5730 enum { 5731 SCHEDULING_HIERARCHY_E_SWITCH = 0x2, 5732 SCHEDULING_HIERARCHY_NIC = 0x3, 5733 }; 5734 5735 struct mlx5_ifc_query_scheduling_element_in_bits { 5736 u8 opcode[0x10]; 5737 u8 reserved_at_10[0x10]; 5738 5739 u8 reserved_at_20[0x10]; 5740 u8 op_mod[0x10]; 5741 5742 u8 scheduling_hierarchy[0x8]; 5743 u8 reserved_at_48[0x18]; 5744 5745 u8 scheduling_element_id[0x20]; 5746 5747 u8 reserved_at_80[0x180]; 5748 }; 5749 5750 struct mlx5_ifc_query_rqt_out_bits { 5751 u8 status[0x8]; 5752 u8 reserved_at_8[0x18]; 5753 5754 u8 syndrome[0x20]; 5755 5756 u8 reserved_at_40[0xc0]; 5757 5758 struct mlx5_ifc_rqtc_bits rqt_context; 5759 }; 5760 5761 struct mlx5_ifc_query_rqt_in_bits { 5762 u8 opcode[0x10]; 5763 u8 reserved_at_10[0x10]; 5764 5765 u8 reserved_at_20[0x10]; 5766 u8 op_mod[0x10]; 5767 5768 u8 reserved_at_40[0x8]; 5769 u8 rqtn[0x18]; 5770 5771 u8 reserved_at_60[0x20]; 5772 }; 5773 5774 struct mlx5_ifc_query_rq_out_bits { 5775 u8 status[0x8]; 5776 u8 reserved_at_8[0x18]; 5777 5778 u8 syndrome[0x20]; 5779 5780 u8 reserved_at_40[0xc0]; 5781 5782 struct mlx5_ifc_rqc_bits rq_context; 5783 }; 5784 5785 struct mlx5_ifc_query_rq_in_bits { 5786 u8 opcode[0x10]; 5787 u8 reserved_at_10[0x10]; 5788 5789 u8 reserved_at_20[0x10]; 5790 u8 op_mod[0x10]; 5791 5792 u8 reserved_at_40[0x8]; 5793 u8 rqn[0x18]; 5794 5795 u8 reserved_at_60[0x20]; 5796 }; 5797 5798 struct mlx5_ifc_query_roce_address_out_bits { 5799 u8 status[0x8]; 5800 u8 reserved_at_8[0x18]; 5801 5802 u8 syndrome[0x20]; 5803 5804 u8 reserved_at_40[0x40]; 5805 5806 struct mlx5_ifc_roce_addr_layout_bits roce_address; 5807 }; 5808 5809 struct mlx5_ifc_query_roce_address_in_bits { 5810 u8 opcode[0x10]; 5811 u8 reserved_at_10[0x10]; 5812 5813 u8 reserved_at_20[0x10]; 5814 u8 op_mod[0x10]; 5815 5816 u8 roce_address_index[0x10]; 5817 u8 reserved_at_50[0xc]; 5818 u8 vhca_port_num[0x4]; 5819 5820 u8 reserved_at_60[0x20]; 5821 }; 5822 5823 struct mlx5_ifc_query_rmp_out_bits { 5824 u8 status[0x8]; 5825 u8 reserved_at_8[0x18]; 5826 5827 u8 syndrome[0x20]; 5828 5829 u8 reserved_at_40[0xc0]; 5830 5831 struct mlx5_ifc_rmpc_bits rmp_context; 5832 }; 5833 5834 struct mlx5_ifc_query_rmp_in_bits { 5835 u8 opcode[0x10]; 5836 u8 reserved_at_10[0x10]; 5837 5838 u8 reserved_at_20[0x10]; 5839 u8 op_mod[0x10]; 5840 5841 u8 reserved_at_40[0x8]; 5842 u8 rmpn[0x18]; 5843 5844 u8 reserved_at_60[0x20]; 5845 }; 5846 5847 struct mlx5_ifc_cqe_error_syndrome_bits { 5848 u8 hw_error_syndrome[0x8]; 5849 u8 hw_syndrome_type[0x4]; 5850 u8 reserved_at_c[0x4]; 5851 u8 vendor_error_syndrome[0x8]; 5852 u8 syndrome[0x8]; 5853 }; 5854 5855 struct mlx5_ifc_qp_context_extension_bits { 5856 u8 reserved_at_0[0x60]; 5857 5858 struct mlx5_ifc_cqe_error_syndrome_bits error_syndrome; 5859 5860 u8 reserved_at_80[0x580]; 5861 }; 5862 5863 struct mlx5_ifc_qpc_extension_and_pas_list_in_bits { 5864 struct mlx5_ifc_qp_context_extension_bits qpc_data_extension; 5865 5866 u8 pas[0][0x40]; 5867 }; 5868 5869 struct mlx5_ifc_qp_pas_list_in_bits { 5870 struct mlx5_ifc_cmd_pas_bits pas[0]; 5871 }; 5872 5873 union mlx5_ifc_qp_pas_or_qpc_ext_and_pas_bits { 5874 struct mlx5_ifc_qp_pas_list_in_bits qp_pas_list; 5875 struct mlx5_ifc_qpc_extension_and_pas_list_in_bits qpc_ext_and_pas_list; 5876 }; 5877 5878 struct mlx5_ifc_query_qp_out_bits { 5879 u8 status[0x8]; 5880 u8 reserved_at_8[0x18]; 5881 5882 u8 syndrome[0x20]; 5883 5884 u8 reserved_at_40[0x40]; 5885 5886 u8 opt_param_mask[0x20]; 5887 5888 u8 ece[0x20]; 5889 5890 struct mlx5_ifc_qpc_bits qpc; 5891 5892 u8 reserved_at_800[0x80]; 5893 5894 union mlx5_ifc_qp_pas_or_qpc_ext_and_pas_bits qp_pas_or_qpc_ext_and_pas; 5895 }; 5896 5897 struct mlx5_ifc_query_qp_in_bits { 5898 u8 opcode[0x10]; 5899 u8 reserved_at_10[0x10]; 5900 5901 u8 reserved_at_20[0x10]; 5902 u8 op_mod[0x10]; 5903 5904 u8 qpc_ext[0x1]; 5905 u8 reserved_at_41[0x7]; 5906 u8 qpn[0x18]; 5907 5908 u8 reserved_at_60[0x20]; 5909 }; 5910 5911 struct mlx5_ifc_query_q_counter_out_bits { 5912 u8 status[0x8]; 5913 u8 reserved_at_8[0x18]; 5914 5915 u8 syndrome[0x20]; 5916 5917 u8 reserved_at_40[0x40]; 5918 5919 u8 rx_write_requests[0x20]; 5920 5921 u8 reserved_at_a0[0x20]; 5922 5923 u8 rx_read_requests[0x20]; 5924 5925 u8 reserved_at_e0[0x20]; 5926 5927 u8 rx_atomic_requests[0x20]; 5928 5929 u8 reserved_at_120[0x20]; 5930 5931 u8 rx_dct_connect[0x20]; 5932 5933 u8 reserved_at_160[0x20]; 5934 5935 u8 out_of_buffer[0x20]; 5936 5937 u8 reserved_at_1a0[0x20]; 5938 5939 u8 out_of_sequence[0x20]; 5940 5941 u8 reserved_at_1e0[0x20]; 5942 5943 u8 duplicate_request[0x20]; 5944 5945 u8 reserved_at_220[0x20]; 5946 5947 u8 rnr_nak_retry_err[0x20]; 5948 5949 u8 reserved_at_260[0x20]; 5950 5951 u8 packet_seq_err[0x20]; 5952 5953 u8 reserved_at_2a0[0x20]; 5954 5955 u8 implied_nak_seq_err[0x20]; 5956 5957 u8 reserved_at_2e0[0x20]; 5958 5959 u8 local_ack_timeout_err[0x20]; 5960 5961 u8 reserved_at_320[0x60]; 5962 5963 u8 req_rnr_retries_exceeded[0x20]; 5964 5965 u8 reserved_at_3a0[0x20]; 5966 5967 u8 resp_local_length_error[0x20]; 5968 5969 u8 req_local_length_error[0x20]; 5970 5971 u8 resp_local_qp_error[0x20]; 5972 5973 u8 local_operation_error[0x20]; 5974 5975 u8 resp_local_protection[0x20]; 5976 5977 u8 req_local_protection[0x20]; 5978 5979 u8 resp_cqe_error[0x20]; 5980 5981 u8 req_cqe_error[0x20]; 5982 5983 u8 req_mw_binding[0x20]; 5984 5985 u8 req_bad_response[0x20]; 5986 5987 u8 req_remote_invalid_request[0x20]; 5988 5989 u8 resp_remote_invalid_request[0x20]; 5990 5991 u8 req_remote_access_errors[0x20]; 5992 5993 u8 resp_remote_access_errors[0x20]; 5994 5995 u8 req_remote_operation_errors[0x20]; 5996 5997 u8 req_transport_retries_exceeded[0x20]; 5998 5999 u8 cq_overflow[0x20]; 6000 6001 u8 resp_cqe_flush_error[0x20]; 6002 6003 u8 req_cqe_flush_error[0x20]; 6004 6005 u8 reserved_at_620[0x20]; 6006 6007 u8 roce_adp_retrans[0x20]; 6008 6009 u8 roce_adp_retrans_to[0x20]; 6010 6011 u8 roce_slow_restart[0x20]; 6012 6013 u8 roce_slow_restart_cnps[0x20]; 6014 6015 u8 roce_slow_restart_trans[0x20]; 6016 6017 u8 reserved_at_6e0[0x120]; 6018 }; 6019 6020 struct mlx5_ifc_query_q_counter_in_bits { 6021 u8 opcode[0x10]; 6022 u8 reserved_at_10[0x10]; 6023 6024 u8 reserved_at_20[0x10]; 6025 u8 op_mod[0x10]; 6026 6027 u8 other_vport[0x1]; 6028 u8 reserved_at_41[0xf]; 6029 u8 vport_number[0x10]; 6030 6031 u8 reserved_at_60[0x60]; 6032 6033 u8 clear[0x1]; 6034 u8 aggregate[0x1]; 6035 u8 reserved_at_c2[0x1e]; 6036 6037 u8 reserved_at_e0[0x18]; 6038 u8 counter_set_id[0x8]; 6039 }; 6040 6041 struct mlx5_ifc_query_pages_out_bits { 6042 u8 status[0x8]; 6043 u8 reserved_at_8[0x18]; 6044 6045 u8 syndrome[0x20]; 6046 6047 u8 embedded_cpu_function[0x1]; 6048 u8 reserved_at_41[0xf]; 6049 u8 function_id[0x10]; 6050 6051 u8 num_pages[0x20]; 6052 }; 6053 6054 enum { 6055 MLX5_QUERY_PAGES_IN_OP_MOD_BOOT_PAGES = 0x1, 6056 MLX5_QUERY_PAGES_IN_OP_MOD_INIT_PAGES = 0x2, 6057 MLX5_QUERY_PAGES_IN_OP_MOD_REGULAR_PAGES = 0x3, 6058 }; 6059 6060 struct mlx5_ifc_query_pages_in_bits { 6061 u8 opcode[0x10]; 6062 u8 reserved_at_10[0x10]; 6063 6064 u8 reserved_at_20[0x10]; 6065 u8 op_mod[0x10]; 6066 6067 u8 embedded_cpu_function[0x1]; 6068 u8 reserved_at_41[0xf]; 6069 u8 function_id[0x10]; 6070 6071 u8 reserved_at_60[0x20]; 6072 }; 6073 6074 struct mlx5_ifc_query_nic_vport_context_out_bits { 6075 u8 status[0x8]; 6076 u8 reserved_at_8[0x18]; 6077 6078 u8 syndrome[0x20]; 6079 6080 u8 reserved_at_40[0x40]; 6081 6082 struct mlx5_ifc_nic_vport_context_bits nic_vport_context; 6083 }; 6084 6085 struct mlx5_ifc_query_nic_vport_context_in_bits { 6086 u8 opcode[0x10]; 6087 u8 reserved_at_10[0x10]; 6088 6089 u8 reserved_at_20[0x10]; 6090 u8 op_mod[0x10]; 6091 6092 u8 other_vport[0x1]; 6093 u8 reserved_at_41[0xf]; 6094 u8 vport_number[0x10]; 6095 6096 u8 reserved_at_60[0x5]; 6097 u8 allowed_list_type[0x3]; 6098 u8 reserved_at_68[0x18]; 6099 }; 6100 6101 struct mlx5_ifc_query_mkey_out_bits { 6102 u8 status[0x8]; 6103 u8 reserved_at_8[0x18]; 6104 6105 u8 syndrome[0x20]; 6106 6107 u8 reserved_at_40[0x40]; 6108 6109 struct mlx5_ifc_mkc_bits memory_key_mkey_entry; 6110 6111 u8 reserved_at_280[0x600]; 6112 6113 u8 bsf0_klm0_pas_mtt0_1[16][0x8]; 6114 6115 u8 bsf1_klm1_pas_mtt2_3[16][0x8]; 6116 }; 6117 6118 struct mlx5_ifc_query_mkey_in_bits { 6119 u8 opcode[0x10]; 6120 u8 reserved_at_10[0x10]; 6121 6122 u8 reserved_at_20[0x10]; 6123 u8 op_mod[0x10]; 6124 6125 u8 reserved_at_40[0x8]; 6126 u8 mkey_index[0x18]; 6127 6128 u8 pg_access[0x1]; 6129 u8 reserved_at_61[0x1f]; 6130 }; 6131 6132 struct mlx5_ifc_query_mad_demux_out_bits { 6133 u8 status[0x8]; 6134 u8 reserved_at_8[0x18]; 6135 6136 u8 syndrome[0x20]; 6137 6138 u8 reserved_at_40[0x40]; 6139 6140 u8 mad_dumux_parameters_block[0x20]; 6141 }; 6142 6143 struct mlx5_ifc_query_mad_demux_in_bits { 6144 u8 opcode[0x10]; 6145 u8 reserved_at_10[0x10]; 6146 6147 u8 reserved_at_20[0x10]; 6148 u8 op_mod[0x10]; 6149 6150 u8 reserved_at_40[0x40]; 6151 }; 6152 6153 struct mlx5_ifc_query_l2_table_entry_out_bits { 6154 u8 status[0x8]; 6155 u8 reserved_at_8[0x18]; 6156 6157 u8 syndrome[0x20]; 6158 6159 u8 reserved_at_40[0xa0]; 6160 6161 u8 reserved_at_e0[0x13]; 6162 u8 vlan_valid[0x1]; 6163 u8 vlan[0xc]; 6164 6165 struct mlx5_ifc_mac_address_layout_bits mac_address; 6166 6167 u8 reserved_at_140[0xc0]; 6168 }; 6169 6170 struct mlx5_ifc_query_l2_table_entry_in_bits { 6171 u8 opcode[0x10]; 6172 u8 reserved_at_10[0x10]; 6173 6174 u8 reserved_at_20[0x10]; 6175 u8 op_mod[0x10]; 6176 6177 u8 reserved_at_40[0x60]; 6178 6179 u8 reserved_at_a0[0x8]; 6180 u8 table_index[0x18]; 6181 6182 u8 reserved_at_c0[0x140]; 6183 }; 6184 6185 struct mlx5_ifc_query_issi_out_bits { 6186 u8 status[0x8]; 6187 u8 reserved_at_8[0x18]; 6188 6189 u8 syndrome[0x20]; 6190 6191 u8 reserved_at_40[0x10]; 6192 u8 current_issi[0x10]; 6193 6194 u8 reserved_at_60[0xa0]; 6195 6196 u8 reserved_at_100[76][0x8]; 6197 u8 supported_issi_dw0[0x20]; 6198 }; 6199 6200 struct mlx5_ifc_query_issi_in_bits { 6201 u8 opcode[0x10]; 6202 u8 reserved_at_10[0x10]; 6203 6204 u8 reserved_at_20[0x10]; 6205 u8 op_mod[0x10]; 6206 6207 u8 reserved_at_40[0x40]; 6208 }; 6209 6210 struct mlx5_ifc_set_driver_version_out_bits { 6211 u8 status[0x8]; 6212 u8 reserved_0[0x18]; 6213 6214 u8 syndrome[0x20]; 6215 u8 reserved_1[0x40]; 6216 }; 6217 6218 struct mlx5_ifc_set_driver_version_in_bits { 6219 u8 opcode[0x10]; 6220 u8 reserved_0[0x10]; 6221 6222 u8 reserved_1[0x10]; 6223 u8 op_mod[0x10]; 6224 6225 u8 reserved_2[0x40]; 6226 u8 driver_version[64][0x8]; 6227 }; 6228 6229 struct mlx5_ifc_query_hca_vport_pkey_out_bits { 6230 u8 status[0x8]; 6231 u8 reserved_at_8[0x18]; 6232 6233 u8 syndrome[0x20]; 6234 6235 u8 reserved_at_40[0x40]; 6236 6237 struct mlx5_ifc_pkey_bits pkey[]; 6238 }; 6239 6240 struct mlx5_ifc_query_hca_vport_pkey_in_bits { 6241 u8 opcode[0x10]; 6242 u8 reserved_at_10[0x10]; 6243 6244 u8 reserved_at_20[0x10]; 6245 u8 op_mod[0x10]; 6246 6247 u8 other_vport[0x1]; 6248 u8 reserved_at_41[0xb]; 6249 u8 port_num[0x4]; 6250 u8 vport_number[0x10]; 6251 6252 u8 reserved_at_60[0x10]; 6253 u8 pkey_index[0x10]; 6254 }; 6255 6256 enum { 6257 MLX5_HCA_VPORT_SEL_PORT_GUID = 1 << 0, 6258 MLX5_HCA_VPORT_SEL_NODE_GUID = 1 << 1, 6259 MLX5_HCA_VPORT_SEL_STATE_POLICY = 1 << 2, 6260 }; 6261 6262 struct mlx5_ifc_query_hca_vport_gid_out_bits { 6263 u8 status[0x8]; 6264 u8 reserved_at_8[0x18]; 6265 6266 u8 syndrome[0x20]; 6267 6268 u8 reserved_at_40[0x20]; 6269 6270 u8 gids_num[0x10]; 6271 u8 reserved_at_70[0x10]; 6272 6273 struct mlx5_ifc_array128_auto_bits gid[]; 6274 }; 6275 6276 struct mlx5_ifc_query_hca_vport_gid_in_bits { 6277 u8 opcode[0x10]; 6278 u8 reserved_at_10[0x10]; 6279 6280 u8 reserved_at_20[0x10]; 6281 u8 op_mod[0x10]; 6282 6283 u8 other_vport[0x1]; 6284 u8 reserved_at_41[0xb]; 6285 u8 port_num[0x4]; 6286 u8 vport_number[0x10]; 6287 6288 u8 reserved_at_60[0x10]; 6289 u8 gid_index[0x10]; 6290 }; 6291 6292 struct mlx5_ifc_query_hca_vport_context_out_bits { 6293 u8 status[0x8]; 6294 u8 reserved_at_8[0x18]; 6295 6296 u8 syndrome[0x20]; 6297 6298 u8 reserved_at_40[0x40]; 6299 6300 struct mlx5_ifc_hca_vport_context_bits hca_vport_context; 6301 }; 6302 6303 struct mlx5_ifc_query_hca_vport_context_in_bits { 6304 u8 opcode[0x10]; 6305 u8 reserved_at_10[0x10]; 6306 6307 u8 reserved_at_20[0x10]; 6308 u8 op_mod[0x10]; 6309 6310 u8 other_vport[0x1]; 6311 u8 reserved_at_41[0xb]; 6312 u8 port_num[0x4]; 6313 u8 vport_number[0x10]; 6314 6315 u8 reserved_at_60[0x20]; 6316 }; 6317 6318 struct mlx5_ifc_query_hca_cap_out_bits { 6319 u8 status[0x8]; 6320 u8 reserved_at_8[0x18]; 6321 6322 u8 syndrome[0x20]; 6323 6324 u8 reserved_at_40[0x40]; 6325 6326 union mlx5_ifc_hca_cap_union_bits capability; 6327 }; 6328 6329 struct mlx5_ifc_query_hca_cap_in_bits { 6330 u8 opcode[0x10]; 6331 u8 reserved_at_10[0x10]; 6332 6333 u8 reserved_at_20[0x10]; 6334 u8 op_mod[0x10]; 6335 6336 u8 other_function[0x1]; 6337 u8 ec_vf_function[0x1]; 6338 u8 reserved_at_42[0xe]; 6339 u8 function_id[0x10]; 6340 6341 u8 reserved_at_60[0x20]; 6342 }; 6343 6344 struct mlx5_ifc_other_hca_cap_bits { 6345 u8 roce[0x1]; 6346 u8 reserved_at_1[0x27f]; 6347 }; 6348 6349 struct mlx5_ifc_query_other_hca_cap_out_bits { 6350 u8 status[0x8]; 6351 u8 reserved_at_8[0x18]; 6352 6353 u8 syndrome[0x20]; 6354 6355 u8 reserved_at_40[0x40]; 6356 6357 struct mlx5_ifc_other_hca_cap_bits other_capability; 6358 }; 6359 6360 struct mlx5_ifc_query_other_hca_cap_in_bits { 6361 u8 opcode[0x10]; 6362 u8 reserved_at_10[0x10]; 6363 6364 u8 reserved_at_20[0x10]; 6365 u8 op_mod[0x10]; 6366 6367 u8 reserved_at_40[0x10]; 6368 u8 function_id[0x10]; 6369 6370 u8 reserved_at_60[0x20]; 6371 }; 6372 6373 struct mlx5_ifc_modify_other_hca_cap_out_bits { 6374 u8 status[0x8]; 6375 u8 reserved_at_8[0x18]; 6376 6377 u8 syndrome[0x20]; 6378 6379 u8 reserved_at_40[0x40]; 6380 }; 6381 6382 struct mlx5_ifc_modify_other_hca_cap_in_bits { 6383 u8 opcode[0x10]; 6384 u8 reserved_at_10[0x10]; 6385 6386 u8 reserved_at_20[0x10]; 6387 u8 op_mod[0x10]; 6388 6389 u8 reserved_at_40[0x10]; 6390 u8 function_id[0x10]; 6391 u8 field_select[0x20]; 6392 6393 struct mlx5_ifc_other_hca_cap_bits other_capability; 6394 }; 6395 6396 struct mlx5_ifc_sw_owner_icm_root_params_bits { 6397 u8 sw_owner_icm_root_1[0x40]; 6398 6399 u8 sw_owner_icm_root_0[0x40]; 6400 }; 6401 6402 struct mlx5_ifc_rtc_params_bits { 6403 u8 rtc_id_0[0x20]; 6404 6405 u8 rtc_id_1[0x20]; 6406 6407 u8 reserved_at_40[0x40]; 6408 }; 6409 6410 struct mlx5_ifc_flow_table_context_bits { 6411 u8 reformat_en[0x1]; 6412 u8 decap_en[0x1]; 6413 u8 sw_owner[0x1]; 6414 u8 termination_table[0x1]; 6415 u8 table_miss_action[0x4]; 6416 u8 level[0x8]; 6417 u8 rtc_valid[0x1]; 6418 u8 reserved_at_11[0x7]; 6419 u8 log_size[0x8]; 6420 6421 u8 reserved_at_20[0x8]; 6422 u8 table_miss_id[0x18]; 6423 6424 u8 reserved_at_40[0x8]; 6425 u8 lag_master_next_table_id[0x18]; 6426 6427 u8 reserved_at_60[0x60]; 6428 6429 union { 6430 struct mlx5_ifc_sw_owner_icm_root_params_bits sws; 6431 struct mlx5_ifc_rtc_params_bits hws; 6432 }; 6433 }; 6434 6435 struct mlx5_ifc_query_flow_table_out_bits { 6436 u8 status[0x8]; 6437 u8 reserved_at_8[0x18]; 6438 6439 u8 syndrome[0x20]; 6440 6441 u8 reserved_at_40[0x80]; 6442 6443 struct mlx5_ifc_flow_table_context_bits flow_table_context; 6444 }; 6445 6446 struct mlx5_ifc_query_flow_table_in_bits { 6447 u8 opcode[0x10]; 6448 u8 reserved_at_10[0x10]; 6449 6450 u8 reserved_at_20[0x10]; 6451 u8 op_mod[0x10]; 6452 6453 u8 reserved_at_40[0x40]; 6454 6455 u8 table_type[0x8]; 6456 u8 reserved_at_88[0x18]; 6457 6458 u8 reserved_at_a0[0x8]; 6459 u8 table_id[0x18]; 6460 6461 u8 reserved_at_c0[0x140]; 6462 }; 6463 6464 struct mlx5_ifc_query_fte_out_bits { 6465 u8 status[0x8]; 6466 u8 reserved_at_8[0x18]; 6467 6468 u8 syndrome[0x20]; 6469 6470 u8 reserved_at_40[0x1c0]; 6471 6472 struct mlx5_ifc_flow_context_bits flow_context; 6473 }; 6474 6475 struct mlx5_ifc_query_fte_in_bits { 6476 u8 opcode[0x10]; 6477 u8 reserved_at_10[0x10]; 6478 6479 u8 reserved_at_20[0x10]; 6480 u8 op_mod[0x10]; 6481 6482 u8 reserved_at_40[0x40]; 6483 6484 u8 table_type[0x8]; 6485 u8 reserved_at_88[0x18]; 6486 6487 u8 reserved_at_a0[0x8]; 6488 u8 table_id[0x18]; 6489 6490 u8 reserved_at_c0[0x40]; 6491 6492 u8 flow_index[0x20]; 6493 6494 u8 reserved_at_120[0xe0]; 6495 }; 6496 6497 struct mlx5_ifc_match_definer_format_0_bits { 6498 u8 reserved_at_0[0x100]; 6499 6500 u8 metadata_reg_c_0[0x20]; 6501 6502 u8 metadata_reg_c_1[0x20]; 6503 6504 u8 outer_dmac_47_16[0x20]; 6505 6506 u8 outer_dmac_15_0[0x10]; 6507 u8 outer_ethertype[0x10]; 6508 6509 u8 reserved_at_180[0x1]; 6510 u8 sx_sniffer[0x1]; 6511 u8 functional_lb[0x1]; 6512 u8 outer_ip_frag[0x1]; 6513 u8 outer_qp_type[0x2]; 6514 u8 outer_encap_type[0x2]; 6515 u8 port_number[0x2]; 6516 u8 outer_l3_type[0x2]; 6517 u8 outer_l4_type[0x2]; 6518 u8 outer_first_vlan_type[0x2]; 6519 u8 outer_first_vlan_prio[0x3]; 6520 u8 outer_first_vlan_cfi[0x1]; 6521 u8 outer_first_vlan_vid[0xc]; 6522 6523 u8 outer_l4_type_ext[0x4]; 6524 u8 reserved_at_1a4[0x2]; 6525 u8 outer_ipsec_layer[0x2]; 6526 u8 outer_l2_type[0x2]; 6527 u8 force_lb[0x1]; 6528 u8 outer_l2_ok[0x1]; 6529 u8 outer_l3_ok[0x1]; 6530 u8 outer_l4_ok[0x1]; 6531 u8 outer_second_vlan_type[0x2]; 6532 u8 outer_second_vlan_prio[0x3]; 6533 u8 outer_second_vlan_cfi[0x1]; 6534 u8 outer_second_vlan_vid[0xc]; 6535 6536 u8 outer_smac_47_16[0x20]; 6537 6538 u8 outer_smac_15_0[0x10]; 6539 u8 inner_ipv4_checksum_ok[0x1]; 6540 u8 inner_l4_checksum_ok[0x1]; 6541 u8 outer_ipv4_checksum_ok[0x1]; 6542 u8 outer_l4_checksum_ok[0x1]; 6543 u8 inner_l3_ok[0x1]; 6544 u8 inner_l4_ok[0x1]; 6545 u8 outer_l3_ok_duplicate[0x1]; 6546 u8 outer_l4_ok_duplicate[0x1]; 6547 u8 outer_tcp_cwr[0x1]; 6548 u8 outer_tcp_ece[0x1]; 6549 u8 outer_tcp_urg[0x1]; 6550 u8 outer_tcp_ack[0x1]; 6551 u8 outer_tcp_psh[0x1]; 6552 u8 outer_tcp_rst[0x1]; 6553 u8 outer_tcp_syn[0x1]; 6554 u8 outer_tcp_fin[0x1]; 6555 }; 6556 6557 struct mlx5_ifc_match_definer_format_22_bits { 6558 u8 reserved_at_0[0x100]; 6559 6560 u8 outer_ip_src_addr[0x20]; 6561 6562 u8 outer_ip_dest_addr[0x20]; 6563 6564 u8 outer_l4_sport[0x10]; 6565 u8 outer_l4_dport[0x10]; 6566 6567 u8 reserved_at_160[0x1]; 6568 u8 sx_sniffer[0x1]; 6569 u8 functional_lb[0x1]; 6570 u8 outer_ip_frag[0x1]; 6571 u8 outer_qp_type[0x2]; 6572 u8 outer_encap_type[0x2]; 6573 u8 port_number[0x2]; 6574 u8 outer_l3_type[0x2]; 6575 u8 outer_l4_type[0x2]; 6576 u8 outer_first_vlan_type[0x2]; 6577 u8 outer_first_vlan_prio[0x3]; 6578 u8 outer_first_vlan_cfi[0x1]; 6579 u8 outer_first_vlan_vid[0xc]; 6580 6581 u8 metadata_reg_c_0[0x20]; 6582 6583 u8 outer_dmac_47_16[0x20]; 6584 6585 u8 outer_smac_47_16[0x20]; 6586 6587 u8 outer_smac_15_0[0x10]; 6588 u8 outer_dmac_15_0[0x10]; 6589 }; 6590 6591 struct mlx5_ifc_match_definer_format_23_bits { 6592 u8 reserved_at_0[0x100]; 6593 6594 u8 inner_ip_src_addr[0x20]; 6595 6596 u8 inner_ip_dest_addr[0x20]; 6597 6598 u8 inner_l4_sport[0x10]; 6599 u8 inner_l4_dport[0x10]; 6600 6601 u8 reserved_at_160[0x1]; 6602 u8 sx_sniffer[0x1]; 6603 u8 functional_lb[0x1]; 6604 u8 inner_ip_frag[0x1]; 6605 u8 inner_qp_type[0x2]; 6606 u8 inner_encap_type[0x2]; 6607 u8 port_number[0x2]; 6608 u8 inner_l3_type[0x2]; 6609 u8 inner_l4_type[0x2]; 6610 u8 inner_first_vlan_type[0x2]; 6611 u8 inner_first_vlan_prio[0x3]; 6612 u8 inner_first_vlan_cfi[0x1]; 6613 u8 inner_first_vlan_vid[0xc]; 6614 6615 u8 tunnel_header_0[0x20]; 6616 6617 u8 inner_dmac_47_16[0x20]; 6618 6619 u8 inner_smac_47_16[0x20]; 6620 6621 u8 inner_smac_15_0[0x10]; 6622 u8 inner_dmac_15_0[0x10]; 6623 }; 6624 6625 struct mlx5_ifc_match_definer_format_29_bits { 6626 u8 reserved_at_0[0xc0]; 6627 6628 u8 outer_ip_dest_addr[0x80]; 6629 6630 u8 outer_ip_src_addr[0x80]; 6631 6632 u8 outer_l4_sport[0x10]; 6633 u8 outer_l4_dport[0x10]; 6634 6635 u8 reserved_at_1e0[0x20]; 6636 }; 6637 6638 struct mlx5_ifc_match_definer_format_30_bits { 6639 u8 reserved_at_0[0xa0]; 6640 6641 u8 outer_ip_dest_addr[0x80]; 6642 6643 u8 outer_ip_src_addr[0x80]; 6644 6645 u8 outer_dmac_47_16[0x20]; 6646 6647 u8 outer_smac_47_16[0x20]; 6648 6649 u8 outer_smac_15_0[0x10]; 6650 u8 outer_dmac_15_0[0x10]; 6651 }; 6652 6653 struct mlx5_ifc_match_definer_format_31_bits { 6654 u8 reserved_at_0[0xc0]; 6655 6656 u8 inner_ip_dest_addr[0x80]; 6657 6658 u8 inner_ip_src_addr[0x80]; 6659 6660 u8 inner_l4_sport[0x10]; 6661 u8 inner_l4_dport[0x10]; 6662 6663 u8 reserved_at_1e0[0x20]; 6664 }; 6665 6666 struct mlx5_ifc_match_definer_format_32_bits { 6667 u8 reserved_at_0[0xa0]; 6668 6669 u8 inner_ip_dest_addr[0x80]; 6670 6671 u8 inner_ip_src_addr[0x80]; 6672 6673 u8 inner_dmac_47_16[0x20]; 6674 6675 u8 inner_smac_47_16[0x20]; 6676 6677 u8 inner_smac_15_0[0x10]; 6678 u8 inner_dmac_15_0[0x10]; 6679 }; 6680 6681 enum { 6682 MLX5_IFC_DEFINER_FORMAT_ID_SELECT = 61, 6683 }; 6684 6685 #define MLX5_IFC_DEFINER_FORMAT_OFFSET_UNUSED 0x0 6686 #define MLX5_IFC_DEFINER_FORMAT_OFFSET_OUTER_ETH_PKT_LEN 0x48 6687 #define MLX5_IFC_DEFINER_DW_SELECTORS_NUM 9 6688 #define MLX5_IFC_DEFINER_BYTE_SELECTORS_NUM 8 6689 6690 struct mlx5_ifc_match_definer_match_mask_bits { 6691 u8 reserved_at_1c0[5][0x20]; 6692 u8 match_dw_8[0x20]; 6693 u8 match_dw_7[0x20]; 6694 u8 match_dw_6[0x20]; 6695 u8 match_dw_5[0x20]; 6696 u8 match_dw_4[0x20]; 6697 u8 match_dw_3[0x20]; 6698 u8 match_dw_2[0x20]; 6699 u8 match_dw_1[0x20]; 6700 u8 match_dw_0[0x20]; 6701 6702 u8 match_byte_7[0x8]; 6703 u8 match_byte_6[0x8]; 6704 u8 match_byte_5[0x8]; 6705 u8 match_byte_4[0x8]; 6706 6707 u8 match_byte_3[0x8]; 6708 u8 match_byte_2[0x8]; 6709 u8 match_byte_1[0x8]; 6710 u8 match_byte_0[0x8]; 6711 }; 6712 6713 struct mlx5_ifc_match_definer_bits { 6714 u8 modify_field_select[0x40]; 6715 6716 u8 reserved_at_40[0x40]; 6717 6718 u8 reserved_at_80[0x10]; 6719 u8 format_id[0x10]; 6720 6721 u8 reserved_at_a0[0x60]; 6722 6723 u8 format_select_dw3[0x8]; 6724 u8 format_select_dw2[0x8]; 6725 u8 format_select_dw1[0x8]; 6726 u8 format_select_dw0[0x8]; 6727 6728 u8 format_select_dw7[0x8]; 6729 u8 format_select_dw6[0x8]; 6730 u8 format_select_dw5[0x8]; 6731 u8 format_select_dw4[0x8]; 6732 6733 u8 reserved_at_100[0x18]; 6734 u8 format_select_dw8[0x8]; 6735 6736 u8 reserved_at_120[0x20]; 6737 6738 u8 format_select_byte3[0x8]; 6739 u8 format_select_byte2[0x8]; 6740 u8 format_select_byte1[0x8]; 6741 u8 format_select_byte0[0x8]; 6742 6743 u8 format_select_byte7[0x8]; 6744 u8 format_select_byte6[0x8]; 6745 u8 format_select_byte5[0x8]; 6746 u8 format_select_byte4[0x8]; 6747 6748 u8 reserved_at_180[0x40]; 6749 6750 union { 6751 struct { 6752 u8 match_mask[16][0x20]; 6753 }; 6754 struct mlx5_ifc_match_definer_match_mask_bits match_mask_format; 6755 }; 6756 }; 6757 6758 struct mlx5_ifc_general_obj_create_param_bits { 6759 u8 alias_object[0x1]; 6760 u8 reserved_at_1[0x2]; 6761 u8 log_obj_range[0x5]; 6762 u8 reserved_at_8[0x18]; 6763 }; 6764 6765 struct mlx5_ifc_general_obj_query_param_bits { 6766 u8 alias_object[0x1]; 6767 u8 obj_offset[0x1f]; 6768 }; 6769 6770 struct mlx5_ifc_general_obj_in_cmd_hdr_bits { 6771 u8 opcode[0x10]; 6772 u8 uid[0x10]; 6773 6774 u8 vhca_tunnel_id[0x10]; 6775 u8 obj_type[0x10]; 6776 6777 u8 obj_id[0x20]; 6778 6779 union { 6780 struct mlx5_ifc_general_obj_create_param_bits create; 6781 struct mlx5_ifc_general_obj_query_param_bits query; 6782 } op_param; 6783 }; 6784 6785 struct mlx5_ifc_general_obj_out_cmd_hdr_bits { 6786 u8 status[0x8]; 6787 u8 reserved_at_8[0x18]; 6788 6789 u8 syndrome[0x20]; 6790 6791 u8 obj_id[0x20]; 6792 6793 u8 reserved_at_60[0x20]; 6794 }; 6795 6796 struct mlx5_ifc_allow_other_vhca_access_in_bits { 6797 u8 opcode[0x10]; 6798 u8 uid[0x10]; 6799 u8 reserved_at_20[0x10]; 6800 u8 op_mod[0x10]; 6801 u8 reserved_at_40[0x50]; 6802 u8 object_type_to_be_accessed[0x10]; 6803 u8 object_id_to_be_accessed[0x20]; 6804 u8 reserved_at_c0[0x40]; 6805 union { 6806 u8 access_key_raw[0x100]; 6807 u8 access_key[8][0x20]; 6808 }; 6809 }; 6810 6811 struct mlx5_ifc_allow_other_vhca_access_out_bits { 6812 u8 status[0x8]; 6813 u8 reserved_at_8[0x18]; 6814 u8 syndrome[0x20]; 6815 u8 reserved_at_40[0x40]; 6816 }; 6817 6818 struct mlx5_ifc_modify_header_arg_bits { 6819 u8 reserved_at_0[0x80]; 6820 6821 u8 reserved_at_80[0x8]; 6822 u8 access_pd[0x18]; 6823 }; 6824 6825 struct mlx5_ifc_create_modify_header_arg_in_bits { 6826 struct mlx5_ifc_general_obj_in_cmd_hdr_bits hdr; 6827 struct mlx5_ifc_modify_header_arg_bits arg; 6828 }; 6829 6830 struct mlx5_ifc_create_match_definer_in_bits { 6831 struct mlx5_ifc_general_obj_in_cmd_hdr_bits general_obj_in_cmd_hdr; 6832 6833 struct mlx5_ifc_match_definer_bits obj_context; 6834 }; 6835 6836 struct mlx5_ifc_create_match_definer_out_bits { 6837 struct mlx5_ifc_general_obj_out_cmd_hdr_bits general_obj_out_cmd_hdr; 6838 }; 6839 6840 struct mlx5_ifc_alias_context_bits { 6841 u8 vhca_id_to_be_accessed[0x10]; 6842 u8 reserved_at_10[0xd]; 6843 u8 status[0x3]; 6844 u8 object_id_to_be_accessed[0x20]; 6845 u8 reserved_at_40[0x40]; 6846 union { 6847 u8 access_key_raw[0x100]; 6848 u8 access_key[8][0x20]; 6849 }; 6850 u8 metadata[0x80]; 6851 }; 6852 6853 struct mlx5_ifc_create_alias_obj_in_bits { 6854 struct mlx5_ifc_general_obj_in_cmd_hdr_bits hdr; 6855 struct mlx5_ifc_alias_context_bits alias_ctx; 6856 }; 6857 6858 enum { 6859 MLX5_QUERY_FLOW_GROUP_OUT_MATCH_CRITERIA_ENABLE_OUTER_HEADERS = 0x0, 6860 MLX5_QUERY_FLOW_GROUP_OUT_MATCH_CRITERIA_ENABLE_MISC_PARAMETERS = 0x1, 6861 MLX5_QUERY_FLOW_GROUP_OUT_MATCH_CRITERIA_ENABLE_INNER_HEADERS = 0x2, 6862 MLX5_QUERY_FLOW_GROUP_IN_MATCH_CRITERIA_ENABLE_MISC_PARAMETERS_2 = 0x3, 6863 MLX5_QUERY_FLOW_GROUP_IN_MATCH_CRITERIA_ENABLE_MISC_PARAMETERS_3 = 0x4, 6864 MLX5_QUERY_FLOW_GROUP_IN_MATCH_CRITERIA_ENABLE_MISC_PARAMETERS_4 = 0x5, 6865 MLX5_QUERY_FLOW_GROUP_IN_MATCH_CRITERIA_ENABLE_MISC_PARAMETERS_5 = 0x6, 6866 }; 6867 6868 struct mlx5_ifc_query_flow_group_out_bits { 6869 u8 status[0x8]; 6870 u8 reserved_at_8[0x18]; 6871 6872 u8 syndrome[0x20]; 6873 6874 u8 reserved_at_40[0xa0]; 6875 6876 u8 start_flow_index[0x20]; 6877 6878 u8 reserved_at_100[0x20]; 6879 6880 u8 end_flow_index[0x20]; 6881 6882 u8 reserved_at_140[0xa0]; 6883 6884 u8 reserved_at_1e0[0x18]; 6885 u8 match_criteria_enable[0x8]; 6886 6887 struct mlx5_ifc_fte_match_param_bits match_criteria; 6888 6889 u8 reserved_at_1200[0xe00]; 6890 }; 6891 6892 struct mlx5_ifc_query_flow_group_in_bits { 6893 u8 opcode[0x10]; 6894 u8 reserved_at_10[0x10]; 6895 6896 u8 reserved_at_20[0x10]; 6897 u8 op_mod[0x10]; 6898 6899 u8 reserved_at_40[0x40]; 6900 6901 u8 table_type[0x8]; 6902 u8 reserved_at_88[0x18]; 6903 6904 u8 reserved_at_a0[0x8]; 6905 u8 table_id[0x18]; 6906 6907 u8 group_id[0x20]; 6908 6909 u8 reserved_at_e0[0x120]; 6910 }; 6911 6912 struct mlx5_ifc_query_flow_counter_out_bits { 6913 u8 status[0x8]; 6914 u8 reserved_at_8[0x18]; 6915 6916 u8 syndrome[0x20]; 6917 6918 u8 reserved_at_40[0x40]; 6919 6920 struct mlx5_ifc_traffic_counter_bits flow_statistics[]; 6921 }; 6922 6923 struct mlx5_ifc_query_flow_counter_in_bits { 6924 u8 opcode[0x10]; 6925 u8 reserved_at_10[0x10]; 6926 6927 u8 reserved_at_20[0x10]; 6928 u8 op_mod[0x10]; 6929 6930 u8 reserved_at_40[0x80]; 6931 6932 u8 clear[0x1]; 6933 u8 reserved_at_c1[0xf]; 6934 u8 num_of_counters[0x10]; 6935 6936 u8 flow_counter_id[0x20]; 6937 }; 6938 6939 struct mlx5_ifc_query_esw_vport_context_out_bits { 6940 u8 status[0x8]; 6941 u8 reserved_at_8[0x18]; 6942 6943 u8 syndrome[0x20]; 6944 6945 u8 reserved_at_40[0x40]; 6946 6947 struct mlx5_ifc_esw_vport_context_bits esw_vport_context; 6948 }; 6949 6950 struct mlx5_ifc_query_esw_vport_context_in_bits { 6951 u8 opcode[0x10]; 6952 u8 reserved_at_10[0x10]; 6953 6954 u8 reserved_at_20[0x10]; 6955 u8 op_mod[0x10]; 6956 6957 u8 other_vport[0x1]; 6958 u8 reserved_at_41[0xf]; 6959 u8 vport_number[0x10]; 6960 6961 u8 reserved_at_60[0x20]; 6962 }; 6963 6964 struct mlx5_ifc_modify_esw_vport_context_out_bits { 6965 u8 status[0x8]; 6966 u8 reserved_at_8[0x18]; 6967 6968 u8 syndrome[0x20]; 6969 6970 u8 reserved_at_40[0x40]; 6971 }; 6972 6973 struct mlx5_ifc_esw_vport_context_fields_select_bits { 6974 u8 reserved_at_0[0x1b]; 6975 u8 fdb_to_vport_reg_c_id[0x1]; 6976 u8 vport_cvlan_insert[0x1]; 6977 u8 vport_svlan_insert[0x1]; 6978 u8 vport_cvlan_strip[0x1]; 6979 u8 vport_svlan_strip[0x1]; 6980 }; 6981 6982 struct mlx5_ifc_modify_esw_vport_context_in_bits { 6983 u8 opcode[0x10]; 6984 u8 reserved_at_10[0x10]; 6985 6986 u8 reserved_at_20[0x10]; 6987 u8 op_mod[0x10]; 6988 6989 u8 other_vport[0x1]; 6990 u8 reserved_at_41[0xf]; 6991 u8 vport_number[0x10]; 6992 6993 struct mlx5_ifc_esw_vport_context_fields_select_bits field_select; 6994 6995 struct mlx5_ifc_esw_vport_context_bits esw_vport_context; 6996 }; 6997 6998 struct mlx5_ifc_query_eq_out_bits { 6999 u8 status[0x8]; 7000 u8 reserved_at_8[0x18]; 7001 7002 u8 syndrome[0x20]; 7003 7004 u8 reserved_at_40[0x40]; 7005 7006 struct mlx5_ifc_eqc_bits eq_context_entry; 7007 7008 u8 reserved_at_280[0x40]; 7009 7010 u8 event_bitmask[0x40]; 7011 7012 u8 reserved_at_300[0x580]; 7013 7014 u8 pas[][0x40]; 7015 }; 7016 7017 struct mlx5_ifc_query_eq_in_bits { 7018 u8 opcode[0x10]; 7019 u8 reserved_at_10[0x10]; 7020 7021 u8 reserved_at_20[0x10]; 7022 u8 op_mod[0x10]; 7023 7024 u8 reserved_at_40[0x18]; 7025 u8 eq_number[0x8]; 7026 7027 u8 reserved_at_60[0x20]; 7028 }; 7029 7030 struct mlx5_ifc_packet_reformat_context_in_bits { 7031 u8 reformat_type[0x8]; 7032 u8 reserved_at_8[0x4]; 7033 u8 reformat_param_0[0x4]; 7034 u8 reserved_at_10[0x6]; 7035 u8 reformat_data_size[0xa]; 7036 7037 u8 reformat_param_1[0x8]; 7038 u8 reserved_at_28[0x8]; 7039 u8 reformat_data[2][0x8]; 7040 7041 u8 more_reformat_data[][0x8]; 7042 }; 7043 7044 struct mlx5_ifc_query_packet_reformat_context_out_bits { 7045 u8 status[0x8]; 7046 u8 reserved_at_8[0x18]; 7047 7048 u8 syndrome[0x20]; 7049 7050 u8 reserved_at_40[0xa0]; 7051 7052 struct mlx5_ifc_packet_reformat_context_in_bits packet_reformat_context[]; 7053 }; 7054 7055 struct mlx5_ifc_query_packet_reformat_context_in_bits { 7056 u8 opcode[0x10]; 7057 u8 reserved_at_10[0x10]; 7058 7059 u8 reserved_at_20[0x10]; 7060 u8 op_mod[0x10]; 7061 7062 u8 packet_reformat_id[0x20]; 7063 7064 u8 reserved_at_60[0xa0]; 7065 }; 7066 7067 struct mlx5_ifc_alloc_packet_reformat_context_out_bits { 7068 u8 status[0x8]; 7069 u8 reserved_at_8[0x18]; 7070 7071 u8 syndrome[0x20]; 7072 7073 u8 packet_reformat_id[0x20]; 7074 7075 u8 reserved_at_60[0x20]; 7076 }; 7077 7078 enum { 7079 MLX5_REFORMAT_CONTEXT_ANCHOR_MAC_START = 0x1, 7080 MLX5_REFORMAT_CONTEXT_ANCHOR_VLAN_START = 0x2, 7081 MLX5_REFORMAT_CONTEXT_ANCHOR_IP_START = 0x7, 7082 MLX5_REFORMAT_CONTEXT_ANCHOR_TCP_UDP_START = 0x9, 7083 }; 7084 7085 enum mlx5_reformat_ctx_type { 7086 MLX5_REFORMAT_TYPE_L2_TO_VXLAN = 0x0, 7087 MLX5_REFORMAT_TYPE_L2_TO_NVGRE = 0x1, 7088 MLX5_REFORMAT_TYPE_L2_TO_L2_TUNNEL = 0x2, 7089 MLX5_REFORMAT_TYPE_L3_TUNNEL_TO_L2 = 0x3, 7090 MLX5_REFORMAT_TYPE_L2_TO_L3_TUNNEL = 0x4, 7091 MLX5_REFORMAT_TYPE_ADD_ESP_TRANSPORT_OVER_IPV4 = 0x5, 7092 MLX5_REFORMAT_TYPE_L2_TO_L3_ESP_TUNNEL = 0x6, 7093 MLX5_REFORMAT_TYPE_ADD_ESP_TRANSPORT_OVER_UDPV4 = 0x7, 7094 MLX5_REFORMAT_TYPE_DEL_ESP_TRANSPORT = 0x8, 7095 MLX5_REFORMAT_TYPE_L3_ESP_TUNNEL_TO_L2 = 0x9, 7096 MLX5_REFORMAT_TYPE_DEL_ESP_TRANSPORT_OVER_UDP = 0xa, 7097 MLX5_REFORMAT_TYPE_ADD_ESP_TRANSPORT_OVER_IPV6 = 0xb, 7098 MLX5_REFORMAT_TYPE_ADD_ESP_TRANSPORT_OVER_UDPV6 = 0xc, 7099 MLX5_REFORMAT_TYPE_INSERT_HDR = 0xf, 7100 MLX5_REFORMAT_TYPE_REMOVE_HDR = 0x10, 7101 MLX5_REFORMAT_TYPE_ADD_MACSEC = 0x11, 7102 MLX5_REFORMAT_TYPE_DEL_MACSEC = 0x12, 7103 }; 7104 7105 struct mlx5_ifc_alloc_packet_reformat_context_in_bits { 7106 u8 opcode[0x10]; 7107 u8 reserved_at_10[0x10]; 7108 7109 u8 reserved_at_20[0x10]; 7110 u8 op_mod[0x10]; 7111 7112 u8 reserved_at_40[0xa0]; 7113 7114 struct mlx5_ifc_packet_reformat_context_in_bits packet_reformat_context; 7115 }; 7116 7117 struct mlx5_ifc_dealloc_packet_reformat_context_out_bits { 7118 u8 status[0x8]; 7119 u8 reserved_at_8[0x18]; 7120 7121 u8 syndrome[0x20]; 7122 7123 u8 reserved_at_40[0x40]; 7124 }; 7125 7126 struct mlx5_ifc_dealloc_packet_reformat_context_in_bits { 7127 u8 opcode[0x10]; 7128 u8 reserved_at_10[0x10]; 7129 7130 u8 reserved_20[0x10]; 7131 u8 op_mod[0x10]; 7132 7133 u8 packet_reformat_id[0x20]; 7134 7135 u8 reserved_60[0x20]; 7136 }; 7137 7138 struct mlx5_ifc_set_action_in_bits { 7139 u8 action_type[0x4]; 7140 u8 field[0xc]; 7141 u8 reserved_at_10[0x3]; 7142 u8 offset[0x5]; 7143 u8 reserved_at_18[0x3]; 7144 u8 length[0x5]; 7145 7146 u8 data[0x20]; 7147 }; 7148 7149 struct mlx5_ifc_add_action_in_bits { 7150 u8 action_type[0x4]; 7151 u8 field[0xc]; 7152 u8 reserved_at_10[0x10]; 7153 7154 u8 data[0x20]; 7155 }; 7156 7157 struct mlx5_ifc_copy_action_in_bits { 7158 u8 action_type[0x4]; 7159 u8 src_field[0xc]; 7160 u8 reserved_at_10[0x3]; 7161 u8 src_offset[0x5]; 7162 u8 reserved_at_18[0x3]; 7163 u8 length[0x5]; 7164 7165 u8 reserved_at_20[0x4]; 7166 u8 dst_field[0xc]; 7167 u8 reserved_at_30[0x3]; 7168 u8 dst_offset[0x5]; 7169 u8 reserved_at_38[0x8]; 7170 }; 7171 7172 union mlx5_ifc_set_add_copy_action_in_auto_bits { 7173 struct mlx5_ifc_set_action_in_bits set_action_in; 7174 struct mlx5_ifc_add_action_in_bits add_action_in; 7175 struct mlx5_ifc_copy_action_in_bits copy_action_in; 7176 u8 reserved_at_0[0x40]; 7177 }; 7178 7179 enum { 7180 MLX5_ACTION_TYPE_SET = 0x1, 7181 MLX5_ACTION_TYPE_ADD = 0x2, 7182 MLX5_ACTION_TYPE_COPY = 0x3, 7183 }; 7184 7185 enum { 7186 MLX5_ACTION_IN_FIELD_OUT_SMAC_47_16 = 0x1, 7187 MLX5_ACTION_IN_FIELD_OUT_SMAC_15_0 = 0x2, 7188 MLX5_ACTION_IN_FIELD_OUT_ETHERTYPE = 0x3, 7189 MLX5_ACTION_IN_FIELD_OUT_DMAC_47_16 = 0x4, 7190 MLX5_ACTION_IN_FIELD_OUT_DMAC_15_0 = 0x5, 7191 MLX5_ACTION_IN_FIELD_OUT_IP_DSCP = 0x6, 7192 MLX5_ACTION_IN_FIELD_OUT_TCP_FLAGS = 0x7, 7193 MLX5_ACTION_IN_FIELD_OUT_TCP_SPORT = 0x8, 7194 MLX5_ACTION_IN_FIELD_OUT_TCP_DPORT = 0x9, 7195 MLX5_ACTION_IN_FIELD_OUT_IP_TTL = 0xa, 7196 MLX5_ACTION_IN_FIELD_OUT_UDP_SPORT = 0xb, 7197 MLX5_ACTION_IN_FIELD_OUT_UDP_DPORT = 0xc, 7198 MLX5_ACTION_IN_FIELD_OUT_SIPV6_127_96 = 0xd, 7199 MLX5_ACTION_IN_FIELD_OUT_SIPV6_95_64 = 0xe, 7200 MLX5_ACTION_IN_FIELD_OUT_SIPV6_63_32 = 0xf, 7201 MLX5_ACTION_IN_FIELD_OUT_SIPV6_31_0 = 0x10, 7202 MLX5_ACTION_IN_FIELD_OUT_DIPV6_127_96 = 0x11, 7203 MLX5_ACTION_IN_FIELD_OUT_DIPV6_95_64 = 0x12, 7204 MLX5_ACTION_IN_FIELD_OUT_DIPV6_63_32 = 0x13, 7205 MLX5_ACTION_IN_FIELD_OUT_DIPV6_31_0 = 0x14, 7206 MLX5_ACTION_IN_FIELD_OUT_SIPV4 = 0x15, 7207 MLX5_ACTION_IN_FIELD_OUT_DIPV4 = 0x16, 7208 MLX5_ACTION_IN_FIELD_OUT_FIRST_VID = 0x17, 7209 MLX5_ACTION_IN_FIELD_OUT_IPV6_HOPLIMIT = 0x47, 7210 MLX5_ACTION_IN_FIELD_METADATA_REG_A = 0x49, 7211 MLX5_ACTION_IN_FIELD_METADATA_REG_B = 0x50, 7212 MLX5_ACTION_IN_FIELD_METADATA_REG_C_0 = 0x51, 7213 MLX5_ACTION_IN_FIELD_METADATA_REG_C_1 = 0x52, 7214 MLX5_ACTION_IN_FIELD_METADATA_REG_C_2 = 0x53, 7215 MLX5_ACTION_IN_FIELD_METADATA_REG_C_3 = 0x54, 7216 MLX5_ACTION_IN_FIELD_METADATA_REG_C_4 = 0x55, 7217 MLX5_ACTION_IN_FIELD_METADATA_REG_C_5 = 0x56, 7218 MLX5_ACTION_IN_FIELD_METADATA_REG_C_6 = 0x57, 7219 MLX5_ACTION_IN_FIELD_METADATA_REG_C_7 = 0x58, 7220 MLX5_ACTION_IN_FIELD_OUT_TCP_SEQ_NUM = 0x59, 7221 MLX5_ACTION_IN_FIELD_OUT_TCP_ACK_NUM = 0x5B, 7222 MLX5_ACTION_IN_FIELD_IPSEC_SYNDROME = 0x5D, 7223 MLX5_ACTION_IN_FIELD_OUT_EMD_47_32 = 0x6F, 7224 MLX5_ACTION_IN_FIELD_OUT_EMD_31_0 = 0x70, 7225 }; 7226 7227 struct mlx5_ifc_alloc_modify_header_context_out_bits { 7228 u8 status[0x8]; 7229 u8 reserved_at_8[0x18]; 7230 7231 u8 syndrome[0x20]; 7232 7233 u8 modify_header_id[0x20]; 7234 7235 u8 reserved_at_60[0x20]; 7236 }; 7237 7238 struct mlx5_ifc_alloc_modify_header_context_in_bits { 7239 u8 opcode[0x10]; 7240 u8 reserved_at_10[0x10]; 7241 7242 u8 reserved_at_20[0x10]; 7243 u8 op_mod[0x10]; 7244 7245 u8 reserved_at_40[0x20]; 7246 7247 u8 table_type[0x8]; 7248 u8 reserved_at_68[0x10]; 7249 u8 num_of_actions[0x8]; 7250 7251 union mlx5_ifc_set_add_copy_action_in_auto_bits actions[]; 7252 }; 7253 7254 struct mlx5_ifc_dealloc_modify_header_context_out_bits { 7255 u8 status[0x8]; 7256 u8 reserved_at_8[0x18]; 7257 7258 u8 syndrome[0x20]; 7259 7260 u8 reserved_at_40[0x40]; 7261 }; 7262 7263 struct mlx5_ifc_dealloc_modify_header_context_in_bits { 7264 u8 opcode[0x10]; 7265 u8 reserved_at_10[0x10]; 7266 7267 u8 reserved_at_20[0x10]; 7268 u8 op_mod[0x10]; 7269 7270 u8 modify_header_id[0x20]; 7271 7272 u8 reserved_at_60[0x20]; 7273 }; 7274 7275 struct mlx5_ifc_query_modify_header_context_in_bits { 7276 u8 opcode[0x10]; 7277 u8 uid[0x10]; 7278 7279 u8 reserved_at_20[0x10]; 7280 u8 op_mod[0x10]; 7281 7282 u8 modify_header_id[0x20]; 7283 7284 u8 reserved_at_60[0xa0]; 7285 }; 7286 7287 struct mlx5_ifc_query_dct_out_bits { 7288 u8 status[0x8]; 7289 u8 reserved_at_8[0x18]; 7290 7291 u8 syndrome[0x20]; 7292 7293 u8 reserved_at_40[0x40]; 7294 7295 struct mlx5_ifc_dctc_bits dct_context_entry; 7296 7297 u8 reserved_at_280[0x180]; 7298 }; 7299 7300 struct mlx5_ifc_query_dct_in_bits { 7301 u8 opcode[0x10]; 7302 u8 reserved_at_10[0x10]; 7303 7304 u8 reserved_at_20[0x10]; 7305 u8 op_mod[0x10]; 7306 7307 u8 reserved_at_40[0x8]; 7308 u8 dctn[0x18]; 7309 7310 u8 reserved_at_60[0x20]; 7311 }; 7312 7313 struct mlx5_ifc_query_cq_out_bits { 7314 u8 status[0x8]; 7315 u8 reserved_at_8[0x18]; 7316 7317 u8 syndrome[0x20]; 7318 7319 u8 reserved_at_40[0x40]; 7320 7321 struct mlx5_ifc_cqc_bits cq_context; 7322 7323 u8 reserved_at_280[0x600]; 7324 7325 u8 pas[][0x40]; 7326 }; 7327 7328 struct mlx5_ifc_query_cq_in_bits { 7329 u8 opcode[0x10]; 7330 u8 reserved_at_10[0x10]; 7331 7332 u8 reserved_at_20[0x10]; 7333 u8 op_mod[0x10]; 7334 7335 u8 reserved_at_40[0x8]; 7336 u8 cqn[0x18]; 7337 7338 u8 reserved_at_60[0x20]; 7339 }; 7340 7341 struct mlx5_ifc_query_cong_status_out_bits { 7342 u8 status[0x8]; 7343 u8 reserved_at_8[0x18]; 7344 7345 u8 syndrome[0x20]; 7346 7347 u8 reserved_at_40[0x20]; 7348 7349 u8 enable[0x1]; 7350 u8 tag_enable[0x1]; 7351 u8 reserved_at_62[0x1e]; 7352 }; 7353 7354 struct mlx5_ifc_query_cong_status_in_bits { 7355 u8 opcode[0x10]; 7356 u8 reserved_at_10[0x10]; 7357 7358 u8 reserved_at_20[0x10]; 7359 u8 op_mod[0x10]; 7360 7361 u8 reserved_at_40[0x18]; 7362 u8 priority[0x4]; 7363 u8 cong_protocol[0x4]; 7364 7365 u8 reserved_at_60[0x20]; 7366 }; 7367 7368 struct mlx5_ifc_query_cong_statistics_out_bits { 7369 u8 status[0x8]; 7370 u8 reserved_at_8[0x18]; 7371 7372 u8 syndrome[0x20]; 7373 7374 u8 reserved_at_40[0x40]; 7375 7376 u8 rp_cur_flows[0x20]; 7377 7378 u8 sum_flows[0x20]; 7379 7380 u8 rp_cnp_ignored_high[0x20]; 7381 7382 u8 rp_cnp_ignored_low[0x20]; 7383 7384 u8 rp_cnp_handled_high[0x20]; 7385 7386 u8 rp_cnp_handled_low[0x20]; 7387 7388 u8 reserved_at_140[0x100]; 7389 7390 u8 time_stamp_high[0x20]; 7391 7392 u8 time_stamp_low[0x20]; 7393 7394 u8 accumulators_period[0x20]; 7395 7396 u8 np_ecn_marked_roce_packets_high[0x20]; 7397 7398 u8 np_ecn_marked_roce_packets_low[0x20]; 7399 7400 u8 np_cnp_sent_high[0x20]; 7401 7402 u8 np_cnp_sent_low[0x20]; 7403 7404 u8 reserved_at_320[0x560]; 7405 }; 7406 7407 struct mlx5_ifc_query_cong_statistics_in_bits { 7408 u8 opcode[0x10]; 7409 u8 reserved_at_10[0x10]; 7410 7411 u8 reserved_at_20[0x10]; 7412 u8 op_mod[0x10]; 7413 7414 u8 clear[0x1]; 7415 u8 reserved_at_41[0x1f]; 7416 7417 u8 reserved_at_60[0x20]; 7418 }; 7419 7420 struct mlx5_ifc_query_cong_params_out_bits { 7421 u8 status[0x8]; 7422 u8 reserved_at_8[0x18]; 7423 7424 u8 syndrome[0x20]; 7425 7426 u8 reserved_at_40[0x40]; 7427 7428 union mlx5_ifc_cong_control_roce_ecn_auto_bits congestion_parameters; 7429 }; 7430 7431 struct mlx5_ifc_query_cong_params_in_bits { 7432 u8 opcode[0x10]; 7433 u8 reserved_at_10[0x10]; 7434 7435 u8 reserved_at_20[0x10]; 7436 u8 op_mod[0x10]; 7437 7438 u8 reserved_at_40[0x1c]; 7439 u8 cong_protocol[0x4]; 7440 7441 u8 reserved_at_60[0x20]; 7442 }; 7443 7444 struct mlx5_ifc_query_adapter_out_bits { 7445 u8 status[0x8]; 7446 u8 reserved_at_8[0x18]; 7447 7448 u8 syndrome[0x20]; 7449 7450 u8 reserved_at_40[0x40]; 7451 7452 struct mlx5_ifc_query_adapter_param_block_bits query_adapter_struct; 7453 }; 7454 7455 struct mlx5_ifc_query_adapter_in_bits { 7456 u8 opcode[0x10]; 7457 u8 reserved_at_10[0x10]; 7458 7459 u8 reserved_at_20[0x10]; 7460 u8 op_mod[0x10]; 7461 7462 u8 reserved_at_40[0x40]; 7463 }; 7464 7465 struct mlx5_ifc_qp_2rst_out_bits { 7466 u8 status[0x8]; 7467 u8 reserved_at_8[0x18]; 7468 7469 u8 syndrome[0x20]; 7470 7471 u8 reserved_at_40[0x40]; 7472 }; 7473 7474 struct mlx5_ifc_qp_2rst_in_bits { 7475 u8 opcode[0x10]; 7476 u8 uid[0x10]; 7477 7478 u8 reserved_at_20[0x10]; 7479 u8 op_mod[0x10]; 7480 7481 u8 reserved_at_40[0x8]; 7482 u8 qpn[0x18]; 7483 7484 u8 reserved_at_60[0x20]; 7485 }; 7486 7487 struct mlx5_ifc_qp_2err_out_bits { 7488 u8 status[0x8]; 7489 u8 reserved_at_8[0x18]; 7490 7491 u8 syndrome[0x20]; 7492 7493 u8 reserved_at_40[0x40]; 7494 }; 7495 7496 struct mlx5_ifc_qp_2err_in_bits { 7497 u8 opcode[0x10]; 7498 u8 uid[0x10]; 7499 7500 u8 reserved_at_20[0x10]; 7501 u8 op_mod[0x10]; 7502 7503 u8 reserved_at_40[0x8]; 7504 u8 qpn[0x18]; 7505 7506 u8 reserved_at_60[0x20]; 7507 }; 7508 7509 struct mlx5_ifc_trans_page_fault_info_bits { 7510 u8 error[0x1]; 7511 u8 reserved_at_1[0x4]; 7512 u8 page_fault_type[0x3]; 7513 u8 wq_number[0x18]; 7514 7515 u8 reserved_at_20[0x8]; 7516 u8 fault_token[0x18]; 7517 }; 7518 7519 struct mlx5_ifc_mem_page_fault_info_bits { 7520 u8 error[0x1]; 7521 u8 reserved_at_1[0xf]; 7522 u8 fault_token_47_32[0x10]; 7523 7524 u8 fault_token_31_0[0x20]; 7525 }; 7526 7527 union mlx5_ifc_page_fault_resume_in_page_fault_info_auto_bits { 7528 struct mlx5_ifc_trans_page_fault_info_bits trans_page_fault_info; 7529 struct mlx5_ifc_mem_page_fault_info_bits mem_page_fault_info; 7530 u8 reserved_at_0[0x40]; 7531 }; 7532 7533 struct mlx5_ifc_page_fault_resume_out_bits { 7534 u8 status[0x8]; 7535 u8 reserved_at_8[0x18]; 7536 7537 u8 syndrome[0x20]; 7538 7539 u8 reserved_at_40[0x40]; 7540 }; 7541 7542 struct mlx5_ifc_page_fault_resume_in_bits { 7543 u8 opcode[0x10]; 7544 u8 reserved_at_10[0x10]; 7545 7546 u8 reserved_at_20[0x10]; 7547 u8 op_mod[0x10]; 7548 7549 union mlx5_ifc_page_fault_resume_in_page_fault_info_auto_bits 7550 page_fault_info; 7551 }; 7552 7553 struct mlx5_ifc_nop_out_bits { 7554 u8 status[0x8]; 7555 u8 reserved_at_8[0x18]; 7556 7557 u8 syndrome[0x20]; 7558 7559 u8 reserved_at_40[0x40]; 7560 }; 7561 7562 struct mlx5_ifc_nop_in_bits { 7563 u8 opcode[0x10]; 7564 u8 reserved_at_10[0x10]; 7565 7566 u8 reserved_at_20[0x10]; 7567 u8 op_mod[0x10]; 7568 7569 u8 reserved_at_40[0x40]; 7570 }; 7571 7572 struct mlx5_ifc_modify_vport_state_out_bits { 7573 u8 status[0x8]; 7574 u8 reserved_at_8[0x18]; 7575 7576 u8 syndrome[0x20]; 7577 7578 u8 reserved_at_40[0x40]; 7579 }; 7580 7581 struct mlx5_ifc_modify_vport_state_in_bits { 7582 u8 opcode[0x10]; 7583 u8 reserved_at_10[0x10]; 7584 7585 u8 reserved_at_20[0x10]; 7586 u8 op_mod[0x10]; 7587 7588 u8 other_vport[0x1]; 7589 u8 reserved_at_41[0xf]; 7590 u8 vport_number[0x10]; 7591 7592 u8 reserved_at_60[0x18]; 7593 u8 admin_state[0x4]; 7594 u8 reserved_at_7c[0x4]; 7595 }; 7596 7597 struct mlx5_ifc_modify_tis_out_bits { 7598 u8 status[0x8]; 7599 u8 reserved_at_8[0x18]; 7600 7601 u8 syndrome[0x20]; 7602 7603 u8 reserved_at_40[0x40]; 7604 }; 7605 7606 struct mlx5_ifc_modify_tis_bitmask_bits { 7607 u8 reserved_at_0[0x20]; 7608 7609 u8 reserved_at_20[0x1d]; 7610 u8 lag_tx_port_affinity[0x1]; 7611 u8 strict_lag_tx_port_affinity[0x1]; 7612 u8 prio[0x1]; 7613 }; 7614 7615 struct mlx5_ifc_modify_tis_in_bits { 7616 u8 opcode[0x10]; 7617 u8 uid[0x10]; 7618 7619 u8 reserved_at_20[0x10]; 7620 u8 op_mod[0x10]; 7621 7622 u8 reserved_at_40[0x8]; 7623 u8 tisn[0x18]; 7624 7625 u8 reserved_at_60[0x20]; 7626 7627 struct mlx5_ifc_modify_tis_bitmask_bits bitmask; 7628 7629 u8 reserved_at_c0[0x40]; 7630 7631 struct mlx5_ifc_tisc_bits ctx; 7632 }; 7633 7634 struct mlx5_ifc_modify_tir_bitmask_bits { 7635 u8 reserved_at_0[0x20]; 7636 7637 u8 reserved_at_20[0x1b]; 7638 u8 self_lb_en[0x1]; 7639 u8 reserved_at_3c[0x1]; 7640 u8 hash[0x1]; 7641 u8 reserved_at_3e[0x1]; 7642 u8 packet_merge[0x1]; 7643 }; 7644 7645 struct mlx5_ifc_modify_tir_out_bits { 7646 u8 status[0x8]; 7647 u8 reserved_at_8[0x18]; 7648 7649 u8 syndrome[0x20]; 7650 7651 u8 reserved_at_40[0x40]; 7652 }; 7653 7654 struct mlx5_ifc_modify_tir_in_bits { 7655 u8 opcode[0x10]; 7656 u8 uid[0x10]; 7657 7658 u8 reserved_at_20[0x10]; 7659 u8 op_mod[0x10]; 7660 7661 u8 reserved_at_40[0x8]; 7662 u8 tirn[0x18]; 7663 7664 u8 reserved_at_60[0x20]; 7665 7666 struct mlx5_ifc_modify_tir_bitmask_bits bitmask; 7667 7668 u8 reserved_at_c0[0x40]; 7669 7670 struct mlx5_ifc_tirc_bits ctx; 7671 }; 7672 7673 struct mlx5_ifc_modify_sq_out_bits { 7674 u8 status[0x8]; 7675 u8 reserved_at_8[0x18]; 7676 7677 u8 syndrome[0x20]; 7678 7679 u8 reserved_at_40[0x40]; 7680 }; 7681 7682 struct mlx5_ifc_modify_sq_in_bits { 7683 u8 opcode[0x10]; 7684 u8 uid[0x10]; 7685 7686 u8 reserved_at_20[0x10]; 7687 u8 op_mod[0x10]; 7688 7689 u8 sq_state[0x4]; 7690 u8 reserved_at_44[0x4]; 7691 u8 sqn[0x18]; 7692 7693 u8 reserved_at_60[0x20]; 7694 7695 u8 modify_bitmask[0x40]; 7696 7697 u8 reserved_at_c0[0x40]; 7698 7699 struct mlx5_ifc_sqc_bits ctx; 7700 }; 7701 7702 struct mlx5_ifc_modify_scheduling_element_out_bits { 7703 u8 status[0x8]; 7704 u8 reserved_at_8[0x18]; 7705 7706 u8 syndrome[0x20]; 7707 7708 u8 reserved_at_40[0x1c0]; 7709 }; 7710 7711 enum { 7712 MODIFY_SCHEDULING_ELEMENT_IN_MODIFY_BITMASK_BW_SHARE = 0x1, 7713 MODIFY_SCHEDULING_ELEMENT_IN_MODIFY_BITMASK_MAX_AVERAGE_BW = 0x2, 7714 }; 7715 7716 struct mlx5_ifc_modify_scheduling_element_in_bits { 7717 u8 opcode[0x10]; 7718 u8 reserved_at_10[0x10]; 7719 7720 u8 reserved_at_20[0x10]; 7721 u8 op_mod[0x10]; 7722 7723 u8 scheduling_hierarchy[0x8]; 7724 u8 reserved_at_48[0x18]; 7725 7726 u8 scheduling_element_id[0x20]; 7727 7728 u8 reserved_at_80[0x20]; 7729 7730 u8 modify_bitmask[0x20]; 7731 7732 u8 reserved_at_c0[0x40]; 7733 7734 struct mlx5_ifc_scheduling_context_bits scheduling_context; 7735 7736 u8 reserved_at_300[0x100]; 7737 }; 7738 7739 struct mlx5_ifc_modify_rqt_out_bits { 7740 u8 status[0x8]; 7741 u8 reserved_at_8[0x18]; 7742 7743 u8 syndrome[0x20]; 7744 7745 u8 reserved_at_40[0x40]; 7746 }; 7747 7748 struct mlx5_ifc_rqt_bitmask_bits { 7749 u8 reserved_at_0[0x20]; 7750 7751 u8 reserved_at_20[0x1f]; 7752 u8 rqn_list[0x1]; 7753 }; 7754 7755 struct mlx5_ifc_modify_rqt_in_bits { 7756 u8 opcode[0x10]; 7757 u8 uid[0x10]; 7758 7759 u8 reserved_at_20[0x10]; 7760 u8 op_mod[0x10]; 7761 7762 u8 reserved_at_40[0x8]; 7763 u8 rqtn[0x18]; 7764 7765 u8 reserved_at_60[0x20]; 7766 7767 struct mlx5_ifc_rqt_bitmask_bits bitmask; 7768 7769 u8 reserved_at_c0[0x40]; 7770 7771 struct mlx5_ifc_rqtc_bits ctx; 7772 }; 7773 7774 struct mlx5_ifc_modify_rq_out_bits { 7775 u8 status[0x8]; 7776 u8 reserved_at_8[0x18]; 7777 7778 u8 syndrome[0x20]; 7779 7780 u8 reserved_at_40[0x40]; 7781 }; 7782 7783 enum { 7784 MLX5_MODIFY_RQ_IN_MODIFY_BITMASK_VSD = 1ULL << 1, 7785 MLX5_MODIFY_RQ_IN_MODIFY_BITMASK_SCATTER_FCS = 1ULL << 2, 7786 MLX5_MODIFY_RQ_IN_MODIFY_BITMASK_RQ_COUNTER_SET_ID = 1ULL << 3, 7787 }; 7788 7789 struct mlx5_ifc_modify_rq_in_bits { 7790 u8 opcode[0x10]; 7791 u8 uid[0x10]; 7792 7793 u8 reserved_at_20[0x10]; 7794 u8 op_mod[0x10]; 7795 7796 u8 rq_state[0x4]; 7797 u8 reserved_at_44[0x4]; 7798 u8 rqn[0x18]; 7799 7800 u8 reserved_at_60[0x20]; 7801 7802 u8 modify_bitmask[0x40]; 7803 7804 u8 reserved_at_c0[0x40]; 7805 7806 struct mlx5_ifc_rqc_bits ctx; 7807 }; 7808 7809 struct mlx5_ifc_modify_rmp_out_bits { 7810 u8 status[0x8]; 7811 u8 reserved_at_8[0x18]; 7812 7813 u8 syndrome[0x20]; 7814 7815 u8 reserved_at_40[0x40]; 7816 }; 7817 7818 struct mlx5_ifc_rmp_bitmask_bits { 7819 u8 reserved_at_0[0x20]; 7820 7821 u8 reserved_at_20[0x1f]; 7822 u8 lwm[0x1]; 7823 }; 7824 7825 struct mlx5_ifc_modify_rmp_in_bits { 7826 u8 opcode[0x10]; 7827 u8 uid[0x10]; 7828 7829 u8 reserved_at_20[0x10]; 7830 u8 op_mod[0x10]; 7831 7832 u8 rmp_state[0x4]; 7833 u8 reserved_at_44[0x4]; 7834 u8 rmpn[0x18]; 7835 7836 u8 reserved_at_60[0x20]; 7837 7838 struct mlx5_ifc_rmp_bitmask_bits bitmask; 7839 7840 u8 reserved_at_c0[0x40]; 7841 7842 struct mlx5_ifc_rmpc_bits ctx; 7843 }; 7844 7845 struct mlx5_ifc_modify_nic_vport_context_out_bits { 7846 u8 status[0x8]; 7847 u8 reserved_at_8[0x18]; 7848 7849 u8 syndrome[0x20]; 7850 7851 u8 reserved_at_40[0x40]; 7852 }; 7853 7854 struct mlx5_ifc_modify_nic_vport_field_select_bits { 7855 u8 reserved_at_0[0x12]; 7856 u8 affiliation[0x1]; 7857 u8 reserved_at_13[0x1]; 7858 u8 disable_uc_local_lb[0x1]; 7859 u8 disable_mc_local_lb[0x1]; 7860 u8 node_guid[0x1]; 7861 u8 port_guid[0x1]; 7862 u8 min_inline[0x1]; 7863 u8 mtu[0x1]; 7864 u8 change_event[0x1]; 7865 u8 promisc[0x1]; 7866 u8 permanent_address[0x1]; 7867 u8 addresses_list[0x1]; 7868 u8 roce_en[0x1]; 7869 u8 reserved_at_1f[0x1]; 7870 }; 7871 7872 struct mlx5_ifc_modify_nic_vport_context_in_bits { 7873 u8 opcode[0x10]; 7874 u8 reserved_at_10[0x10]; 7875 7876 u8 reserved_at_20[0x10]; 7877 u8 op_mod[0x10]; 7878 7879 u8 other_vport[0x1]; 7880 u8 reserved_at_41[0xf]; 7881 u8 vport_number[0x10]; 7882 7883 struct mlx5_ifc_modify_nic_vport_field_select_bits field_select; 7884 7885 u8 reserved_at_80[0x780]; 7886 7887 struct mlx5_ifc_nic_vport_context_bits nic_vport_context; 7888 }; 7889 7890 struct mlx5_ifc_modify_hca_vport_context_out_bits { 7891 u8 status[0x8]; 7892 u8 reserved_at_8[0x18]; 7893 7894 u8 syndrome[0x20]; 7895 7896 u8 reserved_at_40[0x40]; 7897 }; 7898 7899 struct mlx5_ifc_modify_hca_vport_context_in_bits { 7900 u8 opcode[0x10]; 7901 u8 reserved_at_10[0x10]; 7902 7903 u8 reserved_at_20[0x10]; 7904 u8 op_mod[0x10]; 7905 7906 u8 other_vport[0x1]; 7907 u8 reserved_at_41[0xb]; 7908 u8 port_num[0x4]; 7909 u8 vport_number[0x10]; 7910 7911 u8 reserved_at_60[0x20]; 7912 7913 struct mlx5_ifc_hca_vport_context_bits hca_vport_context; 7914 }; 7915 7916 struct mlx5_ifc_modify_cq_out_bits { 7917 u8 status[0x8]; 7918 u8 reserved_at_8[0x18]; 7919 7920 u8 syndrome[0x20]; 7921 7922 u8 reserved_at_40[0x40]; 7923 }; 7924 7925 enum { 7926 MLX5_MODIFY_CQ_IN_OP_MOD_MODIFY_CQ = 0x0, 7927 MLX5_MODIFY_CQ_IN_OP_MOD_RESIZE_CQ = 0x1, 7928 }; 7929 7930 struct mlx5_ifc_modify_cq_in_bits { 7931 u8 opcode[0x10]; 7932 u8 uid[0x10]; 7933 7934 u8 reserved_at_20[0x10]; 7935 u8 op_mod[0x10]; 7936 7937 u8 reserved_at_40[0x8]; 7938 u8 cqn[0x18]; 7939 7940 union mlx5_ifc_modify_field_select_resize_field_select_auto_bits modify_field_select_resize_field_select; 7941 7942 struct mlx5_ifc_cqc_bits cq_context; 7943 7944 u8 reserved_at_280[0x60]; 7945 7946 u8 cq_umem_valid[0x1]; 7947 u8 reserved_at_2e1[0x1f]; 7948 7949 u8 reserved_at_300[0x580]; 7950 7951 u8 pas[][0x40]; 7952 }; 7953 7954 struct mlx5_ifc_modify_cong_status_out_bits { 7955 u8 status[0x8]; 7956 u8 reserved_at_8[0x18]; 7957 7958 u8 syndrome[0x20]; 7959 7960 u8 reserved_at_40[0x40]; 7961 }; 7962 7963 struct mlx5_ifc_modify_cong_status_in_bits { 7964 u8 opcode[0x10]; 7965 u8 reserved_at_10[0x10]; 7966 7967 u8 reserved_at_20[0x10]; 7968 u8 op_mod[0x10]; 7969 7970 u8 reserved_at_40[0x18]; 7971 u8 priority[0x4]; 7972 u8 cong_protocol[0x4]; 7973 7974 u8 enable[0x1]; 7975 u8 tag_enable[0x1]; 7976 u8 reserved_at_62[0x1e]; 7977 }; 7978 7979 struct mlx5_ifc_modify_cong_params_out_bits { 7980 u8 status[0x8]; 7981 u8 reserved_at_8[0x18]; 7982 7983 u8 syndrome[0x20]; 7984 7985 u8 reserved_at_40[0x40]; 7986 }; 7987 7988 struct mlx5_ifc_modify_cong_params_in_bits { 7989 u8 opcode[0x10]; 7990 u8 reserved_at_10[0x10]; 7991 7992 u8 reserved_at_20[0x10]; 7993 u8 op_mod[0x10]; 7994 7995 u8 reserved_at_40[0x1c]; 7996 u8 cong_protocol[0x4]; 7997 7998 union mlx5_ifc_field_select_802_1_r_roce_auto_bits field_select; 7999 8000 u8 reserved_at_80[0x80]; 8001 8002 union mlx5_ifc_cong_control_roce_ecn_auto_bits congestion_parameters; 8003 }; 8004 8005 struct mlx5_ifc_manage_pages_out_bits { 8006 u8 status[0x8]; 8007 u8 reserved_at_8[0x18]; 8008 8009 u8 syndrome[0x20]; 8010 8011 u8 output_num_entries[0x20]; 8012 8013 u8 reserved_at_60[0x20]; 8014 8015 u8 pas[][0x40]; 8016 }; 8017 8018 enum { 8019 MLX5_MANAGE_PAGES_IN_OP_MOD_ALLOCATION_FAIL = 0x0, 8020 MLX5_MANAGE_PAGES_IN_OP_MOD_ALLOCATION_SUCCESS = 0x1, 8021 MLX5_MANAGE_PAGES_IN_OP_MOD_HCA_RETURN_PAGES = 0x2, 8022 }; 8023 8024 struct mlx5_ifc_manage_pages_in_bits { 8025 u8 opcode[0x10]; 8026 u8 reserved_at_10[0x10]; 8027 8028 u8 reserved_at_20[0x10]; 8029 u8 op_mod[0x10]; 8030 8031 u8 embedded_cpu_function[0x1]; 8032 u8 reserved_at_41[0xf]; 8033 u8 function_id[0x10]; 8034 8035 u8 input_num_entries[0x20]; 8036 8037 u8 pas[][0x40]; 8038 }; 8039 8040 struct mlx5_ifc_mad_ifc_out_bits { 8041 u8 status[0x8]; 8042 u8 reserved_at_8[0x18]; 8043 8044 u8 syndrome[0x20]; 8045 8046 u8 reserved_at_40[0x40]; 8047 8048 u8 response_mad_packet[256][0x8]; 8049 }; 8050 8051 struct mlx5_ifc_mad_ifc_in_bits { 8052 u8 opcode[0x10]; 8053 u8 reserved_at_10[0x10]; 8054 8055 u8 reserved_at_20[0x10]; 8056 u8 op_mod[0x10]; 8057 8058 u8 remote_lid[0x10]; 8059 u8 plane_index[0x8]; 8060 u8 port[0x8]; 8061 8062 u8 reserved_at_60[0x20]; 8063 8064 u8 mad[256][0x8]; 8065 }; 8066 8067 struct mlx5_ifc_init_hca_out_bits { 8068 u8 status[0x8]; 8069 u8 reserved_at_8[0x18]; 8070 8071 u8 syndrome[0x20]; 8072 8073 u8 reserved_at_40[0x40]; 8074 }; 8075 8076 struct mlx5_ifc_init_hca_in_bits { 8077 u8 opcode[0x10]; 8078 u8 reserved_at_10[0x10]; 8079 8080 u8 reserved_at_20[0x10]; 8081 u8 op_mod[0x10]; 8082 8083 u8 reserved_at_40[0x20]; 8084 8085 u8 reserved_at_60[0x2]; 8086 u8 sw_vhca_id[0xe]; 8087 u8 reserved_at_70[0x10]; 8088 8089 u8 sw_owner_id[4][0x20]; 8090 }; 8091 8092 struct mlx5_ifc_init2rtr_qp_out_bits { 8093 u8 status[0x8]; 8094 u8 reserved_at_8[0x18]; 8095 8096 u8 syndrome[0x20]; 8097 8098 u8 reserved_at_40[0x20]; 8099 u8 ece[0x20]; 8100 }; 8101 8102 struct mlx5_ifc_init2rtr_qp_in_bits { 8103 u8 opcode[0x10]; 8104 u8 uid[0x10]; 8105 8106 u8 reserved_at_20[0x10]; 8107 u8 op_mod[0x10]; 8108 8109 u8 reserved_at_40[0x8]; 8110 u8 qpn[0x18]; 8111 8112 u8 reserved_at_60[0x20]; 8113 8114 u8 opt_param_mask[0x20]; 8115 8116 u8 ece[0x20]; 8117 8118 struct mlx5_ifc_qpc_bits qpc; 8119 8120 u8 reserved_at_800[0x80]; 8121 }; 8122 8123 struct mlx5_ifc_init2init_qp_out_bits { 8124 u8 status[0x8]; 8125 u8 reserved_at_8[0x18]; 8126 8127 u8 syndrome[0x20]; 8128 8129 u8 reserved_at_40[0x20]; 8130 u8 ece[0x20]; 8131 }; 8132 8133 struct mlx5_ifc_init2init_qp_in_bits { 8134 u8 opcode[0x10]; 8135 u8 uid[0x10]; 8136 8137 u8 reserved_at_20[0x10]; 8138 u8 op_mod[0x10]; 8139 8140 u8 reserved_at_40[0x8]; 8141 u8 qpn[0x18]; 8142 8143 u8 reserved_at_60[0x20]; 8144 8145 u8 opt_param_mask[0x20]; 8146 8147 u8 ece[0x20]; 8148 8149 struct mlx5_ifc_qpc_bits qpc; 8150 8151 u8 reserved_at_800[0x80]; 8152 }; 8153 8154 struct mlx5_ifc_get_dropped_packet_log_out_bits { 8155 u8 status[0x8]; 8156 u8 reserved_at_8[0x18]; 8157 8158 u8 syndrome[0x20]; 8159 8160 u8 reserved_at_40[0x40]; 8161 8162 u8 packet_headers_log[128][0x8]; 8163 8164 u8 packet_syndrome[64][0x8]; 8165 }; 8166 8167 struct mlx5_ifc_get_dropped_packet_log_in_bits { 8168 u8 opcode[0x10]; 8169 u8 reserved_at_10[0x10]; 8170 8171 u8 reserved_at_20[0x10]; 8172 u8 op_mod[0x10]; 8173 8174 u8 reserved_at_40[0x40]; 8175 }; 8176 8177 struct mlx5_ifc_gen_eqe_in_bits { 8178 u8 opcode[0x10]; 8179 u8 reserved_at_10[0x10]; 8180 8181 u8 reserved_at_20[0x10]; 8182 u8 op_mod[0x10]; 8183 8184 u8 reserved_at_40[0x18]; 8185 u8 eq_number[0x8]; 8186 8187 u8 reserved_at_60[0x20]; 8188 8189 u8 eqe[64][0x8]; 8190 }; 8191 8192 struct mlx5_ifc_gen_eq_out_bits { 8193 u8 status[0x8]; 8194 u8 reserved_at_8[0x18]; 8195 8196 u8 syndrome[0x20]; 8197 8198 u8 reserved_at_40[0x40]; 8199 }; 8200 8201 struct mlx5_ifc_enable_hca_out_bits { 8202 u8 status[0x8]; 8203 u8 reserved_at_8[0x18]; 8204 8205 u8 syndrome[0x20]; 8206 8207 u8 reserved_at_40[0x20]; 8208 }; 8209 8210 struct mlx5_ifc_enable_hca_in_bits { 8211 u8 opcode[0x10]; 8212 u8 reserved_at_10[0x10]; 8213 8214 u8 reserved_at_20[0x10]; 8215 u8 op_mod[0x10]; 8216 8217 u8 embedded_cpu_function[0x1]; 8218 u8 reserved_at_41[0xf]; 8219 u8 function_id[0x10]; 8220 8221 u8 reserved_at_60[0x20]; 8222 }; 8223 8224 struct mlx5_ifc_drain_dct_out_bits { 8225 u8 status[0x8]; 8226 u8 reserved_at_8[0x18]; 8227 8228 u8 syndrome[0x20]; 8229 8230 u8 reserved_at_40[0x40]; 8231 }; 8232 8233 struct mlx5_ifc_drain_dct_in_bits { 8234 u8 opcode[0x10]; 8235 u8 uid[0x10]; 8236 8237 u8 reserved_at_20[0x10]; 8238 u8 op_mod[0x10]; 8239 8240 u8 reserved_at_40[0x8]; 8241 u8 dctn[0x18]; 8242 8243 u8 reserved_at_60[0x20]; 8244 }; 8245 8246 struct mlx5_ifc_disable_hca_out_bits { 8247 u8 status[0x8]; 8248 u8 reserved_at_8[0x18]; 8249 8250 u8 syndrome[0x20]; 8251 8252 u8 reserved_at_40[0x20]; 8253 }; 8254 8255 struct mlx5_ifc_disable_hca_in_bits { 8256 u8 opcode[0x10]; 8257 u8 reserved_at_10[0x10]; 8258 8259 u8 reserved_at_20[0x10]; 8260 u8 op_mod[0x10]; 8261 8262 u8 embedded_cpu_function[0x1]; 8263 u8 reserved_at_41[0xf]; 8264 u8 function_id[0x10]; 8265 8266 u8 reserved_at_60[0x20]; 8267 }; 8268 8269 struct mlx5_ifc_detach_from_mcg_out_bits { 8270 u8 status[0x8]; 8271 u8 reserved_at_8[0x18]; 8272 8273 u8 syndrome[0x20]; 8274 8275 u8 reserved_at_40[0x40]; 8276 }; 8277 8278 struct mlx5_ifc_detach_from_mcg_in_bits { 8279 u8 opcode[0x10]; 8280 u8 uid[0x10]; 8281 8282 u8 reserved_at_20[0x10]; 8283 u8 op_mod[0x10]; 8284 8285 u8 reserved_at_40[0x8]; 8286 u8 qpn[0x18]; 8287 8288 u8 reserved_at_60[0x20]; 8289 8290 u8 multicast_gid[16][0x8]; 8291 }; 8292 8293 struct mlx5_ifc_destroy_xrq_out_bits { 8294 u8 status[0x8]; 8295 u8 reserved_at_8[0x18]; 8296 8297 u8 syndrome[0x20]; 8298 8299 u8 reserved_at_40[0x40]; 8300 }; 8301 8302 struct mlx5_ifc_destroy_xrq_in_bits { 8303 u8 opcode[0x10]; 8304 u8 uid[0x10]; 8305 8306 u8 reserved_at_20[0x10]; 8307 u8 op_mod[0x10]; 8308 8309 u8 reserved_at_40[0x8]; 8310 u8 xrqn[0x18]; 8311 8312 u8 reserved_at_60[0x20]; 8313 }; 8314 8315 struct mlx5_ifc_destroy_xrc_srq_out_bits { 8316 u8 status[0x8]; 8317 u8 reserved_at_8[0x18]; 8318 8319 u8 syndrome[0x20]; 8320 8321 u8 reserved_at_40[0x40]; 8322 }; 8323 8324 struct mlx5_ifc_destroy_xrc_srq_in_bits { 8325 u8 opcode[0x10]; 8326 u8 uid[0x10]; 8327 8328 u8 reserved_at_20[0x10]; 8329 u8 op_mod[0x10]; 8330 8331 u8 reserved_at_40[0x8]; 8332 u8 xrc_srqn[0x18]; 8333 8334 u8 reserved_at_60[0x20]; 8335 }; 8336 8337 struct mlx5_ifc_destroy_tis_out_bits { 8338 u8 status[0x8]; 8339 u8 reserved_at_8[0x18]; 8340 8341 u8 syndrome[0x20]; 8342 8343 u8 reserved_at_40[0x40]; 8344 }; 8345 8346 struct mlx5_ifc_destroy_tis_in_bits { 8347 u8 opcode[0x10]; 8348 u8 uid[0x10]; 8349 8350 u8 reserved_at_20[0x10]; 8351 u8 op_mod[0x10]; 8352 8353 u8 reserved_at_40[0x8]; 8354 u8 tisn[0x18]; 8355 8356 u8 reserved_at_60[0x20]; 8357 }; 8358 8359 struct mlx5_ifc_destroy_tir_out_bits { 8360 u8 status[0x8]; 8361 u8 reserved_at_8[0x18]; 8362 8363 u8 syndrome[0x20]; 8364 8365 u8 reserved_at_40[0x40]; 8366 }; 8367 8368 struct mlx5_ifc_destroy_tir_in_bits { 8369 u8 opcode[0x10]; 8370 u8 uid[0x10]; 8371 8372 u8 reserved_at_20[0x10]; 8373 u8 op_mod[0x10]; 8374 8375 u8 reserved_at_40[0x8]; 8376 u8 tirn[0x18]; 8377 8378 u8 reserved_at_60[0x20]; 8379 }; 8380 8381 struct mlx5_ifc_destroy_srq_out_bits { 8382 u8 status[0x8]; 8383 u8 reserved_at_8[0x18]; 8384 8385 u8 syndrome[0x20]; 8386 8387 u8 reserved_at_40[0x40]; 8388 }; 8389 8390 struct mlx5_ifc_destroy_srq_in_bits { 8391 u8 opcode[0x10]; 8392 u8 uid[0x10]; 8393 8394 u8 reserved_at_20[0x10]; 8395 u8 op_mod[0x10]; 8396 8397 u8 reserved_at_40[0x8]; 8398 u8 srqn[0x18]; 8399 8400 u8 reserved_at_60[0x20]; 8401 }; 8402 8403 struct mlx5_ifc_destroy_sq_out_bits { 8404 u8 status[0x8]; 8405 u8 reserved_at_8[0x18]; 8406 8407 u8 syndrome[0x20]; 8408 8409 u8 reserved_at_40[0x40]; 8410 }; 8411 8412 struct mlx5_ifc_destroy_sq_in_bits { 8413 u8 opcode[0x10]; 8414 u8 uid[0x10]; 8415 8416 u8 reserved_at_20[0x10]; 8417 u8 op_mod[0x10]; 8418 8419 u8 reserved_at_40[0x8]; 8420 u8 sqn[0x18]; 8421 8422 u8 reserved_at_60[0x20]; 8423 }; 8424 8425 struct mlx5_ifc_destroy_scheduling_element_out_bits { 8426 u8 status[0x8]; 8427 u8 reserved_at_8[0x18]; 8428 8429 u8 syndrome[0x20]; 8430 8431 u8 reserved_at_40[0x1c0]; 8432 }; 8433 8434 struct mlx5_ifc_destroy_scheduling_element_in_bits { 8435 u8 opcode[0x10]; 8436 u8 reserved_at_10[0x10]; 8437 8438 u8 reserved_at_20[0x10]; 8439 u8 op_mod[0x10]; 8440 8441 u8 scheduling_hierarchy[0x8]; 8442 u8 reserved_at_48[0x18]; 8443 8444 u8 scheduling_element_id[0x20]; 8445 8446 u8 reserved_at_80[0x180]; 8447 }; 8448 8449 struct mlx5_ifc_destroy_rqt_out_bits { 8450 u8 status[0x8]; 8451 u8 reserved_at_8[0x18]; 8452 8453 u8 syndrome[0x20]; 8454 8455 u8 reserved_at_40[0x40]; 8456 }; 8457 8458 struct mlx5_ifc_destroy_rqt_in_bits { 8459 u8 opcode[0x10]; 8460 u8 uid[0x10]; 8461 8462 u8 reserved_at_20[0x10]; 8463 u8 op_mod[0x10]; 8464 8465 u8 reserved_at_40[0x8]; 8466 u8 rqtn[0x18]; 8467 8468 u8 reserved_at_60[0x20]; 8469 }; 8470 8471 struct mlx5_ifc_destroy_rq_out_bits { 8472 u8 status[0x8]; 8473 u8 reserved_at_8[0x18]; 8474 8475 u8 syndrome[0x20]; 8476 8477 u8 reserved_at_40[0x40]; 8478 }; 8479 8480 struct mlx5_ifc_destroy_rq_in_bits { 8481 u8 opcode[0x10]; 8482 u8 uid[0x10]; 8483 8484 u8 reserved_at_20[0x10]; 8485 u8 op_mod[0x10]; 8486 8487 u8 reserved_at_40[0x8]; 8488 u8 rqn[0x18]; 8489 8490 u8 reserved_at_60[0x20]; 8491 }; 8492 8493 struct mlx5_ifc_set_delay_drop_params_in_bits { 8494 u8 opcode[0x10]; 8495 u8 reserved_at_10[0x10]; 8496 8497 u8 reserved_at_20[0x10]; 8498 u8 op_mod[0x10]; 8499 8500 u8 reserved_at_40[0x20]; 8501 8502 u8 reserved_at_60[0x10]; 8503 u8 delay_drop_timeout[0x10]; 8504 }; 8505 8506 struct mlx5_ifc_set_delay_drop_params_out_bits { 8507 u8 status[0x8]; 8508 u8 reserved_at_8[0x18]; 8509 8510 u8 syndrome[0x20]; 8511 8512 u8 reserved_at_40[0x40]; 8513 }; 8514 8515 struct mlx5_ifc_destroy_rmp_out_bits { 8516 u8 status[0x8]; 8517 u8 reserved_at_8[0x18]; 8518 8519 u8 syndrome[0x20]; 8520 8521 u8 reserved_at_40[0x40]; 8522 }; 8523 8524 struct mlx5_ifc_destroy_rmp_in_bits { 8525 u8 opcode[0x10]; 8526 u8 uid[0x10]; 8527 8528 u8 reserved_at_20[0x10]; 8529 u8 op_mod[0x10]; 8530 8531 u8 reserved_at_40[0x8]; 8532 u8 rmpn[0x18]; 8533 8534 u8 reserved_at_60[0x20]; 8535 }; 8536 8537 struct mlx5_ifc_destroy_qp_out_bits { 8538 u8 status[0x8]; 8539 u8 reserved_at_8[0x18]; 8540 8541 u8 syndrome[0x20]; 8542 8543 u8 reserved_at_40[0x40]; 8544 }; 8545 8546 struct mlx5_ifc_destroy_qp_in_bits { 8547 u8 opcode[0x10]; 8548 u8 uid[0x10]; 8549 8550 u8 reserved_at_20[0x10]; 8551 u8 op_mod[0x10]; 8552 8553 u8 reserved_at_40[0x8]; 8554 u8 qpn[0x18]; 8555 8556 u8 reserved_at_60[0x20]; 8557 }; 8558 8559 struct mlx5_ifc_destroy_psv_out_bits { 8560 u8 status[0x8]; 8561 u8 reserved_at_8[0x18]; 8562 8563 u8 syndrome[0x20]; 8564 8565 u8 reserved_at_40[0x40]; 8566 }; 8567 8568 struct mlx5_ifc_destroy_psv_in_bits { 8569 u8 opcode[0x10]; 8570 u8 reserved_at_10[0x10]; 8571 8572 u8 reserved_at_20[0x10]; 8573 u8 op_mod[0x10]; 8574 8575 u8 reserved_at_40[0x8]; 8576 u8 psvn[0x18]; 8577 8578 u8 reserved_at_60[0x20]; 8579 }; 8580 8581 struct mlx5_ifc_destroy_mkey_out_bits { 8582 u8 status[0x8]; 8583 u8 reserved_at_8[0x18]; 8584 8585 u8 syndrome[0x20]; 8586 8587 u8 reserved_at_40[0x40]; 8588 }; 8589 8590 struct mlx5_ifc_destroy_mkey_in_bits { 8591 u8 opcode[0x10]; 8592 u8 uid[0x10]; 8593 8594 u8 reserved_at_20[0x10]; 8595 u8 op_mod[0x10]; 8596 8597 u8 reserved_at_40[0x8]; 8598 u8 mkey_index[0x18]; 8599 8600 u8 reserved_at_60[0x20]; 8601 }; 8602 8603 struct mlx5_ifc_destroy_flow_table_out_bits { 8604 u8 status[0x8]; 8605 u8 reserved_at_8[0x18]; 8606 8607 u8 syndrome[0x20]; 8608 8609 u8 reserved_at_40[0x40]; 8610 }; 8611 8612 struct mlx5_ifc_destroy_flow_table_in_bits { 8613 u8 opcode[0x10]; 8614 u8 reserved_at_10[0x10]; 8615 8616 u8 reserved_at_20[0x10]; 8617 u8 op_mod[0x10]; 8618 8619 u8 other_vport[0x1]; 8620 u8 reserved_at_41[0xf]; 8621 u8 vport_number[0x10]; 8622 8623 u8 reserved_at_60[0x20]; 8624 8625 u8 table_type[0x8]; 8626 u8 reserved_at_88[0x18]; 8627 8628 u8 reserved_at_a0[0x8]; 8629 u8 table_id[0x18]; 8630 8631 u8 reserved_at_c0[0x140]; 8632 }; 8633 8634 struct mlx5_ifc_destroy_flow_group_out_bits { 8635 u8 status[0x8]; 8636 u8 reserved_at_8[0x18]; 8637 8638 u8 syndrome[0x20]; 8639 8640 u8 reserved_at_40[0x40]; 8641 }; 8642 8643 struct mlx5_ifc_destroy_flow_group_in_bits { 8644 u8 opcode[0x10]; 8645 u8 reserved_at_10[0x10]; 8646 8647 u8 reserved_at_20[0x10]; 8648 u8 op_mod[0x10]; 8649 8650 u8 other_vport[0x1]; 8651 u8 reserved_at_41[0xf]; 8652 u8 vport_number[0x10]; 8653 8654 u8 reserved_at_60[0x20]; 8655 8656 u8 table_type[0x8]; 8657 u8 reserved_at_88[0x18]; 8658 8659 u8 reserved_at_a0[0x8]; 8660 u8 table_id[0x18]; 8661 8662 u8 group_id[0x20]; 8663 8664 u8 reserved_at_e0[0x120]; 8665 }; 8666 8667 struct mlx5_ifc_destroy_eq_out_bits { 8668 u8 status[0x8]; 8669 u8 reserved_at_8[0x18]; 8670 8671 u8 syndrome[0x20]; 8672 8673 u8 reserved_at_40[0x40]; 8674 }; 8675 8676 struct mlx5_ifc_destroy_eq_in_bits { 8677 u8 opcode[0x10]; 8678 u8 reserved_at_10[0x10]; 8679 8680 u8 reserved_at_20[0x10]; 8681 u8 op_mod[0x10]; 8682 8683 u8 reserved_at_40[0x18]; 8684 u8 eq_number[0x8]; 8685 8686 u8 reserved_at_60[0x20]; 8687 }; 8688 8689 struct mlx5_ifc_destroy_dct_out_bits { 8690 u8 status[0x8]; 8691 u8 reserved_at_8[0x18]; 8692 8693 u8 syndrome[0x20]; 8694 8695 u8 reserved_at_40[0x40]; 8696 }; 8697 8698 struct mlx5_ifc_destroy_dct_in_bits { 8699 u8 opcode[0x10]; 8700 u8 uid[0x10]; 8701 8702 u8 reserved_at_20[0x10]; 8703 u8 op_mod[0x10]; 8704 8705 u8 reserved_at_40[0x8]; 8706 u8 dctn[0x18]; 8707 8708 u8 reserved_at_60[0x20]; 8709 }; 8710 8711 struct mlx5_ifc_destroy_cq_out_bits { 8712 u8 status[0x8]; 8713 u8 reserved_at_8[0x18]; 8714 8715 u8 syndrome[0x20]; 8716 8717 u8 reserved_at_40[0x40]; 8718 }; 8719 8720 struct mlx5_ifc_destroy_cq_in_bits { 8721 u8 opcode[0x10]; 8722 u8 uid[0x10]; 8723 8724 u8 reserved_at_20[0x10]; 8725 u8 op_mod[0x10]; 8726 8727 u8 reserved_at_40[0x8]; 8728 u8 cqn[0x18]; 8729 8730 u8 reserved_at_60[0x20]; 8731 }; 8732 8733 struct mlx5_ifc_delete_vxlan_udp_dport_out_bits { 8734 u8 status[0x8]; 8735 u8 reserved_at_8[0x18]; 8736 8737 u8 syndrome[0x20]; 8738 8739 u8 reserved_at_40[0x40]; 8740 }; 8741 8742 struct mlx5_ifc_delete_vxlan_udp_dport_in_bits { 8743 u8 opcode[0x10]; 8744 u8 reserved_at_10[0x10]; 8745 8746 u8 reserved_at_20[0x10]; 8747 u8 op_mod[0x10]; 8748 8749 u8 reserved_at_40[0x20]; 8750 8751 u8 reserved_at_60[0x10]; 8752 u8 vxlan_udp_port[0x10]; 8753 }; 8754 8755 struct mlx5_ifc_delete_l2_table_entry_out_bits { 8756 u8 status[0x8]; 8757 u8 reserved_at_8[0x18]; 8758 8759 u8 syndrome[0x20]; 8760 8761 u8 reserved_at_40[0x40]; 8762 }; 8763 8764 struct mlx5_ifc_delete_l2_table_entry_in_bits { 8765 u8 opcode[0x10]; 8766 u8 reserved_at_10[0x10]; 8767 8768 u8 reserved_at_20[0x10]; 8769 u8 op_mod[0x10]; 8770 8771 u8 reserved_at_40[0x60]; 8772 8773 u8 reserved_at_a0[0x8]; 8774 u8 table_index[0x18]; 8775 8776 u8 reserved_at_c0[0x140]; 8777 }; 8778 8779 struct mlx5_ifc_delete_fte_out_bits { 8780 u8 status[0x8]; 8781 u8 reserved_at_8[0x18]; 8782 8783 u8 syndrome[0x20]; 8784 8785 u8 reserved_at_40[0x40]; 8786 }; 8787 8788 struct mlx5_ifc_delete_fte_in_bits { 8789 u8 opcode[0x10]; 8790 u8 reserved_at_10[0x10]; 8791 8792 u8 reserved_at_20[0x10]; 8793 u8 op_mod[0x10]; 8794 8795 u8 other_vport[0x1]; 8796 u8 reserved_at_41[0xf]; 8797 u8 vport_number[0x10]; 8798 8799 u8 reserved_at_60[0x20]; 8800 8801 u8 table_type[0x8]; 8802 u8 reserved_at_88[0x18]; 8803 8804 u8 reserved_at_a0[0x8]; 8805 u8 table_id[0x18]; 8806 8807 u8 reserved_at_c0[0x40]; 8808 8809 u8 flow_index[0x20]; 8810 8811 u8 reserved_at_120[0xe0]; 8812 }; 8813 8814 struct mlx5_ifc_dealloc_xrcd_out_bits { 8815 u8 status[0x8]; 8816 u8 reserved_at_8[0x18]; 8817 8818 u8 syndrome[0x20]; 8819 8820 u8 reserved_at_40[0x40]; 8821 }; 8822 8823 struct mlx5_ifc_dealloc_xrcd_in_bits { 8824 u8 opcode[0x10]; 8825 u8 uid[0x10]; 8826 8827 u8 reserved_at_20[0x10]; 8828 u8 op_mod[0x10]; 8829 8830 u8 reserved_at_40[0x8]; 8831 u8 xrcd[0x18]; 8832 8833 u8 reserved_at_60[0x20]; 8834 }; 8835 8836 struct mlx5_ifc_dealloc_uar_out_bits { 8837 u8 status[0x8]; 8838 u8 reserved_at_8[0x18]; 8839 8840 u8 syndrome[0x20]; 8841 8842 u8 reserved_at_40[0x40]; 8843 }; 8844 8845 struct mlx5_ifc_dealloc_uar_in_bits { 8846 u8 opcode[0x10]; 8847 u8 uid[0x10]; 8848 8849 u8 reserved_at_20[0x10]; 8850 u8 op_mod[0x10]; 8851 8852 u8 reserved_at_40[0x8]; 8853 u8 uar[0x18]; 8854 8855 u8 reserved_at_60[0x20]; 8856 }; 8857 8858 struct mlx5_ifc_dealloc_transport_domain_out_bits { 8859 u8 status[0x8]; 8860 u8 reserved_at_8[0x18]; 8861 8862 u8 syndrome[0x20]; 8863 8864 u8 reserved_at_40[0x40]; 8865 }; 8866 8867 struct mlx5_ifc_dealloc_transport_domain_in_bits { 8868 u8 opcode[0x10]; 8869 u8 uid[0x10]; 8870 8871 u8 reserved_at_20[0x10]; 8872 u8 op_mod[0x10]; 8873 8874 u8 reserved_at_40[0x8]; 8875 u8 transport_domain[0x18]; 8876 8877 u8 reserved_at_60[0x20]; 8878 }; 8879 8880 struct mlx5_ifc_dealloc_q_counter_out_bits { 8881 u8 status[0x8]; 8882 u8 reserved_at_8[0x18]; 8883 8884 u8 syndrome[0x20]; 8885 8886 u8 reserved_at_40[0x40]; 8887 }; 8888 8889 struct mlx5_ifc_dealloc_q_counter_in_bits { 8890 u8 opcode[0x10]; 8891 u8 reserved_at_10[0x10]; 8892 8893 u8 reserved_at_20[0x10]; 8894 u8 op_mod[0x10]; 8895 8896 u8 reserved_at_40[0x18]; 8897 u8 counter_set_id[0x8]; 8898 8899 u8 reserved_at_60[0x20]; 8900 }; 8901 8902 struct mlx5_ifc_dealloc_pd_out_bits { 8903 u8 status[0x8]; 8904 u8 reserved_at_8[0x18]; 8905 8906 u8 syndrome[0x20]; 8907 8908 u8 reserved_at_40[0x40]; 8909 }; 8910 8911 struct mlx5_ifc_dealloc_pd_in_bits { 8912 u8 opcode[0x10]; 8913 u8 uid[0x10]; 8914 8915 u8 reserved_at_20[0x10]; 8916 u8 op_mod[0x10]; 8917 8918 u8 reserved_at_40[0x8]; 8919 u8 pd[0x18]; 8920 8921 u8 reserved_at_60[0x20]; 8922 }; 8923 8924 struct mlx5_ifc_dealloc_flow_counter_out_bits { 8925 u8 status[0x8]; 8926 u8 reserved_at_8[0x18]; 8927 8928 u8 syndrome[0x20]; 8929 8930 u8 reserved_at_40[0x40]; 8931 }; 8932 8933 struct mlx5_ifc_dealloc_flow_counter_in_bits { 8934 u8 opcode[0x10]; 8935 u8 reserved_at_10[0x10]; 8936 8937 u8 reserved_at_20[0x10]; 8938 u8 op_mod[0x10]; 8939 8940 u8 flow_counter_id[0x20]; 8941 8942 u8 reserved_at_60[0x20]; 8943 }; 8944 8945 struct mlx5_ifc_create_xrq_out_bits { 8946 u8 status[0x8]; 8947 u8 reserved_at_8[0x18]; 8948 8949 u8 syndrome[0x20]; 8950 8951 u8 reserved_at_40[0x8]; 8952 u8 xrqn[0x18]; 8953 8954 u8 reserved_at_60[0x20]; 8955 }; 8956 8957 struct mlx5_ifc_create_xrq_in_bits { 8958 u8 opcode[0x10]; 8959 u8 uid[0x10]; 8960 8961 u8 reserved_at_20[0x10]; 8962 u8 op_mod[0x10]; 8963 8964 u8 reserved_at_40[0x40]; 8965 8966 struct mlx5_ifc_xrqc_bits xrq_context; 8967 }; 8968 8969 struct mlx5_ifc_create_xrc_srq_out_bits { 8970 u8 status[0x8]; 8971 u8 reserved_at_8[0x18]; 8972 8973 u8 syndrome[0x20]; 8974 8975 u8 reserved_at_40[0x8]; 8976 u8 xrc_srqn[0x18]; 8977 8978 u8 reserved_at_60[0x20]; 8979 }; 8980 8981 struct mlx5_ifc_create_xrc_srq_in_bits { 8982 u8 opcode[0x10]; 8983 u8 uid[0x10]; 8984 8985 u8 reserved_at_20[0x10]; 8986 u8 op_mod[0x10]; 8987 8988 u8 reserved_at_40[0x40]; 8989 8990 struct mlx5_ifc_xrc_srqc_bits xrc_srq_context_entry; 8991 8992 u8 reserved_at_280[0x60]; 8993 8994 u8 xrc_srq_umem_valid[0x1]; 8995 u8 reserved_at_2e1[0x1f]; 8996 8997 u8 reserved_at_300[0x580]; 8998 8999 u8 pas[][0x40]; 9000 }; 9001 9002 struct mlx5_ifc_create_tis_out_bits { 9003 u8 status[0x8]; 9004 u8 reserved_at_8[0x18]; 9005 9006 u8 syndrome[0x20]; 9007 9008 u8 reserved_at_40[0x8]; 9009 u8 tisn[0x18]; 9010 9011 u8 reserved_at_60[0x20]; 9012 }; 9013 9014 struct mlx5_ifc_create_tis_in_bits { 9015 u8 opcode[0x10]; 9016 u8 uid[0x10]; 9017 9018 u8 reserved_at_20[0x10]; 9019 u8 op_mod[0x10]; 9020 9021 u8 reserved_at_40[0xc0]; 9022 9023 struct mlx5_ifc_tisc_bits ctx; 9024 }; 9025 9026 struct mlx5_ifc_create_tir_out_bits { 9027 u8 status[0x8]; 9028 u8 icm_address_63_40[0x18]; 9029 9030 u8 syndrome[0x20]; 9031 9032 u8 icm_address_39_32[0x8]; 9033 u8 tirn[0x18]; 9034 9035 u8 icm_address_31_0[0x20]; 9036 }; 9037 9038 struct mlx5_ifc_create_tir_in_bits { 9039 u8 opcode[0x10]; 9040 u8 uid[0x10]; 9041 9042 u8 reserved_at_20[0x10]; 9043 u8 op_mod[0x10]; 9044 9045 u8 reserved_at_40[0xc0]; 9046 9047 struct mlx5_ifc_tirc_bits ctx; 9048 }; 9049 9050 struct mlx5_ifc_create_srq_out_bits { 9051 u8 status[0x8]; 9052 u8 reserved_at_8[0x18]; 9053 9054 u8 syndrome[0x20]; 9055 9056 u8 reserved_at_40[0x8]; 9057 u8 srqn[0x18]; 9058 9059 u8 reserved_at_60[0x20]; 9060 }; 9061 9062 struct mlx5_ifc_create_srq_in_bits { 9063 u8 opcode[0x10]; 9064 u8 uid[0x10]; 9065 9066 u8 reserved_at_20[0x10]; 9067 u8 op_mod[0x10]; 9068 9069 u8 reserved_at_40[0x40]; 9070 9071 struct mlx5_ifc_srqc_bits srq_context_entry; 9072 9073 u8 reserved_at_280[0x600]; 9074 9075 u8 pas[][0x40]; 9076 }; 9077 9078 struct mlx5_ifc_create_sq_out_bits { 9079 u8 status[0x8]; 9080 u8 reserved_at_8[0x18]; 9081 9082 u8 syndrome[0x20]; 9083 9084 u8 reserved_at_40[0x8]; 9085 u8 sqn[0x18]; 9086 9087 u8 reserved_at_60[0x20]; 9088 }; 9089 9090 struct mlx5_ifc_create_sq_in_bits { 9091 u8 opcode[0x10]; 9092 u8 uid[0x10]; 9093 9094 u8 reserved_at_20[0x10]; 9095 u8 op_mod[0x10]; 9096 9097 u8 reserved_at_40[0xc0]; 9098 9099 struct mlx5_ifc_sqc_bits ctx; 9100 }; 9101 9102 struct mlx5_ifc_create_scheduling_element_out_bits { 9103 u8 status[0x8]; 9104 u8 reserved_at_8[0x18]; 9105 9106 u8 syndrome[0x20]; 9107 9108 u8 reserved_at_40[0x40]; 9109 9110 u8 scheduling_element_id[0x20]; 9111 9112 u8 reserved_at_a0[0x160]; 9113 }; 9114 9115 struct mlx5_ifc_create_scheduling_element_in_bits { 9116 u8 opcode[0x10]; 9117 u8 reserved_at_10[0x10]; 9118 9119 u8 reserved_at_20[0x10]; 9120 u8 op_mod[0x10]; 9121 9122 u8 scheduling_hierarchy[0x8]; 9123 u8 reserved_at_48[0x18]; 9124 9125 u8 reserved_at_60[0xa0]; 9126 9127 struct mlx5_ifc_scheduling_context_bits scheduling_context; 9128 9129 u8 reserved_at_300[0x100]; 9130 }; 9131 9132 struct mlx5_ifc_create_rqt_out_bits { 9133 u8 status[0x8]; 9134 u8 reserved_at_8[0x18]; 9135 9136 u8 syndrome[0x20]; 9137 9138 u8 reserved_at_40[0x8]; 9139 u8 rqtn[0x18]; 9140 9141 u8 reserved_at_60[0x20]; 9142 }; 9143 9144 struct mlx5_ifc_create_rqt_in_bits { 9145 u8 opcode[0x10]; 9146 u8 uid[0x10]; 9147 9148 u8 reserved_at_20[0x10]; 9149 u8 op_mod[0x10]; 9150 9151 u8 reserved_at_40[0xc0]; 9152 9153 struct mlx5_ifc_rqtc_bits rqt_context; 9154 }; 9155 9156 struct mlx5_ifc_create_rq_out_bits { 9157 u8 status[0x8]; 9158 u8 reserved_at_8[0x18]; 9159 9160 u8 syndrome[0x20]; 9161 9162 u8 reserved_at_40[0x8]; 9163 u8 rqn[0x18]; 9164 9165 u8 reserved_at_60[0x20]; 9166 }; 9167 9168 struct mlx5_ifc_create_rq_in_bits { 9169 u8 opcode[0x10]; 9170 u8 uid[0x10]; 9171 9172 u8 reserved_at_20[0x10]; 9173 u8 op_mod[0x10]; 9174 9175 u8 reserved_at_40[0xc0]; 9176 9177 struct mlx5_ifc_rqc_bits ctx; 9178 }; 9179 9180 struct mlx5_ifc_create_rmp_out_bits { 9181 u8 status[0x8]; 9182 u8 reserved_at_8[0x18]; 9183 9184 u8 syndrome[0x20]; 9185 9186 u8 reserved_at_40[0x8]; 9187 u8 rmpn[0x18]; 9188 9189 u8 reserved_at_60[0x20]; 9190 }; 9191 9192 struct mlx5_ifc_create_rmp_in_bits { 9193 u8 opcode[0x10]; 9194 u8 uid[0x10]; 9195 9196 u8 reserved_at_20[0x10]; 9197 u8 op_mod[0x10]; 9198 9199 u8 reserved_at_40[0xc0]; 9200 9201 struct mlx5_ifc_rmpc_bits ctx; 9202 }; 9203 9204 struct mlx5_ifc_create_qp_out_bits { 9205 u8 status[0x8]; 9206 u8 reserved_at_8[0x18]; 9207 9208 u8 syndrome[0x20]; 9209 9210 u8 reserved_at_40[0x8]; 9211 u8 qpn[0x18]; 9212 9213 u8 ece[0x20]; 9214 }; 9215 9216 struct mlx5_ifc_create_qp_in_bits { 9217 u8 opcode[0x10]; 9218 u8 uid[0x10]; 9219 9220 u8 reserved_at_20[0x10]; 9221 u8 op_mod[0x10]; 9222 9223 u8 qpc_ext[0x1]; 9224 u8 reserved_at_41[0x7]; 9225 u8 input_qpn[0x18]; 9226 9227 u8 reserved_at_60[0x20]; 9228 u8 opt_param_mask[0x20]; 9229 9230 u8 ece[0x20]; 9231 9232 struct mlx5_ifc_qpc_bits qpc; 9233 9234 u8 wq_umem_offset[0x40]; 9235 9236 u8 wq_umem_id[0x20]; 9237 9238 u8 wq_umem_valid[0x1]; 9239 u8 reserved_at_861[0x1f]; 9240 9241 u8 pas[][0x40]; 9242 }; 9243 9244 struct mlx5_ifc_create_psv_out_bits { 9245 u8 status[0x8]; 9246 u8 reserved_at_8[0x18]; 9247 9248 u8 syndrome[0x20]; 9249 9250 u8 reserved_at_40[0x40]; 9251 9252 u8 reserved_at_80[0x8]; 9253 u8 psv0_index[0x18]; 9254 9255 u8 reserved_at_a0[0x8]; 9256 u8 psv1_index[0x18]; 9257 9258 u8 reserved_at_c0[0x8]; 9259 u8 psv2_index[0x18]; 9260 9261 u8 reserved_at_e0[0x8]; 9262 u8 psv3_index[0x18]; 9263 }; 9264 9265 struct mlx5_ifc_create_psv_in_bits { 9266 u8 opcode[0x10]; 9267 u8 reserved_at_10[0x10]; 9268 9269 u8 reserved_at_20[0x10]; 9270 u8 op_mod[0x10]; 9271 9272 u8 num_psv[0x4]; 9273 u8 reserved_at_44[0x4]; 9274 u8 pd[0x18]; 9275 9276 u8 reserved_at_60[0x20]; 9277 }; 9278 9279 struct mlx5_ifc_create_mkey_out_bits { 9280 u8 status[0x8]; 9281 u8 reserved_at_8[0x18]; 9282 9283 u8 syndrome[0x20]; 9284 9285 u8 reserved_at_40[0x8]; 9286 u8 mkey_index[0x18]; 9287 9288 u8 reserved_at_60[0x20]; 9289 }; 9290 9291 struct mlx5_ifc_create_mkey_in_bits { 9292 u8 opcode[0x10]; 9293 u8 uid[0x10]; 9294 9295 u8 reserved_at_20[0x10]; 9296 u8 op_mod[0x10]; 9297 9298 u8 reserved_at_40[0x20]; 9299 9300 u8 pg_access[0x1]; 9301 u8 mkey_umem_valid[0x1]; 9302 u8 data_direct[0x1]; 9303 u8 reserved_at_63[0x1d]; 9304 9305 struct mlx5_ifc_mkc_bits memory_key_mkey_entry; 9306 9307 u8 reserved_at_280[0x80]; 9308 9309 u8 translations_octword_actual_size[0x20]; 9310 9311 u8 reserved_at_320[0x560]; 9312 9313 u8 klm_pas_mtt[][0x20]; 9314 }; 9315 9316 enum { 9317 MLX5_FLOW_TABLE_TYPE_NIC_RX = 0x0, 9318 MLX5_FLOW_TABLE_TYPE_NIC_TX = 0x1, 9319 MLX5_FLOW_TABLE_TYPE_ESW_EGRESS_ACL = 0x2, 9320 MLX5_FLOW_TABLE_TYPE_ESW_INGRESS_ACL = 0x3, 9321 MLX5_FLOW_TABLE_TYPE_FDB = 0X4, 9322 MLX5_FLOW_TABLE_TYPE_SNIFFER_RX = 0X5, 9323 MLX5_FLOW_TABLE_TYPE_SNIFFER_TX = 0X6, 9324 }; 9325 9326 struct mlx5_ifc_create_flow_table_out_bits { 9327 u8 status[0x8]; 9328 u8 icm_address_63_40[0x18]; 9329 9330 u8 syndrome[0x20]; 9331 9332 u8 icm_address_39_32[0x8]; 9333 u8 table_id[0x18]; 9334 9335 u8 icm_address_31_0[0x20]; 9336 }; 9337 9338 struct mlx5_ifc_create_flow_table_in_bits { 9339 u8 opcode[0x10]; 9340 u8 uid[0x10]; 9341 9342 u8 reserved_at_20[0x10]; 9343 u8 op_mod[0x10]; 9344 9345 u8 other_vport[0x1]; 9346 u8 reserved_at_41[0xf]; 9347 u8 vport_number[0x10]; 9348 9349 u8 reserved_at_60[0x20]; 9350 9351 u8 table_type[0x8]; 9352 u8 reserved_at_88[0x18]; 9353 9354 u8 reserved_at_a0[0x20]; 9355 9356 struct mlx5_ifc_flow_table_context_bits flow_table_context; 9357 }; 9358 9359 struct mlx5_ifc_create_flow_group_out_bits { 9360 u8 status[0x8]; 9361 u8 reserved_at_8[0x18]; 9362 9363 u8 syndrome[0x20]; 9364 9365 u8 reserved_at_40[0x8]; 9366 u8 group_id[0x18]; 9367 9368 u8 reserved_at_60[0x20]; 9369 }; 9370 9371 enum { 9372 MLX5_CREATE_FLOW_GROUP_IN_GROUP_TYPE_TCAM_SUBTABLE = 0x0, 9373 MLX5_CREATE_FLOW_GROUP_IN_GROUP_TYPE_HASH_SPLIT = 0x1, 9374 }; 9375 9376 enum { 9377 MLX5_CREATE_FLOW_GROUP_IN_MATCH_CRITERIA_ENABLE_OUTER_HEADERS = 0x0, 9378 MLX5_CREATE_FLOW_GROUP_IN_MATCH_CRITERIA_ENABLE_MISC_PARAMETERS = 0x1, 9379 MLX5_CREATE_FLOW_GROUP_IN_MATCH_CRITERIA_ENABLE_INNER_HEADERS = 0x2, 9380 MLX5_CREATE_FLOW_GROUP_IN_MATCH_CRITERIA_ENABLE_MISC_PARAMETERS_2 = 0x3, 9381 }; 9382 9383 struct mlx5_ifc_create_flow_group_in_bits { 9384 u8 opcode[0x10]; 9385 u8 reserved_at_10[0x10]; 9386 9387 u8 reserved_at_20[0x10]; 9388 u8 op_mod[0x10]; 9389 9390 u8 other_vport[0x1]; 9391 u8 reserved_at_41[0xf]; 9392 u8 vport_number[0x10]; 9393 9394 u8 reserved_at_60[0x20]; 9395 9396 u8 table_type[0x8]; 9397 u8 reserved_at_88[0x4]; 9398 u8 group_type[0x4]; 9399 u8 reserved_at_90[0x10]; 9400 9401 u8 reserved_at_a0[0x8]; 9402 u8 table_id[0x18]; 9403 9404 u8 source_eswitch_owner_vhca_id_valid[0x1]; 9405 9406 u8 reserved_at_c1[0x1f]; 9407 9408 u8 start_flow_index[0x20]; 9409 9410 u8 reserved_at_100[0x20]; 9411 9412 u8 end_flow_index[0x20]; 9413 9414 u8 reserved_at_140[0x10]; 9415 u8 match_definer_id[0x10]; 9416 9417 u8 reserved_at_160[0x80]; 9418 9419 u8 reserved_at_1e0[0x18]; 9420 u8 match_criteria_enable[0x8]; 9421 9422 struct mlx5_ifc_fte_match_param_bits match_criteria; 9423 9424 u8 reserved_at_1200[0xe00]; 9425 }; 9426 9427 struct mlx5_ifc_create_eq_out_bits { 9428 u8 status[0x8]; 9429 u8 reserved_at_8[0x18]; 9430 9431 u8 syndrome[0x20]; 9432 9433 u8 reserved_at_40[0x18]; 9434 u8 eq_number[0x8]; 9435 9436 u8 reserved_at_60[0x20]; 9437 }; 9438 9439 struct mlx5_ifc_create_eq_in_bits { 9440 u8 opcode[0x10]; 9441 u8 uid[0x10]; 9442 9443 u8 reserved_at_20[0x10]; 9444 u8 op_mod[0x10]; 9445 9446 u8 reserved_at_40[0x40]; 9447 9448 struct mlx5_ifc_eqc_bits eq_context_entry; 9449 9450 u8 reserved_at_280[0x40]; 9451 9452 u8 event_bitmask[4][0x40]; 9453 9454 u8 reserved_at_3c0[0x4c0]; 9455 9456 u8 pas[][0x40]; 9457 }; 9458 9459 struct mlx5_ifc_create_dct_out_bits { 9460 u8 status[0x8]; 9461 u8 reserved_at_8[0x18]; 9462 9463 u8 syndrome[0x20]; 9464 9465 u8 reserved_at_40[0x8]; 9466 u8 dctn[0x18]; 9467 9468 u8 ece[0x20]; 9469 }; 9470 9471 struct mlx5_ifc_create_dct_in_bits { 9472 u8 opcode[0x10]; 9473 u8 uid[0x10]; 9474 9475 u8 reserved_at_20[0x10]; 9476 u8 op_mod[0x10]; 9477 9478 u8 reserved_at_40[0x40]; 9479 9480 struct mlx5_ifc_dctc_bits dct_context_entry; 9481 9482 u8 reserved_at_280[0x180]; 9483 }; 9484 9485 struct mlx5_ifc_create_cq_out_bits { 9486 u8 status[0x8]; 9487 u8 reserved_at_8[0x18]; 9488 9489 u8 syndrome[0x20]; 9490 9491 u8 reserved_at_40[0x8]; 9492 u8 cqn[0x18]; 9493 9494 u8 reserved_at_60[0x20]; 9495 }; 9496 9497 struct mlx5_ifc_create_cq_in_bits { 9498 u8 opcode[0x10]; 9499 u8 uid[0x10]; 9500 9501 u8 reserved_at_20[0x10]; 9502 u8 op_mod[0x10]; 9503 9504 u8 reserved_at_40[0x40]; 9505 9506 struct mlx5_ifc_cqc_bits cq_context; 9507 9508 u8 reserved_at_280[0x60]; 9509 9510 u8 cq_umem_valid[0x1]; 9511 u8 reserved_at_2e1[0x59f]; 9512 9513 u8 pas[][0x40]; 9514 }; 9515 9516 struct mlx5_ifc_config_int_moderation_out_bits { 9517 u8 status[0x8]; 9518 u8 reserved_at_8[0x18]; 9519 9520 u8 syndrome[0x20]; 9521 9522 u8 reserved_at_40[0x4]; 9523 u8 min_delay[0xc]; 9524 u8 int_vector[0x10]; 9525 9526 u8 reserved_at_60[0x20]; 9527 }; 9528 9529 enum { 9530 MLX5_CONFIG_INT_MODERATION_IN_OP_MOD_WRITE = 0x0, 9531 MLX5_CONFIG_INT_MODERATION_IN_OP_MOD_READ = 0x1, 9532 }; 9533 9534 struct mlx5_ifc_config_int_moderation_in_bits { 9535 u8 opcode[0x10]; 9536 u8 reserved_at_10[0x10]; 9537 9538 u8 reserved_at_20[0x10]; 9539 u8 op_mod[0x10]; 9540 9541 u8 reserved_at_40[0x4]; 9542 u8 min_delay[0xc]; 9543 u8 int_vector[0x10]; 9544 9545 u8 reserved_at_60[0x20]; 9546 }; 9547 9548 struct mlx5_ifc_attach_to_mcg_out_bits { 9549 u8 status[0x8]; 9550 u8 reserved_at_8[0x18]; 9551 9552 u8 syndrome[0x20]; 9553 9554 u8 reserved_at_40[0x40]; 9555 }; 9556 9557 struct mlx5_ifc_attach_to_mcg_in_bits { 9558 u8 opcode[0x10]; 9559 u8 uid[0x10]; 9560 9561 u8 reserved_at_20[0x10]; 9562 u8 op_mod[0x10]; 9563 9564 u8 reserved_at_40[0x8]; 9565 u8 qpn[0x18]; 9566 9567 u8 reserved_at_60[0x20]; 9568 9569 u8 multicast_gid[16][0x8]; 9570 }; 9571 9572 struct mlx5_ifc_arm_xrq_out_bits { 9573 u8 status[0x8]; 9574 u8 reserved_at_8[0x18]; 9575 9576 u8 syndrome[0x20]; 9577 9578 u8 reserved_at_40[0x40]; 9579 }; 9580 9581 struct mlx5_ifc_arm_xrq_in_bits { 9582 u8 opcode[0x10]; 9583 u8 reserved_at_10[0x10]; 9584 9585 u8 reserved_at_20[0x10]; 9586 u8 op_mod[0x10]; 9587 9588 u8 reserved_at_40[0x8]; 9589 u8 xrqn[0x18]; 9590 9591 u8 reserved_at_60[0x10]; 9592 u8 lwm[0x10]; 9593 }; 9594 9595 struct mlx5_ifc_arm_xrc_srq_out_bits { 9596 u8 status[0x8]; 9597 u8 reserved_at_8[0x18]; 9598 9599 u8 syndrome[0x20]; 9600 9601 u8 reserved_at_40[0x40]; 9602 }; 9603 9604 enum { 9605 MLX5_ARM_XRC_SRQ_IN_OP_MOD_XRC_SRQ = 0x1, 9606 }; 9607 9608 struct mlx5_ifc_arm_xrc_srq_in_bits { 9609 u8 opcode[0x10]; 9610 u8 uid[0x10]; 9611 9612 u8 reserved_at_20[0x10]; 9613 u8 op_mod[0x10]; 9614 9615 u8 reserved_at_40[0x8]; 9616 u8 xrc_srqn[0x18]; 9617 9618 u8 reserved_at_60[0x10]; 9619 u8 lwm[0x10]; 9620 }; 9621 9622 struct mlx5_ifc_arm_rq_out_bits { 9623 u8 status[0x8]; 9624 u8 reserved_at_8[0x18]; 9625 9626 u8 syndrome[0x20]; 9627 9628 u8 reserved_at_40[0x40]; 9629 }; 9630 9631 enum { 9632 MLX5_ARM_RQ_IN_OP_MOD_SRQ = 0x1, 9633 MLX5_ARM_RQ_IN_OP_MOD_XRQ = 0x2, 9634 }; 9635 9636 struct mlx5_ifc_arm_rq_in_bits { 9637 u8 opcode[0x10]; 9638 u8 uid[0x10]; 9639 9640 u8 reserved_at_20[0x10]; 9641 u8 op_mod[0x10]; 9642 9643 u8 reserved_at_40[0x8]; 9644 u8 srq_number[0x18]; 9645 9646 u8 reserved_at_60[0x10]; 9647 u8 lwm[0x10]; 9648 }; 9649 9650 struct mlx5_ifc_arm_dct_out_bits { 9651 u8 status[0x8]; 9652 u8 reserved_at_8[0x18]; 9653 9654 u8 syndrome[0x20]; 9655 9656 u8 reserved_at_40[0x40]; 9657 }; 9658 9659 struct mlx5_ifc_arm_dct_in_bits { 9660 u8 opcode[0x10]; 9661 u8 reserved_at_10[0x10]; 9662 9663 u8 reserved_at_20[0x10]; 9664 u8 op_mod[0x10]; 9665 9666 u8 reserved_at_40[0x8]; 9667 u8 dct_number[0x18]; 9668 9669 u8 reserved_at_60[0x20]; 9670 }; 9671 9672 struct mlx5_ifc_alloc_xrcd_out_bits { 9673 u8 status[0x8]; 9674 u8 reserved_at_8[0x18]; 9675 9676 u8 syndrome[0x20]; 9677 9678 u8 reserved_at_40[0x8]; 9679 u8 xrcd[0x18]; 9680 9681 u8 reserved_at_60[0x20]; 9682 }; 9683 9684 struct mlx5_ifc_alloc_xrcd_in_bits { 9685 u8 opcode[0x10]; 9686 u8 uid[0x10]; 9687 9688 u8 reserved_at_20[0x10]; 9689 u8 op_mod[0x10]; 9690 9691 u8 reserved_at_40[0x40]; 9692 }; 9693 9694 struct mlx5_ifc_alloc_uar_out_bits { 9695 u8 status[0x8]; 9696 u8 reserved_at_8[0x18]; 9697 9698 u8 syndrome[0x20]; 9699 9700 u8 reserved_at_40[0x8]; 9701 u8 uar[0x18]; 9702 9703 u8 reserved_at_60[0x20]; 9704 }; 9705 9706 struct mlx5_ifc_alloc_uar_in_bits { 9707 u8 opcode[0x10]; 9708 u8 uid[0x10]; 9709 9710 u8 reserved_at_20[0x10]; 9711 u8 op_mod[0x10]; 9712 9713 u8 reserved_at_40[0x40]; 9714 }; 9715 9716 struct mlx5_ifc_alloc_transport_domain_out_bits { 9717 u8 status[0x8]; 9718 u8 reserved_at_8[0x18]; 9719 9720 u8 syndrome[0x20]; 9721 9722 u8 reserved_at_40[0x8]; 9723 u8 transport_domain[0x18]; 9724 9725 u8 reserved_at_60[0x20]; 9726 }; 9727 9728 struct mlx5_ifc_alloc_transport_domain_in_bits { 9729 u8 opcode[0x10]; 9730 u8 uid[0x10]; 9731 9732 u8 reserved_at_20[0x10]; 9733 u8 op_mod[0x10]; 9734 9735 u8 reserved_at_40[0x40]; 9736 }; 9737 9738 struct mlx5_ifc_alloc_q_counter_out_bits { 9739 u8 status[0x8]; 9740 u8 reserved_at_8[0x18]; 9741 9742 u8 syndrome[0x20]; 9743 9744 u8 reserved_at_40[0x18]; 9745 u8 counter_set_id[0x8]; 9746 9747 u8 reserved_at_60[0x20]; 9748 }; 9749 9750 struct mlx5_ifc_alloc_q_counter_in_bits { 9751 u8 opcode[0x10]; 9752 u8 uid[0x10]; 9753 9754 u8 reserved_at_20[0x10]; 9755 u8 op_mod[0x10]; 9756 9757 u8 reserved_at_40[0x40]; 9758 }; 9759 9760 struct mlx5_ifc_alloc_pd_out_bits { 9761 u8 status[0x8]; 9762 u8 reserved_at_8[0x18]; 9763 9764 u8 syndrome[0x20]; 9765 9766 u8 reserved_at_40[0x8]; 9767 u8 pd[0x18]; 9768 9769 u8 reserved_at_60[0x20]; 9770 }; 9771 9772 struct mlx5_ifc_alloc_pd_in_bits { 9773 u8 opcode[0x10]; 9774 u8 uid[0x10]; 9775 9776 u8 reserved_at_20[0x10]; 9777 u8 op_mod[0x10]; 9778 9779 u8 reserved_at_40[0x40]; 9780 }; 9781 9782 struct mlx5_ifc_alloc_flow_counter_out_bits { 9783 u8 status[0x8]; 9784 u8 reserved_at_8[0x18]; 9785 9786 u8 syndrome[0x20]; 9787 9788 u8 flow_counter_id[0x20]; 9789 9790 u8 reserved_at_60[0x20]; 9791 }; 9792 9793 struct mlx5_ifc_alloc_flow_counter_in_bits { 9794 u8 opcode[0x10]; 9795 u8 reserved_at_10[0x10]; 9796 9797 u8 reserved_at_20[0x10]; 9798 u8 op_mod[0x10]; 9799 9800 u8 reserved_at_40[0x33]; 9801 u8 flow_counter_bulk_log_size[0x5]; 9802 u8 flow_counter_bulk[0x8]; 9803 }; 9804 9805 struct mlx5_ifc_add_vxlan_udp_dport_out_bits { 9806 u8 status[0x8]; 9807 u8 reserved_at_8[0x18]; 9808 9809 u8 syndrome[0x20]; 9810 9811 u8 reserved_at_40[0x40]; 9812 }; 9813 9814 struct mlx5_ifc_add_vxlan_udp_dport_in_bits { 9815 u8 opcode[0x10]; 9816 u8 reserved_at_10[0x10]; 9817 9818 u8 reserved_at_20[0x10]; 9819 u8 op_mod[0x10]; 9820 9821 u8 reserved_at_40[0x20]; 9822 9823 u8 reserved_at_60[0x10]; 9824 u8 vxlan_udp_port[0x10]; 9825 }; 9826 9827 struct mlx5_ifc_set_pp_rate_limit_out_bits { 9828 u8 status[0x8]; 9829 u8 reserved_at_8[0x18]; 9830 9831 u8 syndrome[0x20]; 9832 9833 u8 reserved_at_40[0x40]; 9834 }; 9835 9836 struct mlx5_ifc_set_pp_rate_limit_context_bits { 9837 u8 rate_limit[0x20]; 9838 9839 u8 burst_upper_bound[0x20]; 9840 9841 u8 reserved_at_40[0x10]; 9842 u8 typical_packet_size[0x10]; 9843 9844 u8 reserved_at_60[0x120]; 9845 }; 9846 9847 struct mlx5_ifc_set_pp_rate_limit_in_bits { 9848 u8 opcode[0x10]; 9849 u8 uid[0x10]; 9850 9851 u8 reserved_at_20[0x10]; 9852 u8 op_mod[0x10]; 9853 9854 u8 reserved_at_40[0x10]; 9855 u8 rate_limit_index[0x10]; 9856 9857 u8 reserved_at_60[0x20]; 9858 9859 struct mlx5_ifc_set_pp_rate_limit_context_bits ctx; 9860 }; 9861 9862 struct mlx5_ifc_access_register_out_bits { 9863 u8 status[0x8]; 9864 u8 reserved_at_8[0x18]; 9865 9866 u8 syndrome[0x20]; 9867 9868 u8 reserved_at_40[0x40]; 9869 9870 u8 register_data[][0x20]; 9871 }; 9872 9873 enum { 9874 MLX5_ACCESS_REGISTER_IN_OP_MOD_WRITE = 0x0, 9875 MLX5_ACCESS_REGISTER_IN_OP_MOD_READ = 0x1, 9876 }; 9877 9878 struct mlx5_ifc_access_register_in_bits { 9879 u8 opcode[0x10]; 9880 u8 reserved_at_10[0x10]; 9881 9882 u8 reserved_at_20[0x10]; 9883 u8 op_mod[0x10]; 9884 9885 u8 reserved_at_40[0x10]; 9886 u8 register_id[0x10]; 9887 9888 u8 argument[0x20]; 9889 9890 u8 register_data[][0x20]; 9891 }; 9892 9893 struct mlx5_ifc_sltp_reg_bits { 9894 u8 status[0x4]; 9895 u8 version[0x4]; 9896 u8 local_port[0x8]; 9897 u8 pnat[0x2]; 9898 u8 reserved_at_12[0x2]; 9899 u8 lane[0x4]; 9900 u8 reserved_at_18[0x8]; 9901 9902 u8 reserved_at_20[0x20]; 9903 9904 u8 reserved_at_40[0x7]; 9905 u8 polarity[0x1]; 9906 u8 ob_tap0[0x8]; 9907 u8 ob_tap1[0x8]; 9908 u8 ob_tap2[0x8]; 9909 9910 u8 reserved_at_60[0xc]; 9911 u8 ob_preemp_mode[0x4]; 9912 u8 ob_reg[0x8]; 9913 u8 ob_bias[0x8]; 9914 9915 u8 reserved_at_80[0x20]; 9916 }; 9917 9918 struct mlx5_ifc_slrg_reg_bits { 9919 u8 status[0x4]; 9920 u8 version[0x4]; 9921 u8 local_port[0x8]; 9922 u8 pnat[0x2]; 9923 u8 reserved_at_12[0x2]; 9924 u8 lane[0x4]; 9925 u8 reserved_at_18[0x8]; 9926 9927 u8 time_to_link_up[0x10]; 9928 u8 reserved_at_30[0xc]; 9929 u8 grade_lane_speed[0x4]; 9930 9931 u8 grade_version[0x8]; 9932 u8 grade[0x18]; 9933 9934 u8 reserved_at_60[0x4]; 9935 u8 height_grade_type[0x4]; 9936 u8 height_grade[0x18]; 9937 9938 u8 height_dz[0x10]; 9939 u8 height_dv[0x10]; 9940 9941 u8 reserved_at_a0[0x10]; 9942 u8 height_sigma[0x10]; 9943 9944 u8 reserved_at_c0[0x20]; 9945 9946 u8 reserved_at_e0[0x4]; 9947 u8 phase_grade_type[0x4]; 9948 u8 phase_grade[0x18]; 9949 9950 u8 reserved_at_100[0x8]; 9951 u8 phase_eo_pos[0x8]; 9952 u8 reserved_at_110[0x8]; 9953 u8 phase_eo_neg[0x8]; 9954 9955 u8 ffe_set_tested[0x10]; 9956 u8 test_errors_per_lane[0x10]; 9957 }; 9958 9959 struct mlx5_ifc_pvlc_reg_bits { 9960 u8 reserved_at_0[0x8]; 9961 u8 local_port[0x8]; 9962 u8 reserved_at_10[0x10]; 9963 9964 u8 reserved_at_20[0x1c]; 9965 u8 vl_hw_cap[0x4]; 9966 9967 u8 reserved_at_40[0x1c]; 9968 u8 vl_admin[0x4]; 9969 9970 u8 reserved_at_60[0x1c]; 9971 u8 vl_operational[0x4]; 9972 }; 9973 9974 struct mlx5_ifc_pude_reg_bits { 9975 u8 swid[0x8]; 9976 u8 local_port[0x8]; 9977 u8 reserved_at_10[0x4]; 9978 u8 admin_status[0x4]; 9979 u8 reserved_at_18[0x4]; 9980 u8 oper_status[0x4]; 9981 9982 u8 reserved_at_20[0x60]; 9983 }; 9984 9985 struct mlx5_ifc_ptys_reg_bits { 9986 u8 reserved_at_0[0x1]; 9987 u8 an_disable_admin[0x1]; 9988 u8 an_disable_cap[0x1]; 9989 u8 reserved_at_3[0x5]; 9990 u8 local_port[0x8]; 9991 u8 reserved_at_10[0x8]; 9992 u8 plane_ind[0x4]; 9993 u8 reserved_at_1c[0x1]; 9994 u8 proto_mask[0x3]; 9995 9996 u8 an_status[0x4]; 9997 u8 reserved_at_24[0xc]; 9998 u8 data_rate_oper[0x10]; 9999 10000 u8 ext_eth_proto_capability[0x20]; 10001 10002 u8 eth_proto_capability[0x20]; 10003 10004 u8 ib_link_width_capability[0x10]; 10005 u8 ib_proto_capability[0x10]; 10006 10007 u8 ext_eth_proto_admin[0x20]; 10008 10009 u8 eth_proto_admin[0x20]; 10010 10011 u8 ib_link_width_admin[0x10]; 10012 u8 ib_proto_admin[0x10]; 10013 10014 u8 ext_eth_proto_oper[0x20]; 10015 10016 u8 eth_proto_oper[0x20]; 10017 10018 u8 ib_link_width_oper[0x10]; 10019 u8 ib_proto_oper[0x10]; 10020 10021 u8 reserved_at_160[0x1c]; 10022 u8 connector_type[0x4]; 10023 10024 u8 eth_proto_lp_advertise[0x20]; 10025 10026 u8 reserved_at_1a0[0x60]; 10027 }; 10028 10029 struct mlx5_ifc_mlcr_reg_bits { 10030 u8 reserved_at_0[0x8]; 10031 u8 local_port[0x8]; 10032 u8 reserved_at_10[0x20]; 10033 10034 u8 beacon_duration[0x10]; 10035 u8 reserved_at_40[0x10]; 10036 10037 u8 beacon_remain[0x10]; 10038 }; 10039 10040 struct mlx5_ifc_ptas_reg_bits { 10041 u8 reserved_at_0[0x20]; 10042 10043 u8 algorithm_options[0x10]; 10044 u8 reserved_at_30[0x4]; 10045 u8 repetitions_mode[0x4]; 10046 u8 num_of_repetitions[0x8]; 10047 10048 u8 grade_version[0x8]; 10049 u8 height_grade_type[0x4]; 10050 u8 phase_grade_type[0x4]; 10051 u8 height_grade_weight[0x8]; 10052 u8 phase_grade_weight[0x8]; 10053 10054 u8 gisim_measure_bits[0x10]; 10055 u8 adaptive_tap_measure_bits[0x10]; 10056 10057 u8 ber_bath_high_error_threshold[0x10]; 10058 u8 ber_bath_mid_error_threshold[0x10]; 10059 10060 u8 ber_bath_low_error_threshold[0x10]; 10061 u8 one_ratio_high_threshold[0x10]; 10062 10063 u8 one_ratio_high_mid_threshold[0x10]; 10064 u8 one_ratio_low_mid_threshold[0x10]; 10065 10066 u8 one_ratio_low_threshold[0x10]; 10067 u8 ndeo_error_threshold[0x10]; 10068 10069 u8 mixer_offset_step_size[0x10]; 10070 u8 reserved_at_110[0x8]; 10071 u8 mix90_phase_for_voltage_bath[0x8]; 10072 10073 u8 mixer_offset_start[0x10]; 10074 u8 mixer_offset_end[0x10]; 10075 10076 u8 reserved_at_140[0x15]; 10077 u8 ber_test_time[0xb]; 10078 }; 10079 10080 struct mlx5_ifc_pspa_reg_bits { 10081 u8 swid[0x8]; 10082 u8 local_port[0x8]; 10083 u8 sub_port[0x8]; 10084 u8 reserved_at_18[0x8]; 10085 10086 u8 reserved_at_20[0x20]; 10087 }; 10088 10089 struct mlx5_ifc_pqdr_reg_bits { 10090 u8 reserved_at_0[0x8]; 10091 u8 local_port[0x8]; 10092 u8 reserved_at_10[0x5]; 10093 u8 prio[0x3]; 10094 u8 reserved_at_18[0x6]; 10095 u8 mode[0x2]; 10096 10097 u8 reserved_at_20[0x20]; 10098 10099 u8 reserved_at_40[0x10]; 10100 u8 min_threshold[0x10]; 10101 10102 u8 reserved_at_60[0x10]; 10103 u8 max_threshold[0x10]; 10104 10105 u8 reserved_at_80[0x10]; 10106 u8 mark_probability_denominator[0x10]; 10107 10108 u8 reserved_at_a0[0x60]; 10109 }; 10110 10111 struct mlx5_ifc_ppsc_reg_bits { 10112 u8 reserved_at_0[0x8]; 10113 u8 local_port[0x8]; 10114 u8 reserved_at_10[0x10]; 10115 10116 u8 reserved_at_20[0x60]; 10117 10118 u8 reserved_at_80[0x1c]; 10119 u8 wrps_admin[0x4]; 10120 10121 u8 reserved_at_a0[0x1c]; 10122 u8 wrps_status[0x4]; 10123 10124 u8 reserved_at_c0[0x8]; 10125 u8 up_threshold[0x8]; 10126 u8 reserved_at_d0[0x8]; 10127 u8 down_threshold[0x8]; 10128 10129 u8 reserved_at_e0[0x20]; 10130 10131 u8 reserved_at_100[0x1c]; 10132 u8 srps_admin[0x4]; 10133 10134 u8 reserved_at_120[0x1c]; 10135 u8 srps_status[0x4]; 10136 10137 u8 reserved_at_140[0x40]; 10138 }; 10139 10140 struct mlx5_ifc_pplr_reg_bits { 10141 u8 reserved_at_0[0x8]; 10142 u8 local_port[0x8]; 10143 u8 reserved_at_10[0x10]; 10144 10145 u8 reserved_at_20[0x8]; 10146 u8 lb_cap[0x8]; 10147 u8 reserved_at_30[0x8]; 10148 u8 lb_en[0x8]; 10149 }; 10150 10151 struct mlx5_ifc_pplm_reg_bits { 10152 u8 reserved_at_0[0x8]; 10153 u8 local_port[0x8]; 10154 u8 reserved_at_10[0x10]; 10155 10156 u8 reserved_at_20[0x20]; 10157 10158 u8 port_profile_mode[0x8]; 10159 u8 static_port_profile[0x8]; 10160 u8 active_port_profile[0x8]; 10161 u8 reserved_at_58[0x8]; 10162 10163 u8 retransmission_active[0x8]; 10164 u8 fec_mode_active[0x18]; 10165 10166 u8 rs_fec_correction_bypass_cap[0x4]; 10167 u8 reserved_at_84[0x8]; 10168 u8 fec_override_cap_56g[0x4]; 10169 u8 fec_override_cap_100g[0x4]; 10170 u8 fec_override_cap_50g[0x4]; 10171 u8 fec_override_cap_25g[0x4]; 10172 u8 fec_override_cap_10g_40g[0x4]; 10173 10174 u8 rs_fec_correction_bypass_admin[0x4]; 10175 u8 reserved_at_a4[0x8]; 10176 u8 fec_override_admin_56g[0x4]; 10177 u8 fec_override_admin_100g[0x4]; 10178 u8 fec_override_admin_50g[0x4]; 10179 u8 fec_override_admin_25g[0x4]; 10180 u8 fec_override_admin_10g_40g[0x4]; 10181 10182 u8 fec_override_cap_400g_8x[0x10]; 10183 u8 fec_override_cap_200g_4x[0x10]; 10184 10185 u8 fec_override_cap_100g_2x[0x10]; 10186 u8 fec_override_cap_50g_1x[0x10]; 10187 10188 u8 fec_override_admin_400g_8x[0x10]; 10189 u8 fec_override_admin_200g_4x[0x10]; 10190 10191 u8 fec_override_admin_100g_2x[0x10]; 10192 u8 fec_override_admin_50g_1x[0x10]; 10193 10194 u8 fec_override_cap_800g_8x[0x10]; 10195 u8 fec_override_cap_400g_4x[0x10]; 10196 10197 u8 fec_override_cap_200g_2x[0x10]; 10198 u8 fec_override_cap_100g_1x[0x10]; 10199 10200 u8 reserved_at_180[0xa0]; 10201 10202 u8 fec_override_admin_800g_8x[0x10]; 10203 u8 fec_override_admin_400g_4x[0x10]; 10204 10205 u8 fec_override_admin_200g_2x[0x10]; 10206 u8 fec_override_admin_100g_1x[0x10]; 10207 10208 u8 reserved_at_260[0x60]; 10209 10210 u8 fec_override_cap_1600g_8x[0x10]; 10211 u8 fec_override_cap_800g_4x[0x10]; 10212 10213 u8 fec_override_cap_400g_2x[0x10]; 10214 u8 fec_override_cap_200g_1x[0x10]; 10215 10216 u8 fec_override_admin_1600g_8x[0x10]; 10217 u8 fec_override_admin_800g_4x[0x10]; 10218 10219 u8 fec_override_admin_400g_2x[0x10]; 10220 u8 fec_override_admin_200g_1x[0x10]; 10221 10222 u8 reserved_at_340[0x80]; 10223 }; 10224 10225 struct mlx5_ifc_ppcnt_reg_bits { 10226 u8 swid[0x8]; 10227 u8 local_port[0x8]; 10228 u8 pnat[0x2]; 10229 u8 reserved_at_12[0x8]; 10230 u8 grp[0x6]; 10231 10232 u8 clr[0x1]; 10233 u8 reserved_at_21[0x13]; 10234 u8 plane_ind[0x4]; 10235 u8 reserved_at_38[0x3]; 10236 u8 prio_tc[0x5]; 10237 10238 union mlx5_ifc_eth_cntrs_grp_data_layout_auto_bits counter_set; 10239 }; 10240 10241 struct mlx5_ifc_mpein_reg_bits { 10242 u8 reserved_at_0[0x2]; 10243 u8 depth[0x6]; 10244 u8 pcie_index[0x8]; 10245 u8 node[0x8]; 10246 u8 reserved_at_18[0x8]; 10247 10248 u8 capability_mask[0x20]; 10249 10250 u8 reserved_at_40[0x8]; 10251 u8 link_width_enabled[0x8]; 10252 u8 link_speed_enabled[0x10]; 10253 10254 u8 lane0_physical_position[0x8]; 10255 u8 link_width_active[0x8]; 10256 u8 link_speed_active[0x10]; 10257 10258 u8 num_of_pfs[0x10]; 10259 u8 num_of_vfs[0x10]; 10260 10261 u8 bdf0[0x10]; 10262 u8 reserved_at_b0[0x10]; 10263 10264 u8 max_read_request_size[0x4]; 10265 u8 max_payload_size[0x4]; 10266 u8 reserved_at_c8[0x5]; 10267 u8 pwr_status[0x3]; 10268 u8 port_type[0x4]; 10269 u8 reserved_at_d4[0xb]; 10270 u8 lane_reversal[0x1]; 10271 10272 u8 reserved_at_e0[0x14]; 10273 u8 pci_power[0xc]; 10274 10275 u8 reserved_at_100[0x20]; 10276 10277 u8 device_status[0x10]; 10278 u8 port_state[0x8]; 10279 u8 reserved_at_138[0x8]; 10280 10281 u8 reserved_at_140[0x10]; 10282 u8 receiver_detect_result[0x10]; 10283 10284 u8 reserved_at_160[0x20]; 10285 }; 10286 10287 struct mlx5_ifc_mpcnt_reg_bits { 10288 u8 reserved_at_0[0x8]; 10289 u8 pcie_index[0x8]; 10290 u8 reserved_at_10[0xa]; 10291 u8 grp[0x6]; 10292 10293 u8 clr[0x1]; 10294 u8 reserved_at_21[0x1f]; 10295 10296 union mlx5_ifc_pcie_cntrs_grp_data_layout_auto_bits counter_set; 10297 }; 10298 10299 struct mlx5_ifc_ppad_reg_bits { 10300 u8 reserved_at_0[0x3]; 10301 u8 single_mac[0x1]; 10302 u8 reserved_at_4[0x4]; 10303 u8 local_port[0x8]; 10304 u8 mac_47_32[0x10]; 10305 10306 u8 mac_31_0[0x20]; 10307 10308 u8 reserved_at_40[0x40]; 10309 }; 10310 10311 struct mlx5_ifc_pmtu_reg_bits { 10312 u8 reserved_at_0[0x8]; 10313 u8 local_port[0x8]; 10314 u8 reserved_at_10[0x10]; 10315 10316 u8 max_mtu[0x10]; 10317 u8 reserved_at_30[0x10]; 10318 10319 u8 admin_mtu[0x10]; 10320 u8 reserved_at_50[0x10]; 10321 10322 u8 oper_mtu[0x10]; 10323 u8 reserved_at_70[0x10]; 10324 }; 10325 10326 struct mlx5_ifc_pmpr_reg_bits { 10327 u8 reserved_at_0[0x8]; 10328 u8 module[0x8]; 10329 u8 reserved_at_10[0x10]; 10330 10331 u8 reserved_at_20[0x18]; 10332 u8 attenuation_5g[0x8]; 10333 10334 u8 reserved_at_40[0x18]; 10335 u8 attenuation_7g[0x8]; 10336 10337 u8 reserved_at_60[0x18]; 10338 u8 attenuation_12g[0x8]; 10339 }; 10340 10341 struct mlx5_ifc_pmpe_reg_bits { 10342 u8 reserved_at_0[0x8]; 10343 u8 module[0x8]; 10344 u8 reserved_at_10[0xc]; 10345 u8 module_status[0x4]; 10346 10347 u8 reserved_at_20[0x60]; 10348 }; 10349 10350 struct mlx5_ifc_pmpc_reg_bits { 10351 u8 module_state_updated[32][0x8]; 10352 }; 10353 10354 struct mlx5_ifc_pmlpn_reg_bits { 10355 u8 reserved_at_0[0x4]; 10356 u8 mlpn_status[0x4]; 10357 u8 local_port[0x8]; 10358 u8 reserved_at_10[0x10]; 10359 10360 u8 e[0x1]; 10361 u8 reserved_at_21[0x1f]; 10362 }; 10363 10364 struct mlx5_ifc_pmlp_reg_bits { 10365 u8 rxtx[0x1]; 10366 u8 reserved_at_1[0x7]; 10367 u8 local_port[0x8]; 10368 u8 reserved_at_10[0x8]; 10369 u8 width[0x8]; 10370 10371 u8 lane0_module_mapping[0x20]; 10372 10373 u8 lane1_module_mapping[0x20]; 10374 10375 u8 lane2_module_mapping[0x20]; 10376 10377 u8 lane3_module_mapping[0x20]; 10378 10379 u8 reserved_at_a0[0x160]; 10380 }; 10381 10382 struct mlx5_ifc_pmaos_reg_bits { 10383 u8 reserved_at_0[0x8]; 10384 u8 module[0x8]; 10385 u8 reserved_at_10[0x4]; 10386 u8 admin_status[0x4]; 10387 u8 reserved_at_18[0x4]; 10388 u8 oper_status[0x4]; 10389 10390 u8 ase[0x1]; 10391 u8 ee[0x1]; 10392 u8 reserved_at_22[0x1c]; 10393 u8 e[0x2]; 10394 10395 u8 reserved_at_40[0x40]; 10396 }; 10397 10398 struct mlx5_ifc_plpc_reg_bits { 10399 u8 reserved_at_0[0x4]; 10400 u8 profile_id[0xc]; 10401 u8 reserved_at_10[0x4]; 10402 u8 proto_mask[0x4]; 10403 u8 reserved_at_18[0x8]; 10404 10405 u8 reserved_at_20[0x10]; 10406 u8 lane_speed[0x10]; 10407 10408 u8 reserved_at_40[0x17]; 10409 u8 lpbf[0x1]; 10410 u8 fec_mode_policy[0x8]; 10411 10412 u8 retransmission_capability[0x8]; 10413 u8 fec_mode_capability[0x18]; 10414 10415 u8 retransmission_support_admin[0x8]; 10416 u8 fec_mode_support_admin[0x18]; 10417 10418 u8 retransmission_request_admin[0x8]; 10419 u8 fec_mode_request_admin[0x18]; 10420 10421 u8 reserved_at_c0[0x80]; 10422 }; 10423 10424 struct mlx5_ifc_plib_reg_bits { 10425 u8 reserved_at_0[0x8]; 10426 u8 local_port[0x8]; 10427 u8 reserved_at_10[0x8]; 10428 u8 ib_port[0x8]; 10429 10430 u8 reserved_at_20[0x60]; 10431 }; 10432 10433 struct mlx5_ifc_plbf_reg_bits { 10434 u8 reserved_at_0[0x8]; 10435 u8 local_port[0x8]; 10436 u8 reserved_at_10[0xd]; 10437 u8 lbf_mode[0x3]; 10438 10439 u8 reserved_at_20[0x20]; 10440 }; 10441 10442 struct mlx5_ifc_pipg_reg_bits { 10443 u8 reserved_at_0[0x8]; 10444 u8 local_port[0x8]; 10445 u8 reserved_at_10[0x10]; 10446 10447 u8 dic[0x1]; 10448 u8 reserved_at_21[0x19]; 10449 u8 ipg[0x4]; 10450 u8 reserved_at_3e[0x2]; 10451 }; 10452 10453 struct mlx5_ifc_pifr_reg_bits { 10454 u8 reserved_at_0[0x8]; 10455 u8 local_port[0x8]; 10456 u8 reserved_at_10[0x10]; 10457 10458 u8 reserved_at_20[0xe0]; 10459 10460 u8 port_filter[8][0x20]; 10461 10462 u8 port_filter_update_en[8][0x20]; 10463 }; 10464 10465 struct mlx5_ifc_pfcc_reg_bits { 10466 u8 reserved_at_0[0x8]; 10467 u8 local_port[0x8]; 10468 u8 reserved_at_10[0xb]; 10469 u8 ppan_mask_n[0x1]; 10470 u8 minor_stall_mask[0x1]; 10471 u8 critical_stall_mask[0x1]; 10472 u8 reserved_at_1e[0x2]; 10473 10474 u8 ppan[0x4]; 10475 u8 reserved_at_24[0x4]; 10476 u8 prio_mask_tx[0x8]; 10477 u8 reserved_at_30[0x8]; 10478 u8 prio_mask_rx[0x8]; 10479 10480 u8 pptx[0x1]; 10481 u8 aptx[0x1]; 10482 u8 pptx_mask_n[0x1]; 10483 u8 reserved_at_43[0x5]; 10484 u8 pfctx[0x8]; 10485 u8 reserved_at_50[0x10]; 10486 10487 u8 pprx[0x1]; 10488 u8 aprx[0x1]; 10489 u8 pprx_mask_n[0x1]; 10490 u8 reserved_at_63[0x5]; 10491 u8 pfcrx[0x8]; 10492 u8 reserved_at_70[0x10]; 10493 10494 u8 device_stall_minor_watermark[0x10]; 10495 u8 device_stall_critical_watermark[0x10]; 10496 10497 u8 reserved_at_a0[0x60]; 10498 }; 10499 10500 struct mlx5_ifc_pelc_reg_bits { 10501 u8 op[0x4]; 10502 u8 reserved_at_4[0x4]; 10503 u8 local_port[0x8]; 10504 u8 reserved_at_10[0x10]; 10505 10506 u8 op_admin[0x8]; 10507 u8 op_capability[0x8]; 10508 u8 op_request[0x8]; 10509 u8 op_active[0x8]; 10510 10511 u8 admin[0x40]; 10512 10513 u8 capability[0x40]; 10514 10515 u8 request[0x40]; 10516 10517 u8 active[0x40]; 10518 10519 u8 reserved_at_140[0x80]; 10520 }; 10521 10522 struct mlx5_ifc_peir_reg_bits { 10523 u8 reserved_at_0[0x8]; 10524 u8 local_port[0x8]; 10525 u8 reserved_at_10[0x10]; 10526 10527 u8 reserved_at_20[0xc]; 10528 u8 error_count[0x4]; 10529 u8 reserved_at_30[0x10]; 10530 10531 u8 reserved_at_40[0xc]; 10532 u8 lane[0x4]; 10533 u8 reserved_at_50[0x8]; 10534 u8 error_type[0x8]; 10535 }; 10536 10537 struct mlx5_ifc_mpegc_reg_bits { 10538 u8 reserved_at_0[0x30]; 10539 u8 field_select[0x10]; 10540 10541 u8 tx_overflow_sense[0x1]; 10542 u8 mark_cqe[0x1]; 10543 u8 mark_cnp[0x1]; 10544 u8 reserved_at_43[0x1b]; 10545 u8 tx_lossy_overflow_oper[0x2]; 10546 10547 u8 reserved_at_60[0x100]; 10548 }; 10549 10550 struct mlx5_ifc_mpir_reg_bits { 10551 u8 sdm[0x1]; 10552 u8 reserved_at_1[0x1b]; 10553 u8 host_buses[0x4]; 10554 10555 u8 reserved_at_20[0x20]; 10556 10557 u8 local_port[0x8]; 10558 u8 reserved_at_28[0x18]; 10559 10560 u8 reserved_at_60[0x20]; 10561 }; 10562 10563 enum { 10564 MLX5_MTUTC_FREQ_ADJ_UNITS_PPB = 0x0, 10565 MLX5_MTUTC_FREQ_ADJ_UNITS_SCALED_PPM = 0x1, 10566 }; 10567 10568 enum { 10569 MLX5_MTUTC_OPERATION_SET_TIME_IMMEDIATE = 0x1, 10570 MLX5_MTUTC_OPERATION_ADJUST_TIME = 0x2, 10571 MLX5_MTUTC_OPERATION_ADJUST_FREQ_UTC = 0x3, 10572 }; 10573 10574 struct mlx5_ifc_mtutc_reg_bits { 10575 u8 reserved_at_0[0x5]; 10576 u8 freq_adj_units[0x3]; 10577 u8 reserved_at_8[0x3]; 10578 u8 log_max_freq_adjustment[0x5]; 10579 10580 u8 reserved_at_10[0xc]; 10581 u8 operation[0x4]; 10582 10583 u8 freq_adjustment[0x20]; 10584 10585 u8 reserved_at_40[0x40]; 10586 10587 u8 utc_sec[0x20]; 10588 10589 u8 reserved_at_a0[0x2]; 10590 u8 utc_nsec[0x1e]; 10591 10592 u8 time_adjustment[0x20]; 10593 }; 10594 10595 struct mlx5_ifc_pcam_enhanced_features_bits { 10596 u8 reserved_at_0[0x10]; 10597 u8 ppcnt_recovery_counters[0x1]; 10598 u8 reserved_at_11[0xc]; 10599 u8 fec_200G_per_lane_in_pplm[0x1]; 10600 u8 reserved_at_1e[0x2a]; 10601 u8 fec_100G_per_lane_in_pplm[0x1]; 10602 u8 reserved_at_49[0x1f]; 10603 u8 fec_50G_per_lane_in_pplm[0x1]; 10604 u8 reserved_at_69[0x4]; 10605 u8 rx_icrc_encapsulated_counter[0x1]; 10606 u8 reserved_at_6e[0x4]; 10607 u8 ptys_extended_ethernet[0x1]; 10608 u8 reserved_at_73[0x3]; 10609 u8 pfcc_mask[0x1]; 10610 u8 reserved_at_77[0x3]; 10611 u8 per_lane_error_counters[0x1]; 10612 u8 rx_buffer_fullness_counters[0x1]; 10613 u8 ptys_connector_type[0x1]; 10614 u8 reserved_at_7d[0x1]; 10615 u8 ppcnt_discard_group[0x1]; 10616 u8 ppcnt_statistical_group[0x1]; 10617 }; 10618 10619 struct mlx5_ifc_pcam_regs_5000_to_507f_bits { 10620 u8 port_access_reg_cap_mask_127_to_96[0x20]; 10621 u8 port_access_reg_cap_mask_95_to_64[0x20]; 10622 10623 u8 port_access_reg_cap_mask_63_to_36[0x1c]; 10624 u8 pplm[0x1]; 10625 u8 port_access_reg_cap_mask_34_to_32[0x3]; 10626 10627 u8 port_access_reg_cap_mask_31_to_13[0x13]; 10628 u8 pbmc[0x1]; 10629 u8 pptb[0x1]; 10630 u8 port_access_reg_cap_mask_10_to_09[0x2]; 10631 u8 ppcnt[0x1]; 10632 u8 port_access_reg_cap_mask_07_to_00[0x8]; 10633 }; 10634 10635 struct mlx5_ifc_pcam_reg_bits { 10636 u8 reserved_at_0[0x8]; 10637 u8 feature_group[0x8]; 10638 u8 reserved_at_10[0x8]; 10639 u8 access_reg_group[0x8]; 10640 10641 u8 reserved_at_20[0x20]; 10642 10643 union { 10644 struct mlx5_ifc_pcam_regs_5000_to_507f_bits regs_5000_to_507f; 10645 u8 reserved_at_0[0x80]; 10646 } port_access_reg_cap_mask; 10647 10648 u8 reserved_at_c0[0x80]; 10649 10650 union { 10651 struct mlx5_ifc_pcam_enhanced_features_bits enhanced_features; 10652 u8 reserved_at_0[0x80]; 10653 } feature_cap_mask; 10654 10655 u8 reserved_at_1c0[0xc0]; 10656 }; 10657 10658 struct mlx5_ifc_mcam_enhanced_features_bits { 10659 u8 reserved_at_0[0x50]; 10660 u8 mtutc_freq_adj_units[0x1]; 10661 u8 mtutc_time_adjustment_extended_range[0x1]; 10662 u8 reserved_at_52[0xb]; 10663 u8 mcia_32dwords[0x1]; 10664 u8 out_pulse_duration_ns[0x1]; 10665 u8 npps_period[0x1]; 10666 u8 reserved_at_60[0xa]; 10667 u8 reset_state[0x1]; 10668 u8 ptpcyc2realtime_modify[0x1]; 10669 u8 reserved_at_6c[0x2]; 10670 u8 pci_status_and_power[0x1]; 10671 u8 reserved_at_6f[0x5]; 10672 u8 mark_tx_action_cnp[0x1]; 10673 u8 mark_tx_action_cqe[0x1]; 10674 u8 dynamic_tx_overflow[0x1]; 10675 u8 reserved_at_77[0x4]; 10676 u8 pcie_outbound_stalled[0x1]; 10677 u8 tx_overflow_buffer_pkt[0x1]; 10678 u8 mtpps_enh_out_per_adj[0x1]; 10679 u8 mtpps_fs[0x1]; 10680 u8 pcie_performance_group[0x1]; 10681 }; 10682 10683 struct mlx5_ifc_mcam_access_reg_bits { 10684 u8 reserved_at_0[0x1c]; 10685 u8 mcda[0x1]; 10686 u8 mcc[0x1]; 10687 u8 mcqi[0x1]; 10688 u8 mcqs[0x1]; 10689 10690 u8 regs_95_to_90[0x6]; 10691 u8 mpir[0x1]; 10692 u8 regs_88_to_87[0x2]; 10693 u8 mpegc[0x1]; 10694 u8 mtutc[0x1]; 10695 u8 regs_84_to_68[0x11]; 10696 u8 tracer_registers[0x4]; 10697 10698 u8 regs_63_to_46[0x12]; 10699 u8 mrtc[0x1]; 10700 u8 regs_44_to_41[0x4]; 10701 u8 mfrl[0x1]; 10702 u8 regs_39_to_32[0x8]; 10703 10704 u8 regs_31_to_11[0x15]; 10705 u8 mtmp[0x1]; 10706 u8 regs_9_to_0[0xa]; 10707 }; 10708 10709 struct mlx5_ifc_mcam_access_reg_bits1 { 10710 u8 regs_127_to_96[0x20]; 10711 10712 u8 regs_95_to_64[0x20]; 10713 10714 u8 regs_63_to_32[0x20]; 10715 10716 u8 regs_31_to_0[0x20]; 10717 }; 10718 10719 struct mlx5_ifc_mcam_access_reg_bits2 { 10720 u8 regs_127_to_99[0x1d]; 10721 u8 mirc[0x1]; 10722 u8 regs_97_to_96[0x2]; 10723 10724 u8 regs_95_to_87[0x09]; 10725 u8 synce_registers[0x2]; 10726 u8 regs_84_to_64[0x15]; 10727 10728 u8 regs_63_to_32[0x20]; 10729 10730 u8 regs_31_to_0[0x20]; 10731 }; 10732 10733 struct mlx5_ifc_mcam_access_reg_bits3 { 10734 u8 regs_127_to_96[0x20]; 10735 10736 u8 regs_95_to_64[0x20]; 10737 10738 u8 regs_63_to_32[0x20]; 10739 10740 u8 regs_31_to_3[0x1d]; 10741 u8 mrtcq[0x1]; 10742 u8 mtctr[0x1]; 10743 u8 mtptm[0x1]; 10744 }; 10745 10746 struct mlx5_ifc_mcam_reg_bits { 10747 u8 reserved_at_0[0x8]; 10748 u8 feature_group[0x8]; 10749 u8 reserved_at_10[0x8]; 10750 u8 access_reg_group[0x8]; 10751 10752 u8 reserved_at_20[0x20]; 10753 10754 union { 10755 struct mlx5_ifc_mcam_access_reg_bits access_regs; 10756 struct mlx5_ifc_mcam_access_reg_bits1 access_regs1; 10757 struct mlx5_ifc_mcam_access_reg_bits2 access_regs2; 10758 struct mlx5_ifc_mcam_access_reg_bits3 access_regs3; 10759 u8 reserved_at_0[0x80]; 10760 } mng_access_reg_cap_mask; 10761 10762 u8 reserved_at_c0[0x80]; 10763 10764 union { 10765 struct mlx5_ifc_mcam_enhanced_features_bits enhanced_features; 10766 u8 reserved_at_0[0x80]; 10767 } mng_feature_cap_mask; 10768 10769 u8 reserved_at_1c0[0x80]; 10770 }; 10771 10772 struct mlx5_ifc_qcam_access_reg_cap_mask { 10773 u8 qcam_access_reg_cap_mask_127_to_20[0x6C]; 10774 u8 qpdpm[0x1]; 10775 u8 qcam_access_reg_cap_mask_18_to_4[0x0F]; 10776 u8 qdpm[0x1]; 10777 u8 qpts[0x1]; 10778 u8 qcap[0x1]; 10779 u8 qcam_access_reg_cap_mask_0[0x1]; 10780 }; 10781 10782 struct mlx5_ifc_qcam_qos_feature_cap_mask { 10783 u8 qcam_qos_feature_cap_mask_127_to_1[0x7F]; 10784 u8 qpts_trust_both[0x1]; 10785 }; 10786 10787 struct mlx5_ifc_qcam_reg_bits { 10788 u8 reserved_at_0[0x8]; 10789 u8 feature_group[0x8]; 10790 u8 reserved_at_10[0x8]; 10791 u8 access_reg_group[0x8]; 10792 u8 reserved_at_20[0x20]; 10793 10794 union { 10795 struct mlx5_ifc_qcam_access_reg_cap_mask reg_cap; 10796 u8 reserved_at_0[0x80]; 10797 } qos_access_reg_cap_mask; 10798 10799 u8 reserved_at_c0[0x80]; 10800 10801 union { 10802 struct mlx5_ifc_qcam_qos_feature_cap_mask feature_cap; 10803 u8 reserved_at_0[0x80]; 10804 } qos_feature_cap_mask; 10805 10806 u8 reserved_at_1c0[0x80]; 10807 }; 10808 10809 struct mlx5_ifc_core_dump_reg_bits { 10810 u8 reserved_at_0[0x18]; 10811 u8 core_dump_type[0x8]; 10812 10813 u8 reserved_at_20[0x30]; 10814 u8 vhca_id[0x10]; 10815 10816 u8 reserved_at_60[0x8]; 10817 u8 qpn[0x18]; 10818 u8 reserved_at_80[0x180]; 10819 }; 10820 10821 struct mlx5_ifc_pcap_reg_bits { 10822 u8 reserved_at_0[0x8]; 10823 u8 local_port[0x8]; 10824 u8 reserved_at_10[0x10]; 10825 10826 u8 port_capability_mask[4][0x20]; 10827 }; 10828 10829 struct mlx5_ifc_paos_reg_bits { 10830 u8 swid[0x8]; 10831 u8 local_port[0x8]; 10832 u8 reserved_at_10[0x4]; 10833 u8 admin_status[0x4]; 10834 u8 reserved_at_18[0x4]; 10835 u8 oper_status[0x4]; 10836 10837 u8 ase[0x1]; 10838 u8 ee[0x1]; 10839 u8 reserved_at_22[0x1c]; 10840 u8 e[0x2]; 10841 10842 u8 reserved_at_40[0x40]; 10843 }; 10844 10845 struct mlx5_ifc_pamp_reg_bits { 10846 u8 reserved_at_0[0x8]; 10847 u8 opamp_group[0x8]; 10848 u8 reserved_at_10[0xc]; 10849 u8 opamp_group_type[0x4]; 10850 10851 u8 start_index[0x10]; 10852 u8 reserved_at_30[0x4]; 10853 u8 num_of_indices[0xc]; 10854 10855 u8 index_data[18][0x10]; 10856 }; 10857 10858 struct mlx5_ifc_pcmr_reg_bits { 10859 u8 reserved_at_0[0x8]; 10860 u8 local_port[0x8]; 10861 u8 reserved_at_10[0x10]; 10862 10863 u8 entropy_force_cap[0x1]; 10864 u8 entropy_calc_cap[0x1]; 10865 u8 entropy_gre_calc_cap[0x1]; 10866 u8 reserved_at_23[0xf]; 10867 u8 rx_ts_over_crc_cap[0x1]; 10868 u8 reserved_at_33[0xb]; 10869 u8 fcs_cap[0x1]; 10870 u8 reserved_at_3f[0x1]; 10871 10872 u8 entropy_force[0x1]; 10873 u8 entropy_calc[0x1]; 10874 u8 entropy_gre_calc[0x1]; 10875 u8 reserved_at_43[0xf]; 10876 u8 rx_ts_over_crc[0x1]; 10877 u8 reserved_at_53[0xb]; 10878 u8 fcs_chk[0x1]; 10879 u8 reserved_at_5f[0x1]; 10880 }; 10881 10882 struct mlx5_ifc_lane_2_module_mapping_bits { 10883 u8 reserved_at_0[0x4]; 10884 u8 rx_lane[0x4]; 10885 u8 reserved_at_8[0x4]; 10886 u8 tx_lane[0x4]; 10887 u8 reserved_at_10[0x8]; 10888 u8 module[0x8]; 10889 }; 10890 10891 struct mlx5_ifc_bufferx_reg_bits { 10892 u8 reserved_at_0[0x6]; 10893 u8 lossy[0x1]; 10894 u8 epsb[0x1]; 10895 u8 reserved_at_8[0x8]; 10896 u8 size[0x10]; 10897 10898 u8 xoff_threshold[0x10]; 10899 u8 xon_threshold[0x10]; 10900 }; 10901 10902 struct mlx5_ifc_set_node_in_bits { 10903 u8 node_description[64][0x8]; 10904 }; 10905 10906 struct mlx5_ifc_register_power_settings_bits { 10907 u8 reserved_at_0[0x18]; 10908 u8 power_settings_level[0x8]; 10909 10910 u8 reserved_at_20[0x60]; 10911 }; 10912 10913 struct mlx5_ifc_register_host_endianness_bits { 10914 u8 he[0x1]; 10915 u8 reserved_at_1[0x1f]; 10916 10917 u8 reserved_at_20[0x60]; 10918 }; 10919 10920 struct mlx5_ifc_umr_pointer_desc_argument_bits { 10921 u8 reserved_at_0[0x20]; 10922 10923 u8 mkey[0x20]; 10924 10925 u8 addressh_63_32[0x20]; 10926 10927 u8 addressl_31_0[0x20]; 10928 }; 10929 10930 struct mlx5_ifc_ud_adrs_vector_bits { 10931 u8 dc_key[0x40]; 10932 10933 u8 ext[0x1]; 10934 u8 reserved_at_41[0x7]; 10935 u8 destination_qp_dct[0x18]; 10936 10937 u8 static_rate[0x4]; 10938 u8 sl_eth_prio[0x4]; 10939 u8 fl[0x1]; 10940 u8 mlid[0x7]; 10941 u8 rlid_udp_sport[0x10]; 10942 10943 u8 reserved_at_80[0x20]; 10944 10945 u8 rmac_47_16[0x20]; 10946 10947 u8 rmac_15_0[0x10]; 10948 u8 tclass[0x8]; 10949 u8 hop_limit[0x8]; 10950 10951 u8 reserved_at_e0[0x1]; 10952 u8 grh[0x1]; 10953 u8 reserved_at_e2[0x2]; 10954 u8 src_addr_index[0x8]; 10955 u8 flow_label[0x14]; 10956 10957 u8 rgid_rip[16][0x8]; 10958 }; 10959 10960 struct mlx5_ifc_pages_req_event_bits { 10961 u8 reserved_at_0[0x10]; 10962 u8 function_id[0x10]; 10963 10964 u8 num_pages[0x20]; 10965 10966 u8 reserved_at_40[0xa0]; 10967 }; 10968 10969 struct mlx5_ifc_eqe_bits { 10970 u8 reserved_at_0[0x8]; 10971 u8 event_type[0x8]; 10972 u8 reserved_at_10[0x8]; 10973 u8 event_sub_type[0x8]; 10974 10975 u8 reserved_at_20[0xe0]; 10976 10977 union mlx5_ifc_event_auto_bits event_data; 10978 10979 u8 reserved_at_1e0[0x10]; 10980 u8 signature[0x8]; 10981 u8 reserved_at_1f8[0x7]; 10982 u8 owner[0x1]; 10983 }; 10984 10985 enum { 10986 MLX5_CMD_QUEUE_ENTRY_TYPE_PCIE_CMD_IF_TRANSPORT = 0x7, 10987 }; 10988 10989 struct mlx5_ifc_cmd_queue_entry_bits { 10990 u8 type[0x8]; 10991 u8 reserved_at_8[0x18]; 10992 10993 u8 input_length[0x20]; 10994 10995 u8 input_mailbox_pointer_63_32[0x20]; 10996 10997 u8 input_mailbox_pointer_31_9[0x17]; 10998 u8 reserved_at_77[0x9]; 10999 11000 u8 command_input_inline_data[16][0x8]; 11001 11002 u8 command_output_inline_data[16][0x8]; 11003 11004 u8 output_mailbox_pointer_63_32[0x20]; 11005 11006 u8 output_mailbox_pointer_31_9[0x17]; 11007 u8 reserved_at_1b7[0x9]; 11008 11009 u8 output_length[0x20]; 11010 11011 u8 token[0x8]; 11012 u8 signature[0x8]; 11013 u8 reserved_at_1f0[0x8]; 11014 u8 status[0x7]; 11015 u8 ownership[0x1]; 11016 }; 11017 11018 struct mlx5_ifc_cmd_out_bits { 11019 u8 status[0x8]; 11020 u8 reserved_at_8[0x18]; 11021 11022 u8 syndrome[0x20]; 11023 11024 u8 command_output[0x20]; 11025 }; 11026 11027 struct mlx5_ifc_cmd_in_bits { 11028 u8 opcode[0x10]; 11029 u8 reserved_at_10[0x10]; 11030 11031 u8 reserved_at_20[0x10]; 11032 u8 op_mod[0x10]; 11033 11034 u8 command[][0x20]; 11035 }; 11036 11037 struct mlx5_ifc_cmd_if_box_bits { 11038 u8 mailbox_data[512][0x8]; 11039 11040 u8 reserved_at_1000[0x180]; 11041 11042 u8 next_pointer_63_32[0x20]; 11043 11044 u8 next_pointer_31_10[0x16]; 11045 u8 reserved_at_11b6[0xa]; 11046 11047 u8 block_number[0x20]; 11048 11049 u8 reserved_at_11e0[0x8]; 11050 u8 token[0x8]; 11051 u8 ctrl_signature[0x8]; 11052 u8 signature[0x8]; 11053 }; 11054 11055 struct mlx5_ifc_mtt_bits { 11056 u8 ptag_63_32[0x20]; 11057 11058 u8 ptag_31_8[0x18]; 11059 u8 reserved_at_38[0x6]; 11060 u8 wr_en[0x1]; 11061 u8 rd_en[0x1]; 11062 }; 11063 11064 struct mlx5_ifc_query_wol_rol_out_bits { 11065 u8 status[0x8]; 11066 u8 reserved_at_8[0x18]; 11067 11068 u8 syndrome[0x20]; 11069 11070 u8 reserved_at_40[0x10]; 11071 u8 rol_mode[0x8]; 11072 u8 wol_mode[0x8]; 11073 11074 u8 reserved_at_60[0x20]; 11075 }; 11076 11077 struct mlx5_ifc_query_wol_rol_in_bits { 11078 u8 opcode[0x10]; 11079 u8 reserved_at_10[0x10]; 11080 11081 u8 reserved_at_20[0x10]; 11082 u8 op_mod[0x10]; 11083 11084 u8 reserved_at_40[0x40]; 11085 }; 11086 11087 struct mlx5_ifc_set_wol_rol_out_bits { 11088 u8 status[0x8]; 11089 u8 reserved_at_8[0x18]; 11090 11091 u8 syndrome[0x20]; 11092 11093 u8 reserved_at_40[0x40]; 11094 }; 11095 11096 struct mlx5_ifc_set_wol_rol_in_bits { 11097 u8 opcode[0x10]; 11098 u8 reserved_at_10[0x10]; 11099 11100 u8 reserved_at_20[0x10]; 11101 u8 op_mod[0x10]; 11102 11103 u8 rol_mode_valid[0x1]; 11104 u8 wol_mode_valid[0x1]; 11105 u8 reserved_at_42[0xe]; 11106 u8 rol_mode[0x8]; 11107 u8 wol_mode[0x8]; 11108 11109 u8 reserved_at_60[0x20]; 11110 }; 11111 11112 enum { 11113 MLX5_INITIAL_SEG_NIC_INTERFACE_FULL_DRIVER = 0x0, 11114 MLX5_INITIAL_SEG_NIC_INTERFACE_DISABLED = 0x1, 11115 MLX5_INITIAL_SEG_NIC_INTERFACE_NO_DRAM_NIC = 0x2, 11116 MLX5_INITIAL_SEG_NIC_INTERFACE_SW_RESET = 0x7, 11117 }; 11118 11119 enum { 11120 MLX5_INITIAL_SEG_NIC_INTERFACE_SUPPORTED_FULL_DRIVER = 0x0, 11121 MLX5_INITIAL_SEG_NIC_INTERFACE_SUPPORTED_DISABLED = 0x1, 11122 MLX5_INITIAL_SEG_NIC_INTERFACE_SUPPORTED_NO_DRAM_NIC = 0x2, 11123 }; 11124 11125 enum { 11126 MLX5_INITIAL_SEG_HEALTH_SYNDROME_FW_INTERNAL_ERR = 0x1, 11127 MLX5_INITIAL_SEG_HEALTH_SYNDROME_DEAD_IRISC = 0x7, 11128 MLX5_INITIAL_SEG_HEALTH_SYNDROME_HW_FATAL_ERR = 0x8, 11129 MLX5_INITIAL_SEG_HEALTH_SYNDROME_FW_CRC_ERR = 0x9, 11130 MLX5_INITIAL_SEG_HEALTH_SYNDROME_ICM_FETCH_PCI_ERR = 0xa, 11131 MLX5_INITIAL_SEG_HEALTH_SYNDROME_ICM_PAGE_ERR = 0xb, 11132 MLX5_INITIAL_SEG_HEALTH_SYNDROME_ASYNCHRONOUS_EQ_BUF_OVERRUN = 0xc, 11133 MLX5_INITIAL_SEG_HEALTH_SYNDROME_EQ_IN_ERR = 0xd, 11134 MLX5_INITIAL_SEG_HEALTH_SYNDROME_EQ_INV = 0xe, 11135 MLX5_INITIAL_SEG_HEALTH_SYNDROME_FFSER_ERR = 0xf, 11136 MLX5_INITIAL_SEG_HEALTH_SYNDROME_HIGH_TEMP_ERR = 0x10, 11137 MLX5_INITIAL_SEG_HEALTH_SYNDROME_ICM_PCI_POISONED_ERR = 0x12, 11138 MLX5_INITIAL_SEG_HEALTH_SYNDROME_TRUST_LOCKDOWN_ERR = 0x13, 11139 }; 11140 11141 struct mlx5_ifc_initial_seg_bits { 11142 u8 fw_rev_minor[0x10]; 11143 u8 fw_rev_major[0x10]; 11144 11145 u8 cmd_interface_rev[0x10]; 11146 u8 fw_rev_subminor[0x10]; 11147 11148 u8 reserved_at_40[0x40]; 11149 11150 u8 cmdq_phy_addr_63_32[0x20]; 11151 11152 u8 cmdq_phy_addr_31_12[0x14]; 11153 u8 reserved_at_b4[0x2]; 11154 u8 nic_interface[0x2]; 11155 u8 log_cmdq_size[0x4]; 11156 u8 log_cmdq_stride[0x4]; 11157 11158 u8 command_doorbell_vector[0x20]; 11159 11160 u8 reserved_at_e0[0xf00]; 11161 11162 u8 initializing[0x1]; 11163 u8 reserved_at_fe1[0x4]; 11164 u8 nic_interface_supported[0x3]; 11165 u8 embedded_cpu[0x1]; 11166 u8 reserved_at_fe9[0x17]; 11167 11168 struct mlx5_ifc_health_buffer_bits health_buffer; 11169 11170 u8 no_dram_nic_offset[0x20]; 11171 11172 u8 reserved_at_1220[0x6e40]; 11173 11174 u8 reserved_at_8060[0x1f]; 11175 u8 clear_int[0x1]; 11176 11177 u8 health_syndrome[0x8]; 11178 u8 health_counter[0x18]; 11179 11180 u8 reserved_at_80a0[0x17fc0]; 11181 }; 11182 11183 struct mlx5_ifc_mtpps_reg_bits { 11184 u8 reserved_at_0[0xc]; 11185 u8 cap_number_of_pps_pins[0x4]; 11186 u8 reserved_at_10[0x4]; 11187 u8 cap_max_num_of_pps_in_pins[0x4]; 11188 u8 reserved_at_18[0x4]; 11189 u8 cap_max_num_of_pps_out_pins[0x4]; 11190 11191 u8 reserved_at_20[0x13]; 11192 u8 cap_log_min_npps_period[0x5]; 11193 u8 reserved_at_38[0x3]; 11194 u8 cap_log_min_out_pulse_duration_ns[0x5]; 11195 11196 u8 reserved_at_40[0x4]; 11197 u8 cap_pin_3_mode[0x4]; 11198 u8 reserved_at_48[0x4]; 11199 u8 cap_pin_2_mode[0x4]; 11200 u8 reserved_at_50[0x4]; 11201 u8 cap_pin_1_mode[0x4]; 11202 u8 reserved_at_58[0x4]; 11203 u8 cap_pin_0_mode[0x4]; 11204 11205 u8 reserved_at_60[0x4]; 11206 u8 cap_pin_7_mode[0x4]; 11207 u8 reserved_at_68[0x4]; 11208 u8 cap_pin_6_mode[0x4]; 11209 u8 reserved_at_70[0x4]; 11210 u8 cap_pin_5_mode[0x4]; 11211 u8 reserved_at_78[0x4]; 11212 u8 cap_pin_4_mode[0x4]; 11213 11214 u8 field_select[0x20]; 11215 u8 reserved_at_a0[0x20]; 11216 11217 u8 npps_period[0x40]; 11218 11219 u8 enable[0x1]; 11220 u8 reserved_at_101[0xb]; 11221 u8 pattern[0x4]; 11222 u8 reserved_at_110[0x4]; 11223 u8 pin_mode[0x4]; 11224 u8 pin[0x8]; 11225 11226 u8 reserved_at_120[0x2]; 11227 u8 out_pulse_duration_ns[0x1e]; 11228 11229 u8 time_stamp[0x40]; 11230 11231 u8 out_pulse_duration[0x10]; 11232 u8 out_periodic_adjustment[0x10]; 11233 u8 enhanced_out_periodic_adjustment[0x20]; 11234 11235 u8 reserved_at_1c0[0x20]; 11236 }; 11237 11238 struct mlx5_ifc_mtppse_reg_bits { 11239 u8 reserved_at_0[0x18]; 11240 u8 pin[0x8]; 11241 u8 event_arm[0x1]; 11242 u8 reserved_at_21[0x1b]; 11243 u8 event_generation_mode[0x4]; 11244 u8 reserved_at_40[0x40]; 11245 }; 11246 11247 struct mlx5_ifc_mcqs_reg_bits { 11248 u8 last_index_flag[0x1]; 11249 u8 reserved_at_1[0x7]; 11250 u8 fw_device[0x8]; 11251 u8 component_index[0x10]; 11252 11253 u8 reserved_at_20[0x10]; 11254 u8 identifier[0x10]; 11255 11256 u8 reserved_at_40[0x17]; 11257 u8 component_status[0x5]; 11258 u8 component_update_state[0x4]; 11259 11260 u8 last_update_state_changer_type[0x4]; 11261 u8 last_update_state_changer_host_id[0x4]; 11262 u8 reserved_at_68[0x18]; 11263 }; 11264 11265 struct mlx5_ifc_mcqi_cap_bits { 11266 u8 supported_info_bitmask[0x20]; 11267 11268 u8 component_size[0x20]; 11269 11270 u8 max_component_size[0x20]; 11271 11272 u8 log_mcda_word_size[0x4]; 11273 u8 reserved_at_64[0xc]; 11274 u8 mcda_max_write_size[0x10]; 11275 11276 u8 rd_en[0x1]; 11277 u8 reserved_at_81[0x1]; 11278 u8 match_chip_id[0x1]; 11279 u8 match_psid[0x1]; 11280 u8 check_user_timestamp[0x1]; 11281 u8 match_base_guid_mac[0x1]; 11282 u8 reserved_at_86[0x1a]; 11283 }; 11284 11285 struct mlx5_ifc_mcqi_version_bits { 11286 u8 reserved_at_0[0x2]; 11287 u8 build_time_valid[0x1]; 11288 u8 user_defined_time_valid[0x1]; 11289 u8 reserved_at_4[0x14]; 11290 u8 version_string_length[0x8]; 11291 11292 u8 version[0x20]; 11293 11294 u8 build_time[0x40]; 11295 11296 u8 user_defined_time[0x40]; 11297 11298 u8 build_tool_version[0x20]; 11299 11300 u8 reserved_at_e0[0x20]; 11301 11302 u8 version_string[92][0x8]; 11303 }; 11304 11305 struct mlx5_ifc_mcqi_activation_method_bits { 11306 u8 pending_server_ac_power_cycle[0x1]; 11307 u8 pending_server_dc_power_cycle[0x1]; 11308 u8 pending_server_reboot[0x1]; 11309 u8 pending_fw_reset[0x1]; 11310 u8 auto_activate[0x1]; 11311 u8 all_hosts_sync[0x1]; 11312 u8 device_hw_reset[0x1]; 11313 u8 reserved_at_7[0x19]; 11314 }; 11315 11316 union mlx5_ifc_mcqi_reg_data_bits { 11317 struct mlx5_ifc_mcqi_cap_bits mcqi_caps; 11318 struct mlx5_ifc_mcqi_version_bits mcqi_version; 11319 struct mlx5_ifc_mcqi_activation_method_bits mcqi_activation_mathod; 11320 }; 11321 11322 struct mlx5_ifc_mcqi_reg_bits { 11323 u8 read_pending_component[0x1]; 11324 u8 reserved_at_1[0xf]; 11325 u8 component_index[0x10]; 11326 11327 u8 reserved_at_20[0x20]; 11328 11329 u8 reserved_at_40[0x1b]; 11330 u8 info_type[0x5]; 11331 11332 u8 info_size[0x20]; 11333 11334 u8 offset[0x20]; 11335 11336 u8 reserved_at_a0[0x10]; 11337 u8 data_size[0x10]; 11338 11339 union mlx5_ifc_mcqi_reg_data_bits data[]; 11340 }; 11341 11342 struct mlx5_ifc_mcc_reg_bits { 11343 u8 reserved_at_0[0x4]; 11344 u8 time_elapsed_since_last_cmd[0xc]; 11345 u8 reserved_at_10[0x8]; 11346 u8 instruction[0x8]; 11347 11348 u8 reserved_at_20[0x10]; 11349 u8 component_index[0x10]; 11350 11351 u8 reserved_at_40[0x8]; 11352 u8 update_handle[0x18]; 11353 11354 u8 handle_owner_type[0x4]; 11355 u8 handle_owner_host_id[0x4]; 11356 u8 reserved_at_68[0x1]; 11357 u8 control_progress[0x7]; 11358 u8 error_code[0x8]; 11359 u8 reserved_at_78[0x4]; 11360 u8 control_state[0x4]; 11361 11362 u8 component_size[0x20]; 11363 11364 u8 reserved_at_a0[0x60]; 11365 }; 11366 11367 struct mlx5_ifc_mcda_reg_bits { 11368 u8 reserved_at_0[0x8]; 11369 u8 update_handle[0x18]; 11370 11371 u8 offset[0x20]; 11372 11373 u8 reserved_at_40[0x10]; 11374 u8 size[0x10]; 11375 11376 u8 reserved_at_60[0x20]; 11377 11378 u8 data[][0x20]; 11379 }; 11380 11381 enum { 11382 MLX5_MFRL_REG_PCI_RESET_METHOD_LINK_TOGGLE = 0, 11383 MLX5_MFRL_REG_PCI_RESET_METHOD_HOT_RESET = 1, 11384 }; 11385 11386 enum { 11387 MLX5_MFRL_REG_RESET_STATE_IDLE = 0, 11388 MLX5_MFRL_REG_RESET_STATE_IN_NEGOTIATION = 1, 11389 MLX5_MFRL_REG_RESET_STATE_RESET_IN_PROGRESS = 2, 11390 MLX5_MFRL_REG_RESET_STATE_NEG_TIMEOUT = 3, 11391 MLX5_MFRL_REG_RESET_STATE_NACK = 4, 11392 MLX5_MFRL_REG_RESET_STATE_UNLOAD_TIMEOUT = 5, 11393 }; 11394 11395 enum { 11396 MLX5_MFRL_REG_RESET_TYPE_FULL_CHIP = BIT(0), 11397 MLX5_MFRL_REG_RESET_TYPE_NET_PORT_ALIVE = BIT(1), 11398 }; 11399 11400 enum { 11401 MLX5_MFRL_REG_RESET_LEVEL0 = BIT(0), 11402 MLX5_MFRL_REG_RESET_LEVEL3 = BIT(3), 11403 MLX5_MFRL_REG_RESET_LEVEL6 = BIT(6), 11404 }; 11405 11406 struct mlx5_ifc_mfrl_reg_bits { 11407 u8 reserved_at_0[0x20]; 11408 11409 u8 reserved_at_20[0x2]; 11410 u8 pci_sync_for_fw_update_start[0x1]; 11411 u8 pci_sync_for_fw_update_resp[0x2]; 11412 u8 rst_type_sel[0x3]; 11413 u8 pci_reset_req_method[0x3]; 11414 u8 reserved_at_2b[0x1]; 11415 u8 reset_state[0x4]; 11416 u8 reset_type[0x8]; 11417 u8 reset_level[0x8]; 11418 }; 11419 11420 struct mlx5_ifc_mirc_reg_bits { 11421 u8 reserved_at_0[0x18]; 11422 u8 status_code[0x8]; 11423 11424 u8 reserved_at_20[0x20]; 11425 }; 11426 11427 struct mlx5_ifc_pddr_monitor_opcode_bits { 11428 u8 reserved_at_0[0x10]; 11429 u8 monitor_opcode[0x10]; 11430 }; 11431 11432 union mlx5_ifc_pddr_troubleshooting_page_status_opcode_auto_bits { 11433 struct mlx5_ifc_pddr_monitor_opcode_bits pddr_monitor_opcode; 11434 u8 reserved_at_0[0x20]; 11435 }; 11436 11437 enum { 11438 /* Monitor opcodes */ 11439 MLX5_PDDR_REG_TRBLSH_GROUP_OPCODE_MONITOR = 0x0, 11440 }; 11441 11442 struct mlx5_ifc_pddr_troubleshooting_page_bits { 11443 u8 reserved_at_0[0x10]; 11444 u8 group_opcode[0x10]; 11445 11446 union mlx5_ifc_pddr_troubleshooting_page_status_opcode_auto_bits status_opcode; 11447 11448 u8 reserved_at_40[0x20]; 11449 11450 u8 status_message[59][0x20]; 11451 }; 11452 11453 union mlx5_ifc_pddr_reg_page_data_auto_bits { 11454 struct mlx5_ifc_pddr_troubleshooting_page_bits pddr_troubleshooting_page; 11455 u8 reserved_at_0[0x7c0]; 11456 }; 11457 11458 enum { 11459 MLX5_PDDR_REG_PAGE_SELECT_TROUBLESHOOTING_INFO_PAGE = 0x1, 11460 }; 11461 11462 struct mlx5_ifc_pddr_reg_bits { 11463 u8 reserved_at_0[0x8]; 11464 u8 local_port[0x8]; 11465 u8 pnat[0x2]; 11466 u8 reserved_at_12[0xe]; 11467 11468 u8 reserved_at_20[0x18]; 11469 u8 page_select[0x8]; 11470 11471 union mlx5_ifc_pddr_reg_page_data_auto_bits page_data; 11472 }; 11473 11474 struct mlx5_ifc_mrtc_reg_bits { 11475 u8 time_synced[0x1]; 11476 u8 reserved_at_1[0x1f]; 11477 11478 u8 reserved_at_20[0x20]; 11479 11480 u8 time_h[0x20]; 11481 11482 u8 time_l[0x20]; 11483 }; 11484 11485 struct mlx5_ifc_mtcap_reg_bits { 11486 u8 reserved_at_0[0x19]; 11487 u8 sensor_count[0x7]; 11488 11489 u8 reserved_at_20[0x20]; 11490 11491 u8 sensor_map[0x40]; 11492 }; 11493 11494 struct mlx5_ifc_mtmp_reg_bits { 11495 u8 reserved_at_0[0x14]; 11496 u8 sensor_index[0xc]; 11497 11498 u8 reserved_at_20[0x10]; 11499 u8 temperature[0x10]; 11500 11501 u8 mte[0x1]; 11502 u8 mtr[0x1]; 11503 u8 reserved_at_42[0xe]; 11504 u8 max_temperature[0x10]; 11505 11506 u8 tee[0x2]; 11507 u8 reserved_at_62[0xe]; 11508 u8 temp_threshold_hi[0x10]; 11509 11510 u8 reserved_at_80[0x10]; 11511 u8 temp_threshold_lo[0x10]; 11512 11513 u8 reserved_at_a0[0x20]; 11514 11515 u8 sensor_name_hi[0x20]; 11516 u8 sensor_name_lo[0x20]; 11517 }; 11518 11519 struct mlx5_ifc_mtptm_reg_bits { 11520 u8 reserved_at_0[0x10]; 11521 u8 psta[0x1]; 11522 u8 reserved_at_11[0xf]; 11523 11524 u8 reserved_at_20[0x60]; 11525 }; 11526 11527 enum { 11528 MLX5_MTCTR_REQUEST_NOP = 0x0, 11529 MLX5_MTCTR_REQUEST_PTM_ROOT_CLOCK = 0x1, 11530 MLX5_MTCTR_REQUEST_FREE_RUNNING_COUNTER = 0x2, 11531 MLX5_MTCTR_REQUEST_REAL_TIME_CLOCK = 0x3, 11532 }; 11533 11534 struct mlx5_ifc_mtctr_reg_bits { 11535 u8 first_clock_timestamp_request[0x8]; 11536 u8 second_clock_timestamp_request[0x8]; 11537 u8 reserved_at_10[0x10]; 11538 11539 u8 first_clock_valid[0x1]; 11540 u8 second_clock_valid[0x1]; 11541 u8 reserved_at_22[0x1e]; 11542 11543 u8 first_clock_timestamp[0x40]; 11544 u8 second_clock_timestamp[0x40]; 11545 }; 11546 11547 union mlx5_ifc_ports_control_registers_document_bits { 11548 struct mlx5_ifc_bufferx_reg_bits bufferx_reg; 11549 struct mlx5_ifc_eth_2819_cntrs_grp_data_layout_bits eth_2819_cntrs_grp_data_layout; 11550 struct mlx5_ifc_eth_2863_cntrs_grp_data_layout_bits eth_2863_cntrs_grp_data_layout; 11551 struct mlx5_ifc_eth_3635_cntrs_grp_data_layout_bits eth_3635_cntrs_grp_data_layout; 11552 struct mlx5_ifc_eth_802_3_cntrs_grp_data_layout_bits eth_802_3_cntrs_grp_data_layout; 11553 struct mlx5_ifc_eth_extended_cntrs_grp_data_layout_bits eth_extended_cntrs_grp_data_layout; 11554 struct mlx5_ifc_eth_per_prio_grp_data_layout_bits eth_per_prio_grp_data_layout; 11555 struct mlx5_ifc_eth_per_tc_prio_grp_data_layout_bits eth_per_tc_prio_grp_data_layout; 11556 struct mlx5_ifc_eth_per_tc_congest_prio_grp_data_layout_bits eth_per_tc_congest_prio_grp_data_layout; 11557 struct mlx5_ifc_lane_2_module_mapping_bits lane_2_module_mapping; 11558 struct mlx5_ifc_pamp_reg_bits pamp_reg; 11559 struct mlx5_ifc_paos_reg_bits paos_reg; 11560 struct mlx5_ifc_pcap_reg_bits pcap_reg; 11561 struct mlx5_ifc_pddr_monitor_opcode_bits pddr_monitor_opcode; 11562 struct mlx5_ifc_pddr_reg_bits pddr_reg; 11563 struct mlx5_ifc_pddr_troubleshooting_page_bits pddr_troubleshooting_page; 11564 struct mlx5_ifc_peir_reg_bits peir_reg; 11565 struct mlx5_ifc_pelc_reg_bits pelc_reg; 11566 struct mlx5_ifc_pfcc_reg_bits pfcc_reg; 11567 struct mlx5_ifc_ib_port_cntrs_grp_data_layout_bits ib_port_cntrs_grp_data_layout; 11568 struct mlx5_ifc_phys_layer_cntrs_bits phys_layer_cntrs; 11569 struct mlx5_ifc_pifr_reg_bits pifr_reg; 11570 struct mlx5_ifc_pipg_reg_bits pipg_reg; 11571 struct mlx5_ifc_plbf_reg_bits plbf_reg; 11572 struct mlx5_ifc_plib_reg_bits plib_reg; 11573 struct mlx5_ifc_plpc_reg_bits plpc_reg; 11574 struct mlx5_ifc_pmaos_reg_bits pmaos_reg; 11575 struct mlx5_ifc_pmlp_reg_bits pmlp_reg; 11576 struct mlx5_ifc_pmlpn_reg_bits pmlpn_reg; 11577 struct mlx5_ifc_pmpc_reg_bits pmpc_reg; 11578 struct mlx5_ifc_pmpe_reg_bits pmpe_reg; 11579 struct mlx5_ifc_pmpr_reg_bits pmpr_reg; 11580 struct mlx5_ifc_pmtu_reg_bits pmtu_reg; 11581 struct mlx5_ifc_ppad_reg_bits ppad_reg; 11582 struct mlx5_ifc_ppcnt_reg_bits ppcnt_reg; 11583 struct mlx5_ifc_mpein_reg_bits mpein_reg; 11584 struct mlx5_ifc_mpcnt_reg_bits mpcnt_reg; 11585 struct mlx5_ifc_pplm_reg_bits pplm_reg; 11586 struct mlx5_ifc_pplr_reg_bits pplr_reg; 11587 struct mlx5_ifc_ppsc_reg_bits ppsc_reg; 11588 struct mlx5_ifc_pqdr_reg_bits pqdr_reg; 11589 struct mlx5_ifc_pspa_reg_bits pspa_reg; 11590 struct mlx5_ifc_ptas_reg_bits ptas_reg; 11591 struct mlx5_ifc_ptys_reg_bits ptys_reg; 11592 struct mlx5_ifc_mlcr_reg_bits mlcr_reg; 11593 struct mlx5_ifc_pude_reg_bits pude_reg; 11594 struct mlx5_ifc_pvlc_reg_bits pvlc_reg; 11595 struct mlx5_ifc_slrg_reg_bits slrg_reg; 11596 struct mlx5_ifc_sltp_reg_bits sltp_reg; 11597 struct mlx5_ifc_mtpps_reg_bits mtpps_reg; 11598 struct mlx5_ifc_mtppse_reg_bits mtppse_reg; 11599 struct mlx5_ifc_fpga_access_reg_bits fpga_access_reg; 11600 struct mlx5_ifc_fpga_ctrl_bits fpga_ctrl_bits; 11601 struct mlx5_ifc_fpga_cap_bits fpga_cap_bits; 11602 struct mlx5_ifc_mcqi_reg_bits mcqi_reg; 11603 struct mlx5_ifc_mcc_reg_bits mcc_reg; 11604 struct mlx5_ifc_mcda_reg_bits mcda_reg; 11605 struct mlx5_ifc_mirc_reg_bits mirc_reg; 11606 struct mlx5_ifc_mfrl_reg_bits mfrl_reg; 11607 struct mlx5_ifc_mtutc_reg_bits mtutc_reg; 11608 struct mlx5_ifc_mrtc_reg_bits mrtc_reg; 11609 struct mlx5_ifc_mtcap_reg_bits mtcap_reg; 11610 struct mlx5_ifc_mtmp_reg_bits mtmp_reg; 11611 struct mlx5_ifc_mtptm_reg_bits mtptm_reg; 11612 struct mlx5_ifc_mtctr_reg_bits mtctr_reg; 11613 u8 reserved_at_0[0x60e0]; 11614 }; 11615 11616 union mlx5_ifc_debug_enhancements_document_bits { 11617 struct mlx5_ifc_health_buffer_bits health_buffer; 11618 u8 reserved_at_0[0x200]; 11619 }; 11620 11621 union mlx5_ifc_uplink_pci_interface_document_bits { 11622 struct mlx5_ifc_initial_seg_bits initial_seg; 11623 u8 reserved_at_0[0x20060]; 11624 }; 11625 11626 struct mlx5_ifc_set_flow_table_root_out_bits { 11627 u8 status[0x8]; 11628 u8 reserved_at_8[0x18]; 11629 11630 u8 syndrome[0x20]; 11631 11632 u8 reserved_at_40[0x40]; 11633 }; 11634 11635 struct mlx5_ifc_set_flow_table_root_in_bits { 11636 u8 opcode[0x10]; 11637 u8 reserved_at_10[0x10]; 11638 11639 u8 reserved_at_20[0x10]; 11640 u8 op_mod[0x10]; 11641 11642 u8 other_vport[0x1]; 11643 u8 reserved_at_41[0xf]; 11644 u8 vport_number[0x10]; 11645 11646 u8 reserved_at_60[0x20]; 11647 11648 u8 table_type[0x8]; 11649 u8 reserved_at_88[0x7]; 11650 u8 table_of_other_vport[0x1]; 11651 u8 table_vport_number[0x10]; 11652 11653 u8 reserved_at_a0[0x8]; 11654 u8 table_id[0x18]; 11655 11656 u8 reserved_at_c0[0x8]; 11657 u8 underlay_qpn[0x18]; 11658 u8 table_eswitch_owner_vhca_id_valid[0x1]; 11659 u8 reserved_at_e1[0xf]; 11660 u8 table_eswitch_owner_vhca_id[0x10]; 11661 u8 reserved_at_100[0x100]; 11662 }; 11663 11664 enum { 11665 MLX5_MODIFY_FLOW_TABLE_MISS_TABLE_ID = (1UL << 0), 11666 MLX5_MODIFY_FLOW_TABLE_LAG_NEXT_TABLE_ID = (1UL << 15), 11667 }; 11668 11669 struct mlx5_ifc_modify_flow_table_out_bits { 11670 u8 status[0x8]; 11671 u8 reserved_at_8[0x18]; 11672 11673 u8 syndrome[0x20]; 11674 11675 u8 reserved_at_40[0x40]; 11676 }; 11677 11678 struct mlx5_ifc_modify_flow_table_in_bits { 11679 u8 opcode[0x10]; 11680 u8 reserved_at_10[0x10]; 11681 11682 u8 reserved_at_20[0x10]; 11683 u8 op_mod[0x10]; 11684 11685 u8 other_vport[0x1]; 11686 u8 reserved_at_41[0xf]; 11687 u8 vport_number[0x10]; 11688 11689 u8 reserved_at_60[0x10]; 11690 u8 modify_field_select[0x10]; 11691 11692 u8 table_type[0x8]; 11693 u8 reserved_at_88[0x18]; 11694 11695 u8 reserved_at_a0[0x8]; 11696 u8 table_id[0x18]; 11697 11698 struct mlx5_ifc_flow_table_context_bits flow_table_context; 11699 }; 11700 11701 struct mlx5_ifc_ets_tcn_config_reg_bits { 11702 u8 g[0x1]; 11703 u8 b[0x1]; 11704 u8 r[0x1]; 11705 u8 reserved_at_3[0x9]; 11706 u8 group[0x4]; 11707 u8 reserved_at_10[0x9]; 11708 u8 bw_allocation[0x7]; 11709 11710 u8 reserved_at_20[0xc]; 11711 u8 max_bw_units[0x4]; 11712 u8 reserved_at_30[0x8]; 11713 u8 max_bw_value[0x8]; 11714 }; 11715 11716 struct mlx5_ifc_ets_global_config_reg_bits { 11717 u8 reserved_at_0[0x2]; 11718 u8 r[0x1]; 11719 u8 reserved_at_3[0x1d]; 11720 11721 u8 reserved_at_20[0xc]; 11722 u8 max_bw_units[0x4]; 11723 u8 reserved_at_30[0x8]; 11724 u8 max_bw_value[0x8]; 11725 }; 11726 11727 struct mlx5_ifc_qetc_reg_bits { 11728 u8 reserved_at_0[0x8]; 11729 u8 port_number[0x8]; 11730 u8 reserved_at_10[0x30]; 11731 11732 struct mlx5_ifc_ets_tcn_config_reg_bits tc_configuration[0x8]; 11733 struct mlx5_ifc_ets_global_config_reg_bits global_configuration; 11734 }; 11735 11736 struct mlx5_ifc_qpdpm_dscp_reg_bits { 11737 u8 e[0x1]; 11738 u8 reserved_at_01[0x0b]; 11739 u8 prio[0x04]; 11740 }; 11741 11742 struct mlx5_ifc_qpdpm_reg_bits { 11743 u8 reserved_at_0[0x8]; 11744 u8 local_port[0x8]; 11745 u8 reserved_at_10[0x10]; 11746 struct mlx5_ifc_qpdpm_dscp_reg_bits dscp[64]; 11747 }; 11748 11749 struct mlx5_ifc_qpts_reg_bits { 11750 u8 reserved_at_0[0x8]; 11751 u8 local_port[0x8]; 11752 u8 reserved_at_10[0x2d]; 11753 u8 trust_state[0x3]; 11754 }; 11755 11756 struct mlx5_ifc_pptb_reg_bits { 11757 u8 reserved_at_0[0x2]; 11758 u8 mm[0x2]; 11759 u8 reserved_at_4[0x4]; 11760 u8 local_port[0x8]; 11761 u8 reserved_at_10[0x6]; 11762 u8 cm[0x1]; 11763 u8 um[0x1]; 11764 u8 pm[0x8]; 11765 11766 u8 prio_x_buff[0x20]; 11767 11768 u8 pm_msb[0x8]; 11769 u8 reserved_at_48[0x10]; 11770 u8 ctrl_buff[0x4]; 11771 u8 untagged_buff[0x4]; 11772 }; 11773 11774 struct mlx5_ifc_sbcam_reg_bits { 11775 u8 reserved_at_0[0x8]; 11776 u8 feature_group[0x8]; 11777 u8 reserved_at_10[0x8]; 11778 u8 access_reg_group[0x8]; 11779 11780 u8 reserved_at_20[0x20]; 11781 11782 u8 sb_access_reg_cap_mask[4][0x20]; 11783 11784 u8 reserved_at_c0[0x80]; 11785 11786 u8 sb_feature_cap_mask[4][0x20]; 11787 11788 u8 reserved_at_1c0[0x40]; 11789 11790 u8 cap_total_buffer_size[0x20]; 11791 11792 u8 cap_cell_size[0x10]; 11793 u8 cap_max_pg_buffers[0x8]; 11794 u8 cap_num_pool_supported[0x8]; 11795 11796 u8 reserved_at_240[0x8]; 11797 u8 cap_sbsr_stat_size[0x8]; 11798 u8 cap_max_tclass_data[0x8]; 11799 u8 cap_max_cpu_ingress_tclass_sb[0x8]; 11800 }; 11801 11802 struct mlx5_ifc_pbmc_reg_bits { 11803 u8 reserved_at_0[0x8]; 11804 u8 local_port[0x8]; 11805 u8 reserved_at_10[0x10]; 11806 11807 u8 xoff_timer_value[0x10]; 11808 u8 xoff_refresh[0x10]; 11809 11810 u8 reserved_at_40[0x9]; 11811 u8 fullness_threshold[0x7]; 11812 u8 port_buffer_size[0x10]; 11813 11814 struct mlx5_ifc_bufferx_reg_bits buffer[10]; 11815 11816 u8 reserved_at_2e0[0x80]; 11817 }; 11818 11819 struct mlx5_ifc_sbpr_reg_bits { 11820 u8 desc[0x1]; 11821 u8 snap[0x1]; 11822 u8 reserved_at_2[0x4]; 11823 u8 dir[0x2]; 11824 u8 reserved_at_8[0x14]; 11825 u8 pool[0x4]; 11826 11827 u8 infi_size[0x1]; 11828 u8 reserved_at_21[0x7]; 11829 u8 size[0x18]; 11830 11831 u8 reserved_at_40[0x1c]; 11832 u8 mode[0x4]; 11833 11834 u8 reserved_at_60[0x8]; 11835 u8 buff_occupancy[0x18]; 11836 11837 u8 clr[0x1]; 11838 u8 reserved_at_81[0x7]; 11839 u8 max_buff_occupancy[0x18]; 11840 11841 u8 reserved_at_a0[0x8]; 11842 u8 ext_buff_occupancy[0x18]; 11843 }; 11844 11845 struct mlx5_ifc_sbcm_reg_bits { 11846 u8 desc[0x1]; 11847 u8 snap[0x1]; 11848 u8 reserved_at_2[0x6]; 11849 u8 local_port[0x8]; 11850 u8 pnat[0x2]; 11851 u8 pg_buff[0x6]; 11852 u8 reserved_at_18[0x6]; 11853 u8 dir[0x2]; 11854 11855 u8 reserved_at_20[0x1f]; 11856 u8 exc[0x1]; 11857 11858 u8 reserved_at_40[0x40]; 11859 11860 u8 reserved_at_80[0x8]; 11861 u8 buff_occupancy[0x18]; 11862 11863 u8 clr[0x1]; 11864 u8 reserved_at_a1[0x7]; 11865 u8 max_buff_occupancy[0x18]; 11866 11867 u8 reserved_at_c0[0x8]; 11868 u8 min_buff[0x18]; 11869 11870 u8 infi_max[0x1]; 11871 u8 reserved_at_e1[0x7]; 11872 u8 max_buff[0x18]; 11873 11874 u8 reserved_at_100[0x20]; 11875 11876 u8 reserved_at_120[0x1c]; 11877 u8 pool[0x4]; 11878 }; 11879 11880 struct mlx5_ifc_qtct_reg_bits { 11881 u8 reserved_at_0[0x8]; 11882 u8 port_number[0x8]; 11883 u8 reserved_at_10[0xd]; 11884 u8 prio[0x3]; 11885 11886 u8 reserved_at_20[0x1d]; 11887 u8 tclass[0x3]; 11888 }; 11889 11890 struct mlx5_ifc_mcia_reg_bits { 11891 u8 l[0x1]; 11892 u8 reserved_at_1[0x7]; 11893 u8 module[0x8]; 11894 u8 reserved_at_10[0x8]; 11895 u8 status[0x8]; 11896 11897 u8 i2c_device_address[0x8]; 11898 u8 page_number[0x8]; 11899 u8 device_address[0x10]; 11900 11901 u8 reserved_at_40[0x10]; 11902 u8 size[0x10]; 11903 11904 u8 reserved_at_60[0x20]; 11905 11906 u8 dword_0[0x20]; 11907 u8 dword_1[0x20]; 11908 u8 dword_2[0x20]; 11909 u8 dword_3[0x20]; 11910 u8 dword_4[0x20]; 11911 u8 dword_5[0x20]; 11912 u8 dword_6[0x20]; 11913 u8 dword_7[0x20]; 11914 u8 dword_8[0x20]; 11915 u8 dword_9[0x20]; 11916 u8 dword_10[0x20]; 11917 u8 dword_11[0x20]; 11918 }; 11919 11920 struct mlx5_ifc_dcbx_param_bits { 11921 u8 dcbx_cee_cap[0x1]; 11922 u8 dcbx_ieee_cap[0x1]; 11923 u8 dcbx_standby_cap[0x1]; 11924 u8 reserved_at_3[0x5]; 11925 u8 port_number[0x8]; 11926 u8 reserved_at_10[0xa]; 11927 u8 max_application_table_size[6]; 11928 u8 reserved_at_20[0x15]; 11929 u8 version_oper[0x3]; 11930 u8 reserved_at_38[5]; 11931 u8 version_admin[0x3]; 11932 u8 willing_admin[0x1]; 11933 u8 reserved_at_41[0x3]; 11934 u8 pfc_cap_oper[0x4]; 11935 u8 reserved_at_48[0x4]; 11936 u8 pfc_cap_admin[0x4]; 11937 u8 reserved_at_50[0x4]; 11938 u8 num_of_tc_oper[0x4]; 11939 u8 reserved_at_58[0x4]; 11940 u8 num_of_tc_admin[0x4]; 11941 u8 remote_willing[0x1]; 11942 u8 reserved_at_61[3]; 11943 u8 remote_pfc_cap[4]; 11944 u8 reserved_at_68[0x14]; 11945 u8 remote_num_of_tc[0x4]; 11946 u8 reserved_at_80[0x18]; 11947 u8 error[0x8]; 11948 u8 reserved_at_a0[0x160]; 11949 }; 11950 11951 enum { 11952 MLX5_LAG_PORT_SELECT_MODE_QUEUE_AFFINITY = 0, 11953 MLX5_LAG_PORT_SELECT_MODE_PORT_SELECT_FT = 1, 11954 MLX5_LAG_PORT_SELECT_MODE_PORT_SELECT_MPESW = 2, 11955 }; 11956 11957 struct mlx5_ifc_lagc_bits { 11958 u8 fdb_selection_mode[0x1]; 11959 u8 reserved_at_1[0x14]; 11960 u8 port_select_mode[0x3]; 11961 u8 reserved_at_18[0x5]; 11962 u8 lag_state[0x3]; 11963 11964 u8 reserved_at_20[0xc]; 11965 u8 active_port[0x4]; 11966 u8 reserved_at_30[0x4]; 11967 u8 tx_remap_affinity_2[0x4]; 11968 u8 reserved_at_38[0x4]; 11969 u8 tx_remap_affinity_1[0x4]; 11970 }; 11971 11972 struct mlx5_ifc_create_lag_out_bits { 11973 u8 status[0x8]; 11974 u8 reserved_at_8[0x18]; 11975 11976 u8 syndrome[0x20]; 11977 11978 u8 reserved_at_40[0x40]; 11979 }; 11980 11981 struct mlx5_ifc_create_lag_in_bits { 11982 u8 opcode[0x10]; 11983 u8 reserved_at_10[0x10]; 11984 11985 u8 reserved_at_20[0x10]; 11986 u8 op_mod[0x10]; 11987 11988 struct mlx5_ifc_lagc_bits ctx; 11989 }; 11990 11991 struct mlx5_ifc_modify_lag_out_bits { 11992 u8 status[0x8]; 11993 u8 reserved_at_8[0x18]; 11994 11995 u8 syndrome[0x20]; 11996 11997 u8 reserved_at_40[0x40]; 11998 }; 11999 12000 struct mlx5_ifc_modify_lag_in_bits { 12001 u8 opcode[0x10]; 12002 u8 reserved_at_10[0x10]; 12003 12004 u8 reserved_at_20[0x10]; 12005 u8 op_mod[0x10]; 12006 12007 u8 reserved_at_40[0x20]; 12008 u8 field_select[0x20]; 12009 12010 struct mlx5_ifc_lagc_bits ctx; 12011 }; 12012 12013 struct mlx5_ifc_query_lag_out_bits { 12014 u8 status[0x8]; 12015 u8 reserved_at_8[0x18]; 12016 12017 u8 syndrome[0x20]; 12018 12019 struct mlx5_ifc_lagc_bits ctx; 12020 }; 12021 12022 struct mlx5_ifc_query_lag_in_bits { 12023 u8 opcode[0x10]; 12024 u8 reserved_at_10[0x10]; 12025 12026 u8 reserved_at_20[0x10]; 12027 u8 op_mod[0x10]; 12028 12029 u8 reserved_at_40[0x40]; 12030 }; 12031 12032 struct mlx5_ifc_destroy_lag_out_bits { 12033 u8 status[0x8]; 12034 u8 reserved_at_8[0x18]; 12035 12036 u8 syndrome[0x20]; 12037 12038 u8 reserved_at_40[0x40]; 12039 }; 12040 12041 struct mlx5_ifc_destroy_lag_in_bits { 12042 u8 opcode[0x10]; 12043 u8 reserved_at_10[0x10]; 12044 12045 u8 reserved_at_20[0x10]; 12046 u8 op_mod[0x10]; 12047 12048 u8 reserved_at_40[0x40]; 12049 }; 12050 12051 struct mlx5_ifc_create_vport_lag_out_bits { 12052 u8 status[0x8]; 12053 u8 reserved_at_8[0x18]; 12054 12055 u8 syndrome[0x20]; 12056 12057 u8 reserved_at_40[0x40]; 12058 }; 12059 12060 struct mlx5_ifc_create_vport_lag_in_bits { 12061 u8 opcode[0x10]; 12062 u8 reserved_at_10[0x10]; 12063 12064 u8 reserved_at_20[0x10]; 12065 u8 op_mod[0x10]; 12066 12067 u8 reserved_at_40[0x40]; 12068 }; 12069 12070 struct mlx5_ifc_destroy_vport_lag_out_bits { 12071 u8 status[0x8]; 12072 u8 reserved_at_8[0x18]; 12073 12074 u8 syndrome[0x20]; 12075 12076 u8 reserved_at_40[0x40]; 12077 }; 12078 12079 struct mlx5_ifc_destroy_vport_lag_in_bits { 12080 u8 opcode[0x10]; 12081 u8 reserved_at_10[0x10]; 12082 12083 u8 reserved_at_20[0x10]; 12084 u8 op_mod[0x10]; 12085 12086 u8 reserved_at_40[0x40]; 12087 }; 12088 12089 enum { 12090 MLX5_MODIFY_MEMIC_OP_MOD_ALLOC, 12091 MLX5_MODIFY_MEMIC_OP_MOD_DEALLOC, 12092 }; 12093 12094 struct mlx5_ifc_modify_memic_in_bits { 12095 u8 opcode[0x10]; 12096 u8 uid[0x10]; 12097 12098 u8 reserved_at_20[0x10]; 12099 u8 op_mod[0x10]; 12100 12101 u8 reserved_at_40[0x20]; 12102 12103 u8 reserved_at_60[0x18]; 12104 u8 memic_operation_type[0x8]; 12105 12106 u8 memic_start_addr[0x40]; 12107 12108 u8 reserved_at_c0[0x140]; 12109 }; 12110 12111 struct mlx5_ifc_modify_memic_out_bits { 12112 u8 status[0x8]; 12113 u8 reserved_at_8[0x18]; 12114 12115 u8 syndrome[0x20]; 12116 12117 u8 reserved_at_40[0x40]; 12118 12119 u8 memic_operation_addr[0x40]; 12120 12121 u8 reserved_at_c0[0x140]; 12122 }; 12123 12124 struct mlx5_ifc_alloc_memic_in_bits { 12125 u8 opcode[0x10]; 12126 u8 reserved_at_10[0x10]; 12127 12128 u8 reserved_at_20[0x10]; 12129 u8 op_mod[0x10]; 12130 12131 u8 reserved_at_30[0x20]; 12132 12133 u8 reserved_at_40[0x18]; 12134 u8 log_memic_addr_alignment[0x8]; 12135 12136 u8 range_start_addr[0x40]; 12137 12138 u8 range_size[0x20]; 12139 12140 u8 memic_size[0x20]; 12141 }; 12142 12143 struct mlx5_ifc_alloc_memic_out_bits { 12144 u8 status[0x8]; 12145 u8 reserved_at_8[0x18]; 12146 12147 u8 syndrome[0x20]; 12148 12149 u8 memic_start_addr[0x40]; 12150 }; 12151 12152 struct mlx5_ifc_dealloc_memic_in_bits { 12153 u8 opcode[0x10]; 12154 u8 reserved_at_10[0x10]; 12155 12156 u8 reserved_at_20[0x10]; 12157 u8 op_mod[0x10]; 12158 12159 u8 reserved_at_40[0x40]; 12160 12161 u8 memic_start_addr[0x40]; 12162 12163 u8 memic_size[0x20]; 12164 12165 u8 reserved_at_e0[0x20]; 12166 }; 12167 12168 struct mlx5_ifc_dealloc_memic_out_bits { 12169 u8 status[0x8]; 12170 u8 reserved_at_8[0x18]; 12171 12172 u8 syndrome[0x20]; 12173 12174 u8 reserved_at_40[0x40]; 12175 }; 12176 12177 struct mlx5_ifc_umem_bits { 12178 u8 reserved_at_0[0x80]; 12179 12180 u8 ats[0x1]; 12181 u8 reserved_at_81[0x1a]; 12182 u8 log_page_size[0x5]; 12183 12184 u8 page_offset[0x20]; 12185 12186 u8 num_of_mtt[0x40]; 12187 12188 struct mlx5_ifc_mtt_bits mtt[]; 12189 }; 12190 12191 struct mlx5_ifc_uctx_bits { 12192 u8 cap[0x20]; 12193 12194 u8 reserved_at_20[0x160]; 12195 }; 12196 12197 struct mlx5_ifc_sw_icm_bits { 12198 u8 modify_field_select[0x40]; 12199 12200 u8 reserved_at_40[0x18]; 12201 u8 log_sw_icm_size[0x8]; 12202 12203 u8 reserved_at_60[0x20]; 12204 12205 u8 sw_icm_start_addr[0x40]; 12206 12207 u8 reserved_at_c0[0x140]; 12208 }; 12209 12210 struct mlx5_ifc_geneve_tlv_option_bits { 12211 u8 modify_field_select[0x40]; 12212 12213 u8 reserved_at_40[0x18]; 12214 u8 geneve_option_fte_index[0x8]; 12215 12216 u8 option_class[0x10]; 12217 u8 option_type[0x8]; 12218 u8 reserved_at_78[0x3]; 12219 u8 option_data_length[0x5]; 12220 12221 u8 reserved_at_80[0x180]; 12222 }; 12223 12224 struct mlx5_ifc_create_umem_in_bits { 12225 u8 opcode[0x10]; 12226 u8 uid[0x10]; 12227 12228 u8 reserved_at_20[0x10]; 12229 u8 op_mod[0x10]; 12230 12231 u8 reserved_at_40[0x40]; 12232 12233 struct mlx5_ifc_umem_bits umem; 12234 }; 12235 12236 struct mlx5_ifc_create_umem_out_bits { 12237 u8 status[0x8]; 12238 u8 reserved_at_8[0x18]; 12239 12240 u8 syndrome[0x20]; 12241 12242 u8 reserved_at_40[0x8]; 12243 u8 umem_id[0x18]; 12244 12245 u8 reserved_at_60[0x20]; 12246 }; 12247 12248 struct mlx5_ifc_destroy_umem_in_bits { 12249 u8 opcode[0x10]; 12250 u8 uid[0x10]; 12251 12252 u8 reserved_at_20[0x10]; 12253 u8 op_mod[0x10]; 12254 12255 u8 reserved_at_40[0x8]; 12256 u8 umem_id[0x18]; 12257 12258 u8 reserved_at_60[0x20]; 12259 }; 12260 12261 struct mlx5_ifc_destroy_umem_out_bits { 12262 u8 status[0x8]; 12263 u8 reserved_at_8[0x18]; 12264 12265 u8 syndrome[0x20]; 12266 12267 u8 reserved_at_40[0x40]; 12268 }; 12269 12270 struct mlx5_ifc_create_uctx_in_bits { 12271 u8 opcode[0x10]; 12272 u8 reserved_at_10[0x10]; 12273 12274 u8 reserved_at_20[0x10]; 12275 u8 op_mod[0x10]; 12276 12277 u8 reserved_at_40[0x40]; 12278 12279 struct mlx5_ifc_uctx_bits uctx; 12280 }; 12281 12282 struct mlx5_ifc_create_uctx_out_bits { 12283 u8 status[0x8]; 12284 u8 reserved_at_8[0x18]; 12285 12286 u8 syndrome[0x20]; 12287 12288 u8 reserved_at_40[0x10]; 12289 u8 uid[0x10]; 12290 12291 u8 reserved_at_60[0x20]; 12292 }; 12293 12294 struct mlx5_ifc_destroy_uctx_in_bits { 12295 u8 opcode[0x10]; 12296 u8 reserved_at_10[0x10]; 12297 12298 u8 reserved_at_20[0x10]; 12299 u8 op_mod[0x10]; 12300 12301 u8 reserved_at_40[0x10]; 12302 u8 uid[0x10]; 12303 12304 u8 reserved_at_60[0x20]; 12305 }; 12306 12307 struct mlx5_ifc_destroy_uctx_out_bits { 12308 u8 status[0x8]; 12309 u8 reserved_at_8[0x18]; 12310 12311 u8 syndrome[0x20]; 12312 12313 u8 reserved_at_40[0x40]; 12314 }; 12315 12316 struct mlx5_ifc_create_sw_icm_in_bits { 12317 struct mlx5_ifc_general_obj_in_cmd_hdr_bits hdr; 12318 struct mlx5_ifc_sw_icm_bits sw_icm; 12319 }; 12320 12321 struct mlx5_ifc_create_geneve_tlv_option_in_bits { 12322 struct mlx5_ifc_general_obj_in_cmd_hdr_bits hdr; 12323 struct mlx5_ifc_geneve_tlv_option_bits geneve_tlv_opt; 12324 }; 12325 12326 struct mlx5_ifc_mtrc_string_db_param_bits { 12327 u8 string_db_base_address[0x20]; 12328 12329 u8 reserved_at_20[0x8]; 12330 u8 string_db_size[0x18]; 12331 }; 12332 12333 struct mlx5_ifc_mtrc_cap_bits { 12334 u8 trace_owner[0x1]; 12335 u8 trace_to_memory[0x1]; 12336 u8 reserved_at_2[0x4]; 12337 u8 trc_ver[0x2]; 12338 u8 reserved_at_8[0x14]; 12339 u8 num_string_db[0x4]; 12340 12341 u8 first_string_trace[0x8]; 12342 u8 num_string_trace[0x8]; 12343 u8 reserved_at_30[0x28]; 12344 12345 u8 log_max_trace_buffer_size[0x8]; 12346 12347 u8 reserved_at_60[0x20]; 12348 12349 struct mlx5_ifc_mtrc_string_db_param_bits string_db_param[8]; 12350 12351 u8 reserved_at_280[0x180]; 12352 }; 12353 12354 struct mlx5_ifc_mtrc_conf_bits { 12355 u8 reserved_at_0[0x1c]; 12356 u8 trace_mode[0x4]; 12357 u8 reserved_at_20[0x18]; 12358 u8 log_trace_buffer_size[0x8]; 12359 u8 trace_mkey[0x20]; 12360 u8 reserved_at_60[0x3a0]; 12361 }; 12362 12363 struct mlx5_ifc_mtrc_stdb_bits { 12364 u8 string_db_index[0x4]; 12365 u8 reserved_at_4[0x4]; 12366 u8 read_size[0x18]; 12367 u8 start_offset[0x20]; 12368 u8 string_db_data[]; 12369 }; 12370 12371 struct mlx5_ifc_mtrc_ctrl_bits { 12372 u8 trace_status[0x2]; 12373 u8 reserved_at_2[0x2]; 12374 u8 arm_event[0x1]; 12375 u8 reserved_at_5[0xb]; 12376 u8 modify_field_select[0x10]; 12377 u8 reserved_at_20[0x2b]; 12378 u8 current_timestamp52_32[0x15]; 12379 u8 current_timestamp31_0[0x20]; 12380 u8 reserved_at_80[0x180]; 12381 }; 12382 12383 struct mlx5_ifc_host_params_context_bits { 12384 u8 host_number[0x8]; 12385 u8 reserved_at_8[0x7]; 12386 u8 host_pf_disabled[0x1]; 12387 u8 host_num_of_vfs[0x10]; 12388 12389 u8 host_total_vfs[0x10]; 12390 u8 host_pci_bus[0x10]; 12391 12392 u8 reserved_at_40[0x10]; 12393 u8 host_pci_device[0x10]; 12394 12395 u8 reserved_at_60[0x10]; 12396 u8 host_pci_function[0x10]; 12397 12398 u8 reserved_at_80[0x180]; 12399 }; 12400 12401 struct mlx5_ifc_query_esw_functions_in_bits { 12402 u8 opcode[0x10]; 12403 u8 reserved_at_10[0x10]; 12404 12405 u8 reserved_at_20[0x10]; 12406 u8 op_mod[0x10]; 12407 12408 u8 reserved_at_40[0x40]; 12409 }; 12410 12411 struct mlx5_ifc_query_esw_functions_out_bits { 12412 u8 status[0x8]; 12413 u8 reserved_at_8[0x18]; 12414 12415 u8 syndrome[0x20]; 12416 12417 u8 reserved_at_40[0x40]; 12418 12419 struct mlx5_ifc_host_params_context_bits host_params_context; 12420 12421 u8 reserved_at_280[0x180]; 12422 u8 host_sf_enable[][0x40]; 12423 }; 12424 12425 struct mlx5_ifc_sf_partition_bits { 12426 u8 reserved_at_0[0x10]; 12427 u8 log_num_sf[0x8]; 12428 u8 log_sf_bar_size[0x8]; 12429 }; 12430 12431 struct mlx5_ifc_query_sf_partitions_out_bits { 12432 u8 status[0x8]; 12433 u8 reserved_at_8[0x18]; 12434 12435 u8 syndrome[0x20]; 12436 12437 u8 reserved_at_40[0x18]; 12438 u8 num_sf_partitions[0x8]; 12439 12440 u8 reserved_at_60[0x20]; 12441 12442 struct mlx5_ifc_sf_partition_bits sf_partition[]; 12443 }; 12444 12445 struct mlx5_ifc_query_sf_partitions_in_bits { 12446 u8 opcode[0x10]; 12447 u8 reserved_at_10[0x10]; 12448 12449 u8 reserved_at_20[0x10]; 12450 u8 op_mod[0x10]; 12451 12452 u8 reserved_at_40[0x40]; 12453 }; 12454 12455 struct mlx5_ifc_dealloc_sf_out_bits { 12456 u8 status[0x8]; 12457 u8 reserved_at_8[0x18]; 12458 12459 u8 syndrome[0x20]; 12460 12461 u8 reserved_at_40[0x40]; 12462 }; 12463 12464 struct mlx5_ifc_dealloc_sf_in_bits { 12465 u8 opcode[0x10]; 12466 u8 reserved_at_10[0x10]; 12467 12468 u8 reserved_at_20[0x10]; 12469 u8 op_mod[0x10]; 12470 12471 u8 reserved_at_40[0x10]; 12472 u8 function_id[0x10]; 12473 12474 u8 reserved_at_60[0x20]; 12475 }; 12476 12477 struct mlx5_ifc_alloc_sf_out_bits { 12478 u8 status[0x8]; 12479 u8 reserved_at_8[0x18]; 12480 12481 u8 syndrome[0x20]; 12482 12483 u8 reserved_at_40[0x40]; 12484 }; 12485 12486 struct mlx5_ifc_alloc_sf_in_bits { 12487 u8 opcode[0x10]; 12488 u8 reserved_at_10[0x10]; 12489 12490 u8 reserved_at_20[0x10]; 12491 u8 op_mod[0x10]; 12492 12493 u8 reserved_at_40[0x10]; 12494 u8 function_id[0x10]; 12495 12496 u8 reserved_at_60[0x20]; 12497 }; 12498 12499 struct mlx5_ifc_affiliated_event_header_bits { 12500 u8 reserved_at_0[0x10]; 12501 u8 obj_type[0x10]; 12502 12503 u8 obj_id[0x20]; 12504 }; 12505 12506 enum { 12507 MLX5_GENERAL_OBJECT_TYPES_ENCRYPTION_KEY = 0xc, 12508 MLX5_GENERAL_OBJECT_TYPES_IPSEC = 0x13, 12509 MLX5_GENERAL_OBJECT_TYPES_SAMPLER = 0x20, 12510 MLX5_GENERAL_OBJECT_TYPES_FLOW_METER_ASO = 0x24, 12511 MLX5_GENERAL_OBJECT_TYPES_MACSEC = 0x27, 12512 MLX5_GENERAL_OBJECT_TYPES_INT_KEK = 0x47, 12513 MLX5_GENERAL_OBJECT_TYPES_RDMA_CTRL = 0x53, 12514 MLX5_GENERAL_OBJECT_TYPES_PCIE_CONG_EVENT = 0x58, 12515 MLX5_GENERAL_OBJECT_TYPES_FLOW_TABLE_ALIAS = 0xff15, 12516 }; 12517 12518 enum { 12519 MLX5_HCA_CAP_GENERAL_OBJECT_TYPES_ENCRYPTION_KEY = 12520 BIT_ULL(MLX5_GENERAL_OBJECT_TYPES_ENCRYPTION_KEY), 12521 MLX5_HCA_CAP_GENERAL_OBJECT_TYPES_IPSEC = 12522 BIT_ULL(MLX5_GENERAL_OBJECT_TYPES_IPSEC), 12523 MLX5_HCA_CAP_GENERAL_OBJECT_TYPES_SAMPLER = 12524 BIT_ULL(MLX5_GENERAL_OBJECT_TYPES_SAMPLER), 12525 MLX5_HCA_CAP_GENERAL_OBJECT_TYPES_FLOW_METER_ASO = 12526 BIT_ULL(MLX5_GENERAL_OBJECT_TYPES_FLOW_METER_ASO), 12527 }; 12528 12529 enum { 12530 MLX5_HCA_CAP_2_GENERAL_OBJECT_TYPES_RDMA_CTRL = 12531 BIT_ULL(MLX5_GENERAL_OBJECT_TYPES_RDMA_CTRL - 0x40), 12532 MLX5_HCA_CAP_2_GENERAL_OBJECT_TYPES_PCIE_CONG_EVENT = 12533 BIT_ULL(MLX5_GENERAL_OBJECT_TYPES_PCIE_CONG_EVENT - 0x40), 12534 }; 12535 12536 enum { 12537 MLX5_IPSEC_OBJECT_ICV_LEN_16B, 12538 }; 12539 12540 enum { 12541 MLX5_IPSEC_ASO_REG_C_0_1 = 0x0, 12542 MLX5_IPSEC_ASO_REG_C_2_3 = 0x1, 12543 MLX5_IPSEC_ASO_REG_C_4_5 = 0x2, 12544 MLX5_IPSEC_ASO_REG_C_6_7 = 0x3, 12545 }; 12546 12547 enum { 12548 MLX5_IPSEC_ASO_MODE = 0x0, 12549 MLX5_IPSEC_ASO_REPLAY_PROTECTION = 0x1, 12550 MLX5_IPSEC_ASO_INC_SN = 0x2, 12551 }; 12552 12553 enum { 12554 MLX5_IPSEC_ASO_REPLAY_WIN_32BIT = 0x0, 12555 MLX5_IPSEC_ASO_REPLAY_WIN_64BIT = 0x1, 12556 MLX5_IPSEC_ASO_REPLAY_WIN_128BIT = 0x2, 12557 MLX5_IPSEC_ASO_REPLAY_WIN_256BIT = 0x3, 12558 }; 12559 12560 struct mlx5_ifc_ipsec_aso_bits { 12561 u8 valid[0x1]; 12562 u8 reserved_at_201[0x1]; 12563 u8 mode[0x2]; 12564 u8 window_sz[0x2]; 12565 u8 soft_lft_arm[0x1]; 12566 u8 hard_lft_arm[0x1]; 12567 u8 remove_flow_enable[0x1]; 12568 u8 esn_event_arm[0x1]; 12569 u8 reserved_at_20a[0x16]; 12570 12571 u8 remove_flow_pkt_cnt[0x20]; 12572 12573 u8 remove_flow_soft_lft[0x20]; 12574 12575 u8 reserved_at_260[0x80]; 12576 12577 u8 mode_parameter[0x20]; 12578 12579 u8 replay_protection_window[0x100]; 12580 }; 12581 12582 struct mlx5_ifc_ipsec_obj_bits { 12583 u8 modify_field_select[0x40]; 12584 u8 full_offload[0x1]; 12585 u8 reserved_at_41[0x1]; 12586 u8 esn_en[0x1]; 12587 u8 esn_overlap[0x1]; 12588 u8 reserved_at_44[0x2]; 12589 u8 icv_length[0x2]; 12590 u8 reserved_at_48[0x4]; 12591 u8 aso_return_reg[0x4]; 12592 u8 reserved_at_50[0x10]; 12593 12594 u8 esn_msb[0x20]; 12595 12596 u8 reserved_at_80[0x8]; 12597 u8 dekn[0x18]; 12598 12599 u8 salt[0x20]; 12600 12601 u8 implicit_iv[0x40]; 12602 12603 u8 reserved_at_100[0x8]; 12604 u8 ipsec_aso_access_pd[0x18]; 12605 u8 reserved_at_120[0xe0]; 12606 12607 struct mlx5_ifc_ipsec_aso_bits ipsec_aso; 12608 }; 12609 12610 struct mlx5_ifc_create_ipsec_obj_in_bits { 12611 struct mlx5_ifc_general_obj_in_cmd_hdr_bits general_obj_in_cmd_hdr; 12612 struct mlx5_ifc_ipsec_obj_bits ipsec_object; 12613 }; 12614 12615 enum { 12616 MLX5_MODIFY_IPSEC_BITMASK_ESN_OVERLAP = BIT(0), 12617 MLX5_MODIFY_IPSEC_BITMASK_ESN_MSB = BIT(1), 12618 }; 12619 12620 struct mlx5_ifc_query_ipsec_obj_out_bits { 12621 struct mlx5_ifc_general_obj_out_cmd_hdr_bits general_obj_out_cmd_hdr; 12622 struct mlx5_ifc_ipsec_obj_bits ipsec_object; 12623 }; 12624 12625 struct mlx5_ifc_modify_ipsec_obj_in_bits { 12626 struct mlx5_ifc_general_obj_in_cmd_hdr_bits general_obj_in_cmd_hdr; 12627 struct mlx5_ifc_ipsec_obj_bits ipsec_object; 12628 }; 12629 12630 enum { 12631 MLX5_MACSEC_ASO_REPLAY_PROTECTION = 0x1, 12632 }; 12633 12634 enum { 12635 MLX5_MACSEC_ASO_REPLAY_WIN_32BIT = 0x0, 12636 MLX5_MACSEC_ASO_REPLAY_WIN_64BIT = 0x1, 12637 MLX5_MACSEC_ASO_REPLAY_WIN_128BIT = 0x2, 12638 MLX5_MACSEC_ASO_REPLAY_WIN_256BIT = 0x3, 12639 }; 12640 12641 #define MLX5_MACSEC_ASO_INC_SN 0x2 12642 #define MLX5_MACSEC_ASO_REG_C_4_5 0x2 12643 12644 struct mlx5_ifc_macsec_aso_bits { 12645 u8 valid[0x1]; 12646 u8 reserved_at_1[0x1]; 12647 u8 mode[0x2]; 12648 u8 window_size[0x2]; 12649 u8 soft_lifetime_arm[0x1]; 12650 u8 hard_lifetime_arm[0x1]; 12651 u8 remove_flow_enable[0x1]; 12652 u8 epn_event_arm[0x1]; 12653 u8 reserved_at_a[0x16]; 12654 12655 u8 remove_flow_packet_count[0x20]; 12656 12657 u8 remove_flow_soft_lifetime[0x20]; 12658 12659 u8 reserved_at_60[0x80]; 12660 12661 u8 mode_parameter[0x20]; 12662 12663 u8 replay_protection_window[8][0x20]; 12664 }; 12665 12666 struct mlx5_ifc_macsec_offload_obj_bits { 12667 u8 modify_field_select[0x40]; 12668 12669 u8 confidentiality_en[0x1]; 12670 u8 reserved_at_41[0x1]; 12671 u8 epn_en[0x1]; 12672 u8 epn_overlap[0x1]; 12673 u8 reserved_at_44[0x2]; 12674 u8 confidentiality_offset[0x2]; 12675 u8 reserved_at_48[0x4]; 12676 u8 aso_return_reg[0x4]; 12677 u8 reserved_at_50[0x10]; 12678 12679 u8 epn_msb[0x20]; 12680 12681 u8 reserved_at_80[0x8]; 12682 u8 dekn[0x18]; 12683 12684 u8 reserved_at_a0[0x20]; 12685 12686 u8 sci[0x40]; 12687 12688 u8 reserved_at_100[0x8]; 12689 u8 macsec_aso_access_pd[0x18]; 12690 12691 u8 reserved_at_120[0x60]; 12692 12693 u8 salt[3][0x20]; 12694 12695 u8 reserved_at_1e0[0x20]; 12696 12697 struct mlx5_ifc_macsec_aso_bits macsec_aso; 12698 }; 12699 12700 struct mlx5_ifc_create_macsec_obj_in_bits { 12701 struct mlx5_ifc_general_obj_in_cmd_hdr_bits general_obj_in_cmd_hdr; 12702 struct mlx5_ifc_macsec_offload_obj_bits macsec_object; 12703 }; 12704 12705 struct mlx5_ifc_modify_macsec_obj_in_bits { 12706 struct mlx5_ifc_general_obj_in_cmd_hdr_bits general_obj_in_cmd_hdr; 12707 struct mlx5_ifc_macsec_offload_obj_bits macsec_object; 12708 }; 12709 12710 enum { 12711 MLX5_MODIFY_MACSEC_BITMASK_EPN_OVERLAP = BIT(0), 12712 MLX5_MODIFY_MACSEC_BITMASK_EPN_MSB = BIT(1), 12713 }; 12714 12715 struct mlx5_ifc_query_macsec_obj_out_bits { 12716 struct mlx5_ifc_general_obj_out_cmd_hdr_bits general_obj_out_cmd_hdr; 12717 struct mlx5_ifc_macsec_offload_obj_bits macsec_object; 12718 }; 12719 12720 struct mlx5_ifc_wrapped_dek_bits { 12721 u8 gcm_iv[0x60]; 12722 12723 u8 reserved_at_60[0x20]; 12724 12725 u8 const0[0x1]; 12726 u8 key_size[0x1]; 12727 u8 reserved_at_82[0x2]; 12728 u8 key2_invalid[0x1]; 12729 u8 reserved_at_85[0x3]; 12730 u8 pd[0x18]; 12731 12732 u8 key_purpose[0x5]; 12733 u8 reserved_at_a5[0x13]; 12734 u8 kek_id[0x8]; 12735 12736 u8 reserved_at_c0[0x40]; 12737 12738 u8 key1[0x8][0x20]; 12739 12740 u8 key2[0x8][0x20]; 12741 12742 u8 reserved_at_300[0x40]; 12743 12744 u8 const1[0x1]; 12745 u8 reserved_at_341[0x1f]; 12746 12747 u8 reserved_at_360[0x20]; 12748 12749 u8 auth_tag[0x80]; 12750 }; 12751 12752 struct mlx5_ifc_encryption_key_obj_bits { 12753 u8 modify_field_select[0x40]; 12754 12755 u8 state[0x8]; 12756 u8 sw_wrapped[0x1]; 12757 u8 reserved_at_49[0xb]; 12758 u8 key_size[0x4]; 12759 u8 reserved_at_58[0x4]; 12760 u8 key_purpose[0x4]; 12761 12762 u8 reserved_at_60[0x8]; 12763 u8 pd[0x18]; 12764 12765 u8 reserved_at_80[0x100]; 12766 12767 u8 opaque[0x40]; 12768 12769 u8 reserved_at_1c0[0x40]; 12770 12771 u8 key[8][0x80]; 12772 12773 u8 sw_wrapped_dek[8][0x80]; 12774 12775 u8 reserved_at_a00[0x600]; 12776 }; 12777 12778 struct mlx5_ifc_create_encryption_key_in_bits { 12779 struct mlx5_ifc_general_obj_in_cmd_hdr_bits general_obj_in_cmd_hdr; 12780 struct mlx5_ifc_encryption_key_obj_bits encryption_key_object; 12781 }; 12782 12783 struct mlx5_ifc_modify_encryption_key_in_bits { 12784 struct mlx5_ifc_general_obj_in_cmd_hdr_bits general_obj_in_cmd_hdr; 12785 struct mlx5_ifc_encryption_key_obj_bits encryption_key_object; 12786 }; 12787 12788 enum { 12789 MLX5_FLOW_METER_MODE_BYTES_IP_LENGTH = 0x0, 12790 MLX5_FLOW_METER_MODE_BYTES_CALC_WITH_L2 = 0x1, 12791 MLX5_FLOW_METER_MODE_BYTES_CALC_WITH_L2_IPG = 0x2, 12792 MLX5_FLOW_METER_MODE_NUM_PACKETS = 0x3, 12793 }; 12794 12795 struct mlx5_ifc_flow_meter_parameters_bits { 12796 u8 valid[0x1]; 12797 u8 bucket_overflow[0x1]; 12798 u8 start_color[0x2]; 12799 u8 both_buckets_on_green[0x1]; 12800 u8 reserved_at_5[0x1]; 12801 u8 meter_mode[0x2]; 12802 u8 reserved_at_8[0x18]; 12803 12804 u8 reserved_at_20[0x20]; 12805 12806 u8 reserved_at_40[0x3]; 12807 u8 cbs_exponent[0x5]; 12808 u8 cbs_mantissa[0x8]; 12809 u8 reserved_at_50[0x3]; 12810 u8 cir_exponent[0x5]; 12811 u8 cir_mantissa[0x8]; 12812 12813 u8 reserved_at_60[0x20]; 12814 12815 u8 reserved_at_80[0x3]; 12816 u8 ebs_exponent[0x5]; 12817 u8 ebs_mantissa[0x8]; 12818 u8 reserved_at_90[0x3]; 12819 u8 eir_exponent[0x5]; 12820 u8 eir_mantissa[0x8]; 12821 12822 u8 reserved_at_a0[0x60]; 12823 }; 12824 12825 struct mlx5_ifc_flow_meter_aso_obj_bits { 12826 u8 modify_field_select[0x40]; 12827 12828 u8 reserved_at_40[0x40]; 12829 12830 u8 reserved_at_80[0x8]; 12831 u8 meter_aso_access_pd[0x18]; 12832 12833 u8 reserved_at_a0[0x160]; 12834 12835 struct mlx5_ifc_flow_meter_parameters_bits flow_meter_parameters[2]; 12836 }; 12837 12838 struct mlx5_ifc_create_flow_meter_aso_obj_in_bits { 12839 struct mlx5_ifc_general_obj_in_cmd_hdr_bits hdr; 12840 struct mlx5_ifc_flow_meter_aso_obj_bits flow_meter_aso_obj; 12841 }; 12842 12843 struct mlx5_ifc_int_kek_obj_bits { 12844 u8 modify_field_select[0x40]; 12845 12846 u8 state[0x8]; 12847 u8 auto_gen[0x1]; 12848 u8 reserved_at_49[0xb]; 12849 u8 key_size[0x4]; 12850 u8 reserved_at_58[0x8]; 12851 12852 u8 reserved_at_60[0x8]; 12853 u8 pd[0x18]; 12854 12855 u8 reserved_at_80[0x180]; 12856 u8 key[8][0x80]; 12857 12858 u8 reserved_at_600[0x200]; 12859 }; 12860 12861 struct mlx5_ifc_create_int_kek_obj_in_bits { 12862 struct mlx5_ifc_general_obj_in_cmd_hdr_bits general_obj_in_cmd_hdr; 12863 struct mlx5_ifc_int_kek_obj_bits int_kek_object; 12864 }; 12865 12866 struct mlx5_ifc_create_int_kek_obj_out_bits { 12867 struct mlx5_ifc_general_obj_out_cmd_hdr_bits general_obj_out_cmd_hdr; 12868 struct mlx5_ifc_int_kek_obj_bits int_kek_object; 12869 }; 12870 12871 struct mlx5_ifc_sampler_obj_bits { 12872 u8 modify_field_select[0x40]; 12873 12874 u8 table_type[0x8]; 12875 u8 level[0x8]; 12876 u8 reserved_at_50[0xf]; 12877 u8 ignore_flow_level[0x1]; 12878 12879 u8 sample_ratio[0x20]; 12880 12881 u8 reserved_at_80[0x8]; 12882 u8 sample_table_id[0x18]; 12883 12884 u8 reserved_at_a0[0x8]; 12885 u8 default_table_id[0x18]; 12886 12887 u8 sw_steering_icm_address_rx[0x40]; 12888 u8 sw_steering_icm_address_tx[0x40]; 12889 12890 u8 reserved_at_140[0xa0]; 12891 }; 12892 12893 struct mlx5_ifc_create_sampler_obj_in_bits { 12894 struct mlx5_ifc_general_obj_in_cmd_hdr_bits general_obj_in_cmd_hdr; 12895 struct mlx5_ifc_sampler_obj_bits sampler_object; 12896 }; 12897 12898 struct mlx5_ifc_query_sampler_obj_out_bits { 12899 struct mlx5_ifc_general_obj_out_cmd_hdr_bits general_obj_out_cmd_hdr; 12900 struct mlx5_ifc_sampler_obj_bits sampler_object; 12901 }; 12902 12903 enum { 12904 MLX5_GENERAL_OBJECT_TYPE_ENCRYPTION_KEY_KEY_SIZE_128 = 0x0, 12905 MLX5_GENERAL_OBJECT_TYPE_ENCRYPTION_KEY_KEY_SIZE_256 = 0x1, 12906 }; 12907 12908 enum { 12909 MLX5_GENERAL_OBJECT_TYPE_ENCRYPTION_KEY_PURPOSE_TLS = 0x1, 12910 MLX5_GENERAL_OBJECT_TYPE_ENCRYPTION_KEY_PURPOSE_IPSEC = 0x2, 12911 MLX5_GENERAL_OBJECT_TYPE_ENCRYPTION_KEY_PURPOSE_MACSEC = 0x4, 12912 }; 12913 12914 struct mlx5_ifc_tls_static_params_bits { 12915 u8 const_2[0x2]; 12916 u8 tls_version[0x4]; 12917 u8 const_1[0x2]; 12918 u8 reserved_at_8[0x14]; 12919 u8 encryption_standard[0x4]; 12920 12921 u8 reserved_at_20[0x20]; 12922 12923 u8 initial_record_number[0x40]; 12924 12925 u8 resync_tcp_sn[0x20]; 12926 12927 u8 gcm_iv[0x20]; 12928 12929 u8 implicit_iv[0x40]; 12930 12931 u8 reserved_at_100[0x8]; 12932 u8 dek_index[0x18]; 12933 12934 u8 reserved_at_120[0xe0]; 12935 }; 12936 12937 struct mlx5_ifc_tls_progress_params_bits { 12938 u8 next_record_tcp_sn[0x20]; 12939 12940 u8 hw_resync_tcp_sn[0x20]; 12941 12942 u8 record_tracker_state[0x2]; 12943 u8 auth_state[0x2]; 12944 u8 reserved_at_44[0x4]; 12945 u8 hw_offset_record_number[0x18]; 12946 }; 12947 12948 enum { 12949 MLX5_MTT_PERM_READ = 1 << 0, 12950 MLX5_MTT_PERM_WRITE = 1 << 1, 12951 MLX5_MTT_PERM_RW = MLX5_MTT_PERM_READ | MLX5_MTT_PERM_WRITE, 12952 }; 12953 12954 enum { 12955 MLX5_SUSPEND_VHCA_IN_OP_MOD_SUSPEND_INITIATOR = 0x0, 12956 MLX5_SUSPEND_VHCA_IN_OP_MOD_SUSPEND_RESPONDER = 0x1, 12957 }; 12958 12959 struct mlx5_ifc_suspend_vhca_in_bits { 12960 u8 opcode[0x10]; 12961 u8 uid[0x10]; 12962 12963 u8 reserved_at_20[0x10]; 12964 u8 op_mod[0x10]; 12965 12966 u8 reserved_at_40[0x10]; 12967 u8 vhca_id[0x10]; 12968 12969 u8 reserved_at_60[0x20]; 12970 }; 12971 12972 struct mlx5_ifc_suspend_vhca_out_bits { 12973 u8 status[0x8]; 12974 u8 reserved_at_8[0x18]; 12975 12976 u8 syndrome[0x20]; 12977 12978 u8 reserved_at_40[0x40]; 12979 }; 12980 12981 enum { 12982 MLX5_RESUME_VHCA_IN_OP_MOD_RESUME_RESPONDER = 0x0, 12983 MLX5_RESUME_VHCA_IN_OP_MOD_RESUME_INITIATOR = 0x1, 12984 }; 12985 12986 struct mlx5_ifc_resume_vhca_in_bits { 12987 u8 opcode[0x10]; 12988 u8 uid[0x10]; 12989 12990 u8 reserved_at_20[0x10]; 12991 u8 op_mod[0x10]; 12992 12993 u8 reserved_at_40[0x10]; 12994 u8 vhca_id[0x10]; 12995 12996 u8 reserved_at_60[0x20]; 12997 }; 12998 12999 struct mlx5_ifc_resume_vhca_out_bits { 13000 u8 status[0x8]; 13001 u8 reserved_at_8[0x18]; 13002 13003 u8 syndrome[0x20]; 13004 13005 u8 reserved_at_40[0x40]; 13006 }; 13007 13008 struct mlx5_ifc_query_vhca_migration_state_in_bits { 13009 u8 opcode[0x10]; 13010 u8 uid[0x10]; 13011 13012 u8 reserved_at_20[0x10]; 13013 u8 op_mod[0x10]; 13014 13015 u8 incremental[0x1]; 13016 u8 chunk[0x1]; 13017 u8 reserved_at_42[0xe]; 13018 u8 vhca_id[0x10]; 13019 13020 u8 reserved_at_60[0x20]; 13021 }; 13022 13023 struct mlx5_ifc_query_vhca_migration_state_out_bits { 13024 u8 status[0x8]; 13025 u8 reserved_at_8[0x18]; 13026 13027 u8 syndrome[0x20]; 13028 13029 u8 reserved_at_40[0x40]; 13030 13031 u8 required_umem_size[0x20]; 13032 13033 u8 reserved_at_a0[0x20]; 13034 13035 u8 remaining_total_size[0x40]; 13036 13037 u8 reserved_at_100[0x100]; 13038 }; 13039 13040 struct mlx5_ifc_save_vhca_state_in_bits { 13041 u8 opcode[0x10]; 13042 u8 uid[0x10]; 13043 13044 u8 reserved_at_20[0x10]; 13045 u8 op_mod[0x10]; 13046 13047 u8 incremental[0x1]; 13048 u8 set_track[0x1]; 13049 u8 reserved_at_42[0xe]; 13050 u8 vhca_id[0x10]; 13051 13052 u8 reserved_at_60[0x20]; 13053 13054 u8 va[0x40]; 13055 13056 u8 mkey[0x20]; 13057 13058 u8 size[0x20]; 13059 }; 13060 13061 struct mlx5_ifc_save_vhca_state_out_bits { 13062 u8 status[0x8]; 13063 u8 reserved_at_8[0x18]; 13064 13065 u8 syndrome[0x20]; 13066 13067 u8 actual_image_size[0x20]; 13068 13069 u8 next_required_umem_size[0x20]; 13070 }; 13071 13072 struct mlx5_ifc_load_vhca_state_in_bits { 13073 u8 opcode[0x10]; 13074 u8 uid[0x10]; 13075 13076 u8 reserved_at_20[0x10]; 13077 u8 op_mod[0x10]; 13078 13079 u8 reserved_at_40[0x10]; 13080 u8 vhca_id[0x10]; 13081 13082 u8 reserved_at_60[0x20]; 13083 13084 u8 va[0x40]; 13085 13086 u8 mkey[0x20]; 13087 13088 u8 size[0x20]; 13089 }; 13090 13091 struct mlx5_ifc_load_vhca_state_out_bits { 13092 u8 status[0x8]; 13093 u8 reserved_at_8[0x18]; 13094 13095 u8 syndrome[0x20]; 13096 13097 u8 reserved_at_40[0x40]; 13098 }; 13099 13100 struct mlx5_ifc_adv_rdma_cap_bits { 13101 u8 rdma_transport_manager[0x1]; 13102 u8 rdma_transport_manager_other_eswitch[0x1]; 13103 u8 reserved_at_2[0x1e]; 13104 13105 u8 rcx_type[0x8]; 13106 u8 reserved_at_28[0x2]; 13107 u8 ps_entry_log_max_value[0x6]; 13108 u8 reserved_at_30[0x6]; 13109 u8 qp_max_ps_num_entry[0xa]; 13110 13111 u8 mp_max_num_queues[0x8]; 13112 u8 ps_user_context_max_log_size[0x8]; 13113 u8 message_based_qp_and_striding_wq[0x8]; 13114 u8 reserved_at_58[0x8]; 13115 13116 u8 max_receive_send_message_size_stride[0x10]; 13117 u8 reserved_at_70[0x10]; 13118 13119 u8 max_receive_send_message_size_byte[0x20]; 13120 13121 u8 reserved_at_a0[0x160]; 13122 13123 struct mlx5_ifc_flow_table_prop_layout_bits rdma_transport_rx_flow_table_properties; 13124 13125 struct mlx5_ifc_flow_table_prop_layout_bits rdma_transport_tx_flow_table_properties; 13126 13127 struct mlx5_ifc_flow_table_fields_supported_2_bits rdma_transport_rx_ft_field_support_2; 13128 13129 struct mlx5_ifc_flow_table_fields_supported_2_bits rdma_transport_tx_ft_field_support_2; 13130 13131 struct mlx5_ifc_flow_table_fields_supported_2_bits rdma_transport_rx_ft_field_bitmask_support_2; 13132 13133 struct mlx5_ifc_flow_table_fields_supported_2_bits rdma_transport_tx_ft_field_bitmask_support_2; 13134 13135 u8 reserved_at_800[0x3800]; 13136 }; 13137 13138 struct mlx5_ifc_adv_virtualization_cap_bits { 13139 u8 reserved_at_0[0x3]; 13140 u8 pg_track_log_max_num[0x5]; 13141 u8 pg_track_max_num_range[0x8]; 13142 u8 pg_track_log_min_addr_space[0x8]; 13143 u8 pg_track_log_max_addr_space[0x8]; 13144 13145 u8 reserved_at_20[0x3]; 13146 u8 pg_track_log_min_msg_size[0x5]; 13147 u8 reserved_at_28[0x3]; 13148 u8 pg_track_log_max_msg_size[0x5]; 13149 u8 reserved_at_30[0x3]; 13150 u8 pg_track_log_min_page_size[0x5]; 13151 u8 reserved_at_38[0x3]; 13152 u8 pg_track_log_max_page_size[0x5]; 13153 13154 u8 reserved_at_40[0x7c0]; 13155 }; 13156 13157 struct mlx5_ifc_page_track_report_entry_bits { 13158 u8 dirty_address_high[0x20]; 13159 13160 u8 dirty_address_low[0x20]; 13161 }; 13162 13163 enum { 13164 MLX5_PAGE_TRACK_STATE_TRACKING, 13165 MLX5_PAGE_TRACK_STATE_REPORTING, 13166 MLX5_PAGE_TRACK_STATE_ERROR, 13167 }; 13168 13169 struct mlx5_ifc_page_track_range_bits { 13170 u8 start_address[0x40]; 13171 13172 u8 length[0x40]; 13173 }; 13174 13175 struct mlx5_ifc_page_track_bits { 13176 u8 modify_field_select[0x40]; 13177 13178 u8 reserved_at_40[0x10]; 13179 u8 vhca_id[0x10]; 13180 13181 u8 reserved_at_60[0x20]; 13182 13183 u8 state[0x4]; 13184 u8 track_type[0x4]; 13185 u8 log_addr_space_size[0x8]; 13186 u8 reserved_at_90[0x3]; 13187 u8 log_page_size[0x5]; 13188 u8 reserved_at_98[0x3]; 13189 u8 log_msg_size[0x5]; 13190 13191 u8 reserved_at_a0[0x8]; 13192 u8 reporting_qpn[0x18]; 13193 13194 u8 reserved_at_c0[0x18]; 13195 u8 num_ranges[0x8]; 13196 13197 u8 reserved_at_e0[0x20]; 13198 13199 u8 range_start_address[0x40]; 13200 13201 u8 length[0x40]; 13202 13203 struct mlx5_ifc_page_track_range_bits track_range[0]; 13204 }; 13205 13206 struct mlx5_ifc_create_page_track_obj_in_bits { 13207 struct mlx5_ifc_general_obj_in_cmd_hdr_bits general_obj_in_cmd_hdr; 13208 struct mlx5_ifc_page_track_bits obj_context; 13209 }; 13210 13211 struct mlx5_ifc_modify_page_track_obj_in_bits { 13212 struct mlx5_ifc_general_obj_in_cmd_hdr_bits general_obj_in_cmd_hdr; 13213 struct mlx5_ifc_page_track_bits obj_context; 13214 }; 13215 13216 struct mlx5_ifc_query_page_track_obj_out_bits { 13217 struct mlx5_ifc_general_obj_out_cmd_hdr_bits general_obj_out_cmd_hdr; 13218 struct mlx5_ifc_page_track_bits obj_context; 13219 }; 13220 13221 struct mlx5_ifc_msecq_reg_bits { 13222 u8 reserved_at_0[0x20]; 13223 13224 u8 reserved_at_20[0x12]; 13225 u8 network_option[0x2]; 13226 u8 local_ssm_code[0x4]; 13227 u8 local_enhanced_ssm_code[0x8]; 13228 13229 u8 local_clock_identity[0x40]; 13230 13231 u8 reserved_at_80[0x180]; 13232 }; 13233 13234 enum { 13235 MLX5_MSEES_FIELD_SELECT_ENABLE = BIT(0), 13236 MLX5_MSEES_FIELD_SELECT_ADMIN_STATUS = BIT(1), 13237 MLX5_MSEES_FIELD_SELECT_ADMIN_FREQ_MEASURE = BIT(2), 13238 }; 13239 13240 enum mlx5_msees_admin_status { 13241 MLX5_MSEES_ADMIN_STATUS_FREE_RUNNING = 0x0, 13242 MLX5_MSEES_ADMIN_STATUS_TRACK = 0x1, 13243 }; 13244 13245 enum mlx5_msees_oper_status { 13246 MLX5_MSEES_OPER_STATUS_FREE_RUNNING = 0x0, 13247 MLX5_MSEES_OPER_STATUS_SELF_TRACK = 0x1, 13248 MLX5_MSEES_OPER_STATUS_OTHER_TRACK = 0x2, 13249 MLX5_MSEES_OPER_STATUS_HOLDOVER = 0x3, 13250 MLX5_MSEES_OPER_STATUS_FAIL_HOLDOVER = 0x4, 13251 MLX5_MSEES_OPER_STATUS_FAIL_FREE_RUNNING = 0x5, 13252 }; 13253 13254 enum mlx5_msees_failure_reason { 13255 MLX5_MSEES_FAILURE_REASON_UNDEFINED_ERROR = 0x0, 13256 MLX5_MSEES_FAILURE_REASON_PORT_DOWN = 0x1, 13257 MLX5_MSEES_FAILURE_REASON_TOO_HIGH_FREQUENCY_DIFF = 0x2, 13258 MLX5_MSEES_FAILURE_REASON_NET_SYNCHRONIZER_DEVICE_ERROR = 0x3, 13259 MLX5_MSEES_FAILURE_REASON_LACK_OF_RESOURCES = 0x4, 13260 }; 13261 13262 struct mlx5_ifc_msees_reg_bits { 13263 u8 reserved_at_0[0x8]; 13264 u8 local_port[0x8]; 13265 u8 pnat[0x2]; 13266 u8 lp_msb[0x2]; 13267 u8 reserved_at_14[0xc]; 13268 13269 u8 field_select[0x20]; 13270 13271 u8 admin_status[0x4]; 13272 u8 oper_status[0x4]; 13273 u8 ho_acq[0x1]; 13274 u8 reserved_at_49[0xc]; 13275 u8 admin_freq_measure[0x1]; 13276 u8 oper_freq_measure[0x1]; 13277 u8 failure_reason[0x9]; 13278 13279 u8 frequency_diff[0x20]; 13280 13281 u8 reserved_at_80[0x180]; 13282 }; 13283 13284 struct mlx5_ifc_mrtcq_reg_bits { 13285 u8 reserved_at_0[0x40]; 13286 13287 u8 rt_clock_identity[0x40]; 13288 13289 u8 reserved_at_80[0x180]; 13290 }; 13291 13292 struct mlx5_ifc_pcie_cong_event_obj_bits { 13293 u8 modify_select_field[0x40]; 13294 13295 u8 inbound_event_en[0x1]; 13296 u8 outbound_event_en[0x1]; 13297 u8 reserved_at_42[0x1e]; 13298 13299 u8 reserved_at_60[0x1]; 13300 u8 inbound_cong_state[0x3]; 13301 u8 reserved_at_64[0x1]; 13302 u8 outbound_cong_state[0x3]; 13303 u8 reserved_at_68[0x18]; 13304 13305 u8 inbound_cong_low_threshold[0x10]; 13306 u8 inbound_cong_high_threshold[0x10]; 13307 13308 u8 outbound_cong_low_threshold[0x10]; 13309 u8 outbound_cong_high_threshold[0x10]; 13310 13311 u8 reserved_at_e0[0x340]; 13312 }; 13313 13314 struct mlx5_ifc_pcie_cong_event_cmd_in_bits { 13315 struct mlx5_ifc_general_obj_in_cmd_hdr_bits hdr; 13316 struct mlx5_ifc_pcie_cong_event_obj_bits cong_obj; 13317 }; 13318 13319 struct mlx5_ifc_pcie_cong_event_cmd_out_bits { 13320 struct mlx5_ifc_general_obj_out_cmd_hdr_bits hdr; 13321 struct mlx5_ifc_pcie_cong_event_obj_bits cong_obj; 13322 }; 13323 13324 enum mlx5e_pcie_cong_event_mod_field { 13325 MLX5_PCIE_CONG_EVENT_MOD_EVENT_EN = BIT(0), 13326 MLX5_PCIE_CONG_EVENT_MOD_THRESH = BIT(2), 13327 }; 13328 13329 #endif /* MLX5_IFC_H */ 13330