1 /* 2 * Copyright (c) 2013-2015, Mellanox Technologies, Ltd. All rights reserved. 3 * 4 * This software is available to you under a choice of one of two 5 * licenses. You may choose to be licensed under the terms of the GNU 6 * General Public License (GPL) Version 2, available from the file 7 * COPYING in the main directory of this source tree, or the 8 * OpenIB.org BSD license below: 9 * 10 * Redistribution and use in source and binary forms, with or 11 * without modification, are permitted provided that the following 12 * conditions are met: 13 * 14 * - Redistributions of source code must retain the above 15 * copyright notice, this list of conditions and the following 16 * disclaimer. 17 * 18 * - Redistributions in binary form must reproduce the above 19 * copyright notice, this list of conditions and the following 20 * disclaimer in the documentation and/or other materials 21 * provided with the distribution. 22 * 23 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, 24 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF 25 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND 26 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS 27 * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN 28 * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN 29 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE 30 * SOFTWARE. 31 */ 32 #ifndef MLX5_IFC_H 33 #define MLX5_IFC_H 34 35 #include "mlx5_ifc_fpga.h" 36 37 enum { 38 MLX5_EVENT_TYPE_CODING_COMPLETION_EVENTS = 0x0, 39 MLX5_EVENT_TYPE_CODING_PATH_MIGRATED_SUCCEEDED = 0x1, 40 MLX5_EVENT_TYPE_CODING_COMMUNICATION_ESTABLISHED = 0x2, 41 MLX5_EVENT_TYPE_CODING_SEND_QUEUE_DRAINED = 0x3, 42 MLX5_EVENT_TYPE_CODING_LAST_WQE_REACHED = 0x13, 43 MLX5_EVENT_TYPE_CODING_SRQ_LIMIT = 0x14, 44 MLX5_EVENT_TYPE_CODING_DCT_ALL_CONNECTIONS_CLOSED = 0x1c, 45 MLX5_EVENT_TYPE_CODING_DCT_ACCESS_KEY_VIOLATION = 0x1d, 46 MLX5_EVENT_TYPE_CODING_CQ_ERROR = 0x4, 47 MLX5_EVENT_TYPE_CODING_LOCAL_WQ_CATASTROPHIC_ERROR = 0x5, 48 MLX5_EVENT_TYPE_CODING_PATH_MIGRATION_FAILED = 0x7, 49 MLX5_EVENT_TYPE_CODING_PAGE_FAULT_EVENT = 0xc, 50 MLX5_EVENT_TYPE_CODING_INVALID_REQUEST_LOCAL_WQ_ERROR = 0x10, 51 MLX5_EVENT_TYPE_CODING_LOCAL_ACCESS_VIOLATION_WQ_ERROR = 0x11, 52 MLX5_EVENT_TYPE_CODING_LOCAL_SRQ_CATASTROPHIC_ERROR = 0x12, 53 MLX5_EVENT_TYPE_CODING_INTERNAL_ERROR = 0x8, 54 MLX5_EVENT_TYPE_CODING_PORT_STATE_CHANGE = 0x9, 55 MLX5_EVENT_TYPE_CODING_GPIO_EVENT = 0x15, 56 MLX5_EVENT_TYPE_CODING_REMOTE_CONFIGURATION_PROTOCOL_EVENT = 0x19, 57 MLX5_EVENT_TYPE_CODING_DOORBELL_BLUEFLAME_CONGESTION_EVENT = 0x1a, 58 MLX5_EVENT_TYPE_CODING_STALL_VL_EVENT = 0x1b, 59 MLX5_EVENT_TYPE_CODING_DROPPED_PACKET_LOGGED_EVENT = 0x1f, 60 MLX5_EVENT_TYPE_CODING_COMMAND_INTERFACE_COMPLETION = 0xa, 61 MLX5_EVENT_TYPE_CODING_PAGE_REQUEST = 0xb, 62 MLX5_EVENT_TYPE_CODING_FPGA_ERROR = 0x20, 63 MLX5_EVENT_TYPE_CODING_FPGA_QP_ERROR = 0x21 64 }; 65 66 enum { 67 MLX5_SET_HCA_CAP_OP_MOD_GENERAL_DEVICE = 0x0, 68 MLX5_SET_HCA_CAP_OP_MOD_ETHERNET_OFFLOADS = 0x1, 69 MLX5_SET_HCA_CAP_OP_MOD_ODP = 0x2, 70 MLX5_SET_HCA_CAP_OP_MOD_ATOMIC = 0x3, 71 MLX5_SET_HCA_CAP_OP_MOD_ROCE = 0x4, 72 MLX5_SET_HCA_CAP_OP_MOD_IPSEC = 0x15, 73 MLX5_SET_HCA_CAP_OP_MOD_GENERAL_DEVICE2 = 0x20, 74 MLX5_SET_HCA_CAP_OP_MOD_PORT_SELECTION = 0x25, 75 }; 76 77 enum { 78 MLX5_SHARED_RESOURCE_UID = 0xffff, 79 }; 80 81 enum { 82 MLX5_OBJ_TYPE_SW_ICM = 0x0008, 83 MLX5_OBJ_TYPE_HEADER_MODIFY_ARGUMENT = 0x23, 84 }; 85 86 enum { 87 MLX5_GENERAL_OBJ_TYPES_CAP_SW_ICM = (1ULL << MLX5_OBJ_TYPE_SW_ICM), 88 MLX5_GENERAL_OBJ_TYPES_CAP_GENEVE_TLV_OPT = (1ULL << 11), 89 MLX5_GENERAL_OBJ_TYPES_CAP_VIRTIO_NET_Q = (1ULL << 13), 90 MLX5_GENERAL_OBJ_TYPES_CAP_HEADER_MODIFY_ARGUMENT = 91 (1ULL << MLX5_OBJ_TYPE_HEADER_MODIFY_ARGUMENT), 92 MLX5_GENERAL_OBJ_TYPES_CAP_MACSEC_OFFLOAD = (1ULL << 39), 93 }; 94 95 enum { 96 MLX5_OBJ_TYPE_GENEVE_TLV_OPT = 0x000b, 97 MLX5_OBJ_TYPE_VIRTIO_NET_Q = 0x000d, 98 MLX5_OBJ_TYPE_VIRTIO_Q_COUNTERS = 0x001c, 99 MLX5_OBJ_TYPE_MATCH_DEFINER = 0x0018, 100 MLX5_OBJ_TYPE_PAGE_TRACK = 0x46, 101 MLX5_OBJ_TYPE_MKEY = 0xff01, 102 MLX5_OBJ_TYPE_QP = 0xff02, 103 MLX5_OBJ_TYPE_PSV = 0xff03, 104 MLX5_OBJ_TYPE_RMP = 0xff04, 105 MLX5_OBJ_TYPE_XRC_SRQ = 0xff05, 106 MLX5_OBJ_TYPE_RQ = 0xff06, 107 MLX5_OBJ_TYPE_SQ = 0xff07, 108 MLX5_OBJ_TYPE_TIR = 0xff08, 109 MLX5_OBJ_TYPE_TIS = 0xff09, 110 MLX5_OBJ_TYPE_DCT = 0xff0a, 111 MLX5_OBJ_TYPE_XRQ = 0xff0b, 112 MLX5_OBJ_TYPE_RQT = 0xff0e, 113 MLX5_OBJ_TYPE_FLOW_COUNTER = 0xff0f, 114 MLX5_OBJ_TYPE_CQ = 0xff10, 115 }; 116 117 enum { 118 MLX5_CMD_OP_QUERY_HCA_CAP = 0x100, 119 MLX5_CMD_OP_QUERY_ADAPTER = 0x101, 120 MLX5_CMD_OP_INIT_HCA = 0x102, 121 MLX5_CMD_OP_TEARDOWN_HCA = 0x103, 122 MLX5_CMD_OP_ENABLE_HCA = 0x104, 123 MLX5_CMD_OP_DISABLE_HCA = 0x105, 124 MLX5_CMD_OP_QUERY_PAGES = 0x107, 125 MLX5_CMD_OP_MANAGE_PAGES = 0x108, 126 MLX5_CMD_OP_SET_HCA_CAP = 0x109, 127 MLX5_CMD_OP_QUERY_ISSI = 0x10a, 128 MLX5_CMD_OP_SET_ISSI = 0x10b, 129 MLX5_CMD_OP_SET_DRIVER_VERSION = 0x10d, 130 MLX5_CMD_OP_QUERY_SF_PARTITION = 0x111, 131 MLX5_CMD_OP_ALLOC_SF = 0x113, 132 MLX5_CMD_OP_DEALLOC_SF = 0x114, 133 MLX5_CMD_OP_SUSPEND_VHCA = 0x115, 134 MLX5_CMD_OP_RESUME_VHCA = 0x116, 135 MLX5_CMD_OP_QUERY_VHCA_MIGRATION_STATE = 0x117, 136 MLX5_CMD_OP_SAVE_VHCA_STATE = 0x118, 137 MLX5_CMD_OP_LOAD_VHCA_STATE = 0x119, 138 MLX5_CMD_OP_CREATE_MKEY = 0x200, 139 MLX5_CMD_OP_QUERY_MKEY = 0x201, 140 MLX5_CMD_OP_DESTROY_MKEY = 0x202, 141 MLX5_CMD_OP_QUERY_SPECIAL_CONTEXTS = 0x203, 142 MLX5_CMD_OP_PAGE_FAULT_RESUME = 0x204, 143 MLX5_CMD_OP_ALLOC_MEMIC = 0x205, 144 MLX5_CMD_OP_DEALLOC_MEMIC = 0x206, 145 MLX5_CMD_OP_MODIFY_MEMIC = 0x207, 146 MLX5_CMD_OP_CREATE_EQ = 0x301, 147 MLX5_CMD_OP_DESTROY_EQ = 0x302, 148 MLX5_CMD_OP_QUERY_EQ = 0x303, 149 MLX5_CMD_OP_GEN_EQE = 0x304, 150 MLX5_CMD_OP_CREATE_CQ = 0x400, 151 MLX5_CMD_OP_DESTROY_CQ = 0x401, 152 MLX5_CMD_OP_QUERY_CQ = 0x402, 153 MLX5_CMD_OP_MODIFY_CQ = 0x403, 154 MLX5_CMD_OP_CREATE_QP = 0x500, 155 MLX5_CMD_OP_DESTROY_QP = 0x501, 156 MLX5_CMD_OP_RST2INIT_QP = 0x502, 157 MLX5_CMD_OP_INIT2RTR_QP = 0x503, 158 MLX5_CMD_OP_RTR2RTS_QP = 0x504, 159 MLX5_CMD_OP_RTS2RTS_QP = 0x505, 160 MLX5_CMD_OP_SQERR2RTS_QP = 0x506, 161 MLX5_CMD_OP_2ERR_QP = 0x507, 162 MLX5_CMD_OP_2RST_QP = 0x50a, 163 MLX5_CMD_OP_QUERY_QP = 0x50b, 164 MLX5_CMD_OP_SQD_RTS_QP = 0x50c, 165 MLX5_CMD_OP_INIT2INIT_QP = 0x50e, 166 MLX5_CMD_OP_CREATE_PSV = 0x600, 167 MLX5_CMD_OP_DESTROY_PSV = 0x601, 168 MLX5_CMD_OP_CREATE_SRQ = 0x700, 169 MLX5_CMD_OP_DESTROY_SRQ = 0x701, 170 MLX5_CMD_OP_QUERY_SRQ = 0x702, 171 MLX5_CMD_OP_ARM_RQ = 0x703, 172 MLX5_CMD_OP_CREATE_XRC_SRQ = 0x705, 173 MLX5_CMD_OP_DESTROY_XRC_SRQ = 0x706, 174 MLX5_CMD_OP_QUERY_XRC_SRQ = 0x707, 175 MLX5_CMD_OP_ARM_XRC_SRQ = 0x708, 176 MLX5_CMD_OP_CREATE_DCT = 0x710, 177 MLX5_CMD_OP_DESTROY_DCT = 0x711, 178 MLX5_CMD_OP_DRAIN_DCT = 0x712, 179 MLX5_CMD_OP_QUERY_DCT = 0x713, 180 MLX5_CMD_OP_ARM_DCT_FOR_KEY_VIOLATION = 0x714, 181 MLX5_CMD_OP_CREATE_XRQ = 0x717, 182 MLX5_CMD_OP_DESTROY_XRQ = 0x718, 183 MLX5_CMD_OP_QUERY_XRQ = 0x719, 184 MLX5_CMD_OP_ARM_XRQ = 0x71a, 185 MLX5_CMD_OP_QUERY_XRQ_DC_PARAMS_ENTRY = 0x725, 186 MLX5_CMD_OP_SET_XRQ_DC_PARAMS_ENTRY = 0x726, 187 MLX5_CMD_OP_QUERY_XRQ_ERROR_PARAMS = 0x727, 188 MLX5_CMD_OP_RELEASE_XRQ_ERROR = 0x729, 189 MLX5_CMD_OP_MODIFY_XRQ = 0x72a, 190 MLX5_CMD_OP_QUERY_ESW_FUNCTIONS = 0x740, 191 MLX5_CMD_OP_QUERY_VPORT_STATE = 0x750, 192 MLX5_CMD_OP_MODIFY_VPORT_STATE = 0x751, 193 MLX5_CMD_OP_QUERY_ESW_VPORT_CONTEXT = 0x752, 194 MLX5_CMD_OP_MODIFY_ESW_VPORT_CONTEXT = 0x753, 195 MLX5_CMD_OP_QUERY_NIC_VPORT_CONTEXT = 0x754, 196 MLX5_CMD_OP_MODIFY_NIC_VPORT_CONTEXT = 0x755, 197 MLX5_CMD_OP_QUERY_ROCE_ADDRESS = 0x760, 198 MLX5_CMD_OP_SET_ROCE_ADDRESS = 0x761, 199 MLX5_CMD_OP_QUERY_HCA_VPORT_CONTEXT = 0x762, 200 MLX5_CMD_OP_MODIFY_HCA_VPORT_CONTEXT = 0x763, 201 MLX5_CMD_OP_QUERY_HCA_VPORT_GID = 0x764, 202 MLX5_CMD_OP_QUERY_HCA_VPORT_PKEY = 0x765, 203 MLX5_CMD_OP_QUERY_VNIC_ENV = 0x76f, 204 MLX5_CMD_OP_QUERY_VPORT_COUNTER = 0x770, 205 MLX5_CMD_OP_ALLOC_Q_COUNTER = 0x771, 206 MLX5_CMD_OP_DEALLOC_Q_COUNTER = 0x772, 207 MLX5_CMD_OP_QUERY_Q_COUNTER = 0x773, 208 MLX5_CMD_OP_SET_MONITOR_COUNTER = 0x774, 209 MLX5_CMD_OP_ARM_MONITOR_COUNTER = 0x775, 210 MLX5_CMD_OP_SET_PP_RATE_LIMIT = 0x780, 211 MLX5_CMD_OP_QUERY_RATE_LIMIT = 0x781, 212 MLX5_CMD_OP_CREATE_SCHEDULING_ELEMENT = 0x782, 213 MLX5_CMD_OP_DESTROY_SCHEDULING_ELEMENT = 0x783, 214 MLX5_CMD_OP_QUERY_SCHEDULING_ELEMENT = 0x784, 215 MLX5_CMD_OP_MODIFY_SCHEDULING_ELEMENT = 0x785, 216 MLX5_CMD_OP_CREATE_QOS_PARA_VPORT = 0x786, 217 MLX5_CMD_OP_DESTROY_QOS_PARA_VPORT = 0x787, 218 MLX5_CMD_OP_ALLOC_PD = 0x800, 219 MLX5_CMD_OP_DEALLOC_PD = 0x801, 220 MLX5_CMD_OP_ALLOC_UAR = 0x802, 221 MLX5_CMD_OP_DEALLOC_UAR = 0x803, 222 MLX5_CMD_OP_CONFIG_INT_MODERATION = 0x804, 223 MLX5_CMD_OP_ACCESS_REG = 0x805, 224 MLX5_CMD_OP_ATTACH_TO_MCG = 0x806, 225 MLX5_CMD_OP_DETACH_FROM_MCG = 0x807, 226 MLX5_CMD_OP_GET_DROPPED_PACKET_LOG = 0x80a, 227 MLX5_CMD_OP_MAD_IFC = 0x50d, 228 MLX5_CMD_OP_QUERY_MAD_DEMUX = 0x80b, 229 MLX5_CMD_OP_SET_MAD_DEMUX = 0x80c, 230 MLX5_CMD_OP_NOP = 0x80d, 231 MLX5_CMD_OP_ALLOC_XRCD = 0x80e, 232 MLX5_CMD_OP_DEALLOC_XRCD = 0x80f, 233 MLX5_CMD_OP_ALLOC_TRANSPORT_DOMAIN = 0x816, 234 MLX5_CMD_OP_DEALLOC_TRANSPORT_DOMAIN = 0x817, 235 MLX5_CMD_OP_QUERY_CONG_STATUS = 0x822, 236 MLX5_CMD_OP_MODIFY_CONG_STATUS = 0x823, 237 MLX5_CMD_OP_QUERY_CONG_PARAMS = 0x824, 238 MLX5_CMD_OP_MODIFY_CONG_PARAMS = 0x825, 239 MLX5_CMD_OP_QUERY_CONG_STATISTICS = 0x826, 240 MLX5_CMD_OP_ADD_VXLAN_UDP_DPORT = 0x827, 241 MLX5_CMD_OP_DELETE_VXLAN_UDP_DPORT = 0x828, 242 MLX5_CMD_OP_SET_L2_TABLE_ENTRY = 0x829, 243 MLX5_CMD_OP_QUERY_L2_TABLE_ENTRY = 0x82a, 244 MLX5_CMD_OP_DELETE_L2_TABLE_ENTRY = 0x82b, 245 MLX5_CMD_OP_SET_WOL_ROL = 0x830, 246 MLX5_CMD_OP_QUERY_WOL_ROL = 0x831, 247 MLX5_CMD_OP_CREATE_LAG = 0x840, 248 MLX5_CMD_OP_MODIFY_LAG = 0x841, 249 MLX5_CMD_OP_QUERY_LAG = 0x842, 250 MLX5_CMD_OP_DESTROY_LAG = 0x843, 251 MLX5_CMD_OP_CREATE_VPORT_LAG = 0x844, 252 MLX5_CMD_OP_DESTROY_VPORT_LAG = 0x845, 253 MLX5_CMD_OP_CREATE_TIR = 0x900, 254 MLX5_CMD_OP_MODIFY_TIR = 0x901, 255 MLX5_CMD_OP_DESTROY_TIR = 0x902, 256 MLX5_CMD_OP_QUERY_TIR = 0x903, 257 MLX5_CMD_OP_CREATE_SQ = 0x904, 258 MLX5_CMD_OP_MODIFY_SQ = 0x905, 259 MLX5_CMD_OP_DESTROY_SQ = 0x906, 260 MLX5_CMD_OP_QUERY_SQ = 0x907, 261 MLX5_CMD_OP_CREATE_RQ = 0x908, 262 MLX5_CMD_OP_MODIFY_RQ = 0x909, 263 MLX5_CMD_OP_SET_DELAY_DROP_PARAMS = 0x910, 264 MLX5_CMD_OP_DESTROY_RQ = 0x90a, 265 MLX5_CMD_OP_QUERY_RQ = 0x90b, 266 MLX5_CMD_OP_CREATE_RMP = 0x90c, 267 MLX5_CMD_OP_MODIFY_RMP = 0x90d, 268 MLX5_CMD_OP_DESTROY_RMP = 0x90e, 269 MLX5_CMD_OP_QUERY_RMP = 0x90f, 270 MLX5_CMD_OP_CREATE_TIS = 0x912, 271 MLX5_CMD_OP_MODIFY_TIS = 0x913, 272 MLX5_CMD_OP_DESTROY_TIS = 0x914, 273 MLX5_CMD_OP_QUERY_TIS = 0x915, 274 MLX5_CMD_OP_CREATE_RQT = 0x916, 275 MLX5_CMD_OP_MODIFY_RQT = 0x917, 276 MLX5_CMD_OP_DESTROY_RQT = 0x918, 277 MLX5_CMD_OP_QUERY_RQT = 0x919, 278 MLX5_CMD_OP_SET_FLOW_TABLE_ROOT = 0x92f, 279 MLX5_CMD_OP_CREATE_FLOW_TABLE = 0x930, 280 MLX5_CMD_OP_DESTROY_FLOW_TABLE = 0x931, 281 MLX5_CMD_OP_QUERY_FLOW_TABLE = 0x932, 282 MLX5_CMD_OP_CREATE_FLOW_GROUP = 0x933, 283 MLX5_CMD_OP_DESTROY_FLOW_GROUP = 0x934, 284 MLX5_CMD_OP_QUERY_FLOW_GROUP = 0x935, 285 MLX5_CMD_OP_SET_FLOW_TABLE_ENTRY = 0x936, 286 MLX5_CMD_OP_QUERY_FLOW_TABLE_ENTRY = 0x937, 287 MLX5_CMD_OP_DELETE_FLOW_TABLE_ENTRY = 0x938, 288 MLX5_CMD_OP_ALLOC_FLOW_COUNTER = 0x939, 289 MLX5_CMD_OP_DEALLOC_FLOW_COUNTER = 0x93a, 290 MLX5_CMD_OP_QUERY_FLOW_COUNTER = 0x93b, 291 MLX5_CMD_OP_MODIFY_FLOW_TABLE = 0x93c, 292 MLX5_CMD_OP_ALLOC_PACKET_REFORMAT_CONTEXT = 0x93d, 293 MLX5_CMD_OP_DEALLOC_PACKET_REFORMAT_CONTEXT = 0x93e, 294 MLX5_CMD_OP_QUERY_PACKET_REFORMAT_CONTEXT = 0x93f, 295 MLX5_CMD_OP_ALLOC_MODIFY_HEADER_CONTEXT = 0x940, 296 MLX5_CMD_OP_DEALLOC_MODIFY_HEADER_CONTEXT = 0x941, 297 MLX5_CMD_OP_QUERY_MODIFY_HEADER_CONTEXT = 0x942, 298 MLX5_CMD_OP_FPGA_CREATE_QP = 0x960, 299 MLX5_CMD_OP_FPGA_MODIFY_QP = 0x961, 300 MLX5_CMD_OP_FPGA_QUERY_QP = 0x962, 301 MLX5_CMD_OP_FPGA_DESTROY_QP = 0x963, 302 MLX5_CMD_OP_FPGA_QUERY_QP_COUNTERS = 0x964, 303 MLX5_CMD_OP_CREATE_GENERAL_OBJECT = 0xa00, 304 MLX5_CMD_OP_MODIFY_GENERAL_OBJECT = 0xa01, 305 MLX5_CMD_OP_QUERY_GENERAL_OBJECT = 0xa02, 306 MLX5_CMD_OP_DESTROY_GENERAL_OBJECT = 0xa03, 307 MLX5_CMD_OP_CREATE_UCTX = 0xa04, 308 MLX5_CMD_OP_DESTROY_UCTX = 0xa06, 309 MLX5_CMD_OP_CREATE_UMEM = 0xa08, 310 MLX5_CMD_OP_DESTROY_UMEM = 0xa0a, 311 MLX5_CMD_OP_SYNC_STEERING = 0xb00, 312 MLX5_CMD_OP_QUERY_VHCA_STATE = 0xb0d, 313 MLX5_CMD_OP_MODIFY_VHCA_STATE = 0xb0e, 314 MLX5_CMD_OP_SYNC_CRYPTO = 0xb12, 315 MLX5_CMD_OP_ALLOW_OTHER_VHCA_ACCESS = 0xb16, 316 MLX5_CMD_OP_MAX 317 }; 318 319 /* Valid range for general commands that don't work over an object */ 320 enum { 321 MLX5_CMD_OP_GENERAL_START = 0xb00, 322 MLX5_CMD_OP_GENERAL_END = 0xd00, 323 }; 324 325 enum { 326 MLX5_FT_NIC_RX_2_NIC_RX_RDMA = BIT(0), 327 MLX5_FT_NIC_TX_RDMA_2_NIC_TX = BIT(1), 328 }; 329 330 enum { 331 MLX5_CMD_OP_MOD_UPDATE_HEADER_MODIFY_ARGUMENT = 0x1, 332 }; 333 334 struct mlx5_ifc_flow_table_fields_supported_bits { 335 u8 outer_dmac[0x1]; 336 u8 outer_smac[0x1]; 337 u8 outer_ether_type[0x1]; 338 u8 outer_ip_version[0x1]; 339 u8 outer_first_prio[0x1]; 340 u8 outer_first_cfi[0x1]; 341 u8 outer_first_vid[0x1]; 342 u8 outer_ipv4_ttl[0x1]; 343 u8 outer_second_prio[0x1]; 344 u8 outer_second_cfi[0x1]; 345 u8 outer_second_vid[0x1]; 346 u8 reserved_at_b[0x1]; 347 u8 outer_sip[0x1]; 348 u8 outer_dip[0x1]; 349 u8 outer_frag[0x1]; 350 u8 outer_ip_protocol[0x1]; 351 u8 outer_ip_ecn[0x1]; 352 u8 outer_ip_dscp[0x1]; 353 u8 outer_udp_sport[0x1]; 354 u8 outer_udp_dport[0x1]; 355 u8 outer_tcp_sport[0x1]; 356 u8 outer_tcp_dport[0x1]; 357 u8 outer_tcp_flags[0x1]; 358 u8 outer_gre_protocol[0x1]; 359 u8 outer_gre_key[0x1]; 360 u8 outer_vxlan_vni[0x1]; 361 u8 outer_geneve_vni[0x1]; 362 u8 outer_geneve_oam[0x1]; 363 u8 outer_geneve_protocol_type[0x1]; 364 u8 outer_geneve_opt_len[0x1]; 365 u8 source_vhca_port[0x1]; 366 u8 source_eswitch_port[0x1]; 367 368 u8 inner_dmac[0x1]; 369 u8 inner_smac[0x1]; 370 u8 inner_ether_type[0x1]; 371 u8 inner_ip_version[0x1]; 372 u8 inner_first_prio[0x1]; 373 u8 inner_first_cfi[0x1]; 374 u8 inner_first_vid[0x1]; 375 u8 reserved_at_27[0x1]; 376 u8 inner_second_prio[0x1]; 377 u8 inner_second_cfi[0x1]; 378 u8 inner_second_vid[0x1]; 379 u8 reserved_at_2b[0x1]; 380 u8 inner_sip[0x1]; 381 u8 inner_dip[0x1]; 382 u8 inner_frag[0x1]; 383 u8 inner_ip_protocol[0x1]; 384 u8 inner_ip_ecn[0x1]; 385 u8 inner_ip_dscp[0x1]; 386 u8 inner_udp_sport[0x1]; 387 u8 inner_udp_dport[0x1]; 388 u8 inner_tcp_sport[0x1]; 389 u8 inner_tcp_dport[0x1]; 390 u8 inner_tcp_flags[0x1]; 391 u8 reserved_at_37[0x9]; 392 393 u8 geneve_tlv_option_0_data[0x1]; 394 u8 geneve_tlv_option_0_exist[0x1]; 395 u8 reserved_at_42[0x3]; 396 u8 outer_first_mpls_over_udp[0x4]; 397 u8 outer_first_mpls_over_gre[0x4]; 398 u8 inner_first_mpls[0x4]; 399 u8 outer_first_mpls[0x4]; 400 u8 reserved_at_55[0x2]; 401 u8 outer_esp_spi[0x1]; 402 u8 reserved_at_58[0x2]; 403 u8 bth_dst_qp[0x1]; 404 u8 reserved_at_5b[0x5]; 405 406 u8 reserved_at_60[0x18]; 407 u8 metadata_reg_c_7[0x1]; 408 u8 metadata_reg_c_6[0x1]; 409 u8 metadata_reg_c_5[0x1]; 410 u8 metadata_reg_c_4[0x1]; 411 u8 metadata_reg_c_3[0x1]; 412 u8 metadata_reg_c_2[0x1]; 413 u8 metadata_reg_c_1[0x1]; 414 u8 metadata_reg_c_0[0x1]; 415 }; 416 417 /* Table 2170 - Flow Table Fields Supported 2 Format */ 418 struct mlx5_ifc_flow_table_fields_supported_2_bits { 419 u8 reserved_at_0[0x2]; 420 u8 inner_l4_type[0x1]; 421 u8 outer_l4_type[0x1]; 422 u8 reserved_at_4[0xa]; 423 u8 bth_opcode[0x1]; 424 u8 reserved_at_f[0x1]; 425 u8 tunnel_header_0_1[0x1]; 426 u8 reserved_at_11[0xf]; 427 428 u8 reserved_at_20[0x60]; 429 }; 430 431 struct mlx5_ifc_flow_table_prop_layout_bits { 432 u8 ft_support[0x1]; 433 u8 reserved_at_1[0x1]; 434 u8 flow_counter[0x1]; 435 u8 flow_modify_en[0x1]; 436 u8 modify_root[0x1]; 437 u8 identified_miss_table_mode[0x1]; 438 u8 flow_table_modify[0x1]; 439 u8 reformat[0x1]; 440 u8 decap[0x1]; 441 u8 reset_root_to_default[0x1]; 442 u8 pop_vlan[0x1]; 443 u8 push_vlan[0x1]; 444 u8 reserved_at_c[0x1]; 445 u8 pop_vlan_2[0x1]; 446 u8 push_vlan_2[0x1]; 447 u8 reformat_and_vlan_action[0x1]; 448 u8 reserved_at_10[0x1]; 449 u8 sw_owner[0x1]; 450 u8 reformat_l3_tunnel_to_l2[0x1]; 451 u8 reformat_l2_to_l3_tunnel[0x1]; 452 u8 reformat_and_modify_action[0x1]; 453 u8 ignore_flow_level[0x1]; 454 u8 reserved_at_16[0x1]; 455 u8 table_miss_action_domain[0x1]; 456 u8 termination_table[0x1]; 457 u8 reformat_and_fwd_to_table[0x1]; 458 u8 reserved_at_1a[0x2]; 459 u8 ipsec_encrypt[0x1]; 460 u8 ipsec_decrypt[0x1]; 461 u8 sw_owner_v2[0x1]; 462 u8 reserved_at_1f[0x1]; 463 464 u8 termination_table_raw_traffic[0x1]; 465 u8 reserved_at_21[0x1]; 466 u8 log_max_ft_size[0x6]; 467 u8 log_max_modify_header_context[0x8]; 468 u8 max_modify_header_actions[0x8]; 469 u8 max_ft_level[0x8]; 470 471 u8 reformat_add_esp_trasport[0x1]; 472 u8 reformat_l2_to_l3_esp_tunnel[0x1]; 473 u8 reformat_add_esp_transport_over_udp[0x1]; 474 u8 reformat_del_esp_trasport[0x1]; 475 u8 reformat_l3_esp_tunnel_to_l2[0x1]; 476 u8 reformat_del_esp_transport_over_udp[0x1]; 477 u8 execute_aso[0x1]; 478 u8 reserved_at_47[0x19]; 479 480 u8 reserved_at_60[0x2]; 481 u8 reformat_insert[0x1]; 482 u8 reformat_remove[0x1]; 483 u8 macsec_encrypt[0x1]; 484 u8 macsec_decrypt[0x1]; 485 u8 reserved_at_66[0x2]; 486 u8 reformat_add_macsec[0x1]; 487 u8 reformat_remove_macsec[0x1]; 488 u8 reserved_at_6a[0xe]; 489 u8 log_max_ft_num[0x8]; 490 491 u8 reserved_at_80[0x10]; 492 u8 log_max_flow_counter[0x8]; 493 u8 log_max_destination[0x8]; 494 495 u8 reserved_at_a0[0x18]; 496 u8 log_max_flow[0x8]; 497 498 u8 reserved_at_c0[0x40]; 499 500 struct mlx5_ifc_flow_table_fields_supported_bits ft_field_support; 501 502 struct mlx5_ifc_flow_table_fields_supported_bits ft_field_bitmask_support; 503 }; 504 505 struct mlx5_ifc_odp_per_transport_service_cap_bits { 506 u8 send[0x1]; 507 u8 receive[0x1]; 508 u8 write[0x1]; 509 u8 read[0x1]; 510 u8 atomic[0x1]; 511 u8 srq_receive[0x1]; 512 u8 reserved_at_6[0x1a]; 513 }; 514 515 struct mlx5_ifc_ipv4_layout_bits { 516 u8 reserved_at_0[0x60]; 517 518 u8 ipv4[0x20]; 519 }; 520 521 struct mlx5_ifc_ipv6_layout_bits { 522 u8 ipv6[16][0x8]; 523 }; 524 525 union mlx5_ifc_ipv6_layout_ipv4_layout_auto_bits { 526 struct mlx5_ifc_ipv6_layout_bits ipv6_layout; 527 struct mlx5_ifc_ipv4_layout_bits ipv4_layout; 528 u8 reserved_at_0[0x80]; 529 }; 530 531 enum { 532 MLX5_PACKET_L4_TYPE_NONE, 533 MLX5_PACKET_L4_TYPE_TCP, 534 MLX5_PACKET_L4_TYPE_UDP, 535 }; 536 537 struct mlx5_ifc_fte_match_set_lyr_2_4_bits { 538 u8 smac_47_16[0x20]; 539 540 u8 smac_15_0[0x10]; 541 u8 ethertype[0x10]; 542 543 u8 dmac_47_16[0x20]; 544 545 u8 dmac_15_0[0x10]; 546 u8 first_prio[0x3]; 547 u8 first_cfi[0x1]; 548 u8 first_vid[0xc]; 549 550 u8 ip_protocol[0x8]; 551 u8 ip_dscp[0x6]; 552 u8 ip_ecn[0x2]; 553 u8 cvlan_tag[0x1]; 554 u8 svlan_tag[0x1]; 555 u8 frag[0x1]; 556 u8 ip_version[0x4]; 557 u8 tcp_flags[0x9]; 558 559 u8 tcp_sport[0x10]; 560 u8 tcp_dport[0x10]; 561 562 u8 l4_type[0x2]; 563 u8 reserved_at_c2[0xe]; 564 u8 ipv4_ihl[0x4]; 565 u8 reserved_at_c4[0x4]; 566 567 u8 ttl_hoplimit[0x8]; 568 569 u8 udp_sport[0x10]; 570 u8 udp_dport[0x10]; 571 572 union mlx5_ifc_ipv6_layout_ipv4_layout_auto_bits src_ipv4_src_ipv6; 573 574 union mlx5_ifc_ipv6_layout_ipv4_layout_auto_bits dst_ipv4_dst_ipv6; 575 }; 576 577 struct mlx5_ifc_nvgre_key_bits { 578 u8 hi[0x18]; 579 u8 lo[0x8]; 580 }; 581 582 union mlx5_ifc_gre_key_bits { 583 struct mlx5_ifc_nvgre_key_bits nvgre; 584 u8 key[0x20]; 585 }; 586 587 struct mlx5_ifc_fte_match_set_misc_bits { 588 u8 gre_c_present[0x1]; 589 u8 reserved_at_1[0x1]; 590 u8 gre_k_present[0x1]; 591 u8 gre_s_present[0x1]; 592 u8 source_vhca_port[0x4]; 593 u8 source_sqn[0x18]; 594 595 u8 source_eswitch_owner_vhca_id[0x10]; 596 u8 source_port[0x10]; 597 598 u8 outer_second_prio[0x3]; 599 u8 outer_second_cfi[0x1]; 600 u8 outer_second_vid[0xc]; 601 u8 inner_second_prio[0x3]; 602 u8 inner_second_cfi[0x1]; 603 u8 inner_second_vid[0xc]; 604 605 u8 outer_second_cvlan_tag[0x1]; 606 u8 inner_second_cvlan_tag[0x1]; 607 u8 outer_second_svlan_tag[0x1]; 608 u8 inner_second_svlan_tag[0x1]; 609 u8 reserved_at_64[0xc]; 610 u8 gre_protocol[0x10]; 611 612 union mlx5_ifc_gre_key_bits gre_key; 613 614 u8 vxlan_vni[0x18]; 615 u8 bth_opcode[0x8]; 616 617 u8 geneve_vni[0x18]; 618 u8 reserved_at_d8[0x6]; 619 u8 geneve_tlv_option_0_exist[0x1]; 620 u8 geneve_oam[0x1]; 621 622 u8 reserved_at_e0[0xc]; 623 u8 outer_ipv6_flow_label[0x14]; 624 625 u8 reserved_at_100[0xc]; 626 u8 inner_ipv6_flow_label[0x14]; 627 628 u8 reserved_at_120[0xa]; 629 u8 geneve_opt_len[0x6]; 630 u8 geneve_protocol_type[0x10]; 631 632 u8 reserved_at_140[0x8]; 633 u8 bth_dst_qp[0x18]; 634 u8 inner_esp_spi[0x20]; 635 u8 outer_esp_spi[0x20]; 636 u8 reserved_at_1a0[0x60]; 637 }; 638 639 struct mlx5_ifc_fte_match_mpls_bits { 640 u8 mpls_label[0x14]; 641 u8 mpls_exp[0x3]; 642 u8 mpls_s_bos[0x1]; 643 u8 mpls_ttl[0x8]; 644 }; 645 646 struct mlx5_ifc_fte_match_set_misc2_bits { 647 struct mlx5_ifc_fte_match_mpls_bits outer_first_mpls; 648 649 struct mlx5_ifc_fte_match_mpls_bits inner_first_mpls; 650 651 struct mlx5_ifc_fte_match_mpls_bits outer_first_mpls_over_gre; 652 653 struct mlx5_ifc_fte_match_mpls_bits outer_first_mpls_over_udp; 654 655 u8 metadata_reg_c_7[0x20]; 656 657 u8 metadata_reg_c_6[0x20]; 658 659 u8 metadata_reg_c_5[0x20]; 660 661 u8 metadata_reg_c_4[0x20]; 662 663 u8 metadata_reg_c_3[0x20]; 664 665 u8 metadata_reg_c_2[0x20]; 666 667 u8 metadata_reg_c_1[0x20]; 668 669 u8 metadata_reg_c_0[0x20]; 670 671 u8 metadata_reg_a[0x20]; 672 673 u8 reserved_at_1a0[0x8]; 674 675 u8 macsec_syndrome[0x8]; 676 u8 ipsec_syndrome[0x8]; 677 u8 reserved_at_1b8[0x8]; 678 679 u8 reserved_at_1c0[0x40]; 680 }; 681 682 struct mlx5_ifc_fte_match_set_misc3_bits { 683 u8 inner_tcp_seq_num[0x20]; 684 685 u8 outer_tcp_seq_num[0x20]; 686 687 u8 inner_tcp_ack_num[0x20]; 688 689 u8 outer_tcp_ack_num[0x20]; 690 691 u8 reserved_at_80[0x8]; 692 u8 outer_vxlan_gpe_vni[0x18]; 693 694 u8 outer_vxlan_gpe_next_protocol[0x8]; 695 u8 outer_vxlan_gpe_flags[0x8]; 696 u8 reserved_at_b0[0x10]; 697 698 u8 icmp_header_data[0x20]; 699 700 u8 icmpv6_header_data[0x20]; 701 702 u8 icmp_type[0x8]; 703 u8 icmp_code[0x8]; 704 u8 icmpv6_type[0x8]; 705 u8 icmpv6_code[0x8]; 706 707 u8 geneve_tlv_option_0_data[0x20]; 708 709 u8 gtpu_teid[0x20]; 710 711 u8 gtpu_msg_type[0x8]; 712 u8 gtpu_msg_flags[0x8]; 713 u8 reserved_at_170[0x10]; 714 715 u8 gtpu_dw_2[0x20]; 716 717 u8 gtpu_first_ext_dw_0[0x20]; 718 719 u8 gtpu_dw_0[0x20]; 720 721 u8 reserved_at_1e0[0x20]; 722 }; 723 724 struct mlx5_ifc_fte_match_set_misc4_bits { 725 u8 prog_sample_field_value_0[0x20]; 726 727 u8 prog_sample_field_id_0[0x20]; 728 729 u8 prog_sample_field_value_1[0x20]; 730 731 u8 prog_sample_field_id_1[0x20]; 732 733 u8 prog_sample_field_value_2[0x20]; 734 735 u8 prog_sample_field_id_2[0x20]; 736 737 u8 prog_sample_field_value_3[0x20]; 738 739 u8 prog_sample_field_id_3[0x20]; 740 741 u8 reserved_at_100[0x100]; 742 }; 743 744 struct mlx5_ifc_fte_match_set_misc5_bits { 745 u8 macsec_tag_0[0x20]; 746 747 u8 macsec_tag_1[0x20]; 748 749 u8 macsec_tag_2[0x20]; 750 751 u8 macsec_tag_3[0x20]; 752 753 u8 tunnel_header_0[0x20]; 754 755 u8 tunnel_header_1[0x20]; 756 757 u8 tunnel_header_2[0x20]; 758 759 u8 tunnel_header_3[0x20]; 760 761 u8 reserved_at_100[0x100]; 762 }; 763 764 struct mlx5_ifc_cmd_pas_bits { 765 u8 pa_h[0x20]; 766 767 u8 pa_l[0x14]; 768 u8 reserved_at_34[0xc]; 769 }; 770 771 struct mlx5_ifc_uint64_bits { 772 u8 hi[0x20]; 773 774 u8 lo[0x20]; 775 }; 776 777 enum { 778 MLX5_ADS_STAT_RATE_NO_LIMIT = 0x0, 779 MLX5_ADS_STAT_RATE_2_5GBPS = 0x7, 780 MLX5_ADS_STAT_RATE_10GBPS = 0x8, 781 MLX5_ADS_STAT_RATE_30GBPS = 0x9, 782 MLX5_ADS_STAT_RATE_5GBPS = 0xa, 783 MLX5_ADS_STAT_RATE_20GBPS = 0xb, 784 MLX5_ADS_STAT_RATE_40GBPS = 0xc, 785 MLX5_ADS_STAT_RATE_60GBPS = 0xd, 786 MLX5_ADS_STAT_RATE_80GBPS = 0xe, 787 MLX5_ADS_STAT_RATE_120GBPS = 0xf, 788 }; 789 790 struct mlx5_ifc_ads_bits { 791 u8 fl[0x1]; 792 u8 free_ar[0x1]; 793 u8 reserved_at_2[0xe]; 794 u8 pkey_index[0x10]; 795 796 u8 reserved_at_20[0x8]; 797 u8 grh[0x1]; 798 u8 mlid[0x7]; 799 u8 rlid[0x10]; 800 801 u8 ack_timeout[0x5]; 802 u8 reserved_at_45[0x3]; 803 u8 src_addr_index[0x8]; 804 u8 reserved_at_50[0x4]; 805 u8 stat_rate[0x4]; 806 u8 hop_limit[0x8]; 807 808 u8 reserved_at_60[0x4]; 809 u8 tclass[0x8]; 810 u8 flow_label[0x14]; 811 812 u8 rgid_rip[16][0x8]; 813 814 u8 reserved_at_100[0x4]; 815 u8 f_dscp[0x1]; 816 u8 f_ecn[0x1]; 817 u8 reserved_at_106[0x1]; 818 u8 f_eth_prio[0x1]; 819 u8 ecn[0x2]; 820 u8 dscp[0x6]; 821 u8 udp_sport[0x10]; 822 823 u8 dei_cfi[0x1]; 824 u8 eth_prio[0x3]; 825 u8 sl[0x4]; 826 u8 vhca_port_num[0x8]; 827 u8 rmac_47_32[0x10]; 828 829 u8 rmac_31_0[0x20]; 830 }; 831 832 struct mlx5_ifc_flow_table_nic_cap_bits { 833 u8 nic_rx_multi_path_tirs[0x1]; 834 u8 nic_rx_multi_path_tirs_fts[0x1]; 835 u8 allow_sniffer_and_nic_rx_shared_tir[0x1]; 836 u8 reserved_at_3[0x4]; 837 u8 sw_owner_reformat_supported[0x1]; 838 u8 reserved_at_8[0x18]; 839 840 u8 encap_general_header[0x1]; 841 u8 reserved_at_21[0xa]; 842 u8 log_max_packet_reformat_context[0x5]; 843 u8 reserved_at_30[0x6]; 844 u8 max_encap_header_size[0xa]; 845 u8 reserved_at_40[0x1c0]; 846 847 struct mlx5_ifc_flow_table_prop_layout_bits flow_table_properties_nic_receive; 848 849 struct mlx5_ifc_flow_table_prop_layout_bits flow_table_properties_nic_receive_rdma; 850 851 struct mlx5_ifc_flow_table_prop_layout_bits flow_table_properties_nic_receive_sniffer; 852 853 struct mlx5_ifc_flow_table_prop_layout_bits flow_table_properties_nic_transmit; 854 855 struct mlx5_ifc_flow_table_prop_layout_bits flow_table_properties_nic_transmit_rdma; 856 857 struct mlx5_ifc_flow_table_prop_layout_bits flow_table_properties_nic_transmit_sniffer; 858 859 u8 reserved_at_e00[0x600]; 860 861 struct mlx5_ifc_flow_table_fields_supported_2_bits ft_field_support_2_nic_receive; 862 863 u8 reserved_at_1480[0x80]; 864 865 struct mlx5_ifc_flow_table_fields_supported_2_bits ft_field_support_2_nic_receive_rdma; 866 867 u8 reserved_at_1580[0x280]; 868 869 struct mlx5_ifc_flow_table_fields_supported_2_bits ft_field_support_2_nic_transmit_rdma; 870 871 u8 reserved_at_1880[0x780]; 872 873 u8 sw_steering_nic_rx_action_drop_icm_address[0x40]; 874 875 u8 sw_steering_nic_tx_action_drop_icm_address[0x40]; 876 877 u8 sw_steering_nic_tx_action_allow_icm_address[0x40]; 878 879 u8 reserved_at_20c0[0x5f40]; 880 }; 881 882 struct mlx5_ifc_port_selection_cap_bits { 883 u8 reserved_at_0[0x10]; 884 u8 port_select_flow_table[0x1]; 885 u8 reserved_at_11[0x1]; 886 u8 port_select_flow_table_bypass[0x1]; 887 u8 reserved_at_13[0xd]; 888 889 u8 reserved_at_20[0x1e0]; 890 891 struct mlx5_ifc_flow_table_prop_layout_bits flow_table_properties_port_selection; 892 893 struct mlx5_ifc_flow_table_fields_supported_2_bits ft_field_support_2_port_selection; 894 895 u8 reserved_at_480[0x7b80]; 896 }; 897 898 enum { 899 MLX5_FDB_TO_VPORT_REG_C_0 = 0x01, 900 MLX5_FDB_TO_VPORT_REG_C_1 = 0x02, 901 MLX5_FDB_TO_VPORT_REG_C_2 = 0x04, 902 MLX5_FDB_TO_VPORT_REG_C_3 = 0x08, 903 MLX5_FDB_TO_VPORT_REG_C_4 = 0x10, 904 MLX5_FDB_TO_VPORT_REG_C_5 = 0x20, 905 MLX5_FDB_TO_VPORT_REG_C_6 = 0x40, 906 MLX5_FDB_TO_VPORT_REG_C_7 = 0x80, 907 }; 908 909 struct mlx5_ifc_flow_table_eswitch_cap_bits { 910 u8 fdb_to_vport_reg_c_id[0x8]; 911 u8 reserved_at_8[0x5]; 912 u8 fdb_uplink_hairpin[0x1]; 913 u8 fdb_multi_path_any_table_limit_regc[0x1]; 914 u8 reserved_at_f[0x3]; 915 u8 fdb_multi_path_any_table[0x1]; 916 u8 reserved_at_13[0x2]; 917 u8 fdb_modify_header_fwd_to_table[0x1]; 918 u8 fdb_ipv4_ttl_modify[0x1]; 919 u8 flow_source[0x1]; 920 u8 reserved_at_18[0x2]; 921 u8 multi_fdb_encap[0x1]; 922 u8 egress_acl_forward_to_vport[0x1]; 923 u8 fdb_multi_path_to_table[0x1]; 924 u8 reserved_at_1d[0x3]; 925 926 u8 reserved_at_20[0x1e0]; 927 928 struct mlx5_ifc_flow_table_prop_layout_bits flow_table_properties_nic_esw_fdb; 929 930 struct mlx5_ifc_flow_table_prop_layout_bits flow_table_properties_esw_acl_ingress; 931 932 struct mlx5_ifc_flow_table_prop_layout_bits flow_table_properties_esw_acl_egress; 933 934 u8 reserved_at_800[0xC00]; 935 936 struct mlx5_ifc_flow_table_fields_supported_2_bits ft_field_support_2_esw_fdb; 937 938 struct mlx5_ifc_flow_table_fields_supported_2_bits ft_field_bitmask_support_2_esw_fdb; 939 940 u8 reserved_at_1500[0x300]; 941 942 u8 sw_steering_fdb_action_drop_icm_address_rx[0x40]; 943 944 u8 sw_steering_fdb_action_drop_icm_address_tx[0x40]; 945 946 u8 sw_steering_uplink_icm_address_rx[0x40]; 947 948 u8 sw_steering_uplink_icm_address_tx[0x40]; 949 950 u8 reserved_at_1900[0x6700]; 951 }; 952 953 enum { 954 MLX5_COUNTER_SOURCE_ESWITCH = 0x0, 955 MLX5_COUNTER_FLOW_ESWITCH = 0x1, 956 }; 957 958 struct mlx5_ifc_e_switch_cap_bits { 959 u8 vport_svlan_strip[0x1]; 960 u8 vport_cvlan_strip[0x1]; 961 u8 vport_svlan_insert[0x1]; 962 u8 vport_cvlan_insert_if_not_exist[0x1]; 963 u8 vport_cvlan_insert_overwrite[0x1]; 964 u8 reserved_at_5[0x1]; 965 u8 vport_cvlan_insert_always[0x1]; 966 u8 esw_shared_ingress_acl[0x1]; 967 u8 esw_uplink_ingress_acl[0x1]; 968 u8 root_ft_on_other_esw[0x1]; 969 u8 reserved_at_a[0xf]; 970 u8 esw_functions_changed[0x1]; 971 u8 reserved_at_1a[0x1]; 972 u8 ecpf_vport_exists[0x1]; 973 u8 counter_eswitch_affinity[0x1]; 974 u8 merged_eswitch[0x1]; 975 u8 nic_vport_node_guid_modify[0x1]; 976 u8 nic_vport_port_guid_modify[0x1]; 977 978 u8 vxlan_encap_decap[0x1]; 979 u8 nvgre_encap_decap[0x1]; 980 u8 reserved_at_22[0x1]; 981 u8 log_max_fdb_encap_uplink[0x5]; 982 u8 reserved_at_21[0x3]; 983 u8 log_max_packet_reformat_context[0x5]; 984 u8 reserved_2b[0x6]; 985 u8 max_encap_header_size[0xa]; 986 987 u8 reserved_at_40[0xb]; 988 u8 log_max_esw_sf[0x5]; 989 u8 esw_sf_base_id[0x10]; 990 991 u8 reserved_at_60[0x7a0]; 992 993 }; 994 995 struct mlx5_ifc_qos_cap_bits { 996 u8 packet_pacing[0x1]; 997 u8 esw_scheduling[0x1]; 998 u8 esw_bw_share[0x1]; 999 u8 esw_rate_limit[0x1]; 1000 u8 reserved_at_4[0x1]; 1001 u8 packet_pacing_burst_bound[0x1]; 1002 u8 packet_pacing_typical_size[0x1]; 1003 u8 reserved_at_7[0x1]; 1004 u8 nic_sq_scheduling[0x1]; 1005 u8 nic_bw_share[0x1]; 1006 u8 nic_rate_limit[0x1]; 1007 u8 packet_pacing_uid[0x1]; 1008 u8 log_esw_max_sched_depth[0x4]; 1009 u8 reserved_at_10[0x10]; 1010 1011 u8 reserved_at_20[0xb]; 1012 u8 log_max_qos_nic_queue_group[0x5]; 1013 u8 reserved_at_30[0x10]; 1014 1015 u8 packet_pacing_max_rate[0x20]; 1016 1017 u8 packet_pacing_min_rate[0x20]; 1018 1019 u8 reserved_at_80[0x10]; 1020 u8 packet_pacing_rate_table_size[0x10]; 1021 1022 u8 esw_element_type[0x10]; 1023 u8 esw_tsar_type[0x10]; 1024 1025 u8 reserved_at_c0[0x10]; 1026 u8 max_qos_para_vport[0x10]; 1027 1028 u8 max_tsar_bw_share[0x20]; 1029 1030 u8 reserved_at_100[0x20]; 1031 1032 u8 reserved_at_120[0x3]; 1033 u8 log_meter_aso_granularity[0x5]; 1034 u8 reserved_at_128[0x3]; 1035 u8 log_meter_aso_max_alloc[0x5]; 1036 u8 reserved_at_130[0x3]; 1037 u8 log_max_num_meter_aso[0x5]; 1038 u8 reserved_at_138[0x8]; 1039 1040 u8 reserved_at_140[0x6c0]; 1041 }; 1042 1043 struct mlx5_ifc_debug_cap_bits { 1044 u8 core_dump_general[0x1]; 1045 u8 core_dump_qp[0x1]; 1046 u8 reserved_at_2[0x7]; 1047 u8 resource_dump[0x1]; 1048 u8 reserved_at_a[0x16]; 1049 1050 u8 reserved_at_20[0x2]; 1051 u8 stall_detect[0x1]; 1052 u8 reserved_at_23[0x1d]; 1053 1054 u8 reserved_at_40[0x7c0]; 1055 }; 1056 1057 struct mlx5_ifc_per_protocol_networking_offload_caps_bits { 1058 u8 csum_cap[0x1]; 1059 u8 vlan_cap[0x1]; 1060 u8 lro_cap[0x1]; 1061 u8 lro_psh_flag[0x1]; 1062 u8 lro_time_stamp[0x1]; 1063 u8 reserved_at_5[0x2]; 1064 u8 wqe_vlan_insert[0x1]; 1065 u8 self_lb_en_modifiable[0x1]; 1066 u8 reserved_at_9[0x2]; 1067 u8 max_lso_cap[0x5]; 1068 u8 multi_pkt_send_wqe[0x2]; 1069 u8 wqe_inline_mode[0x2]; 1070 u8 rss_ind_tbl_cap[0x4]; 1071 u8 reg_umr_sq[0x1]; 1072 u8 scatter_fcs[0x1]; 1073 u8 enhanced_multi_pkt_send_wqe[0x1]; 1074 u8 tunnel_lso_const_out_ip_id[0x1]; 1075 u8 tunnel_lro_gre[0x1]; 1076 u8 tunnel_lro_vxlan[0x1]; 1077 u8 tunnel_stateless_gre[0x1]; 1078 u8 tunnel_stateless_vxlan[0x1]; 1079 1080 u8 swp[0x1]; 1081 u8 swp_csum[0x1]; 1082 u8 swp_lso[0x1]; 1083 u8 cqe_checksum_full[0x1]; 1084 u8 tunnel_stateless_geneve_tx[0x1]; 1085 u8 tunnel_stateless_mpls_over_udp[0x1]; 1086 u8 tunnel_stateless_mpls_over_gre[0x1]; 1087 u8 tunnel_stateless_vxlan_gpe[0x1]; 1088 u8 tunnel_stateless_ipv4_over_vxlan[0x1]; 1089 u8 tunnel_stateless_ip_over_ip[0x1]; 1090 u8 insert_trailer[0x1]; 1091 u8 reserved_at_2b[0x1]; 1092 u8 tunnel_stateless_ip_over_ip_rx[0x1]; 1093 u8 tunnel_stateless_ip_over_ip_tx[0x1]; 1094 u8 reserved_at_2e[0x2]; 1095 u8 max_vxlan_udp_ports[0x8]; 1096 u8 swp_csum_l4_partial[0x1]; 1097 u8 reserved_at_39[0x5]; 1098 u8 max_geneve_opt_len[0x1]; 1099 u8 tunnel_stateless_geneve_rx[0x1]; 1100 1101 u8 reserved_at_40[0x10]; 1102 u8 lro_min_mss_size[0x10]; 1103 1104 u8 reserved_at_60[0x120]; 1105 1106 u8 lro_timer_supported_periods[4][0x20]; 1107 1108 u8 reserved_at_200[0x600]; 1109 }; 1110 1111 enum { 1112 MLX5_TIMESTAMP_FORMAT_CAP_FREE_RUNNING = 0x0, 1113 MLX5_TIMESTAMP_FORMAT_CAP_REAL_TIME = 0x1, 1114 MLX5_TIMESTAMP_FORMAT_CAP_FREE_RUNNING_AND_REAL_TIME = 0x2, 1115 }; 1116 1117 struct mlx5_ifc_roce_cap_bits { 1118 u8 roce_apm[0x1]; 1119 u8 reserved_at_1[0x3]; 1120 u8 sw_r_roce_src_udp_port[0x1]; 1121 u8 fl_rc_qp_when_roce_disabled[0x1]; 1122 u8 fl_rc_qp_when_roce_enabled[0x1]; 1123 u8 roce_cc_general[0x1]; 1124 u8 qp_ooo_transmit_default[0x1]; 1125 u8 reserved_at_9[0x15]; 1126 u8 qp_ts_format[0x2]; 1127 1128 u8 reserved_at_20[0x60]; 1129 1130 u8 reserved_at_80[0xc]; 1131 u8 l3_type[0x4]; 1132 u8 reserved_at_90[0x8]; 1133 u8 roce_version[0x8]; 1134 1135 u8 reserved_at_a0[0x10]; 1136 u8 r_roce_dest_udp_port[0x10]; 1137 1138 u8 r_roce_max_src_udp_port[0x10]; 1139 u8 r_roce_min_src_udp_port[0x10]; 1140 1141 u8 reserved_at_e0[0x10]; 1142 u8 roce_address_table_size[0x10]; 1143 1144 u8 reserved_at_100[0x700]; 1145 }; 1146 1147 struct mlx5_ifc_sync_steering_in_bits { 1148 u8 opcode[0x10]; 1149 u8 uid[0x10]; 1150 1151 u8 reserved_at_20[0x10]; 1152 u8 op_mod[0x10]; 1153 1154 u8 reserved_at_40[0xc0]; 1155 }; 1156 1157 struct mlx5_ifc_sync_steering_out_bits { 1158 u8 status[0x8]; 1159 u8 reserved_at_8[0x18]; 1160 1161 u8 syndrome[0x20]; 1162 1163 u8 reserved_at_40[0x40]; 1164 }; 1165 1166 struct mlx5_ifc_sync_crypto_in_bits { 1167 u8 opcode[0x10]; 1168 u8 uid[0x10]; 1169 1170 u8 reserved_at_20[0x10]; 1171 u8 op_mod[0x10]; 1172 1173 u8 reserved_at_40[0x20]; 1174 1175 u8 reserved_at_60[0x10]; 1176 u8 crypto_type[0x10]; 1177 1178 u8 reserved_at_80[0x80]; 1179 }; 1180 1181 struct mlx5_ifc_sync_crypto_out_bits { 1182 u8 status[0x8]; 1183 u8 reserved_at_8[0x18]; 1184 1185 u8 syndrome[0x20]; 1186 1187 u8 reserved_at_40[0x40]; 1188 }; 1189 1190 struct mlx5_ifc_device_mem_cap_bits { 1191 u8 memic[0x1]; 1192 u8 reserved_at_1[0x1f]; 1193 1194 u8 reserved_at_20[0xb]; 1195 u8 log_min_memic_alloc_size[0x5]; 1196 u8 reserved_at_30[0x8]; 1197 u8 log_max_memic_addr_alignment[0x8]; 1198 1199 u8 memic_bar_start_addr[0x40]; 1200 1201 u8 memic_bar_size[0x20]; 1202 1203 u8 max_memic_size[0x20]; 1204 1205 u8 steering_sw_icm_start_address[0x40]; 1206 1207 u8 reserved_at_100[0x8]; 1208 u8 log_header_modify_sw_icm_size[0x8]; 1209 u8 reserved_at_110[0x2]; 1210 u8 log_sw_icm_alloc_granularity[0x6]; 1211 u8 log_steering_sw_icm_size[0x8]; 1212 1213 u8 log_indirect_encap_sw_icm_size[0x8]; 1214 u8 reserved_at_128[0x10]; 1215 u8 log_header_modify_pattern_sw_icm_size[0x8]; 1216 1217 u8 header_modify_sw_icm_start_address[0x40]; 1218 1219 u8 reserved_at_180[0x40]; 1220 1221 u8 header_modify_pattern_sw_icm_start_address[0x40]; 1222 1223 u8 memic_operations[0x20]; 1224 1225 u8 reserved_at_220[0x20]; 1226 1227 u8 indirect_encap_sw_icm_start_address[0x40]; 1228 1229 u8 reserved_at_280[0x580]; 1230 }; 1231 1232 struct mlx5_ifc_device_event_cap_bits { 1233 u8 user_affiliated_events[4][0x40]; 1234 1235 u8 user_unaffiliated_events[4][0x40]; 1236 }; 1237 1238 struct mlx5_ifc_virtio_emulation_cap_bits { 1239 u8 desc_tunnel_offload_type[0x1]; 1240 u8 eth_frame_offload_type[0x1]; 1241 u8 virtio_version_1_0[0x1]; 1242 u8 device_features_bits_mask[0xd]; 1243 u8 event_mode[0x8]; 1244 u8 virtio_queue_type[0x8]; 1245 1246 u8 max_tunnel_desc[0x10]; 1247 u8 reserved_at_30[0x3]; 1248 u8 log_doorbell_stride[0x5]; 1249 u8 reserved_at_38[0x3]; 1250 u8 log_doorbell_bar_size[0x5]; 1251 1252 u8 doorbell_bar_offset[0x40]; 1253 1254 u8 max_emulated_devices[0x8]; 1255 u8 max_num_virtio_queues[0x18]; 1256 1257 u8 reserved_at_a0[0x20]; 1258 1259 u8 reserved_at_c0[0x13]; 1260 u8 desc_group_mkey_supported[0x1]; 1261 u8 freeze_to_rdy_supported[0x1]; 1262 u8 reserved_at_d5[0xb]; 1263 1264 u8 reserved_at_e0[0x20]; 1265 1266 u8 umem_1_buffer_param_a[0x20]; 1267 1268 u8 umem_1_buffer_param_b[0x20]; 1269 1270 u8 umem_2_buffer_param_a[0x20]; 1271 1272 u8 umem_2_buffer_param_b[0x20]; 1273 1274 u8 umem_3_buffer_param_a[0x20]; 1275 1276 u8 umem_3_buffer_param_b[0x20]; 1277 1278 u8 reserved_at_1c0[0x640]; 1279 }; 1280 1281 enum { 1282 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_QP_1_BYTE = 0x0, 1283 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_QP_2_BYTES = 0x2, 1284 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_QP_4_BYTES = 0x4, 1285 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_QP_8_BYTES = 0x8, 1286 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_QP_16_BYTES = 0x10, 1287 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_QP_32_BYTES = 0x20, 1288 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_QP_64_BYTES = 0x40, 1289 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_QP_128_BYTES = 0x80, 1290 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_QP_256_BYTES = 0x100, 1291 }; 1292 1293 enum { 1294 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_DC_1_BYTE = 0x1, 1295 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_DC_2_BYTES = 0x2, 1296 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_DC_4_BYTES = 0x4, 1297 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_DC_8_BYTES = 0x8, 1298 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_DC_16_BYTES = 0x10, 1299 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_DC_32_BYTES = 0x20, 1300 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_DC_64_BYTES = 0x40, 1301 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_DC_128_BYTES = 0x80, 1302 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_DC_256_BYTES = 0x100, 1303 }; 1304 1305 struct mlx5_ifc_atomic_caps_bits { 1306 u8 reserved_at_0[0x40]; 1307 1308 u8 atomic_req_8B_endianness_mode[0x2]; 1309 u8 reserved_at_42[0x4]; 1310 u8 supported_atomic_req_8B_endianness_mode_1[0x1]; 1311 1312 u8 reserved_at_47[0x19]; 1313 1314 u8 reserved_at_60[0x20]; 1315 1316 u8 reserved_at_80[0x10]; 1317 u8 atomic_operations[0x10]; 1318 1319 u8 reserved_at_a0[0x10]; 1320 u8 atomic_size_qp[0x10]; 1321 1322 u8 reserved_at_c0[0x10]; 1323 u8 atomic_size_dc[0x10]; 1324 1325 u8 reserved_at_e0[0x720]; 1326 }; 1327 1328 struct mlx5_ifc_odp_cap_bits { 1329 u8 reserved_at_0[0x40]; 1330 1331 u8 sig[0x1]; 1332 u8 reserved_at_41[0x1f]; 1333 1334 u8 reserved_at_60[0x20]; 1335 1336 struct mlx5_ifc_odp_per_transport_service_cap_bits rc_odp_caps; 1337 1338 struct mlx5_ifc_odp_per_transport_service_cap_bits uc_odp_caps; 1339 1340 struct mlx5_ifc_odp_per_transport_service_cap_bits ud_odp_caps; 1341 1342 struct mlx5_ifc_odp_per_transport_service_cap_bits xrc_odp_caps; 1343 1344 struct mlx5_ifc_odp_per_transport_service_cap_bits dc_odp_caps; 1345 1346 u8 reserved_at_120[0x6E0]; 1347 }; 1348 1349 struct mlx5_ifc_tls_cap_bits { 1350 u8 tls_1_2_aes_gcm_128[0x1]; 1351 u8 tls_1_3_aes_gcm_128[0x1]; 1352 u8 tls_1_2_aes_gcm_256[0x1]; 1353 u8 tls_1_3_aes_gcm_256[0x1]; 1354 u8 reserved_at_4[0x1c]; 1355 1356 u8 reserved_at_20[0x7e0]; 1357 }; 1358 1359 struct mlx5_ifc_ipsec_cap_bits { 1360 u8 ipsec_full_offload[0x1]; 1361 u8 ipsec_crypto_offload[0x1]; 1362 u8 ipsec_esn[0x1]; 1363 u8 ipsec_crypto_esp_aes_gcm_256_encrypt[0x1]; 1364 u8 ipsec_crypto_esp_aes_gcm_128_encrypt[0x1]; 1365 u8 ipsec_crypto_esp_aes_gcm_256_decrypt[0x1]; 1366 u8 ipsec_crypto_esp_aes_gcm_128_decrypt[0x1]; 1367 u8 reserved_at_7[0x4]; 1368 u8 log_max_ipsec_offload[0x5]; 1369 u8 reserved_at_10[0x10]; 1370 1371 u8 min_log_ipsec_full_replay_window[0x8]; 1372 u8 max_log_ipsec_full_replay_window[0x8]; 1373 u8 reserved_at_30[0x7d0]; 1374 }; 1375 1376 struct mlx5_ifc_macsec_cap_bits { 1377 u8 macsec_epn[0x1]; 1378 u8 reserved_at_1[0x2]; 1379 u8 macsec_crypto_esp_aes_gcm_256_encrypt[0x1]; 1380 u8 macsec_crypto_esp_aes_gcm_128_encrypt[0x1]; 1381 u8 macsec_crypto_esp_aes_gcm_256_decrypt[0x1]; 1382 u8 macsec_crypto_esp_aes_gcm_128_decrypt[0x1]; 1383 u8 reserved_at_7[0x4]; 1384 u8 log_max_macsec_offload[0x5]; 1385 u8 reserved_at_10[0x10]; 1386 1387 u8 min_log_macsec_full_replay_window[0x8]; 1388 u8 max_log_macsec_full_replay_window[0x8]; 1389 u8 reserved_at_30[0x10]; 1390 1391 u8 reserved_at_40[0x7c0]; 1392 }; 1393 1394 enum { 1395 MLX5_WQ_TYPE_LINKED_LIST = 0x0, 1396 MLX5_WQ_TYPE_CYCLIC = 0x1, 1397 MLX5_WQ_TYPE_LINKED_LIST_STRIDING_RQ = 0x2, 1398 MLX5_WQ_TYPE_CYCLIC_STRIDING_RQ = 0x3, 1399 }; 1400 1401 enum { 1402 MLX5_WQ_END_PAD_MODE_NONE = 0x0, 1403 MLX5_WQ_END_PAD_MODE_ALIGN = 0x1, 1404 }; 1405 1406 enum { 1407 MLX5_CMD_HCA_CAP_GID_TABLE_SIZE_8_GID_ENTRIES = 0x0, 1408 MLX5_CMD_HCA_CAP_GID_TABLE_SIZE_16_GID_ENTRIES = 0x1, 1409 MLX5_CMD_HCA_CAP_GID_TABLE_SIZE_32_GID_ENTRIES = 0x2, 1410 MLX5_CMD_HCA_CAP_GID_TABLE_SIZE_64_GID_ENTRIES = 0x3, 1411 MLX5_CMD_HCA_CAP_GID_TABLE_SIZE_128_GID_ENTRIES = 0x4, 1412 }; 1413 1414 enum { 1415 MLX5_CMD_HCA_CAP_PKEY_TABLE_SIZE_128_ENTRIES = 0x0, 1416 MLX5_CMD_HCA_CAP_PKEY_TABLE_SIZE_256_ENTRIES = 0x1, 1417 MLX5_CMD_HCA_CAP_PKEY_TABLE_SIZE_512_ENTRIES = 0x2, 1418 MLX5_CMD_HCA_CAP_PKEY_TABLE_SIZE_1K_ENTRIES = 0x3, 1419 MLX5_CMD_HCA_CAP_PKEY_TABLE_SIZE_2K_ENTRIES = 0x4, 1420 MLX5_CMD_HCA_CAP_PKEY_TABLE_SIZE_4K_ENTRIES = 0x5, 1421 }; 1422 1423 enum { 1424 MLX5_CMD_HCA_CAP_PORT_TYPE_IB = 0x0, 1425 MLX5_CMD_HCA_CAP_PORT_TYPE_ETHERNET = 0x1, 1426 }; 1427 1428 enum { 1429 MLX5_CMD_HCA_CAP_CMDIF_CHECKSUM_DISABLED = 0x0, 1430 MLX5_CMD_HCA_CAP_CMDIF_CHECKSUM_INITIAL_STATE = 0x1, 1431 MLX5_CMD_HCA_CAP_CMDIF_CHECKSUM_ENABLED = 0x3, 1432 }; 1433 1434 enum { 1435 MLX5_CAP_PORT_TYPE_IB = 0x0, 1436 MLX5_CAP_PORT_TYPE_ETH = 0x1, 1437 }; 1438 1439 enum { 1440 MLX5_CAP_UMR_FENCE_STRONG = 0x0, 1441 MLX5_CAP_UMR_FENCE_SMALL = 0x1, 1442 MLX5_CAP_UMR_FENCE_NONE = 0x2, 1443 }; 1444 1445 enum { 1446 MLX5_FLEX_PARSER_GENEVE_ENABLED = 1 << 3, 1447 MLX5_FLEX_PARSER_MPLS_OVER_GRE_ENABLED = 1 << 4, 1448 MLX5_FLEX_PARSER_MPLS_OVER_UDP_ENABLED = 1 << 5, 1449 MLX5_FLEX_PARSER_VXLAN_GPE_ENABLED = 1 << 7, 1450 MLX5_FLEX_PARSER_ICMP_V4_ENABLED = 1 << 8, 1451 MLX5_FLEX_PARSER_ICMP_V6_ENABLED = 1 << 9, 1452 MLX5_FLEX_PARSER_GENEVE_TLV_OPTION_0_ENABLED = 1 << 10, 1453 MLX5_FLEX_PARSER_GTPU_ENABLED = 1 << 11, 1454 MLX5_FLEX_PARSER_GTPU_DW_2_ENABLED = 1 << 16, 1455 MLX5_FLEX_PARSER_GTPU_FIRST_EXT_DW_0_ENABLED = 1 << 17, 1456 MLX5_FLEX_PARSER_GTPU_DW_0_ENABLED = 1 << 18, 1457 MLX5_FLEX_PARSER_GTPU_TEID_ENABLED = 1 << 19, 1458 }; 1459 1460 enum { 1461 MLX5_UCTX_CAP_RAW_TX = 1UL << 0, 1462 MLX5_UCTX_CAP_INTERNAL_DEV_RES = 1UL << 1, 1463 }; 1464 1465 #define MLX5_FC_BULK_SIZE_FACTOR 128 1466 1467 enum mlx5_fc_bulk_alloc_bitmask { 1468 MLX5_FC_BULK_128 = (1 << 0), 1469 MLX5_FC_BULK_256 = (1 << 1), 1470 MLX5_FC_BULK_512 = (1 << 2), 1471 MLX5_FC_BULK_1024 = (1 << 3), 1472 MLX5_FC_BULK_2048 = (1 << 4), 1473 MLX5_FC_BULK_4096 = (1 << 5), 1474 MLX5_FC_BULK_8192 = (1 << 6), 1475 MLX5_FC_BULK_16384 = (1 << 7), 1476 }; 1477 1478 #define MLX5_FC_BULK_NUM_FCS(fc_enum) (MLX5_FC_BULK_SIZE_FACTOR * (fc_enum)) 1479 1480 #define MLX5_FT_MAX_MULTIPATH_LEVEL 63 1481 1482 enum { 1483 MLX5_STEERING_FORMAT_CONNECTX_5 = 0, 1484 MLX5_STEERING_FORMAT_CONNECTX_6DX = 1, 1485 MLX5_STEERING_FORMAT_CONNECTX_7 = 2, 1486 }; 1487 1488 struct mlx5_ifc_cmd_hca_cap_bits { 1489 u8 reserved_at_0[0x6]; 1490 u8 page_request_disable[0x1]; 1491 u8 reserved_at_7[0x9]; 1492 u8 shared_object_to_user_object_allowed[0x1]; 1493 u8 reserved_at_13[0xe]; 1494 u8 vhca_resource_manager[0x1]; 1495 1496 u8 hca_cap_2[0x1]; 1497 u8 create_lag_when_not_master_up[0x1]; 1498 u8 dtor[0x1]; 1499 u8 event_on_vhca_state_teardown_request[0x1]; 1500 u8 event_on_vhca_state_in_use[0x1]; 1501 u8 event_on_vhca_state_active[0x1]; 1502 u8 event_on_vhca_state_allocated[0x1]; 1503 u8 event_on_vhca_state_invalid[0x1]; 1504 u8 reserved_at_28[0x8]; 1505 u8 vhca_id[0x10]; 1506 1507 u8 reserved_at_40[0x40]; 1508 1509 u8 log_max_srq_sz[0x8]; 1510 u8 log_max_qp_sz[0x8]; 1511 u8 event_cap[0x1]; 1512 u8 reserved_at_91[0x2]; 1513 u8 isolate_vl_tc_new[0x1]; 1514 u8 reserved_at_94[0x4]; 1515 u8 prio_tag_required[0x1]; 1516 u8 reserved_at_99[0x2]; 1517 u8 log_max_qp[0x5]; 1518 1519 u8 reserved_at_a0[0x3]; 1520 u8 ece_support[0x1]; 1521 u8 reserved_at_a4[0x5]; 1522 u8 reg_c_preserve[0x1]; 1523 u8 reserved_at_aa[0x1]; 1524 u8 log_max_srq[0x5]; 1525 u8 reserved_at_b0[0x1]; 1526 u8 uplink_follow[0x1]; 1527 u8 ts_cqe_to_dest_cqn[0x1]; 1528 u8 reserved_at_b3[0x6]; 1529 u8 go_back_n[0x1]; 1530 u8 reserved_at_ba[0x6]; 1531 1532 u8 max_sgl_for_optimized_performance[0x8]; 1533 u8 log_max_cq_sz[0x8]; 1534 u8 relaxed_ordering_write_umr[0x1]; 1535 u8 relaxed_ordering_read_umr[0x1]; 1536 u8 reserved_at_d2[0x7]; 1537 u8 virtio_net_device_emualtion_manager[0x1]; 1538 u8 virtio_blk_device_emualtion_manager[0x1]; 1539 u8 log_max_cq[0x5]; 1540 1541 u8 log_max_eq_sz[0x8]; 1542 u8 relaxed_ordering_write[0x1]; 1543 u8 relaxed_ordering_read_pci_enabled[0x1]; 1544 u8 log_max_mkey[0x6]; 1545 u8 reserved_at_f0[0x6]; 1546 u8 terminate_scatter_list_mkey[0x1]; 1547 u8 repeated_mkey[0x1]; 1548 u8 dump_fill_mkey[0x1]; 1549 u8 reserved_at_f9[0x2]; 1550 u8 fast_teardown[0x1]; 1551 u8 log_max_eq[0x4]; 1552 1553 u8 max_indirection[0x8]; 1554 u8 fixed_buffer_size[0x1]; 1555 u8 log_max_mrw_sz[0x7]; 1556 u8 force_teardown[0x1]; 1557 u8 reserved_at_111[0x1]; 1558 u8 log_max_bsf_list_size[0x6]; 1559 u8 umr_extended_translation_offset[0x1]; 1560 u8 null_mkey[0x1]; 1561 u8 log_max_klm_list_size[0x6]; 1562 1563 u8 reserved_at_120[0x2]; 1564 u8 qpc_extension[0x1]; 1565 u8 reserved_at_123[0x7]; 1566 u8 log_max_ra_req_dc[0x6]; 1567 u8 reserved_at_130[0x2]; 1568 u8 eth_wqe_too_small[0x1]; 1569 u8 reserved_at_133[0x6]; 1570 u8 vnic_env_cq_overrun[0x1]; 1571 u8 log_max_ra_res_dc[0x6]; 1572 1573 u8 reserved_at_140[0x5]; 1574 u8 release_all_pages[0x1]; 1575 u8 must_not_use[0x1]; 1576 u8 reserved_at_147[0x2]; 1577 u8 roce_accl[0x1]; 1578 u8 log_max_ra_req_qp[0x6]; 1579 u8 reserved_at_150[0xa]; 1580 u8 log_max_ra_res_qp[0x6]; 1581 1582 u8 end_pad[0x1]; 1583 u8 cc_query_allowed[0x1]; 1584 u8 cc_modify_allowed[0x1]; 1585 u8 start_pad[0x1]; 1586 u8 cache_line_128byte[0x1]; 1587 u8 reserved_at_165[0x4]; 1588 u8 rts2rts_qp_counters_set_id[0x1]; 1589 u8 reserved_at_16a[0x2]; 1590 u8 vnic_env_int_rq_oob[0x1]; 1591 u8 sbcam_reg[0x1]; 1592 u8 reserved_at_16e[0x1]; 1593 u8 qcam_reg[0x1]; 1594 u8 gid_table_size[0x10]; 1595 1596 u8 out_of_seq_cnt[0x1]; 1597 u8 vport_counters[0x1]; 1598 u8 retransmission_q_counters[0x1]; 1599 u8 debug[0x1]; 1600 u8 modify_rq_counter_set_id[0x1]; 1601 u8 rq_delay_drop[0x1]; 1602 u8 max_qp_cnt[0xa]; 1603 u8 pkey_table_size[0x10]; 1604 1605 u8 vport_group_manager[0x1]; 1606 u8 vhca_group_manager[0x1]; 1607 u8 ib_virt[0x1]; 1608 u8 eth_virt[0x1]; 1609 u8 vnic_env_queue_counters[0x1]; 1610 u8 ets[0x1]; 1611 u8 nic_flow_table[0x1]; 1612 u8 eswitch_manager[0x1]; 1613 u8 device_memory[0x1]; 1614 u8 mcam_reg[0x1]; 1615 u8 pcam_reg[0x1]; 1616 u8 local_ca_ack_delay[0x5]; 1617 u8 port_module_event[0x1]; 1618 u8 enhanced_error_q_counters[0x1]; 1619 u8 ports_check[0x1]; 1620 u8 reserved_at_1b3[0x1]; 1621 u8 disable_link_up[0x1]; 1622 u8 beacon_led[0x1]; 1623 u8 port_type[0x2]; 1624 u8 num_ports[0x8]; 1625 1626 u8 reserved_at_1c0[0x1]; 1627 u8 pps[0x1]; 1628 u8 pps_modify[0x1]; 1629 u8 log_max_msg[0x5]; 1630 u8 reserved_at_1c8[0x4]; 1631 u8 max_tc[0x4]; 1632 u8 temp_warn_event[0x1]; 1633 u8 dcbx[0x1]; 1634 u8 general_notification_event[0x1]; 1635 u8 reserved_at_1d3[0x2]; 1636 u8 fpga[0x1]; 1637 u8 rol_s[0x1]; 1638 u8 rol_g[0x1]; 1639 u8 reserved_at_1d8[0x1]; 1640 u8 wol_s[0x1]; 1641 u8 wol_g[0x1]; 1642 u8 wol_a[0x1]; 1643 u8 wol_b[0x1]; 1644 u8 wol_m[0x1]; 1645 u8 wol_u[0x1]; 1646 u8 wol_p[0x1]; 1647 1648 u8 stat_rate_support[0x10]; 1649 u8 reserved_at_1f0[0x1]; 1650 u8 pci_sync_for_fw_update_event[0x1]; 1651 u8 reserved_at_1f2[0x6]; 1652 u8 init2_lag_tx_port_affinity[0x1]; 1653 u8 reserved_at_1fa[0x3]; 1654 u8 cqe_version[0x4]; 1655 1656 u8 compact_address_vector[0x1]; 1657 u8 striding_rq[0x1]; 1658 u8 reserved_at_202[0x1]; 1659 u8 ipoib_enhanced_offloads[0x1]; 1660 u8 ipoib_basic_offloads[0x1]; 1661 u8 reserved_at_205[0x1]; 1662 u8 repeated_block_disabled[0x1]; 1663 u8 umr_modify_entity_size_disabled[0x1]; 1664 u8 umr_modify_atomic_disabled[0x1]; 1665 u8 umr_indirect_mkey_disabled[0x1]; 1666 u8 umr_fence[0x2]; 1667 u8 dc_req_scat_data_cqe[0x1]; 1668 u8 reserved_at_20d[0x2]; 1669 u8 drain_sigerr[0x1]; 1670 u8 cmdif_checksum[0x2]; 1671 u8 sigerr_cqe[0x1]; 1672 u8 reserved_at_213[0x1]; 1673 u8 wq_signature[0x1]; 1674 u8 sctr_data_cqe[0x1]; 1675 u8 reserved_at_216[0x1]; 1676 u8 sho[0x1]; 1677 u8 tph[0x1]; 1678 u8 rf[0x1]; 1679 u8 dct[0x1]; 1680 u8 qos[0x1]; 1681 u8 eth_net_offloads[0x1]; 1682 u8 roce[0x1]; 1683 u8 atomic[0x1]; 1684 u8 reserved_at_21f[0x1]; 1685 1686 u8 cq_oi[0x1]; 1687 u8 cq_resize[0x1]; 1688 u8 cq_moderation[0x1]; 1689 u8 cq_period_mode_modify[0x1]; 1690 u8 reserved_at_224[0x2]; 1691 u8 cq_eq_remap[0x1]; 1692 u8 pg[0x1]; 1693 u8 block_lb_mc[0x1]; 1694 u8 reserved_at_229[0x1]; 1695 u8 scqe_break_moderation[0x1]; 1696 u8 cq_period_start_from_cqe[0x1]; 1697 u8 cd[0x1]; 1698 u8 reserved_at_22d[0x1]; 1699 u8 apm[0x1]; 1700 u8 vector_calc[0x1]; 1701 u8 umr_ptr_rlky[0x1]; 1702 u8 imaicl[0x1]; 1703 u8 qp_packet_based[0x1]; 1704 u8 reserved_at_233[0x3]; 1705 u8 qkv[0x1]; 1706 u8 pkv[0x1]; 1707 u8 set_deth_sqpn[0x1]; 1708 u8 reserved_at_239[0x3]; 1709 u8 xrc[0x1]; 1710 u8 ud[0x1]; 1711 u8 uc[0x1]; 1712 u8 rc[0x1]; 1713 1714 u8 uar_4k[0x1]; 1715 u8 reserved_at_241[0x7]; 1716 u8 fl_rc_qp_when_roce_disabled[0x1]; 1717 u8 regexp_params[0x1]; 1718 u8 uar_sz[0x6]; 1719 u8 port_selection_cap[0x1]; 1720 u8 reserved_at_251[0x1]; 1721 u8 umem_uid_0[0x1]; 1722 u8 reserved_at_253[0x5]; 1723 u8 log_pg_sz[0x8]; 1724 1725 u8 bf[0x1]; 1726 u8 driver_version[0x1]; 1727 u8 pad_tx_eth_packet[0x1]; 1728 u8 reserved_at_263[0x3]; 1729 u8 mkey_by_name[0x1]; 1730 u8 reserved_at_267[0x4]; 1731 1732 u8 log_bf_reg_size[0x5]; 1733 1734 u8 reserved_at_270[0x3]; 1735 u8 qp_error_syndrome[0x1]; 1736 u8 reserved_at_274[0x2]; 1737 u8 lag_dct[0x2]; 1738 u8 lag_tx_port_affinity[0x1]; 1739 u8 lag_native_fdb_selection[0x1]; 1740 u8 reserved_at_27a[0x1]; 1741 u8 lag_master[0x1]; 1742 u8 num_lag_ports[0x4]; 1743 1744 u8 reserved_at_280[0x10]; 1745 u8 max_wqe_sz_sq[0x10]; 1746 1747 u8 reserved_at_2a0[0xb]; 1748 u8 shampo[0x1]; 1749 u8 reserved_at_2ac[0x4]; 1750 u8 max_wqe_sz_rq[0x10]; 1751 1752 u8 max_flow_counter_31_16[0x10]; 1753 u8 max_wqe_sz_sq_dc[0x10]; 1754 1755 u8 reserved_at_2e0[0x7]; 1756 u8 max_qp_mcg[0x19]; 1757 1758 u8 reserved_at_300[0x10]; 1759 u8 flow_counter_bulk_alloc[0x8]; 1760 u8 log_max_mcg[0x8]; 1761 1762 u8 reserved_at_320[0x3]; 1763 u8 log_max_transport_domain[0x5]; 1764 u8 reserved_at_328[0x2]; 1765 u8 relaxed_ordering_read[0x1]; 1766 u8 log_max_pd[0x5]; 1767 u8 reserved_at_330[0x6]; 1768 u8 pci_sync_for_fw_update_with_driver_unload[0x1]; 1769 u8 vnic_env_cnt_steering_fail[0x1]; 1770 u8 vport_counter_local_loopback[0x1]; 1771 u8 q_counter_aggregation[0x1]; 1772 u8 q_counter_other_vport[0x1]; 1773 u8 log_max_xrcd[0x5]; 1774 1775 u8 nic_receive_steering_discard[0x1]; 1776 u8 receive_discard_vport_down[0x1]; 1777 u8 transmit_discard_vport_down[0x1]; 1778 u8 eq_overrun_count[0x1]; 1779 u8 reserved_at_344[0x1]; 1780 u8 invalid_command_count[0x1]; 1781 u8 quota_exceeded_count[0x1]; 1782 u8 reserved_at_347[0x1]; 1783 u8 log_max_flow_counter_bulk[0x8]; 1784 u8 max_flow_counter_15_0[0x10]; 1785 1786 1787 u8 reserved_at_360[0x3]; 1788 u8 log_max_rq[0x5]; 1789 u8 reserved_at_368[0x3]; 1790 u8 log_max_sq[0x5]; 1791 u8 reserved_at_370[0x3]; 1792 u8 log_max_tir[0x5]; 1793 u8 reserved_at_378[0x3]; 1794 u8 log_max_tis[0x5]; 1795 1796 u8 basic_cyclic_rcv_wqe[0x1]; 1797 u8 reserved_at_381[0x2]; 1798 u8 log_max_rmp[0x5]; 1799 u8 reserved_at_388[0x3]; 1800 u8 log_max_rqt[0x5]; 1801 u8 reserved_at_390[0x3]; 1802 u8 log_max_rqt_size[0x5]; 1803 u8 reserved_at_398[0x3]; 1804 u8 log_max_tis_per_sq[0x5]; 1805 1806 u8 ext_stride_num_range[0x1]; 1807 u8 roce_rw_supported[0x1]; 1808 u8 log_max_current_uc_list_wr_supported[0x1]; 1809 u8 log_max_stride_sz_rq[0x5]; 1810 u8 reserved_at_3a8[0x3]; 1811 u8 log_min_stride_sz_rq[0x5]; 1812 u8 reserved_at_3b0[0x3]; 1813 u8 log_max_stride_sz_sq[0x5]; 1814 u8 reserved_at_3b8[0x3]; 1815 u8 log_min_stride_sz_sq[0x5]; 1816 1817 u8 hairpin[0x1]; 1818 u8 reserved_at_3c1[0x2]; 1819 u8 log_max_hairpin_queues[0x5]; 1820 u8 reserved_at_3c8[0x3]; 1821 u8 log_max_hairpin_wq_data_sz[0x5]; 1822 u8 reserved_at_3d0[0x3]; 1823 u8 log_max_hairpin_num_packets[0x5]; 1824 u8 reserved_at_3d8[0x3]; 1825 u8 log_max_wq_sz[0x5]; 1826 1827 u8 nic_vport_change_event[0x1]; 1828 u8 disable_local_lb_uc[0x1]; 1829 u8 disable_local_lb_mc[0x1]; 1830 u8 log_min_hairpin_wq_data_sz[0x5]; 1831 u8 reserved_at_3e8[0x1]; 1832 u8 silent_mode[0x1]; 1833 u8 vhca_state[0x1]; 1834 u8 log_max_vlan_list[0x5]; 1835 u8 reserved_at_3f0[0x3]; 1836 u8 log_max_current_mc_list[0x5]; 1837 u8 reserved_at_3f8[0x3]; 1838 u8 log_max_current_uc_list[0x5]; 1839 1840 u8 general_obj_types[0x40]; 1841 1842 u8 sq_ts_format[0x2]; 1843 u8 rq_ts_format[0x2]; 1844 u8 steering_format_version[0x4]; 1845 u8 create_qp_start_hint[0x18]; 1846 1847 u8 reserved_at_460[0x1]; 1848 u8 ats[0x1]; 1849 u8 cross_vhca_rqt[0x1]; 1850 u8 log_max_uctx[0x5]; 1851 u8 reserved_at_468[0x1]; 1852 u8 crypto[0x1]; 1853 u8 ipsec_offload[0x1]; 1854 u8 log_max_umem[0x5]; 1855 u8 max_num_eqs[0x10]; 1856 1857 u8 reserved_at_480[0x1]; 1858 u8 tls_tx[0x1]; 1859 u8 tls_rx[0x1]; 1860 u8 log_max_l2_table[0x5]; 1861 u8 reserved_at_488[0x8]; 1862 u8 log_uar_page_sz[0x10]; 1863 1864 u8 reserved_at_4a0[0x20]; 1865 u8 device_frequency_mhz[0x20]; 1866 u8 device_frequency_khz[0x20]; 1867 1868 u8 reserved_at_500[0x20]; 1869 u8 num_of_uars_per_page[0x20]; 1870 1871 u8 flex_parser_protocols[0x20]; 1872 1873 u8 max_geneve_tlv_options[0x8]; 1874 u8 reserved_at_568[0x3]; 1875 u8 max_geneve_tlv_option_data_len[0x5]; 1876 u8 reserved_at_570[0x9]; 1877 u8 adv_virtualization[0x1]; 1878 u8 reserved_at_57a[0x6]; 1879 1880 u8 reserved_at_580[0xb]; 1881 u8 log_max_dci_stream_channels[0x5]; 1882 u8 reserved_at_590[0x3]; 1883 u8 log_max_dci_errored_streams[0x5]; 1884 u8 reserved_at_598[0x8]; 1885 1886 u8 reserved_at_5a0[0x10]; 1887 u8 enhanced_cqe_compression[0x1]; 1888 u8 reserved_at_5b1[0x2]; 1889 u8 log_max_dek[0x5]; 1890 u8 reserved_at_5b8[0x4]; 1891 u8 mini_cqe_resp_stride_index[0x1]; 1892 u8 cqe_128_always[0x1]; 1893 u8 cqe_compression_128[0x1]; 1894 u8 cqe_compression[0x1]; 1895 1896 u8 cqe_compression_timeout[0x10]; 1897 u8 cqe_compression_max_num[0x10]; 1898 1899 u8 reserved_at_5e0[0x8]; 1900 u8 flex_parser_id_gtpu_dw_0[0x4]; 1901 u8 reserved_at_5ec[0x4]; 1902 u8 tag_matching[0x1]; 1903 u8 rndv_offload_rc[0x1]; 1904 u8 rndv_offload_dc[0x1]; 1905 u8 log_tag_matching_list_sz[0x5]; 1906 u8 reserved_at_5f8[0x3]; 1907 u8 log_max_xrq[0x5]; 1908 1909 u8 affiliate_nic_vport_criteria[0x8]; 1910 u8 native_port_num[0x8]; 1911 u8 num_vhca_ports[0x8]; 1912 u8 flex_parser_id_gtpu_teid[0x4]; 1913 u8 reserved_at_61c[0x2]; 1914 u8 sw_owner_id[0x1]; 1915 u8 reserved_at_61f[0x1]; 1916 1917 u8 max_num_of_monitor_counters[0x10]; 1918 u8 num_ppcnt_monitor_counters[0x10]; 1919 1920 u8 max_num_sf[0x10]; 1921 u8 num_q_monitor_counters[0x10]; 1922 1923 u8 reserved_at_660[0x20]; 1924 1925 u8 sf[0x1]; 1926 u8 sf_set_partition[0x1]; 1927 u8 reserved_at_682[0x1]; 1928 u8 log_max_sf[0x5]; 1929 u8 apu[0x1]; 1930 u8 reserved_at_689[0x4]; 1931 u8 migration[0x1]; 1932 u8 reserved_at_68e[0x2]; 1933 u8 log_min_sf_size[0x8]; 1934 u8 max_num_sf_partitions[0x8]; 1935 1936 u8 uctx_cap[0x20]; 1937 1938 u8 reserved_at_6c0[0x4]; 1939 u8 flex_parser_id_geneve_tlv_option_0[0x4]; 1940 u8 flex_parser_id_icmp_dw1[0x4]; 1941 u8 flex_parser_id_icmp_dw0[0x4]; 1942 u8 flex_parser_id_icmpv6_dw1[0x4]; 1943 u8 flex_parser_id_icmpv6_dw0[0x4]; 1944 u8 flex_parser_id_outer_first_mpls_over_gre[0x4]; 1945 u8 flex_parser_id_outer_first_mpls_over_udp_label[0x4]; 1946 1947 u8 max_num_match_definer[0x10]; 1948 u8 sf_base_id[0x10]; 1949 1950 u8 flex_parser_id_gtpu_dw_2[0x4]; 1951 u8 flex_parser_id_gtpu_first_ext_dw_0[0x4]; 1952 u8 num_total_dynamic_vf_msix[0x18]; 1953 u8 reserved_at_720[0x14]; 1954 u8 dynamic_msix_table_size[0xc]; 1955 u8 reserved_at_740[0xc]; 1956 u8 min_dynamic_vf_msix_table_size[0x4]; 1957 u8 reserved_at_750[0x4]; 1958 u8 max_dynamic_vf_msix_table_size[0xc]; 1959 1960 u8 reserved_at_760[0x3]; 1961 u8 log_max_num_header_modify_argument[0x5]; 1962 u8 reserved_at_768[0x4]; 1963 u8 log_header_modify_argument_granularity[0x4]; 1964 u8 reserved_at_770[0x3]; 1965 u8 log_header_modify_argument_max_alloc[0x5]; 1966 u8 reserved_at_778[0x8]; 1967 1968 u8 vhca_tunnel_commands[0x40]; 1969 u8 match_definer_format_supported[0x40]; 1970 }; 1971 1972 enum { 1973 MLX5_CROSS_VHCA_OBJ_TO_OBJ_SUPPORTED_LOCAL_FLOW_TABLE_TO_REMOTE_FLOW_TABLE_MISS = 0x80000, 1974 MLX5_CROSS_VHCA_OBJ_TO_OBJ_SUPPORTED_LOCAL_FLOW_TABLE_ROOT_TO_REMOTE_FLOW_TABLE = (1ULL << 20), 1975 }; 1976 1977 enum { 1978 MLX5_ALLOWED_OBJ_FOR_OTHER_VHCA_ACCESS_FLOW_TABLE = 0x200, 1979 }; 1980 1981 struct mlx5_ifc_cmd_hca_cap_2_bits { 1982 u8 reserved_at_0[0x80]; 1983 1984 u8 migratable[0x1]; 1985 u8 reserved_at_81[0x1f]; 1986 1987 u8 max_reformat_insert_size[0x8]; 1988 u8 max_reformat_insert_offset[0x8]; 1989 u8 max_reformat_remove_size[0x8]; 1990 u8 max_reformat_remove_offset[0x8]; 1991 1992 u8 reserved_at_c0[0x8]; 1993 u8 migration_multi_load[0x1]; 1994 u8 migration_tracking_state[0x1]; 1995 u8 reserved_at_ca[0x6]; 1996 u8 migration_in_chunks[0x1]; 1997 u8 reserved_at_d1[0xf]; 1998 1999 u8 cross_vhca_object_to_object_supported[0x20]; 2000 2001 u8 allowed_object_for_other_vhca_access[0x40]; 2002 2003 u8 reserved_at_140[0x60]; 2004 2005 u8 flow_table_type_2_type[0x8]; 2006 u8 reserved_at_1a8[0x3]; 2007 u8 log_min_mkey_entity_size[0x5]; 2008 u8 reserved_at_1b0[0x10]; 2009 2010 u8 reserved_at_1c0[0x60]; 2011 2012 u8 reserved_at_220[0x1]; 2013 u8 sw_vhca_id_valid[0x1]; 2014 u8 sw_vhca_id[0xe]; 2015 u8 reserved_at_230[0x10]; 2016 2017 u8 reserved_at_240[0xb]; 2018 u8 ts_cqe_metadata_size2wqe_counter[0x5]; 2019 u8 reserved_at_250[0x10]; 2020 2021 u8 reserved_at_260[0x120]; 2022 u8 reserved_at_380[0xb]; 2023 u8 min_mkey_log_entity_size_fixed_buffer[0x5]; 2024 u8 ec_vf_vport_base[0x10]; 2025 2026 u8 reserved_at_3a0[0x10]; 2027 u8 max_rqt_vhca_id[0x10]; 2028 2029 u8 reserved_at_3c0[0x20]; 2030 2031 u8 reserved_at_3e0[0x10]; 2032 u8 pcc_ifa2[0x1]; 2033 u8 reserved_at_3f1[0xf]; 2034 2035 u8 reserved_at_400[0x1]; 2036 u8 min_mkey_log_entity_size_fixed_buffer_valid[0x1]; 2037 u8 reserved_at_402[0x1e]; 2038 2039 u8 reserved_at_420[0x20]; 2040 2041 u8 reserved_at_440[0x8]; 2042 u8 max_num_eqs_24b[0x18]; 2043 u8 reserved_at_460[0x3a0]; 2044 }; 2045 2046 enum mlx5_ifc_flow_destination_type { 2047 MLX5_IFC_FLOW_DESTINATION_TYPE_VPORT = 0x0, 2048 MLX5_IFC_FLOW_DESTINATION_TYPE_FLOW_TABLE = 0x1, 2049 MLX5_IFC_FLOW_DESTINATION_TYPE_TIR = 0x2, 2050 MLX5_IFC_FLOW_DESTINATION_TYPE_FLOW_SAMPLER = 0x6, 2051 MLX5_IFC_FLOW_DESTINATION_TYPE_UPLINK = 0x8, 2052 MLX5_IFC_FLOW_DESTINATION_TYPE_TABLE_TYPE = 0xA, 2053 }; 2054 2055 enum mlx5_flow_table_miss_action { 2056 MLX5_FLOW_TABLE_MISS_ACTION_DEF, 2057 MLX5_FLOW_TABLE_MISS_ACTION_FWD, 2058 MLX5_FLOW_TABLE_MISS_ACTION_SWITCH_DOMAIN, 2059 }; 2060 2061 struct mlx5_ifc_dest_format_struct_bits { 2062 u8 destination_type[0x8]; 2063 u8 destination_id[0x18]; 2064 2065 u8 destination_eswitch_owner_vhca_id_valid[0x1]; 2066 u8 packet_reformat[0x1]; 2067 u8 reserved_at_22[0x6]; 2068 u8 destination_table_type[0x8]; 2069 u8 destination_eswitch_owner_vhca_id[0x10]; 2070 }; 2071 2072 struct mlx5_ifc_flow_counter_list_bits { 2073 u8 flow_counter_id[0x20]; 2074 2075 u8 reserved_at_20[0x20]; 2076 }; 2077 2078 struct mlx5_ifc_extended_dest_format_bits { 2079 struct mlx5_ifc_dest_format_struct_bits destination_entry; 2080 2081 u8 packet_reformat_id[0x20]; 2082 2083 u8 reserved_at_60[0x20]; 2084 }; 2085 2086 union mlx5_ifc_dest_format_struct_flow_counter_list_auto_bits { 2087 struct mlx5_ifc_extended_dest_format_bits extended_dest_format; 2088 struct mlx5_ifc_flow_counter_list_bits flow_counter_list; 2089 }; 2090 2091 struct mlx5_ifc_fte_match_param_bits { 2092 struct mlx5_ifc_fte_match_set_lyr_2_4_bits outer_headers; 2093 2094 struct mlx5_ifc_fte_match_set_misc_bits misc_parameters; 2095 2096 struct mlx5_ifc_fte_match_set_lyr_2_4_bits inner_headers; 2097 2098 struct mlx5_ifc_fte_match_set_misc2_bits misc_parameters_2; 2099 2100 struct mlx5_ifc_fte_match_set_misc3_bits misc_parameters_3; 2101 2102 struct mlx5_ifc_fte_match_set_misc4_bits misc_parameters_4; 2103 2104 struct mlx5_ifc_fte_match_set_misc5_bits misc_parameters_5; 2105 2106 u8 reserved_at_e00[0x200]; 2107 }; 2108 2109 enum { 2110 MLX5_RX_HASH_FIELD_SELECT_SELECTED_FIELDS_SRC_IP = 0x0, 2111 MLX5_RX_HASH_FIELD_SELECT_SELECTED_FIELDS_DST_IP = 0x1, 2112 MLX5_RX_HASH_FIELD_SELECT_SELECTED_FIELDS_L4_SPORT = 0x2, 2113 MLX5_RX_HASH_FIELD_SELECT_SELECTED_FIELDS_L4_DPORT = 0x3, 2114 MLX5_RX_HASH_FIELD_SELECT_SELECTED_FIELDS_IPSEC_SPI = 0x4, 2115 }; 2116 2117 struct mlx5_ifc_rx_hash_field_select_bits { 2118 u8 l3_prot_type[0x1]; 2119 u8 l4_prot_type[0x1]; 2120 u8 selected_fields[0x1e]; 2121 }; 2122 2123 enum { 2124 MLX5_WQ_WQ_TYPE_WQ_LINKED_LIST = 0x0, 2125 MLX5_WQ_WQ_TYPE_WQ_CYCLIC = 0x1, 2126 }; 2127 2128 enum { 2129 MLX5_WQ_END_PADDING_MODE_END_PAD_NONE = 0x0, 2130 MLX5_WQ_END_PADDING_MODE_END_PAD_ALIGN = 0x1, 2131 }; 2132 2133 struct mlx5_ifc_wq_bits { 2134 u8 wq_type[0x4]; 2135 u8 wq_signature[0x1]; 2136 u8 end_padding_mode[0x2]; 2137 u8 cd_slave[0x1]; 2138 u8 reserved_at_8[0x18]; 2139 2140 u8 hds_skip_first_sge[0x1]; 2141 u8 log2_hds_buf_size[0x3]; 2142 u8 reserved_at_24[0x7]; 2143 u8 page_offset[0x5]; 2144 u8 lwm[0x10]; 2145 2146 u8 reserved_at_40[0x8]; 2147 u8 pd[0x18]; 2148 2149 u8 reserved_at_60[0x8]; 2150 u8 uar_page[0x18]; 2151 2152 u8 dbr_addr[0x40]; 2153 2154 u8 hw_counter[0x20]; 2155 2156 u8 sw_counter[0x20]; 2157 2158 u8 reserved_at_100[0xc]; 2159 u8 log_wq_stride[0x4]; 2160 u8 reserved_at_110[0x3]; 2161 u8 log_wq_pg_sz[0x5]; 2162 u8 reserved_at_118[0x3]; 2163 u8 log_wq_sz[0x5]; 2164 2165 u8 dbr_umem_valid[0x1]; 2166 u8 wq_umem_valid[0x1]; 2167 u8 reserved_at_122[0x1]; 2168 u8 log_hairpin_num_packets[0x5]; 2169 u8 reserved_at_128[0x3]; 2170 u8 log_hairpin_data_sz[0x5]; 2171 2172 u8 reserved_at_130[0x4]; 2173 u8 log_wqe_num_of_strides[0x4]; 2174 u8 two_byte_shift_en[0x1]; 2175 u8 reserved_at_139[0x4]; 2176 u8 log_wqe_stride_size[0x3]; 2177 2178 u8 reserved_at_140[0x80]; 2179 2180 u8 headers_mkey[0x20]; 2181 2182 u8 shampo_enable[0x1]; 2183 u8 reserved_at_1e1[0x4]; 2184 u8 log_reservation_size[0x3]; 2185 u8 reserved_at_1e8[0x5]; 2186 u8 log_max_num_of_packets_per_reservation[0x3]; 2187 u8 reserved_at_1f0[0x6]; 2188 u8 log_headers_entry_size[0x2]; 2189 u8 reserved_at_1f8[0x4]; 2190 u8 log_headers_buffer_entry_num[0x4]; 2191 2192 u8 reserved_at_200[0x400]; 2193 2194 struct mlx5_ifc_cmd_pas_bits pas[]; 2195 }; 2196 2197 struct mlx5_ifc_rq_num_bits { 2198 u8 reserved_at_0[0x8]; 2199 u8 rq_num[0x18]; 2200 }; 2201 2202 struct mlx5_ifc_rq_vhca_bits { 2203 u8 reserved_at_0[0x8]; 2204 u8 rq_num[0x18]; 2205 u8 reserved_at_20[0x10]; 2206 u8 rq_vhca_id[0x10]; 2207 }; 2208 2209 struct mlx5_ifc_mac_address_layout_bits { 2210 u8 reserved_at_0[0x10]; 2211 u8 mac_addr_47_32[0x10]; 2212 2213 u8 mac_addr_31_0[0x20]; 2214 }; 2215 2216 struct mlx5_ifc_vlan_layout_bits { 2217 u8 reserved_at_0[0x14]; 2218 u8 vlan[0x0c]; 2219 2220 u8 reserved_at_20[0x20]; 2221 }; 2222 2223 struct mlx5_ifc_cong_control_r_roce_ecn_np_bits { 2224 u8 reserved_at_0[0xa0]; 2225 2226 u8 min_time_between_cnps[0x20]; 2227 2228 u8 reserved_at_c0[0x12]; 2229 u8 cnp_dscp[0x6]; 2230 u8 reserved_at_d8[0x4]; 2231 u8 cnp_prio_mode[0x1]; 2232 u8 cnp_802p_prio[0x3]; 2233 2234 u8 reserved_at_e0[0x720]; 2235 }; 2236 2237 struct mlx5_ifc_cong_control_r_roce_ecn_rp_bits { 2238 u8 reserved_at_0[0x60]; 2239 2240 u8 reserved_at_60[0x4]; 2241 u8 clamp_tgt_rate[0x1]; 2242 u8 reserved_at_65[0x3]; 2243 u8 clamp_tgt_rate_after_time_inc[0x1]; 2244 u8 reserved_at_69[0x17]; 2245 2246 u8 reserved_at_80[0x20]; 2247 2248 u8 rpg_time_reset[0x20]; 2249 2250 u8 rpg_byte_reset[0x20]; 2251 2252 u8 rpg_threshold[0x20]; 2253 2254 u8 rpg_max_rate[0x20]; 2255 2256 u8 rpg_ai_rate[0x20]; 2257 2258 u8 rpg_hai_rate[0x20]; 2259 2260 u8 rpg_gd[0x20]; 2261 2262 u8 rpg_min_dec_fac[0x20]; 2263 2264 u8 rpg_min_rate[0x20]; 2265 2266 u8 reserved_at_1c0[0xe0]; 2267 2268 u8 rate_to_set_on_first_cnp[0x20]; 2269 2270 u8 dce_tcp_g[0x20]; 2271 2272 u8 dce_tcp_rtt[0x20]; 2273 2274 u8 rate_reduce_monitor_period[0x20]; 2275 2276 u8 reserved_at_320[0x20]; 2277 2278 u8 initial_alpha_value[0x20]; 2279 2280 u8 reserved_at_360[0x4a0]; 2281 }; 2282 2283 struct mlx5_ifc_cong_control_r_roce_general_bits { 2284 u8 reserved_at_0[0x80]; 2285 2286 u8 reserved_at_80[0x10]; 2287 u8 rtt_resp_dscp_valid[0x1]; 2288 u8 reserved_at_91[0x9]; 2289 u8 rtt_resp_dscp[0x6]; 2290 2291 u8 reserved_at_a0[0x760]; 2292 }; 2293 2294 struct mlx5_ifc_cong_control_802_1qau_rp_bits { 2295 u8 reserved_at_0[0x80]; 2296 2297 u8 rppp_max_rps[0x20]; 2298 2299 u8 rpg_time_reset[0x20]; 2300 2301 u8 rpg_byte_reset[0x20]; 2302 2303 u8 rpg_threshold[0x20]; 2304 2305 u8 rpg_max_rate[0x20]; 2306 2307 u8 rpg_ai_rate[0x20]; 2308 2309 u8 rpg_hai_rate[0x20]; 2310 2311 u8 rpg_gd[0x20]; 2312 2313 u8 rpg_min_dec_fac[0x20]; 2314 2315 u8 rpg_min_rate[0x20]; 2316 2317 u8 reserved_at_1c0[0x640]; 2318 }; 2319 2320 enum { 2321 MLX5_RESIZE_FIELD_SELECT_RESIZE_FIELD_SELECT_LOG_CQ_SIZE = 0x1, 2322 MLX5_RESIZE_FIELD_SELECT_RESIZE_FIELD_SELECT_PAGE_OFFSET = 0x2, 2323 MLX5_RESIZE_FIELD_SELECT_RESIZE_FIELD_SELECT_LOG_PAGE_SIZE = 0x4, 2324 }; 2325 2326 struct mlx5_ifc_resize_field_select_bits { 2327 u8 resize_field_select[0x20]; 2328 }; 2329 2330 struct mlx5_ifc_resource_dump_bits { 2331 u8 more_dump[0x1]; 2332 u8 inline_dump[0x1]; 2333 u8 reserved_at_2[0xa]; 2334 u8 seq_num[0x4]; 2335 u8 segment_type[0x10]; 2336 2337 u8 reserved_at_20[0x10]; 2338 u8 vhca_id[0x10]; 2339 2340 u8 index1[0x20]; 2341 2342 u8 index2[0x20]; 2343 2344 u8 num_of_obj1[0x10]; 2345 u8 num_of_obj2[0x10]; 2346 2347 u8 reserved_at_a0[0x20]; 2348 2349 u8 device_opaque[0x40]; 2350 2351 u8 mkey[0x20]; 2352 2353 u8 size[0x20]; 2354 2355 u8 address[0x40]; 2356 2357 u8 inline_data[52][0x20]; 2358 }; 2359 2360 struct mlx5_ifc_resource_dump_menu_record_bits { 2361 u8 reserved_at_0[0x4]; 2362 u8 num_of_obj2_supports_active[0x1]; 2363 u8 num_of_obj2_supports_all[0x1]; 2364 u8 must_have_num_of_obj2[0x1]; 2365 u8 support_num_of_obj2[0x1]; 2366 u8 num_of_obj1_supports_active[0x1]; 2367 u8 num_of_obj1_supports_all[0x1]; 2368 u8 must_have_num_of_obj1[0x1]; 2369 u8 support_num_of_obj1[0x1]; 2370 u8 must_have_index2[0x1]; 2371 u8 support_index2[0x1]; 2372 u8 must_have_index1[0x1]; 2373 u8 support_index1[0x1]; 2374 u8 segment_type[0x10]; 2375 2376 u8 segment_name[4][0x20]; 2377 2378 u8 index1_name[4][0x20]; 2379 2380 u8 index2_name[4][0x20]; 2381 }; 2382 2383 struct mlx5_ifc_resource_dump_segment_header_bits { 2384 u8 length_dw[0x10]; 2385 u8 segment_type[0x10]; 2386 }; 2387 2388 struct mlx5_ifc_resource_dump_command_segment_bits { 2389 struct mlx5_ifc_resource_dump_segment_header_bits segment_header; 2390 2391 u8 segment_called[0x10]; 2392 u8 vhca_id[0x10]; 2393 2394 u8 index1[0x20]; 2395 2396 u8 index2[0x20]; 2397 2398 u8 num_of_obj1[0x10]; 2399 u8 num_of_obj2[0x10]; 2400 }; 2401 2402 struct mlx5_ifc_resource_dump_error_segment_bits { 2403 struct mlx5_ifc_resource_dump_segment_header_bits segment_header; 2404 2405 u8 reserved_at_20[0x10]; 2406 u8 syndrome_id[0x10]; 2407 2408 u8 reserved_at_40[0x40]; 2409 2410 u8 error[8][0x20]; 2411 }; 2412 2413 struct mlx5_ifc_resource_dump_info_segment_bits { 2414 struct mlx5_ifc_resource_dump_segment_header_bits segment_header; 2415 2416 u8 reserved_at_20[0x18]; 2417 u8 dump_version[0x8]; 2418 2419 u8 hw_version[0x20]; 2420 2421 u8 fw_version[0x20]; 2422 }; 2423 2424 struct mlx5_ifc_resource_dump_menu_segment_bits { 2425 struct mlx5_ifc_resource_dump_segment_header_bits segment_header; 2426 2427 u8 reserved_at_20[0x10]; 2428 u8 num_of_records[0x10]; 2429 2430 struct mlx5_ifc_resource_dump_menu_record_bits record[]; 2431 }; 2432 2433 struct mlx5_ifc_resource_dump_resource_segment_bits { 2434 struct mlx5_ifc_resource_dump_segment_header_bits segment_header; 2435 2436 u8 reserved_at_20[0x20]; 2437 2438 u8 index1[0x20]; 2439 2440 u8 index2[0x20]; 2441 2442 u8 payload[][0x20]; 2443 }; 2444 2445 struct mlx5_ifc_resource_dump_terminate_segment_bits { 2446 struct mlx5_ifc_resource_dump_segment_header_bits segment_header; 2447 }; 2448 2449 struct mlx5_ifc_menu_resource_dump_response_bits { 2450 struct mlx5_ifc_resource_dump_info_segment_bits info; 2451 struct mlx5_ifc_resource_dump_command_segment_bits cmd; 2452 struct mlx5_ifc_resource_dump_menu_segment_bits menu; 2453 struct mlx5_ifc_resource_dump_terminate_segment_bits terminate; 2454 }; 2455 2456 enum { 2457 MLX5_MODIFY_FIELD_SELECT_MODIFY_FIELD_SELECT_CQ_PERIOD = 0x1, 2458 MLX5_MODIFY_FIELD_SELECT_MODIFY_FIELD_SELECT_CQ_MAX_COUNT = 0x2, 2459 MLX5_MODIFY_FIELD_SELECT_MODIFY_FIELD_SELECT_OI = 0x4, 2460 MLX5_MODIFY_FIELD_SELECT_MODIFY_FIELD_SELECT_C_EQN = 0x8, 2461 }; 2462 2463 struct mlx5_ifc_modify_field_select_bits { 2464 u8 modify_field_select[0x20]; 2465 }; 2466 2467 struct mlx5_ifc_field_select_r_roce_np_bits { 2468 u8 field_select_r_roce_np[0x20]; 2469 }; 2470 2471 struct mlx5_ifc_field_select_r_roce_rp_bits { 2472 u8 field_select_r_roce_rp[0x20]; 2473 }; 2474 2475 enum { 2476 MLX5_FIELD_SELECT_802_1QAU_RP_FIELD_SELECT_8021QAURP_RPPP_MAX_RPS = 0x4, 2477 MLX5_FIELD_SELECT_802_1QAU_RP_FIELD_SELECT_8021QAURP_RPG_TIME_RESET = 0x8, 2478 MLX5_FIELD_SELECT_802_1QAU_RP_FIELD_SELECT_8021QAURP_RPG_BYTE_RESET = 0x10, 2479 MLX5_FIELD_SELECT_802_1QAU_RP_FIELD_SELECT_8021QAURP_RPG_THRESHOLD = 0x20, 2480 MLX5_FIELD_SELECT_802_1QAU_RP_FIELD_SELECT_8021QAURP_RPG_MAX_RATE = 0x40, 2481 MLX5_FIELD_SELECT_802_1QAU_RP_FIELD_SELECT_8021QAURP_RPG_AI_RATE = 0x80, 2482 MLX5_FIELD_SELECT_802_1QAU_RP_FIELD_SELECT_8021QAURP_RPG_HAI_RATE = 0x100, 2483 MLX5_FIELD_SELECT_802_1QAU_RP_FIELD_SELECT_8021QAURP_RPG_GD = 0x200, 2484 MLX5_FIELD_SELECT_802_1QAU_RP_FIELD_SELECT_8021QAURP_RPG_MIN_DEC_FAC = 0x400, 2485 MLX5_FIELD_SELECT_802_1QAU_RP_FIELD_SELECT_8021QAURP_RPG_MIN_RATE = 0x800, 2486 }; 2487 2488 struct mlx5_ifc_field_select_802_1qau_rp_bits { 2489 u8 field_select_8021qaurp[0x20]; 2490 }; 2491 2492 struct mlx5_ifc_phys_layer_cntrs_bits { 2493 u8 time_since_last_clear_high[0x20]; 2494 2495 u8 time_since_last_clear_low[0x20]; 2496 2497 u8 symbol_errors_high[0x20]; 2498 2499 u8 symbol_errors_low[0x20]; 2500 2501 u8 sync_headers_errors_high[0x20]; 2502 2503 u8 sync_headers_errors_low[0x20]; 2504 2505 u8 edpl_bip_errors_lane0_high[0x20]; 2506 2507 u8 edpl_bip_errors_lane0_low[0x20]; 2508 2509 u8 edpl_bip_errors_lane1_high[0x20]; 2510 2511 u8 edpl_bip_errors_lane1_low[0x20]; 2512 2513 u8 edpl_bip_errors_lane2_high[0x20]; 2514 2515 u8 edpl_bip_errors_lane2_low[0x20]; 2516 2517 u8 edpl_bip_errors_lane3_high[0x20]; 2518 2519 u8 edpl_bip_errors_lane3_low[0x20]; 2520 2521 u8 fc_fec_corrected_blocks_lane0_high[0x20]; 2522 2523 u8 fc_fec_corrected_blocks_lane0_low[0x20]; 2524 2525 u8 fc_fec_corrected_blocks_lane1_high[0x20]; 2526 2527 u8 fc_fec_corrected_blocks_lane1_low[0x20]; 2528 2529 u8 fc_fec_corrected_blocks_lane2_high[0x20]; 2530 2531 u8 fc_fec_corrected_blocks_lane2_low[0x20]; 2532 2533 u8 fc_fec_corrected_blocks_lane3_high[0x20]; 2534 2535 u8 fc_fec_corrected_blocks_lane3_low[0x20]; 2536 2537 u8 fc_fec_uncorrectable_blocks_lane0_high[0x20]; 2538 2539 u8 fc_fec_uncorrectable_blocks_lane0_low[0x20]; 2540 2541 u8 fc_fec_uncorrectable_blocks_lane1_high[0x20]; 2542 2543 u8 fc_fec_uncorrectable_blocks_lane1_low[0x20]; 2544 2545 u8 fc_fec_uncorrectable_blocks_lane2_high[0x20]; 2546 2547 u8 fc_fec_uncorrectable_blocks_lane2_low[0x20]; 2548 2549 u8 fc_fec_uncorrectable_blocks_lane3_high[0x20]; 2550 2551 u8 fc_fec_uncorrectable_blocks_lane3_low[0x20]; 2552 2553 u8 rs_fec_corrected_blocks_high[0x20]; 2554 2555 u8 rs_fec_corrected_blocks_low[0x20]; 2556 2557 u8 rs_fec_uncorrectable_blocks_high[0x20]; 2558 2559 u8 rs_fec_uncorrectable_blocks_low[0x20]; 2560 2561 u8 rs_fec_no_errors_blocks_high[0x20]; 2562 2563 u8 rs_fec_no_errors_blocks_low[0x20]; 2564 2565 u8 rs_fec_single_error_blocks_high[0x20]; 2566 2567 u8 rs_fec_single_error_blocks_low[0x20]; 2568 2569 u8 rs_fec_corrected_symbols_total_high[0x20]; 2570 2571 u8 rs_fec_corrected_symbols_total_low[0x20]; 2572 2573 u8 rs_fec_corrected_symbols_lane0_high[0x20]; 2574 2575 u8 rs_fec_corrected_symbols_lane0_low[0x20]; 2576 2577 u8 rs_fec_corrected_symbols_lane1_high[0x20]; 2578 2579 u8 rs_fec_corrected_symbols_lane1_low[0x20]; 2580 2581 u8 rs_fec_corrected_symbols_lane2_high[0x20]; 2582 2583 u8 rs_fec_corrected_symbols_lane2_low[0x20]; 2584 2585 u8 rs_fec_corrected_symbols_lane3_high[0x20]; 2586 2587 u8 rs_fec_corrected_symbols_lane3_low[0x20]; 2588 2589 u8 link_down_events[0x20]; 2590 2591 u8 successful_recovery_events[0x20]; 2592 2593 u8 reserved_at_640[0x180]; 2594 }; 2595 2596 struct mlx5_ifc_phys_layer_statistical_cntrs_bits { 2597 u8 time_since_last_clear_high[0x20]; 2598 2599 u8 time_since_last_clear_low[0x20]; 2600 2601 u8 phy_received_bits_high[0x20]; 2602 2603 u8 phy_received_bits_low[0x20]; 2604 2605 u8 phy_symbol_errors_high[0x20]; 2606 2607 u8 phy_symbol_errors_low[0x20]; 2608 2609 u8 phy_corrected_bits_high[0x20]; 2610 2611 u8 phy_corrected_bits_low[0x20]; 2612 2613 u8 phy_corrected_bits_lane0_high[0x20]; 2614 2615 u8 phy_corrected_bits_lane0_low[0x20]; 2616 2617 u8 phy_corrected_bits_lane1_high[0x20]; 2618 2619 u8 phy_corrected_bits_lane1_low[0x20]; 2620 2621 u8 phy_corrected_bits_lane2_high[0x20]; 2622 2623 u8 phy_corrected_bits_lane2_low[0x20]; 2624 2625 u8 phy_corrected_bits_lane3_high[0x20]; 2626 2627 u8 phy_corrected_bits_lane3_low[0x20]; 2628 2629 u8 reserved_at_200[0x5c0]; 2630 }; 2631 2632 struct mlx5_ifc_ib_port_cntrs_grp_data_layout_bits { 2633 u8 symbol_error_counter[0x10]; 2634 2635 u8 link_error_recovery_counter[0x8]; 2636 2637 u8 link_downed_counter[0x8]; 2638 2639 u8 port_rcv_errors[0x10]; 2640 2641 u8 port_rcv_remote_physical_errors[0x10]; 2642 2643 u8 port_rcv_switch_relay_errors[0x10]; 2644 2645 u8 port_xmit_discards[0x10]; 2646 2647 u8 port_xmit_constraint_errors[0x8]; 2648 2649 u8 port_rcv_constraint_errors[0x8]; 2650 2651 u8 reserved_at_70[0x8]; 2652 2653 u8 link_overrun_errors[0x8]; 2654 2655 u8 reserved_at_80[0x10]; 2656 2657 u8 vl_15_dropped[0x10]; 2658 2659 u8 reserved_at_a0[0x80]; 2660 2661 u8 port_xmit_wait[0x20]; 2662 }; 2663 2664 struct mlx5_ifc_eth_per_tc_prio_grp_data_layout_bits { 2665 u8 transmit_queue_high[0x20]; 2666 2667 u8 transmit_queue_low[0x20]; 2668 2669 u8 no_buffer_discard_uc_high[0x20]; 2670 2671 u8 no_buffer_discard_uc_low[0x20]; 2672 2673 u8 reserved_at_80[0x740]; 2674 }; 2675 2676 struct mlx5_ifc_eth_per_tc_congest_prio_grp_data_layout_bits { 2677 u8 wred_discard_high[0x20]; 2678 2679 u8 wred_discard_low[0x20]; 2680 2681 u8 ecn_marked_tc_high[0x20]; 2682 2683 u8 ecn_marked_tc_low[0x20]; 2684 2685 u8 reserved_at_80[0x740]; 2686 }; 2687 2688 struct mlx5_ifc_eth_per_prio_grp_data_layout_bits { 2689 u8 rx_octets_high[0x20]; 2690 2691 u8 rx_octets_low[0x20]; 2692 2693 u8 reserved_at_40[0xc0]; 2694 2695 u8 rx_frames_high[0x20]; 2696 2697 u8 rx_frames_low[0x20]; 2698 2699 u8 tx_octets_high[0x20]; 2700 2701 u8 tx_octets_low[0x20]; 2702 2703 u8 reserved_at_180[0xc0]; 2704 2705 u8 tx_frames_high[0x20]; 2706 2707 u8 tx_frames_low[0x20]; 2708 2709 u8 rx_pause_high[0x20]; 2710 2711 u8 rx_pause_low[0x20]; 2712 2713 u8 rx_pause_duration_high[0x20]; 2714 2715 u8 rx_pause_duration_low[0x20]; 2716 2717 u8 tx_pause_high[0x20]; 2718 2719 u8 tx_pause_low[0x20]; 2720 2721 u8 tx_pause_duration_high[0x20]; 2722 2723 u8 tx_pause_duration_low[0x20]; 2724 2725 u8 rx_pause_transition_high[0x20]; 2726 2727 u8 rx_pause_transition_low[0x20]; 2728 2729 u8 rx_discards_high[0x20]; 2730 2731 u8 rx_discards_low[0x20]; 2732 2733 u8 device_stall_minor_watermark_cnt_high[0x20]; 2734 2735 u8 device_stall_minor_watermark_cnt_low[0x20]; 2736 2737 u8 device_stall_critical_watermark_cnt_high[0x20]; 2738 2739 u8 device_stall_critical_watermark_cnt_low[0x20]; 2740 2741 u8 reserved_at_480[0x340]; 2742 }; 2743 2744 struct mlx5_ifc_eth_extended_cntrs_grp_data_layout_bits { 2745 u8 port_transmit_wait_high[0x20]; 2746 2747 u8 port_transmit_wait_low[0x20]; 2748 2749 u8 reserved_at_40[0x100]; 2750 2751 u8 rx_buffer_almost_full_high[0x20]; 2752 2753 u8 rx_buffer_almost_full_low[0x20]; 2754 2755 u8 rx_buffer_full_high[0x20]; 2756 2757 u8 rx_buffer_full_low[0x20]; 2758 2759 u8 rx_icrc_encapsulated_high[0x20]; 2760 2761 u8 rx_icrc_encapsulated_low[0x20]; 2762 2763 u8 reserved_at_200[0x5c0]; 2764 }; 2765 2766 struct mlx5_ifc_eth_3635_cntrs_grp_data_layout_bits { 2767 u8 dot3stats_alignment_errors_high[0x20]; 2768 2769 u8 dot3stats_alignment_errors_low[0x20]; 2770 2771 u8 dot3stats_fcs_errors_high[0x20]; 2772 2773 u8 dot3stats_fcs_errors_low[0x20]; 2774 2775 u8 dot3stats_single_collision_frames_high[0x20]; 2776 2777 u8 dot3stats_single_collision_frames_low[0x20]; 2778 2779 u8 dot3stats_multiple_collision_frames_high[0x20]; 2780 2781 u8 dot3stats_multiple_collision_frames_low[0x20]; 2782 2783 u8 dot3stats_sqe_test_errors_high[0x20]; 2784 2785 u8 dot3stats_sqe_test_errors_low[0x20]; 2786 2787 u8 dot3stats_deferred_transmissions_high[0x20]; 2788 2789 u8 dot3stats_deferred_transmissions_low[0x20]; 2790 2791 u8 dot3stats_late_collisions_high[0x20]; 2792 2793 u8 dot3stats_late_collisions_low[0x20]; 2794 2795 u8 dot3stats_excessive_collisions_high[0x20]; 2796 2797 u8 dot3stats_excessive_collisions_low[0x20]; 2798 2799 u8 dot3stats_internal_mac_transmit_errors_high[0x20]; 2800 2801 u8 dot3stats_internal_mac_transmit_errors_low[0x20]; 2802 2803 u8 dot3stats_carrier_sense_errors_high[0x20]; 2804 2805 u8 dot3stats_carrier_sense_errors_low[0x20]; 2806 2807 u8 dot3stats_frame_too_longs_high[0x20]; 2808 2809 u8 dot3stats_frame_too_longs_low[0x20]; 2810 2811 u8 dot3stats_internal_mac_receive_errors_high[0x20]; 2812 2813 u8 dot3stats_internal_mac_receive_errors_low[0x20]; 2814 2815 u8 dot3stats_symbol_errors_high[0x20]; 2816 2817 u8 dot3stats_symbol_errors_low[0x20]; 2818 2819 u8 dot3control_in_unknown_opcodes_high[0x20]; 2820 2821 u8 dot3control_in_unknown_opcodes_low[0x20]; 2822 2823 u8 dot3in_pause_frames_high[0x20]; 2824 2825 u8 dot3in_pause_frames_low[0x20]; 2826 2827 u8 dot3out_pause_frames_high[0x20]; 2828 2829 u8 dot3out_pause_frames_low[0x20]; 2830 2831 u8 reserved_at_400[0x3c0]; 2832 }; 2833 2834 struct mlx5_ifc_eth_2819_cntrs_grp_data_layout_bits { 2835 u8 ether_stats_drop_events_high[0x20]; 2836 2837 u8 ether_stats_drop_events_low[0x20]; 2838 2839 u8 ether_stats_octets_high[0x20]; 2840 2841 u8 ether_stats_octets_low[0x20]; 2842 2843 u8 ether_stats_pkts_high[0x20]; 2844 2845 u8 ether_stats_pkts_low[0x20]; 2846 2847 u8 ether_stats_broadcast_pkts_high[0x20]; 2848 2849 u8 ether_stats_broadcast_pkts_low[0x20]; 2850 2851 u8 ether_stats_multicast_pkts_high[0x20]; 2852 2853 u8 ether_stats_multicast_pkts_low[0x20]; 2854 2855 u8 ether_stats_crc_align_errors_high[0x20]; 2856 2857 u8 ether_stats_crc_align_errors_low[0x20]; 2858 2859 u8 ether_stats_undersize_pkts_high[0x20]; 2860 2861 u8 ether_stats_undersize_pkts_low[0x20]; 2862 2863 u8 ether_stats_oversize_pkts_high[0x20]; 2864 2865 u8 ether_stats_oversize_pkts_low[0x20]; 2866 2867 u8 ether_stats_fragments_high[0x20]; 2868 2869 u8 ether_stats_fragments_low[0x20]; 2870 2871 u8 ether_stats_jabbers_high[0x20]; 2872 2873 u8 ether_stats_jabbers_low[0x20]; 2874 2875 u8 ether_stats_collisions_high[0x20]; 2876 2877 u8 ether_stats_collisions_low[0x20]; 2878 2879 u8 ether_stats_pkts64octets_high[0x20]; 2880 2881 u8 ether_stats_pkts64octets_low[0x20]; 2882 2883 u8 ether_stats_pkts65to127octets_high[0x20]; 2884 2885 u8 ether_stats_pkts65to127octets_low[0x20]; 2886 2887 u8 ether_stats_pkts128to255octets_high[0x20]; 2888 2889 u8 ether_stats_pkts128to255octets_low[0x20]; 2890 2891 u8 ether_stats_pkts256to511octets_high[0x20]; 2892 2893 u8 ether_stats_pkts256to511octets_low[0x20]; 2894 2895 u8 ether_stats_pkts512to1023octets_high[0x20]; 2896 2897 u8 ether_stats_pkts512to1023octets_low[0x20]; 2898 2899 u8 ether_stats_pkts1024to1518octets_high[0x20]; 2900 2901 u8 ether_stats_pkts1024to1518octets_low[0x20]; 2902 2903 u8 ether_stats_pkts1519to2047octets_high[0x20]; 2904 2905 u8 ether_stats_pkts1519to2047octets_low[0x20]; 2906 2907 u8 ether_stats_pkts2048to4095octets_high[0x20]; 2908 2909 u8 ether_stats_pkts2048to4095octets_low[0x20]; 2910 2911 u8 ether_stats_pkts4096to8191octets_high[0x20]; 2912 2913 u8 ether_stats_pkts4096to8191octets_low[0x20]; 2914 2915 u8 ether_stats_pkts8192to10239octets_high[0x20]; 2916 2917 u8 ether_stats_pkts8192to10239octets_low[0x20]; 2918 2919 u8 reserved_at_540[0x280]; 2920 }; 2921 2922 struct mlx5_ifc_eth_2863_cntrs_grp_data_layout_bits { 2923 u8 if_in_octets_high[0x20]; 2924 2925 u8 if_in_octets_low[0x20]; 2926 2927 u8 if_in_ucast_pkts_high[0x20]; 2928 2929 u8 if_in_ucast_pkts_low[0x20]; 2930 2931 u8 if_in_discards_high[0x20]; 2932 2933 u8 if_in_discards_low[0x20]; 2934 2935 u8 if_in_errors_high[0x20]; 2936 2937 u8 if_in_errors_low[0x20]; 2938 2939 u8 if_in_unknown_protos_high[0x20]; 2940 2941 u8 if_in_unknown_protos_low[0x20]; 2942 2943 u8 if_out_octets_high[0x20]; 2944 2945 u8 if_out_octets_low[0x20]; 2946 2947 u8 if_out_ucast_pkts_high[0x20]; 2948 2949 u8 if_out_ucast_pkts_low[0x20]; 2950 2951 u8 if_out_discards_high[0x20]; 2952 2953 u8 if_out_discards_low[0x20]; 2954 2955 u8 if_out_errors_high[0x20]; 2956 2957 u8 if_out_errors_low[0x20]; 2958 2959 u8 if_in_multicast_pkts_high[0x20]; 2960 2961 u8 if_in_multicast_pkts_low[0x20]; 2962 2963 u8 if_in_broadcast_pkts_high[0x20]; 2964 2965 u8 if_in_broadcast_pkts_low[0x20]; 2966 2967 u8 if_out_multicast_pkts_high[0x20]; 2968 2969 u8 if_out_multicast_pkts_low[0x20]; 2970 2971 u8 if_out_broadcast_pkts_high[0x20]; 2972 2973 u8 if_out_broadcast_pkts_low[0x20]; 2974 2975 u8 reserved_at_340[0x480]; 2976 }; 2977 2978 struct mlx5_ifc_eth_802_3_cntrs_grp_data_layout_bits { 2979 u8 a_frames_transmitted_ok_high[0x20]; 2980 2981 u8 a_frames_transmitted_ok_low[0x20]; 2982 2983 u8 a_frames_received_ok_high[0x20]; 2984 2985 u8 a_frames_received_ok_low[0x20]; 2986 2987 u8 a_frame_check_sequence_errors_high[0x20]; 2988 2989 u8 a_frame_check_sequence_errors_low[0x20]; 2990 2991 u8 a_alignment_errors_high[0x20]; 2992 2993 u8 a_alignment_errors_low[0x20]; 2994 2995 u8 a_octets_transmitted_ok_high[0x20]; 2996 2997 u8 a_octets_transmitted_ok_low[0x20]; 2998 2999 u8 a_octets_received_ok_high[0x20]; 3000 3001 u8 a_octets_received_ok_low[0x20]; 3002 3003 u8 a_multicast_frames_xmitted_ok_high[0x20]; 3004 3005 u8 a_multicast_frames_xmitted_ok_low[0x20]; 3006 3007 u8 a_broadcast_frames_xmitted_ok_high[0x20]; 3008 3009 u8 a_broadcast_frames_xmitted_ok_low[0x20]; 3010 3011 u8 a_multicast_frames_received_ok_high[0x20]; 3012 3013 u8 a_multicast_frames_received_ok_low[0x20]; 3014 3015 u8 a_broadcast_frames_received_ok_high[0x20]; 3016 3017 u8 a_broadcast_frames_received_ok_low[0x20]; 3018 3019 u8 a_in_range_length_errors_high[0x20]; 3020 3021 u8 a_in_range_length_errors_low[0x20]; 3022 3023 u8 a_out_of_range_length_field_high[0x20]; 3024 3025 u8 a_out_of_range_length_field_low[0x20]; 3026 3027 u8 a_frame_too_long_errors_high[0x20]; 3028 3029 u8 a_frame_too_long_errors_low[0x20]; 3030 3031 u8 a_symbol_error_during_carrier_high[0x20]; 3032 3033 u8 a_symbol_error_during_carrier_low[0x20]; 3034 3035 u8 a_mac_control_frames_transmitted_high[0x20]; 3036 3037 u8 a_mac_control_frames_transmitted_low[0x20]; 3038 3039 u8 a_mac_control_frames_received_high[0x20]; 3040 3041 u8 a_mac_control_frames_received_low[0x20]; 3042 3043 u8 a_unsupported_opcodes_received_high[0x20]; 3044 3045 u8 a_unsupported_opcodes_received_low[0x20]; 3046 3047 u8 a_pause_mac_ctrl_frames_received_high[0x20]; 3048 3049 u8 a_pause_mac_ctrl_frames_received_low[0x20]; 3050 3051 u8 a_pause_mac_ctrl_frames_transmitted_high[0x20]; 3052 3053 u8 a_pause_mac_ctrl_frames_transmitted_low[0x20]; 3054 3055 u8 reserved_at_4c0[0x300]; 3056 }; 3057 3058 struct mlx5_ifc_pcie_perf_cntrs_grp_data_layout_bits { 3059 u8 life_time_counter_high[0x20]; 3060 3061 u8 life_time_counter_low[0x20]; 3062 3063 u8 rx_errors[0x20]; 3064 3065 u8 tx_errors[0x20]; 3066 3067 u8 l0_to_recovery_eieos[0x20]; 3068 3069 u8 l0_to_recovery_ts[0x20]; 3070 3071 u8 l0_to_recovery_framing[0x20]; 3072 3073 u8 l0_to_recovery_retrain[0x20]; 3074 3075 u8 crc_error_dllp[0x20]; 3076 3077 u8 crc_error_tlp[0x20]; 3078 3079 u8 tx_overflow_buffer_pkt_high[0x20]; 3080 3081 u8 tx_overflow_buffer_pkt_low[0x20]; 3082 3083 u8 outbound_stalled_reads[0x20]; 3084 3085 u8 outbound_stalled_writes[0x20]; 3086 3087 u8 outbound_stalled_reads_events[0x20]; 3088 3089 u8 outbound_stalled_writes_events[0x20]; 3090 3091 u8 reserved_at_200[0x5c0]; 3092 }; 3093 3094 struct mlx5_ifc_cmd_inter_comp_event_bits { 3095 u8 command_completion_vector[0x20]; 3096 3097 u8 reserved_at_20[0xc0]; 3098 }; 3099 3100 struct mlx5_ifc_stall_vl_event_bits { 3101 u8 reserved_at_0[0x18]; 3102 u8 port_num[0x1]; 3103 u8 reserved_at_19[0x3]; 3104 u8 vl[0x4]; 3105 3106 u8 reserved_at_20[0xa0]; 3107 }; 3108 3109 struct mlx5_ifc_db_bf_congestion_event_bits { 3110 u8 event_subtype[0x8]; 3111 u8 reserved_at_8[0x8]; 3112 u8 congestion_level[0x8]; 3113 u8 reserved_at_18[0x8]; 3114 3115 u8 reserved_at_20[0xa0]; 3116 }; 3117 3118 struct mlx5_ifc_gpio_event_bits { 3119 u8 reserved_at_0[0x60]; 3120 3121 u8 gpio_event_hi[0x20]; 3122 3123 u8 gpio_event_lo[0x20]; 3124 3125 u8 reserved_at_a0[0x40]; 3126 }; 3127 3128 struct mlx5_ifc_port_state_change_event_bits { 3129 u8 reserved_at_0[0x40]; 3130 3131 u8 port_num[0x4]; 3132 u8 reserved_at_44[0x1c]; 3133 3134 u8 reserved_at_60[0x80]; 3135 }; 3136 3137 struct mlx5_ifc_dropped_packet_logged_bits { 3138 u8 reserved_at_0[0xe0]; 3139 }; 3140 3141 struct mlx5_ifc_default_timeout_bits { 3142 u8 to_multiplier[0x3]; 3143 u8 reserved_at_3[0x9]; 3144 u8 to_value[0x14]; 3145 }; 3146 3147 struct mlx5_ifc_dtor_reg_bits { 3148 u8 reserved_at_0[0x20]; 3149 3150 struct mlx5_ifc_default_timeout_bits pcie_toggle_to; 3151 3152 u8 reserved_at_40[0x60]; 3153 3154 struct mlx5_ifc_default_timeout_bits health_poll_to; 3155 3156 struct mlx5_ifc_default_timeout_bits full_crdump_to; 3157 3158 struct mlx5_ifc_default_timeout_bits fw_reset_to; 3159 3160 struct mlx5_ifc_default_timeout_bits flush_on_err_to; 3161 3162 struct mlx5_ifc_default_timeout_bits pci_sync_update_to; 3163 3164 struct mlx5_ifc_default_timeout_bits tear_down_to; 3165 3166 struct mlx5_ifc_default_timeout_bits fsm_reactivate_to; 3167 3168 struct mlx5_ifc_default_timeout_bits reclaim_pages_to; 3169 3170 struct mlx5_ifc_default_timeout_bits reclaim_vfs_pages_to; 3171 3172 struct mlx5_ifc_default_timeout_bits reset_unload_to; 3173 3174 u8 reserved_at_1c0[0x20]; 3175 }; 3176 3177 enum { 3178 MLX5_CQ_ERROR_SYNDROME_CQ_OVERRUN = 0x1, 3179 MLX5_CQ_ERROR_SYNDROME_CQ_ACCESS_VIOLATION_ERROR = 0x2, 3180 }; 3181 3182 struct mlx5_ifc_cq_error_bits { 3183 u8 reserved_at_0[0x8]; 3184 u8 cqn[0x18]; 3185 3186 u8 reserved_at_20[0x20]; 3187 3188 u8 reserved_at_40[0x18]; 3189 u8 syndrome[0x8]; 3190 3191 u8 reserved_at_60[0x80]; 3192 }; 3193 3194 struct mlx5_ifc_rdma_page_fault_event_bits { 3195 u8 bytes_committed[0x20]; 3196 3197 u8 r_key[0x20]; 3198 3199 u8 reserved_at_40[0x10]; 3200 u8 packet_len[0x10]; 3201 3202 u8 rdma_op_len[0x20]; 3203 3204 u8 rdma_va[0x40]; 3205 3206 u8 reserved_at_c0[0x5]; 3207 u8 rdma[0x1]; 3208 u8 write[0x1]; 3209 u8 requestor[0x1]; 3210 u8 qp_number[0x18]; 3211 }; 3212 3213 struct mlx5_ifc_wqe_associated_page_fault_event_bits { 3214 u8 bytes_committed[0x20]; 3215 3216 u8 reserved_at_20[0x10]; 3217 u8 wqe_index[0x10]; 3218 3219 u8 reserved_at_40[0x10]; 3220 u8 len[0x10]; 3221 3222 u8 reserved_at_60[0x60]; 3223 3224 u8 reserved_at_c0[0x5]; 3225 u8 rdma[0x1]; 3226 u8 write_read[0x1]; 3227 u8 requestor[0x1]; 3228 u8 qpn[0x18]; 3229 }; 3230 3231 struct mlx5_ifc_qp_events_bits { 3232 u8 reserved_at_0[0xa0]; 3233 3234 u8 type[0x8]; 3235 u8 reserved_at_a8[0x18]; 3236 3237 u8 reserved_at_c0[0x8]; 3238 u8 qpn_rqn_sqn[0x18]; 3239 }; 3240 3241 struct mlx5_ifc_dct_events_bits { 3242 u8 reserved_at_0[0xc0]; 3243 3244 u8 reserved_at_c0[0x8]; 3245 u8 dct_number[0x18]; 3246 }; 3247 3248 struct mlx5_ifc_comp_event_bits { 3249 u8 reserved_at_0[0xc0]; 3250 3251 u8 reserved_at_c0[0x8]; 3252 u8 cq_number[0x18]; 3253 }; 3254 3255 enum { 3256 MLX5_QPC_STATE_RST = 0x0, 3257 MLX5_QPC_STATE_INIT = 0x1, 3258 MLX5_QPC_STATE_RTR = 0x2, 3259 MLX5_QPC_STATE_RTS = 0x3, 3260 MLX5_QPC_STATE_SQER = 0x4, 3261 MLX5_QPC_STATE_ERR = 0x6, 3262 MLX5_QPC_STATE_SQD = 0x7, 3263 MLX5_QPC_STATE_SUSPENDED = 0x9, 3264 }; 3265 3266 enum { 3267 MLX5_QPC_ST_RC = 0x0, 3268 MLX5_QPC_ST_UC = 0x1, 3269 MLX5_QPC_ST_UD = 0x2, 3270 MLX5_QPC_ST_XRC = 0x3, 3271 MLX5_QPC_ST_DCI = 0x5, 3272 MLX5_QPC_ST_QP0 = 0x7, 3273 MLX5_QPC_ST_QP1 = 0x8, 3274 MLX5_QPC_ST_RAW_DATAGRAM = 0x9, 3275 MLX5_QPC_ST_REG_UMR = 0xc, 3276 }; 3277 3278 enum { 3279 MLX5_QPC_PM_STATE_ARMED = 0x0, 3280 MLX5_QPC_PM_STATE_REARM = 0x1, 3281 MLX5_QPC_PM_STATE_RESERVED = 0x2, 3282 MLX5_QPC_PM_STATE_MIGRATED = 0x3, 3283 }; 3284 3285 enum { 3286 MLX5_QPC_OFFLOAD_TYPE_RNDV = 0x1, 3287 }; 3288 3289 enum { 3290 MLX5_QPC_END_PADDING_MODE_SCATTER_AS_IS = 0x0, 3291 MLX5_QPC_END_PADDING_MODE_PAD_TO_CACHE_LINE_ALIGNMENT = 0x1, 3292 }; 3293 3294 enum { 3295 MLX5_QPC_MTU_256_BYTES = 0x1, 3296 MLX5_QPC_MTU_512_BYTES = 0x2, 3297 MLX5_QPC_MTU_1K_BYTES = 0x3, 3298 MLX5_QPC_MTU_2K_BYTES = 0x4, 3299 MLX5_QPC_MTU_4K_BYTES = 0x5, 3300 MLX5_QPC_MTU_RAW_ETHERNET_QP = 0x7, 3301 }; 3302 3303 enum { 3304 MLX5_QPC_ATOMIC_MODE_IB_SPEC = 0x1, 3305 MLX5_QPC_ATOMIC_MODE_ONLY_8B = 0x2, 3306 MLX5_QPC_ATOMIC_MODE_UP_TO_8B = 0x3, 3307 MLX5_QPC_ATOMIC_MODE_UP_TO_16B = 0x4, 3308 MLX5_QPC_ATOMIC_MODE_UP_TO_32B = 0x5, 3309 MLX5_QPC_ATOMIC_MODE_UP_TO_64B = 0x6, 3310 MLX5_QPC_ATOMIC_MODE_UP_TO_128B = 0x7, 3311 MLX5_QPC_ATOMIC_MODE_UP_TO_256B = 0x8, 3312 }; 3313 3314 enum { 3315 MLX5_QPC_CS_REQ_DISABLE = 0x0, 3316 MLX5_QPC_CS_REQ_UP_TO_32B = 0x11, 3317 MLX5_QPC_CS_REQ_UP_TO_64B = 0x22, 3318 }; 3319 3320 enum { 3321 MLX5_QPC_CS_RES_DISABLE = 0x0, 3322 MLX5_QPC_CS_RES_UP_TO_32B = 0x1, 3323 MLX5_QPC_CS_RES_UP_TO_64B = 0x2, 3324 }; 3325 3326 enum { 3327 MLX5_TIMESTAMP_FORMAT_FREE_RUNNING = 0x0, 3328 MLX5_TIMESTAMP_FORMAT_DEFAULT = 0x1, 3329 MLX5_TIMESTAMP_FORMAT_REAL_TIME = 0x2, 3330 }; 3331 3332 struct mlx5_ifc_qpc_bits { 3333 u8 state[0x4]; 3334 u8 lag_tx_port_affinity[0x4]; 3335 u8 st[0x8]; 3336 u8 reserved_at_10[0x2]; 3337 u8 isolate_vl_tc[0x1]; 3338 u8 pm_state[0x2]; 3339 u8 reserved_at_15[0x1]; 3340 u8 req_e2e_credit_mode[0x2]; 3341 u8 offload_type[0x4]; 3342 u8 end_padding_mode[0x2]; 3343 u8 reserved_at_1e[0x2]; 3344 3345 u8 wq_signature[0x1]; 3346 u8 block_lb_mc[0x1]; 3347 u8 atomic_like_write_en[0x1]; 3348 u8 latency_sensitive[0x1]; 3349 u8 reserved_at_24[0x1]; 3350 u8 drain_sigerr[0x1]; 3351 u8 reserved_at_26[0x2]; 3352 u8 pd[0x18]; 3353 3354 u8 mtu[0x3]; 3355 u8 log_msg_max[0x5]; 3356 u8 reserved_at_48[0x1]; 3357 u8 log_rq_size[0x4]; 3358 u8 log_rq_stride[0x3]; 3359 u8 no_sq[0x1]; 3360 u8 log_sq_size[0x4]; 3361 u8 reserved_at_55[0x1]; 3362 u8 retry_mode[0x2]; 3363 u8 ts_format[0x2]; 3364 u8 reserved_at_5a[0x1]; 3365 u8 rlky[0x1]; 3366 u8 ulp_stateless_offload_mode[0x4]; 3367 3368 u8 counter_set_id[0x8]; 3369 u8 uar_page[0x18]; 3370 3371 u8 reserved_at_80[0x8]; 3372 u8 user_index[0x18]; 3373 3374 u8 reserved_at_a0[0x3]; 3375 u8 log_page_size[0x5]; 3376 u8 remote_qpn[0x18]; 3377 3378 struct mlx5_ifc_ads_bits primary_address_path; 3379 3380 struct mlx5_ifc_ads_bits secondary_address_path; 3381 3382 u8 log_ack_req_freq[0x4]; 3383 u8 reserved_at_384[0x4]; 3384 u8 log_sra_max[0x3]; 3385 u8 reserved_at_38b[0x2]; 3386 u8 retry_count[0x3]; 3387 u8 rnr_retry[0x3]; 3388 u8 reserved_at_393[0x1]; 3389 u8 fre[0x1]; 3390 u8 cur_rnr_retry[0x3]; 3391 u8 cur_retry_count[0x3]; 3392 u8 reserved_at_39b[0x5]; 3393 3394 u8 reserved_at_3a0[0x20]; 3395 3396 u8 reserved_at_3c0[0x8]; 3397 u8 next_send_psn[0x18]; 3398 3399 u8 reserved_at_3e0[0x3]; 3400 u8 log_num_dci_stream_channels[0x5]; 3401 u8 cqn_snd[0x18]; 3402 3403 u8 reserved_at_400[0x3]; 3404 u8 log_num_dci_errored_streams[0x5]; 3405 u8 deth_sqpn[0x18]; 3406 3407 u8 reserved_at_420[0x20]; 3408 3409 u8 reserved_at_440[0x8]; 3410 u8 last_acked_psn[0x18]; 3411 3412 u8 reserved_at_460[0x8]; 3413 u8 ssn[0x18]; 3414 3415 u8 reserved_at_480[0x8]; 3416 u8 log_rra_max[0x3]; 3417 u8 reserved_at_48b[0x1]; 3418 u8 atomic_mode[0x4]; 3419 u8 rre[0x1]; 3420 u8 rwe[0x1]; 3421 u8 rae[0x1]; 3422 u8 reserved_at_493[0x1]; 3423 u8 page_offset[0x6]; 3424 u8 reserved_at_49a[0x3]; 3425 u8 cd_slave_receive[0x1]; 3426 u8 cd_slave_send[0x1]; 3427 u8 cd_master[0x1]; 3428 3429 u8 reserved_at_4a0[0x3]; 3430 u8 min_rnr_nak[0x5]; 3431 u8 next_rcv_psn[0x18]; 3432 3433 u8 reserved_at_4c0[0x8]; 3434 u8 xrcd[0x18]; 3435 3436 u8 reserved_at_4e0[0x8]; 3437 u8 cqn_rcv[0x18]; 3438 3439 u8 dbr_addr[0x40]; 3440 3441 u8 q_key[0x20]; 3442 3443 u8 reserved_at_560[0x5]; 3444 u8 rq_type[0x3]; 3445 u8 srqn_rmpn_xrqn[0x18]; 3446 3447 u8 reserved_at_580[0x8]; 3448 u8 rmsn[0x18]; 3449 3450 u8 hw_sq_wqebb_counter[0x10]; 3451 u8 sw_sq_wqebb_counter[0x10]; 3452 3453 u8 hw_rq_counter[0x20]; 3454 3455 u8 sw_rq_counter[0x20]; 3456 3457 u8 reserved_at_600[0x20]; 3458 3459 u8 reserved_at_620[0xf]; 3460 u8 cgs[0x1]; 3461 u8 cs_req[0x8]; 3462 u8 cs_res[0x8]; 3463 3464 u8 dc_access_key[0x40]; 3465 3466 u8 reserved_at_680[0x3]; 3467 u8 dbr_umem_valid[0x1]; 3468 3469 u8 reserved_at_684[0xbc]; 3470 }; 3471 3472 struct mlx5_ifc_roce_addr_layout_bits { 3473 u8 source_l3_address[16][0x8]; 3474 3475 u8 reserved_at_80[0x3]; 3476 u8 vlan_valid[0x1]; 3477 u8 vlan_id[0xc]; 3478 u8 source_mac_47_32[0x10]; 3479 3480 u8 source_mac_31_0[0x20]; 3481 3482 u8 reserved_at_c0[0x14]; 3483 u8 roce_l3_type[0x4]; 3484 u8 roce_version[0x8]; 3485 3486 u8 reserved_at_e0[0x20]; 3487 }; 3488 3489 struct mlx5_ifc_crypto_cap_bits { 3490 u8 reserved_at_0[0x3]; 3491 u8 synchronize_dek[0x1]; 3492 u8 int_kek_manual[0x1]; 3493 u8 int_kek_auto[0x1]; 3494 u8 reserved_at_6[0x1a]; 3495 3496 u8 reserved_at_20[0x3]; 3497 u8 log_dek_max_alloc[0x5]; 3498 u8 reserved_at_28[0x3]; 3499 u8 log_max_num_deks[0x5]; 3500 u8 reserved_at_30[0x10]; 3501 3502 u8 reserved_at_40[0x20]; 3503 3504 u8 reserved_at_60[0x3]; 3505 u8 log_dek_granularity[0x5]; 3506 u8 reserved_at_68[0x3]; 3507 u8 log_max_num_int_kek[0x5]; 3508 u8 sw_wrapped_dek[0x10]; 3509 3510 u8 reserved_at_80[0x780]; 3511 }; 3512 3513 union mlx5_ifc_hca_cap_union_bits { 3514 struct mlx5_ifc_cmd_hca_cap_bits cmd_hca_cap; 3515 struct mlx5_ifc_cmd_hca_cap_2_bits cmd_hca_cap_2; 3516 struct mlx5_ifc_odp_cap_bits odp_cap; 3517 struct mlx5_ifc_atomic_caps_bits atomic_caps; 3518 struct mlx5_ifc_roce_cap_bits roce_cap; 3519 struct mlx5_ifc_per_protocol_networking_offload_caps_bits per_protocol_networking_offload_caps; 3520 struct mlx5_ifc_flow_table_nic_cap_bits flow_table_nic_cap; 3521 struct mlx5_ifc_flow_table_eswitch_cap_bits flow_table_eswitch_cap; 3522 struct mlx5_ifc_e_switch_cap_bits e_switch_cap; 3523 struct mlx5_ifc_port_selection_cap_bits port_selection_cap; 3524 struct mlx5_ifc_qos_cap_bits qos_cap; 3525 struct mlx5_ifc_debug_cap_bits debug_cap; 3526 struct mlx5_ifc_fpga_cap_bits fpga_cap; 3527 struct mlx5_ifc_tls_cap_bits tls_cap; 3528 struct mlx5_ifc_device_mem_cap_bits device_mem_cap; 3529 struct mlx5_ifc_virtio_emulation_cap_bits virtio_emulation_cap; 3530 struct mlx5_ifc_macsec_cap_bits macsec_cap; 3531 struct mlx5_ifc_crypto_cap_bits crypto_cap; 3532 struct mlx5_ifc_ipsec_cap_bits ipsec_cap; 3533 u8 reserved_at_0[0x8000]; 3534 }; 3535 3536 enum { 3537 MLX5_FLOW_CONTEXT_ACTION_ALLOW = 0x1, 3538 MLX5_FLOW_CONTEXT_ACTION_DROP = 0x2, 3539 MLX5_FLOW_CONTEXT_ACTION_FWD_DEST = 0x4, 3540 MLX5_FLOW_CONTEXT_ACTION_COUNT = 0x8, 3541 MLX5_FLOW_CONTEXT_ACTION_PACKET_REFORMAT = 0x10, 3542 MLX5_FLOW_CONTEXT_ACTION_DECAP = 0x20, 3543 MLX5_FLOW_CONTEXT_ACTION_MOD_HDR = 0x40, 3544 MLX5_FLOW_CONTEXT_ACTION_VLAN_POP = 0x80, 3545 MLX5_FLOW_CONTEXT_ACTION_VLAN_PUSH = 0x100, 3546 MLX5_FLOW_CONTEXT_ACTION_VLAN_POP_2 = 0x400, 3547 MLX5_FLOW_CONTEXT_ACTION_VLAN_PUSH_2 = 0x800, 3548 MLX5_FLOW_CONTEXT_ACTION_CRYPTO_DECRYPT = 0x1000, 3549 MLX5_FLOW_CONTEXT_ACTION_CRYPTO_ENCRYPT = 0x2000, 3550 MLX5_FLOW_CONTEXT_ACTION_EXECUTE_ASO = 0x4000, 3551 }; 3552 3553 enum { 3554 MLX5_FLOW_CONTEXT_FLOW_SOURCE_ANY_VPORT = 0x0, 3555 MLX5_FLOW_CONTEXT_FLOW_SOURCE_UPLINK = 0x1, 3556 MLX5_FLOW_CONTEXT_FLOW_SOURCE_LOCAL_VPORT = 0x2, 3557 }; 3558 3559 enum { 3560 MLX5_FLOW_CONTEXT_ENCRYPT_DECRYPT_TYPE_IPSEC = 0x0, 3561 MLX5_FLOW_CONTEXT_ENCRYPT_DECRYPT_TYPE_MACSEC = 0x1, 3562 }; 3563 3564 struct mlx5_ifc_vlan_bits { 3565 u8 ethtype[0x10]; 3566 u8 prio[0x3]; 3567 u8 cfi[0x1]; 3568 u8 vid[0xc]; 3569 }; 3570 3571 enum { 3572 MLX5_FLOW_METER_COLOR_RED = 0x0, 3573 MLX5_FLOW_METER_COLOR_YELLOW = 0x1, 3574 MLX5_FLOW_METER_COLOR_GREEN = 0x2, 3575 MLX5_FLOW_METER_COLOR_UNDEFINED = 0x3, 3576 }; 3577 3578 enum { 3579 MLX5_EXE_ASO_FLOW_METER = 0x2, 3580 }; 3581 3582 struct mlx5_ifc_exe_aso_ctrl_flow_meter_bits { 3583 u8 return_reg_id[0x4]; 3584 u8 aso_type[0x4]; 3585 u8 reserved_at_8[0x14]; 3586 u8 action[0x1]; 3587 u8 init_color[0x2]; 3588 u8 meter_id[0x1]; 3589 }; 3590 3591 union mlx5_ifc_exe_aso_ctrl { 3592 struct mlx5_ifc_exe_aso_ctrl_flow_meter_bits exe_aso_ctrl_flow_meter; 3593 }; 3594 3595 struct mlx5_ifc_execute_aso_bits { 3596 u8 valid[0x1]; 3597 u8 reserved_at_1[0x7]; 3598 u8 aso_object_id[0x18]; 3599 3600 union mlx5_ifc_exe_aso_ctrl exe_aso_ctrl; 3601 }; 3602 3603 struct mlx5_ifc_flow_context_bits { 3604 struct mlx5_ifc_vlan_bits push_vlan; 3605 3606 u8 group_id[0x20]; 3607 3608 u8 reserved_at_40[0x8]; 3609 u8 flow_tag[0x18]; 3610 3611 u8 reserved_at_60[0x10]; 3612 u8 action[0x10]; 3613 3614 u8 extended_destination[0x1]; 3615 u8 uplink_hairpin_en[0x1]; 3616 u8 flow_source[0x2]; 3617 u8 encrypt_decrypt_type[0x4]; 3618 u8 destination_list_size[0x18]; 3619 3620 u8 reserved_at_a0[0x8]; 3621 u8 flow_counter_list_size[0x18]; 3622 3623 u8 packet_reformat_id[0x20]; 3624 3625 u8 modify_header_id[0x20]; 3626 3627 struct mlx5_ifc_vlan_bits push_vlan_2; 3628 3629 u8 encrypt_decrypt_obj_id[0x20]; 3630 u8 reserved_at_140[0xc0]; 3631 3632 struct mlx5_ifc_fte_match_param_bits match_value; 3633 3634 struct mlx5_ifc_execute_aso_bits execute_aso[4]; 3635 3636 u8 reserved_at_1300[0x500]; 3637 3638 union mlx5_ifc_dest_format_struct_flow_counter_list_auto_bits destination[]; 3639 }; 3640 3641 enum { 3642 MLX5_XRC_SRQC_STATE_GOOD = 0x0, 3643 MLX5_XRC_SRQC_STATE_ERROR = 0x1, 3644 }; 3645 3646 struct mlx5_ifc_xrc_srqc_bits { 3647 u8 state[0x4]; 3648 u8 log_xrc_srq_size[0x4]; 3649 u8 reserved_at_8[0x18]; 3650 3651 u8 wq_signature[0x1]; 3652 u8 cont_srq[0x1]; 3653 u8 reserved_at_22[0x1]; 3654 u8 rlky[0x1]; 3655 u8 basic_cyclic_rcv_wqe[0x1]; 3656 u8 log_rq_stride[0x3]; 3657 u8 xrcd[0x18]; 3658 3659 u8 page_offset[0x6]; 3660 u8 reserved_at_46[0x1]; 3661 u8 dbr_umem_valid[0x1]; 3662 u8 cqn[0x18]; 3663 3664 u8 reserved_at_60[0x20]; 3665 3666 u8 user_index_equal_xrc_srqn[0x1]; 3667 u8 reserved_at_81[0x1]; 3668 u8 log_page_size[0x6]; 3669 u8 user_index[0x18]; 3670 3671 u8 reserved_at_a0[0x20]; 3672 3673 u8 reserved_at_c0[0x8]; 3674 u8 pd[0x18]; 3675 3676 u8 lwm[0x10]; 3677 u8 wqe_cnt[0x10]; 3678 3679 u8 reserved_at_100[0x40]; 3680 3681 u8 db_record_addr_h[0x20]; 3682 3683 u8 db_record_addr_l[0x1e]; 3684 u8 reserved_at_17e[0x2]; 3685 3686 u8 reserved_at_180[0x80]; 3687 }; 3688 3689 struct mlx5_ifc_vnic_diagnostic_statistics_bits { 3690 u8 counter_error_queues[0x20]; 3691 3692 u8 total_error_queues[0x20]; 3693 3694 u8 send_queue_priority_update_flow[0x20]; 3695 3696 u8 reserved_at_60[0x20]; 3697 3698 u8 nic_receive_steering_discard[0x40]; 3699 3700 u8 receive_discard_vport_down[0x40]; 3701 3702 u8 transmit_discard_vport_down[0x40]; 3703 3704 u8 async_eq_overrun[0x20]; 3705 3706 u8 comp_eq_overrun[0x20]; 3707 3708 u8 reserved_at_180[0x20]; 3709 3710 u8 invalid_command[0x20]; 3711 3712 u8 quota_exceeded_command[0x20]; 3713 3714 u8 internal_rq_out_of_buffer[0x20]; 3715 3716 u8 cq_overrun[0x20]; 3717 3718 u8 eth_wqe_too_small[0x20]; 3719 3720 u8 reserved_at_220[0xc0]; 3721 3722 u8 generated_pkt_steering_fail[0x40]; 3723 3724 u8 handled_pkt_steering_fail[0x40]; 3725 3726 u8 reserved_at_360[0xc80]; 3727 }; 3728 3729 struct mlx5_ifc_traffic_counter_bits { 3730 u8 packets[0x40]; 3731 3732 u8 octets[0x40]; 3733 }; 3734 3735 struct mlx5_ifc_tisc_bits { 3736 u8 strict_lag_tx_port_affinity[0x1]; 3737 u8 tls_en[0x1]; 3738 u8 reserved_at_2[0x2]; 3739 u8 lag_tx_port_affinity[0x04]; 3740 3741 u8 reserved_at_8[0x4]; 3742 u8 prio[0x4]; 3743 u8 reserved_at_10[0x10]; 3744 3745 u8 reserved_at_20[0x100]; 3746 3747 u8 reserved_at_120[0x8]; 3748 u8 transport_domain[0x18]; 3749 3750 u8 reserved_at_140[0x8]; 3751 u8 underlay_qpn[0x18]; 3752 3753 u8 reserved_at_160[0x8]; 3754 u8 pd[0x18]; 3755 3756 u8 reserved_at_180[0x380]; 3757 }; 3758 3759 enum { 3760 MLX5_TIRC_DISP_TYPE_DIRECT = 0x0, 3761 MLX5_TIRC_DISP_TYPE_INDIRECT = 0x1, 3762 }; 3763 3764 enum { 3765 MLX5_TIRC_PACKET_MERGE_MASK_IPV4_LRO = BIT(0), 3766 MLX5_TIRC_PACKET_MERGE_MASK_IPV6_LRO = BIT(1), 3767 }; 3768 3769 enum { 3770 MLX5_RX_HASH_FN_NONE = 0x0, 3771 MLX5_RX_HASH_FN_INVERTED_XOR8 = 0x1, 3772 MLX5_RX_HASH_FN_TOEPLITZ = 0x2, 3773 }; 3774 3775 enum { 3776 MLX5_TIRC_SELF_LB_BLOCK_BLOCK_UNICAST = 0x1, 3777 MLX5_TIRC_SELF_LB_BLOCK_BLOCK_MULTICAST = 0x2, 3778 }; 3779 3780 struct mlx5_ifc_tirc_bits { 3781 u8 reserved_at_0[0x20]; 3782 3783 u8 disp_type[0x4]; 3784 u8 tls_en[0x1]; 3785 u8 reserved_at_25[0x1b]; 3786 3787 u8 reserved_at_40[0x40]; 3788 3789 u8 reserved_at_80[0x4]; 3790 u8 lro_timeout_period_usecs[0x10]; 3791 u8 packet_merge_mask[0x4]; 3792 u8 lro_max_ip_payload_size[0x8]; 3793 3794 u8 reserved_at_a0[0x40]; 3795 3796 u8 reserved_at_e0[0x8]; 3797 u8 inline_rqn[0x18]; 3798 3799 u8 rx_hash_symmetric[0x1]; 3800 u8 reserved_at_101[0x1]; 3801 u8 tunneled_offload_en[0x1]; 3802 u8 reserved_at_103[0x5]; 3803 u8 indirect_table[0x18]; 3804 3805 u8 rx_hash_fn[0x4]; 3806 u8 reserved_at_124[0x2]; 3807 u8 self_lb_block[0x2]; 3808 u8 transport_domain[0x18]; 3809 3810 u8 rx_hash_toeplitz_key[10][0x20]; 3811 3812 struct mlx5_ifc_rx_hash_field_select_bits rx_hash_field_selector_outer; 3813 3814 struct mlx5_ifc_rx_hash_field_select_bits rx_hash_field_selector_inner; 3815 3816 u8 reserved_at_2c0[0x4c0]; 3817 }; 3818 3819 enum { 3820 MLX5_SRQC_STATE_GOOD = 0x0, 3821 MLX5_SRQC_STATE_ERROR = 0x1, 3822 }; 3823 3824 struct mlx5_ifc_srqc_bits { 3825 u8 state[0x4]; 3826 u8 log_srq_size[0x4]; 3827 u8 reserved_at_8[0x18]; 3828 3829 u8 wq_signature[0x1]; 3830 u8 cont_srq[0x1]; 3831 u8 reserved_at_22[0x1]; 3832 u8 rlky[0x1]; 3833 u8 reserved_at_24[0x1]; 3834 u8 log_rq_stride[0x3]; 3835 u8 xrcd[0x18]; 3836 3837 u8 page_offset[0x6]; 3838 u8 reserved_at_46[0x2]; 3839 u8 cqn[0x18]; 3840 3841 u8 reserved_at_60[0x20]; 3842 3843 u8 reserved_at_80[0x2]; 3844 u8 log_page_size[0x6]; 3845 u8 reserved_at_88[0x18]; 3846 3847 u8 reserved_at_a0[0x20]; 3848 3849 u8 reserved_at_c0[0x8]; 3850 u8 pd[0x18]; 3851 3852 u8 lwm[0x10]; 3853 u8 wqe_cnt[0x10]; 3854 3855 u8 reserved_at_100[0x40]; 3856 3857 u8 dbr_addr[0x40]; 3858 3859 u8 reserved_at_180[0x80]; 3860 }; 3861 3862 enum { 3863 MLX5_SQC_STATE_RST = 0x0, 3864 MLX5_SQC_STATE_RDY = 0x1, 3865 MLX5_SQC_STATE_ERR = 0x3, 3866 }; 3867 3868 struct mlx5_ifc_sqc_bits { 3869 u8 rlky[0x1]; 3870 u8 cd_master[0x1]; 3871 u8 fre[0x1]; 3872 u8 flush_in_error_en[0x1]; 3873 u8 allow_multi_pkt_send_wqe[0x1]; 3874 u8 min_wqe_inline_mode[0x3]; 3875 u8 state[0x4]; 3876 u8 reg_umr[0x1]; 3877 u8 allow_swp[0x1]; 3878 u8 hairpin[0x1]; 3879 u8 reserved_at_f[0xb]; 3880 u8 ts_format[0x2]; 3881 u8 reserved_at_1c[0x4]; 3882 3883 u8 reserved_at_20[0x8]; 3884 u8 user_index[0x18]; 3885 3886 u8 reserved_at_40[0x8]; 3887 u8 cqn[0x18]; 3888 3889 u8 reserved_at_60[0x8]; 3890 u8 hairpin_peer_rq[0x18]; 3891 3892 u8 reserved_at_80[0x10]; 3893 u8 hairpin_peer_vhca[0x10]; 3894 3895 u8 reserved_at_a0[0x20]; 3896 3897 u8 reserved_at_c0[0x8]; 3898 u8 ts_cqe_to_dest_cqn[0x18]; 3899 3900 u8 reserved_at_e0[0x10]; 3901 u8 packet_pacing_rate_limit_index[0x10]; 3902 u8 tis_lst_sz[0x10]; 3903 u8 qos_queue_group_id[0x10]; 3904 3905 u8 reserved_at_120[0x40]; 3906 3907 u8 reserved_at_160[0x8]; 3908 u8 tis_num_0[0x18]; 3909 3910 struct mlx5_ifc_wq_bits wq; 3911 }; 3912 3913 enum { 3914 SCHEDULING_CONTEXT_ELEMENT_TYPE_TSAR = 0x0, 3915 SCHEDULING_CONTEXT_ELEMENT_TYPE_VPORT = 0x1, 3916 SCHEDULING_CONTEXT_ELEMENT_TYPE_VPORT_TC = 0x2, 3917 SCHEDULING_CONTEXT_ELEMENT_TYPE_PARA_VPORT_TC = 0x3, 3918 SCHEDULING_CONTEXT_ELEMENT_TYPE_QUEUE_GROUP = 0x4, 3919 }; 3920 3921 enum { 3922 ELEMENT_TYPE_CAP_MASK_TSAR = 1 << 0, 3923 ELEMENT_TYPE_CAP_MASK_VPORT = 1 << 1, 3924 ELEMENT_TYPE_CAP_MASK_VPORT_TC = 1 << 2, 3925 ELEMENT_TYPE_CAP_MASK_PARA_VPORT_TC = 1 << 3, 3926 }; 3927 3928 struct mlx5_ifc_scheduling_context_bits { 3929 u8 element_type[0x8]; 3930 u8 reserved_at_8[0x18]; 3931 3932 u8 element_attributes[0x20]; 3933 3934 u8 parent_element_id[0x20]; 3935 3936 u8 reserved_at_60[0x40]; 3937 3938 u8 bw_share[0x20]; 3939 3940 u8 max_average_bw[0x20]; 3941 3942 u8 reserved_at_e0[0x120]; 3943 }; 3944 3945 struct mlx5_ifc_rqtc_bits { 3946 u8 reserved_at_0[0xa0]; 3947 3948 u8 reserved_at_a0[0x5]; 3949 u8 list_q_type[0x3]; 3950 u8 reserved_at_a8[0x8]; 3951 u8 rqt_max_size[0x10]; 3952 3953 u8 rq_vhca_id_format[0x1]; 3954 u8 reserved_at_c1[0xf]; 3955 u8 rqt_actual_size[0x10]; 3956 3957 u8 reserved_at_e0[0x6a0]; 3958 3959 union { 3960 DECLARE_FLEX_ARRAY(struct mlx5_ifc_rq_num_bits, rq_num); 3961 DECLARE_FLEX_ARRAY(struct mlx5_ifc_rq_vhca_bits, rq_vhca); 3962 }; 3963 }; 3964 3965 enum { 3966 MLX5_RQC_MEM_RQ_TYPE_MEMORY_RQ_INLINE = 0x0, 3967 MLX5_RQC_MEM_RQ_TYPE_MEMORY_RQ_RMP = 0x1, 3968 }; 3969 3970 enum { 3971 MLX5_RQC_STATE_RST = 0x0, 3972 MLX5_RQC_STATE_RDY = 0x1, 3973 MLX5_RQC_STATE_ERR = 0x3, 3974 }; 3975 3976 enum { 3977 MLX5_RQC_SHAMPO_NO_MATCH_ALIGNMENT_GRANULARITY_BYTE = 0x0, 3978 MLX5_RQC_SHAMPO_NO_MATCH_ALIGNMENT_GRANULARITY_STRIDE = 0x1, 3979 MLX5_RQC_SHAMPO_NO_MATCH_ALIGNMENT_GRANULARITY_PAGE = 0x2, 3980 }; 3981 3982 enum { 3983 MLX5_RQC_SHAMPO_MATCH_CRITERIA_TYPE_NO_MATCH = 0x0, 3984 MLX5_RQC_SHAMPO_MATCH_CRITERIA_TYPE_EXTENDED = 0x1, 3985 MLX5_RQC_SHAMPO_MATCH_CRITERIA_TYPE_FIVE_TUPLE = 0x2, 3986 }; 3987 3988 struct mlx5_ifc_rqc_bits { 3989 u8 rlky[0x1]; 3990 u8 delay_drop_en[0x1]; 3991 u8 scatter_fcs[0x1]; 3992 u8 vsd[0x1]; 3993 u8 mem_rq_type[0x4]; 3994 u8 state[0x4]; 3995 u8 reserved_at_c[0x1]; 3996 u8 flush_in_error_en[0x1]; 3997 u8 hairpin[0x1]; 3998 u8 reserved_at_f[0xb]; 3999 u8 ts_format[0x2]; 4000 u8 reserved_at_1c[0x4]; 4001 4002 u8 reserved_at_20[0x8]; 4003 u8 user_index[0x18]; 4004 4005 u8 reserved_at_40[0x8]; 4006 u8 cqn[0x18]; 4007 4008 u8 counter_set_id[0x8]; 4009 u8 reserved_at_68[0x18]; 4010 4011 u8 reserved_at_80[0x8]; 4012 u8 rmpn[0x18]; 4013 4014 u8 reserved_at_a0[0x8]; 4015 u8 hairpin_peer_sq[0x18]; 4016 4017 u8 reserved_at_c0[0x10]; 4018 u8 hairpin_peer_vhca[0x10]; 4019 4020 u8 reserved_at_e0[0x46]; 4021 u8 shampo_no_match_alignment_granularity[0x2]; 4022 u8 reserved_at_128[0x6]; 4023 u8 shampo_match_criteria_type[0x2]; 4024 u8 reservation_timeout[0x10]; 4025 4026 u8 reserved_at_140[0x40]; 4027 4028 struct mlx5_ifc_wq_bits wq; 4029 }; 4030 4031 enum { 4032 MLX5_RMPC_STATE_RDY = 0x1, 4033 MLX5_RMPC_STATE_ERR = 0x3, 4034 }; 4035 4036 struct mlx5_ifc_rmpc_bits { 4037 u8 reserved_at_0[0x8]; 4038 u8 state[0x4]; 4039 u8 reserved_at_c[0x14]; 4040 4041 u8 basic_cyclic_rcv_wqe[0x1]; 4042 u8 reserved_at_21[0x1f]; 4043 4044 u8 reserved_at_40[0x140]; 4045 4046 struct mlx5_ifc_wq_bits wq; 4047 }; 4048 4049 enum { 4050 VHCA_ID_TYPE_HW = 0, 4051 VHCA_ID_TYPE_SW = 1, 4052 }; 4053 4054 struct mlx5_ifc_nic_vport_context_bits { 4055 u8 reserved_at_0[0x5]; 4056 u8 min_wqe_inline_mode[0x3]; 4057 u8 reserved_at_8[0x15]; 4058 u8 disable_mc_local_lb[0x1]; 4059 u8 disable_uc_local_lb[0x1]; 4060 u8 roce_en[0x1]; 4061 4062 u8 arm_change_event[0x1]; 4063 u8 reserved_at_21[0x1a]; 4064 u8 event_on_mtu[0x1]; 4065 u8 event_on_promisc_change[0x1]; 4066 u8 event_on_vlan_change[0x1]; 4067 u8 event_on_mc_address_change[0x1]; 4068 u8 event_on_uc_address_change[0x1]; 4069 4070 u8 vhca_id_type[0x1]; 4071 u8 reserved_at_41[0xb]; 4072 u8 affiliation_criteria[0x4]; 4073 u8 affiliated_vhca_id[0x10]; 4074 4075 u8 reserved_at_60[0xa0]; 4076 4077 u8 reserved_at_100[0x1]; 4078 u8 sd_group[0x3]; 4079 u8 reserved_at_104[0x1c]; 4080 4081 u8 reserved_at_120[0x10]; 4082 u8 mtu[0x10]; 4083 4084 u8 system_image_guid[0x40]; 4085 u8 port_guid[0x40]; 4086 u8 node_guid[0x40]; 4087 4088 u8 reserved_at_200[0x140]; 4089 u8 qkey_violation_counter[0x10]; 4090 u8 reserved_at_350[0x430]; 4091 4092 u8 promisc_uc[0x1]; 4093 u8 promisc_mc[0x1]; 4094 u8 promisc_all[0x1]; 4095 u8 reserved_at_783[0x2]; 4096 u8 allowed_list_type[0x3]; 4097 u8 reserved_at_788[0xc]; 4098 u8 allowed_list_size[0xc]; 4099 4100 struct mlx5_ifc_mac_address_layout_bits permanent_address; 4101 4102 u8 reserved_at_7e0[0x20]; 4103 4104 u8 current_uc_mac_address[][0x40]; 4105 }; 4106 4107 enum { 4108 MLX5_MKC_ACCESS_MODE_PA = 0x0, 4109 MLX5_MKC_ACCESS_MODE_MTT = 0x1, 4110 MLX5_MKC_ACCESS_MODE_KLMS = 0x2, 4111 MLX5_MKC_ACCESS_MODE_KSM = 0x3, 4112 MLX5_MKC_ACCESS_MODE_SW_ICM = 0x4, 4113 MLX5_MKC_ACCESS_MODE_MEMIC = 0x5, 4114 }; 4115 4116 struct mlx5_ifc_mkc_bits { 4117 u8 reserved_at_0[0x1]; 4118 u8 free[0x1]; 4119 u8 reserved_at_2[0x1]; 4120 u8 access_mode_4_2[0x3]; 4121 u8 reserved_at_6[0x7]; 4122 u8 relaxed_ordering_write[0x1]; 4123 u8 reserved_at_e[0x1]; 4124 u8 small_fence_on_rdma_read_response[0x1]; 4125 u8 umr_en[0x1]; 4126 u8 a[0x1]; 4127 u8 rw[0x1]; 4128 u8 rr[0x1]; 4129 u8 lw[0x1]; 4130 u8 lr[0x1]; 4131 u8 access_mode_1_0[0x2]; 4132 u8 reserved_at_18[0x2]; 4133 u8 ma_translation_mode[0x2]; 4134 u8 reserved_at_1c[0x4]; 4135 4136 u8 qpn[0x18]; 4137 u8 mkey_7_0[0x8]; 4138 4139 u8 reserved_at_40[0x20]; 4140 4141 u8 length64[0x1]; 4142 u8 bsf_en[0x1]; 4143 u8 sync_umr[0x1]; 4144 u8 reserved_at_63[0x2]; 4145 u8 expected_sigerr_count[0x1]; 4146 u8 reserved_at_66[0x1]; 4147 u8 en_rinval[0x1]; 4148 u8 pd[0x18]; 4149 4150 u8 start_addr[0x40]; 4151 4152 u8 len[0x40]; 4153 4154 u8 bsf_octword_size[0x20]; 4155 4156 u8 reserved_at_120[0x80]; 4157 4158 u8 translations_octword_size[0x20]; 4159 4160 u8 reserved_at_1c0[0x19]; 4161 u8 relaxed_ordering_read[0x1]; 4162 u8 reserved_at_1d9[0x1]; 4163 u8 log_page_size[0x5]; 4164 4165 u8 reserved_at_1e0[0x20]; 4166 }; 4167 4168 struct mlx5_ifc_pkey_bits { 4169 u8 reserved_at_0[0x10]; 4170 u8 pkey[0x10]; 4171 }; 4172 4173 struct mlx5_ifc_array128_auto_bits { 4174 u8 array128_auto[16][0x8]; 4175 }; 4176 4177 struct mlx5_ifc_hca_vport_context_bits { 4178 u8 field_select[0x20]; 4179 4180 u8 reserved_at_20[0xe0]; 4181 4182 u8 sm_virt_aware[0x1]; 4183 u8 has_smi[0x1]; 4184 u8 has_raw[0x1]; 4185 u8 grh_required[0x1]; 4186 u8 reserved_at_104[0xc]; 4187 u8 port_physical_state[0x4]; 4188 u8 vport_state_policy[0x4]; 4189 u8 port_state[0x4]; 4190 u8 vport_state[0x4]; 4191 4192 u8 reserved_at_120[0x20]; 4193 4194 u8 system_image_guid[0x40]; 4195 4196 u8 port_guid[0x40]; 4197 4198 u8 node_guid[0x40]; 4199 4200 u8 cap_mask1[0x20]; 4201 4202 u8 cap_mask1_field_select[0x20]; 4203 4204 u8 cap_mask2[0x20]; 4205 4206 u8 cap_mask2_field_select[0x20]; 4207 4208 u8 reserved_at_280[0x80]; 4209 4210 u8 lid[0x10]; 4211 u8 reserved_at_310[0x4]; 4212 u8 init_type_reply[0x4]; 4213 u8 lmc[0x3]; 4214 u8 subnet_timeout[0x5]; 4215 4216 u8 sm_lid[0x10]; 4217 u8 sm_sl[0x4]; 4218 u8 reserved_at_334[0xc]; 4219 4220 u8 qkey_violation_counter[0x10]; 4221 u8 pkey_violation_counter[0x10]; 4222 4223 u8 reserved_at_360[0xca0]; 4224 }; 4225 4226 struct mlx5_ifc_esw_vport_context_bits { 4227 u8 fdb_to_vport_reg_c[0x1]; 4228 u8 reserved_at_1[0x2]; 4229 u8 vport_svlan_strip[0x1]; 4230 u8 vport_cvlan_strip[0x1]; 4231 u8 vport_svlan_insert[0x1]; 4232 u8 vport_cvlan_insert[0x2]; 4233 u8 fdb_to_vport_reg_c_id[0x8]; 4234 u8 reserved_at_10[0x10]; 4235 4236 u8 reserved_at_20[0x20]; 4237 4238 u8 svlan_cfi[0x1]; 4239 u8 svlan_pcp[0x3]; 4240 u8 svlan_id[0xc]; 4241 u8 cvlan_cfi[0x1]; 4242 u8 cvlan_pcp[0x3]; 4243 u8 cvlan_id[0xc]; 4244 4245 u8 reserved_at_60[0x720]; 4246 4247 u8 sw_steering_vport_icm_address_rx[0x40]; 4248 4249 u8 sw_steering_vport_icm_address_tx[0x40]; 4250 }; 4251 4252 enum { 4253 MLX5_EQC_STATUS_OK = 0x0, 4254 MLX5_EQC_STATUS_EQ_WRITE_FAILURE = 0xa, 4255 }; 4256 4257 enum { 4258 MLX5_EQC_ST_ARMED = 0x9, 4259 MLX5_EQC_ST_FIRED = 0xa, 4260 }; 4261 4262 struct mlx5_ifc_eqc_bits { 4263 u8 status[0x4]; 4264 u8 reserved_at_4[0x9]; 4265 u8 ec[0x1]; 4266 u8 oi[0x1]; 4267 u8 reserved_at_f[0x5]; 4268 u8 st[0x4]; 4269 u8 reserved_at_18[0x8]; 4270 4271 u8 reserved_at_20[0x20]; 4272 4273 u8 reserved_at_40[0x14]; 4274 u8 page_offset[0x6]; 4275 u8 reserved_at_5a[0x6]; 4276 4277 u8 reserved_at_60[0x3]; 4278 u8 log_eq_size[0x5]; 4279 u8 uar_page[0x18]; 4280 4281 u8 reserved_at_80[0x20]; 4282 4283 u8 reserved_at_a0[0x14]; 4284 u8 intr[0xc]; 4285 4286 u8 reserved_at_c0[0x3]; 4287 u8 log_page_size[0x5]; 4288 u8 reserved_at_c8[0x18]; 4289 4290 u8 reserved_at_e0[0x60]; 4291 4292 u8 reserved_at_140[0x8]; 4293 u8 consumer_counter[0x18]; 4294 4295 u8 reserved_at_160[0x8]; 4296 u8 producer_counter[0x18]; 4297 4298 u8 reserved_at_180[0x80]; 4299 }; 4300 4301 enum { 4302 MLX5_DCTC_STATE_ACTIVE = 0x0, 4303 MLX5_DCTC_STATE_DRAINING = 0x1, 4304 MLX5_DCTC_STATE_DRAINED = 0x2, 4305 }; 4306 4307 enum { 4308 MLX5_DCTC_CS_RES_DISABLE = 0x0, 4309 MLX5_DCTC_CS_RES_NA = 0x1, 4310 MLX5_DCTC_CS_RES_UP_TO_64B = 0x2, 4311 }; 4312 4313 enum { 4314 MLX5_DCTC_MTU_256_BYTES = 0x1, 4315 MLX5_DCTC_MTU_512_BYTES = 0x2, 4316 MLX5_DCTC_MTU_1K_BYTES = 0x3, 4317 MLX5_DCTC_MTU_2K_BYTES = 0x4, 4318 MLX5_DCTC_MTU_4K_BYTES = 0x5, 4319 }; 4320 4321 struct mlx5_ifc_dctc_bits { 4322 u8 reserved_at_0[0x4]; 4323 u8 state[0x4]; 4324 u8 reserved_at_8[0x18]; 4325 4326 u8 reserved_at_20[0x8]; 4327 u8 user_index[0x18]; 4328 4329 u8 reserved_at_40[0x8]; 4330 u8 cqn[0x18]; 4331 4332 u8 counter_set_id[0x8]; 4333 u8 atomic_mode[0x4]; 4334 u8 rre[0x1]; 4335 u8 rwe[0x1]; 4336 u8 rae[0x1]; 4337 u8 atomic_like_write_en[0x1]; 4338 u8 latency_sensitive[0x1]; 4339 u8 rlky[0x1]; 4340 u8 free_ar[0x1]; 4341 u8 reserved_at_73[0xd]; 4342 4343 u8 reserved_at_80[0x8]; 4344 u8 cs_res[0x8]; 4345 u8 reserved_at_90[0x3]; 4346 u8 min_rnr_nak[0x5]; 4347 u8 reserved_at_98[0x8]; 4348 4349 u8 reserved_at_a0[0x8]; 4350 u8 srqn_xrqn[0x18]; 4351 4352 u8 reserved_at_c0[0x8]; 4353 u8 pd[0x18]; 4354 4355 u8 tclass[0x8]; 4356 u8 reserved_at_e8[0x4]; 4357 u8 flow_label[0x14]; 4358 4359 u8 dc_access_key[0x40]; 4360 4361 u8 reserved_at_140[0x5]; 4362 u8 mtu[0x3]; 4363 u8 port[0x8]; 4364 u8 pkey_index[0x10]; 4365 4366 u8 reserved_at_160[0x8]; 4367 u8 my_addr_index[0x8]; 4368 u8 reserved_at_170[0x8]; 4369 u8 hop_limit[0x8]; 4370 4371 u8 dc_access_key_violation_count[0x20]; 4372 4373 u8 reserved_at_1a0[0x14]; 4374 u8 dei_cfi[0x1]; 4375 u8 eth_prio[0x3]; 4376 u8 ecn[0x2]; 4377 u8 dscp[0x6]; 4378 4379 u8 reserved_at_1c0[0x20]; 4380 u8 ece[0x20]; 4381 }; 4382 4383 enum { 4384 MLX5_CQC_STATUS_OK = 0x0, 4385 MLX5_CQC_STATUS_CQ_OVERFLOW = 0x9, 4386 MLX5_CQC_STATUS_CQ_WRITE_FAIL = 0xa, 4387 }; 4388 4389 enum { 4390 MLX5_CQC_CQE_SZ_64_BYTES = 0x0, 4391 MLX5_CQC_CQE_SZ_128_BYTES = 0x1, 4392 }; 4393 4394 enum { 4395 MLX5_CQC_ST_SOLICITED_NOTIFICATION_REQUEST_ARMED = 0x6, 4396 MLX5_CQC_ST_NOTIFICATION_REQUEST_ARMED = 0x9, 4397 MLX5_CQC_ST_FIRED = 0xa, 4398 }; 4399 4400 enum mlx5_cq_period_mode { 4401 MLX5_CQ_PERIOD_MODE_START_FROM_EQE = 0x0, 4402 MLX5_CQ_PERIOD_MODE_START_FROM_CQE = 0x1, 4403 MLX5_CQ_PERIOD_NUM_MODES, 4404 }; 4405 4406 struct mlx5_ifc_cqc_bits { 4407 u8 status[0x4]; 4408 u8 reserved_at_4[0x2]; 4409 u8 dbr_umem_valid[0x1]; 4410 u8 apu_cq[0x1]; 4411 u8 cqe_sz[0x3]; 4412 u8 cc[0x1]; 4413 u8 reserved_at_c[0x1]; 4414 u8 scqe_break_moderation_en[0x1]; 4415 u8 oi[0x1]; 4416 u8 cq_period_mode[0x2]; 4417 u8 cqe_comp_en[0x1]; 4418 u8 mini_cqe_res_format[0x2]; 4419 u8 st[0x4]; 4420 u8 reserved_at_18[0x6]; 4421 u8 cqe_compression_layout[0x2]; 4422 4423 u8 reserved_at_20[0x20]; 4424 4425 u8 reserved_at_40[0x14]; 4426 u8 page_offset[0x6]; 4427 u8 reserved_at_5a[0x6]; 4428 4429 u8 reserved_at_60[0x3]; 4430 u8 log_cq_size[0x5]; 4431 u8 uar_page[0x18]; 4432 4433 u8 reserved_at_80[0x4]; 4434 u8 cq_period[0xc]; 4435 u8 cq_max_count[0x10]; 4436 4437 u8 c_eqn_or_apu_element[0x20]; 4438 4439 u8 reserved_at_c0[0x3]; 4440 u8 log_page_size[0x5]; 4441 u8 reserved_at_c8[0x18]; 4442 4443 u8 reserved_at_e0[0x20]; 4444 4445 u8 reserved_at_100[0x8]; 4446 u8 last_notified_index[0x18]; 4447 4448 u8 reserved_at_120[0x8]; 4449 u8 last_solicit_index[0x18]; 4450 4451 u8 reserved_at_140[0x8]; 4452 u8 consumer_counter[0x18]; 4453 4454 u8 reserved_at_160[0x8]; 4455 u8 producer_counter[0x18]; 4456 4457 u8 reserved_at_180[0x40]; 4458 4459 u8 dbr_addr[0x40]; 4460 }; 4461 4462 union mlx5_ifc_cong_control_roce_ecn_auto_bits { 4463 struct mlx5_ifc_cong_control_802_1qau_rp_bits cong_control_802_1qau_rp; 4464 struct mlx5_ifc_cong_control_r_roce_ecn_rp_bits cong_control_r_roce_ecn_rp; 4465 struct mlx5_ifc_cong_control_r_roce_ecn_np_bits cong_control_r_roce_ecn_np; 4466 struct mlx5_ifc_cong_control_r_roce_general_bits cong_control_r_roce_general; 4467 u8 reserved_at_0[0x800]; 4468 }; 4469 4470 struct mlx5_ifc_query_adapter_param_block_bits { 4471 u8 reserved_at_0[0xc0]; 4472 4473 u8 reserved_at_c0[0x8]; 4474 u8 ieee_vendor_id[0x18]; 4475 4476 u8 reserved_at_e0[0x10]; 4477 u8 vsd_vendor_id[0x10]; 4478 4479 u8 vsd[208][0x8]; 4480 4481 u8 vsd_contd_psid[16][0x8]; 4482 }; 4483 4484 enum { 4485 MLX5_XRQC_STATE_GOOD = 0x0, 4486 MLX5_XRQC_STATE_ERROR = 0x1, 4487 }; 4488 4489 enum { 4490 MLX5_XRQC_TOPOLOGY_NO_SPECIAL_TOPOLOGY = 0x0, 4491 MLX5_XRQC_TOPOLOGY_TAG_MATCHING = 0x1, 4492 }; 4493 4494 enum { 4495 MLX5_XRQC_OFFLOAD_RNDV = 0x1, 4496 }; 4497 4498 struct mlx5_ifc_tag_matching_topology_context_bits { 4499 u8 log_matching_list_sz[0x4]; 4500 u8 reserved_at_4[0xc]; 4501 u8 append_next_index[0x10]; 4502 4503 u8 sw_phase_cnt[0x10]; 4504 u8 hw_phase_cnt[0x10]; 4505 4506 u8 reserved_at_40[0x40]; 4507 }; 4508 4509 struct mlx5_ifc_xrqc_bits { 4510 u8 state[0x4]; 4511 u8 rlkey[0x1]; 4512 u8 reserved_at_5[0xf]; 4513 u8 topology[0x4]; 4514 u8 reserved_at_18[0x4]; 4515 u8 offload[0x4]; 4516 4517 u8 reserved_at_20[0x8]; 4518 u8 user_index[0x18]; 4519 4520 u8 reserved_at_40[0x8]; 4521 u8 cqn[0x18]; 4522 4523 u8 reserved_at_60[0xa0]; 4524 4525 struct mlx5_ifc_tag_matching_topology_context_bits tag_matching_topology_context; 4526 4527 u8 reserved_at_180[0x280]; 4528 4529 struct mlx5_ifc_wq_bits wq; 4530 }; 4531 4532 union mlx5_ifc_modify_field_select_resize_field_select_auto_bits { 4533 struct mlx5_ifc_modify_field_select_bits modify_field_select; 4534 struct mlx5_ifc_resize_field_select_bits resize_field_select; 4535 u8 reserved_at_0[0x20]; 4536 }; 4537 4538 union mlx5_ifc_field_select_802_1_r_roce_auto_bits { 4539 struct mlx5_ifc_field_select_802_1qau_rp_bits field_select_802_1qau_rp; 4540 struct mlx5_ifc_field_select_r_roce_rp_bits field_select_r_roce_rp; 4541 struct mlx5_ifc_field_select_r_roce_np_bits field_select_r_roce_np; 4542 u8 reserved_at_0[0x20]; 4543 }; 4544 4545 union mlx5_ifc_eth_cntrs_grp_data_layout_auto_bits { 4546 struct mlx5_ifc_eth_802_3_cntrs_grp_data_layout_bits eth_802_3_cntrs_grp_data_layout; 4547 struct mlx5_ifc_eth_2863_cntrs_grp_data_layout_bits eth_2863_cntrs_grp_data_layout; 4548 struct mlx5_ifc_eth_2819_cntrs_grp_data_layout_bits eth_2819_cntrs_grp_data_layout; 4549 struct mlx5_ifc_eth_3635_cntrs_grp_data_layout_bits eth_3635_cntrs_grp_data_layout; 4550 struct mlx5_ifc_eth_extended_cntrs_grp_data_layout_bits eth_extended_cntrs_grp_data_layout; 4551 struct mlx5_ifc_eth_per_prio_grp_data_layout_bits eth_per_prio_grp_data_layout; 4552 struct mlx5_ifc_eth_per_tc_prio_grp_data_layout_bits eth_per_tc_prio_grp_data_layout; 4553 struct mlx5_ifc_eth_per_tc_congest_prio_grp_data_layout_bits eth_per_tc_congest_prio_grp_data_layout; 4554 struct mlx5_ifc_ib_port_cntrs_grp_data_layout_bits ib_port_cntrs_grp_data_layout; 4555 struct mlx5_ifc_phys_layer_cntrs_bits phys_layer_cntrs; 4556 struct mlx5_ifc_phys_layer_statistical_cntrs_bits phys_layer_statistical_cntrs; 4557 u8 reserved_at_0[0x7c0]; 4558 }; 4559 4560 union mlx5_ifc_pcie_cntrs_grp_data_layout_auto_bits { 4561 struct mlx5_ifc_pcie_perf_cntrs_grp_data_layout_bits pcie_perf_cntrs_grp_data_layout; 4562 u8 reserved_at_0[0x7c0]; 4563 }; 4564 4565 union mlx5_ifc_event_auto_bits { 4566 struct mlx5_ifc_comp_event_bits comp_event; 4567 struct mlx5_ifc_dct_events_bits dct_events; 4568 struct mlx5_ifc_qp_events_bits qp_events; 4569 struct mlx5_ifc_wqe_associated_page_fault_event_bits wqe_associated_page_fault_event; 4570 struct mlx5_ifc_rdma_page_fault_event_bits rdma_page_fault_event; 4571 struct mlx5_ifc_cq_error_bits cq_error; 4572 struct mlx5_ifc_dropped_packet_logged_bits dropped_packet_logged; 4573 struct mlx5_ifc_port_state_change_event_bits port_state_change_event; 4574 struct mlx5_ifc_gpio_event_bits gpio_event; 4575 struct mlx5_ifc_db_bf_congestion_event_bits db_bf_congestion_event; 4576 struct mlx5_ifc_stall_vl_event_bits stall_vl_event; 4577 struct mlx5_ifc_cmd_inter_comp_event_bits cmd_inter_comp_event; 4578 u8 reserved_at_0[0xe0]; 4579 }; 4580 4581 struct mlx5_ifc_health_buffer_bits { 4582 u8 reserved_at_0[0x100]; 4583 4584 u8 assert_existptr[0x20]; 4585 4586 u8 assert_callra[0x20]; 4587 4588 u8 reserved_at_140[0x20]; 4589 4590 u8 time[0x20]; 4591 4592 u8 fw_version[0x20]; 4593 4594 u8 hw_id[0x20]; 4595 4596 u8 rfr[0x1]; 4597 u8 reserved_at_1c1[0x3]; 4598 u8 valid[0x1]; 4599 u8 severity[0x3]; 4600 u8 reserved_at_1c8[0x18]; 4601 4602 u8 irisc_index[0x8]; 4603 u8 synd[0x8]; 4604 u8 ext_synd[0x10]; 4605 }; 4606 4607 struct mlx5_ifc_register_loopback_control_bits { 4608 u8 no_lb[0x1]; 4609 u8 reserved_at_1[0x7]; 4610 u8 port[0x8]; 4611 u8 reserved_at_10[0x10]; 4612 4613 u8 reserved_at_20[0x60]; 4614 }; 4615 4616 struct mlx5_ifc_vport_tc_element_bits { 4617 u8 traffic_class[0x4]; 4618 u8 reserved_at_4[0xc]; 4619 u8 vport_number[0x10]; 4620 }; 4621 4622 struct mlx5_ifc_vport_element_bits { 4623 u8 reserved_at_0[0x10]; 4624 u8 vport_number[0x10]; 4625 }; 4626 4627 enum { 4628 TSAR_ELEMENT_TSAR_TYPE_DWRR = 0x0, 4629 TSAR_ELEMENT_TSAR_TYPE_ROUND_ROBIN = 0x1, 4630 TSAR_ELEMENT_TSAR_TYPE_ETS = 0x2, 4631 }; 4632 4633 struct mlx5_ifc_tsar_element_bits { 4634 u8 reserved_at_0[0x8]; 4635 u8 tsar_type[0x8]; 4636 u8 reserved_at_10[0x10]; 4637 }; 4638 4639 enum { 4640 MLX5_TEARDOWN_HCA_OUT_FORCE_STATE_SUCCESS = 0x0, 4641 MLX5_TEARDOWN_HCA_OUT_FORCE_STATE_FAIL = 0x1, 4642 }; 4643 4644 struct mlx5_ifc_teardown_hca_out_bits { 4645 u8 status[0x8]; 4646 u8 reserved_at_8[0x18]; 4647 4648 u8 syndrome[0x20]; 4649 4650 u8 reserved_at_40[0x3f]; 4651 4652 u8 state[0x1]; 4653 }; 4654 4655 enum { 4656 MLX5_TEARDOWN_HCA_IN_PROFILE_GRACEFUL_CLOSE = 0x0, 4657 MLX5_TEARDOWN_HCA_IN_PROFILE_FORCE_CLOSE = 0x1, 4658 MLX5_TEARDOWN_HCA_IN_PROFILE_PREPARE_FAST_TEARDOWN = 0x2, 4659 }; 4660 4661 struct mlx5_ifc_teardown_hca_in_bits { 4662 u8 opcode[0x10]; 4663 u8 reserved_at_10[0x10]; 4664 4665 u8 reserved_at_20[0x10]; 4666 u8 op_mod[0x10]; 4667 4668 u8 reserved_at_40[0x10]; 4669 u8 profile[0x10]; 4670 4671 u8 reserved_at_60[0x20]; 4672 }; 4673 4674 struct mlx5_ifc_sqerr2rts_qp_out_bits { 4675 u8 status[0x8]; 4676 u8 reserved_at_8[0x18]; 4677 4678 u8 syndrome[0x20]; 4679 4680 u8 reserved_at_40[0x40]; 4681 }; 4682 4683 struct mlx5_ifc_sqerr2rts_qp_in_bits { 4684 u8 opcode[0x10]; 4685 u8 uid[0x10]; 4686 4687 u8 reserved_at_20[0x10]; 4688 u8 op_mod[0x10]; 4689 4690 u8 reserved_at_40[0x8]; 4691 u8 qpn[0x18]; 4692 4693 u8 reserved_at_60[0x20]; 4694 4695 u8 opt_param_mask[0x20]; 4696 4697 u8 reserved_at_a0[0x20]; 4698 4699 struct mlx5_ifc_qpc_bits qpc; 4700 4701 u8 reserved_at_800[0x80]; 4702 }; 4703 4704 struct mlx5_ifc_sqd2rts_qp_out_bits { 4705 u8 status[0x8]; 4706 u8 reserved_at_8[0x18]; 4707 4708 u8 syndrome[0x20]; 4709 4710 u8 reserved_at_40[0x40]; 4711 }; 4712 4713 struct mlx5_ifc_sqd2rts_qp_in_bits { 4714 u8 opcode[0x10]; 4715 u8 uid[0x10]; 4716 4717 u8 reserved_at_20[0x10]; 4718 u8 op_mod[0x10]; 4719 4720 u8 reserved_at_40[0x8]; 4721 u8 qpn[0x18]; 4722 4723 u8 reserved_at_60[0x20]; 4724 4725 u8 opt_param_mask[0x20]; 4726 4727 u8 reserved_at_a0[0x20]; 4728 4729 struct mlx5_ifc_qpc_bits qpc; 4730 4731 u8 reserved_at_800[0x80]; 4732 }; 4733 4734 struct mlx5_ifc_set_roce_address_out_bits { 4735 u8 status[0x8]; 4736 u8 reserved_at_8[0x18]; 4737 4738 u8 syndrome[0x20]; 4739 4740 u8 reserved_at_40[0x40]; 4741 }; 4742 4743 struct mlx5_ifc_set_roce_address_in_bits { 4744 u8 opcode[0x10]; 4745 u8 reserved_at_10[0x10]; 4746 4747 u8 reserved_at_20[0x10]; 4748 u8 op_mod[0x10]; 4749 4750 u8 roce_address_index[0x10]; 4751 u8 reserved_at_50[0xc]; 4752 u8 vhca_port_num[0x4]; 4753 4754 u8 reserved_at_60[0x20]; 4755 4756 struct mlx5_ifc_roce_addr_layout_bits roce_address; 4757 }; 4758 4759 struct mlx5_ifc_set_mad_demux_out_bits { 4760 u8 status[0x8]; 4761 u8 reserved_at_8[0x18]; 4762 4763 u8 syndrome[0x20]; 4764 4765 u8 reserved_at_40[0x40]; 4766 }; 4767 4768 enum { 4769 MLX5_SET_MAD_DEMUX_IN_DEMUX_MODE_PASS_ALL = 0x0, 4770 MLX5_SET_MAD_DEMUX_IN_DEMUX_MODE_SELECTIVE = 0x2, 4771 }; 4772 4773 struct mlx5_ifc_set_mad_demux_in_bits { 4774 u8 opcode[0x10]; 4775 u8 reserved_at_10[0x10]; 4776 4777 u8 reserved_at_20[0x10]; 4778 u8 op_mod[0x10]; 4779 4780 u8 reserved_at_40[0x20]; 4781 4782 u8 reserved_at_60[0x6]; 4783 u8 demux_mode[0x2]; 4784 u8 reserved_at_68[0x18]; 4785 }; 4786 4787 struct mlx5_ifc_set_l2_table_entry_out_bits { 4788 u8 status[0x8]; 4789 u8 reserved_at_8[0x18]; 4790 4791 u8 syndrome[0x20]; 4792 4793 u8 reserved_at_40[0x40]; 4794 }; 4795 4796 struct mlx5_ifc_set_l2_table_entry_in_bits { 4797 u8 opcode[0x10]; 4798 u8 reserved_at_10[0x10]; 4799 4800 u8 reserved_at_20[0x10]; 4801 u8 op_mod[0x10]; 4802 4803 u8 reserved_at_40[0x60]; 4804 4805 u8 reserved_at_a0[0x8]; 4806 u8 table_index[0x18]; 4807 4808 u8 reserved_at_c0[0x20]; 4809 4810 u8 reserved_at_e0[0x10]; 4811 u8 silent_mode_valid[0x1]; 4812 u8 silent_mode[0x1]; 4813 u8 reserved_at_f2[0x1]; 4814 u8 vlan_valid[0x1]; 4815 u8 vlan[0xc]; 4816 4817 struct mlx5_ifc_mac_address_layout_bits mac_address; 4818 4819 u8 reserved_at_140[0xc0]; 4820 }; 4821 4822 struct mlx5_ifc_set_issi_out_bits { 4823 u8 status[0x8]; 4824 u8 reserved_at_8[0x18]; 4825 4826 u8 syndrome[0x20]; 4827 4828 u8 reserved_at_40[0x40]; 4829 }; 4830 4831 struct mlx5_ifc_set_issi_in_bits { 4832 u8 opcode[0x10]; 4833 u8 reserved_at_10[0x10]; 4834 4835 u8 reserved_at_20[0x10]; 4836 u8 op_mod[0x10]; 4837 4838 u8 reserved_at_40[0x10]; 4839 u8 current_issi[0x10]; 4840 4841 u8 reserved_at_60[0x20]; 4842 }; 4843 4844 struct mlx5_ifc_set_hca_cap_out_bits { 4845 u8 status[0x8]; 4846 u8 reserved_at_8[0x18]; 4847 4848 u8 syndrome[0x20]; 4849 4850 u8 reserved_at_40[0x40]; 4851 }; 4852 4853 struct mlx5_ifc_set_hca_cap_in_bits { 4854 u8 opcode[0x10]; 4855 u8 reserved_at_10[0x10]; 4856 4857 u8 reserved_at_20[0x10]; 4858 u8 op_mod[0x10]; 4859 4860 u8 other_function[0x1]; 4861 u8 ec_vf_function[0x1]; 4862 u8 reserved_at_42[0xe]; 4863 u8 function_id[0x10]; 4864 4865 u8 reserved_at_60[0x20]; 4866 4867 union mlx5_ifc_hca_cap_union_bits capability; 4868 }; 4869 4870 enum { 4871 MLX5_SET_FTE_MODIFY_ENABLE_MASK_ACTION = 0x0, 4872 MLX5_SET_FTE_MODIFY_ENABLE_MASK_FLOW_TAG = 0x1, 4873 MLX5_SET_FTE_MODIFY_ENABLE_MASK_DESTINATION_LIST = 0x2, 4874 MLX5_SET_FTE_MODIFY_ENABLE_MASK_FLOW_COUNTERS = 0x3, 4875 MLX5_SET_FTE_MODIFY_ENABLE_MASK_IPSEC_OBJ_ID = 0x4 4876 }; 4877 4878 struct mlx5_ifc_set_fte_out_bits { 4879 u8 status[0x8]; 4880 u8 reserved_at_8[0x18]; 4881 4882 u8 syndrome[0x20]; 4883 4884 u8 reserved_at_40[0x40]; 4885 }; 4886 4887 struct mlx5_ifc_set_fte_in_bits { 4888 u8 opcode[0x10]; 4889 u8 reserved_at_10[0x10]; 4890 4891 u8 reserved_at_20[0x10]; 4892 u8 op_mod[0x10]; 4893 4894 u8 other_vport[0x1]; 4895 u8 reserved_at_41[0xf]; 4896 u8 vport_number[0x10]; 4897 4898 u8 reserved_at_60[0x20]; 4899 4900 u8 table_type[0x8]; 4901 u8 reserved_at_88[0x18]; 4902 4903 u8 reserved_at_a0[0x8]; 4904 u8 table_id[0x18]; 4905 4906 u8 ignore_flow_level[0x1]; 4907 u8 reserved_at_c1[0x17]; 4908 u8 modify_enable_mask[0x8]; 4909 4910 u8 reserved_at_e0[0x20]; 4911 4912 u8 flow_index[0x20]; 4913 4914 u8 reserved_at_120[0xe0]; 4915 4916 struct mlx5_ifc_flow_context_bits flow_context; 4917 }; 4918 4919 struct mlx5_ifc_rts2rts_qp_out_bits { 4920 u8 status[0x8]; 4921 u8 reserved_at_8[0x18]; 4922 4923 u8 syndrome[0x20]; 4924 4925 u8 reserved_at_40[0x20]; 4926 u8 ece[0x20]; 4927 }; 4928 4929 struct mlx5_ifc_rts2rts_qp_in_bits { 4930 u8 opcode[0x10]; 4931 u8 uid[0x10]; 4932 4933 u8 reserved_at_20[0x10]; 4934 u8 op_mod[0x10]; 4935 4936 u8 reserved_at_40[0x8]; 4937 u8 qpn[0x18]; 4938 4939 u8 reserved_at_60[0x20]; 4940 4941 u8 opt_param_mask[0x20]; 4942 4943 u8 ece[0x20]; 4944 4945 struct mlx5_ifc_qpc_bits qpc; 4946 4947 u8 reserved_at_800[0x80]; 4948 }; 4949 4950 struct mlx5_ifc_rtr2rts_qp_out_bits { 4951 u8 status[0x8]; 4952 u8 reserved_at_8[0x18]; 4953 4954 u8 syndrome[0x20]; 4955 4956 u8 reserved_at_40[0x20]; 4957 u8 ece[0x20]; 4958 }; 4959 4960 struct mlx5_ifc_rtr2rts_qp_in_bits { 4961 u8 opcode[0x10]; 4962 u8 uid[0x10]; 4963 4964 u8 reserved_at_20[0x10]; 4965 u8 op_mod[0x10]; 4966 4967 u8 reserved_at_40[0x8]; 4968 u8 qpn[0x18]; 4969 4970 u8 reserved_at_60[0x20]; 4971 4972 u8 opt_param_mask[0x20]; 4973 4974 u8 ece[0x20]; 4975 4976 struct mlx5_ifc_qpc_bits qpc; 4977 4978 u8 reserved_at_800[0x80]; 4979 }; 4980 4981 struct mlx5_ifc_rst2init_qp_out_bits { 4982 u8 status[0x8]; 4983 u8 reserved_at_8[0x18]; 4984 4985 u8 syndrome[0x20]; 4986 4987 u8 reserved_at_40[0x20]; 4988 u8 ece[0x20]; 4989 }; 4990 4991 struct mlx5_ifc_rst2init_qp_in_bits { 4992 u8 opcode[0x10]; 4993 u8 uid[0x10]; 4994 4995 u8 reserved_at_20[0x10]; 4996 u8 op_mod[0x10]; 4997 4998 u8 reserved_at_40[0x8]; 4999 u8 qpn[0x18]; 5000 5001 u8 reserved_at_60[0x20]; 5002 5003 u8 opt_param_mask[0x20]; 5004 5005 u8 ece[0x20]; 5006 5007 struct mlx5_ifc_qpc_bits qpc; 5008 5009 u8 reserved_at_800[0x80]; 5010 }; 5011 5012 struct mlx5_ifc_query_xrq_out_bits { 5013 u8 status[0x8]; 5014 u8 reserved_at_8[0x18]; 5015 5016 u8 syndrome[0x20]; 5017 5018 u8 reserved_at_40[0x40]; 5019 5020 struct mlx5_ifc_xrqc_bits xrq_context; 5021 }; 5022 5023 struct mlx5_ifc_query_xrq_in_bits { 5024 u8 opcode[0x10]; 5025 u8 reserved_at_10[0x10]; 5026 5027 u8 reserved_at_20[0x10]; 5028 u8 op_mod[0x10]; 5029 5030 u8 reserved_at_40[0x8]; 5031 u8 xrqn[0x18]; 5032 5033 u8 reserved_at_60[0x20]; 5034 }; 5035 5036 struct mlx5_ifc_query_xrc_srq_out_bits { 5037 u8 status[0x8]; 5038 u8 reserved_at_8[0x18]; 5039 5040 u8 syndrome[0x20]; 5041 5042 u8 reserved_at_40[0x40]; 5043 5044 struct mlx5_ifc_xrc_srqc_bits xrc_srq_context_entry; 5045 5046 u8 reserved_at_280[0x600]; 5047 5048 u8 pas[][0x40]; 5049 }; 5050 5051 struct mlx5_ifc_query_xrc_srq_in_bits { 5052 u8 opcode[0x10]; 5053 u8 reserved_at_10[0x10]; 5054 5055 u8 reserved_at_20[0x10]; 5056 u8 op_mod[0x10]; 5057 5058 u8 reserved_at_40[0x8]; 5059 u8 xrc_srqn[0x18]; 5060 5061 u8 reserved_at_60[0x20]; 5062 }; 5063 5064 enum { 5065 MLX5_QUERY_VPORT_STATE_OUT_STATE_DOWN = 0x0, 5066 MLX5_QUERY_VPORT_STATE_OUT_STATE_UP = 0x1, 5067 }; 5068 5069 struct mlx5_ifc_query_vport_state_out_bits { 5070 u8 status[0x8]; 5071 u8 reserved_at_8[0x18]; 5072 5073 u8 syndrome[0x20]; 5074 5075 u8 reserved_at_40[0x20]; 5076 5077 u8 reserved_at_60[0x18]; 5078 u8 admin_state[0x4]; 5079 u8 state[0x4]; 5080 }; 5081 5082 enum { 5083 MLX5_VPORT_STATE_OP_MOD_VNIC_VPORT = 0x0, 5084 MLX5_VPORT_STATE_OP_MOD_ESW_VPORT = 0x1, 5085 MLX5_VPORT_STATE_OP_MOD_UPLINK = 0x2, 5086 }; 5087 5088 struct mlx5_ifc_arm_monitor_counter_in_bits { 5089 u8 opcode[0x10]; 5090 u8 uid[0x10]; 5091 5092 u8 reserved_at_20[0x10]; 5093 u8 op_mod[0x10]; 5094 5095 u8 reserved_at_40[0x20]; 5096 5097 u8 reserved_at_60[0x20]; 5098 }; 5099 5100 struct mlx5_ifc_arm_monitor_counter_out_bits { 5101 u8 status[0x8]; 5102 u8 reserved_at_8[0x18]; 5103 5104 u8 syndrome[0x20]; 5105 5106 u8 reserved_at_40[0x40]; 5107 }; 5108 5109 enum { 5110 MLX5_QUERY_MONITOR_CNT_TYPE_PPCNT = 0x0, 5111 MLX5_QUERY_MONITOR_CNT_TYPE_Q_COUNTER = 0x1, 5112 }; 5113 5114 enum mlx5_monitor_counter_ppcnt { 5115 MLX5_QUERY_MONITOR_PPCNT_IN_RANGE_LENGTH_ERRORS = 0x0, 5116 MLX5_QUERY_MONITOR_PPCNT_OUT_OF_RANGE_LENGTH_FIELD = 0x1, 5117 MLX5_QUERY_MONITOR_PPCNT_FRAME_TOO_LONG_ERRORS = 0x2, 5118 MLX5_QUERY_MONITOR_PPCNT_FRAME_CHECK_SEQUENCE_ERRORS = 0x3, 5119 MLX5_QUERY_MONITOR_PPCNT_ALIGNMENT_ERRORS = 0x4, 5120 MLX5_QUERY_MONITOR_PPCNT_IF_OUT_DISCARDS = 0x5, 5121 }; 5122 5123 enum { 5124 MLX5_QUERY_MONITOR_Q_COUNTER_RX_OUT_OF_BUFFER = 0x4, 5125 }; 5126 5127 struct mlx5_ifc_monitor_counter_output_bits { 5128 u8 reserved_at_0[0x4]; 5129 u8 type[0x4]; 5130 u8 reserved_at_8[0x8]; 5131 u8 counter[0x10]; 5132 5133 u8 counter_group_id[0x20]; 5134 }; 5135 5136 #define MLX5_CMD_SET_MONITOR_NUM_PPCNT_COUNTER_SET1 (6) 5137 #define MLX5_CMD_SET_MONITOR_NUM_Q_COUNTERS_SET1 (1) 5138 #define MLX5_CMD_SET_MONITOR_NUM_COUNTER (MLX5_CMD_SET_MONITOR_NUM_PPCNT_COUNTER_SET1 +\ 5139 MLX5_CMD_SET_MONITOR_NUM_Q_COUNTERS_SET1) 5140 5141 struct mlx5_ifc_set_monitor_counter_in_bits { 5142 u8 opcode[0x10]; 5143 u8 uid[0x10]; 5144 5145 u8 reserved_at_20[0x10]; 5146 u8 op_mod[0x10]; 5147 5148 u8 reserved_at_40[0x10]; 5149 u8 num_of_counters[0x10]; 5150 5151 u8 reserved_at_60[0x20]; 5152 5153 struct mlx5_ifc_monitor_counter_output_bits monitor_counter[MLX5_CMD_SET_MONITOR_NUM_COUNTER]; 5154 }; 5155 5156 struct mlx5_ifc_set_monitor_counter_out_bits { 5157 u8 status[0x8]; 5158 u8 reserved_at_8[0x18]; 5159 5160 u8 syndrome[0x20]; 5161 5162 u8 reserved_at_40[0x40]; 5163 }; 5164 5165 struct mlx5_ifc_query_vport_state_in_bits { 5166 u8 opcode[0x10]; 5167 u8 reserved_at_10[0x10]; 5168 5169 u8 reserved_at_20[0x10]; 5170 u8 op_mod[0x10]; 5171 5172 u8 other_vport[0x1]; 5173 u8 reserved_at_41[0xf]; 5174 u8 vport_number[0x10]; 5175 5176 u8 reserved_at_60[0x20]; 5177 }; 5178 5179 struct mlx5_ifc_query_vnic_env_out_bits { 5180 u8 status[0x8]; 5181 u8 reserved_at_8[0x18]; 5182 5183 u8 syndrome[0x20]; 5184 5185 u8 reserved_at_40[0x40]; 5186 5187 struct mlx5_ifc_vnic_diagnostic_statistics_bits vport_env; 5188 }; 5189 5190 enum { 5191 MLX5_QUERY_VNIC_ENV_IN_OP_MOD_VPORT_DIAG_STATISTICS = 0x0, 5192 }; 5193 5194 struct mlx5_ifc_query_vnic_env_in_bits { 5195 u8 opcode[0x10]; 5196 u8 reserved_at_10[0x10]; 5197 5198 u8 reserved_at_20[0x10]; 5199 u8 op_mod[0x10]; 5200 5201 u8 other_vport[0x1]; 5202 u8 reserved_at_41[0xf]; 5203 u8 vport_number[0x10]; 5204 5205 u8 reserved_at_60[0x20]; 5206 }; 5207 5208 struct mlx5_ifc_query_vport_counter_out_bits { 5209 u8 status[0x8]; 5210 u8 reserved_at_8[0x18]; 5211 5212 u8 syndrome[0x20]; 5213 5214 u8 reserved_at_40[0x40]; 5215 5216 struct mlx5_ifc_traffic_counter_bits received_errors; 5217 5218 struct mlx5_ifc_traffic_counter_bits transmit_errors; 5219 5220 struct mlx5_ifc_traffic_counter_bits received_ib_unicast; 5221 5222 struct mlx5_ifc_traffic_counter_bits transmitted_ib_unicast; 5223 5224 struct mlx5_ifc_traffic_counter_bits received_ib_multicast; 5225 5226 struct mlx5_ifc_traffic_counter_bits transmitted_ib_multicast; 5227 5228 struct mlx5_ifc_traffic_counter_bits received_eth_broadcast; 5229 5230 struct mlx5_ifc_traffic_counter_bits transmitted_eth_broadcast; 5231 5232 struct mlx5_ifc_traffic_counter_bits received_eth_unicast; 5233 5234 struct mlx5_ifc_traffic_counter_bits transmitted_eth_unicast; 5235 5236 struct mlx5_ifc_traffic_counter_bits received_eth_multicast; 5237 5238 struct mlx5_ifc_traffic_counter_bits transmitted_eth_multicast; 5239 5240 struct mlx5_ifc_traffic_counter_bits local_loopback; 5241 5242 u8 reserved_at_700[0x980]; 5243 }; 5244 5245 enum { 5246 MLX5_QUERY_VPORT_COUNTER_IN_OP_MOD_VPORT_COUNTERS = 0x0, 5247 }; 5248 5249 struct mlx5_ifc_query_vport_counter_in_bits { 5250 u8 opcode[0x10]; 5251 u8 reserved_at_10[0x10]; 5252 5253 u8 reserved_at_20[0x10]; 5254 u8 op_mod[0x10]; 5255 5256 u8 other_vport[0x1]; 5257 u8 reserved_at_41[0xb]; 5258 u8 port_num[0x4]; 5259 u8 vport_number[0x10]; 5260 5261 u8 reserved_at_60[0x60]; 5262 5263 u8 clear[0x1]; 5264 u8 reserved_at_c1[0x1f]; 5265 5266 u8 reserved_at_e0[0x20]; 5267 }; 5268 5269 struct mlx5_ifc_query_tis_out_bits { 5270 u8 status[0x8]; 5271 u8 reserved_at_8[0x18]; 5272 5273 u8 syndrome[0x20]; 5274 5275 u8 reserved_at_40[0x40]; 5276 5277 struct mlx5_ifc_tisc_bits tis_context; 5278 }; 5279 5280 struct mlx5_ifc_query_tis_in_bits { 5281 u8 opcode[0x10]; 5282 u8 reserved_at_10[0x10]; 5283 5284 u8 reserved_at_20[0x10]; 5285 u8 op_mod[0x10]; 5286 5287 u8 reserved_at_40[0x8]; 5288 u8 tisn[0x18]; 5289 5290 u8 reserved_at_60[0x20]; 5291 }; 5292 5293 struct mlx5_ifc_query_tir_out_bits { 5294 u8 status[0x8]; 5295 u8 reserved_at_8[0x18]; 5296 5297 u8 syndrome[0x20]; 5298 5299 u8 reserved_at_40[0xc0]; 5300 5301 struct mlx5_ifc_tirc_bits tir_context; 5302 }; 5303 5304 struct mlx5_ifc_query_tir_in_bits { 5305 u8 opcode[0x10]; 5306 u8 reserved_at_10[0x10]; 5307 5308 u8 reserved_at_20[0x10]; 5309 u8 op_mod[0x10]; 5310 5311 u8 reserved_at_40[0x8]; 5312 u8 tirn[0x18]; 5313 5314 u8 reserved_at_60[0x20]; 5315 }; 5316 5317 struct mlx5_ifc_query_srq_out_bits { 5318 u8 status[0x8]; 5319 u8 reserved_at_8[0x18]; 5320 5321 u8 syndrome[0x20]; 5322 5323 u8 reserved_at_40[0x40]; 5324 5325 struct mlx5_ifc_srqc_bits srq_context_entry; 5326 5327 u8 reserved_at_280[0x600]; 5328 5329 u8 pas[][0x40]; 5330 }; 5331 5332 struct mlx5_ifc_query_srq_in_bits { 5333 u8 opcode[0x10]; 5334 u8 reserved_at_10[0x10]; 5335 5336 u8 reserved_at_20[0x10]; 5337 u8 op_mod[0x10]; 5338 5339 u8 reserved_at_40[0x8]; 5340 u8 srqn[0x18]; 5341 5342 u8 reserved_at_60[0x20]; 5343 }; 5344 5345 struct mlx5_ifc_query_sq_out_bits { 5346 u8 status[0x8]; 5347 u8 reserved_at_8[0x18]; 5348 5349 u8 syndrome[0x20]; 5350 5351 u8 reserved_at_40[0xc0]; 5352 5353 struct mlx5_ifc_sqc_bits sq_context; 5354 }; 5355 5356 struct mlx5_ifc_query_sq_in_bits { 5357 u8 opcode[0x10]; 5358 u8 reserved_at_10[0x10]; 5359 5360 u8 reserved_at_20[0x10]; 5361 u8 op_mod[0x10]; 5362 5363 u8 reserved_at_40[0x8]; 5364 u8 sqn[0x18]; 5365 5366 u8 reserved_at_60[0x20]; 5367 }; 5368 5369 struct mlx5_ifc_query_special_contexts_out_bits { 5370 u8 status[0x8]; 5371 u8 reserved_at_8[0x18]; 5372 5373 u8 syndrome[0x20]; 5374 5375 u8 dump_fill_mkey[0x20]; 5376 5377 u8 resd_lkey[0x20]; 5378 5379 u8 null_mkey[0x20]; 5380 5381 u8 terminate_scatter_list_mkey[0x20]; 5382 5383 u8 repeated_mkey[0x20]; 5384 5385 u8 reserved_at_a0[0x20]; 5386 }; 5387 5388 struct mlx5_ifc_query_special_contexts_in_bits { 5389 u8 opcode[0x10]; 5390 u8 reserved_at_10[0x10]; 5391 5392 u8 reserved_at_20[0x10]; 5393 u8 op_mod[0x10]; 5394 5395 u8 reserved_at_40[0x40]; 5396 }; 5397 5398 struct mlx5_ifc_query_scheduling_element_out_bits { 5399 u8 opcode[0x10]; 5400 u8 reserved_at_10[0x10]; 5401 5402 u8 reserved_at_20[0x10]; 5403 u8 op_mod[0x10]; 5404 5405 u8 reserved_at_40[0xc0]; 5406 5407 struct mlx5_ifc_scheduling_context_bits scheduling_context; 5408 5409 u8 reserved_at_300[0x100]; 5410 }; 5411 5412 enum { 5413 SCHEDULING_HIERARCHY_E_SWITCH = 0x2, 5414 SCHEDULING_HIERARCHY_NIC = 0x3, 5415 }; 5416 5417 struct mlx5_ifc_query_scheduling_element_in_bits { 5418 u8 opcode[0x10]; 5419 u8 reserved_at_10[0x10]; 5420 5421 u8 reserved_at_20[0x10]; 5422 u8 op_mod[0x10]; 5423 5424 u8 scheduling_hierarchy[0x8]; 5425 u8 reserved_at_48[0x18]; 5426 5427 u8 scheduling_element_id[0x20]; 5428 5429 u8 reserved_at_80[0x180]; 5430 }; 5431 5432 struct mlx5_ifc_query_rqt_out_bits { 5433 u8 status[0x8]; 5434 u8 reserved_at_8[0x18]; 5435 5436 u8 syndrome[0x20]; 5437 5438 u8 reserved_at_40[0xc0]; 5439 5440 struct mlx5_ifc_rqtc_bits rqt_context; 5441 }; 5442 5443 struct mlx5_ifc_query_rqt_in_bits { 5444 u8 opcode[0x10]; 5445 u8 reserved_at_10[0x10]; 5446 5447 u8 reserved_at_20[0x10]; 5448 u8 op_mod[0x10]; 5449 5450 u8 reserved_at_40[0x8]; 5451 u8 rqtn[0x18]; 5452 5453 u8 reserved_at_60[0x20]; 5454 }; 5455 5456 struct mlx5_ifc_query_rq_out_bits { 5457 u8 status[0x8]; 5458 u8 reserved_at_8[0x18]; 5459 5460 u8 syndrome[0x20]; 5461 5462 u8 reserved_at_40[0xc0]; 5463 5464 struct mlx5_ifc_rqc_bits rq_context; 5465 }; 5466 5467 struct mlx5_ifc_query_rq_in_bits { 5468 u8 opcode[0x10]; 5469 u8 reserved_at_10[0x10]; 5470 5471 u8 reserved_at_20[0x10]; 5472 u8 op_mod[0x10]; 5473 5474 u8 reserved_at_40[0x8]; 5475 u8 rqn[0x18]; 5476 5477 u8 reserved_at_60[0x20]; 5478 }; 5479 5480 struct mlx5_ifc_query_roce_address_out_bits { 5481 u8 status[0x8]; 5482 u8 reserved_at_8[0x18]; 5483 5484 u8 syndrome[0x20]; 5485 5486 u8 reserved_at_40[0x40]; 5487 5488 struct mlx5_ifc_roce_addr_layout_bits roce_address; 5489 }; 5490 5491 struct mlx5_ifc_query_roce_address_in_bits { 5492 u8 opcode[0x10]; 5493 u8 reserved_at_10[0x10]; 5494 5495 u8 reserved_at_20[0x10]; 5496 u8 op_mod[0x10]; 5497 5498 u8 roce_address_index[0x10]; 5499 u8 reserved_at_50[0xc]; 5500 u8 vhca_port_num[0x4]; 5501 5502 u8 reserved_at_60[0x20]; 5503 }; 5504 5505 struct mlx5_ifc_query_rmp_out_bits { 5506 u8 status[0x8]; 5507 u8 reserved_at_8[0x18]; 5508 5509 u8 syndrome[0x20]; 5510 5511 u8 reserved_at_40[0xc0]; 5512 5513 struct mlx5_ifc_rmpc_bits rmp_context; 5514 }; 5515 5516 struct mlx5_ifc_query_rmp_in_bits { 5517 u8 opcode[0x10]; 5518 u8 reserved_at_10[0x10]; 5519 5520 u8 reserved_at_20[0x10]; 5521 u8 op_mod[0x10]; 5522 5523 u8 reserved_at_40[0x8]; 5524 u8 rmpn[0x18]; 5525 5526 u8 reserved_at_60[0x20]; 5527 }; 5528 5529 struct mlx5_ifc_cqe_error_syndrome_bits { 5530 u8 hw_error_syndrome[0x8]; 5531 u8 hw_syndrome_type[0x4]; 5532 u8 reserved_at_c[0x4]; 5533 u8 vendor_error_syndrome[0x8]; 5534 u8 syndrome[0x8]; 5535 }; 5536 5537 struct mlx5_ifc_qp_context_extension_bits { 5538 u8 reserved_at_0[0x60]; 5539 5540 struct mlx5_ifc_cqe_error_syndrome_bits error_syndrome; 5541 5542 u8 reserved_at_80[0x580]; 5543 }; 5544 5545 struct mlx5_ifc_qpc_extension_and_pas_list_in_bits { 5546 struct mlx5_ifc_qp_context_extension_bits qpc_data_extension; 5547 5548 u8 pas[0][0x40]; 5549 }; 5550 5551 struct mlx5_ifc_qp_pas_list_in_bits { 5552 struct mlx5_ifc_cmd_pas_bits pas[0]; 5553 }; 5554 5555 union mlx5_ifc_qp_pas_or_qpc_ext_and_pas_bits { 5556 struct mlx5_ifc_qp_pas_list_in_bits qp_pas_list; 5557 struct mlx5_ifc_qpc_extension_and_pas_list_in_bits qpc_ext_and_pas_list; 5558 }; 5559 5560 struct mlx5_ifc_query_qp_out_bits { 5561 u8 status[0x8]; 5562 u8 reserved_at_8[0x18]; 5563 5564 u8 syndrome[0x20]; 5565 5566 u8 reserved_at_40[0x40]; 5567 5568 u8 opt_param_mask[0x20]; 5569 5570 u8 ece[0x20]; 5571 5572 struct mlx5_ifc_qpc_bits qpc; 5573 5574 u8 reserved_at_800[0x80]; 5575 5576 union mlx5_ifc_qp_pas_or_qpc_ext_and_pas_bits qp_pas_or_qpc_ext_and_pas; 5577 }; 5578 5579 struct mlx5_ifc_query_qp_in_bits { 5580 u8 opcode[0x10]; 5581 u8 reserved_at_10[0x10]; 5582 5583 u8 reserved_at_20[0x10]; 5584 u8 op_mod[0x10]; 5585 5586 u8 qpc_ext[0x1]; 5587 u8 reserved_at_41[0x7]; 5588 u8 qpn[0x18]; 5589 5590 u8 reserved_at_60[0x20]; 5591 }; 5592 5593 struct mlx5_ifc_query_q_counter_out_bits { 5594 u8 status[0x8]; 5595 u8 reserved_at_8[0x18]; 5596 5597 u8 syndrome[0x20]; 5598 5599 u8 reserved_at_40[0x40]; 5600 5601 u8 rx_write_requests[0x20]; 5602 5603 u8 reserved_at_a0[0x20]; 5604 5605 u8 rx_read_requests[0x20]; 5606 5607 u8 reserved_at_e0[0x20]; 5608 5609 u8 rx_atomic_requests[0x20]; 5610 5611 u8 reserved_at_120[0x20]; 5612 5613 u8 rx_dct_connect[0x20]; 5614 5615 u8 reserved_at_160[0x20]; 5616 5617 u8 out_of_buffer[0x20]; 5618 5619 u8 reserved_at_1a0[0x20]; 5620 5621 u8 out_of_sequence[0x20]; 5622 5623 u8 reserved_at_1e0[0x20]; 5624 5625 u8 duplicate_request[0x20]; 5626 5627 u8 reserved_at_220[0x20]; 5628 5629 u8 rnr_nak_retry_err[0x20]; 5630 5631 u8 reserved_at_260[0x20]; 5632 5633 u8 packet_seq_err[0x20]; 5634 5635 u8 reserved_at_2a0[0x20]; 5636 5637 u8 implied_nak_seq_err[0x20]; 5638 5639 u8 reserved_at_2e0[0x20]; 5640 5641 u8 local_ack_timeout_err[0x20]; 5642 5643 u8 reserved_at_320[0xa0]; 5644 5645 u8 resp_local_length_error[0x20]; 5646 5647 u8 req_local_length_error[0x20]; 5648 5649 u8 resp_local_qp_error[0x20]; 5650 5651 u8 local_operation_error[0x20]; 5652 5653 u8 resp_local_protection[0x20]; 5654 5655 u8 req_local_protection[0x20]; 5656 5657 u8 resp_cqe_error[0x20]; 5658 5659 u8 req_cqe_error[0x20]; 5660 5661 u8 req_mw_binding[0x20]; 5662 5663 u8 req_bad_response[0x20]; 5664 5665 u8 req_remote_invalid_request[0x20]; 5666 5667 u8 resp_remote_invalid_request[0x20]; 5668 5669 u8 req_remote_access_errors[0x20]; 5670 5671 u8 resp_remote_access_errors[0x20]; 5672 5673 u8 req_remote_operation_errors[0x20]; 5674 5675 u8 req_transport_retries_exceeded[0x20]; 5676 5677 u8 cq_overflow[0x20]; 5678 5679 u8 resp_cqe_flush_error[0x20]; 5680 5681 u8 req_cqe_flush_error[0x20]; 5682 5683 u8 reserved_at_620[0x20]; 5684 5685 u8 roce_adp_retrans[0x20]; 5686 5687 u8 roce_adp_retrans_to[0x20]; 5688 5689 u8 roce_slow_restart[0x20]; 5690 5691 u8 roce_slow_restart_cnps[0x20]; 5692 5693 u8 roce_slow_restart_trans[0x20]; 5694 5695 u8 reserved_at_6e0[0x120]; 5696 }; 5697 5698 struct mlx5_ifc_query_q_counter_in_bits { 5699 u8 opcode[0x10]; 5700 u8 reserved_at_10[0x10]; 5701 5702 u8 reserved_at_20[0x10]; 5703 u8 op_mod[0x10]; 5704 5705 u8 other_vport[0x1]; 5706 u8 reserved_at_41[0xf]; 5707 u8 vport_number[0x10]; 5708 5709 u8 reserved_at_60[0x60]; 5710 5711 u8 clear[0x1]; 5712 u8 aggregate[0x1]; 5713 u8 reserved_at_c2[0x1e]; 5714 5715 u8 reserved_at_e0[0x18]; 5716 u8 counter_set_id[0x8]; 5717 }; 5718 5719 struct mlx5_ifc_query_pages_out_bits { 5720 u8 status[0x8]; 5721 u8 reserved_at_8[0x18]; 5722 5723 u8 syndrome[0x20]; 5724 5725 u8 embedded_cpu_function[0x1]; 5726 u8 reserved_at_41[0xf]; 5727 u8 function_id[0x10]; 5728 5729 u8 num_pages[0x20]; 5730 }; 5731 5732 enum { 5733 MLX5_QUERY_PAGES_IN_OP_MOD_BOOT_PAGES = 0x1, 5734 MLX5_QUERY_PAGES_IN_OP_MOD_INIT_PAGES = 0x2, 5735 MLX5_QUERY_PAGES_IN_OP_MOD_REGULAR_PAGES = 0x3, 5736 }; 5737 5738 struct mlx5_ifc_query_pages_in_bits { 5739 u8 opcode[0x10]; 5740 u8 reserved_at_10[0x10]; 5741 5742 u8 reserved_at_20[0x10]; 5743 u8 op_mod[0x10]; 5744 5745 u8 embedded_cpu_function[0x1]; 5746 u8 reserved_at_41[0xf]; 5747 u8 function_id[0x10]; 5748 5749 u8 reserved_at_60[0x20]; 5750 }; 5751 5752 struct mlx5_ifc_query_nic_vport_context_out_bits { 5753 u8 status[0x8]; 5754 u8 reserved_at_8[0x18]; 5755 5756 u8 syndrome[0x20]; 5757 5758 u8 reserved_at_40[0x40]; 5759 5760 struct mlx5_ifc_nic_vport_context_bits nic_vport_context; 5761 }; 5762 5763 struct mlx5_ifc_query_nic_vport_context_in_bits { 5764 u8 opcode[0x10]; 5765 u8 reserved_at_10[0x10]; 5766 5767 u8 reserved_at_20[0x10]; 5768 u8 op_mod[0x10]; 5769 5770 u8 other_vport[0x1]; 5771 u8 reserved_at_41[0xf]; 5772 u8 vport_number[0x10]; 5773 5774 u8 reserved_at_60[0x5]; 5775 u8 allowed_list_type[0x3]; 5776 u8 reserved_at_68[0x18]; 5777 }; 5778 5779 struct mlx5_ifc_query_mkey_out_bits { 5780 u8 status[0x8]; 5781 u8 reserved_at_8[0x18]; 5782 5783 u8 syndrome[0x20]; 5784 5785 u8 reserved_at_40[0x40]; 5786 5787 struct mlx5_ifc_mkc_bits memory_key_mkey_entry; 5788 5789 u8 reserved_at_280[0x600]; 5790 5791 u8 bsf0_klm0_pas_mtt0_1[16][0x8]; 5792 5793 u8 bsf1_klm1_pas_mtt2_3[16][0x8]; 5794 }; 5795 5796 struct mlx5_ifc_query_mkey_in_bits { 5797 u8 opcode[0x10]; 5798 u8 reserved_at_10[0x10]; 5799 5800 u8 reserved_at_20[0x10]; 5801 u8 op_mod[0x10]; 5802 5803 u8 reserved_at_40[0x8]; 5804 u8 mkey_index[0x18]; 5805 5806 u8 pg_access[0x1]; 5807 u8 reserved_at_61[0x1f]; 5808 }; 5809 5810 struct mlx5_ifc_query_mad_demux_out_bits { 5811 u8 status[0x8]; 5812 u8 reserved_at_8[0x18]; 5813 5814 u8 syndrome[0x20]; 5815 5816 u8 reserved_at_40[0x40]; 5817 5818 u8 mad_dumux_parameters_block[0x20]; 5819 }; 5820 5821 struct mlx5_ifc_query_mad_demux_in_bits { 5822 u8 opcode[0x10]; 5823 u8 reserved_at_10[0x10]; 5824 5825 u8 reserved_at_20[0x10]; 5826 u8 op_mod[0x10]; 5827 5828 u8 reserved_at_40[0x40]; 5829 }; 5830 5831 struct mlx5_ifc_query_l2_table_entry_out_bits { 5832 u8 status[0x8]; 5833 u8 reserved_at_8[0x18]; 5834 5835 u8 syndrome[0x20]; 5836 5837 u8 reserved_at_40[0xa0]; 5838 5839 u8 reserved_at_e0[0x13]; 5840 u8 vlan_valid[0x1]; 5841 u8 vlan[0xc]; 5842 5843 struct mlx5_ifc_mac_address_layout_bits mac_address; 5844 5845 u8 reserved_at_140[0xc0]; 5846 }; 5847 5848 struct mlx5_ifc_query_l2_table_entry_in_bits { 5849 u8 opcode[0x10]; 5850 u8 reserved_at_10[0x10]; 5851 5852 u8 reserved_at_20[0x10]; 5853 u8 op_mod[0x10]; 5854 5855 u8 reserved_at_40[0x60]; 5856 5857 u8 reserved_at_a0[0x8]; 5858 u8 table_index[0x18]; 5859 5860 u8 reserved_at_c0[0x140]; 5861 }; 5862 5863 struct mlx5_ifc_query_issi_out_bits { 5864 u8 status[0x8]; 5865 u8 reserved_at_8[0x18]; 5866 5867 u8 syndrome[0x20]; 5868 5869 u8 reserved_at_40[0x10]; 5870 u8 current_issi[0x10]; 5871 5872 u8 reserved_at_60[0xa0]; 5873 5874 u8 reserved_at_100[76][0x8]; 5875 u8 supported_issi_dw0[0x20]; 5876 }; 5877 5878 struct mlx5_ifc_query_issi_in_bits { 5879 u8 opcode[0x10]; 5880 u8 reserved_at_10[0x10]; 5881 5882 u8 reserved_at_20[0x10]; 5883 u8 op_mod[0x10]; 5884 5885 u8 reserved_at_40[0x40]; 5886 }; 5887 5888 struct mlx5_ifc_set_driver_version_out_bits { 5889 u8 status[0x8]; 5890 u8 reserved_0[0x18]; 5891 5892 u8 syndrome[0x20]; 5893 u8 reserved_1[0x40]; 5894 }; 5895 5896 struct mlx5_ifc_set_driver_version_in_bits { 5897 u8 opcode[0x10]; 5898 u8 reserved_0[0x10]; 5899 5900 u8 reserved_1[0x10]; 5901 u8 op_mod[0x10]; 5902 5903 u8 reserved_2[0x40]; 5904 u8 driver_version[64][0x8]; 5905 }; 5906 5907 struct mlx5_ifc_query_hca_vport_pkey_out_bits { 5908 u8 status[0x8]; 5909 u8 reserved_at_8[0x18]; 5910 5911 u8 syndrome[0x20]; 5912 5913 u8 reserved_at_40[0x40]; 5914 5915 struct mlx5_ifc_pkey_bits pkey[]; 5916 }; 5917 5918 struct mlx5_ifc_query_hca_vport_pkey_in_bits { 5919 u8 opcode[0x10]; 5920 u8 reserved_at_10[0x10]; 5921 5922 u8 reserved_at_20[0x10]; 5923 u8 op_mod[0x10]; 5924 5925 u8 other_vport[0x1]; 5926 u8 reserved_at_41[0xb]; 5927 u8 port_num[0x4]; 5928 u8 vport_number[0x10]; 5929 5930 u8 reserved_at_60[0x10]; 5931 u8 pkey_index[0x10]; 5932 }; 5933 5934 enum { 5935 MLX5_HCA_VPORT_SEL_PORT_GUID = 1 << 0, 5936 MLX5_HCA_VPORT_SEL_NODE_GUID = 1 << 1, 5937 MLX5_HCA_VPORT_SEL_STATE_POLICY = 1 << 2, 5938 }; 5939 5940 struct mlx5_ifc_query_hca_vport_gid_out_bits { 5941 u8 status[0x8]; 5942 u8 reserved_at_8[0x18]; 5943 5944 u8 syndrome[0x20]; 5945 5946 u8 reserved_at_40[0x20]; 5947 5948 u8 gids_num[0x10]; 5949 u8 reserved_at_70[0x10]; 5950 5951 struct mlx5_ifc_array128_auto_bits gid[]; 5952 }; 5953 5954 struct mlx5_ifc_query_hca_vport_gid_in_bits { 5955 u8 opcode[0x10]; 5956 u8 reserved_at_10[0x10]; 5957 5958 u8 reserved_at_20[0x10]; 5959 u8 op_mod[0x10]; 5960 5961 u8 other_vport[0x1]; 5962 u8 reserved_at_41[0xb]; 5963 u8 port_num[0x4]; 5964 u8 vport_number[0x10]; 5965 5966 u8 reserved_at_60[0x10]; 5967 u8 gid_index[0x10]; 5968 }; 5969 5970 struct mlx5_ifc_query_hca_vport_context_out_bits { 5971 u8 status[0x8]; 5972 u8 reserved_at_8[0x18]; 5973 5974 u8 syndrome[0x20]; 5975 5976 u8 reserved_at_40[0x40]; 5977 5978 struct mlx5_ifc_hca_vport_context_bits hca_vport_context; 5979 }; 5980 5981 struct mlx5_ifc_query_hca_vport_context_in_bits { 5982 u8 opcode[0x10]; 5983 u8 reserved_at_10[0x10]; 5984 5985 u8 reserved_at_20[0x10]; 5986 u8 op_mod[0x10]; 5987 5988 u8 other_vport[0x1]; 5989 u8 reserved_at_41[0xb]; 5990 u8 port_num[0x4]; 5991 u8 vport_number[0x10]; 5992 5993 u8 reserved_at_60[0x20]; 5994 }; 5995 5996 struct mlx5_ifc_query_hca_cap_out_bits { 5997 u8 status[0x8]; 5998 u8 reserved_at_8[0x18]; 5999 6000 u8 syndrome[0x20]; 6001 6002 u8 reserved_at_40[0x40]; 6003 6004 union mlx5_ifc_hca_cap_union_bits capability; 6005 }; 6006 6007 struct mlx5_ifc_query_hca_cap_in_bits { 6008 u8 opcode[0x10]; 6009 u8 reserved_at_10[0x10]; 6010 6011 u8 reserved_at_20[0x10]; 6012 u8 op_mod[0x10]; 6013 6014 u8 other_function[0x1]; 6015 u8 ec_vf_function[0x1]; 6016 u8 reserved_at_42[0xe]; 6017 u8 function_id[0x10]; 6018 6019 u8 reserved_at_60[0x20]; 6020 }; 6021 6022 struct mlx5_ifc_other_hca_cap_bits { 6023 u8 roce[0x1]; 6024 u8 reserved_at_1[0x27f]; 6025 }; 6026 6027 struct mlx5_ifc_query_other_hca_cap_out_bits { 6028 u8 status[0x8]; 6029 u8 reserved_at_8[0x18]; 6030 6031 u8 syndrome[0x20]; 6032 6033 u8 reserved_at_40[0x40]; 6034 6035 struct mlx5_ifc_other_hca_cap_bits other_capability; 6036 }; 6037 6038 struct mlx5_ifc_query_other_hca_cap_in_bits { 6039 u8 opcode[0x10]; 6040 u8 reserved_at_10[0x10]; 6041 6042 u8 reserved_at_20[0x10]; 6043 u8 op_mod[0x10]; 6044 6045 u8 reserved_at_40[0x10]; 6046 u8 function_id[0x10]; 6047 6048 u8 reserved_at_60[0x20]; 6049 }; 6050 6051 struct mlx5_ifc_modify_other_hca_cap_out_bits { 6052 u8 status[0x8]; 6053 u8 reserved_at_8[0x18]; 6054 6055 u8 syndrome[0x20]; 6056 6057 u8 reserved_at_40[0x40]; 6058 }; 6059 6060 struct mlx5_ifc_modify_other_hca_cap_in_bits { 6061 u8 opcode[0x10]; 6062 u8 reserved_at_10[0x10]; 6063 6064 u8 reserved_at_20[0x10]; 6065 u8 op_mod[0x10]; 6066 6067 u8 reserved_at_40[0x10]; 6068 u8 function_id[0x10]; 6069 u8 field_select[0x20]; 6070 6071 struct mlx5_ifc_other_hca_cap_bits other_capability; 6072 }; 6073 6074 struct mlx5_ifc_flow_table_context_bits { 6075 u8 reformat_en[0x1]; 6076 u8 decap_en[0x1]; 6077 u8 sw_owner[0x1]; 6078 u8 termination_table[0x1]; 6079 u8 table_miss_action[0x4]; 6080 u8 level[0x8]; 6081 u8 reserved_at_10[0x8]; 6082 u8 log_size[0x8]; 6083 6084 u8 reserved_at_20[0x8]; 6085 u8 table_miss_id[0x18]; 6086 6087 u8 reserved_at_40[0x8]; 6088 u8 lag_master_next_table_id[0x18]; 6089 6090 u8 reserved_at_60[0x60]; 6091 6092 u8 sw_owner_icm_root_1[0x40]; 6093 6094 u8 sw_owner_icm_root_0[0x40]; 6095 6096 }; 6097 6098 struct mlx5_ifc_query_flow_table_out_bits { 6099 u8 status[0x8]; 6100 u8 reserved_at_8[0x18]; 6101 6102 u8 syndrome[0x20]; 6103 6104 u8 reserved_at_40[0x80]; 6105 6106 struct mlx5_ifc_flow_table_context_bits flow_table_context; 6107 }; 6108 6109 struct mlx5_ifc_query_flow_table_in_bits { 6110 u8 opcode[0x10]; 6111 u8 reserved_at_10[0x10]; 6112 6113 u8 reserved_at_20[0x10]; 6114 u8 op_mod[0x10]; 6115 6116 u8 reserved_at_40[0x40]; 6117 6118 u8 table_type[0x8]; 6119 u8 reserved_at_88[0x18]; 6120 6121 u8 reserved_at_a0[0x8]; 6122 u8 table_id[0x18]; 6123 6124 u8 reserved_at_c0[0x140]; 6125 }; 6126 6127 struct mlx5_ifc_query_fte_out_bits { 6128 u8 status[0x8]; 6129 u8 reserved_at_8[0x18]; 6130 6131 u8 syndrome[0x20]; 6132 6133 u8 reserved_at_40[0x1c0]; 6134 6135 struct mlx5_ifc_flow_context_bits flow_context; 6136 }; 6137 6138 struct mlx5_ifc_query_fte_in_bits { 6139 u8 opcode[0x10]; 6140 u8 reserved_at_10[0x10]; 6141 6142 u8 reserved_at_20[0x10]; 6143 u8 op_mod[0x10]; 6144 6145 u8 reserved_at_40[0x40]; 6146 6147 u8 table_type[0x8]; 6148 u8 reserved_at_88[0x18]; 6149 6150 u8 reserved_at_a0[0x8]; 6151 u8 table_id[0x18]; 6152 6153 u8 reserved_at_c0[0x40]; 6154 6155 u8 flow_index[0x20]; 6156 6157 u8 reserved_at_120[0xe0]; 6158 }; 6159 6160 struct mlx5_ifc_match_definer_format_0_bits { 6161 u8 reserved_at_0[0x100]; 6162 6163 u8 metadata_reg_c_0[0x20]; 6164 6165 u8 metadata_reg_c_1[0x20]; 6166 6167 u8 outer_dmac_47_16[0x20]; 6168 6169 u8 outer_dmac_15_0[0x10]; 6170 u8 outer_ethertype[0x10]; 6171 6172 u8 reserved_at_180[0x1]; 6173 u8 sx_sniffer[0x1]; 6174 u8 functional_lb[0x1]; 6175 u8 outer_ip_frag[0x1]; 6176 u8 outer_qp_type[0x2]; 6177 u8 outer_encap_type[0x2]; 6178 u8 port_number[0x2]; 6179 u8 outer_l3_type[0x2]; 6180 u8 outer_l4_type[0x2]; 6181 u8 outer_first_vlan_type[0x2]; 6182 u8 outer_first_vlan_prio[0x3]; 6183 u8 outer_first_vlan_cfi[0x1]; 6184 u8 outer_first_vlan_vid[0xc]; 6185 6186 u8 outer_l4_type_ext[0x4]; 6187 u8 reserved_at_1a4[0x2]; 6188 u8 outer_ipsec_layer[0x2]; 6189 u8 outer_l2_type[0x2]; 6190 u8 force_lb[0x1]; 6191 u8 outer_l2_ok[0x1]; 6192 u8 outer_l3_ok[0x1]; 6193 u8 outer_l4_ok[0x1]; 6194 u8 outer_second_vlan_type[0x2]; 6195 u8 outer_second_vlan_prio[0x3]; 6196 u8 outer_second_vlan_cfi[0x1]; 6197 u8 outer_second_vlan_vid[0xc]; 6198 6199 u8 outer_smac_47_16[0x20]; 6200 6201 u8 outer_smac_15_0[0x10]; 6202 u8 inner_ipv4_checksum_ok[0x1]; 6203 u8 inner_l4_checksum_ok[0x1]; 6204 u8 outer_ipv4_checksum_ok[0x1]; 6205 u8 outer_l4_checksum_ok[0x1]; 6206 u8 inner_l3_ok[0x1]; 6207 u8 inner_l4_ok[0x1]; 6208 u8 outer_l3_ok_duplicate[0x1]; 6209 u8 outer_l4_ok_duplicate[0x1]; 6210 u8 outer_tcp_cwr[0x1]; 6211 u8 outer_tcp_ece[0x1]; 6212 u8 outer_tcp_urg[0x1]; 6213 u8 outer_tcp_ack[0x1]; 6214 u8 outer_tcp_psh[0x1]; 6215 u8 outer_tcp_rst[0x1]; 6216 u8 outer_tcp_syn[0x1]; 6217 u8 outer_tcp_fin[0x1]; 6218 }; 6219 6220 struct mlx5_ifc_match_definer_format_22_bits { 6221 u8 reserved_at_0[0x100]; 6222 6223 u8 outer_ip_src_addr[0x20]; 6224 6225 u8 outer_ip_dest_addr[0x20]; 6226 6227 u8 outer_l4_sport[0x10]; 6228 u8 outer_l4_dport[0x10]; 6229 6230 u8 reserved_at_160[0x1]; 6231 u8 sx_sniffer[0x1]; 6232 u8 functional_lb[0x1]; 6233 u8 outer_ip_frag[0x1]; 6234 u8 outer_qp_type[0x2]; 6235 u8 outer_encap_type[0x2]; 6236 u8 port_number[0x2]; 6237 u8 outer_l3_type[0x2]; 6238 u8 outer_l4_type[0x2]; 6239 u8 outer_first_vlan_type[0x2]; 6240 u8 outer_first_vlan_prio[0x3]; 6241 u8 outer_first_vlan_cfi[0x1]; 6242 u8 outer_first_vlan_vid[0xc]; 6243 6244 u8 metadata_reg_c_0[0x20]; 6245 6246 u8 outer_dmac_47_16[0x20]; 6247 6248 u8 outer_smac_47_16[0x20]; 6249 6250 u8 outer_smac_15_0[0x10]; 6251 u8 outer_dmac_15_0[0x10]; 6252 }; 6253 6254 struct mlx5_ifc_match_definer_format_23_bits { 6255 u8 reserved_at_0[0x100]; 6256 6257 u8 inner_ip_src_addr[0x20]; 6258 6259 u8 inner_ip_dest_addr[0x20]; 6260 6261 u8 inner_l4_sport[0x10]; 6262 u8 inner_l4_dport[0x10]; 6263 6264 u8 reserved_at_160[0x1]; 6265 u8 sx_sniffer[0x1]; 6266 u8 functional_lb[0x1]; 6267 u8 inner_ip_frag[0x1]; 6268 u8 inner_qp_type[0x2]; 6269 u8 inner_encap_type[0x2]; 6270 u8 port_number[0x2]; 6271 u8 inner_l3_type[0x2]; 6272 u8 inner_l4_type[0x2]; 6273 u8 inner_first_vlan_type[0x2]; 6274 u8 inner_first_vlan_prio[0x3]; 6275 u8 inner_first_vlan_cfi[0x1]; 6276 u8 inner_first_vlan_vid[0xc]; 6277 6278 u8 tunnel_header_0[0x20]; 6279 6280 u8 inner_dmac_47_16[0x20]; 6281 6282 u8 inner_smac_47_16[0x20]; 6283 6284 u8 inner_smac_15_0[0x10]; 6285 u8 inner_dmac_15_0[0x10]; 6286 }; 6287 6288 struct mlx5_ifc_match_definer_format_29_bits { 6289 u8 reserved_at_0[0xc0]; 6290 6291 u8 outer_ip_dest_addr[0x80]; 6292 6293 u8 outer_ip_src_addr[0x80]; 6294 6295 u8 outer_l4_sport[0x10]; 6296 u8 outer_l4_dport[0x10]; 6297 6298 u8 reserved_at_1e0[0x20]; 6299 }; 6300 6301 struct mlx5_ifc_match_definer_format_30_bits { 6302 u8 reserved_at_0[0xa0]; 6303 6304 u8 outer_ip_dest_addr[0x80]; 6305 6306 u8 outer_ip_src_addr[0x80]; 6307 6308 u8 outer_dmac_47_16[0x20]; 6309 6310 u8 outer_smac_47_16[0x20]; 6311 6312 u8 outer_smac_15_0[0x10]; 6313 u8 outer_dmac_15_0[0x10]; 6314 }; 6315 6316 struct mlx5_ifc_match_definer_format_31_bits { 6317 u8 reserved_at_0[0xc0]; 6318 6319 u8 inner_ip_dest_addr[0x80]; 6320 6321 u8 inner_ip_src_addr[0x80]; 6322 6323 u8 inner_l4_sport[0x10]; 6324 u8 inner_l4_dport[0x10]; 6325 6326 u8 reserved_at_1e0[0x20]; 6327 }; 6328 6329 struct mlx5_ifc_match_definer_format_32_bits { 6330 u8 reserved_at_0[0xa0]; 6331 6332 u8 inner_ip_dest_addr[0x80]; 6333 6334 u8 inner_ip_src_addr[0x80]; 6335 6336 u8 inner_dmac_47_16[0x20]; 6337 6338 u8 inner_smac_47_16[0x20]; 6339 6340 u8 inner_smac_15_0[0x10]; 6341 u8 inner_dmac_15_0[0x10]; 6342 }; 6343 6344 enum { 6345 MLX5_IFC_DEFINER_FORMAT_ID_SELECT = 61, 6346 }; 6347 6348 #define MLX5_IFC_DEFINER_FORMAT_OFFSET_UNUSED 0x0 6349 #define MLX5_IFC_DEFINER_FORMAT_OFFSET_OUTER_ETH_PKT_LEN 0x48 6350 #define MLX5_IFC_DEFINER_DW_SELECTORS_NUM 9 6351 #define MLX5_IFC_DEFINER_BYTE_SELECTORS_NUM 8 6352 6353 struct mlx5_ifc_match_definer_match_mask_bits { 6354 u8 reserved_at_1c0[5][0x20]; 6355 u8 match_dw_8[0x20]; 6356 u8 match_dw_7[0x20]; 6357 u8 match_dw_6[0x20]; 6358 u8 match_dw_5[0x20]; 6359 u8 match_dw_4[0x20]; 6360 u8 match_dw_3[0x20]; 6361 u8 match_dw_2[0x20]; 6362 u8 match_dw_1[0x20]; 6363 u8 match_dw_0[0x20]; 6364 6365 u8 match_byte_7[0x8]; 6366 u8 match_byte_6[0x8]; 6367 u8 match_byte_5[0x8]; 6368 u8 match_byte_4[0x8]; 6369 6370 u8 match_byte_3[0x8]; 6371 u8 match_byte_2[0x8]; 6372 u8 match_byte_1[0x8]; 6373 u8 match_byte_0[0x8]; 6374 }; 6375 6376 struct mlx5_ifc_match_definer_bits { 6377 u8 modify_field_select[0x40]; 6378 6379 u8 reserved_at_40[0x40]; 6380 6381 u8 reserved_at_80[0x10]; 6382 u8 format_id[0x10]; 6383 6384 u8 reserved_at_a0[0x60]; 6385 6386 u8 format_select_dw3[0x8]; 6387 u8 format_select_dw2[0x8]; 6388 u8 format_select_dw1[0x8]; 6389 u8 format_select_dw0[0x8]; 6390 6391 u8 format_select_dw7[0x8]; 6392 u8 format_select_dw6[0x8]; 6393 u8 format_select_dw5[0x8]; 6394 u8 format_select_dw4[0x8]; 6395 6396 u8 reserved_at_100[0x18]; 6397 u8 format_select_dw8[0x8]; 6398 6399 u8 reserved_at_120[0x20]; 6400 6401 u8 format_select_byte3[0x8]; 6402 u8 format_select_byte2[0x8]; 6403 u8 format_select_byte1[0x8]; 6404 u8 format_select_byte0[0x8]; 6405 6406 u8 format_select_byte7[0x8]; 6407 u8 format_select_byte6[0x8]; 6408 u8 format_select_byte5[0x8]; 6409 u8 format_select_byte4[0x8]; 6410 6411 u8 reserved_at_180[0x40]; 6412 6413 union { 6414 struct { 6415 u8 match_mask[16][0x20]; 6416 }; 6417 struct mlx5_ifc_match_definer_match_mask_bits match_mask_format; 6418 }; 6419 }; 6420 6421 struct mlx5_ifc_general_obj_create_param_bits { 6422 u8 alias_object[0x1]; 6423 u8 reserved_at_1[0x2]; 6424 u8 log_obj_range[0x5]; 6425 u8 reserved_at_8[0x18]; 6426 }; 6427 6428 struct mlx5_ifc_general_obj_query_param_bits { 6429 u8 alias_object[0x1]; 6430 u8 obj_offset[0x1f]; 6431 }; 6432 6433 struct mlx5_ifc_general_obj_in_cmd_hdr_bits { 6434 u8 opcode[0x10]; 6435 u8 uid[0x10]; 6436 6437 u8 vhca_tunnel_id[0x10]; 6438 u8 obj_type[0x10]; 6439 6440 u8 obj_id[0x20]; 6441 6442 union { 6443 struct mlx5_ifc_general_obj_create_param_bits create; 6444 struct mlx5_ifc_general_obj_query_param_bits query; 6445 } op_param; 6446 }; 6447 6448 struct mlx5_ifc_general_obj_out_cmd_hdr_bits { 6449 u8 status[0x8]; 6450 u8 reserved_at_8[0x18]; 6451 6452 u8 syndrome[0x20]; 6453 6454 u8 obj_id[0x20]; 6455 6456 u8 reserved_at_60[0x20]; 6457 }; 6458 6459 struct mlx5_ifc_allow_other_vhca_access_in_bits { 6460 u8 opcode[0x10]; 6461 u8 uid[0x10]; 6462 u8 reserved_at_20[0x10]; 6463 u8 op_mod[0x10]; 6464 u8 reserved_at_40[0x50]; 6465 u8 object_type_to_be_accessed[0x10]; 6466 u8 object_id_to_be_accessed[0x20]; 6467 u8 reserved_at_c0[0x40]; 6468 union { 6469 u8 access_key_raw[0x100]; 6470 u8 access_key[8][0x20]; 6471 }; 6472 }; 6473 6474 struct mlx5_ifc_allow_other_vhca_access_out_bits { 6475 u8 status[0x8]; 6476 u8 reserved_at_8[0x18]; 6477 u8 syndrome[0x20]; 6478 u8 reserved_at_40[0x40]; 6479 }; 6480 6481 struct mlx5_ifc_modify_header_arg_bits { 6482 u8 reserved_at_0[0x80]; 6483 6484 u8 reserved_at_80[0x8]; 6485 u8 access_pd[0x18]; 6486 }; 6487 6488 struct mlx5_ifc_create_modify_header_arg_in_bits { 6489 struct mlx5_ifc_general_obj_in_cmd_hdr_bits hdr; 6490 struct mlx5_ifc_modify_header_arg_bits arg; 6491 }; 6492 6493 struct mlx5_ifc_create_match_definer_in_bits { 6494 struct mlx5_ifc_general_obj_in_cmd_hdr_bits general_obj_in_cmd_hdr; 6495 6496 struct mlx5_ifc_match_definer_bits obj_context; 6497 }; 6498 6499 struct mlx5_ifc_create_match_definer_out_bits { 6500 struct mlx5_ifc_general_obj_out_cmd_hdr_bits general_obj_out_cmd_hdr; 6501 }; 6502 6503 struct mlx5_ifc_alias_context_bits { 6504 u8 vhca_id_to_be_accessed[0x10]; 6505 u8 reserved_at_10[0xd]; 6506 u8 status[0x3]; 6507 u8 object_id_to_be_accessed[0x20]; 6508 u8 reserved_at_40[0x40]; 6509 union { 6510 u8 access_key_raw[0x100]; 6511 u8 access_key[8][0x20]; 6512 }; 6513 u8 metadata[0x80]; 6514 }; 6515 6516 struct mlx5_ifc_create_alias_obj_in_bits { 6517 struct mlx5_ifc_general_obj_in_cmd_hdr_bits hdr; 6518 struct mlx5_ifc_alias_context_bits alias_ctx; 6519 }; 6520 6521 enum { 6522 MLX5_QUERY_FLOW_GROUP_OUT_MATCH_CRITERIA_ENABLE_OUTER_HEADERS = 0x0, 6523 MLX5_QUERY_FLOW_GROUP_OUT_MATCH_CRITERIA_ENABLE_MISC_PARAMETERS = 0x1, 6524 MLX5_QUERY_FLOW_GROUP_OUT_MATCH_CRITERIA_ENABLE_INNER_HEADERS = 0x2, 6525 MLX5_QUERY_FLOW_GROUP_IN_MATCH_CRITERIA_ENABLE_MISC_PARAMETERS_2 = 0x3, 6526 MLX5_QUERY_FLOW_GROUP_IN_MATCH_CRITERIA_ENABLE_MISC_PARAMETERS_3 = 0x4, 6527 MLX5_QUERY_FLOW_GROUP_IN_MATCH_CRITERIA_ENABLE_MISC_PARAMETERS_4 = 0x5, 6528 MLX5_QUERY_FLOW_GROUP_IN_MATCH_CRITERIA_ENABLE_MISC_PARAMETERS_5 = 0x6, 6529 }; 6530 6531 struct mlx5_ifc_query_flow_group_out_bits { 6532 u8 status[0x8]; 6533 u8 reserved_at_8[0x18]; 6534 6535 u8 syndrome[0x20]; 6536 6537 u8 reserved_at_40[0xa0]; 6538 6539 u8 start_flow_index[0x20]; 6540 6541 u8 reserved_at_100[0x20]; 6542 6543 u8 end_flow_index[0x20]; 6544 6545 u8 reserved_at_140[0xa0]; 6546 6547 u8 reserved_at_1e0[0x18]; 6548 u8 match_criteria_enable[0x8]; 6549 6550 struct mlx5_ifc_fte_match_param_bits match_criteria; 6551 6552 u8 reserved_at_1200[0xe00]; 6553 }; 6554 6555 struct mlx5_ifc_query_flow_group_in_bits { 6556 u8 opcode[0x10]; 6557 u8 reserved_at_10[0x10]; 6558 6559 u8 reserved_at_20[0x10]; 6560 u8 op_mod[0x10]; 6561 6562 u8 reserved_at_40[0x40]; 6563 6564 u8 table_type[0x8]; 6565 u8 reserved_at_88[0x18]; 6566 6567 u8 reserved_at_a0[0x8]; 6568 u8 table_id[0x18]; 6569 6570 u8 group_id[0x20]; 6571 6572 u8 reserved_at_e0[0x120]; 6573 }; 6574 6575 struct mlx5_ifc_query_flow_counter_out_bits { 6576 u8 status[0x8]; 6577 u8 reserved_at_8[0x18]; 6578 6579 u8 syndrome[0x20]; 6580 6581 u8 reserved_at_40[0x40]; 6582 6583 struct mlx5_ifc_traffic_counter_bits flow_statistics[]; 6584 }; 6585 6586 struct mlx5_ifc_query_flow_counter_in_bits { 6587 u8 opcode[0x10]; 6588 u8 reserved_at_10[0x10]; 6589 6590 u8 reserved_at_20[0x10]; 6591 u8 op_mod[0x10]; 6592 6593 u8 reserved_at_40[0x80]; 6594 6595 u8 clear[0x1]; 6596 u8 reserved_at_c1[0xf]; 6597 u8 num_of_counters[0x10]; 6598 6599 u8 flow_counter_id[0x20]; 6600 }; 6601 6602 struct mlx5_ifc_query_esw_vport_context_out_bits { 6603 u8 status[0x8]; 6604 u8 reserved_at_8[0x18]; 6605 6606 u8 syndrome[0x20]; 6607 6608 u8 reserved_at_40[0x40]; 6609 6610 struct mlx5_ifc_esw_vport_context_bits esw_vport_context; 6611 }; 6612 6613 struct mlx5_ifc_query_esw_vport_context_in_bits { 6614 u8 opcode[0x10]; 6615 u8 reserved_at_10[0x10]; 6616 6617 u8 reserved_at_20[0x10]; 6618 u8 op_mod[0x10]; 6619 6620 u8 other_vport[0x1]; 6621 u8 reserved_at_41[0xf]; 6622 u8 vport_number[0x10]; 6623 6624 u8 reserved_at_60[0x20]; 6625 }; 6626 6627 struct mlx5_ifc_modify_esw_vport_context_out_bits { 6628 u8 status[0x8]; 6629 u8 reserved_at_8[0x18]; 6630 6631 u8 syndrome[0x20]; 6632 6633 u8 reserved_at_40[0x40]; 6634 }; 6635 6636 struct mlx5_ifc_esw_vport_context_fields_select_bits { 6637 u8 reserved_at_0[0x1b]; 6638 u8 fdb_to_vport_reg_c_id[0x1]; 6639 u8 vport_cvlan_insert[0x1]; 6640 u8 vport_svlan_insert[0x1]; 6641 u8 vport_cvlan_strip[0x1]; 6642 u8 vport_svlan_strip[0x1]; 6643 }; 6644 6645 struct mlx5_ifc_modify_esw_vport_context_in_bits { 6646 u8 opcode[0x10]; 6647 u8 reserved_at_10[0x10]; 6648 6649 u8 reserved_at_20[0x10]; 6650 u8 op_mod[0x10]; 6651 6652 u8 other_vport[0x1]; 6653 u8 reserved_at_41[0xf]; 6654 u8 vport_number[0x10]; 6655 6656 struct mlx5_ifc_esw_vport_context_fields_select_bits field_select; 6657 6658 struct mlx5_ifc_esw_vport_context_bits esw_vport_context; 6659 }; 6660 6661 struct mlx5_ifc_query_eq_out_bits { 6662 u8 status[0x8]; 6663 u8 reserved_at_8[0x18]; 6664 6665 u8 syndrome[0x20]; 6666 6667 u8 reserved_at_40[0x40]; 6668 6669 struct mlx5_ifc_eqc_bits eq_context_entry; 6670 6671 u8 reserved_at_280[0x40]; 6672 6673 u8 event_bitmask[0x40]; 6674 6675 u8 reserved_at_300[0x580]; 6676 6677 u8 pas[][0x40]; 6678 }; 6679 6680 struct mlx5_ifc_query_eq_in_bits { 6681 u8 opcode[0x10]; 6682 u8 reserved_at_10[0x10]; 6683 6684 u8 reserved_at_20[0x10]; 6685 u8 op_mod[0x10]; 6686 6687 u8 reserved_at_40[0x18]; 6688 u8 eq_number[0x8]; 6689 6690 u8 reserved_at_60[0x20]; 6691 }; 6692 6693 struct mlx5_ifc_packet_reformat_context_in_bits { 6694 u8 reformat_type[0x8]; 6695 u8 reserved_at_8[0x4]; 6696 u8 reformat_param_0[0x4]; 6697 u8 reserved_at_10[0x6]; 6698 u8 reformat_data_size[0xa]; 6699 6700 u8 reformat_param_1[0x8]; 6701 u8 reserved_at_28[0x8]; 6702 u8 reformat_data[2][0x8]; 6703 6704 u8 more_reformat_data[][0x8]; 6705 }; 6706 6707 struct mlx5_ifc_query_packet_reformat_context_out_bits { 6708 u8 status[0x8]; 6709 u8 reserved_at_8[0x18]; 6710 6711 u8 syndrome[0x20]; 6712 6713 u8 reserved_at_40[0xa0]; 6714 6715 struct mlx5_ifc_packet_reformat_context_in_bits packet_reformat_context[]; 6716 }; 6717 6718 struct mlx5_ifc_query_packet_reformat_context_in_bits { 6719 u8 opcode[0x10]; 6720 u8 reserved_at_10[0x10]; 6721 6722 u8 reserved_at_20[0x10]; 6723 u8 op_mod[0x10]; 6724 6725 u8 packet_reformat_id[0x20]; 6726 6727 u8 reserved_at_60[0xa0]; 6728 }; 6729 6730 struct mlx5_ifc_alloc_packet_reformat_context_out_bits { 6731 u8 status[0x8]; 6732 u8 reserved_at_8[0x18]; 6733 6734 u8 syndrome[0x20]; 6735 6736 u8 packet_reformat_id[0x20]; 6737 6738 u8 reserved_at_60[0x20]; 6739 }; 6740 6741 enum { 6742 MLX5_REFORMAT_CONTEXT_ANCHOR_MAC_START = 0x1, 6743 MLX5_REFORMAT_CONTEXT_ANCHOR_IP_START = 0x7, 6744 MLX5_REFORMAT_CONTEXT_ANCHOR_TCP_UDP_START = 0x9, 6745 }; 6746 6747 enum mlx5_reformat_ctx_type { 6748 MLX5_REFORMAT_TYPE_L2_TO_VXLAN = 0x0, 6749 MLX5_REFORMAT_TYPE_L2_TO_NVGRE = 0x1, 6750 MLX5_REFORMAT_TYPE_L2_TO_L2_TUNNEL = 0x2, 6751 MLX5_REFORMAT_TYPE_L3_TUNNEL_TO_L2 = 0x3, 6752 MLX5_REFORMAT_TYPE_L2_TO_L3_TUNNEL = 0x4, 6753 MLX5_REFORMAT_TYPE_ADD_ESP_TRANSPORT_OVER_IPV4 = 0x5, 6754 MLX5_REFORMAT_TYPE_L2_TO_L3_ESP_TUNNEL = 0x6, 6755 MLX5_REFORMAT_TYPE_ADD_ESP_TRANSPORT_OVER_UDPV4 = 0x7, 6756 MLX5_REFORMAT_TYPE_DEL_ESP_TRANSPORT = 0x8, 6757 MLX5_REFORMAT_TYPE_L3_ESP_TUNNEL_TO_L2 = 0x9, 6758 MLX5_REFORMAT_TYPE_DEL_ESP_TRANSPORT_OVER_UDP = 0xa, 6759 MLX5_REFORMAT_TYPE_ADD_ESP_TRANSPORT_OVER_IPV6 = 0xb, 6760 MLX5_REFORMAT_TYPE_ADD_ESP_TRANSPORT_OVER_UDPV6 = 0xc, 6761 MLX5_REFORMAT_TYPE_INSERT_HDR = 0xf, 6762 MLX5_REFORMAT_TYPE_REMOVE_HDR = 0x10, 6763 MLX5_REFORMAT_TYPE_ADD_MACSEC = 0x11, 6764 MLX5_REFORMAT_TYPE_DEL_MACSEC = 0x12, 6765 }; 6766 6767 struct mlx5_ifc_alloc_packet_reformat_context_in_bits { 6768 u8 opcode[0x10]; 6769 u8 reserved_at_10[0x10]; 6770 6771 u8 reserved_at_20[0x10]; 6772 u8 op_mod[0x10]; 6773 6774 u8 reserved_at_40[0xa0]; 6775 6776 struct mlx5_ifc_packet_reformat_context_in_bits packet_reformat_context; 6777 }; 6778 6779 struct mlx5_ifc_dealloc_packet_reformat_context_out_bits { 6780 u8 status[0x8]; 6781 u8 reserved_at_8[0x18]; 6782 6783 u8 syndrome[0x20]; 6784 6785 u8 reserved_at_40[0x40]; 6786 }; 6787 6788 struct mlx5_ifc_dealloc_packet_reformat_context_in_bits { 6789 u8 opcode[0x10]; 6790 u8 reserved_at_10[0x10]; 6791 6792 u8 reserved_20[0x10]; 6793 u8 op_mod[0x10]; 6794 6795 u8 packet_reformat_id[0x20]; 6796 6797 u8 reserved_60[0x20]; 6798 }; 6799 6800 struct mlx5_ifc_set_action_in_bits { 6801 u8 action_type[0x4]; 6802 u8 field[0xc]; 6803 u8 reserved_at_10[0x3]; 6804 u8 offset[0x5]; 6805 u8 reserved_at_18[0x3]; 6806 u8 length[0x5]; 6807 6808 u8 data[0x20]; 6809 }; 6810 6811 struct mlx5_ifc_add_action_in_bits { 6812 u8 action_type[0x4]; 6813 u8 field[0xc]; 6814 u8 reserved_at_10[0x10]; 6815 6816 u8 data[0x20]; 6817 }; 6818 6819 struct mlx5_ifc_copy_action_in_bits { 6820 u8 action_type[0x4]; 6821 u8 src_field[0xc]; 6822 u8 reserved_at_10[0x3]; 6823 u8 src_offset[0x5]; 6824 u8 reserved_at_18[0x3]; 6825 u8 length[0x5]; 6826 6827 u8 reserved_at_20[0x4]; 6828 u8 dst_field[0xc]; 6829 u8 reserved_at_30[0x3]; 6830 u8 dst_offset[0x5]; 6831 u8 reserved_at_38[0x8]; 6832 }; 6833 6834 union mlx5_ifc_set_add_copy_action_in_auto_bits { 6835 struct mlx5_ifc_set_action_in_bits set_action_in; 6836 struct mlx5_ifc_add_action_in_bits add_action_in; 6837 struct mlx5_ifc_copy_action_in_bits copy_action_in; 6838 u8 reserved_at_0[0x40]; 6839 }; 6840 6841 enum { 6842 MLX5_ACTION_TYPE_SET = 0x1, 6843 MLX5_ACTION_TYPE_ADD = 0x2, 6844 MLX5_ACTION_TYPE_COPY = 0x3, 6845 }; 6846 6847 enum { 6848 MLX5_ACTION_IN_FIELD_OUT_SMAC_47_16 = 0x1, 6849 MLX5_ACTION_IN_FIELD_OUT_SMAC_15_0 = 0x2, 6850 MLX5_ACTION_IN_FIELD_OUT_ETHERTYPE = 0x3, 6851 MLX5_ACTION_IN_FIELD_OUT_DMAC_47_16 = 0x4, 6852 MLX5_ACTION_IN_FIELD_OUT_DMAC_15_0 = 0x5, 6853 MLX5_ACTION_IN_FIELD_OUT_IP_DSCP = 0x6, 6854 MLX5_ACTION_IN_FIELD_OUT_TCP_FLAGS = 0x7, 6855 MLX5_ACTION_IN_FIELD_OUT_TCP_SPORT = 0x8, 6856 MLX5_ACTION_IN_FIELD_OUT_TCP_DPORT = 0x9, 6857 MLX5_ACTION_IN_FIELD_OUT_IP_TTL = 0xa, 6858 MLX5_ACTION_IN_FIELD_OUT_UDP_SPORT = 0xb, 6859 MLX5_ACTION_IN_FIELD_OUT_UDP_DPORT = 0xc, 6860 MLX5_ACTION_IN_FIELD_OUT_SIPV6_127_96 = 0xd, 6861 MLX5_ACTION_IN_FIELD_OUT_SIPV6_95_64 = 0xe, 6862 MLX5_ACTION_IN_FIELD_OUT_SIPV6_63_32 = 0xf, 6863 MLX5_ACTION_IN_FIELD_OUT_SIPV6_31_0 = 0x10, 6864 MLX5_ACTION_IN_FIELD_OUT_DIPV6_127_96 = 0x11, 6865 MLX5_ACTION_IN_FIELD_OUT_DIPV6_95_64 = 0x12, 6866 MLX5_ACTION_IN_FIELD_OUT_DIPV6_63_32 = 0x13, 6867 MLX5_ACTION_IN_FIELD_OUT_DIPV6_31_0 = 0x14, 6868 MLX5_ACTION_IN_FIELD_OUT_SIPV4 = 0x15, 6869 MLX5_ACTION_IN_FIELD_OUT_DIPV4 = 0x16, 6870 MLX5_ACTION_IN_FIELD_OUT_FIRST_VID = 0x17, 6871 MLX5_ACTION_IN_FIELD_OUT_IPV6_HOPLIMIT = 0x47, 6872 MLX5_ACTION_IN_FIELD_METADATA_REG_A = 0x49, 6873 MLX5_ACTION_IN_FIELD_METADATA_REG_B = 0x50, 6874 MLX5_ACTION_IN_FIELD_METADATA_REG_C_0 = 0x51, 6875 MLX5_ACTION_IN_FIELD_METADATA_REG_C_1 = 0x52, 6876 MLX5_ACTION_IN_FIELD_METADATA_REG_C_2 = 0x53, 6877 MLX5_ACTION_IN_FIELD_METADATA_REG_C_3 = 0x54, 6878 MLX5_ACTION_IN_FIELD_METADATA_REG_C_4 = 0x55, 6879 MLX5_ACTION_IN_FIELD_METADATA_REG_C_5 = 0x56, 6880 MLX5_ACTION_IN_FIELD_METADATA_REG_C_6 = 0x57, 6881 MLX5_ACTION_IN_FIELD_METADATA_REG_C_7 = 0x58, 6882 MLX5_ACTION_IN_FIELD_OUT_TCP_SEQ_NUM = 0x59, 6883 MLX5_ACTION_IN_FIELD_OUT_TCP_ACK_NUM = 0x5B, 6884 MLX5_ACTION_IN_FIELD_IPSEC_SYNDROME = 0x5D, 6885 MLX5_ACTION_IN_FIELD_OUT_EMD_47_32 = 0x6F, 6886 MLX5_ACTION_IN_FIELD_OUT_EMD_31_0 = 0x70, 6887 }; 6888 6889 struct mlx5_ifc_alloc_modify_header_context_out_bits { 6890 u8 status[0x8]; 6891 u8 reserved_at_8[0x18]; 6892 6893 u8 syndrome[0x20]; 6894 6895 u8 modify_header_id[0x20]; 6896 6897 u8 reserved_at_60[0x20]; 6898 }; 6899 6900 struct mlx5_ifc_alloc_modify_header_context_in_bits { 6901 u8 opcode[0x10]; 6902 u8 reserved_at_10[0x10]; 6903 6904 u8 reserved_at_20[0x10]; 6905 u8 op_mod[0x10]; 6906 6907 u8 reserved_at_40[0x20]; 6908 6909 u8 table_type[0x8]; 6910 u8 reserved_at_68[0x10]; 6911 u8 num_of_actions[0x8]; 6912 6913 union mlx5_ifc_set_add_copy_action_in_auto_bits actions[]; 6914 }; 6915 6916 struct mlx5_ifc_dealloc_modify_header_context_out_bits { 6917 u8 status[0x8]; 6918 u8 reserved_at_8[0x18]; 6919 6920 u8 syndrome[0x20]; 6921 6922 u8 reserved_at_40[0x40]; 6923 }; 6924 6925 struct mlx5_ifc_dealloc_modify_header_context_in_bits { 6926 u8 opcode[0x10]; 6927 u8 reserved_at_10[0x10]; 6928 6929 u8 reserved_at_20[0x10]; 6930 u8 op_mod[0x10]; 6931 6932 u8 modify_header_id[0x20]; 6933 6934 u8 reserved_at_60[0x20]; 6935 }; 6936 6937 struct mlx5_ifc_query_modify_header_context_in_bits { 6938 u8 opcode[0x10]; 6939 u8 uid[0x10]; 6940 6941 u8 reserved_at_20[0x10]; 6942 u8 op_mod[0x10]; 6943 6944 u8 modify_header_id[0x20]; 6945 6946 u8 reserved_at_60[0xa0]; 6947 }; 6948 6949 struct mlx5_ifc_query_dct_out_bits { 6950 u8 status[0x8]; 6951 u8 reserved_at_8[0x18]; 6952 6953 u8 syndrome[0x20]; 6954 6955 u8 reserved_at_40[0x40]; 6956 6957 struct mlx5_ifc_dctc_bits dct_context_entry; 6958 6959 u8 reserved_at_280[0x180]; 6960 }; 6961 6962 struct mlx5_ifc_query_dct_in_bits { 6963 u8 opcode[0x10]; 6964 u8 reserved_at_10[0x10]; 6965 6966 u8 reserved_at_20[0x10]; 6967 u8 op_mod[0x10]; 6968 6969 u8 reserved_at_40[0x8]; 6970 u8 dctn[0x18]; 6971 6972 u8 reserved_at_60[0x20]; 6973 }; 6974 6975 struct mlx5_ifc_query_cq_out_bits { 6976 u8 status[0x8]; 6977 u8 reserved_at_8[0x18]; 6978 6979 u8 syndrome[0x20]; 6980 6981 u8 reserved_at_40[0x40]; 6982 6983 struct mlx5_ifc_cqc_bits cq_context; 6984 6985 u8 reserved_at_280[0x600]; 6986 6987 u8 pas[][0x40]; 6988 }; 6989 6990 struct mlx5_ifc_query_cq_in_bits { 6991 u8 opcode[0x10]; 6992 u8 reserved_at_10[0x10]; 6993 6994 u8 reserved_at_20[0x10]; 6995 u8 op_mod[0x10]; 6996 6997 u8 reserved_at_40[0x8]; 6998 u8 cqn[0x18]; 6999 7000 u8 reserved_at_60[0x20]; 7001 }; 7002 7003 struct mlx5_ifc_query_cong_status_out_bits { 7004 u8 status[0x8]; 7005 u8 reserved_at_8[0x18]; 7006 7007 u8 syndrome[0x20]; 7008 7009 u8 reserved_at_40[0x20]; 7010 7011 u8 enable[0x1]; 7012 u8 tag_enable[0x1]; 7013 u8 reserved_at_62[0x1e]; 7014 }; 7015 7016 struct mlx5_ifc_query_cong_status_in_bits { 7017 u8 opcode[0x10]; 7018 u8 reserved_at_10[0x10]; 7019 7020 u8 reserved_at_20[0x10]; 7021 u8 op_mod[0x10]; 7022 7023 u8 reserved_at_40[0x18]; 7024 u8 priority[0x4]; 7025 u8 cong_protocol[0x4]; 7026 7027 u8 reserved_at_60[0x20]; 7028 }; 7029 7030 struct mlx5_ifc_query_cong_statistics_out_bits { 7031 u8 status[0x8]; 7032 u8 reserved_at_8[0x18]; 7033 7034 u8 syndrome[0x20]; 7035 7036 u8 reserved_at_40[0x40]; 7037 7038 u8 rp_cur_flows[0x20]; 7039 7040 u8 sum_flows[0x20]; 7041 7042 u8 rp_cnp_ignored_high[0x20]; 7043 7044 u8 rp_cnp_ignored_low[0x20]; 7045 7046 u8 rp_cnp_handled_high[0x20]; 7047 7048 u8 rp_cnp_handled_low[0x20]; 7049 7050 u8 reserved_at_140[0x100]; 7051 7052 u8 time_stamp_high[0x20]; 7053 7054 u8 time_stamp_low[0x20]; 7055 7056 u8 accumulators_period[0x20]; 7057 7058 u8 np_ecn_marked_roce_packets_high[0x20]; 7059 7060 u8 np_ecn_marked_roce_packets_low[0x20]; 7061 7062 u8 np_cnp_sent_high[0x20]; 7063 7064 u8 np_cnp_sent_low[0x20]; 7065 7066 u8 reserved_at_320[0x560]; 7067 }; 7068 7069 struct mlx5_ifc_query_cong_statistics_in_bits { 7070 u8 opcode[0x10]; 7071 u8 reserved_at_10[0x10]; 7072 7073 u8 reserved_at_20[0x10]; 7074 u8 op_mod[0x10]; 7075 7076 u8 clear[0x1]; 7077 u8 reserved_at_41[0x1f]; 7078 7079 u8 reserved_at_60[0x20]; 7080 }; 7081 7082 struct mlx5_ifc_query_cong_params_out_bits { 7083 u8 status[0x8]; 7084 u8 reserved_at_8[0x18]; 7085 7086 u8 syndrome[0x20]; 7087 7088 u8 reserved_at_40[0x40]; 7089 7090 union mlx5_ifc_cong_control_roce_ecn_auto_bits congestion_parameters; 7091 }; 7092 7093 struct mlx5_ifc_query_cong_params_in_bits { 7094 u8 opcode[0x10]; 7095 u8 reserved_at_10[0x10]; 7096 7097 u8 reserved_at_20[0x10]; 7098 u8 op_mod[0x10]; 7099 7100 u8 reserved_at_40[0x1c]; 7101 u8 cong_protocol[0x4]; 7102 7103 u8 reserved_at_60[0x20]; 7104 }; 7105 7106 struct mlx5_ifc_query_adapter_out_bits { 7107 u8 status[0x8]; 7108 u8 reserved_at_8[0x18]; 7109 7110 u8 syndrome[0x20]; 7111 7112 u8 reserved_at_40[0x40]; 7113 7114 struct mlx5_ifc_query_adapter_param_block_bits query_adapter_struct; 7115 }; 7116 7117 struct mlx5_ifc_query_adapter_in_bits { 7118 u8 opcode[0x10]; 7119 u8 reserved_at_10[0x10]; 7120 7121 u8 reserved_at_20[0x10]; 7122 u8 op_mod[0x10]; 7123 7124 u8 reserved_at_40[0x40]; 7125 }; 7126 7127 struct mlx5_ifc_qp_2rst_out_bits { 7128 u8 status[0x8]; 7129 u8 reserved_at_8[0x18]; 7130 7131 u8 syndrome[0x20]; 7132 7133 u8 reserved_at_40[0x40]; 7134 }; 7135 7136 struct mlx5_ifc_qp_2rst_in_bits { 7137 u8 opcode[0x10]; 7138 u8 uid[0x10]; 7139 7140 u8 reserved_at_20[0x10]; 7141 u8 op_mod[0x10]; 7142 7143 u8 reserved_at_40[0x8]; 7144 u8 qpn[0x18]; 7145 7146 u8 reserved_at_60[0x20]; 7147 }; 7148 7149 struct mlx5_ifc_qp_2err_out_bits { 7150 u8 status[0x8]; 7151 u8 reserved_at_8[0x18]; 7152 7153 u8 syndrome[0x20]; 7154 7155 u8 reserved_at_40[0x40]; 7156 }; 7157 7158 struct mlx5_ifc_qp_2err_in_bits { 7159 u8 opcode[0x10]; 7160 u8 uid[0x10]; 7161 7162 u8 reserved_at_20[0x10]; 7163 u8 op_mod[0x10]; 7164 7165 u8 reserved_at_40[0x8]; 7166 u8 qpn[0x18]; 7167 7168 u8 reserved_at_60[0x20]; 7169 }; 7170 7171 struct mlx5_ifc_page_fault_resume_out_bits { 7172 u8 status[0x8]; 7173 u8 reserved_at_8[0x18]; 7174 7175 u8 syndrome[0x20]; 7176 7177 u8 reserved_at_40[0x40]; 7178 }; 7179 7180 struct mlx5_ifc_page_fault_resume_in_bits { 7181 u8 opcode[0x10]; 7182 u8 reserved_at_10[0x10]; 7183 7184 u8 reserved_at_20[0x10]; 7185 u8 op_mod[0x10]; 7186 7187 u8 error[0x1]; 7188 u8 reserved_at_41[0x4]; 7189 u8 page_fault_type[0x3]; 7190 u8 wq_number[0x18]; 7191 7192 u8 reserved_at_60[0x8]; 7193 u8 token[0x18]; 7194 }; 7195 7196 struct mlx5_ifc_nop_out_bits { 7197 u8 status[0x8]; 7198 u8 reserved_at_8[0x18]; 7199 7200 u8 syndrome[0x20]; 7201 7202 u8 reserved_at_40[0x40]; 7203 }; 7204 7205 struct mlx5_ifc_nop_in_bits { 7206 u8 opcode[0x10]; 7207 u8 reserved_at_10[0x10]; 7208 7209 u8 reserved_at_20[0x10]; 7210 u8 op_mod[0x10]; 7211 7212 u8 reserved_at_40[0x40]; 7213 }; 7214 7215 struct mlx5_ifc_modify_vport_state_out_bits { 7216 u8 status[0x8]; 7217 u8 reserved_at_8[0x18]; 7218 7219 u8 syndrome[0x20]; 7220 7221 u8 reserved_at_40[0x40]; 7222 }; 7223 7224 struct mlx5_ifc_modify_vport_state_in_bits { 7225 u8 opcode[0x10]; 7226 u8 reserved_at_10[0x10]; 7227 7228 u8 reserved_at_20[0x10]; 7229 u8 op_mod[0x10]; 7230 7231 u8 other_vport[0x1]; 7232 u8 reserved_at_41[0xf]; 7233 u8 vport_number[0x10]; 7234 7235 u8 reserved_at_60[0x18]; 7236 u8 admin_state[0x4]; 7237 u8 reserved_at_7c[0x4]; 7238 }; 7239 7240 struct mlx5_ifc_modify_tis_out_bits { 7241 u8 status[0x8]; 7242 u8 reserved_at_8[0x18]; 7243 7244 u8 syndrome[0x20]; 7245 7246 u8 reserved_at_40[0x40]; 7247 }; 7248 7249 struct mlx5_ifc_modify_tis_bitmask_bits { 7250 u8 reserved_at_0[0x20]; 7251 7252 u8 reserved_at_20[0x1d]; 7253 u8 lag_tx_port_affinity[0x1]; 7254 u8 strict_lag_tx_port_affinity[0x1]; 7255 u8 prio[0x1]; 7256 }; 7257 7258 struct mlx5_ifc_modify_tis_in_bits { 7259 u8 opcode[0x10]; 7260 u8 uid[0x10]; 7261 7262 u8 reserved_at_20[0x10]; 7263 u8 op_mod[0x10]; 7264 7265 u8 reserved_at_40[0x8]; 7266 u8 tisn[0x18]; 7267 7268 u8 reserved_at_60[0x20]; 7269 7270 struct mlx5_ifc_modify_tis_bitmask_bits bitmask; 7271 7272 u8 reserved_at_c0[0x40]; 7273 7274 struct mlx5_ifc_tisc_bits ctx; 7275 }; 7276 7277 struct mlx5_ifc_modify_tir_bitmask_bits { 7278 u8 reserved_at_0[0x20]; 7279 7280 u8 reserved_at_20[0x1b]; 7281 u8 self_lb_en[0x1]; 7282 u8 reserved_at_3c[0x1]; 7283 u8 hash[0x1]; 7284 u8 reserved_at_3e[0x1]; 7285 u8 packet_merge[0x1]; 7286 }; 7287 7288 struct mlx5_ifc_modify_tir_out_bits { 7289 u8 status[0x8]; 7290 u8 reserved_at_8[0x18]; 7291 7292 u8 syndrome[0x20]; 7293 7294 u8 reserved_at_40[0x40]; 7295 }; 7296 7297 struct mlx5_ifc_modify_tir_in_bits { 7298 u8 opcode[0x10]; 7299 u8 uid[0x10]; 7300 7301 u8 reserved_at_20[0x10]; 7302 u8 op_mod[0x10]; 7303 7304 u8 reserved_at_40[0x8]; 7305 u8 tirn[0x18]; 7306 7307 u8 reserved_at_60[0x20]; 7308 7309 struct mlx5_ifc_modify_tir_bitmask_bits bitmask; 7310 7311 u8 reserved_at_c0[0x40]; 7312 7313 struct mlx5_ifc_tirc_bits ctx; 7314 }; 7315 7316 struct mlx5_ifc_modify_sq_out_bits { 7317 u8 status[0x8]; 7318 u8 reserved_at_8[0x18]; 7319 7320 u8 syndrome[0x20]; 7321 7322 u8 reserved_at_40[0x40]; 7323 }; 7324 7325 struct mlx5_ifc_modify_sq_in_bits { 7326 u8 opcode[0x10]; 7327 u8 uid[0x10]; 7328 7329 u8 reserved_at_20[0x10]; 7330 u8 op_mod[0x10]; 7331 7332 u8 sq_state[0x4]; 7333 u8 reserved_at_44[0x4]; 7334 u8 sqn[0x18]; 7335 7336 u8 reserved_at_60[0x20]; 7337 7338 u8 modify_bitmask[0x40]; 7339 7340 u8 reserved_at_c0[0x40]; 7341 7342 struct mlx5_ifc_sqc_bits ctx; 7343 }; 7344 7345 struct mlx5_ifc_modify_scheduling_element_out_bits { 7346 u8 status[0x8]; 7347 u8 reserved_at_8[0x18]; 7348 7349 u8 syndrome[0x20]; 7350 7351 u8 reserved_at_40[0x1c0]; 7352 }; 7353 7354 enum { 7355 MODIFY_SCHEDULING_ELEMENT_IN_MODIFY_BITMASK_BW_SHARE = 0x1, 7356 MODIFY_SCHEDULING_ELEMENT_IN_MODIFY_BITMASK_MAX_AVERAGE_BW = 0x2, 7357 }; 7358 7359 struct mlx5_ifc_modify_scheduling_element_in_bits { 7360 u8 opcode[0x10]; 7361 u8 reserved_at_10[0x10]; 7362 7363 u8 reserved_at_20[0x10]; 7364 u8 op_mod[0x10]; 7365 7366 u8 scheduling_hierarchy[0x8]; 7367 u8 reserved_at_48[0x18]; 7368 7369 u8 scheduling_element_id[0x20]; 7370 7371 u8 reserved_at_80[0x20]; 7372 7373 u8 modify_bitmask[0x20]; 7374 7375 u8 reserved_at_c0[0x40]; 7376 7377 struct mlx5_ifc_scheduling_context_bits scheduling_context; 7378 7379 u8 reserved_at_300[0x100]; 7380 }; 7381 7382 struct mlx5_ifc_modify_rqt_out_bits { 7383 u8 status[0x8]; 7384 u8 reserved_at_8[0x18]; 7385 7386 u8 syndrome[0x20]; 7387 7388 u8 reserved_at_40[0x40]; 7389 }; 7390 7391 struct mlx5_ifc_rqt_bitmask_bits { 7392 u8 reserved_at_0[0x20]; 7393 7394 u8 reserved_at_20[0x1f]; 7395 u8 rqn_list[0x1]; 7396 }; 7397 7398 struct mlx5_ifc_modify_rqt_in_bits { 7399 u8 opcode[0x10]; 7400 u8 uid[0x10]; 7401 7402 u8 reserved_at_20[0x10]; 7403 u8 op_mod[0x10]; 7404 7405 u8 reserved_at_40[0x8]; 7406 u8 rqtn[0x18]; 7407 7408 u8 reserved_at_60[0x20]; 7409 7410 struct mlx5_ifc_rqt_bitmask_bits bitmask; 7411 7412 u8 reserved_at_c0[0x40]; 7413 7414 struct mlx5_ifc_rqtc_bits ctx; 7415 }; 7416 7417 struct mlx5_ifc_modify_rq_out_bits { 7418 u8 status[0x8]; 7419 u8 reserved_at_8[0x18]; 7420 7421 u8 syndrome[0x20]; 7422 7423 u8 reserved_at_40[0x40]; 7424 }; 7425 7426 enum { 7427 MLX5_MODIFY_RQ_IN_MODIFY_BITMASK_VSD = 1ULL << 1, 7428 MLX5_MODIFY_RQ_IN_MODIFY_BITMASK_SCATTER_FCS = 1ULL << 2, 7429 MLX5_MODIFY_RQ_IN_MODIFY_BITMASK_RQ_COUNTER_SET_ID = 1ULL << 3, 7430 }; 7431 7432 struct mlx5_ifc_modify_rq_in_bits { 7433 u8 opcode[0x10]; 7434 u8 uid[0x10]; 7435 7436 u8 reserved_at_20[0x10]; 7437 u8 op_mod[0x10]; 7438 7439 u8 rq_state[0x4]; 7440 u8 reserved_at_44[0x4]; 7441 u8 rqn[0x18]; 7442 7443 u8 reserved_at_60[0x20]; 7444 7445 u8 modify_bitmask[0x40]; 7446 7447 u8 reserved_at_c0[0x40]; 7448 7449 struct mlx5_ifc_rqc_bits ctx; 7450 }; 7451 7452 struct mlx5_ifc_modify_rmp_out_bits { 7453 u8 status[0x8]; 7454 u8 reserved_at_8[0x18]; 7455 7456 u8 syndrome[0x20]; 7457 7458 u8 reserved_at_40[0x40]; 7459 }; 7460 7461 struct mlx5_ifc_rmp_bitmask_bits { 7462 u8 reserved_at_0[0x20]; 7463 7464 u8 reserved_at_20[0x1f]; 7465 u8 lwm[0x1]; 7466 }; 7467 7468 struct mlx5_ifc_modify_rmp_in_bits { 7469 u8 opcode[0x10]; 7470 u8 uid[0x10]; 7471 7472 u8 reserved_at_20[0x10]; 7473 u8 op_mod[0x10]; 7474 7475 u8 rmp_state[0x4]; 7476 u8 reserved_at_44[0x4]; 7477 u8 rmpn[0x18]; 7478 7479 u8 reserved_at_60[0x20]; 7480 7481 struct mlx5_ifc_rmp_bitmask_bits bitmask; 7482 7483 u8 reserved_at_c0[0x40]; 7484 7485 struct mlx5_ifc_rmpc_bits ctx; 7486 }; 7487 7488 struct mlx5_ifc_modify_nic_vport_context_out_bits { 7489 u8 status[0x8]; 7490 u8 reserved_at_8[0x18]; 7491 7492 u8 syndrome[0x20]; 7493 7494 u8 reserved_at_40[0x40]; 7495 }; 7496 7497 struct mlx5_ifc_modify_nic_vport_field_select_bits { 7498 u8 reserved_at_0[0x12]; 7499 u8 affiliation[0x1]; 7500 u8 reserved_at_13[0x1]; 7501 u8 disable_uc_local_lb[0x1]; 7502 u8 disable_mc_local_lb[0x1]; 7503 u8 node_guid[0x1]; 7504 u8 port_guid[0x1]; 7505 u8 min_inline[0x1]; 7506 u8 mtu[0x1]; 7507 u8 change_event[0x1]; 7508 u8 promisc[0x1]; 7509 u8 permanent_address[0x1]; 7510 u8 addresses_list[0x1]; 7511 u8 roce_en[0x1]; 7512 u8 reserved_at_1f[0x1]; 7513 }; 7514 7515 struct mlx5_ifc_modify_nic_vport_context_in_bits { 7516 u8 opcode[0x10]; 7517 u8 reserved_at_10[0x10]; 7518 7519 u8 reserved_at_20[0x10]; 7520 u8 op_mod[0x10]; 7521 7522 u8 other_vport[0x1]; 7523 u8 reserved_at_41[0xf]; 7524 u8 vport_number[0x10]; 7525 7526 struct mlx5_ifc_modify_nic_vport_field_select_bits field_select; 7527 7528 u8 reserved_at_80[0x780]; 7529 7530 struct mlx5_ifc_nic_vport_context_bits nic_vport_context; 7531 }; 7532 7533 struct mlx5_ifc_modify_hca_vport_context_out_bits { 7534 u8 status[0x8]; 7535 u8 reserved_at_8[0x18]; 7536 7537 u8 syndrome[0x20]; 7538 7539 u8 reserved_at_40[0x40]; 7540 }; 7541 7542 struct mlx5_ifc_modify_hca_vport_context_in_bits { 7543 u8 opcode[0x10]; 7544 u8 reserved_at_10[0x10]; 7545 7546 u8 reserved_at_20[0x10]; 7547 u8 op_mod[0x10]; 7548 7549 u8 other_vport[0x1]; 7550 u8 reserved_at_41[0xb]; 7551 u8 port_num[0x4]; 7552 u8 vport_number[0x10]; 7553 7554 u8 reserved_at_60[0x20]; 7555 7556 struct mlx5_ifc_hca_vport_context_bits hca_vport_context; 7557 }; 7558 7559 struct mlx5_ifc_modify_cq_out_bits { 7560 u8 status[0x8]; 7561 u8 reserved_at_8[0x18]; 7562 7563 u8 syndrome[0x20]; 7564 7565 u8 reserved_at_40[0x40]; 7566 }; 7567 7568 enum { 7569 MLX5_MODIFY_CQ_IN_OP_MOD_MODIFY_CQ = 0x0, 7570 MLX5_MODIFY_CQ_IN_OP_MOD_RESIZE_CQ = 0x1, 7571 }; 7572 7573 struct mlx5_ifc_modify_cq_in_bits { 7574 u8 opcode[0x10]; 7575 u8 uid[0x10]; 7576 7577 u8 reserved_at_20[0x10]; 7578 u8 op_mod[0x10]; 7579 7580 u8 reserved_at_40[0x8]; 7581 u8 cqn[0x18]; 7582 7583 union mlx5_ifc_modify_field_select_resize_field_select_auto_bits modify_field_select_resize_field_select; 7584 7585 struct mlx5_ifc_cqc_bits cq_context; 7586 7587 u8 reserved_at_280[0x60]; 7588 7589 u8 cq_umem_valid[0x1]; 7590 u8 reserved_at_2e1[0x1f]; 7591 7592 u8 reserved_at_300[0x580]; 7593 7594 u8 pas[][0x40]; 7595 }; 7596 7597 struct mlx5_ifc_modify_cong_status_out_bits { 7598 u8 status[0x8]; 7599 u8 reserved_at_8[0x18]; 7600 7601 u8 syndrome[0x20]; 7602 7603 u8 reserved_at_40[0x40]; 7604 }; 7605 7606 struct mlx5_ifc_modify_cong_status_in_bits { 7607 u8 opcode[0x10]; 7608 u8 reserved_at_10[0x10]; 7609 7610 u8 reserved_at_20[0x10]; 7611 u8 op_mod[0x10]; 7612 7613 u8 reserved_at_40[0x18]; 7614 u8 priority[0x4]; 7615 u8 cong_protocol[0x4]; 7616 7617 u8 enable[0x1]; 7618 u8 tag_enable[0x1]; 7619 u8 reserved_at_62[0x1e]; 7620 }; 7621 7622 struct mlx5_ifc_modify_cong_params_out_bits { 7623 u8 status[0x8]; 7624 u8 reserved_at_8[0x18]; 7625 7626 u8 syndrome[0x20]; 7627 7628 u8 reserved_at_40[0x40]; 7629 }; 7630 7631 struct mlx5_ifc_modify_cong_params_in_bits { 7632 u8 opcode[0x10]; 7633 u8 reserved_at_10[0x10]; 7634 7635 u8 reserved_at_20[0x10]; 7636 u8 op_mod[0x10]; 7637 7638 u8 reserved_at_40[0x1c]; 7639 u8 cong_protocol[0x4]; 7640 7641 union mlx5_ifc_field_select_802_1_r_roce_auto_bits field_select; 7642 7643 u8 reserved_at_80[0x80]; 7644 7645 union mlx5_ifc_cong_control_roce_ecn_auto_bits congestion_parameters; 7646 }; 7647 7648 struct mlx5_ifc_manage_pages_out_bits { 7649 u8 status[0x8]; 7650 u8 reserved_at_8[0x18]; 7651 7652 u8 syndrome[0x20]; 7653 7654 u8 output_num_entries[0x20]; 7655 7656 u8 reserved_at_60[0x20]; 7657 7658 u8 pas[][0x40]; 7659 }; 7660 7661 enum { 7662 MLX5_MANAGE_PAGES_IN_OP_MOD_ALLOCATION_FAIL = 0x0, 7663 MLX5_MANAGE_PAGES_IN_OP_MOD_ALLOCATION_SUCCESS = 0x1, 7664 MLX5_MANAGE_PAGES_IN_OP_MOD_HCA_RETURN_PAGES = 0x2, 7665 }; 7666 7667 struct mlx5_ifc_manage_pages_in_bits { 7668 u8 opcode[0x10]; 7669 u8 reserved_at_10[0x10]; 7670 7671 u8 reserved_at_20[0x10]; 7672 u8 op_mod[0x10]; 7673 7674 u8 embedded_cpu_function[0x1]; 7675 u8 reserved_at_41[0xf]; 7676 u8 function_id[0x10]; 7677 7678 u8 input_num_entries[0x20]; 7679 7680 u8 pas[][0x40]; 7681 }; 7682 7683 struct mlx5_ifc_mad_ifc_out_bits { 7684 u8 status[0x8]; 7685 u8 reserved_at_8[0x18]; 7686 7687 u8 syndrome[0x20]; 7688 7689 u8 reserved_at_40[0x40]; 7690 7691 u8 response_mad_packet[256][0x8]; 7692 }; 7693 7694 struct mlx5_ifc_mad_ifc_in_bits { 7695 u8 opcode[0x10]; 7696 u8 reserved_at_10[0x10]; 7697 7698 u8 reserved_at_20[0x10]; 7699 u8 op_mod[0x10]; 7700 7701 u8 remote_lid[0x10]; 7702 u8 reserved_at_50[0x8]; 7703 u8 port[0x8]; 7704 7705 u8 reserved_at_60[0x20]; 7706 7707 u8 mad[256][0x8]; 7708 }; 7709 7710 struct mlx5_ifc_init_hca_out_bits { 7711 u8 status[0x8]; 7712 u8 reserved_at_8[0x18]; 7713 7714 u8 syndrome[0x20]; 7715 7716 u8 reserved_at_40[0x40]; 7717 }; 7718 7719 struct mlx5_ifc_init_hca_in_bits { 7720 u8 opcode[0x10]; 7721 u8 reserved_at_10[0x10]; 7722 7723 u8 reserved_at_20[0x10]; 7724 u8 op_mod[0x10]; 7725 7726 u8 reserved_at_40[0x20]; 7727 7728 u8 reserved_at_60[0x2]; 7729 u8 sw_vhca_id[0xe]; 7730 u8 reserved_at_70[0x10]; 7731 7732 u8 sw_owner_id[4][0x20]; 7733 }; 7734 7735 struct mlx5_ifc_init2rtr_qp_out_bits { 7736 u8 status[0x8]; 7737 u8 reserved_at_8[0x18]; 7738 7739 u8 syndrome[0x20]; 7740 7741 u8 reserved_at_40[0x20]; 7742 u8 ece[0x20]; 7743 }; 7744 7745 struct mlx5_ifc_init2rtr_qp_in_bits { 7746 u8 opcode[0x10]; 7747 u8 uid[0x10]; 7748 7749 u8 reserved_at_20[0x10]; 7750 u8 op_mod[0x10]; 7751 7752 u8 reserved_at_40[0x8]; 7753 u8 qpn[0x18]; 7754 7755 u8 reserved_at_60[0x20]; 7756 7757 u8 opt_param_mask[0x20]; 7758 7759 u8 ece[0x20]; 7760 7761 struct mlx5_ifc_qpc_bits qpc; 7762 7763 u8 reserved_at_800[0x80]; 7764 }; 7765 7766 struct mlx5_ifc_init2init_qp_out_bits { 7767 u8 status[0x8]; 7768 u8 reserved_at_8[0x18]; 7769 7770 u8 syndrome[0x20]; 7771 7772 u8 reserved_at_40[0x20]; 7773 u8 ece[0x20]; 7774 }; 7775 7776 struct mlx5_ifc_init2init_qp_in_bits { 7777 u8 opcode[0x10]; 7778 u8 uid[0x10]; 7779 7780 u8 reserved_at_20[0x10]; 7781 u8 op_mod[0x10]; 7782 7783 u8 reserved_at_40[0x8]; 7784 u8 qpn[0x18]; 7785 7786 u8 reserved_at_60[0x20]; 7787 7788 u8 opt_param_mask[0x20]; 7789 7790 u8 ece[0x20]; 7791 7792 struct mlx5_ifc_qpc_bits qpc; 7793 7794 u8 reserved_at_800[0x80]; 7795 }; 7796 7797 struct mlx5_ifc_get_dropped_packet_log_out_bits { 7798 u8 status[0x8]; 7799 u8 reserved_at_8[0x18]; 7800 7801 u8 syndrome[0x20]; 7802 7803 u8 reserved_at_40[0x40]; 7804 7805 u8 packet_headers_log[128][0x8]; 7806 7807 u8 packet_syndrome[64][0x8]; 7808 }; 7809 7810 struct mlx5_ifc_get_dropped_packet_log_in_bits { 7811 u8 opcode[0x10]; 7812 u8 reserved_at_10[0x10]; 7813 7814 u8 reserved_at_20[0x10]; 7815 u8 op_mod[0x10]; 7816 7817 u8 reserved_at_40[0x40]; 7818 }; 7819 7820 struct mlx5_ifc_gen_eqe_in_bits { 7821 u8 opcode[0x10]; 7822 u8 reserved_at_10[0x10]; 7823 7824 u8 reserved_at_20[0x10]; 7825 u8 op_mod[0x10]; 7826 7827 u8 reserved_at_40[0x18]; 7828 u8 eq_number[0x8]; 7829 7830 u8 reserved_at_60[0x20]; 7831 7832 u8 eqe[64][0x8]; 7833 }; 7834 7835 struct mlx5_ifc_gen_eq_out_bits { 7836 u8 status[0x8]; 7837 u8 reserved_at_8[0x18]; 7838 7839 u8 syndrome[0x20]; 7840 7841 u8 reserved_at_40[0x40]; 7842 }; 7843 7844 struct mlx5_ifc_enable_hca_out_bits { 7845 u8 status[0x8]; 7846 u8 reserved_at_8[0x18]; 7847 7848 u8 syndrome[0x20]; 7849 7850 u8 reserved_at_40[0x20]; 7851 }; 7852 7853 struct mlx5_ifc_enable_hca_in_bits { 7854 u8 opcode[0x10]; 7855 u8 reserved_at_10[0x10]; 7856 7857 u8 reserved_at_20[0x10]; 7858 u8 op_mod[0x10]; 7859 7860 u8 embedded_cpu_function[0x1]; 7861 u8 reserved_at_41[0xf]; 7862 u8 function_id[0x10]; 7863 7864 u8 reserved_at_60[0x20]; 7865 }; 7866 7867 struct mlx5_ifc_drain_dct_out_bits { 7868 u8 status[0x8]; 7869 u8 reserved_at_8[0x18]; 7870 7871 u8 syndrome[0x20]; 7872 7873 u8 reserved_at_40[0x40]; 7874 }; 7875 7876 struct mlx5_ifc_drain_dct_in_bits { 7877 u8 opcode[0x10]; 7878 u8 uid[0x10]; 7879 7880 u8 reserved_at_20[0x10]; 7881 u8 op_mod[0x10]; 7882 7883 u8 reserved_at_40[0x8]; 7884 u8 dctn[0x18]; 7885 7886 u8 reserved_at_60[0x20]; 7887 }; 7888 7889 struct mlx5_ifc_disable_hca_out_bits { 7890 u8 status[0x8]; 7891 u8 reserved_at_8[0x18]; 7892 7893 u8 syndrome[0x20]; 7894 7895 u8 reserved_at_40[0x20]; 7896 }; 7897 7898 struct mlx5_ifc_disable_hca_in_bits { 7899 u8 opcode[0x10]; 7900 u8 reserved_at_10[0x10]; 7901 7902 u8 reserved_at_20[0x10]; 7903 u8 op_mod[0x10]; 7904 7905 u8 embedded_cpu_function[0x1]; 7906 u8 reserved_at_41[0xf]; 7907 u8 function_id[0x10]; 7908 7909 u8 reserved_at_60[0x20]; 7910 }; 7911 7912 struct mlx5_ifc_detach_from_mcg_out_bits { 7913 u8 status[0x8]; 7914 u8 reserved_at_8[0x18]; 7915 7916 u8 syndrome[0x20]; 7917 7918 u8 reserved_at_40[0x40]; 7919 }; 7920 7921 struct mlx5_ifc_detach_from_mcg_in_bits { 7922 u8 opcode[0x10]; 7923 u8 uid[0x10]; 7924 7925 u8 reserved_at_20[0x10]; 7926 u8 op_mod[0x10]; 7927 7928 u8 reserved_at_40[0x8]; 7929 u8 qpn[0x18]; 7930 7931 u8 reserved_at_60[0x20]; 7932 7933 u8 multicast_gid[16][0x8]; 7934 }; 7935 7936 struct mlx5_ifc_destroy_xrq_out_bits { 7937 u8 status[0x8]; 7938 u8 reserved_at_8[0x18]; 7939 7940 u8 syndrome[0x20]; 7941 7942 u8 reserved_at_40[0x40]; 7943 }; 7944 7945 struct mlx5_ifc_destroy_xrq_in_bits { 7946 u8 opcode[0x10]; 7947 u8 uid[0x10]; 7948 7949 u8 reserved_at_20[0x10]; 7950 u8 op_mod[0x10]; 7951 7952 u8 reserved_at_40[0x8]; 7953 u8 xrqn[0x18]; 7954 7955 u8 reserved_at_60[0x20]; 7956 }; 7957 7958 struct mlx5_ifc_destroy_xrc_srq_out_bits { 7959 u8 status[0x8]; 7960 u8 reserved_at_8[0x18]; 7961 7962 u8 syndrome[0x20]; 7963 7964 u8 reserved_at_40[0x40]; 7965 }; 7966 7967 struct mlx5_ifc_destroy_xrc_srq_in_bits { 7968 u8 opcode[0x10]; 7969 u8 uid[0x10]; 7970 7971 u8 reserved_at_20[0x10]; 7972 u8 op_mod[0x10]; 7973 7974 u8 reserved_at_40[0x8]; 7975 u8 xrc_srqn[0x18]; 7976 7977 u8 reserved_at_60[0x20]; 7978 }; 7979 7980 struct mlx5_ifc_destroy_tis_out_bits { 7981 u8 status[0x8]; 7982 u8 reserved_at_8[0x18]; 7983 7984 u8 syndrome[0x20]; 7985 7986 u8 reserved_at_40[0x40]; 7987 }; 7988 7989 struct mlx5_ifc_destroy_tis_in_bits { 7990 u8 opcode[0x10]; 7991 u8 uid[0x10]; 7992 7993 u8 reserved_at_20[0x10]; 7994 u8 op_mod[0x10]; 7995 7996 u8 reserved_at_40[0x8]; 7997 u8 tisn[0x18]; 7998 7999 u8 reserved_at_60[0x20]; 8000 }; 8001 8002 struct mlx5_ifc_destroy_tir_out_bits { 8003 u8 status[0x8]; 8004 u8 reserved_at_8[0x18]; 8005 8006 u8 syndrome[0x20]; 8007 8008 u8 reserved_at_40[0x40]; 8009 }; 8010 8011 struct mlx5_ifc_destroy_tir_in_bits { 8012 u8 opcode[0x10]; 8013 u8 uid[0x10]; 8014 8015 u8 reserved_at_20[0x10]; 8016 u8 op_mod[0x10]; 8017 8018 u8 reserved_at_40[0x8]; 8019 u8 tirn[0x18]; 8020 8021 u8 reserved_at_60[0x20]; 8022 }; 8023 8024 struct mlx5_ifc_destroy_srq_out_bits { 8025 u8 status[0x8]; 8026 u8 reserved_at_8[0x18]; 8027 8028 u8 syndrome[0x20]; 8029 8030 u8 reserved_at_40[0x40]; 8031 }; 8032 8033 struct mlx5_ifc_destroy_srq_in_bits { 8034 u8 opcode[0x10]; 8035 u8 uid[0x10]; 8036 8037 u8 reserved_at_20[0x10]; 8038 u8 op_mod[0x10]; 8039 8040 u8 reserved_at_40[0x8]; 8041 u8 srqn[0x18]; 8042 8043 u8 reserved_at_60[0x20]; 8044 }; 8045 8046 struct mlx5_ifc_destroy_sq_out_bits { 8047 u8 status[0x8]; 8048 u8 reserved_at_8[0x18]; 8049 8050 u8 syndrome[0x20]; 8051 8052 u8 reserved_at_40[0x40]; 8053 }; 8054 8055 struct mlx5_ifc_destroy_sq_in_bits { 8056 u8 opcode[0x10]; 8057 u8 uid[0x10]; 8058 8059 u8 reserved_at_20[0x10]; 8060 u8 op_mod[0x10]; 8061 8062 u8 reserved_at_40[0x8]; 8063 u8 sqn[0x18]; 8064 8065 u8 reserved_at_60[0x20]; 8066 }; 8067 8068 struct mlx5_ifc_destroy_scheduling_element_out_bits { 8069 u8 status[0x8]; 8070 u8 reserved_at_8[0x18]; 8071 8072 u8 syndrome[0x20]; 8073 8074 u8 reserved_at_40[0x1c0]; 8075 }; 8076 8077 struct mlx5_ifc_destroy_scheduling_element_in_bits { 8078 u8 opcode[0x10]; 8079 u8 reserved_at_10[0x10]; 8080 8081 u8 reserved_at_20[0x10]; 8082 u8 op_mod[0x10]; 8083 8084 u8 scheduling_hierarchy[0x8]; 8085 u8 reserved_at_48[0x18]; 8086 8087 u8 scheduling_element_id[0x20]; 8088 8089 u8 reserved_at_80[0x180]; 8090 }; 8091 8092 struct mlx5_ifc_destroy_rqt_out_bits { 8093 u8 status[0x8]; 8094 u8 reserved_at_8[0x18]; 8095 8096 u8 syndrome[0x20]; 8097 8098 u8 reserved_at_40[0x40]; 8099 }; 8100 8101 struct mlx5_ifc_destroy_rqt_in_bits { 8102 u8 opcode[0x10]; 8103 u8 uid[0x10]; 8104 8105 u8 reserved_at_20[0x10]; 8106 u8 op_mod[0x10]; 8107 8108 u8 reserved_at_40[0x8]; 8109 u8 rqtn[0x18]; 8110 8111 u8 reserved_at_60[0x20]; 8112 }; 8113 8114 struct mlx5_ifc_destroy_rq_out_bits { 8115 u8 status[0x8]; 8116 u8 reserved_at_8[0x18]; 8117 8118 u8 syndrome[0x20]; 8119 8120 u8 reserved_at_40[0x40]; 8121 }; 8122 8123 struct mlx5_ifc_destroy_rq_in_bits { 8124 u8 opcode[0x10]; 8125 u8 uid[0x10]; 8126 8127 u8 reserved_at_20[0x10]; 8128 u8 op_mod[0x10]; 8129 8130 u8 reserved_at_40[0x8]; 8131 u8 rqn[0x18]; 8132 8133 u8 reserved_at_60[0x20]; 8134 }; 8135 8136 struct mlx5_ifc_set_delay_drop_params_in_bits { 8137 u8 opcode[0x10]; 8138 u8 reserved_at_10[0x10]; 8139 8140 u8 reserved_at_20[0x10]; 8141 u8 op_mod[0x10]; 8142 8143 u8 reserved_at_40[0x20]; 8144 8145 u8 reserved_at_60[0x10]; 8146 u8 delay_drop_timeout[0x10]; 8147 }; 8148 8149 struct mlx5_ifc_set_delay_drop_params_out_bits { 8150 u8 status[0x8]; 8151 u8 reserved_at_8[0x18]; 8152 8153 u8 syndrome[0x20]; 8154 8155 u8 reserved_at_40[0x40]; 8156 }; 8157 8158 struct mlx5_ifc_destroy_rmp_out_bits { 8159 u8 status[0x8]; 8160 u8 reserved_at_8[0x18]; 8161 8162 u8 syndrome[0x20]; 8163 8164 u8 reserved_at_40[0x40]; 8165 }; 8166 8167 struct mlx5_ifc_destroy_rmp_in_bits { 8168 u8 opcode[0x10]; 8169 u8 uid[0x10]; 8170 8171 u8 reserved_at_20[0x10]; 8172 u8 op_mod[0x10]; 8173 8174 u8 reserved_at_40[0x8]; 8175 u8 rmpn[0x18]; 8176 8177 u8 reserved_at_60[0x20]; 8178 }; 8179 8180 struct mlx5_ifc_destroy_qp_out_bits { 8181 u8 status[0x8]; 8182 u8 reserved_at_8[0x18]; 8183 8184 u8 syndrome[0x20]; 8185 8186 u8 reserved_at_40[0x40]; 8187 }; 8188 8189 struct mlx5_ifc_destroy_qp_in_bits { 8190 u8 opcode[0x10]; 8191 u8 uid[0x10]; 8192 8193 u8 reserved_at_20[0x10]; 8194 u8 op_mod[0x10]; 8195 8196 u8 reserved_at_40[0x8]; 8197 u8 qpn[0x18]; 8198 8199 u8 reserved_at_60[0x20]; 8200 }; 8201 8202 struct mlx5_ifc_destroy_psv_out_bits { 8203 u8 status[0x8]; 8204 u8 reserved_at_8[0x18]; 8205 8206 u8 syndrome[0x20]; 8207 8208 u8 reserved_at_40[0x40]; 8209 }; 8210 8211 struct mlx5_ifc_destroy_psv_in_bits { 8212 u8 opcode[0x10]; 8213 u8 reserved_at_10[0x10]; 8214 8215 u8 reserved_at_20[0x10]; 8216 u8 op_mod[0x10]; 8217 8218 u8 reserved_at_40[0x8]; 8219 u8 psvn[0x18]; 8220 8221 u8 reserved_at_60[0x20]; 8222 }; 8223 8224 struct mlx5_ifc_destroy_mkey_out_bits { 8225 u8 status[0x8]; 8226 u8 reserved_at_8[0x18]; 8227 8228 u8 syndrome[0x20]; 8229 8230 u8 reserved_at_40[0x40]; 8231 }; 8232 8233 struct mlx5_ifc_destroy_mkey_in_bits { 8234 u8 opcode[0x10]; 8235 u8 uid[0x10]; 8236 8237 u8 reserved_at_20[0x10]; 8238 u8 op_mod[0x10]; 8239 8240 u8 reserved_at_40[0x8]; 8241 u8 mkey_index[0x18]; 8242 8243 u8 reserved_at_60[0x20]; 8244 }; 8245 8246 struct mlx5_ifc_destroy_flow_table_out_bits { 8247 u8 status[0x8]; 8248 u8 reserved_at_8[0x18]; 8249 8250 u8 syndrome[0x20]; 8251 8252 u8 reserved_at_40[0x40]; 8253 }; 8254 8255 struct mlx5_ifc_destroy_flow_table_in_bits { 8256 u8 opcode[0x10]; 8257 u8 reserved_at_10[0x10]; 8258 8259 u8 reserved_at_20[0x10]; 8260 u8 op_mod[0x10]; 8261 8262 u8 other_vport[0x1]; 8263 u8 reserved_at_41[0xf]; 8264 u8 vport_number[0x10]; 8265 8266 u8 reserved_at_60[0x20]; 8267 8268 u8 table_type[0x8]; 8269 u8 reserved_at_88[0x18]; 8270 8271 u8 reserved_at_a0[0x8]; 8272 u8 table_id[0x18]; 8273 8274 u8 reserved_at_c0[0x140]; 8275 }; 8276 8277 struct mlx5_ifc_destroy_flow_group_out_bits { 8278 u8 status[0x8]; 8279 u8 reserved_at_8[0x18]; 8280 8281 u8 syndrome[0x20]; 8282 8283 u8 reserved_at_40[0x40]; 8284 }; 8285 8286 struct mlx5_ifc_destroy_flow_group_in_bits { 8287 u8 opcode[0x10]; 8288 u8 reserved_at_10[0x10]; 8289 8290 u8 reserved_at_20[0x10]; 8291 u8 op_mod[0x10]; 8292 8293 u8 other_vport[0x1]; 8294 u8 reserved_at_41[0xf]; 8295 u8 vport_number[0x10]; 8296 8297 u8 reserved_at_60[0x20]; 8298 8299 u8 table_type[0x8]; 8300 u8 reserved_at_88[0x18]; 8301 8302 u8 reserved_at_a0[0x8]; 8303 u8 table_id[0x18]; 8304 8305 u8 group_id[0x20]; 8306 8307 u8 reserved_at_e0[0x120]; 8308 }; 8309 8310 struct mlx5_ifc_destroy_eq_out_bits { 8311 u8 status[0x8]; 8312 u8 reserved_at_8[0x18]; 8313 8314 u8 syndrome[0x20]; 8315 8316 u8 reserved_at_40[0x40]; 8317 }; 8318 8319 struct mlx5_ifc_destroy_eq_in_bits { 8320 u8 opcode[0x10]; 8321 u8 reserved_at_10[0x10]; 8322 8323 u8 reserved_at_20[0x10]; 8324 u8 op_mod[0x10]; 8325 8326 u8 reserved_at_40[0x18]; 8327 u8 eq_number[0x8]; 8328 8329 u8 reserved_at_60[0x20]; 8330 }; 8331 8332 struct mlx5_ifc_destroy_dct_out_bits { 8333 u8 status[0x8]; 8334 u8 reserved_at_8[0x18]; 8335 8336 u8 syndrome[0x20]; 8337 8338 u8 reserved_at_40[0x40]; 8339 }; 8340 8341 struct mlx5_ifc_destroy_dct_in_bits { 8342 u8 opcode[0x10]; 8343 u8 uid[0x10]; 8344 8345 u8 reserved_at_20[0x10]; 8346 u8 op_mod[0x10]; 8347 8348 u8 reserved_at_40[0x8]; 8349 u8 dctn[0x18]; 8350 8351 u8 reserved_at_60[0x20]; 8352 }; 8353 8354 struct mlx5_ifc_destroy_cq_out_bits { 8355 u8 status[0x8]; 8356 u8 reserved_at_8[0x18]; 8357 8358 u8 syndrome[0x20]; 8359 8360 u8 reserved_at_40[0x40]; 8361 }; 8362 8363 struct mlx5_ifc_destroy_cq_in_bits { 8364 u8 opcode[0x10]; 8365 u8 uid[0x10]; 8366 8367 u8 reserved_at_20[0x10]; 8368 u8 op_mod[0x10]; 8369 8370 u8 reserved_at_40[0x8]; 8371 u8 cqn[0x18]; 8372 8373 u8 reserved_at_60[0x20]; 8374 }; 8375 8376 struct mlx5_ifc_delete_vxlan_udp_dport_out_bits { 8377 u8 status[0x8]; 8378 u8 reserved_at_8[0x18]; 8379 8380 u8 syndrome[0x20]; 8381 8382 u8 reserved_at_40[0x40]; 8383 }; 8384 8385 struct mlx5_ifc_delete_vxlan_udp_dport_in_bits { 8386 u8 opcode[0x10]; 8387 u8 reserved_at_10[0x10]; 8388 8389 u8 reserved_at_20[0x10]; 8390 u8 op_mod[0x10]; 8391 8392 u8 reserved_at_40[0x20]; 8393 8394 u8 reserved_at_60[0x10]; 8395 u8 vxlan_udp_port[0x10]; 8396 }; 8397 8398 struct mlx5_ifc_delete_l2_table_entry_out_bits { 8399 u8 status[0x8]; 8400 u8 reserved_at_8[0x18]; 8401 8402 u8 syndrome[0x20]; 8403 8404 u8 reserved_at_40[0x40]; 8405 }; 8406 8407 struct mlx5_ifc_delete_l2_table_entry_in_bits { 8408 u8 opcode[0x10]; 8409 u8 reserved_at_10[0x10]; 8410 8411 u8 reserved_at_20[0x10]; 8412 u8 op_mod[0x10]; 8413 8414 u8 reserved_at_40[0x60]; 8415 8416 u8 reserved_at_a0[0x8]; 8417 u8 table_index[0x18]; 8418 8419 u8 reserved_at_c0[0x140]; 8420 }; 8421 8422 struct mlx5_ifc_delete_fte_out_bits { 8423 u8 status[0x8]; 8424 u8 reserved_at_8[0x18]; 8425 8426 u8 syndrome[0x20]; 8427 8428 u8 reserved_at_40[0x40]; 8429 }; 8430 8431 struct mlx5_ifc_delete_fte_in_bits { 8432 u8 opcode[0x10]; 8433 u8 reserved_at_10[0x10]; 8434 8435 u8 reserved_at_20[0x10]; 8436 u8 op_mod[0x10]; 8437 8438 u8 other_vport[0x1]; 8439 u8 reserved_at_41[0xf]; 8440 u8 vport_number[0x10]; 8441 8442 u8 reserved_at_60[0x20]; 8443 8444 u8 table_type[0x8]; 8445 u8 reserved_at_88[0x18]; 8446 8447 u8 reserved_at_a0[0x8]; 8448 u8 table_id[0x18]; 8449 8450 u8 reserved_at_c0[0x40]; 8451 8452 u8 flow_index[0x20]; 8453 8454 u8 reserved_at_120[0xe0]; 8455 }; 8456 8457 struct mlx5_ifc_dealloc_xrcd_out_bits { 8458 u8 status[0x8]; 8459 u8 reserved_at_8[0x18]; 8460 8461 u8 syndrome[0x20]; 8462 8463 u8 reserved_at_40[0x40]; 8464 }; 8465 8466 struct mlx5_ifc_dealloc_xrcd_in_bits { 8467 u8 opcode[0x10]; 8468 u8 uid[0x10]; 8469 8470 u8 reserved_at_20[0x10]; 8471 u8 op_mod[0x10]; 8472 8473 u8 reserved_at_40[0x8]; 8474 u8 xrcd[0x18]; 8475 8476 u8 reserved_at_60[0x20]; 8477 }; 8478 8479 struct mlx5_ifc_dealloc_uar_out_bits { 8480 u8 status[0x8]; 8481 u8 reserved_at_8[0x18]; 8482 8483 u8 syndrome[0x20]; 8484 8485 u8 reserved_at_40[0x40]; 8486 }; 8487 8488 struct mlx5_ifc_dealloc_uar_in_bits { 8489 u8 opcode[0x10]; 8490 u8 uid[0x10]; 8491 8492 u8 reserved_at_20[0x10]; 8493 u8 op_mod[0x10]; 8494 8495 u8 reserved_at_40[0x8]; 8496 u8 uar[0x18]; 8497 8498 u8 reserved_at_60[0x20]; 8499 }; 8500 8501 struct mlx5_ifc_dealloc_transport_domain_out_bits { 8502 u8 status[0x8]; 8503 u8 reserved_at_8[0x18]; 8504 8505 u8 syndrome[0x20]; 8506 8507 u8 reserved_at_40[0x40]; 8508 }; 8509 8510 struct mlx5_ifc_dealloc_transport_domain_in_bits { 8511 u8 opcode[0x10]; 8512 u8 uid[0x10]; 8513 8514 u8 reserved_at_20[0x10]; 8515 u8 op_mod[0x10]; 8516 8517 u8 reserved_at_40[0x8]; 8518 u8 transport_domain[0x18]; 8519 8520 u8 reserved_at_60[0x20]; 8521 }; 8522 8523 struct mlx5_ifc_dealloc_q_counter_out_bits { 8524 u8 status[0x8]; 8525 u8 reserved_at_8[0x18]; 8526 8527 u8 syndrome[0x20]; 8528 8529 u8 reserved_at_40[0x40]; 8530 }; 8531 8532 struct mlx5_ifc_dealloc_q_counter_in_bits { 8533 u8 opcode[0x10]; 8534 u8 reserved_at_10[0x10]; 8535 8536 u8 reserved_at_20[0x10]; 8537 u8 op_mod[0x10]; 8538 8539 u8 reserved_at_40[0x18]; 8540 u8 counter_set_id[0x8]; 8541 8542 u8 reserved_at_60[0x20]; 8543 }; 8544 8545 struct mlx5_ifc_dealloc_pd_out_bits { 8546 u8 status[0x8]; 8547 u8 reserved_at_8[0x18]; 8548 8549 u8 syndrome[0x20]; 8550 8551 u8 reserved_at_40[0x40]; 8552 }; 8553 8554 struct mlx5_ifc_dealloc_pd_in_bits { 8555 u8 opcode[0x10]; 8556 u8 uid[0x10]; 8557 8558 u8 reserved_at_20[0x10]; 8559 u8 op_mod[0x10]; 8560 8561 u8 reserved_at_40[0x8]; 8562 u8 pd[0x18]; 8563 8564 u8 reserved_at_60[0x20]; 8565 }; 8566 8567 struct mlx5_ifc_dealloc_flow_counter_out_bits { 8568 u8 status[0x8]; 8569 u8 reserved_at_8[0x18]; 8570 8571 u8 syndrome[0x20]; 8572 8573 u8 reserved_at_40[0x40]; 8574 }; 8575 8576 struct mlx5_ifc_dealloc_flow_counter_in_bits { 8577 u8 opcode[0x10]; 8578 u8 reserved_at_10[0x10]; 8579 8580 u8 reserved_at_20[0x10]; 8581 u8 op_mod[0x10]; 8582 8583 u8 flow_counter_id[0x20]; 8584 8585 u8 reserved_at_60[0x20]; 8586 }; 8587 8588 struct mlx5_ifc_create_xrq_out_bits { 8589 u8 status[0x8]; 8590 u8 reserved_at_8[0x18]; 8591 8592 u8 syndrome[0x20]; 8593 8594 u8 reserved_at_40[0x8]; 8595 u8 xrqn[0x18]; 8596 8597 u8 reserved_at_60[0x20]; 8598 }; 8599 8600 struct mlx5_ifc_create_xrq_in_bits { 8601 u8 opcode[0x10]; 8602 u8 uid[0x10]; 8603 8604 u8 reserved_at_20[0x10]; 8605 u8 op_mod[0x10]; 8606 8607 u8 reserved_at_40[0x40]; 8608 8609 struct mlx5_ifc_xrqc_bits xrq_context; 8610 }; 8611 8612 struct mlx5_ifc_create_xrc_srq_out_bits { 8613 u8 status[0x8]; 8614 u8 reserved_at_8[0x18]; 8615 8616 u8 syndrome[0x20]; 8617 8618 u8 reserved_at_40[0x8]; 8619 u8 xrc_srqn[0x18]; 8620 8621 u8 reserved_at_60[0x20]; 8622 }; 8623 8624 struct mlx5_ifc_create_xrc_srq_in_bits { 8625 u8 opcode[0x10]; 8626 u8 uid[0x10]; 8627 8628 u8 reserved_at_20[0x10]; 8629 u8 op_mod[0x10]; 8630 8631 u8 reserved_at_40[0x40]; 8632 8633 struct mlx5_ifc_xrc_srqc_bits xrc_srq_context_entry; 8634 8635 u8 reserved_at_280[0x60]; 8636 8637 u8 xrc_srq_umem_valid[0x1]; 8638 u8 reserved_at_2e1[0x1f]; 8639 8640 u8 reserved_at_300[0x580]; 8641 8642 u8 pas[][0x40]; 8643 }; 8644 8645 struct mlx5_ifc_create_tis_out_bits { 8646 u8 status[0x8]; 8647 u8 reserved_at_8[0x18]; 8648 8649 u8 syndrome[0x20]; 8650 8651 u8 reserved_at_40[0x8]; 8652 u8 tisn[0x18]; 8653 8654 u8 reserved_at_60[0x20]; 8655 }; 8656 8657 struct mlx5_ifc_create_tis_in_bits { 8658 u8 opcode[0x10]; 8659 u8 uid[0x10]; 8660 8661 u8 reserved_at_20[0x10]; 8662 u8 op_mod[0x10]; 8663 8664 u8 reserved_at_40[0xc0]; 8665 8666 struct mlx5_ifc_tisc_bits ctx; 8667 }; 8668 8669 struct mlx5_ifc_create_tir_out_bits { 8670 u8 status[0x8]; 8671 u8 icm_address_63_40[0x18]; 8672 8673 u8 syndrome[0x20]; 8674 8675 u8 icm_address_39_32[0x8]; 8676 u8 tirn[0x18]; 8677 8678 u8 icm_address_31_0[0x20]; 8679 }; 8680 8681 struct mlx5_ifc_create_tir_in_bits { 8682 u8 opcode[0x10]; 8683 u8 uid[0x10]; 8684 8685 u8 reserved_at_20[0x10]; 8686 u8 op_mod[0x10]; 8687 8688 u8 reserved_at_40[0xc0]; 8689 8690 struct mlx5_ifc_tirc_bits ctx; 8691 }; 8692 8693 struct mlx5_ifc_create_srq_out_bits { 8694 u8 status[0x8]; 8695 u8 reserved_at_8[0x18]; 8696 8697 u8 syndrome[0x20]; 8698 8699 u8 reserved_at_40[0x8]; 8700 u8 srqn[0x18]; 8701 8702 u8 reserved_at_60[0x20]; 8703 }; 8704 8705 struct mlx5_ifc_create_srq_in_bits { 8706 u8 opcode[0x10]; 8707 u8 uid[0x10]; 8708 8709 u8 reserved_at_20[0x10]; 8710 u8 op_mod[0x10]; 8711 8712 u8 reserved_at_40[0x40]; 8713 8714 struct mlx5_ifc_srqc_bits srq_context_entry; 8715 8716 u8 reserved_at_280[0x600]; 8717 8718 u8 pas[][0x40]; 8719 }; 8720 8721 struct mlx5_ifc_create_sq_out_bits { 8722 u8 status[0x8]; 8723 u8 reserved_at_8[0x18]; 8724 8725 u8 syndrome[0x20]; 8726 8727 u8 reserved_at_40[0x8]; 8728 u8 sqn[0x18]; 8729 8730 u8 reserved_at_60[0x20]; 8731 }; 8732 8733 struct mlx5_ifc_create_sq_in_bits { 8734 u8 opcode[0x10]; 8735 u8 uid[0x10]; 8736 8737 u8 reserved_at_20[0x10]; 8738 u8 op_mod[0x10]; 8739 8740 u8 reserved_at_40[0xc0]; 8741 8742 struct mlx5_ifc_sqc_bits ctx; 8743 }; 8744 8745 struct mlx5_ifc_create_scheduling_element_out_bits { 8746 u8 status[0x8]; 8747 u8 reserved_at_8[0x18]; 8748 8749 u8 syndrome[0x20]; 8750 8751 u8 reserved_at_40[0x40]; 8752 8753 u8 scheduling_element_id[0x20]; 8754 8755 u8 reserved_at_a0[0x160]; 8756 }; 8757 8758 struct mlx5_ifc_create_scheduling_element_in_bits { 8759 u8 opcode[0x10]; 8760 u8 reserved_at_10[0x10]; 8761 8762 u8 reserved_at_20[0x10]; 8763 u8 op_mod[0x10]; 8764 8765 u8 scheduling_hierarchy[0x8]; 8766 u8 reserved_at_48[0x18]; 8767 8768 u8 reserved_at_60[0xa0]; 8769 8770 struct mlx5_ifc_scheduling_context_bits scheduling_context; 8771 8772 u8 reserved_at_300[0x100]; 8773 }; 8774 8775 struct mlx5_ifc_create_rqt_out_bits { 8776 u8 status[0x8]; 8777 u8 reserved_at_8[0x18]; 8778 8779 u8 syndrome[0x20]; 8780 8781 u8 reserved_at_40[0x8]; 8782 u8 rqtn[0x18]; 8783 8784 u8 reserved_at_60[0x20]; 8785 }; 8786 8787 struct mlx5_ifc_create_rqt_in_bits { 8788 u8 opcode[0x10]; 8789 u8 uid[0x10]; 8790 8791 u8 reserved_at_20[0x10]; 8792 u8 op_mod[0x10]; 8793 8794 u8 reserved_at_40[0xc0]; 8795 8796 struct mlx5_ifc_rqtc_bits rqt_context; 8797 }; 8798 8799 struct mlx5_ifc_create_rq_out_bits { 8800 u8 status[0x8]; 8801 u8 reserved_at_8[0x18]; 8802 8803 u8 syndrome[0x20]; 8804 8805 u8 reserved_at_40[0x8]; 8806 u8 rqn[0x18]; 8807 8808 u8 reserved_at_60[0x20]; 8809 }; 8810 8811 struct mlx5_ifc_create_rq_in_bits { 8812 u8 opcode[0x10]; 8813 u8 uid[0x10]; 8814 8815 u8 reserved_at_20[0x10]; 8816 u8 op_mod[0x10]; 8817 8818 u8 reserved_at_40[0xc0]; 8819 8820 struct mlx5_ifc_rqc_bits ctx; 8821 }; 8822 8823 struct mlx5_ifc_create_rmp_out_bits { 8824 u8 status[0x8]; 8825 u8 reserved_at_8[0x18]; 8826 8827 u8 syndrome[0x20]; 8828 8829 u8 reserved_at_40[0x8]; 8830 u8 rmpn[0x18]; 8831 8832 u8 reserved_at_60[0x20]; 8833 }; 8834 8835 struct mlx5_ifc_create_rmp_in_bits { 8836 u8 opcode[0x10]; 8837 u8 uid[0x10]; 8838 8839 u8 reserved_at_20[0x10]; 8840 u8 op_mod[0x10]; 8841 8842 u8 reserved_at_40[0xc0]; 8843 8844 struct mlx5_ifc_rmpc_bits ctx; 8845 }; 8846 8847 struct mlx5_ifc_create_qp_out_bits { 8848 u8 status[0x8]; 8849 u8 reserved_at_8[0x18]; 8850 8851 u8 syndrome[0x20]; 8852 8853 u8 reserved_at_40[0x8]; 8854 u8 qpn[0x18]; 8855 8856 u8 ece[0x20]; 8857 }; 8858 8859 struct mlx5_ifc_create_qp_in_bits { 8860 u8 opcode[0x10]; 8861 u8 uid[0x10]; 8862 8863 u8 reserved_at_20[0x10]; 8864 u8 op_mod[0x10]; 8865 8866 u8 qpc_ext[0x1]; 8867 u8 reserved_at_41[0x7]; 8868 u8 input_qpn[0x18]; 8869 8870 u8 reserved_at_60[0x20]; 8871 u8 opt_param_mask[0x20]; 8872 8873 u8 ece[0x20]; 8874 8875 struct mlx5_ifc_qpc_bits qpc; 8876 8877 u8 reserved_at_800[0x60]; 8878 8879 u8 wq_umem_valid[0x1]; 8880 u8 reserved_at_861[0x1f]; 8881 8882 u8 pas[][0x40]; 8883 }; 8884 8885 struct mlx5_ifc_create_psv_out_bits { 8886 u8 status[0x8]; 8887 u8 reserved_at_8[0x18]; 8888 8889 u8 syndrome[0x20]; 8890 8891 u8 reserved_at_40[0x40]; 8892 8893 u8 reserved_at_80[0x8]; 8894 u8 psv0_index[0x18]; 8895 8896 u8 reserved_at_a0[0x8]; 8897 u8 psv1_index[0x18]; 8898 8899 u8 reserved_at_c0[0x8]; 8900 u8 psv2_index[0x18]; 8901 8902 u8 reserved_at_e0[0x8]; 8903 u8 psv3_index[0x18]; 8904 }; 8905 8906 struct mlx5_ifc_create_psv_in_bits { 8907 u8 opcode[0x10]; 8908 u8 reserved_at_10[0x10]; 8909 8910 u8 reserved_at_20[0x10]; 8911 u8 op_mod[0x10]; 8912 8913 u8 num_psv[0x4]; 8914 u8 reserved_at_44[0x4]; 8915 u8 pd[0x18]; 8916 8917 u8 reserved_at_60[0x20]; 8918 }; 8919 8920 struct mlx5_ifc_create_mkey_out_bits { 8921 u8 status[0x8]; 8922 u8 reserved_at_8[0x18]; 8923 8924 u8 syndrome[0x20]; 8925 8926 u8 reserved_at_40[0x8]; 8927 u8 mkey_index[0x18]; 8928 8929 u8 reserved_at_60[0x20]; 8930 }; 8931 8932 struct mlx5_ifc_create_mkey_in_bits { 8933 u8 opcode[0x10]; 8934 u8 uid[0x10]; 8935 8936 u8 reserved_at_20[0x10]; 8937 u8 op_mod[0x10]; 8938 8939 u8 reserved_at_40[0x20]; 8940 8941 u8 pg_access[0x1]; 8942 u8 mkey_umem_valid[0x1]; 8943 u8 reserved_at_62[0x1e]; 8944 8945 struct mlx5_ifc_mkc_bits memory_key_mkey_entry; 8946 8947 u8 reserved_at_280[0x80]; 8948 8949 u8 translations_octword_actual_size[0x20]; 8950 8951 u8 reserved_at_320[0x560]; 8952 8953 u8 klm_pas_mtt[][0x20]; 8954 }; 8955 8956 enum { 8957 MLX5_FLOW_TABLE_TYPE_NIC_RX = 0x0, 8958 MLX5_FLOW_TABLE_TYPE_NIC_TX = 0x1, 8959 MLX5_FLOW_TABLE_TYPE_ESW_EGRESS_ACL = 0x2, 8960 MLX5_FLOW_TABLE_TYPE_ESW_INGRESS_ACL = 0x3, 8961 MLX5_FLOW_TABLE_TYPE_FDB = 0X4, 8962 MLX5_FLOW_TABLE_TYPE_SNIFFER_RX = 0X5, 8963 MLX5_FLOW_TABLE_TYPE_SNIFFER_TX = 0X6, 8964 }; 8965 8966 struct mlx5_ifc_create_flow_table_out_bits { 8967 u8 status[0x8]; 8968 u8 icm_address_63_40[0x18]; 8969 8970 u8 syndrome[0x20]; 8971 8972 u8 icm_address_39_32[0x8]; 8973 u8 table_id[0x18]; 8974 8975 u8 icm_address_31_0[0x20]; 8976 }; 8977 8978 struct mlx5_ifc_create_flow_table_in_bits { 8979 u8 opcode[0x10]; 8980 u8 uid[0x10]; 8981 8982 u8 reserved_at_20[0x10]; 8983 u8 op_mod[0x10]; 8984 8985 u8 other_vport[0x1]; 8986 u8 reserved_at_41[0xf]; 8987 u8 vport_number[0x10]; 8988 8989 u8 reserved_at_60[0x20]; 8990 8991 u8 table_type[0x8]; 8992 u8 reserved_at_88[0x18]; 8993 8994 u8 reserved_at_a0[0x20]; 8995 8996 struct mlx5_ifc_flow_table_context_bits flow_table_context; 8997 }; 8998 8999 struct mlx5_ifc_create_flow_group_out_bits { 9000 u8 status[0x8]; 9001 u8 reserved_at_8[0x18]; 9002 9003 u8 syndrome[0x20]; 9004 9005 u8 reserved_at_40[0x8]; 9006 u8 group_id[0x18]; 9007 9008 u8 reserved_at_60[0x20]; 9009 }; 9010 9011 enum { 9012 MLX5_CREATE_FLOW_GROUP_IN_GROUP_TYPE_TCAM_SUBTABLE = 0x0, 9013 MLX5_CREATE_FLOW_GROUP_IN_GROUP_TYPE_HASH_SPLIT = 0x1, 9014 }; 9015 9016 enum { 9017 MLX5_CREATE_FLOW_GROUP_IN_MATCH_CRITERIA_ENABLE_OUTER_HEADERS = 0x0, 9018 MLX5_CREATE_FLOW_GROUP_IN_MATCH_CRITERIA_ENABLE_MISC_PARAMETERS = 0x1, 9019 MLX5_CREATE_FLOW_GROUP_IN_MATCH_CRITERIA_ENABLE_INNER_HEADERS = 0x2, 9020 MLX5_CREATE_FLOW_GROUP_IN_MATCH_CRITERIA_ENABLE_MISC_PARAMETERS_2 = 0x3, 9021 }; 9022 9023 struct mlx5_ifc_create_flow_group_in_bits { 9024 u8 opcode[0x10]; 9025 u8 reserved_at_10[0x10]; 9026 9027 u8 reserved_at_20[0x10]; 9028 u8 op_mod[0x10]; 9029 9030 u8 other_vport[0x1]; 9031 u8 reserved_at_41[0xf]; 9032 u8 vport_number[0x10]; 9033 9034 u8 reserved_at_60[0x20]; 9035 9036 u8 table_type[0x8]; 9037 u8 reserved_at_88[0x4]; 9038 u8 group_type[0x4]; 9039 u8 reserved_at_90[0x10]; 9040 9041 u8 reserved_at_a0[0x8]; 9042 u8 table_id[0x18]; 9043 9044 u8 source_eswitch_owner_vhca_id_valid[0x1]; 9045 9046 u8 reserved_at_c1[0x1f]; 9047 9048 u8 start_flow_index[0x20]; 9049 9050 u8 reserved_at_100[0x20]; 9051 9052 u8 end_flow_index[0x20]; 9053 9054 u8 reserved_at_140[0x10]; 9055 u8 match_definer_id[0x10]; 9056 9057 u8 reserved_at_160[0x80]; 9058 9059 u8 reserved_at_1e0[0x18]; 9060 u8 match_criteria_enable[0x8]; 9061 9062 struct mlx5_ifc_fte_match_param_bits match_criteria; 9063 9064 u8 reserved_at_1200[0xe00]; 9065 }; 9066 9067 struct mlx5_ifc_create_eq_out_bits { 9068 u8 status[0x8]; 9069 u8 reserved_at_8[0x18]; 9070 9071 u8 syndrome[0x20]; 9072 9073 u8 reserved_at_40[0x18]; 9074 u8 eq_number[0x8]; 9075 9076 u8 reserved_at_60[0x20]; 9077 }; 9078 9079 struct mlx5_ifc_create_eq_in_bits { 9080 u8 opcode[0x10]; 9081 u8 uid[0x10]; 9082 9083 u8 reserved_at_20[0x10]; 9084 u8 op_mod[0x10]; 9085 9086 u8 reserved_at_40[0x40]; 9087 9088 struct mlx5_ifc_eqc_bits eq_context_entry; 9089 9090 u8 reserved_at_280[0x40]; 9091 9092 u8 event_bitmask[4][0x40]; 9093 9094 u8 reserved_at_3c0[0x4c0]; 9095 9096 u8 pas[][0x40]; 9097 }; 9098 9099 struct mlx5_ifc_create_dct_out_bits { 9100 u8 status[0x8]; 9101 u8 reserved_at_8[0x18]; 9102 9103 u8 syndrome[0x20]; 9104 9105 u8 reserved_at_40[0x8]; 9106 u8 dctn[0x18]; 9107 9108 u8 ece[0x20]; 9109 }; 9110 9111 struct mlx5_ifc_create_dct_in_bits { 9112 u8 opcode[0x10]; 9113 u8 uid[0x10]; 9114 9115 u8 reserved_at_20[0x10]; 9116 u8 op_mod[0x10]; 9117 9118 u8 reserved_at_40[0x40]; 9119 9120 struct mlx5_ifc_dctc_bits dct_context_entry; 9121 9122 u8 reserved_at_280[0x180]; 9123 }; 9124 9125 struct mlx5_ifc_create_cq_out_bits { 9126 u8 status[0x8]; 9127 u8 reserved_at_8[0x18]; 9128 9129 u8 syndrome[0x20]; 9130 9131 u8 reserved_at_40[0x8]; 9132 u8 cqn[0x18]; 9133 9134 u8 reserved_at_60[0x20]; 9135 }; 9136 9137 struct mlx5_ifc_create_cq_in_bits { 9138 u8 opcode[0x10]; 9139 u8 uid[0x10]; 9140 9141 u8 reserved_at_20[0x10]; 9142 u8 op_mod[0x10]; 9143 9144 u8 reserved_at_40[0x40]; 9145 9146 struct mlx5_ifc_cqc_bits cq_context; 9147 9148 u8 reserved_at_280[0x60]; 9149 9150 u8 cq_umem_valid[0x1]; 9151 u8 reserved_at_2e1[0x59f]; 9152 9153 u8 pas[][0x40]; 9154 }; 9155 9156 struct mlx5_ifc_config_int_moderation_out_bits { 9157 u8 status[0x8]; 9158 u8 reserved_at_8[0x18]; 9159 9160 u8 syndrome[0x20]; 9161 9162 u8 reserved_at_40[0x4]; 9163 u8 min_delay[0xc]; 9164 u8 int_vector[0x10]; 9165 9166 u8 reserved_at_60[0x20]; 9167 }; 9168 9169 enum { 9170 MLX5_CONFIG_INT_MODERATION_IN_OP_MOD_WRITE = 0x0, 9171 MLX5_CONFIG_INT_MODERATION_IN_OP_MOD_READ = 0x1, 9172 }; 9173 9174 struct mlx5_ifc_config_int_moderation_in_bits { 9175 u8 opcode[0x10]; 9176 u8 reserved_at_10[0x10]; 9177 9178 u8 reserved_at_20[0x10]; 9179 u8 op_mod[0x10]; 9180 9181 u8 reserved_at_40[0x4]; 9182 u8 min_delay[0xc]; 9183 u8 int_vector[0x10]; 9184 9185 u8 reserved_at_60[0x20]; 9186 }; 9187 9188 struct mlx5_ifc_attach_to_mcg_out_bits { 9189 u8 status[0x8]; 9190 u8 reserved_at_8[0x18]; 9191 9192 u8 syndrome[0x20]; 9193 9194 u8 reserved_at_40[0x40]; 9195 }; 9196 9197 struct mlx5_ifc_attach_to_mcg_in_bits { 9198 u8 opcode[0x10]; 9199 u8 uid[0x10]; 9200 9201 u8 reserved_at_20[0x10]; 9202 u8 op_mod[0x10]; 9203 9204 u8 reserved_at_40[0x8]; 9205 u8 qpn[0x18]; 9206 9207 u8 reserved_at_60[0x20]; 9208 9209 u8 multicast_gid[16][0x8]; 9210 }; 9211 9212 struct mlx5_ifc_arm_xrq_out_bits { 9213 u8 status[0x8]; 9214 u8 reserved_at_8[0x18]; 9215 9216 u8 syndrome[0x20]; 9217 9218 u8 reserved_at_40[0x40]; 9219 }; 9220 9221 struct mlx5_ifc_arm_xrq_in_bits { 9222 u8 opcode[0x10]; 9223 u8 reserved_at_10[0x10]; 9224 9225 u8 reserved_at_20[0x10]; 9226 u8 op_mod[0x10]; 9227 9228 u8 reserved_at_40[0x8]; 9229 u8 xrqn[0x18]; 9230 9231 u8 reserved_at_60[0x10]; 9232 u8 lwm[0x10]; 9233 }; 9234 9235 struct mlx5_ifc_arm_xrc_srq_out_bits { 9236 u8 status[0x8]; 9237 u8 reserved_at_8[0x18]; 9238 9239 u8 syndrome[0x20]; 9240 9241 u8 reserved_at_40[0x40]; 9242 }; 9243 9244 enum { 9245 MLX5_ARM_XRC_SRQ_IN_OP_MOD_XRC_SRQ = 0x1, 9246 }; 9247 9248 struct mlx5_ifc_arm_xrc_srq_in_bits { 9249 u8 opcode[0x10]; 9250 u8 uid[0x10]; 9251 9252 u8 reserved_at_20[0x10]; 9253 u8 op_mod[0x10]; 9254 9255 u8 reserved_at_40[0x8]; 9256 u8 xrc_srqn[0x18]; 9257 9258 u8 reserved_at_60[0x10]; 9259 u8 lwm[0x10]; 9260 }; 9261 9262 struct mlx5_ifc_arm_rq_out_bits { 9263 u8 status[0x8]; 9264 u8 reserved_at_8[0x18]; 9265 9266 u8 syndrome[0x20]; 9267 9268 u8 reserved_at_40[0x40]; 9269 }; 9270 9271 enum { 9272 MLX5_ARM_RQ_IN_OP_MOD_SRQ = 0x1, 9273 MLX5_ARM_RQ_IN_OP_MOD_XRQ = 0x2, 9274 }; 9275 9276 struct mlx5_ifc_arm_rq_in_bits { 9277 u8 opcode[0x10]; 9278 u8 uid[0x10]; 9279 9280 u8 reserved_at_20[0x10]; 9281 u8 op_mod[0x10]; 9282 9283 u8 reserved_at_40[0x8]; 9284 u8 srq_number[0x18]; 9285 9286 u8 reserved_at_60[0x10]; 9287 u8 lwm[0x10]; 9288 }; 9289 9290 struct mlx5_ifc_arm_dct_out_bits { 9291 u8 status[0x8]; 9292 u8 reserved_at_8[0x18]; 9293 9294 u8 syndrome[0x20]; 9295 9296 u8 reserved_at_40[0x40]; 9297 }; 9298 9299 struct mlx5_ifc_arm_dct_in_bits { 9300 u8 opcode[0x10]; 9301 u8 reserved_at_10[0x10]; 9302 9303 u8 reserved_at_20[0x10]; 9304 u8 op_mod[0x10]; 9305 9306 u8 reserved_at_40[0x8]; 9307 u8 dct_number[0x18]; 9308 9309 u8 reserved_at_60[0x20]; 9310 }; 9311 9312 struct mlx5_ifc_alloc_xrcd_out_bits { 9313 u8 status[0x8]; 9314 u8 reserved_at_8[0x18]; 9315 9316 u8 syndrome[0x20]; 9317 9318 u8 reserved_at_40[0x8]; 9319 u8 xrcd[0x18]; 9320 9321 u8 reserved_at_60[0x20]; 9322 }; 9323 9324 struct mlx5_ifc_alloc_xrcd_in_bits { 9325 u8 opcode[0x10]; 9326 u8 uid[0x10]; 9327 9328 u8 reserved_at_20[0x10]; 9329 u8 op_mod[0x10]; 9330 9331 u8 reserved_at_40[0x40]; 9332 }; 9333 9334 struct mlx5_ifc_alloc_uar_out_bits { 9335 u8 status[0x8]; 9336 u8 reserved_at_8[0x18]; 9337 9338 u8 syndrome[0x20]; 9339 9340 u8 reserved_at_40[0x8]; 9341 u8 uar[0x18]; 9342 9343 u8 reserved_at_60[0x20]; 9344 }; 9345 9346 struct mlx5_ifc_alloc_uar_in_bits { 9347 u8 opcode[0x10]; 9348 u8 uid[0x10]; 9349 9350 u8 reserved_at_20[0x10]; 9351 u8 op_mod[0x10]; 9352 9353 u8 reserved_at_40[0x40]; 9354 }; 9355 9356 struct mlx5_ifc_alloc_transport_domain_out_bits { 9357 u8 status[0x8]; 9358 u8 reserved_at_8[0x18]; 9359 9360 u8 syndrome[0x20]; 9361 9362 u8 reserved_at_40[0x8]; 9363 u8 transport_domain[0x18]; 9364 9365 u8 reserved_at_60[0x20]; 9366 }; 9367 9368 struct mlx5_ifc_alloc_transport_domain_in_bits { 9369 u8 opcode[0x10]; 9370 u8 uid[0x10]; 9371 9372 u8 reserved_at_20[0x10]; 9373 u8 op_mod[0x10]; 9374 9375 u8 reserved_at_40[0x40]; 9376 }; 9377 9378 struct mlx5_ifc_alloc_q_counter_out_bits { 9379 u8 status[0x8]; 9380 u8 reserved_at_8[0x18]; 9381 9382 u8 syndrome[0x20]; 9383 9384 u8 reserved_at_40[0x18]; 9385 u8 counter_set_id[0x8]; 9386 9387 u8 reserved_at_60[0x20]; 9388 }; 9389 9390 struct mlx5_ifc_alloc_q_counter_in_bits { 9391 u8 opcode[0x10]; 9392 u8 uid[0x10]; 9393 9394 u8 reserved_at_20[0x10]; 9395 u8 op_mod[0x10]; 9396 9397 u8 reserved_at_40[0x40]; 9398 }; 9399 9400 struct mlx5_ifc_alloc_pd_out_bits { 9401 u8 status[0x8]; 9402 u8 reserved_at_8[0x18]; 9403 9404 u8 syndrome[0x20]; 9405 9406 u8 reserved_at_40[0x8]; 9407 u8 pd[0x18]; 9408 9409 u8 reserved_at_60[0x20]; 9410 }; 9411 9412 struct mlx5_ifc_alloc_pd_in_bits { 9413 u8 opcode[0x10]; 9414 u8 uid[0x10]; 9415 9416 u8 reserved_at_20[0x10]; 9417 u8 op_mod[0x10]; 9418 9419 u8 reserved_at_40[0x40]; 9420 }; 9421 9422 struct mlx5_ifc_alloc_flow_counter_out_bits { 9423 u8 status[0x8]; 9424 u8 reserved_at_8[0x18]; 9425 9426 u8 syndrome[0x20]; 9427 9428 u8 flow_counter_id[0x20]; 9429 9430 u8 reserved_at_60[0x20]; 9431 }; 9432 9433 struct mlx5_ifc_alloc_flow_counter_in_bits { 9434 u8 opcode[0x10]; 9435 u8 reserved_at_10[0x10]; 9436 9437 u8 reserved_at_20[0x10]; 9438 u8 op_mod[0x10]; 9439 9440 u8 reserved_at_40[0x33]; 9441 u8 flow_counter_bulk_log_size[0x5]; 9442 u8 flow_counter_bulk[0x8]; 9443 }; 9444 9445 struct mlx5_ifc_add_vxlan_udp_dport_out_bits { 9446 u8 status[0x8]; 9447 u8 reserved_at_8[0x18]; 9448 9449 u8 syndrome[0x20]; 9450 9451 u8 reserved_at_40[0x40]; 9452 }; 9453 9454 struct mlx5_ifc_add_vxlan_udp_dport_in_bits { 9455 u8 opcode[0x10]; 9456 u8 reserved_at_10[0x10]; 9457 9458 u8 reserved_at_20[0x10]; 9459 u8 op_mod[0x10]; 9460 9461 u8 reserved_at_40[0x20]; 9462 9463 u8 reserved_at_60[0x10]; 9464 u8 vxlan_udp_port[0x10]; 9465 }; 9466 9467 struct mlx5_ifc_set_pp_rate_limit_out_bits { 9468 u8 status[0x8]; 9469 u8 reserved_at_8[0x18]; 9470 9471 u8 syndrome[0x20]; 9472 9473 u8 reserved_at_40[0x40]; 9474 }; 9475 9476 struct mlx5_ifc_set_pp_rate_limit_context_bits { 9477 u8 rate_limit[0x20]; 9478 9479 u8 burst_upper_bound[0x20]; 9480 9481 u8 reserved_at_40[0x10]; 9482 u8 typical_packet_size[0x10]; 9483 9484 u8 reserved_at_60[0x120]; 9485 }; 9486 9487 struct mlx5_ifc_set_pp_rate_limit_in_bits { 9488 u8 opcode[0x10]; 9489 u8 uid[0x10]; 9490 9491 u8 reserved_at_20[0x10]; 9492 u8 op_mod[0x10]; 9493 9494 u8 reserved_at_40[0x10]; 9495 u8 rate_limit_index[0x10]; 9496 9497 u8 reserved_at_60[0x20]; 9498 9499 struct mlx5_ifc_set_pp_rate_limit_context_bits ctx; 9500 }; 9501 9502 struct mlx5_ifc_access_register_out_bits { 9503 u8 status[0x8]; 9504 u8 reserved_at_8[0x18]; 9505 9506 u8 syndrome[0x20]; 9507 9508 u8 reserved_at_40[0x40]; 9509 9510 u8 register_data[][0x20]; 9511 }; 9512 9513 enum { 9514 MLX5_ACCESS_REGISTER_IN_OP_MOD_WRITE = 0x0, 9515 MLX5_ACCESS_REGISTER_IN_OP_MOD_READ = 0x1, 9516 }; 9517 9518 struct mlx5_ifc_access_register_in_bits { 9519 u8 opcode[0x10]; 9520 u8 reserved_at_10[0x10]; 9521 9522 u8 reserved_at_20[0x10]; 9523 u8 op_mod[0x10]; 9524 9525 u8 reserved_at_40[0x10]; 9526 u8 register_id[0x10]; 9527 9528 u8 argument[0x20]; 9529 9530 u8 register_data[][0x20]; 9531 }; 9532 9533 struct mlx5_ifc_sltp_reg_bits { 9534 u8 status[0x4]; 9535 u8 version[0x4]; 9536 u8 local_port[0x8]; 9537 u8 pnat[0x2]; 9538 u8 reserved_at_12[0x2]; 9539 u8 lane[0x4]; 9540 u8 reserved_at_18[0x8]; 9541 9542 u8 reserved_at_20[0x20]; 9543 9544 u8 reserved_at_40[0x7]; 9545 u8 polarity[0x1]; 9546 u8 ob_tap0[0x8]; 9547 u8 ob_tap1[0x8]; 9548 u8 ob_tap2[0x8]; 9549 9550 u8 reserved_at_60[0xc]; 9551 u8 ob_preemp_mode[0x4]; 9552 u8 ob_reg[0x8]; 9553 u8 ob_bias[0x8]; 9554 9555 u8 reserved_at_80[0x20]; 9556 }; 9557 9558 struct mlx5_ifc_slrg_reg_bits { 9559 u8 status[0x4]; 9560 u8 version[0x4]; 9561 u8 local_port[0x8]; 9562 u8 pnat[0x2]; 9563 u8 reserved_at_12[0x2]; 9564 u8 lane[0x4]; 9565 u8 reserved_at_18[0x8]; 9566 9567 u8 time_to_link_up[0x10]; 9568 u8 reserved_at_30[0xc]; 9569 u8 grade_lane_speed[0x4]; 9570 9571 u8 grade_version[0x8]; 9572 u8 grade[0x18]; 9573 9574 u8 reserved_at_60[0x4]; 9575 u8 height_grade_type[0x4]; 9576 u8 height_grade[0x18]; 9577 9578 u8 height_dz[0x10]; 9579 u8 height_dv[0x10]; 9580 9581 u8 reserved_at_a0[0x10]; 9582 u8 height_sigma[0x10]; 9583 9584 u8 reserved_at_c0[0x20]; 9585 9586 u8 reserved_at_e0[0x4]; 9587 u8 phase_grade_type[0x4]; 9588 u8 phase_grade[0x18]; 9589 9590 u8 reserved_at_100[0x8]; 9591 u8 phase_eo_pos[0x8]; 9592 u8 reserved_at_110[0x8]; 9593 u8 phase_eo_neg[0x8]; 9594 9595 u8 ffe_set_tested[0x10]; 9596 u8 test_errors_per_lane[0x10]; 9597 }; 9598 9599 struct mlx5_ifc_pvlc_reg_bits { 9600 u8 reserved_at_0[0x8]; 9601 u8 local_port[0x8]; 9602 u8 reserved_at_10[0x10]; 9603 9604 u8 reserved_at_20[0x1c]; 9605 u8 vl_hw_cap[0x4]; 9606 9607 u8 reserved_at_40[0x1c]; 9608 u8 vl_admin[0x4]; 9609 9610 u8 reserved_at_60[0x1c]; 9611 u8 vl_operational[0x4]; 9612 }; 9613 9614 struct mlx5_ifc_pude_reg_bits { 9615 u8 swid[0x8]; 9616 u8 local_port[0x8]; 9617 u8 reserved_at_10[0x4]; 9618 u8 admin_status[0x4]; 9619 u8 reserved_at_18[0x4]; 9620 u8 oper_status[0x4]; 9621 9622 u8 reserved_at_20[0x60]; 9623 }; 9624 9625 struct mlx5_ifc_ptys_reg_bits { 9626 u8 reserved_at_0[0x1]; 9627 u8 an_disable_admin[0x1]; 9628 u8 an_disable_cap[0x1]; 9629 u8 reserved_at_3[0x5]; 9630 u8 local_port[0x8]; 9631 u8 reserved_at_10[0xd]; 9632 u8 proto_mask[0x3]; 9633 9634 u8 an_status[0x4]; 9635 u8 reserved_at_24[0xc]; 9636 u8 data_rate_oper[0x10]; 9637 9638 u8 ext_eth_proto_capability[0x20]; 9639 9640 u8 eth_proto_capability[0x20]; 9641 9642 u8 ib_link_width_capability[0x10]; 9643 u8 ib_proto_capability[0x10]; 9644 9645 u8 ext_eth_proto_admin[0x20]; 9646 9647 u8 eth_proto_admin[0x20]; 9648 9649 u8 ib_link_width_admin[0x10]; 9650 u8 ib_proto_admin[0x10]; 9651 9652 u8 ext_eth_proto_oper[0x20]; 9653 9654 u8 eth_proto_oper[0x20]; 9655 9656 u8 ib_link_width_oper[0x10]; 9657 u8 ib_proto_oper[0x10]; 9658 9659 u8 reserved_at_160[0x1c]; 9660 u8 connector_type[0x4]; 9661 9662 u8 eth_proto_lp_advertise[0x20]; 9663 9664 u8 reserved_at_1a0[0x60]; 9665 }; 9666 9667 struct mlx5_ifc_mlcr_reg_bits { 9668 u8 reserved_at_0[0x8]; 9669 u8 local_port[0x8]; 9670 u8 reserved_at_10[0x20]; 9671 9672 u8 beacon_duration[0x10]; 9673 u8 reserved_at_40[0x10]; 9674 9675 u8 beacon_remain[0x10]; 9676 }; 9677 9678 struct mlx5_ifc_ptas_reg_bits { 9679 u8 reserved_at_0[0x20]; 9680 9681 u8 algorithm_options[0x10]; 9682 u8 reserved_at_30[0x4]; 9683 u8 repetitions_mode[0x4]; 9684 u8 num_of_repetitions[0x8]; 9685 9686 u8 grade_version[0x8]; 9687 u8 height_grade_type[0x4]; 9688 u8 phase_grade_type[0x4]; 9689 u8 height_grade_weight[0x8]; 9690 u8 phase_grade_weight[0x8]; 9691 9692 u8 gisim_measure_bits[0x10]; 9693 u8 adaptive_tap_measure_bits[0x10]; 9694 9695 u8 ber_bath_high_error_threshold[0x10]; 9696 u8 ber_bath_mid_error_threshold[0x10]; 9697 9698 u8 ber_bath_low_error_threshold[0x10]; 9699 u8 one_ratio_high_threshold[0x10]; 9700 9701 u8 one_ratio_high_mid_threshold[0x10]; 9702 u8 one_ratio_low_mid_threshold[0x10]; 9703 9704 u8 one_ratio_low_threshold[0x10]; 9705 u8 ndeo_error_threshold[0x10]; 9706 9707 u8 mixer_offset_step_size[0x10]; 9708 u8 reserved_at_110[0x8]; 9709 u8 mix90_phase_for_voltage_bath[0x8]; 9710 9711 u8 mixer_offset_start[0x10]; 9712 u8 mixer_offset_end[0x10]; 9713 9714 u8 reserved_at_140[0x15]; 9715 u8 ber_test_time[0xb]; 9716 }; 9717 9718 struct mlx5_ifc_pspa_reg_bits { 9719 u8 swid[0x8]; 9720 u8 local_port[0x8]; 9721 u8 sub_port[0x8]; 9722 u8 reserved_at_18[0x8]; 9723 9724 u8 reserved_at_20[0x20]; 9725 }; 9726 9727 struct mlx5_ifc_pqdr_reg_bits { 9728 u8 reserved_at_0[0x8]; 9729 u8 local_port[0x8]; 9730 u8 reserved_at_10[0x5]; 9731 u8 prio[0x3]; 9732 u8 reserved_at_18[0x6]; 9733 u8 mode[0x2]; 9734 9735 u8 reserved_at_20[0x20]; 9736 9737 u8 reserved_at_40[0x10]; 9738 u8 min_threshold[0x10]; 9739 9740 u8 reserved_at_60[0x10]; 9741 u8 max_threshold[0x10]; 9742 9743 u8 reserved_at_80[0x10]; 9744 u8 mark_probability_denominator[0x10]; 9745 9746 u8 reserved_at_a0[0x60]; 9747 }; 9748 9749 struct mlx5_ifc_ppsc_reg_bits { 9750 u8 reserved_at_0[0x8]; 9751 u8 local_port[0x8]; 9752 u8 reserved_at_10[0x10]; 9753 9754 u8 reserved_at_20[0x60]; 9755 9756 u8 reserved_at_80[0x1c]; 9757 u8 wrps_admin[0x4]; 9758 9759 u8 reserved_at_a0[0x1c]; 9760 u8 wrps_status[0x4]; 9761 9762 u8 reserved_at_c0[0x8]; 9763 u8 up_threshold[0x8]; 9764 u8 reserved_at_d0[0x8]; 9765 u8 down_threshold[0x8]; 9766 9767 u8 reserved_at_e0[0x20]; 9768 9769 u8 reserved_at_100[0x1c]; 9770 u8 srps_admin[0x4]; 9771 9772 u8 reserved_at_120[0x1c]; 9773 u8 srps_status[0x4]; 9774 9775 u8 reserved_at_140[0x40]; 9776 }; 9777 9778 struct mlx5_ifc_pplr_reg_bits { 9779 u8 reserved_at_0[0x8]; 9780 u8 local_port[0x8]; 9781 u8 reserved_at_10[0x10]; 9782 9783 u8 reserved_at_20[0x8]; 9784 u8 lb_cap[0x8]; 9785 u8 reserved_at_30[0x8]; 9786 u8 lb_en[0x8]; 9787 }; 9788 9789 struct mlx5_ifc_pplm_reg_bits { 9790 u8 reserved_at_0[0x8]; 9791 u8 local_port[0x8]; 9792 u8 reserved_at_10[0x10]; 9793 9794 u8 reserved_at_20[0x20]; 9795 9796 u8 port_profile_mode[0x8]; 9797 u8 static_port_profile[0x8]; 9798 u8 active_port_profile[0x8]; 9799 u8 reserved_at_58[0x8]; 9800 9801 u8 retransmission_active[0x8]; 9802 u8 fec_mode_active[0x18]; 9803 9804 u8 rs_fec_correction_bypass_cap[0x4]; 9805 u8 reserved_at_84[0x8]; 9806 u8 fec_override_cap_56g[0x4]; 9807 u8 fec_override_cap_100g[0x4]; 9808 u8 fec_override_cap_50g[0x4]; 9809 u8 fec_override_cap_25g[0x4]; 9810 u8 fec_override_cap_10g_40g[0x4]; 9811 9812 u8 rs_fec_correction_bypass_admin[0x4]; 9813 u8 reserved_at_a4[0x8]; 9814 u8 fec_override_admin_56g[0x4]; 9815 u8 fec_override_admin_100g[0x4]; 9816 u8 fec_override_admin_50g[0x4]; 9817 u8 fec_override_admin_25g[0x4]; 9818 u8 fec_override_admin_10g_40g[0x4]; 9819 9820 u8 fec_override_cap_400g_8x[0x10]; 9821 u8 fec_override_cap_200g_4x[0x10]; 9822 9823 u8 fec_override_cap_100g_2x[0x10]; 9824 u8 fec_override_cap_50g_1x[0x10]; 9825 9826 u8 fec_override_admin_400g_8x[0x10]; 9827 u8 fec_override_admin_200g_4x[0x10]; 9828 9829 u8 fec_override_admin_100g_2x[0x10]; 9830 u8 fec_override_admin_50g_1x[0x10]; 9831 9832 u8 fec_override_cap_800g_8x[0x10]; 9833 u8 fec_override_cap_400g_4x[0x10]; 9834 9835 u8 fec_override_cap_200g_2x[0x10]; 9836 u8 fec_override_cap_100g_1x[0x10]; 9837 9838 u8 reserved_at_180[0xa0]; 9839 9840 u8 fec_override_admin_800g_8x[0x10]; 9841 u8 fec_override_admin_400g_4x[0x10]; 9842 9843 u8 fec_override_admin_200g_2x[0x10]; 9844 u8 fec_override_admin_100g_1x[0x10]; 9845 9846 u8 reserved_at_260[0x20]; 9847 }; 9848 9849 struct mlx5_ifc_ppcnt_reg_bits { 9850 u8 swid[0x8]; 9851 u8 local_port[0x8]; 9852 u8 pnat[0x2]; 9853 u8 reserved_at_12[0x8]; 9854 u8 grp[0x6]; 9855 9856 u8 clr[0x1]; 9857 u8 reserved_at_21[0x1c]; 9858 u8 prio_tc[0x3]; 9859 9860 union mlx5_ifc_eth_cntrs_grp_data_layout_auto_bits counter_set; 9861 }; 9862 9863 struct mlx5_ifc_mpein_reg_bits { 9864 u8 reserved_at_0[0x2]; 9865 u8 depth[0x6]; 9866 u8 pcie_index[0x8]; 9867 u8 node[0x8]; 9868 u8 reserved_at_18[0x8]; 9869 9870 u8 capability_mask[0x20]; 9871 9872 u8 reserved_at_40[0x8]; 9873 u8 link_width_enabled[0x8]; 9874 u8 link_speed_enabled[0x10]; 9875 9876 u8 lane0_physical_position[0x8]; 9877 u8 link_width_active[0x8]; 9878 u8 link_speed_active[0x10]; 9879 9880 u8 num_of_pfs[0x10]; 9881 u8 num_of_vfs[0x10]; 9882 9883 u8 bdf0[0x10]; 9884 u8 reserved_at_b0[0x10]; 9885 9886 u8 max_read_request_size[0x4]; 9887 u8 max_payload_size[0x4]; 9888 u8 reserved_at_c8[0x5]; 9889 u8 pwr_status[0x3]; 9890 u8 port_type[0x4]; 9891 u8 reserved_at_d4[0xb]; 9892 u8 lane_reversal[0x1]; 9893 9894 u8 reserved_at_e0[0x14]; 9895 u8 pci_power[0xc]; 9896 9897 u8 reserved_at_100[0x20]; 9898 9899 u8 device_status[0x10]; 9900 u8 port_state[0x8]; 9901 u8 reserved_at_138[0x8]; 9902 9903 u8 reserved_at_140[0x10]; 9904 u8 receiver_detect_result[0x10]; 9905 9906 u8 reserved_at_160[0x20]; 9907 }; 9908 9909 struct mlx5_ifc_mpcnt_reg_bits { 9910 u8 reserved_at_0[0x8]; 9911 u8 pcie_index[0x8]; 9912 u8 reserved_at_10[0xa]; 9913 u8 grp[0x6]; 9914 9915 u8 clr[0x1]; 9916 u8 reserved_at_21[0x1f]; 9917 9918 union mlx5_ifc_pcie_cntrs_grp_data_layout_auto_bits counter_set; 9919 }; 9920 9921 struct mlx5_ifc_ppad_reg_bits { 9922 u8 reserved_at_0[0x3]; 9923 u8 single_mac[0x1]; 9924 u8 reserved_at_4[0x4]; 9925 u8 local_port[0x8]; 9926 u8 mac_47_32[0x10]; 9927 9928 u8 mac_31_0[0x20]; 9929 9930 u8 reserved_at_40[0x40]; 9931 }; 9932 9933 struct mlx5_ifc_pmtu_reg_bits { 9934 u8 reserved_at_0[0x8]; 9935 u8 local_port[0x8]; 9936 u8 reserved_at_10[0x10]; 9937 9938 u8 max_mtu[0x10]; 9939 u8 reserved_at_30[0x10]; 9940 9941 u8 admin_mtu[0x10]; 9942 u8 reserved_at_50[0x10]; 9943 9944 u8 oper_mtu[0x10]; 9945 u8 reserved_at_70[0x10]; 9946 }; 9947 9948 struct mlx5_ifc_pmpr_reg_bits { 9949 u8 reserved_at_0[0x8]; 9950 u8 module[0x8]; 9951 u8 reserved_at_10[0x10]; 9952 9953 u8 reserved_at_20[0x18]; 9954 u8 attenuation_5g[0x8]; 9955 9956 u8 reserved_at_40[0x18]; 9957 u8 attenuation_7g[0x8]; 9958 9959 u8 reserved_at_60[0x18]; 9960 u8 attenuation_12g[0x8]; 9961 }; 9962 9963 struct mlx5_ifc_pmpe_reg_bits { 9964 u8 reserved_at_0[0x8]; 9965 u8 module[0x8]; 9966 u8 reserved_at_10[0xc]; 9967 u8 module_status[0x4]; 9968 9969 u8 reserved_at_20[0x60]; 9970 }; 9971 9972 struct mlx5_ifc_pmpc_reg_bits { 9973 u8 module_state_updated[32][0x8]; 9974 }; 9975 9976 struct mlx5_ifc_pmlpn_reg_bits { 9977 u8 reserved_at_0[0x4]; 9978 u8 mlpn_status[0x4]; 9979 u8 local_port[0x8]; 9980 u8 reserved_at_10[0x10]; 9981 9982 u8 e[0x1]; 9983 u8 reserved_at_21[0x1f]; 9984 }; 9985 9986 struct mlx5_ifc_pmlp_reg_bits { 9987 u8 rxtx[0x1]; 9988 u8 reserved_at_1[0x7]; 9989 u8 local_port[0x8]; 9990 u8 reserved_at_10[0x8]; 9991 u8 width[0x8]; 9992 9993 u8 lane0_module_mapping[0x20]; 9994 9995 u8 lane1_module_mapping[0x20]; 9996 9997 u8 lane2_module_mapping[0x20]; 9998 9999 u8 lane3_module_mapping[0x20]; 10000 10001 u8 reserved_at_a0[0x160]; 10002 }; 10003 10004 struct mlx5_ifc_pmaos_reg_bits { 10005 u8 reserved_at_0[0x8]; 10006 u8 module[0x8]; 10007 u8 reserved_at_10[0x4]; 10008 u8 admin_status[0x4]; 10009 u8 reserved_at_18[0x4]; 10010 u8 oper_status[0x4]; 10011 10012 u8 ase[0x1]; 10013 u8 ee[0x1]; 10014 u8 reserved_at_22[0x1c]; 10015 u8 e[0x2]; 10016 10017 u8 reserved_at_40[0x40]; 10018 }; 10019 10020 struct mlx5_ifc_plpc_reg_bits { 10021 u8 reserved_at_0[0x4]; 10022 u8 profile_id[0xc]; 10023 u8 reserved_at_10[0x4]; 10024 u8 proto_mask[0x4]; 10025 u8 reserved_at_18[0x8]; 10026 10027 u8 reserved_at_20[0x10]; 10028 u8 lane_speed[0x10]; 10029 10030 u8 reserved_at_40[0x17]; 10031 u8 lpbf[0x1]; 10032 u8 fec_mode_policy[0x8]; 10033 10034 u8 retransmission_capability[0x8]; 10035 u8 fec_mode_capability[0x18]; 10036 10037 u8 retransmission_support_admin[0x8]; 10038 u8 fec_mode_support_admin[0x18]; 10039 10040 u8 retransmission_request_admin[0x8]; 10041 u8 fec_mode_request_admin[0x18]; 10042 10043 u8 reserved_at_c0[0x80]; 10044 }; 10045 10046 struct mlx5_ifc_plib_reg_bits { 10047 u8 reserved_at_0[0x8]; 10048 u8 local_port[0x8]; 10049 u8 reserved_at_10[0x8]; 10050 u8 ib_port[0x8]; 10051 10052 u8 reserved_at_20[0x60]; 10053 }; 10054 10055 struct mlx5_ifc_plbf_reg_bits { 10056 u8 reserved_at_0[0x8]; 10057 u8 local_port[0x8]; 10058 u8 reserved_at_10[0xd]; 10059 u8 lbf_mode[0x3]; 10060 10061 u8 reserved_at_20[0x20]; 10062 }; 10063 10064 struct mlx5_ifc_pipg_reg_bits { 10065 u8 reserved_at_0[0x8]; 10066 u8 local_port[0x8]; 10067 u8 reserved_at_10[0x10]; 10068 10069 u8 dic[0x1]; 10070 u8 reserved_at_21[0x19]; 10071 u8 ipg[0x4]; 10072 u8 reserved_at_3e[0x2]; 10073 }; 10074 10075 struct mlx5_ifc_pifr_reg_bits { 10076 u8 reserved_at_0[0x8]; 10077 u8 local_port[0x8]; 10078 u8 reserved_at_10[0x10]; 10079 10080 u8 reserved_at_20[0xe0]; 10081 10082 u8 port_filter[8][0x20]; 10083 10084 u8 port_filter_update_en[8][0x20]; 10085 }; 10086 10087 struct mlx5_ifc_pfcc_reg_bits { 10088 u8 reserved_at_0[0x8]; 10089 u8 local_port[0x8]; 10090 u8 reserved_at_10[0xb]; 10091 u8 ppan_mask_n[0x1]; 10092 u8 minor_stall_mask[0x1]; 10093 u8 critical_stall_mask[0x1]; 10094 u8 reserved_at_1e[0x2]; 10095 10096 u8 ppan[0x4]; 10097 u8 reserved_at_24[0x4]; 10098 u8 prio_mask_tx[0x8]; 10099 u8 reserved_at_30[0x8]; 10100 u8 prio_mask_rx[0x8]; 10101 10102 u8 pptx[0x1]; 10103 u8 aptx[0x1]; 10104 u8 pptx_mask_n[0x1]; 10105 u8 reserved_at_43[0x5]; 10106 u8 pfctx[0x8]; 10107 u8 reserved_at_50[0x10]; 10108 10109 u8 pprx[0x1]; 10110 u8 aprx[0x1]; 10111 u8 pprx_mask_n[0x1]; 10112 u8 reserved_at_63[0x5]; 10113 u8 pfcrx[0x8]; 10114 u8 reserved_at_70[0x10]; 10115 10116 u8 device_stall_minor_watermark[0x10]; 10117 u8 device_stall_critical_watermark[0x10]; 10118 10119 u8 reserved_at_a0[0x60]; 10120 }; 10121 10122 struct mlx5_ifc_pelc_reg_bits { 10123 u8 op[0x4]; 10124 u8 reserved_at_4[0x4]; 10125 u8 local_port[0x8]; 10126 u8 reserved_at_10[0x10]; 10127 10128 u8 op_admin[0x8]; 10129 u8 op_capability[0x8]; 10130 u8 op_request[0x8]; 10131 u8 op_active[0x8]; 10132 10133 u8 admin[0x40]; 10134 10135 u8 capability[0x40]; 10136 10137 u8 request[0x40]; 10138 10139 u8 active[0x40]; 10140 10141 u8 reserved_at_140[0x80]; 10142 }; 10143 10144 struct mlx5_ifc_peir_reg_bits { 10145 u8 reserved_at_0[0x8]; 10146 u8 local_port[0x8]; 10147 u8 reserved_at_10[0x10]; 10148 10149 u8 reserved_at_20[0xc]; 10150 u8 error_count[0x4]; 10151 u8 reserved_at_30[0x10]; 10152 10153 u8 reserved_at_40[0xc]; 10154 u8 lane[0x4]; 10155 u8 reserved_at_50[0x8]; 10156 u8 error_type[0x8]; 10157 }; 10158 10159 struct mlx5_ifc_mpegc_reg_bits { 10160 u8 reserved_at_0[0x30]; 10161 u8 field_select[0x10]; 10162 10163 u8 tx_overflow_sense[0x1]; 10164 u8 mark_cqe[0x1]; 10165 u8 mark_cnp[0x1]; 10166 u8 reserved_at_43[0x1b]; 10167 u8 tx_lossy_overflow_oper[0x2]; 10168 10169 u8 reserved_at_60[0x100]; 10170 }; 10171 10172 struct mlx5_ifc_mpir_reg_bits { 10173 u8 sdm[0x1]; 10174 u8 reserved_at_1[0x1b]; 10175 u8 host_buses[0x4]; 10176 10177 u8 reserved_at_20[0x20]; 10178 10179 u8 local_port[0x8]; 10180 u8 reserved_at_28[0x18]; 10181 10182 u8 reserved_at_60[0x20]; 10183 }; 10184 10185 enum { 10186 MLX5_MTUTC_FREQ_ADJ_UNITS_PPB = 0x0, 10187 MLX5_MTUTC_FREQ_ADJ_UNITS_SCALED_PPM = 0x1, 10188 }; 10189 10190 enum { 10191 MLX5_MTUTC_OPERATION_SET_TIME_IMMEDIATE = 0x1, 10192 MLX5_MTUTC_OPERATION_ADJUST_TIME = 0x2, 10193 MLX5_MTUTC_OPERATION_ADJUST_FREQ_UTC = 0x3, 10194 }; 10195 10196 struct mlx5_ifc_mtutc_reg_bits { 10197 u8 reserved_at_0[0x5]; 10198 u8 freq_adj_units[0x3]; 10199 u8 reserved_at_8[0x3]; 10200 u8 log_max_freq_adjustment[0x5]; 10201 10202 u8 reserved_at_10[0xc]; 10203 u8 operation[0x4]; 10204 10205 u8 freq_adjustment[0x20]; 10206 10207 u8 reserved_at_40[0x40]; 10208 10209 u8 utc_sec[0x20]; 10210 10211 u8 reserved_at_a0[0x2]; 10212 u8 utc_nsec[0x1e]; 10213 10214 u8 time_adjustment[0x20]; 10215 }; 10216 10217 struct mlx5_ifc_pcam_enhanced_features_bits { 10218 u8 reserved_at_0[0x48]; 10219 u8 fec_100G_per_lane_in_pplm[0x1]; 10220 u8 reserved_at_49[0x1f]; 10221 u8 fec_50G_per_lane_in_pplm[0x1]; 10222 u8 reserved_at_69[0x4]; 10223 u8 rx_icrc_encapsulated_counter[0x1]; 10224 u8 reserved_at_6e[0x4]; 10225 u8 ptys_extended_ethernet[0x1]; 10226 u8 reserved_at_73[0x3]; 10227 u8 pfcc_mask[0x1]; 10228 u8 reserved_at_77[0x3]; 10229 u8 per_lane_error_counters[0x1]; 10230 u8 rx_buffer_fullness_counters[0x1]; 10231 u8 ptys_connector_type[0x1]; 10232 u8 reserved_at_7d[0x1]; 10233 u8 ppcnt_discard_group[0x1]; 10234 u8 ppcnt_statistical_group[0x1]; 10235 }; 10236 10237 struct mlx5_ifc_pcam_regs_5000_to_507f_bits { 10238 u8 port_access_reg_cap_mask_127_to_96[0x20]; 10239 u8 port_access_reg_cap_mask_95_to_64[0x20]; 10240 10241 u8 port_access_reg_cap_mask_63_to_36[0x1c]; 10242 u8 pplm[0x1]; 10243 u8 port_access_reg_cap_mask_34_to_32[0x3]; 10244 10245 u8 port_access_reg_cap_mask_31_to_13[0x13]; 10246 u8 pbmc[0x1]; 10247 u8 pptb[0x1]; 10248 u8 port_access_reg_cap_mask_10_to_09[0x2]; 10249 u8 ppcnt[0x1]; 10250 u8 port_access_reg_cap_mask_07_to_00[0x8]; 10251 }; 10252 10253 struct mlx5_ifc_pcam_reg_bits { 10254 u8 reserved_at_0[0x8]; 10255 u8 feature_group[0x8]; 10256 u8 reserved_at_10[0x8]; 10257 u8 access_reg_group[0x8]; 10258 10259 u8 reserved_at_20[0x20]; 10260 10261 union { 10262 struct mlx5_ifc_pcam_regs_5000_to_507f_bits regs_5000_to_507f; 10263 u8 reserved_at_0[0x80]; 10264 } port_access_reg_cap_mask; 10265 10266 u8 reserved_at_c0[0x80]; 10267 10268 union { 10269 struct mlx5_ifc_pcam_enhanced_features_bits enhanced_features; 10270 u8 reserved_at_0[0x80]; 10271 } feature_cap_mask; 10272 10273 u8 reserved_at_1c0[0xc0]; 10274 }; 10275 10276 struct mlx5_ifc_mcam_enhanced_features_bits { 10277 u8 reserved_at_0[0x50]; 10278 u8 mtutc_freq_adj_units[0x1]; 10279 u8 mtutc_time_adjustment_extended_range[0x1]; 10280 u8 reserved_at_52[0xb]; 10281 u8 mcia_32dwords[0x1]; 10282 u8 out_pulse_duration_ns[0x1]; 10283 u8 npps_period[0x1]; 10284 u8 reserved_at_60[0xa]; 10285 u8 reset_state[0x1]; 10286 u8 ptpcyc2realtime_modify[0x1]; 10287 u8 reserved_at_6c[0x2]; 10288 u8 pci_status_and_power[0x1]; 10289 u8 reserved_at_6f[0x5]; 10290 u8 mark_tx_action_cnp[0x1]; 10291 u8 mark_tx_action_cqe[0x1]; 10292 u8 dynamic_tx_overflow[0x1]; 10293 u8 reserved_at_77[0x4]; 10294 u8 pcie_outbound_stalled[0x1]; 10295 u8 tx_overflow_buffer_pkt[0x1]; 10296 u8 mtpps_enh_out_per_adj[0x1]; 10297 u8 mtpps_fs[0x1]; 10298 u8 pcie_performance_group[0x1]; 10299 }; 10300 10301 struct mlx5_ifc_mcam_access_reg_bits { 10302 u8 reserved_at_0[0x1c]; 10303 u8 mcda[0x1]; 10304 u8 mcc[0x1]; 10305 u8 mcqi[0x1]; 10306 u8 mcqs[0x1]; 10307 10308 u8 regs_95_to_90[0x6]; 10309 u8 mpir[0x1]; 10310 u8 regs_88_to_87[0x2]; 10311 u8 mpegc[0x1]; 10312 u8 mtutc[0x1]; 10313 u8 regs_84_to_68[0x11]; 10314 u8 tracer_registers[0x4]; 10315 10316 u8 regs_63_to_46[0x12]; 10317 u8 mrtc[0x1]; 10318 u8 regs_44_to_41[0x4]; 10319 u8 mfrl[0x1]; 10320 u8 regs_39_to_32[0x8]; 10321 10322 u8 regs_31_to_11[0x15]; 10323 u8 mtmp[0x1]; 10324 u8 regs_9_to_0[0xa]; 10325 }; 10326 10327 struct mlx5_ifc_mcam_access_reg_bits1 { 10328 u8 regs_127_to_96[0x20]; 10329 10330 u8 regs_95_to_64[0x20]; 10331 10332 u8 regs_63_to_32[0x20]; 10333 10334 u8 regs_31_to_0[0x20]; 10335 }; 10336 10337 struct mlx5_ifc_mcam_access_reg_bits2 { 10338 u8 regs_127_to_99[0x1d]; 10339 u8 mirc[0x1]; 10340 u8 regs_97_to_96[0x2]; 10341 10342 u8 regs_95_to_87[0x09]; 10343 u8 synce_registers[0x2]; 10344 u8 regs_84_to_64[0x15]; 10345 10346 u8 regs_63_to_32[0x20]; 10347 10348 u8 regs_31_to_0[0x20]; 10349 }; 10350 10351 struct mlx5_ifc_mcam_reg_bits { 10352 u8 reserved_at_0[0x8]; 10353 u8 feature_group[0x8]; 10354 u8 reserved_at_10[0x8]; 10355 u8 access_reg_group[0x8]; 10356 10357 u8 reserved_at_20[0x20]; 10358 10359 union { 10360 struct mlx5_ifc_mcam_access_reg_bits access_regs; 10361 struct mlx5_ifc_mcam_access_reg_bits1 access_regs1; 10362 struct mlx5_ifc_mcam_access_reg_bits2 access_regs2; 10363 u8 reserved_at_0[0x80]; 10364 } mng_access_reg_cap_mask; 10365 10366 u8 reserved_at_c0[0x80]; 10367 10368 union { 10369 struct mlx5_ifc_mcam_enhanced_features_bits enhanced_features; 10370 u8 reserved_at_0[0x80]; 10371 } mng_feature_cap_mask; 10372 10373 u8 reserved_at_1c0[0x80]; 10374 }; 10375 10376 struct mlx5_ifc_qcam_access_reg_cap_mask { 10377 u8 qcam_access_reg_cap_mask_127_to_20[0x6C]; 10378 u8 qpdpm[0x1]; 10379 u8 qcam_access_reg_cap_mask_18_to_4[0x0F]; 10380 u8 qdpm[0x1]; 10381 u8 qpts[0x1]; 10382 u8 qcap[0x1]; 10383 u8 qcam_access_reg_cap_mask_0[0x1]; 10384 }; 10385 10386 struct mlx5_ifc_qcam_qos_feature_cap_mask { 10387 u8 qcam_qos_feature_cap_mask_127_to_1[0x7F]; 10388 u8 qpts_trust_both[0x1]; 10389 }; 10390 10391 struct mlx5_ifc_qcam_reg_bits { 10392 u8 reserved_at_0[0x8]; 10393 u8 feature_group[0x8]; 10394 u8 reserved_at_10[0x8]; 10395 u8 access_reg_group[0x8]; 10396 u8 reserved_at_20[0x20]; 10397 10398 union { 10399 struct mlx5_ifc_qcam_access_reg_cap_mask reg_cap; 10400 u8 reserved_at_0[0x80]; 10401 } qos_access_reg_cap_mask; 10402 10403 u8 reserved_at_c0[0x80]; 10404 10405 union { 10406 struct mlx5_ifc_qcam_qos_feature_cap_mask feature_cap; 10407 u8 reserved_at_0[0x80]; 10408 } qos_feature_cap_mask; 10409 10410 u8 reserved_at_1c0[0x80]; 10411 }; 10412 10413 struct mlx5_ifc_core_dump_reg_bits { 10414 u8 reserved_at_0[0x18]; 10415 u8 core_dump_type[0x8]; 10416 10417 u8 reserved_at_20[0x30]; 10418 u8 vhca_id[0x10]; 10419 10420 u8 reserved_at_60[0x8]; 10421 u8 qpn[0x18]; 10422 u8 reserved_at_80[0x180]; 10423 }; 10424 10425 struct mlx5_ifc_pcap_reg_bits { 10426 u8 reserved_at_0[0x8]; 10427 u8 local_port[0x8]; 10428 u8 reserved_at_10[0x10]; 10429 10430 u8 port_capability_mask[4][0x20]; 10431 }; 10432 10433 struct mlx5_ifc_paos_reg_bits { 10434 u8 swid[0x8]; 10435 u8 local_port[0x8]; 10436 u8 reserved_at_10[0x4]; 10437 u8 admin_status[0x4]; 10438 u8 reserved_at_18[0x4]; 10439 u8 oper_status[0x4]; 10440 10441 u8 ase[0x1]; 10442 u8 ee[0x1]; 10443 u8 reserved_at_22[0x1c]; 10444 u8 e[0x2]; 10445 10446 u8 reserved_at_40[0x40]; 10447 }; 10448 10449 struct mlx5_ifc_pamp_reg_bits { 10450 u8 reserved_at_0[0x8]; 10451 u8 opamp_group[0x8]; 10452 u8 reserved_at_10[0xc]; 10453 u8 opamp_group_type[0x4]; 10454 10455 u8 start_index[0x10]; 10456 u8 reserved_at_30[0x4]; 10457 u8 num_of_indices[0xc]; 10458 10459 u8 index_data[18][0x10]; 10460 }; 10461 10462 struct mlx5_ifc_pcmr_reg_bits { 10463 u8 reserved_at_0[0x8]; 10464 u8 local_port[0x8]; 10465 u8 reserved_at_10[0x10]; 10466 10467 u8 entropy_force_cap[0x1]; 10468 u8 entropy_calc_cap[0x1]; 10469 u8 entropy_gre_calc_cap[0x1]; 10470 u8 reserved_at_23[0xf]; 10471 u8 rx_ts_over_crc_cap[0x1]; 10472 u8 reserved_at_33[0xb]; 10473 u8 fcs_cap[0x1]; 10474 u8 reserved_at_3f[0x1]; 10475 10476 u8 entropy_force[0x1]; 10477 u8 entropy_calc[0x1]; 10478 u8 entropy_gre_calc[0x1]; 10479 u8 reserved_at_43[0xf]; 10480 u8 rx_ts_over_crc[0x1]; 10481 u8 reserved_at_53[0xb]; 10482 u8 fcs_chk[0x1]; 10483 u8 reserved_at_5f[0x1]; 10484 }; 10485 10486 struct mlx5_ifc_lane_2_module_mapping_bits { 10487 u8 reserved_at_0[0x4]; 10488 u8 rx_lane[0x4]; 10489 u8 reserved_at_8[0x4]; 10490 u8 tx_lane[0x4]; 10491 u8 reserved_at_10[0x8]; 10492 u8 module[0x8]; 10493 }; 10494 10495 struct mlx5_ifc_bufferx_reg_bits { 10496 u8 reserved_at_0[0x6]; 10497 u8 lossy[0x1]; 10498 u8 epsb[0x1]; 10499 u8 reserved_at_8[0x8]; 10500 u8 size[0x10]; 10501 10502 u8 xoff_threshold[0x10]; 10503 u8 xon_threshold[0x10]; 10504 }; 10505 10506 struct mlx5_ifc_set_node_in_bits { 10507 u8 node_description[64][0x8]; 10508 }; 10509 10510 struct mlx5_ifc_register_power_settings_bits { 10511 u8 reserved_at_0[0x18]; 10512 u8 power_settings_level[0x8]; 10513 10514 u8 reserved_at_20[0x60]; 10515 }; 10516 10517 struct mlx5_ifc_register_host_endianness_bits { 10518 u8 he[0x1]; 10519 u8 reserved_at_1[0x1f]; 10520 10521 u8 reserved_at_20[0x60]; 10522 }; 10523 10524 struct mlx5_ifc_umr_pointer_desc_argument_bits { 10525 u8 reserved_at_0[0x20]; 10526 10527 u8 mkey[0x20]; 10528 10529 u8 addressh_63_32[0x20]; 10530 10531 u8 addressl_31_0[0x20]; 10532 }; 10533 10534 struct mlx5_ifc_ud_adrs_vector_bits { 10535 u8 dc_key[0x40]; 10536 10537 u8 ext[0x1]; 10538 u8 reserved_at_41[0x7]; 10539 u8 destination_qp_dct[0x18]; 10540 10541 u8 static_rate[0x4]; 10542 u8 sl_eth_prio[0x4]; 10543 u8 fl[0x1]; 10544 u8 mlid[0x7]; 10545 u8 rlid_udp_sport[0x10]; 10546 10547 u8 reserved_at_80[0x20]; 10548 10549 u8 rmac_47_16[0x20]; 10550 10551 u8 rmac_15_0[0x10]; 10552 u8 tclass[0x8]; 10553 u8 hop_limit[0x8]; 10554 10555 u8 reserved_at_e0[0x1]; 10556 u8 grh[0x1]; 10557 u8 reserved_at_e2[0x2]; 10558 u8 src_addr_index[0x8]; 10559 u8 flow_label[0x14]; 10560 10561 u8 rgid_rip[16][0x8]; 10562 }; 10563 10564 struct mlx5_ifc_pages_req_event_bits { 10565 u8 reserved_at_0[0x10]; 10566 u8 function_id[0x10]; 10567 10568 u8 num_pages[0x20]; 10569 10570 u8 reserved_at_40[0xa0]; 10571 }; 10572 10573 struct mlx5_ifc_eqe_bits { 10574 u8 reserved_at_0[0x8]; 10575 u8 event_type[0x8]; 10576 u8 reserved_at_10[0x8]; 10577 u8 event_sub_type[0x8]; 10578 10579 u8 reserved_at_20[0xe0]; 10580 10581 union mlx5_ifc_event_auto_bits event_data; 10582 10583 u8 reserved_at_1e0[0x10]; 10584 u8 signature[0x8]; 10585 u8 reserved_at_1f8[0x7]; 10586 u8 owner[0x1]; 10587 }; 10588 10589 enum { 10590 MLX5_CMD_QUEUE_ENTRY_TYPE_PCIE_CMD_IF_TRANSPORT = 0x7, 10591 }; 10592 10593 struct mlx5_ifc_cmd_queue_entry_bits { 10594 u8 type[0x8]; 10595 u8 reserved_at_8[0x18]; 10596 10597 u8 input_length[0x20]; 10598 10599 u8 input_mailbox_pointer_63_32[0x20]; 10600 10601 u8 input_mailbox_pointer_31_9[0x17]; 10602 u8 reserved_at_77[0x9]; 10603 10604 u8 command_input_inline_data[16][0x8]; 10605 10606 u8 command_output_inline_data[16][0x8]; 10607 10608 u8 output_mailbox_pointer_63_32[0x20]; 10609 10610 u8 output_mailbox_pointer_31_9[0x17]; 10611 u8 reserved_at_1b7[0x9]; 10612 10613 u8 output_length[0x20]; 10614 10615 u8 token[0x8]; 10616 u8 signature[0x8]; 10617 u8 reserved_at_1f0[0x8]; 10618 u8 status[0x7]; 10619 u8 ownership[0x1]; 10620 }; 10621 10622 struct mlx5_ifc_cmd_out_bits { 10623 u8 status[0x8]; 10624 u8 reserved_at_8[0x18]; 10625 10626 u8 syndrome[0x20]; 10627 10628 u8 command_output[0x20]; 10629 }; 10630 10631 struct mlx5_ifc_cmd_in_bits { 10632 u8 opcode[0x10]; 10633 u8 reserved_at_10[0x10]; 10634 10635 u8 reserved_at_20[0x10]; 10636 u8 op_mod[0x10]; 10637 10638 u8 command[][0x20]; 10639 }; 10640 10641 struct mlx5_ifc_cmd_if_box_bits { 10642 u8 mailbox_data[512][0x8]; 10643 10644 u8 reserved_at_1000[0x180]; 10645 10646 u8 next_pointer_63_32[0x20]; 10647 10648 u8 next_pointer_31_10[0x16]; 10649 u8 reserved_at_11b6[0xa]; 10650 10651 u8 block_number[0x20]; 10652 10653 u8 reserved_at_11e0[0x8]; 10654 u8 token[0x8]; 10655 u8 ctrl_signature[0x8]; 10656 u8 signature[0x8]; 10657 }; 10658 10659 struct mlx5_ifc_mtt_bits { 10660 u8 ptag_63_32[0x20]; 10661 10662 u8 ptag_31_8[0x18]; 10663 u8 reserved_at_38[0x6]; 10664 u8 wr_en[0x1]; 10665 u8 rd_en[0x1]; 10666 }; 10667 10668 struct mlx5_ifc_query_wol_rol_out_bits { 10669 u8 status[0x8]; 10670 u8 reserved_at_8[0x18]; 10671 10672 u8 syndrome[0x20]; 10673 10674 u8 reserved_at_40[0x10]; 10675 u8 rol_mode[0x8]; 10676 u8 wol_mode[0x8]; 10677 10678 u8 reserved_at_60[0x20]; 10679 }; 10680 10681 struct mlx5_ifc_query_wol_rol_in_bits { 10682 u8 opcode[0x10]; 10683 u8 reserved_at_10[0x10]; 10684 10685 u8 reserved_at_20[0x10]; 10686 u8 op_mod[0x10]; 10687 10688 u8 reserved_at_40[0x40]; 10689 }; 10690 10691 struct mlx5_ifc_set_wol_rol_out_bits { 10692 u8 status[0x8]; 10693 u8 reserved_at_8[0x18]; 10694 10695 u8 syndrome[0x20]; 10696 10697 u8 reserved_at_40[0x40]; 10698 }; 10699 10700 struct mlx5_ifc_set_wol_rol_in_bits { 10701 u8 opcode[0x10]; 10702 u8 reserved_at_10[0x10]; 10703 10704 u8 reserved_at_20[0x10]; 10705 u8 op_mod[0x10]; 10706 10707 u8 rol_mode_valid[0x1]; 10708 u8 wol_mode_valid[0x1]; 10709 u8 reserved_at_42[0xe]; 10710 u8 rol_mode[0x8]; 10711 u8 wol_mode[0x8]; 10712 10713 u8 reserved_at_60[0x20]; 10714 }; 10715 10716 enum { 10717 MLX5_INITIAL_SEG_NIC_INTERFACE_FULL_DRIVER = 0x0, 10718 MLX5_INITIAL_SEG_NIC_INTERFACE_DISABLED = 0x1, 10719 MLX5_INITIAL_SEG_NIC_INTERFACE_NO_DRAM_NIC = 0x2, 10720 MLX5_INITIAL_SEG_NIC_INTERFACE_SW_RESET = 0x7, 10721 }; 10722 10723 enum { 10724 MLX5_INITIAL_SEG_NIC_INTERFACE_SUPPORTED_FULL_DRIVER = 0x0, 10725 MLX5_INITIAL_SEG_NIC_INTERFACE_SUPPORTED_DISABLED = 0x1, 10726 MLX5_INITIAL_SEG_NIC_INTERFACE_SUPPORTED_NO_DRAM_NIC = 0x2, 10727 }; 10728 10729 enum { 10730 MLX5_INITIAL_SEG_HEALTH_SYNDROME_FW_INTERNAL_ERR = 0x1, 10731 MLX5_INITIAL_SEG_HEALTH_SYNDROME_DEAD_IRISC = 0x7, 10732 MLX5_INITIAL_SEG_HEALTH_SYNDROME_HW_FATAL_ERR = 0x8, 10733 MLX5_INITIAL_SEG_HEALTH_SYNDROME_FW_CRC_ERR = 0x9, 10734 MLX5_INITIAL_SEG_HEALTH_SYNDROME_ICM_FETCH_PCI_ERR = 0xa, 10735 MLX5_INITIAL_SEG_HEALTH_SYNDROME_ICM_PAGE_ERR = 0xb, 10736 MLX5_INITIAL_SEG_HEALTH_SYNDROME_ASYNCHRONOUS_EQ_BUF_OVERRUN = 0xc, 10737 MLX5_INITIAL_SEG_HEALTH_SYNDROME_EQ_IN_ERR = 0xd, 10738 MLX5_INITIAL_SEG_HEALTH_SYNDROME_EQ_INV = 0xe, 10739 MLX5_INITIAL_SEG_HEALTH_SYNDROME_FFSER_ERR = 0xf, 10740 MLX5_INITIAL_SEG_HEALTH_SYNDROME_HIGH_TEMP_ERR = 0x10, 10741 MLX5_INITIAL_SEG_HEALTH_SYNDROME_ICM_PCI_POISONED_ERR = 0x12, 10742 }; 10743 10744 struct mlx5_ifc_initial_seg_bits { 10745 u8 fw_rev_minor[0x10]; 10746 u8 fw_rev_major[0x10]; 10747 10748 u8 cmd_interface_rev[0x10]; 10749 u8 fw_rev_subminor[0x10]; 10750 10751 u8 reserved_at_40[0x40]; 10752 10753 u8 cmdq_phy_addr_63_32[0x20]; 10754 10755 u8 cmdq_phy_addr_31_12[0x14]; 10756 u8 reserved_at_b4[0x2]; 10757 u8 nic_interface[0x2]; 10758 u8 log_cmdq_size[0x4]; 10759 u8 log_cmdq_stride[0x4]; 10760 10761 u8 command_doorbell_vector[0x20]; 10762 10763 u8 reserved_at_e0[0xf00]; 10764 10765 u8 initializing[0x1]; 10766 u8 reserved_at_fe1[0x4]; 10767 u8 nic_interface_supported[0x3]; 10768 u8 embedded_cpu[0x1]; 10769 u8 reserved_at_fe9[0x17]; 10770 10771 struct mlx5_ifc_health_buffer_bits health_buffer; 10772 10773 u8 no_dram_nic_offset[0x20]; 10774 10775 u8 reserved_at_1220[0x6e40]; 10776 10777 u8 reserved_at_8060[0x1f]; 10778 u8 clear_int[0x1]; 10779 10780 u8 health_syndrome[0x8]; 10781 u8 health_counter[0x18]; 10782 10783 u8 reserved_at_80a0[0x17fc0]; 10784 }; 10785 10786 struct mlx5_ifc_mtpps_reg_bits { 10787 u8 reserved_at_0[0xc]; 10788 u8 cap_number_of_pps_pins[0x4]; 10789 u8 reserved_at_10[0x4]; 10790 u8 cap_max_num_of_pps_in_pins[0x4]; 10791 u8 reserved_at_18[0x4]; 10792 u8 cap_max_num_of_pps_out_pins[0x4]; 10793 10794 u8 reserved_at_20[0x13]; 10795 u8 cap_log_min_npps_period[0x5]; 10796 u8 reserved_at_38[0x3]; 10797 u8 cap_log_min_out_pulse_duration_ns[0x5]; 10798 10799 u8 reserved_at_40[0x4]; 10800 u8 cap_pin_3_mode[0x4]; 10801 u8 reserved_at_48[0x4]; 10802 u8 cap_pin_2_mode[0x4]; 10803 u8 reserved_at_50[0x4]; 10804 u8 cap_pin_1_mode[0x4]; 10805 u8 reserved_at_58[0x4]; 10806 u8 cap_pin_0_mode[0x4]; 10807 10808 u8 reserved_at_60[0x4]; 10809 u8 cap_pin_7_mode[0x4]; 10810 u8 reserved_at_68[0x4]; 10811 u8 cap_pin_6_mode[0x4]; 10812 u8 reserved_at_70[0x4]; 10813 u8 cap_pin_5_mode[0x4]; 10814 u8 reserved_at_78[0x4]; 10815 u8 cap_pin_4_mode[0x4]; 10816 10817 u8 field_select[0x20]; 10818 u8 reserved_at_a0[0x20]; 10819 10820 u8 npps_period[0x40]; 10821 10822 u8 enable[0x1]; 10823 u8 reserved_at_101[0xb]; 10824 u8 pattern[0x4]; 10825 u8 reserved_at_110[0x4]; 10826 u8 pin_mode[0x4]; 10827 u8 pin[0x8]; 10828 10829 u8 reserved_at_120[0x2]; 10830 u8 out_pulse_duration_ns[0x1e]; 10831 10832 u8 time_stamp[0x40]; 10833 10834 u8 out_pulse_duration[0x10]; 10835 u8 out_periodic_adjustment[0x10]; 10836 u8 enhanced_out_periodic_adjustment[0x20]; 10837 10838 u8 reserved_at_1c0[0x20]; 10839 }; 10840 10841 struct mlx5_ifc_mtppse_reg_bits { 10842 u8 reserved_at_0[0x18]; 10843 u8 pin[0x8]; 10844 u8 event_arm[0x1]; 10845 u8 reserved_at_21[0x1b]; 10846 u8 event_generation_mode[0x4]; 10847 u8 reserved_at_40[0x40]; 10848 }; 10849 10850 struct mlx5_ifc_mcqs_reg_bits { 10851 u8 last_index_flag[0x1]; 10852 u8 reserved_at_1[0x7]; 10853 u8 fw_device[0x8]; 10854 u8 component_index[0x10]; 10855 10856 u8 reserved_at_20[0x10]; 10857 u8 identifier[0x10]; 10858 10859 u8 reserved_at_40[0x17]; 10860 u8 component_status[0x5]; 10861 u8 component_update_state[0x4]; 10862 10863 u8 last_update_state_changer_type[0x4]; 10864 u8 last_update_state_changer_host_id[0x4]; 10865 u8 reserved_at_68[0x18]; 10866 }; 10867 10868 struct mlx5_ifc_mcqi_cap_bits { 10869 u8 supported_info_bitmask[0x20]; 10870 10871 u8 component_size[0x20]; 10872 10873 u8 max_component_size[0x20]; 10874 10875 u8 log_mcda_word_size[0x4]; 10876 u8 reserved_at_64[0xc]; 10877 u8 mcda_max_write_size[0x10]; 10878 10879 u8 rd_en[0x1]; 10880 u8 reserved_at_81[0x1]; 10881 u8 match_chip_id[0x1]; 10882 u8 match_psid[0x1]; 10883 u8 check_user_timestamp[0x1]; 10884 u8 match_base_guid_mac[0x1]; 10885 u8 reserved_at_86[0x1a]; 10886 }; 10887 10888 struct mlx5_ifc_mcqi_version_bits { 10889 u8 reserved_at_0[0x2]; 10890 u8 build_time_valid[0x1]; 10891 u8 user_defined_time_valid[0x1]; 10892 u8 reserved_at_4[0x14]; 10893 u8 version_string_length[0x8]; 10894 10895 u8 version[0x20]; 10896 10897 u8 build_time[0x40]; 10898 10899 u8 user_defined_time[0x40]; 10900 10901 u8 build_tool_version[0x20]; 10902 10903 u8 reserved_at_e0[0x20]; 10904 10905 u8 version_string[92][0x8]; 10906 }; 10907 10908 struct mlx5_ifc_mcqi_activation_method_bits { 10909 u8 pending_server_ac_power_cycle[0x1]; 10910 u8 pending_server_dc_power_cycle[0x1]; 10911 u8 pending_server_reboot[0x1]; 10912 u8 pending_fw_reset[0x1]; 10913 u8 auto_activate[0x1]; 10914 u8 all_hosts_sync[0x1]; 10915 u8 device_hw_reset[0x1]; 10916 u8 reserved_at_7[0x19]; 10917 }; 10918 10919 union mlx5_ifc_mcqi_reg_data_bits { 10920 struct mlx5_ifc_mcqi_cap_bits mcqi_caps; 10921 struct mlx5_ifc_mcqi_version_bits mcqi_version; 10922 struct mlx5_ifc_mcqi_activation_method_bits mcqi_activation_mathod; 10923 }; 10924 10925 struct mlx5_ifc_mcqi_reg_bits { 10926 u8 read_pending_component[0x1]; 10927 u8 reserved_at_1[0xf]; 10928 u8 component_index[0x10]; 10929 10930 u8 reserved_at_20[0x20]; 10931 10932 u8 reserved_at_40[0x1b]; 10933 u8 info_type[0x5]; 10934 10935 u8 info_size[0x20]; 10936 10937 u8 offset[0x20]; 10938 10939 u8 reserved_at_a0[0x10]; 10940 u8 data_size[0x10]; 10941 10942 union mlx5_ifc_mcqi_reg_data_bits data[]; 10943 }; 10944 10945 struct mlx5_ifc_mcc_reg_bits { 10946 u8 reserved_at_0[0x4]; 10947 u8 time_elapsed_since_last_cmd[0xc]; 10948 u8 reserved_at_10[0x8]; 10949 u8 instruction[0x8]; 10950 10951 u8 reserved_at_20[0x10]; 10952 u8 component_index[0x10]; 10953 10954 u8 reserved_at_40[0x8]; 10955 u8 update_handle[0x18]; 10956 10957 u8 handle_owner_type[0x4]; 10958 u8 handle_owner_host_id[0x4]; 10959 u8 reserved_at_68[0x1]; 10960 u8 control_progress[0x7]; 10961 u8 error_code[0x8]; 10962 u8 reserved_at_78[0x4]; 10963 u8 control_state[0x4]; 10964 10965 u8 component_size[0x20]; 10966 10967 u8 reserved_at_a0[0x60]; 10968 }; 10969 10970 struct mlx5_ifc_mcda_reg_bits { 10971 u8 reserved_at_0[0x8]; 10972 u8 update_handle[0x18]; 10973 10974 u8 offset[0x20]; 10975 10976 u8 reserved_at_40[0x10]; 10977 u8 size[0x10]; 10978 10979 u8 reserved_at_60[0x20]; 10980 10981 u8 data[][0x20]; 10982 }; 10983 10984 enum { 10985 MLX5_MFRL_REG_RESET_STATE_IDLE = 0, 10986 MLX5_MFRL_REG_RESET_STATE_IN_NEGOTIATION = 1, 10987 MLX5_MFRL_REG_RESET_STATE_RESET_IN_PROGRESS = 2, 10988 MLX5_MFRL_REG_RESET_STATE_NEG_TIMEOUT = 3, 10989 MLX5_MFRL_REG_RESET_STATE_NACK = 4, 10990 MLX5_MFRL_REG_RESET_STATE_UNLOAD_TIMEOUT = 5, 10991 }; 10992 10993 enum { 10994 MLX5_MFRL_REG_RESET_TYPE_FULL_CHIP = BIT(0), 10995 MLX5_MFRL_REG_RESET_TYPE_NET_PORT_ALIVE = BIT(1), 10996 }; 10997 10998 enum { 10999 MLX5_MFRL_REG_RESET_LEVEL0 = BIT(0), 11000 MLX5_MFRL_REG_RESET_LEVEL3 = BIT(3), 11001 MLX5_MFRL_REG_RESET_LEVEL6 = BIT(6), 11002 }; 11003 11004 struct mlx5_ifc_mfrl_reg_bits { 11005 u8 reserved_at_0[0x20]; 11006 11007 u8 reserved_at_20[0x2]; 11008 u8 pci_sync_for_fw_update_start[0x1]; 11009 u8 pci_sync_for_fw_update_resp[0x2]; 11010 u8 rst_type_sel[0x3]; 11011 u8 reserved_at_28[0x4]; 11012 u8 reset_state[0x4]; 11013 u8 reset_type[0x8]; 11014 u8 reset_level[0x8]; 11015 }; 11016 11017 struct mlx5_ifc_mirc_reg_bits { 11018 u8 reserved_at_0[0x18]; 11019 u8 status_code[0x8]; 11020 11021 u8 reserved_at_20[0x20]; 11022 }; 11023 11024 struct mlx5_ifc_pddr_monitor_opcode_bits { 11025 u8 reserved_at_0[0x10]; 11026 u8 monitor_opcode[0x10]; 11027 }; 11028 11029 union mlx5_ifc_pddr_troubleshooting_page_status_opcode_auto_bits { 11030 struct mlx5_ifc_pddr_monitor_opcode_bits pddr_monitor_opcode; 11031 u8 reserved_at_0[0x20]; 11032 }; 11033 11034 enum { 11035 /* Monitor opcodes */ 11036 MLX5_PDDR_REG_TRBLSH_GROUP_OPCODE_MONITOR = 0x0, 11037 }; 11038 11039 struct mlx5_ifc_pddr_troubleshooting_page_bits { 11040 u8 reserved_at_0[0x10]; 11041 u8 group_opcode[0x10]; 11042 11043 union mlx5_ifc_pddr_troubleshooting_page_status_opcode_auto_bits status_opcode; 11044 11045 u8 reserved_at_40[0x20]; 11046 11047 u8 status_message[59][0x20]; 11048 }; 11049 11050 union mlx5_ifc_pddr_reg_page_data_auto_bits { 11051 struct mlx5_ifc_pddr_troubleshooting_page_bits pddr_troubleshooting_page; 11052 u8 reserved_at_0[0x7c0]; 11053 }; 11054 11055 enum { 11056 MLX5_PDDR_REG_PAGE_SELECT_TROUBLESHOOTING_INFO_PAGE = 0x1, 11057 }; 11058 11059 struct mlx5_ifc_pddr_reg_bits { 11060 u8 reserved_at_0[0x8]; 11061 u8 local_port[0x8]; 11062 u8 pnat[0x2]; 11063 u8 reserved_at_12[0xe]; 11064 11065 u8 reserved_at_20[0x18]; 11066 u8 page_select[0x8]; 11067 11068 union mlx5_ifc_pddr_reg_page_data_auto_bits page_data; 11069 }; 11070 11071 struct mlx5_ifc_mrtc_reg_bits { 11072 u8 time_synced[0x1]; 11073 u8 reserved_at_1[0x1f]; 11074 11075 u8 reserved_at_20[0x20]; 11076 11077 u8 time_h[0x20]; 11078 11079 u8 time_l[0x20]; 11080 }; 11081 11082 struct mlx5_ifc_mtcap_reg_bits { 11083 u8 reserved_at_0[0x19]; 11084 u8 sensor_count[0x7]; 11085 11086 u8 reserved_at_20[0x20]; 11087 11088 u8 sensor_map[0x40]; 11089 }; 11090 11091 struct mlx5_ifc_mtmp_reg_bits { 11092 u8 reserved_at_0[0x14]; 11093 u8 sensor_index[0xc]; 11094 11095 u8 reserved_at_20[0x10]; 11096 u8 temperature[0x10]; 11097 11098 u8 mte[0x1]; 11099 u8 mtr[0x1]; 11100 u8 reserved_at_42[0xe]; 11101 u8 max_temperature[0x10]; 11102 11103 u8 tee[0x2]; 11104 u8 reserved_at_62[0xe]; 11105 u8 temp_threshold_hi[0x10]; 11106 11107 u8 reserved_at_80[0x10]; 11108 u8 temp_threshold_lo[0x10]; 11109 11110 u8 reserved_at_a0[0x20]; 11111 11112 u8 sensor_name_hi[0x20]; 11113 u8 sensor_name_lo[0x20]; 11114 }; 11115 11116 union mlx5_ifc_ports_control_registers_document_bits { 11117 struct mlx5_ifc_bufferx_reg_bits bufferx_reg; 11118 struct mlx5_ifc_eth_2819_cntrs_grp_data_layout_bits eth_2819_cntrs_grp_data_layout; 11119 struct mlx5_ifc_eth_2863_cntrs_grp_data_layout_bits eth_2863_cntrs_grp_data_layout; 11120 struct mlx5_ifc_eth_3635_cntrs_grp_data_layout_bits eth_3635_cntrs_grp_data_layout; 11121 struct mlx5_ifc_eth_802_3_cntrs_grp_data_layout_bits eth_802_3_cntrs_grp_data_layout; 11122 struct mlx5_ifc_eth_extended_cntrs_grp_data_layout_bits eth_extended_cntrs_grp_data_layout; 11123 struct mlx5_ifc_eth_per_prio_grp_data_layout_bits eth_per_prio_grp_data_layout; 11124 struct mlx5_ifc_eth_per_tc_prio_grp_data_layout_bits eth_per_tc_prio_grp_data_layout; 11125 struct mlx5_ifc_eth_per_tc_congest_prio_grp_data_layout_bits eth_per_tc_congest_prio_grp_data_layout; 11126 struct mlx5_ifc_lane_2_module_mapping_bits lane_2_module_mapping; 11127 struct mlx5_ifc_pamp_reg_bits pamp_reg; 11128 struct mlx5_ifc_paos_reg_bits paos_reg; 11129 struct mlx5_ifc_pcap_reg_bits pcap_reg; 11130 struct mlx5_ifc_pddr_monitor_opcode_bits pddr_monitor_opcode; 11131 struct mlx5_ifc_pddr_reg_bits pddr_reg; 11132 struct mlx5_ifc_pddr_troubleshooting_page_bits pddr_troubleshooting_page; 11133 struct mlx5_ifc_peir_reg_bits peir_reg; 11134 struct mlx5_ifc_pelc_reg_bits pelc_reg; 11135 struct mlx5_ifc_pfcc_reg_bits pfcc_reg; 11136 struct mlx5_ifc_ib_port_cntrs_grp_data_layout_bits ib_port_cntrs_grp_data_layout; 11137 struct mlx5_ifc_phys_layer_cntrs_bits phys_layer_cntrs; 11138 struct mlx5_ifc_pifr_reg_bits pifr_reg; 11139 struct mlx5_ifc_pipg_reg_bits pipg_reg; 11140 struct mlx5_ifc_plbf_reg_bits plbf_reg; 11141 struct mlx5_ifc_plib_reg_bits plib_reg; 11142 struct mlx5_ifc_plpc_reg_bits plpc_reg; 11143 struct mlx5_ifc_pmaos_reg_bits pmaos_reg; 11144 struct mlx5_ifc_pmlp_reg_bits pmlp_reg; 11145 struct mlx5_ifc_pmlpn_reg_bits pmlpn_reg; 11146 struct mlx5_ifc_pmpc_reg_bits pmpc_reg; 11147 struct mlx5_ifc_pmpe_reg_bits pmpe_reg; 11148 struct mlx5_ifc_pmpr_reg_bits pmpr_reg; 11149 struct mlx5_ifc_pmtu_reg_bits pmtu_reg; 11150 struct mlx5_ifc_ppad_reg_bits ppad_reg; 11151 struct mlx5_ifc_ppcnt_reg_bits ppcnt_reg; 11152 struct mlx5_ifc_mpein_reg_bits mpein_reg; 11153 struct mlx5_ifc_mpcnt_reg_bits mpcnt_reg; 11154 struct mlx5_ifc_pplm_reg_bits pplm_reg; 11155 struct mlx5_ifc_pplr_reg_bits pplr_reg; 11156 struct mlx5_ifc_ppsc_reg_bits ppsc_reg; 11157 struct mlx5_ifc_pqdr_reg_bits pqdr_reg; 11158 struct mlx5_ifc_pspa_reg_bits pspa_reg; 11159 struct mlx5_ifc_ptas_reg_bits ptas_reg; 11160 struct mlx5_ifc_ptys_reg_bits ptys_reg; 11161 struct mlx5_ifc_mlcr_reg_bits mlcr_reg; 11162 struct mlx5_ifc_pude_reg_bits pude_reg; 11163 struct mlx5_ifc_pvlc_reg_bits pvlc_reg; 11164 struct mlx5_ifc_slrg_reg_bits slrg_reg; 11165 struct mlx5_ifc_sltp_reg_bits sltp_reg; 11166 struct mlx5_ifc_mtpps_reg_bits mtpps_reg; 11167 struct mlx5_ifc_mtppse_reg_bits mtppse_reg; 11168 struct mlx5_ifc_fpga_access_reg_bits fpga_access_reg; 11169 struct mlx5_ifc_fpga_ctrl_bits fpga_ctrl_bits; 11170 struct mlx5_ifc_fpga_cap_bits fpga_cap_bits; 11171 struct mlx5_ifc_mcqi_reg_bits mcqi_reg; 11172 struct mlx5_ifc_mcc_reg_bits mcc_reg; 11173 struct mlx5_ifc_mcda_reg_bits mcda_reg; 11174 struct mlx5_ifc_mirc_reg_bits mirc_reg; 11175 struct mlx5_ifc_mfrl_reg_bits mfrl_reg; 11176 struct mlx5_ifc_mtutc_reg_bits mtutc_reg; 11177 struct mlx5_ifc_mrtc_reg_bits mrtc_reg; 11178 struct mlx5_ifc_mtcap_reg_bits mtcap_reg; 11179 struct mlx5_ifc_mtmp_reg_bits mtmp_reg; 11180 u8 reserved_at_0[0x60e0]; 11181 }; 11182 11183 union mlx5_ifc_debug_enhancements_document_bits { 11184 struct mlx5_ifc_health_buffer_bits health_buffer; 11185 u8 reserved_at_0[0x200]; 11186 }; 11187 11188 union mlx5_ifc_uplink_pci_interface_document_bits { 11189 struct mlx5_ifc_initial_seg_bits initial_seg; 11190 u8 reserved_at_0[0x20060]; 11191 }; 11192 11193 struct mlx5_ifc_set_flow_table_root_out_bits { 11194 u8 status[0x8]; 11195 u8 reserved_at_8[0x18]; 11196 11197 u8 syndrome[0x20]; 11198 11199 u8 reserved_at_40[0x40]; 11200 }; 11201 11202 struct mlx5_ifc_set_flow_table_root_in_bits { 11203 u8 opcode[0x10]; 11204 u8 reserved_at_10[0x10]; 11205 11206 u8 reserved_at_20[0x10]; 11207 u8 op_mod[0x10]; 11208 11209 u8 other_vport[0x1]; 11210 u8 reserved_at_41[0xf]; 11211 u8 vport_number[0x10]; 11212 11213 u8 reserved_at_60[0x20]; 11214 11215 u8 table_type[0x8]; 11216 u8 reserved_at_88[0x7]; 11217 u8 table_of_other_vport[0x1]; 11218 u8 table_vport_number[0x10]; 11219 11220 u8 reserved_at_a0[0x8]; 11221 u8 table_id[0x18]; 11222 11223 u8 reserved_at_c0[0x8]; 11224 u8 underlay_qpn[0x18]; 11225 u8 table_eswitch_owner_vhca_id_valid[0x1]; 11226 u8 reserved_at_e1[0xf]; 11227 u8 table_eswitch_owner_vhca_id[0x10]; 11228 u8 reserved_at_100[0x100]; 11229 }; 11230 11231 enum { 11232 MLX5_MODIFY_FLOW_TABLE_MISS_TABLE_ID = (1UL << 0), 11233 MLX5_MODIFY_FLOW_TABLE_LAG_NEXT_TABLE_ID = (1UL << 15), 11234 }; 11235 11236 struct mlx5_ifc_modify_flow_table_out_bits { 11237 u8 status[0x8]; 11238 u8 reserved_at_8[0x18]; 11239 11240 u8 syndrome[0x20]; 11241 11242 u8 reserved_at_40[0x40]; 11243 }; 11244 11245 struct mlx5_ifc_modify_flow_table_in_bits { 11246 u8 opcode[0x10]; 11247 u8 reserved_at_10[0x10]; 11248 11249 u8 reserved_at_20[0x10]; 11250 u8 op_mod[0x10]; 11251 11252 u8 other_vport[0x1]; 11253 u8 reserved_at_41[0xf]; 11254 u8 vport_number[0x10]; 11255 11256 u8 reserved_at_60[0x10]; 11257 u8 modify_field_select[0x10]; 11258 11259 u8 table_type[0x8]; 11260 u8 reserved_at_88[0x18]; 11261 11262 u8 reserved_at_a0[0x8]; 11263 u8 table_id[0x18]; 11264 11265 struct mlx5_ifc_flow_table_context_bits flow_table_context; 11266 }; 11267 11268 struct mlx5_ifc_ets_tcn_config_reg_bits { 11269 u8 g[0x1]; 11270 u8 b[0x1]; 11271 u8 r[0x1]; 11272 u8 reserved_at_3[0x9]; 11273 u8 group[0x4]; 11274 u8 reserved_at_10[0x9]; 11275 u8 bw_allocation[0x7]; 11276 11277 u8 reserved_at_20[0xc]; 11278 u8 max_bw_units[0x4]; 11279 u8 reserved_at_30[0x8]; 11280 u8 max_bw_value[0x8]; 11281 }; 11282 11283 struct mlx5_ifc_ets_global_config_reg_bits { 11284 u8 reserved_at_0[0x2]; 11285 u8 r[0x1]; 11286 u8 reserved_at_3[0x1d]; 11287 11288 u8 reserved_at_20[0xc]; 11289 u8 max_bw_units[0x4]; 11290 u8 reserved_at_30[0x8]; 11291 u8 max_bw_value[0x8]; 11292 }; 11293 11294 struct mlx5_ifc_qetc_reg_bits { 11295 u8 reserved_at_0[0x8]; 11296 u8 port_number[0x8]; 11297 u8 reserved_at_10[0x30]; 11298 11299 struct mlx5_ifc_ets_tcn_config_reg_bits tc_configuration[0x8]; 11300 struct mlx5_ifc_ets_global_config_reg_bits global_configuration; 11301 }; 11302 11303 struct mlx5_ifc_qpdpm_dscp_reg_bits { 11304 u8 e[0x1]; 11305 u8 reserved_at_01[0x0b]; 11306 u8 prio[0x04]; 11307 }; 11308 11309 struct mlx5_ifc_qpdpm_reg_bits { 11310 u8 reserved_at_0[0x8]; 11311 u8 local_port[0x8]; 11312 u8 reserved_at_10[0x10]; 11313 struct mlx5_ifc_qpdpm_dscp_reg_bits dscp[64]; 11314 }; 11315 11316 struct mlx5_ifc_qpts_reg_bits { 11317 u8 reserved_at_0[0x8]; 11318 u8 local_port[0x8]; 11319 u8 reserved_at_10[0x2d]; 11320 u8 trust_state[0x3]; 11321 }; 11322 11323 struct mlx5_ifc_pptb_reg_bits { 11324 u8 reserved_at_0[0x2]; 11325 u8 mm[0x2]; 11326 u8 reserved_at_4[0x4]; 11327 u8 local_port[0x8]; 11328 u8 reserved_at_10[0x6]; 11329 u8 cm[0x1]; 11330 u8 um[0x1]; 11331 u8 pm[0x8]; 11332 11333 u8 prio_x_buff[0x20]; 11334 11335 u8 pm_msb[0x8]; 11336 u8 reserved_at_48[0x10]; 11337 u8 ctrl_buff[0x4]; 11338 u8 untagged_buff[0x4]; 11339 }; 11340 11341 struct mlx5_ifc_sbcam_reg_bits { 11342 u8 reserved_at_0[0x8]; 11343 u8 feature_group[0x8]; 11344 u8 reserved_at_10[0x8]; 11345 u8 access_reg_group[0x8]; 11346 11347 u8 reserved_at_20[0x20]; 11348 11349 u8 sb_access_reg_cap_mask[4][0x20]; 11350 11351 u8 reserved_at_c0[0x80]; 11352 11353 u8 sb_feature_cap_mask[4][0x20]; 11354 11355 u8 reserved_at_1c0[0x40]; 11356 11357 u8 cap_total_buffer_size[0x20]; 11358 11359 u8 cap_cell_size[0x10]; 11360 u8 cap_max_pg_buffers[0x8]; 11361 u8 cap_num_pool_supported[0x8]; 11362 11363 u8 reserved_at_240[0x8]; 11364 u8 cap_sbsr_stat_size[0x8]; 11365 u8 cap_max_tclass_data[0x8]; 11366 u8 cap_max_cpu_ingress_tclass_sb[0x8]; 11367 }; 11368 11369 struct mlx5_ifc_pbmc_reg_bits { 11370 u8 reserved_at_0[0x8]; 11371 u8 local_port[0x8]; 11372 u8 reserved_at_10[0x10]; 11373 11374 u8 xoff_timer_value[0x10]; 11375 u8 xoff_refresh[0x10]; 11376 11377 u8 reserved_at_40[0x9]; 11378 u8 fullness_threshold[0x7]; 11379 u8 port_buffer_size[0x10]; 11380 11381 struct mlx5_ifc_bufferx_reg_bits buffer[10]; 11382 11383 u8 reserved_at_2e0[0x80]; 11384 }; 11385 11386 struct mlx5_ifc_sbpr_reg_bits { 11387 u8 desc[0x1]; 11388 u8 snap[0x1]; 11389 u8 reserved_at_2[0x4]; 11390 u8 dir[0x2]; 11391 u8 reserved_at_8[0x14]; 11392 u8 pool[0x4]; 11393 11394 u8 infi_size[0x1]; 11395 u8 reserved_at_21[0x7]; 11396 u8 size[0x18]; 11397 11398 u8 reserved_at_40[0x1c]; 11399 u8 mode[0x4]; 11400 11401 u8 reserved_at_60[0x8]; 11402 u8 buff_occupancy[0x18]; 11403 11404 u8 clr[0x1]; 11405 u8 reserved_at_81[0x7]; 11406 u8 max_buff_occupancy[0x18]; 11407 11408 u8 reserved_at_a0[0x8]; 11409 u8 ext_buff_occupancy[0x18]; 11410 }; 11411 11412 struct mlx5_ifc_sbcm_reg_bits { 11413 u8 desc[0x1]; 11414 u8 snap[0x1]; 11415 u8 reserved_at_2[0x6]; 11416 u8 local_port[0x8]; 11417 u8 pnat[0x2]; 11418 u8 pg_buff[0x6]; 11419 u8 reserved_at_18[0x6]; 11420 u8 dir[0x2]; 11421 11422 u8 reserved_at_20[0x1f]; 11423 u8 exc[0x1]; 11424 11425 u8 reserved_at_40[0x40]; 11426 11427 u8 reserved_at_80[0x8]; 11428 u8 buff_occupancy[0x18]; 11429 11430 u8 clr[0x1]; 11431 u8 reserved_at_a1[0x7]; 11432 u8 max_buff_occupancy[0x18]; 11433 11434 u8 reserved_at_c0[0x8]; 11435 u8 min_buff[0x18]; 11436 11437 u8 infi_max[0x1]; 11438 u8 reserved_at_e1[0x7]; 11439 u8 max_buff[0x18]; 11440 11441 u8 reserved_at_100[0x20]; 11442 11443 u8 reserved_at_120[0x1c]; 11444 u8 pool[0x4]; 11445 }; 11446 11447 struct mlx5_ifc_qtct_reg_bits { 11448 u8 reserved_at_0[0x8]; 11449 u8 port_number[0x8]; 11450 u8 reserved_at_10[0xd]; 11451 u8 prio[0x3]; 11452 11453 u8 reserved_at_20[0x1d]; 11454 u8 tclass[0x3]; 11455 }; 11456 11457 struct mlx5_ifc_mcia_reg_bits { 11458 u8 l[0x1]; 11459 u8 reserved_at_1[0x7]; 11460 u8 module[0x8]; 11461 u8 reserved_at_10[0x8]; 11462 u8 status[0x8]; 11463 11464 u8 i2c_device_address[0x8]; 11465 u8 page_number[0x8]; 11466 u8 device_address[0x10]; 11467 11468 u8 reserved_at_40[0x10]; 11469 u8 size[0x10]; 11470 11471 u8 reserved_at_60[0x20]; 11472 11473 u8 dword_0[0x20]; 11474 u8 dword_1[0x20]; 11475 u8 dword_2[0x20]; 11476 u8 dword_3[0x20]; 11477 u8 dword_4[0x20]; 11478 u8 dword_5[0x20]; 11479 u8 dword_6[0x20]; 11480 u8 dword_7[0x20]; 11481 u8 dword_8[0x20]; 11482 u8 dword_9[0x20]; 11483 u8 dword_10[0x20]; 11484 u8 dword_11[0x20]; 11485 }; 11486 11487 struct mlx5_ifc_dcbx_param_bits { 11488 u8 dcbx_cee_cap[0x1]; 11489 u8 dcbx_ieee_cap[0x1]; 11490 u8 dcbx_standby_cap[0x1]; 11491 u8 reserved_at_3[0x5]; 11492 u8 port_number[0x8]; 11493 u8 reserved_at_10[0xa]; 11494 u8 max_application_table_size[6]; 11495 u8 reserved_at_20[0x15]; 11496 u8 version_oper[0x3]; 11497 u8 reserved_at_38[5]; 11498 u8 version_admin[0x3]; 11499 u8 willing_admin[0x1]; 11500 u8 reserved_at_41[0x3]; 11501 u8 pfc_cap_oper[0x4]; 11502 u8 reserved_at_48[0x4]; 11503 u8 pfc_cap_admin[0x4]; 11504 u8 reserved_at_50[0x4]; 11505 u8 num_of_tc_oper[0x4]; 11506 u8 reserved_at_58[0x4]; 11507 u8 num_of_tc_admin[0x4]; 11508 u8 remote_willing[0x1]; 11509 u8 reserved_at_61[3]; 11510 u8 remote_pfc_cap[4]; 11511 u8 reserved_at_68[0x14]; 11512 u8 remote_num_of_tc[0x4]; 11513 u8 reserved_at_80[0x18]; 11514 u8 error[0x8]; 11515 u8 reserved_at_a0[0x160]; 11516 }; 11517 11518 enum { 11519 MLX5_LAG_PORT_SELECT_MODE_QUEUE_AFFINITY = 0, 11520 MLX5_LAG_PORT_SELECT_MODE_PORT_SELECT_FT = 1, 11521 MLX5_LAG_PORT_SELECT_MODE_PORT_SELECT_MPESW = 2, 11522 }; 11523 11524 struct mlx5_ifc_lagc_bits { 11525 u8 fdb_selection_mode[0x1]; 11526 u8 reserved_at_1[0x14]; 11527 u8 port_select_mode[0x3]; 11528 u8 reserved_at_18[0x5]; 11529 u8 lag_state[0x3]; 11530 11531 u8 reserved_at_20[0xc]; 11532 u8 active_port[0x4]; 11533 u8 reserved_at_30[0x4]; 11534 u8 tx_remap_affinity_2[0x4]; 11535 u8 reserved_at_38[0x4]; 11536 u8 tx_remap_affinity_1[0x4]; 11537 }; 11538 11539 struct mlx5_ifc_create_lag_out_bits { 11540 u8 status[0x8]; 11541 u8 reserved_at_8[0x18]; 11542 11543 u8 syndrome[0x20]; 11544 11545 u8 reserved_at_40[0x40]; 11546 }; 11547 11548 struct mlx5_ifc_create_lag_in_bits { 11549 u8 opcode[0x10]; 11550 u8 reserved_at_10[0x10]; 11551 11552 u8 reserved_at_20[0x10]; 11553 u8 op_mod[0x10]; 11554 11555 struct mlx5_ifc_lagc_bits ctx; 11556 }; 11557 11558 struct mlx5_ifc_modify_lag_out_bits { 11559 u8 status[0x8]; 11560 u8 reserved_at_8[0x18]; 11561 11562 u8 syndrome[0x20]; 11563 11564 u8 reserved_at_40[0x40]; 11565 }; 11566 11567 struct mlx5_ifc_modify_lag_in_bits { 11568 u8 opcode[0x10]; 11569 u8 reserved_at_10[0x10]; 11570 11571 u8 reserved_at_20[0x10]; 11572 u8 op_mod[0x10]; 11573 11574 u8 reserved_at_40[0x20]; 11575 u8 field_select[0x20]; 11576 11577 struct mlx5_ifc_lagc_bits ctx; 11578 }; 11579 11580 struct mlx5_ifc_query_lag_out_bits { 11581 u8 status[0x8]; 11582 u8 reserved_at_8[0x18]; 11583 11584 u8 syndrome[0x20]; 11585 11586 struct mlx5_ifc_lagc_bits ctx; 11587 }; 11588 11589 struct mlx5_ifc_query_lag_in_bits { 11590 u8 opcode[0x10]; 11591 u8 reserved_at_10[0x10]; 11592 11593 u8 reserved_at_20[0x10]; 11594 u8 op_mod[0x10]; 11595 11596 u8 reserved_at_40[0x40]; 11597 }; 11598 11599 struct mlx5_ifc_destroy_lag_out_bits { 11600 u8 status[0x8]; 11601 u8 reserved_at_8[0x18]; 11602 11603 u8 syndrome[0x20]; 11604 11605 u8 reserved_at_40[0x40]; 11606 }; 11607 11608 struct mlx5_ifc_destroy_lag_in_bits { 11609 u8 opcode[0x10]; 11610 u8 reserved_at_10[0x10]; 11611 11612 u8 reserved_at_20[0x10]; 11613 u8 op_mod[0x10]; 11614 11615 u8 reserved_at_40[0x40]; 11616 }; 11617 11618 struct mlx5_ifc_create_vport_lag_out_bits { 11619 u8 status[0x8]; 11620 u8 reserved_at_8[0x18]; 11621 11622 u8 syndrome[0x20]; 11623 11624 u8 reserved_at_40[0x40]; 11625 }; 11626 11627 struct mlx5_ifc_create_vport_lag_in_bits { 11628 u8 opcode[0x10]; 11629 u8 reserved_at_10[0x10]; 11630 11631 u8 reserved_at_20[0x10]; 11632 u8 op_mod[0x10]; 11633 11634 u8 reserved_at_40[0x40]; 11635 }; 11636 11637 struct mlx5_ifc_destroy_vport_lag_out_bits { 11638 u8 status[0x8]; 11639 u8 reserved_at_8[0x18]; 11640 11641 u8 syndrome[0x20]; 11642 11643 u8 reserved_at_40[0x40]; 11644 }; 11645 11646 struct mlx5_ifc_destroy_vport_lag_in_bits { 11647 u8 opcode[0x10]; 11648 u8 reserved_at_10[0x10]; 11649 11650 u8 reserved_at_20[0x10]; 11651 u8 op_mod[0x10]; 11652 11653 u8 reserved_at_40[0x40]; 11654 }; 11655 11656 enum { 11657 MLX5_MODIFY_MEMIC_OP_MOD_ALLOC, 11658 MLX5_MODIFY_MEMIC_OP_MOD_DEALLOC, 11659 }; 11660 11661 struct mlx5_ifc_modify_memic_in_bits { 11662 u8 opcode[0x10]; 11663 u8 uid[0x10]; 11664 11665 u8 reserved_at_20[0x10]; 11666 u8 op_mod[0x10]; 11667 11668 u8 reserved_at_40[0x20]; 11669 11670 u8 reserved_at_60[0x18]; 11671 u8 memic_operation_type[0x8]; 11672 11673 u8 memic_start_addr[0x40]; 11674 11675 u8 reserved_at_c0[0x140]; 11676 }; 11677 11678 struct mlx5_ifc_modify_memic_out_bits { 11679 u8 status[0x8]; 11680 u8 reserved_at_8[0x18]; 11681 11682 u8 syndrome[0x20]; 11683 11684 u8 reserved_at_40[0x40]; 11685 11686 u8 memic_operation_addr[0x40]; 11687 11688 u8 reserved_at_c0[0x140]; 11689 }; 11690 11691 struct mlx5_ifc_alloc_memic_in_bits { 11692 u8 opcode[0x10]; 11693 u8 reserved_at_10[0x10]; 11694 11695 u8 reserved_at_20[0x10]; 11696 u8 op_mod[0x10]; 11697 11698 u8 reserved_at_30[0x20]; 11699 11700 u8 reserved_at_40[0x18]; 11701 u8 log_memic_addr_alignment[0x8]; 11702 11703 u8 range_start_addr[0x40]; 11704 11705 u8 range_size[0x20]; 11706 11707 u8 memic_size[0x20]; 11708 }; 11709 11710 struct mlx5_ifc_alloc_memic_out_bits { 11711 u8 status[0x8]; 11712 u8 reserved_at_8[0x18]; 11713 11714 u8 syndrome[0x20]; 11715 11716 u8 memic_start_addr[0x40]; 11717 }; 11718 11719 struct mlx5_ifc_dealloc_memic_in_bits { 11720 u8 opcode[0x10]; 11721 u8 reserved_at_10[0x10]; 11722 11723 u8 reserved_at_20[0x10]; 11724 u8 op_mod[0x10]; 11725 11726 u8 reserved_at_40[0x40]; 11727 11728 u8 memic_start_addr[0x40]; 11729 11730 u8 memic_size[0x20]; 11731 11732 u8 reserved_at_e0[0x20]; 11733 }; 11734 11735 struct mlx5_ifc_dealloc_memic_out_bits { 11736 u8 status[0x8]; 11737 u8 reserved_at_8[0x18]; 11738 11739 u8 syndrome[0x20]; 11740 11741 u8 reserved_at_40[0x40]; 11742 }; 11743 11744 struct mlx5_ifc_umem_bits { 11745 u8 reserved_at_0[0x80]; 11746 11747 u8 ats[0x1]; 11748 u8 reserved_at_81[0x1a]; 11749 u8 log_page_size[0x5]; 11750 11751 u8 page_offset[0x20]; 11752 11753 u8 num_of_mtt[0x40]; 11754 11755 struct mlx5_ifc_mtt_bits mtt[]; 11756 }; 11757 11758 struct mlx5_ifc_uctx_bits { 11759 u8 cap[0x20]; 11760 11761 u8 reserved_at_20[0x160]; 11762 }; 11763 11764 struct mlx5_ifc_sw_icm_bits { 11765 u8 modify_field_select[0x40]; 11766 11767 u8 reserved_at_40[0x18]; 11768 u8 log_sw_icm_size[0x8]; 11769 11770 u8 reserved_at_60[0x20]; 11771 11772 u8 sw_icm_start_addr[0x40]; 11773 11774 u8 reserved_at_c0[0x140]; 11775 }; 11776 11777 struct mlx5_ifc_geneve_tlv_option_bits { 11778 u8 modify_field_select[0x40]; 11779 11780 u8 reserved_at_40[0x18]; 11781 u8 geneve_option_fte_index[0x8]; 11782 11783 u8 option_class[0x10]; 11784 u8 option_type[0x8]; 11785 u8 reserved_at_78[0x3]; 11786 u8 option_data_length[0x5]; 11787 11788 u8 reserved_at_80[0x180]; 11789 }; 11790 11791 struct mlx5_ifc_create_umem_in_bits { 11792 u8 opcode[0x10]; 11793 u8 uid[0x10]; 11794 11795 u8 reserved_at_20[0x10]; 11796 u8 op_mod[0x10]; 11797 11798 u8 reserved_at_40[0x40]; 11799 11800 struct mlx5_ifc_umem_bits umem; 11801 }; 11802 11803 struct mlx5_ifc_create_umem_out_bits { 11804 u8 status[0x8]; 11805 u8 reserved_at_8[0x18]; 11806 11807 u8 syndrome[0x20]; 11808 11809 u8 reserved_at_40[0x8]; 11810 u8 umem_id[0x18]; 11811 11812 u8 reserved_at_60[0x20]; 11813 }; 11814 11815 struct mlx5_ifc_destroy_umem_in_bits { 11816 u8 opcode[0x10]; 11817 u8 uid[0x10]; 11818 11819 u8 reserved_at_20[0x10]; 11820 u8 op_mod[0x10]; 11821 11822 u8 reserved_at_40[0x8]; 11823 u8 umem_id[0x18]; 11824 11825 u8 reserved_at_60[0x20]; 11826 }; 11827 11828 struct mlx5_ifc_destroy_umem_out_bits { 11829 u8 status[0x8]; 11830 u8 reserved_at_8[0x18]; 11831 11832 u8 syndrome[0x20]; 11833 11834 u8 reserved_at_40[0x40]; 11835 }; 11836 11837 struct mlx5_ifc_create_uctx_in_bits { 11838 u8 opcode[0x10]; 11839 u8 reserved_at_10[0x10]; 11840 11841 u8 reserved_at_20[0x10]; 11842 u8 op_mod[0x10]; 11843 11844 u8 reserved_at_40[0x40]; 11845 11846 struct mlx5_ifc_uctx_bits uctx; 11847 }; 11848 11849 struct mlx5_ifc_create_uctx_out_bits { 11850 u8 status[0x8]; 11851 u8 reserved_at_8[0x18]; 11852 11853 u8 syndrome[0x20]; 11854 11855 u8 reserved_at_40[0x10]; 11856 u8 uid[0x10]; 11857 11858 u8 reserved_at_60[0x20]; 11859 }; 11860 11861 struct mlx5_ifc_destroy_uctx_in_bits { 11862 u8 opcode[0x10]; 11863 u8 reserved_at_10[0x10]; 11864 11865 u8 reserved_at_20[0x10]; 11866 u8 op_mod[0x10]; 11867 11868 u8 reserved_at_40[0x10]; 11869 u8 uid[0x10]; 11870 11871 u8 reserved_at_60[0x20]; 11872 }; 11873 11874 struct mlx5_ifc_destroy_uctx_out_bits { 11875 u8 status[0x8]; 11876 u8 reserved_at_8[0x18]; 11877 11878 u8 syndrome[0x20]; 11879 11880 u8 reserved_at_40[0x40]; 11881 }; 11882 11883 struct mlx5_ifc_create_sw_icm_in_bits { 11884 struct mlx5_ifc_general_obj_in_cmd_hdr_bits hdr; 11885 struct mlx5_ifc_sw_icm_bits sw_icm; 11886 }; 11887 11888 struct mlx5_ifc_create_geneve_tlv_option_in_bits { 11889 struct mlx5_ifc_general_obj_in_cmd_hdr_bits hdr; 11890 struct mlx5_ifc_geneve_tlv_option_bits geneve_tlv_opt; 11891 }; 11892 11893 struct mlx5_ifc_mtrc_string_db_param_bits { 11894 u8 string_db_base_address[0x20]; 11895 11896 u8 reserved_at_20[0x8]; 11897 u8 string_db_size[0x18]; 11898 }; 11899 11900 struct mlx5_ifc_mtrc_cap_bits { 11901 u8 trace_owner[0x1]; 11902 u8 trace_to_memory[0x1]; 11903 u8 reserved_at_2[0x4]; 11904 u8 trc_ver[0x2]; 11905 u8 reserved_at_8[0x14]; 11906 u8 num_string_db[0x4]; 11907 11908 u8 first_string_trace[0x8]; 11909 u8 num_string_trace[0x8]; 11910 u8 reserved_at_30[0x28]; 11911 11912 u8 log_max_trace_buffer_size[0x8]; 11913 11914 u8 reserved_at_60[0x20]; 11915 11916 struct mlx5_ifc_mtrc_string_db_param_bits string_db_param[8]; 11917 11918 u8 reserved_at_280[0x180]; 11919 }; 11920 11921 struct mlx5_ifc_mtrc_conf_bits { 11922 u8 reserved_at_0[0x1c]; 11923 u8 trace_mode[0x4]; 11924 u8 reserved_at_20[0x18]; 11925 u8 log_trace_buffer_size[0x8]; 11926 u8 trace_mkey[0x20]; 11927 u8 reserved_at_60[0x3a0]; 11928 }; 11929 11930 struct mlx5_ifc_mtrc_stdb_bits { 11931 u8 string_db_index[0x4]; 11932 u8 reserved_at_4[0x4]; 11933 u8 read_size[0x18]; 11934 u8 start_offset[0x20]; 11935 u8 string_db_data[]; 11936 }; 11937 11938 struct mlx5_ifc_mtrc_ctrl_bits { 11939 u8 trace_status[0x2]; 11940 u8 reserved_at_2[0x2]; 11941 u8 arm_event[0x1]; 11942 u8 reserved_at_5[0xb]; 11943 u8 modify_field_select[0x10]; 11944 u8 reserved_at_20[0x2b]; 11945 u8 current_timestamp52_32[0x15]; 11946 u8 current_timestamp31_0[0x20]; 11947 u8 reserved_at_80[0x180]; 11948 }; 11949 11950 struct mlx5_ifc_host_params_context_bits { 11951 u8 host_number[0x8]; 11952 u8 reserved_at_8[0x7]; 11953 u8 host_pf_disabled[0x1]; 11954 u8 host_num_of_vfs[0x10]; 11955 11956 u8 host_total_vfs[0x10]; 11957 u8 host_pci_bus[0x10]; 11958 11959 u8 reserved_at_40[0x10]; 11960 u8 host_pci_device[0x10]; 11961 11962 u8 reserved_at_60[0x10]; 11963 u8 host_pci_function[0x10]; 11964 11965 u8 reserved_at_80[0x180]; 11966 }; 11967 11968 struct mlx5_ifc_query_esw_functions_in_bits { 11969 u8 opcode[0x10]; 11970 u8 reserved_at_10[0x10]; 11971 11972 u8 reserved_at_20[0x10]; 11973 u8 op_mod[0x10]; 11974 11975 u8 reserved_at_40[0x40]; 11976 }; 11977 11978 struct mlx5_ifc_query_esw_functions_out_bits { 11979 u8 status[0x8]; 11980 u8 reserved_at_8[0x18]; 11981 11982 u8 syndrome[0x20]; 11983 11984 u8 reserved_at_40[0x40]; 11985 11986 struct mlx5_ifc_host_params_context_bits host_params_context; 11987 11988 u8 reserved_at_280[0x180]; 11989 u8 host_sf_enable[][0x40]; 11990 }; 11991 11992 struct mlx5_ifc_sf_partition_bits { 11993 u8 reserved_at_0[0x10]; 11994 u8 log_num_sf[0x8]; 11995 u8 log_sf_bar_size[0x8]; 11996 }; 11997 11998 struct mlx5_ifc_query_sf_partitions_out_bits { 11999 u8 status[0x8]; 12000 u8 reserved_at_8[0x18]; 12001 12002 u8 syndrome[0x20]; 12003 12004 u8 reserved_at_40[0x18]; 12005 u8 num_sf_partitions[0x8]; 12006 12007 u8 reserved_at_60[0x20]; 12008 12009 struct mlx5_ifc_sf_partition_bits sf_partition[]; 12010 }; 12011 12012 struct mlx5_ifc_query_sf_partitions_in_bits { 12013 u8 opcode[0x10]; 12014 u8 reserved_at_10[0x10]; 12015 12016 u8 reserved_at_20[0x10]; 12017 u8 op_mod[0x10]; 12018 12019 u8 reserved_at_40[0x40]; 12020 }; 12021 12022 struct mlx5_ifc_dealloc_sf_out_bits { 12023 u8 status[0x8]; 12024 u8 reserved_at_8[0x18]; 12025 12026 u8 syndrome[0x20]; 12027 12028 u8 reserved_at_40[0x40]; 12029 }; 12030 12031 struct mlx5_ifc_dealloc_sf_in_bits { 12032 u8 opcode[0x10]; 12033 u8 reserved_at_10[0x10]; 12034 12035 u8 reserved_at_20[0x10]; 12036 u8 op_mod[0x10]; 12037 12038 u8 reserved_at_40[0x10]; 12039 u8 function_id[0x10]; 12040 12041 u8 reserved_at_60[0x20]; 12042 }; 12043 12044 struct mlx5_ifc_alloc_sf_out_bits { 12045 u8 status[0x8]; 12046 u8 reserved_at_8[0x18]; 12047 12048 u8 syndrome[0x20]; 12049 12050 u8 reserved_at_40[0x40]; 12051 }; 12052 12053 struct mlx5_ifc_alloc_sf_in_bits { 12054 u8 opcode[0x10]; 12055 u8 reserved_at_10[0x10]; 12056 12057 u8 reserved_at_20[0x10]; 12058 u8 op_mod[0x10]; 12059 12060 u8 reserved_at_40[0x10]; 12061 u8 function_id[0x10]; 12062 12063 u8 reserved_at_60[0x20]; 12064 }; 12065 12066 struct mlx5_ifc_affiliated_event_header_bits { 12067 u8 reserved_at_0[0x10]; 12068 u8 obj_type[0x10]; 12069 12070 u8 obj_id[0x20]; 12071 }; 12072 12073 enum { 12074 MLX5_HCA_CAP_GENERAL_OBJECT_TYPES_ENCRYPTION_KEY = BIT_ULL(0xc), 12075 MLX5_HCA_CAP_GENERAL_OBJECT_TYPES_IPSEC = BIT_ULL(0x13), 12076 MLX5_HCA_CAP_GENERAL_OBJECT_TYPES_SAMPLER = BIT_ULL(0x20), 12077 MLX5_HCA_CAP_GENERAL_OBJECT_TYPES_FLOW_METER_ASO = BIT_ULL(0x24), 12078 }; 12079 12080 enum { 12081 MLX5_GENERAL_OBJECT_TYPES_ENCRYPTION_KEY = 0xc, 12082 MLX5_GENERAL_OBJECT_TYPES_IPSEC = 0x13, 12083 MLX5_GENERAL_OBJECT_TYPES_SAMPLER = 0x20, 12084 MLX5_GENERAL_OBJECT_TYPES_FLOW_METER_ASO = 0x24, 12085 MLX5_GENERAL_OBJECT_TYPES_MACSEC = 0x27, 12086 MLX5_GENERAL_OBJECT_TYPES_INT_KEK = 0x47, 12087 MLX5_GENERAL_OBJECT_TYPES_FLOW_TABLE_ALIAS = 0xff15, 12088 }; 12089 12090 enum { 12091 MLX5_IPSEC_OBJECT_ICV_LEN_16B, 12092 }; 12093 12094 enum { 12095 MLX5_IPSEC_ASO_REG_C_0_1 = 0x0, 12096 MLX5_IPSEC_ASO_REG_C_2_3 = 0x1, 12097 MLX5_IPSEC_ASO_REG_C_4_5 = 0x2, 12098 MLX5_IPSEC_ASO_REG_C_6_7 = 0x3, 12099 }; 12100 12101 enum { 12102 MLX5_IPSEC_ASO_MODE = 0x0, 12103 MLX5_IPSEC_ASO_REPLAY_PROTECTION = 0x1, 12104 MLX5_IPSEC_ASO_INC_SN = 0x2, 12105 }; 12106 12107 enum { 12108 MLX5_IPSEC_ASO_REPLAY_WIN_32BIT = 0x0, 12109 MLX5_IPSEC_ASO_REPLAY_WIN_64BIT = 0x1, 12110 MLX5_IPSEC_ASO_REPLAY_WIN_128BIT = 0x2, 12111 MLX5_IPSEC_ASO_REPLAY_WIN_256BIT = 0x3, 12112 }; 12113 12114 struct mlx5_ifc_ipsec_aso_bits { 12115 u8 valid[0x1]; 12116 u8 reserved_at_201[0x1]; 12117 u8 mode[0x2]; 12118 u8 window_sz[0x2]; 12119 u8 soft_lft_arm[0x1]; 12120 u8 hard_lft_arm[0x1]; 12121 u8 remove_flow_enable[0x1]; 12122 u8 esn_event_arm[0x1]; 12123 u8 reserved_at_20a[0x16]; 12124 12125 u8 remove_flow_pkt_cnt[0x20]; 12126 12127 u8 remove_flow_soft_lft[0x20]; 12128 12129 u8 reserved_at_260[0x80]; 12130 12131 u8 mode_parameter[0x20]; 12132 12133 u8 replay_protection_window[0x100]; 12134 }; 12135 12136 struct mlx5_ifc_ipsec_obj_bits { 12137 u8 modify_field_select[0x40]; 12138 u8 full_offload[0x1]; 12139 u8 reserved_at_41[0x1]; 12140 u8 esn_en[0x1]; 12141 u8 esn_overlap[0x1]; 12142 u8 reserved_at_44[0x2]; 12143 u8 icv_length[0x2]; 12144 u8 reserved_at_48[0x4]; 12145 u8 aso_return_reg[0x4]; 12146 u8 reserved_at_50[0x10]; 12147 12148 u8 esn_msb[0x20]; 12149 12150 u8 reserved_at_80[0x8]; 12151 u8 dekn[0x18]; 12152 12153 u8 salt[0x20]; 12154 12155 u8 implicit_iv[0x40]; 12156 12157 u8 reserved_at_100[0x8]; 12158 u8 ipsec_aso_access_pd[0x18]; 12159 u8 reserved_at_120[0xe0]; 12160 12161 struct mlx5_ifc_ipsec_aso_bits ipsec_aso; 12162 }; 12163 12164 struct mlx5_ifc_create_ipsec_obj_in_bits { 12165 struct mlx5_ifc_general_obj_in_cmd_hdr_bits general_obj_in_cmd_hdr; 12166 struct mlx5_ifc_ipsec_obj_bits ipsec_object; 12167 }; 12168 12169 enum { 12170 MLX5_MODIFY_IPSEC_BITMASK_ESN_OVERLAP = BIT(0), 12171 MLX5_MODIFY_IPSEC_BITMASK_ESN_MSB = BIT(1), 12172 }; 12173 12174 struct mlx5_ifc_query_ipsec_obj_out_bits { 12175 struct mlx5_ifc_general_obj_out_cmd_hdr_bits general_obj_out_cmd_hdr; 12176 struct mlx5_ifc_ipsec_obj_bits ipsec_object; 12177 }; 12178 12179 struct mlx5_ifc_modify_ipsec_obj_in_bits { 12180 struct mlx5_ifc_general_obj_in_cmd_hdr_bits general_obj_in_cmd_hdr; 12181 struct mlx5_ifc_ipsec_obj_bits ipsec_object; 12182 }; 12183 12184 enum { 12185 MLX5_MACSEC_ASO_REPLAY_PROTECTION = 0x1, 12186 }; 12187 12188 enum { 12189 MLX5_MACSEC_ASO_REPLAY_WIN_32BIT = 0x0, 12190 MLX5_MACSEC_ASO_REPLAY_WIN_64BIT = 0x1, 12191 MLX5_MACSEC_ASO_REPLAY_WIN_128BIT = 0x2, 12192 MLX5_MACSEC_ASO_REPLAY_WIN_256BIT = 0x3, 12193 }; 12194 12195 #define MLX5_MACSEC_ASO_INC_SN 0x2 12196 #define MLX5_MACSEC_ASO_REG_C_4_5 0x2 12197 12198 struct mlx5_ifc_macsec_aso_bits { 12199 u8 valid[0x1]; 12200 u8 reserved_at_1[0x1]; 12201 u8 mode[0x2]; 12202 u8 window_size[0x2]; 12203 u8 soft_lifetime_arm[0x1]; 12204 u8 hard_lifetime_arm[0x1]; 12205 u8 remove_flow_enable[0x1]; 12206 u8 epn_event_arm[0x1]; 12207 u8 reserved_at_a[0x16]; 12208 12209 u8 remove_flow_packet_count[0x20]; 12210 12211 u8 remove_flow_soft_lifetime[0x20]; 12212 12213 u8 reserved_at_60[0x80]; 12214 12215 u8 mode_parameter[0x20]; 12216 12217 u8 replay_protection_window[8][0x20]; 12218 }; 12219 12220 struct mlx5_ifc_macsec_offload_obj_bits { 12221 u8 modify_field_select[0x40]; 12222 12223 u8 confidentiality_en[0x1]; 12224 u8 reserved_at_41[0x1]; 12225 u8 epn_en[0x1]; 12226 u8 epn_overlap[0x1]; 12227 u8 reserved_at_44[0x2]; 12228 u8 confidentiality_offset[0x2]; 12229 u8 reserved_at_48[0x4]; 12230 u8 aso_return_reg[0x4]; 12231 u8 reserved_at_50[0x10]; 12232 12233 u8 epn_msb[0x20]; 12234 12235 u8 reserved_at_80[0x8]; 12236 u8 dekn[0x18]; 12237 12238 u8 reserved_at_a0[0x20]; 12239 12240 u8 sci[0x40]; 12241 12242 u8 reserved_at_100[0x8]; 12243 u8 macsec_aso_access_pd[0x18]; 12244 12245 u8 reserved_at_120[0x60]; 12246 12247 u8 salt[3][0x20]; 12248 12249 u8 reserved_at_1e0[0x20]; 12250 12251 struct mlx5_ifc_macsec_aso_bits macsec_aso; 12252 }; 12253 12254 struct mlx5_ifc_create_macsec_obj_in_bits { 12255 struct mlx5_ifc_general_obj_in_cmd_hdr_bits general_obj_in_cmd_hdr; 12256 struct mlx5_ifc_macsec_offload_obj_bits macsec_object; 12257 }; 12258 12259 struct mlx5_ifc_modify_macsec_obj_in_bits { 12260 struct mlx5_ifc_general_obj_in_cmd_hdr_bits general_obj_in_cmd_hdr; 12261 struct mlx5_ifc_macsec_offload_obj_bits macsec_object; 12262 }; 12263 12264 enum { 12265 MLX5_MODIFY_MACSEC_BITMASK_EPN_OVERLAP = BIT(0), 12266 MLX5_MODIFY_MACSEC_BITMASK_EPN_MSB = BIT(1), 12267 }; 12268 12269 struct mlx5_ifc_query_macsec_obj_out_bits { 12270 struct mlx5_ifc_general_obj_out_cmd_hdr_bits general_obj_out_cmd_hdr; 12271 struct mlx5_ifc_macsec_offload_obj_bits macsec_object; 12272 }; 12273 12274 struct mlx5_ifc_wrapped_dek_bits { 12275 u8 gcm_iv[0x60]; 12276 12277 u8 reserved_at_60[0x20]; 12278 12279 u8 const0[0x1]; 12280 u8 key_size[0x1]; 12281 u8 reserved_at_82[0x2]; 12282 u8 key2_invalid[0x1]; 12283 u8 reserved_at_85[0x3]; 12284 u8 pd[0x18]; 12285 12286 u8 key_purpose[0x5]; 12287 u8 reserved_at_a5[0x13]; 12288 u8 kek_id[0x8]; 12289 12290 u8 reserved_at_c0[0x40]; 12291 12292 u8 key1[0x8][0x20]; 12293 12294 u8 key2[0x8][0x20]; 12295 12296 u8 reserved_at_300[0x40]; 12297 12298 u8 const1[0x1]; 12299 u8 reserved_at_341[0x1f]; 12300 12301 u8 reserved_at_360[0x20]; 12302 12303 u8 auth_tag[0x80]; 12304 }; 12305 12306 struct mlx5_ifc_encryption_key_obj_bits { 12307 u8 modify_field_select[0x40]; 12308 12309 u8 state[0x8]; 12310 u8 sw_wrapped[0x1]; 12311 u8 reserved_at_49[0xb]; 12312 u8 key_size[0x4]; 12313 u8 reserved_at_58[0x4]; 12314 u8 key_purpose[0x4]; 12315 12316 u8 reserved_at_60[0x8]; 12317 u8 pd[0x18]; 12318 12319 u8 reserved_at_80[0x100]; 12320 12321 u8 opaque[0x40]; 12322 12323 u8 reserved_at_1c0[0x40]; 12324 12325 u8 key[8][0x80]; 12326 12327 u8 sw_wrapped_dek[8][0x80]; 12328 12329 u8 reserved_at_a00[0x600]; 12330 }; 12331 12332 struct mlx5_ifc_create_encryption_key_in_bits { 12333 struct mlx5_ifc_general_obj_in_cmd_hdr_bits general_obj_in_cmd_hdr; 12334 struct mlx5_ifc_encryption_key_obj_bits encryption_key_object; 12335 }; 12336 12337 struct mlx5_ifc_modify_encryption_key_in_bits { 12338 struct mlx5_ifc_general_obj_in_cmd_hdr_bits general_obj_in_cmd_hdr; 12339 struct mlx5_ifc_encryption_key_obj_bits encryption_key_object; 12340 }; 12341 12342 enum { 12343 MLX5_FLOW_METER_MODE_BYTES_IP_LENGTH = 0x0, 12344 MLX5_FLOW_METER_MODE_BYTES_CALC_WITH_L2 = 0x1, 12345 MLX5_FLOW_METER_MODE_BYTES_CALC_WITH_L2_IPG = 0x2, 12346 MLX5_FLOW_METER_MODE_NUM_PACKETS = 0x3, 12347 }; 12348 12349 struct mlx5_ifc_flow_meter_parameters_bits { 12350 u8 valid[0x1]; 12351 u8 bucket_overflow[0x1]; 12352 u8 start_color[0x2]; 12353 u8 both_buckets_on_green[0x1]; 12354 u8 reserved_at_5[0x1]; 12355 u8 meter_mode[0x2]; 12356 u8 reserved_at_8[0x18]; 12357 12358 u8 reserved_at_20[0x20]; 12359 12360 u8 reserved_at_40[0x3]; 12361 u8 cbs_exponent[0x5]; 12362 u8 cbs_mantissa[0x8]; 12363 u8 reserved_at_50[0x3]; 12364 u8 cir_exponent[0x5]; 12365 u8 cir_mantissa[0x8]; 12366 12367 u8 reserved_at_60[0x20]; 12368 12369 u8 reserved_at_80[0x3]; 12370 u8 ebs_exponent[0x5]; 12371 u8 ebs_mantissa[0x8]; 12372 u8 reserved_at_90[0x3]; 12373 u8 eir_exponent[0x5]; 12374 u8 eir_mantissa[0x8]; 12375 12376 u8 reserved_at_a0[0x60]; 12377 }; 12378 12379 struct mlx5_ifc_flow_meter_aso_obj_bits { 12380 u8 modify_field_select[0x40]; 12381 12382 u8 reserved_at_40[0x40]; 12383 12384 u8 reserved_at_80[0x8]; 12385 u8 meter_aso_access_pd[0x18]; 12386 12387 u8 reserved_at_a0[0x160]; 12388 12389 struct mlx5_ifc_flow_meter_parameters_bits flow_meter_parameters[2]; 12390 }; 12391 12392 struct mlx5_ifc_create_flow_meter_aso_obj_in_bits { 12393 struct mlx5_ifc_general_obj_in_cmd_hdr_bits hdr; 12394 struct mlx5_ifc_flow_meter_aso_obj_bits flow_meter_aso_obj; 12395 }; 12396 12397 struct mlx5_ifc_int_kek_obj_bits { 12398 u8 modify_field_select[0x40]; 12399 12400 u8 state[0x8]; 12401 u8 auto_gen[0x1]; 12402 u8 reserved_at_49[0xb]; 12403 u8 key_size[0x4]; 12404 u8 reserved_at_58[0x8]; 12405 12406 u8 reserved_at_60[0x8]; 12407 u8 pd[0x18]; 12408 12409 u8 reserved_at_80[0x180]; 12410 u8 key[8][0x80]; 12411 12412 u8 reserved_at_600[0x200]; 12413 }; 12414 12415 struct mlx5_ifc_create_int_kek_obj_in_bits { 12416 struct mlx5_ifc_general_obj_in_cmd_hdr_bits general_obj_in_cmd_hdr; 12417 struct mlx5_ifc_int_kek_obj_bits int_kek_object; 12418 }; 12419 12420 struct mlx5_ifc_create_int_kek_obj_out_bits { 12421 struct mlx5_ifc_general_obj_out_cmd_hdr_bits general_obj_out_cmd_hdr; 12422 struct mlx5_ifc_int_kek_obj_bits int_kek_object; 12423 }; 12424 12425 struct mlx5_ifc_sampler_obj_bits { 12426 u8 modify_field_select[0x40]; 12427 12428 u8 table_type[0x8]; 12429 u8 level[0x8]; 12430 u8 reserved_at_50[0xf]; 12431 u8 ignore_flow_level[0x1]; 12432 12433 u8 sample_ratio[0x20]; 12434 12435 u8 reserved_at_80[0x8]; 12436 u8 sample_table_id[0x18]; 12437 12438 u8 reserved_at_a0[0x8]; 12439 u8 default_table_id[0x18]; 12440 12441 u8 sw_steering_icm_address_rx[0x40]; 12442 u8 sw_steering_icm_address_tx[0x40]; 12443 12444 u8 reserved_at_140[0xa0]; 12445 }; 12446 12447 struct mlx5_ifc_create_sampler_obj_in_bits { 12448 struct mlx5_ifc_general_obj_in_cmd_hdr_bits general_obj_in_cmd_hdr; 12449 struct mlx5_ifc_sampler_obj_bits sampler_object; 12450 }; 12451 12452 struct mlx5_ifc_query_sampler_obj_out_bits { 12453 struct mlx5_ifc_general_obj_out_cmd_hdr_bits general_obj_out_cmd_hdr; 12454 struct mlx5_ifc_sampler_obj_bits sampler_object; 12455 }; 12456 12457 enum { 12458 MLX5_GENERAL_OBJECT_TYPE_ENCRYPTION_KEY_KEY_SIZE_128 = 0x0, 12459 MLX5_GENERAL_OBJECT_TYPE_ENCRYPTION_KEY_KEY_SIZE_256 = 0x1, 12460 }; 12461 12462 enum { 12463 MLX5_GENERAL_OBJECT_TYPE_ENCRYPTION_KEY_PURPOSE_TLS = 0x1, 12464 MLX5_GENERAL_OBJECT_TYPE_ENCRYPTION_KEY_PURPOSE_IPSEC = 0x2, 12465 MLX5_GENERAL_OBJECT_TYPE_ENCRYPTION_KEY_PURPOSE_MACSEC = 0x4, 12466 }; 12467 12468 struct mlx5_ifc_tls_static_params_bits { 12469 u8 const_2[0x2]; 12470 u8 tls_version[0x4]; 12471 u8 const_1[0x2]; 12472 u8 reserved_at_8[0x14]; 12473 u8 encryption_standard[0x4]; 12474 12475 u8 reserved_at_20[0x20]; 12476 12477 u8 initial_record_number[0x40]; 12478 12479 u8 resync_tcp_sn[0x20]; 12480 12481 u8 gcm_iv[0x20]; 12482 12483 u8 implicit_iv[0x40]; 12484 12485 u8 reserved_at_100[0x8]; 12486 u8 dek_index[0x18]; 12487 12488 u8 reserved_at_120[0xe0]; 12489 }; 12490 12491 struct mlx5_ifc_tls_progress_params_bits { 12492 u8 next_record_tcp_sn[0x20]; 12493 12494 u8 hw_resync_tcp_sn[0x20]; 12495 12496 u8 record_tracker_state[0x2]; 12497 u8 auth_state[0x2]; 12498 u8 reserved_at_44[0x4]; 12499 u8 hw_offset_record_number[0x18]; 12500 }; 12501 12502 enum { 12503 MLX5_MTT_PERM_READ = 1 << 0, 12504 MLX5_MTT_PERM_WRITE = 1 << 1, 12505 MLX5_MTT_PERM_RW = MLX5_MTT_PERM_READ | MLX5_MTT_PERM_WRITE, 12506 }; 12507 12508 enum { 12509 MLX5_SUSPEND_VHCA_IN_OP_MOD_SUSPEND_INITIATOR = 0x0, 12510 MLX5_SUSPEND_VHCA_IN_OP_MOD_SUSPEND_RESPONDER = 0x1, 12511 }; 12512 12513 struct mlx5_ifc_suspend_vhca_in_bits { 12514 u8 opcode[0x10]; 12515 u8 uid[0x10]; 12516 12517 u8 reserved_at_20[0x10]; 12518 u8 op_mod[0x10]; 12519 12520 u8 reserved_at_40[0x10]; 12521 u8 vhca_id[0x10]; 12522 12523 u8 reserved_at_60[0x20]; 12524 }; 12525 12526 struct mlx5_ifc_suspend_vhca_out_bits { 12527 u8 status[0x8]; 12528 u8 reserved_at_8[0x18]; 12529 12530 u8 syndrome[0x20]; 12531 12532 u8 reserved_at_40[0x40]; 12533 }; 12534 12535 enum { 12536 MLX5_RESUME_VHCA_IN_OP_MOD_RESUME_RESPONDER = 0x0, 12537 MLX5_RESUME_VHCA_IN_OP_MOD_RESUME_INITIATOR = 0x1, 12538 }; 12539 12540 struct mlx5_ifc_resume_vhca_in_bits { 12541 u8 opcode[0x10]; 12542 u8 uid[0x10]; 12543 12544 u8 reserved_at_20[0x10]; 12545 u8 op_mod[0x10]; 12546 12547 u8 reserved_at_40[0x10]; 12548 u8 vhca_id[0x10]; 12549 12550 u8 reserved_at_60[0x20]; 12551 }; 12552 12553 struct mlx5_ifc_resume_vhca_out_bits { 12554 u8 status[0x8]; 12555 u8 reserved_at_8[0x18]; 12556 12557 u8 syndrome[0x20]; 12558 12559 u8 reserved_at_40[0x40]; 12560 }; 12561 12562 struct mlx5_ifc_query_vhca_migration_state_in_bits { 12563 u8 opcode[0x10]; 12564 u8 uid[0x10]; 12565 12566 u8 reserved_at_20[0x10]; 12567 u8 op_mod[0x10]; 12568 12569 u8 incremental[0x1]; 12570 u8 chunk[0x1]; 12571 u8 reserved_at_42[0xe]; 12572 u8 vhca_id[0x10]; 12573 12574 u8 reserved_at_60[0x20]; 12575 }; 12576 12577 struct mlx5_ifc_query_vhca_migration_state_out_bits { 12578 u8 status[0x8]; 12579 u8 reserved_at_8[0x18]; 12580 12581 u8 syndrome[0x20]; 12582 12583 u8 reserved_at_40[0x40]; 12584 12585 u8 required_umem_size[0x20]; 12586 12587 u8 reserved_at_a0[0x20]; 12588 12589 u8 remaining_total_size[0x40]; 12590 12591 u8 reserved_at_100[0x100]; 12592 }; 12593 12594 struct mlx5_ifc_save_vhca_state_in_bits { 12595 u8 opcode[0x10]; 12596 u8 uid[0x10]; 12597 12598 u8 reserved_at_20[0x10]; 12599 u8 op_mod[0x10]; 12600 12601 u8 incremental[0x1]; 12602 u8 set_track[0x1]; 12603 u8 reserved_at_42[0xe]; 12604 u8 vhca_id[0x10]; 12605 12606 u8 reserved_at_60[0x20]; 12607 12608 u8 va[0x40]; 12609 12610 u8 mkey[0x20]; 12611 12612 u8 size[0x20]; 12613 }; 12614 12615 struct mlx5_ifc_save_vhca_state_out_bits { 12616 u8 status[0x8]; 12617 u8 reserved_at_8[0x18]; 12618 12619 u8 syndrome[0x20]; 12620 12621 u8 actual_image_size[0x20]; 12622 12623 u8 next_required_umem_size[0x20]; 12624 }; 12625 12626 struct mlx5_ifc_load_vhca_state_in_bits { 12627 u8 opcode[0x10]; 12628 u8 uid[0x10]; 12629 12630 u8 reserved_at_20[0x10]; 12631 u8 op_mod[0x10]; 12632 12633 u8 reserved_at_40[0x10]; 12634 u8 vhca_id[0x10]; 12635 12636 u8 reserved_at_60[0x20]; 12637 12638 u8 va[0x40]; 12639 12640 u8 mkey[0x20]; 12641 12642 u8 size[0x20]; 12643 }; 12644 12645 struct mlx5_ifc_load_vhca_state_out_bits { 12646 u8 status[0x8]; 12647 u8 reserved_at_8[0x18]; 12648 12649 u8 syndrome[0x20]; 12650 12651 u8 reserved_at_40[0x40]; 12652 }; 12653 12654 struct mlx5_ifc_adv_virtualization_cap_bits { 12655 u8 reserved_at_0[0x3]; 12656 u8 pg_track_log_max_num[0x5]; 12657 u8 pg_track_max_num_range[0x8]; 12658 u8 pg_track_log_min_addr_space[0x8]; 12659 u8 pg_track_log_max_addr_space[0x8]; 12660 12661 u8 reserved_at_20[0x3]; 12662 u8 pg_track_log_min_msg_size[0x5]; 12663 u8 reserved_at_28[0x3]; 12664 u8 pg_track_log_max_msg_size[0x5]; 12665 u8 reserved_at_30[0x3]; 12666 u8 pg_track_log_min_page_size[0x5]; 12667 u8 reserved_at_38[0x3]; 12668 u8 pg_track_log_max_page_size[0x5]; 12669 12670 u8 reserved_at_40[0x7c0]; 12671 }; 12672 12673 struct mlx5_ifc_page_track_report_entry_bits { 12674 u8 dirty_address_high[0x20]; 12675 12676 u8 dirty_address_low[0x20]; 12677 }; 12678 12679 enum { 12680 MLX5_PAGE_TRACK_STATE_TRACKING, 12681 MLX5_PAGE_TRACK_STATE_REPORTING, 12682 MLX5_PAGE_TRACK_STATE_ERROR, 12683 }; 12684 12685 struct mlx5_ifc_page_track_range_bits { 12686 u8 start_address[0x40]; 12687 12688 u8 length[0x40]; 12689 }; 12690 12691 struct mlx5_ifc_page_track_bits { 12692 u8 modify_field_select[0x40]; 12693 12694 u8 reserved_at_40[0x10]; 12695 u8 vhca_id[0x10]; 12696 12697 u8 reserved_at_60[0x20]; 12698 12699 u8 state[0x4]; 12700 u8 track_type[0x4]; 12701 u8 log_addr_space_size[0x8]; 12702 u8 reserved_at_90[0x3]; 12703 u8 log_page_size[0x5]; 12704 u8 reserved_at_98[0x3]; 12705 u8 log_msg_size[0x5]; 12706 12707 u8 reserved_at_a0[0x8]; 12708 u8 reporting_qpn[0x18]; 12709 12710 u8 reserved_at_c0[0x18]; 12711 u8 num_ranges[0x8]; 12712 12713 u8 reserved_at_e0[0x20]; 12714 12715 u8 range_start_address[0x40]; 12716 12717 u8 length[0x40]; 12718 12719 struct mlx5_ifc_page_track_range_bits track_range[0]; 12720 }; 12721 12722 struct mlx5_ifc_create_page_track_obj_in_bits { 12723 struct mlx5_ifc_general_obj_in_cmd_hdr_bits general_obj_in_cmd_hdr; 12724 struct mlx5_ifc_page_track_bits obj_context; 12725 }; 12726 12727 struct mlx5_ifc_modify_page_track_obj_in_bits { 12728 struct mlx5_ifc_general_obj_in_cmd_hdr_bits general_obj_in_cmd_hdr; 12729 struct mlx5_ifc_page_track_bits obj_context; 12730 }; 12731 12732 struct mlx5_ifc_query_page_track_obj_out_bits { 12733 struct mlx5_ifc_general_obj_out_cmd_hdr_bits general_obj_out_cmd_hdr; 12734 struct mlx5_ifc_page_track_bits obj_context; 12735 }; 12736 12737 struct mlx5_ifc_msecq_reg_bits { 12738 u8 reserved_at_0[0x20]; 12739 12740 u8 reserved_at_20[0x12]; 12741 u8 network_option[0x2]; 12742 u8 local_ssm_code[0x4]; 12743 u8 local_enhanced_ssm_code[0x8]; 12744 12745 u8 local_clock_identity[0x40]; 12746 12747 u8 reserved_at_80[0x180]; 12748 }; 12749 12750 enum { 12751 MLX5_MSEES_FIELD_SELECT_ENABLE = BIT(0), 12752 MLX5_MSEES_FIELD_SELECT_ADMIN_STATUS = BIT(1), 12753 MLX5_MSEES_FIELD_SELECT_ADMIN_FREQ_MEASURE = BIT(2), 12754 }; 12755 12756 enum mlx5_msees_admin_status { 12757 MLX5_MSEES_ADMIN_STATUS_FREE_RUNNING = 0x0, 12758 MLX5_MSEES_ADMIN_STATUS_TRACK = 0x1, 12759 }; 12760 12761 enum mlx5_msees_oper_status { 12762 MLX5_MSEES_OPER_STATUS_FREE_RUNNING = 0x0, 12763 MLX5_MSEES_OPER_STATUS_SELF_TRACK = 0x1, 12764 MLX5_MSEES_OPER_STATUS_OTHER_TRACK = 0x2, 12765 MLX5_MSEES_OPER_STATUS_HOLDOVER = 0x3, 12766 MLX5_MSEES_OPER_STATUS_FAIL_HOLDOVER = 0x4, 12767 MLX5_MSEES_OPER_STATUS_FAIL_FREE_RUNNING = 0x5, 12768 }; 12769 12770 enum mlx5_msees_failure_reason { 12771 MLX5_MSEES_FAILURE_REASON_UNDEFINED_ERROR = 0x0, 12772 MLX5_MSEES_FAILURE_REASON_PORT_DOWN = 0x1, 12773 MLX5_MSEES_FAILURE_REASON_TOO_HIGH_FREQUENCY_DIFF = 0x2, 12774 MLX5_MSEES_FAILURE_REASON_NET_SYNCHRONIZER_DEVICE_ERROR = 0x3, 12775 MLX5_MSEES_FAILURE_REASON_LACK_OF_RESOURCES = 0x4, 12776 }; 12777 12778 struct mlx5_ifc_msees_reg_bits { 12779 u8 reserved_at_0[0x8]; 12780 u8 local_port[0x8]; 12781 u8 pnat[0x2]; 12782 u8 lp_msb[0x2]; 12783 u8 reserved_at_14[0xc]; 12784 12785 u8 field_select[0x20]; 12786 12787 u8 admin_status[0x4]; 12788 u8 oper_status[0x4]; 12789 u8 ho_acq[0x1]; 12790 u8 reserved_at_49[0xc]; 12791 u8 admin_freq_measure[0x1]; 12792 u8 oper_freq_measure[0x1]; 12793 u8 failure_reason[0x9]; 12794 12795 u8 frequency_diff[0x20]; 12796 12797 u8 reserved_at_80[0x180]; 12798 }; 12799 12800 #endif /* MLX5_IFC_H */ 12801