1 /* 2 * Copyright (c) 2013-2015, Mellanox Technologies, Ltd. All rights reserved. 3 * 4 * This software is available to you under a choice of one of two 5 * licenses. You may choose to be licensed under the terms of the GNU 6 * General Public License (GPL) Version 2, available from the file 7 * COPYING in the main directory of this source tree, or the 8 * OpenIB.org BSD license below: 9 * 10 * Redistribution and use in source and binary forms, with or 11 * without modification, are permitted provided that the following 12 * conditions are met: 13 * 14 * - Redistributions of source code must retain the above 15 * copyright notice, this list of conditions and the following 16 * disclaimer. 17 * 18 * - Redistributions in binary form must reproduce the above 19 * copyright notice, this list of conditions and the following 20 * disclaimer in the documentation and/or other materials 21 * provided with the distribution. 22 * 23 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, 24 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF 25 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND 26 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS 27 * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN 28 * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN 29 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE 30 * SOFTWARE. 31 */ 32 #ifndef MLX5_IFC_H 33 #define MLX5_IFC_H 34 35 #include "mlx5_ifc_fpga.h" 36 37 enum { 38 MLX5_EVENT_TYPE_CODING_COMPLETION_EVENTS = 0x0, 39 MLX5_EVENT_TYPE_CODING_PATH_MIGRATED_SUCCEEDED = 0x1, 40 MLX5_EVENT_TYPE_CODING_COMMUNICATION_ESTABLISHED = 0x2, 41 MLX5_EVENT_TYPE_CODING_SEND_QUEUE_DRAINED = 0x3, 42 MLX5_EVENT_TYPE_CODING_LAST_WQE_REACHED = 0x13, 43 MLX5_EVENT_TYPE_CODING_SRQ_LIMIT = 0x14, 44 MLX5_EVENT_TYPE_CODING_DCT_ALL_CONNECTIONS_CLOSED = 0x1c, 45 MLX5_EVENT_TYPE_CODING_DCT_ACCESS_KEY_VIOLATION = 0x1d, 46 MLX5_EVENT_TYPE_CODING_CQ_ERROR = 0x4, 47 MLX5_EVENT_TYPE_CODING_LOCAL_WQ_CATASTROPHIC_ERROR = 0x5, 48 MLX5_EVENT_TYPE_CODING_PATH_MIGRATION_FAILED = 0x7, 49 MLX5_EVENT_TYPE_CODING_PAGE_FAULT_EVENT = 0xc, 50 MLX5_EVENT_TYPE_CODING_INVALID_REQUEST_LOCAL_WQ_ERROR = 0x10, 51 MLX5_EVENT_TYPE_CODING_LOCAL_ACCESS_VIOLATION_WQ_ERROR = 0x11, 52 MLX5_EVENT_TYPE_CODING_LOCAL_SRQ_CATASTROPHIC_ERROR = 0x12, 53 MLX5_EVENT_TYPE_CODING_INTERNAL_ERROR = 0x8, 54 MLX5_EVENT_TYPE_CODING_PORT_STATE_CHANGE = 0x9, 55 MLX5_EVENT_TYPE_CODING_GPIO_EVENT = 0x15, 56 MLX5_EVENT_TYPE_CODING_REMOTE_CONFIGURATION_PROTOCOL_EVENT = 0x19, 57 MLX5_EVENT_TYPE_CODING_DOORBELL_BLUEFLAME_CONGESTION_EVENT = 0x1a, 58 MLX5_EVENT_TYPE_CODING_STALL_VL_EVENT = 0x1b, 59 MLX5_EVENT_TYPE_CODING_DROPPED_PACKET_LOGGED_EVENT = 0x1f, 60 MLX5_EVENT_TYPE_CODING_COMMAND_INTERFACE_COMPLETION = 0xa, 61 MLX5_EVENT_TYPE_CODING_PAGE_REQUEST = 0xb, 62 MLX5_EVENT_TYPE_CODING_FPGA_ERROR = 0x20, 63 MLX5_EVENT_TYPE_CODING_FPGA_QP_ERROR = 0x21 64 }; 65 66 enum { 67 MLX5_SET_HCA_CAP_OP_MOD_GENERAL_DEVICE = 0x0, 68 MLX5_SET_HCA_CAP_OP_MOD_ETHERNET_OFFLOADS = 0x1, 69 MLX5_SET_HCA_CAP_OP_MOD_ODP = 0x2, 70 MLX5_SET_HCA_CAP_OP_MOD_ATOMIC = 0x3, 71 MLX5_SET_HCA_CAP_OP_MOD_ROCE = 0x4, 72 MLX5_SET_HCA_CAP_OP_MOD_IPSEC = 0x15, 73 MLX5_SET_HCA_CAP_OP_MOD_GENERAL_DEVICE2 = 0x20, 74 MLX5_SET_HCA_CAP_OP_MOD_PORT_SELECTION = 0x25, 75 }; 76 77 enum { 78 MLX5_SHARED_RESOURCE_UID = 0xffff, 79 }; 80 81 enum { 82 MLX5_OBJ_TYPE_SW_ICM = 0x0008, 83 MLX5_OBJ_TYPE_GENEVE_TLV_OPT = 0x000b, 84 MLX5_OBJ_TYPE_VIRTIO_NET_Q = 0x000d, 85 MLX5_OBJ_TYPE_VIRTIO_Q_COUNTERS = 0x001c, 86 MLX5_OBJ_TYPE_MATCH_DEFINER = 0x0018, 87 MLX5_OBJ_TYPE_HEADER_MODIFY_ARGUMENT = 0x23, 88 MLX5_OBJ_TYPE_STC = 0x0040, 89 MLX5_OBJ_TYPE_RTC = 0x0041, 90 MLX5_OBJ_TYPE_STE = 0x0042, 91 MLX5_OBJ_TYPE_MODIFY_HDR_PATTERN = 0x0043, 92 MLX5_OBJ_TYPE_PAGE_TRACK = 0x46, 93 MLX5_OBJ_TYPE_MKEY = 0xff01, 94 MLX5_OBJ_TYPE_QP = 0xff02, 95 MLX5_OBJ_TYPE_PSV = 0xff03, 96 MLX5_OBJ_TYPE_RMP = 0xff04, 97 MLX5_OBJ_TYPE_XRC_SRQ = 0xff05, 98 MLX5_OBJ_TYPE_RQ = 0xff06, 99 MLX5_OBJ_TYPE_SQ = 0xff07, 100 MLX5_OBJ_TYPE_TIR = 0xff08, 101 MLX5_OBJ_TYPE_TIS = 0xff09, 102 MLX5_OBJ_TYPE_DCT = 0xff0a, 103 MLX5_OBJ_TYPE_XRQ = 0xff0b, 104 MLX5_OBJ_TYPE_RQT = 0xff0e, 105 MLX5_OBJ_TYPE_FLOW_COUNTER = 0xff0f, 106 MLX5_OBJ_TYPE_CQ = 0xff10, 107 MLX5_OBJ_TYPE_FT_ALIAS = 0xff15, 108 }; 109 110 enum { 111 MLX5_GENERAL_OBJ_TYPES_CAP_SW_ICM = (1ULL << MLX5_OBJ_TYPE_SW_ICM), 112 MLX5_GENERAL_OBJ_TYPES_CAP_GENEVE_TLV_OPT = (1ULL << 11), 113 MLX5_GENERAL_OBJ_TYPES_CAP_VIRTIO_NET_Q = (1ULL << 13), 114 MLX5_GENERAL_OBJ_TYPES_CAP_HEADER_MODIFY_ARGUMENT = 115 (1ULL << MLX5_OBJ_TYPE_HEADER_MODIFY_ARGUMENT), 116 MLX5_GENERAL_OBJ_TYPES_CAP_MACSEC_OFFLOAD = (1ULL << 39), 117 }; 118 119 enum { 120 MLX5_CMD_OP_QUERY_HCA_CAP = 0x100, 121 MLX5_CMD_OP_QUERY_ADAPTER = 0x101, 122 MLX5_CMD_OP_INIT_HCA = 0x102, 123 MLX5_CMD_OP_TEARDOWN_HCA = 0x103, 124 MLX5_CMD_OP_ENABLE_HCA = 0x104, 125 MLX5_CMD_OP_DISABLE_HCA = 0x105, 126 MLX5_CMD_OP_QUERY_PAGES = 0x107, 127 MLX5_CMD_OP_MANAGE_PAGES = 0x108, 128 MLX5_CMD_OP_SET_HCA_CAP = 0x109, 129 MLX5_CMD_OP_QUERY_ISSI = 0x10a, 130 MLX5_CMD_OP_SET_ISSI = 0x10b, 131 MLX5_CMD_OP_SET_DRIVER_VERSION = 0x10d, 132 MLX5_CMD_OP_QUERY_SF_PARTITION = 0x111, 133 MLX5_CMD_OP_ALLOC_SF = 0x113, 134 MLX5_CMD_OP_DEALLOC_SF = 0x114, 135 MLX5_CMD_OP_SUSPEND_VHCA = 0x115, 136 MLX5_CMD_OP_RESUME_VHCA = 0x116, 137 MLX5_CMD_OP_QUERY_VHCA_MIGRATION_STATE = 0x117, 138 MLX5_CMD_OP_SAVE_VHCA_STATE = 0x118, 139 MLX5_CMD_OP_LOAD_VHCA_STATE = 0x119, 140 MLX5_CMD_OP_CREATE_MKEY = 0x200, 141 MLX5_CMD_OP_QUERY_MKEY = 0x201, 142 MLX5_CMD_OP_DESTROY_MKEY = 0x202, 143 MLX5_CMD_OP_QUERY_SPECIAL_CONTEXTS = 0x203, 144 MLX5_CMD_OP_PAGE_FAULT_RESUME = 0x204, 145 MLX5_CMD_OP_ALLOC_MEMIC = 0x205, 146 MLX5_CMD_OP_DEALLOC_MEMIC = 0x206, 147 MLX5_CMD_OP_MODIFY_MEMIC = 0x207, 148 MLX5_CMD_OP_CREATE_EQ = 0x301, 149 MLX5_CMD_OP_DESTROY_EQ = 0x302, 150 MLX5_CMD_OP_QUERY_EQ = 0x303, 151 MLX5_CMD_OP_GEN_EQE = 0x304, 152 MLX5_CMD_OP_CREATE_CQ = 0x400, 153 MLX5_CMD_OP_DESTROY_CQ = 0x401, 154 MLX5_CMD_OP_QUERY_CQ = 0x402, 155 MLX5_CMD_OP_MODIFY_CQ = 0x403, 156 MLX5_CMD_OP_CREATE_QP = 0x500, 157 MLX5_CMD_OP_DESTROY_QP = 0x501, 158 MLX5_CMD_OP_RST2INIT_QP = 0x502, 159 MLX5_CMD_OP_INIT2RTR_QP = 0x503, 160 MLX5_CMD_OP_RTR2RTS_QP = 0x504, 161 MLX5_CMD_OP_RTS2RTS_QP = 0x505, 162 MLX5_CMD_OP_SQERR2RTS_QP = 0x506, 163 MLX5_CMD_OP_2ERR_QP = 0x507, 164 MLX5_CMD_OP_2RST_QP = 0x50a, 165 MLX5_CMD_OP_QUERY_QP = 0x50b, 166 MLX5_CMD_OP_SQD_RTS_QP = 0x50c, 167 MLX5_CMD_OP_INIT2INIT_QP = 0x50e, 168 MLX5_CMD_OP_CREATE_PSV = 0x600, 169 MLX5_CMD_OP_DESTROY_PSV = 0x601, 170 MLX5_CMD_OP_CREATE_SRQ = 0x700, 171 MLX5_CMD_OP_DESTROY_SRQ = 0x701, 172 MLX5_CMD_OP_QUERY_SRQ = 0x702, 173 MLX5_CMD_OP_ARM_RQ = 0x703, 174 MLX5_CMD_OP_CREATE_XRC_SRQ = 0x705, 175 MLX5_CMD_OP_DESTROY_XRC_SRQ = 0x706, 176 MLX5_CMD_OP_QUERY_XRC_SRQ = 0x707, 177 MLX5_CMD_OP_ARM_XRC_SRQ = 0x708, 178 MLX5_CMD_OP_CREATE_DCT = 0x710, 179 MLX5_CMD_OP_DESTROY_DCT = 0x711, 180 MLX5_CMD_OP_DRAIN_DCT = 0x712, 181 MLX5_CMD_OP_QUERY_DCT = 0x713, 182 MLX5_CMD_OP_ARM_DCT_FOR_KEY_VIOLATION = 0x714, 183 MLX5_CMD_OP_CREATE_XRQ = 0x717, 184 MLX5_CMD_OP_DESTROY_XRQ = 0x718, 185 MLX5_CMD_OP_QUERY_XRQ = 0x719, 186 MLX5_CMD_OP_ARM_XRQ = 0x71a, 187 MLX5_CMD_OP_QUERY_XRQ_DC_PARAMS_ENTRY = 0x725, 188 MLX5_CMD_OP_SET_XRQ_DC_PARAMS_ENTRY = 0x726, 189 MLX5_CMD_OP_QUERY_XRQ_ERROR_PARAMS = 0x727, 190 MLX5_CMD_OP_RELEASE_XRQ_ERROR = 0x729, 191 MLX5_CMD_OP_MODIFY_XRQ = 0x72a, 192 MLX5_CMD_OPCODE_QUERY_DELEGATED_VHCA = 0x732, 193 MLX5_CMD_OPCODE_CREATE_ESW_VPORT = 0x733, 194 MLX5_CMD_OPCODE_DESTROY_ESW_VPORT = 0x734, 195 MLX5_CMD_OP_QUERY_ESW_FUNCTIONS = 0x740, 196 MLX5_CMD_OP_QUERY_VPORT_STATE = 0x750, 197 MLX5_CMD_OP_MODIFY_VPORT_STATE = 0x751, 198 MLX5_CMD_OP_QUERY_ESW_VPORT_CONTEXT = 0x752, 199 MLX5_CMD_OP_MODIFY_ESW_VPORT_CONTEXT = 0x753, 200 MLX5_CMD_OP_QUERY_NIC_VPORT_CONTEXT = 0x754, 201 MLX5_CMD_OP_MODIFY_NIC_VPORT_CONTEXT = 0x755, 202 MLX5_CMD_OP_QUERY_ROCE_ADDRESS = 0x760, 203 MLX5_CMD_OP_SET_ROCE_ADDRESS = 0x761, 204 MLX5_CMD_OP_QUERY_HCA_VPORT_CONTEXT = 0x762, 205 MLX5_CMD_OP_MODIFY_HCA_VPORT_CONTEXT = 0x763, 206 MLX5_CMD_OP_QUERY_HCA_VPORT_GID = 0x764, 207 MLX5_CMD_OP_QUERY_HCA_VPORT_PKEY = 0x765, 208 MLX5_CMD_OP_QUERY_VNIC_ENV = 0x76f, 209 MLX5_CMD_OP_QUERY_VPORT_COUNTER = 0x770, 210 MLX5_CMD_OP_ALLOC_Q_COUNTER = 0x771, 211 MLX5_CMD_OP_DEALLOC_Q_COUNTER = 0x772, 212 MLX5_CMD_OP_QUERY_Q_COUNTER = 0x773, 213 MLX5_CMD_OP_SET_MONITOR_COUNTER = 0x774, 214 MLX5_CMD_OP_ARM_MONITOR_COUNTER = 0x775, 215 MLX5_CMD_OP_SET_PP_RATE_LIMIT = 0x780, 216 MLX5_CMD_OP_QUERY_RATE_LIMIT = 0x781, 217 MLX5_CMD_OP_CREATE_SCHEDULING_ELEMENT = 0x782, 218 MLX5_CMD_OP_DESTROY_SCHEDULING_ELEMENT = 0x783, 219 MLX5_CMD_OP_QUERY_SCHEDULING_ELEMENT = 0x784, 220 MLX5_CMD_OP_MODIFY_SCHEDULING_ELEMENT = 0x785, 221 MLX5_CMD_OP_CREATE_QOS_PARA_VPORT = 0x786, 222 MLX5_CMD_OP_DESTROY_QOS_PARA_VPORT = 0x787, 223 MLX5_CMD_OP_ALLOC_PD = 0x800, 224 MLX5_CMD_OP_DEALLOC_PD = 0x801, 225 MLX5_CMD_OP_ALLOC_UAR = 0x802, 226 MLX5_CMD_OP_DEALLOC_UAR = 0x803, 227 MLX5_CMD_OP_CONFIG_INT_MODERATION = 0x804, 228 MLX5_CMD_OP_ACCESS_REG = 0x805, 229 MLX5_CMD_OP_ATTACH_TO_MCG = 0x806, 230 MLX5_CMD_OP_DETACH_FROM_MCG = 0x807, 231 MLX5_CMD_OP_GET_DROPPED_PACKET_LOG = 0x80a, 232 MLX5_CMD_OP_MAD_IFC = 0x50d, 233 MLX5_CMD_OP_QUERY_MAD_DEMUX = 0x80b, 234 MLX5_CMD_OP_SET_MAD_DEMUX = 0x80c, 235 MLX5_CMD_OP_NOP = 0x80d, 236 MLX5_CMD_OP_ALLOC_XRCD = 0x80e, 237 MLX5_CMD_OP_DEALLOC_XRCD = 0x80f, 238 MLX5_CMD_OP_ALLOC_TRANSPORT_DOMAIN = 0x816, 239 MLX5_CMD_OP_DEALLOC_TRANSPORT_DOMAIN = 0x817, 240 MLX5_CMD_OP_QUERY_CONG_STATUS = 0x822, 241 MLX5_CMD_OP_MODIFY_CONG_STATUS = 0x823, 242 MLX5_CMD_OP_QUERY_CONG_PARAMS = 0x824, 243 MLX5_CMD_OP_MODIFY_CONG_PARAMS = 0x825, 244 MLX5_CMD_OP_QUERY_CONG_STATISTICS = 0x826, 245 MLX5_CMD_OP_ADD_VXLAN_UDP_DPORT = 0x827, 246 MLX5_CMD_OP_DELETE_VXLAN_UDP_DPORT = 0x828, 247 MLX5_CMD_OP_SET_L2_TABLE_ENTRY = 0x829, 248 MLX5_CMD_OP_QUERY_L2_TABLE_ENTRY = 0x82a, 249 MLX5_CMD_OP_DELETE_L2_TABLE_ENTRY = 0x82b, 250 MLX5_CMD_OP_SET_WOL_ROL = 0x830, 251 MLX5_CMD_OP_QUERY_WOL_ROL = 0x831, 252 MLX5_CMD_OP_CREATE_LAG = 0x840, 253 MLX5_CMD_OP_MODIFY_LAG = 0x841, 254 MLX5_CMD_OP_QUERY_LAG = 0x842, 255 MLX5_CMD_OP_DESTROY_LAG = 0x843, 256 MLX5_CMD_OP_CREATE_VPORT_LAG = 0x844, 257 MLX5_CMD_OP_DESTROY_VPORT_LAG = 0x845, 258 MLX5_CMD_OP_CREATE_TIR = 0x900, 259 MLX5_CMD_OP_MODIFY_TIR = 0x901, 260 MLX5_CMD_OP_DESTROY_TIR = 0x902, 261 MLX5_CMD_OP_QUERY_TIR = 0x903, 262 MLX5_CMD_OP_CREATE_SQ = 0x904, 263 MLX5_CMD_OP_MODIFY_SQ = 0x905, 264 MLX5_CMD_OP_DESTROY_SQ = 0x906, 265 MLX5_CMD_OP_QUERY_SQ = 0x907, 266 MLX5_CMD_OP_CREATE_RQ = 0x908, 267 MLX5_CMD_OP_MODIFY_RQ = 0x909, 268 MLX5_CMD_OP_SET_DELAY_DROP_PARAMS = 0x910, 269 MLX5_CMD_OP_DESTROY_RQ = 0x90a, 270 MLX5_CMD_OP_QUERY_RQ = 0x90b, 271 MLX5_CMD_OP_CREATE_RMP = 0x90c, 272 MLX5_CMD_OP_MODIFY_RMP = 0x90d, 273 MLX5_CMD_OP_DESTROY_RMP = 0x90e, 274 MLX5_CMD_OP_QUERY_RMP = 0x90f, 275 MLX5_CMD_OP_CREATE_TIS = 0x912, 276 MLX5_CMD_OP_MODIFY_TIS = 0x913, 277 MLX5_CMD_OP_DESTROY_TIS = 0x914, 278 MLX5_CMD_OP_QUERY_TIS = 0x915, 279 MLX5_CMD_OP_CREATE_RQT = 0x916, 280 MLX5_CMD_OP_MODIFY_RQT = 0x917, 281 MLX5_CMD_OP_DESTROY_RQT = 0x918, 282 MLX5_CMD_OP_QUERY_RQT = 0x919, 283 MLX5_CMD_OP_SET_FLOW_TABLE_ROOT = 0x92f, 284 MLX5_CMD_OP_CREATE_FLOW_TABLE = 0x930, 285 MLX5_CMD_OP_DESTROY_FLOW_TABLE = 0x931, 286 MLX5_CMD_OP_QUERY_FLOW_TABLE = 0x932, 287 MLX5_CMD_OP_CREATE_FLOW_GROUP = 0x933, 288 MLX5_CMD_OP_DESTROY_FLOW_GROUP = 0x934, 289 MLX5_CMD_OP_QUERY_FLOW_GROUP = 0x935, 290 MLX5_CMD_OP_SET_FLOW_TABLE_ENTRY = 0x936, 291 MLX5_CMD_OP_QUERY_FLOW_TABLE_ENTRY = 0x937, 292 MLX5_CMD_OP_DELETE_FLOW_TABLE_ENTRY = 0x938, 293 MLX5_CMD_OP_ALLOC_FLOW_COUNTER = 0x939, 294 MLX5_CMD_OP_DEALLOC_FLOW_COUNTER = 0x93a, 295 MLX5_CMD_OP_QUERY_FLOW_COUNTER = 0x93b, 296 MLX5_CMD_OP_MODIFY_FLOW_TABLE = 0x93c, 297 MLX5_CMD_OP_ALLOC_PACKET_REFORMAT_CONTEXT = 0x93d, 298 MLX5_CMD_OP_DEALLOC_PACKET_REFORMAT_CONTEXT = 0x93e, 299 MLX5_CMD_OP_QUERY_PACKET_REFORMAT_CONTEXT = 0x93f, 300 MLX5_CMD_OP_ALLOC_MODIFY_HEADER_CONTEXT = 0x940, 301 MLX5_CMD_OP_DEALLOC_MODIFY_HEADER_CONTEXT = 0x941, 302 MLX5_CMD_OP_QUERY_MODIFY_HEADER_CONTEXT = 0x942, 303 MLX5_CMD_OP_FPGA_CREATE_QP = 0x960, 304 MLX5_CMD_OP_FPGA_MODIFY_QP = 0x961, 305 MLX5_CMD_OP_FPGA_QUERY_QP = 0x962, 306 MLX5_CMD_OP_FPGA_DESTROY_QP = 0x963, 307 MLX5_CMD_OP_FPGA_QUERY_QP_COUNTERS = 0x964, 308 MLX5_CMD_OP_CREATE_GENERAL_OBJECT = 0xa00, 309 MLX5_CMD_OP_MODIFY_GENERAL_OBJECT = 0xa01, 310 MLX5_CMD_OP_QUERY_GENERAL_OBJECT = 0xa02, 311 MLX5_CMD_OP_DESTROY_GENERAL_OBJECT = 0xa03, 312 MLX5_CMD_OP_CREATE_UCTX = 0xa04, 313 MLX5_CMD_OP_DESTROY_UCTX = 0xa06, 314 MLX5_CMD_OP_CREATE_UMEM = 0xa08, 315 MLX5_CMD_OP_DESTROY_UMEM = 0xa0a, 316 MLX5_CMD_OP_SYNC_STEERING = 0xb00, 317 MLX5_CMD_OP_QUERY_VHCA_STATE = 0xb0d, 318 MLX5_CMD_OP_MODIFY_VHCA_STATE = 0xb0e, 319 MLX5_CMD_OP_SYNC_CRYPTO = 0xb12, 320 MLX5_CMD_OP_ALLOW_OTHER_VHCA_ACCESS = 0xb16, 321 MLX5_CMD_OP_GENERATE_WQE = 0xb17, 322 MLX5_CMD_OPCODE_QUERY_VUID = 0xb22, 323 MLX5_CMD_OP_MAX 324 }; 325 326 /* Valid range for general commands that don't work over an object */ 327 enum { 328 MLX5_CMD_OP_GENERAL_START = 0xb00, 329 MLX5_CMD_OP_GENERAL_END = 0xd00, 330 }; 331 332 enum { 333 MLX5_FT_NIC_RX_2_NIC_RX_RDMA = BIT(0), 334 MLX5_FT_NIC_TX_RDMA_2_NIC_TX = BIT(1), 335 }; 336 337 enum { 338 MLX5_CMD_OP_MOD_UPDATE_HEADER_MODIFY_ARGUMENT = 0x1, 339 }; 340 341 struct mlx5_ifc_flow_table_fields_supported_bits { 342 u8 outer_dmac[0x1]; 343 u8 outer_smac[0x1]; 344 u8 outer_ether_type[0x1]; 345 u8 outer_ip_version[0x1]; 346 u8 outer_first_prio[0x1]; 347 u8 outer_first_cfi[0x1]; 348 u8 outer_first_vid[0x1]; 349 u8 outer_ipv4_ttl[0x1]; 350 u8 outer_second_prio[0x1]; 351 u8 outer_second_cfi[0x1]; 352 u8 outer_second_vid[0x1]; 353 u8 reserved_at_b[0x1]; 354 u8 outer_sip[0x1]; 355 u8 outer_dip[0x1]; 356 u8 outer_frag[0x1]; 357 u8 outer_ip_protocol[0x1]; 358 u8 outer_ip_ecn[0x1]; 359 u8 outer_ip_dscp[0x1]; 360 u8 outer_udp_sport[0x1]; 361 u8 outer_udp_dport[0x1]; 362 u8 outer_tcp_sport[0x1]; 363 u8 outer_tcp_dport[0x1]; 364 u8 outer_tcp_flags[0x1]; 365 u8 outer_gre_protocol[0x1]; 366 u8 outer_gre_key[0x1]; 367 u8 outer_vxlan_vni[0x1]; 368 u8 outer_geneve_vni[0x1]; 369 u8 outer_geneve_oam[0x1]; 370 u8 outer_geneve_protocol_type[0x1]; 371 u8 outer_geneve_opt_len[0x1]; 372 u8 source_vhca_port[0x1]; 373 u8 source_eswitch_port[0x1]; 374 375 u8 inner_dmac[0x1]; 376 u8 inner_smac[0x1]; 377 u8 inner_ether_type[0x1]; 378 u8 inner_ip_version[0x1]; 379 u8 inner_first_prio[0x1]; 380 u8 inner_first_cfi[0x1]; 381 u8 inner_first_vid[0x1]; 382 u8 reserved_at_27[0x1]; 383 u8 inner_second_prio[0x1]; 384 u8 inner_second_cfi[0x1]; 385 u8 inner_second_vid[0x1]; 386 u8 reserved_at_2b[0x1]; 387 u8 inner_sip[0x1]; 388 u8 inner_dip[0x1]; 389 u8 inner_frag[0x1]; 390 u8 inner_ip_protocol[0x1]; 391 u8 inner_ip_ecn[0x1]; 392 u8 inner_ip_dscp[0x1]; 393 u8 inner_udp_sport[0x1]; 394 u8 inner_udp_dport[0x1]; 395 u8 inner_tcp_sport[0x1]; 396 u8 inner_tcp_dport[0x1]; 397 u8 inner_tcp_flags[0x1]; 398 u8 reserved_at_37[0x9]; 399 400 u8 geneve_tlv_option_0_data[0x1]; 401 u8 geneve_tlv_option_0_exist[0x1]; 402 u8 reserved_at_42[0x3]; 403 u8 outer_first_mpls_over_udp[0x4]; 404 u8 outer_first_mpls_over_gre[0x4]; 405 u8 inner_first_mpls[0x4]; 406 u8 outer_first_mpls[0x4]; 407 u8 reserved_at_55[0x2]; 408 u8 outer_esp_spi[0x1]; 409 u8 reserved_at_58[0x2]; 410 u8 bth_dst_qp[0x1]; 411 u8 reserved_at_5b[0x5]; 412 413 u8 reserved_at_60[0x18]; 414 u8 metadata_reg_c_7[0x1]; 415 u8 metadata_reg_c_6[0x1]; 416 u8 metadata_reg_c_5[0x1]; 417 u8 metadata_reg_c_4[0x1]; 418 u8 metadata_reg_c_3[0x1]; 419 u8 metadata_reg_c_2[0x1]; 420 u8 metadata_reg_c_1[0x1]; 421 u8 metadata_reg_c_0[0x1]; 422 }; 423 424 /* Table 2170 - Flow Table Fields Supported 2 Format */ 425 struct mlx5_ifc_flow_table_fields_supported_2_bits { 426 u8 inner_l4_type_ext[0x1]; 427 u8 outer_l4_type_ext[0x1]; 428 u8 inner_l4_type[0x1]; 429 u8 outer_l4_type[0x1]; 430 u8 reserved_at_4[0xa]; 431 u8 bth_opcode[0x1]; 432 u8 reserved_at_f[0x1]; 433 u8 tunnel_header_0_1[0x1]; 434 u8 reserved_at_11[0xf]; 435 436 u8 reserved_at_20[0xf]; 437 u8 ipsec_next_header[0x1]; 438 u8 reserved_at_30[0x10]; 439 440 u8 reserved_at_40[0x40]; 441 }; 442 443 struct mlx5_ifc_flow_table_prop_layout_bits { 444 u8 ft_support[0x1]; 445 u8 reserved_at_1[0x1]; 446 u8 flow_counter[0x1]; 447 u8 flow_modify_en[0x1]; 448 u8 modify_root[0x1]; 449 u8 identified_miss_table_mode[0x1]; 450 u8 flow_table_modify[0x1]; 451 u8 reformat[0x1]; 452 u8 decap[0x1]; 453 u8 reset_root_to_default[0x1]; 454 u8 pop_vlan[0x1]; 455 u8 push_vlan[0x1]; 456 u8 reserved_at_c[0x1]; 457 u8 pop_vlan_2[0x1]; 458 u8 push_vlan_2[0x1]; 459 u8 reformat_and_vlan_action[0x1]; 460 u8 reserved_at_10[0x1]; 461 u8 sw_owner[0x1]; 462 u8 reformat_l3_tunnel_to_l2[0x1]; 463 u8 reformat_l2_to_l3_tunnel[0x1]; 464 u8 reformat_and_modify_action[0x1]; 465 u8 ignore_flow_level[0x1]; 466 u8 reserved_at_16[0x1]; 467 u8 table_miss_action_domain[0x1]; 468 u8 termination_table[0x1]; 469 u8 reformat_and_fwd_to_table[0x1]; 470 u8 reserved_at_1a[0x2]; 471 u8 ipsec_encrypt[0x1]; 472 u8 ipsec_decrypt[0x1]; 473 u8 sw_owner_v2[0x1]; 474 u8 reserved_at_1f[0x1]; 475 476 u8 termination_table_raw_traffic[0x1]; 477 u8 reserved_at_21[0x1]; 478 u8 log_max_ft_size[0x6]; 479 u8 log_max_modify_header_context[0x8]; 480 u8 max_modify_header_actions[0x8]; 481 u8 max_ft_level[0x8]; 482 483 u8 reformat_add_esp_trasport[0x1]; 484 u8 reformat_l2_to_l3_esp_tunnel[0x1]; 485 u8 reformat_add_esp_transport_over_udp[0x1]; 486 u8 reformat_del_esp_trasport[0x1]; 487 u8 reformat_l3_esp_tunnel_to_l2[0x1]; 488 u8 reformat_del_esp_transport_over_udp[0x1]; 489 u8 execute_aso[0x1]; 490 u8 reserved_at_47[0x19]; 491 492 u8 reserved_at_60[0x2]; 493 u8 reformat_insert[0x1]; 494 u8 reformat_remove[0x1]; 495 u8 macsec_encrypt[0x1]; 496 u8 macsec_decrypt[0x1]; 497 u8 reserved_at_66[0x2]; 498 u8 reformat_add_macsec[0x1]; 499 u8 reformat_remove_macsec[0x1]; 500 u8 reparse[0x1]; 501 u8 reserved_at_6b[0x1]; 502 u8 cross_vhca_object[0x1]; 503 u8 reformat_l2_to_l3_audp_tunnel[0x1]; 504 u8 reformat_l3_audp_tunnel_to_l2[0x1]; 505 u8 ignore_flow_level_rtc_valid[0x1]; 506 u8 reserved_at_70[0x8]; 507 u8 log_max_ft_num[0x8]; 508 509 u8 reserved_at_80[0x10]; 510 u8 log_max_flow_counter[0x8]; 511 u8 log_max_destination[0x8]; 512 513 u8 reserved_at_a0[0x18]; 514 u8 log_max_flow[0x8]; 515 516 u8 reserved_at_c0[0x40]; 517 518 struct mlx5_ifc_flow_table_fields_supported_bits ft_field_support; 519 520 struct mlx5_ifc_flow_table_fields_supported_bits ft_field_bitmask_support; 521 }; 522 523 struct mlx5_ifc_odp_per_transport_service_cap_bits { 524 u8 send[0x1]; 525 u8 receive[0x1]; 526 u8 write[0x1]; 527 u8 read[0x1]; 528 u8 atomic[0x1]; 529 u8 srq_receive[0x1]; 530 u8 reserved_at_6[0x1a]; 531 }; 532 533 struct mlx5_ifc_ipv4_layout_bits { 534 u8 reserved_at_0[0x60]; 535 536 u8 ipv4[0x20]; 537 }; 538 539 struct mlx5_ifc_ipv6_layout_bits { 540 u8 ipv6[16][0x8]; 541 }; 542 543 struct mlx5_ifc_ipv6_simple_layout_bits { 544 u8 ipv6_127_96[0x20]; 545 u8 ipv6_95_64[0x20]; 546 u8 ipv6_63_32[0x20]; 547 u8 ipv6_31_0[0x20]; 548 }; 549 550 union mlx5_ifc_ipv6_layout_ipv4_layout_auto_bits { 551 struct mlx5_ifc_ipv6_simple_layout_bits ipv6_simple_layout; 552 struct mlx5_ifc_ipv6_layout_bits ipv6_layout; 553 struct mlx5_ifc_ipv4_layout_bits ipv4_layout; 554 u8 reserved_at_0[0x80]; 555 }; 556 557 enum { 558 MLX5_PACKET_L4_TYPE_NONE, 559 MLX5_PACKET_L4_TYPE_TCP, 560 MLX5_PACKET_L4_TYPE_UDP, 561 }; 562 563 enum { 564 MLX5_PACKET_L4_TYPE_EXT_NONE, 565 MLX5_PACKET_L4_TYPE_EXT_TCP, 566 MLX5_PACKET_L4_TYPE_EXT_UDP, 567 MLX5_PACKET_L4_TYPE_EXT_ICMP, 568 }; 569 570 struct mlx5_ifc_fte_match_set_lyr_2_4_bits { 571 u8 smac_47_16[0x20]; 572 573 u8 smac_15_0[0x10]; 574 u8 ethertype[0x10]; 575 576 u8 dmac_47_16[0x20]; 577 578 u8 dmac_15_0[0x10]; 579 u8 first_prio[0x3]; 580 u8 first_cfi[0x1]; 581 u8 first_vid[0xc]; 582 583 u8 ip_protocol[0x8]; 584 u8 ip_dscp[0x6]; 585 u8 ip_ecn[0x2]; 586 u8 cvlan_tag[0x1]; 587 u8 svlan_tag[0x1]; 588 u8 frag[0x1]; 589 u8 ip_version[0x4]; 590 u8 tcp_flags[0x9]; 591 592 u8 tcp_sport[0x10]; 593 u8 tcp_dport[0x10]; 594 595 u8 l4_type[0x2]; 596 u8 l4_type_ext[0x4]; 597 u8 reserved_at_c6[0xa]; 598 u8 ipv4_ihl[0x4]; 599 u8 reserved_at_d4[0x4]; 600 u8 ttl_hoplimit[0x8]; 601 602 u8 udp_sport[0x10]; 603 u8 udp_dport[0x10]; 604 605 union mlx5_ifc_ipv6_layout_ipv4_layout_auto_bits src_ipv4_src_ipv6; 606 607 union mlx5_ifc_ipv6_layout_ipv4_layout_auto_bits dst_ipv4_dst_ipv6; 608 }; 609 610 struct mlx5_ifc_nvgre_key_bits { 611 u8 hi[0x18]; 612 u8 lo[0x8]; 613 }; 614 615 union mlx5_ifc_gre_key_bits { 616 struct mlx5_ifc_nvgre_key_bits nvgre; 617 u8 key[0x20]; 618 }; 619 620 struct mlx5_ifc_fte_match_set_misc_bits { 621 u8 gre_c_present[0x1]; 622 u8 reserved_at_1[0x1]; 623 u8 gre_k_present[0x1]; 624 u8 gre_s_present[0x1]; 625 u8 source_vhca_port[0x4]; 626 u8 source_sqn[0x18]; 627 628 u8 source_eswitch_owner_vhca_id[0x10]; 629 u8 source_port[0x10]; 630 631 u8 outer_second_prio[0x3]; 632 u8 outer_second_cfi[0x1]; 633 u8 outer_second_vid[0xc]; 634 u8 inner_second_prio[0x3]; 635 u8 inner_second_cfi[0x1]; 636 u8 inner_second_vid[0xc]; 637 638 u8 outer_second_cvlan_tag[0x1]; 639 u8 inner_second_cvlan_tag[0x1]; 640 u8 outer_second_svlan_tag[0x1]; 641 u8 inner_second_svlan_tag[0x1]; 642 u8 reserved_at_64[0xc]; 643 u8 gre_protocol[0x10]; 644 645 union mlx5_ifc_gre_key_bits gre_key; 646 647 u8 vxlan_vni[0x18]; 648 u8 bth_opcode[0x8]; 649 650 u8 geneve_vni[0x18]; 651 u8 reserved_at_d8[0x6]; 652 u8 geneve_tlv_option_0_exist[0x1]; 653 u8 geneve_oam[0x1]; 654 655 u8 reserved_at_e0[0xc]; 656 u8 outer_ipv6_flow_label[0x14]; 657 658 u8 reserved_at_100[0xc]; 659 u8 inner_ipv6_flow_label[0x14]; 660 661 u8 reserved_at_120[0xa]; 662 u8 geneve_opt_len[0x6]; 663 u8 geneve_protocol_type[0x10]; 664 665 u8 reserved_at_140[0x8]; 666 u8 bth_dst_qp[0x18]; 667 u8 inner_esp_spi[0x20]; 668 u8 outer_esp_spi[0x20]; 669 u8 reserved_at_1a0[0x60]; 670 }; 671 672 struct mlx5_ifc_fte_match_mpls_bits { 673 u8 mpls_label[0x14]; 674 u8 mpls_exp[0x3]; 675 u8 mpls_s_bos[0x1]; 676 u8 mpls_ttl[0x8]; 677 }; 678 679 struct mlx5_ifc_fte_match_set_misc2_bits { 680 struct mlx5_ifc_fte_match_mpls_bits outer_first_mpls; 681 682 struct mlx5_ifc_fte_match_mpls_bits inner_first_mpls; 683 684 struct mlx5_ifc_fte_match_mpls_bits outer_first_mpls_over_gre; 685 686 struct mlx5_ifc_fte_match_mpls_bits outer_first_mpls_over_udp; 687 688 u8 metadata_reg_c_7[0x20]; 689 690 u8 metadata_reg_c_6[0x20]; 691 692 u8 metadata_reg_c_5[0x20]; 693 694 u8 metadata_reg_c_4[0x20]; 695 696 u8 metadata_reg_c_3[0x20]; 697 698 u8 metadata_reg_c_2[0x20]; 699 700 u8 metadata_reg_c_1[0x20]; 701 702 u8 metadata_reg_c_0[0x20]; 703 704 u8 metadata_reg_a[0x20]; 705 706 u8 reserved_at_1a0[0x8]; 707 u8 macsec_syndrome[0x8]; 708 u8 ipsec_syndrome[0x8]; 709 u8 ipsec_next_header[0x8]; 710 711 u8 reserved_at_1c0[0x40]; 712 }; 713 714 struct mlx5_ifc_fte_match_set_misc3_bits { 715 u8 inner_tcp_seq_num[0x20]; 716 717 u8 outer_tcp_seq_num[0x20]; 718 719 u8 inner_tcp_ack_num[0x20]; 720 721 u8 outer_tcp_ack_num[0x20]; 722 723 u8 reserved_at_80[0x8]; 724 u8 outer_vxlan_gpe_vni[0x18]; 725 726 u8 outer_vxlan_gpe_next_protocol[0x8]; 727 u8 outer_vxlan_gpe_flags[0x8]; 728 u8 reserved_at_b0[0x10]; 729 730 u8 icmp_header_data[0x20]; 731 732 u8 icmpv6_header_data[0x20]; 733 734 u8 icmp_type[0x8]; 735 u8 icmp_code[0x8]; 736 u8 icmpv6_type[0x8]; 737 u8 icmpv6_code[0x8]; 738 739 u8 geneve_tlv_option_0_data[0x20]; 740 741 u8 gtpu_teid[0x20]; 742 743 u8 gtpu_msg_type[0x8]; 744 u8 gtpu_msg_flags[0x8]; 745 u8 reserved_at_170[0x10]; 746 747 u8 gtpu_dw_2[0x20]; 748 749 u8 gtpu_first_ext_dw_0[0x20]; 750 751 u8 gtpu_dw_0[0x20]; 752 753 u8 reserved_at_1e0[0x20]; 754 }; 755 756 struct mlx5_ifc_fte_match_set_misc4_bits { 757 u8 prog_sample_field_value_0[0x20]; 758 759 u8 prog_sample_field_id_0[0x20]; 760 761 u8 prog_sample_field_value_1[0x20]; 762 763 u8 prog_sample_field_id_1[0x20]; 764 765 u8 prog_sample_field_value_2[0x20]; 766 767 u8 prog_sample_field_id_2[0x20]; 768 769 u8 prog_sample_field_value_3[0x20]; 770 771 u8 prog_sample_field_id_3[0x20]; 772 773 u8 reserved_at_100[0x100]; 774 }; 775 776 struct mlx5_ifc_fte_match_set_misc5_bits { 777 u8 macsec_tag_0[0x20]; 778 779 u8 macsec_tag_1[0x20]; 780 781 u8 macsec_tag_2[0x20]; 782 783 u8 macsec_tag_3[0x20]; 784 785 u8 tunnel_header_0[0x20]; 786 787 u8 tunnel_header_1[0x20]; 788 789 u8 tunnel_header_2[0x20]; 790 791 u8 tunnel_header_3[0x20]; 792 793 u8 reserved_at_100[0x100]; 794 }; 795 796 struct mlx5_ifc_cmd_pas_bits { 797 u8 pa_h[0x20]; 798 799 u8 pa_l[0x14]; 800 u8 reserved_at_34[0xc]; 801 }; 802 803 struct mlx5_ifc_uint64_bits { 804 u8 hi[0x20]; 805 806 u8 lo[0x20]; 807 }; 808 809 enum { 810 MLX5_ADS_STAT_RATE_NO_LIMIT = 0x0, 811 MLX5_ADS_STAT_RATE_2_5GBPS = 0x7, 812 MLX5_ADS_STAT_RATE_10GBPS = 0x8, 813 MLX5_ADS_STAT_RATE_30GBPS = 0x9, 814 MLX5_ADS_STAT_RATE_5GBPS = 0xa, 815 MLX5_ADS_STAT_RATE_20GBPS = 0xb, 816 MLX5_ADS_STAT_RATE_40GBPS = 0xc, 817 MLX5_ADS_STAT_RATE_60GBPS = 0xd, 818 MLX5_ADS_STAT_RATE_80GBPS = 0xe, 819 MLX5_ADS_STAT_RATE_120GBPS = 0xf, 820 }; 821 822 struct mlx5_ifc_ads_bits { 823 u8 fl[0x1]; 824 u8 free_ar[0x1]; 825 u8 reserved_at_2[0xe]; 826 u8 pkey_index[0x10]; 827 828 u8 plane_index[0x8]; 829 u8 grh[0x1]; 830 u8 mlid[0x7]; 831 u8 rlid[0x10]; 832 833 u8 ack_timeout[0x5]; 834 u8 reserved_at_45[0x3]; 835 u8 src_addr_index[0x8]; 836 u8 reserved_at_50[0x4]; 837 u8 stat_rate[0x4]; 838 u8 hop_limit[0x8]; 839 840 u8 reserved_at_60[0x4]; 841 u8 tclass[0x8]; 842 u8 flow_label[0x14]; 843 844 u8 rgid_rip[16][0x8]; 845 846 u8 reserved_at_100[0x4]; 847 u8 f_dscp[0x1]; 848 u8 f_ecn[0x1]; 849 u8 reserved_at_106[0x1]; 850 u8 f_eth_prio[0x1]; 851 u8 ecn[0x2]; 852 u8 dscp[0x6]; 853 u8 udp_sport[0x10]; 854 855 u8 dei_cfi[0x1]; 856 u8 eth_prio[0x3]; 857 u8 sl[0x4]; 858 u8 vhca_port_num[0x8]; 859 u8 rmac_47_32[0x10]; 860 861 u8 rmac_31_0[0x20]; 862 }; 863 864 struct mlx5_ifc_flow_table_nic_cap_bits { 865 u8 nic_rx_multi_path_tirs[0x1]; 866 u8 nic_rx_multi_path_tirs_fts[0x1]; 867 u8 allow_sniffer_and_nic_rx_shared_tir[0x1]; 868 u8 reserved_at_3[0x4]; 869 u8 sw_owner_reformat_supported[0x1]; 870 u8 reserved_at_8[0x18]; 871 872 u8 encap_general_header[0x1]; 873 u8 reserved_at_21[0xa]; 874 u8 log_max_packet_reformat_context[0x5]; 875 u8 reserved_at_30[0x6]; 876 u8 max_encap_header_size[0xa]; 877 u8 reserved_at_40[0x1c0]; 878 879 struct mlx5_ifc_flow_table_prop_layout_bits flow_table_properties_nic_receive; 880 881 struct mlx5_ifc_flow_table_prop_layout_bits flow_table_properties_nic_receive_rdma; 882 883 struct mlx5_ifc_flow_table_prop_layout_bits flow_table_properties_nic_receive_sniffer; 884 885 struct mlx5_ifc_flow_table_prop_layout_bits flow_table_properties_nic_transmit; 886 887 struct mlx5_ifc_flow_table_prop_layout_bits flow_table_properties_nic_transmit_rdma; 888 889 struct mlx5_ifc_flow_table_prop_layout_bits flow_table_properties_nic_transmit_sniffer; 890 891 u8 reserved_at_e00[0x600]; 892 893 struct mlx5_ifc_flow_table_fields_supported_2_bits ft_field_support_2_nic_receive; 894 895 u8 reserved_at_1480[0x80]; 896 897 struct mlx5_ifc_flow_table_fields_supported_2_bits ft_field_support_2_nic_receive_rdma; 898 899 u8 reserved_at_1580[0x280]; 900 901 struct mlx5_ifc_flow_table_fields_supported_2_bits ft_field_support_2_nic_transmit_rdma; 902 903 u8 reserved_at_1880[0x780]; 904 905 u8 sw_steering_nic_rx_action_drop_icm_address[0x40]; 906 907 u8 sw_steering_nic_tx_action_drop_icm_address[0x40]; 908 909 u8 sw_steering_nic_tx_action_allow_icm_address[0x40]; 910 911 u8 reserved_at_20c0[0x5f40]; 912 }; 913 914 struct mlx5_ifc_port_selection_cap_bits { 915 u8 reserved_at_0[0x10]; 916 u8 port_select_flow_table[0x1]; 917 u8 reserved_at_11[0x1]; 918 u8 port_select_flow_table_bypass[0x1]; 919 u8 reserved_at_13[0xd]; 920 921 u8 reserved_at_20[0x1e0]; 922 923 struct mlx5_ifc_flow_table_prop_layout_bits flow_table_properties_port_selection; 924 925 struct mlx5_ifc_flow_table_fields_supported_2_bits ft_field_support_2_port_selection; 926 927 u8 reserved_at_480[0x7b80]; 928 }; 929 930 enum { 931 MLX5_FDB_TO_VPORT_REG_C_0 = 0x01, 932 MLX5_FDB_TO_VPORT_REG_C_1 = 0x02, 933 MLX5_FDB_TO_VPORT_REG_C_2 = 0x04, 934 MLX5_FDB_TO_VPORT_REG_C_3 = 0x08, 935 MLX5_FDB_TO_VPORT_REG_C_4 = 0x10, 936 MLX5_FDB_TO_VPORT_REG_C_5 = 0x20, 937 MLX5_FDB_TO_VPORT_REG_C_6 = 0x40, 938 MLX5_FDB_TO_VPORT_REG_C_7 = 0x80, 939 }; 940 941 struct mlx5_ifc_flow_table_eswitch_cap_bits { 942 u8 fdb_to_vport_reg_c_id[0x8]; 943 u8 reserved_at_8[0x5]; 944 u8 fdb_uplink_hairpin[0x1]; 945 u8 fdb_multi_path_any_table_limit_regc[0x1]; 946 u8 reserved_at_f[0x1]; 947 u8 fdb_dynamic_tunnel[0x1]; 948 u8 reserved_at_11[0x1]; 949 u8 fdb_multi_path_any_table[0x1]; 950 u8 reserved_at_13[0x2]; 951 u8 fdb_modify_header_fwd_to_table[0x1]; 952 u8 fdb_ipv4_ttl_modify[0x1]; 953 u8 flow_source[0x1]; 954 u8 reserved_at_18[0x2]; 955 u8 multi_fdb_encap[0x1]; 956 u8 egress_acl_forward_to_vport[0x1]; 957 u8 fdb_multi_path_to_table[0x1]; 958 u8 reserved_at_1d[0x3]; 959 960 u8 reserved_at_20[0x1e0]; 961 962 struct mlx5_ifc_flow_table_prop_layout_bits flow_table_properties_nic_esw_fdb; 963 964 struct mlx5_ifc_flow_table_prop_layout_bits flow_table_properties_esw_acl_ingress; 965 966 struct mlx5_ifc_flow_table_prop_layout_bits flow_table_properties_esw_acl_egress; 967 968 u8 reserved_at_800[0xC00]; 969 970 struct mlx5_ifc_flow_table_fields_supported_2_bits ft_field_support_2_esw_fdb; 971 972 struct mlx5_ifc_flow_table_fields_supported_2_bits ft_field_bitmask_support_2_esw_fdb; 973 974 u8 reserved_at_1500[0x300]; 975 976 u8 sw_steering_fdb_action_drop_icm_address_rx[0x40]; 977 978 u8 sw_steering_fdb_action_drop_icm_address_tx[0x40]; 979 980 u8 sw_steering_uplink_icm_address_rx[0x40]; 981 982 u8 sw_steering_uplink_icm_address_tx[0x40]; 983 984 u8 reserved_at_1900[0x6700]; 985 }; 986 987 struct mlx5_ifc_wqe_based_flow_table_cap_bits { 988 u8 reserved_at_0[0x3]; 989 u8 log_max_num_ste[0x5]; 990 u8 reserved_at_8[0x3]; 991 u8 log_max_num_stc[0x5]; 992 u8 reserved_at_10[0x3]; 993 u8 log_max_num_rtc[0x5]; 994 u8 reserved_at_18[0x3]; 995 u8 log_max_num_header_modify_pattern[0x5]; 996 997 u8 rtc_hash_split_table[0x1]; 998 u8 rtc_linear_lookup_table[0x1]; 999 u8 reserved_at_22[0x1]; 1000 u8 stc_alloc_log_granularity[0x5]; 1001 u8 reserved_at_28[0x3]; 1002 u8 stc_alloc_log_max[0x5]; 1003 u8 reserved_at_30[0x3]; 1004 u8 ste_alloc_log_granularity[0x5]; 1005 u8 reserved_at_38[0x3]; 1006 u8 ste_alloc_log_max[0x5]; 1007 1008 u8 reserved_at_40[0xb]; 1009 u8 rtc_reparse_mode[0x5]; 1010 u8 reserved_at_50[0x3]; 1011 u8 rtc_index_mode[0x5]; 1012 u8 reserved_at_58[0x3]; 1013 u8 rtc_log_depth_max[0x5]; 1014 1015 u8 reserved_at_60[0x10]; 1016 u8 ste_format[0x10]; 1017 1018 u8 stc_action_type[0x80]; 1019 1020 u8 header_insert_type[0x10]; 1021 u8 header_remove_type[0x10]; 1022 1023 u8 trivial_match_definer[0x20]; 1024 1025 u8 reserved_at_140[0x1b]; 1026 u8 rtc_max_num_hash_definer_gen_wqe[0x5]; 1027 1028 u8 reserved_at_160[0x18]; 1029 u8 access_index_mode[0x8]; 1030 1031 u8 reserved_at_180[0x10]; 1032 u8 ste_format_gen_wqe[0x10]; 1033 1034 u8 linear_match_definer_reg_c3[0x20]; 1035 1036 u8 fdb_jump_to_tir_stc[0x1]; 1037 u8 reserved_at_1c1[0x1f]; 1038 }; 1039 1040 struct mlx5_ifc_esw_cap_bits { 1041 u8 reserved_at_0[0x1d]; 1042 u8 merged_eswitch[0x1]; 1043 u8 reserved_at_1e[0x2]; 1044 1045 u8 reserved_at_20[0x40]; 1046 1047 u8 esw_manager_vport_number_valid[0x1]; 1048 u8 reserved_at_61[0xf]; 1049 u8 esw_manager_vport_number[0x10]; 1050 1051 u8 reserved_at_80[0x780]; 1052 }; 1053 1054 enum { 1055 MLX5_COUNTER_SOURCE_ESWITCH = 0x0, 1056 MLX5_COUNTER_FLOW_ESWITCH = 0x1, 1057 }; 1058 1059 struct mlx5_ifc_e_switch_cap_bits { 1060 u8 vport_svlan_strip[0x1]; 1061 u8 vport_cvlan_strip[0x1]; 1062 u8 vport_svlan_insert[0x1]; 1063 u8 vport_cvlan_insert_if_not_exist[0x1]; 1064 u8 vport_cvlan_insert_overwrite[0x1]; 1065 u8 reserved_at_5[0x1]; 1066 u8 vport_cvlan_insert_always[0x1]; 1067 u8 esw_shared_ingress_acl[0x1]; 1068 u8 esw_uplink_ingress_acl[0x1]; 1069 u8 root_ft_on_other_esw[0x1]; 1070 u8 reserved_at_a[0xf]; 1071 u8 esw_functions_changed[0x1]; 1072 u8 reserved_at_1a[0x1]; 1073 u8 ecpf_vport_exists[0x1]; 1074 u8 counter_eswitch_affinity[0x1]; 1075 u8 merged_eswitch[0x1]; 1076 u8 nic_vport_node_guid_modify[0x1]; 1077 u8 nic_vport_port_guid_modify[0x1]; 1078 1079 u8 vxlan_encap_decap[0x1]; 1080 u8 nvgre_encap_decap[0x1]; 1081 u8 reserved_at_22[0x1]; 1082 u8 log_max_fdb_encap_uplink[0x5]; 1083 u8 reserved_at_21[0x3]; 1084 u8 log_max_packet_reformat_context[0x5]; 1085 u8 reserved_2b[0x6]; 1086 u8 max_encap_header_size[0xa]; 1087 1088 u8 reserved_at_40[0xb]; 1089 u8 log_max_esw_sf[0x5]; 1090 u8 esw_sf_base_id[0x10]; 1091 1092 u8 reserved_at_60[0x7a0]; 1093 1094 }; 1095 1096 struct mlx5_ifc_qos_cap_bits { 1097 u8 packet_pacing[0x1]; 1098 u8 esw_scheduling[0x1]; 1099 u8 esw_bw_share[0x1]; 1100 u8 esw_rate_limit[0x1]; 1101 u8 reserved_at_4[0x1]; 1102 u8 packet_pacing_burst_bound[0x1]; 1103 u8 packet_pacing_typical_size[0x1]; 1104 u8 reserved_at_7[0x1]; 1105 u8 nic_sq_scheduling[0x1]; 1106 u8 nic_bw_share[0x1]; 1107 u8 nic_rate_limit[0x1]; 1108 u8 packet_pacing_uid[0x1]; 1109 u8 log_esw_max_sched_depth[0x4]; 1110 u8 reserved_at_10[0x10]; 1111 1112 u8 reserved_at_20[0x9]; 1113 u8 esw_cross_esw_sched[0x1]; 1114 u8 reserved_at_2a[0x1]; 1115 u8 log_max_qos_nic_queue_group[0x5]; 1116 u8 reserved_at_30[0x10]; 1117 1118 u8 packet_pacing_max_rate[0x20]; 1119 1120 u8 packet_pacing_min_rate[0x20]; 1121 1122 u8 reserved_at_80[0xb]; 1123 u8 log_esw_max_rate_limit[0x5]; 1124 u8 packet_pacing_rate_table_size[0x10]; 1125 1126 u8 esw_element_type[0x10]; 1127 u8 esw_tsar_type[0x10]; 1128 1129 u8 reserved_at_c0[0x10]; 1130 u8 max_qos_para_vport[0x10]; 1131 1132 u8 max_tsar_bw_share[0x20]; 1133 1134 u8 nic_element_type[0x10]; 1135 u8 nic_tsar_type[0x10]; 1136 1137 u8 reserved_at_120[0x3]; 1138 u8 log_meter_aso_granularity[0x5]; 1139 u8 reserved_at_128[0x3]; 1140 u8 log_meter_aso_max_alloc[0x5]; 1141 u8 reserved_at_130[0x3]; 1142 u8 log_max_num_meter_aso[0x5]; 1143 u8 reserved_at_138[0x8]; 1144 1145 u8 reserved_at_140[0x6c0]; 1146 }; 1147 1148 struct mlx5_ifc_debug_cap_bits { 1149 u8 core_dump_general[0x1]; 1150 u8 core_dump_qp[0x1]; 1151 u8 reserved_at_2[0x7]; 1152 u8 resource_dump[0x1]; 1153 u8 reserved_at_a[0x16]; 1154 1155 u8 reserved_at_20[0x2]; 1156 u8 stall_detect[0x1]; 1157 u8 reserved_at_23[0x1d]; 1158 1159 u8 reserved_at_40[0x7c0]; 1160 }; 1161 1162 struct mlx5_ifc_per_protocol_networking_offload_caps_bits { 1163 u8 csum_cap[0x1]; 1164 u8 vlan_cap[0x1]; 1165 u8 lro_cap[0x1]; 1166 u8 lro_psh_flag[0x1]; 1167 u8 lro_time_stamp[0x1]; 1168 u8 reserved_at_5[0x2]; 1169 u8 wqe_vlan_insert[0x1]; 1170 u8 self_lb_en_modifiable[0x1]; 1171 u8 reserved_at_9[0x2]; 1172 u8 max_lso_cap[0x5]; 1173 u8 multi_pkt_send_wqe[0x2]; 1174 u8 wqe_inline_mode[0x2]; 1175 u8 rss_ind_tbl_cap[0x4]; 1176 u8 reg_umr_sq[0x1]; 1177 u8 scatter_fcs[0x1]; 1178 u8 enhanced_multi_pkt_send_wqe[0x1]; 1179 u8 tunnel_lso_const_out_ip_id[0x1]; 1180 u8 tunnel_lro_gre[0x1]; 1181 u8 tunnel_lro_vxlan[0x1]; 1182 u8 tunnel_stateless_gre[0x1]; 1183 u8 tunnel_stateless_vxlan[0x1]; 1184 1185 u8 swp[0x1]; 1186 u8 swp_csum[0x1]; 1187 u8 swp_lso[0x1]; 1188 u8 cqe_checksum_full[0x1]; 1189 u8 tunnel_stateless_geneve_tx[0x1]; 1190 u8 tunnel_stateless_mpls_over_udp[0x1]; 1191 u8 tunnel_stateless_mpls_over_gre[0x1]; 1192 u8 tunnel_stateless_vxlan_gpe[0x1]; 1193 u8 tunnel_stateless_ipv4_over_vxlan[0x1]; 1194 u8 tunnel_stateless_ip_over_ip[0x1]; 1195 u8 insert_trailer[0x1]; 1196 u8 reserved_at_2b[0x1]; 1197 u8 tunnel_stateless_ip_over_ip_rx[0x1]; 1198 u8 tunnel_stateless_ip_over_ip_tx[0x1]; 1199 u8 reserved_at_2e[0x2]; 1200 u8 max_vxlan_udp_ports[0x8]; 1201 u8 swp_csum_l4_partial[0x1]; 1202 u8 reserved_at_39[0x5]; 1203 u8 max_geneve_opt_len[0x1]; 1204 u8 tunnel_stateless_geneve_rx[0x1]; 1205 1206 u8 reserved_at_40[0x10]; 1207 u8 lro_min_mss_size[0x10]; 1208 1209 u8 reserved_at_60[0x120]; 1210 1211 u8 lro_timer_supported_periods[4][0x20]; 1212 1213 u8 reserved_at_200[0x600]; 1214 }; 1215 1216 enum { 1217 MLX5_TIMESTAMP_FORMAT_CAP_FREE_RUNNING = 0x0, 1218 MLX5_TIMESTAMP_FORMAT_CAP_REAL_TIME = 0x1, 1219 MLX5_TIMESTAMP_FORMAT_CAP_FREE_RUNNING_AND_REAL_TIME = 0x2, 1220 }; 1221 1222 struct mlx5_ifc_roce_cap_bits { 1223 u8 roce_apm[0x1]; 1224 u8 reserved_at_1[0x3]; 1225 u8 sw_r_roce_src_udp_port[0x1]; 1226 u8 fl_rc_qp_when_roce_disabled[0x1]; 1227 u8 fl_rc_qp_when_roce_enabled[0x1]; 1228 u8 roce_cc_general[0x1]; 1229 u8 qp_ooo_transmit_default[0x1]; 1230 u8 reserved_at_9[0x15]; 1231 u8 qp_ts_format[0x2]; 1232 1233 u8 reserved_at_20[0x60]; 1234 1235 u8 reserved_at_80[0xc]; 1236 u8 l3_type[0x4]; 1237 u8 reserved_at_90[0x8]; 1238 u8 roce_version[0x8]; 1239 1240 u8 reserved_at_a0[0x10]; 1241 u8 r_roce_dest_udp_port[0x10]; 1242 1243 u8 r_roce_max_src_udp_port[0x10]; 1244 u8 r_roce_min_src_udp_port[0x10]; 1245 1246 u8 reserved_at_e0[0x10]; 1247 u8 roce_address_table_size[0x10]; 1248 1249 u8 reserved_at_100[0x700]; 1250 }; 1251 1252 struct mlx5_ifc_sync_steering_in_bits { 1253 u8 opcode[0x10]; 1254 u8 uid[0x10]; 1255 1256 u8 reserved_at_20[0x10]; 1257 u8 op_mod[0x10]; 1258 1259 u8 reserved_at_40[0xc0]; 1260 }; 1261 1262 struct mlx5_ifc_sync_steering_out_bits { 1263 u8 status[0x8]; 1264 u8 reserved_at_8[0x18]; 1265 1266 u8 syndrome[0x20]; 1267 1268 u8 reserved_at_40[0x40]; 1269 }; 1270 1271 struct mlx5_ifc_sync_crypto_in_bits { 1272 u8 opcode[0x10]; 1273 u8 uid[0x10]; 1274 1275 u8 reserved_at_20[0x10]; 1276 u8 op_mod[0x10]; 1277 1278 u8 reserved_at_40[0x20]; 1279 1280 u8 reserved_at_60[0x10]; 1281 u8 crypto_type[0x10]; 1282 1283 u8 reserved_at_80[0x80]; 1284 }; 1285 1286 struct mlx5_ifc_sync_crypto_out_bits { 1287 u8 status[0x8]; 1288 u8 reserved_at_8[0x18]; 1289 1290 u8 syndrome[0x20]; 1291 1292 u8 reserved_at_40[0x40]; 1293 }; 1294 1295 struct mlx5_ifc_device_mem_cap_bits { 1296 u8 memic[0x1]; 1297 u8 reserved_at_1[0x1f]; 1298 1299 u8 reserved_at_20[0xb]; 1300 u8 log_min_memic_alloc_size[0x5]; 1301 u8 reserved_at_30[0x8]; 1302 u8 log_max_memic_addr_alignment[0x8]; 1303 1304 u8 memic_bar_start_addr[0x40]; 1305 1306 u8 memic_bar_size[0x20]; 1307 1308 u8 max_memic_size[0x20]; 1309 1310 u8 steering_sw_icm_start_address[0x40]; 1311 1312 u8 reserved_at_100[0x8]; 1313 u8 log_header_modify_sw_icm_size[0x8]; 1314 u8 reserved_at_110[0x2]; 1315 u8 log_sw_icm_alloc_granularity[0x6]; 1316 u8 log_steering_sw_icm_size[0x8]; 1317 1318 u8 log_indirect_encap_sw_icm_size[0x8]; 1319 u8 reserved_at_128[0x10]; 1320 u8 log_header_modify_pattern_sw_icm_size[0x8]; 1321 1322 u8 header_modify_sw_icm_start_address[0x40]; 1323 1324 u8 reserved_at_180[0x40]; 1325 1326 u8 header_modify_pattern_sw_icm_start_address[0x40]; 1327 1328 u8 memic_operations[0x20]; 1329 1330 u8 reserved_at_220[0x20]; 1331 1332 u8 indirect_encap_sw_icm_start_address[0x40]; 1333 1334 u8 reserved_at_280[0x580]; 1335 }; 1336 1337 struct mlx5_ifc_device_event_cap_bits { 1338 u8 user_affiliated_events[4][0x40]; 1339 1340 u8 user_unaffiliated_events[4][0x40]; 1341 }; 1342 1343 struct mlx5_ifc_virtio_emulation_cap_bits { 1344 u8 desc_tunnel_offload_type[0x1]; 1345 u8 eth_frame_offload_type[0x1]; 1346 u8 virtio_version_1_0[0x1]; 1347 u8 device_features_bits_mask[0xd]; 1348 u8 event_mode[0x8]; 1349 u8 virtio_queue_type[0x8]; 1350 1351 u8 max_tunnel_desc[0x10]; 1352 u8 reserved_at_30[0x3]; 1353 u8 log_doorbell_stride[0x5]; 1354 u8 reserved_at_38[0x3]; 1355 u8 log_doorbell_bar_size[0x5]; 1356 1357 u8 doorbell_bar_offset[0x40]; 1358 1359 u8 max_emulated_devices[0x8]; 1360 u8 max_num_virtio_queues[0x18]; 1361 1362 u8 reserved_at_a0[0x20]; 1363 1364 u8 reserved_at_c0[0x13]; 1365 u8 desc_group_mkey_supported[0x1]; 1366 u8 freeze_to_rdy_supported[0x1]; 1367 u8 reserved_at_d5[0xb]; 1368 1369 u8 reserved_at_e0[0x20]; 1370 1371 u8 umem_1_buffer_param_a[0x20]; 1372 1373 u8 umem_1_buffer_param_b[0x20]; 1374 1375 u8 umem_2_buffer_param_a[0x20]; 1376 1377 u8 umem_2_buffer_param_b[0x20]; 1378 1379 u8 umem_3_buffer_param_a[0x20]; 1380 1381 u8 umem_3_buffer_param_b[0x20]; 1382 1383 u8 reserved_at_1c0[0x640]; 1384 }; 1385 1386 enum { 1387 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_QP_1_BYTE = 0x0, 1388 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_QP_2_BYTES = 0x2, 1389 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_QP_4_BYTES = 0x4, 1390 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_QP_8_BYTES = 0x8, 1391 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_QP_16_BYTES = 0x10, 1392 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_QP_32_BYTES = 0x20, 1393 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_QP_64_BYTES = 0x40, 1394 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_QP_128_BYTES = 0x80, 1395 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_QP_256_BYTES = 0x100, 1396 }; 1397 1398 enum { 1399 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_DC_1_BYTE = 0x1, 1400 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_DC_2_BYTES = 0x2, 1401 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_DC_4_BYTES = 0x4, 1402 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_DC_8_BYTES = 0x8, 1403 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_DC_16_BYTES = 0x10, 1404 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_DC_32_BYTES = 0x20, 1405 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_DC_64_BYTES = 0x40, 1406 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_DC_128_BYTES = 0x80, 1407 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_DC_256_BYTES = 0x100, 1408 }; 1409 1410 struct mlx5_ifc_atomic_caps_bits { 1411 u8 reserved_at_0[0x40]; 1412 1413 u8 atomic_req_8B_endianness_mode[0x2]; 1414 u8 reserved_at_42[0x4]; 1415 u8 supported_atomic_req_8B_endianness_mode_1[0x1]; 1416 1417 u8 reserved_at_47[0x19]; 1418 1419 u8 reserved_at_60[0x20]; 1420 1421 u8 reserved_at_80[0x10]; 1422 u8 atomic_operations[0x10]; 1423 1424 u8 reserved_at_a0[0x10]; 1425 u8 atomic_size_qp[0x10]; 1426 1427 u8 reserved_at_c0[0x10]; 1428 u8 atomic_size_dc[0x10]; 1429 1430 u8 reserved_at_e0[0x720]; 1431 }; 1432 1433 struct mlx5_ifc_odp_scheme_cap_bits { 1434 u8 reserved_at_0[0x40]; 1435 1436 u8 sig[0x1]; 1437 u8 reserved_at_41[0x4]; 1438 u8 page_prefetch[0x1]; 1439 u8 reserved_at_46[0x1a]; 1440 1441 u8 reserved_at_60[0x20]; 1442 1443 struct mlx5_ifc_odp_per_transport_service_cap_bits rc_odp_caps; 1444 1445 struct mlx5_ifc_odp_per_transport_service_cap_bits uc_odp_caps; 1446 1447 struct mlx5_ifc_odp_per_transport_service_cap_bits ud_odp_caps; 1448 1449 struct mlx5_ifc_odp_per_transport_service_cap_bits xrc_odp_caps; 1450 1451 struct mlx5_ifc_odp_per_transport_service_cap_bits dc_odp_caps; 1452 1453 u8 reserved_at_120[0xe0]; 1454 }; 1455 1456 struct mlx5_ifc_odp_cap_bits { 1457 struct mlx5_ifc_odp_scheme_cap_bits transport_page_fault_scheme_cap; 1458 1459 struct mlx5_ifc_odp_scheme_cap_bits memory_page_fault_scheme_cap; 1460 1461 u8 reserved_at_400[0x200]; 1462 1463 u8 mem_page_fault[0x1]; 1464 u8 reserved_at_601[0x1f]; 1465 1466 u8 reserved_at_620[0x1e0]; 1467 }; 1468 1469 struct mlx5_ifc_tls_cap_bits { 1470 u8 tls_1_2_aes_gcm_128[0x1]; 1471 u8 tls_1_3_aes_gcm_128[0x1]; 1472 u8 tls_1_2_aes_gcm_256[0x1]; 1473 u8 tls_1_3_aes_gcm_256[0x1]; 1474 u8 reserved_at_4[0x1c]; 1475 1476 u8 reserved_at_20[0x7e0]; 1477 }; 1478 1479 struct mlx5_ifc_ipsec_cap_bits { 1480 u8 ipsec_full_offload[0x1]; 1481 u8 ipsec_crypto_offload[0x1]; 1482 u8 ipsec_esn[0x1]; 1483 u8 ipsec_crypto_esp_aes_gcm_256_encrypt[0x1]; 1484 u8 ipsec_crypto_esp_aes_gcm_128_encrypt[0x1]; 1485 u8 ipsec_crypto_esp_aes_gcm_256_decrypt[0x1]; 1486 u8 ipsec_crypto_esp_aes_gcm_128_decrypt[0x1]; 1487 u8 reserved_at_7[0x4]; 1488 u8 log_max_ipsec_offload[0x5]; 1489 u8 reserved_at_10[0x10]; 1490 1491 u8 min_log_ipsec_full_replay_window[0x8]; 1492 u8 max_log_ipsec_full_replay_window[0x8]; 1493 u8 reserved_at_30[0x7d0]; 1494 }; 1495 1496 struct mlx5_ifc_macsec_cap_bits { 1497 u8 macsec_epn[0x1]; 1498 u8 reserved_at_1[0x2]; 1499 u8 macsec_crypto_esp_aes_gcm_256_encrypt[0x1]; 1500 u8 macsec_crypto_esp_aes_gcm_128_encrypt[0x1]; 1501 u8 macsec_crypto_esp_aes_gcm_256_decrypt[0x1]; 1502 u8 macsec_crypto_esp_aes_gcm_128_decrypt[0x1]; 1503 u8 reserved_at_7[0x4]; 1504 u8 log_max_macsec_offload[0x5]; 1505 u8 reserved_at_10[0x10]; 1506 1507 u8 min_log_macsec_full_replay_window[0x8]; 1508 u8 max_log_macsec_full_replay_window[0x8]; 1509 u8 reserved_at_30[0x10]; 1510 1511 u8 reserved_at_40[0x7c0]; 1512 }; 1513 1514 enum { 1515 MLX5_WQ_TYPE_LINKED_LIST = 0x0, 1516 MLX5_WQ_TYPE_CYCLIC = 0x1, 1517 MLX5_WQ_TYPE_LINKED_LIST_STRIDING_RQ = 0x2, 1518 MLX5_WQ_TYPE_CYCLIC_STRIDING_RQ = 0x3, 1519 }; 1520 1521 enum { 1522 MLX5_WQ_END_PAD_MODE_NONE = 0x0, 1523 MLX5_WQ_END_PAD_MODE_ALIGN = 0x1, 1524 }; 1525 1526 enum { 1527 MLX5_CMD_HCA_CAP_GID_TABLE_SIZE_8_GID_ENTRIES = 0x0, 1528 MLX5_CMD_HCA_CAP_GID_TABLE_SIZE_16_GID_ENTRIES = 0x1, 1529 MLX5_CMD_HCA_CAP_GID_TABLE_SIZE_32_GID_ENTRIES = 0x2, 1530 MLX5_CMD_HCA_CAP_GID_TABLE_SIZE_64_GID_ENTRIES = 0x3, 1531 MLX5_CMD_HCA_CAP_GID_TABLE_SIZE_128_GID_ENTRIES = 0x4, 1532 }; 1533 1534 enum { 1535 MLX5_CMD_HCA_CAP_PKEY_TABLE_SIZE_128_ENTRIES = 0x0, 1536 MLX5_CMD_HCA_CAP_PKEY_TABLE_SIZE_256_ENTRIES = 0x1, 1537 MLX5_CMD_HCA_CAP_PKEY_TABLE_SIZE_512_ENTRIES = 0x2, 1538 MLX5_CMD_HCA_CAP_PKEY_TABLE_SIZE_1K_ENTRIES = 0x3, 1539 MLX5_CMD_HCA_CAP_PKEY_TABLE_SIZE_2K_ENTRIES = 0x4, 1540 MLX5_CMD_HCA_CAP_PKEY_TABLE_SIZE_4K_ENTRIES = 0x5, 1541 }; 1542 1543 enum { 1544 MLX5_CMD_HCA_CAP_PORT_TYPE_IB = 0x0, 1545 MLX5_CMD_HCA_CAP_PORT_TYPE_ETHERNET = 0x1, 1546 }; 1547 1548 enum { 1549 MLX5_CMD_HCA_CAP_CMDIF_CHECKSUM_DISABLED = 0x0, 1550 MLX5_CMD_HCA_CAP_CMDIF_CHECKSUM_INITIAL_STATE = 0x1, 1551 MLX5_CMD_HCA_CAP_CMDIF_CHECKSUM_ENABLED = 0x3, 1552 }; 1553 1554 enum { 1555 MLX5_CAP_PORT_TYPE_IB = 0x0, 1556 MLX5_CAP_PORT_TYPE_ETH = 0x1, 1557 }; 1558 1559 enum { 1560 MLX5_CAP_UMR_FENCE_STRONG = 0x0, 1561 MLX5_CAP_UMR_FENCE_SMALL = 0x1, 1562 MLX5_CAP_UMR_FENCE_NONE = 0x2, 1563 }; 1564 1565 enum { 1566 MLX5_FLEX_IPV4_OVER_VXLAN_ENABLED = 1 << 0, 1567 MLX5_FLEX_IPV6_OVER_VXLAN_ENABLED = 1 << 1, 1568 MLX5_FLEX_IPV6_OVER_IP_ENABLED = 1 << 2, 1569 MLX5_FLEX_PARSER_GENEVE_ENABLED = 1 << 3, 1570 MLX5_FLEX_PARSER_MPLS_OVER_GRE_ENABLED = 1 << 4, 1571 MLX5_FLEX_PARSER_MPLS_OVER_UDP_ENABLED = 1 << 5, 1572 MLX5_FLEX_P_BIT_VXLAN_GPE_ENABLED = 1 << 6, 1573 MLX5_FLEX_PARSER_VXLAN_GPE_ENABLED = 1 << 7, 1574 MLX5_FLEX_PARSER_ICMP_V4_ENABLED = 1 << 8, 1575 MLX5_FLEX_PARSER_ICMP_V6_ENABLED = 1 << 9, 1576 MLX5_FLEX_PARSER_GENEVE_TLV_OPTION_0_ENABLED = 1 << 10, 1577 MLX5_FLEX_PARSER_GTPU_ENABLED = 1 << 11, 1578 MLX5_FLEX_PARSER_GTPU_DW_2_ENABLED = 1 << 16, 1579 MLX5_FLEX_PARSER_GTPU_FIRST_EXT_DW_0_ENABLED = 1 << 17, 1580 MLX5_FLEX_PARSER_GTPU_DW_0_ENABLED = 1 << 18, 1581 MLX5_FLEX_PARSER_GTPU_TEID_ENABLED = 1 << 19, 1582 }; 1583 1584 enum { 1585 MLX5_UCTX_CAP_RAW_TX = 1UL << 0, 1586 MLX5_UCTX_CAP_INTERNAL_DEV_RES = 1UL << 1, 1587 MLX5_UCTX_CAP_RDMA_CTRL = 1UL << 3, 1588 MLX5_UCTX_CAP_RDMA_CTRL_OTHER_VHCA = 1UL << 4, 1589 }; 1590 1591 #define MLX5_FC_BULK_SIZE_FACTOR 128 1592 1593 enum mlx5_fc_bulk_alloc_bitmask { 1594 MLX5_FC_BULK_128 = (1 << 0), 1595 MLX5_FC_BULK_256 = (1 << 1), 1596 MLX5_FC_BULK_512 = (1 << 2), 1597 MLX5_FC_BULK_1024 = (1 << 3), 1598 MLX5_FC_BULK_2048 = (1 << 4), 1599 MLX5_FC_BULK_4096 = (1 << 5), 1600 MLX5_FC_BULK_8192 = (1 << 6), 1601 MLX5_FC_BULK_16384 = (1 << 7), 1602 }; 1603 1604 #define MLX5_FC_BULK_NUM_FCS(fc_enum) (MLX5_FC_BULK_SIZE_FACTOR * (fc_enum)) 1605 1606 #define MLX5_FT_MAX_MULTIPATH_LEVEL 63 1607 1608 enum { 1609 MLX5_STEERING_FORMAT_CONNECTX_5 = 0, 1610 MLX5_STEERING_FORMAT_CONNECTX_6DX = 1, 1611 MLX5_STEERING_FORMAT_CONNECTX_7 = 2, 1612 MLX5_STEERING_FORMAT_CONNECTX_8 = 3, 1613 }; 1614 1615 struct mlx5_ifc_cmd_hca_cap_bits { 1616 u8 reserved_at_0[0x6]; 1617 u8 page_request_disable[0x1]; 1618 u8 abs_native_port_num[0x1]; 1619 u8 reserved_at_8[0x8]; 1620 u8 shared_object_to_user_object_allowed[0x1]; 1621 u8 reserved_at_13[0xe]; 1622 u8 vhca_resource_manager[0x1]; 1623 1624 u8 hca_cap_2[0x1]; 1625 u8 create_lag_when_not_master_up[0x1]; 1626 u8 dtor[0x1]; 1627 u8 event_on_vhca_state_teardown_request[0x1]; 1628 u8 event_on_vhca_state_in_use[0x1]; 1629 u8 event_on_vhca_state_active[0x1]; 1630 u8 event_on_vhca_state_allocated[0x1]; 1631 u8 event_on_vhca_state_invalid[0x1]; 1632 u8 reserved_at_28[0x8]; 1633 u8 vhca_id[0x10]; 1634 1635 u8 reserved_at_40[0x40]; 1636 1637 u8 log_max_srq_sz[0x8]; 1638 u8 log_max_qp_sz[0x8]; 1639 u8 event_cap[0x1]; 1640 u8 reserved_at_91[0x2]; 1641 u8 isolate_vl_tc_new[0x1]; 1642 u8 reserved_at_94[0x4]; 1643 u8 prio_tag_required[0x1]; 1644 u8 reserved_at_99[0x2]; 1645 u8 log_max_qp[0x5]; 1646 1647 u8 reserved_at_a0[0x3]; 1648 u8 ece_support[0x1]; 1649 u8 reserved_at_a4[0x5]; 1650 u8 reg_c_preserve[0x1]; 1651 u8 reserved_at_aa[0x1]; 1652 u8 log_max_srq[0x5]; 1653 u8 reserved_at_b0[0x1]; 1654 u8 uplink_follow[0x1]; 1655 u8 ts_cqe_to_dest_cqn[0x1]; 1656 u8 reserved_at_b3[0x6]; 1657 u8 go_back_n[0x1]; 1658 u8 reserved_at_ba[0x6]; 1659 1660 u8 max_sgl_for_optimized_performance[0x8]; 1661 u8 log_max_cq_sz[0x8]; 1662 u8 relaxed_ordering_write_umr[0x1]; 1663 u8 relaxed_ordering_read_umr[0x1]; 1664 u8 reserved_at_d2[0x7]; 1665 u8 virtio_net_device_emualtion_manager[0x1]; 1666 u8 virtio_blk_device_emualtion_manager[0x1]; 1667 u8 log_max_cq[0x5]; 1668 1669 u8 log_max_eq_sz[0x8]; 1670 u8 relaxed_ordering_write[0x1]; 1671 u8 relaxed_ordering_read_pci_enabled[0x1]; 1672 u8 log_max_mkey[0x6]; 1673 u8 reserved_at_f0[0x6]; 1674 u8 terminate_scatter_list_mkey[0x1]; 1675 u8 repeated_mkey[0x1]; 1676 u8 dump_fill_mkey[0x1]; 1677 u8 reserved_at_f9[0x2]; 1678 u8 fast_teardown[0x1]; 1679 u8 log_max_eq[0x4]; 1680 1681 u8 max_indirection[0x8]; 1682 u8 fixed_buffer_size[0x1]; 1683 u8 log_max_mrw_sz[0x7]; 1684 u8 force_teardown[0x1]; 1685 u8 reserved_at_111[0x1]; 1686 u8 log_max_bsf_list_size[0x6]; 1687 u8 umr_extended_translation_offset[0x1]; 1688 u8 null_mkey[0x1]; 1689 u8 log_max_klm_list_size[0x6]; 1690 1691 u8 reserved_at_120[0x2]; 1692 u8 qpc_extension[0x1]; 1693 u8 reserved_at_123[0x7]; 1694 u8 log_max_ra_req_dc[0x6]; 1695 u8 reserved_at_130[0x2]; 1696 u8 eth_wqe_too_small[0x1]; 1697 u8 reserved_at_133[0x6]; 1698 u8 vnic_env_cq_overrun[0x1]; 1699 u8 log_max_ra_res_dc[0x6]; 1700 1701 u8 reserved_at_140[0x5]; 1702 u8 release_all_pages[0x1]; 1703 u8 must_not_use[0x1]; 1704 u8 reserved_at_147[0x2]; 1705 u8 roce_accl[0x1]; 1706 u8 log_max_ra_req_qp[0x6]; 1707 u8 reserved_at_150[0xa]; 1708 u8 log_max_ra_res_qp[0x6]; 1709 1710 u8 end_pad[0x1]; 1711 u8 cc_query_allowed[0x1]; 1712 u8 cc_modify_allowed[0x1]; 1713 u8 start_pad[0x1]; 1714 u8 cache_line_128byte[0x1]; 1715 u8 reserved_at_165[0x4]; 1716 u8 rts2rts_qp_counters_set_id[0x1]; 1717 u8 reserved_at_16a[0x2]; 1718 u8 vnic_env_int_rq_oob[0x1]; 1719 u8 sbcam_reg[0x1]; 1720 u8 reserved_at_16e[0x1]; 1721 u8 qcam_reg[0x1]; 1722 u8 gid_table_size[0x10]; 1723 1724 u8 out_of_seq_cnt[0x1]; 1725 u8 vport_counters[0x1]; 1726 u8 retransmission_q_counters[0x1]; 1727 u8 debug[0x1]; 1728 u8 modify_rq_counter_set_id[0x1]; 1729 u8 rq_delay_drop[0x1]; 1730 u8 max_qp_cnt[0xa]; 1731 u8 pkey_table_size[0x10]; 1732 1733 u8 vport_group_manager[0x1]; 1734 u8 vhca_group_manager[0x1]; 1735 u8 ib_virt[0x1]; 1736 u8 eth_virt[0x1]; 1737 u8 vnic_env_queue_counters[0x1]; 1738 u8 ets[0x1]; 1739 u8 nic_flow_table[0x1]; 1740 u8 eswitch_manager[0x1]; 1741 u8 device_memory[0x1]; 1742 u8 mcam_reg[0x1]; 1743 u8 pcam_reg[0x1]; 1744 u8 local_ca_ack_delay[0x5]; 1745 u8 port_module_event[0x1]; 1746 u8 enhanced_error_q_counters[0x1]; 1747 u8 ports_check[0x1]; 1748 u8 reserved_at_1b3[0x1]; 1749 u8 disable_link_up[0x1]; 1750 u8 beacon_led[0x1]; 1751 u8 port_type[0x2]; 1752 u8 num_ports[0x8]; 1753 1754 u8 reserved_at_1c0[0x1]; 1755 u8 pps[0x1]; 1756 u8 pps_modify[0x1]; 1757 u8 log_max_msg[0x5]; 1758 u8 reserved_at_1c8[0x4]; 1759 u8 max_tc[0x4]; 1760 u8 temp_warn_event[0x1]; 1761 u8 dcbx[0x1]; 1762 u8 general_notification_event[0x1]; 1763 u8 reserved_at_1d3[0x2]; 1764 u8 fpga[0x1]; 1765 u8 rol_s[0x1]; 1766 u8 rol_g[0x1]; 1767 u8 reserved_at_1d8[0x1]; 1768 u8 wol_s[0x1]; 1769 u8 wol_g[0x1]; 1770 u8 wol_a[0x1]; 1771 u8 wol_b[0x1]; 1772 u8 wol_m[0x1]; 1773 u8 wol_u[0x1]; 1774 u8 wol_p[0x1]; 1775 1776 u8 stat_rate_support[0x10]; 1777 u8 reserved_at_1f0[0x1]; 1778 u8 pci_sync_for_fw_update_event[0x1]; 1779 u8 reserved_at_1f2[0x6]; 1780 u8 init2_lag_tx_port_affinity[0x1]; 1781 u8 reserved_at_1fa[0x2]; 1782 u8 wqe_based_flow_table_update_cap[0x1]; 1783 u8 cqe_version[0x4]; 1784 1785 u8 compact_address_vector[0x1]; 1786 u8 striding_rq[0x1]; 1787 u8 reserved_at_202[0x1]; 1788 u8 ipoib_enhanced_offloads[0x1]; 1789 u8 ipoib_basic_offloads[0x1]; 1790 u8 reserved_at_205[0x1]; 1791 u8 repeated_block_disabled[0x1]; 1792 u8 umr_modify_entity_size_disabled[0x1]; 1793 u8 umr_modify_atomic_disabled[0x1]; 1794 u8 umr_indirect_mkey_disabled[0x1]; 1795 u8 umr_fence[0x2]; 1796 u8 dc_req_scat_data_cqe[0x1]; 1797 u8 reserved_at_20d[0x2]; 1798 u8 drain_sigerr[0x1]; 1799 u8 cmdif_checksum[0x2]; 1800 u8 sigerr_cqe[0x1]; 1801 u8 reserved_at_213[0x1]; 1802 u8 wq_signature[0x1]; 1803 u8 sctr_data_cqe[0x1]; 1804 u8 reserved_at_216[0x1]; 1805 u8 sho[0x1]; 1806 u8 tph[0x1]; 1807 u8 rf[0x1]; 1808 u8 dct[0x1]; 1809 u8 qos[0x1]; 1810 u8 eth_net_offloads[0x1]; 1811 u8 roce[0x1]; 1812 u8 atomic[0x1]; 1813 u8 reserved_at_21f[0x1]; 1814 1815 u8 cq_oi[0x1]; 1816 u8 cq_resize[0x1]; 1817 u8 cq_moderation[0x1]; 1818 u8 cq_period_mode_modify[0x1]; 1819 u8 reserved_at_224[0x2]; 1820 u8 cq_eq_remap[0x1]; 1821 u8 pg[0x1]; 1822 u8 block_lb_mc[0x1]; 1823 u8 reserved_at_229[0x1]; 1824 u8 scqe_break_moderation[0x1]; 1825 u8 cq_period_start_from_cqe[0x1]; 1826 u8 cd[0x1]; 1827 u8 reserved_at_22d[0x1]; 1828 u8 apm[0x1]; 1829 u8 vector_calc[0x1]; 1830 u8 umr_ptr_rlky[0x1]; 1831 u8 imaicl[0x1]; 1832 u8 qp_packet_based[0x1]; 1833 u8 reserved_at_233[0x3]; 1834 u8 qkv[0x1]; 1835 u8 pkv[0x1]; 1836 u8 set_deth_sqpn[0x1]; 1837 u8 reserved_at_239[0x3]; 1838 u8 xrc[0x1]; 1839 u8 ud[0x1]; 1840 u8 uc[0x1]; 1841 u8 rc[0x1]; 1842 1843 u8 uar_4k[0x1]; 1844 u8 reserved_at_241[0x7]; 1845 u8 fl_rc_qp_when_roce_disabled[0x1]; 1846 u8 regexp_params[0x1]; 1847 u8 uar_sz[0x6]; 1848 u8 port_selection_cap[0x1]; 1849 u8 nic_cap_reg[0x1]; 1850 u8 umem_uid_0[0x1]; 1851 u8 reserved_at_253[0x5]; 1852 u8 log_pg_sz[0x8]; 1853 1854 u8 bf[0x1]; 1855 u8 driver_version[0x1]; 1856 u8 pad_tx_eth_packet[0x1]; 1857 u8 reserved_at_263[0x3]; 1858 u8 mkey_by_name[0x1]; 1859 u8 reserved_at_267[0x4]; 1860 1861 u8 log_bf_reg_size[0x5]; 1862 1863 u8 disciplined_fr_counter[0x1]; 1864 u8 reserved_at_271[0x2]; 1865 u8 qp_error_syndrome[0x1]; 1866 u8 reserved_at_274[0x2]; 1867 u8 lag_dct[0x2]; 1868 u8 lag_tx_port_affinity[0x1]; 1869 u8 lag_native_fdb_selection[0x1]; 1870 u8 reserved_at_27a[0x1]; 1871 u8 lag_master[0x1]; 1872 u8 num_lag_ports[0x4]; 1873 1874 u8 reserved_at_280[0x10]; 1875 u8 max_wqe_sz_sq[0x10]; 1876 1877 u8 reserved_at_2a0[0x7]; 1878 u8 mkey_pcie_tph[0x1]; 1879 u8 reserved_at_2a8[0x3]; 1880 u8 shampo[0x1]; 1881 u8 reserved_at_2ac[0x4]; 1882 u8 max_wqe_sz_rq[0x10]; 1883 1884 u8 max_flow_counter_31_16[0x10]; 1885 u8 max_wqe_sz_sq_dc[0x10]; 1886 1887 u8 reserved_at_2e0[0x7]; 1888 u8 max_qp_mcg[0x19]; 1889 1890 u8 reserved_at_300[0x10]; 1891 u8 flow_counter_bulk_alloc[0x8]; 1892 u8 log_max_mcg[0x8]; 1893 1894 u8 reserved_at_320[0x3]; 1895 u8 log_max_transport_domain[0x5]; 1896 u8 reserved_at_328[0x2]; 1897 u8 relaxed_ordering_read[0x1]; 1898 u8 log_max_pd[0x5]; 1899 u8 dp_ordering_ooo_all_ud[0x1]; 1900 u8 dp_ordering_ooo_all_uc[0x1]; 1901 u8 dp_ordering_ooo_all_xrc[0x1]; 1902 u8 dp_ordering_ooo_all_dc[0x1]; 1903 u8 dp_ordering_ooo_all_rc[0x1]; 1904 u8 pcie_reset_using_hotreset_method[0x1]; 1905 u8 pci_sync_for_fw_update_with_driver_unload[0x1]; 1906 u8 vnic_env_cnt_steering_fail[0x1]; 1907 u8 vport_counter_local_loopback[0x1]; 1908 u8 q_counter_aggregation[0x1]; 1909 u8 q_counter_other_vport[0x1]; 1910 u8 log_max_xrcd[0x5]; 1911 1912 u8 nic_receive_steering_discard[0x1]; 1913 u8 receive_discard_vport_down[0x1]; 1914 u8 transmit_discard_vport_down[0x1]; 1915 u8 eq_overrun_count[0x1]; 1916 u8 reserved_at_344[0x1]; 1917 u8 invalid_command_count[0x1]; 1918 u8 quota_exceeded_count[0x1]; 1919 u8 reserved_at_347[0x1]; 1920 u8 log_max_flow_counter_bulk[0x8]; 1921 u8 max_flow_counter_15_0[0x10]; 1922 1923 1924 u8 reserved_at_360[0x3]; 1925 u8 log_max_rq[0x5]; 1926 u8 reserved_at_368[0x3]; 1927 u8 log_max_sq[0x5]; 1928 u8 reserved_at_370[0x3]; 1929 u8 log_max_tir[0x5]; 1930 u8 reserved_at_378[0x3]; 1931 u8 log_max_tis[0x5]; 1932 1933 u8 basic_cyclic_rcv_wqe[0x1]; 1934 u8 reserved_at_381[0x2]; 1935 u8 log_max_rmp[0x5]; 1936 u8 reserved_at_388[0x3]; 1937 u8 log_max_rqt[0x5]; 1938 u8 reserved_at_390[0x3]; 1939 u8 log_max_rqt_size[0x5]; 1940 u8 reserved_at_398[0x3]; 1941 u8 log_max_tis_per_sq[0x5]; 1942 1943 u8 ext_stride_num_range[0x1]; 1944 u8 roce_rw_supported[0x1]; 1945 u8 log_max_current_uc_list_wr_supported[0x1]; 1946 u8 log_max_stride_sz_rq[0x5]; 1947 u8 reserved_at_3a8[0x3]; 1948 u8 log_min_stride_sz_rq[0x5]; 1949 u8 reserved_at_3b0[0x3]; 1950 u8 log_max_stride_sz_sq[0x5]; 1951 u8 reserved_at_3b8[0x3]; 1952 u8 log_min_stride_sz_sq[0x5]; 1953 1954 u8 hairpin[0x1]; 1955 u8 reserved_at_3c1[0x2]; 1956 u8 log_max_hairpin_queues[0x5]; 1957 u8 reserved_at_3c8[0x3]; 1958 u8 log_max_hairpin_wq_data_sz[0x5]; 1959 u8 reserved_at_3d0[0x3]; 1960 u8 log_max_hairpin_num_packets[0x5]; 1961 u8 reserved_at_3d8[0x3]; 1962 u8 log_max_wq_sz[0x5]; 1963 1964 u8 nic_vport_change_event[0x1]; 1965 u8 disable_local_lb_uc[0x1]; 1966 u8 disable_local_lb_mc[0x1]; 1967 u8 log_min_hairpin_wq_data_sz[0x5]; 1968 u8 reserved_at_3e8[0x1]; 1969 u8 silent_mode[0x1]; 1970 u8 vhca_state[0x1]; 1971 u8 log_max_vlan_list[0x5]; 1972 u8 reserved_at_3f0[0x3]; 1973 u8 log_max_current_mc_list[0x5]; 1974 u8 reserved_at_3f8[0x3]; 1975 u8 log_max_current_uc_list[0x5]; 1976 1977 u8 general_obj_types[0x40]; 1978 1979 u8 sq_ts_format[0x2]; 1980 u8 rq_ts_format[0x2]; 1981 u8 steering_format_version[0x4]; 1982 u8 create_qp_start_hint[0x18]; 1983 1984 u8 reserved_at_460[0x1]; 1985 u8 ats[0x1]; 1986 u8 cross_vhca_rqt[0x1]; 1987 u8 log_max_uctx[0x5]; 1988 u8 reserved_at_468[0x1]; 1989 u8 crypto[0x1]; 1990 u8 ipsec_offload[0x1]; 1991 u8 log_max_umem[0x5]; 1992 u8 max_num_eqs[0x10]; 1993 1994 u8 reserved_at_480[0x1]; 1995 u8 tls_tx[0x1]; 1996 u8 tls_rx[0x1]; 1997 u8 log_max_l2_table[0x5]; 1998 u8 reserved_at_488[0x8]; 1999 u8 log_uar_page_sz[0x10]; 2000 2001 u8 reserved_at_4a0[0x20]; 2002 u8 device_frequency_mhz[0x20]; 2003 u8 device_frequency_khz[0x20]; 2004 2005 u8 reserved_at_500[0x20]; 2006 u8 num_of_uars_per_page[0x20]; 2007 2008 u8 flex_parser_protocols[0x20]; 2009 2010 u8 max_geneve_tlv_options[0x8]; 2011 u8 reserved_at_568[0x3]; 2012 u8 max_geneve_tlv_option_data_len[0x5]; 2013 u8 reserved_at_570[0x1]; 2014 u8 adv_rdma[0x1]; 2015 u8 reserved_at_572[0x7]; 2016 u8 adv_virtualization[0x1]; 2017 u8 reserved_at_57a[0x6]; 2018 2019 u8 reserved_at_580[0xb]; 2020 u8 log_max_dci_stream_channels[0x5]; 2021 u8 reserved_at_590[0x3]; 2022 u8 log_max_dci_errored_streams[0x5]; 2023 u8 reserved_at_598[0x8]; 2024 2025 u8 reserved_at_5a0[0x10]; 2026 u8 enhanced_cqe_compression[0x1]; 2027 u8 reserved_at_5b1[0x1]; 2028 u8 crossing_vhca_mkey[0x1]; 2029 u8 log_max_dek[0x5]; 2030 u8 reserved_at_5b8[0x4]; 2031 u8 mini_cqe_resp_stride_index[0x1]; 2032 u8 cqe_128_always[0x1]; 2033 u8 cqe_compression_128[0x1]; 2034 u8 cqe_compression[0x1]; 2035 2036 u8 cqe_compression_timeout[0x10]; 2037 u8 cqe_compression_max_num[0x10]; 2038 2039 u8 reserved_at_5e0[0x8]; 2040 u8 flex_parser_id_gtpu_dw_0[0x4]; 2041 u8 reserved_at_5ec[0x4]; 2042 u8 tag_matching[0x1]; 2043 u8 rndv_offload_rc[0x1]; 2044 u8 rndv_offload_dc[0x1]; 2045 u8 log_tag_matching_list_sz[0x5]; 2046 u8 reserved_at_5f8[0x3]; 2047 u8 log_max_xrq[0x5]; 2048 2049 u8 affiliate_nic_vport_criteria[0x8]; 2050 u8 native_port_num[0x8]; 2051 u8 num_vhca_ports[0x8]; 2052 u8 flex_parser_id_gtpu_teid[0x4]; 2053 u8 reserved_at_61c[0x2]; 2054 u8 sw_owner_id[0x1]; 2055 u8 reserved_at_61f[0x1]; 2056 2057 u8 max_num_of_monitor_counters[0x10]; 2058 u8 num_ppcnt_monitor_counters[0x10]; 2059 2060 u8 max_num_sf[0x10]; 2061 u8 num_q_monitor_counters[0x10]; 2062 2063 u8 reserved_at_660[0x20]; 2064 2065 u8 sf[0x1]; 2066 u8 sf_set_partition[0x1]; 2067 u8 reserved_at_682[0x1]; 2068 u8 log_max_sf[0x5]; 2069 u8 apu[0x1]; 2070 u8 reserved_at_689[0x4]; 2071 u8 migration[0x1]; 2072 u8 reserved_at_68e[0x2]; 2073 u8 log_min_sf_size[0x8]; 2074 u8 max_num_sf_partitions[0x8]; 2075 2076 u8 uctx_cap[0x20]; 2077 2078 u8 reserved_at_6c0[0x4]; 2079 u8 flex_parser_id_geneve_tlv_option_0[0x4]; 2080 u8 flex_parser_id_icmp_dw1[0x4]; 2081 u8 flex_parser_id_icmp_dw0[0x4]; 2082 u8 flex_parser_id_icmpv6_dw1[0x4]; 2083 u8 flex_parser_id_icmpv6_dw0[0x4]; 2084 u8 flex_parser_id_outer_first_mpls_over_gre[0x4]; 2085 u8 flex_parser_id_outer_first_mpls_over_udp_label[0x4]; 2086 2087 u8 max_num_match_definer[0x10]; 2088 u8 sf_base_id[0x10]; 2089 2090 u8 flex_parser_id_gtpu_dw_2[0x4]; 2091 u8 flex_parser_id_gtpu_first_ext_dw_0[0x4]; 2092 u8 num_total_dynamic_vf_msix[0x18]; 2093 u8 reserved_at_720[0x14]; 2094 u8 dynamic_msix_table_size[0xc]; 2095 u8 reserved_at_740[0xc]; 2096 u8 min_dynamic_vf_msix_table_size[0x4]; 2097 u8 reserved_at_750[0x2]; 2098 u8 data_direct[0x1]; 2099 u8 reserved_at_753[0x1]; 2100 u8 max_dynamic_vf_msix_table_size[0xc]; 2101 2102 u8 reserved_at_760[0x3]; 2103 u8 log_max_num_header_modify_argument[0x5]; 2104 u8 log_header_modify_argument_granularity_offset[0x4]; 2105 u8 log_header_modify_argument_granularity[0x4]; 2106 u8 reserved_at_770[0x3]; 2107 u8 log_header_modify_argument_max_alloc[0x5]; 2108 u8 reserved_at_778[0x8]; 2109 2110 u8 vhca_tunnel_commands[0x40]; 2111 u8 match_definer_format_supported[0x40]; 2112 }; 2113 2114 enum { 2115 MLX5_CROSS_VHCA_OBJ_TO_OBJ_SUPPORTED_LOCAL_FLOW_TABLE_TO_REMOTE_FLOW_TABLE_MISS = 0x80000, 2116 MLX5_CROSS_VHCA_OBJ_TO_OBJ_SUPPORTED_LOCAL_FLOW_TABLE_ROOT_TO_REMOTE_FLOW_TABLE = (1ULL << 20), 2117 }; 2118 2119 enum { 2120 MLX5_ALLOWED_OBJ_FOR_OTHER_VHCA_ACCESS_FLOW_TABLE = 0x200, 2121 }; 2122 2123 struct mlx5_ifc_cmd_hca_cap_2_bits { 2124 u8 reserved_at_0[0x80]; 2125 2126 u8 migratable[0x1]; 2127 u8 reserved_at_81[0x7]; 2128 u8 dp_ordering_force[0x1]; 2129 u8 reserved_at_89[0x9]; 2130 u8 query_vuid[0x1]; 2131 u8 reserved_at_93[0x5]; 2132 u8 umr_log_entity_size_5[0x1]; 2133 u8 reserved_at_99[0x7]; 2134 2135 u8 max_reformat_insert_size[0x8]; 2136 u8 max_reformat_insert_offset[0x8]; 2137 u8 max_reformat_remove_size[0x8]; 2138 u8 max_reformat_remove_offset[0x8]; 2139 2140 u8 reserved_at_c0[0x8]; 2141 u8 migration_multi_load[0x1]; 2142 u8 migration_tracking_state[0x1]; 2143 u8 multiplane_qp_ud[0x1]; 2144 u8 reserved_at_cb[0x5]; 2145 u8 migration_in_chunks[0x1]; 2146 u8 reserved_at_d1[0x1]; 2147 u8 sf_eq_usage[0x1]; 2148 u8 reserved_at_d3[0x5]; 2149 u8 multiplane[0x1]; 2150 u8 reserved_at_d9[0x7]; 2151 2152 u8 cross_vhca_object_to_object_supported[0x20]; 2153 2154 u8 allowed_object_for_other_vhca_access[0x40]; 2155 2156 u8 reserved_at_140[0x60]; 2157 2158 u8 flow_table_type_2_type[0x8]; 2159 u8 reserved_at_1a8[0x2]; 2160 u8 format_select_dw_8_6_ext[0x1]; 2161 u8 log_min_mkey_entity_size[0x5]; 2162 u8 reserved_at_1b0[0x10]; 2163 2164 u8 general_obj_types_127_64[0x40]; 2165 u8 reserved_at_200[0x20]; 2166 2167 u8 reserved_at_220[0x1]; 2168 u8 sw_vhca_id_valid[0x1]; 2169 u8 sw_vhca_id[0xe]; 2170 u8 reserved_at_230[0x10]; 2171 2172 u8 reserved_at_240[0xb]; 2173 u8 ts_cqe_metadata_size2wqe_counter[0x5]; 2174 u8 reserved_at_250[0x10]; 2175 2176 u8 reserved_at_260[0x20]; 2177 2178 u8 format_select_dw_gtpu_dw_0[0x8]; 2179 u8 format_select_dw_gtpu_dw_1[0x8]; 2180 u8 format_select_dw_gtpu_dw_2[0x8]; 2181 u8 format_select_dw_gtpu_first_ext_dw_0[0x8]; 2182 2183 u8 generate_wqe_type[0x20]; 2184 2185 u8 reserved_at_2c0[0xc0]; 2186 2187 u8 reserved_at_380[0xb]; 2188 u8 min_mkey_log_entity_size_fixed_buffer[0x5]; 2189 u8 ec_vf_vport_base[0x10]; 2190 2191 u8 reserved_at_3a0[0x2]; 2192 u8 max_mkey_log_entity_size_fixed_buffer[0x6]; 2193 u8 reserved_at_3a8[0x2]; 2194 u8 max_mkey_log_entity_size_mtt[0x6]; 2195 u8 max_rqt_vhca_id[0x10]; 2196 2197 u8 reserved_at_3c0[0x20]; 2198 2199 u8 reserved_at_3e0[0x10]; 2200 u8 pcc_ifa2[0x1]; 2201 u8 reserved_at_3f1[0xf]; 2202 2203 u8 reserved_at_400[0x1]; 2204 u8 min_mkey_log_entity_size_fixed_buffer_valid[0x1]; 2205 u8 reserved_at_402[0xe]; 2206 u8 return_reg_id[0x10]; 2207 2208 u8 reserved_at_420[0x1c]; 2209 u8 flow_table_hash_type[0x4]; 2210 2211 u8 reserved_at_440[0x8]; 2212 u8 max_num_eqs_24b[0x18]; 2213 2214 u8 reserved_at_460[0x160]; 2215 2216 u8 query_adjacent_functions_id[0x1]; 2217 u8 ingress_egress_esw_vport_connect[0x1]; 2218 u8 function_id_type_vhca_id[0x1]; 2219 u8 reserved_at_5c3[0xd]; 2220 u8 delegate_vhca_management_profiles[0x10]; 2221 2222 u8 delegated_vhca_max[0x10]; 2223 u8 delegate_vhca_max[0x10]; 2224 2225 u8 reserved_at_600[0x200]; 2226 }; 2227 2228 enum mlx5_ifc_flow_destination_type { 2229 MLX5_IFC_FLOW_DESTINATION_TYPE_VPORT = 0x0, 2230 MLX5_IFC_FLOW_DESTINATION_TYPE_FLOW_TABLE = 0x1, 2231 MLX5_IFC_FLOW_DESTINATION_TYPE_TIR = 0x2, 2232 MLX5_IFC_FLOW_DESTINATION_TYPE_FLOW_SAMPLER = 0x6, 2233 MLX5_IFC_FLOW_DESTINATION_TYPE_UPLINK = 0x8, 2234 MLX5_IFC_FLOW_DESTINATION_TYPE_TABLE_TYPE = 0xA, 2235 }; 2236 2237 enum mlx5_flow_table_miss_action { 2238 MLX5_FLOW_TABLE_MISS_ACTION_DEF, 2239 MLX5_FLOW_TABLE_MISS_ACTION_FWD, 2240 MLX5_FLOW_TABLE_MISS_ACTION_SWITCH_DOMAIN, 2241 }; 2242 2243 struct mlx5_ifc_dest_format_struct_bits { 2244 u8 destination_type[0x8]; 2245 u8 destination_id[0x18]; 2246 2247 u8 destination_eswitch_owner_vhca_id_valid[0x1]; 2248 u8 packet_reformat[0x1]; 2249 u8 reserved_at_22[0x6]; 2250 u8 destination_table_type[0x8]; 2251 u8 destination_eswitch_owner_vhca_id[0x10]; 2252 }; 2253 2254 struct mlx5_ifc_flow_counter_list_bits { 2255 u8 flow_counter_id[0x20]; 2256 2257 u8 reserved_at_20[0x20]; 2258 }; 2259 2260 struct mlx5_ifc_extended_dest_format_bits { 2261 struct mlx5_ifc_dest_format_struct_bits destination_entry; 2262 2263 u8 packet_reformat_id[0x20]; 2264 2265 u8 reserved_at_60[0x20]; 2266 }; 2267 2268 union mlx5_ifc_dest_format_flow_counter_list_auto_bits { 2269 struct mlx5_ifc_extended_dest_format_bits extended_dest_format; 2270 struct mlx5_ifc_flow_counter_list_bits flow_counter_list; 2271 }; 2272 2273 struct mlx5_ifc_fte_match_param_bits { 2274 struct mlx5_ifc_fte_match_set_lyr_2_4_bits outer_headers; 2275 2276 struct mlx5_ifc_fte_match_set_misc_bits misc_parameters; 2277 2278 struct mlx5_ifc_fte_match_set_lyr_2_4_bits inner_headers; 2279 2280 struct mlx5_ifc_fte_match_set_misc2_bits misc_parameters_2; 2281 2282 struct mlx5_ifc_fte_match_set_misc3_bits misc_parameters_3; 2283 2284 struct mlx5_ifc_fte_match_set_misc4_bits misc_parameters_4; 2285 2286 struct mlx5_ifc_fte_match_set_misc5_bits misc_parameters_5; 2287 2288 u8 reserved_at_e00[0x200]; 2289 }; 2290 2291 enum { 2292 MLX5_RX_HASH_FIELD_SELECT_SELECTED_FIELDS_SRC_IP = 0x0, 2293 MLX5_RX_HASH_FIELD_SELECT_SELECTED_FIELDS_DST_IP = 0x1, 2294 MLX5_RX_HASH_FIELD_SELECT_SELECTED_FIELDS_L4_SPORT = 0x2, 2295 MLX5_RX_HASH_FIELD_SELECT_SELECTED_FIELDS_L4_DPORT = 0x3, 2296 MLX5_RX_HASH_FIELD_SELECT_SELECTED_FIELDS_IPSEC_SPI = 0x4, 2297 }; 2298 2299 struct mlx5_ifc_rx_hash_field_select_bits { 2300 u8 l3_prot_type[0x1]; 2301 u8 l4_prot_type[0x1]; 2302 u8 selected_fields[0x1e]; 2303 }; 2304 2305 enum { 2306 MLX5_WQ_WQ_TYPE_WQ_LINKED_LIST = 0x0, 2307 MLX5_WQ_WQ_TYPE_WQ_CYCLIC = 0x1, 2308 }; 2309 2310 enum { 2311 MLX5_WQ_END_PADDING_MODE_END_PAD_NONE = 0x0, 2312 MLX5_WQ_END_PADDING_MODE_END_PAD_ALIGN = 0x1, 2313 }; 2314 2315 struct mlx5_ifc_wq_bits { 2316 u8 wq_type[0x4]; 2317 u8 wq_signature[0x1]; 2318 u8 end_padding_mode[0x2]; 2319 u8 cd_slave[0x1]; 2320 u8 reserved_at_8[0x18]; 2321 2322 u8 hds_skip_first_sge[0x1]; 2323 u8 log2_hds_buf_size[0x3]; 2324 u8 reserved_at_24[0x7]; 2325 u8 page_offset[0x5]; 2326 u8 lwm[0x10]; 2327 2328 u8 reserved_at_40[0x8]; 2329 u8 pd[0x18]; 2330 2331 u8 reserved_at_60[0x8]; 2332 u8 uar_page[0x18]; 2333 2334 u8 dbr_addr[0x40]; 2335 2336 u8 hw_counter[0x20]; 2337 2338 u8 sw_counter[0x20]; 2339 2340 u8 reserved_at_100[0xc]; 2341 u8 log_wq_stride[0x4]; 2342 u8 reserved_at_110[0x3]; 2343 u8 log_wq_pg_sz[0x5]; 2344 u8 reserved_at_118[0x3]; 2345 u8 log_wq_sz[0x5]; 2346 2347 u8 dbr_umem_valid[0x1]; 2348 u8 wq_umem_valid[0x1]; 2349 u8 reserved_at_122[0x1]; 2350 u8 log_hairpin_num_packets[0x5]; 2351 u8 reserved_at_128[0x3]; 2352 u8 log_hairpin_data_sz[0x5]; 2353 2354 u8 reserved_at_130[0x4]; 2355 u8 log_wqe_num_of_strides[0x4]; 2356 u8 two_byte_shift_en[0x1]; 2357 u8 reserved_at_139[0x4]; 2358 u8 log_wqe_stride_size[0x3]; 2359 2360 u8 dbr_umem_id[0x20]; 2361 u8 wq_umem_id[0x20]; 2362 2363 u8 wq_umem_offset[0x40]; 2364 2365 u8 headers_mkey[0x20]; 2366 2367 u8 shampo_enable[0x1]; 2368 u8 reserved_at_1e1[0x1]; 2369 u8 shampo_mode[0x2]; 2370 u8 reserved_at_1e4[0x1]; 2371 u8 log_reservation_size[0x3]; 2372 u8 reserved_at_1e8[0x5]; 2373 u8 log_max_num_of_packets_per_reservation[0x3]; 2374 u8 reserved_at_1f0[0x6]; 2375 u8 log_headers_entry_size[0x2]; 2376 u8 reserved_at_1f8[0x4]; 2377 u8 log_headers_buffer_entry_num[0x4]; 2378 2379 u8 reserved_at_200[0x400]; 2380 2381 struct mlx5_ifc_cmd_pas_bits pas[]; 2382 }; 2383 2384 struct mlx5_ifc_rq_num_bits { 2385 u8 reserved_at_0[0x8]; 2386 u8 rq_num[0x18]; 2387 }; 2388 2389 struct mlx5_ifc_rq_vhca_bits { 2390 u8 reserved_at_0[0x8]; 2391 u8 rq_num[0x18]; 2392 u8 reserved_at_20[0x10]; 2393 u8 rq_vhca_id[0x10]; 2394 }; 2395 2396 struct mlx5_ifc_mac_address_layout_bits { 2397 u8 reserved_at_0[0x10]; 2398 u8 mac_addr_47_32[0x10]; 2399 2400 u8 mac_addr_31_0[0x20]; 2401 }; 2402 2403 struct mlx5_ifc_vlan_layout_bits { 2404 u8 reserved_at_0[0x14]; 2405 u8 vlan[0x0c]; 2406 2407 u8 reserved_at_20[0x20]; 2408 }; 2409 2410 struct mlx5_ifc_cong_control_r_roce_ecn_np_bits { 2411 u8 reserved_at_0[0xa0]; 2412 2413 u8 min_time_between_cnps[0x20]; 2414 2415 u8 reserved_at_c0[0x12]; 2416 u8 cnp_dscp[0x6]; 2417 u8 reserved_at_d8[0x4]; 2418 u8 cnp_prio_mode[0x1]; 2419 u8 cnp_802p_prio[0x3]; 2420 2421 u8 reserved_at_e0[0x720]; 2422 }; 2423 2424 struct mlx5_ifc_cong_control_r_roce_ecn_rp_bits { 2425 u8 reserved_at_0[0x60]; 2426 2427 u8 reserved_at_60[0x4]; 2428 u8 clamp_tgt_rate[0x1]; 2429 u8 reserved_at_65[0x3]; 2430 u8 clamp_tgt_rate_after_time_inc[0x1]; 2431 u8 reserved_at_69[0x17]; 2432 2433 u8 reserved_at_80[0x20]; 2434 2435 u8 rpg_time_reset[0x20]; 2436 2437 u8 rpg_byte_reset[0x20]; 2438 2439 u8 rpg_threshold[0x20]; 2440 2441 u8 rpg_max_rate[0x20]; 2442 2443 u8 rpg_ai_rate[0x20]; 2444 2445 u8 rpg_hai_rate[0x20]; 2446 2447 u8 rpg_gd[0x20]; 2448 2449 u8 rpg_min_dec_fac[0x20]; 2450 2451 u8 rpg_min_rate[0x20]; 2452 2453 u8 reserved_at_1c0[0xe0]; 2454 2455 u8 rate_to_set_on_first_cnp[0x20]; 2456 2457 u8 dce_tcp_g[0x20]; 2458 2459 u8 dce_tcp_rtt[0x20]; 2460 2461 u8 rate_reduce_monitor_period[0x20]; 2462 2463 u8 reserved_at_320[0x20]; 2464 2465 u8 initial_alpha_value[0x20]; 2466 2467 u8 reserved_at_360[0x4a0]; 2468 }; 2469 2470 struct mlx5_ifc_cong_control_r_roce_general_bits { 2471 u8 reserved_at_0[0x80]; 2472 2473 u8 reserved_at_80[0x10]; 2474 u8 rtt_resp_dscp_valid[0x1]; 2475 u8 reserved_at_91[0x9]; 2476 u8 rtt_resp_dscp[0x6]; 2477 2478 u8 reserved_at_a0[0x760]; 2479 }; 2480 2481 struct mlx5_ifc_cong_control_802_1qau_rp_bits { 2482 u8 reserved_at_0[0x80]; 2483 2484 u8 rppp_max_rps[0x20]; 2485 2486 u8 rpg_time_reset[0x20]; 2487 2488 u8 rpg_byte_reset[0x20]; 2489 2490 u8 rpg_threshold[0x20]; 2491 2492 u8 rpg_max_rate[0x20]; 2493 2494 u8 rpg_ai_rate[0x20]; 2495 2496 u8 rpg_hai_rate[0x20]; 2497 2498 u8 rpg_gd[0x20]; 2499 2500 u8 rpg_min_dec_fac[0x20]; 2501 2502 u8 rpg_min_rate[0x20]; 2503 2504 u8 reserved_at_1c0[0x640]; 2505 }; 2506 2507 enum { 2508 MLX5_RESIZE_FIELD_SELECT_RESIZE_FIELD_SELECT_LOG_CQ_SIZE = 0x1, 2509 MLX5_RESIZE_FIELD_SELECT_RESIZE_FIELD_SELECT_PAGE_OFFSET = 0x2, 2510 MLX5_RESIZE_FIELD_SELECT_RESIZE_FIELD_SELECT_LOG_PAGE_SIZE = 0x4, 2511 }; 2512 2513 struct mlx5_ifc_resize_field_select_bits { 2514 u8 resize_field_select[0x20]; 2515 }; 2516 2517 struct mlx5_ifc_resource_dump_bits { 2518 u8 more_dump[0x1]; 2519 u8 inline_dump[0x1]; 2520 u8 reserved_at_2[0xa]; 2521 u8 seq_num[0x4]; 2522 u8 segment_type[0x10]; 2523 2524 u8 reserved_at_20[0x10]; 2525 u8 vhca_id[0x10]; 2526 2527 u8 index1[0x20]; 2528 2529 u8 index2[0x20]; 2530 2531 u8 num_of_obj1[0x10]; 2532 u8 num_of_obj2[0x10]; 2533 2534 u8 reserved_at_a0[0x20]; 2535 2536 u8 device_opaque[0x40]; 2537 2538 u8 mkey[0x20]; 2539 2540 u8 size[0x20]; 2541 2542 u8 address[0x40]; 2543 2544 u8 inline_data[52][0x20]; 2545 }; 2546 2547 struct mlx5_ifc_resource_dump_menu_record_bits { 2548 u8 reserved_at_0[0x4]; 2549 u8 num_of_obj2_supports_active[0x1]; 2550 u8 num_of_obj2_supports_all[0x1]; 2551 u8 must_have_num_of_obj2[0x1]; 2552 u8 support_num_of_obj2[0x1]; 2553 u8 num_of_obj1_supports_active[0x1]; 2554 u8 num_of_obj1_supports_all[0x1]; 2555 u8 must_have_num_of_obj1[0x1]; 2556 u8 support_num_of_obj1[0x1]; 2557 u8 must_have_index2[0x1]; 2558 u8 support_index2[0x1]; 2559 u8 must_have_index1[0x1]; 2560 u8 support_index1[0x1]; 2561 u8 segment_type[0x10]; 2562 2563 u8 segment_name[4][0x20]; 2564 2565 u8 index1_name[4][0x20]; 2566 2567 u8 index2_name[4][0x20]; 2568 }; 2569 2570 struct mlx5_ifc_resource_dump_segment_header_bits { 2571 u8 length_dw[0x10]; 2572 u8 segment_type[0x10]; 2573 }; 2574 2575 struct mlx5_ifc_resource_dump_command_segment_bits { 2576 struct mlx5_ifc_resource_dump_segment_header_bits segment_header; 2577 2578 u8 segment_called[0x10]; 2579 u8 vhca_id[0x10]; 2580 2581 u8 index1[0x20]; 2582 2583 u8 index2[0x20]; 2584 2585 u8 num_of_obj1[0x10]; 2586 u8 num_of_obj2[0x10]; 2587 }; 2588 2589 struct mlx5_ifc_resource_dump_error_segment_bits { 2590 struct mlx5_ifc_resource_dump_segment_header_bits segment_header; 2591 2592 u8 reserved_at_20[0x10]; 2593 u8 syndrome_id[0x10]; 2594 2595 u8 reserved_at_40[0x40]; 2596 2597 u8 error[8][0x20]; 2598 }; 2599 2600 struct mlx5_ifc_resource_dump_info_segment_bits { 2601 struct mlx5_ifc_resource_dump_segment_header_bits segment_header; 2602 2603 u8 reserved_at_20[0x18]; 2604 u8 dump_version[0x8]; 2605 2606 u8 hw_version[0x20]; 2607 2608 u8 fw_version[0x20]; 2609 }; 2610 2611 struct mlx5_ifc_resource_dump_menu_segment_bits { 2612 struct mlx5_ifc_resource_dump_segment_header_bits segment_header; 2613 2614 u8 reserved_at_20[0x10]; 2615 u8 num_of_records[0x10]; 2616 2617 struct mlx5_ifc_resource_dump_menu_record_bits record[]; 2618 }; 2619 2620 struct mlx5_ifc_resource_dump_resource_segment_bits { 2621 struct mlx5_ifc_resource_dump_segment_header_bits segment_header; 2622 2623 u8 reserved_at_20[0x20]; 2624 2625 u8 index1[0x20]; 2626 2627 u8 index2[0x20]; 2628 2629 u8 payload[][0x20]; 2630 }; 2631 2632 struct mlx5_ifc_resource_dump_terminate_segment_bits { 2633 struct mlx5_ifc_resource_dump_segment_header_bits segment_header; 2634 }; 2635 2636 struct mlx5_ifc_menu_resource_dump_response_bits { 2637 struct mlx5_ifc_resource_dump_info_segment_bits info; 2638 struct mlx5_ifc_resource_dump_command_segment_bits cmd; 2639 struct mlx5_ifc_resource_dump_menu_segment_bits menu; 2640 struct mlx5_ifc_resource_dump_terminate_segment_bits terminate; 2641 }; 2642 2643 enum { 2644 MLX5_MODIFY_FIELD_SELECT_MODIFY_FIELD_SELECT_CQ_PERIOD = 0x1, 2645 MLX5_MODIFY_FIELD_SELECT_MODIFY_FIELD_SELECT_CQ_MAX_COUNT = 0x2, 2646 MLX5_MODIFY_FIELD_SELECT_MODIFY_FIELD_SELECT_OI = 0x4, 2647 MLX5_MODIFY_FIELD_SELECT_MODIFY_FIELD_SELECT_C_EQN = 0x8, 2648 }; 2649 2650 struct mlx5_ifc_modify_field_select_bits { 2651 u8 modify_field_select[0x20]; 2652 }; 2653 2654 struct mlx5_ifc_field_select_r_roce_np_bits { 2655 u8 field_select_r_roce_np[0x20]; 2656 }; 2657 2658 struct mlx5_ifc_field_select_r_roce_rp_bits { 2659 u8 field_select_r_roce_rp[0x20]; 2660 }; 2661 2662 enum { 2663 MLX5_FIELD_SELECT_802_1QAU_RP_FIELD_SELECT_8021QAURP_RPPP_MAX_RPS = 0x4, 2664 MLX5_FIELD_SELECT_802_1QAU_RP_FIELD_SELECT_8021QAURP_RPG_TIME_RESET = 0x8, 2665 MLX5_FIELD_SELECT_802_1QAU_RP_FIELD_SELECT_8021QAURP_RPG_BYTE_RESET = 0x10, 2666 MLX5_FIELD_SELECT_802_1QAU_RP_FIELD_SELECT_8021QAURP_RPG_THRESHOLD = 0x20, 2667 MLX5_FIELD_SELECT_802_1QAU_RP_FIELD_SELECT_8021QAURP_RPG_MAX_RATE = 0x40, 2668 MLX5_FIELD_SELECT_802_1QAU_RP_FIELD_SELECT_8021QAURP_RPG_AI_RATE = 0x80, 2669 MLX5_FIELD_SELECT_802_1QAU_RP_FIELD_SELECT_8021QAURP_RPG_HAI_RATE = 0x100, 2670 MLX5_FIELD_SELECT_802_1QAU_RP_FIELD_SELECT_8021QAURP_RPG_GD = 0x200, 2671 MLX5_FIELD_SELECT_802_1QAU_RP_FIELD_SELECT_8021QAURP_RPG_MIN_DEC_FAC = 0x400, 2672 MLX5_FIELD_SELECT_802_1QAU_RP_FIELD_SELECT_8021QAURP_RPG_MIN_RATE = 0x800, 2673 }; 2674 2675 struct mlx5_ifc_field_select_802_1qau_rp_bits { 2676 u8 field_select_8021qaurp[0x20]; 2677 }; 2678 2679 struct mlx5_ifc_phys_layer_recovery_cntrs_bits { 2680 u8 total_successful_recovery_events[0x20]; 2681 2682 u8 reserved_at_20[0x7a0]; 2683 }; 2684 2685 struct mlx5_ifc_phys_layer_cntrs_bits { 2686 u8 time_since_last_clear_high[0x20]; 2687 2688 u8 time_since_last_clear_low[0x20]; 2689 2690 u8 symbol_errors_high[0x20]; 2691 2692 u8 symbol_errors_low[0x20]; 2693 2694 u8 sync_headers_errors_high[0x20]; 2695 2696 u8 sync_headers_errors_low[0x20]; 2697 2698 u8 edpl_bip_errors_lane0_high[0x20]; 2699 2700 u8 edpl_bip_errors_lane0_low[0x20]; 2701 2702 u8 edpl_bip_errors_lane1_high[0x20]; 2703 2704 u8 edpl_bip_errors_lane1_low[0x20]; 2705 2706 u8 edpl_bip_errors_lane2_high[0x20]; 2707 2708 u8 edpl_bip_errors_lane2_low[0x20]; 2709 2710 u8 edpl_bip_errors_lane3_high[0x20]; 2711 2712 u8 edpl_bip_errors_lane3_low[0x20]; 2713 2714 u8 fc_fec_corrected_blocks_lane0_high[0x20]; 2715 2716 u8 fc_fec_corrected_blocks_lane0_low[0x20]; 2717 2718 u8 fc_fec_corrected_blocks_lane1_high[0x20]; 2719 2720 u8 fc_fec_corrected_blocks_lane1_low[0x20]; 2721 2722 u8 fc_fec_corrected_blocks_lane2_high[0x20]; 2723 2724 u8 fc_fec_corrected_blocks_lane2_low[0x20]; 2725 2726 u8 fc_fec_corrected_blocks_lane3_high[0x20]; 2727 2728 u8 fc_fec_corrected_blocks_lane3_low[0x20]; 2729 2730 u8 fc_fec_uncorrectable_blocks_lane0_high[0x20]; 2731 2732 u8 fc_fec_uncorrectable_blocks_lane0_low[0x20]; 2733 2734 u8 fc_fec_uncorrectable_blocks_lane1_high[0x20]; 2735 2736 u8 fc_fec_uncorrectable_blocks_lane1_low[0x20]; 2737 2738 u8 fc_fec_uncorrectable_blocks_lane2_high[0x20]; 2739 2740 u8 fc_fec_uncorrectable_blocks_lane2_low[0x20]; 2741 2742 u8 fc_fec_uncorrectable_blocks_lane3_high[0x20]; 2743 2744 u8 fc_fec_uncorrectable_blocks_lane3_low[0x20]; 2745 2746 u8 rs_fec_corrected_blocks_high[0x20]; 2747 2748 u8 rs_fec_corrected_blocks_low[0x20]; 2749 2750 u8 rs_fec_uncorrectable_blocks_high[0x20]; 2751 2752 u8 rs_fec_uncorrectable_blocks_low[0x20]; 2753 2754 u8 rs_fec_no_errors_blocks_high[0x20]; 2755 2756 u8 rs_fec_no_errors_blocks_low[0x20]; 2757 2758 u8 rs_fec_single_error_blocks_high[0x20]; 2759 2760 u8 rs_fec_single_error_blocks_low[0x20]; 2761 2762 u8 rs_fec_corrected_symbols_total_high[0x20]; 2763 2764 u8 rs_fec_corrected_symbols_total_low[0x20]; 2765 2766 u8 rs_fec_corrected_symbols_lane0_high[0x20]; 2767 2768 u8 rs_fec_corrected_symbols_lane0_low[0x20]; 2769 2770 u8 rs_fec_corrected_symbols_lane1_high[0x20]; 2771 2772 u8 rs_fec_corrected_symbols_lane1_low[0x20]; 2773 2774 u8 rs_fec_corrected_symbols_lane2_high[0x20]; 2775 2776 u8 rs_fec_corrected_symbols_lane2_low[0x20]; 2777 2778 u8 rs_fec_corrected_symbols_lane3_high[0x20]; 2779 2780 u8 rs_fec_corrected_symbols_lane3_low[0x20]; 2781 2782 u8 link_down_events[0x20]; 2783 2784 u8 successful_recovery_events[0x20]; 2785 2786 u8 reserved_at_640[0x180]; 2787 }; 2788 2789 struct mlx5_ifc_phys_layer_statistical_cntrs_bits { 2790 u8 time_since_last_clear_high[0x20]; 2791 2792 u8 time_since_last_clear_low[0x20]; 2793 2794 u8 phy_received_bits_high[0x20]; 2795 2796 u8 phy_received_bits_low[0x20]; 2797 2798 u8 phy_symbol_errors_high[0x20]; 2799 2800 u8 phy_symbol_errors_low[0x20]; 2801 2802 u8 phy_corrected_bits_high[0x20]; 2803 2804 u8 phy_corrected_bits_low[0x20]; 2805 2806 u8 phy_corrected_bits_lane0_high[0x20]; 2807 2808 u8 phy_corrected_bits_lane0_low[0x20]; 2809 2810 u8 phy_corrected_bits_lane1_high[0x20]; 2811 2812 u8 phy_corrected_bits_lane1_low[0x20]; 2813 2814 u8 phy_corrected_bits_lane2_high[0x20]; 2815 2816 u8 phy_corrected_bits_lane2_low[0x20]; 2817 2818 u8 phy_corrected_bits_lane3_high[0x20]; 2819 2820 u8 phy_corrected_bits_lane3_low[0x20]; 2821 2822 u8 reserved_at_200[0x5c0]; 2823 }; 2824 2825 struct mlx5_ifc_ib_port_cntrs_grp_data_layout_bits { 2826 u8 symbol_error_counter[0x10]; 2827 2828 u8 link_error_recovery_counter[0x8]; 2829 2830 u8 link_downed_counter[0x8]; 2831 2832 u8 port_rcv_errors[0x10]; 2833 2834 u8 port_rcv_remote_physical_errors[0x10]; 2835 2836 u8 port_rcv_switch_relay_errors[0x10]; 2837 2838 u8 port_xmit_discards[0x10]; 2839 2840 u8 port_xmit_constraint_errors[0x8]; 2841 2842 u8 port_rcv_constraint_errors[0x8]; 2843 2844 u8 reserved_at_70[0x8]; 2845 2846 u8 link_overrun_errors[0x8]; 2847 2848 u8 reserved_at_80[0x10]; 2849 2850 u8 vl_15_dropped[0x10]; 2851 2852 u8 reserved_at_a0[0x80]; 2853 2854 u8 port_xmit_wait[0x20]; 2855 }; 2856 2857 struct mlx5_ifc_ib_ext_port_cntrs_grp_data_layout_bits { 2858 u8 reserved_at_0[0x300]; 2859 2860 u8 port_xmit_data_high[0x20]; 2861 2862 u8 port_xmit_data_low[0x20]; 2863 2864 u8 port_rcv_data_high[0x20]; 2865 2866 u8 port_rcv_data_low[0x20]; 2867 2868 u8 port_xmit_pkts_high[0x20]; 2869 2870 u8 port_xmit_pkts_low[0x20]; 2871 2872 u8 port_rcv_pkts_high[0x20]; 2873 2874 u8 port_rcv_pkts_low[0x20]; 2875 2876 u8 reserved_at_400[0x80]; 2877 2878 u8 port_unicast_xmit_pkts_high[0x20]; 2879 2880 u8 port_unicast_xmit_pkts_low[0x20]; 2881 2882 u8 port_multicast_xmit_pkts_high[0x20]; 2883 2884 u8 port_multicast_xmit_pkts_low[0x20]; 2885 2886 u8 port_unicast_rcv_pkts_high[0x20]; 2887 2888 u8 port_unicast_rcv_pkts_low[0x20]; 2889 2890 u8 port_multicast_rcv_pkts_high[0x20]; 2891 2892 u8 port_multicast_rcv_pkts_low[0x20]; 2893 2894 u8 reserved_at_580[0x240]; 2895 }; 2896 2897 struct mlx5_ifc_eth_per_tc_prio_grp_data_layout_bits { 2898 u8 transmit_queue_high[0x20]; 2899 2900 u8 transmit_queue_low[0x20]; 2901 2902 u8 no_buffer_discard_uc_high[0x20]; 2903 2904 u8 no_buffer_discard_uc_low[0x20]; 2905 2906 u8 reserved_at_80[0x740]; 2907 }; 2908 2909 struct mlx5_ifc_eth_per_tc_congest_prio_grp_data_layout_bits { 2910 u8 wred_discard_high[0x20]; 2911 2912 u8 wred_discard_low[0x20]; 2913 2914 u8 ecn_marked_tc_high[0x20]; 2915 2916 u8 ecn_marked_tc_low[0x20]; 2917 2918 u8 reserved_at_80[0x740]; 2919 }; 2920 2921 struct mlx5_ifc_eth_per_prio_grp_data_layout_bits { 2922 u8 rx_octets_high[0x20]; 2923 2924 u8 rx_octets_low[0x20]; 2925 2926 u8 reserved_at_40[0xc0]; 2927 2928 u8 rx_frames_high[0x20]; 2929 2930 u8 rx_frames_low[0x20]; 2931 2932 u8 tx_octets_high[0x20]; 2933 2934 u8 tx_octets_low[0x20]; 2935 2936 u8 reserved_at_180[0xc0]; 2937 2938 u8 tx_frames_high[0x20]; 2939 2940 u8 tx_frames_low[0x20]; 2941 2942 u8 rx_pause_high[0x20]; 2943 2944 u8 rx_pause_low[0x20]; 2945 2946 u8 rx_pause_duration_high[0x20]; 2947 2948 u8 rx_pause_duration_low[0x20]; 2949 2950 u8 tx_pause_high[0x20]; 2951 2952 u8 tx_pause_low[0x20]; 2953 2954 u8 tx_pause_duration_high[0x20]; 2955 2956 u8 tx_pause_duration_low[0x20]; 2957 2958 u8 rx_pause_transition_high[0x20]; 2959 2960 u8 rx_pause_transition_low[0x20]; 2961 2962 u8 rx_discards_high[0x20]; 2963 2964 u8 rx_discards_low[0x20]; 2965 2966 u8 device_stall_minor_watermark_cnt_high[0x20]; 2967 2968 u8 device_stall_minor_watermark_cnt_low[0x20]; 2969 2970 u8 device_stall_critical_watermark_cnt_high[0x20]; 2971 2972 u8 device_stall_critical_watermark_cnt_low[0x20]; 2973 2974 u8 reserved_at_480[0x340]; 2975 }; 2976 2977 struct mlx5_ifc_eth_extended_cntrs_grp_data_layout_bits { 2978 u8 port_transmit_wait_high[0x20]; 2979 2980 u8 port_transmit_wait_low[0x20]; 2981 2982 u8 reserved_at_40[0x100]; 2983 2984 u8 rx_buffer_almost_full_high[0x20]; 2985 2986 u8 rx_buffer_almost_full_low[0x20]; 2987 2988 u8 rx_buffer_full_high[0x20]; 2989 2990 u8 rx_buffer_full_low[0x20]; 2991 2992 u8 rx_icrc_encapsulated_high[0x20]; 2993 2994 u8 rx_icrc_encapsulated_low[0x20]; 2995 2996 u8 reserved_at_200[0x5c0]; 2997 }; 2998 2999 struct mlx5_ifc_eth_3635_cntrs_grp_data_layout_bits { 3000 u8 dot3stats_alignment_errors_high[0x20]; 3001 3002 u8 dot3stats_alignment_errors_low[0x20]; 3003 3004 u8 dot3stats_fcs_errors_high[0x20]; 3005 3006 u8 dot3stats_fcs_errors_low[0x20]; 3007 3008 u8 dot3stats_single_collision_frames_high[0x20]; 3009 3010 u8 dot3stats_single_collision_frames_low[0x20]; 3011 3012 u8 dot3stats_multiple_collision_frames_high[0x20]; 3013 3014 u8 dot3stats_multiple_collision_frames_low[0x20]; 3015 3016 u8 dot3stats_sqe_test_errors_high[0x20]; 3017 3018 u8 dot3stats_sqe_test_errors_low[0x20]; 3019 3020 u8 dot3stats_deferred_transmissions_high[0x20]; 3021 3022 u8 dot3stats_deferred_transmissions_low[0x20]; 3023 3024 u8 dot3stats_late_collisions_high[0x20]; 3025 3026 u8 dot3stats_late_collisions_low[0x20]; 3027 3028 u8 dot3stats_excessive_collisions_high[0x20]; 3029 3030 u8 dot3stats_excessive_collisions_low[0x20]; 3031 3032 u8 dot3stats_internal_mac_transmit_errors_high[0x20]; 3033 3034 u8 dot3stats_internal_mac_transmit_errors_low[0x20]; 3035 3036 u8 dot3stats_carrier_sense_errors_high[0x20]; 3037 3038 u8 dot3stats_carrier_sense_errors_low[0x20]; 3039 3040 u8 dot3stats_frame_too_longs_high[0x20]; 3041 3042 u8 dot3stats_frame_too_longs_low[0x20]; 3043 3044 u8 dot3stats_internal_mac_receive_errors_high[0x20]; 3045 3046 u8 dot3stats_internal_mac_receive_errors_low[0x20]; 3047 3048 u8 dot3stats_symbol_errors_high[0x20]; 3049 3050 u8 dot3stats_symbol_errors_low[0x20]; 3051 3052 u8 dot3control_in_unknown_opcodes_high[0x20]; 3053 3054 u8 dot3control_in_unknown_opcodes_low[0x20]; 3055 3056 u8 dot3in_pause_frames_high[0x20]; 3057 3058 u8 dot3in_pause_frames_low[0x20]; 3059 3060 u8 dot3out_pause_frames_high[0x20]; 3061 3062 u8 dot3out_pause_frames_low[0x20]; 3063 3064 u8 reserved_at_400[0x3c0]; 3065 }; 3066 3067 struct mlx5_ifc_eth_2819_cntrs_grp_data_layout_bits { 3068 u8 ether_stats_drop_events_high[0x20]; 3069 3070 u8 ether_stats_drop_events_low[0x20]; 3071 3072 u8 ether_stats_octets_high[0x20]; 3073 3074 u8 ether_stats_octets_low[0x20]; 3075 3076 u8 ether_stats_pkts_high[0x20]; 3077 3078 u8 ether_stats_pkts_low[0x20]; 3079 3080 u8 ether_stats_broadcast_pkts_high[0x20]; 3081 3082 u8 ether_stats_broadcast_pkts_low[0x20]; 3083 3084 u8 ether_stats_multicast_pkts_high[0x20]; 3085 3086 u8 ether_stats_multicast_pkts_low[0x20]; 3087 3088 u8 ether_stats_crc_align_errors_high[0x20]; 3089 3090 u8 ether_stats_crc_align_errors_low[0x20]; 3091 3092 u8 ether_stats_undersize_pkts_high[0x20]; 3093 3094 u8 ether_stats_undersize_pkts_low[0x20]; 3095 3096 u8 ether_stats_oversize_pkts_high[0x20]; 3097 3098 u8 ether_stats_oversize_pkts_low[0x20]; 3099 3100 u8 ether_stats_fragments_high[0x20]; 3101 3102 u8 ether_stats_fragments_low[0x20]; 3103 3104 u8 ether_stats_jabbers_high[0x20]; 3105 3106 u8 ether_stats_jabbers_low[0x20]; 3107 3108 u8 ether_stats_collisions_high[0x20]; 3109 3110 u8 ether_stats_collisions_low[0x20]; 3111 3112 u8 ether_stats_pkts64octets_high[0x20]; 3113 3114 u8 ether_stats_pkts64octets_low[0x20]; 3115 3116 u8 ether_stats_pkts65to127octets_high[0x20]; 3117 3118 u8 ether_stats_pkts65to127octets_low[0x20]; 3119 3120 u8 ether_stats_pkts128to255octets_high[0x20]; 3121 3122 u8 ether_stats_pkts128to255octets_low[0x20]; 3123 3124 u8 ether_stats_pkts256to511octets_high[0x20]; 3125 3126 u8 ether_stats_pkts256to511octets_low[0x20]; 3127 3128 u8 ether_stats_pkts512to1023octets_high[0x20]; 3129 3130 u8 ether_stats_pkts512to1023octets_low[0x20]; 3131 3132 u8 ether_stats_pkts1024to1518octets_high[0x20]; 3133 3134 u8 ether_stats_pkts1024to1518octets_low[0x20]; 3135 3136 u8 ether_stats_pkts1519to2047octets_high[0x20]; 3137 3138 u8 ether_stats_pkts1519to2047octets_low[0x20]; 3139 3140 u8 ether_stats_pkts2048to4095octets_high[0x20]; 3141 3142 u8 ether_stats_pkts2048to4095octets_low[0x20]; 3143 3144 u8 ether_stats_pkts4096to8191octets_high[0x20]; 3145 3146 u8 ether_stats_pkts4096to8191octets_low[0x20]; 3147 3148 u8 ether_stats_pkts8192to10239octets_high[0x20]; 3149 3150 u8 ether_stats_pkts8192to10239octets_low[0x20]; 3151 3152 u8 reserved_at_540[0x280]; 3153 }; 3154 3155 struct mlx5_ifc_eth_2863_cntrs_grp_data_layout_bits { 3156 u8 if_in_octets_high[0x20]; 3157 3158 u8 if_in_octets_low[0x20]; 3159 3160 u8 if_in_ucast_pkts_high[0x20]; 3161 3162 u8 if_in_ucast_pkts_low[0x20]; 3163 3164 u8 if_in_discards_high[0x20]; 3165 3166 u8 if_in_discards_low[0x20]; 3167 3168 u8 if_in_errors_high[0x20]; 3169 3170 u8 if_in_errors_low[0x20]; 3171 3172 u8 if_in_unknown_protos_high[0x20]; 3173 3174 u8 if_in_unknown_protos_low[0x20]; 3175 3176 u8 if_out_octets_high[0x20]; 3177 3178 u8 if_out_octets_low[0x20]; 3179 3180 u8 if_out_ucast_pkts_high[0x20]; 3181 3182 u8 if_out_ucast_pkts_low[0x20]; 3183 3184 u8 if_out_discards_high[0x20]; 3185 3186 u8 if_out_discards_low[0x20]; 3187 3188 u8 if_out_errors_high[0x20]; 3189 3190 u8 if_out_errors_low[0x20]; 3191 3192 u8 if_in_multicast_pkts_high[0x20]; 3193 3194 u8 if_in_multicast_pkts_low[0x20]; 3195 3196 u8 if_in_broadcast_pkts_high[0x20]; 3197 3198 u8 if_in_broadcast_pkts_low[0x20]; 3199 3200 u8 if_out_multicast_pkts_high[0x20]; 3201 3202 u8 if_out_multicast_pkts_low[0x20]; 3203 3204 u8 if_out_broadcast_pkts_high[0x20]; 3205 3206 u8 if_out_broadcast_pkts_low[0x20]; 3207 3208 u8 reserved_at_340[0x480]; 3209 }; 3210 3211 struct mlx5_ifc_eth_802_3_cntrs_grp_data_layout_bits { 3212 u8 a_frames_transmitted_ok_high[0x20]; 3213 3214 u8 a_frames_transmitted_ok_low[0x20]; 3215 3216 u8 a_frames_received_ok_high[0x20]; 3217 3218 u8 a_frames_received_ok_low[0x20]; 3219 3220 u8 a_frame_check_sequence_errors_high[0x20]; 3221 3222 u8 a_frame_check_sequence_errors_low[0x20]; 3223 3224 u8 a_alignment_errors_high[0x20]; 3225 3226 u8 a_alignment_errors_low[0x20]; 3227 3228 u8 a_octets_transmitted_ok_high[0x20]; 3229 3230 u8 a_octets_transmitted_ok_low[0x20]; 3231 3232 u8 a_octets_received_ok_high[0x20]; 3233 3234 u8 a_octets_received_ok_low[0x20]; 3235 3236 u8 a_multicast_frames_xmitted_ok_high[0x20]; 3237 3238 u8 a_multicast_frames_xmitted_ok_low[0x20]; 3239 3240 u8 a_broadcast_frames_xmitted_ok_high[0x20]; 3241 3242 u8 a_broadcast_frames_xmitted_ok_low[0x20]; 3243 3244 u8 a_multicast_frames_received_ok_high[0x20]; 3245 3246 u8 a_multicast_frames_received_ok_low[0x20]; 3247 3248 u8 a_broadcast_frames_received_ok_high[0x20]; 3249 3250 u8 a_broadcast_frames_received_ok_low[0x20]; 3251 3252 u8 a_in_range_length_errors_high[0x20]; 3253 3254 u8 a_in_range_length_errors_low[0x20]; 3255 3256 u8 a_out_of_range_length_field_high[0x20]; 3257 3258 u8 a_out_of_range_length_field_low[0x20]; 3259 3260 u8 a_frame_too_long_errors_high[0x20]; 3261 3262 u8 a_frame_too_long_errors_low[0x20]; 3263 3264 u8 a_symbol_error_during_carrier_high[0x20]; 3265 3266 u8 a_symbol_error_during_carrier_low[0x20]; 3267 3268 u8 a_mac_control_frames_transmitted_high[0x20]; 3269 3270 u8 a_mac_control_frames_transmitted_low[0x20]; 3271 3272 u8 a_mac_control_frames_received_high[0x20]; 3273 3274 u8 a_mac_control_frames_received_low[0x20]; 3275 3276 u8 a_unsupported_opcodes_received_high[0x20]; 3277 3278 u8 a_unsupported_opcodes_received_low[0x20]; 3279 3280 u8 a_pause_mac_ctrl_frames_received_high[0x20]; 3281 3282 u8 a_pause_mac_ctrl_frames_received_low[0x20]; 3283 3284 u8 a_pause_mac_ctrl_frames_transmitted_high[0x20]; 3285 3286 u8 a_pause_mac_ctrl_frames_transmitted_low[0x20]; 3287 3288 u8 reserved_at_4c0[0x300]; 3289 }; 3290 3291 struct mlx5_ifc_pcie_perf_cntrs_grp_data_layout_bits { 3292 u8 life_time_counter_high[0x20]; 3293 3294 u8 life_time_counter_low[0x20]; 3295 3296 u8 rx_errors[0x20]; 3297 3298 u8 tx_errors[0x20]; 3299 3300 u8 l0_to_recovery_eieos[0x20]; 3301 3302 u8 l0_to_recovery_ts[0x20]; 3303 3304 u8 l0_to_recovery_framing[0x20]; 3305 3306 u8 l0_to_recovery_retrain[0x20]; 3307 3308 u8 crc_error_dllp[0x20]; 3309 3310 u8 crc_error_tlp[0x20]; 3311 3312 u8 tx_overflow_buffer_pkt_high[0x20]; 3313 3314 u8 tx_overflow_buffer_pkt_low[0x20]; 3315 3316 u8 outbound_stalled_reads[0x20]; 3317 3318 u8 outbound_stalled_writes[0x20]; 3319 3320 u8 outbound_stalled_reads_events[0x20]; 3321 3322 u8 outbound_stalled_writes_events[0x20]; 3323 3324 u8 reserved_at_200[0x5c0]; 3325 }; 3326 3327 struct mlx5_ifc_cmd_inter_comp_event_bits { 3328 u8 command_completion_vector[0x20]; 3329 3330 u8 reserved_at_20[0xc0]; 3331 }; 3332 3333 struct mlx5_ifc_stall_vl_event_bits { 3334 u8 reserved_at_0[0x18]; 3335 u8 port_num[0x1]; 3336 u8 reserved_at_19[0x3]; 3337 u8 vl[0x4]; 3338 3339 u8 reserved_at_20[0xa0]; 3340 }; 3341 3342 struct mlx5_ifc_db_bf_congestion_event_bits { 3343 u8 event_subtype[0x8]; 3344 u8 reserved_at_8[0x8]; 3345 u8 congestion_level[0x8]; 3346 u8 reserved_at_18[0x8]; 3347 3348 u8 reserved_at_20[0xa0]; 3349 }; 3350 3351 struct mlx5_ifc_gpio_event_bits { 3352 u8 reserved_at_0[0x60]; 3353 3354 u8 gpio_event_hi[0x20]; 3355 3356 u8 gpio_event_lo[0x20]; 3357 3358 u8 reserved_at_a0[0x40]; 3359 }; 3360 3361 struct mlx5_ifc_port_state_change_event_bits { 3362 u8 reserved_at_0[0x40]; 3363 3364 u8 port_num[0x4]; 3365 u8 reserved_at_44[0x1c]; 3366 3367 u8 reserved_at_60[0x80]; 3368 }; 3369 3370 struct mlx5_ifc_dropped_packet_logged_bits { 3371 u8 reserved_at_0[0xe0]; 3372 }; 3373 3374 struct mlx5_ifc_nic_cap_reg_bits { 3375 u8 reserved_at_0[0x1a]; 3376 u8 vhca_icm_ctrl[0x1]; 3377 u8 reserved_at_1b[0x5]; 3378 3379 u8 reserved_at_20[0x60]; 3380 }; 3381 3382 struct mlx5_ifc_default_timeout_bits { 3383 u8 to_multiplier[0x3]; 3384 u8 reserved_at_3[0x9]; 3385 u8 to_value[0x14]; 3386 }; 3387 3388 struct mlx5_ifc_dtor_reg_bits { 3389 u8 reserved_at_0[0x20]; 3390 3391 struct mlx5_ifc_default_timeout_bits pcie_toggle_to; 3392 3393 u8 reserved_at_40[0x60]; 3394 3395 struct mlx5_ifc_default_timeout_bits health_poll_to; 3396 3397 struct mlx5_ifc_default_timeout_bits full_crdump_to; 3398 3399 struct mlx5_ifc_default_timeout_bits fw_reset_to; 3400 3401 struct mlx5_ifc_default_timeout_bits flush_on_err_to; 3402 3403 struct mlx5_ifc_default_timeout_bits pci_sync_update_to; 3404 3405 struct mlx5_ifc_default_timeout_bits tear_down_to; 3406 3407 struct mlx5_ifc_default_timeout_bits fsm_reactivate_to; 3408 3409 struct mlx5_ifc_default_timeout_bits reclaim_pages_to; 3410 3411 struct mlx5_ifc_default_timeout_bits reclaim_vfs_pages_to; 3412 3413 struct mlx5_ifc_default_timeout_bits reset_unload_to; 3414 3415 u8 reserved_at_1c0[0x20]; 3416 }; 3417 3418 struct mlx5_ifc_vhca_icm_ctrl_reg_bits { 3419 u8 vhca_id_valid[0x1]; 3420 u8 reserved_at_1[0xf]; 3421 u8 vhca_id[0x10]; 3422 3423 u8 reserved_at_20[0xa0]; 3424 3425 u8 cur_alloc_icm[0x20]; 3426 3427 u8 reserved_at_e0[0x120]; 3428 }; 3429 3430 enum { 3431 MLX5_CQ_ERROR_SYNDROME_CQ_OVERRUN = 0x1, 3432 MLX5_CQ_ERROR_SYNDROME_CQ_ACCESS_VIOLATION_ERROR = 0x2, 3433 }; 3434 3435 struct mlx5_ifc_cq_error_bits { 3436 u8 reserved_at_0[0x8]; 3437 u8 cqn[0x18]; 3438 3439 u8 reserved_at_20[0x20]; 3440 3441 u8 reserved_at_40[0x18]; 3442 u8 syndrome[0x8]; 3443 3444 u8 reserved_at_60[0x80]; 3445 }; 3446 3447 struct mlx5_ifc_rdma_page_fault_event_bits { 3448 u8 bytes_committed[0x20]; 3449 3450 u8 r_key[0x20]; 3451 3452 u8 reserved_at_40[0x10]; 3453 u8 packet_len[0x10]; 3454 3455 u8 rdma_op_len[0x20]; 3456 3457 u8 rdma_va[0x40]; 3458 3459 u8 reserved_at_c0[0x5]; 3460 u8 rdma[0x1]; 3461 u8 write[0x1]; 3462 u8 requestor[0x1]; 3463 u8 qp_number[0x18]; 3464 }; 3465 3466 struct mlx5_ifc_wqe_associated_page_fault_event_bits { 3467 u8 bytes_committed[0x20]; 3468 3469 u8 reserved_at_20[0x10]; 3470 u8 wqe_index[0x10]; 3471 3472 u8 reserved_at_40[0x10]; 3473 u8 len[0x10]; 3474 3475 u8 reserved_at_60[0x60]; 3476 3477 u8 reserved_at_c0[0x5]; 3478 u8 rdma[0x1]; 3479 u8 write_read[0x1]; 3480 u8 requestor[0x1]; 3481 u8 qpn[0x18]; 3482 }; 3483 3484 struct mlx5_ifc_qp_events_bits { 3485 u8 reserved_at_0[0xa0]; 3486 3487 u8 type[0x8]; 3488 u8 reserved_at_a8[0x18]; 3489 3490 u8 reserved_at_c0[0x8]; 3491 u8 qpn_rqn_sqn[0x18]; 3492 }; 3493 3494 struct mlx5_ifc_dct_events_bits { 3495 u8 reserved_at_0[0xc0]; 3496 3497 u8 reserved_at_c0[0x8]; 3498 u8 dct_number[0x18]; 3499 }; 3500 3501 struct mlx5_ifc_comp_event_bits { 3502 u8 reserved_at_0[0xc0]; 3503 3504 u8 reserved_at_c0[0x8]; 3505 u8 cq_number[0x18]; 3506 }; 3507 3508 enum { 3509 MLX5_QPC_STATE_RST = 0x0, 3510 MLX5_QPC_STATE_INIT = 0x1, 3511 MLX5_QPC_STATE_RTR = 0x2, 3512 MLX5_QPC_STATE_RTS = 0x3, 3513 MLX5_QPC_STATE_SQER = 0x4, 3514 MLX5_QPC_STATE_ERR = 0x6, 3515 MLX5_QPC_STATE_SQD = 0x7, 3516 MLX5_QPC_STATE_SUSPENDED = 0x9, 3517 }; 3518 3519 enum { 3520 MLX5_QPC_ST_RC = 0x0, 3521 MLX5_QPC_ST_UC = 0x1, 3522 MLX5_QPC_ST_UD = 0x2, 3523 MLX5_QPC_ST_XRC = 0x3, 3524 MLX5_QPC_ST_DCI = 0x5, 3525 MLX5_QPC_ST_QP0 = 0x7, 3526 MLX5_QPC_ST_QP1 = 0x8, 3527 MLX5_QPC_ST_RAW_DATAGRAM = 0x9, 3528 MLX5_QPC_ST_REG_UMR = 0xc, 3529 }; 3530 3531 enum { 3532 MLX5_QPC_PM_STATE_ARMED = 0x0, 3533 MLX5_QPC_PM_STATE_REARM = 0x1, 3534 MLX5_QPC_PM_STATE_RESERVED = 0x2, 3535 MLX5_QPC_PM_STATE_MIGRATED = 0x3, 3536 }; 3537 3538 enum { 3539 MLX5_QPC_OFFLOAD_TYPE_RNDV = 0x1, 3540 }; 3541 3542 enum { 3543 MLX5_QPC_END_PADDING_MODE_SCATTER_AS_IS = 0x0, 3544 MLX5_QPC_END_PADDING_MODE_PAD_TO_CACHE_LINE_ALIGNMENT = 0x1, 3545 }; 3546 3547 enum { 3548 MLX5_QPC_MTU_256_BYTES = 0x1, 3549 MLX5_QPC_MTU_512_BYTES = 0x2, 3550 MLX5_QPC_MTU_1K_BYTES = 0x3, 3551 MLX5_QPC_MTU_2K_BYTES = 0x4, 3552 MLX5_QPC_MTU_4K_BYTES = 0x5, 3553 MLX5_QPC_MTU_RAW_ETHERNET_QP = 0x7, 3554 }; 3555 3556 enum { 3557 MLX5_QPC_ATOMIC_MODE_IB_SPEC = 0x1, 3558 MLX5_QPC_ATOMIC_MODE_ONLY_8B = 0x2, 3559 MLX5_QPC_ATOMIC_MODE_UP_TO_8B = 0x3, 3560 MLX5_QPC_ATOMIC_MODE_UP_TO_16B = 0x4, 3561 MLX5_QPC_ATOMIC_MODE_UP_TO_32B = 0x5, 3562 MLX5_QPC_ATOMIC_MODE_UP_TO_64B = 0x6, 3563 MLX5_QPC_ATOMIC_MODE_UP_TO_128B = 0x7, 3564 MLX5_QPC_ATOMIC_MODE_UP_TO_256B = 0x8, 3565 }; 3566 3567 enum { 3568 MLX5_QPC_CS_REQ_DISABLE = 0x0, 3569 MLX5_QPC_CS_REQ_UP_TO_32B = 0x11, 3570 MLX5_QPC_CS_REQ_UP_TO_64B = 0x22, 3571 }; 3572 3573 enum { 3574 MLX5_QPC_CS_RES_DISABLE = 0x0, 3575 MLX5_QPC_CS_RES_UP_TO_32B = 0x1, 3576 MLX5_QPC_CS_RES_UP_TO_64B = 0x2, 3577 }; 3578 3579 enum { 3580 MLX5_TIMESTAMP_FORMAT_FREE_RUNNING = 0x0, 3581 MLX5_TIMESTAMP_FORMAT_DEFAULT = 0x1, 3582 MLX5_TIMESTAMP_FORMAT_REAL_TIME = 0x2, 3583 }; 3584 3585 struct mlx5_ifc_qpc_bits { 3586 u8 state[0x4]; 3587 u8 lag_tx_port_affinity[0x4]; 3588 u8 st[0x8]; 3589 u8 reserved_at_10[0x2]; 3590 u8 isolate_vl_tc[0x1]; 3591 u8 pm_state[0x2]; 3592 u8 reserved_at_15[0x1]; 3593 u8 req_e2e_credit_mode[0x2]; 3594 u8 offload_type[0x4]; 3595 u8 end_padding_mode[0x2]; 3596 u8 reserved_at_1e[0x2]; 3597 3598 u8 wq_signature[0x1]; 3599 u8 block_lb_mc[0x1]; 3600 u8 atomic_like_write_en[0x1]; 3601 u8 latency_sensitive[0x1]; 3602 u8 reserved_at_24[0x1]; 3603 u8 drain_sigerr[0x1]; 3604 u8 reserved_at_26[0x1]; 3605 u8 dp_ordering_force[0x1]; 3606 u8 pd[0x18]; 3607 3608 u8 mtu[0x3]; 3609 u8 log_msg_max[0x5]; 3610 u8 reserved_at_48[0x1]; 3611 u8 log_rq_size[0x4]; 3612 u8 log_rq_stride[0x3]; 3613 u8 no_sq[0x1]; 3614 u8 log_sq_size[0x4]; 3615 u8 reserved_at_55[0x1]; 3616 u8 retry_mode[0x2]; 3617 u8 ts_format[0x2]; 3618 u8 reserved_at_5a[0x1]; 3619 u8 rlky[0x1]; 3620 u8 ulp_stateless_offload_mode[0x4]; 3621 3622 u8 counter_set_id[0x8]; 3623 u8 uar_page[0x18]; 3624 3625 u8 reserved_at_80[0x8]; 3626 u8 user_index[0x18]; 3627 3628 u8 reserved_at_a0[0x3]; 3629 u8 log_page_size[0x5]; 3630 u8 remote_qpn[0x18]; 3631 3632 struct mlx5_ifc_ads_bits primary_address_path; 3633 3634 struct mlx5_ifc_ads_bits secondary_address_path; 3635 3636 u8 log_ack_req_freq[0x4]; 3637 u8 reserved_at_384[0x4]; 3638 u8 log_sra_max[0x3]; 3639 u8 reserved_at_38b[0x2]; 3640 u8 retry_count[0x3]; 3641 u8 rnr_retry[0x3]; 3642 u8 reserved_at_393[0x1]; 3643 u8 fre[0x1]; 3644 u8 cur_rnr_retry[0x3]; 3645 u8 cur_retry_count[0x3]; 3646 u8 reserved_at_39b[0x5]; 3647 3648 u8 reserved_at_3a0[0x20]; 3649 3650 u8 reserved_at_3c0[0x8]; 3651 u8 next_send_psn[0x18]; 3652 3653 u8 reserved_at_3e0[0x3]; 3654 u8 log_num_dci_stream_channels[0x5]; 3655 u8 cqn_snd[0x18]; 3656 3657 u8 reserved_at_400[0x3]; 3658 u8 log_num_dci_errored_streams[0x5]; 3659 u8 deth_sqpn[0x18]; 3660 3661 u8 reserved_at_420[0x20]; 3662 3663 u8 reserved_at_440[0x8]; 3664 u8 last_acked_psn[0x18]; 3665 3666 u8 reserved_at_460[0x8]; 3667 u8 ssn[0x18]; 3668 3669 u8 reserved_at_480[0x8]; 3670 u8 log_rra_max[0x3]; 3671 u8 reserved_at_48b[0x1]; 3672 u8 atomic_mode[0x4]; 3673 u8 rre[0x1]; 3674 u8 rwe[0x1]; 3675 u8 rae[0x1]; 3676 u8 reserved_at_493[0x1]; 3677 u8 page_offset[0x6]; 3678 u8 reserved_at_49a[0x2]; 3679 u8 dp_ordering_1[0x1]; 3680 u8 cd_slave_receive[0x1]; 3681 u8 cd_slave_send[0x1]; 3682 u8 cd_master[0x1]; 3683 3684 u8 reserved_at_4a0[0x3]; 3685 u8 min_rnr_nak[0x5]; 3686 u8 next_rcv_psn[0x18]; 3687 3688 u8 reserved_at_4c0[0x8]; 3689 u8 xrcd[0x18]; 3690 3691 u8 reserved_at_4e0[0x8]; 3692 u8 cqn_rcv[0x18]; 3693 3694 u8 dbr_addr[0x40]; 3695 3696 u8 q_key[0x20]; 3697 3698 u8 reserved_at_560[0x5]; 3699 u8 rq_type[0x3]; 3700 u8 srqn_rmpn_xrqn[0x18]; 3701 3702 u8 reserved_at_580[0x8]; 3703 u8 rmsn[0x18]; 3704 3705 u8 hw_sq_wqebb_counter[0x10]; 3706 u8 sw_sq_wqebb_counter[0x10]; 3707 3708 u8 hw_rq_counter[0x20]; 3709 3710 u8 sw_rq_counter[0x20]; 3711 3712 u8 reserved_at_600[0x20]; 3713 3714 u8 reserved_at_620[0xf]; 3715 u8 cgs[0x1]; 3716 u8 cs_req[0x8]; 3717 u8 cs_res[0x8]; 3718 3719 u8 dc_access_key[0x40]; 3720 3721 u8 reserved_at_680[0x3]; 3722 u8 dbr_umem_valid[0x1]; 3723 3724 u8 reserved_at_684[0xbc]; 3725 }; 3726 3727 struct mlx5_ifc_roce_addr_layout_bits { 3728 u8 source_l3_address[16][0x8]; 3729 3730 u8 reserved_at_80[0x3]; 3731 u8 vlan_valid[0x1]; 3732 u8 vlan_id[0xc]; 3733 u8 source_mac_47_32[0x10]; 3734 3735 u8 source_mac_31_0[0x20]; 3736 3737 u8 reserved_at_c0[0x14]; 3738 u8 roce_l3_type[0x4]; 3739 u8 roce_version[0x8]; 3740 3741 u8 reserved_at_e0[0x20]; 3742 }; 3743 3744 struct mlx5_ifc_crypto_cap_bits { 3745 u8 reserved_at_0[0x3]; 3746 u8 synchronize_dek[0x1]; 3747 u8 int_kek_manual[0x1]; 3748 u8 int_kek_auto[0x1]; 3749 u8 reserved_at_6[0x1a]; 3750 3751 u8 reserved_at_20[0x3]; 3752 u8 log_dek_max_alloc[0x5]; 3753 u8 reserved_at_28[0x3]; 3754 u8 log_max_num_deks[0x5]; 3755 u8 reserved_at_30[0x10]; 3756 3757 u8 reserved_at_40[0x20]; 3758 3759 u8 reserved_at_60[0x3]; 3760 u8 log_dek_granularity[0x5]; 3761 u8 reserved_at_68[0x3]; 3762 u8 log_max_num_int_kek[0x5]; 3763 u8 sw_wrapped_dek[0x10]; 3764 3765 u8 reserved_at_80[0x780]; 3766 }; 3767 3768 struct mlx5_ifc_shampo_cap_bits { 3769 u8 reserved_at_0[0x3]; 3770 u8 shampo_log_max_reservation_size[0x5]; 3771 u8 reserved_at_8[0x3]; 3772 u8 shampo_log_min_reservation_size[0x5]; 3773 u8 shampo_min_mss_size[0x10]; 3774 3775 u8 shampo_header_split[0x1]; 3776 u8 shampo_header_split_data_merge[0x1]; 3777 u8 reserved_at_22[0x1]; 3778 u8 shampo_log_max_headers_entry_size[0x5]; 3779 u8 reserved_at_28[0x18]; 3780 3781 u8 reserved_at_40[0x7c0]; 3782 }; 3783 3784 union mlx5_ifc_hca_cap_union_bits { 3785 struct mlx5_ifc_cmd_hca_cap_bits cmd_hca_cap; 3786 struct mlx5_ifc_cmd_hca_cap_2_bits cmd_hca_cap_2; 3787 struct mlx5_ifc_odp_cap_bits odp_cap; 3788 struct mlx5_ifc_atomic_caps_bits atomic_caps; 3789 struct mlx5_ifc_roce_cap_bits roce_cap; 3790 struct mlx5_ifc_per_protocol_networking_offload_caps_bits per_protocol_networking_offload_caps; 3791 struct mlx5_ifc_flow_table_nic_cap_bits flow_table_nic_cap; 3792 struct mlx5_ifc_flow_table_eswitch_cap_bits flow_table_eswitch_cap; 3793 struct mlx5_ifc_wqe_based_flow_table_cap_bits wqe_based_flow_table_cap; 3794 struct mlx5_ifc_esw_cap_bits esw_cap; 3795 struct mlx5_ifc_e_switch_cap_bits e_switch_cap; 3796 struct mlx5_ifc_port_selection_cap_bits port_selection_cap; 3797 struct mlx5_ifc_qos_cap_bits qos_cap; 3798 struct mlx5_ifc_debug_cap_bits debug_cap; 3799 struct mlx5_ifc_fpga_cap_bits fpga_cap; 3800 struct mlx5_ifc_tls_cap_bits tls_cap; 3801 struct mlx5_ifc_device_mem_cap_bits device_mem_cap; 3802 struct mlx5_ifc_virtio_emulation_cap_bits virtio_emulation_cap; 3803 struct mlx5_ifc_macsec_cap_bits macsec_cap; 3804 struct mlx5_ifc_crypto_cap_bits crypto_cap; 3805 struct mlx5_ifc_ipsec_cap_bits ipsec_cap; 3806 u8 reserved_at_0[0x8000]; 3807 }; 3808 3809 enum { 3810 MLX5_FLOW_CONTEXT_ACTION_ALLOW = 0x1, 3811 MLX5_FLOW_CONTEXT_ACTION_DROP = 0x2, 3812 MLX5_FLOW_CONTEXT_ACTION_FWD_DEST = 0x4, 3813 MLX5_FLOW_CONTEXT_ACTION_COUNT = 0x8, 3814 MLX5_FLOW_CONTEXT_ACTION_PACKET_REFORMAT = 0x10, 3815 MLX5_FLOW_CONTEXT_ACTION_DECAP = 0x20, 3816 MLX5_FLOW_CONTEXT_ACTION_MOD_HDR = 0x40, 3817 MLX5_FLOW_CONTEXT_ACTION_VLAN_POP = 0x80, 3818 MLX5_FLOW_CONTEXT_ACTION_VLAN_PUSH = 0x100, 3819 MLX5_FLOW_CONTEXT_ACTION_VLAN_POP_2 = 0x400, 3820 MLX5_FLOW_CONTEXT_ACTION_VLAN_PUSH_2 = 0x800, 3821 MLX5_FLOW_CONTEXT_ACTION_CRYPTO_DECRYPT = 0x1000, 3822 MLX5_FLOW_CONTEXT_ACTION_CRYPTO_ENCRYPT = 0x2000, 3823 MLX5_FLOW_CONTEXT_ACTION_EXECUTE_ASO = 0x4000, 3824 }; 3825 3826 enum { 3827 MLX5_FLOW_CONTEXT_FLOW_SOURCE_ANY_VPORT = 0x0, 3828 MLX5_FLOW_CONTEXT_FLOW_SOURCE_UPLINK = 0x1, 3829 MLX5_FLOW_CONTEXT_FLOW_SOURCE_LOCAL_VPORT = 0x2, 3830 }; 3831 3832 enum { 3833 MLX5_FLOW_CONTEXT_ENCRYPT_DECRYPT_TYPE_IPSEC = 0x0, 3834 MLX5_FLOW_CONTEXT_ENCRYPT_DECRYPT_TYPE_MACSEC = 0x1, 3835 }; 3836 3837 struct mlx5_ifc_vlan_bits { 3838 u8 ethtype[0x10]; 3839 u8 prio[0x3]; 3840 u8 cfi[0x1]; 3841 u8 vid[0xc]; 3842 }; 3843 3844 enum { 3845 MLX5_FLOW_METER_COLOR_RED = 0x0, 3846 MLX5_FLOW_METER_COLOR_YELLOW = 0x1, 3847 MLX5_FLOW_METER_COLOR_GREEN = 0x2, 3848 MLX5_FLOW_METER_COLOR_UNDEFINED = 0x3, 3849 }; 3850 3851 enum { 3852 MLX5_EXE_ASO_FLOW_METER = 0x2, 3853 }; 3854 3855 struct mlx5_ifc_exe_aso_ctrl_flow_meter_bits { 3856 u8 return_reg_id[0x4]; 3857 u8 aso_type[0x4]; 3858 u8 reserved_at_8[0x14]; 3859 u8 action[0x1]; 3860 u8 init_color[0x2]; 3861 u8 meter_id[0x1]; 3862 }; 3863 3864 union mlx5_ifc_exe_aso_ctrl { 3865 struct mlx5_ifc_exe_aso_ctrl_flow_meter_bits exe_aso_ctrl_flow_meter; 3866 }; 3867 3868 struct mlx5_ifc_execute_aso_bits { 3869 u8 valid[0x1]; 3870 u8 reserved_at_1[0x7]; 3871 u8 aso_object_id[0x18]; 3872 3873 union mlx5_ifc_exe_aso_ctrl exe_aso_ctrl; 3874 }; 3875 3876 struct mlx5_ifc_flow_context_bits { 3877 struct mlx5_ifc_vlan_bits push_vlan; 3878 3879 u8 group_id[0x20]; 3880 3881 u8 reserved_at_40[0x8]; 3882 u8 flow_tag[0x18]; 3883 3884 u8 reserved_at_60[0x10]; 3885 u8 action[0x10]; 3886 3887 u8 extended_destination[0x1]; 3888 u8 uplink_hairpin_en[0x1]; 3889 u8 flow_source[0x2]; 3890 u8 encrypt_decrypt_type[0x4]; 3891 u8 destination_list_size[0x18]; 3892 3893 u8 reserved_at_a0[0x8]; 3894 u8 flow_counter_list_size[0x18]; 3895 3896 u8 packet_reformat_id[0x20]; 3897 3898 u8 modify_header_id[0x20]; 3899 3900 struct mlx5_ifc_vlan_bits push_vlan_2; 3901 3902 u8 encrypt_decrypt_obj_id[0x20]; 3903 u8 reserved_at_140[0xc0]; 3904 3905 struct mlx5_ifc_fte_match_param_bits match_value; 3906 3907 struct mlx5_ifc_execute_aso_bits execute_aso[4]; 3908 3909 u8 reserved_at_1300[0x500]; 3910 3911 union mlx5_ifc_dest_format_flow_counter_list_auto_bits destination[]; 3912 }; 3913 3914 enum { 3915 MLX5_XRC_SRQC_STATE_GOOD = 0x0, 3916 MLX5_XRC_SRQC_STATE_ERROR = 0x1, 3917 }; 3918 3919 struct mlx5_ifc_xrc_srqc_bits { 3920 u8 state[0x4]; 3921 u8 log_xrc_srq_size[0x4]; 3922 u8 reserved_at_8[0x18]; 3923 3924 u8 wq_signature[0x1]; 3925 u8 cont_srq[0x1]; 3926 u8 reserved_at_22[0x1]; 3927 u8 rlky[0x1]; 3928 u8 basic_cyclic_rcv_wqe[0x1]; 3929 u8 log_rq_stride[0x3]; 3930 u8 xrcd[0x18]; 3931 3932 u8 page_offset[0x6]; 3933 u8 reserved_at_46[0x1]; 3934 u8 dbr_umem_valid[0x1]; 3935 u8 cqn[0x18]; 3936 3937 u8 reserved_at_60[0x20]; 3938 3939 u8 user_index_equal_xrc_srqn[0x1]; 3940 u8 reserved_at_81[0x1]; 3941 u8 log_page_size[0x6]; 3942 u8 user_index[0x18]; 3943 3944 u8 reserved_at_a0[0x20]; 3945 3946 u8 reserved_at_c0[0x8]; 3947 u8 pd[0x18]; 3948 3949 u8 lwm[0x10]; 3950 u8 wqe_cnt[0x10]; 3951 3952 u8 reserved_at_100[0x40]; 3953 3954 u8 db_record_addr_h[0x20]; 3955 3956 u8 db_record_addr_l[0x1e]; 3957 u8 reserved_at_17e[0x2]; 3958 3959 u8 reserved_at_180[0x80]; 3960 }; 3961 3962 struct mlx5_ifc_vnic_diagnostic_statistics_bits { 3963 u8 counter_error_queues[0x20]; 3964 3965 u8 total_error_queues[0x20]; 3966 3967 u8 send_queue_priority_update_flow[0x20]; 3968 3969 u8 reserved_at_60[0x20]; 3970 3971 u8 nic_receive_steering_discard[0x40]; 3972 3973 u8 receive_discard_vport_down[0x40]; 3974 3975 u8 transmit_discard_vport_down[0x40]; 3976 3977 u8 async_eq_overrun[0x20]; 3978 3979 u8 comp_eq_overrun[0x20]; 3980 3981 u8 reserved_at_180[0x20]; 3982 3983 u8 invalid_command[0x20]; 3984 3985 u8 quota_exceeded_command[0x20]; 3986 3987 u8 internal_rq_out_of_buffer[0x20]; 3988 3989 u8 cq_overrun[0x20]; 3990 3991 u8 eth_wqe_too_small[0x20]; 3992 3993 u8 reserved_at_220[0xc0]; 3994 3995 u8 generated_pkt_steering_fail[0x40]; 3996 3997 u8 handled_pkt_steering_fail[0x40]; 3998 3999 u8 reserved_at_360[0xc80]; 4000 }; 4001 4002 struct mlx5_ifc_traffic_counter_bits { 4003 u8 packets[0x40]; 4004 4005 u8 octets[0x40]; 4006 }; 4007 4008 struct mlx5_ifc_tisc_bits { 4009 u8 strict_lag_tx_port_affinity[0x1]; 4010 u8 tls_en[0x1]; 4011 u8 reserved_at_2[0x2]; 4012 u8 lag_tx_port_affinity[0x04]; 4013 4014 u8 reserved_at_8[0x4]; 4015 u8 prio[0x4]; 4016 u8 reserved_at_10[0x10]; 4017 4018 u8 reserved_at_20[0x100]; 4019 4020 u8 reserved_at_120[0x8]; 4021 u8 transport_domain[0x18]; 4022 4023 u8 reserved_at_140[0x8]; 4024 u8 underlay_qpn[0x18]; 4025 4026 u8 reserved_at_160[0x8]; 4027 u8 pd[0x18]; 4028 4029 u8 reserved_at_180[0x380]; 4030 }; 4031 4032 enum { 4033 MLX5_TIRC_DISP_TYPE_DIRECT = 0x0, 4034 MLX5_TIRC_DISP_TYPE_INDIRECT = 0x1, 4035 }; 4036 4037 enum { 4038 MLX5_TIRC_PACKET_MERGE_MASK_IPV4_LRO = BIT(0), 4039 MLX5_TIRC_PACKET_MERGE_MASK_IPV6_LRO = BIT(1), 4040 }; 4041 4042 enum { 4043 MLX5_RX_HASH_FN_NONE = 0x0, 4044 MLX5_RX_HASH_FN_INVERTED_XOR8 = 0x1, 4045 MLX5_RX_HASH_FN_TOEPLITZ = 0x2, 4046 }; 4047 4048 enum { 4049 MLX5_TIRC_SELF_LB_BLOCK_BLOCK_UNICAST = 0x1, 4050 MLX5_TIRC_SELF_LB_BLOCK_BLOCK_MULTICAST = 0x2, 4051 }; 4052 4053 struct mlx5_ifc_tirc_bits { 4054 u8 reserved_at_0[0x20]; 4055 4056 u8 disp_type[0x4]; 4057 u8 tls_en[0x1]; 4058 u8 reserved_at_25[0x1b]; 4059 4060 u8 reserved_at_40[0x40]; 4061 4062 u8 reserved_at_80[0x4]; 4063 u8 lro_timeout_period_usecs[0x10]; 4064 u8 packet_merge_mask[0x4]; 4065 u8 lro_max_ip_payload_size[0x8]; 4066 4067 u8 reserved_at_a0[0x40]; 4068 4069 u8 reserved_at_e0[0x8]; 4070 u8 inline_rqn[0x18]; 4071 4072 u8 rx_hash_symmetric[0x1]; 4073 u8 reserved_at_101[0x1]; 4074 u8 tunneled_offload_en[0x1]; 4075 u8 reserved_at_103[0x5]; 4076 u8 indirect_table[0x18]; 4077 4078 u8 rx_hash_fn[0x4]; 4079 u8 reserved_at_124[0x2]; 4080 u8 self_lb_block[0x2]; 4081 u8 transport_domain[0x18]; 4082 4083 u8 rx_hash_toeplitz_key[10][0x20]; 4084 4085 struct mlx5_ifc_rx_hash_field_select_bits rx_hash_field_selector_outer; 4086 4087 struct mlx5_ifc_rx_hash_field_select_bits rx_hash_field_selector_inner; 4088 4089 u8 reserved_at_2c0[0x4c0]; 4090 }; 4091 4092 enum { 4093 MLX5_SRQC_STATE_GOOD = 0x0, 4094 MLX5_SRQC_STATE_ERROR = 0x1, 4095 }; 4096 4097 struct mlx5_ifc_srqc_bits { 4098 u8 state[0x4]; 4099 u8 log_srq_size[0x4]; 4100 u8 reserved_at_8[0x18]; 4101 4102 u8 wq_signature[0x1]; 4103 u8 cont_srq[0x1]; 4104 u8 reserved_at_22[0x1]; 4105 u8 rlky[0x1]; 4106 u8 reserved_at_24[0x1]; 4107 u8 log_rq_stride[0x3]; 4108 u8 xrcd[0x18]; 4109 4110 u8 page_offset[0x6]; 4111 u8 reserved_at_46[0x2]; 4112 u8 cqn[0x18]; 4113 4114 u8 reserved_at_60[0x20]; 4115 4116 u8 reserved_at_80[0x2]; 4117 u8 log_page_size[0x6]; 4118 u8 reserved_at_88[0x18]; 4119 4120 u8 reserved_at_a0[0x20]; 4121 4122 u8 reserved_at_c0[0x8]; 4123 u8 pd[0x18]; 4124 4125 u8 lwm[0x10]; 4126 u8 wqe_cnt[0x10]; 4127 4128 u8 reserved_at_100[0x40]; 4129 4130 u8 dbr_addr[0x40]; 4131 4132 u8 reserved_at_180[0x80]; 4133 }; 4134 4135 enum { 4136 MLX5_SQC_STATE_RST = 0x0, 4137 MLX5_SQC_STATE_RDY = 0x1, 4138 MLX5_SQC_STATE_ERR = 0x3, 4139 }; 4140 4141 struct mlx5_ifc_sqc_bits { 4142 u8 rlky[0x1]; 4143 u8 cd_master[0x1]; 4144 u8 fre[0x1]; 4145 u8 flush_in_error_en[0x1]; 4146 u8 allow_multi_pkt_send_wqe[0x1]; 4147 u8 min_wqe_inline_mode[0x3]; 4148 u8 state[0x4]; 4149 u8 reg_umr[0x1]; 4150 u8 allow_swp[0x1]; 4151 u8 hairpin[0x1]; 4152 u8 non_wire[0x1]; 4153 u8 reserved_at_10[0xa]; 4154 u8 ts_format[0x2]; 4155 u8 reserved_at_1c[0x4]; 4156 4157 u8 reserved_at_20[0x8]; 4158 u8 user_index[0x18]; 4159 4160 u8 reserved_at_40[0x8]; 4161 u8 cqn[0x18]; 4162 4163 u8 reserved_at_60[0x8]; 4164 u8 hairpin_peer_rq[0x18]; 4165 4166 u8 reserved_at_80[0x10]; 4167 u8 hairpin_peer_vhca[0x10]; 4168 4169 u8 reserved_at_a0[0x20]; 4170 4171 u8 reserved_at_c0[0x8]; 4172 u8 ts_cqe_to_dest_cqn[0x18]; 4173 4174 u8 reserved_at_e0[0x10]; 4175 u8 packet_pacing_rate_limit_index[0x10]; 4176 u8 tis_lst_sz[0x10]; 4177 u8 qos_queue_group_id[0x10]; 4178 4179 u8 reserved_at_120[0x40]; 4180 4181 u8 reserved_at_160[0x8]; 4182 u8 tis_num_0[0x18]; 4183 4184 struct mlx5_ifc_wq_bits wq; 4185 }; 4186 4187 enum { 4188 SCHEDULING_CONTEXT_ELEMENT_TYPE_TSAR = 0x0, 4189 SCHEDULING_CONTEXT_ELEMENT_TYPE_VPORT = 0x1, 4190 SCHEDULING_CONTEXT_ELEMENT_TYPE_VPORT_TC = 0x2, 4191 SCHEDULING_CONTEXT_ELEMENT_TYPE_PARA_VPORT_TC = 0x3, 4192 SCHEDULING_CONTEXT_ELEMENT_TYPE_QUEUE_GROUP = 0x4, 4193 SCHEDULING_CONTEXT_ELEMENT_TYPE_RATE_LIMIT = 0x5, 4194 }; 4195 4196 enum { 4197 ELEMENT_TYPE_CAP_MASK_TSAR = 1 << 0, 4198 ELEMENT_TYPE_CAP_MASK_VPORT = 1 << 1, 4199 ELEMENT_TYPE_CAP_MASK_VPORT_TC = 1 << 2, 4200 ELEMENT_TYPE_CAP_MASK_PARA_VPORT_TC = 1 << 3, 4201 ELEMENT_TYPE_CAP_MASK_QUEUE_GROUP = 1 << 4, 4202 ELEMENT_TYPE_CAP_MASK_RATE_LIMIT = 1 << 5, 4203 }; 4204 4205 enum { 4206 TSAR_ELEMENT_TSAR_TYPE_DWRR = 0x0, 4207 TSAR_ELEMENT_TSAR_TYPE_ROUND_ROBIN = 0x1, 4208 TSAR_ELEMENT_TSAR_TYPE_ETS = 0x2, 4209 TSAR_ELEMENT_TSAR_TYPE_TC_ARB = 0x3, 4210 }; 4211 4212 enum { 4213 TSAR_TYPE_CAP_MASK_DWRR = 1 << 0, 4214 TSAR_TYPE_CAP_MASK_ROUND_ROBIN = 1 << 1, 4215 TSAR_TYPE_CAP_MASK_ETS = 1 << 2, 4216 TSAR_TYPE_CAP_MASK_TC_ARB = 1 << 3, 4217 }; 4218 4219 struct mlx5_ifc_tsar_element_bits { 4220 u8 traffic_class[0x4]; 4221 u8 reserved_at_4[0x4]; 4222 u8 tsar_type[0x8]; 4223 u8 reserved_at_10[0x10]; 4224 }; 4225 4226 struct mlx5_ifc_vport_element_bits { 4227 u8 reserved_at_0[0x4]; 4228 u8 eswitch_owner_vhca_id_valid[0x1]; 4229 u8 eswitch_owner_vhca_id[0xb]; 4230 u8 vport_number[0x10]; 4231 }; 4232 4233 struct mlx5_ifc_vport_tc_element_bits { 4234 u8 traffic_class[0x4]; 4235 u8 eswitch_owner_vhca_id_valid[0x1]; 4236 u8 eswitch_owner_vhca_id[0xb]; 4237 u8 vport_number[0x10]; 4238 }; 4239 4240 union mlx5_ifc_element_attributes_bits { 4241 struct mlx5_ifc_tsar_element_bits tsar; 4242 struct mlx5_ifc_vport_element_bits vport; 4243 struct mlx5_ifc_vport_tc_element_bits vport_tc; 4244 u8 reserved_at_0[0x20]; 4245 }; 4246 4247 struct mlx5_ifc_scheduling_context_bits { 4248 u8 element_type[0x8]; 4249 u8 reserved_at_8[0x18]; 4250 4251 union mlx5_ifc_element_attributes_bits element_attributes; 4252 4253 u8 parent_element_id[0x20]; 4254 4255 u8 reserved_at_60[0x40]; 4256 4257 u8 bw_share[0x20]; 4258 4259 u8 max_average_bw[0x20]; 4260 4261 u8 max_bw_obj_id[0x20]; 4262 4263 u8 reserved_at_100[0x100]; 4264 }; 4265 4266 struct mlx5_ifc_rqtc_bits { 4267 u8 reserved_at_0[0xa0]; 4268 4269 u8 reserved_at_a0[0x5]; 4270 u8 list_q_type[0x3]; 4271 u8 reserved_at_a8[0x8]; 4272 u8 rqt_max_size[0x10]; 4273 4274 u8 rq_vhca_id_format[0x1]; 4275 u8 reserved_at_c1[0xf]; 4276 u8 rqt_actual_size[0x10]; 4277 4278 u8 reserved_at_e0[0x6a0]; 4279 4280 union { 4281 DECLARE_FLEX_ARRAY(struct mlx5_ifc_rq_num_bits, rq_num); 4282 DECLARE_FLEX_ARRAY(struct mlx5_ifc_rq_vhca_bits, rq_vhca); 4283 }; 4284 }; 4285 4286 enum { 4287 MLX5_RQC_MEM_RQ_TYPE_MEMORY_RQ_INLINE = 0x0, 4288 MLX5_RQC_MEM_RQ_TYPE_MEMORY_RQ_RMP = 0x1, 4289 }; 4290 4291 enum { 4292 MLX5_RQC_STATE_RST = 0x0, 4293 MLX5_RQC_STATE_RDY = 0x1, 4294 MLX5_RQC_STATE_ERR = 0x3, 4295 }; 4296 4297 enum { 4298 MLX5_RQC_SHAMPO_NO_MATCH_ALIGNMENT_GRANULARITY_BYTE = 0x0, 4299 MLX5_RQC_SHAMPO_NO_MATCH_ALIGNMENT_GRANULARITY_STRIDE = 0x1, 4300 MLX5_RQC_SHAMPO_NO_MATCH_ALIGNMENT_GRANULARITY_PAGE = 0x2, 4301 }; 4302 4303 enum { 4304 MLX5_RQC_SHAMPO_MATCH_CRITERIA_TYPE_NO_MATCH = 0x0, 4305 MLX5_RQC_SHAMPO_MATCH_CRITERIA_TYPE_EXTENDED = 0x1, 4306 MLX5_RQC_SHAMPO_MATCH_CRITERIA_TYPE_FIVE_TUPLE = 0x2, 4307 }; 4308 4309 struct mlx5_ifc_rqc_bits { 4310 u8 rlky[0x1]; 4311 u8 delay_drop_en[0x1]; 4312 u8 scatter_fcs[0x1]; 4313 u8 vsd[0x1]; 4314 u8 mem_rq_type[0x4]; 4315 u8 state[0x4]; 4316 u8 reserved_at_c[0x1]; 4317 u8 flush_in_error_en[0x1]; 4318 u8 hairpin[0x1]; 4319 u8 reserved_at_f[0xb]; 4320 u8 ts_format[0x2]; 4321 u8 reserved_at_1c[0x4]; 4322 4323 u8 reserved_at_20[0x8]; 4324 u8 user_index[0x18]; 4325 4326 u8 reserved_at_40[0x8]; 4327 u8 cqn[0x18]; 4328 4329 u8 counter_set_id[0x8]; 4330 u8 reserved_at_68[0x18]; 4331 4332 u8 reserved_at_80[0x8]; 4333 u8 rmpn[0x18]; 4334 4335 u8 reserved_at_a0[0x8]; 4336 u8 hairpin_peer_sq[0x18]; 4337 4338 u8 reserved_at_c0[0x10]; 4339 u8 hairpin_peer_vhca[0x10]; 4340 4341 u8 reserved_at_e0[0x46]; 4342 u8 shampo_no_match_alignment_granularity[0x2]; 4343 u8 reserved_at_128[0x6]; 4344 u8 shampo_match_criteria_type[0x2]; 4345 u8 reservation_timeout[0x10]; 4346 4347 u8 reserved_at_140[0x40]; 4348 4349 struct mlx5_ifc_wq_bits wq; 4350 }; 4351 4352 enum { 4353 MLX5_RMPC_STATE_RDY = 0x1, 4354 MLX5_RMPC_STATE_ERR = 0x3, 4355 }; 4356 4357 struct mlx5_ifc_rmpc_bits { 4358 u8 reserved_at_0[0x8]; 4359 u8 state[0x4]; 4360 u8 reserved_at_c[0x14]; 4361 4362 u8 basic_cyclic_rcv_wqe[0x1]; 4363 u8 reserved_at_21[0x1f]; 4364 4365 u8 reserved_at_40[0x140]; 4366 4367 struct mlx5_ifc_wq_bits wq; 4368 }; 4369 4370 enum { 4371 VHCA_ID_TYPE_HW = 0, 4372 VHCA_ID_TYPE_SW = 1, 4373 }; 4374 4375 struct mlx5_ifc_nic_vport_context_bits { 4376 u8 reserved_at_0[0x5]; 4377 u8 min_wqe_inline_mode[0x3]; 4378 u8 reserved_at_8[0x15]; 4379 u8 disable_mc_local_lb[0x1]; 4380 u8 disable_uc_local_lb[0x1]; 4381 u8 roce_en[0x1]; 4382 4383 u8 arm_change_event[0x1]; 4384 u8 reserved_at_21[0x1a]; 4385 u8 event_on_mtu[0x1]; 4386 u8 event_on_promisc_change[0x1]; 4387 u8 event_on_vlan_change[0x1]; 4388 u8 event_on_mc_address_change[0x1]; 4389 u8 event_on_uc_address_change[0x1]; 4390 4391 u8 vhca_id_type[0x1]; 4392 u8 reserved_at_41[0xb]; 4393 u8 affiliation_criteria[0x4]; 4394 u8 affiliated_vhca_id[0x10]; 4395 4396 u8 reserved_at_60[0xa0]; 4397 4398 u8 reserved_at_100[0x1]; 4399 u8 sd_group[0x3]; 4400 u8 reserved_at_104[0x1c]; 4401 4402 u8 reserved_at_120[0x10]; 4403 u8 mtu[0x10]; 4404 4405 u8 system_image_guid[0x40]; 4406 u8 port_guid[0x40]; 4407 u8 node_guid[0x40]; 4408 4409 u8 reserved_at_200[0x140]; 4410 u8 qkey_violation_counter[0x10]; 4411 u8 reserved_at_350[0x430]; 4412 4413 u8 promisc_uc[0x1]; 4414 u8 promisc_mc[0x1]; 4415 u8 promisc_all[0x1]; 4416 u8 reserved_at_783[0x2]; 4417 u8 allowed_list_type[0x3]; 4418 u8 reserved_at_788[0xc]; 4419 u8 allowed_list_size[0xc]; 4420 4421 struct mlx5_ifc_mac_address_layout_bits permanent_address; 4422 4423 u8 reserved_at_7e0[0x20]; 4424 4425 u8 current_uc_mac_address[][0x40]; 4426 }; 4427 4428 enum { 4429 MLX5_MKC_ACCESS_MODE_PA = 0x0, 4430 MLX5_MKC_ACCESS_MODE_MTT = 0x1, 4431 MLX5_MKC_ACCESS_MODE_KLMS = 0x2, 4432 MLX5_MKC_ACCESS_MODE_KSM = 0x3, 4433 MLX5_MKC_ACCESS_MODE_SW_ICM = 0x4, 4434 MLX5_MKC_ACCESS_MODE_MEMIC = 0x5, 4435 MLX5_MKC_ACCESS_MODE_CROSSING = 0x6, 4436 }; 4437 4438 enum { 4439 MLX5_MKC_PCIE_TPH_NO_STEERING_TAG_INDEX = 0, 4440 }; 4441 4442 struct mlx5_ifc_mkc_bits { 4443 u8 reserved_at_0[0x1]; 4444 u8 free[0x1]; 4445 u8 reserved_at_2[0x1]; 4446 u8 access_mode_4_2[0x3]; 4447 u8 reserved_at_6[0x7]; 4448 u8 relaxed_ordering_write[0x1]; 4449 u8 reserved_at_e[0x1]; 4450 u8 small_fence_on_rdma_read_response[0x1]; 4451 u8 umr_en[0x1]; 4452 u8 a[0x1]; 4453 u8 rw[0x1]; 4454 u8 rr[0x1]; 4455 u8 lw[0x1]; 4456 u8 lr[0x1]; 4457 u8 access_mode_1_0[0x2]; 4458 u8 reserved_at_18[0x2]; 4459 u8 ma_translation_mode[0x2]; 4460 u8 reserved_at_1c[0x4]; 4461 4462 u8 qpn[0x18]; 4463 u8 mkey_7_0[0x8]; 4464 4465 u8 reserved_at_40[0x20]; 4466 4467 u8 length64[0x1]; 4468 u8 bsf_en[0x1]; 4469 u8 sync_umr[0x1]; 4470 u8 reserved_at_63[0x2]; 4471 u8 expected_sigerr_count[0x1]; 4472 u8 reserved_at_66[0x1]; 4473 u8 en_rinval[0x1]; 4474 u8 pd[0x18]; 4475 4476 u8 start_addr[0x40]; 4477 4478 u8 len[0x40]; 4479 4480 u8 bsf_octword_size[0x20]; 4481 4482 u8 reserved_at_120[0x60]; 4483 4484 u8 crossing_target_vhca_id[0x10]; 4485 u8 reserved_at_190[0x10]; 4486 4487 u8 translations_octword_size[0x20]; 4488 4489 u8 reserved_at_1c0[0x19]; 4490 u8 relaxed_ordering_read[0x1]; 4491 u8 log_page_size[0x6]; 4492 4493 u8 reserved_at_1e0[0x5]; 4494 u8 pcie_tph_en[0x1]; 4495 u8 pcie_tph_ph[0x2]; 4496 u8 pcie_tph_steering_tag_index[0x8]; 4497 u8 reserved_at_1f0[0x10]; 4498 }; 4499 4500 struct mlx5_ifc_pkey_bits { 4501 u8 reserved_at_0[0x10]; 4502 u8 pkey[0x10]; 4503 }; 4504 4505 struct mlx5_ifc_array128_auto_bits { 4506 u8 array128_auto[16][0x8]; 4507 }; 4508 4509 struct mlx5_ifc_hca_vport_context_bits { 4510 u8 field_select[0x20]; 4511 4512 u8 reserved_at_20[0xe0]; 4513 4514 u8 sm_virt_aware[0x1]; 4515 u8 has_smi[0x1]; 4516 u8 has_raw[0x1]; 4517 u8 grh_required[0x1]; 4518 u8 reserved_at_104[0x4]; 4519 u8 num_port_plane[0x8]; 4520 u8 port_physical_state[0x4]; 4521 u8 vport_state_policy[0x4]; 4522 u8 port_state[0x4]; 4523 u8 vport_state[0x4]; 4524 4525 u8 reserved_at_120[0x20]; 4526 4527 u8 system_image_guid[0x40]; 4528 4529 u8 port_guid[0x40]; 4530 4531 u8 node_guid[0x40]; 4532 4533 u8 cap_mask1[0x20]; 4534 4535 u8 cap_mask1_field_select[0x20]; 4536 4537 u8 cap_mask2[0x20]; 4538 4539 u8 cap_mask2_field_select[0x20]; 4540 4541 u8 reserved_at_280[0x80]; 4542 4543 u8 lid[0x10]; 4544 u8 reserved_at_310[0x4]; 4545 u8 init_type_reply[0x4]; 4546 u8 lmc[0x3]; 4547 u8 subnet_timeout[0x5]; 4548 4549 u8 sm_lid[0x10]; 4550 u8 sm_sl[0x4]; 4551 u8 reserved_at_334[0xc]; 4552 4553 u8 qkey_violation_counter[0x10]; 4554 u8 pkey_violation_counter[0x10]; 4555 4556 u8 reserved_at_360[0xca0]; 4557 }; 4558 4559 struct mlx5_ifc_esw_vport_context_bits { 4560 u8 fdb_to_vport_reg_c[0x1]; 4561 u8 reserved_at_1[0x2]; 4562 u8 vport_svlan_strip[0x1]; 4563 u8 vport_cvlan_strip[0x1]; 4564 u8 vport_svlan_insert[0x1]; 4565 u8 vport_cvlan_insert[0x2]; 4566 u8 fdb_to_vport_reg_c_id[0x8]; 4567 u8 reserved_at_10[0x10]; 4568 4569 u8 reserved_at_20[0x20]; 4570 4571 u8 svlan_cfi[0x1]; 4572 u8 svlan_pcp[0x3]; 4573 u8 svlan_id[0xc]; 4574 u8 cvlan_cfi[0x1]; 4575 u8 cvlan_pcp[0x3]; 4576 u8 cvlan_id[0xc]; 4577 4578 u8 reserved_at_60[0x720]; 4579 4580 u8 sw_steering_vport_icm_address_rx[0x40]; 4581 4582 u8 sw_steering_vport_icm_address_tx[0x40]; 4583 }; 4584 4585 enum { 4586 MLX5_EQC_STATUS_OK = 0x0, 4587 MLX5_EQC_STATUS_EQ_WRITE_FAILURE = 0xa, 4588 }; 4589 4590 enum { 4591 MLX5_EQC_ST_ARMED = 0x9, 4592 MLX5_EQC_ST_FIRED = 0xa, 4593 }; 4594 4595 struct mlx5_ifc_eqc_bits { 4596 u8 status[0x4]; 4597 u8 reserved_at_4[0x9]; 4598 u8 ec[0x1]; 4599 u8 oi[0x1]; 4600 u8 reserved_at_f[0x5]; 4601 u8 st[0x4]; 4602 u8 reserved_at_18[0x8]; 4603 4604 u8 reserved_at_20[0x20]; 4605 4606 u8 reserved_at_40[0x14]; 4607 u8 page_offset[0x6]; 4608 u8 reserved_at_5a[0x6]; 4609 4610 u8 reserved_at_60[0x3]; 4611 u8 log_eq_size[0x5]; 4612 u8 uar_page[0x18]; 4613 4614 u8 reserved_at_80[0x20]; 4615 4616 u8 reserved_at_a0[0x14]; 4617 u8 intr[0xc]; 4618 4619 u8 reserved_at_c0[0x3]; 4620 u8 log_page_size[0x5]; 4621 u8 reserved_at_c8[0x18]; 4622 4623 u8 reserved_at_e0[0x60]; 4624 4625 u8 reserved_at_140[0x8]; 4626 u8 consumer_counter[0x18]; 4627 4628 u8 reserved_at_160[0x8]; 4629 u8 producer_counter[0x18]; 4630 4631 u8 reserved_at_180[0x80]; 4632 }; 4633 4634 enum { 4635 MLX5_DCTC_STATE_ACTIVE = 0x0, 4636 MLX5_DCTC_STATE_DRAINING = 0x1, 4637 MLX5_DCTC_STATE_DRAINED = 0x2, 4638 }; 4639 4640 enum { 4641 MLX5_DCTC_CS_RES_DISABLE = 0x0, 4642 MLX5_DCTC_CS_RES_NA = 0x1, 4643 MLX5_DCTC_CS_RES_UP_TO_64B = 0x2, 4644 }; 4645 4646 enum { 4647 MLX5_DCTC_MTU_256_BYTES = 0x1, 4648 MLX5_DCTC_MTU_512_BYTES = 0x2, 4649 MLX5_DCTC_MTU_1K_BYTES = 0x3, 4650 MLX5_DCTC_MTU_2K_BYTES = 0x4, 4651 MLX5_DCTC_MTU_4K_BYTES = 0x5, 4652 }; 4653 4654 struct mlx5_ifc_dctc_bits { 4655 u8 reserved_at_0[0x4]; 4656 u8 state[0x4]; 4657 u8 reserved_at_8[0x18]; 4658 4659 u8 reserved_at_20[0x7]; 4660 u8 dp_ordering_force[0x1]; 4661 u8 user_index[0x18]; 4662 4663 u8 reserved_at_40[0x8]; 4664 u8 cqn[0x18]; 4665 4666 u8 counter_set_id[0x8]; 4667 u8 atomic_mode[0x4]; 4668 u8 rre[0x1]; 4669 u8 rwe[0x1]; 4670 u8 rae[0x1]; 4671 u8 atomic_like_write_en[0x1]; 4672 u8 latency_sensitive[0x1]; 4673 u8 rlky[0x1]; 4674 u8 free_ar[0x1]; 4675 u8 reserved_at_73[0x1]; 4676 u8 dp_ordering_1[0x1]; 4677 u8 reserved_at_75[0xb]; 4678 4679 u8 reserved_at_80[0x8]; 4680 u8 cs_res[0x8]; 4681 u8 reserved_at_90[0x3]; 4682 u8 min_rnr_nak[0x5]; 4683 u8 reserved_at_98[0x8]; 4684 4685 u8 reserved_at_a0[0x8]; 4686 u8 srqn_xrqn[0x18]; 4687 4688 u8 reserved_at_c0[0x8]; 4689 u8 pd[0x18]; 4690 4691 u8 tclass[0x8]; 4692 u8 reserved_at_e8[0x4]; 4693 u8 flow_label[0x14]; 4694 4695 u8 dc_access_key[0x40]; 4696 4697 u8 reserved_at_140[0x5]; 4698 u8 mtu[0x3]; 4699 u8 port[0x8]; 4700 u8 pkey_index[0x10]; 4701 4702 u8 reserved_at_160[0x8]; 4703 u8 my_addr_index[0x8]; 4704 u8 reserved_at_170[0x8]; 4705 u8 hop_limit[0x8]; 4706 4707 u8 dc_access_key_violation_count[0x20]; 4708 4709 u8 reserved_at_1a0[0x14]; 4710 u8 dei_cfi[0x1]; 4711 u8 eth_prio[0x3]; 4712 u8 ecn[0x2]; 4713 u8 dscp[0x6]; 4714 4715 u8 reserved_at_1c0[0x20]; 4716 u8 ece[0x20]; 4717 }; 4718 4719 enum { 4720 MLX5_CQC_STATUS_OK = 0x0, 4721 MLX5_CQC_STATUS_CQ_OVERFLOW = 0x9, 4722 MLX5_CQC_STATUS_CQ_WRITE_FAIL = 0xa, 4723 }; 4724 4725 enum { 4726 MLX5_CQC_CQE_SZ_64_BYTES = 0x0, 4727 MLX5_CQC_CQE_SZ_128_BYTES = 0x1, 4728 }; 4729 4730 enum { 4731 MLX5_CQC_ST_SOLICITED_NOTIFICATION_REQUEST_ARMED = 0x6, 4732 MLX5_CQC_ST_NOTIFICATION_REQUEST_ARMED = 0x9, 4733 MLX5_CQC_ST_FIRED = 0xa, 4734 }; 4735 4736 enum mlx5_cq_period_mode { 4737 MLX5_CQ_PERIOD_MODE_START_FROM_EQE = 0x0, 4738 MLX5_CQ_PERIOD_MODE_START_FROM_CQE = 0x1, 4739 MLX5_CQ_PERIOD_NUM_MODES, 4740 }; 4741 4742 struct mlx5_ifc_cqc_bits { 4743 u8 status[0x4]; 4744 u8 reserved_at_4[0x2]; 4745 u8 dbr_umem_valid[0x1]; 4746 u8 apu_cq[0x1]; 4747 u8 cqe_sz[0x3]; 4748 u8 cc[0x1]; 4749 u8 reserved_at_c[0x1]; 4750 u8 scqe_break_moderation_en[0x1]; 4751 u8 oi[0x1]; 4752 u8 cq_period_mode[0x2]; 4753 u8 cqe_comp_en[0x1]; 4754 u8 mini_cqe_res_format[0x2]; 4755 u8 st[0x4]; 4756 u8 reserved_at_18[0x6]; 4757 u8 cqe_compression_layout[0x2]; 4758 4759 u8 reserved_at_20[0x20]; 4760 4761 u8 reserved_at_40[0x14]; 4762 u8 page_offset[0x6]; 4763 u8 reserved_at_5a[0x6]; 4764 4765 u8 reserved_at_60[0x3]; 4766 u8 log_cq_size[0x5]; 4767 u8 uar_page[0x18]; 4768 4769 u8 reserved_at_80[0x4]; 4770 u8 cq_period[0xc]; 4771 u8 cq_max_count[0x10]; 4772 4773 u8 c_eqn_or_apu_element[0x20]; 4774 4775 u8 reserved_at_c0[0x3]; 4776 u8 log_page_size[0x5]; 4777 u8 reserved_at_c8[0x18]; 4778 4779 u8 reserved_at_e0[0x20]; 4780 4781 u8 reserved_at_100[0x8]; 4782 u8 last_notified_index[0x18]; 4783 4784 u8 reserved_at_120[0x8]; 4785 u8 last_solicit_index[0x18]; 4786 4787 u8 reserved_at_140[0x8]; 4788 u8 consumer_counter[0x18]; 4789 4790 u8 reserved_at_160[0x8]; 4791 u8 producer_counter[0x18]; 4792 4793 u8 reserved_at_180[0x40]; 4794 4795 u8 dbr_addr[0x40]; 4796 }; 4797 4798 union mlx5_ifc_cong_control_roce_ecn_auto_bits { 4799 struct mlx5_ifc_cong_control_802_1qau_rp_bits cong_control_802_1qau_rp; 4800 struct mlx5_ifc_cong_control_r_roce_ecn_rp_bits cong_control_r_roce_ecn_rp; 4801 struct mlx5_ifc_cong_control_r_roce_ecn_np_bits cong_control_r_roce_ecn_np; 4802 struct mlx5_ifc_cong_control_r_roce_general_bits cong_control_r_roce_general; 4803 u8 reserved_at_0[0x800]; 4804 }; 4805 4806 struct mlx5_ifc_query_adapter_param_block_bits { 4807 u8 reserved_at_0[0xc0]; 4808 4809 u8 reserved_at_c0[0x8]; 4810 u8 ieee_vendor_id[0x18]; 4811 4812 u8 reserved_at_e0[0x10]; 4813 u8 vsd_vendor_id[0x10]; 4814 4815 u8 vsd[208][0x8]; 4816 4817 u8 vsd_contd_psid[16][0x8]; 4818 }; 4819 4820 enum { 4821 MLX5_XRQC_STATE_GOOD = 0x0, 4822 MLX5_XRQC_STATE_ERROR = 0x1, 4823 }; 4824 4825 enum { 4826 MLX5_XRQC_TOPOLOGY_NO_SPECIAL_TOPOLOGY = 0x0, 4827 MLX5_XRQC_TOPOLOGY_TAG_MATCHING = 0x1, 4828 }; 4829 4830 enum { 4831 MLX5_XRQC_OFFLOAD_RNDV = 0x1, 4832 }; 4833 4834 struct mlx5_ifc_tag_matching_topology_context_bits { 4835 u8 log_matching_list_sz[0x4]; 4836 u8 reserved_at_4[0xc]; 4837 u8 append_next_index[0x10]; 4838 4839 u8 sw_phase_cnt[0x10]; 4840 u8 hw_phase_cnt[0x10]; 4841 4842 u8 reserved_at_40[0x40]; 4843 }; 4844 4845 struct mlx5_ifc_xrqc_bits { 4846 u8 state[0x4]; 4847 u8 rlkey[0x1]; 4848 u8 reserved_at_5[0xf]; 4849 u8 topology[0x4]; 4850 u8 reserved_at_18[0x4]; 4851 u8 offload[0x4]; 4852 4853 u8 reserved_at_20[0x8]; 4854 u8 user_index[0x18]; 4855 4856 u8 reserved_at_40[0x8]; 4857 u8 cqn[0x18]; 4858 4859 u8 reserved_at_60[0xa0]; 4860 4861 struct mlx5_ifc_tag_matching_topology_context_bits tag_matching_topology_context; 4862 4863 u8 reserved_at_180[0x280]; 4864 4865 struct mlx5_ifc_wq_bits wq; 4866 }; 4867 4868 union mlx5_ifc_modify_field_select_resize_field_select_auto_bits { 4869 struct mlx5_ifc_modify_field_select_bits modify_field_select; 4870 struct mlx5_ifc_resize_field_select_bits resize_field_select; 4871 u8 reserved_at_0[0x20]; 4872 }; 4873 4874 union mlx5_ifc_field_select_802_1_r_roce_auto_bits { 4875 struct mlx5_ifc_field_select_802_1qau_rp_bits field_select_802_1qau_rp; 4876 struct mlx5_ifc_field_select_r_roce_rp_bits field_select_r_roce_rp; 4877 struct mlx5_ifc_field_select_r_roce_np_bits field_select_r_roce_np; 4878 u8 reserved_at_0[0x20]; 4879 }; 4880 4881 union mlx5_ifc_eth_cntrs_grp_data_layout_auto_bits { 4882 struct mlx5_ifc_eth_802_3_cntrs_grp_data_layout_bits eth_802_3_cntrs_grp_data_layout; 4883 struct mlx5_ifc_eth_2863_cntrs_grp_data_layout_bits eth_2863_cntrs_grp_data_layout; 4884 struct mlx5_ifc_eth_2819_cntrs_grp_data_layout_bits eth_2819_cntrs_grp_data_layout; 4885 struct mlx5_ifc_eth_3635_cntrs_grp_data_layout_bits eth_3635_cntrs_grp_data_layout; 4886 struct mlx5_ifc_eth_extended_cntrs_grp_data_layout_bits eth_extended_cntrs_grp_data_layout; 4887 struct mlx5_ifc_eth_per_prio_grp_data_layout_bits eth_per_prio_grp_data_layout; 4888 struct mlx5_ifc_eth_per_tc_prio_grp_data_layout_bits eth_per_tc_prio_grp_data_layout; 4889 struct mlx5_ifc_eth_per_tc_congest_prio_grp_data_layout_bits eth_per_tc_congest_prio_grp_data_layout; 4890 struct mlx5_ifc_ib_port_cntrs_grp_data_layout_bits ib_port_cntrs_grp_data_layout; 4891 struct mlx5_ifc_ib_ext_port_cntrs_grp_data_layout_bits ib_ext_port_cntrs_grp_data_layout; 4892 struct mlx5_ifc_phys_layer_cntrs_bits phys_layer_cntrs; 4893 struct mlx5_ifc_phys_layer_statistical_cntrs_bits phys_layer_statistical_cntrs; 4894 struct mlx5_ifc_phys_layer_recovery_cntrs_bits phys_layer_recovery_cntrs; 4895 u8 reserved_at_0[0x7c0]; 4896 }; 4897 4898 union mlx5_ifc_pcie_cntrs_grp_data_layout_auto_bits { 4899 struct mlx5_ifc_pcie_perf_cntrs_grp_data_layout_bits pcie_perf_cntrs_grp_data_layout; 4900 u8 reserved_at_0[0x7c0]; 4901 }; 4902 4903 union mlx5_ifc_event_auto_bits { 4904 struct mlx5_ifc_comp_event_bits comp_event; 4905 struct mlx5_ifc_dct_events_bits dct_events; 4906 struct mlx5_ifc_qp_events_bits qp_events; 4907 struct mlx5_ifc_wqe_associated_page_fault_event_bits wqe_associated_page_fault_event; 4908 struct mlx5_ifc_rdma_page_fault_event_bits rdma_page_fault_event; 4909 struct mlx5_ifc_cq_error_bits cq_error; 4910 struct mlx5_ifc_dropped_packet_logged_bits dropped_packet_logged; 4911 struct mlx5_ifc_port_state_change_event_bits port_state_change_event; 4912 struct mlx5_ifc_gpio_event_bits gpio_event; 4913 struct mlx5_ifc_db_bf_congestion_event_bits db_bf_congestion_event; 4914 struct mlx5_ifc_stall_vl_event_bits stall_vl_event; 4915 struct mlx5_ifc_cmd_inter_comp_event_bits cmd_inter_comp_event; 4916 u8 reserved_at_0[0xe0]; 4917 }; 4918 4919 struct mlx5_ifc_health_buffer_bits { 4920 u8 reserved_at_0[0x100]; 4921 4922 u8 assert_existptr[0x20]; 4923 4924 u8 assert_callra[0x20]; 4925 4926 u8 reserved_at_140[0x20]; 4927 4928 u8 time[0x20]; 4929 4930 u8 fw_version[0x20]; 4931 4932 u8 hw_id[0x20]; 4933 4934 u8 rfr[0x1]; 4935 u8 reserved_at_1c1[0x3]; 4936 u8 valid[0x1]; 4937 u8 severity[0x3]; 4938 u8 reserved_at_1c8[0x18]; 4939 4940 u8 irisc_index[0x8]; 4941 u8 synd[0x8]; 4942 u8 ext_synd[0x10]; 4943 }; 4944 4945 struct mlx5_ifc_register_loopback_control_bits { 4946 u8 no_lb[0x1]; 4947 u8 reserved_at_1[0x7]; 4948 u8 port[0x8]; 4949 u8 reserved_at_10[0x10]; 4950 4951 u8 reserved_at_20[0x60]; 4952 }; 4953 4954 enum { 4955 MLX5_TEARDOWN_HCA_OUT_FORCE_STATE_SUCCESS = 0x0, 4956 MLX5_TEARDOWN_HCA_OUT_FORCE_STATE_FAIL = 0x1, 4957 }; 4958 4959 struct mlx5_ifc_teardown_hca_out_bits { 4960 u8 status[0x8]; 4961 u8 reserved_at_8[0x18]; 4962 4963 u8 syndrome[0x20]; 4964 4965 u8 reserved_at_40[0x3f]; 4966 4967 u8 state[0x1]; 4968 }; 4969 4970 enum { 4971 MLX5_TEARDOWN_HCA_IN_PROFILE_GRACEFUL_CLOSE = 0x0, 4972 MLX5_TEARDOWN_HCA_IN_PROFILE_FORCE_CLOSE = 0x1, 4973 MLX5_TEARDOWN_HCA_IN_PROFILE_PREPARE_FAST_TEARDOWN = 0x2, 4974 }; 4975 4976 struct mlx5_ifc_teardown_hca_in_bits { 4977 u8 opcode[0x10]; 4978 u8 reserved_at_10[0x10]; 4979 4980 u8 reserved_at_20[0x10]; 4981 u8 op_mod[0x10]; 4982 4983 u8 reserved_at_40[0x10]; 4984 u8 profile[0x10]; 4985 4986 u8 reserved_at_60[0x20]; 4987 }; 4988 4989 struct mlx5_ifc_sqerr2rts_qp_out_bits { 4990 u8 status[0x8]; 4991 u8 reserved_at_8[0x18]; 4992 4993 u8 syndrome[0x20]; 4994 4995 u8 reserved_at_40[0x40]; 4996 }; 4997 4998 struct mlx5_ifc_sqerr2rts_qp_in_bits { 4999 u8 opcode[0x10]; 5000 u8 uid[0x10]; 5001 5002 u8 reserved_at_20[0x10]; 5003 u8 op_mod[0x10]; 5004 5005 u8 reserved_at_40[0x8]; 5006 u8 qpn[0x18]; 5007 5008 u8 reserved_at_60[0x20]; 5009 5010 u8 opt_param_mask[0x20]; 5011 5012 u8 reserved_at_a0[0x20]; 5013 5014 struct mlx5_ifc_qpc_bits qpc; 5015 5016 u8 reserved_at_800[0x80]; 5017 }; 5018 5019 struct mlx5_ifc_sqd2rts_qp_out_bits { 5020 u8 status[0x8]; 5021 u8 reserved_at_8[0x18]; 5022 5023 u8 syndrome[0x20]; 5024 5025 u8 reserved_at_40[0x40]; 5026 }; 5027 5028 struct mlx5_ifc_sqd2rts_qp_in_bits { 5029 u8 opcode[0x10]; 5030 u8 uid[0x10]; 5031 5032 u8 reserved_at_20[0x10]; 5033 u8 op_mod[0x10]; 5034 5035 u8 reserved_at_40[0x8]; 5036 u8 qpn[0x18]; 5037 5038 u8 reserved_at_60[0x20]; 5039 5040 u8 opt_param_mask[0x20]; 5041 5042 u8 reserved_at_a0[0x20]; 5043 5044 struct mlx5_ifc_qpc_bits qpc; 5045 5046 u8 reserved_at_800[0x80]; 5047 }; 5048 5049 struct mlx5_ifc_set_roce_address_out_bits { 5050 u8 status[0x8]; 5051 u8 reserved_at_8[0x18]; 5052 5053 u8 syndrome[0x20]; 5054 5055 u8 reserved_at_40[0x40]; 5056 }; 5057 5058 struct mlx5_ifc_set_roce_address_in_bits { 5059 u8 opcode[0x10]; 5060 u8 reserved_at_10[0x10]; 5061 5062 u8 reserved_at_20[0x10]; 5063 u8 op_mod[0x10]; 5064 5065 u8 roce_address_index[0x10]; 5066 u8 reserved_at_50[0xc]; 5067 u8 vhca_port_num[0x4]; 5068 5069 u8 reserved_at_60[0x20]; 5070 5071 struct mlx5_ifc_roce_addr_layout_bits roce_address; 5072 }; 5073 5074 struct mlx5_ifc_set_mad_demux_out_bits { 5075 u8 status[0x8]; 5076 u8 reserved_at_8[0x18]; 5077 5078 u8 syndrome[0x20]; 5079 5080 u8 reserved_at_40[0x40]; 5081 }; 5082 5083 enum { 5084 MLX5_SET_MAD_DEMUX_IN_DEMUX_MODE_PASS_ALL = 0x0, 5085 MLX5_SET_MAD_DEMUX_IN_DEMUX_MODE_SELECTIVE = 0x2, 5086 }; 5087 5088 struct mlx5_ifc_set_mad_demux_in_bits { 5089 u8 opcode[0x10]; 5090 u8 reserved_at_10[0x10]; 5091 5092 u8 reserved_at_20[0x10]; 5093 u8 op_mod[0x10]; 5094 5095 u8 reserved_at_40[0x20]; 5096 5097 u8 reserved_at_60[0x6]; 5098 u8 demux_mode[0x2]; 5099 u8 reserved_at_68[0x18]; 5100 }; 5101 5102 struct mlx5_ifc_set_l2_table_entry_out_bits { 5103 u8 status[0x8]; 5104 u8 reserved_at_8[0x18]; 5105 5106 u8 syndrome[0x20]; 5107 5108 u8 reserved_at_40[0x40]; 5109 }; 5110 5111 struct mlx5_ifc_set_l2_table_entry_in_bits { 5112 u8 opcode[0x10]; 5113 u8 reserved_at_10[0x10]; 5114 5115 u8 reserved_at_20[0x10]; 5116 u8 op_mod[0x10]; 5117 5118 u8 reserved_at_40[0x60]; 5119 5120 u8 reserved_at_a0[0x8]; 5121 u8 table_index[0x18]; 5122 5123 u8 reserved_at_c0[0x20]; 5124 5125 u8 reserved_at_e0[0x10]; 5126 u8 silent_mode_valid[0x1]; 5127 u8 silent_mode[0x1]; 5128 u8 reserved_at_f2[0x1]; 5129 u8 vlan_valid[0x1]; 5130 u8 vlan[0xc]; 5131 5132 struct mlx5_ifc_mac_address_layout_bits mac_address; 5133 5134 u8 reserved_at_140[0xc0]; 5135 }; 5136 5137 struct mlx5_ifc_set_issi_out_bits { 5138 u8 status[0x8]; 5139 u8 reserved_at_8[0x18]; 5140 5141 u8 syndrome[0x20]; 5142 5143 u8 reserved_at_40[0x40]; 5144 }; 5145 5146 struct mlx5_ifc_set_issi_in_bits { 5147 u8 opcode[0x10]; 5148 u8 reserved_at_10[0x10]; 5149 5150 u8 reserved_at_20[0x10]; 5151 u8 op_mod[0x10]; 5152 5153 u8 reserved_at_40[0x10]; 5154 u8 current_issi[0x10]; 5155 5156 u8 reserved_at_60[0x20]; 5157 }; 5158 5159 struct mlx5_ifc_set_hca_cap_out_bits { 5160 u8 status[0x8]; 5161 u8 reserved_at_8[0x18]; 5162 5163 u8 syndrome[0x20]; 5164 5165 u8 reserved_at_40[0x40]; 5166 }; 5167 5168 struct mlx5_ifc_set_hca_cap_in_bits { 5169 u8 opcode[0x10]; 5170 u8 reserved_at_10[0x10]; 5171 5172 u8 reserved_at_20[0x10]; 5173 u8 op_mod[0x10]; 5174 5175 u8 other_function[0x1]; 5176 u8 ec_vf_function[0x1]; 5177 u8 reserved_at_42[0x1]; 5178 u8 function_id_type[0x1]; 5179 u8 reserved_at_44[0xc]; 5180 u8 function_id[0x10]; 5181 5182 u8 reserved_at_60[0x20]; 5183 5184 union mlx5_ifc_hca_cap_union_bits capability; 5185 }; 5186 5187 enum { 5188 MLX5_SET_FTE_MODIFY_ENABLE_MASK_ACTION = 0x0, 5189 MLX5_SET_FTE_MODIFY_ENABLE_MASK_FLOW_TAG = 0x1, 5190 MLX5_SET_FTE_MODIFY_ENABLE_MASK_DESTINATION_LIST = 0x2, 5191 MLX5_SET_FTE_MODIFY_ENABLE_MASK_FLOW_COUNTERS = 0x3, 5192 MLX5_SET_FTE_MODIFY_ENABLE_MASK_IPSEC_OBJ_ID = 0x4 5193 }; 5194 5195 struct mlx5_ifc_set_fte_out_bits { 5196 u8 status[0x8]; 5197 u8 reserved_at_8[0x18]; 5198 5199 u8 syndrome[0x20]; 5200 5201 u8 reserved_at_40[0x40]; 5202 }; 5203 5204 struct mlx5_ifc_set_fte_in_bits { 5205 u8 opcode[0x10]; 5206 u8 reserved_at_10[0x10]; 5207 5208 u8 reserved_at_20[0x10]; 5209 u8 op_mod[0x10]; 5210 5211 u8 other_vport[0x1]; 5212 u8 reserved_at_41[0xf]; 5213 u8 vport_number[0x10]; 5214 5215 u8 reserved_at_60[0x20]; 5216 5217 u8 table_type[0x8]; 5218 u8 reserved_at_88[0x18]; 5219 5220 u8 reserved_at_a0[0x8]; 5221 u8 table_id[0x18]; 5222 5223 u8 ignore_flow_level[0x1]; 5224 u8 reserved_at_c1[0x17]; 5225 u8 modify_enable_mask[0x8]; 5226 5227 u8 reserved_at_e0[0x20]; 5228 5229 u8 flow_index[0x20]; 5230 5231 u8 reserved_at_120[0xe0]; 5232 5233 struct mlx5_ifc_flow_context_bits flow_context; 5234 }; 5235 5236 struct mlx5_ifc_dest_format_bits { 5237 u8 destination_type[0x8]; 5238 u8 destination_id[0x18]; 5239 5240 u8 destination_eswitch_owner_vhca_id_valid[0x1]; 5241 u8 packet_reformat[0x1]; 5242 u8 reserved_at_22[0xe]; 5243 u8 destination_eswitch_owner_vhca_id[0x10]; 5244 }; 5245 5246 struct mlx5_ifc_rts2rts_qp_out_bits { 5247 u8 status[0x8]; 5248 u8 reserved_at_8[0x18]; 5249 5250 u8 syndrome[0x20]; 5251 5252 u8 reserved_at_40[0x20]; 5253 u8 ece[0x20]; 5254 }; 5255 5256 struct mlx5_ifc_rts2rts_qp_in_bits { 5257 u8 opcode[0x10]; 5258 u8 uid[0x10]; 5259 5260 u8 reserved_at_20[0x10]; 5261 u8 op_mod[0x10]; 5262 5263 u8 reserved_at_40[0x8]; 5264 u8 qpn[0x18]; 5265 5266 u8 reserved_at_60[0x20]; 5267 5268 u8 opt_param_mask[0x20]; 5269 5270 u8 ece[0x20]; 5271 5272 struct mlx5_ifc_qpc_bits qpc; 5273 5274 u8 reserved_at_800[0x80]; 5275 }; 5276 5277 struct mlx5_ifc_rtr2rts_qp_out_bits { 5278 u8 status[0x8]; 5279 u8 reserved_at_8[0x18]; 5280 5281 u8 syndrome[0x20]; 5282 5283 u8 reserved_at_40[0x20]; 5284 u8 ece[0x20]; 5285 }; 5286 5287 struct mlx5_ifc_rtr2rts_qp_in_bits { 5288 u8 opcode[0x10]; 5289 u8 uid[0x10]; 5290 5291 u8 reserved_at_20[0x10]; 5292 u8 op_mod[0x10]; 5293 5294 u8 reserved_at_40[0x8]; 5295 u8 qpn[0x18]; 5296 5297 u8 reserved_at_60[0x20]; 5298 5299 u8 opt_param_mask[0x20]; 5300 5301 u8 ece[0x20]; 5302 5303 struct mlx5_ifc_qpc_bits qpc; 5304 5305 u8 reserved_at_800[0x80]; 5306 }; 5307 5308 struct mlx5_ifc_rst2init_qp_out_bits { 5309 u8 status[0x8]; 5310 u8 reserved_at_8[0x18]; 5311 5312 u8 syndrome[0x20]; 5313 5314 u8 reserved_at_40[0x20]; 5315 u8 ece[0x20]; 5316 }; 5317 5318 struct mlx5_ifc_rst2init_qp_in_bits { 5319 u8 opcode[0x10]; 5320 u8 uid[0x10]; 5321 5322 u8 reserved_at_20[0x10]; 5323 u8 op_mod[0x10]; 5324 5325 u8 reserved_at_40[0x8]; 5326 u8 qpn[0x18]; 5327 5328 u8 reserved_at_60[0x20]; 5329 5330 u8 opt_param_mask[0x20]; 5331 5332 u8 ece[0x20]; 5333 5334 struct mlx5_ifc_qpc_bits qpc; 5335 5336 u8 reserved_at_800[0x80]; 5337 }; 5338 5339 struct mlx5_ifc_query_xrq_out_bits { 5340 u8 status[0x8]; 5341 u8 reserved_at_8[0x18]; 5342 5343 u8 syndrome[0x20]; 5344 5345 u8 reserved_at_40[0x40]; 5346 5347 struct mlx5_ifc_xrqc_bits xrq_context; 5348 }; 5349 5350 struct mlx5_ifc_query_xrq_in_bits { 5351 u8 opcode[0x10]; 5352 u8 reserved_at_10[0x10]; 5353 5354 u8 reserved_at_20[0x10]; 5355 u8 op_mod[0x10]; 5356 5357 u8 reserved_at_40[0x8]; 5358 u8 xrqn[0x18]; 5359 5360 u8 reserved_at_60[0x20]; 5361 }; 5362 5363 struct mlx5_ifc_query_xrc_srq_out_bits { 5364 u8 status[0x8]; 5365 u8 reserved_at_8[0x18]; 5366 5367 u8 syndrome[0x20]; 5368 5369 u8 reserved_at_40[0x40]; 5370 5371 struct mlx5_ifc_xrc_srqc_bits xrc_srq_context_entry; 5372 5373 u8 reserved_at_280[0x600]; 5374 5375 u8 pas[][0x40]; 5376 }; 5377 5378 struct mlx5_ifc_query_xrc_srq_in_bits { 5379 u8 opcode[0x10]; 5380 u8 reserved_at_10[0x10]; 5381 5382 u8 reserved_at_20[0x10]; 5383 u8 op_mod[0x10]; 5384 5385 u8 reserved_at_40[0x8]; 5386 u8 xrc_srqn[0x18]; 5387 5388 u8 reserved_at_60[0x20]; 5389 }; 5390 5391 enum { 5392 MLX5_QUERY_VPORT_STATE_OUT_STATE_DOWN = 0x0, 5393 MLX5_QUERY_VPORT_STATE_OUT_STATE_UP = 0x1, 5394 }; 5395 5396 struct mlx5_ifc_query_vport_state_out_bits { 5397 u8 status[0x8]; 5398 u8 reserved_at_8[0x18]; 5399 5400 u8 syndrome[0x20]; 5401 5402 u8 reserved_at_40[0x20]; 5403 5404 u8 reserved_at_60[0x18]; 5405 u8 admin_state[0x4]; 5406 u8 state[0x4]; 5407 }; 5408 5409 struct mlx5_ifc_array1024_auto_bits { 5410 u8 array1024_auto[32][0x20]; 5411 }; 5412 5413 struct mlx5_ifc_query_vuid_in_bits { 5414 u8 opcode[0x10]; 5415 u8 uid[0x10]; 5416 5417 u8 reserved_at_20[0x40]; 5418 5419 u8 query_vfs_vuid[0x1]; 5420 u8 data_direct[0x1]; 5421 u8 reserved_at_62[0xe]; 5422 u8 vhca_id[0x10]; 5423 }; 5424 5425 struct mlx5_ifc_query_vuid_out_bits { 5426 u8 status[0x8]; 5427 u8 reserved_at_8[0x18]; 5428 5429 u8 syndrome[0x20]; 5430 5431 u8 reserved_at_40[0x1a0]; 5432 5433 u8 reserved_at_1e0[0x10]; 5434 u8 num_of_entries[0x10]; 5435 5436 struct mlx5_ifc_array1024_auto_bits vuid[]; 5437 }; 5438 5439 enum { 5440 MLX5_VPORT_STATE_OP_MOD_VNIC_VPORT = 0x0, 5441 MLX5_VPORT_STATE_OP_MOD_ESW_VPORT = 0x1, 5442 MLX5_VPORT_STATE_OP_MOD_UPLINK = 0x2, 5443 }; 5444 5445 struct mlx5_ifc_arm_monitor_counter_in_bits { 5446 u8 opcode[0x10]; 5447 u8 uid[0x10]; 5448 5449 u8 reserved_at_20[0x10]; 5450 u8 op_mod[0x10]; 5451 5452 u8 reserved_at_40[0x20]; 5453 5454 u8 reserved_at_60[0x20]; 5455 }; 5456 5457 struct mlx5_ifc_arm_monitor_counter_out_bits { 5458 u8 status[0x8]; 5459 u8 reserved_at_8[0x18]; 5460 5461 u8 syndrome[0x20]; 5462 5463 u8 reserved_at_40[0x40]; 5464 }; 5465 5466 enum { 5467 MLX5_QUERY_MONITOR_CNT_TYPE_PPCNT = 0x0, 5468 MLX5_QUERY_MONITOR_CNT_TYPE_Q_COUNTER = 0x1, 5469 }; 5470 5471 enum mlx5_monitor_counter_ppcnt { 5472 MLX5_QUERY_MONITOR_PPCNT_IN_RANGE_LENGTH_ERRORS = 0x0, 5473 MLX5_QUERY_MONITOR_PPCNT_OUT_OF_RANGE_LENGTH_FIELD = 0x1, 5474 MLX5_QUERY_MONITOR_PPCNT_FRAME_TOO_LONG_ERRORS = 0x2, 5475 MLX5_QUERY_MONITOR_PPCNT_FRAME_CHECK_SEQUENCE_ERRORS = 0x3, 5476 MLX5_QUERY_MONITOR_PPCNT_ALIGNMENT_ERRORS = 0x4, 5477 MLX5_QUERY_MONITOR_PPCNT_IF_OUT_DISCARDS = 0x5, 5478 }; 5479 5480 enum { 5481 MLX5_QUERY_MONITOR_Q_COUNTER_RX_OUT_OF_BUFFER = 0x4, 5482 }; 5483 5484 struct mlx5_ifc_monitor_counter_output_bits { 5485 u8 reserved_at_0[0x4]; 5486 u8 type[0x4]; 5487 u8 reserved_at_8[0x8]; 5488 u8 counter[0x10]; 5489 5490 u8 counter_group_id[0x20]; 5491 }; 5492 5493 #define MLX5_CMD_SET_MONITOR_NUM_PPCNT_COUNTER_SET1 (6) 5494 #define MLX5_CMD_SET_MONITOR_NUM_Q_COUNTERS_SET1 (1) 5495 #define MLX5_CMD_SET_MONITOR_NUM_COUNTER (MLX5_CMD_SET_MONITOR_NUM_PPCNT_COUNTER_SET1 +\ 5496 MLX5_CMD_SET_MONITOR_NUM_Q_COUNTERS_SET1) 5497 5498 struct mlx5_ifc_set_monitor_counter_in_bits { 5499 u8 opcode[0x10]; 5500 u8 uid[0x10]; 5501 5502 u8 reserved_at_20[0x10]; 5503 u8 op_mod[0x10]; 5504 5505 u8 reserved_at_40[0x10]; 5506 u8 num_of_counters[0x10]; 5507 5508 u8 reserved_at_60[0x20]; 5509 5510 struct mlx5_ifc_monitor_counter_output_bits monitor_counter[MLX5_CMD_SET_MONITOR_NUM_COUNTER]; 5511 }; 5512 5513 struct mlx5_ifc_set_monitor_counter_out_bits { 5514 u8 status[0x8]; 5515 u8 reserved_at_8[0x18]; 5516 5517 u8 syndrome[0x20]; 5518 5519 u8 reserved_at_40[0x40]; 5520 }; 5521 5522 struct mlx5_ifc_query_vport_state_in_bits { 5523 u8 opcode[0x10]; 5524 u8 reserved_at_10[0x10]; 5525 5526 u8 reserved_at_20[0x10]; 5527 u8 op_mod[0x10]; 5528 5529 u8 other_vport[0x1]; 5530 u8 reserved_at_41[0xf]; 5531 u8 vport_number[0x10]; 5532 5533 u8 reserved_at_60[0x20]; 5534 }; 5535 5536 struct mlx5_ifc_query_vnic_env_out_bits { 5537 u8 status[0x8]; 5538 u8 reserved_at_8[0x18]; 5539 5540 u8 syndrome[0x20]; 5541 5542 u8 reserved_at_40[0x40]; 5543 5544 struct mlx5_ifc_vnic_diagnostic_statistics_bits vport_env; 5545 }; 5546 5547 enum { 5548 MLX5_QUERY_VNIC_ENV_IN_OP_MOD_VPORT_DIAG_STATISTICS = 0x0, 5549 }; 5550 5551 struct mlx5_ifc_query_vnic_env_in_bits { 5552 u8 opcode[0x10]; 5553 u8 reserved_at_10[0x10]; 5554 5555 u8 reserved_at_20[0x10]; 5556 u8 op_mod[0x10]; 5557 5558 u8 other_vport[0x1]; 5559 u8 reserved_at_41[0xf]; 5560 u8 vport_number[0x10]; 5561 5562 u8 reserved_at_60[0x20]; 5563 }; 5564 5565 struct mlx5_ifc_query_vport_counter_out_bits { 5566 u8 status[0x8]; 5567 u8 reserved_at_8[0x18]; 5568 5569 u8 syndrome[0x20]; 5570 5571 u8 reserved_at_40[0x40]; 5572 5573 struct mlx5_ifc_traffic_counter_bits received_errors; 5574 5575 struct mlx5_ifc_traffic_counter_bits transmit_errors; 5576 5577 struct mlx5_ifc_traffic_counter_bits received_ib_unicast; 5578 5579 struct mlx5_ifc_traffic_counter_bits transmitted_ib_unicast; 5580 5581 struct mlx5_ifc_traffic_counter_bits received_ib_multicast; 5582 5583 struct mlx5_ifc_traffic_counter_bits transmitted_ib_multicast; 5584 5585 struct mlx5_ifc_traffic_counter_bits received_eth_broadcast; 5586 5587 struct mlx5_ifc_traffic_counter_bits transmitted_eth_broadcast; 5588 5589 struct mlx5_ifc_traffic_counter_bits received_eth_unicast; 5590 5591 struct mlx5_ifc_traffic_counter_bits transmitted_eth_unicast; 5592 5593 struct mlx5_ifc_traffic_counter_bits received_eth_multicast; 5594 5595 struct mlx5_ifc_traffic_counter_bits transmitted_eth_multicast; 5596 5597 struct mlx5_ifc_traffic_counter_bits local_loopback; 5598 5599 u8 reserved_at_700[0x980]; 5600 }; 5601 5602 enum { 5603 MLX5_QUERY_VPORT_COUNTER_IN_OP_MOD_VPORT_COUNTERS = 0x0, 5604 }; 5605 5606 struct mlx5_ifc_query_vport_counter_in_bits { 5607 u8 opcode[0x10]; 5608 u8 reserved_at_10[0x10]; 5609 5610 u8 reserved_at_20[0x10]; 5611 u8 op_mod[0x10]; 5612 5613 u8 other_vport[0x1]; 5614 u8 reserved_at_41[0xb]; 5615 u8 port_num[0x4]; 5616 u8 vport_number[0x10]; 5617 5618 u8 reserved_at_60[0x60]; 5619 5620 u8 clear[0x1]; 5621 u8 reserved_at_c1[0x1f]; 5622 5623 u8 reserved_at_e0[0x20]; 5624 }; 5625 5626 struct mlx5_ifc_query_tis_out_bits { 5627 u8 status[0x8]; 5628 u8 reserved_at_8[0x18]; 5629 5630 u8 syndrome[0x20]; 5631 5632 u8 reserved_at_40[0x40]; 5633 5634 struct mlx5_ifc_tisc_bits tis_context; 5635 }; 5636 5637 struct mlx5_ifc_query_tis_in_bits { 5638 u8 opcode[0x10]; 5639 u8 reserved_at_10[0x10]; 5640 5641 u8 reserved_at_20[0x10]; 5642 u8 op_mod[0x10]; 5643 5644 u8 reserved_at_40[0x8]; 5645 u8 tisn[0x18]; 5646 5647 u8 reserved_at_60[0x20]; 5648 }; 5649 5650 struct mlx5_ifc_query_tir_out_bits { 5651 u8 status[0x8]; 5652 u8 reserved_at_8[0x18]; 5653 5654 u8 syndrome[0x20]; 5655 5656 u8 reserved_at_40[0xc0]; 5657 5658 struct mlx5_ifc_tirc_bits tir_context; 5659 }; 5660 5661 struct mlx5_ifc_query_tir_in_bits { 5662 u8 opcode[0x10]; 5663 u8 reserved_at_10[0x10]; 5664 5665 u8 reserved_at_20[0x10]; 5666 u8 op_mod[0x10]; 5667 5668 u8 reserved_at_40[0x8]; 5669 u8 tirn[0x18]; 5670 5671 u8 reserved_at_60[0x20]; 5672 }; 5673 5674 struct mlx5_ifc_query_srq_out_bits { 5675 u8 status[0x8]; 5676 u8 reserved_at_8[0x18]; 5677 5678 u8 syndrome[0x20]; 5679 5680 u8 reserved_at_40[0x40]; 5681 5682 struct mlx5_ifc_srqc_bits srq_context_entry; 5683 5684 u8 reserved_at_280[0x600]; 5685 5686 u8 pas[][0x40]; 5687 }; 5688 5689 struct mlx5_ifc_query_srq_in_bits { 5690 u8 opcode[0x10]; 5691 u8 reserved_at_10[0x10]; 5692 5693 u8 reserved_at_20[0x10]; 5694 u8 op_mod[0x10]; 5695 5696 u8 reserved_at_40[0x8]; 5697 u8 srqn[0x18]; 5698 5699 u8 reserved_at_60[0x20]; 5700 }; 5701 5702 struct mlx5_ifc_query_sq_out_bits { 5703 u8 status[0x8]; 5704 u8 reserved_at_8[0x18]; 5705 5706 u8 syndrome[0x20]; 5707 5708 u8 reserved_at_40[0xc0]; 5709 5710 struct mlx5_ifc_sqc_bits sq_context; 5711 }; 5712 5713 struct mlx5_ifc_query_sq_in_bits { 5714 u8 opcode[0x10]; 5715 u8 reserved_at_10[0x10]; 5716 5717 u8 reserved_at_20[0x10]; 5718 u8 op_mod[0x10]; 5719 5720 u8 reserved_at_40[0x8]; 5721 u8 sqn[0x18]; 5722 5723 u8 reserved_at_60[0x20]; 5724 }; 5725 5726 struct mlx5_ifc_query_special_contexts_out_bits { 5727 u8 status[0x8]; 5728 u8 reserved_at_8[0x18]; 5729 5730 u8 syndrome[0x20]; 5731 5732 u8 dump_fill_mkey[0x20]; 5733 5734 u8 resd_lkey[0x20]; 5735 5736 u8 null_mkey[0x20]; 5737 5738 u8 terminate_scatter_list_mkey[0x20]; 5739 5740 u8 repeated_mkey[0x20]; 5741 5742 u8 reserved_at_a0[0x20]; 5743 }; 5744 5745 struct mlx5_ifc_query_special_contexts_in_bits { 5746 u8 opcode[0x10]; 5747 u8 reserved_at_10[0x10]; 5748 5749 u8 reserved_at_20[0x10]; 5750 u8 op_mod[0x10]; 5751 5752 u8 reserved_at_40[0x40]; 5753 }; 5754 5755 struct mlx5_ifc_query_scheduling_element_out_bits { 5756 u8 opcode[0x10]; 5757 u8 reserved_at_10[0x10]; 5758 5759 u8 reserved_at_20[0x10]; 5760 u8 op_mod[0x10]; 5761 5762 u8 reserved_at_40[0xc0]; 5763 5764 struct mlx5_ifc_scheduling_context_bits scheduling_context; 5765 5766 u8 reserved_at_300[0x100]; 5767 }; 5768 5769 enum { 5770 SCHEDULING_HIERARCHY_E_SWITCH = 0x2, 5771 SCHEDULING_HIERARCHY_NIC = 0x3, 5772 }; 5773 5774 struct mlx5_ifc_query_scheduling_element_in_bits { 5775 u8 opcode[0x10]; 5776 u8 reserved_at_10[0x10]; 5777 5778 u8 reserved_at_20[0x10]; 5779 u8 op_mod[0x10]; 5780 5781 u8 scheduling_hierarchy[0x8]; 5782 u8 reserved_at_48[0x18]; 5783 5784 u8 scheduling_element_id[0x20]; 5785 5786 u8 reserved_at_80[0x180]; 5787 }; 5788 5789 struct mlx5_ifc_query_rqt_out_bits { 5790 u8 status[0x8]; 5791 u8 reserved_at_8[0x18]; 5792 5793 u8 syndrome[0x20]; 5794 5795 u8 reserved_at_40[0xc0]; 5796 5797 struct mlx5_ifc_rqtc_bits rqt_context; 5798 }; 5799 5800 struct mlx5_ifc_query_rqt_in_bits { 5801 u8 opcode[0x10]; 5802 u8 reserved_at_10[0x10]; 5803 5804 u8 reserved_at_20[0x10]; 5805 u8 op_mod[0x10]; 5806 5807 u8 reserved_at_40[0x8]; 5808 u8 rqtn[0x18]; 5809 5810 u8 reserved_at_60[0x20]; 5811 }; 5812 5813 struct mlx5_ifc_query_rq_out_bits { 5814 u8 status[0x8]; 5815 u8 reserved_at_8[0x18]; 5816 5817 u8 syndrome[0x20]; 5818 5819 u8 reserved_at_40[0xc0]; 5820 5821 struct mlx5_ifc_rqc_bits rq_context; 5822 }; 5823 5824 struct mlx5_ifc_query_rq_in_bits { 5825 u8 opcode[0x10]; 5826 u8 reserved_at_10[0x10]; 5827 5828 u8 reserved_at_20[0x10]; 5829 u8 op_mod[0x10]; 5830 5831 u8 reserved_at_40[0x8]; 5832 u8 rqn[0x18]; 5833 5834 u8 reserved_at_60[0x20]; 5835 }; 5836 5837 struct mlx5_ifc_query_roce_address_out_bits { 5838 u8 status[0x8]; 5839 u8 reserved_at_8[0x18]; 5840 5841 u8 syndrome[0x20]; 5842 5843 u8 reserved_at_40[0x40]; 5844 5845 struct mlx5_ifc_roce_addr_layout_bits roce_address; 5846 }; 5847 5848 struct mlx5_ifc_query_roce_address_in_bits { 5849 u8 opcode[0x10]; 5850 u8 reserved_at_10[0x10]; 5851 5852 u8 reserved_at_20[0x10]; 5853 u8 op_mod[0x10]; 5854 5855 u8 roce_address_index[0x10]; 5856 u8 reserved_at_50[0xc]; 5857 u8 vhca_port_num[0x4]; 5858 5859 u8 reserved_at_60[0x20]; 5860 }; 5861 5862 struct mlx5_ifc_query_rmp_out_bits { 5863 u8 status[0x8]; 5864 u8 reserved_at_8[0x18]; 5865 5866 u8 syndrome[0x20]; 5867 5868 u8 reserved_at_40[0xc0]; 5869 5870 struct mlx5_ifc_rmpc_bits rmp_context; 5871 }; 5872 5873 struct mlx5_ifc_query_rmp_in_bits { 5874 u8 opcode[0x10]; 5875 u8 reserved_at_10[0x10]; 5876 5877 u8 reserved_at_20[0x10]; 5878 u8 op_mod[0x10]; 5879 5880 u8 reserved_at_40[0x8]; 5881 u8 rmpn[0x18]; 5882 5883 u8 reserved_at_60[0x20]; 5884 }; 5885 5886 struct mlx5_ifc_cqe_error_syndrome_bits { 5887 u8 hw_error_syndrome[0x8]; 5888 u8 hw_syndrome_type[0x4]; 5889 u8 reserved_at_c[0x4]; 5890 u8 vendor_error_syndrome[0x8]; 5891 u8 syndrome[0x8]; 5892 }; 5893 5894 struct mlx5_ifc_qp_context_extension_bits { 5895 u8 reserved_at_0[0x60]; 5896 5897 struct mlx5_ifc_cqe_error_syndrome_bits error_syndrome; 5898 5899 u8 reserved_at_80[0x580]; 5900 }; 5901 5902 struct mlx5_ifc_qpc_extension_and_pas_list_in_bits { 5903 struct mlx5_ifc_qp_context_extension_bits qpc_data_extension; 5904 5905 u8 pas[0][0x40]; 5906 }; 5907 5908 struct mlx5_ifc_qp_pas_list_in_bits { 5909 struct mlx5_ifc_cmd_pas_bits pas[0]; 5910 }; 5911 5912 union mlx5_ifc_qp_pas_or_qpc_ext_and_pas_bits { 5913 struct mlx5_ifc_qp_pas_list_in_bits qp_pas_list; 5914 struct mlx5_ifc_qpc_extension_and_pas_list_in_bits qpc_ext_and_pas_list; 5915 }; 5916 5917 struct mlx5_ifc_query_qp_out_bits { 5918 u8 status[0x8]; 5919 u8 reserved_at_8[0x18]; 5920 5921 u8 syndrome[0x20]; 5922 5923 u8 reserved_at_40[0x40]; 5924 5925 u8 opt_param_mask[0x20]; 5926 5927 u8 ece[0x20]; 5928 5929 struct mlx5_ifc_qpc_bits qpc; 5930 5931 u8 reserved_at_800[0x80]; 5932 5933 union mlx5_ifc_qp_pas_or_qpc_ext_and_pas_bits qp_pas_or_qpc_ext_and_pas; 5934 }; 5935 5936 struct mlx5_ifc_query_qp_in_bits { 5937 u8 opcode[0x10]; 5938 u8 reserved_at_10[0x10]; 5939 5940 u8 reserved_at_20[0x10]; 5941 u8 op_mod[0x10]; 5942 5943 u8 qpc_ext[0x1]; 5944 u8 reserved_at_41[0x7]; 5945 u8 qpn[0x18]; 5946 5947 u8 reserved_at_60[0x20]; 5948 }; 5949 5950 struct mlx5_ifc_query_q_counter_out_bits { 5951 u8 status[0x8]; 5952 u8 reserved_at_8[0x18]; 5953 5954 u8 syndrome[0x20]; 5955 5956 u8 reserved_at_40[0x40]; 5957 5958 u8 rx_write_requests[0x20]; 5959 5960 u8 reserved_at_a0[0x20]; 5961 5962 u8 rx_read_requests[0x20]; 5963 5964 u8 reserved_at_e0[0x20]; 5965 5966 u8 rx_atomic_requests[0x20]; 5967 5968 u8 reserved_at_120[0x20]; 5969 5970 u8 rx_dct_connect[0x20]; 5971 5972 u8 reserved_at_160[0x20]; 5973 5974 u8 out_of_buffer[0x20]; 5975 5976 u8 reserved_at_1a0[0x20]; 5977 5978 u8 out_of_sequence[0x20]; 5979 5980 u8 reserved_at_1e0[0x20]; 5981 5982 u8 duplicate_request[0x20]; 5983 5984 u8 reserved_at_220[0x20]; 5985 5986 u8 rnr_nak_retry_err[0x20]; 5987 5988 u8 reserved_at_260[0x20]; 5989 5990 u8 packet_seq_err[0x20]; 5991 5992 u8 reserved_at_2a0[0x20]; 5993 5994 u8 implied_nak_seq_err[0x20]; 5995 5996 u8 reserved_at_2e0[0x20]; 5997 5998 u8 local_ack_timeout_err[0x20]; 5999 6000 u8 reserved_at_320[0x60]; 6001 6002 u8 req_rnr_retries_exceeded[0x20]; 6003 6004 u8 reserved_at_3a0[0x20]; 6005 6006 u8 resp_local_length_error[0x20]; 6007 6008 u8 req_local_length_error[0x20]; 6009 6010 u8 resp_local_qp_error[0x20]; 6011 6012 u8 local_operation_error[0x20]; 6013 6014 u8 resp_local_protection[0x20]; 6015 6016 u8 req_local_protection[0x20]; 6017 6018 u8 resp_cqe_error[0x20]; 6019 6020 u8 req_cqe_error[0x20]; 6021 6022 u8 req_mw_binding[0x20]; 6023 6024 u8 req_bad_response[0x20]; 6025 6026 u8 req_remote_invalid_request[0x20]; 6027 6028 u8 resp_remote_invalid_request[0x20]; 6029 6030 u8 req_remote_access_errors[0x20]; 6031 6032 u8 resp_remote_access_errors[0x20]; 6033 6034 u8 req_remote_operation_errors[0x20]; 6035 6036 u8 req_transport_retries_exceeded[0x20]; 6037 6038 u8 cq_overflow[0x20]; 6039 6040 u8 resp_cqe_flush_error[0x20]; 6041 6042 u8 req_cqe_flush_error[0x20]; 6043 6044 u8 reserved_at_620[0x20]; 6045 6046 u8 roce_adp_retrans[0x20]; 6047 6048 u8 roce_adp_retrans_to[0x20]; 6049 6050 u8 roce_slow_restart[0x20]; 6051 6052 u8 roce_slow_restart_cnps[0x20]; 6053 6054 u8 roce_slow_restart_trans[0x20]; 6055 6056 u8 reserved_at_6e0[0x120]; 6057 }; 6058 6059 struct mlx5_ifc_query_q_counter_in_bits { 6060 u8 opcode[0x10]; 6061 u8 reserved_at_10[0x10]; 6062 6063 u8 reserved_at_20[0x10]; 6064 u8 op_mod[0x10]; 6065 6066 u8 other_vport[0x1]; 6067 u8 reserved_at_41[0xf]; 6068 u8 vport_number[0x10]; 6069 6070 u8 reserved_at_60[0x60]; 6071 6072 u8 clear[0x1]; 6073 u8 aggregate[0x1]; 6074 u8 reserved_at_c2[0x1e]; 6075 6076 u8 reserved_at_e0[0x18]; 6077 u8 counter_set_id[0x8]; 6078 }; 6079 6080 struct mlx5_ifc_query_pages_out_bits { 6081 u8 status[0x8]; 6082 u8 reserved_at_8[0x18]; 6083 6084 u8 syndrome[0x20]; 6085 6086 u8 embedded_cpu_function[0x1]; 6087 u8 reserved_at_41[0xf]; 6088 u8 function_id[0x10]; 6089 6090 u8 num_pages[0x20]; 6091 }; 6092 6093 enum { 6094 MLX5_QUERY_PAGES_IN_OP_MOD_BOOT_PAGES = 0x1, 6095 MLX5_QUERY_PAGES_IN_OP_MOD_INIT_PAGES = 0x2, 6096 MLX5_QUERY_PAGES_IN_OP_MOD_REGULAR_PAGES = 0x3, 6097 }; 6098 6099 struct mlx5_ifc_query_pages_in_bits { 6100 u8 opcode[0x10]; 6101 u8 reserved_at_10[0x10]; 6102 6103 u8 reserved_at_20[0x10]; 6104 u8 op_mod[0x10]; 6105 6106 u8 embedded_cpu_function[0x1]; 6107 u8 reserved_at_41[0xf]; 6108 u8 function_id[0x10]; 6109 6110 u8 reserved_at_60[0x20]; 6111 }; 6112 6113 struct mlx5_ifc_query_nic_vport_context_out_bits { 6114 u8 status[0x8]; 6115 u8 reserved_at_8[0x18]; 6116 6117 u8 syndrome[0x20]; 6118 6119 u8 reserved_at_40[0x40]; 6120 6121 struct mlx5_ifc_nic_vport_context_bits nic_vport_context; 6122 }; 6123 6124 struct mlx5_ifc_query_nic_vport_context_in_bits { 6125 u8 opcode[0x10]; 6126 u8 reserved_at_10[0x10]; 6127 6128 u8 reserved_at_20[0x10]; 6129 u8 op_mod[0x10]; 6130 6131 u8 other_vport[0x1]; 6132 u8 reserved_at_41[0xf]; 6133 u8 vport_number[0x10]; 6134 6135 u8 reserved_at_60[0x5]; 6136 u8 allowed_list_type[0x3]; 6137 u8 reserved_at_68[0x18]; 6138 }; 6139 6140 struct mlx5_ifc_query_mkey_out_bits { 6141 u8 status[0x8]; 6142 u8 reserved_at_8[0x18]; 6143 6144 u8 syndrome[0x20]; 6145 6146 u8 reserved_at_40[0x40]; 6147 6148 struct mlx5_ifc_mkc_bits memory_key_mkey_entry; 6149 6150 u8 reserved_at_280[0x600]; 6151 6152 u8 bsf0_klm0_pas_mtt0_1[16][0x8]; 6153 6154 u8 bsf1_klm1_pas_mtt2_3[16][0x8]; 6155 }; 6156 6157 struct mlx5_ifc_query_mkey_in_bits { 6158 u8 opcode[0x10]; 6159 u8 reserved_at_10[0x10]; 6160 6161 u8 reserved_at_20[0x10]; 6162 u8 op_mod[0x10]; 6163 6164 u8 reserved_at_40[0x8]; 6165 u8 mkey_index[0x18]; 6166 6167 u8 pg_access[0x1]; 6168 u8 reserved_at_61[0x1f]; 6169 }; 6170 6171 struct mlx5_ifc_query_mad_demux_out_bits { 6172 u8 status[0x8]; 6173 u8 reserved_at_8[0x18]; 6174 6175 u8 syndrome[0x20]; 6176 6177 u8 reserved_at_40[0x40]; 6178 6179 u8 mad_dumux_parameters_block[0x20]; 6180 }; 6181 6182 struct mlx5_ifc_query_mad_demux_in_bits { 6183 u8 opcode[0x10]; 6184 u8 reserved_at_10[0x10]; 6185 6186 u8 reserved_at_20[0x10]; 6187 u8 op_mod[0x10]; 6188 6189 u8 reserved_at_40[0x40]; 6190 }; 6191 6192 struct mlx5_ifc_query_l2_table_entry_out_bits { 6193 u8 status[0x8]; 6194 u8 reserved_at_8[0x18]; 6195 6196 u8 syndrome[0x20]; 6197 6198 u8 reserved_at_40[0xa0]; 6199 6200 u8 reserved_at_e0[0x13]; 6201 u8 vlan_valid[0x1]; 6202 u8 vlan[0xc]; 6203 6204 struct mlx5_ifc_mac_address_layout_bits mac_address; 6205 6206 u8 reserved_at_140[0xc0]; 6207 }; 6208 6209 struct mlx5_ifc_query_l2_table_entry_in_bits { 6210 u8 opcode[0x10]; 6211 u8 reserved_at_10[0x10]; 6212 6213 u8 reserved_at_20[0x10]; 6214 u8 op_mod[0x10]; 6215 6216 u8 reserved_at_40[0x60]; 6217 6218 u8 reserved_at_a0[0x8]; 6219 u8 table_index[0x18]; 6220 6221 u8 reserved_at_c0[0x140]; 6222 }; 6223 6224 struct mlx5_ifc_query_issi_out_bits { 6225 u8 status[0x8]; 6226 u8 reserved_at_8[0x18]; 6227 6228 u8 syndrome[0x20]; 6229 6230 u8 reserved_at_40[0x10]; 6231 u8 current_issi[0x10]; 6232 6233 u8 reserved_at_60[0xa0]; 6234 6235 u8 reserved_at_100[76][0x8]; 6236 u8 supported_issi_dw0[0x20]; 6237 }; 6238 6239 struct mlx5_ifc_query_issi_in_bits { 6240 u8 opcode[0x10]; 6241 u8 reserved_at_10[0x10]; 6242 6243 u8 reserved_at_20[0x10]; 6244 u8 op_mod[0x10]; 6245 6246 u8 reserved_at_40[0x40]; 6247 }; 6248 6249 struct mlx5_ifc_set_driver_version_out_bits { 6250 u8 status[0x8]; 6251 u8 reserved_0[0x18]; 6252 6253 u8 syndrome[0x20]; 6254 u8 reserved_1[0x40]; 6255 }; 6256 6257 struct mlx5_ifc_set_driver_version_in_bits { 6258 u8 opcode[0x10]; 6259 u8 reserved_0[0x10]; 6260 6261 u8 reserved_1[0x10]; 6262 u8 op_mod[0x10]; 6263 6264 u8 reserved_2[0x40]; 6265 u8 driver_version[64][0x8]; 6266 }; 6267 6268 struct mlx5_ifc_query_hca_vport_pkey_out_bits { 6269 u8 status[0x8]; 6270 u8 reserved_at_8[0x18]; 6271 6272 u8 syndrome[0x20]; 6273 6274 u8 reserved_at_40[0x40]; 6275 6276 struct mlx5_ifc_pkey_bits pkey[]; 6277 }; 6278 6279 struct mlx5_ifc_query_hca_vport_pkey_in_bits { 6280 u8 opcode[0x10]; 6281 u8 reserved_at_10[0x10]; 6282 6283 u8 reserved_at_20[0x10]; 6284 u8 op_mod[0x10]; 6285 6286 u8 other_vport[0x1]; 6287 u8 reserved_at_41[0xb]; 6288 u8 port_num[0x4]; 6289 u8 vport_number[0x10]; 6290 6291 u8 reserved_at_60[0x10]; 6292 u8 pkey_index[0x10]; 6293 }; 6294 6295 enum { 6296 MLX5_HCA_VPORT_SEL_PORT_GUID = 1 << 0, 6297 MLX5_HCA_VPORT_SEL_NODE_GUID = 1 << 1, 6298 MLX5_HCA_VPORT_SEL_STATE_POLICY = 1 << 2, 6299 }; 6300 6301 struct mlx5_ifc_query_hca_vport_gid_out_bits { 6302 u8 status[0x8]; 6303 u8 reserved_at_8[0x18]; 6304 6305 u8 syndrome[0x20]; 6306 6307 u8 reserved_at_40[0x20]; 6308 6309 u8 gids_num[0x10]; 6310 u8 reserved_at_70[0x10]; 6311 6312 struct mlx5_ifc_array128_auto_bits gid[]; 6313 }; 6314 6315 struct mlx5_ifc_query_hca_vport_gid_in_bits { 6316 u8 opcode[0x10]; 6317 u8 reserved_at_10[0x10]; 6318 6319 u8 reserved_at_20[0x10]; 6320 u8 op_mod[0x10]; 6321 6322 u8 other_vport[0x1]; 6323 u8 reserved_at_41[0xb]; 6324 u8 port_num[0x4]; 6325 u8 vport_number[0x10]; 6326 6327 u8 reserved_at_60[0x10]; 6328 u8 gid_index[0x10]; 6329 }; 6330 6331 struct mlx5_ifc_query_hca_vport_context_out_bits { 6332 u8 status[0x8]; 6333 u8 reserved_at_8[0x18]; 6334 6335 u8 syndrome[0x20]; 6336 6337 u8 reserved_at_40[0x40]; 6338 6339 struct mlx5_ifc_hca_vport_context_bits hca_vport_context; 6340 }; 6341 6342 struct mlx5_ifc_query_hca_vport_context_in_bits { 6343 u8 opcode[0x10]; 6344 u8 reserved_at_10[0x10]; 6345 6346 u8 reserved_at_20[0x10]; 6347 u8 op_mod[0x10]; 6348 6349 u8 other_vport[0x1]; 6350 u8 reserved_at_41[0xb]; 6351 u8 port_num[0x4]; 6352 u8 vport_number[0x10]; 6353 6354 u8 reserved_at_60[0x20]; 6355 }; 6356 6357 struct mlx5_ifc_query_hca_cap_out_bits { 6358 u8 status[0x8]; 6359 u8 reserved_at_8[0x18]; 6360 6361 u8 syndrome[0x20]; 6362 6363 u8 reserved_at_40[0x40]; 6364 6365 union mlx5_ifc_hca_cap_union_bits capability; 6366 }; 6367 6368 struct mlx5_ifc_query_hca_cap_in_bits { 6369 u8 opcode[0x10]; 6370 u8 reserved_at_10[0x10]; 6371 6372 u8 reserved_at_20[0x10]; 6373 u8 op_mod[0x10]; 6374 6375 u8 other_function[0x1]; 6376 u8 ec_vf_function[0x1]; 6377 u8 reserved_at_42[0x1]; 6378 u8 function_id_type[0x1]; 6379 u8 reserved_at_44[0xc]; 6380 u8 function_id[0x10]; 6381 6382 u8 reserved_at_60[0x20]; 6383 }; 6384 6385 struct mlx5_ifc_other_hca_cap_bits { 6386 u8 roce[0x1]; 6387 u8 reserved_at_1[0x27f]; 6388 }; 6389 6390 struct mlx5_ifc_query_other_hca_cap_out_bits { 6391 u8 status[0x8]; 6392 u8 reserved_at_8[0x18]; 6393 6394 u8 syndrome[0x20]; 6395 6396 u8 reserved_at_40[0x40]; 6397 6398 struct mlx5_ifc_other_hca_cap_bits other_capability; 6399 }; 6400 6401 struct mlx5_ifc_query_other_hca_cap_in_bits { 6402 u8 opcode[0x10]; 6403 u8 reserved_at_10[0x10]; 6404 6405 u8 reserved_at_20[0x10]; 6406 u8 op_mod[0x10]; 6407 6408 u8 reserved_at_40[0x10]; 6409 u8 function_id[0x10]; 6410 6411 u8 reserved_at_60[0x20]; 6412 }; 6413 6414 struct mlx5_ifc_modify_other_hca_cap_out_bits { 6415 u8 status[0x8]; 6416 u8 reserved_at_8[0x18]; 6417 6418 u8 syndrome[0x20]; 6419 6420 u8 reserved_at_40[0x40]; 6421 }; 6422 6423 struct mlx5_ifc_modify_other_hca_cap_in_bits { 6424 u8 opcode[0x10]; 6425 u8 reserved_at_10[0x10]; 6426 6427 u8 reserved_at_20[0x10]; 6428 u8 op_mod[0x10]; 6429 6430 u8 reserved_at_40[0x10]; 6431 u8 function_id[0x10]; 6432 u8 field_select[0x20]; 6433 6434 struct mlx5_ifc_other_hca_cap_bits other_capability; 6435 }; 6436 6437 struct mlx5_ifc_sw_owner_icm_root_params_bits { 6438 u8 sw_owner_icm_root_1[0x40]; 6439 6440 u8 sw_owner_icm_root_0[0x40]; 6441 }; 6442 6443 struct mlx5_ifc_rtc_params_bits { 6444 u8 rtc_id_0[0x20]; 6445 6446 u8 rtc_id_1[0x20]; 6447 6448 u8 reserved_at_40[0x40]; 6449 }; 6450 6451 struct mlx5_ifc_flow_table_context_bits { 6452 u8 reformat_en[0x1]; 6453 u8 decap_en[0x1]; 6454 u8 sw_owner[0x1]; 6455 u8 termination_table[0x1]; 6456 u8 table_miss_action[0x4]; 6457 u8 level[0x8]; 6458 u8 rtc_valid[0x1]; 6459 u8 reserved_at_11[0x7]; 6460 u8 log_size[0x8]; 6461 6462 u8 reserved_at_20[0x8]; 6463 u8 table_miss_id[0x18]; 6464 6465 u8 reserved_at_40[0x8]; 6466 u8 lag_master_next_table_id[0x18]; 6467 6468 u8 reserved_at_60[0x60]; 6469 6470 union { 6471 struct mlx5_ifc_sw_owner_icm_root_params_bits sws; 6472 struct mlx5_ifc_rtc_params_bits hws; 6473 }; 6474 }; 6475 6476 struct mlx5_ifc_query_flow_table_out_bits { 6477 u8 status[0x8]; 6478 u8 reserved_at_8[0x18]; 6479 6480 u8 syndrome[0x20]; 6481 6482 u8 reserved_at_40[0x80]; 6483 6484 struct mlx5_ifc_flow_table_context_bits flow_table_context; 6485 }; 6486 6487 struct mlx5_ifc_query_flow_table_in_bits { 6488 u8 opcode[0x10]; 6489 u8 reserved_at_10[0x10]; 6490 6491 u8 reserved_at_20[0x10]; 6492 u8 op_mod[0x10]; 6493 6494 u8 reserved_at_40[0x40]; 6495 6496 u8 table_type[0x8]; 6497 u8 reserved_at_88[0x18]; 6498 6499 u8 reserved_at_a0[0x8]; 6500 u8 table_id[0x18]; 6501 6502 u8 reserved_at_c0[0x140]; 6503 }; 6504 6505 struct mlx5_ifc_query_fte_out_bits { 6506 u8 status[0x8]; 6507 u8 reserved_at_8[0x18]; 6508 6509 u8 syndrome[0x20]; 6510 6511 u8 reserved_at_40[0x1c0]; 6512 6513 struct mlx5_ifc_flow_context_bits flow_context; 6514 }; 6515 6516 struct mlx5_ifc_query_fte_in_bits { 6517 u8 opcode[0x10]; 6518 u8 reserved_at_10[0x10]; 6519 6520 u8 reserved_at_20[0x10]; 6521 u8 op_mod[0x10]; 6522 6523 u8 reserved_at_40[0x40]; 6524 6525 u8 table_type[0x8]; 6526 u8 reserved_at_88[0x18]; 6527 6528 u8 reserved_at_a0[0x8]; 6529 u8 table_id[0x18]; 6530 6531 u8 reserved_at_c0[0x40]; 6532 6533 u8 flow_index[0x20]; 6534 6535 u8 reserved_at_120[0xe0]; 6536 }; 6537 6538 struct mlx5_ifc_match_definer_format_0_bits { 6539 u8 reserved_at_0[0x100]; 6540 6541 u8 metadata_reg_c_0[0x20]; 6542 6543 u8 metadata_reg_c_1[0x20]; 6544 6545 u8 outer_dmac_47_16[0x20]; 6546 6547 u8 outer_dmac_15_0[0x10]; 6548 u8 outer_ethertype[0x10]; 6549 6550 u8 reserved_at_180[0x1]; 6551 u8 sx_sniffer[0x1]; 6552 u8 functional_lb[0x1]; 6553 u8 outer_ip_frag[0x1]; 6554 u8 outer_qp_type[0x2]; 6555 u8 outer_encap_type[0x2]; 6556 u8 port_number[0x2]; 6557 u8 outer_l3_type[0x2]; 6558 u8 outer_l4_type[0x2]; 6559 u8 outer_first_vlan_type[0x2]; 6560 u8 outer_first_vlan_prio[0x3]; 6561 u8 outer_first_vlan_cfi[0x1]; 6562 u8 outer_first_vlan_vid[0xc]; 6563 6564 u8 outer_l4_type_ext[0x4]; 6565 u8 reserved_at_1a4[0x2]; 6566 u8 outer_ipsec_layer[0x2]; 6567 u8 outer_l2_type[0x2]; 6568 u8 force_lb[0x1]; 6569 u8 outer_l2_ok[0x1]; 6570 u8 outer_l3_ok[0x1]; 6571 u8 outer_l4_ok[0x1]; 6572 u8 outer_second_vlan_type[0x2]; 6573 u8 outer_second_vlan_prio[0x3]; 6574 u8 outer_second_vlan_cfi[0x1]; 6575 u8 outer_second_vlan_vid[0xc]; 6576 6577 u8 outer_smac_47_16[0x20]; 6578 6579 u8 outer_smac_15_0[0x10]; 6580 u8 inner_ipv4_checksum_ok[0x1]; 6581 u8 inner_l4_checksum_ok[0x1]; 6582 u8 outer_ipv4_checksum_ok[0x1]; 6583 u8 outer_l4_checksum_ok[0x1]; 6584 u8 inner_l3_ok[0x1]; 6585 u8 inner_l4_ok[0x1]; 6586 u8 outer_l3_ok_duplicate[0x1]; 6587 u8 outer_l4_ok_duplicate[0x1]; 6588 u8 outer_tcp_cwr[0x1]; 6589 u8 outer_tcp_ece[0x1]; 6590 u8 outer_tcp_urg[0x1]; 6591 u8 outer_tcp_ack[0x1]; 6592 u8 outer_tcp_psh[0x1]; 6593 u8 outer_tcp_rst[0x1]; 6594 u8 outer_tcp_syn[0x1]; 6595 u8 outer_tcp_fin[0x1]; 6596 }; 6597 6598 struct mlx5_ifc_match_definer_format_22_bits { 6599 u8 reserved_at_0[0x100]; 6600 6601 u8 outer_ip_src_addr[0x20]; 6602 6603 u8 outer_ip_dest_addr[0x20]; 6604 6605 u8 outer_l4_sport[0x10]; 6606 u8 outer_l4_dport[0x10]; 6607 6608 u8 reserved_at_160[0x1]; 6609 u8 sx_sniffer[0x1]; 6610 u8 functional_lb[0x1]; 6611 u8 outer_ip_frag[0x1]; 6612 u8 outer_qp_type[0x2]; 6613 u8 outer_encap_type[0x2]; 6614 u8 port_number[0x2]; 6615 u8 outer_l3_type[0x2]; 6616 u8 outer_l4_type[0x2]; 6617 u8 outer_first_vlan_type[0x2]; 6618 u8 outer_first_vlan_prio[0x3]; 6619 u8 outer_first_vlan_cfi[0x1]; 6620 u8 outer_first_vlan_vid[0xc]; 6621 6622 u8 metadata_reg_c_0[0x20]; 6623 6624 u8 outer_dmac_47_16[0x20]; 6625 6626 u8 outer_smac_47_16[0x20]; 6627 6628 u8 outer_smac_15_0[0x10]; 6629 u8 outer_dmac_15_0[0x10]; 6630 }; 6631 6632 struct mlx5_ifc_match_definer_format_23_bits { 6633 u8 reserved_at_0[0x100]; 6634 6635 u8 inner_ip_src_addr[0x20]; 6636 6637 u8 inner_ip_dest_addr[0x20]; 6638 6639 u8 inner_l4_sport[0x10]; 6640 u8 inner_l4_dport[0x10]; 6641 6642 u8 reserved_at_160[0x1]; 6643 u8 sx_sniffer[0x1]; 6644 u8 functional_lb[0x1]; 6645 u8 inner_ip_frag[0x1]; 6646 u8 inner_qp_type[0x2]; 6647 u8 inner_encap_type[0x2]; 6648 u8 port_number[0x2]; 6649 u8 inner_l3_type[0x2]; 6650 u8 inner_l4_type[0x2]; 6651 u8 inner_first_vlan_type[0x2]; 6652 u8 inner_first_vlan_prio[0x3]; 6653 u8 inner_first_vlan_cfi[0x1]; 6654 u8 inner_first_vlan_vid[0xc]; 6655 6656 u8 tunnel_header_0[0x20]; 6657 6658 u8 inner_dmac_47_16[0x20]; 6659 6660 u8 inner_smac_47_16[0x20]; 6661 6662 u8 inner_smac_15_0[0x10]; 6663 u8 inner_dmac_15_0[0x10]; 6664 }; 6665 6666 struct mlx5_ifc_match_definer_format_29_bits { 6667 u8 reserved_at_0[0xc0]; 6668 6669 u8 outer_ip_dest_addr[0x80]; 6670 6671 u8 outer_ip_src_addr[0x80]; 6672 6673 u8 outer_l4_sport[0x10]; 6674 u8 outer_l4_dport[0x10]; 6675 6676 u8 reserved_at_1e0[0x20]; 6677 }; 6678 6679 struct mlx5_ifc_match_definer_format_30_bits { 6680 u8 reserved_at_0[0xa0]; 6681 6682 u8 outer_ip_dest_addr[0x80]; 6683 6684 u8 outer_ip_src_addr[0x80]; 6685 6686 u8 outer_dmac_47_16[0x20]; 6687 6688 u8 outer_smac_47_16[0x20]; 6689 6690 u8 outer_smac_15_0[0x10]; 6691 u8 outer_dmac_15_0[0x10]; 6692 }; 6693 6694 struct mlx5_ifc_match_definer_format_31_bits { 6695 u8 reserved_at_0[0xc0]; 6696 6697 u8 inner_ip_dest_addr[0x80]; 6698 6699 u8 inner_ip_src_addr[0x80]; 6700 6701 u8 inner_l4_sport[0x10]; 6702 u8 inner_l4_dport[0x10]; 6703 6704 u8 reserved_at_1e0[0x20]; 6705 }; 6706 6707 struct mlx5_ifc_match_definer_format_32_bits { 6708 u8 reserved_at_0[0xa0]; 6709 6710 u8 inner_ip_dest_addr[0x80]; 6711 6712 u8 inner_ip_src_addr[0x80]; 6713 6714 u8 inner_dmac_47_16[0x20]; 6715 6716 u8 inner_smac_47_16[0x20]; 6717 6718 u8 inner_smac_15_0[0x10]; 6719 u8 inner_dmac_15_0[0x10]; 6720 }; 6721 6722 enum { 6723 MLX5_IFC_DEFINER_FORMAT_ID_SELECT = 61, 6724 }; 6725 6726 #define MLX5_IFC_DEFINER_FORMAT_OFFSET_UNUSED 0x0 6727 #define MLX5_IFC_DEFINER_FORMAT_OFFSET_OUTER_ETH_PKT_LEN 0x48 6728 #define MLX5_IFC_DEFINER_DW_SELECTORS_NUM 9 6729 #define MLX5_IFC_DEFINER_BYTE_SELECTORS_NUM 8 6730 6731 struct mlx5_ifc_match_definer_match_mask_bits { 6732 u8 reserved_at_1c0[5][0x20]; 6733 u8 match_dw_8[0x20]; 6734 u8 match_dw_7[0x20]; 6735 u8 match_dw_6[0x20]; 6736 u8 match_dw_5[0x20]; 6737 u8 match_dw_4[0x20]; 6738 u8 match_dw_3[0x20]; 6739 u8 match_dw_2[0x20]; 6740 u8 match_dw_1[0x20]; 6741 u8 match_dw_0[0x20]; 6742 6743 u8 match_byte_7[0x8]; 6744 u8 match_byte_6[0x8]; 6745 u8 match_byte_5[0x8]; 6746 u8 match_byte_4[0x8]; 6747 6748 u8 match_byte_3[0x8]; 6749 u8 match_byte_2[0x8]; 6750 u8 match_byte_1[0x8]; 6751 u8 match_byte_0[0x8]; 6752 }; 6753 6754 struct mlx5_ifc_match_definer_bits { 6755 u8 modify_field_select[0x40]; 6756 6757 u8 reserved_at_40[0x40]; 6758 6759 u8 reserved_at_80[0x10]; 6760 u8 format_id[0x10]; 6761 6762 u8 reserved_at_a0[0x60]; 6763 6764 u8 format_select_dw3[0x8]; 6765 u8 format_select_dw2[0x8]; 6766 u8 format_select_dw1[0x8]; 6767 u8 format_select_dw0[0x8]; 6768 6769 u8 format_select_dw7[0x8]; 6770 u8 format_select_dw6[0x8]; 6771 u8 format_select_dw5[0x8]; 6772 u8 format_select_dw4[0x8]; 6773 6774 u8 reserved_at_100[0x18]; 6775 u8 format_select_dw8[0x8]; 6776 6777 u8 reserved_at_120[0x20]; 6778 6779 u8 format_select_byte3[0x8]; 6780 u8 format_select_byte2[0x8]; 6781 u8 format_select_byte1[0x8]; 6782 u8 format_select_byte0[0x8]; 6783 6784 u8 format_select_byte7[0x8]; 6785 u8 format_select_byte6[0x8]; 6786 u8 format_select_byte5[0x8]; 6787 u8 format_select_byte4[0x8]; 6788 6789 u8 reserved_at_180[0x40]; 6790 6791 union { 6792 struct { 6793 u8 match_mask[16][0x20]; 6794 }; 6795 struct mlx5_ifc_match_definer_match_mask_bits match_mask_format; 6796 }; 6797 }; 6798 6799 struct mlx5_ifc_general_obj_create_param_bits { 6800 u8 alias_object[0x1]; 6801 u8 reserved_at_1[0x2]; 6802 u8 log_obj_range[0x5]; 6803 u8 reserved_at_8[0x18]; 6804 }; 6805 6806 struct mlx5_ifc_general_obj_query_param_bits { 6807 u8 alias_object[0x1]; 6808 u8 obj_offset[0x1f]; 6809 }; 6810 6811 struct mlx5_ifc_general_obj_in_cmd_hdr_bits { 6812 u8 opcode[0x10]; 6813 u8 uid[0x10]; 6814 6815 u8 vhca_tunnel_id[0x10]; 6816 u8 obj_type[0x10]; 6817 6818 u8 obj_id[0x20]; 6819 6820 union { 6821 struct mlx5_ifc_general_obj_create_param_bits create; 6822 struct mlx5_ifc_general_obj_query_param_bits query; 6823 } op_param; 6824 }; 6825 6826 struct mlx5_ifc_general_obj_out_cmd_hdr_bits { 6827 u8 status[0x8]; 6828 u8 reserved_at_8[0x18]; 6829 6830 u8 syndrome[0x20]; 6831 6832 u8 obj_id[0x20]; 6833 6834 u8 reserved_at_60[0x20]; 6835 }; 6836 6837 struct mlx5_ifc_allow_other_vhca_access_in_bits { 6838 u8 opcode[0x10]; 6839 u8 uid[0x10]; 6840 u8 reserved_at_20[0x10]; 6841 u8 op_mod[0x10]; 6842 u8 reserved_at_40[0x50]; 6843 u8 object_type_to_be_accessed[0x10]; 6844 u8 object_id_to_be_accessed[0x20]; 6845 u8 reserved_at_c0[0x40]; 6846 union { 6847 u8 access_key_raw[0x100]; 6848 u8 access_key[8][0x20]; 6849 }; 6850 }; 6851 6852 struct mlx5_ifc_allow_other_vhca_access_out_bits { 6853 u8 status[0x8]; 6854 u8 reserved_at_8[0x18]; 6855 u8 syndrome[0x20]; 6856 u8 reserved_at_40[0x40]; 6857 }; 6858 6859 struct mlx5_ifc_modify_header_arg_bits { 6860 u8 reserved_at_0[0x80]; 6861 6862 u8 reserved_at_80[0x8]; 6863 u8 access_pd[0x18]; 6864 }; 6865 6866 struct mlx5_ifc_create_modify_header_arg_in_bits { 6867 struct mlx5_ifc_general_obj_in_cmd_hdr_bits hdr; 6868 struct mlx5_ifc_modify_header_arg_bits arg; 6869 }; 6870 6871 struct mlx5_ifc_create_match_definer_in_bits { 6872 struct mlx5_ifc_general_obj_in_cmd_hdr_bits general_obj_in_cmd_hdr; 6873 6874 struct mlx5_ifc_match_definer_bits obj_context; 6875 }; 6876 6877 struct mlx5_ifc_create_match_definer_out_bits { 6878 struct mlx5_ifc_general_obj_out_cmd_hdr_bits general_obj_out_cmd_hdr; 6879 }; 6880 6881 struct mlx5_ifc_alias_context_bits { 6882 u8 vhca_id_to_be_accessed[0x10]; 6883 u8 reserved_at_10[0xd]; 6884 u8 status[0x3]; 6885 u8 object_id_to_be_accessed[0x20]; 6886 u8 reserved_at_40[0x40]; 6887 union { 6888 u8 access_key_raw[0x100]; 6889 u8 access_key[8][0x20]; 6890 }; 6891 u8 metadata[0x80]; 6892 }; 6893 6894 struct mlx5_ifc_create_alias_obj_in_bits { 6895 struct mlx5_ifc_general_obj_in_cmd_hdr_bits hdr; 6896 struct mlx5_ifc_alias_context_bits alias_ctx; 6897 }; 6898 6899 enum { 6900 MLX5_QUERY_FLOW_GROUP_OUT_MATCH_CRITERIA_ENABLE_OUTER_HEADERS = 0x0, 6901 MLX5_QUERY_FLOW_GROUP_OUT_MATCH_CRITERIA_ENABLE_MISC_PARAMETERS = 0x1, 6902 MLX5_QUERY_FLOW_GROUP_OUT_MATCH_CRITERIA_ENABLE_INNER_HEADERS = 0x2, 6903 MLX5_QUERY_FLOW_GROUP_IN_MATCH_CRITERIA_ENABLE_MISC_PARAMETERS_2 = 0x3, 6904 MLX5_QUERY_FLOW_GROUP_IN_MATCH_CRITERIA_ENABLE_MISC_PARAMETERS_3 = 0x4, 6905 MLX5_QUERY_FLOW_GROUP_IN_MATCH_CRITERIA_ENABLE_MISC_PARAMETERS_4 = 0x5, 6906 MLX5_QUERY_FLOW_GROUP_IN_MATCH_CRITERIA_ENABLE_MISC_PARAMETERS_5 = 0x6, 6907 }; 6908 6909 struct mlx5_ifc_query_flow_group_out_bits { 6910 u8 status[0x8]; 6911 u8 reserved_at_8[0x18]; 6912 6913 u8 syndrome[0x20]; 6914 6915 u8 reserved_at_40[0xa0]; 6916 6917 u8 start_flow_index[0x20]; 6918 6919 u8 reserved_at_100[0x20]; 6920 6921 u8 end_flow_index[0x20]; 6922 6923 u8 reserved_at_140[0xa0]; 6924 6925 u8 reserved_at_1e0[0x18]; 6926 u8 match_criteria_enable[0x8]; 6927 6928 struct mlx5_ifc_fte_match_param_bits match_criteria; 6929 6930 u8 reserved_at_1200[0xe00]; 6931 }; 6932 6933 struct mlx5_ifc_query_flow_group_in_bits { 6934 u8 opcode[0x10]; 6935 u8 reserved_at_10[0x10]; 6936 6937 u8 reserved_at_20[0x10]; 6938 u8 op_mod[0x10]; 6939 6940 u8 reserved_at_40[0x40]; 6941 6942 u8 table_type[0x8]; 6943 u8 reserved_at_88[0x18]; 6944 6945 u8 reserved_at_a0[0x8]; 6946 u8 table_id[0x18]; 6947 6948 u8 group_id[0x20]; 6949 6950 u8 reserved_at_e0[0x120]; 6951 }; 6952 6953 struct mlx5_ifc_query_flow_counter_out_bits { 6954 u8 status[0x8]; 6955 u8 reserved_at_8[0x18]; 6956 6957 u8 syndrome[0x20]; 6958 6959 u8 reserved_at_40[0x40]; 6960 6961 struct mlx5_ifc_traffic_counter_bits flow_statistics[]; 6962 }; 6963 6964 struct mlx5_ifc_query_flow_counter_in_bits { 6965 u8 opcode[0x10]; 6966 u8 reserved_at_10[0x10]; 6967 6968 u8 reserved_at_20[0x10]; 6969 u8 op_mod[0x10]; 6970 6971 u8 reserved_at_40[0x80]; 6972 6973 u8 clear[0x1]; 6974 u8 reserved_at_c1[0xf]; 6975 u8 num_of_counters[0x10]; 6976 6977 u8 flow_counter_id[0x20]; 6978 }; 6979 6980 struct mlx5_ifc_query_esw_vport_context_out_bits { 6981 u8 status[0x8]; 6982 u8 reserved_at_8[0x18]; 6983 6984 u8 syndrome[0x20]; 6985 6986 u8 reserved_at_40[0x40]; 6987 6988 struct mlx5_ifc_esw_vport_context_bits esw_vport_context; 6989 }; 6990 6991 struct mlx5_ifc_query_esw_vport_context_in_bits { 6992 u8 opcode[0x10]; 6993 u8 reserved_at_10[0x10]; 6994 6995 u8 reserved_at_20[0x10]; 6996 u8 op_mod[0x10]; 6997 6998 u8 other_vport[0x1]; 6999 u8 reserved_at_41[0xf]; 7000 u8 vport_number[0x10]; 7001 7002 u8 reserved_at_60[0x20]; 7003 }; 7004 7005 struct mlx5_ifc_destroy_esw_vport_out_bits { 7006 u8 status[0x8]; 7007 u8 reserved_at_8[0x18]; 7008 7009 u8 syndrome[0x20]; 7010 7011 u8 reserved_at_40[0x20]; 7012 }; 7013 7014 struct mlx5_ifc_destroy_esw_vport_in_bits { 7015 u8 opcode[0x10]; 7016 u8 uid[0x10]; 7017 7018 u8 reserved_at_20[0x10]; 7019 u8 op_mod[0x10]; 7020 7021 u8 reserved_at_40[0x10]; 7022 u8 vport_num[0x10]; 7023 7024 u8 reserved_at_60[0x20]; 7025 }; 7026 7027 struct mlx5_ifc_modify_esw_vport_context_out_bits { 7028 u8 status[0x8]; 7029 u8 reserved_at_8[0x18]; 7030 7031 u8 syndrome[0x20]; 7032 7033 u8 reserved_at_40[0x40]; 7034 }; 7035 7036 struct mlx5_ifc_esw_vport_context_fields_select_bits { 7037 u8 reserved_at_0[0x1b]; 7038 u8 fdb_to_vport_reg_c_id[0x1]; 7039 u8 vport_cvlan_insert[0x1]; 7040 u8 vport_svlan_insert[0x1]; 7041 u8 vport_cvlan_strip[0x1]; 7042 u8 vport_svlan_strip[0x1]; 7043 }; 7044 7045 struct mlx5_ifc_modify_esw_vport_context_in_bits { 7046 u8 opcode[0x10]; 7047 u8 reserved_at_10[0x10]; 7048 7049 u8 reserved_at_20[0x10]; 7050 u8 op_mod[0x10]; 7051 7052 u8 other_vport[0x1]; 7053 u8 reserved_at_41[0xf]; 7054 u8 vport_number[0x10]; 7055 7056 struct mlx5_ifc_esw_vport_context_fields_select_bits field_select; 7057 7058 struct mlx5_ifc_esw_vport_context_bits esw_vport_context; 7059 }; 7060 7061 struct mlx5_ifc_query_eq_out_bits { 7062 u8 status[0x8]; 7063 u8 reserved_at_8[0x18]; 7064 7065 u8 syndrome[0x20]; 7066 7067 u8 reserved_at_40[0x40]; 7068 7069 struct mlx5_ifc_eqc_bits eq_context_entry; 7070 7071 u8 reserved_at_280[0x40]; 7072 7073 u8 event_bitmask[0x40]; 7074 7075 u8 reserved_at_300[0x580]; 7076 7077 u8 pas[][0x40]; 7078 }; 7079 7080 struct mlx5_ifc_query_eq_in_bits { 7081 u8 opcode[0x10]; 7082 u8 reserved_at_10[0x10]; 7083 7084 u8 reserved_at_20[0x10]; 7085 u8 op_mod[0x10]; 7086 7087 u8 reserved_at_40[0x18]; 7088 u8 eq_number[0x8]; 7089 7090 u8 reserved_at_60[0x20]; 7091 }; 7092 7093 struct mlx5_ifc_packet_reformat_context_in_bits { 7094 u8 reformat_type[0x8]; 7095 u8 reserved_at_8[0x4]; 7096 u8 reformat_param_0[0x4]; 7097 u8 reserved_at_10[0x6]; 7098 u8 reformat_data_size[0xa]; 7099 7100 u8 reformat_param_1[0x8]; 7101 u8 reserved_at_28[0x8]; 7102 u8 reformat_data[2][0x8]; 7103 7104 u8 more_reformat_data[][0x8]; 7105 }; 7106 7107 struct mlx5_ifc_query_packet_reformat_context_out_bits { 7108 u8 status[0x8]; 7109 u8 reserved_at_8[0x18]; 7110 7111 u8 syndrome[0x20]; 7112 7113 u8 reserved_at_40[0xa0]; 7114 7115 struct mlx5_ifc_packet_reformat_context_in_bits packet_reformat_context[]; 7116 }; 7117 7118 struct mlx5_ifc_query_packet_reformat_context_in_bits { 7119 u8 opcode[0x10]; 7120 u8 reserved_at_10[0x10]; 7121 7122 u8 reserved_at_20[0x10]; 7123 u8 op_mod[0x10]; 7124 7125 u8 packet_reformat_id[0x20]; 7126 7127 u8 reserved_at_60[0xa0]; 7128 }; 7129 7130 struct mlx5_ifc_alloc_packet_reformat_context_out_bits { 7131 u8 status[0x8]; 7132 u8 reserved_at_8[0x18]; 7133 7134 u8 syndrome[0x20]; 7135 7136 u8 packet_reformat_id[0x20]; 7137 7138 u8 reserved_at_60[0x20]; 7139 }; 7140 7141 enum { 7142 MLX5_REFORMAT_CONTEXT_ANCHOR_MAC_START = 0x1, 7143 MLX5_REFORMAT_CONTEXT_ANCHOR_VLAN_START = 0x2, 7144 MLX5_REFORMAT_CONTEXT_ANCHOR_IP_START = 0x7, 7145 MLX5_REFORMAT_CONTEXT_ANCHOR_TCP_UDP_START = 0x9, 7146 }; 7147 7148 enum mlx5_reformat_ctx_type { 7149 MLX5_REFORMAT_TYPE_L2_TO_VXLAN = 0x0, 7150 MLX5_REFORMAT_TYPE_L2_TO_NVGRE = 0x1, 7151 MLX5_REFORMAT_TYPE_L2_TO_L2_TUNNEL = 0x2, 7152 MLX5_REFORMAT_TYPE_L3_TUNNEL_TO_L2 = 0x3, 7153 MLX5_REFORMAT_TYPE_L2_TO_L3_TUNNEL = 0x4, 7154 MLX5_REFORMAT_TYPE_ADD_ESP_TRANSPORT_OVER_IPV4 = 0x5, 7155 MLX5_REFORMAT_TYPE_L2_TO_L3_ESP_TUNNEL = 0x6, 7156 MLX5_REFORMAT_TYPE_ADD_ESP_TRANSPORT_OVER_UDPV4 = 0x7, 7157 MLX5_REFORMAT_TYPE_DEL_ESP_TRANSPORT = 0x8, 7158 MLX5_REFORMAT_TYPE_L3_ESP_TUNNEL_TO_L2 = 0x9, 7159 MLX5_REFORMAT_TYPE_DEL_ESP_TRANSPORT_OVER_UDP = 0xa, 7160 MLX5_REFORMAT_TYPE_ADD_ESP_TRANSPORT_OVER_IPV6 = 0xb, 7161 MLX5_REFORMAT_TYPE_ADD_ESP_TRANSPORT_OVER_UDPV6 = 0xc, 7162 MLX5_REFORMAT_TYPE_INSERT_HDR = 0xf, 7163 MLX5_REFORMAT_TYPE_REMOVE_HDR = 0x10, 7164 MLX5_REFORMAT_TYPE_ADD_MACSEC = 0x11, 7165 MLX5_REFORMAT_TYPE_DEL_MACSEC = 0x12, 7166 }; 7167 7168 struct mlx5_ifc_alloc_packet_reformat_context_in_bits { 7169 u8 opcode[0x10]; 7170 u8 reserved_at_10[0x10]; 7171 7172 u8 reserved_at_20[0x10]; 7173 u8 op_mod[0x10]; 7174 7175 u8 reserved_at_40[0xa0]; 7176 7177 struct mlx5_ifc_packet_reformat_context_in_bits packet_reformat_context; 7178 }; 7179 7180 struct mlx5_ifc_dealloc_packet_reformat_context_out_bits { 7181 u8 status[0x8]; 7182 u8 reserved_at_8[0x18]; 7183 7184 u8 syndrome[0x20]; 7185 7186 u8 reserved_at_40[0x40]; 7187 }; 7188 7189 struct mlx5_ifc_dealloc_packet_reformat_context_in_bits { 7190 u8 opcode[0x10]; 7191 u8 reserved_at_10[0x10]; 7192 7193 u8 reserved_20[0x10]; 7194 u8 op_mod[0x10]; 7195 7196 u8 packet_reformat_id[0x20]; 7197 7198 u8 reserved_60[0x20]; 7199 }; 7200 7201 struct mlx5_ifc_set_action_in_bits { 7202 u8 action_type[0x4]; 7203 u8 field[0xc]; 7204 u8 reserved_at_10[0x3]; 7205 u8 offset[0x5]; 7206 u8 reserved_at_18[0x3]; 7207 u8 length[0x5]; 7208 7209 u8 data[0x20]; 7210 }; 7211 7212 struct mlx5_ifc_add_action_in_bits { 7213 u8 action_type[0x4]; 7214 u8 field[0xc]; 7215 u8 reserved_at_10[0x10]; 7216 7217 u8 data[0x20]; 7218 }; 7219 7220 struct mlx5_ifc_copy_action_in_bits { 7221 u8 action_type[0x4]; 7222 u8 src_field[0xc]; 7223 u8 reserved_at_10[0x3]; 7224 u8 src_offset[0x5]; 7225 u8 reserved_at_18[0x3]; 7226 u8 length[0x5]; 7227 7228 u8 reserved_at_20[0x4]; 7229 u8 dst_field[0xc]; 7230 u8 reserved_at_30[0x3]; 7231 u8 dst_offset[0x5]; 7232 u8 reserved_at_38[0x8]; 7233 }; 7234 7235 union mlx5_ifc_set_add_copy_action_in_auto_bits { 7236 struct mlx5_ifc_set_action_in_bits set_action_in; 7237 struct mlx5_ifc_add_action_in_bits add_action_in; 7238 struct mlx5_ifc_copy_action_in_bits copy_action_in; 7239 u8 reserved_at_0[0x40]; 7240 }; 7241 7242 enum { 7243 MLX5_ACTION_TYPE_SET = 0x1, 7244 MLX5_ACTION_TYPE_ADD = 0x2, 7245 MLX5_ACTION_TYPE_COPY = 0x3, 7246 }; 7247 7248 enum { 7249 MLX5_ACTION_IN_FIELD_OUT_SMAC_47_16 = 0x1, 7250 MLX5_ACTION_IN_FIELD_OUT_SMAC_15_0 = 0x2, 7251 MLX5_ACTION_IN_FIELD_OUT_ETHERTYPE = 0x3, 7252 MLX5_ACTION_IN_FIELD_OUT_DMAC_47_16 = 0x4, 7253 MLX5_ACTION_IN_FIELD_OUT_DMAC_15_0 = 0x5, 7254 MLX5_ACTION_IN_FIELD_OUT_IP_DSCP = 0x6, 7255 MLX5_ACTION_IN_FIELD_OUT_TCP_FLAGS = 0x7, 7256 MLX5_ACTION_IN_FIELD_OUT_TCP_SPORT = 0x8, 7257 MLX5_ACTION_IN_FIELD_OUT_TCP_DPORT = 0x9, 7258 MLX5_ACTION_IN_FIELD_OUT_IP_TTL = 0xa, 7259 MLX5_ACTION_IN_FIELD_OUT_UDP_SPORT = 0xb, 7260 MLX5_ACTION_IN_FIELD_OUT_UDP_DPORT = 0xc, 7261 MLX5_ACTION_IN_FIELD_OUT_SIPV6_127_96 = 0xd, 7262 MLX5_ACTION_IN_FIELD_OUT_SIPV6_95_64 = 0xe, 7263 MLX5_ACTION_IN_FIELD_OUT_SIPV6_63_32 = 0xf, 7264 MLX5_ACTION_IN_FIELD_OUT_SIPV6_31_0 = 0x10, 7265 MLX5_ACTION_IN_FIELD_OUT_DIPV6_127_96 = 0x11, 7266 MLX5_ACTION_IN_FIELD_OUT_DIPV6_95_64 = 0x12, 7267 MLX5_ACTION_IN_FIELD_OUT_DIPV6_63_32 = 0x13, 7268 MLX5_ACTION_IN_FIELD_OUT_DIPV6_31_0 = 0x14, 7269 MLX5_ACTION_IN_FIELD_OUT_SIPV4 = 0x15, 7270 MLX5_ACTION_IN_FIELD_OUT_DIPV4 = 0x16, 7271 MLX5_ACTION_IN_FIELD_OUT_FIRST_VID = 0x17, 7272 MLX5_ACTION_IN_FIELD_OUT_IPV6_HOPLIMIT = 0x47, 7273 MLX5_ACTION_IN_FIELD_METADATA_REG_A = 0x49, 7274 MLX5_ACTION_IN_FIELD_METADATA_REG_B = 0x50, 7275 MLX5_ACTION_IN_FIELD_METADATA_REG_C_0 = 0x51, 7276 MLX5_ACTION_IN_FIELD_METADATA_REG_C_1 = 0x52, 7277 MLX5_ACTION_IN_FIELD_METADATA_REG_C_2 = 0x53, 7278 MLX5_ACTION_IN_FIELD_METADATA_REG_C_3 = 0x54, 7279 MLX5_ACTION_IN_FIELD_METADATA_REG_C_4 = 0x55, 7280 MLX5_ACTION_IN_FIELD_METADATA_REG_C_5 = 0x56, 7281 MLX5_ACTION_IN_FIELD_METADATA_REG_C_6 = 0x57, 7282 MLX5_ACTION_IN_FIELD_METADATA_REG_C_7 = 0x58, 7283 MLX5_ACTION_IN_FIELD_OUT_TCP_SEQ_NUM = 0x59, 7284 MLX5_ACTION_IN_FIELD_OUT_TCP_ACK_NUM = 0x5B, 7285 MLX5_ACTION_IN_FIELD_IPSEC_SYNDROME = 0x5D, 7286 MLX5_ACTION_IN_FIELD_OUT_EMD_47_32 = 0x6F, 7287 MLX5_ACTION_IN_FIELD_OUT_EMD_31_0 = 0x70, 7288 }; 7289 7290 struct mlx5_ifc_alloc_modify_header_context_out_bits { 7291 u8 status[0x8]; 7292 u8 reserved_at_8[0x18]; 7293 7294 u8 syndrome[0x20]; 7295 7296 u8 modify_header_id[0x20]; 7297 7298 u8 reserved_at_60[0x20]; 7299 }; 7300 7301 struct mlx5_ifc_alloc_modify_header_context_in_bits { 7302 u8 opcode[0x10]; 7303 u8 reserved_at_10[0x10]; 7304 7305 u8 reserved_at_20[0x10]; 7306 u8 op_mod[0x10]; 7307 7308 u8 reserved_at_40[0x20]; 7309 7310 u8 table_type[0x8]; 7311 u8 reserved_at_68[0x10]; 7312 u8 num_of_actions[0x8]; 7313 7314 union mlx5_ifc_set_add_copy_action_in_auto_bits actions[]; 7315 }; 7316 7317 struct mlx5_ifc_dealloc_modify_header_context_out_bits { 7318 u8 status[0x8]; 7319 u8 reserved_at_8[0x18]; 7320 7321 u8 syndrome[0x20]; 7322 7323 u8 reserved_at_40[0x40]; 7324 }; 7325 7326 struct mlx5_ifc_dealloc_modify_header_context_in_bits { 7327 u8 opcode[0x10]; 7328 u8 reserved_at_10[0x10]; 7329 7330 u8 reserved_at_20[0x10]; 7331 u8 op_mod[0x10]; 7332 7333 u8 modify_header_id[0x20]; 7334 7335 u8 reserved_at_60[0x20]; 7336 }; 7337 7338 struct mlx5_ifc_query_modify_header_context_in_bits { 7339 u8 opcode[0x10]; 7340 u8 uid[0x10]; 7341 7342 u8 reserved_at_20[0x10]; 7343 u8 op_mod[0x10]; 7344 7345 u8 modify_header_id[0x20]; 7346 7347 u8 reserved_at_60[0xa0]; 7348 }; 7349 7350 struct mlx5_ifc_query_dct_out_bits { 7351 u8 status[0x8]; 7352 u8 reserved_at_8[0x18]; 7353 7354 u8 syndrome[0x20]; 7355 7356 u8 reserved_at_40[0x40]; 7357 7358 struct mlx5_ifc_dctc_bits dct_context_entry; 7359 7360 u8 reserved_at_280[0x180]; 7361 }; 7362 7363 struct mlx5_ifc_query_dct_in_bits { 7364 u8 opcode[0x10]; 7365 u8 reserved_at_10[0x10]; 7366 7367 u8 reserved_at_20[0x10]; 7368 u8 op_mod[0x10]; 7369 7370 u8 reserved_at_40[0x8]; 7371 u8 dctn[0x18]; 7372 7373 u8 reserved_at_60[0x20]; 7374 }; 7375 7376 struct mlx5_ifc_query_cq_out_bits { 7377 u8 status[0x8]; 7378 u8 reserved_at_8[0x18]; 7379 7380 u8 syndrome[0x20]; 7381 7382 u8 reserved_at_40[0x40]; 7383 7384 struct mlx5_ifc_cqc_bits cq_context; 7385 7386 u8 reserved_at_280[0x600]; 7387 7388 u8 pas[][0x40]; 7389 }; 7390 7391 struct mlx5_ifc_query_cq_in_bits { 7392 u8 opcode[0x10]; 7393 u8 reserved_at_10[0x10]; 7394 7395 u8 reserved_at_20[0x10]; 7396 u8 op_mod[0x10]; 7397 7398 u8 reserved_at_40[0x8]; 7399 u8 cqn[0x18]; 7400 7401 u8 reserved_at_60[0x20]; 7402 }; 7403 7404 struct mlx5_ifc_query_cong_status_out_bits { 7405 u8 status[0x8]; 7406 u8 reserved_at_8[0x18]; 7407 7408 u8 syndrome[0x20]; 7409 7410 u8 reserved_at_40[0x20]; 7411 7412 u8 enable[0x1]; 7413 u8 tag_enable[0x1]; 7414 u8 reserved_at_62[0x1e]; 7415 }; 7416 7417 struct mlx5_ifc_query_cong_status_in_bits { 7418 u8 opcode[0x10]; 7419 u8 reserved_at_10[0x10]; 7420 7421 u8 reserved_at_20[0x10]; 7422 u8 op_mod[0x10]; 7423 7424 u8 reserved_at_40[0x18]; 7425 u8 priority[0x4]; 7426 u8 cong_protocol[0x4]; 7427 7428 u8 reserved_at_60[0x20]; 7429 }; 7430 7431 struct mlx5_ifc_query_cong_statistics_out_bits { 7432 u8 status[0x8]; 7433 u8 reserved_at_8[0x18]; 7434 7435 u8 syndrome[0x20]; 7436 7437 u8 reserved_at_40[0x40]; 7438 7439 u8 rp_cur_flows[0x20]; 7440 7441 u8 sum_flows[0x20]; 7442 7443 u8 rp_cnp_ignored_high[0x20]; 7444 7445 u8 rp_cnp_ignored_low[0x20]; 7446 7447 u8 rp_cnp_handled_high[0x20]; 7448 7449 u8 rp_cnp_handled_low[0x20]; 7450 7451 u8 reserved_at_140[0x100]; 7452 7453 u8 time_stamp_high[0x20]; 7454 7455 u8 time_stamp_low[0x20]; 7456 7457 u8 accumulators_period[0x20]; 7458 7459 u8 np_ecn_marked_roce_packets_high[0x20]; 7460 7461 u8 np_ecn_marked_roce_packets_low[0x20]; 7462 7463 u8 np_cnp_sent_high[0x20]; 7464 7465 u8 np_cnp_sent_low[0x20]; 7466 7467 u8 reserved_at_320[0x560]; 7468 }; 7469 7470 struct mlx5_ifc_query_cong_statistics_in_bits { 7471 u8 opcode[0x10]; 7472 u8 reserved_at_10[0x10]; 7473 7474 u8 reserved_at_20[0x10]; 7475 u8 op_mod[0x10]; 7476 7477 u8 clear[0x1]; 7478 u8 reserved_at_41[0x1f]; 7479 7480 u8 reserved_at_60[0x20]; 7481 }; 7482 7483 struct mlx5_ifc_query_cong_params_out_bits { 7484 u8 status[0x8]; 7485 u8 reserved_at_8[0x18]; 7486 7487 u8 syndrome[0x20]; 7488 7489 u8 reserved_at_40[0x40]; 7490 7491 union mlx5_ifc_cong_control_roce_ecn_auto_bits congestion_parameters; 7492 }; 7493 7494 struct mlx5_ifc_query_cong_params_in_bits { 7495 u8 opcode[0x10]; 7496 u8 reserved_at_10[0x10]; 7497 7498 u8 reserved_at_20[0x10]; 7499 u8 op_mod[0x10]; 7500 7501 u8 reserved_at_40[0x1c]; 7502 u8 cong_protocol[0x4]; 7503 7504 u8 reserved_at_60[0x20]; 7505 }; 7506 7507 struct mlx5_ifc_query_adapter_out_bits { 7508 u8 status[0x8]; 7509 u8 reserved_at_8[0x18]; 7510 7511 u8 syndrome[0x20]; 7512 7513 u8 reserved_at_40[0x40]; 7514 7515 struct mlx5_ifc_query_adapter_param_block_bits query_adapter_struct; 7516 }; 7517 7518 struct mlx5_ifc_query_adapter_in_bits { 7519 u8 opcode[0x10]; 7520 u8 reserved_at_10[0x10]; 7521 7522 u8 reserved_at_20[0x10]; 7523 u8 op_mod[0x10]; 7524 7525 u8 reserved_at_40[0x40]; 7526 }; 7527 7528 struct mlx5_ifc_function_vhca_rid_info_reg_bits { 7529 u8 host_number[0x8]; 7530 u8 host_pci_device_function[0x8]; 7531 u8 host_pci_bus[0x8]; 7532 u8 reserved_at_18[0x3]; 7533 u8 pci_bus_assigned[0x1]; 7534 u8 function_type[0x4]; 7535 7536 u8 parent_pci_device_function[0x8]; 7537 u8 parent_pci_bus[0x8]; 7538 u8 vhca_id[0x10]; 7539 7540 u8 reserved_at_40[0x10]; 7541 u8 function_id[0x10]; 7542 7543 u8 reserved_at_60[0x20]; 7544 }; 7545 7546 struct mlx5_ifc_delegated_function_vhca_rid_info_bits { 7547 struct mlx5_ifc_function_vhca_rid_info_reg_bits function_vhca_rid_info; 7548 7549 u8 reserved_at_80[0x18]; 7550 u8 manage_profile[0x8]; 7551 7552 u8 reserved_at_a0[0x60]; 7553 }; 7554 7555 struct mlx5_ifc_query_delegated_vhca_out_bits { 7556 u8 status[0x8]; 7557 u8 reserved_at_8[0x18]; 7558 7559 u8 syndrome[0x20]; 7560 7561 u8 reserved_at_40[0x20]; 7562 7563 u8 reserved_at_60[0x10]; 7564 u8 functions_count[0x10]; 7565 7566 u8 reserved_at_80[0x80]; 7567 7568 struct mlx5_ifc_delegated_function_vhca_rid_info_bits 7569 delegated_function_vhca_rid_info[]; 7570 }; 7571 7572 struct mlx5_ifc_query_delegated_vhca_in_bits { 7573 u8 opcode[0x10]; 7574 u8 uid[0x10]; 7575 7576 u8 reserved_at_20[0x10]; 7577 u8 op_mod[0x10]; 7578 7579 u8 reserved_at_40[0x40]; 7580 }; 7581 7582 struct mlx5_ifc_create_esw_vport_out_bits { 7583 u8 status[0x8]; 7584 u8 reserved_at_8[0x18]; 7585 7586 u8 syndrome[0x20]; 7587 7588 u8 reserved_at_40[0x20]; 7589 7590 u8 reserved_at_60[0x10]; 7591 u8 vport_num[0x10]; 7592 }; 7593 7594 struct mlx5_ifc_create_esw_vport_in_bits { 7595 u8 opcode[0x10]; 7596 u8 reserved_at_10[0x10]; 7597 7598 u8 reserved_at_20[0x10]; 7599 u8 op_mod[0x10]; 7600 7601 u8 reserved_at_40[0x10]; 7602 u8 managed_vhca_id[0x10]; 7603 7604 u8 reserved_at_60[0x20]; 7605 }; 7606 7607 struct mlx5_ifc_qp_2rst_out_bits { 7608 u8 status[0x8]; 7609 u8 reserved_at_8[0x18]; 7610 7611 u8 syndrome[0x20]; 7612 7613 u8 reserved_at_40[0x40]; 7614 }; 7615 7616 struct mlx5_ifc_qp_2rst_in_bits { 7617 u8 opcode[0x10]; 7618 u8 uid[0x10]; 7619 7620 u8 reserved_at_20[0x10]; 7621 u8 op_mod[0x10]; 7622 7623 u8 reserved_at_40[0x8]; 7624 u8 qpn[0x18]; 7625 7626 u8 reserved_at_60[0x20]; 7627 }; 7628 7629 struct mlx5_ifc_qp_2err_out_bits { 7630 u8 status[0x8]; 7631 u8 reserved_at_8[0x18]; 7632 7633 u8 syndrome[0x20]; 7634 7635 u8 reserved_at_40[0x40]; 7636 }; 7637 7638 struct mlx5_ifc_qp_2err_in_bits { 7639 u8 opcode[0x10]; 7640 u8 uid[0x10]; 7641 7642 u8 reserved_at_20[0x10]; 7643 u8 op_mod[0x10]; 7644 7645 u8 reserved_at_40[0x8]; 7646 u8 qpn[0x18]; 7647 7648 u8 reserved_at_60[0x20]; 7649 }; 7650 7651 struct mlx5_ifc_trans_page_fault_info_bits { 7652 u8 error[0x1]; 7653 u8 reserved_at_1[0x4]; 7654 u8 page_fault_type[0x3]; 7655 u8 wq_number[0x18]; 7656 7657 u8 reserved_at_20[0x8]; 7658 u8 fault_token[0x18]; 7659 }; 7660 7661 struct mlx5_ifc_mem_page_fault_info_bits { 7662 u8 error[0x1]; 7663 u8 reserved_at_1[0xf]; 7664 u8 fault_token_47_32[0x10]; 7665 7666 u8 fault_token_31_0[0x20]; 7667 }; 7668 7669 union mlx5_ifc_page_fault_resume_in_page_fault_info_auto_bits { 7670 struct mlx5_ifc_trans_page_fault_info_bits trans_page_fault_info; 7671 struct mlx5_ifc_mem_page_fault_info_bits mem_page_fault_info; 7672 u8 reserved_at_0[0x40]; 7673 }; 7674 7675 struct mlx5_ifc_page_fault_resume_out_bits { 7676 u8 status[0x8]; 7677 u8 reserved_at_8[0x18]; 7678 7679 u8 syndrome[0x20]; 7680 7681 u8 reserved_at_40[0x40]; 7682 }; 7683 7684 struct mlx5_ifc_page_fault_resume_in_bits { 7685 u8 opcode[0x10]; 7686 u8 reserved_at_10[0x10]; 7687 7688 u8 reserved_at_20[0x10]; 7689 u8 op_mod[0x10]; 7690 7691 union mlx5_ifc_page_fault_resume_in_page_fault_info_auto_bits 7692 page_fault_info; 7693 }; 7694 7695 struct mlx5_ifc_nop_out_bits { 7696 u8 status[0x8]; 7697 u8 reserved_at_8[0x18]; 7698 7699 u8 syndrome[0x20]; 7700 7701 u8 reserved_at_40[0x40]; 7702 }; 7703 7704 struct mlx5_ifc_nop_in_bits { 7705 u8 opcode[0x10]; 7706 u8 reserved_at_10[0x10]; 7707 7708 u8 reserved_at_20[0x10]; 7709 u8 op_mod[0x10]; 7710 7711 u8 reserved_at_40[0x40]; 7712 }; 7713 7714 struct mlx5_ifc_modify_vport_state_out_bits { 7715 u8 status[0x8]; 7716 u8 reserved_at_8[0x18]; 7717 7718 u8 syndrome[0x20]; 7719 7720 u8 reserved_at_40[0x40]; 7721 }; 7722 7723 struct mlx5_ifc_modify_vport_state_in_bits { 7724 u8 opcode[0x10]; 7725 u8 reserved_at_10[0x10]; 7726 7727 u8 reserved_at_20[0x10]; 7728 u8 op_mod[0x10]; 7729 7730 u8 other_vport[0x1]; 7731 u8 reserved_at_41[0xf]; 7732 u8 vport_number[0x10]; 7733 7734 u8 reserved_at_60[0x10]; 7735 u8 ingress_connect[0x1]; 7736 u8 egress_connect[0x1]; 7737 u8 ingress_connect_valid[0x1]; 7738 u8 egress_connect_valid[0x1]; 7739 u8 reserved_at_74[0x4]; 7740 u8 admin_state[0x4]; 7741 u8 reserved_at_7c[0x4]; 7742 }; 7743 7744 struct mlx5_ifc_modify_tis_out_bits { 7745 u8 status[0x8]; 7746 u8 reserved_at_8[0x18]; 7747 7748 u8 syndrome[0x20]; 7749 7750 u8 reserved_at_40[0x40]; 7751 }; 7752 7753 struct mlx5_ifc_modify_tis_bitmask_bits { 7754 u8 reserved_at_0[0x20]; 7755 7756 u8 reserved_at_20[0x1d]; 7757 u8 lag_tx_port_affinity[0x1]; 7758 u8 strict_lag_tx_port_affinity[0x1]; 7759 u8 prio[0x1]; 7760 }; 7761 7762 struct mlx5_ifc_modify_tis_in_bits { 7763 u8 opcode[0x10]; 7764 u8 uid[0x10]; 7765 7766 u8 reserved_at_20[0x10]; 7767 u8 op_mod[0x10]; 7768 7769 u8 reserved_at_40[0x8]; 7770 u8 tisn[0x18]; 7771 7772 u8 reserved_at_60[0x20]; 7773 7774 struct mlx5_ifc_modify_tis_bitmask_bits bitmask; 7775 7776 u8 reserved_at_c0[0x40]; 7777 7778 struct mlx5_ifc_tisc_bits ctx; 7779 }; 7780 7781 struct mlx5_ifc_modify_tir_bitmask_bits { 7782 u8 reserved_at_0[0x20]; 7783 7784 u8 reserved_at_20[0x1b]; 7785 u8 self_lb_en[0x1]; 7786 u8 reserved_at_3c[0x1]; 7787 u8 hash[0x1]; 7788 u8 reserved_at_3e[0x1]; 7789 u8 packet_merge[0x1]; 7790 }; 7791 7792 struct mlx5_ifc_modify_tir_out_bits { 7793 u8 status[0x8]; 7794 u8 reserved_at_8[0x18]; 7795 7796 u8 syndrome[0x20]; 7797 7798 u8 reserved_at_40[0x40]; 7799 }; 7800 7801 struct mlx5_ifc_modify_tir_in_bits { 7802 u8 opcode[0x10]; 7803 u8 uid[0x10]; 7804 7805 u8 reserved_at_20[0x10]; 7806 u8 op_mod[0x10]; 7807 7808 u8 reserved_at_40[0x8]; 7809 u8 tirn[0x18]; 7810 7811 u8 reserved_at_60[0x20]; 7812 7813 struct mlx5_ifc_modify_tir_bitmask_bits bitmask; 7814 7815 u8 reserved_at_c0[0x40]; 7816 7817 struct mlx5_ifc_tirc_bits ctx; 7818 }; 7819 7820 struct mlx5_ifc_modify_sq_out_bits { 7821 u8 status[0x8]; 7822 u8 reserved_at_8[0x18]; 7823 7824 u8 syndrome[0x20]; 7825 7826 u8 reserved_at_40[0x40]; 7827 }; 7828 7829 struct mlx5_ifc_modify_sq_in_bits { 7830 u8 opcode[0x10]; 7831 u8 uid[0x10]; 7832 7833 u8 reserved_at_20[0x10]; 7834 u8 op_mod[0x10]; 7835 7836 u8 sq_state[0x4]; 7837 u8 reserved_at_44[0x4]; 7838 u8 sqn[0x18]; 7839 7840 u8 reserved_at_60[0x20]; 7841 7842 u8 modify_bitmask[0x40]; 7843 7844 u8 reserved_at_c0[0x40]; 7845 7846 struct mlx5_ifc_sqc_bits ctx; 7847 }; 7848 7849 struct mlx5_ifc_modify_scheduling_element_out_bits { 7850 u8 status[0x8]; 7851 u8 reserved_at_8[0x18]; 7852 7853 u8 syndrome[0x20]; 7854 7855 u8 reserved_at_40[0x1c0]; 7856 }; 7857 7858 enum { 7859 MODIFY_SCHEDULING_ELEMENT_IN_MODIFY_BITMASK_BW_SHARE = 0x1, 7860 MODIFY_SCHEDULING_ELEMENT_IN_MODIFY_BITMASK_MAX_AVERAGE_BW = 0x2, 7861 }; 7862 7863 struct mlx5_ifc_modify_scheduling_element_in_bits { 7864 u8 opcode[0x10]; 7865 u8 reserved_at_10[0x10]; 7866 7867 u8 reserved_at_20[0x10]; 7868 u8 op_mod[0x10]; 7869 7870 u8 scheduling_hierarchy[0x8]; 7871 u8 reserved_at_48[0x18]; 7872 7873 u8 scheduling_element_id[0x20]; 7874 7875 u8 reserved_at_80[0x20]; 7876 7877 u8 modify_bitmask[0x20]; 7878 7879 u8 reserved_at_c0[0x40]; 7880 7881 struct mlx5_ifc_scheduling_context_bits scheduling_context; 7882 7883 u8 reserved_at_300[0x100]; 7884 }; 7885 7886 struct mlx5_ifc_modify_rqt_out_bits { 7887 u8 status[0x8]; 7888 u8 reserved_at_8[0x18]; 7889 7890 u8 syndrome[0x20]; 7891 7892 u8 reserved_at_40[0x40]; 7893 }; 7894 7895 struct mlx5_ifc_rqt_bitmask_bits { 7896 u8 reserved_at_0[0x20]; 7897 7898 u8 reserved_at_20[0x1f]; 7899 u8 rqn_list[0x1]; 7900 }; 7901 7902 struct mlx5_ifc_modify_rqt_in_bits { 7903 u8 opcode[0x10]; 7904 u8 uid[0x10]; 7905 7906 u8 reserved_at_20[0x10]; 7907 u8 op_mod[0x10]; 7908 7909 u8 reserved_at_40[0x8]; 7910 u8 rqtn[0x18]; 7911 7912 u8 reserved_at_60[0x20]; 7913 7914 struct mlx5_ifc_rqt_bitmask_bits bitmask; 7915 7916 u8 reserved_at_c0[0x40]; 7917 7918 struct mlx5_ifc_rqtc_bits ctx; 7919 }; 7920 7921 struct mlx5_ifc_modify_rq_out_bits { 7922 u8 status[0x8]; 7923 u8 reserved_at_8[0x18]; 7924 7925 u8 syndrome[0x20]; 7926 7927 u8 reserved_at_40[0x40]; 7928 }; 7929 7930 enum { 7931 MLX5_MODIFY_RQ_IN_MODIFY_BITMASK_VSD = 1ULL << 1, 7932 MLX5_MODIFY_RQ_IN_MODIFY_BITMASK_SCATTER_FCS = 1ULL << 2, 7933 MLX5_MODIFY_RQ_IN_MODIFY_BITMASK_RQ_COUNTER_SET_ID = 1ULL << 3, 7934 }; 7935 7936 struct mlx5_ifc_modify_rq_in_bits { 7937 u8 opcode[0x10]; 7938 u8 uid[0x10]; 7939 7940 u8 reserved_at_20[0x10]; 7941 u8 op_mod[0x10]; 7942 7943 u8 rq_state[0x4]; 7944 u8 reserved_at_44[0x4]; 7945 u8 rqn[0x18]; 7946 7947 u8 reserved_at_60[0x20]; 7948 7949 u8 modify_bitmask[0x40]; 7950 7951 u8 reserved_at_c0[0x40]; 7952 7953 struct mlx5_ifc_rqc_bits ctx; 7954 }; 7955 7956 struct mlx5_ifc_modify_rmp_out_bits { 7957 u8 status[0x8]; 7958 u8 reserved_at_8[0x18]; 7959 7960 u8 syndrome[0x20]; 7961 7962 u8 reserved_at_40[0x40]; 7963 }; 7964 7965 struct mlx5_ifc_rmp_bitmask_bits { 7966 u8 reserved_at_0[0x20]; 7967 7968 u8 reserved_at_20[0x1f]; 7969 u8 lwm[0x1]; 7970 }; 7971 7972 struct mlx5_ifc_modify_rmp_in_bits { 7973 u8 opcode[0x10]; 7974 u8 uid[0x10]; 7975 7976 u8 reserved_at_20[0x10]; 7977 u8 op_mod[0x10]; 7978 7979 u8 rmp_state[0x4]; 7980 u8 reserved_at_44[0x4]; 7981 u8 rmpn[0x18]; 7982 7983 u8 reserved_at_60[0x20]; 7984 7985 struct mlx5_ifc_rmp_bitmask_bits bitmask; 7986 7987 u8 reserved_at_c0[0x40]; 7988 7989 struct mlx5_ifc_rmpc_bits ctx; 7990 }; 7991 7992 struct mlx5_ifc_modify_nic_vport_context_out_bits { 7993 u8 status[0x8]; 7994 u8 reserved_at_8[0x18]; 7995 7996 u8 syndrome[0x20]; 7997 7998 u8 reserved_at_40[0x40]; 7999 }; 8000 8001 struct mlx5_ifc_modify_nic_vport_field_select_bits { 8002 u8 reserved_at_0[0x12]; 8003 u8 affiliation[0x1]; 8004 u8 reserved_at_13[0x1]; 8005 u8 disable_uc_local_lb[0x1]; 8006 u8 disable_mc_local_lb[0x1]; 8007 u8 node_guid[0x1]; 8008 u8 port_guid[0x1]; 8009 u8 min_inline[0x1]; 8010 u8 mtu[0x1]; 8011 u8 change_event[0x1]; 8012 u8 promisc[0x1]; 8013 u8 permanent_address[0x1]; 8014 u8 addresses_list[0x1]; 8015 u8 roce_en[0x1]; 8016 u8 reserved_at_1f[0x1]; 8017 }; 8018 8019 struct mlx5_ifc_modify_nic_vport_context_in_bits { 8020 u8 opcode[0x10]; 8021 u8 reserved_at_10[0x10]; 8022 8023 u8 reserved_at_20[0x10]; 8024 u8 op_mod[0x10]; 8025 8026 u8 other_vport[0x1]; 8027 u8 reserved_at_41[0xf]; 8028 u8 vport_number[0x10]; 8029 8030 struct mlx5_ifc_modify_nic_vport_field_select_bits field_select; 8031 8032 u8 reserved_at_80[0x780]; 8033 8034 struct mlx5_ifc_nic_vport_context_bits nic_vport_context; 8035 }; 8036 8037 struct mlx5_ifc_modify_hca_vport_context_out_bits { 8038 u8 status[0x8]; 8039 u8 reserved_at_8[0x18]; 8040 8041 u8 syndrome[0x20]; 8042 8043 u8 reserved_at_40[0x40]; 8044 }; 8045 8046 struct mlx5_ifc_modify_hca_vport_context_in_bits { 8047 u8 opcode[0x10]; 8048 u8 reserved_at_10[0x10]; 8049 8050 u8 reserved_at_20[0x10]; 8051 u8 op_mod[0x10]; 8052 8053 u8 other_vport[0x1]; 8054 u8 reserved_at_41[0xb]; 8055 u8 port_num[0x4]; 8056 u8 vport_number[0x10]; 8057 8058 u8 reserved_at_60[0x20]; 8059 8060 struct mlx5_ifc_hca_vport_context_bits hca_vport_context; 8061 }; 8062 8063 struct mlx5_ifc_modify_cq_out_bits { 8064 u8 status[0x8]; 8065 u8 reserved_at_8[0x18]; 8066 8067 u8 syndrome[0x20]; 8068 8069 u8 reserved_at_40[0x40]; 8070 }; 8071 8072 enum { 8073 MLX5_MODIFY_CQ_IN_OP_MOD_MODIFY_CQ = 0x0, 8074 MLX5_MODIFY_CQ_IN_OP_MOD_RESIZE_CQ = 0x1, 8075 }; 8076 8077 struct mlx5_ifc_modify_cq_in_bits { 8078 u8 opcode[0x10]; 8079 u8 uid[0x10]; 8080 8081 u8 reserved_at_20[0x10]; 8082 u8 op_mod[0x10]; 8083 8084 u8 reserved_at_40[0x8]; 8085 u8 cqn[0x18]; 8086 8087 union mlx5_ifc_modify_field_select_resize_field_select_auto_bits modify_field_select_resize_field_select; 8088 8089 struct mlx5_ifc_cqc_bits cq_context; 8090 8091 u8 reserved_at_280[0x60]; 8092 8093 u8 cq_umem_valid[0x1]; 8094 u8 reserved_at_2e1[0x1f]; 8095 8096 u8 reserved_at_300[0x580]; 8097 8098 u8 pas[][0x40]; 8099 }; 8100 8101 struct mlx5_ifc_modify_cong_status_out_bits { 8102 u8 status[0x8]; 8103 u8 reserved_at_8[0x18]; 8104 8105 u8 syndrome[0x20]; 8106 8107 u8 reserved_at_40[0x40]; 8108 }; 8109 8110 struct mlx5_ifc_modify_cong_status_in_bits { 8111 u8 opcode[0x10]; 8112 u8 reserved_at_10[0x10]; 8113 8114 u8 reserved_at_20[0x10]; 8115 u8 op_mod[0x10]; 8116 8117 u8 reserved_at_40[0x18]; 8118 u8 priority[0x4]; 8119 u8 cong_protocol[0x4]; 8120 8121 u8 enable[0x1]; 8122 u8 tag_enable[0x1]; 8123 u8 reserved_at_62[0x1e]; 8124 }; 8125 8126 struct mlx5_ifc_modify_cong_params_out_bits { 8127 u8 status[0x8]; 8128 u8 reserved_at_8[0x18]; 8129 8130 u8 syndrome[0x20]; 8131 8132 u8 reserved_at_40[0x40]; 8133 }; 8134 8135 struct mlx5_ifc_modify_cong_params_in_bits { 8136 u8 opcode[0x10]; 8137 u8 reserved_at_10[0x10]; 8138 8139 u8 reserved_at_20[0x10]; 8140 u8 op_mod[0x10]; 8141 8142 u8 reserved_at_40[0x1c]; 8143 u8 cong_protocol[0x4]; 8144 8145 union mlx5_ifc_field_select_802_1_r_roce_auto_bits field_select; 8146 8147 u8 reserved_at_80[0x80]; 8148 8149 union mlx5_ifc_cong_control_roce_ecn_auto_bits congestion_parameters; 8150 }; 8151 8152 struct mlx5_ifc_manage_pages_out_bits { 8153 u8 status[0x8]; 8154 u8 reserved_at_8[0x18]; 8155 8156 u8 syndrome[0x20]; 8157 8158 u8 output_num_entries[0x20]; 8159 8160 u8 reserved_at_60[0x20]; 8161 8162 u8 pas[][0x40]; 8163 }; 8164 8165 enum { 8166 MLX5_MANAGE_PAGES_IN_OP_MOD_ALLOCATION_FAIL = 0x0, 8167 MLX5_MANAGE_PAGES_IN_OP_MOD_ALLOCATION_SUCCESS = 0x1, 8168 MLX5_MANAGE_PAGES_IN_OP_MOD_HCA_RETURN_PAGES = 0x2, 8169 }; 8170 8171 struct mlx5_ifc_manage_pages_in_bits { 8172 u8 opcode[0x10]; 8173 u8 reserved_at_10[0x10]; 8174 8175 u8 reserved_at_20[0x10]; 8176 u8 op_mod[0x10]; 8177 8178 u8 embedded_cpu_function[0x1]; 8179 u8 reserved_at_41[0xf]; 8180 u8 function_id[0x10]; 8181 8182 u8 input_num_entries[0x20]; 8183 8184 u8 pas[][0x40]; 8185 }; 8186 8187 struct mlx5_ifc_mad_ifc_out_bits { 8188 u8 status[0x8]; 8189 u8 reserved_at_8[0x18]; 8190 8191 u8 syndrome[0x20]; 8192 8193 u8 reserved_at_40[0x40]; 8194 8195 u8 response_mad_packet[256][0x8]; 8196 }; 8197 8198 struct mlx5_ifc_mad_ifc_in_bits { 8199 u8 opcode[0x10]; 8200 u8 reserved_at_10[0x10]; 8201 8202 u8 reserved_at_20[0x10]; 8203 u8 op_mod[0x10]; 8204 8205 u8 remote_lid[0x10]; 8206 u8 plane_index[0x8]; 8207 u8 port[0x8]; 8208 8209 u8 reserved_at_60[0x20]; 8210 8211 u8 mad[256][0x8]; 8212 }; 8213 8214 struct mlx5_ifc_init_hca_out_bits { 8215 u8 status[0x8]; 8216 u8 reserved_at_8[0x18]; 8217 8218 u8 syndrome[0x20]; 8219 8220 u8 reserved_at_40[0x40]; 8221 }; 8222 8223 struct mlx5_ifc_init_hca_in_bits { 8224 u8 opcode[0x10]; 8225 u8 reserved_at_10[0x10]; 8226 8227 u8 reserved_at_20[0x10]; 8228 u8 op_mod[0x10]; 8229 8230 u8 reserved_at_40[0x20]; 8231 8232 u8 reserved_at_60[0x2]; 8233 u8 sw_vhca_id[0xe]; 8234 u8 reserved_at_70[0x10]; 8235 8236 u8 sw_owner_id[4][0x20]; 8237 }; 8238 8239 struct mlx5_ifc_init2rtr_qp_out_bits { 8240 u8 status[0x8]; 8241 u8 reserved_at_8[0x18]; 8242 8243 u8 syndrome[0x20]; 8244 8245 u8 reserved_at_40[0x20]; 8246 u8 ece[0x20]; 8247 }; 8248 8249 struct mlx5_ifc_init2rtr_qp_in_bits { 8250 u8 opcode[0x10]; 8251 u8 uid[0x10]; 8252 8253 u8 reserved_at_20[0x10]; 8254 u8 op_mod[0x10]; 8255 8256 u8 reserved_at_40[0x8]; 8257 u8 qpn[0x18]; 8258 8259 u8 reserved_at_60[0x20]; 8260 8261 u8 opt_param_mask[0x20]; 8262 8263 u8 ece[0x20]; 8264 8265 struct mlx5_ifc_qpc_bits qpc; 8266 8267 u8 reserved_at_800[0x80]; 8268 }; 8269 8270 struct mlx5_ifc_init2init_qp_out_bits { 8271 u8 status[0x8]; 8272 u8 reserved_at_8[0x18]; 8273 8274 u8 syndrome[0x20]; 8275 8276 u8 reserved_at_40[0x20]; 8277 u8 ece[0x20]; 8278 }; 8279 8280 struct mlx5_ifc_init2init_qp_in_bits { 8281 u8 opcode[0x10]; 8282 u8 uid[0x10]; 8283 8284 u8 reserved_at_20[0x10]; 8285 u8 op_mod[0x10]; 8286 8287 u8 reserved_at_40[0x8]; 8288 u8 qpn[0x18]; 8289 8290 u8 reserved_at_60[0x20]; 8291 8292 u8 opt_param_mask[0x20]; 8293 8294 u8 ece[0x20]; 8295 8296 struct mlx5_ifc_qpc_bits qpc; 8297 8298 u8 reserved_at_800[0x80]; 8299 }; 8300 8301 struct mlx5_ifc_get_dropped_packet_log_out_bits { 8302 u8 status[0x8]; 8303 u8 reserved_at_8[0x18]; 8304 8305 u8 syndrome[0x20]; 8306 8307 u8 reserved_at_40[0x40]; 8308 8309 u8 packet_headers_log[128][0x8]; 8310 8311 u8 packet_syndrome[64][0x8]; 8312 }; 8313 8314 struct mlx5_ifc_get_dropped_packet_log_in_bits { 8315 u8 opcode[0x10]; 8316 u8 reserved_at_10[0x10]; 8317 8318 u8 reserved_at_20[0x10]; 8319 u8 op_mod[0x10]; 8320 8321 u8 reserved_at_40[0x40]; 8322 }; 8323 8324 struct mlx5_ifc_gen_eqe_in_bits { 8325 u8 opcode[0x10]; 8326 u8 reserved_at_10[0x10]; 8327 8328 u8 reserved_at_20[0x10]; 8329 u8 op_mod[0x10]; 8330 8331 u8 reserved_at_40[0x18]; 8332 u8 eq_number[0x8]; 8333 8334 u8 reserved_at_60[0x20]; 8335 8336 u8 eqe[64][0x8]; 8337 }; 8338 8339 struct mlx5_ifc_gen_eq_out_bits { 8340 u8 status[0x8]; 8341 u8 reserved_at_8[0x18]; 8342 8343 u8 syndrome[0x20]; 8344 8345 u8 reserved_at_40[0x40]; 8346 }; 8347 8348 struct mlx5_ifc_enable_hca_out_bits { 8349 u8 status[0x8]; 8350 u8 reserved_at_8[0x18]; 8351 8352 u8 syndrome[0x20]; 8353 8354 u8 reserved_at_40[0x20]; 8355 }; 8356 8357 struct mlx5_ifc_enable_hca_in_bits { 8358 u8 opcode[0x10]; 8359 u8 reserved_at_10[0x10]; 8360 8361 u8 reserved_at_20[0x10]; 8362 u8 op_mod[0x10]; 8363 8364 u8 embedded_cpu_function[0x1]; 8365 u8 reserved_at_41[0xf]; 8366 u8 function_id[0x10]; 8367 8368 u8 reserved_at_60[0x20]; 8369 }; 8370 8371 struct mlx5_ifc_drain_dct_out_bits { 8372 u8 status[0x8]; 8373 u8 reserved_at_8[0x18]; 8374 8375 u8 syndrome[0x20]; 8376 8377 u8 reserved_at_40[0x40]; 8378 }; 8379 8380 struct mlx5_ifc_drain_dct_in_bits { 8381 u8 opcode[0x10]; 8382 u8 uid[0x10]; 8383 8384 u8 reserved_at_20[0x10]; 8385 u8 op_mod[0x10]; 8386 8387 u8 reserved_at_40[0x8]; 8388 u8 dctn[0x18]; 8389 8390 u8 reserved_at_60[0x20]; 8391 }; 8392 8393 struct mlx5_ifc_disable_hca_out_bits { 8394 u8 status[0x8]; 8395 u8 reserved_at_8[0x18]; 8396 8397 u8 syndrome[0x20]; 8398 8399 u8 reserved_at_40[0x20]; 8400 }; 8401 8402 struct mlx5_ifc_disable_hca_in_bits { 8403 u8 opcode[0x10]; 8404 u8 reserved_at_10[0x10]; 8405 8406 u8 reserved_at_20[0x10]; 8407 u8 op_mod[0x10]; 8408 8409 u8 embedded_cpu_function[0x1]; 8410 u8 reserved_at_41[0xf]; 8411 u8 function_id[0x10]; 8412 8413 u8 reserved_at_60[0x20]; 8414 }; 8415 8416 struct mlx5_ifc_detach_from_mcg_out_bits { 8417 u8 status[0x8]; 8418 u8 reserved_at_8[0x18]; 8419 8420 u8 syndrome[0x20]; 8421 8422 u8 reserved_at_40[0x40]; 8423 }; 8424 8425 struct mlx5_ifc_detach_from_mcg_in_bits { 8426 u8 opcode[0x10]; 8427 u8 uid[0x10]; 8428 8429 u8 reserved_at_20[0x10]; 8430 u8 op_mod[0x10]; 8431 8432 u8 reserved_at_40[0x8]; 8433 u8 qpn[0x18]; 8434 8435 u8 reserved_at_60[0x20]; 8436 8437 u8 multicast_gid[16][0x8]; 8438 }; 8439 8440 struct mlx5_ifc_destroy_xrq_out_bits { 8441 u8 status[0x8]; 8442 u8 reserved_at_8[0x18]; 8443 8444 u8 syndrome[0x20]; 8445 8446 u8 reserved_at_40[0x40]; 8447 }; 8448 8449 struct mlx5_ifc_destroy_xrq_in_bits { 8450 u8 opcode[0x10]; 8451 u8 uid[0x10]; 8452 8453 u8 reserved_at_20[0x10]; 8454 u8 op_mod[0x10]; 8455 8456 u8 reserved_at_40[0x8]; 8457 u8 xrqn[0x18]; 8458 8459 u8 reserved_at_60[0x20]; 8460 }; 8461 8462 struct mlx5_ifc_destroy_xrc_srq_out_bits { 8463 u8 status[0x8]; 8464 u8 reserved_at_8[0x18]; 8465 8466 u8 syndrome[0x20]; 8467 8468 u8 reserved_at_40[0x40]; 8469 }; 8470 8471 struct mlx5_ifc_destroy_xrc_srq_in_bits { 8472 u8 opcode[0x10]; 8473 u8 uid[0x10]; 8474 8475 u8 reserved_at_20[0x10]; 8476 u8 op_mod[0x10]; 8477 8478 u8 reserved_at_40[0x8]; 8479 u8 xrc_srqn[0x18]; 8480 8481 u8 reserved_at_60[0x20]; 8482 }; 8483 8484 struct mlx5_ifc_destroy_tis_out_bits { 8485 u8 status[0x8]; 8486 u8 reserved_at_8[0x18]; 8487 8488 u8 syndrome[0x20]; 8489 8490 u8 reserved_at_40[0x40]; 8491 }; 8492 8493 struct mlx5_ifc_destroy_tis_in_bits { 8494 u8 opcode[0x10]; 8495 u8 uid[0x10]; 8496 8497 u8 reserved_at_20[0x10]; 8498 u8 op_mod[0x10]; 8499 8500 u8 reserved_at_40[0x8]; 8501 u8 tisn[0x18]; 8502 8503 u8 reserved_at_60[0x20]; 8504 }; 8505 8506 struct mlx5_ifc_destroy_tir_out_bits { 8507 u8 status[0x8]; 8508 u8 reserved_at_8[0x18]; 8509 8510 u8 syndrome[0x20]; 8511 8512 u8 reserved_at_40[0x40]; 8513 }; 8514 8515 struct mlx5_ifc_destroy_tir_in_bits { 8516 u8 opcode[0x10]; 8517 u8 uid[0x10]; 8518 8519 u8 reserved_at_20[0x10]; 8520 u8 op_mod[0x10]; 8521 8522 u8 reserved_at_40[0x8]; 8523 u8 tirn[0x18]; 8524 8525 u8 reserved_at_60[0x20]; 8526 }; 8527 8528 struct mlx5_ifc_destroy_srq_out_bits { 8529 u8 status[0x8]; 8530 u8 reserved_at_8[0x18]; 8531 8532 u8 syndrome[0x20]; 8533 8534 u8 reserved_at_40[0x40]; 8535 }; 8536 8537 struct mlx5_ifc_destroy_srq_in_bits { 8538 u8 opcode[0x10]; 8539 u8 uid[0x10]; 8540 8541 u8 reserved_at_20[0x10]; 8542 u8 op_mod[0x10]; 8543 8544 u8 reserved_at_40[0x8]; 8545 u8 srqn[0x18]; 8546 8547 u8 reserved_at_60[0x20]; 8548 }; 8549 8550 struct mlx5_ifc_destroy_sq_out_bits { 8551 u8 status[0x8]; 8552 u8 reserved_at_8[0x18]; 8553 8554 u8 syndrome[0x20]; 8555 8556 u8 reserved_at_40[0x40]; 8557 }; 8558 8559 struct mlx5_ifc_destroy_sq_in_bits { 8560 u8 opcode[0x10]; 8561 u8 uid[0x10]; 8562 8563 u8 reserved_at_20[0x10]; 8564 u8 op_mod[0x10]; 8565 8566 u8 reserved_at_40[0x8]; 8567 u8 sqn[0x18]; 8568 8569 u8 reserved_at_60[0x20]; 8570 }; 8571 8572 struct mlx5_ifc_destroy_scheduling_element_out_bits { 8573 u8 status[0x8]; 8574 u8 reserved_at_8[0x18]; 8575 8576 u8 syndrome[0x20]; 8577 8578 u8 reserved_at_40[0x1c0]; 8579 }; 8580 8581 struct mlx5_ifc_destroy_scheduling_element_in_bits { 8582 u8 opcode[0x10]; 8583 u8 reserved_at_10[0x10]; 8584 8585 u8 reserved_at_20[0x10]; 8586 u8 op_mod[0x10]; 8587 8588 u8 scheduling_hierarchy[0x8]; 8589 u8 reserved_at_48[0x18]; 8590 8591 u8 scheduling_element_id[0x20]; 8592 8593 u8 reserved_at_80[0x180]; 8594 }; 8595 8596 struct mlx5_ifc_destroy_rqt_out_bits { 8597 u8 status[0x8]; 8598 u8 reserved_at_8[0x18]; 8599 8600 u8 syndrome[0x20]; 8601 8602 u8 reserved_at_40[0x40]; 8603 }; 8604 8605 struct mlx5_ifc_destroy_rqt_in_bits { 8606 u8 opcode[0x10]; 8607 u8 uid[0x10]; 8608 8609 u8 reserved_at_20[0x10]; 8610 u8 op_mod[0x10]; 8611 8612 u8 reserved_at_40[0x8]; 8613 u8 rqtn[0x18]; 8614 8615 u8 reserved_at_60[0x20]; 8616 }; 8617 8618 struct mlx5_ifc_destroy_rq_out_bits { 8619 u8 status[0x8]; 8620 u8 reserved_at_8[0x18]; 8621 8622 u8 syndrome[0x20]; 8623 8624 u8 reserved_at_40[0x40]; 8625 }; 8626 8627 struct mlx5_ifc_destroy_rq_in_bits { 8628 u8 opcode[0x10]; 8629 u8 uid[0x10]; 8630 8631 u8 reserved_at_20[0x10]; 8632 u8 op_mod[0x10]; 8633 8634 u8 reserved_at_40[0x8]; 8635 u8 rqn[0x18]; 8636 8637 u8 reserved_at_60[0x20]; 8638 }; 8639 8640 struct mlx5_ifc_set_delay_drop_params_in_bits { 8641 u8 opcode[0x10]; 8642 u8 reserved_at_10[0x10]; 8643 8644 u8 reserved_at_20[0x10]; 8645 u8 op_mod[0x10]; 8646 8647 u8 reserved_at_40[0x20]; 8648 8649 u8 reserved_at_60[0x10]; 8650 u8 delay_drop_timeout[0x10]; 8651 }; 8652 8653 struct mlx5_ifc_set_delay_drop_params_out_bits { 8654 u8 status[0x8]; 8655 u8 reserved_at_8[0x18]; 8656 8657 u8 syndrome[0x20]; 8658 8659 u8 reserved_at_40[0x40]; 8660 }; 8661 8662 struct mlx5_ifc_destroy_rmp_out_bits { 8663 u8 status[0x8]; 8664 u8 reserved_at_8[0x18]; 8665 8666 u8 syndrome[0x20]; 8667 8668 u8 reserved_at_40[0x40]; 8669 }; 8670 8671 struct mlx5_ifc_destroy_rmp_in_bits { 8672 u8 opcode[0x10]; 8673 u8 uid[0x10]; 8674 8675 u8 reserved_at_20[0x10]; 8676 u8 op_mod[0x10]; 8677 8678 u8 reserved_at_40[0x8]; 8679 u8 rmpn[0x18]; 8680 8681 u8 reserved_at_60[0x20]; 8682 }; 8683 8684 struct mlx5_ifc_destroy_qp_out_bits { 8685 u8 status[0x8]; 8686 u8 reserved_at_8[0x18]; 8687 8688 u8 syndrome[0x20]; 8689 8690 u8 reserved_at_40[0x40]; 8691 }; 8692 8693 struct mlx5_ifc_destroy_qp_in_bits { 8694 u8 opcode[0x10]; 8695 u8 uid[0x10]; 8696 8697 u8 reserved_at_20[0x10]; 8698 u8 op_mod[0x10]; 8699 8700 u8 reserved_at_40[0x8]; 8701 u8 qpn[0x18]; 8702 8703 u8 reserved_at_60[0x20]; 8704 }; 8705 8706 struct mlx5_ifc_destroy_psv_out_bits { 8707 u8 status[0x8]; 8708 u8 reserved_at_8[0x18]; 8709 8710 u8 syndrome[0x20]; 8711 8712 u8 reserved_at_40[0x40]; 8713 }; 8714 8715 struct mlx5_ifc_destroy_psv_in_bits { 8716 u8 opcode[0x10]; 8717 u8 reserved_at_10[0x10]; 8718 8719 u8 reserved_at_20[0x10]; 8720 u8 op_mod[0x10]; 8721 8722 u8 reserved_at_40[0x8]; 8723 u8 psvn[0x18]; 8724 8725 u8 reserved_at_60[0x20]; 8726 }; 8727 8728 struct mlx5_ifc_destroy_mkey_out_bits { 8729 u8 status[0x8]; 8730 u8 reserved_at_8[0x18]; 8731 8732 u8 syndrome[0x20]; 8733 8734 u8 reserved_at_40[0x40]; 8735 }; 8736 8737 struct mlx5_ifc_destroy_mkey_in_bits { 8738 u8 opcode[0x10]; 8739 u8 uid[0x10]; 8740 8741 u8 reserved_at_20[0x10]; 8742 u8 op_mod[0x10]; 8743 8744 u8 reserved_at_40[0x8]; 8745 u8 mkey_index[0x18]; 8746 8747 u8 reserved_at_60[0x20]; 8748 }; 8749 8750 struct mlx5_ifc_destroy_flow_table_out_bits { 8751 u8 status[0x8]; 8752 u8 reserved_at_8[0x18]; 8753 8754 u8 syndrome[0x20]; 8755 8756 u8 reserved_at_40[0x40]; 8757 }; 8758 8759 struct mlx5_ifc_destroy_flow_table_in_bits { 8760 u8 opcode[0x10]; 8761 u8 reserved_at_10[0x10]; 8762 8763 u8 reserved_at_20[0x10]; 8764 u8 op_mod[0x10]; 8765 8766 u8 other_vport[0x1]; 8767 u8 reserved_at_41[0xf]; 8768 u8 vport_number[0x10]; 8769 8770 u8 reserved_at_60[0x20]; 8771 8772 u8 table_type[0x8]; 8773 u8 reserved_at_88[0x18]; 8774 8775 u8 reserved_at_a0[0x8]; 8776 u8 table_id[0x18]; 8777 8778 u8 reserved_at_c0[0x140]; 8779 }; 8780 8781 struct mlx5_ifc_destroy_flow_group_out_bits { 8782 u8 status[0x8]; 8783 u8 reserved_at_8[0x18]; 8784 8785 u8 syndrome[0x20]; 8786 8787 u8 reserved_at_40[0x40]; 8788 }; 8789 8790 struct mlx5_ifc_destroy_flow_group_in_bits { 8791 u8 opcode[0x10]; 8792 u8 reserved_at_10[0x10]; 8793 8794 u8 reserved_at_20[0x10]; 8795 u8 op_mod[0x10]; 8796 8797 u8 other_vport[0x1]; 8798 u8 reserved_at_41[0xf]; 8799 u8 vport_number[0x10]; 8800 8801 u8 reserved_at_60[0x20]; 8802 8803 u8 table_type[0x8]; 8804 u8 reserved_at_88[0x18]; 8805 8806 u8 reserved_at_a0[0x8]; 8807 u8 table_id[0x18]; 8808 8809 u8 group_id[0x20]; 8810 8811 u8 reserved_at_e0[0x120]; 8812 }; 8813 8814 struct mlx5_ifc_destroy_eq_out_bits { 8815 u8 status[0x8]; 8816 u8 reserved_at_8[0x18]; 8817 8818 u8 syndrome[0x20]; 8819 8820 u8 reserved_at_40[0x40]; 8821 }; 8822 8823 struct mlx5_ifc_destroy_eq_in_bits { 8824 u8 opcode[0x10]; 8825 u8 reserved_at_10[0x10]; 8826 8827 u8 reserved_at_20[0x10]; 8828 u8 op_mod[0x10]; 8829 8830 u8 reserved_at_40[0x18]; 8831 u8 eq_number[0x8]; 8832 8833 u8 reserved_at_60[0x20]; 8834 }; 8835 8836 struct mlx5_ifc_destroy_dct_out_bits { 8837 u8 status[0x8]; 8838 u8 reserved_at_8[0x18]; 8839 8840 u8 syndrome[0x20]; 8841 8842 u8 reserved_at_40[0x40]; 8843 }; 8844 8845 struct mlx5_ifc_destroy_dct_in_bits { 8846 u8 opcode[0x10]; 8847 u8 uid[0x10]; 8848 8849 u8 reserved_at_20[0x10]; 8850 u8 op_mod[0x10]; 8851 8852 u8 reserved_at_40[0x8]; 8853 u8 dctn[0x18]; 8854 8855 u8 reserved_at_60[0x20]; 8856 }; 8857 8858 struct mlx5_ifc_destroy_cq_out_bits { 8859 u8 status[0x8]; 8860 u8 reserved_at_8[0x18]; 8861 8862 u8 syndrome[0x20]; 8863 8864 u8 reserved_at_40[0x40]; 8865 }; 8866 8867 struct mlx5_ifc_destroy_cq_in_bits { 8868 u8 opcode[0x10]; 8869 u8 uid[0x10]; 8870 8871 u8 reserved_at_20[0x10]; 8872 u8 op_mod[0x10]; 8873 8874 u8 reserved_at_40[0x8]; 8875 u8 cqn[0x18]; 8876 8877 u8 reserved_at_60[0x20]; 8878 }; 8879 8880 struct mlx5_ifc_delete_vxlan_udp_dport_out_bits { 8881 u8 status[0x8]; 8882 u8 reserved_at_8[0x18]; 8883 8884 u8 syndrome[0x20]; 8885 8886 u8 reserved_at_40[0x40]; 8887 }; 8888 8889 struct mlx5_ifc_delete_vxlan_udp_dport_in_bits { 8890 u8 opcode[0x10]; 8891 u8 reserved_at_10[0x10]; 8892 8893 u8 reserved_at_20[0x10]; 8894 u8 op_mod[0x10]; 8895 8896 u8 reserved_at_40[0x20]; 8897 8898 u8 reserved_at_60[0x10]; 8899 u8 vxlan_udp_port[0x10]; 8900 }; 8901 8902 struct mlx5_ifc_delete_l2_table_entry_out_bits { 8903 u8 status[0x8]; 8904 u8 reserved_at_8[0x18]; 8905 8906 u8 syndrome[0x20]; 8907 8908 u8 reserved_at_40[0x40]; 8909 }; 8910 8911 struct mlx5_ifc_delete_l2_table_entry_in_bits { 8912 u8 opcode[0x10]; 8913 u8 reserved_at_10[0x10]; 8914 8915 u8 reserved_at_20[0x10]; 8916 u8 op_mod[0x10]; 8917 8918 u8 reserved_at_40[0x60]; 8919 8920 u8 reserved_at_a0[0x8]; 8921 u8 table_index[0x18]; 8922 8923 u8 reserved_at_c0[0x140]; 8924 }; 8925 8926 struct mlx5_ifc_delete_fte_out_bits { 8927 u8 status[0x8]; 8928 u8 reserved_at_8[0x18]; 8929 8930 u8 syndrome[0x20]; 8931 8932 u8 reserved_at_40[0x40]; 8933 }; 8934 8935 struct mlx5_ifc_delete_fte_in_bits { 8936 u8 opcode[0x10]; 8937 u8 reserved_at_10[0x10]; 8938 8939 u8 reserved_at_20[0x10]; 8940 u8 op_mod[0x10]; 8941 8942 u8 other_vport[0x1]; 8943 u8 reserved_at_41[0xf]; 8944 u8 vport_number[0x10]; 8945 8946 u8 reserved_at_60[0x20]; 8947 8948 u8 table_type[0x8]; 8949 u8 reserved_at_88[0x18]; 8950 8951 u8 reserved_at_a0[0x8]; 8952 u8 table_id[0x18]; 8953 8954 u8 reserved_at_c0[0x40]; 8955 8956 u8 flow_index[0x20]; 8957 8958 u8 reserved_at_120[0xe0]; 8959 }; 8960 8961 struct mlx5_ifc_dealloc_xrcd_out_bits { 8962 u8 status[0x8]; 8963 u8 reserved_at_8[0x18]; 8964 8965 u8 syndrome[0x20]; 8966 8967 u8 reserved_at_40[0x40]; 8968 }; 8969 8970 struct mlx5_ifc_dealloc_xrcd_in_bits { 8971 u8 opcode[0x10]; 8972 u8 uid[0x10]; 8973 8974 u8 reserved_at_20[0x10]; 8975 u8 op_mod[0x10]; 8976 8977 u8 reserved_at_40[0x8]; 8978 u8 xrcd[0x18]; 8979 8980 u8 reserved_at_60[0x20]; 8981 }; 8982 8983 struct mlx5_ifc_dealloc_uar_out_bits { 8984 u8 status[0x8]; 8985 u8 reserved_at_8[0x18]; 8986 8987 u8 syndrome[0x20]; 8988 8989 u8 reserved_at_40[0x40]; 8990 }; 8991 8992 struct mlx5_ifc_dealloc_uar_in_bits { 8993 u8 opcode[0x10]; 8994 u8 uid[0x10]; 8995 8996 u8 reserved_at_20[0x10]; 8997 u8 op_mod[0x10]; 8998 8999 u8 reserved_at_40[0x8]; 9000 u8 uar[0x18]; 9001 9002 u8 reserved_at_60[0x20]; 9003 }; 9004 9005 struct mlx5_ifc_dealloc_transport_domain_out_bits { 9006 u8 status[0x8]; 9007 u8 reserved_at_8[0x18]; 9008 9009 u8 syndrome[0x20]; 9010 9011 u8 reserved_at_40[0x40]; 9012 }; 9013 9014 struct mlx5_ifc_dealloc_transport_domain_in_bits { 9015 u8 opcode[0x10]; 9016 u8 uid[0x10]; 9017 9018 u8 reserved_at_20[0x10]; 9019 u8 op_mod[0x10]; 9020 9021 u8 reserved_at_40[0x8]; 9022 u8 transport_domain[0x18]; 9023 9024 u8 reserved_at_60[0x20]; 9025 }; 9026 9027 struct mlx5_ifc_dealloc_q_counter_out_bits { 9028 u8 status[0x8]; 9029 u8 reserved_at_8[0x18]; 9030 9031 u8 syndrome[0x20]; 9032 9033 u8 reserved_at_40[0x40]; 9034 }; 9035 9036 struct mlx5_ifc_dealloc_q_counter_in_bits { 9037 u8 opcode[0x10]; 9038 u8 reserved_at_10[0x10]; 9039 9040 u8 reserved_at_20[0x10]; 9041 u8 op_mod[0x10]; 9042 9043 u8 reserved_at_40[0x18]; 9044 u8 counter_set_id[0x8]; 9045 9046 u8 reserved_at_60[0x20]; 9047 }; 9048 9049 struct mlx5_ifc_dealloc_pd_out_bits { 9050 u8 status[0x8]; 9051 u8 reserved_at_8[0x18]; 9052 9053 u8 syndrome[0x20]; 9054 9055 u8 reserved_at_40[0x40]; 9056 }; 9057 9058 struct mlx5_ifc_dealloc_pd_in_bits { 9059 u8 opcode[0x10]; 9060 u8 uid[0x10]; 9061 9062 u8 reserved_at_20[0x10]; 9063 u8 op_mod[0x10]; 9064 9065 u8 reserved_at_40[0x8]; 9066 u8 pd[0x18]; 9067 9068 u8 reserved_at_60[0x20]; 9069 }; 9070 9071 struct mlx5_ifc_dealloc_flow_counter_out_bits { 9072 u8 status[0x8]; 9073 u8 reserved_at_8[0x18]; 9074 9075 u8 syndrome[0x20]; 9076 9077 u8 reserved_at_40[0x40]; 9078 }; 9079 9080 struct mlx5_ifc_dealloc_flow_counter_in_bits { 9081 u8 opcode[0x10]; 9082 u8 reserved_at_10[0x10]; 9083 9084 u8 reserved_at_20[0x10]; 9085 u8 op_mod[0x10]; 9086 9087 u8 flow_counter_id[0x20]; 9088 9089 u8 reserved_at_60[0x20]; 9090 }; 9091 9092 struct mlx5_ifc_create_xrq_out_bits { 9093 u8 status[0x8]; 9094 u8 reserved_at_8[0x18]; 9095 9096 u8 syndrome[0x20]; 9097 9098 u8 reserved_at_40[0x8]; 9099 u8 xrqn[0x18]; 9100 9101 u8 reserved_at_60[0x20]; 9102 }; 9103 9104 struct mlx5_ifc_create_xrq_in_bits { 9105 u8 opcode[0x10]; 9106 u8 uid[0x10]; 9107 9108 u8 reserved_at_20[0x10]; 9109 u8 op_mod[0x10]; 9110 9111 u8 reserved_at_40[0x40]; 9112 9113 struct mlx5_ifc_xrqc_bits xrq_context; 9114 }; 9115 9116 struct mlx5_ifc_create_xrc_srq_out_bits { 9117 u8 status[0x8]; 9118 u8 reserved_at_8[0x18]; 9119 9120 u8 syndrome[0x20]; 9121 9122 u8 reserved_at_40[0x8]; 9123 u8 xrc_srqn[0x18]; 9124 9125 u8 reserved_at_60[0x20]; 9126 }; 9127 9128 struct mlx5_ifc_create_xrc_srq_in_bits { 9129 u8 opcode[0x10]; 9130 u8 uid[0x10]; 9131 9132 u8 reserved_at_20[0x10]; 9133 u8 op_mod[0x10]; 9134 9135 u8 reserved_at_40[0x40]; 9136 9137 struct mlx5_ifc_xrc_srqc_bits xrc_srq_context_entry; 9138 9139 u8 reserved_at_280[0x60]; 9140 9141 u8 xrc_srq_umem_valid[0x1]; 9142 u8 reserved_at_2e1[0x1f]; 9143 9144 u8 reserved_at_300[0x580]; 9145 9146 u8 pas[][0x40]; 9147 }; 9148 9149 struct mlx5_ifc_create_tis_out_bits { 9150 u8 status[0x8]; 9151 u8 reserved_at_8[0x18]; 9152 9153 u8 syndrome[0x20]; 9154 9155 u8 reserved_at_40[0x8]; 9156 u8 tisn[0x18]; 9157 9158 u8 reserved_at_60[0x20]; 9159 }; 9160 9161 struct mlx5_ifc_create_tis_in_bits { 9162 u8 opcode[0x10]; 9163 u8 uid[0x10]; 9164 9165 u8 reserved_at_20[0x10]; 9166 u8 op_mod[0x10]; 9167 9168 u8 reserved_at_40[0xc0]; 9169 9170 struct mlx5_ifc_tisc_bits ctx; 9171 }; 9172 9173 struct mlx5_ifc_create_tir_out_bits { 9174 u8 status[0x8]; 9175 u8 icm_address_63_40[0x18]; 9176 9177 u8 syndrome[0x20]; 9178 9179 u8 icm_address_39_32[0x8]; 9180 u8 tirn[0x18]; 9181 9182 u8 icm_address_31_0[0x20]; 9183 }; 9184 9185 struct mlx5_ifc_create_tir_in_bits { 9186 u8 opcode[0x10]; 9187 u8 uid[0x10]; 9188 9189 u8 reserved_at_20[0x10]; 9190 u8 op_mod[0x10]; 9191 9192 u8 reserved_at_40[0xc0]; 9193 9194 struct mlx5_ifc_tirc_bits ctx; 9195 }; 9196 9197 struct mlx5_ifc_create_srq_out_bits { 9198 u8 status[0x8]; 9199 u8 reserved_at_8[0x18]; 9200 9201 u8 syndrome[0x20]; 9202 9203 u8 reserved_at_40[0x8]; 9204 u8 srqn[0x18]; 9205 9206 u8 reserved_at_60[0x20]; 9207 }; 9208 9209 struct mlx5_ifc_create_srq_in_bits { 9210 u8 opcode[0x10]; 9211 u8 uid[0x10]; 9212 9213 u8 reserved_at_20[0x10]; 9214 u8 op_mod[0x10]; 9215 9216 u8 reserved_at_40[0x40]; 9217 9218 struct mlx5_ifc_srqc_bits srq_context_entry; 9219 9220 u8 reserved_at_280[0x600]; 9221 9222 u8 pas[][0x40]; 9223 }; 9224 9225 struct mlx5_ifc_create_sq_out_bits { 9226 u8 status[0x8]; 9227 u8 reserved_at_8[0x18]; 9228 9229 u8 syndrome[0x20]; 9230 9231 u8 reserved_at_40[0x8]; 9232 u8 sqn[0x18]; 9233 9234 u8 reserved_at_60[0x20]; 9235 }; 9236 9237 struct mlx5_ifc_create_sq_in_bits { 9238 u8 opcode[0x10]; 9239 u8 uid[0x10]; 9240 9241 u8 reserved_at_20[0x10]; 9242 u8 op_mod[0x10]; 9243 9244 u8 reserved_at_40[0xc0]; 9245 9246 struct mlx5_ifc_sqc_bits ctx; 9247 }; 9248 9249 struct mlx5_ifc_create_scheduling_element_out_bits { 9250 u8 status[0x8]; 9251 u8 reserved_at_8[0x18]; 9252 9253 u8 syndrome[0x20]; 9254 9255 u8 reserved_at_40[0x40]; 9256 9257 u8 scheduling_element_id[0x20]; 9258 9259 u8 reserved_at_a0[0x160]; 9260 }; 9261 9262 struct mlx5_ifc_create_scheduling_element_in_bits { 9263 u8 opcode[0x10]; 9264 u8 reserved_at_10[0x10]; 9265 9266 u8 reserved_at_20[0x10]; 9267 u8 op_mod[0x10]; 9268 9269 u8 scheduling_hierarchy[0x8]; 9270 u8 reserved_at_48[0x18]; 9271 9272 u8 reserved_at_60[0xa0]; 9273 9274 struct mlx5_ifc_scheduling_context_bits scheduling_context; 9275 9276 u8 reserved_at_300[0x100]; 9277 }; 9278 9279 struct mlx5_ifc_create_rqt_out_bits { 9280 u8 status[0x8]; 9281 u8 reserved_at_8[0x18]; 9282 9283 u8 syndrome[0x20]; 9284 9285 u8 reserved_at_40[0x8]; 9286 u8 rqtn[0x18]; 9287 9288 u8 reserved_at_60[0x20]; 9289 }; 9290 9291 struct mlx5_ifc_create_rqt_in_bits { 9292 u8 opcode[0x10]; 9293 u8 uid[0x10]; 9294 9295 u8 reserved_at_20[0x10]; 9296 u8 op_mod[0x10]; 9297 9298 u8 reserved_at_40[0xc0]; 9299 9300 struct mlx5_ifc_rqtc_bits rqt_context; 9301 }; 9302 9303 struct mlx5_ifc_create_rq_out_bits { 9304 u8 status[0x8]; 9305 u8 reserved_at_8[0x18]; 9306 9307 u8 syndrome[0x20]; 9308 9309 u8 reserved_at_40[0x8]; 9310 u8 rqn[0x18]; 9311 9312 u8 reserved_at_60[0x20]; 9313 }; 9314 9315 struct mlx5_ifc_create_rq_in_bits { 9316 u8 opcode[0x10]; 9317 u8 uid[0x10]; 9318 9319 u8 reserved_at_20[0x10]; 9320 u8 op_mod[0x10]; 9321 9322 u8 reserved_at_40[0xc0]; 9323 9324 struct mlx5_ifc_rqc_bits ctx; 9325 }; 9326 9327 struct mlx5_ifc_create_rmp_out_bits { 9328 u8 status[0x8]; 9329 u8 reserved_at_8[0x18]; 9330 9331 u8 syndrome[0x20]; 9332 9333 u8 reserved_at_40[0x8]; 9334 u8 rmpn[0x18]; 9335 9336 u8 reserved_at_60[0x20]; 9337 }; 9338 9339 struct mlx5_ifc_create_rmp_in_bits { 9340 u8 opcode[0x10]; 9341 u8 uid[0x10]; 9342 9343 u8 reserved_at_20[0x10]; 9344 u8 op_mod[0x10]; 9345 9346 u8 reserved_at_40[0xc0]; 9347 9348 struct mlx5_ifc_rmpc_bits ctx; 9349 }; 9350 9351 struct mlx5_ifc_create_qp_out_bits { 9352 u8 status[0x8]; 9353 u8 reserved_at_8[0x18]; 9354 9355 u8 syndrome[0x20]; 9356 9357 u8 reserved_at_40[0x8]; 9358 u8 qpn[0x18]; 9359 9360 u8 ece[0x20]; 9361 }; 9362 9363 struct mlx5_ifc_create_qp_in_bits { 9364 u8 opcode[0x10]; 9365 u8 uid[0x10]; 9366 9367 u8 reserved_at_20[0x10]; 9368 u8 op_mod[0x10]; 9369 9370 u8 qpc_ext[0x1]; 9371 u8 reserved_at_41[0x7]; 9372 u8 input_qpn[0x18]; 9373 9374 u8 reserved_at_60[0x20]; 9375 u8 opt_param_mask[0x20]; 9376 9377 u8 ece[0x20]; 9378 9379 struct mlx5_ifc_qpc_bits qpc; 9380 9381 u8 wq_umem_offset[0x40]; 9382 9383 u8 wq_umem_id[0x20]; 9384 9385 u8 wq_umem_valid[0x1]; 9386 u8 reserved_at_861[0x1f]; 9387 9388 u8 pas[][0x40]; 9389 }; 9390 9391 struct mlx5_ifc_create_psv_out_bits { 9392 u8 status[0x8]; 9393 u8 reserved_at_8[0x18]; 9394 9395 u8 syndrome[0x20]; 9396 9397 u8 reserved_at_40[0x40]; 9398 9399 u8 reserved_at_80[0x8]; 9400 u8 psv0_index[0x18]; 9401 9402 u8 reserved_at_a0[0x8]; 9403 u8 psv1_index[0x18]; 9404 9405 u8 reserved_at_c0[0x8]; 9406 u8 psv2_index[0x18]; 9407 9408 u8 reserved_at_e0[0x8]; 9409 u8 psv3_index[0x18]; 9410 }; 9411 9412 struct mlx5_ifc_create_psv_in_bits { 9413 u8 opcode[0x10]; 9414 u8 reserved_at_10[0x10]; 9415 9416 u8 reserved_at_20[0x10]; 9417 u8 op_mod[0x10]; 9418 9419 u8 num_psv[0x4]; 9420 u8 reserved_at_44[0x4]; 9421 u8 pd[0x18]; 9422 9423 u8 reserved_at_60[0x20]; 9424 }; 9425 9426 struct mlx5_ifc_create_mkey_out_bits { 9427 u8 status[0x8]; 9428 u8 reserved_at_8[0x18]; 9429 9430 u8 syndrome[0x20]; 9431 9432 u8 reserved_at_40[0x8]; 9433 u8 mkey_index[0x18]; 9434 9435 u8 reserved_at_60[0x20]; 9436 }; 9437 9438 struct mlx5_ifc_create_mkey_in_bits { 9439 u8 opcode[0x10]; 9440 u8 uid[0x10]; 9441 9442 u8 reserved_at_20[0x10]; 9443 u8 op_mod[0x10]; 9444 9445 u8 reserved_at_40[0x20]; 9446 9447 u8 pg_access[0x1]; 9448 u8 mkey_umem_valid[0x1]; 9449 u8 data_direct[0x1]; 9450 u8 reserved_at_63[0x1d]; 9451 9452 struct mlx5_ifc_mkc_bits memory_key_mkey_entry; 9453 9454 u8 reserved_at_280[0x80]; 9455 9456 u8 translations_octword_actual_size[0x20]; 9457 9458 u8 reserved_at_320[0x560]; 9459 9460 u8 klm_pas_mtt[][0x20]; 9461 }; 9462 9463 enum { 9464 MLX5_FLOW_TABLE_TYPE_NIC_RX = 0x0, 9465 MLX5_FLOW_TABLE_TYPE_NIC_TX = 0x1, 9466 MLX5_FLOW_TABLE_TYPE_ESW_EGRESS_ACL = 0x2, 9467 MLX5_FLOW_TABLE_TYPE_ESW_INGRESS_ACL = 0x3, 9468 MLX5_FLOW_TABLE_TYPE_FDB = 0X4, 9469 MLX5_FLOW_TABLE_TYPE_SNIFFER_RX = 0X5, 9470 MLX5_FLOW_TABLE_TYPE_SNIFFER_TX = 0X6, 9471 }; 9472 9473 struct mlx5_ifc_create_flow_table_out_bits { 9474 u8 status[0x8]; 9475 u8 icm_address_63_40[0x18]; 9476 9477 u8 syndrome[0x20]; 9478 9479 u8 icm_address_39_32[0x8]; 9480 u8 table_id[0x18]; 9481 9482 u8 icm_address_31_0[0x20]; 9483 }; 9484 9485 struct mlx5_ifc_create_flow_table_in_bits { 9486 u8 opcode[0x10]; 9487 u8 uid[0x10]; 9488 9489 u8 reserved_at_20[0x10]; 9490 u8 op_mod[0x10]; 9491 9492 u8 other_vport[0x1]; 9493 u8 reserved_at_41[0xf]; 9494 u8 vport_number[0x10]; 9495 9496 u8 reserved_at_60[0x20]; 9497 9498 u8 table_type[0x8]; 9499 u8 reserved_at_88[0x18]; 9500 9501 u8 reserved_at_a0[0x20]; 9502 9503 struct mlx5_ifc_flow_table_context_bits flow_table_context; 9504 }; 9505 9506 struct mlx5_ifc_create_flow_group_out_bits { 9507 u8 status[0x8]; 9508 u8 reserved_at_8[0x18]; 9509 9510 u8 syndrome[0x20]; 9511 9512 u8 reserved_at_40[0x8]; 9513 u8 group_id[0x18]; 9514 9515 u8 reserved_at_60[0x20]; 9516 }; 9517 9518 enum { 9519 MLX5_CREATE_FLOW_GROUP_IN_GROUP_TYPE_TCAM_SUBTABLE = 0x0, 9520 MLX5_CREATE_FLOW_GROUP_IN_GROUP_TYPE_HASH_SPLIT = 0x1, 9521 }; 9522 9523 enum { 9524 MLX5_CREATE_FLOW_GROUP_IN_MATCH_CRITERIA_ENABLE_OUTER_HEADERS = 0x0, 9525 MLX5_CREATE_FLOW_GROUP_IN_MATCH_CRITERIA_ENABLE_MISC_PARAMETERS = 0x1, 9526 MLX5_CREATE_FLOW_GROUP_IN_MATCH_CRITERIA_ENABLE_INNER_HEADERS = 0x2, 9527 MLX5_CREATE_FLOW_GROUP_IN_MATCH_CRITERIA_ENABLE_MISC_PARAMETERS_2 = 0x3, 9528 }; 9529 9530 struct mlx5_ifc_create_flow_group_in_bits { 9531 u8 opcode[0x10]; 9532 u8 reserved_at_10[0x10]; 9533 9534 u8 reserved_at_20[0x10]; 9535 u8 op_mod[0x10]; 9536 9537 u8 other_vport[0x1]; 9538 u8 reserved_at_41[0xf]; 9539 u8 vport_number[0x10]; 9540 9541 u8 reserved_at_60[0x20]; 9542 9543 u8 table_type[0x8]; 9544 u8 reserved_at_88[0x4]; 9545 u8 group_type[0x4]; 9546 u8 reserved_at_90[0x10]; 9547 9548 u8 reserved_at_a0[0x8]; 9549 u8 table_id[0x18]; 9550 9551 u8 source_eswitch_owner_vhca_id_valid[0x1]; 9552 9553 u8 reserved_at_c1[0x1f]; 9554 9555 u8 start_flow_index[0x20]; 9556 9557 u8 reserved_at_100[0x20]; 9558 9559 u8 end_flow_index[0x20]; 9560 9561 u8 reserved_at_140[0x10]; 9562 u8 match_definer_id[0x10]; 9563 9564 u8 reserved_at_160[0x80]; 9565 9566 u8 reserved_at_1e0[0x18]; 9567 u8 match_criteria_enable[0x8]; 9568 9569 struct mlx5_ifc_fte_match_param_bits match_criteria; 9570 9571 u8 reserved_at_1200[0xe00]; 9572 }; 9573 9574 struct mlx5_ifc_create_eq_out_bits { 9575 u8 status[0x8]; 9576 u8 reserved_at_8[0x18]; 9577 9578 u8 syndrome[0x20]; 9579 9580 u8 reserved_at_40[0x18]; 9581 u8 eq_number[0x8]; 9582 9583 u8 reserved_at_60[0x20]; 9584 }; 9585 9586 struct mlx5_ifc_create_eq_in_bits { 9587 u8 opcode[0x10]; 9588 u8 uid[0x10]; 9589 9590 u8 reserved_at_20[0x10]; 9591 u8 op_mod[0x10]; 9592 9593 u8 reserved_at_40[0x40]; 9594 9595 struct mlx5_ifc_eqc_bits eq_context_entry; 9596 9597 u8 reserved_at_280[0x40]; 9598 9599 u8 event_bitmask[4][0x40]; 9600 9601 u8 reserved_at_3c0[0x4c0]; 9602 9603 u8 pas[][0x40]; 9604 }; 9605 9606 struct mlx5_ifc_create_dct_out_bits { 9607 u8 status[0x8]; 9608 u8 reserved_at_8[0x18]; 9609 9610 u8 syndrome[0x20]; 9611 9612 u8 reserved_at_40[0x8]; 9613 u8 dctn[0x18]; 9614 9615 u8 ece[0x20]; 9616 }; 9617 9618 struct mlx5_ifc_create_dct_in_bits { 9619 u8 opcode[0x10]; 9620 u8 uid[0x10]; 9621 9622 u8 reserved_at_20[0x10]; 9623 u8 op_mod[0x10]; 9624 9625 u8 reserved_at_40[0x40]; 9626 9627 struct mlx5_ifc_dctc_bits dct_context_entry; 9628 9629 u8 reserved_at_280[0x180]; 9630 }; 9631 9632 struct mlx5_ifc_create_cq_out_bits { 9633 u8 status[0x8]; 9634 u8 reserved_at_8[0x18]; 9635 9636 u8 syndrome[0x20]; 9637 9638 u8 reserved_at_40[0x8]; 9639 u8 cqn[0x18]; 9640 9641 u8 reserved_at_60[0x20]; 9642 }; 9643 9644 struct mlx5_ifc_create_cq_in_bits { 9645 u8 opcode[0x10]; 9646 u8 uid[0x10]; 9647 9648 u8 reserved_at_20[0x10]; 9649 u8 op_mod[0x10]; 9650 9651 u8 reserved_at_40[0x40]; 9652 9653 struct mlx5_ifc_cqc_bits cq_context; 9654 9655 u8 reserved_at_280[0x60]; 9656 9657 u8 cq_umem_valid[0x1]; 9658 u8 reserved_at_2e1[0x59f]; 9659 9660 u8 pas[][0x40]; 9661 }; 9662 9663 struct mlx5_ifc_config_int_moderation_out_bits { 9664 u8 status[0x8]; 9665 u8 reserved_at_8[0x18]; 9666 9667 u8 syndrome[0x20]; 9668 9669 u8 reserved_at_40[0x4]; 9670 u8 min_delay[0xc]; 9671 u8 int_vector[0x10]; 9672 9673 u8 reserved_at_60[0x20]; 9674 }; 9675 9676 enum { 9677 MLX5_CONFIG_INT_MODERATION_IN_OP_MOD_WRITE = 0x0, 9678 MLX5_CONFIG_INT_MODERATION_IN_OP_MOD_READ = 0x1, 9679 }; 9680 9681 struct mlx5_ifc_config_int_moderation_in_bits { 9682 u8 opcode[0x10]; 9683 u8 reserved_at_10[0x10]; 9684 9685 u8 reserved_at_20[0x10]; 9686 u8 op_mod[0x10]; 9687 9688 u8 reserved_at_40[0x4]; 9689 u8 min_delay[0xc]; 9690 u8 int_vector[0x10]; 9691 9692 u8 reserved_at_60[0x20]; 9693 }; 9694 9695 struct mlx5_ifc_attach_to_mcg_out_bits { 9696 u8 status[0x8]; 9697 u8 reserved_at_8[0x18]; 9698 9699 u8 syndrome[0x20]; 9700 9701 u8 reserved_at_40[0x40]; 9702 }; 9703 9704 struct mlx5_ifc_attach_to_mcg_in_bits { 9705 u8 opcode[0x10]; 9706 u8 uid[0x10]; 9707 9708 u8 reserved_at_20[0x10]; 9709 u8 op_mod[0x10]; 9710 9711 u8 reserved_at_40[0x8]; 9712 u8 qpn[0x18]; 9713 9714 u8 reserved_at_60[0x20]; 9715 9716 u8 multicast_gid[16][0x8]; 9717 }; 9718 9719 struct mlx5_ifc_arm_xrq_out_bits { 9720 u8 status[0x8]; 9721 u8 reserved_at_8[0x18]; 9722 9723 u8 syndrome[0x20]; 9724 9725 u8 reserved_at_40[0x40]; 9726 }; 9727 9728 struct mlx5_ifc_arm_xrq_in_bits { 9729 u8 opcode[0x10]; 9730 u8 reserved_at_10[0x10]; 9731 9732 u8 reserved_at_20[0x10]; 9733 u8 op_mod[0x10]; 9734 9735 u8 reserved_at_40[0x8]; 9736 u8 xrqn[0x18]; 9737 9738 u8 reserved_at_60[0x10]; 9739 u8 lwm[0x10]; 9740 }; 9741 9742 struct mlx5_ifc_arm_xrc_srq_out_bits { 9743 u8 status[0x8]; 9744 u8 reserved_at_8[0x18]; 9745 9746 u8 syndrome[0x20]; 9747 9748 u8 reserved_at_40[0x40]; 9749 }; 9750 9751 enum { 9752 MLX5_ARM_XRC_SRQ_IN_OP_MOD_XRC_SRQ = 0x1, 9753 }; 9754 9755 struct mlx5_ifc_arm_xrc_srq_in_bits { 9756 u8 opcode[0x10]; 9757 u8 uid[0x10]; 9758 9759 u8 reserved_at_20[0x10]; 9760 u8 op_mod[0x10]; 9761 9762 u8 reserved_at_40[0x8]; 9763 u8 xrc_srqn[0x18]; 9764 9765 u8 reserved_at_60[0x10]; 9766 u8 lwm[0x10]; 9767 }; 9768 9769 struct mlx5_ifc_arm_rq_out_bits { 9770 u8 status[0x8]; 9771 u8 reserved_at_8[0x18]; 9772 9773 u8 syndrome[0x20]; 9774 9775 u8 reserved_at_40[0x40]; 9776 }; 9777 9778 enum { 9779 MLX5_ARM_RQ_IN_OP_MOD_SRQ = 0x1, 9780 MLX5_ARM_RQ_IN_OP_MOD_XRQ = 0x2, 9781 }; 9782 9783 struct mlx5_ifc_arm_rq_in_bits { 9784 u8 opcode[0x10]; 9785 u8 uid[0x10]; 9786 9787 u8 reserved_at_20[0x10]; 9788 u8 op_mod[0x10]; 9789 9790 u8 reserved_at_40[0x8]; 9791 u8 srq_number[0x18]; 9792 9793 u8 reserved_at_60[0x10]; 9794 u8 lwm[0x10]; 9795 }; 9796 9797 struct mlx5_ifc_arm_dct_out_bits { 9798 u8 status[0x8]; 9799 u8 reserved_at_8[0x18]; 9800 9801 u8 syndrome[0x20]; 9802 9803 u8 reserved_at_40[0x40]; 9804 }; 9805 9806 struct mlx5_ifc_arm_dct_in_bits { 9807 u8 opcode[0x10]; 9808 u8 reserved_at_10[0x10]; 9809 9810 u8 reserved_at_20[0x10]; 9811 u8 op_mod[0x10]; 9812 9813 u8 reserved_at_40[0x8]; 9814 u8 dct_number[0x18]; 9815 9816 u8 reserved_at_60[0x20]; 9817 }; 9818 9819 struct mlx5_ifc_alloc_xrcd_out_bits { 9820 u8 status[0x8]; 9821 u8 reserved_at_8[0x18]; 9822 9823 u8 syndrome[0x20]; 9824 9825 u8 reserved_at_40[0x8]; 9826 u8 xrcd[0x18]; 9827 9828 u8 reserved_at_60[0x20]; 9829 }; 9830 9831 struct mlx5_ifc_alloc_xrcd_in_bits { 9832 u8 opcode[0x10]; 9833 u8 uid[0x10]; 9834 9835 u8 reserved_at_20[0x10]; 9836 u8 op_mod[0x10]; 9837 9838 u8 reserved_at_40[0x40]; 9839 }; 9840 9841 struct mlx5_ifc_alloc_uar_out_bits { 9842 u8 status[0x8]; 9843 u8 reserved_at_8[0x18]; 9844 9845 u8 syndrome[0x20]; 9846 9847 u8 reserved_at_40[0x8]; 9848 u8 uar[0x18]; 9849 9850 u8 reserved_at_60[0x20]; 9851 }; 9852 9853 struct mlx5_ifc_alloc_uar_in_bits { 9854 u8 opcode[0x10]; 9855 u8 uid[0x10]; 9856 9857 u8 reserved_at_20[0x10]; 9858 u8 op_mod[0x10]; 9859 9860 u8 reserved_at_40[0x40]; 9861 }; 9862 9863 struct mlx5_ifc_alloc_transport_domain_out_bits { 9864 u8 status[0x8]; 9865 u8 reserved_at_8[0x18]; 9866 9867 u8 syndrome[0x20]; 9868 9869 u8 reserved_at_40[0x8]; 9870 u8 transport_domain[0x18]; 9871 9872 u8 reserved_at_60[0x20]; 9873 }; 9874 9875 struct mlx5_ifc_alloc_transport_domain_in_bits { 9876 u8 opcode[0x10]; 9877 u8 uid[0x10]; 9878 9879 u8 reserved_at_20[0x10]; 9880 u8 op_mod[0x10]; 9881 9882 u8 reserved_at_40[0x40]; 9883 }; 9884 9885 struct mlx5_ifc_alloc_q_counter_out_bits { 9886 u8 status[0x8]; 9887 u8 reserved_at_8[0x18]; 9888 9889 u8 syndrome[0x20]; 9890 9891 u8 reserved_at_40[0x18]; 9892 u8 counter_set_id[0x8]; 9893 9894 u8 reserved_at_60[0x20]; 9895 }; 9896 9897 struct mlx5_ifc_alloc_q_counter_in_bits { 9898 u8 opcode[0x10]; 9899 u8 uid[0x10]; 9900 9901 u8 reserved_at_20[0x10]; 9902 u8 op_mod[0x10]; 9903 9904 u8 reserved_at_40[0x40]; 9905 }; 9906 9907 struct mlx5_ifc_alloc_pd_out_bits { 9908 u8 status[0x8]; 9909 u8 reserved_at_8[0x18]; 9910 9911 u8 syndrome[0x20]; 9912 9913 u8 reserved_at_40[0x8]; 9914 u8 pd[0x18]; 9915 9916 u8 reserved_at_60[0x20]; 9917 }; 9918 9919 struct mlx5_ifc_alloc_pd_in_bits { 9920 u8 opcode[0x10]; 9921 u8 uid[0x10]; 9922 9923 u8 reserved_at_20[0x10]; 9924 u8 op_mod[0x10]; 9925 9926 u8 reserved_at_40[0x40]; 9927 }; 9928 9929 struct mlx5_ifc_alloc_flow_counter_out_bits { 9930 u8 status[0x8]; 9931 u8 reserved_at_8[0x18]; 9932 9933 u8 syndrome[0x20]; 9934 9935 u8 flow_counter_id[0x20]; 9936 9937 u8 reserved_at_60[0x20]; 9938 }; 9939 9940 struct mlx5_ifc_alloc_flow_counter_in_bits { 9941 u8 opcode[0x10]; 9942 u8 reserved_at_10[0x10]; 9943 9944 u8 reserved_at_20[0x10]; 9945 u8 op_mod[0x10]; 9946 9947 u8 reserved_at_40[0x33]; 9948 u8 flow_counter_bulk_log_size[0x5]; 9949 u8 flow_counter_bulk[0x8]; 9950 }; 9951 9952 struct mlx5_ifc_add_vxlan_udp_dport_out_bits { 9953 u8 status[0x8]; 9954 u8 reserved_at_8[0x18]; 9955 9956 u8 syndrome[0x20]; 9957 9958 u8 reserved_at_40[0x40]; 9959 }; 9960 9961 struct mlx5_ifc_add_vxlan_udp_dport_in_bits { 9962 u8 opcode[0x10]; 9963 u8 reserved_at_10[0x10]; 9964 9965 u8 reserved_at_20[0x10]; 9966 u8 op_mod[0x10]; 9967 9968 u8 reserved_at_40[0x20]; 9969 9970 u8 reserved_at_60[0x10]; 9971 u8 vxlan_udp_port[0x10]; 9972 }; 9973 9974 struct mlx5_ifc_set_pp_rate_limit_out_bits { 9975 u8 status[0x8]; 9976 u8 reserved_at_8[0x18]; 9977 9978 u8 syndrome[0x20]; 9979 9980 u8 reserved_at_40[0x40]; 9981 }; 9982 9983 struct mlx5_ifc_set_pp_rate_limit_context_bits { 9984 u8 rate_limit[0x20]; 9985 9986 u8 burst_upper_bound[0x20]; 9987 9988 u8 reserved_at_40[0x10]; 9989 u8 typical_packet_size[0x10]; 9990 9991 u8 reserved_at_60[0x120]; 9992 }; 9993 9994 struct mlx5_ifc_set_pp_rate_limit_in_bits { 9995 u8 opcode[0x10]; 9996 u8 uid[0x10]; 9997 9998 u8 reserved_at_20[0x10]; 9999 u8 op_mod[0x10]; 10000 10001 u8 reserved_at_40[0x10]; 10002 u8 rate_limit_index[0x10]; 10003 10004 u8 reserved_at_60[0x20]; 10005 10006 struct mlx5_ifc_set_pp_rate_limit_context_bits ctx; 10007 }; 10008 10009 struct mlx5_ifc_access_register_out_bits { 10010 u8 status[0x8]; 10011 u8 reserved_at_8[0x18]; 10012 10013 u8 syndrome[0x20]; 10014 10015 u8 reserved_at_40[0x40]; 10016 10017 u8 register_data[][0x20]; 10018 }; 10019 10020 enum { 10021 MLX5_ACCESS_REGISTER_IN_OP_MOD_WRITE = 0x0, 10022 MLX5_ACCESS_REGISTER_IN_OP_MOD_READ = 0x1, 10023 }; 10024 10025 struct mlx5_ifc_access_register_in_bits { 10026 u8 opcode[0x10]; 10027 u8 reserved_at_10[0x10]; 10028 10029 u8 reserved_at_20[0x10]; 10030 u8 op_mod[0x10]; 10031 10032 u8 reserved_at_40[0x10]; 10033 u8 register_id[0x10]; 10034 10035 u8 argument[0x20]; 10036 10037 u8 register_data[][0x20]; 10038 }; 10039 10040 struct mlx5_ifc_sltp_reg_bits { 10041 u8 status[0x4]; 10042 u8 version[0x4]; 10043 u8 local_port[0x8]; 10044 u8 pnat[0x2]; 10045 u8 reserved_at_12[0x2]; 10046 u8 lane[0x4]; 10047 u8 reserved_at_18[0x8]; 10048 10049 u8 reserved_at_20[0x20]; 10050 10051 u8 reserved_at_40[0x7]; 10052 u8 polarity[0x1]; 10053 u8 ob_tap0[0x8]; 10054 u8 ob_tap1[0x8]; 10055 u8 ob_tap2[0x8]; 10056 10057 u8 reserved_at_60[0xc]; 10058 u8 ob_preemp_mode[0x4]; 10059 u8 ob_reg[0x8]; 10060 u8 ob_bias[0x8]; 10061 10062 u8 reserved_at_80[0x20]; 10063 }; 10064 10065 struct mlx5_ifc_slrg_reg_bits { 10066 u8 status[0x4]; 10067 u8 version[0x4]; 10068 u8 local_port[0x8]; 10069 u8 pnat[0x2]; 10070 u8 reserved_at_12[0x2]; 10071 u8 lane[0x4]; 10072 u8 reserved_at_18[0x8]; 10073 10074 u8 time_to_link_up[0x10]; 10075 u8 reserved_at_30[0xc]; 10076 u8 grade_lane_speed[0x4]; 10077 10078 u8 grade_version[0x8]; 10079 u8 grade[0x18]; 10080 10081 u8 reserved_at_60[0x4]; 10082 u8 height_grade_type[0x4]; 10083 u8 height_grade[0x18]; 10084 10085 u8 height_dz[0x10]; 10086 u8 height_dv[0x10]; 10087 10088 u8 reserved_at_a0[0x10]; 10089 u8 height_sigma[0x10]; 10090 10091 u8 reserved_at_c0[0x20]; 10092 10093 u8 reserved_at_e0[0x4]; 10094 u8 phase_grade_type[0x4]; 10095 u8 phase_grade[0x18]; 10096 10097 u8 reserved_at_100[0x8]; 10098 u8 phase_eo_pos[0x8]; 10099 u8 reserved_at_110[0x8]; 10100 u8 phase_eo_neg[0x8]; 10101 10102 u8 ffe_set_tested[0x10]; 10103 u8 test_errors_per_lane[0x10]; 10104 }; 10105 10106 struct mlx5_ifc_pvlc_reg_bits { 10107 u8 reserved_at_0[0x8]; 10108 u8 local_port[0x8]; 10109 u8 reserved_at_10[0x10]; 10110 10111 u8 reserved_at_20[0x1c]; 10112 u8 vl_hw_cap[0x4]; 10113 10114 u8 reserved_at_40[0x1c]; 10115 u8 vl_admin[0x4]; 10116 10117 u8 reserved_at_60[0x1c]; 10118 u8 vl_operational[0x4]; 10119 }; 10120 10121 struct mlx5_ifc_pude_reg_bits { 10122 u8 swid[0x8]; 10123 u8 local_port[0x8]; 10124 u8 reserved_at_10[0x4]; 10125 u8 admin_status[0x4]; 10126 u8 reserved_at_18[0x4]; 10127 u8 oper_status[0x4]; 10128 10129 u8 reserved_at_20[0x60]; 10130 }; 10131 10132 enum { 10133 MLX5_PTYS_CONNECTOR_TYPE_PORT_DA = 0x7, 10134 }; 10135 10136 struct mlx5_ifc_ptys_reg_bits { 10137 u8 reserved_at_0[0x1]; 10138 u8 an_disable_admin[0x1]; 10139 u8 an_disable_cap[0x1]; 10140 u8 reserved_at_3[0x5]; 10141 u8 local_port[0x8]; 10142 u8 reserved_at_10[0x8]; 10143 u8 plane_ind[0x4]; 10144 u8 reserved_at_1c[0x1]; 10145 u8 proto_mask[0x3]; 10146 10147 u8 an_status[0x4]; 10148 u8 reserved_at_24[0xc]; 10149 u8 data_rate_oper[0x10]; 10150 10151 u8 ext_eth_proto_capability[0x20]; 10152 10153 u8 eth_proto_capability[0x20]; 10154 10155 u8 ib_link_width_capability[0x10]; 10156 u8 ib_proto_capability[0x10]; 10157 10158 u8 ext_eth_proto_admin[0x20]; 10159 10160 u8 eth_proto_admin[0x20]; 10161 10162 u8 ib_link_width_admin[0x10]; 10163 u8 ib_proto_admin[0x10]; 10164 10165 u8 ext_eth_proto_oper[0x20]; 10166 10167 u8 eth_proto_oper[0x20]; 10168 10169 u8 ib_link_width_oper[0x10]; 10170 u8 ib_proto_oper[0x10]; 10171 10172 u8 reserved_at_160[0x8]; 10173 u8 lane_rate_oper[0x14]; 10174 u8 connector_type[0x4]; 10175 10176 u8 eth_proto_lp_advertise[0x20]; 10177 10178 u8 reserved_at_1a0[0x60]; 10179 }; 10180 10181 struct mlx5_ifc_mlcr_reg_bits { 10182 u8 reserved_at_0[0x8]; 10183 u8 local_port[0x8]; 10184 u8 reserved_at_10[0x20]; 10185 10186 u8 beacon_duration[0x10]; 10187 u8 reserved_at_40[0x10]; 10188 10189 u8 beacon_remain[0x10]; 10190 }; 10191 10192 struct mlx5_ifc_ptas_reg_bits { 10193 u8 reserved_at_0[0x20]; 10194 10195 u8 algorithm_options[0x10]; 10196 u8 reserved_at_30[0x4]; 10197 u8 repetitions_mode[0x4]; 10198 u8 num_of_repetitions[0x8]; 10199 10200 u8 grade_version[0x8]; 10201 u8 height_grade_type[0x4]; 10202 u8 phase_grade_type[0x4]; 10203 u8 height_grade_weight[0x8]; 10204 u8 phase_grade_weight[0x8]; 10205 10206 u8 gisim_measure_bits[0x10]; 10207 u8 adaptive_tap_measure_bits[0x10]; 10208 10209 u8 ber_bath_high_error_threshold[0x10]; 10210 u8 ber_bath_mid_error_threshold[0x10]; 10211 10212 u8 ber_bath_low_error_threshold[0x10]; 10213 u8 one_ratio_high_threshold[0x10]; 10214 10215 u8 one_ratio_high_mid_threshold[0x10]; 10216 u8 one_ratio_low_mid_threshold[0x10]; 10217 10218 u8 one_ratio_low_threshold[0x10]; 10219 u8 ndeo_error_threshold[0x10]; 10220 10221 u8 mixer_offset_step_size[0x10]; 10222 u8 reserved_at_110[0x8]; 10223 u8 mix90_phase_for_voltage_bath[0x8]; 10224 10225 u8 mixer_offset_start[0x10]; 10226 u8 mixer_offset_end[0x10]; 10227 10228 u8 reserved_at_140[0x15]; 10229 u8 ber_test_time[0xb]; 10230 }; 10231 10232 struct mlx5_ifc_pspa_reg_bits { 10233 u8 swid[0x8]; 10234 u8 local_port[0x8]; 10235 u8 sub_port[0x8]; 10236 u8 reserved_at_18[0x8]; 10237 10238 u8 reserved_at_20[0x20]; 10239 }; 10240 10241 struct mlx5_ifc_pqdr_reg_bits { 10242 u8 reserved_at_0[0x8]; 10243 u8 local_port[0x8]; 10244 u8 reserved_at_10[0x5]; 10245 u8 prio[0x3]; 10246 u8 reserved_at_18[0x6]; 10247 u8 mode[0x2]; 10248 10249 u8 reserved_at_20[0x20]; 10250 10251 u8 reserved_at_40[0x10]; 10252 u8 min_threshold[0x10]; 10253 10254 u8 reserved_at_60[0x10]; 10255 u8 max_threshold[0x10]; 10256 10257 u8 reserved_at_80[0x10]; 10258 u8 mark_probability_denominator[0x10]; 10259 10260 u8 reserved_at_a0[0x60]; 10261 }; 10262 10263 struct mlx5_ifc_ppsc_reg_bits { 10264 u8 reserved_at_0[0x8]; 10265 u8 local_port[0x8]; 10266 u8 reserved_at_10[0x10]; 10267 10268 u8 reserved_at_20[0x60]; 10269 10270 u8 reserved_at_80[0x1c]; 10271 u8 wrps_admin[0x4]; 10272 10273 u8 reserved_at_a0[0x1c]; 10274 u8 wrps_status[0x4]; 10275 10276 u8 reserved_at_c0[0x8]; 10277 u8 up_threshold[0x8]; 10278 u8 reserved_at_d0[0x8]; 10279 u8 down_threshold[0x8]; 10280 10281 u8 reserved_at_e0[0x20]; 10282 10283 u8 reserved_at_100[0x1c]; 10284 u8 srps_admin[0x4]; 10285 10286 u8 reserved_at_120[0x1c]; 10287 u8 srps_status[0x4]; 10288 10289 u8 reserved_at_140[0x40]; 10290 }; 10291 10292 struct mlx5_ifc_pplr_reg_bits { 10293 u8 reserved_at_0[0x8]; 10294 u8 local_port[0x8]; 10295 u8 reserved_at_10[0x10]; 10296 10297 u8 reserved_at_20[0x8]; 10298 u8 lb_cap[0x8]; 10299 u8 reserved_at_30[0x8]; 10300 u8 lb_en[0x8]; 10301 }; 10302 10303 struct mlx5_ifc_pplm_reg_bits { 10304 u8 reserved_at_0[0x8]; 10305 u8 local_port[0x8]; 10306 u8 reserved_at_10[0x10]; 10307 10308 u8 reserved_at_20[0x20]; 10309 10310 u8 port_profile_mode[0x8]; 10311 u8 static_port_profile[0x8]; 10312 u8 active_port_profile[0x8]; 10313 u8 reserved_at_58[0x8]; 10314 10315 u8 retransmission_active[0x8]; 10316 u8 fec_mode_active[0x18]; 10317 10318 u8 rs_fec_correction_bypass_cap[0x4]; 10319 u8 reserved_at_84[0x8]; 10320 u8 fec_override_cap_56g[0x4]; 10321 u8 fec_override_cap_100g[0x4]; 10322 u8 fec_override_cap_50g[0x4]; 10323 u8 fec_override_cap_25g[0x4]; 10324 u8 fec_override_cap_10g_40g[0x4]; 10325 10326 u8 rs_fec_correction_bypass_admin[0x4]; 10327 u8 reserved_at_a4[0x8]; 10328 u8 fec_override_admin_56g[0x4]; 10329 u8 fec_override_admin_100g[0x4]; 10330 u8 fec_override_admin_50g[0x4]; 10331 u8 fec_override_admin_25g[0x4]; 10332 u8 fec_override_admin_10g_40g[0x4]; 10333 10334 u8 fec_override_cap_400g_8x[0x10]; 10335 u8 fec_override_cap_200g_4x[0x10]; 10336 10337 u8 fec_override_cap_100g_2x[0x10]; 10338 u8 fec_override_cap_50g_1x[0x10]; 10339 10340 u8 fec_override_admin_400g_8x[0x10]; 10341 u8 fec_override_admin_200g_4x[0x10]; 10342 10343 u8 fec_override_admin_100g_2x[0x10]; 10344 u8 fec_override_admin_50g_1x[0x10]; 10345 10346 u8 fec_override_cap_800g_8x[0x10]; 10347 u8 fec_override_cap_400g_4x[0x10]; 10348 10349 u8 fec_override_cap_200g_2x[0x10]; 10350 u8 fec_override_cap_100g_1x[0x10]; 10351 10352 u8 reserved_at_180[0xa0]; 10353 10354 u8 fec_override_admin_800g_8x[0x10]; 10355 u8 fec_override_admin_400g_4x[0x10]; 10356 10357 u8 fec_override_admin_200g_2x[0x10]; 10358 u8 fec_override_admin_100g_1x[0x10]; 10359 10360 u8 reserved_at_260[0x60]; 10361 10362 u8 fec_override_cap_1600g_8x[0x10]; 10363 u8 fec_override_cap_800g_4x[0x10]; 10364 10365 u8 fec_override_cap_400g_2x[0x10]; 10366 u8 fec_override_cap_200g_1x[0x10]; 10367 10368 u8 fec_override_admin_1600g_8x[0x10]; 10369 u8 fec_override_admin_800g_4x[0x10]; 10370 10371 u8 fec_override_admin_400g_2x[0x10]; 10372 u8 fec_override_admin_200g_1x[0x10]; 10373 10374 u8 reserved_at_340[0x80]; 10375 }; 10376 10377 struct mlx5_ifc_ppcnt_reg_bits { 10378 u8 swid[0x8]; 10379 u8 local_port[0x8]; 10380 u8 pnat[0x2]; 10381 u8 reserved_at_12[0x8]; 10382 u8 grp[0x6]; 10383 10384 u8 clr[0x1]; 10385 u8 reserved_at_21[0x13]; 10386 u8 plane_ind[0x4]; 10387 u8 reserved_at_38[0x3]; 10388 u8 prio_tc[0x5]; 10389 10390 union mlx5_ifc_eth_cntrs_grp_data_layout_auto_bits counter_set; 10391 }; 10392 10393 struct mlx5_ifc_mpein_reg_bits { 10394 u8 reserved_at_0[0x2]; 10395 u8 depth[0x6]; 10396 u8 pcie_index[0x8]; 10397 u8 node[0x8]; 10398 u8 reserved_at_18[0x8]; 10399 10400 u8 capability_mask[0x20]; 10401 10402 u8 reserved_at_40[0x8]; 10403 u8 link_width_enabled[0x8]; 10404 u8 link_speed_enabled[0x10]; 10405 10406 u8 lane0_physical_position[0x8]; 10407 u8 link_width_active[0x8]; 10408 u8 link_speed_active[0x10]; 10409 10410 u8 num_of_pfs[0x10]; 10411 u8 num_of_vfs[0x10]; 10412 10413 u8 bdf0[0x10]; 10414 u8 reserved_at_b0[0x10]; 10415 10416 u8 max_read_request_size[0x4]; 10417 u8 max_payload_size[0x4]; 10418 u8 reserved_at_c8[0x5]; 10419 u8 pwr_status[0x3]; 10420 u8 port_type[0x4]; 10421 u8 reserved_at_d4[0xb]; 10422 u8 lane_reversal[0x1]; 10423 10424 u8 reserved_at_e0[0x14]; 10425 u8 pci_power[0xc]; 10426 10427 u8 reserved_at_100[0x20]; 10428 10429 u8 device_status[0x10]; 10430 u8 port_state[0x8]; 10431 u8 reserved_at_138[0x8]; 10432 10433 u8 reserved_at_140[0x10]; 10434 u8 receiver_detect_result[0x10]; 10435 10436 u8 reserved_at_160[0x20]; 10437 }; 10438 10439 struct mlx5_ifc_mpcnt_reg_bits { 10440 u8 reserved_at_0[0x8]; 10441 u8 pcie_index[0x8]; 10442 u8 reserved_at_10[0xa]; 10443 u8 grp[0x6]; 10444 10445 u8 clr[0x1]; 10446 u8 reserved_at_21[0x1f]; 10447 10448 union mlx5_ifc_pcie_cntrs_grp_data_layout_auto_bits counter_set; 10449 }; 10450 10451 struct mlx5_ifc_ppad_reg_bits { 10452 u8 reserved_at_0[0x3]; 10453 u8 single_mac[0x1]; 10454 u8 reserved_at_4[0x4]; 10455 u8 local_port[0x8]; 10456 u8 mac_47_32[0x10]; 10457 10458 u8 mac_31_0[0x20]; 10459 10460 u8 reserved_at_40[0x40]; 10461 }; 10462 10463 struct mlx5_ifc_pmtu_reg_bits { 10464 u8 reserved_at_0[0x8]; 10465 u8 local_port[0x8]; 10466 u8 reserved_at_10[0x10]; 10467 10468 u8 max_mtu[0x10]; 10469 u8 reserved_at_30[0x10]; 10470 10471 u8 admin_mtu[0x10]; 10472 u8 reserved_at_50[0x10]; 10473 10474 u8 oper_mtu[0x10]; 10475 u8 reserved_at_70[0x10]; 10476 }; 10477 10478 struct mlx5_ifc_pmpr_reg_bits { 10479 u8 reserved_at_0[0x8]; 10480 u8 module[0x8]; 10481 u8 reserved_at_10[0x10]; 10482 10483 u8 reserved_at_20[0x18]; 10484 u8 attenuation_5g[0x8]; 10485 10486 u8 reserved_at_40[0x18]; 10487 u8 attenuation_7g[0x8]; 10488 10489 u8 reserved_at_60[0x18]; 10490 u8 attenuation_12g[0x8]; 10491 }; 10492 10493 struct mlx5_ifc_pmpe_reg_bits { 10494 u8 reserved_at_0[0x8]; 10495 u8 module[0x8]; 10496 u8 reserved_at_10[0xc]; 10497 u8 module_status[0x4]; 10498 10499 u8 reserved_at_20[0x60]; 10500 }; 10501 10502 struct mlx5_ifc_pmpc_reg_bits { 10503 u8 module_state_updated[32][0x8]; 10504 }; 10505 10506 struct mlx5_ifc_pmlpn_reg_bits { 10507 u8 reserved_at_0[0x4]; 10508 u8 mlpn_status[0x4]; 10509 u8 local_port[0x8]; 10510 u8 reserved_at_10[0x10]; 10511 10512 u8 e[0x1]; 10513 u8 reserved_at_21[0x1f]; 10514 }; 10515 10516 struct mlx5_ifc_pmlp_reg_bits { 10517 u8 rxtx[0x1]; 10518 u8 reserved_at_1[0x7]; 10519 u8 local_port[0x8]; 10520 u8 reserved_at_10[0x8]; 10521 u8 width[0x8]; 10522 10523 u8 lane0_module_mapping[0x20]; 10524 10525 u8 lane1_module_mapping[0x20]; 10526 10527 u8 lane2_module_mapping[0x20]; 10528 10529 u8 lane3_module_mapping[0x20]; 10530 10531 u8 reserved_at_a0[0x160]; 10532 }; 10533 10534 struct mlx5_ifc_pmaos_reg_bits { 10535 u8 reserved_at_0[0x8]; 10536 u8 module[0x8]; 10537 u8 reserved_at_10[0x4]; 10538 u8 admin_status[0x4]; 10539 u8 reserved_at_18[0x4]; 10540 u8 oper_status[0x4]; 10541 10542 u8 ase[0x1]; 10543 u8 ee[0x1]; 10544 u8 reserved_at_22[0x1c]; 10545 u8 e[0x2]; 10546 10547 u8 reserved_at_40[0x40]; 10548 }; 10549 10550 struct mlx5_ifc_plpc_reg_bits { 10551 u8 reserved_at_0[0x4]; 10552 u8 profile_id[0xc]; 10553 u8 reserved_at_10[0x4]; 10554 u8 proto_mask[0x4]; 10555 u8 reserved_at_18[0x8]; 10556 10557 u8 reserved_at_20[0x10]; 10558 u8 lane_speed[0x10]; 10559 10560 u8 reserved_at_40[0x17]; 10561 u8 lpbf[0x1]; 10562 u8 fec_mode_policy[0x8]; 10563 10564 u8 retransmission_capability[0x8]; 10565 u8 fec_mode_capability[0x18]; 10566 10567 u8 retransmission_support_admin[0x8]; 10568 u8 fec_mode_support_admin[0x18]; 10569 10570 u8 retransmission_request_admin[0x8]; 10571 u8 fec_mode_request_admin[0x18]; 10572 10573 u8 reserved_at_c0[0x80]; 10574 }; 10575 10576 struct mlx5_ifc_plib_reg_bits { 10577 u8 reserved_at_0[0x8]; 10578 u8 local_port[0x8]; 10579 u8 reserved_at_10[0x8]; 10580 u8 ib_port[0x8]; 10581 10582 u8 reserved_at_20[0x60]; 10583 }; 10584 10585 struct mlx5_ifc_plbf_reg_bits { 10586 u8 reserved_at_0[0x8]; 10587 u8 local_port[0x8]; 10588 u8 reserved_at_10[0xd]; 10589 u8 lbf_mode[0x3]; 10590 10591 u8 reserved_at_20[0x20]; 10592 }; 10593 10594 struct mlx5_ifc_pipg_reg_bits { 10595 u8 reserved_at_0[0x8]; 10596 u8 local_port[0x8]; 10597 u8 reserved_at_10[0x10]; 10598 10599 u8 dic[0x1]; 10600 u8 reserved_at_21[0x19]; 10601 u8 ipg[0x4]; 10602 u8 reserved_at_3e[0x2]; 10603 }; 10604 10605 struct mlx5_ifc_pifr_reg_bits { 10606 u8 reserved_at_0[0x8]; 10607 u8 local_port[0x8]; 10608 u8 reserved_at_10[0x10]; 10609 10610 u8 reserved_at_20[0xe0]; 10611 10612 u8 port_filter[8][0x20]; 10613 10614 u8 port_filter_update_en[8][0x20]; 10615 }; 10616 10617 enum { 10618 MLX5_BUF_OWNERSHIP_UNKNOWN = 0x0, 10619 MLX5_BUF_OWNERSHIP_FW_OWNED = 0x1, 10620 MLX5_BUF_OWNERSHIP_SW_OWNED = 0x2, 10621 }; 10622 10623 struct mlx5_ifc_pfcc_reg_bits { 10624 u8 reserved_at_0[0x4]; 10625 u8 buf_ownership[0x2]; 10626 u8 reserved_at_6[0x2]; 10627 u8 local_port[0x8]; 10628 u8 reserved_at_10[0xa]; 10629 u8 cable_length_mask[0x1]; 10630 u8 ppan_mask_n[0x1]; 10631 u8 minor_stall_mask[0x1]; 10632 u8 critical_stall_mask[0x1]; 10633 u8 reserved_at_1e[0x2]; 10634 10635 u8 ppan[0x4]; 10636 u8 reserved_at_24[0x4]; 10637 u8 prio_mask_tx[0x8]; 10638 u8 reserved_at_30[0x8]; 10639 u8 prio_mask_rx[0x8]; 10640 10641 u8 pptx[0x1]; 10642 u8 aptx[0x1]; 10643 u8 pptx_mask_n[0x1]; 10644 u8 reserved_at_43[0x5]; 10645 u8 pfctx[0x8]; 10646 u8 reserved_at_50[0x10]; 10647 10648 u8 pprx[0x1]; 10649 u8 aprx[0x1]; 10650 u8 pprx_mask_n[0x1]; 10651 u8 reserved_at_63[0x5]; 10652 u8 pfcrx[0x8]; 10653 u8 reserved_at_70[0x10]; 10654 10655 u8 device_stall_minor_watermark[0x10]; 10656 u8 device_stall_critical_watermark[0x10]; 10657 10658 u8 reserved_at_a0[0x18]; 10659 u8 cable_length[0x8]; 10660 10661 u8 reserved_at_c0[0x40]; 10662 }; 10663 10664 struct mlx5_ifc_pelc_reg_bits { 10665 u8 op[0x4]; 10666 u8 reserved_at_4[0x4]; 10667 u8 local_port[0x8]; 10668 u8 reserved_at_10[0x10]; 10669 10670 u8 op_admin[0x8]; 10671 u8 op_capability[0x8]; 10672 u8 op_request[0x8]; 10673 u8 op_active[0x8]; 10674 10675 u8 admin[0x40]; 10676 10677 u8 capability[0x40]; 10678 10679 u8 request[0x40]; 10680 10681 u8 active[0x40]; 10682 10683 u8 reserved_at_140[0x80]; 10684 }; 10685 10686 struct mlx5_ifc_peir_reg_bits { 10687 u8 reserved_at_0[0x8]; 10688 u8 local_port[0x8]; 10689 u8 reserved_at_10[0x10]; 10690 10691 u8 reserved_at_20[0xc]; 10692 u8 error_count[0x4]; 10693 u8 reserved_at_30[0x10]; 10694 10695 u8 reserved_at_40[0xc]; 10696 u8 lane[0x4]; 10697 u8 reserved_at_50[0x8]; 10698 u8 error_type[0x8]; 10699 }; 10700 10701 struct mlx5_ifc_mpegc_reg_bits { 10702 u8 reserved_at_0[0x30]; 10703 u8 field_select[0x10]; 10704 10705 u8 tx_overflow_sense[0x1]; 10706 u8 mark_cqe[0x1]; 10707 u8 mark_cnp[0x1]; 10708 u8 reserved_at_43[0x1b]; 10709 u8 tx_lossy_overflow_oper[0x2]; 10710 10711 u8 reserved_at_60[0x100]; 10712 }; 10713 10714 struct mlx5_ifc_mpir_reg_bits { 10715 u8 sdm[0x1]; 10716 u8 reserved_at_1[0x1b]; 10717 u8 host_buses[0x4]; 10718 10719 u8 reserved_at_20[0x20]; 10720 10721 u8 local_port[0x8]; 10722 u8 reserved_at_28[0x18]; 10723 10724 u8 reserved_at_60[0x20]; 10725 }; 10726 10727 enum { 10728 MLX5_MTUTC_FREQ_ADJ_UNITS_PPB = 0x0, 10729 MLX5_MTUTC_FREQ_ADJ_UNITS_SCALED_PPM = 0x1, 10730 }; 10731 10732 enum { 10733 MLX5_MTUTC_OPERATION_SET_TIME_IMMEDIATE = 0x1, 10734 MLX5_MTUTC_OPERATION_ADJUST_TIME = 0x2, 10735 MLX5_MTUTC_OPERATION_ADJUST_FREQ_UTC = 0x3, 10736 }; 10737 10738 struct mlx5_ifc_mtutc_reg_bits { 10739 u8 reserved_at_0[0x5]; 10740 u8 freq_adj_units[0x3]; 10741 u8 reserved_at_8[0x3]; 10742 u8 log_max_freq_adjustment[0x5]; 10743 10744 u8 reserved_at_10[0xc]; 10745 u8 operation[0x4]; 10746 10747 u8 freq_adjustment[0x20]; 10748 10749 u8 reserved_at_40[0x40]; 10750 10751 u8 utc_sec[0x20]; 10752 10753 u8 reserved_at_a0[0x2]; 10754 u8 utc_nsec[0x1e]; 10755 10756 u8 time_adjustment[0x20]; 10757 }; 10758 10759 struct mlx5_ifc_pcam_enhanced_features_bits { 10760 u8 reserved_at_0[0x10]; 10761 u8 ppcnt_recovery_counters[0x1]; 10762 u8 reserved_at_11[0x7]; 10763 u8 cable_length[0x1]; 10764 u8 reserved_at_19[0x4]; 10765 u8 fec_200G_per_lane_in_pplm[0x1]; 10766 u8 reserved_at_1e[0x2a]; 10767 u8 fec_100G_per_lane_in_pplm[0x1]; 10768 u8 reserved_at_49[0xa]; 10769 u8 buffer_ownership[0x1]; 10770 u8 resereved_at_54[0x14]; 10771 u8 fec_50G_per_lane_in_pplm[0x1]; 10772 u8 reserved_at_69[0x4]; 10773 u8 rx_icrc_encapsulated_counter[0x1]; 10774 u8 reserved_at_6e[0x4]; 10775 u8 ptys_extended_ethernet[0x1]; 10776 u8 reserved_at_73[0x3]; 10777 u8 pfcc_mask[0x1]; 10778 u8 reserved_at_77[0x3]; 10779 u8 per_lane_error_counters[0x1]; 10780 u8 rx_buffer_fullness_counters[0x1]; 10781 u8 ptys_connector_type[0x1]; 10782 u8 reserved_at_7d[0x1]; 10783 u8 ppcnt_discard_group[0x1]; 10784 u8 ppcnt_statistical_group[0x1]; 10785 }; 10786 10787 struct mlx5_ifc_pcam_regs_5000_to_507f_bits { 10788 u8 port_access_reg_cap_mask_127_to_96[0x20]; 10789 u8 port_access_reg_cap_mask_95_to_64[0x20]; 10790 10791 u8 port_access_reg_cap_mask_63_to_36[0x1c]; 10792 u8 pplm[0x1]; 10793 u8 port_access_reg_cap_mask_34_to_32[0x3]; 10794 10795 u8 port_access_reg_cap_mask_31_to_13[0x13]; 10796 u8 pbmc[0x1]; 10797 u8 pptb[0x1]; 10798 u8 port_access_reg_cap_mask_10_to_09[0x2]; 10799 u8 ppcnt[0x1]; 10800 u8 port_access_reg_cap_mask_07_to_00[0x8]; 10801 }; 10802 10803 struct mlx5_ifc_pcam_reg_bits { 10804 u8 reserved_at_0[0x8]; 10805 u8 feature_group[0x8]; 10806 u8 reserved_at_10[0x8]; 10807 u8 access_reg_group[0x8]; 10808 10809 u8 reserved_at_20[0x20]; 10810 10811 union { 10812 struct mlx5_ifc_pcam_regs_5000_to_507f_bits regs_5000_to_507f; 10813 u8 reserved_at_0[0x80]; 10814 } port_access_reg_cap_mask; 10815 10816 u8 reserved_at_c0[0x80]; 10817 10818 union { 10819 struct mlx5_ifc_pcam_enhanced_features_bits enhanced_features; 10820 u8 reserved_at_0[0x80]; 10821 } feature_cap_mask; 10822 10823 u8 reserved_at_1c0[0xc0]; 10824 }; 10825 10826 struct mlx5_ifc_mcam_enhanced_features_bits { 10827 u8 reserved_at_0[0x50]; 10828 u8 mtutc_freq_adj_units[0x1]; 10829 u8 mtutc_time_adjustment_extended_range[0x1]; 10830 u8 reserved_at_52[0xb]; 10831 u8 mcia_32dwords[0x1]; 10832 u8 out_pulse_duration_ns[0x1]; 10833 u8 npps_period[0x1]; 10834 u8 reserved_at_60[0xa]; 10835 u8 reset_state[0x1]; 10836 u8 ptpcyc2realtime_modify[0x1]; 10837 u8 reserved_at_6c[0x2]; 10838 u8 pci_status_and_power[0x1]; 10839 u8 reserved_at_6f[0x5]; 10840 u8 mark_tx_action_cnp[0x1]; 10841 u8 mark_tx_action_cqe[0x1]; 10842 u8 dynamic_tx_overflow[0x1]; 10843 u8 reserved_at_77[0x4]; 10844 u8 pcie_outbound_stalled[0x1]; 10845 u8 tx_overflow_buffer_pkt[0x1]; 10846 u8 mtpps_enh_out_per_adj[0x1]; 10847 u8 mtpps_fs[0x1]; 10848 u8 pcie_performance_group[0x1]; 10849 }; 10850 10851 struct mlx5_ifc_mcam_access_reg_bits { 10852 u8 reserved_at_0[0x1c]; 10853 u8 mcda[0x1]; 10854 u8 mcc[0x1]; 10855 u8 mcqi[0x1]; 10856 u8 mcqs[0x1]; 10857 10858 u8 regs_95_to_90[0x6]; 10859 u8 mpir[0x1]; 10860 u8 regs_88_to_87[0x2]; 10861 u8 mpegc[0x1]; 10862 u8 mtutc[0x1]; 10863 u8 regs_84_to_68[0x11]; 10864 u8 tracer_registers[0x4]; 10865 10866 u8 regs_63_to_46[0x12]; 10867 u8 mrtc[0x1]; 10868 u8 regs_44_to_41[0x4]; 10869 u8 mfrl[0x1]; 10870 u8 regs_39_to_32[0x8]; 10871 10872 u8 regs_31_to_11[0x15]; 10873 u8 mtmp[0x1]; 10874 u8 regs_9_to_0[0xa]; 10875 }; 10876 10877 struct mlx5_ifc_mcam_access_reg_bits1 { 10878 u8 regs_127_to_96[0x20]; 10879 10880 u8 regs_95_to_64[0x20]; 10881 10882 u8 regs_63_to_32[0x20]; 10883 10884 u8 regs_31_to_0[0x20]; 10885 }; 10886 10887 struct mlx5_ifc_mcam_access_reg_bits2 { 10888 u8 regs_127_to_99[0x1d]; 10889 u8 mirc[0x1]; 10890 u8 regs_97_to_96[0x2]; 10891 10892 u8 regs_95_to_87[0x09]; 10893 u8 synce_registers[0x2]; 10894 u8 regs_84_to_64[0x15]; 10895 10896 u8 regs_63_to_32[0x20]; 10897 10898 u8 regs_31_to_0[0x20]; 10899 }; 10900 10901 struct mlx5_ifc_mcam_access_reg_bits3 { 10902 u8 regs_127_to_96[0x20]; 10903 10904 u8 regs_95_to_64[0x20]; 10905 10906 u8 regs_63_to_32[0x20]; 10907 10908 u8 regs_31_to_3[0x1d]; 10909 u8 mrtcq[0x1]; 10910 u8 mtctr[0x1]; 10911 u8 mtptm[0x1]; 10912 }; 10913 10914 struct mlx5_ifc_mcam_reg_bits { 10915 u8 reserved_at_0[0x8]; 10916 u8 feature_group[0x8]; 10917 u8 reserved_at_10[0x8]; 10918 u8 access_reg_group[0x8]; 10919 10920 u8 reserved_at_20[0x20]; 10921 10922 union { 10923 struct mlx5_ifc_mcam_access_reg_bits access_regs; 10924 struct mlx5_ifc_mcam_access_reg_bits1 access_regs1; 10925 struct mlx5_ifc_mcam_access_reg_bits2 access_regs2; 10926 struct mlx5_ifc_mcam_access_reg_bits3 access_regs3; 10927 u8 reserved_at_0[0x80]; 10928 } mng_access_reg_cap_mask; 10929 10930 u8 reserved_at_c0[0x80]; 10931 10932 union { 10933 struct mlx5_ifc_mcam_enhanced_features_bits enhanced_features; 10934 u8 reserved_at_0[0x80]; 10935 } mng_feature_cap_mask; 10936 10937 u8 reserved_at_1c0[0x80]; 10938 }; 10939 10940 struct mlx5_ifc_qcam_access_reg_cap_mask { 10941 u8 qcam_access_reg_cap_mask_127_to_20[0x6C]; 10942 u8 qpdpm[0x1]; 10943 u8 qcam_access_reg_cap_mask_18_to_4[0x0F]; 10944 u8 qdpm[0x1]; 10945 u8 qpts[0x1]; 10946 u8 qcap[0x1]; 10947 u8 qcam_access_reg_cap_mask_0[0x1]; 10948 }; 10949 10950 struct mlx5_ifc_qcam_qos_feature_cap_mask { 10951 u8 qcam_qos_feature_cap_mask_127_to_1[0x7F]; 10952 u8 qpts_trust_both[0x1]; 10953 }; 10954 10955 struct mlx5_ifc_qcam_reg_bits { 10956 u8 reserved_at_0[0x8]; 10957 u8 feature_group[0x8]; 10958 u8 reserved_at_10[0x8]; 10959 u8 access_reg_group[0x8]; 10960 u8 reserved_at_20[0x20]; 10961 10962 union { 10963 struct mlx5_ifc_qcam_access_reg_cap_mask reg_cap; 10964 u8 reserved_at_0[0x80]; 10965 } qos_access_reg_cap_mask; 10966 10967 u8 reserved_at_c0[0x80]; 10968 10969 union { 10970 struct mlx5_ifc_qcam_qos_feature_cap_mask feature_cap; 10971 u8 reserved_at_0[0x80]; 10972 } qos_feature_cap_mask; 10973 10974 u8 reserved_at_1c0[0x80]; 10975 }; 10976 10977 struct mlx5_ifc_core_dump_reg_bits { 10978 u8 reserved_at_0[0x18]; 10979 u8 core_dump_type[0x8]; 10980 10981 u8 reserved_at_20[0x30]; 10982 u8 vhca_id[0x10]; 10983 10984 u8 reserved_at_60[0x8]; 10985 u8 qpn[0x18]; 10986 u8 reserved_at_80[0x180]; 10987 }; 10988 10989 struct mlx5_ifc_pcap_reg_bits { 10990 u8 reserved_at_0[0x8]; 10991 u8 local_port[0x8]; 10992 u8 reserved_at_10[0x10]; 10993 10994 u8 port_capability_mask[4][0x20]; 10995 }; 10996 10997 struct mlx5_ifc_paos_reg_bits { 10998 u8 swid[0x8]; 10999 u8 local_port[0x8]; 11000 u8 reserved_at_10[0x4]; 11001 u8 admin_status[0x4]; 11002 u8 reserved_at_18[0x4]; 11003 u8 oper_status[0x4]; 11004 11005 u8 ase[0x1]; 11006 u8 ee[0x1]; 11007 u8 reserved_at_22[0x1c]; 11008 u8 e[0x2]; 11009 11010 u8 reserved_at_40[0x40]; 11011 }; 11012 11013 struct mlx5_ifc_pamp_reg_bits { 11014 u8 reserved_at_0[0x8]; 11015 u8 opamp_group[0x8]; 11016 u8 reserved_at_10[0xc]; 11017 u8 opamp_group_type[0x4]; 11018 11019 u8 start_index[0x10]; 11020 u8 reserved_at_30[0x4]; 11021 u8 num_of_indices[0xc]; 11022 11023 u8 index_data[18][0x10]; 11024 }; 11025 11026 struct mlx5_ifc_pcmr_reg_bits { 11027 u8 reserved_at_0[0x8]; 11028 u8 local_port[0x8]; 11029 u8 reserved_at_10[0x10]; 11030 11031 u8 entropy_force_cap[0x1]; 11032 u8 entropy_calc_cap[0x1]; 11033 u8 entropy_gre_calc_cap[0x1]; 11034 u8 reserved_at_23[0xf]; 11035 u8 rx_ts_over_crc_cap[0x1]; 11036 u8 reserved_at_33[0xb]; 11037 u8 fcs_cap[0x1]; 11038 u8 reserved_at_3f[0x1]; 11039 11040 u8 entropy_force[0x1]; 11041 u8 entropy_calc[0x1]; 11042 u8 entropy_gre_calc[0x1]; 11043 u8 reserved_at_43[0xf]; 11044 u8 rx_ts_over_crc[0x1]; 11045 u8 reserved_at_53[0xb]; 11046 u8 fcs_chk[0x1]; 11047 u8 reserved_at_5f[0x1]; 11048 }; 11049 11050 struct mlx5_ifc_lane_2_module_mapping_bits { 11051 u8 reserved_at_0[0x4]; 11052 u8 rx_lane[0x4]; 11053 u8 reserved_at_8[0x4]; 11054 u8 tx_lane[0x4]; 11055 u8 reserved_at_10[0x8]; 11056 u8 module[0x8]; 11057 }; 11058 11059 struct mlx5_ifc_bufferx_reg_bits { 11060 u8 reserved_at_0[0x6]; 11061 u8 lossy[0x1]; 11062 u8 epsb[0x1]; 11063 u8 reserved_at_8[0x8]; 11064 u8 size[0x10]; 11065 11066 u8 xoff_threshold[0x10]; 11067 u8 xon_threshold[0x10]; 11068 }; 11069 11070 struct mlx5_ifc_set_node_in_bits { 11071 u8 node_description[64][0x8]; 11072 }; 11073 11074 struct mlx5_ifc_register_power_settings_bits { 11075 u8 reserved_at_0[0x18]; 11076 u8 power_settings_level[0x8]; 11077 11078 u8 reserved_at_20[0x60]; 11079 }; 11080 11081 struct mlx5_ifc_register_host_endianness_bits { 11082 u8 he[0x1]; 11083 u8 reserved_at_1[0x1f]; 11084 11085 u8 reserved_at_20[0x60]; 11086 }; 11087 11088 struct mlx5_ifc_umr_pointer_desc_argument_bits { 11089 u8 reserved_at_0[0x20]; 11090 11091 u8 mkey[0x20]; 11092 11093 u8 addressh_63_32[0x20]; 11094 11095 u8 addressl_31_0[0x20]; 11096 }; 11097 11098 struct mlx5_ifc_ud_adrs_vector_bits { 11099 u8 dc_key[0x40]; 11100 11101 u8 ext[0x1]; 11102 u8 reserved_at_41[0x7]; 11103 u8 destination_qp_dct[0x18]; 11104 11105 u8 static_rate[0x4]; 11106 u8 sl_eth_prio[0x4]; 11107 u8 fl[0x1]; 11108 u8 mlid[0x7]; 11109 u8 rlid_udp_sport[0x10]; 11110 11111 u8 reserved_at_80[0x20]; 11112 11113 u8 rmac_47_16[0x20]; 11114 11115 u8 rmac_15_0[0x10]; 11116 u8 tclass[0x8]; 11117 u8 hop_limit[0x8]; 11118 11119 u8 reserved_at_e0[0x1]; 11120 u8 grh[0x1]; 11121 u8 reserved_at_e2[0x2]; 11122 u8 src_addr_index[0x8]; 11123 u8 flow_label[0x14]; 11124 11125 u8 rgid_rip[16][0x8]; 11126 }; 11127 11128 struct mlx5_ifc_pages_req_event_bits { 11129 u8 reserved_at_0[0x10]; 11130 u8 function_id[0x10]; 11131 11132 u8 num_pages[0x20]; 11133 11134 u8 reserved_at_40[0xa0]; 11135 }; 11136 11137 struct mlx5_ifc_eqe_bits { 11138 u8 reserved_at_0[0x8]; 11139 u8 event_type[0x8]; 11140 u8 reserved_at_10[0x8]; 11141 u8 event_sub_type[0x8]; 11142 11143 u8 reserved_at_20[0xe0]; 11144 11145 union mlx5_ifc_event_auto_bits event_data; 11146 11147 u8 reserved_at_1e0[0x10]; 11148 u8 signature[0x8]; 11149 u8 reserved_at_1f8[0x7]; 11150 u8 owner[0x1]; 11151 }; 11152 11153 enum { 11154 MLX5_CMD_QUEUE_ENTRY_TYPE_PCIE_CMD_IF_TRANSPORT = 0x7, 11155 }; 11156 11157 struct mlx5_ifc_cmd_queue_entry_bits { 11158 u8 type[0x8]; 11159 u8 reserved_at_8[0x18]; 11160 11161 u8 input_length[0x20]; 11162 11163 u8 input_mailbox_pointer_63_32[0x20]; 11164 11165 u8 input_mailbox_pointer_31_9[0x17]; 11166 u8 reserved_at_77[0x9]; 11167 11168 u8 command_input_inline_data[16][0x8]; 11169 11170 u8 command_output_inline_data[16][0x8]; 11171 11172 u8 output_mailbox_pointer_63_32[0x20]; 11173 11174 u8 output_mailbox_pointer_31_9[0x17]; 11175 u8 reserved_at_1b7[0x9]; 11176 11177 u8 output_length[0x20]; 11178 11179 u8 token[0x8]; 11180 u8 signature[0x8]; 11181 u8 reserved_at_1f0[0x8]; 11182 u8 status[0x7]; 11183 u8 ownership[0x1]; 11184 }; 11185 11186 struct mlx5_ifc_cmd_out_bits { 11187 u8 status[0x8]; 11188 u8 reserved_at_8[0x18]; 11189 11190 u8 syndrome[0x20]; 11191 11192 u8 command_output[0x20]; 11193 }; 11194 11195 struct mlx5_ifc_cmd_in_bits { 11196 u8 opcode[0x10]; 11197 u8 reserved_at_10[0x10]; 11198 11199 u8 reserved_at_20[0x10]; 11200 u8 op_mod[0x10]; 11201 11202 u8 command[][0x20]; 11203 }; 11204 11205 struct mlx5_ifc_cmd_if_box_bits { 11206 u8 mailbox_data[512][0x8]; 11207 11208 u8 reserved_at_1000[0x180]; 11209 11210 u8 next_pointer_63_32[0x20]; 11211 11212 u8 next_pointer_31_10[0x16]; 11213 u8 reserved_at_11b6[0xa]; 11214 11215 u8 block_number[0x20]; 11216 11217 u8 reserved_at_11e0[0x8]; 11218 u8 token[0x8]; 11219 u8 ctrl_signature[0x8]; 11220 u8 signature[0x8]; 11221 }; 11222 11223 struct mlx5_ifc_mtt_bits { 11224 u8 ptag_63_32[0x20]; 11225 11226 u8 ptag_31_8[0x18]; 11227 u8 reserved_at_38[0x6]; 11228 u8 wr_en[0x1]; 11229 u8 rd_en[0x1]; 11230 }; 11231 11232 struct mlx5_ifc_query_wol_rol_out_bits { 11233 u8 status[0x8]; 11234 u8 reserved_at_8[0x18]; 11235 11236 u8 syndrome[0x20]; 11237 11238 u8 reserved_at_40[0x10]; 11239 u8 rol_mode[0x8]; 11240 u8 wol_mode[0x8]; 11241 11242 u8 reserved_at_60[0x20]; 11243 }; 11244 11245 struct mlx5_ifc_query_wol_rol_in_bits { 11246 u8 opcode[0x10]; 11247 u8 reserved_at_10[0x10]; 11248 11249 u8 reserved_at_20[0x10]; 11250 u8 op_mod[0x10]; 11251 11252 u8 reserved_at_40[0x40]; 11253 }; 11254 11255 struct mlx5_ifc_set_wol_rol_out_bits { 11256 u8 status[0x8]; 11257 u8 reserved_at_8[0x18]; 11258 11259 u8 syndrome[0x20]; 11260 11261 u8 reserved_at_40[0x40]; 11262 }; 11263 11264 struct mlx5_ifc_set_wol_rol_in_bits { 11265 u8 opcode[0x10]; 11266 u8 reserved_at_10[0x10]; 11267 11268 u8 reserved_at_20[0x10]; 11269 u8 op_mod[0x10]; 11270 11271 u8 rol_mode_valid[0x1]; 11272 u8 wol_mode_valid[0x1]; 11273 u8 reserved_at_42[0xe]; 11274 u8 rol_mode[0x8]; 11275 u8 wol_mode[0x8]; 11276 11277 u8 reserved_at_60[0x20]; 11278 }; 11279 11280 enum { 11281 MLX5_INITIAL_SEG_NIC_INTERFACE_FULL_DRIVER = 0x0, 11282 MLX5_INITIAL_SEG_NIC_INTERFACE_DISABLED = 0x1, 11283 MLX5_INITIAL_SEG_NIC_INTERFACE_NO_DRAM_NIC = 0x2, 11284 MLX5_INITIAL_SEG_NIC_INTERFACE_SW_RESET = 0x7, 11285 }; 11286 11287 enum { 11288 MLX5_INITIAL_SEG_NIC_INTERFACE_SUPPORTED_FULL_DRIVER = 0x0, 11289 MLX5_INITIAL_SEG_NIC_INTERFACE_SUPPORTED_DISABLED = 0x1, 11290 MLX5_INITIAL_SEG_NIC_INTERFACE_SUPPORTED_NO_DRAM_NIC = 0x2, 11291 }; 11292 11293 enum { 11294 MLX5_INITIAL_SEG_HEALTH_SYNDROME_FW_INTERNAL_ERR = 0x1, 11295 MLX5_INITIAL_SEG_HEALTH_SYNDROME_DEAD_IRISC = 0x7, 11296 MLX5_INITIAL_SEG_HEALTH_SYNDROME_HW_FATAL_ERR = 0x8, 11297 MLX5_INITIAL_SEG_HEALTH_SYNDROME_FW_CRC_ERR = 0x9, 11298 MLX5_INITIAL_SEG_HEALTH_SYNDROME_ICM_FETCH_PCI_ERR = 0xa, 11299 MLX5_INITIAL_SEG_HEALTH_SYNDROME_ICM_PAGE_ERR = 0xb, 11300 MLX5_INITIAL_SEG_HEALTH_SYNDROME_ASYNCHRONOUS_EQ_BUF_OVERRUN = 0xc, 11301 MLX5_INITIAL_SEG_HEALTH_SYNDROME_EQ_IN_ERR = 0xd, 11302 MLX5_INITIAL_SEG_HEALTH_SYNDROME_EQ_INV = 0xe, 11303 MLX5_INITIAL_SEG_HEALTH_SYNDROME_FFSER_ERR = 0xf, 11304 MLX5_INITIAL_SEG_HEALTH_SYNDROME_HIGH_TEMP_ERR = 0x10, 11305 MLX5_INITIAL_SEG_HEALTH_SYNDROME_ICM_PCI_POISONED_ERR = 0x12, 11306 MLX5_INITIAL_SEG_HEALTH_SYNDROME_TRUST_LOCKDOWN_ERR = 0x13, 11307 }; 11308 11309 struct mlx5_ifc_initial_seg_bits { 11310 u8 fw_rev_minor[0x10]; 11311 u8 fw_rev_major[0x10]; 11312 11313 u8 cmd_interface_rev[0x10]; 11314 u8 fw_rev_subminor[0x10]; 11315 11316 u8 reserved_at_40[0x40]; 11317 11318 u8 cmdq_phy_addr_63_32[0x20]; 11319 11320 u8 cmdq_phy_addr_31_12[0x14]; 11321 u8 reserved_at_b4[0x2]; 11322 u8 nic_interface[0x2]; 11323 u8 log_cmdq_size[0x4]; 11324 u8 log_cmdq_stride[0x4]; 11325 11326 u8 command_doorbell_vector[0x20]; 11327 11328 u8 reserved_at_e0[0xf00]; 11329 11330 u8 initializing[0x1]; 11331 u8 reserved_at_fe1[0x4]; 11332 u8 nic_interface_supported[0x3]; 11333 u8 embedded_cpu[0x1]; 11334 u8 reserved_at_fe9[0x17]; 11335 11336 struct mlx5_ifc_health_buffer_bits health_buffer; 11337 11338 u8 no_dram_nic_offset[0x20]; 11339 11340 u8 reserved_at_1220[0x6e40]; 11341 11342 u8 reserved_at_8060[0x1f]; 11343 u8 clear_int[0x1]; 11344 11345 u8 health_syndrome[0x8]; 11346 u8 health_counter[0x18]; 11347 11348 u8 reserved_at_80a0[0x17fc0]; 11349 }; 11350 11351 struct mlx5_ifc_mtpps_reg_bits { 11352 u8 reserved_at_0[0xc]; 11353 u8 cap_number_of_pps_pins[0x4]; 11354 u8 reserved_at_10[0x4]; 11355 u8 cap_max_num_of_pps_in_pins[0x4]; 11356 u8 reserved_at_18[0x4]; 11357 u8 cap_max_num_of_pps_out_pins[0x4]; 11358 11359 u8 reserved_at_20[0x13]; 11360 u8 cap_log_min_npps_period[0x5]; 11361 u8 reserved_at_38[0x3]; 11362 u8 cap_log_min_out_pulse_duration_ns[0x5]; 11363 11364 u8 reserved_at_40[0x4]; 11365 u8 cap_pin_3_mode[0x4]; 11366 u8 reserved_at_48[0x4]; 11367 u8 cap_pin_2_mode[0x4]; 11368 u8 reserved_at_50[0x4]; 11369 u8 cap_pin_1_mode[0x4]; 11370 u8 reserved_at_58[0x4]; 11371 u8 cap_pin_0_mode[0x4]; 11372 11373 u8 reserved_at_60[0x4]; 11374 u8 cap_pin_7_mode[0x4]; 11375 u8 reserved_at_68[0x4]; 11376 u8 cap_pin_6_mode[0x4]; 11377 u8 reserved_at_70[0x4]; 11378 u8 cap_pin_5_mode[0x4]; 11379 u8 reserved_at_78[0x4]; 11380 u8 cap_pin_4_mode[0x4]; 11381 11382 u8 field_select[0x20]; 11383 u8 reserved_at_a0[0x20]; 11384 11385 u8 npps_period[0x40]; 11386 11387 u8 enable[0x1]; 11388 u8 reserved_at_101[0xb]; 11389 u8 pattern[0x4]; 11390 u8 reserved_at_110[0x4]; 11391 u8 pin_mode[0x4]; 11392 u8 pin[0x8]; 11393 11394 u8 reserved_at_120[0x2]; 11395 u8 out_pulse_duration_ns[0x1e]; 11396 11397 u8 time_stamp[0x40]; 11398 11399 u8 out_pulse_duration[0x10]; 11400 u8 out_periodic_adjustment[0x10]; 11401 u8 enhanced_out_periodic_adjustment[0x20]; 11402 11403 u8 reserved_at_1c0[0x20]; 11404 }; 11405 11406 struct mlx5_ifc_mtppse_reg_bits { 11407 u8 reserved_at_0[0x18]; 11408 u8 pin[0x8]; 11409 u8 event_arm[0x1]; 11410 u8 reserved_at_21[0x1b]; 11411 u8 event_generation_mode[0x4]; 11412 u8 reserved_at_40[0x40]; 11413 }; 11414 11415 struct mlx5_ifc_mcqs_reg_bits { 11416 u8 last_index_flag[0x1]; 11417 u8 reserved_at_1[0x7]; 11418 u8 fw_device[0x8]; 11419 u8 component_index[0x10]; 11420 11421 u8 reserved_at_20[0x10]; 11422 u8 identifier[0x10]; 11423 11424 u8 reserved_at_40[0x17]; 11425 u8 component_status[0x5]; 11426 u8 component_update_state[0x4]; 11427 11428 u8 last_update_state_changer_type[0x4]; 11429 u8 last_update_state_changer_host_id[0x4]; 11430 u8 reserved_at_68[0x18]; 11431 }; 11432 11433 struct mlx5_ifc_mcqi_cap_bits { 11434 u8 supported_info_bitmask[0x20]; 11435 11436 u8 component_size[0x20]; 11437 11438 u8 max_component_size[0x20]; 11439 11440 u8 log_mcda_word_size[0x4]; 11441 u8 reserved_at_64[0xc]; 11442 u8 mcda_max_write_size[0x10]; 11443 11444 u8 rd_en[0x1]; 11445 u8 reserved_at_81[0x1]; 11446 u8 match_chip_id[0x1]; 11447 u8 match_psid[0x1]; 11448 u8 check_user_timestamp[0x1]; 11449 u8 match_base_guid_mac[0x1]; 11450 u8 reserved_at_86[0x1a]; 11451 }; 11452 11453 struct mlx5_ifc_mcqi_version_bits { 11454 u8 reserved_at_0[0x2]; 11455 u8 build_time_valid[0x1]; 11456 u8 user_defined_time_valid[0x1]; 11457 u8 reserved_at_4[0x14]; 11458 u8 version_string_length[0x8]; 11459 11460 u8 version[0x20]; 11461 11462 u8 build_time[0x40]; 11463 11464 u8 user_defined_time[0x40]; 11465 11466 u8 build_tool_version[0x20]; 11467 11468 u8 reserved_at_e0[0x20]; 11469 11470 u8 version_string[92][0x8]; 11471 }; 11472 11473 struct mlx5_ifc_mcqi_activation_method_bits { 11474 u8 pending_server_ac_power_cycle[0x1]; 11475 u8 pending_server_dc_power_cycle[0x1]; 11476 u8 pending_server_reboot[0x1]; 11477 u8 pending_fw_reset[0x1]; 11478 u8 auto_activate[0x1]; 11479 u8 all_hosts_sync[0x1]; 11480 u8 device_hw_reset[0x1]; 11481 u8 reserved_at_7[0x19]; 11482 }; 11483 11484 union mlx5_ifc_mcqi_reg_data_bits { 11485 struct mlx5_ifc_mcqi_cap_bits mcqi_caps; 11486 struct mlx5_ifc_mcqi_version_bits mcqi_version; 11487 struct mlx5_ifc_mcqi_activation_method_bits mcqi_activation_mathod; 11488 }; 11489 11490 struct mlx5_ifc_mcqi_reg_bits { 11491 u8 read_pending_component[0x1]; 11492 u8 reserved_at_1[0xf]; 11493 u8 component_index[0x10]; 11494 11495 u8 reserved_at_20[0x20]; 11496 11497 u8 reserved_at_40[0x1b]; 11498 u8 info_type[0x5]; 11499 11500 u8 info_size[0x20]; 11501 11502 u8 offset[0x20]; 11503 11504 u8 reserved_at_a0[0x10]; 11505 u8 data_size[0x10]; 11506 11507 union mlx5_ifc_mcqi_reg_data_bits data[]; 11508 }; 11509 11510 struct mlx5_ifc_mcc_reg_bits { 11511 u8 reserved_at_0[0x4]; 11512 u8 time_elapsed_since_last_cmd[0xc]; 11513 u8 reserved_at_10[0x8]; 11514 u8 instruction[0x8]; 11515 11516 u8 reserved_at_20[0x10]; 11517 u8 component_index[0x10]; 11518 11519 u8 reserved_at_40[0x8]; 11520 u8 update_handle[0x18]; 11521 11522 u8 handle_owner_type[0x4]; 11523 u8 handle_owner_host_id[0x4]; 11524 u8 reserved_at_68[0x1]; 11525 u8 control_progress[0x7]; 11526 u8 error_code[0x8]; 11527 u8 reserved_at_78[0x4]; 11528 u8 control_state[0x4]; 11529 11530 u8 component_size[0x20]; 11531 11532 u8 reserved_at_a0[0x60]; 11533 }; 11534 11535 struct mlx5_ifc_mcda_reg_bits { 11536 u8 reserved_at_0[0x8]; 11537 u8 update_handle[0x18]; 11538 11539 u8 offset[0x20]; 11540 11541 u8 reserved_at_40[0x10]; 11542 u8 size[0x10]; 11543 11544 u8 reserved_at_60[0x20]; 11545 11546 u8 data[][0x20]; 11547 }; 11548 11549 enum { 11550 MLX5_MFRL_REG_PCI_RESET_METHOD_LINK_TOGGLE = 0, 11551 MLX5_MFRL_REG_PCI_RESET_METHOD_HOT_RESET = 1, 11552 }; 11553 11554 enum { 11555 MLX5_MFRL_REG_RESET_STATE_IDLE = 0, 11556 MLX5_MFRL_REG_RESET_STATE_IN_NEGOTIATION = 1, 11557 MLX5_MFRL_REG_RESET_STATE_RESET_IN_PROGRESS = 2, 11558 MLX5_MFRL_REG_RESET_STATE_NEG_TIMEOUT = 3, 11559 MLX5_MFRL_REG_RESET_STATE_NACK = 4, 11560 MLX5_MFRL_REG_RESET_STATE_UNLOAD_TIMEOUT = 5, 11561 }; 11562 11563 enum { 11564 MLX5_MFRL_REG_RESET_TYPE_FULL_CHIP = BIT(0), 11565 MLX5_MFRL_REG_RESET_TYPE_NET_PORT_ALIVE = BIT(1), 11566 }; 11567 11568 enum { 11569 MLX5_MFRL_REG_RESET_LEVEL0 = BIT(0), 11570 MLX5_MFRL_REG_RESET_LEVEL3 = BIT(3), 11571 MLX5_MFRL_REG_RESET_LEVEL6 = BIT(6), 11572 }; 11573 11574 struct mlx5_ifc_mfrl_reg_bits { 11575 u8 reserved_at_0[0x20]; 11576 11577 u8 reserved_at_20[0x2]; 11578 u8 pci_sync_for_fw_update_start[0x1]; 11579 u8 pci_sync_for_fw_update_resp[0x2]; 11580 u8 rst_type_sel[0x3]; 11581 u8 pci_reset_req_method[0x3]; 11582 u8 reserved_at_2b[0x1]; 11583 u8 reset_state[0x4]; 11584 u8 reset_type[0x8]; 11585 u8 reset_level[0x8]; 11586 }; 11587 11588 struct mlx5_ifc_mirc_reg_bits { 11589 u8 reserved_at_0[0x18]; 11590 u8 status_code[0x8]; 11591 11592 u8 reserved_at_20[0x20]; 11593 }; 11594 11595 struct mlx5_ifc_pddr_monitor_opcode_bits { 11596 u8 reserved_at_0[0x10]; 11597 u8 monitor_opcode[0x10]; 11598 }; 11599 11600 union mlx5_ifc_pddr_troubleshooting_page_status_opcode_auto_bits { 11601 struct mlx5_ifc_pddr_monitor_opcode_bits pddr_monitor_opcode; 11602 u8 reserved_at_0[0x20]; 11603 }; 11604 11605 enum { 11606 /* Monitor opcodes */ 11607 MLX5_PDDR_REG_TRBLSH_GROUP_OPCODE_MONITOR = 0x0, 11608 }; 11609 11610 struct mlx5_ifc_pddr_troubleshooting_page_bits { 11611 u8 reserved_at_0[0x10]; 11612 u8 group_opcode[0x10]; 11613 11614 union mlx5_ifc_pddr_troubleshooting_page_status_opcode_auto_bits status_opcode; 11615 11616 u8 reserved_at_40[0x20]; 11617 11618 u8 status_message[59][0x20]; 11619 }; 11620 11621 union mlx5_ifc_pddr_reg_page_data_auto_bits { 11622 struct mlx5_ifc_pddr_troubleshooting_page_bits pddr_troubleshooting_page; 11623 u8 reserved_at_0[0x7c0]; 11624 }; 11625 11626 enum { 11627 MLX5_PDDR_REG_PAGE_SELECT_TROUBLESHOOTING_INFO_PAGE = 0x1, 11628 }; 11629 11630 struct mlx5_ifc_pddr_reg_bits { 11631 u8 reserved_at_0[0x8]; 11632 u8 local_port[0x8]; 11633 u8 pnat[0x2]; 11634 u8 reserved_at_12[0xe]; 11635 11636 u8 reserved_at_20[0x18]; 11637 u8 page_select[0x8]; 11638 11639 union mlx5_ifc_pddr_reg_page_data_auto_bits page_data; 11640 }; 11641 11642 struct mlx5_ifc_mrtc_reg_bits { 11643 u8 time_synced[0x1]; 11644 u8 reserved_at_1[0x1f]; 11645 11646 u8 reserved_at_20[0x20]; 11647 11648 u8 time_h[0x20]; 11649 11650 u8 time_l[0x20]; 11651 }; 11652 11653 struct mlx5_ifc_mtcap_reg_bits { 11654 u8 reserved_at_0[0x19]; 11655 u8 sensor_count[0x7]; 11656 11657 u8 reserved_at_20[0x20]; 11658 11659 u8 sensor_map[0x40]; 11660 }; 11661 11662 struct mlx5_ifc_mtmp_reg_bits { 11663 u8 reserved_at_0[0x14]; 11664 u8 sensor_index[0xc]; 11665 11666 u8 reserved_at_20[0x10]; 11667 u8 temperature[0x10]; 11668 11669 u8 mte[0x1]; 11670 u8 mtr[0x1]; 11671 u8 reserved_at_42[0xe]; 11672 u8 max_temperature[0x10]; 11673 11674 u8 tee[0x2]; 11675 u8 reserved_at_62[0xe]; 11676 u8 temp_threshold_hi[0x10]; 11677 11678 u8 reserved_at_80[0x10]; 11679 u8 temp_threshold_lo[0x10]; 11680 11681 u8 reserved_at_a0[0x20]; 11682 11683 u8 sensor_name_hi[0x20]; 11684 u8 sensor_name_lo[0x20]; 11685 }; 11686 11687 struct mlx5_ifc_mtptm_reg_bits { 11688 u8 reserved_at_0[0x10]; 11689 u8 psta[0x1]; 11690 u8 reserved_at_11[0xf]; 11691 11692 u8 reserved_at_20[0x60]; 11693 }; 11694 11695 enum { 11696 MLX5_MTCTR_REQUEST_NOP = 0x0, 11697 MLX5_MTCTR_REQUEST_PTM_ROOT_CLOCK = 0x1, 11698 MLX5_MTCTR_REQUEST_FREE_RUNNING_COUNTER = 0x2, 11699 MLX5_MTCTR_REQUEST_REAL_TIME_CLOCK = 0x3, 11700 }; 11701 11702 struct mlx5_ifc_mtctr_reg_bits { 11703 u8 first_clock_timestamp_request[0x8]; 11704 u8 second_clock_timestamp_request[0x8]; 11705 u8 reserved_at_10[0x10]; 11706 11707 u8 first_clock_valid[0x1]; 11708 u8 second_clock_valid[0x1]; 11709 u8 reserved_at_22[0x1e]; 11710 11711 u8 first_clock_timestamp[0x40]; 11712 u8 second_clock_timestamp[0x40]; 11713 }; 11714 11715 union mlx5_ifc_ports_control_registers_document_bits { 11716 struct mlx5_ifc_bufferx_reg_bits bufferx_reg; 11717 struct mlx5_ifc_eth_2819_cntrs_grp_data_layout_bits eth_2819_cntrs_grp_data_layout; 11718 struct mlx5_ifc_eth_2863_cntrs_grp_data_layout_bits eth_2863_cntrs_grp_data_layout; 11719 struct mlx5_ifc_eth_3635_cntrs_grp_data_layout_bits eth_3635_cntrs_grp_data_layout; 11720 struct mlx5_ifc_eth_802_3_cntrs_grp_data_layout_bits eth_802_3_cntrs_grp_data_layout; 11721 struct mlx5_ifc_eth_extended_cntrs_grp_data_layout_bits eth_extended_cntrs_grp_data_layout; 11722 struct mlx5_ifc_eth_per_prio_grp_data_layout_bits eth_per_prio_grp_data_layout; 11723 struct mlx5_ifc_eth_per_tc_prio_grp_data_layout_bits eth_per_tc_prio_grp_data_layout; 11724 struct mlx5_ifc_eth_per_tc_congest_prio_grp_data_layout_bits eth_per_tc_congest_prio_grp_data_layout; 11725 struct mlx5_ifc_lane_2_module_mapping_bits lane_2_module_mapping; 11726 struct mlx5_ifc_pamp_reg_bits pamp_reg; 11727 struct mlx5_ifc_paos_reg_bits paos_reg; 11728 struct mlx5_ifc_pcap_reg_bits pcap_reg; 11729 struct mlx5_ifc_pddr_monitor_opcode_bits pddr_monitor_opcode; 11730 struct mlx5_ifc_pddr_reg_bits pddr_reg; 11731 struct mlx5_ifc_pddr_troubleshooting_page_bits pddr_troubleshooting_page; 11732 struct mlx5_ifc_peir_reg_bits peir_reg; 11733 struct mlx5_ifc_pelc_reg_bits pelc_reg; 11734 struct mlx5_ifc_pfcc_reg_bits pfcc_reg; 11735 struct mlx5_ifc_ib_port_cntrs_grp_data_layout_bits ib_port_cntrs_grp_data_layout; 11736 struct mlx5_ifc_phys_layer_cntrs_bits phys_layer_cntrs; 11737 struct mlx5_ifc_pifr_reg_bits pifr_reg; 11738 struct mlx5_ifc_pipg_reg_bits pipg_reg; 11739 struct mlx5_ifc_plbf_reg_bits plbf_reg; 11740 struct mlx5_ifc_plib_reg_bits plib_reg; 11741 struct mlx5_ifc_plpc_reg_bits plpc_reg; 11742 struct mlx5_ifc_pmaos_reg_bits pmaos_reg; 11743 struct mlx5_ifc_pmlp_reg_bits pmlp_reg; 11744 struct mlx5_ifc_pmlpn_reg_bits pmlpn_reg; 11745 struct mlx5_ifc_pmpc_reg_bits pmpc_reg; 11746 struct mlx5_ifc_pmpe_reg_bits pmpe_reg; 11747 struct mlx5_ifc_pmpr_reg_bits pmpr_reg; 11748 struct mlx5_ifc_pmtu_reg_bits pmtu_reg; 11749 struct mlx5_ifc_ppad_reg_bits ppad_reg; 11750 struct mlx5_ifc_ppcnt_reg_bits ppcnt_reg; 11751 struct mlx5_ifc_mpein_reg_bits mpein_reg; 11752 struct mlx5_ifc_mpcnt_reg_bits mpcnt_reg; 11753 struct mlx5_ifc_pplm_reg_bits pplm_reg; 11754 struct mlx5_ifc_pplr_reg_bits pplr_reg; 11755 struct mlx5_ifc_ppsc_reg_bits ppsc_reg; 11756 struct mlx5_ifc_pqdr_reg_bits pqdr_reg; 11757 struct mlx5_ifc_pspa_reg_bits pspa_reg; 11758 struct mlx5_ifc_ptas_reg_bits ptas_reg; 11759 struct mlx5_ifc_ptys_reg_bits ptys_reg; 11760 struct mlx5_ifc_mlcr_reg_bits mlcr_reg; 11761 struct mlx5_ifc_pude_reg_bits pude_reg; 11762 struct mlx5_ifc_pvlc_reg_bits pvlc_reg; 11763 struct mlx5_ifc_slrg_reg_bits slrg_reg; 11764 struct mlx5_ifc_sltp_reg_bits sltp_reg; 11765 struct mlx5_ifc_mtpps_reg_bits mtpps_reg; 11766 struct mlx5_ifc_mtppse_reg_bits mtppse_reg; 11767 struct mlx5_ifc_fpga_access_reg_bits fpga_access_reg; 11768 struct mlx5_ifc_fpga_ctrl_bits fpga_ctrl_bits; 11769 struct mlx5_ifc_fpga_cap_bits fpga_cap_bits; 11770 struct mlx5_ifc_mcqi_reg_bits mcqi_reg; 11771 struct mlx5_ifc_mcc_reg_bits mcc_reg; 11772 struct mlx5_ifc_mcda_reg_bits mcda_reg; 11773 struct mlx5_ifc_mirc_reg_bits mirc_reg; 11774 struct mlx5_ifc_mfrl_reg_bits mfrl_reg; 11775 struct mlx5_ifc_mtutc_reg_bits mtutc_reg; 11776 struct mlx5_ifc_mrtc_reg_bits mrtc_reg; 11777 struct mlx5_ifc_mtcap_reg_bits mtcap_reg; 11778 struct mlx5_ifc_mtmp_reg_bits mtmp_reg; 11779 struct mlx5_ifc_mtptm_reg_bits mtptm_reg; 11780 struct mlx5_ifc_mtctr_reg_bits mtctr_reg; 11781 u8 reserved_at_0[0x60e0]; 11782 }; 11783 11784 union mlx5_ifc_debug_enhancements_document_bits { 11785 struct mlx5_ifc_health_buffer_bits health_buffer; 11786 u8 reserved_at_0[0x200]; 11787 }; 11788 11789 union mlx5_ifc_uplink_pci_interface_document_bits { 11790 struct mlx5_ifc_initial_seg_bits initial_seg; 11791 u8 reserved_at_0[0x20060]; 11792 }; 11793 11794 struct mlx5_ifc_set_flow_table_root_out_bits { 11795 u8 status[0x8]; 11796 u8 reserved_at_8[0x18]; 11797 11798 u8 syndrome[0x20]; 11799 11800 u8 reserved_at_40[0x40]; 11801 }; 11802 11803 struct mlx5_ifc_set_flow_table_root_in_bits { 11804 u8 opcode[0x10]; 11805 u8 reserved_at_10[0x10]; 11806 11807 u8 reserved_at_20[0x10]; 11808 u8 op_mod[0x10]; 11809 11810 u8 other_vport[0x1]; 11811 u8 reserved_at_41[0xf]; 11812 u8 vport_number[0x10]; 11813 11814 u8 reserved_at_60[0x20]; 11815 11816 u8 table_type[0x8]; 11817 u8 reserved_at_88[0x7]; 11818 u8 table_of_other_vport[0x1]; 11819 u8 table_vport_number[0x10]; 11820 11821 u8 reserved_at_a0[0x8]; 11822 u8 table_id[0x18]; 11823 11824 u8 reserved_at_c0[0x8]; 11825 u8 underlay_qpn[0x18]; 11826 u8 table_eswitch_owner_vhca_id_valid[0x1]; 11827 u8 reserved_at_e1[0xf]; 11828 u8 table_eswitch_owner_vhca_id[0x10]; 11829 u8 reserved_at_100[0x100]; 11830 }; 11831 11832 enum { 11833 MLX5_MODIFY_FLOW_TABLE_MISS_TABLE_ID = (1UL << 0), 11834 MLX5_MODIFY_FLOW_TABLE_LAG_NEXT_TABLE_ID = (1UL << 15), 11835 }; 11836 11837 struct mlx5_ifc_modify_flow_table_out_bits { 11838 u8 status[0x8]; 11839 u8 reserved_at_8[0x18]; 11840 11841 u8 syndrome[0x20]; 11842 11843 u8 reserved_at_40[0x40]; 11844 }; 11845 11846 struct mlx5_ifc_modify_flow_table_in_bits { 11847 u8 opcode[0x10]; 11848 u8 reserved_at_10[0x10]; 11849 11850 u8 reserved_at_20[0x10]; 11851 u8 op_mod[0x10]; 11852 11853 u8 other_vport[0x1]; 11854 u8 reserved_at_41[0xf]; 11855 u8 vport_number[0x10]; 11856 11857 u8 reserved_at_60[0x10]; 11858 u8 modify_field_select[0x10]; 11859 11860 u8 table_type[0x8]; 11861 u8 reserved_at_88[0x18]; 11862 11863 u8 reserved_at_a0[0x8]; 11864 u8 table_id[0x18]; 11865 11866 struct mlx5_ifc_flow_table_context_bits flow_table_context; 11867 }; 11868 11869 struct mlx5_ifc_ets_tcn_config_reg_bits { 11870 u8 g[0x1]; 11871 u8 b[0x1]; 11872 u8 r[0x1]; 11873 u8 reserved_at_3[0x9]; 11874 u8 group[0x4]; 11875 u8 reserved_at_10[0x9]; 11876 u8 bw_allocation[0x7]; 11877 11878 u8 reserved_at_20[0xc]; 11879 u8 max_bw_units[0x4]; 11880 u8 reserved_at_30[0x8]; 11881 u8 max_bw_value[0x8]; 11882 }; 11883 11884 struct mlx5_ifc_ets_global_config_reg_bits { 11885 u8 reserved_at_0[0x2]; 11886 u8 r[0x1]; 11887 u8 reserved_at_3[0x1d]; 11888 11889 u8 reserved_at_20[0xc]; 11890 u8 max_bw_units[0x4]; 11891 u8 reserved_at_30[0x8]; 11892 u8 max_bw_value[0x8]; 11893 }; 11894 11895 struct mlx5_ifc_qetc_reg_bits { 11896 u8 reserved_at_0[0x8]; 11897 u8 port_number[0x8]; 11898 u8 reserved_at_10[0x30]; 11899 11900 struct mlx5_ifc_ets_tcn_config_reg_bits tc_configuration[0x8]; 11901 struct mlx5_ifc_ets_global_config_reg_bits global_configuration; 11902 }; 11903 11904 struct mlx5_ifc_qpdpm_dscp_reg_bits { 11905 u8 e[0x1]; 11906 u8 reserved_at_01[0x0b]; 11907 u8 prio[0x04]; 11908 }; 11909 11910 struct mlx5_ifc_qpdpm_reg_bits { 11911 u8 reserved_at_0[0x8]; 11912 u8 local_port[0x8]; 11913 u8 reserved_at_10[0x10]; 11914 struct mlx5_ifc_qpdpm_dscp_reg_bits dscp[64]; 11915 }; 11916 11917 struct mlx5_ifc_qpts_reg_bits { 11918 u8 reserved_at_0[0x8]; 11919 u8 local_port[0x8]; 11920 u8 reserved_at_10[0x2d]; 11921 u8 trust_state[0x3]; 11922 }; 11923 11924 struct mlx5_ifc_pptb_reg_bits { 11925 u8 reserved_at_0[0x2]; 11926 u8 mm[0x2]; 11927 u8 reserved_at_4[0x4]; 11928 u8 local_port[0x8]; 11929 u8 reserved_at_10[0x6]; 11930 u8 cm[0x1]; 11931 u8 um[0x1]; 11932 u8 pm[0x8]; 11933 11934 u8 prio_x_buff[0x20]; 11935 11936 u8 pm_msb[0x8]; 11937 u8 reserved_at_48[0x10]; 11938 u8 ctrl_buff[0x4]; 11939 u8 untagged_buff[0x4]; 11940 }; 11941 11942 struct mlx5_ifc_sbcam_reg_bits { 11943 u8 reserved_at_0[0x8]; 11944 u8 feature_group[0x8]; 11945 u8 reserved_at_10[0x8]; 11946 u8 access_reg_group[0x8]; 11947 11948 u8 reserved_at_20[0x20]; 11949 11950 u8 sb_access_reg_cap_mask[4][0x20]; 11951 11952 u8 reserved_at_c0[0x80]; 11953 11954 u8 sb_feature_cap_mask[4][0x20]; 11955 11956 u8 reserved_at_1c0[0x40]; 11957 11958 u8 cap_total_buffer_size[0x20]; 11959 11960 u8 cap_cell_size[0x10]; 11961 u8 cap_max_pg_buffers[0x8]; 11962 u8 cap_num_pool_supported[0x8]; 11963 11964 u8 reserved_at_240[0x8]; 11965 u8 cap_sbsr_stat_size[0x8]; 11966 u8 cap_max_tclass_data[0x8]; 11967 u8 cap_max_cpu_ingress_tclass_sb[0x8]; 11968 }; 11969 11970 struct mlx5_ifc_pbmc_reg_bits { 11971 u8 reserved_at_0[0x8]; 11972 u8 local_port[0x8]; 11973 u8 reserved_at_10[0x10]; 11974 11975 u8 xoff_timer_value[0x10]; 11976 u8 xoff_refresh[0x10]; 11977 11978 u8 reserved_at_40[0x9]; 11979 u8 fullness_threshold[0x7]; 11980 u8 port_buffer_size[0x10]; 11981 11982 struct mlx5_ifc_bufferx_reg_bits buffer[10]; 11983 11984 u8 reserved_at_2e0[0x80]; 11985 }; 11986 11987 struct mlx5_ifc_sbpr_reg_bits { 11988 u8 desc[0x1]; 11989 u8 snap[0x1]; 11990 u8 reserved_at_2[0x4]; 11991 u8 dir[0x2]; 11992 u8 reserved_at_8[0x14]; 11993 u8 pool[0x4]; 11994 11995 u8 infi_size[0x1]; 11996 u8 reserved_at_21[0x7]; 11997 u8 size[0x18]; 11998 11999 u8 reserved_at_40[0x1c]; 12000 u8 mode[0x4]; 12001 12002 u8 reserved_at_60[0x8]; 12003 u8 buff_occupancy[0x18]; 12004 12005 u8 clr[0x1]; 12006 u8 reserved_at_81[0x7]; 12007 u8 max_buff_occupancy[0x18]; 12008 12009 u8 reserved_at_a0[0x8]; 12010 u8 ext_buff_occupancy[0x18]; 12011 }; 12012 12013 struct mlx5_ifc_sbcm_reg_bits { 12014 u8 desc[0x1]; 12015 u8 snap[0x1]; 12016 u8 reserved_at_2[0x6]; 12017 u8 local_port[0x8]; 12018 u8 pnat[0x2]; 12019 u8 pg_buff[0x6]; 12020 u8 reserved_at_18[0x6]; 12021 u8 dir[0x2]; 12022 12023 u8 reserved_at_20[0x1f]; 12024 u8 exc[0x1]; 12025 12026 u8 reserved_at_40[0x40]; 12027 12028 u8 reserved_at_80[0x8]; 12029 u8 buff_occupancy[0x18]; 12030 12031 u8 clr[0x1]; 12032 u8 reserved_at_a1[0x7]; 12033 u8 max_buff_occupancy[0x18]; 12034 12035 u8 reserved_at_c0[0x8]; 12036 u8 min_buff[0x18]; 12037 12038 u8 infi_max[0x1]; 12039 u8 reserved_at_e1[0x7]; 12040 u8 max_buff[0x18]; 12041 12042 u8 reserved_at_100[0x20]; 12043 12044 u8 reserved_at_120[0x1c]; 12045 u8 pool[0x4]; 12046 }; 12047 12048 struct mlx5_ifc_qtct_reg_bits { 12049 u8 reserved_at_0[0x8]; 12050 u8 port_number[0x8]; 12051 u8 reserved_at_10[0xd]; 12052 u8 prio[0x3]; 12053 12054 u8 reserved_at_20[0x1d]; 12055 u8 tclass[0x3]; 12056 }; 12057 12058 struct mlx5_ifc_mcia_reg_bits { 12059 u8 l[0x1]; 12060 u8 reserved_at_1[0x7]; 12061 u8 module[0x8]; 12062 u8 reserved_at_10[0x8]; 12063 u8 status[0x8]; 12064 12065 u8 i2c_device_address[0x8]; 12066 u8 page_number[0x8]; 12067 u8 device_address[0x10]; 12068 12069 u8 reserved_at_40[0x10]; 12070 u8 size[0x10]; 12071 12072 u8 reserved_at_60[0x20]; 12073 12074 u8 dword_0[0x20]; 12075 u8 dword_1[0x20]; 12076 u8 dword_2[0x20]; 12077 u8 dword_3[0x20]; 12078 u8 dword_4[0x20]; 12079 u8 dword_5[0x20]; 12080 u8 dword_6[0x20]; 12081 u8 dword_7[0x20]; 12082 u8 dword_8[0x20]; 12083 u8 dword_9[0x20]; 12084 u8 dword_10[0x20]; 12085 u8 dword_11[0x20]; 12086 }; 12087 12088 struct mlx5_ifc_dcbx_param_bits { 12089 u8 dcbx_cee_cap[0x1]; 12090 u8 dcbx_ieee_cap[0x1]; 12091 u8 dcbx_standby_cap[0x1]; 12092 u8 reserved_at_3[0x5]; 12093 u8 port_number[0x8]; 12094 u8 reserved_at_10[0xa]; 12095 u8 max_application_table_size[6]; 12096 u8 reserved_at_20[0x15]; 12097 u8 version_oper[0x3]; 12098 u8 reserved_at_38[5]; 12099 u8 version_admin[0x3]; 12100 u8 willing_admin[0x1]; 12101 u8 reserved_at_41[0x3]; 12102 u8 pfc_cap_oper[0x4]; 12103 u8 reserved_at_48[0x4]; 12104 u8 pfc_cap_admin[0x4]; 12105 u8 reserved_at_50[0x4]; 12106 u8 num_of_tc_oper[0x4]; 12107 u8 reserved_at_58[0x4]; 12108 u8 num_of_tc_admin[0x4]; 12109 u8 remote_willing[0x1]; 12110 u8 reserved_at_61[3]; 12111 u8 remote_pfc_cap[4]; 12112 u8 reserved_at_68[0x14]; 12113 u8 remote_num_of_tc[0x4]; 12114 u8 reserved_at_80[0x18]; 12115 u8 error[0x8]; 12116 u8 reserved_at_a0[0x160]; 12117 }; 12118 12119 enum { 12120 MLX5_LAG_PORT_SELECT_MODE_QUEUE_AFFINITY = 0, 12121 MLX5_LAG_PORT_SELECT_MODE_PORT_SELECT_FT = 1, 12122 MLX5_LAG_PORT_SELECT_MODE_PORT_SELECT_MPESW = 2, 12123 }; 12124 12125 struct mlx5_ifc_lagc_bits { 12126 u8 fdb_selection_mode[0x1]; 12127 u8 reserved_at_1[0x14]; 12128 u8 port_select_mode[0x3]; 12129 u8 reserved_at_18[0x5]; 12130 u8 lag_state[0x3]; 12131 12132 u8 reserved_at_20[0xc]; 12133 u8 active_port[0x4]; 12134 u8 reserved_at_30[0x4]; 12135 u8 tx_remap_affinity_2[0x4]; 12136 u8 reserved_at_38[0x4]; 12137 u8 tx_remap_affinity_1[0x4]; 12138 }; 12139 12140 struct mlx5_ifc_create_lag_out_bits { 12141 u8 status[0x8]; 12142 u8 reserved_at_8[0x18]; 12143 12144 u8 syndrome[0x20]; 12145 12146 u8 reserved_at_40[0x40]; 12147 }; 12148 12149 struct mlx5_ifc_create_lag_in_bits { 12150 u8 opcode[0x10]; 12151 u8 reserved_at_10[0x10]; 12152 12153 u8 reserved_at_20[0x10]; 12154 u8 op_mod[0x10]; 12155 12156 struct mlx5_ifc_lagc_bits ctx; 12157 }; 12158 12159 struct mlx5_ifc_modify_lag_out_bits { 12160 u8 status[0x8]; 12161 u8 reserved_at_8[0x18]; 12162 12163 u8 syndrome[0x20]; 12164 12165 u8 reserved_at_40[0x40]; 12166 }; 12167 12168 struct mlx5_ifc_modify_lag_in_bits { 12169 u8 opcode[0x10]; 12170 u8 reserved_at_10[0x10]; 12171 12172 u8 reserved_at_20[0x10]; 12173 u8 op_mod[0x10]; 12174 12175 u8 reserved_at_40[0x20]; 12176 u8 field_select[0x20]; 12177 12178 struct mlx5_ifc_lagc_bits ctx; 12179 }; 12180 12181 struct mlx5_ifc_query_lag_out_bits { 12182 u8 status[0x8]; 12183 u8 reserved_at_8[0x18]; 12184 12185 u8 syndrome[0x20]; 12186 12187 struct mlx5_ifc_lagc_bits ctx; 12188 }; 12189 12190 struct mlx5_ifc_query_lag_in_bits { 12191 u8 opcode[0x10]; 12192 u8 reserved_at_10[0x10]; 12193 12194 u8 reserved_at_20[0x10]; 12195 u8 op_mod[0x10]; 12196 12197 u8 reserved_at_40[0x40]; 12198 }; 12199 12200 struct mlx5_ifc_destroy_lag_out_bits { 12201 u8 status[0x8]; 12202 u8 reserved_at_8[0x18]; 12203 12204 u8 syndrome[0x20]; 12205 12206 u8 reserved_at_40[0x40]; 12207 }; 12208 12209 struct mlx5_ifc_destroy_lag_in_bits { 12210 u8 opcode[0x10]; 12211 u8 reserved_at_10[0x10]; 12212 12213 u8 reserved_at_20[0x10]; 12214 u8 op_mod[0x10]; 12215 12216 u8 reserved_at_40[0x40]; 12217 }; 12218 12219 struct mlx5_ifc_create_vport_lag_out_bits { 12220 u8 status[0x8]; 12221 u8 reserved_at_8[0x18]; 12222 12223 u8 syndrome[0x20]; 12224 12225 u8 reserved_at_40[0x40]; 12226 }; 12227 12228 struct mlx5_ifc_create_vport_lag_in_bits { 12229 u8 opcode[0x10]; 12230 u8 reserved_at_10[0x10]; 12231 12232 u8 reserved_at_20[0x10]; 12233 u8 op_mod[0x10]; 12234 12235 u8 reserved_at_40[0x40]; 12236 }; 12237 12238 struct mlx5_ifc_destroy_vport_lag_out_bits { 12239 u8 status[0x8]; 12240 u8 reserved_at_8[0x18]; 12241 12242 u8 syndrome[0x20]; 12243 12244 u8 reserved_at_40[0x40]; 12245 }; 12246 12247 struct mlx5_ifc_destroy_vport_lag_in_bits { 12248 u8 opcode[0x10]; 12249 u8 reserved_at_10[0x10]; 12250 12251 u8 reserved_at_20[0x10]; 12252 u8 op_mod[0x10]; 12253 12254 u8 reserved_at_40[0x40]; 12255 }; 12256 12257 enum { 12258 MLX5_MODIFY_MEMIC_OP_MOD_ALLOC, 12259 MLX5_MODIFY_MEMIC_OP_MOD_DEALLOC, 12260 }; 12261 12262 struct mlx5_ifc_modify_memic_in_bits { 12263 u8 opcode[0x10]; 12264 u8 uid[0x10]; 12265 12266 u8 reserved_at_20[0x10]; 12267 u8 op_mod[0x10]; 12268 12269 u8 reserved_at_40[0x20]; 12270 12271 u8 reserved_at_60[0x18]; 12272 u8 memic_operation_type[0x8]; 12273 12274 u8 memic_start_addr[0x40]; 12275 12276 u8 reserved_at_c0[0x140]; 12277 }; 12278 12279 struct mlx5_ifc_modify_memic_out_bits { 12280 u8 status[0x8]; 12281 u8 reserved_at_8[0x18]; 12282 12283 u8 syndrome[0x20]; 12284 12285 u8 reserved_at_40[0x40]; 12286 12287 u8 memic_operation_addr[0x40]; 12288 12289 u8 reserved_at_c0[0x140]; 12290 }; 12291 12292 struct mlx5_ifc_alloc_memic_in_bits { 12293 u8 opcode[0x10]; 12294 u8 reserved_at_10[0x10]; 12295 12296 u8 reserved_at_20[0x10]; 12297 u8 op_mod[0x10]; 12298 12299 u8 reserved_at_30[0x20]; 12300 12301 u8 reserved_at_40[0x18]; 12302 u8 log_memic_addr_alignment[0x8]; 12303 12304 u8 range_start_addr[0x40]; 12305 12306 u8 range_size[0x20]; 12307 12308 u8 memic_size[0x20]; 12309 }; 12310 12311 struct mlx5_ifc_alloc_memic_out_bits { 12312 u8 status[0x8]; 12313 u8 reserved_at_8[0x18]; 12314 12315 u8 syndrome[0x20]; 12316 12317 u8 memic_start_addr[0x40]; 12318 }; 12319 12320 struct mlx5_ifc_dealloc_memic_in_bits { 12321 u8 opcode[0x10]; 12322 u8 reserved_at_10[0x10]; 12323 12324 u8 reserved_at_20[0x10]; 12325 u8 op_mod[0x10]; 12326 12327 u8 reserved_at_40[0x40]; 12328 12329 u8 memic_start_addr[0x40]; 12330 12331 u8 memic_size[0x20]; 12332 12333 u8 reserved_at_e0[0x20]; 12334 }; 12335 12336 struct mlx5_ifc_dealloc_memic_out_bits { 12337 u8 status[0x8]; 12338 u8 reserved_at_8[0x18]; 12339 12340 u8 syndrome[0x20]; 12341 12342 u8 reserved_at_40[0x40]; 12343 }; 12344 12345 struct mlx5_ifc_umem_bits { 12346 u8 reserved_at_0[0x80]; 12347 12348 u8 ats[0x1]; 12349 u8 reserved_at_81[0x1a]; 12350 u8 log_page_size[0x5]; 12351 12352 u8 page_offset[0x20]; 12353 12354 u8 num_of_mtt[0x40]; 12355 12356 struct mlx5_ifc_mtt_bits mtt[]; 12357 }; 12358 12359 struct mlx5_ifc_uctx_bits { 12360 u8 cap[0x20]; 12361 12362 u8 reserved_at_20[0x160]; 12363 }; 12364 12365 struct mlx5_ifc_sw_icm_bits { 12366 u8 modify_field_select[0x40]; 12367 12368 u8 reserved_at_40[0x18]; 12369 u8 log_sw_icm_size[0x8]; 12370 12371 u8 reserved_at_60[0x20]; 12372 12373 u8 sw_icm_start_addr[0x40]; 12374 12375 u8 reserved_at_c0[0x140]; 12376 }; 12377 12378 struct mlx5_ifc_geneve_tlv_option_bits { 12379 u8 modify_field_select[0x40]; 12380 12381 u8 reserved_at_40[0x18]; 12382 u8 geneve_option_fte_index[0x8]; 12383 12384 u8 option_class[0x10]; 12385 u8 option_type[0x8]; 12386 u8 reserved_at_78[0x3]; 12387 u8 option_data_length[0x5]; 12388 12389 u8 reserved_at_80[0x180]; 12390 }; 12391 12392 struct mlx5_ifc_create_umem_in_bits { 12393 u8 opcode[0x10]; 12394 u8 uid[0x10]; 12395 12396 u8 reserved_at_20[0x10]; 12397 u8 op_mod[0x10]; 12398 12399 u8 reserved_at_40[0x40]; 12400 12401 struct mlx5_ifc_umem_bits umem; 12402 }; 12403 12404 struct mlx5_ifc_create_umem_out_bits { 12405 u8 status[0x8]; 12406 u8 reserved_at_8[0x18]; 12407 12408 u8 syndrome[0x20]; 12409 12410 u8 reserved_at_40[0x8]; 12411 u8 umem_id[0x18]; 12412 12413 u8 reserved_at_60[0x20]; 12414 }; 12415 12416 struct mlx5_ifc_destroy_umem_in_bits { 12417 u8 opcode[0x10]; 12418 u8 uid[0x10]; 12419 12420 u8 reserved_at_20[0x10]; 12421 u8 op_mod[0x10]; 12422 12423 u8 reserved_at_40[0x8]; 12424 u8 umem_id[0x18]; 12425 12426 u8 reserved_at_60[0x20]; 12427 }; 12428 12429 struct mlx5_ifc_destroy_umem_out_bits { 12430 u8 status[0x8]; 12431 u8 reserved_at_8[0x18]; 12432 12433 u8 syndrome[0x20]; 12434 12435 u8 reserved_at_40[0x40]; 12436 }; 12437 12438 struct mlx5_ifc_create_uctx_in_bits { 12439 u8 opcode[0x10]; 12440 u8 reserved_at_10[0x10]; 12441 12442 u8 reserved_at_20[0x10]; 12443 u8 op_mod[0x10]; 12444 12445 u8 reserved_at_40[0x40]; 12446 12447 struct mlx5_ifc_uctx_bits uctx; 12448 }; 12449 12450 struct mlx5_ifc_create_uctx_out_bits { 12451 u8 status[0x8]; 12452 u8 reserved_at_8[0x18]; 12453 12454 u8 syndrome[0x20]; 12455 12456 u8 reserved_at_40[0x10]; 12457 u8 uid[0x10]; 12458 12459 u8 reserved_at_60[0x20]; 12460 }; 12461 12462 struct mlx5_ifc_destroy_uctx_in_bits { 12463 u8 opcode[0x10]; 12464 u8 reserved_at_10[0x10]; 12465 12466 u8 reserved_at_20[0x10]; 12467 u8 op_mod[0x10]; 12468 12469 u8 reserved_at_40[0x10]; 12470 u8 uid[0x10]; 12471 12472 u8 reserved_at_60[0x20]; 12473 }; 12474 12475 struct mlx5_ifc_destroy_uctx_out_bits { 12476 u8 status[0x8]; 12477 u8 reserved_at_8[0x18]; 12478 12479 u8 syndrome[0x20]; 12480 12481 u8 reserved_at_40[0x40]; 12482 }; 12483 12484 struct mlx5_ifc_create_sw_icm_in_bits { 12485 struct mlx5_ifc_general_obj_in_cmd_hdr_bits hdr; 12486 struct mlx5_ifc_sw_icm_bits sw_icm; 12487 }; 12488 12489 struct mlx5_ifc_create_geneve_tlv_option_in_bits { 12490 struct mlx5_ifc_general_obj_in_cmd_hdr_bits hdr; 12491 struct mlx5_ifc_geneve_tlv_option_bits geneve_tlv_opt; 12492 }; 12493 12494 struct mlx5_ifc_mtrc_string_db_param_bits { 12495 u8 string_db_base_address[0x20]; 12496 12497 u8 reserved_at_20[0x8]; 12498 u8 string_db_size[0x18]; 12499 }; 12500 12501 struct mlx5_ifc_mtrc_cap_bits { 12502 u8 trace_owner[0x1]; 12503 u8 trace_to_memory[0x1]; 12504 u8 reserved_at_2[0x4]; 12505 u8 trc_ver[0x2]; 12506 u8 reserved_at_8[0x14]; 12507 u8 num_string_db[0x4]; 12508 12509 u8 first_string_trace[0x8]; 12510 u8 num_string_trace[0x8]; 12511 u8 reserved_at_30[0x28]; 12512 12513 u8 log_max_trace_buffer_size[0x8]; 12514 12515 u8 reserved_at_60[0x20]; 12516 12517 struct mlx5_ifc_mtrc_string_db_param_bits string_db_param[8]; 12518 12519 u8 reserved_at_280[0x180]; 12520 }; 12521 12522 struct mlx5_ifc_mtrc_conf_bits { 12523 u8 reserved_at_0[0x1c]; 12524 u8 trace_mode[0x4]; 12525 u8 reserved_at_20[0x18]; 12526 u8 log_trace_buffer_size[0x8]; 12527 u8 trace_mkey[0x20]; 12528 u8 reserved_at_60[0x3a0]; 12529 }; 12530 12531 struct mlx5_ifc_mtrc_stdb_bits { 12532 u8 string_db_index[0x4]; 12533 u8 reserved_at_4[0x4]; 12534 u8 read_size[0x18]; 12535 u8 start_offset[0x20]; 12536 u8 string_db_data[]; 12537 }; 12538 12539 struct mlx5_ifc_mtrc_ctrl_bits { 12540 u8 trace_status[0x2]; 12541 u8 reserved_at_2[0x2]; 12542 u8 arm_event[0x1]; 12543 u8 reserved_at_5[0xb]; 12544 u8 modify_field_select[0x10]; 12545 u8 reserved_at_20[0x2b]; 12546 u8 current_timestamp52_32[0x15]; 12547 u8 current_timestamp31_0[0x20]; 12548 u8 reserved_at_80[0x180]; 12549 }; 12550 12551 struct mlx5_ifc_host_params_context_bits { 12552 u8 host_number[0x8]; 12553 u8 reserved_at_8[0x5]; 12554 u8 host_pf_not_exist[0x1]; 12555 u8 reserved_at_14[0x1]; 12556 u8 host_pf_disabled[0x1]; 12557 u8 host_num_of_vfs[0x10]; 12558 12559 u8 host_total_vfs[0x10]; 12560 u8 host_pci_bus[0x10]; 12561 12562 u8 reserved_at_40[0x10]; 12563 u8 host_pci_device[0x10]; 12564 12565 u8 reserved_at_60[0x10]; 12566 u8 host_pci_function[0x10]; 12567 12568 u8 reserved_at_80[0x180]; 12569 }; 12570 12571 struct mlx5_ifc_query_esw_functions_in_bits { 12572 u8 opcode[0x10]; 12573 u8 reserved_at_10[0x10]; 12574 12575 u8 reserved_at_20[0x10]; 12576 u8 op_mod[0x10]; 12577 12578 u8 reserved_at_40[0x40]; 12579 }; 12580 12581 struct mlx5_ifc_query_esw_functions_out_bits { 12582 u8 status[0x8]; 12583 u8 reserved_at_8[0x18]; 12584 12585 u8 syndrome[0x20]; 12586 12587 u8 reserved_at_40[0x40]; 12588 12589 struct mlx5_ifc_host_params_context_bits host_params_context; 12590 12591 u8 reserved_at_280[0x180]; 12592 u8 host_sf_enable[][0x40]; 12593 }; 12594 12595 struct mlx5_ifc_sf_partition_bits { 12596 u8 reserved_at_0[0x10]; 12597 u8 log_num_sf[0x8]; 12598 u8 log_sf_bar_size[0x8]; 12599 }; 12600 12601 struct mlx5_ifc_query_sf_partitions_out_bits { 12602 u8 status[0x8]; 12603 u8 reserved_at_8[0x18]; 12604 12605 u8 syndrome[0x20]; 12606 12607 u8 reserved_at_40[0x18]; 12608 u8 num_sf_partitions[0x8]; 12609 12610 u8 reserved_at_60[0x20]; 12611 12612 struct mlx5_ifc_sf_partition_bits sf_partition[]; 12613 }; 12614 12615 struct mlx5_ifc_query_sf_partitions_in_bits { 12616 u8 opcode[0x10]; 12617 u8 reserved_at_10[0x10]; 12618 12619 u8 reserved_at_20[0x10]; 12620 u8 op_mod[0x10]; 12621 12622 u8 reserved_at_40[0x40]; 12623 }; 12624 12625 struct mlx5_ifc_dealloc_sf_out_bits { 12626 u8 status[0x8]; 12627 u8 reserved_at_8[0x18]; 12628 12629 u8 syndrome[0x20]; 12630 12631 u8 reserved_at_40[0x40]; 12632 }; 12633 12634 struct mlx5_ifc_dealloc_sf_in_bits { 12635 u8 opcode[0x10]; 12636 u8 reserved_at_10[0x10]; 12637 12638 u8 reserved_at_20[0x10]; 12639 u8 op_mod[0x10]; 12640 12641 u8 reserved_at_40[0x10]; 12642 u8 function_id[0x10]; 12643 12644 u8 reserved_at_60[0x20]; 12645 }; 12646 12647 struct mlx5_ifc_alloc_sf_out_bits { 12648 u8 status[0x8]; 12649 u8 reserved_at_8[0x18]; 12650 12651 u8 syndrome[0x20]; 12652 12653 u8 reserved_at_40[0x40]; 12654 }; 12655 12656 struct mlx5_ifc_alloc_sf_in_bits { 12657 u8 opcode[0x10]; 12658 u8 reserved_at_10[0x10]; 12659 12660 u8 reserved_at_20[0x10]; 12661 u8 op_mod[0x10]; 12662 12663 u8 reserved_at_40[0x10]; 12664 u8 function_id[0x10]; 12665 12666 u8 reserved_at_60[0x20]; 12667 }; 12668 12669 struct mlx5_ifc_affiliated_event_header_bits { 12670 u8 reserved_at_0[0x10]; 12671 u8 obj_type[0x10]; 12672 12673 u8 obj_id[0x20]; 12674 }; 12675 12676 enum { 12677 MLX5_GENERAL_OBJECT_TYPES_ENCRYPTION_KEY = 0xc, 12678 MLX5_GENERAL_OBJECT_TYPES_IPSEC = 0x13, 12679 MLX5_GENERAL_OBJECT_TYPES_SAMPLER = 0x20, 12680 MLX5_GENERAL_OBJECT_TYPES_FLOW_METER_ASO = 0x24, 12681 MLX5_GENERAL_OBJECT_TYPES_MACSEC = 0x27, 12682 MLX5_GENERAL_OBJECT_TYPES_INT_KEK = 0x47, 12683 MLX5_GENERAL_OBJECT_TYPES_RDMA_CTRL = 0x53, 12684 MLX5_GENERAL_OBJECT_TYPES_PCIE_CONG_EVENT = 0x58, 12685 MLX5_GENERAL_OBJECT_TYPES_FLOW_TABLE_ALIAS = 0xff15, 12686 }; 12687 12688 enum { 12689 MLX5_HCA_CAP_GENERAL_OBJECT_TYPES_ENCRYPTION_KEY = 12690 BIT_ULL(MLX5_GENERAL_OBJECT_TYPES_ENCRYPTION_KEY), 12691 MLX5_HCA_CAP_GENERAL_OBJECT_TYPES_IPSEC = 12692 BIT_ULL(MLX5_GENERAL_OBJECT_TYPES_IPSEC), 12693 MLX5_HCA_CAP_GENERAL_OBJECT_TYPES_SAMPLER = 12694 BIT_ULL(MLX5_GENERAL_OBJECT_TYPES_SAMPLER), 12695 MLX5_HCA_CAP_GENERAL_OBJECT_TYPES_FLOW_METER_ASO = 12696 BIT_ULL(MLX5_GENERAL_OBJECT_TYPES_FLOW_METER_ASO), 12697 }; 12698 12699 enum { 12700 MLX5_HCA_CAP_2_GENERAL_OBJECT_TYPES_RDMA_CTRL = 12701 BIT_ULL(MLX5_GENERAL_OBJECT_TYPES_RDMA_CTRL - 0x40), 12702 MLX5_HCA_CAP_2_GENERAL_OBJECT_TYPES_PCIE_CONG_EVENT = 12703 BIT_ULL(MLX5_GENERAL_OBJECT_TYPES_PCIE_CONG_EVENT - 0x40), 12704 }; 12705 12706 enum { 12707 MLX5_IPSEC_OBJECT_ICV_LEN_16B, 12708 }; 12709 12710 enum { 12711 MLX5_IPSEC_ASO_REG_C_0_1 = 0x0, 12712 MLX5_IPSEC_ASO_REG_C_2_3 = 0x1, 12713 MLX5_IPSEC_ASO_REG_C_4_5 = 0x2, 12714 MLX5_IPSEC_ASO_REG_C_6_7 = 0x3, 12715 }; 12716 12717 enum { 12718 MLX5_IPSEC_ASO_MODE = 0x0, 12719 MLX5_IPSEC_ASO_REPLAY_PROTECTION = 0x1, 12720 MLX5_IPSEC_ASO_INC_SN = 0x2, 12721 }; 12722 12723 enum { 12724 MLX5_IPSEC_ASO_REPLAY_WIN_32BIT = 0x0, 12725 MLX5_IPSEC_ASO_REPLAY_WIN_64BIT = 0x1, 12726 MLX5_IPSEC_ASO_REPLAY_WIN_128BIT = 0x2, 12727 MLX5_IPSEC_ASO_REPLAY_WIN_256BIT = 0x3, 12728 }; 12729 12730 struct mlx5_ifc_ipsec_aso_bits { 12731 u8 valid[0x1]; 12732 u8 reserved_at_201[0x1]; 12733 u8 mode[0x2]; 12734 u8 window_sz[0x2]; 12735 u8 soft_lft_arm[0x1]; 12736 u8 hard_lft_arm[0x1]; 12737 u8 remove_flow_enable[0x1]; 12738 u8 esn_event_arm[0x1]; 12739 u8 reserved_at_20a[0x16]; 12740 12741 u8 remove_flow_pkt_cnt[0x20]; 12742 12743 u8 remove_flow_soft_lft[0x20]; 12744 12745 u8 reserved_at_260[0x80]; 12746 12747 u8 mode_parameter[0x20]; 12748 12749 u8 replay_protection_window[0x100]; 12750 }; 12751 12752 struct mlx5_ifc_ipsec_obj_bits { 12753 u8 modify_field_select[0x40]; 12754 u8 full_offload[0x1]; 12755 u8 reserved_at_41[0x1]; 12756 u8 esn_en[0x1]; 12757 u8 esn_overlap[0x1]; 12758 u8 reserved_at_44[0x2]; 12759 u8 icv_length[0x2]; 12760 u8 reserved_at_48[0x4]; 12761 u8 aso_return_reg[0x4]; 12762 u8 reserved_at_50[0x10]; 12763 12764 u8 esn_msb[0x20]; 12765 12766 u8 reserved_at_80[0x8]; 12767 u8 dekn[0x18]; 12768 12769 u8 salt[0x20]; 12770 12771 u8 implicit_iv[0x40]; 12772 12773 u8 reserved_at_100[0x8]; 12774 u8 ipsec_aso_access_pd[0x18]; 12775 u8 reserved_at_120[0xe0]; 12776 12777 struct mlx5_ifc_ipsec_aso_bits ipsec_aso; 12778 }; 12779 12780 struct mlx5_ifc_create_ipsec_obj_in_bits { 12781 struct mlx5_ifc_general_obj_in_cmd_hdr_bits general_obj_in_cmd_hdr; 12782 struct mlx5_ifc_ipsec_obj_bits ipsec_object; 12783 }; 12784 12785 enum { 12786 MLX5_MODIFY_IPSEC_BITMASK_ESN_OVERLAP = BIT(0), 12787 MLX5_MODIFY_IPSEC_BITMASK_ESN_MSB = BIT(1), 12788 }; 12789 12790 struct mlx5_ifc_query_ipsec_obj_out_bits { 12791 struct mlx5_ifc_general_obj_out_cmd_hdr_bits general_obj_out_cmd_hdr; 12792 struct mlx5_ifc_ipsec_obj_bits ipsec_object; 12793 }; 12794 12795 struct mlx5_ifc_modify_ipsec_obj_in_bits { 12796 struct mlx5_ifc_general_obj_in_cmd_hdr_bits general_obj_in_cmd_hdr; 12797 struct mlx5_ifc_ipsec_obj_bits ipsec_object; 12798 }; 12799 12800 enum { 12801 MLX5_MACSEC_ASO_REPLAY_PROTECTION = 0x1, 12802 }; 12803 12804 enum { 12805 MLX5_MACSEC_ASO_REPLAY_WIN_32BIT = 0x0, 12806 MLX5_MACSEC_ASO_REPLAY_WIN_64BIT = 0x1, 12807 MLX5_MACSEC_ASO_REPLAY_WIN_128BIT = 0x2, 12808 MLX5_MACSEC_ASO_REPLAY_WIN_256BIT = 0x3, 12809 }; 12810 12811 #define MLX5_MACSEC_ASO_INC_SN 0x2 12812 #define MLX5_MACSEC_ASO_REG_C_4_5 0x2 12813 12814 struct mlx5_ifc_macsec_aso_bits { 12815 u8 valid[0x1]; 12816 u8 reserved_at_1[0x1]; 12817 u8 mode[0x2]; 12818 u8 window_size[0x2]; 12819 u8 soft_lifetime_arm[0x1]; 12820 u8 hard_lifetime_arm[0x1]; 12821 u8 remove_flow_enable[0x1]; 12822 u8 epn_event_arm[0x1]; 12823 u8 reserved_at_a[0x16]; 12824 12825 u8 remove_flow_packet_count[0x20]; 12826 12827 u8 remove_flow_soft_lifetime[0x20]; 12828 12829 u8 reserved_at_60[0x80]; 12830 12831 u8 mode_parameter[0x20]; 12832 12833 u8 replay_protection_window[8][0x20]; 12834 }; 12835 12836 struct mlx5_ifc_macsec_offload_obj_bits { 12837 u8 modify_field_select[0x40]; 12838 12839 u8 confidentiality_en[0x1]; 12840 u8 reserved_at_41[0x1]; 12841 u8 epn_en[0x1]; 12842 u8 epn_overlap[0x1]; 12843 u8 reserved_at_44[0x2]; 12844 u8 confidentiality_offset[0x2]; 12845 u8 reserved_at_48[0x4]; 12846 u8 aso_return_reg[0x4]; 12847 u8 reserved_at_50[0x10]; 12848 12849 u8 epn_msb[0x20]; 12850 12851 u8 reserved_at_80[0x8]; 12852 u8 dekn[0x18]; 12853 12854 u8 reserved_at_a0[0x20]; 12855 12856 u8 sci[0x40]; 12857 12858 u8 reserved_at_100[0x8]; 12859 u8 macsec_aso_access_pd[0x18]; 12860 12861 u8 reserved_at_120[0x60]; 12862 12863 u8 salt[3][0x20]; 12864 12865 u8 reserved_at_1e0[0x20]; 12866 12867 struct mlx5_ifc_macsec_aso_bits macsec_aso; 12868 }; 12869 12870 struct mlx5_ifc_create_macsec_obj_in_bits { 12871 struct mlx5_ifc_general_obj_in_cmd_hdr_bits general_obj_in_cmd_hdr; 12872 struct mlx5_ifc_macsec_offload_obj_bits macsec_object; 12873 }; 12874 12875 struct mlx5_ifc_modify_macsec_obj_in_bits { 12876 struct mlx5_ifc_general_obj_in_cmd_hdr_bits general_obj_in_cmd_hdr; 12877 struct mlx5_ifc_macsec_offload_obj_bits macsec_object; 12878 }; 12879 12880 enum { 12881 MLX5_MODIFY_MACSEC_BITMASK_EPN_OVERLAP = BIT(0), 12882 MLX5_MODIFY_MACSEC_BITMASK_EPN_MSB = BIT(1), 12883 }; 12884 12885 struct mlx5_ifc_query_macsec_obj_out_bits { 12886 struct mlx5_ifc_general_obj_out_cmd_hdr_bits general_obj_out_cmd_hdr; 12887 struct mlx5_ifc_macsec_offload_obj_bits macsec_object; 12888 }; 12889 12890 struct mlx5_ifc_wrapped_dek_bits { 12891 u8 gcm_iv[0x60]; 12892 12893 u8 reserved_at_60[0x20]; 12894 12895 u8 const0[0x1]; 12896 u8 key_size[0x1]; 12897 u8 reserved_at_82[0x2]; 12898 u8 key2_invalid[0x1]; 12899 u8 reserved_at_85[0x3]; 12900 u8 pd[0x18]; 12901 12902 u8 key_purpose[0x5]; 12903 u8 reserved_at_a5[0x13]; 12904 u8 kek_id[0x8]; 12905 12906 u8 reserved_at_c0[0x40]; 12907 12908 u8 key1[0x8][0x20]; 12909 12910 u8 key2[0x8][0x20]; 12911 12912 u8 reserved_at_300[0x40]; 12913 12914 u8 const1[0x1]; 12915 u8 reserved_at_341[0x1f]; 12916 12917 u8 reserved_at_360[0x20]; 12918 12919 u8 auth_tag[0x80]; 12920 }; 12921 12922 struct mlx5_ifc_encryption_key_obj_bits { 12923 u8 modify_field_select[0x40]; 12924 12925 u8 state[0x8]; 12926 u8 sw_wrapped[0x1]; 12927 u8 reserved_at_49[0xb]; 12928 u8 key_size[0x4]; 12929 u8 reserved_at_58[0x4]; 12930 u8 key_purpose[0x4]; 12931 12932 u8 reserved_at_60[0x8]; 12933 u8 pd[0x18]; 12934 12935 u8 reserved_at_80[0x100]; 12936 12937 u8 opaque[0x40]; 12938 12939 u8 reserved_at_1c0[0x40]; 12940 12941 u8 key[8][0x80]; 12942 12943 u8 sw_wrapped_dek[8][0x80]; 12944 12945 u8 reserved_at_a00[0x600]; 12946 }; 12947 12948 struct mlx5_ifc_create_encryption_key_in_bits { 12949 struct mlx5_ifc_general_obj_in_cmd_hdr_bits general_obj_in_cmd_hdr; 12950 struct mlx5_ifc_encryption_key_obj_bits encryption_key_object; 12951 }; 12952 12953 struct mlx5_ifc_modify_encryption_key_in_bits { 12954 struct mlx5_ifc_general_obj_in_cmd_hdr_bits general_obj_in_cmd_hdr; 12955 struct mlx5_ifc_encryption_key_obj_bits encryption_key_object; 12956 }; 12957 12958 enum { 12959 MLX5_FLOW_METER_MODE_BYTES_IP_LENGTH = 0x0, 12960 MLX5_FLOW_METER_MODE_BYTES_CALC_WITH_L2 = 0x1, 12961 MLX5_FLOW_METER_MODE_BYTES_CALC_WITH_L2_IPG = 0x2, 12962 MLX5_FLOW_METER_MODE_NUM_PACKETS = 0x3, 12963 }; 12964 12965 struct mlx5_ifc_flow_meter_parameters_bits { 12966 u8 valid[0x1]; 12967 u8 bucket_overflow[0x1]; 12968 u8 start_color[0x2]; 12969 u8 both_buckets_on_green[0x1]; 12970 u8 reserved_at_5[0x1]; 12971 u8 meter_mode[0x2]; 12972 u8 reserved_at_8[0x18]; 12973 12974 u8 reserved_at_20[0x20]; 12975 12976 u8 reserved_at_40[0x3]; 12977 u8 cbs_exponent[0x5]; 12978 u8 cbs_mantissa[0x8]; 12979 u8 reserved_at_50[0x3]; 12980 u8 cir_exponent[0x5]; 12981 u8 cir_mantissa[0x8]; 12982 12983 u8 reserved_at_60[0x20]; 12984 12985 u8 reserved_at_80[0x3]; 12986 u8 ebs_exponent[0x5]; 12987 u8 ebs_mantissa[0x8]; 12988 u8 reserved_at_90[0x3]; 12989 u8 eir_exponent[0x5]; 12990 u8 eir_mantissa[0x8]; 12991 12992 u8 reserved_at_a0[0x60]; 12993 }; 12994 12995 struct mlx5_ifc_flow_meter_aso_obj_bits { 12996 u8 modify_field_select[0x40]; 12997 12998 u8 reserved_at_40[0x40]; 12999 13000 u8 reserved_at_80[0x8]; 13001 u8 meter_aso_access_pd[0x18]; 13002 13003 u8 reserved_at_a0[0x160]; 13004 13005 struct mlx5_ifc_flow_meter_parameters_bits flow_meter_parameters[2]; 13006 }; 13007 13008 struct mlx5_ifc_create_flow_meter_aso_obj_in_bits { 13009 struct mlx5_ifc_general_obj_in_cmd_hdr_bits hdr; 13010 struct mlx5_ifc_flow_meter_aso_obj_bits flow_meter_aso_obj; 13011 }; 13012 13013 struct mlx5_ifc_int_kek_obj_bits { 13014 u8 modify_field_select[0x40]; 13015 13016 u8 state[0x8]; 13017 u8 auto_gen[0x1]; 13018 u8 reserved_at_49[0xb]; 13019 u8 key_size[0x4]; 13020 u8 reserved_at_58[0x8]; 13021 13022 u8 reserved_at_60[0x8]; 13023 u8 pd[0x18]; 13024 13025 u8 reserved_at_80[0x180]; 13026 u8 key[8][0x80]; 13027 13028 u8 reserved_at_600[0x200]; 13029 }; 13030 13031 struct mlx5_ifc_create_int_kek_obj_in_bits { 13032 struct mlx5_ifc_general_obj_in_cmd_hdr_bits general_obj_in_cmd_hdr; 13033 struct mlx5_ifc_int_kek_obj_bits int_kek_object; 13034 }; 13035 13036 struct mlx5_ifc_create_int_kek_obj_out_bits { 13037 struct mlx5_ifc_general_obj_out_cmd_hdr_bits general_obj_out_cmd_hdr; 13038 struct mlx5_ifc_int_kek_obj_bits int_kek_object; 13039 }; 13040 13041 struct mlx5_ifc_sampler_obj_bits { 13042 u8 modify_field_select[0x40]; 13043 13044 u8 table_type[0x8]; 13045 u8 level[0x8]; 13046 u8 reserved_at_50[0xf]; 13047 u8 ignore_flow_level[0x1]; 13048 13049 u8 sample_ratio[0x20]; 13050 13051 u8 reserved_at_80[0x8]; 13052 u8 sample_table_id[0x18]; 13053 13054 u8 reserved_at_a0[0x8]; 13055 u8 default_table_id[0x18]; 13056 13057 u8 sw_steering_icm_address_rx[0x40]; 13058 u8 sw_steering_icm_address_tx[0x40]; 13059 13060 u8 reserved_at_140[0xa0]; 13061 }; 13062 13063 struct mlx5_ifc_create_sampler_obj_in_bits { 13064 struct mlx5_ifc_general_obj_in_cmd_hdr_bits general_obj_in_cmd_hdr; 13065 struct mlx5_ifc_sampler_obj_bits sampler_object; 13066 }; 13067 13068 struct mlx5_ifc_query_sampler_obj_out_bits { 13069 struct mlx5_ifc_general_obj_out_cmd_hdr_bits general_obj_out_cmd_hdr; 13070 struct mlx5_ifc_sampler_obj_bits sampler_object; 13071 }; 13072 13073 enum { 13074 MLX5_GENERAL_OBJECT_TYPE_ENCRYPTION_KEY_KEY_SIZE_128 = 0x0, 13075 MLX5_GENERAL_OBJECT_TYPE_ENCRYPTION_KEY_KEY_SIZE_256 = 0x1, 13076 }; 13077 13078 enum { 13079 MLX5_GENERAL_OBJECT_TYPE_ENCRYPTION_KEY_PURPOSE_TLS = 0x1, 13080 MLX5_GENERAL_OBJECT_TYPE_ENCRYPTION_KEY_PURPOSE_IPSEC = 0x2, 13081 MLX5_GENERAL_OBJECT_TYPE_ENCRYPTION_KEY_PURPOSE_MACSEC = 0x4, 13082 }; 13083 13084 struct mlx5_ifc_tls_static_params_bits { 13085 u8 const_2[0x2]; 13086 u8 tls_version[0x4]; 13087 u8 const_1[0x2]; 13088 u8 reserved_at_8[0x14]; 13089 u8 encryption_standard[0x4]; 13090 13091 u8 reserved_at_20[0x20]; 13092 13093 u8 initial_record_number[0x40]; 13094 13095 u8 resync_tcp_sn[0x20]; 13096 13097 u8 gcm_iv[0x20]; 13098 13099 u8 implicit_iv[0x40]; 13100 13101 u8 reserved_at_100[0x8]; 13102 u8 dek_index[0x18]; 13103 13104 u8 reserved_at_120[0xe0]; 13105 }; 13106 13107 struct mlx5_ifc_tls_progress_params_bits { 13108 u8 next_record_tcp_sn[0x20]; 13109 13110 u8 hw_resync_tcp_sn[0x20]; 13111 13112 u8 record_tracker_state[0x2]; 13113 u8 auth_state[0x2]; 13114 u8 reserved_at_44[0x4]; 13115 u8 hw_offset_record_number[0x18]; 13116 }; 13117 13118 enum { 13119 MLX5_MTT_PERM_READ = 1 << 0, 13120 MLX5_MTT_PERM_WRITE = 1 << 1, 13121 MLX5_MTT_PERM_RW = MLX5_MTT_PERM_READ | MLX5_MTT_PERM_WRITE, 13122 }; 13123 13124 enum { 13125 MLX5_SUSPEND_VHCA_IN_OP_MOD_SUSPEND_INITIATOR = 0x0, 13126 MLX5_SUSPEND_VHCA_IN_OP_MOD_SUSPEND_RESPONDER = 0x1, 13127 }; 13128 13129 struct mlx5_ifc_suspend_vhca_in_bits { 13130 u8 opcode[0x10]; 13131 u8 uid[0x10]; 13132 13133 u8 reserved_at_20[0x10]; 13134 u8 op_mod[0x10]; 13135 13136 u8 reserved_at_40[0x10]; 13137 u8 vhca_id[0x10]; 13138 13139 u8 reserved_at_60[0x20]; 13140 }; 13141 13142 struct mlx5_ifc_suspend_vhca_out_bits { 13143 u8 status[0x8]; 13144 u8 reserved_at_8[0x18]; 13145 13146 u8 syndrome[0x20]; 13147 13148 u8 reserved_at_40[0x40]; 13149 }; 13150 13151 enum { 13152 MLX5_RESUME_VHCA_IN_OP_MOD_RESUME_RESPONDER = 0x0, 13153 MLX5_RESUME_VHCA_IN_OP_MOD_RESUME_INITIATOR = 0x1, 13154 }; 13155 13156 struct mlx5_ifc_resume_vhca_in_bits { 13157 u8 opcode[0x10]; 13158 u8 uid[0x10]; 13159 13160 u8 reserved_at_20[0x10]; 13161 u8 op_mod[0x10]; 13162 13163 u8 reserved_at_40[0x10]; 13164 u8 vhca_id[0x10]; 13165 13166 u8 reserved_at_60[0x20]; 13167 }; 13168 13169 struct mlx5_ifc_resume_vhca_out_bits { 13170 u8 status[0x8]; 13171 u8 reserved_at_8[0x18]; 13172 13173 u8 syndrome[0x20]; 13174 13175 u8 reserved_at_40[0x40]; 13176 }; 13177 13178 struct mlx5_ifc_query_vhca_migration_state_in_bits { 13179 u8 opcode[0x10]; 13180 u8 uid[0x10]; 13181 13182 u8 reserved_at_20[0x10]; 13183 u8 op_mod[0x10]; 13184 13185 u8 incremental[0x1]; 13186 u8 chunk[0x1]; 13187 u8 reserved_at_42[0xe]; 13188 u8 vhca_id[0x10]; 13189 13190 u8 reserved_at_60[0x20]; 13191 }; 13192 13193 struct mlx5_ifc_query_vhca_migration_state_out_bits { 13194 u8 status[0x8]; 13195 u8 reserved_at_8[0x18]; 13196 13197 u8 syndrome[0x20]; 13198 13199 u8 reserved_at_40[0x40]; 13200 13201 u8 required_umem_size[0x20]; 13202 13203 u8 reserved_at_a0[0x20]; 13204 13205 u8 remaining_total_size[0x40]; 13206 13207 u8 reserved_at_100[0x100]; 13208 }; 13209 13210 struct mlx5_ifc_save_vhca_state_in_bits { 13211 u8 opcode[0x10]; 13212 u8 uid[0x10]; 13213 13214 u8 reserved_at_20[0x10]; 13215 u8 op_mod[0x10]; 13216 13217 u8 incremental[0x1]; 13218 u8 set_track[0x1]; 13219 u8 reserved_at_42[0xe]; 13220 u8 vhca_id[0x10]; 13221 13222 u8 reserved_at_60[0x20]; 13223 13224 u8 va[0x40]; 13225 13226 u8 mkey[0x20]; 13227 13228 u8 size[0x20]; 13229 }; 13230 13231 struct mlx5_ifc_save_vhca_state_out_bits { 13232 u8 status[0x8]; 13233 u8 reserved_at_8[0x18]; 13234 13235 u8 syndrome[0x20]; 13236 13237 u8 actual_image_size[0x20]; 13238 13239 u8 next_required_umem_size[0x20]; 13240 }; 13241 13242 struct mlx5_ifc_load_vhca_state_in_bits { 13243 u8 opcode[0x10]; 13244 u8 uid[0x10]; 13245 13246 u8 reserved_at_20[0x10]; 13247 u8 op_mod[0x10]; 13248 13249 u8 reserved_at_40[0x10]; 13250 u8 vhca_id[0x10]; 13251 13252 u8 reserved_at_60[0x20]; 13253 13254 u8 va[0x40]; 13255 13256 u8 mkey[0x20]; 13257 13258 u8 size[0x20]; 13259 }; 13260 13261 struct mlx5_ifc_load_vhca_state_out_bits { 13262 u8 status[0x8]; 13263 u8 reserved_at_8[0x18]; 13264 13265 u8 syndrome[0x20]; 13266 13267 u8 reserved_at_40[0x40]; 13268 }; 13269 13270 struct mlx5_ifc_adv_rdma_cap_bits { 13271 u8 rdma_transport_manager[0x1]; 13272 u8 rdma_transport_manager_other_eswitch[0x1]; 13273 u8 reserved_at_2[0x1e]; 13274 13275 u8 rcx_type[0x8]; 13276 u8 reserved_at_28[0x2]; 13277 u8 ps_entry_log_max_value[0x6]; 13278 u8 reserved_at_30[0x6]; 13279 u8 qp_max_ps_num_entry[0xa]; 13280 13281 u8 mp_max_num_queues[0x8]; 13282 u8 ps_user_context_max_log_size[0x8]; 13283 u8 message_based_qp_and_striding_wq[0x8]; 13284 u8 reserved_at_58[0x8]; 13285 13286 u8 max_receive_send_message_size_stride[0x10]; 13287 u8 reserved_at_70[0x10]; 13288 13289 u8 max_receive_send_message_size_byte[0x20]; 13290 13291 u8 reserved_at_a0[0x160]; 13292 13293 struct mlx5_ifc_flow_table_prop_layout_bits rdma_transport_rx_flow_table_properties; 13294 13295 struct mlx5_ifc_flow_table_prop_layout_bits rdma_transport_tx_flow_table_properties; 13296 13297 struct mlx5_ifc_flow_table_fields_supported_2_bits rdma_transport_rx_ft_field_support_2; 13298 13299 struct mlx5_ifc_flow_table_fields_supported_2_bits rdma_transport_tx_ft_field_support_2; 13300 13301 struct mlx5_ifc_flow_table_fields_supported_2_bits rdma_transport_rx_ft_field_bitmask_support_2; 13302 13303 struct mlx5_ifc_flow_table_fields_supported_2_bits rdma_transport_tx_ft_field_bitmask_support_2; 13304 13305 u8 reserved_at_800[0x3800]; 13306 }; 13307 13308 struct mlx5_ifc_adv_virtualization_cap_bits { 13309 u8 reserved_at_0[0x3]; 13310 u8 pg_track_log_max_num[0x5]; 13311 u8 pg_track_max_num_range[0x8]; 13312 u8 pg_track_log_min_addr_space[0x8]; 13313 u8 pg_track_log_max_addr_space[0x8]; 13314 13315 u8 reserved_at_20[0x3]; 13316 u8 pg_track_log_min_msg_size[0x5]; 13317 u8 reserved_at_28[0x3]; 13318 u8 pg_track_log_max_msg_size[0x5]; 13319 u8 reserved_at_30[0x3]; 13320 u8 pg_track_log_min_page_size[0x5]; 13321 u8 reserved_at_38[0x3]; 13322 u8 pg_track_log_max_page_size[0x5]; 13323 13324 u8 reserved_at_40[0x7c0]; 13325 }; 13326 13327 struct mlx5_ifc_page_track_report_entry_bits { 13328 u8 dirty_address_high[0x20]; 13329 13330 u8 dirty_address_low[0x20]; 13331 }; 13332 13333 enum { 13334 MLX5_PAGE_TRACK_STATE_TRACKING, 13335 MLX5_PAGE_TRACK_STATE_REPORTING, 13336 MLX5_PAGE_TRACK_STATE_ERROR, 13337 }; 13338 13339 struct mlx5_ifc_page_track_range_bits { 13340 u8 start_address[0x40]; 13341 13342 u8 length[0x40]; 13343 }; 13344 13345 struct mlx5_ifc_page_track_bits { 13346 u8 modify_field_select[0x40]; 13347 13348 u8 reserved_at_40[0x10]; 13349 u8 vhca_id[0x10]; 13350 13351 u8 reserved_at_60[0x20]; 13352 13353 u8 state[0x4]; 13354 u8 track_type[0x4]; 13355 u8 log_addr_space_size[0x8]; 13356 u8 reserved_at_90[0x3]; 13357 u8 log_page_size[0x5]; 13358 u8 reserved_at_98[0x3]; 13359 u8 log_msg_size[0x5]; 13360 13361 u8 reserved_at_a0[0x8]; 13362 u8 reporting_qpn[0x18]; 13363 13364 u8 reserved_at_c0[0x18]; 13365 u8 num_ranges[0x8]; 13366 13367 u8 reserved_at_e0[0x20]; 13368 13369 u8 range_start_address[0x40]; 13370 13371 u8 length[0x40]; 13372 13373 struct mlx5_ifc_page_track_range_bits track_range[0]; 13374 }; 13375 13376 struct mlx5_ifc_create_page_track_obj_in_bits { 13377 struct mlx5_ifc_general_obj_in_cmd_hdr_bits general_obj_in_cmd_hdr; 13378 struct mlx5_ifc_page_track_bits obj_context; 13379 }; 13380 13381 struct mlx5_ifc_modify_page_track_obj_in_bits { 13382 struct mlx5_ifc_general_obj_in_cmd_hdr_bits general_obj_in_cmd_hdr; 13383 struct mlx5_ifc_page_track_bits obj_context; 13384 }; 13385 13386 struct mlx5_ifc_query_page_track_obj_out_bits { 13387 struct mlx5_ifc_general_obj_out_cmd_hdr_bits general_obj_out_cmd_hdr; 13388 struct mlx5_ifc_page_track_bits obj_context; 13389 }; 13390 13391 struct mlx5_ifc_msecq_reg_bits { 13392 u8 reserved_at_0[0x20]; 13393 13394 u8 reserved_at_20[0x12]; 13395 u8 network_option[0x2]; 13396 u8 local_ssm_code[0x4]; 13397 u8 local_enhanced_ssm_code[0x8]; 13398 13399 u8 local_clock_identity[0x40]; 13400 13401 u8 reserved_at_80[0x180]; 13402 }; 13403 13404 enum { 13405 MLX5_MSEES_FIELD_SELECT_ENABLE = BIT(0), 13406 MLX5_MSEES_FIELD_SELECT_ADMIN_STATUS = BIT(1), 13407 MLX5_MSEES_FIELD_SELECT_ADMIN_FREQ_MEASURE = BIT(2), 13408 }; 13409 13410 enum mlx5_msees_admin_status { 13411 MLX5_MSEES_ADMIN_STATUS_FREE_RUNNING = 0x0, 13412 MLX5_MSEES_ADMIN_STATUS_TRACK = 0x1, 13413 }; 13414 13415 enum mlx5_msees_oper_status { 13416 MLX5_MSEES_OPER_STATUS_FREE_RUNNING = 0x0, 13417 MLX5_MSEES_OPER_STATUS_SELF_TRACK = 0x1, 13418 MLX5_MSEES_OPER_STATUS_OTHER_TRACK = 0x2, 13419 MLX5_MSEES_OPER_STATUS_HOLDOVER = 0x3, 13420 MLX5_MSEES_OPER_STATUS_FAIL_HOLDOVER = 0x4, 13421 MLX5_MSEES_OPER_STATUS_FAIL_FREE_RUNNING = 0x5, 13422 }; 13423 13424 enum mlx5_msees_failure_reason { 13425 MLX5_MSEES_FAILURE_REASON_UNDEFINED_ERROR = 0x0, 13426 MLX5_MSEES_FAILURE_REASON_PORT_DOWN = 0x1, 13427 MLX5_MSEES_FAILURE_REASON_TOO_HIGH_FREQUENCY_DIFF = 0x2, 13428 MLX5_MSEES_FAILURE_REASON_NET_SYNCHRONIZER_DEVICE_ERROR = 0x3, 13429 MLX5_MSEES_FAILURE_REASON_LACK_OF_RESOURCES = 0x4, 13430 }; 13431 13432 struct mlx5_ifc_msees_reg_bits { 13433 u8 reserved_at_0[0x8]; 13434 u8 local_port[0x8]; 13435 u8 pnat[0x2]; 13436 u8 lp_msb[0x2]; 13437 u8 reserved_at_14[0xc]; 13438 13439 u8 field_select[0x20]; 13440 13441 u8 admin_status[0x4]; 13442 u8 oper_status[0x4]; 13443 u8 ho_acq[0x1]; 13444 u8 reserved_at_49[0xc]; 13445 u8 admin_freq_measure[0x1]; 13446 u8 oper_freq_measure[0x1]; 13447 u8 failure_reason[0x9]; 13448 13449 u8 frequency_diff[0x20]; 13450 13451 u8 reserved_at_80[0x180]; 13452 }; 13453 13454 struct mlx5_ifc_mrtcq_reg_bits { 13455 u8 reserved_at_0[0x40]; 13456 13457 u8 rt_clock_identity[0x40]; 13458 13459 u8 reserved_at_80[0x180]; 13460 }; 13461 13462 struct mlx5_ifc_pcie_cong_event_obj_bits { 13463 u8 modify_select_field[0x40]; 13464 13465 u8 inbound_event_en[0x1]; 13466 u8 outbound_event_en[0x1]; 13467 u8 reserved_at_42[0x1e]; 13468 13469 u8 reserved_at_60[0x1]; 13470 u8 inbound_cong_state[0x3]; 13471 u8 reserved_at_64[0x1]; 13472 u8 outbound_cong_state[0x3]; 13473 u8 reserved_at_68[0x18]; 13474 13475 u8 inbound_cong_low_threshold[0x10]; 13476 u8 inbound_cong_high_threshold[0x10]; 13477 13478 u8 outbound_cong_low_threshold[0x10]; 13479 u8 outbound_cong_high_threshold[0x10]; 13480 13481 u8 reserved_at_e0[0x340]; 13482 }; 13483 13484 struct mlx5_ifc_pcie_cong_event_cmd_in_bits { 13485 struct mlx5_ifc_general_obj_in_cmd_hdr_bits hdr; 13486 struct mlx5_ifc_pcie_cong_event_obj_bits cong_obj; 13487 }; 13488 13489 struct mlx5_ifc_pcie_cong_event_cmd_out_bits { 13490 struct mlx5_ifc_general_obj_out_cmd_hdr_bits hdr; 13491 struct mlx5_ifc_pcie_cong_event_obj_bits cong_obj; 13492 }; 13493 13494 enum mlx5e_pcie_cong_event_mod_field { 13495 MLX5_PCIE_CONG_EVENT_MOD_EVENT_EN = BIT(0), 13496 MLX5_PCIE_CONG_EVENT_MOD_THRESH = BIT(2), 13497 }; 13498 13499 #endif /* MLX5_IFC_H */ 13500