1 /* 2 * Copyright (c) 2013-2015, Mellanox Technologies, Ltd. All rights reserved. 3 * 4 * This software is available to you under a choice of one of two 5 * licenses. You may choose to be licensed under the terms of the GNU 6 * General Public License (GPL) Version 2, available from the file 7 * COPYING in the main directory of this source tree, or the 8 * OpenIB.org BSD license below: 9 * 10 * Redistribution and use in source and binary forms, with or 11 * without modification, are permitted provided that the following 12 * conditions are met: 13 * 14 * - Redistributions of source code must retain the above 15 * copyright notice, this list of conditions and the following 16 * disclaimer. 17 * 18 * - Redistributions in binary form must reproduce the above 19 * copyright notice, this list of conditions and the following 20 * disclaimer in the documentation and/or other materials 21 * provided with the distribution. 22 * 23 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, 24 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF 25 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND 26 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS 27 * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN 28 * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN 29 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE 30 * SOFTWARE. 31 */ 32 #ifndef MLX5_IFC_H 33 #define MLX5_IFC_H 34 35 #include "mlx5_ifc_fpga.h" 36 37 enum { 38 MLX5_EVENT_TYPE_CODING_COMPLETION_EVENTS = 0x0, 39 MLX5_EVENT_TYPE_CODING_PATH_MIGRATED_SUCCEEDED = 0x1, 40 MLX5_EVENT_TYPE_CODING_COMMUNICATION_ESTABLISHED = 0x2, 41 MLX5_EVENT_TYPE_CODING_SEND_QUEUE_DRAINED = 0x3, 42 MLX5_EVENT_TYPE_CODING_LAST_WQE_REACHED = 0x13, 43 MLX5_EVENT_TYPE_CODING_SRQ_LIMIT = 0x14, 44 MLX5_EVENT_TYPE_CODING_DCT_ALL_CONNECTIONS_CLOSED = 0x1c, 45 MLX5_EVENT_TYPE_CODING_DCT_ACCESS_KEY_VIOLATION = 0x1d, 46 MLX5_EVENT_TYPE_CODING_CQ_ERROR = 0x4, 47 MLX5_EVENT_TYPE_CODING_LOCAL_WQ_CATASTROPHIC_ERROR = 0x5, 48 MLX5_EVENT_TYPE_CODING_PATH_MIGRATION_FAILED = 0x7, 49 MLX5_EVENT_TYPE_CODING_PAGE_FAULT_EVENT = 0xc, 50 MLX5_EVENT_TYPE_CODING_INVALID_REQUEST_LOCAL_WQ_ERROR = 0x10, 51 MLX5_EVENT_TYPE_CODING_LOCAL_ACCESS_VIOLATION_WQ_ERROR = 0x11, 52 MLX5_EVENT_TYPE_CODING_LOCAL_SRQ_CATASTROPHIC_ERROR = 0x12, 53 MLX5_EVENT_TYPE_CODING_INTERNAL_ERROR = 0x8, 54 MLX5_EVENT_TYPE_CODING_PORT_STATE_CHANGE = 0x9, 55 MLX5_EVENT_TYPE_CODING_GPIO_EVENT = 0x15, 56 MLX5_EVENT_TYPE_CODING_REMOTE_CONFIGURATION_PROTOCOL_EVENT = 0x19, 57 MLX5_EVENT_TYPE_CODING_DOORBELL_BLUEFLAME_CONGESTION_EVENT = 0x1a, 58 MLX5_EVENT_TYPE_CODING_STALL_VL_EVENT = 0x1b, 59 MLX5_EVENT_TYPE_CODING_DROPPED_PACKET_LOGGED_EVENT = 0x1f, 60 MLX5_EVENT_TYPE_CODING_COMMAND_INTERFACE_COMPLETION = 0xa, 61 MLX5_EVENT_TYPE_CODING_PAGE_REQUEST = 0xb, 62 MLX5_EVENT_TYPE_CODING_FPGA_ERROR = 0x20, 63 MLX5_EVENT_TYPE_CODING_FPGA_QP_ERROR = 0x21 64 }; 65 66 enum { 67 MLX5_SET_HCA_CAP_OP_MOD_GENERAL_DEVICE = 0x0, 68 MLX5_SET_HCA_CAP_OP_MOD_ETHERNET_OFFLOADS = 0x1, 69 MLX5_SET_HCA_CAP_OP_MOD_ODP = 0x2, 70 MLX5_SET_HCA_CAP_OP_MOD_ATOMIC = 0x3, 71 MLX5_SET_HCA_CAP_OP_MOD_ROCE = 0x4, 72 MLX5_SET_HCA_CAP_OP_MOD_IPSEC = 0x15, 73 MLX5_SET_HCA_CAP_OP_MOD_GENERAL_DEVICE2 = 0x20, 74 MLX5_SET_HCA_CAP_OP_MOD_PORT_SELECTION = 0x25, 75 }; 76 77 enum { 78 MLX5_SHARED_RESOURCE_UID = 0xffff, 79 }; 80 81 enum { 82 MLX5_OBJ_TYPE_SW_ICM = 0x0008, 83 MLX5_OBJ_TYPE_GENEVE_TLV_OPT = 0x000b, 84 MLX5_OBJ_TYPE_VIRTIO_NET_Q = 0x000d, 85 MLX5_OBJ_TYPE_VIRTIO_Q_COUNTERS = 0x001c, 86 MLX5_OBJ_TYPE_MATCH_DEFINER = 0x0018, 87 MLX5_OBJ_TYPE_HEADER_MODIFY_ARGUMENT = 0x23, 88 MLX5_OBJ_TYPE_STC = 0x0040, 89 MLX5_OBJ_TYPE_RTC = 0x0041, 90 MLX5_OBJ_TYPE_STE = 0x0042, 91 MLX5_OBJ_TYPE_MODIFY_HDR_PATTERN = 0x0043, 92 MLX5_OBJ_TYPE_PAGE_TRACK = 0x46, 93 MLX5_OBJ_TYPE_MKEY = 0xff01, 94 MLX5_OBJ_TYPE_QP = 0xff02, 95 MLX5_OBJ_TYPE_PSV = 0xff03, 96 MLX5_OBJ_TYPE_RMP = 0xff04, 97 MLX5_OBJ_TYPE_XRC_SRQ = 0xff05, 98 MLX5_OBJ_TYPE_RQ = 0xff06, 99 MLX5_OBJ_TYPE_SQ = 0xff07, 100 MLX5_OBJ_TYPE_TIR = 0xff08, 101 MLX5_OBJ_TYPE_TIS = 0xff09, 102 MLX5_OBJ_TYPE_DCT = 0xff0a, 103 MLX5_OBJ_TYPE_XRQ = 0xff0b, 104 MLX5_OBJ_TYPE_RQT = 0xff0e, 105 MLX5_OBJ_TYPE_FLOW_COUNTER = 0xff0f, 106 MLX5_OBJ_TYPE_CQ = 0xff10, 107 MLX5_OBJ_TYPE_FT_ALIAS = 0xff15, 108 }; 109 110 enum { 111 MLX5_GENERAL_OBJ_TYPES_CAP_SW_ICM = (1ULL << MLX5_OBJ_TYPE_SW_ICM), 112 MLX5_GENERAL_OBJ_TYPES_CAP_GENEVE_TLV_OPT = (1ULL << 11), 113 MLX5_GENERAL_OBJ_TYPES_CAP_VIRTIO_NET_Q = (1ULL << 13), 114 MLX5_GENERAL_OBJ_TYPES_CAP_HEADER_MODIFY_ARGUMENT = 115 (1ULL << MLX5_OBJ_TYPE_HEADER_MODIFY_ARGUMENT), 116 MLX5_GENERAL_OBJ_TYPES_CAP_MACSEC_OFFLOAD = (1ULL << 39), 117 }; 118 119 enum { 120 MLX5_CMD_OP_QUERY_HCA_CAP = 0x100, 121 MLX5_CMD_OP_QUERY_ADAPTER = 0x101, 122 MLX5_CMD_OP_INIT_HCA = 0x102, 123 MLX5_CMD_OP_TEARDOWN_HCA = 0x103, 124 MLX5_CMD_OP_ENABLE_HCA = 0x104, 125 MLX5_CMD_OP_DISABLE_HCA = 0x105, 126 MLX5_CMD_OP_QUERY_PAGES = 0x107, 127 MLX5_CMD_OP_MANAGE_PAGES = 0x108, 128 MLX5_CMD_OP_SET_HCA_CAP = 0x109, 129 MLX5_CMD_OP_QUERY_ISSI = 0x10a, 130 MLX5_CMD_OP_SET_ISSI = 0x10b, 131 MLX5_CMD_OP_SET_DRIVER_VERSION = 0x10d, 132 MLX5_CMD_OP_QUERY_SF_PARTITION = 0x111, 133 MLX5_CMD_OP_ALLOC_SF = 0x113, 134 MLX5_CMD_OP_DEALLOC_SF = 0x114, 135 MLX5_CMD_OP_SUSPEND_VHCA = 0x115, 136 MLX5_CMD_OP_RESUME_VHCA = 0x116, 137 MLX5_CMD_OP_QUERY_VHCA_MIGRATION_STATE = 0x117, 138 MLX5_CMD_OP_SAVE_VHCA_STATE = 0x118, 139 MLX5_CMD_OP_LOAD_VHCA_STATE = 0x119, 140 MLX5_CMD_OP_CREATE_MKEY = 0x200, 141 MLX5_CMD_OP_QUERY_MKEY = 0x201, 142 MLX5_CMD_OP_DESTROY_MKEY = 0x202, 143 MLX5_CMD_OP_QUERY_SPECIAL_CONTEXTS = 0x203, 144 MLX5_CMD_OP_PAGE_FAULT_RESUME = 0x204, 145 MLX5_CMD_OP_ALLOC_MEMIC = 0x205, 146 MLX5_CMD_OP_DEALLOC_MEMIC = 0x206, 147 MLX5_CMD_OP_MODIFY_MEMIC = 0x207, 148 MLX5_CMD_OP_CREATE_EQ = 0x301, 149 MLX5_CMD_OP_DESTROY_EQ = 0x302, 150 MLX5_CMD_OP_QUERY_EQ = 0x303, 151 MLX5_CMD_OP_GEN_EQE = 0x304, 152 MLX5_CMD_OP_CREATE_CQ = 0x400, 153 MLX5_CMD_OP_DESTROY_CQ = 0x401, 154 MLX5_CMD_OP_QUERY_CQ = 0x402, 155 MLX5_CMD_OP_MODIFY_CQ = 0x403, 156 MLX5_CMD_OP_CREATE_QP = 0x500, 157 MLX5_CMD_OP_DESTROY_QP = 0x501, 158 MLX5_CMD_OP_RST2INIT_QP = 0x502, 159 MLX5_CMD_OP_INIT2RTR_QP = 0x503, 160 MLX5_CMD_OP_RTR2RTS_QP = 0x504, 161 MLX5_CMD_OP_RTS2RTS_QP = 0x505, 162 MLX5_CMD_OP_SQERR2RTS_QP = 0x506, 163 MLX5_CMD_OP_2ERR_QP = 0x507, 164 MLX5_CMD_OP_2RST_QP = 0x50a, 165 MLX5_CMD_OP_QUERY_QP = 0x50b, 166 MLX5_CMD_OP_SQD_RTS_QP = 0x50c, 167 MLX5_CMD_OP_INIT2INIT_QP = 0x50e, 168 MLX5_CMD_OP_CREATE_PSV = 0x600, 169 MLX5_CMD_OP_DESTROY_PSV = 0x601, 170 MLX5_CMD_OP_CREATE_SRQ = 0x700, 171 MLX5_CMD_OP_DESTROY_SRQ = 0x701, 172 MLX5_CMD_OP_QUERY_SRQ = 0x702, 173 MLX5_CMD_OP_ARM_RQ = 0x703, 174 MLX5_CMD_OP_CREATE_XRC_SRQ = 0x705, 175 MLX5_CMD_OP_DESTROY_XRC_SRQ = 0x706, 176 MLX5_CMD_OP_QUERY_XRC_SRQ = 0x707, 177 MLX5_CMD_OP_ARM_XRC_SRQ = 0x708, 178 MLX5_CMD_OP_CREATE_DCT = 0x710, 179 MLX5_CMD_OP_DESTROY_DCT = 0x711, 180 MLX5_CMD_OP_DRAIN_DCT = 0x712, 181 MLX5_CMD_OP_QUERY_DCT = 0x713, 182 MLX5_CMD_OP_ARM_DCT_FOR_KEY_VIOLATION = 0x714, 183 MLX5_CMD_OP_CREATE_XRQ = 0x717, 184 MLX5_CMD_OP_DESTROY_XRQ = 0x718, 185 MLX5_CMD_OP_QUERY_XRQ = 0x719, 186 MLX5_CMD_OP_ARM_XRQ = 0x71a, 187 MLX5_CMD_OP_QUERY_XRQ_DC_PARAMS_ENTRY = 0x725, 188 MLX5_CMD_OP_SET_XRQ_DC_PARAMS_ENTRY = 0x726, 189 MLX5_CMD_OP_QUERY_XRQ_ERROR_PARAMS = 0x727, 190 MLX5_CMD_OP_RELEASE_XRQ_ERROR = 0x729, 191 MLX5_CMD_OP_MODIFY_XRQ = 0x72a, 192 MLX5_CMD_OPCODE_QUERY_DELEGATED_VHCA = 0x732, 193 MLX5_CMD_OPCODE_CREATE_ESW_VPORT = 0x733, 194 MLX5_CMD_OPCODE_DESTROY_ESW_VPORT = 0x734, 195 MLX5_CMD_OP_QUERY_ESW_FUNCTIONS = 0x740, 196 MLX5_CMD_OP_QUERY_VPORT_STATE = 0x750, 197 MLX5_CMD_OP_MODIFY_VPORT_STATE = 0x751, 198 MLX5_CMD_OP_QUERY_ESW_VPORT_CONTEXT = 0x752, 199 MLX5_CMD_OP_MODIFY_ESW_VPORT_CONTEXT = 0x753, 200 MLX5_CMD_OP_QUERY_NIC_VPORT_CONTEXT = 0x754, 201 MLX5_CMD_OP_MODIFY_NIC_VPORT_CONTEXT = 0x755, 202 MLX5_CMD_OP_QUERY_ROCE_ADDRESS = 0x760, 203 MLX5_CMD_OP_SET_ROCE_ADDRESS = 0x761, 204 MLX5_CMD_OP_QUERY_HCA_VPORT_CONTEXT = 0x762, 205 MLX5_CMD_OP_MODIFY_HCA_VPORT_CONTEXT = 0x763, 206 MLX5_CMD_OP_QUERY_HCA_VPORT_GID = 0x764, 207 MLX5_CMD_OP_QUERY_HCA_VPORT_PKEY = 0x765, 208 MLX5_CMD_OP_QUERY_VNIC_ENV = 0x76f, 209 MLX5_CMD_OP_QUERY_VPORT_COUNTER = 0x770, 210 MLX5_CMD_OP_ALLOC_Q_COUNTER = 0x771, 211 MLX5_CMD_OP_DEALLOC_Q_COUNTER = 0x772, 212 MLX5_CMD_OP_QUERY_Q_COUNTER = 0x773, 213 MLX5_CMD_OP_SET_MONITOR_COUNTER = 0x774, 214 MLX5_CMD_OP_ARM_MONITOR_COUNTER = 0x775, 215 MLX5_CMD_OP_SET_PP_RATE_LIMIT = 0x780, 216 MLX5_CMD_OP_QUERY_RATE_LIMIT = 0x781, 217 MLX5_CMD_OP_CREATE_SCHEDULING_ELEMENT = 0x782, 218 MLX5_CMD_OP_DESTROY_SCHEDULING_ELEMENT = 0x783, 219 MLX5_CMD_OP_QUERY_SCHEDULING_ELEMENT = 0x784, 220 MLX5_CMD_OP_MODIFY_SCHEDULING_ELEMENT = 0x785, 221 MLX5_CMD_OP_CREATE_QOS_PARA_VPORT = 0x786, 222 MLX5_CMD_OP_DESTROY_QOS_PARA_VPORT = 0x787, 223 MLX5_CMD_OP_ALLOC_PD = 0x800, 224 MLX5_CMD_OP_DEALLOC_PD = 0x801, 225 MLX5_CMD_OP_ALLOC_UAR = 0x802, 226 MLX5_CMD_OP_DEALLOC_UAR = 0x803, 227 MLX5_CMD_OP_CONFIG_INT_MODERATION = 0x804, 228 MLX5_CMD_OP_ACCESS_REG = 0x805, 229 MLX5_CMD_OP_ATTACH_TO_MCG = 0x806, 230 MLX5_CMD_OP_DETACH_FROM_MCG = 0x807, 231 MLX5_CMD_OP_GET_DROPPED_PACKET_LOG = 0x80a, 232 MLX5_CMD_OP_MAD_IFC = 0x50d, 233 MLX5_CMD_OP_QUERY_MAD_DEMUX = 0x80b, 234 MLX5_CMD_OP_SET_MAD_DEMUX = 0x80c, 235 MLX5_CMD_OP_NOP = 0x80d, 236 MLX5_CMD_OP_ALLOC_XRCD = 0x80e, 237 MLX5_CMD_OP_DEALLOC_XRCD = 0x80f, 238 MLX5_CMD_OP_ALLOC_TRANSPORT_DOMAIN = 0x816, 239 MLX5_CMD_OP_DEALLOC_TRANSPORT_DOMAIN = 0x817, 240 MLX5_CMD_OP_QUERY_CONG_STATUS = 0x822, 241 MLX5_CMD_OP_MODIFY_CONG_STATUS = 0x823, 242 MLX5_CMD_OP_QUERY_CONG_PARAMS = 0x824, 243 MLX5_CMD_OP_MODIFY_CONG_PARAMS = 0x825, 244 MLX5_CMD_OP_QUERY_CONG_STATISTICS = 0x826, 245 MLX5_CMD_OP_ADD_VXLAN_UDP_DPORT = 0x827, 246 MLX5_CMD_OP_DELETE_VXLAN_UDP_DPORT = 0x828, 247 MLX5_CMD_OP_SET_L2_TABLE_ENTRY = 0x829, 248 MLX5_CMD_OP_QUERY_L2_TABLE_ENTRY = 0x82a, 249 MLX5_CMD_OP_DELETE_L2_TABLE_ENTRY = 0x82b, 250 MLX5_CMD_OP_SET_WOL_ROL = 0x830, 251 MLX5_CMD_OP_QUERY_WOL_ROL = 0x831, 252 MLX5_CMD_OP_CREATE_LAG = 0x840, 253 MLX5_CMD_OP_MODIFY_LAG = 0x841, 254 MLX5_CMD_OP_QUERY_LAG = 0x842, 255 MLX5_CMD_OP_DESTROY_LAG = 0x843, 256 MLX5_CMD_OP_CREATE_VPORT_LAG = 0x844, 257 MLX5_CMD_OP_DESTROY_VPORT_LAG = 0x845, 258 MLX5_CMD_OP_CREATE_TIR = 0x900, 259 MLX5_CMD_OP_MODIFY_TIR = 0x901, 260 MLX5_CMD_OP_DESTROY_TIR = 0x902, 261 MLX5_CMD_OP_QUERY_TIR = 0x903, 262 MLX5_CMD_OP_CREATE_SQ = 0x904, 263 MLX5_CMD_OP_MODIFY_SQ = 0x905, 264 MLX5_CMD_OP_DESTROY_SQ = 0x906, 265 MLX5_CMD_OP_QUERY_SQ = 0x907, 266 MLX5_CMD_OP_CREATE_RQ = 0x908, 267 MLX5_CMD_OP_MODIFY_RQ = 0x909, 268 MLX5_CMD_OP_SET_DELAY_DROP_PARAMS = 0x910, 269 MLX5_CMD_OP_DESTROY_RQ = 0x90a, 270 MLX5_CMD_OP_QUERY_RQ = 0x90b, 271 MLX5_CMD_OP_CREATE_RMP = 0x90c, 272 MLX5_CMD_OP_MODIFY_RMP = 0x90d, 273 MLX5_CMD_OP_DESTROY_RMP = 0x90e, 274 MLX5_CMD_OP_QUERY_RMP = 0x90f, 275 MLX5_CMD_OP_CREATE_TIS = 0x912, 276 MLX5_CMD_OP_MODIFY_TIS = 0x913, 277 MLX5_CMD_OP_DESTROY_TIS = 0x914, 278 MLX5_CMD_OP_QUERY_TIS = 0x915, 279 MLX5_CMD_OP_CREATE_RQT = 0x916, 280 MLX5_CMD_OP_MODIFY_RQT = 0x917, 281 MLX5_CMD_OP_DESTROY_RQT = 0x918, 282 MLX5_CMD_OP_QUERY_RQT = 0x919, 283 MLX5_CMD_OP_SET_FLOW_TABLE_ROOT = 0x92f, 284 MLX5_CMD_OP_CREATE_FLOW_TABLE = 0x930, 285 MLX5_CMD_OP_DESTROY_FLOW_TABLE = 0x931, 286 MLX5_CMD_OP_QUERY_FLOW_TABLE = 0x932, 287 MLX5_CMD_OP_CREATE_FLOW_GROUP = 0x933, 288 MLX5_CMD_OP_DESTROY_FLOW_GROUP = 0x934, 289 MLX5_CMD_OP_QUERY_FLOW_GROUP = 0x935, 290 MLX5_CMD_OP_SET_FLOW_TABLE_ENTRY = 0x936, 291 MLX5_CMD_OP_QUERY_FLOW_TABLE_ENTRY = 0x937, 292 MLX5_CMD_OP_DELETE_FLOW_TABLE_ENTRY = 0x938, 293 MLX5_CMD_OP_ALLOC_FLOW_COUNTER = 0x939, 294 MLX5_CMD_OP_DEALLOC_FLOW_COUNTER = 0x93a, 295 MLX5_CMD_OP_QUERY_FLOW_COUNTER = 0x93b, 296 MLX5_CMD_OP_MODIFY_FLOW_TABLE = 0x93c, 297 MLX5_CMD_OP_ALLOC_PACKET_REFORMAT_CONTEXT = 0x93d, 298 MLX5_CMD_OP_DEALLOC_PACKET_REFORMAT_CONTEXT = 0x93e, 299 MLX5_CMD_OP_QUERY_PACKET_REFORMAT_CONTEXT = 0x93f, 300 MLX5_CMD_OP_ALLOC_MODIFY_HEADER_CONTEXT = 0x940, 301 MLX5_CMD_OP_DEALLOC_MODIFY_HEADER_CONTEXT = 0x941, 302 MLX5_CMD_OP_QUERY_MODIFY_HEADER_CONTEXT = 0x942, 303 MLX5_CMD_OP_FPGA_CREATE_QP = 0x960, 304 MLX5_CMD_OP_FPGA_MODIFY_QP = 0x961, 305 MLX5_CMD_OP_FPGA_QUERY_QP = 0x962, 306 MLX5_CMD_OP_FPGA_DESTROY_QP = 0x963, 307 MLX5_CMD_OP_FPGA_QUERY_QP_COUNTERS = 0x964, 308 MLX5_CMD_OP_CREATE_GENERAL_OBJECT = 0xa00, 309 MLX5_CMD_OP_MODIFY_GENERAL_OBJECT = 0xa01, 310 MLX5_CMD_OP_QUERY_GENERAL_OBJECT = 0xa02, 311 MLX5_CMD_OP_DESTROY_GENERAL_OBJECT = 0xa03, 312 MLX5_CMD_OP_CREATE_UCTX = 0xa04, 313 MLX5_CMD_OP_DESTROY_UCTX = 0xa06, 314 MLX5_CMD_OP_CREATE_UMEM = 0xa08, 315 MLX5_CMD_OP_DESTROY_UMEM = 0xa0a, 316 MLX5_CMD_OP_SYNC_STEERING = 0xb00, 317 MLX5_CMD_OP_PSP_GEN_SPI = 0xb10, 318 MLX5_CMD_OP_PSP_ROTATE_KEY = 0xb11, 319 MLX5_CMD_OP_QUERY_VHCA_STATE = 0xb0d, 320 MLX5_CMD_OP_MODIFY_VHCA_STATE = 0xb0e, 321 MLX5_CMD_OP_SYNC_CRYPTO = 0xb12, 322 MLX5_CMD_OP_ALLOW_OTHER_VHCA_ACCESS = 0xb16, 323 MLX5_CMD_OP_GENERATE_WQE = 0xb17, 324 MLX5_CMD_OPCODE_QUERY_VUID = 0xb22, 325 MLX5_CMD_OP_MAX 326 }; 327 328 /* Valid range for general commands that don't work over an object */ 329 enum { 330 MLX5_CMD_OP_GENERAL_START = 0xb00, 331 MLX5_CMD_OP_GENERAL_END = 0xd00, 332 }; 333 334 enum { 335 MLX5_FT_NIC_RX_2_NIC_RX_RDMA = BIT(0), 336 MLX5_FT_NIC_TX_RDMA_2_NIC_TX = BIT(1), 337 }; 338 339 enum { 340 MLX5_CMD_OP_MOD_UPDATE_HEADER_MODIFY_ARGUMENT = 0x1, 341 }; 342 343 struct mlx5_ifc_flow_table_fields_supported_bits { 344 u8 outer_dmac[0x1]; 345 u8 outer_smac[0x1]; 346 u8 outer_ether_type[0x1]; 347 u8 outer_ip_version[0x1]; 348 u8 outer_first_prio[0x1]; 349 u8 outer_first_cfi[0x1]; 350 u8 outer_first_vid[0x1]; 351 u8 outer_ipv4_ttl[0x1]; 352 u8 outer_second_prio[0x1]; 353 u8 outer_second_cfi[0x1]; 354 u8 outer_second_vid[0x1]; 355 u8 reserved_at_b[0x1]; 356 u8 outer_sip[0x1]; 357 u8 outer_dip[0x1]; 358 u8 outer_frag[0x1]; 359 u8 outer_ip_protocol[0x1]; 360 u8 outer_ip_ecn[0x1]; 361 u8 outer_ip_dscp[0x1]; 362 u8 outer_udp_sport[0x1]; 363 u8 outer_udp_dport[0x1]; 364 u8 outer_tcp_sport[0x1]; 365 u8 outer_tcp_dport[0x1]; 366 u8 outer_tcp_flags[0x1]; 367 u8 outer_gre_protocol[0x1]; 368 u8 outer_gre_key[0x1]; 369 u8 outer_vxlan_vni[0x1]; 370 u8 outer_geneve_vni[0x1]; 371 u8 outer_geneve_oam[0x1]; 372 u8 outer_geneve_protocol_type[0x1]; 373 u8 outer_geneve_opt_len[0x1]; 374 u8 source_vhca_port[0x1]; 375 u8 source_eswitch_port[0x1]; 376 377 u8 inner_dmac[0x1]; 378 u8 inner_smac[0x1]; 379 u8 inner_ether_type[0x1]; 380 u8 inner_ip_version[0x1]; 381 u8 inner_first_prio[0x1]; 382 u8 inner_first_cfi[0x1]; 383 u8 inner_first_vid[0x1]; 384 u8 reserved_at_27[0x1]; 385 u8 inner_second_prio[0x1]; 386 u8 inner_second_cfi[0x1]; 387 u8 inner_second_vid[0x1]; 388 u8 reserved_at_2b[0x1]; 389 u8 inner_sip[0x1]; 390 u8 inner_dip[0x1]; 391 u8 inner_frag[0x1]; 392 u8 inner_ip_protocol[0x1]; 393 u8 inner_ip_ecn[0x1]; 394 u8 inner_ip_dscp[0x1]; 395 u8 inner_udp_sport[0x1]; 396 u8 inner_udp_dport[0x1]; 397 u8 inner_tcp_sport[0x1]; 398 u8 inner_tcp_dport[0x1]; 399 u8 inner_tcp_flags[0x1]; 400 u8 reserved_at_37[0x9]; 401 402 u8 geneve_tlv_option_0_data[0x1]; 403 u8 geneve_tlv_option_0_exist[0x1]; 404 u8 reserved_at_42[0x3]; 405 u8 outer_first_mpls_over_udp[0x4]; 406 u8 outer_first_mpls_over_gre[0x4]; 407 u8 inner_first_mpls[0x4]; 408 u8 outer_first_mpls[0x4]; 409 u8 reserved_at_55[0x2]; 410 u8 outer_esp_spi[0x1]; 411 u8 reserved_at_58[0x2]; 412 u8 bth_dst_qp[0x1]; 413 u8 reserved_at_5b[0x5]; 414 415 u8 reserved_at_60[0x18]; 416 u8 metadata_reg_c_7[0x1]; 417 u8 metadata_reg_c_6[0x1]; 418 u8 metadata_reg_c_5[0x1]; 419 u8 metadata_reg_c_4[0x1]; 420 u8 metadata_reg_c_3[0x1]; 421 u8 metadata_reg_c_2[0x1]; 422 u8 metadata_reg_c_1[0x1]; 423 u8 metadata_reg_c_0[0x1]; 424 }; 425 426 /* Table 2170 - Flow Table Fields Supported 2 Format */ 427 struct mlx5_ifc_flow_table_fields_supported_2_bits { 428 u8 inner_l4_type_ext[0x1]; 429 u8 outer_l4_type_ext[0x1]; 430 u8 inner_l4_type[0x1]; 431 u8 outer_l4_type[0x1]; 432 u8 reserved_at_4[0xa]; 433 u8 bth_opcode[0x1]; 434 u8 reserved_at_f[0x1]; 435 u8 tunnel_header_0_1[0x1]; 436 u8 reserved_at_11[0xf]; 437 438 u8 reserved_at_20[0xf]; 439 u8 ipsec_next_header[0x1]; 440 u8 reserved_at_30[0x10]; 441 442 u8 reserved_at_40[0x40]; 443 }; 444 445 struct mlx5_ifc_flow_table_prop_layout_bits { 446 u8 ft_support[0x1]; 447 u8 reserved_at_1[0x1]; 448 u8 flow_counter[0x1]; 449 u8 flow_modify_en[0x1]; 450 u8 modify_root[0x1]; 451 u8 identified_miss_table_mode[0x1]; 452 u8 flow_table_modify[0x1]; 453 u8 reformat[0x1]; 454 u8 decap[0x1]; 455 u8 reset_root_to_default[0x1]; 456 u8 pop_vlan[0x1]; 457 u8 push_vlan[0x1]; 458 u8 reserved_at_c[0x1]; 459 u8 pop_vlan_2[0x1]; 460 u8 push_vlan_2[0x1]; 461 u8 reformat_and_vlan_action[0x1]; 462 u8 reserved_at_10[0x1]; 463 u8 sw_owner[0x1]; 464 u8 reformat_l3_tunnel_to_l2[0x1]; 465 u8 reformat_l2_to_l3_tunnel[0x1]; 466 u8 reformat_and_modify_action[0x1]; 467 u8 ignore_flow_level[0x1]; 468 u8 reserved_at_16[0x1]; 469 u8 table_miss_action_domain[0x1]; 470 u8 termination_table[0x1]; 471 u8 reformat_and_fwd_to_table[0x1]; 472 u8 forward_vhca_rx[0x1]; 473 u8 reserved_at_1b[0x1]; 474 u8 ipsec_encrypt[0x1]; 475 u8 ipsec_decrypt[0x1]; 476 u8 sw_owner_v2[0x1]; 477 u8 reserved_at_1f[0x1]; 478 479 u8 termination_table_raw_traffic[0x1]; 480 u8 reserved_at_21[0x1]; 481 u8 log_max_ft_size[0x6]; 482 u8 log_max_modify_header_context[0x8]; 483 u8 max_modify_header_actions[0x8]; 484 u8 max_ft_level[0x8]; 485 486 u8 reformat_add_esp_trasport[0x1]; 487 u8 reformat_l2_to_l3_esp_tunnel[0x1]; 488 u8 reformat_add_esp_transport_over_udp[0x1]; 489 u8 reformat_del_esp_trasport[0x1]; 490 u8 reformat_l3_esp_tunnel_to_l2[0x1]; 491 u8 reformat_del_esp_transport_over_udp[0x1]; 492 u8 execute_aso[0x1]; 493 u8 reserved_at_47[0x19]; 494 495 u8 reformat_l2_to_l3_psp_tunnel[0x1]; 496 u8 reformat_l3_psp_tunnel_to_l2[0x1]; 497 u8 reformat_insert[0x1]; 498 u8 reformat_remove[0x1]; 499 u8 macsec_encrypt[0x1]; 500 u8 macsec_decrypt[0x1]; 501 u8 psp_encrypt[0x1]; 502 u8 psp_decrypt[0x1]; 503 u8 reformat_add_macsec[0x1]; 504 u8 reformat_remove_macsec[0x1]; 505 u8 reparse[0x1]; 506 u8 reserved_at_6b[0x1]; 507 u8 cross_vhca_object[0x1]; 508 u8 reformat_l2_to_l3_audp_tunnel[0x1]; 509 u8 reformat_l3_audp_tunnel_to_l2[0x1]; 510 u8 ignore_flow_level_rtc_valid[0x1]; 511 u8 reserved_at_70[0x7]; 512 u8 reformat_del_psp_transport[0x1]; 513 u8 log_max_ft_num[0x8]; 514 515 u8 reserved_at_80[0x10]; 516 u8 log_max_flow_counter[0x8]; 517 u8 log_max_destination[0x8]; 518 519 u8 reserved_at_a0[0x18]; 520 u8 log_max_flow[0x8]; 521 522 u8 reserved_at_c0[0x40]; 523 524 struct mlx5_ifc_flow_table_fields_supported_bits ft_field_support; 525 526 struct mlx5_ifc_flow_table_fields_supported_bits ft_field_bitmask_support; 527 }; 528 529 struct mlx5_ifc_odp_per_transport_service_cap_bits { 530 u8 send[0x1]; 531 u8 receive[0x1]; 532 u8 write[0x1]; 533 u8 read[0x1]; 534 u8 atomic[0x1]; 535 u8 srq_receive[0x1]; 536 u8 reserved_at_6[0x1a]; 537 }; 538 539 struct mlx5_ifc_ipv4_layout_bits { 540 u8 reserved_at_0[0x60]; 541 542 u8 ipv4[0x20]; 543 }; 544 545 struct mlx5_ifc_ipv6_layout_bits { 546 u8 ipv6[16][0x8]; 547 }; 548 549 struct mlx5_ifc_ipv6_simple_layout_bits { 550 u8 ipv6_127_96[0x20]; 551 u8 ipv6_95_64[0x20]; 552 u8 ipv6_63_32[0x20]; 553 u8 ipv6_31_0[0x20]; 554 }; 555 556 union mlx5_ifc_ipv6_layout_ipv4_layout_auto_bits { 557 struct mlx5_ifc_ipv6_simple_layout_bits ipv6_simple_layout; 558 struct mlx5_ifc_ipv6_layout_bits ipv6_layout; 559 struct mlx5_ifc_ipv4_layout_bits ipv4_layout; 560 u8 reserved_at_0[0x80]; 561 }; 562 563 enum { 564 MLX5_PACKET_L4_TYPE_NONE, 565 MLX5_PACKET_L4_TYPE_TCP, 566 MLX5_PACKET_L4_TYPE_UDP, 567 }; 568 569 enum { 570 MLX5_PACKET_L4_TYPE_EXT_NONE, 571 MLX5_PACKET_L4_TYPE_EXT_TCP, 572 MLX5_PACKET_L4_TYPE_EXT_UDP, 573 MLX5_PACKET_L4_TYPE_EXT_ICMP, 574 }; 575 576 struct mlx5_ifc_fte_match_set_lyr_2_4_bits { 577 u8 smac_47_16[0x20]; 578 579 u8 smac_15_0[0x10]; 580 u8 ethertype[0x10]; 581 582 u8 dmac_47_16[0x20]; 583 584 u8 dmac_15_0[0x10]; 585 u8 first_prio[0x3]; 586 u8 first_cfi[0x1]; 587 u8 first_vid[0xc]; 588 589 u8 ip_protocol[0x8]; 590 u8 ip_dscp[0x6]; 591 u8 ip_ecn[0x2]; 592 u8 cvlan_tag[0x1]; 593 u8 svlan_tag[0x1]; 594 u8 frag[0x1]; 595 u8 ip_version[0x4]; 596 u8 tcp_flags[0x9]; 597 598 u8 tcp_sport[0x10]; 599 u8 tcp_dport[0x10]; 600 601 u8 l4_type[0x2]; 602 u8 l4_type_ext[0x4]; 603 u8 reserved_at_c6[0xa]; 604 u8 ipv4_ihl[0x4]; 605 u8 reserved_at_d4[0x4]; 606 u8 ttl_hoplimit[0x8]; 607 608 u8 udp_sport[0x10]; 609 u8 udp_dport[0x10]; 610 611 union mlx5_ifc_ipv6_layout_ipv4_layout_auto_bits src_ipv4_src_ipv6; 612 613 union mlx5_ifc_ipv6_layout_ipv4_layout_auto_bits dst_ipv4_dst_ipv6; 614 }; 615 616 struct mlx5_ifc_nvgre_key_bits { 617 u8 hi[0x18]; 618 u8 lo[0x8]; 619 }; 620 621 union mlx5_ifc_gre_key_bits { 622 struct mlx5_ifc_nvgre_key_bits nvgre; 623 u8 key[0x20]; 624 }; 625 626 struct mlx5_ifc_fte_match_set_misc_bits { 627 u8 gre_c_present[0x1]; 628 u8 reserved_at_1[0x1]; 629 u8 gre_k_present[0x1]; 630 u8 gre_s_present[0x1]; 631 u8 source_vhca_port[0x4]; 632 u8 source_sqn[0x18]; 633 634 u8 source_eswitch_owner_vhca_id[0x10]; 635 u8 source_port[0x10]; 636 637 u8 outer_second_prio[0x3]; 638 u8 outer_second_cfi[0x1]; 639 u8 outer_second_vid[0xc]; 640 u8 inner_second_prio[0x3]; 641 u8 inner_second_cfi[0x1]; 642 u8 inner_second_vid[0xc]; 643 644 u8 outer_second_cvlan_tag[0x1]; 645 u8 inner_second_cvlan_tag[0x1]; 646 u8 outer_second_svlan_tag[0x1]; 647 u8 inner_second_svlan_tag[0x1]; 648 u8 reserved_at_64[0xc]; 649 u8 gre_protocol[0x10]; 650 651 union mlx5_ifc_gre_key_bits gre_key; 652 653 u8 vxlan_vni[0x18]; 654 u8 bth_opcode[0x8]; 655 656 u8 geneve_vni[0x18]; 657 u8 reserved_at_d8[0x6]; 658 u8 geneve_tlv_option_0_exist[0x1]; 659 u8 geneve_oam[0x1]; 660 661 u8 reserved_at_e0[0xc]; 662 u8 outer_ipv6_flow_label[0x14]; 663 664 u8 reserved_at_100[0xc]; 665 u8 inner_ipv6_flow_label[0x14]; 666 667 u8 reserved_at_120[0xa]; 668 u8 geneve_opt_len[0x6]; 669 u8 geneve_protocol_type[0x10]; 670 671 u8 reserved_at_140[0x8]; 672 u8 bth_dst_qp[0x18]; 673 u8 inner_esp_spi[0x20]; 674 u8 outer_esp_spi[0x20]; 675 u8 reserved_at_1a0[0x60]; 676 }; 677 678 struct mlx5_ifc_fte_match_mpls_bits { 679 u8 mpls_label[0x14]; 680 u8 mpls_exp[0x3]; 681 u8 mpls_s_bos[0x1]; 682 u8 mpls_ttl[0x8]; 683 }; 684 685 struct mlx5_ifc_fte_match_set_misc2_bits { 686 struct mlx5_ifc_fte_match_mpls_bits outer_first_mpls; 687 688 struct mlx5_ifc_fte_match_mpls_bits inner_first_mpls; 689 690 struct mlx5_ifc_fte_match_mpls_bits outer_first_mpls_over_gre; 691 692 struct mlx5_ifc_fte_match_mpls_bits outer_first_mpls_over_udp; 693 694 u8 metadata_reg_c_7[0x20]; 695 696 u8 metadata_reg_c_6[0x20]; 697 698 u8 metadata_reg_c_5[0x20]; 699 700 u8 metadata_reg_c_4[0x20]; 701 702 u8 metadata_reg_c_3[0x20]; 703 704 u8 metadata_reg_c_2[0x20]; 705 706 u8 metadata_reg_c_1[0x20]; 707 708 u8 metadata_reg_c_0[0x20]; 709 710 u8 metadata_reg_a[0x20]; 711 712 u8 psp_syndrome[0x8]; 713 u8 macsec_syndrome[0x8]; 714 u8 ipsec_syndrome[0x8]; 715 u8 ipsec_next_header[0x8]; 716 717 u8 reserved_at_1c0[0x40]; 718 }; 719 720 struct mlx5_ifc_fte_match_set_misc3_bits { 721 u8 inner_tcp_seq_num[0x20]; 722 723 u8 outer_tcp_seq_num[0x20]; 724 725 u8 inner_tcp_ack_num[0x20]; 726 727 u8 outer_tcp_ack_num[0x20]; 728 729 u8 reserved_at_80[0x8]; 730 u8 outer_vxlan_gpe_vni[0x18]; 731 732 u8 outer_vxlan_gpe_next_protocol[0x8]; 733 u8 outer_vxlan_gpe_flags[0x8]; 734 u8 reserved_at_b0[0x10]; 735 736 u8 icmp_header_data[0x20]; 737 738 u8 icmpv6_header_data[0x20]; 739 740 u8 icmp_type[0x8]; 741 u8 icmp_code[0x8]; 742 u8 icmpv6_type[0x8]; 743 u8 icmpv6_code[0x8]; 744 745 u8 geneve_tlv_option_0_data[0x20]; 746 747 u8 gtpu_teid[0x20]; 748 749 u8 gtpu_msg_type[0x8]; 750 u8 gtpu_msg_flags[0x8]; 751 u8 reserved_at_170[0x10]; 752 753 u8 gtpu_dw_2[0x20]; 754 755 u8 gtpu_first_ext_dw_0[0x20]; 756 757 u8 gtpu_dw_0[0x20]; 758 759 u8 reserved_at_1e0[0x20]; 760 }; 761 762 struct mlx5_ifc_fte_match_set_misc4_bits { 763 u8 prog_sample_field_value_0[0x20]; 764 765 u8 prog_sample_field_id_0[0x20]; 766 767 u8 prog_sample_field_value_1[0x20]; 768 769 u8 prog_sample_field_id_1[0x20]; 770 771 u8 prog_sample_field_value_2[0x20]; 772 773 u8 prog_sample_field_id_2[0x20]; 774 775 u8 prog_sample_field_value_3[0x20]; 776 777 u8 prog_sample_field_id_3[0x20]; 778 779 u8 reserved_at_100[0x100]; 780 }; 781 782 struct mlx5_ifc_fte_match_set_misc5_bits { 783 u8 macsec_tag_0[0x20]; 784 785 u8 macsec_tag_1[0x20]; 786 787 u8 macsec_tag_2[0x20]; 788 789 u8 macsec_tag_3[0x20]; 790 791 u8 tunnel_header_0[0x20]; 792 793 u8 tunnel_header_1[0x20]; 794 795 u8 tunnel_header_2[0x20]; 796 797 u8 tunnel_header_3[0x20]; 798 799 u8 reserved_at_100[0x100]; 800 }; 801 802 struct mlx5_ifc_fte_match_set_misc6_bits { 803 u8 reserved_at_0[0x1a]; 804 u8 psp_version[0x4]; 805 u8 reserved_at_1e[0x2]; 806 807 u8 reserved_at_20[0x1e0]; 808 }; 809 810 811 struct mlx5_ifc_cmd_pas_bits { 812 u8 pa_h[0x20]; 813 814 u8 pa_l[0x14]; 815 u8 reserved_at_34[0xc]; 816 }; 817 818 struct mlx5_ifc_uint64_bits { 819 u8 hi[0x20]; 820 821 u8 lo[0x20]; 822 }; 823 824 enum { 825 MLX5_ADS_STAT_RATE_NO_LIMIT = 0x0, 826 MLX5_ADS_STAT_RATE_2_5GBPS = 0x7, 827 MLX5_ADS_STAT_RATE_10GBPS = 0x8, 828 MLX5_ADS_STAT_RATE_30GBPS = 0x9, 829 MLX5_ADS_STAT_RATE_5GBPS = 0xa, 830 MLX5_ADS_STAT_RATE_20GBPS = 0xb, 831 MLX5_ADS_STAT_RATE_40GBPS = 0xc, 832 MLX5_ADS_STAT_RATE_60GBPS = 0xd, 833 MLX5_ADS_STAT_RATE_80GBPS = 0xe, 834 MLX5_ADS_STAT_RATE_120GBPS = 0xf, 835 }; 836 837 struct mlx5_ifc_ads_bits { 838 u8 fl[0x1]; 839 u8 free_ar[0x1]; 840 u8 reserved_at_2[0xe]; 841 u8 pkey_index[0x10]; 842 843 u8 plane_index[0x8]; 844 u8 grh[0x1]; 845 u8 mlid[0x7]; 846 u8 rlid[0x10]; 847 848 u8 ack_timeout[0x5]; 849 u8 reserved_at_45[0x3]; 850 u8 src_addr_index[0x8]; 851 u8 reserved_at_50[0x4]; 852 u8 stat_rate[0x4]; 853 u8 hop_limit[0x8]; 854 855 u8 reserved_at_60[0x4]; 856 u8 tclass[0x8]; 857 u8 flow_label[0x14]; 858 859 u8 rgid_rip[16][0x8]; 860 861 u8 reserved_at_100[0x4]; 862 u8 f_dscp[0x1]; 863 u8 f_ecn[0x1]; 864 u8 reserved_at_106[0x1]; 865 u8 f_eth_prio[0x1]; 866 u8 ecn[0x2]; 867 u8 dscp[0x6]; 868 u8 udp_sport[0x10]; 869 870 u8 dei_cfi[0x1]; 871 u8 eth_prio[0x3]; 872 u8 sl[0x4]; 873 u8 vhca_port_num[0x8]; 874 u8 rmac_47_32[0x10]; 875 876 u8 rmac_31_0[0x20]; 877 }; 878 879 struct mlx5_ifc_flow_table_nic_cap_bits { 880 u8 nic_rx_multi_path_tirs[0x1]; 881 u8 nic_rx_multi_path_tirs_fts[0x1]; 882 u8 allow_sniffer_and_nic_rx_shared_tir[0x1]; 883 u8 reserved_at_3[0x4]; 884 u8 sw_owner_reformat_supported[0x1]; 885 u8 reserved_at_8[0x18]; 886 887 u8 encap_general_header[0x1]; 888 u8 reserved_at_21[0xa]; 889 u8 log_max_packet_reformat_context[0x5]; 890 u8 reserved_at_30[0x6]; 891 u8 max_encap_header_size[0xa]; 892 u8 reserved_at_40[0x1c0]; 893 894 struct mlx5_ifc_flow_table_prop_layout_bits flow_table_properties_nic_receive; 895 896 struct mlx5_ifc_flow_table_prop_layout_bits flow_table_properties_nic_receive_rdma; 897 898 struct mlx5_ifc_flow_table_prop_layout_bits flow_table_properties_nic_receive_sniffer; 899 900 struct mlx5_ifc_flow_table_prop_layout_bits flow_table_properties_nic_transmit; 901 902 struct mlx5_ifc_flow_table_prop_layout_bits flow_table_properties_nic_transmit_rdma; 903 904 struct mlx5_ifc_flow_table_prop_layout_bits flow_table_properties_nic_transmit_sniffer; 905 906 u8 reserved_at_e00[0x600]; 907 908 struct mlx5_ifc_flow_table_fields_supported_2_bits ft_field_support_2_nic_receive; 909 910 u8 reserved_at_1480[0x80]; 911 912 struct mlx5_ifc_flow_table_fields_supported_2_bits ft_field_support_2_nic_receive_rdma; 913 914 u8 reserved_at_1580[0x280]; 915 916 struct mlx5_ifc_flow_table_fields_supported_2_bits ft_field_support_2_nic_transmit_rdma; 917 918 u8 reserved_at_1880[0x780]; 919 920 u8 sw_steering_nic_rx_action_drop_icm_address[0x40]; 921 922 u8 sw_steering_nic_tx_action_drop_icm_address[0x40]; 923 924 u8 sw_steering_nic_tx_action_allow_icm_address[0x40]; 925 926 u8 reserved_at_20c0[0x5f40]; 927 }; 928 929 struct mlx5_ifc_port_selection_cap_bits { 930 u8 reserved_at_0[0x10]; 931 u8 port_select_flow_table[0x1]; 932 u8 reserved_at_11[0x1]; 933 u8 port_select_flow_table_bypass[0x1]; 934 u8 reserved_at_13[0xd]; 935 936 u8 reserved_at_20[0x1e0]; 937 938 struct mlx5_ifc_flow_table_prop_layout_bits flow_table_properties_port_selection; 939 940 struct mlx5_ifc_flow_table_fields_supported_2_bits ft_field_support_2_port_selection; 941 942 u8 reserved_at_480[0x7b80]; 943 }; 944 945 enum { 946 MLX5_FDB_TO_VPORT_REG_C_0 = 0x01, 947 MLX5_FDB_TO_VPORT_REG_C_1 = 0x02, 948 MLX5_FDB_TO_VPORT_REG_C_2 = 0x04, 949 MLX5_FDB_TO_VPORT_REG_C_3 = 0x08, 950 MLX5_FDB_TO_VPORT_REG_C_4 = 0x10, 951 MLX5_FDB_TO_VPORT_REG_C_5 = 0x20, 952 MLX5_FDB_TO_VPORT_REG_C_6 = 0x40, 953 MLX5_FDB_TO_VPORT_REG_C_7 = 0x80, 954 }; 955 956 struct mlx5_ifc_flow_table_eswitch_cap_bits { 957 u8 fdb_to_vport_reg_c_id[0x8]; 958 u8 reserved_at_8[0x5]; 959 u8 fdb_uplink_hairpin[0x1]; 960 u8 fdb_multi_path_any_table_limit_regc[0x1]; 961 u8 reserved_at_f[0x1]; 962 u8 fdb_dynamic_tunnel[0x1]; 963 u8 reserved_at_11[0x1]; 964 u8 fdb_multi_path_any_table[0x1]; 965 u8 reserved_at_13[0x2]; 966 u8 fdb_modify_header_fwd_to_table[0x1]; 967 u8 fdb_ipv4_ttl_modify[0x1]; 968 u8 flow_source[0x1]; 969 u8 reserved_at_18[0x2]; 970 u8 multi_fdb_encap[0x1]; 971 u8 egress_acl_forward_to_vport[0x1]; 972 u8 fdb_multi_path_to_table[0x1]; 973 u8 reserved_at_1d[0x3]; 974 975 u8 reserved_at_20[0x1e0]; 976 977 struct mlx5_ifc_flow_table_prop_layout_bits flow_table_properties_nic_esw_fdb; 978 979 struct mlx5_ifc_flow_table_prop_layout_bits flow_table_properties_esw_acl_ingress; 980 981 struct mlx5_ifc_flow_table_prop_layout_bits flow_table_properties_esw_acl_egress; 982 983 u8 reserved_at_800[0xC00]; 984 985 struct mlx5_ifc_flow_table_fields_supported_2_bits ft_field_support_2_esw_fdb; 986 987 struct mlx5_ifc_flow_table_fields_supported_2_bits ft_field_bitmask_support_2_esw_fdb; 988 989 u8 reserved_at_1500[0x300]; 990 991 u8 sw_steering_fdb_action_drop_icm_address_rx[0x40]; 992 993 u8 sw_steering_fdb_action_drop_icm_address_tx[0x40]; 994 995 u8 sw_steering_uplink_icm_address_rx[0x40]; 996 997 u8 sw_steering_uplink_icm_address_tx[0x40]; 998 999 u8 reserved_at_1900[0x6700]; 1000 }; 1001 1002 struct mlx5_ifc_wqe_based_flow_table_cap_bits { 1003 u8 reserved_at_0[0x3]; 1004 u8 log_max_num_ste[0x5]; 1005 u8 reserved_at_8[0x3]; 1006 u8 log_max_num_stc[0x5]; 1007 u8 reserved_at_10[0x3]; 1008 u8 log_max_num_rtc[0x5]; 1009 u8 reserved_at_18[0x3]; 1010 u8 log_max_num_header_modify_pattern[0x5]; 1011 1012 u8 rtc_hash_split_table[0x1]; 1013 u8 rtc_linear_lookup_table[0x1]; 1014 u8 reserved_at_22[0x1]; 1015 u8 stc_alloc_log_granularity[0x5]; 1016 u8 reserved_at_28[0x3]; 1017 u8 stc_alloc_log_max[0x5]; 1018 u8 reserved_at_30[0x3]; 1019 u8 ste_alloc_log_granularity[0x5]; 1020 u8 reserved_at_38[0x3]; 1021 u8 ste_alloc_log_max[0x5]; 1022 1023 u8 reserved_at_40[0xb]; 1024 u8 rtc_reparse_mode[0x5]; 1025 u8 reserved_at_50[0x3]; 1026 u8 rtc_index_mode[0x5]; 1027 u8 reserved_at_58[0x3]; 1028 u8 rtc_log_depth_max[0x5]; 1029 1030 u8 reserved_at_60[0x10]; 1031 u8 ste_format[0x10]; 1032 1033 u8 stc_action_type[0x80]; 1034 1035 u8 header_insert_type[0x10]; 1036 u8 header_remove_type[0x10]; 1037 1038 u8 trivial_match_definer[0x20]; 1039 1040 u8 reserved_at_140[0x1b]; 1041 u8 rtc_max_num_hash_definer_gen_wqe[0x5]; 1042 1043 u8 reserved_at_160[0x18]; 1044 u8 access_index_mode[0x8]; 1045 1046 u8 reserved_at_180[0x10]; 1047 u8 ste_format_gen_wqe[0x10]; 1048 1049 u8 linear_match_definer_reg_c3[0x20]; 1050 1051 u8 fdb_jump_to_tir_stc[0x1]; 1052 u8 reserved_at_1c1[0x1f]; 1053 }; 1054 1055 enum { 1056 MLX5_COUNTER_SOURCE_ESWITCH = 0x0, 1057 MLX5_COUNTER_FLOW_ESWITCH = 0x1, 1058 }; 1059 1060 struct mlx5_ifc_e_switch_cap_bits { 1061 u8 vport_svlan_strip[0x1]; 1062 u8 vport_cvlan_strip[0x1]; 1063 u8 vport_svlan_insert[0x1]; 1064 u8 vport_cvlan_insert_if_not_exist[0x1]; 1065 u8 vport_cvlan_insert_overwrite[0x1]; 1066 u8 reserved_at_5[0x1]; 1067 u8 vport_cvlan_insert_always[0x1]; 1068 u8 esw_shared_ingress_acl[0x1]; 1069 u8 esw_uplink_ingress_acl[0x1]; 1070 u8 root_ft_on_other_esw[0x1]; 1071 u8 reserved_at_a[0x1]; 1072 u8 esw_vport_state_max_tx_speed[0x1]; 1073 u8 reserved_at_c[0xd]; 1074 u8 esw_functions_changed[0x1]; 1075 u8 reserved_at_1a[0x1]; 1076 u8 ecpf_vport_exists[0x1]; 1077 u8 counter_eswitch_affinity[0x1]; 1078 u8 merged_eswitch[0x1]; 1079 u8 nic_vport_node_guid_modify[0x1]; 1080 u8 nic_vport_port_guid_modify[0x1]; 1081 1082 u8 vxlan_encap_decap[0x1]; 1083 u8 nvgre_encap_decap[0x1]; 1084 u8 reserved_at_22[0x1]; 1085 u8 log_max_fdb_encap_uplink[0x5]; 1086 u8 reserved_at_21[0x3]; 1087 u8 log_max_packet_reformat_context[0x5]; 1088 u8 reserved_2b[0x6]; 1089 u8 max_encap_header_size[0xa]; 1090 1091 u8 reserved_at_40[0xb]; 1092 u8 log_max_esw_sf[0x5]; 1093 u8 esw_sf_base_id[0x10]; 1094 1095 u8 esw_manager_vport_number_valid[0x1]; 1096 u8 reserved_at_61[0xf]; 1097 u8 esw_manager_vport_number[0x10]; 1098 1099 u8 reserved_at_80[0x780]; 1100 1101 }; 1102 1103 struct mlx5_ifc_qos_cap_bits { 1104 u8 packet_pacing[0x1]; 1105 u8 esw_scheduling[0x1]; 1106 u8 esw_bw_share[0x1]; 1107 u8 esw_rate_limit[0x1]; 1108 u8 reserved_at_4[0x1]; 1109 u8 packet_pacing_burst_bound[0x1]; 1110 u8 packet_pacing_typical_size[0x1]; 1111 u8 reserved_at_7[0x1]; 1112 u8 nic_sq_scheduling[0x1]; 1113 u8 nic_bw_share[0x1]; 1114 u8 nic_rate_limit[0x1]; 1115 u8 packet_pacing_uid[0x1]; 1116 u8 log_esw_max_sched_depth[0x4]; 1117 u8 reserved_at_10[0x10]; 1118 1119 u8 reserved_at_20[0x2]; 1120 u8 packet_pacing_req_ud[0x1]; 1121 u8 packet_pacing_req_uc[0x1]; 1122 u8 reserved_at_24[0x5]; 1123 u8 esw_cross_esw_sched[0x1]; 1124 u8 reserved_at_2a[0x1]; 1125 u8 log_max_qos_nic_queue_group[0x5]; 1126 u8 reserved_at_30[0x10]; 1127 1128 u8 packet_pacing_max_rate[0x20]; 1129 1130 u8 packet_pacing_min_rate[0x20]; 1131 1132 u8 reserved_at_80[0xb]; 1133 u8 log_esw_max_rate_limit[0x5]; 1134 u8 packet_pacing_rate_table_size[0x10]; 1135 1136 u8 esw_element_type[0x10]; 1137 u8 esw_tsar_type[0x10]; 1138 1139 u8 reserved_at_c0[0x10]; 1140 u8 max_qos_para_vport[0x10]; 1141 1142 u8 max_tsar_bw_share[0x20]; 1143 1144 u8 nic_element_type[0x10]; 1145 u8 nic_tsar_type[0x10]; 1146 1147 u8 reserved_at_120[0x3]; 1148 u8 log_meter_aso_granularity[0x5]; 1149 u8 reserved_at_128[0x3]; 1150 u8 log_meter_aso_max_alloc[0x5]; 1151 u8 reserved_at_130[0x3]; 1152 u8 log_max_num_meter_aso[0x5]; 1153 u8 reserved_at_138[0x8]; 1154 1155 u8 reserved_at_140[0x6c0]; 1156 }; 1157 1158 struct mlx5_ifc_debug_cap_bits { 1159 u8 core_dump_general[0x1]; 1160 u8 core_dump_qp[0x1]; 1161 u8 reserved_at_2[0x7]; 1162 u8 resource_dump[0x1]; 1163 u8 reserved_at_a[0x16]; 1164 1165 u8 reserved_at_20[0x2]; 1166 u8 stall_detect[0x1]; 1167 u8 reserved_at_23[0x1d]; 1168 1169 u8 reserved_at_40[0x7c0]; 1170 }; 1171 1172 struct mlx5_ifc_per_protocol_networking_offload_caps_bits { 1173 u8 csum_cap[0x1]; 1174 u8 vlan_cap[0x1]; 1175 u8 lro_cap[0x1]; 1176 u8 lro_psh_flag[0x1]; 1177 u8 lro_time_stamp[0x1]; 1178 u8 reserved_at_5[0x2]; 1179 u8 wqe_vlan_insert[0x1]; 1180 u8 self_lb_en_modifiable[0x1]; 1181 u8 reserved_at_9[0x2]; 1182 u8 max_lso_cap[0x5]; 1183 u8 multi_pkt_send_wqe[0x2]; 1184 u8 wqe_inline_mode[0x2]; 1185 u8 rss_ind_tbl_cap[0x4]; 1186 u8 reg_umr_sq[0x1]; 1187 u8 scatter_fcs[0x1]; 1188 u8 enhanced_multi_pkt_send_wqe[0x1]; 1189 u8 tunnel_lso_const_out_ip_id[0x1]; 1190 u8 tunnel_lro_gre[0x1]; 1191 u8 tunnel_lro_vxlan[0x1]; 1192 u8 tunnel_stateless_gre[0x1]; 1193 u8 tunnel_stateless_vxlan[0x1]; 1194 1195 u8 swp[0x1]; 1196 u8 swp_csum[0x1]; 1197 u8 swp_lso[0x1]; 1198 u8 cqe_checksum_full[0x1]; 1199 u8 tunnel_stateless_geneve_tx[0x1]; 1200 u8 tunnel_stateless_mpls_over_udp[0x1]; 1201 u8 tunnel_stateless_mpls_over_gre[0x1]; 1202 u8 tunnel_stateless_vxlan_gpe[0x1]; 1203 u8 tunnel_stateless_ipv4_over_vxlan[0x1]; 1204 u8 tunnel_stateless_ip_over_ip[0x1]; 1205 u8 insert_trailer[0x1]; 1206 u8 reserved_at_2b[0x1]; 1207 u8 tunnel_stateless_ip_over_ip_rx[0x1]; 1208 u8 tunnel_stateless_ip_over_ip_tx[0x1]; 1209 u8 reserved_at_2e[0x2]; 1210 u8 max_vxlan_udp_ports[0x8]; 1211 u8 swp_csum_l4_partial[0x1]; 1212 u8 reserved_at_39[0x5]; 1213 u8 max_geneve_opt_len[0x1]; 1214 u8 tunnel_stateless_geneve_rx[0x1]; 1215 1216 u8 reserved_at_40[0x10]; 1217 u8 lro_min_mss_size[0x10]; 1218 1219 u8 reserved_at_60[0x120]; 1220 1221 u8 lro_timer_supported_periods[4][0x20]; 1222 1223 u8 reserved_at_200[0x600]; 1224 }; 1225 1226 enum { 1227 MLX5_TIMESTAMP_FORMAT_CAP_FREE_RUNNING = 0x0, 1228 MLX5_TIMESTAMP_FORMAT_CAP_REAL_TIME = 0x1, 1229 MLX5_TIMESTAMP_FORMAT_CAP_FREE_RUNNING_AND_REAL_TIME = 0x2, 1230 }; 1231 1232 struct mlx5_ifc_roce_cap_bits { 1233 u8 roce_apm[0x1]; 1234 u8 reserved_at_1[0x3]; 1235 u8 sw_r_roce_src_udp_port[0x1]; 1236 u8 fl_rc_qp_when_roce_disabled[0x1]; 1237 u8 fl_rc_qp_when_roce_enabled[0x1]; 1238 u8 roce_cc_general[0x1]; 1239 u8 qp_ooo_transmit_default[0x1]; 1240 u8 reserved_at_9[0x15]; 1241 u8 qp_ts_format[0x2]; 1242 1243 u8 reserved_at_20[0x60]; 1244 1245 u8 reserved_at_80[0xc]; 1246 u8 l3_type[0x4]; 1247 u8 reserved_at_90[0x8]; 1248 u8 roce_version[0x8]; 1249 1250 u8 reserved_at_a0[0x10]; 1251 u8 r_roce_dest_udp_port[0x10]; 1252 1253 u8 r_roce_max_src_udp_port[0x10]; 1254 u8 r_roce_min_src_udp_port[0x10]; 1255 1256 u8 reserved_at_e0[0x10]; 1257 u8 roce_address_table_size[0x10]; 1258 1259 u8 reserved_at_100[0x700]; 1260 }; 1261 1262 struct mlx5_ifc_sync_steering_in_bits { 1263 u8 opcode[0x10]; 1264 u8 uid[0x10]; 1265 1266 u8 reserved_at_20[0x10]; 1267 u8 op_mod[0x10]; 1268 1269 u8 reserved_at_40[0xc0]; 1270 }; 1271 1272 struct mlx5_ifc_sync_steering_out_bits { 1273 u8 status[0x8]; 1274 u8 reserved_at_8[0x18]; 1275 1276 u8 syndrome[0x20]; 1277 1278 u8 reserved_at_40[0x40]; 1279 }; 1280 1281 struct mlx5_ifc_sync_crypto_in_bits { 1282 u8 opcode[0x10]; 1283 u8 uid[0x10]; 1284 1285 u8 reserved_at_20[0x10]; 1286 u8 op_mod[0x10]; 1287 1288 u8 reserved_at_40[0x20]; 1289 1290 u8 reserved_at_60[0x10]; 1291 u8 crypto_type[0x10]; 1292 1293 u8 reserved_at_80[0x80]; 1294 }; 1295 1296 struct mlx5_ifc_sync_crypto_out_bits { 1297 u8 status[0x8]; 1298 u8 reserved_at_8[0x18]; 1299 1300 u8 syndrome[0x20]; 1301 1302 u8 reserved_at_40[0x40]; 1303 }; 1304 1305 struct mlx5_ifc_device_mem_cap_bits { 1306 u8 memic[0x1]; 1307 u8 reserved_at_1[0x1f]; 1308 1309 u8 reserved_at_20[0xb]; 1310 u8 log_min_memic_alloc_size[0x5]; 1311 u8 reserved_at_30[0x8]; 1312 u8 log_max_memic_addr_alignment[0x8]; 1313 1314 u8 memic_bar_start_addr[0x40]; 1315 1316 u8 memic_bar_size[0x20]; 1317 1318 u8 max_memic_size[0x20]; 1319 1320 u8 steering_sw_icm_start_address[0x40]; 1321 1322 u8 reserved_at_100[0x8]; 1323 u8 log_header_modify_sw_icm_size[0x8]; 1324 u8 reserved_at_110[0x2]; 1325 u8 log_sw_icm_alloc_granularity[0x6]; 1326 u8 log_steering_sw_icm_size[0x8]; 1327 1328 u8 log_indirect_encap_sw_icm_size[0x8]; 1329 u8 reserved_at_128[0x10]; 1330 u8 log_header_modify_pattern_sw_icm_size[0x8]; 1331 1332 u8 header_modify_sw_icm_start_address[0x40]; 1333 1334 u8 reserved_at_180[0x40]; 1335 1336 u8 header_modify_pattern_sw_icm_start_address[0x40]; 1337 1338 u8 memic_operations[0x20]; 1339 1340 u8 reserved_at_220[0x20]; 1341 1342 u8 indirect_encap_sw_icm_start_address[0x40]; 1343 1344 u8 reserved_at_280[0x580]; 1345 }; 1346 1347 struct mlx5_ifc_device_event_cap_bits { 1348 u8 user_affiliated_events[4][0x40]; 1349 1350 u8 user_unaffiliated_events[4][0x40]; 1351 }; 1352 1353 struct mlx5_ifc_virtio_emulation_cap_bits { 1354 u8 desc_tunnel_offload_type[0x1]; 1355 u8 eth_frame_offload_type[0x1]; 1356 u8 virtio_version_1_0[0x1]; 1357 u8 device_features_bits_mask[0xd]; 1358 u8 event_mode[0x8]; 1359 u8 virtio_queue_type[0x8]; 1360 1361 u8 max_tunnel_desc[0x10]; 1362 u8 reserved_at_30[0x3]; 1363 u8 log_doorbell_stride[0x5]; 1364 u8 reserved_at_38[0x3]; 1365 u8 log_doorbell_bar_size[0x5]; 1366 1367 u8 doorbell_bar_offset[0x40]; 1368 1369 u8 max_emulated_devices[0x8]; 1370 u8 max_num_virtio_queues[0x18]; 1371 1372 u8 reserved_at_a0[0x20]; 1373 1374 u8 reserved_at_c0[0x13]; 1375 u8 desc_group_mkey_supported[0x1]; 1376 u8 freeze_to_rdy_supported[0x1]; 1377 u8 reserved_at_d5[0xb]; 1378 1379 u8 reserved_at_e0[0x20]; 1380 1381 u8 umem_1_buffer_param_a[0x20]; 1382 1383 u8 umem_1_buffer_param_b[0x20]; 1384 1385 u8 umem_2_buffer_param_a[0x20]; 1386 1387 u8 umem_2_buffer_param_b[0x20]; 1388 1389 u8 umem_3_buffer_param_a[0x20]; 1390 1391 u8 umem_3_buffer_param_b[0x20]; 1392 1393 u8 reserved_at_1c0[0x640]; 1394 }; 1395 1396 struct mlx5_ifc_tlp_dev_emu_capabilities_bits { 1397 u8 reserved_at_0[0x20]; 1398 1399 u8 reserved_at_20[0x13]; 1400 u8 log_tlp_rsp_gw_page_stride[0x5]; 1401 u8 reserved_at_38[0x8]; 1402 1403 u8 reserved_at_40[0xc0]; 1404 1405 u8 reserved_at_100[0xc]; 1406 u8 tlp_rsp_gw_num_pages[0x4]; 1407 u8 reserved_at_110[0x10]; 1408 1409 u8 reserved_at_120[0xa0]; 1410 1411 u8 tlp_rsp_gw_pages_bar_offset[0x40]; 1412 1413 u8 reserved_at_200[0x600]; 1414 }; 1415 1416 enum { 1417 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_QP_1_BYTE = 0x0, 1418 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_QP_2_BYTES = 0x2, 1419 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_QP_4_BYTES = 0x4, 1420 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_QP_8_BYTES = 0x8, 1421 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_QP_16_BYTES = 0x10, 1422 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_QP_32_BYTES = 0x20, 1423 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_QP_64_BYTES = 0x40, 1424 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_QP_128_BYTES = 0x80, 1425 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_QP_256_BYTES = 0x100, 1426 }; 1427 1428 enum { 1429 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_DC_1_BYTE = 0x1, 1430 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_DC_2_BYTES = 0x2, 1431 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_DC_4_BYTES = 0x4, 1432 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_DC_8_BYTES = 0x8, 1433 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_DC_16_BYTES = 0x10, 1434 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_DC_32_BYTES = 0x20, 1435 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_DC_64_BYTES = 0x40, 1436 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_DC_128_BYTES = 0x80, 1437 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_DC_256_BYTES = 0x100, 1438 }; 1439 1440 struct mlx5_ifc_atomic_caps_bits { 1441 u8 reserved_at_0[0x40]; 1442 1443 u8 atomic_req_8B_endianness_mode[0x2]; 1444 u8 reserved_at_42[0x4]; 1445 u8 supported_atomic_req_8B_endianness_mode_1[0x1]; 1446 1447 u8 reserved_at_47[0x19]; 1448 1449 u8 reserved_at_60[0x20]; 1450 1451 u8 reserved_at_80[0x10]; 1452 u8 atomic_operations[0x10]; 1453 1454 u8 reserved_at_a0[0x10]; 1455 u8 atomic_size_qp[0x10]; 1456 1457 u8 reserved_at_c0[0x10]; 1458 u8 atomic_size_dc[0x10]; 1459 1460 u8 reserved_at_e0[0x720]; 1461 }; 1462 1463 struct mlx5_ifc_odp_scheme_cap_bits { 1464 u8 reserved_at_0[0x40]; 1465 1466 u8 sig[0x1]; 1467 u8 reserved_at_41[0x4]; 1468 u8 page_prefetch[0x1]; 1469 u8 reserved_at_46[0x1a]; 1470 1471 u8 reserved_at_60[0x20]; 1472 1473 struct mlx5_ifc_odp_per_transport_service_cap_bits rc_odp_caps; 1474 1475 struct mlx5_ifc_odp_per_transport_service_cap_bits uc_odp_caps; 1476 1477 struct mlx5_ifc_odp_per_transport_service_cap_bits ud_odp_caps; 1478 1479 struct mlx5_ifc_odp_per_transport_service_cap_bits xrc_odp_caps; 1480 1481 struct mlx5_ifc_odp_per_transport_service_cap_bits dc_odp_caps; 1482 1483 u8 reserved_at_120[0xe0]; 1484 }; 1485 1486 struct mlx5_ifc_odp_cap_bits { 1487 struct mlx5_ifc_odp_scheme_cap_bits transport_page_fault_scheme_cap; 1488 1489 struct mlx5_ifc_odp_scheme_cap_bits memory_page_fault_scheme_cap; 1490 1491 u8 reserved_at_400[0x200]; 1492 1493 u8 mem_page_fault[0x1]; 1494 u8 reserved_at_601[0x1f]; 1495 1496 u8 reserved_at_620[0x1e0]; 1497 }; 1498 1499 struct mlx5_ifc_tls_cap_bits { 1500 u8 tls_1_2_aes_gcm_128[0x1]; 1501 u8 tls_1_3_aes_gcm_128[0x1]; 1502 u8 tls_1_2_aes_gcm_256[0x1]; 1503 u8 tls_1_3_aes_gcm_256[0x1]; 1504 u8 reserved_at_4[0x1c]; 1505 1506 u8 reserved_at_20[0x7e0]; 1507 }; 1508 1509 struct mlx5_ifc_ipsec_cap_bits { 1510 u8 ipsec_full_offload[0x1]; 1511 u8 ipsec_crypto_offload[0x1]; 1512 u8 ipsec_esn[0x1]; 1513 u8 ipsec_crypto_esp_aes_gcm_256_encrypt[0x1]; 1514 u8 ipsec_crypto_esp_aes_gcm_128_encrypt[0x1]; 1515 u8 ipsec_crypto_esp_aes_gcm_256_decrypt[0x1]; 1516 u8 ipsec_crypto_esp_aes_gcm_128_decrypt[0x1]; 1517 u8 reserved_at_7[0x4]; 1518 u8 log_max_ipsec_offload[0x5]; 1519 u8 reserved_at_10[0x10]; 1520 1521 u8 min_log_ipsec_full_replay_window[0x8]; 1522 u8 max_log_ipsec_full_replay_window[0x8]; 1523 u8 reserved_at_30[0x7d0]; 1524 }; 1525 1526 struct mlx5_ifc_macsec_cap_bits { 1527 u8 macsec_epn[0x1]; 1528 u8 reserved_at_1[0x2]; 1529 u8 macsec_crypto_esp_aes_gcm_256_encrypt[0x1]; 1530 u8 macsec_crypto_esp_aes_gcm_128_encrypt[0x1]; 1531 u8 macsec_crypto_esp_aes_gcm_256_decrypt[0x1]; 1532 u8 macsec_crypto_esp_aes_gcm_128_decrypt[0x1]; 1533 u8 reserved_at_7[0x4]; 1534 u8 log_max_macsec_offload[0x5]; 1535 u8 reserved_at_10[0x10]; 1536 1537 u8 min_log_macsec_full_replay_window[0x8]; 1538 u8 max_log_macsec_full_replay_window[0x8]; 1539 u8 reserved_at_30[0x10]; 1540 1541 u8 reserved_at_40[0x7c0]; 1542 }; 1543 1544 struct mlx5_ifc_psp_cap_bits { 1545 u8 reserved_at_0[0x1]; 1546 u8 psp_crypto_offload[0x1]; 1547 u8 reserved_at_2[0x1]; 1548 u8 psp_crypto_esp_aes_gcm_256_encrypt[0x1]; 1549 u8 psp_crypto_esp_aes_gcm_128_encrypt[0x1]; 1550 u8 psp_crypto_esp_aes_gcm_256_decrypt[0x1]; 1551 u8 psp_crypto_esp_aes_gcm_128_decrypt[0x1]; 1552 u8 reserved_at_7[0x4]; 1553 u8 log_max_num_of_psp_spi[0x5]; 1554 u8 reserved_at_10[0x10]; 1555 1556 u8 reserved_at_20[0x7e0]; 1557 }; 1558 1559 enum { 1560 MLX5_WQ_TYPE_LINKED_LIST = 0x0, 1561 MLX5_WQ_TYPE_CYCLIC = 0x1, 1562 MLX5_WQ_TYPE_LINKED_LIST_STRIDING_RQ = 0x2, 1563 MLX5_WQ_TYPE_CYCLIC_STRIDING_RQ = 0x3, 1564 }; 1565 1566 enum { 1567 MLX5_WQ_END_PAD_MODE_NONE = 0x0, 1568 MLX5_WQ_END_PAD_MODE_ALIGN = 0x1, 1569 }; 1570 1571 enum { 1572 MLX5_CMD_HCA_CAP_GID_TABLE_SIZE_8_GID_ENTRIES = 0x0, 1573 MLX5_CMD_HCA_CAP_GID_TABLE_SIZE_16_GID_ENTRIES = 0x1, 1574 MLX5_CMD_HCA_CAP_GID_TABLE_SIZE_32_GID_ENTRIES = 0x2, 1575 MLX5_CMD_HCA_CAP_GID_TABLE_SIZE_64_GID_ENTRIES = 0x3, 1576 MLX5_CMD_HCA_CAP_GID_TABLE_SIZE_128_GID_ENTRIES = 0x4, 1577 }; 1578 1579 enum { 1580 MLX5_CMD_HCA_CAP_PKEY_TABLE_SIZE_128_ENTRIES = 0x0, 1581 MLX5_CMD_HCA_CAP_PKEY_TABLE_SIZE_256_ENTRIES = 0x1, 1582 MLX5_CMD_HCA_CAP_PKEY_TABLE_SIZE_512_ENTRIES = 0x2, 1583 MLX5_CMD_HCA_CAP_PKEY_TABLE_SIZE_1K_ENTRIES = 0x3, 1584 MLX5_CMD_HCA_CAP_PKEY_TABLE_SIZE_2K_ENTRIES = 0x4, 1585 MLX5_CMD_HCA_CAP_PKEY_TABLE_SIZE_4K_ENTRIES = 0x5, 1586 }; 1587 1588 enum { 1589 MLX5_CMD_HCA_CAP_PORT_TYPE_IB = 0x0, 1590 MLX5_CMD_HCA_CAP_PORT_TYPE_ETHERNET = 0x1, 1591 }; 1592 1593 enum { 1594 MLX5_CMD_HCA_CAP_CMDIF_CHECKSUM_DISABLED = 0x0, 1595 MLX5_CMD_HCA_CAP_CMDIF_CHECKSUM_INITIAL_STATE = 0x1, 1596 MLX5_CMD_HCA_CAP_CMDIF_CHECKSUM_ENABLED = 0x3, 1597 }; 1598 1599 enum { 1600 MLX5_CAP_PORT_TYPE_IB = 0x0, 1601 MLX5_CAP_PORT_TYPE_ETH = 0x1, 1602 }; 1603 1604 enum { 1605 MLX5_CAP_UMR_FENCE_STRONG = 0x0, 1606 MLX5_CAP_UMR_FENCE_SMALL = 0x1, 1607 MLX5_CAP_UMR_FENCE_NONE = 0x2, 1608 }; 1609 1610 enum { 1611 MLX5_FLEX_IPV4_OVER_VXLAN_ENABLED = 1 << 0, 1612 MLX5_FLEX_IPV6_OVER_VXLAN_ENABLED = 1 << 1, 1613 MLX5_FLEX_IPV6_OVER_IP_ENABLED = 1 << 2, 1614 MLX5_FLEX_PARSER_GENEVE_ENABLED = 1 << 3, 1615 MLX5_FLEX_PARSER_MPLS_OVER_GRE_ENABLED = 1 << 4, 1616 MLX5_FLEX_PARSER_MPLS_OVER_UDP_ENABLED = 1 << 5, 1617 MLX5_FLEX_P_BIT_VXLAN_GPE_ENABLED = 1 << 6, 1618 MLX5_FLEX_PARSER_VXLAN_GPE_ENABLED = 1 << 7, 1619 MLX5_FLEX_PARSER_ICMP_V4_ENABLED = 1 << 8, 1620 MLX5_FLEX_PARSER_ICMP_V6_ENABLED = 1 << 9, 1621 MLX5_FLEX_PARSER_GENEVE_TLV_OPTION_0_ENABLED = 1 << 10, 1622 MLX5_FLEX_PARSER_GTPU_ENABLED = 1 << 11, 1623 MLX5_FLEX_PARSER_GTPU_DW_2_ENABLED = 1 << 16, 1624 MLX5_FLEX_PARSER_GTPU_FIRST_EXT_DW_0_ENABLED = 1 << 17, 1625 MLX5_FLEX_PARSER_GTPU_DW_0_ENABLED = 1 << 18, 1626 MLX5_FLEX_PARSER_GTPU_TEID_ENABLED = 1 << 19, 1627 }; 1628 1629 enum { 1630 MLX5_UCTX_CAP_RAW_TX = 1UL << 0, 1631 MLX5_UCTX_CAP_INTERNAL_DEV_RES = 1UL << 1, 1632 MLX5_UCTX_CAP_RDMA_CTRL = 1UL << 3, 1633 MLX5_UCTX_CAP_RDMA_CTRL_OTHER_VHCA = 1UL << 4, 1634 }; 1635 1636 #define MLX5_FC_BULK_SIZE_FACTOR 128 1637 1638 enum mlx5_fc_bulk_alloc_bitmask { 1639 MLX5_FC_BULK_128 = (1 << 0), 1640 MLX5_FC_BULK_256 = (1 << 1), 1641 MLX5_FC_BULK_512 = (1 << 2), 1642 MLX5_FC_BULK_1024 = (1 << 3), 1643 MLX5_FC_BULK_2048 = (1 << 4), 1644 MLX5_FC_BULK_4096 = (1 << 5), 1645 MLX5_FC_BULK_8192 = (1 << 6), 1646 MLX5_FC_BULK_16384 = (1 << 7), 1647 }; 1648 1649 #define MLX5_FC_BULK_NUM_FCS(fc_enum) (MLX5_FC_BULK_SIZE_FACTOR * (fc_enum)) 1650 1651 #define MLX5_FT_MAX_MULTIPATH_LEVEL 63 1652 1653 enum { 1654 MLX5_STEERING_FORMAT_CONNECTX_5 = 0, 1655 MLX5_STEERING_FORMAT_CONNECTX_6DX = 1, 1656 MLX5_STEERING_FORMAT_CONNECTX_7 = 2, 1657 MLX5_STEERING_FORMAT_CONNECTX_8 = 3, 1658 }; 1659 1660 enum { 1661 MLX5_ID_MODE_FUNCTION_INDEX = 0, 1662 MLX5_ID_MODE_FUNCTION_VHCA_ID = 1, 1663 }; 1664 1665 struct mlx5_ifc_cmd_hca_cap_bits { 1666 u8 reserved_at_0[0x6]; 1667 u8 page_request_disable[0x1]; 1668 u8 abs_native_port_num[0x1]; 1669 u8 reserved_at_8[0x8]; 1670 u8 shared_object_to_user_object_allowed[0x1]; 1671 u8 reserved_at_13[0xe]; 1672 u8 vhca_resource_manager[0x1]; 1673 1674 u8 hca_cap_2[0x1]; 1675 u8 create_lag_when_not_master_up[0x1]; 1676 u8 dtor[0x1]; 1677 u8 event_on_vhca_state_teardown_request[0x1]; 1678 u8 event_on_vhca_state_in_use[0x1]; 1679 u8 event_on_vhca_state_active[0x1]; 1680 u8 event_on_vhca_state_allocated[0x1]; 1681 u8 event_on_vhca_state_invalid[0x1]; 1682 u8 reserved_at_28[0x8]; 1683 u8 vhca_id[0x10]; 1684 1685 u8 reserved_at_40[0x40]; 1686 1687 u8 log_max_srq_sz[0x8]; 1688 u8 log_max_qp_sz[0x8]; 1689 u8 event_cap[0x1]; 1690 u8 reserved_at_91[0x2]; 1691 u8 isolate_vl_tc_new[0x1]; 1692 u8 reserved_at_94[0x4]; 1693 u8 prio_tag_required[0x1]; 1694 u8 reserved_at_99[0x2]; 1695 u8 log_max_qp[0x5]; 1696 1697 u8 reserved_at_a0[0x3]; 1698 u8 ece_support[0x1]; 1699 u8 reserved_at_a4[0x5]; 1700 u8 reg_c_preserve[0x1]; 1701 u8 reserved_at_aa[0x1]; 1702 u8 log_max_srq[0x5]; 1703 u8 reserved_at_b0[0x1]; 1704 u8 uplink_follow[0x1]; 1705 u8 ts_cqe_to_dest_cqn[0x1]; 1706 u8 reserved_at_b3[0x6]; 1707 u8 go_back_n[0x1]; 1708 u8 reserved_at_ba[0x6]; 1709 1710 u8 max_sgl_for_optimized_performance[0x8]; 1711 u8 log_max_cq_sz[0x8]; 1712 u8 relaxed_ordering_write_umr[0x1]; 1713 u8 relaxed_ordering_read_umr[0x1]; 1714 u8 reserved_at_d2[0x7]; 1715 u8 virtio_net_device_emualtion_manager[0x1]; 1716 u8 virtio_blk_device_emualtion_manager[0x1]; 1717 u8 log_max_cq[0x5]; 1718 1719 u8 log_max_eq_sz[0x8]; 1720 u8 relaxed_ordering_write[0x1]; 1721 u8 relaxed_ordering_read_pci_enabled[0x1]; 1722 u8 log_max_mkey[0x6]; 1723 u8 reserved_at_f0[0x6]; 1724 u8 terminate_scatter_list_mkey[0x1]; 1725 u8 repeated_mkey[0x1]; 1726 u8 dump_fill_mkey[0x1]; 1727 u8 reserved_at_f9[0x2]; 1728 u8 fast_teardown[0x1]; 1729 u8 log_max_eq[0x4]; 1730 1731 u8 max_indirection[0x8]; 1732 u8 fixed_buffer_size[0x1]; 1733 u8 log_max_mrw_sz[0x7]; 1734 u8 force_teardown[0x1]; 1735 u8 reserved_at_111[0x1]; 1736 u8 log_max_bsf_list_size[0x6]; 1737 u8 umr_extended_translation_offset[0x1]; 1738 u8 null_mkey[0x1]; 1739 u8 log_max_klm_list_size[0x6]; 1740 1741 u8 reserved_at_120[0x2]; 1742 u8 qpc_extension[0x1]; 1743 u8 reserved_at_123[0x7]; 1744 u8 log_max_ra_req_dc[0x6]; 1745 u8 reserved_at_130[0x2]; 1746 u8 eth_wqe_too_small[0x1]; 1747 u8 reserved_at_133[0x6]; 1748 u8 vnic_env_cq_overrun[0x1]; 1749 u8 log_max_ra_res_dc[0x6]; 1750 1751 u8 reserved_at_140[0x5]; 1752 u8 release_all_pages[0x1]; 1753 u8 must_not_use[0x1]; 1754 u8 reserved_at_147[0x2]; 1755 u8 roce_accl[0x1]; 1756 u8 log_max_ra_req_qp[0x6]; 1757 u8 reserved_at_150[0xa]; 1758 u8 log_max_ra_res_qp[0x6]; 1759 1760 u8 end_pad[0x1]; 1761 u8 cc_query_allowed[0x1]; 1762 u8 cc_modify_allowed[0x1]; 1763 u8 start_pad[0x1]; 1764 u8 cache_line_128byte[0x1]; 1765 u8 reserved_at_165[0x4]; 1766 u8 rts2rts_qp_counters_set_id[0x1]; 1767 u8 reserved_at_16a[0x2]; 1768 u8 vnic_env_int_rq_oob[0x1]; 1769 u8 sbcam_reg[0x1]; 1770 u8 reserved_at_16e[0x1]; 1771 u8 qcam_reg[0x1]; 1772 u8 gid_table_size[0x10]; 1773 1774 u8 out_of_seq_cnt[0x1]; 1775 u8 vport_counters[0x1]; 1776 u8 retransmission_q_counters[0x1]; 1777 u8 debug[0x1]; 1778 u8 modify_rq_counter_set_id[0x1]; 1779 u8 rq_delay_drop[0x1]; 1780 u8 max_qp_cnt[0xa]; 1781 u8 pkey_table_size[0x10]; 1782 1783 u8 vport_group_manager[0x1]; 1784 u8 vhca_group_manager[0x1]; 1785 u8 ib_virt[0x1]; 1786 u8 eth_virt[0x1]; 1787 u8 vnic_env_queue_counters[0x1]; 1788 u8 ets[0x1]; 1789 u8 nic_flow_table[0x1]; 1790 u8 eswitch_manager[0x1]; 1791 u8 device_memory[0x1]; 1792 u8 mcam_reg[0x1]; 1793 u8 pcam_reg[0x1]; 1794 u8 local_ca_ack_delay[0x5]; 1795 u8 port_module_event[0x1]; 1796 u8 enhanced_error_q_counters[0x1]; 1797 u8 ports_check[0x1]; 1798 u8 reserved_at_1b3[0x1]; 1799 u8 disable_link_up[0x1]; 1800 u8 beacon_led[0x1]; 1801 u8 port_type[0x2]; 1802 u8 num_ports[0x8]; 1803 1804 u8 reserved_at_1c0[0x1]; 1805 u8 pps[0x1]; 1806 u8 pps_modify[0x1]; 1807 u8 log_max_msg[0x5]; 1808 u8 reserved_at_1c8[0x4]; 1809 u8 max_tc[0x4]; 1810 u8 temp_warn_event[0x1]; 1811 u8 dcbx[0x1]; 1812 u8 general_notification_event[0x1]; 1813 u8 reserved_at_1d3[0x2]; 1814 u8 fpga[0x1]; 1815 u8 rol_s[0x1]; 1816 u8 rol_g[0x1]; 1817 u8 reserved_at_1d8[0x1]; 1818 u8 wol_s[0x1]; 1819 u8 wol_g[0x1]; 1820 u8 wol_a[0x1]; 1821 u8 wol_b[0x1]; 1822 u8 wol_m[0x1]; 1823 u8 wol_u[0x1]; 1824 u8 wol_p[0x1]; 1825 1826 u8 stat_rate_support[0x10]; 1827 u8 reserved_at_1f0[0x1]; 1828 u8 pci_sync_for_fw_update_event[0x1]; 1829 u8 reserved_at_1f2[0x6]; 1830 u8 init2_lag_tx_port_affinity[0x1]; 1831 u8 reserved_at_1fa[0x2]; 1832 u8 wqe_based_flow_table_update_cap[0x1]; 1833 u8 cqe_version[0x4]; 1834 1835 u8 compact_address_vector[0x1]; 1836 u8 striding_rq[0x1]; 1837 u8 reserved_at_202[0x1]; 1838 u8 ipoib_enhanced_offloads[0x1]; 1839 u8 ipoib_basic_offloads[0x1]; 1840 u8 reserved_at_205[0x1]; 1841 u8 repeated_block_disabled[0x1]; 1842 u8 umr_modify_entity_size_disabled[0x1]; 1843 u8 umr_modify_atomic_disabled[0x1]; 1844 u8 umr_indirect_mkey_disabled[0x1]; 1845 u8 umr_fence[0x2]; 1846 u8 dc_req_scat_data_cqe[0x1]; 1847 u8 reserved_at_20d[0x2]; 1848 u8 drain_sigerr[0x1]; 1849 u8 cmdif_checksum[0x2]; 1850 u8 sigerr_cqe[0x1]; 1851 u8 reserved_at_213[0x1]; 1852 u8 wq_signature[0x1]; 1853 u8 sctr_data_cqe[0x1]; 1854 u8 reserved_at_216[0x1]; 1855 u8 sho[0x1]; 1856 u8 tph[0x1]; 1857 u8 rf[0x1]; 1858 u8 dct[0x1]; 1859 u8 qos[0x1]; 1860 u8 eth_net_offloads[0x1]; 1861 u8 roce[0x1]; 1862 u8 atomic[0x1]; 1863 u8 reserved_at_21f[0x1]; 1864 1865 u8 cq_oi[0x1]; 1866 u8 cq_resize[0x1]; 1867 u8 cq_moderation[0x1]; 1868 u8 cq_period_mode_modify[0x1]; 1869 u8 reserved_at_224[0x2]; 1870 u8 cq_eq_remap[0x1]; 1871 u8 pg[0x1]; 1872 u8 block_lb_mc[0x1]; 1873 u8 reserved_at_229[0x1]; 1874 u8 scqe_break_moderation[0x1]; 1875 u8 cq_period_start_from_cqe[0x1]; 1876 u8 cd[0x1]; 1877 u8 reserved_at_22d[0x1]; 1878 u8 apm[0x1]; 1879 u8 vector_calc[0x1]; 1880 u8 umr_ptr_rlky[0x1]; 1881 u8 imaicl[0x1]; 1882 u8 qp_packet_based[0x1]; 1883 u8 reserved_at_233[0x3]; 1884 u8 qkv[0x1]; 1885 u8 pkv[0x1]; 1886 u8 set_deth_sqpn[0x1]; 1887 u8 reserved_at_239[0x3]; 1888 u8 xrc[0x1]; 1889 u8 ud[0x1]; 1890 u8 uc[0x1]; 1891 u8 rc[0x1]; 1892 1893 u8 uar_4k[0x1]; 1894 u8 reserved_at_241[0x7]; 1895 u8 fl_rc_qp_when_roce_disabled[0x1]; 1896 u8 regexp_params[0x1]; 1897 u8 uar_sz[0x6]; 1898 u8 port_selection_cap[0x1]; 1899 u8 nic_cap_reg[0x1]; 1900 u8 umem_uid_0[0x1]; 1901 u8 reserved_at_253[0x5]; 1902 u8 log_pg_sz[0x8]; 1903 1904 u8 bf[0x1]; 1905 u8 driver_version[0x1]; 1906 u8 pad_tx_eth_packet[0x1]; 1907 u8 reserved_at_263[0x3]; 1908 u8 mkey_by_name[0x1]; 1909 u8 reserved_at_267[0x4]; 1910 1911 u8 log_bf_reg_size[0x5]; 1912 1913 u8 disciplined_fr_counter[0x1]; 1914 u8 reserved_at_271[0x2]; 1915 u8 qp_error_syndrome[0x1]; 1916 u8 reserved_at_274[0x2]; 1917 u8 lag_dct[0x2]; 1918 u8 lag_tx_port_affinity[0x1]; 1919 u8 lag_native_fdb_selection[0x1]; 1920 u8 reserved_at_27a[0x1]; 1921 u8 lag_master[0x1]; 1922 u8 num_lag_ports[0x4]; 1923 1924 u8 reserved_at_280[0x10]; 1925 u8 max_wqe_sz_sq[0x10]; 1926 1927 u8 icm_mng_function_id_mode[0x1]; 1928 u8 reserved_at_2a1[0x6]; 1929 u8 mkey_pcie_tph[0x1]; 1930 u8 reserved_at_2a8[0x1]; 1931 u8 tis_tir_td_order[0x1]; 1932 1933 u8 psp[0x1]; 1934 u8 shampo[0x1]; 1935 u8 reserved_at_2ac[0x4]; 1936 u8 max_wqe_sz_rq[0x10]; 1937 1938 u8 max_flow_counter_31_16[0x10]; 1939 u8 max_wqe_sz_sq_dc[0x10]; 1940 1941 u8 query_host_net_function_num_max[0x5]; 1942 u8 reserved_at_2e5[0x2]; 1943 u8 max_qp_mcg[0x19]; 1944 1945 u8 reserved_at_300[0x10]; 1946 u8 flow_counter_bulk_alloc[0x8]; 1947 u8 log_max_mcg[0x8]; 1948 1949 u8 reserved_at_320[0x3]; 1950 u8 log_max_transport_domain[0x5]; 1951 u8 reserved_at_328[0x2]; 1952 u8 relaxed_ordering_read[0x1]; 1953 u8 log_max_pd[0x5]; 1954 u8 dp_ordering_ooo_all_ud[0x1]; 1955 u8 dp_ordering_ooo_all_uc[0x1]; 1956 u8 dp_ordering_ooo_all_xrc[0x1]; 1957 u8 dp_ordering_ooo_all_dc[0x1]; 1958 u8 dp_ordering_ooo_all_rc[0x1]; 1959 u8 pcie_reset_using_hotreset_method[0x1]; 1960 u8 pci_sync_for_fw_update_with_driver_unload[0x1]; 1961 u8 vnic_env_cnt_steering_fail[0x1]; 1962 u8 vport_counter_local_loopback[0x1]; 1963 u8 q_counter_aggregation[0x1]; 1964 u8 q_counter_other_vport[0x1]; 1965 u8 log_max_xrcd[0x5]; 1966 1967 u8 nic_receive_steering_discard[0x1]; 1968 u8 receive_discard_vport_down[0x1]; 1969 u8 transmit_discard_vport_down[0x1]; 1970 u8 eq_overrun_count[0x1]; 1971 u8 reserved_at_344[0x1]; 1972 u8 invalid_command_count[0x1]; 1973 u8 quota_exceeded_count[0x1]; 1974 u8 reserved_at_347[0x1]; 1975 u8 log_max_flow_counter_bulk[0x8]; 1976 u8 max_flow_counter_15_0[0x10]; 1977 1978 1979 u8 reserved_at_360[0x3]; 1980 u8 log_max_rq[0x5]; 1981 u8 ft_alias_sw_vhca_id[0x1]; 1982 u8 reserved_at_369[0x2]; 1983 u8 log_max_sq[0x5]; 1984 u8 reserved_at_370[0x3]; 1985 u8 log_max_tir[0x5]; 1986 u8 reserved_at_378[0x3]; 1987 u8 log_max_tis[0x5]; 1988 1989 u8 basic_cyclic_rcv_wqe[0x1]; 1990 u8 reserved_at_381[0x2]; 1991 u8 log_max_rmp[0x5]; 1992 u8 sd_group_size[0x1]; 1993 u8 reserved_at_389[0x2]; 1994 u8 log_max_rqt[0x5]; 1995 u8 reserved_at_390[0x3]; 1996 u8 log_max_rqt_size[0x5]; 1997 u8 tlp_device_emulation_manager[0x1]; 1998 u8 vnic_env_cnt_bar_uar_access[0x1]; 1999 u8 vnic_env_cnt_odp_page_fault[0x1]; 2000 u8 log_max_tis_per_sq[0x5]; 2001 2002 u8 ext_stride_num_range[0x1]; 2003 u8 roce_rw_supported[0x1]; 2004 u8 log_max_current_uc_list_wr_supported[0x1]; 2005 u8 log_max_stride_sz_rq[0x5]; 2006 u8 reserved_at_3a8[0x3]; 2007 u8 log_min_stride_sz_rq[0x5]; 2008 u8 reserved_at_3b0[0x3]; 2009 u8 log_max_stride_sz_sq[0x5]; 2010 u8 reserved_at_3b8[0x3]; 2011 u8 log_min_stride_sz_sq[0x5]; 2012 2013 u8 hairpin[0x1]; 2014 u8 reserved_at_3c1[0x2]; 2015 u8 log_max_hairpin_queues[0x5]; 2016 u8 reserved_at_3c8[0x3]; 2017 u8 log_max_hairpin_wq_data_sz[0x5]; 2018 u8 reserved_at_3d0[0x3]; 2019 u8 log_max_hairpin_num_packets[0x5]; 2020 u8 reserved_at_3d8[0x3]; 2021 u8 log_max_wq_sz[0x5]; 2022 2023 u8 nic_vport_change_event[0x1]; 2024 u8 disable_local_lb_uc[0x1]; 2025 u8 disable_local_lb_mc[0x1]; 2026 u8 log_min_hairpin_wq_data_sz[0x5]; 2027 u8 reserved_at_3e8[0x1]; 2028 u8 silent_mode_set[0x1]; 2029 u8 vhca_state[0x1]; 2030 u8 log_max_vlan_list[0x5]; 2031 u8 reserved_at_3f0[0x3]; 2032 u8 log_max_current_mc_list[0x5]; 2033 u8 reserved_at_3f8[0x1]; 2034 u8 silent_mode_query[0x1]; 2035 u8 query_host_net_function_v1[0x1]; 2036 u8 log_max_current_uc_list[0x5]; 2037 2038 u8 general_obj_types[0x40]; 2039 2040 u8 sq_ts_format[0x2]; 2041 u8 rq_ts_format[0x2]; 2042 u8 steering_format_version[0x4]; 2043 u8 create_qp_start_hint[0x18]; 2044 2045 u8 reserved_at_460[0x1]; 2046 u8 ats[0x1]; 2047 u8 cross_vhca_rqt[0x1]; 2048 u8 log_max_uctx[0x5]; 2049 u8 reserved_at_468[0x1]; 2050 u8 crypto[0x1]; 2051 u8 ipsec_offload[0x1]; 2052 u8 log_max_umem[0x5]; 2053 u8 max_num_eqs[0x10]; 2054 2055 u8 reserved_at_480[0x1]; 2056 u8 tls_tx[0x1]; 2057 u8 tls_rx[0x1]; 2058 u8 log_max_l2_table[0x5]; 2059 u8 reserved_at_488[0x8]; 2060 u8 log_uar_page_sz[0x10]; 2061 2062 u8 reserved_at_4a0[0x20]; 2063 u8 device_frequency_mhz[0x20]; 2064 u8 device_frequency_khz[0x20]; 2065 2066 u8 reserved_at_500[0x20]; 2067 u8 num_of_uars_per_page[0x20]; 2068 2069 u8 flex_parser_protocols[0x20]; 2070 2071 u8 max_geneve_tlv_options[0x8]; 2072 u8 reserved_at_568[0x3]; 2073 u8 max_geneve_tlv_option_data_len[0x5]; 2074 u8 reserved_at_570[0x1]; 2075 u8 adv_rdma[0x1]; 2076 u8 reserved_at_572[0x7]; 2077 u8 adv_virtualization[0x1]; 2078 u8 reserved_at_57a[0x6]; 2079 2080 u8 reserved_at_580[0xb]; 2081 u8 log_max_dci_stream_channels[0x5]; 2082 u8 reserved_at_590[0x3]; 2083 u8 log_max_dci_errored_streams[0x5]; 2084 u8 reserved_at_598[0x8]; 2085 2086 u8 reserved_at_5a0[0x10]; 2087 u8 enhanced_cqe_compression[0x1]; 2088 u8 reserved_at_5b1[0x1]; 2089 u8 crossing_vhca_mkey[0x1]; 2090 u8 log_max_dek[0x5]; 2091 u8 reserved_at_5b8[0x4]; 2092 u8 mini_cqe_resp_stride_index[0x1]; 2093 u8 cqe_128_always[0x1]; 2094 u8 cqe_compression_128[0x1]; 2095 u8 cqe_compression[0x1]; 2096 2097 u8 cqe_compression_timeout[0x10]; 2098 u8 cqe_compression_max_num[0x10]; 2099 2100 u8 reserved_at_5e0[0x8]; 2101 u8 flex_parser_id_gtpu_dw_0[0x4]; 2102 u8 reserved_at_5ec[0x4]; 2103 u8 tag_matching[0x1]; 2104 u8 rndv_offload_rc[0x1]; 2105 u8 rndv_offload_dc[0x1]; 2106 u8 log_tag_matching_list_sz[0x5]; 2107 u8 reserved_at_5f8[0x3]; 2108 u8 log_max_xrq[0x5]; 2109 2110 u8 affiliate_nic_vport_criteria[0x8]; 2111 u8 native_port_num[0x8]; 2112 u8 num_vhca_ports[0x8]; 2113 u8 flex_parser_id_gtpu_teid[0x4]; 2114 u8 reserved_at_61c[0x2]; 2115 u8 sw_owner_id[0x1]; 2116 u8 reserved_at_61f[0x1]; 2117 2118 u8 max_num_of_monitor_counters[0x10]; 2119 u8 num_ppcnt_monitor_counters[0x10]; 2120 2121 u8 max_num_sf[0x10]; 2122 u8 num_q_monitor_counters[0x10]; 2123 2124 u8 reserved_at_660[0x20]; 2125 2126 u8 sf[0x1]; 2127 u8 sf_set_partition[0x1]; 2128 u8 reserved_at_682[0x1]; 2129 u8 log_max_sf[0x5]; 2130 u8 apu[0x1]; 2131 u8 reserved_at_689[0x4]; 2132 u8 migration[0x1]; 2133 u8 reserved_at_68e[0x2]; 2134 u8 log_min_sf_size[0x8]; 2135 u8 max_num_sf_partitions[0x8]; 2136 2137 u8 uctx_cap[0x20]; 2138 2139 u8 reserved_at_6c0[0x4]; 2140 u8 flex_parser_id_geneve_tlv_option_0[0x4]; 2141 u8 flex_parser_id_icmp_dw1[0x4]; 2142 u8 flex_parser_id_icmp_dw0[0x4]; 2143 u8 flex_parser_id_icmpv6_dw1[0x4]; 2144 u8 flex_parser_id_icmpv6_dw0[0x4]; 2145 u8 flex_parser_id_outer_first_mpls_over_gre[0x4]; 2146 u8 flex_parser_id_outer_first_mpls_over_udp_label[0x4]; 2147 2148 u8 max_num_match_definer[0x10]; 2149 u8 sf_base_id[0x10]; 2150 2151 u8 flex_parser_id_gtpu_dw_2[0x4]; 2152 u8 flex_parser_id_gtpu_first_ext_dw_0[0x4]; 2153 u8 num_total_dynamic_vf_msix[0x18]; 2154 u8 reserved_at_720[0x14]; 2155 u8 dynamic_msix_table_size[0xc]; 2156 u8 reserved_at_740[0xc]; 2157 u8 min_dynamic_vf_msix_table_size[0x4]; 2158 u8 reserved_at_750[0x2]; 2159 u8 data_direct[0x1]; 2160 u8 reserved_at_753[0x1]; 2161 u8 max_dynamic_vf_msix_table_size[0xc]; 2162 2163 u8 reserved_at_760[0x3]; 2164 u8 log_max_num_header_modify_argument[0x5]; 2165 u8 log_header_modify_argument_granularity_offset[0x4]; 2166 u8 log_header_modify_argument_granularity[0x4]; 2167 u8 reserved_at_770[0x3]; 2168 u8 log_header_modify_argument_max_alloc[0x5]; 2169 u8 reserved_at_778[0x8]; 2170 2171 u8 vhca_tunnel_commands[0x40]; 2172 u8 match_definer_format_supported[0x40]; 2173 }; 2174 2175 enum { 2176 MLX5_CROSS_VHCA_OBJ_TO_OBJ_SUPPORTED_LOCAL_FLOW_TABLE_TO_REMOTE_FLOW_TABLE_MISS = 0x80000, 2177 MLX5_CROSS_VHCA_OBJ_TO_OBJ_SUPPORTED_LOCAL_FLOW_TABLE_ROOT_TO_REMOTE_FLOW_TABLE = (1ULL << 20), 2178 }; 2179 2180 enum { 2181 MLX5_ALLOWED_OBJ_FOR_OTHER_VHCA_ACCESS_FLOW_TABLE = 0x200, 2182 }; 2183 2184 struct mlx5_ifc_cmd_hca_cap_2_bits { 2185 u8 reserved_at_0[0x80]; 2186 2187 u8 migratable[0x1]; 2188 u8 reserved_at_81[0x7]; 2189 u8 dp_ordering_force[0x1]; 2190 u8 reserved_at_89[0x9]; 2191 u8 query_vuid[0x1]; 2192 u8 reserved_at_93[0x5]; 2193 u8 umr_log_entity_size_5[0x1]; 2194 u8 reserved_at_99[0x7]; 2195 2196 u8 max_reformat_insert_size[0x8]; 2197 u8 max_reformat_insert_offset[0x8]; 2198 u8 max_reformat_remove_size[0x8]; 2199 u8 max_reformat_remove_offset[0x8]; 2200 2201 u8 reserved_at_c0[0x8]; 2202 u8 migration_multi_load[0x1]; 2203 u8 migration_tracking_state[0x1]; 2204 u8 multiplane_qp_ud[0x1]; 2205 u8 reserved_at_cb[0x5]; 2206 u8 migration_in_chunks[0x1]; 2207 u8 reserved_at_d1[0x1]; 2208 u8 sf_eq_usage[0x1]; 2209 u8 reserved_at_d3[0x5]; 2210 u8 multiplane[0x1]; 2211 u8 migration_state[0x1]; 2212 u8 reserved_at_da[0x6]; 2213 2214 u8 cross_vhca_object_to_object_supported[0x20]; 2215 2216 u8 allowed_object_for_other_vhca_access[0x40]; 2217 2218 u8 reserved_at_140[0x60]; 2219 2220 u8 flow_table_type_2_type[0x8]; 2221 u8 reserved_at_1a8[0x2]; 2222 u8 format_select_dw_8_6_ext[0x1]; 2223 u8 log_min_mkey_entity_size[0x5]; 2224 u8 reserved_at_1b0[0x10]; 2225 2226 u8 general_obj_types_127_64[0x40]; 2227 u8 reserved_at_200[0x20]; 2228 2229 u8 reserved_at_220[0x1]; 2230 u8 sw_vhca_id_valid[0x1]; 2231 u8 sw_vhca_id[0xe]; 2232 u8 reserved_at_230[0x10]; 2233 2234 u8 reserved_at_240[0xb]; 2235 u8 ts_cqe_metadata_size2wqe_counter[0x5]; 2236 u8 reserved_at_250[0x10]; 2237 2238 u8 reserved_at_260[0x20]; 2239 2240 u8 format_select_dw_gtpu_dw_0[0x8]; 2241 u8 format_select_dw_gtpu_dw_1[0x8]; 2242 u8 format_select_dw_gtpu_dw_2[0x8]; 2243 u8 format_select_dw_gtpu_first_ext_dw_0[0x8]; 2244 2245 u8 generate_wqe_type[0x20]; 2246 2247 u8 reserved_at_2c0[0xc0]; 2248 2249 u8 reserved_at_380[0xb]; 2250 u8 min_mkey_log_entity_size_fixed_buffer[0x5]; 2251 u8 ec_vf_vport_base[0x10]; 2252 2253 u8 reserved_at_3a0[0x2]; 2254 u8 max_mkey_log_entity_size_fixed_buffer[0x6]; 2255 u8 reserved_at_3a8[0x2]; 2256 u8 max_mkey_log_entity_size_mtt[0x6]; 2257 u8 max_rqt_vhca_id[0x10]; 2258 2259 u8 reserved_at_3c0[0x20]; 2260 2261 u8 reserved_at_3e0[0x10]; 2262 u8 pcc_ifa2[0x1]; 2263 u8 reserved_at_3f1[0xf]; 2264 2265 u8 reserved_at_400[0x1]; 2266 u8 min_mkey_log_entity_size_fixed_buffer_valid[0x1]; 2267 u8 reserved_at_402[0xe]; 2268 u8 return_reg_id[0x10]; 2269 2270 u8 reserved_at_420[0x1c]; 2271 u8 flow_table_hash_type[0x4]; 2272 2273 u8 reserved_at_440[0x8]; 2274 u8 max_num_eqs_24b[0x18]; 2275 2276 u8 reserved_at_460[0x144]; 2277 u8 load_balance_id[0x4]; 2278 u8 reserved_at_5a8[0x18]; 2279 2280 u8 query_adjacent_functions_id[0x1]; 2281 u8 ingress_egress_esw_vport_connect[0x1]; 2282 u8 function_id_type_vhca_id[0x1]; 2283 u8 reserved_at_5c3[0x1]; 2284 u8 lag_per_mp_group[0x1]; 2285 u8 reserved_at_5c5[0xb]; 2286 u8 delegate_vhca_management_profiles[0x10]; 2287 2288 u8 delegated_vhca_max[0x10]; 2289 u8 delegate_vhca_max[0x10]; 2290 2291 u8 reserved_at_600[0x200]; 2292 }; 2293 2294 enum mlx5_ifc_flow_destination_type { 2295 MLX5_IFC_FLOW_DESTINATION_TYPE_VPORT = 0x0, 2296 MLX5_IFC_FLOW_DESTINATION_TYPE_FLOW_TABLE = 0x1, 2297 MLX5_IFC_FLOW_DESTINATION_TYPE_TIR = 0x2, 2298 MLX5_IFC_FLOW_DESTINATION_TYPE_VHCA_RX = 0x4, 2299 MLX5_IFC_FLOW_DESTINATION_TYPE_FLOW_SAMPLER = 0x6, 2300 MLX5_IFC_FLOW_DESTINATION_TYPE_UPLINK = 0x8, 2301 MLX5_IFC_FLOW_DESTINATION_TYPE_TABLE_TYPE = 0xA, 2302 }; 2303 2304 enum mlx5_flow_table_miss_action { 2305 MLX5_FLOW_TABLE_MISS_ACTION_DEF, 2306 MLX5_FLOW_TABLE_MISS_ACTION_FWD, 2307 MLX5_FLOW_TABLE_MISS_ACTION_SWITCH_DOMAIN, 2308 }; 2309 2310 struct mlx5_ifc_dest_format_struct_bits { 2311 u8 destination_type[0x8]; 2312 u8 destination_id[0x18]; 2313 2314 u8 destination_eswitch_owner_vhca_id_valid[0x1]; 2315 u8 packet_reformat[0x1]; 2316 u8 reserved_at_22[0x6]; 2317 u8 destination_table_type[0x8]; 2318 u8 destination_eswitch_owner_vhca_id[0x10]; 2319 }; 2320 2321 struct mlx5_ifc_flow_counter_list_bits { 2322 u8 flow_counter_id[0x20]; 2323 2324 u8 reserved_at_20[0x20]; 2325 }; 2326 2327 struct mlx5_ifc_extended_dest_format_bits { 2328 struct mlx5_ifc_dest_format_struct_bits destination_entry; 2329 2330 u8 packet_reformat_id[0x20]; 2331 2332 u8 reserved_at_60[0x20]; 2333 }; 2334 2335 union mlx5_ifc_dest_format_flow_counter_list_auto_bits { 2336 struct mlx5_ifc_extended_dest_format_bits extended_dest_format; 2337 struct mlx5_ifc_flow_counter_list_bits flow_counter_list; 2338 }; 2339 2340 struct mlx5_ifc_fte_match_param_bits { 2341 struct mlx5_ifc_fte_match_set_lyr_2_4_bits outer_headers; 2342 2343 struct mlx5_ifc_fte_match_set_misc_bits misc_parameters; 2344 2345 struct mlx5_ifc_fte_match_set_lyr_2_4_bits inner_headers; 2346 2347 struct mlx5_ifc_fte_match_set_misc2_bits misc_parameters_2; 2348 2349 struct mlx5_ifc_fte_match_set_misc3_bits misc_parameters_3; 2350 2351 struct mlx5_ifc_fte_match_set_misc4_bits misc_parameters_4; 2352 2353 struct mlx5_ifc_fte_match_set_misc5_bits misc_parameters_5; 2354 2355 struct mlx5_ifc_fte_match_set_misc6_bits misc_parameters_6; 2356 }; 2357 2358 enum { 2359 MLX5_RX_HASH_FIELD_SELECT_SELECTED_FIELDS_SRC_IP = 0x0, 2360 MLX5_RX_HASH_FIELD_SELECT_SELECTED_FIELDS_DST_IP = 0x1, 2361 MLX5_RX_HASH_FIELD_SELECT_SELECTED_FIELDS_L4_SPORT = 0x2, 2362 MLX5_RX_HASH_FIELD_SELECT_SELECTED_FIELDS_L4_DPORT = 0x3, 2363 MLX5_RX_HASH_FIELD_SELECT_SELECTED_FIELDS_IPSEC_SPI = 0x4, 2364 }; 2365 2366 struct mlx5_ifc_rx_hash_field_select_bits { 2367 u8 l3_prot_type[0x1]; 2368 u8 l4_prot_type[0x1]; 2369 u8 selected_fields[0x1e]; 2370 }; 2371 2372 enum { 2373 MLX5_WQ_WQ_TYPE_WQ_LINKED_LIST = 0x0, 2374 MLX5_WQ_WQ_TYPE_WQ_CYCLIC = 0x1, 2375 }; 2376 2377 enum { 2378 MLX5_WQ_END_PADDING_MODE_END_PAD_NONE = 0x0, 2379 MLX5_WQ_END_PADDING_MODE_END_PAD_ALIGN = 0x1, 2380 }; 2381 2382 struct mlx5_ifc_wq_bits { 2383 u8 wq_type[0x4]; 2384 u8 wq_signature[0x1]; 2385 u8 end_padding_mode[0x2]; 2386 u8 cd_slave[0x1]; 2387 u8 reserved_at_8[0x18]; 2388 2389 u8 hds_skip_first_sge[0x1]; 2390 u8 log2_hds_buf_size[0x3]; 2391 u8 reserved_at_24[0x7]; 2392 u8 page_offset[0x5]; 2393 u8 lwm[0x10]; 2394 2395 u8 reserved_at_40[0x8]; 2396 u8 pd[0x18]; 2397 2398 u8 reserved_at_60[0x8]; 2399 u8 uar_page[0x18]; 2400 2401 u8 dbr_addr[0x40]; 2402 2403 u8 hw_counter[0x20]; 2404 2405 u8 sw_counter[0x20]; 2406 2407 u8 reserved_at_100[0xc]; 2408 u8 log_wq_stride[0x4]; 2409 u8 reserved_at_110[0x3]; 2410 u8 log_wq_pg_sz[0x5]; 2411 u8 reserved_at_118[0x3]; 2412 u8 log_wq_sz[0x5]; 2413 2414 u8 dbr_umem_valid[0x1]; 2415 u8 wq_umem_valid[0x1]; 2416 u8 reserved_at_122[0x1]; 2417 u8 log_hairpin_num_packets[0x5]; 2418 u8 reserved_at_128[0x3]; 2419 u8 log_hairpin_data_sz[0x5]; 2420 2421 u8 reserved_at_130[0x4]; 2422 u8 log_wqe_num_of_strides[0x4]; 2423 u8 two_byte_shift_en[0x1]; 2424 u8 reserved_at_139[0x4]; 2425 u8 log_wqe_stride_size[0x3]; 2426 2427 u8 dbr_umem_id[0x20]; 2428 u8 wq_umem_id[0x20]; 2429 2430 u8 wq_umem_offset[0x40]; 2431 2432 u8 headers_mkey[0x20]; 2433 2434 u8 shampo_enable[0x1]; 2435 u8 reserved_at_1e1[0x1]; 2436 u8 shampo_mode[0x2]; 2437 u8 reserved_at_1e4[0x1]; 2438 u8 log_reservation_size[0x3]; 2439 u8 reserved_at_1e8[0x5]; 2440 u8 log_max_num_of_packets_per_reservation[0x3]; 2441 u8 reserved_at_1f0[0x6]; 2442 u8 log_headers_entry_size[0x2]; 2443 u8 reserved_at_1f8[0x4]; 2444 u8 log_headers_buffer_entry_num[0x4]; 2445 2446 u8 reserved_at_200[0x400]; 2447 2448 struct mlx5_ifc_cmd_pas_bits pas[]; 2449 }; 2450 2451 struct mlx5_ifc_rq_num_bits { 2452 u8 reserved_at_0[0x8]; 2453 u8 rq_num[0x18]; 2454 }; 2455 2456 struct mlx5_ifc_rq_vhca_bits { 2457 u8 reserved_at_0[0x8]; 2458 u8 rq_num[0x18]; 2459 u8 reserved_at_20[0x10]; 2460 u8 rq_vhca_id[0x10]; 2461 }; 2462 2463 struct mlx5_ifc_mac_address_layout_bits { 2464 u8 reserved_at_0[0x10]; 2465 u8 mac_addr_47_32[0x10]; 2466 2467 u8 mac_addr_31_0[0x20]; 2468 }; 2469 2470 struct mlx5_ifc_vlan_layout_bits { 2471 u8 reserved_at_0[0x14]; 2472 u8 vlan[0x0c]; 2473 2474 u8 reserved_at_20[0x20]; 2475 }; 2476 2477 struct mlx5_ifc_cong_control_r_roce_ecn_np_bits { 2478 u8 reserved_at_0[0xa0]; 2479 2480 u8 min_time_between_cnps[0x20]; 2481 2482 u8 reserved_at_c0[0x12]; 2483 u8 cnp_dscp[0x6]; 2484 u8 reserved_at_d8[0x4]; 2485 u8 cnp_prio_mode[0x1]; 2486 u8 cnp_802p_prio[0x3]; 2487 2488 u8 reserved_at_e0[0x720]; 2489 }; 2490 2491 struct mlx5_ifc_cong_control_r_roce_ecn_rp_bits { 2492 u8 reserved_at_0[0x60]; 2493 2494 u8 reserved_at_60[0x4]; 2495 u8 clamp_tgt_rate[0x1]; 2496 u8 reserved_at_65[0x3]; 2497 u8 clamp_tgt_rate_after_time_inc[0x1]; 2498 u8 reserved_at_69[0x17]; 2499 2500 u8 reserved_at_80[0x20]; 2501 2502 u8 rpg_time_reset[0x20]; 2503 2504 u8 rpg_byte_reset[0x20]; 2505 2506 u8 rpg_threshold[0x20]; 2507 2508 u8 rpg_max_rate[0x20]; 2509 2510 u8 rpg_ai_rate[0x20]; 2511 2512 u8 rpg_hai_rate[0x20]; 2513 2514 u8 rpg_gd[0x20]; 2515 2516 u8 rpg_min_dec_fac[0x20]; 2517 2518 u8 rpg_min_rate[0x20]; 2519 2520 u8 reserved_at_1c0[0xe0]; 2521 2522 u8 rate_to_set_on_first_cnp[0x20]; 2523 2524 u8 dce_tcp_g[0x20]; 2525 2526 u8 dce_tcp_rtt[0x20]; 2527 2528 u8 rate_reduce_monitor_period[0x20]; 2529 2530 u8 reserved_at_320[0x20]; 2531 2532 u8 initial_alpha_value[0x20]; 2533 2534 u8 reserved_at_360[0x4a0]; 2535 }; 2536 2537 struct mlx5_ifc_cong_control_r_roce_general_bits { 2538 u8 reserved_at_0[0x80]; 2539 2540 u8 reserved_at_80[0x10]; 2541 u8 rtt_resp_dscp_valid[0x1]; 2542 u8 reserved_at_91[0x9]; 2543 u8 rtt_resp_dscp[0x6]; 2544 2545 u8 reserved_at_a0[0x760]; 2546 }; 2547 2548 struct mlx5_ifc_cong_control_802_1qau_rp_bits { 2549 u8 reserved_at_0[0x80]; 2550 2551 u8 rppp_max_rps[0x20]; 2552 2553 u8 rpg_time_reset[0x20]; 2554 2555 u8 rpg_byte_reset[0x20]; 2556 2557 u8 rpg_threshold[0x20]; 2558 2559 u8 rpg_max_rate[0x20]; 2560 2561 u8 rpg_ai_rate[0x20]; 2562 2563 u8 rpg_hai_rate[0x20]; 2564 2565 u8 rpg_gd[0x20]; 2566 2567 u8 rpg_min_dec_fac[0x20]; 2568 2569 u8 rpg_min_rate[0x20]; 2570 2571 u8 reserved_at_1c0[0x640]; 2572 }; 2573 2574 enum { 2575 MLX5_RESIZE_FIELD_SELECT_RESIZE_FIELD_SELECT_LOG_CQ_SIZE = 0x1, 2576 MLX5_RESIZE_FIELD_SELECT_RESIZE_FIELD_SELECT_PAGE_OFFSET = 0x2, 2577 MLX5_RESIZE_FIELD_SELECT_RESIZE_FIELD_SELECT_LOG_PAGE_SIZE = 0x4, 2578 }; 2579 2580 struct mlx5_ifc_resize_field_select_bits { 2581 u8 resize_field_select[0x20]; 2582 }; 2583 2584 struct mlx5_ifc_resource_dump_bits { 2585 u8 more_dump[0x1]; 2586 u8 inline_dump[0x1]; 2587 u8 reserved_at_2[0xa]; 2588 u8 seq_num[0x4]; 2589 u8 segment_type[0x10]; 2590 2591 u8 reserved_at_20[0x10]; 2592 u8 vhca_id[0x10]; 2593 2594 u8 index1[0x20]; 2595 2596 u8 index2[0x20]; 2597 2598 u8 num_of_obj1[0x10]; 2599 u8 num_of_obj2[0x10]; 2600 2601 u8 reserved_at_a0[0x20]; 2602 2603 u8 device_opaque[0x40]; 2604 2605 u8 mkey[0x20]; 2606 2607 u8 size[0x20]; 2608 2609 u8 address[0x40]; 2610 2611 u8 inline_data[52][0x20]; 2612 }; 2613 2614 struct mlx5_ifc_resource_dump_menu_record_bits { 2615 u8 reserved_at_0[0x4]; 2616 u8 num_of_obj2_supports_active[0x1]; 2617 u8 num_of_obj2_supports_all[0x1]; 2618 u8 must_have_num_of_obj2[0x1]; 2619 u8 support_num_of_obj2[0x1]; 2620 u8 num_of_obj1_supports_active[0x1]; 2621 u8 num_of_obj1_supports_all[0x1]; 2622 u8 must_have_num_of_obj1[0x1]; 2623 u8 support_num_of_obj1[0x1]; 2624 u8 must_have_index2[0x1]; 2625 u8 support_index2[0x1]; 2626 u8 must_have_index1[0x1]; 2627 u8 support_index1[0x1]; 2628 u8 segment_type[0x10]; 2629 2630 u8 segment_name[4][0x20]; 2631 2632 u8 index1_name[4][0x20]; 2633 2634 u8 index2_name[4][0x20]; 2635 }; 2636 2637 struct mlx5_ifc_resource_dump_segment_header_bits { 2638 u8 length_dw[0x10]; 2639 u8 segment_type[0x10]; 2640 }; 2641 2642 struct mlx5_ifc_resource_dump_command_segment_bits { 2643 struct mlx5_ifc_resource_dump_segment_header_bits segment_header; 2644 2645 u8 segment_called[0x10]; 2646 u8 vhca_id[0x10]; 2647 2648 u8 index1[0x20]; 2649 2650 u8 index2[0x20]; 2651 2652 u8 num_of_obj1[0x10]; 2653 u8 num_of_obj2[0x10]; 2654 }; 2655 2656 struct mlx5_ifc_resource_dump_error_segment_bits { 2657 struct mlx5_ifc_resource_dump_segment_header_bits segment_header; 2658 2659 u8 reserved_at_20[0x10]; 2660 u8 syndrome_id[0x10]; 2661 2662 u8 reserved_at_40[0x40]; 2663 2664 u8 error[8][0x20]; 2665 }; 2666 2667 struct mlx5_ifc_resource_dump_info_segment_bits { 2668 struct mlx5_ifc_resource_dump_segment_header_bits segment_header; 2669 2670 u8 reserved_at_20[0x18]; 2671 u8 dump_version[0x8]; 2672 2673 u8 hw_version[0x20]; 2674 2675 u8 fw_version[0x20]; 2676 }; 2677 2678 struct mlx5_ifc_resource_dump_menu_segment_bits { 2679 struct mlx5_ifc_resource_dump_segment_header_bits segment_header; 2680 2681 u8 reserved_at_20[0x10]; 2682 u8 num_of_records[0x10]; 2683 2684 struct mlx5_ifc_resource_dump_menu_record_bits record[]; 2685 }; 2686 2687 struct mlx5_ifc_resource_dump_resource_segment_bits { 2688 struct mlx5_ifc_resource_dump_segment_header_bits segment_header; 2689 2690 u8 reserved_at_20[0x20]; 2691 2692 u8 index1[0x20]; 2693 2694 u8 index2[0x20]; 2695 2696 u8 payload[][0x20]; 2697 }; 2698 2699 struct mlx5_ifc_resource_dump_terminate_segment_bits { 2700 struct mlx5_ifc_resource_dump_segment_header_bits segment_header; 2701 }; 2702 2703 struct mlx5_ifc_menu_resource_dump_response_bits { 2704 struct mlx5_ifc_resource_dump_info_segment_bits info; 2705 struct mlx5_ifc_resource_dump_command_segment_bits cmd; 2706 struct mlx5_ifc_resource_dump_menu_segment_bits menu; 2707 struct mlx5_ifc_resource_dump_terminate_segment_bits terminate; 2708 }; 2709 2710 enum { 2711 MLX5_MODIFY_FIELD_SELECT_MODIFY_FIELD_SELECT_CQ_PERIOD = 0x1, 2712 MLX5_MODIFY_FIELD_SELECT_MODIFY_FIELD_SELECT_CQ_MAX_COUNT = 0x2, 2713 MLX5_MODIFY_FIELD_SELECT_MODIFY_FIELD_SELECT_OI = 0x4, 2714 MLX5_MODIFY_FIELD_SELECT_MODIFY_FIELD_SELECT_C_EQN = 0x8, 2715 }; 2716 2717 struct mlx5_ifc_modify_field_select_bits { 2718 u8 modify_field_select[0x20]; 2719 }; 2720 2721 struct mlx5_ifc_field_select_r_roce_np_bits { 2722 u8 field_select_r_roce_np[0x20]; 2723 }; 2724 2725 struct mlx5_ifc_field_select_r_roce_rp_bits { 2726 u8 field_select_r_roce_rp[0x20]; 2727 }; 2728 2729 enum { 2730 MLX5_FIELD_SELECT_802_1QAU_RP_FIELD_SELECT_8021QAURP_RPPP_MAX_RPS = 0x4, 2731 MLX5_FIELD_SELECT_802_1QAU_RP_FIELD_SELECT_8021QAURP_RPG_TIME_RESET = 0x8, 2732 MLX5_FIELD_SELECT_802_1QAU_RP_FIELD_SELECT_8021QAURP_RPG_BYTE_RESET = 0x10, 2733 MLX5_FIELD_SELECT_802_1QAU_RP_FIELD_SELECT_8021QAURP_RPG_THRESHOLD = 0x20, 2734 MLX5_FIELD_SELECT_802_1QAU_RP_FIELD_SELECT_8021QAURP_RPG_MAX_RATE = 0x40, 2735 MLX5_FIELD_SELECT_802_1QAU_RP_FIELD_SELECT_8021QAURP_RPG_AI_RATE = 0x80, 2736 MLX5_FIELD_SELECT_802_1QAU_RP_FIELD_SELECT_8021QAURP_RPG_HAI_RATE = 0x100, 2737 MLX5_FIELD_SELECT_802_1QAU_RP_FIELD_SELECT_8021QAURP_RPG_GD = 0x200, 2738 MLX5_FIELD_SELECT_802_1QAU_RP_FIELD_SELECT_8021QAURP_RPG_MIN_DEC_FAC = 0x400, 2739 MLX5_FIELD_SELECT_802_1QAU_RP_FIELD_SELECT_8021QAURP_RPG_MIN_RATE = 0x800, 2740 }; 2741 2742 struct mlx5_ifc_field_select_802_1qau_rp_bits { 2743 u8 field_select_8021qaurp[0x20]; 2744 }; 2745 2746 struct mlx5_ifc_phys_layer_recovery_cntrs_bits { 2747 u8 total_successful_recovery_events[0x20]; 2748 2749 u8 reserved_at_20[0x7a0]; 2750 }; 2751 2752 struct mlx5_ifc_phys_layer_cntrs_bits { 2753 u8 time_since_last_clear_high[0x20]; 2754 2755 u8 time_since_last_clear_low[0x20]; 2756 2757 u8 symbol_errors_high[0x20]; 2758 2759 u8 symbol_errors_low[0x20]; 2760 2761 u8 sync_headers_errors_high[0x20]; 2762 2763 u8 sync_headers_errors_low[0x20]; 2764 2765 u8 edpl_bip_errors_lane0_high[0x20]; 2766 2767 u8 edpl_bip_errors_lane0_low[0x20]; 2768 2769 u8 edpl_bip_errors_lane1_high[0x20]; 2770 2771 u8 edpl_bip_errors_lane1_low[0x20]; 2772 2773 u8 edpl_bip_errors_lane2_high[0x20]; 2774 2775 u8 edpl_bip_errors_lane2_low[0x20]; 2776 2777 u8 edpl_bip_errors_lane3_high[0x20]; 2778 2779 u8 edpl_bip_errors_lane3_low[0x20]; 2780 2781 u8 fc_fec_corrected_blocks_lane0_high[0x20]; 2782 2783 u8 fc_fec_corrected_blocks_lane0_low[0x20]; 2784 2785 u8 fc_fec_corrected_blocks_lane1_high[0x20]; 2786 2787 u8 fc_fec_corrected_blocks_lane1_low[0x20]; 2788 2789 u8 fc_fec_corrected_blocks_lane2_high[0x20]; 2790 2791 u8 fc_fec_corrected_blocks_lane2_low[0x20]; 2792 2793 u8 fc_fec_corrected_blocks_lane3_high[0x20]; 2794 2795 u8 fc_fec_corrected_blocks_lane3_low[0x20]; 2796 2797 u8 fc_fec_uncorrectable_blocks_lane0_high[0x20]; 2798 2799 u8 fc_fec_uncorrectable_blocks_lane0_low[0x20]; 2800 2801 u8 fc_fec_uncorrectable_blocks_lane1_high[0x20]; 2802 2803 u8 fc_fec_uncorrectable_blocks_lane1_low[0x20]; 2804 2805 u8 fc_fec_uncorrectable_blocks_lane2_high[0x20]; 2806 2807 u8 fc_fec_uncorrectable_blocks_lane2_low[0x20]; 2808 2809 u8 fc_fec_uncorrectable_blocks_lane3_high[0x20]; 2810 2811 u8 fc_fec_uncorrectable_blocks_lane3_low[0x20]; 2812 2813 u8 rs_fec_corrected_blocks_high[0x20]; 2814 2815 u8 rs_fec_corrected_blocks_low[0x20]; 2816 2817 u8 rs_fec_uncorrectable_blocks_high[0x20]; 2818 2819 u8 rs_fec_uncorrectable_blocks_low[0x20]; 2820 2821 u8 rs_fec_no_errors_blocks_high[0x20]; 2822 2823 u8 rs_fec_no_errors_blocks_low[0x20]; 2824 2825 u8 rs_fec_single_error_blocks_high[0x20]; 2826 2827 u8 rs_fec_single_error_blocks_low[0x20]; 2828 2829 u8 rs_fec_corrected_symbols_total_high[0x20]; 2830 2831 u8 rs_fec_corrected_symbols_total_low[0x20]; 2832 2833 u8 rs_fec_corrected_symbols_lane0_high[0x20]; 2834 2835 u8 rs_fec_corrected_symbols_lane0_low[0x20]; 2836 2837 u8 rs_fec_corrected_symbols_lane1_high[0x20]; 2838 2839 u8 rs_fec_corrected_symbols_lane1_low[0x20]; 2840 2841 u8 rs_fec_corrected_symbols_lane2_high[0x20]; 2842 2843 u8 rs_fec_corrected_symbols_lane2_low[0x20]; 2844 2845 u8 rs_fec_corrected_symbols_lane3_high[0x20]; 2846 2847 u8 rs_fec_corrected_symbols_lane3_low[0x20]; 2848 2849 u8 link_down_events[0x20]; 2850 2851 u8 successful_recovery_events[0x20]; 2852 2853 u8 reserved_at_640[0x180]; 2854 }; 2855 2856 struct mlx5_ifc_phys_layer_statistical_cntrs_bits { 2857 u8 time_since_last_clear_high[0x20]; 2858 2859 u8 time_since_last_clear_low[0x20]; 2860 2861 u8 phy_received_bits_high[0x20]; 2862 2863 u8 phy_received_bits_low[0x20]; 2864 2865 u8 phy_symbol_errors_high[0x20]; 2866 2867 u8 phy_symbol_errors_low[0x20]; 2868 2869 u8 phy_corrected_bits_high[0x20]; 2870 2871 u8 phy_corrected_bits_low[0x20]; 2872 2873 u8 phy_corrected_bits_lane0_high[0x20]; 2874 2875 u8 phy_corrected_bits_lane0_low[0x20]; 2876 2877 u8 phy_corrected_bits_lane1_high[0x20]; 2878 2879 u8 phy_corrected_bits_lane1_low[0x20]; 2880 2881 u8 phy_corrected_bits_lane2_high[0x20]; 2882 2883 u8 phy_corrected_bits_lane2_low[0x20]; 2884 2885 u8 phy_corrected_bits_lane3_high[0x20]; 2886 2887 u8 phy_corrected_bits_lane3_low[0x20]; 2888 2889 u8 reserved_at_200[0x5c0]; 2890 }; 2891 2892 struct mlx5_ifc_ib_port_cntrs_grp_data_layout_bits { 2893 u8 symbol_error_counter[0x10]; 2894 2895 u8 link_error_recovery_counter[0x8]; 2896 2897 u8 link_downed_counter[0x8]; 2898 2899 u8 port_rcv_errors[0x10]; 2900 2901 u8 port_rcv_remote_physical_errors[0x10]; 2902 2903 u8 port_rcv_switch_relay_errors[0x10]; 2904 2905 u8 port_xmit_discards[0x10]; 2906 2907 u8 port_xmit_constraint_errors[0x8]; 2908 2909 u8 port_rcv_constraint_errors[0x8]; 2910 2911 u8 reserved_at_70[0x8]; 2912 2913 u8 link_overrun_errors[0x8]; 2914 2915 u8 reserved_at_80[0x10]; 2916 2917 u8 vl_15_dropped[0x10]; 2918 2919 u8 reserved_at_a0[0x80]; 2920 2921 u8 port_xmit_wait[0x20]; 2922 }; 2923 2924 struct mlx5_ifc_ib_ext_port_cntrs_grp_data_layout_bits { 2925 u8 reserved_at_0[0x300]; 2926 2927 u8 port_xmit_data_high[0x20]; 2928 2929 u8 port_xmit_data_low[0x20]; 2930 2931 u8 port_rcv_data_high[0x20]; 2932 2933 u8 port_rcv_data_low[0x20]; 2934 2935 u8 port_xmit_pkts_high[0x20]; 2936 2937 u8 port_xmit_pkts_low[0x20]; 2938 2939 u8 port_rcv_pkts_high[0x20]; 2940 2941 u8 port_rcv_pkts_low[0x20]; 2942 2943 u8 reserved_at_400[0x80]; 2944 2945 u8 port_unicast_xmit_pkts_high[0x20]; 2946 2947 u8 port_unicast_xmit_pkts_low[0x20]; 2948 2949 u8 port_multicast_xmit_pkts_high[0x20]; 2950 2951 u8 port_multicast_xmit_pkts_low[0x20]; 2952 2953 u8 port_unicast_rcv_pkts_high[0x20]; 2954 2955 u8 port_unicast_rcv_pkts_low[0x20]; 2956 2957 u8 port_multicast_rcv_pkts_high[0x20]; 2958 2959 u8 port_multicast_rcv_pkts_low[0x20]; 2960 2961 u8 reserved_at_580[0x240]; 2962 }; 2963 2964 struct mlx5_ifc_eth_per_tc_prio_grp_data_layout_bits { 2965 u8 transmit_queue_high[0x20]; 2966 2967 u8 transmit_queue_low[0x20]; 2968 2969 u8 no_buffer_discard_uc_high[0x20]; 2970 2971 u8 no_buffer_discard_uc_low[0x20]; 2972 2973 u8 reserved_at_80[0x740]; 2974 }; 2975 2976 struct mlx5_ifc_eth_per_tc_congest_prio_grp_data_layout_bits { 2977 u8 wred_discard_high[0x20]; 2978 2979 u8 wred_discard_low[0x20]; 2980 2981 u8 ecn_marked_tc_high[0x20]; 2982 2983 u8 ecn_marked_tc_low[0x20]; 2984 2985 u8 reserved_at_80[0x740]; 2986 }; 2987 2988 struct mlx5_ifc_eth_per_prio_grp_data_layout_bits { 2989 u8 rx_octets_high[0x20]; 2990 2991 u8 rx_octets_low[0x20]; 2992 2993 u8 reserved_at_40[0xc0]; 2994 2995 u8 rx_frames_high[0x20]; 2996 2997 u8 rx_frames_low[0x20]; 2998 2999 u8 tx_octets_high[0x20]; 3000 3001 u8 tx_octets_low[0x20]; 3002 3003 u8 reserved_at_180[0xc0]; 3004 3005 u8 tx_frames_high[0x20]; 3006 3007 u8 tx_frames_low[0x20]; 3008 3009 u8 rx_pause_high[0x20]; 3010 3011 u8 rx_pause_low[0x20]; 3012 3013 u8 rx_pause_duration_high[0x20]; 3014 3015 u8 rx_pause_duration_low[0x20]; 3016 3017 u8 tx_pause_high[0x20]; 3018 3019 u8 tx_pause_low[0x20]; 3020 3021 u8 tx_pause_duration_high[0x20]; 3022 3023 u8 tx_pause_duration_low[0x20]; 3024 3025 u8 rx_pause_transition_high[0x20]; 3026 3027 u8 rx_pause_transition_low[0x20]; 3028 3029 u8 rx_discards_high[0x20]; 3030 3031 u8 rx_discards_low[0x20]; 3032 3033 u8 device_stall_minor_watermark_cnt_high[0x20]; 3034 3035 u8 device_stall_minor_watermark_cnt_low[0x20]; 3036 3037 u8 device_stall_critical_watermark_cnt_high[0x20]; 3038 3039 u8 device_stall_critical_watermark_cnt_low[0x20]; 3040 3041 u8 reserved_at_480[0x340]; 3042 }; 3043 3044 struct mlx5_ifc_eth_extended_cntrs_grp_data_layout_bits { 3045 u8 port_transmit_wait_high[0x20]; 3046 3047 u8 port_transmit_wait_low[0x20]; 3048 3049 u8 reserved_at_40[0x100]; 3050 3051 u8 rx_buffer_almost_full_high[0x20]; 3052 3053 u8 rx_buffer_almost_full_low[0x20]; 3054 3055 u8 rx_buffer_full_high[0x20]; 3056 3057 u8 rx_buffer_full_low[0x20]; 3058 3059 u8 rx_icrc_encapsulated_high[0x20]; 3060 3061 u8 rx_icrc_encapsulated_low[0x20]; 3062 3063 u8 reserved_at_200[0x5c0]; 3064 }; 3065 3066 struct mlx5_ifc_eth_3635_cntrs_grp_data_layout_bits { 3067 u8 dot3stats_alignment_errors_high[0x20]; 3068 3069 u8 dot3stats_alignment_errors_low[0x20]; 3070 3071 u8 dot3stats_fcs_errors_high[0x20]; 3072 3073 u8 dot3stats_fcs_errors_low[0x20]; 3074 3075 u8 dot3stats_single_collision_frames_high[0x20]; 3076 3077 u8 dot3stats_single_collision_frames_low[0x20]; 3078 3079 u8 dot3stats_multiple_collision_frames_high[0x20]; 3080 3081 u8 dot3stats_multiple_collision_frames_low[0x20]; 3082 3083 u8 dot3stats_sqe_test_errors_high[0x20]; 3084 3085 u8 dot3stats_sqe_test_errors_low[0x20]; 3086 3087 u8 dot3stats_deferred_transmissions_high[0x20]; 3088 3089 u8 dot3stats_deferred_transmissions_low[0x20]; 3090 3091 u8 dot3stats_late_collisions_high[0x20]; 3092 3093 u8 dot3stats_late_collisions_low[0x20]; 3094 3095 u8 dot3stats_excessive_collisions_high[0x20]; 3096 3097 u8 dot3stats_excessive_collisions_low[0x20]; 3098 3099 u8 dot3stats_internal_mac_transmit_errors_high[0x20]; 3100 3101 u8 dot3stats_internal_mac_transmit_errors_low[0x20]; 3102 3103 u8 dot3stats_carrier_sense_errors_high[0x20]; 3104 3105 u8 dot3stats_carrier_sense_errors_low[0x20]; 3106 3107 u8 dot3stats_frame_too_longs_high[0x20]; 3108 3109 u8 dot3stats_frame_too_longs_low[0x20]; 3110 3111 u8 dot3stats_internal_mac_receive_errors_high[0x20]; 3112 3113 u8 dot3stats_internal_mac_receive_errors_low[0x20]; 3114 3115 u8 dot3stats_symbol_errors_high[0x20]; 3116 3117 u8 dot3stats_symbol_errors_low[0x20]; 3118 3119 u8 dot3control_in_unknown_opcodes_high[0x20]; 3120 3121 u8 dot3control_in_unknown_opcodes_low[0x20]; 3122 3123 u8 dot3in_pause_frames_high[0x20]; 3124 3125 u8 dot3in_pause_frames_low[0x20]; 3126 3127 u8 dot3out_pause_frames_high[0x20]; 3128 3129 u8 dot3out_pause_frames_low[0x20]; 3130 3131 u8 reserved_at_400[0x3c0]; 3132 }; 3133 3134 struct mlx5_ifc_eth_2819_cntrs_grp_data_layout_bits { 3135 u8 ether_stats_drop_events_high[0x20]; 3136 3137 u8 ether_stats_drop_events_low[0x20]; 3138 3139 u8 ether_stats_octets_high[0x20]; 3140 3141 u8 ether_stats_octets_low[0x20]; 3142 3143 u8 ether_stats_pkts_high[0x20]; 3144 3145 u8 ether_stats_pkts_low[0x20]; 3146 3147 u8 ether_stats_broadcast_pkts_high[0x20]; 3148 3149 u8 ether_stats_broadcast_pkts_low[0x20]; 3150 3151 u8 ether_stats_multicast_pkts_high[0x20]; 3152 3153 u8 ether_stats_multicast_pkts_low[0x20]; 3154 3155 u8 ether_stats_crc_align_errors_high[0x20]; 3156 3157 u8 ether_stats_crc_align_errors_low[0x20]; 3158 3159 u8 ether_stats_undersize_pkts_high[0x20]; 3160 3161 u8 ether_stats_undersize_pkts_low[0x20]; 3162 3163 u8 ether_stats_oversize_pkts_high[0x20]; 3164 3165 u8 ether_stats_oversize_pkts_low[0x20]; 3166 3167 u8 ether_stats_fragments_high[0x20]; 3168 3169 u8 ether_stats_fragments_low[0x20]; 3170 3171 u8 ether_stats_jabbers_high[0x20]; 3172 3173 u8 ether_stats_jabbers_low[0x20]; 3174 3175 u8 ether_stats_collisions_high[0x20]; 3176 3177 u8 ether_stats_collisions_low[0x20]; 3178 3179 u8 ether_stats_pkts64octets_high[0x20]; 3180 3181 u8 ether_stats_pkts64octets_low[0x20]; 3182 3183 u8 ether_stats_pkts65to127octets_high[0x20]; 3184 3185 u8 ether_stats_pkts65to127octets_low[0x20]; 3186 3187 u8 ether_stats_pkts128to255octets_high[0x20]; 3188 3189 u8 ether_stats_pkts128to255octets_low[0x20]; 3190 3191 u8 ether_stats_pkts256to511octets_high[0x20]; 3192 3193 u8 ether_stats_pkts256to511octets_low[0x20]; 3194 3195 u8 ether_stats_pkts512to1023octets_high[0x20]; 3196 3197 u8 ether_stats_pkts512to1023octets_low[0x20]; 3198 3199 u8 ether_stats_pkts1024to1518octets_high[0x20]; 3200 3201 u8 ether_stats_pkts1024to1518octets_low[0x20]; 3202 3203 u8 ether_stats_pkts1519to2047octets_high[0x20]; 3204 3205 u8 ether_stats_pkts1519to2047octets_low[0x20]; 3206 3207 u8 ether_stats_pkts2048to4095octets_high[0x20]; 3208 3209 u8 ether_stats_pkts2048to4095octets_low[0x20]; 3210 3211 u8 ether_stats_pkts4096to8191octets_high[0x20]; 3212 3213 u8 ether_stats_pkts4096to8191octets_low[0x20]; 3214 3215 u8 ether_stats_pkts8192to10239octets_high[0x20]; 3216 3217 u8 ether_stats_pkts8192to10239octets_low[0x20]; 3218 3219 u8 reserved_at_540[0x280]; 3220 }; 3221 3222 struct mlx5_ifc_eth_2863_cntrs_grp_data_layout_bits { 3223 u8 if_in_octets_high[0x20]; 3224 3225 u8 if_in_octets_low[0x20]; 3226 3227 u8 if_in_ucast_pkts_high[0x20]; 3228 3229 u8 if_in_ucast_pkts_low[0x20]; 3230 3231 u8 if_in_discards_high[0x20]; 3232 3233 u8 if_in_discards_low[0x20]; 3234 3235 u8 if_in_errors_high[0x20]; 3236 3237 u8 if_in_errors_low[0x20]; 3238 3239 u8 if_in_unknown_protos_high[0x20]; 3240 3241 u8 if_in_unknown_protos_low[0x20]; 3242 3243 u8 if_out_octets_high[0x20]; 3244 3245 u8 if_out_octets_low[0x20]; 3246 3247 u8 if_out_ucast_pkts_high[0x20]; 3248 3249 u8 if_out_ucast_pkts_low[0x20]; 3250 3251 u8 if_out_discards_high[0x20]; 3252 3253 u8 if_out_discards_low[0x20]; 3254 3255 u8 if_out_errors_high[0x20]; 3256 3257 u8 if_out_errors_low[0x20]; 3258 3259 u8 if_in_multicast_pkts_high[0x20]; 3260 3261 u8 if_in_multicast_pkts_low[0x20]; 3262 3263 u8 if_in_broadcast_pkts_high[0x20]; 3264 3265 u8 if_in_broadcast_pkts_low[0x20]; 3266 3267 u8 if_out_multicast_pkts_high[0x20]; 3268 3269 u8 if_out_multicast_pkts_low[0x20]; 3270 3271 u8 if_out_broadcast_pkts_high[0x20]; 3272 3273 u8 if_out_broadcast_pkts_low[0x20]; 3274 3275 u8 reserved_at_340[0x480]; 3276 }; 3277 3278 struct mlx5_ifc_eth_802_3_cntrs_grp_data_layout_bits { 3279 u8 a_frames_transmitted_ok_high[0x20]; 3280 3281 u8 a_frames_transmitted_ok_low[0x20]; 3282 3283 u8 a_frames_received_ok_high[0x20]; 3284 3285 u8 a_frames_received_ok_low[0x20]; 3286 3287 u8 a_frame_check_sequence_errors_high[0x20]; 3288 3289 u8 a_frame_check_sequence_errors_low[0x20]; 3290 3291 u8 a_alignment_errors_high[0x20]; 3292 3293 u8 a_alignment_errors_low[0x20]; 3294 3295 u8 a_octets_transmitted_ok_high[0x20]; 3296 3297 u8 a_octets_transmitted_ok_low[0x20]; 3298 3299 u8 a_octets_received_ok_high[0x20]; 3300 3301 u8 a_octets_received_ok_low[0x20]; 3302 3303 u8 a_multicast_frames_xmitted_ok_high[0x20]; 3304 3305 u8 a_multicast_frames_xmitted_ok_low[0x20]; 3306 3307 u8 a_broadcast_frames_xmitted_ok_high[0x20]; 3308 3309 u8 a_broadcast_frames_xmitted_ok_low[0x20]; 3310 3311 u8 a_multicast_frames_received_ok_high[0x20]; 3312 3313 u8 a_multicast_frames_received_ok_low[0x20]; 3314 3315 u8 a_broadcast_frames_received_ok_high[0x20]; 3316 3317 u8 a_broadcast_frames_received_ok_low[0x20]; 3318 3319 u8 a_in_range_length_errors_high[0x20]; 3320 3321 u8 a_in_range_length_errors_low[0x20]; 3322 3323 u8 a_out_of_range_length_field_high[0x20]; 3324 3325 u8 a_out_of_range_length_field_low[0x20]; 3326 3327 u8 a_frame_too_long_errors_high[0x20]; 3328 3329 u8 a_frame_too_long_errors_low[0x20]; 3330 3331 u8 a_symbol_error_during_carrier_high[0x20]; 3332 3333 u8 a_symbol_error_during_carrier_low[0x20]; 3334 3335 u8 a_mac_control_frames_transmitted_high[0x20]; 3336 3337 u8 a_mac_control_frames_transmitted_low[0x20]; 3338 3339 u8 a_mac_control_frames_received_high[0x20]; 3340 3341 u8 a_mac_control_frames_received_low[0x20]; 3342 3343 u8 a_unsupported_opcodes_received_high[0x20]; 3344 3345 u8 a_unsupported_opcodes_received_low[0x20]; 3346 3347 u8 a_pause_mac_ctrl_frames_received_high[0x20]; 3348 3349 u8 a_pause_mac_ctrl_frames_received_low[0x20]; 3350 3351 u8 a_pause_mac_ctrl_frames_transmitted_high[0x20]; 3352 3353 u8 a_pause_mac_ctrl_frames_transmitted_low[0x20]; 3354 3355 u8 reserved_at_4c0[0x300]; 3356 }; 3357 3358 struct mlx5_ifc_pcie_perf_cntrs_grp_data_layout_bits { 3359 u8 life_time_counter_high[0x20]; 3360 3361 u8 life_time_counter_low[0x20]; 3362 3363 u8 rx_errors[0x20]; 3364 3365 u8 tx_errors[0x20]; 3366 3367 u8 l0_to_recovery_eieos[0x20]; 3368 3369 u8 l0_to_recovery_ts[0x20]; 3370 3371 u8 l0_to_recovery_framing[0x20]; 3372 3373 u8 l0_to_recovery_retrain[0x20]; 3374 3375 u8 crc_error_dllp[0x20]; 3376 3377 u8 crc_error_tlp[0x20]; 3378 3379 u8 tx_overflow_buffer_pkt_high[0x20]; 3380 3381 u8 tx_overflow_buffer_pkt_low[0x20]; 3382 3383 u8 outbound_stalled_reads[0x20]; 3384 3385 u8 outbound_stalled_writes[0x20]; 3386 3387 u8 outbound_stalled_reads_events[0x20]; 3388 3389 u8 outbound_stalled_writes_events[0x20]; 3390 3391 u8 reserved_at_200[0x5c0]; 3392 }; 3393 3394 struct mlx5_ifc_cmd_inter_comp_event_bits { 3395 u8 command_completion_vector[0x20]; 3396 3397 u8 reserved_at_20[0xc0]; 3398 }; 3399 3400 struct mlx5_ifc_stall_vl_event_bits { 3401 u8 reserved_at_0[0x18]; 3402 u8 port_num[0x1]; 3403 u8 reserved_at_19[0x3]; 3404 u8 vl[0x4]; 3405 3406 u8 reserved_at_20[0xa0]; 3407 }; 3408 3409 struct mlx5_ifc_db_bf_congestion_event_bits { 3410 u8 event_subtype[0x8]; 3411 u8 reserved_at_8[0x8]; 3412 u8 congestion_level[0x8]; 3413 u8 reserved_at_18[0x8]; 3414 3415 u8 reserved_at_20[0xa0]; 3416 }; 3417 3418 struct mlx5_ifc_gpio_event_bits { 3419 u8 reserved_at_0[0x60]; 3420 3421 u8 gpio_event_hi[0x20]; 3422 3423 u8 gpio_event_lo[0x20]; 3424 3425 u8 reserved_at_a0[0x40]; 3426 }; 3427 3428 struct mlx5_ifc_port_state_change_event_bits { 3429 u8 reserved_at_0[0x40]; 3430 3431 u8 port_num[0x4]; 3432 u8 reserved_at_44[0x1c]; 3433 3434 u8 reserved_at_60[0x80]; 3435 }; 3436 3437 struct mlx5_ifc_dropped_packet_logged_bits { 3438 u8 reserved_at_0[0xe0]; 3439 }; 3440 3441 struct mlx5_ifc_nic_cap_reg_bits { 3442 u8 reserved_at_0[0x1a]; 3443 u8 vhca_icm_ctrl[0x1]; 3444 u8 reserved_at_1b[0x5]; 3445 3446 u8 reserved_at_20[0x60]; 3447 }; 3448 3449 struct mlx5_ifc_default_timeout_bits { 3450 u8 to_multiplier[0x3]; 3451 u8 reserved_at_3[0x9]; 3452 u8 to_value[0x14]; 3453 }; 3454 3455 struct mlx5_ifc_dtor_reg_bits { 3456 u8 reserved_at_0[0x20]; 3457 3458 struct mlx5_ifc_default_timeout_bits pcie_toggle_to; 3459 3460 u8 reserved_at_40[0x60]; 3461 3462 struct mlx5_ifc_default_timeout_bits health_poll_to; 3463 3464 struct mlx5_ifc_default_timeout_bits full_crdump_to; 3465 3466 struct mlx5_ifc_default_timeout_bits fw_reset_to; 3467 3468 struct mlx5_ifc_default_timeout_bits flush_on_err_to; 3469 3470 struct mlx5_ifc_default_timeout_bits pci_sync_update_to; 3471 3472 struct mlx5_ifc_default_timeout_bits tear_down_to; 3473 3474 struct mlx5_ifc_default_timeout_bits fsm_reactivate_to; 3475 3476 struct mlx5_ifc_default_timeout_bits reclaim_pages_to; 3477 3478 struct mlx5_ifc_default_timeout_bits reclaim_vfs_pages_to; 3479 3480 struct mlx5_ifc_default_timeout_bits reset_unload_to; 3481 3482 u8 reserved_at_1c0[0x20]; 3483 }; 3484 3485 struct mlx5_ifc_vhca_icm_ctrl_reg_bits { 3486 u8 vhca_id_valid[0x1]; 3487 u8 reserved_at_1[0xf]; 3488 u8 vhca_id[0x10]; 3489 3490 u8 reserved_at_20[0xa0]; 3491 3492 u8 cur_alloc_icm[0x20]; 3493 3494 u8 reserved_at_e0[0x120]; 3495 }; 3496 3497 enum { 3498 MLX5_CQ_ERROR_SYNDROME_CQ_OVERRUN = 0x1, 3499 MLX5_CQ_ERROR_SYNDROME_CQ_ACCESS_VIOLATION_ERROR = 0x2, 3500 }; 3501 3502 struct mlx5_ifc_cq_error_bits { 3503 u8 reserved_at_0[0x8]; 3504 u8 cqn[0x18]; 3505 3506 u8 reserved_at_20[0x20]; 3507 3508 u8 reserved_at_40[0x18]; 3509 u8 syndrome[0x8]; 3510 3511 u8 reserved_at_60[0x80]; 3512 }; 3513 3514 struct mlx5_ifc_rdma_page_fault_event_bits { 3515 u8 bytes_committed[0x20]; 3516 3517 u8 r_key[0x20]; 3518 3519 u8 reserved_at_40[0x10]; 3520 u8 packet_len[0x10]; 3521 3522 u8 rdma_op_len[0x20]; 3523 3524 u8 rdma_va[0x40]; 3525 3526 u8 reserved_at_c0[0x5]; 3527 u8 rdma[0x1]; 3528 u8 write[0x1]; 3529 u8 requestor[0x1]; 3530 u8 qp_number[0x18]; 3531 }; 3532 3533 struct mlx5_ifc_wqe_associated_page_fault_event_bits { 3534 u8 bytes_committed[0x20]; 3535 3536 u8 reserved_at_20[0x10]; 3537 u8 wqe_index[0x10]; 3538 3539 u8 reserved_at_40[0x10]; 3540 u8 len[0x10]; 3541 3542 u8 reserved_at_60[0x60]; 3543 3544 u8 reserved_at_c0[0x5]; 3545 u8 rdma[0x1]; 3546 u8 write_read[0x1]; 3547 u8 requestor[0x1]; 3548 u8 qpn[0x18]; 3549 }; 3550 3551 struct mlx5_ifc_qp_events_bits { 3552 u8 reserved_at_0[0xa0]; 3553 3554 u8 type[0x8]; 3555 u8 reserved_at_a8[0x18]; 3556 3557 u8 reserved_at_c0[0x8]; 3558 u8 qpn_rqn_sqn[0x18]; 3559 }; 3560 3561 struct mlx5_ifc_dct_events_bits { 3562 u8 reserved_at_0[0xc0]; 3563 3564 u8 reserved_at_c0[0x8]; 3565 u8 dct_number[0x18]; 3566 }; 3567 3568 struct mlx5_ifc_comp_event_bits { 3569 u8 reserved_at_0[0xc0]; 3570 3571 u8 reserved_at_c0[0x8]; 3572 u8 cq_number[0x18]; 3573 }; 3574 3575 enum { 3576 MLX5_QPC_STATE_RST = 0x0, 3577 MLX5_QPC_STATE_INIT = 0x1, 3578 MLX5_QPC_STATE_RTR = 0x2, 3579 MLX5_QPC_STATE_RTS = 0x3, 3580 MLX5_QPC_STATE_SQER = 0x4, 3581 MLX5_QPC_STATE_ERR = 0x6, 3582 MLX5_QPC_STATE_SQD = 0x7, 3583 MLX5_QPC_STATE_SUSPENDED = 0x9, 3584 }; 3585 3586 enum { 3587 MLX5_QPC_ST_RC = 0x0, 3588 MLX5_QPC_ST_UC = 0x1, 3589 MLX5_QPC_ST_UD = 0x2, 3590 MLX5_QPC_ST_XRC = 0x3, 3591 MLX5_QPC_ST_DCI = 0x5, 3592 MLX5_QPC_ST_QP0 = 0x7, 3593 MLX5_QPC_ST_QP1 = 0x8, 3594 MLX5_QPC_ST_RAW_DATAGRAM = 0x9, 3595 MLX5_QPC_ST_REG_UMR = 0xc, 3596 }; 3597 3598 enum { 3599 MLX5_QPC_PM_STATE_ARMED = 0x0, 3600 MLX5_QPC_PM_STATE_REARM = 0x1, 3601 MLX5_QPC_PM_STATE_RESERVED = 0x2, 3602 MLX5_QPC_PM_STATE_MIGRATED = 0x3, 3603 }; 3604 3605 enum { 3606 MLX5_QPC_OFFLOAD_TYPE_RNDV = 0x1, 3607 }; 3608 3609 enum { 3610 MLX5_QPC_END_PADDING_MODE_SCATTER_AS_IS = 0x0, 3611 MLX5_QPC_END_PADDING_MODE_PAD_TO_CACHE_LINE_ALIGNMENT = 0x1, 3612 }; 3613 3614 enum { 3615 MLX5_QPC_MTU_256_BYTES = 0x1, 3616 MLX5_QPC_MTU_512_BYTES = 0x2, 3617 MLX5_QPC_MTU_1K_BYTES = 0x3, 3618 MLX5_QPC_MTU_2K_BYTES = 0x4, 3619 MLX5_QPC_MTU_4K_BYTES = 0x5, 3620 MLX5_QPC_MTU_RAW_ETHERNET_QP = 0x7, 3621 }; 3622 3623 enum { 3624 MLX5_QPC_ATOMIC_MODE_IB_SPEC = 0x1, 3625 MLX5_QPC_ATOMIC_MODE_ONLY_8B = 0x2, 3626 MLX5_QPC_ATOMIC_MODE_UP_TO_8B = 0x3, 3627 MLX5_QPC_ATOMIC_MODE_UP_TO_16B = 0x4, 3628 MLX5_QPC_ATOMIC_MODE_UP_TO_32B = 0x5, 3629 MLX5_QPC_ATOMIC_MODE_UP_TO_64B = 0x6, 3630 MLX5_QPC_ATOMIC_MODE_UP_TO_128B = 0x7, 3631 MLX5_QPC_ATOMIC_MODE_UP_TO_256B = 0x8, 3632 }; 3633 3634 enum { 3635 MLX5_QPC_CS_REQ_DISABLE = 0x0, 3636 MLX5_QPC_CS_REQ_UP_TO_32B = 0x11, 3637 MLX5_QPC_CS_REQ_UP_TO_64B = 0x22, 3638 }; 3639 3640 enum { 3641 MLX5_QPC_CS_RES_DISABLE = 0x0, 3642 MLX5_QPC_CS_RES_UP_TO_32B = 0x1, 3643 MLX5_QPC_CS_RES_UP_TO_64B = 0x2, 3644 }; 3645 3646 enum { 3647 MLX5_TIMESTAMP_FORMAT_FREE_RUNNING = 0x0, 3648 MLX5_TIMESTAMP_FORMAT_DEFAULT = 0x1, 3649 MLX5_TIMESTAMP_FORMAT_REAL_TIME = 0x2, 3650 }; 3651 3652 struct mlx5_ifc_qpc_bits { 3653 u8 state[0x4]; 3654 u8 lag_tx_port_affinity[0x4]; 3655 u8 st[0x8]; 3656 u8 reserved_at_10[0x2]; 3657 u8 isolate_vl_tc[0x1]; 3658 u8 pm_state[0x2]; 3659 u8 reserved_at_15[0x1]; 3660 u8 req_e2e_credit_mode[0x2]; 3661 u8 offload_type[0x4]; 3662 u8 end_padding_mode[0x2]; 3663 u8 reserved_at_1e[0x2]; 3664 3665 u8 wq_signature[0x1]; 3666 u8 block_lb_mc[0x1]; 3667 u8 atomic_like_write_en[0x1]; 3668 u8 latency_sensitive[0x1]; 3669 u8 reserved_at_24[0x1]; 3670 u8 drain_sigerr[0x1]; 3671 u8 reserved_at_26[0x1]; 3672 u8 dp_ordering_force[0x1]; 3673 u8 pd[0x18]; 3674 3675 u8 mtu[0x3]; 3676 u8 log_msg_max[0x5]; 3677 u8 reserved_at_48[0x1]; 3678 u8 log_rq_size[0x4]; 3679 u8 log_rq_stride[0x3]; 3680 u8 no_sq[0x1]; 3681 u8 log_sq_size[0x4]; 3682 u8 reserved_at_55[0x1]; 3683 u8 retry_mode[0x2]; 3684 u8 ts_format[0x2]; 3685 u8 reserved_at_5a[0x1]; 3686 u8 rlky[0x1]; 3687 u8 ulp_stateless_offload_mode[0x4]; 3688 3689 u8 counter_set_id[0x8]; 3690 u8 uar_page[0x18]; 3691 3692 u8 reserved_at_80[0x8]; 3693 u8 user_index[0x18]; 3694 3695 u8 reserved_at_a0[0x3]; 3696 u8 log_page_size[0x5]; 3697 u8 remote_qpn[0x18]; 3698 3699 struct mlx5_ifc_ads_bits primary_address_path; 3700 3701 struct mlx5_ifc_ads_bits secondary_address_path; 3702 3703 u8 log_ack_req_freq[0x4]; 3704 u8 reserved_at_384[0x4]; 3705 u8 log_sra_max[0x3]; 3706 u8 reserved_at_38b[0x2]; 3707 u8 retry_count[0x3]; 3708 u8 rnr_retry[0x3]; 3709 u8 reserved_at_393[0x1]; 3710 u8 fre[0x1]; 3711 u8 cur_rnr_retry[0x3]; 3712 u8 cur_retry_count[0x3]; 3713 u8 reserved_at_39b[0x5]; 3714 3715 u8 reserved_at_3a0[0x10]; 3716 u8 packet_pacing_rate_limit_index[0x10]; 3717 3718 u8 reserved_at_3c0[0x8]; 3719 u8 next_send_psn[0x18]; 3720 3721 u8 reserved_at_3e0[0x3]; 3722 u8 log_num_dci_stream_channels[0x5]; 3723 u8 cqn_snd[0x18]; 3724 3725 u8 reserved_at_400[0x3]; 3726 u8 log_num_dci_errored_streams[0x5]; 3727 u8 deth_sqpn[0x18]; 3728 3729 u8 reserved_at_420[0x20]; 3730 3731 u8 reserved_at_440[0x8]; 3732 u8 last_acked_psn[0x18]; 3733 3734 u8 reserved_at_460[0x8]; 3735 u8 ssn[0x18]; 3736 3737 u8 reserved_at_480[0x8]; 3738 u8 log_rra_max[0x3]; 3739 u8 reserved_at_48b[0x1]; 3740 u8 atomic_mode[0x4]; 3741 u8 rre[0x1]; 3742 u8 rwe[0x1]; 3743 u8 rae[0x1]; 3744 u8 reserved_at_493[0x1]; 3745 u8 page_offset[0x6]; 3746 u8 reserved_at_49a[0x2]; 3747 u8 dp_ordering_1[0x1]; 3748 u8 cd_slave_receive[0x1]; 3749 u8 cd_slave_send[0x1]; 3750 u8 cd_master[0x1]; 3751 3752 u8 reserved_at_4a0[0x3]; 3753 u8 min_rnr_nak[0x5]; 3754 u8 next_rcv_psn[0x18]; 3755 3756 u8 reserved_at_4c0[0x8]; 3757 u8 xrcd[0x18]; 3758 3759 u8 reserved_at_4e0[0x8]; 3760 u8 cqn_rcv[0x18]; 3761 3762 u8 dbr_addr[0x40]; 3763 3764 u8 q_key[0x20]; 3765 3766 u8 reserved_at_560[0x5]; 3767 u8 rq_type[0x3]; 3768 u8 srqn_rmpn_xrqn[0x18]; 3769 3770 u8 reserved_at_580[0x8]; 3771 u8 rmsn[0x18]; 3772 3773 u8 hw_sq_wqebb_counter[0x10]; 3774 u8 sw_sq_wqebb_counter[0x10]; 3775 3776 u8 hw_rq_counter[0x20]; 3777 3778 u8 sw_rq_counter[0x20]; 3779 3780 u8 reserved_at_600[0x20]; 3781 3782 u8 reserved_at_620[0xf]; 3783 u8 cgs[0x1]; 3784 u8 cs_req[0x8]; 3785 u8 cs_res[0x8]; 3786 3787 u8 dc_access_key[0x40]; 3788 3789 u8 reserved_at_680[0x3]; 3790 u8 dbr_umem_valid[0x1]; 3791 3792 u8 reserved_at_684[0xbc]; 3793 }; 3794 3795 struct mlx5_ifc_roce_addr_layout_bits { 3796 u8 source_l3_address[16][0x8]; 3797 3798 u8 reserved_at_80[0x3]; 3799 u8 vlan_valid[0x1]; 3800 u8 vlan_id[0xc]; 3801 u8 source_mac_47_32[0x10]; 3802 3803 u8 source_mac_31_0[0x20]; 3804 3805 u8 reserved_at_c0[0x14]; 3806 u8 roce_l3_type[0x4]; 3807 u8 roce_version[0x8]; 3808 3809 u8 reserved_at_e0[0x20]; 3810 }; 3811 3812 struct mlx5_ifc_crypto_cap_bits { 3813 u8 reserved_at_0[0x3]; 3814 u8 synchronize_dek[0x1]; 3815 u8 int_kek_manual[0x1]; 3816 u8 int_kek_auto[0x1]; 3817 u8 reserved_at_6[0x1a]; 3818 3819 u8 reserved_at_20[0x3]; 3820 u8 log_dek_max_alloc[0x5]; 3821 u8 reserved_at_28[0x3]; 3822 u8 log_max_num_deks[0x5]; 3823 u8 reserved_at_30[0x10]; 3824 3825 u8 reserved_at_40[0x20]; 3826 3827 u8 reserved_at_60[0x3]; 3828 u8 log_dek_granularity[0x5]; 3829 u8 reserved_at_68[0x3]; 3830 u8 log_max_num_int_kek[0x5]; 3831 u8 sw_wrapped_dek[0x10]; 3832 3833 u8 reserved_at_80[0x780]; 3834 }; 3835 3836 struct mlx5_ifc_shampo_cap_bits { 3837 u8 reserved_at_0[0x3]; 3838 u8 shampo_log_max_reservation_size[0x5]; 3839 u8 reserved_at_8[0x3]; 3840 u8 shampo_log_min_reservation_size[0x5]; 3841 u8 shampo_min_mss_size[0x10]; 3842 3843 u8 shampo_header_split[0x1]; 3844 u8 shampo_header_split_data_merge[0x1]; 3845 u8 reserved_at_22[0x1]; 3846 u8 shampo_log_max_headers_entry_size[0x5]; 3847 u8 reserved_at_28[0x18]; 3848 3849 u8 reserved_at_40[0x7c0]; 3850 }; 3851 3852 union mlx5_ifc_hca_cap_union_bits { 3853 struct mlx5_ifc_cmd_hca_cap_bits cmd_hca_cap; 3854 struct mlx5_ifc_cmd_hca_cap_2_bits cmd_hca_cap_2; 3855 struct mlx5_ifc_odp_cap_bits odp_cap; 3856 struct mlx5_ifc_atomic_caps_bits atomic_caps; 3857 struct mlx5_ifc_roce_cap_bits roce_cap; 3858 struct mlx5_ifc_per_protocol_networking_offload_caps_bits per_protocol_networking_offload_caps; 3859 struct mlx5_ifc_flow_table_nic_cap_bits flow_table_nic_cap; 3860 struct mlx5_ifc_flow_table_eswitch_cap_bits flow_table_eswitch_cap; 3861 struct mlx5_ifc_wqe_based_flow_table_cap_bits wqe_based_flow_table_cap; 3862 struct mlx5_ifc_e_switch_cap_bits e_switch_cap; 3863 struct mlx5_ifc_port_selection_cap_bits port_selection_cap; 3864 struct mlx5_ifc_qos_cap_bits qos_cap; 3865 struct mlx5_ifc_debug_cap_bits debug_cap; 3866 struct mlx5_ifc_fpga_cap_bits fpga_cap; 3867 struct mlx5_ifc_tls_cap_bits tls_cap; 3868 struct mlx5_ifc_device_mem_cap_bits device_mem_cap; 3869 struct mlx5_ifc_virtio_emulation_cap_bits virtio_emulation_cap; 3870 struct mlx5_ifc_tlp_dev_emu_capabilities_bits tlp_dev_emu_capabilities; 3871 struct mlx5_ifc_macsec_cap_bits macsec_cap; 3872 struct mlx5_ifc_crypto_cap_bits crypto_cap; 3873 struct mlx5_ifc_ipsec_cap_bits ipsec_cap; 3874 struct mlx5_ifc_psp_cap_bits psp_cap; 3875 u8 reserved_at_0[0x8000]; 3876 }; 3877 3878 enum { 3879 MLX5_FLOW_CONTEXT_ACTION_ALLOW = 0x1, 3880 MLX5_FLOW_CONTEXT_ACTION_DROP = 0x2, 3881 MLX5_FLOW_CONTEXT_ACTION_FWD_DEST = 0x4, 3882 MLX5_FLOW_CONTEXT_ACTION_COUNT = 0x8, 3883 MLX5_FLOW_CONTEXT_ACTION_PACKET_REFORMAT = 0x10, 3884 MLX5_FLOW_CONTEXT_ACTION_DECAP = 0x20, 3885 MLX5_FLOW_CONTEXT_ACTION_MOD_HDR = 0x40, 3886 MLX5_FLOW_CONTEXT_ACTION_VLAN_POP = 0x80, 3887 MLX5_FLOW_CONTEXT_ACTION_VLAN_PUSH = 0x100, 3888 MLX5_FLOW_CONTEXT_ACTION_VLAN_POP_2 = 0x400, 3889 MLX5_FLOW_CONTEXT_ACTION_VLAN_PUSH_2 = 0x800, 3890 MLX5_FLOW_CONTEXT_ACTION_CRYPTO_DECRYPT = 0x1000, 3891 MLX5_FLOW_CONTEXT_ACTION_CRYPTO_ENCRYPT = 0x2000, 3892 MLX5_FLOW_CONTEXT_ACTION_EXECUTE_ASO = 0x4000, 3893 }; 3894 3895 enum { 3896 MLX5_FLOW_CONTEXT_FLOW_SOURCE_ANY_VPORT = 0x0, 3897 MLX5_FLOW_CONTEXT_FLOW_SOURCE_UPLINK = 0x1, 3898 MLX5_FLOW_CONTEXT_FLOW_SOURCE_LOCAL_VPORT = 0x2, 3899 }; 3900 3901 enum { 3902 MLX5_FLOW_CONTEXT_ENCRYPT_DECRYPT_TYPE_IPSEC = 0x0, 3903 MLX5_FLOW_CONTEXT_ENCRYPT_DECRYPT_TYPE_MACSEC = 0x1, 3904 MLX5_FLOW_CONTEXT_ENCRYPT_DECRYPT_TYPE_PSP = 0x2, 3905 }; 3906 3907 struct mlx5_ifc_vlan_bits { 3908 u8 ethtype[0x10]; 3909 u8 prio[0x3]; 3910 u8 cfi[0x1]; 3911 u8 vid[0xc]; 3912 }; 3913 3914 enum { 3915 MLX5_FLOW_METER_COLOR_RED = 0x0, 3916 MLX5_FLOW_METER_COLOR_YELLOW = 0x1, 3917 MLX5_FLOW_METER_COLOR_GREEN = 0x2, 3918 MLX5_FLOW_METER_COLOR_UNDEFINED = 0x3, 3919 }; 3920 3921 enum { 3922 MLX5_EXE_ASO_FLOW_METER = 0x2, 3923 }; 3924 3925 struct mlx5_ifc_exe_aso_ctrl_flow_meter_bits { 3926 u8 return_reg_id[0x4]; 3927 u8 aso_type[0x4]; 3928 u8 reserved_at_8[0x14]; 3929 u8 action[0x1]; 3930 u8 init_color[0x2]; 3931 u8 meter_id[0x1]; 3932 }; 3933 3934 union mlx5_ifc_exe_aso_ctrl { 3935 struct mlx5_ifc_exe_aso_ctrl_flow_meter_bits exe_aso_ctrl_flow_meter; 3936 }; 3937 3938 struct mlx5_ifc_execute_aso_bits { 3939 u8 valid[0x1]; 3940 u8 reserved_at_1[0x7]; 3941 u8 aso_object_id[0x18]; 3942 3943 union mlx5_ifc_exe_aso_ctrl exe_aso_ctrl; 3944 }; 3945 3946 struct mlx5_ifc_flow_context_bits { 3947 struct mlx5_ifc_vlan_bits push_vlan; 3948 3949 u8 group_id[0x20]; 3950 3951 u8 reserved_at_40[0x8]; 3952 u8 flow_tag[0x18]; 3953 3954 u8 reserved_at_60[0x10]; 3955 u8 action[0x10]; 3956 3957 u8 extended_destination[0x1]; 3958 u8 uplink_hairpin_en[0x1]; 3959 u8 flow_source[0x2]; 3960 u8 encrypt_decrypt_type[0x4]; 3961 u8 destination_list_size[0x18]; 3962 3963 u8 reserved_at_a0[0x8]; 3964 u8 flow_counter_list_size[0x18]; 3965 3966 u8 packet_reformat_id[0x20]; 3967 3968 u8 modify_header_id[0x20]; 3969 3970 struct mlx5_ifc_vlan_bits push_vlan_2; 3971 3972 u8 encrypt_decrypt_obj_id[0x20]; 3973 u8 reserved_at_140[0xc0]; 3974 3975 struct mlx5_ifc_fte_match_param_bits match_value; 3976 3977 struct mlx5_ifc_execute_aso_bits execute_aso[4]; 3978 3979 u8 reserved_at_1300[0x500]; 3980 3981 union mlx5_ifc_dest_format_flow_counter_list_auto_bits destination[]; 3982 }; 3983 3984 enum { 3985 MLX5_XRC_SRQC_STATE_GOOD = 0x0, 3986 MLX5_XRC_SRQC_STATE_ERROR = 0x1, 3987 }; 3988 3989 struct mlx5_ifc_xrc_srqc_bits { 3990 u8 state[0x4]; 3991 u8 log_xrc_srq_size[0x4]; 3992 u8 reserved_at_8[0x18]; 3993 3994 u8 wq_signature[0x1]; 3995 u8 cont_srq[0x1]; 3996 u8 reserved_at_22[0x1]; 3997 u8 rlky[0x1]; 3998 u8 basic_cyclic_rcv_wqe[0x1]; 3999 u8 log_rq_stride[0x3]; 4000 u8 xrcd[0x18]; 4001 4002 u8 page_offset[0x6]; 4003 u8 reserved_at_46[0x1]; 4004 u8 dbr_umem_valid[0x1]; 4005 u8 cqn[0x18]; 4006 4007 u8 reserved_at_60[0x20]; 4008 4009 u8 user_index_equal_xrc_srqn[0x1]; 4010 u8 reserved_at_81[0x1]; 4011 u8 log_page_size[0x6]; 4012 u8 user_index[0x18]; 4013 4014 u8 reserved_at_a0[0x20]; 4015 4016 u8 reserved_at_c0[0x8]; 4017 u8 pd[0x18]; 4018 4019 u8 lwm[0x10]; 4020 u8 wqe_cnt[0x10]; 4021 4022 u8 reserved_at_100[0x40]; 4023 4024 u8 db_record_addr_h[0x20]; 4025 4026 u8 db_record_addr_l[0x1e]; 4027 u8 reserved_at_17e[0x2]; 4028 4029 u8 reserved_at_180[0x80]; 4030 }; 4031 4032 struct mlx5_ifc_vnic_diagnostic_statistics_bits { 4033 u8 counter_error_queues[0x20]; 4034 4035 u8 total_error_queues[0x20]; 4036 4037 u8 send_queue_priority_update_flow[0x20]; 4038 4039 u8 reserved_at_60[0x20]; 4040 4041 u8 nic_receive_steering_discard[0x40]; 4042 4043 u8 receive_discard_vport_down[0x40]; 4044 4045 u8 transmit_discard_vport_down[0x40]; 4046 4047 u8 async_eq_overrun[0x20]; 4048 4049 u8 comp_eq_overrun[0x20]; 4050 4051 u8 reserved_at_180[0x20]; 4052 4053 u8 invalid_command[0x20]; 4054 4055 u8 quota_exceeded_command[0x20]; 4056 4057 u8 internal_rq_out_of_buffer[0x20]; 4058 4059 u8 cq_overrun[0x20]; 4060 4061 u8 eth_wqe_too_small[0x20]; 4062 4063 u8 reserved_at_220[0xc0]; 4064 4065 u8 generated_pkt_steering_fail[0x40]; 4066 4067 u8 handled_pkt_steering_fail[0x40]; 4068 4069 u8 bar_uar_access[0x20]; 4070 4071 u8 odp_local_triggered_page_fault[0x20]; 4072 4073 u8 odp_remote_triggered_page_fault[0x20]; 4074 4075 u8 reserved_at_3c0[0xc20]; 4076 }; 4077 4078 struct mlx5_ifc_traffic_counter_bits { 4079 u8 packets[0x40]; 4080 4081 u8 octets[0x40]; 4082 }; 4083 4084 struct mlx5_ifc_tisc_bits { 4085 u8 strict_lag_tx_port_affinity[0x1]; 4086 u8 tls_en[0x1]; 4087 u8 reserved_at_2[0x2]; 4088 u8 lag_tx_port_affinity[0x04]; 4089 4090 u8 reserved_at_8[0x4]; 4091 u8 prio[0x4]; 4092 u8 reserved_at_10[0x10]; 4093 4094 u8 reserved_at_20[0x100]; 4095 4096 u8 reserved_at_120[0x8]; 4097 u8 transport_domain[0x18]; 4098 4099 u8 reserved_at_140[0x8]; 4100 u8 underlay_qpn[0x18]; 4101 4102 u8 reserved_at_160[0x8]; 4103 u8 pd[0x18]; 4104 4105 u8 reserved_at_180[0x380]; 4106 }; 4107 4108 enum { 4109 MLX5_TIRC_DISP_TYPE_DIRECT = 0x0, 4110 MLX5_TIRC_DISP_TYPE_INDIRECT = 0x1, 4111 }; 4112 4113 enum { 4114 MLX5_TIRC_PACKET_MERGE_MASK_IPV4_LRO = BIT(0), 4115 MLX5_TIRC_PACKET_MERGE_MASK_IPV6_LRO = BIT(1), 4116 }; 4117 4118 enum { 4119 MLX5_RX_HASH_FN_NONE = 0x0, 4120 MLX5_RX_HASH_FN_INVERTED_XOR8 = 0x1, 4121 MLX5_RX_HASH_FN_TOEPLITZ = 0x2, 4122 }; 4123 4124 enum { 4125 MLX5_TIRC_SELF_LB_BLOCK_BLOCK_UNICAST = 0x1, 4126 MLX5_TIRC_SELF_LB_BLOCK_BLOCK_MULTICAST = 0x2, 4127 }; 4128 4129 struct mlx5_ifc_tirc_bits { 4130 u8 reserved_at_0[0x20]; 4131 4132 u8 disp_type[0x4]; 4133 u8 tls_en[0x1]; 4134 u8 reserved_at_25[0x1b]; 4135 4136 u8 reserved_at_40[0x40]; 4137 4138 u8 reserved_at_80[0x4]; 4139 u8 lro_timeout_period_usecs[0x10]; 4140 u8 packet_merge_mask[0x4]; 4141 u8 lro_max_ip_payload_size[0x8]; 4142 4143 u8 reserved_at_a0[0x40]; 4144 4145 u8 reserved_at_e0[0x8]; 4146 u8 inline_rqn[0x18]; 4147 4148 u8 rx_hash_symmetric[0x1]; 4149 u8 reserved_at_101[0x1]; 4150 u8 tunneled_offload_en[0x1]; 4151 u8 reserved_at_103[0x5]; 4152 u8 indirect_table[0x18]; 4153 4154 u8 rx_hash_fn[0x4]; 4155 u8 reserved_at_124[0x2]; 4156 u8 self_lb_block[0x2]; 4157 u8 transport_domain[0x18]; 4158 4159 u8 rx_hash_toeplitz_key[10][0x20]; 4160 4161 struct mlx5_ifc_rx_hash_field_select_bits rx_hash_field_selector_outer; 4162 4163 struct mlx5_ifc_rx_hash_field_select_bits rx_hash_field_selector_inner; 4164 4165 u8 reserved_at_2c0[0x4c0]; 4166 }; 4167 4168 enum { 4169 MLX5_SRQC_STATE_GOOD = 0x0, 4170 MLX5_SRQC_STATE_ERROR = 0x1, 4171 }; 4172 4173 struct mlx5_ifc_srqc_bits { 4174 u8 state[0x4]; 4175 u8 log_srq_size[0x4]; 4176 u8 reserved_at_8[0x18]; 4177 4178 u8 wq_signature[0x1]; 4179 u8 cont_srq[0x1]; 4180 u8 reserved_at_22[0x1]; 4181 u8 rlky[0x1]; 4182 u8 reserved_at_24[0x1]; 4183 u8 log_rq_stride[0x3]; 4184 u8 xrcd[0x18]; 4185 4186 u8 page_offset[0x6]; 4187 u8 reserved_at_46[0x2]; 4188 u8 cqn[0x18]; 4189 4190 u8 reserved_at_60[0x20]; 4191 4192 u8 reserved_at_80[0x2]; 4193 u8 log_page_size[0x6]; 4194 u8 reserved_at_88[0x18]; 4195 4196 u8 reserved_at_a0[0x20]; 4197 4198 u8 reserved_at_c0[0x8]; 4199 u8 pd[0x18]; 4200 4201 u8 lwm[0x10]; 4202 u8 wqe_cnt[0x10]; 4203 4204 u8 reserved_at_100[0x40]; 4205 4206 u8 dbr_addr[0x40]; 4207 4208 u8 reserved_at_180[0x80]; 4209 }; 4210 4211 enum { 4212 MLX5_SQC_STATE_RST = 0x0, 4213 MLX5_SQC_STATE_RDY = 0x1, 4214 MLX5_SQC_STATE_ERR = 0x3, 4215 }; 4216 4217 struct mlx5_ifc_sqc_bits { 4218 u8 rlky[0x1]; 4219 u8 cd_master[0x1]; 4220 u8 fre[0x1]; 4221 u8 flush_in_error_en[0x1]; 4222 u8 allow_multi_pkt_send_wqe[0x1]; 4223 u8 min_wqe_inline_mode[0x3]; 4224 u8 state[0x4]; 4225 u8 reg_umr[0x1]; 4226 u8 allow_swp[0x1]; 4227 u8 hairpin[0x1]; 4228 u8 non_wire[0x1]; 4229 u8 reserved_at_10[0xa]; 4230 u8 ts_format[0x2]; 4231 u8 reserved_at_1c[0x4]; 4232 4233 u8 reserved_at_20[0x8]; 4234 u8 user_index[0x18]; 4235 4236 u8 reserved_at_40[0x8]; 4237 u8 cqn[0x18]; 4238 4239 u8 reserved_at_60[0x8]; 4240 u8 hairpin_peer_rq[0x18]; 4241 4242 u8 reserved_at_80[0x10]; 4243 u8 hairpin_peer_vhca[0x10]; 4244 4245 u8 reserved_at_a0[0x20]; 4246 4247 u8 reserved_at_c0[0x8]; 4248 u8 ts_cqe_to_dest_cqn[0x18]; 4249 4250 u8 reserved_at_e0[0x10]; 4251 u8 packet_pacing_rate_limit_index[0x10]; 4252 u8 tis_lst_sz[0x10]; 4253 u8 qos_queue_group_id[0x10]; 4254 4255 u8 reserved_at_120[0x40]; 4256 4257 u8 reserved_at_160[0x8]; 4258 u8 tis_num_0[0x18]; 4259 4260 struct mlx5_ifc_wq_bits wq; 4261 }; 4262 4263 enum { 4264 SCHEDULING_CONTEXT_ELEMENT_TYPE_TSAR = 0x0, 4265 SCHEDULING_CONTEXT_ELEMENT_TYPE_VPORT = 0x1, 4266 SCHEDULING_CONTEXT_ELEMENT_TYPE_VPORT_TC = 0x2, 4267 SCHEDULING_CONTEXT_ELEMENT_TYPE_PARA_VPORT_TC = 0x3, 4268 SCHEDULING_CONTEXT_ELEMENT_TYPE_QUEUE_GROUP = 0x4, 4269 SCHEDULING_CONTEXT_ELEMENT_TYPE_RATE_LIMIT = 0x5, 4270 }; 4271 4272 enum { 4273 ELEMENT_TYPE_CAP_MASK_TSAR = 1 << 0, 4274 ELEMENT_TYPE_CAP_MASK_VPORT = 1 << 1, 4275 ELEMENT_TYPE_CAP_MASK_VPORT_TC = 1 << 2, 4276 ELEMENT_TYPE_CAP_MASK_PARA_VPORT_TC = 1 << 3, 4277 ELEMENT_TYPE_CAP_MASK_QUEUE_GROUP = 1 << 4, 4278 ELEMENT_TYPE_CAP_MASK_RATE_LIMIT = 1 << 5, 4279 }; 4280 4281 enum { 4282 TSAR_ELEMENT_TSAR_TYPE_DWRR = 0x0, 4283 TSAR_ELEMENT_TSAR_TYPE_ROUND_ROBIN = 0x1, 4284 TSAR_ELEMENT_TSAR_TYPE_ETS = 0x2, 4285 TSAR_ELEMENT_TSAR_TYPE_TC_ARB = 0x3, 4286 }; 4287 4288 enum { 4289 TSAR_TYPE_CAP_MASK_DWRR = 1 << 0, 4290 TSAR_TYPE_CAP_MASK_ROUND_ROBIN = 1 << 1, 4291 TSAR_TYPE_CAP_MASK_ETS = 1 << 2, 4292 TSAR_TYPE_CAP_MASK_TC_ARB = 1 << 3, 4293 }; 4294 4295 struct mlx5_ifc_tsar_element_bits { 4296 u8 traffic_class[0x4]; 4297 u8 reserved_at_4[0x4]; 4298 u8 tsar_type[0x8]; 4299 u8 reserved_at_10[0x10]; 4300 }; 4301 4302 struct mlx5_ifc_vport_element_bits { 4303 u8 reserved_at_0[0x4]; 4304 u8 eswitch_owner_vhca_id_valid[0x1]; 4305 u8 eswitch_owner_vhca_id[0xb]; 4306 u8 vport_number[0x10]; 4307 }; 4308 4309 struct mlx5_ifc_vport_tc_element_bits { 4310 u8 traffic_class[0x4]; 4311 u8 eswitch_owner_vhca_id_valid[0x1]; 4312 u8 eswitch_owner_vhca_id[0xb]; 4313 u8 vport_number[0x10]; 4314 }; 4315 4316 union mlx5_ifc_element_attributes_bits { 4317 struct mlx5_ifc_tsar_element_bits tsar; 4318 struct mlx5_ifc_vport_element_bits vport; 4319 struct mlx5_ifc_vport_tc_element_bits vport_tc; 4320 u8 reserved_at_0[0x20]; 4321 }; 4322 4323 struct mlx5_ifc_scheduling_context_bits { 4324 u8 element_type[0x8]; 4325 u8 reserved_at_8[0x18]; 4326 4327 union mlx5_ifc_element_attributes_bits element_attributes; 4328 4329 u8 parent_element_id[0x20]; 4330 4331 u8 reserved_at_60[0x40]; 4332 4333 u8 bw_share[0x20]; 4334 4335 u8 max_average_bw[0x20]; 4336 4337 u8 max_bw_obj_id[0x20]; 4338 4339 u8 reserved_at_100[0x100]; 4340 }; 4341 4342 struct mlx5_ifc_rqtc_bits { 4343 u8 reserved_at_0[0xa0]; 4344 4345 u8 reserved_at_a0[0x5]; 4346 u8 list_q_type[0x3]; 4347 u8 reserved_at_a8[0x8]; 4348 u8 rqt_max_size[0x10]; 4349 4350 u8 rq_vhca_id_format[0x1]; 4351 u8 reserved_at_c1[0xf]; 4352 u8 rqt_actual_size[0x10]; 4353 4354 u8 reserved_at_e0[0x6a0]; 4355 4356 union { 4357 DECLARE_FLEX_ARRAY(struct mlx5_ifc_rq_num_bits, rq_num); 4358 DECLARE_FLEX_ARRAY(struct mlx5_ifc_rq_vhca_bits, rq_vhca); 4359 }; 4360 }; 4361 4362 enum { 4363 MLX5_RQC_MEM_RQ_TYPE_MEMORY_RQ_INLINE = 0x0, 4364 MLX5_RQC_MEM_RQ_TYPE_MEMORY_RQ_RMP = 0x1, 4365 }; 4366 4367 enum { 4368 MLX5_RQC_STATE_RST = 0x0, 4369 MLX5_RQC_STATE_RDY = 0x1, 4370 MLX5_RQC_STATE_ERR = 0x3, 4371 }; 4372 4373 enum { 4374 MLX5_RQC_SHAMPO_NO_MATCH_ALIGNMENT_GRANULARITY_BYTE = 0x0, 4375 MLX5_RQC_SHAMPO_NO_MATCH_ALIGNMENT_GRANULARITY_STRIDE = 0x1, 4376 MLX5_RQC_SHAMPO_NO_MATCH_ALIGNMENT_GRANULARITY_PAGE = 0x2, 4377 }; 4378 4379 enum { 4380 MLX5_RQC_SHAMPO_MATCH_CRITERIA_TYPE_NO_MATCH = 0x0, 4381 MLX5_RQC_SHAMPO_MATCH_CRITERIA_TYPE_EXTENDED = 0x1, 4382 MLX5_RQC_SHAMPO_MATCH_CRITERIA_TYPE_FIVE_TUPLE = 0x2, 4383 }; 4384 4385 struct mlx5_ifc_rqc_bits { 4386 u8 rlky[0x1]; 4387 u8 delay_drop_en[0x1]; 4388 u8 scatter_fcs[0x1]; 4389 u8 vsd[0x1]; 4390 u8 mem_rq_type[0x4]; 4391 u8 state[0x4]; 4392 u8 reserved_at_c[0x1]; 4393 u8 flush_in_error_en[0x1]; 4394 u8 hairpin[0x1]; 4395 u8 reserved_at_f[0xb]; 4396 u8 ts_format[0x2]; 4397 u8 reserved_at_1c[0x4]; 4398 4399 u8 reserved_at_20[0x8]; 4400 u8 user_index[0x18]; 4401 4402 u8 reserved_at_40[0x8]; 4403 u8 cqn[0x18]; 4404 4405 u8 counter_set_id[0x8]; 4406 u8 reserved_at_68[0x18]; 4407 4408 u8 reserved_at_80[0x8]; 4409 u8 rmpn[0x18]; 4410 4411 u8 reserved_at_a0[0x8]; 4412 u8 hairpin_peer_sq[0x18]; 4413 4414 u8 reserved_at_c0[0x10]; 4415 u8 hairpin_peer_vhca[0x10]; 4416 4417 u8 reserved_at_e0[0x46]; 4418 u8 shampo_no_match_alignment_granularity[0x2]; 4419 u8 reserved_at_128[0x6]; 4420 u8 shampo_match_criteria_type[0x2]; 4421 u8 reservation_timeout[0x10]; 4422 4423 u8 reserved_at_140[0x40]; 4424 4425 struct mlx5_ifc_wq_bits wq; 4426 }; 4427 4428 enum { 4429 MLX5_RMPC_STATE_RDY = 0x1, 4430 MLX5_RMPC_STATE_ERR = 0x3, 4431 }; 4432 4433 struct mlx5_ifc_rmpc_bits { 4434 u8 reserved_at_0[0x8]; 4435 u8 state[0x4]; 4436 u8 reserved_at_c[0x14]; 4437 4438 u8 basic_cyclic_rcv_wqe[0x1]; 4439 u8 reserved_at_21[0x1f]; 4440 4441 u8 reserved_at_40[0x140]; 4442 4443 struct mlx5_ifc_wq_bits wq; 4444 }; 4445 4446 enum { 4447 VHCA_ID_TYPE_HW = 0, 4448 VHCA_ID_TYPE_SW = 1, 4449 }; 4450 4451 struct mlx5_ifc_nic_vport_context_bits { 4452 u8 reserved_at_0[0x5]; 4453 u8 min_wqe_inline_mode[0x3]; 4454 u8 reserved_at_8[0x15]; 4455 u8 disable_mc_local_lb[0x1]; 4456 u8 disable_uc_local_lb[0x1]; 4457 u8 roce_en[0x1]; 4458 4459 u8 arm_change_event[0x1]; 4460 u8 reserved_at_21[0x1a]; 4461 u8 event_on_mtu[0x1]; 4462 u8 event_on_promisc_change[0x1]; 4463 u8 event_on_vlan_change[0x1]; 4464 u8 event_on_mc_address_change[0x1]; 4465 u8 event_on_uc_address_change[0x1]; 4466 4467 u8 vhca_id_type[0x1]; 4468 u8 reserved_at_41[0xb]; 4469 u8 affiliation_criteria[0x4]; 4470 u8 affiliated_vhca_id[0x10]; 4471 4472 u8 reserved_at_60[0xa0]; 4473 4474 u8 reserved_at_100[0x1]; 4475 u8 sd_group[0x3]; 4476 u8 reserved_at_104[0x4]; 4477 u8 sd_group_size[0x8]; 4478 u8 reserved_at_110[0x10]; 4479 4480 u8 reserved_at_120[0x10]; 4481 u8 mtu[0x10]; 4482 4483 u8 system_image_guid[0x40]; 4484 u8 port_guid[0x40]; 4485 u8 node_guid[0x40]; 4486 4487 u8 reserved_at_200[0x140]; 4488 u8 qkey_violation_counter[0x10]; 4489 u8 reserved_at_350[0x430]; 4490 4491 u8 promisc_uc[0x1]; 4492 u8 promisc_mc[0x1]; 4493 u8 promisc_all[0x1]; 4494 u8 reserved_at_783[0x2]; 4495 u8 allowed_list_type[0x3]; 4496 u8 reserved_at_788[0x8]; 4497 u8 allowed_list_size[0x10]; 4498 4499 struct mlx5_ifc_mac_address_layout_bits permanent_address; 4500 4501 u8 reserved_at_7e0[0x20]; 4502 4503 u8 current_uc_mac_address[][0x40]; 4504 }; 4505 4506 enum { 4507 MLX5_MKC_ACCESS_MODE_PA = 0x0, 4508 MLX5_MKC_ACCESS_MODE_MTT = 0x1, 4509 MLX5_MKC_ACCESS_MODE_KLMS = 0x2, 4510 MLX5_MKC_ACCESS_MODE_KSM = 0x3, 4511 MLX5_MKC_ACCESS_MODE_SW_ICM = 0x4, 4512 MLX5_MKC_ACCESS_MODE_MEMIC = 0x5, 4513 MLX5_MKC_ACCESS_MODE_CROSSING = 0x6, 4514 }; 4515 4516 enum { 4517 MLX5_MKC_PCIE_TPH_NO_STEERING_TAG_INDEX = 0, 4518 }; 4519 4520 struct mlx5_ifc_mkc_bits { 4521 u8 reserved_at_0[0x1]; 4522 u8 free[0x1]; 4523 u8 reserved_at_2[0x1]; 4524 u8 access_mode_4_2[0x3]; 4525 u8 reserved_at_6[0x7]; 4526 u8 relaxed_ordering_write[0x1]; 4527 u8 reserved_at_e[0x1]; 4528 u8 small_fence_on_rdma_read_response[0x1]; 4529 u8 umr_en[0x1]; 4530 u8 a[0x1]; 4531 u8 rw[0x1]; 4532 u8 rr[0x1]; 4533 u8 lw[0x1]; 4534 u8 lr[0x1]; 4535 u8 access_mode_1_0[0x2]; 4536 u8 reserved_at_18[0x2]; 4537 u8 ma_translation_mode[0x2]; 4538 u8 reserved_at_1c[0x4]; 4539 4540 u8 qpn[0x18]; 4541 u8 mkey_7_0[0x8]; 4542 4543 u8 reserved_at_40[0x20]; 4544 4545 u8 length64[0x1]; 4546 u8 bsf_en[0x1]; 4547 u8 sync_umr[0x1]; 4548 u8 reserved_at_63[0x2]; 4549 u8 expected_sigerr_count[0x1]; 4550 u8 reserved_at_66[0x1]; 4551 u8 en_rinval[0x1]; 4552 u8 pd[0x18]; 4553 4554 u8 start_addr[0x40]; 4555 4556 u8 len[0x40]; 4557 4558 u8 bsf_octword_size[0x20]; 4559 4560 u8 reserved_at_120[0x60]; 4561 4562 u8 crossing_target_vhca_id[0x10]; 4563 u8 reserved_at_190[0x10]; 4564 4565 u8 translations_octword_size[0x20]; 4566 4567 u8 reserved_at_1c0[0x19]; 4568 u8 relaxed_ordering_read[0x1]; 4569 u8 log_page_size[0x6]; 4570 4571 u8 reserved_at_1e0[0x5]; 4572 u8 pcie_tph_en[0x1]; 4573 u8 pcie_tph_ph[0x2]; 4574 u8 pcie_tph_steering_tag_index[0x8]; 4575 u8 reserved_at_1f0[0x10]; 4576 }; 4577 4578 struct mlx5_ifc_pkey_bits { 4579 u8 reserved_at_0[0x10]; 4580 u8 pkey[0x10]; 4581 }; 4582 4583 struct mlx5_ifc_array128_auto_bits { 4584 u8 array128_auto[16][0x8]; 4585 }; 4586 4587 struct mlx5_ifc_hca_vport_context_bits { 4588 u8 field_select[0x20]; 4589 4590 u8 reserved_at_20[0xe0]; 4591 4592 u8 sm_virt_aware[0x1]; 4593 u8 has_smi[0x1]; 4594 u8 has_raw[0x1]; 4595 u8 grh_required[0x1]; 4596 u8 reserved_at_104[0x4]; 4597 u8 num_port_plane[0x8]; 4598 u8 port_physical_state[0x4]; 4599 u8 vport_state_policy[0x4]; 4600 u8 port_state[0x4]; 4601 u8 vport_state[0x4]; 4602 4603 u8 reserved_at_120[0x20]; 4604 4605 u8 system_image_guid[0x40]; 4606 4607 u8 port_guid[0x40]; 4608 4609 u8 node_guid[0x40]; 4610 4611 u8 cap_mask1[0x20]; 4612 4613 u8 cap_mask1_field_select[0x20]; 4614 4615 u8 cap_mask2[0x20]; 4616 4617 u8 cap_mask2_field_select[0x20]; 4618 4619 u8 reserved_at_280[0x80]; 4620 4621 u8 lid[0x10]; 4622 u8 reserved_at_310[0x4]; 4623 u8 init_type_reply[0x4]; 4624 u8 lmc[0x3]; 4625 u8 subnet_timeout[0x5]; 4626 4627 u8 sm_lid[0x10]; 4628 u8 sm_sl[0x4]; 4629 u8 reserved_at_334[0xc]; 4630 4631 u8 qkey_violation_counter[0x10]; 4632 u8 pkey_violation_counter[0x10]; 4633 4634 u8 reserved_at_360[0xca0]; 4635 }; 4636 4637 struct mlx5_ifc_esw_vport_context_bits { 4638 u8 fdb_to_vport_reg_c[0x1]; 4639 u8 reserved_at_1[0x2]; 4640 u8 vport_svlan_strip[0x1]; 4641 u8 vport_cvlan_strip[0x1]; 4642 u8 vport_svlan_insert[0x1]; 4643 u8 vport_cvlan_insert[0x2]; 4644 u8 fdb_to_vport_reg_c_id[0x8]; 4645 u8 reserved_at_10[0x10]; 4646 4647 u8 reserved_at_20[0x20]; 4648 4649 u8 svlan_cfi[0x1]; 4650 u8 svlan_pcp[0x3]; 4651 u8 svlan_id[0xc]; 4652 u8 cvlan_cfi[0x1]; 4653 u8 cvlan_pcp[0x3]; 4654 u8 cvlan_id[0xc]; 4655 4656 u8 reserved_at_60[0x720]; 4657 4658 u8 sw_steering_vport_icm_address_rx[0x40]; 4659 4660 u8 sw_steering_vport_icm_address_tx[0x40]; 4661 }; 4662 4663 enum { 4664 MLX5_EQC_STATUS_OK = 0x0, 4665 MLX5_EQC_STATUS_EQ_WRITE_FAILURE = 0xa, 4666 }; 4667 4668 enum { 4669 MLX5_EQC_ST_ARMED = 0x9, 4670 MLX5_EQC_ST_FIRED = 0xa, 4671 }; 4672 4673 struct mlx5_ifc_eqc_bits { 4674 u8 status[0x4]; 4675 u8 reserved_at_4[0x9]; 4676 u8 ec[0x1]; 4677 u8 oi[0x1]; 4678 u8 reserved_at_f[0x5]; 4679 u8 st[0x4]; 4680 u8 reserved_at_18[0x8]; 4681 4682 u8 reserved_at_20[0x20]; 4683 4684 u8 reserved_at_40[0x14]; 4685 u8 page_offset[0x6]; 4686 u8 reserved_at_5a[0x6]; 4687 4688 u8 reserved_at_60[0x3]; 4689 u8 log_eq_size[0x5]; 4690 u8 uar_page[0x18]; 4691 4692 u8 reserved_at_80[0x20]; 4693 4694 u8 reserved_at_a0[0x14]; 4695 u8 intr[0xc]; 4696 4697 u8 reserved_at_c0[0x3]; 4698 u8 log_page_size[0x5]; 4699 u8 reserved_at_c8[0x18]; 4700 4701 u8 reserved_at_e0[0x60]; 4702 4703 u8 reserved_at_140[0x8]; 4704 u8 consumer_counter[0x18]; 4705 4706 u8 reserved_at_160[0x8]; 4707 u8 producer_counter[0x18]; 4708 4709 u8 reserved_at_180[0x80]; 4710 }; 4711 4712 enum { 4713 MLX5_DCTC_STATE_ACTIVE = 0x0, 4714 MLX5_DCTC_STATE_DRAINING = 0x1, 4715 MLX5_DCTC_STATE_DRAINED = 0x2, 4716 }; 4717 4718 enum { 4719 MLX5_DCTC_CS_RES_DISABLE = 0x0, 4720 MLX5_DCTC_CS_RES_NA = 0x1, 4721 MLX5_DCTC_CS_RES_UP_TO_64B = 0x2, 4722 }; 4723 4724 enum { 4725 MLX5_DCTC_MTU_256_BYTES = 0x1, 4726 MLX5_DCTC_MTU_512_BYTES = 0x2, 4727 MLX5_DCTC_MTU_1K_BYTES = 0x3, 4728 MLX5_DCTC_MTU_2K_BYTES = 0x4, 4729 MLX5_DCTC_MTU_4K_BYTES = 0x5, 4730 }; 4731 4732 struct mlx5_ifc_dctc_bits { 4733 u8 reserved_at_0[0x4]; 4734 u8 state[0x4]; 4735 u8 reserved_at_8[0x18]; 4736 4737 u8 reserved_at_20[0x7]; 4738 u8 dp_ordering_force[0x1]; 4739 u8 user_index[0x18]; 4740 4741 u8 reserved_at_40[0x8]; 4742 u8 cqn[0x18]; 4743 4744 u8 counter_set_id[0x8]; 4745 u8 atomic_mode[0x4]; 4746 u8 rre[0x1]; 4747 u8 rwe[0x1]; 4748 u8 rae[0x1]; 4749 u8 atomic_like_write_en[0x1]; 4750 u8 latency_sensitive[0x1]; 4751 u8 rlky[0x1]; 4752 u8 free_ar[0x1]; 4753 u8 reserved_at_73[0x1]; 4754 u8 dp_ordering_1[0x1]; 4755 u8 reserved_at_75[0xb]; 4756 4757 u8 reserved_at_80[0x8]; 4758 u8 cs_res[0x8]; 4759 u8 reserved_at_90[0x3]; 4760 u8 min_rnr_nak[0x5]; 4761 u8 reserved_at_98[0x8]; 4762 4763 u8 reserved_at_a0[0x8]; 4764 u8 srqn_xrqn[0x18]; 4765 4766 u8 reserved_at_c0[0x8]; 4767 u8 pd[0x18]; 4768 4769 u8 tclass[0x8]; 4770 u8 reserved_at_e8[0x4]; 4771 u8 flow_label[0x14]; 4772 4773 u8 dc_access_key[0x40]; 4774 4775 u8 reserved_at_140[0x5]; 4776 u8 mtu[0x3]; 4777 u8 port[0x8]; 4778 u8 pkey_index[0x10]; 4779 4780 u8 reserved_at_160[0x8]; 4781 u8 my_addr_index[0x8]; 4782 u8 reserved_at_170[0x8]; 4783 u8 hop_limit[0x8]; 4784 4785 u8 dc_access_key_violation_count[0x20]; 4786 4787 u8 reserved_at_1a0[0x14]; 4788 u8 dei_cfi[0x1]; 4789 u8 eth_prio[0x3]; 4790 u8 ecn[0x2]; 4791 u8 dscp[0x6]; 4792 4793 u8 reserved_at_1c0[0x20]; 4794 u8 ece[0x20]; 4795 }; 4796 4797 enum { 4798 MLX5_CQC_STATUS_OK = 0x0, 4799 MLX5_CQC_STATUS_CQ_OVERFLOW = 0x9, 4800 MLX5_CQC_STATUS_CQ_WRITE_FAIL = 0xa, 4801 }; 4802 4803 enum { 4804 MLX5_CQC_CQE_SZ_64_BYTES = 0x0, 4805 MLX5_CQC_CQE_SZ_128_BYTES = 0x1, 4806 }; 4807 4808 enum { 4809 MLX5_CQC_ST_SOLICITED_NOTIFICATION_REQUEST_ARMED = 0x6, 4810 MLX5_CQC_ST_NOTIFICATION_REQUEST_ARMED = 0x9, 4811 MLX5_CQC_ST_FIRED = 0xa, 4812 }; 4813 4814 enum mlx5_cq_period_mode { 4815 MLX5_CQ_PERIOD_MODE_START_FROM_EQE = 0x0, 4816 MLX5_CQ_PERIOD_MODE_START_FROM_CQE = 0x1, 4817 MLX5_CQ_PERIOD_NUM_MODES, 4818 }; 4819 4820 struct mlx5_ifc_cqc_bits { 4821 u8 status[0x4]; 4822 u8 reserved_at_4[0x2]; 4823 u8 dbr_umem_valid[0x1]; 4824 u8 apu_cq[0x1]; 4825 u8 cqe_sz[0x3]; 4826 u8 cc[0x1]; 4827 u8 reserved_at_c[0x1]; 4828 u8 scqe_break_moderation_en[0x1]; 4829 u8 oi[0x1]; 4830 u8 cq_period_mode[0x2]; 4831 u8 cqe_comp_en[0x1]; 4832 u8 mini_cqe_res_format[0x2]; 4833 u8 st[0x4]; 4834 u8 reserved_at_18[0x6]; 4835 u8 cqe_compression_layout[0x2]; 4836 4837 u8 reserved_at_20[0x20]; 4838 4839 u8 reserved_at_40[0x14]; 4840 u8 page_offset[0x6]; 4841 u8 reserved_at_5a[0x6]; 4842 4843 u8 reserved_at_60[0x3]; 4844 u8 log_cq_size[0x5]; 4845 u8 uar_page[0x18]; 4846 4847 u8 reserved_at_80[0x4]; 4848 u8 cq_period[0xc]; 4849 u8 cq_max_count[0x10]; 4850 4851 u8 c_eqn_or_apu_element[0x20]; 4852 4853 u8 reserved_at_c0[0x3]; 4854 u8 log_page_size[0x5]; 4855 u8 reserved_at_c8[0x18]; 4856 4857 u8 reserved_at_e0[0x20]; 4858 4859 u8 reserved_at_100[0x8]; 4860 u8 last_notified_index[0x18]; 4861 4862 u8 reserved_at_120[0x8]; 4863 u8 last_solicit_index[0x18]; 4864 4865 u8 reserved_at_140[0x8]; 4866 u8 consumer_counter[0x18]; 4867 4868 u8 reserved_at_160[0x8]; 4869 u8 producer_counter[0x18]; 4870 4871 u8 reserved_at_180[0x40]; 4872 4873 u8 dbr_addr[0x40]; 4874 }; 4875 4876 union mlx5_ifc_cong_control_roce_ecn_auto_bits { 4877 struct mlx5_ifc_cong_control_802_1qau_rp_bits cong_control_802_1qau_rp; 4878 struct mlx5_ifc_cong_control_r_roce_ecn_rp_bits cong_control_r_roce_ecn_rp; 4879 struct mlx5_ifc_cong_control_r_roce_ecn_np_bits cong_control_r_roce_ecn_np; 4880 struct mlx5_ifc_cong_control_r_roce_general_bits cong_control_r_roce_general; 4881 u8 reserved_at_0[0x800]; 4882 }; 4883 4884 struct mlx5_ifc_query_adapter_param_block_bits { 4885 u8 reserved_at_0[0xc0]; 4886 4887 u8 reserved_at_c0[0x8]; 4888 u8 ieee_vendor_id[0x18]; 4889 4890 u8 reserved_at_e0[0x10]; 4891 u8 vsd_vendor_id[0x10]; 4892 4893 u8 vsd[208][0x8]; 4894 4895 u8 vsd_contd_psid[16][0x8]; 4896 }; 4897 4898 enum { 4899 MLX5_XRQC_STATE_GOOD = 0x0, 4900 MLX5_XRQC_STATE_ERROR = 0x1, 4901 }; 4902 4903 enum { 4904 MLX5_XRQC_TOPOLOGY_NO_SPECIAL_TOPOLOGY = 0x0, 4905 MLX5_XRQC_TOPOLOGY_TAG_MATCHING = 0x1, 4906 }; 4907 4908 enum { 4909 MLX5_XRQC_OFFLOAD_RNDV = 0x1, 4910 }; 4911 4912 struct mlx5_ifc_tag_matching_topology_context_bits { 4913 u8 log_matching_list_sz[0x4]; 4914 u8 reserved_at_4[0xc]; 4915 u8 append_next_index[0x10]; 4916 4917 u8 sw_phase_cnt[0x10]; 4918 u8 hw_phase_cnt[0x10]; 4919 4920 u8 reserved_at_40[0x40]; 4921 }; 4922 4923 struct mlx5_ifc_xrqc_bits { 4924 u8 state[0x4]; 4925 u8 rlkey[0x1]; 4926 u8 reserved_at_5[0xf]; 4927 u8 topology[0x4]; 4928 u8 reserved_at_18[0x4]; 4929 u8 offload[0x4]; 4930 4931 u8 reserved_at_20[0x8]; 4932 u8 user_index[0x18]; 4933 4934 u8 reserved_at_40[0x8]; 4935 u8 cqn[0x18]; 4936 4937 u8 reserved_at_60[0xa0]; 4938 4939 struct mlx5_ifc_tag_matching_topology_context_bits tag_matching_topology_context; 4940 4941 u8 reserved_at_180[0x280]; 4942 4943 struct mlx5_ifc_wq_bits wq; 4944 }; 4945 4946 union mlx5_ifc_modify_field_select_resize_field_select_auto_bits { 4947 struct mlx5_ifc_modify_field_select_bits modify_field_select; 4948 struct mlx5_ifc_resize_field_select_bits resize_field_select; 4949 u8 reserved_at_0[0x20]; 4950 }; 4951 4952 union mlx5_ifc_field_select_802_1_r_roce_auto_bits { 4953 struct mlx5_ifc_field_select_802_1qau_rp_bits field_select_802_1qau_rp; 4954 struct mlx5_ifc_field_select_r_roce_rp_bits field_select_r_roce_rp; 4955 struct mlx5_ifc_field_select_r_roce_np_bits field_select_r_roce_np; 4956 u8 reserved_at_0[0x20]; 4957 }; 4958 4959 struct mlx5_ifc_rs_histogram_cntrs_bits { 4960 u8 hist[16][0x40]; 4961 u8 reserved_at_400[0x2c0]; 4962 }; 4963 4964 union mlx5_ifc_eth_cntrs_grp_data_layout_auto_bits { 4965 struct mlx5_ifc_eth_802_3_cntrs_grp_data_layout_bits eth_802_3_cntrs_grp_data_layout; 4966 struct mlx5_ifc_eth_2863_cntrs_grp_data_layout_bits eth_2863_cntrs_grp_data_layout; 4967 struct mlx5_ifc_eth_2819_cntrs_grp_data_layout_bits eth_2819_cntrs_grp_data_layout; 4968 struct mlx5_ifc_eth_3635_cntrs_grp_data_layout_bits eth_3635_cntrs_grp_data_layout; 4969 struct mlx5_ifc_eth_extended_cntrs_grp_data_layout_bits eth_extended_cntrs_grp_data_layout; 4970 struct mlx5_ifc_eth_per_prio_grp_data_layout_bits eth_per_prio_grp_data_layout; 4971 struct mlx5_ifc_eth_per_tc_prio_grp_data_layout_bits eth_per_tc_prio_grp_data_layout; 4972 struct mlx5_ifc_eth_per_tc_congest_prio_grp_data_layout_bits eth_per_tc_congest_prio_grp_data_layout; 4973 struct mlx5_ifc_ib_port_cntrs_grp_data_layout_bits ib_port_cntrs_grp_data_layout; 4974 struct mlx5_ifc_ib_ext_port_cntrs_grp_data_layout_bits ib_ext_port_cntrs_grp_data_layout; 4975 struct mlx5_ifc_phys_layer_cntrs_bits phys_layer_cntrs; 4976 struct mlx5_ifc_phys_layer_statistical_cntrs_bits phys_layer_statistical_cntrs; 4977 struct mlx5_ifc_phys_layer_recovery_cntrs_bits phys_layer_recovery_cntrs; 4978 struct mlx5_ifc_rs_histogram_cntrs_bits rs_histogram_cntrs; 4979 u8 reserved_at_0[0x7c0]; 4980 }; 4981 4982 union mlx5_ifc_pcie_cntrs_grp_data_layout_auto_bits { 4983 struct mlx5_ifc_pcie_perf_cntrs_grp_data_layout_bits pcie_perf_cntrs_grp_data_layout; 4984 u8 reserved_at_0[0x7c0]; 4985 }; 4986 4987 union mlx5_ifc_event_auto_bits { 4988 struct mlx5_ifc_comp_event_bits comp_event; 4989 struct mlx5_ifc_dct_events_bits dct_events; 4990 struct mlx5_ifc_qp_events_bits qp_events; 4991 struct mlx5_ifc_wqe_associated_page_fault_event_bits wqe_associated_page_fault_event; 4992 struct mlx5_ifc_rdma_page_fault_event_bits rdma_page_fault_event; 4993 struct mlx5_ifc_cq_error_bits cq_error; 4994 struct mlx5_ifc_dropped_packet_logged_bits dropped_packet_logged; 4995 struct mlx5_ifc_port_state_change_event_bits port_state_change_event; 4996 struct mlx5_ifc_gpio_event_bits gpio_event; 4997 struct mlx5_ifc_db_bf_congestion_event_bits db_bf_congestion_event; 4998 struct mlx5_ifc_stall_vl_event_bits stall_vl_event; 4999 struct mlx5_ifc_cmd_inter_comp_event_bits cmd_inter_comp_event; 5000 u8 reserved_at_0[0xe0]; 5001 }; 5002 5003 struct mlx5_ifc_health_buffer_bits { 5004 u8 reserved_at_0[0x100]; 5005 5006 u8 assert_existptr[0x20]; 5007 5008 u8 assert_callra[0x20]; 5009 5010 u8 reserved_at_140[0x20]; 5011 5012 u8 time[0x20]; 5013 5014 u8 fw_version[0x20]; 5015 5016 u8 hw_id[0x20]; 5017 5018 u8 rfr[0x1]; 5019 u8 reserved_at_1c1[0x3]; 5020 u8 valid[0x1]; 5021 u8 severity[0x3]; 5022 u8 reserved_at_1c8[0x18]; 5023 5024 u8 irisc_index[0x8]; 5025 u8 synd[0x8]; 5026 u8 ext_synd[0x10]; 5027 }; 5028 5029 struct mlx5_ifc_register_loopback_control_bits { 5030 u8 no_lb[0x1]; 5031 u8 reserved_at_1[0x7]; 5032 u8 port[0x8]; 5033 u8 reserved_at_10[0x10]; 5034 5035 u8 reserved_at_20[0x60]; 5036 }; 5037 5038 enum { 5039 MLX5_TEARDOWN_HCA_OUT_FORCE_STATE_SUCCESS = 0x0, 5040 MLX5_TEARDOWN_HCA_OUT_FORCE_STATE_FAIL = 0x1, 5041 }; 5042 5043 struct mlx5_ifc_teardown_hca_out_bits { 5044 u8 status[0x8]; 5045 u8 reserved_at_8[0x18]; 5046 5047 u8 syndrome[0x20]; 5048 5049 u8 reserved_at_40[0x3f]; 5050 5051 u8 state[0x1]; 5052 }; 5053 5054 enum { 5055 MLX5_TEARDOWN_HCA_IN_PROFILE_GRACEFUL_CLOSE = 0x0, 5056 MLX5_TEARDOWN_HCA_IN_PROFILE_FORCE_CLOSE = 0x1, 5057 MLX5_TEARDOWN_HCA_IN_PROFILE_PREPARE_FAST_TEARDOWN = 0x2, 5058 }; 5059 5060 struct mlx5_ifc_teardown_hca_in_bits { 5061 u8 opcode[0x10]; 5062 u8 reserved_at_10[0x10]; 5063 5064 u8 reserved_at_20[0x10]; 5065 u8 op_mod[0x10]; 5066 5067 u8 reserved_at_40[0x10]; 5068 u8 profile[0x10]; 5069 5070 u8 reserved_at_60[0x20]; 5071 }; 5072 5073 struct mlx5_ifc_sqerr2rts_qp_out_bits { 5074 u8 status[0x8]; 5075 u8 reserved_at_8[0x18]; 5076 5077 u8 syndrome[0x20]; 5078 5079 u8 reserved_at_40[0x40]; 5080 }; 5081 5082 struct mlx5_ifc_sqerr2rts_qp_in_bits { 5083 u8 opcode[0x10]; 5084 u8 uid[0x10]; 5085 5086 u8 reserved_at_20[0x10]; 5087 u8 op_mod[0x10]; 5088 5089 u8 reserved_at_40[0x8]; 5090 u8 qpn[0x18]; 5091 5092 u8 reserved_at_60[0x20]; 5093 5094 u8 opt_param_mask[0x20]; 5095 5096 u8 reserved_at_a0[0x20]; 5097 5098 struct mlx5_ifc_qpc_bits qpc; 5099 5100 u8 reserved_at_800[0x80]; 5101 }; 5102 5103 struct mlx5_ifc_sqd2rts_qp_out_bits { 5104 u8 status[0x8]; 5105 u8 reserved_at_8[0x18]; 5106 5107 u8 syndrome[0x20]; 5108 5109 u8 reserved_at_40[0x40]; 5110 }; 5111 5112 struct mlx5_ifc_sqd2rts_qp_in_bits { 5113 u8 opcode[0x10]; 5114 u8 uid[0x10]; 5115 5116 u8 reserved_at_20[0x10]; 5117 u8 op_mod[0x10]; 5118 5119 u8 reserved_at_40[0x8]; 5120 u8 qpn[0x18]; 5121 5122 u8 reserved_at_60[0x20]; 5123 5124 u8 opt_param_mask[0x20]; 5125 5126 u8 reserved_at_a0[0x20]; 5127 5128 struct mlx5_ifc_qpc_bits qpc; 5129 5130 u8 reserved_at_800[0x80]; 5131 }; 5132 5133 struct mlx5_ifc_set_roce_address_out_bits { 5134 u8 status[0x8]; 5135 u8 reserved_at_8[0x18]; 5136 5137 u8 syndrome[0x20]; 5138 5139 u8 reserved_at_40[0x40]; 5140 }; 5141 5142 struct mlx5_ifc_set_roce_address_in_bits { 5143 u8 opcode[0x10]; 5144 u8 reserved_at_10[0x10]; 5145 5146 u8 reserved_at_20[0x10]; 5147 u8 op_mod[0x10]; 5148 5149 u8 roce_address_index[0x10]; 5150 u8 reserved_at_50[0xc]; 5151 u8 vhca_port_num[0x4]; 5152 5153 u8 reserved_at_60[0x20]; 5154 5155 struct mlx5_ifc_roce_addr_layout_bits roce_address; 5156 }; 5157 5158 struct mlx5_ifc_set_mad_demux_out_bits { 5159 u8 status[0x8]; 5160 u8 reserved_at_8[0x18]; 5161 5162 u8 syndrome[0x20]; 5163 5164 u8 reserved_at_40[0x40]; 5165 }; 5166 5167 enum { 5168 MLX5_SET_MAD_DEMUX_IN_DEMUX_MODE_PASS_ALL = 0x0, 5169 MLX5_SET_MAD_DEMUX_IN_DEMUX_MODE_SELECTIVE = 0x2, 5170 }; 5171 5172 struct mlx5_ifc_set_mad_demux_in_bits { 5173 u8 opcode[0x10]; 5174 u8 reserved_at_10[0x10]; 5175 5176 u8 reserved_at_20[0x10]; 5177 u8 op_mod[0x10]; 5178 5179 u8 reserved_at_40[0x20]; 5180 5181 u8 reserved_at_60[0x6]; 5182 u8 demux_mode[0x2]; 5183 u8 reserved_at_68[0x18]; 5184 }; 5185 5186 struct mlx5_ifc_set_l2_table_entry_out_bits { 5187 u8 status[0x8]; 5188 u8 reserved_at_8[0x18]; 5189 5190 u8 syndrome[0x20]; 5191 5192 u8 reserved_at_40[0x40]; 5193 }; 5194 5195 struct mlx5_ifc_set_l2_table_entry_in_bits { 5196 u8 opcode[0x10]; 5197 u8 reserved_at_10[0x10]; 5198 5199 u8 reserved_at_20[0x10]; 5200 u8 op_mod[0x10]; 5201 5202 u8 reserved_at_40[0x60]; 5203 5204 u8 reserved_at_a0[0x8]; 5205 u8 table_index[0x18]; 5206 5207 u8 reserved_at_c0[0x20]; 5208 5209 u8 reserved_at_e0[0x10]; 5210 u8 silent_mode_valid[0x1]; 5211 u8 silent_mode[0x1]; 5212 u8 reserved_at_f2[0x1]; 5213 u8 vlan_valid[0x1]; 5214 u8 vlan[0xc]; 5215 5216 struct mlx5_ifc_mac_address_layout_bits mac_address; 5217 5218 u8 reserved_at_140[0xc0]; 5219 }; 5220 5221 struct mlx5_ifc_set_issi_out_bits { 5222 u8 status[0x8]; 5223 u8 reserved_at_8[0x18]; 5224 5225 u8 syndrome[0x20]; 5226 5227 u8 reserved_at_40[0x40]; 5228 }; 5229 5230 struct mlx5_ifc_set_issi_in_bits { 5231 u8 opcode[0x10]; 5232 u8 reserved_at_10[0x10]; 5233 5234 u8 reserved_at_20[0x10]; 5235 u8 op_mod[0x10]; 5236 5237 u8 reserved_at_40[0x10]; 5238 u8 current_issi[0x10]; 5239 5240 u8 reserved_at_60[0x20]; 5241 }; 5242 5243 struct mlx5_ifc_set_hca_cap_out_bits { 5244 u8 status[0x8]; 5245 u8 reserved_at_8[0x18]; 5246 5247 u8 syndrome[0x20]; 5248 5249 u8 reserved_at_40[0x40]; 5250 }; 5251 5252 struct mlx5_ifc_set_hca_cap_in_bits { 5253 u8 opcode[0x10]; 5254 u8 reserved_at_10[0x10]; 5255 5256 u8 reserved_at_20[0x10]; 5257 u8 op_mod[0x10]; 5258 5259 u8 other_function[0x1]; 5260 u8 ec_vf_function[0x1]; 5261 u8 reserved_at_42[0x1]; 5262 u8 function_id_type[0x1]; 5263 u8 reserved_at_44[0xc]; 5264 u8 function_id[0x10]; 5265 5266 u8 reserved_at_60[0x20]; 5267 5268 union mlx5_ifc_hca_cap_union_bits capability; 5269 }; 5270 5271 enum { 5272 MLX5_SET_FTE_MODIFY_ENABLE_MASK_ACTION = 0x0, 5273 MLX5_SET_FTE_MODIFY_ENABLE_MASK_FLOW_TAG = 0x1, 5274 MLX5_SET_FTE_MODIFY_ENABLE_MASK_DESTINATION_LIST = 0x2, 5275 MLX5_SET_FTE_MODIFY_ENABLE_MASK_FLOW_COUNTERS = 0x3, 5276 MLX5_SET_FTE_MODIFY_ENABLE_MASK_IPSEC_OBJ_ID = 0x4 5277 }; 5278 5279 struct mlx5_ifc_set_fte_out_bits { 5280 u8 status[0x8]; 5281 u8 reserved_at_8[0x18]; 5282 5283 u8 syndrome[0x20]; 5284 5285 u8 reserved_at_40[0x40]; 5286 }; 5287 5288 struct mlx5_ifc_set_fte_in_bits { 5289 u8 opcode[0x10]; 5290 u8 reserved_at_10[0x10]; 5291 5292 u8 reserved_at_20[0x10]; 5293 u8 op_mod[0x10]; 5294 5295 u8 other_vport[0x1]; 5296 u8 other_eswitch[0x1]; 5297 u8 reserved_at_42[0xe]; 5298 u8 vport_number[0x10]; 5299 5300 u8 reserved_at_60[0x20]; 5301 5302 u8 table_type[0x8]; 5303 u8 reserved_at_88[0x8]; 5304 u8 eswitch_owner_vhca_id[0x10]; 5305 5306 u8 reserved_at_a0[0x8]; 5307 u8 table_id[0x18]; 5308 5309 u8 ignore_flow_level[0x1]; 5310 u8 reserved_at_c1[0x17]; 5311 u8 modify_enable_mask[0x8]; 5312 5313 u8 reserved_at_e0[0x20]; 5314 5315 u8 flow_index[0x20]; 5316 5317 u8 reserved_at_120[0xe0]; 5318 5319 struct mlx5_ifc_flow_context_bits flow_context; 5320 }; 5321 5322 struct mlx5_ifc_dest_format_bits { 5323 u8 destination_type[0x8]; 5324 u8 destination_id[0x18]; 5325 5326 u8 destination_eswitch_owner_vhca_id_valid[0x1]; 5327 u8 packet_reformat[0x1]; 5328 u8 reserved_at_22[0xe]; 5329 u8 destination_eswitch_owner_vhca_id[0x10]; 5330 }; 5331 5332 struct mlx5_ifc_rts2rts_qp_out_bits { 5333 u8 status[0x8]; 5334 u8 reserved_at_8[0x18]; 5335 5336 u8 syndrome[0x20]; 5337 5338 u8 reserved_at_40[0x20]; 5339 u8 ece[0x20]; 5340 }; 5341 5342 struct mlx5_ifc_rts2rts_qp_in_bits { 5343 u8 opcode[0x10]; 5344 u8 uid[0x10]; 5345 5346 u8 reserved_at_20[0x10]; 5347 u8 op_mod[0x10]; 5348 5349 u8 reserved_at_40[0x8]; 5350 u8 qpn[0x18]; 5351 5352 u8 reserved_at_60[0x20]; 5353 5354 u8 opt_param_mask[0x20]; 5355 5356 u8 ece[0x20]; 5357 5358 struct mlx5_ifc_qpc_bits qpc; 5359 5360 u8 reserved_at_800[0x80]; 5361 }; 5362 5363 struct mlx5_ifc_rtr2rts_qp_out_bits { 5364 u8 status[0x8]; 5365 u8 reserved_at_8[0x18]; 5366 5367 u8 syndrome[0x20]; 5368 5369 u8 reserved_at_40[0x20]; 5370 u8 ece[0x20]; 5371 }; 5372 5373 struct mlx5_ifc_rtr2rts_qp_in_bits { 5374 u8 opcode[0x10]; 5375 u8 uid[0x10]; 5376 5377 u8 reserved_at_20[0x10]; 5378 u8 op_mod[0x10]; 5379 5380 u8 reserved_at_40[0x8]; 5381 u8 qpn[0x18]; 5382 5383 u8 reserved_at_60[0x20]; 5384 5385 u8 opt_param_mask[0x20]; 5386 5387 u8 ece[0x20]; 5388 5389 struct mlx5_ifc_qpc_bits qpc; 5390 5391 u8 reserved_at_800[0x80]; 5392 }; 5393 5394 struct mlx5_ifc_rst2init_qp_out_bits { 5395 u8 status[0x8]; 5396 u8 reserved_at_8[0x18]; 5397 5398 u8 syndrome[0x20]; 5399 5400 u8 reserved_at_40[0x20]; 5401 u8 ece[0x20]; 5402 }; 5403 5404 struct mlx5_ifc_rst2init_qp_in_bits { 5405 u8 opcode[0x10]; 5406 u8 uid[0x10]; 5407 5408 u8 reserved_at_20[0x10]; 5409 u8 op_mod[0x10]; 5410 5411 u8 reserved_at_40[0x8]; 5412 u8 qpn[0x18]; 5413 5414 u8 reserved_at_60[0x20]; 5415 5416 u8 opt_param_mask[0x20]; 5417 5418 u8 ece[0x20]; 5419 5420 struct mlx5_ifc_qpc_bits qpc; 5421 5422 u8 reserved_at_800[0x80]; 5423 }; 5424 5425 struct mlx5_ifc_query_xrq_out_bits { 5426 u8 status[0x8]; 5427 u8 reserved_at_8[0x18]; 5428 5429 u8 syndrome[0x20]; 5430 5431 u8 reserved_at_40[0x40]; 5432 5433 struct mlx5_ifc_xrqc_bits xrq_context; 5434 }; 5435 5436 struct mlx5_ifc_query_xrq_in_bits { 5437 u8 opcode[0x10]; 5438 u8 reserved_at_10[0x10]; 5439 5440 u8 reserved_at_20[0x10]; 5441 u8 op_mod[0x10]; 5442 5443 u8 reserved_at_40[0x8]; 5444 u8 xrqn[0x18]; 5445 5446 u8 reserved_at_60[0x20]; 5447 }; 5448 5449 struct mlx5_ifc_query_xrc_srq_out_bits { 5450 u8 status[0x8]; 5451 u8 reserved_at_8[0x18]; 5452 5453 u8 syndrome[0x20]; 5454 5455 u8 reserved_at_40[0x40]; 5456 5457 struct mlx5_ifc_xrc_srqc_bits xrc_srq_context_entry; 5458 5459 u8 reserved_at_280[0x600]; 5460 5461 u8 pas[][0x40]; 5462 }; 5463 5464 struct mlx5_ifc_query_xrc_srq_in_bits { 5465 u8 opcode[0x10]; 5466 u8 reserved_at_10[0x10]; 5467 5468 u8 reserved_at_20[0x10]; 5469 u8 op_mod[0x10]; 5470 5471 u8 reserved_at_40[0x8]; 5472 u8 xrc_srqn[0x18]; 5473 5474 u8 reserved_at_60[0x20]; 5475 }; 5476 5477 enum { 5478 MLX5_QUERY_VPORT_STATE_OUT_STATE_DOWN = 0x0, 5479 MLX5_QUERY_VPORT_STATE_OUT_STATE_UP = 0x1, 5480 }; 5481 5482 struct mlx5_ifc_query_vport_state_out_bits { 5483 u8 status[0x8]; 5484 u8 reserved_at_8[0x18]; 5485 5486 u8 syndrome[0x20]; 5487 5488 u8 reserved_at_40[0x20]; 5489 5490 u8 max_tx_speed[0x10]; 5491 u8 reserved_at_70[0x8]; 5492 u8 admin_state[0x4]; 5493 u8 state[0x4]; 5494 }; 5495 5496 struct mlx5_ifc_array1024_auto_bits { 5497 u8 array1024_auto[32][0x20]; 5498 }; 5499 5500 struct mlx5_ifc_query_vuid_in_bits { 5501 u8 opcode[0x10]; 5502 u8 uid[0x10]; 5503 5504 u8 reserved_at_20[0x40]; 5505 5506 u8 query_vfs_vuid[0x1]; 5507 u8 data_direct[0x1]; 5508 u8 reserved_at_62[0xe]; 5509 u8 vhca_id[0x10]; 5510 }; 5511 5512 struct mlx5_ifc_query_vuid_out_bits { 5513 u8 status[0x8]; 5514 u8 reserved_at_8[0x18]; 5515 5516 u8 syndrome[0x20]; 5517 5518 u8 reserved_at_40[0x1a0]; 5519 5520 u8 reserved_at_1e0[0x10]; 5521 u8 num_of_entries[0x10]; 5522 5523 struct mlx5_ifc_array1024_auto_bits vuid[]; 5524 }; 5525 5526 enum { 5527 MLX5_VPORT_STATE_OP_MOD_VNIC_VPORT = 0x0, 5528 MLX5_VPORT_STATE_OP_MOD_ESW_VPORT = 0x1, 5529 MLX5_VPORT_STATE_OP_MOD_UPLINK = 0x2, 5530 }; 5531 5532 struct mlx5_ifc_arm_monitor_counter_in_bits { 5533 u8 opcode[0x10]; 5534 u8 uid[0x10]; 5535 5536 u8 reserved_at_20[0x10]; 5537 u8 op_mod[0x10]; 5538 5539 u8 reserved_at_40[0x20]; 5540 5541 u8 reserved_at_60[0x20]; 5542 }; 5543 5544 struct mlx5_ifc_arm_monitor_counter_out_bits { 5545 u8 status[0x8]; 5546 u8 reserved_at_8[0x18]; 5547 5548 u8 syndrome[0x20]; 5549 5550 u8 reserved_at_40[0x40]; 5551 }; 5552 5553 enum { 5554 MLX5_QUERY_MONITOR_CNT_TYPE_PPCNT = 0x0, 5555 MLX5_QUERY_MONITOR_CNT_TYPE_Q_COUNTER = 0x1, 5556 }; 5557 5558 enum mlx5_monitor_counter_ppcnt { 5559 MLX5_QUERY_MONITOR_PPCNT_IN_RANGE_LENGTH_ERRORS = 0x0, 5560 MLX5_QUERY_MONITOR_PPCNT_OUT_OF_RANGE_LENGTH_FIELD = 0x1, 5561 MLX5_QUERY_MONITOR_PPCNT_FRAME_TOO_LONG_ERRORS = 0x2, 5562 MLX5_QUERY_MONITOR_PPCNT_FRAME_CHECK_SEQUENCE_ERRORS = 0x3, 5563 MLX5_QUERY_MONITOR_PPCNT_ALIGNMENT_ERRORS = 0x4, 5564 MLX5_QUERY_MONITOR_PPCNT_IF_OUT_DISCARDS = 0x5, 5565 }; 5566 5567 enum { 5568 MLX5_QUERY_MONITOR_Q_COUNTER_RX_OUT_OF_BUFFER = 0x4, 5569 }; 5570 5571 struct mlx5_ifc_monitor_counter_output_bits { 5572 u8 reserved_at_0[0x4]; 5573 u8 type[0x4]; 5574 u8 reserved_at_8[0x8]; 5575 u8 counter[0x10]; 5576 5577 u8 counter_group_id[0x20]; 5578 }; 5579 5580 #define MLX5_CMD_SET_MONITOR_NUM_PPCNT_COUNTER_SET1 (6) 5581 #define MLX5_CMD_SET_MONITOR_NUM_Q_COUNTERS_SET1 (1) 5582 #define MLX5_CMD_SET_MONITOR_NUM_COUNTER (MLX5_CMD_SET_MONITOR_NUM_PPCNT_COUNTER_SET1 +\ 5583 MLX5_CMD_SET_MONITOR_NUM_Q_COUNTERS_SET1) 5584 5585 struct mlx5_ifc_set_monitor_counter_in_bits { 5586 u8 opcode[0x10]; 5587 u8 uid[0x10]; 5588 5589 u8 reserved_at_20[0x10]; 5590 u8 op_mod[0x10]; 5591 5592 u8 reserved_at_40[0x10]; 5593 u8 num_of_counters[0x10]; 5594 5595 u8 reserved_at_60[0x20]; 5596 5597 struct mlx5_ifc_monitor_counter_output_bits monitor_counter[MLX5_CMD_SET_MONITOR_NUM_COUNTER]; 5598 }; 5599 5600 struct mlx5_ifc_set_monitor_counter_out_bits { 5601 u8 status[0x8]; 5602 u8 reserved_at_8[0x18]; 5603 5604 u8 syndrome[0x20]; 5605 5606 u8 reserved_at_40[0x40]; 5607 }; 5608 5609 struct mlx5_ifc_query_vport_state_in_bits { 5610 u8 opcode[0x10]; 5611 u8 reserved_at_10[0x10]; 5612 5613 u8 reserved_at_20[0x10]; 5614 u8 op_mod[0x10]; 5615 5616 u8 other_vport[0x1]; 5617 u8 reserved_at_41[0xf]; 5618 u8 vport_number[0x10]; 5619 5620 u8 reserved_at_60[0x20]; 5621 }; 5622 5623 struct mlx5_ifc_query_vnic_env_out_bits { 5624 u8 status[0x8]; 5625 u8 reserved_at_8[0x18]; 5626 5627 u8 syndrome[0x20]; 5628 5629 u8 reserved_at_40[0x40]; 5630 5631 struct mlx5_ifc_vnic_diagnostic_statistics_bits vport_env; 5632 }; 5633 5634 enum { 5635 MLX5_QUERY_VNIC_ENV_IN_OP_MOD_VPORT_DIAG_STATISTICS = 0x0, 5636 }; 5637 5638 struct mlx5_ifc_query_vnic_env_in_bits { 5639 u8 opcode[0x10]; 5640 u8 reserved_at_10[0x10]; 5641 5642 u8 reserved_at_20[0x10]; 5643 u8 op_mod[0x10]; 5644 5645 u8 other_vport[0x1]; 5646 u8 reserved_at_41[0xf]; 5647 u8 vport_number[0x10]; 5648 5649 u8 reserved_at_60[0x20]; 5650 }; 5651 5652 struct mlx5_ifc_query_vport_counter_out_bits { 5653 u8 status[0x8]; 5654 u8 reserved_at_8[0x18]; 5655 5656 u8 syndrome[0x20]; 5657 5658 u8 reserved_at_40[0x40]; 5659 5660 struct mlx5_ifc_traffic_counter_bits received_errors; 5661 5662 struct mlx5_ifc_traffic_counter_bits transmit_errors; 5663 5664 struct mlx5_ifc_traffic_counter_bits received_ib_unicast; 5665 5666 struct mlx5_ifc_traffic_counter_bits transmitted_ib_unicast; 5667 5668 struct mlx5_ifc_traffic_counter_bits received_ib_multicast; 5669 5670 struct mlx5_ifc_traffic_counter_bits transmitted_ib_multicast; 5671 5672 struct mlx5_ifc_traffic_counter_bits received_eth_broadcast; 5673 5674 struct mlx5_ifc_traffic_counter_bits transmitted_eth_broadcast; 5675 5676 struct mlx5_ifc_traffic_counter_bits received_eth_unicast; 5677 5678 struct mlx5_ifc_traffic_counter_bits transmitted_eth_unicast; 5679 5680 struct mlx5_ifc_traffic_counter_bits received_eth_multicast; 5681 5682 struct mlx5_ifc_traffic_counter_bits transmitted_eth_multicast; 5683 5684 struct mlx5_ifc_traffic_counter_bits local_loopback; 5685 5686 u8 reserved_at_700[0x980]; 5687 }; 5688 5689 enum { 5690 MLX5_QUERY_VPORT_COUNTER_IN_OP_MOD_VPORT_COUNTERS = 0x0, 5691 }; 5692 5693 struct mlx5_ifc_query_vport_counter_in_bits { 5694 u8 opcode[0x10]; 5695 u8 reserved_at_10[0x10]; 5696 5697 u8 reserved_at_20[0x10]; 5698 u8 op_mod[0x10]; 5699 5700 u8 other_vport[0x1]; 5701 u8 reserved_at_41[0xb]; 5702 u8 port_num[0x4]; 5703 u8 vport_number[0x10]; 5704 5705 u8 reserved_at_60[0x60]; 5706 5707 u8 clear[0x1]; 5708 u8 reserved_at_c1[0x1f]; 5709 5710 u8 reserved_at_e0[0x20]; 5711 }; 5712 5713 struct mlx5_ifc_query_tis_out_bits { 5714 u8 status[0x8]; 5715 u8 reserved_at_8[0x18]; 5716 5717 u8 syndrome[0x20]; 5718 5719 u8 reserved_at_40[0x40]; 5720 5721 struct mlx5_ifc_tisc_bits tis_context; 5722 }; 5723 5724 struct mlx5_ifc_query_tis_in_bits { 5725 u8 opcode[0x10]; 5726 u8 reserved_at_10[0x10]; 5727 5728 u8 reserved_at_20[0x10]; 5729 u8 op_mod[0x10]; 5730 5731 u8 reserved_at_40[0x8]; 5732 u8 tisn[0x18]; 5733 5734 u8 reserved_at_60[0x20]; 5735 }; 5736 5737 struct mlx5_ifc_query_tir_out_bits { 5738 u8 status[0x8]; 5739 u8 reserved_at_8[0x18]; 5740 5741 u8 syndrome[0x20]; 5742 5743 u8 reserved_at_40[0xc0]; 5744 5745 struct mlx5_ifc_tirc_bits tir_context; 5746 }; 5747 5748 struct mlx5_ifc_query_tir_in_bits { 5749 u8 opcode[0x10]; 5750 u8 reserved_at_10[0x10]; 5751 5752 u8 reserved_at_20[0x10]; 5753 u8 op_mod[0x10]; 5754 5755 u8 reserved_at_40[0x8]; 5756 u8 tirn[0x18]; 5757 5758 u8 reserved_at_60[0x20]; 5759 }; 5760 5761 struct mlx5_ifc_query_srq_out_bits { 5762 u8 status[0x8]; 5763 u8 reserved_at_8[0x18]; 5764 5765 u8 syndrome[0x20]; 5766 5767 u8 reserved_at_40[0x40]; 5768 5769 struct mlx5_ifc_srqc_bits srq_context_entry; 5770 5771 u8 reserved_at_280[0x600]; 5772 5773 u8 pas[][0x40]; 5774 }; 5775 5776 struct mlx5_ifc_query_srq_in_bits { 5777 u8 opcode[0x10]; 5778 u8 reserved_at_10[0x10]; 5779 5780 u8 reserved_at_20[0x10]; 5781 u8 op_mod[0x10]; 5782 5783 u8 reserved_at_40[0x8]; 5784 u8 srqn[0x18]; 5785 5786 u8 reserved_at_60[0x20]; 5787 }; 5788 5789 struct mlx5_ifc_query_sq_out_bits { 5790 u8 status[0x8]; 5791 u8 reserved_at_8[0x18]; 5792 5793 u8 syndrome[0x20]; 5794 5795 u8 reserved_at_40[0xc0]; 5796 5797 struct mlx5_ifc_sqc_bits sq_context; 5798 }; 5799 5800 struct mlx5_ifc_query_sq_in_bits { 5801 u8 opcode[0x10]; 5802 u8 reserved_at_10[0x10]; 5803 5804 u8 reserved_at_20[0x10]; 5805 u8 op_mod[0x10]; 5806 5807 u8 reserved_at_40[0x8]; 5808 u8 sqn[0x18]; 5809 5810 u8 reserved_at_60[0x20]; 5811 }; 5812 5813 struct mlx5_ifc_query_special_contexts_out_bits { 5814 u8 status[0x8]; 5815 u8 reserved_at_8[0x18]; 5816 5817 u8 syndrome[0x20]; 5818 5819 u8 dump_fill_mkey[0x20]; 5820 5821 u8 resd_lkey[0x20]; 5822 5823 u8 null_mkey[0x20]; 5824 5825 u8 terminate_scatter_list_mkey[0x20]; 5826 5827 u8 repeated_mkey[0x20]; 5828 5829 u8 reserved_at_a0[0x20]; 5830 }; 5831 5832 struct mlx5_ifc_query_special_contexts_in_bits { 5833 u8 opcode[0x10]; 5834 u8 reserved_at_10[0x10]; 5835 5836 u8 reserved_at_20[0x10]; 5837 u8 op_mod[0x10]; 5838 5839 u8 reserved_at_40[0x40]; 5840 }; 5841 5842 struct mlx5_ifc_query_scheduling_element_out_bits { 5843 u8 opcode[0x10]; 5844 u8 reserved_at_10[0x10]; 5845 5846 u8 reserved_at_20[0x10]; 5847 u8 op_mod[0x10]; 5848 5849 u8 reserved_at_40[0xc0]; 5850 5851 struct mlx5_ifc_scheduling_context_bits scheduling_context; 5852 5853 u8 reserved_at_300[0x100]; 5854 }; 5855 5856 enum { 5857 SCHEDULING_HIERARCHY_E_SWITCH = 0x2, 5858 SCHEDULING_HIERARCHY_NIC = 0x3, 5859 }; 5860 5861 struct mlx5_ifc_query_scheduling_element_in_bits { 5862 u8 opcode[0x10]; 5863 u8 reserved_at_10[0x10]; 5864 5865 u8 reserved_at_20[0x10]; 5866 u8 op_mod[0x10]; 5867 5868 u8 scheduling_hierarchy[0x8]; 5869 u8 reserved_at_48[0x18]; 5870 5871 u8 scheduling_element_id[0x20]; 5872 5873 u8 reserved_at_80[0x180]; 5874 }; 5875 5876 struct mlx5_ifc_query_rqt_out_bits { 5877 u8 status[0x8]; 5878 u8 reserved_at_8[0x18]; 5879 5880 u8 syndrome[0x20]; 5881 5882 u8 reserved_at_40[0xc0]; 5883 5884 struct mlx5_ifc_rqtc_bits rqt_context; 5885 }; 5886 5887 struct mlx5_ifc_query_rqt_in_bits { 5888 u8 opcode[0x10]; 5889 u8 reserved_at_10[0x10]; 5890 5891 u8 reserved_at_20[0x10]; 5892 u8 op_mod[0x10]; 5893 5894 u8 reserved_at_40[0x8]; 5895 u8 rqtn[0x18]; 5896 5897 u8 reserved_at_60[0x20]; 5898 }; 5899 5900 struct mlx5_ifc_query_rq_out_bits { 5901 u8 status[0x8]; 5902 u8 reserved_at_8[0x18]; 5903 5904 u8 syndrome[0x20]; 5905 5906 u8 reserved_at_40[0xc0]; 5907 5908 struct mlx5_ifc_rqc_bits rq_context; 5909 }; 5910 5911 struct mlx5_ifc_query_rq_in_bits { 5912 u8 opcode[0x10]; 5913 u8 reserved_at_10[0x10]; 5914 5915 u8 reserved_at_20[0x10]; 5916 u8 op_mod[0x10]; 5917 5918 u8 reserved_at_40[0x8]; 5919 u8 rqn[0x18]; 5920 5921 u8 reserved_at_60[0x20]; 5922 }; 5923 5924 struct mlx5_ifc_query_roce_address_out_bits { 5925 u8 status[0x8]; 5926 u8 reserved_at_8[0x18]; 5927 5928 u8 syndrome[0x20]; 5929 5930 u8 reserved_at_40[0x40]; 5931 5932 struct mlx5_ifc_roce_addr_layout_bits roce_address; 5933 }; 5934 5935 struct mlx5_ifc_query_roce_address_in_bits { 5936 u8 opcode[0x10]; 5937 u8 reserved_at_10[0x10]; 5938 5939 u8 reserved_at_20[0x10]; 5940 u8 op_mod[0x10]; 5941 5942 u8 roce_address_index[0x10]; 5943 u8 reserved_at_50[0xc]; 5944 u8 vhca_port_num[0x4]; 5945 5946 u8 reserved_at_60[0x20]; 5947 }; 5948 5949 struct mlx5_ifc_query_rmp_out_bits { 5950 u8 status[0x8]; 5951 u8 reserved_at_8[0x18]; 5952 5953 u8 syndrome[0x20]; 5954 5955 u8 reserved_at_40[0xc0]; 5956 5957 struct mlx5_ifc_rmpc_bits rmp_context; 5958 }; 5959 5960 struct mlx5_ifc_query_rmp_in_bits { 5961 u8 opcode[0x10]; 5962 u8 reserved_at_10[0x10]; 5963 5964 u8 reserved_at_20[0x10]; 5965 u8 op_mod[0x10]; 5966 5967 u8 reserved_at_40[0x8]; 5968 u8 rmpn[0x18]; 5969 5970 u8 reserved_at_60[0x20]; 5971 }; 5972 5973 struct mlx5_ifc_cqe_error_syndrome_bits { 5974 u8 hw_error_syndrome[0x8]; 5975 u8 hw_syndrome_type[0x4]; 5976 u8 reserved_at_c[0x4]; 5977 u8 vendor_error_syndrome[0x8]; 5978 u8 syndrome[0x8]; 5979 }; 5980 5981 struct mlx5_ifc_qp_context_extension_bits { 5982 u8 reserved_at_0[0x60]; 5983 5984 struct mlx5_ifc_cqe_error_syndrome_bits error_syndrome; 5985 5986 u8 reserved_at_80[0x580]; 5987 }; 5988 5989 struct mlx5_ifc_qpc_extension_and_pas_list_in_bits { 5990 struct mlx5_ifc_qp_context_extension_bits qpc_data_extension; 5991 5992 u8 pas[0][0x40]; 5993 }; 5994 5995 struct mlx5_ifc_qp_pas_list_in_bits { 5996 struct mlx5_ifc_cmd_pas_bits pas[0]; 5997 }; 5998 5999 union mlx5_ifc_qp_pas_or_qpc_ext_and_pas_bits { 6000 struct mlx5_ifc_qp_pas_list_in_bits qp_pas_list; 6001 struct mlx5_ifc_qpc_extension_and_pas_list_in_bits qpc_ext_and_pas_list; 6002 }; 6003 6004 struct mlx5_ifc_query_qp_out_bits { 6005 u8 status[0x8]; 6006 u8 reserved_at_8[0x18]; 6007 6008 u8 syndrome[0x20]; 6009 6010 u8 reserved_at_40[0x40]; 6011 6012 u8 opt_param_mask[0x20]; 6013 6014 u8 ece[0x20]; 6015 6016 struct mlx5_ifc_qpc_bits qpc; 6017 6018 u8 reserved_at_800[0x80]; 6019 6020 union mlx5_ifc_qp_pas_or_qpc_ext_and_pas_bits qp_pas_or_qpc_ext_and_pas; 6021 }; 6022 6023 struct mlx5_ifc_query_qp_in_bits { 6024 u8 opcode[0x10]; 6025 u8 reserved_at_10[0x10]; 6026 6027 u8 reserved_at_20[0x10]; 6028 u8 op_mod[0x10]; 6029 6030 u8 qpc_ext[0x1]; 6031 u8 reserved_at_41[0x7]; 6032 u8 qpn[0x18]; 6033 6034 u8 reserved_at_60[0x20]; 6035 }; 6036 6037 struct mlx5_ifc_query_q_counter_out_bits { 6038 u8 status[0x8]; 6039 u8 reserved_at_8[0x18]; 6040 6041 u8 syndrome[0x20]; 6042 6043 u8 reserved_at_40[0x40]; 6044 6045 u8 rx_write_requests[0x20]; 6046 6047 u8 reserved_at_a0[0x20]; 6048 6049 u8 rx_read_requests[0x20]; 6050 6051 u8 reserved_at_e0[0x20]; 6052 6053 u8 rx_atomic_requests[0x20]; 6054 6055 u8 reserved_at_120[0x20]; 6056 6057 u8 rx_dct_connect[0x20]; 6058 6059 u8 reserved_at_160[0x20]; 6060 6061 u8 out_of_buffer[0x20]; 6062 6063 u8 reserved_at_1a0[0x20]; 6064 6065 u8 out_of_sequence[0x20]; 6066 6067 u8 reserved_at_1e0[0x20]; 6068 6069 u8 duplicate_request[0x20]; 6070 6071 u8 reserved_at_220[0x20]; 6072 6073 u8 rnr_nak_retry_err[0x20]; 6074 6075 u8 reserved_at_260[0x20]; 6076 6077 u8 packet_seq_err[0x20]; 6078 6079 u8 reserved_at_2a0[0x20]; 6080 6081 u8 implied_nak_seq_err[0x20]; 6082 6083 u8 reserved_at_2e0[0x20]; 6084 6085 u8 local_ack_timeout_err[0x20]; 6086 6087 u8 reserved_at_320[0x60]; 6088 6089 u8 req_rnr_retries_exceeded[0x20]; 6090 6091 u8 reserved_at_3a0[0x20]; 6092 6093 u8 resp_local_length_error[0x20]; 6094 6095 u8 req_local_length_error[0x20]; 6096 6097 u8 resp_local_qp_error[0x20]; 6098 6099 u8 local_operation_error[0x20]; 6100 6101 u8 resp_local_protection[0x20]; 6102 6103 u8 req_local_protection[0x20]; 6104 6105 u8 resp_cqe_error[0x20]; 6106 6107 u8 req_cqe_error[0x20]; 6108 6109 u8 req_mw_binding[0x20]; 6110 6111 u8 req_bad_response[0x20]; 6112 6113 u8 req_remote_invalid_request[0x20]; 6114 6115 u8 resp_remote_invalid_request[0x20]; 6116 6117 u8 req_remote_access_errors[0x20]; 6118 6119 u8 resp_remote_access_errors[0x20]; 6120 6121 u8 req_remote_operation_errors[0x20]; 6122 6123 u8 req_transport_retries_exceeded[0x20]; 6124 6125 u8 cq_overflow[0x20]; 6126 6127 u8 resp_cqe_flush_error[0x20]; 6128 6129 u8 req_cqe_flush_error[0x20]; 6130 6131 u8 reserved_at_620[0x20]; 6132 6133 u8 roce_adp_retrans[0x20]; 6134 6135 u8 roce_adp_retrans_to[0x20]; 6136 6137 u8 roce_slow_restart[0x20]; 6138 6139 u8 roce_slow_restart_cnps[0x20]; 6140 6141 u8 roce_slow_restart_trans[0x20]; 6142 6143 u8 reserved_at_6e0[0x120]; 6144 }; 6145 6146 struct mlx5_ifc_query_q_counter_in_bits { 6147 u8 opcode[0x10]; 6148 u8 reserved_at_10[0x10]; 6149 6150 u8 reserved_at_20[0x10]; 6151 u8 op_mod[0x10]; 6152 6153 u8 other_vport[0x1]; 6154 u8 reserved_at_41[0xf]; 6155 u8 vport_number[0x10]; 6156 6157 u8 reserved_at_60[0x60]; 6158 6159 u8 clear[0x1]; 6160 u8 aggregate[0x1]; 6161 u8 reserved_at_c2[0x1e]; 6162 6163 u8 reserved_at_e0[0x18]; 6164 u8 counter_set_id[0x8]; 6165 }; 6166 6167 struct mlx5_ifc_query_pages_out_bits { 6168 u8 status[0x8]; 6169 u8 reserved_at_8[0x18]; 6170 6171 u8 syndrome[0x20]; 6172 6173 u8 embedded_cpu_function[0x1]; 6174 u8 reserved_at_41[0xf]; 6175 u8 function_id[0x10]; 6176 6177 u8 num_pages[0x20]; 6178 }; 6179 6180 enum { 6181 MLX5_QUERY_PAGES_IN_OP_MOD_BOOT_PAGES = 0x1, 6182 MLX5_QUERY_PAGES_IN_OP_MOD_INIT_PAGES = 0x2, 6183 MLX5_QUERY_PAGES_IN_OP_MOD_REGULAR_PAGES = 0x3, 6184 }; 6185 6186 struct mlx5_ifc_query_pages_in_bits { 6187 u8 opcode[0x10]; 6188 u8 reserved_at_10[0x10]; 6189 6190 u8 reserved_at_20[0x10]; 6191 u8 op_mod[0x10]; 6192 6193 u8 embedded_cpu_function[0x1]; 6194 u8 reserved_at_41[0xf]; 6195 u8 function_id[0x10]; 6196 6197 u8 reserved_at_60[0x20]; 6198 }; 6199 6200 struct mlx5_ifc_query_nic_vport_context_out_bits { 6201 u8 status[0x8]; 6202 u8 reserved_at_8[0x18]; 6203 6204 u8 syndrome[0x20]; 6205 6206 u8 reserved_at_40[0x40]; 6207 6208 struct mlx5_ifc_nic_vport_context_bits nic_vport_context; 6209 }; 6210 6211 struct mlx5_ifc_query_nic_vport_context_in_bits { 6212 u8 opcode[0x10]; 6213 u8 reserved_at_10[0x10]; 6214 6215 u8 reserved_at_20[0x10]; 6216 u8 op_mod[0x10]; 6217 6218 u8 other_vport[0x1]; 6219 u8 reserved_at_41[0xf]; 6220 u8 vport_number[0x10]; 6221 6222 u8 reserved_at_60[0x5]; 6223 u8 allowed_list_type[0x3]; 6224 u8 reserved_at_68[0x18]; 6225 }; 6226 6227 struct mlx5_ifc_query_mkey_out_bits { 6228 u8 status[0x8]; 6229 u8 reserved_at_8[0x18]; 6230 6231 u8 syndrome[0x20]; 6232 6233 u8 reserved_at_40[0x40]; 6234 6235 struct mlx5_ifc_mkc_bits memory_key_mkey_entry; 6236 6237 u8 reserved_at_280[0x600]; 6238 6239 u8 bsf0_klm0_pas_mtt0_1[16][0x8]; 6240 6241 u8 bsf1_klm1_pas_mtt2_3[16][0x8]; 6242 }; 6243 6244 struct mlx5_ifc_query_mkey_in_bits { 6245 u8 opcode[0x10]; 6246 u8 reserved_at_10[0x10]; 6247 6248 u8 reserved_at_20[0x10]; 6249 u8 op_mod[0x10]; 6250 6251 u8 reserved_at_40[0x8]; 6252 u8 mkey_index[0x18]; 6253 6254 u8 pg_access[0x1]; 6255 u8 reserved_at_61[0x1f]; 6256 }; 6257 6258 struct mlx5_ifc_query_mad_demux_out_bits { 6259 u8 status[0x8]; 6260 u8 reserved_at_8[0x18]; 6261 6262 u8 syndrome[0x20]; 6263 6264 u8 reserved_at_40[0x40]; 6265 6266 u8 mad_dumux_parameters_block[0x20]; 6267 }; 6268 6269 struct mlx5_ifc_query_mad_demux_in_bits { 6270 u8 opcode[0x10]; 6271 u8 reserved_at_10[0x10]; 6272 6273 u8 reserved_at_20[0x10]; 6274 u8 op_mod[0x10]; 6275 6276 u8 reserved_at_40[0x40]; 6277 }; 6278 6279 struct mlx5_ifc_query_l2_table_entry_out_bits { 6280 u8 status[0x8]; 6281 u8 reserved_at_8[0x18]; 6282 6283 u8 syndrome[0x20]; 6284 6285 u8 reserved_at_40[0xa0]; 6286 6287 u8 reserved_at_e0[0x11]; 6288 u8 silent_mode[0x1]; 6289 u8 reserved_at_f2[0x1]; 6290 u8 vlan_valid[0x1]; 6291 u8 vlan[0xc]; 6292 6293 struct mlx5_ifc_mac_address_layout_bits mac_address; 6294 6295 u8 reserved_at_140[0xc0]; 6296 }; 6297 6298 struct mlx5_ifc_query_l2_table_entry_in_bits { 6299 u8 opcode[0x10]; 6300 u8 reserved_at_10[0x10]; 6301 6302 u8 reserved_at_20[0x10]; 6303 u8 op_mod[0x10]; 6304 6305 u8 reserved_at_40[0x40]; 6306 6307 u8 silent_mode_query[0x1]; 6308 u8 reserved_at_81[0x1f]; 6309 6310 u8 reserved_at_a0[0x8]; 6311 u8 table_index[0x18]; 6312 6313 u8 reserved_at_c0[0x140]; 6314 }; 6315 6316 struct mlx5_ifc_query_issi_out_bits { 6317 u8 status[0x8]; 6318 u8 reserved_at_8[0x18]; 6319 6320 u8 syndrome[0x20]; 6321 6322 u8 reserved_at_40[0x10]; 6323 u8 current_issi[0x10]; 6324 6325 u8 reserved_at_60[0xa0]; 6326 6327 u8 reserved_at_100[76][0x8]; 6328 u8 supported_issi_dw0[0x20]; 6329 }; 6330 6331 struct mlx5_ifc_query_issi_in_bits { 6332 u8 opcode[0x10]; 6333 u8 reserved_at_10[0x10]; 6334 6335 u8 reserved_at_20[0x10]; 6336 u8 op_mod[0x10]; 6337 6338 u8 reserved_at_40[0x40]; 6339 }; 6340 6341 struct mlx5_ifc_set_driver_version_out_bits { 6342 u8 status[0x8]; 6343 u8 reserved_0[0x18]; 6344 6345 u8 syndrome[0x20]; 6346 u8 reserved_1[0x40]; 6347 }; 6348 6349 struct mlx5_ifc_set_driver_version_in_bits { 6350 u8 opcode[0x10]; 6351 u8 reserved_0[0x10]; 6352 6353 u8 reserved_1[0x10]; 6354 u8 op_mod[0x10]; 6355 6356 u8 reserved_2[0x40]; 6357 u8 driver_version[64][0x8]; 6358 }; 6359 6360 struct mlx5_ifc_query_hca_vport_pkey_out_bits { 6361 u8 status[0x8]; 6362 u8 reserved_at_8[0x18]; 6363 6364 u8 syndrome[0x20]; 6365 6366 u8 reserved_at_40[0x40]; 6367 6368 struct mlx5_ifc_pkey_bits pkey[]; 6369 }; 6370 6371 struct mlx5_ifc_query_hca_vport_pkey_in_bits { 6372 u8 opcode[0x10]; 6373 u8 reserved_at_10[0x10]; 6374 6375 u8 reserved_at_20[0x10]; 6376 u8 op_mod[0x10]; 6377 6378 u8 other_vport[0x1]; 6379 u8 reserved_at_41[0xb]; 6380 u8 port_num[0x4]; 6381 u8 vport_number[0x10]; 6382 6383 u8 reserved_at_60[0x10]; 6384 u8 pkey_index[0x10]; 6385 }; 6386 6387 enum { 6388 MLX5_HCA_VPORT_SEL_PORT_GUID = 1 << 0, 6389 MLX5_HCA_VPORT_SEL_NODE_GUID = 1 << 1, 6390 MLX5_HCA_VPORT_SEL_STATE_POLICY = 1 << 2, 6391 }; 6392 6393 struct mlx5_ifc_query_hca_vport_gid_out_bits { 6394 u8 status[0x8]; 6395 u8 reserved_at_8[0x18]; 6396 6397 u8 syndrome[0x20]; 6398 6399 u8 reserved_at_40[0x20]; 6400 6401 u8 gids_num[0x10]; 6402 u8 reserved_at_70[0x10]; 6403 6404 struct mlx5_ifc_array128_auto_bits gid[]; 6405 }; 6406 6407 struct mlx5_ifc_query_hca_vport_gid_in_bits { 6408 u8 opcode[0x10]; 6409 u8 reserved_at_10[0x10]; 6410 6411 u8 reserved_at_20[0x10]; 6412 u8 op_mod[0x10]; 6413 6414 u8 other_vport[0x1]; 6415 u8 reserved_at_41[0xb]; 6416 u8 port_num[0x4]; 6417 u8 vport_number[0x10]; 6418 6419 u8 reserved_at_60[0x10]; 6420 u8 gid_index[0x10]; 6421 }; 6422 6423 struct mlx5_ifc_query_hca_vport_context_out_bits { 6424 u8 status[0x8]; 6425 u8 reserved_at_8[0x18]; 6426 6427 u8 syndrome[0x20]; 6428 6429 u8 reserved_at_40[0x40]; 6430 6431 struct mlx5_ifc_hca_vport_context_bits hca_vport_context; 6432 }; 6433 6434 struct mlx5_ifc_query_hca_vport_context_in_bits { 6435 u8 opcode[0x10]; 6436 u8 reserved_at_10[0x10]; 6437 6438 u8 reserved_at_20[0x10]; 6439 u8 op_mod[0x10]; 6440 6441 u8 other_vport[0x1]; 6442 u8 reserved_at_41[0xb]; 6443 u8 port_num[0x4]; 6444 u8 vport_number[0x10]; 6445 6446 u8 reserved_at_60[0x20]; 6447 }; 6448 6449 struct mlx5_ifc_query_hca_cap_out_bits { 6450 u8 status[0x8]; 6451 u8 reserved_at_8[0x18]; 6452 6453 u8 syndrome[0x20]; 6454 6455 u8 reserved_at_40[0x40]; 6456 6457 union mlx5_ifc_hca_cap_union_bits capability; 6458 }; 6459 6460 struct mlx5_ifc_query_hca_cap_in_bits { 6461 u8 opcode[0x10]; 6462 u8 reserved_at_10[0x10]; 6463 6464 u8 reserved_at_20[0x10]; 6465 u8 op_mod[0x10]; 6466 6467 u8 other_function[0x1]; 6468 u8 ec_vf_function[0x1]; 6469 u8 reserved_at_42[0x1]; 6470 u8 function_id_type[0x1]; 6471 u8 reserved_at_44[0xc]; 6472 u8 function_id[0x10]; 6473 6474 u8 reserved_at_60[0x20]; 6475 }; 6476 6477 struct mlx5_ifc_other_hca_cap_bits { 6478 u8 roce[0x1]; 6479 u8 reserved_at_1[0x27f]; 6480 }; 6481 6482 struct mlx5_ifc_query_other_hca_cap_out_bits { 6483 u8 status[0x8]; 6484 u8 reserved_at_8[0x18]; 6485 6486 u8 syndrome[0x20]; 6487 6488 u8 reserved_at_40[0x40]; 6489 6490 struct mlx5_ifc_other_hca_cap_bits other_capability; 6491 }; 6492 6493 struct mlx5_ifc_query_other_hca_cap_in_bits { 6494 u8 opcode[0x10]; 6495 u8 reserved_at_10[0x10]; 6496 6497 u8 reserved_at_20[0x10]; 6498 u8 op_mod[0x10]; 6499 6500 u8 reserved_at_40[0x10]; 6501 u8 function_id[0x10]; 6502 6503 u8 reserved_at_60[0x20]; 6504 }; 6505 6506 struct mlx5_ifc_modify_other_hca_cap_out_bits { 6507 u8 status[0x8]; 6508 u8 reserved_at_8[0x18]; 6509 6510 u8 syndrome[0x20]; 6511 6512 u8 reserved_at_40[0x40]; 6513 }; 6514 6515 struct mlx5_ifc_modify_other_hca_cap_in_bits { 6516 u8 opcode[0x10]; 6517 u8 reserved_at_10[0x10]; 6518 6519 u8 reserved_at_20[0x10]; 6520 u8 op_mod[0x10]; 6521 6522 u8 reserved_at_40[0x10]; 6523 u8 function_id[0x10]; 6524 u8 field_select[0x20]; 6525 6526 struct mlx5_ifc_other_hca_cap_bits other_capability; 6527 }; 6528 6529 struct mlx5_ifc_sw_owner_icm_root_params_bits { 6530 u8 sw_owner_icm_root_1[0x40]; 6531 6532 u8 sw_owner_icm_root_0[0x40]; 6533 }; 6534 6535 struct mlx5_ifc_rtc_params_bits { 6536 u8 rtc_id_0[0x20]; 6537 6538 u8 rtc_id_1[0x20]; 6539 6540 u8 reserved_at_40[0x40]; 6541 }; 6542 6543 struct mlx5_ifc_flow_table_context_bits { 6544 u8 reformat_en[0x1]; 6545 u8 decap_en[0x1]; 6546 u8 sw_owner[0x1]; 6547 u8 termination_table[0x1]; 6548 u8 table_miss_action[0x4]; 6549 u8 level[0x8]; 6550 u8 rtc_valid[0x1]; 6551 u8 reserved_at_11[0x7]; 6552 u8 log_size[0x8]; 6553 6554 u8 reserved_at_20[0x8]; 6555 u8 table_miss_id[0x18]; 6556 6557 u8 reserved_at_40[0x8]; 6558 u8 lag_master_next_table_id[0x18]; 6559 6560 u8 reserved_at_60[0x60]; 6561 6562 union { 6563 struct mlx5_ifc_sw_owner_icm_root_params_bits sws; 6564 struct mlx5_ifc_rtc_params_bits hws; 6565 }; 6566 }; 6567 6568 struct mlx5_ifc_query_flow_table_out_bits { 6569 u8 status[0x8]; 6570 u8 reserved_at_8[0x18]; 6571 6572 u8 syndrome[0x20]; 6573 6574 u8 reserved_at_40[0x80]; 6575 6576 struct mlx5_ifc_flow_table_context_bits flow_table_context; 6577 }; 6578 6579 struct mlx5_ifc_query_flow_table_in_bits { 6580 u8 opcode[0x10]; 6581 u8 reserved_at_10[0x10]; 6582 6583 u8 reserved_at_20[0x10]; 6584 u8 op_mod[0x10]; 6585 6586 u8 reserved_at_40[0x40]; 6587 6588 u8 table_type[0x8]; 6589 u8 reserved_at_88[0x18]; 6590 6591 u8 reserved_at_a0[0x8]; 6592 u8 table_id[0x18]; 6593 6594 u8 reserved_at_c0[0x140]; 6595 }; 6596 6597 struct mlx5_ifc_query_fte_out_bits { 6598 u8 status[0x8]; 6599 u8 reserved_at_8[0x18]; 6600 6601 u8 syndrome[0x20]; 6602 6603 u8 reserved_at_40[0x1c0]; 6604 6605 struct mlx5_ifc_flow_context_bits flow_context; 6606 }; 6607 6608 struct mlx5_ifc_query_fte_in_bits { 6609 u8 opcode[0x10]; 6610 u8 reserved_at_10[0x10]; 6611 6612 u8 reserved_at_20[0x10]; 6613 u8 op_mod[0x10]; 6614 6615 u8 reserved_at_40[0x40]; 6616 6617 u8 table_type[0x8]; 6618 u8 reserved_at_88[0x18]; 6619 6620 u8 reserved_at_a0[0x8]; 6621 u8 table_id[0x18]; 6622 6623 u8 reserved_at_c0[0x40]; 6624 6625 u8 flow_index[0x20]; 6626 6627 u8 reserved_at_120[0xe0]; 6628 }; 6629 6630 struct mlx5_ifc_match_definer_format_0_bits { 6631 u8 reserved_at_0[0x100]; 6632 6633 u8 metadata_reg_c_0[0x20]; 6634 6635 u8 metadata_reg_c_1[0x20]; 6636 6637 u8 outer_dmac_47_16[0x20]; 6638 6639 u8 outer_dmac_15_0[0x10]; 6640 u8 outer_ethertype[0x10]; 6641 6642 u8 reserved_at_180[0x1]; 6643 u8 sx_sniffer[0x1]; 6644 u8 functional_lb[0x1]; 6645 u8 outer_ip_frag[0x1]; 6646 u8 outer_qp_type[0x2]; 6647 u8 outer_encap_type[0x2]; 6648 u8 port_number[0x2]; 6649 u8 outer_l3_type[0x2]; 6650 u8 outer_l4_type[0x2]; 6651 u8 outer_first_vlan_type[0x2]; 6652 u8 outer_first_vlan_prio[0x3]; 6653 u8 outer_first_vlan_cfi[0x1]; 6654 u8 outer_first_vlan_vid[0xc]; 6655 6656 u8 outer_l4_type_ext[0x4]; 6657 u8 reserved_at_1a4[0x2]; 6658 u8 outer_ipsec_layer[0x2]; 6659 u8 outer_l2_type[0x2]; 6660 u8 force_lb[0x1]; 6661 u8 outer_l2_ok[0x1]; 6662 u8 outer_l3_ok[0x1]; 6663 u8 outer_l4_ok[0x1]; 6664 u8 outer_second_vlan_type[0x2]; 6665 u8 outer_second_vlan_prio[0x3]; 6666 u8 outer_second_vlan_cfi[0x1]; 6667 u8 outer_second_vlan_vid[0xc]; 6668 6669 u8 outer_smac_47_16[0x20]; 6670 6671 u8 outer_smac_15_0[0x10]; 6672 u8 inner_ipv4_checksum_ok[0x1]; 6673 u8 inner_l4_checksum_ok[0x1]; 6674 u8 outer_ipv4_checksum_ok[0x1]; 6675 u8 outer_l4_checksum_ok[0x1]; 6676 u8 inner_l3_ok[0x1]; 6677 u8 inner_l4_ok[0x1]; 6678 u8 outer_l3_ok_duplicate[0x1]; 6679 u8 outer_l4_ok_duplicate[0x1]; 6680 u8 outer_tcp_cwr[0x1]; 6681 u8 outer_tcp_ece[0x1]; 6682 u8 outer_tcp_urg[0x1]; 6683 u8 outer_tcp_ack[0x1]; 6684 u8 outer_tcp_psh[0x1]; 6685 u8 outer_tcp_rst[0x1]; 6686 u8 outer_tcp_syn[0x1]; 6687 u8 outer_tcp_fin[0x1]; 6688 }; 6689 6690 struct mlx5_ifc_match_definer_format_22_bits { 6691 u8 reserved_at_0[0x100]; 6692 6693 u8 outer_ip_src_addr[0x20]; 6694 6695 u8 outer_ip_dest_addr[0x20]; 6696 6697 u8 outer_l4_sport[0x10]; 6698 u8 outer_l4_dport[0x10]; 6699 6700 u8 reserved_at_160[0x1]; 6701 u8 sx_sniffer[0x1]; 6702 u8 functional_lb[0x1]; 6703 u8 outer_ip_frag[0x1]; 6704 u8 outer_qp_type[0x2]; 6705 u8 outer_encap_type[0x2]; 6706 u8 port_number[0x2]; 6707 u8 outer_l3_type[0x2]; 6708 u8 outer_l4_type[0x2]; 6709 u8 outer_first_vlan_type[0x2]; 6710 u8 outer_first_vlan_prio[0x3]; 6711 u8 outer_first_vlan_cfi[0x1]; 6712 u8 outer_first_vlan_vid[0xc]; 6713 6714 u8 metadata_reg_c_0[0x20]; 6715 6716 u8 outer_dmac_47_16[0x20]; 6717 6718 u8 outer_smac_47_16[0x20]; 6719 6720 u8 outer_smac_15_0[0x10]; 6721 u8 outer_dmac_15_0[0x10]; 6722 }; 6723 6724 struct mlx5_ifc_match_definer_format_23_bits { 6725 u8 reserved_at_0[0x100]; 6726 6727 u8 inner_ip_src_addr[0x20]; 6728 6729 u8 inner_ip_dest_addr[0x20]; 6730 6731 u8 inner_l4_sport[0x10]; 6732 u8 inner_l4_dport[0x10]; 6733 6734 u8 reserved_at_160[0x1]; 6735 u8 sx_sniffer[0x1]; 6736 u8 functional_lb[0x1]; 6737 u8 inner_ip_frag[0x1]; 6738 u8 inner_qp_type[0x2]; 6739 u8 inner_encap_type[0x2]; 6740 u8 port_number[0x2]; 6741 u8 inner_l3_type[0x2]; 6742 u8 inner_l4_type[0x2]; 6743 u8 inner_first_vlan_type[0x2]; 6744 u8 inner_first_vlan_prio[0x3]; 6745 u8 inner_first_vlan_cfi[0x1]; 6746 u8 inner_first_vlan_vid[0xc]; 6747 6748 u8 tunnel_header_0[0x20]; 6749 6750 u8 inner_dmac_47_16[0x20]; 6751 6752 u8 inner_smac_47_16[0x20]; 6753 6754 u8 inner_smac_15_0[0x10]; 6755 u8 inner_dmac_15_0[0x10]; 6756 }; 6757 6758 struct mlx5_ifc_match_definer_format_29_bits { 6759 u8 reserved_at_0[0xc0]; 6760 6761 u8 outer_ip_dest_addr[0x80]; 6762 6763 u8 outer_ip_src_addr[0x80]; 6764 6765 u8 outer_l4_sport[0x10]; 6766 u8 outer_l4_dport[0x10]; 6767 6768 u8 reserved_at_1e0[0x20]; 6769 }; 6770 6771 struct mlx5_ifc_match_definer_format_30_bits { 6772 u8 reserved_at_0[0xa0]; 6773 6774 u8 outer_ip_dest_addr[0x80]; 6775 6776 u8 outer_ip_src_addr[0x80]; 6777 6778 u8 outer_dmac_47_16[0x20]; 6779 6780 u8 outer_smac_47_16[0x20]; 6781 6782 u8 outer_smac_15_0[0x10]; 6783 u8 outer_dmac_15_0[0x10]; 6784 }; 6785 6786 struct mlx5_ifc_match_definer_format_31_bits { 6787 u8 reserved_at_0[0xc0]; 6788 6789 u8 inner_ip_dest_addr[0x80]; 6790 6791 u8 inner_ip_src_addr[0x80]; 6792 6793 u8 inner_l4_sport[0x10]; 6794 u8 inner_l4_dport[0x10]; 6795 6796 u8 reserved_at_1e0[0x20]; 6797 }; 6798 6799 struct mlx5_ifc_match_definer_format_32_bits { 6800 u8 reserved_at_0[0xa0]; 6801 6802 u8 inner_ip_dest_addr[0x80]; 6803 6804 u8 inner_ip_src_addr[0x80]; 6805 6806 u8 inner_dmac_47_16[0x20]; 6807 6808 u8 inner_smac_47_16[0x20]; 6809 6810 u8 inner_smac_15_0[0x10]; 6811 u8 inner_dmac_15_0[0x10]; 6812 }; 6813 6814 enum { 6815 MLX5_IFC_DEFINER_FORMAT_ID_SELECT = 61, 6816 }; 6817 6818 #define MLX5_IFC_DEFINER_FORMAT_OFFSET_UNUSED 0x0 6819 #define MLX5_IFC_DEFINER_FORMAT_OFFSET_OUTER_ETH_PKT_LEN 0x48 6820 #define MLX5_IFC_DEFINER_DW_SELECTORS_NUM 9 6821 #define MLX5_IFC_DEFINER_BYTE_SELECTORS_NUM 8 6822 6823 struct mlx5_ifc_match_definer_match_mask_bits { 6824 u8 reserved_at_1c0[5][0x20]; 6825 u8 match_dw_8[0x20]; 6826 u8 match_dw_7[0x20]; 6827 u8 match_dw_6[0x20]; 6828 u8 match_dw_5[0x20]; 6829 u8 match_dw_4[0x20]; 6830 u8 match_dw_3[0x20]; 6831 u8 match_dw_2[0x20]; 6832 u8 match_dw_1[0x20]; 6833 u8 match_dw_0[0x20]; 6834 6835 u8 match_byte_7[0x8]; 6836 u8 match_byte_6[0x8]; 6837 u8 match_byte_5[0x8]; 6838 u8 match_byte_4[0x8]; 6839 6840 u8 match_byte_3[0x8]; 6841 u8 match_byte_2[0x8]; 6842 u8 match_byte_1[0x8]; 6843 u8 match_byte_0[0x8]; 6844 }; 6845 6846 struct mlx5_ifc_match_definer_bits { 6847 u8 modify_field_select[0x40]; 6848 6849 u8 reserved_at_40[0x40]; 6850 6851 u8 reserved_at_80[0x10]; 6852 u8 format_id[0x10]; 6853 6854 u8 reserved_at_a0[0x60]; 6855 6856 u8 format_select_dw3[0x8]; 6857 u8 format_select_dw2[0x8]; 6858 u8 format_select_dw1[0x8]; 6859 u8 format_select_dw0[0x8]; 6860 6861 u8 format_select_dw7[0x8]; 6862 u8 format_select_dw6[0x8]; 6863 u8 format_select_dw5[0x8]; 6864 u8 format_select_dw4[0x8]; 6865 6866 u8 reserved_at_100[0x18]; 6867 u8 format_select_dw8[0x8]; 6868 6869 u8 reserved_at_120[0x20]; 6870 6871 u8 format_select_byte3[0x8]; 6872 u8 format_select_byte2[0x8]; 6873 u8 format_select_byte1[0x8]; 6874 u8 format_select_byte0[0x8]; 6875 6876 u8 format_select_byte7[0x8]; 6877 u8 format_select_byte6[0x8]; 6878 u8 format_select_byte5[0x8]; 6879 u8 format_select_byte4[0x8]; 6880 6881 u8 reserved_at_180[0x40]; 6882 6883 union { 6884 struct { 6885 u8 match_mask[16][0x20]; 6886 }; 6887 struct mlx5_ifc_match_definer_match_mask_bits match_mask_format; 6888 }; 6889 }; 6890 6891 struct mlx5_ifc_general_obj_create_param_bits { 6892 u8 alias_object[0x1]; 6893 u8 reserved_at_1[0x2]; 6894 u8 log_obj_range[0x5]; 6895 u8 reserved_at_8[0x18]; 6896 }; 6897 6898 struct mlx5_ifc_general_obj_query_param_bits { 6899 u8 alias_object[0x1]; 6900 u8 obj_offset[0x1f]; 6901 }; 6902 6903 struct mlx5_ifc_general_obj_in_cmd_hdr_bits { 6904 u8 opcode[0x10]; 6905 u8 uid[0x10]; 6906 6907 u8 vhca_tunnel_id[0x10]; 6908 u8 obj_type[0x10]; 6909 6910 u8 obj_id[0x20]; 6911 6912 union { 6913 struct mlx5_ifc_general_obj_create_param_bits create; 6914 struct mlx5_ifc_general_obj_query_param_bits query; 6915 } op_param; 6916 }; 6917 6918 struct mlx5_ifc_general_obj_out_cmd_hdr_bits { 6919 u8 status[0x8]; 6920 u8 reserved_at_8[0x18]; 6921 6922 u8 syndrome[0x20]; 6923 6924 u8 obj_id[0x20]; 6925 6926 u8 reserved_at_60[0x20]; 6927 }; 6928 6929 struct mlx5_ifc_allow_other_vhca_access_in_bits { 6930 u8 opcode[0x10]; 6931 u8 uid[0x10]; 6932 u8 reserved_at_20[0x10]; 6933 u8 op_mod[0x10]; 6934 u8 reserved_at_40[0x50]; 6935 u8 object_type_to_be_accessed[0x10]; 6936 u8 object_id_to_be_accessed[0x20]; 6937 u8 reserved_at_c0[0x40]; 6938 union { 6939 u8 access_key_raw[0x100]; 6940 u8 access_key[8][0x20]; 6941 }; 6942 }; 6943 6944 struct mlx5_ifc_allow_other_vhca_access_out_bits { 6945 u8 status[0x8]; 6946 u8 reserved_at_8[0x18]; 6947 u8 syndrome[0x20]; 6948 u8 reserved_at_40[0x40]; 6949 }; 6950 6951 struct mlx5_ifc_modify_header_arg_bits { 6952 u8 reserved_at_0[0x80]; 6953 6954 u8 reserved_at_80[0x8]; 6955 u8 access_pd[0x18]; 6956 }; 6957 6958 struct mlx5_ifc_create_modify_header_arg_in_bits { 6959 struct mlx5_ifc_general_obj_in_cmd_hdr_bits hdr; 6960 struct mlx5_ifc_modify_header_arg_bits arg; 6961 }; 6962 6963 struct mlx5_ifc_create_match_definer_in_bits { 6964 struct mlx5_ifc_general_obj_in_cmd_hdr_bits general_obj_in_cmd_hdr; 6965 6966 struct mlx5_ifc_match_definer_bits obj_context; 6967 }; 6968 6969 struct mlx5_ifc_create_match_definer_out_bits { 6970 struct mlx5_ifc_general_obj_out_cmd_hdr_bits general_obj_out_cmd_hdr; 6971 }; 6972 6973 struct mlx5_ifc_alias_context_bits { 6974 u8 vhca_id_to_be_accessed[0x10]; 6975 u8 reserved_at_10[0xb]; 6976 u8 vhca_id_type[0x1]; 6977 u8 reserved_at_1c[0x1]; 6978 u8 status[0x3]; 6979 u8 object_id_to_be_accessed[0x20]; 6980 u8 reserved_at_40[0x40]; 6981 union { 6982 u8 access_key_raw[0x100]; 6983 u8 access_key[8][0x20]; 6984 }; 6985 u8 metadata[0x80]; 6986 }; 6987 6988 struct mlx5_ifc_create_alias_obj_in_bits { 6989 struct mlx5_ifc_general_obj_in_cmd_hdr_bits hdr; 6990 struct mlx5_ifc_alias_context_bits alias_ctx; 6991 }; 6992 6993 enum { 6994 MLX5_QUERY_FLOW_GROUP_OUT_MATCH_CRITERIA_ENABLE_OUTER_HEADERS = 0x0, 6995 MLX5_QUERY_FLOW_GROUP_OUT_MATCH_CRITERIA_ENABLE_MISC_PARAMETERS = 0x1, 6996 MLX5_QUERY_FLOW_GROUP_OUT_MATCH_CRITERIA_ENABLE_INNER_HEADERS = 0x2, 6997 MLX5_QUERY_FLOW_GROUP_IN_MATCH_CRITERIA_ENABLE_MISC_PARAMETERS_2 = 0x3, 6998 MLX5_QUERY_FLOW_GROUP_IN_MATCH_CRITERIA_ENABLE_MISC_PARAMETERS_3 = 0x4, 6999 MLX5_QUERY_FLOW_GROUP_IN_MATCH_CRITERIA_ENABLE_MISC_PARAMETERS_4 = 0x5, 7000 MLX5_QUERY_FLOW_GROUP_IN_MATCH_CRITERIA_ENABLE_MISC_PARAMETERS_5 = 0x6, 7001 MLX5_QUERY_FLOW_GROUP_IN_MATCH_CRITERIA_ENABLE_MISC_PARAMETERS_6 = 0x7, 7002 }; 7003 7004 struct mlx5_ifc_query_flow_group_out_bits { 7005 u8 status[0x8]; 7006 u8 reserved_at_8[0x18]; 7007 7008 u8 syndrome[0x20]; 7009 7010 u8 reserved_at_40[0xa0]; 7011 7012 u8 start_flow_index[0x20]; 7013 7014 u8 reserved_at_100[0x20]; 7015 7016 u8 end_flow_index[0x20]; 7017 7018 u8 reserved_at_140[0xa0]; 7019 7020 u8 reserved_at_1e0[0x18]; 7021 u8 match_criteria_enable[0x8]; 7022 7023 struct mlx5_ifc_fte_match_param_bits match_criteria; 7024 7025 u8 reserved_at_1200[0xe00]; 7026 }; 7027 7028 struct mlx5_ifc_query_flow_group_in_bits { 7029 u8 opcode[0x10]; 7030 u8 reserved_at_10[0x10]; 7031 7032 u8 reserved_at_20[0x10]; 7033 u8 op_mod[0x10]; 7034 7035 u8 reserved_at_40[0x40]; 7036 7037 u8 table_type[0x8]; 7038 u8 reserved_at_88[0x18]; 7039 7040 u8 reserved_at_a0[0x8]; 7041 u8 table_id[0x18]; 7042 7043 u8 group_id[0x20]; 7044 7045 u8 reserved_at_e0[0x120]; 7046 }; 7047 7048 struct mlx5_ifc_query_flow_counter_out_bits { 7049 u8 status[0x8]; 7050 u8 reserved_at_8[0x18]; 7051 7052 u8 syndrome[0x20]; 7053 7054 u8 reserved_at_40[0x40]; 7055 7056 struct mlx5_ifc_traffic_counter_bits flow_statistics[]; 7057 }; 7058 7059 struct mlx5_ifc_query_flow_counter_in_bits { 7060 u8 opcode[0x10]; 7061 u8 reserved_at_10[0x10]; 7062 7063 u8 reserved_at_20[0x10]; 7064 u8 op_mod[0x10]; 7065 7066 u8 reserved_at_40[0x80]; 7067 7068 u8 clear[0x1]; 7069 u8 reserved_at_c1[0xf]; 7070 u8 num_of_counters[0x10]; 7071 7072 u8 flow_counter_id[0x20]; 7073 }; 7074 7075 struct mlx5_ifc_query_esw_vport_context_out_bits { 7076 u8 status[0x8]; 7077 u8 reserved_at_8[0x18]; 7078 7079 u8 syndrome[0x20]; 7080 7081 u8 reserved_at_40[0x40]; 7082 7083 struct mlx5_ifc_esw_vport_context_bits esw_vport_context; 7084 }; 7085 7086 struct mlx5_ifc_query_esw_vport_context_in_bits { 7087 u8 opcode[0x10]; 7088 u8 reserved_at_10[0x10]; 7089 7090 u8 reserved_at_20[0x10]; 7091 u8 op_mod[0x10]; 7092 7093 u8 other_vport[0x1]; 7094 u8 reserved_at_41[0xf]; 7095 u8 vport_number[0x10]; 7096 7097 u8 reserved_at_60[0x20]; 7098 }; 7099 7100 struct mlx5_ifc_destroy_esw_vport_out_bits { 7101 u8 status[0x8]; 7102 u8 reserved_at_8[0x18]; 7103 7104 u8 syndrome[0x20]; 7105 7106 u8 reserved_at_40[0x20]; 7107 }; 7108 7109 struct mlx5_ifc_destroy_esw_vport_in_bits { 7110 u8 opcode[0x10]; 7111 u8 uid[0x10]; 7112 7113 u8 reserved_at_20[0x10]; 7114 u8 op_mod[0x10]; 7115 7116 u8 reserved_at_40[0x10]; 7117 u8 vport_num[0x10]; 7118 7119 u8 reserved_at_60[0x20]; 7120 }; 7121 7122 struct mlx5_ifc_modify_esw_vport_context_out_bits { 7123 u8 status[0x8]; 7124 u8 reserved_at_8[0x18]; 7125 7126 u8 syndrome[0x20]; 7127 7128 u8 reserved_at_40[0x40]; 7129 }; 7130 7131 struct mlx5_ifc_esw_vport_context_fields_select_bits { 7132 u8 reserved_at_0[0x1b]; 7133 u8 fdb_to_vport_reg_c_id[0x1]; 7134 u8 vport_cvlan_insert[0x1]; 7135 u8 vport_svlan_insert[0x1]; 7136 u8 vport_cvlan_strip[0x1]; 7137 u8 vport_svlan_strip[0x1]; 7138 }; 7139 7140 struct mlx5_ifc_modify_esw_vport_context_in_bits { 7141 u8 opcode[0x10]; 7142 u8 reserved_at_10[0x10]; 7143 7144 u8 reserved_at_20[0x10]; 7145 u8 op_mod[0x10]; 7146 7147 u8 other_vport[0x1]; 7148 u8 reserved_at_41[0xf]; 7149 u8 vport_number[0x10]; 7150 7151 struct mlx5_ifc_esw_vport_context_fields_select_bits field_select; 7152 7153 struct mlx5_ifc_esw_vport_context_bits esw_vport_context; 7154 }; 7155 7156 struct mlx5_ifc_query_eq_out_bits { 7157 u8 status[0x8]; 7158 u8 reserved_at_8[0x18]; 7159 7160 u8 syndrome[0x20]; 7161 7162 u8 reserved_at_40[0x40]; 7163 7164 struct mlx5_ifc_eqc_bits eq_context_entry; 7165 7166 u8 reserved_at_280[0x40]; 7167 7168 u8 event_bitmask[0x40]; 7169 7170 u8 reserved_at_300[0x580]; 7171 7172 u8 pas[][0x40]; 7173 }; 7174 7175 struct mlx5_ifc_query_eq_in_bits { 7176 u8 opcode[0x10]; 7177 u8 reserved_at_10[0x10]; 7178 7179 u8 reserved_at_20[0x10]; 7180 u8 op_mod[0x10]; 7181 7182 u8 reserved_at_40[0x18]; 7183 u8 eq_number[0x8]; 7184 7185 u8 reserved_at_60[0x20]; 7186 }; 7187 7188 struct mlx5_ifc_packet_reformat_context_in_bits { 7189 u8 reformat_type[0x8]; 7190 u8 reserved_at_8[0x4]; 7191 u8 reformat_param_0[0x4]; 7192 u8 reserved_at_10[0x6]; 7193 u8 reformat_data_size[0xa]; 7194 7195 u8 reformat_param_1[0x8]; 7196 u8 reserved_at_28[0x8]; 7197 u8 reformat_data[2][0x8]; 7198 7199 u8 more_reformat_data[][0x8]; 7200 }; 7201 7202 struct mlx5_ifc_query_packet_reformat_context_out_bits { 7203 u8 status[0x8]; 7204 u8 reserved_at_8[0x18]; 7205 7206 u8 syndrome[0x20]; 7207 7208 u8 reserved_at_40[0xa0]; 7209 7210 struct mlx5_ifc_packet_reformat_context_in_bits packet_reformat_context[]; 7211 }; 7212 7213 struct mlx5_ifc_query_packet_reformat_context_in_bits { 7214 u8 opcode[0x10]; 7215 u8 reserved_at_10[0x10]; 7216 7217 u8 reserved_at_20[0x10]; 7218 u8 op_mod[0x10]; 7219 7220 u8 packet_reformat_id[0x20]; 7221 7222 u8 reserved_at_60[0xa0]; 7223 }; 7224 7225 struct mlx5_ifc_alloc_packet_reformat_context_out_bits { 7226 u8 status[0x8]; 7227 u8 reserved_at_8[0x18]; 7228 7229 u8 syndrome[0x20]; 7230 7231 u8 packet_reformat_id[0x20]; 7232 7233 u8 reserved_at_60[0x20]; 7234 }; 7235 7236 enum { 7237 MLX5_REFORMAT_CONTEXT_ANCHOR_MAC_START = 0x1, 7238 MLX5_REFORMAT_CONTEXT_ANCHOR_VLAN_START = 0x2, 7239 MLX5_REFORMAT_CONTEXT_ANCHOR_IP_START = 0x7, 7240 MLX5_REFORMAT_CONTEXT_ANCHOR_TCP_UDP_START = 0x9, 7241 }; 7242 7243 enum mlx5_reformat_ctx_type { 7244 MLX5_REFORMAT_TYPE_L2_TO_VXLAN = 0x0, 7245 MLX5_REFORMAT_TYPE_L2_TO_NVGRE = 0x1, 7246 MLX5_REFORMAT_TYPE_L2_TO_L2_TUNNEL = 0x2, 7247 MLX5_REFORMAT_TYPE_L3_TUNNEL_TO_L2 = 0x3, 7248 MLX5_REFORMAT_TYPE_L2_TO_L3_TUNNEL = 0x4, 7249 MLX5_REFORMAT_TYPE_ADD_ESP_TRANSPORT_OVER_IPV4 = 0x5, 7250 MLX5_REFORMAT_TYPE_L2_TO_L3_ESP_TUNNEL = 0x6, 7251 MLX5_REFORMAT_TYPE_ADD_ESP_TRANSPORT_OVER_UDPV4 = 0x7, 7252 MLX5_REFORMAT_TYPE_DEL_ESP_TRANSPORT = 0x8, 7253 MLX5_REFORMAT_TYPE_L3_ESP_TUNNEL_TO_L2 = 0x9, 7254 MLX5_REFORMAT_TYPE_DEL_ESP_TRANSPORT_OVER_UDP = 0xa, 7255 MLX5_REFORMAT_TYPE_ADD_ESP_TRANSPORT_OVER_IPV6 = 0xb, 7256 MLX5_REFORMAT_TYPE_ADD_ESP_TRANSPORT_OVER_UDPV6 = 0xc, 7257 MLX5_REFORMAT_TYPE_ADD_PSP_TUNNEL = 0xd, 7258 MLX5_REFORMAT_TYPE_DEL_PSP_TUNNEL = 0xe, 7259 MLX5_REFORMAT_TYPE_INSERT_HDR = 0xf, 7260 MLX5_REFORMAT_TYPE_REMOVE_HDR = 0x10, 7261 MLX5_REFORMAT_TYPE_ADD_MACSEC = 0x11, 7262 MLX5_REFORMAT_TYPE_DEL_MACSEC = 0x12, 7263 MLX5_REFORMAT_TYPE_REMOVE_PSP_TRANSPORT = 0x16, 7264 }; 7265 7266 struct mlx5_ifc_alloc_packet_reformat_context_in_bits { 7267 u8 opcode[0x10]; 7268 u8 reserved_at_10[0x10]; 7269 7270 u8 reserved_at_20[0x10]; 7271 u8 op_mod[0x10]; 7272 7273 u8 reserved_at_40[0xa0]; 7274 7275 struct mlx5_ifc_packet_reformat_context_in_bits packet_reformat_context; 7276 }; 7277 7278 struct mlx5_ifc_dealloc_packet_reformat_context_out_bits { 7279 u8 status[0x8]; 7280 u8 reserved_at_8[0x18]; 7281 7282 u8 syndrome[0x20]; 7283 7284 u8 reserved_at_40[0x40]; 7285 }; 7286 7287 struct mlx5_ifc_dealloc_packet_reformat_context_in_bits { 7288 u8 opcode[0x10]; 7289 u8 reserved_at_10[0x10]; 7290 7291 u8 reserved_20[0x10]; 7292 u8 op_mod[0x10]; 7293 7294 u8 packet_reformat_id[0x20]; 7295 7296 u8 reserved_60[0x20]; 7297 }; 7298 7299 struct mlx5_ifc_set_action_in_bits { 7300 u8 action_type[0x4]; 7301 u8 field[0xc]; 7302 u8 reserved_at_10[0x3]; 7303 u8 offset[0x5]; 7304 u8 reserved_at_18[0x3]; 7305 u8 length[0x5]; 7306 7307 u8 data[0x20]; 7308 }; 7309 7310 struct mlx5_ifc_add_action_in_bits { 7311 u8 action_type[0x4]; 7312 u8 field[0xc]; 7313 u8 reserved_at_10[0x10]; 7314 7315 u8 data[0x20]; 7316 }; 7317 7318 struct mlx5_ifc_copy_action_in_bits { 7319 u8 action_type[0x4]; 7320 u8 src_field[0xc]; 7321 u8 reserved_at_10[0x3]; 7322 u8 src_offset[0x5]; 7323 u8 reserved_at_18[0x3]; 7324 u8 length[0x5]; 7325 7326 u8 reserved_at_20[0x4]; 7327 u8 dst_field[0xc]; 7328 u8 reserved_at_30[0x3]; 7329 u8 dst_offset[0x5]; 7330 u8 reserved_at_38[0x8]; 7331 }; 7332 7333 union mlx5_ifc_set_add_copy_action_in_auto_bits { 7334 struct mlx5_ifc_set_action_in_bits set_action_in; 7335 struct mlx5_ifc_add_action_in_bits add_action_in; 7336 struct mlx5_ifc_copy_action_in_bits copy_action_in; 7337 u8 reserved_at_0[0x40]; 7338 }; 7339 7340 enum { 7341 MLX5_ACTION_TYPE_SET = 0x1, 7342 MLX5_ACTION_TYPE_ADD = 0x2, 7343 MLX5_ACTION_TYPE_COPY = 0x3, 7344 }; 7345 7346 enum { 7347 MLX5_ACTION_IN_FIELD_OUT_SMAC_47_16 = 0x1, 7348 MLX5_ACTION_IN_FIELD_OUT_SMAC_15_0 = 0x2, 7349 MLX5_ACTION_IN_FIELD_OUT_ETHERTYPE = 0x3, 7350 MLX5_ACTION_IN_FIELD_OUT_DMAC_47_16 = 0x4, 7351 MLX5_ACTION_IN_FIELD_OUT_DMAC_15_0 = 0x5, 7352 MLX5_ACTION_IN_FIELD_OUT_IP_DSCP = 0x6, 7353 MLX5_ACTION_IN_FIELD_OUT_TCP_FLAGS = 0x7, 7354 MLX5_ACTION_IN_FIELD_OUT_TCP_SPORT = 0x8, 7355 MLX5_ACTION_IN_FIELD_OUT_TCP_DPORT = 0x9, 7356 MLX5_ACTION_IN_FIELD_OUT_IP_TTL = 0xa, 7357 MLX5_ACTION_IN_FIELD_OUT_UDP_SPORT = 0xb, 7358 MLX5_ACTION_IN_FIELD_OUT_UDP_DPORT = 0xc, 7359 MLX5_ACTION_IN_FIELD_OUT_SIPV6_127_96 = 0xd, 7360 MLX5_ACTION_IN_FIELD_OUT_SIPV6_95_64 = 0xe, 7361 MLX5_ACTION_IN_FIELD_OUT_SIPV6_63_32 = 0xf, 7362 MLX5_ACTION_IN_FIELD_OUT_SIPV6_31_0 = 0x10, 7363 MLX5_ACTION_IN_FIELD_OUT_DIPV6_127_96 = 0x11, 7364 MLX5_ACTION_IN_FIELD_OUT_DIPV6_95_64 = 0x12, 7365 MLX5_ACTION_IN_FIELD_OUT_DIPV6_63_32 = 0x13, 7366 MLX5_ACTION_IN_FIELD_OUT_DIPV6_31_0 = 0x14, 7367 MLX5_ACTION_IN_FIELD_OUT_SIPV4 = 0x15, 7368 MLX5_ACTION_IN_FIELD_OUT_DIPV4 = 0x16, 7369 MLX5_ACTION_IN_FIELD_OUT_FIRST_VID = 0x17, 7370 MLX5_ACTION_IN_FIELD_OUT_IPV6_HOPLIMIT = 0x47, 7371 MLX5_ACTION_IN_FIELD_METADATA_REG_A = 0x49, 7372 MLX5_ACTION_IN_FIELD_METADATA_REG_B = 0x50, 7373 MLX5_ACTION_IN_FIELD_METADATA_REG_C_0 = 0x51, 7374 MLX5_ACTION_IN_FIELD_METADATA_REG_C_1 = 0x52, 7375 MLX5_ACTION_IN_FIELD_METADATA_REG_C_2 = 0x53, 7376 MLX5_ACTION_IN_FIELD_METADATA_REG_C_3 = 0x54, 7377 MLX5_ACTION_IN_FIELD_METADATA_REG_C_4 = 0x55, 7378 MLX5_ACTION_IN_FIELD_METADATA_REG_C_5 = 0x56, 7379 MLX5_ACTION_IN_FIELD_METADATA_REG_C_6 = 0x57, 7380 MLX5_ACTION_IN_FIELD_METADATA_REG_C_7 = 0x58, 7381 MLX5_ACTION_IN_FIELD_OUT_TCP_SEQ_NUM = 0x59, 7382 MLX5_ACTION_IN_FIELD_OUT_TCP_ACK_NUM = 0x5B, 7383 MLX5_ACTION_IN_FIELD_IPSEC_SYNDROME = 0x5D, 7384 MLX5_ACTION_IN_FIELD_OUT_EMD_47_32 = 0x6F, 7385 MLX5_ACTION_IN_FIELD_OUT_EMD_31_0 = 0x70, 7386 MLX5_ACTION_IN_FIELD_PSP_SYNDROME = 0x71, 7387 MLX5_ACTION_IN_FIELD_PSP_HEADER_1 = 0x78, 7388 }; 7389 7390 struct mlx5_ifc_alloc_modify_header_context_out_bits { 7391 u8 status[0x8]; 7392 u8 reserved_at_8[0x18]; 7393 7394 u8 syndrome[0x20]; 7395 7396 u8 modify_header_id[0x20]; 7397 7398 u8 reserved_at_60[0x20]; 7399 }; 7400 7401 struct mlx5_ifc_alloc_modify_header_context_in_bits { 7402 u8 opcode[0x10]; 7403 u8 reserved_at_10[0x10]; 7404 7405 u8 reserved_at_20[0x10]; 7406 u8 op_mod[0x10]; 7407 7408 u8 reserved_at_40[0x20]; 7409 7410 u8 table_type[0x8]; 7411 u8 reserved_at_68[0x10]; 7412 u8 num_of_actions[0x8]; 7413 7414 union mlx5_ifc_set_add_copy_action_in_auto_bits actions[]; 7415 }; 7416 7417 struct mlx5_ifc_dealloc_modify_header_context_out_bits { 7418 u8 status[0x8]; 7419 u8 reserved_at_8[0x18]; 7420 7421 u8 syndrome[0x20]; 7422 7423 u8 reserved_at_40[0x40]; 7424 }; 7425 7426 struct mlx5_ifc_dealloc_modify_header_context_in_bits { 7427 u8 opcode[0x10]; 7428 u8 reserved_at_10[0x10]; 7429 7430 u8 reserved_at_20[0x10]; 7431 u8 op_mod[0x10]; 7432 7433 u8 modify_header_id[0x20]; 7434 7435 u8 reserved_at_60[0x20]; 7436 }; 7437 7438 struct mlx5_ifc_query_modify_header_context_in_bits { 7439 u8 opcode[0x10]; 7440 u8 uid[0x10]; 7441 7442 u8 reserved_at_20[0x10]; 7443 u8 op_mod[0x10]; 7444 7445 u8 modify_header_id[0x20]; 7446 7447 u8 reserved_at_60[0xa0]; 7448 }; 7449 7450 struct mlx5_ifc_query_dct_out_bits { 7451 u8 status[0x8]; 7452 u8 reserved_at_8[0x18]; 7453 7454 u8 syndrome[0x20]; 7455 7456 u8 reserved_at_40[0x40]; 7457 7458 struct mlx5_ifc_dctc_bits dct_context_entry; 7459 7460 u8 reserved_at_280[0x180]; 7461 }; 7462 7463 struct mlx5_ifc_query_dct_in_bits { 7464 u8 opcode[0x10]; 7465 u8 reserved_at_10[0x10]; 7466 7467 u8 reserved_at_20[0x10]; 7468 u8 op_mod[0x10]; 7469 7470 u8 reserved_at_40[0x8]; 7471 u8 dctn[0x18]; 7472 7473 u8 reserved_at_60[0x20]; 7474 }; 7475 7476 struct mlx5_ifc_query_cq_out_bits { 7477 u8 status[0x8]; 7478 u8 reserved_at_8[0x18]; 7479 7480 u8 syndrome[0x20]; 7481 7482 u8 reserved_at_40[0x40]; 7483 7484 struct mlx5_ifc_cqc_bits cq_context; 7485 7486 u8 reserved_at_280[0x600]; 7487 7488 u8 pas[][0x40]; 7489 }; 7490 7491 struct mlx5_ifc_query_cq_in_bits { 7492 u8 opcode[0x10]; 7493 u8 reserved_at_10[0x10]; 7494 7495 u8 reserved_at_20[0x10]; 7496 u8 op_mod[0x10]; 7497 7498 u8 reserved_at_40[0x8]; 7499 u8 cqn[0x18]; 7500 7501 u8 reserved_at_60[0x20]; 7502 }; 7503 7504 struct mlx5_ifc_query_cong_status_out_bits { 7505 u8 status[0x8]; 7506 u8 reserved_at_8[0x18]; 7507 7508 u8 syndrome[0x20]; 7509 7510 u8 reserved_at_40[0x20]; 7511 7512 u8 enable[0x1]; 7513 u8 tag_enable[0x1]; 7514 u8 reserved_at_62[0x1e]; 7515 }; 7516 7517 struct mlx5_ifc_query_cong_status_in_bits { 7518 u8 opcode[0x10]; 7519 u8 reserved_at_10[0x10]; 7520 7521 u8 reserved_at_20[0x10]; 7522 u8 op_mod[0x10]; 7523 7524 u8 reserved_at_40[0x18]; 7525 u8 priority[0x4]; 7526 u8 cong_protocol[0x4]; 7527 7528 u8 reserved_at_60[0x20]; 7529 }; 7530 7531 struct mlx5_ifc_query_cong_statistics_out_bits { 7532 u8 status[0x8]; 7533 u8 reserved_at_8[0x18]; 7534 7535 u8 syndrome[0x20]; 7536 7537 u8 reserved_at_40[0x40]; 7538 7539 u8 rp_cur_flows[0x20]; 7540 7541 u8 sum_flows[0x20]; 7542 7543 u8 rp_cnp_ignored_high[0x20]; 7544 7545 u8 rp_cnp_ignored_low[0x20]; 7546 7547 u8 rp_cnp_handled_high[0x20]; 7548 7549 u8 rp_cnp_handled_low[0x20]; 7550 7551 u8 reserved_at_140[0x100]; 7552 7553 u8 time_stamp_high[0x20]; 7554 7555 u8 time_stamp_low[0x20]; 7556 7557 u8 accumulators_period[0x20]; 7558 7559 u8 np_ecn_marked_roce_packets_high[0x20]; 7560 7561 u8 np_ecn_marked_roce_packets_low[0x20]; 7562 7563 u8 np_cnp_sent_high[0x20]; 7564 7565 u8 np_cnp_sent_low[0x20]; 7566 7567 u8 reserved_at_320[0x560]; 7568 }; 7569 7570 struct mlx5_ifc_query_cong_statistics_in_bits { 7571 u8 opcode[0x10]; 7572 u8 reserved_at_10[0x10]; 7573 7574 u8 reserved_at_20[0x10]; 7575 u8 op_mod[0x10]; 7576 7577 u8 clear[0x1]; 7578 u8 reserved_at_41[0x1f]; 7579 7580 u8 reserved_at_60[0x20]; 7581 }; 7582 7583 struct mlx5_ifc_query_cong_params_out_bits { 7584 u8 status[0x8]; 7585 u8 reserved_at_8[0x18]; 7586 7587 u8 syndrome[0x20]; 7588 7589 u8 reserved_at_40[0x40]; 7590 7591 union mlx5_ifc_cong_control_roce_ecn_auto_bits congestion_parameters; 7592 }; 7593 7594 struct mlx5_ifc_query_cong_params_in_bits { 7595 u8 opcode[0x10]; 7596 u8 reserved_at_10[0x10]; 7597 7598 u8 reserved_at_20[0x10]; 7599 u8 op_mod[0x10]; 7600 7601 u8 reserved_at_40[0x1c]; 7602 u8 cong_protocol[0x4]; 7603 7604 u8 reserved_at_60[0x20]; 7605 }; 7606 7607 struct mlx5_ifc_query_adapter_out_bits { 7608 u8 status[0x8]; 7609 u8 reserved_at_8[0x18]; 7610 7611 u8 syndrome[0x20]; 7612 7613 u8 reserved_at_40[0x40]; 7614 7615 struct mlx5_ifc_query_adapter_param_block_bits query_adapter_struct; 7616 }; 7617 7618 struct mlx5_ifc_query_adapter_in_bits { 7619 u8 opcode[0x10]; 7620 u8 reserved_at_10[0x10]; 7621 7622 u8 reserved_at_20[0x10]; 7623 u8 op_mod[0x10]; 7624 7625 u8 reserved_at_40[0x40]; 7626 }; 7627 7628 struct mlx5_ifc_function_vhca_rid_info_reg_bits { 7629 u8 host_number[0x8]; 7630 u8 host_pci_device_function[0x8]; 7631 u8 host_pci_bus[0x8]; 7632 u8 reserved_at_18[0x3]; 7633 u8 pci_bus_assigned[0x1]; 7634 u8 function_type[0x4]; 7635 7636 u8 parent_pci_device_function[0x8]; 7637 u8 parent_pci_bus[0x8]; 7638 u8 vhca_id[0x10]; 7639 7640 u8 reserved_at_40[0x10]; 7641 u8 function_id[0x10]; 7642 7643 u8 reserved_at_60[0x20]; 7644 }; 7645 7646 struct mlx5_ifc_delegated_function_vhca_rid_info_bits { 7647 struct mlx5_ifc_function_vhca_rid_info_reg_bits function_vhca_rid_info; 7648 7649 u8 reserved_at_80[0x18]; 7650 u8 manage_profile[0x8]; 7651 7652 u8 reserved_at_a0[0x60]; 7653 }; 7654 7655 struct mlx5_ifc_query_delegated_vhca_out_bits { 7656 u8 status[0x8]; 7657 u8 reserved_at_8[0x18]; 7658 7659 u8 syndrome[0x20]; 7660 7661 u8 reserved_at_40[0x20]; 7662 7663 u8 reserved_at_60[0x10]; 7664 u8 functions_count[0x10]; 7665 7666 u8 reserved_at_80[0x80]; 7667 7668 struct mlx5_ifc_delegated_function_vhca_rid_info_bits 7669 delegated_function_vhca_rid_info[]; 7670 }; 7671 7672 struct mlx5_ifc_query_delegated_vhca_in_bits { 7673 u8 opcode[0x10]; 7674 u8 uid[0x10]; 7675 7676 u8 reserved_at_20[0x10]; 7677 u8 op_mod[0x10]; 7678 7679 u8 reserved_at_40[0x40]; 7680 }; 7681 7682 struct mlx5_ifc_create_esw_vport_out_bits { 7683 u8 status[0x8]; 7684 u8 reserved_at_8[0x18]; 7685 7686 u8 syndrome[0x20]; 7687 7688 u8 reserved_at_40[0x20]; 7689 7690 u8 reserved_at_60[0x10]; 7691 u8 vport_num[0x10]; 7692 }; 7693 7694 struct mlx5_ifc_create_esw_vport_in_bits { 7695 u8 opcode[0x10]; 7696 u8 reserved_at_10[0x10]; 7697 7698 u8 reserved_at_20[0x10]; 7699 u8 op_mod[0x10]; 7700 7701 u8 reserved_at_40[0x10]; 7702 u8 managed_vhca_id[0x10]; 7703 7704 u8 reserved_at_60[0x20]; 7705 }; 7706 7707 struct mlx5_ifc_qp_2rst_out_bits { 7708 u8 status[0x8]; 7709 u8 reserved_at_8[0x18]; 7710 7711 u8 syndrome[0x20]; 7712 7713 u8 reserved_at_40[0x40]; 7714 }; 7715 7716 struct mlx5_ifc_qp_2rst_in_bits { 7717 u8 opcode[0x10]; 7718 u8 uid[0x10]; 7719 7720 u8 reserved_at_20[0x10]; 7721 u8 op_mod[0x10]; 7722 7723 u8 reserved_at_40[0x8]; 7724 u8 qpn[0x18]; 7725 7726 u8 reserved_at_60[0x20]; 7727 }; 7728 7729 struct mlx5_ifc_qp_2err_out_bits { 7730 u8 status[0x8]; 7731 u8 reserved_at_8[0x18]; 7732 7733 u8 syndrome[0x20]; 7734 7735 u8 reserved_at_40[0x40]; 7736 }; 7737 7738 struct mlx5_ifc_qp_2err_in_bits { 7739 u8 opcode[0x10]; 7740 u8 uid[0x10]; 7741 7742 u8 reserved_at_20[0x10]; 7743 u8 op_mod[0x10]; 7744 7745 u8 reserved_at_40[0x8]; 7746 u8 qpn[0x18]; 7747 7748 u8 reserved_at_60[0x20]; 7749 }; 7750 7751 struct mlx5_ifc_trans_page_fault_info_bits { 7752 u8 error[0x1]; 7753 u8 reserved_at_1[0x4]; 7754 u8 page_fault_type[0x3]; 7755 u8 wq_number[0x18]; 7756 7757 u8 reserved_at_20[0x8]; 7758 u8 fault_token[0x18]; 7759 }; 7760 7761 struct mlx5_ifc_mem_page_fault_info_bits { 7762 u8 error[0x1]; 7763 u8 reserved_at_1[0xf]; 7764 u8 fault_token_47_32[0x10]; 7765 7766 u8 fault_token_31_0[0x20]; 7767 }; 7768 7769 union mlx5_ifc_page_fault_resume_in_page_fault_info_auto_bits { 7770 struct mlx5_ifc_trans_page_fault_info_bits trans_page_fault_info; 7771 struct mlx5_ifc_mem_page_fault_info_bits mem_page_fault_info; 7772 u8 reserved_at_0[0x40]; 7773 }; 7774 7775 struct mlx5_ifc_page_fault_resume_out_bits { 7776 u8 status[0x8]; 7777 u8 reserved_at_8[0x18]; 7778 7779 u8 syndrome[0x20]; 7780 7781 u8 reserved_at_40[0x40]; 7782 }; 7783 7784 struct mlx5_ifc_page_fault_resume_in_bits { 7785 u8 opcode[0x10]; 7786 u8 reserved_at_10[0x10]; 7787 7788 u8 reserved_at_20[0x10]; 7789 u8 op_mod[0x10]; 7790 7791 union mlx5_ifc_page_fault_resume_in_page_fault_info_auto_bits 7792 page_fault_info; 7793 }; 7794 7795 struct mlx5_ifc_nop_out_bits { 7796 u8 status[0x8]; 7797 u8 reserved_at_8[0x18]; 7798 7799 u8 syndrome[0x20]; 7800 7801 u8 reserved_at_40[0x40]; 7802 }; 7803 7804 struct mlx5_ifc_nop_in_bits { 7805 u8 opcode[0x10]; 7806 u8 reserved_at_10[0x10]; 7807 7808 u8 reserved_at_20[0x10]; 7809 u8 op_mod[0x10]; 7810 7811 u8 reserved_at_40[0x40]; 7812 }; 7813 7814 struct mlx5_ifc_modify_vport_state_out_bits { 7815 u8 status[0x8]; 7816 u8 reserved_at_8[0x18]; 7817 7818 u8 syndrome[0x20]; 7819 7820 u8 reserved_at_40[0x40]; 7821 }; 7822 7823 struct mlx5_ifc_modify_vport_state_in_bits { 7824 u8 opcode[0x10]; 7825 u8 reserved_at_10[0x10]; 7826 7827 u8 reserved_at_20[0x10]; 7828 u8 op_mod[0x10]; 7829 7830 u8 other_vport[0x1]; 7831 u8 reserved_at_41[0xf]; 7832 u8 vport_number[0x10]; 7833 7834 u8 max_tx_speed[0x10]; 7835 u8 ingress_connect[0x1]; 7836 u8 egress_connect[0x1]; 7837 u8 ingress_connect_valid[0x1]; 7838 u8 egress_connect_valid[0x1]; 7839 u8 reserved_at_74[0x4]; 7840 u8 admin_state[0x4]; 7841 u8 reserved_at_7c[0x4]; 7842 }; 7843 7844 struct mlx5_ifc_modify_tis_out_bits { 7845 u8 status[0x8]; 7846 u8 reserved_at_8[0x18]; 7847 7848 u8 syndrome[0x20]; 7849 7850 u8 reserved_at_40[0x40]; 7851 }; 7852 7853 struct mlx5_ifc_modify_tis_bitmask_bits { 7854 u8 reserved_at_0[0x20]; 7855 7856 u8 reserved_at_20[0x1d]; 7857 u8 lag_tx_port_affinity[0x1]; 7858 u8 strict_lag_tx_port_affinity[0x1]; 7859 u8 prio[0x1]; 7860 }; 7861 7862 struct mlx5_ifc_modify_tis_in_bits { 7863 u8 opcode[0x10]; 7864 u8 uid[0x10]; 7865 7866 u8 reserved_at_20[0x10]; 7867 u8 op_mod[0x10]; 7868 7869 u8 reserved_at_40[0x8]; 7870 u8 tisn[0x18]; 7871 7872 u8 reserved_at_60[0x20]; 7873 7874 struct mlx5_ifc_modify_tis_bitmask_bits bitmask; 7875 7876 u8 reserved_at_c0[0x40]; 7877 7878 struct mlx5_ifc_tisc_bits ctx; 7879 }; 7880 7881 struct mlx5_ifc_modify_tir_bitmask_bits { 7882 u8 reserved_at_0[0x20]; 7883 7884 u8 reserved_at_20[0x1b]; 7885 u8 self_lb_en[0x1]; 7886 u8 reserved_at_3c[0x1]; 7887 u8 hash[0x1]; 7888 u8 reserved_at_3e[0x1]; 7889 u8 packet_merge[0x1]; 7890 }; 7891 7892 struct mlx5_ifc_modify_tir_out_bits { 7893 u8 status[0x8]; 7894 u8 reserved_at_8[0x18]; 7895 7896 u8 syndrome[0x20]; 7897 7898 u8 reserved_at_40[0x40]; 7899 }; 7900 7901 struct mlx5_ifc_modify_tir_in_bits { 7902 u8 opcode[0x10]; 7903 u8 uid[0x10]; 7904 7905 u8 reserved_at_20[0x10]; 7906 u8 op_mod[0x10]; 7907 7908 u8 reserved_at_40[0x8]; 7909 u8 tirn[0x18]; 7910 7911 u8 reserved_at_60[0x20]; 7912 7913 struct mlx5_ifc_modify_tir_bitmask_bits bitmask; 7914 7915 u8 reserved_at_c0[0x40]; 7916 7917 struct mlx5_ifc_tirc_bits ctx; 7918 }; 7919 7920 struct mlx5_ifc_modify_sq_out_bits { 7921 u8 status[0x8]; 7922 u8 reserved_at_8[0x18]; 7923 7924 u8 syndrome[0x20]; 7925 7926 u8 reserved_at_40[0x40]; 7927 }; 7928 7929 struct mlx5_ifc_modify_sq_in_bits { 7930 u8 opcode[0x10]; 7931 u8 uid[0x10]; 7932 7933 u8 reserved_at_20[0x10]; 7934 u8 op_mod[0x10]; 7935 7936 u8 sq_state[0x4]; 7937 u8 reserved_at_44[0x4]; 7938 u8 sqn[0x18]; 7939 7940 u8 reserved_at_60[0x20]; 7941 7942 u8 modify_bitmask[0x40]; 7943 7944 u8 reserved_at_c0[0x40]; 7945 7946 struct mlx5_ifc_sqc_bits ctx; 7947 }; 7948 7949 struct mlx5_ifc_modify_scheduling_element_out_bits { 7950 u8 status[0x8]; 7951 u8 reserved_at_8[0x18]; 7952 7953 u8 syndrome[0x20]; 7954 7955 u8 reserved_at_40[0x1c0]; 7956 }; 7957 7958 enum { 7959 MODIFY_SCHEDULING_ELEMENT_IN_MODIFY_BITMASK_BW_SHARE = 0x1, 7960 MODIFY_SCHEDULING_ELEMENT_IN_MODIFY_BITMASK_MAX_AVERAGE_BW = 0x2, 7961 }; 7962 7963 struct mlx5_ifc_modify_scheduling_element_in_bits { 7964 u8 opcode[0x10]; 7965 u8 reserved_at_10[0x10]; 7966 7967 u8 reserved_at_20[0x10]; 7968 u8 op_mod[0x10]; 7969 7970 u8 scheduling_hierarchy[0x8]; 7971 u8 reserved_at_48[0x18]; 7972 7973 u8 scheduling_element_id[0x20]; 7974 7975 u8 reserved_at_80[0x20]; 7976 7977 u8 modify_bitmask[0x20]; 7978 7979 u8 reserved_at_c0[0x40]; 7980 7981 struct mlx5_ifc_scheduling_context_bits scheduling_context; 7982 7983 u8 reserved_at_300[0x100]; 7984 }; 7985 7986 struct mlx5_ifc_modify_rqt_out_bits { 7987 u8 status[0x8]; 7988 u8 reserved_at_8[0x18]; 7989 7990 u8 syndrome[0x20]; 7991 7992 u8 reserved_at_40[0x40]; 7993 }; 7994 7995 struct mlx5_ifc_rqt_bitmask_bits { 7996 u8 reserved_at_0[0x20]; 7997 7998 u8 reserved_at_20[0x1f]; 7999 u8 rqn_list[0x1]; 8000 }; 8001 8002 struct mlx5_ifc_modify_rqt_in_bits { 8003 u8 opcode[0x10]; 8004 u8 uid[0x10]; 8005 8006 u8 reserved_at_20[0x10]; 8007 u8 op_mod[0x10]; 8008 8009 u8 reserved_at_40[0x8]; 8010 u8 rqtn[0x18]; 8011 8012 u8 reserved_at_60[0x20]; 8013 8014 struct mlx5_ifc_rqt_bitmask_bits bitmask; 8015 8016 u8 reserved_at_c0[0x40]; 8017 8018 struct mlx5_ifc_rqtc_bits ctx; 8019 }; 8020 8021 struct mlx5_ifc_modify_rq_out_bits { 8022 u8 status[0x8]; 8023 u8 reserved_at_8[0x18]; 8024 8025 u8 syndrome[0x20]; 8026 8027 u8 reserved_at_40[0x40]; 8028 }; 8029 8030 enum { 8031 MLX5_MODIFY_RQ_IN_MODIFY_BITMASK_VSD = 1ULL << 1, 8032 MLX5_MODIFY_RQ_IN_MODIFY_BITMASK_SCATTER_FCS = 1ULL << 2, 8033 MLX5_MODIFY_RQ_IN_MODIFY_BITMASK_RQ_COUNTER_SET_ID = 1ULL << 3, 8034 }; 8035 8036 struct mlx5_ifc_modify_rq_in_bits { 8037 u8 opcode[0x10]; 8038 u8 uid[0x10]; 8039 8040 u8 reserved_at_20[0x10]; 8041 u8 op_mod[0x10]; 8042 8043 u8 rq_state[0x4]; 8044 u8 reserved_at_44[0x4]; 8045 u8 rqn[0x18]; 8046 8047 u8 reserved_at_60[0x20]; 8048 8049 u8 modify_bitmask[0x40]; 8050 8051 u8 reserved_at_c0[0x40]; 8052 8053 struct mlx5_ifc_rqc_bits ctx; 8054 }; 8055 8056 struct mlx5_ifc_modify_rmp_out_bits { 8057 u8 status[0x8]; 8058 u8 reserved_at_8[0x18]; 8059 8060 u8 syndrome[0x20]; 8061 8062 u8 reserved_at_40[0x40]; 8063 }; 8064 8065 struct mlx5_ifc_rmp_bitmask_bits { 8066 u8 reserved_at_0[0x20]; 8067 8068 u8 reserved_at_20[0x1f]; 8069 u8 lwm[0x1]; 8070 }; 8071 8072 struct mlx5_ifc_modify_rmp_in_bits { 8073 u8 opcode[0x10]; 8074 u8 uid[0x10]; 8075 8076 u8 reserved_at_20[0x10]; 8077 u8 op_mod[0x10]; 8078 8079 u8 rmp_state[0x4]; 8080 u8 reserved_at_44[0x4]; 8081 u8 rmpn[0x18]; 8082 8083 u8 reserved_at_60[0x20]; 8084 8085 struct mlx5_ifc_rmp_bitmask_bits bitmask; 8086 8087 u8 reserved_at_c0[0x40]; 8088 8089 struct mlx5_ifc_rmpc_bits ctx; 8090 }; 8091 8092 struct mlx5_ifc_modify_nic_vport_context_out_bits { 8093 u8 status[0x8]; 8094 u8 reserved_at_8[0x18]; 8095 8096 u8 syndrome[0x20]; 8097 8098 u8 reserved_at_40[0x40]; 8099 }; 8100 8101 struct mlx5_ifc_modify_nic_vport_field_select_bits { 8102 u8 reserved_at_0[0x12]; 8103 u8 affiliation[0x1]; 8104 u8 reserved_at_13[0x1]; 8105 u8 disable_uc_local_lb[0x1]; 8106 u8 disable_mc_local_lb[0x1]; 8107 u8 node_guid[0x1]; 8108 u8 port_guid[0x1]; 8109 u8 min_inline[0x1]; 8110 u8 mtu[0x1]; 8111 u8 change_event[0x1]; 8112 u8 promisc[0x1]; 8113 u8 permanent_address[0x1]; 8114 u8 addresses_list[0x1]; 8115 u8 roce_en[0x1]; 8116 u8 reserved_at_1f[0x1]; 8117 }; 8118 8119 struct mlx5_ifc_modify_nic_vport_context_in_bits { 8120 u8 opcode[0x10]; 8121 u8 reserved_at_10[0x10]; 8122 8123 u8 reserved_at_20[0x10]; 8124 u8 op_mod[0x10]; 8125 8126 u8 other_vport[0x1]; 8127 u8 reserved_at_41[0xf]; 8128 u8 vport_number[0x10]; 8129 8130 struct mlx5_ifc_modify_nic_vport_field_select_bits field_select; 8131 8132 u8 reserved_at_80[0x780]; 8133 8134 struct mlx5_ifc_nic_vport_context_bits nic_vport_context; 8135 }; 8136 8137 struct mlx5_ifc_modify_hca_vport_context_out_bits { 8138 u8 status[0x8]; 8139 u8 reserved_at_8[0x18]; 8140 8141 u8 syndrome[0x20]; 8142 8143 u8 reserved_at_40[0x40]; 8144 }; 8145 8146 struct mlx5_ifc_modify_hca_vport_context_in_bits { 8147 u8 opcode[0x10]; 8148 u8 reserved_at_10[0x10]; 8149 8150 u8 reserved_at_20[0x10]; 8151 u8 op_mod[0x10]; 8152 8153 u8 other_vport[0x1]; 8154 u8 reserved_at_41[0xb]; 8155 u8 port_num[0x4]; 8156 u8 vport_number[0x10]; 8157 8158 u8 reserved_at_60[0x20]; 8159 8160 struct mlx5_ifc_hca_vport_context_bits hca_vport_context; 8161 }; 8162 8163 struct mlx5_ifc_modify_cq_out_bits { 8164 u8 status[0x8]; 8165 u8 reserved_at_8[0x18]; 8166 8167 u8 syndrome[0x20]; 8168 8169 u8 reserved_at_40[0x40]; 8170 }; 8171 8172 enum { 8173 MLX5_MODIFY_CQ_IN_OP_MOD_MODIFY_CQ = 0x0, 8174 MLX5_MODIFY_CQ_IN_OP_MOD_RESIZE_CQ = 0x1, 8175 }; 8176 8177 struct mlx5_ifc_modify_cq_in_bits { 8178 u8 opcode[0x10]; 8179 u8 uid[0x10]; 8180 8181 u8 reserved_at_20[0x10]; 8182 u8 op_mod[0x10]; 8183 8184 u8 reserved_at_40[0x8]; 8185 u8 cqn[0x18]; 8186 8187 union mlx5_ifc_modify_field_select_resize_field_select_auto_bits modify_field_select_resize_field_select; 8188 8189 struct mlx5_ifc_cqc_bits cq_context; 8190 8191 u8 reserved_at_280[0x60]; 8192 8193 u8 cq_umem_valid[0x1]; 8194 u8 reserved_at_2e1[0x1f]; 8195 8196 u8 reserved_at_300[0x580]; 8197 8198 u8 pas[][0x40]; 8199 }; 8200 8201 struct mlx5_ifc_modify_cong_status_out_bits { 8202 u8 status[0x8]; 8203 u8 reserved_at_8[0x18]; 8204 8205 u8 syndrome[0x20]; 8206 8207 u8 reserved_at_40[0x40]; 8208 }; 8209 8210 struct mlx5_ifc_modify_cong_status_in_bits { 8211 u8 opcode[0x10]; 8212 u8 reserved_at_10[0x10]; 8213 8214 u8 reserved_at_20[0x10]; 8215 u8 op_mod[0x10]; 8216 8217 u8 reserved_at_40[0x18]; 8218 u8 priority[0x4]; 8219 u8 cong_protocol[0x4]; 8220 8221 u8 enable[0x1]; 8222 u8 tag_enable[0x1]; 8223 u8 reserved_at_62[0x1e]; 8224 }; 8225 8226 struct mlx5_ifc_modify_cong_params_out_bits { 8227 u8 status[0x8]; 8228 u8 reserved_at_8[0x18]; 8229 8230 u8 syndrome[0x20]; 8231 8232 u8 reserved_at_40[0x40]; 8233 }; 8234 8235 struct mlx5_ifc_modify_cong_params_in_bits { 8236 u8 opcode[0x10]; 8237 u8 reserved_at_10[0x10]; 8238 8239 u8 reserved_at_20[0x10]; 8240 u8 op_mod[0x10]; 8241 8242 u8 reserved_at_40[0x1c]; 8243 u8 cong_protocol[0x4]; 8244 8245 union mlx5_ifc_field_select_802_1_r_roce_auto_bits field_select; 8246 8247 u8 reserved_at_80[0x80]; 8248 8249 union mlx5_ifc_cong_control_roce_ecn_auto_bits congestion_parameters; 8250 }; 8251 8252 struct mlx5_ifc_manage_pages_out_bits { 8253 u8 status[0x8]; 8254 u8 reserved_at_8[0x18]; 8255 8256 u8 syndrome[0x20]; 8257 8258 u8 output_num_entries[0x20]; 8259 8260 u8 reserved_at_60[0x20]; 8261 8262 u8 pas[][0x40]; 8263 }; 8264 8265 enum { 8266 MLX5_MANAGE_PAGES_IN_OP_MOD_ALLOCATION_FAIL = 0x0, 8267 MLX5_MANAGE_PAGES_IN_OP_MOD_ALLOCATION_SUCCESS = 0x1, 8268 MLX5_MANAGE_PAGES_IN_OP_MOD_HCA_RETURN_PAGES = 0x2, 8269 }; 8270 8271 struct mlx5_ifc_manage_pages_in_bits { 8272 u8 opcode[0x10]; 8273 u8 reserved_at_10[0x10]; 8274 8275 u8 reserved_at_20[0x10]; 8276 u8 op_mod[0x10]; 8277 8278 u8 embedded_cpu_function[0x1]; 8279 u8 reserved_at_41[0xf]; 8280 u8 function_id[0x10]; 8281 8282 u8 input_num_entries[0x20]; 8283 8284 u8 pas[][0x40]; 8285 }; 8286 8287 struct mlx5_ifc_mad_ifc_out_bits { 8288 u8 status[0x8]; 8289 u8 reserved_at_8[0x18]; 8290 8291 u8 syndrome[0x20]; 8292 8293 u8 reserved_at_40[0x40]; 8294 8295 u8 response_mad_packet[256][0x8]; 8296 }; 8297 8298 struct mlx5_ifc_mad_ifc_in_bits { 8299 u8 opcode[0x10]; 8300 u8 reserved_at_10[0x10]; 8301 8302 u8 reserved_at_20[0x10]; 8303 u8 op_mod[0x10]; 8304 8305 u8 remote_lid[0x10]; 8306 u8 plane_index[0x8]; 8307 u8 port[0x8]; 8308 8309 u8 reserved_at_60[0x20]; 8310 8311 u8 mad[256][0x8]; 8312 }; 8313 8314 struct mlx5_ifc_init_hca_out_bits { 8315 u8 status[0x8]; 8316 u8 reserved_at_8[0x18]; 8317 8318 u8 syndrome[0x20]; 8319 8320 u8 reserved_at_40[0x40]; 8321 }; 8322 8323 struct mlx5_ifc_init_hca_in_bits { 8324 u8 opcode[0x10]; 8325 u8 reserved_at_10[0x10]; 8326 8327 u8 reserved_at_20[0x10]; 8328 u8 op_mod[0x10]; 8329 8330 u8 reserved_at_40[0x20]; 8331 8332 u8 reserved_at_60[0x2]; 8333 u8 sw_vhca_id[0xe]; 8334 u8 reserved_at_70[0x10]; 8335 8336 u8 sw_owner_id[4][0x20]; 8337 }; 8338 8339 struct mlx5_ifc_init2rtr_qp_out_bits { 8340 u8 status[0x8]; 8341 u8 reserved_at_8[0x18]; 8342 8343 u8 syndrome[0x20]; 8344 8345 u8 reserved_at_40[0x20]; 8346 u8 ece[0x20]; 8347 }; 8348 8349 struct mlx5_ifc_init2rtr_qp_in_bits { 8350 u8 opcode[0x10]; 8351 u8 uid[0x10]; 8352 8353 u8 reserved_at_20[0x10]; 8354 u8 op_mod[0x10]; 8355 8356 u8 reserved_at_40[0x8]; 8357 u8 qpn[0x18]; 8358 8359 u8 reserved_at_60[0x20]; 8360 8361 u8 opt_param_mask[0x20]; 8362 8363 u8 ece[0x20]; 8364 8365 struct mlx5_ifc_qpc_bits qpc; 8366 8367 u8 reserved_at_800[0x80]; 8368 }; 8369 8370 struct mlx5_ifc_init2init_qp_out_bits { 8371 u8 status[0x8]; 8372 u8 reserved_at_8[0x18]; 8373 8374 u8 syndrome[0x20]; 8375 8376 u8 reserved_at_40[0x20]; 8377 u8 ece[0x20]; 8378 }; 8379 8380 struct mlx5_ifc_init2init_qp_in_bits { 8381 u8 opcode[0x10]; 8382 u8 uid[0x10]; 8383 8384 u8 reserved_at_20[0x10]; 8385 u8 op_mod[0x10]; 8386 8387 u8 reserved_at_40[0x8]; 8388 u8 qpn[0x18]; 8389 8390 u8 reserved_at_60[0x20]; 8391 8392 u8 opt_param_mask[0x20]; 8393 8394 u8 ece[0x20]; 8395 8396 struct mlx5_ifc_qpc_bits qpc; 8397 8398 u8 reserved_at_800[0x80]; 8399 }; 8400 8401 struct mlx5_ifc_get_dropped_packet_log_out_bits { 8402 u8 status[0x8]; 8403 u8 reserved_at_8[0x18]; 8404 8405 u8 syndrome[0x20]; 8406 8407 u8 reserved_at_40[0x40]; 8408 8409 u8 packet_headers_log[128][0x8]; 8410 8411 u8 packet_syndrome[64][0x8]; 8412 }; 8413 8414 struct mlx5_ifc_get_dropped_packet_log_in_bits { 8415 u8 opcode[0x10]; 8416 u8 reserved_at_10[0x10]; 8417 8418 u8 reserved_at_20[0x10]; 8419 u8 op_mod[0x10]; 8420 8421 u8 reserved_at_40[0x40]; 8422 }; 8423 8424 struct mlx5_ifc_gen_eqe_in_bits { 8425 u8 opcode[0x10]; 8426 u8 reserved_at_10[0x10]; 8427 8428 u8 reserved_at_20[0x10]; 8429 u8 op_mod[0x10]; 8430 8431 u8 reserved_at_40[0x18]; 8432 u8 eq_number[0x8]; 8433 8434 u8 reserved_at_60[0x20]; 8435 8436 u8 eqe[64][0x8]; 8437 }; 8438 8439 struct mlx5_ifc_gen_eq_out_bits { 8440 u8 status[0x8]; 8441 u8 reserved_at_8[0x18]; 8442 8443 u8 syndrome[0x20]; 8444 8445 u8 reserved_at_40[0x40]; 8446 }; 8447 8448 struct mlx5_ifc_enable_hca_out_bits { 8449 u8 status[0x8]; 8450 u8 reserved_at_8[0x18]; 8451 8452 u8 syndrome[0x20]; 8453 8454 u8 reserved_at_40[0x20]; 8455 }; 8456 8457 struct mlx5_ifc_enable_hca_in_bits { 8458 u8 opcode[0x10]; 8459 u8 reserved_at_10[0x10]; 8460 8461 u8 reserved_at_20[0x10]; 8462 u8 op_mod[0x10]; 8463 8464 u8 embedded_cpu_function[0x1]; 8465 u8 reserved_at_41[0x2]; 8466 u8 function_id_type[0x1]; 8467 u8 reserved_at_44[0xc]; 8468 u8 function_id[0x10]; 8469 8470 u8 reserved_at_60[0x20]; 8471 }; 8472 8473 struct mlx5_ifc_drain_dct_out_bits { 8474 u8 status[0x8]; 8475 u8 reserved_at_8[0x18]; 8476 8477 u8 syndrome[0x20]; 8478 8479 u8 reserved_at_40[0x40]; 8480 }; 8481 8482 struct mlx5_ifc_drain_dct_in_bits { 8483 u8 opcode[0x10]; 8484 u8 uid[0x10]; 8485 8486 u8 reserved_at_20[0x10]; 8487 u8 op_mod[0x10]; 8488 8489 u8 reserved_at_40[0x8]; 8490 u8 dctn[0x18]; 8491 8492 u8 reserved_at_60[0x20]; 8493 }; 8494 8495 struct mlx5_ifc_disable_hca_out_bits { 8496 u8 status[0x8]; 8497 u8 reserved_at_8[0x18]; 8498 8499 u8 syndrome[0x20]; 8500 8501 u8 reserved_at_40[0x20]; 8502 }; 8503 8504 struct mlx5_ifc_disable_hca_in_bits { 8505 u8 opcode[0x10]; 8506 u8 reserved_at_10[0x10]; 8507 8508 u8 reserved_at_20[0x10]; 8509 u8 op_mod[0x10]; 8510 8511 u8 embedded_cpu_function[0x1]; 8512 u8 reserved_at_41[0x2]; 8513 u8 function_id_type[0x1]; 8514 u8 reserved_at_44[0xc]; 8515 u8 function_id[0x10]; 8516 8517 u8 reserved_at_60[0x20]; 8518 }; 8519 8520 struct mlx5_ifc_detach_from_mcg_out_bits { 8521 u8 status[0x8]; 8522 u8 reserved_at_8[0x18]; 8523 8524 u8 syndrome[0x20]; 8525 8526 u8 reserved_at_40[0x40]; 8527 }; 8528 8529 struct mlx5_ifc_detach_from_mcg_in_bits { 8530 u8 opcode[0x10]; 8531 u8 uid[0x10]; 8532 8533 u8 reserved_at_20[0x10]; 8534 u8 op_mod[0x10]; 8535 8536 u8 reserved_at_40[0x8]; 8537 u8 qpn[0x18]; 8538 8539 u8 reserved_at_60[0x20]; 8540 8541 u8 multicast_gid[16][0x8]; 8542 }; 8543 8544 struct mlx5_ifc_destroy_xrq_out_bits { 8545 u8 status[0x8]; 8546 u8 reserved_at_8[0x18]; 8547 8548 u8 syndrome[0x20]; 8549 8550 u8 reserved_at_40[0x40]; 8551 }; 8552 8553 struct mlx5_ifc_destroy_xrq_in_bits { 8554 u8 opcode[0x10]; 8555 u8 uid[0x10]; 8556 8557 u8 reserved_at_20[0x10]; 8558 u8 op_mod[0x10]; 8559 8560 u8 reserved_at_40[0x8]; 8561 u8 xrqn[0x18]; 8562 8563 u8 reserved_at_60[0x20]; 8564 }; 8565 8566 struct mlx5_ifc_destroy_xrc_srq_out_bits { 8567 u8 status[0x8]; 8568 u8 reserved_at_8[0x18]; 8569 8570 u8 syndrome[0x20]; 8571 8572 u8 reserved_at_40[0x40]; 8573 }; 8574 8575 struct mlx5_ifc_destroy_xrc_srq_in_bits { 8576 u8 opcode[0x10]; 8577 u8 uid[0x10]; 8578 8579 u8 reserved_at_20[0x10]; 8580 u8 op_mod[0x10]; 8581 8582 u8 reserved_at_40[0x8]; 8583 u8 xrc_srqn[0x18]; 8584 8585 u8 reserved_at_60[0x20]; 8586 }; 8587 8588 struct mlx5_ifc_destroy_tis_out_bits { 8589 u8 status[0x8]; 8590 u8 reserved_at_8[0x18]; 8591 8592 u8 syndrome[0x20]; 8593 8594 u8 reserved_at_40[0x40]; 8595 }; 8596 8597 struct mlx5_ifc_destroy_tis_in_bits { 8598 u8 opcode[0x10]; 8599 u8 uid[0x10]; 8600 8601 u8 reserved_at_20[0x10]; 8602 u8 op_mod[0x10]; 8603 8604 u8 reserved_at_40[0x8]; 8605 u8 tisn[0x18]; 8606 8607 u8 reserved_at_60[0x20]; 8608 }; 8609 8610 struct mlx5_ifc_destroy_tir_out_bits { 8611 u8 status[0x8]; 8612 u8 reserved_at_8[0x18]; 8613 8614 u8 syndrome[0x20]; 8615 8616 u8 reserved_at_40[0x40]; 8617 }; 8618 8619 struct mlx5_ifc_destroy_tir_in_bits { 8620 u8 opcode[0x10]; 8621 u8 uid[0x10]; 8622 8623 u8 reserved_at_20[0x10]; 8624 u8 op_mod[0x10]; 8625 8626 u8 reserved_at_40[0x8]; 8627 u8 tirn[0x18]; 8628 8629 u8 reserved_at_60[0x20]; 8630 }; 8631 8632 struct mlx5_ifc_destroy_srq_out_bits { 8633 u8 status[0x8]; 8634 u8 reserved_at_8[0x18]; 8635 8636 u8 syndrome[0x20]; 8637 8638 u8 reserved_at_40[0x40]; 8639 }; 8640 8641 struct mlx5_ifc_destroy_srq_in_bits { 8642 u8 opcode[0x10]; 8643 u8 uid[0x10]; 8644 8645 u8 reserved_at_20[0x10]; 8646 u8 op_mod[0x10]; 8647 8648 u8 reserved_at_40[0x8]; 8649 u8 srqn[0x18]; 8650 8651 u8 reserved_at_60[0x20]; 8652 }; 8653 8654 struct mlx5_ifc_destroy_sq_out_bits { 8655 u8 status[0x8]; 8656 u8 reserved_at_8[0x18]; 8657 8658 u8 syndrome[0x20]; 8659 8660 u8 reserved_at_40[0x40]; 8661 }; 8662 8663 struct mlx5_ifc_destroy_sq_in_bits { 8664 u8 opcode[0x10]; 8665 u8 uid[0x10]; 8666 8667 u8 reserved_at_20[0x10]; 8668 u8 op_mod[0x10]; 8669 8670 u8 reserved_at_40[0x8]; 8671 u8 sqn[0x18]; 8672 8673 u8 reserved_at_60[0x20]; 8674 }; 8675 8676 struct mlx5_ifc_destroy_scheduling_element_out_bits { 8677 u8 status[0x8]; 8678 u8 reserved_at_8[0x18]; 8679 8680 u8 syndrome[0x20]; 8681 8682 u8 reserved_at_40[0x1c0]; 8683 }; 8684 8685 struct mlx5_ifc_destroy_scheduling_element_in_bits { 8686 u8 opcode[0x10]; 8687 u8 reserved_at_10[0x10]; 8688 8689 u8 reserved_at_20[0x10]; 8690 u8 op_mod[0x10]; 8691 8692 u8 scheduling_hierarchy[0x8]; 8693 u8 reserved_at_48[0x18]; 8694 8695 u8 scheduling_element_id[0x20]; 8696 8697 u8 reserved_at_80[0x180]; 8698 }; 8699 8700 struct mlx5_ifc_destroy_rqt_out_bits { 8701 u8 status[0x8]; 8702 u8 reserved_at_8[0x18]; 8703 8704 u8 syndrome[0x20]; 8705 8706 u8 reserved_at_40[0x40]; 8707 }; 8708 8709 struct mlx5_ifc_destroy_rqt_in_bits { 8710 u8 opcode[0x10]; 8711 u8 uid[0x10]; 8712 8713 u8 reserved_at_20[0x10]; 8714 u8 op_mod[0x10]; 8715 8716 u8 reserved_at_40[0x8]; 8717 u8 rqtn[0x18]; 8718 8719 u8 reserved_at_60[0x20]; 8720 }; 8721 8722 struct mlx5_ifc_destroy_rq_out_bits { 8723 u8 status[0x8]; 8724 u8 reserved_at_8[0x18]; 8725 8726 u8 syndrome[0x20]; 8727 8728 u8 reserved_at_40[0x40]; 8729 }; 8730 8731 struct mlx5_ifc_destroy_rq_in_bits { 8732 u8 opcode[0x10]; 8733 u8 uid[0x10]; 8734 8735 u8 reserved_at_20[0x10]; 8736 u8 op_mod[0x10]; 8737 8738 u8 reserved_at_40[0x8]; 8739 u8 rqn[0x18]; 8740 8741 u8 reserved_at_60[0x20]; 8742 }; 8743 8744 struct mlx5_ifc_set_delay_drop_params_in_bits { 8745 u8 opcode[0x10]; 8746 u8 reserved_at_10[0x10]; 8747 8748 u8 reserved_at_20[0x10]; 8749 u8 op_mod[0x10]; 8750 8751 u8 reserved_at_40[0x20]; 8752 8753 u8 reserved_at_60[0x10]; 8754 u8 delay_drop_timeout[0x10]; 8755 }; 8756 8757 struct mlx5_ifc_set_delay_drop_params_out_bits { 8758 u8 status[0x8]; 8759 u8 reserved_at_8[0x18]; 8760 8761 u8 syndrome[0x20]; 8762 8763 u8 reserved_at_40[0x40]; 8764 }; 8765 8766 struct mlx5_ifc_destroy_rmp_out_bits { 8767 u8 status[0x8]; 8768 u8 reserved_at_8[0x18]; 8769 8770 u8 syndrome[0x20]; 8771 8772 u8 reserved_at_40[0x40]; 8773 }; 8774 8775 struct mlx5_ifc_destroy_rmp_in_bits { 8776 u8 opcode[0x10]; 8777 u8 uid[0x10]; 8778 8779 u8 reserved_at_20[0x10]; 8780 u8 op_mod[0x10]; 8781 8782 u8 reserved_at_40[0x8]; 8783 u8 rmpn[0x18]; 8784 8785 u8 reserved_at_60[0x20]; 8786 }; 8787 8788 struct mlx5_ifc_destroy_qp_out_bits { 8789 u8 status[0x8]; 8790 u8 reserved_at_8[0x18]; 8791 8792 u8 syndrome[0x20]; 8793 8794 u8 reserved_at_40[0x40]; 8795 }; 8796 8797 struct mlx5_ifc_destroy_qp_in_bits { 8798 u8 opcode[0x10]; 8799 u8 uid[0x10]; 8800 8801 u8 reserved_at_20[0x10]; 8802 u8 op_mod[0x10]; 8803 8804 u8 reserved_at_40[0x8]; 8805 u8 qpn[0x18]; 8806 8807 u8 reserved_at_60[0x20]; 8808 }; 8809 8810 struct mlx5_ifc_destroy_psv_out_bits { 8811 u8 status[0x8]; 8812 u8 reserved_at_8[0x18]; 8813 8814 u8 syndrome[0x20]; 8815 8816 u8 reserved_at_40[0x40]; 8817 }; 8818 8819 struct mlx5_ifc_destroy_psv_in_bits { 8820 u8 opcode[0x10]; 8821 u8 reserved_at_10[0x10]; 8822 8823 u8 reserved_at_20[0x10]; 8824 u8 op_mod[0x10]; 8825 8826 u8 reserved_at_40[0x8]; 8827 u8 psvn[0x18]; 8828 8829 u8 reserved_at_60[0x20]; 8830 }; 8831 8832 struct mlx5_ifc_destroy_mkey_out_bits { 8833 u8 status[0x8]; 8834 u8 reserved_at_8[0x18]; 8835 8836 u8 syndrome[0x20]; 8837 8838 u8 reserved_at_40[0x40]; 8839 }; 8840 8841 struct mlx5_ifc_destroy_mkey_in_bits { 8842 u8 opcode[0x10]; 8843 u8 uid[0x10]; 8844 8845 u8 reserved_at_20[0x10]; 8846 u8 op_mod[0x10]; 8847 8848 u8 reserved_at_40[0x8]; 8849 u8 mkey_index[0x18]; 8850 8851 u8 reserved_at_60[0x20]; 8852 }; 8853 8854 struct mlx5_ifc_destroy_flow_table_out_bits { 8855 u8 status[0x8]; 8856 u8 reserved_at_8[0x18]; 8857 8858 u8 syndrome[0x20]; 8859 8860 u8 reserved_at_40[0x40]; 8861 }; 8862 8863 struct mlx5_ifc_destroy_flow_table_in_bits { 8864 u8 opcode[0x10]; 8865 u8 reserved_at_10[0x10]; 8866 8867 u8 reserved_at_20[0x10]; 8868 u8 op_mod[0x10]; 8869 8870 u8 other_vport[0x1]; 8871 u8 other_eswitch[0x1]; 8872 u8 reserved_at_42[0xe]; 8873 u8 vport_number[0x10]; 8874 8875 u8 reserved_at_60[0x20]; 8876 8877 u8 table_type[0x8]; 8878 u8 reserved_at_88[0x8]; 8879 u8 eswitch_owner_vhca_id[0x10]; 8880 8881 u8 reserved_at_a0[0x8]; 8882 u8 table_id[0x18]; 8883 8884 u8 reserved_at_c0[0x140]; 8885 }; 8886 8887 struct mlx5_ifc_destroy_flow_group_out_bits { 8888 u8 status[0x8]; 8889 u8 reserved_at_8[0x18]; 8890 8891 u8 syndrome[0x20]; 8892 8893 u8 reserved_at_40[0x40]; 8894 }; 8895 8896 struct mlx5_ifc_destroy_flow_group_in_bits { 8897 u8 opcode[0x10]; 8898 u8 reserved_at_10[0x10]; 8899 8900 u8 reserved_at_20[0x10]; 8901 u8 op_mod[0x10]; 8902 8903 u8 other_vport[0x1]; 8904 u8 other_eswitch[0x1]; 8905 u8 reserved_at_42[0xe]; 8906 u8 vport_number[0x10]; 8907 8908 u8 reserved_at_60[0x20]; 8909 8910 u8 table_type[0x8]; 8911 u8 reserved_at_88[0x8]; 8912 u8 eswitch_owner_vhca_id[0x10]; 8913 8914 u8 reserved_at_a0[0x8]; 8915 u8 table_id[0x18]; 8916 8917 u8 group_id[0x20]; 8918 8919 u8 reserved_at_e0[0x120]; 8920 }; 8921 8922 struct mlx5_ifc_destroy_eq_out_bits { 8923 u8 status[0x8]; 8924 u8 reserved_at_8[0x18]; 8925 8926 u8 syndrome[0x20]; 8927 8928 u8 reserved_at_40[0x40]; 8929 }; 8930 8931 struct mlx5_ifc_destroy_eq_in_bits { 8932 u8 opcode[0x10]; 8933 u8 reserved_at_10[0x10]; 8934 8935 u8 reserved_at_20[0x10]; 8936 u8 op_mod[0x10]; 8937 8938 u8 reserved_at_40[0x18]; 8939 u8 eq_number[0x8]; 8940 8941 u8 reserved_at_60[0x20]; 8942 }; 8943 8944 struct mlx5_ifc_destroy_dct_out_bits { 8945 u8 status[0x8]; 8946 u8 reserved_at_8[0x18]; 8947 8948 u8 syndrome[0x20]; 8949 8950 u8 reserved_at_40[0x40]; 8951 }; 8952 8953 struct mlx5_ifc_destroy_dct_in_bits { 8954 u8 opcode[0x10]; 8955 u8 uid[0x10]; 8956 8957 u8 reserved_at_20[0x10]; 8958 u8 op_mod[0x10]; 8959 8960 u8 reserved_at_40[0x8]; 8961 u8 dctn[0x18]; 8962 8963 u8 reserved_at_60[0x20]; 8964 }; 8965 8966 struct mlx5_ifc_destroy_cq_out_bits { 8967 u8 status[0x8]; 8968 u8 reserved_at_8[0x18]; 8969 8970 u8 syndrome[0x20]; 8971 8972 u8 reserved_at_40[0x40]; 8973 }; 8974 8975 struct mlx5_ifc_destroy_cq_in_bits { 8976 u8 opcode[0x10]; 8977 u8 uid[0x10]; 8978 8979 u8 reserved_at_20[0x10]; 8980 u8 op_mod[0x10]; 8981 8982 u8 reserved_at_40[0x8]; 8983 u8 cqn[0x18]; 8984 8985 u8 reserved_at_60[0x20]; 8986 }; 8987 8988 struct mlx5_ifc_delete_vxlan_udp_dport_out_bits { 8989 u8 status[0x8]; 8990 u8 reserved_at_8[0x18]; 8991 8992 u8 syndrome[0x20]; 8993 8994 u8 reserved_at_40[0x40]; 8995 }; 8996 8997 struct mlx5_ifc_delete_vxlan_udp_dport_in_bits { 8998 u8 opcode[0x10]; 8999 u8 reserved_at_10[0x10]; 9000 9001 u8 reserved_at_20[0x10]; 9002 u8 op_mod[0x10]; 9003 9004 u8 reserved_at_40[0x20]; 9005 9006 u8 reserved_at_60[0x10]; 9007 u8 vxlan_udp_port[0x10]; 9008 }; 9009 9010 struct mlx5_ifc_delete_l2_table_entry_out_bits { 9011 u8 status[0x8]; 9012 u8 reserved_at_8[0x18]; 9013 9014 u8 syndrome[0x20]; 9015 9016 u8 reserved_at_40[0x40]; 9017 }; 9018 9019 struct mlx5_ifc_delete_l2_table_entry_in_bits { 9020 u8 opcode[0x10]; 9021 u8 reserved_at_10[0x10]; 9022 9023 u8 reserved_at_20[0x10]; 9024 u8 op_mod[0x10]; 9025 9026 u8 reserved_at_40[0x60]; 9027 9028 u8 reserved_at_a0[0x8]; 9029 u8 table_index[0x18]; 9030 9031 u8 reserved_at_c0[0x140]; 9032 }; 9033 9034 struct mlx5_ifc_delete_fte_out_bits { 9035 u8 status[0x8]; 9036 u8 reserved_at_8[0x18]; 9037 9038 u8 syndrome[0x20]; 9039 9040 u8 reserved_at_40[0x40]; 9041 }; 9042 9043 struct mlx5_ifc_delete_fte_in_bits { 9044 u8 opcode[0x10]; 9045 u8 reserved_at_10[0x10]; 9046 9047 u8 reserved_at_20[0x10]; 9048 u8 op_mod[0x10]; 9049 9050 u8 other_vport[0x1]; 9051 u8 other_eswitch[0x1]; 9052 u8 reserved_at_42[0xe]; 9053 u8 vport_number[0x10]; 9054 9055 u8 reserved_at_60[0x20]; 9056 9057 u8 table_type[0x8]; 9058 u8 reserved_at_88[0x8]; 9059 u8 eswitch_owner_vhca_id[0x10]; 9060 9061 u8 reserved_at_a0[0x8]; 9062 u8 table_id[0x18]; 9063 9064 u8 reserved_at_c0[0x40]; 9065 9066 u8 flow_index[0x20]; 9067 9068 u8 reserved_at_120[0xe0]; 9069 }; 9070 9071 struct mlx5_ifc_dealloc_xrcd_out_bits { 9072 u8 status[0x8]; 9073 u8 reserved_at_8[0x18]; 9074 9075 u8 syndrome[0x20]; 9076 9077 u8 reserved_at_40[0x40]; 9078 }; 9079 9080 struct mlx5_ifc_dealloc_xrcd_in_bits { 9081 u8 opcode[0x10]; 9082 u8 uid[0x10]; 9083 9084 u8 reserved_at_20[0x10]; 9085 u8 op_mod[0x10]; 9086 9087 u8 reserved_at_40[0x8]; 9088 u8 xrcd[0x18]; 9089 9090 u8 reserved_at_60[0x20]; 9091 }; 9092 9093 struct mlx5_ifc_dealloc_uar_out_bits { 9094 u8 status[0x8]; 9095 u8 reserved_at_8[0x18]; 9096 9097 u8 syndrome[0x20]; 9098 9099 u8 reserved_at_40[0x40]; 9100 }; 9101 9102 struct mlx5_ifc_dealloc_uar_in_bits { 9103 u8 opcode[0x10]; 9104 u8 uid[0x10]; 9105 9106 u8 reserved_at_20[0x10]; 9107 u8 op_mod[0x10]; 9108 9109 u8 reserved_at_40[0x8]; 9110 u8 uar[0x18]; 9111 9112 u8 reserved_at_60[0x20]; 9113 }; 9114 9115 struct mlx5_ifc_dealloc_transport_domain_out_bits { 9116 u8 status[0x8]; 9117 u8 reserved_at_8[0x18]; 9118 9119 u8 syndrome[0x20]; 9120 9121 u8 reserved_at_40[0x40]; 9122 }; 9123 9124 struct mlx5_ifc_dealloc_transport_domain_in_bits { 9125 u8 opcode[0x10]; 9126 u8 uid[0x10]; 9127 9128 u8 reserved_at_20[0x10]; 9129 u8 op_mod[0x10]; 9130 9131 u8 reserved_at_40[0x8]; 9132 u8 transport_domain[0x18]; 9133 9134 u8 reserved_at_60[0x20]; 9135 }; 9136 9137 struct mlx5_ifc_dealloc_q_counter_out_bits { 9138 u8 status[0x8]; 9139 u8 reserved_at_8[0x18]; 9140 9141 u8 syndrome[0x20]; 9142 9143 u8 reserved_at_40[0x40]; 9144 }; 9145 9146 struct mlx5_ifc_dealloc_q_counter_in_bits { 9147 u8 opcode[0x10]; 9148 u8 reserved_at_10[0x10]; 9149 9150 u8 reserved_at_20[0x10]; 9151 u8 op_mod[0x10]; 9152 9153 u8 reserved_at_40[0x18]; 9154 u8 counter_set_id[0x8]; 9155 9156 u8 reserved_at_60[0x20]; 9157 }; 9158 9159 struct mlx5_ifc_dealloc_pd_out_bits { 9160 u8 status[0x8]; 9161 u8 reserved_at_8[0x18]; 9162 9163 u8 syndrome[0x20]; 9164 9165 u8 reserved_at_40[0x40]; 9166 }; 9167 9168 struct mlx5_ifc_dealloc_pd_in_bits { 9169 u8 opcode[0x10]; 9170 u8 uid[0x10]; 9171 9172 u8 reserved_at_20[0x10]; 9173 u8 op_mod[0x10]; 9174 9175 u8 reserved_at_40[0x8]; 9176 u8 pd[0x18]; 9177 9178 u8 reserved_at_60[0x20]; 9179 }; 9180 9181 struct mlx5_ifc_dealloc_flow_counter_out_bits { 9182 u8 status[0x8]; 9183 u8 reserved_at_8[0x18]; 9184 9185 u8 syndrome[0x20]; 9186 9187 u8 reserved_at_40[0x40]; 9188 }; 9189 9190 struct mlx5_ifc_dealloc_flow_counter_in_bits { 9191 u8 opcode[0x10]; 9192 u8 reserved_at_10[0x10]; 9193 9194 u8 reserved_at_20[0x10]; 9195 u8 op_mod[0x10]; 9196 9197 u8 flow_counter_id[0x20]; 9198 9199 u8 reserved_at_60[0x20]; 9200 }; 9201 9202 struct mlx5_ifc_create_xrq_out_bits { 9203 u8 status[0x8]; 9204 u8 reserved_at_8[0x18]; 9205 9206 u8 syndrome[0x20]; 9207 9208 u8 reserved_at_40[0x8]; 9209 u8 xrqn[0x18]; 9210 9211 u8 reserved_at_60[0x20]; 9212 }; 9213 9214 struct mlx5_ifc_create_xrq_in_bits { 9215 u8 opcode[0x10]; 9216 u8 uid[0x10]; 9217 9218 u8 reserved_at_20[0x10]; 9219 u8 op_mod[0x10]; 9220 9221 u8 reserved_at_40[0x40]; 9222 9223 struct mlx5_ifc_xrqc_bits xrq_context; 9224 }; 9225 9226 struct mlx5_ifc_create_xrc_srq_out_bits { 9227 u8 status[0x8]; 9228 u8 reserved_at_8[0x18]; 9229 9230 u8 syndrome[0x20]; 9231 9232 u8 reserved_at_40[0x8]; 9233 u8 xrc_srqn[0x18]; 9234 9235 u8 reserved_at_60[0x20]; 9236 }; 9237 9238 struct mlx5_ifc_create_xrc_srq_in_bits { 9239 u8 opcode[0x10]; 9240 u8 uid[0x10]; 9241 9242 u8 reserved_at_20[0x10]; 9243 u8 op_mod[0x10]; 9244 9245 u8 reserved_at_40[0x40]; 9246 9247 struct mlx5_ifc_xrc_srqc_bits xrc_srq_context_entry; 9248 9249 u8 reserved_at_280[0x60]; 9250 9251 u8 xrc_srq_umem_valid[0x1]; 9252 u8 reserved_at_2e1[0x1f]; 9253 9254 u8 reserved_at_300[0x580]; 9255 9256 u8 pas[][0x40]; 9257 }; 9258 9259 struct mlx5_ifc_create_tis_out_bits { 9260 u8 status[0x8]; 9261 u8 reserved_at_8[0x18]; 9262 9263 u8 syndrome[0x20]; 9264 9265 u8 reserved_at_40[0x8]; 9266 u8 tisn[0x18]; 9267 9268 u8 reserved_at_60[0x20]; 9269 }; 9270 9271 struct mlx5_ifc_create_tis_in_bits { 9272 u8 opcode[0x10]; 9273 u8 uid[0x10]; 9274 9275 u8 reserved_at_20[0x10]; 9276 u8 op_mod[0x10]; 9277 9278 u8 reserved_at_40[0xc0]; 9279 9280 struct mlx5_ifc_tisc_bits ctx; 9281 }; 9282 9283 struct mlx5_ifc_create_tir_out_bits { 9284 u8 status[0x8]; 9285 u8 icm_address_63_40[0x18]; 9286 9287 u8 syndrome[0x20]; 9288 9289 u8 icm_address_39_32[0x8]; 9290 u8 tirn[0x18]; 9291 9292 u8 icm_address_31_0[0x20]; 9293 }; 9294 9295 struct mlx5_ifc_create_tir_in_bits { 9296 u8 opcode[0x10]; 9297 u8 uid[0x10]; 9298 9299 u8 reserved_at_20[0x10]; 9300 u8 op_mod[0x10]; 9301 9302 u8 reserved_at_40[0xc0]; 9303 9304 struct mlx5_ifc_tirc_bits ctx; 9305 }; 9306 9307 struct mlx5_ifc_create_srq_out_bits { 9308 u8 status[0x8]; 9309 u8 reserved_at_8[0x18]; 9310 9311 u8 syndrome[0x20]; 9312 9313 u8 reserved_at_40[0x8]; 9314 u8 srqn[0x18]; 9315 9316 u8 reserved_at_60[0x20]; 9317 }; 9318 9319 struct mlx5_ifc_create_srq_in_bits { 9320 u8 opcode[0x10]; 9321 u8 uid[0x10]; 9322 9323 u8 reserved_at_20[0x10]; 9324 u8 op_mod[0x10]; 9325 9326 u8 reserved_at_40[0x40]; 9327 9328 struct mlx5_ifc_srqc_bits srq_context_entry; 9329 9330 u8 reserved_at_280[0x600]; 9331 9332 u8 pas[][0x40]; 9333 }; 9334 9335 struct mlx5_ifc_create_sq_out_bits { 9336 u8 status[0x8]; 9337 u8 reserved_at_8[0x18]; 9338 9339 u8 syndrome[0x20]; 9340 9341 u8 reserved_at_40[0x8]; 9342 u8 sqn[0x18]; 9343 9344 u8 reserved_at_60[0x20]; 9345 }; 9346 9347 struct mlx5_ifc_create_sq_in_bits { 9348 u8 opcode[0x10]; 9349 u8 uid[0x10]; 9350 9351 u8 reserved_at_20[0x10]; 9352 u8 op_mod[0x10]; 9353 9354 u8 reserved_at_40[0xc0]; 9355 9356 struct mlx5_ifc_sqc_bits ctx; 9357 }; 9358 9359 struct mlx5_ifc_create_scheduling_element_out_bits { 9360 u8 status[0x8]; 9361 u8 reserved_at_8[0x18]; 9362 9363 u8 syndrome[0x20]; 9364 9365 u8 reserved_at_40[0x40]; 9366 9367 u8 scheduling_element_id[0x20]; 9368 9369 u8 reserved_at_a0[0x160]; 9370 }; 9371 9372 struct mlx5_ifc_create_scheduling_element_in_bits { 9373 u8 opcode[0x10]; 9374 u8 reserved_at_10[0x10]; 9375 9376 u8 reserved_at_20[0x10]; 9377 u8 op_mod[0x10]; 9378 9379 u8 scheduling_hierarchy[0x8]; 9380 u8 reserved_at_48[0x18]; 9381 9382 u8 reserved_at_60[0xa0]; 9383 9384 struct mlx5_ifc_scheduling_context_bits scheduling_context; 9385 9386 u8 reserved_at_300[0x100]; 9387 }; 9388 9389 struct mlx5_ifc_create_rqt_out_bits { 9390 u8 status[0x8]; 9391 u8 reserved_at_8[0x18]; 9392 9393 u8 syndrome[0x20]; 9394 9395 u8 reserved_at_40[0x8]; 9396 u8 rqtn[0x18]; 9397 9398 u8 reserved_at_60[0x20]; 9399 }; 9400 9401 struct mlx5_ifc_create_rqt_in_bits { 9402 u8 opcode[0x10]; 9403 u8 uid[0x10]; 9404 9405 u8 reserved_at_20[0x10]; 9406 u8 op_mod[0x10]; 9407 9408 u8 reserved_at_40[0xc0]; 9409 9410 struct mlx5_ifc_rqtc_bits rqt_context; 9411 }; 9412 9413 struct mlx5_ifc_create_rq_out_bits { 9414 u8 status[0x8]; 9415 u8 reserved_at_8[0x18]; 9416 9417 u8 syndrome[0x20]; 9418 9419 u8 reserved_at_40[0x8]; 9420 u8 rqn[0x18]; 9421 9422 u8 reserved_at_60[0x20]; 9423 }; 9424 9425 struct mlx5_ifc_create_rq_in_bits { 9426 u8 opcode[0x10]; 9427 u8 uid[0x10]; 9428 9429 u8 reserved_at_20[0x10]; 9430 u8 op_mod[0x10]; 9431 9432 u8 reserved_at_40[0xc0]; 9433 9434 struct mlx5_ifc_rqc_bits ctx; 9435 }; 9436 9437 struct mlx5_ifc_create_rmp_out_bits { 9438 u8 status[0x8]; 9439 u8 reserved_at_8[0x18]; 9440 9441 u8 syndrome[0x20]; 9442 9443 u8 reserved_at_40[0x8]; 9444 u8 rmpn[0x18]; 9445 9446 u8 reserved_at_60[0x20]; 9447 }; 9448 9449 struct mlx5_ifc_create_rmp_in_bits { 9450 u8 opcode[0x10]; 9451 u8 uid[0x10]; 9452 9453 u8 reserved_at_20[0x10]; 9454 u8 op_mod[0x10]; 9455 9456 u8 reserved_at_40[0xc0]; 9457 9458 struct mlx5_ifc_rmpc_bits ctx; 9459 }; 9460 9461 struct mlx5_ifc_create_qp_out_bits { 9462 u8 status[0x8]; 9463 u8 reserved_at_8[0x18]; 9464 9465 u8 syndrome[0x20]; 9466 9467 u8 reserved_at_40[0x8]; 9468 u8 qpn[0x18]; 9469 9470 u8 ece[0x20]; 9471 }; 9472 9473 struct mlx5_ifc_create_qp_in_bits { 9474 u8 opcode[0x10]; 9475 u8 uid[0x10]; 9476 9477 u8 reserved_at_20[0x10]; 9478 u8 op_mod[0x10]; 9479 9480 u8 qpc_ext[0x1]; 9481 u8 reserved_at_41[0x7]; 9482 u8 input_qpn[0x18]; 9483 9484 u8 reserved_at_60[0x20]; 9485 u8 opt_param_mask[0x20]; 9486 9487 u8 ece[0x20]; 9488 9489 struct mlx5_ifc_qpc_bits qpc; 9490 9491 u8 wq_umem_offset[0x40]; 9492 9493 u8 wq_umem_id[0x20]; 9494 9495 u8 wq_umem_valid[0x1]; 9496 u8 reserved_at_861[0x1f]; 9497 9498 u8 pas[][0x40]; 9499 }; 9500 9501 struct mlx5_ifc_create_psv_out_bits { 9502 u8 status[0x8]; 9503 u8 reserved_at_8[0x18]; 9504 9505 u8 syndrome[0x20]; 9506 9507 u8 reserved_at_40[0x40]; 9508 9509 u8 reserved_at_80[0x8]; 9510 u8 psv0_index[0x18]; 9511 9512 u8 reserved_at_a0[0x8]; 9513 u8 psv1_index[0x18]; 9514 9515 u8 reserved_at_c0[0x8]; 9516 u8 psv2_index[0x18]; 9517 9518 u8 reserved_at_e0[0x8]; 9519 u8 psv3_index[0x18]; 9520 }; 9521 9522 struct mlx5_ifc_create_psv_in_bits { 9523 u8 opcode[0x10]; 9524 u8 reserved_at_10[0x10]; 9525 9526 u8 reserved_at_20[0x10]; 9527 u8 op_mod[0x10]; 9528 9529 u8 num_psv[0x4]; 9530 u8 reserved_at_44[0x4]; 9531 u8 pd[0x18]; 9532 9533 u8 reserved_at_60[0x20]; 9534 }; 9535 9536 struct mlx5_ifc_create_mkey_out_bits { 9537 u8 status[0x8]; 9538 u8 reserved_at_8[0x18]; 9539 9540 u8 syndrome[0x20]; 9541 9542 u8 reserved_at_40[0x8]; 9543 u8 mkey_index[0x18]; 9544 9545 u8 reserved_at_60[0x20]; 9546 }; 9547 9548 struct mlx5_ifc_create_mkey_in_bits { 9549 u8 opcode[0x10]; 9550 u8 uid[0x10]; 9551 9552 u8 reserved_at_20[0x10]; 9553 u8 op_mod[0x10]; 9554 9555 u8 reserved_at_40[0x20]; 9556 9557 u8 pg_access[0x1]; 9558 u8 mkey_umem_valid[0x1]; 9559 u8 data_direct[0x1]; 9560 u8 reserved_at_63[0x1d]; 9561 9562 struct mlx5_ifc_mkc_bits memory_key_mkey_entry; 9563 9564 u8 reserved_at_280[0x80]; 9565 9566 u8 translations_octword_actual_size[0x20]; 9567 9568 u8 reserved_at_320[0x560]; 9569 9570 u8 klm_pas_mtt[][0x20]; 9571 }; 9572 9573 enum { 9574 MLX5_FLOW_TABLE_TYPE_NIC_RX = 0x0, 9575 MLX5_FLOW_TABLE_TYPE_NIC_TX = 0x1, 9576 MLX5_FLOW_TABLE_TYPE_ESW_EGRESS_ACL = 0x2, 9577 MLX5_FLOW_TABLE_TYPE_ESW_INGRESS_ACL = 0x3, 9578 MLX5_FLOW_TABLE_TYPE_FDB = 0X4, 9579 MLX5_FLOW_TABLE_TYPE_SNIFFER_RX = 0X5, 9580 MLX5_FLOW_TABLE_TYPE_SNIFFER_TX = 0X6, 9581 }; 9582 9583 struct mlx5_ifc_create_flow_table_out_bits { 9584 u8 status[0x8]; 9585 u8 icm_address_63_40[0x18]; 9586 9587 u8 syndrome[0x20]; 9588 9589 u8 icm_address_39_32[0x8]; 9590 u8 table_id[0x18]; 9591 9592 u8 icm_address_31_0[0x20]; 9593 }; 9594 9595 struct mlx5_ifc_create_flow_table_in_bits { 9596 u8 opcode[0x10]; 9597 u8 uid[0x10]; 9598 9599 u8 reserved_at_20[0x10]; 9600 u8 op_mod[0x10]; 9601 9602 u8 other_vport[0x1]; 9603 u8 other_eswitch[0x1]; 9604 u8 reserved_at_42[0xe]; 9605 u8 vport_number[0x10]; 9606 9607 u8 reserved_at_60[0x20]; 9608 9609 u8 table_type[0x8]; 9610 u8 reserved_at_88[0x8]; 9611 u8 eswitch_owner_vhca_id[0x10]; 9612 9613 u8 reserved_at_a0[0x20]; 9614 9615 struct mlx5_ifc_flow_table_context_bits flow_table_context; 9616 }; 9617 9618 struct mlx5_ifc_create_flow_group_out_bits { 9619 u8 status[0x8]; 9620 u8 reserved_at_8[0x18]; 9621 9622 u8 syndrome[0x20]; 9623 9624 u8 reserved_at_40[0x8]; 9625 u8 group_id[0x18]; 9626 9627 u8 reserved_at_60[0x20]; 9628 }; 9629 9630 enum { 9631 MLX5_CREATE_FLOW_GROUP_IN_GROUP_TYPE_TCAM_SUBTABLE = 0x0, 9632 MLX5_CREATE_FLOW_GROUP_IN_GROUP_TYPE_HASH_SPLIT = 0x1, 9633 }; 9634 9635 enum { 9636 MLX5_CREATE_FLOW_GROUP_IN_MATCH_CRITERIA_ENABLE_OUTER_HEADERS = 0x0, 9637 MLX5_CREATE_FLOW_GROUP_IN_MATCH_CRITERIA_ENABLE_MISC_PARAMETERS = 0x1, 9638 MLX5_CREATE_FLOW_GROUP_IN_MATCH_CRITERIA_ENABLE_INNER_HEADERS = 0x2, 9639 MLX5_CREATE_FLOW_GROUP_IN_MATCH_CRITERIA_ENABLE_MISC_PARAMETERS_2 = 0x3, 9640 }; 9641 9642 struct mlx5_ifc_create_flow_group_in_bits { 9643 u8 opcode[0x10]; 9644 u8 reserved_at_10[0x10]; 9645 9646 u8 reserved_at_20[0x10]; 9647 u8 op_mod[0x10]; 9648 9649 u8 other_vport[0x1]; 9650 u8 other_eswitch[0x1]; 9651 u8 reserved_at_42[0xe]; 9652 u8 vport_number[0x10]; 9653 9654 u8 reserved_at_60[0x20]; 9655 9656 u8 table_type[0x8]; 9657 u8 reserved_at_88[0x4]; 9658 u8 group_type[0x4]; 9659 u8 eswitch_owner_vhca_id[0x10]; 9660 9661 u8 reserved_at_a0[0x8]; 9662 u8 table_id[0x18]; 9663 9664 u8 source_eswitch_owner_vhca_id_valid[0x1]; 9665 9666 u8 reserved_at_c1[0x1f]; 9667 9668 u8 start_flow_index[0x20]; 9669 9670 u8 reserved_at_100[0x20]; 9671 9672 u8 end_flow_index[0x20]; 9673 9674 u8 reserved_at_140[0x10]; 9675 u8 match_definer_id[0x10]; 9676 9677 u8 reserved_at_160[0x80]; 9678 9679 u8 reserved_at_1e0[0x18]; 9680 u8 match_criteria_enable[0x8]; 9681 9682 struct mlx5_ifc_fte_match_param_bits match_criteria; 9683 9684 u8 reserved_at_1200[0xe00]; 9685 }; 9686 9687 struct mlx5_ifc_create_eq_out_bits { 9688 u8 status[0x8]; 9689 u8 reserved_at_8[0x18]; 9690 9691 u8 syndrome[0x20]; 9692 9693 u8 reserved_at_40[0x18]; 9694 u8 eq_number[0x8]; 9695 9696 u8 reserved_at_60[0x20]; 9697 }; 9698 9699 struct mlx5_ifc_create_eq_in_bits { 9700 u8 opcode[0x10]; 9701 u8 uid[0x10]; 9702 9703 u8 reserved_at_20[0x10]; 9704 u8 op_mod[0x10]; 9705 9706 u8 reserved_at_40[0x40]; 9707 9708 struct mlx5_ifc_eqc_bits eq_context_entry; 9709 9710 u8 reserved_at_280[0x40]; 9711 9712 u8 event_bitmask[4][0x40]; 9713 9714 u8 reserved_at_3c0[0x4c0]; 9715 9716 u8 pas[][0x40]; 9717 }; 9718 9719 struct mlx5_ifc_create_dct_out_bits { 9720 u8 status[0x8]; 9721 u8 reserved_at_8[0x18]; 9722 9723 u8 syndrome[0x20]; 9724 9725 u8 reserved_at_40[0x8]; 9726 u8 dctn[0x18]; 9727 9728 u8 ece[0x20]; 9729 }; 9730 9731 struct mlx5_ifc_create_dct_in_bits { 9732 u8 opcode[0x10]; 9733 u8 uid[0x10]; 9734 9735 u8 reserved_at_20[0x10]; 9736 u8 op_mod[0x10]; 9737 9738 u8 reserved_at_40[0x40]; 9739 9740 struct mlx5_ifc_dctc_bits dct_context_entry; 9741 9742 u8 reserved_at_280[0x180]; 9743 }; 9744 9745 struct mlx5_ifc_create_cq_out_bits { 9746 u8 status[0x8]; 9747 u8 reserved_at_8[0x18]; 9748 9749 u8 syndrome[0x20]; 9750 9751 u8 reserved_at_40[0x8]; 9752 u8 cqn[0x18]; 9753 9754 u8 reserved_at_60[0x20]; 9755 }; 9756 9757 struct mlx5_ifc_create_cq_in_bits { 9758 u8 opcode[0x10]; 9759 u8 uid[0x10]; 9760 9761 u8 reserved_at_20[0x10]; 9762 u8 op_mod[0x10]; 9763 9764 u8 reserved_at_40[0x40]; 9765 9766 struct mlx5_ifc_cqc_bits cq_context; 9767 9768 u8 reserved_at_280[0x60]; 9769 9770 u8 cq_umem_valid[0x1]; 9771 u8 reserved_at_2e1[0x59f]; 9772 9773 u8 pas[][0x40]; 9774 }; 9775 9776 struct mlx5_ifc_config_int_moderation_out_bits { 9777 u8 status[0x8]; 9778 u8 reserved_at_8[0x18]; 9779 9780 u8 syndrome[0x20]; 9781 9782 u8 reserved_at_40[0x4]; 9783 u8 min_delay[0xc]; 9784 u8 int_vector[0x10]; 9785 9786 u8 reserved_at_60[0x20]; 9787 }; 9788 9789 enum { 9790 MLX5_CONFIG_INT_MODERATION_IN_OP_MOD_WRITE = 0x0, 9791 MLX5_CONFIG_INT_MODERATION_IN_OP_MOD_READ = 0x1, 9792 }; 9793 9794 struct mlx5_ifc_config_int_moderation_in_bits { 9795 u8 opcode[0x10]; 9796 u8 reserved_at_10[0x10]; 9797 9798 u8 reserved_at_20[0x10]; 9799 u8 op_mod[0x10]; 9800 9801 u8 reserved_at_40[0x4]; 9802 u8 min_delay[0xc]; 9803 u8 int_vector[0x10]; 9804 9805 u8 reserved_at_60[0x20]; 9806 }; 9807 9808 struct mlx5_ifc_attach_to_mcg_out_bits { 9809 u8 status[0x8]; 9810 u8 reserved_at_8[0x18]; 9811 9812 u8 syndrome[0x20]; 9813 9814 u8 reserved_at_40[0x40]; 9815 }; 9816 9817 struct mlx5_ifc_attach_to_mcg_in_bits { 9818 u8 opcode[0x10]; 9819 u8 uid[0x10]; 9820 9821 u8 reserved_at_20[0x10]; 9822 u8 op_mod[0x10]; 9823 9824 u8 reserved_at_40[0x8]; 9825 u8 qpn[0x18]; 9826 9827 u8 reserved_at_60[0x20]; 9828 9829 u8 multicast_gid[16][0x8]; 9830 }; 9831 9832 struct mlx5_ifc_arm_xrq_out_bits { 9833 u8 status[0x8]; 9834 u8 reserved_at_8[0x18]; 9835 9836 u8 syndrome[0x20]; 9837 9838 u8 reserved_at_40[0x40]; 9839 }; 9840 9841 struct mlx5_ifc_arm_xrq_in_bits { 9842 u8 opcode[0x10]; 9843 u8 reserved_at_10[0x10]; 9844 9845 u8 reserved_at_20[0x10]; 9846 u8 op_mod[0x10]; 9847 9848 u8 reserved_at_40[0x8]; 9849 u8 xrqn[0x18]; 9850 9851 u8 reserved_at_60[0x10]; 9852 u8 lwm[0x10]; 9853 }; 9854 9855 struct mlx5_ifc_arm_xrc_srq_out_bits { 9856 u8 status[0x8]; 9857 u8 reserved_at_8[0x18]; 9858 9859 u8 syndrome[0x20]; 9860 9861 u8 reserved_at_40[0x40]; 9862 }; 9863 9864 enum { 9865 MLX5_ARM_XRC_SRQ_IN_OP_MOD_XRC_SRQ = 0x1, 9866 }; 9867 9868 struct mlx5_ifc_arm_xrc_srq_in_bits { 9869 u8 opcode[0x10]; 9870 u8 uid[0x10]; 9871 9872 u8 reserved_at_20[0x10]; 9873 u8 op_mod[0x10]; 9874 9875 u8 reserved_at_40[0x8]; 9876 u8 xrc_srqn[0x18]; 9877 9878 u8 reserved_at_60[0x10]; 9879 u8 lwm[0x10]; 9880 }; 9881 9882 struct mlx5_ifc_arm_rq_out_bits { 9883 u8 status[0x8]; 9884 u8 reserved_at_8[0x18]; 9885 9886 u8 syndrome[0x20]; 9887 9888 u8 reserved_at_40[0x40]; 9889 }; 9890 9891 enum { 9892 MLX5_ARM_RQ_IN_OP_MOD_SRQ = 0x1, 9893 MLX5_ARM_RQ_IN_OP_MOD_XRQ = 0x2, 9894 }; 9895 9896 struct mlx5_ifc_arm_rq_in_bits { 9897 u8 opcode[0x10]; 9898 u8 uid[0x10]; 9899 9900 u8 reserved_at_20[0x10]; 9901 u8 op_mod[0x10]; 9902 9903 u8 reserved_at_40[0x8]; 9904 u8 srq_number[0x18]; 9905 9906 u8 reserved_at_60[0x10]; 9907 u8 lwm[0x10]; 9908 }; 9909 9910 struct mlx5_ifc_arm_dct_out_bits { 9911 u8 status[0x8]; 9912 u8 reserved_at_8[0x18]; 9913 9914 u8 syndrome[0x20]; 9915 9916 u8 reserved_at_40[0x40]; 9917 }; 9918 9919 struct mlx5_ifc_arm_dct_in_bits { 9920 u8 opcode[0x10]; 9921 u8 reserved_at_10[0x10]; 9922 9923 u8 reserved_at_20[0x10]; 9924 u8 op_mod[0x10]; 9925 9926 u8 reserved_at_40[0x8]; 9927 u8 dct_number[0x18]; 9928 9929 u8 reserved_at_60[0x20]; 9930 }; 9931 9932 struct mlx5_ifc_alloc_xrcd_out_bits { 9933 u8 status[0x8]; 9934 u8 reserved_at_8[0x18]; 9935 9936 u8 syndrome[0x20]; 9937 9938 u8 reserved_at_40[0x8]; 9939 u8 xrcd[0x18]; 9940 9941 u8 reserved_at_60[0x20]; 9942 }; 9943 9944 struct mlx5_ifc_alloc_xrcd_in_bits { 9945 u8 opcode[0x10]; 9946 u8 uid[0x10]; 9947 9948 u8 reserved_at_20[0x10]; 9949 u8 op_mod[0x10]; 9950 9951 u8 reserved_at_40[0x40]; 9952 }; 9953 9954 struct mlx5_ifc_alloc_uar_out_bits { 9955 u8 status[0x8]; 9956 u8 reserved_at_8[0x18]; 9957 9958 u8 syndrome[0x20]; 9959 9960 u8 reserved_at_40[0x8]; 9961 u8 uar[0x18]; 9962 9963 u8 reserved_at_60[0x20]; 9964 }; 9965 9966 struct mlx5_ifc_alloc_uar_in_bits { 9967 u8 opcode[0x10]; 9968 u8 uid[0x10]; 9969 9970 u8 reserved_at_20[0x10]; 9971 u8 op_mod[0x10]; 9972 9973 u8 reserved_at_40[0x40]; 9974 }; 9975 9976 struct mlx5_ifc_alloc_transport_domain_out_bits { 9977 u8 status[0x8]; 9978 u8 reserved_at_8[0x18]; 9979 9980 u8 syndrome[0x20]; 9981 9982 u8 reserved_at_40[0x8]; 9983 u8 transport_domain[0x18]; 9984 9985 u8 reserved_at_60[0x20]; 9986 }; 9987 9988 struct mlx5_ifc_alloc_transport_domain_in_bits { 9989 u8 opcode[0x10]; 9990 u8 uid[0x10]; 9991 9992 u8 reserved_at_20[0x10]; 9993 u8 op_mod[0x10]; 9994 9995 u8 reserved_at_40[0x40]; 9996 }; 9997 9998 struct mlx5_ifc_alloc_q_counter_out_bits { 9999 u8 status[0x8]; 10000 u8 reserved_at_8[0x18]; 10001 10002 u8 syndrome[0x20]; 10003 10004 u8 reserved_at_40[0x18]; 10005 u8 counter_set_id[0x8]; 10006 10007 u8 reserved_at_60[0x20]; 10008 }; 10009 10010 struct mlx5_ifc_alloc_q_counter_in_bits { 10011 u8 opcode[0x10]; 10012 u8 uid[0x10]; 10013 10014 u8 reserved_at_20[0x10]; 10015 u8 op_mod[0x10]; 10016 10017 u8 reserved_at_40[0x40]; 10018 }; 10019 10020 struct mlx5_ifc_alloc_pd_out_bits { 10021 u8 status[0x8]; 10022 u8 reserved_at_8[0x18]; 10023 10024 u8 syndrome[0x20]; 10025 10026 u8 reserved_at_40[0x8]; 10027 u8 pd[0x18]; 10028 10029 u8 reserved_at_60[0x20]; 10030 }; 10031 10032 struct mlx5_ifc_alloc_pd_in_bits { 10033 u8 opcode[0x10]; 10034 u8 uid[0x10]; 10035 10036 u8 reserved_at_20[0x10]; 10037 u8 op_mod[0x10]; 10038 10039 u8 reserved_at_40[0x40]; 10040 }; 10041 10042 struct mlx5_ifc_alloc_flow_counter_out_bits { 10043 u8 status[0x8]; 10044 u8 reserved_at_8[0x18]; 10045 10046 u8 syndrome[0x20]; 10047 10048 u8 flow_counter_id[0x20]; 10049 10050 u8 reserved_at_60[0x20]; 10051 }; 10052 10053 struct mlx5_ifc_alloc_flow_counter_in_bits { 10054 u8 opcode[0x10]; 10055 u8 reserved_at_10[0x10]; 10056 10057 u8 reserved_at_20[0x10]; 10058 u8 op_mod[0x10]; 10059 10060 u8 reserved_at_40[0x33]; 10061 u8 flow_counter_bulk_log_size[0x5]; 10062 u8 flow_counter_bulk[0x8]; 10063 }; 10064 10065 struct mlx5_ifc_add_vxlan_udp_dport_out_bits { 10066 u8 status[0x8]; 10067 u8 reserved_at_8[0x18]; 10068 10069 u8 syndrome[0x20]; 10070 10071 u8 reserved_at_40[0x40]; 10072 }; 10073 10074 struct mlx5_ifc_add_vxlan_udp_dport_in_bits { 10075 u8 opcode[0x10]; 10076 u8 reserved_at_10[0x10]; 10077 10078 u8 reserved_at_20[0x10]; 10079 u8 op_mod[0x10]; 10080 10081 u8 reserved_at_40[0x20]; 10082 10083 u8 reserved_at_60[0x10]; 10084 u8 vxlan_udp_port[0x10]; 10085 }; 10086 10087 struct mlx5_ifc_set_pp_rate_limit_out_bits { 10088 u8 status[0x8]; 10089 u8 reserved_at_8[0x18]; 10090 10091 u8 syndrome[0x20]; 10092 10093 u8 reserved_at_40[0x40]; 10094 }; 10095 10096 struct mlx5_ifc_set_pp_rate_limit_context_bits { 10097 u8 rate_limit[0x20]; 10098 10099 u8 burst_upper_bound[0x20]; 10100 10101 u8 reserved_at_40[0x10]; 10102 u8 typical_packet_size[0x10]; 10103 10104 u8 reserved_at_60[0x120]; 10105 }; 10106 10107 struct mlx5_ifc_set_pp_rate_limit_in_bits { 10108 u8 opcode[0x10]; 10109 u8 uid[0x10]; 10110 10111 u8 reserved_at_20[0x10]; 10112 u8 op_mod[0x10]; 10113 10114 u8 reserved_at_40[0x10]; 10115 u8 rate_limit_index[0x10]; 10116 10117 u8 reserved_at_60[0x20]; 10118 10119 struct mlx5_ifc_set_pp_rate_limit_context_bits ctx; 10120 }; 10121 10122 struct mlx5_ifc_access_register_out_bits { 10123 u8 status[0x8]; 10124 u8 reserved_at_8[0x18]; 10125 10126 u8 syndrome[0x20]; 10127 10128 u8 reserved_at_40[0x40]; 10129 10130 u8 register_data[][0x20]; 10131 }; 10132 10133 enum { 10134 MLX5_ACCESS_REGISTER_IN_OP_MOD_WRITE = 0x0, 10135 MLX5_ACCESS_REGISTER_IN_OP_MOD_READ = 0x1, 10136 }; 10137 10138 struct mlx5_ifc_access_register_in_bits { 10139 u8 opcode[0x10]; 10140 u8 reserved_at_10[0x10]; 10141 10142 u8 reserved_at_20[0x10]; 10143 u8 op_mod[0x10]; 10144 10145 u8 reserved_at_40[0x10]; 10146 u8 register_id[0x10]; 10147 10148 u8 argument[0x20]; 10149 10150 u8 register_data[][0x20]; 10151 }; 10152 10153 struct mlx5_ifc_sltp_reg_bits { 10154 u8 status[0x4]; 10155 u8 version[0x4]; 10156 u8 local_port[0x8]; 10157 u8 pnat[0x2]; 10158 u8 reserved_at_12[0x2]; 10159 u8 lane[0x4]; 10160 u8 reserved_at_18[0x8]; 10161 10162 u8 reserved_at_20[0x20]; 10163 10164 u8 reserved_at_40[0x7]; 10165 u8 polarity[0x1]; 10166 u8 ob_tap0[0x8]; 10167 u8 ob_tap1[0x8]; 10168 u8 ob_tap2[0x8]; 10169 10170 u8 reserved_at_60[0xc]; 10171 u8 ob_preemp_mode[0x4]; 10172 u8 ob_reg[0x8]; 10173 u8 ob_bias[0x8]; 10174 10175 u8 reserved_at_80[0x20]; 10176 }; 10177 10178 struct mlx5_ifc_slrg_reg_bits { 10179 u8 status[0x4]; 10180 u8 version[0x4]; 10181 u8 local_port[0x8]; 10182 u8 pnat[0x2]; 10183 u8 reserved_at_12[0x2]; 10184 u8 lane[0x4]; 10185 u8 reserved_at_18[0x8]; 10186 10187 u8 time_to_link_up[0x10]; 10188 u8 reserved_at_30[0xc]; 10189 u8 grade_lane_speed[0x4]; 10190 10191 u8 grade_version[0x8]; 10192 u8 grade[0x18]; 10193 10194 u8 reserved_at_60[0x4]; 10195 u8 height_grade_type[0x4]; 10196 u8 height_grade[0x18]; 10197 10198 u8 height_dz[0x10]; 10199 u8 height_dv[0x10]; 10200 10201 u8 reserved_at_a0[0x10]; 10202 u8 height_sigma[0x10]; 10203 10204 u8 reserved_at_c0[0x20]; 10205 10206 u8 reserved_at_e0[0x4]; 10207 u8 phase_grade_type[0x4]; 10208 u8 phase_grade[0x18]; 10209 10210 u8 reserved_at_100[0x8]; 10211 u8 phase_eo_pos[0x8]; 10212 u8 reserved_at_110[0x8]; 10213 u8 phase_eo_neg[0x8]; 10214 10215 u8 ffe_set_tested[0x10]; 10216 u8 test_errors_per_lane[0x10]; 10217 }; 10218 10219 struct mlx5_ifc_pvlc_reg_bits { 10220 u8 reserved_at_0[0x8]; 10221 u8 local_port[0x8]; 10222 u8 reserved_at_10[0x10]; 10223 10224 u8 reserved_at_20[0x1c]; 10225 u8 vl_hw_cap[0x4]; 10226 10227 u8 reserved_at_40[0x1c]; 10228 u8 vl_admin[0x4]; 10229 10230 u8 reserved_at_60[0x1c]; 10231 u8 vl_operational[0x4]; 10232 }; 10233 10234 struct mlx5_ifc_pude_reg_bits { 10235 u8 swid[0x8]; 10236 u8 local_port[0x8]; 10237 u8 reserved_at_10[0x4]; 10238 u8 admin_status[0x4]; 10239 u8 reserved_at_18[0x4]; 10240 u8 oper_status[0x4]; 10241 10242 u8 reserved_at_20[0x60]; 10243 }; 10244 10245 enum { 10246 MLX5_PTYS_CONNECTOR_TYPE_PORT_DA = 0x7, 10247 }; 10248 10249 struct mlx5_ifc_ptys_reg_bits { 10250 u8 reserved_at_0[0x1]; 10251 u8 an_disable_admin[0x1]; 10252 u8 an_disable_cap[0x1]; 10253 u8 reserved_at_3[0x5]; 10254 u8 local_port[0x8]; 10255 u8 reserved_at_10[0x8]; 10256 u8 plane_ind[0x4]; 10257 u8 reserved_at_1c[0x1]; 10258 u8 proto_mask[0x3]; 10259 10260 u8 an_status[0x4]; 10261 u8 reserved_at_24[0xc]; 10262 u8 data_rate_oper[0x10]; 10263 10264 u8 ext_eth_proto_capability[0x20]; 10265 10266 u8 eth_proto_capability[0x20]; 10267 10268 u8 ib_link_width_capability[0x10]; 10269 u8 ib_proto_capability[0x10]; 10270 10271 u8 ext_eth_proto_admin[0x20]; 10272 10273 u8 eth_proto_admin[0x20]; 10274 10275 u8 ib_link_width_admin[0x10]; 10276 u8 ib_proto_admin[0x10]; 10277 10278 u8 ext_eth_proto_oper[0x20]; 10279 10280 u8 eth_proto_oper[0x20]; 10281 10282 u8 ib_link_width_oper[0x10]; 10283 u8 ib_proto_oper[0x10]; 10284 10285 u8 reserved_at_160[0x8]; 10286 u8 lane_rate_oper[0x14]; 10287 u8 connector_type[0x4]; 10288 10289 u8 eth_proto_lp_advertise[0x20]; 10290 10291 u8 reserved_at_1a0[0x60]; 10292 }; 10293 10294 struct mlx5_ifc_mlcr_reg_bits { 10295 u8 reserved_at_0[0x8]; 10296 u8 local_port[0x8]; 10297 u8 reserved_at_10[0x20]; 10298 10299 u8 beacon_duration[0x10]; 10300 u8 reserved_at_40[0x10]; 10301 10302 u8 beacon_remain[0x10]; 10303 }; 10304 10305 struct mlx5_ifc_ptas_reg_bits { 10306 u8 reserved_at_0[0x20]; 10307 10308 u8 algorithm_options[0x10]; 10309 u8 reserved_at_30[0x4]; 10310 u8 repetitions_mode[0x4]; 10311 u8 num_of_repetitions[0x8]; 10312 10313 u8 grade_version[0x8]; 10314 u8 height_grade_type[0x4]; 10315 u8 phase_grade_type[0x4]; 10316 u8 height_grade_weight[0x8]; 10317 u8 phase_grade_weight[0x8]; 10318 10319 u8 gisim_measure_bits[0x10]; 10320 u8 adaptive_tap_measure_bits[0x10]; 10321 10322 u8 ber_bath_high_error_threshold[0x10]; 10323 u8 ber_bath_mid_error_threshold[0x10]; 10324 10325 u8 ber_bath_low_error_threshold[0x10]; 10326 u8 one_ratio_high_threshold[0x10]; 10327 10328 u8 one_ratio_high_mid_threshold[0x10]; 10329 u8 one_ratio_low_mid_threshold[0x10]; 10330 10331 u8 one_ratio_low_threshold[0x10]; 10332 u8 ndeo_error_threshold[0x10]; 10333 10334 u8 mixer_offset_step_size[0x10]; 10335 u8 reserved_at_110[0x8]; 10336 u8 mix90_phase_for_voltage_bath[0x8]; 10337 10338 u8 mixer_offset_start[0x10]; 10339 u8 mixer_offset_end[0x10]; 10340 10341 u8 reserved_at_140[0x15]; 10342 u8 ber_test_time[0xb]; 10343 }; 10344 10345 struct mlx5_ifc_pspa_reg_bits { 10346 u8 swid[0x8]; 10347 u8 local_port[0x8]; 10348 u8 sub_port[0x8]; 10349 u8 reserved_at_18[0x8]; 10350 10351 u8 reserved_at_20[0x20]; 10352 }; 10353 10354 struct mlx5_ifc_pqdr_reg_bits { 10355 u8 reserved_at_0[0x8]; 10356 u8 local_port[0x8]; 10357 u8 reserved_at_10[0x5]; 10358 u8 prio[0x3]; 10359 u8 reserved_at_18[0x6]; 10360 u8 mode[0x2]; 10361 10362 u8 reserved_at_20[0x20]; 10363 10364 u8 reserved_at_40[0x10]; 10365 u8 min_threshold[0x10]; 10366 10367 u8 reserved_at_60[0x10]; 10368 u8 max_threshold[0x10]; 10369 10370 u8 reserved_at_80[0x10]; 10371 u8 mark_probability_denominator[0x10]; 10372 10373 u8 reserved_at_a0[0x60]; 10374 }; 10375 10376 struct mlx5_ifc_ppsc_reg_bits { 10377 u8 reserved_at_0[0x8]; 10378 u8 local_port[0x8]; 10379 u8 reserved_at_10[0x10]; 10380 10381 u8 reserved_at_20[0x60]; 10382 10383 u8 reserved_at_80[0x1c]; 10384 u8 wrps_admin[0x4]; 10385 10386 u8 reserved_at_a0[0x1c]; 10387 u8 wrps_status[0x4]; 10388 10389 u8 reserved_at_c0[0x8]; 10390 u8 up_threshold[0x8]; 10391 u8 reserved_at_d0[0x8]; 10392 u8 down_threshold[0x8]; 10393 10394 u8 reserved_at_e0[0x20]; 10395 10396 u8 reserved_at_100[0x1c]; 10397 u8 srps_admin[0x4]; 10398 10399 u8 reserved_at_120[0x1c]; 10400 u8 srps_status[0x4]; 10401 10402 u8 reserved_at_140[0x40]; 10403 }; 10404 10405 struct mlx5_ifc_pplr_reg_bits { 10406 u8 reserved_at_0[0x8]; 10407 u8 local_port[0x8]; 10408 u8 reserved_at_10[0x10]; 10409 10410 u8 reserved_at_20[0x8]; 10411 u8 lb_cap[0x8]; 10412 u8 reserved_at_30[0x8]; 10413 u8 lb_en[0x8]; 10414 }; 10415 10416 struct mlx5_ifc_pplm_reg_bits { 10417 u8 reserved_at_0[0x8]; 10418 u8 local_port[0x8]; 10419 u8 reserved_at_10[0x10]; 10420 10421 u8 reserved_at_20[0x20]; 10422 10423 u8 port_profile_mode[0x8]; 10424 u8 static_port_profile[0x8]; 10425 u8 active_port_profile[0x8]; 10426 u8 reserved_at_58[0x8]; 10427 10428 u8 retransmission_active[0x8]; 10429 u8 fec_mode_active[0x18]; 10430 10431 u8 rs_fec_correction_bypass_cap[0x4]; 10432 u8 reserved_at_84[0x8]; 10433 u8 fec_override_cap_56g[0x4]; 10434 u8 fec_override_cap_100g[0x4]; 10435 u8 fec_override_cap_50g[0x4]; 10436 u8 fec_override_cap_25g[0x4]; 10437 u8 fec_override_cap_10g_40g[0x4]; 10438 10439 u8 rs_fec_correction_bypass_admin[0x4]; 10440 u8 reserved_at_a4[0x8]; 10441 u8 fec_override_admin_56g[0x4]; 10442 u8 fec_override_admin_100g[0x4]; 10443 u8 fec_override_admin_50g[0x4]; 10444 u8 fec_override_admin_25g[0x4]; 10445 u8 fec_override_admin_10g_40g[0x4]; 10446 10447 u8 fec_override_cap_400g_8x[0x10]; 10448 u8 fec_override_cap_200g_4x[0x10]; 10449 10450 u8 fec_override_cap_100g_2x[0x10]; 10451 u8 fec_override_cap_50g_1x[0x10]; 10452 10453 u8 fec_override_admin_400g_8x[0x10]; 10454 u8 fec_override_admin_200g_4x[0x10]; 10455 10456 u8 fec_override_admin_100g_2x[0x10]; 10457 u8 fec_override_admin_50g_1x[0x10]; 10458 10459 u8 fec_override_cap_800g_8x[0x10]; 10460 u8 fec_override_cap_400g_4x[0x10]; 10461 10462 u8 fec_override_cap_200g_2x[0x10]; 10463 u8 fec_override_cap_100g_1x[0x10]; 10464 10465 u8 reserved_at_180[0xa0]; 10466 10467 u8 fec_override_admin_800g_8x[0x10]; 10468 u8 fec_override_admin_400g_4x[0x10]; 10469 10470 u8 fec_override_admin_200g_2x[0x10]; 10471 u8 fec_override_admin_100g_1x[0x10]; 10472 10473 u8 reserved_at_260[0x60]; 10474 10475 u8 fec_override_cap_1600g_8x[0x10]; 10476 u8 fec_override_cap_800g_4x[0x10]; 10477 10478 u8 fec_override_cap_400g_2x[0x10]; 10479 u8 fec_override_cap_200g_1x[0x10]; 10480 10481 u8 fec_override_admin_1600g_8x[0x10]; 10482 u8 fec_override_admin_800g_4x[0x10]; 10483 10484 u8 fec_override_admin_400g_2x[0x10]; 10485 u8 fec_override_admin_200g_1x[0x10]; 10486 10487 u8 reserved_at_340[0x80]; 10488 }; 10489 10490 struct mlx5_ifc_ppcnt_reg_bits { 10491 u8 swid[0x8]; 10492 u8 local_port[0x8]; 10493 u8 pnat[0x2]; 10494 u8 reserved_at_12[0x8]; 10495 u8 grp[0x6]; 10496 10497 u8 clr[0x1]; 10498 u8 reserved_at_21[0x13]; 10499 u8 plane_ind[0x4]; 10500 u8 reserved_at_38[0x3]; 10501 u8 prio_tc[0x5]; 10502 10503 union mlx5_ifc_eth_cntrs_grp_data_layout_auto_bits counter_set; 10504 }; 10505 10506 struct mlx5_ifc_mpein_reg_bits { 10507 u8 reserved_at_0[0x2]; 10508 u8 depth[0x6]; 10509 u8 pcie_index[0x8]; 10510 u8 node[0x8]; 10511 u8 reserved_at_18[0x8]; 10512 10513 u8 capability_mask[0x20]; 10514 10515 u8 reserved_at_40[0x8]; 10516 u8 link_width_enabled[0x8]; 10517 u8 link_speed_enabled[0x10]; 10518 10519 u8 lane0_physical_position[0x8]; 10520 u8 link_width_active[0x8]; 10521 u8 link_speed_active[0x10]; 10522 10523 u8 num_of_pfs[0x10]; 10524 u8 num_of_vfs[0x10]; 10525 10526 u8 bdf0[0x10]; 10527 u8 reserved_at_b0[0x10]; 10528 10529 u8 max_read_request_size[0x4]; 10530 u8 max_payload_size[0x4]; 10531 u8 reserved_at_c8[0x5]; 10532 u8 pwr_status[0x3]; 10533 u8 port_type[0x4]; 10534 u8 reserved_at_d4[0xb]; 10535 u8 lane_reversal[0x1]; 10536 10537 u8 reserved_at_e0[0x14]; 10538 u8 pci_power[0xc]; 10539 10540 u8 reserved_at_100[0x20]; 10541 10542 u8 device_status[0x10]; 10543 u8 port_state[0x8]; 10544 u8 reserved_at_138[0x8]; 10545 10546 u8 reserved_at_140[0x10]; 10547 u8 receiver_detect_result[0x10]; 10548 10549 u8 reserved_at_160[0x20]; 10550 }; 10551 10552 struct mlx5_ifc_mpcnt_reg_bits { 10553 u8 reserved_at_0[0x8]; 10554 u8 pcie_index[0x8]; 10555 u8 reserved_at_10[0xa]; 10556 u8 grp[0x6]; 10557 10558 u8 clr[0x1]; 10559 u8 reserved_at_21[0x1f]; 10560 10561 union mlx5_ifc_pcie_cntrs_grp_data_layout_auto_bits counter_set; 10562 }; 10563 10564 struct mlx5_ifc_ppad_reg_bits { 10565 u8 reserved_at_0[0x3]; 10566 u8 single_mac[0x1]; 10567 u8 reserved_at_4[0x4]; 10568 u8 local_port[0x8]; 10569 u8 mac_47_32[0x10]; 10570 10571 u8 mac_31_0[0x20]; 10572 10573 u8 reserved_at_40[0x40]; 10574 }; 10575 10576 struct mlx5_ifc_pmtu_reg_bits { 10577 u8 reserved_at_0[0x8]; 10578 u8 local_port[0x8]; 10579 u8 reserved_at_10[0x10]; 10580 10581 u8 max_mtu[0x10]; 10582 u8 reserved_at_30[0x10]; 10583 10584 u8 admin_mtu[0x10]; 10585 u8 reserved_at_50[0x10]; 10586 10587 u8 oper_mtu[0x10]; 10588 u8 reserved_at_70[0x10]; 10589 }; 10590 10591 struct mlx5_ifc_pmpr_reg_bits { 10592 u8 reserved_at_0[0x8]; 10593 u8 module[0x8]; 10594 u8 reserved_at_10[0x10]; 10595 10596 u8 reserved_at_20[0x18]; 10597 u8 attenuation_5g[0x8]; 10598 10599 u8 reserved_at_40[0x18]; 10600 u8 attenuation_7g[0x8]; 10601 10602 u8 reserved_at_60[0x18]; 10603 u8 attenuation_12g[0x8]; 10604 }; 10605 10606 struct mlx5_ifc_pmpe_reg_bits { 10607 u8 reserved_at_0[0x8]; 10608 u8 module[0x8]; 10609 u8 reserved_at_10[0xc]; 10610 u8 module_status[0x4]; 10611 10612 u8 reserved_at_20[0x60]; 10613 }; 10614 10615 struct mlx5_ifc_pmpc_reg_bits { 10616 u8 module_state_updated[32][0x8]; 10617 }; 10618 10619 struct mlx5_ifc_pmlpn_reg_bits { 10620 u8 reserved_at_0[0x4]; 10621 u8 mlpn_status[0x4]; 10622 u8 local_port[0x8]; 10623 u8 reserved_at_10[0x10]; 10624 10625 u8 e[0x1]; 10626 u8 reserved_at_21[0x1f]; 10627 }; 10628 10629 struct mlx5_ifc_pmlp_reg_bits { 10630 u8 rxtx[0x1]; 10631 u8 reserved_at_1[0x7]; 10632 u8 local_port[0x8]; 10633 u8 reserved_at_10[0x8]; 10634 u8 width[0x8]; 10635 10636 u8 lane0_module_mapping[0x20]; 10637 10638 u8 lane1_module_mapping[0x20]; 10639 10640 u8 lane2_module_mapping[0x20]; 10641 10642 u8 lane3_module_mapping[0x20]; 10643 10644 u8 reserved_at_a0[0x160]; 10645 }; 10646 10647 struct mlx5_ifc_pmaos_reg_bits { 10648 u8 reserved_at_0[0x8]; 10649 u8 module[0x8]; 10650 u8 reserved_at_10[0x4]; 10651 u8 admin_status[0x4]; 10652 u8 reserved_at_18[0x4]; 10653 u8 oper_status[0x4]; 10654 10655 u8 ase[0x1]; 10656 u8 ee[0x1]; 10657 u8 reserved_at_22[0x1c]; 10658 u8 e[0x2]; 10659 10660 u8 reserved_at_40[0x40]; 10661 }; 10662 10663 struct mlx5_ifc_plpc_reg_bits { 10664 u8 reserved_at_0[0x4]; 10665 u8 profile_id[0xc]; 10666 u8 reserved_at_10[0x4]; 10667 u8 proto_mask[0x4]; 10668 u8 reserved_at_18[0x8]; 10669 10670 u8 reserved_at_20[0x10]; 10671 u8 lane_speed[0x10]; 10672 10673 u8 reserved_at_40[0x17]; 10674 u8 lpbf[0x1]; 10675 u8 fec_mode_policy[0x8]; 10676 10677 u8 retransmission_capability[0x8]; 10678 u8 fec_mode_capability[0x18]; 10679 10680 u8 retransmission_support_admin[0x8]; 10681 u8 fec_mode_support_admin[0x18]; 10682 10683 u8 retransmission_request_admin[0x8]; 10684 u8 fec_mode_request_admin[0x18]; 10685 10686 u8 reserved_at_c0[0x80]; 10687 }; 10688 10689 struct mlx5_ifc_plib_reg_bits { 10690 u8 reserved_at_0[0x8]; 10691 u8 local_port[0x8]; 10692 u8 reserved_at_10[0x8]; 10693 u8 ib_port[0x8]; 10694 10695 u8 reserved_at_20[0x60]; 10696 }; 10697 10698 struct mlx5_ifc_plbf_reg_bits { 10699 u8 reserved_at_0[0x8]; 10700 u8 local_port[0x8]; 10701 u8 reserved_at_10[0xd]; 10702 u8 lbf_mode[0x3]; 10703 10704 u8 reserved_at_20[0x20]; 10705 }; 10706 10707 struct mlx5_ifc_pipg_reg_bits { 10708 u8 reserved_at_0[0x8]; 10709 u8 local_port[0x8]; 10710 u8 reserved_at_10[0x10]; 10711 10712 u8 dic[0x1]; 10713 u8 reserved_at_21[0x19]; 10714 u8 ipg[0x4]; 10715 u8 reserved_at_3e[0x2]; 10716 }; 10717 10718 struct mlx5_ifc_pifr_reg_bits { 10719 u8 reserved_at_0[0x8]; 10720 u8 local_port[0x8]; 10721 u8 reserved_at_10[0x10]; 10722 10723 u8 reserved_at_20[0xe0]; 10724 10725 u8 port_filter[8][0x20]; 10726 10727 u8 port_filter_update_en[8][0x20]; 10728 }; 10729 10730 enum { 10731 MLX5_BUF_OWNERSHIP_UNKNOWN = 0x0, 10732 MLX5_BUF_OWNERSHIP_FW_OWNED = 0x1, 10733 MLX5_BUF_OWNERSHIP_SW_OWNED = 0x2, 10734 }; 10735 10736 struct mlx5_ifc_pfcc_reg_bits { 10737 u8 reserved_at_0[0x4]; 10738 u8 buf_ownership[0x2]; 10739 u8 reserved_at_6[0x2]; 10740 u8 local_port[0x8]; 10741 u8 reserved_at_10[0xa]; 10742 u8 cable_length_mask[0x1]; 10743 u8 ppan_mask_n[0x1]; 10744 u8 minor_stall_mask[0x1]; 10745 u8 critical_stall_mask[0x1]; 10746 u8 reserved_at_1e[0x2]; 10747 10748 u8 ppan[0x4]; 10749 u8 reserved_at_24[0x4]; 10750 u8 prio_mask_tx[0x8]; 10751 u8 reserved_at_30[0x8]; 10752 u8 prio_mask_rx[0x8]; 10753 10754 u8 pptx[0x1]; 10755 u8 aptx[0x1]; 10756 u8 pptx_mask_n[0x1]; 10757 u8 reserved_at_43[0x5]; 10758 u8 pfctx[0x8]; 10759 u8 reserved_at_50[0x10]; 10760 10761 u8 pprx[0x1]; 10762 u8 aprx[0x1]; 10763 u8 pprx_mask_n[0x1]; 10764 u8 reserved_at_63[0x5]; 10765 u8 pfcrx[0x8]; 10766 u8 reserved_at_70[0x10]; 10767 10768 u8 device_stall_minor_watermark[0x10]; 10769 u8 device_stall_critical_watermark[0x10]; 10770 10771 u8 reserved_at_a0[0x18]; 10772 u8 cable_length[0x8]; 10773 10774 u8 reserved_at_c0[0x40]; 10775 }; 10776 10777 struct mlx5_ifc_pelc_reg_bits { 10778 u8 op[0x4]; 10779 u8 reserved_at_4[0x4]; 10780 u8 local_port[0x8]; 10781 u8 reserved_at_10[0x10]; 10782 10783 u8 op_admin[0x8]; 10784 u8 op_capability[0x8]; 10785 u8 op_request[0x8]; 10786 u8 op_active[0x8]; 10787 10788 u8 admin[0x40]; 10789 10790 u8 capability[0x40]; 10791 10792 u8 request[0x40]; 10793 10794 u8 active[0x40]; 10795 10796 u8 reserved_at_140[0x80]; 10797 }; 10798 10799 struct mlx5_ifc_peir_reg_bits { 10800 u8 reserved_at_0[0x8]; 10801 u8 local_port[0x8]; 10802 u8 reserved_at_10[0x10]; 10803 10804 u8 reserved_at_20[0xc]; 10805 u8 error_count[0x4]; 10806 u8 reserved_at_30[0x10]; 10807 10808 u8 reserved_at_40[0xc]; 10809 u8 lane[0x4]; 10810 u8 reserved_at_50[0x8]; 10811 u8 error_type[0x8]; 10812 }; 10813 10814 struct mlx5_ifc_mpegc_reg_bits { 10815 u8 reserved_at_0[0x30]; 10816 u8 field_select[0x10]; 10817 10818 u8 tx_overflow_sense[0x1]; 10819 u8 mark_cqe[0x1]; 10820 u8 mark_cnp[0x1]; 10821 u8 reserved_at_43[0x1b]; 10822 u8 tx_lossy_overflow_oper[0x2]; 10823 10824 u8 reserved_at_60[0x100]; 10825 }; 10826 10827 struct mlx5_ifc_mpir_reg_bits { 10828 u8 sdm[0x1]; 10829 u8 reserved_at_1[0x1b]; 10830 u8 host_buses[0x4]; 10831 10832 u8 reserved_at_20[0x20]; 10833 10834 u8 local_port[0x8]; 10835 u8 reserved_at_28[0x18]; 10836 10837 u8 reserved_at_60[0x20]; 10838 }; 10839 10840 enum { 10841 MLX5_MTUTC_FREQ_ADJ_UNITS_PPB = 0x0, 10842 MLX5_MTUTC_FREQ_ADJ_UNITS_SCALED_PPM = 0x1, 10843 }; 10844 10845 enum { 10846 MLX5_MTUTC_OPERATION_SET_TIME_IMMEDIATE = 0x1, 10847 MLX5_MTUTC_OPERATION_ADJUST_TIME = 0x2, 10848 MLX5_MTUTC_OPERATION_ADJUST_FREQ_UTC = 0x3, 10849 }; 10850 10851 struct mlx5_ifc_mtutc_reg_bits { 10852 u8 reserved_at_0[0x5]; 10853 u8 freq_adj_units[0x3]; 10854 u8 reserved_at_8[0x3]; 10855 u8 log_max_freq_adjustment[0x5]; 10856 10857 u8 reserved_at_10[0xc]; 10858 u8 operation[0x4]; 10859 10860 u8 freq_adjustment[0x20]; 10861 10862 u8 reserved_at_40[0x40]; 10863 10864 u8 utc_sec[0x20]; 10865 10866 u8 reserved_at_a0[0x2]; 10867 u8 utc_nsec[0x1e]; 10868 10869 u8 time_adjustment[0x20]; 10870 }; 10871 10872 struct mlx5_ifc_pcam_enhanced_features_bits { 10873 u8 reserved_at_0[0x10]; 10874 u8 ppcnt_recovery_counters[0x1]; 10875 u8 reserved_at_11[0x7]; 10876 u8 cable_length[0x1]; 10877 u8 reserved_at_19[0x4]; 10878 u8 fec_200G_per_lane_in_pplm[0x1]; 10879 u8 reserved_at_1e[0x2a]; 10880 u8 fec_100G_per_lane_in_pplm[0x1]; 10881 u8 reserved_at_49[0x2]; 10882 u8 shp_pbmc_pbsr_support[0x1]; 10883 u8 reserved_at_4c[0x7]; 10884 u8 buffer_ownership[0x1]; 10885 u8 resereved_at_54[0x14]; 10886 u8 fec_50G_per_lane_in_pplm[0x1]; 10887 u8 reserved_at_69[0x4]; 10888 u8 rx_icrc_encapsulated_counter[0x1]; 10889 u8 reserved_at_6e[0x4]; 10890 u8 ptys_extended_ethernet[0x1]; 10891 u8 reserved_at_73[0x3]; 10892 u8 pfcc_mask[0x1]; 10893 u8 reserved_at_77[0x3]; 10894 u8 per_lane_error_counters[0x1]; 10895 u8 rx_buffer_fullness_counters[0x1]; 10896 u8 ptys_connector_type[0x1]; 10897 u8 reserved_at_7d[0x1]; 10898 u8 ppcnt_discard_group[0x1]; 10899 u8 ppcnt_statistical_group[0x1]; 10900 }; 10901 10902 struct mlx5_ifc_pcam_regs_5000_to_507f_bits { 10903 u8 port_access_reg_cap_mask_127_to_96[0x20]; 10904 u8 port_access_reg_cap_mask_95_to_64[0x20]; 10905 10906 u8 port_access_reg_cap_mask_63[0x1]; 10907 u8 pphcr[0x1]; 10908 u8 port_access_reg_cap_mask_61_to_36[0x1a]; 10909 u8 pplm[0x1]; 10910 u8 port_access_reg_cap_mask_34_to_32[0x3]; 10911 10912 u8 port_access_reg_cap_mask_31_to_13[0x13]; 10913 u8 pbmc[0x1]; 10914 u8 pptb[0x1]; 10915 u8 port_access_reg_cap_mask_10_to_09[0x2]; 10916 u8 ppcnt[0x1]; 10917 u8 port_access_reg_cap_mask_07_to_00[0x8]; 10918 }; 10919 10920 struct mlx5_ifc_pcam_reg_bits { 10921 u8 reserved_at_0[0x8]; 10922 u8 feature_group[0x8]; 10923 u8 reserved_at_10[0x8]; 10924 u8 access_reg_group[0x8]; 10925 10926 u8 reserved_at_20[0x20]; 10927 10928 union { 10929 struct mlx5_ifc_pcam_regs_5000_to_507f_bits regs_5000_to_507f; 10930 u8 reserved_at_0[0x80]; 10931 } port_access_reg_cap_mask; 10932 10933 u8 reserved_at_c0[0x80]; 10934 10935 union { 10936 struct mlx5_ifc_pcam_enhanced_features_bits enhanced_features; 10937 u8 reserved_at_0[0x80]; 10938 } feature_cap_mask; 10939 10940 u8 reserved_at_1c0[0xc0]; 10941 }; 10942 10943 struct mlx5_ifc_mcam_enhanced_features_bits { 10944 u8 reserved_at_0[0x50]; 10945 u8 mtutc_freq_adj_units[0x1]; 10946 u8 mtutc_time_adjustment_extended_range[0x1]; 10947 u8 reserved_at_52[0xb]; 10948 u8 mcia_32dwords[0x1]; 10949 u8 out_pulse_duration_ns[0x1]; 10950 u8 npps_period[0x1]; 10951 u8 reserved_at_60[0xa]; 10952 u8 reset_state[0x1]; 10953 u8 ptpcyc2realtime_modify[0x1]; 10954 u8 reserved_at_6c[0x2]; 10955 u8 pci_status_and_power[0x1]; 10956 u8 reserved_at_6f[0x5]; 10957 u8 mark_tx_action_cnp[0x1]; 10958 u8 mark_tx_action_cqe[0x1]; 10959 u8 dynamic_tx_overflow[0x1]; 10960 u8 reserved_at_77[0x4]; 10961 u8 pcie_outbound_stalled[0x1]; 10962 u8 tx_overflow_buffer_pkt[0x1]; 10963 u8 mtpps_enh_out_per_adj[0x1]; 10964 u8 mtpps_fs[0x1]; 10965 u8 pcie_performance_group[0x1]; 10966 }; 10967 10968 struct mlx5_ifc_mcam_access_reg_bits { 10969 u8 reserved_at_0[0x1c]; 10970 u8 mcda[0x1]; 10971 u8 mcc[0x1]; 10972 u8 mcqi[0x1]; 10973 u8 mcqs[0x1]; 10974 10975 u8 regs_95_to_90[0x6]; 10976 u8 mpir[0x1]; 10977 u8 regs_88_to_87[0x2]; 10978 u8 mpegc[0x1]; 10979 u8 mtutc[0x1]; 10980 u8 regs_84_to_68[0x11]; 10981 u8 tracer_registers[0x4]; 10982 10983 u8 regs_63_to_46[0x12]; 10984 u8 mrtc[0x1]; 10985 u8 regs_44_to_41[0x4]; 10986 u8 mfrl[0x1]; 10987 u8 regs_39_to_32[0x8]; 10988 10989 u8 regs_31_to_11[0x15]; 10990 u8 mtmp[0x1]; 10991 u8 regs_9_to_0[0xa]; 10992 }; 10993 10994 struct mlx5_ifc_mcam_access_reg_bits1 { 10995 u8 regs_127_to_96[0x20]; 10996 10997 u8 regs_95_to_64[0x20]; 10998 10999 u8 regs_63_to_32[0x20]; 11000 11001 u8 regs_31_to_0[0x20]; 11002 }; 11003 11004 struct mlx5_ifc_mcam_access_reg_bits2 { 11005 u8 regs_127_to_99[0x1d]; 11006 u8 mirc[0x1]; 11007 u8 regs_97_to_96[0x2]; 11008 11009 u8 regs_95_to_87[0x09]; 11010 u8 synce_registers[0x2]; 11011 u8 regs_84_to_64[0x15]; 11012 11013 u8 regs_63_to_32[0x20]; 11014 11015 u8 regs_31_to_0[0x20]; 11016 }; 11017 11018 struct mlx5_ifc_mcam_access_reg_bits3 { 11019 u8 regs_127_to_96[0x20]; 11020 11021 u8 regs_95_to_64[0x20]; 11022 11023 u8 regs_63_to_32[0x20]; 11024 11025 u8 regs_31_to_3[0x1d]; 11026 u8 mrtcq[0x1]; 11027 u8 mtctr[0x1]; 11028 u8 mtptm[0x1]; 11029 }; 11030 11031 struct mlx5_ifc_mcam_reg_bits { 11032 u8 reserved_at_0[0x8]; 11033 u8 feature_group[0x8]; 11034 u8 reserved_at_10[0x8]; 11035 u8 access_reg_group[0x8]; 11036 11037 u8 reserved_at_20[0x20]; 11038 11039 union { 11040 struct mlx5_ifc_mcam_access_reg_bits access_regs; 11041 struct mlx5_ifc_mcam_access_reg_bits1 access_regs1; 11042 struct mlx5_ifc_mcam_access_reg_bits2 access_regs2; 11043 struct mlx5_ifc_mcam_access_reg_bits3 access_regs3; 11044 u8 reserved_at_0[0x80]; 11045 } mng_access_reg_cap_mask; 11046 11047 u8 reserved_at_c0[0x80]; 11048 11049 union { 11050 struct mlx5_ifc_mcam_enhanced_features_bits enhanced_features; 11051 u8 reserved_at_0[0x80]; 11052 } mng_feature_cap_mask; 11053 11054 u8 reserved_at_1c0[0x80]; 11055 }; 11056 11057 struct mlx5_ifc_qcam_access_reg_cap_mask { 11058 u8 qcam_access_reg_cap_mask_127_to_20[0x6C]; 11059 u8 qpdpm[0x1]; 11060 u8 qcam_access_reg_cap_mask_18_to_4[0x0F]; 11061 u8 qdpm[0x1]; 11062 u8 qpts[0x1]; 11063 u8 qcap[0x1]; 11064 u8 qcam_access_reg_cap_mask_0[0x1]; 11065 }; 11066 11067 struct mlx5_ifc_qcam_qos_feature_cap_mask { 11068 u8 qcam_qos_feature_cap_mask_127_to_5[0x7B]; 11069 u8 qetcr_qshr_max_bw_val_msb[0x1]; 11070 u8 qcam_qos_feature_cap_mask_3_to_1[0x3]; 11071 u8 qpts_trust_both[0x1]; 11072 }; 11073 11074 struct mlx5_ifc_qcam_reg_bits { 11075 u8 reserved_at_0[0x8]; 11076 u8 feature_group[0x8]; 11077 u8 reserved_at_10[0x8]; 11078 u8 access_reg_group[0x8]; 11079 u8 reserved_at_20[0x20]; 11080 11081 union { 11082 struct mlx5_ifc_qcam_access_reg_cap_mask reg_cap; 11083 u8 reserved_at_0[0x80]; 11084 } qos_access_reg_cap_mask; 11085 11086 u8 reserved_at_c0[0x80]; 11087 11088 union { 11089 struct mlx5_ifc_qcam_qos_feature_cap_mask feature_cap; 11090 u8 reserved_at_0[0x80]; 11091 } qos_feature_cap_mask; 11092 11093 u8 reserved_at_1c0[0x80]; 11094 }; 11095 11096 struct mlx5_ifc_core_dump_reg_bits { 11097 u8 reserved_at_0[0x18]; 11098 u8 core_dump_type[0x8]; 11099 11100 u8 reserved_at_20[0x30]; 11101 u8 vhca_id[0x10]; 11102 11103 u8 reserved_at_60[0x8]; 11104 u8 qpn[0x18]; 11105 u8 reserved_at_80[0x180]; 11106 }; 11107 11108 struct mlx5_ifc_pcap_reg_bits { 11109 u8 reserved_at_0[0x8]; 11110 u8 local_port[0x8]; 11111 u8 reserved_at_10[0x10]; 11112 11113 u8 port_capability_mask[4][0x20]; 11114 }; 11115 11116 struct mlx5_ifc_paos_reg_bits { 11117 u8 swid[0x8]; 11118 u8 local_port[0x8]; 11119 u8 reserved_at_10[0x4]; 11120 u8 admin_status[0x4]; 11121 u8 reserved_at_18[0x4]; 11122 u8 oper_status[0x4]; 11123 11124 u8 ase[0x1]; 11125 u8 ee[0x1]; 11126 u8 reserved_at_22[0x1c]; 11127 u8 e[0x2]; 11128 11129 u8 reserved_at_40[0x40]; 11130 }; 11131 11132 struct mlx5_ifc_pamp_reg_bits { 11133 u8 reserved_at_0[0x8]; 11134 u8 opamp_group[0x8]; 11135 u8 reserved_at_10[0xc]; 11136 u8 opamp_group_type[0x4]; 11137 11138 u8 start_index[0x10]; 11139 u8 reserved_at_30[0x4]; 11140 u8 num_of_indices[0xc]; 11141 11142 u8 index_data[18][0x10]; 11143 }; 11144 11145 struct mlx5_ifc_pcmr_reg_bits { 11146 u8 reserved_at_0[0x8]; 11147 u8 local_port[0x8]; 11148 u8 reserved_at_10[0x10]; 11149 11150 u8 entropy_force_cap[0x1]; 11151 u8 entropy_calc_cap[0x1]; 11152 u8 entropy_gre_calc_cap[0x1]; 11153 u8 reserved_at_23[0xf]; 11154 u8 rx_ts_over_crc_cap[0x1]; 11155 u8 reserved_at_33[0xb]; 11156 u8 fcs_cap[0x1]; 11157 u8 reserved_at_3f[0x1]; 11158 11159 u8 entropy_force[0x1]; 11160 u8 entropy_calc[0x1]; 11161 u8 entropy_gre_calc[0x1]; 11162 u8 reserved_at_43[0xf]; 11163 u8 rx_ts_over_crc[0x1]; 11164 u8 reserved_at_53[0xb]; 11165 u8 fcs_chk[0x1]; 11166 u8 reserved_at_5f[0x1]; 11167 }; 11168 11169 struct mlx5_ifc_lane_2_module_mapping_bits { 11170 u8 reserved_at_0[0x4]; 11171 u8 rx_lane[0x4]; 11172 u8 reserved_at_8[0x4]; 11173 u8 tx_lane[0x4]; 11174 u8 reserved_at_10[0x8]; 11175 u8 module[0x8]; 11176 }; 11177 11178 struct mlx5_ifc_bufferx_reg_bits { 11179 u8 reserved_at_0[0x6]; 11180 u8 lossy[0x1]; 11181 u8 epsb[0x1]; 11182 u8 reserved_at_8[0x8]; 11183 u8 size[0x10]; 11184 11185 u8 xoff_threshold[0x10]; 11186 u8 xon_threshold[0x10]; 11187 }; 11188 11189 struct mlx5_ifc_set_node_in_bits { 11190 u8 node_description[64][0x8]; 11191 }; 11192 11193 struct mlx5_ifc_register_power_settings_bits { 11194 u8 reserved_at_0[0x18]; 11195 u8 power_settings_level[0x8]; 11196 11197 u8 reserved_at_20[0x60]; 11198 }; 11199 11200 struct mlx5_ifc_register_host_endianness_bits { 11201 u8 he[0x1]; 11202 u8 reserved_at_1[0x1f]; 11203 11204 u8 reserved_at_20[0x60]; 11205 }; 11206 11207 struct mlx5_ifc_umr_pointer_desc_argument_bits { 11208 u8 reserved_at_0[0x20]; 11209 11210 u8 mkey[0x20]; 11211 11212 u8 addressh_63_32[0x20]; 11213 11214 u8 addressl_31_0[0x20]; 11215 }; 11216 11217 struct mlx5_ifc_ud_adrs_vector_bits { 11218 u8 dc_key[0x40]; 11219 11220 u8 ext[0x1]; 11221 u8 reserved_at_41[0x7]; 11222 u8 destination_qp_dct[0x18]; 11223 11224 u8 static_rate[0x4]; 11225 u8 sl_eth_prio[0x4]; 11226 u8 fl[0x1]; 11227 u8 mlid[0x7]; 11228 u8 rlid_udp_sport[0x10]; 11229 11230 u8 reserved_at_80[0x20]; 11231 11232 u8 rmac_47_16[0x20]; 11233 11234 u8 rmac_15_0[0x10]; 11235 u8 tclass[0x8]; 11236 u8 hop_limit[0x8]; 11237 11238 u8 reserved_at_e0[0x1]; 11239 u8 grh[0x1]; 11240 u8 reserved_at_e2[0x2]; 11241 u8 src_addr_index[0x8]; 11242 u8 flow_label[0x14]; 11243 11244 u8 rgid_rip[16][0x8]; 11245 }; 11246 11247 struct mlx5_ifc_pages_req_event_bits { 11248 u8 reserved_at_0[0x10]; 11249 u8 function_id[0x10]; 11250 11251 u8 num_pages[0x20]; 11252 11253 u8 reserved_at_40[0xa0]; 11254 }; 11255 11256 struct mlx5_ifc_eqe_bits { 11257 u8 reserved_at_0[0x8]; 11258 u8 event_type[0x8]; 11259 u8 reserved_at_10[0x8]; 11260 u8 event_sub_type[0x8]; 11261 11262 u8 reserved_at_20[0xe0]; 11263 11264 union mlx5_ifc_event_auto_bits event_data; 11265 11266 u8 reserved_at_1e0[0x10]; 11267 u8 signature[0x8]; 11268 u8 reserved_at_1f8[0x7]; 11269 u8 owner[0x1]; 11270 }; 11271 11272 enum { 11273 MLX5_CMD_QUEUE_ENTRY_TYPE_PCIE_CMD_IF_TRANSPORT = 0x7, 11274 }; 11275 11276 struct mlx5_ifc_cmd_queue_entry_bits { 11277 u8 type[0x8]; 11278 u8 reserved_at_8[0x18]; 11279 11280 u8 input_length[0x20]; 11281 11282 u8 input_mailbox_pointer_63_32[0x20]; 11283 11284 u8 input_mailbox_pointer_31_9[0x17]; 11285 u8 reserved_at_77[0x9]; 11286 11287 u8 command_input_inline_data[16][0x8]; 11288 11289 u8 command_output_inline_data[16][0x8]; 11290 11291 u8 output_mailbox_pointer_63_32[0x20]; 11292 11293 u8 output_mailbox_pointer_31_9[0x17]; 11294 u8 reserved_at_1b7[0x9]; 11295 11296 u8 output_length[0x20]; 11297 11298 u8 token[0x8]; 11299 u8 signature[0x8]; 11300 u8 reserved_at_1f0[0x8]; 11301 u8 status[0x7]; 11302 u8 ownership[0x1]; 11303 }; 11304 11305 struct mlx5_ifc_cmd_out_bits { 11306 u8 status[0x8]; 11307 u8 reserved_at_8[0x18]; 11308 11309 u8 syndrome[0x20]; 11310 11311 u8 command_output[0x20]; 11312 }; 11313 11314 struct mlx5_ifc_cmd_in_bits { 11315 u8 opcode[0x10]; 11316 u8 reserved_at_10[0x10]; 11317 11318 u8 reserved_at_20[0x10]; 11319 u8 op_mod[0x10]; 11320 11321 u8 command[][0x20]; 11322 }; 11323 11324 struct mlx5_ifc_cmd_if_box_bits { 11325 u8 mailbox_data[512][0x8]; 11326 11327 u8 reserved_at_1000[0x180]; 11328 11329 u8 next_pointer_63_32[0x20]; 11330 11331 u8 next_pointer_31_10[0x16]; 11332 u8 reserved_at_11b6[0xa]; 11333 11334 u8 block_number[0x20]; 11335 11336 u8 reserved_at_11e0[0x8]; 11337 u8 token[0x8]; 11338 u8 ctrl_signature[0x8]; 11339 u8 signature[0x8]; 11340 }; 11341 11342 struct mlx5_ifc_mtt_bits { 11343 u8 ptag_63_32[0x20]; 11344 11345 u8 ptag_31_8[0x18]; 11346 u8 reserved_at_38[0x6]; 11347 u8 wr_en[0x1]; 11348 u8 rd_en[0x1]; 11349 }; 11350 11351 struct mlx5_ifc_query_wol_rol_out_bits { 11352 u8 status[0x8]; 11353 u8 reserved_at_8[0x18]; 11354 11355 u8 syndrome[0x20]; 11356 11357 u8 reserved_at_40[0x10]; 11358 u8 rol_mode[0x8]; 11359 u8 wol_mode[0x8]; 11360 11361 u8 reserved_at_60[0x20]; 11362 }; 11363 11364 struct mlx5_ifc_query_wol_rol_in_bits { 11365 u8 opcode[0x10]; 11366 u8 reserved_at_10[0x10]; 11367 11368 u8 reserved_at_20[0x10]; 11369 u8 op_mod[0x10]; 11370 11371 u8 reserved_at_40[0x40]; 11372 }; 11373 11374 struct mlx5_ifc_set_wol_rol_out_bits { 11375 u8 status[0x8]; 11376 u8 reserved_at_8[0x18]; 11377 11378 u8 syndrome[0x20]; 11379 11380 u8 reserved_at_40[0x40]; 11381 }; 11382 11383 struct mlx5_ifc_set_wol_rol_in_bits { 11384 u8 opcode[0x10]; 11385 u8 reserved_at_10[0x10]; 11386 11387 u8 reserved_at_20[0x10]; 11388 u8 op_mod[0x10]; 11389 11390 u8 rol_mode_valid[0x1]; 11391 u8 wol_mode_valid[0x1]; 11392 u8 reserved_at_42[0xe]; 11393 u8 rol_mode[0x8]; 11394 u8 wol_mode[0x8]; 11395 11396 u8 reserved_at_60[0x20]; 11397 }; 11398 11399 enum { 11400 MLX5_INITIAL_SEG_NIC_INTERFACE_FULL_DRIVER = 0x0, 11401 MLX5_INITIAL_SEG_NIC_INTERFACE_DISABLED = 0x1, 11402 MLX5_INITIAL_SEG_NIC_INTERFACE_NO_DRAM_NIC = 0x2, 11403 MLX5_INITIAL_SEG_NIC_INTERFACE_SW_RESET = 0x7, 11404 }; 11405 11406 enum { 11407 MLX5_INITIAL_SEG_NIC_INTERFACE_SUPPORTED_FULL_DRIVER = 0x0, 11408 MLX5_INITIAL_SEG_NIC_INTERFACE_SUPPORTED_DISABLED = 0x1, 11409 MLX5_INITIAL_SEG_NIC_INTERFACE_SUPPORTED_NO_DRAM_NIC = 0x2, 11410 }; 11411 11412 enum { 11413 MLX5_INITIAL_SEG_HEALTH_SYNDROME_FW_INTERNAL_ERR = 0x1, 11414 MLX5_INITIAL_SEG_HEALTH_SYNDROME_DEAD_IRISC = 0x7, 11415 MLX5_INITIAL_SEG_HEALTH_SYNDROME_HW_FATAL_ERR = 0x8, 11416 MLX5_INITIAL_SEG_HEALTH_SYNDROME_FW_CRC_ERR = 0x9, 11417 MLX5_INITIAL_SEG_HEALTH_SYNDROME_ICM_FETCH_PCI_ERR = 0xa, 11418 MLX5_INITIAL_SEG_HEALTH_SYNDROME_ICM_PAGE_ERR = 0xb, 11419 MLX5_INITIAL_SEG_HEALTH_SYNDROME_ASYNCHRONOUS_EQ_BUF_OVERRUN = 0xc, 11420 MLX5_INITIAL_SEG_HEALTH_SYNDROME_EQ_IN_ERR = 0xd, 11421 MLX5_INITIAL_SEG_HEALTH_SYNDROME_EQ_INV = 0xe, 11422 MLX5_INITIAL_SEG_HEALTH_SYNDROME_FFSER_ERR = 0xf, 11423 MLX5_INITIAL_SEG_HEALTH_SYNDROME_HIGH_TEMP_ERR = 0x10, 11424 MLX5_INITIAL_SEG_HEALTH_SYNDROME_ICM_PCI_POISONED_ERR = 0x12, 11425 MLX5_INITIAL_SEG_HEALTH_SYNDROME_TRUST_LOCKDOWN_ERR = 0x13, 11426 }; 11427 11428 struct mlx5_ifc_initial_seg_bits { 11429 u8 fw_rev_minor[0x10]; 11430 u8 fw_rev_major[0x10]; 11431 11432 u8 cmd_interface_rev[0x10]; 11433 u8 fw_rev_subminor[0x10]; 11434 11435 u8 reserved_at_40[0x40]; 11436 11437 u8 cmdq_phy_addr_63_32[0x20]; 11438 11439 u8 cmdq_phy_addr_31_12[0x14]; 11440 u8 reserved_at_b4[0x2]; 11441 u8 nic_interface[0x2]; 11442 u8 log_cmdq_size[0x4]; 11443 u8 log_cmdq_stride[0x4]; 11444 11445 u8 command_doorbell_vector[0x20]; 11446 11447 u8 reserved_at_e0[0xf00]; 11448 11449 u8 initializing[0x1]; 11450 u8 reserved_at_fe1[0x4]; 11451 u8 nic_interface_supported[0x3]; 11452 u8 embedded_cpu[0x1]; 11453 u8 reserved_at_fe9[0x17]; 11454 11455 struct mlx5_ifc_health_buffer_bits health_buffer; 11456 11457 u8 no_dram_nic_offset[0x20]; 11458 11459 u8 reserved_at_1220[0x6e40]; 11460 11461 u8 reserved_at_8060[0x1f]; 11462 u8 clear_int[0x1]; 11463 11464 u8 health_syndrome[0x8]; 11465 u8 health_counter[0x18]; 11466 11467 u8 reserved_at_80a0[0x17fc0]; 11468 }; 11469 11470 struct mlx5_ifc_mtpps_reg_bits { 11471 u8 reserved_at_0[0xc]; 11472 u8 cap_number_of_pps_pins[0x4]; 11473 u8 reserved_at_10[0x4]; 11474 u8 cap_max_num_of_pps_in_pins[0x4]; 11475 u8 reserved_at_18[0x4]; 11476 u8 cap_max_num_of_pps_out_pins[0x4]; 11477 11478 u8 reserved_at_20[0x13]; 11479 u8 cap_log_min_npps_period[0x5]; 11480 u8 reserved_at_38[0x3]; 11481 u8 cap_log_min_out_pulse_duration_ns[0x5]; 11482 11483 u8 reserved_at_40[0x4]; 11484 u8 cap_pin_3_mode[0x4]; 11485 u8 reserved_at_48[0x4]; 11486 u8 cap_pin_2_mode[0x4]; 11487 u8 reserved_at_50[0x4]; 11488 u8 cap_pin_1_mode[0x4]; 11489 u8 reserved_at_58[0x4]; 11490 u8 cap_pin_0_mode[0x4]; 11491 11492 u8 reserved_at_60[0x4]; 11493 u8 cap_pin_7_mode[0x4]; 11494 u8 reserved_at_68[0x4]; 11495 u8 cap_pin_6_mode[0x4]; 11496 u8 reserved_at_70[0x4]; 11497 u8 cap_pin_5_mode[0x4]; 11498 u8 reserved_at_78[0x4]; 11499 u8 cap_pin_4_mode[0x4]; 11500 11501 u8 field_select[0x20]; 11502 u8 reserved_at_a0[0x20]; 11503 11504 u8 npps_period[0x40]; 11505 11506 u8 enable[0x1]; 11507 u8 reserved_at_101[0xb]; 11508 u8 pattern[0x4]; 11509 u8 reserved_at_110[0x4]; 11510 u8 pin_mode[0x4]; 11511 u8 pin[0x8]; 11512 11513 u8 reserved_at_120[0x2]; 11514 u8 out_pulse_duration_ns[0x1e]; 11515 11516 u8 time_stamp[0x40]; 11517 11518 u8 out_pulse_duration[0x10]; 11519 u8 out_periodic_adjustment[0x10]; 11520 u8 enhanced_out_periodic_adjustment[0x20]; 11521 11522 u8 reserved_at_1c0[0x20]; 11523 }; 11524 11525 struct mlx5_ifc_mtppse_reg_bits { 11526 u8 reserved_at_0[0x18]; 11527 u8 pin[0x8]; 11528 u8 event_arm[0x1]; 11529 u8 reserved_at_21[0x1b]; 11530 u8 event_generation_mode[0x4]; 11531 u8 reserved_at_40[0x40]; 11532 }; 11533 11534 struct mlx5_ifc_mcqs_reg_bits { 11535 u8 last_index_flag[0x1]; 11536 u8 reserved_at_1[0x7]; 11537 u8 fw_device[0x8]; 11538 u8 component_index[0x10]; 11539 11540 u8 reserved_at_20[0x10]; 11541 u8 identifier[0x10]; 11542 11543 u8 reserved_at_40[0x17]; 11544 u8 component_status[0x5]; 11545 u8 component_update_state[0x4]; 11546 11547 u8 last_update_state_changer_type[0x4]; 11548 u8 last_update_state_changer_host_id[0x4]; 11549 u8 reserved_at_68[0x18]; 11550 }; 11551 11552 struct mlx5_ifc_mcqi_cap_bits { 11553 u8 supported_info_bitmask[0x20]; 11554 11555 u8 component_size[0x20]; 11556 11557 u8 max_component_size[0x20]; 11558 11559 u8 log_mcda_word_size[0x4]; 11560 u8 reserved_at_64[0xc]; 11561 u8 mcda_max_write_size[0x10]; 11562 11563 u8 rd_en[0x1]; 11564 u8 reserved_at_81[0x1]; 11565 u8 match_chip_id[0x1]; 11566 u8 match_psid[0x1]; 11567 u8 check_user_timestamp[0x1]; 11568 u8 match_base_guid_mac[0x1]; 11569 u8 reserved_at_86[0x1a]; 11570 }; 11571 11572 struct mlx5_ifc_mcqi_version_bits { 11573 u8 reserved_at_0[0x2]; 11574 u8 build_time_valid[0x1]; 11575 u8 user_defined_time_valid[0x1]; 11576 u8 reserved_at_4[0x14]; 11577 u8 version_string_length[0x8]; 11578 11579 u8 version[0x20]; 11580 11581 u8 build_time[0x40]; 11582 11583 u8 user_defined_time[0x40]; 11584 11585 u8 build_tool_version[0x20]; 11586 11587 u8 reserved_at_e0[0x20]; 11588 11589 u8 version_string[92][0x8]; 11590 }; 11591 11592 struct mlx5_ifc_mcqi_activation_method_bits { 11593 u8 pending_server_ac_power_cycle[0x1]; 11594 u8 pending_server_dc_power_cycle[0x1]; 11595 u8 pending_server_reboot[0x1]; 11596 u8 pending_fw_reset[0x1]; 11597 u8 auto_activate[0x1]; 11598 u8 all_hosts_sync[0x1]; 11599 u8 device_hw_reset[0x1]; 11600 u8 reserved_at_7[0x19]; 11601 }; 11602 11603 union mlx5_ifc_mcqi_reg_data_bits { 11604 struct mlx5_ifc_mcqi_cap_bits mcqi_caps; 11605 struct mlx5_ifc_mcqi_version_bits mcqi_version; 11606 struct mlx5_ifc_mcqi_activation_method_bits mcqi_activation_mathod; 11607 }; 11608 11609 struct mlx5_ifc_mcqi_reg_bits { 11610 u8 read_pending_component[0x1]; 11611 u8 reserved_at_1[0xf]; 11612 u8 component_index[0x10]; 11613 11614 u8 reserved_at_20[0x20]; 11615 11616 u8 reserved_at_40[0x1b]; 11617 u8 info_type[0x5]; 11618 11619 u8 info_size[0x20]; 11620 11621 u8 offset[0x20]; 11622 11623 u8 reserved_at_a0[0x10]; 11624 u8 data_size[0x10]; 11625 11626 union mlx5_ifc_mcqi_reg_data_bits data[]; 11627 }; 11628 11629 struct mlx5_ifc_mcc_reg_bits { 11630 u8 reserved_at_0[0x4]; 11631 u8 time_elapsed_since_last_cmd[0xc]; 11632 u8 reserved_at_10[0x8]; 11633 u8 instruction[0x8]; 11634 11635 u8 reserved_at_20[0x10]; 11636 u8 component_index[0x10]; 11637 11638 u8 reserved_at_40[0x8]; 11639 u8 update_handle[0x18]; 11640 11641 u8 handle_owner_type[0x4]; 11642 u8 handle_owner_host_id[0x4]; 11643 u8 reserved_at_68[0x1]; 11644 u8 control_progress[0x7]; 11645 u8 error_code[0x8]; 11646 u8 reserved_at_78[0x4]; 11647 u8 control_state[0x4]; 11648 11649 u8 component_size[0x20]; 11650 11651 u8 reserved_at_a0[0x60]; 11652 }; 11653 11654 struct mlx5_ifc_mcda_reg_bits { 11655 u8 reserved_at_0[0x8]; 11656 u8 update_handle[0x18]; 11657 11658 u8 offset[0x20]; 11659 11660 u8 reserved_at_40[0x10]; 11661 u8 size[0x10]; 11662 11663 u8 reserved_at_60[0x20]; 11664 11665 u8 data[][0x20]; 11666 }; 11667 11668 enum { 11669 MLX5_MFRL_REG_PCI_RESET_METHOD_LINK_TOGGLE = 0, 11670 MLX5_MFRL_REG_PCI_RESET_METHOD_HOT_RESET = 1, 11671 }; 11672 11673 enum { 11674 MLX5_MFRL_REG_RESET_STATE_IDLE = 0, 11675 MLX5_MFRL_REG_RESET_STATE_IN_NEGOTIATION = 1, 11676 MLX5_MFRL_REG_RESET_STATE_RESET_IN_PROGRESS = 2, 11677 MLX5_MFRL_REG_RESET_STATE_NEG_TIMEOUT = 3, 11678 MLX5_MFRL_REG_RESET_STATE_NACK = 4, 11679 MLX5_MFRL_REG_RESET_STATE_UNLOAD_TIMEOUT = 5, 11680 }; 11681 11682 enum { 11683 MLX5_MFRL_REG_RESET_TYPE_FULL_CHIP = BIT(0), 11684 MLX5_MFRL_REG_RESET_TYPE_NET_PORT_ALIVE = BIT(1), 11685 }; 11686 11687 enum { 11688 MLX5_MFRL_REG_RESET_LEVEL0 = BIT(0), 11689 MLX5_MFRL_REG_RESET_LEVEL3 = BIT(3), 11690 MLX5_MFRL_REG_RESET_LEVEL6 = BIT(6), 11691 }; 11692 11693 struct mlx5_ifc_mfrl_reg_bits { 11694 u8 reserved_at_0[0x20]; 11695 11696 u8 reserved_at_20[0x2]; 11697 u8 pci_sync_for_fw_update_start[0x1]; 11698 u8 pci_sync_for_fw_update_resp[0x2]; 11699 u8 rst_type_sel[0x3]; 11700 u8 pci_reset_req_method[0x3]; 11701 u8 reserved_at_2b[0x1]; 11702 u8 reset_state[0x4]; 11703 u8 reset_type[0x8]; 11704 u8 reset_level[0x8]; 11705 }; 11706 11707 struct mlx5_ifc_mirc_reg_bits { 11708 u8 reserved_at_0[0x18]; 11709 u8 status_code[0x8]; 11710 11711 u8 reserved_at_20[0x20]; 11712 }; 11713 11714 struct mlx5_ifc_pddr_monitor_opcode_bits { 11715 u8 reserved_at_0[0x10]; 11716 u8 monitor_opcode[0x10]; 11717 }; 11718 11719 union mlx5_ifc_pddr_troubleshooting_page_status_opcode_auto_bits { 11720 struct mlx5_ifc_pddr_monitor_opcode_bits pddr_monitor_opcode; 11721 u8 reserved_at_0[0x20]; 11722 }; 11723 11724 enum { 11725 /* Monitor opcodes */ 11726 MLX5_PDDR_REG_TRBLSH_GROUP_OPCODE_MONITOR = 0x0, 11727 }; 11728 11729 struct mlx5_ifc_pddr_troubleshooting_page_bits { 11730 u8 reserved_at_0[0x10]; 11731 u8 group_opcode[0x10]; 11732 11733 union mlx5_ifc_pddr_troubleshooting_page_status_opcode_auto_bits status_opcode; 11734 11735 u8 reserved_at_40[0x20]; 11736 11737 u8 status_message[59][0x20]; 11738 }; 11739 11740 union mlx5_ifc_pddr_reg_page_data_auto_bits { 11741 struct mlx5_ifc_pddr_troubleshooting_page_bits pddr_troubleshooting_page; 11742 u8 reserved_at_0[0x7c0]; 11743 }; 11744 11745 enum { 11746 MLX5_PDDR_REG_PAGE_SELECT_TROUBLESHOOTING_INFO_PAGE = 0x1, 11747 }; 11748 11749 struct mlx5_ifc_pddr_reg_bits { 11750 u8 reserved_at_0[0x8]; 11751 u8 local_port[0x8]; 11752 u8 pnat[0x2]; 11753 u8 reserved_at_12[0xe]; 11754 11755 u8 reserved_at_20[0x18]; 11756 u8 page_select[0x8]; 11757 11758 union mlx5_ifc_pddr_reg_page_data_auto_bits page_data; 11759 }; 11760 11761 struct mlx5_ifc_mrtc_reg_bits { 11762 u8 time_synced[0x1]; 11763 u8 reserved_at_1[0x1f]; 11764 11765 u8 reserved_at_20[0x20]; 11766 11767 u8 time_h[0x20]; 11768 11769 u8 time_l[0x20]; 11770 }; 11771 11772 struct mlx5_ifc_mtcap_reg_bits { 11773 u8 reserved_at_0[0x19]; 11774 u8 sensor_count[0x7]; 11775 11776 u8 reserved_at_20[0x20]; 11777 11778 u8 sensor_map[0x40]; 11779 }; 11780 11781 struct mlx5_ifc_mtmp_reg_bits { 11782 u8 reserved_at_0[0x14]; 11783 u8 sensor_index[0xc]; 11784 11785 u8 reserved_at_20[0x10]; 11786 u8 temperature[0x10]; 11787 11788 u8 mte[0x1]; 11789 u8 mtr[0x1]; 11790 u8 reserved_at_42[0xe]; 11791 u8 max_temperature[0x10]; 11792 11793 u8 tee[0x2]; 11794 u8 reserved_at_62[0xe]; 11795 u8 temp_threshold_hi[0x10]; 11796 11797 u8 reserved_at_80[0x10]; 11798 u8 temp_threshold_lo[0x10]; 11799 11800 u8 reserved_at_a0[0x20]; 11801 11802 u8 sensor_name_hi[0x20]; 11803 u8 sensor_name_lo[0x20]; 11804 }; 11805 11806 struct mlx5_ifc_mtptm_reg_bits { 11807 u8 reserved_at_0[0x10]; 11808 u8 psta[0x1]; 11809 u8 reserved_at_11[0xf]; 11810 11811 u8 reserved_at_20[0x60]; 11812 }; 11813 11814 enum { 11815 MLX5_MTCTR_REQUEST_NOP = 0x0, 11816 MLX5_MTCTR_REQUEST_PTM_ROOT_CLOCK = 0x1, 11817 MLX5_MTCTR_REQUEST_FREE_RUNNING_COUNTER = 0x2, 11818 MLX5_MTCTR_REQUEST_REAL_TIME_CLOCK = 0x3, 11819 }; 11820 11821 struct mlx5_ifc_mtctr_reg_bits { 11822 u8 first_clock_timestamp_request[0x8]; 11823 u8 second_clock_timestamp_request[0x8]; 11824 u8 reserved_at_10[0x10]; 11825 11826 u8 first_clock_valid[0x1]; 11827 u8 second_clock_valid[0x1]; 11828 u8 reserved_at_22[0x1e]; 11829 11830 u8 first_clock_timestamp[0x40]; 11831 u8 second_clock_timestamp[0x40]; 11832 }; 11833 11834 struct mlx5_ifc_bin_range_layout_bits { 11835 u8 reserved_at_0[0xa]; 11836 u8 high_val[0x6]; 11837 u8 reserved_at_10[0xa]; 11838 u8 low_val[0x6]; 11839 }; 11840 11841 struct mlx5_ifc_pphcr_reg_bits { 11842 u8 active_hist_type[0x4]; 11843 u8 reserved_at_4[0x4]; 11844 u8 local_port[0x8]; 11845 u8 reserved_at_10[0x10]; 11846 11847 u8 reserved_at_20[0x8]; 11848 u8 num_of_bins[0x8]; 11849 u8 reserved_at_30[0x10]; 11850 11851 u8 reserved_at_40[0x40]; 11852 11853 struct mlx5_ifc_bin_range_layout_bits bin_range[16]; 11854 }; 11855 11856 union mlx5_ifc_ports_control_registers_document_bits { 11857 struct mlx5_ifc_bufferx_reg_bits bufferx_reg; 11858 struct mlx5_ifc_eth_2819_cntrs_grp_data_layout_bits eth_2819_cntrs_grp_data_layout; 11859 struct mlx5_ifc_eth_2863_cntrs_grp_data_layout_bits eth_2863_cntrs_grp_data_layout; 11860 struct mlx5_ifc_eth_3635_cntrs_grp_data_layout_bits eth_3635_cntrs_grp_data_layout; 11861 struct mlx5_ifc_eth_802_3_cntrs_grp_data_layout_bits eth_802_3_cntrs_grp_data_layout; 11862 struct mlx5_ifc_eth_extended_cntrs_grp_data_layout_bits eth_extended_cntrs_grp_data_layout; 11863 struct mlx5_ifc_eth_per_prio_grp_data_layout_bits eth_per_prio_grp_data_layout; 11864 struct mlx5_ifc_eth_per_tc_prio_grp_data_layout_bits eth_per_tc_prio_grp_data_layout; 11865 struct mlx5_ifc_eth_per_tc_congest_prio_grp_data_layout_bits eth_per_tc_congest_prio_grp_data_layout; 11866 struct mlx5_ifc_lane_2_module_mapping_bits lane_2_module_mapping; 11867 struct mlx5_ifc_pamp_reg_bits pamp_reg; 11868 struct mlx5_ifc_paos_reg_bits paos_reg; 11869 struct mlx5_ifc_pcap_reg_bits pcap_reg; 11870 struct mlx5_ifc_pddr_monitor_opcode_bits pddr_monitor_opcode; 11871 struct mlx5_ifc_pddr_reg_bits pddr_reg; 11872 struct mlx5_ifc_pddr_troubleshooting_page_bits pddr_troubleshooting_page; 11873 struct mlx5_ifc_peir_reg_bits peir_reg; 11874 struct mlx5_ifc_pelc_reg_bits pelc_reg; 11875 struct mlx5_ifc_pfcc_reg_bits pfcc_reg; 11876 struct mlx5_ifc_ib_port_cntrs_grp_data_layout_bits ib_port_cntrs_grp_data_layout; 11877 struct mlx5_ifc_phys_layer_cntrs_bits phys_layer_cntrs; 11878 struct mlx5_ifc_pifr_reg_bits pifr_reg; 11879 struct mlx5_ifc_pipg_reg_bits pipg_reg; 11880 struct mlx5_ifc_plbf_reg_bits plbf_reg; 11881 struct mlx5_ifc_plib_reg_bits plib_reg; 11882 struct mlx5_ifc_plpc_reg_bits plpc_reg; 11883 struct mlx5_ifc_pmaos_reg_bits pmaos_reg; 11884 struct mlx5_ifc_pmlp_reg_bits pmlp_reg; 11885 struct mlx5_ifc_pmlpn_reg_bits pmlpn_reg; 11886 struct mlx5_ifc_pmpc_reg_bits pmpc_reg; 11887 struct mlx5_ifc_pmpe_reg_bits pmpe_reg; 11888 struct mlx5_ifc_pmpr_reg_bits pmpr_reg; 11889 struct mlx5_ifc_pmtu_reg_bits pmtu_reg; 11890 struct mlx5_ifc_ppad_reg_bits ppad_reg; 11891 struct mlx5_ifc_ppcnt_reg_bits ppcnt_reg; 11892 struct mlx5_ifc_mpein_reg_bits mpein_reg; 11893 struct mlx5_ifc_mpcnt_reg_bits mpcnt_reg; 11894 struct mlx5_ifc_pplm_reg_bits pplm_reg; 11895 struct mlx5_ifc_pplr_reg_bits pplr_reg; 11896 struct mlx5_ifc_ppsc_reg_bits ppsc_reg; 11897 struct mlx5_ifc_pqdr_reg_bits pqdr_reg; 11898 struct mlx5_ifc_pspa_reg_bits pspa_reg; 11899 struct mlx5_ifc_ptas_reg_bits ptas_reg; 11900 struct mlx5_ifc_ptys_reg_bits ptys_reg; 11901 struct mlx5_ifc_mlcr_reg_bits mlcr_reg; 11902 struct mlx5_ifc_pude_reg_bits pude_reg; 11903 struct mlx5_ifc_pvlc_reg_bits pvlc_reg; 11904 struct mlx5_ifc_slrg_reg_bits slrg_reg; 11905 struct mlx5_ifc_sltp_reg_bits sltp_reg; 11906 struct mlx5_ifc_mtpps_reg_bits mtpps_reg; 11907 struct mlx5_ifc_mtppse_reg_bits mtppse_reg; 11908 struct mlx5_ifc_fpga_access_reg_bits fpga_access_reg; 11909 struct mlx5_ifc_fpga_ctrl_bits fpga_ctrl_bits; 11910 struct mlx5_ifc_fpga_cap_bits fpga_cap_bits; 11911 struct mlx5_ifc_mcqi_reg_bits mcqi_reg; 11912 struct mlx5_ifc_mcc_reg_bits mcc_reg; 11913 struct mlx5_ifc_mcda_reg_bits mcda_reg; 11914 struct mlx5_ifc_mirc_reg_bits mirc_reg; 11915 struct mlx5_ifc_mfrl_reg_bits mfrl_reg; 11916 struct mlx5_ifc_mtutc_reg_bits mtutc_reg; 11917 struct mlx5_ifc_mrtc_reg_bits mrtc_reg; 11918 struct mlx5_ifc_mtcap_reg_bits mtcap_reg; 11919 struct mlx5_ifc_mtmp_reg_bits mtmp_reg; 11920 struct mlx5_ifc_mtptm_reg_bits mtptm_reg; 11921 struct mlx5_ifc_mtctr_reg_bits mtctr_reg; 11922 struct mlx5_ifc_pphcr_reg_bits pphcr_reg; 11923 u8 reserved_at_0[0x60e0]; 11924 }; 11925 11926 union mlx5_ifc_debug_enhancements_document_bits { 11927 struct mlx5_ifc_health_buffer_bits health_buffer; 11928 u8 reserved_at_0[0x200]; 11929 }; 11930 11931 union mlx5_ifc_uplink_pci_interface_document_bits { 11932 struct mlx5_ifc_initial_seg_bits initial_seg; 11933 u8 reserved_at_0[0x20060]; 11934 }; 11935 11936 struct mlx5_ifc_set_flow_table_root_out_bits { 11937 u8 status[0x8]; 11938 u8 reserved_at_8[0x18]; 11939 11940 u8 syndrome[0x20]; 11941 11942 u8 reserved_at_40[0x40]; 11943 }; 11944 11945 struct mlx5_ifc_set_flow_table_root_in_bits { 11946 u8 opcode[0x10]; 11947 u8 reserved_at_10[0x10]; 11948 11949 u8 reserved_at_20[0x10]; 11950 u8 op_mod[0x10]; 11951 11952 u8 other_vport[0x1]; 11953 u8 other_eswitch[0x1]; 11954 u8 reserved_at_42[0xe]; 11955 u8 vport_number[0x10]; 11956 11957 u8 reserved_at_60[0x10]; 11958 u8 eswitch_owner_vhca_id[0x10]; 11959 11960 u8 table_type[0x8]; 11961 u8 reserved_at_88[0x7]; 11962 u8 table_of_other_vport[0x1]; 11963 u8 table_vport_number[0x10]; 11964 11965 u8 reserved_at_a0[0x8]; 11966 u8 table_id[0x18]; 11967 11968 u8 reserved_at_c0[0x8]; 11969 u8 underlay_qpn[0x18]; 11970 u8 table_eswitch_owner_vhca_id_valid[0x1]; 11971 u8 reserved_at_e1[0xf]; 11972 u8 table_eswitch_owner_vhca_id[0x10]; 11973 u8 reserved_at_100[0x100]; 11974 }; 11975 11976 enum { 11977 MLX5_MODIFY_FLOW_TABLE_MISS_TABLE_ID = (1UL << 0), 11978 MLX5_MODIFY_FLOW_TABLE_LAG_NEXT_TABLE_ID = (1UL << 15), 11979 }; 11980 11981 struct mlx5_ifc_modify_flow_table_out_bits { 11982 u8 status[0x8]; 11983 u8 reserved_at_8[0x18]; 11984 11985 u8 syndrome[0x20]; 11986 11987 u8 reserved_at_40[0x40]; 11988 }; 11989 11990 struct mlx5_ifc_modify_flow_table_in_bits { 11991 u8 opcode[0x10]; 11992 u8 reserved_at_10[0x10]; 11993 11994 u8 reserved_at_20[0x10]; 11995 u8 op_mod[0x10]; 11996 11997 u8 other_vport[0x1]; 11998 u8 other_eswitch[0x1]; 11999 u8 reserved_at_42[0xe]; 12000 u8 vport_number[0x10]; 12001 12002 u8 reserved_at_60[0x10]; 12003 u8 modify_field_select[0x10]; 12004 12005 u8 table_type[0x8]; 12006 u8 reserved_at_88[0x8]; 12007 u8 eswitch_owner_vhca_id[0x10]; 12008 12009 u8 reserved_at_a0[0x8]; 12010 u8 table_id[0x18]; 12011 12012 struct mlx5_ifc_flow_table_context_bits flow_table_context; 12013 }; 12014 12015 struct mlx5_ifc_ets_tcn_config_reg_bits { 12016 u8 g[0x1]; 12017 u8 b[0x1]; 12018 u8 r[0x1]; 12019 u8 reserved_at_3[0x9]; 12020 u8 group[0x4]; 12021 u8 reserved_at_10[0x9]; 12022 u8 bw_allocation[0x7]; 12023 12024 u8 reserved_at_20[0xc]; 12025 u8 max_bw_units[0x4]; 12026 u8 max_bw_value[0x10]; 12027 }; 12028 12029 struct mlx5_ifc_ets_global_config_reg_bits { 12030 u8 reserved_at_0[0x2]; 12031 u8 r[0x1]; 12032 u8 reserved_at_3[0x1d]; 12033 12034 u8 reserved_at_20[0xc]; 12035 u8 max_bw_units[0x4]; 12036 u8 reserved_at_30[0x8]; 12037 u8 max_bw_value[0x8]; 12038 }; 12039 12040 struct mlx5_ifc_qetc_reg_bits { 12041 u8 reserved_at_0[0x8]; 12042 u8 port_number[0x8]; 12043 u8 reserved_at_10[0x30]; 12044 12045 struct mlx5_ifc_ets_tcn_config_reg_bits tc_configuration[0x8]; 12046 struct mlx5_ifc_ets_global_config_reg_bits global_configuration; 12047 }; 12048 12049 struct mlx5_ifc_qpdpm_dscp_reg_bits { 12050 u8 e[0x1]; 12051 u8 reserved_at_01[0x0b]; 12052 u8 prio[0x04]; 12053 }; 12054 12055 struct mlx5_ifc_qpdpm_reg_bits { 12056 u8 reserved_at_0[0x8]; 12057 u8 local_port[0x8]; 12058 u8 reserved_at_10[0x10]; 12059 struct mlx5_ifc_qpdpm_dscp_reg_bits dscp[64]; 12060 }; 12061 12062 struct mlx5_ifc_qpts_reg_bits { 12063 u8 reserved_at_0[0x8]; 12064 u8 local_port[0x8]; 12065 u8 reserved_at_10[0x2d]; 12066 u8 trust_state[0x3]; 12067 }; 12068 12069 struct mlx5_ifc_pptb_reg_bits { 12070 u8 reserved_at_0[0x2]; 12071 u8 mm[0x2]; 12072 u8 reserved_at_4[0x4]; 12073 u8 local_port[0x8]; 12074 u8 reserved_at_10[0x6]; 12075 u8 cm[0x1]; 12076 u8 um[0x1]; 12077 u8 pm[0x8]; 12078 12079 u8 prio_x_buff[0x20]; 12080 12081 u8 pm_msb[0x8]; 12082 u8 reserved_at_48[0x10]; 12083 u8 ctrl_buff[0x4]; 12084 u8 untagged_buff[0x4]; 12085 }; 12086 12087 struct mlx5_ifc_sbcam_reg_bits { 12088 u8 reserved_at_0[0x8]; 12089 u8 feature_group[0x8]; 12090 u8 reserved_at_10[0x8]; 12091 u8 access_reg_group[0x8]; 12092 12093 u8 reserved_at_20[0x20]; 12094 12095 u8 sb_access_reg_cap_mask[4][0x20]; 12096 12097 u8 reserved_at_c0[0x80]; 12098 12099 u8 sb_feature_cap_mask[4][0x20]; 12100 12101 u8 reserved_at_1c0[0x40]; 12102 12103 u8 cap_total_buffer_size[0x20]; 12104 12105 u8 cap_cell_size[0x10]; 12106 u8 cap_max_pg_buffers[0x8]; 12107 u8 cap_num_pool_supported[0x8]; 12108 12109 u8 reserved_at_240[0x8]; 12110 u8 cap_sbsr_stat_size[0x8]; 12111 u8 cap_max_tclass_data[0x8]; 12112 u8 cap_max_cpu_ingress_tclass_sb[0x8]; 12113 }; 12114 12115 struct mlx5_ifc_pbmc_reg_bits { 12116 u8 reserved_at_0[0x8]; 12117 u8 local_port[0x8]; 12118 u8 reserved_at_10[0x10]; 12119 12120 u8 xoff_timer_value[0x10]; 12121 u8 xoff_refresh[0x10]; 12122 12123 u8 reserved_at_40[0x9]; 12124 u8 fullness_threshold[0x7]; 12125 u8 port_buffer_size[0x10]; 12126 12127 struct mlx5_ifc_bufferx_reg_bits buffer[10]; 12128 struct mlx5_ifc_bufferx_reg_bits shared_headroom_pool; 12129 12130 u8 reserved_at_320[0x40]; 12131 }; 12132 12133 struct mlx5_ifc_sbpr_reg_bits { 12134 u8 desc[0x1]; 12135 u8 snap[0x1]; 12136 u8 reserved_at_2[0x4]; 12137 u8 dir[0x2]; 12138 u8 reserved_at_8[0x14]; 12139 u8 pool[0x4]; 12140 12141 u8 infi_size[0x1]; 12142 u8 reserved_at_21[0x7]; 12143 u8 size[0x18]; 12144 12145 u8 reserved_at_40[0x1c]; 12146 u8 mode[0x4]; 12147 12148 u8 reserved_at_60[0x8]; 12149 u8 buff_occupancy[0x18]; 12150 12151 u8 clr[0x1]; 12152 u8 reserved_at_81[0x7]; 12153 u8 max_buff_occupancy[0x18]; 12154 12155 u8 reserved_at_a0[0x8]; 12156 u8 ext_buff_occupancy[0x18]; 12157 }; 12158 12159 struct mlx5_ifc_sbcm_reg_bits { 12160 u8 desc[0x1]; 12161 u8 snap[0x1]; 12162 u8 reserved_at_2[0x6]; 12163 u8 local_port[0x8]; 12164 u8 pnat[0x2]; 12165 u8 pg_buff[0x6]; 12166 u8 reserved_at_18[0x6]; 12167 u8 dir[0x2]; 12168 12169 u8 reserved_at_20[0x1f]; 12170 u8 exc[0x1]; 12171 12172 u8 reserved_at_40[0x40]; 12173 12174 u8 reserved_at_80[0x8]; 12175 u8 buff_occupancy[0x18]; 12176 12177 u8 clr[0x1]; 12178 u8 reserved_at_a1[0x7]; 12179 u8 max_buff_occupancy[0x18]; 12180 12181 u8 reserved_at_c0[0x8]; 12182 u8 min_buff[0x18]; 12183 12184 u8 infi_max[0x1]; 12185 u8 reserved_at_e1[0x7]; 12186 u8 max_buff[0x18]; 12187 12188 u8 reserved_at_100[0x20]; 12189 12190 u8 reserved_at_120[0x1c]; 12191 u8 pool[0x4]; 12192 }; 12193 12194 struct mlx5_ifc_qtct_reg_bits { 12195 u8 reserved_at_0[0x8]; 12196 u8 port_number[0x8]; 12197 u8 reserved_at_10[0xd]; 12198 u8 prio[0x3]; 12199 12200 u8 reserved_at_20[0x1d]; 12201 u8 tclass[0x3]; 12202 }; 12203 12204 struct mlx5_ifc_mcia_reg_bits { 12205 u8 l[0x1]; 12206 u8 reserved_at_1[0x7]; 12207 u8 module[0x8]; 12208 u8 reserved_at_10[0x8]; 12209 u8 status[0x8]; 12210 12211 u8 i2c_device_address[0x8]; 12212 u8 page_number[0x8]; 12213 u8 device_address[0x10]; 12214 12215 u8 reserved_at_40[0x10]; 12216 u8 size[0x10]; 12217 12218 u8 reserved_at_60[0x20]; 12219 12220 u8 dwords[0x400]; 12221 }; 12222 12223 struct mlx5_ifc_dcbx_param_bits { 12224 u8 dcbx_cee_cap[0x1]; 12225 u8 dcbx_ieee_cap[0x1]; 12226 u8 dcbx_standby_cap[0x1]; 12227 u8 reserved_at_3[0x5]; 12228 u8 port_number[0x8]; 12229 u8 reserved_at_10[0xa]; 12230 u8 max_application_table_size[6]; 12231 u8 reserved_at_20[0x15]; 12232 u8 version_oper[0x3]; 12233 u8 reserved_at_38[5]; 12234 u8 version_admin[0x3]; 12235 u8 willing_admin[0x1]; 12236 u8 reserved_at_41[0x3]; 12237 u8 pfc_cap_oper[0x4]; 12238 u8 reserved_at_48[0x4]; 12239 u8 pfc_cap_admin[0x4]; 12240 u8 reserved_at_50[0x4]; 12241 u8 num_of_tc_oper[0x4]; 12242 u8 reserved_at_58[0x4]; 12243 u8 num_of_tc_admin[0x4]; 12244 u8 remote_willing[0x1]; 12245 u8 reserved_at_61[3]; 12246 u8 remote_pfc_cap[4]; 12247 u8 reserved_at_68[0x14]; 12248 u8 remote_num_of_tc[0x4]; 12249 u8 reserved_at_80[0x18]; 12250 u8 error[0x8]; 12251 u8 reserved_at_a0[0x160]; 12252 }; 12253 12254 enum { 12255 MLX5_LAG_PORT_SELECT_MODE_QUEUE_AFFINITY = 0, 12256 MLX5_LAG_PORT_SELECT_MODE_PORT_SELECT_FT = 1, 12257 MLX5_LAG_PORT_SELECT_MODE_PORT_SELECT_MPESW = 2, 12258 }; 12259 12260 struct mlx5_ifc_lagc_bits { 12261 u8 fdb_selection_mode[0x1]; 12262 u8 reserved_at_1[0x14]; 12263 u8 port_select_mode[0x3]; 12264 u8 reserved_at_18[0x5]; 12265 u8 lag_state[0x3]; 12266 12267 u8 reserved_at_20[0xc]; 12268 u8 active_port[0x4]; 12269 u8 reserved_at_30[0x4]; 12270 u8 tx_remap_affinity_2[0x4]; 12271 u8 reserved_at_38[0x4]; 12272 u8 tx_remap_affinity_1[0x4]; 12273 }; 12274 12275 struct mlx5_ifc_create_lag_out_bits { 12276 u8 status[0x8]; 12277 u8 reserved_at_8[0x18]; 12278 12279 u8 syndrome[0x20]; 12280 12281 u8 reserved_at_40[0x40]; 12282 }; 12283 12284 struct mlx5_ifc_create_lag_in_bits { 12285 u8 opcode[0x10]; 12286 u8 reserved_at_10[0x10]; 12287 12288 u8 reserved_at_20[0x10]; 12289 u8 op_mod[0x10]; 12290 12291 struct mlx5_ifc_lagc_bits ctx; 12292 }; 12293 12294 struct mlx5_ifc_modify_lag_out_bits { 12295 u8 status[0x8]; 12296 u8 reserved_at_8[0x18]; 12297 12298 u8 syndrome[0x20]; 12299 12300 u8 reserved_at_40[0x40]; 12301 }; 12302 12303 struct mlx5_ifc_modify_lag_in_bits { 12304 u8 opcode[0x10]; 12305 u8 reserved_at_10[0x10]; 12306 12307 u8 reserved_at_20[0x10]; 12308 u8 op_mod[0x10]; 12309 12310 u8 reserved_at_40[0x20]; 12311 u8 field_select[0x20]; 12312 12313 struct mlx5_ifc_lagc_bits ctx; 12314 }; 12315 12316 struct mlx5_ifc_query_lag_out_bits { 12317 u8 status[0x8]; 12318 u8 reserved_at_8[0x18]; 12319 12320 u8 syndrome[0x20]; 12321 12322 struct mlx5_ifc_lagc_bits ctx; 12323 }; 12324 12325 struct mlx5_ifc_query_lag_in_bits { 12326 u8 opcode[0x10]; 12327 u8 reserved_at_10[0x10]; 12328 12329 u8 reserved_at_20[0x10]; 12330 u8 op_mod[0x10]; 12331 12332 u8 reserved_at_40[0x40]; 12333 }; 12334 12335 struct mlx5_ifc_destroy_lag_out_bits { 12336 u8 status[0x8]; 12337 u8 reserved_at_8[0x18]; 12338 12339 u8 syndrome[0x20]; 12340 12341 u8 reserved_at_40[0x40]; 12342 }; 12343 12344 struct mlx5_ifc_destroy_lag_in_bits { 12345 u8 opcode[0x10]; 12346 u8 reserved_at_10[0x10]; 12347 12348 u8 reserved_at_20[0x10]; 12349 u8 op_mod[0x10]; 12350 12351 u8 reserved_at_40[0x40]; 12352 }; 12353 12354 struct mlx5_ifc_create_vport_lag_out_bits { 12355 u8 status[0x8]; 12356 u8 reserved_at_8[0x18]; 12357 12358 u8 syndrome[0x20]; 12359 12360 u8 reserved_at_40[0x40]; 12361 }; 12362 12363 struct mlx5_ifc_create_vport_lag_in_bits { 12364 u8 opcode[0x10]; 12365 u8 reserved_at_10[0x10]; 12366 12367 u8 reserved_at_20[0x10]; 12368 u8 op_mod[0x10]; 12369 12370 u8 reserved_at_40[0x40]; 12371 }; 12372 12373 struct mlx5_ifc_destroy_vport_lag_out_bits { 12374 u8 status[0x8]; 12375 u8 reserved_at_8[0x18]; 12376 12377 u8 syndrome[0x20]; 12378 12379 u8 reserved_at_40[0x40]; 12380 }; 12381 12382 struct mlx5_ifc_destroy_vport_lag_in_bits { 12383 u8 opcode[0x10]; 12384 u8 reserved_at_10[0x10]; 12385 12386 u8 reserved_at_20[0x10]; 12387 u8 op_mod[0x10]; 12388 12389 u8 reserved_at_40[0x40]; 12390 }; 12391 12392 enum { 12393 MLX5_MODIFY_MEMIC_OP_MOD_ALLOC, 12394 MLX5_MODIFY_MEMIC_OP_MOD_DEALLOC, 12395 }; 12396 12397 struct mlx5_ifc_modify_memic_in_bits { 12398 u8 opcode[0x10]; 12399 u8 uid[0x10]; 12400 12401 u8 reserved_at_20[0x10]; 12402 u8 op_mod[0x10]; 12403 12404 u8 reserved_at_40[0x20]; 12405 12406 u8 reserved_at_60[0x18]; 12407 u8 memic_operation_type[0x8]; 12408 12409 u8 memic_start_addr[0x40]; 12410 12411 u8 reserved_at_c0[0x140]; 12412 }; 12413 12414 struct mlx5_ifc_modify_memic_out_bits { 12415 u8 status[0x8]; 12416 u8 reserved_at_8[0x18]; 12417 12418 u8 syndrome[0x20]; 12419 12420 u8 reserved_at_40[0x40]; 12421 12422 u8 memic_operation_addr[0x40]; 12423 12424 u8 reserved_at_c0[0x140]; 12425 }; 12426 12427 struct mlx5_ifc_alloc_memic_in_bits { 12428 u8 opcode[0x10]; 12429 u8 reserved_at_10[0x10]; 12430 12431 u8 reserved_at_20[0x10]; 12432 u8 op_mod[0x10]; 12433 12434 u8 reserved_at_30[0x20]; 12435 12436 u8 reserved_at_40[0x18]; 12437 u8 log_memic_addr_alignment[0x8]; 12438 12439 u8 range_start_addr[0x40]; 12440 12441 u8 range_size[0x20]; 12442 12443 u8 memic_size[0x20]; 12444 }; 12445 12446 struct mlx5_ifc_alloc_memic_out_bits { 12447 u8 status[0x8]; 12448 u8 reserved_at_8[0x18]; 12449 12450 u8 syndrome[0x20]; 12451 12452 u8 memic_start_addr[0x40]; 12453 }; 12454 12455 struct mlx5_ifc_dealloc_memic_in_bits { 12456 u8 opcode[0x10]; 12457 u8 reserved_at_10[0x10]; 12458 12459 u8 reserved_at_20[0x10]; 12460 u8 op_mod[0x10]; 12461 12462 u8 reserved_at_40[0x40]; 12463 12464 u8 memic_start_addr[0x40]; 12465 12466 u8 memic_size[0x20]; 12467 12468 u8 reserved_at_e0[0x20]; 12469 }; 12470 12471 struct mlx5_ifc_dealloc_memic_out_bits { 12472 u8 status[0x8]; 12473 u8 reserved_at_8[0x18]; 12474 12475 u8 syndrome[0x20]; 12476 12477 u8 reserved_at_40[0x40]; 12478 }; 12479 12480 struct mlx5_ifc_umem_bits { 12481 u8 reserved_at_0[0x80]; 12482 12483 u8 ats[0x1]; 12484 u8 reserved_at_81[0x1a]; 12485 u8 log_page_size[0x5]; 12486 12487 u8 page_offset[0x20]; 12488 12489 u8 num_of_mtt[0x40]; 12490 12491 struct mlx5_ifc_mtt_bits mtt[]; 12492 }; 12493 12494 struct mlx5_ifc_uctx_bits { 12495 u8 cap[0x20]; 12496 12497 u8 reserved_at_20[0x160]; 12498 }; 12499 12500 struct mlx5_ifc_sw_icm_bits { 12501 u8 modify_field_select[0x40]; 12502 12503 u8 reserved_at_40[0x18]; 12504 u8 log_sw_icm_size[0x8]; 12505 12506 u8 reserved_at_60[0x20]; 12507 12508 u8 sw_icm_start_addr[0x40]; 12509 12510 u8 reserved_at_c0[0x140]; 12511 }; 12512 12513 struct mlx5_ifc_geneve_tlv_option_bits { 12514 u8 modify_field_select[0x40]; 12515 12516 u8 reserved_at_40[0x18]; 12517 u8 geneve_option_fte_index[0x8]; 12518 12519 u8 option_class[0x10]; 12520 u8 option_type[0x8]; 12521 u8 reserved_at_78[0x3]; 12522 u8 option_data_length[0x5]; 12523 12524 u8 reserved_at_80[0x180]; 12525 }; 12526 12527 struct mlx5_ifc_create_umem_in_bits { 12528 u8 opcode[0x10]; 12529 u8 uid[0x10]; 12530 12531 u8 reserved_at_20[0x10]; 12532 u8 op_mod[0x10]; 12533 12534 u8 reserved_at_40[0x40]; 12535 12536 struct mlx5_ifc_umem_bits umem; 12537 }; 12538 12539 struct mlx5_ifc_create_umem_out_bits { 12540 u8 status[0x8]; 12541 u8 reserved_at_8[0x18]; 12542 12543 u8 syndrome[0x20]; 12544 12545 u8 reserved_at_40[0x8]; 12546 u8 umem_id[0x18]; 12547 12548 u8 reserved_at_60[0x20]; 12549 }; 12550 12551 struct mlx5_ifc_destroy_umem_in_bits { 12552 u8 opcode[0x10]; 12553 u8 uid[0x10]; 12554 12555 u8 reserved_at_20[0x10]; 12556 u8 op_mod[0x10]; 12557 12558 u8 reserved_at_40[0x8]; 12559 u8 umem_id[0x18]; 12560 12561 u8 reserved_at_60[0x20]; 12562 }; 12563 12564 struct mlx5_ifc_destroy_umem_out_bits { 12565 u8 status[0x8]; 12566 u8 reserved_at_8[0x18]; 12567 12568 u8 syndrome[0x20]; 12569 12570 u8 reserved_at_40[0x40]; 12571 }; 12572 12573 struct mlx5_ifc_create_uctx_in_bits { 12574 u8 opcode[0x10]; 12575 u8 reserved_at_10[0x10]; 12576 12577 u8 reserved_at_20[0x10]; 12578 u8 op_mod[0x10]; 12579 12580 u8 reserved_at_40[0x40]; 12581 12582 struct mlx5_ifc_uctx_bits uctx; 12583 }; 12584 12585 struct mlx5_ifc_create_uctx_out_bits { 12586 u8 status[0x8]; 12587 u8 reserved_at_8[0x18]; 12588 12589 u8 syndrome[0x20]; 12590 12591 u8 reserved_at_40[0x10]; 12592 u8 uid[0x10]; 12593 12594 u8 reserved_at_60[0x20]; 12595 }; 12596 12597 struct mlx5_ifc_destroy_uctx_in_bits { 12598 u8 opcode[0x10]; 12599 u8 reserved_at_10[0x10]; 12600 12601 u8 reserved_at_20[0x10]; 12602 u8 op_mod[0x10]; 12603 12604 u8 reserved_at_40[0x10]; 12605 u8 uid[0x10]; 12606 12607 u8 reserved_at_60[0x20]; 12608 }; 12609 12610 struct mlx5_ifc_destroy_uctx_out_bits { 12611 u8 status[0x8]; 12612 u8 reserved_at_8[0x18]; 12613 12614 u8 syndrome[0x20]; 12615 12616 u8 reserved_at_40[0x40]; 12617 }; 12618 12619 struct mlx5_ifc_create_sw_icm_in_bits { 12620 struct mlx5_ifc_general_obj_in_cmd_hdr_bits hdr; 12621 struct mlx5_ifc_sw_icm_bits sw_icm; 12622 }; 12623 12624 struct mlx5_ifc_create_geneve_tlv_option_in_bits { 12625 struct mlx5_ifc_general_obj_in_cmd_hdr_bits hdr; 12626 struct mlx5_ifc_geneve_tlv_option_bits geneve_tlv_opt; 12627 }; 12628 12629 struct mlx5_ifc_mtrc_string_db_param_bits { 12630 u8 string_db_base_address[0x20]; 12631 12632 u8 reserved_at_20[0x8]; 12633 u8 string_db_size[0x18]; 12634 }; 12635 12636 struct mlx5_ifc_mtrc_cap_bits { 12637 u8 trace_owner[0x1]; 12638 u8 trace_to_memory[0x1]; 12639 u8 reserved_at_2[0x4]; 12640 u8 trc_ver[0x2]; 12641 u8 reserved_at_8[0x14]; 12642 u8 num_string_db[0x4]; 12643 12644 u8 first_string_trace[0x8]; 12645 u8 num_string_trace[0x8]; 12646 u8 reserved_at_30[0x28]; 12647 12648 u8 log_max_trace_buffer_size[0x8]; 12649 12650 u8 reserved_at_60[0x20]; 12651 12652 struct mlx5_ifc_mtrc_string_db_param_bits string_db_param[8]; 12653 12654 u8 reserved_at_280[0x180]; 12655 }; 12656 12657 struct mlx5_ifc_mtrc_conf_bits { 12658 u8 reserved_at_0[0x1c]; 12659 u8 trace_mode[0x4]; 12660 u8 reserved_at_20[0x18]; 12661 u8 log_trace_buffer_size[0x8]; 12662 u8 trace_mkey[0x20]; 12663 u8 reserved_at_60[0x3a0]; 12664 }; 12665 12666 struct mlx5_ifc_mtrc_stdb_bits { 12667 u8 string_db_index[0x4]; 12668 u8 reserved_at_4[0x4]; 12669 u8 read_size[0x18]; 12670 u8 start_offset[0x20]; 12671 u8 string_db_data[]; 12672 }; 12673 12674 struct mlx5_ifc_mtrc_ctrl_bits { 12675 u8 trace_status[0x2]; 12676 u8 reserved_at_2[0x2]; 12677 u8 arm_event[0x1]; 12678 u8 reserved_at_5[0xb]; 12679 u8 modify_field_select[0x10]; 12680 u8 reserved_at_20[0x2b]; 12681 u8 current_timestamp52_32[0x15]; 12682 u8 current_timestamp31_0[0x20]; 12683 u8 reserved_at_80[0x180]; 12684 }; 12685 12686 struct mlx5_ifc_host_params_context_bits { 12687 u8 host_number[0x8]; 12688 u8 reserved_at_8[0x5]; 12689 u8 host_pf_not_exist[0x1]; 12690 u8 reserved_at_14[0x1]; 12691 u8 host_pf_disabled[0x1]; 12692 u8 host_num_of_vfs[0x10]; 12693 12694 u8 host_total_vfs[0x10]; 12695 u8 host_pci_bus[0x10]; 12696 12697 u8 reserved_at_40[0x10]; 12698 u8 host_pci_device[0x10]; 12699 12700 u8 reserved_at_60[0x10]; 12701 u8 host_pci_function[0x10]; 12702 12703 u8 reserved_at_80[0x180]; 12704 }; 12705 12706 enum mlx5_ifc_vhca_state { 12707 MLX5_VHCA_STATE_INVALID = 0x0, 12708 MLX5_VHCA_STATE_ALLOCATED = 0x1, 12709 MLX5_VHCA_STATE_ACTIVE = 0x2, 12710 MLX5_VHCA_STATE_IN_USE = 0x3, 12711 MLX5_VHCA_STATE_TEARDOWN_REQUEST = 0x4, 12712 }; 12713 12714 enum { 12715 MLX5_PCI_PF_TYPE_EXTERNAL_HOST_PF = 0x0, 12716 MLX5_PCI_PF_TYPE_SATELLITE_PF = 0x1, 12717 }; 12718 12719 struct mlx5_ifc_network_function_params_bits { 12720 u8 host_number[0x8]; 12721 u8 pci_pf_type[0x4]; 12722 u8 reserved_at_c[0x4]; 12723 u8 pci_num_vfs[0x10]; 12724 12725 u8 pci_total_vfs[0x10]; 12726 u8 pci_bus[0x8]; 12727 u8 pci_device_function[0x8]; 12728 12729 u8 vhca_id[0x10]; 12730 u8 vhca_state[0x4]; 12731 u8 reserved_at_54[0xc]; 12732 12733 u8 reserved_at_60[0xa]; 12734 u8 esw_vport_manual[0x1]; 12735 u8 pci_bus_assigned[0x1]; 12736 u8 pci_vf_info_valid[0x1]; 12737 u8 reserved_at_6d[0x13]; 12738 12739 u8 pci_vf_stride[0x10]; 12740 u8 pci_first_vf_offset[0x10]; 12741 12742 u8 reserved_at_a0[0x160]; 12743 }; 12744 12745 union mlx5_ifc_net_function_params_bits { 12746 struct mlx5_ifc_host_params_context_bits host_params_context; 12747 struct mlx5_ifc_network_function_params_bits network_function_params; 12748 }; 12749 12750 enum { 12751 MLX5_QUERY_ESW_FUNC_OP_MOD_LAYOUT_V1 = BIT(14), 12752 }; 12753 12754 struct mlx5_ifc_query_esw_functions_in_bits { 12755 u8 opcode[0x10]; 12756 u8 reserved_at_10[0x10]; 12757 12758 u8 reserved_at_20[0x10]; 12759 u8 op_mod[0x10]; 12760 12761 u8 reserved_at_40[0x40]; 12762 }; 12763 12764 struct mlx5_ifc_query_esw_functions_out_bits { 12765 u8 status[0x8]; 12766 u8 reserved_at_8[0x18]; 12767 12768 u8 syndrome[0x20]; 12769 12770 u8 reserved_at_40[0x20]; 12771 12772 u8 net_function_num[0x8]; 12773 u8 reserved_at_68[0x18]; 12774 12775 union { 12776 u8 reserved_at_80[0x380]; 12777 DECLARE_FLEX_ARRAY(union mlx5_ifc_net_function_params_bits, 12778 net_function_params); 12779 }; 12780 }; 12781 12782 struct mlx5_ifc_sf_partition_bits { 12783 u8 reserved_at_0[0x10]; 12784 u8 log_num_sf[0x8]; 12785 u8 log_sf_bar_size[0x8]; 12786 }; 12787 12788 struct mlx5_ifc_query_sf_partitions_out_bits { 12789 u8 status[0x8]; 12790 u8 reserved_at_8[0x18]; 12791 12792 u8 syndrome[0x20]; 12793 12794 u8 reserved_at_40[0x18]; 12795 u8 num_sf_partitions[0x8]; 12796 12797 u8 reserved_at_60[0x20]; 12798 12799 struct mlx5_ifc_sf_partition_bits sf_partition[]; 12800 }; 12801 12802 struct mlx5_ifc_query_sf_partitions_in_bits { 12803 u8 opcode[0x10]; 12804 u8 reserved_at_10[0x10]; 12805 12806 u8 reserved_at_20[0x10]; 12807 u8 op_mod[0x10]; 12808 12809 u8 reserved_at_40[0x40]; 12810 }; 12811 12812 struct mlx5_ifc_dealloc_sf_out_bits { 12813 u8 status[0x8]; 12814 u8 reserved_at_8[0x18]; 12815 12816 u8 syndrome[0x20]; 12817 12818 u8 reserved_at_40[0x40]; 12819 }; 12820 12821 struct mlx5_ifc_dealloc_sf_in_bits { 12822 u8 opcode[0x10]; 12823 u8 reserved_at_10[0x10]; 12824 12825 u8 reserved_at_20[0x10]; 12826 u8 op_mod[0x10]; 12827 12828 u8 reserved_at_40[0x10]; 12829 u8 function_id[0x10]; 12830 12831 u8 reserved_at_60[0x20]; 12832 }; 12833 12834 struct mlx5_ifc_alloc_sf_out_bits { 12835 u8 status[0x8]; 12836 u8 reserved_at_8[0x18]; 12837 12838 u8 syndrome[0x20]; 12839 12840 u8 reserved_at_40[0x40]; 12841 }; 12842 12843 struct mlx5_ifc_alloc_sf_in_bits { 12844 u8 opcode[0x10]; 12845 u8 reserved_at_10[0x10]; 12846 12847 u8 reserved_at_20[0x10]; 12848 u8 op_mod[0x10]; 12849 12850 u8 reserved_at_40[0x10]; 12851 u8 function_id[0x10]; 12852 12853 u8 reserved_at_60[0x20]; 12854 }; 12855 12856 struct mlx5_ifc_affiliated_event_header_bits { 12857 u8 reserved_at_0[0x10]; 12858 u8 obj_type[0x10]; 12859 12860 u8 obj_id[0x20]; 12861 }; 12862 12863 enum { 12864 MLX5_GENERAL_OBJECT_TYPES_ENCRYPTION_KEY = 0xc, 12865 MLX5_GENERAL_OBJECT_TYPES_IPSEC = 0x13, 12866 MLX5_GENERAL_OBJECT_TYPES_SAMPLER = 0x20, 12867 MLX5_GENERAL_OBJECT_TYPES_FLOW_METER_ASO = 0x24, 12868 MLX5_GENERAL_OBJECT_TYPES_MACSEC = 0x27, 12869 MLX5_GENERAL_OBJECT_TYPES_INT_KEK = 0x47, 12870 MLX5_GENERAL_OBJECT_TYPES_RDMA_CTRL = 0x53, 12871 MLX5_GENERAL_OBJECT_TYPES_PCIE_CONG_EVENT = 0x58, 12872 MLX5_GENERAL_OBJECT_TYPES_FLOW_TABLE_ALIAS = 0xff15, 12873 }; 12874 12875 enum { 12876 MLX5_HCA_CAP_GENERAL_OBJECT_TYPES_ENCRYPTION_KEY = 12877 BIT_ULL(MLX5_GENERAL_OBJECT_TYPES_ENCRYPTION_KEY), 12878 MLX5_HCA_CAP_GENERAL_OBJECT_TYPES_IPSEC = 12879 BIT_ULL(MLX5_GENERAL_OBJECT_TYPES_IPSEC), 12880 MLX5_HCA_CAP_GENERAL_OBJECT_TYPES_SAMPLER = 12881 BIT_ULL(MLX5_GENERAL_OBJECT_TYPES_SAMPLER), 12882 MLX5_HCA_CAP_GENERAL_OBJECT_TYPES_FLOW_METER_ASO = 12883 BIT_ULL(MLX5_GENERAL_OBJECT_TYPES_FLOW_METER_ASO), 12884 }; 12885 12886 enum { 12887 MLX5_HCA_CAP_2_GENERAL_OBJECT_TYPES_RDMA_CTRL = 12888 BIT_ULL(MLX5_GENERAL_OBJECT_TYPES_RDMA_CTRL - 0x40), 12889 MLX5_HCA_CAP_2_GENERAL_OBJECT_TYPES_PCIE_CONG_EVENT = 12890 BIT_ULL(MLX5_GENERAL_OBJECT_TYPES_PCIE_CONG_EVENT - 0x40), 12891 }; 12892 12893 enum { 12894 MLX5_IPSEC_OBJECT_ICV_LEN_16B, 12895 }; 12896 12897 enum { 12898 MLX5_IPSEC_ASO_REG_C_0_1 = 0x0, 12899 MLX5_IPSEC_ASO_REG_C_2_3 = 0x1, 12900 MLX5_IPSEC_ASO_REG_C_4_5 = 0x2, 12901 MLX5_IPSEC_ASO_REG_C_6_7 = 0x3, 12902 }; 12903 12904 enum { 12905 MLX5_IPSEC_ASO_MODE = 0x0, 12906 MLX5_IPSEC_ASO_REPLAY_PROTECTION = 0x1, 12907 MLX5_IPSEC_ASO_INC_SN = 0x2, 12908 }; 12909 12910 enum { 12911 MLX5_IPSEC_ASO_REPLAY_WIN_32BIT = 0x0, 12912 MLX5_IPSEC_ASO_REPLAY_WIN_64BIT = 0x1, 12913 MLX5_IPSEC_ASO_REPLAY_WIN_128BIT = 0x2, 12914 MLX5_IPSEC_ASO_REPLAY_WIN_256BIT = 0x3, 12915 }; 12916 12917 struct mlx5_ifc_ipsec_aso_bits { 12918 u8 valid[0x1]; 12919 u8 reserved_at_201[0x1]; 12920 u8 mode[0x2]; 12921 u8 window_sz[0x2]; 12922 u8 soft_lft_arm[0x1]; 12923 u8 hard_lft_arm[0x1]; 12924 u8 remove_flow_enable[0x1]; 12925 u8 esn_event_arm[0x1]; 12926 u8 reserved_at_20a[0x16]; 12927 12928 u8 remove_flow_pkt_cnt[0x20]; 12929 12930 u8 remove_flow_soft_lft[0x20]; 12931 12932 u8 reserved_at_260[0x80]; 12933 12934 u8 mode_parameter[0x20]; 12935 12936 u8 replay_protection_window[0x100]; 12937 }; 12938 12939 struct mlx5_ifc_ipsec_obj_bits { 12940 u8 modify_field_select[0x40]; 12941 u8 full_offload[0x1]; 12942 u8 reserved_at_41[0x1]; 12943 u8 esn_en[0x1]; 12944 u8 esn_overlap[0x1]; 12945 u8 reserved_at_44[0x2]; 12946 u8 icv_length[0x2]; 12947 u8 reserved_at_48[0x4]; 12948 u8 aso_return_reg[0x4]; 12949 u8 reserved_at_50[0x10]; 12950 12951 u8 esn_msb[0x20]; 12952 12953 u8 reserved_at_80[0x8]; 12954 u8 dekn[0x18]; 12955 12956 u8 salt[0x20]; 12957 12958 u8 implicit_iv[0x40]; 12959 12960 u8 reserved_at_100[0x8]; 12961 u8 ipsec_aso_access_pd[0x18]; 12962 u8 reserved_at_120[0xe0]; 12963 12964 struct mlx5_ifc_ipsec_aso_bits ipsec_aso; 12965 }; 12966 12967 struct mlx5_ifc_create_ipsec_obj_in_bits { 12968 struct mlx5_ifc_general_obj_in_cmd_hdr_bits general_obj_in_cmd_hdr; 12969 struct mlx5_ifc_ipsec_obj_bits ipsec_object; 12970 }; 12971 12972 enum { 12973 MLX5_MODIFY_IPSEC_BITMASK_ESN_OVERLAP = BIT(0), 12974 MLX5_MODIFY_IPSEC_BITMASK_ESN_MSB = BIT(1), 12975 }; 12976 12977 struct mlx5_ifc_query_ipsec_obj_out_bits { 12978 struct mlx5_ifc_general_obj_out_cmd_hdr_bits general_obj_out_cmd_hdr; 12979 struct mlx5_ifc_ipsec_obj_bits ipsec_object; 12980 }; 12981 12982 struct mlx5_ifc_modify_ipsec_obj_in_bits { 12983 struct mlx5_ifc_general_obj_in_cmd_hdr_bits general_obj_in_cmd_hdr; 12984 struct mlx5_ifc_ipsec_obj_bits ipsec_object; 12985 }; 12986 12987 enum { 12988 MLX5_MACSEC_ASO_REPLAY_PROTECTION = 0x1, 12989 }; 12990 12991 enum { 12992 MLX5_MACSEC_ASO_REPLAY_WIN_32BIT = 0x0, 12993 MLX5_MACSEC_ASO_REPLAY_WIN_64BIT = 0x1, 12994 MLX5_MACSEC_ASO_REPLAY_WIN_128BIT = 0x2, 12995 MLX5_MACSEC_ASO_REPLAY_WIN_256BIT = 0x3, 12996 }; 12997 12998 #define MLX5_MACSEC_ASO_INC_SN 0x2 12999 #define MLX5_MACSEC_ASO_REG_C_4_5 0x2 13000 13001 struct mlx5_ifc_macsec_aso_bits { 13002 u8 valid[0x1]; 13003 u8 reserved_at_1[0x1]; 13004 u8 mode[0x2]; 13005 u8 window_size[0x2]; 13006 u8 soft_lifetime_arm[0x1]; 13007 u8 hard_lifetime_arm[0x1]; 13008 u8 remove_flow_enable[0x1]; 13009 u8 epn_event_arm[0x1]; 13010 u8 reserved_at_a[0x16]; 13011 13012 u8 remove_flow_packet_count[0x20]; 13013 13014 u8 remove_flow_soft_lifetime[0x20]; 13015 13016 u8 reserved_at_60[0x80]; 13017 13018 u8 mode_parameter[0x20]; 13019 13020 u8 replay_protection_window[8][0x20]; 13021 }; 13022 13023 struct mlx5_ifc_macsec_offload_obj_bits { 13024 u8 modify_field_select[0x40]; 13025 13026 u8 confidentiality_en[0x1]; 13027 u8 reserved_at_41[0x1]; 13028 u8 epn_en[0x1]; 13029 u8 epn_overlap[0x1]; 13030 u8 reserved_at_44[0x2]; 13031 u8 confidentiality_offset[0x2]; 13032 u8 reserved_at_48[0x4]; 13033 u8 aso_return_reg[0x4]; 13034 u8 reserved_at_50[0x10]; 13035 13036 u8 epn_msb[0x20]; 13037 13038 u8 reserved_at_80[0x8]; 13039 u8 dekn[0x18]; 13040 13041 u8 reserved_at_a0[0x20]; 13042 13043 u8 sci[0x40]; 13044 13045 u8 reserved_at_100[0x8]; 13046 u8 macsec_aso_access_pd[0x18]; 13047 13048 u8 reserved_at_120[0x60]; 13049 13050 u8 salt[3][0x20]; 13051 13052 u8 reserved_at_1e0[0x20]; 13053 13054 struct mlx5_ifc_macsec_aso_bits macsec_aso; 13055 }; 13056 13057 struct mlx5_ifc_create_macsec_obj_in_bits { 13058 struct mlx5_ifc_general_obj_in_cmd_hdr_bits general_obj_in_cmd_hdr; 13059 struct mlx5_ifc_macsec_offload_obj_bits macsec_object; 13060 }; 13061 13062 struct mlx5_ifc_modify_macsec_obj_in_bits { 13063 struct mlx5_ifc_general_obj_in_cmd_hdr_bits general_obj_in_cmd_hdr; 13064 struct mlx5_ifc_macsec_offload_obj_bits macsec_object; 13065 }; 13066 13067 enum { 13068 MLX5_MODIFY_MACSEC_BITMASK_EPN_OVERLAP = BIT(0), 13069 MLX5_MODIFY_MACSEC_BITMASK_EPN_MSB = BIT(1), 13070 }; 13071 13072 struct mlx5_ifc_query_macsec_obj_out_bits { 13073 struct mlx5_ifc_general_obj_out_cmd_hdr_bits general_obj_out_cmd_hdr; 13074 struct mlx5_ifc_macsec_offload_obj_bits macsec_object; 13075 }; 13076 13077 struct mlx5_ifc_wrapped_dek_bits { 13078 u8 gcm_iv[0x60]; 13079 13080 u8 reserved_at_60[0x20]; 13081 13082 u8 const0[0x1]; 13083 u8 key_size[0x1]; 13084 u8 reserved_at_82[0x2]; 13085 u8 key2_invalid[0x1]; 13086 u8 reserved_at_85[0x3]; 13087 u8 pd[0x18]; 13088 13089 u8 key_purpose[0x5]; 13090 u8 reserved_at_a5[0x13]; 13091 u8 kek_id[0x8]; 13092 13093 u8 reserved_at_c0[0x40]; 13094 13095 u8 key1[0x8][0x20]; 13096 13097 u8 key2[0x8][0x20]; 13098 13099 u8 reserved_at_300[0x40]; 13100 13101 u8 const1[0x1]; 13102 u8 reserved_at_341[0x1f]; 13103 13104 u8 reserved_at_360[0x20]; 13105 13106 u8 auth_tag[0x80]; 13107 }; 13108 13109 struct mlx5_ifc_encryption_key_obj_bits { 13110 u8 modify_field_select[0x40]; 13111 13112 u8 state[0x8]; 13113 u8 sw_wrapped[0x1]; 13114 u8 reserved_at_49[0xb]; 13115 u8 key_size[0x4]; 13116 u8 reserved_at_58[0x4]; 13117 u8 key_purpose[0x4]; 13118 13119 u8 reserved_at_60[0x8]; 13120 u8 pd[0x18]; 13121 13122 u8 reserved_at_80[0x100]; 13123 13124 u8 opaque[0x40]; 13125 13126 u8 reserved_at_1c0[0x40]; 13127 13128 u8 key[8][0x80]; 13129 13130 u8 sw_wrapped_dek[8][0x80]; 13131 13132 u8 reserved_at_a00[0x600]; 13133 }; 13134 13135 struct mlx5_ifc_create_encryption_key_in_bits { 13136 struct mlx5_ifc_general_obj_in_cmd_hdr_bits general_obj_in_cmd_hdr; 13137 struct mlx5_ifc_encryption_key_obj_bits encryption_key_object; 13138 }; 13139 13140 struct mlx5_ifc_modify_encryption_key_in_bits { 13141 struct mlx5_ifc_general_obj_in_cmd_hdr_bits general_obj_in_cmd_hdr; 13142 struct mlx5_ifc_encryption_key_obj_bits encryption_key_object; 13143 }; 13144 13145 enum { 13146 MLX5_FLOW_METER_MODE_BYTES_IP_LENGTH = 0x0, 13147 MLX5_FLOW_METER_MODE_BYTES_CALC_WITH_L2 = 0x1, 13148 MLX5_FLOW_METER_MODE_BYTES_CALC_WITH_L2_IPG = 0x2, 13149 MLX5_FLOW_METER_MODE_NUM_PACKETS = 0x3, 13150 }; 13151 13152 struct mlx5_ifc_flow_meter_parameters_bits { 13153 u8 valid[0x1]; 13154 u8 bucket_overflow[0x1]; 13155 u8 start_color[0x2]; 13156 u8 both_buckets_on_green[0x1]; 13157 u8 reserved_at_5[0x1]; 13158 u8 meter_mode[0x2]; 13159 u8 reserved_at_8[0x18]; 13160 13161 u8 reserved_at_20[0x20]; 13162 13163 u8 reserved_at_40[0x3]; 13164 u8 cbs_exponent[0x5]; 13165 u8 cbs_mantissa[0x8]; 13166 u8 reserved_at_50[0x3]; 13167 u8 cir_exponent[0x5]; 13168 u8 cir_mantissa[0x8]; 13169 13170 u8 reserved_at_60[0x20]; 13171 13172 u8 reserved_at_80[0x3]; 13173 u8 ebs_exponent[0x5]; 13174 u8 ebs_mantissa[0x8]; 13175 u8 reserved_at_90[0x3]; 13176 u8 eir_exponent[0x5]; 13177 u8 eir_mantissa[0x8]; 13178 13179 u8 reserved_at_a0[0x60]; 13180 }; 13181 13182 struct mlx5_ifc_flow_meter_aso_obj_bits { 13183 u8 modify_field_select[0x40]; 13184 13185 u8 reserved_at_40[0x40]; 13186 13187 u8 reserved_at_80[0x8]; 13188 u8 meter_aso_access_pd[0x18]; 13189 13190 u8 reserved_at_a0[0x160]; 13191 13192 struct mlx5_ifc_flow_meter_parameters_bits flow_meter_parameters[2]; 13193 }; 13194 13195 struct mlx5_ifc_create_flow_meter_aso_obj_in_bits { 13196 struct mlx5_ifc_general_obj_in_cmd_hdr_bits hdr; 13197 struct mlx5_ifc_flow_meter_aso_obj_bits flow_meter_aso_obj; 13198 }; 13199 13200 struct mlx5_ifc_int_kek_obj_bits { 13201 u8 modify_field_select[0x40]; 13202 13203 u8 state[0x8]; 13204 u8 auto_gen[0x1]; 13205 u8 reserved_at_49[0xb]; 13206 u8 key_size[0x4]; 13207 u8 reserved_at_58[0x8]; 13208 13209 u8 reserved_at_60[0x8]; 13210 u8 pd[0x18]; 13211 13212 u8 reserved_at_80[0x180]; 13213 u8 key[8][0x80]; 13214 13215 u8 reserved_at_600[0x200]; 13216 }; 13217 13218 struct mlx5_ifc_create_int_kek_obj_in_bits { 13219 struct mlx5_ifc_general_obj_in_cmd_hdr_bits general_obj_in_cmd_hdr; 13220 struct mlx5_ifc_int_kek_obj_bits int_kek_object; 13221 }; 13222 13223 struct mlx5_ifc_create_int_kek_obj_out_bits { 13224 struct mlx5_ifc_general_obj_out_cmd_hdr_bits general_obj_out_cmd_hdr; 13225 struct mlx5_ifc_int_kek_obj_bits int_kek_object; 13226 }; 13227 13228 struct mlx5_ifc_sampler_obj_bits { 13229 u8 modify_field_select[0x40]; 13230 13231 u8 table_type[0x8]; 13232 u8 level[0x8]; 13233 u8 reserved_at_50[0xf]; 13234 u8 ignore_flow_level[0x1]; 13235 13236 u8 sample_ratio[0x20]; 13237 13238 u8 reserved_at_80[0x8]; 13239 u8 sample_table_id[0x18]; 13240 13241 u8 reserved_at_a0[0x8]; 13242 u8 default_table_id[0x18]; 13243 13244 u8 sw_steering_icm_address_rx[0x40]; 13245 u8 sw_steering_icm_address_tx[0x40]; 13246 13247 u8 reserved_at_140[0xa0]; 13248 }; 13249 13250 struct mlx5_ifc_create_sampler_obj_in_bits { 13251 struct mlx5_ifc_general_obj_in_cmd_hdr_bits general_obj_in_cmd_hdr; 13252 struct mlx5_ifc_sampler_obj_bits sampler_object; 13253 }; 13254 13255 struct mlx5_ifc_query_sampler_obj_out_bits { 13256 struct mlx5_ifc_general_obj_out_cmd_hdr_bits general_obj_out_cmd_hdr; 13257 struct mlx5_ifc_sampler_obj_bits sampler_object; 13258 }; 13259 13260 enum { 13261 MLX5_GENERAL_OBJECT_TYPE_ENCRYPTION_KEY_KEY_SIZE_128 = 0x0, 13262 MLX5_GENERAL_OBJECT_TYPE_ENCRYPTION_KEY_KEY_SIZE_256 = 0x1, 13263 }; 13264 13265 enum { 13266 MLX5_GENERAL_OBJECT_TYPE_ENCRYPTION_KEY_PURPOSE_TLS = 0x1, 13267 MLX5_GENERAL_OBJECT_TYPE_ENCRYPTION_KEY_PURPOSE_IPSEC = 0x2, 13268 MLX5_GENERAL_OBJECT_TYPE_ENCRYPTION_KEY_PURPOSE_MACSEC = 0x4, 13269 MLX5_GENERAL_OBJECT_TYPE_ENCRYPTION_KEY_PURPOSE_PSP = 0x6, 13270 }; 13271 13272 struct mlx5_ifc_tls_static_params_bits { 13273 u8 const_2[0x2]; 13274 u8 tls_version[0x4]; 13275 u8 const_1[0x2]; 13276 u8 reserved_at_8[0x14]; 13277 u8 encryption_standard[0x4]; 13278 13279 u8 reserved_at_20[0x20]; 13280 13281 u8 initial_record_number[0x40]; 13282 13283 u8 resync_tcp_sn[0x20]; 13284 13285 u8 gcm_iv[0x20]; 13286 13287 u8 implicit_iv[0x40]; 13288 13289 u8 reserved_at_100[0x8]; 13290 u8 dek_index[0x18]; 13291 13292 u8 reserved_at_120[0xe0]; 13293 }; 13294 13295 struct mlx5_ifc_tls_progress_params_bits { 13296 u8 next_record_tcp_sn[0x20]; 13297 13298 u8 hw_resync_tcp_sn[0x20]; 13299 13300 u8 record_tracker_state[0x2]; 13301 u8 auth_state[0x2]; 13302 u8 reserved_at_44[0x4]; 13303 u8 hw_offset_record_number[0x18]; 13304 }; 13305 13306 enum { 13307 MLX5_MTT_PERM_READ = 1 << 0, 13308 MLX5_MTT_PERM_WRITE = 1 << 1, 13309 MLX5_MTT_PERM_RW = MLX5_MTT_PERM_READ | MLX5_MTT_PERM_WRITE, 13310 }; 13311 13312 enum { 13313 MLX5_SUSPEND_VHCA_IN_OP_MOD_SUSPEND_INITIATOR = 0x0, 13314 MLX5_SUSPEND_VHCA_IN_OP_MOD_SUSPEND_RESPONDER = 0x1, 13315 }; 13316 13317 struct mlx5_ifc_suspend_vhca_in_bits { 13318 u8 opcode[0x10]; 13319 u8 uid[0x10]; 13320 13321 u8 reserved_at_20[0x10]; 13322 u8 op_mod[0x10]; 13323 13324 u8 reserved_at_40[0x10]; 13325 u8 vhca_id[0x10]; 13326 13327 u8 reserved_at_60[0x20]; 13328 }; 13329 13330 struct mlx5_ifc_suspend_vhca_out_bits { 13331 u8 status[0x8]; 13332 u8 reserved_at_8[0x18]; 13333 13334 u8 syndrome[0x20]; 13335 13336 u8 reserved_at_40[0x40]; 13337 }; 13338 13339 enum { 13340 MLX5_RESUME_VHCA_IN_OP_MOD_RESUME_RESPONDER = 0x0, 13341 MLX5_RESUME_VHCA_IN_OP_MOD_RESUME_INITIATOR = 0x1, 13342 }; 13343 13344 struct mlx5_ifc_resume_vhca_in_bits { 13345 u8 opcode[0x10]; 13346 u8 uid[0x10]; 13347 13348 u8 reserved_at_20[0x10]; 13349 u8 op_mod[0x10]; 13350 13351 u8 reserved_at_40[0x10]; 13352 u8 vhca_id[0x10]; 13353 13354 u8 reserved_at_60[0x20]; 13355 }; 13356 13357 struct mlx5_ifc_resume_vhca_out_bits { 13358 u8 status[0x8]; 13359 u8 reserved_at_8[0x18]; 13360 13361 u8 syndrome[0x20]; 13362 13363 u8 reserved_at_40[0x40]; 13364 }; 13365 13366 struct mlx5_ifc_query_vhca_migration_state_in_bits { 13367 u8 opcode[0x10]; 13368 u8 uid[0x10]; 13369 13370 u8 reserved_at_20[0x10]; 13371 u8 op_mod[0x10]; 13372 13373 u8 incremental[0x1]; 13374 u8 chunk[0x1]; 13375 u8 reserved_at_42[0xe]; 13376 u8 vhca_id[0x10]; 13377 13378 u8 reserved_at_60[0x20]; 13379 }; 13380 13381 enum { 13382 MLX5_QUERY_VHCA_MIG_STATE_UNINITIALIZED = 0x0, 13383 MLX5_QUERY_VHCA_MIG_STATE_OPER_MIGRATION_IDLE = 0x1, 13384 MLX5_QUERY_VHCA_MIG_STATE_OPER_MIGRATION_READY = 0x2, 13385 MLX5_QUERY_VHCA_MIG_STATE_OPER_MIGRATION_DIRTY = 0x3, 13386 MLX5_QUERY_VHCA_MIG_STATE_OPER_MIGRATION_INIT = 0x4, 13387 }; 13388 13389 struct mlx5_ifc_query_vhca_migration_state_out_bits { 13390 u8 status[0x8]; 13391 u8 reserved_at_8[0x18]; 13392 13393 u8 syndrome[0x20]; 13394 13395 u8 reserved_at_40[0x20]; 13396 13397 u8 migration_state[0x4]; 13398 u8 reserved_at_64[0x1c]; 13399 13400 u8 required_umem_size[0x20]; 13401 13402 u8 reserved_at_a0[0x20]; 13403 13404 u8 remaining_total_size[0x40]; 13405 13406 u8 reserved_at_100[0x100]; 13407 }; 13408 13409 struct mlx5_ifc_save_vhca_state_in_bits { 13410 u8 opcode[0x10]; 13411 u8 uid[0x10]; 13412 13413 u8 reserved_at_20[0x10]; 13414 u8 op_mod[0x10]; 13415 13416 u8 incremental[0x1]; 13417 u8 set_track[0x1]; 13418 u8 reserved_at_42[0xe]; 13419 u8 vhca_id[0x10]; 13420 13421 u8 reserved_at_60[0x20]; 13422 13423 u8 va[0x40]; 13424 13425 u8 mkey[0x20]; 13426 13427 u8 size[0x20]; 13428 }; 13429 13430 struct mlx5_ifc_save_vhca_state_out_bits { 13431 u8 status[0x8]; 13432 u8 reserved_at_8[0x18]; 13433 13434 u8 syndrome[0x20]; 13435 13436 u8 actual_image_size[0x20]; 13437 13438 u8 next_required_umem_size[0x20]; 13439 }; 13440 13441 struct mlx5_ifc_load_vhca_state_in_bits { 13442 u8 opcode[0x10]; 13443 u8 uid[0x10]; 13444 13445 u8 reserved_at_20[0x10]; 13446 u8 op_mod[0x10]; 13447 13448 u8 reserved_at_40[0x10]; 13449 u8 vhca_id[0x10]; 13450 13451 u8 reserved_at_60[0x20]; 13452 13453 u8 va[0x40]; 13454 13455 u8 mkey[0x20]; 13456 13457 u8 size[0x20]; 13458 }; 13459 13460 struct mlx5_ifc_load_vhca_state_out_bits { 13461 u8 status[0x8]; 13462 u8 reserved_at_8[0x18]; 13463 13464 u8 syndrome[0x20]; 13465 13466 u8 reserved_at_40[0x40]; 13467 }; 13468 13469 struct mlx5_ifc_adv_rdma_cap_bits { 13470 u8 rdma_transport_manager[0x1]; 13471 u8 rdma_transport_manager_other_eswitch[0x1]; 13472 u8 reserved_at_2[0x1e]; 13473 13474 u8 rcx_type[0x8]; 13475 u8 reserved_at_28[0x2]; 13476 u8 ps_entry_log_max_value[0x6]; 13477 u8 reserved_at_30[0x6]; 13478 u8 qp_max_ps_num_entry[0xa]; 13479 13480 u8 mp_max_num_queues[0x8]; 13481 u8 ps_user_context_max_log_size[0x8]; 13482 u8 message_based_qp_and_striding_wq[0x8]; 13483 u8 reserved_at_58[0x8]; 13484 13485 u8 max_receive_send_message_size_stride[0x10]; 13486 u8 reserved_at_70[0x10]; 13487 13488 u8 max_receive_send_message_size_byte[0x20]; 13489 13490 u8 reserved_at_a0[0x160]; 13491 13492 struct mlx5_ifc_flow_table_prop_layout_bits rdma_transport_rx_flow_table_properties; 13493 13494 struct mlx5_ifc_flow_table_prop_layout_bits rdma_transport_tx_flow_table_properties; 13495 13496 struct mlx5_ifc_flow_table_fields_supported_2_bits rdma_transport_rx_ft_field_support_2; 13497 13498 struct mlx5_ifc_flow_table_fields_supported_2_bits rdma_transport_tx_ft_field_support_2; 13499 13500 struct mlx5_ifc_flow_table_fields_supported_2_bits rdma_transport_rx_ft_field_bitmask_support_2; 13501 13502 struct mlx5_ifc_flow_table_fields_supported_2_bits rdma_transport_tx_ft_field_bitmask_support_2; 13503 13504 u8 reserved_at_800[0x3800]; 13505 }; 13506 13507 struct mlx5_ifc_adv_virtualization_cap_bits { 13508 u8 reserved_at_0[0x3]; 13509 u8 pg_track_log_max_num[0x5]; 13510 u8 pg_track_max_num_range[0x8]; 13511 u8 pg_track_log_min_addr_space[0x8]; 13512 u8 pg_track_log_max_addr_space[0x8]; 13513 13514 u8 reserved_at_20[0x3]; 13515 u8 pg_track_log_min_msg_size[0x5]; 13516 u8 reserved_at_28[0x3]; 13517 u8 pg_track_log_max_msg_size[0x5]; 13518 u8 reserved_at_30[0x3]; 13519 u8 pg_track_log_min_page_size[0x5]; 13520 u8 reserved_at_38[0x3]; 13521 u8 pg_track_log_max_page_size[0x5]; 13522 13523 u8 reserved_at_40[0x7c0]; 13524 }; 13525 13526 struct mlx5_ifc_page_track_report_entry_bits { 13527 u8 dirty_address_high[0x20]; 13528 13529 u8 dirty_address_low[0x20]; 13530 }; 13531 13532 enum { 13533 MLX5_PAGE_TRACK_STATE_TRACKING, 13534 MLX5_PAGE_TRACK_STATE_REPORTING, 13535 MLX5_PAGE_TRACK_STATE_ERROR, 13536 }; 13537 13538 struct mlx5_ifc_page_track_range_bits { 13539 u8 start_address[0x40]; 13540 13541 u8 length[0x40]; 13542 }; 13543 13544 struct mlx5_ifc_page_track_bits { 13545 u8 modify_field_select[0x40]; 13546 13547 u8 reserved_at_40[0x10]; 13548 u8 vhca_id[0x10]; 13549 13550 u8 reserved_at_60[0x20]; 13551 13552 u8 state[0x4]; 13553 u8 track_type[0x4]; 13554 u8 log_addr_space_size[0x8]; 13555 u8 reserved_at_90[0x3]; 13556 u8 log_page_size[0x5]; 13557 u8 reserved_at_98[0x3]; 13558 u8 log_msg_size[0x5]; 13559 13560 u8 reserved_at_a0[0x8]; 13561 u8 reporting_qpn[0x18]; 13562 13563 u8 reserved_at_c0[0x18]; 13564 u8 num_ranges[0x8]; 13565 13566 u8 reserved_at_e0[0x20]; 13567 13568 u8 range_start_address[0x40]; 13569 13570 u8 length[0x40]; 13571 13572 struct mlx5_ifc_page_track_range_bits track_range[0]; 13573 }; 13574 13575 struct mlx5_ifc_create_page_track_obj_in_bits { 13576 struct mlx5_ifc_general_obj_in_cmd_hdr_bits general_obj_in_cmd_hdr; 13577 struct mlx5_ifc_page_track_bits obj_context; 13578 }; 13579 13580 struct mlx5_ifc_modify_page_track_obj_in_bits { 13581 struct mlx5_ifc_general_obj_in_cmd_hdr_bits general_obj_in_cmd_hdr; 13582 struct mlx5_ifc_page_track_bits obj_context; 13583 }; 13584 13585 struct mlx5_ifc_query_page_track_obj_out_bits { 13586 struct mlx5_ifc_general_obj_out_cmd_hdr_bits general_obj_out_cmd_hdr; 13587 struct mlx5_ifc_page_track_bits obj_context; 13588 }; 13589 13590 struct mlx5_ifc_msecq_reg_bits { 13591 u8 reserved_at_0[0x20]; 13592 13593 u8 reserved_at_20[0x12]; 13594 u8 network_option[0x2]; 13595 u8 local_ssm_code[0x4]; 13596 u8 local_enhanced_ssm_code[0x8]; 13597 13598 u8 local_clock_identity[0x40]; 13599 13600 u8 reserved_at_80[0x180]; 13601 }; 13602 13603 enum { 13604 MLX5_MSEES_FIELD_SELECT_ENABLE = BIT(0), 13605 MLX5_MSEES_FIELD_SELECT_ADMIN_STATUS = BIT(1), 13606 MLX5_MSEES_FIELD_SELECT_ADMIN_FREQ_MEASURE = BIT(2), 13607 }; 13608 13609 enum mlx5_msees_admin_status { 13610 MLX5_MSEES_ADMIN_STATUS_FREE_RUNNING = 0x0, 13611 MLX5_MSEES_ADMIN_STATUS_TRACK = 0x1, 13612 }; 13613 13614 enum mlx5_msees_oper_status { 13615 MLX5_MSEES_OPER_STATUS_FREE_RUNNING = 0x0, 13616 MLX5_MSEES_OPER_STATUS_SELF_TRACK = 0x1, 13617 MLX5_MSEES_OPER_STATUS_OTHER_TRACK = 0x2, 13618 MLX5_MSEES_OPER_STATUS_HOLDOVER = 0x3, 13619 MLX5_MSEES_OPER_STATUS_FAIL_HOLDOVER = 0x4, 13620 MLX5_MSEES_OPER_STATUS_FAIL_FREE_RUNNING = 0x5, 13621 }; 13622 13623 enum mlx5_msees_failure_reason { 13624 MLX5_MSEES_FAILURE_REASON_UNDEFINED_ERROR = 0x0, 13625 MLX5_MSEES_FAILURE_REASON_PORT_DOWN = 0x1, 13626 MLX5_MSEES_FAILURE_REASON_TOO_HIGH_FREQUENCY_DIFF = 0x2, 13627 MLX5_MSEES_FAILURE_REASON_NET_SYNCHRONIZER_DEVICE_ERROR = 0x3, 13628 MLX5_MSEES_FAILURE_REASON_LACK_OF_RESOURCES = 0x4, 13629 }; 13630 13631 struct mlx5_ifc_msees_reg_bits { 13632 u8 reserved_at_0[0x8]; 13633 u8 local_port[0x8]; 13634 u8 pnat[0x2]; 13635 u8 lp_msb[0x2]; 13636 u8 reserved_at_14[0xc]; 13637 13638 u8 field_select[0x20]; 13639 13640 u8 admin_status[0x4]; 13641 u8 oper_status[0x4]; 13642 u8 ho_acq[0x1]; 13643 u8 reserved_at_49[0xc]; 13644 u8 admin_freq_measure[0x1]; 13645 u8 oper_freq_measure[0x1]; 13646 u8 failure_reason[0x9]; 13647 13648 u8 frequency_diff[0x20]; 13649 13650 u8 reserved_at_80[0x180]; 13651 }; 13652 13653 struct mlx5_ifc_mrtcq_reg_bits { 13654 u8 reserved_at_0[0x40]; 13655 13656 u8 rt_clock_identity[0x40]; 13657 13658 u8 reserved_at_80[0x180]; 13659 }; 13660 13661 struct mlx5_ifc_pcie_cong_event_obj_bits { 13662 u8 modify_select_field[0x40]; 13663 13664 u8 inbound_event_en[0x1]; 13665 u8 outbound_event_en[0x1]; 13666 u8 reserved_at_42[0x1e]; 13667 13668 u8 reserved_at_60[0x1]; 13669 u8 inbound_cong_state[0x3]; 13670 u8 reserved_at_64[0x1]; 13671 u8 outbound_cong_state[0x3]; 13672 u8 reserved_at_68[0x18]; 13673 13674 u8 inbound_cong_low_threshold[0x10]; 13675 u8 inbound_cong_high_threshold[0x10]; 13676 13677 u8 outbound_cong_low_threshold[0x10]; 13678 u8 outbound_cong_high_threshold[0x10]; 13679 13680 u8 reserved_at_e0[0x340]; 13681 }; 13682 13683 struct mlx5_ifc_pcie_cong_event_cmd_in_bits { 13684 struct mlx5_ifc_general_obj_in_cmd_hdr_bits hdr; 13685 struct mlx5_ifc_pcie_cong_event_obj_bits cong_obj; 13686 }; 13687 13688 struct mlx5_ifc_pcie_cong_event_cmd_out_bits { 13689 struct mlx5_ifc_general_obj_out_cmd_hdr_bits hdr; 13690 struct mlx5_ifc_pcie_cong_event_obj_bits cong_obj; 13691 }; 13692 13693 enum mlx5e_pcie_cong_event_mod_field { 13694 MLX5_PCIE_CONG_EVENT_MOD_EVENT_EN = BIT(0), 13695 MLX5_PCIE_CONG_EVENT_MOD_THRESH = BIT(2), 13696 }; 13697 13698 struct mlx5_ifc_psp_rotate_key_in_bits { 13699 u8 opcode[0x10]; 13700 u8 uid[0x10]; 13701 13702 u8 reserved_at_20[0x10]; 13703 u8 op_mod[0x10]; 13704 13705 u8 reserved_at_40[0x40]; 13706 }; 13707 13708 struct mlx5_ifc_psp_rotate_key_out_bits { 13709 u8 status[0x8]; 13710 u8 reserved_at_8[0x18]; 13711 13712 u8 syndrome[0x20]; 13713 13714 u8 reserved_at_40[0x40]; 13715 }; 13716 13717 enum mlx5_psp_gen_spi_in_key_size { 13718 MLX5_PSP_GEN_SPI_IN_KEY_SIZE_128 = 0x0, 13719 MLX5_PSP_GEN_SPI_IN_KEY_SIZE_256 = 0x1, 13720 }; 13721 13722 struct mlx5_ifc_key_spi_bits { 13723 u8 spi[0x20]; 13724 13725 u8 reserved_at_20[0x60]; 13726 13727 u8 key[8][0x20]; 13728 }; 13729 13730 struct mlx5_ifc_psp_gen_spi_in_bits { 13731 u8 opcode[0x10]; 13732 u8 uid[0x10]; 13733 13734 u8 reserved_at_20[0x10]; 13735 u8 op_mod[0x10]; 13736 13737 u8 reserved_at_40[0x20]; 13738 13739 u8 key_size[0x2]; 13740 u8 reserved_at_62[0xe]; 13741 u8 num_of_spi[0x10]; 13742 }; 13743 13744 struct mlx5_ifc_psp_gen_spi_out_bits { 13745 u8 status[0x8]; 13746 u8 reserved_at_8[0x18]; 13747 13748 u8 syndrome[0x20]; 13749 13750 u8 reserved_at_40[0x10]; 13751 u8 num_of_spi[0x10]; 13752 13753 u8 reserved_at_60[0x20]; 13754 13755 struct mlx5_ifc_key_spi_bits key_spi[]; 13756 }; 13757 13758 #endif /* MLX5_IFC_H */ 13759