1 /* 2 * Copyright (c) 2013-2015, Mellanox Technologies, Ltd. All rights reserved. 3 * 4 * This software is available to you under a choice of one of two 5 * licenses. You may choose to be licensed under the terms of the GNU 6 * General Public License (GPL) Version 2, available from the file 7 * COPYING in the main directory of this source tree, or the 8 * OpenIB.org BSD license below: 9 * 10 * Redistribution and use in source and binary forms, with or 11 * without modification, are permitted provided that the following 12 * conditions are met: 13 * 14 * - Redistributions of source code must retain the above 15 * copyright notice, this list of conditions and the following 16 * disclaimer. 17 * 18 * - Redistributions in binary form must reproduce the above 19 * copyright notice, this list of conditions and the following 20 * disclaimer in the documentation and/or other materials 21 * provided with the distribution. 22 * 23 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, 24 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF 25 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND 26 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS 27 * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN 28 * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN 29 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE 30 * SOFTWARE. 31 */ 32 #ifndef MLX5_IFC_H 33 #define MLX5_IFC_H 34 35 #include "mlx5_ifc_fpga.h" 36 37 enum { 38 MLX5_EVENT_TYPE_CODING_COMPLETION_EVENTS = 0x0, 39 MLX5_EVENT_TYPE_CODING_PATH_MIGRATED_SUCCEEDED = 0x1, 40 MLX5_EVENT_TYPE_CODING_COMMUNICATION_ESTABLISHED = 0x2, 41 MLX5_EVENT_TYPE_CODING_SEND_QUEUE_DRAINED = 0x3, 42 MLX5_EVENT_TYPE_CODING_LAST_WQE_REACHED = 0x13, 43 MLX5_EVENT_TYPE_CODING_SRQ_LIMIT = 0x14, 44 MLX5_EVENT_TYPE_CODING_DCT_ALL_CONNECTIONS_CLOSED = 0x1c, 45 MLX5_EVENT_TYPE_CODING_DCT_ACCESS_KEY_VIOLATION = 0x1d, 46 MLX5_EVENT_TYPE_CODING_CQ_ERROR = 0x4, 47 MLX5_EVENT_TYPE_CODING_LOCAL_WQ_CATASTROPHIC_ERROR = 0x5, 48 MLX5_EVENT_TYPE_CODING_PATH_MIGRATION_FAILED = 0x7, 49 MLX5_EVENT_TYPE_CODING_PAGE_FAULT_EVENT = 0xc, 50 MLX5_EVENT_TYPE_CODING_INVALID_REQUEST_LOCAL_WQ_ERROR = 0x10, 51 MLX5_EVENT_TYPE_CODING_LOCAL_ACCESS_VIOLATION_WQ_ERROR = 0x11, 52 MLX5_EVENT_TYPE_CODING_LOCAL_SRQ_CATASTROPHIC_ERROR = 0x12, 53 MLX5_EVENT_TYPE_CODING_INTERNAL_ERROR = 0x8, 54 MLX5_EVENT_TYPE_CODING_PORT_STATE_CHANGE = 0x9, 55 MLX5_EVENT_TYPE_CODING_GPIO_EVENT = 0x15, 56 MLX5_EVENT_TYPE_CODING_REMOTE_CONFIGURATION_PROTOCOL_EVENT = 0x19, 57 MLX5_EVENT_TYPE_CODING_DOORBELL_BLUEFLAME_CONGESTION_EVENT = 0x1a, 58 MLX5_EVENT_TYPE_CODING_STALL_VL_EVENT = 0x1b, 59 MLX5_EVENT_TYPE_CODING_DROPPED_PACKET_LOGGED_EVENT = 0x1f, 60 MLX5_EVENT_TYPE_CODING_COMMAND_INTERFACE_COMPLETION = 0xa, 61 MLX5_EVENT_TYPE_CODING_PAGE_REQUEST = 0xb, 62 MLX5_EVENT_TYPE_CODING_FPGA_ERROR = 0x20, 63 MLX5_EVENT_TYPE_CODING_FPGA_QP_ERROR = 0x21 64 }; 65 66 enum { 67 MLX5_MODIFY_TIR_BITMASK_LRO = 0x0, 68 MLX5_MODIFY_TIR_BITMASK_INDIRECT_TABLE = 0x1, 69 MLX5_MODIFY_TIR_BITMASK_HASH = 0x2, 70 MLX5_MODIFY_TIR_BITMASK_TUNNELED_OFFLOAD_EN = 0x3 71 }; 72 73 enum { 74 MLX5_SET_HCA_CAP_OP_MOD_GENERAL_DEVICE = 0x0, 75 MLX5_SET_HCA_CAP_OP_MOD_ODP = 0x2, 76 MLX5_SET_HCA_CAP_OP_MOD_ATOMIC = 0x3, 77 MLX5_SET_HCA_CAP_OP_MOD_ROCE = 0x4, 78 }; 79 80 enum { 81 MLX5_SHARED_RESOURCE_UID = 0xffff, 82 }; 83 84 enum { 85 MLX5_OBJ_TYPE_SW_ICM = 0x0008, 86 }; 87 88 enum { 89 MLX5_GENERAL_OBJ_TYPES_CAP_SW_ICM = (1ULL << MLX5_OBJ_TYPE_SW_ICM), 90 MLX5_GENERAL_OBJ_TYPES_CAP_GENEVE_TLV_OPT = (1ULL << 11), 91 MLX5_GENERAL_OBJ_TYPES_CAP_VIRTIO_NET_Q = (1ULL << 13), 92 }; 93 94 enum { 95 MLX5_OBJ_TYPE_GENEVE_TLV_OPT = 0x000b, 96 MLX5_OBJ_TYPE_VIRTIO_NET_Q = 0x000d, 97 MLX5_OBJ_TYPE_MKEY = 0xff01, 98 MLX5_OBJ_TYPE_QP = 0xff02, 99 MLX5_OBJ_TYPE_PSV = 0xff03, 100 MLX5_OBJ_TYPE_RMP = 0xff04, 101 MLX5_OBJ_TYPE_XRC_SRQ = 0xff05, 102 MLX5_OBJ_TYPE_RQ = 0xff06, 103 MLX5_OBJ_TYPE_SQ = 0xff07, 104 MLX5_OBJ_TYPE_TIR = 0xff08, 105 MLX5_OBJ_TYPE_TIS = 0xff09, 106 MLX5_OBJ_TYPE_DCT = 0xff0a, 107 MLX5_OBJ_TYPE_XRQ = 0xff0b, 108 MLX5_OBJ_TYPE_RQT = 0xff0e, 109 MLX5_OBJ_TYPE_FLOW_COUNTER = 0xff0f, 110 MLX5_OBJ_TYPE_CQ = 0xff10, 111 }; 112 113 enum { 114 MLX5_CMD_OP_QUERY_HCA_CAP = 0x100, 115 MLX5_CMD_OP_QUERY_ADAPTER = 0x101, 116 MLX5_CMD_OP_INIT_HCA = 0x102, 117 MLX5_CMD_OP_TEARDOWN_HCA = 0x103, 118 MLX5_CMD_OP_ENABLE_HCA = 0x104, 119 MLX5_CMD_OP_DISABLE_HCA = 0x105, 120 MLX5_CMD_OP_QUERY_PAGES = 0x107, 121 MLX5_CMD_OP_MANAGE_PAGES = 0x108, 122 MLX5_CMD_OP_SET_HCA_CAP = 0x109, 123 MLX5_CMD_OP_QUERY_ISSI = 0x10a, 124 MLX5_CMD_OP_SET_ISSI = 0x10b, 125 MLX5_CMD_OP_SET_DRIVER_VERSION = 0x10d, 126 MLX5_CMD_OP_QUERY_SF_PARTITION = 0x111, 127 MLX5_CMD_OP_ALLOC_SF = 0x113, 128 MLX5_CMD_OP_DEALLOC_SF = 0x114, 129 MLX5_CMD_OP_CREATE_MKEY = 0x200, 130 MLX5_CMD_OP_QUERY_MKEY = 0x201, 131 MLX5_CMD_OP_DESTROY_MKEY = 0x202, 132 MLX5_CMD_OP_QUERY_SPECIAL_CONTEXTS = 0x203, 133 MLX5_CMD_OP_PAGE_FAULT_RESUME = 0x204, 134 MLX5_CMD_OP_ALLOC_MEMIC = 0x205, 135 MLX5_CMD_OP_DEALLOC_MEMIC = 0x206, 136 MLX5_CMD_OP_CREATE_EQ = 0x301, 137 MLX5_CMD_OP_DESTROY_EQ = 0x302, 138 MLX5_CMD_OP_QUERY_EQ = 0x303, 139 MLX5_CMD_OP_GEN_EQE = 0x304, 140 MLX5_CMD_OP_CREATE_CQ = 0x400, 141 MLX5_CMD_OP_DESTROY_CQ = 0x401, 142 MLX5_CMD_OP_QUERY_CQ = 0x402, 143 MLX5_CMD_OP_MODIFY_CQ = 0x403, 144 MLX5_CMD_OP_CREATE_QP = 0x500, 145 MLX5_CMD_OP_DESTROY_QP = 0x501, 146 MLX5_CMD_OP_RST2INIT_QP = 0x502, 147 MLX5_CMD_OP_INIT2RTR_QP = 0x503, 148 MLX5_CMD_OP_RTR2RTS_QP = 0x504, 149 MLX5_CMD_OP_RTS2RTS_QP = 0x505, 150 MLX5_CMD_OP_SQERR2RTS_QP = 0x506, 151 MLX5_CMD_OP_2ERR_QP = 0x507, 152 MLX5_CMD_OP_2RST_QP = 0x50a, 153 MLX5_CMD_OP_QUERY_QP = 0x50b, 154 MLX5_CMD_OP_SQD_RTS_QP = 0x50c, 155 MLX5_CMD_OP_INIT2INIT_QP = 0x50e, 156 MLX5_CMD_OP_CREATE_PSV = 0x600, 157 MLX5_CMD_OP_DESTROY_PSV = 0x601, 158 MLX5_CMD_OP_CREATE_SRQ = 0x700, 159 MLX5_CMD_OP_DESTROY_SRQ = 0x701, 160 MLX5_CMD_OP_QUERY_SRQ = 0x702, 161 MLX5_CMD_OP_ARM_RQ = 0x703, 162 MLX5_CMD_OP_CREATE_XRC_SRQ = 0x705, 163 MLX5_CMD_OP_DESTROY_XRC_SRQ = 0x706, 164 MLX5_CMD_OP_QUERY_XRC_SRQ = 0x707, 165 MLX5_CMD_OP_ARM_XRC_SRQ = 0x708, 166 MLX5_CMD_OP_CREATE_DCT = 0x710, 167 MLX5_CMD_OP_DESTROY_DCT = 0x711, 168 MLX5_CMD_OP_DRAIN_DCT = 0x712, 169 MLX5_CMD_OP_QUERY_DCT = 0x713, 170 MLX5_CMD_OP_ARM_DCT_FOR_KEY_VIOLATION = 0x714, 171 MLX5_CMD_OP_CREATE_XRQ = 0x717, 172 MLX5_CMD_OP_DESTROY_XRQ = 0x718, 173 MLX5_CMD_OP_QUERY_XRQ = 0x719, 174 MLX5_CMD_OP_ARM_XRQ = 0x71a, 175 MLX5_CMD_OP_QUERY_XRQ_DC_PARAMS_ENTRY = 0x725, 176 MLX5_CMD_OP_SET_XRQ_DC_PARAMS_ENTRY = 0x726, 177 MLX5_CMD_OP_QUERY_XRQ_ERROR_PARAMS = 0x727, 178 MLX5_CMD_OP_RELEASE_XRQ_ERROR = 0x729, 179 MLX5_CMD_OP_MODIFY_XRQ = 0x72a, 180 MLX5_CMD_OP_QUERY_ESW_FUNCTIONS = 0x740, 181 MLX5_CMD_OP_QUERY_VPORT_STATE = 0x750, 182 MLX5_CMD_OP_MODIFY_VPORT_STATE = 0x751, 183 MLX5_CMD_OP_QUERY_ESW_VPORT_CONTEXT = 0x752, 184 MLX5_CMD_OP_MODIFY_ESW_VPORT_CONTEXT = 0x753, 185 MLX5_CMD_OP_QUERY_NIC_VPORT_CONTEXT = 0x754, 186 MLX5_CMD_OP_MODIFY_NIC_VPORT_CONTEXT = 0x755, 187 MLX5_CMD_OP_QUERY_ROCE_ADDRESS = 0x760, 188 MLX5_CMD_OP_SET_ROCE_ADDRESS = 0x761, 189 MLX5_CMD_OP_QUERY_HCA_VPORT_CONTEXT = 0x762, 190 MLX5_CMD_OP_MODIFY_HCA_VPORT_CONTEXT = 0x763, 191 MLX5_CMD_OP_QUERY_HCA_VPORT_GID = 0x764, 192 MLX5_CMD_OP_QUERY_HCA_VPORT_PKEY = 0x765, 193 MLX5_CMD_OP_QUERY_VNIC_ENV = 0x76f, 194 MLX5_CMD_OP_QUERY_VPORT_COUNTER = 0x770, 195 MLX5_CMD_OP_ALLOC_Q_COUNTER = 0x771, 196 MLX5_CMD_OP_DEALLOC_Q_COUNTER = 0x772, 197 MLX5_CMD_OP_QUERY_Q_COUNTER = 0x773, 198 MLX5_CMD_OP_SET_MONITOR_COUNTER = 0x774, 199 MLX5_CMD_OP_ARM_MONITOR_COUNTER = 0x775, 200 MLX5_CMD_OP_SET_PP_RATE_LIMIT = 0x780, 201 MLX5_CMD_OP_QUERY_RATE_LIMIT = 0x781, 202 MLX5_CMD_OP_CREATE_SCHEDULING_ELEMENT = 0x782, 203 MLX5_CMD_OP_DESTROY_SCHEDULING_ELEMENT = 0x783, 204 MLX5_CMD_OP_QUERY_SCHEDULING_ELEMENT = 0x784, 205 MLX5_CMD_OP_MODIFY_SCHEDULING_ELEMENT = 0x785, 206 MLX5_CMD_OP_CREATE_QOS_PARA_VPORT = 0x786, 207 MLX5_CMD_OP_DESTROY_QOS_PARA_VPORT = 0x787, 208 MLX5_CMD_OP_ALLOC_PD = 0x800, 209 MLX5_CMD_OP_DEALLOC_PD = 0x801, 210 MLX5_CMD_OP_ALLOC_UAR = 0x802, 211 MLX5_CMD_OP_DEALLOC_UAR = 0x803, 212 MLX5_CMD_OP_CONFIG_INT_MODERATION = 0x804, 213 MLX5_CMD_OP_ACCESS_REG = 0x805, 214 MLX5_CMD_OP_ATTACH_TO_MCG = 0x806, 215 MLX5_CMD_OP_DETACH_FROM_MCG = 0x807, 216 MLX5_CMD_OP_GET_DROPPED_PACKET_LOG = 0x80a, 217 MLX5_CMD_OP_MAD_IFC = 0x50d, 218 MLX5_CMD_OP_QUERY_MAD_DEMUX = 0x80b, 219 MLX5_CMD_OP_SET_MAD_DEMUX = 0x80c, 220 MLX5_CMD_OP_NOP = 0x80d, 221 MLX5_CMD_OP_ALLOC_XRCD = 0x80e, 222 MLX5_CMD_OP_DEALLOC_XRCD = 0x80f, 223 MLX5_CMD_OP_ALLOC_TRANSPORT_DOMAIN = 0x816, 224 MLX5_CMD_OP_DEALLOC_TRANSPORT_DOMAIN = 0x817, 225 MLX5_CMD_OP_QUERY_CONG_STATUS = 0x822, 226 MLX5_CMD_OP_MODIFY_CONG_STATUS = 0x823, 227 MLX5_CMD_OP_QUERY_CONG_PARAMS = 0x824, 228 MLX5_CMD_OP_MODIFY_CONG_PARAMS = 0x825, 229 MLX5_CMD_OP_QUERY_CONG_STATISTICS = 0x826, 230 MLX5_CMD_OP_ADD_VXLAN_UDP_DPORT = 0x827, 231 MLX5_CMD_OP_DELETE_VXLAN_UDP_DPORT = 0x828, 232 MLX5_CMD_OP_SET_L2_TABLE_ENTRY = 0x829, 233 MLX5_CMD_OP_QUERY_L2_TABLE_ENTRY = 0x82a, 234 MLX5_CMD_OP_DELETE_L2_TABLE_ENTRY = 0x82b, 235 MLX5_CMD_OP_SET_WOL_ROL = 0x830, 236 MLX5_CMD_OP_QUERY_WOL_ROL = 0x831, 237 MLX5_CMD_OP_CREATE_LAG = 0x840, 238 MLX5_CMD_OP_MODIFY_LAG = 0x841, 239 MLX5_CMD_OP_QUERY_LAG = 0x842, 240 MLX5_CMD_OP_DESTROY_LAG = 0x843, 241 MLX5_CMD_OP_CREATE_VPORT_LAG = 0x844, 242 MLX5_CMD_OP_DESTROY_VPORT_LAG = 0x845, 243 MLX5_CMD_OP_CREATE_TIR = 0x900, 244 MLX5_CMD_OP_MODIFY_TIR = 0x901, 245 MLX5_CMD_OP_DESTROY_TIR = 0x902, 246 MLX5_CMD_OP_QUERY_TIR = 0x903, 247 MLX5_CMD_OP_CREATE_SQ = 0x904, 248 MLX5_CMD_OP_MODIFY_SQ = 0x905, 249 MLX5_CMD_OP_DESTROY_SQ = 0x906, 250 MLX5_CMD_OP_QUERY_SQ = 0x907, 251 MLX5_CMD_OP_CREATE_RQ = 0x908, 252 MLX5_CMD_OP_MODIFY_RQ = 0x909, 253 MLX5_CMD_OP_SET_DELAY_DROP_PARAMS = 0x910, 254 MLX5_CMD_OP_DESTROY_RQ = 0x90a, 255 MLX5_CMD_OP_QUERY_RQ = 0x90b, 256 MLX5_CMD_OP_CREATE_RMP = 0x90c, 257 MLX5_CMD_OP_MODIFY_RMP = 0x90d, 258 MLX5_CMD_OP_DESTROY_RMP = 0x90e, 259 MLX5_CMD_OP_QUERY_RMP = 0x90f, 260 MLX5_CMD_OP_CREATE_TIS = 0x912, 261 MLX5_CMD_OP_MODIFY_TIS = 0x913, 262 MLX5_CMD_OP_DESTROY_TIS = 0x914, 263 MLX5_CMD_OP_QUERY_TIS = 0x915, 264 MLX5_CMD_OP_CREATE_RQT = 0x916, 265 MLX5_CMD_OP_MODIFY_RQT = 0x917, 266 MLX5_CMD_OP_DESTROY_RQT = 0x918, 267 MLX5_CMD_OP_QUERY_RQT = 0x919, 268 MLX5_CMD_OP_SET_FLOW_TABLE_ROOT = 0x92f, 269 MLX5_CMD_OP_CREATE_FLOW_TABLE = 0x930, 270 MLX5_CMD_OP_DESTROY_FLOW_TABLE = 0x931, 271 MLX5_CMD_OP_QUERY_FLOW_TABLE = 0x932, 272 MLX5_CMD_OP_CREATE_FLOW_GROUP = 0x933, 273 MLX5_CMD_OP_DESTROY_FLOW_GROUP = 0x934, 274 MLX5_CMD_OP_QUERY_FLOW_GROUP = 0x935, 275 MLX5_CMD_OP_SET_FLOW_TABLE_ENTRY = 0x936, 276 MLX5_CMD_OP_QUERY_FLOW_TABLE_ENTRY = 0x937, 277 MLX5_CMD_OP_DELETE_FLOW_TABLE_ENTRY = 0x938, 278 MLX5_CMD_OP_ALLOC_FLOW_COUNTER = 0x939, 279 MLX5_CMD_OP_DEALLOC_FLOW_COUNTER = 0x93a, 280 MLX5_CMD_OP_QUERY_FLOW_COUNTER = 0x93b, 281 MLX5_CMD_OP_MODIFY_FLOW_TABLE = 0x93c, 282 MLX5_CMD_OP_ALLOC_PACKET_REFORMAT_CONTEXT = 0x93d, 283 MLX5_CMD_OP_DEALLOC_PACKET_REFORMAT_CONTEXT = 0x93e, 284 MLX5_CMD_OP_QUERY_PACKET_REFORMAT_CONTEXT = 0x93f, 285 MLX5_CMD_OP_ALLOC_MODIFY_HEADER_CONTEXT = 0x940, 286 MLX5_CMD_OP_DEALLOC_MODIFY_HEADER_CONTEXT = 0x941, 287 MLX5_CMD_OP_QUERY_MODIFY_HEADER_CONTEXT = 0x942, 288 MLX5_CMD_OP_FPGA_CREATE_QP = 0x960, 289 MLX5_CMD_OP_FPGA_MODIFY_QP = 0x961, 290 MLX5_CMD_OP_FPGA_QUERY_QP = 0x962, 291 MLX5_CMD_OP_FPGA_DESTROY_QP = 0x963, 292 MLX5_CMD_OP_FPGA_QUERY_QP_COUNTERS = 0x964, 293 MLX5_CMD_OP_CREATE_GENERAL_OBJECT = 0xa00, 294 MLX5_CMD_OP_MODIFY_GENERAL_OBJECT = 0xa01, 295 MLX5_CMD_OP_QUERY_GENERAL_OBJECT = 0xa02, 296 MLX5_CMD_OP_DESTROY_GENERAL_OBJECT = 0xa03, 297 MLX5_CMD_OP_CREATE_UCTX = 0xa04, 298 MLX5_CMD_OP_DESTROY_UCTX = 0xa06, 299 MLX5_CMD_OP_CREATE_UMEM = 0xa08, 300 MLX5_CMD_OP_DESTROY_UMEM = 0xa0a, 301 MLX5_CMD_OP_SYNC_STEERING = 0xb00, 302 MLX5_CMD_OP_MAX 303 }; 304 305 /* Valid range for general commands that don't work over an object */ 306 enum { 307 MLX5_CMD_OP_GENERAL_START = 0xb00, 308 MLX5_CMD_OP_GENERAL_END = 0xd00, 309 }; 310 311 struct mlx5_ifc_flow_table_fields_supported_bits { 312 u8 outer_dmac[0x1]; 313 u8 outer_smac[0x1]; 314 u8 outer_ether_type[0x1]; 315 u8 outer_ip_version[0x1]; 316 u8 outer_first_prio[0x1]; 317 u8 outer_first_cfi[0x1]; 318 u8 outer_first_vid[0x1]; 319 u8 outer_ipv4_ttl[0x1]; 320 u8 outer_second_prio[0x1]; 321 u8 outer_second_cfi[0x1]; 322 u8 outer_second_vid[0x1]; 323 u8 reserved_at_b[0x1]; 324 u8 outer_sip[0x1]; 325 u8 outer_dip[0x1]; 326 u8 outer_frag[0x1]; 327 u8 outer_ip_protocol[0x1]; 328 u8 outer_ip_ecn[0x1]; 329 u8 outer_ip_dscp[0x1]; 330 u8 outer_udp_sport[0x1]; 331 u8 outer_udp_dport[0x1]; 332 u8 outer_tcp_sport[0x1]; 333 u8 outer_tcp_dport[0x1]; 334 u8 outer_tcp_flags[0x1]; 335 u8 outer_gre_protocol[0x1]; 336 u8 outer_gre_key[0x1]; 337 u8 outer_vxlan_vni[0x1]; 338 u8 outer_geneve_vni[0x1]; 339 u8 outer_geneve_oam[0x1]; 340 u8 outer_geneve_protocol_type[0x1]; 341 u8 outer_geneve_opt_len[0x1]; 342 u8 reserved_at_1e[0x1]; 343 u8 source_eswitch_port[0x1]; 344 345 u8 inner_dmac[0x1]; 346 u8 inner_smac[0x1]; 347 u8 inner_ether_type[0x1]; 348 u8 inner_ip_version[0x1]; 349 u8 inner_first_prio[0x1]; 350 u8 inner_first_cfi[0x1]; 351 u8 inner_first_vid[0x1]; 352 u8 reserved_at_27[0x1]; 353 u8 inner_second_prio[0x1]; 354 u8 inner_second_cfi[0x1]; 355 u8 inner_second_vid[0x1]; 356 u8 reserved_at_2b[0x1]; 357 u8 inner_sip[0x1]; 358 u8 inner_dip[0x1]; 359 u8 inner_frag[0x1]; 360 u8 inner_ip_protocol[0x1]; 361 u8 inner_ip_ecn[0x1]; 362 u8 inner_ip_dscp[0x1]; 363 u8 inner_udp_sport[0x1]; 364 u8 inner_udp_dport[0x1]; 365 u8 inner_tcp_sport[0x1]; 366 u8 inner_tcp_dport[0x1]; 367 u8 inner_tcp_flags[0x1]; 368 u8 reserved_at_37[0x9]; 369 370 u8 geneve_tlv_option_0_data[0x1]; 371 u8 reserved_at_41[0x4]; 372 u8 outer_first_mpls_over_udp[0x4]; 373 u8 outer_first_mpls_over_gre[0x4]; 374 u8 inner_first_mpls[0x4]; 375 u8 outer_first_mpls[0x4]; 376 u8 reserved_at_55[0x2]; 377 u8 outer_esp_spi[0x1]; 378 u8 reserved_at_58[0x2]; 379 u8 bth_dst_qp[0x1]; 380 u8 reserved_at_5b[0x5]; 381 382 u8 reserved_at_60[0x18]; 383 u8 metadata_reg_c_7[0x1]; 384 u8 metadata_reg_c_6[0x1]; 385 u8 metadata_reg_c_5[0x1]; 386 u8 metadata_reg_c_4[0x1]; 387 u8 metadata_reg_c_3[0x1]; 388 u8 metadata_reg_c_2[0x1]; 389 u8 metadata_reg_c_1[0x1]; 390 u8 metadata_reg_c_0[0x1]; 391 }; 392 393 struct mlx5_ifc_flow_table_prop_layout_bits { 394 u8 ft_support[0x1]; 395 u8 reserved_at_1[0x1]; 396 u8 flow_counter[0x1]; 397 u8 flow_modify_en[0x1]; 398 u8 modify_root[0x1]; 399 u8 identified_miss_table_mode[0x1]; 400 u8 flow_table_modify[0x1]; 401 u8 reformat[0x1]; 402 u8 decap[0x1]; 403 u8 reserved_at_9[0x1]; 404 u8 pop_vlan[0x1]; 405 u8 push_vlan[0x1]; 406 u8 reserved_at_c[0x1]; 407 u8 pop_vlan_2[0x1]; 408 u8 push_vlan_2[0x1]; 409 u8 reformat_and_vlan_action[0x1]; 410 u8 reserved_at_10[0x1]; 411 u8 sw_owner[0x1]; 412 u8 reformat_l3_tunnel_to_l2[0x1]; 413 u8 reformat_l2_to_l3_tunnel[0x1]; 414 u8 reformat_and_modify_action[0x1]; 415 u8 ignore_flow_level[0x1]; 416 u8 reserved_at_16[0x1]; 417 u8 table_miss_action_domain[0x1]; 418 u8 termination_table[0x1]; 419 u8 reformat_and_fwd_to_table[0x1]; 420 u8 reserved_at_1a[0x2]; 421 u8 ipsec_encrypt[0x1]; 422 u8 ipsec_decrypt[0x1]; 423 u8 reserved_at_1e[0x2]; 424 425 u8 termination_table_raw_traffic[0x1]; 426 u8 reserved_at_21[0x1]; 427 u8 log_max_ft_size[0x6]; 428 u8 log_max_modify_header_context[0x8]; 429 u8 max_modify_header_actions[0x8]; 430 u8 max_ft_level[0x8]; 431 432 u8 reserved_at_40[0x20]; 433 434 u8 reserved_at_60[0x18]; 435 u8 log_max_ft_num[0x8]; 436 437 u8 reserved_at_80[0x18]; 438 u8 log_max_destination[0x8]; 439 440 u8 log_max_flow_counter[0x8]; 441 u8 reserved_at_a8[0x10]; 442 u8 log_max_flow[0x8]; 443 444 u8 reserved_at_c0[0x40]; 445 446 struct mlx5_ifc_flow_table_fields_supported_bits ft_field_support; 447 448 struct mlx5_ifc_flow_table_fields_supported_bits ft_field_bitmask_support; 449 }; 450 451 struct mlx5_ifc_odp_per_transport_service_cap_bits { 452 u8 send[0x1]; 453 u8 receive[0x1]; 454 u8 write[0x1]; 455 u8 read[0x1]; 456 u8 atomic[0x1]; 457 u8 srq_receive[0x1]; 458 u8 reserved_at_6[0x1a]; 459 }; 460 461 struct mlx5_ifc_fte_match_set_lyr_2_4_bits { 462 u8 smac_47_16[0x20]; 463 464 u8 smac_15_0[0x10]; 465 u8 ethertype[0x10]; 466 467 u8 dmac_47_16[0x20]; 468 469 u8 dmac_15_0[0x10]; 470 u8 first_prio[0x3]; 471 u8 first_cfi[0x1]; 472 u8 first_vid[0xc]; 473 474 u8 ip_protocol[0x8]; 475 u8 ip_dscp[0x6]; 476 u8 ip_ecn[0x2]; 477 u8 cvlan_tag[0x1]; 478 u8 svlan_tag[0x1]; 479 u8 frag[0x1]; 480 u8 ip_version[0x4]; 481 u8 tcp_flags[0x9]; 482 483 u8 tcp_sport[0x10]; 484 u8 tcp_dport[0x10]; 485 486 u8 reserved_at_c0[0x18]; 487 u8 ttl_hoplimit[0x8]; 488 489 u8 udp_sport[0x10]; 490 u8 udp_dport[0x10]; 491 492 union mlx5_ifc_ipv6_layout_ipv4_layout_auto_bits src_ipv4_src_ipv6; 493 494 union mlx5_ifc_ipv6_layout_ipv4_layout_auto_bits dst_ipv4_dst_ipv6; 495 }; 496 497 struct mlx5_ifc_nvgre_key_bits { 498 u8 hi[0x18]; 499 u8 lo[0x8]; 500 }; 501 502 union mlx5_ifc_gre_key_bits { 503 struct mlx5_ifc_nvgre_key_bits nvgre; 504 u8 key[0x20]; 505 }; 506 507 struct mlx5_ifc_fte_match_set_misc_bits { 508 u8 gre_c_present[0x1]; 509 u8 reserved_at_1[0x1]; 510 u8 gre_k_present[0x1]; 511 u8 gre_s_present[0x1]; 512 u8 source_vhca_port[0x4]; 513 u8 source_sqn[0x18]; 514 515 u8 source_eswitch_owner_vhca_id[0x10]; 516 u8 source_port[0x10]; 517 518 u8 outer_second_prio[0x3]; 519 u8 outer_second_cfi[0x1]; 520 u8 outer_second_vid[0xc]; 521 u8 inner_second_prio[0x3]; 522 u8 inner_second_cfi[0x1]; 523 u8 inner_second_vid[0xc]; 524 525 u8 outer_second_cvlan_tag[0x1]; 526 u8 inner_second_cvlan_tag[0x1]; 527 u8 outer_second_svlan_tag[0x1]; 528 u8 inner_second_svlan_tag[0x1]; 529 u8 reserved_at_64[0xc]; 530 u8 gre_protocol[0x10]; 531 532 union mlx5_ifc_gre_key_bits gre_key; 533 534 u8 vxlan_vni[0x18]; 535 u8 reserved_at_b8[0x8]; 536 537 u8 geneve_vni[0x18]; 538 u8 reserved_at_d8[0x7]; 539 u8 geneve_oam[0x1]; 540 541 u8 reserved_at_e0[0xc]; 542 u8 outer_ipv6_flow_label[0x14]; 543 544 u8 reserved_at_100[0xc]; 545 u8 inner_ipv6_flow_label[0x14]; 546 547 u8 reserved_at_120[0xa]; 548 u8 geneve_opt_len[0x6]; 549 u8 geneve_protocol_type[0x10]; 550 551 u8 reserved_at_140[0x8]; 552 u8 bth_dst_qp[0x18]; 553 u8 reserved_at_160[0x20]; 554 u8 outer_esp_spi[0x20]; 555 u8 reserved_at_1a0[0x60]; 556 }; 557 558 struct mlx5_ifc_fte_match_mpls_bits { 559 u8 mpls_label[0x14]; 560 u8 mpls_exp[0x3]; 561 u8 mpls_s_bos[0x1]; 562 u8 mpls_ttl[0x8]; 563 }; 564 565 struct mlx5_ifc_fte_match_set_misc2_bits { 566 struct mlx5_ifc_fte_match_mpls_bits outer_first_mpls; 567 568 struct mlx5_ifc_fte_match_mpls_bits inner_first_mpls; 569 570 struct mlx5_ifc_fte_match_mpls_bits outer_first_mpls_over_gre; 571 572 struct mlx5_ifc_fte_match_mpls_bits outer_first_mpls_over_udp; 573 574 u8 metadata_reg_c_7[0x20]; 575 576 u8 metadata_reg_c_6[0x20]; 577 578 u8 metadata_reg_c_5[0x20]; 579 580 u8 metadata_reg_c_4[0x20]; 581 582 u8 metadata_reg_c_3[0x20]; 583 584 u8 metadata_reg_c_2[0x20]; 585 586 u8 metadata_reg_c_1[0x20]; 587 588 u8 metadata_reg_c_0[0x20]; 589 590 u8 metadata_reg_a[0x20]; 591 592 u8 reserved_at_1a0[0x60]; 593 }; 594 595 struct mlx5_ifc_fte_match_set_misc3_bits { 596 u8 inner_tcp_seq_num[0x20]; 597 598 u8 outer_tcp_seq_num[0x20]; 599 600 u8 inner_tcp_ack_num[0x20]; 601 602 u8 outer_tcp_ack_num[0x20]; 603 604 u8 reserved_at_80[0x8]; 605 u8 outer_vxlan_gpe_vni[0x18]; 606 607 u8 outer_vxlan_gpe_next_protocol[0x8]; 608 u8 outer_vxlan_gpe_flags[0x8]; 609 u8 reserved_at_b0[0x10]; 610 611 u8 icmp_header_data[0x20]; 612 613 u8 icmpv6_header_data[0x20]; 614 615 u8 icmp_type[0x8]; 616 u8 icmp_code[0x8]; 617 u8 icmpv6_type[0x8]; 618 u8 icmpv6_code[0x8]; 619 620 u8 geneve_tlv_option_0_data[0x20]; 621 622 u8 reserved_at_140[0xc0]; 623 }; 624 625 struct mlx5_ifc_cmd_pas_bits { 626 u8 pa_h[0x20]; 627 628 u8 pa_l[0x14]; 629 u8 reserved_at_34[0xc]; 630 }; 631 632 struct mlx5_ifc_uint64_bits { 633 u8 hi[0x20]; 634 635 u8 lo[0x20]; 636 }; 637 638 enum { 639 MLX5_ADS_STAT_RATE_NO_LIMIT = 0x0, 640 MLX5_ADS_STAT_RATE_2_5GBPS = 0x7, 641 MLX5_ADS_STAT_RATE_10GBPS = 0x8, 642 MLX5_ADS_STAT_RATE_30GBPS = 0x9, 643 MLX5_ADS_STAT_RATE_5GBPS = 0xa, 644 MLX5_ADS_STAT_RATE_20GBPS = 0xb, 645 MLX5_ADS_STAT_RATE_40GBPS = 0xc, 646 MLX5_ADS_STAT_RATE_60GBPS = 0xd, 647 MLX5_ADS_STAT_RATE_80GBPS = 0xe, 648 MLX5_ADS_STAT_RATE_120GBPS = 0xf, 649 }; 650 651 struct mlx5_ifc_ads_bits { 652 u8 fl[0x1]; 653 u8 free_ar[0x1]; 654 u8 reserved_at_2[0xe]; 655 u8 pkey_index[0x10]; 656 657 u8 reserved_at_20[0x8]; 658 u8 grh[0x1]; 659 u8 mlid[0x7]; 660 u8 rlid[0x10]; 661 662 u8 ack_timeout[0x5]; 663 u8 reserved_at_45[0x3]; 664 u8 src_addr_index[0x8]; 665 u8 reserved_at_50[0x4]; 666 u8 stat_rate[0x4]; 667 u8 hop_limit[0x8]; 668 669 u8 reserved_at_60[0x4]; 670 u8 tclass[0x8]; 671 u8 flow_label[0x14]; 672 673 u8 rgid_rip[16][0x8]; 674 675 u8 reserved_at_100[0x4]; 676 u8 f_dscp[0x1]; 677 u8 f_ecn[0x1]; 678 u8 reserved_at_106[0x1]; 679 u8 f_eth_prio[0x1]; 680 u8 ecn[0x2]; 681 u8 dscp[0x6]; 682 u8 udp_sport[0x10]; 683 684 u8 dei_cfi[0x1]; 685 u8 eth_prio[0x3]; 686 u8 sl[0x4]; 687 u8 vhca_port_num[0x8]; 688 u8 rmac_47_32[0x10]; 689 690 u8 rmac_31_0[0x20]; 691 }; 692 693 struct mlx5_ifc_flow_table_nic_cap_bits { 694 u8 nic_rx_multi_path_tirs[0x1]; 695 u8 nic_rx_multi_path_tirs_fts[0x1]; 696 u8 allow_sniffer_and_nic_rx_shared_tir[0x1]; 697 u8 reserved_at_3[0x4]; 698 u8 sw_owner_reformat_supported[0x1]; 699 u8 reserved_at_8[0x18]; 700 701 u8 encap_general_header[0x1]; 702 u8 reserved_at_21[0xa]; 703 u8 log_max_packet_reformat_context[0x5]; 704 u8 reserved_at_30[0x6]; 705 u8 max_encap_header_size[0xa]; 706 u8 reserved_at_40[0x1c0]; 707 708 struct mlx5_ifc_flow_table_prop_layout_bits flow_table_properties_nic_receive; 709 710 struct mlx5_ifc_flow_table_prop_layout_bits flow_table_properties_nic_receive_rdma; 711 712 struct mlx5_ifc_flow_table_prop_layout_bits flow_table_properties_nic_receive_sniffer; 713 714 struct mlx5_ifc_flow_table_prop_layout_bits flow_table_properties_nic_transmit; 715 716 struct mlx5_ifc_flow_table_prop_layout_bits flow_table_properties_nic_transmit_rdma; 717 718 struct mlx5_ifc_flow_table_prop_layout_bits flow_table_properties_nic_transmit_sniffer; 719 720 u8 reserved_at_e00[0x1200]; 721 722 u8 sw_steering_nic_rx_action_drop_icm_address[0x40]; 723 724 u8 sw_steering_nic_tx_action_drop_icm_address[0x40]; 725 726 u8 sw_steering_nic_tx_action_allow_icm_address[0x40]; 727 728 u8 reserved_at_20c0[0x5f40]; 729 }; 730 731 enum { 732 MLX5_FDB_TO_VPORT_REG_C_0 = 0x01, 733 MLX5_FDB_TO_VPORT_REG_C_1 = 0x02, 734 MLX5_FDB_TO_VPORT_REG_C_2 = 0x04, 735 MLX5_FDB_TO_VPORT_REG_C_3 = 0x08, 736 MLX5_FDB_TO_VPORT_REG_C_4 = 0x10, 737 MLX5_FDB_TO_VPORT_REG_C_5 = 0x20, 738 MLX5_FDB_TO_VPORT_REG_C_6 = 0x40, 739 MLX5_FDB_TO_VPORT_REG_C_7 = 0x80, 740 }; 741 742 struct mlx5_ifc_flow_table_eswitch_cap_bits { 743 u8 fdb_to_vport_reg_c_id[0x8]; 744 u8 reserved_at_8[0xd]; 745 u8 fdb_modify_header_fwd_to_table[0x1]; 746 u8 reserved_at_16[0x1]; 747 u8 flow_source[0x1]; 748 u8 reserved_at_18[0x2]; 749 u8 multi_fdb_encap[0x1]; 750 u8 egress_acl_forward_to_vport[0x1]; 751 u8 fdb_multi_path_to_table[0x1]; 752 u8 reserved_at_1d[0x3]; 753 754 u8 reserved_at_20[0x1e0]; 755 756 struct mlx5_ifc_flow_table_prop_layout_bits flow_table_properties_nic_esw_fdb; 757 758 struct mlx5_ifc_flow_table_prop_layout_bits flow_table_properties_esw_acl_ingress; 759 760 struct mlx5_ifc_flow_table_prop_layout_bits flow_table_properties_esw_acl_egress; 761 762 u8 reserved_at_800[0x1000]; 763 764 u8 sw_steering_fdb_action_drop_icm_address_rx[0x40]; 765 766 u8 sw_steering_fdb_action_drop_icm_address_tx[0x40]; 767 768 u8 sw_steering_uplink_icm_address_rx[0x40]; 769 770 u8 sw_steering_uplink_icm_address_tx[0x40]; 771 772 u8 reserved_at_1900[0x6700]; 773 }; 774 775 enum { 776 MLX5_COUNTER_SOURCE_ESWITCH = 0x0, 777 MLX5_COUNTER_FLOW_ESWITCH = 0x1, 778 }; 779 780 struct mlx5_ifc_e_switch_cap_bits { 781 u8 vport_svlan_strip[0x1]; 782 u8 vport_cvlan_strip[0x1]; 783 u8 vport_svlan_insert[0x1]; 784 u8 vport_cvlan_insert_if_not_exist[0x1]; 785 u8 vport_cvlan_insert_overwrite[0x1]; 786 u8 reserved_at_5[0x3]; 787 u8 esw_uplink_ingress_acl[0x1]; 788 u8 reserved_at_9[0x10]; 789 u8 esw_functions_changed[0x1]; 790 u8 reserved_at_1a[0x1]; 791 u8 ecpf_vport_exists[0x1]; 792 u8 counter_eswitch_affinity[0x1]; 793 u8 merged_eswitch[0x1]; 794 u8 nic_vport_node_guid_modify[0x1]; 795 u8 nic_vport_port_guid_modify[0x1]; 796 797 u8 vxlan_encap_decap[0x1]; 798 u8 nvgre_encap_decap[0x1]; 799 u8 reserved_at_22[0x1]; 800 u8 log_max_fdb_encap_uplink[0x5]; 801 u8 reserved_at_21[0x3]; 802 u8 log_max_packet_reformat_context[0x5]; 803 u8 reserved_2b[0x6]; 804 u8 max_encap_header_size[0xa]; 805 806 u8 reserved_at_40[0xb]; 807 u8 log_max_esw_sf[0x5]; 808 u8 esw_sf_base_id[0x10]; 809 810 u8 reserved_at_60[0x7a0]; 811 812 }; 813 814 struct mlx5_ifc_qos_cap_bits { 815 u8 packet_pacing[0x1]; 816 u8 esw_scheduling[0x1]; 817 u8 esw_bw_share[0x1]; 818 u8 esw_rate_limit[0x1]; 819 u8 reserved_at_4[0x1]; 820 u8 packet_pacing_burst_bound[0x1]; 821 u8 packet_pacing_typical_size[0x1]; 822 u8 reserved_at_7[0x4]; 823 u8 packet_pacing_uid[0x1]; 824 u8 reserved_at_c[0x14]; 825 826 u8 reserved_at_20[0x20]; 827 828 u8 packet_pacing_max_rate[0x20]; 829 830 u8 packet_pacing_min_rate[0x20]; 831 832 u8 reserved_at_80[0x10]; 833 u8 packet_pacing_rate_table_size[0x10]; 834 835 u8 esw_element_type[0x10]; 836 u8 esw_tsar_type[0x10]; 837 838 u8 reserved_at_c0[0x10]; 839 u8 max_qos_para_vport[0x10]; 840 841 u8 max_tsar_bw_share[0x20]; 842 843 u8 reserved_at_100[0x700]; 844 }; 845 846 struct mlx5_ifc_debug_cap_bits { 847 u8 core_dump_general[0x1]; 848 u8 core_dump_qp[0x1]; 849 u8 reserved_at_2[0x7]; 850 u8 resource_dump[0x1]; 851 u8 reserved_at_a[0x16]; 852 853 u8 reserved_at_20[0x2]; 854 u8 stall_detect[0x1]; 855 u8 reserved_at_23[0x1d]; 856 857 u8 reserved_at_40[0x7c0]; 858 }; 859 860 struct mlx5_ifc_per_protocol_networking_offload_caps_bits { 861 u8 csum_cap[0x1]; 862 u8 vlan_cap[0x1]; 863 u8 lro_cap[0x1]; 864 u8 lro_psh_flag[0x1]; 865 u8 lro_time_stamp[0x1]; 866 u8 reserved_at_5[0x2]; 867 u8 wqe_vlan_insert[0x1]; 868 u8 self_lb_en_modifiable[0x1]; 869 u8 reserved_at_9[0x2]; 870 u8 max_lso_cap[0x5]; 871 u8 multi_pkt_send_wqe[0x2]; 872 u8 wqe_inline_mode[0x2]; 873 u8 rss_ind_tbl_cap[0x4]; 874 u8 reg_umr_sq[0x1]; 875 u8 scatter_fcs[0x1]; 876 u8 enhanced_multi_pkt_send_wqe[0x1]; 877 u8 tunnel_lso_const_out_ip_id[0x1]; 878 u8 reserved_at_1c[0x2]; 879 u8 tunnel_stateless_gre[0x1]; 880 u8 tunnel_stateless_vxlan[0x1]; 881 882 u8 swp[0x1]; 883 u8 swp_csum[0x1]; 884 u8 swp_lso[0x1]; 885 u8 cqe_checksum_full[0x1]; 886 u8 tunnel_stateless_geneve_tx[0x1]; 887 u8 tunnel_stateless_mpls_over_udp[0x1]; 888 u8 tunnel_stateless_mpls_over_gre[0x1]; 889 u8 tunnel_stateless_vxlan_gpe[0x1]; 890 u8 tunnel_stateless_ipv4_over_vxlan[0x1]; 891 u8 tunnel_stateless_ip_over_ip[0x1]; 892 u8 insert_trailer[0x1]; 893 u8 reserved_at_2b[0x5]; 894 u8 max_vxlan_udp_ports[0x8]; 895 u8 reserved_at_38[0x6]; 896 u8 max_geneve_opt_len[0x1]; 897 u8 tunnel_stateless_geneve_rx[0x1]; 898 899 u8 reserved_at_40[0x10]; 900 u8 lro_min_mss_size[0x10]; 901 902 u8 reserved_at_60[0x120]; 903 904 u8 lro_timer_supported_periods[4][0x20]; 905 906 u8 reserved_at_200[0x600]; 907 }; 908 909 struct mlx5_ifc_roce_cap_bits { 910 u8 roce_apm[0x1]; 911 u8 reserved_at_1[0x3]; 912 u8 sw_r_roce_src_udp_port[0x1]; 913 u8 reserved_at_5[0x1b]; 914 915 u8 reserved_at_20[0x60]; 916 917 u8 reserved_at_80[0xc]; 918 u8 l3_type[0x4]; 919 u8 reserved_at_90[0x8]; 920 u8 roce_version[0x8]; 921 922 u8 reserved_at_a0[0x10]; 923 u8 r_roce_dest_udp_port[0x10]; 924 925 u8 r_roce_max_src_udp_port[0x10]; 926 u8 r_roce_min_src_udp_port[0x10]; 927 928 u8 reserved_at_e0[0x10]; 929 u8 roce_address_table_size[0x10]; 930 931 u8 reserved_at_100[0x700]; 932 }; 933 934 struct mlx5_ifc_sync_steering_in_bits { 935 u8 opcode[0x10]; 936 u8 uid[0x10]; 937 938 u8 reserved_at_20[0x10]; 939 u8 op_mod[0x10]; 940 941 u8 reserved_at_40[0xc0]; 942 }; 943 944 struct mlx5_ifc_sync_steering_out_bits { 945 u8 status[0x8]; 946 u8 reserved_at_8[0x18]; 947 948 u8 syndrome[0x20]; 949 950 u8 reserved_at_40[0x40]; 951 }; 952 953 struct mlx5_ifc_device_mem_cap_bits { 954 u8 memic[0x1]; 955 u8 reserved_at_1[0x1f]; 956 957 u8 reserved_at_20[0xb]; 958 u8 log_min_memic_alloc_size[0x5]; 959 u8 reserved_at_30[0x8]; 960 u8 log_max_memic_addr_alignment[0x8]; 961 962 u8 memic_bar_start_addr[0x40]; 963 964 u8 memic_bar_size[0x20]; 965 966 u8 max_memic_size[0x20]; 967 968 u8 steering_sw_icm_start_address[0x40]; 969 970 u8 reserved_at_100[0x8]; 971 u8 log_header_modify_sw_icm_size[0x8]; 972 u8 reserved_at_110[0x2]; 973 u8 log_sw_icm_alloc_granularity[0x6]; 974 u8 log_steering_sw_icm_size[0x8]; 975 976 u8 reserved_at_120[0x20]; 977 978 u8 header_modify_sw_icm_start_address[0x40]; 979 980 u8 reserved_at_180[0x680]; 981 }; 982 983 struct mlx5_ifc_device_event_cap_bits { 984 u8 user_affiliated_events[4][0x40]; 985 986 u8 user_unaffiliated_events[4][0x40]; 987 }; 988 989 struct mlx5_ifc_virtio_emulation_cap_bits { 990 u8 desc_tunnel_offload_type[0x1]; 991 u8 eth_frame_offload_type[0x1]; 992 u8 virtio_version_1_0[0x1]; 993 u8 device_features_bits_mask[0xd]; 994 u8 event_mode[0x8]; 995 u8 virtio_queue_type[0x8]; 996 997 u8 max_tunnel_desc[0x10]; 998 u8 reserved_at_30[0x3]; 999 u8 log_doorbell_stride[0x5]; 1000 u8 reserved_at_38[0x3]; 1001 u8 log_doorbell_bar_size[0x5]; 1002 1003 u8 doorbell_bar_offset[0x40]; 1004 1005 u8 max_emulated_devices[0x8]; 1006 u8 max_num_virtio_queues[0x18]; 1007 1008 u8 reserved_at_a0[0x60]; 1009 1010 u8 umem_1_buffer_param_a[0x20]; 1011 1012 u8 umem_1_buffer_param_b[0x20]; 1013 1014 u8 umem_2_buffer_param_a[0x20]; 1015 1016 u8 umem_2_buffer_param_b[0x20]; 1017 1018 u8 umem_3_buffer_param_a[0x20]; 1019 1020 u8 umem_3_buffer_param_b[0x20]; 1021 1022 u8 reserved_at_1c0[0x640]; 1023 }; 1024 1025 enum { 1026 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_QP_1_BYTE = 0x0, 1027 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_QP_2_BYTES = 0x2, 1028 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_QP_4_BYTES = 0x4, 1029 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_QP_8_BYTES = 0x8, 1030 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_QP_16_BYTES = 0x10, 1031 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_QP_32_BYTES = 0x20, 1032 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_QP_64_BYTES = 0x40, 1033 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_QP_128_BYTES = 0x80, 1034 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_QP_256_BYTES = 0x100, 1035 }; 1036 1037 enum { 1038 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_DC_1_BYTE = 0x1, 1039 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_DC_2_BYTES = 0x2, 1040 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_DC_4_BYTES = 0x4, 1041 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_DC_8_BYTES = 0x8, 1042 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_DC_16_BYTES = 0x10, 1043 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_DC_32_BYTES = 0x20, 1044 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_DC_64_BYTES = 0x40, 1045 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_DC_128_BYTES = 0x80, 1046 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_DC_256_BYTES = 0x100, 1047 }; 1048 1049 struct mlx5_ifc_atomic_caps_bits { 1050 u8 reserved_at_0[0x40]; 1051 1052 u8 atomic_req_8B_endianness_mode[0x2]; 1053 u8 reserved_at_42[0x4]; 1054 u8 supported_atomic_req_8B_endianness_mode_1[0x1]; 1055 1056 u8 reserved_at_47[0x19]; 1057 1058 u8 reserved_at_60[0x20]; 1059 1060 u8 reserved_at_80[0x10]; 1061 u8 atomic_operations[0x10]; 1062 1063 u8 reserved_at_a0[0x10]; 1064 u8 atomic_size_qp[0x10]; 1065 1066 u8 reserved_at_c0[0x10]; 1067 u8 atomic_size_dc[0x10]; 1068 1069 u8 reserved_at_e0[0x720]; 1070 }; 1071 1072 struct mlx5_ifc_odp_cap_bits { 1073 u8 reserved_at_0[0x40]; 1074 1075 u8 sig[0x1]; 1076 u8 reserved_at_41[0x1f]; 1077 1078 u8 reserved_at_60[0x20]; 1079 1080 struct mlx5_ifc_odp_per_transport_service_cap_bits rc_odp_caps; 1081 1082 struct mlx5_ifc_odp_per_transport_service_cap_bits uc_odp_caps; 1083 1084 struct mlx5_ifc_odp_per_transport_service_cap_bits ud_odp_caps; 1085 1086 struct mlx5_ifc_odp_per_transport_service_cap_bits xrc_odp_caps; 1087 1088 struct mlx5_ifc_odp_per_transport_service_cap_bits dc_odp_caps; 1089 1090 u8 reserved_at_120[0x6E0]; 1091 }; 1092 1093 struct mlx5_ifc_calc_op { 1094 u8 reserved_at_0[0x10]; 1095 u8 reserved_at_10[0x9]; 1096 u8 op_swap_endianness[0x1]; 1097 u8 op_min[0x1]; 1098 u8 op_xor[0x1]; 1099 u8 op_or[0x1]; 1100 u8 op_and[0x1]; 1101 u8 op_max[0x1]; 1102 u8 op_add[0x1]; 1103 }; 1104 1105 struct mlx5_ifc_vector_calc_cap_bits { 1106 u8 calc_matrix[0x1]; 1107 u8 reserved_at_1[0x1f]; 1108 u8 reserved_at_20[0x8]; 1109 u8 max_vec_count[0x8]; 1110 u8 reserved_at_30[0xd]; 1111 u8 max_chunk_size[0x3]; 1112 struct mlx5_ifc_calc_op calc0; 1113 struct mlx5_ifc_calc_op calc1; 1114 struct mlx5_ifc_calc_op calc2; 1115 struct mlx5_ifc_calc_op calc3; 1116 1117 u8 reserved_at_c0[0x720]; 1118 }; 1119 1120 struct mlx5_ifc_tls_cap_bits { 1121 u8 tls_1_2_aes_gcm_128[0x1]; 1122 u8 tls_1_3_aes_gcm_128[0x1]; 1123 u8 tls_1_2_aes_gcm_256[0x1]; 1124 u8 tls_1_3_aes_gcm_256[0x1]; 1125 u8 reserved_at_4[0x1c]; 1126 1127 u8 reserved_at_20[0x7e0]; 1128 }; 1129 1130 struct mlx5_ifc_ipsec_cap_bits { 1131 u8 ipsec_full_offload[0x1]; 1132 u8 ipsec_crypto_offload[0x1]; 1133 u8 ipsec_esn[0x1]; 1134 u8 ipsec_crypto_esp_aes_gcm_256_encrypt[0x1]; 1135 u8 ipsec_crypto_esp_aes_gcm_128_encrypt[0x1]; 1136 u8 ipsec_crypto_esp_aes_gcm_256_decrypt[0x1]; 1137 u8 ipsec_crypto_esp_aes_gcm_128_decrypt[0x1]; 1138 u8 reserved_at_7[0x4]; 1139 u8 log_max_ipsec_offload[0x5]; 1140 u8 reserved_at_10[0x10]; 1141 1142 u8 min_log_ipsec_full_replay_window[0x8]; 1143 u8 max_log_ipsec_full_replay_window[0x8]; 1144 u8 reserved_at_30[0x7d0]; 1145 }; 1146 1147 enum { 1148 MLX5_WQ_TYPE_LINKED_LIST = 0x0, 1149 MLX5_WQ_TYPE_CYCLIC = 0x1, 1150 MLX5_WQ_TYPE_LINKED_LIST_STRIDING_RQ = 0x2, 1151 MLX5_WQ_TYPE_CYCLIC_STRIDING_RQ = 0x3, 1152 }; 1153 1154 enum { 1155 MLX5_WQ_END_PAD_MODE_NONE = 0x0, 1156 MLX5_WQ_END_PAD_MODE_ALIGN = 0x1, 1157 }; 1158 1159 enum { 1160 MLX5_CMD_HCA_CAP_GID_TABLE_SIZE_8_GID_ENTRIES = 0x0, 1161 MLX5_CMD_HCA_CAP_GID_TABLE_SIZE_16_GID_ENTRIES = 0x1, 1162 MLX5_CMD_HCA_CAP_GID_TABLE_SIZE_32_GID_ENTRIES = 0x2, 1163 MLX5_CMD_HCA_CAP_GID_TABLE_SIZE_64_GID_ENTRIES = 0x3, 1164 MLX5_CMD_HCA_CAP_GID_TABLE_SIZE_128_GID_ENTRIES = 0x4, 1165 }; 1166 1167 enum { 1168 MLX5_CMD_HCA_CAP_PKEY_TABLE_SIZE_128_ENTRIES = 0x0, 1169 MLX5_CMD_HCA_CAP_PKEY_TABLE_SIZE_256_ENTRIES = 0x1, 1170 MLX5_CMD_HCA_CAP_PKEY_TABLE_SIZE_512_ENTRIES = 0x2, 1171 MLX5_CMD_HCA_CAP_PKEY_TABLE_SIZE_1K_ENTRIES = 0x3, 1172 MLX5_CMD_HCA_CAP_PKEY_TABLE_SIZE_2K_ENTRIES = 0x4, 1173 MLX5_CMD_HCA_CAP_PKEY_TABLE_SIZE_4K_ENTRIES = 0x5, 1174 }; 1175 1176 enum { 1177 MLX5_CMD_HCA_CAP_PORT_TYPE_IB = 0x0, 1178 MLX5_CMD_HCA_CAP_PORT_TYPE_ETHERNET = 0x1, 1179 }; 1180 1181 enum { 1182 MLX5_CMD_HCA_CAP_CMDIF_CHECKSUM_DISABLED = 0x0, 1183 MLX5_CMD_HCA_CAP_CMDIF_CHECKSUM_INITIAL_STATE = 0x1, 1184 MLX5_CMD_HCA_CAP_CMDIF_CHECKSUM_ENABLED = 0x3, 1185 }; 1186 1187 enum { 1188 MLX5_CAP_PORT_TYPE_IB = 0x0, 1189 MLX5_CAP_PORT_TYPE_ETH = 0x1, 1190 }; 1191 1192 enum { 1193 MLX5_CAP_UMR_FENCE_STRONG = 0x0, 1194 MLX5_CAP_UMR_FENCE_SMALL = 0x1, 1195 MLX5_CAP_UMR_FENCE_NONE = 0x2, 1196 }; 1197 1198 enum { 1199 MLX5_FLEX_PARSER_GENEVE_ENABLED = 1 << 3, 1200 MLX5_FLEX_PARSER_VXLAN_GPE_ENABLED = 1 << 7, 1201 MLX5_FLEX_PARSER_ICMP_V4_ENABLED = 1 << 8, 1202 MLX5_FLEX_PARSER_ICMP_V6_ENABLED = 1 << 9, 1203 }; 1204 1205 enum { 1206 MLX5_UCTX_CAP_RAW_TX = 1UL << 0, 1207 MLX5_UCTX_CAP_INTERNAL_DEV_RES = 1UL << 1, 1208 }; 1209 1210 #define MLX5_FC_BULK_SIZE_FACTOR 128 1211 1212 enum mlx5_fc_bulk_alloc_bitmask { 1213 MLX5_FC_BULK_128 = (1 << 0), 1214 MLX5_FC_BULK_256 = (1 << 1), 1215 MLX5_FC_BULK_512 = (1 << 2), 1216 MLX5_FC_BULK_1024 = (1 << 3), 1217 MLX5_FC_BULK_2048 = (1 << 4), 1218 MLX5_FC_BULK_4096 = (1 << 5), 1219 MLX5_FC_BULK_8192 = (1 << 6), 1220 MLX5_FC_BULK_16384 = (1 << 7), 1221 }; 1222 1223 #define MLX5_FC_BULK_NUM_FCS(fc_enum) (MLX5_FC_BULK_SIZE_FACTOR * (fc_enum)) 1224 1225 struct mlx5_ifc_cmd_hca_cap_bits { 1226 u8 reserved_at_0[0x30]; 1227 u8 vhca_id[0x10]; 1228 1229 u8 reserved_at_40[0x40]; 1230 1231 u8 log_max_srq_sz[0x8]; 1232 u8 log_max_qp_sz[0x8]; 1233 u8 event_cap[0x1]; 1234 u8 reserved_at_91[0x7]; 1235 u8 prio_tag_required[0x1]; 1236 u8 reserved_at_99[0x2]; 1237 u8 log_max_qp[0x5]; 1238 1239 u8 reserved_at_a0[0x3]; 1240 u8 ece_support[0x1]; 1241 u8 reserved_at_a4[0x7]; 1242 u8 log_max_srq[0x5]; 1243 u8 reserved_at_b0[0x10]; 1244 1245 u8 max_sgl_for_optimized_performance[0x8]; 1246 u8 log_max_cq_sz[0x8]; 1247 u8 relaxed_ordering_write_umr[0x1]; 1248 u8 relaxed_ordering_read_umr[0x1]; 1249 u8 reserved_at_d2[0x7]; 1250 u8 virtio_net_device_emualtion_manager[0x1]; 1251 u8 virtio_blk_device_emualtion_manager[0x1]; 1252 u8 log_max_cq[0x5]; 1253 1254 u8 log_max_eq_sz[0x8]; 1255 u8 relaxed_ordering_write[0x1]; 1256 u8 relaxed_ordering_read[0x1]; 1257 u8 log_max_mkey[0x6]; 1258 u8 reserved_at_f0[0x8]; 1259 u8 dump_fill_mkey[0x1]; 1260 u8 reserved_at_f9[0x2]; 1261 u8 fast_teardown[0x1]; 1262 u8 log_max_eq[0x4]; 1263 1264 u8 max_indirection[0x8]; 1265 u8 fixed_buffer_size[0x1]; 1266 u8 log_max_mrw_sz[0x7]; 1267 u8 force_teardown[0x1]; 1268 u8 reserved_at_111[0x1]; 1269 u8 log_max_bsf_list_size[0x6]; 1270 u8 umr_extended_translation_offset[0x1]; 1271 u8 null_mkey[0x1]; 1272 u8 log_max_klm_list_size[0x6]; 1273 1274 u8 reserved_at_120[0xa]; 1275 u8 log_max_ra_req_dc[0x6]; 1276 u8 reserved_at_130[0xa]; 1277 u8 log_max_ra_res_dc[0x6]; 1278 1279 u8 reserved_at_140[0x6]; 1280 u8 release_all_pages[0x1]; 1281 u8 reserved_at_147[0x2]; 1282 u8 roce_accl[0x1]; 1283 u8 log_max_ra_req_qp[0x6]; 1284 u8 reserved_at_150[0xa]; 1285 u8 log_max_ra_res_qp[0x6]; 1286 1287 u8 end_pad[0x1]; 1288 u8 cc_query_allowed[0x1]; 1289 u8 cc_modify_allowed[0x1]; 1290 u8 start_pad[0x1]; 1291 u8 cache_line_128byte[0x1]; 1292 u8 reserved_at_165[0x4]; 1293 u8 rts2rts_qp_counters_set_id[0x1]; 1294 u8 reserved_at_16a[0x2]; 1295 u8 vnic_env_int_rq_oob[0x1]; 1296 u8 sbcam_reg[0x1]; 1297 u8 reserved_at_16e[0x1]; 1298 u8 qcam_reg[0x1]; 1299 u8 gid_table_size[0x10]; 1300 1301 u8 out_of_seq_cnt[0x1]; 1302 u8 vport_counters[0x1]; 1303 u8 retransmission_q_counters[0x1]; 1304 u8 debug[0x1]; 1305 u8 modify_rq_counter_set_id[0x1]; 1306 u8 rq_delay_drop[0x1]; 1307 u8 max_qp_cnt[0xa]; 1308 u8 pkey_table_size[0x10]; 1309 1310 u8 vport_group_manager[0x1]; 1311 u8 vhca_group_manager[0x1]; 1312 u8 ib_virt[0x1]; 1313 u8 eth_virt[0x1]; 1314 u8 vnic_env_queue_counters[0x1]; 1315 u8 ets[0x1]; 1316 u8 nic_flow_table[0x1]; 1317 u8 eswitch_manager[0x1]; 1318 u8 device_memory[0x1]; 1319 u8 mcam_reg[0x1]; 1320 u8 pcam_reg[0x1]; 1321 u8 local_ca_ack_delay[0x5]; 1322 u8 port_module_event[0x1]; 1323 u8 enhanced_error_q_counters[0x1]; 1324 u8 ports_check[0x1]; 1325 u8 reserved_at_1b3[0x1]; 1326 u8 disable_link_up[0x1]; 1327 u8 beacon_led[0x1]; 1328 u8 port_type[0x2]; 1329 u8 num_ports[0x8]; 1330 1331 u8 reserved_at_1c0[0x1]; 1332 u8 pps[0x1]; 1333 u8 pps_modify[0x1]; 1334 u8 log_max_msg[0x5]; 1335 u8 reserved_at_1c8[0x4]; 1336 u8 max_tc[0x4]; 1337 u8 temp_warn_event[0x1]; 1338 u8 dcbx[0x1]; 1339 u8 general_notification_event[0x1]; 1340 u8 reserved_at_1d3[0x2]; 1341 u8 fpga[0x1]; 1342 u8 rol_s[0x1]; 1343 u8 rol_g[0x1]; 1344 u8 reserved_at_1d8[0x1]; 1345 u8 wol_s[0x1]; 1346 u8 wol_g[0x1]; 1347 u8 wol_a[0x1]; 1348 u8 wol_b[0x1]; 1349 u8 wol_m[0x1]; 1350 u8 wol_u[0x1]; 1351 u8 wol_p[0x1]; 1352 1353 u8 stat_rate_support[0x10]; 1354 u8 reserved_at_1f0[0x1]; 1355 u8 pci_sync_for_fw_update_event[0x1]; 1356 u8 reserved_at_1f2[0x6]; 1357 u8 init2_lag_tx_port_affinity[0x1]; 1358 u8 reserved_at_1fa[0x3]; 1359 u8 cqe_version[0x4]; 1360 1361 u8 compact_address_vector[0x1]; 1362 u8 striding_rq[0x1]; 1363 u8 reserved_at_202[0x1]; 1364 u8 ipoib_enhanced_offloads[0x1]; 1365 u8 ipoib_basic_offloads[0x1]; 1366 u8 reserved_at_205[0x1]; 1367 u8 repeated_block_disabled[0x1]; 1368 u8 umr_modify_entity_size_disabled[0x1]; 1369 u8 umr_modify_atomic_disabled[0x1]; 1370 u8 umr_indirect_mkey_disabled[0x1]; 1371 u8 umr_fence[0x2]; 1372 u8 dc_req_scat_data_cqe[0x1]; 1373 u8 reserved_at_20d[0x2]; 1374 u8 drain_sigerr[0x1]; 1375 u8 cmdif_checksum[0x2]; 1376 u8 sigerr_cqe[0x1]; 1377 u8 reserved_at_213[0x1]; 1378 u8 wq_signature[0x1]; 1379 u8 sctr_data_cqe[0x1]; 1380 u8 reserved_at_216[0x1]; 1381 u8 sho[0x1]; 1382 u8 tph[0x1]; 1383 u8 rf[0x1]; 1384 u8 dct[0x1]; 1385 u8 qos[0x1]; 1386 u8 eth_net_offloads[0x1]; 1387 u8 roce[0x1]; 1388 u8 atomic[0x1]; 1389 u8 reserved_at_21f[0x1]; 1390 1391 u8 cq_oi[0x1]; 1392 u8 cq_resize[0x1]; 1393 u8 cq_moderation[0x1]; 1394 u8 reserved_at_223[0x3]; 1395 u8 cq_eq_remap[0x1]; 1396 u8 pg[0x1]; 1397 u8 block_lb_mc[0x1]; 1398 u8 reserved_at_229[0x1]; 1399 u8 scqe_break_moderation[0x1]; 1400 u8 cq_period_start_from_cqe[0x1]; 1401 u8 cd[0x1]; 1402 u8 reserved_at_22d[0x1]; 1403 u8 apm[0x1]; 1404 u8 vector_calc[0x1]; 1405 u8 umr_ptr_rlky[0x1]; 1406 u8 imaicl[0x1]; 1407 u8 qp_packet_based[0x1]; 1408 u8 reserved_at_233[0x3]; 1409 u8 qkv[0x1]; 1410 u8 pkv[0x1]; 1411 u8 set_deth_sqpn[0x1]; 1412 u8 reserved_at_239[0x3]; 1413 u8 xrc[0x1]; 1414 u8 ud[0x1]; 1415 u8 uc[0x1]; 1416 u8 rc[0x1]; 1417 1418 u8 uar_4k[0x1]; 1419 u8 reserved_at_241[0x9]; 1420 u8 uar_sz[0x6]; 1421 u8 reserved_at_250[0x8]; 1422 u8 log_pg_sz[0x8]; 1423 1424 u8 bf[0x1]; 1425 u8 driver_version[0x1]; 1426 u8 pad_tx_eth_packet[0x1]; 1427 u8 reserved_at_263[0x3]; 1428 u8 mkey_by_name[0x1]; 1429 u8 reserved_at_267[0x4]; 1430 1431 u8 log_bf_reg_size[0x5]; 1432 1433 u8 reserved_at_270[0x8]; 1434 u8 lag_tx_port_affinity[0x1]; 1435 u8 reserved_at_279[0x2]; 1436 u8 lag_master[0x1]; 1437 u8 num_lag_ports[0x4]; 1438 1439 u8 reserved_at_280[0x10]; 1440 u8 max_wqe_sz_sq[0x10]; 1441 1442 u8 reserved_at_2a0[0x10]; 1443 u8 max_wqe_sz_rq[0x10]; 1444 1445 u8 max_flow_counter_31_16[0x10]; 1446 u8 max_wqe_sz_sq_dc[0x10]; 1447 1448 u8 reserved_at_2e0[0x7]; 1449 u8 max_qp_mcg[0x19]; 1450 1451 u8 reserved_at_300[0x10]; 1452 u8 flow_counter_bulk_alloc[0x8]; 1453 u8 log_max_mcg[0x8]; 1454 1455 u8 reserved_at_320[0x3]; 1456 u8 log_max_transport_domain[0x5]; 1457 u8 reserved_at_328[0x3]; 1458 u8 log_max_pd[0x5]; 1459 u8 reserved_at_330[0xb]; 1460 u8 log_max_xrcd[0x5]; 1461 1462 u8 nic_receive_steering_discard[0x1]; 1463 u8 receive_discard_vport_down[0x1]; 1464 u8 transmit_discard_vport_down[0x1]; 1465 u8 reserved_at_343[0x5]; 1466 u8 log_max_flow_counter_bulk[0x8]; 1467 u8 max_flow_counter_15_0[0x10]; 1468 1469 1470 u8 reserved_at_360[0x3]; 1471 u8 log_max_rq[0x5]; 1472 u8 reserved_at_368[0x3]; 1473 u8 log_max_sq[0x5]; 1474 u8 reserved_at_370[0x3]; 1475 u8 log_max_tir[0x5]; 1476 u8 reserved_at_378[0x3]; 1477 u8 log_max_tis[0x5]; 1478 1479 u8 basic_cyclic_rcv_wqe[0x1]; 1480 u8 reserved_at_381[0x2]; 1481 u8 log_max_rmp[0x5]; 1482 u8 reserved_at_388[0x3]; 1483 u8 log_max_rqt[0x5]; 1484 u8 reserved_at_390[0x3]; 1485 u8 log_max_rqt_size[0x5]; 1486 u8 reserved_at_398[0x3]; 1487 u8 log_max_tis_per_sq[0x5]; 1488 1489 u8 ext_stride_num_range[0x1]; 1490 u8 reserved_at_3a1[0x2]; 1491 u8 log_max_stride_sz_rq[0x5]; 1492 u8 reserved_at_3a8[0x3]; 1493 u8 log_min_stride_sz_rq[0x5]; 1494 u8 reserved_at_3b0[0x3]; 1495 u8 log_max_stride_sz_sq[0x5]; 1496 u8 reserved_at_3b8[0x3]; 1497 u8 log_min_stride_sz_sq[0x5]; 1498 1499 u8 hairpin[0x1]; 1500 u8 reserved_at_3c1[0x2]; 1501 u8 log_max_hairpin_queues[0x5]; 1502 u8 reserved_at_3c8[0x3]; 1503 u8 log_max_hairpin_wq_data_sz[0x5]; 1504 u8 reserved_at_3d0[0x3]; 1505 u8 log_max_hairpin_num_packets[0x5]; 1506 u8 reserved_at_3d8[0x3]; 1507 u8 log_max_wq_sz[0x5]; 1508 1509 u8 nic_vport_change_event[0x1]; 1510 u8 disable_local_lb_uc[0x1]; 1511 u8 disable_local_lb_mc[0x1]; 1512 u8 log_min_hairpin_wq_data_sz[0x5]; 1513 u8 reserved_at_3e8[0x3]; 1514 u8 log_max_vlan_list[0x5]; 1515 u8 reserved_at_3f0[0x3]; 1516 u8 log_max_current_mc_list[0x5]; 1517 u8 reserved_at_3f8[0x3]; 1518 u8 log_max_current_uc_list[0x5]; 1519 1520 u8 general_obj_types[0x40]; 1521 1522 u8 reserved_at_440[0x20]; 1523 1524 u8 reserved_at_460[0x3]; 1525 u8 log_max_uctx[0x5]; 1526 u8 reserved_at_468[0x2]; 1527 u8 ipsec_offload[0x1]; 1528 u8 log_max_umem[0x5]; 1529 u8 max_num_eqs[0x10]; 1530 1531 u8 reserved_at_480[0x1]; 1532 u8 tls_tx[0x1]; 1533 u8 tls_rx[0x1]; 1534 u8 log_max_l2_table[0x5]; 1535 u8 reserved_at_488[0x8]; 1536 u8 log_uar_page_sz[0x10]; 1537 1538 u8 reserved_at_4a0[0x20]; 1539 u8 device_frequency_mhz[0x20]; 1540 u8 device_frequency_khz[0x20]; 1541 1542 u8 reserved_at_500[0x20]; 1543 u8 num_of_uars_per_page[0x20]; 1544 1545 u8 flex_parser_protocols[0x20]; 1546 1547 u8 max_geneve_tlv_options[0x8]; 1548 u8 reserved_at_568[0x3]; 1549 u8 max_geneve_tlv_option_data_len[0x5]; 1550 u8 reserved_at_570[0x10]; 1551 1552 u8 reserved_at_580[0x33]; 1553 u8 log_max_dek[0x5]; 1554 u8 reserved_at_5b8[0x4]; 1555 u8 mini_cqe_resp_stride_index[0x1]; 1556 u8 cqe_128_always[0x1]; 1557 u8 cqe_compression_128[0x1]; 1558 u8 cqe_compression[0x1]; 1559 1560 u8 cqe_compression_timeout[0x10]; 1561 u8 cqe_compression_max_num[0x10]; 1562 1563 u8 reserved_at_5e0[0x10]; 1564 u8 tag_matching[0x1]; 1565 u8 rndv_offload_rc[0x1]; 1566 u8 rndv_offload_dc[0x1]; 1567 u8 log_tag_matching_list_sz[0x5]; 1568 u8 reserved_at_5f8[0x3]; 1569 u8 log_max_xrq[0x5]; 1570 1571 u8 affiliate_nic_vport_criteria[0x8]; 1572 u8 native_port_num[0x8]; 1573 u8 num_vhca_ports[0x8]; 1574 u8 reserved_at_618[0x6]; 1575 u8 sw_owner_id[0x1]; 1576 u8 reserved_at_61f[0x1]; 1577 1578 u8 max_num_of_monitor_counters[0x10]; 1579 u8 num_ppcnt_monitor_counters[0x10]; 1580 1581 u8 reserved_at_640[0x10]; 1582 u8 num_q_monitor_counters[0x10]; 1583 1584 u8 reserved_at_660[0x20]; 1585 1586 u8 sf[0x1]; 1587 u8 sf_set_partition[0x1]; 1588 u8 reserved_at_682[0x1]; 1589 u8 log_max_sf[0x5]; 1590 u8 reserved_at_688[0x8]; 1591 u8 log_min_sf_size[0x8]; 1592 u8 max_num_sf_partitions[0x8]; 1593 1594 u8 uctx_cap[0x20]; 1595 1596 u8 reserved_at_6c0[0x4]; 1597 u8 flex_parser_id_geneve_tlv_option_0[0x4]; 1598 u8 flex_parser_id_icmp_dw1[0x4]; 1599 u8 flex_parser_id_icmp_dw0[0x4]; 1600 u8 flex_parser_id_icmpv6_dw1[0x4]; 1601 u8 flex_parser_id_icmpv6_dw0[0x4]; 1602 u8 flex_parser_id_outer_first_mpls_over_gre[0x4]; 1603 u8 flex_parser_id_outer_first_mpls_over_udp_label[0x4]; 1604 1605 u8 reserved_at_6e0[0x10]; 1606 u8 sf_base_id[0x10]; 1607 1608 u8 reserved_at_700[0x80]; 1609 u8 vhca_tunnel_commands[0x40]; 1610 u8 reserved_at_7c0[0x40]; 1611 }; 1612 1613 enum mlx5_flow_destination_type { 1614 MLX5_FLOW_DESTINATION_TYPE_VPORT = 0x0, 1615 MLX5_FLOW_DESTINATION_TYPE_FLOW_TABLE = 0x1, 1616 MLX5_FLOW_DESTINATION_TYPE_TIR = 0x2, 1617 1618 MLX5_FLOW_DESTINATION_TYPE_PORT = 0x99, 1619 MLX5_FLOW_DESTINATION_TYPE_COUNTER = 0x100, 1620 MLX5_FLOW_DESTINATION_TYPE_FLOW_TABLE_NUM = 0x101, 1621 }; 1622 1623 enum mlx5_flow_table_miss_action { 1624 MLX5_FLOW_TABLE_MISS_ACTION_DEF, 1625 MLX5_FLOW_TABLE_MISS_ACTION_FWD, 1626 MLX5_FLOW_TABLE_MISS_ACTION_SWITCH_DOMAIN, 1627 }; 1628 1629 struct mlx5_ifc_dest_format_struct_bits { 1630 u8 destination_type[0x8]; 1631 u8 destination_id[0x18]; 1632 1633 u8 destination_eswitch_owner_vhca_id_valid[0x1]; 1634 u8 packet_reformat[0x1]; 1635 u8 reserved_at_22[0xe]; 1636 u8 destination_eswitch_owner_vhca_id[0x10]; 1637 }; 1638 1639 struct mlx5_ifc_flow_counter_list_bits { 1640 u8 flow_counter_id[0x20]; 1641 1642 u8 reserved_at_20[0x20]; 1643 }; 1644 1645 struct mlx5_ifc_extended_dest_format_bits { 1646 struct mlx5_ifc_dest_format_struct_bits destination_entry; 1647 1648 u8 packet_reformat_id[0x20]; 1649 1650 u8 reserved_at_60[0x20]; 1651 }; 1652 1653 union mlx5_ifc_dest_format_struct_flow_counter_list_auto_bits { 1654 struct mlx5_ifc_extended_dest_format_bits extended_dest_format; 1655 struct mlx5_ifc_flow_counter_list_bits flow_counter_list; 1656 }; 1657 1658 struct mlx5_ifc_fte_match_param_bits { 1659 struct mlx5_ifc_fte_match_set_lyr_2_4_bits outer_headers; 1660 1661 struct mlx5_ifc_fte_match_set_misc_bits misc_parameters; 1662 1663 struct mlx5_ifc_fte_match_set_lyr_2_4_bits inner_headers; 1664 1665 struct mlx5_ifc_fte_match_set_misc2_bits misc_parameters_2; 1666 1667 struct mlx5_ifc_fte_match_set_misc3_bits misc_parameters_3; 1668 1669 u8 reserved_at_a00[0x600]; 1670 }; 1671 1672 enum { 1673 MLX5_RX_HASH_FIELD_SELECT_SELECTED_FIELDS_SRC_IP = 0x0, 1674 MLX5_RX_HASH_FIELD_SELECT_SELECTED_FIELDS_DST_IP = 0x1, 1675 MLX5_RX_HASH_FIELD_SELECT_SELECTED_FIELDS_L4_SPORT = 0x2, 1676 MLX5_RX_HASH_FIELD_SELECT_SELECTED_FIELDS_L4_DPORT = 0x3, 1677 MLX5_RX_HASH_FIELD_SELECT_SELECTED_FIELDS_IPSEC_SPI = 0x4, 1678 }; 1679 1680 struct mlx5_ifc_rx_hash_field_select_bits { 1681 u8 l3_prot_type[0x1]; 1682 u8 l4_prot_type[0x1]; 1683 u8 selected_fields[0x1e]; 1684 }; 1685 1686 enum { 1687 MLX5_WQ_WQ_TYPE_WQ_LINKED_LIST = 0x0, 1688 MLX5_WQ_WQ_TYPE_WQ_CYCLIC = 0x1, 1689 }; 1690 1691 enum { 1692 MLX5_WQ_END_PADDING_MODE_END_PAD_NONE = 0x0, 1693 MLX5_WQ_END_PADDING_MODE_END_PAD_ALIGN = 0x1, 1694 }; 1695 1696 struct mlx5_ifc_wq_bits { 1697 u8 wq_type[0x4]; 1698 u8 wq_signature[0x1]; 1699 u8 end_padding_mode[0x2]; 1700 u8 cd_slave[0x1]; 1701 u8 reserved_at_8[0x18]; 1702 1703 u8 hds_skip_first_sge[0x1]; 1704 u8 log2_hds_buf_size[0x3]; 1705 u8 reserved_at_24[0x7]; 1706 u8 page_offset[0x5]; 1707 u8 lwm[0x10]; 1708 1709 u8 reserved_at_40[0x8]; 1710 u8 pd[0x18]; 1711 1712 u8 reserved_at_60[0x8]; 1713 u8 uar_page[0x18]; 1714 1715 u8 dbr_addr[0x40]; 1716 1717 u8 hw_counter[0x20]; 1718 1719 u8 sw_counter[0x20]; 1720 1721 u8 reserved_at_100[0xc]; 1722 u8 log_wq_stride[0x4]; 1723 u8 reserved_at_110[0x3]; 1724 u8 log_wq_pg_sz[0x5]; 1725 u8 reserved_at_118[0x3]; 1726 u8 log_wq_sz[0x5]; 1727 1728 u8 dbr_umem_valid[0x1]; 1729 u8 wq_umem_valid[0x1]; 1730 u8 reserved_at_122[0x1]; 1731 u8 log_hairpin_num_packets[0x5]; 1732 u8 reserved_at_128[0x3]; 1733 u8 log_hairpin_data_sz[0x5]; 1734 1735 u8 reserved_at_130[0x4]; 1736 u8 log_wqe_num_of_strides[0x4]; 1737 u8 two_byte_shift_en[0x1]; 1738 u8 reserved_at_139[0x4]; 1739 u8 log_wqe_stride_size[0x3]; 1740 1741 u8 reserved_at_140[0x4c0]; 1742 1743 struct mlx5_ifc_cmd_pas_bits pas[]; 1744 }; 1745 1746 struct mlx5_ifc_rq_num_bits { 1747 u8 reserved_at_0[0x8]; 1748 u8 rq_num[0x18]; 1749 }; 1750 1751 struct mlx5_ifc_mac_address_layout_bits { 1752 u8 reserved_at_0[0x10]; 1753 u8 mac_addr_47_32[0x10]; 1754 1755 u8 mac_addr_31_0[0x20]; 1756 }; 1757 1758 struct mlx5_ifc_vlan_layout_bits { 1759 u8 reserved_at_0[0x14]; 1760 u8 vlan[0x0c]; 1761 1762 u8 reserved_at_20[0x20]; 1763 }; 1764 1765 struct mlx5_ifc_cong_control_r_roce_ecn_np_bits { 1766 u8 reserved_at_0[0xa0]; 1767 1768 u8 min_time_between_cnps[0x20]; 1769 1770 u8 reserved_at_c0[0x12]; 1771 u8 cnp_dscp[0x6]; 1772 u8 reserved_at_d8[0x4]; 1773 u8 cnp_prio_mode[0x1]; 1774 u8 cnp_802p_prio[0x3]; 1775 1776 u8 reserved_at_e0[0x720]; 1777 }; 1778 1779 struct mlx5_ifc_cong_control_r_roce_ecn_rp_bits { 1780 u8 reserved_at_0[0x60]; 1781 1782 u8 reserved_at_60[0x4]; 1783 u8 clamp_tgt_rate[0x1]; 1784 u8 reserved_at_65[0x3]; 1785 u8 clamp_tgt_rate_after_time_inc[0x1]; 1786 u8 reserved_at_69[0x17]; 1787 1788 u8 reserved_at_80[0x20]; 1789 1790 u8 rpg_time_reset[0x20]; 1791 1792 u8 rpg_byte_reset[0x20]; 1793 1794 u8 rpg_threshold[0x20]; 1795 1796 u8 rpg_max_rate[0x20]; 1797 1798 u8 rpg_ai_rate[0x20]; 1799 1800 u8 rpg_hai_rate[0x20]; 1801 1802 u8 rpg_gd[0x20]; 1803 1804 u8 rpg_min_dec_fac[0x20]; 1805 1806 u8 rpg_min_rate[0x20]; 1807 1808 u8 reserved_at_1c0[0xe0]; 1809 1810 u8 rate_to_set_on_first_cnp[0x20]; 1811 1812 u8 dce_tcp_g[0x20]; 1813 1814 u8 dce_tcp_rtt[0x20]; 1815 1816 u8 rate_reduce_monitor_period[0x20]; 1817 1818 u8 reserved_at_320[0x20]; 1819 1820 u8 initial_alpha_value[0x20]; 1821 1822 u8 reserved_at_360[0x4a0]; 1823 }; 1824 1825 struct mlx5_ifc_cong_control_802_1qau_rp_bits { 1826 u8 reserved_at_0[0x80]; 1827 1828 u8 rppp_max_rps[0x20]; 1829 1830 u8 rpg_time_reset[0x20]; 1831 1832 u8 rpg_byte_reset[0x20]; 1833 1834 u8 rpg_threshold[0x20]; 1835 1836 u8 rpg_max_rate[0x20]; 1837 1838 u8 rpg_ai_rate[0x20]; 1839 1840 u8 rpg_hai_rate[0x20]; 1841 1842 u8 rpg_gd[0x20]; 1843 1844 u8 rpg_min_dec_fac[0x20]; 1845 1846 u8 rpg_min_rate[0x20]; 1847 1848 u8 reserved_at_1c0[0x640]; 1849 }; 1850 1851 enum { 1852 MLX5_RESIZE_FIELD_SELECT_RESIZE_FIELD_SELECT_LOG_CQ_SIZE = 0x1, 1853 MLX5_RESIZE_FIELD_SELECT_RESIZE_FIELD_SELECT_PAGE_OFFSET = 0x2, 1854 MLX5_RESIZE_FIELD_SELECT_RESIZE_FIELD_SELECT_LOG_PAGE_SIZE = 0x4, 1855 }; 1856 1857 struct mlx5_ifc_resize_field_select_bits { 1858 u8 resize_field_select[0x20]; 1859 }; 1860 1861 struct mlx5_ifc_resource_dump_bits { 1862 u8 more_dump[0x1]; 1863 u8 inline_dump[0x1]; 1864 u8 reserved_at_2[0xa]; 1865 u8 seq_num[0x4]; 1866 u8 segment_type[0x10]; 1867 1868 u8 reserved_at_20[0x10]; 1869 u8 vhca_id[0x10]; 1870 1871 u8 index1[0x20]; 1872 1873 u8 index2[0x20]; 1874 1875 u8 num_of_obj1[0x10]; 1876 u8 num_of_obj2[0x10]; 1877 1878 u8 reserved_at_a0[0x20]; 1879 1880 u8 device_opaque[0x40]; 1881 1882 u8 mkey[0x20]; 1883 1884 u8 size[0x20]; 1885 1886 u8 address[0x40]; 1887 1888 u8 inline_data[52][0x20]; 1889 }; 1890 1891 struct mlx5_ifc_resource_dump_menu_record_bits { 1892 u8 reserved_at_0[0x4]; 1893 u8 num_of_obj2_supports_active[0x1]; 1894 u8 num_of_obj2_supports_all[0x1]; 1895 u8 must_have_num_of_obj2[0x1]; 1896 u8 support_num_of_obj2[0x1]; 1897 u8 num_of_obj1_supports_active[0x1]; 1898 u8 num_of_obj1_supports_all[0x1]; 1899 u8 must_have_num_of_obj1[0x1]; 1900 u8 support_num_of_obj1[0x1]; 1901 u8 must_have_index2[0x1]; 1902 u8 support_index2[0x1]; 1903 u8 must_have_index1[0x1]; 1904 u8 support_index1[0x1]; 1905 u8 segment_type[0x10]; 1906 1907 u8 segment_name[4][0x20]; 1908 1909 u8 index1_name[4][0x20]; 1910 1911 u8 index2_name[4][0x20]; 1912 }; 1913 1914 struct mlx5_ifc_resource_dump_segment_header_bits { 1915 u8 length_dw[0x10]; 1916 u8 segment_type[0x10]; 1917 }; 1918 1919 struct mlx5_ifc_resource_dump_command_segment_bits { 1920 struct mlx5_ifc_resource_dump_segment_header_bits segment_header; 1921 1922 u8 segment_called[0x10]; 1923 u8 vhca_id[0x10]; 1924 1925 u8 index1[0x20]; 1926 1927 u8 index2[0x20]; 1928 1929 u8 num_of_obj1[0x10]; 1930 u8 num_of_obj2[0x10]; 1931 }; 1932 1933 struct mlx5_ifc_resource_dump_error_segment_bits { 1934 struct mlx5_ifc_resource_dump_segment_header_bits segment_header; 1935 1936 u8 reserved_at_20[0x10]; 1937 u8 syndrome_id[0x10]; 1938 1939 u8 reserved_at_40[0x40]; 1940 1941 u8 error[8][0x20]; 1942 }; 1943 1944 struct mlx5_ifc_resource_dump_info_segment_bits { 1945 struct mlx5_ifc_resource_dump_segment_header_bits segment_header; 1946 1947 u8 reserved_at_20[0x18]; 1948 u8 dump_version[0x8]; 1949 1950 u8 hw_version[0x20]; 1951 1952 u8 fw_version[0x20]; 1953 }; 1954 1955 struct mlx5_ifc_resource_dump_menu_segment_bits { 1956 struct mlx5_ifc_resource_dump_segment_header_bits segment_header; 1957 1958 u8 reserved_at_20[0x10]; 1959 u8 num_of_records[0x10]; 1960 1961 struct mlx5_ifc_resource_dump_menu_record_bits record[]; 1962 }; 1963 1964 struct mlx5_ifc_resource_dump_resource_segment_bits { 1965 struct mlx5_ifc_resource_dump_segment_header_bits segment_header; 1966 1967 u8 reserved_at_20[0x20]; 1968 1969 u8 index1[0x20]; 1970 1971 u8 index2[0x20]; 1972 1973 u8 payload[][0x20]; 1974 }; 1975 1976 struct mlx5_ifc_resource_dump_terminate_segment_bits { 1977 struct mlx5_ifc_resource_dump_segment_header_bits segment_header; 1978 }; 1979 1980 struct mlx5_ifc_menu_resource_dump_response_bits { 1981 struct mlx5_ifc_resource_dump_info_segment_bits info; 1982 struct mlx5_ifc_resource_dump_command_segment_bits cmd; 1983 struct mlx5_ifc_resource_dump_menu_segment_bits menu; 1984 struct mlx5_ifc_resource_dump_terminate_segment_bits terminate; 1985 }; 1986 1987 enum { 1988 MLX5_MODIFY_FIELD_SELECT_MODIFY_FIELD_SELECT_CQ_PERIOD = 0x1, 1989 MLX5_MODIFY_FIELD_SELECT_MODIFY_FIELD_SELECT_CQ_MAX_COUNT = 0x2, 1990 MLX5_MODIFY_FIELD_SELECT_MODIFY_FIELD_SELECT_OI = 0x4, 1991 MLX5_MODIFY_FIELD_SELECT_MODIFY_FIELD_SELECT_C_EQN = 0x8, 1992 }; 1993 1994 struct mlx5_ifc_modify_field_select_bits { 1995 u8 modify_field_select[0x20]; 1996 }; 1997 1998 struct mlx5_ifc_field_select_r_roce_np_bits { 1999 u8 field_select_r_roce_np[0x20]; 2000 }; 2001 2002 struct mlx5_ifc_field_select_r_roce_rp_bits { 2003 u8 field_select_r_roce_rp[0x20]; 2004 }; 2005 2006 enum { 2007 MLX5_FIELD_SELECT_802_1QAU_RP_FIELD_SELECT_8021QAURP_RPPP_MAX_RPS = 0x4, 2008 MLX5_FIELD_SELECT_802_1QAU_RP_FIELD_SELECT_8021QAURP_RPG_TIME_RESET = 0x8, 2009 MLX5_FIELD_SELECT_802_1QAU_RP_FIELD_SELECT_8021QAURP_RPG_BYTE_RESET = 0x10, 2010 MLX5_FIELD_SELECT_802_1QAU_RP_FIELD_SELECT_8021QAURP_RPG_THRESHOLD = 0x20, 2011 MLX5_FIELD_SELECT_802_1QAU_RP_FIELD_SELECT_8021QAURP_RPG_MAX_RATE = 0x40, 2012 MLX5_FIELD_SELECT_802_1QAU_RP_FIELD_SELECT_8021QAURP_RPG_AI_RATE = 0x80, 2013 MLX5_FIELD_SELECT_802_1QAU_RP_FIELD_SELECT_8021QAURP_RPG_HAI_RATE = 0x100, 2014 MLX5_FIELD_SELECT_802_1QAU_RP_FIELD_SELECT_8021QAURP_RPG_GD = 0x200, 2015 MLX5_FIELD_SELECT_802_1QAU_RP_FIELD_SELECT_8021QAURP_RPG_MIN_DEC_FAC = 0x400, 2016 MLX5_FIELD_SELECT_802_1QAU_RP_FIELD_SELECT_8021QAURP_RPG_MIN_RATE = 0x800, 2017 }; 2018 2019 struct mlx5_ifc_field_select_802_1qau_rp_bits { 2020 u8 field_select_8021qaurp[0x20]; 2021 }; 2022 2023 struct mlx5_ifc_phys_layer_cntrs_bits { 2024 u8 time_since_last_clear_high[0x20]; 2025 2026 u8 time_since_last_clear_low[0x20]; 2027 2028 u8 symbol_errors_high[0x20]; 2029 2030 u8 symbol_errors_low[0x20]; 2031 2032 u8 sync_headers_errors_high[0x20]; 2033 2034 u8 sync_headers_errors_low[0x20]; 2035 2036 u8 edpl_bip_errors_lane0_high[0x20]; 2037 2038 u8 edpl_bip_errors_lane0_low[0x20]; 2039 2040 u8 edpl_bip_errors_lane1_high[0x20]; 2041 2042 u8 edpl_bip_errors_lane1_low[0x20]; 2043 2044 u8 edpl_bip_errors_lane2_high[0x20]; 2045 2046 u8 edpl_bip_errors_lane2_low[0x20]; 2047 2048 u8 edpl_bip_errors_lane3_high[0x20]; 2049 2050 u8 edpl_bip_errors_lane3_low[0x20]; 2051 2052 u8 fc_fec_corrected_blocks_lane0_high[0x20]; 2053 2054 u8 fc_fec_corrected_blocks_lane0_low[0x20]; 2055 2056 u8 fc_fec_corrected_blocks_lane1_high[0x20]; 2057 2058 u8 fc_fec_corrected_blocks_lane1_low[0x20]; 2059 2060 u8 fc_fec_corrected_blocks_lane2_high[0x20]; 2061 2062 u8 fc_fec_corrected_blocks_lane2_low[0x20]; 2063 2064 u8 fc_fec_corrected_blocks_lane3_high[0x20]; 2065 2066 u8 fc_fec_corrected_blocks_lane3_low[0x20]; 2067 2068 u8 fc_fec_uncorrectable_blocks_lane0_high[0x20]; 2069 2070 u8 fc_fec_uncorrectable_blocks_lane0_low[0x20]; 2071 2072 u8 fc_fec_uncorrectable_blocks_lane1_high[0x20]; 2073 2074 u8 fc_fec_uncorrectable_blocks_lane1_low[0x20]; 2075 2076 u8 fc_fec_uncorrectable_blocks_lane2_high[0x20]; 2077 2078 u8 fc_fec_uncorrectable_blocks_lane2_low[0x20]; 2079 2080 u8 fc_fec_uncorrectable_blocks_lane3_high[0x20]; 2081 2082 u8 fc_fec_uncorrectable_blocks_lane3_low[0x20]; 2083 2084 u8 rs_fec_corrected_blocks_high[0x20]; 2085 2086 u8 rs_fec_corrected_blocks_low[0x20]; 2087 2088 u8 rs_fec_uncorrectable_blocks_high[0x20]; 2089 2090 u8 rs_fec_uncorrectable_blocks_low[0x20]; 2091 2092 u8 rs_fec_no_errors_blocks_high[0x20]; 2093 2094 u8 rs_fec_no_errors_blocks_low[0x20]; 2095 2096 u8 rs_fec_single_error_blocks_high[0x20]; 2097 2098 u8 rs_fec_single_error_blocks_low[0x20]; 2099 2100 u8 rs_fec_corrected_symbols_total_high[0x20]; 2101 2102 u8 rs_fec_corrected_symbols_total_low[0x20]; 2103 2104 u8 rs_fec_corrected_symbols_lane0_high[0x20]; 2105 2106 u8 rs_fec_corrected_symbols_lane0_low[0x20]; 2107 2108 u8 rs_fec_corrected_symbols_lane1_high[0x20]; 2109 2110 u8 rs_fec_corrected_symbols_lane1_low[0x20]; 2111 2112 u8 rs_fec_corrected_symbols_lane2_high[0x20]; 2113 2114 u8 rs_fec_corrected_symbols_lane2_low[0x20]; 2115 2116 u8 rs_fec_corrected_symbols_lane3_high[0x20]; 2117 2118 u8 rs_fec_corrected_symbols_lane3_low[0x20]; 2119 2120 u8 link_down_events[0x20]; 2121 2122 u8 successful_recovery_events[0x20]; 2123 2124 u8 reserved_at_640[0x180]; 2125 }; 2126 2127 struct mlx5_ifc_phys_layer_statistical_cntrs_bits { 2128 u8 time_since_last_clear_high[0x20]; 2129 2130 u8 time_since_last_clear_low[0x20]; 2131 2132 u8 phy_received_bits_high[0x20]; 2133 2134 u8 phy_received_bits_low[0x20]; 2135 2136 u8 phy_symbol_errors_high[0x20]; 2137 2138 u8 phy_symbol_errors_low[0x20]; 2139 2140 u8 phy_corrected_bits_high[0x20]; 2141 2142 u8 phy_corrected_bits_low[0x20]; 2143 2144 u8 phy_corrected_bits_lane0_high[0x20]; 2145 2146 u8 phy_corrected_bits_lane0_low[0x20]; 2147 2148 u8 phy_corrected_bits_lane1_high[0x20]; 2149 2150 u8 phy_corrected_bits_lane1_low[0x20]; 2151 2152 u8 phy_corrected_bits_lane2_high[0x20]; 2153 2154 u8 phy_corrected_bits_lane2_low[0x20]; 2155 2156 u8 phy_corrected_bits_lane3_high[0x20]; 2157 2158 u8 phy_corrected_bits_lane3_low[0x20]; 2159 2160 u8 reserved_at_200[0x5c0]; 2161 }; 2162 2163 struct mlx5_ifc_ib_port_cntrs_grp_data_layout_bits { 2164 u8 symbol_error_counter[0x10]; 2165 2166 u8 link_error_recovery_counter[0x8]; 2167 2168 u8 link_downed_counter[0x8]; 2169 2170 u8 port_rcv_errors[0x10]; 2171 2172 u8 port_rcv_remote_physical_errors[0x10]; 2173 2174 u8 port_rcv_switch_relay_errors[0x10]; 2175 2176 u8 port_xmit_discards[0x10]; 2177 2178 u8 port_xmit_constraint_errors[0x8]; 2179 2180 u8 port_rcv_constraint_errors[0x8]; 2181 2182 u8 reserved_at_70[0x8]; 2183 2184 u8 link_overrun_errors[0x8]; 2185 2186 u8 reserved_at_80[0x10]; 2187 2188 u8 vl_15_dropped[0x10]; 2189 2190 u8 reserved_at_a0[0x80]; 2191 2192 u8 port_xmit_wait[0x20]; 2193 }; 2194 2195 struct mlx5_ifc_eth_per_tc_prio_grp_data_layout_bits { 2196 u8 transmit_queue_high[0x20]; 2197 2198 u8 transmit_queue_low[0x20]; 2199 2200 u8 no_buffer_discard_uc_high[0x20]; 2201 2202 u8 no_buffer_discard_uc_low[0x20]; 2203 2204 u8 reserved_at_80[0x740]; 2205 }; 2206 2207 struct mlx5_ifc_eth_per_tc_congest_prio_grp_data_layout_bits { 2208 u8 wred_discard_high[0x20]; 2209 2210 u8 wred_discard_low[0x20]; 2211 2212 u8 ecn_marked_tc_high[0x20]; 2213 2214 u8 ecn_marked_tc_low[0x20]; 2215 2216 u8 reserved_at_80[0x740]; 2217 }; 2218 2219 struct mlx5_ifc_eth_per_prio_grp_data_layout_bits { 2220 u8 rx_octets_high[0x20]; 2221 2222 u8 rx_octets_low[0x20]; 2223 2224 u8 reserved_at_40[0xc0]; 2225 2226 u8 rx_frames_high[0x20]; 2227 2228 u8 rx_frames_low[0x20]; 2229 2230 u8 tx_octets_high[0x20]; 2231 2232 u8 tx_octets_low[0x20]; 2233 2234 u8 reserved_at_180[0xc0]; 2235 2236 u8 tx_frames_high[0x20]; 2237 2238 u8 tx_frames_low[0x20]; 2239 2240 u8 rx_pause_high[0x20]; 2241 2242 u8 rx_pause_low[0x20]; 2243 2244 u8 rx_pause_duration_high[0x20]; 2245 2246 u8 rx_pause_duration_low[0x20]; 2247 2248 u8 tx_pause_high[0x20]; 2249 2250 u8 tx_pause_low[0x20]; 2251 2252 u8 tx_pause_duration_high[0x20]; 2253 2254 u8 tx_pause_duration_low[0x20]; 2255 2256 u8 rx_pause_transition_high[0x20]; 2257 2258 u8 rx_pause_transition_low[0x20]; 2259 2260 u8 rx_discards_high[0x20]; 2261 2262 u8 rx_discards_low[0x20]; 2263 2264 u8 device_stall_minor_watermark_cnt_high[0x20]; 2265 2266 u8 device_stall_minor_watermark_cnt_low[0x20]; 2267 2268 u8 device_stall_critical_watermark_cnt_high[0x20]; 2269 2270 u8 device_stall_critical_watermark_cnt_low[0x20]; 2271 2272 u8 reserved_at_480[0x340]; 2273 }; 2274 2275 struct mlx5_ifc_eth_extended_cntrs_grp_data_layout_bits { 2276 u8 port_transmit_wait_high[0x20]; 2277 2278 u8 port_transmit_wait_low[0x20]; 2279 2280 u8 reserved_at_40[0x100]; 2281 2282 u8 rx_buffer_almost_full_high[0x20]; 2283 2284 u8 rx_buffer_almost_full_low[0x20]; 2285 2286 u8 rx_buffer_full_high[0x20]; 2287 2288 u8 rx_buffer_full_low[0x20]; 2289 2290 u8 rx_icrc_encapsulated_high[0x20]; 2291 2292 u8 rx_icrc_encapsulated_low[0x20]; 2293 2294 u8 reserved_at_200[0x5c0]; 2295 }; 2296 2297 struct mlx5_ifc_eth_3635_cntrs_grp_data_layout_bits { 2298 u8 dot3stats_alignment_errors_high[0x20]; 2299 2300 u8 dot3stats_alignment_errors_low[0x20]; 2301 2302 u8 dot3stats_fcs_errors_high[0x20]; 2303 2304 u8 dot3stats_fcs_errors_low[0x20]; 2305 2306 u8 dot3stats_single_collision_frames_high[0x20]; 2307 2308 u8 dot3stats_single_collision_frames_low[0x20]; 2309 2310 u8 dot3stats_multiple_collision_frames_high[0x20]; 2311 2312 u8 dot3stats_multiple_collision_frames_low[0x20]; 2313 2314 u8 dot3stats_sqe_test_errors_high[0x20]; 2315 2316 u8 dot3stats_sqe_test_errors_low[0x20]; 2317 2318 u8 dot3stats_deferred_transmissions_high[0x20]; 2319 2320 u8 dot3stats_deferred_transmissions_low[0x20]; 2321 2322 u8 dot3stats_late_collisions_high[0x20]; 2323 2324 u8 dot3stats_late_collisions_low[0x20]; 2325 2326 u8 dot3stats_excessive_collisions_high[0x20]; 2327 2328 u8 dot3stats_excessive_collisions_low[0x20]; 2329 2330 u8 dot3stats_internal_mac_transmit_errors_high[0x20]; 2331 2332 u8 dot3stats_internal_mac_transmit_errors_low[0x20]; 2333 2334 u8 dot3stats_carrier_sense_errors_high[0x20]; 2335 2336 u8 dot3stats_carrier_sense_errors_low[0x20]; 2337 2338 u8 dot3stats_frame_too_longs_high[0x20]; 2339 2340 u8 dot3stats_frame_too_longs_low[0x20]; 2341 2342 u8 dot3stats_internal_mac_receive_errors_high[0x20]; 2343 2344 u8 dot3stats_internal_mac_receive_errors_low[0x20]; 2345 2346 u8 dot3stats_symbol_errors_high[0x20]; 2347 2348 u8 dot3stats_symbol_errors_low[0x20]; 2349 2350 u8 dot3control_in_unknown_opcodes_high[0x20]; 2351 2352 u8 dot3control_in_unknown_opcodes_low[0x20]; 2353 2354 u8 dot3in_pause_frames_high[0x20]; 2355 2356 u8 dot3in_pause_frames_low[0x20]; 2357 2358 u8 dot3out_pause_frames_high[0x20]; 2359 2360 u8 dot3out_pause_frames_low[0x20]; 2361 2362 u8 reserved_at_400[0x3c0]; 2363 }; 2364 2365 struct mlx5_ifc_eth_2819_cntrs_grp_data_layout_bits { 2366 u8 ether_stats_drop_events_high[0x20]; 2367 2368 u8 ether_stats_drop_events_low[0x20]; 2369 2370 u8 ether_stats_octets_high[0x20]; 2371 2372 u8 ether_stats_octets_low[0x20]; 2373 2374 u8 ether_stats_pkts_high[0x20]; 2375 2376 u8 ether_stats_pkts_low[0x20]; 2377 2378 u8 ether_stats_broadcast_pkts_high[0x20]; 2379 2380 u8 ether_stats_broadcast_pkts_low[0x20]; 2381 2382 u8 ether_stats_multicast_pkts_high[0x20]; 2383 2384 u8 ether_stats_multicast_pkts_low[0x20]; 2385 2386 u8 ether_stats_crc_align_errors_high[0x20]; 2387 2388 u8 ether_stats_crc_align_errors_low[0x20]; 2389 2390 u8 ether_stats_undersize_pkts_high[0x20]; 2391 2392 u8 ether_stats_undersize_pkts_low[0x20]; 2393 2394 u8 ether_stats_oversize_pkts_high[0x20]; 2395 2396 u8 ether_stats_oversize_pkts_low[0x20]; 2397 2398 u8 ether_stats_fragments_high[0x20]; 2399 2400 u8 ether_stats_fragments_low[0x20]; 2401 2402 u8 ether_stats_jabbers_high[0x20]; 2403 2404 u8 ether_stats_jabbers_low[0x20]; 2405 2406 u8 ether_stats_collisions_high[0x20]; 2407 2408 u8 ether_stats_collisions_low[0x20]; 2409 2410 u8 ether_stats_pkts64octets_high[0x20]; 2411 2412 u8 ether_stats_pkts64octets_low[0x20]; 2413 2414 u8 ether_stats_pkts65to127octets_high[0x20]; 2415 2416 u8 ether_stats_pkts65to127octets_low[0x20]; 2417 2418 u8 ether_stats_pkts128to255octets_high[0x20]; 2419 2420 u8 ether_stats_pkts128to255octets_low[0x20]; 2421 2422 u8 ether_stats_pkts256to511octets_high[0x20]; 2423 2424 u8 ether_stats_pkts256to511octets_low[0x20]; 2425 2426 u8 ether_stats_pkts512to1023octets_high[0x20]; 2427 2428 u8 ether_stats_pkts512to1023octets_low[0x20]; 2429 2430 u8 ether_stats_pkts1024to1518octets_high[0x20]; 2431 2432 u8 ether_stats_pkts1024to1518octets_low[0x20]; 2433 2434 u8 ether_stats_pkts1519to2047octets_high[0x20]; 2435 2436 u8 ether_stats_pkts1519to2047octets_low[0x20]; 2437 2438 u8 ether_stats_pkts2048to4095octets_high[0x20]; 2439 2440 u8 ether_stats_pkts2048to4095octets_low[0x20]; 2441 2442 u8 ether_stats_pkts4096to8191octets_high[0x20]; 2443 2444 u8 ether_stats_pkts4096to8191octets_low[0x20]; 2445 2446 u8 ether_stats_pkts8192to10239octets_high[0x20]; 2447 2448 u8 ether_stats_pkts8192to10239octets_low[0x20]; 2449 2450 u8 reserved_at_540[0x280]; 2451 }; 2452 2453 struct mlx5_ifc_eth_2863_cntrs_grp_data_layout_bits { 2454 u8 if_in_octets_high[0x20]; 2455 2456 u8 if_in_octets_low[0x20]; 2457 2458 u8 if_in_ucast_pkts_high[0x20]; 2459 2460 u8 if_in_ucast_pkts_low[0x20]; 2461 2462 u8 if_in_discards_high[0x20]; 2463 2464 u8 if_in_discards_low[0x20]; 2465 2466 u8 if_in_errors_high[0x20]; 2467 2468 u8 if_in_errors_low[0x20]; 2469 2470 u8 if_in_unknown_protos_high[0x20]; 2471 2472 u8 if_in_unknown_protos_low[0x20]; 2473 2474 u8 if_out_octets_high[0x20]; 2475 2476 u8 if_out_octets_low[0x20]; 2477 2478 u8 if_out_ucast_pkts_high[0x20]; 2479 2480 u8 if_out_ucast_pkts_low[0x20]; 2481 2482 u8 if_out_discards_high[0x20]; 2483 2484 u8 if_out_discards_low[0x20]; 2485 2486 u8 if_out_errors_high[0x20]; 2487 2488 u8 if_out_errors_low[0x20]; 2489 2490 u8 if_in_multicast_pkts_high[0x20]; 2491 2492 u8 if_in_multicast_pkts_low[0x20]; 2493 2494 u8 if_in_broadcast_pkts_high[0x20]; 2495 2496 u8 if_in_broadcast_pkts_low[0x20]; 2497 2498 u8 if_out_multicast_pkts_high[0x20]; 2499 2500 u8 if_out_multicast_pkts_low[0x20]; 2501 2502 u8 if_out_broadcast_pkts_high[0x20]; 2503 2504 u8 if_out_broadcast_pkts_low[0x20]; 2505 2506 u8 reserved_at_340[0x480]; 2507 }; 2508 2509 struct mlx5_ifc_eth_802_3_cntrs_grp_data_layout_bits { 2510 u8 a_frames_transmitted_ok_high[0x20]; 2511 2512 u8 a_frames_transmitted_ok_low[0x20]; 2513 2514 u8 a_frames_received_ok_high[0x20]; 2515 2516 u8 a_frames_received_ok_low[0x20]; 2517 2518 u8 a_frame_check_sequence_errors_high[0x20]; 2519 2520 u8 a_frame_check_sequence_errors_low[0x20]; 2521 2522 u8 a_alignment_errors_high[0x20]; 2523 2524 u8 a_alignment_errors_low[0x20]; 2525 2526 u8 a_octets_transmitted_ok_high[0x20]; 2527 2528 u8 a_octets_transmitted_ok_low[0x20]; 2529 2530 u8 a_octets_received_ok_high[0x20]; 2531 2532 u8 a_octets_received_ok_low[0x20]; 2533 2534 u8 a_multicast_frames_xmitted_ok_high[0x20]; 2535 2536 u8 a_multicast_frames_xmitted_ok_low[0x20]; 2537 2538 u8 a_broadcast_frames_xmitted_ok_high[0x20]; 2539 2540 u8 a_broadcast_frames_xmitted_ok_low[0x20]; 2541 2542 u8 a_multicast_frames_received_ok_high[0x20]; 2543 2544 u8 a_multicast_frames_received_ok_low[0x20]; 2545 2546 u8 a_broadcast_frames_received_ok_high[0x20]; 2547 2548 u8 a_broadcast_frames_received_ok_low[0x20]; 2549 2550 u8 a_in_range_length_errors_high[0x20]; 2551 2552 u8 a_in_range_length_errors_low[0x20]; 2553 2554 u8 a_out_of_range_length_field_high[0x20]; 2555 2556 u8 a_out_of_range_length_field_low[0x20]; 2557 2558 u8 a_frame_too_long_errors_high[0x20]; 2559 2560 u8 a_frame_too_long_errors_low[0x20]; 2561 2562 u8 a_symbol_error_during_carrier_high[0x20]; 2563 2564 u8 a_symbol_error_during_carrier_low[0x20]; 2565 2566 u8 a_mac_control_frames_transmitted_high[0x20]; 2567 2568 u8 a_mac_control_frames_transmitted_low[0x20]; 2569 2570 u8 a_mac_control_frames_received_high[0x20]; 2571 2572 u8 a_mac_control_frames_received_low[0x20]; 2573 2574 u8 a_unsupported_opcodes_received_high[0x20]; 2575 2576 u8 a_unsupported_opcodes_received_low[0x20]; 2577 2578 u8 a_pause_mac_ctrl_frames_received_high[0x20]; 2579 2580 u8 a_pause_mac_ctrl_frames_received_low[0x20]; 2581 2582 u8 a_pause_mac_ctrl_frames_transmitted_high[0x20]; 2583 2584 u8 a_pause_mac_ctrl_frames_transmitted_low[0x20]; 2585 2586 u8 reserved_at_4c0[0x300]; 2587 }; 2588 2589 struct mlx5_ifc_pcie_perf_cntrs_grp_data_layout_bits { 2590 u8 life_time_counter_high[0x20]; 2591 2592 u8 life_time_counter_low[0x20]; 2593 2594 u8 rx_errors[0x20]; 2595 2596 u8 tx_errors[0x20]; 2597 2598 u8 l0_to_recovery_eieos[0x20]; 2599 2600 u8 l0_to_recovery_ts[0x20]; 2601 2602 u8 l0_to_recovery_framing[0x20]; 2603 2604 u8 l0_to_recovery_retrain[0x20]; 2605 2606 u8 crc_error_dllp[0x20]; 2607 2608 u8 crc_error_tlp[0x20]; 2609 2610 u8 tx_overflow_buffer_pkt_high[0x20]; 2611 2612 u8 tx_overflow_buffer_pkt_low[0x20]; 2613 2614 u8 outbound_stalled_reads[0x20]; 2615 2616 u8 outbound_stalled_writes[0x20]; 2617 2618 u8 outbound_stalled_reads_events[0x20]; 2619 2620 u8 outbound_stalled_writes_events[0x20]; 2621 2622 u8 reserved_at_200[0x5c0]; 2623 }; 2624 2625 struct mlx5_ifc_cmd_inter_comp_event_bits { 2626 u8 command_completion_vector[0x20]; 2627 2628 u8 reserved_at_20[0xc0]; 2629 }; 2630 2631 struct mlx5_ifc_stall_vl_event_bits { 2632 u8 reserved_at_0[0x18]; 2633 u8 port_num[0x1]; 2634 u8 reserved_at_19[0x3]; 2635 u8 vl[0x4]; 2636 2637 u8 reserved_at_20[0xa0]; 2638 }; 2639 2640 struct mlx5_ifc_db_bf_congestion_event_bits { 2641 u8 event_subtype[0x8]; 2642 u8 reserved_at_8[0x8]; 2643 u8 congestion_level[0x8]; 2644 u8 reserved_at_18[0x8]; 2645 2646 u8 reserved_at_20[0xa0]; 2647 }; 2648 2649 struct mlx5_ifc_gpio_event_bits { 2650 u8 reserved_at_0[0x60]; 2651 2652 u8 gpio_event_hi[0x20]; 2653 2654 u8 gpio_event_lo[0x20]; 2655 2656 u8 reserved_at_a0[0x40]; 2657 }; 2658 2659 struct mlx5_ifc_port_state_change_event_bits { 2660 u8 reserved_at_0[0x40]; 2661 2662 u8 port_num[0x4]; 2663 u8 reserved_at_44[0x1c]; 2664 2665 u8 reserved_at_60[0x80]; 2666 }; 2667 2668 struct mlx5_ifc_dropped_packet_logged_bits { 2669 u8 reserved_at_0[0xe0]; 2670 }; 2671 2672 enum { 2673 MLX5_CQ_ERROR_SYNDROME_CQ_OVERRUN = 0x1, 2674 MLX5_CQ_ERROR_SYNDROME_CQ_ACCESS_VIOLATION_ERROR = 0x2, 2675 }; 2676 2677 struct mlx5_ifc_cq_error_bits { 2678 u8 reserved_at_0[0x8]; 2679 u8 cqn[0x18]; 2680 2681 u8 reserved_at_20[0x20]; 2682 2683 u8 reserved_at_40[0x18]; 2684 u8 syndrome[0x8]; 2685 2686 u8 reserved_at_60[0x80]; 2687 }; 2688 2689 struct mlx5_ifc_rdma_page_fault_event_bits { 2690 u8 bytes_committed[0x20]; 2691 2692 u8 r_key[0x20]; 2693 2694 u8 reserved_at_40[0x10]; 2695 u8 packet_len[0x10]; 2696 2697 u8 rdma_op_len[0x20]; 2698 2699 u8 rdma_va[0x40]; 2700 2701 u8 reserved_at_c0[0x5]; 2702 u8 rdma[0x1]; 2703 u8 write[0x1]; 2704 u8 requestor[0x1]; 2705 u8 qp_number[0x18]; 2706 }; 2707 2708 struct mlx5_ifc_wqe_associated_page_fault_event_bits { 2709 u8 bytes_committed[0x20]; 2710 2711 u8 reserved_at_20[0x10]; 2712 u8 wqe_index[0x10]; 2713 2714 u8 reserved_at_40[0x10]; 2715 u8 len[0x10]; 2716 2717 u8 reserved_at_60[0x60]; 2718 2719 u8 reserved_at_c0[0x5]; 2720 u8 rdma[0x1]; 2721 u8 write_read[0x1]; 2722 u8 requestor[0x1]; 2723 u8 qpn[0x18]; 2724 }; 2725 2726 struct mlx5_ifc_qp_events_bits { 2727 u8 reserved_at_0[0xa0]; 2728 2729 u8 type[0x8]; 2730 u8 reserved_at_a8[0x18]; 2731 2732 u8 reserved_at_c0[0x8]; 2733 u8 qpn_rqn_sqn[0x18]; 2734 }; 2735 2736 struct mlx5_ifc_dct_events_bits { 2737 u8 reserved_at_0[0xc0]; 2738 2739 u8 reserved_at_c0[0x8]; 2740 u8 dct_number[0x18]; 2741 }; 2742 2743 struct mlx5_ifc_comp_event_bits { 2744 u8 reserved_at_0[0xc0]; 2745 2746 u8 reserved_at_c0[0x8]; 2747 u8 cq_number[0x18]; 2748 }; 2749 2750 enum { 2751 MLX5_QPC_STATE_RST = 0x0, 2752 MLX5_QPC_STATE_INIT = 0x1, 2753 MLX5_QPC_STATE_RTR = 0x2, 2754 MLX5_QPC_STATE_RTS = 0x3, 2755 MLX5_QPC_STATE_SQER = 0x4, 2756 MLX5_QPC_STATE_ERR = 0x6, 2757 MLX5_QPC_STATE_SQD = 0x7, 2758 MLX5_QPC_STATE_SUSPENDED = 0x9, 2759 }; 2760 2761 enum { 2762 MLX5_QPC_ST_RC = 0x0, 2763 MLX5_QPC_ST_UC = 0x1, 2764 MLX5_QPC_ST_UD = 0x2, 2765 MLX5_QPC_ST_XRC = 0x3, 2766 MLX5_QPC_ST_DCI = 0x5, 2767 MLX5_QPC_ST_QP0 = 0x7, 2768 MLX5_QPC_ST_QP1 = 0x8, 2769 MLX5_QPC_ST_RAW_DATAGRAM = 0x9, 2770 MLX5_QPC_ST_REG_UMR = 0xc, 2771 }; 2772 2773 enum { 2774 MLX5_QPC_PM_STATE_ARMED = 0x0, 2775 MLX5_QPC_PM_STATE_REARM = 0x1, 2776 MLX5_QPC_PM_STATE_RESERVED = 0x2, 2777 MLX5_QPC_PM_STATE_MIGRATED = 0x3, 2778 }; 2779 2780 enum { 2781 MLX5_QPC_OFFLOAD_TYPE_RNDV = 0x1, 2782 }; 2783 2784 enum { 2785 MLX5_QPC_END_PADDING_MODE_SCATTER_AS_IS = 0x0, 2786 MLX5_QPC_END_PADDING_MODE_PAD_TO_CACHE_LINE_ALIGNMENT = 0x1, 2787 }; 2788 2789 enum { 2790 MLX5_QPC_MTU_256_BYTES = 0x1, 2791 MLX5_QPC_MTU_512_BYTES = 0x2, 2792 MLX5_QPC_MTU_1K_BYTES = 0x3, 2793 MLX5_QPC_MTU_2K_BYTES = 0x4, 2794 MLX5_QPC_MTU_4K_BYTES = 0x5, 2795 MLX5_QPC_MTU_RAW_ETHERNET_QP = 0x7, 2796 }; 2797 2798 enum { 2799 MLX5_QPC_ATOMIC_MODE_IB_SPEC = 0x1, 2800 MLX5_QPC_ATOMIC_MODE_ONLY_8B = 0x2, 2801 MLX5_QPC_ATOMIC_MODE_UP_TO_8B = 0x3, 2802 MLX5_QPC_ATOMIC_MODE_UP_TO_16B = 0x4, 2803 MLX5_QPC_ATOMIC_MODE_UP_TO_32B = 0x5, 2804 MLX5_QPC_ATOMIC_MODE_UP_TO_64B = 0x6, 2805 MLX5_QPC_ATOMIC_MODE_UP_TO_128B = 0x7, 2806 MLX5_QPC_ATOMIC_MODE_UP_TO_256B = 0x8, 2807 }; 2808 2809 enum { 2810 MLX5_QPC_CS_REQ_DISABLE = 0x0, 2811 MLX5_QPC_CS_REQ_UP_TO_32B = 0x11, 2812 MLX5_QPC_CS_REQ_UP_TO_64B = 0x22, 2813 }; 2814 2815 enum { 2816 MLX5_QPC_CS_RES_DISABLE = 0x0, 2817 MLX5_QPC_CS_RES_UP_TO_32B = 0x1, 2818 MLX5_QPC_CS_RES_UP_TO_64B = 0x2, 2819 }; 2820 2821 struct mlx5_ifc_qpc_bits { 2822 u8 state[0x4]; 2823 u8 lag_tx_port_affinity[0x4]; 2824 u8 st[0x8]; 2825 u8 reserved_at_10[0x3]; 2826 u8 pm_state[0x2]; 2827 u8 reserved_at_15[0x1]; 2828 u8 req_e2e_credit_mode[0x2]; 2829 u8 offload_type[0x4]; 2830 u8 end_padding_mode[0x2]; 2831 u8 reserved_at_1e[0x2]; 2832 2833 u8 wq_signature[0x1]; 2834 u8 block_lb_mc[0x1]; 2835 u8 atomic_like_write_en[0x1]; 2836 u8 latency_sensitive[0x1]; 2837 u8 reserved_at_24[0x1]; 2838 u8 drain_sigerr[0x1]; 2839 u8 reserved_at_26[0x2]; 2840 u8 pd[0x18]; 2841 2842 u8 mtu[0x3]; 2843 u8 log_msg_max[0x5]; 2844 u8 reserved_at_48[0x1]; 2845 u8 log_rq_size[0x4]; 2846 u8 log_rq_stride[0x3]; 2847 u8 no_sq[0x1]; 2848 u8 log_sq_size[0x4]; 2849 u8 reserved_at_55[0x6]; 2850 u8 rlky[0x1]; 2851 u8 ulp_stateless_offload_mode[0x4]; 2852 2853 u8 counter_set_id[0x8]; 2854 u8 uar_page[0x18]; 2855 2856 u8 reserved_at_80[0x8]; 2857 u8 user_index[0x18]; 2858 2859 u8 reserved_at_a0[0x3]; 2860 u8 log_page_size[0x5]; 2861 u8 remote_qpn[0x18]; 2862 2863 struct mlx5_ifc_ads_bits primary_address_path; 2864 2865 struct mlx5_ifc_ads_bits secondary_address_path; 2866 2867 u8 log_ack_req_freq[0x4]; 2868 u8 reserved_at_384[0x4]; 2869 u8 log_sra_max[0x3]; 2870 u8 reserved_at_38b[0x2]; 2871 u8 retry_count[0x3]; 2872 u8 rnr_retry[0x3]; 2873 u8 reserved_at_393[0x1]; 2874 u8 fre[0x1]; 2875 u8 cur_rnr_retry[0x3]; 2876 u8 cur_retry_count[0x3]; 2877 u8 reserved_at_39b[0x5]; 2878 2879 u8 reserved_at_3a0[0x20]; 2880 2881 u8 reserved_at_3c0[0x8]; 2882 u8 next_send_psn[0x18]; 2883 2884 u8 reserved_at_3e0[0x8]; 2885 u8 cqn_snd[0x18]; 2886 2887 u8 reserved_at_400[0x8]; 2888 u8 deth_sqpn[0x18]; 2889 2890 u8 reserved_at_420[0x20]; 2891 2892 u8 reserved_at_440[0x8]; 2893 u8 last_acked_psn[0x18]; 2894 2895 u8 reserved_at_460[0x8]; 2896 u8 ssn[0x18]; 2897 2898 u8 reserved_at_480[0x8]; 2899 u8 log_rra_max[0x3]; 2900 u8 reserved_at_48b[0x1]; 2901 u8 atomic_mode[0x4]; 2902 u8 rre[0x1]; 2903 u8 rwe[0x1]; 2904 u8 rae[0x1]; 2905 u8 reserved_at_493[0x1]; 2906 u8 page_offset[0x6]; 2907 u8 reserved_at_49a[0x3]; 2908 u8 cd_slave_receive[0x1]; 2909 u8 cd_slave_send[0x1]; 2910 u8 cd_master[0x1]; 2911 2912 u8 reserved_at_4a0[0x3]; 2913 u8 min_rnr_nak[0x5]; 2914 u8 next_rcv_psn[0x18]; 2915 2916 u8 reserved_at_4c0[0x8]; 2917 u8 xrcd[0x18]; 2918 2919 u8 reserved_at_4e0[0x8]; 2920 u8 cqn_rcv[0x18]; 2921 2922 u8 dbr_addr[0x40]; 2923 2924 u8 q_key[0x20]; 2925 2926 u8 reserved_at_560[0x5]; 2927 u8 rq_type[0x3]; 2928 u8 srqn_rmpn_xrqn[0x18]; 2929 2930 u8 reserved_at_580[0x8]; 2931 u8 rmsn[0x18]; 2932 2933 u8 hw_sq_wqebb_counter[0x10]; 2934 u8 sw_sq_wqebb_counter[0x10]; 2935 2936 u8 hw_rq_counter[0x20]; 2937 2938 u8 sw_rq_counter[0x20]; 2939 2940 u8 reserved_at_600[0x20]; 2941 2942 u8 reserved_at_620[0xf]; 2943 u8 cgs[0x1]; 2944 u8 cs_req[0x8]; 2945 u8 cs_res[0x8]; 2946 2947 u8 dc_access_key[0x40]; 2948 2949 u8 reserved_at_680[0x3]; 2950 u8 dbr_umem_valid[0x1]; 2951 2952 u8 reserved_at_684[0xbc]; 2953 }; 2954 2955 struct mlx5_ifc_roce_addr_layout_bits { 2956 u8 source_l3_address[16][0x8]; 2957 2958 u8 reserved_at_80[0x3]; 2959 u8 vlan_valid[0x1]; 2960 u8 vlan_id[0xc]; 2961 u8 source_mac_47_32[0x10]; 2962 2963 u8 source_mac_31_0[0x20]; 2964 2965 u8 reserved_at_c0[0x14]; 2966 u8 roce_l3_type[0x4]; 2967 u8 roce_version[0x8]; 2968 2969 u8 reserved_at_e0[0x20]; 2970 }; 2971 2972 union mlx5_ifc_hca_cap_union_bits { 2973 struct mlx5_ifc_cmd_hca_cap_bits cmd_hca_cap; 2974 struct mlx5_ifc_odp_cap_bits odp_cap; 2975 struct mlx5_ifc_atomic_caps_bits atomic_caps; 2976 struct mlx5_ifc_roce_cap_bits roce_cap; 2977 struct mlx5_ifc_per_protocol_networking_offload_caps_bits per_protocol_networking_offload_caps; 2978 struct mlx5_ifc_flow_table_nic_cap_bits flow_table_nic_cap; 2979 struct mlx5_ifc_flow_table_eswitch_cap_bits flow_table_eswitch_cap; 2980 struct mlx5_ifc_e_switch_cap_bits e_switch_cap; 2981 struct mlx5_ifc_vector_calc_cap_bits vector_calc_cap; 2982 struct mlx5_ifc_qos_cap_bits qos_cap; 2983 struct mlx5_ifc_debug_cap_bits debug_cap; 2984 struct mlx5_ifc_fpga_cap_bits fpga_cap; 2985 struct mlx5_ifc_tls_cap_bits tls_cap; 2986 struct mlx5_ifc_device_mem_cap_bits device_mem_cap; 2987 struct mlx5_ifc_virtio_emulation_cap_bits virtio_emulation_cap; 2988 u8 reserved_at_0[0x8000]; 2989 }; 2990 2991 enum { 2992 MLX5_FLOW_CONTEXT_ACTION_ALLOW = 0x1, 2993 MLX5_FLOW_CONTEXT_ACTION_DROP = 0x2, 2994 MLX5_FLOW_CONTEXT_ACTION_FWD_DEST = 0x4, 2995 MLX5_FLOW_CONTEXT_ACTION_COUNT = 0x8, 2996 MLX5_FLOW_CONTEXT_ACTION_PACKET_REFORMAT = 0x10, 2997 MLX5_FLOW_CONTEXT_ACTION_DECAP = 0x20, 2998 MLX5_FLOW_CONTEXT_ACTION_MOD_HDR = 0x40, 2999 MLX5_FLOW_CONTEXT_ACTION_VLAN_POP = 0x80, 3000 MLX5_FLOW_CONTEXT_ACTION_VLAN_PUSH = 0x100, 3001 MLX5_FLOW_CONTEXT_ACTION_VLAN_POP_2 = 0x400, 3002 MLX5_FLOW_CONTEXT_ACTION_VLAN_PUSH_2 = 0x800, 3003 MLX5_FLOW_CONTEXT_ACTION_IPSEC_DECRYPT = 0x1000, 3004 MLX5_FLOW_CONTEXT_ACTION_IPSEC_ENCRYPT = 0x2000, 3005 }; 3006 3007 enum { 3008 MLX5_FLOW_CONTEXT_FLOW_SOURCE_ANY_VPORT = 0x0, 3009 MLX5_FLOW_CONTEXT_FLOW_SOURCE_UPLINK = 0x1, 3010 MLX5_FLOW_CONTEXT_FLOW_SOURCE_LOCAL_VPORT = 0x2, 3011 }; 3012 3013 struct mlx5_ifc_vlan_bits { 3014 u8 ethtype[0x10]; 3015 u8 prio[0x3]; 3016 u8 cfi[0x1]; 3017 u8 vid[0xc]; 3018 }; 3019 3020 struct mlx5_ifc_flow_context_bits { 3021 struct mlx5_ifc_vlan_bits push_vlan; 3022 3023 u8 group_id[0x20]; 3024 3025 u8 reserved_at_40[0x8]; 3026 u8 flow_tag[0x18]; 3027 3028 u8 reserved_at_60[0x10]; 3029 u8 action[0x10]; 3030 3031 u8 extended_destination[0x1]; 3032 u8 reserved_at_81[0x1]; 3033 u8 flow_source[0x2]; 3034 u8 reserved_at_84[0x4]; 3035 u8 destination_list_size[0x18]; 3036 3037 u8 reserved_at_a0[0x8]; 3038 u8 flow_counter_list_size[0x18]; 3039 3040 u8 packet_reformat_id[0x20]; 3041 3042 u8 modify_header_id[0x20]; 3043 3044 struct mlx5_ifc_vlan_bits push_vlan_2; 3045 3046 u8 ipsec_obj_id[0x20]; 3047 u8 reserved_at_140[0xc0]; 3048 3049 struct mlx5_ifc_fte_match_param_bits match_value; 3050 3051 u8 reserved_at_1200[0x600]; 3052 3053 union mlx5_ifc_dest_format_struct_flow_counter_list_auto_bits destination[]; 3054 }; 3055 3056 enum { 3057 MLX5_XRC_SRQC_STATE_GOOD = 0x0, 3058 MLX5_XRC_SRQC_STATE_ERROR = 0x1, 3059 }; 3060 3061 struct mlx5_ifc_xrc_srqc_bits { 3062 u8 state[0x4]; 3063 u8 log_xrc_srq_size[0x4]; 3064 u8 reserved_at_8[0x18]; 3065 3066 u8 wq_signature[0x1]; 3067 u8 cont_srq[0x1]; 3068 u8 reserved_at_22[0x1]; 3069 u8 rlky[0x1]; 3070 u8 basic_cyclic_rcv_wqe[0x1]; 3071 u8 log_rq_stride[0x3]; 3072 u8 xrcd[0x18]; 3073 3074 u8 page_offset[0x6]; 3075 u8 reserved_at_46[0x1]; 3076 u8 dbr_umem_valid[0x1]; 3077 u8 cqn[0x18]; 3078 3079 u8 reserved_at_60[0x20]; 3080 3081 u8 user_index_equal_xrc_srqn[0x1]; 3082 u8 reserved_at_81[0x1]; 3083 u8 log_page_size[0x6]; 3084 u8 user_index[0x18]; 3085 3086 u8 reserved_at_a0[0x20]; 3087 3088 u8 reserved_at_c0[0x8]; 3089 u8 pd[0x18]; 3090 3091 u8 lwm[0x10]; 3092 u8 wqe_cnt[0x10]; 3093 3094 u8 reserved_at_100[0x40]; 3095 3096 u8 db_record_addr_h[0x20]; 3097 3098 u8 db_record_addr_l[0x1e]; 3099 u8 reserved_at_17e[0x2]; 3100 3101 u8 reserved_at_180[0x80]; 3102 }; 3103 3104 struct mlx5_ifc_vnic_diagnostic_statistics_bits { 3105 u8 counter_error_queues[0x20]; 3106 3107 u8 total_error_queues[0x20]; 3108 3109 u8 send_queue_priority_update_flow[0x20]; 3110 3111 u8 reserved_at_60[0x20]; 3112 3113 u8 nic_receive_steering_discard[0x40]; 3114 3115 u8 receive_discard_vport_down[0x40]; 3116 3117 u8 transmit_discard_vport_down[0x40]; 3118 3119 u8 reserved_at_140[0xa0]; 3120 3121 u8 internal_rq_out_of_buffer[0x20]; 3122 3123 u8 reserved_at_200[0xe00]; 3124 }; 3125 3126 struct mlx5_ifc_traffic_counter_bits { 3127 u8 packets[0x40]; 3128 3129 u8 octets[0x40]; 3130 }; 3131 3132 struct mlx5_ifc_tisc_bits { 3133 u8 strict_lag_tx_port_affinity[0x1]; 3134 u8 tls_en[0x1]; 3135 u8 reserved_at_2[0x2]; 3136 u8 lag_tx_port_affinity[0x04]; 3137 3138 u8 reserved_at_8[0x4]; 3139 u8 prio[0x4]; 3140 u8 reserved_at_10[0x10]; 3141 3142 u8 reserved_at_20[0x100]; 3143 3144 u8 reserved_at_120[0x8]; 3145 u8 transport_domain[0x18]; 3146 3147 u8 reserved_at_140[0x8]; 3148 u8 underlay_qpn[0x18]; 3149 3150 u8 reserved_at_160[0x8]; 3151 u8 pd[0x18]; 3152 3153 u8 reserved_at_180[0x380]; 3154 }; 3155 3156 enum { 3157 MLX5_TIRC_DISP_TYPE_DIRECT = 0x0, 3158 MLX5_TIRC_DISP_TYPE_INDIRECT = 0x1, 3159 }; 3160 3161 enum { 3162 MLX5_TIRC_LRO_ENABLE_MASK_IPV4_LRO = 0x1, 3163 MLX5_TIRC_LRO_ENABLE_MASK_IPV6_LRO = 0x2, 3164 }; 3165 3166 enum { 3167 MLX5_RX_HASH_FN_NONE = 0x0, 3168 MLX5_RX_HASH_FN_INVERTED_XOR8 = 0x1, 3169 MLX5_RX_HASH_FN_TOEPLITZ = 0x2, 3170 }; 3171 3172 enum { 3173 MLX5_TIRC_SELF_LB_BLOCK_BLOCK_UNICAST = 0x1, 3174 MLX5_TIRC_SELF_LB_BLOCK_BLOCK_MULTICAST = 0x2, 3175 }; 3176 3177 struct mlx5_ifc_tirc_bits { 3178 u8 reserved_at_0[0x20]; 3179 3180 u8 disp_type[0x4]; 3181 u8 tls_en[0x1]; 3182 u8 reserved_at_25[0x1b]; 3183 3184 u8 reserved_at_40[0x40]; 3185 3186 u8 reserved_at_80[0x4]; 3187 u8 lro_timeout_period_usecs[0x10]; 3188 u8 lro_enable_mask[0x4]; 3189 u8 lro_max_ip_payload_size[0x8]; 3190 3191 u8 reserved_at_a0[0x40]; 3192 3193 u8 reserved_at_e0[0x8]; 3194 u8 inline_rqn[0x18]; 3195 3196 u8 rx_hash_symmetric[0x1]; 3197 u8 reserved_at_101[0x1]; 3198 u8 tunneled_offload_en[0x1]; 3199 u8 reserved_at_103[0x5]; 3200 u8 indirect_table[0x18]; 3201 3202 u8 rx_hash_fn[0x4]; 3203 u8 reserved_at_124[0x2]; 3204 u8 self_lb_block[0x2]; 3205 u8 transport_domain[0x18]; 3206 3207 u8 rx_hash_toeplitz_key[10][0x20]; 3208 3209 struct mlx5_ifc_rx_hash_field_select_bits rx_hash_field_selector_outer; 3210 3211 struct mlx5_ifc_rx_hash_field_select_bits rx_hash_field_selector_inner; 3212 3213 u8 reserved_at_2c0[0x4c0]; 3214 }; 3215 3216 enum { 3217 MLX5_SRQC_STATE_GOOD = 0x0, 3218 MLX5_SRQC_STATE_ERROR = 0x1, 3219 }; 3220 3221 struct mlx5_ifc_srqc_bits { 3222 u8 state[0x4]; 3223 u8 log_srq_size[0x4]; 3224 u8 reserved_at_8[0x18]; 3225 3226 u8 wq_signature[0x1]; 3227 u8 cont_srq[0x1]; 3228 u8 reserved_at_22[0x1]; 3229 u8 rlky[0x1]; 3230 u8 reserved_at_24[0x1]; 3231 u8 log_rq_stride[0x3]; 3232 u8 xrcd[0x18]; 3233 3234 u8 page_offset[0x6]; 3235 u8 reserved_at_46[0x2]; 3236 u8 cqn[0x18]; 3237 3238 u8 reserved_at_60[0x20]; 3239 3240 u8 reserved_at_80[0x2]; 3241 u8 log_page_size[0x6]; 3242 u8 reserved_at_88[0x18]; 3243 3244 u8 reserved_at_a0[0x20]; 3245 3246 u8 reserved_at_c0[0x8]; 3247 u8 pd[0x18]; 3248 3249 u8 lwm[0x10]; 3250 u8 wqe_cnt[0x10]; 3251 3252 u8 reserved_at_100[0x40]; 3253 3254 u8 dbr_addr[0x40]; 3255 3256 u8 reserved_at_180[0x80]; 3257 }; 3258 3259 enum { 3260 MLX5_SQC_STATE_RST = 0x0, 3261 MLX5_SQC_STATE_RDY = 0x1, 3262 MLX5_SQC_STATE_ERR = 0x3, 3263 }; 3264 3265 struct mlx5_ifc_sqc_bits { 3266 u8 rlky[0x1]; 3267 u8 cd_master[0x1]; 3268 u8 fre[0x1]; 3269 u8 flush_in_error_en[0x1]; 3270 u8 allow_multi_pkt_send_wqe[0x1]; 3271 u8 min_wqe_inline_mode[0x3]; 3272 u8 state[0x4]; 3273 u8 reg_umr[0x1]; 3274 u8 allow_swp[0x1]; 3275 u8 hairpin[0x1]; 3276 u8 reserved_at_f[0x11]; 3277 3278 u8 reserved_at_20[0x8]; 3279 u8 user_index[0x18]; 3280 3281 u8 reserved_at_40[0x8]; 3282 u8 cqn[0x18]; 3283 3284 u8 reserved_at_60[0x8]; 3285 u8 hairpin_peer_rq[0x18]; 3286 3287 u8 reserved_at_80[0x10]; 3288 u8 hairpin_peer_vhca[0x10]; 3289 3290 u8 reserved_at_a0[0x50]; 3291 3292 u8 packet_pacing_rate_limit_index[0x10]; 3293 u8 tis_lst_sz[0x10]; 3294 u8 reserved_at_110[0x10]; 3295 3296 u8 reserved_at_120[0x40]; 3297 3298 u8 reserved_at_160[0x8]; 3299 u8 tis_num_0[0x18]; 3300 3301 struct mlx5_ifc_wq_bits wq; 3302 }; 3303 3304 enum { 3305 SCHEDULING_CONTEXT_ELEMENT_TYPE_TSAR = 0x0, 3306 SCHEDULING_CONTEXT_ELEMENT_TYPE_VPORT = 0x1, 3307 SCHEDULING_CONTEXT_ELEMENT_TYPE_VPORT_TC = 0x2, 3308 SCHEDULING_CONTEXT_ELEMENT_TYPE_PARA_VPORT_TC = 0x3, 3309 }; 3310 3311 enum { 3312 ELEMENT_TYPE_CAP_MASK_TASR = 1 << 0, 3313 ELEMENT_TYPE_CAP_MASK_VPORT = 1 << 1, 3314 ELEMENT_TYPE_CAP_MASK_VPORT_TC = 1 << 2, 3315 ELEMENT_TYPE_CAP_MASK_PARA_VPORT_TC = 1 << 3, 3316 }; 3317 3318 struct mlx5_ifc_scheduling_context_bits { 3319 u8 element_type[0x8]; 3320 u8 reserved_at_8[0x18]; 3321 3322 u8 element_attributes[0x20]; 3323 3324 u8 parent_element_id[0x20]; 3325 3326 u8 reserved_at_60[0x40]; 3327 3328 u8 bw_share[0x20]; 3329 3330 u8 max_average_bw[0x20]; 3331 3332 u8 reserved_at_e0[0x120]; 3333 }; 3334 3335 struct mlx5_ifc_rqtc_bits { 3336 u8 reserved_at_0[0xa0]; 3337 3338 u8 reserved_at_a0[0x5]; 3339 u8 list_q_type[0x3]; 3340 u8 reserved_at_a8[0x8]; 3341 u8 rqt_max_size[0x10]; 3342 3343 u8 rq_vhca_id_format[0x1]; 3344 u8 reserved_at_c1[0xf]; 3345 u8 rqt_actual_size[0x10]; 3346 3347 u8 reserved_at_e0[0x6a0]; 3348 3349 struct mlx5_ifc_rq_num_bits rq_num[]; 3350 }; 3351 3352 enum { 3353 MLX5_RQC_MEM_RQ_TYPE_MEMORY_RQ_INLINE = 0x0, 3354 MLX5_RQC_MEM_RQ_TYPE_MEMORY_RQ_RMP = 0x1, 3355 }; 3356 3357 enum { 3358 MLX5_RQC_STATE_RST = 0x0, 3359 MLX5_RQC_STATE_RDY = 0x1, 3360 MLX5_RQC_STATE_ERR = 0x3, 3361 }; 3362 3363 struct mlx5_ifc_rqc_bits { 3364 u8 rlky[0x1]; 3365 u8 delay_drop_en[0x1]; 3366 u8 scatter_fcs[0x1]; 3367 u8 vsd[0x1]; 3368 u8 mem_rq_type[0x4]; 3369 u8 state[0x4]; 3370 u8 reserved_at_c[0x1]; 3371 u8 flush_in_error_en[0x1]; 3372 u8 hairpin[0x1]; 3373 u8 reserved_at_f[0x11]; 3374 3375 u8 reserved_at_20[0x8]; 3376 u8 user_index[0x18]; 3377 3378 u8 reserved_at_40[0x8]; 3379 u8 cqn[0x18]; 3380 3381 u8 counter_set_id[0x8]; 3382 u8 reserved_at_68[0x18]; 3383 3384 u8 reserved_at_80[0x8]; 3385 u8 rmpn[0x18]; 3386 3387 u8 reserved_at_a0[0x8]; 3388 u8 hairpin_peer_sq[0x18]; 3389 3390 u8 reserved_at_c0[0x10]; 3391 u8 hairpin_peer_vhca[0x10]; 3392 3393 u8 reserved_at_e0[0xa0]; 3394 3395 struct mlx5_ifc_wq_bits wq; 3396 }; 3397 3398 enum { 3399 MLX5_RMPC_STATE_RDY = 0x1, 3400 MLX5_RMPC_STATE_ERR = 0x3, 3401 }; 3402 3403 struct mlx5_ifc_rmpc_bits { 3404 u8 reserved_at_0[0x8]; 3405 u8 state[0x4]; 3406 u8 reserved_at_c[0x14]; 3407 3408 u8 basic_cyclic_rcv_wqe[0x1]; 3409 u8 reserved_at_21[0x1f]; 3410 3411 u8 reserved_at_40[0x140]; 3412 3413 struct mlx5_ifc_wq_bits wq; 3414 }; 3415 3416 struct mlx5_ifc_nic_vport_context_bits { 3417 u8 reserved_at_0[0x5]; 3418 u8 min_wqe_inline_mode[0x3]; 3419 u8 reserved_at_8[0x15]; 3420 u8 disable_mc_local_lb[0x1]; 3421 u8 disable_uc_local_lb[0x1]; 3422 u8 roce_en[0x1]; 3423 3424 u8 arm_change_event[0x1]; 3425 u8 reserved_at_21[0x1a]; 3426 u8 event_on_mtu[0x1]; 3427 u8 event_on_promisc_change[0x1]; 3428 u8 event_on_vlan_change[0x1]; 3429 u8 event_on_mc_address_change[0x1]; 3430 u8 event_on_uc_address_change[0x1]; 3431 3432 u8 reserved_at_40[0xc]; 3433 3434 u8 affiliation_criteria[0x4]; 3435 u8 affiliated_vhca_id[0x10]; 3436 3437 u8 reserved_at_60[0xd0]; 3438 3439 u8 mtu[0x10]; 3440 3441 u8 system_image_guid[0x40]; 3442 u8 port_guid[0x40]; 3443 u8 node_guid[0x40]; 3444 3445 u8 reserved_at_200[0x140]; 3446 u8 qkey_violation_counter[0x10]; 3447 u8 reserved_at_350[0x430]; 3448 3449 u8 promisc_uc[0x1]; 3450 u8 promisc_mc[0x1]; 3451 u8 promisc_all[0x1]; 3452 u8 reserved_at_783[0x2]; 3453 u8 allowed_list_type[0x3]; 3454 u8 reserved_at_788[0xc]; 3455 u8 allowed_list_size[0xc]; 3456 3457 struct mlx5_ifc_mac_address_layout_bits permanent_address; 3458 3459 u8 reserved_at_7e0[0x20]; 3460 3461 u8 current_uc_mac_address[][0x40]; 3462 }; 3463 3464 enum { 3465 MLX5_MKC_ACCESS_MODE_PA = 0x0, 3466 MLX5_MKC_ACCESS_MODE_MTT = 0x1, 3467 MLX5_MKC_ACCESS_MODE_KLMS = 0x2, 3468 MLX5_MKC_ACCESS_MODE_KSM = 0x3, 3469 MLX5_MKC_ACCESS_MODE_SW_ICM = 0x4, 3470 MLX5_MKC_ACCESS_MODE_MEMIC = 0x5, 3471 }; 3472 3473 struct mlx5_ifc_mkc_bits { 3474 u8 reserved_at_0[0x1]; 3475 u8 free[0x1]; 3476 u8 reserved_at_2[0x1]; 3477 u8 access_mode_4_2[0x3]; 3478 u8 reserved_at_6[0x7]; 3479 u8 relaxed_ordering_write[0x1]; 3480 u8 reserved_at_e[0x1]; 3481 u8 small_fence_on_rdma_read_response[0x1]; 3482 u8 umr_en[0x1]; 3483 u8 a[0x1]; 3484 u8 rw[0x1]; 3485 u8 rr[0x1]; 3486 u8 lw[0x1]; 3487 u8 lr[0x1]; 3488 u8 access_mode_1_0[0x2]; 3489 u8 reserved_at_18[0x8]; 3490 3491 u8 qpn[0x18]; 3492 u8 mkey_7_0[0x8]; 3493 3494 u8 reserved_at_40[0x20]; 3495 3496 u8 length64[0x1]; 3497 u8 bsf_en[0x1]; 3498 u8 sync_umr[0x1]; 3499 u8 reserved_at_63[0x2]; 3500 u8 expected_sigerr_count[0x1]; 3501 u8 reserved_at_66[0x1]; 3502 u8 en_rinval[0x1]; 3503 u8 pd[0x18]; 3504 3505 u8 start_addr[0x40]; 3506 3507 u8 len[0x40]; 3508 3509 u8 bsf_octword_size[0x20]; 3510 3511 u8 reserved_at_120[0x80]; 3512 3513 u8 translations_octword_size[0x20]; 3514 3515 u8 reserved_at_1c0[0x19]; 3516 u8 relaxed_ordering_read[0x1]; 3517 u8 reserved_at_1d9[0x1]; 3518 u8 log_page_size[0x5]; 3519 3520 u8 reserved_at_1e0[0x20]; 3521 }; 3522 3523 struct mlx5_ifc_pkey_bits { 3524 u8 reserved_at_0[0x10]; 3525 u8 pkey[0x10]; 3526 }; 3527 3528 struct mlx5_ifc_array128_auto_bits { 3529 u8 array128_auto[16][0x8]; 3530 }; 3531 3532 struct mlx5_ifc_hca_vport_context_bits { 3533 u8 field_select[0x20]; 3534 3535 u8 reserved_at_20[0xe0]; 3536 3537 u8 sm_virt_aware[0x1]; 3538 u8 has_smi[0x1]; 3539 u8 has_raw[0x1]; 3540 u8 grh_required[0x1]; 3541 u8 reserved_at_104[0xc]; 3542 u8 port_physical_state[0x4]; 3543 u8 vport_state_policy[0x4]; 3544 u8 port_state[0x4]; 3545 u8 vport_state[0x4]; 3546 3547 u8 reserved_at_120[0x20]; 3548 3549 u8 system_image_guid[0x40]; 3550 3551 u8 port_guid[0x40]; 3552 3553 u8 node_guid[0x40]; 3554 3555 u8 cap_mask1[0x20]; 3556 3557 u8 cap_mask1_field_select[0x20]; 3558 3559 u8 cap_mask2[0x20]; 3560 3561 u8 cap_mask2_field_select[0x20]; 3562 3563 u8 reserved_at_280[0x80]; 3564 3565 u8 lid[0x10]; 3566 u8 reserved_at_310[0x4]; 3567 u8 init_type_reply[0x4]; 3568 u8 lmc[0x3]; 3569 u8 subnet_timeout[0x5]; 3570 3571 u8 sm_lid[0x10]; 3572 u8 sm_sl[0x4]; 3573 u8 reserved_at_334[0xc]; 3574 3575 u8 qkey_violation_counter[0x10]; 3576 u8 pkey_violation_counter[0x10]; 3577 3578 u8 reserved_at_360[0xca0]; 3579 }; 3580 3581 struct mlx5_ifc_esw_vport_context_bits { 3582 u8 fdb_to_vport_reg_c[0x1]; 3583 u8 reserved_at_1[0x2]; 3584 u8 vport_svlan_strip[0x1]; 3585 u8 vport_cvlan_strip[0x1]; 3586 u8 vport_svlan_insert[0x1]; 3587 u8 vport_cvlan_insert[0x2]; 3588 u8 fdb_to_vport_reg_c_id[0x8]; 3589 u8 reserved_at_10[0x10]; 3590 3591 u8 reserved_at_20[0x20]; 3592 3593 u8 svlan_cfi[0x1]; 3594 u8 svlan_pcp[0x3]; 3595 u8 svlan_id[0xc]; 3596 u8 cvlan_cfi[0x1]; 3597 u8 cvlan_pcp[0x3]; 3598 u8 cvlan_id[0xc]; 3599 3600 u8 reserved_at_60[0x720]; 3601 3602 u8 sw_steering_vport_icm_address_rx[0x40]; 3603 3604 u8 sw_steering_vport_icm_address_tx[0x40]; 3605 }; 3606 3607 enum { 3608 MLX5_EQC_STATUS_OK = 0x0, 3609 MLX5_EQC_STATUS_EQ_WRITE_FAILURE = 0xa, 3610 }; 3611 3612 enum { 3613 MLX5_EQC_ST_ARMED = 0x9, 3614 MLX5_EQC_ST_FIRED = 0xa, 3615 }; 3616 3617 struct mlx5_ifc_eqc_bits { 3618 u8 status[0x4]; 3619 u8 reserved_at_4[0x9]; 3620 u8 ec[0x1]; 3621 u8 oi[0x1]; 3622 u8 reserved_at_f[0x5]; 3623 u8 st[0x4]; 3624 u8 reserved_at_18[0x8]; 3625 3626 u8 reserved_at_20[0x20]; 3627 3628 u8 reserved_at_40[0x14]; 3629 u8 page_offset[0x6]; 3630 u8 reserved_at_5a[0x6]; 3631 3632 u8 reserved_at_60[0x3]; 3633 u8 log_eq_size[0x5]; 3634 u8 uar_page[0x18]; 3635 3636 u8 reserved_at_80[0x20]; 3637 3638 u8 reserved_at_a0[0x18]; 3639 u8 intr[0x8]; 3640 3641 u8 reserved_at_c0[0x3]; 3642 u8 log_page_size[0x5]; 3643 u8 reserved_at_c8[0x18]; 3644 3645 u8 reserved_at_e0[0x60]; 3646 3647 u8 reserved_at_140[0x8]; 3648 u8 consumer_counter[0x18]; 3649 3650 u8 reserved_at_160[0x8]; 3651 u8 producer_counter[0x18]; 3652 3653 u8 reserved_at_180[0x80]; 3654 }; 3655 3656 enum { 3657 MLX5_DCTC_STATE_ACTIVE = 0x0, 3658 MLX5_DCTC_STATE_DRAINING = 0x1, 3659 MLX5_DCTC_STATE_DRAINED = 0x2, 3660 }; 3661 3662 enum { 3663 MLX5_DCTC_CS_RES_DISABLE = 0x0, 3664 MLX5_DCTC_CS_RES_NA = 0x1, 3665 MLX5_DCTC_CS_RES_UP_TO_64B = 0x2, 3666 }; 3667 3668 enum { 3669 MLX5_DCTC_MTU_256_BYTES = 0x1, 3670 MLX5_DCTC_MTU_512_BYTES = 0x2, 3671 MLX5_DCTC_MTU_1K_BYTES = 0x3, 3672 MLX5_DCTC_MTU_2K_BYTES = 0x4, 3673 MLX5_DCTC_MTU_4K_BYTES = 0x5, 3674 }; 3675 3676 struct mlx5_ifc_dctc_bits { 3677 u8 reserved_at_0[0x4]; 3678 u8 state[0x4]; 3679 u8 reserved_at_8[0x18]; 3680 3681 u8 reserved_at_20[0x8]; 3682 u8 user_index[0x18]; 3683 3684 u8 reserved_at_40[0x8]; 3685 u8 cqn[0x18]; 3686 3687 u8 counter_set_id[0x8]; 3688 u8 atomic_mode[0x4]; 3689 u8 rre[0x1]; 3690 u8 rwe[0x1]; 3691 u8 rae[0x1]; 3692 u8 atomic_like_write_en[0x1]; 3693 u8 latency_sensitive[0x1]; 3694 u8 rlky[0x1]; 3695 u8 free_ar[0x1]; 3696 u8 reserved_at_73[0xd]; 3697 3698 u8 reserved_at_80[0x8]; 3699 u8 cs_res[0x8]; 3700 u8 reserved_at_90[0x3]; 3701 u8 min_rnr_nak[0x5]; 3702 u8 reserved_at_98[0x8]; 3703 3704 u8 reserved_at_a0[0x8]; 3705 u8 srqn_xrqn[0x18]; 3706 3707 u8 reserved_at_c0[0x8]; 3708 u8 pd[0x18]; 3709 3710 u8 tclass[0x8]; 3711 u8 reserved_at_e8[0x4]; 3712 u8 flow_label[0x14]; 3713 3714 u8 dc_access_key[0x40]; 3715 3716 u8 reserved_at_140[0x5]; 3717 u8 mtu[0x3]; 3718 u8 port[0x8]; 3719 u8 pkey_index[0x10]; 3720 3721 u8 reserved_at_160[0x8]; 3722 u8 my_addr_index[0x8]; 3723 u8 reserved_at_170[0x8]; 3724 u8 hop_limit[0x8]; 3725 3726 u8 dc_access_key_violation_count[0x20]; 3727 3728 u8 reserved_at_1a0[0x14]; 3729 u8 dei_cfi[0x1]; 3730 u8 eth_prio[0x3]; 3731 u8 ecn[0x2]; 3732 u8 dscp[0x6]; 3733 3734 u8 reserved_at_1c0[0x20]; 3735 u8 ece[0x20]; 3736 }; 3737 3738 enum { 3739 MLX5_CQC_STATUS_OK = 0x0, 3740 MLX5_CQC_STATUS_CQ_OVERFLOW = 0x9, 3741 MLX5_CQC_STATUS_CQ_WRITE_FAIL = 0xa, 3742 }; 3743 3744 enum { 3745 MLX5_CQC_CQE_SZ_64_BYTES = 0x0, 3746 MLX5_CQC_CQE_SZ_128_BYTES = 0x1, 3747 }; 3748 3749 enum { 3750 MLX5_CQC_ST_SOLICITED_NOTIFICATION_REQUEST_ARMED = 0x6, 3751 MLX5_CQC_ST_NOTIFICATION_REQUEST_ARMED = 0x9, 3752 MLX5_CQC_ST_FIRED = 0xa, 3753 }; 3754 3755 enum { 3756 MLX5_CQ_PERIOD_MODE_START_FROM_EQE = 0x0, 3757 MLX5_CQ_PERIOD_MODE_START_FROM_CQE = 0x1, 3758 MLX5_CQ_PERIOD_NUM_MODES 3759 }; 3760 3761 struct mlx5_ifc_cqc_bits { 3762 u8 status[0x4]; 3763 u8 reserved_at_4[0x2]; 3764 u8 dbr_umem_valid[0x1]; 3765 u8 reserved_at_7[0x1]; 3766 u8 cqe_sz[0x3]; 3767 u8 cc[0x1]; 3768 u8 reserved_at_c[0x1]; 3769 u8 scqe_break_moderation_en[0x1]; 3770 u8 oi[0x1]; 3771 u8 cq_period_mode[0x2]; 3772 u8 cqe_comp_en[0x1]; 3773 u8 mini_cqe_res_format[0x2]; 3774 u8 st[0x4]; 3775 u8 reserved_at_18[0x8]; 3776 3777 u8 reserved_at_20[0x20]; 3778 3779 u8 reserved_at_40[0x14]; 3780 u8 page_offset[0x6]; 3781 u8 reserved_at_5a[0x6]; 3782 3783 u8 reserved_at_60[0x3]; 3784 u8 log_cq_size[0x5]; 3785 u8 uar_page[0x18]; 3786 3787 u8 reserved_at_80[0x4]; 3788 u8 cq_period[0xc]; 3789 u8 cq_max_count[0x10]; 3790 3791 u8 reserved_at_a0[0x18]; 3792 u8 c_eqn[0x8]; 3793 3794 u8 reserved_at_c0[0x3]; 3795 u8 log_page_size[0x5]; 3796 u8 reserved_at_c8[0x18]; 3797 3798 u8 reserved_at_e0[0x20]; 3799 3800 u8 reserved_at_100[0x8]; 3801 u8 last_notified_index[0x18]; 3802 3803 u8 reserved_at_120[0x8]; 3804 u8 last_solicit_index[0x18]; 3805 3806 u8 reserved_at_140[0x8]; 3807 u8 consumer_counter[0x18]; 3808 3809 u8 reserved_at_160[0x8]; 3810 u8 producer_counter[0x18]; 3811 3812 u8 reserved_at_180[0x40]; 3813 3814 u8 dbr_addr[0x40]; 3815 }; 3816 3817 union mlx5_ifc_cong_control_roce_ecn_auto_bits { 3818 struct mlx5_ifc_cong_control_802_1qau_rp_bits cong_control_802_1qau_rp; 3819 struct mlx5_ifc_cong_control_r_roce_ecn_rp_bits cong_control_r_roce_ecn_rp; 3820 struct mlx5_ifc_cong_control_r_roce_ecn_np_bits cong_control_r_roce_ecn_np; 3821 u8 reserved_at_0[0x800]; 3822 }; 3823 3824 struct mlx5_ifc_query_adapter_param_block_bits { 3825 u8 reserved_at_0[0xc0]; 3826 3827 u8 reserved_at_c0[0x8]; 3828 u8 ieee_vendor_id[0x18]; 3829 3830 u8 reserved_at_e0[0x10]; 3831 u8 vsd_vendor_id[0x10]; 3832 3833 u8 vsd[208][0x8]; 3834 3835 u8 vsd_contd_psid[16][0x8]; 3836 }; 3837 3838 enum { 3839 MLX5_XRQC_STATE_GOOD = 0x0, 3840 MLX5_XRQC_STATE_ERROR = 0x1, 3841 }; 3842 3843 enum { 3844 MLX5_XRQC_TOPOLOGY_NO_SPECIAL_TOPOLOGY = 0x0, 3845 MLX5_XRQC_TOPOLOGY_TAG_MATCHING = 0x1, 3846 }; 3847 3848 enum { 3849 MLX5_XRQC_OFFLOAD_RNDV = 0x1, 3850 }; 3851 3852 struct mlx5_ifc_tag_matching_topology_context_bits { 3853 u8 log_matching_list_sz[0x4]; 3854 u8 reserved_at_4[0xc]; 3855 u8 append_next_index[0x10]; 3856 3857 u8 sw_phase_cnt[0x10]; 3858 u8 hw_phase_cnt[0x10]; 3859 3860 u8 reserved_at_40[0x40]; 3861 }; 3862 3863 struct mlx5_ifc_xrqc_bits { 3864 u8 state[0x4]; 3865 u8 rlkey[0x1]; 3866 u8 reserved_at_5[0xf]; 3867 u8 topology[0x4]; 3868 u8 reserved_at_18[0x4]; 3869 u8 offload[0x4]; 3870 3871 u8 reserved_at_20[0x8]; 3872 u8 user_index[0x18]; 3873 3874 u8 reserved_at_40[0x8]; 3875 u8 cqn[0x18]; 3876 3877 u8 reserved_at_60[0xa0]; 3878 3879 struct mlx5_ifc_tag_matching_topology_context_bits tag_matching_topology_context; 3880 3881 u8 reserved_at_180[0x280]; 3882 3883 struct mlx5_ifc_wq_bits wq; 3884 }; 3885 3886 union mlx5_ifc_modify_field_select_resize_field_select_auto_bits { 3887 struct mlx5_ifc_modify_field_select_bits modify_field_select; 3888 struct mlx5_ifc_resize_field_select_bits resize_field_select; 3889 u8 reserved_at_0[0x20]; 3890 }; 3891 3892 union mlx5_ifc_field_select_802_1_r_roce_auto_bits { 3893 struct mlx5_ifc_field_select_802_1qau_rp_bits field_select_802_1qau_rp; 3894 struct mlx5_ifc_field_select_r_roce_rp_bits field_select_r_roce_rp; 3895 struct mlx5_ifc_field_select_r_roce_np_bits field_select_r_roce_np; 3896 u8 reserved_at_0[0x20]; 3897 }; 3898 3899 union mlx5_ifc_eth_cntrs_grp_data_layout_auto_bits { 3900 struct mlx5_ifc_eth_802_3_cntrs_grp_data_layout_bits eth_802_3_cntrs_grp_data_layout; 3901 struct mlx5_ifc_eth_2863_cntrs_grp_data_layout_bits eth_2863_cntrs_grp_data_layout; 3902 struct mlx5_ifc_eth_2819_cntrs_grp_data_layout_bits eth_2819_cntrs_grp_data_layout; 3903 struct mlx5_ifc_eth_3635_cntrs_grp_data_layout_bits eth_3635_cntrs_grp_data_layout; 3904 struct mlx5_ifc_eth_extended_cntrs_grp_data_layout_bits eth_extended_cntrs_grp_data_layout; 3905 struct mlx5_ifc_eth_per_prio_grp_data_layout_bits eth_per_prio_grp_data_layout; 3906 struct mlx5_ifc_eth_per_tc_prio_grp_data_layout_bits eth_per_tc_prio_grp_data_layout; 3907 struct mlx5_ifc_eth_per_tc_congest_prio_grp_data_layout_bits eth_per_tc_congest_prio_grp_data_layout; 3908 struct mlx5_ifc_ib_port_cntrs_grp_data_layout_bits ib_port_cntrs_grp_data_layout; 3909 struct mlx5_ifc_phys_layer_cntrs_bits phys_layer_cntrs; 3910 struct mlx5_ifc_phys_layer_statistical_cntrs_bits phys_layer_statistical_cntrs; 3911 u8 reserved_at_0[0x7c0]; 3912 }; 3913 3914 union mlx5_ifc_pcie_cntrs_grp_data_layout_auto_bits { 3915 struct mlx5_ifc_pcie_perf_cntrs_grp_data_layout_bits pcie_perf_cntrs_grp_data_layout; 3916 u8 reserved_at_0[0x7c0]; 3917 }; 3918 3919 union mlx5_ifc_event_auto_bits { 3920 struct mlx5_ifc_comp_event_bits comp_event; 3921 struct mlx5_ifc_dct_events_bits dct_events; 3922 struct mlx5_ifc_qp_events_bits qp_events; 3923 struct mlx5_ifc_wqe_associated_page_fault_event_bits wqe_associated_page_fault_event; 3924 struct mlx5_ifc_rdma_page_fault_event_bits rdma_page_fault_event; 3925 struct mlx5_ifc_cq_error_bits cq_error; 3926 struct mlx5_ifc_dropped_packet_logged_bits dropped_packet_logged; 3927 struct mlx5_ifc_port_state_change_event_bits port_state_change_event; 3928 struct mlx5_ifc_gpio_event_bits gpio_event; 3929 struct mlx5_ifc_db_bf_congestion_event_bits db_bf_congestion_event; 3930 struct mlx5_ifc_stall_vl_event_bits stall_vl_event; 3931 struct mlx5_ifc_cmd_inter_comp_event_bits cmd_inter_comp_event; 3932 u8 reserved_at_0[0xe0]; 3933 }; 3934 3935 struct mlx5_ifc_health_buffer_bits { 3936 u8 reserved_at_0[0x100]; 3937 3938 u8 assert_existptr[0x20]; 3939 3940 u8 assert_callra[0x20]; 3941 3942 u8 reserved_at_140[0x40]; 3943 3944 u8 fw_version[0x20]; 3945 3946 u8 hw_id[0x20]; 3947 3948 u8 reserved_at_1c0[0x20]; 3949 3950 u8 irisc_index[0x8]; 3951 u8 synd[0x8]; 3952 u8 ext_synd[0x10]; 3953 }; 3954 3955 struct mlx5_ifc_register_loopback_control_bits { 3956 u8 no_lb[0x1]; 3957 u8 reserved_at_1[0x7]; 3958 u8 port[0x8]; 3959 u8 reserved_at_10[0x10]; 3960 3961 u8 reserved_at_20[0x60]; 3962 }; 3963 3964 struct mlx5_ifc_vport_tc_element_bits { 3965 u8 traffic_class[0x4]; 3966 u8 reserved_at_4[0xc]; 3967 u8 vport_number[0x10]; 3968 }; 3969 3970 struct mlx5_ifc_vport_element_bits { 3971 u8 reserved_at_0[0x10]; 3972 u8 vport_number[0x10]; 3973 }; 3974 3975 enum { 3976 TSAR_ELEMENT_TSAR_TYPE_DWRR = 0x0, 3977 TSAR_ELEMENT_TSAR_TYPE_ROUND_ROBIN = 0x1, 3978 TSAR_ELEMENT_TSAR_TYPE_ETS = 0x2, 3979 }; 3980 3981 struct mlx5_ifc_tsar_element_bits { 3982 u8 reserved_at_0[0x8]; 3983 u8 tsar_type[0x8]; 3984 u8 reserved_at_10[0x10]; 3985 }; 3986 3987 enum { 3988 MLX5_TEARDOWN_HCA_OUT_FORCE_STATE_SUCCESS = 0x0, 3989 MLX5_TEARDOWN_HCA_OUT_FORCE_STATE_FAIL = 0x1, 3990 }; 3991 3992 struct mlx5_ifc_teardown_hca_out_bits { 3993 u8 status[0x8]; 3994 u8 reserved_at_8[0x18]; 3995 3996 u8 syndrome[0x20]; 3997 3998 u8 reserved_at_40[0x3f]; 3999 4000 u8 state[0x1]; 4001 }; 4002 4003 enum { 4004 MLX5_TEARDOWN_HCA_IN_PROFILE_GRACEFUL_CLOSE = 0x0, 4005 MLX5_TEARDOWN_HCA_IN_PROFILE_FORCE_CLOSE = 0x1, 4006 MLX5_TEARDOWN_HCA_IN_PROFILE_PREPARE_FAST_TEARDOWN = 0x2, 4007 }; 4008 4009 struct mlx5_ifc_teardown_hca_in_bits { 4010 u8 opcode[0x10]; 4011 u8 reserved_at_10[0x10]; 4012 4013 u8 reserved_at_20[0x10]; 4014 u8 op_mod[0x10]; 4015 4016 u8 reserved_at_40[0x10]; 4017 u8 profile[0x10]; 4018 4019 u8 reserved_at_60[0x20]; 4020 }; 4021 4022 struct mlx5_ifc_sqerr2rts_qp_out_bits { 4023 u8 status[0x8]; 4024 u8 reserved_at_8[0x18]; 4025 4026 u8 syndrome[0x20]; 4027 4028 u8 reserved_at_40[0x40]; 4029 }; 4030 4031 struct mlx5_ifc_sqerr2rts_qp_in_bits { 4032 u8 opcode[0x10]; 4033 u8 uid[0x10]; 4034 4035 u8 reserved_at_20[0x10]; 4036 u8 op_mod[0x10]; 4037 4038 u8 reserved_at_40[0x8]; 4039 u8 qpn[0x18]; 4040 4041 u8 reserved_at_60[0x20]; 4042 4043 u8 opt_param_mask[0x20]; 4044 4045 u8 reserved_at_a0[0x20]; 4046 4047 struct mlx5_ifc_qpc_bits qpc; 4048 4049 u8 reserved_at_800[0x80]; 4050 }; 4051 4052 struct mlx5_ifc_sqd2rts_qp_out_bits { 4053 u8 status[0x8]; 4054 u8 reserved_at_8[0x18]; 4055 4056 u8 syndrome[0x20]; 4057 4058 u8 reserved_at_40[0x40]; 4059 }; 4060 4061 struct mlx5_ifc_sqd2rts_qp_in_bits { 4062 u8 opcode[0x10]; 4063 u8 uid[0x10]; 4064 4065 u8 reserved_at_20[0x10]; 4066 u8 op_mod[0x10]; 4067 4068 u8 reserved_at_40[0x8]; 4069 u8 qpn[0x18]; 4070 4071 u8 reserved_at_60[0x20]; 4072 4073 u8 opt_param_mask[0x20]; 4074 4075 u8 reserved_at_a0[0x20]; 4076 4077 struct mlx5_ifc_qpc_bits qpc; 4078 4079 u8 reserved_at_800[0x80]; 4080 }; 4081 4082 struct mlx5_ifc_set_roce_address_out_bits { 4083 u8 status[0x8]; 4084 u8 reserved_at_8[0x18]; 4085 4086 u8 syndrome[0x20]; 4087 4088 u8 reserved_at_40[0x40]; 4089 }; 4090 4091 struct mlx5_ifc_set_roce_address_in_bits { 4092 u8 opcode[0x10]; 4093 u8 reserved_at_10[0x10]; 4094 4095 u8 reserved_at_20[0x10]; 4096 u8 op_mod[0x10]; 4097 4098 u8 roce_address_index[0x10]; 4099 u8 reserved_at_50[0xc]; 4100 u8 vhca_port_num[0x4]; 4101 4102 u8 reserved_at_60[0x20]; 4103 4104 struct mlx5_ifc_roce_addr_layout_bits roce_address; 4105 }; 4106 4107 struct mlx5_ifc_set_mad_demux_out_bits { 4108 u8 status[0x8]; 4109 u8 reserved_at_8[0x18]; 4110 4111 u8 syndrome[0x20]; 4112 4113 u8 reserved_at_40[0x40]; 4114 }; 4115 4116 enum { 4117 MLX5_SET_MAD_DEMUX_IN_DEMUX_MODE_PASS_ALL = 0x0, 4118 MLX5_SET_MAD_DEMUX_IN_DEMUX_MODE_SELECTIVE = 0x2, 4119 }; 4120 4121 struct mlx5_ifc_set_mad_demux_in_bits { 4122 u8 opcode[0x10]; 4123 u8 reserved_at_10[0x10]; 4124 4125 u8 reserved_at_20[0x10]; 4126 u8 op_mod[0x10]; 4127 4128 u8 reserved_at_40[0x20]; 4129 4130 u8 reserved_at_60[0x6]; 4131 u8 demux_mode[0x2]; 4132 u8 reserved_at_68[0x18]; 4133 }; 4134 4135 struct mlx5_ifc_set_l2_table_entry_out_bits { 4136 u8 status[0x8]; 4137 u8 reserved_at_8[0x18]; 4138 4139 u8 syndrome[0x20]; 4140 4141 u8 reserved_at_40[0x40]; 4142 }; 4143 4144 struct mlx5_ifc_set_l2_table_entry_in_bits { 4145 u8 opcode[0x10]; 4146 u8 reserved_at_10[0x10]; 4147 4148 u8 reserved_at_20[0x10]; 4149 u8 op_mod[0x10]; 4150 4151 u8 reserved_at_40[0x60]; 4152 4153 u8 reserved_at_a0[0x8]; 4154 u8 table_index[0x18]; 4155 4156 u8 reserved_at_c0[0x20]; 4157 4158 u8 reserved_at_e0[0x13]; 4159 u8 vlan_valid[0x1]; 4160 u8 vlan[0xc]; 4161 4162 struct mlx5_ifc_mac_address_layout_bits mac_address; 4163 4164 u8 reserved_at_140[0xc0]; 4165 }; 4166 4167 struct mlx5_ifc_set_issi_out_bits { 4168 u8 status[0x8]; 4169 u8 reserved_at_8[0x18]; 4170 4171 u8 syndrome[0x20]; 4172 4173 u8 reserved_at_40[0x40]; 4174 }; 4175 4176 struct mlx5_ifc_set_issi_in_bits { 4177 u8 opcode[0x10]; 4178 u8 reserved_at_10[0x10]; 4179 4180 u8 reserved_at_20[0x10]; 4181 u8 op_mod[0x10]; 4182 4183 u8 reserved_at_40[0x10]; 4184 u8 current_issi[0x10]; 4185 4186 u8 reserved_at_60[0x20]; 4187 }; 4188 4189 struct mlx5_ifc_set_hca_cap_out_bits { 4190 u8 status[0x8]; 4191 u8 reserved_at_8[0x18]; 4192 4193 u8 syndrome[0x20]; 4194 4195 u8 reserved_at_40[0x40]; 4196 }; 4197 4198 struct mlx5_ifc_set_hca_cap_in_bits { 4199 u8 opcode[0x10]; 4200 u8 reserved_at_10[0x10]; 4201 4202 u8 reserved_at_20[0x10]; 4203 u8 op_mod[0x10]; 4204 4205 u8 reserved_at_40[0x40]; 4206 4207 union mlx5_ifc_hca_cap_union_bits capability; 4208 }; 4209 4210 enum { 4211 MLX5_SET_FTE_MODIFY_ENABLE_MASK_ACTION = 0x0, 4212 MLX5_SET_FTE_MODIFY_ENABLE_MASK_FLOW_TAG = 0x1, 4213 MLX5_SET_FTE_MODIFY_ENABLE_MASK_DESTINATION_LIST = 0x2, 4214 MLX5_SET_FTE_MODIFY_ENABLE_MASK_FLOW_COUNTERS = 0x3, 4215 MLX5_SET_FTE_MODIFY_ENABLE_MASK_IPSEC_OBJ_ID = 0x4 4216 }; 4217 4218 struct mlx5_ifc_set_fte_out_bits { 4219 u8 status[0x8]; 4220 u8 reserved_at_8[0x18]; 4221 4222 u8 syndrome[0x20]; 4223 4224 u8 reserved_at_40[0x40]; 4225 }; 4226 4227 struct mlx5_ifc_set_fte_in_bits { 4228 u8 opcode[0x10]; 4229 u8 reserved_at_10[0x10]; 4230 4231 u8 reserved_at_20[0x10]; 4232 u8 op_mod[0x10]; 4233 4234 u8 other_vport[0x1]; 4235 u8 reserved_at_41[0xf]; 4236 u8 vport_number[0x10]; 4237 4238 u8 reserved_at_60[0x20]; 4239 4240 u8 table_type[0x8]; 4241 u8 reserved_at_88[0x18]; 4242 4243 u8 reserved_at_a0[0x8]; 4244 u8 table_id[0x18]; 4245 4246 u8 ignore_flow_level[0x1]; 4247 u8 reserved_at_c1[0x17]; 4248 u8 modify_enable_mask[0x8]; 4249 4250 u8 reserved_at_e0[0x20]; 4251 4252 u8 flow_index[0x20]; 4253 4254 u8 reserved_at_120[0xe0]; 4255 4256 struct mlx5_ifc_flow_context_bits flow_context; 4257 }; 4258 4259 struct mlx5_ifc_rts2rts_qp_out_bits { 4260 u8 status[0x8]; 4261 u8 reserved_at_8[0x18]; 4262 4263 u8 syndrome[0x20]; 4264 4265 u8 reserved_at_40[0x20]; 4266 u8 ece[0x20]; 4267 }; 4268 4269 struct mlx5_ifc_rts2rts_qp_in_bits { 4270 u8 opcode[0x10]; 4271 u8 uid[0x10]; 4272 4273 u8 reserved_at_20[0x10]; 4274 u8 op_mod[0x10]; 4275 4276 u8 reserved_at_40[0x8]; 4277 u8 qpn[0x18]; 4278 4279 u8 reserved_at_60[0x20]; 4280 4281 u8 opt_param_mask[0x20]; 4282 4283 u8 ece[0x20]; 4284 4285 struct mlx5_ifc_qpc_bits qpc; 4286 4287 u8 reserved_at_800[0x80]; 4288 }; 4289 4290 struct mlx5_ifc_rtr2rts_qp_out_bits { 4291 u8 status[0x8]; 4292 u8 reserved_at_8[0x18]; 4293 4294 u8 syndrome[0x20]; 4295 4296 u8 reserved_at_40[0x20]; 4297 u8 ece[0x20]; 4298 }; 4299 4300 struct mlx5_ifc_rtr2rts_qp_in_bits { 4301 u8 opcode[0x10]; 4302 u8 uid[0x10]; 4303 4304 u8 reserved_at_20[0x10]; 4305 u8 op_mod[0x10]; 4306 4307 u8 reserved_at_40[0x8]; 4308 u8 qpn[0x18]; 4309 4310 u8 reserved_at_60[0x20]; 4311 4312 u8 opt_param_mask[0x20]; 4313 4314 u8 ece[0x20]; 4315 4316 struct mlx5_ifc_qpc_bits qpc; 4317 4318 u8 reserved_at_800[0x80]; 4319 }; 4320 4321 struct mlx5_ifc_rst2init_qp_out_bits { 4322 u8 status[0x8]; 4323 u8 reserved_at_8[0x18]; 4324 4325 u8 syndrome[0x20]; 4326 4327 u8 reserved_at_40[0x20]; 4328 u8 ece[0x20]; 4329 }; 4330 4331 struct mlx5_ifc_rst2init_qp_in_bits { 4332 u8 opcode[0x10]; 4333 u8 uid[0x10]; 4334 4335 u8 reserved_at_20[0x10]; 4336 u8 op_mod[0x10]; 4337 4338 u8 reserved_at_40[0x8]; 4339 u8 qpn[0x18]; 4340 4341 u8 reserved_at_60[0x20]; 4342 4343 u8 opt_param_mask[0x20]; 4344 4345 u8 ece[0x20]; 4346 4347 struct mlx5_ifc_qpc_bits qpc; 4348 4349 u8 reserved_at_800[0x80]; 4350 }; 4351 4352 struct mlx5_ifc_query_xrq_out_bits { 4353 u8 status[0x8]; 4354 u8 reserved_at_8[0x18]; 4355 4356 u8 syndrome[0x20]; 4357 4358 u8 reserved_at_40[0x40]; 4359 4360 struct mlx5_ifc_xrqc_bits xrq_context; 4361 }; 4362 4363 struct mlx5_ifc_query_xrq_in_bits { 4364 u8 opcode[0x10]; 4365 u8 reserved_at_10[0x10]; 4366 4367 u8 reserved_at_20[0x10]; 4368 u8 op_mod[0x10]; 4369 4370 u8 reserved_at_40[0x8]; 4371 u8 xrqn[0x18]; 4372 4373 u8 reserved_at_60[0x20]; 4374 }; 4375 4376 struct mlx5_ifc_query_xrc_srq_out_bits { 4377 u8 status[0x8]; 4378 u8 reserved_at_8[0x18]; 4379 4380 u8 syndrome[0x20]; 4381 4382 u8 reserved_at_40[0x40]; 4383 4384 struct mlx5_ifc_xrc_srqc_bits xrc_srq_context_entry; 4385 4386 u8 reserved_at_280[0x600]; 4387 4388 u8 pas[][0x40]; 4389 }; 4390 4391 struct mlx5_ifc_query_xrc_srq_in_bits { 4392 u8 opcode[0x10]; 4393 u8 reserved_at_10[0x10]; 4394 4395 u8 reserved_at_20[0x10]; 4396 u8 op_mod[0x10]; 4397 4398 u8 reserved_at_40[0x8]; 4399 u8 xrc_srqn[0x18]; 4400 4401 u8 reserved_at_60[0x20]; 4402 }; 4403 4404 enum { 4405 MLX5_QUERY_VPORT_STATE_OUT_STATE_DOWN = 0x0, 4406 MLX5_QUERY_VPORT_STATE_OUT_STATE_UP = 0x1, 4407 }; 4408 4409 struct mlx5_ifc_query_vport_state_out_bits { 4410 u8 status[0x8]; 4411 u8 reserved_at_8[0x18]; 4412 4413 u8 syndrome[0x20]; 4414 4415 u8 reserved_at_40[0x20]; 4416 4417 u8 reserved_at_60[0x18]; 4418 u8 admin_state[0x4]; 4419 u8 state[0x4]; 4420 }; 4421 4422 enum { 4423 MLX5_VPORT_STATE_OP_MOD_VNIC_VPORT = 0x0, 4424 MLX5_VPORT_STATE_OP_MOD_ESW_VPORT = 0x1, 4425 MLX5_VPORT_STATE_OP_MOD_UPLINK = 0x2, 4426 }; 4427 4428 struct mlx5_ifc_arm_monitor_counter_in_bits { 4429 u8 opcode[0x10]; 4430 u8 uid[0x10]; 4431 4432 u8 reserved_at_20[0x10]; 4433 u8 op_mod[0x10]; 4434 4435 u8 reserved_at_40[0x20]; 4436 4437 u8 reserved_at_60[0x20]; 4438 }; 4439 4440 struct mlx5_ifc_arm_monitor_counter_out_bits { 4441 u8 status[0x8]; 4442 u8 reserved_at_8[0x18]; 4443 4444 u8 syndrome[0x20]; 4445 4446 u8 reserved_at_40[0x40]; 4447 }; 4448 4449 enum { 4450 MLX5_QUERY_MONITOR_CNT_TYPE_PPCNT = 0x0, 4451 MLX5_QUERY_MONITOR_CNT_TYPE_Q_COUNTER = 0x1, 4452 }; 4453 4454 enum mlx5_monitor_counter_ppcnt { 4455 MLX5_QUERY_MONITOR_PPCNT_IN_RANGE_LENGTH_ERRORS = 0x0, 4456 MLX5_QUERY_MONITOR_PPCNT_OUT_OF_RANGE_LENGTH_FIELD = 0x1, 4457 MLX5_QUERY_MONITOR_PPCNT_FRAME_TOO_LONG_ERRORS = 0x2, 4458 MLX5_QUERY_MONITOR_PPCNT_FRAME_CHECK_SEQUENCE_ERRORS = 0x3, 4459 MLX5_QUERY_MONITOR_PPCNT_ALIGNMENT_ERRORS = 0x4, 4460 MLX5_QUERY_MONITOR_PPCNT_IF_OUT_DISCARDS = 0x5, 4461 }; 4462 4463 enum { 4464 MLX5_QUERY_MONITOR_Q_COUNTER_RX_OUT_OF_BUFFER = 0x4, 4465 }; 4466 4467 struct mlx5_ifc_monitor_counter_output_bits { 4468 u8 reserved_at_0[0x4]; 4469 u8 type[0x4]; 4470 u8 reserved_at_8[0x8]; 4471 u8 counter[0x10]; 4472 4473 u8 counter_group_id[0x20]; 4474 }; 4475 4476 #define MLX5_CMD_SET_MONITOR_NUM_PPCNT_COUNTER_SET1 (6) 4477 #define MLX5_CMD_SET_MONITOR_NUM_Q_COUNTERS_SET1 (1) 4478 #define MLX5_CMD_SET_MONITOR_NUM_COUNTER (MLX5_CMD_SET_MONITOR_NUM_PPCNT_COUNTER_SET1 +\ 4479 MLX5_CMD_SET_MONITOR_NUM_Q_COUNTERS_SET1) 4480 4481 struct mlx5_ifc_set_monitor_counter_in_bits { 4482 u8 opcode[0x10]; 4483 u8 uid[0x10]; 4484 4485 u8 reserved_at_20[0x10]; 4486 u8 op_mod[0x10]; 4487 4488 u8 reserved_at_40[0x10]; 4489 u8 num_of_counters[0x10]; 4490 4491 u8 reserved_at_60[0x20]; 4492 4493 struct mlx5_ifc_monitor_counter_output_bits monitor_counter[MLX5_CMD_SET_MONITOR_NUM_COUNTER]; 4494 }; 4495 4496 struct mlx5_ifc_set_monitor_counter_out_bits { 4497 u8 status[0x8]; 4498 u8 reserved_at_8[0x18]; 4499 4500 u8 syndrome[0x20]; 4501 4502 u8 reserved_at_40[0x40]; 4503 }; 4504 4505 struct mlx5_ifc_query_vport_state_in_bits { 4506 u8 opcode[0x10]; 4507 u8 reserved_at_10[0x10]; 4508 4509 u8 reserved_at_20[0x10]; 4510 u8 op_mod[0x10]; 4511 4512 u8 other_vport[0x1]; 4513 u8 reserved_at_41[0xf]; 4514 u8 vport_number[0x10]; 4515 4516 u8 reserved_at_60[0x20]; 4517 }; 4518 4519 struct mlx5_ifc_query_vnic_env_out_bits { 4520 u8 status[0x8]; 4521 u8 reserved_at_8[0x18]; 4522 4523 u8 syndrome[0x20]; 4524 4525 u8 reserved_at_40[0x40]; 4526 4527 struct mlx5_ifc_vnic_diagnostic_statistics_bits vport_env; 4528 }; 4529 4530 enum { 4531 MLX5_QUERY_VNIC_ENV_IN_OP_MOD_VPORT_DIAG_STATISTICS = 0x0, 4532 }; 4533 4534 struct mlx5_ifc_query_vnic_env_in_bits { 4535 u8 opcode[0x10]; 4536 u8 reserved_at_10[0x10]; 4537 4538 u8 reserved_at_20[0x10]; 4539 u8 op_mod[0x10]; 4540 4541 u8 other_vport[0x1]; 4542 u8 reserved_at_41[0xf]; 4543 u8 vport_number[0x10]; 4544 4545 u8 reserved_at_60[0x20]; 4546 }; 4547 4548 struct mlx5_ifc_query_vport_counter_out_bits { 4549 u8 status[0x8]; 4550 u8 reserved_at_8[0x18]; 4551 4552 u8 syndrome[0x20]; 4553 4554 u8 reserved_at_40[0x40]; 4555 4556 struct mlx5_ifc_traffic_counter_bits received_errors; 4557 4558 struct mlx5_ifc_traffic_counter_bits transmit_errors; 4559 4560 struct mlx5_ifc_traffic_counter_bits received_ib_unicast; 4561 4562 struct mlx5_ifc_traffic_counter_bits transmitted_ib_unicast; 4563 4564 struct mlx5_ifc_traffic_counter_bits received_ib_multicast; 4565 4566 struct mlx5_ifc_traffic_counter_bits transmitted_ib_multicast; 4567 4568 struct mlx5_ifc_traffic_counter_bits received_eth_broadcast; 4569 4570 struct mlx5_ifc_traffic_counter_bits transmitted_eth_broadcast; 4571 4572 struct mlx5_ifc_traffic_counter_bits received_eth_unicast; 4573 4574 struct mlx5_ifc_traffic_counter_bits transmitted_eth_unicast; 4575 4576 struct mlx5_ifc_traffic_counter_bits received_eth_multicast; 4577 4578 struct mlx5_ifc_traffic_counter_bits transmitted_eth_multicast; 4579 4580 u8 reserved_at_680[0xa00]; 4581 }; 4582 4583 enum { 4584 MLX5_QUERY_VPORT_COUNTER_IN_OP_MOD_VPORT_COUNTERS = 0x0, 4585 }; 4586 4587 struct mlx5_ifc_query_vport_counter_in_bits { 4588 u8 opcode[0x10]; 4589 u8 reserved_at_10[0x10]; 4590 4591 u8 reserved_at_20[0x10]; 4592 u8 op_mod[0x10]; 4593 4594 u8 other_vport[0x1]; 4595 u8 reserved_at_41[0xb]; 4596 u8 port_num[0x4]; 4597 u8 vport_number[0x10]; 4598 4599 u8 reserved_at_60[0x60]; 4600 4601 u8 clear[0x1]; 4602 u8 reserved_at_c1[0x1f]; 4603 4604 u8 reserved_at_e0[0x20]; 4605 }; 4606 4607 struct mlx5_ifc_query_tis_out_bits { 4608 u8 status[0x8]; 4609 u8 reserved_at_8[0x18]; 4610 4611 u8 syndrome[0x20]; 4612 4613 u8 reserved_at_40[0x40]; 4614 4615 struct mlx5_ifc_tisc_bits tis_context; 4616 }; 4617 4618 struct mlx5_ifc_query_tis_in_bits { 4619 u8 opcode[0x10]; 4620 u8 reserved_at_10[0x10]; 4621 4622 u8 reserved_at_20[0x10]; 4623 u8 op_mod[0x10]; 4624 4625 u8 reserved_at_40[0x8]; 4626 u8 tisn[0x18]; 4627 4628 u8 reserved_at_60[0x20]; 4629 }; 4630 4631 struct mlx5_ifc_query_tir_out_bits { 4632 u8 status[0x8]; 4633 u8 reserved_at_8[0x18]; 4634 4635 u8 syndrome[0x20]; 4636 4637 u8 reserved_at_40[0xc0]; 4638 4639 struct mlx5_ifc_tirc_bits tir_context; 4640 }; 4641 4642 struct mlx5_ifc_query_tir_in_bits { 4643 u8 opcode[0x10]; 4644 u8 reserved_at_10[0x10]; 4645 4646 u8 reserved_at_20[0x10]; 4647 u8 op_mod[0x10]; 4648 4649 u8 reserved_at_40[0x8]; 4650 u8 tirn[0x18]; 4651 4652 u8 reserved_at_60[0x20]; 4653 }; 4654 4655 struct mlx5_ifc_query_srq_out_bits { 4656 u8 status[0x8]; 4657 u8 reserved_at_8[0x18]; 4658 4659 u8 syndrome[0x20]; 4660 4661 u8 reserved_at_40[0x40]; 4662 4663 struct mlx5_ifc_srqc_bits srq_context_entry; 4664 4665 u8 reserved_at_280[0x600]; 4666 4667 u8 pas[][0x40]; 4668 }; 4669 4670 struct mlx5_ifc_query_srq_in_bits { 4671 u8 opcode[0x10]; 4672 u8 reserved_at_10[0x10]; 4673 4674 u8 reserved_at_20[0x10]; 4675 u8 op_mod[0x10]; 4676 4677 u8 reserved_at_40[0x8]; 4678 u8 srqn[0x18]; 4679 4680 u8 reserved_at_60[0x20]; 4681 }; 4682 4683 struct mlx5_ifc_query_sq_out_bits { 4684 u8 status[0x8]; 4685 u8 reserved_at_8[0x18]; 4686 4687 u8 syndrome[0x20]; 4688 4689 u8 reserved_at_40[0xc0]; 4690 4691 struct mlx5_ifc_sqc_bits sq_context; 4692 }; 4693 4694 struct mlx5_ifc_query_sq_in_bits { 4695 u8 opcode[0x10]; 4696 u8 reserved_at_10[0x10]; 4697 4698 u8 reserved_at_20[0x10]; 4699 u8 op_mod[0x10]; 4700 4701 u8 reserved_at_40[0x8]; 4702 u8 sqn[0x18]; 4703 4704 u8 reserved_at_60[0x20]; 4705 }; 4706 4707 struct mlx5_ifc_query_special_contexts_out_bits { 4708 u8 status[0x8]; 4709 u8 reserved_at_8[0x18]; 4710 4711 u8 syndrome[0x20]; 4712 4713 u8 dump_fill_mkey[0x20]; 4714 4715 u8 resd_lkey[0x20]; 4716 4717 u8 null_mkey[0x20]; 4718 4719 u8 reserved_at_a0[0x60]; 4720 }; 4721 4722 struct mlx5_ifc_query_special_contexts_in_bits { 4723 u8 opcode[0x10]; 4724 u8 reserved_at_10[0x10]; 4725 4726 u8 reserved_at_20[0x10]; 4727 u8 op_mod[0x10]; 4728 4729 u8 reserved_at_40[0x40]; 4730 }; 4731 4732 struct mlx5_ifc_query_scheduling_element_out_bits { 4733 u8 opcode[0x10]; 4734 u8 reserved_at_10[0x10]; 4735 4736 u8 reserved_at_20[0x10]; 4737 u8 op_mod[0x10]; 4738 4739 u8 reserved_at_40[0xc0]; 4740 4741 struct mlx5_ifc_scheduling_context_bits scheduling_context; 4742 4743 u8 reserved_at_300[0x100]; 4744 }; 4745 4746 enum { 4747 SCHEDULING_HIERARCHY_E_SWITCH = 0x2, 4748 }; 4749 4750 struct mlx5_ifc_query_scheduling_element_in_bits { 4751 u8 opcode[0x10]; 4752 u8 reserved_at_10[0x10]; 4753 4754 u8 reserved_at_20[0x10]; 4755 u8 op_mod[0x10]; 4756 4757 u8 scheduling_hierarchy[0x8]; 4758 u8 reserved_at_48[0x18]; 4759 4760 u8 scheduling_element_id[0x20]; 4761 4762 u8 reserved_at_80[0x180]; 4763 }; 4764 4765 struct mlx5_ifc_query_rqt_out_bits { 4766 u8 status[0x8]; 4767 u8 reserved_at_8[0x18]; 4768 4769 u8 syndrome[0x20]; 4770 4771 u8 reserved_at_40[0xc0]; 4772 4773 struct mlx5_ifc_rqtc_bits rqt_context; 4774 }; 4775 4776 struct mlx5_ifc_query_rqt_in_bits { 4777 u8 opcode[0x10]; 4778 u8 reserved_at_10[0x10]; 4779 4780 u8 reserved_at_20[0x10]; 4781 u8 op_mod[0x10]; 4782 4783 u8 reserved_at_40[0x8]; 4784 u8 rqtn[0x18]; 4785 4786 u8 reserved_at_60[0x20]; 4787 }; 4788 4789 struct mlx5_ifc_query_rq_out_bits { 4790 u8 status[0x8]; 4791 u8 reserved_at_8[0x18]; 4792 4793 u8 syndrome[0x20]; 4794 4795 u8 reserved_at_40[0xc0]; 4796 4797 struct mlx5_ifc_rqc_bits rq_context; 4798 }; 4799 4800 struct mlx5_ifc_query_rq_in_bits { 4801 u8 opcode[0x10]; 4802 u8 reserved_at_10[0x10]; 4803 4804 u8 reserved_at_20[0x10]; 4805 u8 op_mod[0x10]; 4806 4807 u8 reserved_at_40[0x8]; 4808 u8 rqn[0x18]; 4809 4810 u8 reserved_at_60[0x20]; 4811 }; 4812 4813 struct mlx5_ifc_query_roce_address_out_bits { 4814 u8 status[0x8]; 4815 u8 reserved_at_8[0x18]; 4816 4817 u8 syndrome[0x20]; 4818 4819 u8 reserved_at_40[0x40]; 4820 4821 struct mlx5_ifc_roce_addr_layout_bits roce_address; 4822 }; 4823 4824 struct mlx5_ifc_query_roce_address_in_bits { 4825 u8 opcode[0x10]; 4826 u8 reserved_at_10[0x10]; 4827 4828 u8 reserved_at_20[0x10]; 4829 u8 op_mod[0x10]; 4830 4831 u8 roce_address_index[0x10]; 4832 u8 reserved_at_50[0xc]; 4833 u8 vhca_port_num[0x4]; 4834 4835 u8 reserved_at_60[0x20]; 4836 }; 4837 4838 struct mlx5_ifc_query_rmp_out_bits { 4839 u8 status[0x8]; 4840 u8 reserved_at_8[0x18]; 4841 4842 u8 syndrome[0x20]; 4843 4844 u8 reserved_at_40[0xc0]; 4845 4846 struct mlx5_ifc_rmpc_bits rmp_context; 4847 }; 4848 4849 struct mlx5_ifc_query_rmp_in_bits { 4850 u8 opcode[0x10]; 4851 u8 reserved_at_10[0x10]; 4852 4853 u8 reserved_at_20[0x10]; 4854 u8 op_mod[0x10]; 4855 4856 u8 reserved_at_40[0x8]; 4857 u8 rmpn[0x18]; 4858 4859 u8 reserved_at_60[0x20]; 4860 }; 4861 4862 struct mlx5_ifc_query_qp_out_bits { 4863 u8 status[0x8]; 4864 u8 reserved_at_8[0x18]; 4865 4866 u8 syndrome[0x20]; 4867 4868 u8 reserved_at_40[0x20]; 4869 u8 ece[0x20]; 4870 4871 u8 opt_param_mask[0x20]; 4872 4873 u8 reserved_at_a0[0x20]; 4874 4875 struct mlx5_ifc_qpc_bits qpc; 4876 4877 u8 reserved_at_800[0x80]; 4878 4879 u8 pas[][0x40]; 4880 }; 4881 4882 struct mlx5_ifc_query_qp_in_bits { 4883 u8 opcode[0x10]; 4884 u8 reserved_at_10[0x10]; 4885 4886 u8 reserved_at_20[0x10]; 4887 u8 op_mod[0x10]; 4888 4889 u8 reserved_at_40[0x8]; 4890 u8 qpn[0x18]; 4891 4892 u8 reserved_at_60[0x20]; 4893 }; 4894 4895 struct mlx5_ifc_query_q_counter_out_bits { 4896 u8 status[0x8]; 4897 u8 reserved_at_8[0x18]; 4898 4899 u8 syndrome[0x20]; 4900 4901 u8 reserved_at_40[0x40]; 4902 4903 u8 rx_write_requests[0x20]; 4904 4905 u8 reserved_at_a0[0x20]; 4906 4907 u8 rx_read_requests[0x20]; 4908 4909 u8 reserved_at_e0[0x20]; 4910 4911 u8 rx_atomic_requests[0x20]; 4912 4913 u8 reserved_at_120[0x20]; 4914 4915 u8 rx_dct_connect[0x20]; 4916 4917 u8 reserved_at_160[0x20]; 4918 4919 u8 out_of_buffer[0x20]; 4920 4921 u8 reserved_at_1a0[0x20]; 4922 4923 u8 out_of_sequence[0x20]; 4924 4925 u8 reserved_at_1e0[0x20]; 4926 4927 u8 duplicate_request[0x20]; 4928 4929 u8 reserved_at_220[0x20]; 4930 4931 u8 rnr_nak_retry_err[0x20]; 4932 4933 u8 reserved_at_260[0x20]; 4934 4935 u8 packet_seq_err[0x20]; 4936 4937 u8 reserved_at_2a0[0x20]; 4938 4939 u8 implied_nak_seq_err[0x20]; 4940 4941 u8 reserved_at_2e0[0x20]; 4942 4943 u8 local_ack_timeout_err[0x20]; 4944 4945 u8 reserved_at_320[0xa0]; 4946 4947 u8 resp_local_length_error[0x20]; 4948 4949 u8 req_local_length_error[0x20]; 4950 4951 u8 resp_local_qp_error[0x20]; 4952 4953 u8 local_operation_error[0x20]; 4954 4955 u8 resp_local_protection[0x20]; 4956 4957 u8 req_local_protection[0x20]; 4958 4959 u8 resp_cqe_error[0x20]; 4960 4961 u8 req_cqe_error[0x20]; 4962 4963 u8 req_mw_binding[0x20]; 4964 4965 u8 req_bad_response[0x20]; 4966 4967 u8 req_remote_invalid_request[0x20]; 4968 4969 u8 resp_remote_invalid_request[0x20]; 4970 4971 u8 req_remote_access_errors[0x20]; 4972 4973 u8 resp_remote_access_errors[0x20]; 4974 4975 u8 req_remote_operation_errors[0x20]; 4976 4977 u8 req_transport_retries_exceeded[0x20]; 4978 4979 u8 cq_overflow[0x20]; 4980 4981 u8 resp_cqe_flush_error[0x20]; 4982 4983 u8 req_cqe_flush_error[0x20]; 4984 4985 u8 reserved_at_620[0x20]; 4986 4987 u8 roce_adp_retrans[0x20]; 4988 4989 u8 roce_adp_retrans_to[0x20]; 4990 4991 u8 roce_slow_restart[0x20]; 4992 4993 u8 roce_slow_restart_cnps[0x20]; 4994 4995 u8 roce_slow_restart_trans[0x20]; 4996 4997 u8 reserved_at_6e0[0x120]; 4998 }; 4999 5000 struct mlx5_ifc_query_q_counter_in_bits { 5001 u8 opcode[0x10]; 5002 u8 reserved_at_10[0x10]; 5003 5004 u8 reserved_at_20[0x10]; 5005 u8 op_mod[0x10]; 5006 5007 u8 reserved_at_40[0x80]; 5008 5009 u8 clear[0x1]; 5010 u8 reserved_at_c1[0x1f]; 5011 5012 u8 reserved_at_e0[0x18]; 5013 u8 counter_set_id[0x8]; 5014 }; 5015 5016 struct mlx5_ifc_query_pages_out_bits { 5017 u8 status[0x8]; 5018 u8 reserved_at_8[0x18]; 5019 5020 u8 syndrome[0x20]; 5021 5022 u8 embedded_cpu_function[0x1]; 5023 u8 reserved_at_41[0xf]; 5024 u8 function_id[0x10]; 5025 5026 u8 num_pages[0x20]; 5027 }; 5028 5029 enum { 5030 MLX5_QUERY_PAGES_IN_OP_MOD_BOOT_PAGES = 0x1, 5031 MLX5_QUERY_PAGES_IN_OP_MOD_INIT_PAGES = 0x2, 5032 MLX5_QUERY_PAGES_IN_OP_MOD_REGULAR_PAGES = 0x3, 5033 }; 5034 5035 struct mlx5_ifc_query_pages_in_bits { 5036 u8 opcode[0x10]; 5037 u8 reserved_at_10[0x10]; 5038 5039 u8 reserved_at_20[0x10]; 5040 u8 op_mod[0x10]; 5041 5042 u8 embedded_cpu_function[0x1]; 5043 u8 reserved_at_41[0xf]; 5044 u8 function_id[0x10]; 5045 5046 u8 reserved_at_60[0x20]; 5047 }; 5048 5049 struct mlx5_ifc_query_nic_vport_context_out_bits { 5050 u8 status[0x8]; 5051 u8 reserved_at_8[0x18]; 5052 5053 u8 syndrome[0x20]; 5054 5055 u8 reserved_at_40[0x40]; 5056 5057 struct mlx5_ifc_nic_vport_context_bits nic_vport_context; 5058 }; 5059 5060 struct mlx5_ifc_query_nic_vport_context_in_bits { 5061 u8 opcode[0x10]; 5062 u8 reserved_at_10[0x10]; 5063 5064 u8 reserved_at_20[0x10]; 5065 u8 op_mod[0x10]; 5066 5067 u8 other_vport[0x1]; 5068 u8 reserved_at_41[0xf]; 5069 u8 vport_number[0x10]; 5070 5071 u8 reserved_at_60[0x5]; 5072 u8 allowed_list_type[0x3]; 5073 u8 reserved_at_68[0x18]; 5074 }; 5075 5076 struct mlx5_ifc_query_mkey_out_bits { 5077 u8 status[0x8]; 5078 u8 reserved_at_8[0x18]; 5079 5080 u8 syndrome[0x20]; 5081 5082 u8 reserved_at_40[0x40]; 5083 5084 struct mlx5_ifc_mkc_bits memory_key_mkey_entry; 5085 5086 u8 reserved_at_280[0x600]; 5087 5088 u8 bsf0_klm0_pas_mtt0_1[16][0x8]; 5089 5090 u8 bsf1_klm1_pas_mtt2_3[16][0x8]; 5091 }; 5092 5093 struct mlx5_ifc_query_mkey_in_bits { 5094 u8 opcode[0x10]; 5095 u8 reserved_at_10[0x10]; 5096 5097 u8 reserved_at_20[0x10]; 5098 u8 op_mod[0x10]; 5099 5100 u8 reserved_at_40[0x8]; 5101 u8 mkey_index[0x18]; 5102 5103 u8 pg_access[0x1]; 5104 u8 reserved_at_61[0x1f]; 5105 }; 5106 5107 struct mlx5_ifc_query_mad_demux_out_bits { 5108 u8 status[0x8]; 5109 u8 reserved_at_8[0x18]; 5110 5111 u8 syndrome[0x20]; 5112 5113 u8 reserved_at_40[0x40]; 5114 5115 u8 mad_dumux_parameters_block[0x20]; 5116 }; 5117 5118 struct mlx5_ifc_query_mad_demux_in_bits { 5119 u8 opcode[0x10]; 5120 u8 reserved_at_10[0x10]; 5121 5122 u8 reserved_at_20[0x10]; 5123 u8 op_mod[0x10]; 5124 5125 u8 reserved_at_40[0x40]; 5126 }; 5127 5128 struct mlx5_ifc_query_l2_table_entry_out_bits { 5129 u8 status[0x8]; 5130 u8 reserved_at_8[0x18]; 5131 5132 u8 syndrome[0x20]; 5133 5134 u8 reserved_at_40[0xa0]; 5135 5136 u8 reserved_at_e0[0x13]; 5137 u8 vlan_valid[0x1]; 5138 u8 vlan[0xc]; 5139 5140 struct mlx5_ifc_mac_address_layout_bits mac_address; 5141 5142 u8 reserved_at_140[0xc0]; 5143 }; 5144 5145 struct mlx5_ifc_query_l2_table_entry_in_bits { 5146 u8 opcode[0x10]; 5147 u8 reserved_at_10[0x10]; 5148 5149 u8 reserved_at_20[0x10]; 5150 u8 op_mod[0x10]; 5151 5152 u8 reserved_at_40[0x60]; 5153 5154 u8 reserved_at_a0[0x8]; 5155 u8 table_index[0x18]; 5156 5157 u8 reserved_at_c0[0x140]; 5158 }; 5159 5160 struct mlx5_ifc_query_issi_out_bits { 5161 u8 status[0x8]; 5162 u8 reserved_at_8[0x18]; 5163 5164 u8 syndrome[0x20]; 5165 5166 u8 reserved_at_40[0x10]; 5167 u8 current_issi[0x10]; 5168 5169 u8 reserved_at_60[0xa0]; 5170 5171 u8 reserved_at_100[76][0x8]; 5172 u8 supported_issi_dw0[0x20]; 5173 }; 5174 5175 struct mlx5_ifc_query_issi_in_bits { 5176 u8 opcode[0x10]; 5177 u8 reserved_at_10[0x10]; 5178 5179 u8 reserved_at_20[0x10]; 5180 u8 op_mod[0x10]; 5181 5182 u8 reserved_at_40[0x40]; 5183 }; 5184 5185 struct mlx5_ifc_set_driver_version_out_bits { 5186 u8 status[0x8]; 5187 u8 reserved_0[0x18]; 5188 5189 u8 syndrome[0x20]; 5190 u8 reserved_1[0x40]; 5191 }; 5192 5193 struct mlx5_ifc_set_driver_version_in_bits { 5194 u8 opcode[0x10]; 5195 u8 reserved_0[0x10]; 5196 5197 u8 reserved_1[0x10]; 5198 u8 op_mod[0x10]; 5199 5200 u8 reserved_2[0x40]; 5201 u8 driver_version[64][0x8]; 5202 }; 5203 5204 struct mlx5_ifc_query_hca_vport_pkey_out_bits { 5205 u8 status[0x8]; 5206 u8 reserved_at_8[0x18]; 5207 5208 u8 syndrome[0x20]; 5209 5210 u8 reserved_at_40[0x40]; 5211 5212 struct mlx5_ifc_pkey_bits pkey[]; 5213 }; 5214 5215 struct mlx5_ifc_query_hca_vport_pkey_in_bits { 5216 u8 opcode[0x10]; 5217 u8 reserved_at_10[0x10]; 5218 5219 u8 reserved_at_20[0x10]; 5220 u8 op_mod[0x10]; 5221 5222 u8 other_vport[0x1]; 5223 u8 reserved_at_41[0xb]; 5224 u8 port_num[0x4]; 5225 u8 vport_number[0x10]; 5226 5227 u8 reserved_at_60[0x10]; 5228 u8 pkey_index[0x10]; 5229 }; 5230 5231 enum { 5232 MLX5_HCA_VPORT_SEL_PORT_GUID = 1 << 0, 5233 MLX5_HCA_VPORT_SEL_NODE_GUID = 1 << 1, 5234 MLX5_HCA_VPORT_SEL_STATE_POLICY = 1 << 2, 5235 }; 5236 5237 struct mlx5_ifc_query_hca_vport_gid_out_bits { 5238 u8 status[0x8]; 5239 u8 reserved_at_8[0x18]; 5240 5241 u8 syndrome[0x20]; 5242 5243 u8 reserved_at_40[0x20]; 5244 5245 u8 gids_num[0x10]; 5246 u8 reserved_at_70[0x10]; 5247 5248 struct mlx5_ifc_array128_auto_bits gid[]; 5249 }; 5250 5251 struct mlx5_ifc_query_hca_vport_gid_in_bits { 5252 u8 opcode[0x10]; 5253 u8 reserved_at_10[0x10]; 5254 5255 u8 reserved_at_20[0x10]; 5256 u8 op_mod[0x10]; 5257 5258 u8 other_vport[0x1]; 5259 u8 reserved_at_41[0xb]; 5260 u8 port_num[0x4]; 5261 u8 vport_number[0x10]; 5262 5263 u8 reserved_at_60[0x10]; 5264 u8 gid_index[0x10]; 5265 }; 5266 5267 struct mlx5_ifc_query_hca_vport_context_out_bits { 5268 u8 status[0x8]; 5269 u8 reserved_at_8[0x18]; 5270 5271 u8 syndrome[0x20]; 5272 5273 u8 reserved_at_40[0x40]; 5274 5275 struct mlx5_ifc_hca_vport_context_bits hca_vport_context; 5276 }; 5277 5278 struct mlx5_ifc_query_hca_vport_context_in_bits { 5279 u8 opcode[0x10]; 5280 u8 reserved_at_10[0x10]; 5281 5282 u8 reserved_at_20[0x10]; 5283 u8 op_mod[0x10]; 5284 5285 u8 other_vport[0x1]; 5286 u8 reserved_at_41[0xb]; 5287 u8 port_num[0x4]; 5288 u8 vport_number[0x10]; 5289 5290 u8 reserved_at_60[0x20]; 5291 }; 5292 5293 struct mlx5_ifc_query_hca_cap_out_bits { 5294 u8 status[0x8]; 5295 u8 reserved_at_8[0x18]; 5296 5297 u8 syndrome[0x20]; 5298 5299 u8 reserved_at_40[0x40]; 5300 5301 union mlx5_ifc_hca_cap_union_bits capability; 5302 }; 5303 5304 struct mlx5_ifc_query_hca_cap_in_bits { 5305 u8 opcode[0x10]; 5306 u8 reserved_at_10[0x10]; 5307 5308 u8 reserved_at_20[0x10]; 5309 u8 op_mod[0x10]; 5310 5311 u8 other_function[0x1]; 5312 u8 reserved_at_41[0xf]; 5313 u8 function_id[0x10]; 5314 5315 u8 reserved_at_60[0x20]; 5316 }; 5317 5318 struct mlx5_ifc_other_hca_cap_bits { 5319 u8 roce[0x1]; 5320 u8 reserved_at_1[0x27f]; 5321 }; 5322 5323 struct mlx5_ifc_query_other_hca_cap_out_bits { 5324 u8 status[0x8]; 5325 u8 reserved_at_8[0x18]; 5326 5327 u8 syndrome[0x20]; 5328 5329 u8 reserved_at_40[0x40]; 5330 5331 struct mlx5_ifc_other_hca_cap_bits other_capability; 5332 }; 5333 5334 struct mlx5_ifc_query_other_hca_cap_in_bits { 5335 u8 opcode[0x10]; 5336 u8 reserved_at_10[0x10]; 5337 5338 u8 reserved_at_20[0x10]; 5339 u8 op_mod[0x10]; 5340 5341 u8 reserved_at_40[0x10]; 5342 u8 function_id[0x10]; 5343 5344 u8 reserved_at_60[0x20]; 5345 }; 5346 5347 struct mlx5_ifc_modify_other_hca_cap_out_bits { 5348 u8 status[0x8]; 5349 u8 reserved_at_8[0x18]; 5350 5351 u8 syndrome[0x20]; 5352 5353 u8 reserved_at_40[0x40]; 5354 }; 5355 5356 struct mlx5_ifc_modify_other_hca_cap_in_bits { 5357 u8 opcode[0x10]; 5358 u8 reserved_at_10[0x10]; 5359 5360 u8 reserved_at_20[0x10]; 5361 u8 op_mod[0x10]; 5362 5363 u8 reserved_at_40[0x10]; 5364 u8 function_id[0x10]; 5365 u8 field_select[0x20]; 5366 5367 struct mlx5_ifc_other_hca_cap_bits other_capability; 5368 }; 5369 5370 struct mlx5_ifc_flow_table_context_bits { 5371 u8 reformat_en[0x1]; 5372 u8 decap_en[0x1]; 5373 u8 sw_owner[0x1]; 5374 u8 termination_table[0x1]; 5375 u8 table_miss_action[0x4]; 5376 u8 level[0x8]; 5377 u8 reserved_at_10[0x8]; 5378 u8 log_size[0x8]; 5379 5380 u8 reserved_at_20[0x8]; 5381 u8 table_miss_id[0x18]; 5382 5383 u8 reserved_at_40[0x8]; 5384 u8 lag_master_next_table_id[0x18]; 5385 5386 u8 reserved_at_60[0x60]; 5387 5388 u8 sw_owner_icm_root_1[0x40]; 5389 5390 u8 sw_owner_icm_root_0[0x40]; 5391 5392 }; 5393 5394 struct mlx5_ifc_query_flow_table_out_bits { 5395 u8 status[0x8]; 5396 u8 reserved_at_8[0x18]; 5397 5398 u8 syndrome[0x20]; 5399 5400 u8 reserved_at_40[0x80]; 5401 5402 struct mlx5_ifc_flow_table_context_bits flow_table_context; 5403 }; 5404 5405 struct mlx5_ifc_query_flow_table_in_bits { 5406 u8 opcode[0x10]; 5407 u8 reserved_at_10[0x10]; 5408 5409 u8 reserved_at_20[0x10]; 5410 u8 op_mod[0x10]; 5411 5412 u8 reserved_at_40[0x40]; 5413 5414 u8 table_type[0x8]; 5415 u8 reserved_at_88[0x18]; 5416 5417 u8 reserved_at_a0[0x8]; 5418 u8 table_id[0x18]; 5419 5420 u8 reserved_at_c0[0x140]; 5421 }; 5422 5423 struct mlx5_ifc_query_fte_out_bits { 5424 u8 status[0x8]; 5425 u8 reserved_at_8[0x18]; 5426 5427 u8 syndrome[0x20]; 5428 5429 u8 reserved_at_40[0x1c0]; 5430 5431 struct mlx5_ifc_flow_context_bits flow_context; 5432 }; 5433 5434 struct mlx5_ifc_query_fte_in_bits { 5435 u8 opcode[0x10]; 5436 u8 reserved_at_10[0x10]; 5437 5438 u8 reserved_at_20[0x10]; 5439 u8 op_mod[0x10]; 5440 5441 u8 reserved_at_40[0x40]; 5442 5443 u8 table_type[0x8]; 5444 u8 reserved_at_88[0x18]; 5445 5446 u8 reserved_at_a0[0x8]; 5447 u8 table_id[0x18]; 5448 5449 u8 reserved_at_c0[0x40]; 5450 5451 u8 flow_index[0x20]; 5452 5453 u8 reserved_at_120[0xe0]; 5454 }; 5455 5456 enum { 5457 MLX5_QUERY_FLOW_GROUP_OUT_MATCH_CRITERIA_ENABLE_OUTER_HEADERS = 0x0, 5458 MLX5_QUERY_FLOW_GROUP_OUT_MATCH_CRITERIA_ENABLE_MISC_PARAMETERS = 0x1, 5459 MLX5_QUERY_FLOW_GROUP_OUT_MATCH_CRITERIA_ENABLE_INNER_HEADERS = 0x2, 5460 MLX5_QUERY_FLOW_GROUP_IN_MATCH_CRITERIA_ENABLE_MISC_PARAMETERS_2 = 0x3, 5461 MLX5_QUERY_FLOW_GROUP_IN_MATCH_CRITERIA_ENABLE_MISC_PARAMETERS_3 = 0x4, 5462 }; 5463 5464 struct mlx5_ifc_query_flow_group_out_bits { 5465 u8 status[0x8]; 5466 u8 reserved_at_8[0x18]; 5467 5468 u8 syndrome[0x20]; 5469 5470 u8 reserved_at_40[0xa0]; 5471 5472 u8 start_flow_index[0x20]; 5473 5474 u8 reserved_at_100[0x20]; 5475 5476 u8 end_flow_index[0x20]; 5477 5478 u8 reserved_at_140[0xa0]; 5479 5480 u8 reserved_at_1e0[0x18]; 5481 u8 match_criteria_enable[0x8]; 5482 5483 struct mlx5_ifc_fte_match_param_bits match_criteria; 5484 5485 u8 reserved_at_1200[0xe00]; 5486 }; 5487 5488 struct mlx5_ifc_query_flow_group_in_bits { 5489 u8 opcode[0x10]; 5490 u8 reserved_at_10[0x10]; 5491 5492 u8 reserved_at_20[0x10]; 5493 u8 op_mod[0x10]; 5494 5495 u8 reserved_at_40[0x40]; 5496 5497 u8 table_type[0x8]; 5498 u8 reserved_at_88[0x18]; 5499 5500 u8 reserved_at_a0[0x8]; 5501 u8 table_id[0x18]; 5502 5503 u8 group_id[0x20]; 5504 5505 u8 reserved_at_e0[0x120]; 5506 }; 5507 5508 struct mlx5_ifc_query_flow_counter_out_bits { 5509 u8 status[0x8]; 5510 u8 reserved_at_8[0x18]; 5511 5512 u8 syndrome[0x20]; 5513 5514 u8 reserved_at_40[0x40]; 5515 5516 struct mlx5_ifc_traffic_counter_bits flow_statistics[]; 5517 }; 5518 5519 struct mlx5_ifc_query_flow_counter_in_bits { 5520 u8 opcode[0x10]; 5521 u8 reserved_at_10[0x10]; 5522 5523 u8 reserved_at_20[0x10]; 5524 u8 op_mod[0x10]; 5525 5526 u8 reserved_at_40[0x80]; 5527 5528 u8 clear[0x1]; 5529 u8 reserved_at_c1[0xf]; 5530 u8 num_of_counters[0x10]; 5531 5532 u8 flow_counter_id[0x20]; 5533 }; 5534 5535 struct mlx5_ifc_query_esw_vport_context_out_bits { 5536 u8 status[0x8]; 5537 u8 reserved_at_8[0x18]; 5538 5539 u8 syndrome[0x20]; 5540 5541 u8 reserved_at_40[0x40]; 5542 5543 struct mlx5_ifc_esw_vport_context_bits esw_vport_context; 5544 }; 5545 5546 struct mlx5_ifc_query_esw_vport_context_in_bits { 5547 u8 opcode[0x10]; 5548 u8 reserved_at_10[0x10]; 5549 5550 u8 reserved_at_20[0x10]; 5551 u8 op_mod[0x10]; 5552 5553 u8 other_vport[0x1]; 5554 u8 reserved_at_41[0xf]; 5555 u8 vport_number[0x10]; 5556 5557 u8 reserved_at_60[0x20]; 5558 }; 5559 5560 struct mlx5_ifc_modify_esw_vport_context_out_bits { 5561 u8 status[0x8]; 5562 u8 reserved_at_8[0x18]; 5563 5564 u8 syndrome[0x20]; 5565 5566 u8 reserved_at_40[0x40]; 5567 }; 5568 5569 struct mlx5_ifc_esw_vport_context_fields_select_bits { 5570 u8 reserved_at_0[0x1b]; 5571 u8 fdb_to_vport_reg_c_id[0x1]; 5572 u8 vport_cvlan_insert[0x1]; 5573 u8 vport_svlan_insert[0x1]; 5574 u8 vport_cvlan_strip[0x1]; 5575 u8 vport_svlan_strip[0x1]; 5576 }; 5577 5578 struct mlx5_ifc_modify_esw_vport_context_in_bits { 5579 u8 opcode[0x10]; 5580 u8 reserved_at_10[0x10]; 5581 5582 u8 reserved_at_20[0x10]; 5583 u8 op_mod[0x10]; 5584 5585 u8 other_vport[0x1]; 5586 u8 reserved_at_41[0xf]; 5587 u8 vport_number[0x10]; 5588 5589 struct mlx5_ifc_esw_vport_context_fields_select_bits field_select; 5590 5591 struct mlx5_ifc_esw_vport_context_bits esw_vport_context; 5592 }; 5593 5594 struct mlx5_ifc_query_eq_out_bits { 5595 u8 status[0x8]; 5596 u8 reserved_at_8[0x18]; 5597 5598 u8 syndrome[0x20]; 5599 5600 u8 reserved_at_40[0x40]; 5601 5602 struct mlx5_ifc_eqc_bits eq_context_entry; 5603 5604 u8 reserved_at_280[0x40]; 5605 5606 u8 event_bitmask[0x40]; 5607 5608 u8 reserved_at_300[0x580]; 5609 5610 u8 pas[][0x40]; 5611 }; 5612 5613 struct mlx5_ifc_query_eq_in_bits { 5614 u8 opcode[0x10]; 5615 u8 reserved_at_10[0x10]; 5616 5617 u8 reserved_at_20[0x10]; 5618 u8 op_mod[0x10]; 5619 5620 u8 reserved_at_40[0x18]; 5621 u8 eq_number[0x8]; 5622 5623 u8 reserved_at_60[0x20]; 5624 }; 5625 5626 struct mlx5_ifc_packet_reformat_context_in_bits { 5627 u8 reserved_at_0[0x5]; 5628 u8 reformat_type[0x3]; 5629 u8 reserved_at_8[0xe]; 5630 u8 reformat_data_size[0xa]; 5631 5632 u8 reserved_at_20[0x10]; 5633 u8 reformat_data[2][0x8]; 5634 5635 u8 more_reformat_data[][0x8]; 5636 }; 5637 5638 struct mlx5_ifc_query_packet_reformat_context_out_bits { 5639 u8 status[0x8]; 5640 u8 reserved_at_8[0x18]; 5641 5642 u8 syndrome[0x20]; 5643 5644 u8 reserved_at_40[0xa0]; 5645 5646 struct mlx5_ifc_packet_reformat_context_in_bits packet_reformat_context[]; 5647 }; 5648 5649 struct mlx5_ifc_query_packet_reformat_context_in_bits { 5650 u8 opcode[0x10]; 5651 u8 reserved_at_10[0x10]; 5652 5653 u8 reserved_at_20[0x10]; 5654 u8 op_mod[0x10]; 5655 5656 u8 packet_reformat_id[0x20]; 5657 5658 u8 reserved_at_60[0xa0]; 5659 }; 5660 5661 struct mlx5_ifc_alloc_packet_reformat_context_out_bits { 5662 u8 status[0x8]; 5663 u8 reserved_at_8[0x18]; 5664 5665 u8 syndrome[0x20]; 5666 5667 u8 packet_reformat_id[0x20]; 5668 5669 u8 reserved_at_60[0x20]; 5670 }; 5671 5672 enum mlx5_reformat_ctx_type { 5673 MLX5_REFORMAT_TYPE_L2_TO_VXLAN = 0x0, 5674 MLX5_REFORMAT_TYPE_L2_TO_NVGRE = 0x1, 5675 MLX5_REFORMAT_TYPE_L2_TO_L2_TUNNEL = 0x2, 5676 MLX5_REFORMAT_TYPE_L3_TUNNEL_TO_L2 = 0x3, 5677 MLX5_REFORMAT_TYPE_L2_TO_L3_TUNNEL = 0x4, 5678 }; 5679 5680 struct mlx5_ifc_alloc_packet_reformat_context_in_bits { 5681 u8 opcode[0x10]; 5682 u8 reserved_at_10[0x10]; 5683 5684 u8 reserved_at_20[0x10]; 5685 u8 op_mod[0x10]; 5686 5687 u8 reserved_at_40[0xa0]; 5688 5689 struct mlx5_ifc_packet_reformat_context_in_bits packet_reformat_context; 5690 }; 5691 5692 struct mlx5_ifc_dealloc_packet_reformat_context_out_bits { 5693 u8 status[0x8]; 5694 u8 reserved_at_8[0x18]; 5695 5696 u8 syndrome[0x20]; 5697 5698 u8 reserved_at_40[0x40]; 5699 }; 5700 5701 struct mlx5_ifc_dealloc_packet_reformat_context_in_bits { 5702 u8 opcode[0x10]; 5703 u8 reserved_at_10[0x10]; 5704 5705 u8 reserved_20[0x10]; 5706 u8 op_mod[0x10]; 5707 5708 u8 packet_reformat_id[0x20]; 5709 5710 u8 reserved_60[0x20]; 5711 }; 5712 5713 struct mlx5_ifc_set_action_in_bits { 5714 u8 action_type[0x4]; 5715 u8 field[0xc]; 5716 u8 reserved_at_10[0x3]; 5717 u8 offset[0x5]; 5718 u8 reserved_at_18[0x3]; 5719 u8 length[0x5]; 5720 5721 u8 data[0x20]; 5722 }; 5723 5724 struct mlx5_ifc_add_action_in_bits { 5725 u8 action_type[0x4]; 5726 u8 field[0xc]; 5727 u8 reserved_at_10[0x10]; 5728 5729 u8 data[0x20]; 5730 }; 5731 5732 struct mlx5_ifc_copy_action_in_bits { 5733 u8 action_type[0x4]; 5734 u8 src_field[0xc]; 5735 u8 reserved_at_10[0x3]; 5736 u8 src_offset[0x5]; 5737 u8 reserved_at_18[0x3]; 5738 u8 length[0x5]; 5739 5740 u8 reserved_at_20[0x4]; 5741 u8 dst_field[0xc]; 5742 u8 reserved_at_30[0x3]; 5743 u8 dst_offset[0x5]; 5744 u8 reserved_at_38[0x8]; 5745 }; 5746 5747 union mlx5_ifc_set_add_copy_action_in_auto_bits { 5748 struct mlx5_ifc_set_action_in_bits set_action_in; 5749 struct mlx5_ifc_add_action_in_bits add_action_in; 5750 struct mlx5_ifc_copy_action_in_bits copy_action_in; 5751 u8 reserved_at_0[0x40]; 5752 }; 5753 5754 enum { 5755 MLX5_ACTION_TYPE_SET = 0x1, 5756 MLX5_ACTION_TYPE_ADD = 0x2, 5757 MLX5_ACTION_TYPE_COPY = 0x3, 5758 }; 5759 5760 enum { 5761 MLX5_ACTION_IN_FIELD_OUT_SMAC_47_16 = 0x1, 5762 MLX5_ACTION_IN_FIELD_OUT_SMAC_15_0 = 0x2, 5763 MLX5_ACTION_IN_FIELD_OUT_ETHERTYPE = 0x3, 5764 MLX5_ACTION_IN_FIELD_OUT_DMAC_47_16 = 0x4, 5765 MLX5_ACTION_IN_FIELD_OUT_DMAC_15_0 = 0x5, 5766 MLX5_ACTION_IN_FIELD_OUT_IP_DSCP = 0x6, 5767 MLX5_ACTION_IN_FIELD_OUT_TCP_FLAGS = 0x7, 5768 MLX5_ACTION_IN_FIELD_OUT_TCP_SPORT = 0x8, 5769 MLX5_ACTION_IN_FIELD_OUT_TCP_DPORT = 0x9, 5770 MLX5_ACTION_IN_FIELD_OUT_IP_TTL = 0xa, 5771 MLX5_ACTION_IN_FIELD_OUT_UDP_SPORT = 0xb, 5772 MLX5_ACTION_IN_FIELD_OUT_UDP_DPORT = 0xc, 5773 MLX5_ACTION_IN_FIELD_OUT_SIPV6_127_96 = 0xd, 5774 MLX5_ACTION_IN_FIELD_OUT_SIPV6_95_64 = 0xe, 5775 MLX5_ACTION_IN_FIELD_OUT_SIPV6_63_32 = 0xf, 5776 MLX5_ACTION_IN_FIELD_OUT_SIPV6_31_0 = 0x10, 5777 MLX5_ACTION_IN_FIELD_OUT_DIPV6_127_96 = 0x11, 5778 MLX5_ACTION_IN_FIELD_OUT_DIPV6_95_64 = 0x12, 5779 MLX5_ACTION_IN_FIELD_OUT_DIPV6_63_32 = 0x13, 5780 MLX5_ACTION_IN_FIELD_OUT_DIPV6_31_0 = 0x14, 5781 MLX5_ACTION_IN_FIELD_OUT_SIPV4 = 0x15, 5782 MLX5_ACTION_IN_FIELD_OUT_DIPV4 = 0x16, 5783 MLX5_ACTION_IN_FIELD_OUT_FIRST_VID = 0x17, 5784 MLX5_ACTION_IN_FIELD_OUT_IPV6_HOPLIMIT = 0x47, 5785 MLX5_ACTION_IN_FIELD_METADATA_REG_A = 0x49, 5786 MLX5_ACTION_IN_FIELD_METADATA_REG_B = 0x50, 5787 MLX5_ACTION_IN_FIELD_METADATA_REG_C_0 = 0x51, 5788 MLX5_ACTION_IN_FIELD_METADATA_REG_C_1 = 0x52, 5789 MLX5_ACTION_IN_FIELD_METADATA_REG_C_2 = 0x53, 5790 MLX5_ACTION_IN_FIELD_METADATA_REG_C_3 = 0x54, 5791 MLX5_ACTION_IN_FIELD_METADATA_REG_C_4 = 0x55, 5792 MLX5_ACTION_IN_FIELD_METADATA_REG_C_5 = 0x56, 5793 MLX5_ACTION_IN_FIELD_METADATA_REG_C_6 = 0x57, 5794 MLX5_ACTION_IN_FIELD_METADATA_REG_C_7 = 0x58, 5795 MLX5_ACTION_IN_FIELD_OUT_TCP_SEQ_NUM = 0x59, 5796 MLX5_ACTION_IN_FIELD_OUT_TCP_ACK_NUM = 0x5B, 5797 MLX5_ACTION_IN_FIELD_IPSEC_SYNDROME = 0x5D, 5798 }; 5799 5800 struct mlx5_ifc_alloc_modify_header_context_out_bits { 5801 u8 status[0x8]; 5802 u8 reserved_at_8[0x18]; 5803 5804 u8 syndrome[0x20]; 5805 5806 u8 modify_header_id[0x20]; 5807 5808 u8 reserved_at_60[0x20]; 5809 }; 5810 5811 struct mlx5_ifc_alloc_modify_header_context_in_bits { 5812 u8 opcode[0x10]; 5813 u8 reserved_at_10[0x10]; 5814 5815 u8 reserved_at_20[0x10]; 5816 u8 op_mod[0x10]; 5817 5818 u8 reserved_at_40[0x20]; 5819 5820 u8 table_type[0x8]; 5821 u8 reserved_at_68[0x10]; 5822 u8 num_of_actions[0x8]; 5823 5824 union mlx5_ifc_set_add_copy_action_in_auto_bits actions[0]; 5825 }; 5826 5827 struct mlx5_ifc_dealloc_modify_header_context_out_bits { 5828 u8 status[0x8]; 5829 u8 reserved_at_8[0x18]; 5830 5831 u8 syndrome[0x20]; 5832 5833 u8 reserved_at_40[0x40]; 5834 }; 5835 5836 struct mlx5_ifc_dealloc_modify_header_context_in_bits { 5837 u8 opcode[0x10]; 5838 u8 reserved_at_10[0x10]; 5839 5840 u8 reserved_at_20[0x10]; 5841 u8 op_mod[0x10]; 5842 5843 u8 modify_header_id[0x20]; 5844 5845 u8 reserved_at_60[0x20]; 5846 }; 5847 5848 struct mlx5_ifc_query_dct_out_bits { 5849 u8 status[0x8]; 5850 u8 reserved_at_8[0x18]; 5851 5852 u8 syndrome[0x20]; 5853 5854 u8 reserved_at_40[0x40]; 5855 5856 struct mlx5_ifc_dctc_bits dct_context_entry; 5857 5858 u8 reserved_at_280[0x180]; 5859 }; 5860 5861 struct mlx5_ifc_query_dct_in_bits { 5862 u8 opcode[0x10]; 5863 u8 reserved_at_10[0x10]; 5864 5865 u8 reserved_at_20[0x10]; 5866 u8 op_mod[0x10]; 5867 5868 u8 reserved_at_40[0x8]; 5869 u8 dctn[0x18]; 5870 5871 u8 reserved_at_60[0x20]; 5872 }; 5873 5874 struct mlx5_ifc_query_cq_out_bits { 5875 u8 status[0x8]; 5876 u8 reserved_at_8[0x18]; 5877 5878 u8 syndrome[0x20]; 5879 5880 u8 reserved_at_40[0x40]; 5881 5882 struct mlx5_ifc_cqc_bits cq_context; 5883 5884 u8 reserved_at_280[0x600]; 5885 5886 u8 pas[][0x40]; 5887 }; 5888 5889 struct mlx5_ifc_query_cq_in_bits { 5890 u8 opcode[0x10]; 5891 u8 reserved_at_10[0x10]; 5892 5893 u8 reserved_at_20[0x10]; 5894 u8 op_mod[0x10]; 5895 5896 u8 reserved_at_40[0x8]; 5897 u8 cqn[0x18]; 5898 5899 u8 reserved_at_60[0x20]; 5900 }; 5901 5902 struct mlx5_ifc_query_cong_status_out_bits { 5903 u8 status[0x8]; 5904 u8 reserved_at_8[0x18]; 5905 5906 u8 syndrome[0x20]; 5907 5908 u8 reserved_at_40[0x20]; 5909 5910 u8 enable[0x1]; 5911 u8 tag_enable[0x1]; 5912 u8 reserved_at_62[0x1e]; 5913 }; 5914 5915 struct mlx5_ifc_query_cong_status_in_bits { 5916 u8 opcode[0x10]; 5917 u8 reserved_at_10[0x10]; 5918 5919 u8 reserved_at_20[0x10]; 5920 u8 op_mod[0x10]; 5921 5922 u8 reserved_at_40[0x18]; 5923 u8 priority[0x4]; 5924 u8 cong_protocol[0x4]; 5925 5926 u8 reserved_at_60[0x20]; 5927 }; 5928 5929 struct mlx5_ifc_query_cong_statistics_out_bits { 5930 u8 status[0x8]; 5931 u8 reserved_at_8[0x18]; 5932 5933 u8 syndrome[0x20]; 5934 5935 u8 reserved_at_40[0x40]; 5936 5937 u8 rp_cur_flows[0x20]; 5938 5939 u8 sum_flows[0x20]; 5940 5941 u8 rp_cnp_ignored_high[0x20]; 5942 5943 u8 rp_cnp_ignored_low[0x20]; 5944 5945 u8 rp_cnp_handled_high[0x20]; 5946 5947 u8 rp_cnp_handled_low[0x20]; 5948 5949 u8 reserved_at_140[0x100]; 5950 5951 u8 time_stamp_high[0x20]; 5952 5953 u8 time_stamp_low[0x20]; 5954 5955 u8 accumulators_period[0x20]; 5956 5957 u8 np_ecn_marked_roce_packets_high[0x20]; 5958 5959 u8 np_ecn_marked_roce_packets_low[0x20]; 5960 5961 u8 np_cnp_sent_high[0x20]; 5962 5963 u8 np_cnp_sent_low[0x20]; 5964 5965 u8 reserved_at_320[0x560]; 5966 }; 5967 5968 struct mlx5_ifc_query_cong_statistics_in_bits { 5969 u8 opcode[0x10]; 5970 u8 reserved_at_10[0x10]; 5971 5972 u8 reserved_at_20[0x10]; 5973 u8 op_mod[0x10]; 5974 5975 u8 clear[0x1]; 5976 u8 reserved_at_41[0x1f]; 5977 5978 u8 reserved_at_60[0x20]; 5979 }; 5980 5981 struct mlx5_ifc_query_cong_params_out_bits { 5982 u8 status[0x8]; 5983 u8 reserved_at_8[0x18]; 5984 5985 u8 syndrome[0x20]; 5986 5987 u8 reserved_at_40[0x40]; 5988 5989 union mlx5_ifc_cong_control_roce_ecn_auto_bits congestion_parameters; 5990 }; 5991 5992 struct mlx5_ifc_query_cong_params_in_bits { 5993 u8 opcode[0x10]; 5994 u8 reserved_at_10[0x10]; 5995 5996 u8 reserved_at_20[0x10]; 5997 u8 op_mod[0x10]; 5998 5999 u8 reserved_at_40[0x1c]; 6000 u8 cong_protocol[0x4]; 6001 6002 u8 reserved_at_60[0x20]; 6003 }; 6004 6005 struct mlx5_ifc_query_adapter_out_bits { 6006 u8 status[0x8]; 6007 u8 reserved_at_8[0x18]; 6008 6009 u8 syndrome[0x20]; 6010 6011 u8 reserved_at_40[0x40]; 6012 6013 struct mlx5_ifc_query_adapter_param_block_bits query_adapter_struct; 6014 }; 6015 6016 struct mlx5_ifc_query_adapter_in_bits { 6017 u8 opcode[0x10]; 6018 u8 reserved_at_10[0x10]; 6019 6020 u8 reserved_at_20[0x10]; 6021 u8 op_mod[0x10]; 6022 6023 u8 reserved_at_40[0x40]; 6024 }; 6025 6026 struct mlx5_ifc_qp_2rst_out_bits { 6027 u8 status[0x8]; 6028 u8 reserved_at_8[0x18]; 6029 6030 u8 syndrome[0x20]; 6031 6032 u8 reserved_at_40[0x40]; 6033 }; 6034 6035 struct mlx5_ifc_qp_2rst_in_bits { 6036 u8 opcode[0x10]; 6037 u8 uid[0x10]; 6038 6039 u8 reserved_at_20[0x10]; 6040 u8 op_mod[0x10]; 6041 6042 u8 reserved_at_40[0x8]; 6043 u8 qpn[0x18]; 6044 6045 u8 reserved_at_60[0x20]; 6046 }; 6047 6048 struct mlx5_ifc_qp_2err_out_bits { 6049 u8 status[0x8]; 6050 u8 reserved_at_8[0x18]; 6051 6052 u8 syndrome[0x20]; 6053 6054 u8 reserved_at_40[0x40]; 6055 }; 6056 6057 struct mlx5_ifc_qp_2err_in_bits { 6058 u8 opcode[0x10]; 6059 u8 uid[0x10]; 6060 6061 u8 reserved_at_20[0x10]; 6062 u8 op_mod[0x10]; 6063 6064 u8 reserved_at_40[0x8]; 6065 u8 qpn[0x18]; 6066 6067 u8 reserved_at_60[0x20]; 6068 }; 6069 6070 struct mlx5_ifc_page_fault_resume_out_bits { 6071 u8 status[0x8]; 6072 u8 reserved_at_8[0x18]; 6073 6074 u8 syndrome[0x20]; 6075 6076 u8 reserved_at_40[0x40]; 6077 }; 6078 6079 struct mlx5_ifc_page_fault_resume_in_bits { 6080 u8 opcode[0x10]; 6081 u8 reserved_at_10[0x10]; 6082 6083 u8 reserved_at_20[0x10]; 6084 u8 op_mod[0x10]; 6085 6086 u8 error[0x1]; 6087 u8 reserved_at_41[0x4]; 6088 u8 page_fault_type[0x3]; 6089 u8 wq_number[0x18]; 6090 6091 u8 reserved_at_60[0x8]; 6092 u8 token[0x18]; 6093 }; 6094 6095 struct mlx5_ifc_nop_out_bits { 6096 u8 status[0x8]; 6097 u8 reserved_at_8[0x18]; 6098 6099 u8 syndrome[0x20]; 6100 6101 u8 reserved_at_40[0x40]; 6102 }; 6103 6104 struct mlx5_ifc_nop_in_bits { 6105 u8 opcode[0x10]; 6106 u8 reserved_at_10[0x10]; 6107 6108 u8 reserved_at_20[0x10]; 6109 u8 op_mod[0x10]; 6110 6111 u8 reserved_at_40[0x40]; 6112 }; 6113 6114 struct mlx5_ifc_modify_vport_state_out_bits { 6115 u8 status[0x8]; 6116 u8 reserved_at_8[0x18]; 6117 6118 u8 syndrome[0x20]; 6119 6120 u8 reserved_at_40[0x40]; 6121 }; 6122 6123 struct mlx5_ifc_modify_vport_state_in_bits { 6124 u8 opcode[0x10]; 6125 u8 reserved_at_10[0x10]; 6126 6127 u8 reserved_at_20[0x10]; 6128 u8 op_mod[0x10]; 6129 6130 u8 other_vport[0x1]; 6131 u8 reserved_at_41[0xf]; 6132 u8 vport_number[0x10]; 6133 6134 u8 reserved_at_60[0x18]; 6135 u8 admin_state[0x4]; 6136 u8 reserved_at_7c[0x4]; 6137 }; 6138 6139 struct mlx5_ifc_modify_tis_out_bits { 6140 u8 status[0x8]; 6141 u8 reserved_at_8[0x18]; 6142 6143 u8 syndrome[0x20]; 6144 6145 u8 reserved_at_40[0x40]; 6146 }; 6147 6148 struct mlx5_ifc_modify_tis_bitmask_bits { 6149 u8 reserved_at_0[0x20]; 6150 6151 u8 reserved_at_20[0x1d]; 6152 u8 lag_tx_port_affinity[0x1]; 6153 u8 strict_lag_tx_port_affinity[0x1]; 6154 u8 prio[0x1]; 6155 }; 6156 6157 struct mlx5_ifc_modify_tis_in_bits { 6158 u8 opcode[0x10]; 6159 u8 uid[0x10]; 6160 6161 u8 reserved_at_20[0x10]; 6162 u8 op_mod[0x10]; 6163 6164 u8 reserved_at_40[0x8]; 6165 u8 tisn[0x18]; 6166 6167 u8 reserved_at_60[0x20]; 6168 6169 struct mlx5_ifc_modify_tis_bitmask_bits bitmask; 6170 6171 u8 reserved_at_c0[0x40]; 6172 6173 struct mlx5_ifc_tisc_bits ctx; 6174 }; 6175 6176 struct mlx5_ifc_modify_tir_bitmask_bits { 6177 u8 reserved_at_0[0x20]; 6178 6179 u8 reserved_at_20[0x1b]; 6180 u8 self_lb_en[0x1]; 6181 u8 reserved_at_3c[0x1]; 6182 u8 hash[0x1]; 6183 u8 reserved_at_3e[0x1]; 6184 u8 lro[0x1]; 6185 }; 6186 6187 struct mlx5_ifc_modify_tir_out_bits { 6188 u8 status[0x8]; 6189 u8 reserved_at_8[0x18]; 6190 6191 u8 syndrome[0x20]; 6192 6193 u8 reserved_at_40[0x40]; 6194 }; 6195 6196 struct mlx5_ifc_modify_tir_in_bits { 6197 u8 opcode[0x10]; 6198 u8 uid[0x10]; 6199 6200 u8 reserved_at_20[0x10]; 6201 u8 op_mod[0x10]; 6202 6203 u8 reserved_at_40[0x8]; 6204 u8 tirn[0x18]; 6205 6206 u8 reserved_at_60[0x20]; 6207 6208 struct mlx5_ifc_modify_tir_bitmask_bits bitmask; 6209 6210 u8 reserved_at_c0[0x40]; 6211 6212 struct mlx5_ifc_tirc_bits ctx; 6213 }; 6214 6215 struct mlx5_ifc_modify_sq_out_bits { 6216 u8 status[0x8]; 6217 u8 reserved_at_8[0x18]; 6218 6219 u8 syndrome[0x20]; 6220 6221 u8 reserved_at_40[0x40]; 6222 }; 6223 6224 struct mlx5_ifc_modify_sq_in_bits { 6225 u8 opcode[0x10]; 6226 u8 uid[0x10]; 6227 6228 u8 reserved_at_20[0x10]; 6229 u8 op_mod[0x10]; 6230 6231 u8 sq_state[0x4]; 6232 u8 reserved_at_44[0x4]; 6233 u8 sqn[0x18]; 6234 6235 u8 reserved_at_60[0x20]; 6236 6237 u8 modify_bitmask[0x40]; 6238 6239 u8 reserved_at_c0[0x40]; 6240 6241 struct mlx5_ifc_sqc_bits ctx; 6242 }; 6243 6244 struct mlx5_ifc_modify_scheduling_element_out_bits { 6245 u8 status[0x8]; 6246 u8 reserved_at_8[0x18]; 6247 6248 u8 syndrome[0x20]; 6249 6250 u8 reserved_at_40[0x1c0]; 6251 }; 6252 6253 enum { 6254 MODIFY_SCHEDULING_ELEMENT_IN_MODIFY_BITMASK_BW_SHARE = 0x1, 6255 MODIFY_SCHEDULING_ELEMENT_IN_MODIFY_BITMASK_MAX_AVERAGE_BW = 0x2, 6256 }; 6257 6258 struct mlx5_ifc_modify_scheduling_element_in_bits { 6259 u8 opcode[0x10]; 6260 u8 reserved_at_10[0x10]; 6261 6262 u8 reserved_at_20[0x10]; 6263 u8 op_mod[0x10]; 6264 6265 u8 scheduling_hierarchy[0x8]; 6266 u8 reserved_at_48[0x18]; 6267 6268 u8 scheduling_element_id[0x20]; 6269 6270 u8 reserved_at_80[0x20]; 6271 6272 u8 modify_bitmask[0x20]; 6273 6274 u8 reserved_at_c0[0x40]; 6275 6276 struct mlx5_ifc_scheduling_context_bits scheduling_context; 6277 6278 u8 reserved_at_300[0x100]; 6279 }; 6280 6281 struct mlx5_ifc_modify_rqt_out_bits { 6282 u8 status[0x8]; 6283 u8 reserved_at_8[0x18]; 6284 6285 u8 syndrome[0x20]; 6286 6287 u8 reserved_at_40[0x40]; 6288 }; 6289 6290 struct mlx5_ifc_rqt_bitmask_bits { 6291 u8 reserved_at_0[0x20]; 6292 6293 u8 reserved_at_20[0x1f]; 6294 u8 rqn_list[0x1]; 6295 }; 6296 6297 struct mlx5_ifc_modify_rqt_in_bits { 6298 u8 opcode[0x10]; 6299 u8 uid[0x10]; 6300 6301 u8 reserved_at_20[0x10]; 6302 u8 op_mod[0x10]; 6303 6304 u8 reserved_at_40[0x8]; 6305 u8 rqtn[0x18]; 6306 6307 u8 reserved_at_60[0x20]; 6308 6309 struct mlx5_ifc_rqt_bitmask_bits bitmask; 6310 6311 u8 reserved_at_c0[0x40]; 6312 6313 struct mlx5_ifc_rqtc_bits ctx; 6314 }; 6315 6316 struct mlx5_ifc_modify_rq_out_bits { 6317 u8 status[0x8]; 6318 u8 reserved_at_8[0x18]; 6319 6320 u8 syndrome[0x20]; 6321 6322 u8 reserved_at_40[0x40]; 6323 }; 6324 6325 enum { 6326 MLX5_MODIFY_RQ_IN_MODIFY_BITMASK_VSD = 1ULL << 1, 6327 MLX5_MODIFY_RQ_IN_MODIFY_BITMASK_SCATTER_FCS = 1ULL << 2, 6328 MLX5_MODIFY_RQ_IN_MODIFY_BITMASK_RQ_COUNTER_SET_ID = 1ULL << 3, 6329 }; 6330 6331 struct mlx5_ifc_modify_rq_in_bits { 6332 u8 opcode[0x10]; 6333 u8 uid[0x10]; 6334 6335 u8 reserved_at_20[0x10]; 6336 u8 op_mod[0x10]; 6337 6338 u8 rq_state[0x4]; 6339 u8 reserved_at_44[0x4]; 6340 u8 rqn[0x18]; 6341 6342 u8 reserved_at_60[0x20]; 6343 6344 u8 modify_bitmask[0x40]; 6345 6346 u8 reserved_at_c0[0x40]; 6347 6348 struct mlx5_ifc_rqc_bits ctx; 6349 }; 6350 6351 struct mlx5_ifc_modify_rmp_out_bits { 6352 u8 status[0x8]; 6353 u8 reserved_at_8[0x18]; 6354 6355 u8 syndrome[0x20]; 6356 6357 u8 reserved_at_40[0x40]; 6358 }; 6359 6360 struct mlx5_ifc_rmp_bitmask_bits { 6361 u8 reserved_at_0[0x20]; 6362 6363 u8 reserved_at_20[0x1f]; 6364 u8 lwm[0x1]; 6365 }; 6366 6367 struct mlx5_ifc_modify_rmp_in_bits { 6368 u8 opcode[0x10]; 6369 u8 uid[0x10]; 6370 6371 u8 reserved_at_20[0x10]; 6372 u8 op_mod[0x10]; 6373 6374 u8 rmp_state[0x4]; 6375 u8 reserved_at_44[0x4]; 6376 u8 rmpn[0x18]; 6377 6378 u8 reserved_at_60[0x20]; 6379 6380 struct mlx5_ifc_rmp_bitmask_bits bitmask; 6381 6382 u8 reserved_at_c0[0x40]; 6383 6384 struct mlx5_ifc_rmpc_bits ctx; 6385 }; 6386 6387 struct mlx5_ifc_modify_nic_vport_context_out_bits { 6388 u8 status[0x8]; 6389 u8 reserved_at_8[0x18]; 6390 6391 u8 syndrome[0x20]; 6392 6393 u8 reserved_at_40[0x40]; 6394 }; 6395 6396 struct mlx5_ifc_modify_nic_vport_field_select_bits { 6397 u8 reserved_at_0[0x12]; 6398 u8 affiliation[0x1]; 6399 u8 reserved_at_13[0x1]; 6400 u8 disable_uc_local_lb[0x1]; 6401 u8 disable_mc_local_lb[0x1]; 6402 u8 node_guid[0x1]; 6403 u8 port_guid[0x1]; 6404 u8 min_inline[0x1]; 6405 u8 mtu[0x1]; 6406 u8 change_event[0x1]; 6407 u8 promisc[0x1]; 6408 u8 permanent_address[0x1]; 6409 u8 addresses_list[0x1]; 6410 u8 roce_en[0x1]; 6411 u8 reserved_at_1f[0x1]; 6412 }; 6413 6414 struct mlx5_ifc_modify_nic_vport_context_in_bits { 6415 u8 opcode[0x10]; 6416 u8 reserved_at_10[0x10]; 6417 6418 u8 reserved_at_20[0x10]; 6419 u8 op_mod[0x10]; 6420 6421 u8 other_vport[0x1]; 6422 u8 reserved_at_41[0xf]; 6423 u8 vport_number[0x10]; 6424 6425 struct mlx5_ifc_modify_nic_vport_field_select_bits field_select; 6426 6427 u8 reserved_at_80[0x780]; 6428 6429 struct mlx5_ifc_nic_vport_context_bits nic_vport_context; 6430 }; 6431 6432 struct mlx5_ifc_modify_hca_vport_context_out_bits { 6433 u8 status[0x8]; 6434 u8 reserved_at_8[0x18]; 6435 6436 u8 syndrome[0x20]; 6437 6438 u8 reserved_at_40[0x40]; 6439 }; 6440 6441 struct mlx5_ifc_modify_hca_vport_context_in_bits { 6442 u8 opcode[0x10]; 6443 u8 reserved_at_10[0x10]; 6444 6445 u8 reserved_at_20[0x10]; 6446 u8 op_mod[0x10]; 6447 6448 u8 other_vport[0x1]; 6449 u8 reserved_at_41[0xb]; 6450 u8 port_num[0x4]; 6451 u8 vport_number[0x10]; 6452 6453 u8 reserved_at_60[0x20]; 6454 6455 struct mlx5_ifc_hca_vport_context_bits hca_vport_context; 6456 }; 6457 6458 struct mlx5_ifc_modify_cq_out_bits { 6459 u8 status[0x8]; 6460 u8 reserved_at_8[0x18]; 6461 6462 u8 syndrome[0x20]; 6463 6464 u8 reserved_at_40[0x40]; 6465 }; 6466 6467 enum { 6468 MLX5_MODIFY_CQ_IN_OP_MOD_MODIFY_CQ = 0x0, 6469 MLX5_MODIFY_CQ_IN_OP_MOD_RESIZE_CQ = 0x1, 6470 }; 6471 6472 struct mlx5_ifc_modify_cq_in_bits { 6473 u8 opcode[0x10]; 6474 u8 uid[0x10]; 6475 6476 u8 reserved_at_20[0x10]; 6477 u8 op_mod[0x10]; 6478 6479 u8 reserved_at_40[0x8]; 6480 u8 cqn[0x18]; 6481 6482 union mlx5_ifc_modify_field_select_resize_field_select_auto_bits modify_field_select_resize_field_select; 6483 6484 struct mlx5_ifc_cqc_bits cq_context; 6485 6486 u8 reserved_at_280[0x60]; 6487 6488 u8 cq_umem_valid[0x1]; 6489 u8 reserved_at_2e1[0x1f]; 6490 6491 u8 reserved_at_300[0x580]; 6492 6493 u8 pas[][0x40]; 6494 }; 6495 6496 struct mlx5_ifc_modify_cong_status_out_bits { 6497 u8 status[0x8]; 6498 u8 reserved_at_8[0x18]; 6499 6500 u8 syndrome[0x20]; 6501 6502 u8 reserved_at_40[0x40]; 6503 }; 6504 6505 struct mlx5_ifc_modify_cong_status_in_bits { 6506 u8 opcode[0x10]; 6507 u8 reserved_at_10[0x10]; 6508 6509 u8 reserved_at_20[0x10]; 6510 u8 op_mod[0x10]; 6511 6512 u8 reserved_at_40[0x18]; 6513 u8 priority[0x4]; 6514 u8 cong_protocol[0x4]; 6515 6516 u8 enable[0x1]; 6517 u8 tag_enable[0x1]; 6518 u8 reserved_at_62[0x1e]; 6519 }; 6520 6521 struct mlx5_ifc_modify_cong_params_out_bits { 6522 u8 status[0x8]; 6523 u8 reserved_at_8[0x18]; 6524 6525 u8 syndrome[0x20]; 6526 6527 u8 reserved_at_40[0x40]; 6528 }; 6529 6530 struct mlx5_ifc_modify_cong_params_in_bits { 6531 u8 opcode[0x10]; 6532 u8 reserved_at_10[0x10]; 6533 6534 u8 reserved_at_20[0x10]; 6535 u8 op_mod[0x10]; 6536 6537 u8 reserved_at_40[0x1c]; 6538 u8 cong_protocol[0x4]; 6539 6540 union mlx5_ifc_field_select_802_1_r_roce_auto_bits field_select; 6541 6542 u8 reserved_at_80[0x80]; 6543 6544 union mlx5_ifc_cong_control_roce_ecn_auto_bits congestion_parameters; 6545 }; 6546 6547 struct mlx5_ifc_manage_pages_out_bits { 6548 u8 status[0x8]; 6549 u8 reserved_at_8[0x18]; 6550 6551 u8 syndrome[0x20]; 6552 6553 u8 output_num_entries[0x20]; 6554 6555 u8 reserved_at_60[0x20]; 6556 6557 u8 pas[][0x40]; 6558 }; 6559 6560 enum { 6561 MLX5_MANAGE_PAGES_IN_OP_MOD_ALLOCATION_FAIL = 0x0, 6562 MLX5_MANAGE_PAGES_IN_OP_MOD_ALLOCATION_SUCCESS = 0x1, 6563 MLX5_MANAGE_PAGES_IN_OP_MOD_HCA_RETURN_PAGES = 0x2, 6564 }; 6565 6566 struct mlx5_ifc_manage_pages_in_bits { 6567 u8 opcode[0x10]; 6568 u8 reserved_at_10[0x10]; 6569 6570 u8 reserved_at_20[0x10]; 6571 u8 op_mod[0x10]; 6572 6573 u8 embedded_cpu_function[0x1]; 6574 u8 reserved_at_41[0xf]; 6575 u8 function_id[0x10]; 6576 6577 u8 input_num_entries[0x20]; 6578 6579 u8 pas[][0x40]; 6580 }; 6581 6582 struct mlx5_ifc_mad_ifc_out_bits { 6583 u8 status[0x8]; 6584 u8 reserved_at_8[0x18]; 6585 6586 u8 syndrome[0x20]; 6587 6588 u8 reserved_at_40[0x40]; 6589 6590 u8 response_mad_packet[256][0x8]; 6591 }; 6592 6593 struct mlx5_ifc_mad_ifc_in_bits { 6594 u8 opcode[0x10]; 6595 u8 reserved_at_10[0x10]; 6596 6597 u8 reserved_at_20[0x10]; 6598 u8 op_mod[0x10]; 6599 6600 u8 remote_lid[0x10]; 6601 u8 reserved_at_50[0x8]; 6602 u8 port[0x8]; 6603 6604 u8 reserved_at_60[0x20]; 6605 6606 u8 mad[256][0x8]; 6607 }; 6608 6609 struct mlx5_ifc_init_hca_out_bits { 6610 u8 status[0x8]; 6611 u8 reserved_at_8[0x18]; 6612 6613 u8 syndrome[0x20]; 6614 6615 u8 reserved_at_40[0x40]; 6616 }; 6617 6618 struct mlx5_ifc_init_hca_in_bits { 6619 u8 opcode[0x10]; 6620 u8 reserved_at_10[0x10]; 6621 6622 u8 reserved_at_20[0x10]; 6623 u8 op_mod[0x10]; 6624 6625 u8 reserved_at_40[0x40]; 6626 u8 sw_owner_id[4][0x20]; 6627 }; 6628 6629 struct mlx5_ifc_init2rtr_qp_out_bits { 6630 u8 status[0x8]; 6631 u8 reserved_at_8[0x18]; 6632 6633 u8 syndrome[0x20]; 6634 6635 u8 reserved_at_40[0x20]; 6636 u8 ece[0x20]; 6637 }; 6638 6639 struct mlx5_ifc_init2rtr_qp_in_bits { 6640 u8 opcode[0x10]; 6641 u8 uid[0x10]; 6642 6643 u8 reserved_at_20[0x10]; 6644 u8 op_mod[0x10]; 6645 6646 u8 reserved_at_40[0x8]; 6647 u8 qpn[0x18]; 6648 6649 u8 reserved_at_60[0x20]; 6650 6651 u8 opt_param_mask[0x20]; 6652 6653 u8 ece[0x20]; 6654 6655 struct mlx5_ifc_qpc_bits qpc; 6656 6657 u8 reserved_at_800[0x80]; 6658 }; 6659 6660 struct mlx5_ifc_init2init_qp_out_bits { 6661 u8 status[0x8]; 6662 u8 reserved_at_8[0x18]; 6663 6664 u8 syndrome[0x20]; 6665 6666 u8 reserved_at_40[0x20]; 6667 u8 ece[0x20]; 6668 }; 6669 6670 struct mlx5_ifc_init2init_qp_in_bits { 6671 u8 opcode[0x10]; 6672 u8 uid[0x10]; 6673 6674 u8 reserved_at_20[0x10]; 6675 u8 op_mod[0x10]; 6676 6677 u8 reserved_at_40[0x8]; 6678 u8 qpn[0x18]; 6679 6680 u8 reserved_at_60[0x20]; 6681 6682 u8 opt_param_mask[0x20]; 6683 6684 u8 ece[0x20]; 6685 6686 struct mlx5_ifc_qpc_bits qpc; 6687 6688 u8 reserved_at_800[0x80]; 6689 }; 6690 6691 struct mlx5_ifc_get_dropped_packet_log_out_bits { 6692 u8 status[0x8]; 6693 u8 reserved_at_8[0x18]; 6694 6695 u8 syndrome[0x20]; 6696 6697 u8 reserved_at_40[0x40]; 6698 6699 u8 packet_headers_log[128][0x8]; 6700 6701 u8 packet_syndrome[64][0x8]; 6702 }; 6703 6704 struct mlx5_ifc_get_dropped_packet_log_in_bits { 6705 u8 opcode[0x10]; 6706 u8 reserved_at_10[0x10]; 6707 6708 u8 reserved_at_20[0x10]; 6709 u8 op_mod[0x10]; 6710 6711 u8 reserved_at_40[0x40]; 6712 }; 6713 6714 struct mlx5_ifc_gen_eqe_in_bits { 6715 u8 opcode[0x10]; 6716 u8 reserved_at_10[0x10]; 6717 6718 u8 reserved_at_20[0x10]; 6719 u8 op_mod[0x10]; 6720 6721 u8 reserved_at_40[0x18]; 6722 u8 eq_number[0x8]; 6723 6724 u8 reserved_at_60[0x20]; 6725 6726 u8 eqe[64][0x8]; 6727 }; 6728 6729 struct mlx5_ifc_gen_eq_out_bits { 6730 u8 status[0x8]; 6731 u8 reserved_at_8[0x18]; 6732 6733 u8 syndrome[0x20]; 6734 6735 u8 reserved_at_40[0x40]; 6736 }; 6737 6738 struct mlx5_ifc_enable_hca_out_bits { 6739 u8 status[0x8]; 6740 u8 reserved_at_8[0x18]; 6741 6742 u8 syndrome[0x20]; 6743 6744 u8 reserved_at_40[0x20]; 6745 }; 6746 6747 struct mlx5_ifc_enable_hca_in_bits { 6748 u8 opcode[0x10]; 6749 u8 reserved_at_10[0x10]; 6750 6751 u8 reserved_at_20[0x10]; 6752 u8 op_mod[0x10]; 6753 6754 u8 embedded_cpu_function[0x1]; 6755 u8 reserved_at_41[0xf]; 6756 u8 function_id[0x10]; 6757 6758 u8 reserved_at_60[0x20]; 6759 }; 6760 6761 struct mlx5_ifc_drain_dct_out_bits { 6762 u8 status[0x8]; 6763 u8 reserved_at_8[0x18]; 6764 6765 u8 syndrome[0x20]; 6766 6767 u8 reserved_at_40[0x40]; 6768 }; 6769 6770 struct mlx5_ifc_drain_dct_in_bits { 6771 u8 opcode[0x10]; 6772 u8 uid[0x10]; 6773 6774 u8 reserved_at_20[0x10]; 6775 u8 op_mod[0x10]; 6776 6777 u8 reserved_at_40[0x8]; 6778 u8 dctn[0x18]; 6779 6780 u8 reserved_at_60[0x20]; 6781 }; 6782 6783 struct mlx5_ifc_disable_hca_out_bits { 6784 u8 status[0x8]; 6785 u8 reserved_at_8[0x18]; 6786 6787 u8 syndrome[0x20]; 6788 6789 u8 reserved_at_40[0x20]; 6790 }; 6791 6792 struct mlx5_ifc_disable_hca_in_bits { 6793 u8 opcode[0x10]; 6794 u8 reserved_at_10[0x10]; 6795 6796 u8 reserved_at_20[0x10]; 6797 u8 op_mod[0x10]; 6798 6799 u8 embedded_cpu_function[0x1]; 6800 u8 reserved_at_41[0xf]; 6801 u8 function_id[0x10]; 6802 6803 u8 reserved_at_60[0x20]; 6804 }; 6805 6806 struct mlx5_ifc_detach_from_mcg_out_bits { 6807 u8 status[0x8]; 6808 u8 reserved_at_8[0x18]; 6809 6810 u8 syndrome[0x20]; 6811 6812 u8 reserved_at_40[0x40]; 6813 }; 6814 6815 struct mlx5_ifc_detach_from_mcg_in_bits { 6816 u8 opcode[0x10]; 6817 u8 uid[0x10]; 6818 6819 u8 reserved_at_20[0x10]; 6820 u8 op_mod[0x10]; 6821 6822 u8 reserved_at_40[0x8]; 6823 u8 qpn[0x18]; 6824 6825 u8 reserved_at_60[0x20]; 6826 6827 u8 multicast_gid[16][0x8]; 6828 }; 6829 6830 struct mlx5_ifc_destroy_xrq_out_bits { 6831 u8 status[0x8]; 6832 u8 reserved_at_8[0x18]; 6833 6834 u8 syndrome[0x20]; 6835 6836 u8 reserved_at_40[0x40]; 6837 }; 6838 6839 struct mlx5_ifc_destroy_xrq_in_bits { 6840 u8 opcode[0x10]; 6841 u8 uid[0x10]; 6842 6843 u8 reserved_at_20[0x10]; 6844 u8 op_mod[0x10]; 6845 6846 u8 reserved_at_40[0x8]; 6847 u8 xrqn[0x18]; 6848 6849 u8 reserved_at_60[0x20]; 6850 }; 6851 6852 struct mlx5_ifc_destroy_xrc_srq_out_bits { 6853 u8 status[0x8]; 6854 u8 reserved_at_8[0x18]; 6855 6856 u8 syndrome[0x20]; 6857 6858 u8 reserved_at_40[0x40]; 6859 }; 6860 6861 struct mlx5_ifc_destroy_xrc_srq_in_bits { 6862 u8 opcode[0x10]; 6863 u8 uid[0x10]; 6864 6865 u8 reserved_at_20[0x10]; 6866 u8 op_mod[0x10]; 6867 6868 u8 reserved_at_40[0x8]; 6869 u8 xrc_srqn[0x18]; 6870 6871 u8 reserved_at_60[0x20]; 6872 }; 6873 6874 struct mlx5_ifc_destroy_tis_out_bits { 6875 u8 status[0x8]; 6876 u8 reserved_at_8[0x18]; 6877 6878 u8 syndrome[0x20]; 6879 6880 u8 reserved_at_40[0x40]; 6881 }; 6882 6883 struct mlx5_ifc_destroy_tis_in_bits { 6884 u8 opcode[0x10]; 6885 u8 uid[0x10]; 6886 6887 u8 reserved_at_20[0x10]; 6888 u8 op_mod[0x10]; 6889 6890 u8 reserved_at_40[0x8]; 6891 u8 tisn[0x18]; 6892 6893 u8 reserved_at_60[0x20]; 6894 }; 6895 6896 struct mlx5_ifc_destroy_tir_out_bits { 6897 u8 status[0x8]; 6898 u8 reserved_at_8[0x18]; 6899 6900 u8 syndrome[0x20]; 6901 6902 u8 reserved_at_40[0x40]; 6903 }; 6904 6905 struct mlx5_ifc_destroy_tir_in_bits { 6906 u8 opcode[0x10]; 6907 u8 uid[0x10]; 6908 6909 u8 reserved_at_20[0x10]; 6910 u8 op_mod[0x10]; 6911 6912 u8 reserved_at_40[0x8]; 6913 u8 tirn[0x18]; 6914 6915 u8 reserved_at_60[0x20]; 6916 }; 6917 6918 struct mlx5_ifc_destroy_srq_out_bits { 6919 u8 status[0x8]; 6920 u8 reserved_at_8[0x18]; 6921 6922 u8 syndrome[0x20]; 6923 6924 u8 reserved_at_40[0x40]; 6925 }; 6926 6927 struct mlx5_ifc_destroy_srq_in_bits { 6928 u8 opcode[0x10]; 6929 u8 uid[0x10]; 6930 6931 u8 reserved_at_20[0x10]; 6932 u8 op_mod[0x10]; 6933 6934 u8 reserved_at_40[0x8]; 6935 u8 srqn[0x18]; 6936 6937 u8 reserved_at_60[0x20]; 6938 }; 6939 6940 struct mlx5_ifc_destroy_sq_out_bits { 6941 u8 status[0x8]; 6942 u8 reserved_at_8[0x18]; 6943 6944 u8 syndrome[0x20]; 6945 6946 u8 reserved_at_40[0x40]; 6947 }; 6948 6949 struct mlx5_ifc_destroy_sq_in_bits { 6950 u8 opcode[0x10]; 6951 u8 uid[0x10]; 6952 6953 u8 reserved_at_20[0x10]; 6954 u8 op_mod[0x10]; 6955 6956 u8 reserved_at_40[0x8]; 6957 u8 sqn[0x18]; 6958 6959 u8 reserved_at_60[0x20]; 6960 }; 6961 6962 struct mlx5_ifc_destroy_scheduling_element_out_bits { 6963 u8 status[0x8]; 6964 u8 reserved_at_8[0x18]; 6965 6966 u8 syndrome[0x20]; 6967 6968 u8 reserved_at_40[0x1c0]; 6969 }; 6970 6971 struct mlx5_ifc_destroy_scheduling_element_in_bits { 6972 u8 opcode[0x10]; 6973 u8 reserved_at_10[0x10]; 6974 6975 u8 reserved_at_20[0x10]; 6976 u8 op_mod[0x10]; 6977 6978 u8 scheduling_hierarchy[0x8]; 6979 u8 reserved_at_48[0x18]; 6980 6981 u8 scheduling_element_id[0x20]; 6982 6983 u8 reserved_at_80[0x180]; 6984 }; 6985 6986 struct mlx5_ifc_destroy_rqt_out_bits { 6987 u8 status[0x8]; 6988 u8 reserved_at_8[0x18]; 6989 6990 u8 syndrome[0x20]; 6991 6992 u8 reserved_at_40[0x40]; 6993 }; 6994 6995 struct mlx5_ifc_destroy_rqt_in_bits { 6996 u8 opcode[0x10]; 6997 u8 uid[0x10]; 6998 6999 u8 reserved_at_20[0x10]; 7000 u8 op_mod[0x10]; 7001 7002 u8 reserved_at_40[0x8]; 7003 u8 rqtn[0x18]; 7004 7005 u8 reserved_at_60[0x20]; 7006 }; 7007 7008 struct mlx5_ifc_destroy_rq_out_bits { 7009 u8 status[0x8]; 7010 u8 reserved_at_8[0x18]; 7011 7012 u8 syndrome[0x20]; 7013 7014 u8 reserved_at_40[0x40]; 7015 }; 7016 7017 struct mlx5_ifc_destroy_rq_in_bits { 7018 u8 opcode[0x10]; 7019 u8 uid[0x10]; 7020 7021 u8 reserved_at_20[0x10]; 7022 u8 op_mod[0x10]; 7023 7024 u8 reserved_at_40[0x8]; 7025 u8 rqn[0x18]; 7026 7027 u8 reserved_at_60[0x20]; 7028 }; 7029 7030 struct mlx5_ifc_set_delay_drop_params_in_bits { 7031 u8 opcode[0x10]; 7032 u8 reserved_at_10[0x10]; 7033 7034 u8 reserved_at_20[0x10]; 7035 u8 op_mod[0x10]; 7036 7037 u8 reserved_at_40[0x20]; 7038 7039 u8 reserved_at_60[0x10]; 7040 u8 delay_drop_timeout[0x10]; 7041 }; 7042 7043 struct mlx5_ifc_set_delay_drop_params_out_bits { 7044 u8 status[0x8]; 7045 u8 reserved_at_8[0x18]; 7046 7047 u8 syndrome[0x20]; 7048 7049 u8 reserved_at_40[0x40]; 7050 }; 7051 7052 struct mlx5_ifc_destroy_rmp_out_bits { 7053 u8 status[0x8]; 7054 u8 reserved_at_8[0x18]; 7055 7056 u8 syndrome[0x20]; 7057 7058 u8 reserved_at_40[0x40]; 7059 }; 7060 7061 struct mlx5_ifc_destroy_rmp_in_bits { 7062 u8 opcode[0x10]; 7063 u8 uid[0x10]; 7064 7065 u8 reserved_at_20[0x10]; 7066 u8 op_mod[0x10]; 7067 7068 u8 reserved_at_40[0x8]; 7069 u8 rmpn[0x18]; 7070 7071 u8 reserved_at_60[0x20]; 7072 }; 7073 7074 struct mlx5_ifc_destroy_qp_out_bits { 7075 u8 status[0x8]; 7076 u8 reserved_at_8[0x18]; 7077 7078 u8 syndrome[0x20]; 7079 7080 u8 reserved_at_40[0x40]; 7081 }; 7082 7083 struct mlx5_ifc_destroy_qp_in_bits { 7084 u8 opcode[0x10]; 7085 u8 uid[0x10]; 7086 7087 u8 reserved_at_20[0x10]; 7088 u8 op_mod[0x10]; 7089 7090 u8 reserved_at_40[0x8]; 7091 u8 qpn[0x18]; 7092 7093 u8 reserved_at_60[0x20]; 7094 }; 7095 7096 struct mlx5_ifc_destroy_psv_out_bits { 7097 u8 status[0x8]; 7098 u8 reserved_at_8[0x18]; 7099 7100 u8 syndrome[0x20]; 7101 7102 u8 reserved_at_40[0x40]; 7103 }; 7104 7105 struct mlx5_ifc_destroy_psv_in_bits { 7106 u8 opcode[0x10]; 7107 u8 reserved_at_10[0x10]; 7108 7109 u8 reserved_at_20[0x10]; 7110 u8 op_mod[0x10]; 7111 7112 u8 reserved_at_40[0x8]; 7113 u8 psvn[0x18]; 7114 7115 u8 reserved_at_60[0x20]; 7116 }; 7117 7118 struct mlx5_ifc_destroy_mkey_out_bits { 7119 u8 status[0x8]; 7120 u8 reserved_at_8[0x18]; 7121 7122 u8 syndrome[0x20]; 7123 7124 u8 reserved_at_40[0x40]; 7125 }; 7126 7127 struct mlx5_ifc_destroy_mkey_in_bits { 7128 u8 opcode[0x10]; 7129 u8 uid[0x10]; 7130 7131 u8 reserved_at_20[0x10]; 7132 u8 op_mod[0x10]; 7133 7134 u8 reserved_at_40[0x8]; 7135 u8 mkey_index[0x18]; 7136 7137 u8 reserved_at_60[0x20]; 7138 }; 7139 7140 struct mlx5_ifc_destroy_flow_table_out_bits { 7141 u8 status[0x8]; 7142 u8 reserved_at_8[0x18]; 7143 7144 u8 syndrome[0x20]; 7145 7146 u8 reserved_at_40[0x40]; 7147 }; 7148 7149 struct mlx5_ifc_destroy_flow_table_in_bits { 7150 u8 opcode[0x10]; 7151 u8 reserved_at_10[0x10]; 7152 7153 u8 reserved_at_20[0x10]; 7154 u8 op_mod[0x10]; 7155 7156 u8 other_vport[0x1]; 7157 u8 reserved_at_41[0xf]; 7158 u8 vport_number[0x10]; 7159 7160 u8 reserved_at_60[0x20]; 7161 7162 u8 table_type[0x8]; 7163 u8 reserved_at_88[0x18]; 7164 7165 u8 reserved_at_a0[0x8]; 7166 u8 table_id[0x18]; 7167 7168 u8 reserved_at_c0[0x140]; 7169 }; 7170 7171 struct mlx5_ifc_destroy_flow_group_out_bits { 7172 u8 status[0x8]; 7173 u8 reserved_at_8[0x18]; 7174 7175 u8 syndrome[0x20]; 7176 7177 u8 reserved_at_40[0x40]; 7178 }; 7179 7180 struct mlx5_ifc_destroy_flow_group_in_bits { 7181 u8 opcode[0x10]; 7182 u8 reserved_at_10[0x10]; 7183 7184 u8 reserved_at_20[0x10]; 7185 u8 op_mod[0x10]; 7186 7187 u8 other_vport[0x1]; 7188 u8 reserved_at_41[0xf]; 7189 u8 vport_number[0x10]; 7190 7191 u8 reserved_at_60[0x20]; 7192 7193 u8 table_type[0x8]; 7194 u8 reserved_at_88[0x18]; 7195 7196 u8 reserved_at_a0[0x8]; 7197 u8 table_id[0x18]; 7198 7199 u8 group_id[0x20]; 7200 7201 u8 reserved_at_e0[0x120]; 7202 }; 7203 7204 struct mlx5_ifc_destroy_eq_out_bits { 7205 u8 status[0x8]; 7206 u8 reserved_at_8[0x18]; 7207 7208 u8 syndrome[0x20]; 7209 7210 u8 reserved_at_40[0x40]; 7211 }; 7212 7213 struct mlx5_ifc_destroy_eq_in_bits { 7214 u8 opcode[0x10]; 7215 u8 reserved_at_10[0x10]; 7216 7217 u8 reserved_at_20[0x10]; 7218 u8 op_mod[0x10]; 7219 7220 u8 reserved_at_40[0x18]; 7221 u8 eq_number[0x8]; 7222 7223 u8 reserved_at_60[0x20]; 7224 }; 7225 7226 struct mlx5_ifc_destroy_dct_out_bits { 7227 u8 status[0x8]; 7228 u8 reserved_at_8[0x18]; 7229 7230 u8 syndrome[0x20]; 7231 7232 u8 reserved_at_40[0x40]; 7233 }; 7234 7235 struct mlx5_ifc_destroy_dct_in_bits { 7236 u8 opcode[0x10]; 7237 u8 uid[0x10]; 7238 7239 u8 reserved_at_20[0x10]; 7240 u8 op_mod[0x10]; 7241 7242 u8 reserved_at_40[0x8]; 7243 u8 dctn[0x18]; 7244 7245 u8 reserved_at_60[0x20]; 7246 }; 7247 7248 struct mlx5_ifc_destroy_cq_out_bits { 7249 u8 status[0x8]; 7250 u8 reserved_at_8[0x18]; 7251 7252 u8 syndrome[0x20]; 7253 7254 u8 reserved_at_40[0x40]; 7255 }; 7256 7257 struct mlx5_ifc_destroy_cq_in_bits { 7258 u8 opcode[0x10]; 7259 u8 uid[0x10]; 7260 7261 u8 reserved_at_20[0x10]; 7262 u8 op_mod[0x10]; 7263 7264 u8 reserved_at_40[0x8]; 7265 u8 cqn[0x18]; 7266 7267 u8 reserved_at_60[0x20]; 7268 }; 7269 7270 struct mlx5_ifc_delete_vxlan_udp_dport_out_bits { 7271 u8 status[0x8]; 7272 u8 reserved_at_8[0x18]; 7273 7274 u8 syndrome[0x20]; 7275 7276 u8 reserved_at_40[0x40]; 7277 }; 7278 7279 struct mlx5_ifc_delete_vxlan_udp_dport_in_bits { 7280 u8 opcode[0x10]; 7281 u8 reserved_at_10[0x10]; 7282 7283 u8 reserved_at_20[0x10]; 7284 u8 op_mod[0x10]; 7285 7286 u8 reserved_at_40[0x20]; 7287 7288 u8 reserved_at_60[0x10]; 7289 u8 vxlan_udp_port[0x10]; 7290 }; 7291 7292 struct mlx5_ifc_delete_l2_table_entry_out_bits { 7293 u8 status[0x8]; 7294 u8 reserved_at_8[0x18]; 7295 7296 u8 syndrome[0x20]; 7297 7298 u8 reserved_at_40[0x40]; 7299 }; 7300 7301 struct mlx5_ifc_delete_l2_table_entry_in_bits { 7302 u8 opcode[0x10]; 7303 u8 reserved_at_10[0x10]; 7304 7305 u8 reserved_at_20[0x10]; 7306 u8 op_mod[0x10]; 7307 7308 u8 reserved_at_40[0x60]; 7309 7310 u8 reserved_at_a0[0x8]; 7311 u8 table_index[0x18]; 7312 7313 u8 reserved_at_c0[0x140]; 7314 }; 7315 7316 struct mlx5_ifc_delete_fte_out_bits { 7317 u8 status[0x8]; 7318 u8 reserved_at_8[0x18]; 7319 7320 u8 syndrome[0x20]; 7321 7322 u8 reserved_at_40[0x40]; 7323 }; 7324 7325 struct mlx5_ifc_delete_fte_in_bits { 7326 u8 opcode[0x10]; 7327 u8 reserved_at_10[0x10]; 7328 7329 u8 reserved_at_20[0x10]; 7330 u8 op_mod[0x10]; 7331 7332 u8 other_vport[0x1]; 7333 u8 reserved_at_41[0xf]; 7334 u8 vport_number[0x10]; 7335 7336 u8 reserved_at_60[0x20]; 7337 7338 u8 table_type[0x8]; 7339 u8 reserved_at_88[0x18]; 7340 7341 u8 reserved_at_a0[0x8]; 7342 u8 table_id[0x18]; 7343 7344 u8 reserved_at_c0[0x40]; 7345 7346 u8 flow_index[0x20]; 7347 7348 u8 reserved_at_120[0xe0]; 7349 }; 7350 7351 struct mlx5_ifc_dealloc_xrcd_out_bits { 7352 u8 status[0x8]; 7353 u8 reserved_at_8[0x18]; 7354 7355 u8 syndrome[0x20]; 7356 7357 u8 reserved_at_40[0x40]; 7358 }; 7359 7360 struct mlx5_ifc_dealloc_xrcd_in_bits { 7361 u8 opcode[0x10]; 7362 u8 uid[0x10]; 7363 7364 u8 reserved_at_20[0x10]; 7365 u8 op_mod[0x10]; 7366 7367 u8 reserved_at_40[0x8]; 7368 u8 xrcd[0x18]; 7369 7370 u8 reserved_at_60[0x20]; 7371 }; 7372 7373 struct mlx5_ifc_dealloc_uar_out_bits { 7374 u8 status[0x8]; 7375 u8 reserved_at_8[0x18]; 7376 7377 u8 syndrome[0x20]; 7378 7379 u8 reserved_at_40[0x40]; 7380 }; 7381 7382 struct mlx5_ifc_dealloc_uar_in_bits { 7383 u8 opcode[0x10]; 7384 u8 reserved_at_10[0x10]; 7385 7386 u8 reserved_at_20[0x10]; 7387 u8 op_mod[0x10]; 7388 7389 u8 reserved_at_40[0x8]; 7390 u8 uar[0x18]; 7391 7392 u8 reserved_at_60[0x20]; 7393 }; 7394 7395 struct mlx5_ifc_dealloc_transport_domain_out_bits { 7396 u8 status[0x8]; 7397 u8 reserved_at_8[0x18]; 7398 7399 u8 syndrome[0x20]; 7400 7401 u8 reserved_at_40[0x40]; 7402 }; 7403 7404 struct mlx5_ifc_dealloc_transport_domain_in_bits { 7405 u8 opcode[0x10]; 7406 u8 uid[0x10]; 7407 7408 u8 reserved_at_20[0x10]; 7409 u8 op_mod[0x10]; 7410 7411 u8 reserved_at_40[0x8]; 7412 u8 transport_domain[0x18]; 7413 7414 u8 reserved_at_60[0x20]; 7415 }; 7416 7417 struct mlx5_ifc_dealloc_q_counter_out_bits { 7418 u8 status[0x8]; 7419 u8 reserved_at_8[0x18]; 7420 7421 u8 syndrome[0x20]; 7422 7423 u8 reserved_at_40[0x40]; 7424 }; 7425 7426 struct mlx5_ifc_dealloc_q_counter_in_bits { 7427 u8 opcode[0x10]; 7428 u8 reserved_at_10[0x10]; 7429 7430 u8 reserved_at_20[0x10]; 7431 u8 op_mod[0x10]; 7432 7433 u8 reserved_at_40[0x18]; 7434 u8 counter_set_id[0x8]; 7435 7436 u8 reserved_at_60[0x20]; 7437 }; 7438 7439 struct mlx5_ifc_dealloc_pd_out_bits { 7440 u8 status[0x8]; 7441 u8 reserved_at_8[0x18]; 7442 7443 u8 syndrome[0x20]; 7444 7445 u8 reserved_at_40[0x40]; 7446 }; 7447 7448 struct mlx5_ifc_dealloc_pd_in_bits { 7449 u8 opcode[0x10]; 7450 u8 uid[0x10]; 7451 7452 u8 reserved_at_20[0x10]; 7453 u8 op_mod[0x10]; 7454 7455 u8 reserved_at_40[0x8]; 7456 u8 pd[0x18]; 7457 7458 u8 reserved_at_60[0x20]; 7459 }; 7460 7461 struct mlx5_ifc_dealloc_flow_counter_out_bits { 7462 u8 status[0x8]; 7463 u8 reserved_at_8[0x18]; 7464 7465 u8 syndrome[0x20]; 7466 7467 u8 reserved_at_40[0x40]; 7468 }; 7469 7470 struct mlx5_ifc_dealloc_flow_counter_in_bits { 7471 u8 opcode[0x10]; 7472 u8 reserved_at_10[0x10]; 7473 7474 u8 reserved_at_20[0x10]; 7475 u8 op_mod[0x10]; 7476 7477 u8 flow_counter_id[0x20]; 7478 7479 u8 reserved_at_60[0x20]; 7480 }; 7481 7482 struct mlx5_ifc_create_xrq_out_bits { 7483 u8 status[0x8]; 7484 u8 reserved_at_8[0x18]; 7485 7486 u8 syndrome[0x20]; 7487 7488 u8 reserved_at_40[0x8]; 7489 u8 xrqn[0x18]; 7490 7491 u8 reserved_at_60[0x20]; 7492 }; 7493 7494 struct mlx5_ifc_create_xrq_in_bits { 7495 u8 opcode[0x10]; 7496 u8 uid[0x10]; 7497 7498 u8 reserved_at_20[0x10]; 7499 u8 op_mod[0x10]; 7500 7501 u8 reserved_at_40[0x40]; 7502 7503 struct mlx5_ifc_xrqc_bits xrq_context; 7504 }; 7505 7506 struct mlx5_ifc_create_xrc_srq_out_bits { 7507 u8 status[0x8]; 7508 u8 reserved_at_8[0x18]; 7509 7510 u8 syndrome[0x20]; 7511 7512 u8 reserved_at_40[0x8]; 7513 u8 xrc_srqn[0x18]; 7514 7515 u8 reserved_at_60[0x20]; 7516 }; 7517 7518 struct mlx5_ifc_create_xrc_srq_in_bits { 7519 u8 opcode[0x10]; 7520 u8 uid[0x10]; 7521 7522 u8 reserved_at_20[0x10]; 7523 u8 op_mod[0x10]; 7524 7525 u8 reserved_at_40[0x40]; 7526 7527 struct mlx5_ifc_xrc_srqc_bits xrc_srq_context_entry; 7528 7529 u8 reserved_at_280[0x60]; 7530 7531 u8 xrc_srq_umem_valid[0x1]; 7532 u8 reserved_at_2e1[0x1f]; 7533 7534 u8 reserved_at_300[0x580]; 7535 7536 u8 pas[][0x40]; 7537 }; 7538 7539 struct mlx5_ifc_create_tis_out_bits { 7540 u8 status[0x8]; 7541 u8 reserved_at_8[0x18]; 7542 7543 u8 syndrome[0x20]; 7544 7545 u8 reserved_at_40[0x8]; 7546 u8 tisn[0x18]; 7547 7548 u8 reserved_at_60[0x20]; 7549 }; 7550 7551 struct mlx5_ifc_create_tis_in_bits { 7552 u8 opcode[0x10]; 7553 u8 uid[0x10]; 7554 7555 u8 reserved_at_20[0x10]; 7556 u8 op_mod[0x10]; 7557 7558 u8 reserved_at_40[0xc0]; 7559 7560 struct mlx5_ifc_tisc_bits ctx; 7561 }; 7562 7563 struct mlx5_ifc_create_tir_out_bits { 7564 u8 status[0x8]; 7565 u8 icm_address_63_40[0x18]; 7566 7567 u8 syndrome[0x20]; 7568 7569 u8 icm_address_39_32[0x8]; 7570 u8 tirn[0x18]; 7571 7572 u8 icm_address_31_0[0x20]; 7573 }; 7574 7575 struct mlx5_ifc_create_tir_in_bits { 7576 u8 opcode[0x10]; 7577 u8 uid[0x10]; 7578 7579 u8 reserved_at_20[0x10]; 7580 u8 op_mod[0x10]; 7581 7582 u8 reserved_at_40[0xc0]; 7583 7584 struct mlx5_ifc_tirc_bits ctx; 7585 }; 7586 7587 struct mlx5_ifc_create_srq_out_bits { 7588 u8 status[0x8]; 7589 u8 reserved_at_8[0x18]; 7590 7591 u8 syndrome[0x20]; 7592 7593 u8 reserved_at_40[0x8]; 7594 u8 srqn[0x18]; 7595 7596 u8 reserved_at_60[0x20]; 7597 }; 7598 7599 struct mlx5_ifc_create_srq_in_bits { 7600 u8 opcode[0x10]; 7601 u8 uid[0x10]; 7602 7603 u8 reserved_at_20[0x10]; 7604 u8 op_mod[0x10]; 7605 7606 u8 reserved_at_40[0x40]; 7607 7608 struct mlx5_ifc_srqc_bits srq_context_entry; 7609 7610 u8 reserved_at_280[0x600]; 7611 7612 u8 pas[][0x40]; 7613 }; 7614 7615 struct mlx5_ifc_create_sq_out_bits { 7616 u8 status[0x8]; 7617 u8 reserved_at_8[0x18]; 7618 7619 u8 syndrome[0x20]; 7620 7621 u8 reserved_at_40[0x8]; 7622 u8 sqn[0x18]; 7623 7624 u8 reserved_at_60[0x20]; 7625 }; 7626 7627 struct mlx5_ifc_create_sq_in_bits { 7628 u8 opcode[0x10]; 7629 u8 uid[0x10]; 7630 7631 u8 reserved_at_20[0x10]; 7632 u8 op_mod[0x10]; 7633 7634 u8 reserved_at_40[0xc0]; 7635 7636 struct mlx5_ifc_sqc_bits ctx; 7637 }; 7638 7639 struct mlx5_ifc_create_scheduling_element_out_bits { 7640 u8 status[0x8]; 7641 u8 reserved_at_8[0x18]; 7642 7643 u8 syndrome[0x20]; 7644 7645 u8 reserved_at_40[0x40]; 7646 7647 u8 scheduling_element_id[0x20]; 7648 7649 u8 reserved_at_a0[0x160]; 7650 }; 7651 7652 struct mlx5_ifc_create_scheduling_element_in_bits { 7653 u8 opcode[0x10]; 7654 u8 reserved_at_10[0x10]; 7655 7656 u8 reserved_at_20[0x10]; 7657 u8 op_mod[0x10]; 7658 7659 u8 scheduling_hierarchy[0x8]; 7660 u8 reserved_at_48[0x18]; 7661 7662 u8 reserved_at_60[0xa0]; 7663 7664 struct mlx5_ifc_scheduling_context_bits scheduling_context; 7665 7666 u8 reserved_at_300[0x100]; 7667 }; 7668 7669 struct mlx5_ifc_create_rqt_out_bits { 7670 u8 status[0x8]; 7671 u8 reserved_at_8[0x18]; 7672 7673 u8 syndrome[0x20]; 7674 7675 u8 reserved_at_40[0x8]; 7676 u8 rqtn[0x18]; 7677 7678 u8 reserved_at_60[0x20]; 7679 }; 7680 7681 struct mlx5_ifc_create_rqt_in_bits { 7682 u8 opcode[0x10]; 7683 u8 uid[0x10]; 7684 7685 u8 reserved_at_20[0x10]; 7686 u8 op_mod[0x10]; 7687 7688 u8 reserved_at_40[0xc0]; 7689 7690 struct mlx5_ifc_rqtc_bits rqt_context; 7691 }; 7692 7693 struct mlx5_ifc_create_rq_out_bits { 7694 u8 status[0x8]; 7695 u8 reserved_at_8[0x18]; 7696 7697 u8 syndrome[0x20]; 7698 7699 u8 reserved_at_40[0x8]; 7700 u8 rqn[0x18]; 7701 7702 u8 reserved_at_60[0x20]; 7703 }; 7704 7705 struct mlx5_ifc_create_rq_in_bits { 7706 u8 opcode[0x10]; 7707 u8 uid[0x10]; 7708 7709 u8 reserved_at_20[0x10]; 7710 u8 op_mod[0x10]; 7711 7712 u8 reserved_at_40[0xc0]; 7713 7714 struct mlx5_ifc_rqc_bits ctx; 7715 }; 7716 7717 struct mlx5_ifc_create_rmp_out_bits { 7718 u8 status[0x8]; 7719 u8 reserved_at_8[0x18]; 7720 7721 u8 syndrome[0x20]; 7722 7723 u8 reserved_at_40[0x8]; 7724 u8 rmpn[0x18]; 7725 7726 u8 reserved_at_60[0x20]; 7727 }; 7728 7729 struct mlx5_ifc_create_rmp_in_bits { 7730 u8 opcode[0x10]; 7731 u8 uid[0x10]; 7732 7733 u8 reserved_at_20[0x10]; 7734 u8 op_mod[0x10]; 7735 7736 u8 reserved_at_40[0xc0]; 7737 7738 struct mlx5_ifc_rmpc_bits ctx; 7739 }; 7740 7741 struct mlx5_ifc_create_qp_out_bits { 7742 u8 status[0x8]; 7743 u8 reserved_at_8[0x18]; 7744 7745 u8 syndrome[0x20]; 7746 7747 u8 reserved_at_40[0x8]; 7748 u8 qpn[0x18]; 7749 7750 u8 ece[0x20]; 7751 }; 7752 7753 struct mlx5_ifc_create_qp_in_bits { 7754 u8 opcode[0x10]; 7755 u8 uid[0x10]; 7756 7757 u8 reserved_at_20[0x10]; 7758 u8 op_mod[0x10]; 7759 7760 u8 reserved_at_40[0x8]; 7761 u8 input_qpn[0x18]; 7762 7763 u8 reserved_at_60[0x20]; 7764 u8 opt_param_mask[0x20]; 7765 7766 u8 ece[0x20]; 7767 7768 struct mlx5_ifc_qpc_bits qpc; 7769 7770 u8 reserved_at_800[0x60]; 7771 7772 u8 wq_umem_valid[0x1]; 7773 u8 reserved_at_861[0x1f]; 7774 7775 u8 pas[][0x40]; 7776 }; 7777 7778 struct mlx5_ifc_create_psv_out_bits { 7779 u8 status[0x8]; 7780 u8 reserved_at_8[0x18]; 7781 7782 u8 syndrome[0x20]; 7783 7784 u8 reserved_at_40[0x40]; 7785 7786 u8 reserved_at_80[0x8]; 7787 u8 psv0_index[0x18]; 7788 7789 u8 reserved_at_a0[0x8]; 7790 u8 psv1_index[0x18]; 7791 7792 u8 reserved_at_c0[0x8]; 7793 u8 psv2_index[0x18]; 7794 7795 u8 reserved_at_e0[0x8]; 7796 u8 psv3_index[0x18]; 7797 }; 7798 7799 struct mlx5_ifc_create_psv_in_bits { 7800 u8 opcode[0x10]; 7801 u8 reserved_at_10[0x10]; 7802 7803 u8 reserved_at_20[0x10]; 7804 u8 op_mod[0x10]; 7805 7806 u8 num_psv[0x4]; 7807 u8 reserved_at_44[0x4]; 7808 u8 pd[0x18]; 7809 7810 u8 reserved_at_60[0x20]; 7811 }; 7812 7813 struct mlx5_ifc_create_mkey_out_bits { 7814 u8 status[0x8]; 7815 u8 reserved_at_8[0x18]; 7816 7817 u8 syndrome[0x20]; 7818 7819 u8 reserved_at_40[0x8]; 7820 u8 mkey_index[0x18]; 7821 7822 u8 reserved_at_60[0x20]; 7823 }; 7824 7825 struct mlx5_ifc_create_mkey_in_bits { 7826 u8 opcode[0x10]; 7827 u8 uid[0x10]; 7828 7829 u8 reserved_at_20[0x10]; 7830 u8 op_mod[0x10]; 7831 7832 u8 reserved_at_40[0x20]; 7833 7834 u8 pg_access[0x1]; 7835 u8 mkey_umem_valid[0x1]; 7836 u8 reserved_at_62[0x1e]; 7837 7838 struct mlx5_ifc_mkc_bits memory_key_mkey_entry; 7839 7840 u8 reserved_at_280[0x80]; 7841 7842 u8 translations_octword_actual_size[0x20]; 7843 7844 u8 reserved_at_320[0x560]; 7845 7846 u8 klm_pas_mtt[][0x20]; 7847 }; 7848 7849 enum { 7850 MLX5_FLOW_TABLE_TYPE_NIC_RX = 0x0, 7851 MLX5_FLOW_TABLE_TYPE_NIC_TX = 0x1, 7852 MLX5_FLOW_TABLE_TYPE_ESW_EGRESS_ACL = 0x2, 7853 MLX5_FLOW_TABLE_TYPE_ESW_INGRESS_ACL = 0x3, 7854 MLX5_FLOW_TABLE_TYPE_FDB = 0X4, 7855 MLX5_FLOW_TABLE_TYPE_SNIFFER_RX = 0X5, 7856 MLX5_FLOW_TABLE_TYPE_SNIFFER_TX = 0X6, 7857 }; 7858 7859 struct mlx5_ifc_create_flow_table_out_bits { 7860 u8 status[0x8]; 7861 u8 icm_address_63_40[0x18]; 7862 7863 u8 syndrome[0x20]; 7864 7865 u8 icm_address_39_32[0x8]; 7866 u8 table_id[0x18]; 7867 7868 u8 icm_address_31_0[0x20]; 7869 }; 7870 7871 struct mlx5_ifc_create_flow_table_in_bits { 7872 u8 opcode[0x10]; 7873 u8 reserved_at_10[0x10]; 7874 7875 u8 reserved_at_20[0x10]; 7876 u8 op_mod[0x10]; 7877 7878 u8 other_vport[0x1]; 7879 u8 reserved_at_41[0xf]; 7880 u8 vport_number[0x10]; 7881 7882 u8 reserved_at_60[0x20]; 7883 7884 u8 table_type[0x8]; 7885 u8 reserved_at_88[0x18]; 7886 7887 u8 reserved_at_a0[0x20]; 7888 7889 struct mlx5_ifc_flow_table_context_bits flow_table_context; 7890 }; 7891 7892 struct mlx5_ifc_create_flow_group_out_bits { 7893 u8 status[0x8]; 7894 u8 reserved_at_8[0x18]; 7895 7896 u8 syndrome[0x20]; 7897 7898 u8 reserved_at_40[0x8]; 7899 u8 group_id[0x18]; 7900 7901 u8 reserved_at_60[0x20]; 7902 }; 7903 7904 enum { 7905 MLX5_CREATE_FLOW_GROUP_IN_MATCH_CRITERIA_ENABLE_OUTER_HEADERS = 0x0, 7906 MLX5_CREATE_FLOW_GROUP_IN_MATCH_CRITERIA_ENABLE_MISC_PARAMETERS = 0x1, 7907 MLX5_CREATE_FLOW_GROUP_IN_MATCH_CRITERIA_ENABLE_INNER_HEADERS = 0x2, 7908 MLX5_CREATE_FLOW_GROUP_IN_MATCH_CRITERIA_ENABLE_MISC_PARAMETERS_2 = 0x3, 7909 }; 7910 7911 struct mlx5_ifc_create_flow_group_in_bits { 7912 u8 opcode[0x10]; 7913 u8 reserved_at_10[0x10]; 7914 7915 u8 reserved_at_20[0x10]; 7916 u8 op_mod[0x10]; 7917 7918 u8 other_vport[0x1]; 7919 u8 reserved_at_41[0xf]; 7920 u8 vport_number[0x10]; 7921 7922 u8 reserved_at_60[0x20]; 7923 7924 u8 table_type[0x8]; 7925 u8 reserved_at_88[0x18]; 7926 7927 u8 reserved_at_a0[0x8]; 7928 u8 table_id[0x18]; 7929 7930 u8 source_eswitch_owner_vhca_id_valid[0x1]; 7931 7932 u8 reserved_at_c1[0x1f]; 7933 7934 u8 start_flow_index[0x20]; 7935 7936 u8 reserved_at_100[0x20]; 7937 7938 u8 end_flow_index[0x20]; 7939 7940 u8 reserved_at_140[0xa0]; 7941 7942 u8 reserved_at_1e0[0x18]; 7943 u8 match_criteria_enable[0x8]; 7944 7945 struct mlx5_ifc_fte_match_param_bits match_criteria; 7946 7947 u8 reserved_at_1200[0xe00]; 7948 }; 7949 7950 struct mlx5_ifc_create_eq_out_bits { 7951 u8 status[0x8]; 7952 u8 reserved_at_8[0x18]; 7953 7954 u8 syndrome[0x20]; 7955 7956 u8 reserved_at_40[0x18]; 7957 u8 eq_number[0x8]; 7958 7959 u8 reserved_at_60[0x20]; 7960 }; 7961 7962 struct mlx5_ifc_create_eq_in_bits { 7963 u8 opcode[0x10]; 7964 u8 uid[0x10]; 7965 7966 u8 reserved_at_20[0x10]; 7967 u8 op_mod[0x10]; 7968 7969 u8 reserved_at_40[0x40]; 7970 7971 struct mlx5_ifc_eqc_bits eq_context_entry; 7972 7973 u8 reserved_at_280[0x40]; 7974 7975 u8 event_bitmask[4][0x40]; 7976 7977 u8 reserved_at_3c0[0x4c0]; 7978 7979 u8 pas[][0x40]; 7980 }; 7981 7982 struct mlx5_ifc_create_dct_out_bits { 7983 u8 status[0x8]; 7984 u8 reserved_at_8[0x18]; 7985 7986 u8 syndrome[0x20]; 7987 7988 u8 reserved_at_40[0x8]; 7989 u8 dctn[0x18]; 7990 7991 u8 ece[0x20]; 7992 }; 7993 7994 struct mlx5_ifc_create_dct_in_bits { 7995 u8 opcode[0x10]; 7996 u8 uid[0x10]; 7997 7998 u8 reserved_at_20[0x10]; 7999 u8 op_mod[0x10]; 8000 8001 u8 reserved_at_40[0x40]; 8002 8003 struct mlx5_ifc_dctc_bits dct_context_entry; 8004 8005 u8 reserved_at_280[0x180]; 8006 }; 8007 8008 struct mlx5_ifc_create_cq_out_bits { 8009 u8 status[0x8]; 8010 u8 reserved_at_8[0x18]; 8011 8012 u8 syndrome[0x20]; 8013 8014 u8 reserved_at_40[0x8]; 8015 u8 cqn[0x18]; 8016 8017 u8 reserved_at_60[0x20]; 8018 }; 8019 8020 struct mlx5_ifc_create_cq_in_bits { 8021 u8 opcode[0x10]; 8022 u8 uid[0x10]; 8023 8024 u8 reserved_at_20[0x10]; 8025 u8 op_mod[0x10]; 8026 8027 u8 reserved_at_40[0x40]; 8028 8029 struct mlx5_ifc_cqc_bits cq_context; 8030 8031 u8 reserved_at_280[0x60]; 8032 8033 u8 cq_umem_valid[0x1]; 8034 u8 reserved_at_2e1[0x59f]; 8035 8036 u8 pas[][0x40]; 8037 }; 8038 8039 struct mlx5_ifc_config_int_moderation_out_bits { 8040 u8 status[0x8]; 8041 u8 reserved_at_8[0x18]; 8042 8043 u8 syndrome[0x20]; 8044 8045 u8 reserved_at_40[0x4]; 8046 u8 min_delay[0xc]; 8047 u8 int_vector[0x10]; 8048 8049 u8 reserved_at_60[0x20]; 8050 }; 8051 8052 enum { 8053 MLX5_CONFIG_INT_MODERATION_IN_OP_MOD_WRITE = 0x0, 8054 MLX5_CONFIG_INT_MODERATION_IN_OP_MOD_READ = 0x1, 8055 }; 8056 8057 struct mlx5_ifc_config_int_moderation_in_bits { 8058 u8 opcode[0x10]; 8059 u8 reserved_at_10[0x10]; 8060 8061 u8 reserved_at_20[0x10]; 8062 u8 op_mod[0x10]; 8063 8064 u8 reserved_at_40[0x4]; 8065 u8 min_delay[0xc]; 8066 u8 int_vector[0x10]; 8067 8068 u8 reserved_at_60[0x20]; 8069 }; 8070 8071 struct mlx5_ifc_attach_to_mcg_out_bits { 8072 u8 status[0x8]; 8073 u8 reserved_at_8[0x18]; 8074 8075 u8 syndrome[0x20]; 8076 8077 u8 reserved_at_40[0x40]; 8078 }; 8079 8080 struct mlx5_ifc_attach_to_mcg_in_bits { 8081 u8 opcode[0x10]; 8082 u8 uid[0x10]; 8083 8084 u8 reserved_at_20[0x10]; 8085 u8 op_mod[0x10]; 8086 8087 u8 reserved_at_40[0x8]; 8088 u8 qpn[0x18]; 8089 8090 u8 reserved_at_60[0x20]; 8091 8092 u8 multicast_gid[16][0x8]; 8093 }; 8094 8095 struct mlx5_ifc_arm_xrq_out_bits { 8096 u8 status[0x8]; 8097 u8 reserved_at_8[0x18]; 8098 8099 u8 syndrome[0x20]; 8100 8101 u8 reserved_at_40[0x40]; 8102 }; 8103 8104 struct mlx5_ifc_arm_xrq_in_bits { 8105 u8 opcode[0x10]; 8106 u8 reserved_at_10[0x10]; 8107 8108 u8 reserved_at_20[0x10]; 8109 u8 op_mod[0x10]; 8110 8111 u8 reserved_at_40[0x8]; 8112 u8 xrqn[0x18]; 8113 8114 u8 reserved_at_60[0x10]; 8115 u8 lwm[0x10]; 8116 }; 8117 8118 struct mlx5_ifc_arm_xrc_srq_out_bits { 8119 u8 status[0x8]; 8120 u8 reserved_at_8[0x18]; 8121 8122 u8 syndrome[0x20]; 8123 8124 u8 reserved_at_40[0x40]; 8125 }; 8126 8127 enum { 8128 MLX5_ARM_XRC_SRQ_IN_OP_MOD_XRC_SRQ = 0x1, 8129 }; 8130 8131 struct mlx5_ifc_arm_xrc_srq_in_bits { 8132 u8 opcode[0x10]; 8133 u8 uid[0x10]; 8134 8135 u8 reserved_at_20[0x10]; 8136 u8 op_mod[0x10]; 8137 8138 u8 reserved_at_40[0x8]; 8139 u8 xrc_srqn[0x18]; 8140 8141 u8 reserved_at_60[0x10]; 8142 u8 lwm[0x10]; 8143 }; 8144 8145 struct mlx5_ifc_arm_rq_out_bits { 8146 u8 status[0x8]; 8147 u8 reserved_at_8[0x18]; 8148 8149 u8 syndrome[0x20]; 8150 8151 u8 reserved_at_40[0x40]; 8152 }; 8153 8154 enum { 8155 MLX5_ARM_RQ_IN_OP_MOD_SRQ = 0x1, 8156 MLX5_ARM_RQ_IN_OP_MOD_XRQ = 0x2, 8157 }; 8158 8159 struct mlx5_ifc_arm_rq_in_bits { 8160 u8 opcode[0x10]; 8161 u8 uid[0x10]; 8162 8163 u8 reserved_at_20[0x10]; 8164 u8 op_mod[0x10]; 8165 8166 u8 reserved_at_40[0x8]; 8167 u8 srq_number[0x18]; 8168 8169 u8 reserved_at_60[0x10]; 8170 u8 lwm[0x10]; 8171 }; 8172 8173 struct mlx5_ifc_arm_dct_out_bits { 8174 u8 status[0x8]; 8175 u8 reserved_at_8[0x18]; 8176 8177 u8 syndrome[0x20]; 8178 8179 u8 reserved_at_40[0x40]; 8180 }; 8181 8182 struct mlx5_ifc_arm_dct_in_bits { 8183 u8 opcode[0x10]; 8184 u8 reserved_at_10[0x10]; 8185 8186 u8 reserved_at_20[0x10]; 8187 u8 op_mod[0x10]; 8188 8189 u8 reserved_at_40[0x8]; 8190 u8 dct_number[0x18]; 8191 8192 u8 reserved_at_60[0x20]; 8193 }; 8194 8195 struct mlx5_ifc_alloc_xrcd_out_bits { 8196 u8 status[0x8]; 8197 u8 reserved_at_8[0x18]; 8198 8199 u8 syndrome[0x20]; 8200 8201 u8 reserved_at_40[0x8]; 8202 u8 xrcd[0x18]; 8203 8204 u8 reserved_at_60[0x20]; 8205 }; 8206 8207 struct mlx5_ifc_alloc_xrcd_in_bits { 8208 u8 opcode[0x10]; 8209 u8 uid[0x10]; 8210 8211 u8 reserved_at_20[0x10]; 8212 u8 op_mod[0x10]; 8213 8214 u8 reserved_at_40[0x40]; 8215 }; 8216 8217 struct mlx5_ifc_alloc_uar_out_bits { 8218 u8 status[0x8]; 8219 u8 reserved_at_8[0x18]; 8220 8221 u8 syndrome[0x20]; 8222 8223 u8 reserved_at_40[0x8]; 8224 u8 uar[0x18]; 8225 8226 u8 reserved_at_60[0x20]; 8227 }; 8228 8229 struct mlx5_ifc_alloc_uar_in_bits { 8230 u8 opcode[0x10]; 8231 u8 reserved_at_10[0x10]; 8232 8233 u8 reserved_at_20[0x10]; 8234 u8 op_mod[0x10]; 8235 8236 u8 reserved_at_40[0x40]; 8237 }; 8238 8239 struct mlx5_ifc_alloc_transport_domain_out_bits { 8240 u8 status[0x8]; 8241 u8 reserved_at_8[0x18]; 8242 8243 u8 syndrome[0x20]; 8244 8245 u8 reserved_at_40[0x8]; 8246 u8 transport_domain[0x18]; 8247 8248 u8 reserved_at_60[0x20]; 8249 }; 8250 8251 struct mlx5_ifc_alloc_transport_domain_in_bits { 8252 u8 opcode[0x10]; 8253 u8 uid[0x10]; 8254 8255 u8 reserved_at_20[0x10]; 8256 u8 op_mod[0x10]; 8257 8258 u8 reserved_at_40[0x40]; 8259 }; 8260 8261 struct mlx5_ifc_alloc_q_counter_out_bits { 8262 u8 status[0x8]; 8263 u8 reserved_at_8[0x18]; 8264 8265 u8 syndrome[0x20]; 8266 8267 u8 reserved_at_40[0x18]; 8268 u8 counter_set_id[0x8]; 8269 8270 u8 reserved_at_60[0x20]; 8271 }; 8272 8273 struct mlx5_ifc_alloc_q_counter_in_bits { 8274 u8 opcode[0x10]; 8275 u8 uid[0x10]; 8276 8277 u8 reserved_at_20[0x10]; 8278 u8 op_mod[0x10]; 8279 8280 u8 reserved_at_40[0x40]; 8281 }; 8282 8283 struct mlx5_ifc_alloc_pd_out_bits { 8284 u8 status[0x8]; 8285 u8 reserved_at_8[0x18]; 8286 8287 u8 syndrome[0x20]; 8288 8289 u8 reserved_at_40[0x8]; 8290 u8 pd[0x18]; 8291 8292 u8 reserved_at_60[0x20]; 8293 }; 8294 8295 struct mlx5_ifc_alloc_pd_in_bits { 8296 u8 opcode[0x10]; 8297 u8 uid[0x10]; 8298 8299 u8 reserved_at_20[0x10]; 8300 u8 op_mod[0x10]; 8301 8302 u8 reserved_at_40[0x40]; 8303 }; 8304 8305 struct mlx5_ifc_alloc_flow_counter_out_bits { 8306 u8 status[0x8]; 8307 u8 reserved_at_8[0x18]; 8308 8309 u8 syndrome[0x20]; 8310 8311 u8 flow_counter_id[0x20]; 8312 8313 u8 reserved_at_60[0x20]; 8314 }; 8315 8316 struct mlx5_ifc_alloc_flow_counter_in_bits { 8317 u8 opcode[0x10]; 8318 u8 reserved_at_10[0x10]; 8319 8320 u8 reserved_at_20[0x10]; 8321 u8 op_mod[0x10]; 8322 8323 u8 reserved_at_40[0x38]; 8324 u8 flow_counter_bulk[0x8]; 8325 }; 8326 8327 struct mlx5_ifc_add_vxlan_udp_dport_out_bits { 8328 u8 status[0x8]; 8329 u8 reserved_at_8[0x18]; 8330 8331 u8 syndrome[0x20]; 8332 8333 u8 reserved_at_40[0x40]; 8334 }; 8335 8336 struct mlx5_ifc_add_vxlan_udp_dport_in_bits { 8337 u8 opcode[0x10]; 8338 u8 reserved_at_10[0x10]; 8339 8340 u8 reserved_at_20[0x10]; 8341 u8 op_mod[0x10]; 8342 8343 u8 reserved_at_40[0x20]; 8344 8345 u8 reserved_at_60[0x10]; 8346 u8 vxlan_udp_port[0x10]; 8347 }; 8348 8349 struct mlx5_ifc_set_pp_rate_limit_out_bits { 8350 u8 status[0x8]; 8351 u8 reserved_at_8[0x18]; 8352 8353 u8 syndrome[0x20]; 8354 8355 u8 reserved_at_40[0x40]; 8356 }; 8357 8358 struct mlx5_ifc_set_pp_rate_limit_context_bits { 8359 u8 rate_limit[0x20]; 8360 8361 u8 burst_upper_bound[0x20]; 8362 8363 u8 reserved_at_40[0x10]; 8364 u8 typical_packet_size[0x10]; 8365 8366 u8 reserved_at_60[0x120]; 8367 }; 8368 8369 struct mlx5_ifc_set_pp_rate_limit_in_bits { 8370 u8 opcode[0x10]; 8371 u8 uid[0x10]; 8372 8373 u8 reserved_at_20[0x10]; 8374 u8 op_mod[0x10]; 8375 8376 u8 reserved_at_40[0x10]; 8377 u8 rate_limit_index[0x10]; 8378 8379 u8 reserved_at_60[0x20]; 8380 8381 struct mlx5_ifc_set_pp_rate_limit_context_bits ctx; 8382 }; 8383 8384 struct mlx5_ifc_access_register_out_bits { 8385 u8 status[0x8]; 8386 u8 reserved_at_8[0x18]; 8387 8388 u8 syndrome[0x20]; 8389 8390 u8 reserved_at_40[0x40]; 8391 8392 u8 register_data[][0x20]; 8393 }; 8394 8395 enum { 8396 MLX5_ACCESS_REGISTER_IN_OP_MOD_WRITE = 0x0, 8397 MLX5_ACCESS_REGISTER_IN_OP_MOD_READ = 0x1, 8398 }; 8399 8400 struct mlx5_ifc_access_register_in_bits { 8401 u8 opcode[0x10]; 8402 u8 reserved_at_10[0x10]; 8403 8404 u8 reserved_at_20[0x10]; 8405 u8 op_mod[0x10]; 8406 8407 u8 reserved_at_40[0x10]; 8408 u8 register_id[0x10]; 8409 8410 u8 argument[0x20]; 8411 8412 u8 register_data[][0x20]; 8413 }; 8414 8415 struct mlx5_ifc_sltp_reg_bits { 8416 u8 status[0x4]; 8417 u8 version[0x4]; 8418 u8 local_port[0x8]; 8419 u8 pnat[0x2]; 8420 u8 reserved_at_12[0x2]; 8421 u8 lane[0x4]; 8422 u8 reserved_at_18[0x8]; 8423 8424 u8 reserved_at_20[0x20]; 8425 8426 u8 reserved_at_40[0x7]; 8427 u8 polarity[0x1]; 8428 u8 ob_tap0[0x8]; 8429 u8 ob_tap1[0x8]; 8430 u8 ob_tap2[0x8]; 8431 8432 u8 reserved_at_60[0xc]; 8433 u8 ob_preemp_mode[0x4]; 8434 u8 ob_reg[0x8]; 8435 u8 ob_bias[0x8]; 8436 8437 u8 reserved_at_80[0x20]; 8438 }; 8439 8440 struct mlx5_ifc_slrg_reg_bits { 8441 u8 status[0x4]; 8442 u8 version[0x4]; 8443 u8 local_port[0x8]; 8444 u8 pnat[0x2]; 8445 u8 reserved_at_12[0x2]; 8446 u8 lane[0x4]; 8447 u8 reserved_at_18[0x8]; 8448 8449 u8 time_to_link_up[0x10]; 8450 u8 reserved_at_30[0xc]; 8451 u8 grade_lane_speed[0x4]; 8452 8453 u8 grade_version[0x8]; 8454 u8 grade[0x18]; 8455 8456 u8 reserved_at_60[0x4]; 8457 u8 height_grade_type[0x4]; 8458 u8 height_grade[0x18]; 8459 8460 u8 height_dz[0x10]; 8461 u8 height_dv[0x10]; 8462 8463 u8 reserved_at_a0[0x10]; 8464 u8 height_sigma[0x10]; 8465 8466 u8 reserved_at_c0[0x20]; 8467 8468 u8 reserved_at_e0[0x4]; 8469 u8 phase_grade_type[0x4]; 8470 u8 phase_grade[0x18]; 8471 8472 u8 reserved_at_100[0x8]; 8473 u8 phase_eo_pos[0x8]; 8474 u8 reserved_at_110[0x8]; 8475 u8 phase_eo_neg[0x8]; 8476 8477 u8 ffe_set_tested[0x10]; 8478 u8 test_errors_per_lane[0x10]; 8479 }; 8480 8481 struct mlx5_ifc_pvlc_reg_bits { 8482 u8 reserved_at_0[0x8]; 8483 u8 local_port[0x8]; 8484 u8 reserved_at_10[0x10]; 8485 8486 u8 reserved_at_20[0x1c]; 8487 u8 vl_hw_cap[0x4]; 8488 8489 u8 reserved_at_40[0x1c]; 8490 u8 vl_admin[0x4]; 8491 8492 u8 reserved_at_60[0x1c]; 8493 u8 vl_operational[0x4]; 8494 }; 8495 8496 struct mlx5_ifc_pude_reg_bits { 8497 u8 swid[0x8]; 8498 u8 local_port[0x8]; 8499 u8 reserved_at_10[0x4]; 8500 u8 admin_status[0x4]; 8501 u8 reserved_at_18[0x4]; 8502 u8 oper_status[0x4]; 8503 8504 u8 reserved_at_20[0x60]; 8505 }; 8506 8507 struct mlx5_ifc_ptys_reg_bits { 8508 u8 reserved_at_0[0x1]; 8509 u8 an_disable_admin[0x1]; 8510 u8 an_disable_cap[0x1]; 8511 u8 reserved_at_3[0x5]; 8512 u8 local_port[0x8]; 8513 u8 reserved_at_10[0xd]; 8514 u8 proto_mask[0x3]; 8515 8516 u8 an_status[0x4]; 8517 u8 reserved_at_24[0xc]; 8518 u8 data_rate_oper[0x10]; 8519 8520 u8 ext_eth_proto_capability[0x20]; 8521 8522 u8 eth_proto_capability[0x20]; 8523 8524 u8 ib_link_width_capability[0x10]; 8525 u8 ib_proto_capability[0x10]; 8526 8527 u8 ext_eth_proto_admin[0x20]; 8528 8529 u8 eth_proto_admin[0x20]; 8530 8531 u8 ib_link_width_admin[0x10]; 8532 u8 ib_proto_admin[0x10]; 8533 8534 u8 ext_eth_proto_oper[0x20]; 8535 8536 u8 eth_proto_oper[0x20]; 8537 8538 u8 ib_link_width_oper[0x10]; 8539 u8 ib_proto_oper[0x10]; 8540 8541 u8 reserved_at_160[0x1c]; 8542 u8 connector_type[0x4]; 8543 8544 u8 eth_proto_lp_advertise[0x20]; 8545 8546 u8 reserved_at_1a0[0x60]; 8547 }; 8548 8549 struct mlx5_ifc_mlcr_reg_bits { 8550 u8 reserved_at_0[0x8]; 8551 u8 local_port[0x8]; 8552 u8 reserved_at_10[0x20]; 8553 8554 u8 beacon_duration[0x10]; 8555 u8 reserved_at_40[0x10]; 8556 8557 u8 beacon_remain[0x10]; 8558 }; 8559 8560 struct mlx5_ifc_ptas_reg_bits { 8561 u8 reserved_at_0[0x20]; 8562 8563 u8 algorithm_options[0x10]; 8564 u8 reserved_at_30[0x4]; 8565 u8 repetitions_mode[0x4]; 8566 u8 num_of_repetitions[0x8]; 8567 8568 u8 grade_version[0x8]; 8569 u8 height_grade_type[0x4]; 8570 u8 phase_grade_type[0x4]; 8571 u8 height_grade_weight[0x8]; 8572 u8 phase_grade_weight[0x8]; 8573 8574 u8 gisim_measure_bits[0x10]; 8575 u8 adaptive_tap_measure_bits[0x10]; 8576 8577 u8 ber_bath_high_error_threshold[0x10]; 8578 u8 ber_bath_mid_error_threshold[0x10]; 8579 8580 u8 ber_bath_low_error_threshold[0x10]; 8581 u8 one_ratio_high_threshold[0x10]; 8582 8583 u8 one_ratio_high_mid_threshold[0x10]; 8584 u8 one_ratio_low_mid_threshold[0x10]; 8585 8586 u8 one_ratio_low_threshold[0x10]; 8587 u8 ndeo_error_threshold[0x10]; 8588 8589 u8 mixer_offset_step_size[0x10]; 8590 u8 reserved_at_110[0x8]; 8591 u8 mix90_phase_for_voltage_bath[0x8]; 8592 8593 u8 mixer_offset_start[0x10]; 8594 u8 mixer_offset_end[0x10]; 8595 8596 u8 reserved_at_140[0x15]; 8597 u8 ber_test_time[0xb]; 8598 }; 8599 8600 struct mlx5_ifc_pspa_reg_bits { 8601 u8 swid[0x8]; 8602 u8 local_port[0x8]; 8603 u8 sub_port[0x8]; 8604 u8 reserved_at_18[0x8]; 8605 8606 u8 reserved_at_20[0x20]; 8607 }; 8608 8609 struct mlx5_ifc_pqdr_reg_bits { 8610 u8 reserved_at_0[0x8]; 8611 u8 local_port[0x8]; 8612 u8 reserved_at_10[0x5]; 8613 u8 prio[0x3]; 8614 u8 reserved_at_18[0x6]; 8615 u8 mode[0x2]; 8616 8617 u8 reserved_at_20[0x20]; 8618 8619 u8 reserved_at_40[0x10]; 8620 u8 min_threshold[0x10]; 8621 8622 u8 reserved_at_60[0x10]; 8623 u8 max_threshold[0x10]; 8624 8625 u8 reserved_at_80[0x10]; 8626 u8 mark_probability_denominator[0x10]; 8627 8628 u8 reserved_at_a0[0x60]; 8629 }; 8630 8631 struct mlx5_ifc_ppsc_reg_bits { 8632 u8 reserved_at_0[0x8]; 8633 u8 local_port[0x8]; 8634 u8 reserved_at_10[0x10]; 8635 8636 u8 reserved_at_20[0x60]; 8637 8638 u8 reserved_at_80[0x1c]; 8639 u8 wrps_admin[0x4]; 8640 8641 u8 reserved_at_a0[0x1c]; 8642 u8 wrps_status[0x4]; 8643 8644 u8 reserved_at_c0[0x8]; 8645 u8 up_threshold[0x8]; 8646 u8 reserved_at_d0[0x8]; 8647 u8 down_threshold[0x8]; 8648 8649 u8 reserved_at_e0[0x20]; 8650 8651 u8 reserved_at_100[0x1c]; 8652 u8 srps_admin[0x4]; 8653 8654 u8 reserved_at_120[0x1c]; 8655 u8 srps_status[0x4]; 8656 8657 u8 reserved_at_140[0x40]; 8658 }; 8659 8660 struct mlx5_ifc_pplr_reg_bits { 8661 u8 reserved_at_0[0x8]; 8662 u8 local_port[0x8]; 8663 u8 reserved_at_10[0x10]; 8664 8665 u8 reserved_at_20[0x8]; 8666 u8 lb_cap[0x8]; 8667 u8 reserved_at_30[0x8]; 8668 u8 lb_en[0x8]; 8669 }; 8670 8671 struct mlx5_ifc_pplm_reg_bits { 8672 u8 reserved_at_0[0x8]; 8673 u8 local_port[0x8]; 8674 u8 reserved_at_10[0x10]; 8675 8676 u8 reserved_at_20[0x20]; 8677 8678 u8 port_profile_mode[0x8]; 8679 u8 static_port_profile[0x8]; 8680 u8 active_port_profile[0x8]; 8681 u8 reserved_at_58[0x8]; 8682 8683 u8 retransmission_active[0x8]; 8684 u8 fec_mode_active[0x18]; 8685 8686 u8 rs_fec_correction_bypass_cap[0x4]; 8687 u8 reserved_at_84[0x8]; 8688 u8 fec_override_cap_56g[0x4]; 8689 u8 fec_override_cap_100g[0x4]; 8690 u8 fec_override_cap_50g[0x4]; 8691 u8 fec_override_cap_25g[0x4]; 8692 u8 fec_override_cap_10g_40g[0x4]; 8693 8694 u8 rs_fec_correction_bypass_admin[0x4]; 8695 u8 reserved_at_a4[0x8]; 8696 u8 fec_override_admin_56g[0x4]; 8697 u8 fec_override_admin_100g[0x4]; 8698 u8 fec_override_admin_50g[0x4]; 8699 u8 fec_override_admin_25g[0x4]; 8700 u8 fec_override_admin_10g_40g[0x4]; 8701 8702 u8 fec_override_cap_400g_8x[0x10]; 8703 u8 fec_override_cap_200g_4x[0x10]; 8704 8705 u8 fec_override_cap_100g_2x[0x10]; 8706 u8 fec_override_cap_50g_1x[0x10]; 8707 8708 u8 fec_override_admin_400g_8x[0x10]; 8709 u8 fec_override_admin_200g_4x[0x10]; 8710 8711 u8 fec_override_admin_100g_2x[0x10]; 8712 u8 fec_override_admin_50g_1x[0x10]; 8713 }; 8714 8715 struct mlx5_ifc_ppcnt_reg_bits { 8716 u8 swid[0x8]; 8717 u8 local_port[0x8]; 8718 u8 pnat[0x2]; 8719 u8 reserved_at_12[0x8]; 8720 u8 grp[0x6]; 8721 8722 u8 clr[0x1]; 8723 u8 reserved_at_21[0x1c]; 8724 u8 prio_tc[0x3]; 8725 8726 union mlx5_ifc_eth_cntrs_grp_data_layout_auto_bits counter_set; 8727 }; 8728 8729 struct mlx5_ifc_mpein_reg_bits { 8730 u8 reserved_at_0[0x2]; 8731 u8 depth[0x6]; 8732 u8 pcie_index[0x8]; 8733 u8 node[0x8]; 8734 u8 reserved_at_18[0x8]; 8735 8736 u8 capability_mask[0x20]; 8737 8738 u8 reserved_at_40[0x8]; 8739 u8 link_width_enabled[0x8]; 8740 u8 link_speed_enabled[0x10]; 8741 8742 u8 lane0_physical_position[0x8]; 8743 u8 link_width_active[0x8]; 8744 u8 link_speed_active[0x10]; 8745 8746 u8 num_of_pfs[0x10]; 8747 u8 num_of_vfs[0x10]; 8748 8749 u8 bdf0[0x10]; 8750 u8 reserved_at_b0[0x10]; 8751 8752 u8 max_read_request_size[0x4]; 8753 u8 max_payload_size[0x4]; 8754 u8 reserved_at_c8[0x5]; 8755 u8 pwr_status[0x3]; 8756 u8 port_type[0x4]; 8757 u8 reserved_at_d4[0xb]; 8758 u8 lane_reversal[0x1]; 8759 8760 u8 reserved_at_e0[0x14]; 8761 u8 pci_power[0xc]; 8762 8763 u8 reserved_at_100[0x20]; 8764 8765 u8 device_status[0x10]; 8766 u8 port_state[0x8]; 8767 u8 reserved_at_138[0x8]; 8768 8769 u8 reserved_at_140[0x10]; 8770 u8 receiver_detect_result[0x10]; 8771 8772 u8 reserved_at_160[0x20]; 8773 }; 8774 8775 struct mlx5_ifc_mpcnt_reg_bits { 8776 u8 reserved_at_0[0x8]; 8777 u8 pcie_index[0x8]; 8778 u8 reserved_at_10[0xa]; 8779 u8 grp[0x6]; 8780 8781 u8 clr[0x1]; 8782 u8 reserved_at_21[0x1f]; 8783 8784 union mlx5_ifc_pcie_cntrs_grp_data_layout_auto_bits counter_set; 8785 }; 8786 8787 struct mlx5_ifc_ppad_reg_bits { 8788 u8 reserved_at_0[0x3]; 8789 u8 single_mac[0x1]; 8790 u8 reserved_at_4[0x4]; 8791 u8 local_port[0x8]; 8792 u8 mac_47_32[0x10]; 8793 8794 u8 mac_31_0[0x20]; 8795 8796 u8 reserved_at_40[0x40]; 8797 }; 8798 8799 struct mlx5_ifc_pmtu_reg_bits { 8800 u8 reserved_at_0[0x8]; 8801 u8 local_port[0x8]; 8802 u8 reserved_at_10[0x10]; 8803 8804 u8 max_mtu[0x10]; 8805 u8 reserved_at_30[0x10]; 8806 8807 u8 admin_mtu[0x10]; 8808 u8 reserved_at_50[0x10]; 8809 8810 u8 oper_mtu[0x10]; 8811 u8 reserved_at_70[0x10]; 8812 }; 8813 8814 struct mlx5_ifc_pmpr_reg_bits { 8815 u8 reserved_at_0[0x8]; 8816 u8 module[0x8]; 8817 u8 reserved_at_10[0x10]; 8818 8819 u8 reserved_at_20[0x18]; 8820 u8 attenuation_5g[0x8]; 8821 8822 u8 reserved_at_40[0x18]; 8823 u8 attenuation_7g[0x8]; 8824 8825 u8 reserved_at_60[0x18]; 8826 u8 attenuation_12g[0x8]; 8827 }; 8828 8829 struct mlx5_ifc_pmpe_reg_bits { 8830 u8 reserved_at_0[0x8]; 8831 u8 module[0x8]; 8832 u8 reserved_at_10[0xc]; 8833 u8 module_status[0x4]; 8834 8835 u8 reserved_at_20[0x60]; 8836 }; 8837 8838 struct mlx5_ifc_pmpc_reg_bits { 8839 u8 module_state_updated[32][0x8]; 8840 }; 8841 8842 struct mlx5_ifc_pmlpn_reg_bits { 8843 u8 reserved_at_0[0x4]; 8844 u8 mlpn_status[0x4]; 8845 u8 local_port[0x8]; 8846 u8 reserved_at_10[0x10]; 8847 8848 u8 e[0x1]; 8849 u8 reserved_at_21[0x1f]; 8850 }; 8851 8852 struct mlx5_ifc_pmlp_reg_bits { 8853 u8 rxtx[0x1]; 8854 u8 reserved_at_1[0x7]; 8855 u8 local_port[0x8]; 8856 u8 reserved_at_10[0x8]; 8857 u8 width[0x8]; 8858 8859 u8 lane0_module_mapping[0x20]; 8860 8861 u8 lane1_module_mapping[0x20]; 8862 8863 u8 lane2_module_mapping[0x20]; 8864 8865 u8 lane3_module_mapping[0x20]; 8866 8867 u8 reserved_at_a0[0x160]; 8868 }; 8869 8870 struct mlx5_ifc_pmaos_reg_bits { 8871 u8 reserved_at_0[0x8]; 8872 u8 module[0x8]; 8873 u8 reserved_at_10[0x4]; 8874 u8 admin_status[0x4]; 8875 u8 reserved_at_18[0x4]; 8876 u8 oper_status[0x4]; 8877 8878 u8 ase[0x1]; 8879 u8 ee[0x1]; 8880 u8 reserved_at_22[0x1c]; 8881 u8 e[0x2]; 8882 8883 u8 reserved_at_40[0x40]; 8884 }; 8885 8886 struct mlx5_ifc_plpc_reg_bits { 8887 u8 reserved_at_0[0x4]; 8888 u8 profile_id[0xc]; 8889 u8 reserved_at_10[0x4]; 8890 u8 proto_mask[0x4]; 8891 u8 reserved_at_18[0x8]; 8892 8893 u8 reserved_at_20[0x10]; 8894 u8 lane_speed[0x10]; 8895 8896 u8 reserved_at_40[0x17]; 8897 u8 lpbf[0x1]; 8898 u8 fec_mode_policy[0x8]; 8899 8900 u8 retransmission_capability[0x8]; 8901 u8 fec_mode_capability[0x18]; 8902 8903 u8 retransmission_support_admin[0x8]; 8904 u8 fec_mode_support_admin[0x18]; 8905 8906 u8 retransmission_request_admin[0x8]; 8907 u8 fec_mode_request_admin[0x18]; 8908 8909 u8 reserved_at_c0[0x80]; 8910 }; 8911 8912 struct mlx5_ifc_plib_reg_bits { 8913 u8 reserved_at_0[0x8]; 8914 u8 local_port[0x8]; 8915 u8 reserved_at_10[0x8]; 8916 u8 ib_port[0x8]; 8917 8918 u8 reserved_at_20[0x60]; 8919 }; 8920 8921 struct mlx5_ifc_plbf_reg_bits { 8922 u8 reserved_at_0[0x8]; 8923 u8 local_port[0x8]; 8924 u8 reserved_at_10[0xd]; 8925 u8 lbf_mode[0x3]; 8926 8927 u8 reserved_at_20[0x20]; 8928 }; 8929 8930 struct mlx5_ifc_pipg_reg_bits { 8931 u8 reserved_at_0[0x8]; 8932 u8 local_port[0x8]; 8933 u8 reserved_at_10[0x10]; 8934 8935 u8 dic[0x1]; 8936 u8 reserved_at_21[0x19]; 8937 u8 ipg[0x4]; 8938 u8 reserved_at_3e[0x2]; 8939 }; 8940 8941 struct mlx5_ifc_pifr_reg_bits { 8942 u8 reserved_at_0[0x8]; 8943 u8 local_port[0x8]; 8944 u8 reserved_at_10[0x10]; 8945 8946 u8 reserved_at_20[0xe0]; 8947 8948 u8 port_filter[8][0x20]; 8949 8950 u8 port_filter_update_en[8][0x20]; 8951 }; 8952 8953 struct mlx5_ifc_pfcc_reg_bits { 8954 u8 reserved_at_0[0x8]; 8955 u8 local_port[0x8]; 8956 u8 reserved_at_10[0xb]; 8957 u8 ppan_mask_n[0x1]; 8958 u8 minor_stall_mask[0x1]; 8959 u8 critical_stall_mask[0x1]; 8960 u8 reserved_at_1e[0x2]; 8961 8962 u8 ppan[0x4]; 8963 u8 reserved_at_24[0x4]; 8964 u8 prio_mask_tx[0x8]; 8965 u8 reserved_at_30[0x8]; 8966 u8 prio_mask_rx[0x8]; 8967 8968 u8 pptx[0x1]; 8969 u8 aptx[0x1]; 8970 u8 pptx_mask_n[0x1]; 8971 u8 reserved_at_43[0x5]; 8972 u8 pfctx[0x8]; 8973 u8 reserved_at_50[0x10]; 8974 8975 u8 pprx[0x1]; 8976 u8 aprx[0x1]; 8977 u8 pprx_mask_n[0x1]; 8978 u8 reserved_at_63[0x5]; 8979 u8 pfcrx[0x8]; 8980 u8 reserved_at_70[0x10]; 8981 8982 u8 device_stall_minor_watermark[0x10]; 8983 u8 device_stall_critical_watermark[0x10]; 8984 8985 u8 reserved_at_a0[0x60]; 8986 }; 8987 8988 struct mlx5_ifc_pelc_reg_bits { 8989 u8 op[0x4]; 8990 u8 reserved_at_4[0x4]; 8991 u8 local_port[0x8]; 8992 u8 reserved_at_10[0x10]; 8993 8994 u8 op_admin[0x8]; 8995 u8 op_capability[0x8]; 8996 u8 op_request[0x8]; 8997 u8 op_active[0x8]; 8998 8999 u8 admin[0x40]; 9000 9001 u8 capability[0x40]; 9002 9003 u8 request[0x40]; 9004 9005 u8 active[0x40]; 9006 9007 u8 reserved_at_140[0x80]; 9008 }; 9009 9010 struct mlx5_ifc_peir_reg_bits { 9011 u8 reserved_at_0[0x8]; 9012 u8 local_port[0x8]; 9013 u8 reserved_at_10[0x10]; 9014 9015 u8 reserved_at_20[0xc]; 9016 u8 error_count[0x4]; 9017 u8 reserved_at_30[0x10]; 9018 9019 u8 reserved_at_40[0xc]; 9020 u8 lane[0x4]; 9021 u8 reserved_at_50[0x8]; 9022 u8 error_type[0x8]; 9023 }; 9024 9025 struct mlx5_ifc_mpegc_reg_bits { 9026 u8 reserved_at_0[0x30]; 9027 u8 field_select[0x10]; 9028 9029 u8 tx_overflow_sense[0x1]; 9030 u8 mark_cqe[0x1]; 9031 u8 mark_cnp[0x1]; 9032 u8 reserved_at_43[0x1b]; 9033 u8 tx_lossy_overflow_oper[0x2]; 9034 9035 u8 reserved_at_60[0x100]; 9036 }; 9037 9038 struct mlx5_ifc_pcam_enhanced_features_bits { 9039 u8 reserved_at_0[0x68]; 9040 u8 fec_50G_per_lane_in_pplm[0x1]; 9041 u8 reserved_at_69[0x4]; 9042 u8 rx_icrc_encapsulated_counter[0x1]; 9043 u8 reserved_at_6e[0x4]; 9044 u8 ptys_extended_ethernet[0x1]; 9045 u8 reserved_at_73[0x3]; 9046 u8 pfcc_mask[0x1]; 9047 u8 reserved_at_77[0x3]; 9048 u8 per_lane_error_counters[0x1]; 9049 u8 rx_buffer_fullness_counters[0x1]; 9050 u8 ptys_connector_type[0x1]; 9051 u8 reserved_at_7d[0x1]; 9052 u8 ppcnt_discard_group[0x1]; 9053 u8 ppcnt_statistical_group[0x1]; 9054 }; 9055 9056 struct mlx5_ifc_pcam_regs_5000_to_507f_bits { 9057 u8 port_access_reg_cap_mask_127_to_96[0x20]; 9058 u8 port_access_reg_cap_mask_95_to_64[0x20]; 9059 9060 u8 port_access_reg_cap_mask_63_to_36[0x1c]; 9061 u8 pplm[0x1]; 9062 u8 port_access_reg_cap_mask_34_to_32[0x3]; 9063 9064 u8 port_access_reg_cap_mask_31_to_13[0x13]; 9065 u8 pbmc[0x1]; 9066 u8 pptb[0x1]; 9067 u8 port_access_reg_cap_mask_10_to_09[0x2]; 9068 u8 ppcnt[0x1]; 9069 u8 port_access_reg_cap_mask_07_to_00[0x8]; 9070 }; 9071 9072 struct mlx5_ifc_pcam_reg_bits { 9073 u8 reserved_at_0[0x8]; 9074 u8 feature_group[0x8]; 9075 u8 reserved_at_10[0x8]; 9076 u8 access_reg_group[0x8]; 9077 9078 u8 reserved_at_20[0x20]; 9079 9080 union { 9081 struct mlx5_ifc_pcam_regs_5000_to_507f_bits regs_5000_to_507f; 9082 u8 reserved_at_0[0x80]; 9083 } port_access_reg_cap_mask; 9084 9085 u8 reserved_at_c0[0x80]; 9086 9087 union { 9088 struct mlx5_ifc_pcam_enhanced_features_bits enhanced_features; 9089 u8 reserved_at_0[0x80]; 9090 } feature_cap_mask; 9091 9092 u8 reserved_at_1c0[0xc0]; 9093 }; 9094 9095 struct mlx5_ifc_mcam_enhanced_features_bits { 9096 u8 reserved_at_0[0x6e]; 9097 u8 pci_status_and_power[0x1]; 9098 u8 reserved_at_6f[0x5]; 9099 u8 mark_tx_action_cnp[0x1]; 9100 u8 mark_tx_action_cqe[0x1]; 9101 u8 dynamic_tx_overflow[0x1]; 9102 u8 reserved_at_77[0x4]; 9103 u8 pcie_outbound_stalled[0x1]; 9104 u8 tx_overflow_buffer_pkt[0x1]; 9105 u8 mtpps_enh_out_per_adj[0x1]; 9106 u8 mtpps_fs[0x1]; 9107 u8 pcie_performance_group[0x1]; 9108 }; 9109 9110 struct mlx5_ifc_mcam_access_reg_bits { 9111 u8 reserved_at_0[0x1c]; 9112 u8 mcda[0x1]; 9113 u8 mcc[0x1]; 9114 u8 mcqi[0x1]; 9115 u8 mcqs[0x1]; 9116 9117 u8 regs_95_to_87[0x9]; 9118 u8 mpegc[0x1]; 9119 u8 regs_85_to_68[0x12]; 9120 u8 tracer_registers[0x4]; 9121 9122 u8 regs_63_to_32[0x20]; 9123 u8 regs_31_to_0[0x20]; 9124 }; 9125 9126 struct mlx5_ifc_mcam_access_reg_bits1 { 9127 u8 regs_127_to_96[0x20]; 9128 9129 u8 regs_95_to_64[0x20]; 9130 9131 u8 regs_63_to_32[0x20]; 9132 9133 u8 regs_31_to_0[0x20]; 9134 }; 9135 9136 struct mlx5_ifc_mcam_access_reg_bits2 { 9137 u8 regs_127_to_99[0x1d]; 9138 u8 mirc[0x1]; 9139 u8 regs_97_to_96[0x2]; 9140 9141 u8 regs_95_to_64[0x20]; 9142 9143 u8 regs_63_to_32[0x20]; 9144 9145 u8 regs_31_to_0[0x20]; 9146 }; 9147 9148 struct mlx5_ifc_mcam_reg_bits { 9149 u8 reserved_at_0[0x8]; 9150 u8 feature_group[0x8]; 9151 u8 reserved_at_10[0x8]; 9152 u8 access_reg_group[0x8]; 9153 9154 u8 reserved_at_20[0x20]; 9155 9156 union { 9157 struct mlx5_ifc_mcam_access_reg_bits access_regs; 9158 struct mlx5_ifc_mcam_access_reg_bits1 access_regs1; 9159 struct mlx5_ifc_mcam_access_reg_bits2 access_regs2; 9160 u8 reserved_at_0[0x80]; 9161 } mng_access_reg_cap_mask; 9162 9163 u8 reserved_at_c0[0x80]; 9164 9165 union { 9166 struct mlx5_ifc_mcam_enhanced_features_bits enhanced_features; 9167 u8 reserved_at_0[0x80]; 9168 } mng_feature_cap_mask; 9169 9170 u8 reserved_at_1c0[0x80]; 9171 }; 9172 9173 struct mlx5_ifc_qcam_access_reg_cap_mask { 9174 u8 qcam_access_reg_cap_mask_127_to_20[0x6C]; 9175 u8 qpdpm[0x1]; 9176 u8 qcam_access_reg_cap_mask_18_to_4[0x0F]; 9177 u8 qdpm[0x1]; 9178 u8 qpts[0x1]; 9179 u8 qcap[0x1]; 9180 u8 qcam_access_reg_cap_mask_0[0x1]; 9181 }; 9182 9183 struct mlx5_ifc_qcam_qos_feature_cap_mask { 9184 u8 qcam_qos_feature_cap_mask_127_to_1[0x7F]; 9185 u8 qpts_trust_both[0x1]; 9186 }; 9187 9188 struct mlx5_ifc_qcam_reg_bits { 9189 u8 reserved_at_0[0x8]; 9190 u8 feature_group[0x8]; 9191 u8 reserved_at_10[0x8]; 9192 u8 access_reg_group[0x8]; 9193 u8 reserved_at_20[0x20]; 9194 9195 union { 9196 struct mlx5_ifc_qcam_access_reg_cap_mask reg_cap; 9197 u8 reserved_at_0[0x80]; 9198 } qos_access_reg_cap_mask; 9199 9200 u8 reserved_at_c0[0x80]; 9201 9202 union { 9203 struct mlx5_ifc_qcam_qos_feature_cap_mask feature_cap; 9204 u8 reserved_at_0[0x80]; 9205 } qos_feature_cap_mask; 9206 9207 u8 reserved_at_1c0[0x80]; 9208 }; 9209 9210 struct mlx5_ifc_core_dump_reg_bits { 9211 u8 reserved_at_0[0x18]; 9212 u8 core_dump_type[0x8]; 9213 9214 u8 reserved_at_20[0x30]; 9215 u8 vhca_id[0x10]; 9216 9217 u8 reserved_at_60[0x8]; 9218 u8 qpn[0x18]; 9219 u8 reserved_at_80[0x180]; 9220 }; 9221 9222 struct mlx5_ifc_pcap_reg_bits { 9223 u8 reserved_at_0[0x8]; 9224 u8 local_port[0x8]; 9225 u8 reserved_at_10[0x10]; 9226 9227 u8 port_capability_mask[4][0x20]; 9228 }; 9229 9230 struct mlx5_ifc_paos_reg_bits { 9231 u8 swid[0x8]; 9232 u8 local_port[0x8]; 9233 u8 reserved_at_10[0x4]; 9234 u8 admin_status[0x4]; 9235 u8 reserved_at_18[0x4]; 9236 u8 oper_status[0x4]; 9237 9238 u8 ase[0x1]; 9239 u8 ee[0x1]; 9240 u8 reserved_at_22[0x1c]; 9241 u8 e[0x2]; 9242 9243 u8 reserved_at_40[0x40]; 9244 }; 9245 9246 struct mlx5_ifc_pamp_reg_bits { 9247 u8 reserved_at_0[0x8]; 9248 u8 opamp_group[0x8]; 9249 u8 reserved_at_10[0xc]; 9250 u8 opamp_group_type[0x4]; 9251 9252 u8 start_index[0x10]; 9253 u8 reserved_at_30[0x4]; 9254 u8 num_of_indices[0xc]; 9255 9256 u8 index_data[18][0x10]; 9257 }; 9258 9259 struct mlx5_ifc_pcmr_reg_bits { 9260 u8 reserved_at_0[0x8]; 9261 u8 local_port[0x8]; 9262 u8 reserved_at_10[0x10]; 9263 u8 entropy_force_cap[0x1]; 9264 u8 entropy_calc_cap[0x1]; 9265 u8 entropy_gre_calc_cap[0x1]; 9266 u8 reserved_at_23[0x1b]; 9267 u8 fcs_cap[0x1]; 9268 u8 reserved_at_3f[0x1]; 9269 u8 entropy_force[0x1]; 9270 u8 entropy_calc[0x1]; 9271 u8 entropy_gre_calc[0x1]; 9272 u8 reserved_at_43[0x1b]; 9273 u8 fcs_chk[0x1]; 9274 u8 reserved_at_5f[0x1]; 9275 }; 9276 9277 struct mlx5_ifc_lane_2_module_mapping_bits { 9278 u8 reserved_at_0[0x6]; 9279 u8 rx_lane[0x2]; 9280 u8 reserved_at_8[0x6]; 9281 u8 tx_lane[0x2]; 9282 u8 reserved_at_10[0x8]; 9283 u8 module[0x8]; 9284 }; 9285 9286 struct mlx5_ifc_bufferx_reg_bits { 9287 u8 reserved_at_0[0x6]; 9288 u8 lossy[0x1]; 9289 u8 epsb[0x1]; 9290 u8 reserved_at_8[0xc]; 9291 u8 size[0xc]; 9292 9293 u8 xoff_threshold[0x10]; 9294 u8 xon_threshold[0x10]; 9295 }; 9296 9297 struct mlx5_ifc_set_node_in_bits { 9298 u8 node_description[64][0x8]; 9299 }; 9300 9301 struct mlx5_ifc_register_power_settings_bits { 9302 u8 reserved_at_0[0x18]; 9303 u8 power_settings_level[0x8]; 9304 9305 u8 reserved_at_20[0x60]; 9306 }; 9307 9308 struct mlx5_ifc_register_host_endianness_bits { 9309 u8 he[0x1]; 9310 u8 reserved_at_1[0x1f]; 9311 9312 u8 reserved_at_20[0x60]; 9313 }; 9314 9315 struct mlx5_ifc_umr_pointer_desc_argument_bits { 9316 u8 reserved_at_0[0x20]; 9317 9318 u8 mkey[0x20]; 9319 9320 u8 addressh_63_32[0x20]; 9321 9322 u8 addressl_31_0[0x20]; 9323 }; 9324 9325 struct mlx5_ifc_ud_adrs_vector_bits { 9326 u8 dc_key[0x40]; 9327 9328 u8 ext[0x1]; 9329 u8 reserved_at_41[0x7]; 9330 u8 destination_qp_dct[0x18]; 9331 9332 u8 static_rate[0x4]; 9333 u8 sl_eth_prio[0x4]; 9334 u8 fl[0x1]; 9335 u8 mlid[0x7]; 9336 u8 rlid_udp_sport[0x10]; 9337 9338 u8 reserved_at_80[0x20]; 9339 9340 u8 rmac_47_16[0x20]; 9341 9342 u8 rmac_15_0[0x10]; 9343 u8 tclass[0x8]; 9344 u8 hop_limit[0x8]; 9345 9346 u8 reserved_at_e0[0x1]; 9347 u8 grh[0x1]; 9348 u8 reserved_at_e2[0x2]; 9349 u8 src_addr_index[0x8]; 9350 u8 flow_label[0x14]; 9351 9352 u8 rgid_rip[16][0x8]; 9353 }; 9354 9355 struct mlx5_ifc_pages_req_event_bits { 9356 u8 reserved_at_0[0x10]; 9357 u8 function_id[0x10]; 9358 9359 u8 num_pages[0x20]; 9360 9361 u8 reserved_at_40[0xa0]; 9362 }; 9363 9364 struct mlx5_ifc_eqe_bits { 9365 u8 reserved_at_0[0x8]; 9366 u8 event_type[0x8]; 9367 u8 reserved_at_10[0x8]; 9368 u8 event_sub_type[0x8]; 9369 9370 u8 reserved_at_20[0xe0]; 9371 9372 union mlx5_ifc_event_auto_bits event_data; 9373 9374 u8 reserved_at_1e0[0x10]; 9375 u8 signature[0x8]; 9376 u8 reserved_at_1f8[0x7]; 9377 u8 owner[0x1]; 9378 }; 9379 9380 enum { 9381 MLX5_CMD_QUEUE_ENTRY_TYPE_PCIE_CMD_IF_TRANSPORT = 0x7, 9382 }; 9383 9384 struct mlx5_ifc_cmd_queue_entry_bits { 9385 u8 type[0x8]; 9386 u8 reserved_at_8[0x18]; 9387 9388 u8 input_length[0x20]; 9389 9390 u8 input_mailbox_pointer_63_32[0x20]; 9391 9392 u8 input_mailbox_pointer_31_9[0x17]; 9393 u8 reserved_at_77[0x9]; 9394 9395 u8 command_input_inline_data[16][0x8]; 9396 9397 u8 command_output_inline_data[16][0x8]; 9398 9399 u8 output_mailbox_pointer_63_32[0x20]; 9400 9401 u8 output_mailbox_pointer_31_9[0x17]; 9402 u8 reserved_at_1b7[0x9]; 9403 9404 u8 output_length[0x20]; 9405 9406 u8 token[0x8]; 9407 u8 signature[0x8]; 9408 u8 reserved_at_1f0[0x8]; 9409 u8 status[0x7]; 9410 u8 ownership[0x1]; 9411 }; 9412 9413 struct mlx5_ifc_cmd_out_bits { 9414 u8 status[0x8]; 9415 u8 reserved_at_8[0x18]; 9416 9417 u8 syndrome[0x20]; 9418 9419 u8 command_output[0x20]; 9420 }; 9421 9422 struct mlx5_ifc_cmd_in_bits { 9423 u8 opcode[0x10]; 9424 u8 reserved_at_10[0x10]; 9425 9426 u8 reserved_at_20[0x10]; 9427 u8 op_mod[0x10]; 9428 9429 u8 command[][0x20]; 9430 }; 9431 9432 struct mlx5_ifc_cmd_if_box_bits { 9433 u8 mailbox_data[512][0x8]; 9434 9435 u8 reserved_at_1000[0x180]; 9436 9437 u8 next_pointer_63_32[0x20]; 9438 9439 u8 next_pointer_31_10[0x16]; 9440 u8 reserved_at_11b6[0xa]; 9441 9442 u8 block_number[0x20]; 9443 9444 u8 reserved_at_11e0[0x8]; 9445 u8 token[0x8]; 9446 u8 ctrl_signature[0x8]; 9447 u8 signature[0x8]; 9448 }; 9449 9450 struct mlx5_ifc_mtt_bits { 9451 u8 ptag_63_32[0x20]; 9452 9453 u8 ptag_31_8[0x18]; 9454 u8 reserved_at_38[0x6]; 9455 u8 wr_en[0x1]; 9456 u8 rd_en[0x1]; 9457 }; 9458 9459 struct mlx5_ifc_query_wol_rol_out_bits { 9460 u8 status[0x8]; 9461 u8 reserved_at_8[0x18]; 9462 9463 u8 syndrome[0x20]; 9464 9465 u8 reserved_at_40[0x10]; 9466 u8 rol_mode[0x8]; 9467 u8 wol_mode[0x8]; 9468 9469 u8 reserved_at_60[0x20]; 9470 }; 9471 9472 struct mlx5_ifc_query_wol_rol_in_bits { 9473 u8 opcode[0x10]; 9474 u8 reserved_at_10[0x10]; 9475 9476 u8 reserved_at_20[0x10]; 9477 u8 op_mod[0x10]; 9478 9479 u8 reserved_at_40[0x40]; 9480 }; 9481 9482 struct mlx5_ifc_set_wol_rol_out_bits { 9483 u8 status[0x8]; 9484 u8 reserved_at_8[0x18]; 9485 9486 u8 syndrome[0x20]; 9487 9488 u8 reserved_at_40[0x40]; 9489 }; 9490 9491 struct mlx5_ifc_set_wol_rol_in_bits { 9492 u8 opcode[0x10]; 9493 u8 reserved_at_10[0x10]; 9494 9495 u8 reserved_at_20[0x10]; 9496 u8 op_mod[0x10]; 9497 9498 u8 rol_mode_valid[0x1]; 9499 u8 wol_mode_valid[0x1]; 9500 u8 reserved_at_42[0xe]; 9501 u8 rol_mode[0x8]; 9502 u8 wol_mode[0x8]; 9503 9504 u8 reserved_at_60[0x20]; 9505 }; 9506 9507 enum { 9508 MLX5_INITIAL_SEG_NIC_INTERFACE_FULL_DRIVER = 0x0, 9509 MLX5_INITIAL_SEG_NIC_INTERFACE_DISABLED = 0x1, 9510 MLX5_INITIAL_SEG_NIC_INTERFACE_NO_DRAM_NIC = 0x2, 9511 }; 9512 9513 enum { 9514 MLX5_INITIAL_SEG_NIC_INTERFACE_SUPPORTED_FULL_DRIVER = 0x0, 9515 MLX5_INITIAL_SEG_NIC_INTERFACE_SUPPORTED_DISABLED = 0x1, 9516 MLX5_INITIAL_SEG_NIC_INTERFACE_SUPPORTED_NO_DRAM_NIC = 0x2, 9517 }; 9518 9519 enum { 9520 MLX5_INITIAL_SEG_HEALTH_SYNDROME_FW_INTERNAL_ERR = 0x1, 9521 MLX5_INITIAL_SEG_HEALTH_SYNDROME_DEAD_IRISC = 0x7, 9522 MLX5_INITIAL_SEG_HEALTH_SYNDROME_HW_FATAL_ERR = 0x8, 9523 MLX5_INITIAL_SEG_HEALTH_SYNDROME_FW_CRC_ERR = 0x9, 9524 MLX5_INITIAL_SEG_HEALTH_SYNDROME_ICM_FETCH_PCI_ERR = 0xa, 9525 MLX5_INITIAL_SEG_HEALTH_SYNDROME_ICM_PAGE_ERR = 0xb, 9526 MLX5_INITIAL_SEG_HEALTH_SYNDROME_ASYNCHRONOUS_EQ_BUF_OVERRUN = 0xc, 9527 MLX5_INITIAL_SEG_HEALTH_SYNDROME_EQ_IN_ERR = 0xd, 9528 MLX5_INITIAL_SEG_HEALTH_SYNDROME_EQ_INV = 0xe, 9529 MLX5_INITIAL_SEG_HEALTH_SYNDROME_FFSER_ERR = 0xf, 9530 MLX5_INITIAL_SEG_HEALTH_SYNDROME_HIGH_TEMP_ERR = 0x10, 9531 }; 9532 9533 struct mlx5_ifc_initial_seg_bits { 9534 u8 fw_rev_minor[0x10]; 9535 u8 fw_rev_major[0x10]; 9536 9537 u8 cmd_interface_rev[0x10]; 9538 u8 fw_rev_subminor[0x10]; 9539 9540 u8 reserved_at_40[0x40]; 9541 9542 u8 cmdq_phy_addr_63_32[0x20]; 9543 9544 u8 cmdq_phy_addr_31_12[0x14]; 9545 u8 reserved_at_b4[0x2]; 9546 u8 nic_interface[0x2]; 9547 u8 log_cmdq_size[0x4]; 9548 u8 log_cmdq_stride[0x4]; 9549 9550 u8 command_doorbell_vector[0x20]; 9551 9552 u8 reserved_at_e0[0xf00]; 9553 9554 u8 initializing[0x1]; 9555 u8 reserved_at_fe1[0x4]; 9556 u8 nic_interface_supported[0x3]; 9557 u8 embedded_cpu[0x1]; 9558 u8 reserved_at_fe9[0x17]; 9559 9560 struct mlx5_ifc_health_buffer_bits health_buffer; 9561 9562 u8 no_dram_nic_offset[0x20]; 9563 9564 u8 reserved_at_1220[0x6e40]; 9565 9566 u8 reserved_at_8060[0x1f]; 9567 u8 clear_int[0x1]; 9568 9569 u8 health_syndrome[0x8]; 9570 u8 health_counter[0x18]; 9571 9572 u8 reserved_at_80a0[0x17fc0]; 9573 }; 9574 9575 struct mlx5_ifc_mtpps_reg_bits { 9576 u8 reserved_at_0[0xc]; 9577 u8 cap_number_of_pps_pins[0x4]; 9578 u8 reserved_at_10[0x4]; 9579 u8 cap_max_num_of_pps_in_pins[0x4]; 9580 u8 reserved_at_18[0x4]; 9581 u8 cap_max_num_of_pps_out_pins[0x4]; 9582 9583 u8 reserved_at_20[0x24]; 9584 u8 cap_pin_3_mode[0x4]; 9585 u8 reserved_at_48[0x4]; 9586 u8 cap_pin_2_mode[0x4]; 9587 u8 reserved_at_50[0x4]; 9588 u8 cap_pin_1_mode[0x4]; 9589 u8 reserved_at_58[0x4]; 9590 u8 cap_pin_0_mode[0x4]; 9591 9592 u8 reserved_at_60[0x4]; 9593 u8 cap_pin_7_mode[0x4]; 9594 u8 reserved_at_68[0x4]; 9595 u8 cap_pin_6_mode[0x4]; 9596 u8 reserved_at_70[0x4]; 9597 u8 cap_pin_5_mode[0x4]; 9598 u8 reserved_at_78[0x4]; 9599 u8 cap_pin_4_mode[0x4]; 9600 9601 u8 field_select[0x20]; 9602 u8 reserved_at_a0[0x60]; 9603 9604 u8 enable[0x1]; 9605 u8 reserved_at_101[0xb]; 9606 u8 pattern[0x4]; 9607 u8 reserved_at_110[0x4]; 9608 u8 pin_mode[0x4]; 9609 u8 pin[0x8]; 9610 9611 u8 reserved_at_120[0x20]; 9612 9613 u8 time_stamp[0x40]; 9614 9615 u8 out_pulse_duration[0x10]; 9616 u8 out_periodic_adjustment[0x10]; 9617 u8 enhanced_out_periodic_adjustment[0x20]; 9618 9619 u8 reserved_at_1c0[0x20]; 9620 }; 9621 9622 struct mlx5_ifc_mtppse_reg_bits { 9623 u8 reserved_at_0[0x18]; 9624 u8 pin[0x8]; 9625 u8 event_arm[0x1]; 9626 u8 reserved_at_21[0x1b]; 9627 u8 event_generation_mode[0x4]; 9628 u8 reserved_at_40[0x40]; 9629 }; 9630 9631 struct mlx5_ifc_mcqs_reg_bits { 9632 u8 last_index_flag[0x1]; 9633 u8 reserved_at_1[0x7]; 9634 u8 fw_device[0x8]; 9635 u8 component_index[0x10]; 9636 9637 u8 reserved_at_20[0x10]; 9638 u8 identifier[0x10]; 9639 9640 u8 reserved_at_40[0x17]; 9641 u8 component_status[0x5]; 9642 u8 component_update_state[0x4]; 9643 9644 u8 last_update_state_changer_type[0x4]; 9645 u8 last_update_state_changer_host_id[0x4]; 9646 u8 reserved_at_68[0x18]; 9647 }; 9648 9649 struct mlx5_ifc_mcqi_cap_bits { 9650 u8 supported_info_bitmask[0x20]; 9651 9652 u8 component_size[0x20]; 9653 9654 u8 max_component_size[0x20]; 9655 9656 u8 log_mcda_word_size[0x4]; 9657 u8 reserved_at_64[0xc]; 9658 u8 mcda_max_write_size[0x10]; 9659 9660 u8 rd_en[0x1]; 9661 u8 reserved_at_81[0x1]; 9662 u8 match_chip_id[0x1]; 9663 u8 match_psid[0x1]; 9664 u8 check_user_timestamp[0x1]; 9665 u8 match_base_guid_mac[0x1]; 9666 u8 reserved_at_86[0x1a]; 9667 }; 9668 9669 struct mlx5_ifc_mcqi_version_bits { 9670 u8 reserved_at_0[0x2]; 9671 u8 build_time_valid[0x1]; 9672 u8 user_defined_time_valid[0x1]; 9673 u8 reserved_at_4[0x14]; 9674 u8 version_string_length[0x8]; 9675 9676 u8 version[0x20]; 9677 9678 u8 build_time[0x40]; 9679 9680 u8 user_defined_time[0x40]; 9681 9682 u8 build_tool_version[0x20]; 9683 9684 u8 reserved_at_e0[0x20]; 9685 9686 u8 version_string[92][0x8]; 9687 }; 9688 9689 struct mlx5_ifc_mcqi_activation_method_bits { 9690 u8 pending_server_ac_power_cycle[0x1]; 9691 u8 pending_server_dc_power_cycle[0x1]; 9692 u8 pending_server_reboot[0x1]; 9693 u8 pending_fw_reset[0x1]; 9694 u8 auto_activate[0x1]; 9695 u8 all_hosts_sync[0x1]; 9696 u8 device_hw_reset[0x1]; 9697 u8 reserved_at_7[0x19]; 9698 }; 9699 9700 union mlx5_ifc_mcqi_reg_data_bits { 9701 struct mlx5_ifc_mcqi_cap_bits mcqi_caps; 9702 struct mlx5_ifc_mcqi_version_bits mcqi_version; 9703 struct mlx5_ifc_mcqi_activation_method_bits mcqi_activation_mathod; 9704 }; 9705 9706 struct mlx5_ifc_mcqi_reg_bits { 9707 u8 read_pending_component[0x1]; 9708 u8 reserved_at_1[0xf]; 9709 u8 component_index[0x10]; 9710 9711 u8 reserved_at_20[0x20]; 9712 9713 u8 reserved_at_40[0x1b]; 9714 u8 info_type[0x5]; 9715 9716 u8 info_size[0x20]; 9717 9718 u8 offset[0x20]; 9719 9720 u8 reserved_at_a0[0x10]; 9721 u8 data_size[0x10]; 9722 9723 union mlx5_ifc_mcqi_reg_data_bits data[]; 9724 }; 9725 9726 struct mlx5_ifc_mcc_reg_bits { 9727 u8 reserved_at_0[0x4]; 9728 u8 time_elapsed_since_last_cmd[0xc]; 9729 u8 reserved_at_10[0x8]; 9730 u8 instruction[0x8]; 9731 9732 u8 reserved_at_20[0x10]; 9733 u8 component_index[0x10]; 9734 9735 u8 reserved_at_40[0x8]; 9736 u8 update_handle[0x18]; 9737 9738 u8 handle_owner_type[0x4]; 9739 u8 handle_owner_host_id[0x4]; 9740 u8 reserved_at_68[0x1]; 9741 u8 control_progress[0x7]; 9742 u8 error_code[0x8]; 9743 u8 reserved_at_78[0x4]; 9744 u8 control_state[0x4]; 9745 9746 u8 component_size[0x20]; 9747 9748 u8 reserved_at_a0[0x60]; 9749 }; 9750 9751 struct mlx5_ifc_mcda_reg_bits { 9752 u8 reserved_at_0[0x8]; 9753 u8 update_handle[0x18]; 9754 9755 u8 offset[0x20]; 9756 9757 u8 reserved_at_40[0x10]; 9758 u8 size[0x10]; 9759 9760 u8 reserved_at_60[0x20]; 9761 9762 u8 data[0][0x20]; 9763 }; 9764 9765 enum { 9766 MLX5_MFRL_REG_RESET_TYPE_FULL_CHIP = BIT(0), 9767 MLX5_MFRL_REG_RESET_TYPE_NET_PORT_ALIVE = BIT(1), 9768 }; 9769 9770 enum { 9771 MLX5_MFRL_REG_RESET_LEVEL0 = BIT(0), 9772 MLX5_MFRL_REG_RESET_LEVEL3 = BIT(3), 9773 MLX5_MFRL_REG_RESET_LEVEL6 = BIT(6), 9774 }; 9775 9776 struct mlx5_ifc_mfrl_reg_bits { 9777 u8 reserved_at_0[0x20]; 9778 9779 u8 reserved_at_20[0x2]; 9780 u8 pci_sync_for_fw_update_start[0x1]; 9781 u8 pci_sync_for_fw_update_resp[0x2]; 9782 u8 rst_type_sel[0x3]; 9783 u8 reserved_at_28[0x8]; 9784 u8 reset_type[0x8]; 9785 u8 reset_level[0x8]; 9786 }; 9787 9788 struct mlx5_ifc_mirc_reg_bits { 9789 u8 reserved_at_0[0x18]; 9790 u8 status_code[0x8]; 9791 9792 u8 reserved_at_20[0x20]; 9793 }; 9794 9795 union mlx5_ifc_ports_control_registers_document_bits { 9796 struct mlx5_ifc_bufferx_reg_bits bufferx_reg; 9797 struct mlx5_ifc_eth_2819_cntrs_grp_data_layout_bits eth_2819_cntrs_grp_data_layout; 9798 struct mlx5_ifc_eth_2863_cntrs_grp_data_layout_bits eth_2863_cntrs_grp_data_layout; 9799 struct mlx5_ifc_eth_3635_cntrs_grp_data_layout_bits eth_3635_cntrs_grp_data_layout; 9800 struct mlx5_ifc_eth_802_3_cntrs_grp_data_layout_bits eth_802_3_cntrs_grp_data_layout; 9801 struct mlx5_ifc_eth_extended_cntrs_grp_data_layout_bits eth_extended_cntrs_grp_data_layout; 9802 struct mlx5_ifc_eth_per_prio_grp_data_layout_bits eth_per_prio_grp_data_layout; 9803 struct mlx5_ifc_eth_per_tc_prio_grp_data_layout_bits eth_per_tc_prio_grp_data_layout; 9804 struct mlx5_ifc_eth_per_tc_congest_prio_grp_data_layout_bits eth_per_tc_congest_prio_grp_data_layout; 9805 struct mlx5_ifc_lane_2_module_mapping_bits lane_2_module_mapping; 9806 struct mlx5_ifc_pamp_reg_bits pamp_reg; 9807 struct mlx5_ifc_paos_reg_bits paos_reg; 9808 struct mlx5_ifc_pcap_reg_bits pcap_reg; 9809 struct mlx5_ifc_peir_reg_bits peir_reg; 9810 struct mlx5_ifc_pelc_reg_bits pelc_reg; 9811 struct mlx5_ifc_pfcc_reg_bits pfcc_reg; 9812 struct mlx5_ifc_ib_port_cntrs_grp_data_layout_bits ib_port_cntrs_grp_data_layout; 9813 struct mlx5_ifc_phys_layer_cntrs_bits phys_layer_cntrs; 9814 struct mlx5_ifc_pifr_reg_bits pifr_reg; 9815 struct mlx5_ifc_pipg_reg_bits pipg_reg; 9816 struct mlx5_ifc_plbf_reg_bits plbf_reg; 9817 struct mlx5_ifc_plib_reg_bits plib_reg; 9818 struct mlx5_ifc_plpc_reg_bits plpc_reg; 9819 struct mlx5_ifc_pmaos_reg_bits pmaos_reg; 9820 struct mlx5_ifc_pmlp_reg_bits pmlp_reg; 9821 struct mlx5_ifc_pmlpn_reg_bits pmlpn_reg; 9822 struct mlx5_ifc_pmpc_reg_bits pmpc_reg; 9823 struct mlx5_ifc_pmpe_reg_bits pmpe_reg; 9824 struct mlx5_ifc_pmpr_reg_bits pmpr_reg; 9825 struct mlx5_ifc_pmtu_reg_bits pmtu_reg; 9826 struct mlx5_ifc_ppad_reg_bits ppad_reg; 9827 struct mlx5_ifc_ppcnt_reg_bits ppcnt_reg; 9828 struct mlx5_ifc_mpein_reg_bits mpein_reg; 9829 struct mlx5_ifc_mpcnt_reg_bits mpcnt_reg; 9830 struct mlx5_ifc_pplm_reg_bits pplm_reg; 9831 struct mlx5_ifc_pplr_reg_bits pplr_reg; 9832 struct mlx5_ifc_ppsc_reg_bits ppsc_reg; 9833 struct mlx5_ifc_pqdr_reg_bits pqdr_reg; 9834 struct mlx5_ifc_pspa_reg_bits pspa_reg; 9835 struct mlx5_ifc_ptas_reg_bits ptas_reg; 9836 struct mlx5_ifc_ptys_reg_bits ptys_reg; 9837 struct mlx5_ifc_mlcr_reg_bits mlcr_reg; 9838 struct mlx5_ifc_pude_reg_bits pude_reg; 9839 struct mlx5_ifc_pvlc_reg_bits pvlc_reg; 9840 struct mlx5_ifc_slrg_reg_bits slrg_reg; 9841 struct mlx5_ifc_sltp_reg_bits sltp_reg; 9842 struct mlx5_ifc_mtpps_reg_bits mtpps_reg; 9843 struct mlx5_ifc_mtppse_reg_bits mtppse_reg; 9844 struct mlx5_ifc_fpga_access_reg_bits fpga_access_reg; 9845 struct mlx5_ifc_fpga_ctrl_bits fpga_ctrl_bits; 9846 struct mlx5_ifc_fpga_cap_bits fpga_cap_bits; 9847 struct mlx5_ifc_mcqi_reg_bits mcqi_reg; 9848 struct mlx5_ifc_mcc_reg_bits mcc_reg; 9849 struct mlx5_ifc_mcda_reg_bits mcda_reg; 9850 struct mlx5_ifc_mirc_reg_bits mirc_reg; 9851 struct mlx5_ifc_mfrl_reg_bits mfrl_reg; 9852 u8 reserved_at_0[0x60e0]; 9853 }; 9854 9855 union mlx5_ifc_debug_enhancements_document_bits { 9856 struct mlx5_ifc_health_buffer_bits health_buffer; 9857 u8 reserved_at_0[0x200]; 9858 }; 9859 9860 union mlx5_ifc_uplink_pci_interface_document_bits { 9861 struct mlx5_ifc_initial_seg_bits initial_seg; 9862 u8 reserved_at_0[0x20060]; 9863 }; 9864 9865 struct mlx5_ifc_set_flow_table_root_out_bits { 9866 u8 status[0x8]; 9867 u8 reserved_at_8[0x18]; 9868 9869 u8 syndrome[0x20]; 9870 9871 u8 reserved_at_40[0x40]; 9872 }; 9873 9874 struct mlx5_ifc_set_flow_table_root_in_bits { 9875 u8 opcode[0x10]; 9876 u8 reserved_at_10[0x10]; 9877 9878 u8 reserved_at_20[0x10]; 9879 u8 op_mod[0x10]; 9880 9881 u8 other_vport[0x1]; 9882 u8 reserved_at_41[0xf]; 9883 u8 vport_number[0x10]; 9884 9885 u8 reserved_at_60[0x20]; 9886 9887 u8 table_type[0x8]; 9888 u8 reserved_at_88[0x18]; 9889 9890 u8 reserved_at_a0[0x8]; 9891 u8 table_id[0x18]; 9892 9893 u8 reserved_at_c0[0x8]; 9894 u8 underlay_qpn[0x18]; 9895 u8 reserved_at_e0[0x120]; 9896 }; 9897 9898 enum { 9899 MLX5_MODIFY_FLOW_TABLE_MISS_TABLE_ID = (1UL << 0), 9900 MLX5_MODIFY_FLOW_TABLE_LAG_NEXT_TABLE_ID = (1UL << 15), 9901 }; 9902 9903 struct mlx5_ifc_modify_flow_table_out_bits { 9904 u8 status[0x8]; 9905 u8 reserved_at_8[0x18]; 9906 9907 u8 syndrome[0x20]; 9908 9909 u8 reserved_at_40[0x40]; 9910 }; 9911 9912 struct mlx5_ifc_modify_flow_table_in_bits { 9913 u8 opcode[0x10]; 9914 u8 reserved_at_10[0x10]; 9915 9916 u8 reserved_at_20[0x10]; 9917 u8 op_mod[0x10]; 9918 9919 u8 other_vport[0x1]; 9920 u8 reserved_at_41[0xf]; 9921 u8 vport_number[0x10]; 9922 9923 u8 reserved_at_60[0x10]; 9924 u8 modify_field_select[0x10]; 9925 9926 u8 table_type[0x8]; 9927 u8 reserved_at_88[0x18]; 9928 9929 u8 reserved_at_a0[0x8]; 9930 u8 table_id[0x18]; 9931 9932 struct mlx5_ifc_flow_table_context_bits flow_table_context; 9933 }; 9934 9935 struct mlx5_ifc_ets_tcn_config_reg_bits { 9936 u8 g[0x1]; 9937 u8 b[0x1]; 9938 u8 r[0x1]; 9939 u8 reserved_at_3[0x9]; 9940 u8 group[0x4]; 9941 u8 reserved_at_10[0x9]; 9942 u8 bw_allocation[0x7]; 9943 9944 u8 reserved_at_20[0xc]; 9945 u8 max_bw_units[0x4]; 9946 u8 reserved_at_30[0x8]; 9947 u8 max_bw_value[0x8]; 9948 }; 9949 9950 struct mlx5_ifc_ets_global_config_reg_bits { 9951 u8 reserved_at_0[0x2]; 9952 u8 r[0x1]; 9953 u8 reserved_at_3[0x1d]; 9954 9955 u8 reserved_at_20[0xc]; 9956 u8 max_bw_units[0x4]; 9957 u8 reserved_at_30[0x8]; 9958 u8 max_bw_value[0x8]; 9959 }; 9960 9961 struct mlx5_ifc_qetc_reg_bits { 9962 u8 reserved_at_0[0x8]; 9963 u8 port_number[0x8]; 9964 u8 reserved_at_10[0x30]; 9965 9966 struct mlx5_ifc_ets_tcn_config_reg_bits tc_configuration[0x8]; 9967 struct mlx5_ifc_ets_global_config_reg_bits global_configuration; 9968 }; 9969 9970 struct mlx5_ifc_qpdpm_dscp_reg_bits { 9971 u8 e[0x1]; 9972 u8 reserved_at_01[0x0b]; 9973 u8 prio[0x04]; 9974 }; 9975 9976 struct mlx5_ifc_qpdpm_reg_bits { 9977 u8 reserved_at_0[0x8]; 9978 u8 local_port[0x8]; 9979 u8 reserved_at_10[0x10]; 9980 struct mlx5_ifc_qpdpm_dscp_reg_bits dscp[64]; 9981 }; 9982 9983 struct mlx5_ifc_qpts_reg_bits { 9984 u8 reserved_at_0[0x8]; 9985 u8 local_port[0x8]; 9986 u8 reserved_at_10[0x2d]; 9987 u8 trust_state[0x3]; 9988 }; 9989 9990 struct mlx5_ifc_pptb_reg_bits { 9991 u8 reserved_at_0[0x2]; 9992 u8 mm[0x2]; 9993 u8 reserved_at_4[0x4]; 9994 u8 local_port[0x8]; 9995 u8 reserved_at_10[0x6]; 9996 u8 cm[0x1]; 9997 u8 um[0x1]; 9998 u8 pm[0x8]; 9999 10000 u8 prio_x_buff[0x20]; 10001 10002 u8 pm_msb[0x8]; 10003 u8 reserved_at_48[0x10]; 10004 u8 ctrl_buff[0x4]; 10005 u8 untagged_buff[0x4]; 10006 }; 10007 10008 struct mlx5_ifc_sbcam_reg_bits { 10009 u8 reserved_at_0[0x8]; 10010 u8 feature_group[0x8]; 10011 u8 reserved_at_10[0x8]; 10012 u8 access_reg_group[0x8]; 10013 10014 u8 reserved_at_20[0x20]; 10015 10016 u8 sb_access_reg_cap_mask[4][0x20]; 10017 10018 u8 reserved_at_c0[0x80]; 10019 10020 u8 sb_feature_cap_mask[4][0x20]; 10021 10022 u8 reserved_at_1c0[0x40]; 10023 10024 u8 cap_total_buffer_size[0x20]; 10025 10026 u8 cap_cell_size[0x10]; 10027 u8 cap_max_pg_buffers[0x8]; 10028 u8 cap_num_pool_supported[0x8]; 10029 10030 u8 reserved_at_240[0x8]; 10031 u8 cap_sbsr_stat_size[0x8]; 10032 u8 cap_max_tclass_data[0x8]; 10033 u8 cap_max_cpu_ingress_tclass_sb[0x8]; 10034 }; 10035 10036 struct mlx5_ifc_pbmc_reg_bits { 10037 u8 reserved_at_0[0x8]; 10038 u8 local_port[0x8]; 10039 u8 reserved_at_10[0x10]; 10040 10041 u8 xoff_timer_value[0x10]; 10042 u8 xoff_refresh[0x10]; 10043 10044 u8 reserved_at_40[0x9]; 10045 u8 fullness_threshold[0x7]; 10046 u8 port_buffer_size[0x10]; 10047 10048 struct mlx5_ifc_bufferx_reg_bits buffer[10]; 10049 10050 u8 reserved_at_2e0[0x40]; 10051 }; 10052 10053 struct mlx5_ifc_qtct_reg_bits { 10054 u8 reserved_at_0[0x8]; 10055 u8 port_number[0x8]; 10056 u8 reserved_at_10[0xd]; 10057 u8 prio[0x3]; 10058 10059 u8 reserved_at_20[0x1d]; 10060 u8 tclass[0x3]; 10061 }; 10062 10063 struct mlx5_ifc_mcia_reg_bits { 10064 u8 l[0x1]; 10065 u8 reserved_at_1[0x7]; 10066 u8 module[0x8]; 10067 u8 reserved_at_10[0x8]; 10068 u8 status[0x8]; 10069 10070 u8 i2c_device_address[0x8]; 10071 u8 page_number[0x8]; 10072 u8 device_address[0x10]; 10073 10074 u8 reserved_at_40[0x10]; 10075 u8 size[0x10]; 10076 10077 u8 reserved_at_60[0x20]; 10078 10079 u8 dword_0[0x20]; 10080 u8 dword_1[0x20]; 10081 u8 dword_2[0x20]; 10082 u8 dword_3[0x20]; 10083 u8 dword_4[0x20]; 10084 u8 dword_5[0x20]; 10085 u8 dword_6[0x20]; 10086 u8 dword_7[0x20]; 10087 u8 dword_8[0x20]; 10088 u8 dword_9[0x20]; 10089 u8 dword_10[0x20]; 10090 u8 dword_11[0x20]; 10091 }; 10092 10093 struct mlx5_ifc_dcbx_param_bits { 10094 u8 dcbx_cee_cap[0x1]; 10095 u8 dcbx_ieee_cap[0x1]; 10096 u8 dcbx_standby_cap[0x1]; 10097 u8 reserved_at_3[0x5]; 10098 u8 port_number[0x8]; 10099 u8 reserved_at_10[0xa]; 10100 u8 max_application_table_size[6]; 10101 u8 reserved_at_20[0x15]; 10102 u8 version_oper[0x3]; 10103 u8 reserved_at_38[5]; 10104 u8 version_admin[0x3]; 10105 u8 willing_admin[0x1]; 10106 u8 reserved_at_41[0x3]; 10107 u8 pfc_cap_oper[0x4]; 10108 u8 reserved_at_48[0x4]; 10109 u8 pfc_cap_admin[0x4]; 10110 u8 reserved_at_50[0x4]; 10111 u8 num_of_tc_oper[0x4]; 10112 u8 reserved_at_58[0x4]; 10113 u8 num_of_tc_admin[0x4]; 10114 u8 remote_willing[0x1]; 10115 u8 reserved_at_61[3]; 10116 u8 remote_pfc_cap[4]; 10117 u8 reserved_at_68[0x14]; 10118 u8 remote_num_of_tc[0x4]; 10119 u8 reserved_at_80[0x18]; 10120 u8 error[0x8]; 10121 u8 reserved_at_a0[0x160]; 10122 }; 10123 10124 struct mlx5_ifc_lagc_bits { 10125 u8 reserved_at_0[0x1d]; 10126 u8 lag_state[0x3]; 10127 10128 u8 reserved_at_20[0x14]; 10129 u8 tx_remap_affinity_2[0x4]; 10130 u8 reserved_at_38[0x4]; 10131 u8 tx_remap_affinity_1[0x4]; 10132 }; 10133 10134 struct mlx5_ifc_create_lag_out_bits { 10135 u8 status[0x8]; 10136 u8 reserved_at_8[0x18]; 10137 10138 u8 syndrome[0x20]; 10139 10140 u8 reserved_at_40[0x40]; 10141 }; 10142 10143 struct mlx5_ifc_create_lag_in_bits { 10144 u8 opcode[0x10]; 10145 u8 reserved_at_10[0x10]; 10146 10147 u8 reserved_at_20[0x10]; 10148 u8 op_mod[0x10]; 10149 10150 struct mlx5_ifc_lagc_bits ctx; 10151 }; 10152 10153 struct mlx5_ifc_modify_lag_out_bits { 10154 u8 status[0x8]; 10155 u8 reserved_at_8[0x18]; 10156 10157 u8 syndrome[0x20]; 10158 10159 u8 reserved_at_40[0x40]; 10160 }; 10161 10162 struct mlx5_ifc_modify_lag_in_bits { 10163 u8 opcode[0x10]; 10164 u8 reserved_at_10[0x10]; 10165 10166 u8 reserved_at_20[0x10]; 10167 u8 op_mod[0x10]; 10168 10169 u8 reserved_at_40[0x20]; 10170 u8 field_select[0x20]; 10171 10172 struct mlx5_ifc_lagc_bits ctx; 10173 }; 10174 10175 struct mlx5_ifc_query_lag_out_bits { 10176 u8 status[0x8]; 10177 u8 reserved_at_8[0x18]; 10178 10179 u8 syndrome[0x20]; 10180 10181 struct mlx5_ifc_lagc_bits ctx; 10182 }; 10183 10184 struct mlx5_ifc_query_lag_in_bits { 10185 u8 opcode[0x10]; 10186 u8 reserved_at_10[0x10]; 10187 10188 u8 reserved_at_20[0x10]; 10189 u8 op_mod[0x10]; 10190 10191 u8 reserved_at_40[0x40]; 10192 }; 10193 10194 struct mlx5_ifc_destroy_lag_out_bits { 10195 u8 status[0x8]; 10196 u8 reserved_at_8[0x18]; 10197 10198 u8 syndrome[0x20]; 10199 10200 u8 reserved_at_40[0x40]; 10201 }; 10202 10203 struct mlx5_ifc_destroy_lag_in_bits { 10204 u8 opcode[0x10]; 10205 u8 reserved_at_10[0x10]; 10206 10207 u8 reserved_at_20[0x10]; 10208 u8 op_mod[0x10]; 10209 10210 u8 reserved_at_40[0x40]; 10211 }; 10212 10213 struct mlx5_ifc_create_vport_lag_out_bits { 10214 u8 status[0x8]; 10215 u8 reserved_at_8[0x18]; 10216 10217 u8 syndrome[0x20]; 10218 10219 u8 reserved_at_40[0x40]; 10220 }; 10221 10222 struct mlx5_ifc_create_vport_lag_in_bits { 10223 u8 opcode[0x10]; 10224 u8 reserved_at_10[0x10]; 10225 10226 u8 reserved_at_20[0x10]; 10227 u8 op_mod[0x10]; 10228 10229 u8 reserved_at_40[0x40]; 10230 }; 10231 10232 struct mlx5_ifc_destroy_vport_lag_out_bits { 10233 u8 status[0x8]; 10234 u8 reserved_at_8[0x18]; 10235 10236 u8 syndrome[0x20]; 10237 10238 u8 reserved_at_40[0x40]; 10239 }; 10240 10241 struct mlx5_ifc_destroy_vport_lag_in_bits { 10242 u8 opcode[0x10]; 10243 u8 reserved_at_10[0x10]; 10244 10245 u8 reserved_at_20[0x10]; 10246 u8 op_mod[0x10]; 10247 10248 u8 reserved_at_40[0x40]; 10249 }; 10250 10251 struct mlx5_ifc_alloc_memic_in_bits { 10252 u8 opcode[0x10]; 10253 u8 reserved_at_10[0x10]; 10254 10255 u8 reserved_at_20[0x10]; 10256 u8 op_mod[0x10]; 10257 10258 u8 reserved_at_30[0x20]; 10259 10260 u8 reserved_at_40[0x18]; 10261 u8 log_memic_addr_alignment[0x8]; 10262 10263 u8 range_start_addr[0x40]; 10264 10265 u8 range_size[0x20]; 10266 10267 u8 memic_size[0x20]; 10268 }; 10269 10270 struct mlx5_ifc_alloc_memic_out_bits { 10271 u8 status[0x8]; 10272 u8 reserved_at_8[0x18]; 10273 10274 u8 syndrome[0x20]; 10275 10276 u8 memic_start_addr[0x40]; 10277 }; 10278 10279 struct mlx5_ifc_dealloc_memic_in_bits { 10280 u8 opcode[0x10]; 10281 u8 reserved_at_10[0x10]; 10282 10283 u8 reserved_at_20[0x10]; 10284 u8 op_mod[0x10]; 10285 10286 u8 reserved_at_40[0x40]; 10287 10288 u8 memic_start_addr[0x40]; 10289 10290 u8 memic_size[0x20]; 10291 10292 u8 reserved_at_e0[0x20]; 10293 }; 10294 10295 struct mlx5_ifc_dealloc_memic_out_bits { 10296 u8 status[0x8]; 10297 u8 reserved_at_8[0x18]; 10298 10299 u8 syndrome[0x20]; 10300 10301 u8 reserved_at_40[0x40]; 10302 }; 10303 10304 struct mlx5_ifc_general_obj_in_cmd_hdr_bits { 10305 u8 opcode[0x10]; 10306 u8 uid[0x10]; 10307 10308 u8 vhca_tunnel_id[0x10]; 10309 u8 obj_type[0x10]; 10310 10311 u8 obj_id[0x20]; 10312 10313 u8 reserved_at_60[0x20]; 10314 }; 10315 10316 struct mlx5_ifc_general_obj_out_cmd_hdr_bits { 10317 u8 status[0x8]; 10318 u8 reserved_at_8[0x18]; 10319 10320 u8 syndrome[0x20]; 10321 10322 u8 obj_id[0x20]; 10323 10324 u8 reserved_at_60[0x20]; 10325 }; 10326 10327 struct mlx5_ifc_umem_bits { 10328 u8 reserved_at_0[0x80]; 10329 10330 u8 reserved_at_80[0x1b]; 10331 u8 log_page_size[0x5]; 10332 10333 u8 page_offset[0x20]; 10334 10335 u8 num_of_mtt[0x40]; 10336 10337 struct mlx5_ifc_mtt_bits mtt[]; 10338 }; 10339 10340 struct mlx5_ifc_uctx_bits { 10341 u8 cap[0x20]; 10342 10343 u8 reserved_at_20[0x160]; 10344 }; 10345 10346 struct mlx5_ifc_sw_icm_bits { 10347 u8 modify_field_select[0x40]; 10348 10349 u8 reserved_at_40[0x18]; 10350 u8 log_sw_icm_size[0x8]; 10351 10352 u8 reserved_at_60[0x20]; 10353 10354 u8 sw_icm_start_addr[0x40]; 10355 10356 u8 reserved_at_c0[0x140]; 10357 }; 10358 10359 struct mlx5_ifc_geneve_tlv_option_bits { 10360 u8 modify_field_select[0x40]; 10361 10362 u8 reserved_at_40[0x18]; 10363 u8 geneve_option_fte_index[0x8]; 10364 10365 u8 option_class[0x10]; 10366 u8 option_type[0x8]; 10367 u8 reserved_at_78[0x3]; 10368 u8 option_data_length[0x5]; 10369 10370 u8 reserved_at_80[0x180]; 10371 }; 10372 10373 struct mlx5_ifc_create_umem_in_bits { 10374 u8 opcode[0x10]; 10375 u8 uid[0x10]; 10376 10377 u8 reserved_at_20[0x10]; 10378 u8 op_mod[0x10]; 10379 10380 u8 reserved_at_40[0x40]; 10381 10382 struct mlx5_ifc_umem_bits umem; 10383 }; 10384 10385 struct mlx5_ifc_create_umem_out_bits { 10386 u8 status[0x8]; 10387 u8 reserved_at_8[0x18]; 10388 10389 u8 syndrome[0x20]; 10390 10391 u8 reserved_at_40[0x8]; 10392 u8 umem_id[0x18]; 10393 10394 u8 reserved_at_60[0x20]; 10395 }; 10396 10397 struct mlx5_ifc_destroy_umem_in_bits { 10398 u8 opcode[0x10]; 10399 u8 uid[0x10]; 10400 10401 u8 reserved_at_20[0x10]; 10402 u8 op_mod[0x10]; 10403 10404 u8 reserved_at_40[0x8]; 10405 u8 umem_id[0x18]; 10406 10407 u8 reserved_at_60[0x20]; 10408 }; 10409 10410 struct mlx5_ifc_destroy_umem_out_bits { 10411 u8 status[0x8]; 10412 u8 reserved_at_8[0x18]; 10413 10414 u8 syndrome[0x20]; 10415 10416 u8 reserved_at_40[0x40]; 10417 }; 10418 10419 struct mlx5_ifc_create_uctx_in_bits { 10420 u8 opcode[0x10]; 10421 u8 reserved_at_10[0x10]; 10422 10423 u8 reserved_at_20[0x10]; 10424 u8 op_mod[0x10]; 10425 10426 u8 reserved_at_40[0x40]; 10427 10428 struct mlx5_ifc_uctx_bits uctx; 10429 }; 10430 10431 struct mlx5_ifc_create_uctx_out_bits { 10432 u8 status[0x8]; 10433 u8 reserved_at_8[0x18]; 10434 10435 u8 syndrome[0x20]; 10436 10437 u8 reserved_at_40[0x10]; 10438 u8 uid[0x10]; 10439 10440 u8 reserved_at_60[0x20]; 10441 }; 10442 10443 struct mlx5_ifc_destroy_uctx_in_bits { 10444 u8 opcode[0x10]; 10445 u8 reserved_at_10[0x10]; 10446 10447 u8 reserved_at_20[0x10]; 10448 u8 op_mod[0x10]; 10449 10450 u8 reserved_at_40[0x10]; 10451 u8 uid[0x10]; 10452 10453 u8 reserved_at_60[0x20]; 10454 }; 10455 10456 struct mlx5_ifc_destroy_uctx_out_bits { 10457 u8 status[0x8]; 10458 u8 reserved_at_8[0x18]; 10459 10460 u8 syndrome[0x20]; 10461 10462 u8 reserved_at_40[0x40]; 10463 }; 10464 10465 struct mlx5_ifc_create_sw_icm_in_bits { 10466 struct mlx5_ifc_general_obj_in_cmd_hdr_bits hdr; 10467 struct mlx5_ifc_sw_icm_bits sw_icm; 10468 }; 10469 10470 struct mlx5_ifc_create_geneve_tlv_option_in_bits { 10471 struct mlx5_ifc_general_obj_in_cmd_hdr_bits hdr; 10472 struct mlx5_ifc_geneve_tlv_option_bits geneve_tlv_opt; 10473 }; 10474 10475 struct mlx5_ifc_mtrc_string_db_param_bits { 10476 u8 string_db_base_address[0x20]; 10477 10478 u8 reserved_at_20[0x8]; 10479 u8 string_db_size[0x18]; 10480 }; 10481 10482 struct mlx5_ifc_mtrc_cap_bits { 10483 u8 trace_owner[0x1]; 10484 u8 trace_to_memory[0x1]; 10485 u8 reserved_at_2[0x4]; 10486 u8 trc_ver[0x2]; 10487 u8 reserved_at_8[0x14]; 10488 u8 num_string_db[0x4]; 10489 10490 u8 first_string_trace[0x8]; 10491 u8 num_string_trace[0x8]; 10492 u8 reserved_at_30[0x28]; 10493 10494 u8 log_max_trace_buffer_size[0x8]; 10495 10496 u8 reserved_at_60[0x20]; 10497 10498 struct mlx5_ifc_mtrc_string_db_param_bits string_db_param[8]; 10499 10500 u8 reserved_at_280[0x180]; 10501 }; 10502 10503 struct mlx5_ifc_mtrc_conf_bits { 10504 u8 reserved_at_0[0x1c]; 10505 u8 trace_mode[0x4]; 10506 u8 reserved_at_20[0x18]; 10507 u8 log_trace_buffer_size[0x8]; 10508 u8 trace_mkey[0x20]; 10509 u8 reserved_at_60[0x3a0]; 10510 }; 10511 10512 struct mlx5_ifc_mtrc_stdb_bits { 10513 u8 string_db_index[0x4]; 10514 u8 reserved_at_4[0x4]; 10515 u8 read_size[0x18]; 10516 u8 start_offset[0x20]; 10517 u8 string_db_data[]; 10518 }; 10519 10520 struct mlx5_ifc_mtrc_ctrl_bits { 10521 u8 trace_status[0x2]; 10522 u8 reserved_at_2[0x2]; 10523 u8 arm_event[0x1]; 10524 u8 reserved_at_5[0xb]; 10525 u8 modify_field_select[0x10]; 10526 u8 reserved_at_20[0x2b]; 10527 u8 current_timestamp52_32[0x15]; 10528 u8 current_timestamp31_0[0x20]; 10529 u8 reserved_at_80[0x180]; 10530 }; 10531 10532 struct mlx5_ifc_host_params_context_bits { 10533 u8 host_number[0x8]; 10534 u8 reserved_at_8[0x7]; 10535 u8 host_pf_disabled[0x1]; 10536 u8 host_num_of_vfs[0x10]; 10537 10538 u8 host_total_vfs[0x10]; 10539 u8 host_pci_bus[0x10]; 10540 10541 u8 reserved_at_40[0x10]; 10542 u8 host_pci_device[0x10]; 10543 10544 u8 reserved_at_60[0x10]; 10545 u8 host_pci_function[0x10]; 10546 10547 u8 reserved_at_80[0x180]; 10548 }; 10549 10550 struct mlx5_ifc_query_esw_functions_in_bits { 10551 u8 opcode[0x10]; 10552 u8 reserved_at_10[0x10]; 10553 10554 u8 reserved_at_20[0x10]; 10555 u8 op_mod[0x10]; 10556 10557 u8 reserved_at_40[0x40]; 10558 }; 10559 10560 struct mlx5_ifc_query_esw_functions_out_bits { 10561 u8 status[0x8]; 10562 u8 reserved_at_8[0x18]; 10563 10564 u8 syndrome[0x20]; 10565 10566 u8 reserved_at_40[0x40]; 10567 10568 struct mlx5_ifc_host_params_context_bits host_params_context; 10569 10570 u8 reserved_at_280[0x180]; 10571 u8 host_sf_enable[][0x40]; 10572 }; 10573 10574 struct mlx5_ifc_sf_partition_bits { 10575 u8 reserved_at_0[0x10]; 10576 u8 log_num_sf[0x8]; 10577 u8 log_sf_bar_size[0x8]; 10578 }; 10579 10580 struct mlx5_ifc_query_sf_partitions_out_bits { 10581 u8 status[0x8]; 10582 u8 reserved_at_8[0x18]; 10583 10584 u8 syndrome[0x20]; 10585 10586 u8 reserved_at_40[0x18]; 10587 u8 num_sf_partitions[0x8]; 10588 10589 u8 reserved_at_60[0x20]; 10590 10591 struct mlx5_ifc_sf_partition_bits sf_partition[]; 10592 }; 10593 10594 struct mlx5_ifc_query_sf_partitions_in_bits { 10595 u8 opcode[0x10]; 10596 u8 reserved_at_10[0x10]; 10597 10598 u8 reserved_at_20[0x10]; 10599 u8 op_mod[0x10]; 10600 10601 u8 reserved_at_40[0x40]; 10602 }; 10603 10604 struct mlx5_ifc_dealloc_sf_out_bits { 10605 u8 status[0x8]; 10606 u8 reserved_at_8[0x18]; 10607 10608 u8 syndrome[0x20]; 10609 10610 u8 reserved_at_40[0x40]; 10611 }; 10612 10613 struct mlx5_ifc_dealloc_sf_in_bits { 10614 u8 opcode[0x10]; 10615 u8 reserved_at_10[0x10]; 10616 10617 u8 reserved_at_20[0x10]; 10618 u8 op_mod[0x10]; 10619 10620 u8 reserved_at_40[0x10]; 10621 u8 function_id[0x10]; 10622 10623 u8 reserved_at_60[0x20]; 10624 }; 10625 10626 struct mlx5_ifc_alloc_sf_out_bits { 10627 u8 status[0x8]; 10628 u8 reserved_at_8[0x18]; 10629 10630 u8 syndrome[0x20]; 10631 10632 u8 reserved_at_40[0x40]; 10633 }; 10634 10635 struct mlx5_ifc_alloc_sf_in_bits { 10636 u8 opcode[0x10]; 10637 u8 reserved_at_10[0x10]; 10638 10639 u8 reserved_at_20[0x10]; 10640 u8 op_mod[0x10]; 10641 10642 u8 reserved_at_40[0x10]; 10643 u8 function_id[0x10]; 10644 10645 u8 reserved_at_60[0x20]; 10646 }; 10647 10648 struct mlx5_ifc_affiliated_event_header_bits { 10649 u8 reserved_at_0[0x10]; 10650 u8 obj_type[0x10]; 10651 10652 u8 obj_id[0x20]; 10653 }; 10654 10655 enum { 10656 MLX5_HCA_CAP_GENERAL_OBJECT_TYPES_ENCRYPTION_KEY = BIT(0xc), 10657 MLX5_HCA_CAP_GENERAL_OBJECT_TYPES_IPSEC = BIT(0x13), 10658 }; 10659 10660 enum { 10661 MLX5_GENERAL_OBJECT_TYPES_ENCRYPTION_KEY = 0xc, 10662 MLX5_GENERAL_OBJECT_TYPES_IPSEC = 0x13, 10663 }; 10664 10665 enum { 10666 MLX5_IPSEC_OBJECT_ICV_LEN_16B, 10667 MLX5_IPSEC_OBJECT_ICV_LEN_12B, 10668 MLX5_IPSEC_OBJECT_ICV_LEN_8B, 10669 }; 10670 10671 struct mlx5_ifc_ipsec_obj_bits { 10672 u8 modify_field_select[0x40]; 10673 u8 full_offload[0x1]; 10674 u8 reserved_at_41[0x1]; 10675 u8 esn_en[0x1]; 10676 u8 esn_overlap[0x1]; 10677 u8 reserved_at_44[0x2]; 10678 u8 icv_length[0x2]; 10679 u8 reserved_at_48[0x4]; 10680 u8 aso_return_reg[0x4]; 10681 u8 reserved_at_50[0x10]; 10682 10683 u8 esn_msb[0x20]; 10684 10685 u8 reserved_at_80[0x8]; 10686 u8 dekn[0x18]; 10687 10688 u8 salt[0x20]; 10689 10690 u8 implicit_iv[0x40]; 10691 10692 u8 reserved_at_100[0x700]; 10693 }; 10694 10695 struct mlx5_ifc_create_ipsec_obj_in_bits { 10696 struct mlx5_ifc_general_obj_in_cmd_hdr_bits general_obj_in_cmd_hdr; 10697 struct mlx5_ifc_ipsec_obj_bits ipsec_object; 10698 }; 10699 10700 enum { 10701 MLX5_MODIFY_IPSEC_BITMASK_ESN_OVERLAP = BIT(0), 10702 MLX5_MODIFY_IPSEC_BITMASK_ESN_MSB = BIT(1), 10703 }; 10704 10705 struct mlx5_ifc_query_ipsec_obj_out_bits { 10706 struct mlx5_ifc_general_obj_out_cmd_hdr_bits general_obj_out_cmd_hdr; 10707 struct mlx5_ifc_ipsec_obj_bits ipsec_object; 10708 }; 10709 10710 struct mlx5_ifc_modify_ipsec_obj_in_bits { 10711 struct mlx5_ifc_general_obj_in_cmd_hdr_bits general_obj_in_cmd_hdr; 10712 struct mlx5_ifc_ipsec_obj_bits ipsec_object; 10713 }; 10714 10715 struct mlx5_ifc_encryption_key_obj_bits { 10716 u8 modify_field_select[0x40]; 10717 10718 u8 reserved_at_40[0x14]; 10719 u8 key_size[0x4]; 10720 u8 reserved_at_58[0x4]; 10721 u8 key_type[0x4]; 10722 10723 u8 reserved_at_60[0x8]; 10724 u8 pd[0x18]; 10725 10726 u8 reserved_at_80[0x180]; 10727 u8 key[8][0x20]; 10728 10729 u8 reserved_at_300[0x500]; 10730 }; 10731 10732 struct mlx5_ifc_create_encryption_key_in_bits { 10733 struct mlx5_ifc_general_obj_in_cmd_hdr_bits general_obj_in_cmd_hdr; 10734 struct mlx5_ifc_encryption_key_obj_bits encryption_key_object; 10735 }; 10736 10737 enum { 10738 MLX5_GENERAL_OBJECT_TYPE_ENCRYPTION_KEY_KEY_SIZE_128 = 0x0, 10739 MLX5_GENERAL_OBJECT_TYPE_ENCRYPTION_KEY_KEY_SIZE_256 = 0x1, 10740 }; 10741 10742 enum { 10743 MLX5_GENERAL_OBJECT_TYPE_ENCRYPTION_KEY_TYPE_TLS = 0x1, 10744 MLX5_GENERAL_OBJECT_TYPE_ENCRYPTION_KEY_TYPE_IPSEC = 0x2, 10745 }; 10746 10747 struct mlx5_ifc_tls_static_params_bits { 10748 u8 const_2[0x2]; 10749 u8 tls_version[0x4]; 10750 u8 const_1[0x2]; 10751 u8 reserved_at_8[0x14]; 10752 u8 encryption_standard[0x4]; 10753 10754 u8 reserved_at_20[0x20]; 10755 10756 u8 initial_record_number[0x40]; 10757 10758 u8 resync_tcp_sn[0x20]; 10759 10760 u8 gcm_iv[0x20]; 10761 10762 u8 implicit_iv[0x40]; 10763 10764 u8 reserved_at_100[0x8]; 10765 u8 dek_index[0x18]; 10766 10767 u8 reserved_at_120[0xe0]; 10768 }; 10769 10770 struct mlx5_ifc_tls_progress_params_bits { 10771 u8 next_record_tcp_sn[0x20]; 10772 10773 u8 hw_resync_tcp_sn[0x20]; 10774 10775 u8 record_tracker_state[0x2]; 10776 u8 auth_state[0x2]; 10777 u8 reserved_at_44[0x4]; 10778 u8 hw_offset_record_number[0x18]; 10779 }; 10780 10781 enum { 10782 MLX5_MTT_PERM_READ = 1 << 0, 10783 MLX5_MTT_PERM_WRITE = 1 << 1, 10784 MLX5_MTT_PERM_RW = MLX5_MTT_PERM_READ | MLX5_MTT_PERM_WRITE, 10785 }; 10786 10787 #endif /* MLX5_IFC_H */ 10788