1 /* 2 * Copyright (c) 2013-2015, Mellanox Technologies, Ltd. All rights reserved. 3 * 4 * This software is available to you under a choice of one of two 5 * licenses. You may choose to be licensed under the terms of the GNU 6 * General Public License (GPL) Version 2, available from the file 7 * COPYING in the main directory of this source tree, or the 8 * OpenIB.org BSD license below: 9 * 10 * Redistribution and use in source and binary forms, with or 11 * without modification, are permitted provided that the following 12 * conditions are met: 13 * 14 * - Redistributions of source code must retain the above 15 * copyright notice, this list of conditions and the following 16 * disclaimer. 17 * 18 * - Redistributions in binary form must reproduce the above 19 * copyright notice, this list of conditions and the following 20 * disclaimer in the documentation and/or other materials 21 * provided with the distribution. 22 * 23 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, 24 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF 25 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND 26 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS 27 * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN 28 * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN 29 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE 30 * SOFTWARE. 31 */ 32 #ifndef MLX5_IFC_H 33 #define MLX5_IFC_H 34 35 #include "mlx5_ifc_fpga.h" 36 37 enum { 38 MLX5_EVENT_TYPE_CODING_COMPLETION_EVENTS = 0x0, 39 MLX5_EVENT_TYPE_CODING_PATH_MIGRATED_SUCCEEDED = 0x1, 40 MLX5_EVENT_TYPE_CODING_COMMUNICATION_ESTABLISHED = 0x2, 41 MLX5_EVENT_TYPE_CODING_SEND_QUEUE_DRAINED = 0x3, 42 MLX5_EVENT_TYPE_CODING_LAST_WQE_REACHED = 0x13, 43 MLX5_EVENT_TYPE_CODING_SRQ_LIMIT = 0x14, 44 MLX5_EVENT_TYPE_CODING_DCT_ALL_CONNECTIONS_CLOSED = 0x1c, 45 MLX5_EVENT_TYPE_CODING_DCT_ACCESS_KEY_VIOLATION = 0x1d, 46 MLX5_EVENT_TYPE_CODING_CQ_ERROR = 0x4, 47 MLX5_EVENT_TYPE_CODING_LOCAL_WQ_CATASTROPHIC_ERROR = 0x5, 48 MLX5_EVENT_TYPE_CODING_PATH_MIGRATION_FAILED = 0x7, 49 MLX5_EVENT_TYPE_CODING_PAGE_FAULT_EVENT = 0xc, 50 MLX5_EVENT_TYPE_CODING_INVALID_REQUEST_LOCAL_WQ_ERROR = 0x10, 51 MLX5_EVENT_TYPE_CODING_LOCAL_ACCESS_VIOLATION_WQ_ERROR = 0x11, 52 MLX5_EVENT_TYPE_CODING_LOCAL_SRQ_CATASTROPHIC_ERROR = 0x12, 53 MLX5_EVENT_TYPE_CODING_INTERNAL_ERROR = 0x8, 54 MLX5_EVENT_TYPE_CODING_PORT_STATE_CHANGE = 0x9, 55 MLX5_EVENT_TYPE_CODING_GPIO_EVENT = 0x15, 56 MLX5_EVENT_TYPE_CODING_REMOTE_CONFIGURATION_PROTOCOL_EVENT = 0x19, 57 MLX5_EVENT_TYPE_CODING_DOORBELL_BLUEFLAME_CONGESTION_EVENT = 0x1a, 58 MLX5_EVENT_TYPE_CODING_STALL_VL_EVENT = 0x1b, 59 MLX5_EVENT_TYPE_CODING_DROPPED_PACKET_LOGGED_EVENT = 0x1f, 60 MLX5_EVENT_TYPE_CODING_COMMAND_INTERFACE_COMPLETION = 0xa, 61 MLX5_EVENT_TYPE_CODING_PAGE_REQUEST = 0xb, 62 MLX5_EVENT_TYPE_CODING_FPGA_ERROR = 0x20, 63 }; 64 65 enum { 66 MLX5_MODIFY_TIR_BITMASK_LRO = 0x0, 67 MLX5_MODIFY_TIR_BITMASK_INDIRECT_TABLE = 0x1, 68 MLX5_MODIFY_TIR_BITMASK_HASH = 0x2, 69 MLX5_MODIFY_TIR_BITMASK_TUNNELED_OFFLOAD_EN = 0x3 70 }; 71 72 enum { 73 MLX5_SET_HCA_CAP_OP_MOD_GENERAL_DEVICE = 0x0, 74 MLX5_SET_HCA_CAP_OP_MOD_ATOMIC = 0x3, 75 }; 76 77 enum { 78 MLX5_CMD_OP_QUERY_HCA_CAP = 0x100, 79 MLX5_CMD_OP_QUERY_ADAPTER = 0x101, 80 MLX5_CMD_OP_INIT_HCA = 0x102, 81 MLX5_CMD_OP_TEARDOWN_HCA = 0x103, 82 MLX5_CMD_OP_ENABLE_HCA = 0x104, 83 MLX5_CMD_OP_DISABLE_HCA = 0x105, 84 MLX5_CMD_OP_QUERY_PAGES = 0x107, 85 MLX5_CMD_OP_MANAGE_PAGES = 0x108, 86 MLX5_CMD_OP_SET_HCA_CAP = 0x109, 87 MLX5_CMD_OP_QUERY_ISSI = 0x10a, 88 MLX5_CMD_OP_SET_ISSI = 0x10b, 89 MLX5_CMD_OP_SET_DRIVER_VERSION = 0x10d, 90 MLX5_CMD_OP_CREATE_MKEY = 0x200, 91 MLX5_CMD_OP_QUERY_MKEY = 0x201, 92 MLX5_CMD_OP_DESTROY_MKEY = 0x202, 93 MLX5_CMD_OP_QUERY_SPECIAL_CONTEXTS = 0x203, 94 MLX5_CMD_OP_PAGE_FAULT_RESUME = 0x204, 95 MLX5_CMD_OP_CREATE_EQ = 0x301, 96 MLX5_CMD_OP_DESTROY_EQ = 0x302, 97 MLX5_CMD_OP_QUERY_EQ = 0x303, 98 MLX5_CMD_OP_GEN_EQE = 0x304, 99 MLX5_CMD_OP_CREATE_CQ = 0x400, 100 MLX5_CMD_OP_DESTROY_CQ = 0x401, 101 MLX5_CMD_OP_QUERY_CQ = 0x402, 102 MLX5_CMD_OP_MODIFY_CQ = 0x403, 103 MLX5_CMD_OP_CREATE_QP = 0x500, 104 MLX5_CMD_OP_DESTROY_QP = 0x501, 105 MLX5_CMD_OP_RST2INIT_QP = 0x502, 106 MLX5_CMD_OP_INIT2RTR_QP = 0x503, 107 MLX5_CMD_OP_RTR2RTS_QP = 0x504, 108 MLX5_CMD_OP_RTS2RTS_QP = 0x505, 109 MLX5_CMD_OP_SQERR2RTS_QP = 0x506, 110 MLX5_CMD_OP_2ERR_QP = 0x507, 111 MLX5_CMD_OP_2RST_QP = 0x50a, 112 MLX5_CMD_OP_QUERY_QP = 0x50b, 113 MLX5_CMD_OP_SQD_RTS_QP = 0x50c, 114 MLX5_CMD_OP_INIT2INIT_QP = 0x50e, 115 MLX5_CMD_OP_CREATE_PSV = 0x600, 116 MLX5_CMD_OP_DESTROY_PSV = 0x601, 117 MLX5_CMD_OP_CREATE_SRQ = 0x700, 118 MLX5_CMD_OP_DESTROY_SRQ = 0x701, 119 MLX5_CMD_OP_QUERY_SRQ = 0x702, 120 MLX5_CMD_OP_ARM_RQ = 0x703, 121 MLX5_CMD_OP_CREATE_XRC_SRQ = 0x705, 122 MLX5_CMD_OP_DESTROY_XRC_SRQ = 0x706, 123 MLX5_CMD_OP_QUERY_XRC_SRQ = 0x707, 124 MLX5_CMD_OP_ARM_XRC_SRQ = 0x708, 125 MLX5_CMD_OP_CREATE_DCT = 0x710, 126 MLX5_CMD_OP_DESTROY_DCT = 0x711, 127 MLX5_CMD_OP_DRAIN_DCT = 0x712, 128 MLX5_CMD_OP_QUERY_DCT = 0x713, 129 MLX5_CMD_OP_ARM_DCT_FOR_KEY_VIOLATION = 0x714, 130 MLX5_CMD_OP_CREATE_XRQ = 0x717, 131 MLX5_CMD_OP_DESTROY_XRQ = 0x718, 132 MLX5_CMD_OP_QUERY_XRQ = 0x719, 133 MLX5_CMD_OP_ARM_XRQ = 0x71a, 134 MLX5_CMD_OP_QUERY_VPORT_STATE = 0x750, 135 MLX5_CMD_OP_MODIFY_VPORT_STATE = 0x751, 136 MLX5_CMD_OP_QUERY_ESW_VPORT_CONTEXT = 0x752, 137 MLX5_CMD_OP_MODIFY_ESW_VPORT_CONTEXT = 0x753, 138 MLX5_CMD_OP_QUERY_NIC_VPORT_CONTEXT = 0x754, 139 MLX5_CMD_OP_MODIFY_NIC_VPORT_CONTEXT = 0x755, 140 MLX5_CMD_OP_QUERY_ROCE_ADDRESS = 0x760, 141 MLX5_CMD_OP_SET_ROCE_ADDRESS = 0x761, 142 MLX5_CMD_OP_QUERY_HCA_VPORT_CONTEXT = 0x762, 143 MLX5_CMD_OP_MODIFY_HCA_VPORT_CONTEXT = 0x763, 144 MLX5_CMD_OP_QUERY_HCA_VPORT_GID = 0x764, 145 MLX5_CMD_OP_QUERY_HCA_VPORT_PKEY = 0x765, 146 MLX5_CMD_OP_QUERY_VPORT_COUNTER = 0x770, 147 MLX5_CMD_OP_ALLOC_Q_COUNTER = 0x771, 148 MLX5_CMD_OP_DEALLOC_Q_COUNTER = 0x772, 149 MLX5_CMD_OP_QUERY_Q_COUNTER = 0x773, 150 MLX5_CMD_OP_SET_PP_RATE_LIMIT = 0x780, 151 MLX5_CMD_OP_QUERY_RATE_LIMIT = 0x781, 152 MLX5_CMD_OP_CREATE_SCHEDULING_ELEMENT = 0x782, 153 MLX5_CMD_OP_DESTROY_SCHEDULING_ELEMENT = 0x783, 154 MLX5_CMD_OP_QUERY_SCHEDULING_ELEMENT = 0x784, 155 MLX5_CMD_OP_MODIFY_SCHEDULING_ELEMENT = 0x785, 156 MLX5_CMD_OP_CREATE_QOS_PARA_VPORT = 0x786, 157 MLX5_CMD_OP_DESTROY_QOS_PARA_VPORT = 0x787, 158 MLX5_CMD_OP_ALLOC_PD = 0x800, 159 MLX5_CMD_OP_DEALLOC_PD = 0x801, 160 MLX5_CMD_OP_ALLOC_UAR = 0x802, 161 MLX5_CMD_OP_DEALLOC_UAR = 0x803, 162 MLX5_CMD_OP_CONFIG_INT_MODERATION = 0x804, 163 MLX5_CMD_OP_ACCESS_REG = 0x805, 164 MLX5_CMD_OP_ATTACH_TO_MCG = 0x806, 165 MLX5_CMD_OP_DETACH_FROM_MCG = 0x807, 166 MLX5_CMD_OP_GET_DROPPED_PACKET_LOG = 0x80a, 167 MLX5_CMD_OP_MAD_IFC = 0x50d, 168 MLX5_CMD_OP_QUERY_MAD_DEMUX = 0x80b, 169 MLX5_CMD_OP_SET_MAD_DEMUX = 0x80c, 170 MLX5_CMD_OP_NOP = 0x80d, 171 MLX5_CMD_OP_ALLOC_XRCD = 0x80e, 172 MLX5_CMD_OP_DEALLOC_XRCD = 0x80f, 173 MLX5_CMD_OP_ALLOC_TRANSPORT_DOMAIN = 0x816, 174 MLX5_CMD_OP_DEALLOC_TRANSPORT_DOMAIN = 0x817, 175 MLX5_CMD_OP_QUERY_CONG_STATUS = 0x822, 176 MLX5_CMD_OP_MODIFY_CONG_STATUS = 0x823, 177 MLX5_CMD_OP_QUERY_CONG_PARAMS = 0x824, 178 MLX5_CMD_OP_MODIFY_CONG_PARAMS = 0x825, 179 MLX5_CMD_OP_QUERY_CONG_STATISTICS = 0x826, 180 MLX5_CMD_OP_ADD_VXLAN_UDP_DPORT = 0x827, 181 MLX5_CMD_OP_DELETE_VXLAN_UDP_DPORT = 0x828, 182 MLX5_CMD_OP_SET_L2_TABLE_ENTRY = 0x829, 183 MLX5_CMD_OP_QUERY_L2_TABLE_ENTRY = 0x82a, 184 MLX5_CMD_OP_DELETE_L2_TABLE_ENTRY = 0x82b, 185 MLX5_CMD_OP_SET_WOL_ROL = 0x830, 186 MLX5_CMD_OP_QUERY_WOL_ROL = 0x831, 187 MLX5_CMD_OP_CREATE_LAG = 0x840, 188 MLX5_CMD_OP_MODIFY_LAG = 0x841, 189 MLX5_CMD_OP_QUERY_LAG = 0x842, 190 MLX5_CMD_OP_DESTROY_LAG = 0x843, 191 MLX5_CMD_OP_CREATE_VPORT_LAG = 0x844, 192 MLX5_CMD_OP_DESTROY_VPORT_LAG = 0x845, 193 MLX5_CMD_OP_CREATE_TIR = 0x900, 194 MLX5_CMD_OP_MODIFY_TIR = 0x901, 195 MLX5_CMD_OP_DESTROY_TIR = 0x902, 196 MLX5_CMD_OP_QUERY_TIR = 0x903, 197 MLX5_CMD_OP_CREATE_SQ = 0x904, 198 MLX5_CMD_OP_MODIFY_SQ = 0x905, 199 MLX5_CMD_OP_DESTROY_SQ = 0x906, 200 MLX5_CMD_OP_QUERY_SQ = 0x907, 201 MLX5_CMD_OP_CREATE_RQ = 0x908, 202 MLX5_CMD_OP_MODIFY_RQ = 0x909, 203 MLX5_CMD_OP_SET_DELAY_DROP_PARAMS = 0x910, 204 MLX5_CMD_OP_DESTROY_RQ = 0x90a, 205 MLX5_CMD_OP_QUERY_RQ = 0x90b, 206 MLX5_CMD_OP_CREATE_RMP = 0x90c, 207 MLX5_CMD_OP_MODIFY_RMP = 0x90d, 208 MLX5_CMD_OP_DESTROY_RMP = 0x90e, 209 MLX5_CMD_OP_QUERY_RMP = 0x90f, 210 MLX5_CMD_OP_CREATE_TIS = 0x912, 211 MLX5_CMD_OP_MODIFY_TIS = 0x913, 212 MLX5_CMD_OP_DESTROY_TIS = 0x914, 213 MLX5_CMD_OP_QUERY_TIS = 0x915, 214 MLX5_CMD_OP_CREATE_RQT = 0x916, 215 MLX5_CMD_OP_MODIFY_RQT = 0x917, 216 MLX5_CMD_OP_DESTROY_RQT = 0x918, 217 MLX5_CMD_OP_QUERY_RQT = 0x919, 218 MLX5_CMD_OP_SET_FLOW_TABLE_ROOT = 0x92f, 219 MLX5_CMD_OP_CREATE_FLOW_TABLE = 0x930, 220 MLX5_CMD_OP_DESTROY_FLOW_TABLE = 0x931, 221 MLX5_CMD_OP_QUERY_FLOW_TABLE = 0x932, 222 MLX5_CMD_OP_CREATE_FLOW_GROUP = 0x933, 223 MLX5_CMD_OP_DESTROY_FLOW_GROUP = 0x934, 224 MLX5_CMD_OP_QUERY_FLOW_GROUP = 0x935, 225 MLX5_CMD_OP_SET_FLOW_TABLE_ENTRY = 0x936, 226 MLX5_CMD_OP_QUERY_FLOW_TABLE_ENTRY = 0x937, 227 MLX5_CMD_OP_DELETE_FLOW_TABLE_ENTRY = 0x938, 228 MLX5_CMD_OP_ALLOC_FLOW_COUNTER = 0x939, 229 MLX5_CMD_OP_DEALLOC_FLOW_COUNTER = 0x93a, 230 MLX5_CMD_OP_QUERY_FLOW_COUNTER = 0x93b, 231 MLX5_CMD_OP_MODIFY_FLOW_TABLE = 0x93c, 232 MLX5_CMD_OP_ALLOC_ENCAP_HEADER = 0x93d, 233 MLX5_CMD_OP_DEALLOC_ENCAP_HEADER = 0x93e, 234 MLX5_CMD_OP_ALLOC_MODIFY_HEADER_CONTEXT = 0x940, 235 MLX5_CMD_OP_DEALLOC_MODIFY_HEADER_CONTEXT = 0x941, 236 MLX5_CMD_OP_FPGA_CREATE_QP = 0x960, 237 MLX5_CMD_OP_FPGA_MODIFY_QP = 0x961, 238 MLX5_CMD_OP_FPGA_QUERY_QP = 0x962, 239 MLX5_CMD_OP_FPGA_DESTROY_QP = 0x963, 240 MLX5_CMD_OP_FPGA_QUERY_QP_COUNTERS = 0x964, 241 MLX5_CMD_OP_MAX 242 }; 243 244 struct mlx5_ifc_flow_table_fields_supported_bits { 245 u8 outer_dmac[0x1]; 246 u8 outer_smac[0x1]; 247 u8 outer_ether_type[0x1]; 248 u8 outer_ip_version[0x1]; 249 u8 outer_first_prio[0x1]; 250 u8 outer_first_cfi[0x1]; 251 u8 outer_first_vid[0x1]; 252 u8 outer_ipv4_ttl[0x1]; 253 u8 outer_second_prio[0x1]; 254 u8 outer_second_cfi[0x1]; 255 u8 outer_second_vid[0x1]; 256 u8 reserved_at_b[0x1]; 257 u8 outer_sip[0x1]; 258 u8 outer_dip[0x1]; 259 u8 outer_frag[0x1]; 260 u8 outer_ip_protocol[0x1]; 261 u8 outer_ip_ecn[0x1]; 262 u8 outer_ip_dscp[0x1]; 263 u8 outer_udp_sport[0x1]; 264 u8 outer_udp_dport[0x1]; 265 u8 outer_tcp_sport[0x1]; 266 u8 outer_tcp_dport[0x1]; 267 u8 outer_tcp_flags[0x1]; 268 u8 outer_gre_protocol[0x1]; 269 u8 outer_gre_key[0x1]; 270 u8 outer_vxlan_vni[0x1]; 271 u8 reserved_at_1a[0x5]; 272 u8 source_eswitch_port[0x1]; 273 274 u8 inner_dmac[0x1]; 275 u8 inner_smac[0x1]; 276 u8 inner_ether_type[0x1]; 277 u8 inner_ip_version[0x1]; 278 u8 inner_first_prio[0x1]; 279 u8 inner_first_cfi[0x1]; 280 u8 inner_first_vid[0x1]; 281 u8 reserved_at_27[0x1]; 282 u8 inner_second_prio[0x1]; 283 u8 inner_second_cfi[0x1]; 284 u8 inner_second_vid[0x1]; 285 u8 reserved_at_2b[0x1]; 286 u8 inner_sip[0x1]; 287 u8 inner_dip[0x1]; 288 u8 inner_frag[0x1]; 289 u8 inner_ip_protocol[0x1]; 290 u8 inner_ip_ecn[0x1]; 291 u8 inner_ip_dscp[0x1]; 292 u8 inner_udp_sport[0x1]; 293 u8 inner_udp_dport[0x1]; 294 u8 inner_tcp_sport[0x1]; 295 u8 inner_tcp_dport[0x1]; 296 u8 inner_tcp_flags[0x1]; 297 u8 reserved_at_37[0x9]; 298 u8 reserved_at_40[0x1a]; 299 u8 bth_dst_qp[0x1]; 300 301 u8 reserved_at_5b[0x25]; 302 }; 303 304 struct mlx5_ifc_flow_table_prop_layout_bits { 305 u8 ft_support[0x1]; 306 u8 reserved_at_1[0x1]; 307 u8 flow_counter[0x1]; 308 u8 flow_modify_en[0x1]; 309 u8 modify_root[0x1]; 310 u8 identified_miss_table_mode[0x1]; 311 u8 flow_table_modify[0x1]; 312 u8 encap[0x1]; 313 u8 decap[0x1]; 314 u8 reserved_at_9[0x17]; 315 316 u8 reserved_at_20[0x2]; 317 u8 log_max_ft_size[0x6]; 318 u8 log_max_modify_header_context[0x8]; 319 u8 max_modify_header_actions[0x8]; 320 u8 max_ft_level[0x8]; 321 322 u8 reserved_at_40[0x20]; 323 324 u8 reserved_at_60[0x18]; 325 u8 log_max_ft_num[0x8]; 326 327 u8 reserved_at_80[0x18]; 328 u8 log_max_destination[0x8]; 329 330 u8 log_max_flow_counter[0x8]; 331 u8 reserved_at_a8[0x10]; 332 u8 log_max_flow[0x8]; 333 334 u8 reserved_at_c0[0x40]; 335 336 struct mlx5_ifc_flow_table_fields_supported_bits ft_field_support; 337 338 struct mlx5_ifc_flow_table_fields_supported_bits ft_field_bitmask_support; 339 }; 340 341 struct mlx5_ifc_odp_per_transport_service_cap_bits { 342 u8 send[0x1]; 343 u8 receive[0x1]; 344 u8 write[0x1]; 345 u8 read[0x1]; 346 u8 atomic[0x1]; 347 u8 srq_receive[0x1]; 348 u8 reserved_at_6[0x1a]; 349 }; 350 351 struct mlx5_ifc_ipv4_layout_bits { 352 u8 reserved_at_0[0x60]; 353 354 u8 ipv4[0x20]; 355 }; 356 357 struct mlx5_ifc_ipv6_layout_bits { 358 u8 ipv6[16][0x8]; 359 }; 360 361 union mlx5_ifc_ipv6_layout_ipv4_layout_auto_bits { 362 struct mlx5_ifc_ipv6_layout_bits ipv6_layout; 363 struct mlx5_ifc_ipv4_layout_bits ipv4_layout; 364 u8 reserved_at_0[0x80]; 365 }; 366 367 struct mlx5_ifc_fte_match_set_lyr_2_4_bits { 368 u8 smac_47_16[0x20]; 369 370 u8 smac_15_0[0x10]; 371 u8 ethertype[0x10]; 372 373 u8 dmac_47_16[0x20]; 374 375 u8 dmac_15_0[0x10]; 376 u8 first_prio[0x3]; 377 u8 first_cfi[0x1]; 378 u8 first_vid[0xc]; 379 380 u8 ip_protocol[0x8]; 381 u8 ip_dscp[0x6]; 382 u8 ip_ecn[0x2]; 383 u8 cvlan_tag[0x1]; 384 u8 svlan_tag[0x1]; 385 u8 frag[0x1]; 386 u8 ip_version[0x4]; 387 u8 tcp_flags[0x9]; 388 389 u8 tcp_sport[0x10]; 390 u8 tcp_dport[0x10]; 391 392 u8 reserved_at_c0[0x18]; 393 u8 ttl_hoplimit[0x8]; 394 395 u8 udp_sport[0x10]; 396 u8 udp_dport[0x10]; 397 398 union mlx5_ifc_ipv6_layout_ipv4_layout_auto_bits src_ipv4_src_ipv6; 399 400 union mlx5_ifc_ipv6_layout_ipv4_layout_auto_bits dst_ipv4_dst_ipv6; 401 }; 402 403 struct mlx5_ifc_fte_match_set_misc_bits { 404 u8 reserved_at_0[0x8]; 405 u8 source_sqn[0x18]; 406 407 u8 reserved_at_20[0x10]; 408 u8 source_port[0x10]; 409 410 u8 outer_second_prio[0x3]; 411 u8 outer_second_cfi[0x1]; 412 u8 outer_second_vid[0xc]; 413 u8 inner_second_prio[0x3]; 414 u8 inner_second_cfi[0x1]; 415 u8 inner_second_vid[0xc]; 416 417 u8 outer_second_cvlan_tag[0x1]; 418 u8 inner_second_cvlan_tag[0x1]; 419 u8 outer_second_svlan_tag[0x1]; 420 u8 inner_second_svlan_tag[0x1]; 421 u8 reserved_at_64[0xc]; 422 u8 gre_protocol[0x10]; 423 424 u8 gre_key_h[0x18]; 425 u8 gre_key_l[0x8]; 426 427 u8 vxlan_vni[0x18]; 428 u8 reserved_at_b8[0x8]; 429 430 u8 reserved_at_c0[0x20]; 431 432 u8 reserved_at_e0[0xc]; 433 u8 outer_ipv6_flow_label[0x14]; 434 435 u8 reserved_at_100[0xc]; 436 u8 inner_ipv6_flow_label[0x14]; 437 438 u8 reserved_at_120[0x28]; 439 u8 bth_dst_qp[0x18]; 440 u8 reserved_at_160[0xa0]; 441 }; 442 443 struct mlx5_ifc_cmd_pas_bits { 444 u8 pa_h[0x20]; 445 446 u8 pa_l[0x14]; 447 u8 reserved_at_34[0xc]; 448 }; 449 450 struct mlx5_ifc_uint64_bits { 451 u8 hi[0x20]; 452 453 u8 lo[0x20]; 454 }; 455 456 enum { 457 MLX5_ADS_STAT_RATE_NO_LIMIT = 0x0, 458 MLX5_ADS_STAT_RATE_2_5GBPS = 0x7, 459 MLX5_ADS_STAT_RATE_10GBPS = 0x8, 460 MLX5_ADS_STAT_RATE_30GBPS = 0x9, 461 MLX5_ADS_STAT_RATE_5GBPS = 0xa, 462 MLX5_ADS_STAT_RATE_20GBPS = 0xb, 463 MLX5_ADS_STAT_RATE_40GBPS = 0xc, 464 MLX5_ADS_STAT_RATE_60GBPS = 0xd, 465 MLX5_ADS_STAT_RATE_80GBPS = 0xe, 466 MLX5_ADS_STAT_RATE_120GBPS = 0xf, 467 }; 468 469 struct mlx5_ifc_ads_bits { 470 u8 fl[0x1]; 471 u8 free_ar[0x1]; 472 u8 reserved_at_2[0xe]; 473 u8 pkey_index[0x10]; 474 475 u8 reserved_at_20[0x8]; 476 u8 grh[0x1]; 477 u8 mlid[0x7]; 478 u8 rlid[0x10]; 479 480 u8 ack_timeout[0x5]; 481 u8 reserved_at_45[0x3]; 482 u8 src_addr_index[0x8]; 483 u8 reserved_at_50[0x4]; 484 u8 stat_rate[0x4]; 485 u8 hop_limit[0x8]; 486 487 u8 reserved_at_60[0x4]; 488 u8 tclass[0x8]; 489 u8 flow_label[0x14]; 490 491 u8 rgid_rip[16][0x8]; 492 493 u8 reserved_at_100[0x4]; 494 u8 f_dscp[0x1]; 495 u8 f_ecn[0x1]; 496 u8 reserved_at_106[0x1]; 497 u8 f_eth_prio[0x1]; 498 u8 ecn[0x2]; 499 u8 dscp[0x6]; 500 u8 udp_sport[0x10]; 501 502 u8 dei_cfi[0x1]; 503 u8 eth_prio[0x3]; 504 u8 sl[0x4]; 505 u8 vhca_port_num[0x8]; 506 u8 rmac_47_32[0x10]; 507 508 u8 rmac_31_0[0x20]; 509 }; 510 511 struct mlx5_ifc_flow_table_nic_cap_bits { 512 u8 nic_rx_multi_path_tirs[0x1]; 513 u8 nic_rx_multi_path_tirs_fts[0x1]; 514 u8 allow_sniffer_and_nic_rx_shared_tir[0x1]; 515 u8 reserved_at_3[0x1fd]; 516 517 struct mlx5_ifc_flow_table_prop_layout_bits flow_table_properties_nic_receive; 518 519 u8 reserved_at_400[0x200]; 520 521 struct mlx5_ifc_flow_table_prop_layout_bits flow_table_properties_nic_receive_sniffer; 522 523 struct mlx5_ifc_flow_table_prop_layout_bits flow_table_properties_nic_transmit; 524 525 u8 reserved_at_a00[0x200]; 526 527 struct mlx5_ifc_flow_table_prop_layout_bits flow_table_properties_nic_transmit_sniffer; 528 529 u8 reserved_at_e00[0x7200]; 530 }; 531 532 struct mlx5_ifc_flow_table_eswitch_cap_bits { 533 u8 reserved_at_0[0x200]; 534 535 struct mlx5_ifc_flow_table_prop_layout_bits flow_table_properties_nic_esw_fdb; 536 537 struct mlx5_ifc_flow_table_prop_layout_bits flow_table_properties_esw_acl_ingress; 538 539 struct mlx5_ifc_flow_table_prop_layout_bits flow_table_properties_esw_acl_egress; 540 541 u8 reserved_at_800[0x7800]; 542 }; 543 544 struct mlx5_ifc_e_switch_cap_bits { 545 u8 vport_svlan_strip[0x1]; 546 u8 vport_cvlan_strip[0x1]; 547 u8 vport_svlan_insert[0x1]; 548 u8 vport_cvlan_insert_if_not_exist[0x1]; 549 u8 vport_cvlan_insert_overwrite[0x1]; 550 u8 reserved_at_5[0x19]; 551 u8 nic_vport_node_guid_modify[0x1]; 552 u8 nic_vport_port_guid_modify[0x1]; 553 554 u8 vxlan_encap_decap[0x1]; 555 u8 nvgre_encap_decap[0x1]; 556 u8 reserved_at_22[0x9]; 557 u8 log_max_encap_headers[0x5]; 558 u8 reserved_2b[0x6]; 559 u8 max_encap_header_size[0xa]; 560 561 u8 reserved_40[0x7c0]; 562 563 }; 564 565 struct mlx5_ifc_qos_cap_bits { 566 u8 packet_pacing[0x1]; 567 u8 esw_scheduling[0x1]; 568 u8 esw_bw_share[0x1]; 569 u8 esw_rate_limit[0x1]; 570 u8 reserved_at_4[0x1c]; 571 572 u8 reserved_at_20[0x20]; 573 574 u8 packet_pacing_max_rate[0x20]; 575 576 u8 packet_pacing_min_rate[0x20]; 577 578 u8 reserved_at_80[0x10]; 579 u8 packet_pacing_rate_table_size[0x10]; 580 581 u8 esw_element_type[0x10]; 582 u8 esw_tsar_type[0x10]; 583 584 u8 reserved_at_c0[0x10]; 585 u8 max_qos_para_vport[0x10]; 586 587 u8 max_tsar_bw_share[0x20]; 588 589 u8 reserved_at_100[0x700]; 590 }; 591 592 struct mlx5_ifc_per_protocol_networking_offload_caps_bits { 593 u8 csum_cap[0x1]; 594 u8 vlan_cap[0x1]; 595 u8 lro_cap[0x1]; 596 u8 lro_psh_flag[0x1]; 597 u8 lro_time_stamp[0x1]; 598 u8 reserved_at_5[0x2]; 599 u8 wqe_vlan_insert[0x1]; 600 u8 self_lb_en_modifiable[0x1]; 601 u8 reserved_at_9[0x2]; 602 u8 max_lso_cap[0x5]; 603 u8 multi_pkt_send_wqe[0x2]; 604 u8 wqe_inline_mode[0x2]; 605 u8 rss_ind_tbl_cap[0x4]; 606 u8 reg_umr_sq[0x1]; 607 u8 scatter_fcs[0x1]; 608 u8 enhanced_multi_pkt_send_wqe[0x1]; 609 u8 tunnel_lso_const_out_ip_id[0x1]; 610 u8 reserved_at_1c[0x2]; 611 u8 tunnel_stateless_gre[0x1]; 612 u8 tunnel_stateless_vxlan[0x1]; 613 614 u8 swp[0x1]; 615 u8 swp_csum[0x1]; 616 u8 swp_lso[0x1]; 617 u8 reserved_at_23[0x1b]; 618 u8 max_geneve_opt_len[0x1]; 619 u8 tunnel_stateless_geneve_rx[0x1]; 620 621 u8 reserved_at_40[0x10]; 622 u8 lro_min_mss_size[0x10]; 623 624 u8 reserved_at_60[0x120]; 625 626 u8 lro_timer_supported_periods[4][0x20]; 627 628 u8 reserved_at_200[0x600]; 629 }; 630 631 struct mlx5_ifc_roce_cap_bits { 632 u8 roce_apm[0x1]; 633 u8 reserved_at_1[0x1f]; 634 635 u8 reserved_at_20[0x60]; 636 637 u8 reserved_at_80[0xc]; 638 u8 l3_type[0x4]; 639 u8 reserved_at_90[0x8]; 640 u8 roce_version[0x8]; 641 642 u8 reserved_at_a0[0x10]; 643 u8 r_roce_dest_udp_port[0x10]; 644 645 u8 r_roce_max_src_udp_port[0x10]; 646 u8 r_roce_min_src_udp_port[0x10]; 647 648 u8 reserved_at_e0[0x10]; 649 u8 roce_address_table_size[0x10]; 650 651 u8 reserved_at_100[0x700]; 652 }; 653 654 enum { 655 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_QP_1_BYTE = 0x0, 656 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_QP_2_BYTES = 0x2, 657 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_QP_4_BYTES = 0x4, 658 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_QP_8_BYTES = 0x8, 659 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_QP_16_BYTES = 0x10, 660 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_QP_32_BYTES = 0x20, 661 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_QP_64_BYTES = 0x40, 662 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_QP_128_BYTES = 0x80, 663 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_QP_256_BYTES = 0x100, 664 }; 665 666 enum { 667 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_DC_1_BYTE = 0x1, 668 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_DC_2_BYTES = 0x2, 669 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_DC_4_BYTES = 0x4, 670 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_DC_8_BYTES = 0x8, 671 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_DC_16_BYTES = 0x10, 672 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_DC_32_BYTES = 0x20, 673 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_DC_64_BYTES = 0x40, 674 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_DC_128_BYTES = 0x80, 675 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_DC_256_BYTES = 0x100, 676 }; 677 678 struct mlx5_ifc_atomic_caps_bits { 679 u8 reserved_at_0[0x40]; 680 681 u8 atomic_req_8B_endianness_mode[0x2]; 682 u8 reserved_at_42[0x4]; 683 u8 supported_atomic_req_8B_endianness_mode_1[0x1]; 684 685 u8 reserved_at_47[0x19]; 686 687 u8 reserved_at_60[0x20]; 688 689 u8 reserved_at_80[0x10]; 690 u8 atomic_operations[0x10]; 691 692 u8 reserved_at_a0[0x10]; 693 u8 atomic_size_qp[0x10]; 694 695 u8 reserved_at_c0[0x10]; 696 u8 atomic_size_dc[0x10]; 697 698 u8 reserved_at_e0[0x720]; 699 }; 700 701 struct mlx5_ifc_odp_cap_bits { 702 u8 reserved_at_0[0x40]; 703 704 u8 sig[0x1]; 705 u8 reserved_at_41[0x1f]; 706 707 u8 reserved_at_60[0x20]; 708 709 struct mlx5_ifc_odp_per_transport_service_cap_bits rc_odp_caps; 710 711 struct mlx5_ifc_odp_per_transport_service_cap_bits uc_odp_caps; 712 713 struct mlx5_ifc_odp_per_transport_service_cap_bits ud_odp_caps; 714 715 u8 reserved_at_e0[0x720]; 716 }; 717 718 struct mlx5_ifc_calc_op { 719 u8 reserved_at_0[0x10]; 720 u8 reserved_at_10[0x9]; 721 u8 op_swap_endianness[0x1]; 722 u8 op_min[0x1]; 723 u8 op_xor[0x1]; 724 u8 op_or[0x1]; 725 u8 op_and[0x1]; 726 u8 op_max[0x1]; 727 u8 op_add[0x1]; 728 }; 729 730 struct mlx5_ifc_vector_calc_cap_bits { 731 u8 calc_matrix[0x1]; 732 u8 reserved_at_1[0x1f]; 733 u8 reserved_at_20[0x8]; 734 u8 max_vec_count[0x8]; 735 u8 reserved_at_30[0xd]; 736 u8 max_chunk_size[0x3]; 737 struct mlx5_ifc_calc_op calc0; 738 struct mlx5_ifc_calc_op calc1; 739 struct mlx5_ifc_calc_op calc2; 740 struct mlx5_ifc_calc_op calc3; 741 742 u8 reserved_at_e0[0x720]; 743 }; 744 745 enum { 746 MLX5_WQ_TYPE_LINKED_LIST = 0x0, 747 MLX5_WQ_TYPE_CYCLIC = 0x1, 748 MLX5_WQ_TYPE_LINKED_LIST_STRIDING_RQ = 0x2, 749 MLX5_WQ_TYPE_CYCLIC_STRIDING_RQ = 0x3, 750 }; 751 752 enum { 753 MLX5_WQ_END_PAD_MODE_NONE = 0x0, 754 MLX5_WQ_END_PAD_MODE_ALIGN = 0x1, 755 }; 756 757 enum { 758 MLX5_CMD_HCA_CAP_GID_TABLE_SIZE_8_GID_ENTRIES = 0x0, 759 MLX5_CMD_HCA_CAP_GID_TABLE_SIZE_16_GID_ENTRIES = 0x1, 760 MLX5_CMD_HCA_CAP_GID_TABLE_SIZE_32_GID_ENTRIES = 0x2, 761 MLX5_CMD_HCA_CAP_GID_TABLE_SIZE_64_GID_ENTRIES = 0x3, 762 MLX5_CMD_HCA_CAP_GID_TABLE_SIZE_128_GID_ENTRIES = 0x4, 763 }; 764 765 enum { 766 MLX5_CMD_HCA_CAP_PKEY_TABLE_SIZE_128_ENTRIES = 0x0, 767 MLX5_CMD_HCA_CAP_PKEY_TABLE_SIZE_256_ENTRIES = 0x1, 768 MLX5_CMD_HCA_CAP_PKEY_TABLE_SIZE_512_ENTRIES = 0x2, 769 MLX5_CMD_HCA_CAP_PKEY_TABLE_SIZE_1K_ENTRIES = 0x3, 770 MLX5_CMD_HCA_CAP_PKEY_TABLE_SIZE_2K_ENTRIES = 0x4, 771 MLX5_CMD_HCA_CAP_PKEY_TABLE_SIZE_4K_ENTRIES = 0x5, 772 }; 773 774 enum { 775 MLX5_CMD_HCA_CAP_PORT_TYPE_IB = 0x0, 776 MLX5_CMD_HCA_CAP_PORT_TYPE_ETHERNET = 0x1, 777 }; 778 779 enum { 780 MLX5_CMD_HCA_CAP_CMDIF_CHECKSUM_DISABLED = 0x0, 781 MLX5_CMD_HCA_CAP_CMDIF_CHECKSUM_INITIAL_STATE = 0x1, 782 MLX5_CMD_HCA_CAP_CMDIF_CHECKSUM_ENABLED = 0x3, 783 }; 784 785 enum { 786 MLX5_CAP_PORT_TYPE_IB = 0x0, 787 MLX5_CAP_PORT_TYPE_ETH = 0x1, 788 }; 789 790 enum { 791 MLX5_CAP_UMR_FENCE_STRONG = 0x0, 792 MLX5_CAP_UMR_FENCE_SMALL = 0x1, 793 MLX5_CAP_UMR_FENCE_NONE = 0x2, 794 }; 795 796 struct mlx5_ifc_cmd_hca_cap_bits { 797 u8 reserved_at_0[0x30]; 798 u8 vhca_id[0x10]; 799 800 u8 reserved_at_40[0x40]; 801 802 u8 log_max_srq_sz[0x8]; 803 u8 log_max_qp_sz[0x8]; 804 u8 reserved_at_90[0xb]; 805 u8 log_max_qp[0x5]; 806 807 u8 reserved_at_a0[0xb]; 808 u8 log_max_srq[0x5]; 809 u8 reserved_at_b0[0x10]; 810 811 u8 reserved_at_c0[0x8]; 812 u8 log_max_cq_sz[0x8]; 813 u8 reserved_at_d0[0xb]; 814 u8 log_max_cq[0x5]; 815 816 u8 log_max_eq_sz[0x8]; 817 u8 reserved_at_e8[0x2]; 818 u8 log_max_mkey[0x6]; 819 u8 reserved_at_f0[0xc]; 820 u8 log_max_eq[0x4]; 821 822 u8 max_indirection[0x8]; 823 u8 fixed_buffer_size[0x1]; 824 u8 log_max_mrw_sz[0x7]; 825 u8 force_teardown[0x1]; 826 u8 reserved_at_111[0x1]; 827 u8 log_max_bsf_list_size[0x6]; 828 u8 umr_extended_translation_offset[0x1]; 829 u8 null_mkey[0x1]; 830 u8 log_max_klm_list_size[0x6]; 831 832 u8 reserved_at_120[0xa]; 833 u8 log_max_ra_req_dc[0x6]; 834 u8 reserved_at_130[0xa]; 835 u8 log_max_ra_res_dc[0x6]; 836 837 u8 reserved_at_140[0xa]; 838 u8 log_max_ra_req_qp[0x6]; 839 u8 reserved_at_150[0xa]; 840 u8 log_max_ra_res_qp[0x6]; 841 842 u8 end_pad[0x1]; 843 u8 cc_query_allowed[0x1]; 844 u8 cc_modify_allowed[0x1]; 845 u8 start_pad[0x1]; 846 u8 cache_line_128byte[0x1]; 847 u8 reserved_at_165[0xa]; 848 u8 qcam_reg[0x1]; 849 u8 gid_table_size[0x10]; 850 851 u8 out_of_seq_cnt[0x1]; 852 u8 vport_counters[0x1]; 853 u8 retransmission_q_counters[0x1]; 854 u8 reserved_at_183[0x1]; 855 u8 modify_rq_counter_set_id[0x1]; 856 u8 rq_delay_drop[0x1]; 857 u8 max_qp_cnt[0xa]; 858 u8 pkey_table_size[0x10]; 859 860 u8 vport_group_manager[0x1]; 861 u8 vhca_group_manager[0x1]; 862 u8 ib_virt[0x1]; 863 u8 eth_virt[0x1]; 864 u8 reserved_at_1a4[0x1]; 865 u8 ets[0x1]; 866 u8 nic_flow_table[0x1]; 867 u8 eswitch_flow_table[0x1]; 868 u8 early_vf_enable[0x1]; 869 u8 mcam_reg[0x1]; 870 u8 pcam_reg[0x1]; 871 u8 local_ca_ack_delay[0x5]; 872 u8 port_module_event[0x1]; 873 u8 enhanced_error_q_counters[0x1]; 874 u8 ports_check[0x1]; 875 u8 reserved_at_1b3[0x1]; 876 u8 disable_link_up[0x1]; 877 u8 beacon_led[0x1]; 878 u8 port_type[0x2]; 879 u8 num_ports[0x8]; 880 881 u8 reserved_at_1c0[0x1]; 882 u8 pps[0x1]; 883 u8 pps_modify[0x1]; 884 u8 log_max_msg[0x5]; 885 u8 reserved_at_1c8[0x4]; 886 u8 max_tc[0x4]; 887 u8 reserved_at_1d0[0x1]; 888 u8 dcbx[0x1]; 889 u8 general_notification_event[0x1]; 890 u8 reserved_at_1d3[0x2]; 891 u8 fpga[0x1]; 892 u8 rol_s[0x1]; 893 u8 rol_g[0x1]; 894 u8 reserved_at_1d8[0x1]; 895 u8 wol_s[0x1]; 896 u8 wol_g[0x1]; 897 u8 wol_a[0x1]; 898 u8 wol_b[0x1]; 899 u8 wol_m[0x1]; 900 u8 wol_u[0x1]; 901 u8 wol_p[0x1]; 902 903 u8 stat_rate_support[0x10]; 904 u8 reserved_at_1f0[0xc]; 905 u8 cqe_version[0x4]; 906 907 u8 compact_address_vector[0x1]; 908 u8 striding_rq[0x1]; 909 u8 reserved_at_202[0x1]; 910 u8 ipoib_enhanced_offloads[0x1]; 911 u8 ipoib_basic_offloads[0x1]; 912 u8 reserved_at_205[0x5]; 913 u8 umr_fence[0x2]; 914 u8 reserved_at_20c[0x3]; 915 u8 drain_sigerr[0x1]; 916 u8 cmdif_checksum[0x2]; 917 u8 sigerr_cqe[0x1]; 918 u8 reserved_at_213[0x1]; 919 u8 wq_signature[0x1]; 920 u8 sctr_data_cqe[0x1]; 921 u8 reserved_at_216[0x1]; 922 u8 sho[0x1]; 923 u8 tph[0x1]; 924 u8 rf[0x1]; 925 u8 dct[0x1]; 926 u8 qos[0x1]; 927 u8 eth_net_offloads[0x1]; 928 u8 roce[0x1]; 929 u8 atomic[0x1]; 930 u8 reserved_at_21f[0x1]; 931 932 u8 cq_oi[0x1]; 933 u8 cq_resize[0x1]; 934 u8 cq_moderation[0x1]; 935 u8 reserved_at_223[0x3]; 936 u8 cq_eq_remap[0x1]; 937 u8 pg[0x1]; 938 u8 block_lb_mc[0x1]; 939 u8 reserved_at_229[0x1]; 940 u8 scqe_break_moderation[0x1]; 941 u8 cq_period_start_from_cqe[0x1]; 942 u8 cd[0x1]; 943 u8 reserved_at_22d[0x1]; 944 u8 apm[0x1]; 945 u8 vector_calc[0x1]; 946 u8 umr_ptr_rlky[0x1]; 947 u8 imaicl[0x1]; 948 u8 reserved_at_232[0x4]; 949 u8 qkv[0x1]; 950 u8 pkv[0x1]; 951 u8 set_deth_sqpn[0x1]; 952 u8 reserved_at_239[0x3]; 953 u8 xrc[0x1]; 954 u8 ud[0x1]; 955 u8 uc[0x1]; 956 u8 rc[0x1]; 957 958 u8 uar_4k[0x1]; 959 u8 reserved_at_241[0x9]; 960 u8 uar_sz[0x6]; 961 u8 reserved_at_250[0x8]; 962 u8 log_pg_sz[0x8]; 963 964 u8 bf[0x1]; 965 u8 driver_version[0x1]; 966 u8 pad_tx_eth_packet[0x1]; 967 u8 reserved_at_263[0x8]; 968 u8 log_bf_reg_size[0x5]; 969 970 u8 reserved_at_270[0xb]; 971 u8 lag_master[0x1]; 972 u8 num_lag_ports[0x4]; 973 974 u8 reserved_at_280[0x10]; 975 u8 max_wqe_sz_sq[0x10]; 976 977 u8 reserved_at_2a0[0x10]; 978 u8 max_wqe_sz_rq[0x10]; 979 980 u8 max_flow_counter_31_16[0x10]; 981 u8 max_wqe_sz_sq_dc[0x10]; 982 983 u8 reserved_at_2e0[0x7]; 984 u8 max_qp_mcg[0x19]; 985 986 u8 reserved_at_300[0x18]; 987 u8 log_max_mcg[0x8]; 988 989 u8 reserved_at_320[0x3]; 990 u8 log_max_transport_domain[0x5]; 991 u8 reserved_at_328[0x3]; 992 u8 log_max_pd[0x5]; 993 u8 reserved_at_330[0xb]; 994 u8 log_max_xrcd[0x5]; 995 996 u8 reserved_at_340[0x8]; 997 u8 log_max_flow_counter_bulk[0x8]; 998 u8 max_flow_counter_15_0[0x10]; 999 1000 1001 u8 reserved_at_360[0x3]; 1002 u8 log_max_rq[0x5]; 1003 u8 reserved_at_368[0x3]; 1004 u8 log_max_sq[0x5]; 1005 u8 reserved_at_370[0x3]; 1006 u8 log_max_tir[0x5]; 1007 u8 reserved_at_378[0x3]; 1008 u8 log_max_tis[0x5]; 1009 1010 u8 basic_cyclic_rcv_wqe[0x1]; 1011 u8 reserved_at_381[0x2]; 1012 u8 log_max_rmp[0x5]; 1013 u8 reserved_at_388[0x3]; 1014 u8 log_max_rqt[0x5]; 1015 u8 reserved_at_390[0x3]; 1016 u8 log_max_rqt_size[0x5]; 1017 u8 reserved_at_398[0x3]; 1018 u8 log_max_tis_per_sq[0x5]; 1019 1020 u8 reserved_at_3a0[0x3]; 1021 u8 log_max_stride_sz_rq[0x5]; 1022 u8 reserved_at_3a8[0x3]; 1023 u8 log_min_stride_sz_rq[0x5]; 1024 u8 reserved_at_3b0[0x3]; 1025 u8 log_max_stride_sz_sq[0x5]; 1026 u8 reserved_at_3b8[0x3]; 1027 u8 log_min_stride_sz_sq[0x5]; 1028 1029 u8 reserved_at_3c0[0x1b]; 1030 u8 log_max_wq_sz[0x5]; 1031 1032 u8 nic_vport_change_event[0x1]; 1033 u8 disable_local_lb_uc[0x1]; 1034 u8 disable_local_lb_mc[0x1]; 1035 u8 reserved_at_3e3[0x8]; 1036 u8 log_max_vlan_list[0x5]; 1037 u8 reserved_at_3f0[0x3]; 1038 u8 log_max_current_mc_list[0x5]; 1039 u8 reserved_at_3f8[0x3]; 1040 u8 log_max_current_uc_list[0x5]; 1041 1042 u8 reserved_at_400[0x80]; 1043 1044 u8 reserved_at_480[0x3]; 1045 u8 log_max_l2_table[0x5]; 1046 u8 reserved_at_488[0x8]; 1047 u8 log_uar_page_sz[0x10]; 1048 1049 u8 reserved_at_4a0[0x20]; 1050 u8 device_frequency_mhz[0x20]; 1051 u8 device_frequency_khz[0x20]; 1052 1053 u8 reserved_at_500[0x20]; 1054 u8 num_of_uars_per_page[0x20]; 1055 u8 reserved_at_540[0x40]; 1056 1057 u8 reserved_at_580[0x3d]; 1058 u8 cqe_128_always[0x1]; 1059 u8 cqe_compression_128[0x1]; 1060 u8 cqe_compression[0x1]; 1061 1062 u8 cqe_compression_timeout[0x10]; 1063 u8 cqe_compression_max_num[0x10]; 1064 1065 u8 reserved_at_5e0[0x10]; 1066 u8 tag_matching[0x1]; 1067 u8 rndv_offload_rc[0x1]; 1068 u8 rndv_offload_dc[0x1]; 1069 u8 log_tag_matching_list_sz[0x5]; 1070 u8 reserved_at_5f8[0x3]; 1071 u8 log_max_xrq[0x5]; 1072 1073 u8 affiliate_nic_vport_criteria[0x8]; 1074 u8 native_port_num[0x8]; 1075 u8 num_vhca_ports[0x8]; 1076 u8 reserved_at_618[0x6]; 1077 u8 sw_owner_id[0x1]; 1078 u8 reserved_at_61f[0x1e1]; 1079 }; 1080 1081 enum mlx5_flow_destination_type { 1082 MLX5_FLOW_DESTINATION_TYPE_VPORT = 0x0, 1083 MLX5_FLOW_DESTINATION_TYPE_FLOW_TABLE = 0x1, 1084 MLX5_FLOW_DESTINATION_TYPE_TIR = 0x2, 1085 1086 MLX5_FLOW_DESTINATION_TYPE_COUNTER = 0x100, 1087 }; 1088 1089 struct mlx5_ifc_dest_format_struct_bits { 1090 u8 destination_type[0x8]; 1091 u8 destination_id[0x18]; 1092 1093 u8 reserved_at_20[0x20]; 1094 }; 1095 1096 struct mlx5_ifc_flow_counter_list_bits { 1097 u8 flow_counter_id[0x20]; 1098 1099 u8 reserved_at_20[0x20]; 1100 }; 1101 1102 union mlx5_ifc_dest_format_struct_flow_counter_list_auto_bits { 1103 struct mlx5_ifc_dest_format_struct_bits dest_format_struct; 1104 struct mlx5_ifc_flow_counter_list_bits flow_counter_list; 1105 u8 reserved_at_0[0x40]; 1106 }; 1107 1108 struct mlx5_ifc_fte_match_param_bits { 1109 struct mlx5_ifc_fte_match_set_lyr_2_4_bits outer_headers; 1110 1111 struct mlx5_ifc_fte_match_set_misc_bits misc_parameters; 1112 1113 struct mlx5_ifc_fte_match_set_lyr_2_4_bits inner_headers; 1114 1115 u8 reserved_at_600[0xa00]; 1116 }; 1117 1118 enum { 1119 MLX5_RX_HASH_FIELD_SELECT_SELECTED_FIELDS_SRC_IP = 0x0, 1120 MLX5_RX_HASH_FIELD_SELECT_SELECTED_FIELDS_DST_IP = 0x1, 1121 MLX5_RX_HASH_FIELD_SELECT_SELECTED_FIELDS_L4_SPORT = 0x2, 1122 MLX5_RX_HASH_FIELD_SELECT_SELECTED_FIELDS_L4_DPORT = 0x3, 1123 MLX5_RX_HASH_FIELD_SELECT_SELECTED_FIELDS_IPSEC_SPI = 0x4, 1124 }; 1125 1126 struct mlx5_ifc_rx_hash_field_select_bits { 1127 u8 l3_prot_type[0x1]; 1128 u8 l4_prot_type[0x1]; 1129 u8 selected_fields[0x1e]; 1130 }; 1131 1132 enum { 1133 MLX5_WQ_WQ_TYPE_WQ_LINKED_LIST = 0x0, 1134 MLX5_WQ_WQ_TYPE_WQ_CYCLIC = 0x1, 1135 }; 1136 1137 enum { 1138 MLX5_WQ_END_PADDING_MODE_END_PAD_NONE = 0x0, 1139 MLX5_WQ_END_PADDING_MODE_END_PAD_ALIGN = 0x1, 1140 }; 1141 1142 struct mlx5_ifc_wq_bits { 1143 u8 wq_type[0x4]; 1144 u8 wq_signature[0x1]; 1145 u8 end_padding_mode[0x2]; 1146 u8 cd_slave[0x1]; 1147 u8 reserved_at_8[0x18]; 1148 1149 u8 hds_skip_first_sge[0x1]; 1150 u8 log2_hds_buf_size[0x3]; 1151 u8 reserved_at_24[0x7]; 1152 u8 page_offset[0x5]; 1153 u8 lwm[0x10]; 1154 1155 u8 reserved_at_40[0x8]; 1156 u8 pd[0x18]; 1157 1158 u8 reserved_at_60[0x8]; 1159 u8 uar_page[0x18]; 1160 1161 u8 dbr_addr[0x40]; 1162 1163 u8 hw_counter[0x20]; 1164 1165 u8 sw_counter[0x20]; 1166 1167 u8 reserved_at_100[0xc]; 1168 u8 log_wq_stride[0x4]; 1169 u8 reserved_at_110[0x3]; 1170 u8 log_wq_pg_sz[0x5]; 1171 u8 reserved_at_118[0x3]; 1172 u8 log_wq_sz[0x5]; 1173 1174 u8 reserved_at_120[0x15]; 1175 u8 log_wqe_num_of_strides[0x3]; 1176 u8 two_byte_shift_en[0x1]; 1177 u8 reserved_at_139[0x4]; 1178 u8 log_wqe_stride_size[0x3]; 1179 1180 u8 reserved_at_140[0x4c0]; 1181 1182 struct mlx5_ifc_cmd_pas_bits pas[0]; 1183 }; 1184 1185 struct mlx5_ifc_rq_num_bits { 1186 u8 reserved_at_0[0x8]; 1187 u8 rq_num[0x18]; 1188 }; 1189 1190 struct mlx5_ifc_mac_address_layout_bits { 1191 u8 reserved_at_0[0x10]; 1192 u8 mac_addr_47_32[0x10]; 1193 1194 u8 mac_addr_31_0[0x20]; 1195 }; 1196 1197 struct mlx5_ifc_vlan_layout_bits { 1198 u8 reserved_at_0[0x14]; 1199 u8 vlan[0x0c]; 1200 1201 u8 reserved_at_20[0x20]; 1202 }; 1203 1204 struct mlx5_ifc_cong_control_r_roce_ecn_np_bits { 1205 u8 reserved_at_0[0xa0]; 1206 1207 u8 min_time_between_cnps[0x20]; 1208 1209 u8 reserved_at_c0[0x12]; 1210 u8 cnp_dscp[0x6]; 1211 u8 reserved_at_d8[0x4]; 1212 u8 cnp_prio_mode[0x1]; 1213 u8 cnp_802p_prio[0x3]; 1214 1215 u8 reserved_at_e0[0x720]; 1216 }; 1217 1218 struct mlx5_ifc_cong_control_r_roce_ecn_rp_bits { 1219 u8 reserved_at_0[0x60]; 1220 1221 u8 reserved_at_60[0x4]; 1222 u8 clamp_tgt_rate[0x1]; 1223 u8 reserved_at_65[0x3]; 1224 u8 clamp_tgt_rate_after_time_inc[0x1]; 1225 u8 reserved_at_69[0x17]; 1226 1227 u8 reserved_at_80[0x20]; 1228 1229 u8 rpg_time_reset[0x20]; 1230 1231 u8 rpg_byte_reset[0x20]; 1232 1233 u8 rpg_threshold[0x20]; 1234 1235 u8 rpg_max_rate[0x20]; 1236 1237 u8 rpg_ai_rate[0x20]; 1238 1239 u8 rpg_hai_rate[0x20]; 1240 1241 u8 rpg_gd[0x20]; 1242 1243 u8 rpg_min_dec_fac[0x20]; 1244 1245 u8 rpg_min_rate[0x20]; 1246 1247 u8 reserved_at_1c0[0xe0]; 1248 1249 u8 rate_to_set_on_first_cnp[0x20]; 1250 1251 u8 dce_tcp_g[0x20]; 1252 1253 u8 dce_tcp_rtt[0x20]; 1254 1255 u8 rate_reduce_monitor_period[0x20]; 1256 1257 u8 reserved_at_320[0x20]; 1258 1259 u8 initial_alpha_value[0x20]; 1260 1261 u8 reserved_at_360[0x4a0]; 1262 }; 1263 1264 struct mlx5_ifc_cong_control_802_1qau_rp_bits { 1265 u8 reserved_at_0[0x80]; 1266 1267 u8 rppp_max_rps[0x20]; 1268 1269 u8 rpg_time_reset[0x20]; 1270 1271 u8 rpg_byte_reset[0x20]; 1272 1273 u8 rpg_threshold[0x20]; 1274 1275 u8 rpg_max_rate[0x20]; 1276 1277 u8 rpg_ai_rate[0x20]; 1278 1279 u8 rpg_hai_rate[0x20]; 1280 1281 u8 rpg_gd[0x20]; 1282 1283 u8 rpg_min_dec_fac[0x20]; 1284 1285 u8 rpg_min_rate[0x20]; 1286 1287 u8 reserved_at_1c0[0x640]; 1288 }; 1289 1290 enum { 1291 MLX5_RESIZE_FIELD_SELECT_RESIZE_FIELD_SELECT_LOG_CQ_SIZE = 0x1, 1292 MLX5_RESIZE_FIELD_SELECT_RESIZE_FIELD_SELECT_PAGE_OFFSET = 0x2, 1293 MLX5_RESIZE_FIELD_SELECT_RESIZE_FIELD_SELECT_LOG_PAGE_SIZE = 0x4, 1294 }; 1295 1296 struct mlx5_ifc_resize_field_select_bits { 1297 u8 resize_field_select[0x20]; 1298 }; 1299 1300 enum { 1301 MLX5_MODIFY_FIELD_SELECT_MODIFY_FIELD_SELECT_CQ_PERIOD = 0x1, 1302 MLX5_MODIFY_FIELD_SELECT_MODIFY_FIELD_SELECT_CQ_MAX_COUNT = 0x2, 1303 MLX5_MODIFY_FIELD_SELECT_MODIFY_FIELD_SELECT_OI = 0x4, 1304 MLX5_MODIFY_FIELD_SELECT_MODIFY_FIELD_SELECT_C_EQN = 0x8, 1305 }; 1306 1307 struct mlx5_ifc_modify_field_select_bits { 1308 u8 modify_field_select[0x20]; 1309 }; 1310 1311 struct mlx5_ifc_field_select_r_roce_np_bits { 1312 u8 field_select_r_roce_np[0x20]; 1313 }; 1314 1315 struct mlx5_ifc_field_select_r_roce_rp_bits { 1316 u8 field_select_r_roce_rp[0x20]; 1317 }; 1318 1319 enum { 1320 MLX5_FIELD_SELECT_802_1QAU_RP_FIELD_SELECT_8021QAURP_RPPP_MAX_RPS = 0x4, 1321 MLX5_FIELD_SELECT_802_1QAU_RP_FIELD_SELECT_8021QAURP_RPG_TIME_RESET = 0x8, 1322 MLX5_FIELD_SELECT_802_1QAU_RP_FIELD_SELECT_8021QAURP_RPG_BYTE_RESET = 0x10, 1323 MLX5_FIELD_SELECT_802_1QAU_RP_FIELD_SELECT_8021QAURP_RPG_THRESHOLD = 0x20, 1324 MLX5_FIELD_SELECT_802_1QAU_RP_FIELD_SELECT_8021QAURP_RPG_MAX_RATE = 0x40, 1325 MLX5_FIELD_SELECT_802_1QAU_RP_FIELD_SELECT_8021QAURP_RPG_AI_RATE = 0x80, 1326 MLX5_FIELD_SELECT_802_1QAU_RP_FIELD_SELECT_8021QAURP_RPG_HAI_RATE = 0x100, 1327 MLX5_FIELD_SELECT_802_1QAU_RP_FIELD_SELECT_8021QAURP_RPG_GD = 0x200, 1328 MLX5_FIELD_SELECT_802_1QAU_RP_FIELD_SELECT_8021QAURP_RPG_MIN_DEC_FAC = 0x400, 1329 MLX5_FIELD_SELECT_802_1QAU_RP_FIELD_SELECT_8021QAURP_RPG_MIN_RATE = 0x800, 1330 }; 1331 1332 struct mlx5_ifc_field_select_802_1qau_rp_bits { 1333 u8 field_select_8021qaurp[0x20]; 1334 }; 1335 1336 struct mlx5_ifc_phys_layer_cntrs_bits { 1337 u8 time_since_last_clear_high[0x20]; 1338 1339 u8 time_since_last_clear_low[0x20]; 1340 1341 u8 symbol_errors_high[0x20]; 1342 1343 u8 symbol_errors_low[0x20]; 1344 1345 u8 sync_headers_errors_high[0x20]; 1346 1347 u8 sync_headers_errors_low[0x20]; 1348 1349 u8 edpl_bip_errors_lane0_high[0x20]; 1350 1351 u8 edpl_bip_errors_lane0_low[0x20]; 1352 1353 u8 edpl_bip_errors_lane1_high[0x20]; 1354 1355 u8 edpl_bip_errors_lane1_low[0x20]; 1356 1357 u8 edpl_bip_errors_lane2_high[0x20]; 1358 1359 u8 edpl_bip_errors_lane2_low[0x20]; 1360 1361 u8 edpl_bip_errors_lane3_high[0x20]; 1362 1363 u8 edpl_bip_errors_lane3_low[0x20]; 1364 1365 u8 fc_fec_corrected_blocks_lane0_high[0x20]; 1366 1367 u8 fc_fec_corrected_blocks_lane0_low[0x20]; 1368 1369 u8 fc_fec_corrected_blocks_lane1_high[0x20]; 1370 1371 u8 fc_fec_corrected_blocks_lane1_low[0x20]; 1372 1373 u8 fc_fec_corrected_blocks_lane2_high[0x20]; 1374 1375 u8 fc_fec_corrected_blocks_lane2_low[0x20]; 1376 1377 u8 fc_fec_corrected_blocks_lane3_high[0x20]; 1378 1379 u8 fc_fec_corrected_blocks_lane3_low[0x20]; 1380 1381 u8 fc_fec_uncorrectable_blocks_lane0_high[0x20]; 1382 1383 u8 fc_fec_uncorrectable_blocks_lane0_low[0x20]; 1384 1385 u8 fc_fec_uncorrectable_blocks_lane1_high[0x20]; 1386 1387 u8 fc_fec_uncorrectable_blocks_lane1_low[0x20]; 1388 1389 u8 fc_fec_uncorrectable_blocks_lane2_high[0x20]; 1390 1391 u8 fc_fec_uncorrectable_blocks_lane2_low[0x20]; 1392 1393 u8 fc_fec_uncorrectable_blocks_lane3_high[0x20]; 1394 1395 u8 fc_fec_uncorrectable_blocks_lane3_low[0x20]; 1396 1397 u8 rs_fec_corrected_blocks_high[0x20]; 1398 1399 u8 rs_fec_corrected_blocks_low[0x20]; 1400 1401 u8 rs_fec_uncorrectable_blocks_high[0x20]; 1402 1403 u8 rs_fec_uncorrectable_blocks_low[0x20]; 1404 1405 u8 rs_fec_no_errors_blocks_high[0x20]; 1406 1407 u8 rs_fec_no_errors_blocks_low[0x20]; 1408 1409 u8 rs_fec_single_error_blocks_high[0x20]; 1410 1411 u8 rs_fec_single_error_blocks_low[0x20]; 1412 1413 u8 rs_fec_corrected_symbols_total_high[0x20]; 1414 1415 u8 rs_fec_corrected_symbols_total_low[0x20]; 1416 1417 u8 rs_fec_corrected_symbols_lane0_high[0x20]; 1418 1419 u8 rs_fec_corrected_symbols_lane0_low[0x20]; 1420 1421 u8 rs_fec_corrected_symbols_lane1_high[0x20]; 1422 1423 u8 rs_fec_corrected_symbols_lane1_low[0x20]; 1424 1425 u8 rs_fec_corrected_symbols_lane2_high[0x20]; 1426 1427 u8 rs_fec_corrected_symbols_lane2_low[0x20]; 1428 1429 u8 rs_fec_corrected_symbols_lane3_high[0x20]; 1430 1431 u8 rs_fec_corrected_symbols_lane3_low[0x20]; 1432 1433 u8 link_down_events[0x20]; 1434 1435 u8 successful_recovery_events[0x20]; 1436 1437 u8 reserved_at_640[0x180]; 1438 }; 1439 1440 struct mlx5_ifc_phys_layer_statistical_cntrs_bits { 1441 u8 time_since_last_clear_high[0x20]; 1442 1443 u8 time_since_last_clear_low[0x20]; 1444 1445 u8 phy_received_bits_high[0x20]; 1446 1447 u8 phy_received_bits_low[0x20]; 1448 1449 u8 phy_symbol_errors_high[0x20]; 1450 1451 u8 phy_symbol_errors_low[0x20]; 1452 1453 u8 phy_corrected_bits_high[0x20]; 1454 1455 u8 phy_corrected_bits_low[0x20]; 1456 1457 u8 phy_corrected_bits_lane0_high[0x20]; 1458 1459 u8 phy_corrected_bits_lane0_low[0x20]; 1460 1461 u8 phy_corrected_bits_lane1_high[0x20]; 1462 1463 u8 phy_corrected_bits_lane1_low[0x20]; 1464 1465 u8 phy_corrected_bits_lane2_high[0x20]; 1466 1467 u8 phy_corrected_bits_lane2_low[0x20]; 1468 1469 u8 phy_corrected_bits_lane3_high[0x20]; 1470 1471 u8 phy_corrected_bits_lane3_low[0x20]; 1472 1473 u8 reserved_at_200[0x5c0]; 1474 }; 1475 1476 struct mlx5_ifc_ib_port_cntrs_grp_data_layout_bits { 1477 u8 symbol_error_counter[0x10]; 1478 1479 u8 link_error_recovery_counter[0x8]; 1480 1481 u8 link_downed_counter[0x8]; 1482 1483 u8 port_rcv_errors[0x10]; 1484 1485 u8 port_rcv_remote_physical_errors[0x10]; 1486 1487 u8 port_rcv_switch_relay_errors[0x10]; 1488 1489 u8 port_xmit_discards[0x10]; 1490 1491 u8 port_xmit_constraint_errors[0x8]; 1492 1493 u8 port_rcv_constraint_errors[0x8]; 1494 1495 u8 reserved_at_70[0x8]; 1496 1497 u8 link_overrun_errors[0x8]; 1498 1499 u8 reserved_at_80[0x10]; 1500 1501 u8 vl_15_dropped[0x10]; 1502 1503 u8 reserved_at_a0[0x80]; 1504 1505 u8 port_xmit_wait[0x20]; 1506 }; 1507 1508 struct mlx5_ifc_eth_per_traffic_grp_data_layout_bits { 1509 u8 transmit_queue_high[0x20]; 1510 1511 u8 transmit_queue_low[0x20]; 1512 1513 u8 reserved_at_40[0x780]; 1514 }; 1515 1516 struct mlx5_ifc_eth_per_prio_grp_data_layout_bits { 1517 u8 rx_octets_high[0x20]; 1518 1519 u8 rx_octets_low[0x20]; 1520 1521 u8 reserved_at_40[0xc0]; 1522 1523 u8 rx_frames_high[0x20]; 1524 1525 u8 rx_frames_low[0x20]; 1526 1527 u8 tx_octets_high[0x20]; 1528 1529 u8 tx_octets_low[0x20]; 1530 1531 u8 reserved_at_180[0xc0]; 1532 1533 u8 tx_frames_high[0x20]; 1534 1535 u8 tx_frames_low[0x20]; 1536 1537 u8 rx_pause_high[0x20]; 1538 1539 u8 rx_pause_low[0x20]; 1540 1541 u8 rx_pause_duration_high[0x20]; 1542 1543 u8 rx_pause_duration_low[0x20]; 1544 1545 u8 tx_pause_high[0x20]; 1546 1547 u8 tx_pause_low[0x20]; 1548 1549 u8 tx_pause_duration_high[0x20]; 1550 1551 u8 tx_pause_duration_low[0x20]; 1552 1553 u8 rx_pause_transition_high[0x20]; 1554 1555 u8 rx_pause_transition_low[0x20]; 1556 1557 u8 reserved_at_3c0[0x400]; 1558 }; 1559 1560 struct mlx5_ifc_eth_extended_cntrs_grp_data_layout_bits { 1561 u8 port_transmit_wait_high[0x20]; 1562 1563 u8 port_transmit_wait_low[0x20]; 1564 1565 u8 reserved_at_40[0x100]; 1566 1567 u8 rx_buffer_almost_full_high[0x20]; 1568 1569 u8 rx_buffer_almost_full_low[0x20]; 1570 1571 u8 rx_buffer_full_high[0x20]; 1572 1573 u8 rx_buffer_full_low[0x20]; 1574 1575 u8 reserved_at_1c0[0x600]; 1576 }; 1577 1578 struct mlx5_ifc_eth_3635_cntrs_grp_data_layout_bits { 1579 u8 dot3stats_alignment_errors_high[0x20]; 1580 1581 u8 dot3stats_alignment_errors_low[0x20]; 1582 1583 u8 dot3stats_fcs_errors_high[0x20]; 1584 1585 u8 dot3stats_fcs_errors_low[0x20]; 1586 1587 u8 dot3stats_single_collision_frames_high[0x20]; 1588 1589 u8 dot3stats_single_collision_frames_low[0x20]; 1590 1591 u8 dot3stats_multiple_collision_frames_high[0x20]; 1592 1593 u8 dot3stats_multiple_collision_frames_low[0x20]; 1594 1595 u8 dot3stats_sqe_test_errors_high[0x20]; 1596 1597 u8 dot3stats_sqe_test_errors_low[0x20]; 1598 1599 u8 dot3stats_deferred_transmissions_high[0x20]; 1600 1601 u8 dot3stats_deferred_transmissions_low[0x20]; 1602 1603 u8 dot3stats_late_collisions_high[0x20]; 1604 1605 u8 dot3stats_late_collisions_low[0x20]; 1606 1607 u8 dot3stats_excessive_collisions_high[0x20]; 1608 1609 u8 dot3stats_excessive_collisions_low[0x20]; 1610 1611 u8 dot3stats_internal_mac_transmit_errors_high[0x20]; 1612 1613 u8 dot3stats_internal_mac_transmit_errors_low[0x20]; 1614 1615 u8 dot3stats_carrier_sense_errors_high[0x20]; 1616 1617 u8 dot3stats_carrier_sense_errors_low[0x20]; 1618 1619 u8 dot3stats_frame_too_longs_high[0x20]; 1620 1621 u8 dot3stats_frame_too_longs_low[0x20]; 1622 1623 u8 dot3stats_internal_mac_receive_errors_high[0x20]; 1624 1625 u8 dot3stats_internal_mac_receive_errors_low[0x20]; 1626 1627 u8 dot3stats_symbol_errors_high[0x20]; 1628 1629 u8 dot3stats_symbol_errors_low[0x20]; 1630 1631 u8 dot3control_in_unknown_opcodes_high[0x20]; 1632 1633 u8 dot3control_in_unknown_opcodes_low[0x20]; 1634 1635 u8 dot3in_pause_frames_high[0x20]; 1636 1637 u8 dot3in_pause_frames_low[0x20]; 1638 1639 u8 dot3out_pause_frames_high[0x20]; 1640 1641 u8 dot3out_pause_frames_low[0x20]; 1642 1643 u8 reserved_at_400[0x3c0]; 1644 }; 1645 1646 struct mlx5_ifc_eth_2819_cntrs_grp_data_layout_bits { 1647 u8 ether_stats_drop_events_high[0x20]; 1648 1649 u8 ether_stats_drop_events_low[0x20]; 1650 1651 u8 ether_stats_octets_high[0x20]; 1652 1653 u8 ether_stats_octets_low[0x20]; 1654 1655 u8 ether_stats_pkts_high[0x20]; 1656 1657 u8 ether_stats_pkts_low[0x20]; 1658 1659 u8 ether_stats_broadcast_pkts_high[0x20]; 1660 1661 u8 ether_stats_broadcast_pkts_low[0x20]; 1662 1663 u8 ether_stats_multicast_pkts_high[0x20]; 1664 1665 u8 ether_stats_multicast_pkts_low[0x20]; 1666 1667 u8 ether_stats_crc_align_errors_high[0x20]; 1668 1669 u8 ether_stats_crc_align_errors_low[0x20]; 1670 1671 u8 ether_stats_undersize_pkts_high[0x20]; 1672 1673 u8 ether_stats_undersize_pkts_low[0x20]; 1674 1675 u8 ether_stats_oversize_pkts_high[0x20]; 1676 1677 u8 ether_stats_oversize_pkts_low[0x20]; 1678 1679 u8 ether_stats_fragments_high[0x20]; 1680 1681 u8 ether_stats_fragments_low[0x20]; 1682 1683 u8 ether_stats_jabbers_high[0x20]; 1684 1685 u8 ether_stats_jabbers_low[0x20]; 1686 1687 u8 ether_stats_collisions_high[0x20]; 1688 1689 u8 ether_stats_collisions_low[0x20]; 1690 1691 u8 ether_stats_pkts64octets_high[0x20]; 1692 1693 u8 ether_stats_pkts64octets_low[0x20]; 1694 1695 u8 ether_stats_pkts65to127octets_high[0x20]; 1696 1697 u8 ether_stats_pkts65to127octets_low[0x20]; 1698 1699 u8 ether_stats_pkts128to255octets_high[0x20]; 1700 1701 u8 ether_stats_pkts128to255octets_low[0x20]; 1702 1703 u8 ether_stats_pkts256to511octets_high[0x20]; 1704 1705 u8 ether_stats_pkts256to511octets_low[0x20]; 1706 1707 u8 ether_stats_pkts512to1023octets_high[0x20]; 1708 1709 u8 ether_stats_pkts512to1023octets_low[0x20]; 1710 1711 u8 ether_stats_pkts1024to1518octets_high[0x20]; 1712 1713 u8 ether_stats_pkts1024to1518octets_low[0x20]; 1714 1715 u8 ether_stats_pkts1519to2047octets_high[0x20]; 1716 1717 u8 ether_stats_pkts1519to2047octets_low[0x20]; 1718 1719 u8 ether_stats_pkts2048to4095octets_high[0x20]; 1720 1721 u8 ether_stats_pkts2048to4095octets_low[0x20]; 1722 1723 u8 ether_stats_pkts4096to8191octets_high[0x20]; 1724 1725 u8 ether_stats_pkts4096to8191octets_low[0x20]; 1726 1727 u8 ether_stats_pkts8192to10239octets_high[0x20]; 1728 1729 u8 ether_stats_pkts8192to10239octets_low[0x20]; 1730 1731 u8 reserved_at_540[0x280]; 1732 }; 1733 1734 struct mlx5_ifc_eth_2863_cntrs_grp_data_layout_bits { 1735 u8 if_in_octets_high[0x20]; 1736 1737 u8 if_in_octets_low[0x20]; 1738 1739 u8 if_in_ucast_pkts_high[0x20]; 1740 1741 u8 if_in_ucast_pkts_low[0x20]; 1742 1743 u8 if_in_discards_high[0x20]; 1744 1745 u8 if_in_discards_low[0x20]; 1746 1747 u8 if_in_errors_high[0x20]; 1748 1749 u8 if_in_errors_low[0x20]; 1750 1751 u8 if_in_unknown_protos_high[0x20]; 1752 1753 u8 if_in_unknown_protos_low[0x20]; 1754 1755 u8 if_out_octets_high[0x20]; 1756 1757 u8 if_out_octets_low[0x20]; 1758 1759 u8 if_out_ucast_pkts_high[0x20]; 1760 1761 u8 if_out_ucast_pkts_low[0x20]; 1762 1763 u8 if_out_discards_high[0x20]; 1764 1765 u8 if_out_discards_low[0x20]; 1766 1767 u8 if_out_errors_high[0x20]; 1768 1769 u8 if_out_errors_low[0x20]; 1770 1771 u8 if_in_multicast_pkts_high[0x20]; 1772 1773 u8 if_in_multicast_pkts_low[0x20]; 1774 1775 u8 if_in_broadcast_pkts_high[0x20]; 1776 1777 u8 if_in_broadcast_pkts_low[0x20]; 1778 1779 u8 if_out_multicast_pkts_high[0x20]; 1780 1781 u8 if_out_multicast_pkts_low[0x20]; 1782 1783 u8 if_out_broadcast_pkts_high[0x20]; 1784 1785 u8 if_out_broadcast_pkts_low[0x20]; 1786 1787 u8 reserved_at_340[0x480]; 1788 }; 1789 1790 struct mlx5_ifc_eth_802_3_cntrs_grp_data_layout_bits { 1791 u8 a_frames_transmitted_ok_high[0x20]; 1792 1793 u8 a_frames_transmitted_ok_low[0x20]; 1794 1795 u8 a_frames_received_ok_high[0x20]; 1796 1797 u8 a_frames_received_ok_low[0x20]; 1798 1799 u8 a_frame_check_sequence_errors_high[0x20]; 1800 1801 u8 a_frame_check_sequence_errors_low[0x20]; 1802 1803 u8 a_alignment_errors_high[0x20]; 1804 1805 u8 a_alignment_errors_low[0x20]; 1806 1807 u8 a_octets_transmitted_ok_high[0x20]; 1808 1809 u8 a_octets_transmitted_ok_low[0x20]; 1810 1811 u8 a_octets_received_ok_high[0x20]; 1812 1813 u8 a_octets_received_ok_low[0x20]; 1814 1815 u8 a_multicast_frames_xmitted_ok_high[0x20]; 1816 1817 u8 a_multicast_frames_xmitted_ok_low[0x20]; 1818 1819 u8 a_broadcast_frames_xmitted_ok_high[0x20]; 1820 1821 u8 a_broadcast_frames_xmitted_ok_low[0x20]; 1822 1823 u8 a_multicast_frames_received_ok_high[0x20]; 1824 1825 u8 a_multicast_frames_received_ok_low[0x20]; 1826 1827 u8 a_broadcast_frames_received_ok_high[0x20]; 1828 1829 u8 a_broadcast_frames_received_ok_low[0x20]; 1830 1831 u8 a_in_range_length_errors_high[0x20]; 1832 1833 u8 a_in_range_length_errors_low[0x20]; 1834 1835 u8 a_out_of_range_length_field_high[0x20]; 1836 1837 u8 a_out_of_range_length_field_low[0x20]; 1838 1839 u8 a_frame_too_long_errors_high[0x20]; 1840 1841 u8 a_frame_too_long_errors_low[0x20]; 1842 1843 u8 a_symbol_error_during_carrier_high[0x20]; 1844 1845 u8 a_symbol_error_during_carrier_low[0x20]; 1846 1847 u8 a_mac_control_frames_transmitted_high[0x20]; 1848 1849 u8 a_mac_control_frames_transmitted_low[0x20]; 1850 1851 u8 a_mac_control_frames_received_high[0x20]; 1852 1853 u8 a_mac_control_frames_received_low[0x20]; 1854 1855 u8 a_unsupported_opcodes_received_high[0x20]; 1856 1857 u8 a_unsupported_opcodes_received_low[0x20]; 1858 1859 u8 a_pause_mac_ctrl_frames_received_high[0x20]; 1860 1861 u8 a_pause_mac_ctrl_frames_received_low[0x20]; 1862 1863 u8 a_pause_mac_ctrl_frames_transmitted_high[0x20]; 1864 1865 u8 a_pause_mac_ctrl_frames_transmitted_low[0x20]; 1866 1867 u8 reserved_at_4c0[0x300]; 1868 }; 1869 1870 struct mlx5_ifc_pcie_perf_cntrs_grp_data_layout_bits { 1871 u8 life_time_counter_high[0x20]; 1872 1873 u8 life_time_counter_low[0x20]; 1874 1875 u8 rx_errors[0x20]; 1876 1877 u8 tx_errors[0x20]; 1878 1879 u8 l0_to_recovery_eieos[0x20]; 1880 1881 u8 l0_to_recovery_ts[0x20]; 1882 1883 u8 l0_to_recovery_framing[0x20]; 1884 1885 u8 l0_to_recovery_retrain[0x20]; 1886 1887 u8 crc_error_dllp[0x20]; 1888 1889 u8 crc_error_tlp[0x20]; 1890 1891 u8 tx_overflow_buffer_pkt_high[0x20]; 1892 1893 u8 tx_overflow_buffer_pkt_low[0x20]; 1894 1895 u8 outbound_stalled_reads[0x20]; 1896 1897 u8 outbound_stalled_writes[0x20]; 1898 1899 u8 outbound_stalled_reads_events[0x20]; 1900 1901 u8 outbound_stalled_writes_events[0x20]; 1902 1903 u8 reserved_at_200[0x5c0]; 1904 }; 1905 1906 struct mlx5_ifc_cmd_inter_comp_event_bits { 1907 u8 command_completion_vector[0x20]; 1908 1909 u8 reserved_at_20[0xc0]; 1910 }; 1911 1912 struct mlx5_ifc_stall_vl_event_bits { 1913 u8 reserved_at_0[0x18]; 1914 u8 port_num[0x1]; 1915 u8 reserved_at_19[0x3]; 1916 u8 vl[0x4]; 1917 1918 u8 reserved_at_20[0xa0]; 1919 }; 1920 1921 struct mlx5_ifc_db_bf_congestion_event_bits { 1922 u8 event_subtype[0x8]; 1923 u8 reserved_at_8[0x8]; 1924 u8 congestion_level[0x8]; 1925 u8 reserved_at_18[0x8]; 1926 1927 u8 reserved_at_20[0xa0]; 1928 }; 1929 1930 struct mlx5_ifc_gpio_event_bits { 1931 u8 reserved_at_0[0x60]; 1932 1933 u8 gpio_event_hi[0x20]; 1934 1935 u8 gpio_event_lo[0x20]; 1936 1937 u8 reserved_at_a0[0x40]; 1938 }; 1939 1940 struct mlx5_ifc_port_state_change_event_bits { 1941 u8 reserved_at_0[0x40]; 1942 1943 u8 port_num[0x4]; 1944 u8 reserved_at_44[0x1c]; 1945 1946 u8 reserved_at_60[0x80]; 1947 }; 1948 1949 struct mlx5_ifc_dropped_packet_logged_bits { 1950 u8 reserved_at_0[0xe0]; 1951 }; 1952 1953 enum { 1954 MLX5_CQ_ERROR_SYNDROME_CQ_OVERRUN = 0x1, 1955 MLX5_CQ_ERROR_SYNDROME_CQ_ACCESS_VIOLATION_ERROR = 0x2, 1956 }; 1957 1958 struct mlx5_ifc_cq_error_bits { 1959 u8 reserved_at_0[0x8]; 1960 u8 cqn[0x18]; 1961 1962 u8 reserved_at_20[0x20]; 1963 1964 u8 reserved_at_40[0x18]; 1965 u8 syndrome[0x8]; 1966 1967 u8 reserved_at_60[0x80]; 1968 }; 1969 1970 struct mlx5_ifc_rdma_page_fault_event_bits { 1971 u8 bytes_committed[0x20]; 1972 1973 u8 r_key[0x20]; 1974 1975 u8 reserved_at_40[0x10]; 1976 u8 packet_len[0x10]; 1977 1978 u8 rdma_op_len[0x20]; 1979 1980 u8 rdma_va[0x40]; 1981 1982 u8 reserved_at_c0[0x5]; 1983 u8 rdma[0x1]; 1984 u8 write[0x1]; 1985 u8 requestor[0x1]; 1986 u8 qp_number[0x18]; 1987 }; 1988 1989 struct mlx5_ifc_wqe_associated_page_fault_event_bits { 1990 u8 bytes_committed[0x20]; 1991 1992 u8 reserved_at_20[0x10]; 1993 u8 wqe_index[0x10]; 1994 1995 u8 reserved_at_40[0x10]; 1996 u8 len[0x10]; 1997 1998 u8 reserved_at_60[0x60]; 1999 2000 u8 reserved_at_c0[0x5]; 2001 u8 rdma[0x1]; 2002 u8 write_read[0x1]; 2003 u8 requestor[0x1]; 2004 u8 qpn[0x18]; 2005 }; 2006 2007 struct mlx5_ifc_qp_events_bits { 2008 u8 reserved_at_0[0xa0]; 2009 2010 u8 type[0x8]; 2011 u8 reserved_at_a8[0x18]; 2012 2013 u8 reserved_at_c0[0x8]; 2014 u8 qpn_rqn_sqn[0x18]; 2015 }; 2016 2017 struct mlx5_ifc_dct_events_bits { 2018 u8 reserved_at_0[0xc0]; 2019 2020 u8 reserved_at_c0[0x8]; 2021 u8 dct_number[0x18]; 2022 }; 2023 2024 struct mlx5_ifc_comp_event_bits { 2025 u8 reserved_at_0[0xc0]; 2026 2027 u8 reserved_at_c0[0x8]; 2028 u8 cq_number[0x18]; 2029 }; 2030 2031 enum { 2032 MLX5_QPC_STATE_RST = 0x0, 2033 MLX5_QPC_STATE_INIT = 0x1, 2034 MLX5_QPC_STATE_RTR = 0x2, 2035 MLX5_QPC_STATE_RTS = 0x3, 2036 MLX5_QPC_STATE_SQER = 0x4, 2037 MLX5_QPC_STATE_ERR = 0x6, 2038 MLX5_QPC_STATE_SQD = 0x7, 2039 MLX5_QPC_STATE_SUSPENDED = 0x9, 2040 }; 2041 2042 enum { 2043 MLX5_QPC_ST_RC = 0x0, 2044 MLX5_QPC_ST_UC = 0x1, 2045 MLX5_QPC_ST_UD = 0x2, 2046 MLX5_QPC_ST_XRC = 0x3, 2047 MLX5_QPC_ST_DCI = 0x5, 2048 MLX5_QPC_ST_QP0 = 0x7, 2049 MLX5_QPC_ST_QP1 = 0x8, 2050 MLX5_QPC_ST_RAW_DATAGRAM = 0x9, 2051 MLX5_QPC_ST_REG_UMR = 0xc, 2052 }; 2053 2054 enum { 2055 MLX5_QPC_PM_STATE_ARMED = 0x0, 2056 MLX5_QPC_PM_STATE_REARM = 0x1, 2057 MLX5_QPC_PM_STATE_RESERVED = 0x2, 2058 MLX5_QPC_PM_STATE_MIGRATED = 0x3, 2059 }; 2060 2061 enum { 2062 MLX5_QPC_OFFLOAD_TYPE_RNDV = 0x1, 2063 }; 2064 2065 enum { 2066 MLX5_QPC_END_PADDING_MODE_SCATTER_AS_IS = 0x0, 2067 MLX5_QPC_END_PADDING_MODE_PAD_TO_CACHE_LINE_ALIGNMENT = 0x1, 2068 }; 2069 2070 enum { 2071 MLX5_QPC_MTU_256_BYTES = 0x1, 2072 MLX5_QPC_MTU_512_BYTES = 0x2, 2073 MLX5_QPC_MTU_1K_BYTES = 0x3, 2074 MLX5_QPC_MTU_2K_BYTES = 0x4, 2075 MLX5_QPC_MTU_4K_BYTES = 0x5, 2076 MLX5_QPC_MTU_RAW_ETHERNET_QP = 0x7, 2077 }; 2078 2079 enum { 2080 MLX5_QPC_ATOMIC_MODE_IB_SPEC = 0x1, 2081 MLX5_QPC_ATOMIC_MODE_ONLY_8B = 0x2, 2082 MLX5_QPC_ATOMIC_MODE_UP_TO_8B = 0x3, 2083 MLX5_QPC_ATOMIC_MODE_UP_TO_16B = 0x4, 2084 MLX5_QPC_ATOMIC_MODE_UP_TO_32B = 0x5, 2085 MLX5_QPC_ATOMIC_MODE_UP_TO_64B = 0x6, 2086 MLX5_QPC_ATOMIC_MODE_UP_TO_128B = 0x7, 2087 MLX5_QPC_ATOMIC_MODE_UP_TO_256B = 0x8, 2088 }; 2089 2090 enum { 2091 MLX5_QPC_CS_REQ_DISABLE = 0x0, 2092 MLX5_QPC_CS_REQ_UP_TO_32B = 0x11, 2093 MLX5_QPC_CS_REQ_UP_TO_64B = 0x22, 2094 }; 2095 2096 enum { 2097 MLX5_QPC_CS_RES_DISABLE = 0x0, 2098 MLX5_QPC_CS_RES_UP_TO_32B = 0x1, 2099 MLX5_QPC_CS_RES_UP_TO_64B = 0x2, 2100 }; 2101 2102 struct mlx5_ifc_qpc_bits { 2103 u8 state[0x4]; 2104 u8 lag_tx_port_affinity[0x4]; 2105 u8 st[0x8]; 2106 u8 reserved_at_10[0x3]; 2107 u8 pm_state[0x2]; 2108 u8 reserved_at_15[0x3]; 2109 u8 offload_type[0x4]; 2110 u8 end_padding_mode[0x2]; 2111 u8 reserved_at_1e[0x2]; 2112 2113 u8 wq_signature[0x1]; 2114 u8 block_lb_mc[0x1]; 2115 u8 atomic_like_write_en[0x1]; 2116 u8 latency_sensitive[0x1]; 2117 u8 reserved_at_24[0x1]; 2118 u8 drain_sigerr[0x1]; 2119 u8 reserved_at_26[0x2]; 2120 u8 pd[0x18]; 2121 2122 u8 mtu[0x3]; 2123 u8 log_msg_max[0x5]; 2124 u8 reserved_at_48[0x1]; 2125 u8 log_rq_size[0x4]; 2126 u8 log_rq_stride[0x3]; 2127 u8 no_sq[0x1]; 2128 u8 log_sq_size[0x4]; 2129 u8 reserved_at_55[0x6]; 2130 u8 rlky[0x1]; 2131 u8 ulp_stateless_offload_mode[0x4]; 2132 2133 u8 counter_set_id[0x8]; 2134 u8 uar_page[0x18]; 2135 2136 u8 reserved_at_80[0x8]; 2137 u8 user_index[0x18]; 2138 2139 u8 reserved_at_a0[0x3]; 2140 u8 log_page_size[0x5]; 2141 u8 remote_qpn[0x18]; 2142 2143 struct mlx5_ifc_ads_bits primary_address_path; 2144 2145 struct mlx5_ifc_ads_bits secondary_address_path; 2146 2147 u8 log_ack_req_freq[0x4]; 2148 u8 reserved_at_384[0x4]; 2149 u8 log_sra_max[0x3]; 2150 u8 reserved_at_38b[0x2]; 2151 u8 retry_count[0x3]; 2152 u8 rnr_retry[0x3]; 2153 u8 reserved_at_393[0x1]; 2154 u8 fre[0x1]; 2155 u8 cur_rnr_retry[0x3]; 2156 u8 cur_retry_count[0x3]; 2157 u8 reserved_at_39b[0x5]; 2158 2159 u8 reserved_at_3a0[0x20]; 2160 2161 u8 reserved_at_3c0[0x8]; 2162 u8 next_send_psn[0x18]; 2163 2164 u8 reserved_at_3e0[0x8]; 2165 u8 cqn_snd[0x18]; 2166 2167 u8 reserved_at_400[0x8]; 2168 u8 deth_sqpn[0x18]; 2169 2170 u8 reserved_at_420[0x20]; 2171 2172 u8 reserved_at_440[0x8]; 2173 u8 last_acked_psn[0x18]; 2174 2175 u8 reserved_at_460[0x8]; 2176 u8 ssn[0x18]; 2177 2178 u8 reserved_at_480[0x8]; 2179 u8 log_rra_max[0x3]; 2180 u8 reserved_at_48b[0x1]; 2181 u8 atomic_mode[0x4]; 2182 u8 rre[0x1]; 2183 u8 rwe[0x1]; 2184 u8 rae[0x1]; 2185 u8 reserved_at_493[0x1]; 2186 u8 page_offset[0x6]; 2187 u8 reserved_at_49a[0x3]; 2188 u8 cd_slave_receive[0x1]; 2189 u8 cd_slave_send[0x1]; 2190 u8 cd_master[0x1]; 2191 2192 u8 reserved_at_4a0[0x3]; 2193 u8 min_rnr_nak[0x5]; 2194 u8 next_rcv_psn[0x18]; 2195 2196 u8 reserved_at_4c0[0x8]; 2197 u8 xrcd[0x18]; 2198 2199 u8 reserved_at_4e0[0x8]; 2200 u8 cqn_rcv[0x18]; 2201 2202 u8 dbr_addr[0x40]; 2203 2204 u8 q_key[0x20]; 2205 2206 u8 reserved_at_560[0x5]; 2207 u8 rq_type[0x3]; 2208 u8 srqn_rmpn_xrqn[0x18]; 2209 2210 u8 reserved_at_580[0x8]; 2211 u8 rmsn[0x18]; 2212 2213 u8 hw_sq_wqebb_counter[0x10]; 2214 u8 sw_sq_wqebb_counter[0x10]; 2215 2216 u8 hw_rq_counter[0x20]; 2217 2218 u8 sw_rq_counter[0x20]; 2219 2220 u8 reserved_at_600[0x20]; 2221 2222 u8 reserved_at_620[0xf]; 2223 u8 cgs[0x1]; 2224 u8 cs_req[0x8]; 2225 u8 cs_res[0x8]; 2226 2227 u8 dc_access_key[0x40]; 2228 2229 u8 reserved_at_680[0xc0]; 2230 }; 2231 2232 struct mlx5_ifc_roce_addr_layout_bits { 2233 u8 source_l3_address[16][0x8]; 2234 2235 u8 reserved_at_80[0x3]; 2236 u8 vlan_valid[0x1]; 2237 u8 vlan_id[0xc]; 2238 u8 source_mac_47_32[0x10]; 2239 2240 u8 source_mac_31_0[0x20]; 2241 2242 u8 reserved_at_c0[0x14]; 2243 u8 roce_l3_type[0x4]; 2244 u8 roce_version[0x8]; 2245 2246 u8 reserved_at_e0[0x20]; 2247 }; 2248 2249 union mlx5_ifc_hca_cap_union_bits { 2250 struct mlx5_ifc_cmd_hca_cap_bits cmd_hca_cap; 2251 struct mlx5_ifc_odp_cap_bits odp_cap; 2252 struct mlx5_ifc_atomic_caps_bits atomic_caps; 2253 struct mlx5_ifc_roce_cap_bits roce_cap; 2254 struct mlx5_ifc_per_protocol_networking_offload_caps_bits per_protocol_networking_offload_caps; 2255 struct mlx5_ifc_flow_table_nic_cap_bits flow_table_nic_cap; 2256 struct mlx5_ifc_flow_table_eswitch_cap_bits flow_table_eswitch_cap; 2257 struct mlx5_ifc_e_switch_cap_bits e_switch_cap; 2258 struct mlx5_ifc_vector_calc_cap_bits vector_calc_cap; 2259 struct mlx5_ifc_qos_cap_bits qos_cap; 2260 struct mlx5_ifc_fpga_cap_bits fpga_cap; 2261 u8 reserved_at_0[0x8000]; 2262 }; 2263 2264 enum { 2265 MLX5_FLOW_CONTEXT_ACTION_ALLOW = 0x1, 2266 MLX5_FLOW_CONTEXT_ACTION_DROP = 0x2, 2267 MLX5_FLOW_CONTEXT_ACTION_FWD_DEST = 0x4, 2268 MLX5_FLOW_CONTEXT_ACTION_COUNT = 0x8, 2269 MLX5_FLOW_CONTEXT_ACTION_ENCAP = 0x10, 2270 MLX5_FLOW_CONTEXT_ACTION_DECAP = 0x20, 2271 MLX5_FLOW_CONTEXT_ACTION_MOD_HDR = 0x40, 2272 }; 2273 2274 struct mlx5_ifc_flow_context_bits { 2275 u8 reserved_at_0[0x20]; 2276 2277 u8 group_id[0x20]; 2278 2279 u8 reserved_at_40[0x8]; 2280 u8 flow_tag[0x18]; 2281 2282 u8 reserved_at_60[0x10]; 2283 u8 action[0x10]; 2284 2285 u8 reserved_at_80[0x8]; 2286 u8 destination_list_size[0x18]; 2287 2288 u8 reserved_at_a0[0x8]; 2289 u8 flow_counter_list_size[0x18]; 2290 2291 u8 encap_id[0x20]; 2292 2293 u8 modify_header_id[0x20]; 2294 2295 u8 reserved_at_100[0x100]; 2296 2297 struct mlx5_ifc_fte_match_param_bits match_value; 2298 2299 u8 reserved_at_1200[0x600]; 2300 2301 union mlx5_ifc_dest_format_struct_flow_counter_list_auto_bits destination[0]; 2302 }; 2303 2304 enum { 2305 MLX5_XRC_SRQC_STATE_GOOD = 0x0, 2306 MLX5_XRC_SRQC_STATE_ERROR = 0x1, 2307 }; 2308 2309 struct mlx5_ifc_xrc_srqc_bits { 2310 u8 state[0x4]; 2311 u8 log_xrc_srq_size[0x4]; 2312 u8 reserved_at_8[0x18]; 2313 2314 u8 wq_signature[0x1]; 2315 u8 cont_srq[0x1]; 2316 u8 reserved_at_22[0x1]; 2317 u8 rlky[0x1]; 2318 u8 basic_cyclic_rcv_wqe[0x1]; 2319 u8 log_rq_stride[0x3]; 2320 u8 xrcd[0x18]; 2321 2322 u8 page_offset[0x6]; 2323 u8 reserved_at_46[0x2]; 2324 u8 cqn[0x18]; 2325 2326 u8 reserved_at_60[0x20]; 2327 2328 u8 user_index_equal_xrc_srqn[0x1]; 2329 u8 reserved_at_81[0x1]; 2330 u8 log_page_size[0x6]; 2331 u8 user_index[0x18]; 2332 2333 u8 reserved_at_a0[0x20]; 2334 2335 u8 reserved_at_c0[0x8]; 2336 u8 pd[0x18]; 2337 2338 u8 lwm[0x10]; 2339 u8 wqe_cnt[0x10]; 2340 2341 u8 reserved_at_100[0x40]; 2342 2343 u8 db_record_addr_h[0x20]; 2344 2345 u8 db_record_addr_l[0x1e]; 2346 u8 reserved_at_17e[0x2]; 2347 2348 u8 reserved_at_180[0x80]; 2349 }; 2350 2351 struct mlx5_ifc_traffic_counter_bits { 2352 u8 packets[0x40]; 2353 2354 u8 octets[0x40]; 2355 }; 2356 2357 struct mlx5_ifc_tisc_bits { 2358 u8 strict_lag_tx_port_affinity[0x1]; 2359 u8 reserved_at_1[0x3]; 2360 u8 lag_tx_port_affinity[0x04]; 2361 2362 u8 reserved_at_8[0x4]; 2363 u8 prio[0x4]; 2364 u8 reserved_at_10[0x10]; 2365 2366 u8 reserved_at_20[0x100]; 2367 2368 u8 reserved_at_120[0x8]; 2369 u8 transport_domain[0x18]; 2370 2371 u8 reserved_at_140[0x8]; 2372 u8 underlay_qpn[0x18]; 2373 u8 reserved_at_160[0x3a0]; 2374 }; 2375 2376 enum { 2377 MLX5_TIRC_DISP_TYPE_DIRECT = 0x0, 2378 MLX5_TIRC_DISP_TYPE_INDIRECT = 0x1, 2379 }; 2380 2381 enum { 2382 MLX5_TIRC_LRO_ENABLE_MASK_IPV4_LRO = 0x1, 2383 MLX5_TIRC_LRO_ENABLE_MASK_IPV6_LRO = 0x2, 2384 }; 2385 2386 enum { 2387 MLX5_RX_HASH_FN_NONE = 0x0, 2388 MLX5_RX_HASH_FN_INVERTED_XOR8 = 0x1, 2389 MLX5_RX_HASH_FN_TOEPLITZ = 0x2, 2390 }; 2391 2392 enum { 2393 MLX5_TIRC_SELF_LB_BLOCK_BLOCK_UNICAST_ = 0x1, 2394 MLX5_TIRC_SELF_LB_BLOCK_BLOCK_MULTICAST_ = 0x2, 2395 }; 2396 2397 struct mlx5_ifc_tirc_bits { 2398 u8 reserved_at_0[0x20]; 2399 2400 u8 disp_type[0x4]; 2401 u8 reserved_at_24[0x1c]; 2402 2403 u8 reserved_at_40[0x40]; 2404 2405 u8 reserved_at_80[0x4]; 2406 u8 lro_timeout_period_usecs[0x10]; 2407 u8 lro_enable_mask[0x4]; 2408 u8 lro_max_ip_payload_size[0x8]; 2409 2410 u8 reserved_at_a0[0x40]; 2411 2412 u8 reserved_at_e0[0x8]; 2413 u8 inline_rqn[0x18]; 2414 2415 u8 rx_hash_symmetric[0x1]; 2416 u8 reserved_at_101[0x1]; 2417 u8 tunneled_offload_en[0x1]; 2418 u8 reserved_at_103[0x5]; 2419 u8 indirect_table[0x18]; 2420 2421 u8 rx_hash_fn[0x4]; 2422 u8 reserved_at_124[0x2]; 2423 u8 self_lb_block[0x2]; 2424 u8 transport_domain[0x18]; 2425 2426 u8 rx_hash_toeplitz_key[10][0x20]; 2427 2428 struct mlx5_ifc_rx_hash_field_select_bits rx_hash_field_selector_outer; 2429 2430 struct mlx5_ifc_rx_hash_field_select_bits rx_hash_field_selector_inner; 2431 2432 u8 reserved_at_2c0[0x4c0]; 2433 }; 2434 2435 enum { 2436 MLX5_SRQC_STATE_GOOD = 0x0, 2437 MLX5_SRQC_STATE_ERROR = 0x1, 2438 }; 2439 2440 struct mlx5_ifc_srqc_bits { 2441 u8 state[0x4]; 2442 u8 log_srq_size[0x4]; 2443 u8 reserved_at_8[0x18]; 2444 2445 u8 wq_signature[0x1]; 2446 u8 cont_srq[0x1]; 2447 u8 reserved_at_22[0x1]; 2448 u8 rlky[0x1]; 2449 u8 reserved_at_24[0x1]; 2450 u8 log_rq_stride[0x3]; 2451 u8 xrcd[0x18]; 2452 2453 u8 page_offset[0x6]; 2454 u8 reserved_at_46[0x2]; 2455 u8 cqn[0x18]; 2456 2457 u8 reserved_at_60[0x20]; 2458 2459 u8 reserved_at_80[0x2]; 2460 u8 log_page_size[0x6]; 2461 u8 reserved_at_88[0x18]; 2462 2463 u8 reserved_at_a0[0x20]; 2464 2465 u8 reserved_at_c0[0x8]; 2466 u8 pd[0x18]; 2467 2468 u8 lwm[0x10]; 2469 u8 wqe_cnt[0x10]; 2470 2471 u8 reserved_at_100[0x40]; 2472 2473 u8 dbr_addr[0x40]; 2474 2475 u8 reserved_at_180[0x80]; 2476 }; 2477 2478 enum { 2479 MLX5_SQC_STATE_RST = 0x0, 2480 MLX5_SQC_STATE_RDY = 0x1, 2481 MLX5_SQC_STATE_ERR = 0x3, 2482 }; 2483 2484 struct mlx5_ifc_sqc_bits { 2485 u8 rlky[0x1]; 2486 u8 cd_master[0x1]; 2487 u8 fre[0x1]; 2488 u8 flush_in_error_en[0x1]; 2489 u8 allow_multi_pkt_send_wqe[0x1]; 2490 u8 min_wqe_inline_mode[0x3]; 2491 u8 state[0x4]; 2492 u8 reg_umr[0x1]; 2493 u8 allow_swp[0x1]; 2494 u8 reserved_at_e[0x12]; 2495 2496 u8 reserved_at_20[0x8]; 2497 u8 user_index[0x18]; 2498 2499 u8 reserved_at_40[0x8]; 2500 u8 cqn[0x18]; 2501 2502 u8 reserved_at_60[0x90]; 2503 2504 u8 packet_pacing_rate_limit_index[0x10]; 2505 u8 tis_lst_sz[0x10]; 2506 u8 reserved_at_110[0x10]; 2507 2508 u8 reserved_at_120[0x40]; 2509 2510 u8 reserved_at_160[0x8]; 2511 u8 tis_num_0[0x18]; 2512 2513 struct mlx5_ifc_wq_bits wq; 2514 }; 2515 2516 enum { 2517 SCHEDULING_CONTEXT_ELEMENT_TYPE_TSAR = 0x0, 2518 SCHEDULING_CONTEXT_ELEMENT_TYPE_VPORT = 0x1, 2519 SCHEDULING_CONTEXT_ELEMENT_TYPE_VPORT_TC = 0x2, 2520 SCHEDULING_CONTEXT_ELEMENT_TYPE_PARA_VPORT_TC = 0x3, 2521 }; 2522 2523 struct mlx5_ifc_scheduling_context_bits { 2524 u8 element_type[0x8]; 2525 u8 reserved_at_8[0x18]; 2526 2527 u8 element_attributes[0x20]; 2528 2529 u8 parent_element_id[0x20]; 2530 2531 u8 reserved_at_60[0x40]; 2532 2533 u8 bw_share[0x20]; 2534 2535 u8 max_average_bw[0x20]; 2536 2537 u8 reserved_at_e0[0x120]; 2538 }; 2539 2540 struct mlx5_ifc_rqtc_bits { 2541 u8 reserved_at_0[0xa0]; 2542 2543 u8 reserved_at_a0[0x10]; 2544 u8 rqt_max_size[0x10]; 2545 2546 u8 reserved_at_c0[0x10]; 2547 u8 rqt_actual_size[0x10]; 2548 2549 u8 reserved_at_e0[0x6a0]; 2550 2551 struct mlx5_ifc_rq_num_bits rq_num[0]; 2552 }; 2553 2554 enum { 2555 MLX5_RQC_MEM_RQ_TYPE_MEMORY_RQ_INLINE = 0x0, 2556 MLX5_RQC_MEM_RQ_TYPE_MEMORY_RQ_RMP = 0x1, 2557 }; 2558 2559 enum { 2560 MLX5_RQC_STATE_RST = 0x0, 2561 MLX5_RQC_STATE_RDY = 0x1, 2562 MLX5_RQC_STATE_ERR = 0x3, 2563 }; 2564 2565 struct mlx5_ifc_rqc_bits { 2566 u8 rlky[0x1]; 2567 u8 delay_drop_en[0x1]; 2568 u8 scatter_fcs[0x1]; 2569 u8 vsd[0x1]; 2570 u8 mem_rq_type[0x4]; 2571 u8 state[0x4]; 2572 u8 reserved_at_c[0x1]; 2573 u8 flush_in_error_en[0x1]; 2574 u8 reserved_at_e[0x12]; 2575 2576 u8 reserved_at_20[0x8]; 2577 u8 user_index[0x18]; 2578 2579 u8 reserved_at_40[0x8]; 2580 u8 cqn[0x18]; 2581 2582 u8 counter_set_id[0x8]; 2583 u8 reserved_at_68[0x18]; 2584 2585 u8 reserved_at_80[0x8]; 2586 u8 rmpn[0x18]; 2587 2588 u8 reserved_at_a0[0xe0]; 2589 2590 struct mlx5_ifc_wq_bits wq; 2591 }; 2592 2593 enum { 2594 MLX5_RMPC_STATE_RDY = 0x1, 2595 MLX5_RMPC_STATE_ERR = 0x3, 2596 }; 2597 2598 struct mlx5_ifc_rmpc_bits { 2599 u8 reserved_at_0[0x8]; 2600 u8 state[0x4]; 2601 u8 reserved_at_c[0x14]; 2602 2603 u8 basic_cyclic_rcv_wqe[0x1]; 2604 u8 reserved_at_21[0x1f]; 2605 2606 u8 reserved_at_40[0x140]; 2607 2608 struct mlx5_ifc_wq_bits wq; 2609 }; 2610 2611 struct mlx5_ifc_nic_vport_context_bits { 2612 u8 reserved_at_0[0x5]; 2613 u8 min_wqe_inline_mode[0x3]; 2614 u8 reserved_at_8[0x15]; 2615 u8 disable_mc_local_lb[0x1]; 2616 u8 disable_uc_local_lb[0x1]; 2617 u8 roce_en[0x1]; 2618 2619 u8 arm_change_event[0x1]; 2620 u8 reserved_at_21[0x1a]; 2621 u8 event_on_mtu[0x1]; 2622 u8 event_on_promisc_change[0x1]; 2623 u8 event_on_vlan_change[0x1]; 2624 u8 event_on_mc_address_change[0x1]; 2625 u8 event_on_uc_address_change[0x1]; 2626 2627 u8 reserved_at_40[0xc]; 2628 2629 u8 affiliation_criteria[0x4]; 2630 u8 affiliated_vhca_id[0x10]; 2631 2632 u8 reserved_at_60[0xd0]; 2633 2634 u8 mtu[0x10]; 2635 2636 u8 system_image_guid[0x40]; 2637 u8 port_guid[0x40]; 2638 u8 node_guid[0x40]; 2639 2640 u8 reserved_at_200[0x140]; 2641 u8 qkey_violation_counter[0x10]; 2642 u8 reserved_at_350[0x430]; 2643 2644 u8 promisc_uc[0x1]; 2645 u8 promisc_mc[0x1]; 2646 u8 promisc_all[0x1]; 2647 u8 reserved_at_783[0x2]; 2648 u8 allowed_list_type[0x3]; 2649 u8 reserved_at_788[0xc]; 2650 u8 allowed_list_size[0xc]; 2651 2652 struct mlx5_ifc_mac_address_layout_bits permanent_address; 2653 2654 u8 reserved_at_7e0[0x20]; 2655 2656 u8 current_uc_mac_address[0][0x40]; 2657 }; 2658 2659 enum { 2660 MLX5_MKC_ACCESS_MODE_PA = 0x0, 2661 MLX5_MKC_ACCESS_MODE_MTT = 0x1, 2662 MLX5_MKC_ACCESS_MODE_KLMS = 0x2, 2663 MLX5_MKC_ACCESS_MODE_KSM = 0x3, 2664 }; 2665 2666 struct mlx5_ifc_mkc_bits { 2667 u8 reserved_at_0[0x1]; 2668 u8 free[0x1]; 2669 u8 reserved_at_2[0xd]; 2670 u8 small_fence_on_rdma_read_response[0x1]; 2671 u8 umr_en[0x1]; 2672 u8 a[0x1]; 2673 u8 rw[0x1]; 2674 u8 rr[0x1]; 2675 u8 lw[0x1]; 2676 u8 lr[0x1]; 2677 u8 access_mode[0x2]; 2678 u8 reserved_at_18[0x8]; 2679 2680 u8 qpn[0x18]; 2681 u8 mkey_7_0[0x8]; 2682 2683 u8 reserved_at_40[0x20]; 2684 2685 u8 length64[0x1]; 2686 u8 bsf_en[0x1]; 2687 u8 sync_umr[0x1]; 2688 u8 reserved_at_63[0x2]; 2689 u8 expected_sigerr_count[0x1]; 2690 u8 reserved_at_66[0x1]; 2691 u8 en_rinval[0x1]; 2692 u8 pd[0x18]; 2693 2694 u8 start_addr[0x40]; 2695 2696 u8 len[0x40]; 2697 2698 u8 bsf_octword_size[0x20]; 2699 2700 u8 reserved_at_120[0x80]; 2701 2702 u8 translations_octword_size[0x20]; 2703 2704 u8 reserved_at_1c0[0x1b]; 2705 u8 log_page_size[0x5]; 2706 2707 u8 reserved_at_1e0[0x20]; 2708 }; 2709 2710 struct mlx5_ifc_pkey_bits { 2711 u8 reserved_at_0[0x10]; 2712 u8 pkey[0x10]; 2713 }; 2714 2715 struct mlx5_ifc_array128_auto_bits { 2716 u8 array128_auto[16][0x8]; 2717 }; 2718 2719 struct mlx5_ifc_hca_vport_context_bits { 2720 u8 field_select[0x20]; 2721 2722 u8 reserved_at_20[0xe0]; 2723 2724 u8 sm_virt_aware[0x1]; 2725 u8 has_smi[0x1]; 2726 u8 has_raw[0x1]; 2727 u8 grh_required[0x1]; 2728 u8 reserved_at_104[0xc]; 2729 u8 port_physical_state[0x4]; 2730 u8 vport_state_policy[0x4]; 2731 u8 port_state[0x4]; 2732 u8 vport_state[0x4]; 2733 2734 u8 reserved_at_120[0x20]; 2735 2736 u8 system_image_guid[0x40]; 2737 2738 u8 port_guid[0x40]; 2739 2740 u8 node_guid[0x40]; 2741 2742 u8 cap_mask1[0x20]; 2743 2744 u8 cap_mask1_field_select[0x20]; 2745 2746 u8 cap_mask2[0x20]; 2747 2748 u8 cap_mask2_field_select[0x20]; 2749 2750 u8 reserved_at_280[0x80]; 2751 2752 u8 lid[0x10]; 2753 u8 reserved_at_310[0x4]; 2754 u8 init_type_reply[0x4]; 2755 u8 lmc[0x3]; 2756 u8 subnet_timeout[0x5]; 2757 2758 u8 sm_lid[0x10]; 2759 u8 sm_sl[0x4]; 2760 u8 reserved_at_334[0xc]; 2761 2762 u8 qkey_violation_counter[0x10]; 2763 u8 pkey_violation_counter[0x10]; 2764 2765 u8 reserved_at_360[0xca0]; 2766 }; 2767 2768 struct mlx5_ifc_esw_vport_context_bits { 2769 u8 reserved_at_0[0x3]; 2770 u8 vport_svlan_strip[0x1]; 2771 u8 vport_cvlan_strip[0x1]; 2772 u8 vport_svlan_insert[0x1]; 2773 u8 vport_cvlan_insert[0x2]; 2774 u8 reserved_at_8[0x18]; 2775 2776 u8 reserved_at_20[0x20]; 2777 2778 u8 svlan_cfi[0x1]; 2779 u8 svlan_pcp[0x3]; 2780 u8 svlan_id[0xc]; 2781 u8 cvlan_cfi[0x1]; 2782 u8 cvlan_pcp[0x3]; 2783 u8 cvlan_id[0xc]; 2784 2785 u8 reserved_at_60[0x7a0]; 2786 }; 2787 2788 enum { 2789 MLX5_EQC_STATUS_OK = 0x0, 2790 MLX5_EQC_STATUS_EQ_WRITE_FAILURE = 0xa, 2791 }; 2792 2793 enum { 2794 MLX5_EQC_ST_ARMED = 0x9, 2795 MLX5_EQC_ST_FIRED = 0xa, 2796 }; 2797 2798 struct mlx5_ifc_eqc_bits { 2799 u8 status[0x4]; 2800 u8 reserved_at_4[0x9]; 2801 u8 ec[0x1]; 2802 u8 oi[0x1]; 2803 u8 reserved_at_f[0x5]; 2804 u8 st[0x4]; 2805 u8 reserved_at_18[0x8]; 2806 2807 u8 reserved_at_20[0x20]; 2808 2809 u8 reserved_at_40[0x14]; 2810 u8 page_offset[0x6]; 2811 u8 reserved_at_5a[0x6]; 2812 2813 u8 reserved_at_60[0x3]; 2814 u8 log_eq_size[0x5]; 2815 u8 uar_page[0x18]; 2816 2817 u8 reserved_at_80[0x20]; 2818 2819 u8 reserved_at_a0[0x18]; 2820 u8 intr[0x8]; 2821 2822 u8 reserved_at_c0[0x3]; 2823 u8 log_page_size[0x5]; 2824 u8 reserved_at_c8[0x18]; 2825 2826 u8 reserved_at_e0[0x60]; 2827 2828 u8 reserved_at_140[0x8]; 2829 u8 consumer_counter[0x18]; 2830 2831 u8 reserved_at_160[0x8]; 2832 u8 producer_counter[0x18]; 2833 2834 u8 reserved_at_180[0x80]; 2835 }; 2836 2837 enum { 2838 MLX5_DCTC_STATE_ACTIVE = 0x0, 2839 MLX5_DCTC_STATE_DRAINING = 0x1, 2840 MLX5_DCTC_STATE_DRAINED = 0x2, 2841 }; 2842 2843 enum { 2844 MLX5_DCTC_CS_RES_DISABLE = 0x0, 2845 MLX5_DCTC_CS_RES_NA = 0x1, 2846 MLX5_DCTC_CS_RES_UP_TO_64B = 0x2, 2847 }; 2848 2849 enum { 2850 MLX5_DCTC_MTU_256_BYTES = 0x1, 2851 MLX5_DCTC_MTU_512_BYTES = 0x2, 2852 MLX5_DCTC_MTU_1K_BYTES = 0x3, 2853 MLX5_DCTC_MTU_2K_BYTES = 0x4, 2854 MLX5_DCTC_MTU_4K_BYTES = 0x5, 2855 }; 2856 2857 struct mlx5_ifc_dctc_bits { 2858 u8 reserved_at_0[0x4]; 2859 u8 state[0x4]; 2860 u8 reserved_at_8[0x18]; 2861 2862 u8 reserved_at_20[0x8]; 2863 u8 user_index[0x18]; 2864 2865 u8 reserved_at_40[0x8]; 2866 u8 cqn[0x18]; 2867 2868 u8 counter_set_id[0x8]; 2869 u8 atomic_mode[0x4]; 2870 u8 rre[0x1]; 2871 u8 rwe[0x1]; 2872 u8 rae[0x1]; 2873 u8 atomic_like_write_en[0x1]; 2874 u8 latency_sensitive[0x1]; 2875 u8 rlky[0x1]; 2876 u8 free_ar[0x1]; 2877 u8 reserved_at_73[0xd]; 2878 2879 u8 reserved_at_80[0x8]; 2880 u8 cs_res[0x8]; 2881 u8 reserved_at_90[0x3]; 2882 u8 min_rnr_nak[0x5]; 2883 u8 reserved_at_98[0x8]; 2884 2885 u8 reserved_at_a0[0x8]; 2886 u8 srqn_xrqn[0x18]; 2887 2888 u8 reserved_at_c0[0x8]; 2889 u8 pd[0x18]; 2890 2891 u8 tclass[0x8]; 2892 u8 reserved_at_e8[0x4]; 2893 u8 flow_label[0x14]; 2894 2895 u8 dc_access_key[0x40]; 2896 2897 u8 reserved_at_140[0x5]; 2898 u8 mtu[0x3]; 2899 u8 port[0x8]; 2900 u8 pkey_index[0x10]; 2901 2902 u8 reserved_at_160[0x8]; 2903 u8 my_addr_index[0x8]; 2904 u8 reserved_at_170[0x8]; 2905 u8 hop_limit[0x8]; 2906 2907 u8 dc_access_key_violation_count[0x20]; 2908 2909 u8 reserved_at_1a0[0x14]; 2910 u8 dei_cfi[0x1]; 2911 u8 eth_prio[0x3]; 2912 u8 ecn[0x2]; 2913 u8 dscp[0x6]; 2914 2915 u8 reserved_at_1c0[0x40]; 2916 }; 2917 2918 enum { 2919 MLX5_CQC_STATUS_OK = 0x0, 2920 MLX5_CQC_STATUS_CQ_OVERFLOW = 0x9, 2921 MLX5_CQC_STATUS_CQ_WRITE_FAIL = 0xa, 2922 }; 2923 2924 enum { 2925 MLX5_CQC_CQE_SZ_64_BYTES = 0x0, 2926 MLX5_CQC_CQE_SZ_128_BYTES = 0x1, 2927 }; 2928 2929 enum { 2930 MLX5_CQC_ST_SOLICITED_NOTIFICATION_REQUEST_ARMED = 0x6, 2931 MLX5_CQC_ST_NOTIFICATION_REQUEST_ARMED = 0x9, 2932 MLX5_CQC_ST_FIRED = 0xa, 2933 }; 2934 2935 enum { 2936 MLX5_CQ_PERIOD_MODE_START_FROM_EQE = 0x0, 2937 MLX5_CQ_PERIOD_MODE_START_FROM_CQE = 0x1, 2938 MLX5_CQ_PERIOD_NUM_MODES 2939 }; 2940 2941 struct mlx5_ifc_cqc_bits { 2942 u8 status[0x4]; 2943 u8 reserved_at_4[0x4]; 2944 u8 cqe_sz[0x3]; 2945 u8 cc[0x1]; 2946 u8 reserved_at_c[0x1]; 2947 u8 scqe_break_moderation_en[0x1]; 2948 u8 oi[0x1]; 2949 u8 cq_period_mode[0x2]; 2950 u8 cqe_comp_en[0x1]; 2951 u8 mini_cqe_res_format[0x2]; 2952 u8 st[0x4]; 2953 u8 reserved_at_18[0x8]; 2954 2955 u8 reserved_at_20[0x20]; 2956 2957 u8 reserved_at_40[0x14]; 2958 u8 page_offset[0x6]; 2959 u8 reserved_at_5a[0x6]; 2960 2961 u8 reserved_at_60[0x3]; 2962 u8 log_cq_size[0x5]; 2963 u8 uar_page[0x18]; 2964 2965 u8 reserved_at_80[0x4]; 2966 u8 cq_period[0xc]; 2967 u8 cq_max_count[0x10]; 2968 2969 u8 reserved_at_a0[0x18]; 2970 u8 c_eqn[0x8]; 2971 2972 u8 reserved_at_c0[0x3]; 2973 u8 log_page_size[0x5]; 2974 u8 reserved_at_c8[0x18]; 2975 2976 u8 reserved_at_e0[0x20]; 2977 2978 u8 reserved_at_100[0x8]; 2979 u8 last_notified_index[0x18]; 2980 2981 u8 reserved_at_120[0x8]; 2982 u8 last_solicit_index[0x18]; 2983 2984 u8 reserved_at_140[0x8]; 2985 u8 consumer_counter[0x18]; 2986 2987 u8 reserved_at_160[0x8]; 2988 u8 producer_counter[0x18]; 2989 2990 u8 reserved_at_180[0x40]; 2991 2992 u8 dbr_addr[0x40]; 2993 }; 2994 2995 union mlx5_ifc_cong_control_roce_ecn_auto_bits { 2996 struct mlx5_ifc_cong_control_802_1qau_rp_bits cong_control_802_1qau_rp; 2997 struct mlx5_ifc_cong_control_r_roce_ecn_rp_bits cong_control_r_roce_ecn_rp; 2998 struct mlx5_ifc_cong_control_r_roce_ecn_np_bits cong_control_r_roce_ecn_np; 2999 u8 reserved_at_0[0x800]; 3000 }; 3001 3002 struct mlx5_ifc_query_adapter_param_block_bits { 3003 u8 reserved_at_0[0xc0]; 3004 3005 u8 reserved_at_c0[0x8]; 3006 u8 ieee_vendor_id[0x18]; 3007 3008 u8 reserved_at_e0[0x10]; 3009 u8 vsd_vendor_id[0x10]; 3010 3011 u8 vsd[208][0x8]; 3012 3013 u8 vsd_contd_psid[16][0x8]; 3014 }; 3015 3016 enum { 3017 MLX5_XRQC_STATE_GOOD = 0x0, 3018 MLX5_XRQC_STATE_ERROR = 0x1, 3019 }; 3020 3021 enum { 3022 MLX5_XRQC_TOPOLOGY_NO_SPECIAL_TOPOLOGY = 0x0, 3023 MLX5_XRQC_TOPOLOGY_TAG_MATCHING = 0x1, 3024 }; 3025 3026 enum { 3027 MLX5_XRQC_OFFLOAD_RNDV = 0x1, 3028 }; 3029 3030 struct mlx5_ifc_tag_matching_topology_context_bits { 3031 u8 log_matching_list_sz[0x4]; 3032 u8 reserved_at_4[0xc]; 3033 u8 append_next_index[0x10]; 3034 3035 u8 sw_phase_cnt[0x10]; 3036 u8 hw_phase_cnt[0x10]; 3037 3038 u8 reserved_at_40[0x40]; 3039 }; 3040 3041 struct mlx5_ifc_xrqc_bits { 3042 u8 state[0x4]; 3043 u8 rlkey[0x1]; 3044 u8 reserved_at_5[0xf]; 3045 u8 topology[0x4]; 3046 u8 reserved_at_18[0x4]; 3047 u8 offload[0x4]; 3048 3049 u8 reserved_at_20[0x8]; 3050 u8 user_index[0x18]; 3051 3052 u8 reserved_at_40[0x8]; 3053 u8 cqn[0x18]; 3054 3055 u8 reserved_at_60[0xa0]; 3056 3057 struct mlx5_ifc_tag_matching_topology_context_bits tag_matching_topology_context; 3058 3059 u8 reserved_at_180[0x280]; 3060 3061 struct mlx5_ifc_wq_bits wq; 3062 }; 3063 3064 union mlx5_ifc_modify_field_select_resize_field_select_auto_bits { 3065 struct mlx5_ifc_modify_field_select_bits modify_field_select; 3066 struct mlx5_ifc_resize_field_select_bits resize_field_select; 3067 u8 reserved_at_0[0x20]; 3068 }; 3069 3070 union mlx5_ifc_field_select_802_1_r_roce_auto_bits { 3071 struct mlx5_ifc_field_select_802_1qau_rp_bits field_select_802_1qau_rp; 3072 struct mlx5_ifc_field_select_r_roce_rp_bits field_select_r_roce_rp; 3073 struct mlx5_ifc_field_select_r_roce_np_bits field_select_r_roce_np; 3074 u8 reserved_at_0[0x20]; 3075 }; 3076 3077 union mlx5_ifc_eth_cntrs_grp_data_layout_auto_bits { 3078 struct mlx5_ifc_eth_802_3_cntrs_grp_data_layout_bits eth_802_3_cntrs_grp_data_layout; 3079 struct mlx5_ifc_eth_2863_cntrs_grp_data_layout_bits eth_2863_cntrs_grp_data_layout; 3080 struct mlx5_ifc_eth_2819_cntrs_grp_data_layout_bits eth_2819_cntrs_grp_data_layout; 3081 struct mlx5_ifc_eth_3635_cntrs_grp_data_layout_bits eth_3635_cntrs_grp_data_layout; 3082 struct mlx5_ifc_eth_extended_cntrs_grp_data_layout_bits eth_extended_cntrs_grp_data_layout; 3083 struct mlx5_ifc_eth_per_prio_grp_data_layout_bits eth_per_prio_grp_data_layout; 3084 struct mlx5_ifc_eth_per_traffic_grp_data_layout_bits eth_per_traffic_grp_data_layout; 3085 struct mlx5_ifc_ib_port_cntrs_grp_data_layout_bits ib_port_cntrs_grp_data_layout; 3086 struct mlx5_ifc_phys_layer_cntrs_bits phys_layer_cntrs; 3087 struct mlx5_ifc_phys_layer_statistical_cntrs_bits phys_layer_statistical_cntrs; 3088 u8 reserved_at_0[0x7c0]; 3089 }; 3090 3091 union mlx5_ifc_pcie_cntrs_grp_data_layout_auto_bits { 3092 struct mlx5_ifc_pcie_perf_cntrs_grp_data_layout_bits pcie_perf_cntrs_grp_data_layout; 3093 u8 reserved_at_0[0x7c0]; 3094 }; 3095 3096 union mlx5_ifc_event_auto_bits { 3097 struct mlx5_ifc_comp_event_bits comp_event; 3098 struct mlx5_ifc_dct_events_bits dct_events; 3099 struct mlx5_ifc_qp_events_bits qp_events; 3100 struct mlx5_ifc_wqe_associated_page_fault_event_bits wqe_associated_page_fault_event; 3101 struct mlx5_ifc_rdma_page_fault_event_bits rdma_page_fault_event; 3102 struct mlx5_ifc_cq_error_bits cq_error; 3103 struct mlx5_ifc_dropped_packet_logged_bits dropped_packet_logged; 3104 struct mlx5_ifc_port_state_change_event_bits port_state_change_event; 3105 struct mlx5_ifc_gpio_event_bits gpio_event; 3106 struct mlx5_ifc_db_bf_congestion_event_bits db_bf_congestion_event; 3107 struct mlx5_ifc_stall_vl_event_bits stall_vl_event; 3108 struct mlx5_ifc_cmd_inter_comp_event_bits cmd_inter_comp_event; 3109 u8 reserved_at_0[0xe0]; 3110 }; 3111 3112 struct mlx5_ifc_health_buffer_bits { 3113 u8 reserved_at_0[0x100]; 3114 3115 u8 assert_existptr[0x20]; 3116 3117 u8 assert_callra[0x20]; 3118 3119 u8 reserved_at_140[0x40]; 3120 3121 u8 fw_version[0x20]; 3122 3123 u8 hw_id[0x20]; 3124 3125 u8 reserved_at_1c0[0x20]; 3126 3127 u8 irisc_index[0x8]; 3128 u8 synd[0x8]; 3129 u8 ext_synd[0x10]; 3130 }; 3131 3132 struct mlx5_ifc_register_loopback_control_bits { 3133 u8 no_lb[0x1]; 3134 u8 reserved_at_1[0x7]; 3135 u8 port[0x8]; 3136 u8 reserved_at_10[0x10]; 3137 3138 u8 reserved_at_20[0x60]; 3139 }; 3140 3141 struct mlx5_ifc_vport_tc_element_bits { 3142 u8 traffic_class[0x4]; 3143 u8 reserved_at_4[0xc]; 3144 u8 vport_number[0x10]; 3145 }; 3146 3147 struct mlx5_ifc_vport_element_bits { 3148 u8 reserved_at_0[0x10]; 3149 u8 vport_number[0x10]; 3150 }; 3151 3152 enum { 3153 TSAR_ELEMENT_TSAR_TYPE_DWRR = 0x0, 3154 TSAR_ELEMENT_TSAR_TYPE_ROUND_ROBIN = 0x1, 3155 TSAR_ELEMENT_TSAR_TYPE_ETS = 0x2, 3156 }; 3157 3158 struct mlx5_ifc_tsar_element_bits { 3159 u8 reserved_at_0[0x8]; 3160 u8 tsar_type[0x8]; 3161 u8 reserved_at_10[0x10]; 3162 }; 3163 3164 enum { 3165 MLX5_TEARDOWN_HCA_OUT_FORCE_STATE_SUCCESS = 0x0, 3166 MLX5_TEARDOWN_HCA_OUT_FORCE_STATE_FAIL = 0x1, 3167 }; 3168 3169 struct mlx5_ifc_teardown_hca_out_bits { 3170 u8 status[0x8]; 3171 u8 reserved_at_8[0x18]; 3172 3173 u8 syndrome[0x20]; 3174 3175 u8 reserved_at_40[0x3f]; 3176 3177 u8 force_state[0x1]; 3178 }; 3179 3180 enum { 3181 MLX5_TEARDOWN_HCA_IN_PROFILE_GRACEFUL_CLOSE = 0x0, 3182 MLX5_TEARDOWN_HCA_IN_PROFILE_FORCE_CLOSE = 0x1, 3183 }; 3184 3185 struct mlx5_ifc_teardown_hca_in_bits { 3186 u8 opcode[0x10]; 3187 u8 reserved_at_10[0x10]; 3188 3189 u8 reserved_at_20[0x10]; 3190 u8 op_mod[0x10]; 3191 3192 u8 reserved_at_40[0x10]; 3193 u8 profile[0x10]; 3194 3195 u8 reserved_at_60[0x20]; 3196 }; 3197 3198 struct mlx5_ifc_sqerr2rts_qp_out_bits { 3199 u8 status[0x8]; 3200 u8 reserved_at_8[0x18]; 3201 3202 u8 syndrome[0x20]; 3203 3204 u8 reserved_at_40[0x40]; 3205 }; 3206 3207 struct mlx5_ifc_sqerr2rts_qp_in_bits { 3208 u8 opcode[0x10]; 3209 u8 reserved_at_10[0x10]; 3210 3211 u8 reserved_at_20[0x10]; 3212 u8 op_mod[0x10]; 3213 3214 u8 reserved_at_40[0x8]; 3215 u8 qpn[0x18]; 3216 3217 u8 reserved_at_60[0x20]; 3218 3219 u8 opt_param_mask[0x20]; 3220 3221 u8 reserved_at_a0[0x20]; 3222 3223 struct mlx5_ifc_qpc_bits qpc; 3224 3225 u8 reserved_at_800[0x80]; 3226 }; 3227 3228 struct mlx5_ifc_sqd2rts_qp_out_bits { 3229 u8 status[0x8]; 3230 u8 reserved_at_8[0x18]; 3231 3232 u8 syndrome[0x20]; 3233 3234 u8 reserved_at_40[0x40]; 3235 }; 3236 3237 struct mlx5_ifc_sqd2rts_qp_in_bits { 3238 u8 opcode[0x10]; 3239 u8 reserved_at_10[0x10]; 3240 3241 u8 reserved_at_20[0x10]; 3242 u8 op_mod[0x10]; 3243 3244 u8 reserved_at_40[0x8]; 3245 u8 qpn[0x18]; 3246 3247 u8 reserved_at_60[0x20]; 3248 3249 u8 opt_param_mask[0x20]; 3250 3251 u8 reserved_at_a0[0x20]; 3252 3253 struct mlx5_ifc_qpc_bits qpc; 3254 3255 u8 reserved_at_800[0x80]; 3256 }; 3257 3258 struct mlx5_ifc_set_roce_address_out_bits { 3259 u8 status[0x8]; 3260 u8 reserved_at_8[0x18]; 3261 3262 u8 syndrome[0x20]; 3263 3264 u8 reserved_at_40[0x40]; 3265 }; 3266 3267 struct mlx5_ifc_set_roce_address_in_bits { 3268 u8 opcode[0x10]; 3269 u8 reserved_at_10[0x10]; 3270 3271 u8 reserved_at_20[0x10]; 3272 u8 op_mod[0x10]; 3273 3274 u8 roce_address_index[0x10]; 3275 u8 reserved_at_50[0xc]; 3276 u8 vhca_port_num[0x4]; 3277 3278 u8 reserved_at_60[0x20]; 3279 3280 struct mlx5_ifc_roce_addr_layout_bits roce_address; 3281 }; 3282 3283 struct mlx5_ifc_set_mad_demux_out_bits { 3284 u8 status[0x8]; 3285 u8 reserved_at_8[0x18]; 3286 3287 u8 syndrome[0x20]; 3288 3289 u8 reserved_at_40[0x40]; 3290 }; 3291 3292 enum { 3293 MLX5_SET_MAD_DEMUX_IN_DEMUX_MODE_PASS_ALL = 0x0, 3294 MLX5_SET_MAD_DEMUX_IN_DEMUX_MODE_SELECTIVE = 0x2, 3295 }; 3296 3297 struct mlx5_ifc_set_mad_demux_in_bits { 3298 u8 opcode[0x10]; 3299 u8 reserved_at_10[0x10]; 3300 3301 u8 reserved_at_20[0x10]; 3302 u8 op_mod[0x10]; 3303 3304 u8 reserved_at_40[0x20]; 3305 3306 u8 reserved_at_60[0x6]; 3307 u8 demux_mode[0x2]; 3308 u8 reserved_at_68[0x18]; 3309 }; 3310 3311 struct mlx5_ifc_set_l2_table_entry_out_bits { 3312 u8 status[0x8]; 3313 u8 reserved_at_8[0x18]; 3314 3315 u8 syndrome[0x20]; 3316 3317 u8 reserved_at_40[0x40]; 3318 }; 3319 3320 struct mlx5_ifc_set_l2_table_entry_in_bits { 3321 u8 opcode[0x10]; 3322 u8 reserved_at_10[0x10]; 3323 3324 u8 reserved_at_20[0x10]; 3325 u8 op_mod[0x10]; 3326 3327 u8 reserved_at_40[0x60]; 3328 3329 u8 reserved_at_a0[0x8]; 3330 u8 table_index[0x18]; 3331 3332 u8 reserved_at_c0[0x20]; 3333 3334 u8 reserved_at_e0[0x13]; 3335 u8 vlan_valid[0x1]; 3336 u8 vlan[0xc]; 3337 3338 struct mlx5_ifc_mac_address_layout_bits mac_address; 3339 3340 u8 reserved_at_140[0xc0]; 3341 }; 3342 3343 struct mlx5_ifc_set_issi_out_bits { 3344 u8 status[0x8]; 3345 u8 reserved_at_8[0x18]; 3346 3347 u8 syndrome[0x20]; 3348 3349 u8 reserved_at_40[0x40]; 3350 }; 3351 3352 struct mlx5_ifc_set_issi_in_bits { 3353 u8 opcode[0x10]; 3354 u8 reserved_at_10[0x10]; 3355 3356 u8 reserved_at_20[0x10]; 3357 u8 op_mod[0x10]; 3358 3359 u8 reserved_at_40[0x10]; 3360 u8 current_issi[0x10]; 3361 3362 u8 reserved_at_60[0x20]; 3363 }; 3364 3365 struct mlx5_ifc_set_hca_cap_out_bits { 3366 u8 status[0x8]; 3367 u8 reserved_at_8[0x18]; 3368 3369 u8 syndrome[0x20]; 3370 3371 u8 reserved_at_40[0x40]; 3372 }; 3373 3374 struct mlx5_ifc_set_hca_cap_in_bits { 3375 u8 opcode[0x10]; 3376 u8 reserved_at_10[0x10]; 3377 3378 u8 reserved_at_20[0x10]; 3379 u8 op_mod[0x10]; 3380 3381 u8 reserved_at_40[0x40]; 3382 3383 union mlx5_ifc_hca_cap_union_bits capability; 3384 }; 3385 3386 enum { 3387 MLX5_SET_FTE_MODIFY_ENABLE_MASK_ACTION = 0x0, 3388 MLX5_SET_FTE_MODIFY_ENABLE_MASK_FLOW_TAG = 0x1, 3389 MLX5_SET_FTE_MODIFY_ENABLE_MASK_DESTINATION_LIST = 0x2, 3390 MLX5_SET_FTE_MODIFY_ENABLE_MASK_FLOW_COUNTERS = 0x3 3391 }; 3392 3393 struct mlx5_ifc_set_fte_out_bits { 3394 u8 status[0x8]; 3395 u8 reserved_at_8[0x18]; 3396 3397 u8 syndrome[0x20]; 3398 3399 u8 reserved_at_40[0x40]; 3400 }; 3401 3402 struct mlx5_ifc_set_fte_in_bits { 3403 u8 opcode[0x10]; 3404 u8 reserved_at_10[0x10]; 3405 3406 u8 reserved_at_20[0x10]; 3407 u8 op_mod[0x10]; 3408 3409 u8 other_vport[0x1]; 3410 u8 reserved_at_41[0xf]; 3411 u8 vport_number[0x10]; 3412 3413 u8 reserved_at_60[0x20]; 3414 3415 u8 table_type[0x8]; 3416 u8 reserved_at_88[0x18]; 3417 3418 u8 reserved_at_a0[0x8]; 3419 u8 table_id[0x18]; 3420 3421 u8 reserved_at_c0[0x18]; 3422 u8 modify_enable_mask[0x8]; 3423 3424 u8 reserved_at_e0[0x20]; 3425 3426 u8 flow_index[0x20]; 3427 3428 u8 reserved_at_120[0xe0]; 3429 3430 struct mlx5_ifc_flow_context_bits flow_context; 3431 }; 3432 3433 struct mlx5_ifc_rts2rts_qp_out_bits { 3434 u8 status[0x8]; 3435 u8 reserved_at_8[0x18]; 3436 3437 u8 syndrome[0x20]; 3438 3439 u8 reserved_at_40[0x40]; 3440 }; 3441 3442 struct mlx5_ifc_rts2rts_qp_in_bits { 3443 u8 opcode[0x10]; 3444 u8 reserved_at_10[0x10]; 3445 3446 u8 reserved_at_20[0x10]; 3447 u8 op_mod[0x10]; 3448 3449 u8 reserved_at_40[0x8]; 3450 u8 qpn[0x18]; 3451 3452 u8 reserved_at_60[0x20]; 3453 3454 u8 opt_param_mask[0x20]; 3455 3456 u8 reserved_at_a0[0x20]; 3457 3458 struct mlx5_ifc_qpc_bits qpc; 3459 3460 u8 reserved_at_800[0x80]; 3461 }; 3462 3463 struct mlx5_ifc_rtr2rts_qp_out_bits { 3464 u8 status[0x8]; 3465 u8 reserved_at_8[0x18]; 3466 3467 u8 syndrome[0x20]; 3468 3469 u8 reserved_at_40[0x40]; 3470 }; 3471 3472 struct mlx5_ifc_rtr2rts_qp_in_bits { 3473 u8 opcode[0x10]; 3474 u8 reserved_at_10[0x10]; 3475 3476 u8 reserved_at_20[0x10]; 3477 u8 op_mod[0x10]; 3478 3479 u8 reserved_at_40[0x8]; 3480 u8 qpn[0x18]; 3481 3482 u8 reserved_at_60[0x20]; 3483 3484 u8 opt_param_mask[0x20]; 3485 3486 u8 reserved_at_a0[0x20]; 3487 3488 struct mlx5_ifc_qpc_bits qpc; 3489 3490 u8 reserved_at_800[0x80]; 3491 }; 3492 3493 struct mlx5_ifc_rst2init_qp_out_bits { 3494 u8 status[0x8]; 3495 u8 reserved_at_8[0x18]; 3496 3497 u8 syndrome[0x20]; 3498 3499 u8 reserved_at_40[0x40]; 3500 }; 3501 3502 struct mlx5_ifc_rst2init_qp_in_bits { 3503 u8 opcode[0x10]; 3504 u8 reserved_at_10[0x10]; 3505 3506 u8 reserved_at_20[0x10]; 3507 u8 op_mod[0x10]; 3508 3509 u8 reserved_at_40[0x8]; 3510 u8 qpn[0x18]; 3511 3512 u8 reserved_at_60[0x20]; 3513 3514 u8 opt_param_mask[0x20]; 3515 3516 u8 reserved_at_a0[0x20]; 3517 3518 struct mlx5_ifc_qpc_bits qpc; 3519 3520 u8 reserved_at_800[0x80]; 3521 }; 3522 3523 struct mlx5_ifc_query_xrq_out_bits { 3524 u8 status[0x8]; 3525 u8 reserved_at_8[0x18]; 3526 3527 u8 syndrome[0x20]; 3528 3529 u8 reserved_at_40[0x40]; 3530 3531 struct mlx5_ifc_xrqc_bits xrq_context; 3532 }; 3533 3534 struct mlx5_ifc_query_xrq_in_bits { 3535 u8 opcode[0x10]; 3536 u8 reserved_at_10[0x10]; 3537 3538 u8 reserved_at_20[0x10]; 3539 u8 op_mod[0x10]; 3540 3541 u8 reserved_at_40[0x8]; 3542 u8 xrqn[0x18]; 3543 3544 u8 reserved_at_60[0x20]; 3545 }; 3546 3547 struct mlx5_ifc_query_xrc_srq_out_bits { 3548 u8 status[0x8]; 3549 u8 reserved_at_8[0x18]; 3550 3551 u8 syndrome[0x20]; 3552 3553 u8 reserved_at_40[0x40]; 3554 3555 struct mlx5_ifc_xrc_srqc_bits xrc_srq_context_entry; 3556 3557 u8 reserved_at_280[0x600]; 3558 3559 u8 pas[0][0x40]; 3560 }; 3561 3562 struct mlx5_ifc_query_xrc_srq_in_bits { 3563 u8 opcode[0x10]; 3564 u8 reserved_at_10[0x10]; 3565 3566 u8 reserved_at_20[0x10]; 3567 u8 op_mod[0x10]; 3568 3569 u8 reserved_at_40[0x8]; 3570 u8 xrc_srqn[0x18]; 3571 3572 u8 reserved_at_60[0x20]; 3573 }; 3574 3575 enum { 3576 MLX5_QUERY_VPORT_STATE_OUT_STATE_DOWN = 0x0, 3577 MLX5_QUERY_VPORT_STATE_OUT_STATE_UP = 0x1, 3578 }; 3579 3580 struct mlx5_ifc_query_vport_state_out_bits { 3581 u8 status[0x8]; 3582 u8 reserved_at_8[0x18]; 3583 3584 u8 syndrome[0x20]; 3585 3586 u8 reserved_at_40[0x20]; 3587 3588 u8 reserved_at_60[0x18]; 3589 u8 admin_state[0x4]; 3590 u8 state[0x4]; 3591 }; 3592 3593 enum { 3594 MLX5_QUERY_VPORT_STATE_IN_OP_MOD_VNIC_VPORT = 0x0, 3595 MLX5_QUERY_VPORT_STATE_IN_OP_MOD_ESW_VPORT = 0x1, 3596 }; 3597 3598 struct mlx5_ifc_query_vport_state_in_bits { 3599 u8 opcode[0x10]; 3600 u8 reserved_at_10[0x10]; 3601 3602 u8 reserved_at_20[0x10]; 3603 u8 op_mod[0x10]; 3604 3605 u8 other_vport[0x1]; 3606 u8 reserved_at_41[0xf]; 3607 u8 vport_number[0x10]; 3608 3609 u8 reserved_at_60[0x20]; 3610 }; 3611 3612 struct mlx5_ifc_query_vport_counter_out_bits { 3613 u8 status[0x8]; 3614 u8 reserved_at_8[0x18]; 3615 3616 u8 syndrome[0x20]; 3617 3618 u8 reserved_at_40[0x40]; 3619 3620 struct mlx5_ifc_traffic_counter_bits received_errors; 3621 3622 struct mlx5_ifc_traffic_counter_bits transmit_errors; 3623 3624 struct mlx5_ifc_traffic_counter_bits received_ib_unicast; 3625 3626 struct mlx5_ifc_traffic_counter_bits transmitted_ib_unicast; 3627 3628 struct mlx5_ifc_traffic_counter_bits received_ib_multicast; 3629 3630 struct mlx5_ifc_traffic_counter_bits transmitted_ib_multicast; 3631 3632 struct mlx5_ifc_traffic_counter_bits received_eth_broadcast; 3633 3634 struct mlx5_ifc_traffic_counter_bits transmitted_eth_broadcast; 3635 3636 struct mlx5_ifc_traffic_counter_bits received_eth_unicast; 3637 3638 struct mlx5_ifc_traffic_counter_bits transmitted_eth_unicast; 3639 3640 struct mlx5_ifc_traffic_counter_bits received_eth_multicast; 3641 3642 struct mlx5_ifc_traffic_counter_bits transmitted_eth_multicast; 3643 3644 u8 reserved_at_680[0xa00]; 3645 }; 3646 3647 enum { 3648 MLX5_QUERY_VPORT_COUNTER_IN_OP_MOD_VPORT_COUNTERS = 0x0, 3649 }; 3650 3651 struct mlx5_ifc_query_vport_counter_in_bits { 3652 u8 opcode[0x10]; 3653 u8 reserved_at_10[0x10]; 3654 3655 u8 reserved_at_20[0x10]; 3656 u8 op_mod[0x10]; 3657 3658 u8 other_vport[0x1]; 3659 u8 reserved_at_41[0xb]; 3660 u8 port_num[0x4]; 3661 u8 vport_number[0x10]; 3662 3663 u8 reserved_at_60[0x60]; 3664 3665 u8 clear[0x1]; 3666 u8 reserved_at_c1[0x1f]; 3667 3668 u8 reserved_at_e0[0x20]; 3669 }; 3670 3671 struct mlx5_ifc_query_tis_out_bits { 3672 u8 status[0x8]; 3673 u8 reserved_at_8[0x18]; 3674 3675 u8 syndrome[0x20]; 3676 3677 u8 reserved_at_40[0x40]; 3678 3679 struct mlx5_ifc_tisc_bits tis_context; 3680 }; 3681 3682 struct mlx5_ifc_query_tis_in_bits { 3683 u8 opcode[0x10]; 3684 u8 reserved_at_10[0x10]; 3685 3686 u8 reserved_at_20[0x10]; 3687 u8 op_mod[0x10]; 3688 3689 u8 reserved_at_40[0x8]; 3690 u8 tisn[0x18]; 3691 3692 u8 reserved_at_60[0x20]; 3693 }; 3694 3695 struct mlx5_ifc_query_tir_out_bits { 3696 u8 status[0x8]; 3697 u8 reserved_at_8[0x18]; 3698 3699 u8 syndrome[0x20]; 3700 3701 u8 reserved_at_40[0xc0]; 3702 3703 struct mlx5_ifc_tirc_bits tir_context; 3704 }; 3705 3706 struct mlx5_ifc_query_tir_in_bits { 3707 u8 opcode[0x10]; 3708 u8 reserved_at_10[0x10]; 3709 3710 u8 reserved_at_20[0x10]; 3711 u8 op_mod[0x10]; 3712 3713 u8 reserved_at_40[0x8]; 3714 u8 tirn[0x18]; 3715 3716 u8 reserved_at_60[0x20]; 3717 }; 3718 3719 struct mlx5_ifc_query_srq_out_bits { 3720 u8 status[0x8]; 3721 u8 reserved_at_8[0x18]; 3722 3723 u8 syndrome[0x20]; 3724 3725 u8 reserved_at_40[0x40]; 3726 3727 struct mlx5_ifc_srqc_bits srq_context_entry; 3728 3729 u8 reserved_at_280[0x600]; 3730 3731 u8 pas[0][0x40]; 3732 }; 3733 3734 struct mlx5_ifc_query_srq_in_bits { 3735 u8 opcode[0x10]; 3736 u8 reserved_at_10[0x10]; 3737 3738 u8 reserved_at_20[0x10]; 3739 u8 op_mod[0x10]; 3740 3741 u8 reserved_at_40[0x8]; 3742 u8 srqn[0x18]; 3743 3744 u8 reserved_at_60[0x20]; 3745 }; 3746 3747 struct mlx5_ifc_query_sq_out_bits { 3748 u8 status[0x8]; 3749 u8 reserved_at_8[0x18]; 3750 3751 u8 syndrome[0x20]; 3752 3753 u8 reserved_at_40[0xc0]; 3754 3755 struct mlx5_ifc_sqc_bits sq_context; 3756 }; 3757 3758 struct mlx5_ifc_query_sq_in_bits { 3759 u8 opcode[0x10]; 3760 u8 reserved_at_10[0x10]; 3761 3762 u8 reserved_at_20[0x10]; 3763 u8 op_mod[0x10]; 3764 3765 u8 reserved_at_40[0x8]; 3766 u8 sqn[0x18]; 3767 3768 u8 reserved_at_60[0x20]; 3769 }; 3770 3771 struct mlx5_ifc_query_special_contexts_out_bits { 3772 u8 status[0x8]; 3773 u8 reserved_at_8[0x18]; 3774 3775 u8 syndrome[0x20]; 3776 3777 u8 dump_fill_mkey[0x20]; 3778 3779 u8 resd_lkey[0x20]; 3780 3781 u8 null_mkey[0x20]; 3782 3783 u8 reserved_at_a0[0x60]; 3784 }; 3785 3786 struct mlx5_ifc_query_special_contexts_in_bits { 3787 u8 opcode[0x10]; 3788 u8 reserved_at_10[0x10]; 3789 3790 u8 reserved_at_20[0x10]; 3791 u8 op_mod[0x10]; 3792 3793 u8 reserved_at_40[0x40]; 3794 }; 3795 3796 struct mlx5_ifc_query_scheduling_element_out_bits { 3797 u8 opcode[0x10]; 3798 u8 reserved_at_10[0x10]; 3799 3800 u8 reserved_at_20[0x10]; 3801 u8 op_mod[0x10]; 3802 3803 u8 reserved_at_40[0xc0]; 3804 3805 struct mlx5_ifc_scheduling_context_bits scheduling_context; 3806 3807 u8 reserved_at_300[0x100]; 3808 }; 3809 3810 enum { 3811 SCHEDULING_HIERARCHY_E_SWITCH = 0x2, 3812 }; 3813 3814 struct mlx5_ifc_query_scheduling_element_in_bits { 3815 u8 opcode[0x10]; 3816 u8 reserved_at_10[0x10]; 3817 3818 u8 reserved_at_20[0x10]; 3819 u8 op_mod[0x10]; 3820 3821 u8 scheduling_hierarchy[0x8]; 3822 u8 reserved_at_48[0x18]; 3823 3824 u8 scheduling_element_id[0x20]; 3825 3826 u8 reserved_at_80[0x180]; 3827 }; 3828 3829 struct mlx5_ifc_query_rqt_out_bits { 3830 u8 status[0x8]; 3831 u8 reserved_at_8[0x18]; 3832 3833 u8 syndrome[0x20]; 3834 3835 u8 reserved_at_40[0xc0]; 3836 3837 struct mlx5_ifc_rqtc_bits rqt_context; 3838 }; 3839 3840 struct mlx5_ifc_query_rqt_in_bits { 3841 u8 opcode[0x10]; 3842 u8 reserved_at_10[0x10]; 3843 3844 u8 reserved_at_20[0x10]; 3845 u8 op_mod[0x10]; 3846 3847 u8 reserved_at_40[0x8]; 3848 u8 rqtn[0x18]; 3849 3850 u8 reserved_at_60[0x20]; 3851 }; 3852 3853 struct mlx5_ifc_query_rq_out_bits { 3854 u8 status[0x8]; 3855 u8 reserved_at_8[0x18]; 3856 3857 u8 syndrome[0x20]; 3858 3859 u8 reserved_at_40[0xc0]; 3860 3861 struct mlx5_ifc_rqc_bits rq_context; 3862 }; 3863 3864 struct mlx5_ifc_query_rq_in_bits { 3865 u8 opcode[0x10]; 3866 u8 reserved_at_10[0x10]; 3867 3868 u8 reserved_at_20[0x10]; 3869 u8 op_mod[0x10]; 3870 3871 u8 reserved_at_40[0x8]; 3872 u8 rqn[0x18]; 3873 3874 u8 reserved_at_60[0x20]; 3875 }; 3876 3877 struct mlx5_ifc_query_roce_address_out_bits { 3878 u8 status[0x8]; 3879 u8 reserved_at_8[0x18]; 3880 3881 u8 syndrome[0x20]; 3882 3883 u8 reserved_at_40[0x40]; 3884 3885 struct mlx5_ifc_roce_addr_layout_bits roce_address; 3886 }; 3887 3888 struct mlx5_ifc_query_roce_address_in_bits { 3889 u8 opcode[0x10]; 3890 u8 reserved_at_10[0x10]; 3891 3892 u8 reserved_at_20[0x10]; 3893 u8 op_mod[0x10]; 3894 3895 u8 roce_address_index[0x10]; 3896 u8 reserved_at_50[0xc]; 3897 u8 vhca_port_num[0x4]; 3898 3899 u8 reserved_at_60[0x20]; 3900 }; 3901 3902 struct mlx5_ifc_query_rmp_out_bits { 3903 u8 status[0x8]; 3904 u8 reserved_at_8[0x18]; 3905 3906 u8 syndrome[0x20]; 3907 3908 u8 reserved_at_40[0xc0]; 3909 3910 struct mlx5_ifc_rmpc_bits rmp_context; 3911 }; 3912 3913 struct mlx5_ifc_query_rmp_in_bits { 3914 u8 opcode[0x10]; 3915 u8 reserved_at_10[0x10]; 3916 3917 u8 reserved_at_20[0x10]; 3918 u8 op_mod[0x10]; 3919 3920 u8 reserved_at_40[0x8]; 3921 u8 rmpn[0x18]; 3922 3923 u8 reserved_at_60[0x20]; 3924 }; 3925 3926 struct mlx5_ifc_query_qp_out_bits { 3927 u8 status[0x8]; 3928 u8 reserved_at_8[0x18]; 3929 3930 u8 syndrome[0x20]; 3931 3932 u8 reserved_at_40[0x40]; 3933 3934 u8 opt_param_mask[0x20]; 3935 3936 u8 reserved_at_a0[0x20]; 3937 3938 struct mlx5_ifc_qpc_bits qpc; 3939 3940 u8 reserved_at_800[0x80]; 3941 3942 u8 pas[0][0x40]; 3943 }; 3944 3945 struct mlx5_ifc_query_qp_in_bits { 3946 u8 opcode[0x10]; 3947 u8 reserved_at_10[0x10]; 3948 3949 u8 reserved_at_20[0x10]; 3950 u8 op_mod[0x10]; 3951 3952 u8 reserved_at_40[0x8]; 3953 u8 qpn[0x18]; 3954 3955 u8 reserved_at_60[0x20]; 3956 }; 3957 3958 struct mlx5_ifc_query_q_counter_out_bits { 3959 u8 status[0x8]; 3960 u8 reserved_at_8[0x18]; 3961 3962 u8 syndrome[0x20]; 3963 3964 u8 reserved_at_40[0x40]; 3965 3966 u8 rx_write_requests[0x20]; 3967 3968 u8 reserved_at_a0[0x20]; 3969 3970 u8 rx_read_requests[0x20]; 3971 3972 u8 reserved_at_e0[0x20]; 3973 3974 u8 rx_atomic_requests[0x20]; 3975 3976 u8 reserved_at_120[0x20]; 3977 3978 u8 rx_dct_connect[0x20]; 3979 3980 u8 reserved_at_160[0x20]; 3981 3982 u8 out_of_buffer[0x20]; 3983 3984 u8 reserved_at_1a0[0x20]; 3985 3986 u8 out_of_sequence[0x20]; 3987 3988 u8 reserved_at_1e0[0x20]; 3989 3990 u8 duplicate_request[0x20]; 3991 3992 u8 reserved_at_220[0x20]; 3993 3994 u8 rnr_nak_retry_err[0x20]; 3995 3996 u8 reserved_at_260[0x20]; 3997 3998 u8 packet_seq_err[0x20]; 3999 4000 u8 reserved_at_2a0[0x20]; 4001 4002 u8 implied_nak_seq_err[0x20]; 4003 4004 u8 reserved_at_2e0[0x20]; 4005 4006 u8 local_ack_timeout_err[0x20]; 4007 4008 u8 reserved_at_320[0xa0]; 4009 4010 u8 resp_local_length_error[0x20]; 4011 4012 u8 req_local_length_error[0x20]; 4013 4014 u8 resp_local_qp_error[0x20]; 4015 4016 u8 local_operation_error[0x20]; 4017 4018 u8 resp_local_protection[0x20]; 4019 4020 u8 req_local_protection[0x20]; 4021 4022 u8 resp_cqe_error[0x20]; 4023 4024 u8 req_cqe_error[0x20]; 4025 4026 u8 req_mw_binding[0x20]; 4027 4028 u8 req_bad_response[0x20]; 4029 4030 u8 req_remote_invalid_request[0x20]; 4031 4032 u8 resp_remote_invalid_request[0x20]; 4033 4034 u8 req_remote_access_errors[0x20]; 4035 4036 u8 resp_remote_access_errors[0x20]; 4037 4038 u8 req_remote_operation_errors[0x20]; 4039 4040 u8 req_transport_retries_exceeded[0x20]; 4041 4042 u8 cq_overflow[0x20]; 4043 4044 u8 resp_cqe_flush_error[0x20]; 4045 4046 u8 req_cqe_flush_error[0x20]; 4047 4048 u8 reserved_at_620[0x1e0]; 4049 }; 4050 4051 struct mlx5_ifc_query_q_counter_in_bits { 4052 u8 opcode[0x10]; 4053 u8 reserved_at_10[0x10]; 4054 4055 u8 reserved_at_20[0x10]; 4056 u8 op_mod[0x10]; 4057 4058 u8 reserved_at_40[0x80]; 4059 4060 u8 clear[0x1]; 4061 u8 reserved_at_c1[0x1f]; 4062 4063 u8 reserved_at_e0[0x18]; 4064 u8 counter_set_id[0x8]; 4065 }; 4066 4067 struct mlx5_ifc_query_pages_out_bits { 4068 u8 status[0x8]; 4069 u8 reserved_at_8[0x18]; 4070 4071 u8 syndrome[0x20]; 4072 4073 u8 reserved_at_40[0x10]; 4074 u8 function_id[0x10]; 4075 4076 u8 num_pages[0x20]; 4077 }; 4078 4079 enum { 4080 MLX5_QUERY_PAGES_IN_OP_MOD_BOOT_PAGES = 0x1, 4081 MLX5_QUERY_PAGES_IN_OP_MOD_INIT_PAGES = 0x2, 4082 MLX5_QUERY_PAGES_IN_OP_MOD_REGULAR_PAGES = 0x3, 4083 }; 4084 4085 struct mlx5_ifc_query_pages_in_bits { 4086 u8 opcode[0x10]; 4087 u8 reserved_at_10[0x10]; 4088 4089 u8 reserved_at_20[0x10]; 4090 u8 op_mod[0x10]; 4091 4092 u8 reserved_at_40[0x10]; 4093 u8 function_id[0x10]; 4094 4095 u8 reserved_at_60[0x20]; 4096 }; 4097 4098 struct mlx5_ifc_query_nic_vport_context_out_bits { 4099 u8 status[0x8]; 4100 u8 reserved_at_8[0x18]; 4101 4102 u8 syndrome[0x20]; 4103 4104 u8 reserved_at_40[0x40]; 4105 4106 struct mlx5_ifc_nic_vport_context_bits nic_vport_context; 4107 }; 4108 4109 struct mlx5_ifc_query_nic_vport_context_in_bits { 4110 u8 opcode[0x10]; 4111 u8 reserved_at_10[0x10]; 4112 4113 u8 reserved_at_20[0x10]; 4114 u8 op_mod[0x10]; 4115 4116 u8 other_vport[0x1]; 4117 u8 reserved_at_41[0xf]; 4118 u8 vport_number[0x10]; 4119 4120 u8 reserved_at_60[0x5]; 4121 u8 allowed_list_type[0x3]; 4122 u8 reserved_at_68[0x18]; 4123 }; 4124 4125 struct mlx5_ifc_query_mkey_out_bits { 4126 u8 status[0x8]; 4127 u8 reserved_at_8[0x18]; 4128 4129 u8 syndrome[0x20]; 4130 4131 u8 reserved_at_40[0x40]; 4132 4133 struct mlx5_ifc_mkc_bits memory_key_mkey_entry; 4134 4135 u8 reserved_at_280[0x600]; 4136 4137 u8 bsf0_klm0_pas_mtt0_1[16][0x8]; 4138 4139 u8 bsf1_klm1_pas_mtt2_3[16][0x8]; 4140 }; 4141 4142 struct mlx5_ifc_query_mkey_in_bits { 4143 u8 opcode[0x10]; 4144 u8 reserved_at_10[0x10]; 4145 4146 u8 reserved_at_20[0x10]; 4147 u8 op_mod[0x10]; 4148 4149 u8 reserved_at_40[0x8]; 4150 u8 mkey_index[0x18]; 4151 4152 u8 pg_access[0x1]; 4153 u8 reserved_at_61[0x1f]; 4154 }; 4155 4156 struct mlx5_ifc_query_mad_demux_out_bits { 4157 u8 status[0x8]; 4158 u8 reserved_at_8[0x18]; 4159 4160 u8 syndrome[0x20]; 4161 4162 u8 reserved_at_40[0x40]; 4163 4164 u8 mad_dumux_parameters_block[0x20]; 4165 }; 4166 4167 struct mlx5_ifc_query_mad_demux_in_bits { 4168 u8 opcode[0x10]; 4169 u8 reserved_at_10[0x10]; 4170 4171 u8 reserved_at_20[0x10]; 4172 u8 op_mod[0x10]; 4173 4174 u8 reserved_at_40[0x40]; 4175 }; 4176 4177 struct mlx5_ifc_query_l2_table_entry_out_bits { 4178 u8 status[0x8]; 4179 u8 reserved_at_8[0x18]; 4180 4181 u8 syndrome[0x20]; 4182 4183 u8 reserved_at_40[0xa0]; 4184 4185 u8 reserved_at_e0[0x13]; 4186 u8 vlan_valid[0x1]; 4187 u8 vlan[0xc]; 4188 4189 struct mlx5_ifc_mac_address_layout_bits mac_address; 4190 4191 u8 reserved_at_140[0xc0]; 4192 }; 4193 4194 struct mlx5_ifc_query_l2_table_entry_in_bits { 4195 u8 opcode[0x10]; 4196 u8 reserved_at_10[0x10]; 4197 4198 u8 reserved_at_20[0x10]; 4199 u8 op_mod[0x10]; 4200 4201 u8 reserved_at_40[0x60]; 4202 4203 u8 reserved_at_a0[0x8]; 4204 u8 table_index[0x18]; 4205 4206 u8 reserved_at_c0[0x140]; 4207 }; 4208 4209 struct mlx5_ifc_query_issi_out_bits { 4210 u8 status[0x8]; 4211 u8 reserved_at_8[0x18]; 4212 4213 u8 syndrome[0x20]; 4214 4215 u8 reserved_at_40[0x10]; 4216 u8 current_issi[0x10]; 4217 4218 u8 reserved_at_60[0xa0]; 4219 4220 u8 reserved_at_100[76][0x8]; 4221 u8 supported_issi_dw0[0x20]; 4222 }; 4223 4224 struct mlx5_ifc_query_issi_in_bits { 4225 u8 opcode[0x10]; 4226 u8 reserved_at_10[0x10]; 4227 4228 u8 reserved_at_20[0x10]; 4229 u8 op_mod[0x10]; 4230 4231 u8 reserved_at_40[0x40]; 4232 }; 4233 4234 struct mlx5_ifc_set_driver_version_out_bits { 4235 u8 status[0x8]; 4236 u8 reserved_0[0x18]; 4237 4238 u8 syndrome[0x20]; 4239 u8 reserved_1[0x40]; 4240 }; 4241 4242 struct mlx5_ifc_set_driver_version_in_bits { 4243 u8 opcode[0x10]; 4244 u8 reserved_0[0x10]; 4245 4246 u8 reserved_1[0x10]; 4247 u8 op_mod[0x10]; 4248 4249 u8 reserved_2[0x40]; 4250 u8 driver_version[64][0x8]; 4251 }; 4252 4253 struct mlx5_ifc_query_hca_vport_pkey_out_bits { 4254 u8 status[0x8]; 4255 u8 reserved_at_8[0x18]; 4256 4257 u8 syndrome[0x20]; 4258 4259 u8 reserved_at_40[0x40]; 4260 4261 struct mlx5_ifc_pkey_bits pkey[0]; 4262 }; 4263 4264 struct mlx5_ifc_query_hca_vport_pkey_in_bits { 4265 u8 opcode[0x10]; 4266 u8 reserved_at_10[0x10]; 4267 4268 u8 reserved_at_20[0x10]; 4269 u8 op_mod[0x10]; 4270 4271 u8 other_vport[0x1]; 4272 u8 reserved_at_41[0xb]; 4273 u8 port_num[0x4]; 4274 u8 vport_number[0x10]; 4275 4276 u8 reserved_at_60[0x10]; 4277 u8 pkey_index[0x10]; 4278 }; 4279 4280 enum { 4281 MLX5_HCA_VPORT_SEL_PORT_GUID = 1 << 0, 4282 MLX5_HCA_VPORT_SEL_NODE_GUID = 1 << 1, 4283 MLX5_HCA_VPORT_SEL_STATE_POLICY = 1 << 2, 4284 }; 4285 4286 struct mlx5_ifc_query_hca_vport_gid_out_bits { 4287 u8 status[0x8]; 4288 u8 reserved_at_8[0x18]; 4289 4290 u8 syndrome[0x20]; 4291 4292 u8 reserved_at_40[0x20]; 4293 4294 u8 gids_num[0x10]; 4295 u8 reserved_at_70[0x10]; 4296 4297 struct mlx5_ifc_array128_auto_bits gid[0]; 4298 }; 4299 4300 struct mlx5_ifc_query_hca_vport_gid_in_bits { 4301 u8 opcode[0x10]; 4302 u8 reserved_at_10[0x10]; 4303 4304 u8 reserved_at_20[0x10]; 4305 u8 op_mod[0x10]; 4306 4307 u8 other_vport[0x1]; 4308 u8 reserved_at_41[0xb]; 4309 u8 port_num[0x4]; 4310 u8 vport_number[0x10]; 4311 4312 u8 reserved_at_60[0x10]; 4313 u8 gid_index[0x10]; 4314 }; 4315 4316 struct mlx5_ifc_query_hca_vport_context_out_bits { 4317 u8 status[0x8]; 4318 u8 reserved_at_8[0x18]; 4319 4320 u8 syndrome[0x20]; 4321 4322 u8 reserved_at_40[0x40]; 4323 4324 struct mlx5_ifc_hca_vport_context_bits hca_vport_context; 4325 }; 4326 4327 struct mlx5_ifc_query_hca_vport_context_in_bits { 4328 u8 opcode[0x10]; 4329 u8 reserved_at_10[0x10]; 4330 4331 u8 reserved_at_20[0x10]; 4332 u8 op_mod[0x10]; 4333 4334 u8 other_vport[0x1]; 4335 u8 reserved_at_41[0xb]; 4336 u8 port_num[0x4]; 4337 u8 vport_number[0x10]; 4338 4339 u8 reserved_at_60[0x20]; 4340 }; 4341 4342 struct mlx5_ifc_query_hca_cap_out_bits { 4343 u8 status[0x8]; 4344 u8 reserved_at_8[0x18]; 4345 4346 u8 syndrome[0x20]; 4347 4348 u8 reserved_at_40[0x40]; 4349 4350 union mlx5_ifc_hca_cap_union_bits capability; 4351 }; 4352 4353 struct mlx5_ifc_query_hca_cap_in_bits { 4354 u8 opcode[0x10]; 4355 u8 reserved_at_10[0x10]; 4356 4357 u8 reserved_at_20[0x10]; 4358 u8 op_mod[0x10]; 4359 4360 u8 reserved_at_40[0x40]; 4361 }; 4362 4363 struct mlx5_ifc_query_flow_table_out_bits { 4364 u8 status[0x8]; 4365 u8 reserved_at_8[0x18]; 4366 4367 u8 syndrome[0x20]; 4368 4369 u8 reserved_at_40[0x80]; 4370 4371 u8 reserved_at_c0[0x8]; 4372 u8 level[0x8]; 4373 u8 reserved_at_d0[0x8]; 4374 u8 log_size[0x8]; 4375 4376 u8 reserved_at_e0[0x120]; 4377 }; 4378 4379 struct mlx5_ifc_query_flow_table_in_bits { 4380 u8 opcode[0x10]; 4381 u8 reserved_at_10[0x10]; 4382 4383 u8 reserved_at_20[0x10]; 4384 u8 op_mod[0x10]; 4385 4386 u8 reserved_at_40[0x40]; 4387 4388 u8 table_type[0x8]; 4389 u8 reserved_at_88[0x18]; 4390 4391 u8 reserved_at_a0[0x8]; 4392 u8 table_id[0x18]; 4393 4394 u8 reserved_at_c0[0x140]; 4395 }; 4396 4397 struct mlx5_ifc_query_fte_out_bits { 4398 u8 status[0x8]; 4399 u8 reserved_at_8[0x18]; 4400 4401 u8 syndrome[0x20]; 4402 4403 u8 reserved_at_40[0x1c0]; 4404 4405 struct mlx5_ifc_flow_context_bits flow_context; 4406 }; 4407 4408 struct mlx5_ifc_query_fte_in_bits { 4409 u8 opcode[0x10]; 4410 u8 reserved_at_10[0x10]; 4411 4412 u8 reserved_at_20[0x10]; 4413 u8 op_mod[0x10]; 4414 4415 u8 reserved_at_40[0x40]; 4416 4417 u8 table_type[0x8]; 4418 u8 reserved_at_88[0x18]; 4419 4420 u8 reserved_at_a0[0x8]; 4421 u8 table_id[0x18]; 4422 4423 u8 reserved_at_c0[0x40]; 4424 4425 u8 flow_index[0x20]; 4426 4427 u8 reserved_at_120[0xe0]; 4428 }; 4429 4430 enum { 4431 MLX5_QUERY_FLOW_GROUP_OUT_MATCH_CRITERIA_ENABLE_OUTER_HEADERS = 0x0, 4432 MLX5_QUERY_FLOW_GROUP_OUT_MATCH_CRITERIA_ENABLE_MISC_PARAMETERS = 0x1, 4433 MLX5_QUERY_FLOW_GROUP_OUT_MATCH_CRITERIA_ENABLE_INNER_HEADERS = 0x2, 4434 }; 4435 4436 struct mlx5_ifc_query_flow_group_out_bits { 4437 u8 status[0x8]; 4438 u8 reserved_at_8[0x18]; 4439 4440 u8 syndrome[0x20]; 4441 4442 u8 reserved_at_40[0xa0]; 4443 4444 u8 start_flow_index[0x20]; 4445 4446 u8 reserved_at_100[0x20]; 4447 4448 u8 end_flow_index[0x20]; 4449 4450 u8 reserved_at_140[0xa0]; 4451 4452 u8 reserved_at_1e0[0x18]; 4453 u8 match_criteria_enable[0x8]; 4454 4455 struct mlx5_ifc_fte_match_param_bits match_criteria; 4456 4457 u8 reserved_at_1200[0xe00]; 4458 }; 4459 4460 struct mlx5_ifc_query_flow_group_in_bits { 4461 u8 opcode[0x10]; 4462 u8 reserved_at_10[0x10]; 4463 4464 u8 reserved_at_20[0x10]; 4465 u8 op_mod[0x10]; 4466 4467 u8 reserved_at_40[0x40]; 4468 4469 u8 table_type[0x8]; 4470 u8 reserved_at_88[0x18]; 4471 4472 u8 reserved_at_a0[0x8]; 4473 u8 table_id[0x18]; 4474 4475 u8 group_id[0x20]; 4476 4477 u8 reserved_at_e0[0x120]; 4478 }; 4479 4480 struct mlx5_ifc_query_flow_counter_out_bits { 4481 u8 status[0x8]; 4482 u8 reserved_at_8[0x18]; 4483 4484 u8 syndrome[0x20]; 4485 4486 u8 reserved_at_40[0x40]; 4487 4488 struct mlx5_ifc_traffic_counter_bits flow_statistics[0]; 4489 }; 4490 4491 struct mlx5_ifc_query_flow_counter_in_bits { 4492 u8 opcode[0x10]; 4493 u8 reserved_at_10[0x10]; 4494 4495 u8 reserved_at_20[0x10]; 4496 u8 op_mod[0x10]; 4497 4498 u8 reserved_at_40[0x80]; 4499 4500 u8 clear[0x1]; 4501 u8 reserved_at_c1[0xf]; 4502 u8 num_of_counters[0x10]; 4503 4504 u8 flow_counter_id[0x20]; 4505 }; 4506 4507 struct mlx5_ifc_query_esw_vport_context_out_bits { 4508 u8 status[0x8]; 4509 u8 reserved_at_8[0x18]; 4510 4511 u8 syndrome[0x20]; 4512 4513 u8 reserved_at_40[0x40]; 4514 4515 struct mlx5_ifc_esw_vport_context_bits esw_vport_context; 4516 }; 4517 4518 struct mlx5_ifc_query_esw_vport_context_in_bits { 4519 u8 opcode[0x10]; 4520 u8 reserved_at_10[0x10]; 4521 4522 u8 reserved_at_20[0x10]; 4523 u8 op_mod[0x10]; 4524 4525 u8 other_vport[0x1]; 4526 u8 reserved_at_41[0xf]; 4527 u8 vport_number[0x10]; 4528 4529 u8 reserved_at_60[0x20]; 4530 }; 4531 4532 struct mlx5_ifc_modify_esw_vport_context_out_bits { 4533 u8 status[0x8]; 4534 u8 reserved_at_8[0x18]; 4535 4536 u8 syndrome[0x20]; 4537 4538 u8 reserved_at_40[0x40]; 4539 }; 4540 4541 struct mlx5_ifc_esw_vport_context_fields_select_bits { 4542 u8 reserved_at_0[0x1c]; 4543 u8 vport_cvlan_insert[0x1]; 4544 u8 vport_svlan_insert[0x1]; 4545 u8 vport_cvlan_strip[0x1]; 4546 u8 vport_svlan_strip[0x1]; 4547 }; 4548 4549 struct mlx5_ifc_modify_esw_vport_context_in_bits { 4550 u8 opcode[0x10]; 4551 u8 reserved_at_10[0x10]; 4552 4553 u8 reserved_at_20[0x10]; 4554 u8 op_mod[0x10]; 4555 4556 u8 other_vport[0x1]; 4557 u8 reserved_at_41[0xf]; 4558 u8 vport_number[0x10]; 4559 4560 struct mlx5_ifc_esw_vport_context_fields_select_bits field_select; 4561 4562 struct mlx5_ifc_esw_vport_context_bits esw_vport_context; 4563 }; 4564 4565 struct mlx5_ifc_query_eq_out_bits { 4566 u8 status[0x8]; 4567 u8 reserved_at_8[0x18]; 4568 4569 u8 syndrome[0x20]; 4570 4571 u8 reserved_at_40[0x40]; 4572 4573 struct mlx5_ifc_eqc_bits eq_context_entry; 4574 4575 u8 reserved_at_280[0x40]; 4576 4577 u8 event_bitmask[0x40]; 4578 4579 u8 reserved_at_300[0x580]; 4580 4581 u8 pas[0][0x40]; 4582 }; 4583 4584 struct mlx5_ifc_query_eq_in_bits { 4585 u8 opcode[0x10]; 4586 u8 reserved_at_10[0x10]; 4587 4588 u8 reserved_at_20[0x10]; 4589 u8 op_mod[0x10]; 4590 4591 u8 reserved_at_40[0x18]; 4592 u8 eq_number[0x8]; 4593 4594 u8 reserved_at_60[0x20]; 4595 }; 4596 4597 struct mlx5_ifc_encap_header_in_bits { 4598 u8 reserved_at_0[0x5]; 4599 u8 header_type[0x3]; 4600 u8 reserved_at_8[0xe]; 4601 u8 encap_header_size[0xa]; 4602 4603 u8 reserved_at_20[0x10]; 4604 u8 encap_header[2][0x8]; 4605 4606 u8 more_encap_header[0][0x8]; 4607 }; 4608 4609 struct mlx5_ifc_query_encap_header_out_bits { 4610 u8 status[0x8]; 4611 u8 reserved_at_8[0x18]; 4612 4613 u8 syndrome[0x20]; 4614 4615 u8 reserved_at_40[0xa0]; 4616 4617 struct mlx5_ifc_encap_header_in_bits encap_header[0]; 4618 }; 4619 4620 struct mlx5_ifc_query_encap_header_in_bits { 4621 u8 opcode[0x10]; 4622 u8 reserved_at_10[0x10]; 4623 4624 u8 reserved_at_20[0x10]; 4625 u8 op_mod[0x10]; 4626 4627 u8 encap_id[0x20]; 4628 4629 u8 reserved_at_60[0xa0]; 4630 }; 4631 4632 struct mlx5_ifc_alloc_encap_header_out_bits { 4633 u8 status[0x8]; 4634 u8 reserved_at_8[0x18]; 4635 4636 u8 syndrome[0x20]; 4637 4638 u8 encap_id[0x20]; 4639 4640 u8 reserved_at_60[0x20]; 4641 }; 4642 4643 struct mlx5_ifc_alloc_encap_header_in_bits { 4644 u8 opcode[0x10]; 4645 u8 reserved_at_10[0x10]; 4646 4647 u8 reserved_at_20[0x10]; 4648 u8 op_mod[0x10]; 4649 4650 u8 reserved_at_40[0xa0]; 4651 4652 struct mlx5_ifc_encap_header_in_bits encap_header; 4653 }; 4654 4655 struct mlx5_ifc_dealloc_encap_header_out_bits { 4656 u8 status[0x8]; 4657 u8 reserved_at_8[0x18]; 4658 4659 u8 syndrome[0x20]; 4660 4661 u8 reserved_at_40[0x40]; 4662 }; 4663 4664 struct mlx5_ifc_dealloc_encap_header_in_bits { 4665 u8 opcode[0x10]; 4666 u8 reserved_at_10[0x10]; 4667 4668 u8 reserved_20[0x10]; 4669 u8 op_mod[0x10]; 4670 4671 u8 encap_id[0x20]; 4672 4673 u8 reserved_60[0x20]; 4674 }; 4675 4676 struct mlx5_ifc_set_action_in_bits { 4677 u8 action_type[0x4]; 4678 u8 field[0xc]; 4679 u8 reserved_at_10[0x3]; 4680 u8 offset[0x5]; 4681 u8 reserved_at_18[0x3]; 4682 u8 length[0x5]; 4683 4684 u8 data[0x20]; 4685 }; 4686 4687 struct mlx5_ifc_add_action_in_bits { 4688 u8 action_type[0x4]; 4689 u8 field[0xc]; 4690 u8 reserved_at_10[0x10]; 4691 4692 u8 data[0x20]; 4693 }; 4694 4695 union mlx5_ifc_set_action_in_add_action_in_auto_bits { 4696 struct mlx5_ifc_set_action_in_bits set_action_in; 4697 struct mlx5_ifc_add_action_in_bits add_action_in; 4698 u8 reserved_at_0[0x40]; 4699 }; 4700 4701 enum { 4702 MLX5_ACTION_TYPE_SET = 0x1, 4703 MLX5_ACTION_TYPE_ADD = 0x2, 4704 }; 4705 4706 enum { 4707 MLX5_ACTION_IN_FIELD_OUT_SMAC_47_16 = 0x1, 4708 MLX5_ACTION_IN_FIELD_OUT_SMAC_15_0 = 0x2, 4709 MLX5_ACTION_IN_FIELD_OUT_ETHERTYPE = 0x3, 4710 MLX5_ACTION_IN_FIELD_OUT_DMAC_47_16 = 0x4, 4711 MLX5_ACTION_IN_FIELD_OUT_DMAC_15_0 = 0x5, 4712 MLX5_ACTION_IN_FIELD_OUT_IP_DSCP = 0x6, 4713 MLX5_ACTION_IN_FIELD_OUT_TCP_FLAGS = 0x7, 4714 MLX5_ACTION_IN_FIELD_OUT_TCP_SPORT = 0x8, 4715 MLX5_ACTION_IN_FIELD_OUT_TCP_DPORT = 0x9, 4716 MLX5_ACTION_IN_FIELD_OUT_IP_TTL = 0xa, 4717 MLX5_ACTION_IN_FIELD_OUT_UDP_SPORT = 0xb, 4718 MLX5_ACTION_IN_FIELD_OUT_UDP_DPORT = 0xc, 4719 MLX5_ACTION_IN_FIELD_OUT_SIPV6_127_96 = 0xd, 4720 MLX5_ACTION_IN_FIELD_OUT_SIPV6_95_64 = 0xe, 4721 MLX5_ACTION_IN_FIELD_OUT_SIPV6_63_32 = 0xf, 4722 MLX5_ACTION_IN_FIELD_OUT_SIPV6_31_0 = 0x10, 4723 MLX5_ACTION_IN_FIELD_OUT_DIPV6_127_96 = 0x11, 4724 MLX5_ACTION_IN_FIELD_OUT_DIPV6_95_64 = 0x12, 4725 MLX5_ACTION_IN_FIELD_OUT_DIPV6_63_32 = 0x13, 4726 MLX5_ACTION_IN_FIELD_OUT_DIPV6_31_0 = 0x14, 4727 MLX5_ACTION_IN_FIELD_OUT_SIPV4 = 0x15, 4728 MLX5_ACTION_IN_FIELD_OUT_DIPV4 = 0x16, 4729 MLX5_ACTION_IN_FIELD_OUT_IPV6_HOPLIMIT = 0x47, 4730 }; 4731 4732 struct mlx5_ifc_alloc_modify_header_context_out_bits { 4733 u8 status[0x8]; 4734 u8 reserved_at_8[0x18]; 4735 4736 u8 syndrome[0x20]; 4737 4738 u8 modify_header_id[0x20]; 4739 4740 u8 reserved_at_60[0x20]; 4741 }; 4742 4743 struct mlx5_ifc_alloc_modify_header_context_in_bits { 4744 u8 opcode[0x10]; 4745 u8 reserved_at_10[0x10]; 4746 4747 u8 reserved_at_20[0x10]; 4748 u8 op_mod[0x10]; 4749 4750 u8 reserved_at_40[0x20]; 4751 4752 u8 table_type[0x8]; 4753 u8 reserved_at_68[0x10]; 4754 u8 num_of_actions[0x8]; 4755 4756 union mlx5_ifc_set_action_in_add_action_in_auto_bits actions[0]; 4757 }; 4758 4759 struct mlx5_ifc_dealloc_modify_header_context_out_bits { 4760 u8 status[0x8]; 4761 u8 reserved_at_8[0x18]; 4762 4763 u8 syndrome[0x20]; 4764 4765 u8 reserved_at_40[0x40]; 4766 }; 4767 4768 struct mlx5_ifc_dealloc_modify_header_context_in_bits { 4769 u8 opcode[0x10]; 4770 u8 reserved_at_10[0x10]; 4771 4772 u8 reserved_at_20[0x10]; 4773 u8 op_mod[0x10]; 4774 4775 u8 modify_header_id[0x20]; 4776 4777 u8 reserved_at_60[0x20]; 4778 }; 4779 4780 struct mlx5_ifc_query_dct_out_bits { 4781 u8 status[0x8]; 4782 u8 reserved_at_8[0x18]; 4783 4784 u8 syndrome[0x20]; 4785 4786 u8 reserved_at_40[0x40]; 4787 4788 struct mlx5_ifc_dctc_bits dct_context_entry; 4789 4790 u8 reserved_at_280[0x180]; 4791 }; 4792 4793 struct mlx5_ifc_query_dct_in_bits { 4794 u8 opcode[0x10]; 4795 u8 reserved_at_10[0x10]; 4796 4797 u8 reserved_at_20[0x10]; 4798 u8 op_mod[0x10]; 4799 4800 u8 reserved_at_40[0x8]; 4801 u8 dctn[0x18]; 4802 4803 u8 reserved_at_60[0x20]; 4804 }; 4805 4806 struct mlx5_ifc_query_cq_out_bits { 4807 u8 status[0x8]; 4808 u8 reserved_at_8[0x18]; 4809 4810 u8 syndrome[0x20]; 4811 4812 u8 reserved_at_40[0x40]; 4813 4814 struct mlx5_ifc_cqc_bits cq_context; 4815 4816 u8 reserved_at_280[0x600]; 4817 4818 u8 pas[0][0x40]; 4819 }; 4820 4821 struct mlx5_ifc_query_cq_in_bits { 4822 u8 opcode[0x10]; 4823 u8 reserved_at_10[0x10]; 4824 4825 u8 reserved_at_20[0x10]; 4826 u8 op_mod[0x10]; 4827 4828 u8 reserved_at_40[0x8]; 4829 u8 cqn[0x18]; 4830 4831 u8 reserved_at_60[0x20]; 4832 }; 4833 4834 struct mlx5_ifc_query_cong_status_out_bits { 4835 u8 status[0x8]; 4836 u8 reserved_at_8[0x18]; 4837 4838 u8 syndrome[0x20]; 4839 4840 u8 reserved_at_40[0x20]; 4841 4842 u8 enable[0x1]; 4843 u8 tag_enable[0x1]; 4844 u8 reserved_at_62[0x1e]; 4845 }; 4846 4847 struct mlx5_ifc_query_cong_status_in_bits { 4848 u8 opcode[0x10]; 4849 u8 reserved_at_10[0x10]; 4850 4851 u8 reserved_at_20[0x10]; 4852 u8 op_mod[0x10]; 4853 4854 u8 reserved_at_40[0x18]; 4855 u8 priority[0x4]; 4856 u8 cong_protocol[0x4]; 4857 4858 u8 reserved_at_60[0x20]; 4859 }; 4860 4861 struct mlx5_ifc_query_cong_statistics_out_bits { 4862 u8 status[0x8]; 4863 u8 reserved_at_8[0x18]; 4864 4865 u8 syndrome[0x20]; 4866 4867 u8 reserved_at_40[0x40]; 4868 4869 u8 rp_cur_flows[0x20]; 4870 4871 u8 sum_flows[0x20]; 4872 4873 u8 rp_cnp_ignored_high[0x20]; 4874 4875 u8 rp_cnp_ignored_low[0x20]; 4876 4877 u8 rp_cnp_handled_high[0x20]; 4878 4879 u8 rp_cnp_handled_low[0x20]; 4880 4881 u8 reserved_at_140[0x100]; 4882 4883 u8 time_stamp_high[0x20]; 4884 4885 u8 time_stamp_low[0x20]; 4886 4887 u8 accumulators_period[0x20]; 4888 4889 u8 np_ecn_marked_roce_packets_high[0x20]; 4890 4891 u8 np_ecn_marked_roce_packets_low[0x20]; 4892 4893 u8 np_cnp_sent_high[0x20]; 4894 4895 u8 np_cnp_sent_low[0x20]; 4896 4897 u8 reserved_at_320[0x560]; 4898 }; 4899 4900 struct mlx5_ifc_query_cong_statistics_in_bits { 4901 u8 opcode[0x10]; 4902 u8 reserved_at_10[0x10]; 4903 4904 u8 reserved_at_20[0x10]; 4905 u8 op_mod[0x10]; 4906 4907 u8 clear[0x1]; 4908 u8 reserved_at_41[0x1f]; 4909 4910 u8 reserved_at_60[0x20]; 4911 }; 4912 4913 struct mlx5_ifc_query_cong_params_out_bits { 4914 u8 status[0x8]; 4915 u8 reserved_at_8[0x18]; 4916 4917 u8 syndrome[0x20]; 4918 4919 u8 reserved_at_40[0x40]; 4920 4921 union mlx5_ifc_cong_control_roce_ecn_auto_bits congestion_parameters; 4922 }; 4923 4924 struct mlx5_ifc_query_cong_params_in_bits { 4925 u8 opcode[0x10]; 4926 u8 reserved_at_10[0x10]; 4927 4928 u8 reserved_at_20[0x10]; 4929 u8 op_mod[0x10]; 4930 4931 u8 reserved_at_40[0x1c]; 4932 u8 cong_protocol[0x4]; 4933 4934 u8 reserved_at_60[0x20]; 4935 }; 4936 4937 struct mlx5_ifc_query_adapter_out_bits { 4938 u8 status[0x8]; 4939 u8 reserved_at_8[0x18]; 4940 4941 u8 syndrome[0x20]; 4942 4943 u8 reserved_at_40[0x40]; 4944 4945 struct mlx5_ifc_query_adapter_param_block_bits query_adapter_struct; 4946 }; 4947 4948 struct mlx5_ifc_query_adapter_in_bits { 4949 u8 opcode[0x10]; 4950 u8 reserved_at_10[0x10]; 4951 4952 u8 reserved_at_20[0x10]; 4953 u8 op_mod[0x10]; 4954 4955 u8 reserved_at_40[0x40]; 4956 }; 4957 4958 struct mlx5_ifc_qp_2rst_out_bits { 4959 u8 status[0x8]; 4960 u8 reserved_at_8[0x18]; 4961 4962 u8 syndrome[0x20]; 4963 4964 u8 reserved_at_40[0x40]; 4965 }; 4966 4967 struct mlx5_ifc_qp_2rst_in_bits { 4968 u8 opcode[0x10]; 4969 u8 reserved_at_10[0x10]; 4970 4971 u8 reserved_at_20[0x10]; 4972 u8 op_mod[0x10]; 4973 4974 u8 reserved_at_40[0x8]; 4975 u8 qpn[0x18]; 4976 4977 u8 reserved_at_60[0x20]; 4978 }; 4979 4980 struct mlx5_ifc_qp_2err_out_bits { 4981 u8 status[0x8]; 4982 u8 reserved_at_8[0x18]; 4983 4984 u8 syndrome[0x20]; 4985 4986 u8 reserved_at_40[0x40]; 4987 }; 4988 4989 struct mlx5_ifc_qp_2err_in_bits { 4990 u8 opcode[0x10]; 4991 u8 reserved_at_10[0x10]; 4992 4993 u8 reserved_at_20[0x10]; 4994 u8 op_mod[0x10]; 4995 4996 u8 reserved_at_40[0x8]; 4997 u8 qpn[0x18]; 4998 4999 u8 reserved_at_60[0x20]; 5000 }; 5001 5002 struct mlx5_ifc_page_fault_resume_out_bits { 5003 u8 status[0x8]; 5004 u8 reserved_at_8[0x18]; 5005 5006 u8 syndrome[0x20]; 5007 5008 u8 reserved_at_40[0x40]; 5009 }; 5010 5011 struct mlx5_ifc_page_fault_resume_in_bits { 5012 u8 opcode[0x10]; 5013 u8 reserved_at_10[0x10]; 5014 5015 u8 reserved_at_20[0x10]; 5016 u8 op_mod[0x10]; 5017 5018 u8 error[0x1]; 5019 u8 reserved_at_41[0x4]; 5020 u8 page_fault_type[0x3]; 5021 u8 wq_number[0x18]; 5022 5023 u8 reserved_at_60[0x8]; 5024 u8 token[0x18]; 5025 }; 5026 5027 struct mlx5_ifc_nop_out_bits { 5028 u8 status[0x8]; 5029 u8 reserved_at_8[0x18]; 5030 5031 u8 syndrome[0x20]; 5032 5033 u8 reserved_at_40[0x40]; 5034 }; 5035 5036 struct mlx5_ifc_nop_in_bits { 5037 u8 opcode[0x10]; 5038 u8 reserved_at_10[0x10]; 5039 5040 u8 reserved_at_20[0x10]; 5041 u8 op_mod[0x10]; 5042 5043 u8 reserved_at_40[0x40]; 5044 }; 5045 5046 struct mlx5_ifc_modify_vport_state_out_bits { 5047 u8 status[0x8]; 5048 u8 reserved_at_8[0x18]; 5049 5050 u8 syndrome[0x20]; 5051 5052 u8 reserved_at_40[0x40]; 5053 }; 5054 5055 struct mlx5_ifc_modify_vport_state_in_bits { 5056 u8 opcode[0x10]; 5057 u8 reserved_at_10[0x10]; 5058 5059 u8 reserved_at_20[0x10]; 5060 u8 op_mod[0x10]; 5061 5062 u8 other_vport[0x1]; 5063 u8 reserved_at_41[0xf]; 5064 u8 vport_number[0x10]; 5065 5066 u8 reserved_at_60[0x18]; 5067 u8 admin_state[0x4]; 5068 u8 reserved_at_7c[0x4]; 5069 }; 5070 5071 struct mlx5_ifc_modify_tis_out_bits { 5072 u8 status[0x8]; 5073 u8 reserved_at_8[0x18]; 5074 5075 u8 syndrome[0x20]; 5076 5077 u8 reserved_at_40[0x40]; 5078 }; 5079 5080 struct mlx5_ifc_modify_tis_bitmask_bits { 5081 u8 reserved_at_0[0x20]; 5082 5083 u8 reserved_at_20[0x1d]; 5084 u8 lag_tx_port_affinity[0x1]; 5085 u8 strict_lag_tx_port_affinity[0x1]; 5086 u8 prio[0x1]; 5087 }; 5088 5089 struct mlx5_ifc_modify_tis_in_bits { 5090 u8 opcode[0x10]; 5091 u8 reserved_at_10[0x10]; 5092 5093 u8 reserved_at_20[0x10]; 5094 u8 op_mod[0x10]; 5095 5096 u8 reserved_at_40[0x8]; 5097 u8 tisn[0x18]; 5098 5099 u8 reserved_at_60[0x20]; 5100 5101 struct mlx5_ifc_modify_tis_bitmask_bits bitmask; 5102 5103 u8 reserved_at_c0[0x40]; 5104 5105 struct mlx5_ifc_tisc_bits ctx; 5106 }; 5107 5108 struct mlx5_ifc_modify_tir_bitmask_bits { 5109 u8 reserved_at_0[0x20]; 5110 5111 u8 reserved_at_20[0x1b]; 5112 u8 self_lb_en[0x1]; 5113 u8 reserved_at_3c[0x1]; 5114 u8 hash[0x1]; 5115 u8 reserved_at_3e[0x1]; 5116 u8 lro[0x1]; 5117 }; 5118 5119 struct mlx5_ifc_modify_tir_out_bits { 5120 u8 status[0x8]; 5121 u8 reserved_at_8[0x18]; 5122 5123 u8 syndrome[0x20]; 5124 5125 u8 reserved_at_40[0x40]; 5126 }; 5127 5128 struct mlx5_ifc_modify_tir_in_bits { 5129 u8 opcode[0x10]; 5130 u8 reserved_at_10[0x10]; 5131 5132 u8 reserved_at_20[0x10]; 5133 u8 op_mod[0x10]; 5134 5135 u8 reserved_at_40[0x8]; 5136 u8 tirn[0x18]; 5137 5138 u8 reserved_at_60[0x20]; 5139 5140 struct mlx5_ifc_modify_tir_bitmask_bits bitmask; 5141 5142 u8 reserved_at_c0[0x40]; 5143 5144 struct mlx5_ifc_tirc_bits ctx; 5145 }; 5146 5147 struct mlx5_ifc_modify_sq_out_bits { 5148 u8 status[0x8]; 5149 u8 reserved_at_8[0x18]; 5150 5151 u8 syndrome[0x20]; 5152 5153 u8 reserved_at_40[0x40]; 5154 }; 5155 5156 struct mlx5_ifc_modify_sq_in_bits { 5157 u8 opcode[0x10]; 5158 u8 reserved_at_10[0x10]; 5159 5160 u8 reserved_at_20[0x10]; 5161 u8 op_mod[0x10]; 5162 5163 u8 sq_state[0x4]; 5164 u8 reserved_at_44[0x4]; 5165 u8 sqn[0x18]; 5166 5167 u8 reserved_at_60[0x20]; 5168 5169 u8 modify_bitmask[0x40]; 5170 5171 u8 reserved_at_c0[0x40]; 5172 5173 struct mlx5_ifc_sqc_bits ctx; 5174 }; 5175 5176 struct mlx5_ifc_modify_scheduling_element_out_bits { 5177 u8 status[0x8]; 5178 u8 reserved_at_8[0x18]; 5179 5180 u8 syndrome[0x20]; 5181 5182 u8 reserved_at_40[0x1c0]; 5183 }; 5184 5185 enum { 5186 MODIFY_SCHEDULING_ELEMENT_IN_MODIFY_BITMASK_BW_SHARE = 0x1, 5187 MODIFY_SCHEDULING_ELEMENT_IN_MODIFY_BITMASK_MAX_AVERAGE_BW = 0x2, 5188 }; 5189 5190 struct mlx5_ifc_modify_scheduling_element_in_bits { 5191 u8 opcode[0x10]; 5192 u8 reserved_at_10[0x10]; 5193 5194 u8 reserved_at_20[0x10]; 5195 u8 op_mod[0x10]; 5196 5197 u8 scheduling_hierarchy[0x8]; 5198 u8 reserved_at_48[0x18]; 5199 5200 u8 scheduling_element_id[0x20]; 5201 5202 u8 reserved_at_80[0x20]; 5203 5204 u8 modify_bitmask[0x20]; 5205 5206 u8 reserved_at_c0[0x40]; 5207 5208 struct mlx5_ifc_scheduling_context_bits scheduling_context; 5209 5210 u8 reserved_at_300[0x100]; 5211 }; 5212 5213 struct mlx5_ifc_modify_rqt_out_bits { 5214 u8 status[0x8]; 5215 u8 reserved_at_8[0x18]; 5216 5217 u8 syndrome[0x20]; 5218 5219 u8 reserved_at_40[0x40]; 5220 }; 5221 5222 struct mlx5_ifc_rqt_bitmask_bits { 5223 u8 reserved_at_0[0x20]; 5224 5225 u8 reserved_at_20[0x1f]; 5226 u8 rqn_list[0x1]; 5227 }; 5228 5229 struct mlx5_ifc_modify_rqt_in_bits { 5230 u8 opcode[0x10]; 5231 u8 reserved_at_10[0x10]; 5232 5233 u8 reserved_at_20[0x10]; 5234 u8 op_mod[0x10]; 5235 5236 u8 reserved_at_40[0x8]; 5237 u8 rqtn[0x18]; 5238 5239 u8 reserved_at_60[0x20]; 5240 5241 struct mlx5_ifc_rqt_bitmask_bits bitmask; 5242 5243 u8 reserved_at_c0[0x40]; 5244 5245 struct mlx5_ifc_rqtc_bits ctx; 5246 }; 5247 5248 struct mlx5_ifc_modify_rq_out_bits { 5249 u8 status[0x8]; 5250 u8 reserved_at_8[0x18]; 5251 5252 u8 syndrome[0x20]; 5253 5254 u8 reserved_at_40[0x40]; 5255 }; 5256 5257 enum { 5258 MLX5_MODIFY_RQ_IN_MODIFY_BITMASK_VSD = 1ULL << 1, 5259 MLX5_MODIFY_RQ_IN_MODIFY_BITMASK_SCATTER_FCS = 1ULL << 2, 5260 MLX5_MODIFY_RQ_IN_MODIFY_BITMASK_RQ_COUNTER_SET_ID = 1ULL << 3, 5261 }; 5262 5263 struct mlx5_ifc_modify_rq_in_bits { 5264 u8 opcode[0x10]; 5265 u8 reserved_at_10[0x10]; 5266 5267 u8 reserved_at_20[0x10]; 5268 u8 op_mod[0x10]; 5269 5270 u8 rq_state[0x4]; 5271 u8 reserved_at_44[0x4]; 5272 u8 rqn[0x18]; 5273 5274 u8 reserved_at_60[0x20]; 5275 5276 u8 modify_bitmask[0x40]; 5277 5278 u8 reserved_at_c0[0x40]; 5279 5280 struct mlx5_ifc_rqc_bits ctx; 5281 }; 5282 5283 struct mlx5_ifc_modify_rmp_out_bits { 5284 u8 status[0x8]; 5285 u8 reserved_at_8[0x18]; 5286 5287 u8 syndrome[0x20]; 5288 5289 u8 reserved_at_40[0x40]; 5290 }; 5291 5292 struct mlx5_ifc_rmp_bitmask_bits { 5293 u8 reserved_at_0[0x20]; 5294 5295 u8 reserved_at_20[0x1f]; 5296 u8 lwm[0x1]; 5297 }; 5298 5299 struct mlx5_ifc_modify_rmp_in_bits { 5300 u8 opcode[0x10]; 5301 u8 reserved_at_10[0x10]; 5302 5303 u8 reserved_at_20[0x10]; 5304 u8 op_mod[0x10]; 5305 5306 u8 rmp_state[0x4]; 5307 u8 reserved_at_44[0x4]; 5308 u8 rmpn[0x18]; 5309 5310 u8 reserved_at_60[0x20]; 5311 5312 struct mlx5_ifc_rmp_bitmask_bits bitmask; 5313 5314 u8 reserved_at_c0[0x40]; 5315 5316 struct mlx5_ifc_rmpc_bits ctx; 5317 }; 5318 5319 struct mlx5_ifc_modify_nic_vport_context_out_bits { 5320 u8 status[0x8]; 5321 u8 reserved_at_8[0x18]; 5322 5323 u8 syndrome[0x20]; 5324 5325 u8 reserved_at_40[0x40]; 5326 }; 5327 5328 struct mlx5_ifc_modify_nic_vport_field_select_bits { 5329 u8 reserved_at_0[0x12]; 5330 u8 affiliation[0x1]; 5331 u8 reserved_at_e[0x1]; 5332 u8 disable_uc_local_lb[0x1]; 5333 u8 disable_mc_local_lb[0x1]; 5334 u8 node_guid[0x1]; 5335 u8 port_guid[0x1]; 5336 u8 min_inline[0x1]; 5337 u8 mtu[0x1]; 5338 u8 change_event[0x1]; 5339 u8 promisc[0x1]; 5340 u8 permanent_address[0x1]; 5341 u8 addresses_list[0x1]; 5342 u8 roce_en[0x1]; 5343 u8 reserved_at_1f[0x1]; 5344 }; 5345 5346 struct mlx5_ifc_modify_nic_vport_context_in_bits { 5347 u8 opcode[0x10]; 5348 u8 reserved_at_10[0x10]; 5349 5350 u8 reserved_at_20[0x10]; 5351 u8 op_mod[0x10]; 5352 5353 u8 other_vport[0x1]; 5354 u8 reserved_at_41[0xf]; 5355 u8 vport_number[0x10]; 5356 5357 struct mlx5_ifc_modify_nic_vport_field_select_bits field_select; 5358 5359 u8 reserved_at_80[0x780]; 5360 5361 struct mlx5_ifc_nic_vport_context_bits nic_vport_context; 5362 }; 5363 5364 struct mlx5_ifc_modify_hca_vport_context_out_bits { 5365 u8 status[0x8]; 5366 u8 reserved_at_8[0x18]; 5367 5368 u8 syndrome[0x20]; 5369 5370 u8 reserved_at_40[0x40]; 5371 }; 5372 5373 struct mlx5_ifc_modify_hca_vport_context_in_bits { 5374 u8 opcode[0x10]; 5375 u8 reserved_at_10[0x10]; 5376 5377 u8 reserved_at_20[0x10]; 5378 u8 op_mod[0x10]; 5379 5380 u8 other_vport[0x1]; 5381 u8 reserved_at_41[0xb]; 5382 u8 port_num[0x4]; 5383 u8 vport_number[0x10]; 5384 5385 u8 reserved_at_60[0x20]; 5386 5387 struct mlx5_ifc_hca_vport_context_bits hca_vport_context; 5388 }; 5389 5390 struct mlx5_ifc_modify_cq_out_bits { 5391 u8 status[0x8]; 5392 u8 reserved_at_8[0x18]; 5393 5394 u8 syndrome[0x20]; 5395 5396 u8 reserved_at_40[0x40]; 5397 }; 5398 5399 enum { 5400 MLX5_MODIFY_CQ_IN_OP_MOD_MODIFY_CQ = 0x0, 5401 MLX5_MODIFY_CQ_IN_OP_MOD_RESIZE_CQ = 0x1, 5402 }; 5403 5404 struct mlx5_ifc_modify_cq_in_bits { 5405 u8 opcode[0x10]; 5406 u8 reserved_at_10[0x10]; 5407 5408 u8 reserved_at_20[0x10]; 5409 u8 op_mod[0x10]; 5410 5411 u8 reserved_at_40[0x8]; 5412 u8 cqn[0x18]; 5413 5414 union mlx5_ifc_modify_field_select_resize_field_select_auto_bits modify_field_select_resize_field_select; 5415 5416 struct mlx5_ifc_cqc_bits cq_context; 5417 5418 u8 reserved_at_280[0x600]; 5419 5420 u8 pas[0][0x40]; 5421 }; 5422 5423 struct mlx5_ifc_modify_cong_status_out_bits { 5424 u8 status[0x8]; 5425 u8 reserved_at_8[0x18]; 5426 5427 u8 syndrome[0x20]; 5428 5429 u8 reserved_at_40[0x40]; 5430 }; 5431 5432 struct mlx5_ifc_modify_cong_status_in_bits { 5433 u8 opcode[0x10]; 5434 u8 reserved_at_10[0x10]; 5435 5436 u8 reserved_at_20[0x10]; 5437 u8 op_mod[0x10]; 5438 5439 u8 reserved_at_40[0x18]; 5440 u8 priority[0x4]; 5441 u8 cong_protocol[0x4]; 5442 5443 u8 enable[0x1]; 5444 u8 tag_enable[0x1]; 5445 u8 reserved_at_62[0x1e]; 5446 }; 5447 5448 struct mlx5_ifc_modify_cong_params_out_bits { 5449 u8 status[0x8]; 5450 u8 reserved_at_8[0x18]; 5451 5452 u8 syndrome[0x20]; 5453 5454 u8 reserved_at_40[0x40]; 5455 }; 5456 5457 struct mlx5_ifc_modify_cong_params_in_bits { 5458 u8 opcode[0x10]; 5459 u8 reserved_at_10[0x10]; 5460 5461 u8 reserved_at_20[0x10]; 5462 u8 op_mod[0x10]; 5463 5464 u8 reserved_at_40[0x1c]; 5465 u8 cong_protocol[0x4]; 5466 5467 union mlx5_ifc_field_select_802_1_r_roce_auto_bits field_select; 5468 5469 u8 reserved_at_80[0x80]; 5470 5471 union mlx5_ifc_cong_control_roce_ecn_auto_bits congestion_parameters; 5472 }; 5473 5474 struct mlx5_ifc_manage_pages_out_bits { 5475 u8 status[0x8]; 5476 u8 reserved_at_8[0x18]; 5477 5478 u8 syndrome[0x20]; 5479 5480 u8 output_num_entries[0x20]; 5481 5482 u8 reserved_at_60[0x20]; 5483 5484 u8 pas[0][0x40]; 5485 }; 5486 5487 enum { 5488 MLX5_MANAGE_PAGES_IN_OP_MOD_ALLOCATION_FAIL = 0x0, 5489 MLX5_MANAGE_PAGES_IN_OP_MOD_ALLOCATION_SUCCESS = 0x1, 5490 MLX5_MANAGE_PAGES_IN_OP_MOD_HCA_RETURN_PAGES = 0x2, 5491 }; 5492 5493 struct mlx5_ifc_manage_pages_in_bits { 5494 u8 opcode[0x10]; 5495 u8 reserved_at_10[0x10]; 5496 5497 u8 reserved_at_20[0x10]; 5498 u8 op_mod[0x10]; 5499 5500 u8 reserved_at_40[0x10]; 5501 u8 function_id[0x10]; 5502 5503 u8 input_num_entries[0x20]; 5504 5505 u8 pas[0][0x40]; 5506 }; 5507 5508 struct mlx5_ifc_mad_ifc_out_bits { 5509 u8 status[0x8]; 5510 u8 reserved_at_8[0x18]; 5511 5512 u8 syndrome[0x20]; 5513 5514 u8 reserved_at_40[0x40]; 5515 5516 u8 response_mad_packet[256][0x8]; 5517 }; 5518 5519 struct mlx5_ifc_mad_ifc_in_bits { 5520 u8 opcode[0x10]; 5521 u8 reserved_at_10[0x10]; 5522 5523 u8 reserved_at_20[0x10]; 5524 u8 op_mod[0x10]; 5525 5526 u8 remote_lid[0x10]; 5527 u8 reserved_at_50[0x8]; 5528 u8 port[0x8]; 5529 5530 u8 reserved_at_60[0x20]; 5531 5532 u8 mad[256][0x8]; 5533 }; 5534 5535 struct mlx5_ifc_init_hca_out_bits { 5536 u8 status[0x8]; 5537 u8 reserved_at_8[0x18]; 5538 5539 u8 syndrome[0x20]; 5540 5541 u8 reserved_at_40[0x40]; 5542 }; 5543 5544 struct mlx5_ifc_init_hca_in_bits { 5545 u8 opcode[0x10]; 5546 u8 reserved_at_10[0x10]; 5547 5548 u8 reserved_at_20[0x10]; 5549 u8 op_mod[0x10]; 5550 5551 u8 reserved_at_40[0x40]; 5552 u8 sw_owner_id[4][0x20]; 5553 }; 5554 5555 struct mlx5_ifc_init2rtr_qp_out_bits { 5556 u8 status[0x8]; 5557 u8 reserved_at_8[0x18]; 5558 5559 u8 syndrome[0x20]; 5560 5561 u8 reserved_at_40[0x40]; 5562 }; 5563 5564 struct mlx5_ifc_init2rtr_qp_in_bits { 5565 u8 opcode[0x10]; 5566 u8 reserved_at_10[0x10]; 5567 5568 u8 reserved_at_20[0x10]; 5569 u8 op_mod[0x10]; 5570 5571 u8 reserved_at_40[0x8]; 5572 u8 qpn[0x18]; 5573 5574 u8 reserved_at_60[0x20]; 5575 5576 u8 opt_param_mask[0x20]; 5577 5578 u8 reserved_at_a0[0x20]; 5579 5580 struct mlx5_ifc_qpc_bits qpc; 5581 5582 u8 reserved_at_800[0x80]; 5583 }; 5584 5585 struct mlx5_ifc_init2init_qp_out_bits { 5586 u8 status[0x8]; 5587 u8 reserved_at_8[0x18]; 5588 5589 u8 syndrome[0x20]; 5590 5591 u8 reserved_at_40[0x40]; 5592 }; 5593 5594 struct mlx5_ifc_init2init_qp_in_bits { 5595 u8 opcode[0x10]; 5596 u8 reserved_at_10[0x10]; 5597 5598 u8 reserved_at_20[0x10]; 5599 u8 op_mod[0x10]; 5600 5601 u8 reserved_at_40[0x8]; 5602 u8 qpn[0x18]; 5603 5604 u8 reserved_at_60[0x20]; 5605 5606 u8 opt_param_mask[0x20]; 5607 5608 u8 reserved_at_a0[0x20]; 5609 5610 struct mlx5_ifc_qpc_bits qpc; 5611 5612 u8 reserved_at_800[0x80]; 5613 }; 5614 5615 struct mlx5_ifc_get_dropped_packet_log_out_bits { 5616 u8 status[0x8]; 5617 u8 reserved_at_8[0x18]; 5618 5619 u8 syndrome[0x20]; 5620 5621 u8 reserved_at_40[0x40]; 5622 5623 u8 packet_headers_log[128][0x8]; 5624 5625 u8 packet_syndrome[64][0x8]; 5626 }; 5627 5628 struct mlx5_ifc_get_dropped_packet_log_in_bits { 5629 u8 opcode[0x10]; 5630 u8 reserved_at_10[0x10]; 5631 5632 u8 reserved_at_20[0x10]; 5633 u8 op_mod[0x10]; 5634 5635 u8 reserved_at_40[0x40]; 5636 }; 5637 5638 struct mlx5_ifc_gen_eqe_in_bits { 5639 u8 opcode[0x10]; 5640 u8 reserved_at_10[0x10]; 5641 5642 u8 reserved_at_20[0x10]; 5643 u8 op_mod[0x10]; 5644 5645 u8 reserved_at_40[0x18]; 5646 u8 eq_number[0x8]; 5647 5648 u8 reserved_at_60[0x20]; 5649 5650 u8 eqe[64][0x8]; 5651 }; 5652 5653 struct mlx5_ifc_gen_eq_out_bits { 5654 u8 status[0x8]; 5655 u8 reserved_at_8[0x18]; 5656 5657 u8 syndrome[0x20]; 5658 5659 u8 reserved_at_40[0x40]; 5660 }; 5661 5662 struct mlx5_ifc_enable_hca_out_bits { 5663 u8 status[0x8]; 5664 u8 reserved_at_8[0x18]; 5665 5666 u8 syndrome[0x20]; 5667 5668 u8 reserved_at_40[0x20]; 5669 }; 5670 5671 struct mlx5_ifc_enable_hca_in_bits { 5672 u8 opcode[0x10]; 5673 u8 reserved_at_10[0x10]; 5674 5675 u8 reserved_at_20[0x10]; 5676 u8 op_mod[0x10]; 5677 5678 u8 reserved_at_40[0x10]; 5679 u8 function_id[0x10]; 5680 5681 u8 reserved_at_60[0x20]; 5682 }; 5683 5684 struct mlx5_ifc_drain_dct_out_bits { 5685 u8 status[0x8]; 5686 u8 reserved_at_8[0x18]; 5687 5688 u8 syndrome[0x20]; 5689 5690 u8 reserved_at_40[0x40]; 5691 }; 5692 5693 struct mlx5_ifc_drain_dct_in_bits { 5694 u8 opcode[0x10]; 5695 u8 reserved_at_10[0x10]; 5696 5697 u8 reserved_at_20[0x10]; 5698 u8 op_mod[0x10]; 5699 5700 u8 reserved_at_40[0x8]; 5701 u8 dctn[0x18]; 5702 5703 u8 reserved_at_60[0x20]; 5704 }; 5705 5706 struct mlx5_ifc_disable_hca_out_bits { 5707 u8 status[0x8]; 5708 u8 reserved_at_8[0x18]; 5709 5710 u8 syndrome[0x20]; 5711 5712 u8 reserved_at_40[0x20]; 5713 }; 5714 5715 struct mlx5_ifc_disable_hca_in_bits { 5716 u8 opcode[0x10]; 5717 u8 reserved_at_10[0x10]; 5718 5719 u8 reserved_at_20[0x10]; 5720 u8 op_mod[0x10]; 5721 5722 u8 reserved_at_40[0x10]; 5723 u8 function_id[0x10]; 5724 5725 u8 reserved_at_60[0x20]; 5726 }; 5727 5728 struct mlx5_ifc_detach_from_mcg_out_bits { 5729 u8 status[0x8]; 5730 u8 reserved_at_8[0x18]; 5731 5732 u8 syndrome[0x20]; 5733 5734 u8 reserved_at_40[0x40]; 5735 }; 5736 5737 struct mlx5_ifc_detach_from_mcg_in_bits { 5738 u8 opcode[0x10]; 5739 u8 reserved_at_10[0x10]; 5740 5741 u8 reserved_at_20[0x10]; 5742 u8 op_mod[0x10]; 5743 5744 u8 reserved_at_40[0x8]; 5745 u8 qpn[0x18]; 5746 5747 u8 reserved_at_60[0x20]; 5748 5749 u8 multicast_gid[16][0x8]; 5750 }; 5751 5752 struct mlx5_ifc_destroy_xrq_out_bits { 5753 u8 status[0x8]; 5754 u8 reserved_at_8[0x18]; 5755 5756 u8 syndrome[0x20]; 5757 5758 u8 reserved_at_40[0x40]; 5759 }; 5760 5761 struct mlx5_ifc_destroy_xrq_in_bits { 5762 u8 opcode[0x10]; 5763 u8 reserved_at_10[0x10]; 5764 5765 u8 reserved_at_20[0x10]; 5766 u8 op_mod[0x10]; 5767 5768 u8 reserved_at_40[0x8]; 5769 u8 xrqn[0x18]; 5770 5771 u8 reserved_at_60[0x20]; 5772 }; 5773 5774 struct mlx5_ifc_destroy_xrc_srq_out_bits { 5775 u8 status[0x8]; 5776 u8 reserved_at_8[0x18]; 5777 5778 u8 syndrome[0x20]; 5779 5780 u8 reserved_at_40[0x40]; 5781 }; 5782 5783 struct mlx5_ifc_destroy_xrc_srq_in_bits { 5784 u8 opcode[0x10]; 5785 u8 reserved_at_10[0x10]; 5786 5787 u8 reserved_at_20[0x10]; 5788 u8 op_mod[0x10]; 5789 5790 u8 reserved_at_40[0x8]; 5791 u8 xrc_srqn[0x18]; 5792 5793 u8 reserved_at_60[0x20]; 5794 }; 5795 5796 struct mlx5_ifc_destroy_tis_out_bits { 5797 u8 status[0x8]; 5798 u8 reserved_at_8[0x18]; 5799 5800 u8 syndrome[0x20]; 5801 5802 u8 reserved_at_40[0x40]; 5803 }; 5804 5805 struct mlx5_ifc_destroy_tis_in_bits { 5806 u8 opcode[0x10]; 5807 u8 reserved_at_10[0x10]; 5808 5809 u8 reserved_at_20[0x10]; 5810 u8 op_mod[0x10]; 5811 5812 u8 reserved_at_40[0x8]; 5813 u8 tisn[0x18]; 5814 5815 u8 reserved_at_60[0x20]; 5816 }; 5817 5818 struct mlx5_ifc_destroy_tir_out_bits { 5819 u8 status[0x8]; 5820 u8 reserved_at_8[0x18]; 5821 5822 u8 syndrome[0x20]; 5823 5824 u8 reserved_at_40[0x40]; 5825 }; 5826 5827 struct mlx5_ifc_destroy_tir_in_bits { 5828 u8 opcode[0x10]; 5829 u8 reserved_at_10[0x10]; 5830 5831 u8 reserved_at_20[0x10]; 5832 u8 op_mod[0x10]; 5833 5834 u8 reserved_at_40[0x8]; 5835 u8 tirn[0x18]; 5836 5837 u8 reserved_at_60[0x20]; 5838 }; 5839 5840 struct mlx5_ifc_destroy_srq_out_bits { 5841 u8 status[0x8]; 5842 u8 reserved_at_8[0x18]; 5843 5844 u8 syndrome[0x20]; 5845 5846 u8 reserved_at_40[0x40]; 5847 }; 5848 5849 struct mlx5_ifc_destroy_srq_in_bits { 5850 u8 opcode[0x10]; 5851 u8 reserved_at_10[0x10]; 5852 5853 u8 reserved_at_20[0x10]; 5854 u8 op_mod[0x10]; 5855 5856 u8 reserved_at_40[0x8]; 5857 u8 srqn[0x18]; 5858 5859 u8 reserved_at_60[0x20]; 5860 }; 5861 5862 struct mlx5_ifc_destroy_sq_out_bits { 5863 u8 status[0x8]; 5864 u8 reserved_at_8[0x18]; 5865 5866 u8 syndrome[0x20]; 5867 5868 u8 reserved_at_40[0x40]; 5869 }; 5870 5871 struct mlx5_ifc_destroy_sq_in_bits { 5872 u8 opcode[0x10]; 5873 u8 reserved_at_10[0x10]; 5874 5875 u8 reserved_at_20[0x10]; 5876 u8 op_mod[0x10]; 5877 5878 u8 reserved_at_40[0x8]; 5879 u8 sqn[0x18]; 5880 5881 u8 reserved_at_60[0x20]; 5882 }; 5883 5884 struct mlx5_ifc_destroy_scheduling_element_out_bits { 5885 u8 status[0x8]; 5886 u8 reserved_at_8[0x18]; 5887 5888 u8 syndrome[0x20]; 5889 5890 u8 reserved_at_40[0x1c0]; 5891 }; 5892 5893 struct mlx5_ifc_destroy_scheduling_element_in_bits { 5894 u8 opcode[0x10]; 5895 u8 reserved_at_10[0x10]; 5896 5897 u8 reserved_at_20[0x10]; 5898 u8 op_mod[0x10]; 5899 5900 u8 scheduling_hierarchy[0x8]; 5901 u8 reserved_at_48[0x18]; 5902 5903 u8 scheduling_element_id[0x20]; 5904 5905 u8 reserved_at_80[0x180]; 5906 }; 5907 5908 struct mlx5_ifc_destroy_rqt_out_bits { 5909 u8 status[0x8]; 5910 u8 reserved_at_8[0x18]; 5911 5912 u8 syndrome[0x20]; 5913 5914 u8 reserved_at_40[0x40]; 5915 }; 5916 5917 struct mlx5_ifc_destroy_rqt_in_bits { 5918 u8 opcode[0x10]; 5919 u8 reserved_at_10[0x10]; 5920 5921 u8 reserved_at_20[0x10]; 5922 u8 op_mod[0x10]; 5923 5924 u8 reserved_at_40[0x8]; 5925 u8 rqtn[0x18]; 5926 5927 u8 reserved_at_60[0x20]; 5928 }; 5929 5930 struct mlx5_ifc_destroy_rq_out_bits { 5931 u8 status[0x8]; 5932 u8 reserved_at_8[0x18]; 5933 5934 u8 syndrome[0x20]; 5935 5936 u8 reserved_at_40[0x40]; 5937 }; 5938 5939 struct mlx5_ifc_destroy_rq_in_bits { 5940 u8 opcode[0x10]; 5941 u8 reserved_at_10[0x10]; 5942 5943 u8 reserved_at_20[0x10]; 5944 u8 op_mod[0x10]; 5945 5946 u8 reserved_at_40[0x8]; 5947 u8 rqn[0x18]; 5948 5949 u8 reserved_at_60[0x20]; 5950 }; 5951 5952 struct mlx5_ifc_set_delay_drop_params_in_bits { 5953 u8 opcode[0x10]; 5954 u8 reserved_at_10[0x10]; 5955 5956 u8 reserved_at_20[0x10]; 5957 u8 op_mod[0x10]; 5958 5959 u8 reserved_at_40[0x20]; 5960 5961 u8 reserved_at_60[0x10]; 5962 u8 delay_drop_timeout[0x10]; 5963 }; 5964 5965 struct mlx5_ifc_set_delay_drop_params_out_bits { 5966 u8 status[0x8]; 5967 u8 reserved_at_8[0x18]; 5968 5969 u8 syndrome[0x20]; 5970 5971 u8 reserved_at_40[0x40]; 5972 }; 5973 5974 struct mlx5_ifc_destroy_rmp_out_bits { 5975 u8 status[0x8]; 5976 u8 reserved_at_8[0x18]; 5977 5978 u8 syndrome[0x20]; 5979 5980 u8 reserved_at_40[0x40]; 5981 }; 5982 5983 struct mlx5_ifc_destroy_rmp_in_bits { 5984 u8 opcode[0x10]; 5985 u8 reserved_at_10[0x10]; 5986 5987 u8 reserved_at_20[0x10]; 5988 u8 op_mod[0x10]; 5989 5990 u8 reserved_at_40[0x8]; 5991 u8 rmpn[0x18]; 5992 5993 u8 reserved_at_60[0x20]; 5994 }; 5995 5996 struct mlx5_ifc_destroy_qp_out_bits { 5997 u8 status[0x8]; 5998 u8 reserved_at_8[0x18]; 5999 6000 u8 syndrome[0x20]; 6001 6002 u8 reserved_at_40[0x40]; 6003 }; 6004 6005 struct mlx5_ifc_destroy_qp_in_bits { 6006 u8 opcode[0x10]; 6007 u8 reserved_at_10[0x10]; 6008 6009 u8 reserved_at_20[0x10]; 6010 u8 op_mod[0x10]; 6011 6012 u8 reserved_at_40[0x8]; 6013 u8 qpn[0x18]; 6014 6015 u8 reserved_at_60[0x20]; 6016 }; 6017 6018 struct mlx5_ifc_destroy_psv_out_bits { 6019 u8 status[0x8]; 6020 u8 reserved_at_8[0x18]; 6021 6022 u8 syndrome[0x20]; 6023 6024 u8 reserved_at_40[0x40]; 6025 }; 6026 6027 struct mlx5_ifc_destroy_psv_in_bits { 6028 u8 opcode[0x10]; 6029 u8 reserved_at_10[0x10]; 6030 6031 u8 reserved_at_20[0x10]; 6032 u8 op_mod[0x10]; 6033 6034 u8 reserved_at_40[0x8]; 6035 u8 psvn[0x18]; 6036 6037 u8 reserved_at_60[0x20]; 6038 }; 6039 6040 struct mlx5_ifc_destroy_mkey_out_bits { 6041 u8 status[0x8]; 6042 u8 reserved_at_8[0x18]; 6043 6044 u8 syndrome[0x20]; 6045 6046 u8 reserved_at_40[0x40]; 6047 }; 6048 6049 struct mlx5_ifc_destroy_mkey_in_bits { 6050 u8 opcode[0x10]; 6051 u8 reserved_at_10[0x10]; 6052 6053 u8 reserved_at_20[0x10]; 6054 u8 op_mod[0x10]; 6055 6056 u8 reserved_at_40[0x8]; 6057 u8 mkey_index[0x18]; 6058 6059 u8 reserved_at_60[0x20]; 6060 }; 6061 6062 struct mlx5_ifc_destroy_flow_table_out_bits { 6063 u8 status[0x8]; 6064 u8 reserved_at_8[0x18]; 6065 6066 u8 syndrome[0x20]; 6067 6068 u8 reserved_at_40[0x40]; 6069 }; 6070 6071 struct mlx5_ifc_destroy_flow_table_in_bits { 6072 u8 opcode[0x10]; 6073 u8 reserved_at_10[0x10]; 6074 6075 u8 reserved_at_20[0x10]; 6076 u8 op_mod[0x10]; 6077 6078 u8 other_vport[0x1]; 6079 u8 reserved_at_41[0xf]; 6080 u8 vport_number[0x10]; 6081 6082 u8 reserved_at_60[0x20]; 6083 6084 u8 table_type[0x8]; 6085 u8 reserved_at_88[0x18]; 6086 6087 u8 reserved_at_a0[0x8]; 6088 u8 table_id[0x18]; 6089 6090 u8 reserved_at_c0[0x140]; 6091 }; 6092 6093 struct mlx5_ifc_destroy_flow_group_out_bits { 6094 u8 status[0x8]; 6095 u8 reserved_at_8[0x18]; 6096 6097 u8 syndrome[0x20]; 6098 6099 u8 reserved_at_40[0x40]; 6100 }; 6101 6102 struct mlx5_ifc_destroy_flow_group_in_bits { 6103 u8 opcode[0x10]; 6104 u8 reserved_at_10[0x10]; 6105 6106 u8 reserved_at_20[0x10]; 6107 u8 op_mod[0x10]; 6108 6109 u8 other_vport[0x1]; 6110 u8 reserved_at_41[0xf]; 6111 u8 vport_number[0x10]; 6112 6113 u8 reserved_at_60[0x20]; 6114 6115 u8 table_type[0x8]; 6116 u8 reserved_at_88[0x18]; 6117 6118 u8 reserved_at_a0[0x8]; 6119 u8 table_id[0x18]; 6120 6121 u8 group_id[0x20]; 6122 6123 u8 reserved_at_e0[0x120]; 6124 }; 6125 6126 struct mlx5_ifc_destroy_eq_out_bits { 6127 u8 status[0x8]; 6128 u8 reserved_at_8[0x18]; 6129 6130 u8 syndrome[0x20]; 6131 6132 u8 reserved_at_40[0x40]; 6133 }; 6134 6135 struct mlx5_ifc_destroy_eq_in_bits { 6136 u8 opcode[0x10]; 6137 u8 reserved_at_10[0x10]; 6138 6139 u8 reserved_at_20[0x10]; 6140 u8 op_mod[0x10]; 6141 6142 u8 reserved_at_40[0x18]; 6143 u8 eq_number[0x8]; 6144 6145 u8 reserved_at_60[0x20]; 6146 }; 6147 6148 struct mlx5_ifc_destroy_dct_out_bits { 6149 u8 status[0x8]; 6150 u8 reserved_at_8[0x18]; 6151 6152 u8 syndrome[0x20]; 6153 6154 u8 reserved_at_40[0x40]; 6155 }; 6156 6157 struct mlx5_ifc_destroy_dct_in_bits { 6158 u8 opcode[0x10]; 6159 u8 reserved_at_10[0x10]; 6160 6161 u8 reserved_at_20[0x10]; 6162 u8 op_mod[0x10]; 6163 6164 u8 reserved_at_40[0x8]; 6165 u8 dctn[0x18]; 6166 6167 u8 reserved_at_60[0x20]; 6168 }; 6169 6170 struct mlx5_ifc_destroy_cq_out_bits { 6171 u8 status[0x8]; 6172 u8 reserved_at_8[0x18]; 6173 6174 u8 syndrome[0x20]; 6175 6176 u8 reserved_at_40[0x40]; 6177 }; 6178 6179 struct mlx5_ifc_destroy_cq_in_bits { 6180 u8 opcode[0x10]; 6181 u8 reserved_at_10[0x10]; 6182 6183 u8 reserved_at_20[0x10]; 6184 u8 op_mod[0x10]; 6185 6186 u8 reserved_at_40[0x8]; 6187 u8 cqn[0x18]; 6188 6189 u8 reserved_at_60[0x20]; 6190 }; 6191 6192 struct mlx5_ifc_delete_vxlan_udp_dport_out_bits { 6193 u8 status[0x8]; 6194 u8 reserved_at_8[0x18]; 6195 6196 u8 syndrome[0x20]; 6197 6198 u8 reserved_at_40[0x40]; 6199 }; 6200 6201 struct mlx5_ifc_delete_vxlan_udp_dport_in_bits { 6202 u8 opcode[0x10]; 6203 u8 reserved_at_10[0x10]; 6204 6205 u8 reserved_at_20[0x10]; 6206 u8 op_mod[0x10]; 6207 6208 u8 reserved_at_40[0x20]; 6209 6210 u8 reserved_at_60[0x10]; 6211 u8 vxlan_udp_port[0x10]; 6212 }; 6213 6214 struct mlx5_ifc_delete_l2_table_entry_out_bits { 6215 u8 status[0x8]; 6216 u8 reserved_at_8[0x18]; 6217 6218 u8 syndrome[0x20]; 6219 6220 u8 reserved_at_40[0x40]; 6221 }; 6222 6223 struct mlx5_ifc_delete_l2_table_entry_in_bits { 6224 u8 opcode[0x10]; 6225 u8 reserved_at_10[0x10]; 6226 6227 u8 reserved_at_20[0x10]; 6228 u8 op_mod[0x10]; 6229 6230 u8 reserved_at_40[0x60]; 6231 6232 u8 reserved_at_a0[0x8]; 6233 u8 table_index[0x18]; 6234 6235 u8 reserved_at_c0[0x140]; 6236 }; 6237 6238 struct mlx5_ifc_delete_fte_out_bits { 6239 u8 status[0x8]; 6240 u8 reserved_at_8[0x18]; 6241 6242 u8 syndrome[0x20]; 6243 6244 u8 reserved_at_40[0x40]; 6245 }; 6246 6247 struct mlx5_ifc_delete_fte_in_bits { 6248 u8 opcode[0x10]; 6249 u8 reserved_at_10[0x10]; 6250 6251 u8 reserved_at_20[0x10]; 6252 u8 op_mod[0x10]; 6253 6254 u8 other_vport[0x1]; 6255 u8 reserved_at_41[0xf]; 6256 u8 vport_number[0x10]; 6257 6258 u8 reserved_at_60[0x20]; 6259 6260 u8 table_type[0x8]; 6261 u8 reserved_at_88[0x18]; 6262 6263 u8 reserved_at_a0[0x8]; 6264 u8 table_id[0x18]; 6265 6266 u8 reserved_at_c0[0x40]; 6267 6268 u8 flow_index[0x20]; 6269 6270 u8 reserved_at_120[0xe0]; 6271 }; 6272 6273 struct mlx5_ifc_dealloc_xrcd_out_bits { 6274 u8 status[0x8]; 6275 u8 reserved_at_8[0x18]; 6276 6277 u8 syndrome[0x20]; 6278 6279 u8 reserved_at_40[0x40]; 6280 }; 6281 6282 struct mlx5_ifc_dealloc_xrcd_in_bits { 6283 u8 opcode[0x10]; 6284 u8 reserved_at_10[0x10]; 6285 6286 u8 reserved_at_20[0x10]; 6287 u8 op_mod[0x10]; 6288 6289 u8 reserved_at_40[0x8]; 6290 u8 xrcd[0x18]; 6291 6292 u8 reserved_at_60[0x20]; 6293 }; 6294 6295 struct mlx5_ifc_dealloc_uar_out_bits { 6296 u8 status[0x8]; 6297 u8 reserved_at_8[0x18]; 6298 6299 u8 syndrome[0x20]; 6300 6301 u8 reserved_at_40[0x40]; 6302 }; 6303 6304 struct mlx5_ifc_dealloc_uar_in_bits { 6305 u8 opcode[0x10]; 6306 u8 reserved_at_10[0x10]; 6307 6308 u8 reserved_at_20[0x10]; 6309 u8 op_mod[0x10]; 6310 6311 u8 reserved_at_40[0x8]; 6312 u8 uar[0x18]; 6313 6314 u8 reserved_at_60[0x20]; 6315 }; 6316 6317 struct mlx5_ifc_dealloc_transport_domain_out_bits { 6318 u8 status[0x8]; 6319 u8 reserved_at_8[0x18]; 6320 6321 u8 syndrome[0x20]; 6322 6323 u8 reserved_at_40[0x40]; 6324 }; 6325 6326 struct mlx5_ifc_dealloc_transport_domain_in_bits { 6327 u8 opcode[0x10]; 6328 u8 reserved_at_10[0x10]; 6329 6330 u8 reserved_at_20[0x10]; 6331 u8 op_mod[0x10]; 6332 6333 u8 reserved_at_40[0x8]; 6334 u8 transport_domain[0x18]; 6335 6336 u8 reserved_at_60[0x20]; 6337 }; 6338 6339 struct mlx5_ifc_dealloc_q_counter_out_bits { 6340 u8 status[0x8]; 6341 u8 reserved_at_8[0x18]; 6342 6343 u8 syndrome[0x20]; 6344 6345 u8 reserved_at_40[0x40]; 6346 }; 6347 6348 struct mlx5_ifc_dealloc_q_counter_in_bits { 6349 u8 opcode[0x10]; 6350 u8 reserved_at_10[0x10]; 6351 6352 u8 reserved_at_20[0x10]; 6353 u8 op_mod[0x10]; 6354 6355 u8 reserved_at_40[0x18]; 6356 u8 counter_set_id[0x8]; 6357 6358 u8 reserved_at_60[0x20]; 6359 }; 6360 6361 struct mlx5_ifc_dealloc_pd_out_bits { 6362 u8 status[0x8]; 6363 u8 reserved_at_8[0x18]; 6364 6365 u8 syndrome[0x20]; 6366 6367 u8 reserved_at_40[0x40]; 6368 }; 6369 6370 struct mlx5_ifc_dealloc_pd_in_bits { 6371 u8 opcode[0x10]; 6372 u8 reserved_at_10[0x10]; 6373 6374 u8 reserved_at_20[0x10]; 6375 u8 op_mod[0x10]; 6376 6377 u8 reserved_at_40[0x8]; 6378 u8 pd[0x18]; 6379 6380 u8 reserved_at_60[0x20]; 6381 }; 6382 6383 struct mlx5_ifc_dealloc_flow_counter_out_bits { 6384 u8 status[0x8]; 6385 u8 reserved_at_8[0x18]; 6386 6387 u8 syndrome[0x20]; 6388 6389 u8 reserved_at_40[0x40]; 6390 }; 6391 6392 struct mlx5_ifc_dealloc_flow_counter_in_bits { 6393 u8 opcode[0x10]; 6394 u8 reserved_at_10[0x10]; 6395 6396 u8 reserved_at_20[0x10]; 6397 u8 op_mod[0x10]; 6398 6399 u8 flow_counter_id[0x20]; 6400 6401 u8 reserved_at_60[0x20]; 6402 }; 6403 6404 struct mlx5_ifc_create_xrq_out_bits { 6405 u8 status[0x8]; 6406 u8 reserved_at_8[0x18]; 6407 6408 u8 syndrome[0x20]; 6409 6410 u8 reserved_at_40[0x8]; 6411 u8 xrqn[0x18]; 6412 6413 u8 reserved_at_60[0x20]; 6414 }; 6415 6416 struct mlx5_ifc_create_xrq_in_bits { 6417 u8 opcode[0x10]; 6418 u8 reserved_at_10[0x10]; 6419 6420 u8 reserved_at_20[0x10]; 6421 u8 op_mod[0x10]; 6422 6423 u8 reserved_at_40[0x40]; 6424 6425 struct mlx5_ifc_xrqc_bits xrq_context; 6426 }; 6427 6428 struct mlx5_ifc_create_xrc_srq_out_bits { 6429 u8 status[0x8]; 6430 u8 reserved_at_8[0x18]; 6431 6432 u8 syndrome[0x20]; 6433 6434 u8 reserved_at_40[0x8]; 6435 u8 xrc_srqn[0x18]; 6436 6437 u8 reserved_at_60[0x20]; 6438 }; 6439 6440 struct mlx5_ifc_create_xrc_srq_in_bits { 6441 u8 opcode[0x10]; 6442 u8 reserved_at_10[0x10]; 6443 6444 u8 reserved_at_20[0x10]; 6445 u8 op_mod[0x10]; 6446 6447 u8 reserved_at_40[0x40]; 6448 6449 struct mlx5_ifc_xrc_srqc_bits xrc_srq_context_entry; 6450 6451 u8 reserved_at_280[0x600]; 6452 6453 u8 pas[0][0x40]; 6454 }; 6455 6456 struct mlx5_ifc_create_tis_out_bits { 6457 u8 status[0x8]; 6458 u8 reserved_at_8[0x18]; 6459 6460 u8 syndrome[0x20]; 6461 6462 u8 reserved_at_40[0x8]; 6463 u8 tisn[0x18]; 6464 6465 u8 reserved_at_60[0x20]; 6466 }; 6467 6468 struct mlx5_ifc_create_tis_in_bits { 6469 u8 opcode[0x10]; 6470 u8 reserved_at_10[0x10]; 6471 6472 u8 reserved_at_20[0x10]; 6473 u8 op_mod[0x10]; 6474 6475 u8 reserved_at_40[0xc0]; 6476 6477 struct mlx5_ifc_tisc_bits ctx; 6478 }; 6479 6480 struct mlx5_ifc_create_tir_out_bits { 6481 u8 status[0x8]; 6482 u8 reserved_at_8[0x18]; 6483 6484 u8 syndrome[0x20]; 6485 6486 u8 reserved_at_40[0x8]; 6487 u8 tirn[0x18]; 6488 6489 u8 reserved_at_60[0x20]; 6490 }; 6491 6492 struct mlx5_ifc_create_tir_in_bits { 6493 u8 opcode[0x10]; 6494 u8 reserved_at_10[0x10]; 6495 6496 u8 reserved_at_20[0x10]; 6497 u8 op_mod[0x10]; 6498 6499 u8 reserved_at_40[0xc0]; 6500 6501 struct mlx5_ifc_tirc_bits ctx; 6502 }; 6503 6504 struct mlx5_ifc_create_srq_out_bits { 6505 u8 status[0x8]; 6506 u8 reserved_at_8[0x18]; 6507 6508 u8 syndrome[0x20]; 6509 6510 u8 reserved_at_40[0x8]; 6511 u8 srqn[0x18]; 6512 6513 u8 reserved_at_60[0x20]; 6514 }; 6515 6516 struct mlx5_ifc_create_srq_in_bits { 6517 u8 opcode[0x10]; 6518 u8 reserved_at_10[0x10]; 6519 6520 u8 reserved_at_20[0x10]; 6521 u8 op_mod[0x10]; 6522 6523 u8 reserved_at_40[0x40]; 6524 6525 struct mlx5_ifc_srqc_bits srq_context_entry; 6526 6527 u8 reserved_at_280[0x600]; 6528 6529 u8 pas[0][0x40]; 6530 }; 6531 6532 struct mlx5_ifc_create_sq_out_bits { 6533 u8 status[0x8]; 6534 u8 reserved_at_8[0x18]; 6535 6536 u8 syndrome[0x20]; 6537 6538 u8 reserved_at_40[0x8]; 6539 u8 sqn[0x18]; 6540 6541 u8 reserved_at_60[0x20]; 6542 }; 6543 6544 struct mlx5_ifc_create_sq_in_bits { 6545 u8 opcode[0x10]; 6546 u8 reserved_at_10[0x10]; 6547 6548 u8 reserved_at_20[0x10]; 6549 u8 op_mod[0x10]; 6550 6551 u8 reserved_at_40[0xc0]; 6552 6553 struct mlx5_ifc_sqc_bits ctx; 6554 }; 6555 6556 struct mlx5_ifc_create_scheduling_element_out_bits { 6557 u8 status[0x8]; 6558 u8 reserved_at_8[0x18]; 6559 6560 u8 syndrome[0x20]; 6561 6562 u8 reserved_at_40[0x40]; 6563 6564 u8 scheduling_element_id[0x20]; 6565 6566 u8 reserved_at_a0[0x160]; 6567 }; 6568 6569 struct mlx5_ifc_create_scheduling_element_in_bits { 6570 u8 opcode[0x10]; 6571 u8 reserved_at_10[0x10]; 6572 6573 u8 reserved_at_20[0x10]; 6574 u8 op_mod[0x10]; 6575 6576 u8 scheduling_hierarchy[0x8]; 6577 u8 reserved_at_48[0x18]; 6578 6579 u8 reserved_at_60[0xa0]; 6580 6581 struct mlx5_ifc_scheduling_context_bits scheduling_context; 6582 6583 u8 reserved_at_300[0x100]; 6584 }; 6585 6586 struct mlx5_ifc_create_rqt_out_bits { 6587 u8 status[0x8]; 6588 u8 reserved_at_8[0x18]; 6589 6590 u8 syndrome[0x20]; 6591 6592 u8 reserved_at_40[0x8]; 6593 u8 rqtn[0x18]; 6594 6595 u8 reserved_at_60[0x20]; 6596 }; 6597 6598 struct mlx5_ifc_create_rqt_in_bits { 6599 u8 opcode[0x10]; 6600 u8 reserved_at_10[0x10]; 6601 6602 u8 reserved_at_20[0x10]; 6603 u8 op_mod[0x10]; 6604 6605 u8 reserved_at_40[0xc0]; 6606 6607 struct mlx5_ifc_rqtc_bits rqt_context; 6608 }; 6609 6610 struct mlx5_ifc_create_rq_out_bits { 6611 u8 status[0x8]; 6612 u8 reserved_at_8[0x18]; 6613 6614 u8 syndrome[0x20]; 6615 6616 u8 reserved_at_40[0x8]; 6617 u8 rqn[0x18]; 6618 6619 u8 reserved_at_60[0x20]; 6620 }; 6621 6622 struct mlx5_ifc_create_rq_in_bits { 6623 u8 opcode[0x10]; 6624 u8 reserved_at_10[0x10]; 6625 6626 u8 reserved_at_20[0x10]; 6627 u8 op_mod[0x10]; 6628 6629 u8 reserved_at_40[0xc0]; 6630 6631 struct mlx5_ifc_rqc_bits ctx; 6632 }; 6633 6634 struct mlx5_ifc_create_rmp_out_bits { 6635 u8 status[0x8]; 6636 u8 reserved_at_8[0x18]; 6637 6638 u8 syndrome[0x20]; 6639 6640 u8 reserved_at_40[0x8]; 6641 u8 rmpn[0x18]; 6642 6643 u8 reserved_at_60[0x20]; 6644 }; 6645 6646 struct mlx5_ifc_create_rmp_in_bits { 6647 u8 opcode[0x10]; 6648 u8 reserved_at_10[0x10]; 6649 6650 u8 reserved_at_20[0x10]; 6651 u8 op_mod[0x10]; 6652 6653 u8 reserved_at_40[0xc0]; 6654 6655 struct mlx5_ifc_rmpc_bits ctx; 6656 }; 6657 6658 struct mlx5_ifc_create_qp_out_bits { 6659 u8 status[0x8]; 6660 u8 reserved_at_8[0x18]; 6661 6662 u8 syndrome[0x20]; 6663 6664 u8 reserved_at_40[0x8]; 6665 u8 qpn[0x18]; 6666 6667 u8 reserved_at_60[0x20]; 6668 }; 6669 6670 struct mlx5_ifc_create_qp_in_bits { 6671 u8 opcode[0x10]; 6672 u8 reserved_at_10[0x10]; 6673 6674 u8 reserved_at_20[0x10]; 6675 u8 op_mod[0x10]; 6676 6677 u8 reserved_at_40[0x40]; 6678 6679 u8 opt_param_mask[0x20]; 6680 6681 u8 reserved_at_a0[0x20]; 6682 6683 struct mlx5_ifc_qpc_bits qpc; 6684 6685 u8 reserved_at_800[0x80]; 6686 6687 u8 pas[0][0x40]; 6688 }; 6689 6690 struct mlx5_ifc_create_psv_out_bits { 6691 u8 status[0x8]; 6692 u8 reserved_at_8[0x18]; 6693 6694 u8 syndrome[0x20]; 6695 6696 u8 reserved_at_40[0x40]; 6697 6698 u8 reserved_at_80[0x8]; 6699 u8 psv0_index[0x18]; 6700 6701 u8 reserved_at_a0[0x8]; 6702 u8 psv1_index[0x18]; 6703 6704 u8 reserved_at_c0[0x8]; 6705 u8 psv2_index[0x18]; 6706 6707 u8 reserved_at_e0[0x8]; 6708 u8 psv3_index[0x18]; 6709 }; 6710 6711 struct mlx5_ifc_create_psv_in_bits { 6712 u8 opcode[0x10]; 6713 u8 reserved_at_10[0x10]; 6714 6715 u8 reserved_at_20[0x10]; 6716 u8 op_mod[0x10]; 6717 6718 u8 num_psv[0x4]; 6719 u8 reserved_at_44[0x4]; 6720 u8 pd[0x18]; 6721 6722 u8 reserved_at_60[0x20]; 6723 }; 6724 6725 struct mlx5_ifc_create_mkey_out_bits { 6726 u8 status[0x8]; 6727 u8 reserved_at_8[0x18]; 6728 6729 u8 syndrome[0x20]; 6730 6731 u8 reserved_at_40[0x8]; 6732 u8 mkey_index[0x18]; 6733 6734 u8 reserved_at_60[0x20]; 6735 }; 6736 6737 struct mlx5_ifc_create_mkey_in_bits { 6738 u8 opcode[0x10]; 6739 u8 reserved_at_10[0x10]; 6740 6741 u8 reserved_at_20[0x10]; 6742 u8 op_mod[0x10]; 6743 6744 u8 reserved_at_40[0x20]; 6745 6746 u8 pg_access[0x1]; 6747 u8 reserved_at_61[0x1f]; 6748 6749 struct mlx5_ifc_mkc_bits memory_key_mkey_entry; 6750 6751 u8 reserved_at_280[0x80]; 6752 6753 u8 translations_octword_actual_size[0x20]; 6754 6755 u8 reserved_at_320[0x560]; 6756 6757 u8 klm_pas_mtt[0][0x20]; 6758 }; 6759 6760 struct mlx5_ifc_create_flow_table_out_bits { 6761 u8 status[0x8]; 6762 u8 reserved_at_8[0x18]; 6763 6764 u8 syndrome[0x20]; 6765 6766 u8 reserved_at_40[0x8]; 6767 u8 table_id[0x18]; 6768 6769 u8 reserved_at_60[0x20]; 6770 }; 6771 6772 struct mlx5_ifc_flow_table_context_bits { 6773 u8 encap_en[0x1]; 6774 u8 decap_en[0x1]; 6775 u8 reserved_at_2[0x2]; 6776 u8 table_miss_action[0x4]; 6777 u8 level[0x8]; 6778 u8 reserved_at_10[0x8]; 6779 u8 log_size[0x8]; 6780 6781 u8 reserved_at_20[0x8]; 6782 u8 table_miss_id[0x18]; 6783 6784 u8 reserved_at_40[0x8]; 6785 u8 lag_master_next_table_id[0x18]; 6786 6787 u8 reserved_at_60[0xe0]; 6788 }; 6789 6790 struct mlx5_ifc_create_flow_table_in_bits { 6791 u8 opcode[0x10]; 6792 u8 reserved_at_10[0x10]; 6793 6794 u8 reserved_at_20[0x10]; 6795 u8 op_mod[0x10]; 6796 6797 u8 other_vport[0x1]; 6798 u8 reserved_at_41[0xf]; 6799 u8 vport_number[0x10]; 6800 6801 u8 reserved_at_60[0x20]; 6802 6803 u8 table_type[0x8]; 6804 u8 reserved_at_88[0x18]; 6805 6806 u8 reserved_at_a0[0x20]; 6807 6808 struct mlx5_ifc_flow_table_context_bits flow_table_context; 6809 }; 6810 6811 struct mlx5_ifc_create_flow_group_out_bits { 6812 u8 status[0x8]; 6813 u8 reserved_at_8[0x18]; 6814 6815 u8 syndrome[0x20]; 6816 6817 u8 reserved_at_40[0x8]; 6818 u8 group_id[0x18]; 6819 6820 u8 reserved_at_60[0x20]; 6821 }; 6822 6823 enum { 6824 MLX5_CREATE_FLOW_GROUP_IN_MATCH_CRITERIA_ENABLE_OUTER_HEADERS = 0x0, 6825 MLX5_CREATE_FLOW_GROUP_IN_MATCH_CRITERIA_ENABLE_MISC_PARAMETERS = 0x1, 6826 MLX5_CREATE_FLOW_GROUP_IN_MATCH_CRITERIA_ENABLE_INNER_HEADERS = 0x2, 6827 }; 6828 6829 struct mlx5_ifc_create_flow_group_in_bits { 6830 u8 opcode[0x10]; 6831 u8 reserved_at_10[0x10]; 6832 6833 u8 reserved_at_20[0x10]; 6834 u8 op_mod[0x10]; 6835 6836 u8 other_vport[0x1]; 6837 u8 reserved_at_41[0xf]; 6838 u8 vport_number[0x10]; 6839 6840 u8 reserved_at_60[0x20]; 6841 6842 u8 table_type[0x8]; 6843 u8 reserved_at_88[0x18]; 6844 6845 u8 reserved_at_a0[0x8]; 6846 u8 table_id[0x18]; 6847 6848 u8 reserved_at_c0[0x20]; 6849 6850 u8 start_flow_index[0x20]; 6851 6852 u8 reserved_at_100[0x20]; 6853 6854 u8 end_flow_index[0x20]; 6855 6856 u8 reserved_at_140[0xa0]; 6857 6858 u8 reserved_at_1e0[0x18]; 6859 u8 match_criteria_enable[0x8]; 6860 6861 struct mlx5_ifc_fte_match_param_bits match_criteria; 6862 6863 u8 reserved_at_1200[0xe00]; 6864 }; 6865 6866 struct mlx5_ifc_create_eq_out_bits { 6867 u8 status[0x8]; 6868 u8 reserved_at_8[0x18]; 6869 6870 u8 syndrome[0x20]; 6871 6872 u8 reserved_at_40[0x18]; 6873 u8 eq_number[0x8]; 6874 6875 u8 reserved_at_60[0x20]; 6876 }; 6877 6878 struct mlx5_ifc_create_eq_in_bits { 6879 u8 opcode[0x10]; 6880 u8 reserved_at_10[0x10]; 6881 6882 u8 reserved_at_20[0x10]; 6883 u8 op_mod[0x10]; 6884 6885 u8 reserved_at_40[0x40]; 6886 6887 struct mlx5_ifc_eqc_bits eq_context_entry; 6888 6889 u8 reserved_at_280[0x40]; 6890 6891 u8 event_bitmask[0x40]; 6892 6893 u8 reserved_at_300[0x580]; 6894 6895 u8 pas[0][0x40]; 6896 }; 6897 6898 struct mlx5_ifc_create_dct_out_bits { 6899 u8 status[0x8]; 6900 u8 reserved_at_8[0x18]; 6901 6902 u8 syndrome[0x20]; 6903 6904 u8 reserved_at_40[0x8]; 6905 u8 dctn[0x18]; 6906 6907 u8 reserved_at_60[0x20]; 6908 }; 6909 6910 struct mlx5_ifc_create_dct_in_bits { 6911 u8 opcode[0x10]; 6912 u8 reserved_at_10[0x10]; 6913 6914 u8 reserved_at_20[0x10]; 6915 u8 op_mod[0x10]; 6916 6917 u8 reserved_at_40[0x40]; 6918 6919 struct mlx5_ifc_dctc_bits dct_context_entry; 6920 6921 u8 reserved_at_280[0x180]; 6922 }; 6923 6924 struct mlx5_ifc_create_cq_out_bits { 6925 u8 status[0x8]; 6926 u8 reserved_at_8[0x18]; 6927 6928 u8 syndrome[0x20]; 6929 6930 u8 reserved_at_40[0x8]; 6931 u8 cqn[0x18]; 6932 6933 u8 reserved_at_60[0x20]; 6934 }; 6935 6936 struct mlx5_ifc_create_cq_in_bits { 6937 u8 opcode[0x10]; 6938 u8 reserved_at_10[0x10]; 6939 6940 u8 reserved_at_20[0x10]; 6941 u8 op_mod[0x10]; 6942 6943 u8 reserved_at_40[0x40]; 6944 6945 struct mlx5_ifc_cqc_bits cq_context; 6946 6947 u8 reserved_at_280[0x600]; 6948 6949 u8 pas[0][0x40]; 6950 }; 6951 6952 struct mlx5_ifc_config_int_moderation_out_bits { 6953 u8 status[0x8]; 6954 u8 reserved_at_8[0x18]; 6955 6956 u8 syndrome[0x20]; 6957 6958 u8 reserved_at_40[0x4]; 6959 u8 min_delay[0xc]; 6960 u8 int_vector[0x10]; 6961 6962 u8 reserved_at_60[0x20]; 6963 }; 6964 6965 enum { 6966 MLX5_CONFIG_INT_MODERATION_IN_OP_MOD_WRITE = 0x0, 6967 MLX5_CONFIG_INT_MODERATION_IN_OP_MOD_READ = 0x1, 6968 }; 6969 6970 struct mlx5_ifc_config_int_moderation_in_bits { 6971 u8 opcode[0x10]; 6972 u8 reserved_at_10[0x10]; 6973 6974 u8 reserved_at_20[0x10]; 6975 u8 op_mod[0x10]; 6976 6977 u8 reserved_at_40[0x4]; 6978 u8 min_delay[0xc]; 6979 u8 int_vector[0x10]; 6980 6981 u8 reserved_at_60[0x20]; 6982 }; 6983 6984 struct mlx5_ifc_attach_to_mcg_out_bits { 6985 u8 status[0x8]; 6986 u8 reserved_at_8[0x18]; 6987 6988 u8 syndrome[0x20]; 6989 6990 u8 reserved_at_40[0x40]; 6991 }; 6992 6993 struct mlx5_ifc_attach_to_mcg_in_bits { 6994 u8 opcode[0x10]; 6995 u8 reserved_at_10[0x10]; 6996 6997 u8 reserved_at_20[0x10]; 6998 u8 op_mod[0x10]; 6999 7000 u8 reserved_at_40[0x8]; 7001 u8 qpn[0x18]; 7002 7003 u8 reserved_at_60[0x20]; 7004 7005 u8 multicast_gid[16][0x8]; 7006 }; 7007 7008 struct mlx5_ifc_arm_xrq_out_bits { 7009 u8 status[0x8]; 7010 u8 reserved_at_8[0x18]; 7011 7012 u8 syndrome[0x20]; 7013 7014 u8 reserved_at_40[0x40]; 7015 }; 7016 7017 struct mlx5_ifc_arm_xrq_in_bits { 7018 u8 opcode[0x10]; 7019 u8 reserved_at_10[0x10]; 7020 7021 u8 reserved_at_20[0x10]; 7022 u8 op_mod[0x10]; 7023 7024 u8 reserved_at_40[0x8]; 7025 u8 xrqn[0x18]; 7026 7027 u8 reserved_at_60[0x10]; 7028 u8 lwm[0x10]; 7029 }; 7030 7031 struct mlx5_ifc_arm_xrc_srq_out_bits { 7032 u8 status[0x8]; 7033 u8 reserved_at_8[0x18]; 7034 7035 u8 syndrome[0x20]; 7036 7037 u8 reserved_at_40[0x40]; 7038 }; 7039 7040 enum { 7041 MLX5_ARM_XRC_SRQ_IN_OP_MOD_XRC_SRQ = 0x1, 7042 }; 7043 7044 struct mlx5_ifc_arm_xrc_srq_in_bits { 7045 u8 opcode[0x10]; 7046 u8 reserved_at_10[0x10]; 7047 7048 u8 reserved_at_20[0x10]; 7049 u8 op_mod[0x10]; 7050 7051 u8 reserved_at_40[0x8]; 7052 u8 xrc_srqn[0x18]; 7053 7054 u8 reserved_at_60[0x10]; 7055 u8 lwm[0x10]; 7056 }; 7057 7058 struct mlx5_ifc_arm_rq_out_bits { 7059 u8 status[0x8]; 7060 u8 reserved_at_8[0x18]; 7061 7062 u8 syndrome[0x20]; 7063 7064 u8 reserved_at_40[0x40]; 7065 }; 7066 7067 enum { 7068 MLX5_ARM_RQ_IN_OP_MOD_SRQ = 0x1, 7069 MLX5_ARM_RQ_IN_OP_MOD_XRQ = 0x2, 7070 }; 7071 7072 struct mlx5_ifc_arm_rq_in_bits { 7073 u8 opcode[0x10]; 7074 u8 reserved_at_10[0x10]; 7075 7076 u8 reserved_at_20[0x10]; 7077 u8 op_mod[0x10]; 7078 7079 u8 reserved_at_40[0x8]; 7080 u8 srq_number[0x18]; 7081 7082 u8 reserved_at_60[0x10]; 7083 u8 lwm[0x10]; 7084 }; 7085 7086 struct mlx5_ifc_arm_dct_out_bits { 7087 u8 status[0x8]; 7088 u8 reserved_at_8[0x18]; 7089 7090 u8 syndrome[0x20]; 7091 7092 u8 reserved_at_40[0x40]; 7093 }; 7094 7095 struct mlx5_ifc_arm_dct_in_bits { 7096 u8 opcode[0x10]; 7097 u8 reserved_at_10[0x10]; 7098 7099 u8 reserved_at_20[0x10]; 7100 u8 op_mod[0x10]; 7101 7102 u8 reserved_at_40[0x8]; 7103 u8 dct_number[0x18]; 7104 7105 u8 reserved_at_60[0x20]; 7106 }; 7107 7108 struct mlx5_ifc_alloc_xrcd_out_bits { 7109 u8 status[0x8]; 7110 u8 reserved_at_8[0x18]; 7111 7112 u8 syndrome[0x20]; 7113 7114 u8 reserved_at_40[0x8]; 7115 u8 xrcd[0x18]; 7116 7117 u8 reserved_at_60[0x20]; 7118 }; 7119 7120 struct mlx5_ifc_alloc_xrcd_in_bits { 7121 u8 opcode[0x10]; 7122 u8 reserved_at_10[0x10]; 7123 7124 u8 reserved_at_20[0x10]; 7125 u8 op_mod[0x10]; 7126 7127 u8 reserved_at_40[0x40]; 7128 }; 7129 7130 struct mlx5_ifc_alloc_uar_out_bits { 7131 u8 status[0x8]; 7132 u8 reserved_at_8[0x18]; 7133 7134 u8 syndrome[0x20]; 7135 7136 u8 reserved_at_40[0x8]; 7137 u8 uar[0x18]; 7138 7139 u8 reserved_at_60[0x20]; 7140 }; 7141 7142 struct mlx5_ifc_alloc_uar_in_bits { 7143 u8 opcode[0x10]; 7144 u8 reserved_at_10[0x10]; 7145 7146 u8 reserved_at_20[0x10]; 7147 u8 op_mod[0x10]; 7148 7149 u8 reserved_at_40[0x40]; 7150 }; 7151 7152 struct mlx5_ifc_alloc_transport_domain_out_bits { 7153 u8 status[0x8]; 7154 u8 reserved_at_8[0x18]; 7155 7156 u8 syndrome[0x20]; 7157 7158 u8 reserved_at_40[0x8]; 7159 u8 transport_domain[0x18]; 7160 7161 u8 reserved_at_60[0x20]; 7162 }; 7163 7164 struct mlx5_ifc_alloc_transport_domain_in_bits { 7165 u8 opcode[0x10]; 7166 u8 reserved_at_10[0x10]; 7167 7168 u8 reserved_at_20[0x10]; 7169 u8 op_mod[0x10]; 7170 7171 u8 reserved_at_40[0x40]; 7172 }; 7173 7174 struct mlx5_ifc_alloc_q_counter_out_bits { 7175 u8 status[0x8]; 7176 u8 reserved_at_8[0x18]; 7177 7178 u8 syndrome[0x20]; 7179 7180 u8 reserved_at_40[0x18]; 7181 u8 counter_set_id[0x8]; 7182 7183 u8 reserved_at_60[0x20]; 7184 }; 7185 7186 struct mlx5_ifc_alloc_q_counter_in_bits { 7187 u8 opcode[0x10]; 7188 u8 reserved_at_10[0x10]; 7189 7190 u8 reserved_at_20[0x10]; 7191 u8 op_mod[0x10]; 7192 7193 u8 reserved_at_40[0x40]; 7194 }; 7195 7196 struct mlx5_ifc_alloc_pd_out_bits { 7197 u8 status[0x8]; 7198 u8 reserved_at_8[0x18]; 7199 7200 u8 syndrome[0x20]; 7201 7202 u8 reserved_at_40[0x8]; 7203 u8 pd[0x18]; 7204 7205 u8 reserved_at_60[0x20]; 7206 }; 7207 7208 struct mlx5_ifc_alloc_pd_in_bits { 7209 u8 opcode[0x10]; 7210 u8 reserved_at_10[0x10]; 7211 7212 u8 reserved_at_20[0x10]; 7213 u8 op_mod[0x10]; 7214 7215 u8 reserved_at_40[0x40]; 7216 }; 7217 7218 struct mlx5_ifc_alloc_flow_counter_out_bits { 7219 u8 status[0x8]; 7220 u8 reserved_at_8[0x18]; 7221 7222 u8 syndrome[0x20]; 7223 7224 u8 flow_counter_id[0x20]; 7225 7226 u8 reserved_at_60[0x20]; 7227 }; 7228 7229 struct mlx5_ifc_alloc_flow_counter_in_bits { 7230 u8 opcode[0x10]; 7231 u8 reserved_at_10[0x10]; 7232 7233 u8 reserved_at_20[0x10]; 7234 u8 op_mod[0x10]; 7235 7236 u8 reserved_at_40[0x40]; 7237 }; 7238 7239 struct mlx5_ifc_add_vxlan_udp_dport_out_bits { 7240 u8 status[0x8]; 7241 u8 reserved_at_8[0x18]; 7242 7243 u8 syndrome[0x20]; 7244 7245 u8 reserved_at_40[0x40]; 7246 }; 7247 7248 struct mlx5_ifc_add_vxlan_udp_dport_in_bits { 7249 u8 opcode[0x10]; 7250 u8 reserved_at_10[0x10]; 7251 7252 u8 reserved_at_20[0x10]; 7253 u8 op_mod[0x10]; 7254 7255 u8 reserved_at_40[0x20]; 7256 7257 u8 reserved_at_60[0x10]; 7258 u8 vxlan_udp_port[0x10]; 7259 }; 7260 7261 struct mlx5_ifc_set_pp_rate_limit_out_bits { 7262 u8 status[0x8]; 7263 u8 reserved_at_8[0x18]; 7264 7265 u8 syndrome[0x20]; 7266 7267 u8 reserved_at_40[0x40]; 7268 }; 7269 7270 struct mlx5_ifc_set_pp_rate_limit_in_bits { 7271 u8 opcode[0x10]; 7272 u8 reserved_at_10[0x10]; 7273 7274 u8 reserved_at_20[0x10]; 7275 u8 op_mod[0x10]; 7276 7277 u8 reserved_at_40[0x10]; 7278 u8 rate_limit_index[0x10]; 7279 7280 u8 reserved_at_60[0x20]; 7281 7282 u8 rate_limit[0x20]; 7283 7284 u8 reserved_at_a0[0x160]; 7285 }; 7286 7287 struct mlx5_ifc_access_register_out_bits { 7288 u8 status[0x8]; 7289 u8 reserved_at_8[0x18]; 7290 7291 u8 syndrome[0x20]; 7292 7293 u8 reserved_at_40[0x40]; 7294 7295 u8 register_data[0][0x20]; 7296 }; 7297 7298 enum { 7299 MLX5_ACCESS_REGISTER_IN_OP_MOD_WRITE = 0x0, 7300 MLX5_ACCESS_REGISTER_IN_OP_MOD_READ = 0x1, 7301 }; 7302 7303 struct mlx5_ifc_access_register_in_bits { 7304 u8 opcode[0x10]; 7305 u8 reserved_at_10[0x10]; 7306 7307 u8 reserved_at_20[0x10]; 7308 u8 op_mod[0x10]; 7309 7310 u8 reserved_at_40[0x10]; 7311 u8 register_id[0x10]; 7312 7313 u8 argument[0x20]; 7314 7315 u8 register_data[0][0x20]; 7316 }; 7317 7318 struct mlx5_ifc_sltp_reg_bits { 7319 u8 status[0x4]; 7320 u8 version[0x4]; 7321 u8 local_port[0x8]; 7322 u8 pnat[0x2]; 7323 u8 reserved_at_12[0x2]; 7324 u8 lane[0x4]; 7325 u8 reserved_at_18[0x8]; 7326 7327 u8 reserved_at_20[0x20]; 7328 7329 u8 reserved_at_40[0x7]; 7330 u8 polarity[0x1]; 7331 u8 ob_tap0[0x8]; 7332 u8 ob_tap1[0x8]; 7333 u8 ob_tap2[0x8]; 7334 7335 u8 reserved_at_60[0xc]; 7336 u8 ob_preemp_mode[0x4]; 7337 u8 ob_reg[0x8]; 7338 u8 ob_bias[0x8]; 7339 7340 u8 reserved_at_80[0x20]; 7341 }; 7342 7343 struct mlx5_ifc_slrg_reg_bits { 7344 u8 status[0x4]; 7345 u8 version[0x4]; 7346 u8 local_port[0x8]; 7347 u8 pnat[0x2]; 7348 u8 reserved_at_12[0x2]; 7349 u8 lane[0x4]; 7350 u8 reserved_at_18[0x8]; 7351 7352 u8 time_to_link_up[0x10]; 7353 u8 reserved_at_30[0xc]; 7354 u8 grade_lane_speed[0x4]; 7355 7356 u8 grade_version[0x8]; 7357 u8 grade[0x18]; 7358 7359 u8 reserved_at_60[0x4]; 7360 u8 height_grade_type[0x4]; 7361 u8 height_grade[0x18]; 7362 7363 u8 height_dz[0x10]; 7364 u8 height_dv[0x10]; 7365 7366 u8 reserved_at_a0[0x10]; 7367 u8 height_sigma[0x10]; 7368 7369 u8 reserved_at_c0[0x20]; 7370 7371 u8 reserved_at_e0[0x4]; 7372 u8 phase_grade_type[0x4]; 7373 u8 phase_grade[0x18]; 7374 7375 u8 reserved_at_100[0x8]; 7376 u8 phase_eo_pos[0x8]; 7377 u8 reserved_at_110[0x8]; 7378 u8 phase_eo_neg[0x8]; 7379 7380 u8 ffe_set_tested[0x10]; 7381 u8 test_errors_per_lane[0x10]; 7382 }; 7383 7384 struct mlx5_ifc_pvlc_reg_bits { 7385 u8 reserved_at_0[0x8]; 7386 u8 local_port[0x8]; 7387 u8 reserved_at_10[0x10]; 7388 7389 u8 reserved_at_20[0x1c]; 7390 u8 vl_hw_cap[0x4]; 7391 7392 u8 reserved_at_40[0x1c]; 7393 u8 vl_admin[0x4]; 7394 7395 u8 reserved_at_60[0x1c]; 7396 u8 vl_operational[0x4]; 7397 }; 7398 7399 struct mlx5_ifc_pude_reg_bits { 7400 u8 swid[0x8]; 7401 u8 local_port[0x8]; 7402 u8 reserved_at_10[0x4]; 7403 u8 admin_status[0x4]; 7404 u8 reserved_at_18[0x4]; 7405 u8 oper_status[0x4]; 7406 7407 u8 reserved_at_20[0x60]; 7408 }; 7409 7410 struct mlx5_ifc_ptys_reg_bits { 7411 u8 reserved_at_0[0x1]; 7412 u8 an_disable_admin[0x1]; 7413 u8 an_disable_cap[0x1]; 7414 u8 reserved_at_3[0x5]; 7415 u8 local_port[0x8]; 7416 u8 reserved_at_10[0xd]; 7417 u8 proto_mask[0x3]; 7418 7419 u8 an_status[0x4]; 7420 u8 reserved_at_24[0x3c]; 7421 7422 u8 eth_proto_capability[0x20]; 7423 7424 u8 ib_link_width_capability[0x10]; 7425 u8 ib_proto_capability[0x10]; 7426 7427 u8 reserved_at_a0[0x20]; 7428 7429 u8 eth_proto_admin[0x20]; 7430 7431 u8 ib_link_width_admin[0x10]; 7432 u8 ib_proto_admin[0x10]; 7433 7434 u8 reserved_at_100[0x20]; 7435 7436 u8 eth_proto_oper[0x20]; 7437 7438 u8 ib_link_width_oper[0x10]; 7439 u8 ib_proto_oper[0x10]; 7440 7441 u8 reserved_at_160[0x1c]; 7442 u8 connector_type[0x4]; 7443 7444 u8 eth_proto_lp_advertise[0x20]; 7445 7446 u8 reserved_at_1a0[0x60]; 7447 }; 7448 7449 struct mlx5_ifc_mlcr_reg_bits { 7450 u8 reserved_at_0[0x8]; 7451 u8 local_port[0x8]; 7452 u8 reserved_at_10[0x20]; 7453 7454 u8 beacon_duration[0x10]; 7455 u8 reserved_at_40[0x10]; 7456 7457 u8 beacon_remain[0x10]; 7458 }; 7459 7460 struct mlx5_ifc_ptas_reg_bits { 7461 u8 reserved_at_0[0x20]; 7462 7463 u8 algorithm_options[0x10]; 7464 u8 reserved_at_30[0x4]; 7465 u8 repetitions_mode[0x4]; 7466 u8 num_of_repetitions[0x8]; 7467 7468 u8 grade_version[0x8]; 7469 u8 height_grade_type[0x4]; 7470 u8 phase_grade_type[0x4]; 7471 u8 height_grade_weight[0x8]; 7472 u8 phase_grade_weight[0x8]; 7473 7474 u8 gisim_measure_bits[0x10]; 7475 u8 adaptive_tap_measure_bits[0x10]; 7476 7477 u8 ber_bath_high_error_threshold[0x10]; 7478 u8 ber_bath_mid_error_threshold[0x10]; 7479 7480 u8 ber_bath_low_error_threshold[0x10]; 7481 u8 one_ratio_high_threshold[0x10]; 7482 7483 u8 one_ratio_high_mid_threshold[0x10]; 7484 u8 one_ratio_low_mid_threshold[0x10]; 7485 7486 u8 one_ratio_low_threshold[0x10]; 7487 u8 ndeo_error_threshold[0x10]; 7488 7489 u8 mixer_offset_step_size[0x10]; 7490 u8 reserved_at_110[0x8]; 7491 u8 mix90_phase_for_voltage_bath[0x8]; 7492 7493 u8 mixer_offset_start[0x10]; 7494 u8 mixer_offset_end[0x10]; 7495 7496 u8 reserved_at_140[0x15]; 7497 u8 ber_test_time[0xb]; 7498 }; 7499 7500 struct mlx5_ifc_pspa_reg_bits { 7501 u8 swid[0x8]; 7502 u8 local_port[0x8]; 7503 u8 sub_port[0x8]; 7504 u8 reserved_at_18[0x8]; 7505 7506 u8 reserved_at_20[0x20]; 7507 }; 7508 7509 struct mlx5_ifc_pqdr_reg_bits { 7510 u8 reserved_at_0[0x8]; 7511 u8 local_port[0x8]; 7512 u8 reserved_at_10[0x5]; 7513 u8 prio[0x3]; 7514 u8 reserved_at_18[0x6]; 7515 u8 mode[0x2]; 7516 7517 u8 reserved_at_20[0x20]; 7518 7519 u8 reserved_at_40[0x10]; 7520 u8 min_threshold[0x10]; 7521 7522 u8 reserved_at_60[0x10]; 7523 u8 max_threshold[0x10]; 7524 7525 u8 reserved_at_80[0x10]; 7526 u8 mark_probability_denominator[0x10]; 7527 7528 u8 reserved_at_a0[0x60]; 7529 }; 7530 7531 struct mlx5_ifc_ppsc_reg_bits { 7532 u8 reserved_at_0[0x8]; 7533 u8 local_port[0x8]; 7534 u8 reserved_at_10[0x10]; 7535 7536 u8 reserved_at_20[0x60]; 7537 7538 u8 reserved_at_80[0x1c]; 7539 u8 wrps_admin[0x4]; 7540 7541 u8 reserved_at_a0[0x1c]; 7542 u8 wrps_status[0x4]; 7543 7544 u8 reserved_at_c0[0x8]; 7545 u8 up_threshold[0x8]; 7546 u8 reserved_at_d0[0x8]; 7547 u8 down_threshold[0x8]; 7548 7549 u8 reserved_at_e0[0x20]; 7550 7551 u8 reserved_at_100[0x1c]; 7552 u8 srps_admin[0x4]; 7553 7554 u8 reserved_at_120[0x1c]; 7555 u8 srps_status[0x4]; 7556 7557 u8 reserved_at_140[0x40]; 7558 }; 7559 7560 struct mlx5_ifc_pplr_reg_bits { 7561 u8 reserved_at_0[0x8]; 7562 u8 local_port[0x8]; 7563 u8 reserved_at_10[0x10]; 7564 7565 u8 reserved_at_20[0x8]; 7566 u8 lb_cap[0x8]; 7567 u8 reserved_at_30[0x8]; 7568 u8 lb_en[0x8]; 7569 }; 7570 7571 struct mlx5_ifc_pplm_reg_bits { 7572 u8 reserved_at_0[0x8]; 7573 u8 local_port[0x8]; 7574 u8 reserved_at_10[0x10]; 7575 7576 u8 reserved_at_20[0x20]; 7577 7578 u8 port_profile_mode[0x8]; 7579 u8 static_port_profile[0x8]; 7580 u8 active_port_profile[0x8]; 7581 u8 reserved_at_58[0x8]; 7582 7583 u8 retransmission_active[0x8]; 7584 u8 fec_mode_active[0x18]; 7585 7586 u8 reserved_at_80[0x20]; 7587 }; 7588 7589 struct mlx5_ifc_ppcnt_reg_bits { 7590 u8 swid[0x8]; 7591 u8 local_port[0x8]; 7592 u8 pnat[0x2]; 7593 u8 reserved_at_12[0x8]; 7594 u8 grp[0x6]; 7595 7596 u8 clr[0x1]; 7597 u8 reserved_at_21[0x1c]; 7598 u8 prio_tc[0x3]; 7599 7600 union mlx5_ifc_eth_cntrs_grp_data_layout_auto_bits counter_set; 7601 }; 7602 7603 struct mlx5_ifc_mpcnt_reg_bits { 7604 u8 reserved_at_0[0x8]; 7605 u8 pcie_index[0x8]; 7606 u8 reserved_at_10[0xa]; 7607 u8 grp[0x6]; 7608 7609 u8 clr[0x1]; 7610 u8 reserved_at_21[0x1f]; 7611 7612 union mlx5_ifc_pcie_cntrs_grp_data_layout_auto_bits counter_set; 7613 }; 7614 7615 struct mlx5_ifc_ppad_reg_bits { 7616 u8 reserved_at_0[0x3]; 7617 u8 single_mac[0x1]; 7618 u8 reserved_at_4[0x4]; 7619 u8 local_port[0x8]; 7620 u8 mac_47_32[0x10]; 7621 7622 u8 mac_31_0[0x20]; 7623 7624 u8 reserved_at_40[0x40]; 7625 }; 7626 7627 struct mlx5_ifc_pmtu_reg_bits { 7628 u8 reserved_at_0[0x8]; 7629 u8 local_port[0x8]; 7630 u8 reserved_at_10[0x10]; 7631 7632 u8 max_mtu[0x10]; 7633 u8 reserved_at_30[0x10]; 7634 7635 u8 admin_mtu[0x10]; 7636 u8 reserved_at_50[0x10]; 7637 7638 u8 oper_mtu[0x10]; 7639 u8 reserved_at_70[0x10]; 7640 }; 7641 7642 struct mlx5_ifc_pmpr_reg_bits { 7643 u8 reserved_at_0[0x8]; 7644 u8 module[0x8]; 7645 u8 reserved_at_10[0x10]; 7646 7647 u8 reserved_at_20[0x18]; 7648 u8 attenuation_5g[0x8]; 7649 7650 u8 reserved_at_40[0x18]; 7651 u8 attenuation_7g[0x8]; 7652 7653 u8 reserved_at_60[0x18]; 7654 u8 attenuation_12g[0x8]; 7655 }; 7656 7657 struct mlx5_ifc_pmpe_reg_bits { 7658 u8 reserved_at_0[0x8]; 7659 u8 module[0x8]; 7660 u8 reserved_at_10[0xc]; 7661 u8 module_status[0x4]; 7662 7663 u8 reserved_at_20[0x60]; 7664 }; 7665 7666 struct mlx5_ifc_pmpc_reg_bits { 7667 u8 module_state_updated[32][0x8]; 7668 }; 7669 7670 struct mlx5_ifc_pmlpn_reg_bits { 7671 u8 reserved_at_0[0x4]; 7672 u8 mlpn_status[0x4]; 7673 u8 local_port[0x8]; 7674 u8 reserved_at_10[0x10]; 7675 7676 u8 e[0x1]; 7677 u8 reserved_at_21[0x1f]; 7678 }; 7679 7680 struct mlx5_ifc_pmlp_reg_bits { 7681 u8 rxtx[0x1]; 7682 u8 reserved_at_1[0x7]; 7683 u8 local_port[0x8]; 7684 u8 reserved_at_10[0x8]; 7685 u8 width[0x8]; 7686 7687 u8 lane0_module_mapping[0x20]; 7688 7689 u8 lane1_module_mapping[0x20]; 7690 7691 u8 lane2_module_mapping[0x20]; 7692 7693 u8 lane3_module_mapping[0x20]; 7694 7695 u8 reserved_at_a0[0x160]; 7696 }; 7697 7698 struct mlx5_ifc_pmaos_reg_bits { 7699 u8 reserved_at_0[0x8]; 7700 u8 module[0x8]; 7701 u8 reserved_at_10[0x4]; 7702 u8 admin_status[0x4]; 7703 u8 reserved_at_18[0x4]; 7704 u8 oper_status[0x4]; 7705 7706 u8 ase[0x1]; 7707 u8 ee[0x1]; 7708 u8 reserved_at_22[0x1c]; 7709 u8 e[0x2]; 7710 7711 u8 reserved_at_40[0x40]; 7712 }; 7713 7714 struct mlx5_ifc_plpc_reg_bits { 7715 u8 reserved_at_0[0x4]; 7716 u8 profile_id[0xc]; 7717 u8 reserved_at_10[0x4]; 7718 u8 proto_mask[0x4]; 7719 u8 reserved_at_18[0x8]; 7720 7721 u8 reserved_at_20[0x10]; 7722 u8 lane_speed[0x10]; 7723 7724 u8 reserved_at_40[0x17]; 7725 u8 lpbf[0x1]; 7726 u8 fec_mode_policy[0x8]; 7727 7728 u8 retransmission_capability[0x8]; 7729 u8 fec_mode_capability[0x18]; 7730 7731 u8 retransmission_support_admin[0x8]; 7732 u8 fec_mode_support_admin[0x18]; 7733 7734 u8 retransmission_request_admin[0x8]; 7735 u8 fec_mode_request_admin[0x18]; 7736 7737 u8 reserved_at_c0[0x80]; 7738 }; 7739 7740 struct mlx5_ifc_plib_reg_bits { 7741 u8 reserved_at_0[0x8]; 7742 u8 local_port[0x8]; 7743 u8 reserved_at_10[0x8]; 7744 u8 ib_port[0x8]; 7745 7746 u8 reserved_at_20[0x60]; 7747 }; 7748 7749 struct mlx5_ifc_plbf_reg_bits { 7750 u8 reserved_at_0[0x8]; 7751 u8 local_port[0x8]; 7752 u8 reserved_at_10[0xd]; 7753 u8 lbf_mode[0x3]; 7754 7755 u8 reserved_at_20[0x20]; 7756 }; 7757 7758 struct mlx5_ifc_pipg_reg_bits { 7759 u8 reserved_at_0[0x8]; 7760 u8 local_port[0x8]; 7761 u8 reserved_at_10[0x10]; 7762 7763 u8 dic[0x1]; 7764 u8 reserved_at_21[0x19]; 7765 u8 ipg[0x4]; 7766 u8 reserved_at_3e[0x2]; 7767 }; 7768 7769 struct mlx5_ifc_pifr_reg_bits { 7770 u8 reserved_at_0[0x8]; 7771 u8 local_port[0x8]; 7772 u8 reserved_at_10[0x10]; 7773 7774 u8 reserved_at_20[0xe0]; 7775 7776 u8 port_filter[8][0x20]; 7777 7778 u8 port_filter_update_en[8][0x20]; 7779 }; 7780 7781 struct mlx5_ifc_pfcc_reg_bits { 7782 u8 reserved_at_0[0x8]; 7783 u8 local_port[0x8]; 7784 u8 reserved_at_10[0x10]; 7785 7786 u8 ppan[0x4]; 7787 u8 reserved_at_24[0x4]; 7788 u8 prio_mask_tx[0x8]; 7789 u8 reserved_at_30[0x8]; 7790 u8 prio_mask_rx[0x8]; 7791 7792 u8 pptx[0x1]; 7793 u8 aptx[0x1]; 7794 u8 reserved_at_42[0x6]; 7795 u8 pfctx[0x8]; 7796 u8 reserved_at_50[0x10]; 7797 7798 u8 pprx[0x1]; 7799 u8 aprx[0x1]; 7800 u8 reserved_at_62[0x6]; 7801 u8 pfcrx[0x8]; 7802 u8 reserved_at_70[0x10]; 7803 7804 u8 reserved_at_80[0x80]; 7805 }; 7806 7807 struct mlx5_ifc_pelc_reg_bits { 7808 u8 op[0x4]; 7809 u8 reserved_at_4[0x4]; 7810 u8 local_port[0x8]; 7811 u8 reserved_at_10[0x10]; 7812 7813 u8 op_admin[0x8]; 7814 u8 op_capability[0x8]; 7815 u8 op_request[0x8]; 7816 u8 op_active[0x8]; 7817 7818 u8 admin[0x40]; 7819 7820 u8 capability[0x40]; 7821 7822 u8 request[0x40]; 7823 7824 u8 active[0x40]; 7825 7826 u8 reserved_at_140[0x80]; 7827 }; 7828 7829 struct mlx5_ifc_peir_reg_bits { 7830 u8 reserved_at_0[0x8]; 7831 u8 local_port[0x8]; 7832 u8 reserved_at_10[0x10]; 7833 7834 u8 reserved_at_20[0xc]; 7835 u8 error_count[0x4]; 7836 u8 reserved_at_30[0x10]; 7837 7838 u8 reserved_at_40[0xc]; 7839 u8 lane[0x4]; 7840 u8 reserved_at_50[0x8]; 7841 u8 error_type[0x8]; 7842 }; 7843 7844 struct mlx5_ifc_pcam_enhanced_features_bits { 7845 u8 reserved_at_0[0x7b]; 7846 7847 u8 rx_buffer_fullness_counters[0x1]; 7848 u8 ptys_connector_type[0x1]; 7849 u8 reserved_at_7d[0x1]; 7850 u8 ppcnt_discard_group[0x1]; 7851 u8 ppcnt_statistical_group[0x1]; 7852 }; 7853 7854 struct mlx5_ifc_pcam_reg_bits { 7855 u8 reserved_at_0[0x8]; 7856 u8 feature_group[0x8]; 7857 u8 reserved_at_10[0x8]; 7858 u8 access_reg_group[0x8]; 7859 7860 u8 reserved_at_20[0x20]; 7861 7862 union { 7863 u8 reserved_at_0[0x80]; 7864 } port_access_reg_cap_mask; 7865 7866 u8 reserved_at_c0[0x80]; 7867 7868 union { 7869 struct mlx5_ifc_pcam_enhanced_features_bits enhanced_features; 7870 u8 reserved_at_0[0x80]; 7871 } feature_cap_mask; 7872 7873 u8 reserved_at_1c0[0xc0]; 7874 }; 7875 7876 struct mlx5_ifc_mcam_enhanced_features_bits { 7877 u8 reserved_at_0[0x7b]; 7878 u8 pcie_outbound_stalled[0x1]; 7879 u8 tx_overflow_buffer_pkt[0x1]; 7880 u8 mtpps_enh_out_per_adj[0x1]; 7881 u8 mtpps_fs[0x1]; 7882 u8 pcie_performance_group[0x1]; 7883 }; 7884 7885 struct mlx5_ifc_mcam_access_reg_bits { 7886 u8 reserved_at_0[0x1c]; 7887 u8 mcda[0x1]; 7888 u8 mcc[0x1]; 7889 u8 mcqi[0x1]; 7890 u8 reserved_at_1f[0x1]; 7891 7892 u8 regs_95_to_64[0x20]; 7893 u8 regs_63_to_32[0x20]; 7894 u8 regs_31_to_0[0x20]; 7895 }; 7896 7897 struct mlx5_ifc_mcam_reg_bits { 7898 u8 reserved_at_0[0x8]; 7899 u8 feature_group[0x8]; 7900 u8 reserved_at_10[0x8]; 7901 u8 access_reg_group[0x8]; 7902 7903 u8 reserved_at_20[0x20]; 7904 7905 union { 7906 struct mlx5_ifc_mcam_access_reg_bits access_regs; 7907 u8 reserved_at_0[0x80]; 7908 } mng_access_reg_cap_mask; 7909 7910 u8 reserved_at_c0[0x80]; 7911 7912 union { 7913 struct mlx5_ifc_mcam_enhanced_features_bits enhanced_features; 7914 u8 reserved_at_0[0x80]; 7915 } mng_feature_cap_mask; 7916 7917 u8 reserved_at_1c0[0x80]; 7918 }; 7919 7920 struct mlx5_ifc_qcam_access_reg_cap_mask { 7921 u8 qcam_access_reg_cap_mask_127_to_20[0x6C]; 7922 u8 qpdpm[0x1]; 7923 u8 qcam_access_reg_cap_mask_18_to_4[0x0F]; 7924 u8 qdpm[0x1]; 7925 u8 qpts[0x1]; 7926 u8 qcap[0x1]; 7927 u8 qcam_access_reg_cap_mask_0[0x1]; 7928 }; 7929 7930 struct mlx5_ifc_qcam_qos_feature_cap_mask { 7931 u8 qcam_qos_feature_cap_mask_127_to_1[0x7F]; 7932 u8 qpts_trust_both[0x1]; 7933 }; 7934 7935 struct mlx5_ifc_qcam_reg_bits { 7936 u8 reserved_at_0[0x8]; 7937 u8 feature_group[0x8]; 7938 u8 reserved_at_10[0x8]; 7939 u8 access_reg_group[0x8]; 7940 u8 reserved_at_20[0x20]; 7941 7942 union { 7943 struct mlx5_ifc_qcam_access_reg_cap_mask reg_cap; 7944 u8 reserved_at_0[0x80]; 7945 } qos_access_reg_cap_mask; 7946 7947 u8 reserved_at_c0[0x80]; 7948 7949 union { 7950 struct mlx5_ifc_qcam_qos_feature_cap_mask feature_cap; 7951 u8 reserved_at_0[0x80]; 7952 } qos_feature_cap_mask; 7953 7954 u8 reserved_at_1c0[0x80]; 7955 }; 7956 7957 struct mlx5_ifc_pcap_reg_bits { 7958 u8 reserved_at_0[0x8]; 7959 u8 local_port[0x8]; 7960 u8 reserved_at_10[0x10]; 7961 7962 u8 port_capability_mask[4][0x20]; 7963 }; 7964 7965 struct mlx5_ifc_paos_reg_bits { 7966 u8 swid[0x8]; 7967 u8 local_port[0x8]; 7968 u8 reserved_at_10[0x4]; 7969 u8 admin_status[0x4]; 7970 u8 reserved_at_18[0x4]; 7971 u8 oper_status[0x4]; 7972 7973 u8 ase[0x1]; 7974 u8 ee[0x1]; 7975 u8 reserved_at_22[0x1c]; 7976 u8 e[0x2]; 7977 7978 u8 reserved_at_40[0x40]; 7979 }; 7980 7981 struct mlx5_ifc_pamp_reg_bits { 7982 u8 reserved_at_0[0x8]; 7983 u8 opamp_group[0x8]; 7984 u8 reserved_at_10[0xc]; 7985 u8 opamp_group_type[0x4]; 7986 7987 u8 start_index[0x10]; 7988 u8 reserved_at_30[0x4]; 7989 u8 num_of_indices[0xc]; 7990 7991 u8 index_data[18][0x10]; 7992 }; 7993 7994 struct mlx5_ifc_pcmr_reg_bits { 7995 u8 reserved_at_0[0x8]; 7996 u8 local_port[0x8]; 7997 u8 reserved_at_10[0x2e]; 7998 u8 fcs_cap[0x1]; 7999 u8 reserved_at_3f[0x1f]; 8000 u8 fcs_chk[0x1]; 8001 u8 reserved_at_5f[0x1]; 8002 }; 8003 8004 struct mlx5_ifc_lane_2_module_mapping_bits { 8005 u8 reserved_at_0[0x6]; 8006 u8 rx_lane[0x2]; 8007 u8 reserved_at_8[0x6]; 8008 u8 tx_lane[0x2]; 8009 u8 reserved_at_10[0x8]; 8010 u8 module[0x8]; 8011 }; 8012 8013 struct mlx5_ifc_bufferx_reg_bits { 8014 u8 reserved_at_0[0x6]; 8015 u8 lossy[0x1]; 8016 u8 epsb[0x1]; 8017 u8 reserved_at_8[0xc]; 8018 u8 size[0xc]; 8019 8020 u8 xoff_threshold[0x10]; 8021 u8 xon_threshold[0x10]; 8022 }; 8023 8024 struct mlx5_ifc_set_node_in_bits { 8025 u8 node_description[64][0x8]; 8026 }; 8027 8028 struct mlx5_ifc_register_power_settings_bits { 8029 u8 reserved_at_0[0x18]; 8030 u8 power_settings_level[0x8]; 8031 8032 u8 reserved_at_20[0x60]; 8033 }; 8034 8035 struct mlx5_ifc_register_host_endianness_bits { 8036 u8 he[0x1]; 8037 u8 reserved_at_1[0x1f]; 8038 8039 u8 reserved_at_20[0x60]; 8040 }; 8041 8042 struct mlx5_ifc_umr_pointer_desc_argument_bits { 8043 u8 reserved_at_0[0x20]; 8044 8045 u8 mkey[0x20]; 8046 8047 u8 addressh_63_32[0x20]; 8048 8049 u8 addressl_31_0[0x20]; 8050 }; 8051 8052 struct mlx5_ifc_ud_adrs_vector_bits { 8053 u8 dc_key[0x40]; 8054 8055 u8 ext[0x1]; 8056 u8 reserved_at_41[0x7]; 8057 u8 destination_qp_dct[0x18]; 8058 8059 u8 static_rate[0x4]; 8060 u8 sl_eth_prio[0x4]; 8061 u8 fl[0x1]; 8062 u8 mlid[0x7]; 8063 u8 rlid_udp_sport[0x10]; 8064 8065 u8 reserved_at_80[0x20]; 8066 8067 u8 rmac_47_16[0x20]; 8068 8069 u8 rmac_15_0[0x10]; 8070 u8 tclass[0x8]; 8071 u8 hop_limit[0x8]; 8072 8073 u8 reserved_at_e0[0x1]; 8074 u8 grh[0x1]; 8075 u8 reserved_at_e2[0x2]; 8076 u8 src_addr_index[0x8]; 8077 u8 flow_label[0x14]; 8078 8079 u8 rgid_rip[16][0x8]; 8080 }; 8081 8082 struct mlx5_ifc_pages_req_event_bits { 8083 u8 reserved_at_0[0x10]; 8084 u8 function_id[0x10]; 8085 8086 u8 num_pages[0x20]; 8087 8088 u8 reserved_at_40[0xa0]; 8089 }; 8090 8091 struct mlx5_ifc_eqe_bits { 8092 u8 reserved_at_0[0x8]; 8093 u8 event_type[0x8]; 8094 u8 reserved_at_10[0x8]; 8095 u8 event_sub_type[0x8]; 8096 8097 u8 reserved_at_20[0xe0]; 8098 8099 union mlx5_ifc_event_auto_bits event_data; 8100 8101 u8 reserved_at_1e0[0x10]; 8102 u8 signature[0x8]; 8103 u8 reserved_at_1f8[0x7]; 8104 u8 owner[0x1]; 8105 }; 8106 8107 enum { 8108 MLX5_CMD_QUEUE_ENTRY_TYPE_PCIE_CMD_IF_TRANSPORT = 0x7, 8109 }; 8110 8111 struct mlx5_ifc_cmd_queue_entry_bits { 8112 u8 type[0x8]; 8113 u8 reserved_at_8[0x18]; 8114 8115 u8 input_length[0x20]; 8116 8117 u8 input_mailbox_pointer_63_32[0x20]; 8118 8119 u8 input_mailbox_pointer_31_9[0x17]; 8120 u8 reserved_at_77[0x9]; 8121 8122 u8 command_input_inline_data[16][0x8]; 8123 8124 u8 command_output_inline_data[16][0x8]; 8125 8126 u8 output_mailbox_pointer_63_32[0x20]; 8127 8128 u8 output_mailbox_pointer_31_9[0x17]; 8129 u8 reserved_at_1b7[0x9]; 8130 8131 u8 output_length[0x20]; 8132 8133 u8 token[0x8]; 8134 u8 signature[0x8]; 8135 u8 reserved_at_1f0[0x8]; 8136 u8 status[0x7]; 8137 u8 ownership[0x1]; 8138 }; 8139 8140 struct mlx5_ifc_cmd_out_bits { 8141 u8 status[0x8]; 8142 u8 reserved_at_8[0x18]; 8143 8144 u8 syndrome[0x20]; 8145 8146 u8 command_output[0x20]; 8147 }; 8148 8149 struct mlx5_ifc_cmd_in_bits { 8150 u8 opcode[0x10]; 8151 u8 reserved_at_10[0x10]; 8152 8153 u8 reserved_at_20[0x10]; 8154 u8 op_mod[0x10]; 8155 8156 u8 command[0][0x20]; 8157 }; 8158 8159 struct mlx5_ifc_cmd_if_box_bits { 8160 u8 mailbox_data[512][0x8]; 8161 8162 u8 reserved_at_1000[0x180]; 8163 8164 u8 next_pointer_63_32[0x20]; 8165 8166 u8 next_pointer_31_10[0x16]; 8167 u8 reserved_at_11b6[0xa]; 8168 8169 u8 block_number[0x20]; 8170 8171 u8 reserved_at_11e0[0x8]; 8172 u8 token[0x8]; 8173 u8 ctrl_signature[0x8]; 8174 u8 signature[0x8]; 8175 }; 8176 8177 struct mlx5_ifc_mtt_bits { 8178 u8 ptag_63_32[0x20]; 8179 8180 u8 ptag_31_8[0x18]; 8181 u8 reserved_at_38[0x6]; 8182 u8 wr_en[0x1]; 8183 u8 rd_en[0x1]; 8184 }; 8185 8186 struct mlx5_ifc_query_wol_rol_out_bits { 8187 u8 status[0x8]; 8188 u8 reserved_at_8[0x18]; 8189 8190 u8 syndrome[0x20]; 8191 8192 u8 reserved_at_40[0x10]; 8193 u8 rol_mode[0x8]; 8194 u8 wol_mode[0x8]; 8195 8196 u8 reserved_at_60[0x20]; 8197 }; 8198 8199 struct mlx5_ifc_query_wol_rol_in_bits { 8200 u8 opcode[0x10]; 8201 u8 reserved_at_10[0x10]; 8202 8203 u8 reserved_at_20[0x10]; 8204 u8 op_mod[0x10]; 8205 8206 u8 reserved_at_40[0x40]; 8207 }; 8208 8209 struct mlx5_ifc_set_wol_rol_out_bits { 8210 u8 status[0x8]; 8211 u8 reserved_at_8[0x18]; 8212 8213 u8 syndrome[0x20]; 8214 8215 u8 reserved_at_40[0x40]; 8216 }; 8217 8218 struct mlx5_ifc_set_wol_rol_in_bits { 8219 u8 opcode[0x10]; 8220 u8 reserved_at_10[0x10]; 8221 8222 u8 reserved_at_20[0x10]; 8223 u8 op_mod[0x10]; 8224 8225 u8 rol_mode_valid[0x1]; 8226 u8 wol_mode_valid[0x1]; 8227 u8 reserved_at_42[0xe]; 8228 u8 rol_mode[0x8]; 8229 u8 wol_mode[0x8]; 8230 8231 u8 reserved_at_60[0x20]; 8232 }; 8233 8234 enum { 8235 MLX5_INITIAL_SEG_NIC_INTERFACE_FULL_DRIVER = 0x0, 8236 MLX5_INITIAL_SEG_NIC_INTERFACE_DISABLED = 0x1, 8237 MLX5_INITIAL_SEG_NIC_INTERFACE_NO_DRAM_NIC = 0x2, 8238 }; 8239 8240 enum { 8241 MLX5_INITIAL_SEG_NIC_INTERFACE_SUPPORTED_FULL_DRIVER = 0x0, 8242 MLX5_INITIAL_SEG_NIC_INTERFACE_SUPPORTED_DISABLED = 0x1, 8243 MLX5_INITIAL_SEG_NIC_INTERFACE_SUPPORTED_NO_DRAM_NIC = 0x2, 8244 }; 8245 8246 enum { 8247 MLX5_INITIAL_SEG_HEALTH_SYNDROME_FW_INTERNAL_ERR = 0x1, 8248 MLX5_INITIAL_SEG_HEALTH_SYNDROME_DEAD_IRISC = 0x7, 8249 MLX5_INITIAL_SEG_HEALTH_SYNDROME_HW_FATAL_ERR = 0x8, 8250 MLX5_INITIAL_SEG_HEALTH_SYNDROME_FW_CRC_ERR = 0x9, 8251 MLX5_INITIAL_SEG_HEALTH_SYNDROME_ICM_FETCH_PCI_ERR = 0xa, 8252 MLX5_INITIAL_SEG_HEALTH_SYNDROME_ICM_PAGE_ERR = 0xb, 8253 MLX5_INITIAL_SEG_HEALTH_SYNDROME_ASYNCHRONOUS_EQ_BUF_OVERRUN = 0xc, 8254 MLX5_INITIAL_SEG_HEALTH_SYNDROME_EQ_IN_ERR = 0xd, 8255 MLX5_INITIAL_SEG_HEALTH_SYNDROME_EQ_INV = 0xe, 8256 MLX5_INITIAL_SEG_HEALTH_SYNDROME_FFSER_ERR = 0xf, 8257 MLX5_INITIAL_SEG_HEALTH_SYNDROME_HIGH_TEMP_ERR = 0x10, 8258 }; 8259 8260 struct mlx5_ifc_initial_seg_bits { 8261 u8 fw_rev_minor[0x10]; 8262 u8 fw_rev_major[0x10]; 8263 8264 u8 cmd_interface_rev[0x10]; 8265 u8 fw_rev_subminor[0x10]; 8266 8267 u8 reserved_at_40[0x40]; 8268 8269 u8 cmdq_phy_addr_63_32[0x20]; 8270 8271 u8 cmdq_phy_addr_31_12[0x14]; 8272 u8 reserved_at_b4[0x2]; 8273 u8 nic_interface[0x2]; 8274 u8 log_cmdq_size[0x4]; 8275 u8 log_cmdq_stride[0x4]; 8276 8277 u8 command_doorbell_vector[0x20]; 8278 8279 u8 reserved_at_e0[0xf00]; 8280 8281 u8 initializing[0x1]; 8282 u8 reserved_at_fe1[0x4]; 8283 u8 nic_interface_supported[0x3]; 8284 u8 reserved_at_fe8[0x18]; 8285 8286 struct mlx5_ifc_health_buffer_bits health_buffer; 8287 8288 u8 no_dram_nic_offset[0x20]; 8289 8290 u8 reserved_at_1220[0x6e40]; 8291 8292 u8 reserved_at_8060[0x1f]; 8293 u8 clear_int[0x1]; 8294 8295 u8 health_syndrome[0x8]; 8296 u8 health_counter[0x18]; 8297 8298 u8 reserved_at_80a0[0x17fc0]; 8299 }; 8300 8301 struct mlx5_ifc_mtpps_reg_bits { 8302 u8 reserved_at_0[0xc]; 8303 u8 cap_number_of_pps_pins[0x4]; 8304 u8 reserved_at_10[0x4]; 8305 u8 cap_max_num_of_pps_in_pins[0x4]; 8306 u8 reserved_at_18[0x4]; 8307 u8 cap_max_num_of_pps_out_pins[0x4]; 8308 8309 u8 reserved_at_20[0x24]; 8310 u8 cap_pin_3_mode[0x4]; 8311 u8 reserved_at_48[0x4]; 8312 u8 cap_pin_2_mode[0x4]; 8313 u8 reserved_at_50[0x4]; 8314 u8 cap_pin_1_mode[0x4]; 8315 u8 reserved_at_58[0x4]; 8316 u8 cap_pin_0_mode[0x4]; 8317 8318 u8 reserved_at_60[0x4]; 8319 u8 cap_pin_7_mode[0x4]; 8320 u8 reserved_at_68[0x4]; 8321 u8 cap_pin_6_mode[0x4]; 8322 u8 reserved_at_70[0x4]; 8323 u8 cap_pin_5_mode[0x4]; 8324 u8 reserved_at_78[0x4]; 8325 u8 cap_pin_4_mode[0x4]; 8326 8327 u8 field_select[0x20]; 8328 u8 reserved_at_a0[0x60]; 8329 8330 u8 enable[0x1]; 8331 u8 reserved_at_101[0xb]; 8332 u8 pattern[0x4]; 8333 u8 reserved_at_110[0x4]; 8334 u8 pin_mode[0x4]; 8335 u8 pin[0x8]; 8336 8337 u8 reserved_at_120[0x20]; 8338 8339 u8 time_stamp[0x40]; 8340 8341 u8 out_pulse_duration[0x10]; 8342 u8 out_periodic_adjustment[0x10]; 8343 u8 enhanced_out_periodic_adjustment[0x20]; 8344 8345 u8 reserved_at_1c0[0x20]; 8346 }; 8347 8348 struct mlx5_ifc_mtppse_reg_bits { 8349 u8 reserved_at_0[0x18]; 8350 u8 pin[0x8]; 8351 u8 event_arm[0x1]; 8352 u8 reserved_at_21[0x1b]; 8353 u8 event_generation_mode[0x4]; 8354 u8 reserved_at_40[0x40]; 8355 }; 8356 8357 struct mlx5_ifc_mcqi_cap_bits { 8358 u8 supported_info_bitmask[0x20]; 8359 8360 u8 component_size[0x20]; 8361 8362 u8 max_component_size[0x20]; 8363 8364 u8 log_mcda_word_size[0x4]; 8365 u8 reserved_at_64[0xc]; 8366 u8 mcda_max_write_size[0x10]; 8367 8368 u8 rd_en[0x1]; 8369 u8 reserved_at_81[0x1]; 8370 u8 match_chip_id[0x1]; 8371 u8 match_psid[0x1]; 8372 u8 check_user_timestamp[0x1]; 8373 u8 match_base_guid_mac[0x1]; 8374 u8 reserved_at_86[0x1a]; 8375 }; 8376 8377 struct mlx5_ifc_mcqi_reg_bits { 8378 u8 read_pending_component[0x1]; 8379 u8 reserved_at_1[0xf]; 8380 u8 component_index[0x10]; 8381 8382 u8 reserved_at_20[0x20]; 8383 8384 u8 reserved_at_40[0x1b]; 8385 u8 info_type[0x5]; 8386 8387 u8 info_size[0x20]; 8388 8389 u8 offset[0x20]; 8390 8391 u8 reserved_at_a0[0x10]; 8392 u8 data_size[0x10]; 8393 8394 u8 data[0][0x20]; 8395 }; 8396 8397 struct mlx5_ifc_mcc_reg_bits { 8398 u8 reserved_at_0[0x4]; 8399 u8 time_elapsed_since_last_cmd[0xc]; 8400 u8 reserved_at_10[0x8]; 8401 u8 instruction[0x8]; 8402 8403 u8 reserved_at_20[0x10]; 8404 u8 component_index[0x10]; 8405 8406 u8 reserved_at_40[0x8]; 8407 u8 update_handle[0x18]; 8408 8409 u8 handle_owner_type[0x4]; 8410 u8 handle_owner_host_id[0x4]; 8411 u8 reserved_at_68[0x1]; 8412 u8 control_progress[0x7]; 8413 u8 error_code[0x8]; 8414 u8 reserved_at_78[0x4]; 8415 u8 control_state[0x4]; 8416 8417 u8 component_size[0x20]; 8418 8419 u8 reserved_at_a0[0x60]; 8420 }; 8421 8422 struct mlx5_ifc_mcda_reg_bits { 8423 u8 reserved_at_0[0x8]; 8424 u8 update_handle[0x18]; 8425 8426 u8 offset[0x20]; 8427 8428 u8 reserved_at_40[0x10]; 8429 u8 size[0x10]; 8430 8431 u8 reserved_at_60[0x20]; 8432 8433 u8 data[0][0x20]; 8434 }; 8435 8436 union mlx5_ifc_ports_control_registers_document_bits { 8437 struct mlx5_ifc_bufferx_reg_bits bufferx_reg; 8438 struct mlx5_ifc_eth_2819_cntrs_grp_data_layout_bits eth_2819_cntrs_grp_data_layout; 8439 struct mlx5_ifc_eth_2863_cntrs_grp_data_layout_bits eth_2863_cntrs_grp_data_layout; 8440 struct mlx5_ifc_eth_3635_cntrs_grp_data_layout_bits eth_3635_cntrs_grp_data_layout; 8441 struct mlx5_ifc_eth_802_3_cntrs_grp_data_layout_bits eth_802_3_cntrs_grp_data_layout; 8442 struct mlx5_ifc_eth_extended_cntrs_grp_data_layout_bits eth_extended_cntrs_grp_data_layout; 8443 struct mlx5_ifc_eth_per_prio_grp_data_layout_bits eth_per_prio_grp_data_layout; 8444 struct mlx5_ifc_eth_per_traffic_grp_data_layout_bits eth_per_traffic_grp_data_layout; 8445 struct mlx5_ifc_lane_2_module_mapping_bits lane_2_module_mapping; 8446 struct mlx5_ifc_pamp_reg_bits pamp_reg; 8447 struct mlx5_ifc_paos_reg_bits paos_reg; 8448 struct mlx5_ifc_pcap_reg_bits pcap_reg; 8449 struct mlx5_ifc_peir_reg_bits peir_reg; 8450 struct mlx5_ifc_pelc_reg_bits pelc_reg; 8451 struct mlx5_ifc_pfcc_reg_bits pfcc_reg; 8452 struct mlx5_ifc_ib_port_cntrs_grp_data_layout_bits ib_port_cntrs_grp_data_layout; 8453 struct mlx5_ifc_phys_layer_cntrs_bits phys_layer_cntrs; 8454 struct mlx5_ifc_pifr_reg_bits pifr_reg; 8455 struct mlx5_ifc_pipg_reg_bits pipg_reg; 8456 struct mlx5_ifc_plbf_reg_bits plbf_reg; 8457 struct mlx5_ifc_plib_reg_bits plib_reg; 8458 struct mlx5_ifc_plpc_reg_bits plpc_reg; 8459 struct mlx5_ifc_pmaos_reg_bits pmaos_reg; 8460 struct mlx5_ifc_pmlp_reg_bits pmlp_reg; 8461 struct mlx5_ifc_pmlpn_reg_bits pmlpn_reg; 8462 struct mlx5_ifc_pmpc_reg_bits pmpc_reg; 8463 struct mlx5_ifc_pmpe_reg_bits pmpe_reg; 8464 struct mlx5_ifc_pmpr_reg_bits pmpr_reg; 8465 struct mlx5_ifc_pmtu_reg_bits pmtu_reg; 8466 struct mlx5_ifc_ppad_reg_bits ppad_reg; 8467 struct mlx5_ifc_ppcnt_reg_bits ppcnt_reg; 8468 struct mlx5_ifc_mpcnt_reg_bits mpcnt_reg; 8469 struct mlx5_ifc_pplm_reg_bits pplm_reg; 8470 struct mlx5_ifc_pplr_reg_bits pplr_reg; 8471 struct mlx5_ifc_ppsc_reg_bits ppsc_reg; 8472 struct mlx5_ifc_pqdr_reg_bits pqdr_reg; 8473 struct mlx5_ifc_pspa_reg_bits pspa_reg; 8474 struct mlx5_ifc_ptas_reg_bits ptas_reg; 8475 struct mlx5_ifc_ptys_reg_bits ptys_reg; 8476 struct mlx5_ifc_mlcr_reg_bits mlcr_reg; 8477 struct mlx5_ifc_pude_reg_bits pude_reg; 8478 struct mlx5_ifc_pvlc_reg_bits pvlc_reg; 8479 struct mlx5_ifc_slrg_reg_bits slrg_reg; 8480 struct mlx5_ifc_sltp_reg_bits sltp_reg; 8481 struct mlx5_ifc_mtpps_reg_bits mtpps_reg; 8482 struct mlx5_ifc_mtppse_reg_bits mtppse_reg; 8483 struct mlx5_ifc_fpga_access_reg_bits fpga_access_reg; 8484 struct mlx5_ifc_fpga_ctrl_bits fpga_ctrl_bits; 8485 struct mlx5_ifc_fpga_cap_bits fpga_cap_bits; 8486 struct mlx5_ifc_mcqi_reg_bits mcqi_reg; 8487 struct mlx5_ifc_mcc_reg_bits mcc_reg; 8488 struct mlx5_ifc_mcda_reg_bits mcda_reg; 8489 u8 reserved_at_0[0x60e0]; 8490 }; 8491 8492 union mlx5_ifc_debug_enhancements_document_bits { 8493 struct mlx5_ifc_health_buffer_bits health_buffer; 8494 u8 reserved_at_0[0x200]; 8495 }; 8496 8497 union mlx5_ifc_uplink_pci_interface_document_bits { 8498 struct mlx5_ifc_initial_seg_bits initial_seg; 8499 u8 reserved_at_0[0x20060]; 8500 }; 8501 8502 struct mlx5_ifc_set_flow_table_root_out_bits { 8503 u8 status[0x8]; 8504 u8 reserved_at_8[0x18]; 8505 8506 u8 syndrome[0x20]; 8507 8508 u8 reserved_at_40[0x40]; 8509 }; 8510 8511 struct mlx5_ifc_set_flow_table_root_in_bits { 8512 u8 opcode[0x10]; 8513 u8 reserved_at_10[0x10]; 8514 8515 u8 reserved_at_20[0x10]; 8516 u8 op_mod[0x10]; 8517 8518 u8 other_vport[0x1]; 8519 u8 reserved_at_41[0xf]; 8520 u8 vport_number[0x10]; 8521 8522 u8 reserved_at_60[0x20]; 8523 8524 u8 table_type[0x8]; 8525 u8 reserved_at_88[0x18]; 8526 8527 u8 reserved_at_a0[0x8]; 8528 u8 table_id[0x18]; 8529 8530 u8 reserved_at_c0[0x8]; 8531 u8 underlay_qpn[0x18]; 8532 u8 reserved_at_e0[0x120]; 8533 }; 8534 8535 enum { 8536 MLX5_MODIFY_FLOW_TABLE_MISS_TABLE_ID = (1UL << 0), 8537 MLX5_MODIFY_FLOW_TABLE_LAG_NEXT_TABLE_ID = (1UL << 15), 8538 }; 8539 8540 struct mlx5_ifc_modify_flow_table_out_bits { 8541 u8 status[0x8]; 8542 u8 reserved_at_8[0x18]; 8543 8544 u8 syndrome[0x20]; 8545 8546 u8 reserved_at_40[0x40]; 8547 }; 8548 8549 struct mlx5_ifc_modify_flow_table_in_bits { 8550 u8 opcode[0x10]; 8551 u8 reserved_at_10[0x10]; 8552 8553 u8 reserved_at_20[0x10]; 8554 u8 op_mod[0x10]; 8555 8556 u8 other_vport[0x1]; 8557 u8 reserved_at_41[0xf]; 8558 u8 vport_number[0x10]; 8559 8560 u8 reserved_at_60[0x10]; 8561 u8 modify_field_select[0x10]; 8562 8563 u8 table_type[0x8]; 8564 u8 reserved_at_88[0x18]; 8565 8566 u8 reserved_at_a0[0x8]; 8567 u8 table_id[0x18]; 8568 8569 struct mlx5_ifc_flow_table_context_bits flow_table_context; 8570 }; 8571 8572 struct mlx5_ifc_ets_tcn_config_reg_bits { 8573 u8 g[0x1]; 8574 u8 b[0x1]; 8575 u8 r[0x1]; 8576 u8 reserved_at_3[0x9]; 8577 u8 group[0x4]; 8578 u8 reserved_at_10[0x9]; 8579 u8 bw_allocation[0x7]; 8580 8581 u8 reserved_at_20[0xc]; 8582 u8 max_bw_units[0x4]; 8583 u8 reserved_at_30[0x8]; 8584 u8 max_bw_value[0x8]; 8585 }; 8586 8587 struct mlx5_ifc_ets_global_config_reg_bits { 8588 u8 reserved_at_0[0x2]; 8589 u8 r[0x1]; 8590 u8 reserved_at_3[0x1d]; 8591 8592 u8 reserved_at_20[0xc]; 8593 u8 max_bw_units[0x4]; 8594 u8 reserved_at_30[0x8]; 8595 u8 max_bw_value[0x8]; 8596 }; 8597 8598 struct mlx5_ifc_qetc_reg_bits { 8599 u8 reserved_at_0[0x8]; 8600 u8 port_number[0x8]; 8601 u8 reserved_at_10[0x30]; 8602 8603 struct mlx5_ifc_ets_tcn_config_reg_bits tc_configuration[0x8]; 8604 struct mlx5_ifc_ets_global_config_reg_bits global_configuration; 8605 }; 8606 8607 struct mlx5_ifc_qpdpm_dscp_reg_bits { 8608 u8 e[0x1]; 8609 u8 reserved_at_01[0x0b]; 8610 u8 prio[0x04]; 8611 }; 8612 8613 struct mlx5_ifc_qpdpm_reg_bits { 8614 u8 reserved_at_0[0x8]; 8615 u8 local_port[0x8]; 8616 u8 reserved_at_10[0x10]; 8617 struct mlx5_ifc_qpdpm_dscp_reg_bits dscp[64]; 8618 }; 8619 8620 struct mlx5_ifc_qpts_reg_bits { 8621 u8 reserved_at_0[0x8]; 8622 u8 local_port[0x8]; 8623 u8 reserved_at_10[0x2d]; 8624 u8 trust_state[0x3]; 8625 }; 8626 8627 struct mlx5_ifc_qtct_reg_bits { 8628 u8 reserved_at_0[0x8]; 8629 u8 port_number[0x8]; 8630 u8 reserved_at_10[0xd]; 8631 u8 prio[0x3]; 8632 8633 u8 reserved_at_20[0x1d]; 8634 u8 tclass[0x3]; 8635 }; 8636 8637 struct mlx5_ifc_mcia_reg_bits { 8638 u8 l[0x1]; 8639 u8 reserved_at_1[0x7]; 8640 u8 module[0x8]; 8641 u8 reserved_at_10[0x8]; 8642 u8 status[0x8]; 8643 8644 u8 i2c_device_address[0x8]; 8645 u8 page_number[0x8]; 8646 u8 device_address[0x10]; 8647 8648 u8 reserved_at_40[0x10]; 8649 u8 size[0x10]; 8650 8651 u8 reserved_at_60[0x20]; 8652 8653 u8 dword_0[0x20]; 8654 u8 dword_1[0x20]; 8655 u8 dword_2[0x20]; 8656 u8 dword_3[0x20]; 8657 u8 dword_4[0x20]; 8658 u8 dword_5[0x20]; 8659 u8 dword_6[0x20]; 8660 u8 dword_7[0x20]; 8661 u8 dword_8[0x20]; 8662 u8 dword_9[0x20]; 8663 u8 dword_10[0x20]; 8664 u8 dword_11[0x20]; 8665 }; 8666 8667 struct mlx5_ifc_dcbx_param_bits { 8668 u8 dcbx_cee_cap[0x1]; 8669 u8 dcbx_ieee_cap[0x1]; 8670 u8 dcbx_standby_cap[0x1]; 8671 u8 reserved_at_0[0x5]; 8672 u8 port_number[0x8]; 8673 u8 reserved_at_10[0xa]; 8674 u8 max_application_table_size[6]; 8675 u8 reserved_at_20[0x15]; 8676 u8 version_oper[0x3]; 8677 u8 reserved_at_38[5]; 8678 u8 version_admin[0x3]; 8679 u8 willing_admin[0x1]; 8680 u8 reserved_at_41[0x3]; 8681 u8 pfc_cap_oper[0x4]; 8682 u8 reserved_at_48[0x4]; 8683 u8 pfc_cap_admin[0x4]; 8684 u8 reserved_at_50[0x4]; 8685 u8 num_of_tc_oper[0x4]; 8686 u8 reserved_at_58[0x4]; 8687 u8 num_of_tc_admin[0x4]; 8688 u8 remote_willing[0x1]; 8689 u8 reserved_at_61[3]; 8690 u8 remote_pfc_cap[4]; 8691 u8 reserved_at_68[0x14]; 8692 u8 remote_num_of_tc[0x4]; 8693 u8 reserved_at_80[0x18]; 8694 u8 error[0x8]; 8695 u8 reserved_at_a0[0x160]; 8696 }; 8697 8698 struct mlx5_ifc_lagc_bits { 8699 u8 reserved_at_0[0x1d]; 8700 u8 lag_state[0x3]; 8701 8702 u8 reserved_at_20[0x14]; 8703 u8 tx_remap_affinity_2[0x4]; 8704 u8 reserved_at_38[0x4]; 8705 u8 tx_remap_affinity_1[0x4]; 8706 }; 8707 8708 struct mlx5_ifc_create_lag_out_bits { 8709 u8 status[0x8]; 8710 u8 reserved_at_8[0x18]; 8711 8712 u8 syndrome[0x20]; 8713 8714 u8 reserved_at_40[0x40]; 8715 }; 8716 8717 struct mlx5_ifc_create_lag_in_bits { 8718 u8 opcode[0x10]; 8719 u8 reserved_at_10[0x10]; 8720 8721 u8 reserved_at_20[0x10]; 8722 u8 op_mod[0x10]; 8723 8724 struct mlx5_ifc_lagc_bits ctx; 8725 }; 8726 8727 struct mlx5_ifc_modify_lag_out_bits { 8728 u8 status[0x8]; 8729 u8 reserved_at_8[0x18]; 8730 8731 u8 syndrome[0x20]; 8732 8733 u8 reserved_at_40[0x40]; 8734 }; 8735 8736 struct mlx5_ifc_modify_lag_in_bits { 8737 u8 opcode[0x10]; 8738 u8 reserved_at_10[0x10]; 8739 8740 u8 reserved_at_20[0x10]; 8741 u8 op_mod[0x10]; 8742 8743 u8 reserved_at_40[0x20]; 8744 u8 field_select[0x20]; 8745 8746 struct mlx5_ifc_lagc_bits ctx; 8747 }; 8748 8749 struct mlx5_ifc_query_lag_out_bits { 8750 u8 status[0x8]; 8751 u8 reserved_at_8[0x18]; 8752 8753 u8 syndrome[0x20]; 8754 8755 u8 reserved_at_40[0x40]; 8756 8757 struct mlx5_ifc_lagc_bits ctx; 8758 }; 8759 8760 struct mlx5_ifc_query_lag_in_bits { 8761 u8 opcode[0x10]; 8762 u8 reserved_at_10[0x10]; 8763 8764 u8 reserved_at_20[0x10]; 8765 u8 op_mod[0x10]; 8766 8767 u8 reserved_at_40[0x40]; 8768 }; 8769 8770 struct mlx5_ifc_destroy_lag_out_bits { 8771 u8 status[0x8]; 8772 u8 reserved_at_8[0x18]; 8773 8774 u8 syndrome[0x20]; 8775 8776 u8 reserved_at_40[0x40]; 8777 }; 8778 8779 struct mlx5_ifc_destroy_lag_in_bits { 8780 u8 opcode[0x10]; 8781 u8 reserved_at_10[0x10]; 8782 8783 u8 reserved_at_20[0x10]; 8784 u8 op_mod[0x10]; 8785 8786 u8 reserved_at_40[0x40]; 8787 }; 8788 8789 struct mlx5_ifc_create_vport_lag_out_bits { 8790 u8 status[0x8]; 8791 u8 reserved_at_8[0x18]; 8792 8793 u8 syndrome[0x20]; 8794 8795 u8 reserved_at_40[0x40]; 8796 }; 8797 8798 struct mlx5_ifc_create_vport_lag_in_bits { 8799 u8 opcode[0x10]; 8800 u8 reserved_at_10[0x10]; 8801 8802 u8 reserved_at_20[0x10]; 8803 u8 op_mod[0x10]; 8804 8805 u8 reserved_at_40[0x40]; 8806 }; 8807 8808 struct mlx5_ifc_destroy_vport_lag_out_bits { 8809 u8 status[0x8]; 8810 u8 reserved_at_8[0x18]; 8811 8812 u8 syndrome[0x20]; 8813 8814 u8 reserved_at_40[0x40]; 8815 }; 8816 8817 struct mlx5_ifc_destroy_vport_lag_in_bits { 8818 u8 opcode[0x10]; 8819 u8 reserved_at_10[0x10]; 8820 8821 u8 reserved_at_20[0x10]; 8822 u8 op_mod[0x10]; 8823 8824 u8 reserved_at_40[0x40]; 8825 }; 8826 8827 #endif /* MLX5_IFC_H */ 8828