1 /* 2 * Copyright (c) 2013-2015, Mellanox Technologies, Ltd. All rights reserved. 3 * 4 * This software is available to you under a choice of one of two 5 * licenses. You may choose to be licensed under the terms of the GNU 6 * General Public License (GPL) Version 2, available from the file 7 * COPYING in the main directory of this source tree, or the 8 * OpenIB.org BSD license below: 9 * 10 * Redistribution and use in source and binary forms, with or 11 * without modification, are permitted provided that the following 12 * conditions are met: 13 * 14 * - Redistributions of source code must retain the above 15 * copyright notice, this list of conditions and the following 16 * disclaimer. 17 * 18 * - Redistributions in binary form must reproduce the above 19 * copyright notice, this list of conditions and the following 20 * disclaimer in the documentation and/or other materials 21 * provided with the distribution. 22 * 23 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, 24 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF 25 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND 26 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS 27 * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN 28 * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN 29 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE 30 * SOFTWARE. 31 */ 32 #ifndef MLX5_IFC_H 33 #define MLX5_IFC_H 34 35 #include "mlx5_ifc_fpga.h" 36 37 enum { 38 MLX5_EVENT_TYPE_CODING_COMPLETION_EVENTS = 0x0, 39 MLX5_EVENT_TYPE_CODING_PATH_MIGRATED_SUCCEEDED = 0x1, 40 MLX5_EVENT_TYPE_CODING_COMMUNICATION_ESTABLISHED = 0x2, 41 MLX5_EVENT_TYPE_CODING_SEND_QUEUE_DRAINED = 0x3, 42 MLX5_EVENT_TYPE_CODING_LAST_WQE_REACHED = 0x13, 43 MLX5_EVENT_TYPE_CODING_SRQ_LIMIT = 0x14, 44 MLX5_EVENT_TYPE_CODING_DCT_ALL_CONNECTIONS_CLOSED = 0x1c, 45 MLX5_EVENT_TYPE_CODING_DCT_ACCESS_KEY_VIOLATION = 0x1d, 46 MLX5_EVENT_TYPE_CODING_CQ_ERROR = 0x4, 47 MLX5_EVENT_TYPE_CODING_LOCAL_WQ_CATASTROPHIC_ERROR = 0x5, 48 MLX5_EVENT_TYPE_CODING_PATH_MIGRATION_FAILED = 0x7, 49 MLX5_EVENT_TYPE_CODING_PAGE_FAULT_EVENT = 0xc, 50 MLX5_EVENT_TYPE_CODING_INVALID_REQUEST_LOCAL_WQ_ERROR = 0x10, 51 MLX5_EVENT_TYPE_CODING_LOCAL_ACCESS_VIOLATION_WQ_ERROR = 0x11, 52 MLX5_EVENT_TYPE_CODING_LOCAL_SRQ_CATASTROPHIC_ERROR = 0x12, 53 MLX5_EVENT_TYPE_CODING_INTERNAL_ERROR = 0x8, 54 MLX5_EVENT_TYPE_CODING_PORT_STATE_CHANGE = 0x9, 55 MLX5_EVENT_TYPE_CODING_GPIO_EVENT = 0x15, 56 MLX5_EVENT_TYPE_CODING_REMOTE_CONFIGURATION_PROTOCOL_EVENT = 0x19, 57 MLX5_EVENT_TYPE_CODING_DOORBELL_BLUEFLAME_CONGESTION_EVENT = 0x1a, 58 MLX5_EVENT_TYPE_CODING_STALL_VL_EVENT = 0x1b, 59 MLX5_EVENT_TYPE_CODING_DROPPED_PACKET_LOGGED_EVENT = 0x1f, 60 MLX5_EVENT_TYPE_CODING_COMMAND_INTERFACE_COMPLETION = 0xa, 61 MLX5_EVENT_TYPE_CODING_PAGE_REQUEST = 0xb, 62 MLX5_EVENT_TYPE_CODING_FPGA_ERROR = 0x20, 63 MLX5_EVENT_TYPE_CODING_FPGA_QP_ERROR = 0x21 64 }; 65 66 enum { 67 MLX5_SET_HCA_CAP_OP_MOD_GENERAL_DEVICE = 0x0, 68 MLX5_SET_HCA_CAP_OP_MOD_ETHERNET_OFFLOADS = 0x1, 69 MLX5_SET_HCA_CAP_OP_MOD_ODP = 0x2, 70 MLX5_SET_HCA_CAP_OP_MOD_ATOMIC = 0x3, 71 MLX5_SET_HCA_CAP_OP_MOD_ROCE = 0x4, 72 MLX5_SET_HCA_CAP_OP_MOD_IPSEC = 0x15, 73 MLX5_SET_HCA_CAP_OP_MOD_GENERAL_DEVICE2 = 0x20, 74 MLX5_SET_HCA_CAP_OP_MOD_PORT_SELECTION = 0x25, 75 }; 76 77 enum { 78 MLX5_SHARED_RESOURCE_UID = 0xffff, 79 }; 80 81 enum { 82 MLX5_OBJ_TYPE_SW_ICM = 0x0008, 83 MLX5_OBJ_TYPE_HEADER_MODIFY_ARGUMENT = 0x23, 84 }; 85 86 enum { 87 MLX5_GENERAL_OBJ_TYPES_CAP_SW_ICM = (1ULL << MLX5_OBJ_TYPE_SW_ICM), 88 MLX5_GENERAL_OBJ_TYPES_CAP_GENEVE_TLV_OPT = (1ULL << 11), 89 MLX5_GENERAL_OBJ_TYPES_CAP_VIRTIO_NET_Q = (1ULL << 13), 90 MLX5_GENERAL_OBJ_TYPES_CAP_HEADER_MODIFY_ARGUMENT = 91 (1ULL << MLX5_OBJ_TYPE_HEADER_MODIFY_ARGUMENT), 92 MLX5_GENERAL_OBJ_TYPES_CAP_MACSEC_OFFLOAD = (1ULL << 39), 93 }; 94 95 enum { 96 MLX5_OBJ_TYPE_GENEVE_TLV_OPT = 0x000b, 97 MLX5_OBJ_TYPE_VIRTIO_NET_Q = 0x000d, 98 MLX5_OBJ_TYPE_VIRTIO_Q_COUNTERS = 0x001c, 99 MLX5_OBJ_TYPE_MATCH_DEFINER = 0x0018, 100 MLX5_OBJ_TYPE_PAGE_TRACK = 0x46, 101 MLX5_OBJ_TYPE_MKEY = 0xff01, 102 MLX5_OBJ_TYPE_QP = 0xff02, 103 MLX5_OBJ_TYPE_PSV = 0xff03, 104 MLX5_OBJ_TYPE_RMP = 0xff04, 105 MLX5_OBJ_TYPE_XRC_SRQ = 0xff05, 106 MLX5_OBJ_TYPE_RQ = 0xff06, 107 MLX5_OBJ_TYPE_SQ = 0xff07, 108 MLX5_OBJ_TYPE_TIR = 0xff08, 109 MLX5_OBJ_TYPE_TIS = 0xff09, 110 MLX5_OBJ_TYPE_DCT = 0xff0a, 111 MLX5_OBJ_TYPE_XRQ = 0xff0b, 112 MLX5_OBJ_TYPE_RQT = 0xff0e, 113 MLX5_OBJ_TYPE_FLOW_COUNTER = 0xff0f, 114 MLX5_OBJ_TYPE_CQ = 0xff10, 115 }; 116 117 enum { 118 MLX5_CMD_OP_QUERY_HCA_CAP = 0x100, 119 MLX5_CMD_OP_QUERY_ADAPTER = 0x101, 120 MLX5_CMD_OP_INIT_HCA = 0x102, 121 MLX5_CMD_OP_TEARDOWN_HCA = 0x103, 122 MLX5_CMD_OP_ENABLE_HCA = 0x104, 123 MLX5_CMD_OP_DISABLE_HCA = 0x105, 124 MLX5_CMD_OP_QUERY_PAGES = 0x107, 125 MLX5_CMD_OP_MANAGE_PAGES = 0x108, 126 MLX5_CMD_OP_SET_HCA_CAP = 0x109, 127 MLX5_CMD_OP_QUERY_ISSI = 0x10a, 128 MLX5_CMD_OP_SET_ISSI = 0x10b, 129 MLX5_CMD_OP_SET_DRIVER_VERSION = 0x10d, 130 MLX5_CMD_OP_QUERY_SF_PARTITION = 0x111, 131 MLX5_CMD_OP_ALLOC_SF = 0x113, 132 MLX5_CMD_OP_DEALLOC_SF = 0x114, 133 MLX5_CMD_OP_SUSPEND_VHCA = 0x115, 134 MLX5_CMD_OP_RESUME_VHCA = 0x116, 135 MLX5_CMD_OP_QUERY_VHCA_MIGRATION_STATE = 0x117, 136 MLX5_CMD_OP_SAVE_VHCA_STATE = 0x118, 137 MLX5_CMD_OP_LOAD_VHCA_STATE = 0x119, 138 MLX5_CMD_OP_CREATE_MKEY = 0x200, 139 MLX5_CMD_OP_QUERY_MKEY = 0x201, 140 MLX5_CMD_OP_DESTROY_MKEY = 0x202, 141 MLX5_CMD_OP_QUERY_SPECIAL_CONTEXTS = 0x203, 142 MLX5_CMD_OP_PAGE_FAULT_RESUME = 0x204, 143 MLX5_CMD_OP_ALLOC_MEMIC = 0x205, 144 MLX5_CMD_OP_DEALLOC_MEMIC = 0x206, 145 MLX5_CMD_OP_MODIFY_MEMIC = 0x207, 146 MLX5_CMD_OP_CREATE_EQ = 0x301, 147 MLX5_CMD_OP_DESTROY_EQ = 0x302, 148 MLX5_CMD_OP_QUERY_EQ = 0x303, 149 MLX5_CMD_OP_GEN_EQE = 0x304, 150 MLX5_CMD_OP_CREATE_CQ = 0x400, 151 MLX5_CMD_OP_DESTROY_CQ = 0x401, 152 MLX5_CMD_OP_QUERY_CQ = 0x402, 153 MLX5_CMD_OP_MODIFY_CQ = 0x403, 154 MLX5_CMD_OP_CREATE_QP = 0x500, 155 MLX5_CMD_OP_DESTROY_QP = 0x501, 156 MLX5_CMD_OP_RST2INIT_QP = 0x502, 157 MLX5_CMD_OP_INIT2RTR_QP = 0x503, 158 MLX5_CMD_OP_RTR2RTS_QP = 0x504, 159 MLX5_CMD_OP_RTS2RTS_QP = 0x505, 160 MLX5_CMD_OP_SQERR2RTS_QP = 0x506, 161 MLX5_CMD_OP_2ERR_QP = 0x507, 162 MLX5_CMD_OP_2RST_QP = 0x50a, 163 MLX5_CMD_OP_QUERY_QP = 0x50b, 164 MLX5_CMD_OP_SQD_RTS_QP = 0x50c, 165 MLX5_CMD_OP_INIT2INIT_QP = 0x50e, 166 MLX5_CMD_OP_CREATE_PSV = 0x600, 167 MLX5_CMD_OP_DESTROY_PSV = 0x601, 168 MLX5_CMD_OP_CREATE_SRQ = 0x700, 169 MLX5_CMD_OP_DESTROY_SRQ = 0x701, 170 MLX5_CMD_OP_QUERY_SRQ = 0x702, 171 MLX5_CMD_OP_ARM_RQ = 0x703, 172 MLX5_CMD_OP_CREATE_XRC_SRQ = 0x705, 173 MLX5_CMD_OP_DESTROY_XRC_SRQ = 0x706, 174 MLX5_CMD_OP_QUERY_XRC_SRQ = 0x707, 175 MLX5_CMD_OP_ARM_XRC_SRQ = 0x708, 176 MLX5_CMD_OP_CREATE_DCT = 0x710, 177 MLX5_CMD_OP_DESTROY_DCT = 0x711, 178 MLX5_CMD_OP_DRAIN_DCT = 0x712, 179 MLX5_CMD_OP_QUERY_DCT = 0x713, 180 MLX5_CMD_OP_ARM_DCT_FOR_KEY_VIOLATION = 0x714, 181 MLX5_CMD_OP_CREATE_XRQ = 0x717, 182 MLX5_CMD_OP_DESTROY_XRQ = 0x718, 183 MLX5_CMD_OP_QUERY_XRQ = 0x719, 184 MLX5_CMD_OP_ARM_XRQ = 0x71a, 185 MLX5_CMD_OP_QUERY_XRQ_DC_PARAMS_ENTRY = 0x725, 186 MLX5_CMD_OP_SET_XRQ_DC_PARAMS_ENTRY = 0x726, 187 MLX5_CMD_OP_QUERY_XRQ_ERROR_PARAMS = 0x727, 188 MLX5_CMD_OP_RELEASE_XRQ_ERROR = 0x729, 189 MLX5_CMD_OP_MODIFY_XRQ = 0x72a, 190 MLX5_CMD_OP_QUERY_ESW_FUNCTIONS = 0x740, 191 MLX5_CMD_OP_QUERY_VPORT_STATE = 0x750, 192 MLX5_CMD_OP_MODIFY_VPORT_STATE = 0x751, 193 MLX5_CMD_OP_QUERY_ESW_VPORT_CONTEXT = 0x752, 194 MLX5_CMD_OP_MODIFY_ESW_VPORT_CONTEXT = 0x753, 195 MLX5_CMD_OP_QUERY_NIC_VPORT_CONTEXT = 0x754, 196 MLX5_CMD_OP_MODIFY_NIC_VPORT_CONTEXT = 0x755, 197 MLX5_CMD_OP_QUERY_ROCE_ADDRESS = 0x760, 198 MLX5_CMD_OP_SET_ROCE_ADDRESS = 0x761, 199 MLX5_CMD_OP_QUERY_HCA_VPORT_CONTEXT = 0x762, 200 MLX5_CMD_OP_MODIFY_HCA_VPORT_CONTEXT = 0x763, 201 MLX5_CMD_OP_QUERY_HCA_VPORT_GID = 0x764, 202 MLX5_CMD_OP_QUERY_HCA_VPORT_PKEY = 0x765, 203 MLX5_CMD_OP_QUERY_VNIC_ENV = 0x76f, 204 MLX5_CMD_OP_QUERY_VPORT_COUNTER = 0x770, 205 MLX5_CMD_OP_ALLOC_Q_COUNTER = 0x771, 206 MLX5_CMD_OP_DEALLOC_Q_COUNTER = 0x772, 207 MLX5_CMD_OP_QUERY_Q_COUNTER = 0x773, 208 MLX5_CMD_OP_SET_MONITOR_COUNTER = 0x774, 209 MLX5_CMD_OP_ARM_MONITOR_COUNTER = 0x775, 210 MLX5_CMD_OP_SET_PP_RATE_LIMIT = 0x780, 211 MLX5_CMD_OP_QUERY_RATE_LIMIT = 0x781, 212 MLX5_CMD_OP_CREATE_SCHEDULING_ELEMENT = 0x782, 213 MLX5_CMD_OP_DESTROY_SCHEDULING_ELEMENT = 0x783, 214 MLX5_CMD_OP_QUERY_SCHEDULING_ELEMENT = 0x784, 215 MLX5_CMD_OP_MODIFY_SCHEDULING_ELEMENT = 0x785, 216 MLX5_CMD_OP_CREATE_QOS_PARA_VPORT = 0x786, 217 MLX5_CMD_OP_DESTROY_QOS_PARA_VPORT = 0x787, 218 MLX5_CMD_OP_ALLOC_PD = 0x800, 219 MLX5_CMD_OP_DEALLOC_PD = 0x801, 220 MLX5_CMD_OP_ALLOC_UAR = 0x802, 221 MLX5_CMD_OP_DEALLOC_UAR = 0x803, 222 MLX5_CMD_OP_CONFIG_INT_MODERATION = 0x804, 223 MLX5_CMD_OP_ACCESS_REG = 0x805, 224 MLX5_CMD_OP_ATTACH_TO_MCG = 0x806, 225 MLX5_CMD_OP_DETACH_FROM_MCG = 0x807, 226 MLX5_CMD_OP_GET_DROPPED_PACKET_LOG = 0x80a, 227 MLX5_CMD_OP_MAD_IFC = 0x50d, 228 MLX5_CMD_OP_QUERY_MAD_DEMUX = 0x80b, 229 MLX5_CMD_OP_SET_MAD_DEMUX = 0x80c, 230 MLX5_CMD_OP_NOP = 0x80d, 231 MLX5_CMD_OP_ALLOC_XRCD = 0x80e, 232 MLX5_CMD_OP_DEALLOC_XRCD = 0x80f, 233 MLX5_CMD_OP_ALLOC_TRANSPORT_DOMAIN = 0x816, 234 MLX5_CMD_OP_DEALLOC_TRANSPORT_DOMAIN = 0x817, 235 MLX5_CMD_OP_QUERY_CONG_STATUS = 0x822, 236 MLX5_CMD_OP_MODIFY_CONG_STATUS = 0x823, 237 MLX5_CMD_OP_QUERY_CONG_PARAMS = 0x824, 238 MLX5_CMD_OP_MODIFY_CONG_PARAMS = 0x825, 239 MLX5_CMD_OP_QUERY_CONG_STATISTICS = 0x826, 240 MLX5_CMD_OP_ADD_VXLAN_UDP_DPORT = 0x827, 241 MLX5_CMD_OP_DELETE_VXLAN_UDP_DPORT = 0x828, 242 MLX5_CMD_OP_SET_L2_TABLE_ENTRY = 0x829, 243 MLX5_CMD_OP_QUERY_L2_TABLE_ENTRY = 0x82a, 244 MLX5_CMD_OP_DELETE_L2_TABLE_ENTRY = 0x82b, 245 MLX5_CMD_OP_SET_WOL_ROL = 0x830, 246 MLX5_CMD_OP_QUERY_WOL_ROL = 0x831, 247 MLX5_CMD_OP_CREATE_LAG = 0x840, 248 MLX5_CMD_OP_MODIFY_LAG = 0x841, 249 MLX5_CMD_OP_QUERY_LAG = 0x842, 250 MLX5_CMD_OP_DESTROY_LAG = 0x843, 251 MLX5_CMD_OP_CREATE_VPORT_LAG = 0x844, 252 MLX5_CMD_OP_DESTROY_VPORT_LAG = 0x845, 253 MLX5_CMD_OP_CREATE_TIR = 0x900, 254 MLX5_CMD_OP_MODIFY_TIR = 0x901, 255 MLX5_CMD_OP_DESTROY_TIR = 0x902, 256 MLX5_CMD_OP_QUERY_TIR = 0x903, 257 MLX5_CMD_OP_CREATE_SQ = 0x904, 258 MLX5_CMD_OP_MODIFY_SQ = 0x905, 259 MLX5_CMD_OP_DESTROY_SQ = 0x906, 260 MLX5_CMD_OP_QUERY_SQ = 0x907, 261 MLX5_CMD_OP_CREATE_RQ = 0x908, 262 MLX5_CMD_OP_MODIFY_RQ = 0x909, 263 MLX5_CMD_OP_SET_DELAY_DROP_PARAMS = 0x910, 264 MLX5_CMD_OP_DESTROY_RQ = 0x90a, 265 MLX5_CMD_OP_QUERY_RQ = 0x90b, 266 MLX5_CMD_OP_CREATE_RMP = 0x90c, 267 MLX5_CMD_OP_MODIFY_RMP = 0x90d, 268 MLX5_CMD_OP_DESTROY_RMP = 0x90e, 269 MLX5_CMD_OP_QUERY_RMP = 0x90f, 270 MLX5_CMD_OP_CREATE_TIS = 0x912, 271 MLX5_CMD_OP_MODIFY_TIS = 0x913, 272 MLX5_CMD_OP_DESTROY_TIS = 0x914, 273 MLX5_CMD_OP_QUERY_TIS = 0x915, 274 MLX5_CMD_OP_CREATE_RQT = 0x916, 275 MLX5_CMD_OP_MODIFY_RQT = 0x917, 276 MLX5_CMD_OP_DESTROY_RQT = 0x918, 277 MLX5_CMD_OP_QUERY_RQT = 0x919, 278 MLX5_CMD_OP_SET_FLOW_TABLE_ROOT = 0x92f, 279 MLX5_CMD_OP_CREATE_FLOW_TABLE = 0x930, 280 MLX5_CMD_OP_DESTROY_FLOW_TABLE = 0x931, 281 MLX5_CMD_OP_QUERY_FLOW_TABLE = 0x932, 282 MLX5_CMD_OP_CREATE_FLOW_GROUP = 0x933, 283 MLX5_CMD_OP_DESTROY_FLOW_GROUP = 0x934, 284 MLX5_CMD_OP_QUERY_FLOW_GROUP = 0x935, 285 MLX5_CMD_OP_SET_FLOW_TABLE_ENTRY = 0x936, 286 MLX5_CMD_OP_QUERY_FLOW_TABLE_ENTRY = 0x937, 287 MLX5_CMD_OP_DELETE_FLOW_TABLE_ENTRY = 0x938, 288 MLX5_CMD_OP_ALLOC_FLOW_COUNTER = 0x939, 289 MLX5_CMD_OP_DEALLOC_FLOW_COUNTER = 0x93a, 290 MLX5_CMD_OP_QUERY_FLOW_COUNTER = 0x93b, 291 MLX5_CMD_OP_MODIFY_FLOW_TABLE = 0x93c, 292 MLX5_CMD_OP_ALLOC_PACKET_REFORMAT_CONTEXT = 0x93d, 293 MLX5_CMD_OP_DEALLOC_PACKET_REFORMAT_CONTEXT = 0x93e, 294 MLX5_CMD_OP_QUERY_PACKET_REFORMAT_CONTEXT = 0x93f, 295 MLX5_CMD_OP_ALLOC_MODIFY_HEADER_CONTEXT = 0x940, 296 MLX5_CMD_OP_DEALLOC_MODIFY_HEADER_CONTEXT = 0x941, 297 MLX5_CMD_OP_QUERY_MODIFY_HEADER_CONTEXT = 0x942, 298 MLX5_CMD_OP_FPGA_CREATE_QP = 0x960, 299 MLX5_CMD_OP_FPGA_MODIFY_QP = 0x961, 300 MLX5_CMD_OP_FPGA_QUERY_QP = 0x962, 301 MLX5_CMD_OP_FPGA_DESTROY_QP = 0x963, 302 MLX5_CMD_OP_FPGA_QUERY_QP_COUNTERS = 0x964, 303 MLX5_CMD_OP_CREATE_GENERAL_OBJECT = 0xa00, 304 MLX5_CMD_OP_MODIFY_GENERAL_OBJECT = 0xa01, 305 MLX5_CMD_OP_QUERY_GENERAL_OBJECT = 0xa02, 306 MLX5_CMD_OP_DESTROY_GENERAL_OBJECT = 0xa03, 307 MLX5_CMD_OP_CREATE_UCTX = 0xa04, 308 MLX5_CMD_OP_DESTROY_UCTX = 0xa06, 309 MLX5_CMD_OP_CREATE_UMEM = 0xa08, 310 MLX5_CMD_OP_DESTROY_UMEM = 0xa0a, 311 MLX5_CMD_OP_SYNC_STEERING = 0xb00, 312 MLX5_CMD_OP_QUERY_VHCA_STATE = 0xb0d, 313 MLX5_CMD_OP_MODIFY_VHCA_STATE = 0xb0e, 314 MLX5_CMD_OP_SYNC_CRYPTO = 0xb12, 315 MLX5_CMD_OP_ALLOW_OTHER_VHCA_ACCESS = 0xb16, 316 MLX5_CMD_OP_MAX 317 }; 318 319 /* Valid range for general commands that don't work over an object */ 320 enum { 321 MLX5_CMD_OP_GENERAL_START = 0xb00, 322 MLX5_CMD_OP_GENERAL_END = 0xd00, 323 }; 324 325 enum { 326 MLX5_FT_NIC_RX_2_NIC_RX_RDMA = BIT(0), 327 MLX5_FT_NIC_TX_RDMA_2_NIC_TX = BIT(1), 328 }; 329 330 enum { 331 MLX5_CMD_OP_MOD_UPDATE_HEADER_MODIFY_ARGUMENT = 0x1, 332 }; 333 334 struct mlx5_ifc_flow_table_fields_supported_bits { 335 u8 outer_dmac[0x1]; 336 u8 outer_smac[0x1]; 337 u8 outer_ether_type[0x1]; 338 u8 outer_ip_version[0x1]; 339 u8 outer_first_prio[0x1]; 340 u8 outer_first_cfi[0x1]; 341 u8 outer_first_vid[0x1]; 342 u8 outer_ipv4_ttl[0x1]; 343 u8 outer_second_prio[0x1]; 344 u8 outer_second_cfi[0x1]; 345 u8 outer_second_vid[0x1]; 346 u8 reserved_at_b[0x1]; 347 u8 outer_sip[0x1]; 348 u8 outer_dip[0x1]; 349 u8 outer_frag[0x1]; 350 u8 outer_ip_protocol[0x1]; 351 u8 outer_ip_ecn[0x1]; 352 u8 outer_ip_dscp[0x1]; 353 u8 outer_udp_sport[0x1]; 354 u8 outer_udp_dport[0x1]; 355 u8 outer_tcp_sport[0x1]; 356 u8 outer_tcp_dport[0x1]; 357 u8 outer_tcp_flags[0x1]; 358 u8 outer_gre_protocol[0x1]; 359 u8 outer_gre_key[0x1]; 360 u8 outer_vxlan_vni[0x1]; 361 u8 outer_geneve_vni[0x1]; 362 u8 outer_geneve_oam[0x1]; 363 u8 outer_geneve_protocol_type[0x1]; 364 u8 outer_geneve_opt_len[0x1]; 365 u8 source_vhca_port[0x1]; 366 u8 source_eswitch_port[0x1]; 367 368 u8 inner_dmac[0x1]; 369 u8 inner_smac[0x1]; 370 u8 inner_ether_type[0x1]; 371 u8 inner_ip_version[0x1]; 372 u8 inner_first_prio[0x1]; 373 u8 inner_first_cfi[0x1]; 374 u8 inner_first_vid[0x1]; 375 u8 reserved_at_27[0x1]; 376 u8 inner_second_prio[0x1]; 377 u8 inner_second_cfi[0x1]; 378 u8 inner_second_vid[0x1]; 379 u8 reserved_at_2b[0x1]; 380 u8 inner_sip[0x1]; 381 u8 inner_dip[0x1]; 382 u8 inner_frag[0x1]; 383 u8 inner_ip_protocol[0x1]; 384 u8 inner_ip_ecn[0x1]; 385 u8 inner_ip_dscp[0x1]; 386 u8 inner_udp_sport[0x1]; 387 u8 inner_udp_dport[0x1]; 388 u8 inner_tcp_sport[0x1]; 389 u8 inner_tcp_dport[0x1]; 390 u8 inner_tcp_flags[0x1]; 391 u8 reserved_at_37[0x9]; 392 393 u8 geneve_tlv_option_0_data[0x1]; 394 u8 geneve_tlv_option_0_exist[0x1]; 395 u8 reserved_at_42[0x3]; 396 u8 outer_first_mpls_over_udp[0x4]; 397 u8 outer_first_mpls_over_gre[0x4]; 398 u8 inner_first_mpls[0x4]; 399 u8 outer_first_mpls[0x4]; 400 u8 reserved_at_55[0x2]; 401 u8 outer_esp_spi[0x1]; 402 u8 reserved_at_58[0x2]; 403 u8 bth_dst_qp[0x1]; 404 u8 reserved_at_5b[0x5]; 405 406 u8 reserved_at_60[0x18]; 407 u8 metadata_reg_c_7[0x1]; 408 u8 metadata_reg_c_6[0x1]; 409 u8 metadata_reg_c_5[0x1]; 410 u8 metadata_reg_c_4[0x1]; 411 u8 metadata_reg_c_3[0x1]; 412 u8 metadata_reg_c_2[0x1]; 413 u8 metadata_reg_c_1[0x1]; 414 u8 metadata_reg_c_0[0x1]; 415 }; 416 417 /* Table 2170 - Flow Table Fields Supported 2 Format */ 418 struct mlx5_ifc_flow_table_fields_supported_2_bits { 419 u8 reserved_at_0[0xe]; 420 u8 bth_opcode[0x1]; 421 u8 reserved_at_f[0x1]; 422 u8 tunnel_header_0_1[0x1]; 423 u8 reserved_at_11[0xf]; 424 425 u8 reserved_at_20[0x60]; 426 }; 427 428 struct mlx5_ifc_flow_table_prop_layout_bits { 429 u8 ft_support[0x1]; 430 u8 reserved_at_1[0x1]; 431 u8 flow_counter[0x1]; 432 u8 flow_modify_en[0x1]; 433 u8 modify_root[0x1]; 434 u8 identified_miss_table_mode[0x1]; 435 u8 flow_table_modify[0x1]; 436 u8 reformat[0x1]; 437 u8 decap[0x1]; 438 u8 reset_root_to_default[0x1]; 439 u8 pop_vlan[0x1]; 440 u8 push_vlan[0x1]; 441 u8 reserved_at_c[0x1]; 442 u8 pop_vlan_2[0x1]; 443 u8 push_vlan_2[0x1]; 444 u8 reformat_and_vlan_action[0x1]; 445 u8 reserved_at_10[0x1]; 446 u8 sw_owner[0x1]; 447 u8 reformat_l3_tunnel_to_l2[0x1]; 448 u8 reformat_l2_to_l3_tunnel[0x1]; 449 u8 reformat_and_modify_action[0x1]; 450 u8 ignore_flow_level[0x1]; 451 u8 reserved_at_16[0x1]; 452 u8 table_miss_action_domain[0x1]; 453 u8 termination_table[0x1]; 454 u8 reformat_and_fwd_to_table[0x1]; 455 u8 reserved_at_1a[0x2]; 456 u8 ipsec_encrypt[0x1]; 457 u8 ipsec_decrypt[0x1]; 458 u8 sw_owner_v2[0x1]; 459 u8 reserved_at_1f[0x1]; 460 461 u8 termination_table_raw_traffic[0x1]; 462 u8 reserved_at_21[0x1]; 463 u8 log_max_ft_size[0x6]; 464 u8 log_max_modify_header_context[0x8]; 465 u8 max_modify_header_actions[0x8]; 466 u8 max_ft_level[0x8]; 467 468 u8 reformat_add_esp_trasport[0x1]; 469 u8 reformat_l2_to_l3_esp_tunnel[0x1]; 470 u8 reformat_add_esp_transport_over_udp[0x1]; 471 u8 reformat_del_esp_trasport[0x1]; 472 u8 reformat_l3_esp_tunnel_to_l2[0x1]; 473 u8 reformat_del_esp_transport_over_udp[0x1]; 474 u8 execute_aso[0x1]; 475 u8 reserved_at_47[0x19]; 476 477 u8 reserved_at_60[0x2]; 478 u8 reformat_insert[0x1]; 479 u8 reformat_remove[0x1]; 480 u8 macsec_encrypt[0x1]; 481 u8 macsec_decrypt[0x1]; 482 u8 reserved_at_66[0x2]; 483 u8 reformat_add_macsec[0x1]; 484 u8 reformat_remove_macsec[0x1]; 485 u8 reserved_at_6a[0xe]; 486 u8 log_max_ft_num[0x8]; 487 488 u8 reserved_at_80[0x10]; 489 u8 log_max_flow_counter[0x8]; 490 u8 log_max_destination[0x8]; 491 492 u8 reserved_at_a0[0x18]; 493 u8 log_max_flow[0x8]; 494 495 u8 reserved_at_c0[0x40]; 496 497 struct mlx5_ifc_flow_table_fields_supported_bits ft_field_support; 498 499 struct mlx5_ifc_flow_table_fields_supported_bits ft_field_bitmask_support; 500 }; 501 502 struct mlx5_ifc_odp_per_transport_service_cap_bits { 503 u8 send[0x1]; 504 u8 receive[0x1]; 505 u8 write[0x1]; 506 u8 read[0x1]; 507 u8 atomic[0x1]; 508 u8 srq_receive[0x1]; 509 u8 reserved_at_6[0x1a]; 510 }; 511 512 struct mlx5_ifc_ipv4_layout_bits { 513 u8 reserved_at_0[0x60]; 514 515 u8 ipv4[0x20]; 516 }; 517 518 struct mlx5_ifc_ipv6_layout_bits { 519 u8 ipv6[16][0x8]; 520 }; 521 522 union mlx5_ifc_ipv6_layout_ipv4_layout_auto_bits { 523 struct mlx5_ifc_ipv6_layout_bits ipv6_layout; 524 struct mlx5_ifc_ipv4_layout_bits ipv4_layout; 525 u8 reserved_at_0[0x80]; 526 }; 527 528 struct mlx5_ifc_fte_match_set_lyr_2_4_bits { 529 u8 smac_47_16[0x20]; 530 531 u8 smac_15_0[0x10]; 532 u8 ethertype[0x10]; 533 534 u8 dmac_47_16[0x20]; 535 536 u8 dmac_15_0[0x10]; 537 u8 first_prio[0x3]; 538 u8 first_cfi[0x1]; 539 u8 first_vid[0xc]; 540 541 u8 ip_protocol[0x8]; 542 u8 ip_dscp[0x6]; 543 u8 ip_ecn[0x2]; 544 u8 cvlan_tag[0x1]; 545 u8 svlan_tag[0x1]; 546 u8 frag[0x1]; 547 u8 ip_version[0x4]; 548 u8 tcp_flags[0x9]; 549 550 u8 tcp_sport[0x10]; 551 u8 tcp_dport[0x10]; 552 553 u8 reserved_at_c0[0x10]; 554 u8 ipv4_ihl[0x4]; 555 u8 reserved_at_c4[0x4]; 556 557 u8 ttl_hoplimit[0x8]; 558 559 u8 udp_sport[0x10]; 560 u8 udp_dport[0x10]; 561 562 union mlx5_ifc_ipv6_layout_ipv4_layout_auto_bits src_ipv4_src_ipv6; 563 564 union mlx5_ifc_ipv6_layout_ipv4_layout_auto_bits dst_ipv4_dst_ipv6; 565 }; 566 567 struct mlx5_ifc_nvgre_key_bits { 568 u8 hi[0x18]; 569 u8 lo[0x8]; 570 }; 571 572 union mlx5_ifc_gre_key_bits { 573 struct mlx5_ifc_nvgre_key_bits nvgre; 574 u8 key[0x20]; 575 }; 576 577 struct mlx5_ifc_fte_match_set_misc_bits { 578 u8 gre_c_present[0x1]; 579 u8 reserved_at_1[0x1]; 580 u8 gre_k_present[0x1]; 581 u8 gre_s_present[0x1]; 582 u8 source_vhca_port[0x4]; 583 u8 source_sqn[0x18]; 584 585 u8 source_eswitch_owner_vhca_id[0x10]; 586 u8 source_port[0x10]; 587 588 u8 outer_second_prio[0x3]; 589 u8 outer_second_cfi[0x1]; 590 u8 outer_second_vid[0xc]; 591 u8 inner_second_prio[0x3]; 592 u8 inner_second_cfi[0x1]; 593 u8 inner_second_vid[0xc]; 594 595 u8 outer_second_cvlan_tag[0x1]; 596 u8 inner_second_cvlan_tag[0x1]; 597 u8 outer_second_svlan_tag[0x1]; 598 u8 inner_second_svlan_tag[0x1]; 599 u8 reserved_at_64[0xc]; 600 u8 gre_protocol[0x10]; 601 602 union mlx5_ifc_gre_key_bits gre_key; 603 604 u8 vxlan_vni[0x18]; 605 u8 bth_opcode[0x8]; 606 607 u8 geneve_vni[0x18]; 608 u8 reserved_at_d8[0x6]; 609 u8 geneve_tlv_option_0_exist[0x1]; 610 u8 geneve_oam[0x1]; 611 612 u8 reserved_at_e0[0xc]; 613 u8 outer_ipv6_flow_label[0x14]; 614 615 u8 reserved_at_100[0xc]; 616 u8 inner_ipv6_flow_label[0x14]; 617 618 u8 reserved_at_120[0xa]; 619 u8 geneve_opt_len[0x6]; 620 u8 geneve_protocol_type[0x10]; 621 622 u8 reserved_at_140[0x8]; 623 u8 bth_dst_qp[0x18]; 624 u8 inner_esp_spi[0x20]; 625 u8 outer_esp_spi[0x20]; 626 u8 reserved_at_1a0[0x60]; 627 }; 628 629 struct mlx5_ifc_fte_match_mpls_bits { 630 u8 mpls_label[0x14]; 631 u8 mpls_exp[0x3]; 632 u8 mpls_s_bos[0x1]; 633 u8 mpls_ttl[0x8]; 634 }; 635 636 struct mlx5_ifc_fte_match_set_misc2_bits { 637 struct mlx5_ifc_fte_match_mpls_bits outer_first_mpls; 638 639 struct mlx5_ifc_fte_match_mpls_bits inner_first_mpls; 640 641 struct mlx5_ifc_fte_match_mpls_bits outer_first_mpls_over_gre; 642 643 struct mlx5_ifc_fte_match_mpls_bits outer_first_mpls_over_udp; 644 645 u8 metadata_reg_c_7[0x20]; 646 647 u8 metadata_reg_c_6[0x20]; 648 649 u8 metadata_reg_c_5[0x20]; 650 651 u8 metadata_reg_c_4[0x20]; 652 653 u8 metadata_reg_c_3[0x20]; 654 655 u8 metadata_reg_c_2[0x20]; 656 657 u8 metadata_reg_c_1[0x20]; 658 659 u8 metadata_reg_c_0[0x20]; 660 661 u8 metadata_reg_a[0x20]; 662 663 u8 reserved_at_1a0[0x8]; 664 665 u8 macsec_syndrome[0x8]; 666 u8 ipsec_syndrome[0x8]; 667 u8 reserved_at_1b8[0x8]; 668 669 u8 reserved_at_1c0[0x40]; 670 }; 671 672 struct mlx5_ifc_fte_match_set_misc3_bits { 673 u8 inner_tcp_seq_num[0x20]; 674 675 u8 outer_tcp_seq_num[0x20]; 676 677 u8 inner_tcp_ack_num[0x20]; 678 679 u8 outer_tcp_ack_num[0x20]; 680 681 u8 reserved_at_80[0x8]; 682 u8 outer_vxlan_gpe_vni[0x18]; 683 684 u8 outer_vxlan_gpe_next_protocol[0x8]; 685 u8 outer_vxlan_gpe_flags[0x8]; 686 u8 reserved_at_b0[0x10]; 687 688 u8 icmp_header_data[0x20]; 689 690 u8 icmpv6_header_data[0x20]; 691 692 u8 icmp_type[0x8]; 693 u8 icmp_code[0x8]; 694 u8 icmpv6_type[0x8]; 695 u8 icmpv6_code[0x8]; 696 697 u8 geneve_tlv_option_0_data[0x20]; 698 699 u8 gtpu_teid[0x20]; 700 701 u8 gtpu_msg_type[0x8]; 702 u8 gtpu_msg_flags[0x8]; 703 u8 reserved_at_170[0x10]; 704 705 u8 gtpu_dw_2[0x20]; 706 707 u8 gtpu_first_ext_dw_0[0x20]; 708 709 u8 gtpu_dw_0[0x20]; 710 711 u8 reserved_at_1e0[0x20]; 712 }; 713 714 struct mlx5_ifc_fte_match_set_misc4_bits { 715 u8 prog_sample_field_value_0[0x20]; 716 717 u8 prog_sample_field_id_0[0x20]; 718 719 u8 prog_sample_field_value_1[0x20]; 720 721 u8 prog_sample_field_id_1[0x20]; 722 723 u8 prog_sample_field_value_2[0x20]; 724 725 u8 prog_sample_field_id_2[0x20]; 726 727 u8 prog_sample_field_value_3[0x20]; 728 729 u8 prog_sample_field_id_3[0x20]; 730 731 u8 reserved_at_100[0x100]; 732 }; 733 734 struct mlx5_ifc_fte_match_set_misc5_bits { 735 u8 macsec_tag_0[0x20]; 736 737 u8 macsec_tag_1[0x20]; 738 739 u8 macsec_tag_2[0x20]; 740 741 u8 macsec_tag_3[0x20]; 742 743 u8 tunnel_header_0[0x20]; 744 745 u8 tunnel_header_1[0x20]; 746 747 u8 tunnel_header_2[0x20]; 748 749 u8 tunnel_header_3[0x20]; 750 751 u8 reserved_at_100[0x100]; 752 }; 753 754 struct mlx5_ifc_cmd_pas_bits { 755 u8 pa_h[0x20]; 756 757 u8 pa_l[0x14]; 758 u8 reserved_at_34[0xc]; 759 }; 760 761 struct mlx5_ifc_uint64_bits { 762 u8 hi[0x20]; 763 764 u8 lo[0x20]; 765 }; 766 767 enum { 768 MLX5_ADS_STAT_RATE_NO_LIMIT = 0x0, 769 MLX5_ADS_STAT_RATE_2_5GBPS = 0x7, 770 MLX5_ADS_STAT_RATE_10GBPS = 0x8, 771 MLX5_ADS_STAT_RATE_30GBPS = 0x9, 772 MLX5_ADS_STAT_RATE_5GBPS = 0xa, 773 MLX5_ADS_STAT_RATE_20GBPS = 0xb, 774 MLX5_ADS_STAT_RATE_40GBPS = 0xc, 775 MLX5_ADS_STAT_RATE_60GBPS = 0xd, 776 MLX5_ADS_STAT_RATE_80GBPS = 0xe, 777 MLX5_ADS_STAT_RATE_120GBPS = 0xf, 778 }; 779 780 struct mlx5_ifc_ads_bits { 781 u8 fl[0x1]; 782 u8 free_ar[0x1]; 783 u8 reserved_at_2[0xe]; 784 u8 pkey_index[0x10]; 785 786 u8 reserved_at_20[0x8]; 787 u8 grh[0x1]; 788 u8 mlid[0x7]; 789 u8 rlid[0x10]; 790 791 u8 ack_timeout[0x5]; 792 u8 reserved_at_45[0x3]; 793 u8 src_addr_index[0x8]; 794 u8 reserved_at_50[0x4]; 795 u8 stat_rate[0x4]; 796 u8 hop_limit[0x8]; 797 798 u8 reserved_at_60[0x4]; 799 u8 tclass[0x8]; 800 u8 flow_label[0x14]; 801 802 u8 rgid_rip[16][0x8]; 803 804 u8 reserved_at_100[0x4]; 805 u8 f_dscp[0x1]; 806 u8 f_ecn[0x1]; 807 u8 reserved_at_106[0x1]; 808 u8 f_eth_prio[0x1]; 809 u8 ecn[0x2]; 810 u8 dscp[0x6]; 811 u8 udp_sport[0x10]; 812 813 u8 dei_cfi[0x1]; 814 u8 eth_prio[0x3]; 815 u8 sl[0x4]; 816 u8 vhca_port_num[0x8]; 817 u8 rmac_47_32[0x10]; 818 819 u8 rmac_31_0[0x20]; 820 }; 821 822 struct mlx5_ifc_flow_table_nic_cap_bits { 823 u8 nic_rx_multi_path_tirs[0x1]; 824 u8 nic_rx_multi_path_tirs_fts[0x1]; 825 u8 allow_sniffer_and_nic_rx_shared_tir[0x1]; 826 u8 reserved_at_3[0x4]; 827 u8 sw_owner_reformat_supported[0x1]; 828 u8 reserved_at_8[0x18]; 829 830 u8 encap_general_header[0x1]; 831 u8 reserved_at_21[0xa]; 832 u8 log_max_packet_reformat_context[0x5]; 833 u8 reserved_at_30[0x6]; 834 u8 max_encap_header_size[0xa]; 835 u8 reserved_at_40[0x1c0]; 836 837 struct mlx5_ifc_flow_table_prop_layout_bits flow_table_properties_nic_receive; 838 839 struct mlx5_ifc_flow_table_prop_layout_bits flow_table_properties_nic_receive_rdma; 840 841 struct mlx5_ifc_flow_table_prop_layout_bits flow_table_properties_nic_receive_sniffer; 842 843 struct mlx5_ifc_flow_table_prop_layout_bits flow_table_properties_nic_transmit; 844 845 struct mlx5_ifc_flow_table_prop_layout_bits flow_table_properties_nic_transmit_rdma; 846 847 struct mlx5_ifc_flow_table_prop_layout_bits flow_table_properties_nic_transmit_sniffer; 848 849 u8 reserved_at_e00[0x700]; 850 851 struct mlx5_ifc_flow_table_fields_supported_2_bits ft_field_support_2_nic_receive_rdma; 852 853 u8 reserved_at_1580[0x280]; 854 855 struct mlx5_ifc_flow_table_fields_supported_2_bits ft_field_support_2_nic_transmit_rdma; 856 857 u8 reserved_at_1880[0x780]; 858 859 u8 sw_steering_nic_rx_action_drop_icm_address[0x40]; 860 861 u8 sw_steering_nic_tx_action_drop_icm_address[0x40]; 862 863 u8 sw_steering_nic_tx_action_allow_icm_address[0x40]; 864 865 u8 reserved_at_20c0[0x5f40]; 866 }; 867 868 struct mlx5_ifc_port_selection_cap_bits { 869 u8 reserved_at_0[0x10]; 870 u8 port_select_flow_table[0x1]; 871 u8 reserved_at_11[0x1]; 872 u8 port_select_flow_table_bypass[0x1]; 873 u8 reserved_at_13[0xd]; 874 875 u8 reserved_at_20[0x1e0]; 876 877 struct mlx5_ifc_flow_table_prop_layout_bits flow_table_properties_port_selection; 878 879 u8 reserved_at_400[0x7c00]; 880 }; 881 882 enum { 883 MLX5_FDB_TO_VPORT_REG_C_0 = 0x01, 884 MLX5_FDB_TO_VPORT_REG_C_1 = 0x02, 885 MLX5_FDB_TO_VPORT_REG_C_2 = 0x04, 886 MLX5_FDB_TO_VPORT_REG_C_3 = 0x08, 887 MLX5_FDB_TO_VPORT_REG_C_4 = 0x10, 888 MLX5_FDB_TO_VPORT_REG_C_5 = 0x20, 889 MLX5_FDB_TO_VPORT_REG_C_6 = 0x40, 890 MLX5_FDB_TO_VPORT_REG_C_7 = 0x80, 891 }; 892 893 struct mlx5_ifc_flow_table_eswitch_cap_bits { 894 u8 fdb_to_vport_reg_c_id[0x8]; 895 u8 reserved_at_8[0x5]; 896 u8 fdb_uplink_hairpin[0x1]; 897 u8 fdb_multi_path_any_table_limit_regc[0x1]; 898 u8 reserved_at_f[0x3]; 899 u8 fdb_multi_path_any_table[0x1]; 900 u8 reserved_at_13[0x2]; 901 u8 fdb_modify_header_fwd_to_table[0x1]; 902 u8 fdb_ipv4_ttl_modify[0x1]; 903 u8 flow_source[0x1]; 904 u8 reserved_at_18[0x2]; 905 u8 multi_fdb_encap[0x1]; 906 u8 egress_acl_forward_to_vport[0x1]; 907 u8 fdb_multi_path_to_table[0x1]; 908 u8 reserved_at_1d[0x3]; 909 910 u8 reserved_at_20[0x1e0]; 911 912 struct mlx5_ifc_flow_table_prop_layout_bits flow_table_properties_nic_esw_fdb; 913 914 struct mlx5_ifc_flow_table_prop_layout_bits flow_table_properties_esw_acl_ingress; 915 916 struct mlx5_ifc_flow_table_prop_layout_bits flow_table_properties_esw_acl_egress; 917 918 u8 reserved_at_800[0xC00]; 919 920 struct mlx5_ifc_flow_table_fields_supported_2_bits ft_field_support_2_esw_fdb; 921 922 struct mlx5_ifc_flow_table_fields_supported_2_bits ft_field_bitmask_support_2_esw_fdb; 923 924 u8 reserved_at_1500[0x300]; 925 926 u8 sw_steering_fdb_action_drop_icm_address_rx[0x40]; 927 928 u8 sw_steering_fdb_action_drop_icm_address_tx[0x40]; 929 930 u8 sw_steering_uplink_icm_address_rx[0x40]; 931 932 u8 sw_steering_uplink_icm_address_tx[0x40]; 933 934 u8 reserved_at_1900[0x6700]; 935 }; 936 937 enum { 938 MLX5_COUNTER_SOURCE_ESWITCH = 0x0, 939 MLX5_COUNTER_FLOW_ESWITCH = 0x1, 940 }; 941 942 struct mlx5_ifc_e_switch_cap_bits { 943 u8 vport_svlan_strip[0x1]; 944 u8 vport_cvlan_strip[0x1]; 945 u8 vport_svlan_insert[0x1]; 946 u8 vport_cvlan_insert_if_not_exist[0x1]; 947 u8 vport_cvlan_insert_overwrite[0x1]; 948 u8 reserved_at_5[0x1]; 949 u8 vport_cvlan_insert_always[0x1]; 950 u8 esw_shared_ingress_acl[0x1]; 951 u8 esw_uplink_ingress_acl[0x1]; 952 u8 root_ft_on_other_esw[0x1]; 953 u8 reserved_at_a[0xf]; 954 u8 esw_functions_changed[0x1]; 955 u8 reserved_at_1a[0x1]; 956 u8 ecpf_vport_exists[0x1]; 957 u8 counter_eswitch_affinity[0x1]; 958 u8 merged_eswitch[0x1]; 959 u8 nic_vport_node_guid_modify[0x1]; 960 u8 nic_vport_port_guid_modify[0x1]; 961 962 u8 vxlan_encap_decap[0x1]; 963 u8 nvgre_encap_decap[0x1]; 964 u8 reserved_at_22[0x1]; 965 u8 log_max_fdb_encap_uplink[0x5]; 966 u8 reserved_at_21[0x3]; 967 u8 log_max_packet_reformat_context[0x5]; 968 u8 reserved_2b[0x6]; 969 u8 max_encap_header_size[0xa]; 970 971 u8 reserved_at_40[0xb]; 972 u8 log_max_esw_sf[0x5]; 973 u8 esw_sf_base_id[0x10]; 974 975 u8 reserved_at_60[0x7a0]; 976 977 }; 978 979 struct mlx5_ifc_qos_cap_bits { 980 u8 packet_pacing[0x1]; 981 u8 esw_scheduling[0x1]; 982 u8 esw_bw_share[0x1]; 983 u8 esw_rate_limit[0x1]; 984 u8 reserved_at_4[0x1]; 985 u8 packet_pacing_burst_bound[0x1]; 986 u8 packet_pacing_typical_size[0x1]; 987 u8 reserved_at_7[0x1]; 988 u8 nic_sq_scheduling[0x1]; 989 u8 nic_bw_share[0x1]; 990 u8 nic_rate_limit[0x1]; 991 u8 packet_pacing_uid[0x1]; 992 u8 log_esw_max_sched_depth[0x4]; 993 u8 reserved_at_10[0x10]; 994 995 u8 reserved_at_20[0xb]; 996 u8 log_max_qos_nic_queue_group[0x5]; 997 u8 reserved_at_30[0x10]; 998 999 u8 packet_pacing_max_rate[0x20]; 1000 1001 u8 packet_pacing_min_rate[0x20]; 1002 1003 u8 reserved_at_80[0x10]; 1004 u8 packet_pacing_rate_table_size[0x10]; 1005 1006 u8 esw_element_type[0x10]; 1007 u8 esw_tsar_type[0x10]; 1008 1009 u8 reserved_at_c0[0x10]; 1010 u8 max_qos_para_vport[0x10]; 1011 1012 u8 max_tsar_bw_share[0x20]; 1013 1014 u8 reserved_at_100[0x20]; 1015 1016 u8 reserved_at_120[0x3]; 1017 u8 log_meter_aso_granularity[0x5]; 1018 u8 reserved_at_128[0x3]; 1019 u8 log_meter_aso_max_alloc[0x5]; 1020 u8 reserved_at_130[0x3]; 1021 u8 log_max_num_meter_aso[0x5]; 1022 u8 reserved_at_138[0x8]; 1023 1024 u8 reserved_at_140[0x6c0]; 1025 }; 1026 1027 struct mlx5_ifc_debug_cap_bits { 1028 u8 core_dump_general[0x1]; 1029 u8 core_dump_qp[0x1]; 1030 u8 reserved_at_2[0x7]; 1031 u8 resource_dump[0x1]; 1032 u8 reserved_at_a[0x16]; 1033 1034 u8 reserved_at_20[0x2]; 1035 u8 stall_detect[0x1]; 1036 u8 reserved_at_23[0x1d]; 1037 1038 u8 reserved_at_40[0x7c0]; 1039 }; 1040 1041 struct mlx5_ifc_per_protocol_networking_offload_caps_bits { 1042 u8 csum_cap[0x1]; 1043 u8 vlan_cap[0x1]; 1044 u8 lro_cap[0x1]; 1045 u8 lro_psh_flag[0x1]; 1046 u8 lro_time_stamp[0x1]; 1047 u8 reserved_at_5[0x2]; 1048 u8 wqe_vlan_insert[0x1]; 1049 u8 self_lb_en_modifiable[0x1]; 1050 u8 reserved_at_9[0x2]; 1051 u8 max_lso_cap[0x5]; 1052 u8 multi_pkt_send_wqe[0x2]; 1053 u8 wqe_inline_mode[0x2]; 1054 u8 rss_ind_tbl_cap[0x4]; 1055 u8 reg_umr_sq[0x1]; 1056 u8 scatter_fcs[0x1]; 1057 u8 enhanced_multi_pkt_send_wqe[0x1]; 1058 u8 tunnel_lso_const_out_ip_id[0x1]; 1059 u8 tunnel_lro_gre[0x1]; 1060 u8 tunnel_lro_vxlan[0x1]; 1061 u8 tunnel_stateless_gre[0x1]; 1062 u8 tunnel_stateless_vxlan[0x1]; 1063 1064 u8 swp[0x1]; 1065 u8 swp_csum[0x1]; 1066 u8 swp_lso[0x1]; 1067 u8 cqe_checksum_full[0x1]; 1068 u8 tunnel_stateless_geneve_tx[0x1]; 1069 u8 tunnel_stateless_mpls_over_udp[0x1]; 1070 u8 tunnel_stateless_mpls_over_gre[0x1]; 1071 u8 tunnel_stateless_vxlan_gpe[0x1]; 1072 u8 tunnel_stateless_ipv4_over_vxlan[0x1]; 1073 u8 tunnel_stateless_ip_over_ip[0x1]; 1074 u8 insert_trailer[0x1]; 1075 u8 reserved_at_2b[0x1]; 1076 u8 tunnel_stateless_ip_over_ip_rx[0x1]; 1077 u8 tunnel_stateless_ip_over_ip_tx[0x1]; 1078 u8 reserved_at_2e[0x2]; 1079 u8 max_vxlan_udp_ports[0x8]; 1080 u8 reserved_at_38[0x6]; 1081 u8 max_geneve_opt_len[0x1]; 1082 u8 tunnel_stateless_geneve_rx[0x1]; 1083 1084 u8 reserved_at_40[0x10]; 1085 u8 lro_min_mss_size[0x10]; 1086 1087 u8 reserved_at_60[0x120]; 1088 1089 u8 lro_timer_supported_periods[4][0x20]; 1090 1091 u8 reserved_at_200[0x600]; 1092 }; 1093 1094 enum { 1095 MLX5_TIMESTAMP_FORMAT_CAP_FREE_RUNNING = 0x0, 1096 MLX5_TIMESTAMP_FORMAT_CAP_REAL_TIME = 0x1, 1097 MLX5_TIMESTAMP_FORMAT_CAP_FREE_RUNNING_AND_REAL_TIME = 0x2, 1098 }; 1099 1100 struct mlx5_ifc_roce_cap_bits { 1101 u8 roce_apm[0x1]; 1102 u8 reserved_at_1[0x3]; 1103 u8 sw_r_roce_src_udp_port[0x1]; 1104 u8 fl_rc_qp_when_roce_disabled[0x1]; 1105 u8 fl_rc_qp_when_roce_enabled[0x1]; 1106 u8 reserved_at_7[0x1]; 1107 u8 qp_ooo_transmit_default[0x1]; 1108 u8 reserved_at_9[0x15]; 1109 u8 qp_ts_format[0x2]; 1110 1111 u8 reserved_at_20[0x60]; 1112 1113 u8 reserved_at_80[0xc]; 1114 u8 l3_type[0x4]; 1115 u8 reserved_at_90[0x8]; 1116 u8 roce_version[0x8]; 1117 1118 u8 reserved_at_a0[0x10]; 1119 u8 r_roce_dest_udp_port[0x10]; 1120 1121 u8 r_roce_max_src_udp_port[0x10]; 1122 u8 r_roce_min_src_udp_port[0x10]; 1123 1124 u8 reserved_at_e0[0x10]; 1125 u8 roce_address_table_size[0x10]; 1126 1127 u8 reserved_at_100[0x700]; 1128 }; 1129 1130 struct mlx5_ifc_sync_steering_in_bits { 1131 u8 opcode[0x10]; 1132 u8 uid[0x10]; 1133 1134 u8 reserved_at_20[0x10]; 1135 u8 op_mod[0x10]; 1136 1137 u8 reserved_at_40[0xc0]; 1138 }; 1139 1140 struct mlx5_ifc_sync_steering_out_bits { 1141 u8 status[0x8]; 1142 u8 reserved_at_8[0x18]; 1143 1144 u8 syndrome[0x20]; 1145 1146 u8 reserved_at_40[0x40]; 1147 }; 1148 1149 struct mlx5_ifc_sync_crypto_in_bits { 1150 u8 opcode[0x10]; 1151 u8 uid[0x10]; 1152 1153 u8 reserved_at_20[0x10]; 1154 u8 op_mod[0x10]; 1155 1156 u8 reserved_at_40[0x20]; 1157 1158 u8 reserved_at_60[0x10]; 1159 u8 crypto_type[0x10]; 1160 1161 u8 reserved_at_80[0x80]; 1162 }; 1163 1164 struct mlx5_ifc_sync_crypto_out_bits { 1165 u8 status[0x8]; 1166 u8 reserved_at_8[0x18]; 1167 1168 u8 syndrome[0x20]; 1169 1170 u8 reserved_at_40[0x40]; 1171 }; 1172 1173 struct mlx5_ifc_device_mem_cap_bits { 1174 u8 memic[0x1]; 1175 u8 reserved_at_1[0x1f]; 1176 1177 u8 reserved_at_20[0xb]; 1178 u8 log_min_memic_alloc_size[0x5]; 1179 u8 reserved_at_30[0x8]; 1180 u8 log_max_memic_addr_alignment[0x8]; 1181 1182 u8 memic_bar_start_addr[0x40]; 1183 1184 u8 memic_bar_size[0x20]; 1185 1186 u8 max_memic_size[0x20]; 1187 1188 u8 steering_sw_icm_start_address[0x40]; 1189 1190 u8 reserved_at_100[0x8]; 1191 u8 log_header_modify_sw_icm_size[0x8]; 1192 u8 reserved_at_110[0x2]; 1193 u8 log_sw_icm_alloc_granularity[0x6]; 1194 u8 log_steering_sw_icm_size[0x8]; 1195 1196 u8 log_indirect_encap_sw_icm_size[0x8]; 1197 u8 reserved_at_128[0x10]; 1198 u8 log_header_modify_pattern_sw_icm_size[0x8]; 1199 1200 u8 header_modify_sw_icm_start_address[0x40]; 1201 1202 u8 reserved_at_180[0x40]; 1203 1204 u8 header_modify_pattern_sw_icm_start_address[0x40]; 1205 1206 u8 memic_operations[0x20]; 1207 1208 u8 reserved_at_220[0x20]; 1209 1210 u8 indirect_encap_sw_icm_start_address[0x40]; 1211 1212 u8 reserved_at_280[0x580]; 1213 }; 1214 1215 struct mlx5_ifc_device_event_cap_bits { 1216 u8 user_affiliated_events[4][0x40]; 1217 1218 u8 user_unaffiliated_events[4][0x40]; 1219 }; 1220 1221 struct mlx5_ifc_virtio_emulation_cap_bits { 1222 u8 desc_tunnel_offload_type[0x1]; 1223 u8 eth_frame_offload_type[0x1]; 1224 u8 virtio_version_1_0[0x1]; 1225 u8 device_features_bits_mask[0xd]; 1226 u8 event_mode[0x8]; 1227 u8 virtio_queue_type[0x8]; 1228 1229 u8 max_tunnel_desc[0x10]; 1230 u8 reserved_at_30[0x3]; 1231 u8 log_doorbell_stride[0x5]; 1232 u8 reserved_at_38[0x3]; 1233 u8 log_doorbell_bar_size[0x5]; 1234 1235 u8 doorbell_bar_offset[0x40]; 1236 1237 u8 max_emulated_devices[0x8]; 1238 u8 max_num_virtio_queues[0x18]; 1239 1240 u8 reserved_at_a0[0x20]; 1241 1242 u8 reserved_at_c0[0x13]; 1243 u8 desc_group_mkey_supported[0x1]; 1244 u8 reserved_at_d4[0xc]; 1245 1246 u8 reserved_at_e0[0x20]; 1247 1248 u8 umem_1_buffer_param_a[0x20]; 1249 1250 u8 umem_1_buffer_param_b[0x20]; 1251 1252 u8 umem_2_buffer_param_a[0x20]; 1253 1254 u8 umem_2_buffer_param_b[0x20]; 1255 1256 u8 umem_3_buffer_param_a[0x20]; 1257 1258 u8 umem_3_buffer_param_b[0x20]; 1259 1260 u8 reserved_at_1c0[0x640]; 1261 }; 1262 1263 enum { 1264 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_QP_1_BYTE = 0x0, 1265 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_QP_2_BYTES = 0x2, 1266 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_QP_4_BYTES = 0x4, 1267 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_QP_8_BYTES = 0x8, 1268 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_QP_16_BYTES = 0x10, 1269 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_QP_32_BYTES = 0x20, 1270 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_QP_64_BYTES = 0x40, 1271 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_QP_128_BYTES = 0x80, 1272 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_QP_256_BYTES = 0x100, 1273 }; 1274 1275 enum { 1276 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_DC_1_BYTE = 0x1, 1277 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_DC_2_BYTES = 0x2, 1278 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_DC_4_BYTES = 0x4, 1279 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_DC_8_BYTES = 0x8, 1280 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_DC_16_BYTES = 0x10, 1281 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_DC_32_BYTES = 0x20, 1282 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_DC_64_BYTES = 0x40, 1283 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_DC_128_BYTES = 0x80, 1284 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_DC_256_BYTES = 0x100, 1285 }; 1286 1287 struct mlx5_ifc_atomic_caps_bits { 1288 u8 reserved_at_0[0x40]; 1289 1290 u8 atomic_req_8B_endianness_mode[0x2]; 1291 u8 reserved_at_42[0x4]; 1292 u8 supported_atomic_req_8B_endianness_mode_1[0x1]; 1293 1294 u8 reserved_at_47[0x19]; 1295 1296 u8 reserved_at_60[0x20]; 1297 1298 u8 reserved_at_80[0x10]; 1299 u8 atomic_operations[0x10]; 1300 1301 u8 reserved_at_a0[0x10]; 1302 u8 atomic_size_qp[0x10]; 1303 1304 u8 reserved_at_c0[0x10]; 1305 u8 atomic_size_dc[0x10]; 1306 1307 u8 reserved_at_e0[0x720]; 1308 }; 1309 1310 struct mlx5_ifc_odp_cap_bits { 1311 u8 reserved_at_0[0x40]; 1312 1313 u8 sig[0x1]; 1314 u8 reserved_at_41[0x1f]; 1315 1316 u8 reserved_at_60[0x20]; 1317 1318 struct mlx5_ifc_odp_per_transport_service_cap_bits rc_odp_caps; 1319 1320 struct mlx5_ifc_odp_per_transport_service_cap_bits uc_odp_caps; 1321 1322 struct mlx5_ifc_odp_per_transport_service_cap_bits ud_odp_caps; 1323 1324 struct mlx5_ifc_odp_per_transport_service_cap_bits xrc_odp_caps; 1325 1326 struct mlx5_ifc_odp_per_transport_service_cap_bits dc_odp_caps; 1327 1328 u8 reserved_at_120[0x6E0]; 1329 }; 1330 1331 struct mlx5_ifc_tls_cap_bits { 1332 u8 tls_1_2_aes_gcm_128[0x1]; 1333 u8 tls_1_3_aes_gcm_128[0x1]; 1334 u8 tls_1_2_aes_gcm_256[0x1]; 1335 u8 tls_1_3_aes_gcm_256[0x1]; 1336 u8 reserved_at_4[0x1c]; 1337 1338 u8 reserved_at_20[0x7e0]; 1339 }; 1340 1341 struct mlx5_ifc_ipsec_cap_bits { 1342 u8 ipsec_full_offload[0x1]; 1343 u8 ipsec_crypto_offload[0x1]; 1344 u8 ipsec_esn[0x1]; 1345 u8 ipsec_crypto_esp_aes_gcm_256_encrypt[0x1]; 1346 u8 ipsec_crypto_esp_aes_gcm_128_encrypt[0x1]; 1347 u8 ipsec_crypto_esp_aes_gcm_256_decrypt[0x1]; 1348 u8 ipsec_crypto_esp_aes_gcm_128_decrypt[0x1]; 1349 u8 reserved_at_7[0x4]; 1350 u8 log_max_ipsec_offload[0x5]; 1351 u8 reserved_at_10[0x10]; 1352 1353 u8 min_log_ipsec_full_replay_window[0x8]; 1354 u8 max_log_ipsec_full_replay_window[0x8]; 1355 u8 reserved_at_30[0x7d0]; 1356 }; 1357 1358 struct mlx5_ifc_macsec_cap_bits { 1359 u8 macsec_epn[0x1]; 1360 u8 reserved_at_1[0x2]; 1361 u8 macsec_crypto_esp_aes_gcm_256_encrypt[0x1]; 1362 u8 macsec_crypto_esp_aes_gcm_128_encrypt[0x1]; 1363 u8 macsec_crypto_esp_aes_gcm_256_decrypt[0x1]; 1364 u8 macsec_crypto_esp_aes_gcm_128_decrypt[0x1]; 1365 u8 reserved_at_7[0x4]; 1366 u8 log_max_macsec_offload[0x5]; 1367 u8 reserved_at_10[0x10]; 1368 1369 u8 min_log_macsec_full_replay_window[0x8]; 1370 u8 max_log_macsec_full_replay_window[0x8]; 1371 u8 reserved_at_30[0x10]; 1372 1373 u8 reserved_at_40[0x7c0]; 1374 }; 1375 1376 enum { 1377 MLX5_WQ_TYPE_LINKED_LIST = 0x0, 1378 MLX5_WQ_TYPE_CYCLIC = 0x1, 1379 MLX5_WQ_TYPE_LINKED_LIST_STRIDING_RQ = 0x2, 1380 MLX5_WQ_TYPE_CYCLIC_STRIDING_RQ = 0x3, 1381 }; 1382 1383 enum { 1384 MLX5_WQ_END_PAD_MODE_NONE = 0x0, 1385 MLX5_WQ_END_PAD_MODE_ALIGN = 0x1, 1386 }; 1387 1388 enum { 1389 MLX5_CMD_HCA_CAP_GID_TABLE_SIZE_8_GID_ENTRIES = 0x0, 1390 MLX5_CMD_HCA_CAP_GID_TABLE_SIZE_16_GID_ENTRIES = 0x1, 1391 MLX5_CMD_HCA_CAP_GID_TABLE_SIZE_32_GID_ENTRIES = 0x2, 1392 MLX5_CMD_HCA_CAP_GID_TABLE_SIZE_64_GID_ENTRIES = 0x3, 1393 MLX5_CMD_HCA_CAP_GID_TABLE_SIZE_128_GID_ENTRIES = 0x4, 1394 }; 1395 1396 enum { 1397 MLX5_CMD_HCA_CAP_PKEY_TABLE_SIZE_128_ENTRIES = 0x0, 1398 MLX5_CMD_HCA_CAP_PKEY_TABLE_SIZE_256_ENTRIES = 0x1, 1399 MLX5_CMD_HCA_CAP_PKEY_TABLE_SIZE_512_ENTRIES = 0x2, 1400 MLX5_CMD_HCA_CAP_PKEY_TABLE_SIZE_1K_ENTRIES = 0x3, 1401 MLX5_CMD_HCA_CAP_PKEY_TABLE_SIZE_2K_ENTRIES = 0x4, 1402 MLX5_CMD_HCA_CAP_PKEY_TABLE_SIZE_4K_ENTRIES = 0x5, 1403 }; 1404 1405 enum { 1406 MLX5_CMD_HCA_CAP_PORT_TYPE_IB = 0x0, 1407 MLX5_CMD_HCA_CAP_PORT_TYPE_ETHERNET = 0x1, 1408 }; 1409 1410 enum { 1411 MLX5_CMD_HCA_CAP_CMDIF_CHECKSUM_DISABLED = 0x0, 1412 MLX5_CMD_HCA_CAP_CMDIF_CHECKSUM_INITIAL_STATE = 0x1, 1413 MLX5_CMD_HCA_CAP_CMDIF_CHECKSUM_ENABLED = 0x3, 1414 }; 1415 1416 enum { 1417 MLX5_CAP_PORT_TYPE_IB = 0x0, 1418 MLX5_CAP_PORT_TYPE_ETH = 0x1, 1419 }; 1420 1421 enum { 1422 MLX5_CAP_UMR_FENCE_STRONG = 0x0, 1423 MLX5_CAP_UMR_FENCE_SMALL = 0x1, 1424 MLX5_CAP_UMR_FENCE_NONE = 0x2, 1425 }; 1426 1427 enum { 1428 MLX5_FLEX_PARSER_GENEVE_ENABLED = 1 << 3, 1429 MLX5_FLEX_PARSER_MPLS_OVER_GRE_ENABLED = 1 << 4, 1430 MLX5_FLEX_PARSER_MPLS_OVER_UDP_ENABLED = 1 << 5, 1431 MLX5_FLEX_PARSER_VXLAN_GPE_ENABLED = 1 << 7, 1432 MLX5_FLEX_PARSER_ICMP_V4_ENABLED = 1 << 8, 1433 MLX5_FLEX_PARSER_ICMP_V6_ENABLED = 1 << 9, 1434 MLX5_FLEX_PARSER_GENEVE_TLV_OPTION_0_ENABLED = 1 << 10, 1435 MLX5_FLEX_PARSER_GTPU_ENABLED = 1 << 11, 1436 MLX5_FLEX_PARSER_GTPU_DW_2_ENABLED = 1 << 16, 1437 MLX5_FLEX_PARSER_GTPU_FIRST_EXT_DW_0_ENABLED = 1 << 17, 1438 MLX5_FLEX_PARSER_GTPU_DW_0_ENABLED = 1 << 18, 1439 MLX5_FLEX_PARSER_GTPU_TEID_ENABLED = 1 << 19, 1440 }; 1441 1442 enum { 1443 MLX5_UCTX_CAP_RAW_TX = 1UL << 0, 1444 MLX5_UCTX_CAP_INTERNAL_DEV_RES = 1UL << 1, 1445 }; 1446 1447 #define MLX5_FC_BULK_SIZE_FACTOR 128 1448 1449 enum mlx5_fc_bulk_alloc_bitmask { 1450 MLX5_FC_BULK_128 = (1 << 0), 1451 MLX5_FC_BULK_256 = (1 << 1), 1452 MLX5_FC_BULK_512 = (1 << 2), 1453 MLX5_FC_BULK_1024 = (1 << 3), 1454 MLX5_FC_BULK_2048 = (1 << 4), 1455 MLX5_FC_BULK_4096 = (1 << 5), 1456 MLX5_FC_BULK_8192 = (1 << 6), 1457 MLX5_FC_BULK_16384 = (1 << 7), 1458 }; 1459 1460 #define MLX5_FC_BULK_NUM_FCS(fc_enum) (MLX5_FC_BULK_SIZE_FACTOR * (fc_enum)) 1461 1462 #define MLX5_FT_MAX_MULTIPATH_LEVEL 63 1463 1464 enum { 1465 MLX5_STEERING_FORMAT_CONNECTX_5 = 0, 1466 MLX5_STEERING_FORMAT_CONNECTX_6DX = 1, 1467 MLX5_STEERING_FORMAT_CONNECTX_7 = 2, 1468 }; 1469 1470 struct mlx5_ifc_cmd_hca_cap_bits { 1471 u8 reserved_at_0[0x10]; 1472 u8 shared_object_to_user_object_allowed[0x1]; 1473 u8 reserved_at_13[0xe]; 1474 u8 vhca_resource_manager[0x1]; 1475 1476 u8 hca_cap_2[0x1]; 1477 u8 create_lag_when_not_master_up[0x1]; 1478 u8 dtor[0x1]; 1479 u8 event_on_vhca_state_teardown_request[0x1]; 1480 u8 event_on_vhca_state_in_use[0x1]; 1481 u8 event_on_vhca_state_active[0x1]; 1482 u8 event_on_vhca_state_allocated[0x1]; 1483 u8 event_on_vhca_state_invalid[0x1]; 1484 u8 reserved_at_28[0x8]; 1485 u8 vhca_id[0x10]; 1486 1487 u8 reserved_at_40[0x40]; 1488 1489 u8 log_max_srq_sz[0x8]; 1490 u8 log_max_qp_sz[0x8]; 1491 u8 event_cap[0x1]; 1492 u8 reserved_at_91[0x2]; 1493 u8 isolate_vl_tc_new[0x1]; 1494 u8 reserved_at_94[0x4]; 1495 u8 prio_tag_required[0x1]; 1496 u8 reserved_at_99[0x2]; 1497 u8 log_max_qp[0x5]; 1498 1499 u8 reserved_at_a0[0x3]; 1500 u8 ece_support[0x1]; 1501 u8 reserved_at_a4[0x5]; 1502 u8 reg_c_preserve[0x1]; 1503 u8 reserved_at_aa[0x1]; 1504 u8 log_max_srq[0x5]; 1505 u8 reserved_at_b0[0x1]; 1506 u8 uplink_follow[0x1]; 1507 u8 ts_cqe_to_dest_cqn[0x1]; 1508 u8 reserved_at_b3[0x6]; 1509 u8 go_back_n[0x1]; 1510 u8 shampo[0x1]; 1511 u8 reserved_at_bb[0x5]; 1512 1513 u8 max_sgl_for_optimized_performance[0x8]; 1514 u8 log_max_cq_sz[0x8]; 1515 u8 relaxed_ordering_write_umr[0x1]; 1516 u8 relaxed_ordering_read_umr[0x1]; 1517 u8 reserved_at_d2[0x7]; 1518 u8 virtio_net_device_emualtion_manager[0x1]; 1519 u8 virtio_blk_device_emualtion_manager[0x1]; 1520 u8 log_max_cq[0x5]; 1521 1522 u8 log_max_eq_sz[0x8]; 1523 u8 relaxed_ordering_write[0x1]; 1524 u8 relaxed_ordering_read_pci_enabled[0x1]; 1525 u8 log_max_mkey[0x6]; 1526 u8 reserved_at_f0[0x6]; 1527 u8 terminate_scatter_list_mkey[0x1]; 1528 u8 repeated_mkey[0x1]; 1529 u8 dump_fill_mkey[0x1]; 1530 u8 reserved_at_f9[0x2]; 1531 u8 fast_teardown[0x1]; 1532 u8 log_max_eq[0x4]; 1533 1534 u8 max_indirection[0x8]; 1535 u8 fixed_buffer_size[0x1]; 1536 u8 log_max_mrw_sz[0x7]; 1537 u8 force_teardown[0x1]; 1538 u8 reserved_at_111[0x1]; 1539 u8 log_max_bsf_list_size[0x6]; 1540 u8 umr_extended_translation_offset[0x1]; 1541 u8 null_mkey[0x1]; 1542 u8 log_max_klm_list_size[0x6]; 1543 1544 u8 reserved_at_120[0x2]; 1545 u8 qpc_extension[0x1]; 1546 u8 reserved_at_123[0x7]; 1547 u8 log_max_ra_req_dc[0x6]; 1548 u8 reserved_at_130[0x2]; 1549 u8 eth_wqe_too_small[0x1]; 1550 u8 reserved_at_133[0x6]; 1551 u8 vnic_env_cq_overrun[0x1]; 1552 u8 log_max_ra_res_dc[0x6]; 1553 1554 u8 reserved_at_140[0x5]; 1555 u8 release_all_pages[0x1]; 1556 u8 must_not_use[0x1]; 1557 u8 reserved_at_147[0x2]; 1558 u8 roce_accl[0x1]; 1559 u8 log_max_ra_req_qp[0x6]; 1560 u8 reserved_at_150[0xa]; 1561 u8 log_max_ra_res_qp[0x6]; 1562 1563 u8 end_pad[0x1]; 1564 u8 cc_query_allowed[0x1]; 1565 u8 cc_modify_allowed[0x1]; 1566 u8 start_pad[0x1]; 1567 u8 cache_line_128byte[0x1]; 1568 u8 reserved_at_165[0x4]; 1569 u8 rts2rts_qp_counters_set_id[0x1]; 1570 u8 reserved_at_16a[0x2]; 1571 u8 vnic_env_int_rq_oob[0x1]; 1572 u8 sbcam_reg[0x1]; 1573 u8 reserved_at_16e[0x1]; 1574 u8 qcam_reg[0x1]; 1575 u8 gid_table_size[0x10]; 1576 1577 u8 out_of_seq_cnt[0x1]; 1578 u8 vport_counters[0x1]; 1579 u8 retransmission_q_counters[0x1]; 1580 u8 debug[0x1]; 1581 u8 modify_rq_counter_set_id[0x1]; 1582 u8 rq_delay_drop[0x1]; 1583 u8 max_qp_cnt[0xa]; 1584 u8 pkey_table_size[0x10]; 1585 1586 u8 vport_group_manager[0x1]; 1587 u8 vhca_group_manager[0x1]; 1588 u8 ib_virt[0x1]; 1589 u8 eth_virt[0x1]; 1590 u8 vnic_env_queue_counters[0x1]; 1591 u8 ets[0x1]; 1592 u8 nic_flow_table[0x1]; 1593 u8 eswitch_manager[0x1]; 1594 u8 device_memory[0x1]; 1595 u8 mcam_reg[0x1]; 1596 u8 pcam_reg[0x1]; 1597 u8 local_ca_ack_delay[0x5]; 1598 u8 port_module_event[0x1]; 1599 u8 enhanced_error_q_counters[0x1]; 1600 u8 ports_check[0x1]; 1601 u8 reserved_at_1b3[0x1]; 1602 u8 disable_link_up[0x1]; 1603 u8 beacon_led[0x1]; 1604 u8 port_type[0x2]; 1605 u8 num_ports[0x8]; 1606 1607 u8 reserved_at_1c0[0x1]; 1608 u8 pps[0x1]; 1609 u8 pps_modify[0x1]; 1610 u8 log_max_msg[0x5]; 1611 u8 reserved_at_1c8[0x4]; 1612 u8 max_tc[0x4]; 1613 u8 temp_warn_event[0x1]; 1614 u8 dcbx[0x1]; 1615 u8 general_notification_event[0x1]; 1616 u8 reserved_at_1d3[0x2]; 1617 u8 fpga[0x1]; 1618 u8 rol_s[0x1]; 1619 u8 rol_g[0x1]; 1620 u8 reserved_at_1d8[0x1]; 1621 u8 wol_s[0x1]; 1622 u8 wol_g[0x1]; 1623 u8 wol_a[0x1]; 1624 u8 wol_b[0x1]; 1625 u8 wol_m[0x1]; 1626 u8 wol_u[0x1]; 1627 u8 wol_p[0x1]; 1628 1629 u8 stat_rate_support[0x10]; 1630 u8 reserved_at_1f0[0x1]; 1631 u8 pci_sync_for_fw_update_event[0x1]; 1632 u8 reserved_at_1f2[0x6]; 1633 u8 init2_lag_tx_port_affinity[0x1]; 1634 u8 reserved_at_1fa[0x3]; 1635 u8 cqe_version[0x4]; 1636 1637 u8 compact_address_vector[0x1]; 1638 u8 striding_rq[0x1]; 1639 u8 reserved_at_202[0x1]; 1640 u8 ipoib_enhanced_offloads[0x1]; 1641 u8 ipoib_basic_offloads[0x1]; 1642 u8 reserved_at_205[0x1]; 1643 u8 repeated_block_disabled[0x1]; 1644 u8 umr_modify_entity_size_disabled[0x1]; 1645 u8 umr_modify_atomic_disabled[0x1]; 1646 u8 umr_indirect_mkey_disabled[0x1]; 1647 u8 umr_fence[0x2]; 1648 u8 dc_req_scat_data_cqe[0x1]; 1649 u8 reserved_at_20d[0x2]; 1650 u8 drain_sigerr[0x1]; 1651 u8 cmdif_checksum[0x2]; 1652 u8 sigerr_cqe[0x1]; 1653 u8 reserved_at_213[0x1]; 1654 u8 wq_signature[0x1]; 1655 u8 sctr_data_cqe[0x1]; 1656 u8 reserved_at_216[0x1]; 1657 u8 sho[0x1]; 1658 u8 tph[0x1]; 1659 u8 rf[0x1]; 1660 u8 dct[0x1]; 1661 u8 qos[0x1]; 1662 u8 eth_net_offloads[0x1]; 1663 u8 roce[0x1]; 1664 u8 atomic[0x1]; 1665 u8 reserved_at_21f[0x1]; 1666 1667 u8 cq_oi[0x1]; 1668 u8 cq_resize[0x1]; 1669 u8 cq_moderation[0x1]; 1670 u8 reserved_at_223[0x3]; 1671 u8 cq_eq_remap[0x1]; 1672 u8 pg[0x1]; 1673 u8 block_lb_mc[0x1]; 1674 u8 reserved_at_229[0x1]; 1675 u8 scqe_break_moderation[0x1]; 1676 u8 cq_period_start_from_cqe[0x1]; 1677 u8 cd[0x1]; 1678 u8 reserved_at_22d[0x1]; 1679 u8 apm[0x1]; 1680 u8 vector_calc[0x1]; 1681 u8 umr_ptr_rlky[0x1]; 1682 u8 imaicl[0x1]; 1683 u8 qp_packet_based[0x1]; 1684 u8 reserved_at_233[0x3]; 1685 u8 qkv[0x1]; 1686 u8 pkv[0x1]; 1687 u8 set_deth_sqpn[0x1]; 1688 u8 reserved_at_239[0x3]; 1689 u8 xrc[0x1]; 1690 u8 ud[0x1]; 1691 u8 uc[0x1]; 1692 u8 rc[0x1]; 1693 1694 u8 uar_4k[0x1]; 1695 u8 reserved_at_241[0x7]; 1696 u8 fl_rc_qp_when_roce_disabled[0x1]; 1697 u8 regexp_params[0x1]; 1698 u8 uar_sz[0x6]; 1699 u8 port_selection_cap[0x1]; 1700 u8 reserved_at_251[0x1]; 1701 u8 umem_uid_0[0x1]; 1702 u8 reserved_at_253[0x5]; 1703 u8 log_pg_sz[0x8]; 1704 1705 u8 bf[0x1]; 1706 u8 driver_version[0x1]; 1707 u8 pad_tx_eth_packet[0x1]; 1708 u8 reserved_at_263[0x3]; 1709 u8 mkey_by_name[0x1]; 1710 u8 reserved_at_267[0x4]; 1711 1712 u8 log_bf_reg_size[0x5]; 1713 1714 u8 reserved_at_270[0x3]; 1715 u8 qp_error_syndrome[0x1]; 1716 u8 reserved_at_274[0x2]; 1717 u8 lag_dct[0x2]; 1718 u8 lag_tx_port_affinity[0x1]; 1719 u8 lag_native_fdb_selection[0x1]; 1720 u8 reserved_at_27a[0x1]; 1721 u8 lag_master[0x1]; 1722 u8 num_lag_ports[0x4]; 1723 1724 u8 reserved_at_280[0x10]; 1725 u8 max_wqe_sz_sq[0x10]; 1726 1727 u8 reserved_at_2a0[0x10]; 1728 u8 max_wqe_sz_rq[0x10]; 1729 1730 u8 max_flow_counter_31_16[0x10]; 1731 u8 max_wqe_sz_sq_dc[0x10]; 1732 1733 u8 reserved_at_2e0[0x7]; 1734 u8 max_qp_mcg[0x19]; 1735 1736 u8 reserved_at_300[0x10]; 1737 u8 flow_counter_bulk_alloc[0x8]; 1738 u8 log_max_mcg[0x8]; 1739 1740 u8 reserved_at_320[0x3]; 1741 u8 log_max_transport_domain[0x5]; 1742 u8 reserved_at_328[0x2]; 1743 u8 relaxed_ordering_read[0x1]; 1744 u8 log_max_pd[0x5]; 1745 u8 reserved_at_330[0x6]; 1746 u8 pci_sync_for_fw_update_with_driver_unload[0x1]; 1747 u8 vnic_env_cnt_steering_fail[0x1]; 1748 u8 vport_counter_local_loopback[0x1]; 1749 u8 q_counter_aggregation[0x1]; 1750 u8 q_counter_other_vport[0x1]; 1751 u8 log_max_xrcd[0x5]; 1752 1753 u8 nic_receive_steering_discard[0x1]; 1754 u8 receive_discard_vport_down[0x1]; 1755 u8 transmit_discard_vport_down[0x1]; 1756 u8 eq_overrun_count[0x1]; 1757 u8 reserved_at_344[0x1]; 1758 u8 invalid_command_count[0x1]; 1759 u8 quota_exceeded_count[0x1]; 1760 u8 reserved_at_347[0x1]; 1761 u8 log_max_flow_counter_bulk[0x8]; 1762 u8 max_flow_counter_15_0[0x10]; 1763 1764 1765 u8 reserved_at_360[0x3]; 1766 u8 log_max_rq[0x5]; 1767 u8 reserved_at_368[0x3]; 1768 u8 log_max_sq[0x5]; 1769 u8 reserved_at_370[0x3]; 1770 u8 log_max_tir[0x5]; 1771 u8 reserved_at_378[0x3]; 1772 u8 log_max_tis[0x5]; 1773 1774 u8 basic_cyclic_rcv_wqe[0x1]; 1775 u8 reserved_at_381[0x2]; 1776 u8 log_max_rmp[0x5]; 1777 u8 reserved_at_388[0x3]; 1778 u8 log_max_rqt[0x5]; 1779 u8 reserved_at_390[0x3]; 1780 u8 log_max_rqt_size[0x5]; 1781 u8 reserved_at_398[0x3]; 1782 u8 log_max_tis_per_sq[0x5]; 1783 1784 u8 ext_stride_num_range[0x1]; 1785 u8 roce_rw_supported[0x1]; 1786 u8 log_max_current_uc_list_wr_supported[0x1]; 1787 u8 log_max_stride_sz_rq[0x5]; 1788 u8 reserved_at_3a8[0x3]; 1789 u8 log_min_stride_sz_rq[0x5]; 1790 u8 reserved_at_3b0[0x3]; 1791 u8 log_max_stride_sz_sq[0x5]; 1792 u8 reserved_at_3b8[0x3]; 1793 u8 log_min_stride_sz_sq[0x5]; 1794 1795 u8 hairpin[0x1]; 1796 u8 reserved_at_3c1[0x2]; 1797 u8 log_max_hairpin_queues[0x5]; 1798 u8 reserved_at_3c8[0x3]; 1799 u8 log_max_hairpin_wq_data_sz[0x5]; 1800 u8 reserved_at_3d0[0x3]; 1801 u8 log_max_hairpin_num_packets[0x5]; 1802 u8 reserved_at_3d8[0x3]; 1803 u8 log_max_wq_sz[0x5]; 1804 1805 u8 nic_vport_change_event[0x1]; 1806 u8 disable_local_lb_uc[0x1]; 1807 u8 disable_local_lb_mc[0x1]; 1808 u8 log_min_hairpin_wq_data_sz[0x5]; 1809 u8 reserved_at_3e8[0x1]; 1810 u8 silent_mode[0x1]; 1811 u8 vhca_state[0x1]; 1812 u8 log_max_vlan_list[0x5]; 1813 u8 reserved_at_3f0[0x3]; 1814 u8 log_max_current_mc_list[0x5]; 1815 u8 reserved_at_3f8[0x3]; 1816 u8 log_max_current_uc_list[0x5]; 1817 1818 u8 general_obj_types[0x40]; 1819 1820 u8 sq_ts_format[0x2]; 1821 u8 rq_ts_format[0x2]; 1822 u8 steering_format_version[0x4]; 1823 u8 create_qp_start_hint[0x18]; 1824 1825 u8 reserved_at_460[0x1]; 1826 u8 ats[0x1]; 1827 u8 cross_vhca_rqt[0x1]; 1828 u8 log_max_uctx[0x5]; 1829 u8 reserved_at_468[0x1]; 1830 u8 crypto[0x1]; 1831 u8 ipsec_offload[0x1]; 1832 u8 log_max_umem[0x5]; 1833 u8 max_num_eqs[0x10]; 1834 1835 u8 reserved_at_480[0x1]; 1836 u8 tls_tx[0x1]; 1837 u8 tls_rx[0x1]; 1838 u8 log_max_l2_table[0x5]; 1839 u8 reserved_at_488[0x8]; 1840 u8 log_uar_page_sz[0x10]; 1841 1842 u8 reserved_at_4a0[0x20]; 1843 u8 device_frequency_mhz[0x20]; 1844 u8 device_frequency_khz[0x20]; 1845 1846 u8 reserved_at_500[0x20]; 1847 u8 num_of_uars_per_page[0x20]; 1848 1849 u8 flex_parser_protocols[0x20]; 1850 1851 u8 max_geneve_tlv_options[0x8]; 1852 u8 reserved_at_568[0x3]; 1853 u8 max_geneve_tlv_option_data_len[0x5]; 1854 u8 reserved_at_570[0x9]; 1855 u8 adv_virtualization[0x1]; 1856 u8 reserved_at_57a[0x6]; 1857 1858 u8 reserved_at_580[0xb]; 1859 u8 log_max_dci_stream_channels[0x5]; 1860 u8 reserved_at_590[0x3]; 1861 u8 log_max_dci_errored_streams[0x5]; 1862 u8 reserved_at_598[0x8]; 1863 1864 u8 reserved_at_5a0[0x10]; 1865 u8 enhanced_cqe_compression[0x1]; 1866 u8 reserved_at_5b1[0x2]; 1867 u8 log_max_dek[0x5]; 1868 u8 reserved_at_5b8[0x4]; 1869 u8 mini_cqe_resp_stride_index[0x1]; 1870 u8 cqe_128_always[0x1]; 1871 u8 cqe_compression_128[0x1]; 1872 u8 cqe_compression[0x1]; 1873 1874 u8 cqe_compression_timeout[0x10]; 1875 u8 cqe_compression_max_num[0x10]; 1876 1877 u8 reserved_at_5e0[0x8]; 1878 u8 flex_parser_id_gtpu_dw_0[0x4]; 1879 u8 reserved_at_5ec[0x4]; 1880 u8 tag_matching[0x1]; 1881 u8 rndv_offload_rc[0x1]; 1882 u8 rndv_offload_dc[0x1]; 1883 u8 log_tag_matching_list_sz[0x5]; 1884 u8 reserved_at_5f8[0x3]; 1885 u8 log_max_xrq[0x5]; 1886 1887 u8 affiliate_nic_vport_criteria[0x8]; 1888 u8 native_port_num[0x8]; 1889 u8 num_vhca_ports[0x8]; 1890 u8 flex_parser_id_gtpu_teid[0x4]; 1891 u8 reserved_at_61c[0x2]; 1892 u8 sw_owner_id[0x1]; 1893 u8 reserved_at_61f[0x1]; 1894 1895 u8 max_num_of_monitor_counters[0x10]; 1896 u8 num_ppcnt_monitor_counters[0x10]; 1897 1898 u8 max_num_sf[0x10]; 1899 u8 num_q_monitor_counters[0x10]; 1900 1901 u8 reserved_at_660[0x20]; 1902 1903 u8 sf[0x1]; 1904 u8 sf_set_partition[0x1]; 1905 u8 reserved_at_682[0x1]; 1906 u8 log_max_sf[0x5]; 1907 u8 apu[0x1]; 1908 u8 reserved_at_689[0x4]; 1909 u8 migration[0x1]; 1910 u8 reserved_at_68e[0x2]; 1911 u8 log_min_sf_size[0x8]; 1912 u8 max_num_sf_partitions[0x8]; 1913 1914 u8 uctx_cap[0x20]; 1915 1916 u8 reserved_at_6c0[0x4]; 1917 u8 flex_parser_id_geneve_tlv_option_0[0x4]; 1918 u8 flex_parser_id_icmp_dw1[0x4]; 1919 u8 flex_parser_id_icmp_dw0[0x4]; 1920 u8 flex_parser_id_icmpv6_dw1[0x4]; 1921 u8 flex_parser_id_icmpv6_dw0[0x4]; 1922 u8 flex_parser_id_outer_first_mpls_over_gre[0x4]; 1923 u8 flex_parser_id_outer_first_mpls_over_udp_label[0x4]; 1924 1925 u8 max_num_match_definer[0x10]; 1926 u8 sf_base_id[0x10]; 1927 1928 u8 flex_parser_id_gtpu_dw_2[0x4]; 1929 u8 flex_parser_id_gtpu_first_ext_dw_0[0x4]; 1930 u8 num_total_dynamic_vf_msix[0x18]; 1931 u8 reserved_at_720[0x14]; 1932 u8 dynamic_msix_table_size[0xc]; 1933 u8 reserved_at_740[0xc]; 1934 u8 min_dynamic_vf_msix_table_size[0x4]; 1935 u8 reserved_at_750[0x4]; 1936 u8 max_dynamic_vf_msix_table_size[0xc]; 1937 1938 u8 reserved_at_760[0x3]; 1939 u8 log_max_num_header_modify_argument[0x5]; 1940 u8 reserved_at_768[0x4]; 1941 u8 log_header_modify_argument_granularity[0x4]; 1942 u8 reserved_at_770[0x3]; 1943 u8 log_header_modify_argument_max_alloc[0x5]; 1944 u8 reserved_at_778[0x8]; 1945 1946 u8 vhca_tunnel_commands[0x40]; 1947 u8 match_definer_format_supported[0x40]; 1948 }; 1949 1950 enum { 1951 MLX5_CROSS_VHCA_OBJ_TO_OBJ_SUPPORTED_LOCAL_FLOW_TABLE_TO_REMOTE_FLOW_TABLE_MISS = 0x80000, 1952 MLX5_CROSS_VHCA_OBJ_TO_OBJ_SUPPORTED_LOCAL_FLOW_TABLE_ROOT_TO_REMOTE_FLOW_TABLE = (1ULL << 20), 1953 }; 1954 1955 enum { 1956 MLX5_ALLOWED_OBJ_FOR_OTHER_VHCA_ACCESS_FLOW_TABLE = 0x200, 1957 }; 1958 1959 struct mlx5_ifc_cmd_hca_cap_2_bits { 1960 u8 reserved_at_0[0x80]; 1961 1962 u8 migratable[0x1]; 1963 u8 reserved_at_81[0x1f]; 1964 1965 u8 max_reformat_insert_size[0x8]; 1966 u8 max_reformat_insert_offset[0x8]; 1967 u8 max_reformat_remove_size[0x8]; 1968 u8 max_reformat_remove_offset[0x8]; 1969 1970 u8 reserved_at_c0[0x8]; 1971 u8 migration_multi_load[0x1]; 1972 u8 migration_tracking_state[0x1]; 1973 u8 reserved_at_ca[0x6]; 1974 u8 migration_in_chunks[0x1]; 1975 u8 reserved_at_d1[0xf]; 1976 1977 u8 cross_vhca_object_to_object_supported[0x20]; 1978 1979 u8 allowed_object_for_other_vhca_access[0x40]; 1980 1981 u8 reserved_at_140[0x60]; 1982 1983 u8 flow_table_type_2_type[0x8]; 1984 u8 reserved_at_1a8[0x3]; 1985 u8 log_min_mkey_entity_size[0x5]; 1986 u8 reserved_at_1b0[0x10]; 1987 1988 u8 reserved_at_1c0[0x60]; 1989 1990 u8 reserved_at_220[0x1]; 1991 u8 sw_vhca_id_valid[0x1]; 1992 u8 sw_vhca_id[0xe]; 1993 u8 reserved_at_230[0x10]; 1994 1995 u8 reserved_at_240[0xb]; 1996 u8 ts_cqe_metadata_size2wqe_counter[0x5]; 1997 u8 reserved_at_250[0x10]; 1998 1999 u8 reserved_at_260[0x120]; 2000 u8 reserved_at_380[0x10]; 2001 u8 ec_vf_vport_base[0x10]; 2002 2003 u8 reserved_at_3a0[0x10]; 2004 u8 max_rqt_vhca_id[0x10]; 2005 2006 u8 reserved_at_3c0[0x440]; 2007 }; 2008 2009 enum mlx5_ifc_flow_destination_type { 2010 MLX5_IFC_FLOW_DESTINATION_TYPE_VPORT = 0x0, 2011 MLX5_IFC_FLOW_DESTINATION_TYPE_FLOW_TABLE = 0x1, 2012 MLX5_IFC_FLOW_DESTINATION_TYPE_TIR = 0x2, 2013 MLX5_IFC_FLOW_DESTINATION_TYPE_FLOW_SAMPLER = 0x6, 2014 MLX5_IFC_FLOW_DESTINATION_TYPE_UPLINK = 0x8, 2015 MLX5_IFC_FLOW_DESTINATION_TYPE_TABLE_TYPE = 0xA, 2016 }; 2017 2018 enum mlx5_flow_table_miss_action { 2019 MLX5_FLOW_TABLE_MISS_ACTION_DEF, 2020 MLX5_FLOW_TABLE_MISS_ACTION_FWD, 2021 MLX5_FLOW_TABLE_MISS_ACTION_SWITCH_DOMAIN, 2022 }; 2023 2024 struct mlx5_ifc_dest_format_struct_bits { 2025 u8 destination_type[0x8]; 2026 u8 destination_id[0x18]; 2027 2028 u8 destination_eswitch_owner_vhca_id_valid[0x1]; 2029 u8 packet_reformat[0x1]; 2030 u8 reserved_at_22[0x6]; 2031 u8 destination_table_type[0x8]; 2032 u8 destination_eswitch_owner_vhca_id[0x10]; 2033 }; 2034 2035 struct mlx5_ifc_flow_counter_list_bits { 2036 u8 flow_counter_id[0x20]; 2037 2038 u8 reserved_at_20[0x20]; 2039 }; 2040 2041 struct mlx5_ifc_extended_dest_format_bits { 2042 struct mlx5_ifc_dest_format_struct_bits destination_entry; 2043 2044 u8 packet_reformat_id[0x20]; 2045 2046 u8 reserved_at_60[0x20]; 2047 }; 2048 2049 union mlx5_ifc_dest_format_struct_flow_counter_list_auto_bits { 2050 struct mlx5_ifc_extended_dest_format_bits extended_dest_format; 2051 struct mlx5_ifc_flow_counter_list_bits flow_counter_list; 2052 }; 2053 2054 struct mlx5_ifc_fte_match_param_bits { 2055 struct mlx5_ifc_fte_match_set_lyr_2_4_bits outer_headers; 2056 2057 struct mlx5_ifc_fte_match_set_misc_bits misc_parameters; 2058 2059 struct mlx5_ifc_fte_match_set_lyr_2_4_bits inner_headers; 2060 2061 struct mlx5_ifc_fte_match_set_misc2_bits misc_parameters_2; 2062 2063 struct mlx5_ifc_fte_match_set_misc3_bits misc_parameters_3; 2064 2065 struct mlx5_ifc_fte_match_set_misc4_bits misc_parameters_4; 2066 2067 struct mlx5_ifc_fte_match_set_misc5_bits misc_parameters_5; 2068 2069 u8 reserved_at_e00[0x200]; 2070 }; 2071 2072 enum { 2073 MLX5_RX_HASH_FIELD_SELECT_SELECTED_FIELDS_SRC_IP = 0x0, 2074 MLX5_RX_HASH_FIELD_SELECT_SELECTED_FIELDS_DST_IP = 0x1, 2075 MLX5_RX_HASH_FIELD_SELECT_SELECTED_FIELDS_L4_SPORT = 0x2, 2076 MLX5_RX_HASH_FIELD_SELECT_SELECTED_FIELDS_L4_DPORT = 0x3, 2077 MLX5_RX_HASH_FIELD_SELECT_SELECTED_FIELDS_IPSEC_SPI = 0x4, 2078 }; 2079 2080 struct mlx5_ifc_rx_hash_field_select_bits { 2081 u8 l3_prot_type[0x1]; 2082 u8 l4_prot_type[0x1]; 2083 u8 selected_fields[0x1e]; 2084 }; 2085 2086 enum { 2087 MLX5_WQ_WQ_TYPE_WQ_LINKED_LIST = 0x0, 2088 MLX5_WQ_WQ_TYPE_WQ_CYCLIC = 0x1, 2089 }; 2090 2091 enum { 2092 MLX5_WQ_END_PADDING_MODE_END_PAD_NONE = 0x0, 2093 MLX5_WQ_END_PADDING_MODE_END_PAD_ALIGN = 0x1, 2094 }; 2095 2096 struct mlx5_ifc_wq_bits { 2097 u8 wq_type[0x4]; 2098 u8 wq_signature[0x1]; 2099 u8 end_padding_mode[0x2]; 2100 u8 cd_slave[0x1]; 2101 u8 reserved_at_8[0x18]; 2102 2103 u8 hds_skip_first_sge[0x1]; 2104 u8 log2_hds_buf_size[0x3]; 2105 u8 reserved_at_24[0x7]; 2106 u8 page_offset[0x5]; 2107 u8 lwm[0x10]; 2108 2109 u8 reserved_at_40[0x8]; 2110 u8 pd[0x18]; 2111 2112 u8 reserved_at_60[0x8]; 2113 u8 uar_page[0x18]; 2114 2115 u8 dbr_addr[0x40]; 2116 2117 u8 hw_counter[0x20]; 2118 2119 u8 sw_counter[0x20]; 2120 2121 u8 reserved_at_100[0xc]; 2122 u8 log_wq_stride[0x4]; 2123 u8 reserved_at_110[0x3]; 2124 u8 log_wq_pg_sz[0x5]; 2125 u8 reserved_at_118[0x3]; 2126 u8 log_wq_sz[0x5]; 2127 2128 u8 dbr_umem_valid[0x1]; 2129 u8 wq_umem_valid[0x1]; 2130 u8 reserved_at_122[0x1]; 2131 u8 log_hairpin_num_packets[0x5]; 2132 u8 reserved_at_128[0x3]; 2133 u8 log_hairpin_data_sz[0x5]; 2134 2135 u8 reserved_at_130[0x4]; 2136 u8 log_wqe_num_of_strides[0x4]; 2137 u8 two_byte_shift_en[0x1]; 2138 u8 reserved_at_139[0x4]; 2139 u8 log_wqe_stride_size[0x3]; 2140 2141 u8 reserved_at_140[0x80]; 2142 2143 u8 headers_mkey[0x20]; 2144 2145 u8 shampo_enable[0x1]; 2146 u8 reserved_at_1e1[0x4]; 2147 u8 log_reservation_size[0x3]; 2148 u8 reserved_at_1e8[0x5]; 2149 u8 log_max_num_of_packets_per_reservation[0x3]; 2150 u8 reserved_at_1f0[0x6]; 2151 u8 log_headers_entry_size[0x2]; 2152 u8 reserved_at_1f8[0x4]; 2153 u8 log_headers_buffer_entry_num[0x4]; 2154 2155 u8 reserved_at_200[0x400]; 2156 2157 struct mlx5_ifc_cmd_pas_bits pas[]; 2158 }; 2159 2160 struct mlx5_ifc_rq_num_bits { 2161 u8 reserved_at_0[0x8]; 2162 u8 rq_num[0x18]; 2163 }; 2164 2165 struct mlx5_ifc_rq_vhca_bits { 2166 u8 reserved_at_0[0x8]; 2167 u8 rq_num[0x18]; 2168 u8 reserved_at_20[0x10]; 2169 u8 rq_vhca_id[0x10]; 2170 }; 2171 2172 struct mlx5_ifc_mac_address_layout_bits { 2173 u8 reserved_at_0[0x10]; 2174 u8 mac_addr_47_32[0x10]; 2175 2176 u8 mac_addr_31_0[0x20]; 2177 }; 2178 2179 struct mlx5_ifc_vlan_layout_bits { 2180 u8 reserved_at_0[0x14]; 2181 u8 vlan[0x0c]; 2182 2183 u8 reserved_at_20[0x20]; 2184 }; 2185 2186 struct mlx5_ifc_cong_control_r_roce_ecn_np_bits { 2187 u8 reserved_at_0[0xa0]; 2188 2189 u8 min_time_between_cnps[0x20]; 2190 2191 u8 reserved_at_c0[0x12]; 2192 u8 cnp_dscp[0x6]; 2193 u8 reserved_at_d8[0x4]; 2194 u8 cnp_prio_mode[0x1]; 2195 u8 cnp_802p_prio[0x3]; 2196 2197 u8 reserved_at_e0[0x720]; 2198 }; 2199 2200 struct mlx5_ifc_cong_control_r_roce_ecn_rp_bits { 2201 u8 reserved_at_0[0x60]; 2202 2203 u8 reserved_at_60[0x4]; 2204 u8 clamp_tgt_rate[0x1]; 2205 u8 reserved_at_65[0x3]; 2206 u8 clamp_tgt_rate_after_time_inc[0x1]; 2207 u8 reserved_at_69[0x17]; 2208 2209 u8 reserved_at_80[0x20]; 2210 2211 u8 rpg_time_reset[0x20]; 2212 2213 u8 rpg_byte_reset[0x20]; 2214 2215 u8 rpg_threshold[0x20]; 2216 2217 u8 rpg_max_rate[0x20]; 2218 2219 u8 rpg_ai_rate[0x20]; 2220 2221 u8 rpg_hai_rate[0x20]; 2222 2223 u8 rpg_gd[0x20]; 2224 2225 u8 rpg_min_dec_fac[0x20]; 2226 2227 u8 rpg_min_rate[0x20]; 2228 2229 u8 reserved_at_1c0[0xe0]; 2230 2231 u8 rate_to_set_on_first_cnp[0x20]; 2232 2233 u8 dce_tcp_g[0x20]; 2234 2235 u8 dce_tcp_rtt[0x20]; 2236 2237 u8 rate_reduce_monitor_period[0x20]; 2238 2239 u8 reserved_at_320[0x20]; 2240 2241 u8 initial_alpha_value[0x20]; 2242 2243 u8 reserved_at_360[0x4a0]; 2244 }; 2245 2246 struct mlx5_ifc_cong_control_r_roce_general_bits { 2247 u8 reserved_at_0[0x80]; 2248 2249 u8 reserved_at_80[0x10]; 2250 u8 rtt_resp_dscp_valid[0x1]; 2251 u8 reserved_at_91[0x9]; 2252 u8 rtt_resp_dscp[0x6]; 2253 2254 u8 reserved_at_a0[0x760]; 2255 }; 2256 2257 struct mlx5_ifc_cong_control_802_1qau_rp_bits { 2258 u8 reserved_at_0[0x80]; 2259 2260 u8 rppp_max_rps[0x20]; 2261 2262 u8 rpg_time_reset[0x20]; 2263 2264 u8 rpg_byte_reset[0x20]; 2265 2266 u8 rpg_threshold[0x20]; 2267 2268 u8 rpg_max_rate[0x20]; 2269 2270 u8 rpg_ai_rate[0x20]; 2271 2272 u8 rpg_hai_rate[0x20]; 2273 2274 u8 rpg_gd[0x20]; 2275 2276 u8 rpg_min_dec_fac[0x20]; 2277 2278 u8 rpg_min_rate[0x20]; 2279 2280 u8 reserved_at_1c0[0x640]; 2281 }; 2282 2283 enum { 2284 MLX5_RESIZE_FIELD_SELECT_RESIZE_FIELD_SELECT_LOG_CQ_SIZE = 0x1, 2285 MLX5_RESIZE_FIELD_SELECT_RESIZE_FIELD_SELECT_PAGE_OFFSET = 0x2, 2286 MLX5_RESIZE_FIELD_SELECT_RESIZE_FIELD_SELECT_LOG_PAGE_SIZE = 0x4, 2287 }; 2288 2289 struct mlx5_ifc_resize_field_select_bits { 2290 u8 resize_field_select[0x20]; 2291 }; 2292 2293 struct mlx5_ifc_resource_dump_bits { 2294 u8 more_dump[0x1]; 2295 u8 inline_dump[0x1]; 2296 u8 reserved_at_2[0xa]; 2297 u8 seq_num[0x4]; 2298 u8 segment_type[0x10]; 2299 2300 u8 reserved_at_20[0x10]; 2301 u8 vhca_id[0x10]; 2302 2303 u8 index1[0x20]; 2304 2305 u8 index2[0x20]; 2306 2307 u8 num_of_obj1[0x10]; 2308 u8 num_of_obj2[0x10]; 2309 2310 u8 reserved_at_a0[0x20]; 2311 2312 u8 device_opaque[0x40]; 2313 2314 u8 mkey[0x20]; 2315 2316 u8 size[0x20]; 2317 2318 u8 address[0x40]; 2319 2320 u8 inline_data[52][0x20]; 2321 }; 2322 2323 struct mlx5_ifc_resource_dump_menu_record_bits { 2324 u8 reserved_at_0[0x4]; 2325 u8 num_of_obj2_supports_active[0x1]; 2326 u8 num_of_obj2_supports_all[0x1]; 2327 u8 must_have_num_of_obj2[0x1]; 2328 u8 support_num_of_obj2[0x1]; 2329 u8 num_of_obj1_supports_active[0x1]; 2330 u8 num_of_obj1_supports_all[0x1]; 2331 u8 must_have_num_of_obj1[0x1]; 2332 u8 support_num_of_obj1[0x1]; 2333 u8 must_have_index2[0x1]; 2334 u8 support_index2[0x1]; 2335 u8 must_have_index1[0x1]; 2336 u8 support_index1[0x1]; 2337 u8 segment_type[0x10]; 2338 2339 u8 segment_name[4][0x20]; 2340 2341 u8 index1_name[4][0x20]; 2342 2343 u8 index2_name[4][0x20]; 2344 }; 2345 2346 struct mlx5_ifc_resource_dump_segment_header_bits { 2347 u8 length_dw[0x10]; 2348 u8 segment_type[0x10]; 2349 }; 2350 2351 struct mlx5_ifc_resource_dump_command_segment_bits { 2352 struct mlx5_ifc_resource_dump_segment_header_bits segment_header; 2353 2354 u8 segment_called[0x10]; 2355 u8 vhca_id[0x10]; 2356 2357 u8 index1[0x20]; 2358 2359 u8 index2[0x20]; 2360 2361 u8 num_of_obj1[0x10]; 2362 u8 num_of_obj2[0x10]; 2363 }; 2364 2365 struct mlx5_ifc_resource_dump_error_segment_bits { 2366 struct mlx5_ifc_resource_dump_segment_header_bits segment_header; 2367 2368 u8 reserved_at_20[0x10]; 2369 u8 syndrome_id[0x10]; 2370 2371 u8 reserved_at_40[0x40]; 2372 2373 u8 error[8][0x20]; 2374 }; 2375 2376 struct mlx5_ifc_resource_dump_info_segment_bits { 2377 struct mlx5_ifc_resource_dump_segment_header_bits segment_header; 2378 2379 u8 reserved_at_20[0x18]; 2380 u8 dump_version[0x8]; 2381 2382 u8 hw_version[0x20]; 2383 2384 u8 fw_version[0x20]; 2385 }; 2386 2387 struct mlx5_ifc_resource_dump_menu_segment_bits { 2388 struct mlx5_ifc_resource_dump_segment_header_bits segment_header; 2389 2390 u8 reserved_at_20[0x10]; 2391 u8 num_of_records[0x10]; 2392 2393 struct mlx5_ifc_resource_dump_menu_record_bits record[]; 2394 }; 2395 2396 struct mlx5_ifc_resource_dump_resource_segment_bits { 2397 struct mlx5_ifc_resource_dump_segment_header_bits segment_header; 2398 2399 u8 reserved_at_20[0x20]; 2400 2401 u8 index1[0x20]; 2402 2403 u8 index2[0x20]; 2404 2405 u8 payload[][0x20]; 2406 }; 2407 2408 struct mlx5_ifc_resource_dump_terminate_segment_bits { 2409 struct mlx5_ifc_resource_dump_segment_header_bits segment_header; 2410 }; 2411 2412 struct mlx5_ifc_menu_resource_dump_response_bits { 2413 struct mlx5_ifc_resource_dump_info_segment_bits info; 2414 struct mlx5_ifc_resource_dump_command_segment_bits cmd; 2415 struct mlx5_ifc_resource_dump_menu_segment_bits menu; 2416 struct mlx5_ifc_resource_dump_terminate_segment_bits terminate; 2417 }; 2418 2419 enum { 2420 MLX5_MODIFY_FIELD_SELECT_MODIFY_FIELD_SELECT_CQ_PERIOD = 0x1, 2421 MLX5_MODIFY_FIELD_SELECT_MODIFY_FIELD_SELECT_CQ_MAX_COUNT = 0x2, 2422 MLX5_MODIFY_FIELD_SELECT_MODIFY_FIELD_SELECT_OI = 0x4, 2423 MLX5_MODIFY_FIELD_SELECT_MODIFY_FIELD_SELECT_C_EQN = 0x8, 2424 }; 2425 2426 struct mlx5_ifc_modify_field_select_bits { 2427 u8 modify_field_select[0x20]; 2428 }; 2429 2430 struct mlx5_ifc_field_select_r_roce_np_bits { 2431 u8 field_select_r_roce_np[0x20]; 2432 }; 2433 2434 struct mlx5_ifc_field_select_r_roce_rp_bits { 2435 u8 field_select_r_roce_rp[0x20]; 2436 }; 2437 2438 enum { 2439 MLX5_FIELD_SELECT_802_1QAU_RP_FIELD_SELECT_8021QAURP_RPPP_MAX_RPS = 0x4, 2440 MLX5_FIELD_SELECT_802_1QAU_RP_FIELD_SELECT_8021QAURP_RPG_TIME_RESET = 0x8, 2441 MLX5_FIELD_SELECT_802_1QAU_RP_FIELD_SELECT_8021QAURP_RPG_BYTE_RESET = 0x10, 2442 MLX5_FIELD_SELECT_802_1QAU_RP_FIELD_SELECT_8021QAURP_RPG_THRESHOLD = 0x20, 2443 MLX5_FIELD_SELECT_802_1QAU_RP_FIELD_SELECT_8021QAURP_RPG_MAX_RATE = 0x40, 2444 MLX5_FIELD_SELECT_802_1QAU_RP_FIELD_SELECT_8021QAURP_RPG_AI_RATE = 0x80, 2445 MLX5_FIELD_SELECT_802_1QAU_RP_FIELD_SELECT_8021QAURP_RPG_HAI_RATE = 0x100, 2446 MLX5_FIELD_SELECT_802_1QAU_RP_FIELD_SELECT_8021QAURP_RPG_GD = 0x200, 2447 MLX5_FIELD_SELECT_802_1QAU_RP_FIELD_SELECT_8021QAURP_RPG_MIN_DEC_FAC = 0x400, 2448 MLX5_FIELD_SELECT_802_1QAU_RP_FIELD_SELECT_8021QAURP_RPG_MIN_RATE = 0x800, 2449 }; 2450 2451 struct mlx5_ifc_field_select_802_1qau_rp_bits { 2452 u8 field_select_8021qaurp[0x20]; 2453 }; 2454 2455 struct mlx5_ifc_phys_layer_cntrs_bits { 2456 u8 time_since_last_clear_high[0x20]; 2457 2458 u8 time_since_last_clear_low[0x20]; 2459 2460 u8 symbol_errors_high[0x20]; 2461 2462 u8 symbol_errors_low[0x20]; 2463 2464 u8 sync_headers_errors_high[0x20]; 2465 2466 u8 sync_headers_errors_low[0x20]; 2467 2468 u8 edpl_bip_errors_lane0_high[0x20]; 2469 2470 u8 edpl_bip_errors_lane0_low[0x20]; 2471 2472 u8 edpl_bip_errors_lane1_high[0x20]; 2473 2474 u8 edpl_bip_errors_lane1_low[0x20]; 2475 2476 u8 edpl_bip_errors_lane2_high[0x20]; 2477 2478 u8 edpl_bip_errors_lane2_low[0x20]; 2479 2480 u8 edpl_bip_errors_lane3_high[0x20]; 2481 2482 u8 edpl_bip_errors_lane3_low[0x20]; 2483 2484 u8 fc_fec_corrected_blocks_lane0_high[0x20]; 2485 2486 u8 fc_fec_corrected_blocks_lane0_low[0x20]; 2487 2488 u8 fc_fec_corrected_blocks_lane1_high[0x20]; 2489 2490 u8 fc_fec_corrected_blocks_lane1_low[0x20]; 2491 2492 u8 fc_fec_corrected_blocks_lane2_high[0x20]; 2493 2494 u8 fc_fec_corrected_blocks_lane2_low[0x20]; 2495 2496 u8 fc_fec_corrected_blocks_lane3_high[0x20]; 2497 2498 u8 fc_fec_corrected_blocks_lane3_low[0x20]; 2499 2500 u8 fc_fec_uncorrectable_blocks_lane0_high[0x20]; 2501 2502 u8 fc_fec_uncorrectable_blocks_lane0_low[0x20]; 2503 2504 u8 fc_fec_uncorrectable_blocks_lane1_high[0x20]; 2505 2506 u8 fc_fec_uncorrectable_blocks_lane1_low[0x20]; 2507 2508 u8 fc_fec_uncorrectable_blocks_lane2_high[0x20]; 2509 2510 u8 fc_fec_uncorrectable_blocks_lane2_low[0x20]; 2511 2512 u8 fc_fec_uncorrectable_blocks_lane3_high[0x20]; 2513 2514 u8 fc_fec_uncorrectable_blocks_lane3_low[0x20]; 2515 2516 u8 rs_fec_corrected_blocks_high[0x20]; 2517 2518 u8 rs_fec_corrected_blocks_low[0x20]; 2519 2520 u8 rs_fec_uncorrectable_blocks_high[0x20]; 2521 2522 u8 rs_fec_uncorrectable_blocks_low[0x20]; 2523 2524 u8 rs_fec_no_errors_blocks_high[0x20]; 2525 2526 u8 rs_fec_no_errors_blocks_low[0x20]; 2527 2528 u8 rs_fec_single_error_blocks_high[0x20]; 2529 2530 u8 rs_fec_single_error_blocks_low[0x20]; 2531 2532 u8 rs_fec_corrected_symbols_total_high[0x20]; 2533 2534 u8 rs_fec_corrected_symbols_total_low[0x20]; 2535 2536 u8 rs_fec_corrected_symbols_lane0_high[0x20]; 2537 2538 u8 rs_fec_corrected_symbols_lane0_low[0x20]; 2539 2540 u8 rs_fec_corrected_symbols_lane1_high[0x20]; 2541 2542 u8 rs_fec_corrected_symbols_lane1_low[0x20]; 2543 2544 u8 rs_fec_corrected_symbols_lane2_high[0x20]; 2545 2546 u8 rs_fec_corrected_symbols_lane2_low[0x20]; 2547 2548 u8 rs_fec_corrected_symbols_lane3_high[0x20]; 2549 2550 u8 rs_fec_corrected_symbols_lane3_low[0x20]; 2551 2552 u8 link_down_events[0x20]; 2553 2554 u8 successful_recovery_events[0x20]; 2555 2556 u8 reserved_at_640[0x180]; 2557 }; 2558 2559 struct mlx5_ifc_phys_layer_statistical_cntrs_bits { 2560 u8 time_since_last_clear_high[0x20]; 2561 2562 u8 time_since_last_clear_low[0x20]; 2563 2564 u8 phy_received_bits_high[0x20]; 2565 2566 u8 phy_received_bits_low[0x20]; 2567 2568 u8 phy_symbol_errors_high[0x20]; 2569 2570 u8 phy_symbol_errors_low[0x20]; 2571 2572 u8 phy_corrected_bits_high[0x20]; 2573 2574 u8 phy_corrected_bits_low[0x20]; 2575 2576 u8 phy_corrected_bits_lane0_high[0x20]; 2577 2578 u8 phy_corrected_bits_lane0_low[0x20]; 2579 2580 u8 phy_corrected_bits_lane1_high[0x20]; 2581 2582 u8 phy_corrected_bits_lane1_low[0x20]; 2583 2584 u8 phy_corrected_bits_lane2_high[0x20]; 2585 2586 u8 phy_corrected_bits_lane2_low[0x20]; 2587 2588 u8 phy_corrected_bits_lane3_high[0x20]; 2589 2590 u8 phy_corrected_bits_lane3_low[0x20]; 2591 2592 u8 reserved_at_200[0x5c0]; 2593 }; 2594 2595 struct mlx5_ifc_ib_port_cntrs_grp_data_layout_bits { 2596 u8 symbol_error_counter[0x10]; 2597 2598 u8 link_error_recovery_counter[0x8]; 2599 2600 u8 link_downed_counter[0x8]; 2601 2602 u8 port_rcv_errors[0x10]; 2603 2604 u8 port_rcv_remote_physical_errors[0x10]; 2605 2606 u8 port_rcv_switch_relay_errors[0x10]; 2607 2608 u8 port_xmit_discards[0x10]; 2609 2610 u8 port_xmit_constraint_errors[0x8]; 2611 2612 u8 port_rcv_constraint_errors[0x8]; 2613 2614 u8 reserved_at_70[0x8]; 2615 2616 u8 link_overrun_errors[0x8]; 2617 2618 u8 reserved_at_80[0x10]; 2619 2620 u8 vl_15_dropped[0x10]; 2621 2622 u8 reserved_at_a0[0x80]; 2623 2624 u8 port_xmit_wait[0x20]; 2625 }; 2626 2627 struct mlx5_ifc_eth_per_tc_prio_grp_data_layout_bits { 2628 u8 transmit_queue_high[0x20]; 2629 2630 u8 transmit_queue_low[0x20]; 2631 2632 u8 no_buffer_discard_uc_high[0x20]; 2633 2634 u8 no_buffer_discard_uc_low[0x20]; 2635 2636 u8 reserved_at_80[0x740]; 2637 }; 2638 2639 struct mlx5_ifc_eth_per_tc_congest_prio_grp_data_layout_bits { 2640 u8 wred_discard_high[0x20]; 2641 2642 u8 wred_discard_low[0x20]; 2643 2644 u8 ecn_marked_tc_high[0x20]; 2645 2646 u8 ecn_marked_tc_low[0x20]; 2647 2648 u8 reserved_at_80[0x740]; 2649 }; 2650 2651 struct mlx5_ifc_eth_per_prio_grp_data_layout_bits { 2652 u8 rx_octets_high[0x20]; 2653 2654 u8 rx_octets_low[0x20]; 2655 2656 u8 reserved_at_40[0xc0]; 2657 2658 u8 rx_frames_high[0x20]; 2659 2660 u8 rx_frames_low[0x20]; 2661 2662 u8 tx_octets_high[0x20]; 2663 2664 u8 tx_octets_low[0x20]; 2665 2666 u8 reserved_at_180[0xc0]; 2667 2668 u8 tx_frames_high[0x20]; 2669 2670 u8 tx_frames_low[0x20]; 2671 2672 u8 rx_pause_high[0x20]; 2673 2674 u8 rx_pause_low[0x20]; 2675 2676 u8 rx_pause_duration_high[0x20]; 2677 2678 u8 rx_pause_duration_low[0x20]; 2679 2680 u8 tx_pause_high[0x20]; 2681 2682 u8 tx_pause_low[0x20]; 2683 2684 u8 tx_pause_duration_high[0x20]; 2685 2686 u8 tx_pause_duration_low[0x20]; 2687 2688 u8 rx_pause_transition_high[0x20]; 2689 2690 u8 rx_pause_transition_low[0x20]; 2691 2692 u8 rx_discards_high[0x20]; 2693 2694 u8 rx_discards_low[0x20]; 2695 2696 u8 device_stall_minor_watermark_cnt_high[0x20]; 2697 2698 u8 device_stall_minor_watermark_cnt_low[0x20]; 2699 2700 u8 device_stall_critical_watermark_cnt_high[0x20]; 2701 2702 u8 device_stall_critical_watermark_cnt_low[0x20]; 2703 2704 u8 reserved_at_480[0x340]; 2705 }; 2706 2707 struct mlx5_ifc_eth_extended_cntrs_grp_data_layout_bits { 2708 u8 port_transmit_wait_high[0x20]; 2709 2710 u8 port_transmit_wait_low[0x20]; 2711 2712 u8 reserved_at_40[0x100]; 2713 2714 u8 rx_buffer_almost_full_high[0x20]; 2715 2716 u8 rx_buffer_almost_full_low[0x20]; 2717 2718 u8 rx_buffer_full_high[0x20]; 2719 2720 u8 rx_buffer_full_low[0x20]; 2721 2722 u8 rx_icrc_encapsulated_high[0x20]; 2723 2724 u8 rx_icrc_encapsulated_low[0x20]; 2725 2726 u8 reserved_at_200[0x5c0]; 2727 }; 2728 2729 struct mlx5_ifc_eth_3635_cntrs_grp_data_layout_bits { 2730 u8 dot3stats_alignment_errors_high[0x20]; 2731 2732 u8 dot3stats_alignment_errors_low[0x20]; 2733 2734 u8 dot3stats_fcs_errors_high[0x20]; 2735 2736 u8 dot3stats_fcs_errors_low[0x20]; 2737 2738 u8 dot3stats_single_collision_frames_high[0x20]; 2739 2740 u8 dot3stats_single_collision_frames_low[0x20]; 2741 2742 u8 dot3stats_multiple_collision_frames_high[0x20]; 2743 2744 u8 dot3stats_multiple_collision_frames_low[0x20]; 2745 2746 u8 dot3stats_sqe_test_errors_high[0x20]; 2747 2748 u8 dot3stats_sqe_test_errors_low[0x20]; 2749 2750 u8 dot3stats_deferred_transmissions_high[0x20]; 2751 2752 u8 dot3stats_deferred_transmissions_low[0x20]; 2753 2754 u8 dot3stats_late_collisions_high[0x20]; 2755 2756 u8 dot3stats_late_collisions_low[0x20]; 2757 2758 u8 dot3stats_excessive_collisions_high[0x20]; 2759 2760 u8 dot3stats_excessive_collisions_low[0x20]; 2761 2762 u8 dot3stats_internal_mac_transmit_errors_high[0x20]; 2763 2764 u8 dot3stats_internal_mac_transmit_errors_low[0x20]; 2765 2766 u8 dot3stats_carrier_sense_errors_high[0x20]; 2767 2768 u8 dot3stats_carrier_sense_errors_low[0x20]; 2769 2770 u8 dot3stats_frame_too_longs_high[0x20]; 2771 2772 u8 dot3stats_frame_too_longs_low[0x20]; 2773 2774 u8 dot3stats_internal_mac_receive_errors_high[0x20]; 2775 2776 u8 dot3stats_internal_mac_receive_errors_low[0x20]; 2777 2778 u8 dot3stats_symbol_errors_high[0x20]; 2779 2780 u8 dot3stats_symbol_errors_low[0x20]; 2781 2782 u8 dot3control_in_unknown_opcodes_high[0x20]; 2783 2784 u8 dot3control_in_unknown_opcodes_low[0x20]; 2785 2786 u8 dot3in_pause_frames_high[0x20]; 2787 2788 u8 dot3in_pause_frames_low[0x20]; 2789 2790 u8 dot3out_pause_frames_high[0x20]; 2791 2792 u8 dot3out_pause_frames_low[0x20]; 2793 2794 u8 reserved_at_400[0x3c0]; 2795 }; 2796 2797 struct mlx5_ifc_eth_2819_cntrs_grp_data_layout_bits { 2798 u8 ether_stats_drop_events_high[0x20]; 2799 2800 u8 ether_stats_drop_events_low[0x20]; 2801 2802 u8 ether_stats_octets_high[0x20]; 2803 2804 u8 ether_stats_octets_low[0x20]; 2805 2806 u8 ether_stats_pkts_high[0x20]; 2807 2808 u8 ether_stats_pkts_low[0x20]; 2809 2810 u8 ether_stats_broadcast_pkts_high[0x20]; 2811 2812 u8 ether_stats_broadcast_pkts_low[0x20]; 2813 2814 u8 ether_stats_multicast_pkts_high[0x20]; 2815 2816 u8 ether_stats_multicast_pkts_low[0x20]; 2817 2818 u8 ether_stats_crc_align_errors_high[0x20]; 2819 2820 u8 ether_stats_crc_align_errors_low[0x20]; 2821 2822 u8 ether_stats_undersize_pkts_high[0x20]; 2823 2824 u8 ether_stats_undersize_pkts_low[0x20]; 2825 2826 u8 ether_stats_oversize_pkts_high[0x20]; 2827 2828 u8 ether_stats_oversize_pkts_low[0x20]; 2829 2830 u8 ether_stats_fragments_high[0x20]; 2831 2832 u8 ether_stats_fragments_low[0x20]; 2833 2834 u8 ether_stats_jabbers_high[0x20]; 2835 2836 u8 ether_stats_jabbers_low[0x20]; 2837 2838 u8 ether_stats_collisions_high[0x20]; 2839 2840 u8 ether_stats_collisions_low[0x20]; 2841 2842 u8 ether_stats_pkts64octets_high[0x20]; 2843 2844 u8 ether_stats_pkts64octets_low[0x20]; 2845 2846 u8 ether_stats_pkts65to127octets_high[0x20]; 2847 2848 u8 ether_stats_pkts65to127octets_low[0x20]; 2849 2850 u8 ether_stats_pkts128to255octets_high[0x20]; 2851 2852 u8 ether_stats_pkts128to255octets_low[0x20]; 2853 2854 u8 ether_stats_pkts256to511octets_high[0x20]; 2855 2856 u8 ether_stats_pkts256to511octets_low[0x20]; 2857 2858 u8 ether_stats_pkts512to1023octets_high[0x20]; 2859 2860 u8 ether_stats_pkts512to1023octets_low[0x20]; 2861 2862 u8 ether_stats_pkts1024to1518octets_high[0x20]; 2863 2864 u8 ether_stats_pkts1024to1518octets_low[0x20]; 2865 2866 u8 ether_stats_pkts1519to2047octets_high[0x20]; 2867 2868 u8 ether_stats_pkts1519to2047octets_low[0x20]; 2869 2870 u8 ether_stats_pkts2048to4095octets_high[0x20]; 2871 2872 u8 ether_stats_pkts2048to4095octets_low[0x20]; 2873 2874 u8 ether_stats_pkts4096to8191octets_high[0x20]; 2875 2876 u8 ether_stats_pkts4096to8191octets_low[0x20]; 2877 2878 u8 ether_stats_pkts8192to10239octets_high[0x20]; 2879 2880 u8 ether_stats_pkts8192to10239octets_low[0x20]; 2881 2882 u8 reserved_at_540[0x280]; 2883 }; 2884 2885 struct mlx5_ifc_eth_2863_cntrs_grp_data_layout_bits { 2886 u8 if_in_octets_high[0x20]; 2887 2888 u8 if_in_octets_low[0x20]; 2889 2890 u8 if_in_ucast_pkts_high[0x20]; 2891 2892 u8 if_in_ucast_pkts_low[0x20]; 2893 2894 u8 if_in_discards_high[0x20]; 2895 2896 u8 if_in_discards_low[0x20]; 2897 2898 u8 if_in_errors_high[0x20]; 2899 2900 u8 if_in_errors_low[0x20]; 2901 2902 u8 if_in_unknown_protos_high[0x20]; 2903 2904 u8 if_in_unknown_protos_low[0x20]; 2905 2906 u8 if_out_octets_high[0x20]; 2907 2908 u8 if_out_octets_low[0x20]; 2909 2910 u8 if_out_ucast_pkts_high[0x20]; 2911 2912 u8 if_out_ucast_pkts_low[0x20]; 2913 2914 u8 if_out_discards_high[0x20]; 2915 2916 u8 if_out_discards_low[0x20]; 2917 2918 u8 if_out_errors_high[0x20]; 2919 2920 u8 if_out_errors_low[0x20]; 2921 2922 u8 if_in_multicast_pkts_high[0x20]; 2923 2924 u8 if_in_multicast_pkts_low[0x20]; 2925 2926 u8 if_in_broadcast_pkts_high[0x20]; 2927 2928 u8 if_in_broadcast_pkts_low[0x20]; 2929 2930 u8 if_out_multicast_pkts_high[0x20]; 2931 2932 u8 if_out_multicast_pkts_low[0x20]; 2933 2934 u8 if_out_broadcast_pkts_high[0x20]; 2935 2936 u8 if_out_broadcast_pkts_low[0x20]; 2937 2938 u8 reserved_at_340[0x480]; 2939 }; 2940 2941 struct mlx5_ifc_eth_802_3_cntrs_grp_data_layout_bits { 2942 u8 a_frames_transmitted_ok_high[0x20]; 2943 2944 u8 a_frames_transmitted_ok_low[0x20]; 2945 2946 u8 a_frames_received_ok_high[0x20]; 2947 2948 u8 a_frames_received_ok_low[0x20]; 2949 2950 u8 a_frame_check_sequence_errors_high[0x20]; 2951 2952 u8 a_frame_check_sequence_errors_low[0x20]; 2953 2954 u8 a_alignment_errors_high[0x20]; 2955 2956 u8 a_alignment_errors_low[0x20]; 2957 2958 u8 a_octets_transmitted_ok_high[0x20]; 2959 2960 u8 a_octets_transmitted_ok_low[0x20]; 2961 2962 u8 a_octets_received_ok_high[0x20]; 2963 2964 u8 a_octets_received_ok_low[0x20]; 2965 2966 u8 a_multicast_frames_xmitted_ok_high[0x20]; 2967 2968 u8 a_multicast_frames_xmitted_ok_low[0x20]; 2969 2970 u8 a_broadcast_frames_xmitted_ok_high[0x20]; 2971 2972 u8 a_broadcast_frames_xmitted_ok_low[0x20]; 2973 2974 u8 a_multicast_frames_received_ok_high[0x20]; 2975 2976 u8 a_multicast_frames_received_ok_low[0x20]; 2977 2978 u8 a_broadcast_frames_received_ok_high[0x20]; 2979 2980 u8 a_broadcast_frames_received_ok_low[0x20]; 2981 2982 u8 a_in_range_length_errors_high[0x20]; 2983 2984 u8 a_in_range_length_errors_low[0x20]; 2985 2986 u8 a_out_of_range_length_field_high[0x20]; 2987 2988 u8 a_out_of_range_length_field_low[0x20]; 2989 2990 u8 a_frame_too_long_errors_high[0x20]; 2991 2992 u8 a_frame_too_long_errors_low[0x20]; 2993 2994 u8 a_symbol_error_during_carrier_high[0x20]; 2995 2996 u8 a_symbol_error_during_carrier_low[0x20]; 2997 2998 u8 a_mac_control_frames_transmitted_high[0x20]; 2999 3000 u8 a_mac_control_frames_transmitted_low[0x20]; 3001 3002 u8 a_mac_control_frames_received_high[0x20]; 3003 3004 u8 a_mac_control_frames_received_low[0x20]; 3005 3006 u8 a_unsupported_opcodes_received_high[0x20]; 3007 3008 u8 a_unsupported_opcodes_received_low[0x20]; 3009 3010 u8 a_pause_mac_ctrl_frames_received_high[0x20]; 3011 3012 u8 a_pause_mac_ctrl_frames_received_low[0x20]; 3013 3014 u8 a_pause_mac_ctrl_frames_transmitted_high[0x20]; 3015 3016 u8 a_pause_mac_ctrl_frames_transmitted_low[0x20]; 3017 3018 u8 reserved_at_4c0[0x300]; 3019 }; 3020 3021 struct mlx5_ifc_pcie_perf_cntrs_grp_data_layout_bits { 3022 u8 life_time_counter_high[0x20]; 3023 3024 u8 life_time_counter_low[0x20]; 3025 3026 u8 rx_errors[0x20]; 3027 3028 u8 tx_errors[0x20]; 3029 3030 u8 l0_to_recovery_eieos[0x20]; 3031 3032 u8 l0_to_recovery_ts[0x20]; 3033 3034 u8 l0_to_recovery_framing[0x20]; 3035 3036 u8 l0_to_recovery_retrain[0x20]; 3037 3038 u8 crc_error_dllp[0x20]; 3039 3040 u8 crc_error_tlp[0x20]; 3041 3042 u8 tx_overflow_buffer_pkt_high[0x20]; 3043 3044 u8 tx_overflow_buffer_pkt_low[0x20]; 3045 3046 u8 outbound_stalled_reads[0x20]; 3047 3048 u8 outbound_stalled_writes[0x20]; 3049 3050 u8 outbound_stalled_reads_events[0x20]; 3051 3052 u8 outbound_stalled_writes_events[0x20]; 3053 3054 u8 reserved_at_200[0x5c0]; 3055 }; 3056 3057 struct mlx5_ifc_cmd_inter_comp_event_bits { 3058 u8 command_completion_vector[0x20]; 3059 3060 u8 reserved_at_20[0xc0]; 3061 }; 3062 3063 struct mlx5_ifc_stall_vl_event_bits { 3064 u8 reserved_at_0[0x18]; 3065 u8 port_num[0x1]; 3066 u8 reserved_at_19[0x3]; 3067 u8 vl[0x4]; 3068 3069 u8 reserved_at_20[0xa0]; 3070 }; 3071 3072 struct mlx5_ifc_db_bf_congestion_event_bits { 3073 u8 event_subtype[0x8]; 3074 u8 reserved_at_8[0x8]; 3075 u8 congestion_level[0x8]; 3076 u8 reserved_at_18[0x8]; 3077 3078 u8 reserved_at_20[0xa0]; 3079 }; 3080 3081 struct mlx5_ifc_gpio_event_bits { 3082 u8 reserved_at_0[0x60]; 3083 3084 u8 gpio_event_hi[0x20]; 3085 3086 u8 gpio_event_lo[0x20]; 3087 3088 u8 reserved_at_a0[0x40]; 3089 }; 3090 3091 struct mlx5_ifc_port_state_change_event_bits { 3092 u8 reserved_at_0[0x40]; 3093 3094 u8 port_num[0x4]; 3095 u8 reserved_at_44[0x1c]; 3096 3097 u8 reserved_at_60[0x80]; 3098 }; 3099 3100 struct mlx5_ifc_dropped_packet_logged_bits { 3101 u8 reserved_at_0[0xe0]; 3102 }; 3103 3104 struct mlx5_ifc_default_timeout_bits { 3105 u8 to_multiplier[0x3]; 3106 u8 reserved_at_3[0x9]; 3107 u8 to_value[0x14]; 3108 }; 3109 3110 struct mlx5_ifc_dtor_reg_bits { 3111 u8 reserved_at_0[0x20]; 3112 3113 struct mlx5_ifc_default_timeout_bits pcie_toggle_to; 3114 3115 u8 reserved_at_40[0x60]; 3116 3117 struct mlx5_ifc_default_timeout_bits health_poll_to; 3118 3119 struct mlx5_ifc_default_timeout_bits full_crdump_to; 3120 3121 struct mlx5_ifc_default_timeout_bits fw_reset_to; 3122 3123 struct mlx5_ifc_default_timeout_bits flush_on_err_to; 3124 3125 struct mlx5_ifc_default_timeout_bits pci_sync_update_to; 3126 3127 struct mlx5_ifc_default_timeout_bits tear_down_to; 3128 3129 struct mlx5_ifc_default_timeout_bits fsm_reactivate_to; 3130 3131 struct mlx5_ifc_default_timeout_bits reclaim_pages_to; 3132 3133 struct mlx5_ifc_default_timeout_bits reclaim_vfs_pages_to; 3134 3135 struct mlx5_ifc_default_timeout_bits reset_unload_to; 3136 3137 u8 reserved_at_1c0[0x20]; 3138 }; 3139 3140 enum { 3141 MLX5_CQ_ERROR_SYNDROME_CQ_OVERRUN = 0x1, 3142 MLX5_CQ_ERROR_SYNDROME_CQ_ACCESS_VIOLATION_ERROR = 0x2, 3143 }; 3144 3145 struct mlx5_ifc_cq_error_bits { 3146 u8 reserved_at_0[0x8]; 3147 u8 cqn[0x18]; 3148 3149 u8 reserved_at_20[0x20]; 3150 3151 u8 reserved_at_40[0x18]; 3152 u8 syndrome[0x8]; 3153 3154 u8 reserved_at_60[0x80]; 3155 }; 3156 3157 struct mlx5_ifc_rdma_page_fault_event_bits { 3158 u8 bytes_committed[0x20]; 3159 3160 u8 r_key[0x20]; 3161 3162 u8 reserved_at_40[0x10]; 3163 u8 packet_len[0x10]; 3164 3165 u8 rdma_op_len[0x20]; 3166 3167 u8 rdma_va[0x40]; 3168 3169 u8 reserved_at_c0[0x5]; 3170 u8 rdma[0x1]; 3171 u8 write[0x1]; 3172 u8 requestor[0x1]; 3173 u8 qp_number[0x18]; 3174 }; 3175 3176 struct mlx5_ifc_wqe_associated_page_fault_event_bits { 3177 u8 bytes_committed[0x20]; 3178 3179 u8 reserved_at_20[0x10]; 3180 u8 wqe_index[0x10]; 3181 3182 u8 reserved_at_40[0x10]; 3183 u8 len[0x10]; 3184 3185 u8 reserved_at_60[0x60]; 3186 3187 u8 reserved_at_c0[0x5]; 3188 u8 rdma[0x1]; 3189 u8 write_read[0x1]; 3190 u8 requestor[0x1]; 3191 u8 qpn[0x18]; 3192 }; 3193 3194 struct mlx5_ifc_qp_events_bits { 3195 u8 reserved_at_0[0xa0]; 3196 3197 u8 type[0x8]; 3198 u8 reserved_at_a8[0x18]; 3199 3200 u8 reserved_at_c0[0x8]; 3201 u8 qpn_rqn_sqn[0x18]; 3202 }; 3203 3204 struct mlx5_ifc_dct_events_bits { 3205 u8 reserved_at_0[0xc0]; 3206 3207 u8 reserved_at_c0[0x8]; 3208 u8 dct_number[0x18]; 3209 }; 3210 3211 struct mlx5_ifc_comp_event_bits { 3212 u8 reserved_at_0[0xc0]; 3213 3214 u8 reserved_at_c0[0x8]; 3215 u8 cq_number[0x18]; 3216 }; 3217 3218 enum { 3219 MLX5_QPC_STATE_RST = 0x0, 3220 MLX5_QPC_STATE_INIT = 0x1, 3221 MLX5_QPC_STATE_RTR = 0x2, 3222 MLX5_QPC_STATE_RTS = 0x3, 3223 MLX5_QPC_STATE_SQER = 0x4, 3224 MLX5_QPC_STATE_ERR = 0x6, 3225 MLX5_QPC_STATE_SQD = 0x7, 3226 MLX5_QPC_STATE_SUSPENDED = 0x9, 3227 }; 3228 3229 enum { 3230 MLX5_QPC_ST_RC = 0x0, 3231 MLX5_QPC_ST_UC = 0x1, 3232 MLX5_QPC_ST_UD = 0x2, 3233 MLX5_QPC_ST_XRC = 0x3, 3234 MLX5_QPC_ST_DCI = 0x5, 3235 MLX5_QPC_ST_QP0 = 0x7, 3236 MLX5_QPC_ST_QP1 = 0x8, 3237 MLX5_QPC_ST_RAW_DATAGRAM = 0x9, 3238 MLX5_QPC_ST_REG_UMR = 0xc, 3239 }; 3240 3241 enum { 3242 MLX5_QPC_PM_STATE_ARMED = 0x0, 3243 MLX5_QPC_PM_STATE_REARM = 0x1, 3244 MLX5_QPC_PM_STATE_RESERVED = 0x2, 3245 MLX5_QPC_PM_STATE_MIGRATED = 0x3, 3246 }; 3247 3248 enum { 3249 MLX5_QPC_OFFLOAD_TYPE_RNDV = 0x1, 3250 }; 3251 3252 enum { 3253 MLX5_QPC_END_PADDING_MODE_SCATTER_AS_IS = 0x0, 3254 MLX5_QPC_END_PADDING_MODE_PAD_TO_CACHE_LINE_ALIGNMENT = 0x1, 3255 }; 3256 3257 enum { 3258 MLX5_QPC_MTU_256_BYTES = 0x1, 3259 MLX5_QPC_MTU_512_BYTES = 0x2, 3260 MLX5_QPC_MTU_1K_BYTES = 0x3, 3261 MLX5_QPC_MTU_2K_BYTES = 0x4, 3262 MLX5_QPC_MTU_4K_BYTES = 0x5, 3263 MLX5_QPC_MTU_RAW_ETHERNET_QP = 0x7, 3264 }; 3265 3266 enum { 3267 MLX5_QPC_ATOMIC_MODE_IB_SPEC = 0x1, 3268 MLX5_QPC_ATOMIC_MODE_ONLY_8B = 0x2, 3269 MLX5_QPC_ATOMIC_MODE_UP_TO_8B = 0x3, 3270 MLX5_QPC_ATOMIC_MODE_UP_TO_16B = 0x4, 3271 MLX5_QPC_ATOMIC_MODE_UP_TO_32B = 0x5, 3272 MLX5_QPC_ATOMIC_MODE_UP_TO_64B = 0x6, 3273 MLX5_QPC_ATOMIC_MODE_UP_TO_128B = 0x7, 3274 MLX5_QPC_ATOMIC_MODE_UP_TO_256B = 0x8, 3275 }; 3276 3277 enum { 3278 MLX5_QPC_CS_REQ_DISABLE = 0x0, 3279 MLX5_QPC_CS_REQ_UP_TO_32B = 0x11, 3280 MLX5_QPC_CS_REQ_UP_TO_64B = 0x22, 3281 }; 3282 3283 enum { 3284 MLX5_QPC_CS_RES_DISABLE = 0x0, 3285 MLX5_QPC_CS_RES_UP_TO_32B = 0x1, 3286 MLX5_QPC_CS_RES_UP_TO_64B = 0x2, 3287 }; 3288 3289 enum { 3290 MLX5_TIMESTAMP_FORMAT_FREE_RUNNING = 0x0, 3291 MLX5_TIMESTAMP_FORMAT_DEFAULT = 0x1, 3292 MLX5_TIMESTAMP_FORMAT_REAL_TIME = 0x2, 3293 }; 3294 3295 struct mlx5_ifc_qpc_bits { 3296 u8 state[0x4]; 3297 u8 lag_tx_port_affinity[0x4]; 3298 u8 st[0x8]; 3299 u8 reserved_at_10[0x2]; 3300 u8 isolate_vl_tc[0x1]; 3301 u8 pm_state[0x2]; 3302 u8 reserved_at_15[0x1]; 3303 u8 req_e2e_credit_mode[0x2]; 3304 u8 offload_type[0x4]; 3305 u8 end_padding_mode[0x2]; 3306 u8 reserved_at_1e[0x2]; 3307 3308 u8 wq_signature[0x1]; 3309 u8 block_lb_mc[0x1]; 3310 u8 atomic_like_write_en[0x1]; 3311 u8 latency_sensitive[0x1]; 3312 u8 reserved_at_24[0x1]; 3313 u8 drain_sigerr[0x1]; 3314 u8 reserved_at_26[0x2]; 3315 u8 pd[0x18]; 3316 3317 u8 mtu[0x3]; 3318 u8 log_msg_max[0x5]; 3319 u8 reserved_at_48[0x1]; 3320 u8 log_rq_size[0x4]; 3321 u8 log_rq_stride[0x3]; 3322 u8 no_sq[0x1]; 3323 u8 log_sq_size[0x4]; 3324 u8 reserved_at_55[0x1]; 3325 u8 retry_mode[0x2]; 3326 u8 ts_format[0x2]; 3327 u8 reserved_at_5a[0x1]; 3328 u8 rlky[0x1]; 3329 u8 ulp_stateless_offload_mode[0x4]; 3330 3331 u8 counter_set_id[0x8]; 3332 u8 uar_page[0x18]; 3333 3334 u8 reserved_at_80[0x8]; 3335 u8 user_index[0x18]; 3336 3337 u8 reserved_at_a0[0x3]; 3338 u8 log_page_size[0x5]; 3339 u8 remote_qpn[0x18]; 3340 3341 struct mlx5_ifc_ads_bits primary_address_path; 3342 3343 struct mlx5_ifc_ads_bits secondary_address_path; 3344 3345 u8 log_ack_req_freq[0x4]; 3346 u8 reserved_at_384[0x4]; 3347 u8 log_sra_max[0x3]; 3348 u8 reserved_at_38b[0x2]; 3349 u8 retry_count[0x3]; 3350 u8 rnr_retry[0x3]; 3351 u8 reserved_at_393[0x1]; 3352 u8 fre[0x1]; 3353 u8 cur_rnr_retry[0x3]; 3354 u8 cur_retry_count[0x3]; 3355 u8 reserved_at_39b[0x5]; 3356 3357 u8 reserved_at_3a0[0x20]; 3358 3359 u8 reserved_at_3c0[0x8]; 3360 u8 next_send_psn[0x18]; 3361 3362 u8 reserved_at_3e0[0x3]; 3363 u8 log_num_dci_stream_channels[0x5]; 3364 u8 cqn_snd[0x18]; 3365 3366 u8 reserved_at_400[0x3]; 3367 u8 log_num_dci_errored_streams[0x5]; 3368 u8 deth_sqpn[0x18]; 3369 3370 u8 reserved_at_420[0x20]; 3371 3372 u8 reserved_at_440[0x8]; 3373 u8 last_acked_psn[0x18]; 3374 3375 u8 reserved_at_460[0x8]; 3376 u8 ssn[0x18]; 3377 3378 u8 reserved_at_480[0x8]; 3379 u8 log_rra_max[0x3]; 3380 u8 reserved_at_48b[0x1]; 3381 u8 atomic_mode[0x4]; 3382 u8 rre[0x1]; 3383 u8 rwe[0x1]; 3384 u8 rae[0x1]; 3385 u8 reserved_at_493[0x1]; 3386 u8 page_offset[0x6]; 3387 u8 reserved_at_49a[0x3]; 3388 u8 cd_slave_receive[0x1]; 3389 u8 cd_slave_send[0x1]; 3390 u8 cd_master[0x1]; 3391 3392 u8 reserved_at_4a0[0x3]; 3393 u8 min_rnr_nak[0x5]; 3394 u8 next_rcv_psn[0x18]; 3395 3396 u8 reserved_at_4c0[0x8]; 3397 u8 xrcd[0x18]; 3398 3399 u8 reserved_at_4e0[0x8]; 3400 u8 cqn_rcv[0x18]; 3401 3402 u8 dbr_addr[0x40]; 3403 3404 u8 q_key[0x20]; 3405 3406 u8 reserved_at_560[0x5]; 3407 u8 rq_type[0x3]; 3408 u8 srqn_rmpn_xrqn[0x18]; 3409 3410 u8 reserved_at_580[0x8]; 3411 u8 rmsn[0x18]; 3412 3413 u8 hw_sq_wqebb_counter[0x10]; 3414 u8 sw_sq_wqebb_counter[0x10]; 3415 3416 u8 hw_rq_counter[0x20]; 3417 3418 u8 sw_rq_counter[0x20]; 3419 3420 u8 reserved_at_600[0x20]; 3421 3422 u8 reserved_at_620[0xf]; 3423 u8 cgs[0x1]; 3424 u8 cs_req[0x8]; 3425 u8 cs_res[0x8]; 3426 3427 u8 dc_access_key[0x40]; 3428 3429 u8 reserved_at_680[0x3]; 3430 u8 dbr_umem_valid[0x1]; 3431 3432 u8 reserved_at_684[0xbc]; 3433 }; 3434 3435 struct mlx5_ifc_roce_addr_layout_bits { 3436 u8 source_l3_address[16][0x8]; 3437 3438 u8 reserved_at_80[0x3]; 3439 u8 vlan_valid[0x1]; 3440 u8 vlan_id[0xc]; 3441 u8 source_mac_47_32[0x10]; 3442 3443 u8 source_mac_31_0[0x20]; 3444 3445 u8 reserved_at_c0[0x14]; 3446 u8 roce_l3_type[0x4]; 3447 u8 roce_version[0x8]; 3448 3449 u8 reserved_at_e0[0x20]; 3450 }; 3451 3452 struct mlx5_ifc_crypto_cap_bits { 3453 u8 reserved_at_0[0x3]; 3454 u8 synchronize_dek[0x1]; 3455 u8 int_kek_manual[0x1]; 3456 u8 int_kek_auto[0x1]; 3457 u8 reserved_at_6[0x1a]; 3458 3459 u8 reserved_at_20[0x3]; 3460 u8 log_dek_max_alloc[0x5]; 3461 u8 reserved_at_28[0x3]; 3462 u8 log_max_num_deks[0x5]; 3463 u8 reserved_at_30[0x10]; 3464 3465 u8 reserved_at_40[0x20]; 3466 3467 u8 reserved_at_60[0x3]; 3468 u8 log_dek_granularity[0x5]; 3469 u8 reserved_at_68[0x3]; 3470 u8 log_max_num_int_kek[0x5]; 3471 u8 sw_wrapped_dek[0x10]; 3472 3473 u8 reserved_at_80[0x780]; 3474 }; 3475 3476 union mlx5_ifc_hca_cap_union_bits { 3477 struct mlx5_ifc_cmd_hca_cap_bits cmd_hca_cap; 3478 struct mlx5_ifc_cmd_hca_cap_2_bits cmd_hca_cap_2; 3479 struct mlx5_ifc_odp_cap_bits odp_cap; 3480 struct mlx5_ifc_atomic_caps_bits atomic_caps; 3481 struct mlx5_ifc_roce_cap_bits roce_cap; 3482 struct mlx5_ifc_per_protocol_networking_offload_caps_bits per_protocol_networking_offload_caps; 3483 struct mlx5_ifc_flow_table_nic_cap_bits flow_table_nic_cap; 3484 struct mlx5_ifc_flow_table_eswitch_cap_bits flow_table_eswitch_cap; 3485 struct mlx5_ifc_e_switch_cap_bits e_switch_cap; 3486 struct mlx5_ifc_port_selection_cap_bits port_selection_cap; 3487 struct mlx5_ifc_qos_cap_bits qos_cap; 3488 struct mlx5_ifc_debug_cap_bits debug_cap; 3489 struct mlx5_ifc_fpga_cap_bits fpga_cap; 3490 struct mlx5_ifc_tls_cap_bits tls_cap; 3491 struct mlx5_ifc_device_mem_cap_bits device_mem_cap; 3492 struct mlx5_ifc_virtio_emulation_cap_bits virtio_emulation_cap; 3493 struct mlx5_ifc_macsec_cap_bits macsec_cap; 3494 struct mlx5_ifc_crypto_cap_bits crypto_cap; 3495 struct mlx5_ifc_ipsec_cap_bits ipsec_cap; 3496 u8 reserved_at_0[0x8000]; 3497 }; 3498 3499 enum { 3500 MLX5_FLOW_CONTEXT_ACTION_ALLOW = 0x1, 3501 MLX5_FLOW_CONTEXT_ACTION_DROP = 0x2, 3502 MLX5_FLOW_CONTEXT_ACTION_FWD_DEST = 0x4, 3503 MLX5_FLOW_CONTEXT_ACTION_COUNT = 0x8, 3504 MLX5_FLOW_CONTEXT_ACTION_PACKET_REFORMAT = 0x10, 3505 MLX5_FLOW_CONTEXT_ACTION_DECAP = 0x20, 3506 MLX5_FLOW_CONTEXT_ACTION_MOD_HDR = 0x40, 3507 MLX5_FLOW_CONTEXT_ACTION_VLAN_POP = 0x80, 3508 MLX5_FLOW_CONTEXT_ACTION_VLAN_PUSH = 0x100, 3509 MLX5_FLOW_CONTEXT_ACTION_VLAN_POP_2 = 0x400, 3510 MLX5_FLOW_CONTEXT_ACTION_VLAN_PUSH_2 = 0x800, 3511 MLX5_FLOW_CONTEXT_ACTION_CRYPTO_DECRYPT = 0x1000, 3512 MLX5_FLOW_CONTEXT_ACTION_CRYPTO_ENCRYPT = 0x2000, 3513 MLX5_FLOW_CONTEXT_ACTION_EXECUTE_ASO = 0x4000, 3514 }; 3515 3516 enum { 3517 MLX5_FLOW_CONTEXT_FLOW_SOURCE_ANY_VPORT = 0x0, 3518 MLX5_FLOW_CONTEXT_FLOW_SOURCE_UPLINK = 0x1, 3519 MLX5_FLOW_CONTEXT_FLOW_SOURCE_LOCAL_VPORT = 0x2, 3520 }; 3521 3522 enum { 3523 MLX5_FLOW_CONTEXT_ENCRYPT_DECRYPT_TYPE_IPSEC = 0x0, 3524 MLX5_FLOW_CONTEXT_ENCRYPT_DECRYPT_TYPE_MACSEC = 0x1, 3525 }; 3526 3527 struct mlx5_ifc_vlan_bits { 3528 u8 ethtype[0x10]; 3529 u8 prio[0x3]; 3530 u8 cfi[0x1]; 3531 u8 vid[0xc]; 3532 }; 3533 3534 enum { 3535 MLX5_FLOW_METER_COLOR_RED = 0x0, 3536 MLX5_FLOW_METER_COLOR_YELLOW = 0x1, 3537 MLX5_FLOW_METER_COLOR_GREEN = 0x2, 3538 MLX5_FLOW_METER_COLOR_UNDEFINED = 0x3, 3539 }; 3540 3541 enum { 3542 MLX5_EXE_ASO_FLOW_METER = 0x2, 3543 }; 3544 3545 struct mlx5_ifc_exe_aso_ctrl_flow_meter_bits { 3546 u8 return_reg_id[0x4]; 3547 u8 aso_type[0x4]; 3548 u8 reserved_at_8[0x14]; 3549 u8 action[0x1]; 3550 u8 init_color[0x2]; 3551 u8 meter_id[0x1]; 3552 }; 3553 3554 union mlx5_ifc_exe_aso_ctrl { 3555 struct mlx5_ifc_exe_aso_ctrl_flow_meter_bits exe_aso_ctrl_flow_meter; 3556 }; 3557 3558 struct mlx5_ifc_execute_aso_bits { 3559 u8 valid[0x1]; 3560 u8 reserved_at_1[0x7]; 3561 u8 aso_object_id[0x18]; 3562 3563 union mlx5_ifc_exe_aso_ctrl exe_aso_ctrl; 3564 }; 3565 3566 struct mlx5_ifc_flow_context_bits { 3567 struct mlx5_ifc_vlan_bits push_vlan; 3568 3569 u8 group_id[0x20]; 3570 3571 u8 reserved_at_40[0x8]; 3572 u8 flow_tag[0x18]; 3573 3574 u8 reserved_at_60[0x10]; 3575 u8 action[0x10]; 3576 3577 u8 extended_destination[0x1]; 3578 u8 reserved_at_81[0x1]; 3579 u8 flow_source[0x2]; 3580 u8 encrypt_decrypt_type[0x4]; 3581 u8 destination_list_size[0x18]; 3582 3583 u8 reserved_at_a0[0x8]; 3584 u8 flow_counter_list_size[0x18]; 3585 3586 u8 packet_reformat_id[0x20]; 3587 3588 u8 modify_header_id[0x20]; 3589 3590 struct mlx5_ifc_vlan_bits push_vlan_2; 3591 3592 u8 encrypt_decrypt_obj_id[0x20]; 3593 u8 reserved_at_140[0xc0]; 3594 3595 struct mlx5_ifc_fte_match_param_bits match_value; 3596 3597 struct mlx5_ifc_execute_aso_bits execute_aso[4]; 3598 3599 u8 reserved_at_1300[0x500]; 3600 3601 union mlx5_ifc_dest_format_struct_flow_counter_list_auto_bits destination[]; 3602 }; 3603 3604 enum { 3605 MLX5_XRC_SRQC_STATE_GOOD = 0x0, 3606 MLX5_XRC_SRQC_STATE_ERROR = 0x1, 3607 }; 3608 3609 struct mlx5_ifc_xrc_srqc_bits { 3610 u8 state[0x4]; 3611 u8 log_xrc_srq_size[0x4]; 3612 u8 reserved_at_8[0x18]; 3613 3614 u8 wq_signature[0x1]; 3615 u8 cont_srq[0x1]; 3616 u8 reserved_at_22[0x1]; 3617 u8 rlky[0x1]; 3618 u8 basic_cyclic_rcv_wqe[0x1]; 3619 u8 log_rq_stride[0x3]; 3620 u8 xrcd[0x18]; 3621 3622 u8 page_offset[0x6]; 3623 u8 reserved_at_46[0x1]; 3624 u8 dbr_umem_valid[0x1]; 3625 u8 cqn[0x18]; 3626 3627 u8 reserved_at_60[0x20]; 3628 3629 u8 user_index_equal_xrc_srqn[0x1]; 3630 u8 reserved_at_81[0x1]; 3631 u8 log_page_size[0x6]; 3632 u8 user_index[0x18]; 3633 3634 u8 reserved_at_a0[0x20]; 3635 3636 u8 reserved_at_c0[0x8]; 3637 u8 pd[0x18]; 3638 3639 u8 lwm[0x10]; 3640 u8 wqe_cnt[0x10]; 3641 3642 u8 reserved_at_100[0x40]; 3643 3644 u8 db_record_addr_h[0x20]; 3645 3646 u8 db_record_addr_l[0x1e]; 3647 u8 reserved_at_17e[0x2]; 3648 3649 u8 reserved_at_180[0x80]; 3650 }; 3651 3652 struct mlx5_ifc_vnic_diagnostic_statistics_bits { 3653 u8 counter_error_queues[0x20]; 3654 3655 u8 total_error_queues[0x20]; 3656 3657 u8 send_queue_priority_update_flow[0x20]; 3658 3659 u8 reserved_at_60[0x20]; 3660 3661 u8 nic_receive_steering_discard[0x40]; 3662 3663 u8 receive_discard_vport_down[0x40]; 3664 3665 u8 transmit_discard_vport_down[0x40]; 3666 3667 u8 async_eq_overrun[0x20]; 3668 3669 u8 comp_eq_overrun[0x20]; 3670 3671 u8 reserved_at_180[0x20]; 3672 3673 u8 invalid_command[0x20]; 3674 3675 u8 quota_exceeded_command[0x20]; 3676 3677 u8 internal_rq_out_of_buffer[0x20]; 3678 3679 u8 cq_overrun[0x20]; 3680 3681 u8 eth_wqe_too_small[0x20]; 3682 3683 u8 reserved_at_220[0xc0]; 3684 3685 u8 generated_pkt_steering_fail[0x40]; 3686 3687 u8 handled_pkt_steering_fail[0x40]; 3688 3689 u8 reserved_at_360[0xc80]; 3690 }; 3691 3692 struct mlx5_ifc_traffic_counter_bits { 3693 u8 packets[0x40]; 3694 3695 u8 octets[0x40]; 3696 }; 3697 3698 struct mlx5_ifc_tisc_bits { 3699 u8 strict_lag_tx_port_affinity[0x1]; 3700 u8 tls_en[0x1]; 3701 u8 reserved_at_2[0x2]; 3702 u8 lag_tx_port_affinity[0x04]; 3703 3704 u8 reserved_at_8[0x4]; 3705 u8 prio[0x4]; 3706 u8 reserved_at_10[0x10]; 3707 3708 u8 reserved_at_20[0x100]; 3709 3710 u8 reserved_at_120[0x8]; 3711 u8 transport_domain[0x18]; 3712 3713 u8 reserved_at_140[0x8]; 3714 u8 underlay_qpn[0x18]; 3715 3716 u8 reserved_at_160[0x8]; 3717 u8 pd[0x18]; 3718 3719 u8 reserved_at_180[0x380]; 3720 }; 3721 3722 enum { 3723 MLX5_TIRC_DISP_TYPE_DIRECT = 0x0, 3724 MLX5_TIRC_DISP_TYPE_INDIRECT = 0x1, 3725 }; 3726 3727 enum { 3728 MLX5_TIRC_PACKET_MERGE_MASK_IPV4_LRO = BIT(0), 3729 MLX5_TIRC_PACKET_MERGE_MASK_IPV6_LRO = BIT(1), 3730 }; 3731 3732 enum { 3733 MLX5_RX_HASH_FN_NONE = 0x0, 3734 MLX5_RX_HASH_FN_INVERTED_XOR8 = 0x1, 3735 MLX5_RX_HASH_FN_TOEPLITZ = 0x2, 3736 }; 3737 3738 enum { 3739 MLX5_TIRC_SELF_LB_BLOCK_BLOCK_UNICAST = 0x1, 3740 MLX5_TIRC_SELF_LB_BLOCK_BLOCK_MULTICAST = 0x2, 3741 }; 3742 3743 struct mlx5_ifc_tirc_bits { 3744 u8 reserved_at_0[0x20]; 3745 3746 u8 disp_type[0x4]; 3747 u8 tls_en[0x1]; 3748 u8 reserved_at_25[0x1b]; 3749 3750 u8 reserved_at_40[0x40]; 3751 3752 u8 reserved_at_80[0x4]; 3753 u8 lro_timeout_period_usecs[0x10]; 3754 u8 packet_merge_mask[0x4]; 3755 u8 lro_max_ip_payload_size[0x8]; 3756 3757 u8 reserved_at_a0[0x40]; 3758 3759 u8 reserved_at_e0[0x8]; 3760 u8 inline_rqn[0x18]; 3761 3762 u8 rx_hash_symmetric[0x1]; 3763 u8 reserved_at_101[0x1]; 3764 u8 tunneled_offload_en[0x1]; 3765 u8 reserved_at_103[0x5]; 3766 u8 indirect_table[0x18]; 3767 3768 u8 rx_hash_fn[0x4]; 3769 u8 reserved_at_124[0x2]; 3770 u8 self_lb_block[0x2]; 3771 u8 transport_domain[0x18]; 3772 3773 u8 rx_hash_toeplitz_key[10][0x20]; 3774 3775 struct mlx5_ifc_rx_hash_field_select_bits rx_hash_field_selector_outer; 3776 3777 struct mlx5_ifc_rx_hash_field_select_bits rx_hash_field_selector_inner; 3778 3779 u8 reserved_at_2c0[0x4c0]; 3780 }; 3781 3782 enum { 3783 MLX5_SRQC_STATE_GOOD = 0x0, 3784 MLX5_SRQC_STATE_ERROR = 0x1, 3785 }; 3786 3787 struct mlx5_ifc_srqc_bits { 3788 u8 state[0x4]; 3789 u8 log_srq_size[0x4]; 3790 u8 reserved_at_8[0x18]; 3791 3792 u8 wq_signature[0x1]; 3793 u8 cont_srq[0x1]; 3794 u8 reserved_at_22[0x1]; 3795 u8 rlky[0x1]; 3796 u8 reserved_at_24[0x1]; 3797 u8 log_rq_stride[0x3]; 3798 u8 xrcd[0x18]; 3799 3800 u8 page_offset[0x6]; 3801 u8 reserved_at_46[0x2]; 3802 u8 cqn[0x18]; 3803 3804 u8 reserved_at_60[0x20]; 3805 3806 u8 reserved_at_80[0x2]; 3807 u8 log_page_size[0x6]; 3808 u8 reserved_at_88[0x18]; 3809 3810 u8 reserved_at_a0[0x20]; 3811 3812 u8 reserved_at_c0[0x8]; 3813 u8 pd[0x18]; 3814 3815 u8 lwm[0x10]; 3816 u8 wqe_cnt[0x10]; 3817 3818 u8 reserved_at_100[0x40]; 3819 3820 u8 dbr_addr[0x40]; 3821 3822 u8 reserved_at_180[0x80]; 3823 }; 3824 3825 enum { 3826 MLX5_SQC_STATE_RST = 0x0, 3827 MLX5_SQC_STATE_RDY = 0x1, 3828 MLX5_SQC_STATE_ERR = 0x3, 3829 }; 3830 3831 struct mlx5_ifc_sqc_bits { 3832 u8 rlky[0x1]; 3833 u8 cd_master[0x1]; 3834 u8 fre[0x1]; 3835 u8 flush_in_error_en[0x1]; 3836 u8 allow_multi_pkt_send_wqe[0x1]; 3837 u8 min_wqe_inline_mode[0x3]; 3838 u8 state[0x4]; 3839 u8 reg_umr[0x1]; 3840 u8 allow_swp[0x1]; 3841 u8 hairpin[0x1]; 3842 u8 reserved_at_f[0xb]; 3843 u8 ts_format[0x2]; 3844 u8 reserved_at_1c[0x4]; 3845 3846 u8 reserved_at_20[0x8]; 3847 u8 user_index[0x18]; 3848 3849 u8 reserved_at_40[0x8]; 3850 u8 cqn[0x18]; 3851 3852 u8 reserved_at_60[0x8]; 3853 u8 hairpin_peer_rq[0x18]; 3854 3855 u8 reserved_at_80[0x10]; 3856 u8 hairpin_peer_vhca[0x10]; 3857 3858 u8 reserved_at_a0[0x20]; 3859 3860 u8 reserved_at_c0[0x8]; 3861 u8 ts_cqe_to_dest_cqn[0x18]; 3862 3863 u8 reserved_at_e0[0x10]; 3864 u8 packet_pacing_rate_limit_index[0x10]; 3865 u8 tis_lst_sz[0x10]; 3866 u8 qos_queue_group_id[0x10]; 3867 3868 u8 reserved_at_120[0x40]; 3869 3870 u8 reserved_at_160[0x8]; 3871 u8 tis_num_0[0x18]; 3872 3873 struct mlx5_ifc_wq_bits wq; 3874 }; 3875 3876 enum { 3877 SCHEDULING_CONTEXT_ELEMENT_TYPE_TSAR = 0x0, 3878 SCHEDULING_CONTEXT_ELEMENT_TYPE_VPORT = 0x1, 3879 SCHEDULING_CONTEXT_ELEMENT_TYPE_VPORT_TC = 0x2, 3880 SCHEDULING_CONTEXT_ELEMENT_TYPE_PARA_VPORT_TC = 0x3, 3881 SCHEDULING_CONTEXT_ELEMENT_TYPE_QUEUE_GROUP = 0x4, 3882 }; 3883 3884 enum { 3885 ELEMENT_TYPE_CAP_MASK_TASR = 1 << 0, 3886 ELEMENT_TYPE_CAP_MASK_VPORT = 1 << 1, 3887 ELEMENT_TYPE_CAP_MASK_VPORT_TC = 1 << 2, 3888 ELEMENT_TYPE_CAP_MASK_PARA_VPORT_TC = 1 << 3, 3889 }; 3890 3891 struct mlx5_ifc_scheduling_context_bits { 3892 u8 element_type[0x8]; 3893 u8 reserved_at_8[0x18]; 3894 3895 u8 element_attributes[0x20]; 3896 3897 u8 parent_element_id[0x20]; 3898 3899 u8 reserved_at_60[0x40]; 3900 3901 u8 bw_share[0x20]; 3902 3903 u8 max_average_bw[0x20]; 3904 3905 u8 reserved_at_e0[0x120]; 3906 }; 3907 3908 struct mlx5_ifc_rqtc_bits { 3909 u8 reserved_at_0[0xa0]; 3910 3911 u8 reserved_at_a0[0x5]; 3912 u8 list_q_type[0x3]; 3913 u8 reserved_at_a8[0x8]; 3914 u8 rqt_max_size[0x10]; 3915 3916 u8 rq_vhca_id_format[0x1]; 3917 u8 reserved_at_c1[0xf]; 3918 u8 rqt_actual_size[0x10]; 3919 3920 u8 reserved_at_e0[0x6a0]; 3921 3922 union { 3923 DECLARE_FLEX_ARRAY(struct mlx5_ifc_rq_num_bits, rq_num); 3924 DECLARE_FLEX_ARRAY(struct mlx5_ifc_rq_vhca_bits, rq_vhca); 3925 }; 3926 }; 3927 3928 enum { 3929 MLX5_RQC_MEM_RQ_TYPE_MEMORY_RQ_INLINE = 0x0, 3930 MLX5_RQC_MEM_RQ_TYPE_MEMORY_RQ_RMP = 0x1, 3931 }; 3932 3933 enum { 3934 MLX5_RQC_STATE_RST = 0x0, 3935 MLX5_RQC_STATE_RDY = 0x1, 3936 MLX5_RQC_STATE_ERR = 0x3, 3937 }; 3938 3939 enum { 3940 MLX5_RQC_SHAMPO_NO_MATCH_ALIGNMENT_GRANULARITY_BYTE = 0x0, 3941 MLX5_RQC_SHAMPO_NO_MATCH_ALIGNMENT_GRANULARITY_STRIDE = 0x1, 3942 MLX5_RQC_SHAMPO_NO_MATCH_ALIGNMENT_GRANULARITY_PAGE = 0x2, 3943 }; 3944 3945 enum { 3946 MLX5_RQC_SHAMPO_MATCH_CRITERIA_TYPE_NO_MATCH = 0x0, 3947 MLX5_RQC_SHAMPO_MATCH_CRITERIA_TYPE_EXTENDED = 0x1, 3948 MLX5_RQC_SHAMPO_MATCH_CRITERIA_TYPE_FIVE_TUPLE = 0x2, 3949 }; 3950 3951 struct mlx5_ifc_rqc_bits { 3952 u8 rlky[0x1]; 3953 u8 delay_drop_en[0x1]; 3954 u8 scatter_fcs[0x1]; 3955 u8 vsd[0x1]; 3956 u8 mem_rq_type[0x4]; 3957 u8 state[0x4]; 3958 u8 reserved_at_c[0x1]; 3959 u8 flush_in_error_en[0x1]; 3960 u8 hairpin[0x1]; 3961 u8 reserved_at_f[0xb]; 3962 u8 ts_format[0x2]; 3963 u8 reserved_at_1c[0x4]; 3964 3965 u8 reserved_at_20[0x8]; 3966 u8 user_index[0x18]; 3967 3968 u8 reserved_at_40[0x8]; 3969 u8 cqn[0x18]; 3970 3971 u8 counter_set_id[0x8]; 3972 u8 reserved_at_68[0x18]; 3973 3974 u8 reserved_at_80[0x8]; 3975 u8 rmpn[0x18]; 3976 3977 u8 reserved_at_a0[0x8]; 3978 u8 hairpin_peer_sq[0x18]; 3979 3980 u8 reserved_at_c0[0x10]; 3981 u8 hairpin_peer_vhca[0x10]; 3982 3983 u8 reserved_at_e0[0x46]; 3984 u8 shampo_no_match_alignment_granularity[0x2]; 3985 u8 reserved_at_128[0x6]; 3986 u8 shampo_match_criteria_type[0x2]; 3987 u8 reservation_timeout[0x10]; 3988 3989 u8 reserved_at_140[0x40]; 3990 3991 struct mlx5_ifc_wq_bits wq; 3992 }; 3993 3994 enum { 3995 MLX5_RMPC_STATE_RDY = 0x1, 3996 MLX5_RMPC_STATE_ERR = 0x3, 3997 }; 3998 3999 struct mlx5_ifc_rmpc_bits { 4000 u8 reserved_at_0[0x8]; 4001 u8 state[0x4]; 4002 u8 reserved_at_c[0x14]; 4003 4004 u8 basic_cyclic_rcv_wqe[0x1]; 4005 u8 reserved_at_21[0x1f]; 4006 4007 u8 reserved_at_40[0x140]; 4008 4009 struct mlx5_ifc_wq_bits wq; 4010 }; 4011 4012 enum { 4013 VHCA_ID_TYPE_HW = 0, 4014 VHCA_ID_TYPE_SW = 1, 4015 }; 4016 4017 struct mlx5_ifc_nic_vport_context_bits { 4018 u8 reserved_at_0[0x5]; 4019 u8 min_wqe_inline_mode[0x3]; 4020 u8 reserved_at_8[0x15]; 4021 u8 disable_mc_local_lb[0x1]; 4022 u8 disable_uc_local_lb[0x1]; 4023 u8 roce_en[0x1]; 4024 4025 u8 arm_change_event[0x1]; 4026 u8 reserved_at_21[0x1a]; 4027 u8 event_on_mtu[0x1]; 4028 u8 event_on_promisc_change[0x1]; 4029 u8 event_on_vlan_change[0x1]; 4030 u8 event_on_mc_address_change[0x1]; 4031 u8 event_on_uc_address_change[0x1]; 4032 4033 u8 vhca_id_type[0x1]; 4034 u8 reserved_at_41[0xb]; 4035 u8 affiliation_criteria[0x4]; 4036 u8 affiliated_vhca_id[0x10]; 4037 4038 u8 reserved_at_60[0xd0]; 4039 4040 u8 mtu[0x10]; 4041 4042 u8 system_image_guid[0x40]; 4043 u8 port_guid[0x40]; 4044 u8 node_guid[0x40]; 4045 4046 u8 reserved_at_200[0x140]; 4047 u8 qkey_violation_counter[0x10]; 4048 u8 reserved_at_350[0x430]; 4049 4050 u8 promisc_uc[0x1]; 4051 u8 promisc_mc[0x1]; 4052 u8 promisc_all[0x1]; 4053 u8 reserved_at_783[0x2]; 4054 u8 allowed_list_type[0x3]; 4055 u8 reserved_at_788[0xc]; 4056 u8 allowed_list_size[0xc]; 4057 4058 struct mlx5_ifc_mac_address_layout_bits permanent_address; 4059 4060 u8 reserved_at_7e0[0x20]; 4061 4062 u8 current_uc_mac_address[][0x40]; 4063 }; 4064 4065 enum { 4066 MLX5_MKC_ACCESS_MODE_PA = 0x0, 4067 MLX5_MKC_ACCESS_MODE_MTT = 0x1, 4068 MLX5_MKC_ACCESS_MODE_KLMS = 0x2, 4069 MLX5_MKC_ACCESS_MODE_KSM = 0x3, 4070 MLX5_MKC_ACCESS_MODE_SW_ICM = 0x4, 4071 MLX5_MKC_ACCESS_MODE_MEMIC = 0x5, 4072 }; 4073 4074 struct mlx5_ifc_mkc_bits { 4075 u8 reserved_at_0[0x1]; 4076 u8 free[0x1]; 4077 u8 reserved_at_2[0x1]; 4078 u8 access_mode_4_2[0x3]; 4079 u8 reserved_at_6[0x7]; 4080 u8 relaxed_ordering_write[0x1]; 4081 u8 reserved_at_e[0x1]; 4082 u8 small_fence_on_rdma_read_response[0x1]; 4083 u8 umr_en[0x1]; 4084 u8 a[0x1]; 4085 u8 rw[0x1]; 4086 u8 rr[0x1]; 4087 u8 lw[0x1]; 4088 u8 lr[0x1]; 4089 u8 access_mode_1_0[0x2]; 4090 u8 reserved_at_18[0x2]; 4091 u8 ma_translation_mode[0x2]; 4092 u8 reserved_at_1c[0x4]; 4093 4094 u8 qpn[0x18]; 4095 u8 mkey_7_0[0x8]; 4096 4097 u8 reserved_at_40[0x20]; 4098 4099 u8 length64[0x1]; 4100 u8 bsf_en[0x1]; 4101 u8 sync_umr[0x1]; 4102 u8 reserved_at_63[0x2]; 4103 u8 expected_sigerr_count[0x1]; 4104 u8 reserved_at_66[0x1]; 4105 u8 en_rinval[0x1]; 4106 u8 pd[0x18]; 4107 4108 u8 start_addr[0x40]; 4109 4110 u8 len[0x40]; 4111 4112 u8 bsf_octword_size[0x20]; 4113 4114 u8 reserved_at_120[0x80]; 4115 4116 u8 translations_octword_size[0x20]; 4117 4118 u8 reserved_at_1c0[0x19]; 4119 u8 relaxed_ordering_read[0x1]; 4120 u8 reserved_at_1d9[0x1]; 4121 u8 log_page_size[0x5]; 4122 4123 u8 reserved_at_1e0[0x20]; 4124 }; 4125 4126 struct mlx5_ifc_pkey_bits { 4127 u8 reserved_at_0[0x10]; 4128 u8 pkey[0x10]; 4129 }; 4130 4131 struct mlx5_ifc_array128_auto_bits { 4132 u8 array128_auto[16][0x8]; 4133 }; 4134 4135 struct mlx5_ifc_hca_vport_context_bits { 4136 u8 field_select[0x20]; 4137 4138 u8 reserved_at_20[0xe0]; 4139 4140 u8 sm_virt_aware[0x1]; 4141 u8 has_smi[0x1]; 4142 u8 has_raw[0x1]; 4143 u8 grh_required[0x1]; 4144 u8 reserved_at_104[0xc]; 4145 u8 port_physical_state[0x4]; 4146 u8 vport_state_policy[0x4]; 4147 u8 port_state[0x4]; 4148 u8 vport_state[0x4]; 4149 4150 u8 reserved_at_120[0x20]; 4151 4152 u8 system_image_guid[0x40]; 4153 4154 u8 port_guid[0x40]; 4155 4156 u8 node_guid[0x40]; 4157 4158 u8 cap_mask1[0x20]; 4159 4160 u8 cap_mask1_field_select[0x20]; 4161 4162 u8 cap_mask2[0x20]; 4163 4164 u8 cap_mask2_field_select[0x20]; 4165 4166 u8 reserved_at_280[0x80]; 4167 4168 u8 lid[0x10]; 4169 u8 reserved_at_310[0x4]; 4170 u8 init_type_reply[0x4]; 4171 u8 lmc[0x3]; 4172 u8 subnet_timeout[0x5]; 4173 4174 u8 sm_lid[0x10]; 4175 u8 sm_sl[0x4]; 4176 u8 reserved_at_334[0xc]; 4177 4178 u8 qkey_violation_counter[0x10]; 4179 u8 pkey_violation_counter[0x10]; 4180 4181 u8 reserved_at_360[0xca0]; 4182 }; 4183 4184 struct mlx5_ifc_esw_vport_context_bits { 4185 u8 fdb_to_vport_reg_c[0x1]; 4186 u8 reserved_at_1[0x2]; 4187 u8 vport_svlan_strip[0x1]; 4188 u8 vport_cvlan_strip[0x1]; 4189 u8 vport_svlan_insert[0x1]; 4190 u8 vport_cvlan_insert[0x2]; 4191 u8 fdb_to_vport_reg_c_id[0x8]; 4192 u8 reserved_at_10[0x10]; 4193 4194 u8 reserved_at_20[0x20]; 4195 4196 u8 svlan_cfi[0x1]; 4197 u8 svlan_pcp[0x3]; 4198 u8 svlan_id[0xc]; 4199 u8 cvlan_cfi[0x1]; 4200 u8 cvlan_pcp[0x3]; 4201 u8 cvlan_id[0xc]; 4202 4203 u8 reserved_at_60[0x720]; 4204 4205 u8 sw_steering_vport_icm_address_rx[0x40]; 4206 4207 u8 sw_steering_vport_icm_address_tx[0x40]; 4208 }; 4209 4210 enum { 4211 MLX5_EQC_STATUS_OK = 0x0, 4212 MLX5_EQC_STATUS_EQ_WRITE_FAILURE = 0xa, 4213 }; 4214 4215 enum { 4216 MLX5_EQC_ST_ARMED = 0x9, 4217 MLX5_EQC_ST_FIRED = 0xa, 4218 }; 4219 4220 struct mlx5_ifc_eqc_bits { 4221 u8 status[0x4]; 4222 u8 reserved_at_4[0x9]; 4223 u8 ec[0x1]; 4224 u8 oi[0x1]; 4225 u8 reserved_at_f[0x5]; 4226 u8 st[0x4]; 4227 u8 reserved_at_18[0x8]; 4228 4229 u8 reserved_at_20[0x20]; 4230 4231 u8 reserved_at_40[0x14]; 4232 u8 page_offset[0x6]; 4233 u8 reserved_at_5a[0x6]; 4234 4235 u8 reserved_at_60[0x3]; 4236 u8 log_eq_size[0x5]; 4237 u8 uar_page[0x18]; 4238 4239 u8 reserved_at_80[0x20]; 4240 4241 u8 reserved_at_a0[0x14]; 4242 u8 intr[0xc]; 4243 4244 u8 reserved_at_c0[0x3]; 4245 u8 log_page_size[0x5]; 4246 u8 reserved_at_c8[0x18]; 4247 4248 u8 reserved_at_e0[0x60]; 4249 4250 u8 reserved_at_140[0x8]; 4251 u8 consumer_counter[0x18]; 4252 4253 u8 reserved_at_160[0x8]; 4254 u8 producer_counter[0x18]; 4255 4256 u8 reserved_at_180[0x80]; 4257 }; 4258 4259 enum { 4260 MLX5_DCTC_STATE_ACTIVE = 0x0, 4261 MLX5_DCTC_STATE_DRAINING = 0x1, 4262 MLX5_DCTC_STATE_DRAINED = 0x2, 4263 }; 4264 4265 enum { 4266 MLX5_DCTC_CS_RES_DISABLE = 0x0, 4267 MLX5_DCTC_CS_RES_NA = 0x1, 4268 MLX5_DCTC_CS_RES_UP_TO_64B = 0x2, 4269 }; 4270 4271 enum { 4272 MLX5_DCTC_MTU_256_BYTES = 0x1, 4273 MLX5_DCTC_MTU_512_BYTES = 0x2, 4274 MLX5_DCTC_MTU_1K_BYTES = 0x3, 4275 MLX5_DCTC_MTU_2K_BYTES = 0x4, 4276 MLX5_DCTC_MTU_4K_BYTES = 0x5, 4277 }; 4278 4279 struct mlx5_ifc_dctc_bits { 4280 u8 reserved_at_0[0x4]; 4281 u8 state[0x4]; 4282 u8 reserved_at_8[0x18]; 4283 4284 u8 reserved_at_20[0x8]; 4285 u8 user_index[0x18]; 4286 4287 u8 reserved_at_40[0x8]; 4288 u8 cqn[0x18]; 4289 4290 u8 counter_set_id[0x8]; 4291 u8 atomic_mode[0x4]; 4292 u8 rre[0x1]; 4293 u8 rwe[0x1]; 4294 u8 rae[0x1]; 4295 u8 atomic_like_write_en[0x1]; 4296 u8 latency_sensitive[0x1]; 4297 u8 rlky[0x1]; 4298 u8 free_ar[0x1]; 4299 u8 reserved_at_73[0xd]; 4300 4301 u8 reserved_at_80[0x8]; 4302 u8 cs_res[0x8]; 4303 u8 reserved_at_90[0x3]; 4304 u8 min_rnr_nak[0x5]; 4305 u8 reserved_at_98[0x8]; 4306 4307 u8 reserved_at_a0[0x8]; 4308 u8 srqn_xrqn[0x18]; 4309 4310 u8 reserved_at_c0[0x8]; 4311 u8 pd[0x18]; 4312 4313 u8 tclass[0x8]; 4314 u8 reserved_at_e8[0x4]; 4315 u8 flow_label[0x14]; 4316 4317 u8 dc_access_key[0x40]; 4318 4319 u8 reserved_at_140[0x5]; 4320 u8 mtu[0x3]; 4321 u8 port[0x8]; 4322 u8 pkey_index[0x10]; 4323 4324 u8 reserved_at_160[0x8]; 4325 u8 my_addr_index[0x8]; 4326 u8 reserved_at_170[0x8]; 4327 u8 hop_limit[0x8]; 4328 4329 u8 dc_access_key_violation_count[0x20]; 4330 4331 u8 reserved_at_1a0[0x14]; 4332 u8 dei_cfi[0x1]; 4333 u8 eth_prio[0x3]; 4334 u8 ecn[0x2]; 4335 u8 dscp[0x6]; 4336 4337 u8 reserved_at_1c0[0x20]; 4338 u8 ece[0x20]; 4339 }; 4340 4341 enum { 4342 MLX5_CQC_STATUS_OK = 0x0, 4343 MLX5_CQC_STATUS_CQ_OVERFLOW = 0x9, 4344 MLX5_CQC_STATUS_CQ_WRITE_FAIL = 0xa, 4345 }; 4346 4347 enum { 4348 MLX5_CQC_CQE_SZ_64_BYTES = 0x0, 4349 MLX5_CQC_CQE_SZ_128_BYTES = 0x1, 4350 }; 4351 4352 enum { 4353 MLX5_CQC_ST_SOLICITED_NOTIFICATION_REQUEST_ARMED = 0x6, 4354 MLX5_CQC_ST_NOTIFICATION_REQUEST_ARMED = 0x9, 4355 MLX5_CQC_ST_FIRED = 0xa, 4356 }; 4357 4358 enum { 4359 MLX5_CQ_PERIOD_MODE_START_FROM_EQE = 0x0, 4360 MLX5_CQ_PERIOD_MODE_START_FROM_CQE = 0x1, 4361 MLX5_CQ_PERIOD_NUM_MODES 4362 }; 4363 4364 struct mlx5_ifc_cqc_bits { 4365 u8 status[0x4]; 4366 u8 reserved_at_4[0x2]; 4367 u8 dbr_umem_valid[0x1]; 4368 u8 apu_cq[0x1]; 4369 u8 cqe_sz[0x3]; 4370 u8 cc[0x1]; 4371 u8 reserved_at_c[0x1]; 4372 u8 scqe_break_moderation_en[0x1]; 4373 u8 oi[0x1]; 4374 u8 cq_period_mode[0x2]; 4375 u8 cqe_comp_en[0x1]; 4376 u8 mini_cqe_res_format[0x2]; 4377 u8 st[0x4]; 4378 u8 reserved_at_18[0x6]; 4379 u8 cqe_compression_layout[0x2]; 4380 4381 u8 reserved_at_20[0x20]; 4382 4383 u8 reserved_at_40[0x14]; 4384 u8 page_offset[0x6]; 4385 u8 reserved_at_5a[0x6]; 4386 4387 u8 reserved_at_60[0x3]; 4388 u8 log_cq_size[0x5]; 4389 u8 uar_page[0x18]; 4390 4391 u8 reserved_at_80[0x4]; 4392 u8 cq_period[0xc]; 4393 u8 cq_max_count[0x10]; 4394 4395 u8 c_eqn_or_apu_element[0x20]; 4396 4397 u8 reserved_at_c0[0x3]; 4398 u8 log_page_size[0x5]; 4399 u8 reserved_at_c8[0x18]; 4400 4401 u8 reserved_at_e0[0x20]; 4402 4403 u8 reserved_at_100[0x8]; 4404 u8 last_notified_index[0x18]; 4405 4406 u8 reserved_at_120[0x8]; 4407 u8 last_solicit_index[0x18]; 4408 4409 u8 reserved_at_140[0x8]; 4410 u8 consumer_counter[0x18]; 4411 4412 u8 reserved_at_160[0x8]; 4413 u8 producer_counter[0x18]; 4414 4415 u8 reserved_at_180[0x40]; 4416 4417 u8 dbr_addr[0x40]; 4418 }; 4419 4420 union mlx5_ifc_cong_control_roce_ecn_auto_bits { 4421 struct mlx5_ifc_cong_control_802_1qau_rp_bits cong_control_802_1qau_rp; 4422 struct mlx5_ifc_cong_control_r_roce_ecn_rp_bits cong_control_r_roce_ecn_rp; 4423 struct mlx5_ifc_cong_control_r_roce_ecn_np_bits cong_control_r_roce_ecn_np; 4424 struct mlx5_ifc_cong_control_r_roce_general_bits cong_control_r_roce_general; 4425 u8 reserved_at_0[0x800]; 4426 }; 4427 4428 struct mlx5_ifc_query_adapter_param_block_bits { 4429 u8 reserved_at_0[0xc0]; 4430 4431 u8 reserved_at_c0[0x8]; 4432 u8 ieee_vendor_id[0x18]; 4433 4434 u8 reserved_at_e0[0x10]; 4435 u8 vsd_vendor_id[0x10]; 4436 4437 u8 vsd[208][0x8]; 4438 4439 u8 vsd_contd_psid[16][0x8]; 4440 }; 4441 4442 enum { 4443 MLX5_XRQC_STATE_GOOD = 0x0, 4444 MLX5_XRQC_STATE_ERROR = 0x1, 4445 }; 4446 4447 enum { 4448 MLX5_XRQC_TOPOLOGY_NO_SPECIAL_TOPOLOGY = 0x0, 4449 MLX5_XRQC_TOPOLOGY_TAG_MATCHING = 0x1, 4450 }; 4451 4452 enum { 4453 MLX5_XRQC_OFFLOAD_RNDV = 0x1, 4454 }; 4455 4456 struct mlx5_ifc_tag_matching_topology_context_bits { 4457 u8 log_matching_list_sz[0x4]; 4458 u8 reserved_at_4[0xc]; 4459 u8 append_next_index[0x10]; 4460 4461 u8 sw_phase_cnt[0x10]; 4462 u8 hw_phase_cnt[0x10]; 4463 4464 u8 reserved_at_40[0x40]; 4465 }; 4466 4467 struct mlx5_ifc_xrqc_bits { 4468 u8 state[0x4]; 4469 u8 rlkey[0x1]; 4470 u8 reserved_at_5[0xf]; 4471 u8 topology[0x4]; 4472 u8 reserved_at_18[0x4]; 4473 u8 offload[0x4]; 4474 4475 u8 reserved_at_20[0x8]; 4476 u8 user_index[0x18]; 4477 4478 u8 reserved_at_40[0x8]; 4479 u8 cqn[0x18]; 4480 4481 u8 reserved_at_60[0xa0]; 4482 4483 struct mlx5_ifc_tag_matching_topology_context_bits tag_matching_topology_context; 4484 4485 u8 reserved_at_180[0x280]; 4486 4487 struct mlx5_ifc_wq_bits wq; 4488 }; 4489 4490 union mlx5_ifc_modify_field_select_resize_field_select_auto_bits { 4491 struct mlx5_ifc_modify_field_select_bits modify_field_select; 4492 struct mlx5_ifc_resize_field_select_bits resize_field_select; 4493 u8 reserved_at_0[0x20]; 4494 }; 4495 4496 union mlx5_ifc_field_select_802_1_r_roce_auto_bits { 4497 struct mlx5_ifc_field_select_802_1qau_rp_bits field_select_802_1qau_rp; 4498 struct mlx5_ifc_field_select_r_roce_rp_bits field_select_r_roce_rp; 4499 struct mlx5_ifc_field_select_r_roce_np_bits field_select_r_roce_np; 4500 u8 reserved_at_0[0x20]; 4501 }; 4502 4503 union mlx5_ifc_eth_cntrs_grp_data_layout_auto_bits { 4504 struct mlx5_ifc_eth_802_3_cntrs_grp_data_layout_bits eth_802_3_cntrs_grp_data_layout; 4505 struct mlx5_ifc_eth_2863_cntrs_grp_data_layout_bits eth_2863_cntrs_grp_data_layout; 4506 struct mlx5_ifc_eth_2819_cntrs_grp_data_layout_bits eth_2819_cntrs_grp_data_layout; 4507 struct mlx5_ifc_eth_3635_cntrs_grp_data_layout_bits eth_3635_cntrs_grp_data_layout; 4508 struct mlx5_ifc_eth_extended_cntrs_grp_data_layout_bits eth_extended_cntrs_grp_data_layout; 4509 struct mlx5_ifc_eth_per_prio_grp_data_layout_bits eth_per_prio_grp_data_layout; 4510 struct mlx5_ifc_eth_per_tc_prio_grp_data_layout_bits eth_per_tc_prio_grp_data_layout; 4511 struct mlx5_ifc_eth_per_tc_congest_prio_grp_data_layout_bits eth_per_tc_congest_prio_grp_data_layout; 4512 struct mlx5_ifc_ib_port_cntrs_grp_data_layout_bits ib_port_cntrs_grp_data_layout; 4513 struct mlx5_ifc_phys_layer_cntrs_bits phys_layer_cntrs; 4514 struct mlx5_ifc_phys_layer_statistical_cntrs_bits phys_layer_statistical_cntrs; 4515 u8 reserved_at_0[0x7c0]; 4516 }; 4517 4518 union mlx5_ifc_pcie_cntrs_grp_data_layout_auto_bits { 4519 struct mlx5_ifc_pcie_perf_cntrs_grp_data_layout_bits pcie_perf_cntrs_grp_data_layout; 4520 u8 reserved_at_0[0x7c0]; 4521 }; 4522 4523 union mlx5_ifc_event_auto_bits { 4524 struct mlx5_ifc_comp_event_bits comp_event; 4525 struct mlx5_ifc_dct_events_bits dct_events; 4526 struct mlx5_ifc_qp_events_bits qp_events; 4527 struct mlx5_ifc_wqe_associated_page_fault_event_bits wqe_associated_page_fault_event; 4528 struct mlx5_ifc_rdma_page_fault_event_bits rdma_page_fault_event; 4529 struct mlx5_ifc_cq_error_bits cq_error; 4530 struct mlx5_ifc_dropped_packet_logged_bits dropped_packet_logged; 4531 struct mlx5_ifc_port_state_change_event_bits port_state_change_event; 4532 struct mlx5_ifc_gpio_event_bits gpio_event; 4533 struct mlx5_ifc_db_bf_congestion_event_bits db_bf_congestion_event; 4534 struct mlx5_ifc_stall_vl_event_bits stall_vl_event; 4535 struct mlx5_ifc_cmd_inter_comp_event_bits cmd_inter_comp_event; 4536 u8 reserved_at_0[0xe0]; 4537 }; 4538 4539 struct mlx5_ifc_health_buffer_bits { 4540 u8 reserved_at_0[0x100]; 4541 4542 u8 assert_existptr[0x20]; 4543 4544 u8 assert_callra[0x20]; 4545 4546 u8 reserved_at_140[0x20]; 4547 4548 u8 time[0x20]; 4549 4550 u8 fw_version[0x20]; 4551 4552 u8 hw_id[0x20]; 4553 4554 u8 rfr[0x1]; 4555 u8 reserved_at_1c1[0x3]; 4556 u8 valid[0x1]; 4557 u8 severity[0x3]; 4558 u8 reserved_at_1c8[0x18]; 4559 4560 u8 irisc_index[0x8]; 4561 u8 synd[0x8]; 4562 u8 ext_synd[0x10]; 4563 }; 4564 4565 struct mlx5_ifc_register_loopback_control_bits { 4566 u8 no_lb[0x1]; 4567 u8 reserved_at_1[0x7]; 4568 u8 port[0x8]; 4569 u8 reserved_at_10[0x10]; 4570 4571 u8 reserved_at_20[0x60]; 4572 }; 4573 4574 struct mlx5_ifc_vport_tc_element_bits { 4575 u8 traffic_class[0x4]; 4576 u8 reserved_at_4[0xc]; 4577 u8 vport_number[0x10]; 4578 }; 4579 4580 struct mlx5_ifc_vport_element_bits { 4581 u8 reserved_at_0[0x10]; 4582 u8 vport_number[0x10]; 4583 }; 4584 4585 enum { 4586 TSAR_ELEMENT_TSAR_TYPE_DWRR = 0x0, 4587 TSAR_ELEMENT_TSAR_TYPE_ROUND_ROBIN = 0x1, 4588 TSAR_ELEMENT_TSAR_TYPE_ETS = 0x2, 4589 }; 4590 4591 struct mlx5_ifc_tsar_element_bits { 4592 u8 reserved_at_0[0x8]; 4593 u8 tsar_type[0x8]; 4594 u8 reserved_at_10[0x10]; 4595 }; 4596 4597 enum { 4598 MLX5_TEARDOWN_HCA_OUT_FORCE_STATE_SUCCESS = 0x0, 4599 MLX5_TEARDOWN_HCA_OUT_FORCE_STATE_FAIL = 0x1, 4600 }; 4601 4602 struct mlx5_ifc_teardown_hca_out_bits { 4603 u8 status[0x8]; 4604 u8 reserved_at_8[0x18]; 4605 4606 u8 syndrome[0x20]; 4607 4608 u8 reserved_at_40[0x3f]; 4609 4610 u8 state[0x1]; 4611 }; 4612 4613 enum { 4614 MLX5_TEARDOWN_HCA_IN_PROFILE_GRACEFUL_CLOSE = 0x0, 4615 MLX5_TEARDOWN_HCA_IN_PROFILE_FORCE_CLOSE = 0x1, 4616 MLX5_TEARDOWN_HCA_IN_PROFILE_PREPARE_FAST_TEARDOWN = 0x2, 4617 }; 4618 4619 struct mlx5_ifc_teardown_hca_in_bits { 4620 u8 opcode[0x10]; 4621 u8 reserved_at_10[0x10]; 4622 4623 u8 reserved_at_20[0x10]; 4624 u8 op_mod[0x10]; 4625 4626 u8 reserved_at_40[0x10]; 4627 u8 profile[0x10]; 4628 4629 u8 reserved_at_60[0x20]; 4630 }; 4631 4632 struct mlx5_ifc_sqerr2rts_qp_out_bits { 4633 u8 status[0x8]; 4634 u8 reserved_at_8[0x18]; 4635 4636 u8 syndrome[0x20]; 4637 4638 u8 reserved_at_40[0x40]; 4639 }; 4640 4641 struct mlx5_ifc_sqerr2rts_qp_in_bits { 4642 u8 opcode[0x10]; 4643 u8 uid[0x10]; 4644 4645 u8 reserved_at_20[0x10]; 4646 u8 op_mod[0x10]; 4647 4648 u8 reserved_at_40[0x8]; 4649 u8 qpn[0x18]; 4650 4651 u8 reserved_at_60[0x20]; 4652 4653 u8 opt_param_mask[0x20]; 4654 4655 u8 reserved_at_a0[0x20]; 4656 4657 struct mlx5_ifc_qpc_bits qpc; 4658 4659 u8 reserved_at_800[0x80]; 4660 }; 4661 4662 struct mlx5_ifc_sqd2rts_qp_out_bits { 4663 u8 status[0x8]; 4664 u8 reserved_at_8[0x18]; 4665 4666 u8 syndrome[0x20]; 4667 4668 u8 reserved_at_40[0x40]; 4669 }; 4670 4671 struct mlx5_ifc_sqd2rts_qp_in_bits { 4672 u8 opcode[0x10]; 4673 u8 uid[0x10]; 4674 4675 u8 reserved_at_20[0x10]; 4676 u8 op_mod[0x10]; 4677 4678 u8 reserved_at_40[0x8]; 4679 u8 qpn[0x18]; 4680 4681 u8 reserved_at_60[0x20]; 4682 4683 u8 opt_param_mask[0x20]; 4684 4685 u8 reserved_at_a0[0x20]; 4686 4687 struct mlx5_ifc_qpc_bits qpc; 4688 4689 u8 reserved_at_800[0x80]; 4690 }; 4691 4692 struct mlx5_ifc_set_roce_address_out_bits { 4693 u8 status[0x8]; 4694 u8 reserved_at_8[0x18]; 4695 4696 u8 syndrome[0x20]; 4697 4698 u8 reserved_at_40[0x40]; 4699 }; 4700 4701 struct mlx5_ifc_set_roce_address_in_bits { 4702 u8 opcode[0x10]; 4703 u8 reserved_at_10[0x10]; 4704 4705 u8 reserved_at_20[0x10]; 4706 u8 op_mod[0x10]; 4707 4708 u8 roce_address_index[0x10]; 4709 u8 reserved_at_50[0xc]; 4710 u8 vhca_port_num[0x4]; 4711 4712 u8 reserved_at_60[0x20]; 4713 4714 struct mlx5_ifc_roce_addr_layout_bits roce_address; 4715 }; 4716 4717 struct mlx5_ifc_set_mad_demux_out_bits { 4718 u8 status[0x8]; 4719 u8 reserved_at_8[0x18]; 4720 4721 u8 syndrome[0x20]; 4722 4723 u8 reserved_at_40[0x40]; 4724 }; 4725 4726 enum { 4727 MLX5_SET_MAD_DEMUX_IN_DEMUX_MODE_PASS_ALL = 0x0, 4728 MLX5_SET_MAD_DEMUX_IN_DEMUX_MODE_SELECTIVE = 0x2, 4729 }; 4730 4731 struct mlx5_ifc_set_mad_demux_in_bits { 4732 u8 opcode[0x10]; 4733 u8 reserved_at_10[0x10]; 4734 4735 u8 reserved_at_20[0x10]; 4736 u8 op_mod[0x10]; 4737 4738 u8 reserved_at_40[0x20]; 4739 4740 u8 reserved_at_60[0x6]; 4741 u8 demux_mode[0x2]; 4742 u8 reserved_at_68[0x18]; 4743 }; 4744 4745 struct mlx5_ifc_set_l2_table_entry_out_bits { 4746 u8 status[0x8]; 4747 u8 reserved_at_8[0x18]; 4748 4749 u8 syndrome[0x20]; 4750 4751 u8 reserved_at_40[0x40]; 4752 }; 4753 4754 struct mlx5_ifc_set_l2_table_entry_in_bits { 4755 u8 opcode[0x10]; 4756 u8 reserved_at_10[0x10]; 4757 4758 u8 reserved_at_20[0x10]; 4759 u8 op_mod[0x10]; 4760 4761 u8 reserved_at_40[0x60]; 4762 4763 u8 reserved_at_a0[0x8]; 4764 u8 table_index[0x18]; 4765 4766 u8 reserved_at_c0[0x20]; 4767 4768 u8 reserved_at_e0[0x10]; 4769 u8 silent_mode_valid[0x1]; 4770 u8 silent_mode[0x1]; 4771 u8 reserved_at_f2[0x1]; 4772 u8 vlan_valid[0x1]; 4773 u8 vlan[0xc]; 4774 4775 struct mlx5_ifc_mac_address_layout_bits mac_address; 4776 4777 u8 reserved_at_140[0xc0]; 4778 }; 4779 4780 struct mlx5_ifc_set_issi_out_bits { 4781 u8 status[0x8]; 4782 u8 reserved_at_8[0x18]; 4783 4784 u8 syndrome[0x20]; 4785 4786 u8 reserved_at_40[0x40]; 4787 }; 4788 4789 struct mlx5_ifc_set_issi_in_bits { 4790 u8 opcode[0x10]; 4791 u8 reserved_at_10[0x10]; 4792 4793 u8 reserved_at_20[0x10]; 4794 u8 op_mod[0x10]; 4795 4796 u8 reserved_at_40[0x10]; 4797 u8 current_issi[0x10]; 4798 4799 u8 reserved_at_60[0x20]; 4800 }; 4801 4802 struct mlx5_ifc_set_hca_cap_out_bits { 4803 u8 status[0x8]; 4804 u8 reserved_at_8[0x18]; 4805 4806 u8 syndrome[0x20]; 4807 4808 u8 reserved_at_40[0x40]; 4809 }; 4810 4811 struct mlx5_ifc_set_hca_cap_in_bits { 4812 u8 opcode[0x10]; 4813 u8 reserved_at_10[0x10]; 4814 4815 u8 reserved_at_20[0x10]; 4816 u8 op_mod[0x10]; 4817 4818 u8 other_function[0x1]; 4819 u8 ec_vf_function[0x1]; 4820 u8 reserved_at_42[0xe]; 4821 u8 function_id[0x10]; 4822 4823 u8 reserved_at_60[0x20]; 4824 4825 union mlx5_ifc_hca_cap_union_bits capability; 4826 }; 4827 4828 enum { 4829 MLX5_SET_FTE_MODIFY_ENABLE_MASK_ACTION = 0x0, 4830 MLX5_SET_FTE_MODIFY_ENABLE_MASK_FLOW_TAG = 0x1, 4831 MLX5_SET_FTE_MODIFY_ENABLE_MASK_DESTINATION_LIST = 0x2, 4832 MLX5_SET_FTE_MODIFY_ENABLE_MASK_FLOW_COUNTERS = 0x3, 4833 MLX5_SET_FTE_MODIFY_ENABLE_MASK_IPSEC_OBJ_ID = 0x4 4834 }; 4835 4836 struct mlx5_ifc_set_fte_out_bits { 4837 u8 status[0x8]; 4838 u8 reserved_at_8[0x18]; 4839 4840 u8 syndrome[0x20]; 4841 4842 u8 reserved_at_40[0x40]; 4843 }; 4844 4845 struct mlx5_ifc_set_fte_in_bits { 4846 u8 opcode[0x10]; 4847 u8 reserved_at_10[0x10]; 4848 4849 u8 reserved_at_20[0x10]; 4850 u8 op_mod[0x10]; 4851 4852 u8 other_vport[0x1]; 4853 u8 reserved_at_41[0xf]; 4854 u8 vport_number[0x10]; 4855 4856 u8 reserved_at_60[0x20]; 4857 4858 u8 table_type[0x8]; 4859 u8 reserved_at_88[0x18]; 4860 4861 u8 reserved_at_a0[0x8]; 4862 u8 table_id[0x18]; 4863 4864 u8 ignore_flow_level[0x1]; 4865 u8 reserved_at_c1[0x17]; 4866 u8 modify_enable_mask[0x8]; 4867 4868 u8 reserved_at_e0[0x20]; 4869 4870 u8 flow_index[0x20]; 4871 4872 u8 reserved_at_120[0xe0]; 4873 4874 struct mlx5_ifc_flow_context_bits flow_context; 4875 }; 4876 4877 struct mlx5_ifc_rts2rts_qp_out_bits { 4878 u8 status[0x8]; 4879 u8 reserved_at_8[0x18]; 4880 4881 u8 syndrome[0x20]; 4882 4883 u8 reserved_at_40[0x20]; 4884 u8 ece[0x20]; 4885 }; 4886 4887 struct mlx5_ifc_rts2rts_qp_in_bits { 4888 u8 opcode[0x10]; 4889 u8 uid[0x10]; 4890 4891 u8 reserved_at_20[0x10]; 4892 u8 op_mod[0x10]; 4893 4894 u8 reserved_at_40[0x8]; 4895 u8 qpn[0x18]; 4896 4897 u8 reserved_at_60[0x20]; 4898 4899 u8 opt_param_mask[0x20]; 4900 4901 u8 ece[0x20]; 4902 4903 struct mlx5_ifc_qpc_bits qpc; 4904 4905 u8 reserved_at_800[0x80]; 4906 }; 4907 4908 struct mlx5_ifc_rtr2rts_qp_out_bits { 4909 u8 status[0x8]; 4910 u8 reserved_at_8[0x18]; 4911 4912 u8 syndrome[0x20]; 4913 4914 u8 reserved_at_40[0x20]; 4915 u8 ece[0x20]; 4916 }; 4917 4918 struct mlx5_ifc_rtr2rts_qp_in_bits { 4919 u8 opcode[0x10]; 4920 u8 uid[0x10]; 4921 4922 u8 reserved_at_20[0x10]; 4923 u8 op_mod[0x10]; 4924 4925 u8 reserved_at_40[0x8]; 4926 u8 qpn[0x18]; 4927 4928 u8 reserved_at_60[0x20]; 4929 4930 u8 opt_param_mask[0x20]; 4931 4932 u8 ece[0x20]; 4933 4934 struct mlx5_ifc_qpc_bits qpc; 4935 4936 u8 reserved_at_800[0x80]; 4937 }; 4938 4939 struct mlx5_ifc_rst2init_qp_out_bits { 4940 u8 status[0x8]; 4941 u8 reserved_at_8[0x18]; 4942 4943 u8 syndrome[0x20]; 4944 4945 u8 reserved_at_40[0x20]; 4946 u8 ece[0x20]; 4947 }; 4948 4949 struct mlx5_ifc_rst2init_qp_in_bits { 4950 u8 opcode[0x10]; 4951 u8 uid[0x10]; 4952 4953 u8 reserved_at_20[0x10]; 4954 u8 op_mod[0x10]; 4955 4956 u8 reserved_at_40[0x8]; 4957 u8 qpn[0x18]; 4958 4959 u8 reserved_at_60[0x20]; 4960 4961 u8 opt_param_mask[0x20]; 4962 4963 u8 ece[0x20]; 4964 4965 struct mlx5_ifc_qpc_bits qpc; 4966 4967 u8 reserved_at_800[0x80]; 4968 }; 4969 4970 struct mlx5_ifc_query_xrq_out_bits { 4971 u8 status[0x8]; 4972 u8 reserved_at_8[0x18]; 4973 4974 u8 syndrome[0x20]; 4975 4976 u8 reserved_at_40[0x40]; 4977 4978 struct mlx5_ifc_xrqc_bits xrq_context; 4979 }; 4980 4981 struct mlx5_ifc_query_xrq_in_bits { 4982 u8 opcode[0x10]; 4983 u8 reserved_at_10[0x10]; 4984 4985 u8 reserved_at_20[0x10]; 4986 u8 op_mod[0x10]; 4987 4988 u8 reserved_at_40[0x8]; 4989 u8 xrqn[0x18]; 4990 4991 u8 reserved_at_60[0x20]; 4992 }; 4993 4994 struct mlx5_ifc_query_xrc_srq_out_bits { 4995 u8 status[0x8]; 4996 u8 reserved_at_8[0x18]; 4997 4998 u8 syndrome[0x20]; 4999 5000 u8 reserved_at_40[0x40]; 5001 5002 struct mlx5_ifc_xrc_srqc_bits xrc_srq_context_entry; 5003 5004 u8 reserved_at_280[0x600]; 5005 5006 u8 pas[][0x40]; 5007 }; 5008 5009 struct mlx5_ifc_query_xrc_srq_in_bits { 5010 u8 opcode[0x10]; 5011 u8 reserved_at_10[0x10]; 5012 5013 u8 reserved_at_20[0x10]; 5014 u8 op_mod[0x10]; 5015 5016 u8 reserved_at_40[0x8]; 5017 u8 xrc_srqn[0x18]; 5018 5019 u8 reserved_at_60[0x20]; 5020 }; 5021 5022 enum { 5023 MLX5_QUERY_VPORT_STATE_OUT_STATE_DOWN = 0x0, 5024 MLX5_QUERY_VPORT_STATE_OUT_STATE_UP = 0x1, 5025 }; 5026 5027 struct mlx5_ifc_query_vport_state_out_bits { 5028 u8 status[0x8]; 5029 u8 reserved_at_8[0x18]; 5030 5031 u8 syndrome[0x20]; 5032 5033 u8 reserved_at_40[0x20]; 5034 5035 u8 reserved_at_60[0x18]; 5036 u8 admin_state[0x4]; 5037 u8 state[0x4]; 5038 }; 5039 5040 enum { 5041 MLX5_VPORT_STATE_OP_MOD_VNIC_VPORT = 0x0, 5042 MLX5_VPORT_STATE_OP_MOD_ESW_VPORT = 0x1, 5043 MLX5_VPORT_STATE_OP_MOD_UPLINK = 0x2, 5044 }; 5045 5046 struct mlx5_ifc_arm_monitor_counter_in_bits { 5047 u8 opcode[0x10]; 5048 u8 uid[0x10]; 5049 5050 u8 reserved_at_20[0x10]; 5051 u8 op_mod[0x10]; 5052 5053 u8 reserved_at_40[0x20]; 5054 5055 u8 reserved_at_60[0x20]; 5056 }; 5057 5058 struct mlx5_ifc_arm_monitor_counter_out_bits { 5059 u8 status[0x8]; 5060 u8 reserved_at_8[0x18]; 5061 5062 u8 syndrome[0x20]; 5063 5064 u8 reserved_at_40[0x40]; 5065 }; 5066 5067 enum { 5068 MLX5_QUERY_MONITOR_CNT_TYPE_PPCNT = 0x0, 5069 MLX5_QUERY_MONITOR_CNT_TYPE_Q_COUNTER = 0x1, 5070 }; 5071 5072 enum mlx5_monitor_counter_ppcnt { 5073 MLX5_QUERY_MONITOR_PPCNT_IN_RANGE_LENGTH_ERRORS = 0x0, 5074 MLX5_QUERY_MONITOR_PPCNT_OUT_OF_RANGE_LENGTH_FIELD = 0x1, 5075 MLX5_QUERY_MONITOR_PPCNT_FRAME_TOO_LONG_ERRORS = 0x2, 5076 MLX5_QUERY_MONITOR_PPCNT_FRAME_CHECK_SEQUENCE_ERRORS = 0x3, 5077 MLX5_QUERY_MONITOR_PPCNT_ALIGNMENT_ERRORS = 0x4, 5078 MLX5_QUERY_MONITOR_PPCNT_IF_OUT_DISCARDS = 0x5, 5079 }; 5080 5081 enum { 5082 MLX5_QUERY_MONITOR_Q_COUNTER_RX_OUT_OF_BUFFER = 0x4, 5083 }; 5084 5085 struct mlx5_ifc_monitor_counter_output_bits { 5086 u8 reserved_at_0[0x4]; 5087 u8 type[0x4]; 5088 u8 reserved_at_8[0x8]; 5089 u8 counter[0x10]; 5090 5091 u8 counter_group_id[0x20]; 5092 }; 5093 5094 #define MLX5_CMD_SET_MONITOR_NUM_PPCNT_COUNTER_SET1 (6) 5095 #define MLX5_CMD_SET_MONITOR_NUM_Q_COUNTERS_SET1 (1) 5096 #define MLX5_CMD_SET_MONITOR_NUM_COUNTER (MLX5_CMD_SET_MONITOR_NUM_PPCNT_COUNTER_SET1 +\ 5097 MLX5_CMD_SET_MONITOR_NUM_Q_COUNTERS_SET1) 5098 5099 struct mlx5_ifc_set_monitor_counter_in_bits { 5100 u8 opcode[0x10]; 5101 u8 uid[0x10]; 5102 5103 u8 reserved_at_20[0x10]; 5104 u8 op_mod[0x10]; 5105 5106 u8 reserved_at_40[0x10]; 5107 u8 num_of_counters[0x10]; 5108 5109 u8 reserved_at_60[0x20]; 5110 5111 struct mlx5_ifc_monitor_counter_output_bits monitor_counter[MLX5_CMD_SET_MONITOR_NUM_COUNTER]; 5112 }; 5113 5114 struct mlx5_ifc_set_monitor_counter_out_bits { 5115 u8 status[0x8]; 5116 u8 reserved_at_8[0x18]; 5117 5118 u8 syndrome[0x20]; 5119 5120 u8 reserved_at_40[0x40]; 5121 }; 5122 5123 struct mlx5_ifc_query_vport_state_in_bits { 5124 u8 opcode[0x10]; 5125 u8 reserved_at_10[0x10]; 5126 5127 u8 reserved_at_20[0x10]; 5128 u8 op_mod[0x10]; 5129 5130 u8 other_vport[0x1]; 5131 u8 reserved_at_41[0xf]; 5132 u8 vport_number[0x10]; 5133 5134 u8 reserved_at_60[0x20]; 5135 }; 5136 5137 struct mlx5_ifc_query_vnic_env_out_bits { 5138 u8 status[0x8]; 5139 u8 reserved_at_8[0x18]; 5140 5141 u8 syndrome[0x20]; 5142 5143 u8 reserved_at_40[0x40]; 5144 5145 struct mlx5_ifc_vnic_diagnostic_statistics_bits vport_env; 5146 }; 5147 5148 enum { 5149 MLX5_QUERY_VNIC_ENV_IN_OP_MOD_VPORT_DIAG_STATISTICS = 0x0, 5150 }; 5151 5152 struct mlx5_ifc_query_vnic_env_in_bits { 5153 u8 opcode[0x10]; 5154 u8 reserved_at_10[0x10]; 5155 5156 u8 reserved_at_20[0x10]; 5157 u8 op_mod[0x10]; 5158 5159 u8 other_vport[0x1]; 5160 u8 reserved_at_41[0xf]; 5161 u8 vport_number[0x10]; 5162 5163 u8 reserved_at_60[0x20]; 5164 }; 5165 5166 struct mlx5_ifc_query_vport_counter_out_bits { 5167 u8 status[0x8]; 5168 u8 reserved_at_8[0x18]; 5169 5170 u8 syndrome[0x20]; 5171 5172 u8 reserved_at_40[0x40]; 5173 5174 struct mlx5_ifc_traffic_counter_bits received_errors; 5175 5176 struct mlx5_ifc_traffic_counter_bits transmit_errors; 5177 5178 struct mlx5_ifc_traffic_counter_bits received_ib_unicast; 5179 5180 struct mlx5_ifc_traffic_counter_bits transmitted_ib_unicast; 5181 5182 struct mlx5_ifc_traffic_counter_bits received_ib_multicast; 5183 5184 struct mlx5_ifc_traffic_counter_bits transmitted_ib_multicast; 5185 5186 struct mlx5_ifc_traffic_counter_bits received_eth_broadcast; 5187 5188 struct mlx5_ifc_traffic_counter_bits transmitted_eth_broadcast; 5189 5190 struct mlx5_ifc_traffic_counter_bits received_eth_unicast; 5191 5192 struct mlx5_ifc_traffic_counter_bits transmitted_eth_unicast; 5193 5194 struct mlx5_ifc_traffic_counter_bits received_eth_multicast; 5195 5196 struct mlx5_ifc_traffic_counter_bits transmitted_eth_multicast; 5197 5198 struct mlx5_ifc_traffic_counter_bits local_loopback; 5199 5200 u8 reserved_at_700[0x980]; 5201 }; 5202 5203 enum { 5204 MLX5_QUERY_VPORT_COUNTER_IN_OP_MOD_VPORT_COUNTERS = 0x0, 5205 }; 5206 5207 struct mlx5_ifc_query_vport_counter_in_bits { 5208 u8 opcode[0x10]; 5209 u8 reserved_at_10[0x10]; 5210 5211 u8 reserved_at_20[0x10]; 5212 u8 op_mod[0x10]; 5213 5214 u8 other_vport[0x1]; 5215 u8 reserved_at_41[0xb]; 5216 u8 port_num[0x4]; 5217 u8 vport_number[0x10]; 5218 5219 u8 reserved_at_60[0x60]; 5220 5221 u8 clear[0x1]; 5222 u8 reserved_at_c1[0x1f]; 5223 5224 u8 reserved_at_e0[0x20]; 5225 }; 5226 5227 struct mlx5_ifc_query_tis_out_bits { 5228 u8 status[0x8]; 5229 u8 reserved_at_8[0x18]; 5230 5231 u8 syndrome[0x20]; 5232 5233 u8 reserved_at_40[0x40]; 5234 5235 struct mlx5_ifc_tisc_bits tis_context; 5236 }; 5237 5238 struct mlx5_ifc_query_tis_in_bits { 5239 u8 opcode[0x10]; 5240 u8 reserved_at_10[0x10]; 5241 5242 u8 reserved_at_20[0x10]; 5243 u8 op_mod[0x10]; 5244 5245 u8 reserved_at_40[0x8]; 5246 u8 tisn[0x18]; 5247 5248 u8 reserved_at_60[0x20]; 5249 }; 5250 5251 struct mlx5_ifc_query_tir_out_bits { 5252 u8 status[0x8]; 5253 u8 reserved_at_8[0x18]; 5254 5255 u8 syndrome[0x20]; 5256 5257 u8 reserved_at_40[0xc0]; 5258 5259 struct mlx5_ifc_tirc_bits tir_context; 5260 }; 5261 5262 struct mlx5_ifc_query_tir_in_bits { 5263 u8 opcode[0x10]; 5264 u8 reserved_at_10[0x10]; 5265 5266 u8 reserved_at_20[0x10]; 5267 u8 op_mod[0x10]; 5268 5269 u8 reserved_at_40[0x8]; 5270 u8 tirn[0x18]; 5271 5272 u8 reserved_at_60[0x20]; 5273 }; 5274 5275 struct mlx5_ifc_query_srq_out_bits { 5276 u8 status[0x8]; 5277 u8 reserved_at_8[0x18]; 5278 5279 u8 syndrome[0x20]; 5280 5281 u8 reserved_at_40[0x40]; 5282 5283 struct mlx5_ifc_srqc_bits srq_context_entry; 5284 5285 u8 reserved_at_280[0x600]; 5286 5287 u8 pas[][0x40]; 5288 }; 5289 5290 struct mlx5_ifc_query_srq_in_bits { 5291 u8 opcode[0x10]; 5292 u8 reserved_at_10[0x10]; 5293 5294 u8 reserved_at_20[0x10]; 5295 u8 op_mod[0x10]; 5296 5297 u8 reserved_at_40[0x8]; 5298 u8 srqn[0x18]; 5299 5300 u8 reserved_at_60[0x20]; 5301 }; 5302 5303 struct mlx5_ifc_query_sq_out_bits { 5304 u8 status[0x8]; 5305 u8 reserved_at_8[0x18]; 5306 5307 u8 syndrome[0x20]; 5308 5309 u8 reserved_at_40[0xc0]; 5310 5311 struct mlx5_ifc_sqc_bits sq_context; 5312 }; 5313 5314 struct mlx5_ifc_query_sq_in_bits { 5315 u8 opcode[0x10]; 5316 u8 reserved_at_10[0x10]; 5317 5318 u8 reserved_at_20[0x10]; 5319 u8 op_mod[0x10]; 5320 5321 u8 reserved_at_40[0x8]; 5322 u8 sqn[0x18]; 5323 5324 u8 reserved_at_60[0x20]; 5325 }; 5326 5327 struct mlx5_ifc_query_special_contexts_out_bits { 5328 u8 status[0x8]; 5329 u8 reserved_at_8[0x18]; 5330 5331 u8 syndrome[0x20]; 5332 5333 u8 dump_fill_mkey[0x20]; 5334 5335 u8 resd_lkey[0x20]; 5336 5337 u8 null_mkey[0x20]; 5338 5339 u8 terminate_scatter_list_mkey[0x20]; 5340 5341 u8 repeated_mkey[0x20]; 5342 5343 u8 reserved_at_a0[0x20]; 5344 }; 5345 5346 struct mlx5_ifc_query_special_contexts_in_bits { 5347 u8 opcode[0x10]; 5348 u8 reserved_at_10[0x10]; 5349 5350 u8 reserved_at_20[0x10]; 5351 u8 op_mod[0x10]; 5352 5353 u8 reserved_at_40[0x40]; 5354 }; 5355 5356 struct mlx5_ifc_query_scheduling_element_out_bits { 5357 u8 opcode[0x10]; 5358 u8 reserved_at_10[0x10]; 5359 5360 u8 reserved_at_20[0x10]; 5361 u8 op_mod[0x10]; 5362 5363 u8 reserved_at_40[0xc0]; 5364 5365 struct mlx5_ifc_scheduling_context_bits scheduling_context; 5366 5367 u8 reserved_at_300[0x100]; 5368 }; 5369 5370 enum { 5371 SCHEDULING_HIERARCHY_E_SWITCH = 0x2, 5372 SCHEDULING_HIERARCHY_NIC = 0x3, 5373 }; 5374 5375 struct mlx5_ifc_query_scheduling_element_in_bits { 5376 u8 opcode[0x10]; 5377 u8 reserved_at_10[0x10]; 5378 5379 u8 reserved_at_20[0x10]; 5380 u8 op_mod[0x10]; 5381 5382 u8 scheduling_hierarchy[0x8]; 5383 u8 reserved_at_48[0x18]; 5384 5385 u8 scheduling_element_id[0x20]; 5386 5387 u8 reserved_at_80[0x180]; 5388 }; 5389 5390 struct mlx5_ifc_query_rqt_out_bits { 5391 u8 status[0x8]; 5392 u8 reserved_at_8[0x18]; 5393 5394 u8 syndrome[0x20]; 5395 5396 u8 reserved_at_40[0xc0]; 5397 5398 struct mlx5_ifc_rqtc_bits rqt_context; 5399 }; 5400 5401 struct mlx5_ifc_query_rqt_in_bits { 5402 u8 opcode[0x10]; 5403 u8 reserved_at_10[0x10]; 5404 5405 u8 reserved_at_20[0x10]; 5406 u8 op_mod[0x10]; 5407 5408 u8 reserved_at_40[0x8]; 5409 u8 rqtn[0x18]; 5410 5411 u8 reserved_at_60[0x20]; 5412 }; 5413 5414 struct mlx5_ifc_query_rq_out_bits { 5415 u8 status[0x8]; 5416 u8 reserved_at_8[0x18]; 5417 5418 u8 syndrome[0x20]; 5419 5420 u8 reserved_at_40[0xc0]; 5421 5422 struct mlx5_ifc_rqc_bits rq_context; 5423 }; 5424 5425 struct mlx5_ifc_query_rq_in_bits { 5426 u8 opcode[0x10]; 5427 u8 reserved_at_10[0x10]; 5428 5429 u8 reserved_at_20[0x10]; 5430 u8 op_mod[0x10]; 5431 5432 u8 reserved_at_40[0x8]; 5433 u8 rqn[0x18]; 5434 5435 u8 reserved_at_60[0x20]; 5436 }; 5437 5438 struct mlx5_ifc_query_roce_address_out_bits { 5439 u8 status[0x8]; 5440 u8 reserved_at_8[0x18]; 5441 5442 u8 syndrome[0x20]; 5443 5444 u8 reserved_at_40[0x40]; 5445 5446 struct mlx5_ifc_roce_addr_layout_bits roce_address; 5447 }; 5448 5449 struct mlx5_ifc_query_roce_address_in_bits { 5450 u8 opcode[0x10]; 5451 u8 reserved_at_10[0x10]; 5452 5453 u8 reserved_at_20[0x10]; 5454 u8 op_mod[0x10]; 5455 5456 u8 roce_address_index[0x10]; 5457 u8 reserved_at_50[0xc]; 5458 u8 vhca_port_num[0x4]; 5459 5460 u8 reserved_at_60[0x20]; 5461 }; 5462 5463 struct mlx5_ifc_query_rmp_out_bits { 5464 u8 status[0x8]; 5465 u8 reserved_at_8[0x18]; 5466 5467 u8 syndrome[0x20]; 5468 5469 u8 reserved_at_40[0xc0]; 5470 5471 struct mlx5_ifc_rmpc_bits rmp_context; 5472 }; 5473 5474 struct mlx5_ifc_query_rmp_in_bits { 5475 u8 opcode[0x10]; 5476 u8 reserved_at_10[0x10]; 5477 5478 u8 reserved_at_20[0x10]; 5479 u8 op_mod[0x10]; 5480 5481 u8 reserved_at_40[0x8]; 5482 u8 rmpn[0x18]; 5483 5484 u8 reserved_at_60[0x20]; 5485 }; 5486 5487 struct mlx5_ifc_cqe_error_syndrome_bits { 5488 u8 hw_error_syndrome[0x8]; 5489 u8 hw_syndrome_type[0x4]; 5490 u8 reserved_at_c[0x4]; 5491 u8 vendor_error_syndrome[0x8]; 5492 u8 syndrome[0x8]; 5493 }; 5494 5495 struct mlx5_ifc_qp_context_extension_bits { 5496 u8 reserved_at_0[0x60]; 5497 5498 struct mlx5_ifc_cqe_error_syndrome_bits error_syndrome; 5499 5500 u8 reserved_at_80[0x580]; 5501 }; 5502 5503 struct mlx5_ifc_qpc_extension_and_pas_list_in_bits { 5504 struct mlx5_ifc_qp_context_extension_bits qpc_data_extension; 5505 5506 u8 pas[0][0x40]; 5507 }; 5508 5509 struct mlx5_ifc_qp_pas_list_in_bits { 5510 struct mlx5_ifc_cmd_pas_bits pas[0]; 5511 }; 5512 5513 union mlx5_ifc_qp_pas_or_qpc_ext_and_pas_bits { 5514 struct mlx5_ifc_qp_pas_list_in_bits qp_pas_list; 5515 struct mlx5_ifc_qpc_extension_and_pas_list_in_bits qpc_ext_and_pas_list; 5516 }; 5517 5518 struct mlx5_ifc_query_qp_out_bits { 5519 u8 status[0x8]; 5520 u8 reserved_at_8[0x18]; 5521 5522 u8 syndrome[0x20]; 5523 5524 u8 reserved_at_40[0x40]; 5525 5526 u8 opt_param_mask[0x20]; 5527 5528 u8 ece[0x20]; 5529 5530 struct mlx5_ifc_qpc_bits qpc; 5531 5532 u8 reserved_at_800[0x80]; 5533 5534 union mlx5_ifc_qp_pas_or_qpc_ext_and_pas_bits qp_pas_or_qpc_ext_and_pas; 5535 }; 5536 5537 struct mlx5_ifc_query_qp_in_bits { 5538 u8 opcode[0x10]; 5539 u8 reserved_at_10[0x10]; 5540 5541 u8 reserved_at_20[0x10]; 5542 u8 op_mod[0x10]; 5543 5544 u8 qpc_ext[0x1]; 5545 u8 reserved_at_41[0x7]; 5546 u8 qpn[0x18]; 5547 5548 u8 reserved_at_60[0x20]; 5549 }; 5550 5551 struct mlx5_ifc_query_q_counter_out_bits { 5552 u8 status[0x8]; 5553 u8 reserved_at_8[0x18]; 5554 5555 u8 syndrome[0x20]; 5556 5557 u8 reserved_at_40[0x40]; 5558 5559 u8 rx_write_requests[0x20]; 5560 5561 u8 reserved_at_a0[0x20]; 5562 5563 u8 rx_read_requests[0x20]; 5564 5565 u8 reserved_at_e0[0x20]; 5566 5567 u8 rx_atomic_requests[0x20]; 5568 5569 u8 reserved_at_120[0x20]; 5570 5571 u8 rx_dct_connect[0x20]; 5572 5573 u8 reserved_at_160[0x20]; 5574 5575 u8 out_of_buffer[0x20]; 5576 5577 u8 reserved_at_1a0[0x20]; 5578 5579 u8 out_of_sequence[0x20]; 5580 5581 u8 reserved_at_1e0[0x20]; 5582 5583 u8 duplicate_request[0x20]; 5584 5585 u8 reserved_at_220[0x20]; 5586 5587 u8 rnr_nak_retry_err[0x20]; 5588 5589 u8 reserved_at_260[0x20]; 5590 5591 u8 packet_seq_err[0x20]; 5592 5593 u8 reserved_at_2a0[0x20]; 5594 5595 u8 implied_nak_seq_err[0x20]; 5596 5597 u8 reserved_at_2e0[0x20]; 5598 5599 u8 local_ack_timeout_err[0x20]; 5600 5601 u8 reserved_at_320[0xa0]; 5602 5603 u8 resp_local_length_error[0x20]; 5604 5605 u8 req_local_length_error[0x20]; 5606 5607 u8 resp_local_qp_error[0x20]; 5608 5609 u8 local_operation_error[0x20]; 5610 5611 u8 resp_local_protection[0x20]; 5612 5613 u8 req_local_protection[0x20]; 5614 5615 u8 resp_cqe_error[0x20]; 5616 5617 u8 req_cqe_error[0x20]; 5618 5619 u8 req_mw_binding[0x20]; 5620 5621 u8 req_bad_response[0x20]; 5622 5623 u8 req_remote_invalid_request[0x20]; 5624 5625 u8 resp_remote_invalid_request[0x20]; 5626 5627 u8 req_remote_access_errors[0x20]; 5628 5629 u8 resp_remote_access_errors[0x20]; 5630 5631 u8 req_remote_operation_errors[0x20]; 5632 5633 u8 req_transport_retries_exceeded[0x20]; 5634 5635 u8 cq_overflow[0x20]; 5636 5637 u8 resp_cqe_flush_error[0x20]; 5638 5639 u8 req_cqe_flush_error[0x20]; 5640 5641 u8 reserved_at_620[0x20]; 5642 5643 u8 roce_adp_retrans[0x20]; 5644 5645 u8 roce_adp_retrans_to[0x20]; 5646 5647 u8 roce_slow_restart[0x20]; 5648 5649 u8 roce_slow_restart_cnps[0x20]; 5650 5651 u8 roce_slow_restart_trans[0x20]; 5652 5653 u8 reserved_at_6e0[0x120]; 5654 }; 5655 5656 struct mlx5_ifc_query_q_counter_in_bits { 5657 u8 opcode[0x10]; 5658 u8 reserved_at_10[0x10]; 5659 5660 u8 reserved_at_20[0x10]; 5661 u8 op_mod[0x10]; 5662 5663 u8 other_vport[0x1]; 5664 u8 reserved_at_41[0xf]; 5665 u8 vport_number[0x10]; 5666 5667 u8 reserved_at_60[0x60]; 5668 5669 u8 clear[0x1]; 5670 u8 aggregate[0x1]; 5671 u8 reserved_at_c2[0x1e]; 5672 5673 u8 reserved_at_e0[0x18]; 5674 u8 counter_set_id[0x8]; 5675 }; 5676 5677 struct mlx5_ifc_query_pages_out_bits { 5678 u8 status[0x8]; 5679 u8 reserved_at_8[0x18]; 5680 5681 u8 syndrome[0x20]; 5682 5683 u8 embedded_cpu_function[0x1]; 5684 u8 reserved_at_41[0xf]; 5685 u8 function_id[0x10]; 5686 5687 u8 num_pages[0x20]; 5688 }; 5689 5690 enum { 5691 MLX5_QUERY_PAGES_IN_OP_MOD_BOOT_PAGES = 0x1, 5692 MLX5_QUERY_PAGES_IN_OP_MOD_INIT_PAGES = 0x2, 5693 MLX5_QUERY_PAGES_IN_OP_MOD_REGULAR_PAGES = 0x3, 5694 }; 5695 5696 struct mlx5_ifc_query_pages_in_bits { 5697 u8 opcode[0x10]; 5698 u8 reserved_at_10[0x10]; 5699 5700 u8 reserved_at_20[0x10]; 5701 u8 op_mod[0x10]; 5702 5703 u8 embedded_cpu_function[0x1]; 5704 u8 reserved_at_41[0xf]; 5705 u8 function_id[0x10]; 5706 5707 u8 reserved_at_60[0x20]; 5708 }; 5709 5710 struct mlx5_ifc_query_nic_vport_context_out_bits { 5711 u8 status[0x8]; 5712 u8 reserved_at_8[0x18]; 5713 5714 u8 syndrome[0x20]; 5715 5716 u8 reserved_at_40[0x40]; 5717 5718 struct mlx5_ifc_nic_vport_context_bits nic_vport_context; 5719 }; 5720 5721 struct mlx5_ifc_query_nic_vport_context_in_bits { 5722 u8 opcode[0x10]; 5723 u8 reserved_at_10[0x10]; 5724 5725 u8 reserved_at_20[0x10]; 5726 u8 op_mod[0x10]; 5727 5728 u8 other_vport[0x1]; 5729 u8 reserved_at_41[0xf]; 5730 u8 vport_number[0x10]; 5731 5732 u8 reserved_at_60[0x5]; 5733 u8 allowed_list_type[0x3]; 5734 u8 reserved_at_68[0x18]; 5735 }; 5736 5737 struct mlx5_ifc_query_mkey_out_bits { 5738 u8 status[0x8]; 5739 u8 reserved_at_8[0x18]; 5740 5741 u8 syndrome[0x20]; 5742 5743 u8 reserved_at_40[0x40]; 5744 5745 struct mlx5_ifc_mkc_bits memory_key_mkey_entry; 5746 5747 u8 reserved_at_280[0x600]; 5748 5749 u8 bsf0_klm0_pas_mtt0_1[16][0x8]; 5750 5751 u8 bsf1_klm1_pas_mtt2_3[16][0x8]; 5752 }; 5753 5754 struct mlx5_ifc_query_mkey_in_bits { 5755 u8 opcode[0x10]; 5756 u8 reserved_at_10[0x10]; 5757 5758 u8 reserved_at_20[0x10]; 5759 u8 op_mod[0x10]; 5760 5761 u8 reserved_at_40[0x8]; 5762 u8 mkey_index[0x18]; 5763 5764 u8 pg_access[0x1]; 5765 u8 reserved_at_61[0x1f]; 5766 }; 5767 5768 struct mlx5_ifc_query_mad_demux_out_bits { 5769 u8 status[0x8]; 5770 u8 reserved_at_8[0x18]; 5771 5772 u8 syndrome[0x20]; 5773 5774 u8 reserved_at_40[0x40]; 5775 5776 u8 mad_dumux_parameters_block[0x20]; 5777 }; 5778 5779 struct mlx5_ifc_query_mad_demux_in_bits { 5780 u8 opcode[0x10]; 5781 u8 reserved_at_10[0x10]; 5782 5783 u8 reserved_at_20[0x10]; 5784 u8 op_mod[0x10]; 5785 5786 u8 reserved_at_40[0x40]; 5787 }; 5788 5789 struct mlx5_ifc_query_l2_table_entry_out_bits { 5790 u8 status[0x8]; 5791 u8 reserved_at_8[0x18]; 5792 5793 u8 syndrome[0x20]; 5794 5795 u8 reserved_at_40[0xa0]; 5796 5797 u8 reserved_at_e0[0x13]; 5798 u8 vlan_valid[0x1]; 5799 u8 vlan[0xc]; 5800 5801 struct mlx5_ifc_mac_address_layout_bits mac_address; 5802 5803 u8 reserved_at_140[0xc0]; 5804 }; 5805 5806 struct mlx5_ifc_query_l2_table_entry_in_bits { 5807 u8 opcode[0x10]; 5808 u8 reserved_at_10[0x10]; 5809 5810 u8 reserved_at_20[0x10]; 5811 u8 op_mod[0x10]; 5812 5813 u8 reserved_at_40[0x60]; 5814 5815 u8 reserved_at_a0[0x8]; 5816 u8 table_index[0x18]; 5817 5818 u8 reserved_at_c0[0x140]; 5819 }; 5820 5821 struct mlx5_ifc_query_issi_out_bits { 5822 u8 status[0x8]; 5823 u8 reserved_at_8[0x18]; 5824 5825 u8 syndrome[0x20]; 5826 5827 u8 reserved_at_40[0x10]; 5828 u8 current_issi[0x10]; 5829 5830 u8 reserved_at_60[0xa0]; 5831 5832 u8 reserved_at_100[76][0x8]; 5833 u8 supported_issi_dw0[0x20]; 5834 }; 5835 5836 struct mlx5_ifc_query_issi_in_bits { 5837 u8 opcode[0x10]; 5838 u8 reserved_at_10[0x10]; 5839 5840 u8 reserved_at_20[0x10]; 5841 u8 op_mod[0x10]; 5842 5843 u8 reserved_at_40[0x40]; 5844 }; 5845 5846 struct mlx5_ifc_set_driver_version_out_bits { 5847 u8 status[0x8]; 5848 u8 reserved_0[0x18]; 5849 5850 u8 syndrome[0x20]; 5851 u8 reserved_1[0x40]; 5852 }; 5853 5854 struct mlx5_ifc_set_driver_version_in_bits { 5855 u8 opcode[0x10]; 5856 u8 reserved_0[0x10]; 5857 5858 u8 reserved_1[0x10]; 5859 u8 op_mod[0x10]; 5860 5861 u8 reserved_2[0x40]; 5862 u8 driver_version[64][0x8]; 5863 }; 5864 5865 struct mlx5_ifc_query_hca_vport_pkey_out_bits { 5866 u8 status[0x8]; 5867 u8 reserved_at_8[0x18]; 5868 5869 u8 syndrome[0x20]; 5870 5871 u8 reserved_at_40[0x40]; 5872 5873 struct mlx5_ifc_pkey_bits pkey[]; 5874 }; 5875 5876 struct mlx5_ifc_query_hca_vport_pkey_in_bits { 5877 u8 opcode[0x10]; 5878 u8 reserved_at_10[0x10]; 5879 5880 u8 reserved_at_20[0x10]; 5881 u8 op_mod[0x10]; 5882 5883 u8 other_vport[0x1]; 5884 u8 reserved_at_41[0xb]; 5885 u8 port_num[0x4]; 5886 u8 vport_number[0x10]; 5887 5888 u8 reserved_at_60[0x10]; 5889 u8 pkey_index[0x10]; 5890 }; 5891 5892 enum { 5893 MLX5_HCA_VPORT_SEL_PORT_GUID = 1 << 0, 5894 MLX5_HCA_VPORT_SEL_NODE_GUID = 1 << 1, 5895 MLX5_HCA_VPORT_SEL_STATE_POLICY = 1 << 2, 5896 }; 5897 5898 struct mlx5_ifc_query_hca_vport_gid_out_bits { 5899 u8 status[0x8]; 5900 u8 reserved_at_8[0x18]; 5901 5902 u8 syndrome[0x20]; 5903 5904 u8 reserved_at_40[0x20]; 5905 5906 u8 gids_num[0x10]; 5907 u8 reserved_at_70[0x10]; 5908 5909 struct mlx5_ifc_array128_auto_bits gid[]; 5910 }; 5911 5912 struct mlx5_ifc_query_hca_vport_gid_in_bits { 5913 u8 opcode[0x10]; 5914 u8 reserved_at_10[0x10]; 5915 5916 u8 reserved_at_20[0x10]; 5917 u8 op_mod[0x10]; 5918 5919 u8 other_vport[0x1]; 5920 u8 reserved_at_41[0xb]; 5921 u8 port_num[0x4]; 5922 u8 vport_number[0x10]; 5923 5924 u8 reserved_at_60[0x10]; 5925 u8 gid_index[0x10]; 5926 }; 5927 5928 struct mlx5_ifc_query_hca_vport_context_out_bits { 5929 u8 status[0x8]; 5930 u8 reserved_at_8[0x18]; 5931 5932 u8 syndrome[0x20]; 5933 5934 u8 reserved_at_40[0x40]; 5935 5936 struct mlx5_ifc_hca_vport_context_bits hca_vport_context; 5937 }; 5938 5939 struct mlx5_ifc_query_hca_vport_context_in_bits { 5940 u8 opcode[0x10]; 5941 u8 reserved_at_10[0x10]; 5942 5943 u8 reserved_at_20[0x10]; 5944 u8 op_mod[0x10]; 5945 5946 u8 other_vport[0x1]; 5947 u8 reserved_at_41[0xb]; 5948 u8 port_num[0x4]; 5949 u8 vport_number[0x10]; 5950 5951 u8 reserved_at_60[0x20]; 5952 }; 5953 5954 struct mlx5_ifc_query_hca_cap_out_bits { 5955 u8 status[0x8]; 5956 u8 reserved_at_8[0x18]; 5957 5958 u8 syndrome[0x20]; 5959 5960 u8 reserved_at_40[0x40]; 5961 5962 union mlx5_ifc_hca_cap_union_bits capability; 5963 }; 5964 5965 struct mlx5_ifc_query_hca_cap_in_bits { 5966 u8 opcode[0x10]; 5967 u8 reserved_at_10[0x10]; 5968 5969 u8 reserved_at_20[0x10]; 5970 u8 op_mod[0x10]; 5971 5972 u8 other_function[0x1]; 5973 u8 ec_vf_function[0x1]; 5974 u8 reserved_at_42[0xe]; 5975 u8 function_id[0x10]; 5976 5977 u8 reserved_at_60[0x20]; 5978 }; 5979 5980 struct mlx5_ifc_other_hca_cap_bits { 5981 u8 roce[0x1]; 5982 u8 reserved_at_1[0x27f]; 5983 }; 5984 5985 struct mlx5_ifc_query_other_hca_cap_out_bits { 5986 u8 status[0x8]; 5987 u8 reserved_at_8[0x18]; 5988 5989 u8 syndrome[0x20]; 5990 5991 u8 reserved_at_40[0x40]; 5992 5993 struct mlx5_ifc_other_hca_cap_bits other_capability; 5994 }; 5995 5996 struct mlx5_ifc_query_other_hca_cap_in_bits { 5997 u8 opcode[0x10]; 5998 u8 reserved_at_10[0x10]; 5999 6000 u8 reserved_at_20[0x10]; 6001 u8 op_mod[0x10]; 6002 6003 u8 reserved_at_40[0x10]; 6004 u8 function_id[0x10]; 6005 6006 u8 reserved_at_60[0x20]; 6007 }; 6008 6009 struct mlx5_ifc_modify_other_hca_cap_out_bits { 6010 u8 status[0x8]; 6011 u8 reserved_at_8[0x18]; 6012 6013 u8 syndrome[0x20]; 6014 6015 u8 reserved_at_40[0x40]; 6016 }; 6017 6018 struct mlx5_ifc_modify_other_hca_cap_in_bits { 6019 u8 opcode[0x10]; 6020 u8 reserved_at_10[0x10]; 6021 6022 u8 reserved_at_20[0x10]; 6023 u8 op_mod[0x10]; 6024 6025 u8 reserved_at_40[0x10]; 6026 u8 function_id[0x10]; 6027 u8 field_select[0x20]; 6028 6029 struct mlx5_ifc_other_hca_cap_bits other_capability; 6030 }; 6031 6032 struct mlx5_ifc_flow_table_context_bits { 6033 u8 reformat_en[0x1]; 6034 u8 decap_en[0x1]; 6035 u8 sw_owner[0x1]; 6036 u8 termination_table[0x1]; 6037 u8 table_miss_action[0x4]; 6038 u8 level[0x8]; 6039 u8 reserved_at_10[0x8]; 6040 u8 log_size[0x8]; 6041 6042 u8 reserved_at_20[0x8]; 6043 u8 table_miss_id[0x18]; 6044 6045 u8 reserved_at_40[0x8]; 6046 u8 lag_master_next_table_id[0x18]; 6047 6048 u8 reserved_at_60[0x60]; 6049 6050 u8 sw_owner_icm_root_1[0x40]; 6051 6052 u8 sw_owner_icm_root_0[0x40]; 6053 6054 }; 6055 6056 struct mlx5_ifc_query_flow_table_out_bits { 6057 u8 status[0x8]; 6058 u8 reserved_at_8[0x18]; 6059 6060 u8 syndrome[0x20]; 6061 6062 u8 reserved_at_40[0x80]; 6063 6064 struct mlx5_ifc_flow_table_context_bits flow_table_context; 6065 }; 6066 6067 struct mlx5_ifc_query_flow_table_in_bits { 6068 u8 opcode[0x10]; 6069 u8 reserved_at_10[0x10]; 6070 6071 u8 reserved_at_20[0x10]; 6072 u8 op_mod[0x10]; 6073 6074 u8 reserved_at_40[0x40]; 6075 6076 u8 table_type[0x8]; 6077 u8 reserved_at_88[0x18]; 6078 6079 u8 reserved_at_a0[0x8]; 6080 u8 table_id[0x18]; 6081 6082 u8 reserved_at_c0[0x140]; 6083 }; 6084 6085 struct mlx5_ifc_query_fte_out_bits { 6086 u8 status[0x8]; 6087 u8 reserved_at_8[0x18]; 6088 6089 u8 syndrome[0x20]; 6090 6091 u8 reserved_at_40[0x1c0]; 6092 6093 struct mlx5_ifc_flow_context_bits flow_context; 6094 }; 6095 6096 struct mlx5_ifc_query_fte_in_bits { 6097 u8 opcode[0x10]; 6098 u8 reserved_at_10[0x10]; 6099 6100 u8 reserved_at_20[0x10]; 6101 u8 op_mod[0x10]; 6102 6103 u8 reserved_at_40[0x40]; 6104 6105 u8 table_type[0x8]; 6106 u8 reserved_at_88[0x18]; 6107 6108 u8 reserved_at_a0[0x8]; 6109 u8 table_id[0x18]; 6110 6111 u8 reserved_at_c0[0x40]; 6112 6113 u8 flow_index[0x20]; 6114 6115 u8 reserved_at_120[0xe0]; 6116 }; 6117 6118 struct mlx5_ifc_match_definer_format_0_bits { 6119 u8 reserved_at_0[0x100]; 6120 6121 u8 metadata_reg_c_0[0x20]; 6122 6123 u8 metadata_reg_c_1[0x20]; 6124 6125 u8 outer_dmac_47_16[0x20]; 6126 6127 u8 outer_dmac_15_0[0x10]; 6128 u8 outer_ethertype[0x10]; 6129 6130 u8 reserved_at_180[0x1]; 6131 u8 sx_sniffer[0x1]; 6132 u8 functional_lb[0x1]; 6133 u8 outer_ip_frag[0x1]; 6134 u8 outer_qp_type[0x2]; 6135 u8 outer_encap_type[0x2]; 6136 u8 port_number[0x2]; 6137 u8 outer_l3_type[0x2]; 6138 u8 outer_l4_type[0x2]; 6139 u8 outer_first_vlan_type[0x2]; 6140 u8 outer_first_vlan_prio[0x3]; 6141 u8 outer_first_vlan_cfi[0x1]; 6142 u8 outer_first_vlan_vid[0xc]; 6143 6144 u8 outer_l4_type_ext[0x4]; 6145 u8 reserved_at_1a4[0x2]; 6146 u8 outer_ipsec_layer[0x2]; 6147 u8 outer_l2_type[0x2]; 6148 u8 force_lb[0x1]; 6149 u8 outer_l2_ok[0x1]; 6150 u8 outer_l3_ok[0x1]; 6151 u8 outer_l4_ok[0x1]; 6152 u8 outer_second_vlan_type[0x2]; 6153 u8 outer_second_vlan_prio[0x3]; 6154 u8 outer_second_vlan_cfi[0x1]; 6155 u8 outer_second_vlan_vid[0xc]; 6156 6157 u8 outer_smac_47_16[0x20]; 6158 6159 u8 outer_smac_15_0[0x10]; 6160 u8 inner_ipv4_checksum_ok[0x1]; 6161 u8 inner_l4_checksum_ok[0x1]; 6162 u8 outer_ipv4_checksum_ok[0x1]; 6163 u8 outer_l4_checksum_ok[0x1]; 6164 u8 inner_l3_ok[0x1]; 6165 u8 inner_l4_ok[0x1]; 6166 u8 outer_l3_ok_duplicate[0x1]; 6167 u8 outer_l4_ok_duplicate[0x1]; 6168 u8 outer_tcp_cwr[0x1]; 6169 u8 outer_tcp_ece[0x1]; 6170 u8 outer_tcp_urg[0x1]; 6171 u8 outer_tcp_ack[0x1]; 6172 u8 outer_tcp_psh[0x1]; 6173 u8 outer_tcp_rst[0x1]; 6174 u8 outer_tcp_syn[0x1]; 6175 u8 outer_tcp_fin[0x1]; 6176 }; 6177 6178 struct mlx5_ifc_match_definer_format_22_bits { 6179 u8 reserved_at_0[0x100]; 6180 6181 u8 outer_ip_src_addr[0x20]; 6182 6183 u8 outer_ip_dest_addr[0x20]; 6184 6185 u8 outer_l4_sport[0x10]; 6186 u8 outer_l4_dport[0x10]; 6187 6188 u8 reserved_at_160[0x1]; 6189 u8 sx_sniffer[0x1]; 6190 u8 functional_lb[0x1]; 6191 u8 outer_ip_frag[0x1]; 6192 u8 outer_qp_type[0x2]; 6193 u8 outer_encap_type[0x2]; 6194 u8 port_number[0x2]; 6195 u8 outer_l3_type[0x2]; 6196 u8 outer_l4_type[0x2]; 6197 u8 outer_first_vlan_type[0x2]; 6198 u8 outer_first_vlan_prio[0x3]; 6199 u8 outer_first_vlan_cfi[0x1]; 6200 u8 outer_first_vlan_vid[0xc]; 6201 6202 u8 metadata_reg_c_0[0x20]; 6203 6204 u8 outer_dmac_47_16[0x20]; 6205 6206 u8 outer_smac_47_16[0x20]; 6207 6208 u8 outer_smac_15_0[0x10]; 6209 u8 outer_dmac_15_0[0x10]; 6210 }; 6211 6212 struct mlx5_ifc_match_definer_format_23_bits { 6213 u8 reserved_at_0[0x100]; 6214 6215 u8 inner_ip_src_addr[0x20]; 6216 6217 u8 inner_ip_dest_addr[0x20]; 6218 6219 u8 inner_l4_sport[0x10]; 6220 u8 inner_l4_dport[0x10]; 6221 6222 u8 reserved_at_160[0x1]; 6223 u8 sx_sniffer[0x1]; 6224 u8 functional_lb[0x1]; 6225 u8 inner_ip_frag[0x1]; 6226 u8 inner_qp_type[0x2]; 6227 u8 inner_encap_type[0x2]; 6228 u8 port_number[0x2]; 6229 u8 inner_l3_type[0x2]; 6230 u8 inner_l4_type[0x2]; 6231 u8 inner_first_vlan_type[0x2]; 6232 u8 inner_first_vlan_prio[0x3]; 6233 u8 inner_first_vlan_cfi[0x1]; 6234 u8 inner_first_vlan_vid[0xc]; 6235 6236 u8 tunnel_header_0[0x20]; 6237 6238 u8 inner_dmac_47_16[0x20]; 6239 6240 u8 inner_smac_47_16[0x20]; 6241 6242 u8 inner_smac_15_0[0x10]; 6243 u8 inner_dmac_15_0[0x10]; 6244 }; 6245 6246 struct mlx5_ifc_match_definer_format_29_bits { 6247 u8 reserved_at_0[0xc0]; 6248 6249 u8 outer_ip_dest_addr[0x80]; 6250 6251 u8 outer_ip_src_addr[0x80]; 6252 6253 u8 outer_l4_sport[0x10]; 6254 u8 outer_l4_dport[0x10]; 6255 6256 u8 reserved_at_1e0[0x20]; 6257 }; 6258 6259 struct mlx5_ifc_match_definer_format_30_bits { 6260 u8 reserved_at_0[0xa0]; 6261 6262 u8 outer_ip_dest_addr[0x80]; 6263 6264 u8 outer_ip_src_addr[0x80]; 6265 6266 u8 outer_dmac_47_16[0x20]; 6267 6268 u8 outer_smac_47_16[0x20]; 6269 6270 u8 outer_smac_15_0[0x10]; 6271 u8 outer_dmac_15_0[0x10]; 6272 }; 6273 6274 struct mlx5_ifc_match_definer_format_31_bits { 6275 u8 reserved_at_0[0xc0]; 6276 6277 u8 inner_ip_dest_addr[0x80]; 6278 6279 u8 inner_ip_src_addr[0x80]; 6280 6281 u8 inner_l4_sport[0x10]; 6282 u8 inner_l4_dport[0x10]; 6283 6284 u8 reserved_at_1e0[0x20]; 6285 }; 6286 6287 struct mlx5_ifc_match_definer_format_32_bits { 6288 u8 reserved_at_0[0xa0]; 6289 6290 u8 inner_ip_dest_addr[0x80]; 6291 6292 u8 inner_ip_src_addr[0x80]; 6293 6294 u8 inner_dmac_47_16[0x20]; 6295 6296 u8 inner_smac_47_16[0x20]; 6297 6298 u8 inner_smac_15_0[0x10]; 6299 u8 inner_dmac_15_0[0x10]; 6300 }; 6301 6302 enum { 6303 MLX5_IFC_DEFINER_FORMAT_ID_SELECT = 61, 6304 }; 6305 6306 #define MLX5_IFC_DEFINER_FORMAT_OFFSET_UNUSED 0x0 6307 #define MLX5_IFC_DEFINER_FORMAT_OFFSET_OUTER_ETH_PKT_LEN 0x48 6308 #define MLX5_IFC_DEFINER_DW_SELECTORS_NUM 9 6309 #define MLX5_IFC_DEFINER_BYTE_SELECTORS_NUM 8 6310 6311 struct mlx5_ifc_match_definer_match_mask_bits { 6312 u8 reserved_at_1c0[5][0x20]; 6313 u8 match_dw_8[0x20]; 6314 u8 match_dw_7[0x20]; 6315 u8 match_dw_6[0x20]; 6316 u8 match_dw_5[0x20]; 6317 u8 match_dw_4[0x20]; 6318 u8 match_dw_3[0x20]; 6319 u8 match_dw_2[0x20]; 6320 u8 match_dw_1[0x20]; 6321 u8 match_dw_0[0x20]; 6322 6323 u8 match_byte_7[0x8]; 6324 u8 match_byte_6[0x8]; 6325 u8 match_byte_5[0x8]; 6326 u8 match_byte_4[0x8]; 6327 6328 u8 match_byte_3[0x8]; 6329 u8 match_byte_2[0x8]; 6330 u8 match_byte_1[0x8]; 6331 u8 match_byte_0[0x8]; 6332 }; 6333 6334 struct mlx5_ifc_match_definer_bits { 6335 u8 modify_field_select[0x40]; 6336 6337 u8 reserved_at_40[0x40]; 6338 6339 u8 reserved_at_80[0x10]; 6340 u8 format_id[0x10]; 6341 6342 u8 reserved_at_a0[0x60]; 6343 6344 u8 format_select_dw3[0x8]; 6345 u8 format_select_dw2[0x8]; 6346 u8 format_select_dw1[0x8]; 6347 u8 format_select_dw0[0x8]; 6348 6349 u8 format_select_dw7[0x8]; 6350 u8 format_select_dw6[0x8]; 6351 u8 format_select_dw5[0x8]; 6352 u8 format_select_dw4[0x8]; 6353 6354 u8 reserved_at_100[0x18]; 6355 u8 format_select_dw8[0x8]; 6356 6357 u8 reserved_at_120[0x20]; 6358 6359 u8 format_select_byte3[0x8]; 6360 u8 format_select_byte2[0x8]; 6361 u8 format_select_byte1[0x8]; 6362 u8 format_select_byte0[0x8]; 6363 6364 u8 format_select_byte7[0x8]; 6365 u8 format_select_byte6[0x8]; 6366 u8 format_select_byte5[0x8]; 6367 u8 format_select_byte4[0x8]; 6368 6369 u8 reserved_at_180[0x40]; 6370 6371 union { 6372 struct { 6373 u8 match_mask[16][0x20]; 6374 }; 6375 struct mlx5_ifc_match_definer_match_mask_bits match_mask_format; 6376 }; 6377 }; 6378 6379 struct mlx5_ifc_general_obj_create_param_bits { 6380 u8 alias_object[0x1]; 6381 u8 reserved_at_1[0x2]; 6382 u8 log_obj_range[0x5]; 6383 u8 reserved_at_8[0x18]; 6384 }; 6385 6386 struct mlx5_ifc_general_obj_query_param_bits { 6387 u8 alias_object[0x1]; 6388 u8 obj_offset[0x1f]; 6389 }; 6390 6391 struct mlx5_ifc_general_obj_in_cmd_hdr_bits { 6392 u8 opcode[0x10]; 6393 u8 uid[0x10]; 6394 6395 u8 vhca_tunnel_id[0x10]; 6396 u8 obj_type[0x10]; 6397 6398 u8 obj_id[0x20]; 6399 6400 union { 6401 struct mlx5_ifc_general_obj_create_param_bits create; 6402 struct mlx5_ifc_general_obj_query_param_bits query; 6403 } op_param; 6404 }; 6405 6406 struct mlx5_ifc_general_obj_out_cmd_hdr_bits { 6407 u8 status[0x8]; 6408 u8 reserved_at_8[0x18]; 6409 6410 u8 syndrome[0x20]; 6411 6412 u8 obj_id[0x20]; 6413 6414 u8 reserved_at_60[0x20]; 6415 }; 6416 6417 struct mlx5_ifc_allow_other_vhca_access_in_bits { 6418 u8 opcode[0x10]; 6419 u8 uid[0x10]; 6420 u8 reserved_at_20[0x10]; 6421 u8 op_mod[0x10]; 6422 u8 reserved_at_40[0x50]; 6423 u8 object_type_to_be_accessed[0x10]; 6424 u8 object_id_to_be_accessed[0x20]; 6425 u8 reserved_at_c0[0x40]; 6426 union { 6427 u8 access_key_raw[0x100]; 6428 u8 access_key[8][0x20]; 6429 }; 6430 }; 6431 6432 struct mlx5_ifc_allow_other_vhca_access_out_bits { 6433 u8 status[0x8]; 6434 u8 reserved_at_8[0x18]; 6435 u8 syndrome[0x20]; 6436 u8 reserved_at_40[0x40]; 6437 }; 6438 6439 struct mlx5_ifc_modify_header_arg_bits { 6440 u8 reserved_at_0[0x80]; 6441 6442 u8 reserved_at_80[0x8]; 6443 u8 access_pd[0x18]; 6444 }; 6445 6446 struct mlx5_ifc_create_modify_header_arg_in_bits { 6447 struct mlx5_ifc_general_obj_in_cmd_hdr_bits hdr; 6448 struct mlx5_ifc_modify_header_arg_bits arg; 6449 }; 6450 6451 struct mlx5_ifc_create_match_definer_in_bits { 6452 struct mlx5_ifc_general_obj_in_cmd_hdr_bits general_obj_in_cmd_hdr; 6453 6454 struct mlx5_ifc_match_definer_bits obj_context; 6455 }; 6456 6457 struct mlx5_ifc_create_match_definer_out_bits { 6458 struct mlx5_ifc_general_obj_out_cmd_hdr_bits general_obj_out_cmd_hdr; 6459 }; 6460 6461 struct mlx5_ifc_alias_context_bits { 6462 u8 vhca_id_to_be_accessed[0x10]; 6463 u8 reserved_at_10[0xd]; 6464 u8 status[0x3]; 6465 u8 object_id_to_be_accessed[0x20]; 6466 u8 reserved_at_40[0x40]; 6467 union { 6468 u8 access_key_raw[0x100]; 6469 u8 access_key[8][0x20]; 6470 }; 6471 u8 metadata[0x80]; 6472 }; 6473 6474 struct mlx5_ifc_create_alias_obj_in_bits { 6475 struct mlx5_ifc_general_obj_in_cmd_hdr_bits hdr; 6476 struct mlx5_ifc_alias_context_bits alias_ctx; 6477 }; 6478 6479 enum { 6480 MLX5_QUERY_FLOW_GROUP_OUT_MATCH_CRITERIA_ENABLE_OUTER_HEADERS = 0x0, 6481 MLX5_QUERY_FLOW_GROUP_OUT_MATCH_CRITERIA_ENABLE_MISC_PARAMETERS = 0x1, 6482 MLX5_QUERY_FLOW_GROUP_OUT_MATCH_CRITERIA_ENABLE_INNER_HEADERS = 0x2, 6483 MLX5_QUERY_FLOW_GROUP_IN_MATCH_CRITERIA_ENABLE_MISC_PARAMETERS_2 = 0x3, 6484 MLX5_QUERY_FLOW_GROUP_IN_MATCH_CRITERIA_ENABLE_MISC_PARAMETERS_3 = 0x4, 6485 MLX5_QUERY_FLOW_GROUP_IN_MATCH_CRITERIA_ENABLE_MISC_PARAMETERS_4 = 0x5, 6486 MLX5_QUERY_FLOW_GROUP_IN_MATCH_CRITERIA_ENABLE_MISC_PARAMETERS_5 = 0x6, 6487 }; 6488 6489 struct mlx5_ifc_query_flow_group_out_bits { 6490 u8 status[0x8]; 6491 u8 reserved_at_8[0x18]; 6492 6493 u8 syndrome[0x20]; 6494 6495 u8 reserved_at_40[0xa0]; 6496 6497 u8 start_flow_index[0x20]; 6498 6499 u8 reserved_at_100[0x20]; 6500 6501 u8 end_flow_index[0x20]; 6502 6503 u8 reserved_at_140[0xa0]; 6504 6505 u8 reserved_at_1e0[0x18]; 6506 u8 match_criteria_enable[0x8]; 6507 6508 struct mlx5_ifc_fte_match_param_bits match_criteria; 6509 6510 u8 reserved_at_1200[0xe00]; 6511 }; 6512 6513 struct mlx5_ifc_query_flow_group_in_bits { 6514 u8 opcode[0x10]; 6515 u8 reserved_at_10[0x10]; 6516 6517 u8 reserved_at_20[0x10]; 6518 u8 op_mod[0x10]; 6519 6520 u8 reserved_at_40[0x40]; 6521 6522 u8 table_type[0x8]; 6523 u8 reserved_at_88[0x18]; 6524 6525 u8 reserved_at_a0[0x8]; 6526 u8 table_id[0x18]; 6527 6528 u8 group_id[0x20]; 6529 6530 u8 reserved_at_e0[0x120]; 6531 }; 6532 6533 struct mlx5_ifc_query_flow_counter_out_bits { 6534 u8 status[0x8]; 6535 u8 reserved_at_8[0x18]; 6536 6537 u8 syndrome[0x20]; 6538 6539 u8 reserved_at_40[0x40]; 6540 6541 struct mlx5_ifc_traffic_counter_bits flow_statistics[]; 6542 }; 6543 6544 struct mlx5_ifc_query_flow_counter_in_bits { 6545 u8 opcode[0x10]; 6546 u8 reserved_at_10[0x10]; 6547 6548 u8 reserved_at_20[0x10]; 6549 u8 op_mod[0x10]; 6550 6551 u8 reserved_at_40[0x80]; 6552 6553 u8 clear[0x1]; 6554 u8 reserved_at_c1[0xf]; 6555 u8 num_of_counters[0x10]; 6556 6557 u8 flow_counter_id[0x20]; 6558 }; 6559 6560 struct mlx5_ifc_query_esw_vport_context_out_bits { 6561 u8 status[0x8]; 6562 u8 reserved_at_8[0x18]; 6563 6564 u8 syndrome[0x20]; 6565 6566 u8 reserved_at_40[0x40]; 6567 6568 struct mlx5_ifc_esw_vport_context_bits esw_vport_context; 6569 }; 6570 6571 struct mlx5_ifc_query_esw_vport_context_in_bits { 6572 u8 opcode[0x10]; 6573 u8 reserved_at_10[0x10]; 6574 6575 u8 reserved_at_20[0x10]; 6576 u8 op_mod[0x10]; 6577 6578 u8 other_vport[0x1]; 6579 u8 reserved_at_41[0xf]; 6580 u8 vport_number[0x10]; 6581 6582 u8 reserved_at_60[0x20]; 6583 }; 6584 6585 struct mlx5_ifc_modify_esw_vport_context_out_bits { 6586 u8 status[0x8]; 6587 u8 reserved_at_8[0x18]; 6588 6589 u8 syndrome[0x20]; 6590 6591 u8 reserved_at_40[0x40]; 6592 }; 6593 6594 struct mlx5_ifc_esw_vport_context_fields_select_bits { 6595 u8 reserved_at_0[0x1b]; 6596 u8 fdb_to_vport_reg_c_id[0x1]; 6597 u8 vport_cvlan_insert[0x1]; 6598 u8 vport_svlan_insert[0x1]; 6599 u8 vport_cvlan_strip[0x1]; 6600 u8 vport_svlan_strip[0x1]; 6601 }; 6602 6603 struct mlx5_ifc_modify_esw_vport_context_in_bits { 6604 u8 opcode[0x10]; 6605 u8 reserved_at_10[0x10]; 6606 6607 u8 reserved_at_20[0x10]; 6608 u8 op_mod[0x10]; 6609 6610 u8 other_vport[0x1]; 6611 u8 reserved_at_41[0xf]; 6612 u8 vport_number[0x10]; 6613 6614 struct mlx5_ifc_esw_vport_context_fields_select_bits field_select; 6615 6616 struct mlx5_ifc_esw_vport_context_bits esw_vport_context; 6617 }; 6618 6619 struct mlx5_ifc_query_eq_out_bits { 6620 u8 status[0x8]; 6621 u8 reserved_at_8[0x18]; 6622 6623 u8 syndrome[0x20]; 6624 6625 u8 reserved_at_40[0x40]; 6626 6627 struct mlx5_ifc_eqc_bits eq_context_entry; 6628 6629 u8 reserved_at_280[0x40]; 6630 6631 u8 event_bitmask[0x40]; 6632 6633 u8 reserved_at_300[0x580]; 6634 6635 u8 pas[][0x40]; 6636 }; 6637 6638 struct mlx5_ifc_query_eq_in_bits { 6639 u8 opcode[0x10]; 6640 u8 reserved_at_10[0x10]; 6641 6642 u8 reserved_at_20[0x10]; 6643 u8 op_mod[0x10]; 6644 6645 u8 reserved_at_40[0x18]; 6646 u8 eq_number[0x8]; 6647 6648 u8 reserved_at_60[0x20]; 6649 }; 6650 6651 struct mlx5_ifc_packet_reformat_context_in_bits { 6652 u8 reformat_type[0x8]; 6653 u8 reserved_at_8[0x4]; 6654 u8 reformat_param_0[0x4]; 6655 u8 reserved_at_10[0x6]; 6656 u8 reformat_data_size[0xa]; 6657 6658 u8 reformat_param_1[0x8]; 6659 u8 reserved_at_28[0x8]; 6660 u8 reformat_data[2][0x8]; 6661 6662 u8 more_reformat_data[][0x8]; 6663 }; 6664 6665 struct mlx5_ifc_query_packet_reformat_context_out_bits { 6666 u8 status[0x8]; 6667 u8 reserved_at_8[0x18]; 6668 6669 u8 syndrome[0x20]; 6670 6671 u8 reserved_at_40[0xa0]; 6672 6673 struct mlx5_ifc_packet_reformat_context_in_bits packet_reformat_context[]; 6674 }; 6675 6676 struct mlx5_ifc_query_packet_reformat_context_in_bits { 6677 u8 opcode[0x10]; 6678 u8 reserved_at_10[0x10]; 6679 6680 u8 reserved_at_20[0x10]; 6681 u8 op_mod[0x10]; 6682 6683 u8 packet_reformat_id[0x20]; 6684 6685 u8 reserved_at_60[0xa0]; 6686 }; 6687 6688 struct mlx5_ifc_alloc_packet_reformat_context_out_bits { 6689 u8 status[0x8]; 6690 u8 reserved_at_8[0x18]; 6691 6692 u8 syndrome[0x20]; 6693 6694 u8 packet_reformat_id[0x20]; 6695 6696 u8 reserved_at_60[0x20]; 6697 }; 6698 6699 enum { 6700 MLX5_REFORMAT_CONTEXT_ANCHOR_MAC_START = 0x1, 6701 MLX5_REFORMAT_CONTEXT_ANCHOR_IP_START = 0x7, 6702 MLX5_REFORMAT_CONTEXT_ANCHOR_TCP_UDP_START = 0x9, 6703 }; 6704 6705 enum mlx5_reformat_ctx_type { 6706 MLX5_REFORMAT_TYPE_L2_TO_VXLAN = 0x0, 6707 MLX5_REFORMAT_TYPE_L2_TO_NVGRE = 0x1, 6708 MLX5_REFORMAT_TYPE_L2_TO_L2_TUNNEL = 0x2, 6709 MLX5_REFORMAT_TYPE_L3_TUNNEL_TO_L2 = 0x3, 6710 MLX5_REFORMAT_TYPE_L2_TO_L3_TUNNEL = 0x4, 6711 MLX5_REFORMAT_TYPE_ADD_ESP_TRANSPORT_OVER_IPV4 = 0x5, 6712 MLX5_REFORMAT_TYPE_L2_TO_L3_ESP_TUNNEL = 0x6, 6713 MLX5_REFORMAT_TYPE_ADD_ESP_TRANSPORT_OVER_UDPV4 = 0x7, 6714 MLX5_REFORMAT_TYPE_DEL_ESP_TRANSPORT = 0x8, 6715 MLX5_REFORMAT_TYPE_L3_ESP_TUNNEL_TO_L2 = 0x9, 6716 MLX5_REFORMAT_TYPE_DEL_ESP_TRANSPORT_OVER_UDP = 0xa, 6717 MLX5_REFORMAT_TYPE_ADD_ESP_TRANSPORT_OVER_IPV6 = 0xb, 6718 MLX5_REFORMAT_TYPE_ADD_ESP_TRANSPORT_OVER_UDPV6 = 0xc, 6719 MLX5_REFORMAT_TYPE_INSERT_HDR = 0xf, 6720 MLX5_REFORMAT_TYPE_REMOVE_HDR = 0x10, 6721 MLX5_REFORMAT_TYPE_ADD_MACSEC = 0x11, 6722 MLX5_REFORMAT_TYPE_DEL_MACSEC = 0x12, 6723 }; 6724 6725 struct mlx5_ifc_alloc_packet_reformat_context_in_bits { 6726 u8 opcode[0x10]; 6727 u8 reserved_at_10[0x10]; 6728 6729 u8 reserved_at_20[0x10]; 6730 u8 op_mod[0x10]; 6731 6732 u8 reserved_at_40[0xa0]; 6733 6734 struct mlx5_ifc_packet_reformat_context_in_bits packet_reformat_context; 6735 }; 6736 6737 struct mlx5_ifc_dealloc_packet_reformat_context_out_bits { 6738 u8 status[0x8]; 6739 u8 reserved_at_8[0x18]; 6740 6741 u8 syndrome[0x20]; 6742 6743 u8 reserved_at_40[0x40]; 6744 }; 6745 6746 struct mlx5_ifc_dealloc_packet_reformat_context_in_bits { 6747 u8 opcode[0x10]; 6748 u8 reserved_at_10[0x10]; 6749 6750 u8 reserved_20[0x10]; 6751 u8 op_mod[0x10]; 6752 6753 u8 packet_reformat_id[0x20]; 6754 6755 u8 reserved_60[0x20]; 6756 }; 6757 6758 struct mlx5_ifc_set_action_in_bits { 6759 u8 action_type[0x4]; 6760 u8 field[0xc]; 6761 u8 reserved_at_10[0x3]; 6762 u8 offset[0x5]; 6763 u8 reserved_at_18[0x3]; 6764 u8 length[0x5]; 6765 6766 u8 data[0x20]; 6767 }; 6768 6769 struct mlx5_ifc_add_action_in_bits { 6770 u8 action_type[0x4]; 6771 u8 field[0xc]; 6772 u8 reserved_at_10[0x10]; 6773 6774 u8 data[0x20]; 6775 }; 6776 6777 struct mlx5_ifc_copy_action_in_bits { 6778 u8 action_type[0x4]; 6779 u8 src_field[0xc]; 6780 u8 reserved_at_10[0x3]; 6781 u8 src_offset[0x5]; 6782 u8 reserved_at_18[0x3]; 6783 u8 length[0x5]; 6784 6785 u8 reserved_at_20[0x4]; 6786 u8 dst_field[0xc]; 6787 u8 reserved_at_30[0x3]; 6788 u8 dst_offset[0x5]; 6789 u8 reserved_at_38[0x8]; 6790 }; 6791 6792 union mlx5_ifc_set_add_copy_action_in_auto_bits { 6793 struct mlx5_ifc_set_action_in_bits set_action_in; 6794 struct mlx5_ifc_add_action_in_bits add_action_in; 6795 struct mlx5_ifc_copy_action_in_bits copy_action_in; 6796 u8 reserved_at_0[0x40]; 6797 }; 6798 6799 enum { 6800 MLX5_ACTION_TYPE_SET = 0x1, 6801 MLX5_ACTION_TYPE_ADD = 0x2, 6802 MLX5_ACTION_TYPE_COPY = 0x3, 6803 }; 6804 6805 enum { 6806 MLX5_ACTION_IN_FIELD_OUT_SMAC_47_16 = 0x1, 6807 MLX5_ACTION_IN_FIELD_OUT_SMAC_15_0 = 0x2, 6808 MLX5_ACTION_IN_FIELD_OUT_ETHERTYPE = 0x3, 6809 MLX5_ACTION_IN_FIELD_OUT_DMAC_47_16 = 0x4, 6810 MLX5_ACTION_IN_FIELD_OUT_DMAC_15_0 = 0x5, 6811 MLX5_ACTION_IN_FIELD_OUT_IP_DSCP = 0x6, 6812 MLX5_ACTION_IN_FIELD_OUT_TCP_FLAGS = 0x7, 6813 MLX5_ACTION_IN_FIELD_OUT_TCP_SPORT = 0x8, 6814 MLX5_ACTION_IN_FIELD_OUT_TCP_DPORT = 0x9, 6815 MLX5_ACTION_IN_FIELD_OUT_IP_TTL = 0xa, 6816 MLX5_ACTION_IN_FIELD_OUT_UDP_SPORT = 0xb, 6817 MLX5_ACTION_IN_FIELD_OUT_UDP_DPORT = 0xc, 6818 MLX5_ACTION_IN_FIELD_OUT_SIPV6_127_96 = 0xd, 6819 MLX5_ACTION_IN_FIELD_OUT_SIPV6_95_64 = 0xe, 6820 MLX5_ACTION_IN_FIELD_OUT_SIPV6_63_32 = 0xf, 6821 MLX5_ACTION_IN_FIELD_OUT_SIPV6_31_0 = 0x10, 6822 MLX5_ACTION_IN_FIELD_OUT_DIPV6_127_96 = 0x11, 6823 MLX5_ACTION_IN_FIELD_OUT_DIPV6_95_64 = 0x12, 6824 MLX5_ACTION_IN_FIELD_OUT_DIPV6_63_32 = 0x13, 6825 MLX5_ACTION_IN_FIELD_OUT_DIPV6_31_0 = 0x14, 6826 MLX5_ACTION_IN_FIELD_OUT_SIPV4 = 0x15, 6827 MLX5_ACTION_IN_FIELD_OUT_DIPV4 = 0x16, 6828 MLX5_ACTION_IN_FIELD_OUT_FIRST_VID = 0x17, 6829 MLX5_ACTION_IN_FIELD_OUT_IPV6_HOPLIMIT = 0x47, 6830 MLX5_ACTION_IN_FIELD_METADATA_REG_A = 0x49, 6831 MLX5_ACTION_IN_FIELD_METADATA_REG_B = 0x50, 6832 MLX5_ACTION_IN_FIELD_METADATA_REG_C_0 = 0x51, 6833 MLX5_ACTION_IN_FIELD_METADATA_REG_C_1 = 0x52, 6834 MLX5_ACTION_IN_FIELD_METADATA_REG_C_2 = 0x53, 6835 MLX5_ACTION_IN_FIELD_METADATA_REG_C_3 = 0x54, 6836 MLX5_ACTION_IN_FIELD_METADATA_REG_C_4 = 0x55, 6837 MLX5_ACTION_IN_FIELD_METADATA_REG_C_5 = 0x56, 6838 MLX5_ACTION_IN_FIELD_METADATA_REG_C_6 = 0x57, 6839 MLX5_ACTION_IN_FIELD_METADATA_REG_C_7 = 0x58, 6840 MLX5_ACTION_IN_FIELD_OUT_TCP_SEQ_NUM = 0x59, 6841 MLX5_ACTION_IN_FIELD_OUT_TCP_ACK_NUM = 0x5B, 6842 MLX5_ACTION_IN_FIELD_IPSEC_SYNDROME = 0x5D, 6843 MLX5_ACTION_IN_FIELD_OUT_EMD_47_32 = 0x6F, 6844 MLX5_ACTION_IN_FIELD_OUT_EMD_31_0 = 0x70, 6845 }; 6846 6847 struct mlx5_ifc_alloc_modify_header_context_out_bits { 6848 u8 status[0x8]; 6849 u8 reserved_at_8[0x18]; 6850 6851 u8 syndrome[0x20]; 6852 6853 u8 modify_header_id[0x20]; 6854 6855 u8 reserved_at_60[0x20]; 6856 }; 6857 6858 struct mlx5_ifc_alloc_modify_header_context_in_bits { 6859 u8 opcode[0x10]; 6860 u8 reserved_at_10[0x10]; 6861 6862 u8 reserved_at_20[0x10]; 6863 u8 op_mod[0x10]; 6864 6865 u8 reserved_at_40[0x20]; 6866 6867 u8 table_type[0x8]; 6868 u8 reserved_at_68[0x10]; 6869 u8 num_of_actions[0x8]; 6870 6871 union mlx5_ifc_set_add_copy_action_in_auto_bits actions[]; 6872 }; 6873 6874 struct mlx5_ifc_dealloc_modify_header_context_out_bits { 6875 u8 status[0x8]; 6876 u8 reserved_at_8[0x18]; 6877 6878 u8 syndrome[0x20]; 6879 6880 u8 reserved_at_40[0x40]; 6881 }; 6882 6883 struct mlx5_ifc_dealloc_modify_header_context_in_bits { 6884 u8 opcode[0x10]; 6885 u8 reserved_at_10[0x10]; 6886 6887 u8 reserved_at_20[0x10]; 6888 u8 op_mod[0x10]; 6889 6890 u8 modify_header_id[0x20]; 6891 6892 u8 reserved_at_60[0x20]; 6893 }; 6894 6895 struct mlx5_ifc_query_modify_header_context_in_bits { 6896 u8 opcode[0x10]; 6897 u8 uid[0x10]; 6898 6899 u8 reserved_at_20[0x10]; 6900 u8 op_mod[0x10]; 6901 6902 u8 modify_header_id[0x20]; 6903 6904 u8 reserved_at_60[0xa0]; 6905 }; 6906 6907 struct mlx5_ifc_query_dct_out_bits { 6908 u8 status[0x8]; 6909 u8 reserved_at_8[0x18]; 6910 6911 u8 syndrome[0x20]; 6912 6913 u8 reserved_at_40[0x40]; 6914 6915 struct mlx5_ifc_dctc_bits dct_context_entry; 6916 6917 u8 reserved_at_280[0x180]; 6918 }; 6919 6920 struct mlx5_ifc_query_dct_in_bits { 6921 u8 opcode[0x10]; 6922 u8 reserved_at_10[0x10]; 6923 6924 u8 reserved_at_20[0x10]; 6925 u8 op_mod[0x10]; 6926 6927 u8 reserved_at_40[0x8]; 6928 u8 dctn[0x18]; 6929 6930 u8 reserved_at_60[0x20]; 6931 }; 6932 6933 struct mlx5_ifc_query_cq_out_bits { 6934 u8 status[0x8]; 6935 u8 reserved_at_8[0x18]; 6936 6937 u8 syndrome[0x20]; 6938 6939 u8 reserved_at_40[0x40]; 6940 6941 struct mlx5_ifc_cqc_bits cq_context; 6942 6943 u8 reserved_at_280[0x600]; 6944 6945 u8 pas[][0x40]; 6946 }; 6947 6948 struct mlx5_ifc_query_cq_in_bits { 6949 u8 opcode[0x10]; 6950 u8 reserved_at_10[0x10]; 6951 6952 u8 reserved_at_20[0x10]; 6953 u8 op_mod[0x10]; 6954 6955 u8 reserved_at_40[0x8]; 6956 u8 cqn[0x18]; 6957 6958 u8 reserved_at_60[0x20]; 6959 }; 6960 6961 struct mlx5_ifc_query_cong_status_out_bits { 6962 u8 status[0x8]; 6963 u8 reserved_at_8[0x18]; 6964 6965 u8 syndrome[0x20]; 6966 6967 u8 reserved_at_40[0x20]; 6968 6969 u8 enable[0x1]; 6970 u8 tag_enable[0x1]; 6971 u8 reserved_at_62[0x1e]; 6972 }; 6973 6974 struct mlx5_ifc_query_cong_status_in_bits { 6975 u8 opcode[0x10]; 6976 u8 reserved_at_10[0x10]; 6977 6978 u8 reserved_at_20[0x10]; 6979 u8 op_mod[0x10]; 6980 6981 u8 reserved_at_40[0x18]; 6982 u8 priority[0x4]; 6983 u8 cong_protocol[0x4]; 6984 6985 u8 reserved_at_60[0x20]; 6986 }; 6987 6988 struct mlx5_ifc_query_cong_statistics_out_bits { 6989 u8 status[0x8]; 6990 u8 reserved_at_8[0x18]; 6991 6992 u8 syndrome[0x20]; 6993 6994 u8 reserved_at_40[0x40]; 6995 6996 u8 rp_cur_flows[0x20]; 6997 6998 u8 sum_flows[0x20]; 6999 7000 u8 rp_cnp_ignored_high[0x20]; 7001 7002 u8 rp_cnp_ignored_low[0x20]; 7003 7004 u8 rp_cnp_handled_high[0x20]; 7005 7006 u8 rp_cnp_handled_low[0x20]; 7007 7008 u8 reserved_at_140[0x100]; 7009 7010 u8 time_stamp_high[0x20]; 7011 7012 u8 time_stamp_low[0x20]; 7013 7014 u8 accumulators_period[0x20]; 7015 7016 u8 np_ecn_marked_roce_packets_high[0x20]; 7017 7018 u8 np_ecn_marked_roce_packets_low[0x20]; 7019 7020 u8 np_cnp_sent_high[0x20]; 7021 7022 u8 np_cnp_sent_low[0x20]; 7023 7024 u8 reserved_at_320[0x560]; 7025 }; 7026 7027 struct mlx5_ifc_query_cong_statistics_in_bits { 7028 u8 opcode[0x10]; 7029 u8 reserved_at_10[0x10]; 7030 7031 u8 reserved_at_20[0x10]; 7032 u8 op_mod[0x10]; 7033 7034 u8 clear[0x1]; 7035 u8 reserved_at_41[0x1f]; 7036 7037 u8 reserved_at_60[0x20]; 7038 }; 7039 7040 struct mlx5_ifc_query_cong_params_out_bits { 7041 u8 status[0x8]; 7042 u8 reserved_at_8[0x18]; 7043 7044 u8 syndrome[0x20]; 7045 7046 u8 reserved_at_40[0x40]; 7047 7048 union mlx5_ifc_cong_control_roce_ecn_auto_bits congestion_parameters; 7049 }; 7050 7051 struct mlx5_ifc_query_cong_params_in_bits { 7052 u8 opcode[0x10]; 7053 u8 reserved_at_10[0x10]; 7054 7055 u8 reserved_at_20[0x10]; 7056 u8 op_mod[0x10]; 7057 7058 u8 reserved_at_40[0x1c]; 7059 u8 cong_protocol[0x4]; 7060 7061 u8 reserved_at_60[0x20]; 7062 }; 7063 7064 struct mlx5_ifc_query_adapter_out_bits { 7065 u8 status[0x8]; 7066 u8 reserved_at_8[0x18]; 7067 7068 u8 syndrome[0x20]; 7069 7070 u8 reserved_at_40[0x40]; 7071 7072 struct mlx5_ifc_query_adapter_param_block_bits query_adapter_struct; 7073 }; 7074 7075 struct mlx5_ifc_query_adapter_in_bits { 7076 u8 opcode[0x10]; 7077 u8 reserved_at_10[0x10]; 7078 7079 u8 reserved_at_20[0x10]; 7080 u8 op_mod[0x10]; 7081 7082 u8 reserved_at_40[0x40]; 7083 }; 7084 7085 struct mlx5_ifc_qp_2rst_out_bits { 7086 u8 status[0x8]; 7087 u8 reserved_at_8[0x18]; 7088 7089 u8 syndrome[0x20]; 7090 7091 u8 reserved_at_40[0x40]; 7092 }; 7093 7094 struct mlx5_ifc_qp_2rst_in_bits { 7095 u8 opcode[0x10]; 7096 u8 uid[0x10]; 7097 7098 u8 reserved_at_20[0x10]; 7099 u8 op_mod[0x10]; 7100 7101 u8 reserved_at_40[0x8]; 7102 u8 qpn[0x18]; 7103 7104 u8 reserved_at_60[0x20]; 7105 }; 7106 7107 struct mlx5_ifc_qp_2err_out_bits { 7108 u8 status[0x8]; 7109 u8 reserved_at_8[0x18]; 7110 7111 u8 syndrome[0x20]; 7112 7113 u8 reserved_at_40[0x40]; 7114 }; 7115 7116 struct mlx5_ifc_qp_2err_in_bits { 7117 u8 opcode[0x10]; 7118 u8 uid[0x10]; 7119 7120 u8 reserved_at_20[0x10]; 7121 u8 op_mod[0x10]; 7122 7123 u8 reserved_at_40[0x8]; 7124 u8 qpn[0x18]; 7125 7126 u8 reserved_at_60[0x20]; 7127 }; 7128 7129 struct mlx5_ifc_page_fault_resume_out_bits { 7130 u8 status[0x8]; 7131 u8 reserved_at_8[0x18]; 7132 7133 u8 syndrome[0x20]; 7134 7135 u8 reserved_at_40[0x40]; 7136 }; 7137 7138 struct mlx5_ifc_page_fault_resume_in_bits { 7139 u8 opcode[0x10]; 7140 u8 reserved_at_10[0x10]; 7141 7142 u8 reserved_at_20[0x10]; 7143 u8 op_mod[0x10]; 7144 7145 u8 error[0x1]; 7146 u8 reserved_at_41[0x4]; 7147 u8 page_fault_type[0x3]; 7148 u8 wq_number[0x18]; 7149 7150 u8 reserved_at_60[0x8]; 7151 u8 token[0x18]; 7152 }; 7153 7154 struct mlx5_ifc_nop_out_bits { 7155 u8 status[0x8]; 7156 u8 reserved_at_8[0x18]; 7157 7158 u8 syndrome[0x20]; 7159 7160 u8 reserved_at_40[0x40]; 7161 }; 7162 7163 struct mlx5_ifc_nop_in_bits { 7164 u8 opcode[0x10]; 7165 u8 reserved_at_10[0x10]; 7166 7167 u8 reserved_at_20[0x10]; 7168 u8 op_mod[0x10]; 7169 7170 u8 reserved_at_40[0x40]; 7171 }; 7172 7173 struct mlx5_ifc_modify_vport_state_out_bits { 7174 u8 status[0x8]; 7175 u8 reserved_at_8[0x18]; 7176 7177 u8 syndrome[0x20]; 7178 7179 u8 reserved_at_40[0x40]; 7180 }; 7181 7182 struct mlx5_ifc_modify_vport_state_in_bits { 7183 u8 opcode[0x10]; 7184 u8 reserved_at_10[0x10]; 7185 7186 u8 reserved_at_20[0x10]; 7187 u8 op_mod[0x10]; 7188 7189 u8 other_vport[0x1]; 7190 u8 reserved_at_41[0xf]; 7191 u8 vport_number[0x10]; 7192 7193 u8 reserved_at_60[0x18]; 7194 u8 admin_state[0x4]; 7195 u8 reserved_at_7c[0x4]; 7196 }; 7197 7198 struct mlx5_ifc_modify_tis_out_bits { 7199 u8 status[0x8]; 7200 u8 reserved_at_8[0x18]; 7201 7202 u8 syndrome[0x20]; 7203 7204 u8 reserved_at_40[0x40]; 7205 }; 7206 7207 struct mlx5_ifc_modify_tis_bitmask_bits { 7208 u8 reserved_at_0[0x20]; 7209 7210 u8 reserved_at_20[0x1d]; 7211 u8 lag_tx_port_affinity[0x1]; 7212 u8 strict_lag_tx_port_affinity[0x1]; 7213 u8 prio[0x1]; 7214 }; 7215 7216 struct mlx5_ifc_modify_tis_in_bits { 7217 u8 opcode[0x10]; 7218 u8 uid[0x10]; 7219 7220 u8 reserved_at_20[0x10]; 7221 u8 op_mod[0x10]; 7222 7223 u8 reserved_at_40[0x8]; 7224 u8 tisn[0x18]; 7225 7226 u8 reserved_at_60[0x20]; 7227 7228 struct mlx5_ifc_modify_tis_bitmask_bits bitmask; 7229 7230 u8 reserved_at_c0[0x40]; 7231 7232 struct mlx5_ifc_tisc_bits ctx; 7233 }; 7234 7235 struct mlx5_ifc_modify_tir_bitmask_bits { 7236 u8 reserved_at_0[0x20]; 7237 7238 u8 reserved_at_20[0x1b]; 7239 u8 self_lb_en[0x1]; 7240 u8 reserved_at_3c[0x1]; 7241 u8 hash[0x1]; 7242 u8 reserved_at_3e[0x1]; 7243 u8 packet_merge[0x1]; 7244 }; 7245 7246 struct mlx5_ifc_modify_tir_out_bits { 7247 u8 status[0x8]; 7248 u8 reserved_at_8[0x18]; 7249 7250 u8 syndrome[0x20]; 7251 7252 u8 reserved_at_40[0x40]; 7253 }; 7254 7255 struct mlx5_ifc_modify_tir_in_bits { 7256 u8 opcode[0x10]; 7257 u8 uid[0x10]; 7258 7259 u8 reserved_at_20[0x10]; 7260 u8 op_mod[0x10]; 7261 7262 u8 reserved_at_40[0x8]; 7263 u8 tirn[0x18]; 7264 7265 u8 reserved_at_60[0x20]; 7266 7267 struct mlx5_ifc_modify_tir_bitmask_bits bitmask; 7268 7269 u8 reserved_at_c0[0x40]; 7270 7271 struct mlx5_ifc_tirc_bits ctx; 7272 }; 7273 7274 struct mlx5_ifc_modify_sq_out_bits { 7275 u8 status[0x8]; 7276 u8 reserved_at_8[0x18]; 7277 7278 u8 syndrome[0x20]; 7279 7280 u8 reserved_at_40[0x40]; 7281 }; 7282 7283 struct mlx5_ifc_modify_sq_in_bits { 7284 u8 opcode[0x10]; 7285 u8 uid[0x10]; 7286 7287 u8 reserved_at_20[0x10]; 7288 u8 op_mod[0x10]; 7289 7290 u8 sq_state[0x4]; 7291 u8 reserved_at_44[0x4]; 7292 u8 sqn[0x18]; 7293 7294 u8 reserved_at_60[0x20]; 7295 7296 u8 modify_bitmask[0x40]; 7297 7298 u8 reserved_at_c0[0x40]; 7299 7300 struct mlx5_ifc_sqc_bits ctx; 7301 }; 7302 7303 struct mlx5_ifc_modify_scheduling_element_out_bits { 7304 u8 status[0x8]; 7305 u8 reserved_at_8[0x18]; 7306 7307 u8 syndrome[0x20]; 7308 7309 u8 reserved_at_40[0x1c0]; 7310 }; 7311 7312 enum { 7313 MODIFY_SCHEDULING_ELEMENT_IN_MODIFY_BITMASK_BW_SHARE = 0x1, 7314 MODIFY_SCHEDULING_ELEMENT_IN_MODIFY_BITMASK_MAX_AVERAGE_BW = 0x2, 7315 }; 7316 7317 struct mlx5_ifc_modify_scheduling_element_in_bits { 7318 u8 opcode[0x10]; 7319 u8 reserved_at_10[0x10]; 7320 7321 u8 reserved_at_20[0x10]; 7322 u8 op_mod[0x10]; 7323 7324 u8 scheduling_hierarchy[0x8]; 7325 u8 reserved_at_48[0x18]; 7326 7327 u8 scheduling_element_id[0x20]; 7328 7329 u8 reserved_at_80[0x20]; 7330 7331 u8 modify_bitmask[0x20]; 7332 7333 u8 reserved_at_c0[0x40]; 7334 7335 struct mlx5_ifc_scheduling_context_bits scheduling_context; 7336 7337 u8 reserved_at_300[0x100]; 7338 }; 7339 7340 struct mlx5_ifc_modify_rqt_out_bits { 7341 u8 status[0x8]; 7342 u8 reserved_at_8[0x18]; 7343 7344 u8 syndrome[0x20]; 7345 7346 u8 reserved_at_40[0x40]; 7347 }; 7348 7349 struct mlx5_ifc_rqt_bitmask_bits { 7350 u8 reserved_at_0[0x20]; 7351 7352 u8 reserved_at_20[0x1f]; 7353 u8 rqn_list[0x1]; 7354 }; 7355 7356 struct mlx5_ifc_modify_rqt_in_bits { 7357 u8 opcode[0x10]; 7358 u8 uid[0x10]; 7359 7360 u8 reserved_at_20[0x10]; 7361 u8 op_mod[0x10]; 7362 7363 u8 reserved_at_40[0x8]; 7364 u8 rqtn[0x18]; 7365 7366 u8 reserved_at_60[0x20]; 7367 7368 struct mlx5_ifc_rqt_bitmask_bits bitmask; 7369 7370 u8 reserved_at_c0[0x40]; 7371 7372 struct mlx5_ifc_rqtc_bits ctx; 7373 }; 7374 7375 struct mlx5_ifc_modify_rq_out_bits { 7376 u8 status[0x8]; 7377 u8 reserved_at_8[0x18]; 7378 7379 u8 syndrome[0x20]; 7380 7381 u8 reserved_at_40[0x40]; 7382 }; 7383 7384 enum { 7385 MLX5_MODIFY_RQ_IN_MODIFY_BITMASK_VSD = 1ULL << 1, 7386 MLX5_MODIFY_RQ_IN_MODIFY_BITMASK_SCATTER_FCS = 1ULL << 2, 7387 MLX5_MODIFY_RQ_IN_MODIFY_BITMASK_RQ_COUNTER_SET_ID = 1ULL << 3, 7388 }; 7389 7390 struct mlx5_ifc_modify_rq_in_bits { 7391 u8 opcode[0x10]; 7392 u8 uid[0x10]; 7393 7394 u8 reserved_at_20[0x10]; 7395 u8 op_mod[0x10]; 7396 7397 u8 rq_state[0x4]; 7398 u8 reserved_at_44[0x4]; 7399 u8 rqn[0x18]; 7400 7401 u8 reserved_at_60[0x20]; 7402 7403 u8 modify_bitmask[0x40]; 7404 7405 u8 reserved_at_c0[0x40]; 7406 7407 struct mlx5_ifc_rqc_bits ctx; 7408 }; 7409 7410 struct mlx5_ifc_modify_rmp_out_bits { 7411 u8 status[0x8]; 7412 u8 reserved_at_8[0x18]; 7413 7414 u8 syndrome[0x20]; 7415 7416 u8 reserved_at_40[0x40]; 7417 }; 7418 7419 struct mlx5_ifc_rmp_bitmask_bits { 7420 u8 reserved_at_0[0x20]; 7421 7422 u8 reserved_at_20[0x1f]; 7423 u8 lwm[0x1]; 7424 }; 7425 7426 struct mlx5_ifc_modify_rmp_in_bits { 7427 u8 opcode[0x10]; 7428 u8 uid[0x10]; 7429 7430 u8 reserved_at_20[0x10]; 7431 u8 op_mod[0x10]; 7432 7433 u8 rmp_state[0x4]; 7434 u8 reserved_at_44[0x4]; 7435 u8 rmpn[0x18]; 7436 7437 u8 reserved_at_60[0x20]; 7438 7439 struct mlx5_ifc_rmp_bitmask_bits bitmask; 7440 7441 u8 reserved_at_c0[0x40]; 7442 7443 struct mlx5_ifc_rmpc_bits ctx; 7444 }; 7445 7446 struct mlx5_ifc_modify_nic_vport_context_out_bits { 7447 u8 status[0x8]; 7448 u8 reserved_at_8[0x18]; 7449 7450 u8 syndrome[0x20]; 7451 7452 u8 reserved_at_40[0x40]; 7453 }; 7454 7455 struct mlx5_ifc_modify_nic_vport_field_select_bits { 7456 u8 reserved_at_0[0x12]; 7457 u8 affiliation[0x1]; 7458 u8 reserved_at_13[0x1]; 7459 u8 disable_uc_local_lb[0x1]; 7460 u8 disable_mc_local_lb[0x1]; 7461 u8 node_guid[0x1]; 7462 u8 port_guid[0x1]; 7463 u8 min_inline[0x1]; 7464 u8 mtu[0x1]; 7465 u8 change_event[0x1]; 7466 u8 promisc[0x1]; 7467 u8 permanent_address[0x1]; 7468 u8 addresses_list[0x1]; 7469 u8 roce_en[0x1]; 7470 u8 reserved_at_1f[0x1]; 7471 }; 7472 7473 struct mlx5_ifc_modify_nic_vport_context_in_bits { 7474 u8 opcode[0x10]; 7475 u8 reserved_at_10[0x10]; 7476 7477 u8 reserved_at_20[0x10]; 7478 u8 op_mod[0x10]; 7479 7480 u8 other_vport[0x1]; 7481 u8 reserved_at_41[0xf]; 7482 u8 vport_number[0x10]; 7483 7484 struct mlx5_ifc_modify_nic_vport_field_select_bits field_select; 7485 7486 u8 reserved_at_80[0x780]; 7487 7488 struct mlx5_ifc_nic_vport_context_bits nic_vport_context; 7489 }; 7490 7491 struct mlx5_ifc_modify_hca_vport_context_out_bits { 7492 u8 status[0x8]; 7493 u8 reserved_at_8[0x18]; 7494 7495 u8 syndrome[0x20]; 7496 7497 u8 reserved_at_40[0x40]; 7498 }; 7499 7500 struct mlx5_ifc_modify_hca_vport_context_in_bits { 7501 u8 opcode[0x10]; 7502 u8 reserved_at_10[0x10]; 7503 7504 u8 reserved_at_20[0x10]; 7505 u8 op_mod[0x10]; 7506 7507 u8 other_vport[0x1]; 7508 u8 reserved_at_41[0xb]; 7509 u8 port_num[0x4]; 7510 u8 vport_number[0x10]; 7511 7512 u8 reserved_at_60[0x20]; 7513 7514 struct mlx5_ifc_hca_vport_context_bits hca_vport_context; 7515 }; 7516 7517 struct mlx5_ifc_modify_cq_out_bits { 7518 u8 status[0x8]; 7519 u8 reserved_at_8[0x18]; 7520 7521 u8 syndrome[0x20]; 7522 7523 u8 reserved_at_40[0x40]; 7524 }; 7525 7526 enum { 7527 MLX5_MODIFY_CQ_IN_OP_MOD_MODIFY_CQ = 0x0, 7528 MLX5_MODIFY_CQ_IN_OP_MOD_RESIZE_CQ = 0x1, 7529 }; 7530 7531 struct mlx5_ifc_modify_cq_in_bits { 7532 u8 opcode[0x10]; 7533 u8 uid[0x10]; 7534 7535 u8 reserved_at_20[0x10]; 7536 u8 op_mod[0x10]; 7537 7538 u8 reserved_at_40[0x8]; 7539 u8 cqn[0x18]; 7540 7541 union mlx5_ifc_modify_field_select_resize_field_select_auto_bits modify_field_select_resize_field_select; 7542 7543 struct mlx5_ifc_cqc_bits cq_context; 7544 7545 u8 reserved_at_280[0x60]; 7546 7547 u8 cq_umem_valid[0x1]; 7548 u8 reserved_at_2e1[0x1f]; 7549 7550 u8 reserved_at_300[0x580]; 7551 7552 u8 pas[][0x40]; 7553 }; 7554 7555 struct mlx5_ifc_modify_cong_status_out_bits { 7556 u8 status[0x8]; 7557 u8 reserved_at_8[0x18]; 7558 7559 u8 syndrome[0x20]; 7560 7561 u8 reserved_at_40[0x40]; 7562 }; 7563 7564 struct mlx5_ifc_modify_cong_status_in_bits { 7565 u8 opcode[0x10]; 7566 u8 reserved_at_10[0x10]; 7567 7568 u8 reserved_at_20[0x10]; 7569 u8 op_mod[0x10]; 7570 7571 u8 reserved_at_40[0x18]; 7572 u8 priority[0x4]; 7573 u8 cong_protocol[0x4]; 7574 7575 u8 enable[0x1]; 7576 u8 tag_enable[0x1]; 7577 u8 reserved_at_62[0x1e]; 7578 }; 7579 7580 struct mlx5_ifc_modify_cong_params_out_bits { 7581 u8 status[0x8]; 7582 u8 reserved_at_8[0x18]; 7583 7584 u8 syndrome[0x20]; 7585 7586 u8 reserved_at_40[0x40]; 7587 }; 7588 7589 struct mlx5_ifc_modify_cong_params_in_bits { 7590 u8 opcode[0x10]; 7591 u8 reserved_at_10[0x10]; 7592 7593 u8 reserved_at_20[0x10]; 7594 u8 op_mod[0x10]; 7595 7596 u8 reserved_at_40[0x1c]; 7597 u8 cong_protocol[0x4]; 7598 7599 union mlx5_ifc_field_select_802_1_r_roce_auto_bits field_select; 7600 7601 u8 reserved_at_80[0x80]; 7602 7603 union mlx5_ifc_cong_control_roce_ecn_auto_bits congestion_parameters; 7604 }; 7605 7606 struct mlx5_ifc_manage_pages_out_bits { 7607 u8 status[0x8]; 7608 u8 reserved_at_8[0x18]; 7609 7610 u8 syndrome[0x20]; 7611 7612 u8 output_num_entries[0x20]; 7613 7614 u8 reserved_at_60[0x20]; 7615 7616 u8 pas[][0x40]; 7617 }; 7618 7619 enum { 7620 MLX5_MANAGE_PAGES_IN_OP_MOD_ALLOCATION_FAIL = 0x0, 7621 MLX5_MANAGE_PAGES_IN_OP_MOD_ALLOCATION_SUCCESS = 0x1, 7622 MLX5_MANAGE_PAGES_IN_OP_MOD_HCA_RETURN_PAGES = 0x2, 7623 }; 7624 7625 struct mlx5_ifc_manage_pages_in_bits { 7626 u8 opcode[0x10]; 7627 u8 reserved_at_10[0x10]; 7628 7629 u8 reserved_at_20[0x10]; 7630 u8 op_mod[0x10]; 7631 7632 u8 embedded_cpu_function[0x1]; 7633 u8 reserved_at_41[0xf]; 7634 u8 function_id[0x10]; 7635 7636 u8 input_num_entries[0x20]; 7637 7638 u8 pas[][0x40]; 7639 }; 7640 7641 struct mlx5_ifc_mad_ifc_out_bits { 7642 u8 status[0x8]; 7643 u8 reserved_at_8[0x18]; 7644 7645 u8 syndrome[0x20]; 7646 7647 u8 reserved_at_40[0x40]; 7648 7649 u8 response_mad_packet[256][0x8]; 7650 }; 7651 7652 struct mlx5_ifc_mad_ifc_in_bits { 7653 u8 opcode[0x10]; 7654 u8 reserved_at_10[0x10]; 7655 7656 u8 reserved_at_20[0x10]; 7657 u8 op_mod[0x10]; 7658 7659 u8 remote_lid[0x10]; 7660 u8 reserved_at_50[0x8]; 7661 u8 port[0x8]; 7662 7663 u8 reserved_at_60[0x20]; 7664 7665 u8 mad[256][0x8]; 7666 }; 7667 7668 struct mlx5_ifc_init_hca_out_bits { 7669 u8 status[0x8]; 7670 u8 reserved_at_8[0x18]; 7671 7672 u8 syndrome[0x20]; 7673 7674 u8 reserved_at_40[0x40]; 7675 }; 7676 7677 struct mlx5_ifc_init_hca_in_bits { 7678 u8 opcode[0x10]; 7679 u8 reserved_at_10[0x10]; 7680 7681 u8 reserved_at_20[0x10]; 7682 u8 op_mod[0x10]; 7683 7684 u8 reserved_at_40[0x20]; 7685 7686 u8 reserved_at_60[0x2]; 7687 u8 sw_vhca_id[0xe]; 7688 u8 reserved_at_70[0x10]; 7689 7690 u8 sw_owner_id[4][0x20]; 7691 }; 7692 7693 struct mlx5_ifc_init2rtr_qp_out_bits { 7694 u8 status[0x8]; 7695 u8 reserved_at_8[0x18]; 7696 7697 u8 syndrome[0x20]; 7698 7699 u8 reserved_at_40[0x20]; 7700 u8 ece[0x20]; 7701 }; 7702 7703 struct mlx5_ifc_init2rtr_qp_in_bits { 7704 u8 opcode[0x10]; 7705 u8 uid[0x10]; 7706 7707 u8 reserved_at_20[0x10]; 7708 u8 op_mod[0x10]; 7709 7710 u8 reserved_at_40[0x8]; 7711 u8 qpn[0x18]; 7712 7713 u8 reserved_at_60[0x20]; 7714 7715 u8 opt_param_mask[0x20]; 7716 7717 u8 ece[0x20]; 7718 7719 struct mlx5_ifc_qpc_bits qpc; 7720 7721 u8 reserved_at_800[0x80]; 7722 }; 7723 7724 struct mlx5_ifc_init2init_qp_out_bits { 7725 u8 status[0x8]; 7726 u8 reserved_at_8[0x18]; 7727 7728 u8 syndrome[0x20]; 7729 7730 u8 reserved_at_40[0x20]; 7731 u8 ece[0x20]; 7732 }; 7733 7734 struct mlx5_ifc_init2init_qp_in_bits { 7735 u8 opcode[0x10]; 7736 u8 uid[0x10]; 7737 7738 u8 reserved_at_20[0x10]; 7739 u8 op_mod[0x10]; 7740 7741 u8 reserved_at_40[0x8]; 7742 u8 qpn[0x18]; 7743 7744 u8 reserved_at_60[0x20]; 7745 7746 u8 opt_param_mask[0x20]; 7747 7748 u8 ece[0x20]; 7749 7750 struct mlx5_ifc_qpc_bits qpc; 7751 7752 u8 reserved_at_800[0x80]; 7753 }; 7754 7755 struct mlx5_ifc_get_dropped_packet_log_out_bits { 7756 u8 status[0x8]; 7757 u8 reserved_at_8[0x18]; 7758 7759 u8 syndrome[0x20]; 7760 7761 u8 reserved_at_40[0x40]; 7762 7763 u8 packet_headers_log[128][0x8]; 7764 7765 u8 packet_syndrome[64][0x8]; 7766 }; 7767 7768 struct mlx5_ifc_get_dropped_packet_log_in_bits { 7769 u8 opcode[0x10]; 7770 u8 reserved_at_10[0x10]; 7771 7772 u8 reserved_at_20[0x10]; 7773 u8 op_mod[0x10]; 7774 7775 u8 reserved_at_40[0x40]; 7776 }; 7777 7778 struct mlx5_ifc_gen_eqe_in_bits { 7779 u8 opcode[0x10]; 7780 u8 reserved_at_10[0x10]; 7781 7782 u8 reserved_at_20[0x10]; 7783 u8 op_mod[0x10]; 7784 7785 u8 reserved_at_40[0x18]; 7786 u8 eq_number[0x8]; 7787 7788 u8 reserved_at_60[0x20]; 7789 7790 u8 eqe[64][0x8]; 7791 }; 7792 7793 struct mlx5_ifc_gen_eq_out_bits { 7794 u8 status[0x8]; 7795 u8 reserved_at_8[0x18]; 7796 7797 u8 syndrome[0x20]; 7798 7799 u8 reserved_at_40[0x40]; 7800 }; 7801 7802 struct mlx5_ifc_enable_hca_out_bits { 7803 u8 status[0x8]; 7804 u8 reserved_at_8[0x18]; 7805 7806 u8 syndrome[0x20]; 7807 7808 u8 reserved_at_40[0x20]; 7809 }; 7810 7811 struct mlx5_ifc_enable_hca_in_bits { 7812 u8 opcode[0x10]; 7813 u8 reserved_at_10[0x10]; 7814 7815 u8 reserved_at_20[0x10]; 7816 u8 op_mod[0x10]; 7817 7818 u8 embedded_cpu_function[0x1]; 7819 u8 reserved_at_41[0xf]; 7820 u8 function_id[0x10]; 7821 7822 u8 reserved_at_60[0x20]; 7823 }; 7824 7825 struct mlx5_ifc_drain_dct_out_bits { 7826 u8 status[0x8]; 7827 u8 reserved_at_8[0x18]; 7828 7829 u8 syndrome[0x20]; 7830 7831 u8 reserved_at_40[0x40]; 7832 }; 7833 7834 struct mlx5_ifc_drain_dct_in_bits { 7835 u8 opcode[0x10]; 7836 u8 uid[0x10]; 7837 7838 u8 reserved_at_20[0x10]; 7839 u8 op_mod[0x10]; 7840 7841 u8 reserved_at_40[0x8]; 7842 u8 dctn[0x18]; 7843 7844 u8 reserved_at_60[0x20]; 7845 }; 7846 7847 struct mlx5_ifc_disable_hca_out_bits { 7848 u8 status[0x8]; 7849 u8 reserved_at_8[0x18]; 7850 7851 u8 syndrome[0x20]; 7852 7853 u8 reserved_at_40[0x20]; 7854 }; 7855 7856 struct mlx5_ifc_disable_hca_in_bits { 7857 u8 opcode[0x10]; 7858 u8 reserved_at_10[0x10]; 7859 7860 u8 reserved_at_20[0x10]; 7861 u8 op_mod[0x10]; 7862 7863 u8 embedded_cpu_function[0x1]; 7864 u8 reserved_at_41[0xf]; 7865 u8 function_id[0x10]; 7866 7867 u8 reserved_at_60[0x20]; 7868 }; 7869 7870 struct mlx5_ifc_detach_from_mcg_out_bits { 7871 u8 status[0x8]; 7872 u8 reserved_at_8[0x18]; 7873 7874 u8 syndrome[0x20]; 7875 7876 u8 reserved_at_40[0x40]; 7877 }; 7878 7879 struct mlx5_ifc_detach_from_mcg_in_bits { 7880 u8 opcode[0x10]; 7881 u8 uid[0x10]; 7882 7883 u8 reserved_at_20[0x10]; 7884 u8 op_mod[0x10]; 7885 7886 u8 reserved_at_40[0x8]; 7887 u8 qpn[0x18]; 7888 7889 u8 reserved_at_60[0x20]; 7890 7891 u8 multicast_gid[16][0x8]; 7892 }; 7893 7894 struct mlx5_ifc_destroy_xrq_out_bits { 7895 u8 status[0x8]; 7896 u8 reserved_at_8[0x18]; 7897 7898 u8 syndrome[0x20]; 7899 7900 u8 reserved_at_40[0x40]; 7901 }; 7902 7903 struct mlx5_ifc_destroy_xrq_in_bits { 7904 u8 opcode[0x10]; 7905 u8 uid[0x10]; 7906 7907 u8 reserved_at_20[0x10]; 7908 u8 op_mod[0x10]; 7909 7910 u8 reserved_at_40[0x8]; 7911 u8 xrqn[0x18]; 7912 7913 u8 reserved_at_60[0x20]; 7914 }; 7915 7916 struct mlx5_ifc_destroy_xrc_srq_out_bits { 7917 u8 status[0x8]; 7918 u8 reserved_at_8[0x18]; 7919 7920 u8 syndrome[0x20]; 7921 7922 u8 reserved_at_40[0x40]; 7923 }; 7924 7925 struct mlx5_ifc_destroy_xrc_srq_in_bits { 7926 u8 opcode[0x10]; 7927 u8 uid[0x10]; 7928 7929 u8 reserved_at_20[0x10]; 7930 u8 op_mod[0x10]; 7931 7932 u8 reserved_at_40[0x8]; 7933 u8 xrc_srqn[0x18]; 7934 7935 u8 reserved_at_60[0x20]; 7936 }; 7937 7938 struct mlx5_ifc_destroy_tis_out_bits { 7939 u8 status[0x8]; 7940 u8 reserved_at_8[0x18]; 7941 7942 u8 syndrome[0x20]; 7943 7944 u8 reserved_at_40[0x40]; 7945 }; 7946 7947 struct mlx5_ifc_destroy_tis_in_bits { 7948 u8 opcode[0x10]; 7949 u8 uid[0x10]; 7950 7951 u8 reserved_at_20[0x10]; 7952 u8 op_mod[0x10]; 7953 7954 u8 reserved_at_40[0x8]; 7955 u8 tisn[0x18]; 7956 7957 u8 reserved_at_60[0x20]; 7958 }; 7959 7960 struct mlx5_ifc_destroy_tir_out_bits { 7961 u8 status[0x8]; 7962 u8 reserved_at_8[0x18]; 7963 7964 u8 syndrome[0x20]; 7965 7966 u8 reserved_at_40[0x40]; 7967 }; 7968 7969 struct mlx5_ifc_destroy_tir_in_bits { 7970 u8 opcode[0x10]; 7971 u8 uid[0x10]; 7972 7973 u8 reserved_at_20[0x10]; 7974 u8 op_mod[0x10]; 7975 7976 u8 reserved_at_40[0x8]; 7977 u8 tirn[0x18]; 7978 7979 u8 reserved_at_60[0x20]; 7980 }; 7981 7982 struct mlx5_ifc_destroy_srq_out_bits { 7983 u8 status[0x8]; 7984 u8 reserved_at_8[0x18]; 7985 7986 u8 syndrome[0x20]; 7987 7988 u8 reserved_at_40[0x40]; 7989 }; 7990 7991 struct mlx5_ifc_destroy_srq_in_bits { 7992 u8 opcode[0x10]; 7993 u8 uid[0x10]; 7994 7995 u8 reserved_at_20[0x10]; 7996 u8 op_mod[0x10]; 7997 7998 u8 reserved_at_40[0x8]; 7999 u8 srqn[0x18]; 8000 8001 u8 reserved_at_60[0x20]; 8002 }; 8003 8004 struct mlx5_ifc_destroy_sq_out_bits { 8005 u8 status[0x8]; 8006 u8 reserved_at_8[0x18]; 8007 8008 u8 syndrome[0x20]; 8009 8010 u8 reserved_at_40[0x40]; 8011 }; 8012 8013 struct mlx5_ifc_destroy_sq_in_bits { 8014 u8 opcode[0x10]; 8015 u8 uid[0x10]; 8016 8017 u8 reserved_at_20[0x10]; 8018 u8 op_mod[0x10]; 8019 8020 u8 reserved_at_40[0x8]; 8021 u8 sqn[0x18]; 8022 8023 u8 reserved_at_60[0x20]; 8024 }; 8025 8026 struct mlx5_ifc_destroy_scheduling_element_out_bits { 8027 u8 status[0x8]; 8028 u8 reserved_at_8[0x18]; 8029 8030 u8 syndrome[0x20]; 8031 8032 u8 reserved_at_40[0x1c0]; 8033 }; 8034 8035 struct mlx5_ifc_destroy_scheduling_element_in_bits { 8036 u8 opcode[0x10]; 8037 u8 reserved_at_10[0x10]; 8038 8039 u8 reserved_at_20[0x10]; 8040 u8 op_mod[0x10]; 8041 8042 u8 scheduling_hierarchy[0x8]; 8043 u8 reserved_at_48[0x18]; 8044 8045 u8 scheduling_element_id[0x20]; 8046 8047 u8 reserved_at_80[0x180]; 8048 }; 8049 8050 struct mlx5_ifc_destroy_rqt_out_bits { 8051 u8 status[0x8]; 8052 u8 reserved_at_8[0x18]; 8053 8054 u8 syndrome[0x20]; 8055 8056 u8 reserved_at_40[0x40]; 8057 }; 8058 8059 struct mlx5_ifc_destroy_rqt_in_bits { 8060 u8 opcode[0x10]; 8061 u8 uid[0x10]; 8062 8063 u8 reserved_at_20[0x10]; 8064 u8 op_mod[0x10]; 8065 8066 u8 reserved_at_40[0x8]; 8067 u8 rqtn[0x18]; 8068 8069 u8 reserved_at_60[0x20]; 8070 }; 8071 8072 struct mlx5_ifc_destroy_rq_out_bits { 8073 u8 status[0x8]; 8074 u8 reserved_at_8[0x18]; 8075 8076 u8 syndrome[0x20]; 8077 8078 u8 reserved_at_40[0x40]; 8079 }; 8080 8081 struct mlx5_ifc_destroy_rq_in_bits { 8082 u8 opcode[0x10]; 8083 u8 uid[0x10]; 8084 8085 u8 reserved_at_20[0x10]; 8086 u8 op_mod[0x10]; 8087 8088 u8 reserved_at_40[0x8]; 8089 u8 rqn[0x18]; 8090 8091 u8 reserved_at_60[0x20]; 8092 }; 8093 8094 struct mlx5_ifc_set_delay_drop_params_in_bits { 8095 u8 opcode[0x10]; 8096 u8 reserved_at_10[0x10]; 8097 8098 u8 reserved_at_20[0x10]; 8099 u8 op_mod[0x10]; 8100 8101 u8 reserved_at_40[0x20]; 8102 8103 u8 reserved_at_60[0x10]; 8104 u8 delay_drop_timeout[0x10]; 8105 }; 8106 8107 struct mlx5_ifc_set_delay_drop_params_out_bits { 8108 u8 status[0x8]; 8109 u8 reserved_at_8[0x18]; 8110 8111 u8 syndrome[0x20]; 8112 8113 u8 reserved_at_40[0x40]; 8114 }; 8115 8116 struct mlx5_ifc_destroy_rmp_out_bits { 8117 u8 status[0x8]; 8118 u8 reserved_at_8[0x18]; 8119 8120 u8 syndrome[0x20]; 8121 8122 u8 reserved_at_40[0x40]; 8123 }; 8124 8125 struct mlx5_ifc_destroy_rmp_in_bits { 8126 u8 opcode[0x10]; 8127 u8 uid[0x10]; 8128 8129 u8 reserved_at_20[0x10]; 8130 u8 op_mod[0x10]; 8131 8132 u8 reserved_at_40[0x8]; 8133 u8 rmpn[0x18]; 8134 8135 u8 reserved_at_60[0x20]; 8136 }; 8137 8138 struct mlx5_ifc_destroy_qp_out_bits { 8139 u8 status[0x8]; 8140 u8 reserved_at_8[0x18]; 8141 8142 u8 syndrome[0x20]; 8143 8144 u8 reserved_at_40[0x40]; 8145 }; 8146 8147 struct mlx5_ifc_destroy_qp_in_bits { 8148 u8 opcode[0x10]; 8149 u8 uid[0x10]; 8150 8151 u8 reserved_at_20[0x10]; 8152 u8 op_mod[0x10]; 8153 8154 u8 reserved_at_40[0x8]; 8155 u8 qpn[0x18]; 8156 8157 u8 reserved_at_60[0x20]; 8158 }; 8159 8160 struct mlx5_ifc_destroy_psv_out_bits { 8161 u8 status[0x8]; 8162 u8 reserved_at_8[0x18]; 8163 8164 u8 syndrome[0x20]; 8165 8166 u8 reserved_at_40[0x40]; 8167 }; 8168 8169 struct mlx5_ifc_destroy_psv_in_bits { 8170 u8 opcode[0x10]; 8171 u8 reserved_at_10[0x10]; 8172 8173 u8 reserved_at_20[0x10]; 8174 u8 op_mod[0x10]; 8175 8176 u8 reserved_at_40[0x8]; 8177 u8 psvn[0x18]; 8178 8179 u8 reserved_at_60[0x20]; 8180 }; 8181 8182 struct mlx5_ifc_destroy_mkey_out_bits { 8183 u8 status[0x8]; 8184 u8 reserved_at_8[0x18]; 8185 8186 u8 syndrome[0x20]; 8187 8188 u8 reserved_at_40[0x40]; 8189 }; 8190 8191 struct mlx5_ifc_destroy_mkey_in_bits { 8192 u8 opcode[0x10]; 8193 u8 uid[0x10]; 8194 8195 u8 reserved_at_20[0x10]; 8196 u8 op_mod[0x10]; 8197 8198 u8 reserved_at_40[0x8]; 8199 u8 mkey_index[0x18]; 8200 8201 u8 reserved_at_60[0x20]; 8202 }; 8203 8204 struct mlx5_ifc_destroy_flow_table_out_bits { 8205 u8 status[0x8]; 8206 u8 reserved_at_8[0x18]; 8207 8208 u8 syndrome[0x20]; 8209 8210 u8 reserved_at_40[0x40]; 8211 }; 8212 8213 struct mlx5_ifc_destroy_flow_table_in_bits { 8214 u8 opcode[0x10]; 8215 u8 reserved_at_10[0x10]; 8216 8217 u8 reserved_at_20[0x10]; 8218 u8 op_mod[0x10]; 8219 8220 u8 other_vport[0x1]; 8221 u8 reserved_at_41[0xf]; 8222 u8 vport_number[0x10]; 8223 8224 u8 reserved_at_60[0x20]; 8225 8226 u8 table_type[0x8]; 8227 u8 reserved_at_88[0x18]; 8228 8229 u8 reserved_at_a0[0x8]; 8230 u8 table_id[0x18]; 8231 8232 u8 reserved_at_c0[0x140]; 8233 }; 8234 8235 struct mlx5_ifc_destroy_flow_group_out_bits { 8236 u8 status[0x8]; 8237 u8 reserved_at_8[0x18]; 8238 8239 u8 syndrome[0x20]; 8240 8241 u8 reserved_at_40[0x40]; 8242 }; 8243 8244 struct mlx5_ifc_destroy_flow_group_in_bits { 8245 u8 opcode[0x10]; 8246 u8 reserved_at_10[0x10]; 8247 8248 u8 reserved_at_20[0x10]; 8249 u8 op_mod[0x10]; 8250 8251 u8 other_vport[0x1]; 8252 u8 reserved_at_41[0xf]; 8253 u8 vport_number[0x10]; 8254 8255 u8 reserved_at_60[0x20]; 8256 8257 u8 table_type[0x8]; 8258 u8 reserved_at_88[0x18]; 8259 8260 u8 reserved_at_a0[0x8]; 8261 u8 table_id[0x18]; 8262 8263 u8 group_id[0x20]; 8264 8265 u8 reserved_at_e0[0x120]; 8266 }; 8267 8268 struct mlx5_ifc_destroy_eq_out_bits { 8269 u8 status[0x8]; 8270 u8 reserved_at_8[0x18]; 8271 8272 u8 syndrome[0x20]; 8273 8274 u8 reserved_at_40[0x40]; 8275 }; 8276 8277 struct mlx5_ifc_destroy_eq_in_bits { 8278 u8 opcode[0x10]; 8279 u8 reserved_at_10[0x10]; 8280 8281 u8 reserved_at_20[0x10]; 8282 u8 op_mod[0x10]; 8283 8284 u8 reserved_at_40[0x18]; 8285 u8 eq_number[0x8]; 8286 8287 u8 reserved_at_60[0x20]; 8288 }; 8289 8290 struct mlx5_ifc_destroy_dct_out_bits { 8291 u8 status[0x8]; 8292 u8 reserved_at_8[0x18]; 8293 8294 u8 syndrome[0x20]; 8295 8296 u8 reserved_at_40[0x40]; 8297 }; 8298 8299 struct mlx5_ifc_destroy_dct_in_bits { 8300 u8 opcode[0x10]; 8301 u8 uid[0x10]; 8302 8303 u8 reserved_at_20[0x10]; 8304 u8 op_mod[0x10]; 8305 8306 u8 reserved_at_40[0x8]; 8307 u8 dctn[0x18]; 8308 8309 u8 reserved_at_60[0x20]; 8310 }; 8311 8312 struct mlx5_ifc_destroy_cq_out_bits { 8313 u8 status[0x8]; 8314 u8 reserved_at_8[0x18]; 8315 8316 u8 syndrome[0x20]; 8317 8318 u8 reserved_at_40[0x40]; 8319 }; 8320 8321 struct mlx5_ifc_destroy_cq_in_bits { 8322 u8 opcode[0x10]; 8323 u8 uid[0x10]; 8324 8325 u8 reserved_at_20[0x10]; 8326 u8 op_mod[0x10]; 8327 8328 u8 reserved_at_40[0x8]; 8329 u8 cqn[0x18]; 8330 8331 u8 reserved_at_60[0x20]; 8332 }; 8333 8334 struct mlx5_ifc_delete_vxlan_udp_dport_out_bits { 8335 u8 status[0x8]; 8336 u8 reserved_at_8[0x18]; 8337 8338 u8 syndrome[0x20]; 8339 8340 u8 reserved_at_40[0x40]; 8341 }; 8342 8343 struct mlx5_ifc_delete_vxlan_udp_dport_in_bits { 8344 u8 opcode[0x10]; 8345 u8 reserved_at_10[0x10]; 8346 8347 u8 reserved_at_20[0x10]; 8348 u8 op_mod[0x10]; 8349 8350 u8 reserved_at_40[0x20]; 8351 8352 u8 reserved_at_60[0x10]; 8353 u8 vxlan_udp_port[0x10]; 8354 }; 8355 8356 struct mlx5_ifc_delete_l2_table_entry_out_bits { 8357 u8 status[0x8]; 8358 u8 reserved_at_8[0x18]; 8359 8360 u8 syndrome[0x20]; 8361 8362 u8 reserved_at_40[0x40]; 8363 }; 8364 8365 struct mlx5_ifc_delete_l2_table_entry_in_bits { 8366 u8 opcode[0x10]; 8367 u8 reserved_at_10[0x10]; 8368 8369 u8 reserved_at_20[0x10]; 8370 u8 op_mod[0x10]; 8371 8372 u8 reserved_at_40[0x60]; 8373 8374 u8 reserved_at_a0[0x8]; 8375 u8 table_index[0x18]; 8376 8377 u8 reserved_at_c0[0x140]; 8378 }; 8379 8380 struct mlx5_ifc_delete_fte_out_bits { 8381 u8 status[0x8]; 8382 u8 reserved_at_8[0x18]; 8383 8384 u8 syndrome[0x20]; 8385 8386 u8 reserved_at_40[0x40]; 8387 }; 8388 8389 struct mlx5_ifc_delete_fte_in_bits { 8390 u8 opcode[0x10]; 8391 u8 reserved_at_10[0x10]; 8392 8393 u8 reserved_at_20[0x10]; 8394 u8 op_mod[0x10]; 8395 8396 u8 other_vport[0x1]; 8397 u8 reserved_at_41[0xf]; 8398 u8 vport_number[0x10]; 8399 8400 u8 reserved_at_60[0x20]; 8401 8402 u8 table_type[0x8]; 8403 u8 reserved_at_88[0x18]; 8404 8405 u8 reserved_at_a0[0x8]; 8406 u8 table_id[0x18]; 8407 8408 u8 reserved_at_c0[0x40]; 8409 8410 u8 flow_index[0x20]; 8411 8412 u8 reserved_at_120[0xe0]; 8413 }; 8414 8415 struct mlx5_ifc_dealloc_xrcd_out_bits { 8416 u8 status[0x8]; 8417 u8 reserved_at_8[0x18]; 8418 8419 u8 syndrome[0x20]; 8420 8421 u8 reserved_at_40[0x40]; 8422 }; 8423 8424 struct mlx5_ifc_dealloc_xrcd_in_bits { 8425 u8 opcode[0x10]; 8426 u8 uid[0x10]; 8427 8428 u8 reserved_at_20[0x10]; 8429 u8 op_mod[0x10]; 8430 8431 u8 reserved_at_40[0x8]; 8432 u8 xrcd[0x18]; 8433 8434 u8 reserved_at_60[0x20]; 8435 }; 8436 8437 struct mlx5_ifc_dealloc_uar_out_bits { 8438 u8 status[0x8]; 8439 u8 reserved_at_8[0x18]; 8440 8441 u8 syndrome[0x20]; 8442 8443 u8 reserved_at_40[0x40]; 8444 }; 8445 8446 struct mlx5_ifc_dealloc_uar_in_bits { 8447 u8 opcode[0x10]; 8448 u8 uid[0x10]; 8449 8450 u8 reserved_at_20[0x10]; 8451 u8 op_mod[0x10]; 8452 8453 u8 reserved_at_40[0x8]; 8454 u8 uar[0x18]; 8455 8456 u8 reserved_at_60[0x20]; 8457 }; 8458 8459 struct mlx5_ifc_dealloc_transport_domain_out_bits { 8460 u8 status[0x8]; 8461 u8 reserved_at_8[0x18]; 8462 8463 u8 syndrome[0x20]; 8464 8465 u8 reserved_at_40[0x40]; 8466 }; 8467 8468 struct mlx5_ifc_dealloc_transport_domain_in_bits { 8469 u8 opcode[0x10]; 8470 u8 uid[0x10]; 8471 8472 u8 reserved_at_20[0x10]; 8473 u8 op_mod[0x10]; 8474 8475 u8 reserved_at_40[0x8]; 8476 u8 transport_domain[0x18]; 8477 8478 u8 reserved_at_60[0x20]; 8479 }; 8480 8481 struct mlx5_ifc_dealloc_q_counter_out_bits { 8482 u8 status[0x8]; 8483 u8 reserved_at_8[0x18]; 8484 8485 u8 syndrome[0x20]; 8486 8487 u8 reserved_at_40[0x40]; 8488 }; 8489 8490 struct mlx5_ifc_dealloc_q_counter_in_bits { 8491 u8 opcode[0x10]; 8492 u8 reserved_at_10[0x10]; 8493 8494 u8 reserved_at_20[0x10]; 8495 u8 op_mod[0x10]; 8496 8497 u8 reserved_at_40[0x18]; 8498 u8 counter_set_id[0x8]; 8499 8500 u8 reserved_at_60[0x20]; 8501 }; 8502 8503 struct mlx5_ifc_dealloc_pd_out_bits { 8504 u8 status[0x8]; 8505 u8 reserved_at_8[0x18]; 8506 8507 u8 syndrome[0x20]; 8508 8509 u8 reserved_at_40[0x40]; 8510 }; 8511 8512 struct mlx5_ifc_dealloc_pd_in_bits { 8513 u8 opcode[0x10]; 8514 u8 uid[0x10]; 8515 8516 u8 reserved_at_20[0x10]; 8517 u8 op_mod[0x10]; 8518 8519 u8 reserved_at_40[0x8]; 8520 u8 pd[0x18]; 8521 8522 u8 reserved_at_60[0x20]; 8523 }; 8524 8525 struct mlx5_ifc_dealloc_flow_counter_out_bits { 8526 u8 status[0x8]; 8527 u8 reserved_at_8[0x18]; 8528 8529 u8 syndrome[0x20]; 8530 8531 u8 reserved_at_40[0x40]; 8532 }; 8533 8534 struct mlx5_ifc_dealloc_flow_counter_in_bits { 8535 u8 opcode[0x10]; 8536 u8 reserved_at_10[0x10]; 8537 8538 u8 reserved_at_20[0x10]; 8539 u8 op_mod[0x10]; 8540 8541 u8 flow_counter_id[0x20]; 8542 8543 u8 reserved_at_60[0x20]; 8544 }; 8545 8546 struct mlx5_ifc_create_xrq_out_bits { 8547 u8 status[0x8]; 8548 u8 reserved_at_8[0x18]; 8549 8550 u8 syndrome[0x20]; 8551 8552 u8 reserved_at_40[0x8]; 8553 u8 xrqn[0x18]; 8554 8555 u8 reserved_at_60[0x20]; 8556 }; 8557 8558 struct mlx5_ifc_create_xrq_in_bits { 8559 u8 opcode[0x10]; 8560 u8 uid[0x10]; 8561 8562 u8 reserved_at_20[0x10]; 8563 u8 op_mod[0x10]; 8564 8565 u8 reserved_at_40[0x40]; 8566 8567 struct mlx5_ifc_xrqc_bits xrq_context; 8568 }; 8569 8570 struct mlx5_ifc_create_xrc_srq_out_bits { 8571 u8 status[0x8]; 8572 u8 reserved_at_8[0x18]; 8573 8574 u8 syndrome[0x20]; 8575 8576 u8 reserved_at_40[0x8]; 8577 u8 xrc_srqn[0x18]; 8578 8579 u8 reserved_at_60[0x20]; 8580 }; 8581 8582 struct mlx5_ifc_create_xrc_srq_in_bits { 8583 u8 opcode[0x10]; 8584 u8 uid[0x10]; 8585 8586 u8 reserved_at_20[0x10]; 8587 u8 op_mod[0x10]; 8588 8589 u8 reserved_at_40[0x40]; 8590 8591 struct mlx5_ifc_xrc_srqc_bits xrc_srq_context_entry; 8592 8593 u8 reserved_at_280[0x60]; 8594 8595 u8 xrc_srq_umem_valid[0x1]; 8596 u8 reserved_at_2e1[0x1f]; 8597 8598 u8 reserved_at_300[0x580]; 8599 8600 u8 pas[][0x40]; 8601 }; 8602 8603 struct mlx5_ifc_create_tis_out_bits { 8604 u8 status[0x8]; 8605 u8 reserved_at_8[0x18]; 8606 8607 u8 syndrome[0x20]; 8608 8609 u8 reserved_at_40[0x8]; 8610 u8 tisn[0x18]; 8611 8612 u8 reserved_at_60[0x20]; 8613 }; 8614 8615 struct mlx5_ifc_create_tis_in_bits { 8616 u8 opcode[0x10]; 8617 u8 uid[0x10]; 8618 8619 u8 reserved_at_20[0x10]; 8620 u8 op_mod[0x10]; 8621 8622 u8 reserved_at_40[0xc0]; 8623 8624 struct mlx5_ifc_tisc_bits ctx; 8625 }; 8626 8627 struct mlx5_ifc_create_tir_out_bits { 8628 u8 status[0x8]; 8629 u8 icm_address_63_40[0x18]; 8630 8631 u8 syndrome[0x20]; 8632 8633 u8 icm_address_39_32[0x8]; 8634 u8 tirn[0x18]; 8635 8636 u8 icm_address_31_0[0x20]; 8637 }; 8638 8639 struct mlx5_ifc_create_tir_in_bits { 8640 u8 opcode[0x10]; 8641 u8 uid[0x10]; 8642 8643 u8 reserved_at_20[0x10]; 8644 u8 op_mod[0x10]; 8645 8646 u8 reserved_at_40[0xc0]; 8647 8648 struct mlx5_ifc_tirc_bits ctx; 8649 }; 8650 8651 struct mlx5_ifc_create_srq_out_bits { 8652 u8 status[0x8]; 8653 u8 reserved_at_8[0x18]; 8654 8655 u8 syndrome[0x20]; 8656 8657 u8 reserved_at_40[0x8]; 8658 u8 srqn[0x18]; 8659 8660 u8 reserved_at_60[0x20]; 8661 }; 8662 8663 struct mlx5_ifc_create_srq_in_bits { 8664 u8 opcode[0x10]; 8665 u8 uid[0x10]; 8666 8667 u8 reserved_at_20[0x10]; 8668 u8 op_mod[0x10]; 8669 8670 u8 reserved_at_40[0x40]; 8671 8672 struct mlx5_ifc_srqc_bits srq_context_entry; 8673 8674 u8 reserved_at_280[0x600]; 8675 8676 u8 pas[][0x40]; 8677 }; 8678 8679 struct mlx5_ifc_create_sq_out_bits { 8680 u8 status[0x8]; 8681 u8 reserved_at_8[0x18]; 8682 8683 u8 syndrome[0x20]; 8684 8685 u8 reserved_at_40[0x8]; 8686 u8 sqn[0x18]; 8687 8688 u8 reserved_at_60[0x20]; 8689 }; 8690 8691 struct mlx5_ifc_create_sq_in_bits { 8692 u8 opcode[0x10]; 8693 u8 uid[0x10]; 8694 8695 u8 reserved_at_20[0x10]; 8696 u8 op_mod[0x10]; 8697 8698 u8 reserved_at_40[0xc0]; 8699 8700 struct mlx5_ifc_sqc_bits ctx; 8701 }; 8702 8703 struct mlx5_ifc_create_scheduling_element_out_bits { 8704 u8 status[0x8]; 8705 u8 reserved_at_8[0x18]; 8706 8707 u8 syndrome[0x20]; 8708 8709 u8 reserved_at_40[0x40]; 8710 8711 u8 scheduling_element_id[0x20]; 8712 8713 u8 reserved_at_a0[0x160]; 8714 }; 8715 8716 struct mlx5_ifc_create_scheduling_element_in_bits { 8717 u8 opcode[0x10]; 8718 u8 reserved_at_10[0x10]; 8719 8720 u8 reserved_at_20[0x10]; 8721 u8 op_mod[0x10]; 8722 8723 u8 scheduling_hierarchy[0x8]; 8724 u8 reserved_at_48[0x18]; 8725 8726 u8 reserved_at_60[0xa0]; 8727 8728 struct mlx5_ifc_scheduling_context_bits scheduling_context; 8729 8730 u8 reserved_at_300[0x100]; 8731 }; 8732 8733 struct mlx5_ifc_create_rqt_out_bits { 8734 u8 status[0x8]; 8735 u8 reserved_at_8[0x18]; 8736 8737 u8 syndrome[0x20]; 8738 8739 u8 reserved_at_40[0x8]; 8740 u8 rqtn[0x18]; 8741 8742 u8 reserved_at_60[0x20]; 8743 }; 8744 8745 struct mlx5_ifc_create_rqt_in_bits { 8746 u8 opcode[0x10]; 8747 u8 uid[0x10]; 8748 8749 u8 reserved_at_20[0x10]; 8750 u8 op_mod[0x10]; 8751 8752 u8 reserved_at_40[0xc0]; 8753 8754 struct mlx5_ifc_rqtc_bits rqt_context; 8755 }; 8756 8757 struct mlx5_ifc_create_rq_out_bits { 8758 u8 status[0x8]; 8759 u8 reserved_at_8[0x18]; 8760 8761 u8 syndrome[0x20]; 8762 8763 u8 reserved_at_40[0x8]; 8764 u8 rqn[0x18]; 8765 8766 u8 reserved_at_60[0x20]; 8767 }; 8768 8769 struct mlx5_ifc_create_rq_in_bits { 8770 u8 opcode[0x10]; 8771 u8 uid[0x10]; 8772 8773 u8 reserved_at_20[0x10]; 8774 u8 op_mod[0x10]; 8775 8776 u8 reserved_at_40[0xc0]; 8777 8778 struct mlx5_ifc_rqc_bits ctx; 8779 }; 8780 8781 struct mlx5_ifc_create_rmp_out_bits { 8782 u8 status[0x8]; 8783 u8 reserved_at_8[0x18]; 8784 8785 u8 syndrome[0x20]; 8786 8787 u8 reserved_at_40[0x8]; 8788 u8 rmpn[0x18]; 8789 8790 u8 reserved_at_60[0x20]; 8791 }; 8792 8793 struct mlx5_ifc_create_rmp_in_bits { 8794 u8 opcode[0x10]; 8795 u8 uid[0x10]; 8796 8797 u8 reserved_at_20[0x10]; 8798 u8 op_mod[0x10]; 8799 8800 u8 reserved_at_40[0xc0]; 8801 8802 struct mlx5_ifc_rmpc_bits ctx; 8803 }; 8804 8805 struct mlx5_ifc_create_qp_out_bits { 8806 u8 status[0x8]; 8807 u8 reserved_at_8[0x18]; 8808 8809 u8 syndrome[0x20]; 8810 8811 u8 reserved_at_40[0x8]; 8812 u8 qpn[0x18]; 8813 8814 u8 ece[0x20]; 8815 }; 8816 8817 struct mlx5_ifc_create_qp_in_bits { 8818 u8 opcode[0x10]; 8819 u8 uid[0x10]; 8820 8821 u8 reserved_at_20[0x10]; 8822 u8 op_mod[0x10]; 8823 8824 u8 qpc_ext[0x1]; 8825 u8 reserved_at_41[0x7]; 8826 u8 input_qpn[0x18]; 8827 8828 u8 reserved_at_60[0x20]; 8829 u8 opt_param_mask[0x20]; 8830 8831 u8 ece[0x20]; 8832 8833 struct mlx5_ifc_qpc_bits qpc; 8834 8835 u8 reserved_at_800[0x60]; 8836 8837 u8 wq_umem_valid[0x1]; 8838 u8 reserved_at_861[0x1f]; 8839 8840 u8 pas[][0x40]; 8841 }; 8842 8843 struct mlx5_ifc_create_psv_out_bits { 8844 u8 status[0x8]; 8845 u8 reserved_at_8[0x18]; 8846 8847 u8 syndrome[0x20]; 8848 8849 u8 reserved_at_40[0x40]; 8850 8851 u8 reserved_at_80[0x8]; 8852 u8 psv0_index[0x18]; 8853 8854 u8 reserved_at_a0[0x8]; 8855 u8 psv1_index[0x18]; 8856 8857 u8 reserved_at_c0[0x8]; 8858 u8 psv2_index[0x18]; 8859 8860 u8 reserved_at_e0[0x8]; 8861 u8 psv3_index[0x18]; 8862 }; 8863 8864 struct mlx5_ifc_create_psv_in_bits { 8865 u8 opcode[0x10]; 8866 u8 reserved_at_10[0x10]; 8867 8868 u8 reserved_at_20[0x10]; 8869 u8 op_mod[0x10]; 8870 8871 u8 num_psv[0x4]; 8872 u8 reserved_at_44[0x4]; 8873 u8 pd[0x18]; 8874 8875 u8 reserved_at_60[0x20]; 8876 }; 8877 8878 struct mlx5_ifc_create_mkey_out_bits { 8879 u8 status[0x8]; 8880 u8 reserved_at_8[0x18]; 8881 8882 u8 syndrome[0x20]; 8883 8884 u8 reserved_at_40[0x8]; 8885 u8 mkey_index[0x18]; 8886 8887 u8 reserved_at_60[0x20]; 8888 }; 8889 8890 struct mlx5_ifc_create_mkey_in_bits { 8891 u8 opcode[0x10]; 8892 u8 uid[0x10]; 8893 8894 u8 reserved_at_20[0x10]; 8895 u8 op_mod[0x10]; 8896 8897 u8 reserved_at_40[0x20]; 8898 8899 u8 pg_access[0x1]; 8900 u8 mkey_umem_valid[0x1]; 8901 u8 reserved_at_62[0x1e]; 8902 8903 struct mlx5_ifc_mkc_bits memory_key_mkey_entry; 8904 8905 u8 reserved_at_280[0x80]; 8906 8907 u8 translations_octword_actual_size[0x20]; 8908 8909 u8 reserved_at_320[0x560]; 8910 8911 u8 klm_pas_mtt[][0x20]; 8912 }; 8913 8914 enum { 8915 MLX5_FLOW_TABLE_TYPE_NIC_RX = 0x0, 8916 MLX5_FLOW_TABLE_TYPE_NIC_TX = 0x1, 8917 MLX5_FLOW_TABLE_TYPE_ESW_EGRESS_ACL = 0x2, 8918 MLX5_FLOW_TABLE_TYPE_ESW_INGRESS_ACL = 0x3, 8919 MLX5_FLOW_TABLE_TYPE_FDB = 0X4, 8920 MLX5_FLOW_TABLE_TYPE_SNIFFER_RX = 0X5, 8921 MLX5_FLOW_TABLE_TYPE_SNIFFER_TX = 0X6, 8922 }; 8923 8924 struct mlx5_ifc_create_flow_table_out_bits { 8925 u8 status[0x8]; 8926 u8 icm_address_63_40[0x18]; 8927 8928 u8 syndrome[0x20]; 8929 8930 u8 icm_address_39_32[0x8]; 8931 u8 table_id[0x18]; 8932 8933 u8 icm_address_31_0[0x20]; 8934 }; 8935 8936 struct mlx5_ifc_create_flow_table_in_bits { 8937 u8 opcode[0x10]; 8938 u8 uid[0x10]; 8939 8940 u8 reserved_at_20[0x10]; 8941 u8 op_mod[0x10]; 8942 8943 u8 other_vport[0x1]; 8944 u8 reserved_at_41[0xf]; 8945 u8 vport_number[0x10]; 8946 8947 u8 reserved_at_60[0x20]; 8948 8949 u8 table_type[0x8]; 8950 u8 reserved_at_88[0x18]; 8951 8952 u8 reserved_at_a0[0x20]; 8953 8954 struct mlx5_ifc_flow_table_context_bits flow_table_context; 8955 }; 8956 8957 struct mlx5_ifc_create_flow_group_out_bits { 8958 u8 status[0x8]; 8959 u8 reserved_at_8[0x18]; 8960 8961 u8 syndrome[0x20]; 8962 8963 u8 reserved_at_40[0x8]; 8964 u8 group_id[0x18]; 8965 8966 u8 reserved_at_60[0x20]; 8967 }; 8968 8969 enum { 8970 MLX5_CREATE_FLOW_GROUP_IN_GROUP_TYPE_TCAM_SUBTABLE = 0x0, 8971 MLX5_CREATE_FLOW_GROUP_IN_GROUP_TYPE_HASH_SPLIT = 0x1, 8972 }; 8973 8974 enum { 8975 MLX5_CREATE_FLOW_GROUP_IN_MATCH_CRITERIA_ENABLE_OUTER_HEADERS = 0x0, 8976 MLX5_CREATE_FLOW_GROUP_IN_MATCH_CRITERIA_ENABLE_MISC_PARAMETERS = 0x1, 8977 MLX5_CREATE_FLOW_GROUP_IN_MATCH_CRITERIA_ENABLE_INNER_HEADERS = 0x2, 8978 MLX5_CREATE_FLOW_GROUP_IN_MATCH_CRITERIA_ENABLE_MISC_PARAMETERS_2 = 0x3, 8979 }; 8980 8981 struct mlx5_ifc_create_flow_group_in_bits { 8982 u8 opcode[0x10]; 8983 u8 reserved_at_10[0x10]; 8984 8985 u8 reserved_at_20[0x10]; 8986 u8 op_mod[0x10]; 8987 8988 u8 other_vport[0x1]; 8989 u8 reserved_at_41[0xf]; 8990 u8 vport_number[0x10]; 8991 8992 u8 reserved_at_60[0x20]; 8993 8994 u8 table_type[0x8]; 8995 u8 reserved_at_88[0x4]; 8996 u8 group_type[0x4]; 8997 u8 reserved_at_90[0x10]; 8998 8999 u8 reserved_at_a0[0x8]; 9000 u8 table_id[0x18]; 9001 9002 u8 source_eswitch_owner_vhca_id_valid[0x1]; 9003 9004 u8 reserved_at_c1[0x1f]; 9005 9006 u8 start_flow_index[0x20]; 9007 9008 u8 reserved_at_100[0x20]; 9009 9010 u8 end_flow_index[0x20]; 9011 9012 u8 reserved_at_140[0x10]; 9013 u8 match_definer_id[0x10]; 9014 9015 u8 reserved_at_160[0x80]; 9016 9017 u8 reserved_at_1e0[0x18]; 9018 u8 match_criteria_enable[0x8]; 9019 9020 struct mlx5_ifc_fte_match_param_bits match_criteria; 9021 9022 u8 reserved_at_1200[0xe00]; 9023 }; 9024 9025 struct mlx5_ifc_create_eq_out_bits { 9026 u8 status[0x8]; 9027 u8 reserved_at_8[0x18]; 9028 9029 u8 syndrome[0x20]; 9030 9031 u8 reserved_at_40[0x18]; 9032 u8 eq_number[0x8]; 9033 9034 u8 reserved_at_60[0x20]; 9035 }; 9036 9037 struct mlx5_ifc_create_eq_in_bits { 9038 u8 opcode[0x10]; 9039 u8 uid[0x10]; 9040 9041 u8 reserved_at_20[0x10]; 9042 u8 op_mod[0x10]; 9043 9044 u8 reserved_at_40[0x40]; 9045 9046 struct mlx5_ifc_eqc_bits eq_context_entry; 9047 9048 u8 reserved_at_280[0x40]; 9049 9050 u8 event_bitmask[4][0x40]; 9051 9052 u8 reserved_at_3c0[0x4c0]; 9053 9054 u8 pas[][0x40]; 9055 }; 9056 9057 struct mlx5_ifc_create_dct_out_bits { 9058 u8 status[0x8]; 9059 u8 reserved_at_8[0x18]; 9060 9061 u8 syndrome[0x20]; 9062 9063 u8 reserved_at_40[0x8]; 9064 u8 dctn[0x18]; 9065 9066 u8 ece[0x20]; 9067 }; 9068 9069 struct mlx5_ifc_create_dct_in_bits { 9070 u8 opcode[0x10]; 9071 u8 uid[0x10]; 9072 9073 u8 reserved_at_20[0x10]; 9074 u8 op_mod[0x10]; 9075 9076 u8 reserved_at_40[0x40]; 9077 9078 struct mlx5_ifc_dctc_bits dct_context_entry; 9079 9080 u8 reserved_at_280[0x180]; 9081 }; 9082 9083 struct mlx5_ifc_create_cq_out_bits { 9084 u8 status[0x8]; 9085 u8 reserved_at_8[0x18]; 9086 9087 u8 syndrome[0x20]; 9088 9089 u8 reserved_at_40[0x8]; 9090 u8 cqn[0x18]; 9091 9092 u8 reserved_at_60[0x20]; 9093 }; 9094 9095 struct mlx5_ifc_create_cq_in_bits { 9096 u8 opcode[0x10]; 9097 u8 uid[0x10]; 9098 9099 u8 reserved_at_20[0x10]; 9100 u8 op_mod[0x10]; 9101 9102 u8 reserved_at_40[0x40]; 9103 9104 struct mlx5_ifc_cqc_bits cq_context; 9105 9106 u8 reserved_at_280[0x60]; 9107 9108 u8 cq_umem_valid[0x1]; 9109 u8 reserved_at_2e1[0x59f]; 9110 9111 u8 pas[][0x40]; 9112 }; 9113 9114 struct mlx5_ifc_config_int_moderation_out_bits { 9115 u8 status[0x8]; 9116 u8 reserved_at_8[0x18]; 9117 9118 u8 syndrome[0x20]; 9119 9120 u8 reserved_at_40[0x4]; 9121 u8 min_delay[0xc]; 9122 u8 int_vector[0x10]; 9123 9124 u8 reserved_at_60[0x20]; 9125 }; 9126 9127 enum { 9128 MLX5_CONFIG_INT_MODERATION_IN_OP_MOD_WRITE = 0x0, 9129 MLX5_CONFIG_INT_MODERATION_IN_OP_MOD_READ = 0x1, 9130 }; 9131 9132 struct mlx5_ifc_config_int_moderation_in_bits { 9133 u8 opcode[0x10]; 9134 u8 reserved_at_10[0x10]; 9135 9136 u8 reserved_at_20[0x10]; 9137 u8 op_mod[0x10]; 9138 9139 u8 reserved_at_40[0x4]; 9140 u8 min_delay[0xc]; 9141 u8 int_vector[0x10]; 9142 9143 u8 reserved_at_60[0x20]; 9144 }; 9145 9146 struct mlx5_ifc_attach_to_mcg_out_bits { 9147 u8 status[0x8]; 9148 u8 reserved_at_8[0x18]; 9149 9150 u8 syndrome[0x20]; 9151 9152 u8 reserved_at_40[0x40]; 9153 }; 9154 9155 struct mlx5_ifc_attach_to_mcg_in_bits { 9156 u8 opcode[0x10]; 9157 u8 uid[0x10]; 9158 9159 u8 reserved_at_20[0x10]; 9160 u8 op_mod[0x10]; 9161 9162 u8 reserved_at_40[0x8]; 9163 u8 qpn[0x18]; 9164 9165 u8 reserved_at_60[0x20]; 9166 9167 u8 multicast_gid[16][0x8]; 9168 }; 9169 9170 struct mlx5_ifc_arm_xrq_out_bits { 9171 u8 status[0x8]; 9172 u8 reserved_at_8[0x18]; 9173 9174 u8 syndrome[0x20]; 9175 9176 u8 reserved_at_40[0x40]; 9177 }; 9178 9179 struct mlx5_ifc_arm_xrq_in_bits { 9180 u8 opcode[0x10]; 9181 u8 reserved_at_10[0x10]; 9182 9183 u8 reserved_at_20[0x10]; 9184 u8 op_mod[0x10]; 9185 9186 u8 reserved_at_40[0x8]; 9187 u8 xrqn[0x18]; 9188 9189 u8 reserved_at_60[0x10]; 9190 u8 lwm[0x10]; 9191 }; 9192 9193 struct mlx5_ifc_arm_xrc_srq_out_bits { 9194 u8 status[0x8]; 9195 u8 reserved_at_8[0x18]; 9196 9197 u8 syndrome[0x20]; 9198 9199 u8 reserved_at_40[0x40]; 9200 }; 9201 9202 enum { 9203 MLX5_ARM_XRC_SRQ_IN_OP_MOD_XRC_SRQ = 0x1, 9204 }; 9205 9206 struct mlx5_ifc_arm_xrc_srq_in_bits { 9207 u8 opcode[0x10]; 9208 u8 uid[0x10]; 9209 9210 u8 reserved_at_20[0x10]; 9211 u8 op_mod[0x10]; 9212 9213 u8 reserved_at_40[0x8]; 9214 u8 xrc_srqn[0x18]; 9215 9216 u8 reserved_at_60[0x10]; 9217 u8 lwm[0x10]; 9218 }; 9219 9220 struct mlx5_ifc_arm_rq_out_bits { 9221 u8 status[0x8]; 9222 u8 reserved_at_8[0x18]; 9223 9224 u8 syndrome[0x20]; 9225 9226 u8 reserved_at_40[0x40]; 9227 }; 9228 9229 enum { 9230 MLX5_ARM_RQ_IN_OP_MOD_SRQ = 0x1, 9231 MLX5_ARM_RQ_IN_OP_MOD_XRQ = 0x2, 9232 }; 9233 9234 struct mlx5_ifc_arm_rq_in_bits { 9235 u8 opcode[0x10]; 9236 u8 uid[0x10]; 9237 9238 u8 reserved_at_20[0x10]; 9239 u8 op_mod[0x10]; 9240 9241 u8 reserved_at_40[0x8]; 9242 u8 srq_number[0x18]; 9243 9244 u8 reserved_at_60[0x10]; 9245 u8 lwm[0x10]; 9246 }; 9247 9248 struct mlx5_ifc_arm_dct_out_bits { 9249 u8 status[0x8]; 9250 u8 reserved_at_8[0x18]; 9251 9252 u8 syndrome[0x20]; 9253 9254 u8 reserved_at_40[0x40]; 9255 }; 9256 9257 struct mlx5_ifc_arm_dct_in_bits { 9258 u8 opcode[0x10]; 9259 u8 reserved_at_10[0x10]; 9260 9261 u8 reserved_at_20[0x10]; 9262 u8 op_mod[0x10]; 9263 9264 u8 reserved_at_40[0x8]; 9265 u8 dct_number[0x18]; 9266 9267 u8 reserved_at_60[0x20]; 9268 }; 9269 9270 struct mlx5_ifc_alloc_xrcd_out_bits { 9271 u8 status[0x8]; 9272 u8 reserved_at_8[0x18]; 9273 9274 u8 syndrome[0x20]; 9275 9276 u8 reserved_at_40[0x8]; 9277 u8 xrcd[0x18]; 9278 9279 u8 reserved_at_60[0x20]; 9280 }; 9281 9282 struct mlx5_ifc_alloc_xrcd_in_bits { 9283 u8 opcode[0x10]; 9284 u8 uid[0x10]; 9285 9286 u8 reserved_at_20[0x10]; 9287 u8 op_mod[0x10]; 9288 9289 u8 reserved_at_40[0x40]; 9290 }; 9291 9292 struct mlx5_ifc_alloc_uar_out_bits { 9293 u8 status[0x8]; 9294 u8 reserved_at_8[0x18]; 9295 9296 u8 syndrome[0x20]; 9297 9298 u8 reserved_at_40[0x8]; 9299 u8 uar[0x18]; 9300 9301 u8 reserved_at_60[0x20]; 9302 }; 9303 9304 struct mlx5_ifc_alloc_uar_in_bits { 9305 u8 opcode[0x10]; 9306 u8 uid[0x10]; 9307 9308 u8 reserved_at_20[0x10]; 9309 u8 op_mod[0x10]; 9310 9311 u8 reserved_at_40[0x40]; 9312 }; 9313 9314 struct mlx5_ifc_alloc_transport_domain_out_bits { 9315 u8 status[0x8]; 9316 u8 reserved_at_8[0x18]; 9317 9318 u8 syndrome[0x20]; 9319 9320 u8 reserved_at_40[0x8]; 9321 u8 transport_domain[0x18]; 9322 9323 u8 reserved_at_60[0x20]; 9324 }; 9325 9326 struct mlx5_ifc_alloc_transport_domain_in_bits { 9327 u8 opcode[0x10]; 9328 u8 uid[0x10]; 9329 9330 u8 reserved_at_20[0x10]; 9331 u8 op_mod[0x10]; 9332 9333 u8 reserved_at_40[0x40]; 9334 }; 9335 9336 struct mlx5_ifc_alloc_q_counter_out_bits { 9337 u8 status[0x8]; 9338 u8 reserved_at_8[0x18]; 9339 9340 u8 syndrome[0x20]; 9341 9342 u8 reserved_at_40[0x18]; 9343 u8 counter_set_id[0x8]; 9344 9345 u8 reserved_at_60[0x20]; 9346 }; 9347 9348 struct mlx5_ifc_alloc_q_counter_in_bits { 9349 u8 opcode[0x10]; 9350 u8 uid[0x10]; 9351 9352 u8 reserved_at_20[0x10]; 9353 u8 op_mod[0x10]; 9354 9355 u8 reserved_at_40[0x40]; 9356 }; 9357 9358 struct mlx5_ifc_alloc_pd_out_bits { 9359 u8 status[0x8]; 9360 u8 reserved_at_8[0x18]; 9361 9362 u8 syndrome[0x20]; 9363 9364 u8 reserved_at_40[0x8]; 9365 u8 pd[0x18]; 9366 9367 u8 reserved_at_60[0x20]; 9368 }; 9369 9370 struct mlx5_ifc_alloc_pd_in_bits { 9371 u8 opcode[0x10]; 9372 u8 uid[0x10]; 9373 9374 u8 reserved_at_20[0x10]; 9375 u8 op_mod[0x10]; 9376 9377 u8 reserved_at_40[0x40]; 9378 }; 9379 9380 struct mlx5_ifc_alloc_flow_counter_out_bits { 9381 u8 status[0x8]; 9382 u8 reserved_at_8[0x18]; 9383 9384 u8 syndrome[0x20]; 9385 9386 u8 flow_counter_id[0x20]; 9387 9388 u8 reserved_at_60[0x20]; 9389 }; 9390 9391 struct mlx5_ifc_alloc_flow_counter_in_bits { 9392 u8 opcode[0x10]; 9393 u8 reserved_at_10[0x10]; 9394 9395 u8 reserved_at_20[0x10]; 9396 u8 op_mod[0x10]; 9397 9398 u8 reserved_at_40[0x33]; 9399 u8 flow_counter_bulk_log_size[0x5]; 9400 u8 flow_counter_bulk[0x8]; 9401 }; 9402 9403 struct mlx5_ifc_add_vxlan_udp_dport_out_bits { 9404 u8 status[0x8]; 9405 u8 reserved_at_8[0x18]; 9406 9407 u8 syndrome[0x20]; 9408 9409 u8 reserved_at_40[0x40]; 9410 }; 9411 9412 struct mlx5_ifc_add_vxlan_udp_dport_in_bits { 9413 u8 opcode[0x10]; 9414 u8 reserved_at_10[0x10]; 9415 9416 u8 reserved_at_20[0x10]; 9417 u8 op_mod[0x10]; 9418 9419 u8 reserved_at_40[0x20]; 9420 9421 u8 reserved_at_60[0x10]; 9422 u8 vxlan_udp_port[0x10]; 9423 }; 9424 9425 struct mlx5_ifc_set_pp_rate_limit_out_bits { 9426 u8 status[0x8]; 9427 u8 reserved_at_8[0x18]; 9428 9429 u8 syndrome[0x20]; 9430 9431 u8 reserved_at_40[0x40]; 9432 }; 9433 9434 struct mlx5_ifc_set_pp_rate_limit_context_bits { 9435 u8 rate_limit[0x20]; 9436 9437 u8 burst_upper_bound[0x20]; 9438 9439 u8 reserved_at_40[0x10]; 9440 u8 typical_packet_size[0x10]; 9441 9442 u8 reserved_at_60[0x120]; 9443 }; 9444 9445 struct mlx5_ifc_set_pp_rate_limit_in_bits { 9446 u8 opcode[0x10]; 9447 u8 uid[0x10]; 9448 9449 u8 reserved_at_20[0x10]; 9450 u8 op_mod[0x10]; 9451 9452 u8 reserved_at_40[0x10]; 9453 u8 rate_limit_index[0x10]; 9454 9455 u8 reserved_at_60[0x20]; 9456 9457 struct mlx5_ifc_set_pp_rate_limit_context_bits ctx; 9458 }; 9459 9460 struct mlx5_ifc_access_register_out_bits { 9461 u8 status[0x8]; 9462 u8 reserved_at_8[0x18]; 9463 9464 u8 syndrome[0x20]; 9465 9466 u8 reserved_at_40[0x40]; 9467 9468 u8 register_data[][0x20]; 9469 }; 9470 9471 enum { 9472 MLX5_ACCESS_REGISTER_IN_OP_MOD_WRITE = 0x0, 9473 MLX5_ACCESS_REGISTER_IN_OP_MOD_READ = 0x1, 9474 }; 9475 9476 struct mlx5_ifc_access_register_in_bits { 9477 u8 opcode[0x10]; 9478 u8 reserved_at_10[0x10]; 9479 9480 u8 reserved_at_20[0x10]; 9481 u8 op_mod[0x10]; 9482 9483 u8 reserved_at_40[0x10]; 9484 u8 register_id[0x10]; 9485 9486 u8 argument[0x20]; 9487 9488 u8 register_data[][0x20]; 9489 }; 9490 9491 struct mlx5_ifc_sltp_reg_bits { 9492 u8 status[0x4]; 9493 u8 version[0x4]; 9494 u8 local_port[0x8]; 9495 u8 pnat[0x2]; 9496 u8 reserved_at_12[0x2]; 9497 u8 lane[0x4]; 9498 u8 reserved_at_18[0x8]; 9499 9500 u8 reserved_at_20[0x20]; 9501 9502 u8 reserved_at_40[0x7]; 9503 u8 polarity[0x1]; 9504 u8 ob_tap0[0x8]; 9505 u8 ob_tap1[0x8]; 9506 u8 ob_tap2[0x8]; 9507 9508 u8 reserved_at_60[0xc]; 9509 u8 ob_preemp_mode[0x4]; 9510 u8 ob_reg[0x8]; 9511 u8 ob_bias[0x8]; 9512 9513 u8 reserved_at_80[0x20]; 9514 }; 9515 9516 struct mlx5_ifc_slrg_reg_bits { 9517 u8 status[0x4]; 9518 u8 version[0x4]; 9519 u8 local_port[0x8]; 9520 u8 pnat[0x2]; 9521 u8 reserved_at_12[0x2]; 9522 u8 lane[0x4]; 9523 u8 reserved_at_18[0x8]; 9524 9525 u8 time_to_link_up[0x10]; 9526 u8 reserved_at_30[0xc]; 9527 u8 grade_lane_speed[0x4]; 9528 9529 u8 grade_version[0x8]; 9530 u8 grade[0x18]; 9531 9532 u8 reserved_at_60[0x4]; 9533 u8 height_grade_type[0x4]; 9534 u8 height_grade[0x18]; 9535 9536 u8 height_dz[0x10]; 9537 u8 height_dv[0x10]; 9538 9539 u8 reserved_at_a0[0x10]; 9540 u8 height_sigma[0x10]; 9541 9542 u8 reserved_at_c0[0x20]; 9543 9544 u8 reserved_at_e0[0x4]; 9545 u8 phase_grade_type[0x4]; 9546 u8 phase_grade[0x18]; 9547 9548 u8 reserved_at_100[0x8]; 9549 u8 phase_eo_pos[0x8]; 9550 u8 reserved_at_110[0x8]; 9551 u8 phase_eo_neg[0x8]; 9552 9553 u8 ffe_set_tested[0x10]; 9554 u8 test_errors_per_lane[0x10]; 9555 }; 9556 9557 struct mlx5_ifc_pvlc_reg_bits { 9558 u8 reserved_at_0[0x8]; 9559 u8 local_port[0x8]; 9560 u8 reserved_at_10[0x10]; 9561 9562 u8 reserved_at_20[0x1c]; 9563 u8 vl_hw_cap[0x4]; 9564 9565 u8 reserved_at_40[0x1c]; 9566 u8 vl_admin[0x4]; 9567 9568 u8 reserved_at_60[0x1c]; 9569 u8 vl_operational[0x4]; 9570 }; 9571 9572 struct mlx5_ifc_pude_reg_bits { 9573 u8 swid[0x8]; 9574 u8 local_port[0x8]; 9575 u8 reserved_at_10[0x4]; 9576 u8 admin_status[0x4]; 9577 u8 reserved_at_18[0x4]; 9578 u8 oper_status[0x4]; 9579 9580 u8 reserved_at_20[0x60]; 9581 }; 9582 9583 struct mlx5_ifc_ptys_reg_bits { 9584 u8 reserved_at_0[0x1]; 9585 u8 an_disable_admin[0x1]; 9586 u8 an_disable_cap[0x1]; 9587 u8 reserved_at_3[0x5]; 9588 u8 local_port[0x8]; 9589 u8 reserved_at_10[0xd]; 9590 u8 proto_mask[0x3]; 9591 9592 u8 an_status[0x4]; 9593 u8 reserved_at_24[0xc]; 9594 u8 data_rate_oper[0x10]; 9595 9596 u8 ext_eth_proto_capability[0x20]; 9597 9598 u8 eth_proto_capability[0x20]; 9599 9600 u8 ib_link_width_capability[0x10]; 9601 u8 ib_proto_capability[0x10]; 9602 9603 u8 ext_eth_proto_admin[0x20]; 9604 9605 u8 eth_proto_admin[0x20]; 9606 9607 u8 ib_link_width_admin[0x10]; 9608 u8 ib_proto_admin[0x10]; 9609 9610 u8 ext_eth_proto_oper[0x20]; 9611 9612 u8 eth_proto_oper[0x20]; 9613 9614 u8 ib_link_width_oper[0x10]; 9615 u8 ib_proto_oper[0x10]; 9616 9617 u8 reserved_at_160[0x1c]; 9618 u8 connector_type[0x4]; 9619 9620 u8 eth_proto_lp_advertise[0x20]; 9621 9622 u8 reserved_at_1a0[0x60]; 9623 }; 9624 9625 struct mlx5_ifc_mlcr_reg_bits { 9626 u8 reserved_at_0[0x8]; 9627 u8 local_port[0x8]; 9628 u8 reserved_at_10[0x20]; 9629 9630 u8 beacon_duration[0x10]; 9631 u8 reserved_at_40[0x10]; 9632 9633 u8 beacon_remain[0x10]; 9634 }; 9635 9636 struct mlx5_ifc_ptas_reg_bits { 9637 u8 reserved_at_0[0x20]; 9638 9639 u8 algorithm_options[0x10]; 9640 u8 reserved_at_30[0x4]; 9641 u8 repetitions_mode[0x4]; 9642 u8 num_of_repetitions[0x8]; 9643 9644 u8 grade_version[0x8]; 9645 u8 height_grade_type[0x4]; 9646 u8 phase_grade_type[0x4]; 9647 u8 height_grade_weight[0x8]; 9648 u8 phase_grade_weight[0x8]; 9649 9650 u8 gisim_measure_bits[0x10]; 9651 u8 adaptive_tap_measure_bits[0x10]; 9652 9653 u8 ber_bath_high_error_threshold[0x10]; 9654 u8 ber_bath_mid_error_threshold[0x10]; 9655 9656 u8 ber_bath_low_error_threshold[0x10]; 9657 u8 one_ratio_high_threshold[0x10]; 9658 9659 u8 one_ratio_high_mid_threshold[0x10]; 9660 u8 one_ratio_low_mid_threshold[0x10]; 9661 9662 u8 one_ratio_low_threshold[0x10]; 9663 u8 ndeo_error_threshold[0x10]; 9664 9665 u8 mixer_offset_step_size[0x10]; 9666 u8 reserved_at_110[0x8]; 9667 u8 mix90_phase_for_voltage_bath[0x8]; 9668 9669 u8 mixer_offset_start[0x10]; 9670 u8 mixer_offset_end[0x10]; 9671 9672 u8 reserved_at_140[0x15]; 9673 u8 ber_test_time[0xb]; 9674 }; 9675 9676 struct mlx5_ifc_pspa_reg_bits { 9677 u8 swid[0x8]; 9678 u8 local_port[0x8]; 9679 u8 sub_port[0x8]; 9680 u8 reserved_at_18[0x8]; 9681 9682 u8 reserved_at_20[0x20]; 9683 }; 9684 9685 struct mlx5_ifc_pqdr_reg_bits { 9686 u8 reserved_at_0[0x8]; 9687 u8 local_port[0x8]; 9688 u8 reserved_at_10[0x5]; 9689 u8 prio[0x3]; 9690 u8 reserved_at_18[0x6]; 9691 u8 mode[0x2]; 9692 9693 u8 reserved_at_20[0x20]; 9694 9695 u8 reserved_at_40[0x10]; 9696 u8 min_threshold[0x10]; 9697 9698 u8 reserved_at_60[0x10]; 9699 u8 max_threshold[0x10]; 9700 9701 u8 reserved_at_80[0x10]; 9702 u8 mark_probability_denominator[0x10]; 9703 9704 u8 reserved_at_a0[0x60]; 9705 }; 9706 9707 struct mlx5_ifc_ppsc_reg_bits { 9708 u8 reserved_at_0[0x8]; 9709 u8 local_port[0x8]; 9710 u8 reserved_at_10[0x10]; 9711 9712 u8 reserved_at_20[0x60]; 9713 9714 u8 reserved_at_80[0x1c]; 9715 u8 wrps_admin[0x4]; 9716 9717 u8 reserved_at_a0[0x1c]; 9718 u8 wrps_status[0x4]; 9719 9720 u8 reserved_at_c0[0x8]; 9721 u8 up_threshold[0x8]; 9722 u8 reserved_at_d0[0x8]; 9723 u8 down_threshold[0x8]; 9724 9725 u8 reserved_at_e0[0x20]; 9726 9727 u8 reserved_at_100[0x1c]; 9728 u8 srps_admin[0x4]; 9729 9730 u8 reserved_at_120[0x1c]; 9731 u8 srps_status[0x4]; 9732 9733 u8 reserved_at_140[0x40]; 9734 }; 9735 9736 struct mlx5_ifc_pplr_reg_bits { 9737 u8 reserved_at_0[0x8]; 9738 u8 local_port[0x8]; 9739 u8 reserved_at_10[0x10]; 9740 9741 u8 reserved_at_20[0x8]; 9742 u8 lb_cap[0x8]; 9743 u8 reserved_at_30[0x8]; 9744 u8 lb_en[0x8]; 9745 }; 9746 9747 struct mlx5_ifc_pplm_reg_bits { 9748 u8 reserved_at_0[0x8]; 9749 u8 local_port[0x8]; 9750 u8 reserved_at_10[0x10]; 9751 9752 u8 reserved_at_20[0x20]; 9753 9754 u8 port_profile_mode[0x8]; 9755 u8 static_port_profile[0x8]; 9756 u8 active_port_profile[0x8]; 9757 u8 reserved_at_58[0x8]; 9758 9759 u8 retransmission_active[0x8]; 9760 u8 fec_mode_active[0x18]; 9761 9762 u8 rs_fec_correction_bypass_cap[0x4]; 9763 u8 reserved_at_84[0x8]; 9764 u8 fec_override_cap_56g[0x4]; 9765 u8 fec_override_cap_100g[0x4]; 9766 u8 fec_override_cap_50g[0x4]; 9767 u8 fec_override_cap_25g[0x4]; 9768 u8 fec_override_cap_10g_40g[0x4]; 9769 9770 u8 rs_fec_correction_bypass_admin[0x4]; 9771 u8 reserved_at_a4[0x8]; 9772 u8 fec_override_admin_56g[0x4]; 9773 u8 fec_override_admin_100g[0x4]; 9774 u8 fec_override_admin_50g[0x4]; 9775 u8 fec_override_admin_25g[0x4]; 9776 u8 fec_override_admin_10g_40g[0x4]; 9777 9778 u8 fec_override_cap_400g_8x[0x10]; 9779 u8 fec_override_cap_200g_4x[0x10]; 9780 9781 u8 fec_override_cap_100g_2x[0x10]; 9782 u8 fec_override_cap_50g_1x[0x10]; 9783 9784 u8 fec_override_admin_400g_8x[0x10]; 9785 u8 fec_override_admin_200g_4x[0x10]; 9786 9787 u8 fec_override_admin_100g_2x[0x10]; 9788 u8 fec_override_admin_50g_1x[0x10]; 9789 9790 u8 reserved_at_140[0x140]; 9791 }; 9792 9793 struct mlx5_ifc_ppcnt_reg_bits { 9794 u8 swid[0x8]; 9795 u8 local_port[0x8]; 9796 u8 pnat[0x2]; 9797 u8 reserved_at_12[0x8]; 9798 u8 grp[0x6]; 9799 9800 u8 clr[0x1]; 9801 u8 reserved_at_21[0x1c]; 9802 u8 prio_tc[0x3]; 9803 9804 union mlx5_ifc_eth_cntrs_grp_data_layout_auto_bits counter_set; 9805 }; 9806 9807 struct mlx5_ifc_mpein_reg_bits { 9808 u8 reserved_at_0[0x2]; 9809 u8 depth[0x6]; 9810 u8 pcie_index[0x8]; 9811 u8 node[0x8]; 9812 u8 reserved_at_18[0x8]; 9813 9814 u8 capability_mask[0x20]; 9815 9816 u8 reserved_at_40[0x8]; 9817 u8 link_width_enabled[0x8]; 9818 u8 link_speed_enabled[0x10]; 9819 9820 u8 lane0_physical_position[0x8]; 9821 u8 link_width_active[0x8]; 9822 u8 link_speed_active[0x10]; 9823 9824 u8 num_of_pfs[0x10]; 9825 u8 num_of_vfs[0x10]; 9826 9827 u8 bdf0[0x10]; 9828 u8 reserved_at_b0[0x10]; 9829 9830 u8 max_read_request_size[0x4]; 9831 u8 max_payload_size[0x4]; 9832 u8 reserved_at_c8[0x5]; 9833 u8 pwr_status[0x3]; 9834 u8 port_type[0x4]; 9835 u8 reserved_at_d4[0xb]; 9836 u8 lane_reversal[0x1]; 9837 9838 u8 reserved_at_e0[0x14]; 9839 u8 pci_power[0xc]; 9840 9841 u8 reserved_at_100[0x20]; 9842 9843 u8 device_status[0x10]; 9844 u8 port_state[0x8]; 9845 u8 reserved_at_138[0x8]; 9846 9847 u8 reserved_at_140[0x10]; 9848 u8 receiver_detect_result[0x10]; 9849 9850 u8 reserved_at_160[0x20]; 9851 }; 9852 9853 struct mlx5_ifc_mpcnt_reg_bits { 9854 u8 reserved_at_0[0x8]; 9855 u8 pcie_index[0x8]; 9856 u8 reserved_at_10[0xa]; 9857 u8 grp[0x6]; 9858 9859 u8 clr[0x1]; 9860 u8 reserved_at_21[0x1f]; 9861 9862 union mlx5_ifc_pcie_cntrs_grp_data_layout_auto_bits counter_set; 9863 }; 9864 9865 struct mlx5_ifc_ppad_reg_bits { 9866 u8 reserved_at_0[0x3]; 9867 u8 single_mac[0x1]; 9868 u8 reserved_at_4[0x4]; 9869 u8 local_port[0x8]; 9870 u8 mac_47_32[0x10]; 9871 9872 u8 mac_31_0[0x20]; 9873 9874 u8 reserved_at_40[0x40]; 9875 }; 9876 9877 struct mlx5_ifc_pmtu_reg_bits { 9878 u8 reserved_at_0[0x8]; 9879 u8 local_port[0x8]; 9880 u8 reserved_at_10[0x10]; 9881 9882 u8 max_mtu[0x10]; 9883 u8 reserved_at_30[0x10]; 9884 9885 u8 admin_mtu[0x10]; 9886 u8 reserved_at_50[0x10]; 9887 9888 u8 oper_mtu[0x10]; 9889 u8 reserved_at_70[0x10]; 9890 }; 9891 9892 struct mlx5_ifc_pmpr_reg_bits { 9893 u8 reserved_at_0[0x8]; 9894 u8 module[0x8]; 9895 u8 reserved_at_10[0x10]; 9896 9897 u8 reserved_at_20[0x18]; 9898 u8 attenuation_5g[0x8]; 9899 9900 u8 reserved_at_40[0x18]; 9901 u8 attenuation_7g[0x8]; 9902 9903 u8 reserved_at_60[0x18]; 9904 u8 attenuation_12g[0x8]; 9905 }; 9906 9907 struct mlx5_ifc_pmpe_reg_bits { 9908 u8 reserved_at_0[0x8]; 9909 u8 module[0x8]; 9910 u8 reserved_at_10[0xc]; 9911 u8 module_status[0x4]; 9912 9913 u8 reserved_at_20[0x60]; 9914 }; 9915 9916 struct mlx5_ifc_pmpc_reg_bits { 9917 u8 module_state_updated[32][0x8]; 9918 }; 9919 9920 struct mlx5_ifc_pmlpn_reg_bits { 9921 u8 reserved_at_0[0x4]; 9922 u8 mlpn_status[0x4]; 9923 u8 local_port[0x8]; 9924 u8 reserved_at_10[0x10]; 9925 9926 u8 e[0x1]; 9927 u8 reserved_at_21[0x1f]; 9928 }; 9929 9930 struct mlx5_ifc_pmlp_reg_bits { 9931 u8 rxtx[0x1]; 9932 u8 reserved_at_1[0x7]; 9933 u8 local_port[0x8]; 9934 u8 reserved_at_10[0x8]; 9935 u8 width[0x8]; 9936 9937 u8 lane0_module_mapping[0x20]; 9938 9939 u8 lane1_module_mapping[0x20]; 9940 9941 u8 lane2_module_mapping[0x20]; 9942 9943 u8 lane3_module_mapping[0x20]; 9944 9945 u8 reserved_at_a0[0x160]; 9946 }; 9947 9948 struct mlx5_ifc_pmaos_reg_bits { 9949 u8 reserved_at_0[0x8]; 9950 u8 module[0x8]; 9951 u8 reserved_at_10[0x4]; 9952 u8 admin_status[0x4]; 9953 u8 reserved_at_18[0x4]; 9954 u8 oper_status[0x4]; 9955 9956 u8 ase[0x1]; 9957 u8 ee[0x1]; 9958 u8 reserved_at_22[0x1c]; 9959 u8 e[0x2]; 9960 9961 u8 reserved_at_40[0x40]; 9962 }; 9963 9964 struct mlx5_ifc_plpc_reg_bits { 9965 u8 reserved_at_0[0x4]; 9966 u8 profile_id[0xc]; 9967 u8 reserved_at_10[0x4]; 9968 u8 proto_mask[0x4]; 9969 u8 reserved_at_18[0x8]; 9970 9971 u8 reserved_at_20[0x10]; 9972 u8 lane_speed[0x10]; 9973 9974 u8 reserved_at_40[0x17]; 9975 u8 lpbf[0x1]; 9976 u8 fec_mode_policy[0x8]; 9977 9978 u8 retransmission_capability[0x8]; 9979 u8 fec_mode_capability[0x18]; 9980 9981 u8 retransmission_support_admin[0x8]; 9982 u8 fec_mode_support_admin[0x18]; 9983 9984 u8 retransmission_request_admin[0x8]; 9985 u8 fec_mode_request_admin[0x18]; 9986 9987 u8 reserved_at_c0[0x80]; 9988 }; 9989 9990 struct mlx5_ifc_plib_reg_bits { 9991 u8 reserved_at_0[0x8]; 9992 u8 local_port[0x8]; 9993 u8 reserved_at_10[0x8]; 9994 u8 ib_port[0x8]; 9995 9996 u8 reserved_at_20[0x60]; 9997 }; 9998 9999 struct mlx5_ifc_plbf_reg_bits { 10000 u8 reserved_at_0[0x8]; 10001 u8 local_port[0x8]; 10002 u8 reserved_at_10[0xd]; 10003 u8 lbf_mode[0x3]; 10004 10005 u8 reserved_at_20[0x20]; 10006 }; 10007 10008 struct mlx5_ifc_pipg_reg_bits { 10009 u8 reserved_at_0[0x8]; 10010 u8 local_port[0x8]; 10011 u8 reserved_at_10[0x10]; 10012 10013 u8 dic[0x1]; 10014 u8 reserved_at_21[0x19]; 10015 u8 ipg[0x4]; 10016 u8 reserved_at_3e[0x2]; 10017 }; 10018 10019 struct mlx5_ifc_pifr_reg_bits { 10020 u8 reserved_at_0[0x8]; 10021 u8 local_port[0x8]; 10022 u8 reserved_at_10[0x10]; 10023 10024 u8 reserved_at_20[0xe0]; 10025 10026 u8 port_filter[8][0x20]; 10027 10028 u8 port_filter_update_en[8][0x20]; 10029 }; 10030 10031 struct mlx5_ifc_pfcc_reg_bits { 10032 u8 reserved_at_0[0x8]; 10033 u8 local_port[0x8]; 10034 u8 reserved_at_10[0xb]; 10035 u8 ppan_mask_n[0x1]; 10036 u8 minor_stall_mask[0x1]; 10037 u8 critical_stall_mask[0x1]; 10038 u8 reserved_at_1e[0x2]; 10039 10040 u8 ppan[0x4]; 10041 u8 reserved_at_24[0x4]; 10042 u8 prio_mask_tx[0x8]; 10043 u8 reserved_at_30[0x8]; 10044 u8 prio_mask_rx[0x8]; 10045 10046 u8 pptx[0x1]; 10047 u8 aptx[0x1]; 10048 u8 pptx_mask_n[0x1]; 10049 u8 reserved_at_43[0x5]; 10050 u8 pfctx[0x8]; 10051 u8 reserved_at_50[0x10]; 10052 10053 u8 pprx[0x1]; 10054 u8 aprx[0x1]; 10055 u8 pprx_mask_n[0x1]; 10056 u8 reserved_at_63[0x5]; 10057 u8 pfcrx[0x8]; 10058 u8 reserved_at_70[0x10]; 10059 10060 u8 device_stall_minor_watermark[0x10]; 10061 u8 device_stall_critical_watermark[0x10]; 10062 10063 u8 reserved_at_a0[0x60]; 10064 }; 10065 10066 struct mlx5_ifc_pelc_reg_bits { 10067 u8 op[0x4]; 10068 u8 reserved_at_4[0x4]; 10069 u8 local_port[0x8]; 10070 u8 reserved_at_10[0x10]; 10071 10072 u8 op_admin[0x8]; 10073 u8 op_capability[0x8]; 10074 u8 op_request[0x8]; 10075 u8 op_active[0x8]; 10076 10077 u8 admin[0x40]; 10078 10079 u8 capability[0x40]; 10080 10081 u8 request[0x40]; 10082 10083 u8 active[0x40]; 10084 10085 u8 reserved_at_140[0x80]; 10086 }; 10087 10088 struct mlx5_ifc_peir_reg_bits { 10089 u8 reserved_at_0[0x8]; 10090 u8 local_port[0x8]; 10091 u8 reserved_at_10[0x10]; 10092 10093 u8 reserved_at_20[0xc]; 10094 u8 error_count[0x4]; 10095 u8 reserved_at_30[0x10]; 10096 10097 u8 reserved_at_40[0xc]; 10098 u8 lane[0x4]; 10099 u8 reserved_at_50[0x8]; 10100 u8 error_type[0x8]; 10101 }; 10102 10103 struct mlx5_ifc_mpegc_reg_bits { 10104 u8 reserved_at_0[0x30]; 10105 u8 field_select[0x10]; 10106 10107 u8 tx_overflow_sense[0x1]; 10108 u8 mark_cqe[0x1]; 10109 u8 mark_cnp[0x1]; 10110 u8 reserved_at_43[0x1b]; 10111 u8 tx_lossy_overflow_oper[0x2]; 10112 10113 u8 reserved_at_60[0x100]; 10114 }; 10115 10116 struct mlx5_ifc_mpir_reg_bits { 10117 u8 sdm[0x1]; 10118 u8 reserved_at_1[0x1b]; 10119 u8 host_buses[0x4]; 10120 10121 u8 reserved_at_20[0x20]; 10122 10123 u8 local_port[0x8]; 10124 u8 reserved_at_28[0x15]; 10125 u8 sd_group[0x3]; 10126 10127 u8 reserved_at_60[0x20]; 10128 }; 10129 10130 enum { 10131 MLX5_MTUTC_FREQ_ADJ_UNITS_PPB = 0x0, 10132 MLX5_MTUTC_FREQ_ADJ_UNITS_SCALED_PPM = 0x1, 10133 }; 10134 10135 enum { 10136 MLX5_MTUTC_OPERATION_SET_TIME_IMMEDIATE = 0x1, 10137 MLX5_MTUTC_OPERATION_ADJUST_TIME = 0x2, 10138 MLX5_MTUTC_OPERATION_ADJUST_FREQ_UTC = 0x3, 10139 }; 10140 10141 struct mlx5_ifc_mtutc_reg_bits { 10142 u8 reserved_at_0[0x5]; 10143 u8 freq_adj_units[0x3]; 10144 u8 reserved_at_8[0x3]; 10145 u8 log_max_freq_adjustment[0x5]; 10146 10147 u8 reserved_at_10[0xc]; 10148 u8 operation[0x4]; 10149 10150 u8 freq_adjustment[0x20]; 10151 10152 u8 reserved_at_40[0x40]; 10153 10154 u8 utc_sec[0x20]; 10155 10156 u8 reserved_at_a0[0x2]; 10157 u8 utc_nsec[0x1e]; 10158 10159 u8 time_adjustment[0x20]; 10160 }; 10161 10162 struct mlx5_ifc_pcam_enhanced_features_bits { 10163 u8 reserved_at_0[0x68]; 10164 u8 fec_50G_per_lane_in_pplm[0x1]; 10165 u8 reserved_at_69[0x4]; 10166 u8 rx_icrc_encapsulated_counter[0x1]; 10167 u8 reserved_at_6e[0x4]; 10168 u8 ptys_extended_ethernet[0x1]; 10169 u8 reserved_at_73[0x3]; 10170 u8 pfcc_mask[0x1]; 10171 u8 reserved_at_77[0x3]; 10172 u8 per_lane_error_counters[0x1]; 10173 u8 rx_buffer_fullness_counters[0x1]; 10174 u8 ptys_connector_type[0x1]; 10175 u8 reserved_at_7d[0x1]; 10176 u8 ppcnt_discard_group[0x1]; 10177 u8 ppcnt_statistical_group[0x1]; 10178 }; 10179 10180 struct mlx5_ifc_pcam_regs_5000_to_507f_bits { 10181 u8 port_access_reg_cap_mask_127_to_96[0x20]; 10182 u8 port_access_reg_cap_mask_95_to_64[0x20]; 10183 10184 u8 port_access_reg_cap_mask_63_to_36[0x1c]; 10185 u8 pplm[0x1]; 10186 u8 port_access_reg_cap_mask_34_to_32[0x3]; 10187 10188 u8 port_access_reg_cap_mask_31_to_13[0x13]; 10189 u8 pbmc[0x1]; 10190 u8 pptb[0x1]; 10191 u8 port_access_reg_cap_mask_10_to_09[0x2]; 10192 u8 ppcnt[0x1]; 10193 u8 port_access_reg_cap_mask_07_to_00[0x8]; 10194 }; 10195 10196 struct mlx5_ifc_pcam_reg_bits { 10197 u8 reserved_at_0[0x8]; 10198 u8 feature_group[0x8]; 10199 u8 reserved_at_10[0x8]; 10200 u8 access_reg_group[0x8]; 10201 10202 u8 reserved_at_20[0x20]; 10203 10204 union { 10205 struct mlx5_ifc_pcam_regs_5000_to_507f_bits regs_5000_to_507f; 10206 u8 reserved_at_0[0x80]; 10207 } port_access_reg_cap_mask; 10208 10209 u8 reserved_at_c0[0x80]; 10210 10211 union { 10212 struct mlx5_ifc_pcam_enhanced_features_bits enhanced_features; 10213 u8 reserved_at_0[0x80]; 10214 } feature_cap_mask; 10215 10216 u8 reserved_at_1c0[0xc0]; 10217 }; 10218 10219 struct mlx5_ifc_mcam_enhanced_features_bits { 10220 u8 reserved_at_0[0x50]; 10221 u8 mtutc_freq_adj_units[0x1]; 10222 u8 mtutc_time_adjustment_extended_range[0x1]; 10223 u8 reserved_at_52[0xb]; 10224 u8 mcia_32dwords[0x1]; 10225 u8 out_pulse_duration_ns[0x1]; 10226 u8 npps_period[0x1]; 10227 u8 reserved_at_60[0xa]; 10228 u8 reset_state[0x1]; 10229 u8 ptpcyc2realtime_modify[0x1]; 10230 u8 reserved_at_6c[0x2]; 10231 u8 pci_status_and_power[0x1]; 10232 u8 reserved_at_6f[0x5]; 10233 u8 mark_tx_action_cnp[0x1]; 10234 u8 mark_tx_action_cqe[0x1]; 10235 u8 dynamic_tx_overflow[0x1]; 10236 u8 reserved_at_77[0x4]; 10237 u8 pcie_outbound_stalled[0x1]; 10238 u8 tx_overflow_buffer_pkt[0x1]; 10239 u8 mtpps_enh_out_per_adj[0x1]; 10240 u8 mtpps_fs[0x1]; 10241 u8 pcie_performance_group[0x1]; 10242 }; 10243 10244 struct mlx5_ifc_mcam_access_reg_bits { 10245 u8 reserved_at_0[0x1c]; 10246 u8 mcda[0x1]; 10247 u8 mcc[0x1]; 10248 u8 mcqi[0x1]; 10249 u8 mcqs[0x1]; 10250 10251 u8 regs_95_to_87[0x9]; 10252 u8 mpegc[0x1]; 10253 u8 mtutc[0x1]; 10254 u8 regs_84_to_68[0x11]; 10255 u8 tracer_registers[0x4]; 10256 10257 u8 regs_63_to_46[0x12]; 10258 u8 mrtc[0x1]; 10259 u8 regs_44_to_32[0xd]; 10260 10261 u8 regs_31_to_10[0x16]; 10262 u8 mtmp[0x1]; 10263 u8 regs_8_to_0[0x9]; 10264 }; 10265 10266 struct mlx5_ifc_mcam_access_reg_bits1 { 10267 u8 regs_127_to_96[0x20]; 10268 10269 u8 regs_95_to_64[0x20]; 10270 10271 u8 regs_63_to_32[0x20]; 10272 10273 u8 regs_31_to_0[0x20]; 10274 }; 10275 10276 struct mlx5_ifc_mcam_access_reg_bits2 { 10277 u8 regs_127_to_99[0x1d]; 10278 u8 mirc[0x1]; 10279 u8 regs_97_to_96[0x2]; 10280 10281 u8 regs_95_to_87[0x09]; 10282 u8 synce_registers[0x2]; 10283 u8 regs_84_to_64[0x15]; 10284 10285 u8 regs_63_to_32[0x20]; 10286 10287 u8 regs_31_to_0[0x20]; 10288 }; 10289 10290 struct mlx5_ifc_mcam_reg_bits { 10291 u8 reserved_at_0[0x8]; 10292 u8 feature_group[0x8]; 10293 u8 reserved_at_10[0x8]; 10294 u8 access_reg_group[0x8]; 10295 10296 u8 reserved_at_20[0x20]; 10297 10298 union { 10299 struct mlx5_ifc_mcam_access_reg_bits access_regs; 10300 struct mlx5_ifc_mcam_access_reg_bits1 access_regs1; 10301 struct mlx5_ifc_mcam_access_reg_bits2 access_regs2; 10302 u8 reserved_at_0[0x80]; 10303 } mng_access_reg_cap_mask; 10304 10305 u8 reserved_at_c0[0x80]; 10306 10307 union { 10308 struct mlx5_ifc_mcam_enhanced_features_bits enhanced_features; 10309 u8 reserved_at_0[0x80]; 10310 } mng_feature_cap_mask; 10311 10312 u8 reserved_at_1c0[0x80]; 10313 }; 10314 10315 struct mlx5_ifc_qcam_access_reg_cap_mask { 10316 u8 qcam_access_reg_cap_mask_127_to_20[0x6C]; 10317 u8 qpdpm[0x1]; 10318 u8 qcam_access_reg_cap_mask_18_to_4[0x0F]; 10319 u8 qdpm[0x1]; 10320 u8 qpts[0x1]; 10321 u8 qcap[0x1]; 10322 u8 qcam_access_reg_cap_mask_0[0x1]; 10323 }; 10324 10325 struct mlx5_ifc_qcam_qos_feature_cap_mask { 10326 u8 qcam_qos_feature_cap_mask_127_to_1[0x7F]; 10327 u8 qpts_trust_both[0x1]; 10328 }; 10329 10330 struct mlx5_ifc_qcam_reg_bits { 10331 u8 reserved_at_0[0x8]; 10332 u8 feature_group[0x8]; 10333 u8 reserved_at_10[0x8]; 10334 u8 access_reg_group[0x8]; 10335 u8 reserved_at_20[0x20]; 10336 10337 union { 10338 struct mlx5_ifc_qcam_access_reg_cap_mask reg_cap; 10339 u8 reserved_at_0[0x80]; 10340 } qos_access_reg_cap_mask; 10341 10342 u8 reserved_at_c0[0x80]; 10343 10344 union { 10345 struct mlx5_ifc_qcam_qos_feature_cap_mask feature_cap; 10346 u8 reserved_at_0[0x80]; 10347 } qos_feature_cap_mask; 10348 10349 u8 reserved_at_1c0[0x80]; 10350 }; 10351 10352 struct mlx5_ifc_core_dump_reg_bits { 10353 u8 reserved_at_0[0x18]; 10354 u8 core_dump_type[0x8]; 10355 10356 u8 reserved_at_20[0x30]; 10357 u8 vhca_id[0x10]; 10358 10359 u8 reserved_at_60[0x8]; 10360 u8 qpn[0x18]; 10361 u8 reserved_at_80[0x180]; 10362 }; 10363 10364 struct mlx5_ifc_pcap_reg_bits { 10365 u8 reserved_at_0[0x8]; 10366 u8 local_port[0x8]; 10367 u8 reserved_at_10[0x10]; 10368 10369 u8 port_capability_mask[4][0x20]; 10370 }; 10371 10372 struct mlx5_ifc_paos_reg_bits { 10373 u8 swid[0x8]; 10374 u8 local_port[0x8]; 10375 u8 reserved_at_10[0x4]; 10376 u8 admin_status[0x4]; 10377 u8 reserved_at_18[0x4]; 10378 u8 oper_status[0x4]; 10379 10380 u8 ase[0x1]; 10381 u8 ee[0x1]; 10382 u8 reserved_at_22[0x1c]; 10383 u8 e[0x2]; 10384 10385 u8 reserved_at_40[0x40]; 10386 }; 10387 10388 struct mlx5_ifc_pamp_reg_bits { 10389 u8 reserved_at_0[0x8]; 10390 u8 opamp_group[0x8]; 10391 u8 reserved_at_10[0xc]; 10392 u8 opamp_group_type[0x4]; 10393 10394 u8 start_index[0x10]; 10395 u8 reserved_at_30[0x4]; 10396 u8 num_of_indices[0xc]; 10397 10398 u8 index_data[18][0x10]; 10399 }; 10400 10401 struct mlx5_ifc_pcmr_reg_bits { 10402 u8 reserved_at_0[0x8]; 10403 u8 local_port[0x8]; 10404 u8 reserved_at_10[0x10]; 10405 10406 u8 entropy_force_cap[0x1]; 10407 u8 entropy_calc_cap[0x1]; 10408 u8 entropy_gre_calc_cap[0x1]; 10409 u8 reserved_at_23[0xf]; 10410 u8 rx_ts_over_crc_cap[0x1]; 10411 u8 reserved_at_33[0xb]; 10412 u8 fcs_cap[0x1]; 10413 u8 reserved_at_3f[0x1]; 10414 10415 u8 entropy_force[0x1]; 10416 u8 entropy_calc[0x1]; 10417 u8 entropy_gre_calc[0x1]; 10418 u8 reserved_at_43[0xf]; 10419 u8 rx_ts_over_crc[0x1]; 10420 u8 reserved_at_53[0xb]; 10421 u8 fcs_chk[0x1]; 10422 u8 reserved_at_5f[0x1]; 10423 }; 10424 10425 struct mlx5_ifc_lane_2_module_mapping_bits { 10426 u8 reserved_at_0[0x4]; 10427 u8 rx_lane[0x4]; 10428 u8 reserved_at_8[0x4]; 10429 u8 tx_lane[0x4]; 10430 u8 reserved_at_10[0x8]; 10431 u8 module[0x8]; 10432 }; 10433 10434 struct mlx5_ifc_bufferx_reg_bits { 10435 u8 reserved_at_0[0x6]; 10436 u8 lossy[0x1]; 10437 u8 epsb[0x1]; 10438 u8 reserved_at_8[0x8]; 10439 u8 size[0x10]; 10440 10441 u8 xoff_threshold[0x10]; 10442 u8 xon_threshold[0x10]; 10443 }; 10444 10445 struct mlx5_ifc_set_node_in_bits { 10446 u8 node_description[64][0x8]; 10447 }; 10448 10449 struct mlx5_ifc_register_power_settings_bits { 10450 u8 reserved_at_0[0x18]; 10451 u8 power_settings_level[0x8]; 10452 10453 u8 reserved_at_20[0x60]; 10454 }; 10455 10456 struct mlx5_ifc_register_host_endianness_bits { 10457 u8 he[0x1]; 10458 u8 reserved_at_1[0x1f]; 10459 10460 u8 reserved_at_20[0x60]; 10461 }; 10462 10463 struct mlx5_ifc_umr_pointer_desc_argument_bits { 10464 u8 reserved_at_0[0x20]; 10465 10466 u8 mkey[0x20]; 10467 10468 u8 addressh_63_32[0x20]; 10469 10470 u8 addressl_31_0[0x20]; 10471 }; 10472 10473 struct mlx5_ifc_ud_adrs_vector_bits { 10474 u8 dc_key[0x40]; 10475 10476 u8 ext[0x1]; 10477 u8 reserved_at_41[0x7]; 10478 u8 destination_qp_dct[0x18]; 10479 10480 u8 static_rate[0x4]; 10481 u8 sl_eth_prio[0x4]; 10482 u8 fl[0x1]; 10483 u8 mlid[0x7]; 10484 u8 rlid_udp_sport[0x10]; 10485 10486 u8 reserved_at_80[0x20]; 10487 10488 u8 rmac_47_16[0x20]; 10489 10490 u8 rmac_15_0[0x10]; 10491 u8 tclass[0x8]; 10492 u8 hop_limit[0x8]; 10493 10494 u8 reserved_at_e0[0x1]; 10495 u8 grh[0x1]; 10496 u8 reserved_at_e2[0x2]; 10497 u8 src_addr_index[0x8]; 10498 u8 flow_label[0x14]; 10499 10500 u8 rgid_rip[16][0x8]; 10501 }; 10502 10503 struct mlx5_ifc_pages_req_event_bits { 10504 u8 reserved_at_0[0x10]; 10505 u8 function_id[0x10]; 10506 10507 u8 num_pages[0x20]; 10508 10509 u8 reserved_at_40[0xa0]; 10510 }; 10511 10512 struct mlx5_ifc_eqe_bits { 10513 u8 reserved_at_0[0x8]; 10514 u8 event_type[0x8]; 10515 u8 reserved_at_10[0x8]; 10516 u8 event_sub_type[0x8]; 10517 10518 u8 reserved_at_20[0xe0]; 10519 10520 union mlx5_ifc_event_auto_bits event_data; 10521 10522 u8 reserved_at_1e0[0x10]; 10523 u8 signature[0x8]; 10524 u8 reserved_at_1f8[0x7]; 10525 u8 owner[0x1]; 10526 }; 10527 10528 enum { 10529 MLX5_CMD_QUEUE_ENTRY_TYPE_PCIE_CMD_IF_TRANSPORT = 0x7, 10530 }; 10531 10532 struct mlx5_ifc_cmd_queue_entry_bits { 10533 u8 type[0x8]; 10534 u8 reserved_at_8[0x18]; 10535 10536 u8 input_length[0x20]; 10537 10538 u8 input_mailbox_pointer_63_32[0x20]; 10539 10540 u8 input_mailbox_pointer_31_9[0x17]; 10541 u8 reserved_at_77[0x9]; 10542 10543 u8 command_input_inline_data[16][0x8]; 10544 10545 u8 command_output_inline_data[16][0x8]; 10546 10547 u8 output_mailbox_pointer_63_32[0x20]; 10548 10549 u8 output_mailbox_pointer_31_9[0x17]; 10550 u8 reserved_at_1b7[0x9]; 10551 10552 u8 output_length[0x20]; 10553 10554 u8 token[0x8]; 10555 u8 signature[0x8]; 10556 u8 reserved_at_1f0[0x8]; 10557 u8 status[0x7]; 10558 u8 ownership[0x1]; 10559 }; 10560 10561 struct mlx5_ifc_cmd_out_bits { 10562 u8 status[0x8]; 10563 u8 reserved_at_8[0x18]; 10564 10565 u8 syndrome[0x20]; 10566 10567 u8 command_output[0x20]; 10568 }; 10569 10570 struct mlx5_ifc_cmd_in_bits { 10571 u8 opcode[0x10]; 10572 u8 reserved_at_10[0x10]; 10573 10574 u8 reserved_at_20[0x10]; 10575 u8 op_mod[0x10]; 10576 10577 u8 command[][0x20]; 10578 }; 10579 10580 struct mlx5_ifc_cmd_if_box_bits { 10581 u8 mailbox_data[512][0x8]; 10582 10583 u8 reserved_at_1000[0x180]; 10584 10585 u8 next_pointer_63_32[0x20]; 10586 10587 u8 next_pointer_31_10[0x16]; 10588 u8 reserved_at_11b6[0xa]; 10589 10590 u8 block_number[0x20]; 10591 10592 u8 reserved_at_11e0[0x8]; 10593 u8 token[0x8]; 10594 u8 ctrl_signature[0x8]; 10595 u8 signature[0x8]; 10596 }; 10597 10598 struct mlx5_ifc_mtt_bits { 10599 u8 ptag_63_32[0x20]; 10600 10601 u8 ptag_31_8[0x18]; 10602 u8 reserved_at_38[0x6]; 10603 u8 wr_en[0x1]; 10604 u8 rd_en[0x1]; 10605 }; 10606 10607 struct mlx5_ifc_query_wol_rol_out_bits { 10608 u8 status[0x8]; 10609 u8 reserved_at_8[0x18]; 10610 10611 u8 syndrome[0x20]; 10612 10613 u8 reserved_at_40[0x10]; 10614 u8 rol_mode[0x8]; 10615 u8 wol_mode[0x8]; 10616 10617 u8 reserved_at_60[0x20]; 10618 }; 10619 10620 struct mlx5_ifc_query_wol_rol_in_bits { 10621 u8 opcode[0x10]; 10622 u8 reserved_at_10[0x10]; 10623 10624 u8 reserved_at_20[0x10]; 10625 u8 op_mod[0x10]; 10626 10627 u8 reserved_at_40[0x40]; 10628 }; 10629 10630 struct mlx5_ifc_set_wol_rol_out_bits { 10631 u8 status[0x8]; 10632 u8 reserved_at_8[0x18]; 10633 10634 u8 syndrome[0x20]; 10635 10636 u8 reserved_at_40[0x40]; 10637 }; 10638 10639 struct mlx5_ifc_set_wol_rol_in_bits { 10640 u8 opcode[0x10]; 10641 u8 reserved_at_10[0x10]; 10642 10643 u8 reserved_at_20[0x10]; 10644 u8 op_mod[0x10]; 10645 10646 u8 rol_mode_valid[0x1]; 10647 u8 wol_mode_valid[0x1]; 10648 u8 reserved_at_42[0xe]; 10649 u8 rol_mode[0x8]; 10650 u8 wol_mode[0x8]; 10651 10652 u8 reserved_at_60[0x20]; 10653 }; 10654 10655 enum { 10656 MLX5_INITIAL_SEG_NIC_INTERFACE_FULL_DRIVER = 0x0, 10657 MLX5_INITIAL_SEG_NIC_INTERFACE_DISABLED = 0x1, 10658 MLX5_INITIAL_SEG_NIC_INTERFACE_NO_DRAM_NIC = 0x2, 10659 }; 10660 10661 enum { 10662 MLX5_INITIAL_SEG_NIC_INTERFACE_SUPPORTED_FULL_DRIVER = 0x0, 10663 MLX5_INITIAL_SEG_NIC_INTERFACE_SUPPORTED_DISABLED = 0x1, 10664 MLX5_INITIAL_SEG_NIC_INTERFACE_SUPPORTED_NO_DRAM_NIC = 0x2, 10665 }; 10666 10667 enum { 10668 MLX5_INITIAL_SEG_HEALTH_SYNDROME_FW_INTERNAL_ERR = 0x1, 10669 MLX5_INITIAL_SEG_HEALTH_SYNDROME_DEAD_IRISC = 0x7, 10670 MLX5_INITIAL_SEG_HEALTH_SYNDROME_HW_FATAL_ERR = 0x8, 10671 MLX5_INITIAL_SEG_HEALTH_SYNDROME_FW_CRC_ERR = 0x9, 10672 MLX5_INITIAL_SEG_HEALTH_SYNDROME_ICM_FETCH_PCI_ERR = 0xa, 10673 MLX5_INITIAL_SEG_HEALTH_SYNDROME_ICM_PAGE_ERR = 0xb, 10674 MLX5_INITIAL_SEG_HEALTH_SYNDROME_ASYNCHRONOUS_EQ_BUF_OVERRUN = 0xc, 10675 MLX5_INITIAL_SEG_HEALTH_SYNDROME_EQ_IN_ERR = 0xd, 10676 MLX5_INITIAL_SEG_HEALTH_SYNDROME_EQ_INV = 0xe, 10677 MLX5_INITIAL_SEG_HEALTH_SYNDROME_FFSER_ERR = 0xf, 10678 MLX5_INITIAL_SEG_HEALTH_SYNDROME_HIGH_TEMP_ERR = 0x10, 10679 MLX5_INITIAL_SEG_HEALTH_SYNDROME_ICM_PCI_POISONED_ERR = 0x12, 10680 }; 10681 10682 struct mlx5_ifc_initial_seg_bits { 10683 u8 fw_rev_minor[0x10]; 10684 u8 fw_rev_major[0x10]; 10685 10686 u8 cmd_interface_rev[0x10]; 10687 u8 fw_rev_subminor[0x10]; 10688 10689 u8 reserved_at_40[0x40]; 10690 10691 u8 cmdq_phy_addr_63_32[0x20]; 10692 10693 u8 cmdq_phy_addr_31_12[0x14]; 10694 u8 reserved_at_b4[0x2]; 10695 u8 nic_interface[0x2]; 10696 u8 log_cmdq_size[0x4]; 10697 u8 log_cmdq_stride[0x4]; 10698 10699 u8 command_doorbell_vector[0x20]; 10700 10701 u8 reserved_at_e0[0xf00]; 10702 10703 u8 initializing[0x1]; 10704 u8 reserved_at_fe1[0x4]; 10705 u8 nic_interface_supported[0x3]; 10706 u8 embedded_cpu[0x1]; 10707 u8 reserved_at_fe9[0x17]; 10708 10709 struct mlx5_ifc_health_buffer_bits health_buffer; 10710 10711 u8 no_dram_nic_offset[0x20]; 10712 10713 u8 reserved_at_1220[0x6e40]; 10714 10715 u8 reserved_at_8060[0x1f]; 10716 u8 clear_int[0x1]; 10717 10718 u8 health_syndrome[0x8]; 10719 u8 health_counter[0x18]; 10720 10721 u8 reserved_at_80a0[0x17fc0]; 10722 }; 10723 10724 struct mlx5_ifc_mtpps_reg_bits { 10725 u8 reserved_at_0[0xc]; 10726 u8 cap_number_of_pps_pins[0x4]; 10727 u8 reserved_at_10[0x4]; 10728 u8 cap_max_num_of_pps_in_pins[0x4]; 10729 u8 reserved_at_18[0x4]; 10730 u8 cap_max_num_of_pps_out_pins[0x4]; 10731 10732 u8 reserved_at_20[0x13]; 10733 u8 cap_log_min_npps_period[0x5]; 10734 u8 reserved_at_38[0x3]; 10735 u8 cap_log_min_out_pulse_duration_ns[0x5]; 10736 10737 u8 reserved_at_40[0x4]; 10738 u8 cap_pin_3_mode[0x4]; 10739 u8 reserved_at_48[0x4]; 10740 u8 cap_pin_2_mode[0x4]; 10741 u8 reserved_at_50[0x4]; 10742 u8 cap_pin_1_mode[0x4]; 10743 u8 reserved_at_58[0x4]; 10744 u8 cap_pin_0_mode[0x4]; 10745 10746 u8 reserved_at_60[0x4]; 10747 u8 cap_pin_7_mode[0x4]; 10748 u8 reserved_at_68[0x4]; 10749 u8 cap_pin_6_mode[0x4]; 10750 u8 reserved_at_70[0x4]; 10751 u8 cap_pin_5_mode[0x4]; 10752 u8 reserved_at_78[0x4]; 10753 u8 cap_pin_4_mode[0x4]; 10754 10755 u8 field_select[0x20]; 10756 u8 reserved_at_a0[0x20]; 10757 10758 u8 npps_period[0x40]; 10759 10760 u8 enable[0x1]; 10761 u8 reserved_at_101[0xb]; 10762 u8 pattern[0x4]; 10763 u8 reserved_at_110[0x4]; 10764 u8 pin_mode[0x4]; 10765 u8 pin[0x8]; 10766 10767 u8 reserved_at_120[0x2]; 10768 u8 out_pulse_duration_ns[0x1e]; 10769 10770 u8 time_stamp[0x40]; 10771 10772 u8 out_pulse_duration[0x10]; 10773 u8 out_periodic_adjustment[0x10]; 10774 u8 enhanced_out_periodic_adjustment[0x20]; 10775 10776 u8 reserved_at_1c0[0x20]; 10777 }; 10778 10779 struct mlx5_ifc_mtppse_reg_bits { 10780 u8 reserved_at_0[0x18]; 10781 u8 pin[0x8]; 10782 u8 event_arm[0x1]; 10783 u8 reserved_at_21[0x1b]; 10784 u8 event_generation_mode[0x4]; 10785 u8 reserved_at_40[0x40]; 10786 }; 10787 10788 struct mlx5_ifc_mcqs_reg_bits { 10789 u8 last_index_flag[0x1]; 10790 u8 reserved_at_1[0x7]; 10791 u8 fw_device[0x8]; 10792 u8 component_index[0x10]; 10793 10794 u8 reserved_at_20[0x10]; 10795 u8 identifier[0x10]; 10796 10797 u8 reserved_at_40[0x17]; 10798 u8 component_status[0x5]; 10799 u8 component_update_state[0x4]; 10800 10801 u8 last_update_state_changer_type[0x4]; 10802 u8 last_update_state_changer_host_id[0x4]; 10803 u8 reserved_at_68[0x18]; 10804 }; 10805 10806 struct mlx5_ifc_mcqi_cap_bits { 10807 u8 supported_info_bitmask[0x20]; 10808 10809 u8 component_size[0x20]; 10810 10811 u8 max_component_size[0x20]; 10812 10813 u8 log_mcda_word_size[0x4]; 10814 u8 reserved_at_64[0xc]; 10815 u8 mcda_max_write_size[0x10]; 10816 10817 u8 rd_en[0x1]; 10818 u8 reserved_at_81[0x1]; 10819 u8 match_chip_id[0x1]; 10820 u8 match_psid[0x1]; 10821 u8 check_user_timestamp[0x1]; 10822 u8 match_base_guid_mac[0x1]; 10823 u8 reserved_at_86[0x1a]; 10824 }; 10825 10826 struct mlx5_ifc_mcqi_version_bits { 10827 u8 reserved_at_0[0x2]; 10828 u8 build_time_valid[0x1]; 10829 u8 user_defined_time_valid[0x1]; 10830 u8 reserved_at_4[0x14]; 10831 u8 version_string_length[0x8]; 10832 10833 u8 version[0x20]; 10834 10835 u8 build_time[0x40]; 10836 10837 u8 user_defined_time[0x40]; 10838 10839 u8 build_tool_version[0x20]; 10840 10841 u8 reserved_at_e0[0x20]; 10842 10843 u8 version_string[92][0x8]; 10844 }; 10845 10846 struct mlx5_ifc_mcqi_activation_method_bits { 10847 u8 pending_server_ac_power_cycle[0x1]; 10848 u8 pending_server_dc_power_cycle[0x1]; 10849 u8 pending_server_reboot[0x1]; 10850 u8 pending_fw_reset[0x1]; 10851 u8 auto_activate[0x1]; 10852 u8 all_hosts_sync[0x1]; 10853 u8 device_hw_reset[0x1]; 10854 u8 reserved_at_7[0x19]; 10855 }; 10856 10857 union mlx5_ifc_mcqi_reg_data_bits { 10858 struct mlx5_ifc_mcqi_cap_bits mcqi_caps; 10859 struct mlx5_ifc_mcqi_version_bits mcqi_version; 10860 struct mlx5_ifc_mcqi_activation_method_bits mcqi_activation_mathod; 10861 }; 10862 10863 struct mlx5_ifc_mcqi_reg_bits { 10864 u8 read_pending_component[0x1]; 10865 u8 reserved_at_1[0xf]; 10866 u8 component_index[0x10]; 10867 10868 u8 reserved_at_20[0x20]; 10869 10870 u8 reserved_at_40[0x1b]; 10871 u8 info_type[0x5]; 10872 10873 u8 info_size[0x20]; 10874 10875 u8 offset[0x20]; 10876 10877 u8 reserved_at_a0[0x10]; 10878 u8 data_size[0x10]; 10879 10880 union mlx5_ifc_mcqi_reg_data_bits data[]; 10881 }; 10882 10883 struct mlx5_ifc_mcc_reg_bits { 10884 u8 reserved_at_0[0x4]; 10885 u8 time_elapsed_since_last_cmd[0xc]; 10886 u8 reserved_at_10[0x8]; 10887 u8 instruction[0x8]; 10888 10889 u8 reserved_at_20[0x10]; 10890 u8 component_index[0x10]; 10891 10892 u8 reserved_at_40[0x8]; 10893 u8 update_handle[0x18]; 10894 10895 u8 handle_owner_type[0x4]; 10896 u8 handle_owner_host_id[0x4]; 10897 u8 reserved_at_68[0x1]; 10898 u8 control_progress[0x7]; 10899 u8 error_code[0x8]; 10900 u8 reserved_at_78[0x4]; 10901 u8 control_state[0x4]; 10902 10903 u8 component_size[0x20]; 10904 10905 u8 reserved_at_a0[0x60]; 10906 }; 10907 10908 struct mlx5_ifc_mcda_reg_bits { 10909 u8 reserved_at_0[0x8]; 10910 u8 update_handle[0x18]; 10911 10912 u8 offset[0x20]; 10913 10914 u8 reserved_at_40[0x10]; 10915 u8 size[0x10]; 10916 10917 u8 reserved_at_60[0x20]; 10918 10919 u8 data[][0x20]; 10920 }; 10921 10922 enum { 10923 MLX5_MFRL_REG_RESET_STATE_IDLE = 0, 10924 MLX5_MFRL_REG_RESET_STATE_IN_NEGOTIATION = 1, 10925 MLX5_MFRL_REG_RESET_STATE_RESET_IN_PROGRESS = 2, 10926 MLX5_MFRL_REG_RESET_STATE_NEG_TIMEOUT = 3, 10927 MLX5_MFRL_REG_RESET_STATE_NACK = 4, 10928 MLX5_MFRL_REG_RESET_STATE_UNLOAD_TIMEOUT = 5, 10929 }; 10930 10931 enum { 10932 MLX5_MFRL_REG_RESET_TYPE_FULL_CHIP = BIT(0), 10933 MLX5_MFRL_REG_RESET_TYPE_NET_PORT_ALIVE = BIT(1), 10934 }; 10935 10936 enum { 10937 MLX5_MFRL_REG_RESET_LEVEL0 = BIT(0), 10938 MLX5_MFRL_REG_RESET_LEVEL3 = BIT(3), 10939 MLX5_MFRL_REG_RESET_LEVEL6 = BIT(6), 10940 }; 10941 10942 struct mlx5_ifc_mfrl_reg_bits { 10943 u8 reserved_at_0[0x20]; 10944 10945 u8 reserved_at_20[0x2]; 10946 u8 pci_sync_for_fw_update_start[0x1]; 10947 u8 pci_sync_for_fw_update_resp[0x2]; 10948 u8 rst_type_sel[0x3]; 10949 u8 reserved_at_28[0x4]; 10950 u8 reset_state[0x4]; 10951 u8 reset_type[0x8]; 10952 u8 reset_level[0x8]; 10953 }; 10954 10955 struct mlx5_ifc_mirc_reg_bits { 10956 u8 reserved_at_0[0x18]; 10957 u8 status_code[0x8]; 10958 10959 u8 reserved_at_20[0x20]; 10960 }; 10961 10962 struct mlx5_ifc_pddr_monitor_opcode_bits { 10963 u8 reserved_at_0[0x10]; 10964 u8 monitor_opcode[0x10]; 10965 }; 10966 10967 union mlx5_ifc_pddr_troubleshooting_page_status_opcode_auto_bits { 10968 struct mlx5_ifc_pddr_monitor_opcode_bits pddr_monitor_opcode; 10969 u8 reserved_at_0[0x20]; 10970 }; 10971 10972 enum { 10973 /* Monitor opcodes */ 10974 MLX5_PDDR_REG_TRBLSH_GROUP_OPCODE_MONITOR = 0x0, 10975 }; 10976 10977 struct mlx5_ifc_pddr_troubleshooting_page_bits { 10978 u8 reserved_at_0[0x10]; 10979 u8 group_opcode[0x10]; 10980 10981 union mlx5_ifc_pddr_troubleshooting_page_status_opcode_auto_bits status_opcode; 10982 10983 u8 reserved_at_40[0x20]; 10984 10985 u8 status_message[59][0x20]; 10986 }; 10987 10988 union mlx5_ifc_pddr_reg_page_data_auto_bits { 10989 struct mlx5_ifc_pddr_troubleshooting_page_bits pddr_troubleshooting_page; 10990 u8 reserved_at_0[0x7c0]; 10991 }; 10992 10993 enum { 10994 MLX5_PDDR_REG_PAGE_SELECT_TROUBLESHOOTING_INFO_PAGE = 0x1, 10995 }; 10996 10997 struct mlx5_ifc_pddr_reg_bits { 10998 u8 reserved_at_0[0x8]; 10999 u8 local_port[0x8]; 11000 u8 pnat[0x2]; 11001 u8 reserved_at_12[0xe]; 11002 11003 u8 reserved_at_20[0x18]; 11004 u8 page_select[0x8]; 11005 11006 union mlx5_ifc_pddr_reg_page_data_auto_bits page_data; 11007 }; 11008 11009 struct mlx5_ifc_mrtc_reg_bits { 11010 u8 time_synced[0x1]; 11011 u8 reserved_at_1[0x1f]; 11012 11013 u8 reserved_at_20[0x20]; 11014 11015 u8 time_h[0x20]; 11016 11017 u8 time_l[0x20]; 11018 }; 11019 11020 struct mlx5_ifc_mtcap_reg_bits { 11021 u8 reserved_at_0[0x19]; 11022 u8 sensor_count[0x7]; 11023 11024 u8 reserved_at_20[0x20]; 11025 11026 u8 sensor_map[0x40]; 11027 }; 11028 11029 struct mlx5_ifc_mtmp_reg_bits { 11030 u8 reserved_at_0[0x14]; 11031 u8 sensor_index[0xc]; 11032 11033 u8 reserved_at_20[0x10]; 11034 u8 temperature[0x10]; 11035 11036 u8 mte[0x1]; 11037 u8 mtr[0x1]; 11038 u8 reserved_at_42[0xe]; 11039 u8 max_temperature[0x10]; 11040 11041 u8 tee[0x2]; 11042 u8 reserved_at_62[0xe]; 11043 u8 temp_threshold_hi[0x10]; 11044 11045 u8 reserved_at_80[0x10]; 11046 u8 temp_threshold_lo[0x10]; 11047 11048 u8 reserved_at_a0[0x20]; 11049 11050 u8 sensor_name_hi[0x20]; 11051 u8 sensor_name_lo[0x20]; 11052 }; 11053 11054 union mlx5_ifc_ports_control_registers_document_bits { 11055 struct mlx5_ifc_bufferx_reg_bits bufferx_reg; 11056 struct mlx5_ifc_eth_2819_cntrs_grp_data_layout_bits eth_2819_cntrs_grp_data_layout; 11057 struct mlx5_ifc_eth_2863_cntrs_grp_data_layout_bits eth_2863_cntrs_grp_data_layout; 11058 struct mlx5_ifc_eth_3635_cntrs_grp_data_layout_bits eth_3635_cntrs_grp_data_layout; 11059 struct mlx5_ifc_eth_802_3_cntrs_grp_data_layout_bits eth_802_3_cntrs_grp_data_layout; 11060 struct mlx5_ifc_eth_extended_cntrs_grp_data_layout_bits eth_extended_cntrs_grp_data_layout; 11061 struct mlx5_ifc_eth_per_prio_grp_data_layout_bits eth_per_prio_grp_data_layout; 11062 struct mlx5_ifc_eth_per_tc_prio_grp_data_layout_bits eth_per_tc_prio_grp_data_layout; 11063 struct mlx5_ifc_eth_per_tc_congest_prio_grp_data_layout_bits eth_per_tc_congest_prio_grp_data_layout; 11064 struct mlx5_ifc_lane_2_module_mapping_bits lane_2_module_mapping; 11065 struct mlx5_ifc_pamp_reg_bits pamp_reg; 11066 struct mlx5_ifc_paos_reg_bits paos_reg; 11067 struct mlx5_ifc_pcap_reg_bits pcap_reg; 11068 struct mlx5_ifc_pddr_monitor_opcode_bits pddr_monitor_opcode; 11069 struct mlx5_ifc_pddr_reg_bits pddr_reg; 11070 struct mlx5_ifc_pddr_troubleshooting_page_bits pddr_troubleshooting_page; 11071 struct mlx5_ifc_peir_reg_bits peir_reg; 11072 struct mlx5_ifc_pelc_reg_bits pelc_reg; 11073 struct mlx5_ifc_pfcc_reg_bits pfcc_reg; 11074 struct mlx5_ifc_ib_port_cntrs_grp_data_layout_bits ib_port_cntrs_grp_data_layout; 11075 struct mlx5_ifc_phys_layer_cntrs_bits phys_layer_cntrs; 11076 struct mlx5_ifc_pifr_reg_bits pifr_reg; 11077 struct mlx5_ifc_pipg_reg_bits pipg_reg; 11078 struct mlx5_ifc_plbf_reg_bits plbf_reg; 11079 struct mlx5_ifc_plib_reg_bits plib_reg; 11080 struct mlx5_ifc_plpc_reg_bits plpc_reg; 11081 struct mlx5_ifc_pmaos_reg_bits pmaos_reg; 11082 struct mlx5_ifc_pmlp_reg_bits pmlp_reg; 11083 struct mlx5_ifc_pmlpn_reg_bits pmlpn_reg; 11084 struct mlx5_ifc_pmpc_reg_bits pmpc_reg; 11085 struct mlx5_ifc_pmpe_reg_bits pmpe_reg; 11086 struct mlx5_ifc_pmpr_reg_bits pmpr_reg; 11087 struct mlx5_ifc_pmtu_reg_bits pmtu_reg; 11088 struct mlx5_ifc_ppad_reg_bits ppad_reg; 11089 struct mlx5_ifc_ppcnt_reg_bits ppcnt_reg; 11090 struct mlx5_ifc_mpein_reg_bits mpein_reg; 11091 struct mlx5_ifc_mpcnt_reg_bits mpcnt_reg; 11092 struct mlx5_ifc_pplm_reg_bits pplm_reg; 11093 struct mlx5_ifc_pplr_reg_bits pplr_reg; 11094 struct mlx5_ifc_ppsc_reg_bits ppsc_reg; 11095 struct mlx5_ifc_pqdr_reg_bits pqdr_reg; 11096 struct mlx5_ifc_pspa_reg_bits pspa_reg; 11097 struct mlx5_ifc_ptas_reg_bits ptas_reg; 11098 struct mlx5_ifc_ptys_reg_bits ptys_reg; 11099 struct mlx5_ifc_mlcr_reg_bits mlcr_reg; 11100 struct mlx5_ifc_pude_reg_bits pude_reg; 11101 struct mlx5_ifc_pvlc_reg_bits pvlc_reg; 11102 struct mlx5_ifc_slrg_reg_bits slrg_reg; 11103 struct mlx5_ifc_sltp_reg_bits sltp_reg; 11104 struct mlx5_ifc_mtpps_reg_bits mtpps_reg; 11105 struct mlx5_ifc_mtppse_reg_bits mtppse_reg; 11106 struct mlx5_ifc_fpga_access_reg_bits fpga_access_reg; 11107 struct mlx5_ifc_fpga_ctrl_bits fpga_ctrl_bits; 11108 struct mlx5_ifc_fpga_cap_bits fpga_cap_bits; 11109 struct mlx5_ifc_mcqi_reg_bits mcqi_reg; 11110 struct mlx5_ifc_mcc_reg_bits mcc_reg; 11111 struct mlx5_ifc_mcda_reg_bits mcda_reg; 11112 struct mlx5_ifc_mirc_reg_bits mirc_reg; 11113 struct mlx5_ifc_mfrl_reg_bits mfrl_reg; 11114 struct mlx5_ifc_mtutc_reg_bits mtutc_reg; 11115 struct mlx5_ifc_mrtc_reg_bits mrtc_reg; 11116 struct mlx5_ifc_mtcap_reg_bits mtcap_reg; 11117 struct mlx5_ifc_mtmp_reg_bits mtmp_reg; 11118 u8 reserved_at_0[0x60e0]; 11119 }; 11120 11121 union mlx5_ifc_debug_enhancements_document_bits { 11122 struct mlx5_ifc_health_buffer_bits health_buffer; 11123 u8 reserved_at_0[0x200]; 11124 }; 11125 11126 union mlx5_ifc_uplink_pci_interface_document_bits { 11127 struct mlx5_ifc_initial_seg_bits initial_seg; 11128 u8 reserved_at_0[0x20060]; 11129 }; 11130 11131 struct mlx5_ifc_set_flow_table_root_out_bits { 11132 u8 status[0x8]; 11133 u8 reserved_at_8[0x18]; 11134 11135 u8 syndrome[0x20]; 11136 11137 u8 reserved_at_40[0x40]; 11138 }; 11139 11140 struct mlx5_ifc_set_flow_table_root_in_bits { 11141 u8 opcode[0x10]; 11142 u8 reserved_at_10[0x10]; 11143 11144 u8 reserved_at_20[0x10]; 11145 u8 op_mod[0x10]; 11146 11147 u8 other_vport[0x1]; 11148 u8 reserved_at_41[0xf]; 11149 u8 vport_number[0x10]; 11150 11151 u8 reserved_at_60[0x20]; 11152 11153 u8 table_type[0x8]; 11154 u8 reserved_at_88[0x7]; 11155 u8 table_of_other_vport[0x1]; 11156 u8 table_vport_number[0x10]; 11157 11158 u8 reserved_at_a0[0x8]; 11159 u8 table_id[0x18]; 11160 11161 u8 reserved_at_c0[0x8]; 11162 u8 underlay_qpn[0x18]; 11163 u8 table_eswitch_owner_vhca_id_valid[0x1]; 11164 u8 reserved_at_e1[0xf]; 11165 u8 table_eswitch_owner_vhca_id[0x10]; 11166 u8 reserved_at_100[0x100]; 11167 }; 11168 11169 enum { 11170 MLX5_MODIFY_FLOW_TABLE_MISS_TABLE_ID = (1UL << 0), 11171 MLX5_MODIFY_FLOW_TABLE_LAG_NEXT_TABLE_ID = (1UL << 15), 11172 }; 11173 11174 struct mlx5_ifc_modify_flow_table_out_bits { 11175 u8 status[0x8]; 11176 u8 reserved_at_8[0x18]; 11177 11178 u8 syndrome[0x20]; 11179 11180 u8 reserved_at_40[0x40]; 11181 }; 11182 11183 struct mlx5_ifc_modify_flow_table_in_bits { 11184 u8 opcode[0x10]; 11185 u8 reserved_at_10[0x10]; 11186 11187 u8 reserved_at_20[0x10]; 11188 u8 op_mod[0x10]; 11189 11190 u8 other_vport[0x1]; 11191 u8 reserved_at_41[0xf]; 11192 u8 vport_number[0x10]; 11193 11194 u8 reserved_at_60[0x10]; 11195 u8 modify_field_select[0x10]; 11196 11197 u8 table_type[0x8]; 11198 u8 reserved_at_88[0x18]; 11199 11200 u8 reserved_at_a0[0x8]; 11201 u8 table_id[0x18]; 11202 11203 struct mlx5_ifc_flow_table_context_bits flow_table_context; 11204 }; 11205 11206 struct mlx5_ifc_ets_tcn_config_reg_bits { 11207 u8 g[0x1]; 11208 u8 b[0x1]; 11209 u8 r[0x1]; 11210 u8 reserved_at_3[0x9]; 11211 u8 group[0x4]; 11212 u8 reserved_at_10[0x9]; 11213 u8 bw_allocation[0x7]; 11214 11215 u8 reserved_at_20[0xc]; 11216 u8 max_bw_units[0x4]; 11217 u8 reserved_at_30[0x8]; 11218 u8 max_bw_value[0x8]; 11219 }; 11220 11221 struct mlx5_ifc_ets_global_config_reg_bits { 11222 u8 reserved_at_0[0x2]; 11223 u8 r[0x1]; 11224 u8 reserved_at_3[0x1d]; 11225 11226 u8 reserved_at_20[0xc]; 11227 u8 max_bw_units[0x4]; 11228 u8 reserved_at_30[0x8]; 11229 u8 max_bw_value[0x8]; 11230 }; 11231 11232 struct mlx5_ifc_qetc_reg_bits { 11233 u8 reserved_at_0[0x8]; 11234 u8 port_number[0x8]; 11235 u8 reserved_at_10[0x30]; 11236 11237 struct mlx5_ifc_ets_tcn_config_reg_bits tc_configuration[0x8]; 11238 struct mlx5_ifc_ets_global_config_reg_bits global_configuration; 11239 }; 11240 11241 struct mlx5_ifc_qpdpm_dscp_reg_bits { 11242 u8 e[0x1]; 11243 u8 reserved_at_01[0x0b]; 11244 u8 prio[0x04]; 11245 }; 11246 11247 struct mlx5_ifc_qpdpm_reg_bits { 11248 u8 reserved_at_0[0x8]; 11249 u8 local_port[0x8]; 11250 u8 reserved_at_10[0x10]; 11251 struct mlx5_ifc_qpdpm_dscp_reg_bits dscp[64]; 11252 }; 11253 11254 struct mlx5_ifc_qpts_reg_bits { 11255 u8 reserved_at_0[0x8]; 11256 u8 local_port[0x8]; 11257 u8 reserved_at_10[0x2d]; 11258 u8 trust_state[0x3]; 11259 }; 11260 11261 struct mlx5_ifc_pptb_reg_bits { 11262 u8 reserved_at_0[0x2]; 11263 u8 mm[0x2]; 11264 u8 reserved_at_4[0x4]; 11265 u8 local_port[0x8]; 11266 u8 reserved_at_10[0x6]; 11267 u8 cm[0x1]; 11268 u8 um[0x1]; 11269 u8 pm[0x8]; 11270 11271 u8 prio_x_buff[0x20]; 11272 11273 u8 pm_msb[0x8]; 11274 u8 reserved_at_48[0x10]; 11275 u8 ctrl_buff[0x4]; 11276 u8 untagged_buff[0x4]; 11277 }; 11278 11279 struct mlx5_ifc_sbcam_reg_bits { 11280 u8 reserved_at_0[0x8]; 11281 u8 feature_group[0x8]; 11282 u8 reserved_at_10[0x8]; 11283 u8 access_reg_group[0x8]; 11284 11285 u8 reserved_at_20[0x20]; 11286 11287 u8 sb_access_reg_cap_mask[4][0x20]; 11288 11289 u8 reserved_at_c0[0x80]; 11290 11291 u8 sb_feature_cap_mask[4][0x20]; 11292 11293 u8 reserved_at_1c0[0x40]; 11294 11295 u8 cap_total_buffer_size[0x20]; 11296 11297 u8 cap_cell_size[0x10]; 11298 u8 cap_max_pg_buffers[0x8]; 11299 u8 cap_num_pool_supported[0x8]; 11300 11301 u8 reserved_at_240[0x8]; 11302 u8 cap_sbsr_stat_size[0x8]; 11303 u8 cap_max_tclass_data[0x8]; 11304 u8 cap_max_cpu_ingress_tclass_sb[0x8]; 11305 }; 11306 11307 struct mlx5_ifc_pbmc_reg_bits { 11308 u8 reserved_at_0[0x8]; 11309 u8 local_port[0x8]; 11310 u8 reserved_at_10[0x10]; 11311 11312 u8 xoff_timer_value[0x10]; 11313 u8 xoff_refresh[0x10]; 11314 11315 u8 reserved_at_40[0x9]; 11316 u8 fullness_threshold[0x7]; 11317 u8 port_buffer_size[0x10]; 11318 11319 struct mlx5_ifc_bufferx_reg_bits buffer[10]; 11320 11321 u8 reserved_at_2e0[0x80]; 11322 }; 11323 11324 struct mlx5_ifc_sbpr_reg_bits { 11325 u8 desc[0x1]; 11326 u8 snap[0x1]; 11327 u8 reserved_at_2[0x4]; 11328 u8 dir[0x2]; 11329 u8 reserved_at_8[0x14]; 11330 u8 pool[0x4]; 11331 11332 u8 infi_size[0x1]; 11333 u8 reserved_at_21[0x7]; 11334 u8 size[0x18]; 11335 11336 u8 reserved_at_40[0x1c]; 11337 u8 mode[0x4]; 11338 11339 u8 reserved_at_60[0x8]; 11340 u8 buff_occupancy[0x18]; 11341 11342 u8 clr[0x1]; 11343 u8 reserved_at_81[0x7]; 11344 u8 max_buff_occupancy[0x18]; 11345 11346 u8 reserved_at_a0[0x8]; 11347 u8 ext_buff_occupancy[0x18]; 11348 }; 11349 11350 struct mlx5_ifc_sbcm_reg_bits { 11351 u8 desc[0x1]; 11352 u8 snap[0x1]; 11353 u8 reserved_at_2[0x6]; 11354 u8 local_port[0x8]; 11355 u8 pnat[0x2]; 11356 u8 pg_buff[0x6]; 11357 u8 reserved_at_18[0x6]; 11358 u8 dir[0x2]; 11359 11360 u8 reserved_at_20[0x1f]; 11361 u8 exc[0x1]; 11362 11363 u8 reserved_at_40[0x40]; 11364 11365 u8 reserved_at_80[0x8]; 11366 u8 buff_occupancy[0x18]; 11367 11368 u8 clr[0x1]; 11369 u8 reserved_at_a1[0x7]; 11370 u8 max_buff_occupancy[0x18]; 11371 11372 u8 reserved_at_c0[0x8]; 11373 u8 min_buff[0x18]; 11374 11375 u8 infi_max[0x1]; 11376 u8 reserved_at_e1[0x7]; 11377 u8 max_buff[0x18]; 11378 11379 u8 reserved_at_100[0x20]; 11380 11381 u8 reserved_at_120[0x1c]; 11382 u8 pool[0x4]; 11383 }; 11384 11385 struct mlx5_ifc_qtct_reg_bits { 11386 u8 reserved_at_0[0x8]; 11387 u8 port_number[0x8]; 11388 u8 reserved_at_10[0xd]; 11389 u8 prio[0x3]; 11390 11391 u8 reserved_at_20[0x1d]; 11392 u8 tclass[0x3]; 11393 }; 11394 11395 struct mlx5_ifc_mcia_reg_bits { 11396 u8 l[0x1]; 11397 u8 reserved_at_1[0x7]; 11398 u8 module[0x8]; 11399 u8 reserved_at_10[0x8]; 11400 u8 status[0x8]; 11401 11402 u8 i2c_device_address[0x8]; 11403 u8 page_number[0x8]; 11404 u8 device_address[0x10]; 11405 11406 u8 reserved_at_40[0x10]; 11407 u8 size[0x10]; 11408 11409 u8 reserved_at_60[0x20]; 11410 11411 u8 dword_0[0x20]; 11412 u8 dword_1[0x20]; 11413 u8 dword_2[0x20]; 11414 u8 dword_3[0x20]; 11415 u8 dword_4[0x20]; 11416 u8 dword_5[0x20]; 11417 u8 dword_6[0x20]; 11418 u8 dword_7[0x20]; 11419 u8 dword_8[0x20]; 11420 u8 dword_9[0x20]; 11421 u8 dword_10[0x20]; 11422 u8 dword_11[0x20]; 11423 }; 11424 11425 struct mlx5_ifc_dcbx_param_bits { 11426 u8 dcbx_cee_cap[0x1]; 11427 u8 dcbx_ieee_cap[0x1]; 11428 u8 dcbx_standby_cap[0x1]; 11429 u8 reserved_at_3[0x5]; 11430 u8 port_number[0x8]; 11431 u8 reserved_at_10[0xa]; 11432 u8 max_application_table_size[6]; 11433 u8 reserved_at_20[0x15]; 11434 u8 version_oper[0x3]; 11435 u8 reserved_at_38[5]; 11436 u8 version_admin[0x3]; 11437 u8 willing_admin[0x1]; 11438 u8 reserved_at_41[0x3]; 11439 u8 pfc_cap_oper[0x4]; 11440 u8 reserved_at_48[0x4]; 11441 u8 pfc_cap_admin[0x4]; 11442 u8 reserved_at_50[0x4]; 11443 u8 num_of_tc_oper[0x4]; 11444 u8 reserved_at_58[0x4]; 11445 u8 num_of_tc_admin[0x4]; 11446 u8 remote_willing[0x1]; 11447 u8 reserved_at_61[3]; 11448 u8 remote_pfc_cap[4]; 11449 u8 reserved_at_68[0x14]; 11450 u8 remote_num_of_tc[0x4]; 11451 u8 reserved_at_80[0x18]; 11452 u8 error[0x8]; 11453 u8 reserved_at_a0[0x160]; 11454 }; 11455 11456 enum { 11457 MLX5_LAG_PORT_SELECT_MODE_QUEUE_AFFINITY = 0, 11458 MLX5_LAG_PORT_SELECT_MODE_PORT_SELECT_FT = 1, 11459 MLX5_LAG_PORT_SELECT_MODE_PORT_SELECT_MPESW = 2, 11460 }; 11461 11462 struct mlx5_ifc_lagc_bits { 11463 u8 fdb_selection_mode[0x1]; 11464 u8 reserved_at_1[0x14]; 11465 u8 port_select_mode[0x3]; 11466 u8 reserved_at_18[0x5]; 11467 u8 lag_state[0x3]; 11468 11469 u8 reserved_at_20[0xc]; 11470 u8 active_port[0x4]; 11471 u8 reserved_at_30[0x4]; 11472 u8 tx_remap_affinity_2[0x4]; 11473 u8 reserved_at_38[0x4]; 11474 u8 tx_remap_affinity_1[0x4]; 11475 }; 11476 11477 struct mlx5_ifc_create_lag_out_bits { 11478 u8 status[0x8]; 11479 u8 reserved_at_8[0x18]; 11480 11481 u8 syndrome[0x20]; 11482 11483 u8 reserved_at_40[0x40]; 11484 }; 11485 11486 struct mlx5_ifc_create_lag_in_bits { 11487 u8 opcode[0x10]; 11488 u8 reserved_at_10[0x10]; 11489 11490 u8 reserved_at_20[0x10]; 11491 u8 op_mod[0x10]; 11492 11493 struct mlx5_ifc_lagc_bits ctx; 11494 }; 11495 11496 struct mlx5_ifc_modify_lag_out_bits { 11497 u8 status[0x8]; 11498 u8 reserved_at_8[0x18]; 11499 11500 u8 syndrome[0x20]; 11501 11502 u8 reserved_at_40[0x40]; 11503 }; 11504 11505 struct mlx5_ifc_modify_lag_in_bits { 11506 u8 opcode[0x10]; 11507 u8 reserved_at_10[0x10]; 11508 11509 u8 reserved_at_20[0x10]; 11510 u8 op_mod[0x10]; 11511 11512 u8 reserved_at_40[0x20]; 11513 u8 field_select[0x20]; 11514 11515 struct mlx5_ifc_lagc_bits ctx; 11516 }; 11517 11518 struct mlx5_ifc_query_lag_out_bits { 11519 u8 status[0x8]; 11520 u8 reserved_at_8[0x18]; 11521 11522 u8 syndrome[0x20]; 11523 11524 struct mlx5_ifc_lagc_bits ctx; 11525 }; 11526 11527 struct mlx5_ifc_query_lag_in_bits { 11528 u8 opcode[0x10]; 11529 u8 reserved_at_10[0x10]; 11530 11531 u8 reserved_at_20[0x10]; 11532 u8 op_mod[0x10]; 11533 11534 u8 reserved_at_40[0x40]; 11535 }; 11536 11537 struct mlx5_ifc_destroy_lag_out_bits { 11538 u8 status[0x8]; 11539 u8 reserved_at_8[0x18]; 11540 11541 u8 syndrome[0x20]; 11542 11543 u8 reserved_at_40[0x40]; 11544 }; 11545 11546 struct mlx5_ifc_destroy_lag_in_bits { 11547 u8 opcode[0x10]; 11548 u8 reserved_at_10[0x10]; 11549 11550 u8 reserved_at_20[0x10]; 11551 u8 op_mod[0x10]; 11552 11553 u8 reserved_at_40[0x40]; 11554 }; 11555 11556 struct mlx5_ifc_create_vport_lag_out_bits { 11557 u8 status[0x8]; 11558 u8 reserved_at_8[0x18]; 11559 11560 u8 syndrome[0x20]; 11561 11562 u8 reserved_at_40[0x40]; 11563 }; 11564 11565 struct mlx5_ifc_create_vport_lag_in_bits { 11566 u8 opcode[0x10]; 11567 u8 reserved_at_10[0x10]; 11568 11569 u8 reserved_at_20[0x10]; 11570 u8 op_mod[0x10]; 11571 11572 u8 reserved_at_40[0x40]; 11573 }; 11574 11575 struct mlx5_ifc_destroy_vport_lag_out_bits { 11576 u8 status[0x8]; 11577 u8 reserved_at_8[0x18]; 11578 11579 u8 syndrome[0x20]; 11580 11581 u8 reserved_at_40[0x40]; 11582 }; 11583 11584 struct mlx5_ifc_destroy_vport_lag_in_bits { 11585 u8 opcode[0x10]; 11586 u8 reserved_at_10[0x10]; 11587 11588 u8 reserved_at_20[0x10]; 11589 u8 op_mod[0x10]; 11590 11591 u8 reserved_at_40[0x40]; 11592 }; 11593 11594 enum { 11595 MLX5_MODIFY_MEMIC_OP_MOD_ALLOC, 11596 MLX5_MODIFY_MEMIC_OP_MOD_DEALLOC, 11597 }; 11598 11599 struct mlx5_ifc_modify_memic_in_bits { 11600 u8 opcode[0x10]; 11601 u8 uid[0x10]; 11602 11603 u8 reserved_at_20[0x10]; 11604 u8 op_mod[0x10]; 11605 11606 u8 reserved_at_40[0x20]; 11607 11608 u8 reserved_at_60[0x18]; 11609 u8 memic_operation_type[0x8]; 11610 11611 u8 memic_start_addr[0x40]; 11612 11613 u8 reserved_at_c0[0x140]; 11614 }; 11615 11616 struct mlx5_ifc_modify_memic_out_bits { 11617 u8 status[0x8]; 11618 u8 reserved_at_8[0x18]; 11619 11620 u8 syndrome[0x20]; 11621 11622 u8 reserved_at_40[0x40]; 11623 11624 u8 memic_operation_addr[0x40]; 11625 11626 u8 reserved_at_c0[0x140]; 11627 }; 11628 11629 struct mlx5_ifc_alloc_memic_in_bits { 11630 u8 opcode[0x10]; 11631 u8 reserved_at_10[0x10]; 11632 11633 u8 reserved_at_20[0x10]; 11634 u8 op_mod[0x10]; 11635 11636 u8 reserved_at_30[0x20]; 11637 11638 u8 reserved_at_40[0x18]; 11639 u8 log_memic_addr_alignment[0x8]; 11640 11641 u8 range_start_addr[0x40]; 11642 11643 u8 range_size[0x20]; 11644 11645 u8 memic_size[0x20]; 11646 }; 11647 11648 struct mlx5_ifc_alloc_memic_out_bits { 11649 u8 status[0x8]; 11650 u8 reserved_at_8[0x18]; 11651 11652 u8 syndrome[0x20]; 11653 11654 u8 memic_start_addr[0x40]; 11655 }; 11656 11657 struct mlx5_ifc_dealloc_memic_in_bits { 11658 u8 opcode[0x10]; 11659 u8 reserved_at_10[0x10]; 11660 11661 u8 reserved_at_20[0x10]; 11662 u8 op_mod[0x10]; 11663 11664 u8 reserved_at_40[0x40]; 11665 11666 u8 memic_start_addr[0x40]; 11667 11668 u8 memic_size[0x20]; 11669 11670 u8 reserved_at_e0[0x20]; 11671 }; 11672 11673 struct mlx5_ifc_dealloc_memic_out_bits { 11674 u8 status[0x8]; 11675 u8 reserved_at_8[0x18]; 11676 11677 u8 syndrome[0x20]; 11678 11679 u8 reserved_at_40[0x40]; 11680 }; 11681 11682 struct mlx5_ifc_umem_bits { 11683 u8 reserved_at_0[0x80]; 11684 11685 u8 ats[0x1]; 11686 u8 reserved_at_81[0x1a]; 11687 u8 log_page_size[0x5]; 11688 11689 u8 page_offset[0x20]; 11690 11691 u8 num_of_mtt[0x40]; 11692 11693 struct mlx5_ifc_mtt_bits mtt[]; 11694 }; 11695 11696 struct mlx5_ifc_uctx_bits { 11697 u8 cap[0x20]; 11698 11699 u8 reserved_at_20[0x160]; 11700 }; 11701 11702 struct mlx5_ifc_sw_icm_bits { 11703 u8 modify_field_select[0x40]; 11704 11705 u8 reserved_at_40[0x18]; 11706 u8 log_sw_icm_size[0x8]; 11707 11708 u8 reserved_at_60[0x20]; 11709 11710 u8 sw_icm_start_addr[0x40]; 11711 11712 u8 reserved_at_c0[0x140]; 11713 }; 11714 11715 struct mlx5_ifc_geneve_tlv_option_bits { 11716 u8 modify_field_select[0x40]; 11717 11718 u8 reserved_at_40[0x18]; 11719 u8 geneve_option_fte_index[0x8]; 11720 11721 u8 option_class[0x10]; 11722 u8 option_type[0x8]; 11723 u8 reserved_at_78[0x3]; 11724 u8 option_data_length[0x5]; 11725 11726 u8 reserved_at_80[0x180]; 11727 }; 11728 11729 struct mlx5_ifc_create_umem_in_bits { 11730 u8 opcode[0x10]; 11731 u8 uid[0x10]; 11732 11733 u8 reserved_at_20[0x10]; 11734 u8 op_mod[0x10]; 11735 11736 u8 reserved_at_40[0x40]; 11737 11738 struct mlx5_ifc_umem_bits umem; 11739 }; 11740 11741 struct mlx5_ifc_create_umem_out_bits { 11742 u8 status[0x8]; 11743 u8 reserved_at_8[0x18]; 11744 11745 u8 syndrome[0x20]; 11746 11747 u8 reserved_at_40[0x8]; 11748 u8 umem_id[0x18]; 11749 11750 u8 reserved_at_60[0x20]; 11751 }; 11752 11753 struct mlx5_ifc_destroy_umem_in_bits { 11754 u8 opcode[0x10]; 11755 u8 uid[0x10]; 11756 11757 u8 reserved_at_20[0x10]; 11758 u8 op_mod[0x10]; 11759 11760 u8 reserved_at_40[0x8]; 11761 u8 umem_id[0x18]; 11762 11763 u8 reserved_at_60[0x20]; 11764 }; 11765 11766 struct mlx5_ifc_destroy_umem_out_bits { 11767 u8 status[0x8]; 11768 u8 reserved_at_8[0x18]; 11769 11770 u8 syndrome[0x20]; 11771 11772 u8 reserved_at_40[0x40]; 11773 }; 11774 11775 struct mlx5_ifc_create_uctx_in_bits { 11776 u8 opcode[0x10]; 11777 u8 reserved_at_10[0x10]; 11778 11779 u8 reserved_at_20[0x10]; 11780 u8 op_mod[0x10]; 11781 11782 u8 reserved_at_40[0x40]; 11783 11784 struct mlx5_ifc_uctx_bits uctx; 11785 }; 11786 11787 struct mlx5_ifc_create_uctx_out_bits { 11788 u8 status[0x8]; 11789 u8 reserved_at_8[0x18]; 11790 11791 u8 syndrome[0x20]; 11792 11793 u8 reserved_at_40[0x10]; 11794 u8 uid[0x10]; 11795 11796 u8 reserved_at_60[0x20]; 11797 }; 11798 11799 struct mlx5_ifc_destroy_uctx_in_bits { 11800 u8 opcode[0x10]; 11801 u8 reserved_at_10[0x10]; 11802 11803 u8 reserved_at_20[0x10]; 11804 u8 op_mod[0x10]; 11805 11806 u8 reserved_at_40[0x10]; 11807 u8 uid[0x10]; 11808 11809 u8 reserved_at_60[0x20]; 11810 }; 11811 11812 struct mlx5_ifc_destroy_uctx_out_bits { 11813 u8 status[0x8]; 11814 u8 reserved_at_8[0x18]; 11815 11816 u8 syndrome[0x20]; 11817 11818 u8 reserved_at_40[0x40]; 11819 }; 11820 11821 struct mlx5_ifc_create_sw_icm_in_bits { 11822 struct mlx5_ifc_general_obj_in_cmd_hdr_bits hdr; 11823 struct mlx5_ifc_sw_icm_bits sw_icm; 11824 }; 11825 11826 struct mlx5_ifc_create_geneve_tlv_option_in_bits { 11827 struct mlx5_ifc_general_obj_in_cmd_hdr_bits hdr; 11828 struct mlx5_ifc_geneve_tlv_option_bits geneve_tlv_opt; 11829 }; 11830 11831 struct mlx5_ifc_mtrc_string_db_param_bits { 11832 u8 string_db_base_address[0x20]; 11833 11834 u8 reserved_at_20[0x8]; 11835 u8 string_db_size[0x18]; 11836 }; 11837 11838 struct mlx5_ifc_mtrc_cap_bits { 11839 u8 trace_owner[0x1]; 11840 u8 trace_to_memory[0x1]; 11841 u8 reserved_at_2[0x4]; 11842 u8 trc_ver[0x2]; 11843 u8 reserved_at_8[0x14]; 11844 u8 num_string_db[0x4]; 11845 11846 u8 first_string_trace[0x8]; 11847 u8 num_string_trace[0x8]; 11848 u8 reserved_at_30[0x28]; 11849 11850 u8 log_max_trace_buffer_size[0x8]; 11851 11852 u8 reserved_at_60[0x20]; 11853 11854 struct mlx5_ifc_mtrc_string_db_param_bits string_db_param[8]; 11855 11856 u8 reserved_at_280[0x180]; 11857 }; 11858 11859 struct mlx5_ifc_mtrc_conf_bits { 11860 u8 reserved_at_0[0x1c]; 11861 u8 trace_mode[0x4]; 11862 u8 reserved_at_20[0x18]; 11863 u8 log_trace_buffer_size[0x8]; 11864 u8 trace_mkey[0x20]; 11865 u8 reserved_at_60[0x3a0]; 11866 }; 11867 11868 struct mlx5_ifc_mtrc_stdb_bits { 11869 u8 string_db_index[0x4]; 11870 u8 reserved_at_4[0x4]; 11871 u8 read_size[0x18]; 11872 u8 start_offset[0x20]; 11873 u8 string_db_data[]; 11874 }; 11875 11876 struct mlx5_ifc_mtrc_ctrl_bits { 11877 u8 trace_status[0x2]; 11878 u8 reserved_at_2[0x2]; 11879 u8 arm_event[0x1]; 11880 u8 reserved_at_5[0xb]; 11881 u8 modify_field_select[0x10]; 11882 u8 reserved_at_20[0x2b]; 11883 u8 current_timestamp52_32[0x15]; 11884 u8 current_timestamp31_0[0x20]; 11885 u8 reserved_at_80[0x180]; 11886 }; 11887 11888 struct mlx5_ifc_host_params_context_bits { 11889 u8 host_number[0x8]; 11890 u8 reserved_at_8[0x7]; 11891 u8 host_pf_disabled[0x1]; 11892 u8 host_num_of_vfs[0x10]; 11893 11894 u8 host_total_vfs[0x10]; 11895 u8 host_pci_bus[0x10]; 11896 11897 u8 reserved_at_40[0x10]; 11898 u8 host_pci_device[0x10]; 11899 11900 u8 reserved_at_60[0x10]; 11901 u8 host_pci_function[0x10]; 11902 11903 u8 reserved_at_80[0x180]; 11904 }; 11905 11906 struct mlx5_ifc_query_esw_functions_in_bits { 11907 u8 opcode[0x10]; 11908 u8 reserved_at_10[0x10]; 11909 11910 u8 reserved_at_20[0x10]; 11911 u8 op_mod[0x10]; 11912 11913 u8 reserved_at_40[0x40]; 11914 }; 11915 11916 struct mlx5_ifc_query_esw_functions_out_bits { 11917 u8 status[0x8]; 11918 u8 reserved_at_8[0x18]; 11919 11920 u8 syndrome[0x20]; 11921 11922 u8 reserved_at_40[0x40]; 11923 11924 struct mlx5_ifc_host_params_context_bits host_params_context; 11925 11926 u8 reserved_at_280[0x180]; 11927 u8 host_sf_enable[][0x40]; 11928 }; 11929 11930 struct mlx5_ifc_sf_partition_bits { 11931 u8 reserved_at_0[0x10]; 11932 u8 log_num_sf[0x8]; 11933 u8 log_sf_bar_size[0x8]; 11934 }; 11935 11936 struct mlx5_ifc_query_sf_partitions_out_bits { 11937 u8 status[0x8]; 11938 u8 reserved_at_8[0x18]; 11939 11940 u8 syndrome[0x20]; 11941 11942 u8 reserved_at_40[0x18]; 11943 u8 num_sf_partitions[0x8]; 11944 11945 u8 reserved_at_60[0x20]; 11946 11947 struct mlx5_ifc_sf_partition_bits sf_partition[]; 11948 }; 11949 11950 struct mlx5_ifc_query_sf_partitions_in_bits { 11951 u8 opcode[0x10]; 11952 u8 reserved_at_10[0x10]; 11953 11954 u8 reserved_at_20[0x10]; 11955 u8 op_mod[0x10]; 11956 11957 u8 reserved_at_40[0x40]; 11958 }; 11959 11960 struct mlx5_ifc_dealloc_sf_out_bits { 11961 u8 status[0x8]; 11962 u8 reserved_at_8[0x18]; 11963 11964 u8 syndrome[0x20]; 11965 11966 u8 reserved_at_40[0x40]; 11967 }; 11968 11969 struct mlx5_ifc_dealloc_sf_in_bits { 11970 u8 opcode[0x10]; 11971 u8 reserved_at_10[0x10]; 11972 11973 u8 reserved_at_20[0x10]; 11974 u8 op_mod[0x10]; 11975 11976 u8 reserved_at_40[0x10]; 11977 u8 function_id[0x10]; 11978 11979 u8 reserved_at_60[0x20]; 11980 }; 11981 11982 struct mlx5_ifc_alloc_sf_out_bits { 11983 u8 status[0x8]; 11984 u8 reserved_at_8[0x18]; 11985 11986 u8 syndrome[0x20]; 11987 11988 u8 reserved_at_40[0x40]; 11989 }; 11990 11991 struct mlx5_ifc_alloc_sf_in_bits { 11992 u8 opcode[0x10]; 11993 u8 reserved_at_10[0x10]; 11994 11995 u8 reserved_at_20[0x10]; 11996 u8 op_mod[0x10]; 11997 11998 u8 reserved_at_40[0x10]; 11999 u8 function_id[0x10]; 12000 12001 u8 reserved_at_60[0x20]; 12002 }; 12003 12004 struct mlx5_ifc_affiliated_event_header_bits { 12005 u8 reserved_at_0[0x10]; 12006 u8 obj_type[0x10]; 12007 12008 u8 obj_id[0x20]; 12009 }; 12010 12011 enum { 12012 MLX5_HCA_CAP_GENERAL_OBJECT_TYPES_ENCRYPTION_KEY = BIT_ULL(0xc), 12013 MLX5_HCA_CAP_GENERAL_OBJECT_TYPES_IPSEC = BIT_ULL(0x13), 12014 MLX5_HCA_CAP_GENERAL_OBJECT_TYPES_SAMPLER = BIT_ULL(0x20), 12015 MLX5_HCA_CAP_GENERAL_OBJECT_TYPES_FLOW_METER_ASO = BIT_ULL(0x24), 12016 }; 12017 12018 enum { 12019 MLX5_GENERAL_OBJECT_TYPES_ENCRYPTION_KEY = 0xc, 12020 MLX5_GENERAL_OBJECT_TYPES_IPSEC = 0x13, 12021 MLX5_GENERAL_OBJECT_TYPES_SAMPLER = 0x20, 12022 MLX5_GENERAL_OBJECT_TYPES_FLOW_METER_ASO = 0x24, 12023 MLX5_GENERAL_OBJECT_TYPES_MACSEC = 0x27, 12024 MLX5_GENERAL_OBJECT_TYPES_INT_KEK = 0x47, 12025 MLX5_GENERAL_OBJECT_TYPES_FLOW_TABLE_ALIAS = 0xff15, 12026 }; 12027 12028 enum { 12029 MLX5_IPSEC_OBJECT_ICV_LEN_16B, 12030 }; 12031 12032 enum { 12033 MLX5_IPSEC_ASO_REG_C_0_1 = 0x0, 12034 MLX5_IPSEC_ASO_REG_C_2_3 = 0x1, 12035 MLX5_IPSEC_ASO_REG_C_4_5 = 0x2, 12036 MLX5_IPSEC_ASO_REG_C_6_7 = 0x3, 12037 }; 12038 12039 enum { 12040 MLX5_IPSEC_ASO_MODE = 0x0, 12041 MLX5_IPSEC_ASO_REPLAY_PROTECTION = 0x1, 12042 MLX5_IPSEC_ASO_INC_SN = 0x2, 12043 }; 12044 12045 enum { 12046 MLX5_IPSEC_ASO_REPLAY_WIN_32BIT = 0x0, 12047 MLX5_IPSEC_ASO_REPLAY_WIN_64BIT = 0x1, 12048 MLX5_IPSEC_ASO_REPLAY_WIN_128BIT = 0x2, 12049 MLX5_IPSEC_ASO_REPLAY_WIN_256BIT = 0x3, 12050 }; 12051 12052 struct mlx5_ifc_ipsec_aso_bits { 12053 u8 valid[0x1]; 12054 u8 reserved_at_201[0x1]; 12055 u8 mode[0x2]; 12056 u8 window_sz[0x2]; 12057 u8 soft_lft_arm[0x1]; 12058 u8 hard_lft_arm[0x1]; 12059 u8 remove_flow_enable[0x1]; 12060 u8 esn_event_arm[0x1]; 12061 u8 reserved_at_20a[0x16]; 12062 12063 u8 remove_flow_pkt_cnt[0x20]; 12064 12065 u8 remove_flow_soft_lft[0x20]; 12066 12067 u8 reserved_at_260[0x80]; 12068 12069 u8 mode_parameter[0x20]; 12070 12071 u8 replay_protection_window[0x100]; 12072 }; 12073 12074 struct mlx5_ifc_ipsec_obj_bits { 12075 u8 modify_field_select[0x40]; 12076 u8 full_offload[0x1]; 12077 u8 reserved_at_41[0x1]; 12078 u8 esn_en[0x1]; 12079 u8 esn_overlap[0x1]; 12080 u8 reserved_at_44[0x2]; 12081 u8 icv_length[0x2]; 12082 u8 reserved_at_48[0x4]; 12083 u8 aso_return_reg[0x4]; 12084 u8 reserved_at_50[0x10]; 12085 12086 u8 esn_msb[0x20]; 12087 12088 u8 reserved_at_80[0x8]; 12089 u8 dekn[0x18]; 12090 12091 u8 salt[0x20]; 12092 12093 u8 implicit_iv[0x40]; 12094 12095 u8 reserved_at_100[0x8]; 12096 u8 ipsec_aso_access_pd[0x18]; 12097 u8 reserved_at_120[0xe0]; 12098 12099 struct mlx5_ifc_ipsec_aso_bits ipsec_aso; 12100 }; 12101 12102 struct mlx5_ifc_create_ipsec_obj_in_bits { 12103 struct mlx5_ifc_general_obj_in_cmd_hdr_bits general_obj_in_cmd_hdr; 12104 struct mlx5_ifc_ipsec_obj_bits ipsec_object; 12105 }; 12106 12107 enum { 12108 MLX5_MODIFY_IPSEC_BITMASK_ESN_OVERLAP = BIT(0), 12109 MLX5_MODIFY_IPSEC_BITMASK_ESN_MSB = BIT(1), 12110 }; 12111 12112 struct mlx5_ifc_query_ipsec_obj_out_bits { 12113 struct mlx5_ifc_general_obj_out_cmd_hdr_bits general_obj_out_cmd_hdr; 12114 struct mlx5_ifc_ipsec_obj_bits ipsec_object; 12115 }; 12116 12117 struct mlx5_ifc_modify_ipsec_obj_in_bits { 12118 struct mlx5_ifc_general_obj_in_cmd_hdr_bits general_obj_in_cmd_hdr; 12119 struct mlx5_ifc_ipsec_obj_bits ipsec_object; 12120 }; 12121 12122 enum { 12123 MLX5_MACSEC_ASO_REPLAY_PROTECTION = 0x1, 12124 }; 12125 12126 enum { 12127 MLX5_MACSEC_ASO_REPLAY_WIN_32BIT = 0x0, 12128 MLX5_MACSEC_ASO_REPLAY_WIN_64BIT = 0x1, 12129 MLX5_MACSEC_ASO_REPLAY_WIN_128BIT = 0x2, 12130 MLX5_MACSEC_ASO_REPLAY_WIN_256BIT = 0x3, 12131 }; 12132 12133 #define MLX5_MACSEC_ASO_INC_SN 0x2 12134 #define MLX5_MACSEC_ASO_REG_C_4_5 0x2 12135 12136 struct mlx5_ifc_macsec_aso_bits { 12137 u8 valid[0x1]; 12138 u8 reserved_at_1[0x1]; 12139 u8 mode[0x2]; 12140 u8 window_size[0x2]; 12141 u8 soft_lifetime_arm[0x1]; 12142 u8 hard_lifetime_arm[0x1]; 12143 u8 remove_flow_enable[0x1]; 12144 u8 epn_event_arm[0x1]; 12145 u8 reserved_at_a[0x16]; 12146 12147 u8 remove_flow_packet_count[0x20]; 12148 12149 u8 remove_flow_soft_lifetime[0x20]; 12150 12151 u8 reserved_at_60[0x80]; 12152 12153 u8 mode_parameter[0x20]; 12154 12155 u8 replay_protection_window[8][0x20]; 12156 }; 12157 12158 struct mlx5_ifc_macsec_offload_obj_bits { 12159 u8 modify_field_select[0x40]; 12160 12161 u8 confidentiality_en[0x1]; 12162 u8 reserved_at_41[0x1]; 12163 u8 epn_en[0x1]; 12164 u8 epn_overlap[0x1]; 12165 u8 reserved_at_44[0x2]; 12166 u8 confidentiality_offset[0x2]; 12167 u8 reserved_at_48[0x4]; 12168 u8 aso_return_reg[0x4]; 12169 u8 reserved_at_50[0x10]; 12170 12171 u8 epn_msb[0x20]; 12172 12173 u8 reserved_at_80[0x8]; 12174 u8 dekn[0x18]; 12175 12176 u8 reserved_at_a0[0x20]; 12177 12178 u8 sci[0x40]; 12179 12180 u8 reserved_at_100[0x8]; 12181 u8 macsec_aso_access_pd[0x18]; 12182 12183 u8 reserved_at_120[0x60]; 12184 12185 u8 salt[3][0x20]; 12186 12187 u8 reserved_at_1e0[0x20]; 12188 12189 struct mlx5_ifc_macsec_aso_bits macsec_aso; 12190 }; 12191 12192 struct mlx5_ifc_create_macsec_obj_in_bits { 12193 struct mlx5_ifc_general_obj_in_cmd_hdr_bits general_obj_in_cmd_hdr; 12194 struct mlx5_ifc_macsec_offload_obj_bits macsec_object; 12195 }; 12196 12197 struct mlx5_ifc_modify_macsec_obj_in_bits { 12198 struct mlx5_ifc_general_obj_in_cmd_hdr_bits general_obj_in_cmd_hdr; 12199 struct mlx5_ifc_macsec_offload_obj_bits macsec_object; 12200 }; 12201 12202 enum { 12203 MLX5_MODIFY_MACSEC_BITMASK_EPN_OVERLAP = BIT(0), 12204 MLX5_MODIFY_MACSEC_BITMASK_EPN_MSB = BIT(1), 12205 }; 12206 12207 struct mlx5_ifc_query_macsec_obj_out_bits { 12208 struct mlx5_ifc_general_obj_out_cmd_hdr_bits general_obj_out_cmd_hdr; 12209 struct mlx5_ifc_macsec_offload_obj_bits macsec_object; 12210 }; 12211 12212 struct mlx5_ifc_wrapped_dek_bits { 12213 u8 gcm_iv[0x60]; 12214 12215 u8 reserved_at_60[0x20]; 12216 12217 u8 const0[0x1]; 12218 u8 key_size[0x1]; 12219 u8 reserved_at_82[0x2]; 12220 u8 key2_invalid[0x1]; 12221 u8 reserved_at_85[0x3]; 12222 u8 pd[0x18]; 12223 12224 u8 key_purpose[0x5]; 12225 u8 reserved_at_a5[0x13]; 12226 u8 kek_id[0x8]; 12227 12228 u8 reserved_at_c0[0x40]; 12229 12230 u8 key1[0x8][0x20]; 12231 12232 u8 key2[0x8][0x20]; 12233 12234 u8 reserved_at_300[0x40]; 12235 12236 u8 const1[0x1]; 12237 u8 reserved_at_341[0x1f]; 12238 12239 u8 reserved_at_360[0x20]; 12240 12241 u8 auth_tag[0x80]; 12242 }; 12243 12244 struct mlx5_ifc_encryption_key_obj_bits { 12245 u8 modify_field_select[0x40]; 12246 12247 u8 state[0x8]; 12248 u8 sw_wrapped[0x1]; 12249 u8 reserved_at_49[0xb]; 12250 u8 key_size[0x4]; 12251 u8 reserved_at_58[0x4]; 12252 u8 key_purpose[0x4]; 12253 12254 u8 reserved_at_60[0x8]; 12255 u8 pd[0x18]; 12256 12257 u8 reserved_at_80[0x100]; 12258 12259 u8 opaque[0x40]; 12260 12261 u8 reserved_at_1c0[0x40]; 12262 12263 u8 key[8][0x80]; 12264 12265 u8 sw_wrapped_dek[8][0x80]; 12266 12267 u8 reserved_at_a00[0x600]; 12268 }; 12269 12270 struct mlx5_ifc_create_encryption_key_in_bits { 12271 struct mlx5_ifc_general_obj_in_cmd_hdr_bits general_obj_in_cmd_hdr; 12272 struct mlx5_ifc_encryption_key_obj_bits encryption_key_object; 12273 }; 12274 12275 struct mlx5_ifc_modify_encryption_key_in_bits { 12276 struct mlx5_ifc_general_obj_in_cmd_hdr_bits general_obj_in_cmd_hdr; 12277 struct mlx5_ifc_encryption_key_obj_bits encryption_key_object; 12278 }; 12279 12280 enum { 12281 MLX5_FLOW_METER_MODE_BYTES_IP_LENGTH = 0x0, 12282 MLX5_FLOW_METER_MODE_BYTES_CALC_WITH_L2 = 0x1, 12283 MLX5_FLOW_METER_MODE_BYTES_CALC_WITH_L2_IPG = 0x2, 12284 MLX5_FLOW_METER_MODE_NUM_PACKETS = 0x3, 12285 }; 12286 12287 struct mlx5_ifc_flow_meter_parameters_bits { 12288 u8 valid[0x1]; 12289 u8 bucket_overflow[0x1]; 12290 u8 start_color[0x2]; 12291 u8 both_buckets_on_green[0x1]; 12292 u8 reserved_at_5[0x1]; 12293 u8 meter_mode[0x2]; 12294 u8 reserved_at_8[0x18]; 12295 12296 u8 reserved_at_20[0x20]; 12297 12298 u8 reserved_at_40[0x3]; 12299 u8 cbs_exponent[0x5]; 12300 u8 cbs_mantissa[0x8]; 12301 u8 reserved_at_50[0x3]; 12302 u8 cir_exponent[0x5]; 12303 u8 cir_mantissa[0x8]; 12304 12305 u8 reserved_at_60[0x20]; 12306 12307 u8 reserved_at_80[0x3]; 12308 u8 ebs_exponent[0x5]; 12309 u8 ebs_mantissa[0x8]; 12310 u8 reserved_at_90[0x3]; 12311 u8 eir_exponent[0x5]; 12312 u8 eir_mantissa[0x8]; 12313 12314 u8 reserved_at_a0[0x60]; 12315 }; 12316 12317 struct mlx5_ifc_flow_meter_aso_obj_bits { 12318 u8 modify_field_select[0x40]; 12319 12320 u8 reserved_at_40[0x40]; 12321 12322 u8 reserved_at_80[0x8]; 12323 u8 meter_aso_access_pd[0x18]; 12324 12325 u8 reserved_at_a0[0x160]; 12326 12327 struct mlx5_ifc_flow_meter_parameters_bits flow_meter_parameters[2]; 12328 }; 12329 12330 struct mlx5_ifc_create_flow_meter_aso_obj_in_bits { 12331 struct mlx5_ifc_general_obj_in_cmd_hdr_bits hdr; 12332 struct mlx5_ifc_flow_meter_aso_obj_bits flow_meter_aso_obj; 12333 }; 12334 12335 struct mlx5_ifc_int_kek_obj_bits { 12336 u8 modify_field_select[0x40]; 12337 12338 u8 state[0x8]; 12339 u8 auto_gen[0x1]; 12340 u8 reserved_at_49[0xb]; 12341 u8 key_size[0x4]; 12342 u8 reserved_at_58[0x8]; 12343 12344 u8 reserved_at_60[0x8]; 12345 u8 pd[0x18]; 12346 12347 u8 reserved_at_80[0x180]; 12348 u8 key[8][0x80]; 12349 12350 u8 reserved_at_600[0x200]; 12351 }; 12352 12353 struct mlx5_ifc_create_int_kek_obj_in_bits { 12354 struct mlx5_ifc_general_obj_in_cmd_hdr_bits general_obj_in_cmd_hdr; 12355 struct mlx5_ifc_int_kek_obj_bits int_kek_object; 12356 }; 12357 12358 struct mlx5_ifc_create_int_kek_obj_out_bits { 12359 struct mlx5_ifc_general_obj_out_cmd_hdr_bits general_obj_out_cmd_hdr; 12360 struct mlx5_ifc_int_kek_obj_bits int_kek_object; 12361 }; 12362 12363 struct mlx5_ifc_sampler_obj_bits { 12364 u8 modify_field_select[0x40]; 12365 12366 u8 table_type[0x8]; 12367 u8 level[0x8]; 12368 u8 reserved_at_50[0xf]; 12369 u8 ignore_flow_level[0x1]; 12370 12371 u8 sample_ratio[0x20]; 12372 12373 u8 reserved_at_80[0x8]; 12374 u8 sample_table_id[0x18]; 12375 12376 u8 reserved_at_a0[0x8]; 12377 u8 default_table_id[0x18]; 12378 12379 u8 sw_steering_icm_address_rx[0x40]; 12380 u8 sw_steering_icm_address_tx[0x40]; 12381 12382 u8 reserved_at_140[0xa0]; 12383 }; 12384 12385 struct mlx5_ifc_create_sampler_obj_in_bits { 12386 struct mlx5_ifc_general_obj_in_cmd_hdr_bits general_obj_in_cmd_hdr; 12387 struct mlx5_ifc_sampler_obj_bits sampler_object; 12388 }; 12389 12390 struct mlx5_ifc_query_sampler_obj_out_bits { 12391 struct mlx5_ifc_general_obj_out_cmd_hdr_bits general_obj_out_cmd_hdr; 12392 struct mlx5_ifc_sampler_obj_bits sampler_object; 12393 }; 12394 12395 enum { 12396 MLX5_GENERAL_OBJECT_TYPE_ENCRYPTION_KEY_KEY_SIZE_128 = 0x0, 12397 MLX5_GENERAL_OBJECT_TYPE_ENCRYPTION_KEY_KEY_SIZE_256 = 0x1, 12398 }; 12399 12400 enum { 12401 MLX5_GENERAL_OBJECT_TYPE_ENCRYPTION_KEY_PURPOSE_TLS = 0x1, 12402 MLX5_GENERAL_OBJECT_TYPE_ENCRYPTION_KEY_PURPOSE_IPSEC = 0x2, 12403 MLX5_GENERAL_OBJECT_TYPE_ENCRYPTION_KEY_PURPOSE_MACSEC = 0x4, 12404 }; 12405 12406 struct mlx5_ifc_tls_static_params_bits { 12407 u8 const_2[0x2]; 12408 u8 tls_version[0x4]; 12409 u8 const_1[0x2]; 12410 u8 reserved_at_8[0x14]; 12411 u8 encryption_standard[0x4]; 12412 12413 u8 reserved_at_20[0x20]; 12414 12415 u8 initial_record_number[0x40]; 12416 12417 u8 resync_tcp_sn[0x20]; 12418 12419 u8 gcm_iv[0x20]; 12420 12421 u8 implicit_iv[0x40]; 12422 12423 u8 reserved_at_100[0x8]; 12424 u8 dek_index[0x18]; 12425 12426 u8 reserved_at_120[0xe0]; 12427 }; 12428 12429 struct mlx5_ifc_tls_progress_params_bits { 12430 u8 next_record_tcp_sn[0x20]; 12431 12432 u8 hw_resync_tcp_sn[0x20]; 12433 12434 u8 record_tracker_state[0x2]; 12435 u8 auth_state[0x2]; 12436 u8 reserved_at_44[0x4]; 12437 u8 hw_offset_record_number[0x18]; 12438 }; 12439 12440 enum { 12441 MLX5_MTT_PERM_READ = 1 << 0, 12442 MLX5_MTT_PERM_WRITE = 1 << 1, 12443 MLX5_MTT_PERM_RW = MLX5_MTT_PERM_READ | MLX5_MTT_PERM_WRITE, 12444 }; 12445 12446 enum { 12447 MLX5_SUSPEND_VHCA_IN_OP_MOD_SUSPEND_INITIATOR = 0x0, 12448 MLX5_SUSPEND_VHCA_IN_OP_MOD_SUSPEND_RESPONDER = 0x1, 12449 }; 12450 12451 struct mlx5_ifc_suspend_vhca_in_bits { 12452 u8 opcode[0x10]; 12453 u8 uid[0x10]; 12454 12455 u8 reserved_at_20[0x10]; 12456 u8 op_mod[0x10]; 12457 12458 u8 reserved_at_40[0x10]; 12459 u8 vhca_id[0x10]; 12460 12461 u8 reserved_at_60[0x20]; 12462 }; 12463 12464 struct mlx5_ifc_suspend_vhca_out_bits { 12465 u8 status[0x8]; 12466 u8 reserved_at_8[0x18]; 12467 12468 u8 syndrome[0x20]; 12469 12470 u8 reserved_at_40[0x40]; 12471 }; 12472 12473 enum { 12474 MLX5_RESUME_VHCA_IN_OP_MOD_RESUME_RESPONDER = 0x0, 12475 MLX5_RESUME_VHCA_IN_OP_MOD_RESUME_INITIATOR = 0x1, 12476 }; 12477 12478 struct mlx5_ifc_resume_vhca_in_bits { 12479 u8 opcode[0x10]; 12480 u8 uid[0x10]; 12481 12482 u8 reserved_at_20[0x10]; 12483 u8 op_mod[0x10]; 12484 12485 u8 reserved_at_40[0x10]; 12486 u8 vhca_id[0x10]; 12487 12488 u8 reserved_at_60[0x20]; 12489 }; 12490 12491 struct mlx5_ifc_resume_vhca_out_bits { 12492 u8 status[0x8]; 12493 u8 reserved_at_8[0x18]; 12494 12495 u8 syndrome[0x20]; 12496 12497 u8 reserved_at_40[0x40]; 12498 }; 12499 12500 struct mlx5_ifc_query_vhca_migration_state_in_bits { 12501 u8 opcode[0x10]; 12502 u8 uid[0x10]; 12503 12504 u8 reserved_at_20[0x10]; 12505 u8 op_mod[0x10]; 12506 12507 u8 incremental[0x1]; 12508 u8 chunk[0x1]; 12509 u8 reserved_at_42[0xe]; 12510 u8 vhca_id[0x10]; 12511 12512 u8 reserved_at_60[0x20]; 12513 }; 12514 12515 struct mlx5_ifc_query_vhca_migration_state_out_bits { 12516 u8 status[0x8]; 12517 u8 reserved_at_8[0x18]; 12518 12519 u8 syndrome[0x20]; 12520 12521 u8 reserved_at_40[0x40]; 12522 12523 u8 required_umem_size[0x20]; 12524 12525 u8 reserved_at_a0[0x20]; 12526 12527 u8 remaining_total_size[0x40]; 12528 12529 u8 reserved_at_100[0x100]; 12530 }; 12531 12532 struct mlx5_ifc_save_vhca_state_in_bits { 12533 u8 opcode[0x10]; 12534 u8 uid[0x10]; 12535 12536 u8 reserved_at_20[0x10]; 12537 u8 op_mod[0x10]; 12538 12539 u8 incremental[0x1]; 12540 u8 set_track[0x1]; 12541 u8 reserved_at_42[0xe]; 12542 u8 vhca_id[0x10]; 12543 12544 u8 reserved_at_60[0x20]; 12545 12546 u8 va[0x40]; 12547 12548 u8 mkey[0x20]; 12549 12550 u8 size[0x20]; 12551 }; 12552 12553 struct mlx5_ifc_save_vhca_state_out_bits { 12554 u8 status[0x8]; 12555 u8 reserved_at_8[0x18]; 12556 12557 u8 syndrome[0x20]; 12558 12559 u8 actual_image_size[0x20]; 12560 12561 u8 next_required_umem_size[0x20]; 12562 }; 12563 12564 struct mlx5_ifc_load_vhca_state_in_bits { 12565 u8 opcode[0x10]; 12566 u8 uid[0x10]; 12567 12568 u8 reserved_at_20[0x10]; 12569 u8 op_mod[0x10]; 12570 12571 u8 reserved_at_40[0x10]; 12572 u8 vhca_id[0x10]; 12573 12574 u8 reserved_at_60[0x20]; 12575 12576 u8 va[0x40]; 12577 12578 u8 mkey[0x20]; 12579 12580 u8 size[0x20]; 12581 }; 12582 12583 struct mlx5_ifc_load_vhca_state_out_bits { 12584 u8 status[0x8]; 12585 u8 reserved_at_8[0x18]; 12586 12587 u8 syndrome[0x20]; 12588 12589 u8 reserved_at_40[0x40]; 12590 }; 12591 12592 struct mlx5_ifc_adv_virtualization_cap_bits { 12593 u8 reserved_at_0[0x3]; 12594 u8 pg_track_log_max_num[0x5]; 12595 u8 pg_track_max_num_range[0x8]; 12596 u8 pg_track_log_min_addr_space[0x8]; 12597 u8 pg_track_log_max_addr_space[0x8]; 12598 12599 u8 reserved_at_20[0x3]; 12600 u8 pg_track_log_min_msg_size[0x5]; 12601 u8 reserved_at_28[0x3]; 12602 u8 pg_track_log_max_msg_size[0x5]; 12603 u8 reserved_at_30[0x3]; 12604 u8 pg_track_log_min_page_size[0x5]; 12605 u8 reserved_at_38[0x3]; 12606 u8 pg_track_log_max_page_size[0x5]; 12607 12608 u8 reserved_at_40[0x7c0]; 12609 }; 12610 12611 struct mlx5_ifc_page_track_report_entry_bits { 12612 u8 dirty_address_high[0x20]; 12613 12614 u8 dirty_address_low[0x20]; 12615 }; 12616 12617 enum { 12618 MLX5_PAGE_TRACK_STATE_TRACKING, 12619 MLX5_PAGE_TRACK_STATE_REPORTING, 12620 MLX5_PAGE_TRACK_STATE_ERROR, 12621 }; 12622 12623 struct mlx5_ifc_page_track_range_bits { 12624 u8 start_address[0x40]; 12625 12626 u8 length[0x40]; 12627 }; 12628 12629 struct mlx5_ifc_page_track_bits { 12630 u8 modify_field_select[0x40]; 12631 12632 u8 reserved_at_40[0x10]; 12633 u8 vhca_id[0x10]; 12634 12635 u8 reserved_at_60[0x20]; 12636 12637 u8 state[0x4]; 12638 u8 track_type[0x4]; 12639 u8 log_addr_space_size[0x8]; 12640 u8 reserved_at_90[0x3]; 12641 u8 log_page_size[0x5]; 12642 u8 reserved_at_98[0x3]; 12643 u8 log_msg_size[0x5]; 12644 12645 u8 reserved_at_a0[0x8]; 12646 u8 reporting_qpn[0x18]; 12647 12648 u8 reserved_at_c0[0x18]; 12649 u8 num_ranges[0x8]; 12650 12651 u8 reserved_at_e0[0x20]; 12652 12653 u8 range_start_address[0x40]; 12654 12655 u8 length[0x40]; 12656 12657 struct mlx5_ifc_page_track_range_bits track_range[0]; 12658 }; 12659 12660 struct mlx5_ifc_create_page_track_obj_in_bits { 12661 struct mlx5_ifc_general_obj_in_cmd_hdr_bits general_obj_in_cmd_hdr; 12662 struct mlx5_ifc_page_track_bits obj_context; 12663 }; 12664 12665 struct mlx5_ifc_modify_page_track_obj_in_bits { 12666 struct mlx5_ifc_general_obj_in_cmd_hdr_bits general_obj_in_cmd_hdr; 12667 struct mlx5_ifc_page_track_bits obj_context; 12668 }; 12669 12670 struct mlx5_ifc_msecq_reg_bits { 12671 u8 reserved_at_0[0x20]; 12672 12673 u8 reserved_at_20[0x12]; 12674 u8 network_option[0x2]; 12675 u8 local_ssm_code[0x4]; 12676 u8 local_enhanced_ssm_code[0x8]; 12677 12678 u8 local_clock_identity[0x40]; 12679 12680 u8 reserved_at_80[0x180]; 12681 }; 12682 12683 enum { 12684 MLX5_MSEES_FIELD_SELECT_ENABLE = BIT(0), 12685 MLX5_MSEES_FIELD_SELECT_ADMIN_STATUS = BIT(1), 12686 MLX5_MSEES_FIELD_SELECT_ADMIN_FREQ_MEASURE = BIT(2), 12687 }; 12688 12689 enum mlx5_msees_admin_status { 12690 MLX5_MSEES_ADMIN_STATUS_FREE_RUNNING = 0x0, 12691 MLX5_MSEES_ADMIN_STATUS_TRACK = 0x1, 12692 }; 12693 12694 enum mlx5_msees_oper_status { 12695 MLX5_MSEES_OPER_STATUS_FREE_RUNNING = 0x0, 12696 MLX5_MSEES_OPER_STATUS_SELF_TRACK = 0x1, 12697 MLX5_MSEES_OPER_STATUS_OTHER_TRACK = 0x2, 12698 MLX5_MSEES_OPER_STATUS_HOLDOVER = 0x3, 12699 MLX5_MSEES_OPER_STATUS_FAIL_HOLDOVER = 0x4, 12700 MLX5_MSEES_OPER_STATUS_FAIL_FREE_RUNNING = 0x5, 12701 }; 12702 12703 struct mlx5_ifc_msees_reg_bits { 12704 u8 reserved_at_0[0x8]; 12705 u8 local_port[0x8]; 12706 u8 pnat[0x2]; 12707 u8 lp_msb[0x2]; 12708 u8 reserved_at_14[0xc]; 12709 12710 u8 field_select[0x20]; 12711 12712 u8 admin_status[0x4]; 12713 u8 oper_status[0x4]; 12714 u8 ho_acq[0x1]; 12715 u8 reserved_at_49[0xc]; 12716 u8 admin_freq_measure[0x1]; 12717 u8 oper_freq_measure[0x1]; 12718 u8 failure_reason[0x9]; 12719 12720 u8 frequency_diff[0x20]; 12721 12722 u8 reserved_at_80[0x180]; 12723 }; 12724 12725 #endif /* MLX5_IFC_H */ 12726