1 /* 2 * Copyright (c) 2013-2015, Mellanox Technologies, Ltd. All rights reserved. 3 * 4 * This software is available to you under a choice of one of two 5 * licenses. You may choose to be licensed under the terms of the GNU 6 * General Public License (GPL) Version 2, available from the file 7 * COPYING in the main directory of this source tree, or the 8 * OpenIB.org BSD license below: 9 * 10 * Redistribution and use in source and binary forms, with or 11 * without modification, are permitted provided that the following 12 * conditions are met: 13 * 14 * - Redistributions of source code must retain the above 15 * copyright notice, this list of conditions and the following 16 * disclaimer. 17 * 18 * - Redistributions in binary form must reproduce the above 19 * copyright notice, this list of conditions and the following 20 * disclaimer in the documentation and/or other materials 21 * provided with the distribution. 22 * 23 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, 24 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF 25 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND 26 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS 27 * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN 28 * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN 29 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE 30 * SOFTWARE. 31 */ 32 #ifndef MLX5_IFC_H 33 #define MLX5_IFC_H 34 35 #include "mlx5_ifc_fpga.h" 36 37 enum { 38 MLX5_EVENT_TYPE_CODING_COMPLETION_EVENTS = 0x0, 39 MLX5_EVENT_TYPE_CODING_PATH_MIGRATED_SUCCEEDED = 0x1, 40 MLX5_EVENT_TYPE_CODING_COMMUNICATION_ESTABLISHED = 0x2, 41 MLX5_EVENT_TYPE_CODING_SEND_QUEUE_DRAINED = 0x3, 42 MLX5_EVENT_TYPE_CODING_LAST_WQE_REACHED = 0x13, 43 MLX5_EVENT_TYPE_CODING_SRQ_LIMIT = 0x14, 44 MLX5_EVENT_TYPE_CODING_DCT_ALL_CONNECTIONS_CLOSED = 0x1c, 45 MLX5_EVENT_TYPE_CODING_DCT_ACCESS_KEY_VIOLATION = 0x1d, 46 MLX5_EVENT_TYPE_CODING_CQ_ERROR = 0x4, 47 MLX5_EVENT_TYPE_CODING_LOCAL_WQ_CATASTROPHIC_ERROR = 0x5, 48 MLX5_EVENT_TYPE_CODING_PATH_MIGRATION_FAILED = 0x7, 49 MLX5_EVENT_TYPE_CODING_PAGE_FAULT_EVENT = 0xc, 50 MLX5_EVENT_TYPE_CODING_INVALID_REQUEST_LOCAL_WQ_ERROR = 0x10, 51 MLX5_EVENT_TYPE_CODING_LOCAL_ACCESS_VIOLATION_WQ_ERROR = 0x11, 52 MLX5_EVENT_TYPE_CODING_LOCAL_SRQ_CATASTROPHIC_ERROR = 0x12, 53 MLX5_EVENT_TYPE_CODING_INTERNAL_ERROR = 0x8, 54 MLX5_EVENT_TYPE_CODING_PORT_STATE_CHANGE = 0x9, 55 MLX5_EVENT_TYPE_CODING_GPIO_EVENT = 0x15, 56 MLX5_EVENT_TYPE_CODING_REMOTE_CONFIGURATION_PROTOCOL_EVENT = 0x19, 57 MLX5_EVENT_TYPE_CODING_DOORBELL_BLUEFLAME_CONGESTION_EVENT = 0x1a, 58 MLX5_EVENT_TYPE_CODING_STALL_VL_EVENT = 0x1b, 59 MLX5_EVENT_TYPE_CODING_DROPPED_PACKET_LOGGED_EVENT = 0x1f, 60 MLX5_EVENT_TYPE_CODING_COMMAND_INTERFACE_COMPLETION = 0xa, 61 MLX5_EVENT_TYPE_CODING_PAGE_REQUEST = 0xb, 62 MLX5_EVENT_TYPE_CODING_FPGA_ERROR = 0x20, 63 MLX5_EVENT_TYPE_CODING_FPGA_QP_ERROR = 0x21 64 }; 65 66 enum { 67 MLX5_MODIFY_TIR_BITMASK_LRO = 0x0, 68 MLX5_MODIFY_TIR_BITMASK_INDIRECT_TABLE = 0x1, 69 MLX5_MODIFY_TIR_BITMASK_HASH = 0x2, 70 MLX5_MODIFY_TIR_BITMASK_TUNNELED_OFFLOAD_EN = 0x3 71 }; 72 73 enum { 74 MLX5_SET_HCA_CAP_OP_MOD_GENERAL_DEVICE = 0x0, 75 MLX5_SET_HCA_CAP_OP_MOD_ATOMIC = 0x3, 76 }; 77 78 enum { 79 MLX5_GENERAL_OBJ_TYPES_CAP_UCTX = (1ULL << 4), 80 MLX5_GENERAL_OBJ_TYPES_CAP_UMEM = (1ULL << 5), 81 }; 82 83 enum { 84 MLX5_OBJ_TYPE_UCTX = 0x0004, 85 MLX5_OBJ_TYPE_UMEM = 0x0005, 86 }; 87 88 enum { 89 MLX5_CMD_OP_QUERY_HCA_CAP = 0x100, 90 MLX5_CMD_OP_QUERY_ADAPTER = 0x101, 91 MLX5_CMD_OP_INIT_HCA = 0x102, 92 MLX5_CMD_OP_TEARDOWN_HCA = 0x103, 93 MLX5_CMD_OP_ENABLE_HCA = 0x104, 94 MLX5_CMD_OP_DISABLE_HCA = 0x105, 95 MLX5_CMD_OP_QUERY_PAGES = 0x107, 96 MLX5_CMD_OP_MANAGE_PAGES = 0x108, 97 MLX5_CMD_OP_SET_HCA_CAP = 0x109, 98 MLX5_CMD_OP_QUERY_ISSI = 0x10a, 99 MLX5_CMD_OP_SET_ISSI = 0x10b, 100 MLX5_CMD_OP_SET_DRIVER_VERSION = 0x10d, 101 MLX5_CMD_OP_CREATE_MKEY = 0x200, 102 MLX5_CMD_OP_QUERY_MKEY = 0x201, 103 MLX5_CMD_OP_DESTROY_MKEY = 0x202, 104 MLX5_CMD_OP_QUERY_SPECIAL_CONTEXTS = 0x203, 105 MLX5_CMD_OP_PAGE_FAULT_RESUME = 0x204, 106 MLX5_CMD_OP_ALLOC_MEMIC = 0x205, 107 MLX5_CMD_OP_DEALLOC_MEMIC = 0x206, 108 MLX5_CMD_OP_CREATE_EQ = 0x301, 109 MLX5_CMD_OP_DESTROY_EQ = 0x302, 110 MLX5_CMD_OP_QUERY_EQ = 0x303, 111 MLX5_CMD_OP_GEN_EQE = 0x304, 112 MLX5_CMD_OP_CREATE_CQ = 0x400, 113 MLX5_CMD_OP_DESTROY_CQ = 0x401, 114 MLX5_CMD_OP_QUERY_CQ = 0x402, 115 MLX5_CMD_OP_MODIFY_CQ = 0x403, 116 MLX5_CMD_OP_CREATE_QP = 0x500, 117 MLX5_CMD_OP_DESTROY_QP = 0x501, 118 MLX5_CMD_OP_RST2INIT_QP = 0x502, 119 MLX5_CMD_OP_INIT2RTR_QP = 0x503, 120 MLX5_CMD_OP_RTR2RTS_QP = 0x504, 121 MLX5_CMD_OP_RTS2RTS_QP = 0x505, 122 MLX5_CMD_OP_SQERR2RTS_QP = 0x506, 123 MLX5_CMD_OP_2ERR_QP = 0x507, 124 MLX5_CMD_OP_2RST_QP = 0x50a, 125 MLX5_CMD_OP_QUERY_QP = 0x50b, 126 MLX5_CMD_OP_SQD_RTS_QP = 0x50c, 127 MLX5_CMD_OP_INIT2INIT_QP = 0x50e, 128 MLX5_CMD_OP_CREATE_PSV = 0x600, 129 MLX5_CMD_OP_DESTROY_PSV = 0x601, 130 MLX5_CMD_OP_CREATE_SRQ = 0x700, 131 MLX5_CMD_OP_DESTROY_SRQ = 0x701, 132 MLX5_CMD_OP_QUERY_SRQ = 0x702, 133 MLX5_CMD_OP_ARM_RQ = 0x703, 134 MLX5_CMD_OP_CREATE_XRC_SRQ = 0x705, 135 MLX5_CMD_OP_DESTROY_XRC_SRQ = 0x706, 136 MLX5_CMD_OP_QUERY_XRC_SRQ = 0x707, 137 MLX5_CMD_OP_ARM_XRC_SRQ = 0x708, 138 MLX5_CMD_OP_CREATE_DCT = 0x710, 139 MLX5_CMD_OP_DESTROY_DCT = 0x711, 140 MLX5_CMD_OP_DRAIN_DCT = 0x712, 141 MLX5_CMD_OP_QUERY_DCT = 0x713, 142 MLX5_CMD_OP_ARM_DCT_FOR_KEY_VIOLATION = 0x714, 143 MLX5_CMD_OP_CREATE_XRQ = 0x717, 144 MLX5_CMD_OP_DESTROY_XRQ = 0x718, 145 MLX5_CMD_OP_QUERY_XRQ = 0x719, 146 MLX5_CMD_OP_ARM_XRQ = 0x71a, 147 MLX5_CMD_OP_QUERY_VPORT_STATE = 0x750, 148 MLX5_CMD_OP_MODIFY_VPORT_STATE = 0x751, 149 MLX5_CMD_OP_QUERY_ESW_VPORT_CONTEXT = 0x752, 150 MLX5_CMD_OP_MODIFY_ESW_VPORT_CONTEXT = 0x753, 151 MLX5_CMD_OP_QUERY_NIC_VPORT_CONTEXT = 0x754, 152 MLX5_CMD_OP_MODIFY_NIC_VPORT_CONTEXT = 0x755, 153 MLX5_CMD_OP_QUERY_ROCE_ADDRESS = 0x760, 154 MLX5_CMD_OP_SET_ROCE_ADDRESS = 0x761, 155 MLX5_CMD_OP_QUERY_HCA_VPORT_CONTEXT = 0x762, 156 MLX5_CMD_OP_MODIFY_HCA_VPORT_CONTEXT = 0x763, 157 MLX5_CMD_OP_QUERY_HCA_VPORT_GID = 0x764, 158 MLX5_CMD_OP_QUERY_HCA_VPORT_PKEY = 0x765, 159 MLX5_CMD_OP_QUERY_VNIC_ENV = 0x76f, 160 MLX5_CMD_OP_QUERY_VPORT_COUNTER = 0x770, 161 MLX5_CMD_OP_ALLOC_Q_COUNTER = 0x771, 162 MLX5_CMD_OP_DEALLOC_Q_COUNTER = 0x772, 163 MLX5_CMD_OP_QUERY_Q_COUNTER = 0x773, 164 MLX5_CMD_OP_SET_PP_RATE_LIMIT = 0x780, 165 MLX5_CMD_OP_QUERY_RATE_LIMIT = 0x781, 166 MLX5_CMD_OP_CREATE_SCHEDULING_ELEMENT = 0x782, 167 MLX5_CMD_OP_DESTROY_SCHEDULING_ELEMENT = 0x783, 168 MLX5_CMD_OP_QUERY_SCHEDULING_ELEMENT = 0x784, 169 MLX5_CMD_OP_MODIFY_SCHEDULING_ELEMENT = 0x785, 170 MLX5_CMD_OP_CREATE_QOS_PARA_VPORT = 0x786, 171 MLX5_CMD_OP_DESTROY_QOS_PARA_VPORT = 0x787, 172 MLX5_CMD_OP_ALLOC_PD = 0x800, 173 MLX5_CMD_OP_DEALLOC_PD = 0x801, 174 MLX5_CMD_OP_ALLOC_UAR = 0x802, 175 MLX5_CMD_OP_DEALLOC_UAR = 0x803, 176 MLX5_CMD_OP_CONFIG_INT_MODERATION = 0x804, 177 MLX5_CMD_OP_ACCESS_REG = 0x805, 178 MLX5_CMD_OP_ATTACH_TO_MCG = 0x806, 179 MLX5_CMD_OP_DETACH_FROM_MCG = 0x807, 180 MLX5_CMD_OP_GET_DROPPED_PACKET_LOG = 0x80a, 181 MLX5_CMD_OP_MAD_IFC = 0x50d, 182 MLX5_CMD_OP_QUERY_MAD_DEMUX = 0x80b, 183 MLX5_CMD_OP_SET_MAD_DEMUX = 0x80c, 184 MLX5_CMD_OP_NOP = 0x80d, 185 MLX5_CMD_OP_ALLOC_XRCD = 0x80e, 186 MLX5_CMD_OP_DEALLOC_XRCD = 0x80f, 187 MLX5_CMD_OP_ALLOC_TRANSPORT_DOMAIN = 0x816, 188 MLX5_CMD_OP_DEALLOC_TRANSPORT_DOMAIN = 0x817, 189 MLX5_CMD_OP_QUERY_CONG_STATUS = 0x822, 190 MLX5_CMD_OP_MODIFY_CONG_STATUS = 0x823, 191 MLX5_CMD_OP_QUERY_CONG_PARAMS = 0x824, 192 MLX5_CMD_OP_MODIFY_CONG_PARAMS = 0x825, 193 MLX5_CMD_OP_QUERY_CONG_STATISTICS = 0x826, 194 MLX5_CMD_OP_ADD_VXLAN_UDP_DPORT = 0x827, 195 MLX5_CMD_OP_DELETE_VXLAN_UDP_DPORT = 0x828, 196 MLX5_CMD_OP_SET_L2_TABLE_ENTRY = 0x829, 197 MLX5_CMD_OP_QUERY_L2_TABLE_ENTRY = 0x82a, 198 MLX5_CMD_OP_DELETE_L2_TABLE_ENTRY = 0x82b, 199 MLX5_CMD_OP_SET_WOL_ROL = 0x830, 200 MLX5_CMD_OP_QUERY_WOL_ROL = 0x831, 201 MLX5_CMD_OP_CREATE_LAG = 0x840, 202 MLX5_CMD_OP_MODIFY_LAG = 0x841, 203 MLX5_CMD_OP_QUERY_LAG = 0x842, 204 MLX5_CMD_OP_DESTROY_LAG = 0x843, 205 MLX5_CMD_OP_CREATE_VPORT_LAG = 0x844, 206 MLX5_CMD_OP_DESTROY_VPORT_LAG = 0x845, 207 MLX5_CMD_OP_CREATE_TIR = 0x900, 208 MLX5_CMD_OP_MODIFY_TIR = 0x901, 209 MLX5_CMD_OP_DESTROY_TIR = 0x902, 210 MLX5_CMD_OP_QUERY_TIR = 0x903, 211 MLX5_CMD_OP_CREATE_SQ = 0x904, 212 MLX5_CMD_OP_MODIFY_SQ = 0x905, 213 MLX5_CMD_OP_DESTROY_SQ = 0x906, 214 MLX5_CMD_OP_QUERY_SQ = 0x907, 215 MLX5_CMD_OP_CREATE_RQ = 0x908, 216 MLX5_CMD_OP_MODIFY_RQ = 0x909, 217 MLX5_CMD_OP_SET_DELAY_DROP_PARAMS = 0x910, 218 MLX5_CMD_OP_DESTROY_RQ = 0x90a, 219 MLX5_CMD_OP_QUERY_RQ = 0x90b, 220 MLX5_CMD_OP_CREATE_RMP = 0x90c, 221 MLX5_CMD_OP_MODIFY_RMP = 0x90d, 222 MLX5_CMD_OP_DESTROY_RMP = 0x90e, 223 MLX5_CMD_OP_QUERY_RMP = 0x90f, 224 MLX5_CMD_OP_CREATE_TIS = 0x912, 225 MLX5_CMD_OP_MODIFY_TIS = 0x913, 226 MLX5_CMD_OP_DESTROY_TIS = 0x914, 227 MLX5_CMD_OP_QUERY_TIS = 0x915, 228 MLX5_CMD_OP_CREATE_RQT = 0x916, 229 MLX5_CMD_OP_MODIFY_RQT = 0x917, 230 MLX5_CMD_OP_DESTROY_RQT = 0x918, 231 MLX5_CMD_OP_QUERY_RQT = 0x919, 232 MLX5_CMD_OP_SET_FLOW_TABLE_ROOT = 0x92f, 233 MLX5_CMD_OP_CREATE_FLOW_TABLE = 0x930, 234 MLX5_CMD_OP_DESTROY_FLOW_TABLE = 0x931, 235 MLX5_CMD_OP_QUERY_FLOW_TABLE = 0x932, 236 MLX5_CMD_OP_CREATE_FLOW_GROUP = 0x933, 237 MLX5_CMD_OP_DESTROY_FLOW_GROUP = 0x934, 238 MLX5_CMD_OP_QUERY_FLOW_GROUP = 0x935, 239 MLX5_CMD_OP_SET_FLOW_TABLE_ENTRY = 0x936, 240 MLX5_CMD_OP_QUERY_FLOW_TABLE_ENTRY = 0x937, 241 MLX5_CMD_OP_DELETE_FLOW_TABLE_ENTRY = 0x938, 242 MLX5_CMD_OP_ALLOC_FLOW_COUNTER = 0x939, 243 MLX5_CMD_OP_DEALLOC_FLOW_COUNTER = 0x93a, 244 MLX5_CMD_OP_QUERY_FLOW_COUNTER = 0x93b, 245 MLX5_CMD_OP_MODIFY_FLOW_TABLE = 0x93c, 246 MLX5_CMD_OP_ALLOC_ENCAP_HEADER = 0x93d, 247 MLX5_CMD_OP_DEALLOC_ENCAP_HEADER = 0x93e, 248 MLX5_CMD_OP_ALLOC_MODIFY_HEADER_CONTEXT = 0x940, 249 MLX5_CMD_OP_DEALLOC_MODIFY_HEADER_CONTEXT = 0x941, 250 MLX5_CMD_OP_QUERY_MODIFY_HEADER_CONTEXT = 0x942, 251 MLX5_CMD_OP_FPGA_CREATE_QP = 0x960, 252 MLX5_CMD_OP_FPGA_MODIFY_QP = 0x961, 253 MLX5_CMD_OP_FPGA_QUERY_QP = 0x962, 254 MLX5_CMD_OP_FPGA_DESTROY_QP = 0x963, 255 MLX5_CMD_OP_FPGA_QUERY_QP_COUNTERS = 0x964, 256 MLX5_CMD_OP_CREATE_GENERAL_OBJECT = 0xa00, 257 MLX5_CMD_OP_MODIFY_GENERAL_OBJECT = 0xa01, 258 MLX5_CMD_OP_QUERY_GENERAL_OBJECT = 0xa02, 259 MLX5_CMD_OP_DESTROY_GENERAL_OBJECT = 0xa03, 260 MLX5_CMD_OP_MAX 261 }; 262 263 struct mlx5_ifc_flow_table_fields_supported_bits { 264 u8 outer_dmac[0x1]; 265 u8 outer_smac[0x1]; 266 u8 outer_ether_type[0x1]; 267 u8 outer_ip_version[0x1]; 268 u8 outer_first_prio[0x1]; 269 u8 outer_first_cfi[0x1]; 270 u8 outer_first_vid[0x1]; 271 u8 outer_ipv4_ttl[0x1]; 272 u8 outer_second_prio[0x1]; 273 u8 outer_second_cfi[0x1]; 274 u8 outer_second_vid[0x1]; 275 u8 reserved_at_b[0x1]; 276 u8 outer_sip[0x1]; 277 u8 outer_dip[0x1]; 278 u8 outer_frag[0x1]; 279 u8 outer_ip_protocol[0x1]; 280 u8 outer_ip_ecn[0x1]; 281 u8 outer_ip_dscp[0x1]; 282 u8 outer_udp_sport[0x1]; 283 u8 outer_udp_dport[0x1]; 284 u8 outer_tcp_sport[0x1]; 285 u8 outer_tcp_dport[0x1]; 286 u8 outer_tcp_flags[0x1]; 287 u8 outer_gre_protocol[0x1]; 288 u8 outer_gre_key[0x1]; 289 u8 outer_vxlan_vni[0x1]; 290 u8 reserved_at_1a[0x5]; 291 u8 source_eswitch_port[0x1]; 292 293 u8 inner_dmac[0x1]; 294 u8 inner_smac[0x1]; 295 u8 inner_ether_type[0x1]; 296 u8 inner_ip_version[0x1]; 297 u8 inner_first_prio[0x1]; 298 u8 inner_first_cfi[0x1]; 299 u8 inner_first_vid[0x1]; 300 u8 reserved_at_27[0x1]; 301 u8 inner_second_prio[0x1]; 302 u8 inner_second_cfi[0x1]; 303 u8 inner_second_vid[0x1]; 304 u8 reserved_at_2b[0x1]; 305 u8 inner_sip[0x1]; 306 u8 inner_dip[0x1]; 307 u8 inner_frag[0x1]; 308 u8 inner_ip_protocol[0x1]; 309 u8 inner_ip_ecn[0x1]; 310 u8 inner_ip_dscp[0x1]; 311 u8 inner_udp_sport[0x1]; 312 u8 inner_udp_dport[0x1]; 313 u8 inner_tcp_sport[0x1]; 314 u8 inner_tcp_dport[0x1]; 315 u8 inner_tcp_flags[0x1]; 316 u8 reserved_at_37[0x9]; 317 318 u8 reserved_at_40[0x5]; 319 u8 outer_first_mpls_over_udp[0x4]; 320 u8 outer_first_mpls_over_gre[0x4]; 321 u8 inner_first_mpls[0x4]; 322 u8 outer_first_mpls[0x4]; 323 u8 reserved_at_55[0x2]; 324 u8 outer_esp_spi[0x1]; 325 u8 reserved_at_58[0x2]; 326 u8 bth_dst_qp[0x1]; 327 328 u8 reserved_at_5b[0x25]; 329 }; 330 331 struct mlx5_ifc_flow_table_prop_layout_bits { 332 u8 ft_support[0x1]; 333 u8 reserved_at_1[0x1]; 334 u8 flow_counter[0x1]; 335 u8 flow_modify_en[0x1]; 336 u8 modify_root[0x1]; 337 u8 identified_miss_table_mode[0x1]; 338 u8 flow_table_modify[0x1]; 339 u8 encap[0x1]; 340 u8 decap[0x1]; 341 u8 reserved_at_9[0x1]; 342 u8 pop_vlan[0x1]; 343 u8 push_vlan[0x1]; 344 u8 reserved_at_c[0x1]; 345 u8 pop_vlan_2[0x1]; 346 u8 push_vlan_2[0x1]; 347 u8 reserved_at_f[0x11]; 348 349 u8 reserved_at_20[0x2]; 350 u8 log_max_ft_size[0x6]; 351 u8 log_max_modify_header_context[0x8]; 352 u8 max_modify_header_actions[0x8]; 353 u8 max_ft_level[0x8]; 354 355 u8 reserved_at_40[0x20]; 356 357 u8 reserved_at_60[0x18]; 358 u8 log_max_ft_num[0x8]; 359 360 u8 reserved_at_80[0x18]; 361 u8 log_max_destination[0x8]; 362 363 u8 log_max_flow_counter[0x8]; 364 u8 reserved_at_a8[0x10]; 365 u8 log_max_flow[0x8]; 366 367 u8 reserved_at_c0[0x40]; 368 369 struct mlx5_ifc_flow_table_fields_supported_bits ft_field_support; 370 371 struct mlx5_ifc_flow_table_fields_supported_bits ft_field_bitmask_support; 372 }; 373 374 struct mlx5_ifc_odp_per_transport_service_cap_bits { 375 u8 send[0x1]; 376 u8 receive[0x1]; 377 u8 write[0x1]; 378 u8 read[0x1]; 379 u8 atomic[0x1]; 380 u8 srq_receive[0x1]; 381 u8 reserved_at_6[0x1a]; 382 }; 383 384 struct mlx5_ifc_fte_match_set_lyr_2_4_bits { 385 u8 smac_47_16[0x20]; 386 387 u8 smac_15_0[0x10]; 388 u8 ethertype[0x10]; 389 390 u8 dmac_47_16[0x20]; 391 392 u8 dmac_15_0[0x10]; 393 u8 first_prio[0x3]; 394 u8 first_cfi[0x1]; 395 u8 first_vid[0xc]; 396 397 u8 ip_protocol[0x8]; 398 u8 ip_dscp[0x6]; 399 u8 ip_ecn[0x2]; 400 u8 cvlan_tag[0x1]; 401 u8 svlan_tag[0x1]; 402 u8 frag[0x1]; 403 u8 ip_version[0x4]; 404 u8 tcp_flags[0x9]; 405 406 u8 tcp_sport[0x10]; 407 u8 tcp_dport[0x10]; 408 409 u8 reserved_at_c0[0x18]; 410 u8 ttl_hoplimit[0x8]; 411 412 u8 udp_sport[0x10]; 413 u8 udp_dport[0x10]; 414 415 union mlx5_ifc_ipv6_layout_ipv4_layout_auto_bits src_ipv4_src_ipv6; 416 417 union mlx5_ifc_ipv6_layout_ipv4_layout_auto_bits dst_ipv4_dst_ipv6; 418 }; 419 420 struct mlx5_ifc_fte_match_set_misc_bits { 421 u8 reserved_at_0[0x8]; 422 u8 source_sqn[0x18]; 423 424 u8 source_eswitch_owner_vhca_id[0x10]; 425 u8 source_port[0x10]; 426 427 u8 outer_second_prio[0x3]; 428 u8 outer_second_cfi[0x1]; 429 u8 outer_second_vid[0xc]; 430 u8 inner_second_prio[0x3]; 431 u8 inner_second_cfi[0x1]; 432 u8 inner_second_vid[0xc]; 433 434 u8 outer_second_cvlan_tag[0x1]; 435 u8 inner_second_cvlan_tag[0x1]; 436 u8 outer_second_svlan_tag[0x1]; 437 u8 inner_second_svlan_tag[0x1]; 438 u8 reserved_at_64[0xc]; 439 u8 gre_protocol[0x10]; 440 441 u8 gre_key_h[0x18]; 442 u8 gre_key_l[0x8]; 443 444 u8 vxlan_vni[0x18]; 445 u8 reserved_at_b8[0x8]; 446 447 u8 reserved_at_c0[0x20]; 448 449 u8 reserved_at_e0[0xc]; 450 u8 outer_ipv6_flow_label[0x14]; 451 452 u8 reserved_at_100[0xc]; 453 u8 inner_ipv6_flow_label[0x14]; 454 455 u8 reserved_at_120[0x28]; 456 u8 bth_dst_qp[0x18]; 457 u8 reserved_at_160[0x20]; 458 u8 outer_esp_spi[0x20]; 459 u8 reserved_at_1a0[0x60]; 460 }; 461 462 struct mlx5_ifc_fte_match_mpls_bits { 463 u8 mpls_label[0x14]; 464 u8 mpls_exp[0x3]; 465 u8 mpls_s_bos[0x1]; 466 u8 mpls_ttl[0x8]; 467 }; 468 469 struct mlx5_ifc_fte_match_set_misc2_bits { 470 struct mlx5_ifc_fte_match_mpls_bits outer_first_mpls; 471 472 struct mlx5_ifc_fte_match_mpls_bits inner_first_mpls; 473 474 struct mlx5_ifc_fte_match_mpls_bits outer_first_mpls_over_gre; 475 476 struct mlx5_ifc_fte_match_mpls_bits outer_first_mpls_over_udp; 477 478 u8 reserved_at_80[0x100]; 479 480 u8 metadata_reg_a[0x20]; 481 482 u8 reserved_at_1a0[0x60]; 483 }; 484 485 struct mlx5_ifc_cmd_pas_bits { 486 u8 pa_h[0x20]; 487 488 u8 pa_l[0x14]; 489 u8 reserved_at_34[0xc]; 490 }; 491 492 struct mlx5_ifc_uint64_bits { 493 u8 hi[0x20]; 494 495 u8 lo[0x20]; 496 }; 497 498 enum { 499 MLX5_ADS_STAT_RATE_NO_LIMIT = 0x0, 500 MLX5_ADS_STAT_RATE_2_5GBPS = 0x7, 501 MLX5_ADS_STAT_RATE_10GBPS = 0x8, 502 MLX5_ADS_STAT_RATE_30GBPS = 0x9, 503 MLX5_ADS_STAT_RATE_5GBPS = 0xa, 504 MLX5_ADS_STAT_RATE_20GBPS = 0xb, 505 MLX5_ADS_STAT_RATE_40GBPS = 0xc, 506 MLX5_ADS_STAT_RATE_60GBPS = 0xd, 507 MLX5_ADS_STAT_RATE_80GBPS = 0xe, 508 MLX5_ADS_STAT_RATE_120GBPS = 0xf, 509 }; 510 511 struct mlx5_ifc_ads_bits { 512 u8 fl[0x1]; 513 u8 free_ar[0x1]; 514 u8 reserved_at_2[0xe]; 515 u8 pkey_index[0x10]; 516 517 u8 reserved_at_20[0x8]; 518 u8 grh[0x1]; 519 u8 mlid[0x7]; 520 u8 rlid[0x10]; 521 522 u8 ack_timeout[0x5]; 523 u8 reserved_at_45[0x3]; 524 u8 src_addr_index[0x8]; 525 u8 reserved_at_50[0x4]; 526 u8 stat_rate[0x4]; 527 u8 hop_limit[0x8]; 528 529 u8 reserved_at_60[0x4]; 530 u8 tclass[0x8]; 531 u8 flow_label[0x14]; 532 533 u8 rgid_rip[16][0x8]; 534 535 u8 reserved_at_100[0x4]; 536 u8 f_dscp[0x1]; 537 u8 f_ecn[0x1]; 538 u8 reserved_at_106[0x1]; 539 u8 f_eth_prio[0x1]; 540 u8 ecn[0x2]; 541 u8 dscp[0x6]; 542 u8 udp_sport[0x10]; 543 544 u8 dei_cfi[0x1]; 545 u8 eth_prio[0x3]; 546 u8 sl[0x4]; 547 u8 vhca_port_num[0x8]; 548 u8 rmac_47_32[0x10]; 549 550 u8 rmac_31_0[0x20]; 551 }; 552 553 struct mlx5_ifc_flow_table_nic_cap_bits { 554 u8 nic_rx_multi_path_tirs[0x1]; 555 u8 nic_rx_multi_path_tirs_fts[0x1]; 556 u8 allow_sniffer_and_nic_rx_shared_tir[0x1]; 557 u8 reserved_at_3[0x1fd]; 558 559 struct mlx5_ifc_flow_table_prop_layout_bits flow_table_properties_nic_receive; 560 561 u8 reserved_at_400[0x200]; 562 563 struct mlx5_ifc_flow_table_prop_layout_bits flow_table_properties_nic_receive_sniffer; 564 565 struct mlx5_ifc_flow_table_prop_layout_bits flow_table_properties_nic_transmit; 566 567 u8 reserved_at_a00[0x200]; 568 569 struct mlx5_ifc_flow_table_prop_layout_bits flow_table_properties_nic_transmit_sniffer; 570 571 u8 reserved_at_e00[0x7200]; 572 }; 573 574 struct mlx5_ifc_flow_table_eswitch_cap_bits { 575 u8 reserved_at_0[0x1c]; 576 u8 fdb_multi_path_to_table[0x1]; 577 u8 reserved_at_1d[0x1e3]; 578 579 struct mlx5_ifc_flow_table_prop_layout_bits flow_table_properties_nic_esw_fdb; 580 581 struct mlx5_ifc_flow_table_prop_layout_bits flow_table_properties_esw_acl_ingress; 582 583 struct mlx5_ifc_flow_table_prop_layout_bits flow_table_properties_esw_acl_egress; 584 585 u8 reserved_at_800[0x7800]; 586 }; 587 588 struct mlx5_ifc_e_switch_cap_bits { 589 u8 vport_svlan_strip[0x1]; 590 u8 vport_cvlan_strip[0x1]; 591 u8 vport_svlan_insert[0x1]; 592 u8 vport_cvlan_insert_if_not_exist[0x1]; 593 u8 vport_cvlan_insert_overwrite[0x1]; 594 u8 reserved_at_5[0x18]; 595 u8 merged_eswitch[0x1]; 596 u8 nic_vport_node_guid_modify[0x1]; 597 u8 nic_vport_port_guid_modify[0x1]; 598 599 u8 vxlan_encap_decap[0x1]; 600 u8 nvgre_encap_decap[0x1]; 601 u8 reserved_at_22[0x9]; 602 u8 log_max_encap_headers[0x5]; 603 u8 reserved_2b[0x6]; 604 u8 max_encap_header_size[0xa]; 605 606 u8 reserved_40[0x7c0]; 607 608 }; 609 610 struct mlx5_ifc_qos_cap_bits { 611 u8 packet_pacing[0x1]; 612 u8 esw_scheduling[0x1]; 613 u8 esw_bw_share[0x1]; 614 u8 esw_rate_limit[0x1]; 615 u8 reserved_at_4[0x1]; 616 u8 packet_pacing_burst_bound[0x1]; 617 u8 packet_pacing_typical_size[0x1]; 618 u8 reserved_at_7[0x19]; 619 620 u8 reserved_at_20[0x20]; 621 622 u8 packet_pacing_max_rate[0x20]; 623 624 u8 packet_pacing_min_rate[0x20]; 625 626 u8 reserved_at_80[0x10]; 627 u8 packet_pacing_rate_table_size[0x10]; 628 629 u8 esw_element_type[0x10]; 630 u8 esw_tsar_type[0x10]; 631 632 u8 reserved_at_c0[0x10]; 633 u8 max_qos_para_vport[0x10]; 634 635 u8 max_tsar_bw_share[0x20]; 636 637 u8 reserved_at_100[0x700]; 638 }; 639 640 struct mlx5_ifc_debug_cap_bits { 641 u8 reserved_at_0[0x20]; 642 643 u8 reserved_at_20[0x2]; 644 u8 stall_detect[0x1]; 645 u8 reserved_at_23[0x1d]; 646 647 u8 reserved_at_40[0x7c0]; 648 }; 649 650 struct mlx5_ifc_per_protocol_networking_offload_caps_bits { 651 u8 csum_cap[0x1]; 652 u8 vlan_cap[0x1]; 653 u8 lro_cap[0x1]; 654 u8 lro_psh_flag[0x1]; 655 u8 lro_time_stamp[0x1]; 656 u8 reserved_at_5[0x2]; 657 u8 wqe_vlan_insert[0x1]; 658 u8 self_lb_en_modifiable[0x1]; 659 u8 reserved_at_9[0x2]; 660 u8 max_lso_cap[0x5]; 661 u8 multi_pkt_send_wqe[0x2]; 662 u8 wqe_inline_mode[0x2]; 663 u8 rss_ind_tbl_cap[0x4]; 664 u8 reg_umr_sq[0x1]; 665 u8 scatter_fcs[0x1]; 666 u8 enhanced_multi_pkt_send_wqe[0x1]; 667 u8 tunnel_lso_const_out_ip_id[0x1]; 668 u8 reserved_at_1c[0x2]; 669 u8 tunnel_stateless_gre[0x1]; 670 u8 tunnel_stateless_vxlan[0x1]; 671 672 u8 swp[0x1]; 673 u8 swp_csum[0x1]; 674 u8 swp_lso[0x1]; 675 u8 reserved_at_23[0xd]; 676 u8 max_vxlan_udp_ports[0x8]; 677 u8 reserved_at_38[0x6]; 678 u8 max_geneve_opt_len[0x1]; 679 u8 tunnel_stateless_geneve_rx[0x1]; 680 681 u8 reserved_at_40[0x10]; 682 u8 lro_min_mss_size[0x10]; 683 684 u8 reserved_at_60[0x120]; 685 686 u8 lro_timer_supported_periods[4][0x20]; 687 688 u8 reserved_at_200[0x600]; 689 }; 690 691 struct mlx5_ifc_roce_cap_bits { 692 u8 roce_apm[0x1]; 693 u8 reserved_at_1[0x1f]; 694 695 u8 reserved_at_20[0x60]; 696 697 u8 reserved_at_80[0xc]; 698 u8 l3_type[0x4]; 699 u8 reserved_at_90[0x8]; 700 u8 roce_version[0x8]; 701 702 u8 reserved_at_a0[0x10]; 703 u8 r_roce_dest_udp_port[0x10]; 704 705 u8 r_roce_max_src_udp_port[0x10]; 706 u8 r_roce_min_src_udp_port[0x10]; 707 708 u8 reserved_at_e0[0x10]; 709 u8 roce_address_table_size[0x10]; 710 711 u8 reserved_at_100[0x700]; 712 }; 713 714 struct mlx5_ifc_device_mem_cap_bits { 715 u8 memic[0x1]; 716 u8 reserved_at_1[0x1f]; 717 718 u8 reserved_at_20[0xb]; 719 u8 log_min_memic_alloc_size[0x5]; 720 u8 reserved_at_30[0x8]; 721 u8 log_max_memic_addr_alignment[0x8]; 722 723 u8 memic_bar_start_addr[0x40]; 724 725 u8 memic_bar_size[0x20]; 726 727 u8 max_memic_size[0x20]; 728 729 u8 reserved_at_c0[0x740]; 730 }; 731 732 enum { 733 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_QP_1_BYTE = 0x0, 734 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_QP_2_BYTES = 0x2, 735 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_QP_4_BYTES = 0x4, 736 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_QP_8_BYTES = 0x8, 737 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_QP_16_BYTES = 0x10, 738 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_QP_32_BYTES = 0x20, 739 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_QP_64_BYTES = 0x40, 740 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_QP_128_BYTES = 0x80, 741 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_QP_256_BYTES = 0x100, 742 }; 743 744 enum { 745 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_DC_1_BYTE = 0x1, 746 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_DC_2_BYTES = 0x2, 747 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_DC_4_BYTES = 0x4, 748 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_DC_8_BYTES = 0x8, 749 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_DC_16_BYTES = 0x10, 750 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_DC_32_BYTES = 0x20, 751 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_DC_64_BYTES = 0x40, 752 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_DC_128_BYTES = 0x80, 753 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_DC_256_BYTES = 0x100, 754 }; 755 756 struct mlx5_ifc_atomic_caps_bits { 757 u8 reserved_at_0[0x40]; 758 759 u8 atomic_req_8B_endianness_mode[0x2]; 760 u8 reserved_at_42[0x4]; 761 u8 supported_atomic_req_8B_endianness_mode_1[0x1]; 762 763 u8 reserved_at_47[0x19]; 764 765 u8 reserved_at_60[0x20]; 766 767 u8 reserved_at_80[0x10]; 768 u8 atomic_operations[0x10]; 769 770 u8 reserved_at_a0[0x10]; 771 u8 atomic_size_qp[0x10]; 772 773 u8 reserved_at_c0[0x10]; 774 u8 atomic_size_dc[0x10]; 775 776 u8 reserved_at_e0[0x720]; 777 }; 778 779 struct mlx5_ifc_odp_cap_bits { 780 u8 reserved_at_0[0x40]; 781 782 u8 sig[0x1]; 783 u8 reserved_at_41[0x1f]; 784 785 u8 reserved_at_60[0x20]; 786 787 struct mlx5_ifc_odp_per_transport_service_cap_bits rc_odp_caps; 788 789 struct mlx5_ifc_odp_per_transport_service_cap_bits uc_odp_caps; 790 791 struct mlx5_ifc_odp_per_transport_service_cap_bits ud_odp_caps; 792 793 u8 reserved_at_e0[0x720]; 794 }; 795 796 struct mlx5_ifc_calc_op { 797 u8 reserved_at_0[0x10]; 798 u8 reserved_at_10[0x9]; 799 u8 op_swap_endianness[0x1]; 800 u8 op_min[0x1]; 801 u8 op_xor[0x1]; 802 u8 op_or[0x1]; 803 u8 op_and[0x1]; 804 u8 op_max[0x1]; 805 u8 op_add[0x1]; 806 }; 807 808 struct mlx5_ifc_vector_calc_cap_bits { 809 u8 calc_matrix[0x1]; 810 u8 reserved_at_1[0x1f]; 811 u8 reserved_at_20[0x8]; 812 u8 max_vec_count[0x8]; 813 u8 reserved_at_30[0xd]; 814 u8 max_chunk_size[0x3]; 815 struct mlx5_ifc_calc_op calc0; 816 struct mlx5_ifc_calc_op calc1; 817 struct mlx5_ifc_calc_op calc2; 818 struct mlx5_ifc_calc_op calc3; 819 820 u8 reserved_at_e0[0x720]; 821 }; 822 823 enum { 824 MLX5_WQ_TYPE_LINKED_LIST = 0x0, 825 MLX5_WQ_TYPE_CYCLIC = 0x1, 826 MLX5_WQ_TYPE_LINKED_LIST_STRIDING_RQ = 0x2, 827 MLX5_WQ_TYPE_CYCLIC_STRIDING_RQ = 0x3, 828 }; 829 830 enum { 831 MLX5_WQ_END_PAD_MODE_NONE = 0x0, 832 MLX5_WQ_END_PAD_MODE_ALIGN = 0x1, 833 }; 834 835 enum { 836 MLX5_CMD_HCA_CAP_GID_TABLE_SIZE_8_GID_ENTRIES = 0x0, 837 MLX5_CMD_HCA_CAP_GID_TABLE_SIZE_16_GID_ENTRIES = 0x1, 838 MLX5_CMD_HCA_CAP_GID_TABLE_SIZE_32_GID_ENTRIES = 0x2, 839 MLX5_CMD_HCA_CAP_GID_TABLE_SIZE_64_GID_ENTRIES = 0x3, 840 MLX5_CMD_HCA_CAP_GID_TABLE_SIZE_128_GID_ENTRIES = 0x4, 841 }; 842 843 enum { 844 MLX5_CMD_HCA_CAP_PKEY_TABLE_SIZE_128_ENTRIES = 0x0, 845 MLX5_CMD_HCA_CAP_PKEY_TABLE_SIZE_256_ENTRIES = 0x1, 846 MLX5_CMD_HCA_CAP_PKEY_TABLE_SIZE_512_ENTRIES = 0x2, 847 MLX5_CMD_HCA_CAP_PKEY_TABLE_SIZE_1K_ENTRIES = 0x3, 848 MLX5_CMD_HCA_CAP_PKEY_TABLE_SIZE_2K_ENTRIES = 0x4, 849 MLX5_CMD_HCA_CAP_PKEY_TABLE_SIZE_4K_ENTRIES = 0x5, 850 }; 851 852 enum { 853 MLX5_CMD_HCA_CAP_PORT_TYPE_IB = 0x0, 854 MLX5_CMD_HCA_CAP_PORT_TYPE_ETHERNET = 0x1, 855 }; 856 857 enum { 858 MLX5_CMD_HCA_CAP_CMDIF_CHECKSUM_DISABLED = 0x0, 859 MLX5_CMD_HCA_CAP_CMDIF_CHECKSUM_INITIAL_STATE = 0x1, 860 MLX5_CMD_HCA_CAP_CMDIF_CHECKSUM_ENABLED = 0x3, 861 }; 862 863 enum { 864 MLX5_CAP_PORT_TYPE_IB = 0x0, 865 MLX5_CAP_PORT_TYPE_ETH = 0x1, 866 }; 867 868 enum { 869 MLX5_CAP_UMR_FENCE_STRONG = 0x0, 870 MLX5_CAP_UMR_FENCE_SMALL = 0x1, 871 MLX5_CAP_UMR_FENCE_NONE = 0x2, 872 }; 873 874 struct mlx5_ifc_cmd_hca_cap_bits { 875 u8 reserved_at_0[0x30]; 876 u8 vhca_id[0x10]; 877 878 u8 reserved_at_40[0x40]; 879 880 u8 log_max_srq_sz[0x8]; 881 u8 log_max_qp_sz[0x8]; 882 u8 reserved_at_90[0xb]; 883 u8 log_max_qp[0x5]; 884 885 u8 reserved_at_a0[0xb]; 886 u8 log_max_srq[0x5]; 887 u8 reserved_at_b0[0x10]; 888 889 u8 reserved_at_c0[0x8]; 890 u8 log_max_cq_sz[0x8]; 891 u8 reserved_at_d0[0xb]; 892 u8 log_max_cq[0x5]; 893 894 u8 log_max_eq_sz[0x8]; 895 u8 reserved_at_e8[0x2]; 896 u8 log_max_mkey[0x6]; 897 u8 reserved_at_f0[0x8]; 898 u8 dump_fill_mkey[0x1]; 899 u8 reserved_at_f9[0x2]; 900 u8 fast_teardown[0x1]; 901 u8 log_max_eq[0x4]; 902 903 u8 max_indirection[0x8]; 904 u8 fixed_buffer_size[0x1]; 905 u8 log_max_mrw_sz[0x7]; 906 u8 force_teardown[0x1]; 907 u8 reserved_at_111[0x1]; 908 u8 log_max_bsf_list_size[0x6]; 909 u8 umr_extended_translation_offset[0x1]; 910 u8 null_mkey[0x1]; 911 u8 log_max_klm_list_size[0x6]; 912 913 u8 reserved_at_120[0xa]; 914 u8 log_max_ra_req_dc[0x6]; 915 u8 reserved_at_130[0xa]; 916 u8 log_max_ra_res_dc[0x6]; 917 918 u8 reserved_at_140[0xa]; 919 u8 log_max_ra_req_qp[0x6]; 920 u8 reserved_at_150[0xa]; 921 u8 log_max_ra_res_qp[0x6]; 922 923 u8 end_pad[0x1]; 924 u8 cc_query_allowed[0x1]; 925 u8 cc_modify_allowed[0x1]; 926 u8 start_pad[0x1]; 927 u8 cache_line_128byte[0x1]; 928 u8 reserved_at_165[0xa]; 929 u8 qcam_reg[0x1]; 930 u8 gid_table_size[0x10]; 931 932 u8 out_of_seq_cnt[0x1]; 933 u8 vport_counters[0x1]; 934 u8 retransmission_q_counters[0x1]; 935 u8 debug[0x1]; 936 u8 modify_rq_counter_set_id[0x1]; 937 u8 rq_delay_drop[0x1]; 938 u8 max_qp_cnt[0xa]; 939 u8 pkey_table_size[0x10]; 940 941 u8 vport_group_manager[0x1]; 942 u8 vhca_group_manager[0x1]; 943 u8 ib_virt[0x1]; 944 u8 eth_virt[0x1]; 945 u8 vnic_env_queue_counters[0x1]; 946 u8 ets[0x1]; 947 u8 nic_flow_table[0x1]; 948 u8 eswitch_manager[0x1]; 949 u8 device_memory[0x1]; 950 u8 mcam_reg[0x1]; 951 u8 pcam_reg[0x1]; 952 u8 local_ca_ack_delay[0x5]; 953 u8 port_module_event[0x1]; 954 u8 enhanced_error_q_counters[0x1]; 955 u8 ports_check[0x1]; 956 u8 reserved_at_1b3[0x1]; 957 u8 disable_link_up[0x1]; 958 u8 beacon_led[0x1]; 959 u8 port_type[0x2]; 960 u8 num_ports[0x8]; 961 962 u8 reserved_at_1c0[0x1]; 963 u8 pps[0x1]; 964 u8 pps_modify[0x1]; 965 u8 log_max_msg[0x5]; 966 u8 reserved_at_1c8[0x4]; 967 u8 max_tc[0x4]; 968 u8 temp_warn_event[0x1]; 969 u8 dcbx[0x1]; 970 u8 general_notification_event[0x1]; 971 u8 reserved_at_1d3[0x2]; 972 u8 fpga[0x1]; 973 u8 rol_s[0x1]; 974 u8 rol_g[0x1]; 975 u8 reserved_at_1d8[0x1]; 976 u8 wol_s[0x1]; 977 u8 wol_g[0x1]; 978 u8 wol_a[0x1]; 979 u8 wol_b[0x1]; 980 u8 wol_m[0x1]; 981 u8 wol_u[0x1]; 982 u8 wol_p[0x1]; 983 984 u8 stat_rate_support[0x10]; 985 u8 reserved_at_1f0[0xc]; 986 u8 cqe_version[0x4]; 987 988 u8 compact_address_vector[0x1]; 989 u8 striding_rq[0x1]; 990 u8 reserved_at_202[0x1]; 991 u8 ipoib_enhanced_offloads[0x1]; 992 u8 ipoib_basic_offloads[0x1]; 993 u8 reserved_at_205[0x1]; 994 u8 repeated_block_disabled[0x1]; 995 u8 umr_modify_entity_size_disabled[0x1]; 996 u8 umr_modify_atomic_disabled[0x1]; 997 u8 umr_indirect_mkey_disabled[0x1]; 998 u8 umr_fence[0x2]; 999 u8 reserved_at_20c[0x3]; 1000 u8 drain_sigerr[0x1]; 1001 u8 cmdif_checksum[0x2]; 1002 u8 sigerr_cqe[0x1]; 1003 u8 reserved_at_213[0x1]; 1004 u8 wq_signature[0x1]; 1005 u8 sctr_data_cqe[0x1]; 1006 u8 reserved_at_216[0x1]; 1007 u8 sho[0x1]; 1008 u8 tph[0x1]; 1009 u8 rf[0x1]; 1010 u8 dct[0x1]; 1011 u8 qos[0x1]; 1012 u8 eth_net_offloads[0x1]; 1013 u8 roce[0x1]; 1014 u8 atomic[0x1]; 1015 u8 reserved_at_21f[0x1]; 1016 1017 u8 cq_oi[0x1]; 1018 u8 cq_resize[0x1]; 1019 u8 cq_moderation[0x1]; 1020 u8 reserved_at_223[0x3]; 1021 u8 cq_eq_remap[0x1]; 1022 u8 pg[0x1]; 1023 u8 block_lb_mc[0x1]; 1024 u8 reserved_at_229[0x1]; 1025 u8 scqe_break_moderation[0x1]; 1026 u8 cq_period_start_from_cqe[0x1]; 1027 u8 cd[0x1]; 1028 u8 reserved_at_22d[0x1]; 1029 u8 apm[0x1]; 1030 u8 vector_calc[0x1]; 1031 u8 umr_ptr_rlky[0x1]; 1032 u8 imaicl[0x1]; 1033 u8 reserved_at_232[0x4]; 1034 u8 qkv[0x1]; 1035 u8 pkv[0x1]; 1036 u8 set_deth_sqpn[0x1]; 1037 u8 reserved_at_239[0x3]; 1038 u8 xrc[0x1]; 1039 u8 ud[0x1]; 1040 u8 uc[0x1]; 1041 u8 rc[0x1]; 1042 1043 u8 uar_4k[0x1]; 1044 u8 reserved_at_241[0x9]; 1045 u8 uar_sz[0x6]; 1046 u8 reserved_at_250[0x8]; 1047 u8 log_pg_sz[0x8]; 1048 1049 u8 bf[0x1]; 1050 u8 driver_version[0x1]; 1051 u8 pad_tx_eth_packet[0x1]; 1052 u8 reserved_at_263[0x8]; 1053 u8 log_bf_reg_size[0x5]; 1054 1055 u8 reserved_at_270[0xb]; 1056 u8 lag_master[0x1]; 1057 u8 num_lag_ports[0x4]; 1058 1059 u8 reserved_at_280[0x10]; 1060 u8 max_wqe_sz_sq[0x10]; 1061 1062 u8 reserved_at_2a0[0x10]; 1063 u8 max_wqe_sz_rq[0x10]; 1064 1065 u8 max_flow_counter_31_16[0x10]; 1066 u8 max_wqe_sz_sq_dc[0x10]; 1067 1068 u8 reserved_at_2e0[0x7]; 1069 u8 max_qp_mcg[0x19]; 1070 1071 u8 reserved_at_300[0x18]; 1072 u8 log_max_mcg[0x8]; 1073 1074 u8 reserved_at_320[0x3]; 1075 u8 log_max_transport_domain[0x5]; 1076 u8 reserved_at_328[0x3]; 1077 u8 log_max_pd[0x5]; 1078 u8 reserved_at_330[0xb]; 1079 u8 log_max_xrcd[0x5]; 1080 1081 u8 nic_receive_steering_discard[0x1]; 1082 u8 receive_discard_vport_down[0x1]; 1083 u8 transmit_discard_vport_down[0x1]; 1084 u8 reserved_at_343[0x5]; 1085 u8 log_max_flow_counter_bulk[0x8]; 1086 u8 max_flow_counter_15_0[0x10]; 1087 1088 1089 u8 reserved_at_360[0x3]; 1090 u8 log_max_rq[0x5]; 1091 u8 reserved_at_368[0x3]; 1092 u8 log_max_sq[0x5]; 1093 u8 reserved_at_370[0x3]; 1094 u8 log_max_tir[0x5]; 1095 u8 reserved_at_378[0x3]; 1096 u8 log_max_tis[0x5]; 1097 1098 u8 basic_cyclic_rcv_wqe[0x1]; 1099 u8 reserved_at_381[0x2]; 1100 u8 log_max_rmp[0x5]; 1101 u8 reserved_at_388[0x3]; 1102 u8 log_max_rqt[0x5]; 1103 u8 reserved_at_390[0x3]; 1104 u8 log_max_rqt_size[0x5]; 1105 u8 reserved_at_398[0x3]; 1106 u8 log_max_tis_per_sq[0x5]; 1107 1108 u8 ext_stride_num_range[0x1]; 1109 u8 reserved_at_3a1[0x2]; 1110 u8 log_max_stride_sz_rq[0x5]; 1111 u8 reserved_at_3a8[0x3]; 1112 u8 log_min_stride_sz_rq[0x5]; 1113 u8 reserved_at_3b0[0x3]; 1114 u8 log_max_stride_sz_sq[0x5]; 1115 u8 reserved_at_3b8[0x3]; 1116 u8 log_min_stride_sz_sq[0x5]; 1117 1118 u8 hairpin[0x1]; 1119 u8 reserved_at_3c1[0x2]; 1120 u8 log_max_hairpin_queues[0x5]; 1121 u8 reserved_at_3c8[0x3]; 1122 u8 log_max_hairpin_wq_data_sz[0x5]; 1123 u8 reserved_at_3d0[0x3]; 1124 u8 log_max_hairpin_num_packets[0x5]; 1125 u8 reserved_at_3d8[0x3]; 1126 u8 log_max_wq_sz[0x5]; 1127 1128 u8 nic_vport_change_event[0x1]; 1129 u8 disable_local_lb_uc[0x1]; 1130 u8 disable_local_lb_mc[0x1]; 1131 u8 log_min_hairpin_wq_data_sz[0x5]; 1132 u8 reserved_at_3e8[0x3]; 1133 u8 log_max_vlan_list[0x5]; 1134 u8 reserved_at_3f0[0x3]; 1135 u8 log_max_current_mc_list[0x5]; 1136 u8 reserved_at_3f8[0x3]; 1137 u8 log_max_current_uc_list[0x5]; 1138 1139 u8 general_obj_types[0x40]; 1140 1141 u8 reserved_at_440[0x20]; 1142 1143 u8 reserved_at_460[0x10]; 1144 u8 max_num_eqs[0x10]; 1145 1146 u8 reserved_at_480[0x3]; 1147 u8 log_max_l2_table[0x5]; 1148 u8 reserved_at_488[0x8]; 1149 u8 log_uar_page_sz[0x10]; 1150 1151 u8 reserved_at_4a0[0x20]; 1152 u8 device_frequency_mhz[0x20]; 1153 u8 device_frequency_khz[0x20]; 1154 1155 u8 reserved_at_500[0x20]; 1156 u8 num_of_uars_per_page[0x20]; 1157 1158 u8 flex_parser_protocols[0x20]; 1159 u8 reserved_at_560[0x20]; 1160 1161 u8 reserved_at_580[0x3c]; 1162 u8 mini_cqe_resp_stride_index[0x1]; 1163 u8 cqe_128_always[0x1]; 1164 u8 cqe_compression_128[0x1]; 1165 u8 cqe_compression[0x1]; 1166 1167 u8 cqe_compression_timeout[0x10]; 1168 u8 cqe_compression_max_num[0x10]; 1169 1170 u8 reserved_at_5e0[0x10]; 1171 u8 tag_matching[0x1]; 1172 u8 rndv_offload_rc[0x1]; 1173 u8 rndv_offload_dc[0x1]; 1174 u8 log_tag_matching_list_sz[0x5]; 1175 u8 reserved_at_5f8[0x3]; 1176 u8 log_max_xrq[0x5]; 1177 1178 u8 affiliate_nic_vport_criteria[0x8]; 1179 u8 native_port_num[0x8]; 1180 u8 num_vhca_ports[0x8]; 1181 u8 reserved_at_618[0x6]; 1182 u8 sw_owner_id[0x1]; 1183 u8 reserved_at_61f[0x1e1]; 1184 }; 1185 1186 enum mlx5_flow_destination_type { 1187 MLX5_FLOW_DESTINATION_TYPE_VPORT = 0x0, 1188 MLX5_FLOW_DESTINATION_TYPE_FLOW_TABLE = 0x1, 1189 MLX5_FLOW_DESTINATION_TYPE_TIR = 0x2, 1190 1191 MLX5_FLOW_DESTINATION_TYPE_PORT = 0x99, 1192 MLX5_FLOW_DESTINATION_TYPE_COUNTER = 0x100, 1193 MLX5_FLOW_DESTINATION_TYPE_FLOW_TABLE_NUM = 0x101, 1194 }; 1195 1196 struct mlx5_ifc_dest_format_struct_bits { 1197 u8 destination_type[0x8]; 1198 u8 destination_id[0x18]; 1199 u8 destination_eswitch_owner_vhca_id_valid[0x1]; 1200 u8 reserved_at_21[0xf]; 1201 u8 destination_eswitch_owner_vhca_id[0x10]; 1202 }; 1203 1204 struct mlx5_ifc_flow_counter_list_bits { 1205 u8 flow_counter_id[0x20]; 1206 1207 u8 reserved_at_20[0x20]; 1208 }; 1209 1210 union mlx5_ifc_dest_format_struct_flow_counter_list_auto_bits { 1211 struct mlx5_ifc_dest_format_struct_bits dest_format_struct; 1212 struct mlx5_ifc_flow_counter_list_bits flow_counter_list; 1213 u8 reserved_at_0[0x40]; 1214 }; 1215 1216 struct mlx5_ifc_fte_match_param_bits { 1217 struct mlx5_ifc_fte_match_set_lyr_2_4_bits outer_headers; 1218 1219 struct mlx5_ifc_fte_match_set_misc_bits misc_parameters; 1220 1221 struct mlx5_ifc_fte_match_set_lyr_2_4_bits inner_headers; 1222 1223 struct mlx5_ifc_fte_match_set_misc2_bits misc_parameters_2; 1224 1225 u8 reserved_at_800[0x800]; 1226 }; 1227 1228 enum { 1229 MLX5_RX_HASH_FIELD_SELECT_SELECTED_FIELDS_SRC_IP = 0x0, 1230 MLX5_RX_HASH_FIELD_SELECT_SELECTED_FIELDS_DST_IP = 0x1, 1231 MLX5_RX_HASH_FIELD_SELECT_SELECTED_FIELDS_L4_SPORT = 0x2, 1232 MLX5_RX_HASH_FIELD_SELECT_SELECTED_FIELDS_L4_DPORT = 0x3, 1233 MLX5_RX_HASH_FIELD_SELECT_SELECTED_FIELDS_IPSEC_SPI = 0x4, 1234 }; 1235 1236 struct mlx5_ifc_rx_hash_field_select_bits { 1237 u8 l3_prot_type[0x1]; 1238 u8 l4_prot_type[0x1]; 1239 u8 selected_fields[0x1e]; 1240 }; 1241 1242 enum { 1243 MLX5_WQ_WQ_TYPE_WQ_LINKED_LIST = 0x0, 1244 MLX5_WQ_WQ_TYPE_WQ_CYCLIC = 0x1, 1245 }; 1246 1247 enum { 1248 MLX5_WQ_END_PADDING_MODE_END_PAD_NONE = 0x0, 1249 MLX5_WQ_END_PADDING_MODE_END_PAD_ALIGN = 0x1, 1250 }; 1251 1252 struct mlx5_ifc_wq_bits { 1253 u8 wq_type[0x4]; 1254 u8 wq_signature[0x1]; 1255 u8 end_padding_mode[0x2]; 1256 u8 cd_slave[0x1]; 1257 u8 reserved_at_8[0x18]; 1258 1259 u8 hds_skip_first_sge[0x1]; 1260 u8 log2_hds_buf_size[0x3]; 1261 u8 reserved_at_24[0x7]; 1262 u8 page_offset[0x5]; 1263 u8 lwm[0x10]; 1264 1265 u8 reserved_at_40[0x8]; 1266 u8 pd[0x18]; 1267 1268 u8 reserved_at_60[0x8]; 1269 u8 uar_page[0x18]; 1270 1271 u8 dbr_addr[0x40]; 1272 1273 u8 hw_counter[0x20]; 1274 1275 u8 sw_counter[0x20]; 1276 1277 u8 reserved_at_100[0xc]; 1278 u8 log_wq_stride[0x4]; 1279 u8 reserved_at_110[0x3]; 1280 u8 log_wq_pg_sz[0x5]; 1281 u8 reserved_at_118[0x3]; 1282 u8 log_wq_sz[0x5]; 1283 1284 u8 reserved_at_120[0x3]; 1285 u8 log_hairpin_num_packets[0x5]; 1286 u8 reserved_at_128[0x3]; 1287 u8 log_hairpin_data_sz[0x5]; 1288 1289 u8 reserved_at_130[0x4]; 1290 u8 log_wqe_num_of_strides[0x4]; 1291 u8 two_byte_shift_en[0x1]; 1292 u8 reserved_at_139[0x4]; 1293 u8 log_wqe_stride_size[0x3]; 1294 1295 u8 reserved_at_140[0x4c0]; 1296 1297 struct mlx5_ifc_cmd_pas_bits pas[0]; 1298 }; 1299 1300 struct mlx5_ifc_rq_num_bits { 1301 u8 reserved_at_0[0x8]; 1302 u8 rq_num[0x18]; 1303 }; 1304 1305 struct mlx5_ifc_mac_address_layout_bits { 1306 u8 reserved_at_0[0x10]; 1307 u8 mac_addr_47_32[0x10]; 1308 1309 u8 mac_addr_31_0[0x20]; 1310 }; 1311 1312 struct mlx5_ifc_vlan_layout_bits { 1313 u8 reserved_at_0[0x14]; 1314 u8 vlan[0x0c]; 1315 1316 u8 reserved_at_20[0x20]; 1317 }; 1318 1319 struct mlx5_ifc_cong_control_r_roce_ecn_np_bits { 1320 u8 reserved_at_0[0xa0]; 1321 1322 u8 min_time_between_cnps[0x20]; 1323 1324 u8 reserved_at_c0[0x12]; 1325 u8 cnp_dscp[0x6]; 1326 u8 reserved_at_d8[0x4]; 1327 u8 cnp_prio_mode[0x1]; 1328 u8 cnp_802p_prio[0x3]; 1329 1330 u8 reserved_at_e0[0x720]; 1331 }; 1332 1333 struct mlx5_ifc_cong_control_r_roce_ecn_rp_bits { 1334 u8 reserved_at_0[0x60]; 1335 1336 u8 reserved_at_60[0x4]; 1337 u8 clamp_tgt_rate[0x1]; 1338 u8 reserved_at_65[0x3]; 1339 u8 clamp_tgt_rate_after_time_inc[0x1]; 1340 u8 reserved_at_69[0x17]; 1341 1342 u8 reserved_at_80[0x20]; 1343 1344 u8 rpg_time_reset[0x20]; 1345 1346 u8 rpg_byte_reset[0x20]; 1347 1348 u8 rpg_threshold[0x20]; 1349 1350 u8 rpg_max_rate[0x20]; 1351 1352 u8 rpg_ai_rate[0x20]; 1353 1354 u8 rpg_hai_rate[0x20]; 1355 1356 u8 rpg_gd[0x20]; 1357 1358 u8 rpg_min_dec_fac[0x20]; 1359 1360 u8 rpg_min_rate[0x20]; 1361 1362 u8 reserved_at_1c0[0xe0]; 1363 1364 u8 rate_to_set_on_first_cnp[0x20]; 1365 1366 u8 dce_tcp_g[0x20]; 1367 1368 u8 dce_tcp_rtt[0x20]; 1369 1370 u8 rate_reduce_monitor_period[0x20]; 1371 1372 u8 reserved_at_320[0x20]; 1373 1374 u8 initial_alpha_value[0x20]; 1375 1376 u8 reserved_at_360[0x4a0]; 1377 }; 1378 1379 struct mlx5_ifc_cong_control_802_1qau_rp_bits { 1380 u8 reserved_at_0[0x80]; 1381 1382 u8 rppp_max_rps[0x20]; 1383 1384 u8 rpg_time_reset[0x20]; 1385 1386 u8 rpg_byte_reset[0x20]; 1387 1388 u8 rpg_threshold[0x20]; 1389 1390 u8 rpg_max_rate[0x20]; 1391 1392 u8 rpg_ai_rate[0x20]; 1393 1394 u8 rpg_hai_rate[0x20]; 1395 1396 u8 rpg_gd[0x20]; 1397 1398 u8 rpg_min_dec_fac[0x20]; 1399 1400 u8 rpg_min_rate[0x20]; 1401 1402 u8 reserved_at_1c0[0x640]; 1403 }; 1404 1405 enum { 1406 MLX5_RESIZE_FIELD_SELECT_RESIZE_FIELD_SELECT_LOG_CQ_SIZE = 0x1, 1407 MLX5_RESIZE_FIELD_SELECT_RESIZE_FIELD_SELECT_PAGE_OFFSET = 0x2, 1408 MLX5_RESIZE_FIELD_SELECT_RESIZE_FIELD_SELECT_LOG_PAGE_SIZE = 0x4, 1409 }; 1410 1411 struct mlx5_ifc_resize_field_select_bits { 1412 u8 resize_field_select[0x20]; 1413 }; 1414 1415 enum { 1416 MLX5_MODIFY_FIELD_SELECT_MODIFY_FIELD_SELECT_CQ_PERIOD = 0x1, 1417 MLX5_MODIFY_FIELD_SELECT_MODIFY_FIELD_SELECT_CQ_MAX_COUNT = 0x2, 1418 MLX5_MODIFY_FIELD_SELECT_MODIFY_FIELD_SELECT_OI = 0x4, 1419 MLX5_MODIFY_FIELD_SELECT_MODIFY_FIELD_SELECT_C_EQN = 0x8, 1420 }; 1421 1422 struct mlx5_ifc_modify_field_select_bits { 1423 u8 modify_field_select[0x20]; 1424 }; 1425 1426 struct mlx5_ifc_field_select_r_roce_np_bits { 1427 u8 field_select_r_roce_np[0x20]; 1428 }; 1429 1430 struct mlx5_ifc_field_select_r_roce_rp_bits { 1431 u8 field_select_r_roce_rp[0x20]; 1432 }; 1433 1434 enum { 1435 MLX5_FIELD_SELECT_802_1QAU_RP_FIELD_SELECT_8021QAURP_RPPP_MAX_RPS = 0x4, 1436 MLX5_FIELD_SELECT_802_1QAU_RP_FIELD_SELECT_8021QAURP_RPG_TIME_RESET = 0x8, 1437 MLX5_FIELD_SELECT_802_1QAU_RP_FIELD_SELECT_8021QAURP_RPG_BYTE_RESET = 0x10, 1438 MLX5_FIELD_SELECT_802_1QAU_RP_FIELD_SELECT_8021QAURP_RPG_THRESHOLD = 0x20, 1439 MLX5_FIELD_SELECT_802_1QAU_RP_FIELD_SELECT_8021QAURP_RPG_MAX_RATE = 0x40, 1440 MLX5_FIELD_SELECT_802_1QAU_RP_FIELD_SELECT_8021QAURP_RPG_AI_RATE = 0x80, 1441 MLX5_FIELD_SELECT_802_1QAU_RP_FIELD_SELECT_8021QAURP_RPG_HAI_RATE = 0x100, 1442 MLX5_FIELD_SELECT_802_1QAU_RP_FIELD_SELECT_8021QAURP_RPG_GD = 0x200, 1443 MLX5_FIELD_SELECT_802_1QAU_RP_FIELD_SELECT_8021QAURP_RPG_MIN_DEC_FAC = 0x400, 1444 MLX5_FIELD_SELECT_802_1QAU_RP_FIELD_SELECT_8021QAURP_RPG_MIN_RATE = 0x800, 1445 }; 1446 1447 struct mlx5_ifc_field_select_802_1qau_rp_bits { 1448 u8 field_select_8021qaurp[0x20]; 1449 }; 1450 1451 struct mlx5_ifc_phys_layer_cntrs_bits { 1452 u8 time_since_last_clear_high[0x20]; 1453 1454 u8 time_since_last_clear_low[0x20]; 1455 1456 u8 symbol_errors_high[0x20]; 1457 1458 u8 symbol_errors_low[0x20]; 1459 1460 u8 sync_headers_errors_high[0x20]; 1461 1462 u8 sync_headers_errors_low[0x20]; 1463 1464 u8 edpl_bip_errors_lane0_high[0x20]; 1465 1466 u8 edpl_bip_errors_lane0_low[0x20]; 1467 1468 u8 edpl_bip_errors_lane1_high[0x20]; 1469 1470 u8 edpl_bip_errors_lane1_low[0x20]; 1471 1472 u8 edpl_bip_errors_lane2_high[0x20]; 1473 1474 u8 edpl_bip_errors_lane2_low[0x20]; 1475 1476 u8 edpl_bip_errors_lane3_high[0x20]; 1477 1478 u8 edpl_bip_errors_lane3_low[0x20]; 1479 1480 u8 fc_fec_corrected_blocks_lane0_high[0x20]; 1481 1482 u8 fc_fec_corrected_blocks_lane0_low[0x20]; 1483 1484 u8 fc_fec_corrected_blocks_lane1_high[0x20]; 1485 1486 u8 fc_fec_corrected_blocks_lane1_low[0x20]; 1487 1488 u8 fc_fec_corrected_blocks_lane2_high[0x20]; 1489 1490 u8 fc_fec_corrected_blocks_lane2_low[0x20]; 1491 1492 u8 fc_fec_corrected_blocks_lane3_high[0x20]; 1493 1494 u8 fc_fec_corrected_blocks_lane3_low[0x20]; 1495 1496 u8 fc_fec_uncorrectable_blocks_lane0_high[0x20]; 1497 1498 u8 fc_fec_uncorrectable_blocks_lane0_low[0x20]; 1499 1500 u8 fc_fec_uncorrectable_blocks_lane1_high[0x20]; 1501 1502 u8 fc_fec_uncorrectable_blocks_lane1_low[0x20]; 1503 1504 u8 fc_fec_uncorrectable_blocks_lane2_high[0x20]; 1505 1506 u8 fc_fec_uncorrectable_blocks_lane2_low[0x20]; 1507 1508 u8 fc_fec_uncorrectable_blocks_lane3_high[0x20]; 1509 1510 u8 fc_fec_uncorrectable_blocks_lane3_low[0x20]; 1511 1512 u8 rs_fec_corrected_blocks_high[0x20]; 1513 1514 u8 rs_fec_corrected_blocks_low[0x20]; 1515 1516 u8 rs_fec_uncorrectable_blocks_high[0x20]; 1517 1518 u8 rs_fec_uncorrectable_blocks_low[0x20]; 1519 1520 u8 rs_fec_no_errors_blocks_high[0x20]; 1521 1522 u8 rs_fec_no_errors_blocks_low[0x20]; 1523 1524 u8 rs_fec_single_error_blocks_high[0x20]; 1525 1526 u8 rs_fec_single_error_blocks_low[0x20]; 1527 1528 u8 rs_fec_corrected_symbols_total_high[0x20]; 1529 1530 u8 rs_fec_corrected_symbols_total_low[0x20]; 1531 1532 u8 rs_fec_corrected_symbols_lane0_high[0x20]; 1533 1534 u8 rs_fec_corrected_symbols_lane0_low[0x20]; 1535 1536 u8 rs_fec_corrected_symbols_lane1_high[0x20]; 1537 1538 u8 rs_fec_corrected_symbols_lane1_low[0x20]; 1539 1540 u8 rs_fec_corrected_symbols_lane2_high[0x20]; 1541 1542 u8 rs_fec_corrected_symbols_lane2_low[0x20]; 1543 1544 u8 rs_fec_corrected_symbols_lane3_high[0x20]; 1545 1546 u8 rs_fec_corrected_symbols_lane3_low[0x20]; 1547 1548 u8 link_down_events[0x20]; 1549 1550 u8 successful_recovery_events[0x20]; 1551 1552 u8 reserved_at_640[0x180]; 1553 }; 1554 1555 struct mlx5_ifc_phys_layer_statistical_cntrs_bits { 1556 u8 time_since_last_clear_high[0x20]; 1557 1558 u8 time_since_last_clear_low[0x20]; 1559 1560 u8 phy_received_bits_high[0x20]; 1561 1562 u8 phy_received_bits_low[0x20]; 1563 1564 u8 phy_symbol_errors_high[0x20]; 1565 1566 u8 phy_symbol_errors_low[0x20]; 1567 1568 u8 phy_corrected_bits_high[0x20]; 1569 1570 u8 phy_corrected_bits_low[0x20]; 1571 1572 u8 phy_corrected_bits_lane0_high[0x20]; 1573 1574 u8 phy_corrected_bits_lane0_low[0x20]; 1575 1576 u8 phy_corrected_bits_lane1_high[0x20]; 1577 1578 u8 phy_corrected_bits_lane1_low[0x20]; 1579 1580 u8 phy_corrected_bits_lane2_high[0x20]; 1581 1582 u8 phy_corrected_bits_lane2_low[0x20]; 1583 1584 u8 phy_corrected_bits_lane3_high[0x20]; 1585 1586 u8 phy_corrected_bits_lane3_low[0x20]; 1587 1588 u8 reserved_at_200[0x5c0]; 1589 }; 1590 1591 struct mlx5_ifc_ib_port_cntrs_grp_data_layout_bits { 1592 u8 symbol_error_counter[0x10]; 1593 1594 u8 link_error_recovery_counter[0x8]; 1595 1596 u8 link_downed_counter[0x8]; 1597 1598 u8 port_rcv_errors[0x10]; 1599 1600 u8 port_rcv_remote_physical_errors[0x10]; 1601 1602 u8 port_rcv_switch_relay_errors[0x10]; 1603 1604 u8 port_xmit_discards[0x10]; 1605 1606 u8 port_xmit_constraint_errors[0x8]; 1607 1608 u8 port_rcv_constraint_errors[0x8]; 1609 1610 u8 reserved_at_70[0x8]; 1611 1612 u8 link_overrun_errors[0x8]; 1613 1614 u8 reserved_at_80[0x10]; 1615 1616 u8 vl_15_dropped[0x10]; 1617 1618 u8 reserved_at_a0[0x80]; 1619 1620 u8 port_xmit_wait[0x20]; 1621 }; 1622 1623 struct mlx5_ifc_eth_per_traffic_grp_data_layout_bits { 1624 u8 transmit_queue_high[0x20]; 1625 1626 u8 transmit_queue_low[0x20]; 1627 1628 u8 reserved_at_40[0x780]; 1629 }; 1630 1631 struct mlx5_ifc_eth_per_prio_grp_data_layout_bits { 1632 u8 rx_octets_high[0x20]; 1633 1634 u8 rx_octets_low[0x20]; 1635 1636 u8 reserved_at_40[0xc0]; 1637 1638 u8 rx_frames_high[0x20]; 1639 1640 u8 rx_frames_low[0x20]; 1641 1642 u8 tx_octets_high[0x20]; 1643 1644 u8 tx_octets_low[0x20]; 1645 1646 u8 reserved_at_180[0xc0]; 1647 1648 u8 tx_frames_high[0x20]; 1649 1650 u8 tx_frames_low[0x20]; 1651 1652 u8 rx_pause_high[0x20]; 1653 1654 u8 rx_pause_low[0x20]; 1655 1656 u8 rx_pause_duration_high[0x20]; 1657 1658 u8 rx_pause_duration_low[0x20]; 1659 1660 u8 tx_pause_high[0x20]; 1661 1662 u8 tx_pause_low[0x20]; 1663 1664 u8 tx_pause_duration_high[0x20]; 1665 1666 u8 tx_pause_duration_low[0x20]; 1667 1668 u8 rx_pause_transition_high[0x20]; 1669 1670 u8 rx_pause_transition_low[0x20]; 1671 1672 u8 reserved_at_3c0[0x40]; 1673 1674 u8 device_stall_minor_watermark_cnt_high[0x20]; 1675 1676 u8 device_stall_minor_watermark_cnt_low[0x20]; 1677 1678 u8 device_stall_critical_watermark_cnt_high[0x20]; 1679 1680 u8 device_stall_critical_watermark_cnt_low[0x20]; 1681 1682 u8 reserved_at_480[0x340]; 1683 }; 1684 1685 struct mlx5_ifc_eth_extended_cntrs_grp_data_layout_bits { 1686 u8 port_transmit_wait_high[0x20]; 1687 1688 u8 port_transmit_wait_low[0x20]; 1689 1690 u8 reserved_at_40[0x100]; 1691 1692 u8 rx_buffer_almost_full_high[0x20]; 1693 1694 u8 rx_buffer_almost_full_low[0x20]; 1695 1696 u8 rx_buffer_full_high[0x20]; 1697 1698 u8 rx_buffer_full_low[0x20]; 1699 1700 u8 rx_icrc_encapsulated_high[0x20]; 1701 1702 u8 rx_icrc_encapsulated_low[0x20]; 1703 1704 u8 reserved_at_200[0x5c0]; 1705 }; 1706 1707 struct mlx5_ifc_eth_3635_cntrs_grp_data_layout_bits { 1708 u8 dot3stats_alignment_errors_high[0x20]; 1709 1710 u8 dot3stats_alignment_errors_low[0x20]; 1711 1712 u8 dot3stats_fcs_errors_high[0x20]; 1713 1714 u8 dot3stats_fcs_errors_low[0x20]; 1715 1716 u8 dot3stats_single_collision_frames_high[0x20]; 1717 1718 u8 dot3stats_single_collision_frames_low[0x20]; 1719 1720 u8 dot3stats_multiple_collision_frames_high[0x20]; 1721 1722 u8 dot3stats_multiple_collision_frames_low[0x20]; 1723 1724 u8 dot3stats_sqe_test_errors_high[0x20]; 1725 1726 u8 dot3stats_sqe_test_errors_low[0x20]; 1727 1728 u8 dot3stats_deferred_transmissions_high[0x20]; 1729 1730 u8 dot3stats_deferred_transmissions_low[0x20]; 1731 1732 u8 dot3stats_late_collisions_high[0x20]; 1733 1734 u8 dot3stats_late_collisions_low[0x20]; 1735 1736 u8 dot3stats_excessive_collisions_high[0x20]; 1737 1738 u8 dot3stats_excessive_collisions_low[0x20]; 1739 1740 u8 dot3stats_internal_mac_transmit_errors_high[0x20]; 1741 1742 u8 dot3stats_internal_mac_transmit_errors_low[0x20]; 1743 1744 u8 dot3stats_carrier_sense_errors_high[0x20]; 1745 1746 u8 dot3stats_carrier_sense_errors_low[0x20]; 1747 1748 u8 dot3stats_frame_too_longs_high[0x20]; 1749 1750 u8 dot3stats_frame_too_longs_low[0x20]; 1751 1752 u8 dot3stats_internal_mac_receive_errors_high[0x20]; 1753 1754 u8 dot3stats_internal_mac_receive_errors_low[0x20]; 1755 1756 u8 dot3stats_symbol_errors_high[0x20]; 1757 1758 u8 dot3stats_symbol_errors_low[0x20]; 1759 1760 u8 dot3control_in_unknown_opcodes_high[0x20]; 1761 1762 u8 dot3control_in_unknown_opcodes_low[0x20]; 1763 1764 u8 dot3in_pause_frames_high[0x20]; 1765 1766 u8 dot3in_pause_frames_low[0x20]; 1767 1768 u8 dot3out_pause_frames_high[0x20]; 1769 1770 u8 dot3out_pause_frames_low[0x20]; 1771 1772 u8 reserved_at_400[0x3c0]; 1773 }; 1774 1775 struct mlx5_ifc_eth_2819_cntrs_grp_data_layout_bits { 1776 u8 ether_stats_drop_events_high[0x20]; 1777 1778 u8 ether_stats_drop_events_low[0x20]; 1779 1780 u8 ether_stats_octets_high[0x20]; 1781 1782 u8 ether_stats_octets_low[0x20]; 1783 1784 u8 ether_stats_pkts_high[0x20]; 1785 1786 u8 ether_stats_pkts_low[0x20]; 1787 1788 u8 ether_stats_broadcast_pkts_high[0x20]; 1789 1790 u8 ether_stats_broadcast_pkts_low[0x20]; 1791 1792 u8 ether_stats_multicast_pkts_high[0x20]; 1793 1794 u8 ether_stats_multicast_pkts_low[0x20]; 1795 1796 u8 ether_stats_crc_align_errors_high[0x20]; 1797 1798 u8 ether_stats_crc_align_errors_low[0x20]; 1799 1800 u8 ether_stats_undersize_pkts_high[0x20]; 1801 1802 u8 ether_stats_undersize_pkts_low[0x20]; 1803 1804 u8 ether_stats_oversize_pkts_high[0x20]; 1805 1806 u8 ether_stats_oversize_pkts_low[0x20]; 1807 1808 u8 ether_stats_fragments_high[0x20]; 1809 1810 u8 ether_stats_fragments_low[0x20]; 1811 1812 u8 ether_stats_jabbers_high[0x20]; 1813 1814 u8 ether_stats_jabbers_low[0x20]; 1815 1816 u8 ether_stats_collisions_high[0x20]; 1817 1818 u8 ether_stats_collisions_low[0x20]; 1819 1820 u8 ether_stats_pkts64octets_high[0x20]; 1821 1822 u8 ether_stats_pkts64octets_low[0x20]; 1823 1824 u8 ether_stats_pkts65to127octets_high[0x20]; 1825 1826 u8 ether_stats_pkts65to127octets_low[0x20]; 1827 1828 u8 ether_stats_pkts128to255octets_high[0x20]; 1829 1830 u8 ether_stats_pkts128to255octets_low[0x20]; 1831 1832 u8 ether_stats_pkts256to511octets_high[0x20]; 1833 1834 u8 ether_stats_pkts256to511octets_low[0x20]; 1835 1836 u8 ether_stats_pkts512to1023octets_high[0x20]; 1837 1838 u8 ether_stats_pkts512to1023octets_low[0x20]; 1839 1840 u8 ether_stats_pkts1024to1518octets_high[0x20]; 1841 1842 u8 ether_stats_pkts1024to1518octets_low[0x20]; 1843 1844 u8 ether_stats_pkts1519to2047octets_high[0x20]; 1845 1846 u8 ether_stats_pkts1519to2047octets_low[0x20]; 1847 1848 u8 ether_stats_pkts2048to4095octets_high[0x20]; 1849 1850 u8 ether_stats_pkts2048to4095octets_low[0x20]; 1851 1852 u8 ether_stats_pkts4096to8191octets_high[0x20]; 1853 1854 u8 ether_stats_pkts4096to8191octets_low[0x20]; 1855 1856 u8 ether_stats_pkts8192to10239octets_high[0x20]; 1857 1858 u8 ether_stats_pkts8192to10239octets_low[0x20]; 1859 1860 u8 reserved_at_540[0x280]; 1861 }; 1862 1863 struct mlx5_ifc_eth_2863_cntrs_grp_data_layout_bits { 1864 u8 if_in_octets_high[0x20]; 1865 1866 u8 if_in_octets_low[0x20]; 1867 1868 u8 if_in_ucast_pkts_high[0x20]; 1869 1870 u8 if_in_ucast_pkts_low[0x20]; 1871 1872 u8 if_in_discards_high[0x20]; 1873 1874 u8 if_in_discards_low[0x20]; 1875 1876 u8 if_in_errors_high[0x20]; 1877 1878 u8 if_in_errors_low[0x20]; 1879 1880 u8 if_in_unknown_protos_high[0x20]; 1881 1882 u8 if_in_unknown_protos_low[0x20]; 1883 1884 u8 if_out_octets_high[0x20]; 1885 1886 u8 if_out_octets_low[0x20]; 1887 1888 u8 if_out_ucast_pkts_high[0x20]; 1889 1890 u8 if_out_ucast_pkts_low[0x20]; 1891 1892 u8 if_out_discards_high[0x20]; 1893 1894 u8 if_out_discards_low[0x20]; 1895 1896 u8 if_out_errors_high[0x20]; 1897 1898 u8 if_out_errors_low[0x20]; 1899 1900 u8 if_in_multicast_pkts_high[0x20]; 1901 1902 u8 if_in_multicast_pkts_low[0x20]; 1903 1904 u8 if_in_broadcast_pkts_high[0x20]; 1905 1906 u8 if_in_broadcast_pkts_low[0x20]; 1907 1908 u8 if_out_multicast_pkts_high[0x20]; 1909 1910 u8 if_out_multicast_pkts_low[0x20]; 1911 1912 u8 if_out_broadcast_pkts_high[0x20]; 1913 1914 u8 if_out_broadcast_pkts_low[0x20]; 1915 1916 u8 reserved_at_340[0x480]; 1917 }; 1918 1919 struct mlx5_ifc_eth_802_3_cntrs_grp_data_layout_bits { 1920 u8 a_frames_transmitted_ok_high[0x20]; 1921 1922 u8 a_frames_transmitted_ok_low[0x20]; 1923 1924 u8 a_frames_received_ok_high[0x20]; 1925 1926 u8 a_frames_received_ok_low[0x20]; 1927 1928 u8 a_frame_check_sequence_errors_high[0x20]; 1929 1930 u8 a_frame_check_sequence_errors_low[0x20]; 1931 1932 u8 a_alignment_errors_high[0x20]; 1933 1934 u8 a_alignment_errors_low[0x20]; 1935 1936 u8 a_octets_transmitted_ok_high[0x20]; 1937 1938 u8 a_octets_transmitted_ok_low[0x20]; 1939 1940 u8 a_octets_received_ok_high[0x20]; 1941 1942 u8 a_octets_received_ok_low[0x20]; 1943 1944 u8 a_multicast_frames_xmitted_ok_high[0x20]; 1945 1946 u8 a_multicast_frames_xmitted_ok_low[0x20]; 1947 1948 u8 a_broadcast_frames_xmitted_ok_high[0x20]; 1949 1950 u8 a_broadcast_frames_xmitted_ok_low[0x20]; 1951 1952 u8 a_multicast_frames_received_ok_high[0x20]; 1953 1954 u8 a_multicast_frames_received_ok_low[0x20]; 1955 1956 u8 a_broadcast_frames_received_ok_high[0x20]; 1957 1958 u8 a_broadcast_frames_received_ok_low[0x20]; 1959 1960 u8 a_in_range_length_errors_high[0x20]; 1961 1962 u8 a_in_range_length_errors_low[0x20]; 1963 1964 u8 a_out_of_range_length_field_high[0x20]; 1965 1966 u8 a_out_of_range_length_field_low[0x20]; 1967 1968 u8 a_frame_too_long_errors_high[0x20]; 1969 1970 u8 a_frame_too_long_errors_low[0x20]; 1971 1972 u8 a_symbol_error_during_carrier_high[0x20]; 1973 1974 u8 a_symbol_error_during_carrier_low[0x20]; 1975 1976 u8 a_mac_control_frames_transmitted_high[0x20]; 1977 1978 u8 a_mac_control_frames_transmitted_low[0x20]; 1979 1980 u8 a_mac_control_frames_received_high[0x20]; 1981 1982 u8 a_mac_control_frames_received_low[0x20]; 1983 1984 u8 a_unsupported_opcodes_received_high[0x20]; 1985 1986 u8 a_unsupported_opcodes_received_low[0x20]; 1987 1988 u8 a_pause_mac_ctrl_frames_received_high[0x20]; 1989 1990 u8 a_pause_mac_ctrl_frames_received_low[0x20]; 1991 1992 u8 a_pause_mac_ctrl_frames_transmitted_high[0x20]; 1993 1994 u8 a_pause_mac_ctrl_frames_transmitted_low[0x20]; 1995 1996 u8 reserved_at_4c0[0x300]; 1997 }; 1998 1999 struct mlx5_ifc_pcie_perf_cntrs_grp_data_layout_bits { 2000 u8 life_time_counter_high[0x20]; 2001 2002 u8 life_time_counter_low[0x20]; 2003 2004 u8 rx_errors[0x20]; 2005 2006 u8 tx_errors[0x20]; 2007 2008 u8 l0_to_recovery_eieos[0x20]; 2009 2010 u8 l0_to_recovery_ts[0x20]; 2011 2012 u8 l0_to_recovery_framing[0x20]; 2013 2014 u8 l0_to_recovery_retrain[0x20]; 2015 2016 u8 crc_error_dllp[0x20]; 2017 2018 u8 crc_error_tlp[0x20]; 2019 2020 u8 tx_overflow_buffer_pkt_high[0x20]; 2021 2022 u8 tx_overflow_buffer_pkt_low[0x20]; 2023 2024 u8 outbound_stalled_reads[0x20]; 2025 2026 u8 outbound_stalled_writes[0x20]; 2027 2028 u8 outbound_stalled_reads_events[0x20]; 2029 2030 u8 outbound_stalled_writes_events[0x20]; 2031 2032 u8 reserved_at_200[0x5c0]; 2033 }; 2034 2035 struct mlx5_ifc_cmd_inter_comp_event_bits { 2036 u8 command_completion_vector[0x20]; 2037 2038 u8 reserved_at_20[0xc0]; 2039 }; 2040 2041 struct mlx5_ifc_stall_vl_event_bits { 2042 u8 reserved_at_0[0x18]; 2043 u8 port_num[0x1]; 2044 u8 reserved_at_19[0x3]; 2045 u8 vl[0x4]; 2046 2047 u8 reserved_at_20[0xa0]; 2048 }; 2049 2050 struct mlx5_ifc_db_bf_congestion_event_bits { 2051 u8 event_subtype[0x8]; 2052 u8 reserved_at_8[0x8]; 2053 u8 congestion_level[0x8]; 2054 u8 reserved_at_18[0x8]; 2055 2056 u8 reserved_at_20[0xa0]; 2057 }; 2058 2059 struct mlx5_ifc_gpio_event_bits { 2060 u8 reserved_at_0[0x60]; 2061 2062 u8 gpio_event_hi[0x20]; 2063 2064 u8 gpio_event_lo[0x20]; 2065 2066 u8 reserved_at_a0[0x40]; 2067 }; 2068 2069 struct mlx5_ifc_port_state_change_event_bits { 2070 u8 reserved_at_0[0x40]; 2071 2072 u8 port_num[0x4]; 2073 u8 reserved_at_44[0x1c]; 2074 2075 u8 reserved_at_60[0x80]; 2076 }; 2077 2078 struct mlx5_ifc_dropped_packet_logged_bits { 2079 u8 reserved_at_0[0xe0]; 2080 }; 2081 2082 enum { 2083 MLX5_CQ_ERROR_SYNDROME_CQ_OVERRUN = 0x1, 2084 MLX5_CQ_ERROR_SYNDROME_CQ_ACCESS_VIOLATION_ERROR = 0x2, 2085 }; 2086 2087 struct mlx5_ifc_cq_error_bits { 2088 u8 reserved_at_0[0x8]; 2089 u8 cqn[0x18]; 2090 2091 u8 reserved_at_20[0x20]; 2092 2093 u8 reserved_at_40[0x18]; 2094 u8 syndrome[0x8]; 2095 2096 u8 reserved_at_60[0x80]; 2097 }; 2098 2099 struct mlx5_ifc_rdma_page_fault_event_bits { 2100 u8 bytes_committed[0x20]; 2101 2102 u8 r_key[0x20]; 2103 2104 u8 reserved_at_40[0x10]; 2105 u8 packet_len[0x10]; 2106 2107 u8 rdma_op_len[0x20]; 2108 2109 u8 rdma_va[0x40]; 2110 2111 u8 reserved_at_c0[0x5]; 2112 u8 rdma[0x1]; 2113 u8 write[0x1]; 2114 u8 requestor[0x1]; 2115 u8 qp_number[0x18]; 2116 }; 2117 2118 struct mlx5_ifc_wqe_associated_page_fault_event_bits { 2119 u8 bytes_committed[0x20]; 2120 2121 u8 reserved_at_20[0x10]; 2122 u8 wqe_index[0x10]; 2123 2124 u8 reserved_at_40[0x10]; 2125 u8 len[0x10]; 2126 2127 u8 reserved_at_60[0x60]; 2128 2129 u8 reserved_at_c0[0x5]; 2130 u8 rdma[0x1]; 2131 u8 write_read[0x1]; 2132 u8 requestor[0x1]; 2133 u8 qpn[0x18]; 2134 }; 2135 2136 struct mlx5_ifc_qp_events_bits { 2137 u8 reserved_at_0[0xa0]; 2138 2139 u8 type[0x8]; 2140 u8 reserved_at_a8[0x18]; 2141 2142 u8 reserved_at_c0[0x8]; 2143 u8 qpn_rqn_sqn[0x18]; 2144 }; 2145 2146 struct mlx5_ifc_dct_events_bits { 2147 u8 reserved_at_0[0xc0]; 2148 2149 u8 reserved_at_c0[0x8]; 2150 u8 dct_number[0x18]; 2151 }; 2152 2153 struct mlx5_ifc_comp_event_bits { 2154 u8 reserved_at_0[0xc0]; 2155 2156 u8 reserved_at_c0[0x8]; 2157 u8 cq_number[0x18]; 2158 }; 2159 2160 enum { 2161 MLX5_QPC_STATE_RST = 0x0, 2162 MLX5_QPC_STATE_INIT = 0x1, 2163 MLX5_QPC_STATE_RTR = 0x2, 2164 MLX5_QPC_STATE_RTS = 0x3, 2165 MLX5_QPC_STATE_SQER = 0x4, 2166 MLX5_QPC_STATE_ERR = 0x6, 2167 MLX5_QPC_STATE_SQD = 0x7, 2168 MLX5_QPC_STATE_SUSPENDED = 0x9, 2169 }; 2170 2171 enum { 2172 MLX5_QPC_ST_RC = 0x0, 2173 MLX5_QPC_ST_UC = 0x1, 2174 MLX5_QPC_ST_UD = 0x2, 2175 MLX5_QPC_ST_XRC = 0x3, 2176 MLX5_QPC_ST_DCI = 0x5, 2177 MLX5_QPC_ST_QP0 = 0x7, 2178 MLX5_QPC_ST_QP1 = 0x8, 2179 MLX5_QPC_ST_RAW_DATAGRAM = 0x9, 2180 MLX5_QPC_ST_REG_UMR = 0xc, 2181 }; 2182 2183 enum { 2184 MLX5_QPC_PM_STATE_ARMED = 0x0, 2185 MLX5_QPC_PM_STATE_REARM = 0x1, 2186 MLX5_QPC_PM_STATE_RESERVED = 0x2, 2187 MLX5_QPC_PM_STATE_MIGRATED = 0x3, 2188 }; 2189 2190 enum { 2191 MLX5_QPC_OFFLOAD_TYPE_RNDV = 0x1, 2192 }; 2193 2194 enum { 2195 MLX5_QPC_END_PADDING_MODE_SCATTER_AS_IS = 0x0, 2196 MLX5_QPC_END_PADDING_MODE_PAD_TO_CACHE_LINE_ALIGNMENT = 0x1, 2197 }; 2198 2199 enum { 2200 MLX5_QPC_MTU_256_BYTES = 0x1, 2201 MLX5_QPC_MTU_512_BYTES = 0x2, 2202 MLX5_QPC_MTU_1K_BYTES = 0x3, 2203 MLX5_QPC_MTU_2K_BYTES = 0x4, 2204 MLX5_QPC_MTU_4K_BYTES = 0x5, 2205 MLX5_QPC_MTU_RAW_ETHERNET_QP = 0x7, 2206 }; 2207 2208 enum { 2209 MLX5_QPC_ATOMIC_MODE_IB_SPEC = 0x1, 2210 MLX5_QPC_ATOMIC_MODE_ONLY_8B = 0x2, 2211 MLX5_QPC_ATOMIC_MODE_UP_TO_8B = 0x3, 2212 MLX5_QPC_ATOMIC_MODE_UP_TO_16B = 0x4, 2213 MLX5_QPC_ATOMIC_MODE_UP_TO_32B = 0x5, 2214 MLX5_QPC_ATOMIC_MODE_UP_TO_64B = 0x6, 2215 MLX5_QPC_ATOMIC_MODE_UP_TO_128B = 0x7, 2216 MLX5_QPC_ATOMIC_MODE_UP_TO_256B = 0x8, 2217 }; 2218 2219 enum { 2220 MLX5_QPC_CS_REQ_DISABLE = 0x0, 2221 MLX5_QPC_CS_REQ_UP_TO_32B = 0x11, 2222 MLX5_QPC_CS_REQ_UP_TO_64B = 0x22, 2223 }; 2224 2225 enum { 2226 MLX5_QPC_CS_RES_DISABLE = 0x0, 2227 MLX5_QPC_CS_RES_UP_TO_32B = 0x1, 2228 MLX5_QPC_CS_RES_UP_TO_64B = 0x2, 2229 }; 2230 2231 struct mlx5_ifc_qpc_bits { 2232 u8 state[0x4]; 2233 u8 lag_tx_port_affinity[0x4]; 2234 u8 st[0x8]; 2235 u8 reserved_at_10[0x3]; 2236 u8 pm_state[0x2]; 2237 u8 reserved_at_15[0x3]; 2238 u8 offload_type[0x4]; 2239 u8 end_padding_mode[0x2]; 2240 u8 reserved_at_1e[0x2]; 2241 2242 u8 wq_signature[0x1]; 2243 u8 block_lb_mc[0x1]; 2244 u8 atomic_like_write_en[0x1]; 2245 u8 latency_sensitive[0x1]; 2246 u8 reserved_at_24[0x1]; 2247 u8 drain_sigerr[0x1]; 2248 u8 reserved_at_26[0x2]; 2249 u8 pd[0x18]; 2250 2251 u8 mtu[0x3]; 2252 u8 log_msg_max[0x5]; 2253 u8 reserved_at_48[0x1]; 2254 u8 log_rq_size[0x4]; 2255 u8 log_rq_stride[0x3]; 2256 u8 no_sq[0x1]; 2257 u8 log_sq_size[0x4]; 2258 u8 reserved_at_55[0x6]; 2259 u8 rlky[0x1]; 2260 u8 ulp_stateless_offload_mode[0x4]; 2261 2262 u8 counter_set_id[0x8]; 2263 u8 uar_page[0x18]; 2264 2265 u8 reserved_at_80[0x8]; 2266 u8 user_index[0x18]; 2267 2268 u8 reserved_at_a0[0x3]; 2269 u8 log_page_size[0x5]; 2270 u8 remote_qpn[0x18]; 2271 2272 struct mlx5_ifc_ads_bits primary_address_path; 2273 2274 struct mlx5_ifc_ads_bits secondary_address_path; 2275 2276 u8 log_ack_req_freq[0x4]; 2277 u8 reserved_at_384[0x4]; 2278 u8 log_sra_max[0x3]; 2279 u8 reserved_at_38b[0x2]; 2280 u8 retry_count[0x3]; 2281 u8 rnr_retry[0x3]; 2282 u8 reserved_at_393[0x1]; 2283 u8 fre[0x1]; 2284 u8 cur_rnr_retry[0x3]; 2285 u8 cur_retry_count[0x3]; 2286 u8 reserved_at_39b[0x5]; 2287 2288 u8 reserved_at_3a0[0x20]; 2289 2290 u8 reserved_at_3c0[0x8]; 2291 u8 next_send_psn[0x18]; 2292 2293 u8 reserved_at_3e0[0x8]; 2294 u8 cqn_snd[0x18]; 2295 2296 u8 reserved_at_400[0x8]; 2297 u8 deth_sqpn[0x18]; 2298 2299 u8 reserved_at_420[0x20]; 2300 2301 u8 reserved_at_440[0x8]; 2302 u8 last_acked_psn[0x18]; 2303 2304 u8 reserved_at_460[0x8]; 2305 u8 ssn[0x18]; 2306 2307 u8 reserved_at_480[0x8]; 2308 u8 log_rra_max[0x3]; 2309 u8 reserved_at_48b[0x1]; 2310 u8 atomic_mode[0x4]; 2311 u8 rre[0x1]; 2312 u8 rwe[0x1]; 2313 u8 rae[0x1]; 2314 u8 reserved_at_493[0x1]; 2315 u8 page_offset[0x6]; 2316 u8 reserved_at_49a[0x3]; 2317 u8 cd_slave_receive[0x1]; 2318 u8 cd_slave_send[0x1]; 2319 u8 cd_master[0x1]; 2320 2321 u8 reserved_at_4a0[0x3]; 2322 u8 min_rnr_nak[0x5]; 2323 u8 next_rcv_psn[0x18]; 2324 2325 u8 reserved_at_4c0[0x8]; 2326 u8 xrcd[0x18]; 2327 2328 u8 reserved_at_4e0[0x8]; 2329 u8 cqn_rcv[0x18]; 2330 2331 u8 dbr_addr[0x40]; 2332 2333 u8 q_key[0x20]; 2334 2335 u8 reserved_at_560[0x5]; 2336 u8 rq_type[0x3]; 2337 u8 srqn_rmpn_xrqn[0x18]; 2338 2339 u8 reserved_at_580[0x8]; 2340 u8 rmsn[0x18]; 2341 2342 u8 hw_sq_wqebb_counter[0x10]; 2343 u8 sw_sq_wqebb_counter[0x10]; 2344 2345 u8 hw_rq_counter[0x20]; 2346 2347 u8 sw_rq_counter[0x20]; 2348 2349 u8 reserved_at_600[0x20]; 2350 2351 u8 reserved_at_620[0xf]; 2352 u8 cgs[0x1]; 2353 u8 cs_req[0x8]; 2354 u8 cs_res[0x8]; 2355 2356 u8 dc_access_key[0x40]; 2357 2358 u8 reserved_at_680[0xc0]; 2359 }; 2360 2361 struct mlx5_ifc_roce_addr_layout_bits { 2362 u8 source_l3_address[16][0x8]; 2363 2364 u8 reserved_at_80[0x3]; 2365 u8 vlan_valid[0x1]; 2366 u8 vlan_id[0xc]; 2367 u8 source_mac_47_32[0x10]; 2368 2369 u8 source_mac_31_0[0x20]; 2370 2371 u8 reserved_at_c0[0x14]; 2372 u8 roce_l3_type[0x4]; 2373 u8 roce_version[0x8]; 2374 2375 u8 reserved_at_e0[0x20]; 2376 }; 2377 2378 union mlx5_ifc_hca_cap_union_bits { 2379 struct mlx5_ifc_cmd_hca_cap_bits cmd_hca_cap; 2380 struct mlx5_ifc_odp_cap_bits odp_cap; 2381 struct mlx5_ifc_atomic_caps_bits atomic_caps; 2382 struct mlx5_ifc_roce_cap_bits roce_cap; 2383 struct mlx5_ifc_per_protocol_networking_offload_caps_bits per_protocol_networking_offload_caps; 2384 struct mlx5_ifc_flow_table_nic_cap_bits flow_table_nic_cap; 2385 struct mlx5_ifc_flow_table_eswitch_cap_bits flow_table_eswitch_cap; 2386 struct mlx5_ifc_e_switch_cap_bits e_switch_cap; 2387 struct mlx5_ifc_vector_calc_cap_bits vector_calc_cap; 2388 struct mlx5_ifc_qos_cap_bits qos_cap; 2389 struct mlx5_ifc_fpga_cap_bits fpga_cap; 2390 u8 reserved_at_0[0x8000]; 2391 }; 2392 2393 enum { 2394 MLX5_FLOW_CONTEXT_ACTION_ALLOW = 0x1, 2395 MLX5_FLOW_CONTEXT_ACTION_DROP = 0x2, 2396 MLX5_FLOW_CONTEXT_ACTION_FWD_DEST = 0x4, 2397 MLX5_FLOW_CONTEXT_ACTION_COUNT = 0x8, 2398 MLX5_FLOW_CONTEXT_ACTION_ENCAP = 0x10, 2399 MLX5_FLOW_CONTEXT_ACTION_DECAP = 0x20, 2400 MLX5_FLOW_CONTEXT_ACTION_MOD_HDR = 0x40, 2401 MLX5_FLOW_CONTEXT_ACTION_VLAN_POP = 0x80, 2402 MLX5_FLOW_CONTEXT_ACTION_VLAN_PUSH = 0x100, 2403 MLX5_FLOW_CONTEXT_ACTION_VLAN_POP_2 = 0x400, 2404 MLX5_FLOW_CONTEXT_ACTION_VLAN_PUSH_2 = 0x800, 2405 }; 2406 2407 struct mlx5_ifc_vlan_bits { 2408 u8 ethtype[0x10]; 2409 u8 prio[0x3]; 2410 u8 cfi[0x1]; 2411 u8 vid[0xc]; 2412 }; 2413 2414 struct mlx5_ifc_flow_context_bits { 2415 struct mlx5_ifc_vlan_bits push_vlan; 2416 2417 u8 group_id[0x20]; 2418 2419 u8 reserved_at_40[0x8]; 2420 u8 flow_tag[0x18]; 2421 2422 u8 reserved_at_60[0x10]; 2423 u8 action[0x10]; 2424 2425 u8 reserved_at_80[0x8]; 2426 u8 destination_list_size[0x18]; 2427 2428 u8 reserved_at_a0[0x8]; 2429 u8 flow_counter_list_size[0x18]; 2430 2431 u8 encap_id[0x20]; 2432 2433 u8 modify_header_id[0x20]; 2434 2435 struct mlx5_ifc_vlan_bits push_vlan_2; 2436 2437 u8 reserved_at_120[0xe0]; 2438 2439 struct mlx5_ifc_fte_match_param_bits match_value; 2440 2441 u8 reserved_at_1200[0x600]; 2442 2443 union mlx5_ifc_dest_format_struct_flow_counter_list_auto_bits destination[0]; 2444 }; 2445 2446 enum { 2447 MLX5_XRC_SRQC_STATE_GOOD = 0x0, 2448 MLX5_XRC_SRQC_STATE_ERROR = 0x1, 2449 }; 2450 2451 struct mlx5_ifc_xrc_srqc_bits { 2452 u8 state[0x4]; 2453 u8 log_xrc_srq_size[0x4]; 2454 u8 reserved_at_8[0x18]; 2455 2456 u8 wq_signature[0x1]; 2457 u8 cont_srq[0x1]; 2458 u8 reserved_at_22[0x1]; 2459 u8 rlky[0x1]; 2460 u8 basic_cyclic_rcv_wqe[0x1]; 2461 u8 log_rq_stride[0x3]; 2462 u8 xrcd[0x18]; 2463 2464 u8 page_offset[0x6]; 2465 u8 reserved_at_46[0x2]; 2466 u8 cqn[0x18]; 2467 2468 u8 reserved_at_60[0x20]; 2469 2470 u8 user_index_equal_xrc_srqn[0x1]; 2471 u8 reserved_at_81[0x1]; 2472 u8 log_page_size[0x6]; 2473 u8 user_index[0x18]; 2474 2475 u8 reserved_at_a0[0x20]; 2476 2477 u8 reserved_at_c0[0x8]; 2478 u8 pd[0x18]; 2479 2480 u8 lwm[0x10]; 2481 u8 wqe_cnt[0x10]; 2482 2483 u8 reserved_at_100[0x40]; 2484 2485 u8 db_record_addr_h[0x20]; 2486 2487 u8 db_record_addr_l[0x1e]; 2488 u8 reserved_at_17e[0x2]; 2489 2490 u8 reserved_at_180[0x80]; 2491 }; 2492 2493 struct mlx5_ifc_vnic_diagnostic_statistics_bits { 2494 u8 counter_error_queues[0x20]; 2495 2496 u8 total_error_queues[0x20]; 2497 2498 u8 send_queue_priority_update_flow[0x20]; 2499 2500 u8 reserved_at_60[0x20]; 2501 2502 u8 nic_receive_steering_discard[0x40]; 2503 2504 u8 receive_discard_vport_down[0x40]; 2505 2506 u8 transmit_discard_vport_down[0x40]; 2507 2508 u8 reserved_at_140[0xec0]; 2509 }; 2510 2511 struct mlx5_ifc_traffic_counter_bits { 2512 u8 packets[0x40]; 2513 2514 u8 octets[0x40]; 2515 }; 2516 2517 struct mlx5_ifc_tisc_bits { 2518 u8 strict_lag_tx_port_affinity[0x1]; 2519 u8 reserved_at_1[0x3]; 2520 u8 lag_tx_port_affinity[0x04]; 2521 2522 u8 reserved_at_8[0x4]; 2523 u8 prio[0x4]; 2524 u8 reserved_at_10[0x10]; 2525 2526 u8 reserved_at_20[0x100]; 2527 2528 u8 reserved_at_120[0x8]; 2529 u8 transport_domain[0x18]; 2530 2531 u8 reserved_at_140[0x8]; 2532 u8 underlay_qpn[0x18]; 2533 u8 reserved_at_160[0x3a0]; 2534 }; 2535 2536 enum { 2537 MLX5_TIRC_DISP_TYPE_DIRECT = 0x0, 2538 MLX5_TIRC_DISP_TYPE_INDIRECT = 0x1, 2539 }; 2540 2541 enum { 2542 MLX5_TIRC_LRO_ENABLE_MASK_IPV4_LRO = 0x1, 2543 MLX5_TIRC_LRO_ENABLE_MASK_IPV6_LRO = 0x2, 2544 }; 2545 2546 enum { 2547 MLX5_RX_HASH_FN_NONE = 0x0, 2548 MLX5_RX_HASH_FN_INVERTED_XOR8 = 0x1, 2549 MLX5_RX_HASH_FN_TOEPLITZ = 0x2, 2550 }; 2551 2552 enum { 2553 MLX5_TIRC_SELF_LB_BLOCK_BLOCK_UNICAST_ = 0x1, 2554 MLX5_TIRC_SELF_LB_BLOCK_BLOCK_MULTICAST_ = 0x2, 2555 }; 2556 2557 struct mlx5_ifc_tirc_bits { 2558 u8 reserved_at_0[0x20]; 2559 2560 u8 disp_type[0x4]; 2561 u8 reserved_at_24[0x1c]; 2562 2563 u8 reserved_at_40[0x40]; 2564 2565 u8 reserved_at_80[0x4]; 2566 u8 lro_timeout_period_usecs[0x10]; 2567 u8 lro_enable_mask[0x4]; 2568 u8 lro_max_ip_payload_size[0x8]; 2569 2570 u8 reserved_at_a0[0x40]; 2571 2572 u8 reserved_at_e0[0x8]; 2573 u8 inline_rqn[0x18]; 2574 2575 u8 rx_hash_symmetric[0x1]; 2576 u8 reserved_at_101[0x1]; 2577 u8 tunneled_offload_en[0x1]; 2578 u8 reserved_at_103[0x5]; 2579 u8 indirect_table[0x18]; 2580 2581 u8 rx_hash_fn[0x4]; 2582 u8 reserved_at_124[0x2]; 2583 u8 self_lb_block[0x2]; 2584 u8 transport_domain[0x18]; 2585 2586 u8 rx_hash_toeplitz_key[10][0x20]; 2587 2588 struct mlx5_ifc_rx_hash_field_select_bits rx_hash_field_selector_outer; 2589 2590 struct mlx5_ifc_rx_hash_field_select_bits rx_hash_field_selector_inner; 2591 2592 u8 reserved_at_2c0[0x4c0]; 2593 }; 2594 2595 enum { 2596 MLX5_SRQC_STATE_GOOD = 0x0, 2597 MLX5_SRQC_STATE_ERROR = 0x1, 2598 }; 2599 2600 struct mlx5_ifc_srqc_bits { 2601 u8 state[0x4]; 2602 u8 log_srq_size[0x4]; 2603 u8 reserved_at_8[0x18]; 2604 2605 u8 wq_signature[0x1]; 2606 u8 cont_srq[0x1]; 2607 u8 reserved_at_22[0x1]; 2608 u8 rlky[0x1]; 2609 u8 reserved_at_24[0x1]; 2610 u8 log_rq_stride[0x3]; 2611 u8 xrcd[0x18]; 2612 2613 u8 page_offset[0x6]; 2614 u8 reserved_at_46[0x2]; 2615 u8 cqn[0x18]; 2616 2617 u8 reserved_at_60[0x20]; 2618 2619 u8 reserved_at_80[0x2]; 2620 u8 log_page_size[0x6]; 2621 u8 reserved_at_88[0x18]; 2622 2623 u8 reserved_at_a0[0x20]; 2624 2625 u8 reserved_at_c0[0x8]; 2626 u8 pd[0x18]; 2627 2628 u8 lwm[0x10]; 2629 u8 wqe_cnt[0x10]; 2630 2631 u8 reserved_at_100[0x40]; 2632 2633 u8 dbr_addr[0x40]; 2634 2635 u8 reserved_at_180[0x80]; 2636 }; 2637 2638 enum { 2639 MLX5_SQC_STATE_RST = 0x0, 2640 MLX5_SQC_STATE_RDY = 0x1, 2641 MLX5_SQC_STATE_ERR = 0x3, 2642 }; 2643 2644 struct mlx5_ifc_sqc_bits { 2645 u8 rlky[0x1]; 2646 u8 cd_master[0x1]; 2647 u8 fre[0x1]; 2648 u8 flush_in_error_en[0x1]; 2649 u8 allow_multi_pkt_send_wqe[0x1]; 2650 u8 min_wqe_inline_mode[0x3]; 2651 u8 state[0x4]; 2652 u8 reg_umr[0x1]; 2653 u8 allow_swp[0x1]; 2654 u8 hairpin[0x1]; 2655 u8 reserved_at_f[0x11]; 2656 2657 u8 reserved_at_20[0x8]; 2658 u8 user_index[0x18]; 2659 2660 u8 reserved_at_40[0x8]; 2661 u8 cqn[0x18]; 2662 2663 u8 reserved_at_60[0x8]; 2664 u8 hairpin_peer_rq[0x18]; 2665 2666 u8 reserved_at_80[0x10]; 2667 u8 hairpin_peer_vhca[0x10]; 2668 2669 u8 reserved_at_a0[0x50]; 2670 2671 u8 packet_pacing_rate_limit_index[0x10]; 2672 u8 tis_lst_sz[0x10]; 2673 u8 reserved_at_110[0x10]; 2674 2675 u8 reserved_at_120[0x40]; 2676 2677 u8 reserved_at_160[0x8]; 2678 u8 tis_num_0[0x18]; 2679 2680 struct mlx5_ifc_wq_bits wq; 2681 }; 2682 2683 enum { 2684 SCHEDULING_CONTEXT_ELEMENT_TYPE_TSAR = 0x0, 2685 SCHEDULING_CONTEXT_ELEMENT_TYPE_VPORT = 0x1, 2686 SCHEDULING_CONTEXT_ELEMENT_TYPE_VPORT_TC = 0x2, 2687 SCHEDULING_CONTEXT_ELEMENT_TYPE_PARA_VPORT_TC = 0x3, 2688 }; 2689 2690 struct mlx5_ifc_scheduling_context_bits { 2691 u8 element_type[0x8]; 2692 u8 reserved_at_8[0x18]; 2693 2694 u8 element_attributes[0x20]; 2695 2696 u8 parent_element_id[0x20]; 2697 2698 u8 reserved_at_60[0x40]; 2699 2700 u8 bw_share[0x20]; 2701 2702 u8 max_average_bw[0x20]; 2703 2704 u8 reserved_at_e0[0x120]; 2705 }; 2706 2707 struct mlx5_ifc_rqtc_bits { 2708 u8 reserved_at_0[0xa0]; 2709 2710 u8 reserved_at_a0[0x10]; 2711 u8 rqt_max_size[0x10]; 2712 2713 u8 reserved_at_c0[0x10]; 2714 u8 rqt_actual_size[0x10]; 2715 2716 u8 reserved_at_e0[0x6a0]; 2717 2718 struct mlx5_ifc_rq_num_bits rq_num[0]; 2719 }; 2720 2721 enum { 2722 MLX5_RQC_MEM_RQ_TYPE_MEMORY_RQ_INLINE = 0x0, 2723 MLX5_RQC_MEM_RQ_TYPE_MEMORY_RQ_RMP = 0x1, 2724 }; 2725 2726 enum { 2727 MLX5_RQC_STATE_RST = 0x0, 2728 MLX5_RQC_STATE_RDY = 0x1, 2729 MLX5_RQC_STATE_ERR = 0x3, 2730 }; 2731 2732 struct mlx5_ifc_rqc_bits { 2733 u8 rlky[0x1]; 2734 u8 delay_drop_en[0x1]; 2735 u8 scatter_fcs[0x1]; 2736 u8 vsd[0x1]; 2737 u8 mem_rq_type[0x4]; 2738 u8 state[0x4]; 2739 u8 reserved_at_c[0x1]; 2740 u8 flush_in_error_en[0x1]; 2741 u8 hairpin[0x1]; 2742 u8 reserved_at_f[0x11]; 2743 2744 u8 reserved_at_20[0x8]; 2745 u8 user_index[0x18]; 2746 2747 u8 reserved_at_40[0x8]; 2748 u8 cqn[0x18]; 2749 2750 u8 counter_set_id[0x8]; 2751 u8 reserved_at_68[0x18]; 2752 2753 u8 reserved_at_80[0x8]; 2754 u8 rmpn[0x18]; 2755 2756 u8 reserved_at_a0[0x8]; 2757 u8 hairpin_peer_sq[0x18]; 2758 2759 u8 reserved_at_c0[0x10]; 2760 u8 hairpin_peer_vhca[0x10]; 2761 2762 u8 reserved_at_e0[0xa0]; 2763 2764 struct mlx5_ifc_wq_bits wq; 2765 }; 2766 2767 enum { 2768 MLX5_RMPC_STATE_RDY = 0x1, 2769 MLX5_RMPC_STATE_ERR = 0x3, 2770 }; 2771 2772 struct mlx5_ifc_rmpc_bits { 2773 u8 reserved_at_0[0x8]; 2774 u8 state[0x4]; 2775 u8 reserved_at_c[0x14]; 2776 2777 u8 basic_cyclic_rcv_wqe[0x1]; 2778 u8 reserved_at_21[0x1f]; 2779 2780 u8 reserved_at_40[0x140]; 2781 2782 struct mlx5_ifc_wq_bits wq; 2783 }; 2784 2785 struct mlx5_ifc_nic_vport_context_bits { 2786 u8 reserved_at_0[0x5]; 2787 u8 min_wqe_inline_mode[0x3]; 2788 u8 reserved_at_8[0x15]; 2789 u8 disable_mc_local_lb[0x1]; 2790 u8 disable_uc_local_lb[0x1]; 2791 u8 roce_en[0x1]; 2792 2793 u8 arm_change_event[0x1]; 2794 u8 reserved_at_21[0x1a]; 2795 u8 event_on_mtu[0x1]; 2796 u8 event_on_promisc_change[0x1]; 2797 u8 event_on_vlan_change[0x1]; 2798 u8 event_on_mc_address_change[0x1]; 2799 u8 event_on_uc_address_change[0x1]; 2800 2801 u8 reserved_at_40[0xc]; 2802 2803 u8 affiliation_criteria[0x4]; 2804 u8 affiliated_vhca_id[0x10]; 2805 2806 u8 reserved_at_60[0xd0]; 2807 2808 u8 mtu[0x10]; 2809 2810 u8 system_image_guid[0x40]; 2811 u8 port_guid[0x40]; 2812 u8 node_guid[0x40]; 2813 2814 u8 reserved_at_200[0x140]; 2815 u8 qkey_violation_counter[0x10]; 2816 u8 reserved_at_350[0x430]; 2817 2818 u8 promisc_uc[0x1]; 2819 u8 promisc_mc[0x1]; 2820 u8 promisc_all[0x1]; 2821 u8 reserved_at_783[0x2]; 2822 u8 allowed_list_type[0x3]; 2823 u8 reserved_at_788[0xc]; 2824 u8 allowed_list_size[0xc]; 2825 2826 struct mlx5_ifc_mac_address_layout_bits permanent_address; 2827 2828 u8 reserved_at_7e0[0x20]; 2829 2830 u8 current_uc_mac_address[0][0x40]; 2831 }; 2832 2833 enum { 2834 MLX5_MKC_ACCESS_MODE_PA = 0x0, 2835 MLX5_MKC_ACCESS_MODE_MTT = 0x1, 2836 MLX5_MKC_ACCESS_MODE_KLMS = 0x2, 2837 MLX5_MKC_ACCESS_MODE_KSM = 0x3, 2838 MLX5_MKC_ACCESS_MODE_MEMIC = 0x5, 2839 }; 2840 2841 struct mlx5_ifc_mkc_bits { 2842 u8 reserved_at_0[0x1]; 2843 u8 free[0x1]; 2844 u8 reserved_at_2[0x1]; 2845 u8 access_mode_4_2[0x3]; 2846 u8 reserved_at_6[0x7]; 2847 u8 relaxed_ordering_write[0x1]; 2848 u8 reserved_at_e[0x1]; 2849 u8 small_fence_on_rdma_read_response[0x1]; 2850 u8 umr_en[0x1]; 2851 u8 a[0x1]; 2852 u8 rw[0x1]; 2853 u8 rr[0x1]; 2854 u8 lw[0x1]; 2855 u8 lr[0x1]; 2856 u8 access_mode_1_0[0x2]; 2857 u8 reserved_at_18[0x8]; 2858 2859 u8 qpn[0x18]; 2860 u8 mkey_7_0[0x8]; 2861 2862 u8 reserved_at_40[0x20]; 2863 2864 u8 length64[0x1]; 2865 u8 bsf_en[0x1]; 2866 u8 sync_umr[0x1]; 2867 u8 reserved_at_63[0x2]; 2868 u8 expected_sigerr_count[0x1]; 2869 u8 reserved_at_66[0x1]; 2870 u8 en_rinval[0x1]; 2871 u8 pd[0x18]; 2872 2873 u8 start_addr[0x40]; 2874 2875 u8 len[0x40]; 2876 2877 u8 bsf_octword_size[0x20]; 2878 2879 u8 reserved_at_120[0x80]; 2880 2881 u8 translations_octword_size[0x20]; 2882 2883 u8 reserved_at_1c0[0x1b]; 2884 u8 log_page_size[0x5]; 2885 2886 u8 reserved_at_1e0[0x20]; 2887 }; 2888 2889 struct mlx5_ifc_pkey_bits { 2890 u8 reserved_at_0[0x10]; 2891 u8 pkey[0x10]; 2892 }; 2893 2894 struct mlx5_ifc_array128_auto_bits { 2895 u8 array128_auto[16][0x8]; 2896 }; 2897 2898 struct mlx5_ifc_hca_vport_context_bits { 2899 u8 field_select[0x20]; 2900 2901 u8 reserved_at_20[0xe0]; 2902 2903 u8 sm_virt_aware[0x1]; 2904 u8 has_smi[0x1]; 2905 u8 has_raw[0x1]; 2906 u8 grh_required[0x1]; 2907 u8 reserved_at_104[0xc]; 2908 u8 port_physical_state[0x4]; 2909 u8 vport_state_policy[0x4]; 2910 u8 port_state[0x4]; 2911 u8 vport_state[0x4]; 2912 2913 u8 reserved_at_120[0x20]; 2914 2915 u8 system_image_guid[0x40]; 2916 2917 u8 port_guid[0x40]; 2918 2919 u8 node_guid[0x40]; 2920 2921 u8 cap_mask1[0x20]; 2922 2923 u8 cap_mask1_field_select[0x20]; 2924 2925 u8 cap_mask2[0x20]; 2926 2927 u8 cap_mask2_field_select[0x20]; 2928 2929 u8 reserved_at_280[0x80]; 2930 2931 u8 lid[0x10]; 2932 u8 reserved_at_310[0x4]; 2933 u8 init_type_reply[0x4]; 2934 u8 lmc[0x3]; 2935 u8 subnet_timeout[0x5]; 2936 2937 u8 sm_lid[0x10]; 2938 u8 sm_sl[0x4]; 2939 u8 reserved_at_334[0xc]; 2940 2941 u8 qkey_violation_counter[0x10]; 2942 u8 pkey_violation_counter[0x10]; 2943 2944 u8 reserved_at_360[0xca0]; 2945 }; 2946 2947 struct mlx5_ifc_esw_vport_context_bits { 2948 u8 reserved_at_0[0x3]; 2949 u8 vport_svlan_strip[0x1]; 2950 u8 vport_cvlan_strip[0x1]; 2951 u8 vport_svlan_insert[0x1]; 2952 u8 vport_cvlan_insert[0x2]; 2953 u8 reserved_at_8[0x18]; 2954 2955 u8 reserved_at_20[0x20]; 2956 2957 u8 svlan_cfi[0x1]; 2958 u8 svlan_pcp[0x3]; 2959 u8 svlan_id[0xc]; 2960 u8 cvlan_cfi[0x1]; 2961 u8 cvlan_pcp[0x3]; 2962 u8 cvlan_id[0xc]; 2963 2964 u8 reserved_at_60[0x7a0]; 2965 }; 2966 2967 enum { 2968 MLX5_EQC_STATUS_OK = 0x0, 2969 MLX5_EQC_STATUS_EQ_WRITE_FAILURE = 0xa, 2970 }; 2971 2972 enum { 2973 MLX5_EQC_ST_ARMED = 0x9, 2974 MLX5_EQC_ST_FIRED = 0xa, 2975 }; 2976 2977 struct mlx5_ifc_eqc_bits { 2978 u8 status[0x4]; 2979 u8 reserved_at_4[0x9]; 2980 u8 ec[0x1]; 2981 u8 oi[0x1]; 2982 u8 reserved_at_f[0x5]; 2983 u8 st[0x4]; 2984 u8 reserved_at_18[0x8]; 2985 2986 u8 reserved_at_20[0x20]; 2987 2988 u8 reserved_at_40[0x14]; 2989 u8 page_offset[0x6]; 2990 u8 reserved_at_5a[0x6]; 2991 2992 u8 reserved_at_60[0x3]; 2993 u8 log_eq_size[0x5]; 2994 u8 uar_page[0x18]; 2995 2996 u8 reserved_at_80[0x20]; 2997 2998 u8 reserved_at_a0[0x18]; 2999 u8 intr[0x8]; 3000 3001 u8 reserved_at_c0[0x3]; 3002 u8 log_page_size[0x5]; 3003 u8 reserved_at_c8[0x18]; 3004 3005 u8 reserved_at_e0[0x60]; 3006 3007 u8 reserved_at_140[0x8]; 3008 u8 consumer_counter[0x18]; 3009 3010 u8 reserved_at_160[0x8]; 3011 u8 producer_counter[0x18]; 3012 3013 u8 reserved_at_180[0x80]; 3014 }; 3015 3016 enum { 3017 MLX5_DCTC_STATE_ACTIVE = 0x0, 3018 MLX5_DCTC_STATE_DRAINING = 0x1, 3019 MLX5_DCTC_STATE_DRAINED = 0x2, 3020 }; 3021 3022 enum { 3023 MLX5_DCTC_CS_RES_DISABLE = 0x0, 3024 MLX5_DCTC_CS_RES_NA = 0x1, 3025 MLX5_DCTC_CS_RES_UP_TO_64B = 0x2, 3026 }; 3027 3028 enum { 3029 MLX5_DCTC_MTU_256_BYTES = 0x1, 3030 MLX5_DCTC_MTU_512_BYTES = 0x2, 3031 MLX5_DCTC_MTU_1K_BYTES = 0x3, 3032 MLX5_DCTC_MTU_2K_BYTES = 0x4, 3033 MLX5_DCTC_MTU_4K_BYTES = 0x5, 3034 }; 3035 3036 struct mlx5_ifc_dctc_bits { 3037 u8 reserved_at_0[0x4]; 3038 u8 state[0x4]; 3039 u8 reserved_at_8[0x18]; 3040 3041 u8 reserved_at_20[0x8]; 3042 u8 user_index[0x18]; 3043 3044 u8 reserved_at_40[0x8]; 3045 u8 cqn[0x18]; 3046 3047 u8 counter_set_id[0x8]; 3048 u8 atomic_mode[0x4]; 3049 u8 rre[0x1]; 3050 u8 rwe[0x1]; 3051 u8 rae[0x1]; 3052 u8 atomic_like_write_en[0x1]; 3053 u8 latency_sensitive[0x1]; 3054 u8 rlky[0x1]; 3055 u8 free_ar[0x1]; 3056 u8 reserved_at_73[0xd]; 3057 3058 u8 reserved_at_80[0x8]; 3059 u8 cs_res[0x8]; 3060 u8 reserved_at_90[0x3]; 3061 u8 min_rnr_nak[0x5]; 3062 u8 reserved_at_98[0x8]; 3063 3064 u8 reserved_at_a0[0x8]; 3065 u8 srqn_xrqn[0x18]; 3066 3067 u8 reserved_at_c0[0x8]; 3068 u8 pd[0x18]; 3069 3070 u8 tclass[0x8]; 3071 u8 reserved_at_e8[0x4]; 3072 u8 flow_label[0x14]; 3073 3074 u8 dc_access_key[0x40]; 3075 3076 u8 reserved_at_140[0x5]; 3077 u8 mtu[0x3]; 3078 u8 port[0x8]; 3079 u8 pkey_index[0x10]; 3080 3081 u8 reserved_at_160[0x8]; 3082 u8 my_addr_index[0x8]; 3083 u8 reserved_at_170[0x8]; 3084 u8 hop_limit[0x8]; 3085 3086 u8 dc_access_key_violation_count[0x20]; 3087 3088 u8 reserved_at_1a0[0x14]; 3089 u8 dei_cfi[0x1]; 3090 u8 eth_prio[0x3]; 3091 u8 ecn[0x2]; 3092 u8 dscp[0x6]; 3093 3094 u8 reserved_at_1c0[0x40]; 3095 }; 3096 3097 enum { 3098 MLX5_CQC_STATUS_OK = 0x0, 3099 MLX5_CQC_STATUS_CQ_OVERFLOW = 0x9, 3100 MLX5_CQC_STATUS_CQ_WRITE_FAIL = 0xa, 3101 }; 3102 3103 enum { 3104 MLX5_CQC_CQE_SZ_64_BYTES = 0x0, 3105 MLX5_CQC_CQE_SZ_128_BYTES = 0x1, 3106 }; 3107 3108 enum { 3109 MLX5_CQC_ST_SOLICITED_NOTIFICATION_REQUEST_ARMED = 0x6, 3110 MLX5_CQC_ST_NOTIFICATION_REQUEST_ARMED = 0x9, 3111 MLX5_CQC_ST_FIRED = 0xa, 3112 }; 3113 3114 enum { 3115 MLX5_CQ_PERIOD_MODE_START_FROM_EQE = 0x0, 3116 MLX5_CQ_PERIOD_MODE_START_FROM_CQE = 0x1, 3117 MLX5_CQ_PERIOD_NUM_MODES 3118 }; 3119 3120 struct mlx5_ifc_cqc_bits { 3121 u8 status[0x4]; 3122 u8 reserved_at_4[0x4]; 3123 u8 cqe_sz[0x3]; 3124 u8 cc[0x1]; 3125 u8 reserved_at_c[0x1]; 3126 u8 scqe_break_moderation_en[0x1]; 3127 u8 oi[0x1]; 3128 u8 cq_period_mode[0x2]; 3129 u8 cqe_comp_en[0x1]; 3130 u8 mini_cqe_res_format[0x2]; 3131 u8 st[0x4]; 3132 u8 reserved_at_18[0x8]; 3133 3134 u8 reserved_at_20[0x20]; 3135 3136 u8 reserved_at_40[0x14]; 3137 u8 page_offset[0x6]; 3138 u8 reserved_at_5a[0x6]; 3139 3140 u8 reserved_at_60[0x3]; 3141 u8 log_cq_size[0x5]; 3142 u8 uar_page[0x18]; 3143 3144 u8 reserved_at_80[0x4]; 3145 u8 cq_period[0xc]; 3146 u8 cq_max_count[0x10]; 3147 3148 u8 reserved_at_a0[0x18]; 3149 u8 c_eqn[0x8]; 3150 3151 u8 reserved_at_c0[0x3]; 3152 u8 log_page_size[0x5]; 3153 u8 reserved_at_c8[0x18]; 3154 3155 u8 reserved_at_e0[0x20]; 3156 3157 u8 reserved_at_100[0x8]; 3158 u8 last_notified_index[0x18]; 3159 3160 u8 reserved_at_120[0x8]; 3161 u8 last_solicit_index[0x18]; 3162 3163 u8 reserved_at_140[0x8]; 3164 u8 consumer_counter[0x18]; 3165 3166 u8 reserved_at_160[0x8]; 3167 u8 producer_counter[0x18]; 3168 3169 u8 reserved_at_180[0x40]; 3170 3171 u8 dbr_addr[0x40]; 3172 }; 3173 3174 union mlx5_ifc_cong_control_roce_ecn_auto_bits { 3175 struct mlx5_ifc_cong_control_802_1qau_rp_bits cong_control_802_1qau_rp; 3176 struct mlx5_ifc_cong_control_r_roce_ecn_rp_bits cong_control_r_roce_ecn_rp; 3177 struct mlx5_ifc_cong_control_r_roce_ecn_np_bits cong_control_r_roce_ecn_np; 3178 u8 reserved_at_0[0x800]; 3179 }; 3180 3181 struct mlx5_ifc_query_adapter_param_block_bits { 3182 u8 reserved_at_0[0xc0]; 3183 3184 u8 reserved_at_c0[0x8]; 3185 u8 ieee_vendor_id[0x18]; 3186 3187 u8 reserved_at_e0[0x10]; 3188 u8 vsd_vendor_id[0x10]; 3189 3190 u8 vsd[208][0x8]; 3191 3192 u8 vsd_contd_psid[16][0x8]; 3193 }; 3194 3195 enum { 3196 MLX5_XRQC_STATE_GOOD = 0x0, 3197 MLX5_XRQC_STATE_ERROR = 0x1, 3198 }; 3199 3200 enum { 3201 MLX5_XRQC_TOPOLOGY_NO_SPECIAL_TOPOLOGY = 0x0, 3202 MLX5_XRQC_TOPOLOGY_TAG_MATCHING = 0x1, 3203 }; 3204 3205 enum { 3206 MLX5_XRQC_OFFLOAD_RNDV = 0x1, 3207 }; 3208 3209 struct mlx5_ifc_tag_matching_topology_context_bits { 3210 u8 log_matching_list_sz[0x4]; 3211 u8 reserved_at_4[0xc]; 3212 u8 append_next_index[0x10]; 3213 3214 u8 sw_phase_cnt[0x10]; 3215 u8 hw_phase_cnt[0x10]; 3216 3217 u8 reserved_at_40[0x40]; 3218 }; 3219 3220 struct mlx5_ifc_xrqc_bits { 3221 u8 state[0x4]; 3222 u8 rlkey[0x1]; 3223 u8 reserved_at_5[0xf]; 3224 u8 topology[0x4]; 3225 u8 reserved_at_18[0x4]; 3226 u8 offload[0x4]; 3227 3228 u8 reserved_at_20[0x8]; 3229 u8 user_index[0x18]; 3230 3231 u8 reserved_at_40[0x8]; 3232 u8 cqn[0x18]; 3233 3234 u8 reserved_at_60[0xa0]; 3235 3236 struct mlx5_ifc_tag_matching_topology_context_bits tag_matching_topology_context; 3237 3238 u8 reserved_at_180[0x280]; 3239 3240 struct mlx5_ifc_wq_bits wq; 3241 }; 3242 3243 union mlx5_ifc_modify_field_select_resize_field_select_auto_bits { 3244 struct mlx5_ifc_modify_field_select_bits modify_field_select; 3245 struct mlx5_ifc_resize_field_select_bits resize_field_select; 3246 u8 reserved_at_0[0x20]; 3247 }; 3248 3249 union mlx5_ifc_field_select_802_1_r_roce_auto_bits { 3250 struct mlx5_ifc_field_select_802_1qau_rp_bits field_select_802_1qau_rp; 3251 struct mlx5_ifc_field_select_r_roce_rp_bits field_select_r_roce_rp; 3252 struct mlx5_ifc_field_select_r_roce_np_bits field_select_r_roce_np; 3253 u8 reserved_at_0[0x20]; 3254 }; 3255 3256 union mlx5_ifc_eth_cntrs_grp_data_layout_auto_bits { 3257 struct mlx5_ifc_eth_802_3_cntrs_grp_data_layout_bits eth_802_3_cntrs_grp_data_layout; 3258 struct mlx5_ifc_eth_2863_cntrs_grp_data_layout_bits eth_2863_cntrs_grp_data_layout; 3259 struct mlx5_ifc_eth_2819_cntrs_grp_data_layout_bits eth_2819_cntrs_grp_data_layout; 3260 struct mlx5_ifc_eth_3635_cntrs_grp_data_layout_bits eth_3635_cntrs_grp_data_layout; 3261 struct mlx5_ifc_eth_extended_cntrs_grp_data_layout_bits eth_extended_cntrs_grp_data_layout; 3262 struct mlx5_ifc_eth_per_prio_grp_data_layout_bits eth_per_prio_grp_data_layout; 3263 struct mlx5_ifc_eth_per_traffic_grp_data_layout_bits eth_per_traffic_grp_data_layout; 3264 struct mlx5_ifc_ib_port_cntrs_grp_data_layout_bits ib_port_cntrs_grp_data_layout; 3265 struct mlx5_ifc_phys_layer_cntrs_bits phys_layer_cntrs; 3266 struct mlx5_ifc_phys_layer_statistical_cntrs_bits phys_layer_statistical_cntrs; 3267 u8 reserved_at_0[0x7c0]; 3268 }; 3269 3270 union mlx5_ifc_pcie_cntrs_grp_data_layout_auto_bits { 3271 struct mlx5_ifc_pcie_perf_cntrs_grp_data_layout_bits pcie_perf_cntrs_grp_data_layout; 3272 u8 reserved_at_0[0x7c0]; 3273 }; 3274 3275 union mlx5_ifc_event_auto_bits { 3276 struct mlx5_ifc_comp_event_bits comp_event; 3277 struct mlx5_ifc_dct_events_bits dct_events; 3278 struct mlx5_ifc_qp_events_bits qp_events; 3279 struct mlx5_ifc_wqe_associated_page_fault_event_bits wqe_associated_page_fault_event; 3280 struct mlx5_ifc_rdma_page_fault_event_bits rdma_page_fault_event; 3281 struct mlx5_ifc_cq_error_bits cq_error; 3282 struct mlx5_ifc_dropped_packet_logged_bits dropped_packet_logged; 3283 struct mlx5_ifc_port_state_change_event_bits port_state_change_event; 3284 struct mlx5_ifc_gpio_event_bits gpio_event; 3285 struct mlx5_ifc_db_bf_congestion_event_bits db_bf_congestion_event; 3286 struct mlx5_ifc_stall_vl_event_bits stall_vl_event; 3287 struct mlx5_ifc_cmd_inter_comp_event_bits cmd_inter_comp_event; 3288 u8 reserved_at_0[0xe0]; 3289 }; 3290 3291 struct mlx5_ifc_health_buffer_bits { 3292 u8 reserved_at_0[0x100]; 3293 3294 u8 assert_existptr[0x20]; 3295 3296 u8 assert_callra[0x20]; 3297 3298 u8 reserved_at_140[0x40]; 3299 3300 u8 fw_version[0x20]; 3301 3302 u8 hw_id[0x20]; 3303 3304 u8 reserved_at_1c0[0x20]; 3305 3306 u8 irisc_index[0x8]; 3307 u8 synd[0x8]; 3308 u8 ext_synd[0x10]; 3309 }; 3310 3311 struct mlx5_ifc_register_loopback_control_bits { 3312 u8 no_lb[0x1]; 3313 u8 reserved_at_1[0x7]; 3314 u8 port[0x8]; 3315 u8 reserved_at_10[0x10]; 3316 3317 u8 reserved_at_20[0x60]; 3318 }; 3319 3320 struct mlx5_ifc_vport_tc_element_bits { 3321 u8 traffic_class[0x4]; 3322 u8 reserved_at_4[0xc]; 3323 u8 vport_number[0x10]; 3324 }; 3325 3326 struct mlx5_ifc_vport_element_bits { 3327 u8 reserved_at_0[0x10]; 3328 u8 vport_number[0x10]; 3329 }; 3330 3331 enum { 3332 TSAR_ELEMENT_TSAR_TYPE_DWRR = 0x0, 3333 TSAR_ELEMENT_TSAR_TYPE_ROUND_ROBIN = 0x1, 3334 TSAR_ELEMENT_TSAR_TYPE_ETS = 0x2, 3335 }; 3336 3337 struct mlx5_ifc_tsar_element_bits { 3338 u8 reserved_at_0[0x8]; 3339 u8 tsar_type[0x8]; 3340 u8 reserved_at_10[0x10]; 3341 }; 3342 3343 enum { 3344 MLX5_TEARDOWN_HCA_OUT_FORCE_STATE_SUCCESS = 0x0, 3345 MLX5_TEARDOWN_HCA_OUT_FORCE_STATE_FAIL = 0x1, 3346 }; 3347 3348 struct mlx5_ifc_teardown_hca_out_bits { 3349 u8 status[0x8]; 3350 u8 reserved_at_8[0x18]; 3351 3352 u8 syndrome[0x20]; 3353 3354 u8 reserved_at_40[0x3f]; 3355 3356 u8 state[0x1]; 3357 }; 3358 3359 enum { 3360 MLX5_TEARDOWN_HCA_IN_PROFILE_GRACEFUL_CLOSE = 0x0, 3361 MLX5_TEARDOWN_HCA_IN_PROFILE_FORCE_CLOSE = 0x1, 3362 MLX5_TEARDOWN_HCA_IN_PROFILE_PREPARE_FAST_TEARDOWN = 0x2, 3363 }; 3364 3365 struct mlx5_ifc_teardown_hca_in_bits { 3366 u8 opcode[0x10]; 3367 u8 reserved_at_10[0x10]; 3368 3369 u8 reserved_at_20[0x10]; 3370 u8 op_mod[0x10]; 3371 3372 u8 reserved_at_40[0x10]; 3373 u8 profile[0x10]; 3374 3375 u8 reserved_at_60[0x20]; 3376 }; 3377 3378 struct mlx5_ifc_sqerr2rts_qp_out_bits { 3379 u8 status[0x8]; 3380 u8 reserved_at_8[0x18]; 3381 3382 u8 syndrome[0x20]; 3383 3384 u8 reserved_at_40[0x40]; 3385 }; 3386 3387 struct mlx5_ifc_sqerr2rts_qp_in_bits { 3388 u8 opcode[0x10]; 3389 u8 reserved_at_10[0x10]; 3390 3391 u8 reserved_at_20[0x10]; 3392 u8 op_mod[0x10]; 3393 3394 u8 reserved_at_40[0x8]; 3395 u8 qpn[0x18]; 3396 3397 u8 reserved_at_60[0x20]; 3398 3399 u8 opt_param_mask[0x20]; 3400 3401 u8 reserved_at_a0[0x20]; 3402 3403 struct mlx5_ifc_qpc_bits qpc; 3404 3405 u8 reserved_at_800[0x80]; 3406 }; 3407 3408 struct mlx5_ifc_sqd2rts_qp_out_bits { 3409 u8 status[0x8]; 3410 u8 reserved_at_8[0x18]; 3411 3412 u8 syndrome[0x20]; 3413 3414 u8 reserved_at_40[0x40]; 3415 }; 3416 3417 struct mlx5_ifc_sqd2rts_qp_in_bits { 3418 u8 opcode[0x10]; 3419 u8 reserved_at_10[0x10]; 3420 3421 u8 reserved_at_20[0x10]; 3422 u8 op_mod[0x10]; 3423 3424 u8 reserved_at_40[0x8]; 3425 u8 qpn[0x18]; 3426 3427 u8 reserved_at_60[0x20]; 3428 3429 u8 opt_param_mask[0x20]; 3430 3431 u8 reserved_at_a0[0x20]; 3432 3433 struct mlx5_ifc_qpc_bits qpc; 3434 3435 u8 reserved_at_800[0x80]; 3436 }; 3437 3438 struct mlx5_ifc_set_roce_address_out_bits { 3439 u8 status[0x8]; 3440 u8 reserved_at_8[0x18]; 3441 3442 u8 syndrome[0x20]; 3443 3444 u8 reserved_at_40[0x40]; 3445 }; 3446 3447 struct mlx5_ifc_set_roce_address_in_bits { 3448 u8 opcode[0x10]; 3449 u8 reserved_at_10[0x10]; 3450 3451 u8 reserved_at_20[0x10]; 3452 u8 op_mod[0x10]; 3453 3454 u8 roce_address_index[0x10]; 3455 u8 reserved_at_50[0xc]; 3456 u8 vhca_port_num[0x4]; 3457 3458 u8 reserved_at_60[0x20]; 3459 3460 struct mlx5_ifc_roce_addr_layout_bits roce_address; 3461 }; 3462 3463 struct mlx5_ifc_set_mad_demux_out_bits { 3464 u8 status[0x8]; 3465 u8 reserved_at_8[0x18]; 3466 3467 u8 syndrome[0x20]; 3468 3469 u8 reserved_at_40[0x40]; 3470 }; 3471 3472 enum { 3473 MLX5_SET_MAD_DEMUX_IN_DEMUX_MODE_PASS_ALL = 0x0, 3474 MLX5_SET_MAD_DEMUX_IN_DEMUX_MODE_SELECTIVE = 0x2, 3475 }; 3476 3477 struct mlx5_ifc_set_mad_demux_in_bits { 3478 u8 opcode[0x10]; 3479 u8 reserved_at_10[0x10]; 3480 3481 u8 reserved_at_20[0x10]; 3482 u8 op_mod[0x10]; 3483 3484 u8 reserved_at_40[0x20]; 3485 3486 u8 reserved_at_60[0x6]; 3487 u8 demux_mode[0x2]; 3488 u8 reserved_at_68[0x18]; 3489 }; 3490 3491 struct mlx5_ifc_set_l2_table_entry_out_bits { 3492 u8 status[0x8]; 3493 u8 reserved_at_8[0x18]; 3494 3495 u8 syndrome[0x20]; 3496 3497 u8 reserved_at_40[0x40]; 3498 }; 3499 3500 struct mlx5_ifc_set_l2_table_entry_in_bits { 3501 u8 opcode[0x10]; 3502 u8 reserved_at_10[0x10]; 3503 3504 u8 reserved_at_20[0x10]; 3505 u8 op_mod[0x10]; 3506 3507 u8 reserved_at_40[0x60]; 3508 3509 u8 reserved_at_a0[0x8]; 3510 u8 table_index[0x18]; 3511 3512 u8 reserved_at_c0[0x20]; 3513 3514 u8 reserved_at_e0[0x13]; 3515 u8 vlan_valid[0x1]; 3516 u8 vlan[0xc]; 3517 3518 struct mlx5_ifc_mac_address_layout_bits mac_address; 3519 3520 u8 reserved_at_140[0xc0]; 3521 }; 3522 3523 struct mlx5_ifc_set_issi_out_bits { 3524 u8 status[0x8]; 3525 u8 reserved_at_8[0x18]; 3526 3527 u8 syndrome[0x20]; 3528 3529 u8 reserved_at_40[0x40]; 3530 }; 3531 3532 struct mlx5_ifc_set_issi_in_bits { 3533 u8 opcode[0x10]; 3534 u8 reserved_at_10[0x10]; 3535 3536 u8 reserved_at_20[0x10]; 3537 u8 op_mod[0x10]; 3538 3539 u8 reserved_at_40[0x10]; 3540 u8 current_issi[0x10]; 3541 3542 u8 reserved_at_60[0x20]; 3543 }; 3544 3545 struct mlx5_ifc_set_hca_cap_out_bits { 3546 u8 status[0x8]; 3547 u8 reserved_at_8[0x18]; 3548 3549 u8 syndrome[0x20]; 3550 3551 u8 reserved_at_40[0x40]; 3552 }; 3553 3554 struct mlx5_ifc_set_hca_cap_in_bits { 3555 u8 opcode[0x10]; 3556 u8 reserved_at_10[0x10]; 3557 3558 u8 reserved_at_20[0x10]; 3559 u8 op_mod[0x10]; 3560 3561 u8 reserved_at_40[0x40]; 3562 3563 union mlx5_ifc_hca_cap_union_bits capability; 3564 }; 3565 3566 enum { 3567 MLX5_SET_FTE_MODIFY_ENABLE_MASK_ACTION = 0x0, 3568 MLX5_SET_FTE_MODIFY_ENABLE_MASK_FLOW_TAG = 0x1, 3569 MLX5_SET_FTE_MODIFY_ENABLE_MASK_DESTINATION_LIST = 0x2, 3570 MLX5_SET_FTE_MODIFY_ENABLE_MASK_FLOW_COUNTERS = 0x3 3571 }; 3572 3573 struct mlx5_ifc_set_fte_out_bits { 3574 u8 status[0x8]; 3575 u8 reserved_at_8[0x18]; 3576 3577 u8 syndrome[0x20]; 3578 3579 u8 reserved_at_40[0x40]; 3580 }; 3581 3582 struct mlx5_ifc_set_fte_in_bits { 3583 u8 opcode[0x10]; 3584 u8 reserved_at_10[0x10]; 3585 3586 u8 reserved_at_20[0x10]; 3587 u8 op_mod[0x10]; 3588 3589 u8 other_vport[0x1]; 3590 u8 reserved_at_41[0xf]; 3591 u8 vport_number[0x10]; 3592 3593 u8 reserved_at_60[0x20]; 3594 3595 u8 table_type[0x8]; 3596 u8 reserved_at_88[0x18]; 3597 3598 u8 reserved_at_a0[0x8]; 3599 u8 table_id[0x18]; 3600 3601 u8 reserved_at_c0[0x18]; 3602 u8 modify_enable_mask[0x8]; 3603 3604 u8 reserved_at_e0[0x20]; 3605 3606 u8 flow_index[0x20]; 3607 3608 u8 reserved_at_120[0xe0]; 3609 3610 struct mlx5_ifc_flow_context_bits flow_context; 3611 }; 3612 3613 struct mlx5_ifc_rts2rts_qp_out_bits { 3614 u8 status[0x8]; 3615 u8 reserved_at_8[0x18]; 3616 3617 u8 syndrome[0x20]; 3618 3619 u8 reserved_at_40[0x40]; 3620 }; 3621 3622 struct mlx5_ifc_rts2rts_qp_in_bits { 3623 u8 opcode[0x10]; 3624 u8 reserved_at_10[0x10]; 3625 3626 u8 reserved_at_20[0x10]; 3627 u8 op_mod[0x10]; 3628 3629 u8 reserved_at_40[0x8]; 3630 u8 qpn[0x18]; 3631 3632 u8 reserved_at_60[0x20]; 3633 3634 u8 opt_param_mask[0x20]; 3635 3636 u8 reserved_at_a0[0x20]; 3637 3638 struct mlx5_ifc_qpc_bits qpc; 3639 3640 u8 reserved_at_800[0x80]; 3641 }; 3642 3643 struct mlx5_ifc_rtr2rts_qp_out_bits { 3644 u8 status[0x8]; 3645 u8 reserved_at_8[0x18]; 3646 3647 u8 syndrome[0x20]; 3648 3649 u8 reserved_at_40[0x40]; 3650 }; 3651 3652 struct mlx5_ifc_rtr2rts_qp_in_bits { 3653 u8 opcode[0x10]; 3654 u8 reserved_at_10[0x10]; 3655 3656 u8 reserved_at_20[0x10]; 3657 u8 op_mod[0x10]; 3658 3659 u8 reserved_at_40[0x8]; 3660 u8 qpn[0x18]; 3661 3662 u8 reserved_at_60[0x20]; 3663 3664 u8 opt_param_mask[0x20]; 3665 3666 u8 reserved_at_a0[0x20]; 3667 3668 struct mlx5_ifc_qpc_bits qpc; 3669 3670 u8 reserved_at_800[0x80]; 3671 }; 3672 3673 struct mlx5_ifc_rst2init_qp_out_bits { 3674 u8 status[0x8]; 3675 u8 reserved_at_8[0x18]; 3676 3677 u8 syndrome[0x20]; 3678 3679 u8 reserved_at_40[0x40]; 3680 }; 3681 3682 struct mlx5_ifc_rst2init_qp_in_bits { 3683 u8 opcode[0x10]; 3684 u8 reserved_at_10[0x10]; 3685 3686 u8 reserved_at_20[0x10]; 3687 u8 op_mod[0x10]; 3688 3689 u8 reserved_at_40[0x8]; 3690 u8 qpn[0x18]; 3691 3692 u8 reserved_at_60[0x20]; 3693 3694 u8 opt_param_mask[0x20]; 3695 3696 u8 reserved_at_a0[0x20]; 3697 3698 struct mlx5_ifc_qpc_bits qpc; 3699 3700 u8 reserved_at_800[0x80]; 3701 }; 3702 3703 struct mlx5_ifc_query_xrq_out_bits { 3704 u8 status[0x8]; 3705 u8 reserved_at_8[0x18]; 3706 3707 u8 syndrome[0x20]; 3708 3709 u8 reserved_at_40[0x40]; 3710 3711 struct mlx5_ifc_xrqc_bits xrq_context; 3712 }; 3713 3714 struct mlx5_ifc_query_xrq_in_bits { 3715 u8 opcode[0x10]; 3716 u8 reserved_at_10[0x10]; 3717 3718 u8 reserved_at_20[0x10]; 3719 u8 op_mod[0x10]; 3720 3721 u8 reserved_at_40[0x8]; 3722 u8 xrqn[0x18]; 3723 3724 u8 reserved_at_60[0x20]; 3725 }; 3726 3727 struct mlx5_ifc_query_xrc_srq_out_bits { 3728 u8 status[0x8]; 3729 u8 reserved_at_8[0x18]; 3730 3731 u8 syndrome[0x20]; 3732 3733 u8 reserved_at_40[0x40]; 3734 3735 struct mlx5_ifc_xrc_srqc_bits xrc_srq_context_entry; 3736 3737 u8 reserved_at_280[0x600]; 3738 3739 u8 pas[0][0x40]; 3740 }; 3741 3742 struct mlx5_ifc_query_xrc_srq_in_bits { 3743 u8 opcode[0x10]; 3744 u8 reserved_at_10[0x10]; 3745 3746 u8 reserved_at_20[0x10]; 3747 u8 op_mod[0x10]; 3748 3749 u8 reserved_at_40[0x8]; 3750 u8 xrc_srqn[0x18]; 3751 3752 u8 reserved_at_60[0x20]; 3753 }; 3754 3755 enum { 3756 MLX5_QUERY_VPORT_STATE_OUT_STATE_DOWN = 0x0, 3757 MLX5_QUERY_VPORT_STATE_OUT_STATE_UP = 0x1, 3758 }; 3759 3760 struct mlx5_ifc_query_vport_state_out_bits { 3761 u8 status[0x8]; 3762 u8 reserved_at_8[0x18]; 3763 3764 u8 syndrome[0x20]; 3765 3766 u8 reserved_at_40[0x20]; 3767 3768 u8 reserved_at_60[0x18]; 3769 u8 admin_state[0x4]; 3770 u8 state[0x4]; 3771 }; 3772 3773 enum { 3774 MLX5_VPORT_STATE_OP_MOD_VNIC_VPORT = 0x0, 3775 MLX5_VPORT_STATE_OP_MOD_ESW_VPORT = 0x1, 3776 }; 3777 3778 struct mlx5_ifc_query_vport_state_in_bits { 3779 u8 opcode[0x10]; 3780 u8 reserved_at_10[0x10]; 3781 3782 u8 reserved_at_20[0x10]; 3783 u8 op_mod[0x10]; 3784 3785 u8 other_vport[0x1]; 3786 u8 reserved_at_41[0xf]; 3787 u8 vport_number[0x10]; 3788 3789 u8 reserved_at_60[0x20]; 3790 }; 3791 3792 struct mlx5_ifc_query_vnic_env_out_bits { 3793 u8 status[0x8]; 3794 u8 reserved_at_8[0x18]; 3795 3796 u8 syndrome[0x20]; 3797 3798 u8 reserved_at_40[0x40]; 3799 3800 struct mlx5_ifc_vnic_diagnostic_statistics_bits vport_env; 3801 }; 3802 3803 enum { 3804 MLX5_QUERY_VNIC_ENV_IN_OP_MOD_VPORT_DIAG_STATISTICS = 0x0, 3805 }; 3806 3807 struct mlx5_ifc_query_vnic_env_in_bits { 3808 u8 opcode[0x10]; 3809 u8 reserved_at_10[0x10]; 3810 3811 u8 reserved_at_20[0x10]; 3812 u8 op_mod[0x10]; 3813 3814 u8 other_vport[0x1]; 3815 u8 reserved_at_41[0xf]; 3816 u8 vport_number[0x10]; 3817 3818 u8 reserved_at_60[0x20]; 3819 }; 3820 3821 struct mlx5_ifc_query_vport_counter_out_bits { 3822 u8 status[0x8]; 3823 u8 reserved_at_8[0x18]; 3824 3825 u8 syndrome[0x20]; 3826 3827 u8 reserved_at_40[0x40]; 3828 3829 struct mlx5_ifc_traffic_counter_bits received_errors; 3830 3831 struct mlx5_ifc_traffic_counter_bits transmit_errors; 3832 3833 struct mlx5_ifc_traffic_counter_bits received_ib_unicast; 3834 3835 struct mlx5_ifc_traffic_counter_bits transmitted_ib_unicast; 3836 3837 struct mlx5_ifc_traffic_counter_bits received_ib_multicast; 3838 3839 struct mlx5_ifc_traffic_counter_bits transmitted_ib_multicast; 3840 3841 struct mlx5_ifc_traffic_counter_bits received_eth_broadcast; 3842 3843 struct mlx5_ifc_traffic_counter_bits transmitted_eth_broadcast; 3844 3845 struct mlx5_ifc_traffic_counter_bits received_eth_unicast; 3846 3847 struct mlx5_ifc_traffic_counter_bits transmitted_eth_unicast; 3848 3849 struct mlx5_ifc_traffic_counter_bits received_eth_multicast; 3850 3851 struct mlx5_ifc_traffic_counter_bits transmitted_eth_multicast; 3852 3853 u8 reserved_at_680[0xa00]; 3854 }; 3855 3856 enum { 3857 MLX5_QUERY_VPORT_COUNTER_IN_OP_MOD_VPORT_COUNTERS = 0x0, 3858 }; 3859 3860 struct mlx5_ifc_query_vport_counter_in_bits { 3861 u8 opcode[0x10]; 3862 u8 reserved_at_10[0x10]; 3863 3864 u8 reserved_at_20[0x10]; 3865 u8 op_mod[0x10]; 3866 3867 u8 other_vport[0x1]; 3868 u8 reserved_at_41[0xb]; 3869 u8 port_num[0x4]; 3870 u8 vport_number[0x10]; 3871 3872 u8 reserved_at_60[0x60]; 3873 3874 u8 clear[0x1]; 3875 u8 reserved_at_c1[0x1f]; 3876 3877 u8 reserved_at_e0[0x20]; 3878 }; 3879 3880 struct mlx5_ifc_query_tis_out_bits { 3881 u8 status[0x8]; 3882 u8 reserved_at_8[0x18]; 3883 3884 u8 syndrome[0x20]; 3885 3886 u8 reserved_at_40[0x40]; 3887 3888 struct mlx5_ifc_tisc_bits tis_context; 3889 }; 3890 3891 struct mlx5_ifc_query_tis_in_bits { 3892 u8 opcode[0x10]; 3893 u8 reserved_at_10[0x10]; 3894 3895 u8 reserved_at_20[0x10]; 3896 u8 op_mod[0x10]; 3897 3898 u8 reserved_at_40[0x8]; 3899 u8 tisn[0x18]; 3900 3901 u8 reserved_at_60[0x20]; 3902 }; 3903 3904 struct mlx5_ifc_query_tir_out_bits { 3905 u8 status[0x8]; 3906 u8 reserved_at_8[0x18]; 3907 3908 u8 syndrome[0x20]; 3909 3910 u8 reserved_at_40[0xc0]; 3911 3912 struct mlx5_ifc_tirc_bits tir_context; 3913 }; 3914 3915 struct mlx5_ifc_query_tir_in_bits { 3916 u8 opcode[0x10]; 3917 u8 reserved_at_10[0x10]; 3918 3919 u8 reserved_at_20[0x10]; 3920 u8 op_mod[0x10]; 3921 3922 u8 reserved_at_40[0x8]; 3923 u8 tirn[0x18]; 3924 3925 u8 reserved_at_60[0x20]; 3926 }; 3927 3928 struct mlx5_ifc_query_srq_out_bits { 3929 u8 status[0x8]; 3930 u8 reserved_at_8[0x18]; 3931 3932 u8 syndrome[0x20]; 3933 3934 u8 reserved_at_40[0x40]; 3935 3936 struct mlx5_ifc_srqc_bits srq_context_entry; 3937 3938 u8 reserved_at_280[0x600]; 3939 3940 u8 pas[0][0x40]; 3941 }; 3942 3943 struct mlx5_ifc_query_srq_in_bits { 3944 u8 opcode[0x10]; 3945 u8 reserved_at_10[0x10]; 3946 3947 u8 reserved_at_20[0x10]; 3948 u8 op_mod[0x10]; 3949 3950 u8 reserved_at_40[0x8]; 3951 u8 srqn[0x18]; 3952 3953 u8 reserved_at_60[0x20]; 3954 }; 3955 3956 struct mlx5_ifc_query_sq_out_bits { 3957 u8 status[0x8]; 3958 u8 reserved_at_8[0x18]; 3959 3960 u8 syndrome[0x20]; 3961 3962 u8 reserved_at_40[0xc0]; 3963 3964 struct mlx5_ifc_sqc_bits sq_context; 3965 }; 3966 3967 struct mlx5_ifc_query_sq_in_bits { 3968 u8 opcode[0x10]; 3969 u8 reserved_at_10[0x10]; 3970 3971 u8 reserved_at_20[0x10]; 3972 u8 op_mod[0x10]; 3973 3974 u8 reserved_at_40[0x8]; 3975 u8 sqn[0x18]; 3976 3977 u8 reserved_at_60[0x20]; 3978 }; 3979 3980 struct mlx5_ifc_query_special_contexts_out_bits { 3981 u8 status[0x8]; 3982 u8 reserved_at_8[0x18]; 3983 3984 u8 syndrome[0x20]; 3985 3986 u8 dump_fill_mkey[0x20]; 3987 3988 u8 resd_lkey[0x20]; 3989 3990 u8 null_mkey[0x20]; 3991 3992 u8 reserved_at_a0[0x60]; 3993 }; 3994 3995 struct mlx5_ifc_query_special_contexts_in_bits { 3996 u8 opcode[0x10]; 3997 u8 reserved_at_10[0x10]; 3998 3999 u8 reserved_at_20[0x10]; 4000 u8 op_mod[0x10]; 4001 4002 u8 reserved_at_40[0x40]; 4003 }; 4004 4005 struct mlx5_ifc_query_scheduling_element_out_bits { 4006 u8 opcode[0x10]; 4007 u8 reserved_at_10[0x10]; 4008 4009 u8 reserved_at_20[0x10]; 4010 u8 op_mod[0x10]; 4011 4012 u8 reserved_at_40[0xc0]; 4013 4014 struct mlx5_ifc_scheduling_context_bits scheduling_context; 4015 4016 u8 reserved_at_300[0x100]; 4017 }; 4018 4019 enum { 4020 SCHEDULING_HIERARCHY_E_SWITCH = 0x2, 4021 }; 4022 4023 struct mlx5_ifc_query_scheduling_element_in_bits { 4024 u8 opcode[0x10]; 4025 u8 reserved_at_10[0x10]; 4026 4027 u8 reserved_at_20[0x10]; 4028 u8 op_mod[0x10]; 4029 4030 u8 scheduling_hierarchy[0x8]; 4031 u8 reserved_at_48[0x18]; 4032 4033 u8 scheduling_element_id[0x20]; 4034 4035 u8 reserved_at_80[0x180]; 4036 }; 4037 4038 struct mlx5_ifc_query_rqt_out_bits { 4039 u8 status[0x8]; 4040 u8 reserved_at_8[0x18]; 4041 4042 u8 syndrome[0x20]; 4043 4044 u8 reserved_at_40[0xc0]; 4045 4046 struct mlx5_ifc_rqtc_bits rqt_context; 4047 }; 4048 4049 struct mlx5_ifc_query_rqt_in_bits { 4050 u8 opcode[0x10]; 4051 u8 reserved_at_10[0x10]; 4052 4053 u8 reserved_at_20[0x10]; 4054 u8 op_mod[0x10]; 4055 4056 u8 reserved_at_40[0x8]; 4057 u8 rqtn[0x18]; 4058 4059 u8 reserved_at_60[0x20]; 4060 }; 4061 4062 struct mlx5_ifc_query_rq_out_bits { 4063 u8 status[0x8]; 4064 u8 reserved_at_8[0x18]; 4065 4066 u8 syndrome[0x20]; 4067 4068 u8 reserved_at_40[0xc0]; 4069 4070 struct mlx5_ifc_rqc_bits rq_context; 4071 }; 4072 4073 struct mlx5_ifc_query_rq_in_bits { 4074 u8 opcode[0x10]; 4075 u8 reserved_at_10[0x10]; 4076 4077 u8 reserved_at_20[0x10]; 4078 u8 op_mod[0x10]; 4079 4080 u8 reserved_at_40[0x8]; 4081 u8 rqn[0x18]; 4082 4083 u8 reserved_at_60[0x20]; 4084 }; 4085 4086 struct mlx5_ifc_query_roce_address_out_bits { 4087 u8 status[0x8]; 4088 u8 reserved_at_8[0x18]; 4089 4090 u8 syndrome[0x20]; 4091 4092 u8 reserved_at_40[0x40]; 4093 4094 struct mlx5_ifc_roce_addr_layout_bits roce_address; 4095 }; 4096 4097 struct mlx5_ifc_query_roce_address_in_bits { 4098 u8 opcode[0x10]; 4099 u8 reserved_at_10[0x10]; 4100 4101 u8 reserved_at_20[0x10]; 4102 u8 op_mod[0x10]; 4103 4104 u8 roce_address_index[0x10]; 4105 u8 reserved_at_50[0xc]; 4106 u8 vhca_port_num[0x4]; 4107 4108 u8 reserved_at_60[0x20]; 4109 }; 4110 4111 struct mlx5_ifc_query_rmp_out_bits { 4112 u8 status[0x8]; 4113 u8 reserved_at_8[0x18]; 4114 4115 u8 syndrome[0x20]; 4116 4117 u8 reserved_at_40[0xc0]; 4118 4119 struct mlx5_ifc_rmpc_bits rmp_context; 4120 }; 4121 4122 struct mlx5_ifc_query_rmp_in_bits { 4123 u8 opcode[0x10]; 4124 u8 reserved_at_10[0x10]; 4125 4126 u8 reserved_at_20[0x10]; 4127 u8 op_mod[0x10]; 4128 4129 u8 reserved_at_40[0x8]; 4130 u8 rmpn[0x18]; 4131 4132 u8 reserved_at_60[0x20]; 4133 }; 4134 4135 struct mlx5_ifc_query_qp_out_bits { 4136 u8 status[0x8]; 4137 u8 reserved_at_8[0x18]; 4138 4139 u8 syndrome[0x20]; 4140 4141 u8 reserved_at_40[0x40]; 4142 4143 u8 opt_param_mask[0x20]; 4144 4145 u8 reserved_at_a0[0x20]; 4146 4147 struct mlx5_ifc_qpc_bits qpc; 4148 4149 u8 reserved_at_800[0x80]; 4150 4151 u8 pas[0][0x40]; 4152 }; 4153 4154 struct mlx5_ifc_query_qp_in_bits { 4155 u8 opcode[0x10]; 4156 u8 reserved_at_10[0x10]; 4157 4158 u8 reserved_at_20[0x10]; 4159 u8 op_mod[0x10]; 4160 4161 u8 reserved_at_40[0x8]; 4162 u8 qpn[0x18]; 4163 4164 u8 reserved_at_60[0x20]; 4165 }; 4166 4167 struct mlx5_ifc_query_q_counter_out_bits { 4168 u8 status[0x8]; 4169 u8 reserved_at_8[0x18]; 4170 4171 u8 syndrome[0x20]; 4172 4173 u8 reserved_at_40[0x40]; 4174 4175 u8 rx_write_requests[0x20]; 4176 4177 u8 reserved_at_a0[0x20]; 4178 4179 u8 rx_read_requests[0x20]; 4180 4181 u8 reserved_at_e0[0x20]; 4182 4183 u8 rx_atomic_requests[0x20]; 4184 4185 u8 reserved_at_120[0x20]; 4186 4187 u8 rx_dct_connect[0x20]; 4188 4189 u8 reserved_at_160[0x20]; 4190 4191 u8 out_of_buffer[0x20]; 4192 4193 u8 reserved_at_1a0[0x20]; 4194 4195 u8 out_of_sequence[0x20]; 4196 4197 u8 reserved_at_1e0[0x20]; 4198 4199 u8 duplicate_request[0x20]; 4200 4201 u8 reserved_at_220[0x20]; 4202 4203 u8 rnr_nak_retry_err[0x20]; 4204 4205 u8 reserved_at_260[0x20]; 4206 4207 u8 packet_seq_err[0x20]; 4208 4209 u8 reserved_at_2a0[0x20]; 4210 4211 u8 implied_nak_seq_err[0x20]; 4212 4213 u8 reserved_at_2e0[0x20]; 4214 4215 u8 local_ack_timeout_err[0x20]; 4216 4217 u8 reserved_at_320[0xa0]; 4218 4219 u8 resp_local_length_error[0x20]; 4220 4221 u8 req_local_length_error[0x20]; 4222 4223 u8 resp_local_qp_error[0x20]; 4224 4225 u8 local_operation_error[0x20]; 4226 4227 u8 resp_local_protection[0x20]; 4228 4229 u8 req_local_protection[0x20]; 4230 4231 u8 resp_cqe_error[0x20]; 4232 4233 u8 req_cqe_error[0x20]; 4234 4235 u8 req_mw_binding[0x20]; 4236 4237 u8 req_bad_response[0x20]; 4238 4239 u8 req_remote_invalid_request[0x20]; 4240 4241 u8 resp_remote_invalid_request[0x20]; 4242 4243 u8 req_remote_access_errors[0x20]; 4244 4245 u8 resp_remote_access_errors[0x20]; 4246 4247 u8 req_remote_operation_errors[0x20]; 4248 4249 u8 req_transport_retries_exceeded[0x20]; 4250 4251 u8 cq_overflow[0x20]; 4252 4253 u8 resp_cqe_flush_error[0x20]; 4254 4255 u8 req_cqe_flush_error[0x20]; 4256 4257 u8 reserved_at_620[0x1e0]; 4258 }; 4259 4260 struct mlx5_ifc_query_q_counter_in_bits { 4261 u8 opcode[0x10]; 4262 u8 reserved_at_10[0x10]; 4263 4264 u8 reserved_at_20[0x10]; 4265 u8 op_mod[0x10]; 4266 4267 u8 reserved_at_40[0x80]; 4268 4269 u8 clear[0x1]; 4270 u8 reserved_at_c1[0x1f]; 4271 4272 u8 reserved_at_e0[0x18]; 4273 u8 counter_set_id[0x8]; 4274 }; 4275 4276 struct mlx5_ifc_query_pages_out_bits { 4277 u8 status[0x8]; 4278 u8 reserved_at_8[0x18]; 4279 4280 u8 syndrome[0x20]; 4281 4282 u8 reserved_at_40[0x10]; 4283 u8 function_id[0x10]; 4284 4285 u8 num_pages[0x20]; 4286 }; 4287 4288 enum { 4289 MLX5_QUERY_PAGES_IN_OP_MOD_BOOT_PAGES = 0x1, 4290 MLX5_QUERY_PAGES_IN_OP_MOD_INIT_PAGES = 0x2, 4291 MLX5_QUERY_PAGES_IN_OP_MOD_REGULAR_PAGES = 0x3, 4292 }; 4293 4294 struct mlx5_ifc_query_pages_in_bits { 4295 u8 opcode[0x10]; 4296 u8 reserved_at_10[0x10]; 4297 4298 u8 reserved_at_20[0x10]; 4299 u8 op_mod[0x10]; 4300 4301 u8 reserved_at_40[0x10]; 4302 u8 function_id[0x10]; 4303 4304 u8 reserved_at_60[0x20]; 4305 }; 4306 4307 struct mlx5_ifc_query_nic_vport_context_out_bits { 4308 u8 status[0x8]; 4309 u8 reserved_at_8[0x18]; 4310 4311 u8 syndrome[0x20]; 4312 4313 u8 reserved_at_40[0x40]; 4314 4315 struct mlx5_ifc_nic_vport_context_bits nic_vport_context; 4316 }; 4317 4318 struct mlx5_ifc_query_nic_vport_context_in_bits { 4319 u8 opcode[0x10]; 4320 u8 reserved_at_10[0x10]; 4321 4322 u8 reserved_at_20[0x10]; 4323 u8 op_mod[0x10]; 4324 4325 u8 other_vport[0x1]; 4326 u8 reserved_at_41[0xf]; 4327 u8 vport_number[0x10]; 4328 4329 u8 reserved_at_60[0x5]; 4330 u8 allowed_list_type[0x3]; 4331 u8 reserved_at_68[0x18]; 4332 }; 4333 4334 struct mlx5_ifc_query_mkey_out_bits { 4335 u8 status[0x8]; 4336 u8 reserved_at_8[0x18]; 4337 4338 u8 syndrome[0x20]; 4339 4340 u8 reserved_at_40[0x40]; 4341 4342 struct mlx5_ifc_mkc_bits memory_key_mkey_entry; 4343 4344 u8 reserved_at_280[0x600]; 4345 4346 u8 bsf0_klm0_pas_mtt0_1[16][0x8]; 4347 4348 u8 bsf1_klm1_pas_mtt2_3[16][0x8]; 4349 }; 4350 4351 struct mlx5_ifc_query_mkey_in_bits { 4352 u8 opcode[0x10]; 4353 u8 reserved_at_10[0x10]; 4354 4355 u8 reserved_at_20[0x10]; 4356 u8 op_mod[0x10]; 4357 4358 u8 reserved_at_40[0x8]; 4359 u8 mkey_index[0x18]; 4360 4361 u8 pg_access[0x1]; 4362 u8 reserved_at_61[0x1f]; 4363 }; 4364 4365 struct mlx5_ifc_query_mad_demux_out_bits { 4366 u8 status[0x8]; 4367 u8 reserved_at_8[0x18]; 4368 4369 u8 syndrome[0x20]; 4370 4371 u8 reserved_at_40[0x40]; 4372 4373 u8 mad_dumux_parameters_block[0x20]; 4374 }; 4375 4376 struct mlx5_ifc_query_mad_demux_in_bits { 4377 u8 opcode[0x10]; 4378 u8 reserved_at_10[0x10]; 4379 4380 u8 reserved_at_20[0x10]; 4381 u8 op_mod[0x10]; 4382 4383 u8 reserved_at_40[0x40]; 4384 }; 4385 4386 struct mlx5_ifc_query_l2_table_entry_out_bits { 4387 u8 status[0x8]; 4388 u8 reserved_at_8[0x18]; 4389 4390 u8 syndrome[0x20]; 4391 4392 u8 reserved_at_40[0xa0]; 4393 4394 u8 reserved_at_e0[0x13]; 4395 u8 vlan_valid[0x1]; 4396 u8 vlan[0xc]; 4397 4398 struct mlx5_ifc_mac_address_layout_bits mac_address; 4399 4400 u8 reserved_at_140[0xc0]; 4401 }; 4402 4403 struct mlx5_ifc_query_l2_table_entry_in_bits { 4404 u8 opcode[0x10]; 4405 u8 reserved_at_10[0x10]; 4406 4407 u8 reserved_at_20[0x10]; 4408 u8 op_mod[0x10]; 4409 4410 u8 reserved_at_40[0x60]; 4411 4412 u8 reserved_at_a0[0x8]; 4413 u8 table_index[0x18]; 4414 4415 u8 reserved_at_c0[0x140]; 4416 }; 4417 4418 struct mlx5_ifc_query_issi_out_bits { 4419 u8 status[0x8]; 4420 u8 reserved_at_8[0x18]; 4421 4422 u8 syndrome[0x20]; 4423 4424 u8 reserved_at_40[0x10]; 4425 u8 current_issi[0x10]; 4426 4427 u8 reserved_at_60[0xa0]; 4428 4429 u8 reserved_at_100[76][0x8]; 4430 u8 supported_issi_dw0[0x20]; 4431 }; 4432 4433 struct mlx5_ifc_query_issi_in_bits { 4434 u8 opcode[0x10]; 4435 u8 reserved_at_10[0x10]; 4436 4437 u8 reserved_at_20[0x10]; 4438 u8 op_mod[0x10]; 4439 4440 u8 reserved_at_40[0x40]; 4441 }; 4442 4443 struct mlx5_ifc_set_driver_version_out_bits { 4444 u8 status[0x8]; 4445 u8 reserved_0[0x18]; 4446 4447 u8 syndrome[0x20]; 4448 u8 reserved_1[0x40]; 4449 }; 4450 4451 struct mlx5_ifc_set_driver_version_in_bits { 4452 u8 opcode[0x10]; 4453 u8 reserved_0[0x10]; 4454 4455 u8 reserved_1[0x10]; 4456 u8 op_mod[0x10]; 4457 4458 u8 reserved_2[0x40]; 4459 u8 driver_version[64][0x8]; 4460 }; 4461 4462 struct mlx5_ifc_query_hca_vport_pkey_out_bits { 4463 u8 status[0x8]; 4464 u8 reserved_at_8[0x18]; 4465 4466 u8 syndrome[0x20]; 4467 4468 u8 reserved_at_40[0x40]; 4469 4470 struct mlx5_ifc_pkey_bits pkey[0]; 4471 }; 4472 4473 struct mlx5_ifc_query_hca_vport_pkey_in_bits { 4474 u8 opcode[0x10]; 4475 u8 reserved_at_10[0x10]; 4476 4477 u8 reserved_at_20[0x10]; 4478 u8 op_mod[0x10]; 4479 4480 u8 other_vport[0x1]; 4481 u8 reserved_at_41[0xb]; 4482 u8 port_num[0x4]; 4483 u8 vport_number[0x10]; 4484 4485 u8 reserved_at_60[0x10]; 4486 u8 pkey_index[0x10]; 4487 }; 4488 4489 enum { 4490 MLX5_HCA_VPORT_SEL_PORT_GUID = 1 << 0, 4491 MLX5_HCA_VPORT_SEL_NODE_GUID = 1 << 1, 4492 MLX5_HCA_VPORT_SEL_STATE_POLICY = 1 << 2, 4493 }; 4494 4495 struct mlx5_ifc_query_hca_vport_gid_out_bits { 4496 u8 status[0x8]; 4497 u8 reserved_at_8[0x18]; 4498 4499 u8 syndrome[0x20]; 4500 4501 u8 reserved_at_40[0x20]; 4502 4503 u8 gids_num[0x10]; 4504 u8 reserved_at_70[0x10]; 4505 4506 struct mlx5_ifc_array128_auto_bits gid[0]; 4507 }; 4508 4509 struct mlx5_ifc_query_hca_vport_gid_in_bits { 4510 u8 opcode[0x10]; 4511 u8 reserved_at_10[0x10]; 4512 4513 u8 reserved_at_20[0x10]; 4514 u8 op_mod[0x10]; 4515 4516 u8 other_vport[0x1]; 4517 u8 reserved_at_41[0xb]; 4518 u8 port_num[0x4]; 4519 u8 vport_number[0x10]; 4520 4521 u8 reserved_at_60[0x10]; 4522 u8 gid_index[0x10]; 4523 }; 4524 4525 struct mlx5_ifc_query_hca_vport_context_out_bits { 4526 u8 status[0x8]; 4527 u8 reserved_at_8[0x18]; 4528 4529 u8 syndrome[0x20]; 4530 4531 u8 reserved_at_40[0x40]; 4532 4533 struct mlx5_ifc_hca_vport_context_bits hca_vport_context; 4534 }; 4535 4536 struct mlx5_ifc_query_hca_vport_context_in_bits { 4537 u8 opcode[0x10]; 4538 u8 reserved_at_10[0x10]; 4539 4540 u8 reserved_at_20[0x10]; 4541 u8 op_mod[0x10]; 4542 4543 u8 other_vport[0x1]; 4544 u8 reserved_at_41[0xb]; 4545 u8 port_num[0x4]; 4546 u8 vport_number[0x10]; 4547 4548 u8 reserved_at_60[0x20]; 4549 }; 4550 4551 struct mlx5_ifc_query_hca_cap_out_bits { 4552 u8 status[0x8]; 4553 u8 reserved_at_8[0x18]; 4554 4555 u8 syndrome[0x20]; 4556 4557 u8 reserved_at_40[0x40]; 4558 4559 union mlx5_ifc_hca_cap_union_bits capability; 4560 }; 4561 4562 struct mlx5_ifc_query_hca_cap_in_bits { 4563 u8 opcode[0x10]; 4564 u8 reserved_at_10[0x10]; 4565 4566 u8 reserved_at_20[0x10]; 4567 u8 op_mod[0x10]; 4568 4569 u8 reserved_at_40[0x40]; 4570 }; 4571 4572 struct mlx5_ifc_query_flow_table_out_bits { 4573 u8 status[0x8]; 4574 u8 reserved_at_8[0x18]; 4575 4576 u8 syndrome[0x20]; 4577 4578 u8 reserved_at_40[0x80]; 4579 4580 u8 reserved_at_c0[0x8]; 4581 u8 level[0x8]; 4582 u8 reserved_at_d0[0x8]; 4583 u8 log_size[0x8]; 4584 4585 u8 reserved_at_e0[0x120]; 4586 }; 4587 4588 struct mlx5_ifc_query_flow_table_in_bits { 4589 u8 opcode[0x10]; 4590 u8 reserved_at_10[0x10]; 4591 4592 u8 reserved_at_20[0x10]; 4593 u8 op_mod[0x10]; 4594 4595 u8 reserved_at_40[0x40]; 4596 4597 u8 table_type[0x8]; 4598 u8 reserved_at_88[0x18]; 4599 4600 u8 reserved_at_a0[0x8]; 4601 u8 table_id[0x18]; 4602 4603 u8 reserved_at_c0[0x140]; 4604 }; 4605 4606 struct mlx5_ifc_query_fte_out_bits { 4607 u8 status[0x8]; 4608 u8 reserved_at_8[0x18]; 4609 4610 u8 syndrome[0x20]; 4611 4612 u8 reserved_at_40[0x1c0]; 4613 4614 struct mlx5_ifc_flow_context_bits flow_context; 4615 }; 4616 4617 struct mlx5_ifc_query_fte_in_bits { 4618 u8 opcode[0x10]; 4619 u8 reserved_at_10[0x10]; 4620 4621 u8 reserved_at_20[0x10]; 4622 u8 op_mod[0x10]; 4623 4624 u8 reserved_at_40[0x40]; 4625 4626 u8 table_type[0x8]; 4627 u8 reserved_at_88[0x18]; 4628 4629 u8 reserved_at_a0[0x8]; 4630 u8 table_id[0x18]; 4631 4632 u8 reserved_at_c0[0x40]; 4633 4634 u8 flow_index[0x20]; 4635 4636 u8 reserved_at_120[0xe0]; 4637 }; 4638 4639 enum { 4640 MLX5_QUERY_FLOW_GROUP_OUT_MATCH_CRITERIA_ENABLE_OUTER_HEADERS = 0x0, 4641 MLX5_QUERY_FLOW_GROUP_OUT_MATCH_CRITERIA_ENABLE_MISC_PARAMETERS = 0x1, 4642 MLX5_QUERY_FLOW_GROUP_OUT_MATCH_CRITERIA_ENABLE_INNER_HEADERS = 0x2, 4643 MLX5_QUERY_FLOW_GROUP_IN_MATCH_CRITERIA_ENABLE_MISC_PARAMETERS_2 = 0X3, 4644 }; 4645 4646 struct mlx5_ifc_query_flow_group_out_bits { 4647 u8 status[0x8]; 4648 u8 reserved_at_8[0x18]; 4649 4650 u8 syndrome[0x20]; 4651 4652 u8 reserved_at_40[0xa0]; 4653 4654 u8 start_flow_index[0x20]; 4655 4656 u8 reserved_at_100[0x20]; 4657 4658 u8 end_flow_index[0x20]; 4659 4660 u8 reserved_at_140[0xa0]; 4661 4662 u8 reserved_at_1e0[0x18]; 4663 u8 match_criteria_enable[0x8]; 4664 4665 struct mlx5_ifc_fte_match_param_bits match_criteria; 4666 4667 u8 reserved_at_1200[0xe00]; 4668 }; 4669 4670 struct mlx5_ifc_query_flow_group_in_bits { 4671 u8 opcode[0x10]; 4672 u8 reserved_at_10[0x10]; 4673 4674 u8 reserved_at_20[0x10]; 4675 u8 op_mod[0x10]; 4676 4677 u8 reserved_at_40[0x40]; 4678 4679 u8 table_type[0x8]; 4680 u8 reserved_at_88[0x18]; 4681 4682 u8 reserved_at_a0[0x8]; 4683 u8 table_id[0x18]; 4684 4685 u8 group_id[0x20]; 4686 4687 u8 reserved_at_e0[0x120]; 4688 }; 4689 4690 struct mlx5_ifc_query_flow_counter_out_bits { 4691 u8 status[0x8]; 4692 u8 reserved_at_8[0x18]; 4693 4694 u8 syndrome[0x20]; 4695 4696 u8 reserved_at_40[0x40]; 4697 4698 struct mlx5_ifc_traffic_counter_bits flow_statistics[0]; 4699 }; 4700 4701 struct mlx5_ifc_query_flow_counter_in_bits { 4702 u8 opcode[0x10]; 4703 u8 reserved_at_10[0x10]; 4704 4705 u8 reserved_at_20[0x10]; 4706 u8 op_mod[0x10]; 4707 4708 u8 reserved_at_40[0x80]; 4709 4710 u8 clear[0x1]; 4711 u8 reserved_at_c1[0xf]; 4712 u8 num_of_counters[0x10]; 4713 4714 u8 flow_counter_id[0x20]; 4715 }; 4716 4717 struct mlx5_ifc_query_esw_vport_context_out_bits { 4718 u8 status[0x8]; 4719 u8 reserved_at_8[0x18]; 4720 4721 u8 syndrome[0x20]; 4722 4723 u8 reserved_at_40[0x40]; 4724 4725 struct mlx5_ifc_esw_vport_context_bits esw_vport_context; 4726 }; 4727 4728 struct mlx5_ifc_query_esw_vport_context_in_bits { 4729 u8 opcode[0x10]; 4730 u8 reserved_at_10[0x10]; 4731 4732 u8 reserved_at_20[0x10]; 4733 u8 op_mod[0x10]; 4734 4735 u8 other_vport[0x1]; 4736 u8 reserved_at_41[0xf]; 4737 u8 vport_number[0x10]; 4738 4739 u8 reserved_at_60[0x20]; 4740 }; 4741 4742 struct mlx5_ifc_modify_esw_vport_context_out_bits { 4743 u8 status[0x8]; 4744 u8 reserved_at_8[0x18]; 4745 4746 u8 syndrome[0x20]; 4747 4748 u8 reserved_at_40[0x40]; 4749 }; 4750 4751 struct mlx5_ifc_esw_vport_context_fields_select_bits { 4752 u8 reserved_at_0[0x1c]; 4753 u8 vport_cvlan_insert[0x1]; 4754 u8 vport_svlan_insert[0x1]; 4755 u8 vport_cvlan_strip[0x1]; 4756 u8 vport_svlan_strip[0x1]; 4757 }; 4758 4759 struct mlx5_ifc_modify_esw_vport_context_in_bits { 4760 u8 opcode[0x10]; 4761 u8 reserved_at_10[0x10]; 4762 4763 u8 reserved_at_20[0x10]; 4764 u8 op_mod[0x10]; 4765 4766 u8 other_vport[0x1]; 4767 u8 reserved_at_41[0xf]; 4768 u8 vport_number[0x10]; 4769 4770 struct mlx5_ifc_esw_vport_context_fields_select_bits field_select; 4771 4772 struct mlx5_ifc_esw_vport_context_bits esw_vport_context; 4773 }; 4774 4775 struct mlx5_ifc_query_eq_out_bits { 4776 u8 status[0x8]; 4777 u8 reserved_at_8[0x18]; 4778 4779 u8 syndrome[0x20]; 4780 4781 u8 reserved_at_40[0x40]; 4782 4783 struct mlx5_ifc_eqc_bits eq_context_entry; 4784 4785 u8 reserved_at_280[0x40]; 4786 4787 u8 event_bitmask[0x40]; 4788 4789 u8 reserved_at_300[0x580]; 4790 4791 u8 pas[0][0x40]; 4792 }; 4793 4794 struct mlx5_ifc_query_eq_in_bits { 4795 u8 opcode[0x10]; 4796 u8 reserved_at_10[0x10]; 4797 4798 u8 reserved_at_20[0x10]; 4799 u8 op_mod[0x10]; 4800 4801 u8 reserved_at_40[0x18]; 4802 u8 eq_number[0x8]; 4803 4804 u8 reserved_at_60[0x20]; 4805 }; 4806 4807 struct mlx5_ifc_encap_header_in_bits { 4808 u8 reserved_at_0[0x5]; 4809 u8 header_type[0x3]; 4810 u8 reserved_at_8[0xe]; 4811 u8 encap_header_size[0xa]; 4812 4813 u8 reserved_at_20[0x10]; 4814 u8 encap_header[2][0x8]; 4815 4816 u8 more_encap_header[0][0x8]; 4817 }; 4818 4819 struct mlx5_ifc_query_encap_header_out_bits { 4820 u8 status[0x8]; 4821 u8 reserved_at_8[0x18]; 4822 4823 u8 syndrome[0x20]; 4824 4825 u8 reserved_at_40[0xa0]; 4826 4827 struct mlx5_ifc_encap_header_in_bits encap_header[0]; 4828 }; 4829 4830 struct mlx5_ifc_query_encap_header_in_bits { 4831 u8 opcode[0x10]; 4832 u8 reserved_at_10[0x10]; 4833 4834 u8 reserved_at_20[0x10]; 4835 u8 op_mod[0x10]; 4836 4837 u8 encap_id[0x20]; 4838 4839 u8 reserved_at_60[0xa0]; 4840 }; 4841 4842 struct mlx5_ifc_alloc_encap_header_out_bits { 4843 u8 status[0x8]; 4844 u8 reserved_at_8[0x18]; 4845 4846 u8 syndrome[0x20]; 4847 4848 u8 encap_id[0x20]; 4849 4850 u8 reserved_at_60[0x20]; 4851 }; 4852 4853 struct mlx5_ifc_alloc_encap_header_in_bits { 4854 u8 opcode[0x10]; 4855 u8 reserved_at_10[0x10]; 4856 4857 u8 reserved_at_20[0x10]; 4858 u8 op_mod[0x10]; 4859 4860 u8 reserved_at_40[0xa0]; 4861 4862 struct mlx5_ifc_encap_header_in_bits encap_header; 4863 }; 4864 4865 struct mlx5_ifc_dealloc_encap_header_out_bits { 4866 u8 status[0x8]; 4867 u8 reserved_at_8[0x18]; 4868 4869 u8 syndrome[0x20]; 4870 4871 u8 reserved_at_40[0x40]; 4872 }; 4873 4874 struct mlx5_ifc_dealloc_encap_header_in_bits { 4875 u8 opcode[0x10]; 4876 u8 reserved_at_10[0x10]; 4877 4878 u8 reserved_20[0x10]; 4879 u8 op_mod[0x10]; 4880 4881 u8 encap_id[0x20]; 4882 4883 u8 reserved_60[0x20]; 4884 }; 4885 4886 struct mlx5_ifc_set_action_in_bits { 4887 u8 action_type[0x4]; 4888 u8 field[0xc]; 4889 u8 reserved_at_10[0x3]; 4890 u8 offset[0x5]; 4891 u8 reserved_at_18[0x3]; 4892 u8 length[0x5]; 4893 4894 u8 data[0x20]; 4895 }; 4896 4897 struct mlx5_ifc_add_action_in_bits { 4898 u8 action_type[0x4]; 4899 u8 field[0xc]; 4900 u8 reserved_at_10[0x10]; 4901 4902 u8 data[0x20]; 4903 }; 4904 4905 union mlx5_ifc_set_action_in_add_action_in_auto_bits { 4906 struct mlx5_ifc_set_action_in_bits set_action_in; 4907 struct mlx5_ifc_add_action_in_bits add_action_in; 4908 u8 reserved_at_0[0x40]; 4909 }; 4910 4911 enum { 4912 MLX5_ACTION_TYPE_SET = 0x1, 4913 MLX5_ACTION_TYPE_ADD = 0x2, 4914 }; 4915 4916 enum { 4917 MLX5_ACTION_IN_FIELD_OUT_SMAC_47_16 = 0x1, 4918 MLX5_ACTION_IN_FIELD_OUT_SMAC_15_0 = 0x2, 4919 MLX5_ACTION_IN_FIELD_OUT_ETHERTYPE = 0x3, 4920 MLX5_ACTION_IN_FIELD_OUT_DMAC_47_16 = 0x4, 4921 MLX5_ACTION_IN_FIELD_OUT_DMAC_15_0 = 0x5, 4922 MLX5_ACTION_IN_FIELD_OUT_IP_DSCP = 0x6, 4923 MLX5_ACTION_IN_FIELD_OUT_TCP_FLAGS = 0x7, 4924 MLX5_ACTION_IN_FIELD_OUT_TCP_SPORT = 0x8, 4925 MLX5_ACTION_IN_FIELD_OUT_TCP_DPORT = 0x9, 4926 MLX5_ACTION_IN_FIELD_OUT_IP_TTL = 0xa, 4927 MLX5_ACTION_IN_FIELD_OUT_UDP_SPORT = 0xb, 4928 MLX5_ACTION_IN_FIELD_OUT_UDP_DPORT = 0xc, 4929 MLX5_ACTION_IN_FIELD_OUT_SIPV6_127_96 = 0xd, 4930 MLX5_ACTION_IN_FIELD_OUT_SIPV6_95_64 = 0xe, 4931 MLX5_ACTION_IN_FIELD_OUT_SIPV6_63_32 = 0xf, 4932 MLX5_ACTION_IN_FIELD_OUT_SIPV6_31_0 = 0x10, 4933 MLX5_ACTION_IN_FIELD_OUT_DIPV6_127_96 = 0x11, 4934 MLX5_ACTION_IN_FIELD_OUT_DIPV6_95_64 = 0x12, 4935 MLX5_ACTION_IN_FIELD_OUT_DIPV6_63_32 = 0x13, 4936 MLX5_ACTION_IN_FIELD_OUT_DIPV6_31_0 = 0x14, 4937 MLX5_ACTION_IN_FIELD_OUT_SIPV4 = 0x15, 4938 MLX5_ACTION_IN_FIELD_OUT_DIPV4 = 0x16, 4939 MLX5_ACTION_IN_FIELD_OUT_IPV6_HOPLIMIT = 0x47, 4940 }; 4941 4942 struct mlx5_ifc_alloc_modify_header_context_out_bits { 4943 u8 status[0x8]; 4944 u8 reserved_at_8[0x18]; 4945 4946 u8 syndrome[0x20]; 4947 4948 u8 modify_header_id[0x20]; 4949 4950 u8 reserved_at_60[0x20]; 4951 }; 4952 4953 struct mlx5_ifc_alloc_modify_header_context_in_bits { 4954 u8 opcode[0x10]; 4955 u8 reserved_at_10[0x10]; 4956 4957 u8 reserved_at_20[0x10]; 4958 u8 op_mod[0x10]; 4959 4960 u8 reserved_at_40[0x20]; 4961 4962 u8 table_type[0x8]; 4963 u8 reserved_at_68[0x10]; 4964 u8 num_of_actions[0x8]; 4965 4966 union mlx5_ifc_set_action_in_add_action_in_auto_bits actions[0]; 4967 }; 4968 4969 struct mlx5_ifc_dealloc_modify_header_context_out_bits { 4970 u8 status[0x8]; 4971 u8 reserved_at_8[0x18]; 4972 4973 u8 syndrome[0x20]; 4974 4975 u8 reserved_at_40[0x40]; 4976 }; 4977 4978 struct mlx5_ifc_dealloc_modify_header_context_in_bits { 4979 u8 opcode[0x10]; 4980 u8 reserved_at_10[0x10]; 4981 4982 u8 reserved_at_20[0x10]; 4983 u8 op_mod[0x10]; 4984 4985 u8 modify_header_id[0x20]; 4986 4987 u8 reserved_at_60[0x20]; 4988 }; 4989 4990 struct mlx5_ifc_query_dct_out_bits { 4991 u8 status[0x8]; 4992 u8 reserved_at_8[0x18]; 4993 4994 u8 syndrome[0x20]; 4995 4996 u8 reserved_at_40[0x40]; 4997 4998 struct mlx5_ifc_dctc_bits dct_context_entry; 4999 5000 u8 reserved_at_280[0x180]; 5001 }; 5002 5003 struct mlx5_ifc_query_dct_in_bits { 5004 u8 opcode[0x10]; 5005 u8 reserved_at_10[0x10]; 5006 5007 u8 reserved_at_20[0x10]; 5008 u8 op_mod[0x10]; 5009 5010 u8 reserved_at_40[0x8]; 5011 u8 dctn[0x18]; 5012 5013 u8 reserved_at_60[0x20]; 5014 }; 5015 5016 struct mlx5_ifc_query_cq_out_bits { 5017 u8 status[0x8]; 5018 u8 reserved_at_8[0x18]; 5019 5020 u8 syndrome[0x20]; 5021 5022 u8 reserved_at_40[0x40]; 5023 5024 struct mlx5_ifc_cqc_bits cq_context; 5025 5026 u8 reserved_at_280[0x600]; 5027 5028 u8 pas[0][0x40]; 5029 }; 5030 5031 struct mlx5_ifc_query_cq_in_bits { 5032 u8 opcode[0x10]; 5033 u8 reserved_at_10[0x10]; 5034 5035 u8 reserved_at_20[0x10]; 5036 u8 op_mod[0x10]; 5037 5038 u8 reserved_at_40[0x8]; 5039 u8 cqn[0x18]; 5040 5041 u8 reserved_at_60[0x20]; 5042 }; 5043 5044 struct mlx5_ifc_query_cong_status_out_bits { 5045 u8 status[0x8]; 5046 u8 reserved_at_8[0x18]; 5047 5048 u8 syndrome[0x20]; 5049 5050 u8 reserved_at_40[0x20]; 5051 5052 u8 enable[0x1]; 5053 u8 tag_enable[0x1]; 5054 u8 reserved_at_62[0x1e]; 5055 }; 5056 5057 struct mlx5_ifc_query_cong_status_in_bits { 5058 u8 opcode[0x10]; 5059 u8 reserved_at_10[0x10]; 5060 5061 u8 reserved_at_20[0x10]; 5062 u8 op_mod[0x10]; 5063 5064 u8 reserved_at_40[0x18]; 5065 u8 priority[0x4]; 5066 u8 cong_protocol[0x4]; 5067 5068 u8 reserved_at_60[0x20]; 5069 }; 5070 5071 struct mlx5_ifc_query_cong_statistics_out_bits { 5072 u8 status[0x8]; 5073 u8 reserved_at_8[0x18]; 5074 5075 u8 syndrome[0x20]; 5076 5077 u8 reserved_at_40[0x40]; 5078 5079 u8 rp_cur_flows[0x20]; 5080 5081 u8 sum_flows[0x20]; 5082 5083 u8 rp_cnp_ignored_high[0x20]; 5084 5085 u8 rp_cnp_ignored_low[0x20]; 5086 5087 u8 rp_cnp_handled_high[0x20]; 5088 5089 u8 rp_cnp_handled_low[0x20]; 5090 5091 u8 reserved_at_140[0x100]; 5092 5093 u8 time_stamp_high[0x20]; 5094 5095 u8 time_stamp_low[0x20]; 5096 5097 u8 accumulators_period[0x20]; 5098 5099 u8 np_ecn_marked_roce_packets_high[0x20]; 5100 5101 u8 np_ecn_marked_roce_packets_low[0x20]; 5102 5103 u8 np_cnp_sent_high[0x20]; 5104 5105 u8 np_cnp_sent_low[0x20]; 5106 5107 u8 reserved_at_320[0x560]; 5108 }; 5109 5110 struct mlx5_ifc_query_cong_statistics_in_bits { 5111 u8 opcode[0x10]; 5112 u8 reserved_at_10[0x10]; 5113 5114 u8 reserved_at_20[0x10]; 5115 u8 op_mod[0x10]; 5116 5117 u8 clear[0x1]; 5118 u8 reserved_at_41[0x1f]; 5119 5120 u8 reserved_at_60[0x20]; 5121 }; 5122 5123 struct mlx5_ifc_query_cong_params_out_bits { 5124 u8 status[0x8]; 5125 u8 reserved_at_8[0x18]; 5126 5127 u8 syndrome[0x20]; 5128 5129 u8 reserved_at_40[0x40]; 5130 5131 union mlx5_ifc_cong_control_roce_ecn_auto_bits congestion_parameters; 5132 }; 5133 5134 struct mlx5_ifc_query_cong_params_in_bits { 5135 u8 opcode[0x10]; 5136 u8 reserved_at_10[0x10]; 5137 5138 u8 reserved_at_20[0x10]; 5139 u8 op_mod[0x10]; 5140 5141 u8 reserved_at_40[0x1c]; 5142 u8 cong_protocol[0x4]; 5143 5144 u8 reserved_at_60[0x20]; 5145 }; 5146 5147 struct mlx5_ifc_query_adapter_out_bits { 5148 u8 status[0x8]; 5149 u8 reserved_at_8[0x18]; 5150 5151 u8 syndrome[0x20]; 5152 5153 u8 reserved_at_40[0x40]; 5154 5155 struct mlx5_ifc_query_adapter_param_block_bits query_adapter_struct; 5156 }; 5157 5158 struct mlx5_ifc_query_adapter_in_bits { 5159 u8 opcode[0x10]; 5160 u8 reserved_at_10[0x10]; 5161 5162 u8 reserved_at_20[0x10]; 5163 u8 op_mod[0x10]; 5164 5165 u8 reserved_at_40[0x40]; 5166 }; 5167 5168 struct mlx5_ifc_qp_2rst_out_bits { 5169 u8 status[0x8]; 5170 u8 reserved_at_8[0x18]; 5171 5172 u8 syndrome[0x20]; 5173 5174 u8 reserved_at_40[0x40]; 5175 }; 5176 5177 struct mlx5_ifc_qp_2rst_in_bits { 5178 u8 opcode[0x10]; 5179 u8 reserved_at_10[0x10]; 5180 5181 u8 reserved_at_20[0x10]; 5182 u8 op_mod[0x10]; 5183 5184 u8 reserved_at_40[0x8]; 5185 u8 qpn[0x18]; 5186 5187 u8 reserved_at_60[0x20]; 5188 }; 5189 5190 struct mlx5_ifc_qp_2err_out_bits { 5191 u8 status[0x8]; 5192 u8 reserved_at_8[0x18]; 5193 5194 u8 syndrome[0x20]; 5195 5196 u8 reserved_at_40[0x40]; 5197 }; 5198 5199 struct mlx5_ifc_qp_2err_in_bits { 5200 u8 opcode[0x10]; 5201 u8 reserved_at_10[0x10]; 5202 5203 u8 reserved_at_20[0x10]; 5204 u8 op_mod[0x10]; 5205 5206 u8 reserved_at_40[0x8]; 5207 u8 qpn[0x18]; 5208 5209 u8 reserved_at_60[0x20]; 5210 }; 5211 5212 struct mlx5_ifc_page_fault_resume_out_bits { 5213 u8 status[0x8]; 5214 u8 reserved_at_8[0x18]; 5215 5216 u8 syndrome[0x20]; 5217 5218 u8 reserved_at_40[0x40]; 5219 }; 5220 5221 struct mlx5_ifc_page_fault_resume_in_bits { 5222 u8 opcode[0x10]; 5223 u8 reserved_at_10[0x10]; 5224 5225 u8 reserved_at_20[0x10]; 5226 u8 op_mod[0x10]; 5227 5228 u8 error[0x1]; 5229 u8 reserved_at_41[0x4]; 5230 u8 page_fault_type[0x3]; 5231 u8 wq_number[0x18]; 5232 5233 u8 reserved_at_60[0x8]; 5234 u8 token[0x18]; 5235 }; 5236 5237 struct mlx5_ifc_nop_out_bits { 5238 u8 status[0x8]; 5239 u8 reserved_at_8[0x18]; 5240 5241 u8 syndrome[0x20]; 5242 5243 u8 reserved_at_40[0x40]; 5244 }; 5245 5246 struct mlx5_ifc_nop_in_bits { 5247 u8 opcode[0x10]; 5248 u8 reserved_at_10[0x10]; 5249 5250 u8 reserved_at_20[0x10]; 5251 u8 op_mod[0x10]; 5252 5253 u8 reserved_at_40[0x40]; 5254 }; 5255 5256 struct mlx5_ifc_modify_vport_state_out_bits { 5257 u8 status[0x8]; 5258 u8 reserved_at_8[0x18]; 5259 5260 u8 syndrome[0x20]; 5261 5262 u8 reserved_at_40[0x40]; 5263 }; 5264 5265 struct mlx5_ifc_modify_vport_state_in_bits { 5266 u8 opcode[0x10]; 5267 u8 reserved_at_10[0x10]; 5268 5269 u8 reserved_at_20[0x10]; 5270 u8 op_mod[0x10]; 5271 5272 u8 other_vport[0x1]; 5273 u8 reserved_at_41[0xf]; 5274 u8 vport_number[0x10]; 5275 5276 u8 reserved_at_60[0x18]; 5277 u8 admin_state[0x4]; 5278 u8 reserved_at_7c[0x4]; 5279 }; 5280 5281 struct mlx5_ifc_modify_tis_out_bits { 5282 u8 status[0x8]; 5283 u8 reserved_at_8[0x18]; 5284 5285 u8 syndrome[0x20]; 5286 5287 u8 reserved_at_40[0x40]; 5288 }; 5289 5290 struct mlx5_ifc_modify_tis_bitmask_bits { 5291 u8 reserved_at_0[0x20]; 5292 5293 u8 reserved_at_20[0x1d]; 5294 u8 lag_tx_port_affinity[0x1]; 5295 u8 strict_lag_tx_port_affinity[0x1]; 5296 u8 prio[0x1]; 5297 }; 5298 5299 struct mlx5_ifc_modify_tis_in_bits { 5300 u8 opcode[0x10]; 5301 u8 reserved_at_10[0x10]; 5302 5303 u8 reserved_at_20[0x10]; 5304 u8 op_mod[0x10]; 5305 5306 u8 reserved_at_40[0x8]; 5307 u8 tisn[0x18]; 5308 5309 u8 reserved_at_60[0x20]; 5310 5311 struct mlx5_ifc_modify_tis_bitmask_bits bitmask; 5312 5313 u8 reserved_at_c0[0x40]; 5314 5315 struct mlx5_ifc_tisc_bits ctx; 5316 }; 5317 5318 struct mlx5_ifc_modify_tir_bitmask_bits { 5319 u8 reserved_at_0[0x20]; 5320 5321 u8 reserved_at_20[0x1b]; 5322 u8 self_lb_en[0x1]; 5323 u8 reserved_at_3c[0x1]; 5324 u8 hash[0x1]; 5325 u8 reserved_at_3e[0x1]; 5326 u8 lro[0x1]; 5327 }; 5328 5329 struct mlx5_ifc_modify_tir_out_bits { 5330 u8 status[0x8]; 5331 u8 reserved_at_8[0x18]; 5332 5333 u8 syndrome[0x20]; 5334 5335 u8 reserved_at_40[0x40]; 5336 }; 5337 5338 struct mlx5_ifc_modify_tir_in_bits { 5339 u8 opcode[0x10]; 5340 u8 reserved_at_10[0x10]; 5341 5342 u8 reserved_at_20[0x10]; 5343 u8 op_mod[0x10]; 5344 5345 u8 reserved_at_40[0x8]; 5346 u8 tirn[0x18]; 5347 5348 u8 reserved_at_60[0x20]; 5349 5350 struct mlx5_ifc_modify_tir_bitmask_bits bitmask; 5351 5352 u8 reserved_at_c0[0x40]; 5353 5354 struct mlx5_ifc_tirc_bits ctx; 5355 }; 5356 5357 struct mlx5_ifc_modify_sq_out_bits { 5358 u8 status[0x8]; 5359 u8 reserved_at_8[0x18]; 5360 5361 u8 syndrome[0x20]; 5362 5363 u8 reserved_at_40[0x40]; 5364 }; 5365 5366 struct mlx5_ifc_modify_sq_in_bits { 5367 u8 opcode[0x10]; 5368 u8 reserved_at_10[0x10]; 5369 5370 u8 reserved_at_20[0x10]; 5371 u8 op_mod[0x10]; 5372 5373 u8 sq_state[0x4]; 5374 u8 reserved_at_44[0x4]; 5375 u8 sqn[0x18]; 5376 5377 u8 reserved_at_60[0x20]; 5378 5379 u8 modify_bitmask[0x40]; 5380 5381 u8 reserved_at_c0[0x40]; 5382 5383 struct mlx5_ifc_sqc_bits ctx; 5384 }; 5385 5386 struct mlx5_ifc_modify_scheduling_element_out_bits { 5387 u8 status[0x8]; 5388 u8 reserved_at_8[0x18]; 5389 5390 u8 syndrome[0x20]; 5391 5392 u8 reserved_at_40[0x1c0]; 5393 }; 5394 5395 enum { 5396 MODIFY_SCHEDULING_ELEMENT_IN_MODIFY_BITMASK_BW_SHARE = 0x1, 5397 MODIFY_SCHEDULING_ELEMENT_IN_MODIFY_BITMASK_MAX_AVERAGE_BW = 0x2, 5398 }; 5399 5400 struct mlx5_ifc_modify_scheduling_element_in_bits { 5401 u8 opcode[0x10]; 5402 u8 reserved_at_10[0x10]; 5403 5404 u8 reserved_at_20[0x10]; 5405 u8 op_mod[0x10]; 5406 5407 u8 scheduling_hierarchy[0x8]; 5408 u8 reserved_at_48[0x18]; 5409 5410 u8 scheduling_element_id[0x20]; 5411 5412 u8 reserved_at_80[0x20]; 5413 5414 u8 modify_bitmask[0x20]; 5415 5416 u8 reserved_at_c0[0x40]; 5417 5418 struct mlx5_ifc_scheduling_context_bits scheduling_context; 5419 5420 u8 reserved_at_300[0x100]; 5421 }; 5422 5423 struct mlx5_ifc_modify_rqt_out_bits { 5424 u8 status[0x8]; 5425 u8 reserved_at_8[0x18]; 5426 5427 u8 syndrome[0x20]; 5428 5429 u8 reserved_at_40[0x40]; 5430 }; 5431 5432 struct mlx5_ifc_rqt_bitmask_bits { 5433 u8 reserved_at_0[0x20]; 5434 5435 u8 reserved_at_20[0x1f]; 5436 u8 rqn_list[0x1]; 5437 }; 5438 5439 struct mlx5_ifc_modify_rqt_in_bits { 5440 u8 opcode[0x10]; 5441 u8 reserved_at_10[0x10]; 5442 5443 u8 reserved_at_20[0x10]; 5444 u8 op_mod[0x10]; 5445 5446 u8 reserved_at_40[0x8]; 5447 u8 rqtn[0x18]; 5448 5449 u8 reserved_at_60[0x20]; 5450 5451 struct mlx5_ifc_rqt_bitmask_bits bitmask; 5452 5453 u8 reserved_at_c0[0x40]; 5454 5455 struct mlx5_ifc_rqtc_bits ctx; 5456 }; 5457 5458 struct mlx5_ifc_modify_rq_out_bits { 5459 u8 status[0x8]; 5460 u8 reserved_at_8[0x18]; 5461 5462 u8 syndrome[0x20]; 5463 5464 u8 reserved_at_40[0x40]; 5465 }; 5466 5467 enum { 5468 MLX5_MODIFY_RQ_IN_MODIFY_BITMASK_VSD = 1ULL << 1, 5469 MLX5_MODIFY_RQ_IN_MODIFY_BITMASK_SCATTER_FCS = 1ULL << 2, 5470 MLX5_MODIFY_RQ_IN_MODIFY_BITMASK_RQ_COUNTER_SET_ID = 1ULL << 3, 5471 }; 5472 5473 struct mlx5_ifc_modify_rq_in_bits { 5474 u8 opcode[0x10]; 5475 u8 reserved_at_10[0x10]; 5476 5477 u8 reserved_at_20[0x10]; 5478 u8 op_mod[0x10]; 5479 5480 u8 rq_state[0x4]; 5481 u8 reserved_at_44[0x4]; 5482 u8 rqn[0x18]; 5483 5484 u8 reserved_at_60[0x20]; 5485 5486 u8 modify_bitmask[0x40]; 5487 5488 u8 reserved_at_c0[0x40]; 5489 5490 struct mlx5_ifc_rqc_bits ctx; 5491 }; 5492 5493 struct mlx5_ifc_modify_rmp_out_bits { 5494 u8 status[0x8]; 5495 u8 reserved_at_8[0x18]; 5496 5497 u8 syndrome[0x20]; 5498 5499 u8 reserved_at_40[0x40]; 5500 }; 5501 5502 struct mlx5_ifc_rmp_bitmask_bits { 5503 u8 reserved_at_0[0x20]; 5504 5505 u8 reserved_at_20[0x1f]; 5506 u8 lwm[0x1]; 5507 }; 5508 5509 struct mlx5_ifc_modify_rmp_in_bits { 5510 u8 opcode[0x10]; 5511 u8 reserved_at_10[0x10]; 5512 5513 u8 reserved_at_20[0x10]; 5514 u8 op_mod[0x10]; 5515 5516 u8 rmp_state[0x4]; 5517 u8 reserved_at_44[0x4]; 5518 u8 rmpn[0x18]; 5519 5520 u8 reserved_at_60[0x20]; 5521 5522 struct mlx5_ifc_rmp_bitmask_bits bitmask; 5523 5524 u8 reserved_at_c0[0x40]; 5525 5526 struct mlx5_ifc_rmpc_bits ctx; 5527 }; 5528 5529 struct mlx5_ifc_modify_nic_vport_context_out_bits { 5530 u8 status[0x8]; 5531 u8 reserved_at_8[0x18]; 5532 5533 u8 syndrome[0x20]; 5534 5535 u8 reserved_at_40[0x40]; 5536 }; 5537 5538 struct mlx5_ifc_modify_nic_vport_field_select_bits { 5539 u8 reserved_at_0[0x12]; 5540 u8 affiliation[0x1]; 5541 u8 reserved_at_e[0x1]; 5542 u8 disable_uc_local_lb[0x1]; 5543 u8 disable_mc_local_lb[0x1]; 5544 u8 node_guid[0x1]; 5545 u8 port_guid[0x1]; 5546 u8 min_inline[0x1]; 5547 u8 mtu[0x1]; 5548 u8 change_event[0x1]; 5549 u8 promisc[0x1]; 5550 u8 permanent_address[0x1]; 5551 u8 addresses_list[0x1]; 5552 u8 roce_en[0x1]; 5553 u8 reserved_at_1f[0x1]; 5554 }; 5555 5556 struct mlx5_ifc_modify_nic_vport_context_in_bits { 5557 u8 opcode[0x10]; 5558 u8 reserved_at_10[0x10]; 5559 5560 u8 reserved_at_20[0x10]; 5561 u8 op_mod[0x10]; 5562 5563 u8 other_vport[0x1]; 5564 u8 reserved_at_41[0xf]; 5565 u8 vport_number[0x10]; 5566 5567 struct mlx5_ifc_modify_nic_vport_field_select_bits field_select; 5568 5569 u8 reserved_at_80[0x780]; 5570 5571 struct mlx5_ifc_nic_vport_context_bits nic_vport_context; 5572 }; 5573 5574 struct mlx5_ifc_modify_hca_vport_context_out_bits { 5575 u8 status[0x8]; 5576 u8 reserved_at_8[0x18]; 5577 5578 u8 syndrome[0x20]; 5579 5580 u8 reserved_at_40[0x40]; 5581 }; 5582 5583 struct mlx5_ifc_modify_hca_vport_context_in_bits { 5584 u8 opcode[0x10]; 5585 u8 reserved_at_10[0x10]; 5586 5587 u8 reserved_at_20[0x10]; 5588 u8 op_mod[0x10]; 5589 5590 u8 other_vport[0x1]; 5591 u8 reserved_at_41[0xb]; 5592 u8 port_num[0x4]; 5593 u8 vport_number[0x10]; 5594 5595 u8 reserved_at_60[0x20]; 5596 5597 struct mlx5_ifc_hca_vport_context_bits hca_vport_context; 5598 }; 5599 5600 struct mlx5_ifc_modify_cq_out_bits { 5601 u8 status[0x8]; 5602 u8 reserved_at_8[0x18]; 5603 5604 u8 syndrome[0x20]; 5605 5606 u8 reserved_at_40[0x40]; 5607 }; 5608 5609 enum { 5610 MLX5_MODIFY_CQ_IN_OP_MOD_MODIFY_CQ = 0x0, 5611 MLX5_MODIFY_CQ_IN_OP_MOD_RESIZE_CQ = 0x1, 5612 }; 5613 5614 struct mlx5_ifc_modify_cq_in_bits { 5615 u8 opcode[0x10]; 5616 u8 reserved_at_10[0x10]; 5617 5618 u8 reserved_at_20[0x10]; 5619 u8 op_mod[0x10]; 5620 5621 u8 reserved_at_40[0x8]; 5622 u8 cqn[0x18]; 5623 5624 union mlx5_ifc_modify_field_select_resize_field_select_auto_bits modify_field_select_resize_field_select; 5625 5626 struct mlx5_ifc_cqc_bits cq_context; 5627 5628 u8 reserved_at_280[0x600]; 5629 5630 u8 pas[0][0x40]; 5631 }; 5632 5633 struct mlx5_ifc_modify_cong_status_out_bits { 5634 u8 status[0x8]; 5635 u8 reserved_at_8[0x18]; 5636 5637 u8 syndrome[0x20]; 5638 5639 u8 reserved_at_40[0x40]; 5640 }; 5641 5642 struct mlx5_ifc_modify_cong_status_in_bits { 5643 u8 opcode[0x10]; 5644 u8 reserved_at_10[0x10]; 5645 5646 u8 reserved_at_20[0x10]; 5647 u8 op_mod[0x10]; 5648 5649 u8 reserved_at_40[0x18]; 5650 u8 priority[0x4]; 5651 u8 cong_protocol[0x4]; 5652 5653 u8 enable[0x1]; 5654 u8 tag_enable[0x1]; 5655 u8 reserved_at_62[0x1e]; 5656 }; 5657 5658 struct mlx5_ifc_modify_cong_params_out_bits { 5659 u8 status[0x8]; 5660 u8 reserved_at_8[0x18]; 5661 5662 u8 syndrome[0x20]; 5663 5664 u8 reserved_at_40[0x40]; 5665 }; 5666 5667 struct mlx5_ifc_modify_cong_params_in_bits { 5668 u8 opcode[0x10]; 5669 u8 reserved_at_10[0x10]; 5670 5671 u8 reserved_at_20[0x10]; 5672 u8 op_mod[0x10]; 5673 5674 u8 reserved_at_40[0x1c]; 5675 u8 cong_protocol[0x4]; 5676 5677 union mlx5_ifc_field_select_802_1_r_roce_auto_bits field_select; 5678 5679 u8 reserved_at_80[0x80]; 5680 5681 union mlx5_ifc_cong_control_roce_ecn_auto_bits congestion_parameters; 5682 }; 5683 5684 struct mlx5_ifc_manage_pages_out_bits { 5685 u8 status[0x8]; 5686 u8 reserved_at_8[0x18]; 5687 5688 u8 syndrome[0x20]; 5689 5690 u8 output_num_entries[0x20]; 5691 5692 u8 reserved_at_60[0x20]; 5693 5694 u8 pas[0][0x40]; 5695 }; 5696 5697 enum { 5698 MLX5_MANAGE_PAGES_IN_OP_MOD_ALLOCATION_FAIL = 0x0, 5699 MLX5_MANAGE_PAGES_IN_OP_MOD_ALLOCATION_SUCCESS = 0x1, 5700 MLX5_MANAGE_PAGES_IN_OP_MOD_HCA_RETURN_PAGES = 0x2, 5701 }; 5702 5703 struct mlx5_ifc_manage_pages_in_bits { 5704 u8 opcode[0x10]; 5705 u8 reserved_at_10[0x10]; 5706 5707 u8 reserved_at_20[0x10]; 5708 u8 op_mod[0x10]; 5709 5710 u8 reserved_at_40[0x10]; 5711 u8 function_id[0x10]; 5712 5713 u8 input_num_entries[0x20]; 5714 5715 u8 pas[0][0x40]; 5716 }; 5717 5718 struct mlx5_ifc_mad_ifc_out_bits { 5719 u8 status[0x8]; 5720 u8 reserved_at_8[0x18]; 5721 5722 u8 syndrome[0x20]; 5723 5724 u8 reserved_at_40[0x40]; 5725 5726 u8 response_mad_packet[256][0x8]; 5727 }; 5728 5729 struct mlx5_ifc_mad_ifc_in_bits { 5730 u8 opcode[0x10]; 5731 u8 reserved_at_10[0x10]; 5732 5733 u8 reserved_at_20[0x10]; 5734 u8 op_mod[0x10]; 5735 5736 u8 remote_lid[0x10]; 5737 u8 reserved_at_50[0x8]; 5738 u8 port[0x8]; 5739 5740 u8 reserved_at_60[0x20]; 5741 5742 u8 mad[256][0x8]; 5743 }; 5744 5745 struct mlx5_ifc_init_hca_out_bits { 5746 u8 status[0x8]; 5747 u8 reserved_at_8[0x18]; 5748 5749 u8 syndrome[0x20]; 5750 5751 u8 reserved_at_40[0x40]; 5752 }; 5753 5754 struct mlx5_ifc_init_hca_in_bits { 5755 u8 opcode[0x10]; 5756 u8 reserved_at_10[0x10]; 5757 5758 u8 reserved_at_20[0x10]; 5759 u8 op_mod[0x10]; 5760 5761 u8 reserved_at_40[0x40]; 5762 u8 sw_owner_id[4][0x20]; 5763 }; 5764 5765 struct mlx5_ifc_init2rtr_qp_out_bits { 5766 u8 status[0x8]; 5767 u8 reserved_at_8[0x18]; 5768 5769 u8 syndrome[0x20]; 5770 5771 u8 reserved_at_40[0x40]; 5772 }; 5773 5774 struct mlx5_ifc_init2rtr_qp_in_bits { 5775 u8 opcode[0x10]; 5776 u8 reserved_at_10[0x10]; 5777 5778 u8 reserved_at_20[0x10]; 5779 u8 op_mod[0x10]; 5780 5781 u8 reserved_at_40[0x8]; 5782 u8 qpn[0x18]; 5783 5784 u8 reserved_at_60[0x20]; 5785 5786 u8 opt_param_mask[0x20]; 5787 5788 u8 reserved_at_a0[0x20]; 5789 5790 struct mlx5_ifc_qpc_bits qpc; 5791 5792 u8 reserved_at_800[0x80]; 5793 }; 5794 5795 struct mlx5_ifc_init2init_qp_out_bits { 5796 u8 status[0x8]; 5797 u8 reserved_at_8[0x18]; 5798 5799 u8 syndrome[0x20]; 5800 5801 u8 reserved_at_40[0x40]; 5802 }; 5803 5804 struct mlx5_ifc_init2init_qp_in_bits { 5805 u8 opcode[0x10]; 5806 u8 reserved_at_10[0x10]; 5807 5808 u8 reserved_at_20[0x10]; 5809 u8 op_mod[0x10]; 5810 5811 u8 reserved_at_40[0x8]; 5812 u8 qpn[0x18]; 5813 5814 u8 reserved_at_60[0x20]; 5815 5816 u8 opt_param_mask[0x20]; 5817 5818 u8 reserved_at_a0[0x20]; 5819 5820 struct mlx5_ifc_qpc_bits qpc; 5821 5822 u8 reserved_at_800[0x80]; 5823 }; 5824 5825 struct mlx5_ifc_get_dropped_packet_log_out_bits { 5826 u8 status[0x8]; 5827 u8 reserved_at_8[0x18]; 5828 5829 u8 syndrome[0x20]; 5830 5831 u8 reserved_at_40[0x40]; 5832 5833 u8 packet_headers_log[128][0x8]; 5834 5835 u8 packet_syndrome[64][0x8]; 5836 }; 5837 5838 struct mlx5_ifc_get_dropped_packet_log_in_bits { 5839 u8 opcode[0x10]; 5840 u8 reserved_at_10[0x10]; 5841 5842 u8 reserved_at_20[0x10]; 5843 u8 op_mod[0x10]; 5844 5845 u8 reserved_at_40[0x40]; 5846 }; 5847 5848 struct mlx5_ifc_gen_eqe_in_bits { 5849 u8 opcode[0x10]; 5850 u8 reserved_at_10[0x10]; 5851 5852 u8 reserved_at_20[0x10]; 5853 u8 op_mod[0x10]; 5854 5855 u8 reserved_at_40[0x18]; 5856 u8 eq_number[0x8]; 5857 5858 u8 reserved_at_60[0x20]; 5859 5860 u8 eqe[64][0x8]; 5861 }; 5862 5863 struct mlx5_ifc_gen_eq_out_bits { 5864 u8 status[0x8]; 5865 u8 reserved_at_8[0x18]; 5866 5867 u8 syndrome[0x20]; 5868 5869 u8 reserved_at_40[0x40]; 5870 }; 5871 5872 struct mlx5_ifc_enable_hca_out_bits { 5873 u8 status[0x8]; 5874 u8 reserved_at_8[0x18]; 5875 5876 u8 syndrome[0x20]; 5877 5878 u8 reserved_at_40[0x20]; 5879 }; 5880 5881 struct mlx5_ifc_enable_hca_in_bits { 5882 u8 opcode[0x10]; 5883 u8 reserved_at_10[0x10]; 5884 5885 u8 reserved_at_20[0x10]; 5886 u8 op_mod[0x10]; 5887 5888 u8 reserved_at_40[0x10]; 5889 u8 function_id[0x10]; 5890 5891 u8 reserved_at_60[0x20]; 5892 }; 5893 5894 struct mlx5_ifc_drain_dct_out_bits { 5895 u8 status[0x8]; 5896 u8 reserved_at_8[0x18]; 5897 5898 u8 syndrome[0x20]; 5899 5900 u8 reserved_at_40[0x40]; 5901 }; 5902 5903 struct mlx5_ifc_drain_dct_in_bits { 5904 u8 opcode[0x10]; 5905 u8 reserved_at_10[0x10]; 5906 5907 u8 reserved_at_20[0x10]; 5908 u8 op_mod[0x10]; 5909 5910 u8 reserved_at_40[0x8]; 5911 u8 dctn[0x18]; 5912 5913 u8 reserved_at_60[0x20]; 5914 }; 5915 5916 struct mlx5_ifc_disable_hca_out_bits { 5917 u8 status[0x8]; 5918 u8 reserved_at_8[0x18]; 5919 5920 u8 syndrome[0x20]; 5921 5922 u8 reserved_at_40[0x20]; 5923 }; 5924 5925 struct mlx5_ifc_disable_hca_in_bits { 5926 u8 opcode[0x10]; 5927 u8 reserved_at_10[0x10]; 5928 5929 u8 reserved_at_20[0x10]; 5930 u8 op_mod[0x10]; 5931 5932 u8 reserved_at_40[0x10]; 5933 u8 function_id[0x10]; 5934 5935 u8 reserved_at_60[0x20]; 5936 }; 5937 5938 struct mlx5_ifc_detach_from_mcg_out_bits { 5939 u8 status[0x8]; 5940 u8 reserved_at_8[0x18]; 5941 5942 u8 syndrome[0x20]; 5943 5944 u8 reserved_at_40[0x40]; 5945 }; 5946 5947 struct mlx5_ifc_detach_from_mcg_in_bits { 5948 u8 opcode[0x10]; 5949 u8 reserved_at_10[0x10]; 5950 5951 u8 reserved_at_20[0x10]; 5952 u8 op_mod[0x10]; 5953 5954 u8 reserved_at_40[0x8]; 5955 u8 qpn[0x18]; 5956 5957 u8 reserved_at_60[0x20]; 5958 5959 u8 multicast_gid[16][0x8]; 5960 }; 5961 5962 struct mlx5_ifc_destroy_xrq_out_bits { 5963 u8 status[0x8]; 5964 u8 reserved_at_8[0x18]; 5965 5966 u8 syndrome[0x20]; 5967 5968 u8 reserved_at_40[0x40]; 5969 }; 5970 5971 struct mlx5_ifc_destroy_xrq_in_bits { 5972 u8 opcode[0x10]; 5973 u8 reserved_at_10[0x10]; 5974 5975 u8 reserved_at_20[0x10]; 5976 u8 op_mod[0x10]; 5977 5978 u8 reserved_at_40[0x8]; 5979 u8 xrqn[0x18]; 5980 5981 u8 reserved_at_60[0x20]; 5982 }; 5983 5984 struct mlx5_ifc_destroy_xrc_srq_out_bits { 5985 u8 status[0x8]; 5986 u8 reserved_at_8[0x18]; 5987 5988 u8 syndrome[0x20]; 5989 5990 u8 reserved_at_40[0x40]; 5991 }; 5992 5993 struct mlx5_ifc_destroy_xrc_srq_in_bits { 5994 u8 opcode[0x10]; 5995 u8 reserved_at_10[0x10]; 5996 5997 u8 reserved_at_20[0x10]; 5998 u8 op_mod[0x10]; 5999 6000 u8 reserved_at_40[0x8]; 6001 u8 xrc_srqn[0x18]; 6002 6003 u8 reserved_at_60[0x20]; 6004 }; 6005 6006 struct mlx5_ifc_destroy_tis_out_bits { 6007 u8 status[0x8]; 6008 u8 reserved_at_8[0x18]; 6009 6010 u8 syndrome[0x20]; 6011 6012 u8 reserved_at_40[0x40]; 6013 }; 6014 6015 struct mlx5_ifc_destroy_tis_in_bits { 6016 u8 opcode[0x10]; 6017 u8 reserved_at_10[0x10]; 6018 6019 u8 reserved_at_20[0x10]; 6020 u8 op_mod[0x10]; 6021 6022 u8 reserved_at_40[0x8]; 6023 u8 tisn[0x18]; 6024 6025 u8 reserved_at_60[0x20]; 6026 }; 6027 6028 struct mlx5_ifc_destroy_tir_out_bits { 6029 u8 status[0x8]; 6030 u8 reserved_at_8[0x18]; 6031 6032 u8 syndrome[0x20]; 6033 6034 u8 reserved_at_40[0x40]; 6035 }; 6036 6037 struct mlx5_ifc_destroy_tir_in_bits { 6038 u8 opcode[0x10]; 6039 u8 reserved_at_10[0x10]; 6040 6041 u8 reserved_at_20[0x10]; 6042 u8 op_mod[0x10]; 6043 6044 u8 reserved_at_40[0x8]; 6045 u8 tirn[0x18]; 6046 6047 u8 reserved_at_60[0x20]; 6048 }; 6049 6050 struct mlx5_ifc_destroy_srq_out_bits { 6051 u8 status[0x8]; 6052 u8 reserved_at_8[0x18]; 6053 6054 u8 syndrome[0x20]; 6055 6056 u8 reserved_at_40[0x40]; 6057 }; 6058 6059 struct mlx5_ifc_destroy_srq_in_bits { 6060 u8 opcode[0x10]; 6061 u8 reserved_at_10[0x10]; 6062 6063 u8 reserved_at_20[0x10]; 6064 u8 op_mod[0x10]; 6065 6066 u8 reserved_at_40[0x8]; 6067 u8 srqn[0x18]; 6068 6069 u8 reserved_at_60[0x20]; 6070 }; 6071 6072 struct mlx5_ifc_destroy_sq_out_bits { 6073 u8 status[0x8]; 6074 u8 reserved_at_8[0x18]; 6075 6076 u8 syndrome[0x20]; 6077 6078 u8 reserved_at_40[0x40]; 6079 }; 6080 6081 struct mlx5_ifc_destroy_sq_in_bits { 6082 u8 opcode[0x10]; 6083 u8 reserved_at_10[0x10]; 6084 6085 u8 reserved_at_20[0x10]; 6086 u8 op_mod[0x10]; 6087 6088 u8 reserved_at_40[0x8]; 6089 u8 sqn[0x18]; 6090 6091 u8 reserved_at_60[0x20]; 6092 }; 6093 6094 struct mlx5_ifc_destroy_scheduling_element_out_bits { 6095 u8 status[0x8]; 6096 u8 reserved_at_8[0x18]; 6097 6098 u8 syndrome[0x20]; 6099 6100 u8 reserved_at_40[0x1c0]; 6101 }; 6102 6103 struct mlx5_ifc_destroy_scheduling_element_in_bits { 6104 u8 opcode[0x10]; 6105 u8 reserved_at_10[0x10]; 6106 6107 u8 reserved_at_20[0x10]; 6108 u8 op_mod[0x10]; 6109 6110 u8 scheduling_hierarchy[0x8]; 6111 u8 reserved_at_48[0x18]; 6112 6113 u8 scheduling_element_id[0x20]; 6114 6115 u8 reserved_at_80[0x180]; 6116 }; 6117 6118 struct mlx5_ifc_destroy_rqt_out_bits { 6119 u8 status[0x8]; 6120 u8 reserved_at_8[0x18]; 6121 6122 u8 syndrome[0x20]; 6123 6124 u8 reserved_at_40[0x40]; 6125 }; 6126 6127 struct mlx5_ifc_destroy_rqt_in_bits { 6128 u8 opcode[0x10]; 6129 u8 reserved_at_10[0x10]; 6130 6131 u8 reserved_at_20[0x10]; 6132 u8 op_mod[0x10]; 6133 6134 u8 reserved_at_40[0x8]; 6135 u8 rqtn[0x18]; 6136 6137 u8 reserved_at_60[0x20]; 6138 }; 6139 6140 struct mlx5_ifc_destroy_rq_out_bits { 6141 u8 status[0x8]; 6142 u8 reserved_at_8[0x18]; 6143 6144 u8 syndrome[0x20]; 6145 6146 u8 reserved_at_40[0x40]; 6147 }; 6148 6149 struct mlx5_ifc_destroy_rq_in_bits { 6150 u8 opcode[0x10]; 6151 u8 reserved_at_10[0x10]; 6152 6153 u8 reserved_at_20[0x10]; 6154 u8 op_mod[0x10]; 6155 6156 u8 reserved_at_40[0x8]; 6157 u8 rqn[0x18]; 6158 6159 u8 reserved_at_60[0x20]; 6160 }; 6161 6162 struct mlx5_ifc_set_delay_drop_params_in_bits { 6163 u8 opcode[0x10]; 6164 u8 reserved_at_10[0x10]; 6165 6166 u8 reserved_at_20[0x10]; 6167 u8 op_mod[0x10]; 6168 6169 u8 reserved_at_40[0x20]; 6170 6171 u8 reserved_at_60[0x10]; 6172 u8 delay_drop_timeout[0x10]; 6173 }; 6174 6175 struct mlx5_ifc_set_delay_drop_params_out_bits { 6176 u8 status[0x8]; 6177 u8 reserved_at_8[0x18]; 6178 6179 u8 syndrome[0x20]; 6180 6181 u8 reserved_at_40[0x40]; 6182 }; 6183 6184 struct mlx5_ifc_destroy_rmp_out_bits { 6185 u8 status[0x8]; 6186 u8 reserved_at_8[0x18]; 6187 6188 u8 syndrome[0x20]; 6189 6190 u8 reserved_at_40[0x40]; 6191 }; 6192 6193 struct mlx5_ifc_destroy_rmp_in_bits { 6194 u8 opcode[0x10]; 6195 u8 reserved_at_10[0x10]; 6196 6197 u8 reserved_at_20[0x10]; 6198 u8 op_mod[0x10]; 6199 6200 u8 reserved_at_40[0x8]; 6201 u8 rmpn[0x18]; 6202 6203 u8 reserved_at_60[0x20]; 6204 }; 6205 6206 struct mlx5_ifc_destroy_qp_out_bits { 6207 u8 status[0x8]; 6208 u8 reserved_at_8[0x18]; 6209 6210 u8 syndrome[0x20]; 6211 6212 u8 reserved_at_40[0x40]; 6213 }; 6214 6215 struct mlx5_ifc_destroy_qp_in_bits { 6216 u8 opcode[0x10]; 6217 u8 reserved_at_10[0x10]; 6218 6219 u8 reserved_at_20[0x10]; 6220 u8 op_mod[0x10]; 6221 6222 u8 reserved_at_40[0x8]; 6223 u8 qpn[0x18]; 6224 6225 u8 reserved_at_60[0x20]; 6226 }; 6227 6228 struct mlx5_ifc_destroy_psv_out_bits { 6229 u8 status[0x8]; 6230 u8 reserved_at_8[0x18]; 6231 6232 u8 syndrome[0x20]; 6233 6234 u8 reserved_at_40[0x40]; 6235 }; 6236 6237 struct mlx5_ifc_destroy_psv_in_bits { 6238 u8 opcode[0x10]; 6239 u8 reserved_at_10[0x10]; 6240 6241 u8 reserved_at_20[0x10]; 6242 u8 op_mod[0x10]; 6243 6244 u8 reserved_at_40[0x8]; 6245 u8 psvn[0x18]; 6246 6247 u8 reserved_at_60[0x20]; 6248 }; 6249 6250 struct mlx5_ifc_destroy_mkey_out_bits { 6251 u8 status[0x8]; 6252 u8 reserved_at_8[0x18]; 6253 6254 u8 syndrome[0x20]; 6255 6256 u8 reserved_at_40[0x40]; 6257 }; 6258 6259 struct mlx5_ifc_destroy_mkey_in_bits { 6260 u8 opcode[0x10]; 6261 u8 reserved_at_10[0x10]; 6262 6263 u8 reserved_at_20[0x10]; 6264 u8 op_mod[0x10]; 6265 6266 u8 reserved_at_40[0x8]; 6267 u8 mkey_index[0x18]; 6268 6269 u8 reserved_at_60[0x20]; 6270 }; 6271 6272 struct mlx5_ifc_destroy_flow_table_out_bits { 6273 u8 status[0x8]; 6274 u8 reserved_at_8[0x18]; 6275 6276 u8 syndrome[0x20]; 6277 6278 u8 reserved_at_40[0x40]; 6279 }; 6280 6281 struct mlx5_ifc_destroy_flow_table_in_bits { 6282 u8 opcode[0x10]; 6283 u8 reserved_at_10[0x10]; 6284 6285 u8 reserved_at_20[0x10]; 6286 u8 op_mod[0x10]; 6287 6288 u8 other_vport[0x1]; 6289 u8 reserved_at_41[0xf]; 6290 u8 vport_number[0x10]; 6291 6292 u8 reserved_at_60[0x20]; 6293 6294 u8 table_type[0x8]; 6295 u8 reserved_at_88[0x18]; 6296 6297 u8 reserved_at_a0[0x8]; 6298 u8 table_id[0x18]; 6299 6300 u8 reserved_at_c0[0x140]; 6301 }; 6302 6303 struct mlx5_ifc_destroy_flow_group_out_bits { 6304 u8 status[0x8]; 6305 u8 reserved_at_8[0x18]; 6306 6307 u8 syndrome[0x20]; 6308 6309 u8 reserved_at_40[0x40]; 6310 }; 6311 6312 struct mlx5_ifc_destroy_flow_group_in_bits { 6313 u8 opcode[0x10]; 6314 u8 reserved_at_10[0x10]; 6315 6316 u8 reserved_at_20[0x10]; 6317 u8 op_mod[0x10]; 6318 6319 u8 other_vport[0x1]; 6320 u8 reserved_at_41[0xf]; 6321 u8 vport_number[0x10]; 6322 6323 u8 reserved_at_60[0x20]; 6324 6325 u8 table_type[0x8]; 6326 u8 reserved_at_88[0x18]; 6327 6328 u8 reserved_at_a0[0x8]; 6329 u8 table_id[0x18]; 6330 6331 u8 group_id[0x20]; 6332 6333 u8 reserved_at_e0[0x120]; 6334 }; 6335 6336 struct mlx5_ifc_destroy_eq_out_bits { 6337 u8 status[0x8]; 6338 u8 reserved_at_8[0x18]; 6339 6340 u8 syndrome[0x20]; 6341 6342 u8 reserved_at_40[0x40]; 6343 }; 6344 6345 struct mlx5_ifc_destroy_eq_in_bits { 6346 u8 opcode[0x10]; 6347 u8 reserved_at_10[0x10]; 6348 6349 u8 reserved_at_20[0x10]; 6350 u8 op_mod[0x10]; 6351 6352 u8 reserved_at_40[0x18]; 6353 u8 eq_number[0x8]; 6354 6355 u8 reserved_at_60[0x20]; 6356 }; 6357 6358 struct mlx5_ifc_destroy_dct_out_bits { 6359 u8 status[0x8]; 6360 u8 reserved_at_8[0x18]; 6361 6362 u8 syndrome[0x20]; 6363 6364 u8 reserved_at_40[0x40]; 6365 }; 6366 6367 struct mlx5_ifc_destroy_dct_in_bits { 6368 u8 opcode[0x10]; 6369 u8 reserved_at_10[0x10]; 6370 6371 u8 reserved_at_20[0x10]; 6372 u8 op_mod[0x10]; 6373 6374 u8 reserved_at_40[0x8]; 6375 u8 dctn[0x18]; 6376 6377 u8 reserved_at_60[0x20]; 6378 }; 6379 6380 struct mlx5_ifc_destroy_cq_out_bits { 6381 u8 status[0x8]; 6382 u8 reserved_at_8[0x18]; 6383 6384 u8 syndrome[0x20]; 6385 6386 u8 reserved_at_40[0x40]; 6387 }; 6388 6389 struct mlx5_ifc_destroy_cq_in_bits { 6390 u8 opcode[0x10]; 6391 u8 reserved_at_10[0x10]; 6392 6393 u8 reserved_at_20[0x10]; 6394 u8 op_mod[0x10]; 6395 6396 u8 reserved_at_40[0x8]; 6397 u8 cqn[0x18]; 6398 6399 u8 reserved_at_60[0x20]; 6400 }; 6401 6402 struct mlx5_ifc_delete_vxlan_udp_dport_out_bits { 6403 u8 status[0x8]; 6404 u8 reserved_at_8[0x18]; 6405 6406 u8 syndrome[0x20]; 6407 6408 u8 reserved_at_40[0x40]; 6409 }; 6410 6411 struct mlx5_ifc_delete_vxlan_udp_dport_in_bits { 6412 u8 opcode[0x10]; 6413 u8 reserved_at_10[0x10]; 6414 6415 u8 reserved_at_20[0x10]; 6416 u8 op_mod[0x10]; 6417 6418 u8 reserved_at_40[0x20]; 6419 6420 u8 reserved_at_60[0x10]; 6421 u8 vxlan_udp_port[0x10]; 6422 }; 6423 6424 struct mlx5_ifc_delete_l2_table_entry_out_bits { 6425 u8 status[0x8]; 6426 u8 reserved_at_8[0x18]; 6427 6428 u8 syndrome[0x20]; 6429 6430 u8 reserved_at_40[0x40]; 6431 }; 6432 6433 struct mlx5_ifc_delete_l2_table_entry_in_bits { 6434 u8 opcode[0x10]; 6435 u8 reserved_at_10[0x10]; 6436 6437 u8 reserved_at_20[0x10]; 6438 u8 op_mod[0x10]; 6439 6440 u8 reserved_at_40[0x60]; 6441 6442 u8 reserved_at_a0[0x8]; 6443 u8 table_index[0x18]; 6444 6445 u8 reserved_at_c0[0x140]; 6446 }; 6447 6448 struct mlx5_ifc_delete_fte_out_bits { 6449 u8 status[0x8]; 6450 u8 reserved_at_8[0x18]; 6451 6452 u8 syndrome[0x20]; 6453 6454 u8 reserved_at_40[0x40]; 6455 }; 6456 6457 struct mlx5_ifc_delete_fte_in_bits { 6458 u8 opcode[0x10]; 6459 u8 reserved_at_10[0x10]; 6460 6461 u8 reserved_at_20[0x10]; 6462 u8 op_mod[0x10]; 6463 6464 u8 other_vport[0x1]; 6465 u8 reserved_at_41[0xf]; 6466 u8 vport_number[0x10]; 6467 6468 u8 reserved_at_60[0x20]; 6469 6470 u8 table_type[0x8]; 6471 u8 reserved_at_88[0x18]; 6472 6473 u8 reserved_at_a0[0x8]; 6474 u8 table_id[0x18]; 6475 6476 u8 reserved_at_c0[0x40]; 6477 6478 u8 flow_index[0x20]; 6479 6480 u8 reserved_at_120[0xe0]; 6481 }; 6482 6483 struct mlx5_ifc_dealloc_xrcd_out_bits { 6484 u8 status[0x8]; 6485 u8 reserved_at_8[0x18]; 6486 6487 u8 syndrome[0x20]; 6488 6489 u8 reserved_at_40[0x40]; 6490 }; 6491 6492 struct mlx5_ifc_dealloc_xrcd_in_bits { 6493 u8 opcode[0x10]; 6494 u8 reserved_at_10[0x10]; 6495 6496 u8 reserved_at_20[0x10]; 6497 u8 op_mod[0x10]; 6498 6499 u8 reserved_at_40[0x8]; 6500 u8 xrcd[0x18]; 6501 6502 u8 reserved_at_60[0x20]; 6503 }; 6504 6505 struct mlx5_ifc_dealloc_uar_out_bits { 6506 u8 status[0x8]; 6507 u8 reserved_at_8[0x18]; 6508 6509 u8 syndrome[0x20]; 6510 6511 u8 reserved_at_40[0x40]; 6512 }; 6513 6514 struct mlx5_ifc_dealloc_uar_in_bits { 6515 u8 opcode[0x10]; 6516 u8 reserved_at_10[0x10]; 6517 6518 u8 reserved_at_20[0x10]; 6519 u8 op_mod[0x10]; 6520 6521 u8 reserved_at_40[0x8]; 6522 u8 uar[0x18]; 6523 6524 u8 reserved_at_60[0x20]; 6525 }; 6526 6527 struct mlx5_ifc_dealloc_transport_domain_out_bits { 6528 u8 status[0x8]; 6529 u8 reserved_at_8[0x18]; 6530 6531 u8 syndrome[0x20]; 6532 6533 u8 reserved_at_40[0x40]; 6534 }; 6535 6536 struct mlx5_ifc_dealloc_transport_domain_in_bits { 6537 u8 opcode[0x10]; 6538 u8 reserved_at_10[0x10]; 6539 6540 u8 reserved_at_20[0x10]; 6541 u8 op_mod[0x10]; 6542 6543 u8 reserved_at_40[0x8]; 6544 u8 transport_domain[0x18]; 6545 6546 u8 reserved_at_60[0x20]; 6547 }; 6548 6549 struct mlx5_ifc_dealloc_q_counter_out_bits { 6550 u8 status[0x8]; 6551 u8 reserved_at_8[0x18]; 6552 6553 u8 syndrome[0x20]; 6554 6555 u8 reserved_at_40[0x40]; 6556 }; 6557 6558 struct mlx5_ifc_dealloc_q_counter_in_bits { 6559 u8 opcode[0x10]; 6560 u8 reserved_at_10[0x10]; 6561 6562 u8 reserved_at_20[0x10]; 6563 u8 op_mod[0x10]; 6564 6565 u8 reserved_at_40[0x18]; 6566 u8 counter_set_id[0x8]; 6567 6568 u8 reserved_at_60[0x20]; 6569 }; 6570 6571 struct mlx5_ifc_dealloc_pd_out_bits { 6572 u8 status[0x8]; 6573 u8 reserved_at_8[0x18]; 6574 6575 u8 syndrome[0x20]; 6576 6577 u8 reserved_at_40[0x40]; 6578 }; 6579 6580 struct mlx5_ifc_dealloc_pd_in_bits { 6581 u8 opcode[0x10]; 6582 u8 reserved_at_10[0x10]; 6583 6584 u8 reserved_at_20[0x10]; 6585 u8 op_mod[0x10]; 6586 6587 u8 reserved_at_40[0x8]; 6588 u8 pd[0x18]; 6589 6590 u8 reserved_at_60[0x20]; 6591 }; 6592 6593 struct mlx5_ifc_dealloc_flow_counter_out_bits { 6594 u8 status[0x8]; 6595 u8 reserved_at_8[0x18]; 6596 6597 u8 syndrome[0x20]; 6598 6599 u8 reserved_at_40[0x40]; 6600 }; 6601 6602 struct mlx5_ifc_dealloc_flow_counter_in_bits { 6603 u8 opcode[0x10]; 6604 u8 reserved_at_10[0x10]; 6605 6606 u8 reserved_at_20[0x10]; 6607 u8 op_mod[0x10]; 6608 6609 u8 flow_counter_id[0x20]; 6610 6611 u8 reserved_at_60[0x20]; 6612 }; 6613 6614 struct mlx5_ifc_create_xrq_out_bits { 6615 u8 status[0x8]; 6616 u8 reserved_at_8[0x18]; 6617 6618 u8 syndrome[0x20]; 6619 6620 u8 reserved_at_40[0x8]; 6621 u8 xrqn[0x18]; 6622 6623 u8 reserved_at_60[0x20]; 6624 }; 6625 6626 struct mlx5_ifc_create_xrq_in_bits { 6627 u8 opcode[0x10]; 6628 u8 reserved_at_10[0x10]; 6629 6630 u8 reserved_at_20[0x10]; 6631 u8 op_mod[0x10]; 6632 6633 u8 reserved_at_40[0x40]; 6634 6635 struct mlx5_ifc_xrqc_bits xrq_context; 6636 }; 6637 6638 struct mlx5_ifc_create_xrc_srq_out_bits { 6639 u8 status[0x8]; 6640 u8 reserved_at_8[0x18]; 6641 6642 u8 syndrome[0x20]; 6643 6644 u8 reserved_at_40[0x8]; 6645 u8 xrc_srqn[0x18]; 6646 6647 u8 reserved_at_60[0x20]; 6648 }; 6649 6650 struct mlx5_ifc_create_xrc_srq_in_bits { 6651 u8 opcode[0x10]; 6652 u8 reserved_at_10[0x10]; 6653 6654 u8 reserved_at_20[0x10]; 6655 u8 op_mod[0x10]; 6656 6657 u8 reserved_at_40[0x40]; 6658 6659 struct mlx5_ifc_xrc_srqc_bits xrc_srq_context_entry; 6660 6661 u8 reserved_at_280[0x600]; 6662 6663 u8 pas[0][0x40]; 6664 }; 6665 6666 struct mlx5_ifc_create_tis_out_bits { 6667 u8 status[0x8]; 6668 u8 reserved_at_8[0x18]; 6669 6670 u8 syndrome[0x20]; 6671 6672 u8 reserved_at_40[0x8]; 6673 u8 tisn[0x18]; 6674 6675 u8 reserved_at_60[0x20]; 6676 }; 6677 6678 struct mlx5_ifc_create_tis_in_bits { 6679 u8 opcode[0x10]; 6680 u8 reserved_at_10[0x10]; 6681 6682 u8 reserved_at_20[0x10]; 6683 u8 op_mod[0x10]; 6684 6685 u8 reserved_at_40[0xc0]; 6686 6687 struct mlx5_ifc_tisc_bits ctx; 6688 }; 6689 6690 struct mlx5_ifc_create_tir_out_bits { 6691 u8 status[0x8]; 6692 u8 reserved_at_8[0x18]; 6693 6694 u8 syndrome[0x20]; 6695 6696 u8 reserved_at_40[0x8]; 6697 u8 tirn[0x18]; 6698 6699 u8 reserved_at_60[0x20]; 6700 }; 6701 6702 struct mlx5_ifc_create_tir_in_bits { 6703 u8 opcode[0x10]; 6704 u8 reserved_at_10[0x10]; 6705 6706 u8 reserved_at_20[0x10]; 6707 u8 op_mod[0x10]; 6708 6709 u8 reserved_at_40[0xc0]; 6710 6711 struct mlx5_ifc_tirc_bits ctx; 6712 }; 6713 6714 struct mlx5_ifc_create_srq_out_bits { 6715 u8 status[0x8]; 6716 u8 reserved_at_8[0x18]; 6717 6718 u8 syndrome[0x20]; 6719 6720 u8 reserved_at_40[0x8]; 6721 u8 srqn[0x18]; 6722 6723 u8 reserved_at_60[0x20]; 6724 }; 6725 6726 struct mlx5_ifc_create_srq_in_bits { 6727 u8 opcode[0x10]; 6728 u8 reserved_at_10[0x10]; 6729 6730 u8 reserved_at_20[0x10]; 6731 u8 op_mod[0x10]; 6732 6733 u8 reserved_at_40[0x40]; 6734 6735 struct mlx5_ifc_srqc_bits srq_context_entry; 6736 6737 u8 reserved_at_280[0x600]; 6738 6739 u8 pas[0][0x40]; 6740 }; 6741 6742 struct mlx5_ifc_create_sq_out_bits { 6743 u8 status[0x8]; 6744 u8 reserved_at_8[0x18]; 6745 6746 u8 syndrome[0x20]; 6747 6748 u8 reserved_at_40[0x8]; 6749 u8 sqn[0x18]; 6750 6751 u8 reserved_at_60[0x20]; 6752 }; 6753 6754 struct mlx5_ifc_create_sq_in_bits { 6755 u8 opcode[0x10]; 6756 u8 reserved_at_10[0x10]; 6757 6758 u8 reserved_at_20[0x10]; 6759 u8 op_mod[0x10]; 6760 6761 u8 reserved_at_40[0xc0]; 6762 6763 struct mlx5_ifc_sqc_bits ctx; 6764 }; 6765 6766 struct mlx5_ifc_create_scheduling_element_out_bits { 6767 u8 status[0x8]; 6768 u8 reserved_at_8[0x18]; 6769 6770 u8 syndrome[0x20]; 6771 6772 u8 reserved_at_40[0x40]; 6773 6774 u8 scheduling_element_id[0x20]; 6775 6776 u8 reserved_at_a0[0x160]; 6777 }; 6778 6779 struct mlx5_ifc_create_scheduling_element_in_bits { 6780 u8 opcode[0x10]; 6781 u8 reserved_at_10[0x10]; 6782 6783 u8 reserved_at_20[0x10]; 6784 u8 op_mod[0x10]; 6785 6786 u8 scheduling_hierarchy[0x8]; 6787 u8 reserved_at_48[0x18]; 6788 6789 u8 reserved_at_60[0xa0]; 6790 6791 struct mlx5_ifc_scheduling_context_bits scheduling_context; 6792 6793 u8 reserved_at_300[0x100]; 6794 }; 6795 6796 struct mlx5_ifc_create_rqt_out_bits { 6797 u8 status[0x8]; 6798 u8 reserved_at_8[0x18]; 6799 6800 u8 syndrome[0x20]; 6801 6802 u8 reserved_at_40[0x8]; 6803 u8 rqtn[0x18]; 6804 6805 u8 reserved_at_60[0x20]; 6806 }; 6807 6808 struct mlx5_ifc_create_rqt_in_bits { 6809 u8 opcode[0x10]; 6810 u8 reserved_at_10[0x10]; 6811 6812 u8 reserved_at_20[0x10]; 6813 u8 op_mod[0x10]; 6814 6815 u8 reserved_at_40[0xc0]; 6816 6817 struct mlx5_ifc_rqtc_bits rqt_context; 6818 }; 6819 6820 struct mlx5_ifc_create_rq_out_bits { 6821 u8 status[0x8]; 6822 u8 reserved_at_8[0x18]; 6823 6824 u8 syndrome[0x20]; 6825 6826 u8 reserved_at_40[0x8]; 6827 u8 rqn[0x18]; 6828 6829 u8 reserved_at_60[0x20]; 6830 }; 6831 6832 struct mlx5_ifc_create_rq_in_bits { 6833 u8 opcode[0x10]; 6834 u8 reserved_at_10[0x10]; 6835 6836 u8 reserved_at_20[0x10]; 6837 u8 op_mod[0x10]; 6838 6839 u8 reserved_at_40[0xc0]; 6840 6841 struct mlx5_ifc_rqc_bits ctx; 6842 }; 6843 6844 struct mlx5_ifc_create_rmp_out_bits { 6845 u8 status[0x8]; 6846 u8 reserved_at_8[0x18]; 6847 6848 u8 syndrome[0x20]; 6849 6850 u8 reserved_at_40[0x8]; 6851 u8 rmpn[0x18]; 6852 6853 u8 reserved_at_60[0x20]; 6854 }; 6855 6856 struct mlx5_ifc_create_rmp_in_bits { 6857 u8 opcode[0x10]; 6858 u8 reserved_at_10[0x10]; 6859 6860 u8 reserved_at_20[0x10]; 6861 u8 op_mod[0x10]; 6862 6863 u8 reserved_at_40[0xc0]; 6864 6865 struct mlx5_ifc_rmpc_bits ctx; 6866 }; 6867 6868 struct mlx5_ifc_create_qp_out_bits { 6869 u8 status[0x8]; 6870 u8 reserved_at_8[0x18]; 6871 6872 u8 syndrome[0x20]; 6873 6874 u8 reserved_at_40[0x8]; 6875 u8 qpn[0x18]; 6876 6877 u8 reserved_at_60[0x20]; 6878 }; 6879 6880 struct mlx5_ifc_create_qp_in_bits { 6881 u8 opcode[0x10]; 6882 u8 reserved_at_10[0x10]; 6883 6884 u8 reserved_at_20[0x10]; 6885 u8 op_mod[0x10]; 6886 6887 u8 reserved_at_40[0x40]; 6888 6889 u8 opt_param_mask[0x20]; 6890 6891 u8 reserved_at_a0[0x20]; 6892 6893 struct mlx5_ifc_qpc_bits qpc; 6894 6895 u8 reserved_at_800[0x80]; 6896 6897 u8 pas[0][0x40]; 6898 }; 6899 6900 struct mlx5_ifc_create_psv_out_bits { 6901 u8 status[0x8]; 6902 u8 reserved_at_8[0x18]; 6903 6904 u8 syndrome[0x20]; 6905 6906 u8 reserved_at_40[0x40]; 6907 6908 u8 reserved_at_80[0x8]; 6909 u8 psv0_index[0x18]; 6910 6911 u8 reserved_at_a0[0x8]; 6912 u8 psv1_index[0x18]; 6913 6914 u8 reserved_at_c0[0x8]; 6915 u8 psv2_index[0x18]; 6916 6917 u8 reserved_at_e0[0x8]; 6918 u8 psv3_index[0x18]; 6919 }; 6920 6921 struct mlx5_ifc_create_psv_in_bits { 6922 u8 opcode[0x10]; 6923 u8 reserved_at_10[0x10]; 6924 6925 u8 reserved_at_20[0x10]; 6926 u8 op_mod[0x10]; 6927 6928 u8 num_psv[0x4]; 6929 u8 reserved_at_44[0x4]; 6930 u8 pd[0x18]; 6931 6932 u8 reserved_at_60[0x20]; 6933 }; 6934 6935 struct mlx5_ifc_create_mkey_out_bits { 6936 u8 status[0x8]; 6937 u8 reserved_at_8[0x18]; 6938 6939 u8 syndrome[0x20]; 6940 6941 u8 reserved_at_40[0x8]; 6942 u8 mkey_index[0x18]; 6943 6944 u8 reserved_at_60[0x20]; 6945 }; 6946 6947 struct mlx5_ifc_create_mkey_in_bits { 6948 u8 opcode[0x10]; 6949 u8 reserved_at_10[0x10]; 6950 6951 u8 reserved_at_20[0x10]; 6952 u8 op_mod[0x10]; 6953 6954 u8 reserved_at_40[0x20]; 6955 6956 u8 pg_access[0x1]; 6957 u8 reserved_at_61[0x1f]; 6958 6959 struct mlx5_ifc_mkc_bits memory_key_mkey_entry; 6960 6961 u8 reserved_at_280[0x80]; 6962 6963 u8 translations_octword_actual_size[0x20]; 6964 6965 u8 reserved_at_320[0x560]; 6966 6967 u8 klm_pas_mtt[0][0x20]; 6968 }; 6969 6970 struct mlx5_ifc_create_flow_table_out_bits { 6971 u8 status[0x8]; 6972 u8 reserved_at_8[0x18]; 6973 6974 u8 syndrome[0x20]; 6975 6976 u8 reserved_at_40[0x8]; 6977 u8 table_id[0x18]; 6978 6979 u8 reserved_at_60[0x20]; 6980 }; 6981 6982 struct mlx5_ifc_flow_table_context_bits { 6983 u8 encap_en[0x1]; 6984 u8 decap_en[0x1]; 6985 u8 reserved_at_2[0x2]; 6986 u8 table_miss_action[0x4]; 6987 u8 level[0x8]; 6988 u8 reserved_at_10[0x8]; 6989 u8 log_size[0x8]; 6990 6991 u8 reserved_at_20[0x8]; 6992 u8 table_miss_id[0x18]; 6993 6994 u8 reserved_at_40[0x8]; 6995 u8 lag_master_next_table_id[0x18]; 6996 6997 u8 reserved_at_60[0xe0]; 6998 }; 6999 7000 struct mlx5_ifc_create_flow_table_in_bits { 7001 u8 opcode[0x10]; 7002 u8 reserved_at_10[0x10]; 7003 7004 u8 reserved_at_20[0x10]; 7005 u8 op_mod[0x10]; 7006 7007 u8 other_vport[0x1]; 7008 u8 reserved_at_41[0xf]; 7009 u8 vport_number[0x10]; 7010 7011 u8 reserved_at_60[0x20]; 7012 7013 u8 table_type[0x8]; 7014 u8 reserved_at_88[0x18]; 7015 7016 u8 reserved_at_a0[0x20]; 7017 7018 struct mlx5_ifc_flow_table_context_bits flow_table_context; 7019 }; 7020 7021 struct mlx5_ifc_create_flow_group_out_bits { 7022 u8 status[0x8]; 7023 u8 reserved_at_8[0x18]; 7024 7025 u8 syndrome[0x20]; 7026 7027 u8 reserved_at_40[0x8]; 7028 u8 group_id[0x18]; 7029 7030 u8 reserved_at_60[0x20]; 7031 }; 7032 7033 enum { 7034 MLX5_CREATE_FLOW_GROUP_IN_MATCH_CRITERIA_ENABLE_OUTER_HEADERS = 0x0, 7035 MLX5_CREATE_FLOW_GROUP_IN_MATCH_CRITERIA_ENABLE_MISC_PARAMETERS = 0x1, 7036 MLX5_CREATE_FLOW_GROUP_IN_MATCH_CRITERIA_ENABLE_INNER_HEADERS = 0x2, 7037 MLX5_CREATE_FLOW_GROUP_IN_MATCH_CRITERIA_ENABLE_MISC_PARAMETERS_2 = 0x3, 7038 }; 7039 7040 struct mlx5_ifc_create_flow_group_in_bits { 7041 u8 opcode[0x10]; 7042 u8 reserved_at_10[0x10]; 7043 7044 u8 reserved_at_20[0x10]; 7045 u8 op_mod[0x10]; 7046 7047 u8 other_vport[0x1]; 7048 u8 reserved_at_41[0xf]; 7049 u8 vport_number[0x10]; 7050 7051 u8 reserved_at_60[0x20]; 7052 7053 u8 table_type[0x8]; 7054 u8 reserved_at_88[0x18]; 7055 7056 u8 reserved_at_a0[0x8]; 7057 u8 table_id[0x18]; 7058 7059 u8 source_eswitch_owner_vhca_id_valid[0x1]; 7060 7061 u8 reserved_at_c1[0x1f]; 7062 7063 u8 start_flow_index[0x20]; 7064 7065 u8 reserved_at_100[0x20]; 7066 7067 u8 end_flow_index[0x20]; 7068 7069 u8 reserved_at_140[0xa0]; 7070 7071 u8 reserved_at_1e0[0x18]; 7072 u8 match_criteria_enable[0x8]; 7073 7074 struct mlx5_ifc_fte_match_param_bits match_criteria; 7075 7076 u8 reserved_at_1200[0xe00]; 7077 }; 7078 7079 struct mlx5_ifc_create_eq_out_bits { 7080 u8 status[0x8]; 7081 u8 reserved_at_8[0x18]; 7082 7083 u8 syndrome[0x20]; 7084 7085 u8 reserved_at_40[0x18]; 7086 u8 eq_number[0x8]; 7087 7088 u8 reserved_at_60[0x20]; 7089 }; 7090 7091 struct mlx5_ifc_create_eq_in_bits { 7092 u8 opcode[0x10]; 7093 u8 reserved_at_10[0x10]; 7094 7095 u8 reserved_at_20[0x10]; 7096 u8 op_mod[0x10]; 7097 7098 u8 reserved_at_40[0x40]; 7099 7100 struct mlx5_ifc_eqc_bits eq_context_entry; 7101 7102 u8 reserved_at_280[0x40]; 7103 7104 u8 event_bitmask[0x40]; 7105 7106 u8 reserved_at_300[0x580]; 7107 7108 u8 pas[0][0x40]; 7109 }; 7110 7111 struct mlx5_ifc_create_dct_out_bits { 7112 u8 status[0x8]; 7113 u8 reserved_at_8[0x18]; 7114 7115 u8 syndrome[0x20]; 7116 7117 u8 reserved_at_40[0x8]; 7118 u8 dctn[0x18]; 7119 7120 u8 reserved_at_60[0x20]; 7121 }; 7122 7123 struct mlx5_ifc_create_dct_in_bits { 7124 u8 opcode[0x10]; 7125 u8 reserved_at_10[0x10]; 7126 7127 u8 reserved_at_20[0x10]; 7128 u8 op_mod[0x10]; 7129 7130 u8 reserved_at_40[0x40]; 7131 7132 struct mlx5_ifc_dctc_bits dct_context_entry; 7133 7134 u8 reserved_at_280[0x180]; 7135 }; 7136 7137 struct mlx5_ifc_create_cq_out_bits { 7138 u8 status[0x8]; 7139 u8 reserved_at_8[0x18]; 7140 7141 u8 syndrome[0x20]; 7142 7143 u8 reserved_at_40[0x8]; 7144 u8 cqn[0x18]; 7145 7146 u8 reserved_at_60[0x20]; 7147 }; 7148 7149 struct mlx5_ifc_create_cq_in_bits { 7150 u8 opcode[0x10]; 7151 u8 reserved_at_10[0x10]; 7152 7153 u8 reserved_at_20[0x10]; 7154 u8 op_mod[0x10]; 7155 7156 u8 reserved_at_40[0x40]; 7157 7158 struct mlx5_ifc_cqc_bits cq_context; 7159 7160 u8 reserved_at_280[0x600]; 7161 7162 u8 pas[0][0x40]; 7163 }; 7164 7165 struct mlx5_ifc_config_int_moderation_out_bits { 7166 u8 status[0x8]; 7167 u8 reserved_at_8[0x18]; 7168 7169 u8 syndrome[0x20]; 7170 7171 u8 reserved_at_40[0x4]; 7172 u8 min_delay[0xc]; 7173 u8 int_vector[0x10]; 7174 7175 u8 reserved_at_60[0x20]; 7176 }; 7177 7178 enum { 7179 MLX5_CONFIG_INT_MODERATION_IN_OP_MOD_WRITE = 0x0, 7180 MLX5_CONFIG_INT_MODERATION_IN_OP_MOD_READ = 0x1, 7181 }; 7182 7183 struct mlx5_ifc_config_int_moderation_in_bits { 7184 u8 opcode[0x10]; 7185 u8 reserved_at_10[0x10]; 7186 7187 u8 reserved_at_20[0x10]; 7188 u8 op_mod[0x10]; 7189 7190 u8 reserved_at_40[0x4]; 7191 u8 min_delay[0xc]; 7192 u8 int_vector[0x10]; 7193 7194 u8 reserved_at_60[0x20]; 7195 }; 7196 7197 struct mlx5_ifc_attach_to_mcg_out_bits { 7198 u8 status[0x8]; 7199 u8 reserved_at_8[0x18]; 7200 7201 u8 syndrome[0x20]; 7202 7203 u8 reserved_at_40[0x40]; 7204 }; 7205 7206 struct mlx5_ifc_attach_to_mcg_in_bits { 7207 u8 opcode[0x10]; 7208 u8 reserved_at_10[0x10]; 7209 7210 u8 reserved_at_20[0x10]; 7211 u8 op_mod[0x10]; 7212 7213 u8 reserved_at_40[0x8]; 7214 u8 qpn[0x18]; 7215 7216 u8 reserved_at_60[0x20]; 7217 7218 u8 multicast_gid[16][0x8]; 7219 }; 7220 7221 struct mlx5_ifc_arm_xrq_out_bits { 7222 u8 status[0x8]; 7223 u8 reserved_at_8[0x18]; 7224 7225 u8 syndrome[0x20]; 7226 7227 u8 reserved_at_40[0x40]; 7228 }; 7229 7230 struct mlx5_ifc_arm_xrq_in_bits { 7231 u8 opcode[0x10]; 7232 u8 reserved_at_10[0x10]; 7233 7234 u8 reserved_at_20[0x10]; 7235 u8 op_mod[0x10]; 7236 7237 u8 reserved_at_40[0x8]; 7238 u8 xrqn[0x18]; 7239 7240 u8 reserved_at_60[0x10]; 7241 u8 lwm[0x10]; 7242 }; 7243 7244 struct mlx5_ifc_arm_xrc_srq_out_bits { 7245 u8 status[0x8]; 7246 u8 reserved_at_8[0x18]; 7247 7248 u8 syndrome[0x20]; 7249 7250 u8 reserved_at_40[0x40]; 7251 }; 7252 7253 enum { 7254 MLX5_ARM_XRC_SRQ_IN_OP_MOD_XRC_SRQ = 0x1, 7255 }; 7256 7257 struct mlx5_ifc_arm_xrc_srq_in_bits { 7258 u8 opcode[0x10]; 7259 u8 reserved_at_10[0x10]; 7260 7261 u8 reserved_at_20[0x10]; 7262 u8 op_mod[0x10]; 7263 7264 u8 reserved_at_40[0x8]; 7265 u8 xrc_srqn[0x18]; 7266 7267 u8 reserved_at_60[0x10]; 7268 u8 lwm[0x10]; 7269 }; 7270 7271 struct mlx5_ifc_arm_rq_out_bits { 7272 u8 status[0x8]; 7273 u8 reserved_at_8[0x18]; 7274 7275 u8 syndrome[0x20]; 7276 7277 u8 reserved_at_40[0x40]; 7278 }; 7279 7280 enum { 7281 MLX5_ARM_RQ_IN_OP_MOD_SRQ = 0x1, 7282 MLX5_ARM_RQ_IN_OP_MOD_XRQ = 0x2, 7283 }; 7284 7285 struct mlx5_ifc_arm_rq_in_bits { 7286 u8 opcode[0x10]; 7287 u8 reserved_at_10[0x10]; 7288 7289 u8 reserved_at_20[0x10]; 7290 u8 op_mod[0x10]; 7291 7292 u8 reserved_at_40[0x8]; 7293 u8 srq_number[0x18]; 7294 7295 u8 reserved_at_60[0x10]; 7296 u8 lwm[0x10]; 7297 }; 7298 7299 struct mlx5_ifc_arm_dct_out_bits { 7300 u8 status[0x8]; 7301 u8 reserved_at_8[0x18]; 7302 7303 u8 syndrome[0x20]; 7304 7305 u8 reserved_at_40[0x40]; 7306 }; 7307 7308 struct mlx5_ifc_arm_dct_in_bits { 7309 u8 opcode[0x10]; 7310 u8 reserved_at_10[0x10]; 7311 7312 u8 reserved_at_20[0x10]; 7313 u8 op_mod[0x10]; 7314 7315 u8 reserved_at_40[0x8]; 7316 u8 dct_number[0x18]; 7317 7318 u8 reserved_at_60[0x20]; 7319 }; 7320 7321 struct mlx5_ifc_alloc_xrcd_out_bits { 7322 u8 status[0x8]; 7323 u8 reserved_at_8[0x18]; 7324 7325 u8 syndrome[0x20]; 7326 7327 u8 reserved_at_40[0x8]; 7328 u8 xrcd[0x18]; 7329 7330 u8 reserved_at_60[0x20]; 7331 }; 7332 7333 struct mlx5_ifc_alloc_xrcd_in_bits { 7334 u8 opcode[0x10]; 7335 u8 reserved_at_10[0x10]; 7336 7337 u8 reserved_at_20[0x10]; 7338 u8 op_mod[0x10]; 7339 7340 u8 reserved_at_40[0x40]; 7341 }; 7342 7343 struct mlx5_ifc_alloc_uar_out_bits { 7344 u8 status[0x8]; 7345 u8 reserved_at_8[0x18]; 7346 7347 u8 syndrome[0x20]; 7348 7349 u8 reserved_at_40[0x8]; 7350 u8 uar[0x18]; 7351 7352 u8 reserved_at_60[0x20]; 7353 }; 7354 7355 struct mlx5_ifc_alloc_uar_in_bits { 7356 u8 opcode[0x10]; 7357 u8 reserved_at_10[0x10]; 7358 7359 u8 reserved_at_20[0x10]; 7360 u8 op_mod[0x10]; 7361 7362 u8 reserved_at_40[0x40]; 7363 }; 7364 7365 struct mlx5_ifc_alloc_transport_domain_out_bits { 7366 u8 status[0x8]; 7367 u8 reserved_at_8[0x18]; 7368 7369 u8 syndrome[0x20]; 7370 7371 u8 reserved_at_40[0x8]; 7372 u8 transport_domain[0x18]; 7373 7374 u8 reserved_at_60[0x20]; 7375 }; 7376 7377 struct mlx5_ifc_alloc_transport_domain_in_bits { 7378 u8 opcode[0x10]; 7379 u8 reserved_at_10[0x10]; 7380 7381 u8 reserved_at_20[0x10]; 7382 u8 op_mod[0x10]; 7383 7384 u8 reserved_at_40[0x40]; 7385 }; 7386 7387 struct mlx5_ifc_alloc_q_counter_out_bits { 7388 u8 status[0x8]; 7389 u8 reserved_at_8[0x18]; 7390 7391 u8 syndrome[0x20]; 7392 7393 u8 reserved_at_40[0x18]; 7394 u8 counter_set_id[0x8]; 7395 7396 u8 reserved_at_60[0x20]; 7397 }; 7398 7399 struct mlx5_ifc_alloc_q_counter_in_bits { 7400 u8 opcode[0x10]; 7401 u8 reserved_at_10[0x10]; 7402 7403 u8 reserved_at_20[0x10]; 7404 u8 op_mod[0x10]; 7405 7406 u8 reserved_at_40[0x40]; 7407 }; 7408 7409 struct mlx5_ifc_alloc_pd_out_bits { 7410 u8 status[0x8]; 7411 u8 reserved_at_8[0x18]; 7412 7413 u8 syndrome[0x20]; 7414 7415 u8 reserved_at_40[0x8]; 7416 u8 pd[0x18]; 7417 7418 u8 reserved_at_60[0x20]; 7419 }; 7420 7421 struct mlx5_ifc_alloc_pd_in_bits { 7422 u8 opcode[0x10]; 7423 u8 reserved_at_10[0x10]; 7424 7425 u8 reserved_at_20[0x10]; 7426 u8 op_mod[0x10]; 7427 7428 u8 reserved_at_40[0x40]; 7429 }; 7430 7431 struct mlx5_ifc_alloc_flow_counter_out_bits { 7432 u8 status[0x8]; 7433 u8 reserved_at_8[0x18]; 7434 7435 u8 syndrome[0x20]; 7436 7437 u8 flow_counter_id[0x20]; 7438 7439 u8 reserved_at_60[0x20]; 7440 }; 7441 7442 struct mlx5_ifc_alloc_flow_counter_in_bits { 7443 u8 opcode[0x10]; 7444 u8 reserved_at_10[0x10]; 7445 7446 u8 reserved_at_20[0x10]; 7447 u8 op_mod[0x10]; 7448 7449 u8 reserved_at_40[0x40]; 7450 }; 7451 7452 struct mlx5_ifc_add_vxlan_udp_dport_out_bits { 7453 u8 status[0x8]; 7454 u8 reserved_at_8[0x18]; 7455 7456 u8 syndrome[0x20]; 7457 7458 u8 reserved_at_40[0x40]; 7459 }; 7460 7461 struct mlx5_ifc_add_vxlan_udp_dport_in_bits { 7462 u8 opcode[0x10]; 7463 u8 reserved_at_10[0x10]; 7464 7465 u8 reserved_at_20[0x10]; 7466 u8 op_mod[0x10]; 7467 7468 u8 reserved_at_40[0x20]; 7469 7470 u8 reserved_at_60[0x10]; 7471 u8 vxlan_udp_port[0x10]; 7472 }; 7473 7474 struct mlx5_ifc_set_pp_rate_limit_out_bits { 7475 u8 status[0x8]; 7476 u8 reserved_at_8[0x18]; 7477 7478 u8 syndrome[0x20]; 7479 7480 u8 reserved_at_40[0x40]; 7481 }; 7482 7483 struct mlx5_ifc_set_pp_rate_limit_in_bits { 7484 u8 opcode[0x10]; 7485 u8 reserved_at_10[0x10]; 7486 7487 u8 reserved_at_20[0x10]; 7488 u8 op_mod[0x10]; 7489 7490 u8 reserved_at_40[0x10]; 7491 u8 rate_limit_index[0x10]; 7492 7493 u8 reserved_at_60[0x20]; 7494 7495 u8 rate_limit[0x20]; 7496 7497 u8 burst_upper_bound[0x20]; 7498 7499 u8 reserved_at_c0[0x10]; 7500 u8 typical_packet_size[0x10]; 7501 7502 u8 reserved_at_e0[0x120]; 7503 }; 7504 7505 struct mlx5_ifc_access_register_out_bits { 7506 u8 status[0x8]; 7507 u8 reserved_at_8[0x18]; 7508 7509 u8 syndrome[0x20]; 7510 7511 u8 reserved_at_40[0x40]; 7512 7513 u8 register_data[0][0x20]; 7514 }; 7515 7516 enum { 7517 MLX5_ACCESS_REGISTER_IN_OP_MOD_WRITE = 0x0, 7518 MLX5_ACCESS_REGISTER_IN_OP_MOD_READ = 0x1, 7519 }; 7520 7521 struct mlx5_ifc_access_register_in_bits { 7522 u8 opcode[0x10]; 7523 u8 reserved_at_10[0x10]; 7524 7525 u8 reserved_at_20[0x10]; 7526 u8 op_mod[0x10]; 7527 7528 u8 reserved_at_40[0x10]; 7529 u8 register_id[0x10]; 7530 7531 u8 argument[0x20]; 7532 7533 u8 register_data[0][0x20]; 7534 }; 7535 7536 struct mlx5_ifc_sltp_reg_bits { 7537 u8 status[0x4]; 7538 u8 version[0x4]; 7539 u8 local_port[0x8]; 7540 u8 pnat[0x2]; 7541 u8 reserved_at_12[0x2]; 7542 u8 lane[0x4]; 7543 u8 reserved_at_18[0x8]; 7544 7545 u8 reserved_at_20[0x20]; 7546 7547 u8 reserved_at_40[0x7]; 7548 u8 polarity[0x1]; 7549 u8 ob_tap0[0x8]; 7550 u8 ob_tap1[0x8]; 7551 u8 ob_tap2[0x8]; 7552 7553 u8 reserved_at_60[0xc]; 7554 u8 ob_preemp_mode[0x4]; 7555 u8 ob_reg[0x8]; 7556 u8 ob_bias[0x8]; 7557 7558 u8 reserved_at_80[0x20]; 7559 }; 7560 7561 struct mlx5_ifc_slrg_reg_bits { 7562 u8 status[0x4]; 7563 u8 version[0x4]; 7564 u8 local_port[0x8]; 7565 u8 pnat[0x2]; 7566 u8 reserved_at_12[0x2]; 7567 u8 lane[0x4]; 7568 u8 reserved_at_18[0x8]; 7569 7570 u8 time_to_link_up[0x10]; 7571 u8 reserved_at_30[0xc]; 7572 u8 grade_lane_speed[0x4]; 7573 7574 u8 grade_version[0x8]; 7575 u8 grade[0x18]; 7576 7577 u8 reserved_at_60[0x4]; 7578 u8 height_grade_type[0x4]; 7579 u8 height_grade[0x18]; 7580 7581 u8 height_dz[0x10]; 7582 u8 height_dv[0x10]; 7583 7584 u8 reserved_at_a0[0x10]; 7585 u8 height_sigma[0x10]; 7586 7587 u8 reserved_at_c0[0x20]; 7588 7589 u8 reserved_at_e0[0x4]; 7590 u8 phase_grade_type[0x4]; 7591 u8 phase_grade[0x18]; 7592 7593 u8 reserved_at_100[0x8]; 7594 u8 phase_eo_pos[0x8]; 7595 u8 reserved_at_110[0x8]; 7596 u8 phase_eo_neg[0x8]; 7597 7598 u8 ffe_set_tested[0x10]; 7599 u8 test_errors_per_lane[0x10]; 7600 }; 7601 7602 struct mlx5_ifc_pvlc_reg_bits { 7603 u8 reserved_at_0[0x8]; 7604 u8 local_port[0x8]; 7605 u8 reserved_at_10[0x10]; 7606 7607 u8 reserved_at_20[0x1c]; 7608 u8 vl_hw_cap[0x4]; 7609 7610 u8 reserved_at_40[0x1c]; 7611 u8 vl_admin[0x4]; 7612 7613 u8 reserved_at_60[0x1c]; 7614 u8 vl_operational[0x4]; 7615 }; 7616 7617 struct mlx5_ifc_pude_reg_bits { 7618 u8 swid[0x8]; 7619 u8 local_port[0x8]; 7620 u8 reserved_at_10[0x4]; 7621 u8 admin_status[0x4]; 7622 u8 reserved_at_18[0x4]; 7623 u8 oper_status[0x4]; 7624 7625 u8 reserved_at_20[0x60]; 7626 }; 7627 7628 struct mlx5_ifc_ptys_reg_bits { 7629 u8 reserved_at_0[0x1]; 7630 u8 an_disable_admin[0x1]; 7631 u8 an_disable_cap[0x1]; 7632 u8 reserved_at_3[0x5]; 7633 u8 local_port[0x8]; 7634 u8 reserved_at_10[0xd]; 7635 u8 proto_mask[0x3]; 7636 7637 u8 an_status[0x4]; 7638 u8 reserved_at_24[0x3c]; 7639 7640 u8 eth_proto_capability[0x20]; 7641 7642 u8 ib_link_width_capability[0x10]; 7643 u8 ib_proto_capability[0x10]; 7644 7645 u8 reserved_at_a0[0x20]; 7646 7647 u8 eth_proto_admin[0x20]; 7648 7649 u8 ib_link_width_admin[0x10]; 7650 u8 ib_proto_admin[0x10]; 7651 7652 u8 reserved_at_100[0x20]; 7653 7654 u8 eth_proto_oper[0x20]; 7655 7656 u8 ib_link_width_oper[0x10]; 7657 u8 ib_proto_oper[0x10]; 7658 7659 u8 reserved_at_160[0x1c]; 7660 u8 connector_type[0x4]; 7661 7662 u8 eth_proto_lp_advertise[0x20]; 7663 7664 u8 reserved_at_1a0[0x60]; 7665 }; 7666 7667 struct mlx5_ifc_mlcr_reg_bits { 7668 u8 reserved_at_0[0x8]; 7669 u8 local_port[0x8]; 7670 u8 reserved_at_10[0x20]; 7671 7672 u8 beacon_duration[0x10]; 7673 u8 reserved_at_40[0x10]; 7674 7675 u8 beacon_remain[0x10]; 7676 }; 7677 7678 struct mlx5_ifc_ptas_reg_bits { 7679 u8 reserved_at_0[0x20]; 7680 7681 u8 algorithm_options[0x10]; 7682 u8 reserved_at_30[0x4]; 7683 u8 repetitions_mode[0x4]; 7684 u8 num_of_repetitions[0x8]; 7685 7686 u8 grade_version[0x8]; 7687 u8 height_grade_type[0x4]; 7688 u8 phase_grade_type[0x4]; 7689 u8 height_grade_weight[0x8]; 7690 u8 phase_grade_weight[0x8]; 7691 7692 u8 gisim_measure_bits[0x10]; 7693 u8 adaptive_tap_measure_bits[0x10]; 7694 7695 u8 ber_bath_high_error_threshold[0x10]; 7696 u8 ber_bath_mid_error_threshold[0x10]; 7697 7698 u8 ber_bath_low_error_threshold[0x10]; 7699 u8 one_ratio_high_threshold[0x10]; 7700 7701 u8 one_ratio_high_mid_threshold[0x10]; 7702 u8 one_ratio_low_mid_threshold[0x10]; 7703 7704 u8 one_ratio_low_threshold[0x10]; 7705 u8 ndeo_error_threshold[0x10]; 7706 7707 u8 mixer_offset_step_size[0x10]; 7708 u8 reserved_at_110[0x8]; 7709 u8 mix90_phase_for_voltage_bath[0x8]; 7710 7711 u8 mixer_offset_start[0x10]; 7712 u8 mixer_offset_end[0x10]; 7713 7714 u8 reserved_at_140[0x15]; 7715 u8 ber_test_time[0xb]; 7716 }; 7717 7718 struct mlx5_ifc_pspa_reg_bits { 7719 u8 swid[0x8]; 7720 u8 local_port[0x8]; 7721 u8 sub_port[0x8]; 7722 u8 reserved_at_18[0x8]; 7723 7724 u8 reserved_at_20[0x20]; 7725 }; 7726 7727 struct mlx5_ifc_pqdr_reg_bits { 7728 u8 reserved_at_0[0x8]; 7729 u8 local_port[0x8]; 7730 u8 reserved_at_10[0x5]; 7731 u8 prio[0x3]; 7732 u8 reserved_at_18[0x6]; 7733 u8 mode[0x2]; 7734 7735 u8 reserved_at_20[0x20]; 7736 7737 u8 reserved_at_40[0x10]; 7738 u8 min_threshold[0x10]; 7739 7740 u8 reserved_at_60[0x10]; 7741 u8 max_threshold[0x10]; 7742 7743 u8 reserved_at_80[0x10]; 7744 u8 mark_probability_denominator[0x10]; 7745 7746 u8 reserved_at_a0[0x60]; 7747 }; 7748 7749 struct mlx5_ifc_ppsc_reg_bits { 7750 u8 reserved_at_0[0x8]; 7751 u8 local_port[0x8]; 7752 u8 reserved_at_10[0x10]; 7753 7754 u8 reserved_at_20[0x60]; 7755 7756 u8 reserved_at_80[0x1c]; 7757 u8 wrps_admin[0x4]; 7758 7759 u8 reserved_at_a0[0x1c]; 7760 u8 wrps_status[0x4]; 7761 7762 u8 reserved_at_c0[0x8]; 7763 u8 up_threshold[0x8]; 7764 u8 reserved_at_d0[0x8]; 7765 u8 down_threshold[0x8]; 7766 7767 u8 reserved_at_e0[0x20]; 7768 7769 u8 reserved_at_100[0x1c]; 7770 u8 srps_admin[0x4]; 7771 7772 u8 reserved_at_120[0x1c]; 7773 u8 srps_status[0x4]; 7774 7775 u8 reserved_at_140[0x40]; 7776 }; 7777 7778 struct mlx5_ifc_pplr_reg_bits { 7779 u8 reserved_at_0[0x8]; 7780 u8 local_port[0x8]; 7781 u8 reserved_at_10[0x10]; 7782 7783 u8 reserved_at_20[0x8]; 7784 u8 lb_cap[0x8]; 7785 u8 reserved_at_30[0x8]; 7786 u8 lb_en[0x8]; 7787 }; 7788 7789 struct mlx5_ifc_pplm_reg_bits { 7790 u8 reserved_at_0[0x8]; 7791 u8 local_port[0x8]; 7792 u8 reserved_at_10[0x10]; 7793 7794 u8 reserved_at_20[0x20]; 7795 7796 u8 port_profile_mode[0x8]; 7797 u8 static_port_profile[0x8]; 7798 u8 active_port_profile[0x8]; 7799 u8 reserved_at_58[0x8]; 7800 7801 u8 retransmission_active[0x8]; 7802 u8 fec_mode_active[0x18]; 7803 7804 u8 reserved_at_80[0x20]; 7805 }; 7806 7807 struct mlx5_ifc_ppcnt_reg_bits { 7808 u8 swid[0x8]; 7809 u8 local_port[0x8]; 7810 u8 pnat[0x2]; 7811 u8 reserved_at_12[0x8]; 7812 u8 grp[0x6]; 7813 7814 u8 clr[0x1]; 7815 u8 reserved_at_21[0x1c]; 7816 u8 prio_tc[0x3]; 7817 7818 union mlx5_ifc_eth_cntrs_grp_data_layout_auto_bits counter_set; 7819 }; 7820 7821 struct mlx5_ifc_mpcnt_reg_bits { 7822 u8 reserved_at_0[0x8]; 7823 u8 pcie_index[0x8]; 7824 u8 reserved_at_10[0xa]; 7825 u8 grp[0x6]; 7826 7827 u8 clr[0x1]; 7828 u8 reserved_at_21[0x1f]; 7829 7830 union mlx5_ifc_pcie_cntrs_grp_data_layout_auto_bits counter_set; 7831 }; 7832 7833 struct mlx5_ifc_ppad_reg_bits { 7834 u8 reserved_at_0[0x3]; 7835 u8 single_mac[0x1]; 7836 u8 reserved_at_4[0x4]; 7837 u8 local_port[0x8]; 7838 u8 mac_47_32[0x10]; 7839 7840 u8 mac_31_0[0x20]; 7841 7842 u8 reserved_at_40[0x40]; 7843 }; 7844 7845 struct mlx5_ifc_pmtu_reg_bits { 7846 u8 reserved_at_0[0x8]; 7847 u8 local_port[0x8]; 7848 u8 reserved_at_10[0x10]; 7849 7850 u8 max_mtu[0x10]; 7851 u8 reserved_at_30[0x10]; 7852 7853 u8 admin_mtu[0x10]; 7854 u8 reserved_at_50[0x10]; 7855 7856 u8 oper_mtu[0x10]; 7857 u8 reserved_at_70[0x10]; 7858 }; 7859 7860 struct mlx5_ifc_pmpr_reg_bits { 7861 u8 reserved_at_0[0x8]; 7862 u8 module[0x8]; 7863 u8 reserved_at_10[0x10]; 7864 7865 u8 reserved_at_20[0x18]; 7866 u8 attenuation_5g[0x8]; 7867 7868 u8 reserved_at_40[0x18]; 7869 u8 attenuation_7g[0x8]; 7870 7871 u8 reserved_at_60[0x18]; 7872 u8 attenuation_12g[0x8]; 7873 }; 7874 7875 struct mlx5_ifc_pmpe_reg_bits { 7876 u8 reserved_at_0[0x8]; 7877 u8 module[0x8]; 7878 u8 reserved_at_10[0xc]; 7879 u8 module_status[0x4]; 7880 7881 u8 reserved_at_20[0x60]; 7882 }; 7883 7884 struct mlx5_ifc_pmpc_reg_bits { 7885 u8 module_state_updated[32][0x8]; 7886 }; 7887 7888 struct mlx5_ifc_pmlpn_reg_bits { 7889 u8 reserved_at_0[0x4]; 7890 u8 mlpn_status[0x4]; 7891 u8 local_port[0x8]; 7892 u8 reserved_at_10[0x10]; 7893 7894 u8 e[0x1]; 7895 u8 reserved_at_21[0x1f]; 7896 }; 7897 7898 struct mlx5_ifc_pmlp_reg_bits { 7899 u8 rxtx[0x1]; 7900 u8 reserved_at_1[0x7]; 7901 u8 local_port[0x8]; 7902 u8 reserved_at_10[0x8]; 7903 u8 width[0x8]; 7904 7905 u8 lane0_module_mapping[0x20]; 7906 7907 u8 lane1_module_mapping[0x20]; 7908 7909 u8 lane2_module_mapping[0x20]; 7910 7911 u8 lane3_module_mapping[0x20]; 7912 7913 u8 reserved_at_a0[0x160]; 7914 }; 7915 7916 struct mlx5_ifc_pmaos_reg_bits { 7917 u8 reserved_at_0[0x8]; 7918 u8 module[0x8]; 7919 u8 reserved_at_10[0x4]; 7920 u8 admin_status[0x4]; 7921 u8 reserved_at_18[0x4]; 7922 u8 oper_status[0x4]; 7923 7924 u8 ase[0x1]; 7925 u8 ee[0x1]; 7926 u8 reserved_at_22[0x1c]; 7927 u8 e[0x2]; 7928 7929 u8 reserved_at_40[0x40]; 7930 }; 7931 7932 struct mlx5_ifc_plpc_reg_bits { 7933 u8 reserved_at_0[0x4]; 7934 u8 profile_id[0xc]; 7935 u8 reserved_at_10[0x4]; 7936 u8 proto_mask[0x4]; 7937 u8 reserved_at_18[0x8]; 7938 7939 u8 reserved_at_20[0x10]; 7940 u8 lane_speed[0x10]; 7941 7942 u8 reserved_at_40[0x17]; 7943 u8 lpbf[0x1]; 7944 u8 fec_mode_policy[0x8]; 7945 7946 u8 retransmission_capability[0x8]; 7947 u8 fec_mode_capability[0x18]; 7948 7949 u8 retransmission_support_admin[0x8]; 7950 u8 fec_mode_support_admin[0x18]; 7951 7952 u8 retransmission_request_admin[0x8]; 7953 u8 fec_mode_request_admin[0x18]; 7954 7955 u8 reserved_at_c0[0x80]; 7956 }; 7957 7958 struct mlx5_ifc_plib_reg_bits { 7959 u8 reserved_at_0[0x8]; 7960 u8 local_port[0x8]; 7961 u8 reserved_at_10[0x8]; 7962 u8 ib_port[0x8]; 7963 7964 u8 reserved_at_20[0x60]; 7965 }; 7966 7967 struct mlx5_ifc_plbf_reg_bits { 7968 u8 reserved_at_0[0x8]; 7969 u8 local_port[0x8]; 7970 u8 reserved_at_10[0xd]; 7971 u8 lbf_mode[0x3]; 7972 7973 u8 reserved_at_20[0x20]; 7974 }; 7975 7976 struct mlx5_ifc_pipg_reg_bits { 7977 u8 reserved_at_0[0x8]; 7978 u8 local_port[0x8]; 7979 u8 reserved_at_10[0x10]; 7980 7981 u8 dic[0x1]; 7982 u8 reserved_at_21[0x19]; 7983 u8 ipg[0x4]; 7984 u8 reserved_at_3e[0x2]; 7985 }; 7986 7987 struct mlx5_ifc_pifr_reg_bits { 7988 u8 reserved_at_0[0x8]; 7989 u8 local_port[0x8]; 7990 u8 reserved_at_10[0x10]; 7991 7992 u8 reserved_at_20[0xe0]; 7993 7994 u8 port_filter[8][0x20]; 7995 7996 u8 port_filter_update_en[8][0x20]; 7997 }; 7998 7999 struct mlx5_ifc_pfcc_reg_bits { 8000 u8 reserved_at_0[0x8]; 8001 u8 local_port[0x8]; 8002 u8 reserved_at_10[0xb]; 8003 u8 ppan_mask_n[0x1]; 8004 u8 minor_stall_mask[0x1]; 8005 u8 critical_stall_mask[0x1]; 8006 u8 reserved_at_1e[0x2]; 8007 8008 u8 ppan[0x4]; 8009 u8 reserved_at_24[0x4]; 8010 u8 prio_mask_tx[0x8]; 8011 u8 reserved_at_30[0x8]; 8012 u8 prio_mask_rx[0x8]; 8013 8014 u8 pptx[0x1]; 8015 u8 aptx[0x1]; 8016 u8 pptx_mask_n[0x1]; 8017 u8 reserved_at_43[0x5]; 8018 u8 pfctx[0x8]; 8019 u8 reserved_at_50[0x10]; 8020 8021 u8 pprx[0x1]; 8022 u8 aprx[0x1]; 8023 u8 pprx_mask_n[0x1]; 8024 u8 reserved_at_63[0x5]; 8025 u8 pfcrx[0x8]; 8026 u8 reserved_at_70[0x10]; 8027 8028 u8 device_stall_minor_watermark[0x10]; 8029 u8 device_stall_critical_watermark[0x10]; 8030 8031 u8 reserved_at_a0[0x60]; 8032 }; 8033 8034 struct mlx5_ifc_pelc_reg_bits { 8035 u8 op[0x4]; 8036 u8 reserved_at_4[0x4]; 8037 u8 local_port[0x8]; 8038 u8 reserved_at_10[0x10]; 8039 8040 u8 op_admin[0x8]; 8041 u8 op_capability[0x8]; 8042 u8 op_request[0x8]; 8043 u8 op_active[0x8]; 8044 8045 u8 admin[0x40]; 8046 8047 u8 capability[0x40]; 8048 8049 u8 request[0x40]; 8050 8051 u8 active[0x40]; 8052 8053 u8 reserved_at_140[0x80]; 8054 }; 8055 8056 struct mlx5_ifc_peir_reg_bits { 8057 u8 reserved_at_0[0x8]; 8058 u8 local_port[0x8]; 8059 u8 reserved_at_10[0x10]; 8060 8061 u8 reserved_at_20[0xc]; 8062 u8 error_count[0x4]; 8063 u8 reserved_at_30[0x10]; 8064 8065 u8 reserved_at_40[0xc]; 8066 u8 lane[0x4]; 8067 u8 reserved_at_50[0x8]; 8068 u8 error_type[0x8]; 8069 }; 8070 8071 struct mlx5_ifc_mpegc_reg_bits { 8072 u8 reserved_at_0[0x30]; 8073 u8 field_select[0x10]; 8074 8075 u8 tx_overflow_sense[0x1]; 8076 u8 mark_cqe[0x1]; 8077 u8 mark_cnp[0x1]; 8078 u8 reserved_at_43[0x1b]; 8079 u8 tx_lossy_overflow_oper[0x2]; 8080 8081 u8 reserved_at_60[0x100]; 8082 }; 8083 8084 struct mlx5_ifc_pcam_enhanced_features_bits { 8085 u8 reserved_at_0[0x6d]; 8086 u8 rx_icrc_encapsulated_counter[0x1]; 8087 u8 reserved_at_6e[0x8]; 8088 u8 pfcc_mask[0x1]; 8089 u8 reserved_at_77[0x4]; 8090 u8 rx_buffer_fullness_counters[0x1]; 8091 u8 ptys_connector_type[0x1]; 8092 u8 reserved_at_7d[0x1]; 8093 u8 ppcnt_discard_group[0x1]; 8094 u8 ppcnt_statistical_group[0x1]; 8095 }; 8096 8097 struct mlx5_ifc_pcam_regs_5000_to_507f_bits { 8098 u8 port_access_reg_cap_mask_127_to_96[0x20]; 8099 u8 port_access_reg_cap_mask_95_to_64[0x20]; 8100 u8 port_access_reg_cap_mask_63_to_32[0x20]; 8101 8102 u8 port_access_reg_cap_mask_31_to_13[0x13]; 8103 u8 pbmc[0x1]; 8104 u8 pptb[0x1]; 8105 u8 port_access_reg_cap_mask_10_to_0[0xb]; 8106 }; 8107 8108 struct mlx5_ifc_pcam_reg_bits { 8109 u8 reserved_at_0[0x8]; 8110 u8 feature_group[0x8]; 8111 u8 reserved_at_10[0x8]; 8112 u8 access_reg_group[0x8]; 8113 8114 u8 reserved_at_20[0x20]; 8115 8116 union { 8117 struct mlx5_ifc_pcam_regs_5000_to_507f_bits regs_5000_to_507f; 8118 u8 reserved_at_0[0x80]; 8119 } port_access_reg_cap_mask; 8120 8121 u8 reserved_at_c0[0x80]; 8122 8123 union { 8124 struct mlx5_ifc_pcam_enhanced_features_bits enhanced_features; 8125 u8 reserved_at_0[0x80]; 8126 } feature_cap_mask; 8127 8128 u8 reserved_at_1c0[0xc0]; 8129 }; 8130 8131 struct mlx5_ifc_mcam_enhanced_features_bits { 8132 u8 reserved_at_0[0x74]; 8133 u8 mark_tx_action_cnp[0x1]; 8134 u8 mark_tx_action_cqe[0x1]; 8135 u8 dynamic_tx_overflow[0x1]; 8136 u8 reserved_at_77[0x4]; 8137 u8 pcie_outbound_stalled[0x1]; 8138 u8 tx_overflow_buffer_pkt[0x1]; 8139 u8 mtpps_enh_out_per_adj[0x1]; 8140 u8 mtpps_fs[0x1]; 8141 u8 pcie_performance_group[0x1]; 8142 }; 8143 8144 struct mlx5_ifc_mcam_access_reg_bits { 8145 u8 reserved_at_0[0x1c]; 8146 u8 mcda[0x1]; 8147 u8 mcc[0x1]; 8148 u8 mcqi[0x1]; 8149 u8 reserved_at_1f[0x1]; 8150 8151 u8 regs_95_to_87[0x9]; 8152 u8 mpegc[0x1]; 8153 u8 regs_85_to_68[0x12]; 8154 u8 tracer_registers[0x4]; 8155 8156 u8 regs_63_to_32[0x20]; 8157 u8 regs_31_to_0[0x20]; 8158 }; 8159 8160 struct mlx5_ifc_mcam_reg_bits { 8161 u8 reserved_at_0[0x8]; 8162 u8 feature_group[0x8]; 8163 u8 reserved_at_10[0x8]; 8164 u8 access_reg_group[0x8]; 8165 8166 u8 reserved_at_20[0x20]; 8167 8168 union { 8169 struct mlx5_ifc_mcam_access_reg_bits access_regs; 8170 u8 reserved_at_0[0x80]; 8171 } mng_access_reg_cap_mask; 8172 8173 u8 reserved_at_c0[0x80]; 8174 8175 union { 8176 struct mlx5_ifc_mcam_enhanced_features_bits enhanced_features; 8177 u8 reserved_at_0[0x80]; 8178 } mng_feature_cap_mask; 8179 8180 u8 reserved_at_1c0[0x80]; 8181 }; 8182 8183 struct mlx5_ifc_qcam_access_reg_cap_mask { 8184 u8 qcam_access_reg_cap_mask_127_to_20[0x6C]; 8185 u8 qpdpm[0x1]; 8186 u8 qcam_access_reg_cap_mask_18_to_4[0x0F]; 8187 u8 qdpm[0x1]; 8188 u8 qpts[0x1]; 8189 u8 qcap[0x1]; 8190 u8 qcam_access_reg_cap_mask_0[0x1]; 8191 }; 8192 8193 struct mlx5_ifc_qcam_qos_feature_cap_mask { 8194 u8 qcam_qos_feature_cap_mask_127_to_1[0x7F]; 8195 u8 qpts_trust_both[0x1]; 8196 }; 8197 8198 struct mlx5_ifc_qcam_reg_bits { 8199 u8 reserved_at_0[0x8]; 8200 u8 feature_group[0x8]; 8201 u8 reserved_at_10[0x8]; 8202 u8 access_reg_group[0x8]; 8203 u8 reserved_at_20[0x20]; 8204 8205 union { 8206 struct mlx5_ifc_qcam_access_reg_cap_mask reg_cap; 8207 u8 reserved_at_0[0x80]; 8208 } qos_access_reg_cap_mask; 8209 8210 u8 reserved_at_c0[0x80]; 8211 8212 union { 8213 struct mlx5_ifc_qcam_qos_feature_cap_mask feature_cap; 8214 u8 reserved_at_0[0x80]; 8215 } qos_feature_cap_mask; 8216 8217 u8 reserved_at_1c0[0x80]; 8218 }; 8219 8220 struct mlx5_ifc_pcap_reg_bits { 8221 u8 reserved_at_0[0x8]; 8222 u8 local_port[0x8]; 8223 u8 reserved_at_10[0x10]; 8224 8225 u8 port_capability_mask[4][0x20]; 8226 }; 8227 8228 struct mlx5_ifc_paos_reg_bits { 8229 u8 swid[0x8]; 8230 u8 local_port[0x8]; 8231 u8 reserved_at_10[0x4]; 8232 u8 admin_status[0x4]; 8233 u8 reserved_at_18[0x4]; 8234 u8 oper_status[0x4]; 8235 8236 u8 ase[0x1]; 8237 u8 ee[0x1]; 8238 u8 reserved_at_22[0x1c]; 8239 u8 e[0x2]; 8240 8241 u8 reserved_at_40[0x40]; 8242 }; 8243 8244 struct mlx5_ifc_pamp_reg_bits { 8245 u8 reserved_at_0[0x8]; 8246 u8 opamp_group[0x8]; 8247 u8 reserved_at_10[0xc]; 8248 u8 opamp_group_type[0x4]; 8249 8250 u8 start_index[0x10]; 8251 u8 reserved_at_30[0x4]; 8252 u8 num_of_indices[0xc]; 8253 8254 u8 index_data[18][0x10]; 8255 }; 8256 8257 struct mlx5_ifc_pcmr_reg_bits { 8258 u8 reserved_at_0[0x8]; 8259 u8 local_port[0x8]; 8260 u8 reserved_at_10[0x2e]; 8261 u8 fcs_cap[0x1]; 8262 u8 reserved_at_3f[0x1f]; 8263 u8 fcs_chk[0x1]; 8264 u8 reserved_at_5f[0x1]; 8265 }; 8266 8267 struct mlx5_ifc_lane_2_module_mapping_bits { 8268 u8 reserved_at_0[0x6]; 8269 u8 rx_lane[0x2]; 8270 u8 reserved_at_8[0x6]; 8271 u8 tx_lane[0x2]; 8272 u8 reserved_at_10[0x8]; 8273 u8 module[0x8]; 8274 }; 8275 8276 struct mlx5_ifc_bufferx_reg_bits { 8277 u8 reserved_at_0[0x6]; 8278 u8 lossy[0x1]; 8279 u8 epsb[0x1]; 8280 u8 reserved_at_8[0xc]; 8281 u8 size[0xc]; 8282 8283 u8 xoff_threshold[0x10]; 8284 u8 xon_threshold[0x10]; 8285 }; 8286 8287 struct mlx5_ifc_set_node_in_bits { 8288 u8 node_description[64][0x8]; 8289 }; 8290 8291 struct mlx5_ifc_register_power_settings_bits { 8292 u8 reserved_at_0[0x18]; 8293 u8 power_settings_level[0x8]; 8294 8295 u8 reserved_at_20[0x60]; 8296 }; 8297 8298 struct mlx5_ifc_register_host_endianness_bits { 8299 u8 he[0x1]; 8300 u8 reserved_at_1[0x1f]; 8301 8302 u8 reserved_at_20[0x60]; 8303 }; 8304 8305 struct mlx5_ifc_umr_pointer_desc_argument_bits { 8306 u8 reserved_at_0[0x20]; 8307 8308 u8 mkey[0x20]; 8309 8310 u8 addressh_63_32[0x20]; 8311 8312 u8 addressl_31_0[0x20]; 8313 }; 8314 8315 struct mlx5_ifc_ud_adrs_vector_bits { 8316 u8 dc_key[0x40]; 8317 8318 u8 ext[0x1]; 8319 u8 reserved_at_41[0x7]; 8320 u8 destination_qp_dct[0x18]; 8321 8322 u8 static_rate[0x4]; 8323 u8 sl_eth_prio[0x4]; 8324 u8 fl[0x1]; 8325 u8 mlid[0x7]; 8326 u8 rlid_udp_sport[0x10]; 8327 8328 u8 reserved_at_80[0x20]; 8329 8330 u8 rmac_47_16[0x20]; 8331 8332 u8 rmac_15_0[0x10]; 8333 u8 tclass[0x8]; 8334 u8 hop_limit[0x8]; 8335 8336 u8 reserved_at_e0[0x1]; 8337 u8 grh[0x1]; 8338 u8 reserved_at_e2[0x2]; 8339 u8 src_addr_index[0x8]; 8340 u8 flow_label[0x14]; 8341 8342 u8 rgid_rip[16][0x8]; 8343 }; 8344 8345 struct mlx5_ifc_pages_req_event_bits { 8346 u8 reserved_at_0[0x10]; 8347 u8 function_id[0x10]; 8348 8349 u8 num_pages[0x20]; 8350 8351 u8 reserved_at_40[0xa0]; 8352 }; 8353 8354 struct mlx5_ifc_eqe_bits { 8355 u8 reserved_at_0[0x8]; 8356 u8 event_type[0x8]; 8357 u8 reserved_at_10[0x8]; 8358 u8 event_sub_type[0x8]; 8359 8360 u8 reserved_at_20[0xe0]; 8361 8362 union mlx5_ifc_event_auto_bits event_data; 8363 8364 u8 reserved_at_1e0[0x10]; 8365 u8 signature[0x8]; 8366 u8 reserved_at_1f8[0x7]; 8367 u8 owner[0x1]; 8368 }; 8369 8370 enum { 8371 MLX5_CMD_QUEUE_ENTRY_TYPE_PCIE_CMD_IF_TRANSPORT = 0x7, 8372 }; 8373 8374 struct mlx5_ifc_cmd_queue_entry_bits { 8375 u8 type[0x8]; 8376 u8 reserved_at_8[0x18]; 8377 8378 u8 input_length[0x20]; 8379 8380 u8 input_mailbox_pointer_63_32[0x20]; 8381 8382 u8 input_mailbox_pointer_31_9[0x17]; 8383 u8 reserved_at_77[0x9]; 8384 8385 u8 command_input_inline_data[16][0x8]; 8386 8387 u8 command_output_inline_data[16][0x8]; 8388 8389 u8 output_mailbox_pointer_63_32[0x20]; 8390 8391 u8 output_mailbox_pointer_31_9[0x17]; 8392 u8 reserved_at_1b7[0x9]; 8393 8394 u8 output_length[0x20]; 8395 8396 u8 token[0x8]; 8397 u8 signature[0x8]; 8398 u8 reserved_at_1f0[0x8]; 8399 u8 status[0x7]; 8400 u8 ownership[0x1]; 8401 }; 8402 8403 struct mlx5_ifc_cmd_out_bits { 8404 u8 status[0x8]; 8405 u8 reserved_at_8[0x18]; 8406 8407 u8 syndrome[0x20]; 8408 8409 u8 command_output[0x20]; 8410 }; 8411 8412 struct mlx5_ifc_cmd_in_bits { 8413 u8 opcode[0x10]; 8414 u8 reserved_at_10[0x10]; 8415 8416 u8 reserved_at_20[0x10]; 8417 u8 op_mod[0x10]; 8418 8419 u8 command[0][0x20]; 8420 }; 8421 8422 struct mlx5_ifc_cmd_if_box_bits { 8423 u8 mailbox_data[512][0x8]; 8424 8425 u8 reserved_at_1000[0x180]; 8426 8427 u8 next_pointer_63_32[0x20]; 8428 8429 u8 next_pointer_31_10[0x16]; 8430 u8 reserved_at_11b6[0xa]; 8431 8432 u8 block_number[0x20]; 8433 8434 u8 reserved_at_11e0[0x8]; 8435 u8 token[0x8]; 8436 u8 ctrl_signature[0x8]; 8437 u8 signature[0x8]; 8438 }; 8439 8440 struct mlx5_ifc_mtt_bits { 8441 u8 ptag_63_32[0x20]; 8442 8443 u8 ptag_31_8[0x18]; 8444 u8 reserved_at_38[0x6]; 8445 u8 wr_en[0x1]; 8446 u8 rd_en[0x1]; 8447 }; 8448 8449 struct mlx5_ifc_query_wol_rol_out_bits { 8450 u8 status[0x8]; 8451 u8 reserved_at_8[0x18]; 8452 8453 u8 syndrome[0x20]; 8454 8455 u8 reserved_at_40[0x10]; 8456 u8 rol_mode[0x8]; 8457 u8 wol_mode[0x8]; 8458 8459 u8 reserved_at_60[0x20]; 8460 }; 8461 8462 struct mlx5_ifc_query_wol_rol_in_bits { 8463 u8 opcode[0x10]; 8464 u8 reserved_at_10[0x10]; 8465 8466 u8 reserved_at_20[0x10]; 8467 u8 op_mod[0x10]; 8468 8469 u8 reserved_at_40[0x40]; 8470 }; 8471 8472 struct mlx5_ifc_set_wol_rol_out_bits { 8473 u8 status[0x8]; 8474 u8 reserved_at_8[0x18]; 8475 8476 u8 syndrome[0x20]; 8477 8478 u8 reserved_at_40[0x40]; 8479 }; 8480 8481 struct mlx5_ifc_set_wol_rol_in_bits { 8482 u8 opcode[0x10]; 8483 u8 reserved_at_10[0x10]; 8484 8485 u8 reserved_at_20[0x10]; 8486 u8 op_mod[0x10]; 8487 8488 u8 rol_mode_valid[0x1]; 8489 u8 wol_mode_valid[0x1]; 8490 u8 reserved_at_42[0xe]; 8491 u8 rol_mode[0x8]; 8492 u8 wol_mode[0x8]; 8493 8494 u8 reserved_at_60[0x20]; 8495 }; 8496 8497 enum { 8498 MLX5_INITIAL_SEG_NIC_INTERFACE_FULL_DRIVER = 0x0, 8499 MLX5_INITIAL_SEG_NIC_INTERFACE_DISABLED = 0x1, 8500 MLX5_INITIAL_SEG_NIC_INTERFACE_NO_DRAM_NIC = 0x2, 8501 }; 8502 8503 enum { 8504 MLX5_INITIAL_SEG_NIC_INTERFACE_SUPPORTED_FULL_DRIVER = 0x0, 8505 MLX5_INITIAL_SEG_NIC_INTERFACE_SUPPORTED_DISABLED = 0x1, 8506 MLX5_INITIAL_SEG_NIC_INTERFACE_SUPPORTED_NO_DRAM_NIC = 0x2, 8507 }; 8508 8509 enum { 8510 MLX5_INITIAL_SEG_HEALTH_SYNDROME_FW_INTERNAL_ERR = 0x1, 8511 MLX5_INITIAL_SEG_HEALTH_SYNDROME_DEAD_IRISC = 0x7, 8512 MLX5_INITIAL_SEG_HEALTH_SYNDROME_HW_FATAL_ERR = 0x8, 8513 MLX5_INITIAL_SEG_HEALTH_SYNDROME_FW_CRC_ERR = 0x9, 8514 MLX5_INITIAL_SEG_HEALTH_SYNDROME_ICM_FETCH_PCI_ERR = 0xa, 8515 MLX5_INITIAL_SEG_HEALTH_SYNDROME_ICM_PAGE_ERR = 0xb, 8516 MLX5_INITIAL_SEG_HEALTH_SYNDROME_ASYNCHRONOUS_EQ_BUF_OVERRUN = 0xc, 8517 MLX5_INITIAL_SEG_HEALTH_SYNDROME_EQ_IN_ERR = 0xd, 8518 MLX5_INITIAL_SEG_HEALTH_SYNDROME_EQ_INV = 0xe, 8519 MLX5_INITIAL_SEG_HEALTH_SYNDROME_FFSER_ERR = 0xf, 8520 MLX5_INITIAL_SEG_HEALTH_SYNDROME_HIGH_TEMP_ERR = 0x10, 8521 }; 8522 8523 struct mlx5_ifc_initial_seg_bits { 8524 u8 fw_rev_minor[0x10]; 8525 u8 fw_rev_major[0x10]; 8526 8527 u8 cmd_interface_rev[0x10]; 8528 u8 fw_rev_subminor[0x10]; 8529 8530 u8 reserved_at_40[0x40]; 8531 8532 u8 cmdq_phy_addr_63_32[0x20]; 8533 8534 u8 cmdq_phy_addr_31_12[0x14]; 8535 u8 reserved_at_b4[0x2]; 8536 u8 nic_interface[0x2]; 8537 u8 log_cmdq_size[0x4]; 8538 u8 log_cmdq_stride[0x4]; 8539 8540 u8 command_doorbell_vector[0x20]; 8541 8542 u8 reserved_at_e0[0xf00]; 8543 8544 u8 initializing[0x1]; 8545 u8 reserved_at_fe1[0x4]; 8546 u8 nic_interface_supported[0x3]; 8547 u8 reserved_at_fe8[0x18]; 8548 8549 struct mlx5_ifc_health_buffer_bits health_buffer; 8550 8551 u8 no_dram_nic_offset[0x20]; 8552 8553 u8 reserved_at_1220[0x6e40]; 8554 8555 u8 reserved_at_8060[0x1f]; 8556 u8 clear_int[0x1]; 8557 8558 u8 health_syndrome[0x8]; 8559 u8 health_counter[0x18]; 8560 8561 u8 reserved_at_80a0[0x17fc0]; 8562 }; 8563 8564 struct mlx5_ifc_mtpps_reg_bits { 8565 u8 reserved_at_0[0xc]; 8566 u8 cap_number_of_pps_pins[0x4]; 8567 u8 reserved_at_10[0x4]; 8568 u8 cap_max_num_of_pps_in_pins[0x4]; 8569 u8 reserved_at_18[0x4]; 8570 u8 cap_max_num_of_pps_out_pins[0x4]; 8571 8572 u8 reserved_at_20[0x24]; 8573 u8 cap_pin_3_mode[0x4]; 8574 u8 reserved_at_48[0x4]; 8575 u8 cap_pin_2_mode[0x4]; 8576 u8 reserved_at_50[0x4]; 8577 u8 cap_pin_1_mode[0x4]; 8578 u8 reserved_at_58[0x4]; 8579 u8 cap_pin_0_mode[0x4]; 8580 8581 u8 reserved_at_60[0x4]; 8582 u8 cap_pin_7_mode[0x4]; 8583 u8 reserved_at_68[0x4]; 8584 u8 cap_pin_6_mode[0x4]; 8585 u8 reserved_at_70[0x4]; 8586 u8 cap_pin_5_mode[0x4]; 8587 u8 reserved_at_78[0x4]; 8588 u8 cap_pin_4_mode[0x4]; 8589 8590 u8 field_select[0x20]; 8591 u8 reserved_at_a0[0x60]; 8592 8593 u8 enable[0x1]; 8594 u8 reserved_at_101[0xb]; 8595 u8 pattern[0x4]; 8596 u8 reserved_at_110[0x4]; 8597 u8 pin_mode[0x4]; 8598 u8 pin[0x8]; 8599 8600 u8 reserved_at_120[0x20]; 8601 8602 u8 time_stamp[0x40]; 8603 8604 u8 out_pulse_duration[0x10]; 8605 u8 out_periodic_adjustment[0x10]; 8606 u8 enhanced_out_periodic_adjustment[0x20]; 8607 8608 u8 reserved_at_1c0[0x20]; 8609 }; 8610 8611 struct mlx5_ifc_mtppse_reg_bits { 8612 u8 reserved_at_0[0x18]; 8613 u8 pin[0x8]; 8614 u8 event_arm[0x1]; 8615 u8 reserved_at_21[0x1b]; 8616 u8 event_generation_mode[0x4]; 8617 u8 reserved_at_40[0x40]; 8618 }; 8619 8620 struct mlx5_ifc_mcqi_cap_bits { 8621 u8 supported_info_bitmask[0x20]; 8622 8623 u8 component_size[0x20]; 8624 8625 u8 max_component_size[0x20]; 8626 8627 u8 log_mcda_word_size[0x4]; 8628 u8 reserved_at_64[0xc]; 8629 u8 mcda_max_write_size[0x10]; 8630 8631 u8 rd_en[0x1]; 8632 u8 reserved_at_81[0x1]; 8633 u8 match_chip_id[0x1]; 8634 u8 match_psid[0x1]; 8635 u8 check_user_timestamp[0x1]; 8636 u8 match_base_guid_mac[0x1]; 8637 u8 reserved_at_86[0x1a]; 8638 }; 8639 8640 struct mlx5_ifc_mcqi_reg_bits { 8641 u8 read_pending_component[0x1]; 8642 u8 reserved_at_1[0xf]; 8643 u8 component_index[0x10]; 8644 8645 u8 reserved_at_20[0x20]; 8646 8647 u8 reserved_at_40[0x1b]; 8648 u8 info_type[0x5]; 8649 8650 u8 info_size[0x20]; 8651 8652 u8 offset[0x20]; 8653 8654 u8 reserved_at_a0[0x10]; 8655 u8 data_size[0x10]; 8656 8657 u8 data[0][0x20]; 8658 }; 8659 8660 struct mlx5_ifc_mcc_reg_bits { 8661 u8 reserved_at_0[0x4]; 8662 u8 time_elapsed_since_last_cmd[0xc]; 8663 u8 reserved_at_10[0x8]; 8664 u8 instruction[0x8]; 8665 8666 u8 reserved_at_20[0x10]; 8667 u8 component_index[0x10]; 8668 8669 u8 reserved_at_40[0x8]; 8670 u8 update_handle[0x18]; 8671 8672 u8 handle_owner_type[0x4]; 8673 u8 handle_owner_host_id[0x4]; 8674 u8 reserved_at_68[0x1]; 8675 u8 control_progress[0x7]; 8676 u8 error_code[0x8]; 8677 u8 reserved_at_78[0x4]; 8678 u8 control_state[0x4]; 8679 8680 u8 component_size[0x20]; 8681 8682 u8 reserved_at_a0[0x60]; 8683 }; 8684 8685 struct mlx5_ifc_mcda_reg_bits { 8686 u8 reserved_at_0[0x8]; 8687 u8 update_handle[0x18]; 8688 8689 u8 offset[0x20]; 8690 8691 u8 reserved_at_40[0x10]; 8692 u8 size[0x10]; 8693 8694 u8 reserved_at_60[0x20]; 8695 8696 u8 data[0][0x20]; 8697 }; 8698 8699 union mlx5_ifc_ports_control_registers_document_bits { 8700 struct mlx5_ifc_bufferx_reg_bits bufferx_reg; 8701 struct mlx5_ifc_eth_2819_cntrs_grp_data_layout_bits eth_2819_cntrs_grp_data_layout; 8702 struct mlx5_ifc_eth_2863_cntrs_grp_data_layout_bits eth_2863_cntrs_grp_data_layout; 8703 struct mlx5_ifc_eth_3635_cntrs_grp_data_layout_bits eth_3635_cntrs_grp_data_layout; 8704 struct mlx5_ifc_eth_802_3_cntrs_grp_data_layout_bits eth_802_3_cntrs_grp_data_layout; 8705 struct mlx5_ifc_eth_extended_cntrs_grp_data_layout_bits eth_extended_cntrs_grp_data_layout; 8706 struct mlx5_ifc_eth_per_prio_grp_data_layout_bits eth_per_prio_grp_data_layout; 8707 struct mlx5_ifc_eth_per_traffic_grp_data_layout_bits eth_per_traffic_grp_data_layout; 8708 struct mlx5_ifc_lane_2_module_mapping_bits lane_2_module_mapping; 8709 struct mlx5_ifc_pamp_reg_bits pamp_reg; 8710 struct mlx5_ifc_paos_reg_bits paos_reg; 8711 struct mlx5_ifc_pcap_reg_bits pcap_reg; 8712 struct mlx5_ifc_peir_reg_bits peir_reg; 8713 struct mlx5_ifc_pelc_reg_bits pelc_reg; 8714 struct mlx5_ifc_pfcc_reg_bits pfcc_reg; 8715 struct mlx5_ifc_ib_port_cntrs_grp_data_layout_bits ib_port_cntrs_grp_data_layout; 8716 struct mlx5_ifc_phys_layer_cntrs_bits phys_layer_cntrs; 8717 struct mlx5_ifc_pifr_reg_bits pifr_reg; 8718 struct mlx5_ifc_pipg_reg_bits pipg_reg; 8719 struct mlx5_ifc_plbf_reg_bits plbf_reg; 8720 struct mlx5_ifc_plib_reg_bits plib_reg; 8721 struct mlx5_ifc_plpc_reg_bits plpc_reg; 8722 struct mlx5_ifc_pmaos_reg_bits pmaos_reg; 8723 struct mlx5_ifc_pmlp_reg_bits pmlp_reg; 8724 struct mlx5_ifc_pmlpn_reg_bits pmlpn_reg; 8725 struct mlx5_ifc_pmpc_reg_bits pmpc_reg; 8726 struct mlx5_ifc_pmpe_reg_bits pmpe_reg; 8727 struct mlx5_ifc_pmpr_reg_bits pmpr_reg; 8728 struct mlx5_ifc_pmtu_reg_bits pmtu_reg; 8729 struct mlx5_ifc_ppad_reg_bits ppad_reg; 8730 struct mlx5_ifc_ppcnt_reg_bits ppcnt_reg; 8731 struct mlx5_ifc_mpcnt_reg_bits mpcnt_reg; 8732 struct mlx5_ifc_pplm_reg_bits pplm_reg; 8733 struct mlx5_ifc_pplr_reg_bits pplr_reg; 8734 struct mlx5_ifc_ppsc_reg_bits ppsc_reg; 8735 struct mlx5_ifc_pqdr_reg_bits pqdr_reg; 8736 struct mlx5_ifc_pspa_reg_bits pspa_reg; 8737 struct mlx5_ifc_ptas_reg_bits ptas_reg; 8738 struct mlx5_ifc_ptys_reg_bits ptys_reg; 8739 struct mlx5_ifc_mlcr_reg_bits mlcr_reg; 8740 struct mlx5_ifc_pude_reg_bits pude_reg; 8741 struct mlx5_ifc_pvlc_reg_bits pvlc_reg; 8742 struct mlx5_ifc_slrg_reg_bits slrg_reg; 8743 struct mlx5_ifc_sltp_reg_bits sltp_reg; 8744 struct mlx5_ifc_mtpps_reg_bits mtpps_reg; 8745 struct mlx5_ifc_mtppse_reg_bits mtppse_reg; 8746 struct mlx5_ifc_fpga_access_reg_bits fpga_access_reg; 8747 struct mlx5_ifc_fpga_ctrl_bits fpga_ctrl_bits; 8748 struct mlx5_ifc_fpga_cap_bits fpga_cap_bits; 8749 struct mlx5_ifc_mcqi_reg_bits mcqi_reg; 8750 struct mlx5_ifc_mcc_reg_bits mcc_reg; 8751 struct mlx5_ifc_mcda_reg_bits mcda_reg; 8752 u8 reserved_at_0[0x60e0]; 8753 }; 8754 8755 union mlx5_ifc_debug_enhancements_document_bits { 8756 struct mlx5_ifc_health_buffer_bits health_buffer; 8757 u8 reserved_at_0[0x200]; 8758 }; 8759 8760 union mlx5_ifc_uplink_pci_interface_document_bits { 8761 struct mlx5_ifc_initial_seg_bits initial_seg; 8762 u8 reserved_at_0[0x20060]; 8763 }; 8764 8765 struct mlx5_ifc_set_flow_table_root_out_bits { 8766 u8 status[0x8]; 8767 u8 reserved_at_8[0x18]; 8768 8769 u8 syndrome[0x20]; 8770 8771 u8 reserved_at_40[0x40]; 8772 }; 8773 8774 struct mlx5_ifc_set_flow_table_root_in_bits { 8775 u8 opcode[0x10]; 8776 u8 reserved_at_10[0x10]; 8777 8778 u8 reserved_at_20[0x10]; 8779 u8 op_mod[0x10]; 8780 8781 u8 other_vport[0x1]; 8782 u8 reserved_at_41[0xf]; 8783 u8 vport_number[0x10]; 8784 8785 u8 reserved_at_60[0x20]; 8786 8787 u8 table_type[0x8]; 8788 u8 reserved_at_88[0x18]; 8789 8790 u8 reserved_at_a0[0x8]; 8791 u8 table_id[0x18]; 8792 8793 u8 reserved_at_c0[0x8]; 8794 u8 underlay_qpn[0x18]; 8795 u8 reserved_at_e0[0x120]; 8796 }; 8797 8798 enum { 8799 MLX5_MODIFY_FLOW_TABLE_MISS_TABLE_ID = (1UL << 0), 8800 MLX5_MODIFY_FLOW_TABLE_LAG_NEXT_TABLE_ID = (1UL << 15), 8801 }; 8802 8803 struct mlx5_ifc_modify_flow_table_out_bits { 8804 u8 status[0x8]; 8805 u8 reserved_at_8[0x18]; 8806 8807 u8 syndrome[0x20]; 8808 8809 u8 reserved_at_40[0x40]; 8810 }; 8811 8812 struct mlx5_ifc_modify_flow_table_in_bits { 8813 u8 opcode[0x10]; 8814 u8 reserved_at_10[0x10]; 8815 8816 u8 reserved_at_20[0x10]; 8817 u8 op_mod[0x10]; 8818 8819 u8 other_vport[0x1]; 8820 u8 reserved_at_41[0xf]; 8821 u8 vport_number[0x10]; 8822 8823 u8 reserved_at_60[0x10]; 8824 u8 modify_field_select[0x10]; 8825 8826 u8 table_type[0x8]; 8827 u8 reserved_at_88[0x18]; 8828 8829 u8 reserved_at_a0[0x8]; 8830 u8 table_id[0x18]; 8831 8832 struct mlx5_ifc_flow_table_context_bits flow_table_context; 8833 }; 8834 8835 struct mlx5_ifc_ets_tcn_config_reg_bits { 8836 u8 g[0x1]; 8837 u8 b[0x1]; 8838 u8 r[0x1]; 8839 u8 reserved_at_3[0x9]; 8840 u8 group[0x4]; 8841 u8 reserved_at_10[0x9]; 8842 u8 bw_allocation[0x7]; 8843 8844 u8 reserved_at_20[0xc]; 8845 u8 max_bw_units[0x4]; 8846 u8 reserved_at_30[0x8]; 8847 u8 max_bw_value[0x8]; 8848 }; 8849 8850 struct mlx5_ifc_ets_global_config_reg_bits { 8851 u8 reserved_at_0[0x2]; 8852 u8 r[0x1]; 8853 u8 reserved_at_3[0x1d]; 8854 8855 u8 reserved_at_20[0xc]; 8856 u8 max_bw_units[0x4]; 8857 u8 reserved_at_30[0x8]; 8858 u8 max_bw_value[0x8]; 8859 }; 8860 8861 struct mlx5_ifc_qetc_reg_bits { 8862 u8 reserved_at_0[0x8]; 8863 u8 port_number[0x8]; 8864 u8 reserved_at_10[0x30]; 8865 8866 struct mlx5_ifc_ets_tcn_config_reg_bits tc_configuration[0x8]; 8867 struct mlx5_ifc_ets_global_config_reg_bits global_configuration; 8868 }; 8869 8870 struct mlx5_ifc_qpdpm_dscp_reg_bits { 8871 u8 e[0x1]; 8872 u8 reserved_at_01[0x0b]; 8873 u8 prio[0x04]; 8874 }; 8875 8876 struct mlx5_ifc_qpdpm_reg_bits { 8877 u8 reserved_at_0[0x8]; 8878 u8 local_port[0x8]; 8879 u8 reserved_at_10[0x10]; 8880 struct mlx5_ifc_qpdpm_dscp_reg_bits dscp[64]; 8881 }; 8882 8883 struct mlx5_ifc_qpts_reg_bits { 8884 u8 reserved_at_0[0x8]; 8885 u8 local_port[0x8]; 8886 u8 reserved_at_10[0x2d]; 8887 u8 trust_state[0x3]; 8888 }; 8889 8890 struct mlx5_ifc_pptb_reg_bits { 8891 u8 reserved_at_0[0x2]; 8892 u8 mm[0x2]; 8893 u8 reserved_at_4[0x4]; 8894 u8 local_port[0x8]; 8895 u8 reserved_at_10[0x6]; 8896 u8 cm[0x1]; 8897 u8 um[0x1]; 8898 u8 pm[0x8]; 8899 8900 u8 prio_x_buff[0x20]; 8901 8902 u8 pm_msb[0x8]; 8903 u8 reserved_at_48[0x10]; 8904 u8 ctrl_buff[0x4]; 8905 u8 untagged_buff[0x4]; 8906 }; 8907 8908 struct mlx5_ifc_pbmc_reg_bits { 8909 u8 reserved_at_0[0x8]; 8910 u8 local_port[0x8]; 8911 u8 reserved_at_10[0x10]; 8912 8913 u8 xoff_timer_value[0x10]; 8914 u8 xoff_refresh[0x10]; 8915 8916 u8 reserved_at_40[0x9]; 8917 u8 fullness_threshold[0x7]; 8918 u8 port_buffer_size[0x10]; 8919 8920 struct mlx5_ifc_bufferx_reg_bits buffer[10]; 8921 8922 u8 reserved_at_2e0[0x40]; 8923 }; 8924 8925 struct mlx5_ifc_qtct_reg_bits { 8926 u8 reserved_at_0[0x8]; 8927 u8 port_number[0x8]; 8928 u8 reserved_at_10[0xd]; 8929 u8 prio[0x3]; 8930 8931 u8 reserved_at_20[0x1d]; 8932 u8 tclass[0x3]; 8933 }; 8934 8935 struct mlx5_ifc_mcia_reg_bits { 8936 u8 l[0x1]; 8937 u8 reserved_at_1[0x7]; 8938 u8 module[0x8]; 8939 u8 reserved_at_10[0x8]; 8940 u8 status[0x8]; 8941 8942 u8 i2c_device_address[0x8]; 8943 u8 page_number[0x8]; 8944 u8 device_address[0x10]; 8945 8946 u8 reserved_at_40[0x10]; 8947 u8 size[0x10]; 8948 8949 u8 reserved_at_60[0x20]; 8950 8951 u8 dword_0[0x20]; 8952 u8 dword_1[0x20]; 8953 u8 dword_2[0x20]; 8954 u8 dword_3[0x20]; 8955 u8 dword_4[0x20]; 8956 u8 dword_5[0x20]; 8957 u8 dword_6[0x20]; 8958 u8 dword_7[0x20]; 8959 u8 dword_8[0x20]; 8960 u8 dword_9[0x20]; 8961 u8 dword_10[0x20]; 8962 u8 dword_11[0x20]; 8963 }; 8964 8965 struct mlx5_ifc_dcbx_param_bits { 8966 u8 dcbx_cee_cap[0x1]; 8967 u8 dcbx_ieee_cap[0x1]; 8968 u8 dcbx_standby_cap[0x1]; 8969 u8 reserved_at_0[0x5]; 8970 u8 port_number[0x8]; 8971 u8 reserved_at_10[0xa]; 8972 u8 max_application_table_size[6]; 8973 u8 reserved_at_20[0x15]; 8974 u8 version_oper[0x3]; 8975 u8 reserved_at_38[5]; 8976 u8 version_admin[0x3]; 8977 u8 willing_admin[0x1]; 8978 u8 reserved_at_41[0x3]; 8979 u8 pfc_cap_oper[0x4]; 8980 u8 reserved_at_48[0x4]; 8981 u8 pfc_cap_admin[0x4]; 8982 u8 reserved_at_50[0x4]; 8983 u8 num_of_tc_oper[0x4]; 8984 u8 reserved_at_58[0x4]; 8985 u8 num_of_tc_admin[0x4]; 8986 u8 remote_willing[0x1]; 8987 u8 reserved_at_61[3]; 8988 u8 remote_pfc_cap[4]; 8989 u8 reserved_at_68[0x14]; 8990 u8 remote_num_of_tc[0x4]; 8991 u8 reserved_at_80[0x18]; 8992 u8 error[0x8]; 8993 u8 reserved_at_a0[0x160]; 8994 }; 8995 8996 struct mlx5_ifc_lagc_bits { 8997 u8 reserved_at_0[0x1d]; 8998 u8 lag_state[0x3]; 8999 9000 u8 reserved_at_20[0x14]; 9001 u8 tx_remap_affinity_2[0x4]; 9002 u8 reserved_at_38[0x4]; 9003 u8 tx_remap_affinity_1[0x4]; 9004 }; 9005 9006 struct mlx5_ifc_create_lag_out_bits { 9007 u8 status[0x8]; 9008 u8 reserved_at_8[0x18]; 9009 9010 u8 syndrome[0x20]; 9011 9012 u8 reserved_at_40[0x40]; 9013 }; 9014 9015 struct mlx5_ifc_create_lag_in_bits { 9016 u8 opcode[0x10]; 9017 u8 reserved_at_10[0x10]; 9018 9019 u8 reserved_at_20[0x10]; 9020 u8 op_mod[0x10]; 9021 9022 struct mlx5_ifc_lagc_bits ctx; 9023 }; 9024 9025 struct mlx5_ifc_modify_lag_out_bits { 9026 u8 status[0x8]; 9027 u8 reserved_at_8[0x18]; 9028 9029 u8 syndrome[0x20]; 9030 9031 u8 reserved_at_40[0x40]; 9032 }; 9033 9034 struct mlx5_ifc_modify_lag_in_bits { 9035 u8 opcode[0x10]; 9036 u8 reserved_at_10[0x10]; 9037 9038 u8 reserved_at_20[0x10]; 9039 u8 op_mod[0x10]; 9040 9041 u8 reserved_at_40[0x20]; 9042 u8 field_select[0x20]; 9043 9044 struct mlx5_ifc_lagc_bits ctx; 9045 }; 9046 9047 struct mlx5_ifc_query_lag_out_bits { 9048 u8 status[0x8]; 9049 u8 reserved_at_8[0x18]; 9050 9051 u8 syndrome[0x20]; 9052 9053 u8 reserved_at_40[0x40]; 9054 9055 struct mlx5_ifc_lagc_bits ctx; 9056 }; 9057 9058 struct mlx5_ifc_query_lag_in_bits { 9059 u8 opcode[0x10]; 9060 u8 reserved_at_10[0x10]; 9061 9062 u8 reserved_at_20[0x10]; 9063 u8 op_mod[0x10]; 9064 9065 u8 reserved_at_40[0x40]; 9066 }; 9067 9068 struct mlx5_ifc_destroy_lag_out_bits { 9069 u8 status[0x8]; 9070 u8 reserved_at_8[0x18]; 9071 9072 u8 syndrome[0x20]; 9073 9074 u8 reserved_at_40[0x40]; 9075 }; 9076 9077 struct mlx5_ifc_destroy_lag_in_bits { 9078 u8 opcode[0x10]; 9079 u8 reserved_at_10[0x10]; 9080 9081 u8 reserved_at_20[0x10]; 9082 u8 op_mod[0x10]; 9083 9084 u8 reserved_at_40[0x40]; 9085 }; 9086 9087 struct mlx5_ifc_create_vport_lag_out_bits { 9088 u8 status[0x8]; 9089 u8 reserved_at_8[0x18]; 9090 9091 u8 syndrome[0x20]; 9092 9093 u8 reserved_at_40[0x40]; 9094 }; 9095 9096 struct mlx5_ifc_create_vport_lag_in_bits { 9097 u8 opcode[0x10]; 9098 u8 reserved_at_10[0x10]; 9099 9100 u8 reserved_at_20[0x10]; 9101 u8 op_mod[0x10]; 9102 9103 u8 reserved_at_40[0x40]; 9104 }; 9105 9106 struct mlx5_ifc_destroy_vport_lag_out_bits { 9107 u8 status[0x8]; 9108 u8 reserved_at_8[0x18]; 9109 9110 u8 syndrome[0x20]; 9111 9112 u8 reserved_at_40[0x40]; 9113 }; 9114 9115 struct mlx5_ifc_destroy_vport_lag_in_bits { 9116 u8 opcode[0x10]; 9117 u8 reserved_at_10[0x10]; 9118 9119 u8 reserved_at_20[0x10]; 9120 u8 op_mod[0x10]; 9121 9122 u8 reserved_at_40[0x40]; 9123 }; 9124 9125 struct mlx5_ifc_alloc_memic_in_bits { 9126 u8 opcode[0x10]; 9127 u8 reserved_at_10[0x10]; 9128 9129 u8 reserved_at_20[0x10]; 9130 u8 op_mod[0x10]; 9131 9132 u8 reserved_at_30[0x20]; 9133 9134 u8 reserved_at_40[0x18]; 9135 u8 log_memic_addr_alignment[0x8]; 9136 9137 u8 range_start_addr[0x40]; 9138 9139 u8 range_size[0x20]; 9140 9141 u8 memic_size[0x20]; 9142 }; 9143 9144 struct mlx5_ifc_alloc_memic_out_bits { 9145 u8 status[0x8]; 9146 u8 reserved_at_8[0x18]; 9147 9148 u8 syndrome[0x20]; 9149 9150 u8 memic_start_addr[0x40]; 9151 }; 9152 9153 struct mlx5_ifc_dealloc_memic_in_bits { 9154 u8 opcode[0x10]; 9155 u8 reserved_at_10[0x10]; 9156 9157 u8 reserved_at_20[0x10]; 9158 u8 op_mod[0x10]; 9159 9160 u8 reserved_at_40[0x40]; 9161 9162 u8 memic_start_addr[0x40]; 9163 9164 u8 memic_size[0x20]; 9165 9166 u8 reserved_at_e0[0x20]; 9167 }; 9168 9169 struct mlx5_ifc_dealloc_memic_out_bits { 9170 u8 status[0x8]; 9171 u8 reserved_at_8[0x18]; 9172 9173 u8 syndrome[0x20]; 9174 9175 u8 reserved_at_40[0x40]; 9176 }; 9177 9178 struct mlx5_ifc_general_obj_in_cmd_hdr_bits { 9179 u8 opcode[0x10]; 9180 u8 uid[0x10]; 9181 9182 u8 reserved_at_20[0x10]; 9183 u8 obj_type[0x10]; 9184 9185 u8 obj_id[0x20]; 9186 9187 u8 reserved_at_60[0x20]; 9188 }; 9189 9190 struct mlx5_ifc_general_obj_out_cmd_hdr_bits { 9191 u8 status[0x8]; 9192 u8 reserved_at_8[0x18]; 9193 9194 u8 syndrome[0x20]; 9195 9196 u8 obj_id[0x20]; 9197 9198 u8 reserved_at_60[0x20]; 9199 }; 9200 9201 struct mlx5_ifc_umem_bits { 9202 u8 modify_field_select[0x40]; 9203 9204 u8 reserved_at_40[0x5b]; 9205 u8 log_page_size[0x5]; 9206 9207 u8 page_offset[0x20]; 9208 9209 u8 num_of_mtt[0x40]; 9210 9211 struct mlx5_ifc_mtt_bits mtt[0]; 9212 }; 9213 9214 struct mlx5_ifc_uctx_bits { 9215 u8 modify_field_select[0x40]; 9216 9217 u8 reserved_at_40[0x1c0]; 9218 }; 9219 9220 struct mlx5_ifc_create_umem_in_bits { 9221 struct mlx5_ifc_general_obj_in_cmd_hdr_bits hdr; 9222 struct mlx5_ifc_umem_bits umem; 9223 }; 9224 9225 struct mlx5_ifc_create_uctx_in_bits { 9226 struct mlx5_ifc_general_obj_in_cmd_hdr_bits hdr; 9227 struct mlx5_ifc_uctx_bits uctx; 9228 }; 9229 9230 struct mlx5_ifc_mtrc_string_db_param_bits { 9231 u8 string_db_base_address[0x20]; 9232 9233 u8 reserved_at_20[0x8]; 9234 u8 string_db_size[0x18]; 9235 }; 9236 9237 struct mlx5_ifc_mtrc_cap_bits { 9238 u8 trace_owner[0x1]; 9239 u8 trace_to_memory[0x1]; 9240 u8 reserved_at_2[0x4]; 9241 u8 trc_ver[0x2]; 9242 u8 reserved_at_8[0x14]; 9243 u8 num_string_db[0x4]; 9244 9245 u8 first_string_trace[0x8]; 9246 u8 num_string_trace[0x8]; 9247 u8 reserved_at_30[0x28]; 9248 9249 u8 log_max_trace_buffer_size[0x8]; 9250 9251 u8 reserved_at_60[0x20]; 9252 9253 struct mlx5_ifc_mtrc_string_db_param_bits string_db_param[8]; 9254 9255 u8 reserved_at_280[0x180]; 9256 }; 9257 9258 struct mlx5_ifc_mtrc_conf_bits { 9259 u8 reserved_at_0[0x1c]; 9260 u8 trace_mode[0x4]; 9261 u8 reserved_at_20[0x18]; 9262 u8 log_trace_buffer_size[0x8]; 9263 u8 trace_mkey[0x20]; 9264 u8 reserved_at_60[0x3a0]; 9265 }; 9266 9267 struct mlx5_ifc_mtrc_stdb_bits { 9268 u8 string_db_index[0x4]; 9269 u8 reserved_at_4[0x4]; 9270 u8 read_size[0x18]; 9271 u8 start_offset[0x20]; 9272 u8 string_db_data[0]; 9273 }; 9274 9275 struct mlx5_ifc_mtrc_ctrl_bits { 9276 u8 trace_status[0x2]; 9277 u8 reserved_at_2[0x2]; 9278 u8 arm_event[0x1]; 9279 u8 reserved_at_5[0xb]; 9280 u8 modify_field_select[0x10]; 9281 u8 reserved_at_20[0x2b]; 9282 u8 current_timestamp52_32[0x15]; 9283 u8 current_timestamp31_0[0x20]; 9284 u8 reserved_at_80[0x180]; 9285 }; 9286 9287 #endif /* MLX5_IFC_H */ 9288