1 /* 2 * Copyright (c) 2013-2015, Mellanox Technologies, Ltd. All rights reserved. 3 * 4 * This software is available to you under a choice of one of two 5 * licenses. You may choose to be licensed under the terms of the GNU 6 * General Public License (GPL) Version 2, available from the file 7 * COPYING in the main directory of this source tree, or the 8 * OpenIB.org BSD license below: 9 * 10 * Redistribution and use in source and binary forms, with or 11 * without modification, are permitted provided that the following 12 * conditions are met: 13 * 14 * - Redistributions of source code must retain the above 15 * copyright notice, this list of conditions and the following 16 * disclaimer. 17 * 18 * - Redistributions in binary form must reproduce the above 19 * copyright notice, this list of conditions and the following 20 * disclaimer in the documentation and/or other materials 21 * provided with the distribution. 22 * 23 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, 24 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF 25 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND 26 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS 27 * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN 28 * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN 29 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE 30 * SOFTWARE. 31 */ 32 #ifndef MLX5_IFC_H 33 #define MLX5_IFC_H 34 35 #include "mlx5_ifc_fpga.h" 36 37 enum { 38 MLX5_EVENT_TYPE_CODING_COMPLETION_EVENTS = 0x0, 39 MLX5_EVENT_TYPE_CODING_PATH_MIGRATED_SUCCEEDED = 0x1, 40 MLX5_EVENT_TYPE_CODING_COMMUNICATION_ESTABLISHED = 0x2, 41 MLX5_EVENT_TYPE_CODING_SEND_QUEUE_DRAINED = 0x3, 42 MLX5_EVENT_TYPE_CODING_LAST_WQE_REACHED = 0x13, 43 MLX5_EVENT_TYPE_CODING_SRQ_LIMIT = 0x14, 44 MLX5_EVENT_TYPE_CODING_DCT_ALL_CONNECTIONS_CLOSED = 0x1c, 45 MLX5_EVENT_TYPE_CODING_DCT_ACCESS_KEY_VIOLATION = 0x1d, 46 MLX5_EVENT_TYPE_CODING_CQ_ERROR = 0x4, 47 MLX5_EVENT_TYPE_CODING_LOCAL_WQ_CATASTROPHIC_ERROR = 0x5, 48 MLX5_EVENT_TYPE_CODING_PATH_MIGRATION_FAILED = 0x7, 49 MLX5_EVENT_TYPE_CODING_PAGE_FAULT_EVENT = 0xc, 50 MLX5_EVENT_TYPE_CODING_INVALID_REQUEST_LOCAL_WQ_ERROR = 0x10, 51 MLX5_EVENT_TYPE_CODING_LOCAL_ACCESS_VIOLATION_WQ_ERROR = 0x11, 52 MLX5_EVENT_TYPE_CODING_LOCAL_SRQ_CATASTROPHIC_ERROR = 0x12, 53 MLX5_EVENT_TYPE_CODING_INTERNAL_ERROR = 0x8, 54 MLX5_EVENT_TYPE_CODING_PORT_STATE_CHANGE = 0x9, 55 MLX5_EVENT_TYPE_CODING_GPIO_EVENT = 0x15, 56 MLX5_EVENT_TYPE_CODING_REMOTE_CONFIGURATION_PROTOCOL_EVENT = 0x19, 57 MLX5_EVENT_TYPE_CODING_DOORBELL_BLUEFLAME_CONGESTION_EVENT = 0x1a, 58 MLX5_EVENT_TYPE_CODING_STALL_VL_EVENT = 0x1b, 59 MLX5_EVENT_TYPE_CODING_DROPPED_PACKET_LOGGED_EVENT = 0x1f, 60 MLX5_EVENT_TYPE_CODING_COMMAND_INTERFACE_COMPLETION = 0xa, 61 MLX5_EVENT_TYPE_CODING_PAGE_REQUEST = 0xb, 62 MLX5_EVENT_TYPE_CODING_FPGA_ERROR = 0x20, 63 MLX5_EVENT_TYPE_CODING_FPGA_QP_ERROR = 0x21 64 }; 65 66 enum { 67 MLX5_SET_HCA_CAP_OP_MOD_GENERAL_DEVICE = 0x0, 68 MLX5_SET_HCA_CAP_OP_MOD_ETHERNET_OFFLOADS = 0x1, 69 MLX5_SET_HCA_CAP_OP_MOD_ODP = 0x2, 70 MLX5_SET_HCA_CAP_OP_MOD_ATOMIC = 0x3, 71 MLX5_SET_HCA_CAP_OP_MOD_ROCE = 0x4, 72 MLX5_SET_HCA_CAP_OP_MOD_IPSEC = 0x15, 73 MLX5_SET_HCA_CAP_OP_MOD_GENERAL_DEVICE2 = 0x20, 74 MLX5_SET_HCA_CAP_OP_MOD_PORT_SELECTION = 0x25, 75 }; 76 77 enum { 78 MLX5_SHARED_RESOURCE_UID = 0xffff, 79 }; 80 81 enum { 82 MLX5_OBJ_TYPE_SW_ICM = 0x0008, 83 MLX5_OBJ_TYPE_HEADER_MODIFY_ARGUMENT = 0x23, 84 }; 85 86 enum { 87 MLX5_GENERAL_OBJ_TYPES_CAP_SW_ICM = (1ULL << MLX5_OBJ_TYPE_SW_ICM), 88 MLX5_GENERAL_OBJ_TYPES_CAP_GENEVE_TLV_OPT = (1ULL << 11), 89 MLX5_GENERAL_OBJ_TYPES_CAP_VIRTIO_NET_Q = (1ULL << 13), 90 MLX5_GENERAL_OBJ_TYPES_CAP_HEADER_MODIFY_ARGUMENT = 91 (1ULL << MLX5_OBJ_TYPE_HEADER_MODIFY_ARGUMENT), 92 MLX5_GENERAL_OBJ_TYPES_CAP_MACSEC_OFFLOAD = (1ULL << 39), 93 }; 94 95 enum { 96 MLX5_OBJ_TYPE_GENEVE_TLV_OPT = 0x000b, 97 MLX5_OBJ_TYPE_VIRTIO_NET_Q = 0x000d, 98 MLX5_OBJ_TYPE_VIRTIO_Q_COUNTERS = 0x001c, 99 MLX5_OBJ_TYPE_MATCH_DEFINER = 0x0018, 100 MLX5_OBJ_TYPE_PAGE_TRACK = 0x46, 101 MLX5_OBJ_TYPE_MKEY = 0xff01, 102 MLX5_OBJ_TYPE_QP = 0xff02, 103 MLX5_OBJ_TYPE_PSV = 0xff03, 104 MLX5_OBJ_TYPE_RMP = 0xff04, 105 MLX5_OBJ_TYPE_XRC_SRQ = 0xff05, 106 MLX5_OBJ_TYPE_RQ = 0xff06, 107 MLX5_OBJ_TYPE_SQ = 0xff07, 108 MLX5_OBJ_TYPE_TIR = 0xff08, 109 MLX5_OBJ_TYPE_TIS = 0xff09, 110 MLX5_OBJ_TYPE_DCT = 0xff0a, 111 MLX5_OBJ_TYPE_XRQ = 0xff0b, 112 MLX5_OBJ_TYPE_RQT = 0xff0e, 113 MLX5_OBJ_TYPE_FLOW_COUNTER = 0xff0f, 114 MLX5_OBJ_TYPE_CQ = 0xff10, 115 }; 116 117 enum { 118 MLX5_CMD_OP_QUERY_HCA_CAP = 0x100, 119 MLX5_CMD_OP_QUERY_ADAPTER = 0x101, 120 MLX5_CMD_OP_INIT_HCA = 0x102, 121 MLX5_CMD_OP_TEARDOWN_HCA = 0x103, 122 MLX5_CMD_OP_ENABLE_HCA = 0x104, 123 MLX5_CMD_OP_DISABLE_HCA = 0x105, 124 MLX5_CMD_OP_QUERY_PAGES = 0x107, 125 MLX5_CMD_OP_MANAGE_PAGES = 0x108, 126 MLX5_CMD_OP_SET_HCA_CAP = 0x109, 127 MLX5_CMD_OP_QUERY_ISSI = 0x10a, 128 MLX5_CMD_OP_SET_ISSI = 0x10b, 129 MLX5_CMD_OP_SET_DRIVER_VERSION = 0x10d, 130 MLX5_CMD_OP_QUERY_SF_PARTITION = 0x111, 131 MLX5_CMD_OP_ALLOC_SF = 0x113, 132 MLX5_CMD_OP_DEALLOC_SF = 0x114, 133 MLX5_CMD_OP_SUSPEND_VHCA = 0x115, 134 MLX5_CMD_OP_RESUME_VHCA = 0x116, 135 MLX5_CMD_OP_QUERY_VHCA_MIGRATION_STATE = 0x117, 136 MLX5_CMD_OP_SAVE_VHCA_STATE = 0x118, 137 MLX5_CMD_OP_LOAD_VHCA_STATE = 0x119, 138 MLX5_CMD_OP_CREATE_MKEY = 0x200, 139 MLX5_CMD_OP_QUERY_MKEY = 0x201, 140 MLX5_CMD_OP_DESTROY_MKEY = 0x202, 141 MLX5_CMD_OP_QUERY_SPECIAL_CONTEXTS = 0x203, 142 MLX5_CMD_OP_PAGE_FAULT_RESUME = 0x204, 143 MLX5_CMD_OP_ALLOC_MEMIC = 0x205, 144 MLX5_CMD_OP_DEALLOC_MEMIC = 0x206, 145 MLX5_CMD_OP_MODIFY_MEMIC = 0x207, 146 MLX5_CMD_OP_CREATE_EQ = 0x301, 147 MLX5_CMD_OP_DESTROY_EQ = 0x302, 148 MLX5_CMD_OP_QUERY_EQ = 0x303, 149 MLX5_CMD_OP_GEN_EQE = 0x304, 150 MLX5_CMD_OP_CREATE_CQ = 0x400, 151 MLX5_CMD_OP_DESTROY_CQ = 0x401, 152 MLX5_CMD_OP_QUERY_CQ = 0x402, 153 MLX5_CMD_OP_MODIFY_CQ = 0x403, 154 MLX5_CMD_OP_CREATE_QP = 0x500, 155 MLX5_CMD_OP_DESTROY_QP = 0x501, 156 MLX5_CMD_OP_RST2INIT_QP = 0x502, 157 MLX5_CMD_OP_INIT2RTR_QP = 0x503, 158 MLX5_CMD_OP_RTR2RTS_QP = 0x504, 159 MLX5_CMD_OP_RTS2RTS_QP = 0x505, 160 MLX5_CMD_OP_SQERR2RTS_QP = 0x506, 161 MLX5_CMD_OP_2ERR_QP = 0x507, 162 MLX5_CMD_OP_2RST_QP = 0x50a, 163 MLX5_CMD_OP_QUERY_QP = 0x50b, 164 MLX5_CMD_OP_SQD_RTS_QP = 0x50c, 165 MLX5_CMD_OP_INIT2INIT_QP = 0x50e, 166 MLX5_CMD_OP_CREATE_PSV = 0x600, 167 MLX5_CMD_OP_DESTROY_PSV = 0x601, 168 MLX5_CMD_OP_CREATE_SRQ = 0x700, 169 MLX5_CMD_OP_DESTROY_SRQ = 0x701, 170 MLX5_CMD_OP_QUERY_SRQ = 0x702, 171 MLX5_CMD_OP_ARM_RQ = 0x703, 172 MLX5_CMD_OP_CREATE_XRC_SRQ = 0x705, 173 MLX5_CMD_OP_DESTROY_XRC_SRQ = 0x706, 174 MLX5_CMD_OP_QUERY_XRC_SRQ = 0x707, 175 MLX5_CMD_OP_ARM_XRC_SRQ = 0x708, 176 MLX5_CMD_OP_CREATE_DCT = 0x710, 177 MLX5_CMD_OP_DESTROY_DCT = 0x711, 178 MLX5_CMD_OP_DRAIN_DCT = 0x712, 179 MLX5_CMD_OP_QUERY_DCT = 0x713, 180 MLX5_CMD_OP_ARM_DCT_FOR_KEY_VIOLATION = 0x714, 181 MLX5_CMD_OP_CREATE_XRQ = 0x717, 182 MLX5_CMD_OP_DESTROY_XRQ = 0x718, 183 MLX5_CMD_OP_QUERY_XRQ = 0x719, 184 MLX5_CMD_OP_ARM_XRQ = 0x71a, 185 MLX5_CMD_OP_QUERY_XRQ_DC_PARAMS_ENTRY = 0x725, 186 MLX5_CMD_OP_SET_XRQ_DC_PARAMS_ENTRY = 0x726, 187 MLX5_CMD_OP_QUERY_XRQ_ERROR_PARAMS = 0x727, 188 MLX5_CMD_OP_RELEASE_XRQ_ERROR = 0x729, 189 MLX5_CMD_OP_MODIFY_XRQ = 0x72a, 190 MLX5_CMD_OP_QUERY_ESW_FUNCTIONS = 0x740, 191 MLX5_CMD_OP_QUERY_VPORT_STATE = 0x750, 192 MLX5_CMD_OP_MODIFY_VPORT_STATE = 0x751, 193 MLX5_CMD_OP_QUERY_ESW_VPORT_CONTEXT = 0x752, 194 MLX5_CMD_OP_MODIFY_ESW_VPORT_CONTEXT = 0x753, 195 MLX5_CMD_OP_QUERY_NIC_VPORT_CONTEXT = 0x754, 196 MLX5_CMD_OP_MODIFY_NIC_VPORT_CONTEXT = 0x755, 197 MLX5_CMD_OP_QUERY_ROCE_ADDRESS = 0x760, 198 MLX5_CMD_OP_SET_ROCE_ADDRESS = 0x761, 199 MLX5_CMD_OP_QUERY_HCA_VPORT_CONTEXT = 0x762, 200 MLX5_CMD_OP_MODIFY_HCA_VPORT_CONTEXT = 0x763, 201 MLX5_CMD_OP_QUERY_HCA_VPORT_GID = 0x764, 202 MLX5_CMD_OP_QUERY_HCA_VPORT_PKEY = 0x765, 203 MLX5_CMD_OP_QUERY_VNIC_ENV = 0x76f, 204 MLX5_CMD_OP_QUERY_VPORT_COUNTER = 0x770, 205 MLX5_CMD_OP_ALLOC_Q_COUNTER = 0x771, 206 MLX5_CMD_OP_DEALLOC_Q_COUNTER = 0x772, 207 MLX5_CMD_OP_QUERY_Q_COUNTER = 0x773, 208 MLX5_CMD_OP_SET_MONITOR_COUNTER = 0x774, 209 MLX5_CMD_OP_ARM_MONITOR_COUNTER = 0x775, 210 MLX5_CMD_OP_SET_PP_RATE_LIMIT = 0x780, 211 MLX5_CMD_OP_QUERY_RATE_LIMIT = 0x781, 212 MLX5_CMD_OP_CREATE_SCHEDULING_ELEMENT = 0x782, 213 MLX5_CMD_OP_DESTROY_SCHEDULING_ELEMENT = 0x783, 214 MLX5_CMD_OP_QUERY_SCHEDULING_ELEMENT = 0x784, 215 MLX5_CMD_OP_MODIFY_SCHEDULING_ELEMENT = 0x785, 216 MLX5_CMD_OP_CREATE_QOS_PARA_VPORT = 0x786, 217 MLX5_CMD_OP_DESTROY_QOS_PARA_VPORT = 0x787, 218 MLX5_CMD_OP_ALLOC_PD = 0x800, 219 MLX5_CMD_OP_DEALLOC_PD = 0x801, 220 MLX5_CMD_OP_ALLOC_UAR = 0x802, 221 MLX5_CMD_OP_DEALLOC_UAR = 0x803, 222 MLX5_CMD_OP_CONFIG_INT_MODERATION = 0x804, 223 MLX5_CMD_OP_ACCESS_REG = 0x805, 224 MLX5_CMD_OP_ATTACH_TO_MCG = 0x806, 225 MLX5_CMD_OP_DETACH_FROM_MCG = 0x807, 226 MLX5_CMD_OP_GET_DROPPED_PACKET_LOG = 0x80a, 227 MLX5_CMD_OP_MAD_IFC = 0x50d, 228 MLX5_CMD_OP_QUERY_MAD_DEMUX = 0x80b, 229 MLX5_CMD_OP_SET_MAD_DEMUX = 0x80c, 230 MLX5_CMD_OP_NOP = 0x80d, 231 MLX5_CMD_OP_ALLOC_XRCD = 0x80e, 232 MLX5_CMD_OP_DEALLOC_XRCD = 0x80f, 233 MLX5_CMD_OP_ALLOC_TRANSPORT_DOMAIN = 0x816, 234 MLX5_CMD_OP_DEALLOC_TRANSPORT_DOMAIN = 0x817, 235 MLX5_CMD_OP_QUERY_CONG_STATUS = 0x822, 236 MLX5_CMD_OP_MODIFY_CONG_STATUS = 0x823, 237 MLX5_CMD_OP_QUERY_CONG_PARAMS = 0x824, 238 MLX5_CMD_OP_MODIFY_CONG_PARAMS = 0x825, 239 MLX5_CMD_OP_QUERY_CONG_STATISTICS = 0x826, 240 MLX5_CMD_OP_ADD_VXLAN_UDP_DPORT = 0x827, 241 MLX5_CMD_OP_DELETE_VXLAN_UDP_DPORT = 0x828, 242 MLX5_CMD_OP_SET_L2_TABLE_ENTRY = 0x829, 243 MLX5_CMD_OP_QUERY_L2_TABLE_ENTRY = 0x82a, 244 MLX5_CMD_OP_DELETE_L2_TABLE_ENTRY = 0x82b, 245 MLX5_CMD_OP_SET_WOL_ROL = 0x830, 246 MLX5_CMD_OP_QUERY_WOL_ROL = 0x831, 247 MLX5_CMD_OP_CREATE_LAG = 0x840, 248 MLX5_CMD_OP_MODIFY_LAG = 0x841, 249 MLX5_CMD_OP_QUERY_LAG = 0x842, 250 MLX5_CMD_OP_DESTROY_LAG = 0x843, 251 MLX5_CMD_OP_CREATE_VPORT_LAG = 0x844, 252 MLX5_CMD_OP_DESTROY_VPORT_LAG = 0x845, 253 MLX5_CMD_OP_CREATE_TIR = 0x900, 254 MLX5_CMD_OP_MODIFY_TIR = 0x901, 255 MLX5_CMD_OP_DESTROY_TIR = 0x902, 256 MLX5_CMD_OP_QUERY_TIR = 0x903, 257 MLX5_CMD_OP_CREATE_SQ = 0x904, 258 MLX5_CMD_OP_MODIFY_SQ = 0x905, 259 MLX5_CMD_OP_DESTROY_SQ = 0x906, 260 MLX5_CMD_OP_QUERY_SQ = 0x907, 261 MLX5_CMD_OP_CREATE_RQ = 0x908, 262 MLX5_CMD_OP_MODIFY_RQ = 0x909, 263 MLX5_CMD_OP_SET_DELAY_DROP_PARAMS = 0x910, 264 MLX5_CMD_OP_DESTROY_RQ = 0x90a, 265 MLX5_CMD_OP_QUERY_RQ = 0x90b, 266 MLX5_CMD_OP_CREATE_RMP = 0x90c, 267 MLX5_CMD_OP_MODIFY_RMP = 0x90d, 268 MLX5_CMD_OP_DESTROY_RMP = 0x90e, 269 MLX5_CMD_OP_QUERY_RMP = 0x90f, 270 MLX5_CMD_OP_CREATE_TIS = 0x912, 271 MLX5_CMD_OP_MODIFY_TIS = 0x913, 272 MLX5_CMD_OP_DESTROY_TIS = 0x914, 273 MLX5_CMD_OP_QUERY_TIS = 0x915, 274 MLX5_CMD_OP_CREATE_RQT = 0x916, 275 MLX5_CMD_OP_MODIFY_RQT = 0x917, 276 MLX5_CMD_OP_DESTROY_RQT = 0x918, 277 MLX5_CMD_OP_QUERY_RQT = 0x919, 278 MLX5_CMD_OP_SET_FLOW_TABLE_ROOT = 0x92f, 279 MLX5_CMD_OP_CREATE_FLOW_TABLE = 0x930, 280 MLX5_CMD_OP_DESTROY_FLOW_TABLE = 0x931, 281 MLX5_CMD_OP_QUERY_FLOW_TABLE = 0x932, 282 MLX5_CMD_OP_CREATE_FLOW_GROUP = 0x933, 283 MLX5_CMD_OP_DESTROY_FLOW_GROUP = 0x934, 284 MLX5_CMD_OP_QUERY_FLOW_GROUP = 0x935, 285 MLX5_CMD_OP_SET_FLOW_TABLE_ENTRY = 0x936, 286 MLX5_CMD_OP_QUERY_FLOW_TABLE_ENTRY = 0x937, 287 MLX5_CMD_OP_DELETE_FLOW_TABLE_ENTRY = 0x938, 288 MLX5_CMD_OP_ALLOC_FLOW_COUNTER = 0x939, 289 MLX5_CMD_OP_DEALLOC_FLOW_COUNTER = 0x93a, 290 MLX5_CMD_OP_QUERY_FLOW_COUNTER = 0x93b, 291 MLX5_CMD_OP_MODIFY_FLOW_TABLE = 0x93c, 292 MLX5_CMD_OP_ALLOC_PACKET_REFORMAT_CONTEXT = 0x93d, 293 MLX5_CMD_OP_DEALLOC_PACKET_REFORMAT_CONTEXT = 0x93e, 294 MLX5_CMD_OP_QUERY_PACKET_REFORMAT_CONTEXT = 0x93f, 295 MLX5_CMD_OP_ALLOC_MODIFY_HEADER_CONTEXT = 0x940, 296 MLX5_CMD_OP_DEALLOC_MODIFY_HEADER_CONTEXT = 0x941, 297 MLX5_CMD_OP_QUERY_MODIFY_HEADER_CONTEXT = 0x942, 298 MLX5_CMD_OP_FPGA_CREATE_QP = 0x960, 299 MLX5_CMD_OP_FPGA_MODIFY_QP = 0x961, 300 MLX5_CMD_OP_FPGA_QUERY_QP = 0x962, 301 MLX5_CMD_OP_FPGA_DESTROY_QP = 0x963, 302 MLX5_CMD_OP_FPGA_QUERY_QP_COUNTERS = 0x964, 303 MLX5_CMD_OP_CREATE_GENERAL_OBJECT = 0xa00, 304 MLX5_CMD_OP_MODIFY_GENERAL_OBJECT = 0xa01, 305 MLX5_CMD_OP_QUERY_GENERAL_OBJECT = 0xa02, 306 MLX5_CMD_OP_DESTROY_GENERAL_OBJECT = 0xa03, 307 MLX5_CMD_OP_CREATE_UCTX = 0xa04, 308 MLX5_CMD_OP_DESTROY_UCTX = 0xa06, 309 MLX5_CMD_OP_CREATE_UMEM = 0xa08, 310 MLX5_CMD_OP_DESTROY_UMEM = 0xa0a, 311 MLX5_CMD_OP_SYNC_STEERING = 0xb00, 312 MLX5_CMD_OP_QUERY_VHCA_STATE = 0xb0d, 313 MLX5_CMD_OP_MODIFY_VHCA_STATE = 0xb0e, 314 MLX5_CMD_OP_SYNC_CRYPTO = 0xb12, 315 MLX5_CMD_OP_ALLOW_OTHER_VHCA_ACCESS = 0xb16, 316 MLX5_CMD_OP_MAX 317 }; 318 319 /* Valid range for general commands that don't work over an object */ 320 enum { 321 MLX5_CMD_OP_GENERAL_START = 0xb00, 322 MLX5_CMD_OP_GENERAL_END = 0xd00, 323 }; 324 325 enum { 326 MLX5_FT_NIC_RX_2_NIC_RX_RDMA = BIT(0), 327 MLX5_FT_NIC_TX_RDMA_2_NIC_TX = BIT(1), 328 }; 329 330 enum { 331 MLX5_CMD_OP_MOD_UPDATE_HEADER_MODIFY_ARGUMENT = 0x1, 332 }; 333 334 struct mlx5_ifc_flow_table_fields_supported_bits { 335 u8 outer_dmac[0x1]; 336 u8 outer_smac[0x1]; 337 u8 outer_ether_type[0x1]; 338 u8 outer_ip_version[0x1]; 339 u8 outer_first_prio[0x1]; 340 u8 outer_first_cfi[0x1]; 341 u8 outer_first_vid[0x1]; 342 u8 outer_ipv4_ttl[0x1]; 343 u8 outer_second_prio[0x1]; 344 u8 outer_second_cfi[0x1]; 345 u8 outer_second_vid[0x1]; 346 u8 reserved_at_b[0x1]; 347 u8 outer_sip[0x1]; 348 u8 outer_dip[0x1]; 349 u8 outer_frag[0x1]; 350 u8 outer_ip_protocol[0x1]; 351 u8 outer_ip_ecn[0x1]; 352 u8 outer_ip_dscp[0x1]; 353 u8 outer_udp_sport[0x1]; 354 u8 outer_udp_dport[0x1]; 355 u8 outer_tcp_sport[0x1]; 356 u8 outer_tcp_dport[0x1]; 357 u8 outer_tcp_flags[0x1]; 358 u8 outer_gre_protocol[0x1]; 359 u8 outer_gre_key[0x1]; 360 u8 outer_vxlan_vni[0x1]; 361 u8 outer_geneve_vni[0x1]; 362 u8 outer_geneve_oam[0x1]; 363 u8 outer_geneve_protocol_type[0x1]; 364 u8 outer_geneve_opt_len[0x1]; 365 u8 source_vhca_port[0x1]; 366 u8 source_eswitch_port[0x1]; 367 368 u8 inner_dmac[0x1]; 369 u8 inner_smac[0x1]; 370 u8 inner_ether_type[0x1]; 371 u8 inner_ip_version[0x1]; 372 u8 inner_first_prio[0x1]; 373 u8 inner_first_cfi[0x1]; 374 u8 inner_first_vid[0x1]; 375 u8 reserved_at_27[0x1]; 376 u8 inner_second_prio[0x1]; 377 u8 inner_second_cfi[0x1]; 378 u8 inner_second_vid[0x1]; 379 u8 reserved_at_2b[0x1]; 380 u8 inner_sip[0x1]; 381 u8 inner_dip[0x1]; 382 u8 inner_frag[0x1]; 383 u8 inner_ip_protocol[0x1]; 384 u8 inner_ip_ecn[0x1]; 385 u8 inner_ip_dscp[0x1]; 386 u8 inner_udp_sport[0x1]; 387 u8 inner_udp_dport[0x1]; 388 u8 inner_tcp_sport[0x1]; 389 u8 inner_tcp_dport[0x1]; 390 u8 inner_tcp_flags[0x1]; 391 u8 reserved_at_37[0x9]; 392 393 u8 geneve_tlv_option_0_data[0x1]; 394 u8 geneve_tlv_option_0_exist[0x1]; 395 u8 reserved_at_42[0x3]; 396 u8 outer_first_mpls_over_udp[0x4]; 397 u8 outer_first_mpls_over_gre[0x4]; 398 u8 inner_first_mpls[0x4]; 399 u8 outer_first_mpls[0x4]; 400 u8 reserved_at_55[0x2]; 401 u8 outer_esp_spi[0x1]; 402 u8 reserved_at_58[0x2]; 403 u8 bth_dst_qp[0x1]; 404 u8 reserved_at_5b[0x5]; 405 406 u8 reserved_at_60[0x18]; 407 u8 metadata_reg_c_7[0x1]; 408 u8 metadata_reg_c_6[0x1]; 409 u8 metadata_reg_c_5[0x1]; 410 u8 metadata_reg_c_4[0x1]; 411 u8 metadata_reg_c_3[0x1]; 412 u8 metadata_reg_c_2[0x1]; 413 u8 metadata_reg_c_1[0x1]; 414 u8 metadata_reg_c_0[0x1]; 415 }; 416 417 /* Table 2170 - Flow Table Fields Supported 2 Format */ 418 struct mlx5_ifc_flow_table_fields_supported_2_bits { 419 u8 reserved_at_0[0x2]; 420 u8 inner_l4_type[0x1]; 421 u8 outer_l4_type[0x1]; 422 u8 reserved_at_4[0xa]; 423 u8 bth_opcode[0x1]; 424 u8 reserved_at_f[0x1]; 425 u8 tunnel_header_0_1[0x1]; 426 u8 reserved_at_11[0xf]; 427 428 u8 reserved_at_20[0x60]; 429 }; 430 431 struct mlx5_ifc_flow_table_prop_layout_bits { 432 u8 ft_support[0x1]; 433 u8 reserved_at_1[0x1]; 434 u8 flow_counter[0x1]; 435 u8 flow_modify_en[0x1]; 436 u8 modify_root[0x1]; 437 u8 identified_miss_table_mode[0x1]; 438 u8 flow_table_modify[0x1]; 439 u8 reformat[0x1]; 440 u8 decap[0x1]; 441 u8 reset_root_to_default[0x1]; 442 u8 pop_vlan[0x1]; 443 u8 push_vlan[0x1]; 444 u8 reserved_at_c[0x1]; 445 u8 pop_vlan_2[0x1]; 446 u8 push_vlan_2[0x1]; 447 u8 reformat_and_vlan_action[0x1]; 448 u8 reserved_at_10[0x1]; 449 u8 sw_owner[0x1]; 450 u8 reformat_l3_tunnel_to_l2[0x1]; 451 u8 reformat_l2_to_l3_tunnel[0x1]; 452 u8 reformat_and_modify_action[0x1]; 453 u8 ignore_flow_level[0x1]; 454 u8 reserved_at_16[0x1]; 455 u8 table_miss_action_domain[0x1]; 456 u8 termination_table[0x1]; 457 u8 reformat_and_fwd_to_table[0x1]; 458 u8 reserved_at_1a[0x2]; 459 u8 ipsec_encrypt[0x1]; 460 u8 ipsec_decrypt[0x1]; 461 u8 sw_owner_v2[0x1]; 462 u8 reserved_at_1f[0x1]; 463 464 u8 termination_table_raw_traffic[0x1]; 465 u8 reserved_at_21[0x1]; 466 u8 log_max_ft_size[0x6]; 467 u8 log_max_modify_header_context[0x8]; 468 u8 max_modify_header_actions[0x8]; 469 u8 max_ft_level[0x8]; 470 471 u8 reformat_add_esp_trasport[0x1]; 472 u8 reformat_l2_to_l3_esp_tunnel[0x1]; 473 u8 reformat_add_esp_transport_over_udp[0x1]; 474 u8 reformat_del_esp_trasport[0x1]; 475 u8 reformat_l3_esp_tunnel_to_l2[0x1]; 476 u8 reformat_del_esp_transport_over_udp[0x1]; 477 u8 execute_aso[0x1]; 478 u8 reserved_at_47[0x19]; 479 480 u8 reserved_at_60[0x2]; 481 u8 reformat_insert[0x1]; 482 u8 reformat_remove[0x1]; 483 u8 macsec_encrypt[0x1]; 484 u8 macsec_decrypt[0x1]; 485 u8 reserved_at_66[0x2]; 486 u8 reformat_add_macsec[0x1]; 487 u8 reformat_remove_macsec[0x1]; 488 u8 reserved_at_6a[0xe]; 489 u8 log_max_ft_num[0x8]; 490 491 u8 reserved_at_80[0x10]; 492 u8 log_max_flow_counter[0x8]; 493 u8 log_max_destination[0x8]; 494 495 u8 reserved_at_a0[0x18]; 496 u8 log_max_flow[0x8]; 497 498 u8 reserved_at_c0[0x40]; 499 500 struct mlx5_ifc_flow_table_fields_supported_bits ft_field_support; 501 502 struct mlx5_ifc_flow_table_fields_supported_bits ft_field_bitmask_support; 503 }; 504 505 struct mlx5_ifc_odp_per_transport_service_cap_bits { 506 u8 send[0x1]; 507 u8 receive[0x1]; 508 u8 write[0x1]; 509 u8 read[0x1]; 510 u8 atomic[0x1]; 511 u8 srq_receive[0x1]; 512 u8 reserved_at_6[0x1a]; 513 }; 514 515 struct mlx5_ifc_ipv4_layout_bits { 516 u8 reserved_at_0[0x60]; 517 518 u8 ipv4[0x20]; 519 }; 520 521 struct mlx5_ifc_ipv6_layout_bits { 522 u8 ipv6[16][0x8]; 523 }; 524 525 union mlx5_ifc_ipv6_layout_ipv4_layout_auto_bits { 526 struct mlx5_ifc_ipv6_layout_bits ipv6_layout; 527 struct mlx5_ifc_ipv4_layout_bits ipv4_layout; 528 u8 reserved_at_0[0x80]; 529 }; 530 531 enum { 532 MLX5_PACKET_L4_TYPE_NONE, 533 MLX5_PACKET_L4_TYPE_TCP, 534 MLX5_PACKET_L4_TYPE_UDP, 535 }; 536 537 struct mlx5_ifc_fte_match_set_lyr_2_4_bits { 538 u8 smac_47_16[0x20]; 539 540 u8 smac_15_0[0x10]; 541 u8 ethertype[0x10]; 542 543 u8 dmac_47_16[0x20]; 544 545 u8 dmac_15_0[0x10]; 546 u8 first_prio[0x3]; 547 u8 first_cfi[0x1]; 548 u8 first_vid[0xc]; 549 550 u8 ip_protocol[0x8]; 551 u8 ip_dscp[0x6]; 552 u8 ip_ecn[0x2]; 553 u8 cvlan_tag[0x1]; 554 u8 svlan_tag[0x1]; 555 u8 frag[0x1]; 556 u8 ip_version[0x4]; 557 u8 tcp_flags[0x9]; 558 559 u8 tcp_sport[0x10]; 560 u8 tcp_dport[0x10]; 561 562 u8 l4_type[0x2]; 563 u8 reserved_at_c2[0xe]; 564 u8 ipv4_ihl[0x4]; 565 u8 reserved_at_c4[0x4]; 566 567 u8 ttl_hoplimit[0x8]; 568 569 u8 udp_sport[0x10]; 570 u8 udp_dport[0x10]; 571 572 union mlx5_ifc_ipv6_layout_ipv4_layout_auto_bits src_ipv4_src_ipv6; 573 574 union mlx5_ifc_ipv6_layout_ipv4_layout_auto_bits dst_ipv4_dst_ipv6; 575 }; 576 577 struct mlx5_ifc_nvgre_key_bits { 578 u8 hi[0x18]; 579 u8 lo[0x8]; 580 }; 581 582 union mlx5_ifc_gre_key_bits { 583 struct mlx5_ifc_nvgre_key_bits nvgre; 584 u8 key[0x20]; 585 }; 586 587 struct mlx5_ifc_fte_match_set_misc_bits { 588 u8 gre_c_present[0x1]; 589 u8 reserved_at_1[0x1]; 590 u8 gre_k_present[0x1]; 591 u8 gre_s_present[0x1]; 592 u8 source_vhca_port[0x4]; 593 u8 source_sqn[0x18]; 594 595 u8 source_eswitch_owner_vhca_id[0x10]; 596 u8 source_port[0x10]; 597 598 u8 outer_second_prio[0x3]; 599 u8 outer_second_cfi[0x1]; 600 u8 outer_second_vid[0xc]; 601 u8 inner_second_prio[0x3]; 602 u8 inner_second_cfi[0x1]; 603 u8 inner_second_vid[0xc]; 604 605 u8 outer_second_cvlan_tag[0x1]; 606 u8 inner_second_cvlan_tag[0x1]; 607 u8 outer_second_svlan_tag[0x1]; 608 u8 inner_second_svlan_tag[0x1]; 609 u8 reserved_at_64[0xc]; 610 u8 gre_protocol[0x10]; 611 612 union mlx5_ifc_gre_key_bits gre_key; 613 614 u8 vxlan_vni[0x18]; 615 u8 bth_opcode[0x8]; 616 617 u8 geneve_vni[0x18]; 618 u8 reserved_at_d8[0x6]; 619 u8 geneve_tlv_option_0_exist[0x1]; 620 u8 geneve_oam[0x1]; 621 622 u8 reserved_at_e0[0xc]; 623 u8 outer_ipv6_flow_label[0x14]; 624 625 u8 reserved_at_100[0xc]; 626 u8 inner_ipv6_flow_label[0x14]; 627 628 u8 reserved_at_120[0xa]; 629 u8 geneve_opt_len[0x6]; 630 u8 geneve_protocol_type[0x10]; 631 632 u8 reserved_at_140[0x8]; 633 u8 bth_dst_qp[0x18]; 634 u8 inner_esp_spi[0x20]; 635 u8 outer_esp_spi[0x20]; 636 u8 reserved_at_1a0[0x60]; 637 }; 638 639 struct mlx5_ifc_fte_match_mpls_bits { 640 u8 mpls_label[0x14]; 641 u8 mpls_exp[0x3]; 642 u8 mpls_s_bos[0x1]; 643 u8 mpls_ttl[0x8]; 644 }; 645 646 struct mlx5_ifc_fte_match_set_misc2_bits { 647 struct mlx5_ifc_fte_match_mpls_bits outer_first_mpls; 648 649 struct mlx5_ifc_fte_match_mpls_bits inner_first_mpls; 650 651 struct mlx5_ifc_fte_match_mpls_bits outer_first_mpls_over_gre; 652 653 struct mlx5_ifc_fte_match_mpls_bits outer_first_mpls_over_udp; 654 655 u8 metadata_reg_c_7[0x20]; 656 657 u8 metadata_reg_c_6[0x20]; 658 659 u8 metadata_reg_c_5[0x20]; 660 661 u8 metadata_reg_c_4[0x20]; 662 663 u8 metadata_reg_c_3[0x20]; 664 665 u8 metadata_reg_c_2[0x20]; 666 667 u8 metadata_reg_c_1[0x20]; 668 669 u8 metadata_reg_c_0[0x20]; 670 671 u8 metadata_reg_a[0x20]; 672 673 u8 reserved_at_1a0[0x8]; 674 675 u8 macsec_syndrome[0x8]; 676 u8 ipsec_syndrome[0x8]; 677 u8 reserved_at_1b8[0x8]; 678 679 u8 reserved_at_1c0[0x40]; 680 }; 681 682 struct mlx5_ifc_fte_match_set_misc3_bits { 683 u8 inner_tcp_seq_num[0x20]; 684 685 u8 outer_tcp_seq_num[0x20]; 686 687 u8 inner_tcp_ack_num[0x20]; 688 689 u8 outer_tcp_ack_num[0x20]; 690 691 u8 reserved_at_80[0x8]; 692 u8 outer_vxlan_gpe_vni[0x18]; 693 694 u8 outer_vxlan_gpe_next_protocol[0x8]; 695 u8 outer_vxlan_gpe_flags[0x8]; 696 u8 reserved_at_b0[0x10]; 697 698 u8 icmp_header_data[0x20]; 699 700 u8 icmpv6_header_data[0x20]; 701 702 u8 icmp_type[0x8]; 703 u8 icmp_code[0x8]; 704 u8 icmpv6_type[0x8]; 705 u8 icmpv6_code[0x8]; 706 707 u8 geneve_tlv_option_0_data[0x20]; 708 709 u8 gtpu_teid[0x20]; 710 711 u8 gtpu_msg_type[0x8]; 712 u8 gtpu_msg_flags[0x8]; 713 u8 reserved_at_170[0x10]; 714 715 u8 gtpu_dw_2[0x20]; 716 717 u8 gtpu_first_ext_dw_0[0x20]; 718 719 u8 gtpu_dw_0[0x20]; 720 721 u8 reserved_at_1e0[0x20]; 722 }; 723 724 struct mlx5_ifc_fte_match_set_misc4_bits { 725 u8 prog_sample_field_value_0[0x20]; 726 727 u8 prog_sample_field_id_0[0x20]; 728 729 u8 prog_sample_field_value_1[0x20]; 730 731 u8 prog_sample_field_id_1[0x20]; 732 733 u8 prog_sample_field_value_2[0x20]; 734 735 u8 prog_sample_field_id_2[0x20]; 736 737 u8 prog_sample_field_value_3[0x20]; 738 739 u8 prog_sample_field_id_3[0x20]; 740 741 u8 reserved_at_100[0x100]; 742 }; 743 744 struct mlx5_ifc_fte_match_set_misc5_bits { 745 u8 macsec_tag_0[0x20]; 746 747 u8 macsec_tag_1[0x20]; 748 749 u8 macsec_tag_2[0x20]; 750 751 u8 macsec_tag_3[0x20]; 752 753 u8 tunnel_header_0[0x20]; 754 755 u8 tunnel_header_1[0x20]; 756 757 u8 tunnel_header_2[0x20]; 758 759 u8 tunnel_header_3[0x20]; 760 761 u8 reserved_at_100[0x100]; 762 }; 763 764 struct mlx5_ifc_cmd_pas_bits { 765 u8 pa_h[0x20]; 766 767 u8 pa_l[0x14]; 768 u8 reserved_at_34[0xc]; 769 }; 770 771 struct mlx5_ifc_uint64_bits { 772 u8 hi[0x20]; 773 774 u8 lo[0x20]; 775 }; 776 777 enum { 778 MLX5_ADS_STAT_RATE_NO_LIMIT = 0x0, 779 MLX5_ADS_STAT_RATE_2_5GBPS = 0x7, 780 MLX5_ADS_STAT_RATE_10GBPS = 0x8, 781 MLX5_ADS_STAT_RATE_30GBPS = 0x9, 782 MLX5_ADS_STAT_RATE_5GBPS = 0xa, 783 MLX5_ADS_STAT_RATE_20GBPS = 0xb, 784 MLX5_ADS_STAT_RATE_40GBPS = 0xc, 785 MLX5_ADS_STAT_RATE_60GBPS = 0xd, 786 MLX5_ADS_STAT_RATE_80GBPS = 0xe, 787 MLX5_ADS_STAT_RATE_120GBPS = 0xf, 788 }; 789 790 struct mlx5_ifc_ads_bits { 791 u8 fl[0x1]; 792 u8 free_ar[0x1]; 793 u8 reserved_at_2[0xe]; 794 u8 pkey_index[0x10]; 795 796 u8 plane_index[0x8]; 797 u8 grh[0x1]; 798 u8 mlid[0x7]; 799 u8 rlid[0x10]; 800 801 u8 ack_timeout[0x5]; 802 u8 reserved_at_45[0x3]; 803 u8 src_addr_index[0x8]; 804 u8 reserved_at_50[0x4]; 805 u8 stat_rate[0x4]; 806 u8 hop_limit[0x8]; 807 808 u8 reserved_at_60[0x4]; 809 u8 tclass[0x8]; 810 u8 flow_label[0x14]; 811 812 u8 rgid_rip[16][0x8]; 813 814 u8 reserved_at_100[0x4]; 815 u8 f_dscp[0x1]; 816 u8 f_ecn[0x1]; 817 u8 reserved_at_106[0x1]; 818 u8 f_eth_prio[0x1]; 819 u8 ecn[0x2]; 820 u8 dscp[0x6]; 821 u8 udp_sport[0x10]; 822 823 u8 dei_cfi[0x1]; 824 u8 eth_prio[0x3]; 825 u8 sl[0x4]; 826 u8 vhca_port_num[0x8]; 827 u8 rmac_47_32[0x10]; 828 829 u8 rmac_31_0[0x20]; 830 }; 831 832 struct mlx5_ifc_flow_table_nic_cap_bits { 833 u8 nic_rx_multi_path_tirs[0x1]; 834 u8 nic_rx_multi_path_tirs_fts[0x1]; 835 u8 allow_sniffer_and_nic_rx_shared_tir[0x1]; 836 u8 reserved_at_3[0x4]; 837 u8 sw_owner_reformat_supported[0x1]; 838 u8 reserved_at_8[0x18]; 839 840 u8 encap_general_header[0x1]; 841 u8 reserved_at_21[0xa]; 842 u8 log_max_packet_reformat_context[0x5]; 843 u8 reserved_at_30[0x6]; 844 u8 max_encap_header_size[0xa]; 845 u8 reserved_at_40[0x1c0]; 846 847 struct mlx5_ifc_flow_table_prop_layout_bits flow_table_properties_nic_receive; 848 849 struct mlx5_ifc_flow_table_prop_layout_bits flow_table_properties_nic_receive_rdma; 850 851 struct mlx5_ifc_flow_table_prop_layout_bits flow_table_properties_nic_receive_sniffer; 852 853 struct mlx5_ifc_flow_table_prop_layout_bits flow_table_properties_nic_transmit; 854 855 struct mlx5_ifc_flow_table_prop_layout_bits flow_table_properties_nic_transmit_rdma; 856 857 struct mlx5_ifc_flow_table_prop_layout_bits flow_table_properties_nic_transmit_sniffer; 858 859 u8 reserved_at_e00[0x600]; 860 861 struct mlx5_ifc_flow_table_fields_supported_2_bits ft_field_support_2_nic_receive; 862 863 u8 reserved_at_1480[0x80]; 864 865 struct mlx5_ifc_flow_table_fields_supported_2_bits ft_field_support_2_nic_receive_rdma; 866 867 u8 reserved_at_1580[0x280]; 868 869 struct mlx5_ifc_flow_table_fields_supported_2_bits ft_field_support_2_nic_transmit_rdma; 870 871 u8 reserved_at_1880[0x780]; 872 873 u8 sw_steering_nic_rx_action_drop_icm_address[0x40]; 874 875 u8 sw_steering_nic_tx_action_drop_icm_address[0x40]; 876 877 u8 sw_steering_nic_tx_action_allow_icm_address[0x40]; 878 879 u8 reserved_at_20c0[0x5f40]; 880 }; 881 882 struct mlx5_ifc_port_selection_cap_bits { 883 u8 reserved_at_0[0x10]; 884 u8 port_select_flow_table[0x1]; 885 u8 reserved_at_11[0x1]; 886 u8 port_select_flow_table_bypass[0x1]; 887 u8 reserved_at_13[0xd]; 888 889 u8 reserved_at_20[0x1e0]; 890 891 struct mlx5_ifc_flow_table_prop_layout_bits flow_table_properties_port_selection; 892 893 struct mlx5_ifc_flow_table_fields_supported_2_bits ft_field_support_2_port_selection; 894 895 u8 reserved_at_480[0x7b80]; 896 }; 897 898 enum { 899 MLX5_FDB_TO_VPORT_REG_C_0 = 0x01, 900 MLX5_FDB_TO_VPORT_REG_C_1 = 0x02, 901 MLX5_FDB_TO_VPORT_REG_C_2 = 0x04, 902 MLX5_FDB_TO_VPORT_REG_C_3 = 0x08, 903 MLX5_FDB_TO_VPORT_REG_C_4 = 0x10, 904 MLX5_FDB_TO_VPORT_REG_C_5 = 0x20, 905 MLX5_FDB_TO_VPORT_REG_C_6 = 0x40, 906 MLX5_FDB_TO_VPORT_REG_C_7 = 0x80, 907 }; 908 909 struct mlx5_ifc_flow_table_eswitch_cap_bits { 910 u8 fdb_to_vport_reg_c_id[0x8]; 911 u8 reserved_at_8[0x5]; 912 u8 fdb_uplink_hairpin[0x1]; 913 u8 fdb_multi_path_any_table_limit_regc[0x1]; 914 u8 reserved_at_f[0x3]; 915 u8 fdb_multi_path_any_table[0x1]; 916 u8 reserved_at_13[0x2]; 917 u8 fdb_modify_header_fwd_to_table[0x1]; 918 u8 fdb_ipv4_ttl_modify[0x1]; 919 u8 flow_source[0x1]; 920 u8 reserved_at_18[0x2]; 921 u8 multi_fdb_encap[0x1]; 922 u8 egress_acl_forward_to_vport[0x1]; 923 u8 fdb_multi_path_to_table[0x1]; 924 u8 reserved_at_1d[0x3]; 925 926 u8 reserved_at_20[0x1e0]; 927 928 struct mlx5_ifc_flow_table_prop_layout_bits flow_table_properties_nic_esw_fdb; 929 930 struct mlx5_ifc_flow_table_prop_layout_bits flow_table_properties_esw_acl_ingress; 931 932 struct mlx5_ifc_flow_table_prop_layout_bits flow_table_properties_esw_acl_egress; 933 934 u8 reserved_at_800[0xC00]; 935 936 struct mlx5_ifc_flow_table_fields_supported_2_bits ft_field_support_2_esw_fdb; 937 938 struct mlx5_ifc_flow_table_fields_supported_2_bits ft_field_bitmask_support_2_esw_fdb; 939 940 u8 reserved_at_1500[0x300]; 941 942 u8 sw_steering_fdb_action_drop_icm_address_rx[0x40]; 943 944 u8 sw_steering_fdb_action_drop_icm_address_tx[0x40]; 945 946 u8 sw_steering_uplink_icm_address_rx[0x40]; 947 948 u8 sw_steering_uplink_icm_address_tx[0x40]; 949 950 u8 reserved_at_1900[0x6700]; 951 }; 952 953 enum { 954 MLX5_COUNTER_SOURCE_ESWITCH = 0x0, 955 MLX5_COUNTER_FLOW_ESWITCH = 0x1, 956 }; 957 958 struct mlx5_ifc_e_switch_cap_bits { 959 u8 vport_svlan_strip[0x1]; 960 u8 vport_cvlan_strip[0x1]; 961 u8 vport_svlan_insert[0x1]; 962 u8 vport_cvlan_insert_if_not_exist[0x1]; 963 u8 vport_cvlan_insert_overwrite[0x1]; 964 u8 reserved_at_5[0x1]; 965 u8 vport_cvlan_insert_always[0x1]; 966 u8 esw_shared_ingress_acl[0x1]; 967 u8 esw_uplink_ingress_acl[0x1]; 968 u8 root_ft_on_other_esw[0x1]; 969 u8 reserved_at_a[0xf]; 970 u8 esw_functions_changed[0x1]; 971 u8 reserved_at_1a[0x1]; 972 u8 ecpf_vport_exists[0x1]; 973 u8 counter_eswitch_affinity[0x1]; 974 u8 merged_eswitch[0x1]; 975 u8 nic_vport_node_guid_modify[0x1]; 976 u8 nic_vport_port_guid_modify[0x1]; 977 978 u8 vxlan_encap_decap[0x1]; 979 u8 nvgre_encap_decap[0x1]; 980 u8 reserved_at_22[0x1]; 981 u8 log_max_fdb_encap_uplink[0x5]; 982 u8 reserved_at_21[0x3]; 983 u8 log_max_packet_reformat_context[0x5]; 984 u8 reserved_2b[0x6]; 985 u8 max_encap_header_size[0xa]; 986 987 u8 reserved_at_40[0xb]; 988 u8 log_max_esw_sf[0x5]; 989 u8 esw_sf_base_id[0x10]; 990 991 u8 reserved_at_60[0x7a0]; 992 993 }; 994 995 struct mlx5_ifc_qos_cap_bits { 996 u8 packet_pacing[0x1]; 997 u8 esw_scheduling[0x1]; 998 u8 esw_bw_share[0x1]; 999 u8 esw_rate_limit[0x1]; 1000 u8 reserved_at_4[0x1]; 1001 u8 packet_pacing_burst_bound[0x1]; 1002 u8 packet_pacing_typical_size[0x1]; 1003 u8 reserved_at_7[0x1]; 1004 u8 nic_sq_scheduling[0x1]; 1005 u8 nic_bw_share[0x1]; 1006 u8 nic_rate_limit[0x1]; 1007 u8 packet_pacing_uid[0x1]; 1008 u8 log_esw_max_sched_depth[0x4]; 1009 u8 reserved_at_10[0x10]; 1010 1011 u8 reserved_at_20[0xb]; 1012 u8 log_max_qos_nic_queue_group[0x5]; 1013 u8 reserved_at_30[0x10]; 1014 1015 u8 packet_pacing_max_rate[0x20]; 1016 1017 u8 packet_pacing_min_rate[0x20]; 1018 1019 u8 reserved_at_80[0x10]; 1020 u8 packet_pacing_rate_table_size[0x10]; 1021 1022 u8 esw_element_type[0x10]; 1023 u8 esw_tsar_type[0x10]; 1024 1025 u8 reserved_at_c0[0x10]; 1026 u8 max_qos_para_vport[0x10]; 1027 1028 u8 max_tsar_bw_share[0x20]; 1029 1030 u8 reserved_at_100[0x20]; 1031 1032 u8 reserved_at_120[0x3]; 1033 u8 log_meter_aso_granularity[0x5]; 1034 u8 reserved_at_128[0x3]; 1035 u8 log_meter_aso_max_alloc[0x5]; 1036 u8 reserved_at_130[0x3]; 1037 u8 log_max_num_meter_aso[0x5]; 1038 u8 reserved_at_138[0x8]; 1039 1040 u8 reserved_at_140[0x6c0]; 1041 }; 1042 1043 struct mlx5_ifc_debug_cap_bits { 1044 u8 core_dump_general[0x1]; 1045 u8 core_dump_qp[0x1]; 1046 u8 reserved_at_2[0x7]; 1047 u8 resource_dump[0x1]; 1048 u8 reserved_at_a[0x16]; 1049 1050 u8 reserved_at_20[0x2]; 1051 u8 stall_detect[0x1]; 1052 u8 reserved_at_23[0x1d]; 1053 1054 u8 reserved_at_40[0x7c0]; 1055 }; 1056 1057 struct mlx5_ifc_per_protocol_networking_offload_caps_bits { 1058 u8 csum_cap[0x1]; 1059 u8 vlan_cap[0x1]; 1060 u8 lro_cap[0x1]; 1061 u8 lro_psh_flag[0x1]; 1062 u8 lro_time_stamp[0x1]; 1063 u8 reserved_at_5[0x2]; 1064 u8 wqe_vlan_insert[0x1]; 1065 u8 self_lb_en_modifiable[0x1]; 1066 u8 reserved_at_9[0x2]; 1067 u8 max_lso_cap[0x5]; 1068 u8 multi_pkt_send_wqe[0x2]; 1069 u8 wqe_inline_mode[0x2]; 1070 u8 rss_ind_tbl_cap[0x4]; 1071 u8 reg_umr_sq[0x1]; 1072 u8 scatter_fcs[0x1]; 1073 u8 enhanced_multi_pkt_send_wqe[0x1]; 1074 u8 tunnel_lso_const_out_ip_id[0x1]; 1075 u8 tunnel_lro_gre[0x1]; 1076 u8 tunnel_lro_vxlan[0x1]; 1077 u8 tunnel_stateless_gre[0x1]; 1078 u8 tunnel_stateless_vxlan[0x1]; 1079 1080 u8 swp[0x1]; 1081 u8 swp_csum[0x1]; 1082 u8 swp_lso[0x1]; 1083 u8 cqe_checksum_full[0x1]; 1084 u8 tunnel_stateless_geneve_tx[0x1]; 1085 u8 tunnel_stateless_mpls_over_udp[0x1]; 1086 u8 tunnel_stateless_mpls_over_gre[0x1]; 1087 u8 tunnel_stateless_vxlan_gpe[0x1]; 1088 u8 tunnel_stateless_ipv4_over_vxlan[0x1]; 1089 u8 tunnel_stateless_ip_over_ip[0x1]; 1090 u8 insert_trailer[0x1]; 1091 u8 reserved_at_2b[0x1]; 1092 u8 tunnel_stateless_ip_over_ip_rx[0x1]; 1093 u8 tunnel_stateless_ip_over_ip_tx[0x1]; 1094 u8 reserved_at_2e[0x2]; 1095 u8 max_vxlan_udp_ports[0x8]; 1096 u8 swp_csum_l4_partial[0x1]; 1097 u8 reserved_at_39[0x5]; 1098 u8 max_geneve_opt_len[0x1]; 1099 u8 tunnel_stateless_geneve_rx[0x1]; 1100 1101 u8 reserved_at_40[0x10]; 1102 u8 lro_min_mss_size[0x10]; 1103 1104 u8 reserved_at_60[0x120]; 1105 1106 u8 lro_timer_supported_periods[4][0x20]; 1107 1108 u8 reserved_at_200[0x600]; 1109 }; 1110 1111 enum { 1112 MLX5_TIMESTAMP_FORMAT_CAP_FREE_RUNNING = 0x0, 1113 MLX5_TIMESTAMP_FORMAT_CAP_REAL_TIME = 0x1, 1114 MLX5_TIMESTAMP_FORMAT_CAP_FREE_RUNNING_AND_REAL_TIME = 0x2, 1115 }; 1116 1117 struct mlx5_ifc_roce_cap_bits { 1118 u8 roce_apm[0x1]; 1119 u8 reserved_at_1[0x3]; 1120 u8 sw_r_roce_src_udp_port[0x1]; 1121 u8 fl_rc_qp_when_roce_disabled[0x1]; 1122 u8 fl_rc_qp_when_roce_enabled[0x1]; 1123 u8 roce_cc_general[0x1]; 1124 u8 qp_ooo_transmit_default[0x1]; 1125 u8 reserved_at_9[0x15]; 1126 u8 qp_ts_format[0x2]; 1127 1128 u8 reserved_at_20[0x60]; 1129 1130 u8 reserved_at_80[0xc]; 1131 u8 l3_type[0x4]; 1132 u8 reserved_at_90[0x8]; 1133 u8 roce_version[0x8]; 1134 1135 u8 reserved_at_a0[0x10]; 1136 u8 r_roce_dest_udp_port[0x10]; 1137 1138 u8 r_roce_max_src_udp_port[0x10]; 1139 u8 r_roce_min_src_udp_port[0x10]; 1140 1141 u8 reserved_at_e0[0x10]; 1142 u8 roce_address_table_size[0x10]; 1143 1144 u8 reserved_at_100[0x700]; 1145 }; 1146 1147 struct mlx5_ifc_sync_steering_in_bits { 1148 u8 opcode[0x10]; 1149 u8 uid[0x10]; 1150 1151 u8 reserved_at_20[0x10]; 1152 u8 op_mod[0x10]; 1153 1154 u8 reserved_at_40[0xc0]; 1155 }; 1156 1157 struct mlx5_ifc_sync_steering_out_bits { 1158 u8 status[0x8]; 1159 u8 reserved_at_8[0x18]; 1160 1161 u8 syndrome[0x20]; 1162 1163 u8 reserved_at_40[0x40]; 1164 }; 1165 1166 struct mlx5_ifc_sync_crypto_in_bits { 1167 u8 opcode[0x10]; 1168 u8 uid[0x10]; 1169 1170 u8 reserved_at_20[0x10]; 1171 u8 op_mod[0x10]; 1172 1173 u8 reserved_at_40[0x20]; 1174 1175 u8 reserved_at_60[0x10]; 1176 u8 crypto_type[0x10]; 1177 1178 u8 reserved_at_80[0x80]; 1179 }; 1180 1181 struct mlx5_ifc_sync_crypto_out_bits { 1182 u8 status[0x8]; 1183 u8 reserved_at_8[0x18]; 1184 1185 u8 syndrome[0x20]; 1186 1187 u8 reserved_at_40[0x40]; 1188 }; 1189 1190 struct mlx5_ifc_device_mem_cap_bits { 1191 u8 memic[0x1]; 1192 u8 reserved_at_1[0x1f]; 1193 1194 u8 reserved_at_20[0xb]; 1195 u8 log_min_memic_alloc_size[0x5]; 1196 u8 reserved_at_30[0x8]; 1197 u8 log_max_memic_addr_alignment[0x8]; 1198 1199 u8 memic_bar_start_addr[0x40]; 1200 1201 u8 memic_bar_size[0x20]; 1202 1203 u8 max_memic_size[0x20]; 1204 1205 u8 steering_sw_icm_start_address[0x40]; 1206 1207 u8 reserved_at_100[0x8]; 1208 u8 log_header_modify_sw_icm_size[0x8]; 1209 u8 reserved_at_110[0x2]; 1210 u8 log_sw_icm_alloc_granularity[0x6]; 1211 u8 log_steering_sw_icm_size[0x8]; 1212 1213 u8 log_indirect_encap_sw_icm_size[0x8]; 1214 u8 reserved_at_128[0x10]; 1215 u8 log_header_modify_pattern_sw_icm_size[0x8]; 1216 1217 u8 header_modify_sw_icm_start_address[0x40]; 1218 1219 u8 reserved_at_180[0x40]; 1220 1221 u8 header_modify_pattern_sw_icm_start_address[0x40]; 1222 1223 u8 memic_operations[0x20]; 1224 1225 u8 reserved_at_220[0x20]; 1226 1227 u8 indirect_encap_sw_icm_start_address[0x40]; 1228 1229 u8 reserved_at_280[0x580]; 1230 }; 1231 1232 struct mlx5_ifc_device_event_cap_bits { 1233 u8 user_affiliated_events[4][0x40]; 1234 1235 u8 user_unaffiliated_events[4][0x40]; 1236 }; 1237 1238 struct mlx5_ifc_virtio_emulation_cap_bits { 1239 u8 desc_tunnel_offload_type[0x1]; 1240 u8 eth_frame_offload_type[0x1]; 1241 u8 virtio_version_1_0[0x1]; 1242 u8 device_features_bits_mask[0xd]; 1243 u8 event_mode[0x8]; 1244 u8 virtio_queue_type[0x8]; 1245 1246 u8 max_tunnel_desc[0x10]; 1247 u8 reserved_at_30[0x3]; 1248 u8 log_doorbell_stride[0x5]; 1249 u8 reserved_at_38[0x3]; 1250 u8 log_doorbell_bar_size[0x5]; 1251 1252 u8 doorbell_bar_offset[0x40]; 1253 1254 u8 max_emulated_devices[0x8]; 1255 u8 max_num_virtio_queues[0x18]; 1256 1257 u8 reserved_at_a0[0x20]; 1258 1259 u8 reserved_at_c0[0x13]; 1260 u8 desc_group_mkey_supported[0x1]; 1261 u8 freeze_to_rdy_supported[0x1]; 1262 u8 reserved_at_d5[0xb]; 1263 1264 u8 reserved_at_e0[0x20]; 1265 1266 u8 umem_1_buffer_param_a[0x20]; 1267 1268 u8 umem_1_buffer_param_b[0x20]; 1269 1270 u8 umem_2_buffer_param_a[0x20]; 1271 1272 u8 umem_2_buffer_param_b[0x20]; 1273 1274 u8 umem_3_buffer_param_a[0x20]; 1275 1276 u8 umem_3_buffer_param_b[0x20]; 1277 1278 u8 reserved_at_1c0[0x640]; 1279 }; 1280 1281 enum { 1282 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_QP_1_BYTE = 0x0, 1283 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_QP_2_BYTES = 0x2, 1284 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_QP_4_BYTES = 0x4, 1285 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_QP_8_BYTES = 0x8, 1286 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_QP_16_BYTES = 0x10, 1287 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_QP_32_BYTES = 0x20, 1288 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_QP_64_BYTES = 0x40, 1289 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_QP_128_BYTES = 0x80, 1290 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_QP_256_BYTES = 0x100, 1291 }; 1292 1293 enum { 1294 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_DC_1_BYTE = 0x1, 1295 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_DC_2_BYTES = 0x2, 1296 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_DC_4_BYTES = 0x4, 1297 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_DC_8_BYTES = 0x8, 1298 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_DC_16_BYTES = 0x10, 1299 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_DC_32_BYTES = 0x20, 1300 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_DC_64_BYTES = 0x40, 1301 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_DC_128_BYTES = 0x80, 1302 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_DC_256_BYTES = 0x100, 1303 }; 1304 1305 struct mlx5_ifc_atomic_caps_bits { 1306 u8 reserved_at_0[0x40]; 1307 1308 u8 atomic_req_8B_endianness_mode[0x2]; 1309 u8 reserved_at_42[0x4]; 1310 u8 supported_atomic_req_8B_endianness_mode_1[0x1]; 1311 1312 u8 reserved_at_47[0x19]; 1313 1314 u8 reserved_at_60[0x20]; 1315 1316 u8 reserved_at_80[0x10]; 1317 u8 atomic_operations[0x10]; 1318 1319 u8 reserved_at_a0[0x10]; 1320 u8 atomic_size_qp[0x10]; 1321 1322 u8 reserved_at_c0[0x10]; 1323 u8 atomic_size_dc[0x10]; 1324 1325 u8 reserved_at_e0[0x720]; 1326 }; 1327 1328 struct mlx5_ifc_odp_cap_bits { 1329 u8 reserved_at_0[0x40]; 1330 1331 u8 sig[0x1]; 1332 u8 reserved_at_41[0x1f]; 1333 1334 u8 reserved_at_60[0x20]; 1335 1336 struct mlx5_ifc_odp_per_transport_service_cap_bits rc_odp_caps; 1337 1338 struct mlx5_ifc_odp_per_transport_service_cap_bits uc_odp_caps; 1339 1340 struct mlx5_ifc_odp_per_transport_service_cap_bits ud_odp_caps; 1341 1342 struct mlx5_ifc_odp_per_transport_service_cap_bits xrc_odp_caps; 1343 1344 struct mlx5_ifc_odp_per_transport_service_cap_bits dc_odp_caps; 1345 1346 u8 reserved_at_120[0x6E0]; 1347 }; 1348 1349 struct mlx5_ifc_tls_cap_bits { 1350 u8 tls_1_2_aes_gcm_128[0x1]; 1351 u8 tls_1_3_aes_gcm_128[0x1]; 1352 u8 tls_1_2_aes_gcm_256[0x1]; 1353 u8 tls_1_3_aes_gcm_256[0x1]; 1354 u8 reserved_at_4[0x1c]; 1355 1356 u8 reserved_at_20[0x7e0]; 1357 }; 1358 1359 struct mlx5_ifc_ipsec_cap_bits { 1360 u8 ipsec_full_offload[0x1]; 1361 u8 ipsec_crypto_offload[0x1]; 1362 u8 ipsec_esn[0x1]; 1363 u8 ipsec_crypto_esp_aes_gcm_256_encrypt[0x1]; 1364 u8 ipsec_crypto_esp_aes_gcm_128_encrypt[0x1]; 1365 u8 ipsec_crypto_esp_aes_gcm_256_decrypt[0x1]; 1366 u8 ipsec_crypto_esp_aes_gcm_128_decrypt[0x1]; 1367 u8 reserved_at_7[0x4]; 1368 u8 log_max_ipsec_offload[0x5]; 1369 u8 reserved_at_10[0x10]; 1370 1371 u8 min_log_ipsec_full_replay_window[0x8]; 1372 u8 max_log_ipsec_full_replay_window[0x8]; 1373 u8 reserved_at_30[0x7d0]; 1374 }; 1375 1376 struct mlx5_ifc_macsec_cap_bits { 1377 u8 macsec_epn[0x1]; 1378 u8 reserved_at_1[0x2]; 1379 u8 macsec_crypto_esp_aes_gcm_256_encrypt[0x1]; 1380 u8 macsec_crypto_esp_aes_gcm_128_encrypt[0x1]; 1381 u8 macsec_crypto_esp_aes_gcm_256_decrypt[0x1]; 1382 u8 macsec_crypto_esp_aes_gcm_128_decrypt[0x1]; 1383 u8 reserved_at_7[0x4]; 1384 u8 log_max_macsec_offload[0x5]; 1385 u8 reserved_at_10[0x10]; 1386 1387 u8 min_log_macsec_full_replay_window[0x8]; 1388 u8 max_log_macsec_full_replay_window[0x8]; 1389 u8 reserved_at_30[0x10]; 1390 1391 u8 reserved_at_40[0x7c0]; 1392 }; 1393 1394 enum { 1395 MLX5_WQ_TYPE_LINKED_LIST = 0x0, 1396 MLX5_WQ_TYPE_CYCLIC = 0x1, 1397 MLX5_WQ_TYPE_LINKED_LIST_STRIDING_RQ = 0x2, 1398 MLX5_WQ_TYPE_CYCLIC_STRIDING_RQ = 0x3, 1399 }; 1400 1401 enum { 1402 MLX5_WQ_END_PAD_MODE_NONE = 0x0, 1403 MLX5_WQ_END_PAD_MODE_ALIGN = 0x1, 1404 }; 1405 1406 enum { 1407 MLX5_CMD_HCA_CAP_GID_TABLE_SIZE_8_GID_ENTRIES = 0x0, 1408 MLX5_CMD_HCA_CAP_GID_TABLE_SIZE_16_GID_ENTRIES = 0x1, 1409 MLX5_CMD_HCA_CAP_GID_TABLE_SIZE_32_GID_ENTRIES = 0x2, 1410 MLX5_CMD_HCA_CAP_GID_TABLE_SIZE_64_GID_ENTRIES = 0x3, 1411 MLX5_CMD_HCA_CAP_GID_TABLE_SIZE_128_GID_ENTRIES = 0x4, 1412 }; 1413 1414 enum { 1415 MLX5_CMD_HCA_CAP_PKEY_TABLE_SIZE_128_ENTRIES = 0x0, 1416 MLX5_CMD_HCA_CAP_PKEY_TABLE_SIZE_256_ENTRIES = 0x1, 1417 MLX5_CMD_HCA_CAP_PKEY_TABLE_SIZE_512_ENTRIES = 0x2, 1418 MLX5_CMD_HCA_CAP_PKEY_TABLE_SIZE_1K_ENTRIES = 0x3, 1419 MLX5_CMD_HCA_CAP_PKEY_TABLE_SIZE_2K_ENTRIES = 0x4, 1420 MLX5_CMD_HCA_CAP_PKEY_TABLE_SIZE_4K_ENTRIES = 0x5, 1421 }; 1422 1423 enum { 1424 MLX5_CMD_HCA_CAP_PORT_TYPE_IB = 0x0, 1425 MLX5_CMD_HCA_CAP_PORT_TYPE_ETHERNET = 0x1, 1426 }; 1427 1428 enum { 1429 MLX5_CMD_HCA_CAP_CMDIF_CHECKSUM_DISABLED = 0x0, 1430 MLX5_CMD_HCA_CAP_CMDIF_CHECKSUM_INITIAL_STATE = 0x1, 1431 MLX5_CMD_HCA_CAP_CMDIF_CHECKSUM_ENABLED = 0x3, 1432 }; 1433 1434 enum { 1435 MLX5_CAP_PORT_TYPE_IB = 0x0, 1436 MLX5_CAP_PORT_TYPE_ETH = 0x1, 1437 }; 1438 1439 enum { 1440 MLX5_CAP_UMR_FENCE_STRONG = 0x0, 1441 MLX5_CAP_UMR_FENCE_SMALL = 0x1, 1442 MLX5_CAP_UMR_FENCE_NONE = 0x2, 1443 }; 1444 1445 enum { 1446 MLX5_FLEX_PARSER_GENEVE_ENABLED = 1 << 3, 1447 MLX5_FLEX_PARSER_MPLS_OVER_GRE_ENABLED = 1 << 4, 1448 MLX5_FLEX_PARSER_MPLS_OVER_UDP_ENABLED = 1 << 5, 1449 MLX5_FLEX_PARSER_VXLAN_GPE_ENABLED = 1 << 7, 1450 MLX5_FLEX_PARSER_ICMP_V4_ENABLED = 1 << 8, 1451 MLX5_FLEX_PARSER_ICMP_V6_ENABLED = 1 << 9, 1452 MLX5_FLEX_PARSER_GENEVE_TLV_OPTION_0_ENABLED = 1 << 10, 1453 MLX5_FLEX_PARSER_GTPU_ENABLED = 1 << 11, 1454 MLX5_FLEX_PARSER_GTPU_DW_2_ENABLED = 1 << 16, 1455 MLX5_FLEX_PARSER_GTPU_FIRST_EXT_DW_0_ENABLED = 1 << 17, 1456 MLX5_FLEX_PARSER_GTPU_DW_0_ENABLED = 1 << 18, 1457 MLX5_FLEX_PARSER_GTPU_TEID_ENABLED = 1 << 19, 1458 }; 1459 1460 enum { 1461 MLX5_UCTX_CAP_RAW_TX = 1UL << 0, 1462 MLX5_UCTX_CAP_INTERNAL_DEV_RES = 1UL << 1, 1463 }; 1464 1465 #define MLX5_FC_BULK_SIZE_FACTOR 128 1466 1467 enum mlx5_fc_bulk_alloc_bitmask { 1468 MLX5_FC_BULK_128 = (1 << 0), 1469 MLX5_FC_BULK_256 = (1 << 1), 1470 MLX5_FC_BULK_512 = (1 << 2), 1471 MLX5_FC_BULK_1024 = (1 << 3), 1472 MLX5_FC_BULK_2048 = (1 << 4), 1473 MLX5_FC_BULK_4096 = (1 << 5), 1474 MLX5_FC_BULK_8192 = (1 << 6), 1475 MLX5_FC_BULK_16384 = (1 << 7), 1476 }; 1477 1478 #define MLX5_FC_BULK_NUM_FCS(fc_enum) (MLX5_FC_BULK_SIZE_FACTOR * (fc_enum)) 1479 1480 #define MLX5_FT_MAX_MULTIPATH_LEVEL 63 1481 1482 enum { 1483 MLX5_STEERING_FORMAT_CONNECTX_5 = 0, 1484 MLX5_STEERING_FORMAT_CONNECTX_6DX = 1, 1485 MLX5_STEERING_FORMAT_CONNECTX_7 = 2, 1486 }; 1487 1488 struct mlx5_ifc_cmd_hca_cap_bits { 1489 u8 reserved_at_0[0x6]; 1490 u8 page_request_disable[0x1]; 1491 u8 reserved_at_7[0x9]; 1492 u8 shared_object_to_user_object_allowed[0x1]; 1493 u8 reserved_at_13[0xe]; 1494 u8 vhca_resource_manager[0x1]; 1495 1496 u8 hca_cap_2[0x1]; 1497 u8 create_lag_when_not_master_up[0x1]; 1498 u8 dtor[0x1]; 1499 u8 event_on_vhca_state_teardown_request[0x1]; 1500 u8 event_on_vhca_state_in_use[0x1]; 1501 u8 event_on_vhca_state_active[0x1]; 1502 u8 event_on_vhca_state_allocated[0x1]; 1503 u8 event_on_vhca_state_invalid[0x1]; 1504 u8 reserved_at_28[0x8]; 1505 u8 vhca_id[0x10]; 1506 1507 u8 reserved_at_40[0x40]; 1508 1509 u8 log_max_srq_sz[0x8]; 1510 u8 log_max_qp_sz[0x8]; 1511 u8 event_cap[0x1]; 1512 u8 reserved_at_91[0x2]; 1513 u8 isolate_vl_tc_new[0x1]; 1514 u8 reserved_at_94[0x4]; 1515 u8 prio_tag_required[0x1]; 1516 u8 reserved_at_99[0x2]; 1517 u8 log_max_qp[0x5]; 1518 1519 u8 reserved_at_a0[0x3]; 1520 u8 ece_support[0x1]; 1521 u8 reserved_at_a4[0x5]; 1522 u8 reg_c_preserve[0x1]; 1523 u8 reserved_at_aa[0x1]; 1524 u8 log_max_srq[0x5]; 1525 u8 reserved_at_b0[0x1]; 1526 u8 uplink_follow[0x1]; 1527 u8 ts_cqe_to_dest_cqn[0x1]; 1528 u8 reserved_at_b3[0x6]; 1529 u8 go_back_n[0x1]; 1530 u8 reserved_at_ba[0x6]; 1531 1532 u8 max_sgl_for_optimized_performance[0x8]; 1533 u8 log_max_cq_sz[0x8]; 1534 u8 relaxed_ordering_write_umr[0x1]; 1535 u8 relaxed_ordering_read_umr[0x1]; 1536 u8 reserved_at_d2[0x7]; 1537 u8 virtio_net_device_emualtion_manager[0x1]; 1538 u8 virtio_blk_device_emualtion_manager[0x1]; 1539 u8 log_max_cq[0x5]; 1540 1541 u8 log_max_eq_sz[0x8]; 1542 u8 relaxed_ordering_write[0x1]; 1543 u8 relaxed_ordering_read_pci_enabled[0x1]; 1544 u8 log_max_mkey[0x6]; 1545 u8 reserved_at_f0[0x6]; 1546 u8 terminate_scatter_list_mkey[0x1]; 1547 u8 repeated_mkey[0x1]; 1548 u8 dump_fill_mkey[0x1]; 1549 u8 reserved_at_f9[0x2]; 1550 u8 fast_teardown[0x1]; 1551 u8 log_max_eq[0x4]; 1552 1553 u8 max_indirection[0x8]; 1554 u8 fixed_buffer_size[0x1]; 1555 u8 log_max_mrw_sz[0x7]; 1556 u8 force_teardown[0x1]; 1557 u8 reserved_at_111[0x1]; 1558 u8 log_max_bsf_list_size[0x6]; 1559 u8 umr_extended_translation_offset[0x1]; 1560 u8 null_mkey[0x1]; 1561 u8 log_max_klm_list_size[0x6]; 1562 1563 u8 reserved_at_120[0x2]; 1564 u8 qpc_extension[0x1]; 1565 u8 reserved_at_123[0x7]; 1566 u8 log_max_ra_req_dc[0x6]; 1567 u8 reserved_at_130[0x2]; 1568 u8 eth_wqe_too_small[0x1]; 1569 u8 reserved_at_133[0x6]; 1570 u8 vnic_env_cq_overrun[0x1]; 1571 u8 log_max_ra_res_dc[0x6]; 1572 1573 u8 reserved_at_140[0x5]; 1574 u8 release_all_pages[0x1]; 1575 u8 must_not_use[0x1]; 1576 u8 reserved_at_147[0x2]; 1577 u8 roce_accl[0x1]; 1578 u8 log_max_ra_req_qp[0x6]; 1579 u8 reserved_at_150[0xa]; 1580 u8 log_max_ra_res_qp[0x6]; 1581 1582 u8 end_pad[0x1]; 1583 u8 cc_query_allowed[0x1]; 1584 u8 cc_modify_allowed[0x1]; 1585 u8 start_pad[0x1]; 1586 u8 cache_line_128byte[0x1]; 1587 u8 reserved_at_165[0x4]; 1588 u8 rts2rts_qp_counters_set_id[0x1]; 1589 u8 reserved_at_16a[0x2]; 1590 u8 vnic_env_int_rq_oob[0x1]; 1591 u8 sbcam_reg[0x1]; 1592 u8 reserved_at_16e[0x1]; 1593 u8 qcam_reg[0x1]; 1594 u8 gid_table_size[0x10]; 1595 1596 u8 out_of_seq_cnt[0x1]; 1597 u8 vport_counters[0x1]; 1598 u8 retransmission_q_counters[0x1]; 1599 u8 debug[0x1]; 1600 u8 modify_rq_counter_set_id[0x1]; 1601 u8 rq_delay_drop[0x1]; 1602 u8 max_qp_cnt[0xa]; 1603 u8 pkey_table_size[0x10]; 1604 1605 u8 vport_group_manager[0x1]; 1606 u8 vhca_group_manager[0x1]; 1607 u8 ib_virt[0x1]; 1608 u8 eth_virt[0x1]; 1609 u8 vnic_env_queue_counters[0x1]; 1610 u8 ets[0x1]; 1611 u8 nic_flow_table[0x1]; 1612 u8 eswitch_manager[0x1]; 1613 u8 device_memory[0x1]; 1614 u8 mcam_reg[0x1]; 1615 u8 pcam_reg[0x1]; 1616 u8 local_ca_ack_delay[0x5]; 1617 u8 port_module_event[0x1]; 1618 u8 enhanced_error_q_counters[0x1]; 1619 u8 ports_check[0x1]; 1620 u8 reserved_at_1b3[0x1]; 1621 u8 disable_link_up[0x1]; 1622 u8 beacon_led[0x1]; 1623 u8 port_type[0x2]; 1624 u8 num_ports[0x8]; 1625 1626 u8 reserved_at_1c0[0x1]; 1627 u8 pps[0x1]; 1628 u8 pps_modify[0x1]; 1629 u8 log_max_msg[0x5]; 1630 u8 reserved_at_1c8[0x4]; 1631 u8 max_tc[0x4]; 1632 u8 temp_warn_event[0x1]; 1633 u8 dcbx[0x1]; 1634 u8 general_notification_event[0x1]; 1635 u8 reserved_at_1d3[0x2]; 1636 u8 fpga[0x1]; 1637 u8 rol_s[0x1]; 1638 u8 rol_g[0x1]; 1639 u8 reserved_at_1d8[0x1]; 1640 u8 wol_s[0x1]; 1641 u8 wol_g[0x1]; 1642 u8 wol_a[0x1]; 1643 u8 wol_b[0x1]; 1644 u8 wol_m[0x1]; 1645 u8 wol_u[0x1]; 1646 u8 wol_p[0x1]; 1647 1648 u8 stat_rate_support[0x10]; 1649 u8 reserved_at_1f0[0x1]; 1650 u8 pci_sync_for_fw_update_event[0x1]; 1651 u8 reserved_at_1f2[0x6]; 1652 u8 init2_lag_tx_port_affinity[0x1]; 1653 u8 reserved_at_1fa[0x3]; 1654 u8 cqe_version[0x4]; 1655 1656 u8 compact_address_vector[0x1]; 1657 u8 striding_rq[0x1]; 1658 u8 reserved_at_202[0x1]; 1659 u8 ipoib_enhanced_offloads[0x1]; 1660 u8 ipoib_basic_offloads[0x1]; 1661 u8 reserved_at_205[0x1]; 1662 u8 repeated_block_disabled[0x1]; 1663 u8 umr_modify_entity_size_disabled[0x1]; 1664 u8 umr_modify_atomic_disabled[0x1]; 1665 u8 umr_indirect_mkey_disabled[0x1]; 1666 u8 umr_fence[0x2]; 1667 u8 dc_req_scat_data_cqe[0x1]; 1668 u8 reserved_at_20d[0x2]; 1669 u8 drain_sigerr[0x1]; 1670 u8 cmdif_checksum[0x2]; 1671 u8 sigerr_cqe[0x1]; 1672 u8 reserved_at_213[0x1]; 1673 u8 wq_signature[0x1]; 1674 u8 sctr_data_cqe[0x1]; 1675 u8 reserved_at_216[0x1]; 1676 u8 sho[0x1]; 1677 u8 tph[0x1]; 1678 u8 rf[0x1]; 1679 u8 dct[0x1]; 1680 u8 qos[0x1]; 1681 u8 eth_net_offloads[0x1]; 1682 u8 roce[0x1]; 1683 u8 atomic[0x1]; 1684 u8 reserved_at_21f[0x1]; 1685 1686 u8 cq_oi[0x1]; 1687 u8 cq_resize[0x1]; 1688 u8 cq_moderation[0x1]; 1689 u8 cq_period_mode_modify[0x1]; 1690 u8 reserved_at_224[0x2]; 1691 u8 cq_eq_remap[0x1]; 1692 u8 pg[0x1]; 1693 u8 block_lb_mc[0x1]; 1694 u8 reserved_at_229[0x1]; 1695 u8 scqe_break_moderation[0x1]; 1696 u8 cq_period_start_from_cqe[0x1]; 1697 u8 cd[0x1]; 1698 u8 reserved_at_22d[0x1]; 1699 u8 apm[0x1]; 1700 u8 vector_calc[0x1]; 1701 u8 umr_ptr_rlky[0x1]; 1702 u8 imaicl[0x1]; 1703 u8 qp_packet_based[0x1]; 1704 u8 reserved_at_233[0x3]; 1705 u8 qkv[0x1]; 1706 u8 pkv[0x1]; 1707 u8 set_deth_sqpn[0x1]; 1708 u8 reserved_at_239[0x3]; 1709 u8 xrc[0x1]; 1710 u8 ud[0x1]; 1711 u8 uc[0x1]; 1712 u8 rc[0x1]; 1713 1714 u8 uar_4k[0x1]; 1715 u8 reserved_at_241[0x7]; 1716 u8 fl_rc_qp_when_roce_disabled[0x1]; 1717 u8 regexp_params[0x1]; 1718 u8 uar_sz[0x6]; 1719 u8 port_selection_cap[0x1]; 1720 u8 reserved_at_251[0x1]; 1721 u8 umem_uid_0[0x1]; 1722 u8 reserved_at_253[0x5]; 1723 u8 log_pg_sz[0x8]; 1724 1725 u8 bf[0x1]; 1726 u8 driver_version[0x1]; 1727 u8 pad_tx_eth_packet[0x1]; 1728 u8 reserved_at_263[0x3]; 1729 u8 mkey_by_name[0x1]; 1730 u8 reserved_at_267[0x4]; 1731 1732 u8 log_bf_reg_size[0x5]; 1733 1734 u8 reserved_at_270[0x3]; 1735 u8 qp_error_syndrome[0x1]; 1736 u8 reserved_at_274[0x2]; 1737 u8 lag_dct[0x2]; 1738 u8 lag_tx_port_affinity[0x1]; 1739 u8 lag_native_fdb_selection[0x1]; 1740 u8 reserved_at_27a[0x1]; 1741 u8 lag_master[0x1]; 1742 u8 num_lag_ports[0x4]; 1743 1744 u8 reserved_at_280[0x10]; 1745 u8 max_wqe_sz_sq[0x10]; 1746 1747 u8 reserved_at_2a0[0xb]; 1748 u8 shampo[0x1]; 1749 u8 reserved_at_2ac[0x4]; 1750 u8 max_wqe_sz_rq[0x10]; 1751 1752 u8 max_flow_counter_31_16[0x10]; 1753 u8 max_wqe_sz_sq_dc[0x10]; 1754 1755 u8 reserved_at_2e0[0x7]; 1756 u8 max_qp_mcg[0x19]; 1757 1758 u8 reserved_at_300[0x10]; 1759 u8 flow_counter_bulk_alloc[0x8]; 1760 u8 log_max_mcg[0x8]; 1761 1762 u8 reserved_at_320[0x3]; 1763 u8 log_max_transport_domain[0x5]; 1764 u8 reserved_at_328[0x2]; 1765 u8 relaxed_ordering_read[0x1]; 1766 u8 log_max_pd[0x5]; 1767 u8 reserved_at_330[0x6]; 1768 u8 pci_sync_for_fw_update_with_driver_unload[0x1]; 1769 u8 vnic_env_cnt_steering_fail[0x1]; 1770 u8 vport_counter_local_loopback[0x1]; 1771 u8 q_counter_aggregation[0x1]; 1772 u8 q_counter_other_vport[0x1]; 1773 u8 log_max_xrcd[0x5]; 1774 1775 u8 nic_receive_steering_discard[0x1]; 1776 u8 receive_discard_vport_down[0x1]; 1777 u8 transmit_discard_vport_down[0x1]; 1778 u8 eq_overrun_count[0x1]; 1779 u8 reserved_at_344[0x1]; 1780 u8 invalid_command_count[0x1]; 1781 u8 quota_exceeded_count[0x1]; 1782 u8 reserved_at_347[0x1]; 1783 u8 log_max_flow_counter_bulk[0x8]; 1784 u8 max_flow_counter_15_0[0x10]; 1785 1786 1787 u8 reserved_at_360[0x3]; 1788 u8 log_max_rq[0x5]; 1789 u8 reserved_at_368[0x3]; 1790 u8 log_max_sq[0x5]; 1791 u8 reserved_at_370[0x3]; 1792 u8 log_max_tir[0x5]; 1793 u8 reserved_at_378[0x3]; 1794 u8 log_max_tis[0x5]; 1795 1796 u8 basic_cyclic_rcv_wqe[0x1]; 1797 u8 reserved_at_381[0x2]; 1798 u8 log_max_rmp[0x5]; 1799 u8 reserved_at_388[0x3]; 1800 u8 log_max_rqt[0x5]; 1801 u8 reserved_at_390[0x3]; 1802 u8 log_max_rqt_size[0x5]; 1803 u8 reserved_at_398[0x3]; 1804 u8 log_max_tis_per_sq[0x5]; 1805 1806 u8 ext_stride_num_range[0x1]; 1807 u8 roce_rw_supported[0x1]; 1808 u8 log_max_current_uc_list_wr_supported[0x1]; 1809 u8 log_max_stride_sz_rq[0x5]; 1810 u8 reserved_at_3a8[0x3]; 1811 u8 log_min_stride_sz_rq[0x5]; 1812 u8 reserved_at_3b0[0x3]; 1813 u8 log_max_stride_sz_sq[0x5]; 1814 u8 reserved_at_3b8[0x3]; 1815 u8 log_min_stride_sz_sq[0x5]; 1816 1817 u8 hairpin[0x1]; 1818 u8 reserved_at_3c1[0x2]; 1819 u8 log_max_hairpin_queues[0x5]; 1820 u8 reserved_at_3c8[0x3]; 1821 u8 log_max_hairpin_wq_data_sz[0x5]; 1822 u8 reserved_at_3d0[0x3]; 1823 u8 log_max_hairpin_num_packets[0x5]; 1824 u8 reserved_at_3d8[0x3]; 1825 u8 log_max_wq_sz[0x5]; 1826 1827 u8 nic_vport_change_event[0x1]; 1828 u8 disable_local_lb_uc[0x1]; 1829 u8 disable_local_lb_mc[0x1]; 1830 u8 log_min_hairpin_wq_data_sz[0x5]; 1831 u8 reserved_at_3e8[0x1]; 1832 u8 silent_mode[0x1]; 1833 u8 vhca_state[0x1]; 1834 u8 log_max_vlan_list[0x5]; 1835 u8 reserved_at_3f0[0x3]; 1836 u8 log_max_current_mc_list[0x5]; 1837 u8 reserved_at_3f8[0x3]; 1838 u8 log_max_current_uc_list[0x5]; 1839 1840 u8 general_obj_types[0x40]; 1841 1842 u8 sq_ts_format[0x2]; 1843 u8 rq_ts_format[0x2]; 1844 u8 steering_format_version[0x4]; 1845 u8 create_qp_start_hint[0x18]; 1846 1847 u8 reserved_at_460[0x1]; 1848 u8 ats[0x1]; 1849 u8 cross_vhca_rqt[0x1]; 1850 u8 log_max_uctx[0x5]; 1851 u8 reserved_at_468[0x1]; 1852 u8 crypto[0x1]; 1853 u8 ipsec_offload[0x1]; 1854 u8 log_max_umem[0x5]; 1855 u8 max_num_eqs[0x10]; 1856 1857 u8 reserved_at_480[0x1]; 1858 u8 tls_tx[0x1]; 1859 u8 tls_rx[0x1]; 1860 u8 log_max_l2_table[0x5]; 1861 u8 reserved_at_488[0x8]; 1862 u8 log_uar_page_sz[0x10]; 1863 1864 u8 reserved_at_4a0[0x20]; 1865 u8 device_frequency_mhz[0x20]; 1866 u8 device_frequency_khz[0x20]; 1867 1868 u8 reserved_at_500[0x20]; 1869 u8 num_of_uars_per_page[0x20]; 1870 1871 u8 flex_parser_protocols[0x20]; 1872 1873 u8 max_geneve_tlv_options[0x8]; 1874 u8 reserved_at_568[0x3]; 1875 u8 max_geneve_tlv_option_data_len[0x5]; 1876 u8 reserved_at_570[0x9]; 1877 u8 adv_virtualization[0x1]; 1878 u8 reserved_at_57a[0x6]; 1879 1880 u8 reserved_at_580[0xb]; 1881 u8 log_max_dci_stream_channels[0x5]; 1882 u8 reserved_at_590[0x3]; 1883 u8 log_max_dci_errored_streams[0x5]; 1884 u8 reserved_at_598[0x8]; 1885 1886 u8 reserved_at_5a0[0x10]; 1887 u8 enhanced_cqe_compression[0x1]; 1888 u8 reserved_at_5b1[0x2]; 1889 u8 log_max_dek[0x5]; 1890 u8 reserved_at_5b8[0x4]; 1891 u8 mini_cqe_resp_stride_index[0x1]; 1892 u8 cqe_128_always[0x1]; 1893 u8 cqe_compression_128[0x1]; 1894 u8 cqe_compression[0x1]; 1895 1896 u8 cqe_compression_timeout[0x10]; 1897 u8 cqe_compression_max_num[0x10]; 1898 1899 u8 reserved_at_5e0[0x8]; 1900 u8 flex_parser_id_gtpu_dw_0[0x4]; 1901 u8 reserved_at_5ec[0x4]; 1902 u8 tag_matching[0x1]; 1903 u8 rndv_offload_rc[0x1]; 1904 u8 rndv_offload_dc[0x1]; 1905 u8 log_tag_matching_list_sz[0x5]; 1906 u8 reserved_at_5f8[0x3]; 1907 u8 log_max_xrq[0x5]; 1908 1909 u8 affiliate_nic_vport_criteria[0x8]; 1910 u8 native_port_num[0x8]; 1911 u8 num_vhca_ports[0x8]; 1912 u8 flex_parser_id_gtpu_teid[0x4]; 1913 u8 reserved_at_61c[0x2]; 1914 u8 sw_owner_id[0x1]; 1915 u8 reserved_at_61f[0x1]; 1916 1917 u8 max_num_of_monitor_counters[0x10]; 1918 u8 num_ppcnt_monitor_counters[0x10]; 1919 1920 u8 max_num_sf[0x10]; 1921 u8 num_q_monitor_counters[0x10]; 1922 1923 u8 reserved_at_660[0x20]; 1924 1925 u8 sf[0x1]; 1926 u8 sf_set_partition[0x1]; 1927 u8 reserved_at_682[0x1]; 1928 u8 log_max_sf[0x5]; 1929 u8 apu[0x1]; 1930 u8 reserved_at_689[0x4]; 1931 u8 migration[0x1]; 1932 u8 reserved_at_68e[0x2]; 1933 u8 log_min_sf_size[0x8]; 1934 u8 max_num_sf_partitions[0x8]; 1935 1936 u8 uctx_cap[0x20]; 1937 1938 u8 reserved_at_6c0[0x4]; 1939 u8 flex_parser_id_geneve_tlv_option_0[0x4]; 1940 u8 flex_parser_id_icmp_dw1[0x4]; 1941 u8 flex_parser_id_icmp_dw0[0x4]; 1942 u8 flex_parser_id_icmpv6_dw1[0x4]; 1943 u8 flex_parser_id_icmpv6_dw0[0x4]; 1944 u8 flex_parser_id_outer_first_mpls_over_gre[0x4]; 1945 u8 flex_parser_id_outer_first_mpls_over_udp_label[0x4]; 1946 1947 u8 max_num_match_definer[0x10]; 1948 u8 sf_base_id[0x10]; 1949 1950 u8 flex_parser_id_gtpu_dw_2[0x4]; 1951 u8 flex_parser_id_gtpu_first_ext_dw_0[0x4]; 1952 u8 num_total_dynamic_vf_msix[0x18]; 1953 u8 reserved_at_720[0x14]; 1954 u8 dynamic_msix_table_size[0xc]; 1955 u8 reserved_at_740[0xc]; 1956 u8 min_dynamic_vf_msix_table_size[0x4]; 1957 u8 reserved_at_750[0x4]; 1958 u8 max_dynamic_vf_msix_table_size[0xc]; 1959 1960 u8 reserved_at_760[0x3]; 1961 u8 log_max_num_header_modify_argument[0x5]; 1962 u8 reserved_at_768[0x4]; 1963 u8 log_header_modify_argument_granularity[0x4]; 1964 u8 reserved_at_770[0x3]; 1965 u8 log_header_modify_argument_max_alloc[0x5]; 1966 u8 reserved_at_778[0x8]; 1967 1968 u8 vhca_tunnel_commands[0x40]; 1969 u8 match_definer_format_supported[0x40]; 1970 }; 1971 1972 enum { 1973 MLX5_CROSS_VHCA_OBJ_TO_OBJ_SUPPORTED_LOCAL_FLOW_TABLE_TO_REMOTE_FLOW_TABLE_MISS = 0x80000, 1974 MLX5_CROSS_VHCA_OBJ_TO_OBJ_SUPPORTED_LOCAL_FLOW_TABLE_ROOT_TO_REMOTE_FLOW_TABLE = (1ULL << 20), 1975 }; 1976 1977 enum { 1978 MLX5_ALLOWED_OBJ_FOR_OTHER_VHCA_ACCESS_FLOW_TABLE = 0x200, 1979 }; 1980 1981 struct mlx5_ifc_cmd_hca_cap_2_bits { 1982 u8 reserved_at_0[0x80]; 1983 1984 u8 migratable[0x1]; 1985 u8 reserved_at_81[0x1f]; 1986 1987 u8 max_reformat_insert_size[0x8]; 1988 u8 max_reformat_insert_offset[0x8]; 1989 u8 max_reformat_remove_size[0x8]; 1990 u8 max_reformat_remove_offset[0x8]; 1991 1992 u8 reserved_at_c0[0x8]; 1993 u8 migration_multi_load[0x1]; 1994 u8 migration_tracking_state[0x1]; 1995 u8 multiplane_qp_ud[0x1]; 1996 u8 reserved_at_cb[0x5]; 1997 u8 migration_in_chunks[0x1]; 1998 u8 reserved_at_d1[0x1]; 1999 u8 sf_eq_usage[0x1]; 2000 u8 reserved_at_d3[0xd]; 2001 2002 u8 cross_vhca_object_to_object_supported[0x20]; 2003 2004 u8 allowed_object_for_other_vhca_access[0x40]; 2005 2006 u8 reserved_at_140[0x60]; 2007 2008 u8 flow_table_type_2_type[0x8]; 2009 u8 reserved_at_1a8[0x3]; 2010 u8 log_min_mkey_entity_size[0x5]; 2011 u8 reserved_at_1b0[0x10]; 2012 2013 u8 reserved_at_1c0[0x60]; 2014 2015 u8 reserved_at_220[0x1]; 2016 u8 sw_vhca_id_valid[0x1]; 2017 u8 sw_vhca_id[0xe]; 2018 u8 reserved_at_230[0x10]; 2019 2020 u8 reserved_at_240[0xb]; 2021 u8 ts_cqe_metadata_size2wqe_counter[0x5]; 2022 u8 reserved_at_250[0x10]; 2023 2024 u8 reserved_at_260[0x120]; 2025 u8 reserved_at_380[0xb]; 2026 u8 min_mkey_log_entity_size_fixed_buffer[0x5]; 2027 u8 ec_vf_vport_base[0x10]; 2028 2029 u8 reserved_at_3a0[0x10]; 2030 u8 max_rqt_vhca_id[0x10]; 2031 2032 u8 reserved_at_3c0[0x20]; 2033 2034 u8 reserved_at_3e0[0x10]; 2035 u8 pcc_ifa2[0x1]; 2036 u8 reserved_at_3f1[0xf]; 2037 2038 u8 reserved_at_400[0x1]; 2039 u8 min_mkey_log_entity_size_fixed_buffer_valid[0x1]; 2040 u8 reserved_at_402[0x1e]; 2041 2042 u8 reserved_at_420[0x20]; 2043 2044 u8 reserved_at_440[0x8]; 2045 u8 max_num_eqs_24b[0x18]; 2046 u8 reserved_at_460[0x3a0]; 2047 }; 2048 2049 enum mlx5_ifc_flow_destination_type { 2050 MLX5_IFC_FLOW_DESTINATION_TYPE_VPORT = 0x0, 2051 MLX5_IFC_FLOW_DESTINATION_TYPE_FLOW_TABLE = 0x1, 2052 MLX5_IFC_FLOW_DESTINATION_TYPE_TIR = 0x2, 2053 MLX5_IFC_FLOW_DESTINATION_TYPE_FLOW_SAMPLER = 0x6, 2054 MLX5_IFC_FLOW_DESTINATION_TYPE_UPLINK = 0x8, 2055 MLX5_IFC_FLOW_DESTINATION_TYPE_TABLE_TYPE = 0xA, 2056 }; 2057 2058 enum mlx5_flow_table_miss_action { 2059 MLX5_FLOW_TABLE_MISS_ACTION_DEF, 2060 MLX5_FLOW_TABLE_MISS_ACTION_FWD, 2061 MLX5_FLOW_TABLE_MISS_ACTION_SWITCH_DOMAIN, 2062 }; 2063 2064 struct mlx5_ifc_dest_format_struct_bits { 2065 u8 destination_type[0x8]; 2066 u8 destination_id[0x18]; 2067 2068 u8 destination_eswitch_owner_vhca_id_valid[0x1]; 2069 u8 packet_reformat[0x1]; 2070 u8 reserved_at_22[0x6]; 2071 u8 destination_table_type[0x8]; 2072 u8 destination_eswitch_owner_vhca_id[0x10]; 2073 }; 2074 2075 struct mlx5_ifc_flow_counter_list_bits { 2076 u8 flow_counter_id[0x20]; 2077 2078 u8 reserved_at_20[0x20]; 2079 }; 2080 2081 struct mlx5_ifc_extended_dest_format_bits { 2082 struct mlx5_ifc_dest_format_struct_bits destination_entry; 2083 2084 u8 packet_reformat_id[0x20]; 2085 2086 u8 reserved_at_60[0x20]; 2087 }; 2088 2089 union mlx5_ifc_dest_format_struct_flow_counter_list_auto_bits { 2090 struct mlx5_ifc_extended_dest_format_bits extended_dest_format; 2091 struct mlx5_ifc_flow_counter_list_bits flow_counter_list; 2092 }; 2093 2094 struct mlx5_ifc_fte_match_param_bits { 2095 struct mlx5_ifc_fte_match_set_lyr_2_4_bits outer_headers; 2096 2097 struct mlx5_ifc_fte_match_set_misc_bits misc_parameters; 2098 2099 struct mlx5_ifc_fte_match_set_lyr_2_4_bits inner_headers; 2100 2101 struct mlx5_ifc_fte_match_set_misc2_bits misc_parameters_2; 2102 2103 struct mlx5_ifc_fte_match_set_misc3_bits misc_parameters_3; 2104 2105 struct mlx5_ifc_fte_match_set_misc4_bits misc_parameters_4; 2106 2107 struct mlx5_ifc_fte_match_set_misc5_bits misc_parameters_5; 2108 2109 u8 reserved_at_e00[0x200]; 2110 }; 2111 2112 enum { 2113 MLX5_RX_HASH_FIELD_SELECT_SELECTED_FIELDS_SRC_IP = 0x0, 2114 MLX5_RX_HASH_FIELD_SELECT_SELECTED_FIELDS_DST_IP = 0x1, 2115 MLX5_RX_HASH_FIELD_SELECT_SELECTED_FIELDS_L4_SPORT = 0x2, 2116 MLX5_RX_HASH_FIELD_SELECT_SELECTED_FIELDS_L4_DPORT = 0x3, 2117 MLX5_RX_HASH_FIELD_SELECT_SELECTED_FIELDS_IPSEC_SPI = 0x4, 2118 }; 2119 2120 struct mlx5_ifc_rx_hash_field_select_bits { 2121 u8 l3_prot_type[0x1]; 2122 u8 l4_prot_type[0x1]; 2123 u8 selected_fields[0x1e]; 2124 }; 2125 2126 enum { 2127 MLX5_WQ_WQ_TYPE_WQ_LINKED_LIST = 0x0, 2128 MLX5_WQ_WQ_TYPE_WQ_CYCLIC = 0x1, 2129 }; 2130 2131 enum { 2132 MLX5_WQ_END_PADDING_MODE_END_PAD_NONE = 0x0, 2133 MLX5_WQ_END_PADDING_MODE_END_PAD_ALIGN = 0x1, 2134 }; 2135 2136 struct mlx5_ifc_wq_bits { 2137 u8 wq_type[0x4]; 2138 u8 wq_signature[0x1]; 2139 u8 end_padding_mode[0x2]; 2140 u8 cd_slave[0x1]; 2141 u8 reserved_at_8[0x18]; 2142 2143 u8 hds_skip_first_sge[0x1]; 2144 u8 log2_hds_buf_size[0x3]; 2145 u8 reserved_at_24[0x7]; 2146 u8 page_offset[0x5]; 2147 u8 lwm[0x10]; 2148 2149 u8 reserved_at_40[0x8]; 2150 u8 pd[0x18]; 2151 2152 u8 reserved_at_60[0x8]; 2153 u8 uar_page[0x18]; 2154 2155 u8 dbr_addr[0x40]; 2156 2157 u8 hw_counter[0x20]; 2158 2159 u8 sw_counter[0x20]; 2160 2161 u8 reserved_at_100[0xc]; 2162 u8 log_wq_stride[0x4]; 2163 u8 reserved_at_110[0x3]; 2164 u8 log_wq_pg_sz[0x5]; 2165 u8 reserved_at_118[0x3]; 2166 u8 log_wq_sz[0x5]; 2167 2168 u8 dbr_umem_valid[0x1]; 2169 u8 wq_umem_valid[0x1]; 2170 u8 reserved_at_122[0x1]; 2171 u8 log_hairpin_num_packets[0x5]; 2172 u8 reserved_at_128[0x3]; 2173 u8 log_hairpin_data_sz[0x5]; 2174 2175 u8 reserved_at_130[0x4]; 2176 u8 log_wqe_num_of_strides[0x4]; 2177 u8 two_byte_shift_en[0x1]; 2178 u8 reserved_at_139[0x4]; 2179 u8 log_wqe_stride_size[0x3]; 2180 2181 u8 reserved_at_140[0x80]; 2182 2183 u8 headers_mkey[0x20]; 2184 2185 u8 shampo_enable[0x1]; 2186 u8 reserved_at_1e1[0x4]; 2187 u8 log_reservation_size[0x3]; 2188 u8 reserved_at_1e8[0x5]; 2189 u8 log_max_num_of_packets_per_reservation[0x3]; 2190 u8 reserved_at_1f0[0x6]; 2191 u8 log_headers_entry_size[0x2]; 2192 u8 reserved_at_1f8[0x4]; 2193 u8 log_headers_buffer_entry_num[0x4]; 2194 2195 u8 reserved_at_200[0x400]; 2196 2197 struct mlx5_ifc_cmd_pas_bits pas[]; 2198 }; 2199 2200 struct mlx5_ifc_rq_num_bits { 2201 u8 reserved_at_0[0x8]; 2202 u8 rq_num[0x18]; 2203 }; 2204 2205 struct mlx5_ifc_rq_vhca_bits { 2206 u8 reserved_at_0[0x8]; 2207 u8 rq_num[0x18]; 2208 u8 reserved_at_20[0x10]; 2209 u8 rq_vhca_id[0x10]; 2210 }; 2211 2212 struct mlx5_ifc_mac_address_layout_bits { 2213 u8 reserved_at_0[0x10]; 2214 u8 mac_addr_47_32[0x10]; 2215 2216 u8 mac_addr_31_0[0x20]; 2217 }; 2218 2219 struct mlx5_ifc_vlan_layout_bits { 2220 u8 reserved_at_0[0x14]; 2221 u8 vlan[0x0c]; 2222 2223 u8 reserved_at_20[0x20]; 2224 }; 2225 2226 struct mlx5_ifc_cong_control_r_roce_ecn_np_bits { 2227 u8 reserved_at_0[0xa0]; 2228 2229 u8 min_time_between_cnps[0x20]; 2230 2231 u8 reserved_at_c0[0x12]; 2232 u8 cnp_dscp[0x6]; 2233 u8 reserved_at_d8[0x4]; 2234 u8 cnp_prio_mode[0x1]; 2235 u8 cnp_802p_prio[0x3]; 2236 2237 u8 reserved_at_e0[0x720]; 2238 }; 2239 2240 struct mlx5_ifc_cong_control_r_roce_ecn_rp_bits { 2241 u8 reserved_at_0[0x60]; 2242 2243 u8 reserved_at_60[0x4]; 2244 u8 clamp_tgt_rate[0x1]; 2245 u8 reserved_at_65[0x3]; 2246 u8 clamp_tgt_rate_after_time_inc[0x1]; 2247 u8 reserved_at_69[0x17]; 2248 2249 u8 reserved_at_80[0x20]; 2250 2251 u8 rpg_time_reset[0x20]; 2252 2253 u8 rpg_byte_reset[0x20]; 2254 2255 u8 rpg_threshold[0x20]; 2256 2257 u8 rpg_max_rate[0x20]; 2258 2259 u8 rpg_ai_rate[0x20]; 2260 2261 u8 rpg_hai_rate[0x20]; 2262 2263 u8 rpg_gd[0x20]; 2264 2265 u8 rpg_min_dec_fac[0x20]; 2266 2267 u8 rpg_min_rate[0x20]; 2268 2269 u8 reserved_at_1c0[0xe0]; 2270 2271 u8 rate_to_set_on_first_cnp[0x20]; 2272 2273 u8 dce_tcp_g[0x20]; 2274 2275 u8 dce_tcp_rtt[0x20]; 2276 2277 u8 rate_reduce_monitor_period[0x20]; 2278 2279 u8 reserved_at_320[0x20]; 2280 2281 u8 initial_alpha_value[0x20]; 2282 2283 u8 reserved_at_360[0x4a0]; 2284 }; 2285 2286 struct mlx5_ifc_cong_control_r_roce_general_bits { 2287 u8 reserved_at_0[0x80]; 2288 2289 u8 reserved_at_80[0x10]; 2290 u8 rtt_resp_dscp_valid[0x1]; 2291 u8 reserved_at_91[0x9]; 2292 u8 rtt_resp_dscp[0x6]; 2293 2294 u8 reserved_at_a0[0x760]; 2295 }; 2296 2297 struct mlx5_ifc_cong_control_802_1qau_rp_bits { 2298 u8 reserved_at_0[0x80]; 2299 2300 u8 rppp_max_rps[0x20]; 2301 2302 u8 rpg_time_reset[0x20]; 2303 2304 u8 rpg_byte_reset[0x20]; 2305 2306 u8 rpg_threshold[0x20]; 2307 2308 u8 rpg_max_rate[0x20]; 2309 2310 u8 rpg_ai_rate[0x20]; 2311 2312 u8 rpg_hai_rate[0x20]; 2313 2314 u8 rpg_gd[0x20]; 2315 2316 u8 rpg_min_dec_fac[0x20]; 2317 2318 u8 rpg_min_rate[0x20]; 2319 2320 u8 reserved_at_1c0[0x640]; 2321 }; 2322 2323 enum { 2324 MLX5_RESIZE_FIELD_SELECT_RESIZE_FIELD_SELECT_LOG_CQ_SIZE = 0x1, 2325 MLX5_RESIZE_FIELD_SELECT_RESIZE_FIELD_SELECT_PAGE_OFFSET = 0x2, 2326 MLX5_RESIZE_FIELD_SELECT_RESIZE_FIELD_SELECT_LOG_PAGE_SIZE = 0x4, 2327 }; 2328 2329 struct mlx5_ifc_resize_field_select_bits { 2330 u8 resize_field_select[0x20]; 2331 }; 2332 2333 struct mlx5_ifc_resource_dump_bits { 2334 u8 more_dump[0x1]; 2335 u8 inline_dump[0x1]; 2336 u8 reserved_at_2[0xa]; 2337 u8 seq_num[0x4]; 2338 u8 segment_type[0x10]; 2339 2340 u8 reserved_at_20[0x10]; 2341 u8 vhca_id[0x10]; 2342 2343 u8 index1[0x20]; 2344 2345 u8 index2[0x20]; 2346 2347 u8 num_of_obj1[0x10]; 2348 u8 num_of_obj2[0x10]; 2349 2350 u8 reserved_at_a0[0x20]; 2351 2352 u8 device_opaque[0x40]; 2353 2354 u8 mkey[0x20]; 2355 2356 u8 size[0x20]; 2357 2358 u8 address[0x40]; 2359 2360 u8 inline_data[52][0x20]; 2361 }; 2362 2363 struct mlx5_ifc_resource_dump_menu_record_bits { 2364 u8 reserved_at_0[0x4]; 2365 u8 num_of_obj2_supports_active[0x1]; 2366 u8 num_of_obj2_supports_all[0x1]; 2367 u8 must_have_num_of_obj2[0x1]; 2368 u8 support_num_of_obj2[0x1]; 2369 u8 num_of_obj1_supports_active[0x1]; 2370 u8 num_of_obj1_supports_all[0x1]; 2371 u8 must_have_num_of_obj1[0x1]; 2372 u8 support_num_of_obj1[0x1]; 2373 u8 must_have_index2[0x1]; 2374 u8 support_index2[0x1]; 2375 u8 must_have_index1[0x1]; 2376 u8 support_index1[0x1]; 2377 u8 segment_type[0x10]; 2378 2379 u8 segment_name[4][0x20]; 2380 2381 u8 index1_name[4][0x20]; 2382 2383 u8 index2_name[4][0x20]; 2384 }; 2385 2386 struct mlx5_ifc_resource_dump_segment_header_bits { 2387 u8 length_dw[0x10]; 2388 u8 segment_type[0x10]; 2389 }; 2390 2391 struct mlx5_ifc_resource_dump_command_segment_bits { 2392 struct mlx5_ifc_resource_dump_segment_header_bits segment_header; 2393 2394 u8 segment_called[0x10]; 2395 u8 vhca_id[0x10]; 2396 2397 u8 index1[0x20]; 2398 2399 u8 index2[0x20]; 2400 2401 u8 num_of_obj1[0x10]; 2402 u8 num_of_obj2[0x10]; 2403 }; 2404 2405 struct mlx5_ifc_resource_dump_error_segment_bits { 2406 struct mlx5_ifc_resource_dump_segment_header_bits segment_header; 2407 2408 u8 reserved_at_20[0x10]; 2409 u8 syndrome_id[0x10]; 2410 2411 u8 reserved_at_40[0x40]; 2412 2413 u8 error[8][0x20]; 2414 }; 2415 2416 struct mlx5_ifc_resource_dump_info_segment_bits { 2417 struct mlx5_ifc_resource_dump_segment_header_bits segment_header; 2418 2419 u8 reserved_at_20[0x18]; 2420 u8 dump_version[0x8]; 2421 2422 u8 hw_version[0x20]; 2423 2424 u8 fw_version[0x20]; 2425 }; 2426 2427 struct mlx5_ifc_resource_dump_menu_segment_bits { 2428 struct mlx5_ifc_resource_dump_segment_header_bits segment_header; 2429 2430 u8 reserved_at_20[0x10]; 2431 u8 num_of_records[0x10]; 2432 2433 struct mlx5_ifc_resource_dump_menu_record_bits record[]; 2434 }; 2435 2436 struct mlx5_ifc_resource_dump_resource_segment_bits { 2437 struct mlx5_ifc_resource_dump_segment_header_bits segment_header; 2438 2439 u8 reserved_at_20[0x20]; 2440 2441 u8 index1[0x20]; 2442 2443 u8 index2[0x20]; 2444 2445 u8 payload[][0x20]; 2446 }; 2447 2448 struct mlx5_ifc_resource_dump_terminate_segment_bits { 2449 struct mlx5_ifc_resource_dump_segment_header_bits segment_header; 2450 }; 2451 2452 struct mlx5_ifc_menu_resource_dump_response_bits { 2453 struct mlx5_ifc_resource_dump_info_segment_bits info; 2454 struct mlx5_ifc_resource_dump_command_segment_bits cmd; 2455 struct mlx5_ifc_resource_dump_menu_segment_bits menu; 2456 struct mlx5_ifc_resource_dump_terminate_segment_bits terminate; 2457 }; 2458 2459 enum { 2460 MLX5_MODIFY_FIELD_SELECT_MODIFY_FIELD_SELECT_CQ_PERIOD = 0x1, 2461 MLX5_MODIFY_FIELD_SELECT_MODIFY_FIELD_SELECT_CQ_MAX_COUNT = 0x2, 2462 MLX5_MODIFY_FIELD_SELECT_MODIFY_FIELD_SELECT_OI = 0x4, 2463 MLX5_MODIFY_FIELD_SELECT_MODIFY_FIELD_SELECT_C_EQN = 0x8, 2464 }; 2465 2466 struct mlx5_ifc_modify_field_select_bits { 2467 u8 modify_field_select[0x20]; 2468 }; 2469 2470 struct mlx5_ifc_field_select_r_roce_np_bits { 2471 u8 field_select_r_roce_np[0x20]; 2472 }; 2473 2474 struct mlx5_ifc_field_select_r_roce_rp_bits { 2475 u8 field_select_r_roce_rp[0x20]; 2476 }; 2477 2478 enum { 2479 MLX5_FIELD_SELECT_802_1QAU_RP_FIELD_SELECT_8021QAURP_RPPP_MAX_RPS = 0x4, 2480 MLX5_FIELD_SELECT_802_1QAU_RP_FIELD_SELECT_8021QAURP_RPG_TIME_RESET = 0x8, 2481 MLX5_FIELD_SELECT_802_1QAU_RP_FIELD_SELECT_8021QAURP_RPG_BYTE_RESET = 0x10, 2482 MLX5_FIELD_SELECT_802_1QAU_RP_FIELD_SELECT_8021QAURP_RPG_THRESHOLD = 0x20, 2483 MLX5_FIELD_SELECT_802_1QAU_RP_FIELD_SELECT_8021QAURP_RPG_MAX_RATE = 0x40, 2484 MLX5_FIELD_SELECT_802_1QAU_RP_FIELD_SELECT_8021QAURP_RPG_AI_RATE = 0x80, 2485 MLX5_FIELD_SELECT_802_1QAU_RP_FIELD_SELECT_8021QAURP_RPG_HAI_RATE = 0x100, 2486 MLX5_FIELD_SELECT_802_1QAU_RP_FIELD_SELECT_8021QAURP_RPG_GD = 0x200, 2487 MLX5_FIELD_SELECT_802_1QAU_RP_FIELD_SELECT_8021QAURP_RPG_MIN_DEC_FAC = 0x400, 2488 MLX5_FIELD_SELECT_802_1QAU_RP_FIELD_SELECT_8021QAURP_RPG_MIN_RATE = 0x800, 2489 }; 2490 2491 struct mlx5_ifc_field_select_802_1qau_rp_bits { 2492 u8 field_select_8021qaurp[0x20]; 2493 }; 2494 2495 struct mlx5_ifc_phys_layer_cntrs_bits { 2496 u8 time_since_last_clear_high[0x20]; 2497 2498 u8 time_since_last_clear_low[0x20]; 2499 2500 u8 symbol_errors_high[0x20]; 2501 2502 u8 symbol_errors_low[0x20]; 2503 2504 u8 sync_headers_errors_high[0x20]; 2505 2506 u8 sync_headers_errors_low[0x20]; 2507 2508 u8 edpl_bip_errors_lane0_high[0x20]; 2509 2510 u8 edpl_bip_errors_lane0_low[0x20]; 2511 2512 u8 edpl_bip_errors_lane1_high[0x20]; 2513 2514 u8 edpl_bip_errors_lane1_low[0x20]; 2515 2516 u8 edpl_bip_errors_lane2_high[0x20]; 2517 2518 u8 edpl_bip_errors_lane2_low[0x20]; 2519 2520 u8 edpl_bip_errors_lane3_high[0x20]; 2521 2522 u8 edpl_bip_errors_lane3_low[0x20]; 2523 2524 u8 fc_fec_corrected_blocks_lane0_high[0x20]; 2525 2526 u8 fc_fec_corrected_blocks_lane0_low[0x20]; 2527 2528 u8 fc_fec_corrected_blocks_lane1_high[0x20]; 2529 2530 u8 fc_fec_corrected_blocks_lane1_low[0x20]; 2531 2532 u8 fc_fec_corrected_blocks_lane2_high[0x20]; 2533 2534 u8 fc_fec_corrected_blocks_lane2_low[0x20]; 2535 2536 u8 fc_fec_corrected_blocks_lane3_high[0x20]; 2537 2538 u8 fc_fec_corrected_blocks_lane3_low[0x20]; 2539 2540 u8 fc_fec_uncorrectable_blocks_lane0_high[0x20]; 2541 2542 u8 fc_fec_uncorrectable_blocks_lane0_low[0x20]; 2543 2544 u8 fc_fec_uncorrectable_blocks_lane1_high[0x20]; 2545 2546 u8 fc_fec_uncorrectable_blocks_lane1_low[0x20]; 2547 2548 u8 fc_fec_uncorrectable_blocks_lane2_high[0x20]; 2549 2550 u8 fc_fec_uncorrectable_blocks_lane2_low[0x20]; 2551 2552 u8 fc_fec_uncorrectable_blocks_lane3_high[0x20]; 2553 2554 u8 fc_fec_uncorrectable_blocks_lane3_low[0x20]; 2555 2556 u8 rs_fec_corrected_blocks_high[0x20]; 2557 2558 u8 rs_fec_corrected_blocks_low[0x20]; 2559 2560 u8 rs_fec_uncorrectable_blocks_high[0x20]; 2561 2562 u8 rs_fec_uncorrectable_blocks_low[0x20]; 2563 2564 u8 rs_fec_no_errors_blocks_high[0x20]; 2565 2566 u8 rs_fec_no_errors_blocks_low[0x20]; 2567 2568 u8 rs_fec_single_error_blocks_high[0x20]; 2569 2570 u8 rs_fec_single_error_blocks_low[0x20]; 2571 2572 u8 rs_fec_corrected_symbols_total_high[0x20]; 2573 2574 u8 rs_fec_corrected_symbols_total_low[0x20]; 2575 2576 u8 rs_fec_corrected_symbols_lane0_high[0x20]; 2577 2578 u8 rs_fec_corrected_symbols_lane0_low[0x20]; 2579 2580 u8 rs_fec_corrected_symbols_lane1_high[0x20]; 2581 2582 u8 rs_fec_corrected_symbols_lane1_low[0x20]; 2583 2584 u8 rs_fec_corrected_symbols_lane2_high[0x20]; 2585 2586 u8 rs_fec_corrected_symbols_lane2_low[0x20]; 2587 2588 u8 rs_fec_corrected_symbols_lane3_high[0x20]; 2589 2590 u8 rs_fec_corrected_symbols_lane3_low[0x20]; 2591 2592 u8 link_down_events[0x20]; 2593 2594 u8 successful_recovery_events[0x20]; 2595 2596 u8 reserved_at_640[0x180]; 2597 }; 2598 2599 struct mlx5_ifc_phys_layer_statistical_cntrs_bits { 2600 u8 time_since_last_clear_high[0x20]; 2601 2602 u8 time_since_last_clear_low[0x20]; 2603 2604 u8 phy_received_bits_high[0x20]; 2605 2606 u8 phy_received_bits_low[0x20]; 2607 2608 u8 phy_symbol_errors_high[0x20]; 2609 2610 u8 phy_symbol_errors_low[0x20]; 2611 2612 u8 phy_corrected_bits_high[0x20]; 2613 2614 u8 phy_corrected_bits_low[0x20]; 2615 2616 u8 phy_corrected_bits_lane0_high[0x20]; 2617 2618 u8 phy_corrected_bits_lane0_low[0x20]; 2619 2620 u8 phy_corrected_bits_lane1_high[0x20]; 2621 2622 u8 phy_corrected_bits_lane1_low[0x20]; 2623 2624 u8 phy_corrected_bits_lane2_high[0x20]; 2625 2626 u8 phy_corrected_bits_lane2_low[0x20]; 2627 2628 u8 phy_corrected_bits_lane3_high[0x20]; 2629 2630 u8 phy_corrected_bits_lane3_low[0x20]; 2631 2632 u8 reserved_at_200[0x5c0]; 2633 }; 2634 2635 struct mlx5_ifc_ib_port_cntrs_grp_data_layout_bits { 2636 u8 symbol_error_counter[0x10]; 2637 2638 u8 link_error_recovery_counter[0x8]; 2639 2640 u8 link_downed_counter[0x8]; 2641 2642 u8 port_rcv_errors[0x10]; 2643 2644 u8 port_rcv_remote_physical_errors[0x10]; 2645 2646 u8 port_rcv_switch_relay_errors[0x10]; 2647 2648 u8 port_xmit_discards[0x10]; 2649 2650 u8 port_xmit_constraint_errors[0x8]; 2651 2652 u8 port_rcv_constraint_errors[0x8]; 2653 2654 u8 reserved_at_70[0x8]; 2655 2656 u8 link_overrun_errors[0x8]; 2657 2658 u8 reserved_at_80[0x10]; 2659 2660 u8 vl_15_dropped[0x10]; 2661 2662 u8 reserved_at_a0[0x80]; 2663 2664 u8 port_xmit_wait[0x20]; 2665 }; 2666 2667 struct mlx5_ifc_ib_ext_port_cntrs_grp_data_layout_bits { 2668 u8 reserved_at_0[0x300]; 2669 2670 u8 port_xmit_data_high[0x20]; 2671 2672 u8 port_xmit_data_low[0x20]; 2673 2674 u8 port_rcv_data_high[0x20]; 2675 2676 u8 port_rcv_data_low[0x20]; 2677 2678 u8 port_xmit_pkts_high[0x20]; 2679 2680 u8 port_xmit_pkts_low[0x20]; 2681 2682 u8 port_rcv_pkts_high[0x20]; 2683 2684 u8 port_rcv_pkts_low[0x20]; 2685 2686 u8 reserved_at_400[0x80]; 2687 2688 u8 port_unicast_xmit_pkts_high[0x20]; 2689 2690 u8 port_unicast_xmit_pkts_low[0x20]; 2691 2692 u8 port_multicast_xmit_pkts_high[0x20]; 2693 2694 u8 port_multicast_xmit_pkts_low[0x20]; 2695 2696 u8 port_unicast_rcv_pkts_high[0x20]; 2697 2698 u8 port_unicast_rcv_pkts_low[0x20]; 2699 2700 u8 port_multicast_rcv_pkts_high[0x20]; 2701 2702 u8 port_multicast_rcv_pkts_low[0x20]; 2703 2704 u8 reserved_at_580[0x240]; 2705 }; 2706 2707 struct mlx5_ifc_eth_per_tc_prio_grp_data_layout_bits { 2708 u8 transmit_queue_high[0x20]; 2709 2710 u8 transmit_queue_low[0x20]; 2711 2712 u8 no_buffer_discard_uc_high[0x20]; 2713 2714 u8 no_buffer_discard_uc_low[0x20]; 2715 2716 u8 reserved_at_80[0x740]; 2717 }; 2718 2719 struct mlx5_ifc_eth_per_tc_congest_prio_grp_data_layout_bits { 2720 u8 wred_discard_high[0x20]; 2721 2722 u8 wred_discard_low[0x20]; 2723 2724 u8 ecn_marked_tc_high[0x20]; 2725 2726 u8 ecn_marked_tc_low[0x20]; 2727 2728 u8 reserved_at_80[0x740]; 2729 }; 2730 2731 struct mlx5_ifc_eth_per_prio_grp_data_layout_bits { 2732 u8 rx_octets_high[0x20]; 2733 2734 u8 rx_octets_low[0x20]; 2735 2736 u8 reserved_at_40[0xc0]; 2737 2738 u8 rx_frames_high[0x20]; 2739 2740 u8 rx_frames_low[0x20]; 2741 2742 u8 tx_octets_high[0x20]; 2743 2744 u8 tx_octets_low[0x20]; 2745 2746 u8 reserved_at_180[0xc0]; 2747 2748 u8 tx_frames_high[0x20]; 2749 2750 u8 tx_frames_low[0x20]; 2751 2752 u8 rx_pause_high[0x20]; 2753 2754 u8 rx_pause_low[0x20]; 2755 2756 u8 rx_pause_duration_high[0x20]; 2757 2758 u8 rx_pause_duration_low[0x20]; 2759 2760 u8 tx_pause_high[0x20]; 2761 2762 u8 tx_pause_low[0x20]; 2763 2764 u8 tx_pause_duration_high[0x20]; 2765 2766 u8 tx_pause_duration_low[0x20]; 2767 2768 u8 rx_pause_transition_high[0x20]; 2769 2770 u8 rx_pause_transition_low[0x20]; 2771 2772 u8 rx_discards_high[0x20]; 2773 2774 u8 rx_discards_low[0x20]; 2775 2776 u8 device_stall_minor_watermark_cnt_high[0x20]; 2777 2778 u8 device_stall_minor_watermark_cnt_low[0x20]; 2779 2780 u8 device_stall_critical_watermark_cnt_high[0x20]; 2781 2782 u8 device_stall_critical_watermark_cnt_low[0x20]; 2783 2784 u8 reserved_at_480[0x340]; 2785 }; 2786 2787 struct mlx5_ifc_eth_extended_cntrs_grp_data_layout_bits { 2788 u8 port_transmit_wait_high[0x20]; 2789 2790 u8 port_transmit_wait_low[0x20]; 2791 2792 u8 reserved_at_40[0x100]; 2793 2794 u8 rx_buffer_almost_full_high[0x20]; 2795 2796 u8 rx_buffer_almost_full_low[0x20]; 2797 2798 u8 rx_buffer_full_high[0x20]; 2799 2800 u8 rx_buffer_full_low[0x20]; 2801 2802 u8 rx_icrc_encapsulated_high[0x20]; 2803 2804 u8 rx_icrc_encapsulated_low[0x20]; 2805 2806 u8 reserved_at_200[0x5c0]; 2807 }; 2808 2809 struct mlx5_ifc_eth_3635_cntrs_grp_data_layout_bits { 2810 u8 dot3stats_alignment_errors_high[0x20]; 2811 2812 u8 dot3stats_alignment_errors_low[0x20]; 2813 2814 u8 dot3stats_fcs_errors_high[0x20]; 2815 2816 u8 dot3stats_fcs_errors_low[0x20]; 2817 2818 u8 dot3stats_single_collision_frames_high[0x20]; 2819 2820 u8 dot3stats_single_collision_frames_low[0x20]; 2821 2822 u8 dot3stats_multiple_collision_frames_high[0x20]; 2823 2824 u8 dot3stats_multiple_collision_frames_low[0x20]; 2825 2826 u8 dot3stats_sqe_test_errors_high[0x20]; 2827 2828 u8 dot3stats_sqe_test_errors_low[0x20]; 2829 2830 u8 dot3stats_deferred_transmissions_high[0x20]; 2831 2832 u8 dot3stats_deferred_transmissions_low[0x20]; 2833 2834 u8 dot3stats_late_collisions_high[0x20]; 2835 2836 u8 dot3stats_late_collisions_low[0x20]; 2837 2838 u8 dot3stats_excessive_collisions_high[0x20]; 2839 2840 u8 dot3stats_excessive_collisions_low[0x20]; 2841 2842 u8 dot3stats_internal_mac_transmit_errors_high[0x20]; 2843 2844 u8 dot3stats_internal_mac_transmit_errors_low[0x20]; 2845 2846 u8 dot3stats_carrier_sense_errors_high[0x20]; 2847 2848 u8 dot3stats_carrier_sense_errors_low[0x20]; 2849 2850 u8 dot3stats_frame_too_longs_high[0x20]; 2851 2852 u8 dot3stats_frame_too_longs_low[0x20]; 2853 2854 u8 dot3stats_internal_mac_receive_errors_high[0x20]; 2855 2856 u8 dot3stats_internal_mac_receive_errors_low[0x20]; 2857 2858 u8 dot3stats_symbol_errors_high[0x20]; 2859 2860 u8 dot3stats_symbol_errors_low[0x20]; 2861 2862 u8 dot3control_in_unknown_opcodes_high[0x20]; 2863 2864 u8 dot3control_in_unknown_opcodes_low[0x20]; 2865 2866 u8 dot3in_pause_frames_high[0x20]; 2867 2868 u8 dot3in_pause_frames_low[0x20]; 2869 2870 u8 dot3out_pause_frames_high[0x20]; 2871 2872 u8 dot3out_pause_frames_low[0x20]; 2873 2874 u8 reserved_at_400[0x3c0]; 2875 }; 2876 2877 struct mlx5_ifc_eth_2819_cntrs_grp_data_layout_bits { 2878 u8 ether_stats_drop_events_high[0x20]; 2879 2880 u8 ether_stats_drop_events_low[0x20]; 2881 2882 u8 ether_stats_octets_high[0x20]; 2883 2884 u8 ether_stats_octets_low[0x20]; 2885 2886 u8 ether_stats_pkts_high[0x20]; 2887 2888 u8 ether_stats_pkts_low[0x20]; 2889 2890 u8 ether_stats_broadcast_pkts_high[0x20]; 2891 2892 u8 ether_stats_broadcast_pkts_low[0x20]; 2893 2894 u8 ether_stats_multicast_pkts_high[0x20]; 2895 2896 u8 ether_stats_multicast_pkts_low[0x20]; 2897 2898 u8 ether_stats_crc_align_errors_high[0x20]; 2899 2900 u8 ether_stats_crc_align_errors_low[0x20]; 2901 2902 u8 ether_stats_undersize_pkts_high[0x20]; 2903 2904 u8 ether_stats_undersize_pkts_low[0x20]; 2905 2906 u8 ether_stats_oversize_pkts_high[0x20]; 2907 2908 u8 ether_stats_oversize_pkts_low[0x20]; 2909 2910 u8 ether_stats_fragments_high[0x20]; 2911 2912 u8 ether_stats_fragments_low[0x20]; 2913 2914 u8 ether_stats_jabbers_high[0x20]; 2915 2916 u8 ether_stats_jabbers_low[0x20]; 2917 2918 u8 ether_stats_collisions_high[0x20]; 2919 2920 u8 ether_stats_collisions_low[0x20]; 2921 2922 u8 ether_stats_pkts64octets_high[0x20]; 2923 2924 u8 ether_stats_pkts64octets_low[0x20]; 2925 2926 u8 ether_stats_pkts65to127octets_high[0x20]; 2927 2928 u8 ether_stats_pkts65to127octets_low[0x20]; 2929 2930 u8 ether_stats_pkts128to255octets_high[0x20]; 2931 2932 u8 ether_stats_pkts128to255octets_low[0x20]; 2933 2934 u8 ether_stats_pkts256to511octets_high[0x20]; 2935 2936 u8 ether_stats_pkts256to511octets_low[0x20]; 2937 2938 u8 ether_stats_pkts512to1023octets_high[0x20]; 2939 2940 u8 ether_stats_pkts512to1023octets_low[0x20]; 2941 2942 u8 ether_stats_pkts1024to1518octets_high[0x20]; 2943 2944 u8 ether_stats_pkts1024to1518octets_low[0x20]; 2945 2946 u8 ether_stats_pkts1519to2047octets_high[0x20]; 2947 2948 u8 ether_stats_pkts1519to2047octets_low[0x20]; 2949 2950 u8 ether_stats_pkts2048to4095octets_high[0x20]; 2951 2952 u8 ether_stats_pkts2048to4095octets_low[0x20]; 2953 2954 u8 ether_stats_pkts4096to8191octets_high[0x20]; 2955 2956 u8 ether_stats_pkts4096to8191octets_low[0x20]; 2957 2958 u8 ether_stats_pkts8192to10239octets_high[0x20]; 2959 2960 u8 ether_stats_pkts8192to10239octets_low[0x20]; 2961 2962 u8 reserved_at_540[0x280]; 2963 }; 2964 2965 struct mlx5_ifc_eth_2863_cntrs_grp_data_layout_bits { 2966 u8 if_in_octets_high[0x20]; 2967 2968 u8 if_in_octets_low[0x20]; 2969 2970 u8 if_in_ucast_pkts_high[0x20]; 2971 2972 u8 if_in_ucast_pkts_low[0x20]; 2973 2974 u8 if_in_discards_high[0x20]; 2975 2976 u8 if_in_discards_low[0x20]; 2977 2978 u8 if_in_errors_high[0x20]; 2979 2980 u8 if_in_errors_low[0x20]; 2981 2982 u8 if_in_unknown_protos_high[0x20]; 2983 2984 u8 if_in_unknown_protos_low[0x20]; 2985 2986 u8 if_out_octets_high[0x20]; 2987 2988 u8 if_out_octets_low[0x20]; 2989 2990 u8 if_out_ucast_pkts_high[0x20]; 2991 2992 u8 if_out_ucast_pkts_low[0x20]; 2993 2994 u8 if_out_discards_high[0x20]; 2995 2996 u8 if_out_discards_low[0x20]; 2997 2998 u8 if_out_errors_high[0x20]; 2999 3000 u8 if_out_errors_low[0x20]; 3001 3002 u8 if_in_multicast_pkts_high[0x20]; 3003 3004 u8 if_in_multicast_pkts_low[0x20]; 3005 3006 u8 if_in_broadcast_pkts_high[0x20]; 3007 3008 u8 if_in_broadcast_pkts_low[0x20]; 3009 3010 u8 if_out_multicast_pkts_high[0x20]; 3011 3012 u8 if_out_multicast_pkts_low[0x20]; 3013 3014 u8 if_out_broadcast_pkts_high[0x20]; 3015 3016 u8 if_out_broadcast_pkts_low[0x20]; 3017 3018 u8 reserved_at_340[0x480]; 3019 }; 3020 3021 struct mlx5_ifc_eth_802_3_cntrs_grp_data_layout_bits { 3022 u8 a_frames_transmitted_ok_high[0x20]; 3023 3024 u8 a_frames_transmitted_ok_low[0x20]; 3025 3026 u8 a_frames_received_ok_high[0x20]; 3027 3028 u8 a_frames_received_ok_low[0x20]; 3029 3030 u8 a_frame_check_sequence_errors_high[0x20]; 3031 3032 u8 a_frame_check_sequence_errors_low[0x20]; 3033 3034 u8 a_alignment_errors_high[0x20]; 3035 3036 u8 a_alignment_errors_low[0x20]; 3037 3038 u8 a_octets_transmitted_ok_high[0x20]; 3039 3040 u8 a_octets_transmitted_ok_low[0x20]; 3041 3042 u8 a_octets_received_ok_high[0x20]; 3043 3044 u8 a_octets_received_ok_low[0x20]; 3045 3046 u8 a_multicast_frames_xmitted_ok_high[0x20]; 3047 3048 u8 a_multicast_frames_xmitted_ok_low[0x20]; 3049 3050 u8 a_broadcast_frames_xmitted_ok_high[0x20]; 3051 3052 u8 a_broadcast_frames_xmitted_ok_low[0x20]; 3053 3054 u8 a_multicast_frames_received_ok_high[0x20]; 3055 3056 u8 a_multicast_frames_received_ok_low[0x20]; 3057 3058 u8 a_broadcast_frames_received_ok_high[0x20]; 3059 3060 u8 a_broadcast_frames_received_ok_low[0x20]; 3061 3062 u8 a_in_range_length_errors_high[0x20]; 3063 3064 u8 a_in_range_length_errors_low[0x20]; 3065 3066 u8 a_out_of_range_length_field_high[0x20]; 3067 3068 u8 a_out_of_range_length_field_low[0x20]; 3069 3070 u8 a_frame_too_long_errors_high[0x20]; 3071 3072 u8 a_frame_too_long_errors_low[0x20]; 3073 3074 u8 a_symbol_error_during_carrier_high[0x20]; 3075 3076 u8 a_symbol_error_during_carrier_low[0x20]; 3077 3078 u8 a_mac_control_frames_transmitted_high[0x20]; 3079 3080 u8 a_mac_control_frames_transmitted_low[0x20]; 3081 3082 u8 a_mac_control_frames_received_high[0x20]; 3083 3084 u8 a_mac_control_frames_received_low[0x20]; 3085 3086 u8 a_unsupported_opcodes_received_high[0x20]; 3087 3088 u8 a_unsupported_opcodes_received_low[0x20]; 3089 3090 u8 a_pause_mac_ctrl_frames_received_high[0x20]; 3091 3092 u8 a_pause_mac_ctrl_frames_received_low[0x20]; 3093 3094 u8 a_pause_mac_ctrl_frames_transmitted_high[0x20]; 3095 3096 u8 a_pause_mac_ctrl_frames_transmitted_low[0x20]; 3097 3098 u8 reserved_at_4c0[0x300]; 3099 }; 3100 3101 struct mlx5_ifc_pcie_perf_cntrs_grp_data_layout_bits { 3102 u8 life_time_counter_high[0x20]; 3103 3104 u8 life_time_counter_low[0x20]; 3105 3106 u8 rx_errors[0x20]; 3107 3108 u8 tx_errors[0x20]; 3109 3110 u8 l0_to_recovery_eieos[0x20]; 3111 3112 u8 l0_to_recovery_ts[0x20]; 3113 3114 u8 l0_to_recovery_framing[0x20]; 3115 3116 u8 l0_to_recovery_retrain[0x20]; 3117 3118 u8 crc_error_dllp[0x20]; 3119 3120 u8 crc_error_tlp[0x20]; 3121 3122 u8 tx_overflow_buffer_pkt_high[0x20]; 3123 3124 u8 tx_overflow_buffer_pkt_low[0x20]; 3125 3126 u8 outbound_stalled_reads[0x20]; 3127 3128 u8 outbound_stalled_writes[0x20]; 3129 3130 u8 outbound_stalled_reads_events[0x20]; 3131 3132 u8 outbound_stalled_writes_events[0x20]; 3133 3134 u8 reserved_at_200[0x5c0]; 3135 }; 3136 3137 struct mlx5_ifc_cmd_inter_comp_event_bits { 3138 u8 command_completion_vector[0x20]; 3139 3140 u8 reserved_at_20[0xc0]; 3141 }; 3142 3143 struct mlx5_ifc_stall_vl_event_bits { 3144 u8 reserved_at_0[0x18]; 3145 u8 port_num[0x1]; 3146 u8 reserved_at_19[0x3]; 3147 u8 vl[0x4]; 3148 3149 u8 reserved_at_20[0xa0]; 3150 }; 3151 3152 struct mlx5_ifc_db_bf_congestion_event_bits { 3153 u8 event_subtype[0x8]; 3154 u8 reserved_at_8[0x8]; 3155 u8 congestion_level[0x8]; 3156 u8 reserved_at_18[0x8]; 3157 3158 u8 reserved_at_20[0xa0]; 3159 }; 3160 3161 struct mlx5_ifc_gpio_event_bits { 3162 u8 reserved_at_0[0x60]; 3163 3164 u8 gpio_event_hi[0x20]; 3165 3166 u8 gpio_event_lo[0x20]; 3167 3168 u8 reserved_at_a0[0x40]; 3169 }; 3170 3171 struct mlx5_ifc_port_state_change_event_bits { 3172 u8 reserved_at_0[0x40]; 3173 3174 u8 port_num[0x4]; 3175 u8 reserved_at_44[0x1c]; 3176 3177 u8 reserved_at_60[0x80]; 3178 }; 3179 3180 struct mlx5_ifc_dropped_packet_logged_bits { 3181 u8 reserved_at_0[0xe0]; 3182 }; 3183 3184 struct mlx5_ifc_default_timeout_bits { 3185 u8 to_multiplier[0x3]; 3186 u8 reserved_at_3[0x9]; 3187 u8 to_value[0x14]; 3188 }; 3189 3190 struct mlx5_ifc_dtor_reg_bits { 3191 u8 reserved_at_0[0x20]; 3192 3193 struct mlx5_ifc_default_timeout_bits pcie_toggle_to; 3194 3195 u8 reserved_at_40[0x60]; 3196 3197 struct mlx5_ifc_default_timeout_bits health_poll_to; 3198 3199 struct mlx5_ifc_default_timeout_bits full_crdump_to; 3200 3201 struct mlx5_ifc_default_timeout_bits fw_reset_to; 3202 3203 struct mlx5_ifc_default_timeout_bits flush_on_err_to; 3204 3205 struct mlx5_ifc_default_timeout_bits pci_sync_update_to; 3206 3207 struct mlx5_ifc_default_timeout_bits tear_down_to; 3208 3209 struct mlx5_ifc_default_timeout_bits fsm_reactivate_to; 3210 3211 struct mlx5_ifc_default_timeout_bits reclaim_pages_to; 3212 3213 struct mlx5_ifc_default_timeout_bits reclaim_vfs_pages_to; 3214 3215 struct mlx5_ifc_default_timeout_bits reset_unload_to; 3216 3217 u8 reserved_at_1c0[0x20]; 3218 }; 3219 3220 enum { 3221 MLX5_CQ_ERROR_SYNDROME_CQ_OVERRUN = 0x1, 3222 MLX5_CQ_ERROR_SYNDROME_CQ_ACCESS_VIOLATION_ERROR = 0x2, 3223 }; 3224 3225 struct mlx5_ifc_cq_error_bits { 3226 u8 reserved_at_0[0x8]; 3227 u8 cqn[0x18]; 3228 3229 u8 reserved_at_20[0x20]; 3230 3231 u8 reserved_at_40[0x18]; 3232 u8 syndrome[0x8]; 3233 3234 u8 reserved_at_60[0x80]; 3235 }; 3236 3237 struct mlx5_ifc_rdma_page_fault_event_bits { 3238 u8 bytes_committed[0x20]; 3239 3240 u8 r_key[0x20]; 3241 3242 u8 reserved_at_40[0x10]; 3243 u8 packet_len[0x10]; 3244 3245 u8 rdma_op_len[0x20]; 3246 3247 u8 rdma_va[0x40]; 3248 3249 u8 reserved_at_c0[0x5]; 3250 u8 rdma[0x1]; 3251 u8 write[0x1]; 3252 u8 requestor[0x1]; 3253 u8 qp_number[0x18]; 3254 }; 3255 3256 struct mlx5_ifc_wqe_associated_page_fault_event_bits { 3257 u8 bytes_committed[0x20]; 3258 3259 u8 reserved_at_20[0x10]; 3260 u8 wqe_index[0x10]; 3261 3262 u8 reserved_at_40[0x10]; 3263 u8 len[0x10]; 3264 3265 u8 reserved_at_60[0x60]; 3266 3267 u8 reserved_at_c0[0x5]; 3268 u8 rdma[0x1]; 3269 u8 write_read[0x1]; 3270 u8 requestor[0x1]; 3271 u8 qpn[0x18]; 3272 }; 3273 3274 struct mlx5_ifc_qp_events_bits { 3275 u8 reserved_at_0[0xa0]; 3276 3277 u8 type[0x8]; 3278 u8 reserved_at_a8[0x18]; 3279 3280 u8 reserved_at_c0[0x8]; 3281 u8 qpn_rqn_sqn[0x18]; 3282 }; 3283 3284 struct mlx5_ifc_dct_events_bits { 3285 u8 reserved_at_0[0xc0]; 3286 3287 u8 reserved_at_c0[0x8]; 3288 u8 dct_number[0x18]; 3289 }; 3290 3291 struct mlx5_ifc_comp_event_bits { 3292 u8 reserved_at_0[0xc0]; 3293 3294 u8 reserved_at_c0[0x8]; 3295 u8 cq_number[0x18]; 3296 }; 3297 3298 enum { 3299 MLX5_QPC_STATE_RST = 0x0, 3300 MLX5_QPC_STATE_INIT = 0x1, 3301 MLX5_QPC_STATE_RTR = 0x2, 3302 MLX5_QPC_STATE_RTS = 0x3, 3303 MLX5_QPC_STATE_SQER = 0x4, 3304 MLX5_QPC_STATE_ERR = 0x6, 3305 MLX5_QPC_STATE_SQD = 0x7, 3306 MLX5_QPC_STATE_SUSPENDED = 0x9, 3307 }; 3308 3309 enum { 3310 MLX5_QPC_ST_RC = 0x0, 3311 MLX5_QPC_ST_UC = 0x1, 3312 MLX5_QPC_ST_UD = 0x2, 3313 MLX5_QPC_ST_XRC = 0x3, 3314 MLX5_QPC_ST_DCI = 0x5, 3315 MLX5_QPC_ST_QP0 = 0x7, 3316 MLX5_QPC_ST_QP1 = 0x8, 3317 MLX5_QPC_ST_RAW_DATAGRAM = 0x9, 3318 MLX5_QPC_ST_REG_UMR = 0xc, 3319 }; 3320 3321 enum { 3322 MLX5_QPC_PM_STATE_ARMED = 0x0, 3323 MLX5_QPC_PM_STATE_REARM = 0x1, 3324 MLX5_QPC_PM_STATE_RESERVED = 0x2, 3325 MLX5_QPC_PM_STATE_MIGRATED = 0x3, 3326 }; 3327 3328 enum { 3329 MLX5_QPC_OFFLOAD_TYPE_RNDV = 0x1, 3330 }; 3331 3332 enum { 3333 MLX5_QPC_END_PADDING_MODE_SCATTER_AS_IS = 0x0, 3334 MLX5_QPC_END_PADDING_MODE_PAD_TO_CACHE_LINE_ALIGNMENT = 0x1, 3335 }; 3336 3337 enum { 3338 MLX5_QPC_MTU_256_BYTES = 0x1, 3339 MLX5_QPC_MTU_512_BYTES = 0x2, 3340 MLX5_QPC_MTU_1K_BYTES = 0x3, 3341 MLX5_QPC_MTU_2K_BYTES = 0x4, 3342 MLX5_QPC_MTU_4K_BYTES = 0x5, 3343 MLX5_QPC_MTU_RAW_ETHERNET_QP = 0x7, 3344 }; 3345 3346 enum { 3347 MLX5_QPC_ATOMIC_MODE_IB_SPEC = 0x1, 3348 MLX5_QPC_ATOMIC_MODE_ONLY_8B = 0x2, 3349 MLX5_QPC_ATOMIC_MODE_UP_TO_8B = 0x3, 3350 MLX5_QPC_ATOMIC_MODE_UP_TO_16B = 0x4, 3351 MLX5_QPC_ATOMIC_MODE_UP_TO_32B = 0x5, 3352 MLX5_QPC_ATOMIC_MODE_UP_TO_64B = 0x6, 3353 MLX5_QPC_ATOMIC_MODE_UP_TO_128B = 0x7, 3354 MLX5_QPC_ATOMIC_MODE_UP_TO_256B = 0x8, 3355 }; 3356 3357 enum { 3358 MLX5_QPC_CS_REQ_DISABLE = 0x0, 3359 MLX5_QPC_CS_REQ_UP_TO_32B = 0x11, 3360 MLX5_QPC_CS_REQ_UP_TO_64B = 0x22, 3361 }; 3362 3363 enum { 3364 MLX5_QPC_CS_RES_DISABLE = 0x0, 3365 MLX5_QPC_CS_RES_UP_TO_32B = 0x1, 3366 MLX5_QPC_CS_RES_UP_TO_64B = 0x2, 3367 }; 3368 3369 enum { 3370 MLX5_TIMESTAMP_FORMAT_FREE_RUNNING = 0x0, 3371 MLX5_TIMESTAMP_FORMAT_DEFAULT = 0x1, 3372 MLX5_TIMESTAMP_FORMAT_REAL_TIME = 0x2, 3373 }; 3374 3375 struct mlx5_ifc_qpc_bits { 3376 u8 state[0x4]; 3377 u8 lag_tx_port_affinity[0x4]; 3378 u8 st[0x8]; 3379 u8 reserved_at_10[0x2]; 3380 u8 isolate_vl_tc[0x1]; 3381 u8 pm_state[0x2]; 3382 u8 reserved_at_15[0x1]; 3383 u8 req_e2e_credit_mode[0x2]; 3384 u8 offload_type[0x4]; 3385 u8 end_padding_mode[0x2]; 3386 u8 reserved_at_1e[0x2]; 3387 3388 u8 wq_signature[0x1]; 3389 u8 block_lb_mc[0x1]; 3390 u8 atomic_like_write_en[0x1]; 3391 u8 latency_sensitive[0x1]; 3392 u8 reserved_at_24[0x1]; 3393 u8 drain_sigerr[0x1]; 3394 u8 reserved_at_26[0x2]; 3395 u8 pd[0x18]; 3396 3397 u8 mtu[0x3]; 3398 u8 log_msg_max[0x5]; 3399 u8 reserved_at_48[0x1]; 3400 u8 log_rq_size[0x4]; 3401 u8 log_rq_stride[0x3]; 3402 u8 no_sq[0x1]; 3403 u8 log_sq_size[0x4]; 3404 u8 reserved_at_55[0x1]; 3405 u8 retry_mode[0x2]; 3406 u8 ts_format[0x2]; 3407 u8 reserved_at_5a[0x1]; 3408 u8 rlky[0x1]; 3409 u8 ulp_stateless_offload_mode[0x4]; 3410 3411 u8 counter_set_id[0x8]; 3412 u8 uar_page[0x18]; 3413 3414 u8 reserved_at_80[0x8]; 3415 u8 user_index[0x18]; 3416 3417 u8 reserved_at_a0[0x3]; 3418 u8 log_page_size[0x5]; 3419 u8 remote_qpn[0x18]; 3420 3421 struct mlx5_ifc_ads_bits primary_address_path; 3422 3423 struct mlx5_ifc_ads_bits secondary_address_path; 3424 3425 u8 log_ack_req_freq[0x4]; 3426 u8 reserved_at_384[0x4]; 3427 u8 log_sra_max[0x3]; 3428 u8 reserved_at_38b[0x2]; 3429 u8 retry_count[0x3]; 3430 u8 rnr_retry[0x3]; 3431 u8 reserved_at_393[0x1]; 3432 u8 fre[0x1]; 3433 u8 cur_rnr_retry[0x3]; 3434 u8 cur_retry_count[0x3]; 3435 u8 reserved_at_39b[0x5]; 3436 3437 u8 reserved_at_3a0[0x20]; 3438 3439 u8 reserved_at_3c0[0x8]; 3440 u8 next_send_psn[0x18]; 3441 3442 u8 reserved_at_3e0[0x3]; 3443 u8 log_num_dci_stream_channels[0x5]; 3444 u8 cqn_snd[0x18]; 3445 3446 u8 reserved_at_400[0x3]; 3447 u8 log_num_dci_errored_streams[0x5]; 3448 u8 deth_sqpn[0x18]; 3449 3450 u8 reserved_at_420[0x20]; 3451 3452 u8 reserved_at_440[0x8]; 3453 u8 last_acked_psn[0x18]; 3454 3455 u8 reserved_at_460[0x8]; 3456 u8 ssn[0x18]; 3457 3458 u8 reserved_at_480[0x8]; 3459 u8 log_rra_max[0x3]; 3460 u8 reserved_at_48b[0x1]; 3461 u8 atomic_mode[0x4]; 3462 u8 rre[0x1]; 3463 u8 rwe[0x1]; 3464 u8 rae[0x1]; 3465 u8 reserved_at_493[0x1]; 3466 u8 page_offset[0x6]; 3467 u8 reserved_at_49a[0x3]; 3468 u8 cd_slave_receive[0x1]; 3469 u8 cd_slave_send[0x1]; 3470 u8 cd_master[0x1]; 3471 3472 u8 reserved_at_4a0[0x3]; 3473 u8 min_rnr_nak[0x5]; 3474 u8 next_rcv_psn[0x18]; 3475 3476 u8 reserved_at_4c0[0x8]; 3477 u8 xrcd[0x18]; 3478 3479 u8 reserved_at_4e0[0x8]; 3480 u8 cqn_rcv[0x18]; 3481 3482 u8 dbr_addr[0x40]; 3483 3484 u8 q_key[0x20]; 3485 3486 u8 reserved_at_560[0x5]; 3487 u8 rq_type[0x3]; 3488 u8 srqn_rmpn_xrqn[0x18]; 3489 3490 u8 reserved_at_580[0x8]; 3491 u8 rmsn[0x18]; 3492 3493 u8 hw_sq_wqebb_counter[0x10]; 3494 u8 sw_sq_wqebb_counter[0x10]; 3495 3496 u8 hw_rq_counter[0x20]; 3497 3498 u8 sw_rq_counter[0x20]; 3499 3500 u8 reserved_at_600[0x20]; 3501 3502 u8 reserved_at_620[0xf]; 3503 u8 cgs[0x1]; 3504 u8 cs_req[0x8]; 3505 u8 cs_res[0x8]; 3506 3507 u8 dc_access_key[0x40]; 3508 3509 u8 reserved_at_680[0x3]; 3510 u8 dbr_umem_valid[0x1]; 3511 3512 u8 reserved_at_684[0xbc]; 3513 }; 3514 3515 struct mlx5_ifc_roce_addr_layout_bits { 3516 u8 source_l3_address[16][0x8]; 3517 3518 u8 reserved_at_80[0x3]; 3519 u8 vlan_valid[0x1]; 3520 u8 vlan_id[0xc]; 3521 u8 source_mac_47_32[0x10]; 3522 3523 u8 source_mac_31_0[0x20]; 3524 3525 u8 reserved_at_c0[0x14]; 3526 u8 roce_l3_type[0x4]; 3527 u8 roce_version[0x8]; 3528 3529 u8 reserved_at_e0[0x20]; 3530 }; 3531 3532 struct mlx5_ifc_crypto_cap_bits { 3533 u8 reserved_at_0[0x3]; 3534 u8 synchronize_dek[0x1]; 3535 u8 int_kek_manual[0x1]; 3536 u8 int_kek_auto[0x1]; 3537 u8 reserved_at_6[0x1a]; 3538 3539 u8 reserved_at_20[0x3]; 3540 u8 log_dek_max_alloc[0x5]; 3541 u8 reserved_at_28[0x3]; 3542 u8 log_max_num_deks[0x5]; 3543 u8 reserved_at_30[0x10]; 3544 3545 u8 reserved_at_40[0x20]; 3546 3547 u8 reserved_at_60[0x3]; 3548 u8 log_dek_granularity[0x5]; 3549 u8 reserved_at_68[0x3]; 3550 u8 log_max_num_int_kek[0x5]; 3551 u8 sw_wrapped_dek[0x10]; 3552 3553 u8 reserved_at_80[0x780]; 3554 }; 3555 3556 union mlx5_ifc_hca_cap_union_bits { 3557 struct mlx5_ifc_cmd_hca_cap_bits cmd_hca_cap; 3558 struct mlx5_ifc_cmd_hca_cap_2_bits cmd_hca_cap_2; 3559 struct mlx5_ifc_odp_cap_bits odp_cap; 3560 struct mlx5_ifc_atomic_caps_bits atomic_caps; 3561 struct mlx5_ifc_roce_cap_bits roce_cap; 3562 struct mlx5_ifc_per_protocol_networking_offload_caps_bits per_protocol_networking_offload_caps; 3563 struct mlx5_ifc_flow_table_nic_cap_bits flow_table_nic_cap; 3564 struct mlx5_ifc_flow_table_eswitch_cap_bits flow_table_eswitch_cap; 3565 struct mlx5_ifc_e_switch_cap_bits e_switch_cap; 3566 struct mlx5_ifc_port_selection_cap_bits port_selection_cap; 3567 struct mlx5_ifc_qos_cap_bits qos_cap; 3568 struct mlx5_ifc_debug_cap_bits debug_cap; 3569 struct mlx5_ifc_fpga_cap_bits fpga_cap; 3570 struct mlx5_ifc_tls_cap_bits tls_cap; 3571 struct mlx5_ifc_device_mem_cap_bits device_mem_cap; 3572 struct mlx5_ifc_virtio_emulation_cap_bits virtio_emulation_cap; 3573 struct mlx5_ifc_macsec_cap_bits macsec_cap; 3574 struct mlx5_ifc_crypto_cap_bits crypto_cap; 3575 struct mlx5_ifc_ipsec_cap_bits ipsec_cap; 3576 u8 reserved_at_0[0x8000]; 3577 }; 3578 3579 enum { 3580 MLX5_FLOW_CONTEXT_ACTION_ALLOW = 0x1, 3581 MLX5_FLOW_CONTEXT_ACTION_DROP = 0x2, 3582 MLX5_FLOW_CONTEXT_ACTION_FWD_DEST = 0x4, 3583 MLX5_FLOW_CONTEXT_ACTION_COUNT = 0x8, 3584 MLX5_FLOW_CONTEXT_ACTION_PACKET_REFORMAT = 0x10, 3585 MLX5_FLOW_CONTEXT_ACTION_DECAP = 0x20, 3586 MLX5_FLOW_CONTEXT_ACTION_MOD_HDR = 0x40, 3587 MLX5_FLOW_CONTEXT_ACTION_VLAN_POP = 0x80, 3588 MLX5_FLOW_CONTEXT_ACTION_VLAN_PUSH = 0x100, 3589 MLX5_FLOW_CONTEXT_ACTION_VLAN_POP_2 = 0x400, 3590 MLX5_FLOW_CONTEXT_ACTION_VLAN_PUSH_2 = 0x800, 3591 MLX5_FLOW_CONTEXT_ACTION_CRYPTO_DECRYPT = 0x1000, 3592 MLX5_FLOW_CONTEXT_ACTION_CRYPTO_ENCRYPT = 0x2000, 3593 MLX5_FLOW_CONTEXT_ACTION_EXECUTE_ASO = 0x4000, 3594 }; 3595 3596 enum { 3597 MLX5_FLOW_CONTEXT_FLOW_SOURCE_ANY_VPORT = 0x0, 3598 MLX5_FLOW_CONTEXT_FLOW_SOURCE_UPLINK = 0x1, 3599 MLX5_FLOW_CONTEXT_FLOW_SOURCE_LOCAL_VPORT = 0x2, 3600 }; 3601 3602 enum { 3603 MLX5_FLOW_CONTEXT_ENCRYPT_DECRYPT_TYPE_IPSEC = 0x0, 3604 MLX5_FLOW_CONTEXT_ENCRYPT_DECRYPT_TYPE_MACSEC = 0x1, 3605 }; 3606 3607 struct mlx5_ifc_vlan_bits { 3608 u8 ethtype[0x10]; 3609 u8 prio[0x3]; 3610 u8 cfi[0x1]; 3611 u8 vid[0xc]; 3612 }; 3613 3614 enum { 3615 MLX5_FLOW_METER_COLOR_RED = 0x0, 3616 MLX5_FLOW_METER_COLOR_YELLOW = 0x1, 3617 MLX5_FLOW_METER_COLOR_GREEN = 0x2, 3618 MLX5_FLOW_METER_COLOR_UNDEFINED = 0x3, 3619 }; 3620 3621 enum { 3622 MLX5_EXE_ASO_FLOW_METER = 0x2, 3623 }; 3624 3625 struct mlx5_ifc_exe_aso_ctrl_flow_meter_bits { 3626 u8 return_reg_id[0x4]; 3627 u8 aso_type[0x4]; 3628 u8 reserved_at_8[0x14]; 3629 u8 action[0x1]; 3630 u8 init_color[0x2]; 3631 u8 meter_id[0x1]; 3632 }; 3633 3634 union mlx5_ifc_exe_aso_ctrl { 3635 struct mlx5_ifc_exe_aso_ctrl_flow_meter_bits exe_aso_ctrl_flow_meter; 3636 }; 3637 3638 struct mlx5_ifc_execute_aso_bits { 3639 u8 valid[0x1]; 3640 u8 reserved_at_1[0x7]; 3641 u8 aso_object_id[0x18]; 3642 3643 union mlx5_ifc_exe_aso_ctrl exe_aso_ctrl; 3644 }; 3645 3646 struct mlx5_ifc_flow_context_bits { 3647 struct mlx5_ifc_vlan_bits push_vlan; 3648 3649 u8 group_id[0x20]; 3650 3651 u8 reserved_at_40[0x8]; 3652 u8 flow_tag[0x18]; 3653 3654 u8 reserved_at_60[0x10]; 3655 u8 action[0x10]; 3656 3657 u8 extended_destination[0x1]; 3658 u8 uplink_hairpin_en[0x1]; 3659 u8 flow_source[0x2]; 3660 u8 encrypt_decrypt_type[0x4]; 3661 u8 destination_list_size[0x18]; 3662 3663 u8 reserved_at_a0[0x8]; 3664 u8 flow_counter_list_size[0x18]; 3665 3666 u8 packet_reformat_id[0x20]; 3667 3668 u8 modify_header_id[0x20]; 3669 3670 struct mlx5_ifc_vlan_bits push_vlan_2; 3671 3672 u8 encrypt_decrypt_obj_id[0x20]; 3673 u8 reserved_at_140[0xc0]; 3674 3675 struct mlx5_ifc_fte_match_param_bits match_value; 3676 3677 struct mlx5_ifc_execute_aso_bits execute_aso[4]; 3678 3679 u8 reserved_at_1300[0x500]; 3680 3681 union mlx5_ifc_dest_format_struct_flow_counter_list_auto_bits destination[]; 3682 }; 3683 3684 enum { 3685 MLX5_XRC_SRQC_STATE_GOOD = 0x0, 3686 MLX5_XRC_SRQC_STATE_ERROR = 0x1, 3687 }; 3688 3689 struct mlx5_ifc_xrc_srqc_bits { 3690 u8 state[0x4]; 3691 u8 log_xrc_srq_size[0x4]; 3692 u8 reserved_at_8[0x18]; 3693 3694 u8 wq_signature[0x1]; 3695 u8 cont_srq[0x1]; 3696 u8 reserved_at_22[0x1]; 3697 u8 rlky[0x1]; 3698 u8 basic_cyclic_rcv_wqe[0x1]; 3699 u8 log_rq_stride[0x3]; 3700 u8 xrcd[0x18]; 3701 3702 u8 page_offset[0x6]; 3703 u8 reserved_at_46[0x1]; 3704 u8 dbr_umem_valid[0x1]; 3705 u8 cqn[0x18]; 3706 3707 u8 reserved_at_60[0x20]; 3708 3709 u8 user_index_equal_xrc_srqn[0x1]; 3710 u8 reserved_at_81[0x1]; 3711 u8 log_page_size[0x6]; 3712 u8 user_index[0x18]; 3713 3714 u8 reserved_at_a0[0x20]; 3715 3716 u8 reserved_at_c0[0x8]; 3717 u8 pd[0x18]; 3718 3719 u8 lwm[0x10]; 3720 u8 wqe_cnt[0x10]; 3721 3722 u8 reserved_at_100[0x40]; 3723 3724 u8 db_record_addr_h[0x20]; 3725 3726 u8 db_record_addr_l[0x1e]; 3727 u8 reserved_at_17e[0x2]; 3728 3729 u8 reserved_at_180[0x80]; 3730 }; 3731 3732 struct mlx5_ifc_vnic_diagnostic_statistics_bits { 3733 u8 counter_error_queues[0x20]; 3734 3735 u8 total_error_queues[0x20]; 3736 3737 u8 send_queue_priority_update_flow[0x20]; 3738 3739 u8 reserved_at_60[0x20]; 3740 3741 u8 nic_receive_steering_discard[0x40]; 3742 3743 u8 receive_discard_vport_down[0x40]; 3744 3745 u8 transmit_discard_vport_down[0x40]; 3746 3747 u8 async_eq_overrun[0x20]; 3748 3749 u8 comp_eq_overrun[0x20]; 3750 3751 u8 reserved_at_180[0x20]; 3752 3753 u8 invalid_command[0x20]; 3754 3755 u8 quota_exceeded_command[0x20]; 3756 3757 u8 internal_rq_out_of_buffer[0x20]; 3758 3759 u8 cq_overrun[0x20]; 3760 3761 u8 eth_wqe_too_small[0x20]; 3762 3763 u8 reserved_at_220[0xc0]; 3764 3765 u8 generated_pkt_steering_fail[0x40]; 3766 3767 u8 handled_pkt_steering_fail[0x40]; 3768 3769 u8 reserved_at_360[0xc80]; 3770 }; 3771 3772 struct mlx5_ifc_traffic_counter_bits { 3773 u8 packets[0x40]; 3774 3775 u8 octets[0x40]; 3776 }; 3777 3778 struct mlx5_ifc_tisc_bits { 3779 u8 strict_lag_tx_port_affinity[0x1]; 3780 u8 tls_en[0x1]; 3781 u8 reserved_at_2[0x2]; 3782 u8 lag_tx_port_affinity[0x04]; 3783 3784 u8 reserved_at_8[0x4]; 3785 u8 prio[0x4]; 3786 u8 reserved_at_10[0x10]; 3787 3788 u8 reserved_at_20[0x100]; 3789 3790 u8 reserved_at_120[0x8]; 3791 u8 transport_domain[0x18]; 3792 3793 u8 reserved_at_140[0x8]; 3794 u8 underlay_qpn[0x18]; 3795 3796 u8 reserved_at_160[0x8]; 3797 u8 pd[0x18]; 3798 3799 u8 reserved_at_180[0x380]; 3800 }; 3801 3802 enum { 3803 MLX5_TIRC_DISP_TYPE_DIRECT = 0x0, 3804 MLX5_TIRC_DISP_TYPE_INDIRECT = 0x1, 3805 }; 3806 3807 enum { 3808 MLX5_TIRC_PACKET_MERGE_MASK_IPV4_LRO = BIT(0), 3809 MLX5_TIRC_PACKET_MERGE_MASK_IPV6_LRO = BIT(1), 3810 }; 3811 3812 enum { 3813 MLX5_RX_HASH_FN_NONE = 0x0, 3814 MLX5_RX_HASH_FN_INVERTED_XOR8 = 0x1, 3815 MLX5_RX_HASH_FN_TOEPLITZ = 0x2, 3816 }; 3817 3818 enum { 3819 MLX5_TIRC_SELF_LB_BLOCK_BLOCK_UNICAST = 0x1, 3820 MLX5_TIRC_SELF_LB_BLOCK_BLOCK_MULTICAST = 0x2, 3821 }; 3822 3823 struct mlx5_ifc_tirc_bits { 3824 u8 reserved_at_0[0x20]; 3825 3826 u8 disp_type[0x4]; 3827 u8 tls_en[0x1]; 3828 u8 reserved_at_25[0x1b]; 3829 3830 u8 reserved_at_40[0x40]; 3831 3832 u8 reserved_at_80[0x4]; 3833 u8 lro_timeout_period_usecs[0x10]; 3834 u8 packet_merge_mask[0x4]; 3835 u8 lro_max_ip_payload_size[0x8]; 3836 3837 u8 reserved_at_a0[0x40]; 3838 3839 u8 reserved_at_e0[0x8]; 3840 u8 inline_rqn[0x18]; 3841 3842 u8 rx_hash_symmetric[0x1]; 3843 u8 reserved_at_101[0x1]; 3844 u8 tunneled_offload_en[0x1]; 3845 u8 reserved_at_103[0x5]; 3846 u8 indirect_table[0x18]; 3847 3848 u8 rx_hash_fn[0x4]; 3849 u8 reserved_at_124[0x2]; 3850 u8 self_lb_block[0x2]; 3851 u8 transport_domain[0x18]; 3852 3853 u8 rx_hash_toeplitz_key[10][0x20]; 3854 3855 struct mlx5_ifc_rx_hash_field_select_bits rx_hash_field_selector_outer; 3856 3857 struct mlx5_ifc_rx_hash_field_select_bits rx_hash_field_selector_inner; 3858 3859 u8 reserved_at_2c0[0x4c0]; 3860 }; 3861 3862 enum { 3863 MLX5_SRQC_STATE_GOOD = 0x0, 3864 MLX5_SRQC_STATE_ERROR = 0x1, 3865 }; 3866 3867 struct mlx5_ifc_srqc_bits { 3868 u8 state[0x4]; 3869 u8 log_srq_size[0x4]; 3870 u8 reserved_at_8[0x18]; 3871 3872 u8 wq_signature[0x1]; 3873 u8 cont_srq[0x1]; 3874 u8 reserved_at_22[0x1]; 3875 u8 rlky[0x1]; 3876 u8 reserved_at_24[0x1]; 3877 u8 log_rq_stride[0x3]; 3878 u8 xrcd[0x18]; 3879 3880 u8 page_offset[0x6]; 3881 u8 reserved_at_46[0x2]; 3882 u8 cqn[0x18]; 3883 3884 u8 reserved_at_60[0x20]; 3885 3886 u8 reserved_at_80[0x2]; 3887 u8 log_page_size[0x6]; 3888 u8 reserved_at_88[0x18]; 3889 3890 u8 reserved_at_a0[0x20]; 3891 3892 u8 reserved_at_c0[0x8]; 3893 u8 pd[0x18]; 3894 3895 u8 lwm[0x10]; 3896 u8 wqe_cnt[0x10]; 3897 3898 u8 reserved_at_100[0x40]; 3899 3900 u8 dbr_addr[0x40]; 3901 3902 u8 reserved_at_180[0x80]; 3903 }; 3904 3905 enum { 3906 MLX5_SQC_STATE_RST = 0x0, 3907 MLX5_SQC_STATE_RDY = 0x1, 3908 MLX5_SQC_STATE_ERR = 0x3, 3909 }; 3910 3911 struct mlx5_ifc_sqc_bits { 3912 u8 rlky[0x1]; 3913 u8 cd_master[0x1]; 3914 u8 fre[0x1]; 3915 u8 flush_in_error_en[0x1]; 3916 u8 allow_multi_pkt_send_wqe[0x1]; 3917 u8 min_wqe_inline_mode[0x3]; 3918 u8 state[0x4]; 3919 u8 reg_umr[0x1]; 3920 u8 allow_swp[0x1]; 3921 u8 hairpin[0x1]; 3922 u8 reserved_at_f[0xb]; 3923 u8 ts_format[0x2]; 3924 u8 reserved_at_1c[0x4]; 3925 3926 u8 reserved_at_20[0x8]; 3927 u8 user_index[0x18]; 3928 3929 u8 reserved_at_40[0x8]; 3930 u8 cqn[0x18]; 3931 3932 u8 reserved_at_60[0x8]; 3933 u8 hairpin_peer_rq[0x18]; 3934 3935 u8 reserved_at_80[0x10]; 3936 u8 hairpin_peer_vhca[0x10]; 3937 3938 u8 reserved_at_a0[0x20]; 3939 3940 u8 reserved_at_c0[0x8]; 3941 u8 ts_cqe_to_dest_cqn[0x18]; 3942 3943 u8 reserved_at_e0[0x10]; 3944 u8 packet_pacing_rate_limit_index[0x10]; 3945 u8 tis_lst_sz[0x10]; 3946 u8 qos_queue_group_id[0x10]; 3947 3948 u8 reserved_at_120[0x40]; 3949 3950 u8 reserved_at_160[0x8]; 3951 u8 tis_num_0[0x18]; 3952 3953 struct mlx5_ifc_wq_bits wq; 3954 }; 3955 3956 enum { 3957 SCHEDULING_CONTEXT_ELEMENT_TYPE_TSAR = 0x0, 3958 SCHEDULING_CONTEXT_ELEMENT_TYPE_VPORT = 0x1, 3959 SCHEDULING_CONTEXT_ELEMENT_TYPE_VPORT_TC = 0x2, 3960 SCHEDULING_CONTEXT_ELEMENT_TYPE_PARA_VPORT_TC = 0x3, 3961 SCHEDULING_CONTEXT_ELEMENT_TYPE_QUEUE_GROUP = 0x4, 3962 }; 3963 3964 enum { 3965 ELEMENT_TYPE_CAP_MASK_TSAR = 1 << 0, 3966 ELEMENT_TYPE_CAP_MASK_VPORT = 1 << 1, 3967 ELEMENT_TYPE_CAP_MASK_VPORT_TC = 1 << 2, 3968 ELEMENT_TYPE_CAP_MASK_PARA_VPORT_TC = 1 << 3, 3969 }; 3970 3971 struct mlx5_ifc_scheduling_context_bits { 3972 u8 element_type[0x8]; 3973 u8 reserved_at_8[0x18]; 3974 3975 u8 element_attributes[0x20]; 3976 3977 u8 parent_element_id[0x20]; 3978 3979 u8 reserved_at_60[0x40]; 3980 3981 u8 bw_share[0x20]; 3982 3983 u8 max_average_bw[0x20]; 3984 3985 u8 reserved_at_e0[0x120]; 3986 }; 3987 3988 struct mlx5_ifc_rqtc_bits { 3989 u8 reserved_at_0[0xa0]; 3990 3991 u8 reserved_at_a0[0x5]; 3992 u8 list_q_type[0x3]; 3993 u8 reserved_at_a8[0x8]; 3994 u8 rqt_max_size[0x10]; 3995 3996 u8 rq_vhca_id_format[0x1]; 3997 u8 reserved_at_c1[0xf]; 3998 u8 rqt_actual_size[0x10]; 3999 4000 u8 reserved_at_e0[0x6a0]; 4001 4002 union { 4003 DECLARE_FLEX_ARRAY(struct mlx5_ifc_rq_num_bits, rq_num); 4004 DECLARE_FLEX_ARRAY(struct mlx5_ifc_rq_vhca_bits, rq_vhca); 4005 }; 4006 }; 4007 4008 enum { 4009 MLX5_RQC_MEM_RQ_TYPE_MEMORY_RQ_INLINE = 0x0, 4010 MLX5_RQC_MEM_RQ_TYPE_MEMORY_RQ_RMP = 0x1, 4011 }; 4012 4013 enum { 4014 MLX5_RQC_STATE_RST = 0x0, 4015 MLX5_RQC_STATE_RDY = 0x1, 4016 MLX5_RQC_STATE_ERR = 0x3, 4017 }; 4018 4019 enum { 4020 MLX5_RQC_SHAMPO_NO_MATCH_ALIGNMENT_GRANULARITY_BYTE = 0x0, 4021 MLX5_RQC_SHAMPO_NO_MATCH_ALIGNMENT_GRANULARITY_STRIDE = 0x1, 4022 MLX5_RQC_SHAMPO_NO_MATCH_ALIGNMENT_GRANULARITY_PAGE = 0x2, 4023 }; 4024 4025 enum { 4026 MLX5_RQC_SHAMPO_MATCH_CRITERIA_TYPE_NO_MATCH = 0x0, 4027 MLX5_RQC_SHAMPO_MATCH_CRITERIA_TYPE_EXTENDED = 0x1, 4028 MLX5_RQC_SHAMPO_MATCH_CRITERIA_TYPE_FIVE_TUPLE = 0x2, 4029 }; 4030 4031 struct mlx5_ifc_rqc_bits { 4032 u8 rlky[0x1]; 4033 u8 delay_drop_en[0x1]; 4034 u8 scatter_fcs[0x1]; 4035 u8 vsd[0x1]; 4036 u8 mem_rq_type[0x4]; 4037 u8 state[0x4]; 4038 u8 reserved_at_c[0x1]; 4039 u8 flush_in_error_en[0x1]; 4040 u8 hairpin[0x1]; 4041 u8 reserved_at_f[0xb]; 4042 u8 ts_format[0x2]; 4043 u8 reserved_at_1c[0x4]; 4044 4045 u8 reserved_at_20[0x8]; 4046 u8 user_index[0x18]; 4047 4048 u8 reserved_at_40[0x8]; 4049 u8 cqn[0x18]; 4050 4051 u8 counter_set_id[0x8]; 4052 u8 reserved_at_68[0x18]; 4053 4054 u8 reserved_at_80[0x8]; 4055 u8 rmpn[0x18]; 4056 4057 u8 reserved_at_a0[0x8]; 4058 u8 hairpin_peer_sq[0x18]; 4059 4060 u8 reserved_at_c0[0x10]; 4061 u8 hairpin_peer_vhca[0x10]; 4062 4063 u8 reserved_at_e0[0x46]; 4064 u8 shampo_no_match_alignment_granularity[0x2]; 4065 u8 reserved_at_128[0x6]; 4066 u8 shampo_match_criteria_type[0x2]; 4067 u8 reservation_timeout[0x10]; 4068 4069 u8 reserved_at_140[0x40]; 4070 4071 struct mlx5_ifc_wq_bits wq; 4072 }; 4073 4074 enum { 4075 MLX5_RMPC_STATE_RDY = 0x1, 4076 MLX5_RMPC_STATE_ERR = 0x3, 4077 }; 4078 4079 struct mlx5_ifc_rmpc_bits { 4080 u8 reserved_at_0[0x8]; 4081 u8 state[0x4]; 4082 u8 reserved_at_c[0x14]; 4083 4084 u8 basic_cyclic_rcv_wqe[0x1]; 4085 u8 reserved_at_21[0x1f]; 4086 4087 u8 reserved_at_40[0x140]; 4088 4089 struct mlx5_ifc_wq_bits wq; 4090 }; 4091 4092 enum { 4093 VHCA_ID_TYPE_HW = 0, 4094 VHCA_ID_TYPE_SW = 1, 4095 }; 4096 4097 struct mlx5_ifc_nic_vport_context_bits { 4098 u8 reserved_at_0[0x5]; 4099 u8 min_wqe_inline_mode[0x3]; 4100 u8 reserved_at_8[0x15]; 4101 u8 disable_mc_local_lb[0x1]; 4102 u8 disable_uc_local_lb[0x1]; 4103 u8 roce_en[0x1]; 4104 4105 u8 arm_change_event[0x1]; 4106 u8 reserved_at_21[0x1a]; 4107 u8 event_on_mtu[0x1]; 4108 u8 event_on_promisc_change[0x1]; 4109 u8 event_on_vlan_change[0x1]; 4110 u8 event_on_mc_address_change[0x1]; 4111 u8 event_on_uc_address_change[0x1]; 4112 4113 u8 vhca_id_type[0x1]; 4114 u8 reserved_at_41[0xb]; 4115 u8 affiliation_criteria[0x4]; 4116 u8 affiliated_vhca_id[0x10]; 4117 4118 u8 reserved_at_60[0xa0]; 4119 4120 u8 reserved_at_100[0x1]; 4121 u8 sd_group[0x3]; 4122 u8 reserved_at_104[0x1c]; 4123 4124 u8 reserved_at_120[0x10]; 4125 u8 mtu[0x10]; 4126 4127 u8 system_image_guid[0x40]; 4128 u8 port_guid[0x40]; 4129 u8 node_guid[0x40]; 4130 4131 u8 reserved_at_200[0x140]; 4132 u8 qkey_violation_counter[0x10]; 4133 u8 reserved_at_350[0x430]; 4134 4135 u8 promisc_uc[0x1]; 4136 u8 promisc_mc[0x1]; 4137 u8 promisc_all[0x1]; 4138 u8 reserved_at_783[0x2]; 4139 u8 allowed_list_type[0x3]; 4140 u8 reserved_at_788[0xc]; 4141 u8 allowed_list_size[0xc]; 4142 4143 struct mlx5_ifc_mac_address_layout_bits permanent_address; 4144 4145 u8 reserved_at_7e0[0x20]; 4146 4147 u8 current_uc_mac_address[][0x40]; 4148 }; 4149 4150 enum { 4151 MLX5_MKC_ACCESS_MODE_PA = 0x0, 4152 MLX5_MKC_ACCESS_MODE_MTT = 0x1, 4153 MLX5_MKC_ACCESS_MODE_KLMS = 0x2, 4154 MLX5_MKC_ACCESS_MODE_KSM = 0x3, 4155 MLX5_MKC_ACCESS_MODE_SW_ICM = 0x4, 4156 MLX5_MKC_ACCESS_MODE_MEMIC = 0x5, 4157 }; 4158 4159 struct mlx5_ifc_mkc_bits { 4160 u8 reserved_at_0[0x1]; 4161 u8 free[0x1]; 4162 u8 reserved_at_2[0x1]; 4163 u8 access_mode_4_2[0x3]; 4164 u8 reserved_at_6[0x7]; 4165 u8 relaxed_ordering_write[0x1]; 4166 u8 reserved_at_e[0x1]; 4167 u8 small_fence_on_rdma_read_response[0x1]; 4168 u8 umr_en[0x1]; 4169 u8 a[0x1]; 4170 u8 rw[0x1]; 4171 u8 rr[0x1]; 4172 u8 lw[0x1]; 4173 u8 lr[0x1]; 4174 u8 access_mode_1_0[0x2]; 4175 u8 reserved_at_18[0x2]; 4176 u8 ma_translation_mode[0x2]; 4177 u8 reserved_at_1c[0x4]; 4178 4179 u8 qpn[0x18]; 4180 u8 mkey_7_0[0x8]; 4181 4182 u8 reserved_at_40[0x20]; 4183 4184 u8 length64[0x1]; 4185 u8 bsf_en[0x1]; 4186 u8 sync_umr[0x1]; 4187 u8 reserved_at_63[0x2]; 4188 u8 expected_sigerr_count[0x1]; 4189 u8 reserved_at_66[0x1]; 4190 u8 en_rinval[0x1]; 4191 u8 pd[0x18]; 4192 4193 u8 start_addr[0x40]; 4194 4195 u8 len[0x40]; 4196 4197 u8 bsf_octword_size[0x20]; 4198 4199 u8 reserved_at_120[0x80]; 4200 4201 u8 translations_octword_size[0x20]; 4202 4203 u8 reserved_at_1c0[0x19]; 4204 u8 relaxed_ordering_read[0x1]; 4205 u8 reserved_at_1d9[0x1]; 4206 u8 log_page_size[0x5]; 4207 4208 u8 reserved_at_1e0[0x20]; 4209 }; 4210 4211 struct mlx5_ifc_pkey_bits { 4212 u8 reserved_at_0[0x10]; 4213 u8 pkey[0x10]; 4214 }; 4215 4216 struct mlx5_ifc_array128_auto_bits { 4217 u8 array128_auto[16][0x8]; 4218 }; 4219 4220 struct mlx5_ifc_hca_vport_context_bits { 4221 u8 field_select[0x20]; 4222 4223 u8 reserved_at_20[0xe0]; 4224 4225 u8 sm_virt_aware[0x1]; 4226 u8 has_smi[0x1]; 4227 u8 has_raw[0x1]; 4228 u8 grh_required[0x1]; 4229 u8 reserved_at_104[0x4]; 4230 u8 num_port_plane[0x8]; 4231 u8 port_physical_state[0x4]; 4232 u8 vport_state_policy[0x4]; 4233 u8 port_state[0x4]; 4234 u8 vport_state[0x4]; 4235 4236 u8 reserved_at_120[0x20]; 4237 4238 u8 system_image_guid[0x40]; 4239 4240 u8 port_guid[0x40]; 4241 4242 u8 node_guid[0x40]; 4243 4244 u8 cap_mask1[0x20]; 4245 4246 u8 cap_mask1_field_select[0x20]; 4247 4248 u8 cap_mask2[0x20]; 4249 4250 u8 cap_mask2_field_select[0x20]; 4251 4252 u8 reserved_at_280[0x80]; 4253 4254 u8 lid[0x10]; 4255 u8 reserved_at_310[0x4]; 4256 u8 init_type_reply[0x4]; 4257 u8 lmc[0x3]; 4258 u8 subnet_timeout[0x5]; 4259 4260 u8 sm_lid[0x10]; 4261 u8 sm_sl[0x4]; 4262 u8 reserved_at_334[0xc]; 4263 4264 u8 qkey_violation_counter[0x10]; 4265 u8 pkey_violation_counter[0x10]; 4266 4267 u8 reserved_at_360[0xca0]; 4268 }; 4269 4270 struct mlx5_ifc_esw_vport_context_bits { 4271 u8 fdb_to_vport_reg_c[0x1]; 4272 u8 reserved_at_1[0x2]; 4273 u8 vport_svlan_strip[0x1]; 4274 u8 vport_cvlan_strip[0x1]; 4275 u8 vport_svlan_insert[0x1]; 4276 u8 vport_cvlan_insert[0x2]; 4277 u8 fdb_to_vport_reg_c_id[0x8]; 4278 u8 reserved_at_10[0x10]; 4279 4280 u8 reserved_at_20[0x20]; 4281 4282 u8 svlan_cfi[0x1]; 4283 u8 svlan_pcp[0x3]; 4284 u8 svlan_id[0xc]; 4285 u8 cvlan_cfi[0x1]; 4286 u8 cvlan_pcp[0x3]; 4287 u8 cvlan_id[0xc]; 4288 4289 u8 reserved_at_60[0x720]; 4290 4291 u8 sw_steering_vport_icm_address_rx[0x40]; 4292 4293 u8 sw_steering_vport_icm_address_tx[0x40]; 4294 }; 4295 4296 enum { 4297 MLX5_EQC_STATUS_OK = 0x0, 4298 MLX5_EQC_STATUS_EQ_WRITE_FAILURE = 0xa, 4299 }; 4300 4301 enum { 4302 MLX5_EQC_ST_ARMED = 0x9, 4303 MLX5_EQC_ST_FIRED = 0xa, 4304 }; 4305 4306 struct mlx5_ifc_eqc_bits { 4307 u8 status[0x4]; 4308 u8 reserved_at_4[0x9]; 4309 u8 ec[0x1]; 4310 u8 oi[0x1]; 4311 u8 reserved_at_f[0x5]; 4312 u8 st[0x4]; 4313 u8 reserved_at_18[0x8]; 4314 4315 u8 reserved_at_20[0x20]; 4316 4317 u8 reserved_at_40[0x14]; 4318 u8 page_offset[0x6]; 4319 u8 reserved_at_5a[0x6]; 4320 4321 u8 reserved_at_60[0x3]; 4322 u8 log_eq_size[0x5]; 4323 u8 uar_page[0x18]; 4324 4325 u8 reserved_at_80[0x20]; 4326 4327 u8 reserved_at_a0[0x14]; 4328 u8 intr[0xc]; 4329 4330 u8 reserved_at_c0[0x3]; 4331 u8 log_page_size[0x5]; 4332 u8 reserved_at_c8[0x18]; 4333 4334 u8 reserved_at_e0[0x60]; 4335 4336 u8 reserved_at_140[0x8]; 4337 u8 consumer_counter[0x18]; 4338 4339 u8 reserved_at_160[0x8]; 4340 u8 producer_counter[0x18]; 4341 4342 u8 reserved_at_180[0x80]; 4343 }; 4344 4345 enum { 4346 MLX5_DCTC_STATE_ACTIVE = 0x0, 4347 MLX5_DCTC_STATE_DRAINING = 0x1, 4348 MLX5_DCTC_STATE_DRAINED = 0x2, 4349 }; 4350 4351 enum { 4352 MLX5_DCTC_CS_RES_DISABLE = 0x0, 4353 MLX5_DCTC_CS_RES_NA = 0x1, 4354 MLX5_DCTC_CS_RES_UP_TO_64B = 0x2, 4355 }; 4356 4357 enum { 4358 MLX5_DCTC_MTU_256_BYTES = 0x1, 4359 MLX5_DCTC_MTU_512_BYTES = 0x2, 4360 MLX5_DCTC_MTU_1K_BYTES = 0x3, 4361 MLX5_DCTC_MTU_2K_BYTES = 0x4, 4362 MLX5_DCTC_MTU_4K_BYTES = 0x5, 4363 }; 4364 4365 struct mlx5_ifc_dctc_bits { 4366 u8 reserved_at_0[0x4]; 4367 u8 state[0x4]; 4368 u8 reserved_at_8[0x18]; 4369 4370 u8 reserved_at_20[0x8]; 4371 u8 user_index[0x18]; 4372 4373 u8 reserved_at_40[0x8]; 4374 u8 cqn[0x18]; 4375 4376 u8 counter_set_id[0x8]; 4377 u8 atomic_mode[0x4]; 4378 u8 rre[0x1]; 4379 u8 rwe[0x1]; 4380 u8 rae[0x1]; 4381 u8 atomic_like_write_en[0x1]; 4382 u8 latency_sensitive[0x1]; 4383 u8 rlky[0x1]; 4384 u8 free_ar[0x1]; 4385 u8 reserved_at_73[0xd]; 4386 4387 u8 reserved_at_80[0x8]; 4388 u8 cs_res[0x8]; 4389 u8 reserved_at_90[0x3]; 4390 u8 min_rnr_nak[0x5]; 4391 u8 reserved_at_98[0x8]; 4392 4393 u8 reserved_at_a0[0x8]; 4394 u8 srqn_xrqn[0x18]; 4395 4396 u8 reserved_at_c0[0x8]; 4397 u8 pd[0x18]; 4398 4399 u8 tclass[0x8]; 4400 u8 reserved_at_e8[0x4]; 4401 u8 flow_label[0x14]; 4402 4403 u8 dc_access_key[0x40]; 4404 4405 u8 reserved_at_140[0x5]; 4406 u8 mtu[0x3]; 4407 u8 port[0x8]; 4408 u8 pkey_index[0x10]; 4409 4410 u8 reserved_at_160[0x8]; 4411 u8 my_addr_index[0x8]; 4412 u8 reserved_at_170[0x8]; 4413 u8 hop_limit[0x8]; 4414 4415 u8 dc_access_key_violation_count[0x20]; 4416 4417 u8 reserved_at_1a0[0x14]; 4418 u8 dei_cfi[0x1]; 4419 u8 eth_prio[0x3]; 4420 u8 ecn[0x2]; 4421 u8 dscp[0x6]; 4422 4423 u8 reserved_at_1c0[0x20]; 4424 u8 ece[0x20]; 4425 }; 4426 4427 enum { 4428 MLX5_CQC_STATUS_OK = 0x0, 4429 MLX5_CQC_STATUS_CQ_OVERFLOW = 0x9, 4430 MLX5_CQC_STATUS_CQ_WRITE_FAIL = 0xa, 4431 }; 4432 4433 enum { 4434 MLX5_CQC_CQE_SZ_64_BYTES = 0x0, 4435 MLX5_CQC_CQE_SZ_128_BYTES = 0x1, 4436 }; 4437 4438 enum { 4439 MLX5_CQC_ST_SOLICITED_NOTIFICATION_REQUEST_ARMED = 0x6, 4440 MLX5_CQC_ST_NOTIFICATION_REQUEST_ARMED = 0x9, 4441 MLX5_CQC_ST_FIRED = 0xa, 4442 }; 4443 4444 enum mlx5_cq_period_mode { 4445 MLX5_CQ_PERIOD_MODE_START_FROM_EQE = 0x0, 4446 MLX5_CQ_PERIOD_MODE_START_FROM_CQE = 0x1, 4447 MLX5_CQ_PERIOD_NUM_MODES, 4448 }; 4449 4450 struct mlx5_ifc_cqc_bits { 4451 u8 status[0x4]; 4452 u8 reserved_at_4[0x2]; 4453 u8 dbr_umem_valid[0x1]; 4454 u8 apu_cq[0x1]; 4455 u8 cqe_sz[0x3]; 4456 u8 cc[0x1]; 4457 u8 reserved_at_c[0x1]; 4458 u8 scqe_break_moderation_en[0x1]; 4459 u8 oi[0x1]; 4460 u8 cq_period_mode[0x2]; 4461 u8 cqe_comp_en[0x1]; 4462 u8 mini_cqe_res_format[0x2]; 4463 u8 st[0x4]; 4464 u8 reserved_at_18[0x6]; 4465 u8 cqe_compression_layout[0x2]; 4466 4467 u8 reserved_at_20[0x20]; 4468 4469 u8 reserved_at_40[0x14]; 4470 u8 page_offset[0x6]; 4471 u8 reserved_at_5a[0x6]; 4472 4473 u8 reserved_at_60[0x3]; 4474 u8 log_cq_size[0x5]; 4475 u8 uar_page[0x18]; 4476 4477 u8 reserved_at_80[0x4]; 4478 u8 cq_period[0xc]; 4479 u8 cq_max_count[0x10]; 4480 4481 u8 c_eqn_or_apu_element[0x20]; 4482 4483 u8 reserved_at_c0[0x3]; 4484 u8 log_page_size[0x5]; 4485 u8 reserved_at_c8[0x18]; 4486 4487 u8 reserved_at_e0[0x20]; 4488 4489 u8 reserved_at_100[0x8]; 4490 u8 last_notified_index[0x18]; 4491 4492 u8 reserved_at_120[0x8]; 4493 u8 last_solicit_index[0x18]; 4494 4495 u8 reserved_at_140[0x8]; 4496 u8 consumer_counter[0x18]; 4497 4498 u8 reserved_at_160[0x8]; 4499 u8 producer_counter[0x18]; 4500 4501 u8 reserved_at_180[0x40]; 4502 4503 u8 dbr_addr[0x40]; 4504 }; 4505 4506 union mlx5_ifc_cong_control_roce_ecn_auto_bits { 4507 struct mlx5_ifc_cong_control_802_1qau_rp_bits cong_control_802_1qau_rp; 4508 struct mlx5_ifc_cong_control_r_roce_ecn_rp_bits cong_control_r_roce_ecn_rp; 4509 struct mlx5_ifc_cong_control_r_roce_ecn_np_bits cong_control_r_roce_ecn_np; 4510 struct mlx5_ifc_cong_control_r_roce_general_bits cong_control_r_roce_general; 4511 u8 reserved_at_0[0x800]; 4512 }; 4513 4514 struct mlx5_ifc_query_adapter_param_block_bits { 4515 u8 reserved_at_0[0xc0]; 4516 4517 u8 reserved_at_c0[0x8]; 4518 u8 ieee_vendor_id[0x18]; 4519 4520 u8 reserved_at_e0[0x10]; 4521 u8 vsd_vendor_id[0x10]; 4522 4523 u8 vsd[208][0x8]; 4524 4525 u8 vsd_contd_psid[16][0x8]; 4526 }; 4527 4528 enum { 4529 MLX5_XRQC_STATE_GOOD = 0x0, 4530 MLX5_XRQC_STATE_ERROR = 0x1, 4531 }; 4532 4533 enum { 4534 MLX5_XRQC_TOPOLOGY_NO_SPECIAL_TOPOLOGY = 0x0, 4535 MLX5_XRQC_TOPOLOGY_TAG_MATCHING = 0x1, 4536 }; 4537 4538 enum { 4539 MLX5_XRQC_OFFLOAD_RNDV = 0x1, 4540 }; 4541 4542 struct mlx5_ifc_tag_matching_topology_context_bits { 4543 u8 log_matching_list_sz[0x4]; 4544 u8 reserved_at_4[0xc]; 4545 u8 append_next_index[0x10]; 4546 4547 u8 sw_phase_cnt[0x10]; 4548 u8 hw_phase_cnt[0x10]; 4549 4550 u8 reserved_at_40[0x40]; 4551 }; 4552 4553 struct mlx5_ifc_xrqc_bits { 4554 u8 state[0x4]; 4555 u8 rlkey[0x1]; 4556 u8 reserved_at_5[0xf]; 4557 u8 topology[0x4]; 4558 u8 reserved_at_18[0x4]; 4559 u8 offload[0x4]; 4560 4561 u8 reserved_at_20[0x8]; 4562 u8 user_index[0x18]; 4563 4564 u8 reserved_at_40[0x8]; 4565 u8 cqn[0x18]; 4566 4567 u8 reserved_at_60[0xa0]; 4568 4569 struct mlx5_ifc_tag_matching_topology_context_bits tag_matching_topology_context; 4570 4571 u8 reserved_at_180[0x280]; 4572 4573 struct mlx5_ifc_wq_bits wq; 4574 }; 4575 4576 union mlx5_ifc_modify_field_select_resize_field_select_auto_bits { 4577 struct mlx5_ifc_modify_field_select_bits modify_field_select; 4578 struct mlx5_ifc_resize_field_select_bits resize_field_select; 4579 u8 reserved_at_0[0x20]; 4580 }; 4581 4582 union mlx5_ifc_field_select_802_1_r_roce_auto_bits { 4583 struct mlx5_ifc_field_select_802_1qau_rp_bits field_select_802_1qau_rp; 4584 struct mlx5_ifc_field_select_r_roce_rp_bits field_select_r_roce_rp; 4585 struct mlx5_ifc_field_select_r_roce_np_bits field_select_r_roce_np; 4586 u8 reserved_at_0[0x20]; 4587 }; 4588 4589 union mlx5_ifc_eth_cntrs_grp_data_layout_auto_bits { 4590 struct mlx5_ifc_eth_802_3_cntrs_grp_data_layout_bits eth_802_3_cntrs_grp_data_layout; 4591 struct mlx5_ifc_eth_2863_cntrs_grp_data_layout_bits eth_2863_cntrs_grp_data_layout; 4592 struct mlx5_ifc_eth_2819_cntrs_grp_data_layout_bits eth_2819_cntrs_grp_data_layout; 4593 struct mlx5_ifc_eth_3635_cntrs_grp_data_layout_bits eth_3635_cntrs_grp_data_layout; 4594 struct mlx5_ifc_eth_extended_cntrs_grp_data_layout_bits eth_extended_cntrs_grp_data_layout; 4595 struct mlx5_ifc_eth_per_prio_grp_data_layout_bits eth_per_prio_grp_data_layout; 4596 struct mlx5_ifc_eth_per_tc_prio_grp_data_layout_bits eth_per_tc_prio_grp_data_layout; 4597 struct mlx5_ifc_eth_per_tc_congest_prio_grp_data_layout_bits eth_per_tc_congest_prio_grp_data_layout; 4598 struct mlx5_ifc_ib_port_cntrs_grp_data_layout_bits ib_port_cntrs_grp_data_layout; 4599 struct mlx5_ifc_ib_ext_port_cntrs_grp_data_layout_bits ib_ext_port_cntrs_grp_data_layout; 4600 struct mlx5_ifc_phys_layer_cntrs_bits phys_layer_cntrs; 4601 struct mlx5_ifc_phys_layer_statistical_cntrs_bits phys_layer_statistical_cntrs; 4602 u8 reserved_at_0[0x7c0]; 4603 }; 4604 4605 union mlx5_ifc_pcie_cntrs_grp_data_layout_auto_bits { 4606 struct mlx5_ifc_pcie_perf_cntrs_grp_data_layout_bits pcie_perf_cntrs_grp_data_layout; 4607 u8 reserved_at_0[0x7c0]; 4608 }; 4609 4610 union mlx5_ifc_event_auto_bits { 4611 struct mlx5_ifc_comp_event_bits comp_event; 4612 struct mlx5_ifc_dct_events_bits dct_events; 4613 struct mlx5_ifc_qp_events_bits qp_events; 4614 struct mlx5_ifc_wqe_associated_page_fault_event_bits wqe_associated_page_fault_event; 4615 struct mlx5_ifc_rdma_page_fault_event_bits rdma_page_fault_event; 4616 struct mlx5_ifc_cq_error_bits cq_error; 4617 struct mlx5_ifc_dropped_packet_logged_bits dropped_packet_logged; 4618 struct mlx5_ifc_port_state_change_event_bits port_state_change_event; 4619 struct mlx5_ifc_gpio_event_bits gpio_event; 4620 struct mlx5_ifc_db_bf_congestion_event_bits db_bf_congestion_event; 4621 struct mlx5_ifc_stall_vl_event_bits stall_vl_event; 4622 struct mlx5_ifc_cmd_inter_comp_event_bits cmd_inter_comp_event; 4623 u8 reserved_at_0[0xe0]; 4624 }; 4625 4626 struct mlx5_ifc_health_buffer_bits { 4627 u8 reserved_at_0[0x100]; 4628 4629 u8 assert_existptr[0x20]; 4630 4631 u8 assert_callra[0x20]; 4632 4633 u8 reserved_at_140[0x20]; 4634 4635 u8 time[0x20]; 4636 4637 u8 fw_version[0x20]; 4638 4639 u8 hw_id[0x20]; 4640 4641 u8 rfr[0x1]; 4642 u8 reserved_at_1c1[0x3]; 4643 u8 valid[0x1]; 4644 u8 severity[0x3]; 4645 u8 reserved_at_1c8[0x18]; 4646 4647 u8 irisc_index[0x8]; 4648 u8 synd[0x8]; 4649 u8 ext_synd[0x10]; 4650 }; 4651 4652 struct mlx5_ifc_register_loopback_control_bits { 4653 u8 no_lb[0x1]; 4654 u8 reserved_at_1[0x7]; 4655 u8 port[0x8]; 4656 u8 reserved_at_10[0x10]; 4657 4658 u8 reserved_at_20[0x60]; 4659 }; 4660 4661 struct mlx5_ifc_vport_tc_element_bits { 4662 u8 traffic_class[0x4]; 4663 u8 reserved_at_4[0xc]; 4664 u8 vport_number[0x10]; 4665 }; 4666 4667 struct mlx5_ifc_vport_element_bits { 4668 u8 reserved_at_0[0x10]; 4669 u8 vport_number[0x10]; 4670 }; 4671 4672 enum { 4673 TSAR_ELEMENT_TSAR_TYPE_DWRR = 0x0, 4674 TSAR_ELEMENT_TSAR_TYPE_ROUND_ROBIN = 0x1, 4675 TSAR_ELEMENT_TSAR_TYPE_ETS = 0x2, 4676 }; 4677 4678 struct mlx5_ifc_tsar_element_bits { 4679 u8 reserved_at_0[0x8]; 4680 u8 tsar_type[0x8]; 4681 u8 reserved_at_10[0x10]; 4682 }; 4683 4684 enum { 4685 MLX5_TEARDOWN_HCA_OUT_FORCE_STATE_SUCCESS = 0x0, 4686 MLX5_TEARDOWN_HCA_OUT_FORCE_STATE_FAIL = 0x1, 4687 }; 4688 4689 struct mlx5_ifc_teardown_hca_out_bits { 4690 u8 status[0x8]; 4691 u8 reserved_at_8[0x18]; 4692 4693 u8 syndrome[0x20]; 4694 4695 u8 reserved_at_40[0x3f]; 4696 4697 u8 state[0x1]; 4698 }; 4699 4700 enum { 4701 MLX5_TEARDOWN_HCA_IN_PROFILE_GRACEFUL_CLOSE = 0x0, 4702 MLX5_TEARDOWN_HCA_IN_PROFILE_FORCE_CLOSE = 0x1, 4703 MLX5_TEARDOWN_HCA_IN_PROFILE_PREPARE_FAST_TEARDOWN = 0x2, 4704 }; 4705 4706 struct mlx5_ifc_teardown_hca_in_bits { 4707 u8 opcode[0x10]; 4708 u8 reserved_at_10[0x10]; 4709 4710 u8 reserved_at_20[0x10]; 4711 u8 op_mod[0x10]; 4712 4713 u8 reserved_at_40[0x10]; 4714 u8 profile[0x10]; 4715 4716 u8 reserved_at_60[0x20]; 4717 }; 4718 4719 struct mlx5_ifc_sqerr2rts_qp_out_bits { 4720 u8 status[0x8]; 4721 u8 reserved_at_8[0x18]; 4722 4723 u8 syndrome[0x20]; 4724 4725 u8 reserved_at_40[0x40]; 4726 }; 4727 4728 struct mlx5_ifc_sqerr2rts_qp_in_bits { 4729 u8 opcode[0x10]; 4730 u8 uid[0x10]; 4731 4732 u8 reserved_at_20[0x10]; 4733 u8 op_mod[0x10]; 4734 4735 u8 reserved_at_40[0x8]; 4736 u8 qpn[0x18]; 4737 4738 u8 reserved_at_60[0x20]; 4739 4740 u8 opt_param_mask[0x20]; 4741 4742 u8 reserved_at_a0[0x20]; 4743 4744 struct mlx5_ifc_qpc_bits qpc; 4745 4746 u8 reserved_at_800[0x80]; 4747 }; 4748 4749 struct mlx5_ifc_sqd2rts_qp_out_bits { 4750 u8 status[0x8]; 4751 u8 reserved_at_8[0x18]; 4752 4753 u8 syndrome[0x20]; 4754 4755 u8 reserved_at_40[0x40]; 4756 }; 4757 4758 struct mlx5_ifc_sqd2rts_qp_in_bits { 4759 u8 opcode[0x10]; 4760 u8 uid[0x10]; 4761 4762 u8 reserved_at_20[0x10]; 4763 u8 op_mod[0x10]; 4764 4765 u8 reserved_at_40[0x8]; 4766 u8 qpn[0x18]; 4767 4768 u8 reserved_at_60[0x20]; 4769 4770 u8 opt_param_mask[0x20]; 4771 4772 u8 reserved_at_a0[0x20]; 4773 4774 struct mlx5_ifc_qpc_bits qpc; 4775 4776 u8 reserved_at_800[0x80]; 4777 }; 4778 4779 struct mlx5_ifc_set_roce_address_out_bits { 4780 u8 status[0x8]; 4781 u8 reserved_at_8[0x18]; 4782 4783 u8 syndrome[0x20]; 4784 4785 u8 reserved_at_40[0x40]; 4786 }; 4787 4788 struct mlx5_ifc_set_roce_address_in_bits { 4789 u8 opcode[0x10]; 4790 u8 reserved_at_10[0x10]; 4791 4792 u8 reserved_at_20[0x10]; 4793 u8 op_mod[0x10]; 4794 4795 u8 roce_address_index[0x10]; 4796 u8 reserved_at_50[0xc]; 4797 u8 vhca_port_num[0x4]; 4798 4799 u8 reserved_at_60[0x20]; 4800 4801 struct mlx5_ifc_roce_addr_layout_bits roce_address; 4802 }; 4803 4804 struct mlx5_ifc_set_mad_demux_out_bits { 4805 u8 status[0x8]; 4806 u8 reserved_at_8[0x18]; 4807 4808 u8 syndrome[0x20]; 4809 4810 u8 reserved_at_40[0x40]; 4811 }; 4812 4813 enum { 4814 MLX5_SET_MAD_DEMUX_IN_DEMUX_MODE_PASS_ALL = 0x0, 4815 MLX5_SET_MAD_DEMUX_IN_DEMUX_MODE_SELECTIVE = 0x2, 4816 }; 4817 4818 struct mlx5_ifc_set_mad_demux_in_bits { 4819 u8 opcode[0x10]; 4820 u8 reserved_at_10[0x10]; 4821 4822 u8 reserved_at_20[0x10]; 4823 u8 op_mod[0x10]; 4824 4825 u8 reserved_at_40[0x20]; 4826 4827 u8 reserved_at_60[0x6]; 4828 u8 demux_mode[0x2]; 4829 u8 reserved_at_68[0x18]; 4830 }; 4831 4832 struct mlx5_ifc_set_l2_table_entry_out_bits { 4833 u8 status[0x8]; 4834 u8 reserved_at_8[0x18]; 4835 4836 u8 syndrome[0x20]; 4837 4838 u8 reserved_at_40[0x40]; 4839 }; 4840 4841 struct mlx5_ifc_set_l2_table_entry_in_bits { 4842 u8 opcode[0x10]; 4843 u8 reserved_at_10[0x10]; 4844 4845 u8 reserved_at_20[0x10]; 4846 u8 op_mod[0x10]; 4847 4848 u8 reserved_at_40[0x60]; 4849 4850 u8 reserved_at_a0[0x8]; 4851 u8 table_index[0x18]; 4852 4853 u8 reserved_at_c0[0x20]; 4854 4855 u8 reserved_at_e0[0x10]; 4856 u8 silent_mode_valid[0x1]; 4857 u8 silent_mode[0x1]; 4858 u8 reserved_at_f2[0x1]; 4859 u8 vlan_valid[0x1]; 4860 u8 vlan[0xc]; 4861 4862 struct mlx5_ifc_mac_address_layout_bits mac_address; 4863 4864 u8 reserved_at_140[0xc0]; 4865 }; 4866 4867 struct mlx5_ifc_set_issi_out_bits { 4868 u8 status[0x8]; 4869 u8 reserved_at_8[0x18]; 4870 4871 u8 syndrome[0x20]; 4872 4873 u8 reserved_at_40[0x40]; 4874 }; 4875 4876 struct mlx5_ifc_set_issi_in_bits { 4877 u8 opcode[0x10]; 4878 u8 reserved_at_10[0x10]; 4879 4880 u8 reserved_at_20[0x10]; 4881 u8 op_mod[0x10]; 4882 4883 u8 reserved_at_40[0x10]; 4884 u8 current_issi[0x10]; 4885 4886 u8 reserved_at_60[0x20]; 4887 }; 4888 4889 struct mlx5_ifc_set_hca_cap_out_bits { 4890 u8 status[0x8]; 4891 u8 reserved_at_8[0x18]; 4892 4893 u8 syndrome[0x20]; 4894 4895 u8 reserved_at_40[0x40]; 4896 }; 4897 4898 struct mlx5_ifc_set_hca_cap_in_bits { 4899 u8 opcode[0x10]; 4900 u8 reserved_at_10[0x10]; 4901 4902 u8 reserved_at_20[0x10]; 4903 u8 op_mod[0x10]; 4904 4905 u8 other_function[0x1]; 4906 u8 ec_vf_function[0x1]; 4907 u8 reserved_at_42[0xe]; 4908 u8 function_id[0x10]; 4909 4910 u8 reserved_at_60[0x20]; 4911 4912 union mlx5_ifc_hca_cap_union_bits capability; 4913 }; 4914 4915 enum { 4916 MLX5_SET_FTE_MODIFY_ENABLE_MASK_ACTION = 0x0, 4917 MLX5_SET_FTE_MODIFY_ENABLE_MASK_FLOW_TAG = 0x1, 4918 MLX5_SET_FTE_MODIFY_ENABLE_MASK_DESTINATION_LIST = 0x2, 4919 MLX5_SET_FTE_MODIFY_ENABLE_MASK_FLOW_COUNTERS = 0x3, 4920 MLX5_SET_FTE_MODIFY_ENABLE_MASK_IPSEC_OBJ_ID = 0x4 4921 }; 4922 4923 struct mlx5_ifc_set_fte_out_bits { 4924 u8 status[0x8]; 4925 u8 reserved_at_8[0x18]; 4926 4927 u8 syndrome[0x20]; 4928 4929 u8 reserved_at_40[0x40]; 4930 }; 4931 4932 struct mlx5_ifc_set_fte_in_bits { 4933 u8 opcode[0x10]; 4934 u8 reserved_at_10[0x10]; 4935 4936 u8 reserved_at_20[0x10]; 4937 u8 op_mod[0x10]; 4938 4939 u8 other_vport[0x1]; 4940 u8 reserved_at_41[0xf]; 4941 u8 vport_number[0x10]; 4942 4943 u8 reserved_at_60[0x20]; 4944 4945 u8 table_type[0x8]; 4946 u8 reserved_at_88[0x18]; 4947 4948 u8 reserved_at_a0[0x8]; 4949 u8 table_id[0x18]; 4950 4951 u8 ignore_flow_level[0x1]; 4952 u8 reserved_at_c1[0x17]; 4953 u8 modify_enable_mask[0x8]; 4954 4955 u8 reserved_at_e0[0x20]; 4956 4957 u8 flow_index[0x20]; 4958 4959 u8 reserved_at_120[0xe0]; 4960 4961 struct mlx5_ifc_flow_context_bits flow_context; 4962 }; 4963 4964 struct mlx5_ifc_rts2rts_qp_out_bits { 4965 u8 status[0x8]; 4966 u8 reserved_at_8[0x18]; 4967 4968 u8 syndrome[0x20]; 4969 4970 u8 reserved_at_40[0x20]; 4971 u8 ece[0x20]; 4972 }; 4973 4974 struct mlx5_ifc_rts2rts_qp_in_bits { 4975 u8 opcode[0x10]; 4976 u8 uid[0x10]; 4977 4978 u8 reserved_at_20[0x10]; 4979 u8 op_mod[0x10]; 4980 4981 u8 reserved_at_40[0x8]; 4982 u8 qpn[0x18]; 4983 4984 u8 reserved_at_60[0x20]; 4985 4986 u8 opt_param_mask[0x20]; 4987 4988 u8 ece[0x20]; 4989 4990 struct mlx5_ifc_qpc_bits qpc; 4991 4992 u8 reserved_at_800[0x80]; 4993 }; 4994 4995 struct mlx5_ifc_rtr2rts_qp_out_bits { 4996 u8 status[0x8]; 4997 u8 reserved_at_8[0x18]; 4998 4999 u8 syndrome[0x20]; 5000 5001 u8 reserved_at_40[0x20]; 5002 u8 ece[0x20]; 5003 }; 5004 5005 struct mlx5_ifc_rtr2rts_qp_in_bits { 5006 u8 opcode[0x10]; 5007 u8 uid[0x10]; 5008 5009 u8 reserved_at_20[0x10]; 5010 u8 op_mod[0x10]; 5011 5012 u8 reserved_at_40[0x8]; 5013 u8 qpn[0x18]; 5014 5015 u8 reserved_at_60[0x20]; 5016 5017 u8 opt_param_mask[0x20]; 5018 5019 u8 ece[0x20]; 5020 5021 struct mlx5_ifc_qpc_bits qpc; 5022 5023 u8 reserved_at_800[0x80]; 5024 }; 5025 5026 struct mlx5_ifc_rst2init_qp_out_bits { 5027 u8 status[0x8]; 5028 u8 reserved_at_8[0x18]; 5029 5030 u8 syndrome[0x20]; 5031 5032 u8 reserved_at_40[0x20]; 5033 u8 ece[0x20]; 5034 }; 5035 5036 struct mlx5_ifc_rst2init_qp_in_bits { 5037 u8 opcode[0x10]; 5038 u8 uid[0x10]; 5039 5040 u8 reserved_at_20[0x10]; 5041 u8 op_mod[0x10]; 5042 5043 u8 reserved_at_40[0x8]; 5044 u8 qpn[0x18]; 5045 5046 u8 reserved_at_60[0x20]; 5047 5048 u8 opt_param_mask[0x20]; 5049 5050 u8 ece[0x20]; 5051 5052 struct mlx5_ifc_qpc_bits qpc; 5053 5054 u8 reserved_at_800[0x80]; 5055 }; 5056 5057 struct mlx5_ifc_query_xrq_out_bits { 5058 u8 status[0x8]; 5059 u8 reserved_at_8[0x18]; 5060 5061 u8 syndrome[0x20]; 5062 5063 u8 reserved_at_40[0x40]; 5064 5065 struct mlx5_ifc_xrqc_bits xrq_context; 5066 }; 5067 5068 struct mlx5_ifc_query_xrq_in_bits { 5069 u8 opcode[0x10]; 5070 u8 reserved_at_10[0x10]; 5071 5072 u8 reserved_at_20[0x10]; 5073 u8 op_mod[0x10]; 5074 5075 u8 reserved_at_40[0x8]; 5076 u8 xrqn[0x18]; 5077 5078 u8 reserved_at_60[0x20]; 5079 }; 5080 5081 struct mlx5_ifc_query_xrc_srq_out_bits { 5082 u8 status[0x8]; 5083 u8 reserved_at_8[0x18]; 5084 5085 u8 syndrome[0x20]; 5086 5087 u8 reserved_at_40[0x40]; 5088 5089 struct mlx5_ifc_xrc_srqc_bits xrc_srq_context_entry; 5090 5091 u8 reserved_at_280[0x600]; 5092 5093 u8 pas[][0x40]; 5094 }; 5095 5096 struct mlx5_ifc_query_xrc_srq_in_bits { 5097 u8 opcode[0x10]; 5098 u8 reserved_at_10[0x10]; 5099 5100 u8 reserved_at_20[0x10]; 5101 u8 op_mod[0x10]; 5102 5103 u8 reserved_at_40[0x8]; 5104 u8 xrc_srqn[0x18]; 5105 5106 u8 reserved_at_60[0x20]; 5107 }; 5108 5109 enum { 5110 MLX5_QUERY_VPORT_STATE_OUT_STATE_DOWN = 0x0, 5111 MLX5_QUERY_VPORT_STATE_OUT_STATE_UP = 0x1, 5112 }; 5113 5114 struct mlx5_ifc_query_vport_state_out_bits { 5115 u8 status[0x8]; 5116 u8 reserved_at_8[0x18]; 5117 5118 u8 syndrome[0x20]; 5119 5120 u8 reserved_at_40[0x20]; 5121 5122 u8 reserved_at_60[0x18]; 5123 u8 admin_state[0x4]; 5124 u8 state[0x4]; 5125 }; 5126 5127 enum { 5128 MLX5_VPORT_STATE_OP_MOD_VNIC_VPORT = 0x0, 5129 MLX5_VPORT_STATE_OP_MOD_ESW_VPORT = 0x1, 5130 MLX5_VPORT_STATE_OP_MOD_UPLINK = 0x2, 5131 }; 5132 5133 struct mlx5_ifc_arm_monitor_counter_in_bits { 5134 u8 opcode[0x10]; 5135 u8 uid[0x10]; 5136 5137 u8 reserved_at_20[0x10]; 5138 u8 op_mod[0x10]; 5139 5140 u8 reserved_at_40[0x20]; 5141 5142 u8 reserved_at_60[0x20]; 5143 }; 5144 5145 struct mlx5_ifc_arm_monitor_counter_out_bits { 5146 u8 status[0x8]; 5147 u8 reserved_at_8[0x18]; 5148 5149 u8 syndrome[0x20]; 5150 5151 u8 reserved_at_40[0x40]; 5152 }; 5153 5154 enum { 5155 MLX5_QUERY_MONITOR_CNT_TYPE_PPCNT = 0x0, 5156 MLX5_QUERY_MONITOR_CNT_TYPE_Q_COUNTER = 0x1, 5157 }; 5158 5159 enum mlx5_monitor_counter_ppcnt { 5160 MLX5_QUERY_MONITOR_PPCNT_IN_RANGE_LENGTH_ERRORS = 0x0, 5161 MLX5_QUERY_MONITOR_PPCNT_OUT_OF_RANGE_LENGTH_FIELD = 0x1, 5162 MLX5_QUERY_MONITOR_PPCNT_FRAME_TOO_LONG_ERRORS = 0x2, 5163 MLX5_QUERY_MONITOR_PPCNT_FRAME_CHECK_SEQUENCE_ERRORS = 0x3, 5164 MLX5_QUERY_MONITOR_PPCNT_ALIGNMENT_ERRORS = 0x4, 5165 MLX5_QUERY_MONITOR_PPCNT_IF_OUT_DISCARDS = 0x5, 5166 }; 5167 5168 enum { 5169 MLX5_QUERY_MONITOR_Q_COUNTER_RX_OUT_OF_BUFFER = 0x4, 5170 }; 5171 5172 struct mlx5_ifc_monitor_counter_output_bits { 5173 u8 reserved_at_0[0x4]; 5174 u8 type[0x4]; 5175 u8 reserved_at_8[0x8]; 5176 u8 counter[0x10]; 5177 5178 u8 counter_group_id[0x20]; 5179 }; 5180 5181 #define MLX5_CMD_SET_MONITOR_NUM_PPCNT_COUNTER_SET1 (6) 5182 #define MLX5_CMD_SET_MONITOR_NUM_Q_COUNTERS_SET1 (1) 5183 #define MLX5_CMD_SET_MONITOR_NUM_COUNTER (MLX5_CMD_SET_MONITOR_NUM_PPCNT_COUNTER_SET1 +\ 5184 MLX5_CMD_SET_MONITOR_NUM_Q_COUNTERS_SET1) 5185 5186 struct mlx5_ifc_set_monitor_counter_in_bits { 5187 u8 opcode[0x10]; 5188 u8 uid[0x10]; 5189 5190 u8 reserved_at_20[0x10]; 5191 u8 op_mod[0x10]; 5192 5193 u8 reserved_at_40[0x10]; 5194 u8 num_of_counters[0x10]; 5195 5196 u8 reserved_at_60[0x20]; 5197 5198 struct mlx5_ifc_monitor_counter_output_bits monitor_counter[MLX5_CMD_SET_MONITOR_NUM_COUNTER]; 5199 }; 5200 5201 struct mlx5_ifc_set_monitor_counter_out_bits { 5202 u8 status[0x8]; 5203 u8 reserved_at_8[0x18]; 5204 5205 u8 syndrome[0x20]; 5206 5207 u8 reserved_at_40[0x40]; 5208 }; 5209 5210 struct mlx5_ifc_query_vport_state_in_bits { 5211 u8 opcode[0x10]; 5212 u8 reserved_at_10[0x10]; 5213 5214 u8 reserved_at_20[0x10]; 5215 u8 op_mod[0x10]; 5216 5217 u8 other_vport[0x1]; 5218 u8 reserved_at_41[0xf]; 5219 u8 vport_number[0x10]; 5220 5221 u8 reserved_at_60[0x20]; 5222 }; 5223 5224 struct mlx5_ifc_query_vnic_env_out_bits { 5225 u8 status[0x8]; 5226 u8 reserved_at_8[0x18]; 5227 5228 u8 syndrome[0x20]; 5229 5230 u8 reserved_at_40[0x40]; 5231 5232 struct mlx5_ifc_vnic_diagnostic_statistics_bits vport_env; 5233 }; 5234 5235 enum { 5236 MLX5_QUERY_VNIC_ENV_IN_OP_MOD_VPORT_DIAG_STATISTICS = 0x0, 5237 }; 5238 5239 struct mlx5_ifc_query_vnic_env_in_bits { 5240 u8 opcode[0x10]; 5241 u8 reserved_at_10[0x10]; 5242 5243 u8 reserved_at_20[0x10]; 5244 u8 op_mod[0x10]; 5245 5246 u8 other_vport[0x1]; 5247 u8 reserved_at_41[0xf]; 5248 u8 vport_number[0x10]; 5249 5250 u8 reserved_at_60[0x20]; 5251 }; 5252 5253 struct mlx5_ifc_query_vport_counter_out_bits { 5254 u8 status[0x8]; 5255 u8 reserved_at_8[0x18]; 5256 5257 u8 syndrome[0x20]; 5258 5259 u8 reserved_at_40[0x40]; 5260 5261 struct mlx5_ifc_traffic_counter_bits received_errors; 5262 5263 struct mlx5_ifc_traffic_counter_bits transmit_errors; 5264 5265 struct mlx5_ifc_traffic_counter_bits received_ib_unicast; 5266 5267 struct mlx5_ifc_traffic_counter_bits transmitted_ib_unicast; 5268 5269 struct mlx5_ifc_traffic_counter_bits received_ib_multicast; 5270 5271 struct mlx5_ifc_traffic_counter_bits transmitted_ib_multicast; 5272 5273 struct mlx5_ifc_traffic_counter_bits received_eth_broadcast; 5274 5275 struct mlx5_ifc_traffic_counter_bits transmitted_eth_broadcast; 5276 5277 struct mlx5_ifc_traffic_counter_bits received_eth_unicast; 5278 5279 struct mlx5_ifc_traffic_counter_bits transmitted_eth_unicast; 5280 5281 struct mlx5_ifc_traffic_counter_bits received_eth_multicast; 5282 5283 struct mlx5_ifc_traffic_counter_bits transmitted_eth_multicast; 5284 5285 struct mlx5_ifc_traffic_counter_bits local_loopback; 5286 5287 u8 reserved_at_700[0x980]; 5288 }; 5289 5290 enum { 5291 MLX5_QUERY_VPORT_COUNTER_IN_OP_MOD_VPORT_COUNTERS = 0x0, 5292 }; 5293 5294 struct mlx5_ifc_query_vport_counter_in_bits { 5295 u8 opcode[0x10]; 5296 u8 reserved_at_10[0x10]; 5297 5298 u8 reserved_at_20[0x10]; 5299 u8 op_mod[0x10]; 5300 5301 u8 other_vport[0x1]; 5302 u8 reserved_at_41[0xb]; 5303 u8 port_num[0x4]; 5304 u8 vport_number[0x10]; 5305 5306 u8 reserved_at_60[0x60]; 5307 5308 u8 clear[0x1]; 5309 u8 reserved_at_c1[0x1f]; 5310 5311 u8 reserved_at_e0[0x20]; 5312 }; 5313 5314 struct mlx5_ifc_query_tis_out_bits { 5315 u8 status[0x8]; 5316 u8 reserved_at_8[0x18]; 5317 5318 u8 syndrome[0x20]; 5319 5320 u8 reserved_at_40[0x40]; 5321 5322 struct mlx5_ifc_tisc_bits tis_context; 5323 }; 5324 5325 struct mlx5_ifc_query_tis_in_bits { 5326 u8 opcode[0x10]; 5327 u8 reserved_at_10[0x10]; 5328 5329 u8 reserved_at_20[0x10]; 5330 u8 op_mod[0x10]; 5331 5332 u8 reserved_at_40[0x8]; 5333 u8 tisn[0x18]; 5334 5335 u8 reserved_at_60[0x20]; 5336 }; 5337 5338 struct mlx5_ifc_query_tir_out_bits { 5339 u8 status[0x8]; 5340 u8 reserved_at_8[0x18]; 5341 5342 u8 syndrome[0x20]; 5343 5344 u8 reserved_at_40[0xc0]; 5345 5346 struct mlx5_ifc_tirc_bits tir_context; 5347 }; 5348 5349 struct mlx5_ifc_query_tir_in_bits { 5350 u8 opcode[0x10]; 5351 u8 reserved_at_10[0x10]; 5352 5353 u8 reserved_at_20[0x10]; 5354 u8 op_mod[0x10]; 5355 5356 u8 reserved_at_40[0x8]; 5357 u8 tirn[0x18]; 5358 5359 u8 reserved_at_60[0x20]; 5360 }; 5361 5362 struct mlx5_ifc_query_srq_out_bits { 5363 u8 status[0x8]; 5364 u8 reserved_at_8[0x18]; 5365 5366 u8 syndrome[0x20]; 5367 5368 u8 reserved_at_40[0x40]; 5369 5370 struct mlx5_ifc_srqc_bits srq_context_entry; 5371 5372 u8 reserved_at_280[0x600]; 5373 5374 u8 pas[][0x40]; 5375 }; 5376 5377 struct mlx5_ifc_query_srq_in_bits { 5378 u8 opcode[0x10]; 5379 u8 reserved_at_10[0x10]; 5380 5381 u8 reserved_at_20[0x10]; 5382 u8 op_mod[0x10]; 5383 5384 u8 reserved_at_40[0x8]; 5385 u8 srqn[0x18]; 5386 5387 u8 reserved_at_60[0x20]; 5388 }; 5389 5390 struct mlx5_ifc_query_sq_out_bits { 5391 u8 status[0x8]; 5392 u8 reserved_at_8[0x18]; 5393 5394 u8 syndrome[0x20]; 5395 5396 u8 reserved_at_40[0xc0]; 5397 5398 struct mlx5_ifc_sqc_bits sq_context; 5399 }; 5400 5401 struct mlx5_ifc_query_sq_in_bits { 5402 u8 opcode[0x10]; 5403 u8 reserved_at_10[0x10]; 5404 5405 u8 reserved_at_20[0x10]; 5406 u8 op_mod[0x10]; 5407 5408 u8 reserved_at_40[0x8]; 5409 u8 sqn[0x18]; 5410 5411 u8 reserved_at_60[0x20]; 5412 }; 5413 5414 struct mlx5_ifc_query_special_contexts_out_bits { 5415 u8 status[0x8]; 5416 u8 reserved_at_8[0x18]; 5417 5418 u8 syndrome[0x20]; 5419 5420 u8 dump_fill_mkey[0x20]; 5421 5422 u8 resd_lkey[0x20]; 5423 5424 u8 null_mkey[0x20]; 5425 5426 u8 terminate_scatter_list_mkey[0x20]; 5427 5428 u8 repeated_mkey[0x20]; 5429 5430 u8 reserved_at_a0[0x20]; 5431 }; 5432 5433 struct mlx5_ifc_query_special_contexts_in_bits { 5434 u8 opcode[0x10]; 5435 u8 reserved_at_10[0x10]; 5436 5437 u8 reserved_at_20[0x10]; 5438 u8 op_mod[0x10]; 5439 5440 u8 reserved_at_40[0x40]; 5441 }; 5442 5443 struct mlx5_ifc_query_scheduling_element_out_bits { 5444 u8 opcode[0x10]; 5445 u8 reserved_at_10[0x10]; 5446 5447 u8 reserved_at_20[0x10]; 5448 u8 op_mod[0x10]; 5449 5450 u8 reserved_at_40[0xc0]; 5451 5452 struct mlx5_ifc_scheduling_context_bits scheduling_context; 5453 5454 u8 reserved_at_300[0x100]; 5455 }; 5456 5457 enum { 5458 SCHEDULING_HIERARCHY_E_SWITCH = 0x2, 5459 SCHEDULING_HIERARCHY_NIC = 0x3, 5460 }; 5461 5462 struct mlx5_ifc_query_scheduling_element_in_bits { 5463 u8 opcode[0x10]; 5464 u8 reserved_at_10[0x10]; 5465 5466 u8 reserved_at_20[0x10]; 5467 u8 op_mod[0x10]; 5468 5469 u8 scheduling_hierarchy[0x8]; 5470 u8 reserved_at_48[0x18]; 5471 5472 u8 scheduling_element_id[0x20]; 5473 5474 u8 reserved_at_80[0x180]; 5475 }; 5476 5477 struct mlx5_ifc_query_rqt_out_bits { 5478 u8 status[0x8]; 5479 u8 reserved_at_8[0x18]; 5480 5481 u8 syndrome[0x20]; 5482 5483 u8 reserved_at_40[0xc0]; 5484 5485 struct mlx5_ifc_rqtc_bits rqt_context; 5486 }; 5487 5488 struct mlx5_ifc_query_rqt_in_bits { 5489 u8 opcode[0x10]; 5490 u8 reserved_at_10[0x10]; 5491 5492 u8 reserved_at_20[0x10]; 5493 u8 op_mod[0x10]; 5494 5495 u8 reserved_at_40[0x8]; 5496 u8 rqtn[0x18]; 5497 5498 u8 reserved_at_60[0x20]; 5499 }; 5500 5501 struct mlx5_ifc_query_rq_out_bits { 5502 u8 status[0x8]; 5503 u8 reserved_at_8[0x18]; 5504 5505 u8 syndrome[0x20]; 5506 5507 u8 reserved_at_40[0xc0]; 5508 5509 struct mlx5_ifc_rqc_bits rq_context; 5510 }; 5511 5512 struct mlx5_ifc_query_rq_in_bits { 5513 u8 opcode[0x10]; 5514 u8 reserved_at_10[0x10]; 5515 5516 u8 reserved_at_20[0x10]; 5517 u8 op_mod[0x10]; 5518 5519 u8 reserved_at_40[0x8]; 5520 u8 rqn[0x18]; 5521 5522 u8 reserved_at_60[0x20]; 5523 }; 5524 5525 struct mlx5_ifc_query_roce_address_out_bits { 5526 u8 status[0x8]; 5527 u8 reserved_at_8[0x18]; 5528 5529 u8 syndrome[0x20]; 5530 5531 u8 reserved_at_40[0x40]; 5532 5533 struct mlx5_ifc_roce_addr_layout_bits roce_address; 5534 }; 5535 5536 struct mlx5_ifc_query_roce_address_in_bits { 5537 u8 opcode[0x10]; 5538 u8 reserved_at_10[0x10]; 5539 5540 u8 reserved_at_20[0x10]; 5541 u8 op_mod[0x10]; 5542 5543 u8 roce_address_index[0x10]; 5544 u8 reserved_at_50[0xc]; 5545 u8 vhca_port_num[0x4]; 5546 5547 u8 reserved_at_60[0x20]; 5548 }; 5549 5550 struct mlx5_ifc_query_rmp_out_bits { 5551 u8 status[0x8]; 5552 u8 reserved_at_8[0x18]; 5553 5554 u8 syndrome[0x20]; 5555 5556 u8 reserved_at_40[0xc0]; 5557 5558 struct mlx5_ifc_rmpc_bits rmp_context; 5559 }; 5560 5561 struct mlx5_ifc_query_rmp_in_bits { 5562 u8 opcode[0x10]; 5563 u8 reserved_at_10[0x10]; 5564 5565 u8 reserved_at_20[0x10]; 5566 u8 op_mod[0x10]; 5567 5568 u8 reserved_at_40[0x8]; 5569 u8 rmpn[0x18]; 5570 5571 u8 reserved_at_60[0x20]; 5572 }; 5573 5574 struct mlx5_ifc_cqe_error_syndrome_bits { 5575 u8 hw_error_syndrome[0x8]; 5576 u8 hw_syndrome_type[0x4]; 5577 u8 reserved_at_c[0x4]; 5578 u8 vendor_error_syndrome[0x8]; 5579 u8 syndrome[0x8]; 5580 }; 5581 5582 struct mlx5_ifc_qp_context_extension_bits { 5583 u8 reserved_at_0[0x60]; 5584 5585 struct mlx5_ifc_cqe_error_syndrome_bits error_syndrome; 5586 5587 u8 reserved_at_80[0x580]; 5588 }; 5589 5590 struct mlx5_ifc_qpc_extension_and_pas_list_in_bits { 5591 struct mlx5_ifc_qp_context_extension_bits qpc_data_extension; 5592 5593 u8 pas[0][0x40]; 5594 }; 5595 5596 struct mlx5_ifc_qp_pas_list_in_bits { 5597 struct mlx5_ifc_cmd_pas_bits pas[0]; 5598 }; 5599 5600 union mlx5_ifc_qp_pas_or_qpc_ext_and_pas_bits { 5601 struct mlx5_ifc_qp_pas_list_in_bits qp_pas_list; 5602 struct mlx5_ifc_qpc_extension_and_pas_list_in_bits qpc_ext_and_pas_list; 5603 }; 5604 5605 struct mlx5_ifc_query_qp_out_bits { 5606 u8 status[0x8]; 5607 u8 reserved_at_8[0x18]; 5608 5609 u8 syndrome[0x20]; 5610 5611 u8 reserved_at_40[0x40]; 5612 5613 u8 opt_param_mask[0x20]; 5614 5615 u8 ece[0x20]; 5616 5617 struct mlx5_ifc_qpc_bits qpc; 5618 5619 u8 reserved_at_800[0x80]; 5620 5621 union mlx5_ifc_qp_pas_or_qpc_ext_and_pas_bits qp_pas_or_qpc_ext_and_pas; 5622 }; 5623 5624 struct mlx5_ifc_query_qp_in_bits { 5625 u8 opcode[0x10]; 5626 u8 reserved_at_10[0x10]; 5627 5628 u8 reserved_at_20[0x10]; 5629 u8 op_mod[0x10]; 5630 5631 u8 qpc_ext[0x1]; 5632 u8 reserved_at_41[0x7]; 5633 u8 qpn[0x18]; 5634 5635 u8 reserved_at_60[0x20]; 5636 }; 5637 5638 struct mlx5_ifc_query_q_counter_out_bits { 5639 u8 status[0x8]; 5640 u8 reserved_at_8[0x18]; 5641 5642 u8 syndrome[0x20]; 5643 5644 u8 reserved_at_40[0x40]; 5645 5646 u8 rx_write_requests[0x20]; 5647 5648 u8 reserved_at_a0[0x20]; 5649 5650 u8 rx_read_requests[0x20]; 5651 5652 u8 reserved_at_e0[0x20]; 5653 5654 u8 rx_atomic_requests[0x20]; 5655 5656 u8 reserved_at_120[0x20]; 5657 5658 u8 rx_dct_connect[0x20]; 5659 5660 u8 reserved_at_160[0x20]; 5661 5662 u8 out_of_buffer[0x20]; 5663 5664 u8 reserved_at_1a0[0x20]; 5665 5666 u8 out_of_sequence[0x20]; 5667 5668 u8 reserved_at_1e0[0x20]; 5669 5670 u8 duplicate_request[0x20]; 5671 5672 u8 reserved_at_220[0x20]; 5673 5674 u8 rnr_nak_retry_err[0x20]; 5675 5676 u8 reserved_at_260[0x20]; 5677 5678 u8 packet_seq_err[0x20]; 5679 5680 u8 reserved_at_2a0[0x20]; 5681 5682 u8 implied_nak_seq_err[0x20]; 5683 5684 u8 reserved_at_2e0[0x20]; 5685 5686 u8 local_ack_timeout_err[0x20]; 5687 5688 u8 reserved_at_320[0x60]; 5689 5690 u8 req_rnr_retries_exceeded[0x20]; 5691 5692 u8 reserved_at_3a0[0x20]; 5693 5694 u8 resp_local_length_error[0x20]; 5695 5696 u8 req_local_length_error[0x20]; 5697 5698 u8 resp_local_qp_error[0x20]; 5699 5700 u8 local_operation_error[0x20]; 5701 5702 u8 resp_local_protection[0x20]; 5703 5704 u8 req_local_protection[0x20]; 5705 5706 u8 resp_cqe_error[0x20]; 5707 5708 u8 req_cqe_error[0x20]; 5709 5710 u8 req_mw_binding[0x20]; 5711 5712 u8 req_bad_response[0x20]; 5713 5714 u8 req_remote_invalid_request[0x20]; 5715 5716 u8 resp_remote_invalid_request[0x20]; 5717 5718 u8 req_remote_access_errors[0x20]; 5719 5720 u8 resp_remote_access_errors[0x20]; 5721 5722 u8 req_remote_operation_errors[0x20]; 5723 5724 u8 req_transport_retries_exceeded[0x20]; 5725 5726 u8 cq_overflow[0x20]; 5727 5728 u8 resp_cqe_flush_error[0x20]; 5729 5730 u8 req_cqe_flush_error[0x20]; 5731 5732 u8 reserved_at_620[0x20]; 5733 5734 u8 roce_adp_retrans[0x20]; 5735 5736 u8 roce_adp_retrans_to[0x20]; 5737 5738 u8 roce_slow_restart[0x20]; 5739 5740 u8 roce_slow_restart_cnps[0x20]; 5741 5742 u8 roce_slow_restart_trans[0x20]; 5743 5744 u8 reserved_at_6e0[0x120]; 5745 }; 5746 5747 struct mlx5_ifc_query_q_counter_in_bits { 5748 u8 opcode[0x10]; 5749 u8 reserved_at_10[0x10]; 5750 5751 u8 reserved_at_20[0x10]; 5752 u8 op_mod[0x10]; 5753 5754 u8 other_vport[0x1]; 5755 u8 reserved_at_41[0xf]; 5756 u8 vport_number[0x10]; 5757 5758 u8 reserved_at_60[0x60]; 5759 5760 u8 clear[0x1]; 5761 u8 aggregate[0x1]; 5762 u8 reserved_at_c2[0x1e]; 5763 5764 u8 reserved_at_e0[0x18]; 5765 u8 counter_set_id[0x8]; 5766 }; 5767 5768 struct mlx5_ifc_query_pages_out_bits { 5769 u8 status[0x8]; 5770 u8 reserved_at_8[0x18]; 5771 5772 u8 syndrome[0x20]; 5773 5774 u8 embedded_cpu_function[0x1]; 5775 u8 reserved_at_41[0xf]; 5776 u8 function_id[0x10]; 5777 5778 u8 num_pages[0x20]; 5779 }; 5780 5781 enum { 5782 MLX5_QUERY_PAGES_IN_OP_MOD_BOOT_PAGES = 0x1, 5783 MLX5_QUERY_PAGES_IN_OP_MOD_INIT_PAGES = 0x2, 5784 MLX5_QUERY_PAGES_IN_OP_MOD_REGULAR_PAGES = 0x3, 5785 }; 5786 5787 struct mlx5_ifc_query_pages_in_bits { 5788 u8 opcode[0x10]; 5789 u8 reserved_at_10[0x10]; 5790 5791 u8 reserved_at_20[0x10]; 5792 u8 op_mod[0x10]; 5793 5794 u8 embedded_cpu_function[0x1]; 5795 u8 reserved_at_41[0xf]; 5796 u8 function_id[0x10]; 5797 5798 u8 reserved_at_60[0x20]; 5799 }; 5800 5801 struct mlx5_ifc_query_nic_vport_context_out_bits { 5802 u8 status[0x8]; 5803 u8 reserved_at_8[0x18]; 5804 5805 u8 syndrome[0x20]; 5806 5807 u8 reserved_at_40[0x40]; 5808 5809 struct mlx5_ifc_nic_vport_context_bits nic_vport_context; 5810 }; 5811 5812 struct mlx5_ifc_query_nic_vport_context_in_bits { 5813 u8 opcode[0x10]; 5814 u8 reserved_at_10[0x10]; 5815 5816 u8 reserved_at_20[0x10]; 5817 u8 op_mod[0x10]; 5818 5819 u8 other_vport[0x1]; 5820 u8 reserved_at_41[0xf]; 5821 u8 vport_number[0x10]; 5822 5823 u8 reserved_at_60[0x5]; 5824 u8 allowed_list_type[0x3]; 5825 u8 reserved_at_68[0x18]; 5826 }; 5827 5828 struct mlx5_ifc_query_mkey_out_bits { 5829 u8 status[0x8]; 5830 u8 reserved_at_8[0x18]; 5831 5832 u8 syndrome[0x20]; 5833 5834 u8 reserved_at_40[0x40]; 5835 5836 struct mlx5_ifc_mkc_bits memory_key_mkey_entry; 5837 5838 u8 reserved_at_280[0x600]; 5839 5840 u8 bsf0_klm0_pas_mtt0_1[16][0x8]; 5841 5842 u8 bsf1_klm1_pas_mtt2_3[16][0x8]; 5843 }; 5844 5845 struct mlx5_ifc_query_mkey_in_bits { 5846 u8 opcode[0x10]; 5847 u8 reserved_at_10[0x10]; 5848 5849 u8 reserved_at_20[0x10]; 5850 u8 op_mod[0x10]; 5851 5852 u8 reserved_at_40[0x8]; 5853 u8 mkey_index[0x18]; 5854 5855 u8 pg_access[0x1]; 5856 u8 reserved_at_61[0x1f]; 5857 }; 5858 5859 struct mlx5_ifc_query_mad_demux_out_bits { 5860 u8 status[0x8]; 5861 u8 reserved_at_8[0x18]; 5862 5863 u8 syndrome[0x20]; 5864 5865 u8 reserved_at_40[0x40]; 5866 5867 u8 mad_dumux_parameters_block[0x20]; 5868 }; 5869 5870 struct mlx5_ifc_query_mad_demux_in_bits { 5871 u8 opcode[0x10]; 5872 u8 reserved_at_10[0x10]; 5873 5874 u8 reserved_at_20[0x10]; 5875 u8 op_mod[0x10]; 5876 5877 u8 reserved_at_40[0x40]; 5878 }; 5879 5880 struct mlx5_ifc_query_l2_table_entry_out_bits { 5881 u8 status[0x8]; 5882 u8 reserved_at_8[0x18]; 5883 5884 u8 syndrome[0x20]; 5885 5886 u8 reserved_at_40[0xa0]; 5887 5888 u8 reserved_at_e0[0x13]; 5889 u8 vlan_valid[0x1]; 5890 u8 vlan[0xc]; 5891 5892 struct mlx5_ifc_mac_address_layout_bits mac_address; 5893 5894 u8 reserved_at_140[0xc0]; 5895 }; 5896 5897 struct mlx5_ifc_query_l2_table_entry_in_bits { 5898 u8 opcode[0x10]; 5899 u8 reserved_at_10[0x10]; 5900 5901 u8 reserved_at_20[0x10]; 5902 u8 op_mod[0x10]; 5903 5904 u8 reserved_at_40[0x60]; 5905 5906 u8 reserved_at_a0[0x8]; 5907 u8 table_index[0x18]; 5908 5909 u8 reserved_at_c0[0x140]; 5910 }; 5911 5912 struct mlx5_ifc_query_issi_out_bits { 5913 u8 status[0x8]; 5914 u8 reserved_at_8[0x18]; 5915 5916 u8 syndrome[0x20]; 5917 5918 u8 reserved_at_40[0x10]; 5919 u8 current_issi[0x10]; 5920 5921 u8 reserved_at_60[0xa0]; 5922 5923 u8 reserved_at_100[76][0x8]; 5924 u8 supported_issi_dw0[0x20]; 5925 }; 5926 5927 struct mlx5_ifc_query_issi_in_bits { 5928 u8 opcode[0x10]; 5929 u8 reserved_at_10[0x10]; 5930 5931 u8 reserved_at_20[0x10]; 5932 u8 op_mod[0x10]; 5933 5934 u8 reserved_at_40[0x40]; 5935 }; 5936 5937 struct mlx5_ifc_set_driver_version_out_bits { 5938 u8 status[0x8]; 5939 u8 reserved_0[0x18]; 5940 5941 u8 syndrome[0x20]; 5942 u8 reserved_1[0x40]; 5943 }; 5944 5945 struct mlx5_ifc_set_driver_version_in_bits { 5946 u8 opcode[0x10]; 5947 u8 reserved_0[0x10]; 5948 5949 u8 reserved_1[0x10]; 5950 u8 op_mod[0x10]; 5951 5952 u8 reserved_2[0x40]; 5953 u8 driver_version[64][0x8]; 5954 }; 5955 5956 struct mlx5_ifc_query_hca_vport_pkey_out_bits { 5957 u8 status[0x8]; 5958 u8 reserved_at_8[0x18]; 5959 5960 u8 syndrome[0x20]; 5961 5962 u8 reserved_at_40[0x40]; 5963 5964 struct mlx5_ifc_pkey_bits pkey[]; 5965 }; 5966 5967 struct mlx5_ifc_query_hca_vport_pkey_in_bits { 5968 u8 opcode[0x10]; 5969 u8 reserved_at_10[0x10]; 5970 5971 u8 reserved_at_20[0x10]; 5972 u8 op_mod[0x10]; 5973 5974 u8 other_vport[0x1]; 5975 u8 reserved_at_41[0xb]; 5976 u8 port_num[0x4]; 5977 u8 vport_number[0x10]; 5978 5979 u8 reserved_at_60[0x10]; 5980 u8 pkey_index[0x10]; 5981 }; 5982 5983 enum { 5984 MLX5_HCA_VPORT_SEL_PORT_GUID = 1 << 0, 5985 MLX5_HCA_VPORT_SEL_NODE_GUID = 1 << 1, 5986 MLX5_HCA_VPORT_SEL_STATE_POLICY = 1 << 2, 5987 }; 5988 5989 struct mlx5_ifc_query_hca_vport_gid_out_bits { 5990 u8 status[0x8]; 5991 u8 reserved_at_8[0x18]; 5992 5993 u8 syndrome[0x20]; 5994 5995 u8 reserved_at_40[0x20]; 5996 5997 u8 gids_num[0x10]; 5998 u8 reserved_at_70[0x10]; 5999 6000 struct mlx5_ifc_array128_auto_bits gid[]; 6001 }; 6002 6003 struct mlx5_ifc_query_hca_vport_gid_in_bits { 6004 u8 opcode[0x10]; 6005 u8 reserved_at_10[0x10]; 6006 6007 u8 reserved_at_20[0x10]; 6008 u8 op_mod[0x10]; 6009 6010 u8 other_vport[0x1]; 6011 u8 reserved_at_41[0xb]; 6012 u8 port_num[0x4]; 6013 u8 vport_number[0x10]; 6014 6015 u8 reserved_at_60[0x10]; 6016 u8 gid_index[0x10]; 6017 }; 6018 6019 struct mlx5_ifc_query_hca_vport_context_out_bits { 6020 u8 status[0x8]; 6021 u8 reserved_at_8[0x18]; 6022 6023 u8 syndrome[0x20]; 6024 6025 u8 reserved_at_40[0x40]; 6026 6027 struct mlx5_ifc_hca_vport_context_bits hca_vport_context; 6028 }; 6029 6030 struct mlx5_ifc_query_hca_vport_context_in_bits { 6031 u8 opcode[0x10]; 6032 u8 reserved_at_10[0x10]; 6033 6034 u8 reserved_at_20[0x10]; 6035 u8 op_mod[0x10]; 6036 6037 u8 other_vport[0x1]; 6038 u8 reserved_at_41[0xb]; 6039 u8 port_num[0x4]; 6040 u8 vport_number[0x10]; 6041 6042 u8 reserved_at_60[0x20]; 6043 }; 6044 6045 struct mlx5_ifc_query_hca_cap_out_bits { 6046 u8 status[0x8]; 6047 u8 reserved_at_8[0x18]; 6048 6049 u8 syndrome[0x20]; 6050 6051 u8 reserved_at_40[0x40]; 6052 6053 union mlx5_ifc_hca_cap_union_bits capability; 6054 }; 6055 6056 struct mlx5_ifc_query_hca_cap_in_bits { 6057 u8 opcode[0x10]; 6058 u8 reserved_at_10[0x10]; 6059 6060 u8 reserved_at_20[0x10]; 6061 u8 op_mod[0x10]; 6062 6063 u8 other_function[0x1]; 6064 u8 ec_vf_function[0x1]; 6065 u8 reserved_at_42[0xe]; 6066 u8 function_id[0x10]; 6067 6068 u8 reserved_at_60[0x20]; 6069 }; 6070 6071 struct mlx5_ifc_other_hca_cap_bits { 6072 u8 roce[0x1]; 6073 u8 reserved_at_1[0x27f]; 6074 }; 6075 6076 struct mlx5_ifc_query_other_hca_cap_out_bits { 6077 u8 status[0x8]; 6078 u8 reserved_at_8[0x18]; 6079 6080 u8 syndrome[0x20]; 6081 6082 u8 reserved_at_40[0x40]; 6083 6084 struct mlx5_ifc_other_hca_cap_bits other_capability; 6085 }; 6086 6087 struct mlx5_ifc_query_other_hca_cap_in_bits { 6088 u8 opcode[0x10]; 6089 u8 reserved_at_10[0x10]; 6090 6091 u8 reserved_at_20[0x10]; 6092 u8 op_mod[0x10]; 6093 6094 u8 reserved_at_40[0x10]; 6095 u8 function_id[0x10]; 6096 6097 u8 reserved_at_60[0x20]; 6098 }; 6099 6100 struct mlx5_ifc_modify_other_hca_cap_out_bits { 6101 u8 status[0x8]; 6102 u8 reserved_at_8[0x18]; 6103 6104 u8 syndrome[0x20]; 6105 6106 u8 reserved_at_40[0x40]; 6107 }; 6108 6109 struct mlx5_ifc_modify_other_hca_cap_in_bits { 6110 u8 opcode[0x10]; 6111 u8 reserved_at_10[0x10]; 6112 6113 u8 reserved_at_20[0x10]; 6114 u8 op_mod[0x10]; 6115 6116 u8 reserved_at_40[0x10]; 6117 u8 function_id[0x10]; 6118 u8 field_select[0x20]; 6119 6120 struct mlx5_ifc_other_hca_cap_bits other_capability; 6121 }; 6122 6123 struct mlx5_ifc_flow_table_context_bits { 6124 u8 reformat_en[0x1]; 6125 u8 decap_en[0x1]; 6126 u8 sw_owner[0x1]; 6127 u8 termination_table[0x1]; 6128 u8 table_miss_action[0x4]; 6129 u8 level[0x8]; 6130 u8 reserved_at_10[0x8]; 6131 u8 log_size[0x8]; 6132 6133 u8 reserved_at_20[0x8]; 6134 u8 table_miss_id[0x18]; 6135 6136 u8 reserved_at_40[0x8]; 6137 u8 lag_master_next_table_id[0x18]; 6138 6139 u8 reserved_at_60[0x60]; 6140 6141 u8 sw_owner_icm_root_1[0x40]; 6142 6143 u8 sw_owner_icm_root_0[0x40]; 6144 6145 }; 6146 6147 struct mlx5_ifc_query_flow_table_out_bits { 6148 u8 status[0x8]; 6149 u8 reserved_at_8[0x18]; 6150 6151 u8 syndrome[0x20]; 6152 6153 u8 reserved_at_40[0x80]; 6154 6155 struct mlx5_ifc_flow_table_context_bits flow_table_context; 6156 }; 6157 6158 struct mlx5_ifc_query_flow_table_in_bits { 6159 u8 opcode[0x10]; 6160 u8 reserved_at_10[0x10]; 6161 6162 u8 reserved_at_20[0x10]; 6163 u8 op_mod[0x10]; 6164 6165 u8 reserved_at_40[0x40]; 6166 6167 u8 table_type[0x8]; 6168 u8 reserved_at_88[0x18]; 6169 6170 u8 reserved_at_a0[0x8]; 6171 u8 table_id[0x18]; 6172 6173 u8 reserved_at_c0[0x140]; 6174 }; 6175 6176 struct mlx5_ifc_query_fte_out_bits { 6177 u8 status[0x8]; 6178 u8 reserved_at_8[0x18]; 6179 6180 u8 syndrome[0x20]; 6181 6182 u8 reserved_at_40[0x1c0]; 6183 6184 struct mlx5_ifc_flow_context_bits flow_context; 6185 }; 6186 6187 struct mlx5_ifc_query_fte_in_bits { 6188 u8 opcode[0x10]; 6189 u8 reserved_at_10[0x10]; 6190 6191 u8 reserved_at_20[0x10]; 6192 u8 op_mod[0x10]; 6193 6194 u8 reserved_at_40[0x40]; 6195 6196 u8 table_type[0x8]; 6197 u8 reserved_at_88[0x18]; 6198 6199 u8 reserved_at_a0[0x8]; 6200 u8 table_id[0x18]; 6201 6202 u8 reserved_at_c0[0x40]; 6203 6204 u8 flow_index[0x20]; 6205 6206 u8 reserved_at_120[0xe0]; 6207 }; 6208 6209 struct mlx5_ifc_match_definer_format_0_bits { 6210 u8 reserved_at_0[0x100]; 6211 6212 u8 metadata_reg_c_0[0x20]; 6213 6214 u8 metadata_reg_c_1[0x20]; 6215 6216 u8 outer_dmac_47_16[0x20]; 6217 6218 u8 outer_dmac_15_0[0x10]; 6219 u8 outer_ethertype[0x10]; 6220 6221 u8 reserved_at_180[0x1]; 6222 u8 sx_sniffer[0x1]; 6223 u8 functional_lb[0x1]; 6224 u8 outer_ip_frag[0x1]; 6225 u8 outer_qp_type[0x2]; 6226 u8 outer_encap_type[0x2]; 6227 u8 port_number[0x2]; 6228 u8 outer_l3_type[0x2]; 6229 u8 outer_l4_type[0x2]; 6230 u8 outer_first_vlan_type[0x2]; 6231 u8 outer_first_vlan_prio[0x3]; 6232 u8 outer_first_vlan_cfi[0x1]; 6233 u8 outer_first_vlan_vid[0xc]; 6234 6235 u8 outer_l4_type_ext[0x4]; 6236 u8 reserved_at_1a4[0x2]; 6237 u8 outer_ipsec_layer[0x2]; 6238 u8 outer_l2_type[0x2]; 6239 u8 force_lb[0x1]; 6240 u8 outer_l2_ok[0x1]; 6241 u8 outer_l3_ok[0x1]; 6242 u8 outer_l4_ok[0x1]; 6243 u8 outer_second_vlan_type[0x2]; 6244 u8 outer_second_vlan_prio[0x3]; 6245 u8 outer_second_vlan_cfi[0x1]; 6246 u8 outer_second_vlan_vid[0xc]; 6247 6248 u8 outer_smac_47_16[0x20]; 6249 6250 u8 outer_smac_15_0[0x10]; 6251 u8 inner_ipv4_checksum_ok[0x1]; 6252 u8 inner_l4_checksum_ok[0x1]; 6253 u8 outer_ipv4_checksum_ok[0x1]; 6254 u8 outer_l4_checksum_ok[0x1]; 6255 u8 inner_l3_ok[0x1]; 6256 u8 inner_l4_ok[0x1]; 6257 u8 outer_l3_ok_duplicate[0x1]; 6258 u8 outer_l4_ok_duplicate[0x1]; 6259 u8 outer_tcp_cwr[0x1]; 6260 u8 outer_tcp_ece[0x1]; 6261 u8 outer_tcp_urg[0x1]; 6262 u8 outer_tcp_ack[0x1]; 6263 u8 outer_tcp_psh[0x1]; 6264 u8 outer_tcp_rst[0x1]; 6265 u8 outer_tcp_syn[0x1]; 6266 u8 outer_tcp_fin[0x1]; 6267 }; 6268 6269 struct mlx5_ifc_match_definer_format_22_bits { 6270 u8 reserved_at_0[0x100]; 6271 6272 u8 outer_ip_src_addr[0x20]; 6273 6274 u8 outer_ip_dest_addr[0x20]; 6275 6276 u8 outer_l4_sport[0x10]; 6277 u8 outer_l4_dport[0x10]; 6278 6279 u8 reserved_at_160[0x1]; 6280 u8 sx_sniffer[0x1]; 6281 u8 functional_lb[0x1]; 6282 u8 outer_ip_frag[0x1]; 6283 u8 outer_qp_type[0x2]; 6284 u8 outer_encap_type[0x2]; 6285 u8 port_number[0x2]; 6286 u8 outer_l3_type[0x2]; 6287 u8 outer_l4_type[0x2]; 6288 u8 outer_first_vlan_type[0x2]; 6289 u8 outer_first_vlan_prio[0x3]; 6290 u8 outer_first_vlan_cfi[0x1]; 6291 u8 outer_first_vlan_vid[0xc]; 6292 6293 u8 metadata_reg_c_0[0x20]; 6294 6295 u8 outer_dmac_47_16[0x20]; 6296 6297 u8 outer_smac_47_16[0x20]; 6298 6299 u8 outer_smac_15_0[0x10]; 6300 u8 outer_dmac_15_0[0x10]; 6301 }; 6302 6303 struct mlx5_ifc_match_definer_format_23_bits { 6304 u8 reserved_at_0[0x100]; 6305 6306 u8 inner_ip_src_addr[0x20]; 6307 6308 u8 inner_ip_dest_addr[0x20]; 6309 6310 u8 inner_l4_sport[0x10]; 6311 u8 inner_l4_dport[0x10]; 6312 6313 u8 reserved_at_160[0x1]; 6314 u8 sx_sniffer[0x1]; 6315 u8 functional_lb[0x1]; 6316 u8 inner_ip_frag[0x1]; 6317 u8 inner_qp_type[0x2]; 6318 u8 inner_encap_type[0x2]; 6319 u8 port_number[0x2]; 6320 u8 inner_l3_type[0x2]; 6321 u8 inner_l4_type[0x2]; 6322 u8 inner_first_vlan_type[0x2]; 6323 u8 inner_first_vlan_prio[0x3]; 6324 u8 inner_first_vlan_cfi[0x1]; 6325 u8 inner_first_vlan_vid[0xc]; 6326 6327 u8 tunnel_header_0[0x20]; 6328 6329 u8 inner_dmac_47_16[0x20]; 6330 6331 u8 inner_smac_47_16[0x20]; 6332 6333 u8 inner_smac_15_0[0x10]; 6334 u8 inner_dmac_15_0[0x10]; 6335 }; 6336 6337 struct mlx5_ifc_match_definer_format_29_bits { 6338 u8 reserved_at_0[0xc0]; 6339 6340 u8 outer_ip_dest_addr[0x80]; 6341 6342 u8 outer_ip_src_addr[0x80]; 6343 6344 u8 outer_l4_sport[0x10]; 6345 u8 outer_l4_dport[0x10]; 6346 6347 u8 reserved_at_1e0[0x20]; 6348 }; 6349 6350 struct mlx5_ifc_match_definer_format_30_bits { 6351 u8 reserved_at_0[0xa0]; 6352 6353 u8 outer_ip_dest_addr[0x80]; 6354 6355 u8 outer_ip_src_addr[0x80]; 6356 6357 u8 outer_dmac_47_16[0x20]; 6358 6359 u8 outer_smac_47_16[0x20]; 6360 6361 u8 outer_smac_15_0[0x10]; 6362 u8 outer_dmac_15_0[0x10]; 6363 }; 6364 6365 struct mlx5_ifc_match_definer_format_31_bits { 6366 u8 reserved_at_0[0xc0]; 6367 6368 u8 inner_ip_dest_addr[0x80]; 6369 6370 u8 inner_ip_src_addr[0x80]; 6371 6372 u8 inner_l4_sport[0x10]; 6373 u8 inner_l4_dport[0x10]; 6374 6375 u8 reserved_at_1e0[0x20]; 6376 }; 6377 6378 struct mlx5_ifc_match_definer_format_32_bits { 6379 u8 reserved_at_0[0xa0]; 6380 6381 u8 inner_ip_dest_addr[0x80]; 6382 6383 u8 inner_ip_src_addr[0x80]; 6384 6385 u8 inner_dmac_47_16[0x20]; 6386 6387 u8 inner_smac_47_16[0x20]; 6388 6389 u8 inner_smac_15_0[0x10]; 6390 u8 inner_dmac_15_0[0x10]; 6391 }; 6392 6393 enum { 6394 MLX5_IFC_DEFINER_FORMAT_ID_SELECT = 61, 6395 }; 6396 6397 #define MLX5_IFC_DEFINER_FORMAT_OFFSET_UNUSED 0x0 6398 #define MLX5_IFC_DEFINER_FORMAT_OFFSET_OUTER_ETH_PKT_LEN 0x48 6399 #define MLX5_IFC_DEFINER_DW_SELECTORS_NUM 9 6400 #define MLX5_IFC_DEFINER_BYTE_SELECTORS_NUM 8 6401 6402 struct mlx5_ifc_match_definer_match_mask_bits { 6403 u8 reserved_at_1c0[5][0x20]; 6404 u8 match_dw_8[0x20]; 6405 u8 match_dw_7[0x20]; 6406 u8 match_dw_6[0x20]; 6407 u8 match_dw_5[0x20]; 6408 u8 match_dw_4[0x20]; 6409 u8 match_dw_3[0x20]; 6410 u8 match_dw_2[0x20]; 6411 u8 match_dw_1[0x20]; 6412 u8 match_dw_0[0x20]; 6413 6414 u8 match_byte_7[0x8]; 6415 u8 match_byte_6[0x8]; 6416 u8 match_byte_5[0x8]; 6417 u8 match_byte_4[0x8]; 6418 6419 u8 match_byte_3[0x8]; 6420 u8 match_byte_2[0x8]; 6421 u8 match_byte_1[0x8]; 6422 u8 match_byte_0[0x8]; 6423 }; 6424 6425 struct mlx5_ifc_match_definer_bits { 6426 u8 modify_field_select[0x40]; 6427 6428 u8 reserved_at_40[0x40]; 6429 6430 u8 reserved_at_80[0x10]; 6431 u8 format_id[0x10]; 6432 6433 u8 reserved_at_a0[0x60]; 6434 6435 u8 format_select_dw3[0x8]; 6436 u8 format_select_dw2[0x8]; 6437 u8 format_select_dw1[0x8]; 6438 u8 format_select_dw0[0x8]; 6439 6440 u8 format_select_dw7[0x8]; 6441 u8 format_select_dw6[0x8]; 6442 u8 format_select_dw5[0x8]; 6443 u8 format_select_dw4[0x8]; 6444 6445 u8 reserved_at_100[0x18]; 6446 u8 format_select_dw8[0x8]; 6447 6448 u8 reserved_at_120[0x20]; 6449 6450 u8 format_select_byte3[0x8]; 6451 u8 format_select_byte2[0x8]; 6452 u8 format_select_byte1[0x8]; 6453 u8 format_select_byte0[0x8]; 6454 6455 u8 format_select_byte7[0x8]; 6456 u8 format_select_byte6[0x8]; 6457 u8 format_select_byte5[0x8]; 6458 u8 format_select_byte4[0x8]; 6459 6460 u8 reserved_at_180[0x40]; 6461 6462 union { 6463 struct { 6464 u8 match_mask[16][0x20]; 6465 }; 6466 struct mlx5_ifc_match_definer_match_mask_bits match_mask_format; 6467 }; 6468 }; 6469 6470 struct mlx5_ifc_general_obj_create_param_bits { 6471 u8 alias_object[0x1]; 6472 u8 reserved_at_1[0x2]; 6473 u8 log_obj_range[0x5]; 6474 u8 reserved_at_8[0x18]; 6475 }; 6476 6477 struct mlx5_ifc_general_obj_query_param_bits { 6478 u8 alias_object[0x1]; 6479 u8 obj_offset[0x1f]; 6480 }; 6481 6482 struct mlx5_ifc_general_obj_in_cmd_hdr_bits { 6483 u8 opcode[0x10]; 6484 u8 uid[0x10]; 6485 6486 u8 vhca_tunnel_id[0x10]; 6487 u8 obj_type[0x10]; 6488 6489 u8 obj_id[0x20]; 6490 6491 union { 6492 struct mlx5_ifc_general_obj_create_param_bits create; 6493 struct mlx5_ifc_general_obj_query_param_bits query; 6494 } op_param; 6495 }; 6496 6497 struct mlx5_ifc_general_obj_out_cmd_hdr_bits { 6498 u8 status[0x8]; 6499 u8 reserved_at_8[0x18]; 6500 6501 u8 syndrome[0x20]; 6502 6503 u8 obj_id[0x20]; 6504 6505 u8 reserved_at_60[0x20]; 6506 }; 6507 6508 struct mlx5_ifc_allow_other_vhca_access_in_bits { 6509 u8 opcode[0x10]; 6510 u8 uid[0x10]; 6511 u8 reserved_at_20[0x10]; 6512 u8 op_mod[0x10]; 6513 u8 reserved_at_40[0x50]; 6514 u8 object_type_to_be_accessed[0x10]; 6515 u8 object_id_to_be_accessed[0x20]; 6516 u8 reserved_at_c0[0x40]; 6517 union { 6518 u8 access_key_raw[0x100]; 6519 u8 access_key[8][0x20]; 6520 }; 6521 }; 6522 6523 struct mlx5_ifc_allow_other_vhca_access_out_bits { 6524 u8 status[0x8]; 6525 u8 reserved_at_8[0x18]; 6526 u8 syndrome[0x20]; 6527 u8 reserved_at_40[0x40]; 6528 }; 6529 6530 struct mlx5_ifc_modify_header_arg_bits { 6531 u8 reserved_at_0[0x80]; 6532 6533 u8 reserved_at_80[0x8]; 6534 u8 access_pd[0x18]; 6535 }; 6536 6537 struct mlx5_ifc_create_modify_header_arg_in_bits { 6538 struct mlx5_ifc_general_obj_in_cmd_hdr_bits hdr; 6539 struct mlx5_ifc_modify_header_arg_bits arg; 6540 }; 6541 6542 struct mlx5_ifc_create_match_definer_in_bits { 6543 struct mlx5_ifc_general_obj_in_cmd_hdr_bits general_obj_in_cmd_hdr; 6544 6545 struct mlx5_ifc_match_definer_bits obj_context; 6546 }; 6547 6548 struct mlx5_ifc_create_match_definer_out_bits { 6549 struct mlx5_ifc_general_obj_out_cmd_hdr_bits general_obj_out_cmd_hdr; 6550 }; 6551 6552 struct mlx5_ifc_alias_context_bits { 6553 u8 vhca_id_to_be_accessed[0x10]; 6554 u8 reserved_at_10[0xd]; 6555 u8 status[0x3]; 6556 u8 object_id_to_be_accessed[0x20]; 6557 u8 reserved_at_40[0x40]; 6558 union { 6559 u8 access_key_raw[0x100]; 6560 u8 access_key[8][0x20]; 6561 }; 6562 u8 metadata[0x80]; 6563 }; 6564 6565 struct mlx5_ifc_create_alias_obj_in_bits { 6566 struct mlx5_ifc_general_obj_in_cmd_hdr_bits hdr; 6567 struct mlx5_ifc_alias_context_bits alias_ctx; 6568 }; 6569 6570 enum { 6571 MLX5_QUERY_FLOW_GROUP_OUT_MATCH_CRITERIA_ENABLE_OUTER_HEADERS = 0x0, 6572 MLX5_QUERY_FLOW_GROUP_OUT_MATCH_CRITERIA_ENABLE_MISC_PARAMETERS = 0x1, 6573 MLX5_QUERY_FLOW_GROUP_OUT_MATCH_CRITERIA_ENABLE_INNER_HEADERS = 0x2, 6574 MLX5_QUERY_FLOW_GROUP_IN_MATCH_CRITERIA_ENABLE_MISC_PARAMETERS_2 = 0x3, 6575 MLX5_QUERY_FLOW_GROUP_IN_MATCH_CRITERIA_ENABLE_MISC_PARAMETERS_3 = 0x4, 6576 MLX5_QUERY_FLOW_GROUP_IN_MATCH_CRITERIA_ENABLE_MISC_PARAMETERS_4 = 0x5, 6577 MLX5_QUERY_FLOW_GROUP_IN_MATCH_CRITERIA_ENABLE_MISC_PARAMETERS_5 = 0x6, 6578 }; 6579 6580 struct mlx5_ifc_query_flow_group_out_bits { 6581 u8 status[0x8]; 6582 u8 reserved_at_8[0x18]; 6583 6584 u8 syndrome[0x20]; 6585 6586 u8 reserved_at_40[0xa0]; 6587 6588 u8 start_flow_index[0x20]; 6589 6590 u8 reserved_at_100[0x20]; 6591 6592 u8 end_flow_index[0x20]; 6593 6594 u8 reserved_at_140[0xa0]; 6595 6596 u8 reserved_at_1e0[0x18]; 6597 u8 match_criteria_enable[0x8]; 6598 6599 struct mlx5_ifc_fte_match_param_bits match_criteria; 6600 6601 u8 reserved_at_1200[0xe00]; 6602 }; 6603 6604 struct mlx5_ifc_query_flow_group_in_bits { 6605 u8 opcode[0x10]; 6606 u8 reserved_at_10[0x10]; 6607 6608 u8 reserved_at_20[0x10]; 6609 u8 op_mod[0x10]; 6610 6611 u8 reserved_at_40[0x40]; 6612 6613 u8 table_type[0x8]; 6614 u8 reserved_at_88[0x18]; 6615 6616 u8 reserved_at_a0[0x8]; 6617 u8 table_id[0x18]; 6618 6619 u8 group_id[0x20]; 6620 6621 u8 reserved_at_e0[0x120]; 6622 }; 6623 6624 struct mlx5_ifc_query_flow_counter_out_bits { 6625 u8 status[0x8]; 6626 u8 reserved_at_8[0x18]; 6627 6628 u8 syndrome[0x20]; 6629 6630 u8 reserved_at_40[0x40]; 6631 6632 struct mlx5_ifc_traffic_counter_bits flow_statistics[]; 6633 }; 6634 6635 struct mlx5_ifc_query_flow_counter_in_bits { 6636 u8 opcode[0x10]; 6637 u8 reserved_at_10[0x10]; 6638 6639 u8 reserved_at_20[0x10]; 6640 u8 op_mod[0x10]; 6641 6642 u8 reserved_at_40[0x80]; 6643 6644 u8 clear[0x1]; 6645 u8 reserved_at_c1[0xf]; 6646 u8 num_of_counters[0x10]; 6647 6648 u8 flow_counter_id[0x20]; 6649 }; 6650 6651 struct mlx5_ifc_query_esw_vport_context_out_bits { 6652 u8 status[0x8]; 6653 u8 reserved_at_8[0x18]; 6654 6655 u8 syndrome[0x20]; 6656 6657 u8 reserved_at_40[0x40]; 6658 6659 struct mlx5_ifc_esw_vport_context_bits esw_vport_context; 6660 }; 6661 6662 struct mlx5_ifc_query_esw_vport_context_in_bits { 6663 u8 opcode[0x10]; 6664 u8 reserved_at_10[0x10]; 6665 6666 u8 reserved_at_20[0x10]; 6667 u8 op_mod[0x10]; 6668 6669 u8 other_vport[0x1]; 6670 u8 reserved_at_41[0xf]; 6671 u8 vport_number[0x10]; 6672 6673 u8 reserved_at_60[0x20]; 6674 }; 6675 6676 struct mlx5_ifc_modify_esw_vport_context_out_bits { 6677 u8 status[0x8]; 6678 u8 reserved_at_8[0x18]; 6679 6680 u8 syndrome[0x20]; 6681 6682 u8 reserved_at_40[0x40]; 6683 }; 6684 6685 struct mlx5_ifc_esw_vport_context_fields_select_bits { 6686 u8 reserved_at_0[0x1b]; 6687 u8 fdb_to_vport_reg_c_id[0x1]; 6688 u8 vport_cvlan_insert[0x1]; 6689 u8 vport_svlan_insert[0x1]; 6690 u8 vport_cvlan_strip[0x1]; 6691 u8 vport_svlan_strip[0x1]; 6692 }; 6693 6694 struct mlx5_ifc_modify_esw_vport_context_in_bits { 6695 u8 opcode[0x10]; 6696 u8 reserved_at_10[0x10]; 6697 6698 u8 reserved_at_20[0x10]; 6699 u8 op_mod[0x10]; 6700 6701 u8 other_vport[0x1]; 6702 u8 reserved_at_41[0xf]; 6703 u8 vport_number[0x10]; 6704 6705 struct mlx5_ifc_esw_vport_context_fields_select_bits field_select; 6706 6707 struct mlx5_ifc_esw_vport_context_bits esw_vport_context; 6708 }; 6709 6710 struct mlx5_ifc_query_eq_out_bits { 6711 u8 status[0x8]; 6712 u8 reserved_at_8[0x18]; 6713 6714 u8 syndrome[0x20]; 6715 6716 u8 reserved_at_40[0x40]; 6717 6718 struct mlx5_ifc_eqc_bits eq_context_entry; 6719 6720 u8 reserved_at_280[0x40]; 6721 6722 u8 event_bitmask[0x40]; 6723 6724 u8 reserved_at_300[0x580]; 6725 6726 u8 pas[][0x40]; 6727 }; 6728 6729 struct mlx5_ifc_query_eq_in_bits { 6730 u8 opcode[0x10]; 6731 u8 reserved_at_10[0x10]; 6732 6733 u8 reserved_at_20[0x10]; 6734 u8 op_mod[0x10]; 6735 6736 u8 reserved_at_40[0x18]; 6737 u8 eq_number[0x8]; 6738 6739 u8 reserved_at_60[0x20]; 6740 }; 6741 6742 struct mlx5_ifc_packet_reformat_context_in_bits { 6743 u8 reformat_type[0x8]; 6744 u8 reserved_at_8[0x4]; 6745 u8 reformat_param_0[0x4]; 6746 u8 reserved_at_10[0x6]; 6747 u8 reformat_data_size[0xa]; 6748 6749 u8 reformat_param_1[0x8]; 6750 u8 reserved_at_28[0x8]; 6751 u8 reformat_data[2][0x8]; 6752 6753 u8 more_reformat_data[][0x8]; 6754 }; 6755 6756 struct mlx5_ifc_query_packet_reformat_context_out_bits { 6757 u8 status[0x8]; 6758 u8 reserved_at_8[0x18]; 6759 6760 u8 syndrome[0x20]; 6761 6762 u8 reserved_at_40[0xa0]; 6763 6764 struct mlx5_ifc_packet_reformat_context_in_bits packet_reformat_context[]; 6765 }; 6766 6767 struct mlx5_ifc_query_packet_reformat_context_in_bits { 6768 u8 opcode[0x10]; 6769 u8 reserved_at_10[0x10]; 6770 6771 u8 reserved_at_20[0x10]; 6772 u8 op_mod[0x10]; 6773 6774 u8 packet_reformat_id[0x20]; 6775 6776 u8 reserved_at_60[0xa0]; 6777 }; 6778 6779 struct mlx5_ifc_alloc_packet_reformat_context_out_bits { 6780 u8 status[0x8]; 6781 u8 reserved_at_8[0x18]; 6782 6783 u8 syndrome[0x20]; 6784 6785 u8 packet_reformat_id[0x20]; 6786 6787 u8 reserved_at_60[0x20]; 6788 }; 6789 6790 enum { 6791 MLX5_REFORMAT_CONTEXT_ANCHOR_MAC_START = 0x1, 6792 MLX5_REFORMAT_CONTEXT_ANCHOR_IP_START = 0x7, 6793 MLX5_REFORMAT_CONTEXT_ANCHOR_TCP_UDP_START = 0x9, 6794 }; 6795 6796 enum mlx5_reformat_ctx_type { 6797 MLX5_REFORMAT_TYPE_L2_TO_VXLAN = 0x0, 6798 MLX5_REFORMAT_TYPE_L2_TO_NVGRE = 0x1, 6799 MLX5_REFORMAT_TYPE_L2_TO_L2_TUNNEL = 0x2, 6800 MLX5_REFORMAT_TYPE_L3_TUNNEL_TO_L2 = 0x3, 6801 MLX5_REFORMAT_TYPE_L2_TO_L3_TUNNEL = 0x4, 6802 MLX5_REFORMAT_TYPE_ADD_ESP_TRANSPORT_OVER_IPV4 = 0x5, 6803 MLX5_REFORMAT_TYPE_L2_TO_L3_ESP_TUNNEL = 0x6, 6804 MLX5_REFORMAT_TYPE_ADD_ESP_TRANSPORT_OVER_UDPV4 = 0x7, 6805 MLX5_REFORMAT_TYPE_DEL_ESP_TRANSPORT = 0x8, 6806 MLX5_REFORMAT_TYPE_L3_ESP_TUNNEL_TO_L2 = 0x9, 6807 MLX5_REFORMAT_TYPE_DEL_ESP_TRANSPORT_OVER_UDP = 0xa, 6808 MLX5_REFORMAT_TYPE_ADD_ESP_TRANSPORT_OVER_IPV6 = 0xb, 6809 MLX5_REFORMAT_TYPE_ADD_ESP_TRANSPORT_OVER_UDPV6 = 0xc, 6810 MLX5_REFORMAT_TYPE_INSERT_HDR = 0xf, 6811 MLX5_REFORMAT_TYPE_REMOVE_HDR = 0x10, 6812 MLX5_REFORMAT_TYPE_ADD_MACSEC = 0x11, 6813 MLX5_REFORMAT_TYPE_DEL_MACSEC = 0x12, 6814 }; 6815 6816 struct mlx5_ifc_alloc_packet_reformat_context_in_bits { 6817 u8 opcode[0x10]; 6818 u8 reserved_at_10[0x10]; 6819 6820 u8 reserved_at_20[0x10]; 6821 u8 op_mod[0x10]; 6822 6823 u8 reserved_at_40[0xa0]; 6824 6825 struct mlx5_ifc_packet_reformat_context_in_bits packet_reformat_context; 6826 }; 6827 6828 struct mlx5_ifc_dealloc_packet_reformat_context_out_bits { 6829 u8 status[0x8]; 6830 u8 reserved_at_8[0x18]; 6831 6832 u8 syndrome[0x20]; 6833 6834 u8 reserved_at_40[0x40]; 6835 }; 6836 6837 struct mlx5_ifc_dealloc_packet_reformat_context_in_bits { 6838 u8 opcode[0x10]; 6839 u8 reserved_at_10[0x10]; 6840 6841 u8 reserved_20[0x10]; 6842 u8 op_mod[0x10]; 6843 6844 u8 packet_reformat_id[0x20]; 6845 6846 u8 reserved_60[0x20]; 6847 }; 6848 6849 struct mlx5_ifc_set_action_in_bits { 6850 u8 action_type[0x4]; 6851 u8 field[0xc]; 6852 u8 reserved_at_10[0x3]; 6853 u8 offset[0x5]; 6854 u8 reserved_at_18[0x3]; 6855 u8 length[0x5]; 6856 6857 u8 data[0x20]; 6858 }; 6859 6860 struct mlx5_ifc_add_action_in_bits { 6861 u8 action_type[0x4]; 6862 u8 field[0xc]; 6863 u8 reserved_at_10[0x10]; 6864 6865 u8 data[0x20]; 6866 }; 6867 6868 struct mlx5_ifc_copy_action_in_bits { 6869 u8 action_type[0x4]; 6870 u8 src_field[0xc]; 6871 u8 reserved_at_10[0x3]; 6872 u8 src_offset[0x5]; 6873 u8 reserved_at_18[0x3]; 6874 u8 length[0x5]; 6875 6876 u8 reserved_at_20[0x4]; 6877 u8 dst_field[0xc]; 6878 u8 reserved_at_30[0x3]; 6879 u8 dst_offset[0x5]; 6880 u8 reserved_at_38[0x8]; 6881 }; 6882 6883 union mlx5_ifc_set_add_copy_action_in_auto_bits { 6884 struct mlx5_ifc_set_action_in_bits set_action_in; 6885 struct mlx5_ifc_add_action_in_bits add_action_in; 6886 struct mlx5_ifc_copy_action_in_bits copy_action_in; 6887 u8 reserved_at_0[0x40]; 6888 }; 6889 6890 enum { 6891 MLX5_ACTION_TYPE_SET = 0x1, 6892 MLX5_ACTION_TYPE_ADD = 0x2, 6893 MLX5_ACTION_TYPE_COPY = 0x3, 6894 }; 6895 6896 enum { 6897 MLX5_ACTION_IN_FIELD_OUT_SMAC_47_16 = 0x1, 6898 MLX5_ACTION_IN_FIELD_OUT_SMAC_15_0 = 0x2, 6899 MLX5_ACTION_IN_FIELD_OUT_ETHERTYPE = 0x3, 6900 MLX5_ACTION_IN_FIELD_OUT_DMAC_47_16 = 0x4, 6901 MLX5_ACTION_IN_FIELD_OUT_DMAC_15_0 = 0x5, 6902 MLX5_ACTION_IN_FIELD_OUT_IP_DSCP = 0x6, 6903 MLX5_ACTION_IN_FIELD_OUT_TCP_FLAGS = 0x7, 6904 MLX5_ACTION_IN_FIELD_OUT_TCP_SPORT = 0x8, 6905 MLX5_ACTION_IN_FIELD_OUT_TCP_DPORT = 0x9, 6906 MLX5_ACTION_IN_FIELD_OUT_IP_TTL = 0xa, 6907 MLX5_ACTION_IN_FIELD_OUT_UDP_SPORT = 0xb, 6908 MLX5_ACTION_IN_FIELD_OUT_UDP_DPORT = 0xc, 6909 MLX5_ACTION_IN_FIELD_OUT_SIPV6_127_96 = 0xd, 6910 MLX5_ACTION_IN_FIELD_OUT_SIPV6_95_64 = 0xe, 6911 MLX5_ACTION_IN_FIELD_OUT_SIPV6_63_32 = 0xf, 6912 MLX5_ACTION_IN_FIELD_OUT_SIPV6_31_0 = 0x10, 6913 MLX5_ACTION_IN_FIELD_OUT_DIPV6_127_96 = 0x11, 6914 MLX5_ACTION_IN_FIELD_OUT_DIPV6_95_64 = 0x12, 6915 MLX5_ACTION_IN_FIELD_OUT_DIPV6_63_32 = 0x13, 6916 MLX5_ACTION_IN_FIELD_OUT_DIPV6_31_0 = 0x14, 6917 MLX5_ACTION_IN_FIELD_OUT_SIPV4 = 0x15, 6918 MLX5_ACTION_IN_FIELD_OUT_DIPV4 = 0x16, 6919 MLX5_ACTION_IN_FIELD_OUT_FIRST_VID = 0x17, 6920 MLX5_ACTION_IN_FIELD_OUT_IPV6_HOPLIMIT = 0x47, 6921 MLX5_ACTION_IN_FIELD_METADATA_REG_A = 0x49, 6922 MLX5_ACTION_IN_FIELD_METADATA_REG_B = 0x50, 6923 MLX5_ACTION_IN_FIELD_METADATA_REG_C_0 = 0x51, 6924 MLX5_ACTION_IN_FIELD_METADATA_REG_C_1 = 0x52, 6925 MLX5_ACTION_IN_FIELD_METADATA_REG_C_2 = 0x53, 6926 MLX5_ACTION_IN_FIELD_METADATA_REG_C_3 = 0x54, 6927 MLX5_ACTION_IN_FIELD_METADATA_REG_C_4 = 0x55, 6928 MLX5_ACTION_IN_FIELD_METADATA_REG_C_5 = 0x56, 6929 MLX5_ACTION_IN_FIELD_METADATA_REG_C_6 = 0x57, 6930 MLX5_ACTION_IN_FIELD_METADATA_REG_C_7 = 0x58, 6931 MLX5_ACTION_IN_FIELD_OUT_TCP_SEQ_NUM = 0x59, 6932 MLX5_ACTION_IN_FIELD_OUT_TCP_ACK_NUM = 0x5B, 6933 MLX5_ACTION_IN_FIELD_IPSEC_SYNDROME = 0x5D, 6934 MLX5_ACTION_IN_FIELD_OUT_EMD_47_32 = 0x6F, 6935 MLX5_ACTION_IN_FIELD_OUT_EMD_31_0 = 0x70, 6936 }; 6937 6938 struct mlx5_ifc_alloc_modify_header_context_out_bits { 6939 u8 status[0x8]; 6940 u8 reserved_at_8[0x18]; 6941 6942 u8 syndrome[0x20]; 6943 6944 u8 modify_header_id[0x20]; 6945 6946 u8 reserved_at_60[0x20]; 6947 }; 6948 6949 struct mlx5_ifc_alloc_modify_header_context_in_bits { 6950 u8 opcode[0x10]; 6951 u8 reserved_at_10[0x10]; 6952 6953 u8 reserved_at_20[0x10]; 6954 u8 op_mod[0x10]; 6955 6956 u8 reserved_at_40[0x20]; 6957 6958 u8 table_type[0x8]; 6959 u8 reserved_at_68[0x10]; 6960 u8 num_of_actions[0x8]; 6961 6962 union mlx5_ifc_set_add_copy_action_in_auto_bits actions[]; 6963 }; 6964 6965 struct mlx5_ifc_dealloc_modify_header_context_out_bits { 6966 u8 status[0x8]; 6967 u8 reserved_at_8[0x18]; 6968 6969 u8 syndrome[0x20]; 6970 6971 u8 reserved_at_40[0x40]; 6972 }; 6973 6974 struct mlx5_ifc_dealloc_modify_header_context_in_bits { 6975 u8 opcode[0x10]; 6976 u8 reserved_at_10[0x10]; 6977 6978 u8 reserved_at_20[0x10]; 6979 u8 op_mod[0x10]; 6980 6981 u8 modify_header_id[0x20]; 6982 6983 u8 reserved_at_60[0x20]; 6984 }; 6985 6986 struct mlx5_ifc_query_modify_header_context_in_bits { 6987 u8 opcode[0x10]; 6988 u8 uid[0x10]; 6989 6990 u8 reserved_at_20[0x10]; 6991 u8 op_mod[0x10]; 6992 6993 u8 modify_header_id[0x20]; 6994 6995 u8 reserved_at_60[0xa0]; 6996 }; 6997 6998 struct mlx5_ifc_query_dct_out_bits { 6999 u8 status[0x8]; 7000 u8 reserved_at_8[0x18]; 7001 7002 u8 syndrome[0x20]; 7003 7004 u8 reserved_at_40[0x40]; 7005 7006 struct mlx5_ifc_dctc_bits dct_context_entry; 7007 7008 u8 reserved_at_280[0x180]; 7009 }; 7010 7011 struct mlx5_ifc_query_dct_in_bits { 7012 u8 opcode[0x10]; 7013 u8 reserved_at_10[0x10]; 7014 7015 u8 reserved_at_20[0x10]; 7016 u8 op_mod[0x10]; 7017 7018 u8 reserved_at_40[0x8]; 7019 u8 dctn[0x18]; 7020 7021 u8 reserved_at_60[0x20]; 7022 }; 7023 7024 struct mlx5_ifc_query_cq_out_bits { 7025 u8 status[0x8]; 7026 u8 reserved_at_8[0x18]; 7027 7028 u8 syndrome[0x20]; 7029 7030 u8 reserved_at_40[0x40]; 7031 7032 struct mlx5_ifc_cqc_bits cq_context; 7033 7034 u8 reserved_at_280[0x600]; 7035 7036 u8 pas[][0x40]; 7037 }; 7038 7039 struct mlx5_ifc_query_cq_in_bits { 7040 u8 opcode[0x10]; 7041 u8 reserved_at_10[0x10]; 7042 7043 u8 reserved_at_20[0x10]; 7044 u8 op_mod[0x10]; 7045 7046 u8 reserved_at_40[0x8]; 7047 u8 cqn[0x18]; 7048 7049 u8 reserved_at_60[0x20]; 7050 }; 7051 7052 struct mlx5_ifc_query_cong_status_out_bits { 7053 u8 status[0x8]; 7054 u8 reserved_at_8[0x18]; 7055 7056 u8 syndrome[0x20]; 7057 7058 u8 reserved_at_40[0x20]; 7059 7060 u8 enable[0x1]; 7061 u8 tag_enable[0x1]; 7062 u8 reserved_at_62[0x1e]; 7063 }; 7064 7065 struct mlx5_ifc_query_cong_status_in_bits { 7066 u8 opcode[0x10]; 7067 u8 reserved_at_10[0x10]; 7068 7069 u8 reserved_at_20[0x10]; 7070 u8 op_mod[0x10]; 7071 7072 u8 reserved_at_40[0x18]; 7073 u8 priority[0x4]; 7074 u8 cong_protocol[0x4]; 7075 7076 u8 reserved_at_60[0x20]; 7077 }; 7078 7079 struct mlx5_ifc_query_cong_statistics_out_bits { 7080 u8 status[0x8]; 7081 u8 reserved_at_8[0x18]; 7082 7083 u8 syndrome[0x20]; 7084 7085 u8 reserved_at_40[0x40]; 7086 7087 u8 rp_cur_flows[0x20]; 7088 7089 u8 sum_flows[0x20]; 7090 7091 u8 rp_cnp_ignored_high[0x20]; 7092 7093 u8 rp_cnp_ignored_low[0x20]; 7094 7095 u8 rp_cnp_handled_high[0x20]; 7096 7097 u8 rp_cnp_handled_low[0x20]; 7098 7099 u8 reserved_at_140[0x100]; 7100 7101 u8 time_stamp_high[0x20]; 7102 7103 u8 time_stamp_low[0x20]; 7104 7105 u8 accumulators_period[0x20]; 7106 7107 u8 np_ecn_marked_roce_packets_high[0x20]; 7108 7109 u8 np_ecn_marked_roce_packets_low[0x20]; 7110 7111 u8 np_cnp_sent_high[0x20]; 7112 7113 u8 np_cnp_sent_low[0x20]; 7114 7115 u8 reserved_at_320[0x560]; 7116 }; 7117 7118 struct mlx5_ifc_query_cong_statistics_in_bits { 7119 u8 opcode[0x10]; 7120 u8 reserved_at_10[0x10]; 7121 7122 u8 reserved_at_20[0x10]; 7123 u8 op_mod[0x10]; 7124 7125 u8 clear[0x1]; 7126 u8 reserved_at_41[0x1f]; 7127 7128 u8 reserved_at_60[0x20]; 7129 }; 7130 7131 struct mlx5_ifc_query_cong_params_out_bits { 7132 u8 status[0x8]; 7133 u8 reserved_at_8[0x18]; 7134 7135 u8 syndrome[0x20]; 7136 7137 u8 reserved_at_40[0x40]; 7138 7139 union mlx5_ifc_cong_control_roce_ecn_auto_bits congestion_parameters; 7140 }; 7141 7142 struct mlx5_ifc_query_cong_params_in_bits { 7143 u8 opcode[0x10]; 7144 u8 reserved_at_10[0x10]; 7145 7146 u8 reserved_at_20[0x10]; 7147 u8 op_mod[0x10]; 7148 7149 u8 reserved_at_40[0x1c]; 7150 u8 cong_protocol[0x4]; 7151 7152 u8 reserved_at_60[0x20]; 7153 }; 7154 7155 struct mlx5_ifc_query_adapter_out_bits { 7156 u8 status[0x8]; 7157 u8 reserved_at_8[0x18]; 7158 7159 u8 syndrome[0x20]; 7160 7161 u8 reserved_at_40[0x40]; 7162 7163 struct mlx5_ifc_query_adapter_param_block_bits query_adapter_struct; 7164 }; 7165 7166 struct mlx5_ifc_query_adapter_in_bits { 7167 u8 opcode[0x10]; 7168 u8 reserved_at_10[0x10]; 7169 7170 u8 reserved_at_20[0x10]; 7171 u8 op_mod[0x10]; 7172 7173 u8 reserved_at_40[0x40]; 7174 }; 7175 7176 struct mlx5_ifc_qp_2rst_out_bits { 7177 u8 status[0x8]; 7178 u8 reserved_at_8[0x18]; 7179 7180 u8 syndrome[0x20]; 7181 7182 u8 reserved_at_40[0x40]; 7183 }; 7184 7185 struct mlx5_ifc_qp_2rst_in_bits { 7186 u8 opcode[0x10]; 7187 u8 uid[0x10]; 7188 7189 u8 reserved_at_20[0x10]; 7190 u8 op_mod[0x10]; 7191 7192 u8 reserved_at_40[0x8]; 7193 u8 qpn[0x18]; 7194 7195 u8 reserved_at_60[0x20]; 7196 }; 7197 7198 struct mlx5_ifc_qp_2err_out_bits { 7199 u8 status[0x8]; 7200 u8 reserved_at_8[0x18]; 7201 7202 u8 syndrome[0x20]; 7203 7204 u8 reserved_at_40[0x40]; 7205 }; 7206 7207 struct mlx5_ifc_qp_2err_in_bits { 7208 u8 opcode[0x10]; 7209 u8 uid[0x10]; 7210 7211 u8 reserved_at_20[0x10]; 7212 u8 op_mod[0x10]; 7213 7214 u8 reserved_at_40[0x8]; 7215 u8 qpn[0x18]; 7216 7217 u8 reserved_at_60[0x20]; 7218 }; 7219 7220 struct mlx5_ifc_page_fault_resume_out_bits { 7221 u8 status[0x8]; 7222 u8 reserved_at_8[0x18]; 7223 7224 u8 syndrome[0x20]; 7225 7226 u8 reserved_at_40[0x40]; 7227 }; 7228 7229 struct mlx5_ifc_page_fault_resume_in_bits { 7230 u8 opcode[0x10]; 7231 u8 reserved_at_10[0x10]; 7232 7233 u8 reserved_at_20[0x10]; 7234 u8 op_mod[0x10]; 7235 7236 u8 error[0x1]; 7237 u8 reserved_at_41[0x4]; 7238 u8 page_fault_type[0x3]; 7239 u8 wq_number[0x18]; 7240 7241 u8 reserved_at_60[0x8]; 7242 u8 token[0x18]; 7243 }; 7244 7245 struct mlx5_ifc_nop_out_bits { 7246 u8 status[0x8]; 7247 u8 reserved_at_8[0x18]; 7248 7249 u8 syndrome[0x20]; 7250 7251 u8 reserved_at_40[0x40]; 7252 }; 7253 7254 struct mlx5_ifc_nop_in_bits { 7255 u8 opcode[0x10]; 7256 u8 reserved_at_10[0x10]; 7257 7258 u8 reserved_at_20[0x10]; 7259 u8 op_mod[0x10]; 7260 7261 u8 reserved_at_40[0x40]; 7262 }; 7263 7264 struct mlx5_ifc_modify_vport_state_out_bits { 7265 u8 status[0x8]; 7266 u8 reserved_at_8[0x18]; 7267 7268 u8 syndrome[0x20]; 7269 7270 u8 reserved_at_40[0x40]; 7271 }; 7272 7273 struct mlx5_ifc_modify_vport_state_in_bits { 7274 u8 opcode[0x10]; 7275 u8 reserved_at_10[0x10]; 7276 7277 u8 reserved_at_20[0x10]; 7278 u8 op_mod[0x10]; 7279 7280 u8 other_vport[0x1]; 7281 u8 reserved_at_41[0xf]; 7282 u8 vport_number[0x10]; 7283 7284 u8 reserved_at_60[0x18]; 7285 u8 admin_state[0x4]; 7286 u8 reserved_at_7c[0x4]; 7287 }; 7288 7289 struct mlx5_ifc_modify_tis_out_bits { 7290 u8 status[0x8]; 7291 u8 reserved_at_8[0x18]; 7292 7293 u8 syndrome[0x20]; 7294 7295 u8 reserved_at_40[0x40]; 7296 }; 7297 7298 struct mlx5_ifc_modify_tis_bitmask_bits { 7299 u8 reserved_at_0[0x20]; 7300 7301 u8 reserved_at_20[0x1d]; 7302 u8 lag_tx_port_affinity[0x1]; 7303 u8 strict_lag_tx_port_affinity[0x1]; 7304 u8 prio[0x1]; 7305 }; 7306 7307 struct mlx5_ifc_modify_tis_in_bits { 7308 u8 opcode[0x10]; 7309 u8 uid[0x10]; 7310 7311 u8 reserved_at_20[0x10]; 7312 u8 op_mod[0x10]; 7313 7314 u8 reserved_at_40[0x8]; 7315 u8 tisn[0x18]; 7316 7317 u8 reserved_at_60[0x20]; 7318 7319 struct mlx5_ifc_modify_tis_bitmask_bits bitmask; 7320 7321 u8 reserved_at_c0[0x40]; 7322 7323 struct mlx5_ifc_tisc_bits ctx; 7324 }; 7325 7326 struct mlx5_ifc_modify_tir_bitmask_bits { 7327 u8 reserved_at_0[0x20]; 7328 7329 u8 reserved_at_20[0x1b]; 7330 u8 self_lb_en[0x1]; 7331 u8 reserved_at_3c[0x1]; 7332 u8 hash[0x1]; 7333 u8 reserved_at_3e[0x1]; 7334 u8 packet_merge[0x1]; 7335 }; 7336 7337 struct mlx5_ifc_modify_tir_out_bits { 7338 u8 status[0x8]; 7339 u8 reserved_at_8[0x18]; 7340 7341 u8 syndrome[0x20]; 7342 7343 u8 reserved_at_40[0x40]; 7344 }; 7345 7346 struct mlx5_ifc_modify_tir_in_bits { 7347 u8 opcode[0x10]; 7348 u8 uid[0x10]; 7349 7350 u8 reserved_at_20[0x10]; 7351 u8 op_mod[0x10]; 7352 7353 u8 reserved_at_40[0x8]; 7354 u8 tirn[0x18]; 7355 7356 u8 reserved_at_60[0x20]; 7357 7358 struct mlx5_ifc_modify_tir_bitmask_bits bitmask; 7359 7360 u8 reserved_at_c0[0x40]; 7361 7362 struct mlx5_ifc_tirc_bits ctx; 7363 }; 7364 7365 struct mlx5_ifc_modify_sq_out_bits { 7366 u8 status[0x8]; 7367 u8 reserved_at_8[0x18]; 7368 7369 u8 syndrome[0x20]; 7370 7371 u8 reserved_at_40[0x40]; 7372 }; 7373 7374 struct mlx5_ifc_modify_sq_in_bits { 7375 u8 opcode[0x10]; 7376 u8 uid[0x10]; 7377 7378 u8 reserved_at_20[0x10]; 7379 u8 op_mod[0x10]; 7380 7381 u8 sq_state[0x4]; 7382 u8 reserved_at_44[0x4]; 7383 u8 sqn[0x18]; 7384 7385 u8 reserved_at_60[0x20]; 7386 7387 u8 modify_bitmask[0x40]; 7388 7389 u8 reserved_at_c0[0x40]; 7390 7391 struct mlx5_ifc_sqc_bits ctx; 7392 }; 7393 7394 struct mlx5_ifc_modify_scheduling_element_out_bits { 7395 u8 status[0x8]; 7396 u8 reserved_at_8[0x18]; 7397 7398 u8 syndrome[0x20]; 7399 7400 u8 reserved_at_40[0x1c0]; 7401 }; 7402 7403 enum { 7404 MODIFY_SCHEDULING_ELEMENT_IN_MODIFY_BITMASK_BW_SHARE = 0x1, 7405 MODIFY_SCHEDULING_ELEMENT_IN_MODIFY_BITMASK_MAX_AVERAGE_BW = 0x2, 7406 }; 7407 7408 struct mlx5_ifc_modify_scheduling_element_in_bits { 7409 u8 opcode[0x10]; 7410 u8 reserved_at_10[0x10]; 7411 7412 u8 reserved_at_20[0x10]; 7413 u8 op_mod[0x10]; 7414 7415 u8 scheduling_hierarchy[0x8]; 7416 u8 reserved_at_48[0x18]; 7417 7418 u8 scheduling_element_id[0x20]; 7419 7420 u8 reserved_at_80[0x20]; 7421 7422 u8 modify_bitmask[0x20]; 7423 7424 u8 reserved_at_c0[0x40]; 7425 7426 struct mlx5_ifc_scheduling_context_bits scheduling_context; 7427 7428 u8 reserved_at_300[0x100]; 7429 }; 7430 7431 struct mlx5_ifc_modify_rqt_out_bits { 7432 u8 status[0x8]; 7433 u8 reserved_at_8[0x18]; 7434 7435 u8 syndrome[0x20]; 7436 7437 u8 reserved_at_40[0x40]; 7438 }; 7439 7440 struct mlx5_ifc_rqt_bitmask_bits { 7441 u8 reserved_at_0[0x20]; 7442 7443 u8 reserved_at_20[0x1f]; 7444 u8 rqn_list[0x1]; 7445 }; 7446 7447 struct mlx5_ifc_modify_rqt_in_bits { 7448 u8 opcode[0x10]; 7449 u8 uid[0x10]; 7450 7451 u8 reserved_at_20[0x10]; 7452 u8 op_mod[0x10]; 7453 7454 u8 reserved_at_40[0x8]; 7455 u8 rqtn[0x18]; 7456 7457 u8 reserved_at_60[0x20]; 7458 7459 struct mlx5_ifc_rqt_bitmask_bits bitmask; 7460 7461 u8 reserved_at_c0[0x40]; 7462 7463 struct mlx5_ifc_rqtc_bits ctx; 7464 }; 7465 7466 struct mlx5_ifc_modify_rq_out_bits { 7467 u8 status[0x8]; 7468 u8 reserved_at_8[0x18]; 7469 7470 u8 syndrome[0x20]; 7471 7472 u8 reserved_at_40[0x40]; 7473 }; 7474 7475 enum { 7476 MLX5_MODIFY_RQ_IN_MODIFY_BITMASK_VSD = 1ULL << 1, 7477 MLX5_MODIFY_RQ_IN_MODIFY_BITMASK_SCATTER_FCS = 1ULL << 2, 7478 MLX5_MODIFY_RQ_IN_MODIFY_BITMASK_RQ_COUNTER_SET_ID = 1ULL << 3, 7479 }; 7480 7481 struct mlx5_ifc_modify_rq_in_bits { 7482 u8 opcode[0x10]; 7483 u8 uid[0x10]; 7484 7485 u8 reserved_at_20[0x10]; 7486 u8 op_mod[0x10]; 7487 7488 u8 rq_state[0x4]; 7489 u8 reserved_at_44[0x4]; 7490 u8 rqn[0x18]; 7491 7492 u8 reserved_at_60[0x20]; 7493 7494 u8 modify_bitmask[0x40]; 7495 7496 u8 reserved_at_c0[0x40]; 7497 7498 struct mlx5_ifc_rqc_bits ctx; 7499 }; 7500 7501 struct mlx5_ifc_modify_rmp_out_bits { 7502 u8 status[0x8]; 7503 u8 reserved_at_8[0x18]; 7504 7505 u8 syndrome[0x20]; 7506 7507 u8 reserved_at_40[0x40]; 7508 }; 7509 7510 struct mlx5_ifc_rmp_bitmask_bits { 7511 u8 reserved_at_0[0x20]; 7512 7513 u8 reserved_at_20[0x1f]; 7514 u8 lwm[0x1]; 7515 }; 7516 7517 struct mlx5_ifc_modify_rmp_in_bits { 7518 u8 opcode[0x10]; 7519 u8 uid[0x10]; 7520 7521 u8 reserved_at_20[0x10]; 7522 u8 op_mod[0x10]; 7523 7524 u8 rmp_state[0x4]; 7525 u8 reserved_at_44[0x4]; 7526 u8 rmpn[0x18]; 7527 7528 u8 reserved_at_60[0x20]; 7529 7530 struct mlx5_ifc_rmp_bitmask_bits bitmask; 7531 7532 u8 reserved_at_c0[0x40]; 7533 7534 struct mlx5_ifc_rmpc_bits ctx; 7535 }; 7536 7537 struct mlx5_ifc_modify_nic_vport_context_out_bits { 7538 u8 status[0x8]; 7539 u8 reserved_at_8[0x18]; 7540 7541 u8 syndrome[0x20]; 7542 7543 u8 reserved_at_40[0x40]; 7544 }; 7545 7546 struct mlx5_ifc_modify_nic_vport_field_select_bits { 7547 u8 reserved_at_0[0x12]; 7548 u8 affiliation[0x1]; 7549 u8 reserved_at_13[0x1]; 7550 u8 disable_uc_local_lb[0x1]; 7551 u8 disable_mc_local_lb[0x1]; 7552 u8 node_guid[0x1]; 7553 u8 port_guid[0x1]; 7554 u8 min_inline[0x1]; 7555 u8 mtu[0x1]; 7556 u8 change_event[0x1]; 7557 u8 promisc[0x1]; 7558 u8 permanent_address[0x1]; 7559 u8 addresses_list[0x1]; 7560 u8 roce_en[0x1]; 7561 u8 reserved_at_1f[0x1]; 7562 }; 7563 7564 struct mlx5_ifc_modify_nic_vport_context_in_bits { 7565 u8 opcode[0x10]; 7566 u8 reserved_at_10[0x10]; 7567 7568 u8 reserved_at_20[0x10]; 7569 u8 op_mod[0x10]; 7570 7571 u8 other_vport[0x1]; 7572 u8 reserved_at_41[0xf]; 7573 u8 vport_number[0x10]; 7574 7575 struct mlx5_ifc_modify_nic_vport_field_select_bits field_select; 7576 7577 u8 reserved_at_80[0x780]; 7578 7579 struct mlx5_ifc_nic_vport_context_bits nic_vport_context; 7580 }; 7581 7582 struct mlx5_ifc_modify_hca_vport_context_out_bits { 7583 u8 status[0x8]; 7584 u8 reserved_at_8[0x18]; 7585 7586 u8 syndrome[0x20]; 7587 7588 u8 reserved_at_40[0x40]; 7589 }; 7590 7591 struct mlx5_ifc_modify_hca_vport_context_in_bits { 7592 u8 opcode[0x10]; 7593 u8 reserved_at_10[0x10]; 7594 7595 u8 reserved_at_20[0x10]; 7596 u8 op_mod[0x10]; 7597 7598 u8 other_vport[0x1]; 7599 u8 reserved_at_41[0xb]; 7600 u8 port_num[0x4]; 7601 u8 vport_number[0x10]; 7602 7603 u8 reserved_at_60[0x20]; 7604 7605 struct mlx5_ifc_hca_vport_context_bits hca_vport_context; 7606 }; 7607 7608 struct mlx5_ifc_modify_cq_out_bits { 7609 u8 status[0x8]; 7610 u8 reserved_at_8[0x18]; 7611 7612 u8 syndrome[0x20]; 7613 7614 u8 reserved_at_40[0x40]; 7615 }; 7616 7617 enum { 7618 MLX5_MODIFY_CQ_IN_OP_MOD_MODIFY_CQ = 0x0, 7619 MLX5_MODIFY_CQ_IN_OP_MOD_RESIZE_CQ = 0x1, 7620 }; 7621 7622 struct mlx5_ifc_modify_cq_in_bits { 7623 u8 opcode[0x10]; 7624 u8 uid[0x10]; 7625 7626 u8 reserved_at_20[0x10]; 7627 u8 op_mod[0x10]; 7628 7629 u8 reserved_at_40[0x8]; 7630 u8 cqn[0x18]; 7631 7632 union mlx5_ifc_modify_field_select_resize_field_select_auto_bits modify_field_select_resize_field_select; 7633 7634 struct mlx5_ifc_cqc_bits cq_context; 7635 7636 u8 reserved_at_280[0x60]; 7637 7638 u8 cq_umem_valid[0x1]; 7639 u8 reserved_at_2e1[0x1f]; 7640 7641 u8 reserved_at_300[0x580]; 7642 7643 u8 pas[][0x40]; 7644 }; 7645 7646 struct mlx5_ifc_modify_cong_status_out_bits { 7647 u8 status[0x8]; 7648 u8 reserved_at_8[0x18]; 7649 7650 u8 syndrome[0x20]; 7651 7652 u8 reserved_at_40[0x40]; 7653 }; 7654 7655 struct mlx5_ifc_modify_cong_status_in_bits { 7656 u8 opcode[0x10]; 7657 u8 reserved_at_10[0x10]; 7658 7659 u8 reserved_at_20[0x10]; 7660 u8 op_mod[0x10]; 7661 7662 u8 reserved_at_40[0x18]; 7663 u8 priority[0x4]; 7664 u8 cong_protocol[0x4]; 7665 7666 u8 enable[0x1]; 7667 u8 tag_enable[0x1]; 7668 u8 reserved_at_62[0x1e]; 7669 }; 7670 7671 struct mlx5_ifc_modify_cong_params_out_bits { 7672 u8 status[0x8]; 7673 u8 reserved_at_8[0x18]; 7674 7675 u8 syndrome[0x20]; 7676 7677 u8 reserved_at_40[0x40]; 7678 }; 7679 7680 struct mlx5_ifc_modify_cong_params_in_bits { 7681 u8 opcode[0x10]; 7682 u8 reserved_at_10[0x10]; 7683 7684 u8 reserved_at_20[0x10]; 7685 u8 op_mod[0x10]; 7686 7687 u8 reserved_at_40[0x1c]; 7688 u8 cong_protocol[0x4]; 7689 7690 union mlx5_ifc_field_select_802_1_r_roce_auto_bits field_select; 7691 7692 u8 reserved_at_80[0x80]; 7693 7694 union mlx5_ifc_cong_control_roce_ecn_auto_bits congestion_parameters; 7695 }; 7696 7697 struct mlx5_ifc_manage_pages_out_bits { 7698 u8 status[0x8]; 7699 u8 reserved_at_8[0x18]; 7700 7701 u8 syndrome[0x20]; 7702 7703 u8 output_num_entries[0x20]; 7704 7705 u8 reserved_at_60[0x20]; 7706 7707 u8 pas[][0x40]; 7708 }; 7709 7710 enum { 7711 MLX5_MANAGE_PAGES_IN_OP_MOD_ALLOCATION_FAIL = 0x0, 7712 MLX5_MANAGE_PAGES_IN_OP_MOD_ALLOCATION_SUCCESS = 0x1, 7713 MLX5_MANAGE_PAGES_IN_OP_MOD_HCA_RETURN_PAGES = 0x2, 7714 }; 7715 7716 struct mlx5_ifc_manage_pages_in_bits { 7717 u8 opcode[0x10]; 7718 u8 reserved_at_10[0x10]; 7719 7720 u8 reserved_at_20[0x10]; 7721 u8 op_mod[0x10]; 7722 7723 u8 embedded_cpu_function[0x1]; 7724 u8 reserved_at_41[0xf]; 7725 u8 function_id[0x10]; 7726 7727 u8 input_num_entries[0x20]; 7728 7729 u8 pas[][0x40]; 7730 }; 7731 7732 struct mlx5_ifc_mad_ifc_out_bits { 7733 u8 status[0x8]; 7734 u8 reserved_at_8[0x18]; 7735 7736 u8 syndrome[0x20]; 7737 7738 u8 reserved_at_40[0x40]; 7739 7740 u8 response_mad_packet[256][0x8]; 7741 }; 7742 7743 struct mlx5_ifc_mad_ifc_in_bits { 7744 u8 opcode[0x10]; 7745 u8 reserved_at_10[0x10]; 7746 7747 u8 reserved_at_20[0x10]; 7748 u8 op_mod[0x10]; 7749 7750 u8 remote_lid[0x10]; 7751 u8 plane_index[0x8]; 7752 u8 port[0x8]; 7753 7754 u8 reserved_at_60[0x20]; 7755 7756 u8 mad[256][0x8]; 7757 }; 7758 7759 struct mlx5_ifc_init_hca_out_bits { 7760 u8 status[0x8]; 7761 u8 reserved_at_8[0x18]; 7762 7763 u8 syndrome[0x20]; 7764 7765 u8 reserved_at_40[0x40]; 7766 }; 7767 7768 struct mlx5_ifc_init_hca_in_bits { 7769 u8 opcode[0x10]; 7770 u8 reserved_at_10[0x10]; 7771 7772 u8 reserved_at_20[0x10]; 7773 u8 op_mod[0x10]; 7774 7775 u8 reserved_at_40[0x20]; 7776 7777 u8 reserved_at_60[0x2]; 7778 u8 sw_vhca_id[0xe]; 7779 u8 reserved_at_70[0x10]; 7780 7781 u8 sw_owner_id[4][0x20]; 7782 }; 7783 7784 struct mlx5_ifc_init2rtr_qp_out_bits { 7785 u8 status[0x8]; 7786 u8 reserved_at_8[0x18]; 7787 7788 u8 syndrome[0x20]; 7789 7790 u8 reserved_at_40[0x20]; 7791 u8 ece[0x20]; 7792 }; 7793 7794 struct mlx5_ifc_init2rtr_qp_in_bits { 7795 u8 opcode[0x10]; 7796 u8 uid[0x10]; 7797 7798 u8 reserved_at_20[0x10]; 7799 u8 op_mod[0x10]; 7800 7801 u8 reserved_at_40[0x8]; 7802 u8 qpn[0x18]; 7803 7804 u8 reserved_at_60[0x20]; 7805 7806 u8 opt_param_mask[0x20]; 7807 7808 u8 ece[0x20]; 7809 7810 struct mlx5_ifc_qpc_bits qpc; 7811 7812 u8 reserved_at_800[0x80]; 7813 }; 7814 7815 struct mlx5_ifc_init2init_qp_out_bits { 7816 u8 status[0x8]; 7817 u8 reserved_at_8[0x18]; 7818 7819 u8 syndrome[0x20]; 7820 7821 u8 reserved_at_40[0x20]; 7822 u8 ece[0x20]; 7823 }; 7824 7825 struct mlx5_ifc_init2init_qp_in_bits { 7826 u8 opcode[0x10]; 7827 u8 uid[0x10]; 7828 7829 u8 reserved_at_20[0x10]; 7830 u8 op_mod[0x10]; 7831 7832 u8 reserved_at_40[0x8]; 7833 u8 qpn[0x18]; 7834 7835 u8 reserved_at_60[0x20]; 7836 7837 u8 opt_param_mask[0x20]; 7838 7839 u8 ece[0x20]; 7840 7841 struct mlx5_ifc_qpc_bits qpc; 7842 7843 u8 reserved_at_800[0x80]; 7844 }; 7845 7846 struct mlx5_ifc_get_dropped_packet_log_out_bits { 7847 u8 status[0x8]; 7848 u8 reserved_at_8[0x18]; 7849 7850 u8 syndrome[0x20]; 7851 7852 u8 reserved_at_40[0x40]; 7853 7854 u8 packet_headers_log[128][0x8]; 7855 7856 u8 packet_syndrome[64][0x8]; 7857 }; 7858 7859 struct mlx5_ifc_get_dropped_packet_log_in_bits { 7860 u8 opcode[0x10]; 7861 u8 reserved_at_10[0x10]; 7862 7863 u8 reserved_at_20[0x10]; 7864 u8 op_mod[0x10]; 7865 7866 u8 reserved_at_40[0x40]; 7867 }; 7868 7869 struct mlx5_ifc_gen_eqe_in_bits { 7870 u8 opcode[0x10]; 7871 u8 reserved_at_10[0x10]; 7872 7873 u8 reserved_at_20[0x10]; 7874 u8 op_mod[0x10]; 7875 7876 u8 reserved_at_40[0x18]; 7877 u8 eq_number[0x8]; 7878 7879 u8 reserved_at_60[0x20]; 7880 7881 u8 eqe[64][0x8]; 7882 }; 7883 7884 struct mlx5_ifc_gen_eq_out_bits { 7885 u8 status[0x8]; 7886 u8 reserved_at_8[0x18]; 7887 7888 u8 syndrome[0x20]; 7889 7890 u8 reserved_at_40[0x40]; 7891 }; 7892 7893 struct mlx5_ifc_enable_hca_out_bits { 7894 u8 status[0x8]; 7895 u8 reserved_at_8[0x18]; 7896 7897 u8 syndrome[0x20]; 7898 7899 u8 reserved_at_40[0x20]; 7900 }; 7901 7902 struct mlx5_ifc_enable_hca_in_bits { 7903 u8 opcode[0x10]; 7904 u8 reserved_at_10[0x10]; 7905 7906 u8 reserved_at_20[0x10]; 7907 u8 op_mod[0x10]; 7908 7909 u8 embedded_cpu_function[0x1]; 7910 u8 reserved_at_41[0xf]; 7911 u8 function_id[0x10]; 7912 7913 u8 reserved_at_60[0x20]; 7914 }; 7915 7916 struct mlx5_ifc_drain_dct_out_bits { 7917 u8 status[0x8]; 7918 u8 reserved_at_8[0x18]; 7919 7920 u8 syndrome[0x20]; 7921 7922 u8 reserved_at_40[0x40]; 7923 }; 7924 7925 struct mlx5_ifc_drain_dct_in_bits { 7926 u8 opcode[0x10]; 7927 u8 uid[0x10]; 7928 7929 u8 reserved_at_20[0x10]; 7930 u8 op_mod[0x10]; 7931 7932 u8 reserved_at_40[0x8]; 7933 u8 dctn[0x18]; 7934 7935 u8 reserved_at_60[0x20]; 7936 }; 7937 7938 struct mlx5_ifc_disable_hca_out_bits { 7939 u8 status[0x8]; 7940 u8 reserved_at_8[0x18]; 7941 7942 u8 syndrome[0x20]; 7943 7944 u8 reserved_at_40[0x20]; 7945 }; 7946 7947 struct mlx5_ifc_disable_hca_in_bits { 7948 u8 opcode[0x10]; 7949 u8 reserved_at_10[0x10]; 7950 7951 u8 reserved_at_20[0x10]; 7952 u8 op_mod[0x10]; 7953 7954 u8 embedded_cpu_function[0x1]; 7955 u8 reserved_at_41[0xf]; 7956 u8 function_id[0x10]; 7957 7958 u8 reserved_at_60[0x20]; 7959 }; 7960 7961 struct mlx5_ifc_detach_from_mcg_out_bits { 7962 u8 status[0x8]; 7963 u8 reserved_at_8[0x18]; 7964 7965 u8 syndrome[0x20]; 7966 7967 u8 reserved_at_40[0x40]; 7968 }; 7969 7970 struct mlx5_ifc_detach_from_mcg_in_bits { 7971 u8 opcode[0x10]; 7972 u8 uid[0x10]; 7973 7974 u8 reserved_at_20[0x10]; 7975 u8 op_mod[0x10]; 7976 7977 u8 reserved_at_40[0x8]; 7978 u8 qpn[0x18]; 7979 7980 u8 reserved_at_60[0x20]; 7981 7982 u8 multicast_gid[16][0x8]; 7983 }; 7984 7985 struct mlx5_ifc_destroy_xrq_out_bits { 7986 u8 status[0x8]; 7987 u8 reserved_at_8[0x18]; 7988 7989 u8 syndrome[0x20]; 7990 7991 u8 reserved_at_40[0x40]; 7992 }; 7993 7994 struct mlx5_ifc_destroy_xrq_in_bits { 7995 u8 opcode[0x10]; 7996 u8 uid[0x10]; 7997 7998 u8 reserved_at_20[0x10]; 7999 u8 op_mod[0x10]; 8000 8001 u8 reserved_at_40[0x8]; 8002 u8 xrqn[0x18]; 8003 8004 u8 reserved_at_60[0x20]; 8005 }; 8006 8007 struct mlx5_ifc_destroy_xrc_srq_out_bits { 8008 u8 status[0x8]; 8009 u8 reserved_at_8[0x18]; 8010 8011 u8 syndrome[0x20]; 8012 8013 u8 reserved_at_40[0x40]; 8014 }; 8015 8016 struct mlx5_ifc_destroy_xrc_srq_in_bits { 8017 u8 opcode[0x10]; 8018 u8 uid[0x10]; 8019 8020 u8 reserved_at_20[0x10]; 8021 u8 op_mod[0x10]; 8022 8023 u8 reserved_at_40[0x8]; 8024 u8 xrc_srqn[0x18]; 8025 8026 u8 reserved_at_60[0x20]; 8027 }; 8028 8029 struct mlx5_ifc_destroy_tis_out_bits { 8030 u8 status[0x8]; 8031 u8 reserved_at_8[0x18]; 8032 8033 u8 syndrome[0x20]; 8034 8035 u8 reserved_at_40[0x40]; 8036 }; 8037 8038 struct mlx5_ifc_destroy_tis_in_bits { 8039 u8 opcode[0x10]; 8040 u8 uid[0x10]; 8041 8042 u8 reserved_at_20[0x10]; 8043 u8 op_mod[0x10]; 8044 8045 u8 reserved_at_40[0x8]; 8046 u8 tisn[0x18]; 8047 8048 u8 reserved_at_60[0x20]; 8049 }; 8050 8051 struct mlx5_ifc_destroy_tir_out_bits { 8052 u8 status[0x8]; 8053 u8 reserved_at_8[0x18]; 8054 8055 u8 syndrome[0x20]; 8056 8057 u8 reserved_at_40[0x40]; 8058 }; 8059 8060 struct mlx5_ifc_destroy_tir_in_bits { 8061 u8 opcode[0x10]; 8062 u8 uid[0x10]; 8063 8064 u8 reserved_at_20[0x10]; 8065 u8 op_mod[0x10]; 8066 8067 u8 reserved_at_40[0x8]; 8068 u8 tirn[0x18]; 8069 8070 u8 reserved_at_60[0x20]; 8071 }; 8072 8073 struct mlx5_ifc_destroy_srq_out_bits { 8074 u8 status[0x8]; 8075 u8 reserved_at_8[0x18]; 8076 8077 u8 syndrome[0x20]; 8078 8079 u8 reserved_at_40[0x40]; 8080 }; 8081 8082 struct mlx5_ifc_destroy_srq_in_bits { 8083 u8 opcode[0x10]; 8084 u8 uid[0x10]; 8085 8086 u8 reserved_at_20[0x10]; 8087 u8 op_mod[0x10]; 8088 8089 u8 reserved_at_40[0x8]; 8090 u8 srqn[0x18]; 8091 8092 u8 reserved_at_60[0x20]; 8093 }; 8094 8095 struct mlx5_ifc_destroy_sq_out_bits { 8096 u8 status[0x8]; 8097 u8 reserved_at_8[0x18]; 8098 8099 u8 syndrome[0x20]; 8100 8101 u8 reserved_at_40[0x40]; 8102 }; 8103 8104 struct mlx5_ifc_destroy_sq_in_bits { 8105 u8 opcode[0x10]; 8106 u8 uid[0x10]; 8107 8108 u8 reserved_at_20[0x10]; 8109 u8 op_mod[0x10]; 8110 8111 u8 reserved_at_40[0x8]; 8112 u8 sqn[0x18]; 8113 8114 u8 reserved_at_60[0x20]; 8115 }; 8116 8117 struct mlx5_ifc_destroy_scheduling_element_out_bits { 8118 u8 status[0x8]; 8119 u8 reserved_at_8[0x18]; 8120 8121 u8 syndrome[0x20]; 8122 8123 u8 reserved_at_40[0x1c0]; 8124 }; 8125 8126 struct mlx5_ifc_destroy_scheduling_element_in_bits { 8127 u8 opcode[0x10]; 8128 u8 reserved_at_10[0x10]; 8129 8130 u8 reserved_at_20[0x10]; 8131 u8 op_mod[0x10]; 8132 8133 u8 scheduling_hierarchy[0x8]; 8134 u8 reserved_at_48[0x18]; 8135 8136 u8 scheduling_element_id[0x20]; 8137 8138 u8 reserved_at_80[0x180]; 8139 }; 8140 8141 struct mlx5_ifc_destroy_rqt_out_bits { 8142 u8 status[0x8]; 8143 u8 reserved_at_8[0x18]; 8144 8145 u8 syndrome[0x20]; 8146 8147 u8 reserved_at_40[0x40]; 8148 }; 8149 8150 struct mlx5_ifc_destroy_rqt_in_bits { 8151 u8 opcode[0x10]; 8152 u8 uid[0x10]; 8153 8154 u8 reserved_at_20[0x10]; 8155 u8 op_mod[0x10]; 8156 8157 u8 reserved_at_40[0x8]; 8158 u8 rqtn[0x18]; 8159 8160 u8 reserved_at_60[0x20]; 8161 }; 8162 8163 struct mlx5_ifc_destroy_rq_out_bits { 8164 u8 status[0x8]; 8165 u8 reserved_at_8[0x18]; 8166 8167 u8 syndrome[0x20]; 8168 8169 u8 reserved_at_40[0x40]; 8170 }; 8171 8172 struct mlx5_ifc_destroy_rq_in_bits { 8173 u8 opcode[0x10]; 8174 u8 uid[0x10]; 8175 8176 u8 reserved_at_20[0x10]; 8177 u8 op_mod[0x10]; 8178 8179 u8 reserved_at_40[0x8]; 8180 u8 rqn[0x18]; 8181 8182 u8 reserved_at_60[0x20]; 8183 }; 8184 8185 struct mlx5_ifc_set_delay_drop_params_in_bits { 8186 u8 opcode[0x10]; 8187 u8 reserved_at_10[0x10]; 8188 8189 u8 reserved_at_20[0x10]; 8190 u8 op_mod[0x10]; 8191 8192 u8 reserved_at_40[0x20]; 8193 8194 u8 reserved_at_60[0x10]; 8195 u8 delay_drop_timeout[0x10]; 8196 }; 8197 8198 struct mlx5_ifc_set_delay_drop_params_out_bits { 8199 u8 status[0x8]; 8200 u8 reserved_at_8[0x18]; 8201 8202 u8 syndrome[0x20]; 8203 8204 u8 reserved_at_40[0x40]; 8205 }; 8206 8207 struct mlx5_ifc_destroy_rmp_out_bits { 8208 u8 status[0x8]; 8209 u8 reserved_at_8[0x18]; 8210 8211 u8 syndrome[0x20]; 8212 8213 u8 reserved_at_40[0x40]; 8214 }; 8215 8216 struct mlx5_ifc_destroy_rmp_in_bits { 8217 u8 opcode[0x10]; 8218 u8 uid[0x10]; 8219 8220 u8 reserved_at_20[0x10]; 8221 u8 op_mod[0x10]; 8222 8223 u8 reserved_at_40[0x8]; 8224 u8 rmpn[0x18]; 8225 8226 u8 reserved_at_60[0x20]; 8227 }; 8228 8229 struct mlx5_ifc_destroy_qp_out_bits { 8230 u8 status[0x8]; 8231 u8 reserved_at_8[0x18]; 8232 8233 u8 syndrome[0x20]; 8234 8235 u8 reserved_at_40[0x40]; 8236 }; 8237 8238 struct mlx5_ifc_destroy_qp_in_bits { 8239 u8 opcode[0x10]; 8240 u8 uid[0x10]; 8241 8242 u8 reserved_at_20[0x10]; 8243 u8 op_mod[0x10]; 8244 8245 u8 reserved_at_40[0x8]; 8246 u8 qpn[0x18]; 8247 8248 u8 reserved_at_60[0x20]; 8249 }; 8250 8251 struct mlx5_ifc_destroy_psv_out_bits { 8252 u8 status[0x8]; 8253 u8 reserved_at_8[0x18]; 8254 8255 u8 syndrome[0x20]; 8256 8257 u8 reserved_at_40[0x40]; 8258 }; 8259 8260 struct mlx5_ifc_destroy_psv_in_bits { 8261 u8 opcode[0x10]; 8262 u8 reserved_at_10[0x10]; 8263 8264 u8 reserved_at_20[0x10]; 8265 u8 op_mod[0x10]; 8266 8267 u8 reserved_at_40[0x8]; 8268 u8 psvn[0x18]; 8269 8270 u8 reserved_at_60[0x20]; 8271 }; 8272 8273 struct mlx5_ifc_destroy_mkey_out_bits { 8274 u8 status[0x8]; 8275 u8 reserved_at_8[0x18]; 8276 8277 u8 syndrome[0x20]; 8278 8279 u8 reserved_at_40[0x40]; 8280 }; 8281 8282 struct mlx5_ifc_destroy_mkey_in_bits { 8283 u8 opcode[0x10]; 8284 u8 uid[0x10]; 8285 8286 u8 reserved_at_20[0x10]; 8287 u8 op_mod[0x10]; 8288 8289 u8 reserved_at_40[0x8]; 8290 u8 mkey_index[0x18]; 8291 8292 u8 reserved_at_60[0x20]; 8293 }; 8294 8295 struct mlx5_ifc_destroy_flow_table_out_bits { 8296 u8 status[0x8]; 8297 u8 reserved_at_8[0x18]; 8298 8299 u8 syndrome[0x20]; 8300 8301 u8 reserved_at_40[0x40]; 8302 }; 8303 8304 struct mlx5_ifc_destroy_flow_table_in_bits { 8305 u8 opcode[0x10]; 8306 u8 reserved_at_10[0x10]; 8307 8308 u8 reserved_at_20[0x10]; 8309 u8 op_mod[0x10]; 8310 8311 u8 other_vport[0x1]; 8312 u8 reserved_at_41[0xf]; 8313 u8 vport_number[0x10]; 8314 8315 u8 reserved_at_60[0x20]; 8316 8317 u8 table_type[0x8]; 8318 u8 reserved_at_88[0x18]; 8319 8320 u8 reserved_at_a0[0x8]; 8321 u8 table_id[0x18]; 8322 8323 u8 reserved_at_c0[0x140]; 8324 }; 8325 8326 struct mlx5_ifc_destroy_flow_group_out_bits { 8327 u8 status[0x8]; 8328 u8 reserved_at_8[0x18]; 8329 8330 u8 syndrome[0x20]; 8331 8332 u8 reserved_at_40[0x40]; 8333 }; 8334 8335 struct mlx5_ifc_destroy_flow_group_in_bits { 8336 u8 opcode[0x10]; 8337 u8 reserved_at_10[0x10]; 8338 8339 u8 reserved_at_20[0x10]; 8340 u8 op_mod[0x10]; 8341 8342 u8 other_vport[0x1]; 8343 u8 reserved_at_41[0xf]; 8344 u8 vport_number[0x10]; 8345 8346 u8 reserved_at_60[0x20]; 8347 8348 u8 table_type[0x8]; 8349 u8 reserved_at_88[0x18]; 8350 8351 u8 reserved_at_a0[0x8]; 8352 u8 table_id[0x18]; 8353 8354 u8 group_id[0x20]; 8355 8356 u8 reserved_at_e0[0x120]; 8357 }; 8358 8359 struct mlx5_ifc_destroy_eq_out_bits { 8360 u8 status[0x8]; 8361 u8 reserved_at_8[0x18]; 8362 8363 u8 syndrome[0x20]; 8364 8365 u8 reserved_at_40[0x40]; 8366 }; 8367 8368 struct mlx5_ifc_destroy_eq_in_bits { 8369 u8 opcode[0x10]; 8370 u8 reserved_at_10[0x10]; 8371 8372 u8 reserved_at_20[0x10]; 8373 u8 op_mod[0x10]; 8374 8375 u8 reserved_at_40[0x18]; 8376 u8 eq_number[0x8]; 8377 8378 u8 reserved_at_60[0x20]; 8379 }; 8380 8381 struct mlx5_ifc_destroy_dct_out_bits { 8382 u8 status[0x8]; 8383 u8 reserved_at_8[0x18]; 8384 8385 u8 syndrome[0x20]; 8386 8387 u8 reserved_at_40[0x40]; 8388 }; 8389 8390 struct mlx5_ifc_destroy_dct_in_bits { 8391 u8 opcode[0x10]; 8392 u8 uid[0x10]; 8393 8394 u8 reserved_at_20[0x10]; 8395 u8 op_mod[0x10]; 8396 8397 u8 reserved_at_40[0x8]; 8398 u8 dctn[0x18]; 8399 8400 u8 reserved_at_60[0x20]; 8401 }; 8402 8403 struct mlx5_ifc_destroy_cq_out_bits { 8404 u8 status[0x8]; 8405 u8 reserved_at_8[0x18]; 8406 8407 u8 syndrome[0x20]; 8408 8409 u8 reserved_at_40[0x40]; 8410 }; 8411 8412 struct mlx5_ifc_destroy_cq_in_bits { 8413 u8 opcode[0x10]; 8414 u8 uid[0x10]; 8415 8416 u8 reserved_at_20[0x10]; 8417 u8 op_mod[0x10]; 8418 8419 u8 reserved_at_40[0x8]; 8420 u8 cqn[0x18]; 8421 8422 u8 reserved_at_60[0x20]; 8423 }; 8424 8425 struct mlx5_ifc_delete_vxlan_udp_dport_out_bits { 8426 u8 status[0x8]; 8427 u8 reserved_at_8[0x18]; 8428 8429 u8 syndrome[0x20]; 8430 8431 u8 reserved_at_40[0x40]; 8432 }; 8433 8434 struct mlx5_ifc_delete_vxlan_udp_dport_in_bits { 8435 u8 opcode[0x10]; 8436 u8 reserved_at_10[0x10]; 8437 8438 u8 reserved_at_20[0x10]; 8439 u8 op_mod[0x10]; 8440 8441 u8 reserved_at_40[0x20]; 8442 8443 u8 reserved_at_60[0x10]; 8444 u8 vxlan_udp_port[0x10]; 8445 }; 8446 8447 struct mlx5_ifc_delete_l2_table_entry_out_bits { 8448 u8 status[0x8]; 8449 u8 reserved_at_8[0x18]; 8450 8451 u8 syndrome[0x20]; 8452 8453 u8 reserved_at_40[0x40]; 8454 }; 8455 8456 struct mlx5_ifc_delete_l2_table_entry_in_bits { 8457 u8 opcode[0x10]; 8458 u8 reserved_at_10[0x10]; 8459 8460 u8 reserved_at_20[0x10]; 8461 u8 op_mod[0x10]; 8462 8463 u8 reserved_at_40[0x60]; 8464 8465 u8 reserved_at_a0[0x8]; 8466 u8 table_index[0x18]; 8467 8468 u8 reserved_at_c0[0x140]; 8469 }; 8470 8471 struct mlx5_ifc_delete_fte_out_bits { 8472 u8 status[0x8]; 8473 u8 reserved_at_8[0x18]; 8474 8475 u8 syndrome[0x20]; 8476 8477 u8 reserved_at_40[0x40]; 8478 }; 8479 8480 struct mlx5_ifc_delete_fte_in_bits { 8481 u8 opcode[0x10]; 8482 u8 reserved_at_10[0x10]; 8483 8484 u8 reserved_at_20[0x10]; 8485 u8 op_mod[0x10]; 8486 8487 u8 other_vport[0x1]; 8488 u8 reserved_at_41[0xf]; 8489 u8 vport_number[0x10]; 8490 8491 u8 reserved_at_60[0x20]; 8492 8493 u8 table_type[0x8]; 8494 u8 reserved_at_88[0x18]; 8495 8496 u8 reserved_at_a0[0x8]; 8497 u8 table_id[0x18]; 8498 8499 u8 reserved_at_c0[0x40]; 8500 8501 u8 flow_index[0x20]; 8502 8503 u8 reserved_at_120[0xe0]; 8504 }; 8505 8506 struct mlx5_ifc_dealloc_xrcd_out_bits { 8507 u8 status[0x8]; 8508 u8 reserved_at_8[0x18]; 8509 8510 u8 syndrome[0x20]; 8511 8512 u8 reserved_at_40[0x40]; 8513 }; 8514 8515 struct mlx5_ifc_dealloc_xrcd_in_bits { 8516 u8 opcode[0x10]; 8517 u8 uid[0x10]; 8518 8519 u8 reserved_at_20[0x10]; 8520 u8 op_mod[0x10]; 8521 8522 u8 reserved_at_40[0x8]; 8523 u8 xrcd[0x18]; 8524 8525 u8 reserved_at_60[0x20]; 8526 }; 8527 8528 struct mlx5_ifc_dealloc_uar_out_bits { 8529 u8 status[0x8]; 8530 u8 reserved_at_8[0x18]; 8531 8532 u8 syndrome[0x20]; 8533 8534 u8 reserved_at_40[0x40]; 8535 }; 8536 8537 struct mlx5_ifc_dealloc_uar_in_bits { 8538 u8 opcode[0x10]; 8539 u8 uid[0x10]; 8540 8541 u8 reserved_at_20[0x10]; 8542 u8 op_mod[0x10]; 8543 8544 u8 reserved_at_40[0x8]; 8545 u8 uar[0x18]; 8546 8547 u8 reserved_at_60[0x20]; 8548 }; 8549 8550 struct mlx5_ifc_dealloc_transport_domain_out_bits { 8551 u8 status[0x8]; 8552 u8 reserved_at_8[0x18]; 8553 8554 u8 syndrome[0x20]; 8555 8556 u8 reserved_at_40[0x40]; 8557 }; 8558 8559 struct mlx5_ifc_dealloc_transport_domain_in_bits { 8560 u8 opcode[0x10]; 8561 u8 uid[0x10]; 8562 8563 u8 reserved_at_20[0x10]; 8564 u8 op_mod[0x10]; 8565 8566 u8 reserved_at_40[0x8]; 8567 u8 transport_domain[0x18]; 8568 8569 u8 reserved_at_60[0x20]; 8570 }; 8571 8572 struct mlx5_ifc_dealloc_q_counter_out_bits { 8573 u8 status[0x8]; 8574 u8 reserved_at_8[0x18]; 8575 8576 u8 syndrome[0x20]; 8577 8578 u8 reserved_at_40[0x40]; 8579 }; 8580 8581 struct mlx5_ifc_dealloc_q_counter_in_bits { 8582 u8 opcode[0x10]; 8583 u8 reserved_at_10[0x10]; 8584 8585 u8 reserved_at_20[0x10]; 8586 u8 op_mod[0x10]; 8587 8588 u8 reserved_at_40[0x18]; 8589 u8 counter_set_id[0x8]; 8590 8591 u8 reserved_at_60[0x20]; 8592 }; 8593 8594 struct mlx5_ifc_dealloc_pd_out_bits { 8595 u8 status[0x8]; 8596 u8 reserved_at_8[0x18]; 8597 8598 u8 syndrome[0x20]; 8599 8600 u8 reserved_at_40[0x40]; 8601 }; 8602 8603 struct mlx5_ifc_dealloc_pd_in_bits { 8604 u8 opcode[0x10]; 8605 u8 uid[0x10]; 8606 8607 u8 reserved_at_20[0x10]; 8608 u8 op_mod[0x10]; 8609 8610 u8 reserved_at_40[0x8]; 8611 u8 pd[0x18]; 8612 8613 u8 reserved_at_60[0x20]; 8614 }; 8615 8616 struct mlx5_ifc_dealloc_flow_counter_out_bits { 8617 u8 status[0x8]; 8618 u8 reserved_at_8[0x18]; 8619 8620 u8 syndrome[0x20]; 8621 8622 u8 reserved_at_40[0x40]; 8623 }; 8624 8625 struct mlx5_ifc_dealloc_flow_counter_in_bits { 8626 u8 opcode[0x10]; 8627 u8 reserved_at_10[0x10]; 8628 8629 u8 reserved_at_20[0x10]; 8630 u8 op_mod[0x10]; 8631 8632 u8 flow_counter_id[0x20]; 8633 8634 u8 reserved_at_60[0x20]; 8635 }; 8636 8637 struct mlx5_ifc_create_xrq_out_bits { 8638 u8 status[0x8]; 8639 u8 reserved_at_8[0x18]; 8640 8641 u8 syndrome[0x20]; 8642 8643 u8 reserved_at_40[0x8]; 8644 u8 xrqn[0x18]; 8645 8646 u8 reserved_at_60[0x20]; 8647 }; 8648 8649 struct mlx5_ifc_create_xrq_in_bits { 8650 u8 opcode[0x10]; 8651 u8 uid[0x10]; 8652 8653 u8 reserved_at_20[0x10]; 8654 u8 op_mod[0x10]; 8655 8656 u8 reserved_at_40[0x40]; 8657 8658 struct mlx5_ifc_xrqc_bits xrq_context; 8659 }; 8660 8661 struct mlx5_ifc_create_xrc_srq_out_bits { 8662 u8 status[0x8]; 8663 u8 reserved_at_8[0x18]; 8664 8665 u8 syndrome[0x20]; 8666 8667 u8 reserved_at_40[0x8]; 8668 u8 xrc_srqn[0x18]; 8669 8670 u8 reserved_at_60[0x20]; 8671 }; 8672 8673 struct mlx5_ifc_create_xrc_srq_in_bits { 8674 u8 opcode[0x10]; 8675 u8 uid[0x10]; 8676 8677 u8 reserved_at_20[0x10]; 8678 u8 op_mod[0x10]; 8679 8680 u8 reserved_at_40[0x40]; 8681 8682 struct mlx5_ifc_xrc_srqc_bits xrc_srq_context_entry; 8683 8684 u8 reserved_at_280[0x60]; 8685 8686 u8 xrc_srq_umem_valid[0x1]; 8687 u8 reserved_at_2e1[0x1f]; 8688 8689 u8 reserved_at_300[0x580]; 8690 8691 u8 pas[][0x40]; 8692 }; 8693 8694 struct mlx5_ifc_create_tis_out_bits { 8695 u8 status[0x8]; 8696 u8 reserved_at_8[0x18]; 8697 8698 u8 syndrome[0x20]; 8699 8700 u8 reserved_at_40[0x8]; 8701 u8 tisn[0x18]; 8702 8703 u8 reserved_at_60[0x20]; 8704 }; 8705 8706 struct mlx5_ifc_create_tis_in_bits { 8707 u8 opcode[0x10]; 8708 u8 uid[0x10]; 8709 8710 u8 reserved_at_20[0x10]; 8711 u8 op_mod[0x10]; 8712 8713 u8 reserved_at_40[0xc0]; 8714 8715 struct mlx5_ifc_tisc_bits ctx; 8716 }; 8717 8718 struct mlx5_ifc_create_tir_out_bits { 8719 u8 status[0x8]; 8720 u8 icm_address_63_40[0x18]; 8721 8722 u8 syndrome[0x20]; 8723 8724 u8 icm_address_39_32[0x8]; 8725 u8 tirn[0x18]; 8726 8727 u8 icm_address_31_0[0x20]; 8728 }; 8729 8730 struct mlx5_ifc_create_tir_in_bits { 8731 u8 opcode[0x10]; 8732 u8 uid[0x10]; 8733 8734 u8 reserved_at_20[0x10]; 8735 u8 op_mod[0x10]; 8736 8737 u8 reserved_at_40[0xc0]; 8738 8739 struct mlx5_ifc_tirc_bits ctx; 8740 }; 8741 8742 struct mlx5_ifc_create_srq_out_bits { 8743 u8 status[0x8]; 8744 u8 reserved_at_8[0x18]; 8745 8746 u8 syndrome[0x20]; 8747 8748 u8 reserved_at_40[0x8]; 8749 u8 srqn[0x18]; 8750 8751 u8 reserved_at_60[0x20]; 8752 }; 8753 8754 struct mlx5_ifc_create_srq_in_bits { 8755 u8 opcode[0x10]; 8756 u8 uid[0x10]; 8757 8758 u8 reserved_at_20[0x10]; 8759 u8 op_mod[0x10]; 8760 8761 u8 reserved_at_40[0x40]; 8762 8763 struct mlx5_ifc_srqc_bits srq_context_entry; 8764 8765 u8 reserved_at_280[0x600]; 8766 8767 u8 pas[][0x40]; 8768 }; 8769 8770 struct mlx5_ifc_create_sq_out_bits { 8771 u8 status[0x8]; 8772 u8 reserved_at_8[0x18]; 8773 8774 u8 syndrome[0x20]; 8775 8776 u8 reserved_at_40[0x8]; 8777 u8 sqn[0x18]; 8778 8779 u8 reserved_at_60[0x20]; 8780 }; 8781 8782 struct mlx5_ifc_create_sq_in_bits { 8783 u8 opcode[0x10]; 8784 u8 uid[0x10]; 8785 8786 u8 reserved_at_20[0x10]; 8787 u8 op_mod[0x10]; 8788 8789 u8 reserved_at_40[0xc0]; 8790 8791 struct mlx5_ifc_sqc_bits ctx; 8792 }; 8793 8794 struct mlx5_ifc_create_scheduling_element_out_bits { 8795 u8 status[0x8]; 8796 u8 reserved_at_8[0x18]; 8797 8798 u8 syndrome[0x20]; 8799 8800 u8 reserved_at_40[0x40]; 8801 8802 u8 scheduling_element_id[0x20]; 8803 8804 u8 reserved_at_a0[0x160]; 8805 }; 8806 8807 struct mlx5_ifc_create_scheduling_element_in_bits { 8808 u8 opcode[0x10]; 8809 u8 reserved_at_10[0x10]; 8810 8811 u8 reserved_at_20[0x10]; 8812 u8 op_mod[0x10]; 8813 8814 u8 scheduling_hierarchy[0x8]; 8815 u8 reserved_at_48[0x18]; 8816 8817 u8 reserved_at_60[0xa0]; 8818 8819 struct mlx5_ifc_scheduling_context_bits scheduling_context; 8820 8821 u8 reserved_at_300[0x100]; 8822 }; 8823 8824 struct mlx5_ifc_create_rqt_out_bits { 8825 u8 status[0x8]; 8826 u8 reserved_at_8[0x18]; 8827 8828 u8 syndrome[0x20]; 8829 8830 u8 reserved_at_40[0x8]; 8831 u8 rqtn[0x18]; 8832 8833 u8 reserved_at_60[0x20]; 8834 }; 8835 8836 struct mlx5_ifc_create_rqt_in_bits { 8837 u8 opcode[0x10]; 8838 u8 uid[0x10]; 8839 8840 u8 reserved_at_20[0x10]; 8841 u8 op_mod[0x10]; 8842 8843 u8 reserved_at_40[0xc0]; 8844 8845 struct mlx5_ifc_rqtc_bits rqt_context; 8846 }; 8847 8848 struct mlx5_ifc_create_rq_out_bits { 8849 u8 status[0x8]; 8850 u8 reserved_at_8[0x18]; 8851 8852 u8 syndrome[0x20]; 8853 8854 u8 reserved_at_40[0x8]; 8855 u8 rqn[0x18]; 8856 8857 u8 reserved_at_60[0x20]; 8858 }; 8859 8860 struct mlx5_ifc_create_rq_in_bits { 8861 u8 opcode[0x10]; 8862 u8 uid[0x10]; 8863 8864 u8 reserved_at_20[0x10]; 8865 u8 op_mod[0x10]; 8866 8867 u8 reserved_at_40[0xc0]; 8868 8869 struct mlx5_ifc_rqc_bits ctx; 8870 }; 8871 8872 struct mlx5_ifc_create_rmp_out_bits { 8873 u8 status[0x8]; 8874 u8 reserved_at_8[0x18]; 8875 8876 u8 syndrome[0x20]; 8877 8878 u8 reserved_at_40[0x8]; 8879 u8 rmpn[0x18]; 8880 8881 u8 reserved_at_60[0x20]; 8882 }; 8883 8884 struct mlx5_ifc_create_rmp_in_bits { 8885 u8 opcode[0x10]; 8886 u8 uid[0x10]; 8887 8888 u8 reserved_at_20[0x10]; 8889 u8 op_mod[0x10]; 8890 8891 u8 reserved_at_40[0xc0]; 8892 8893 struct mlx5_ifc_rmpc_bits ctx; 8894 }; 8895 8896 struct mlx5_ifc_create_qp_out_bits { 8897 u8 status[0x8]; 8898 u8 reserved_at_8[0x18]; 8899 8900 u8 syndrome[0x20]; 8901 8902 u8 reserved_at_40[0x8]; 8903 u8 qpn[0x18]; 8904 8905 u8 ece[0x20]; 8906 }; 8907 8908 struct mlx5_ifc_create_qp_in_bits { 8909 u8 opcode[0x10]; 8910 u8 uid[0x10]; 8911 8912 u8 reserved_at_20[0x10]; 8913 u8 op_mod[0x10]; 8914 8915 u8 qpc_ext[0x1]; 8916 u8 reserved_at_41[0x7]; 8917 u8 input_qpn[0x18]; 8918 8919 u8 reserved_at_60[0x20]; 8920 u8 opt_param_mask[0x20]; 8921 8922 u8 ece[0x20]; 8923 8924 struct mlx5_ifc_qpc_bits qpc; 8925 8926 u8 reserved_at_800[0x60]; 8927 8928 u8 wq_umem_valid[0x1]; 8929 u8 reserved_at_861[0x1f]; 8930 8931 u8 pas[][0x40]; 8932 }; 8933 8934 struct mlx5_ifc_create_psv_out_bits { 8935 u8 status[0x8]; 8936 u8 reserved_at_8[0x18]; 8937 8938 u8 syndrome[0x20]; 8939 8940 u8 reserved_at_40[0x40]; 8941 8942 u8 reserved_at_80[0x8]; 8943 u8 psv0_index[0x18]; 8944 8945 u8 reserved_at_a0[0x8]; 8946 u8 psv1_index[0x18]; 8947 8948 u8 reserved_at_c0[0x8]; 8949 u8 psv2_index[0x18]; 8950 8951 u8 reserved_at_e0[0x8]; 8952 u8 psv3_index[0x18]; 8953 }; 8954 8955 struct mlx5_ifc_create_psv_in_bits { 8956 u8 opcode[0x10]; 8957 u8 reserved_at_10[0x10]; 8958 8959 u8 reserved_at_20[0x10]; 8960 u8 op_mod[0x10]; 8961 8962 u8 num_psv[0x4]; 8963 u8 reserved_at_44[0x4]; 8964 u8 pd[0x18]; 8965 8966 u8 reserved_at_60[0x20]; 8967 }; 8968 8969 struct mlx5_ifc_create_mkey_out_bits { 8970 u8 status[0x8]; 8971 u8 reserved_at_8[0x18]; 8972 8973 u8 syndrome[0x20]; 8974 8975 u8 reserved_at_40[0x8]; 8976 u8 mkey_index[0x18]; 8977 8978 u8 reserved_at_60[0x20]; 8979 }; 8980 8981 struct mlx5_ifc_create_mkey_in_bits { 8982 u8 opcode[0x10]; 8983 u8 uid[0x10]; 8984 8985 u8 reserved_at_20[0x10]; 8986 u8 op_mod[0x10]; 8987 8988 u8 reserved_at_40[0x20]; 8989 8990 u8 pg_access[0x1]; 8991 u8 mkey_umem_valid[0x1]; 8992 u8 reserved_at_62[0x1e]; 8993 8994 struct mlx5_ifc_mkc_bits memory_key_mkey_entry; 8995 8996 u8 reserved_at_280[0x80]; 8997 8998 u8 translations_octword_actual_size[0x20]; 8999 9000 u8 reserved_at_320[0x560]; 9001 9002 u8 klm_pas_mtt[][0x20]; 9003 }; 9004 9005 enum { 9006 MLX5_FLOW_TABLE_TYPE_NIC_RX = 0x0, 9007 MLX5_FLOW_TABLE_TYPE_NIC_TX = 0x1, 9008 MLX5_FLOW_TABLE_TYPE_ESW_EGRESS_ACL = 0x2, 9009 MLX5_FLOW_TABLE_TYPE_ESW_INGRESS_ACL = 0x3, 9010 MLX5_FLOW_TABLE_TYPE_FDB = 0X4, 9011 MLX5_FLOW_TABLE_TYPE_SNIFFER_RX = 0X5, 9012 MLX5_FLOW_TABLE_TYPE_SNIFFER_TX = 0X6, 9013 }; 9014 9015 struct mlx5_ifc_create_flow_table_out_bits { 9016 u8 status[0x8]; 9017 u8 icm_address_63_40[0x18]; 9018 9019 u8 syndrome[0x20]; 9020 9021 u8 icm_address_39_32[0x8]; 9022 u8 table_id[0x18]; 9023 9024 u8 icm_address_31_0[0x20]; 9025 }; 9026 9027 struct mlx5_ifc_create_flow_table_in_bits { 9028 u8 opcode[0x10]; 9029 u8 uid[0x10]; 9030 9031 u8 reserved_at_20[0x10]; 9032 u8 op_mod[0x10]; 9033 9034 u8 other_vport[0x1]; 9035 u8 reserved_at_41[0xf]; 9036 u8 vport_number[0x10]; 9037 9038 u8 reserved_at_60[0x20]; 9039 9040 u8 table_type[0x8]; 9041 u8 reserved_at_88[0x18]; 9042 9043 u8 reserved_at_a0[0x20]; 9044 9045 struct mlx5_ifc_flow_table_context_bits flow_table_context; 9046 }; 9047 9048 struct mlx5_ifc_create_flow_group_out_bits { 9049 u8 status[0x8]; 9050 u8 reserved_at_8[0x18]; 9051 9052 u8 syndrome[0x20]; 9053 9054 u8 reserved_at_40[0x8]; 9055 u8 group_id[0x18]; 9056 9057 u8 reserved_at_60[0x20]; 9058 }; 9059 9060 enum { 9061 MLX5_CREATE_FLOW_GROUP_IN_GROUP_TYPE_TCAM_SUBTABLE = 0x0, 9062 MLX5_CREATE_FLOW_GROUP_IN_GROUP_TYPE_HASH_SPLIT = 0x1, 9063 }; 9064 9065 enum { 9066 MLX5_CREATE_FLOW_GROUP_IN_MATCH_CRITERIA_ENABLE_OUTER_HEADERS = 0x0, 9067 MLX5_CREATE_FLOW_GROUP_IN_MATCH_CRITERIA_ENABLE_MISC_PARAMETERS = 0x1, 9068 MLX5_CREATE_FLOW_GROUP_IN_MATCH_CRITERIA_ENABLE_INNER_HEADERS = 0x2, 9069 MLX5_CREATE_FLOW_GROUP_IN_MATCH_CRITERIA_ENABLE_MISC_PARAMETERS_2 = 0x3, 9070 }; 9071 9072 struct mlx5_ifc_create_flow_group_in_bits { 9073 u8 opcode[0x10]; 9074 u8 reserved_at_10[0x10]; 9075 9076 u8 reserved_at_20[0x10]; 9077 u8 op_mod[0x10]; 9078 9079 u8 other_vport[0x1]; 9080 u8 reserved_at_41[0xf]; 9081 u8 vport_number[0x10]; 9082 9083 u8 reserved_at_60[0x20]; 9084 9085 u8 table_type[0x8]; 9086 u8 reserved_at_88[0x4]; 9087 u8 group_type[0x4]; 9088 u8 reserved_at_90[0x10]; 9089 9090 u8 reserved_at_a0[0x8]; 9091 u8 table_id[0x18]; 9092 9093 u8 source_eswitch_owner_vhca_id_valid[0x1]; 9094 9095 u8 reserved_at_c1[0x1f]; 9096 9097 u8 start_flow_index[0x20]; 9098 9099 u8 reserved_at_100[0x20]; 9100 9101 u8 end_flow_index[0x20]; 9102 9103 u8 reserved_at_140[0x10]; 9104 u8 match_definer_id[0x10]; 9105 9106 u8 reserved_at_160[0x80]; 9107 9108 u8 reserved_at_1e0[0x18]; 9109 u8 match_criteria_enable[0x8]; 9110 9111 struct mlx5_ifc_fte_match_param_bits match_criteria; 9112 9113 u8 reserved_at_1200[0xe00]; 9114 }; 9115 9116 struct mlx5_ifc_create_eq_out_bits { 9117 u8 status[0x8]; 9118 u8 reserved_at_8[0x18]; 9119 9120 u8 syndrome[0x20]; 9121 9122 u8 reserved_at_40[0x18]; 9123 u8 eq_number[0x8]; 9124 9125 u8 reserved_at_60[0x20]; 9126 }; 9127 9128 struct mlx5_ifc_create_eq_in_bits { 9129 u8 opcode[0x10]; 9130 u8 uid[0x10]; 9131 9132 u8 reserved_at_20[0x10]; 9133 u8 op_mod[0x10]; 9134 9135 u8 reserved_at_40[0x40]; 9136 9137 struct mlx5_ifc_eqc_bits eq_context_entry; 9138 9139 u8 reserved_at_280[0x40]; 9140 9141 u8 event_bitmask[4][0x40]; 9142 9143 u8 reserved_at_3c0[0x4c0]; 9144 9145 u8 pas[][0x40]; 9146 }; 9147 9148 struct mlx5_ifc_create_dct_out_bits { 9149 u8 status[0x8]; 9150 u8 reserved_at_8[0x18]; 9151 9152 u8 syndrome[0x20]; 9153 9154 u8 reserved_at_40[0x8]; 9155 u8 dctn[0x18]; 9156 9157 u8 ece[0x20]; 9158 }; 9159 9160 struct mlx5_ifc_create_dct_in_bits { 9161 u8 opcode[0x10]; 9162 u8 uid[0x10]; 9163 9164 u8 reserved_at_20[0x10]; 9165 u8 op_mod[0x10]; 9166 9167 u8 reserved_at_40[0x40]; 9168 9169 struct mlx5_ifc_dctc_bits dct_context_entry; 9170 9171 u8 reserved_at_280[0x180]; 9172 }; 9173 9174 struct mlx5_ifc_create_cq_out_bits { 9175 u8 status[0x8]; 9176 u8 reserved_at_8[0x18]; 9177 9178 u8 syndrome[0x20]; 9179 9180 u8 reserved_at_40[0x8]; 9181 u8 cqn[0x18]; 9182 9183 u8 reserved_at_60[0x20]; 9184 }; 9185 9186 struct mlx5_ifc_create_cq_in_bits { 9187 u8 opcode[0x10]; 9188 u8 uid[0x10]; 9189 9190 u8 reserved_at_20[0x10]; 9191 u8 op_mod[0x10]; 9192 9193 u8 reserved_at_40[0x40]; 9194 9195 struct mlx5_ifc_cqc_bits cq_context; 9196 9197 u8 reserved_at_280[0x60]; 9198 9199 u8 cq_umem_valid[0x1]; 9200 u8 reserved_at_2e1[0x59f]; 9201 9202 u8 pas[][0x40]; 9203 }; 9204 9205 struct mlx5_ifc_config_int_moderation_out_bits { 9206 u8 status[0x8]; 9207 u8 reserved_at_8[0x18]; 9208 9209 u8 syndrome[0x20]; 9210 9211 u8 reserved_at_40[0x4]; 9212 u8 min_delay[0xc]; 9213 u8 int_vector[0x10]; 9214 9215 u8 reserved_at_60[0x20]; 9216 }; 9217 9218 enum { 9219 MLX5_CONFIG_INT_MODERATION_IN_OP_MOD_WRITE = 0x0, 9220 MLX5_CONFIG_INT_MODERATION_IN_OP_MOD_READ = 0x1, 9221 }; 9222 9223 struct mlx5_ifc_config_int_moderation_in_bits { 9224 u8 opcode[0x10]; 9225 u8 reserved_at_10[0x10]; 9226 9227 u8 reserved_at_20[0x10]; 9228 u8 op_mod[0x10]; 9229 9230 u8 reserved_at_40[0x4]; 9231 u8 min_delay[0xc]; 9232 u8 int_vector[0x10]; 9233 9234 u8 reserved_at_60[0x20]; 9235 }; 9236 9237 struct mlx5_ifc_attach_to_mcg_out_bits { 9238 u8 status[0x8]; 9239 u8 reserved_at_8[0x18]; 9240 9241 u8 syndrome[0x20]; 9242 9243 u8 reserved_at_40[0x40]; 9244 }; 9245 9246 struct mlx5_ifc_attach_to_mcg_in_bits { 9247 u8 opcode[0x10]; 9248 u8 uid[0x10]; 9249 9250 u8 reserved_at_20[0x10]; 9251 u8 op_mod[0x10]; 9252 9253 u8 reserved_at_40[0x8]; 9254 u8 qpn[0x18]; 9255 9256 u8 reserved_at_60[0x20]; 9257 9258 u8 multicast_gid[16][0x8]; 9259 }; 9260 9261 struct mlx5_ifc_arm_xrq_out_bits { 9262 u8 status[0x8]; 9263 u8 reserved_at_8[0x18]; 9264 9265 u8 syndrome[0x20]; 9266 9267 u8 reserved_at_40[0x40]; 9268 }; 9269 9270 struct mlx5_ifc_arm_xrq_in_bits { 9271 u8 opcode[0x10]; 9272 u8 reserved_at_10[0x10]; 9273 9274 u8 reserved_at_20[0x10]; 9275 u8 op_mod[0x10]; 9276 9277 u8 reserved_at_40[0x8]; 9278 u8 xrqn[0x18]; 9279 9280 u8 reserved_at_60[0x10]; 9281 u8 lwm[0x10]; 9282 }; 9283 9284 struct mlx5_ifc_arm_xrc_srq_out_bits { 9285 u8 status[0x8]; 9286 u8 reserved_at_8[0x18]; 9287 9288 u8 syndrome[0x20]; 9289 9290 u8 reserved_at_40[0x40]; 9291 }; 9292 9293 enum { 9294 MLX5_ARM_XRC_SRQ_IN_OP_MOD_XRC_SRQ = 0x1, 9295 }; 9296 9297 struct mlx5_ifc_arm_xrc_srq_in_bits { 9298 u8 opcode[0x10]; 9299 u8 uid[0x10]; 9300 9301 u8 reserved_at_20[0x10]; 9302 u8 op_mod[0x10]; 9303 9304 u8 reserved_at_40[0x8]; 9305 u8 xrc_srqn[0x18]; 9306 9307 u8 reserved_at_60[0x10]; 9308 u8 lwm[0x10]; 9309 }; 9310 9311 struct mlx5_ifc_arm_rq_out_bits { 9312 u8 status[0x8]; 9313 u8 reserved_at_8[0x18]; 9314 9315 u8 syndrome[0x20]; 9316 9317 u8 reserved_at_40[0x40]; 9318 }; 9319 9320 enum { 9321 MLX5_ARM_RQ_IN_OP_MOD_SRQ = 0x1, 9322 MLX5_ARM_RQ_IN_OP_MOD_XRQ = 0x2, 9323 }; 9324 9325 struct mlx5_ifc_arm_rq_in_bits { 9326 u8 opcode[0x10]; 9327 u8 uid[0x10]; 9328 9329 u8 reserved_at_20[0x10]; 9330 u8 op_mod[0x10]; 9331 9332 u8 reserved_at_40[0x8]; 9333 u8 srq_number[0x18]; 9334 9335 u8 reserved_at_60[0x10]; 9336 u8 lwm[0x10]; 9337 }; 9338 9339 struct mlx5_ifc_arm_dct_out_bits { 9340 u8 status[0x8]; 9341 u8 reserved_at_8[0x18]; 9342 9343 u8 syndrome[0x20]; 9344 9345 u8 reserved_at_40[0x40]; 9346 }; 9347 9348 struct mlx5_ifc_arm_dct_in_bits { 9349 u8 opcode[0x10]; 9350 u8 reserved_at_10[0x10]; 9351 9352 u8 reserved_at_20[0x10]; 9353 u8 op_mod[0x10]; 9354 9355 u8 reserved_at_40[0x8]; 9356 u8 dct_number[0x18]; 9357 9358 u8 reserved_at_60[0x20]; 9359 }; 9360 9361 struct mlx5_ifc_alloc_xrcd_out_bits { 9362 u8 status[0x8]; 9363 u8 reserved_at_8[0x18]; 9364 9365 u8 syndrome[0x20]; 9366 9367 u8 reserved_at_40[0x8]; 9368 u8 xrcd[0x18]; 9369 9370 u8 reserved_at_60[0x20]; 9371 }; 9372 9373 struct mlx5_ifc_alloc_xrcd_in_bits { 9374 u8 opcode[0x10]; 9375 u8 uid[0x10]; 9376 9377 u8 reserved_at_20[0x10]; 9378 u8 op_mod[0x10]; 9379 9380 u8 reserved_at_40[0x40]; 9381 }; 9382 9383 struct mlx5_ifc_alloc_uar_out_bits { 9384 u8 status[0x8]; 9385 u8 reserved_at_8[0x18]; 9386 9387 u8 syndrome[0x20]; 9388 9389 u8 reserved_at_40[0x8]; 9390 u8 uar[0x18]; 9391 9392 u8 reserved_at_60[0x20]; 9393 }; 9394 9395 struct mlx5_ifc_alloc_uar_in_bits { 9396 u8 opcode[0x10]; 9397 u8 uid[0x10]; 9398 9399 u8 reserved_at_20[0x10]; 9400 u8 op_mod[0x10]; 9401 9402 u8 reserved_at_40[0x40]; 9403 }; 9404 9405 struct mlx5_ifc_alloc_transport_domain_out_bits { 9406 u8 status[0x8]; 9407 u8 reserved_at_8[0x18]; 9408 9409 u8 syndrome[0x20]; 9410 9411 u8 reserved_at_40[0x8]; 9412 u8 transport_domain[0x18]; 9413 9414 u8 reserved_at_60[0x20]; 9415 }; 9416 9417 struct mlx5_ifc_alloc_transport_domain_in_bits { 9418 u8 opcode[0x10]; 9419 u8 uid[0x10]; 9420 9421 u8 reserved_at_20[0x10]; 9422 u8 op_mod[0x10]; 9423 9424 u8 reserved_at_40[0x40]; 9425 }; 9426 9427 struct mlx5_ifc_alloc_q_counter_out_bits { 9428 u8 status[0x8]; 9429 u8 reserved_at_8[0x18]; 9430 9431 u8 syndrome[0x20]; 9432 9433 u8 reserved_at_40[0x18]; 9434 u8 counter_set_id[0x8]; 9435 9436 u8 reserved_at_60[0x20]; 9437 }; 9438 9439 struct mlx5_ifc_alloc_q_counter_in_bits { 9440 u8 opcode[0x10]; 9441 u8 uid[0x10]; 9442 9443 u8 reserved_at_20[0x10]; 9444 u8 op_mod[0x10]; 9445 9446 u8 reserved_at_40[0x40]; 9447 }; 9448 9449 struct mlx5_ifc_alloc_pd_out_bits { 9450 u8 status[0x8]; 9451 u8 reserved_at_8[0x18]; 9452 9453 u8 syndrome[0x20]; 9454 9455 u8 reserved_at_40[0x8]; 9456 u8 pd[0x18]; 9457 9458 u8 reserved_at_60[0x20]; 9459 }; 9460 9461 struct mlx5_ifc_alloc_pd_in_bits { 9462 u8 opcode[0x10]; 9463 u8 uid[0x10]; 9464 9465 u8 reserved_at_20[0x10]; 9466 u8 op_mod[0x10]; 9467 9468 u8 reserved_at_40[0x40]; 9469 }; 9470 9471 struct mlx5_ifc_alloc_flow_counter_out_bits { 9472 u8 status[0x8]; 9473 u8 reserved_at_8[0x18]; 9474 9475 u8 syndrome[0x20]; 9476 9477 u8 flow_counter_id[0x20]; 9478 9479 u8 reserved_at_60[0x20]; 9480 }; 9481 9482 struct mlx5_ifc_alloc_flow_counter_in_bits { 9483 u8 opcode[0x10]; 9484 u8 reserved_at_10[0x10]; 9485 9486 u8 reserved_at_20[0x10]; 9487 u8 op_mod[0x10]; 9488 9489 u8 reserved_at_40[0x33]; 9490 u8 flow_counter_bulk_log_size[0x5]; 9491 u8 flow_counter_bulk[0x8]; 9492 }; 9493 9494 struct mlx5_ifc_add_vxlan_udp_dport_out_bits { 9495 u8 status[0x8]; 9496 u8 reserved_at_8[0x18]; 9497 9498 u8 syndrome[0x20]; 9499 9500 u8 reserved_at_40[0x40]; 9501 }; 9502 9503 struct mlx5_ifc_add_vxlan_udp_dport_in_bits { 9504 u8 opcode[0x10]; 9505 u8 reserved_at_10[0x10]; 9506 9507 u8 reserved_at_20[0x10]; 9508 u8 op_mod[0x10]; 9509 9510 u8 reserved_at_40[0x20]; 9511 9512 u8 reserved_at_60[0x10]; 9513 u8 vxlan_udp_port[0x10]; 9514 }; 9515 9516 struct mlx5_ifc_set_pp_rate_limit_out_bits { 9517 u8 status[0x8]; 9518 u8 reserved_at_8[0x18]; 9519 9520 u8 syndrome[0x20]; 9521 9522 u8 reserved_at_40[0x40]; 9523 }; 9524 9525 struct mlx5_ifc_set_pp_rate_limit_context_bits { 9526 u8 rate_limit[0x20]; 9527 9528 u8 burst_upper_bound[0x20]; 9529 9530 u8 reserved_at_40[0x10]; 9531 u8 typical_packet_size[0x10]; 9532 9533 u8 reserved_at_60[0x120]; 9534 }; 9535 9536 struct mlx5_ifc_set_pp_rate_limit_in_bits { 9537 u8 opcode[0x10]; 9538 u8 uid[0x10]; 9539 9540 u8 reserved_at_20[0x10]; 9541 u8 op_mod[0x10]; 9542 9543 u8 reserved_at_40[0x10]; 9544 u8 rate_limit_index[0x10]; 9545 9546 u8 reserved_at_60[0x20]; 9547 9548 struct mlx5_ifc_set_pp_rate_limit_context_bits ctx; 9549 }; 9550 9551 struct mlx5_ifc_access_register_out_bits { 9552 u8 status[0x8]; 9553 u8 reserved_at_8[0x18]; 9554 9555 u8 syndrome[0x20]; 9556 9557 u8 reserved_at_40[0x40]; 9558 9559 u8 register_data[][0x20]; 9560 }; 9561 9562 enum { 9563 MLX5_ACCESS_REGISTER_IN_OP_MOD_WRITE = 0x0, 9564 MLX5_ACCESS_REGISTER_IN_OP_MOD_READ = 0x1, 9565 }; 9566 9567 struct mlx5_ifc_access_register_in_bits { 9568 u8 opcode[0x10]; 9569 u8 reserved_at_10[0x10]; 9570 9571 u8 reserved_at_20[0x10]; 9572 u8 op_mod[0x10]; 9573 9574 u8 reserved_at_40[0x10]; 9575 u8 register_id[0x10]; 9576 9577 u8 argument[0x20]; 9578 9579 u8 register_data[][0x20]; 9580 }; 9581 9582 struct mlx5_ifc_sltp_reg_bits { 9583 u8 status[0x4]; 9584 u8 version[0x4]; 9585 u8 local_port[0x8]; 9586 u8 pnat[0x2]; 9587 u8 reserved_at_12[0x2]; 9588 u8 lane[0x4]; 9589 u8 reserved_at_18[0x8]; 9590 9591 u8 reserved_at_20[0x20]; 9592 9593 u8 reserved_at_40[0x7]; 9594 u8 polarity[0x1]; 9595 u8 ob_tap0[0x8]; 9596 u8 ob_tap1[0x8]; 9597 u8 ob_tap2[0x8]; 9598 9599 u8 reserved_at_60[0xc]; 9600 u8 ob_preemp_mode[0x4]; 9601 u8 ob_reg[0x8]; 9602 u8 ob_bias[0x8]; 9603 9604 u8 reserved_at_80[0x20]; 9605 }; 9606 9607 struct mlx5_ifc_slrg_reg_bits { 9608 u8 status[0x4]; 9609 u8 version[0x4]; 9610 u8 local_port[0x8]; 9611 u8 pnat[0x2]; 9612 u8 reserved_at_12[0x2]; 9613 u8 lane[0x4]; 9614 u8 reserved_at_18[0x8]; 9615 9616 u8 time_to_link_up[0x10]; 9617 u8 reserved_at_30[0xc]; 9618 u8 grade_lane_speed[0x4]; 9619 9620 u8 grade_version[0x8]; 9621 u8 grade[0x18]; 9622 9623 u8 reserved_at_60[0x4]; 9624 u8 height_grade_type[0x4]; 9625 u8 height_grade[0x18]; 9626 9627 u8 height_dz[0x10]; 9628 u8 height_dv[0x10]; 9629 9630 u8 reserved_at_a0[0x10]; 9631 u8 height_sigma[0x10]; 9632 9633 u8 reserved_at_c0[0x20]; 9634 9635 u8 reserved_at_e0[0x4]; 9636 u8 phase_grade_type[0x4]; 9637 u8 phase_grade[0x18]; 9638 9639 u8 reserved_at_100[0x8]; 9640 u8 phase_eo_pos[0x8]; 9641 u8 reserved_at_110[0x8]; 9642 u8 phase_eo_neg[0x8]; 9643 9644 u8 ffe_set_tested[0x10]; 9645 u8 test_errors_per_lane[0x10]; 9646 }; 9647 9648 struct mlx5_ifc_pvlc_reg_bits { 9649 u8 reserved_at_0[0x8]; 9650 u8 local_port[0x8]; 9651 u8 reserved_at_10[0x10]; 9652 9653 u8 reserved_at_20[0x1c]; 9654 u8 vl_hw_cap[0x4]; 9655 9656 u8 reserved_at_40[0x1c]; 9657 u8 vl_admin[0x4]; 9658 9659 u8 reserved_at_60[0x1c]; 9660 u8 vl_operational[0x4]; 9661 }; 9662 9663 struct mlx5_ifc_pude_reg_bits { 9664 u8 swid[0x8]; 9665 u8 local_port[0x8]; 9666 u8 reserved_at_10[0x4]; 9667 u8 admin_status[0x4]; 9668 u8 reserved_at_18[0x4]; 9669 u8 oper_status[0x4]; 9670 9671 u8 reserved_at_20[0x60]; 9672 }; 9673 9674 struct mlx5_ifc_ptys_reg_bits { 9675 u8 reserved_at_0[0x1]; 9676 u8 an_disable_admin[0x1]; 9677 u8 an_disable_cap[0x1]; 9678 u8 reserved_at_3[0x5]; 9679 u8 local_port[0x8]; 9680 u8 reserved_at_10[0x8]; 9681 u8 plane_ind[0x4]; 9682 u8 reserved_at_1c[0x1]; 9683 u8 proto_mask[0x3]; 9684 9685 u8 an_status[0x4]; 9686 u8 reserved_at_24[0xc]; 9687 u8 data_rate_oper[0x10]; 9688 9689 u8 ext_eth_proto_capability[0x20]; 9690 9691 u8 eth_proto_capability[0x20]; 9692 9693 u8 ib_link_width_capability[0x10]; 9694 u8 ib_proto_capability[0x10]; 9695 9696 u8 ext_eth_proto_admin[0x20]; 9697 9698 u8 eth_proto_admin[0x20]; 9699 9700 u8 ib_link_width_admin[0x10]; 9701 u8 ib_proto_admin[0x10]; 9702 9703 u8 ext_eth_proto_oper[0x20]; 9704 9705 u8 eth_proto_oper[0x20]; 9706 9707 u8 ib_link_width_oper[0x10]; 9708 u8 ib_proto_oper[0x10]; 9709 9710 u8 reserved_at_160[0x1c]; 9711 u8 connector_type[0x4]; 9712 9713 u8 eth_proto_lp_advertise[0x20]; 9714 9715 u8 reserved_at_1a0[0x60]; 9716 }; 9717 9718 struct mlx5_ifc_mlcr_reg_bits { 9719 u8 reserved_at_0[0x8]; 9720 u8 local_port[0x8]; 9721 u8 reserved_at_10[0x20]; 9722 9723 u8 beacon_duration[0x10]; 9724 u8 reserved_at_40[0x10]; 9725 9726 u8 beacon_remain[0x10]; 9727 }; 9728 9729 struct mlx5_ifc_ptas_reg_bits { 9730 u8 reserved_at_0[0x20]; 9731 9732 u8 algorithm_options[0x10]; 9733 u8 reserved_at_30[0x4]; 9734 u8 repetitions_mode[0x4]; 9735 u8 num_of_repetitions[0x8]; 9736 9737 u8 grade_version[0x8]; 9738 u8 height_grade_type[0x4]; 9739 u8 phase_grade_type[0x4]; 9740 u8 height_grade_weight[0x8]; 9741 u8 phase_grade_weight[0x8]; 9742 9743 u8 gisim_measure_bits[0x10]; 9744 u8 adaptive_tap_measure_bits[0x10]; 9745 9746 u8 ber_bath_high_error_threshold[0x10]; 9747 u8 ber_bath_mid_error_threshold[0x10]; 9748 9749 u8 ber_bath_low_error_threshold[0x10]; 9750 u8 one_ratio_high_threshold[0x10]; 9751 9752 u8 one_ratio_high_mid_threshold[0x10]; 9753 u8 one_ratio_low_mid_threshold[0x10]; 9754 9755 u8 one_ratio_low_threshold[0x10]; 9756 u8 ndeo_error_threshold[0x10]; 9757 9758 u8 mixer_offset_step_size[0x10]; 9759 u8 reserved_at_110[0x8]; 9760 u8 mix90_phase_for_voltage_bath[0x8]; 9761 9762 u8 mixer_offset_start[0x10]; 9763 u8 mixer_offset_end[0x10]; 9764 9765 u8 reserved_at_140[0x15]; 9766 u8 ber_test_time[0xb]; 9767 }; 9768 9769 struct mlx5_ifc_pspa_reg_bits { 9770 u8 swid[0x8]; 9771 u8 local_port[0x8]; 9772 u8 sub_port[0x8]; 9773 u8 reserved_at_18[0x8]; 9774 9775 u8 reserved_at_20[0x20]; 9776 }; 9777 9778 struct mlx5_ifc_pqdr_reg_bits { 9779 u8 reserved_at_0[0x8]; 9780 u8 local_port[0x8]; 9781 u8 reserved_at_10[0x5]; 9782 u8 prio[0x3]; 9783 u8 reserved_at_18[0x6]; 9784 u8 mode[0x2]; 9785 9786 u8 reserved_at_20[0x20]; 9787 9788 u8 reserved_at_40[0x10]; 9789 u8 min_threshold[0x10]; 9790 9791 u8 reserved_at_60[0x10]; 9792 u8 max_threshold[0x10]; 9793 9794 u8 reserved_at_80[0x10]; 9795 u8 mark_probability_denominator[0x10]; 9796 9797 u8 reserved_at_a0[0x60]; 9798 }; 9799 9800 struct mlx5_ifc_ppsc_reg_bits { 9801 u8 reserved_at_0[0x8]; 9802 u8 local_port[0x8]; 9803 u8 reserved_at_10[0x10]; 9804 9805 u8 reserved_at_20[0x60]; 9806 9807 u8 reserved_at_80[0x1c]; 9808 u8 wrps_admin[0x4]; 9809 9810 u8 reserved_at_a0[0x1c]; 9811 u8 wrps_status[0x4]; 9812 9813 u8 reserved_at_c0[0x8]; 9814 u8 up_threshold[0x8]; 9815 u8 reserved_at_d0[0x8]; 9816 u8 down_threshold[0x8]; 9817 9818 u8 reserved_at_e0[0x20]; 9819 9820 u8 reserved_at_100[0x1c]; 9821 u8 srps_admin[0x4]; 9822 9823 u8 reserved_at_120[0x1c]; 9824 u8 srps_status[0x4]; 9825 9826 u8 reserved_at_140[0x40]; 9827 }; 9828 9829 struct mlx5_ifc_pplr_reg_bits { 9830 u8 reserved_at_0[0x8]; 9831 u8 local_port[0x8]; 9832 u8 reserved_at_10[0x10]; 9833 9834 u8 reserved_at_20[0x8]; 9835 u8 lb_cap[0x8]; 9836 u8 reserved_at_30[0x8]; 9837 u8 lb_en[0x8]; 9838 }; 9839 9840 struct mlx5_ifc_pplm_reg_bits { 9841 u8 reserved_at_0[0x8]; 9842 u8 local_port[0x8]; 9843 u8 reserved_at_10[0x10]; 9844 9845 u8 reserved_at_20[0x20]; 9846 9847 u8 port_profile_mode[0x8]; 9848 u8 static_port_profile[0x8]; 9849 u8 active_port_profile[0x8]; 9850 u8 reserved_at_58[0x8]; 9851 9852 u8 retransmission_active[0x8]; 9853 u8 fec_mode_active[0x18]; 9854 9855 u8 rs_fec_correction_bypass_cap[0x4]; 9856 u8 reserved_at_84[0x8]; 9857 u8 fec_override_cap_56g[0x4]; 9858 u8 fec_override_cap_100g[0x4]; 9859 u8 fec_override_cap_50g[0x4]; 9860 u8 fec_override_cap_25g[0x4]; 9861 u8 fec_override_cap_10g_40g[0x4]; 9862 9863 u8 rs_fec_correction_bypass_admin[0x4]; 9864 u8 reserved_at_a4[0x8]; 9865 u8 fec_override_admin_56g[0x4]; 9866 u8 fec_override_admin_100g[0x4]; 9867 u8 fec_override_admin_50g[0x4]; 9868 u8 fec_override_admin_25g[0x4]; 9869 u8 fec_override_admin_10g_40g[0x4]; 9870 9871 u8 fec_override_cap_400g_8x[0x10]; 9872 u8 fec_override_cap_200g_4x[0x10]; 9873 9874 u8 fec_override_cap_100g_2x[0x10]; 9875 u8 fec_override_cap_50g_1x[0x10]; 9876 9877 u8 fec_override_admin_400g_8x[0x10]; 9878 u8 fec_override_admin_200g_4x[0x10]; 9879 9880 u8 fec_override_admin_100g_2x[0x10]; 9881 u8 fec_override_admin_50g_1x[0x10]; 9882 9883 u8 fec_override_cap_800g_8x[0x10]; 9884 u8 fec_override_cap_400g_4x[0x10]; 9885 9886 u8 fec_override_cap_200g_2x[0x10]; 9887 u8 fec_override_cap_100g_1x[0x10]; 9888 9889 u8 reserved_at_180[0xa0]; 9890 9891 u8 fec_override_admin_800g_8x[0x10]; 9892 u8 fec_override_admin_400g_4x[0x10]; 9893 9894 u8 fec_override_admin_200g_2x[0x10]; 9895 u8 fec_override_admin_100g_1x[0x10]; 9896 9897 u8 reserved_at_260[0x20]; 9898 }; 9899 9900 struct mlx5_ifc_ppcnt_reg_bits { 9901 u8 swid[0x8]; 9902 u8 local_port[0x8]; 9903 u8 pnat[0x2]; 9904 u8 reserved_at_12[0x8]; 9905 u8 grp[0x6]; 9906 9907 u8 clr[0x1]; 9908 u8 reserved_at_21[0x13]; 9909 u8 plane_ind[0x4]; 9910 u8 reserved_at_38[0x3]; 9911 u8 prio_tc[0x5]; 9912 9913 union mlx5_ifc_eth_cntrs_grp_data_layout_auto_bits counter_set; 9914 }; 9915 9916 struct mlx5_ifc_mpein_reg_bits { 9917 u8 reserved_at_0[0x2]; 9918 u8 depth[0x6]; 9919 u8 pcie_index[0x8]; 9920 u8 node[0x8]; 9921 u8 reserved_at_18[0x8]; 9922 9923 u8 capability_mask[0x20]; 9924 9925 u8 reserved_at_40[0x8]; 9926 u8 link_width_enabled[0x8]; 9927 u8 link_speed_enabled[0x10]; 9928 9929 u8 lane0_physical_position[0x8]; 9930 u8 link_width_active[0x8]; 9931 u8 link_speed_active[0x10]; 9932 9933 u8 num_of_pfs[0x10]; 9934 u8 num_of_vfs[0x10]; 9935 9936 u8 bdf0[0x10]; 9937 u8 reserved_at_b0[0x10]; 9938 9939 u8 max_read_request_size[0x4]; 9940 u8 max_payload_size[0x4]; 9941 u8 reserved_at_c8[0x5]; 9942 u8 pwr_status[0x3]; 9943 u8 port_type[0x4]; 9944 u8 reserved_at_d4[0xb]; 9945 u8 lane_reversal[0x1]; 9946 9947 u8 reserved_at_e0[0x14]; 9948 u8 pci_power[0xc]; 9949 9950 u8 reserved_at_100[0x20]; 9951 9952 u8 device_status[0x10]; 9953 u8 port_state[0x8]; 9954 u8 reserved_at_138[0x8]; 9955 9956 u8 reserved_at_140[0x10]; 9957 u8 receiver_detect_result[0x10]; 9958 9959 u8 reserved_at_160[0x20]; 9960 }; 9961 9962 struct mlx5_ifc_mpcnt_reg_bits { 9963 u8 reserved_at_0[0x8]; 9964 u8 pcie_index[0x8]; 9965 u8 reserved_at_10[0xa]; 9966 u8 grp[0x6]; 9967 9968 u8 clr[0x1]; 9969 u8 reserved_at_21[0x1f]; 9970 9971 union mlx5_ifc_pcie_cntrs_grp_data_layout_auto_bits counter_set; 9972 }; 9973 9974 struct mlx5_ifc_ppad_reg_bits { 9975 u8 reserved_at_0[0x3]; 9976 u8 single_mac[0x1]; 9977 u8 reserved_at_4[0x4]; 9978 u8 local_port[0x8]; 9979 u8 mac_47_32[0x10]; 9980 9981 u8 mac_31_0[0x20]; 9982 9983 u8 reserved_at_40[0x40]; 9984 }; 9985 9986 struct mlx5_ifc_pmtu_reg_bits { 9987 u8 reserved_at_0[0x8]; 9988 u8 local_port[0x8]; 9989 u8 reserved_at_10[0x10]; 9990 9991 u8 max_mtu[0x10]; 9992 u8 reserved_at_30[0x10]; 9993 9994 u8 admin_mtu[0x10]; 9995 u8 reserved_at_50[0x10]; 9996 9997 u8 oper_mtu[0x10]; 9998 u8 reserved_at_70[0x10]; 9999 }; 10000 10001 struct mlx5_ifc_pmpr_reg_bits { 10002 u8 reserved_at_0[0x8]; 10003 u8 module[0x8]; 10004 u8 reserved_at_10[0x10]; 10005 10006 u8 reserved_at_20[0x18]; 10007 u8 attenuation_5g[0x8]; 10008 10009 u8 reserved_at_40[0x18]; 10010 u8 attenuation_7g[0x8]; 10011 10012 u8 reserved_at_60[0x18]; 10013 u8 attenuation_12g[0x8]; 10014 }; 10015 10016 struct mlx5_ifc_pmpe_reg_bits { 10017 u8 reserved_at_0[0x8]; 10018 u8 module[0x8]; 10019 u8 reserved_at_10[0xc]; 10020 u8 module_status[0x4]; 10021 10022 u8 reserved_at_20[0x60]; 10023 }; 10024 10025 struct mlx5_ifc_pmpc_reg_bits { 10026 u8 module_state_updated[32][0x8]; 10027 }; 10028 10029 struct mlx5_ifc_pmlpn_reg_bits { 10030 u8 reserved_at_0[0x4]; 10031 u8 mlpn_status[0x4]; 10032 u8 local_port[0x8]; 10033 u8 reserved_at_10[0x10]; 10034 10035 u8 e[0x1]; 10036 u8 reserved_at_21[0x1f]; 10037 }; 10038 10039 struct mlx5_ifc_pmlp_reg_bits { 10040 u8 rxtx[0x1]; 10041 u8 reserved_at_1[0x7]; 10042 u8 local_port[0x8]; 10043 u8 reserved_at_10[0x8]; 10044 u8 width[0x8]; 10045 10046 u8 lane0_module_mapping[0x20]; 10047 10048 u8 lane1_module_mapping[0x20]; 10049 10050 u8 lane2_module_mapping[0x20]; 10051 10052 u8 lane3_module_mapping[0x20]; 10053 10054 u8 reserved_at_a0[0x160]; 10055 }; 10056 10057 struct mlx5_ifc_pmaos_reg_bits { 10058 u8 reserved_at_0[0x8]; 10059 u8 module[0x8]; 10060 u8 reserved_at_10[0x4]; 10061 u8 admin_status[0x4]; 10062 u8 reserved_at_18[0x4]; 10063 u8 oper_status[0x4]; 10064 10065 u8 ase[0x1]; 10066 u8 ee[0x1]; 10067 u8 reserved_at_22[0x1c]; 10068 u8 e[0x2]; 10069 10070 u8 reserved_at_40[0x40]; 10071 }; 10072 10073 struct mlx5_ifc_plpc_reg_bits { 10074 u8 reserved_at_0[0x4]; 10075 u8 profile_id[0xc]; 10076 u8 reserved_at_10[0x4]; 10077 u8 proto_mask[0x4]; 10078 u8 reserved_at_18[0x8]; 10079 10080 u8 reserved_at_20[0x10]; 10081 u8 lane_speed[0x10]; 10082 10083 u8 reserved_at_40[0x17]; 10084 u8 lpbf[0x1]; 10085 u8 fec_mode_policy[0x8]; 10086 10087 u8 retransmission_capability[0x8]; 10088 u8 fec_mode_capability[0x18]; 10089 10090 u8 retransmission_support_admin[0x8]; 10091 u8 fec_mode_support_admin[0x18]; 10092 10093 u8 retransmission_request_admin[0x8]; 10094 u8 fec_mode_request_admin[0x18]; 10095 10096 u8 reserved_at_c0[0x80]; 10097 }; 10098 10099 struct mlx5_ifc_plib_reg_bits { 10100 u8 reserved_at_0[0x8]; 10101 u8 local_port[0x8]; 10102 u8 reserved_at_10[0x8]; 10103 u8 ib_port[0x8]; 10104 10105 u8 reserved_at_20[0x60]; 10106 }; 10107 10108 struct mlx5_ifc_plbf_reg_bits { 10109 u8 reserved_at_0[0x8]; 10110 u8 local_port[0x8]; 10111 u8 reserved_at_10[0xd]; 10112 u8 lbf_mode[0x3]; 10113 10114 u8 reserved_at_20[0x20]; 10115 }; 10116 10117 struct mlx5_ifc_pipg_reg_bits { 10118 u8 reserved_at_0[0x8]; 10119 u8 local_port[0x8]; 10120 u8 reserved_at_10[0x10]; 10121 10122 u8 dic[0x1]; 10123 u8 reserved_at_21[0x19]; 10124 u8 ipg[0x4]; 10125 u8 reserved_at_3e[0x2]; 10126 }; 10127 10128 struct mlx5_ifc_pifr_reg_bits { 10129 u8 reserved_at_0[0x8]; 10130 u8 local_port[0x8]; 10131 u8 reserved_at_10[0x10]; 10132 10133 u8 reserved_at_20[0xe0]; 10134 10135 u8 port_filter[8][0x20]; 10136 10137 u8 port_filter_update_en[8][0x20]; 10138 }; 10139 10140 struct mlx5_ifc_pfcc_reg_bits { 10141 u8 reserved_at_0[0x8]; 10142 u8 local_port[0x8]; 10143 u8 reserved_at_10[0xb]; 10144 u8 ppan_mask_n[0x1]; 10145 u8 minor_stall_mask[0x1]; 10146 u8 critical_stall_mask[0x1]; 10147 u8 reserved_at_1e[0x2]; 10148 10149 u8 ppan[0x4]; 10150 u8 reserved_at_24[0x4]; 10151 u8 prio_mask_tx[0x8]; 10152 u8 reserved_at_30[0x8]; 10153 u8 prio_mask_rx[0x8]; 10154 10155 u8 pptx[0x1]; 10156 u8 aptx[0x1]; 10157 u8 pptx_mask_n[0x1]; 10158 u8 reserved_at_43[0x5]; 10159 u8 pfctx[0x8]; 10160 u8 reserved_at_50[0x10]; 10161 10162 u8 pprx[0x1]; 10163 u8 aprx[0x1]; 10164 u8 pprx_mask_n[0x1]; 10165 u8 reserved_at_63[0x5]; 10166 u8 pfcrx[0x8]; 10167 u8 reserved_at_70[0x10]; 10168 10169 u8 device_stall_minor_watermark[0x10]; 10170 u8 device_stall_critical_watermark[0x10]; 10171 10172 u8 reserved_at_a0[0x60]; 10173 }; 10174 10175 struct mlx5_ifc_pelc_reg_bits { 10176 u8 op[0x4]; 10177 u8 reserved_at_4[0x4]; 10178 u8 local_port[0x8]; 10179 u8 reserved_at_10[0x10]; 10180 10181 u8 op_admin[0x8]; 10182 u8 op_capability[0x8]; 10183 u8 op_request[0x8]; 10184 u8 op_active[0x8]; 10185 10186 u8 admin[0x40]; 10187 10188 u8 capability[0x40]; 10189 10190 u8 request[0x40]; 10191 10192 u8 active[0x40]; 10193 10194 u8 reserved_at_140[0x80]; 10195 }; 10196 10197 struct mlx5_ifc_peir_reg_bits { 10198 u8 reserved_at_0[0x8]; 10199 u8 local_port[0x8]; 10200 u8 reserved_at_10[0x10]; 10201 10202 u8 reserved_at_20[0xc]; 10203 u8 error_count[0x4]; 10204 u8 reserved_at_30[0x10]; 10205 10206 u8 reserved_at_40[0xc]; 10207 u8 lane[0x4]; 10208 u8 reserved_at_50[0x8]; 10209 u8 error_type[0x8]; 10210 }; 10211 10212 struct mlx5_ifc_mpegc_reg_bits { 10213 u8 reserved_at_0[0x30]; 10214 u8 field_select[0x10]; 10215 10216 u8 tx_overflow_sense[0x1]; 10217 u8 mark_cqe[0x1]; 10218 u8 mark_cnp[0x1]; 10219 u8 reserved_at_43[0x1b]; 10220 u8 tx_lossy_overflow_oper[0x2]; 10221 10222 u8 reserved_at_60[0x100]; 10223 }; 10224 10225 struct mlx5_ifc_mpir_reg_bits { 10226 u8 sdm[0x1]; 10227 u8 reserved_at_1[0x1b]; 10228 u8 host_buses[0x4]; 10229 10230 u8 reserved_at_20[0x20]; 10231 10232 u8 local_port[0x8]; 10233 u8 reserved_at_28[0x18]; 10234 10235 u8 reserved_at_60[0x20]; 10236 }; 10237 10238 enum { 10239 MLX5_MTUTC_FREQ_ADJ_UNITS_PPB = 0x0, 10240 MLX5_MTUTC_FREQ_ADJ_UNITS_SCALED_PPM = 0x1, 10241 }; 10242 10243 enum { 10244 MLX5_MTUTC_OPERATION_SET_TIME_IMMEDIATE = 0x1, 10245 MLX5_MTUTC_OPERATION_ADJUST_TIME = 0x2, 10246 MLX5_MTUTC_OPERATION_ADJUST_FREQ_UTC = 0x3, 10247 }; 10248 10249 struct mlx5_ifc_mtutc_reg_bits { 10250 u8 reserved_at_0[0x5]; 10251 u8 freq_adj_units[0x3]; 10252 u8 reserved_at_8[0x3]; 10253 u8 log_max_freq_adjustment[0x5]; 10254 10255 u8 reserved_at_10[0xc]; 10256 u8 operation[0x4]; 10257 10258 u8 freq_adjustment[0x20]; 10259 10260 u8 reserved_at_40[0x40]; 10261 10262 u8 utc_sec[0x20]; 10263 10264 u8 reserved_at_a0[0x2]; 10265 u8 utc_nsec[0x1e]; 10266 10267 u8 time_adjustment[0x20]; 10268 }; 10269 10270 struct mlx5_ifc_pcam_enhanced_features_bits { 10271 u8 reserved_at_0[0x48]; 10272 u8 fec_100G_per_lane_in_pplm[0x1]; 10273 u8 reserved_at_49[0x1f]; 10274 u8 fec_50G_per_lane_in_pplm[0x1]; 10275 u8 reserved_at_69[0x4]; 10276 u8 rx_icrc_encapsulated_counter[0x1]; 10277 u8 reserved_at_6e[0x4]; 10278 u8 ptys_extended_ethernet[0x1]; 10279 u8 reserved_at_73[0x3]; 10280 u8 pfcc_mask[0x1]; 10281 u8 reserved_at_77[0x3]; 10282 u8 per_lane_error_counters[0x1]; 10283 u8 rx_buffer_fullness_counters[0x1]; 10284 u8 ptys_connector_type[0x1]; 10285 u8 reserved_at_7d[0x1]; 10286 u8 ppcnt_discard_group[0x1]; 10287 u8 ppcnt_statistical_group[0x1]; 10288 }; 10289 10290 struct mlx5_ifc_pcam_regs_5000_to_507f_bits { 10291 u8 port_access_reg_cap_mask_127_to_96[0x20]; 10292 u8 port_access_reg_cap_mask_95_to_64[0x20]; 10293 10294 u8 port_access_reg_cap_mask_63_to_36[0x1c]; 10295 u8 pplm[0x1]; 10296 u8 port_access_reg_cap_mask_34_to_32[0x3]; 10297 10298 u8 port_access_reg_cap_mask_31_to_13[0x13]; 10299 u8 pbmc[0x1]; 10300 u8 pptb[0x1]; 10301 u8 port_access_reg_cap_mask_10_to_09[0x2]; 10302 u8 ppcnt[0x1]; 10303 u8 port_access_reg_cap_mask_07_to_00[0x8]; 10304 }; 10305 10306 struct mlx5_ifc_pcam_reg_bits { 10307 u8 reserved_at_0[0x8]; 10308 u8 feature_group[0x8]; 10309 u8 reserved_at_10[0x8]; 10310 u8 access_reg_group[0x8]; 10311 10312 u8 reserved_at_20[0x20]; 10313 10314 union { 10315 struct mlx5_ifc_pcam_regs_5000_to_507f_bits regs_5000_to_507f; 10316 u8 reserved_at_0[0x80]; 10317 } port_access_reg_cap_mask; 10318 10319 u8 reserved_at_c0[0x80]; 10320 10321 union { 10322 struct mlx5_ifc_pcam_enhanced_features_bits enhanced_features; 10323 u8 reserved_at_0[0x80]; 10324 } feature_cap_mask; 10325 10326 u8 reserved_at_1c0[0xc0]; 10327 }; 10328 10329 struct mlx5_ifc_mcam_enhanced_features_bits { 10330 u8 reserved_at_0[0x50]; 10331 u8 mtutc_freq_adj_units[0x1]; 10332 u8 mtutc_time_adjustment_extended_range[0x1]; 10333 u8 reserved_at_52[0xb]; 10334 u8 mcia_32dwords[0x1]; 10335 u8 out_pulse_duration_ns[0x1]; 10336 u8 npps_period[0x1]; 10337 u8 reserved_at_60[0xa]; 10338 u8 reset_state[0x1]; 10339 u8 ptpcyc2realtime_modify[0x1]; 10340 u8 reserved_at_6c[0x2]; 10341 u8 pci_status_and_power[0x1]; 10342 u8 reserved_at_6f[0x5]; 10343 u8 mark_tx_action_cnp[0x1]; 10344 u8 mark_tx_action_cqe[0x1]; 10345 u8 dynamic_tx_overflow[0x1]; 10346 u8 reserved_at_77[0x4]; 10347 u8 pcie_outbound_stalled[0x1]; 10348 u8 tx_overflow_buffer_pkt[0x1]; 10349 u8 mtpps_enh_out_per_adj[0x1]; 10350 u8 mtpps_fs[0x1]; 10351 u8 pcie_performance_group[0x1]; 10352 }; 10353 10354 struct mlx5_ifc_mcam_access_reg_bits { 10355 u8 reserved_at_0[0x1c]; 10356 u8 mcda[0x1]; 10357 u8 mcc[0x1]; 10358 u8 mcqi[0x1]; 10359 u8 mcqs[0x1]; 10360 10361 u8 regs_95_to_90[0x6]; 10362 u8 mpir[0x1]; 10363 u8 regs_88_to_87[0x2]; 10364 u8 mpegc[0x1]; 10365 u8 mtutc[0x1]; 10366 u8 regs_84_to_68[0x11]; 10367 u8 tracer_registers[0x4]; 10368 10369 u8 regs_63_to_46[0x12]; 10370 u8 mrtc[0x1]; 10371 u8 regs_44_to_41[0x4]; 10372 u8 mfrl[0x1]; 10373 u8 regs_39_to_32[0x8]; 10374 10375 u8 regs_31_to_11[0x15]; 10376 u8 mtmp[0x1]; 10377 u8 regs_9_to_0[0xa]; 10378 }; 10379 10380 struct mlx5_ifc_mcam_access_reg_bits1 { 10381 u8 regs_127_to_96[0x20]; 10382 10383 u8 regs_95_to_64[0x20]; 10384 10385 u8 regs_63_to_32[0x20]; 10386 10387 u8 regs_31_to_0[0x20]; 10388 }; 10389 10390 struct mlx5_ifc_mcam_access_reg_bits2 { 10391 u8 regs_127_to_99[0x1d]; 10392 u8 mirc[0x1]; 10393 u8 regs_97_to_96[0x2]; 10394 10395 u8 regs_95_to_87[0x09]; 10396 u8 synce_registers[0x2]; 10397 u8 regs_84_to_64[0x15]; 10398 10399 u8 regs_63_to_32[0x20]; 10400 10401 u8 regs_31_to_0[0x20]; 10402 }; 10403 10404 struct mlx5_ifc_mcam_reg_bits { 10405 u8 reserved_at_0[0x8]; 10406 u8 feature_group[0x8]; 10407 u8 reserved_at_10[0x8]; 10408 u8 access_reg_group[0x8]; 10409 10410 u8 reserved_at_20[0x20]; 10411 10412 union { 10413 struct mlx5_ifc_mcam_access_reg_bits access_regs; 10414 struct mlx5_ifc_mcam_access_reg_bits1 access_regs1; 10415 struct mlx5_ifc_mcam_access_reg_bits2 access_regs2; 10416 u8 reserved_at_0[0x80]; 10417 } mng_access_reg_cap_mask; 10418 10419 u8 reserved_at_c0[0x80]; 10420 10421 union { 10422 struct mlx5_ifc_mcam_enhanced_features_bits enhanced_features; 10423 u8 reserved_at_0[0x80]; 10424 } mng_feature_cap_mask; 10425 10426 u8 reserved_at_1c0[0x80]; 10427 }; 10428 10429 struct mlx5_ifc_qcam_access_reg_cap_mask { 10430 u8 qcam_access_reg_cap_mask_127_to_20[0x6C]; 10431 u8 qpdpm[0x1]; 10432 u8 qcam_access_reg_cap_mask_18_to_4[0x0F]; 10433 u8 qdpm[0x1]; 10434 u8 qpts[0x1]; 10435 u8 qcap[0x1]; 10436 u8 qcam_access_reg_cap_mask_0[0x1]; 10437 }; 10438 10439 struct mlx5_ifc_qcam_qos_feature_cap_mask { 10440 u8 qcam_qos_feature_cap_mask_127_to_1[0x7F]; 10441 u8 qpts_trust_both[0x1]; 10442 }; 10443 10444 struct mlx5_ifc_qcam_reg_bits { 10445 u8 reserved_at_0[0x8]; 10446 u8 feature_group[0x8]; 10447 u8 reserved_at_10[0x8]; 10448 u8 access_reg_group[0x8]; 10449 u8 reserved_at_20[0x20]; 10450 10451 union { 10452 struct mlx5_ifc_qcam_access_reg_cap_mask reg_cap; 10453 u8 reserved_at_0[0x80]; 10454 } qos_access_reg_cap_mask; 10455 10456 u8 reserved_at_c0[0x80]; 10457 10458 union { 10459 struct mlx5_ifc_qcam_qos_feature_cap_mask feature_cap; 10460 u8 reserved_at_0[0x80]; 10461 } qos_feature_cap_mask; 10462 10463 u8 reserved_at_1c0[0x80]; 10464 }; 10465 10466 struct mlx5_ifc_core_dump_reg_bits { 10467 u8 reserved_at_0[0x18]; 10468 u8 core_dump_type[0x8]; 10469 10470 u8 reserved_at_20[0x30]; 10471 u8 vhca_id[0x10]; 10472 10473 u8 reserved_at_60[0x8]; 10474 u8 qpn[0x18]; 10475 u8 reserved_at_80[0x180]; 10476 }; 10477 10478 struct mlx5_ifc_pcap_reg_bits { 10479 u8 reserved_at_0[0x8]; 10480 u8 local_port[0x8]; 10481 u8 reserved_at_10[0x10]; 10482 10483 u8 port_capability_mask[4][0x20]; 10484 }; 10485 10486 struct mlx5_ifc_paos_reg_bits { 10487 u8 swid[0x8]; 10488 u8 local_port[0x8]; 10489 u8 reserved_at_10[0x4]; 10490 u8 admin_status[0x4]; 10491 u8 reserved_at_18[0x4]; 10492 u8 oper_status[0x4]; 10493 10494 u8 ase[0x1]; 10495 u8 ee[0x1]; 10496 u8 reserved_at_22[0x1c]; 10497 u8 e[0x2]; 10498 10499 u8 reserved_at_40[0x40]; 10500 }; 10501 10502 struct mlx5_ifc_pamp_reg_bits { 10503 u8 reserved_at_0[0x8]; 10504 u8 opamp_group[0x8]; 10505 u8 reserved_at_10[0xc]; 10506 u8 opamp_group_type[0x4]; 10507 10508 u8 start_index[0x10]; 10509 u8 reserved_at_30[0x4]; 10510 u8 num_of_indices[0xc]; 10511 10512 u8 index_data[18][0x10]; 10513 }; 10514 10515 struct mlx5_ifc_pcmr_reg_bits { 10516 u8 reserved_at_0[0x8]; 10517 u8 local_port[0x8]; 10518 u8 reserved_at_10[0x10]; 10519 10520 u8 entropy_force_cap[0x1]; 10521 u8 entropy_calc_cap[0x1]; 10522 u8 entropy_gre_calc_cap[0x1]; 10523 u8 reserved_at_23[0xf]; 10524 u8 rx_ts_over_crc_cap[0x1]; 10525 u8 reserved_at_33[0xb]; 10526 u8 fcs_cap[0x1]; 10527 u8 reserved_at_3f[0x1]; 10528 10529 u8 entropy_force[0x1]; 10530 u8 entropy_calc[0x1]; 10531 u8 entropy_gre_calc[0x1]; 10532 u8 reserved_at_43[0xf]; 10533 u8 rx_ts_over_crc[0x1]; 10534 u8 reserved_at_53[0xb]; 10535 u8 fcs_chk[0x1]; 10536 u8 reserved_at_5f[0x1]; 10537 }; 10538 10539 struct mlx5_ifc_lane_2_module_mapping_bits { 10540 u8 reserved_at_0[0x4]; 10541 u8 rx_lane[0x4]; 10542 u8 reserved_at_8[0x4]; 10543 u8 tx_lane[0x4]; 10544 u8 reserved_at_10[0x8]; 10545 u8 module[0x8]; 10546 }; 10547 10548 struct mlx5_ifc_bufferx_reg_bits { 10549 u8 reserved_at_0[0x6]; 10550 u8 lossy[0x1]; 10551 u8 epsb[0x1]; 10552 u8 reserved_at_8[0x8]; 10553 u8 size[0x10]; 10554 10555 u8 xoff_threshold[0x10]; 10556 u8 xon_threshold[0x10]; 10557 }; 10558 10559 struct mlx5_ifc_set_node_in_bits { 10560 u8 node_description[64][0x8]; 10561 }; 10562 10563 struct mlx5_ifc_register_power_settings_bits { 10564 u8 reserved_at_0[0x18]; 10565 u8 power_settings_level[0x8]; 10566 10567 u8 reserved_at_20[0x60]; 10568 }; 10569 10570 struct mlx5_ifc_register_host_endianness_bits { 10571 u8 he[0x1]; 10572 u8 reserved_at_1[0x1f]; 10573 10574 u8 reserved_at_20[0x60]; 10575 }; 10576 10577 struct mlx5_ifc_umr_pointer_desc_argument_bits { 10578 u8 reserved_at_0[0x20]; 10579 10580 u8 mkey[0x20]; 10581 10582 u8 addressh_63_32[0x20]; 10583 10584 u8 addressl_31_0[0x20]; 10585 }; 10586 10587 struct mlx5_ifc_ud_adrs_vector_bits { 10588 u8 dc_key[0x40]; 10589 10590 u8 ext[0x1]; 10591 u8 reserved_at_41[0x7]; 10592 u8 destination_qp_dct[0x18]; 10593 10594 u8 static_rate[0x4]; 10595 u8 sl_eth_prio[0x4]; 10596 u8 fl[0x1]; 10597 u8 mlid[0x7]; 10598 u8 rlid_udp_sport[0x10]; 10599 10600 u8 reserved_at_80[0x20]; 10601 10602 u8 rmac_47_16[0x20]; 10603 10604 u8 rmac_15_0[0x10]; 10605 u8 tclass[0x8]; 10606 u8 hop_limit[0x8]; 10607 10608 u8 reserved_at_e0[0x1]; 10609 u8 grh[0x1]; 10610 u8 reserved_at_e2[0x2]; 10611 u8 src_addr_index[0x8]; 10612 u8 flow_label[0x14]; 10613 10614 u8 rgid_rip[16][0x8]; 10615 }; 10616 10617 struct mlx5_ifc_pages_req_event_bits { 10618 u8 reserved_at_0[0x10]; 10619 u8 function_id[0x10]; 10620 10621 u8 num_pages[0x20]; 10622 10623 u8 reserved_at_40[0xa0]; 10624 }; 10625 10626 struct mlx5_ifc_eqe_bits { 10627 u8 reserved_at_0[0x8]; 10628 u8 event_type[0x8]; 10629 u8 reserved_at_10[0x8]; 10630 u8 event_sub_type[0x8]; 10631 10632 u8 reserved_at_20[0xe0]; 10633 10634 union mlx5_ifc_event_auto_bits event_data; 10635 10636 u8 reserved_at_1e0[0x10]; 10637 u8 signature[0x8]; 10638 u8 reserved_at_1f8[0x7]; 10639 u8 owner[0x1]; 10640 }; 10641 10642 enum { 10643 MLX5_CMD_QUEUE_ENTRY_TYPE_PCIE_CMD_IF_TRANSPORT = 0x7, 10644 }; 10645 10646 struct mlx5_ifc_cmd_queue_entry_bits { 10647 u8 type[0x8]; 10648 u8 reserved_at_8[0x18]; 10649 10650 u8 input_length[0x20]; 10651 10652 u8 input_mailbox_pointer_63_32[0x20]; 10653 10654 u8 input_mailbox_pointer_31_9[0x17]; 10655 u8 reserved_at_77[0x9]; 10656 10657 u8 command_input_inline_data[16][0x8]; 10658 10659 u8 command_output_inline_data[16][0x8]; 10660 10661 u8 output_mailbox_pointer_63_32[0x20]; 10662 10663 u8 output_mailbox_pointer_31_9[0x17]; 10664 u8 reserved_at_1b7[0x9]; 10665 10666 u8 output_length[0x20]; 10667 10668 u8 token[0x8]; 10669 u8 signature[0x8]; 10670 u8 reserved_at_1f0[0x8]; 10671 u8 status[0x7]; 10672 u8 ownership[0x1]; 10673 }; 10674 10675 struct mlx5_ifc_cmd_out_bits { 10676 u8 status[0x8]; 10677 u8 reserved_at_8[0x18]; 10678 10679 u8 syndrome[0x20]; 10680 10681 u8 command_output[0x20]; 10682 }; 10683 10684 struct mlx5_ifc_cmd_in_bits { 10685 u8 opcode[0x10]; 10686 u8 reserved_at_10[0x10]; 10687 10688 u8 reserved_at_20[0x10]; 10689 u8 op_mod[0x10]; 10690 10691 u8 command[][0x20]; 10692 }; 10693 10694 struct mlx5_ifc_cmd_if_box_bits { 10695 u8 mailbox_data[512][0x8]; 10696 10697 u8 reserved_at_1000[0x180]; 10698 10699 u8 next_pointer_63_32[0x20]; 10700 10701 u8 next_pointer_31_10[0x16]; 10702 u8 reserved_at_11b6[0xa]; 10703 10704 u8 block_number[0x20]; 10705 10706 u8 reserved_at_11e0[0x8]; 10707 u8 token[0x8]; 10708 u8 ctrl_signature[0x8]; 10709 u8 signature[0x8]; 10710 }; 10711 10712 struct mlx5_ifc_mtt_bits { 10713 u8 ptag_63_32[0x20]; 10714 10715 u8 ptag_31_8[0x18]; 10716 u8 reserved_at_38[0x6]; 10717 u8 wr_en[0x1]; 10718 u8 rd_en[0x1]; 10719 }; 10720 10721 struct mlx5_ifc_query_wol_rol_out_bits { 10722 u8 status[0x8]; 10723 u8 reserved_at_8[0x18]; 10724 10725 u8 syndrome[0x20]; 10726 10727 u8 reserved_at_40[0x10]; 10728 u8 rol_mode[0x8]; 10729 u8 wol_mode[0x8]; 10730 10731 u8 reserved_at_60[0x20]; 10732 }; 10733 10734 struct mlx5_ifc_query_wol_rol_in_bits { 10735 u8 opcode[0x10]; 10736 u8 reserved_at_10[0x10]; 10737 10738 u8 reserved_at_20[0x10]; 10739 u8 op_mod[0x10]; 10740 10741 u8 reserved_at_40[0x40]; 10742 }; 10743 10744 struct mlx5_ifc_set_wol_rol_out_bits { 10745 u8 status[0x8]; 10746 u8 reserved_at_8[0x18]; 10747 10748 u8 syndrome[0x20]; 10749 10750 u8 reserved_at_40[0x40]; 10751 }; 10752 10753 struct mlx5_ifc_set_wol_rol_in_bits { 10754 u8 opcode[0x10]; 10755 u8 reserved_at_10[0x10]; 10756 10757 u8 reserved_at_20[0x10]; 10758 u8 op_mod[0x10]; 10759 10760 u8 rol_mode_valid[0x1]; 10761 u8 wol_mode_valid[0x1]; 10762 u8 reserved_at_42[0xe]; 10763 u8 rol_mode[0x8]; 10764 u8 wol_mode[0x8]; 10765 10766 u8 reserved_at_60[0x20]; 10767 }; 10768 10769 enum { 10770 MLX5_INITIAL_SEG_NIC_INTERFACE_FULL_DRIVER = 0x0, 10771 MLX5_INITIAL_SEG_NIC_INTERFACE_DISABLED = 0x1, 10772 MLX5_INITIAL_SEG_NIC_INTERFACE_NO_DRAM_NIC = 0x2, 10773 MLX5_INITIAL_SEG_NIC_INTERFACE_SW_RESET = 0x7, 10774 }; 10775 10776 enum { 10777 MLX5_INITIAL_SEG_NIC_INTERFACE_SUPPORTED_FULL_DRIVER = 0x0, 10778 MLX5_INITIAL_SEG_NIC_INTERFACE_SUPPORTED_DISABLED = 0x1, 10779 MLX5_INITIAL_SEG_NIC_INTERFACE_SUPPORTED_NO_DRAM_NIC = 0x2, 10780 }; 10781 10782 enum { 10783 MLX5_INITIAL_SEG_HEALTH_SYNDROME_FW_INTERNAL_ERR = 0x1, 10784 MLX5_INITIAL_SEG_HEALTH_SYNDROME_DEAD_IRISC = 0x7, 10785 MLX5_INITIAL_SEG_HEALTH_SYNDROME_HW_FATAL_ERR = 0x8, 10786 MLX5_INITIAL_SEG_HEALTH_SYNDROME_FW_CRC_ERR = 0x9, 10787 MLX5_INITIAL_SEG_HEALTH_SYNDROME_ICM_FETCH_PCI_ERR = 0xa, 10788 MLX5_INITIAL_SEG_HEALTH_SYNDROME_ICM_PAGE_ERR = 0xb, 10789 MLX5_INITIAL_SEG_HEALTH_SYNDROME_ASYNCHRONOUS_EQ_BUF_OVERRUN = 0xc, 10790 MLX5_INITIAL_SEG_HEALTH_SYNDROME_EQ_IN_ERR = 0xd, 10791 MLX5_INITIAL_SEG_HEALTH_SYNDROME_EQ_INV = 0xe, 10792 MLX5_INITIAL_SEG_HEALTH_SYNDROME_FFSER_ERR = 0xf, 10793 MLX5_INITIAL_SEG_HEALTH_SYNDROME_HIGH_TEMP_ERR = 0x10, 10794 MLX5_INITIAL_SEG_HEALTH_SYNDROME_ICM_PCI_POISONED_ERR = 0x12, 10795 }; 10796 10797 struct mlx5_ifc_initial_seg_bits { 10798 u8 fw_rev_minor[0x10]; 10799 u8 fw_rev_major[0x10]; 10800 10801 u8 cmd_interface_rev[0x10]; 10802 u8 fw_rev_subminor[0x10]; 10803 10804 u8 reserved_at_40[0x40]; 10805 10806 u8 cmdq_phy_addr_63_32[0x20]; 10807 10808 u8 cmdq_phy_addr_31_12[0x14]; 10809 u8 reserved_at_b4[0x2]; 10810 u8 nic_interface[0x2]; 10811 u8 log_cmdq_size[0x4]; 10812 u8 log_cmdq_stride[0x4]; 10813 10814 u8 command_doorbell_vector[0x20]; 10815 10816 u8 reserved_at_e0[0xf00]; 10817 10818 u8 initializing[0x1]; 10819 u8 reserved_at_fe1[0x4]; 10820 u8 nic_interface_supported[0x3]; 10821 u8 embedded_cpu[0x1]; 10822 u8 reserved_at_fe9[0x17]; 10823 10824 struct mlx5_ifc_health_buffer_bits health_buffer; 10825 10826 u8 no_dram_nic_offset[0x20]; 10827 10828 u8 reserved_at_1220[0x6e40]; 10829 10830 u8 reserved_at_8060[0x1f]; 10831 u8 clear_int[0x1]; 10832 10833 u8 health_syndrome[0x8]; 10834 u8 health_counter[0x18]; 10835 10836 u8 reserved_at_80a0[0x17fc0]; 10837 }; 10838 10839 struct mlx5_ifc_mtpps_reg_bits { 10840 u8 reserved_at_0[0xc]; 10841 u8 cap_number_of_pps_pins[0x4]; 10842 u8 reserved_at_10[0x4]; 10843 u8 cap_max_num_of_pps_in_pins[0x4]; 10844 u8 reserved_at_18[0x4]; 10845 u8 cap_max_num_of_pps_out_pins[0x4]; 10846 10847 u8 reserved_at_20[0x13]; 10848 u8 cap_log_min_npps_period[0x5]; 10849 u8 reserved_at_38[0x3]; 10850 u8 cap_log_min_out_pulse_duration_ns[0x5]; 10851 10852 u8 reserved_at_40[0x4]; 10853 u8 cap_pin_3_mode[0x4]; 10854 u8 reserved_at_48[0x4]; 10855 u8 cap_pin_2_mode[0x4]; 10856 u8 reserved_at_50[0x4]; 10857 u8 cap_pin_1_mode[0x4]; 10858 u8 reserved_at_58[0x4]; 10859 u8 cap_pin_0_mode[0x4]; 10860 10861 u8 reserved_at_60[0x4]; 10862 u8 cap_pin_7_mode[0x4]; 10863 u8 reserved_at_68[0x4]; 10864 u8 cap_pin_6_mode[0x4]; 10865 u8 reserved_at_70[0x4]; 10866 u8 cap_pin_5_mode[0x4]; 10867 u8 reserved_at_78[0x4]; 10868 u8 cap_pin_4_mode[0x4]; 10869 10870 u8 field_select[0x20]; 10871 u8 reserved_at_a0[0x20]; 10872 10873 u8 npps_period[0x40]; 10874 10875 u8 enable[0x1]; 10876 u8 reserved_at_101[0xb]; 10877 u8 pattern[0x4]; 10878 u8 reserved_at_110[0x4]; 10879 u8 pin_mode[0x4]; 10880 u8 pin[0x8]; 10881 10882 u8 reserved_at_120[0x2]; 10883 u8 out_pulse_duration_ns[0x1e]; 10884 10885 u8 time_stamp[0x40]; 10886 10887 u8 out_pulse_duration[0x10]; 10888 u8 out_periodic_adjustment[0x10]; 10889 u8 enhanced_out_periodic_adjustment[0x20]; 10890 10891 u8 reserved_at_1c0[0x20]; 10892 }; 10893 10894 struct mlx5_ifc_mtppse_reg_bits { 10895 u8 reserved_at_0[0x18]; 10896 u8 pin[0x8]; 10897 u8 event_arm[0x1]; 10898 u8 reserved_at_21[0x1b]; 10899 u8 event_generation_mode[0x4]; 10900 u8 reserved_at_40[0x40]; 10901 }; 10902 10903 struct mlx5_ifc_mcqs_reg_bits { 10904 u8 last_index_flag[0x1]; 10905 u8 reserved_at_1[0x7]; 10906 u8 fw_device[0x8]; 10907 u8 component_index[0x10]; 10908 10909 u8 reserved_at_20[0x10]; 10910 u8 identifier[0x10]; 10911 10912 u8 reserved_at_40[0x17]; 10913 u8 component_status[0x5]; 10914 u8 component_update_state[0x4]; 10915 10916 u8 last_update_state_changer_type[0x4]; 10917 u8 last_update_state_changer_host_id[0x4]; 10918 u8 reserved_at_68[0x18]; 10919 }; 10920 10921 struct mlx5_ifc_mcqi_cap_bits { 10922 u8 supported_info_bitmask[0x20]; 10923 10924 u8 component_size[0x20]; 10925 10926 u8 max_component_size[0x20]; 10927 10928 u8 log_mcda_word_size[0x4]; 10929 u8 reserved_at_64[0xc]; 10930 u8 mcda_max_write_size[0x10]; 10931 10932 u8 rd_en[0x1]; 10933 u8 reserved_at_81[0x1]; 10934 u8 match_chip_id[0x1]; 10935 u8 match_psid[0x1]; 10936 u8 check_user_timestamp[0x1]; 10937 u8 match_base_guid_mac[0x1]; 10938 u8 reserved_at_86[0x1a]; 10939 }; 10940 10941 struct mlx5_ifc_mcqi_version_bits { 10942 u8 reserved_at_0[0x2]; 10943 u8 build_time_valid[0x1]; 10944 u8 user_defined_time_valid[0x1]; 10945 u8 reserved_at_4[0x14]; 10946 u8 version_string_length[0x8]; 10947 10948 u8 version[0x20]; 10949 10950 u8 build_time[0x40]; 10951 10952 u8 user_defined_time[0x40]; 10953 10954 u8 build_tool_version[0x20]; 10955 10956 u8 reserved_at_e0[0x20]; 10957 10958 u8 version_string[92][0x8]; 10959 }; 10960 10961 struct mlx5_ifc_mcqi_activation_method_bits { 10962 u8 pending_server_ac_power_cycle[0x1]; 10963 u8 pending_server_dc_power_cycle[0x1]; 10964 u8 pending_server_reboot[0x1]; 10965 u8 pending_fw_reset[0x1]; 10966 u8 auto_activate[0x1]; 10967 u8 all_hosts_sync[0x1]; 10968 u8 device_hw_reset[0x1]; 10969 u8 reserved_at_7[0x19]; 10970 }; 10971 10972 union mlx5_ifc_mcqi_reg_data_bits { 10973 struct mlx5_ifc_mcqi_cap_bits mcqi_caps; 10974 struct mlx5_ifc_mcqi_version_bits mcqi_version; 10975 struct mlx5_ifc_mcqi_activation_method_bits mcqi_activation_mathod; 10976 }; 10977 10978 struct mlx5_ifc_mcqi_reg_bits { 10979 u8 read_pending_component[0x1]; 10980 u8 reserved_at_1[0xf]; 10981 u8 component_index[0x10]; 10982 10983 u8 reserved_at_20[0x20]; 10984 10985 u8 reserved_at_40[0x1b]; 10986 u8 info_type[0x5]; 10987 10988 u8 info_size[0x20]; 10989 10990 u8 offset[0x20]; 10991 10992 u8 reserved_at_a0[0x10]; 10993 u8 data_size[0x10]; 10994 10995 union mlx5_ifc_mcqi_reg_data_bits data[]; 10996 }; 10997 10998 struct mlx5_ifc_mcc_reg_bits { 10999 u8 reserved_at_0[0x4]; 11000 u8 time_elapsed_since_last_cmd[0xc]; 11001 u8 reserved_at_10[0x8]; 11002 u8 instruction[0x8]; 11003 11004 u8 reserved_at_20[0x10]; 11005 u8 component_index[0x10]; 11006 11007 u8 reserved_at_40[0x8]; 11008 u8 update_handle[0x18]; 11009 11010 u8 handle_owner_type[0x4]; 11011 u8 handle_owner_host_id[0x4]; 11012 u8 reserved_at_68[0x1]; 11013 u8 control_progress[0x7]; 11014 u8 error_code[0x8]; 11015 u8 reserved_at_78[0x4]; 11016 u8 control_state[0x4]; 11017 11018 u8 component_size[0x20]; 11019 11020 u8 reserved_at_a0[0x60]; 11021 }; 11022 11023 struct mlx5_ifc_mcda_reg_bits { 11024 u8 reserved_at_0[0x8]; 11025 u8 update_handle[0x18]; 11026 11027 u8 offset[0x20]; 11028 11029 u8 reserved_at_40[0x10]; 11030 u8 size[0x10]; 11031 11032 u8 reserved_at_60[0x20]; 11033 11034 u8 data[][0x20]; 11035 }; 11036 11037 enum { 11038 MLX5_MFRL_REG_RESET_STATE_IDLE = 0, 11039 MLX5_MFRL_REG_RESET_STATE_IN_NEGOTIATION = 1, 11040 MLX5_MFRL_REG_RESET_STATE_RESET_IN_PROGRESS = 2, 11041 MLX5_MFRL_REG_RESET_STATE_NEG_TIMEOUT = 3, 11042 MLX5_MFRL_REG_RESET_STATE_NACK = 4, 11043 MLX5_MFRL_REG_RESET_STATE_UNLOAD_TIMEOUT = 5, 11044 }; 11045 11046 enum { 11047 MLX5_MFRL_REG_RESET_TYPE_FULL_CHIP = BIT(0), 11048 MLX5_MFRL_REG_RESET_TYPE_NET_PORT_ALIVE = BIT(1), 11049 }; 11050 11051 enum { 11052 MLX5_MFRL_REG_RESET_LEVEL0 = BIT(0), 11053 MLX5_MFRL_REG_RESET_LEVEL3 = BIT(3), 11054 MLX5_MFRL_REG_RESET_LEVEL6 = BIT(6), 11055 }; 11056 11057 struct mlx5_ifc_mfrl_reg_bits { 11058 u8 reserved_at_0[0x20]; 11059 11060 u8 reserved_at_20[0x2]; 11061 u8 pci_sync_for_fw_update_start[0x1]; 11062 u8 pci_sync_for_fw_update_resp[0x2]; 11063 u8 rst_type_sel[0x3]; 11064 u8 reserved_at_28[0x4]; 11065 u8 reset_state[0x4]; 11066 u8 reset_type[0x8]; 11067 u8 reset_level[0x8]; 11068 }; 11069 11070 struct mlx5_ifc_mirc_reg_bits { 11071 u8 reserved_at_0[0x18]; 11072 u8 status_code[0x8]; 11073 11074 u8 reserved_at_20[0x20]; 11075 }; 11076 11077 struct mlx5_ifc_pddr_monitor_opcode_bits { 11078 u8 reserved_at_0[0x10]; 11079 u8 monitor_opcode[0x10]; 11080 }; 11081 11082 union mlx5_ifc_pddr_troubleshooting_page_status_opcode_auto_bits { 11083 struct mlx5_ifc_pddr_monitor_opcode_bits pddr_monitor_opcode; 11084 u8 reserved_at_0[0x20]; 11085 }; 11086 11087 enum { 11088 /* Monitor opcodes */ 11089 MLX5_PDDR_REG_TRBLSH_GROUP_OPCODE_MONITOR = 0x0, 11090 }; 11091 11092 struct mlx5_ifc_pddr_troubleshooting_page_bits { 11093 u8 reserved_at_0[0x10]; 11094 u8 group_opcode[0x10]; 11095 11096 union mlx5_ifc_pddr_troubleshooting_page_status_opcode_auto_bits status_opcode; 11097 11098 u8 reserved_at_40[0x20]; 11099 11100 u8 status_message[59][0x20]; 11101 }; 11102 11103 union mlx5_ifc_pddr_reg_page_data_auto_bits { 11104 struct mlx5_ifc_pddr_troubleshooting_page_bits pddr_troubleshooting_page; 11105 u8 reserved_at_0[0x7c0]; 11106 }; 11107 11108 enum { 11109 MLX5_PDDR_REG_PAGE_SELECT_TROUBLESHOOTING_INFO_PAGE = 0x1, 11110 }; 11111 11112 struct mlx5_ifc_pddr_reg_bits { 11113 u8 reserved_at_0[0x8]; 11114 u8 local_port[0x8]; 11115 u8 pnat[0x2]; 11116 u8 reserved_at_12[0xe]; 11117 11118 u8 reserved_at_20[0x18]; 11119 u8 page_select[0x8]; 11120 11121 union mlx5_ifc_pddr_reg_page_data_auto_bits page_data; 11122 }; 11123 11124 struct mlx5_ifc_mrtc_reg_bits { 11125 u8 time_synced[0x1]; 11126 u8 reserved_at_1[0x1f]; 11127 11128 u8 reserved_at_20[0x20]; 11129 11130 u8 time_h[0x20]; 11131 11132 u8 time_l[0x20]; 11133 }; 11134 11135 struct mlx5_ifc_mtcap_reg_bits { 11136 u8 reserved_at_0[0x19]; 11137 u8 sensor_count[0x7]; 11138 11139 u8 reserved_at_20[0x20]; 11140 11141 u8 sensor_map[0x40]; 11142 }; 11143 11144 struct mlx5_ifc_mtmp_reg_bits { 11145 u8 reserved_at_0[0x14]; 11146 u8 sensor_index[0xc]; 11147 11148 u8 reserved_at_20[0x10]; 11149 u8 temperature[0x10]; 11150 11151 u8 mte[0x1]; 11152 u8 mtr[0x1]; 11153 u8 reserved_at_42[0xe]; 11154 u8 max_temperature[0x10]; 11155 11156 u8 tee[0x2]; 11157 u8 reserved_at_62[0xe]; 11158 u8 temp_threshold_hi[0x10]; 11159 11160 u8 reserved_at_80[0x10]; 11161 u8 temp_threshold_lo[0x10]; 11162 11163 u8 reserved_at_a0[0x20]; 11164 11165 u8 sensor_name_hi[0x20]; 11166 u8 sensor_name_lo[0x20]; 11167 }; 11168 11169 union mlx5_ifc_ports_control_registers_document_bits { 11170 struct mlx5_ifc_bufferx_reg_bits bufferx_reg; 11171 struct mlx5_ifc_eth_2819_cntrs_grp_data_layout_bits eth_2819_cntrs_grp_data_layout; 11172 struct mlx5_ifc_eth_2863_cntrs_grp_data_layout_bits eth_2863_cntrs_grp_data_layout; 11173 struct mlx5_ifc_eth_3635_cntrs_grp_data_layout_bits eth_3635_cntrs_grp_data_layout; 11174 struct mlx5_ifc_eth_802_3_cntrs_grp_data_layout_bits eth_802_3_cntrs_grp_data_layout; 11175 struct mlx5_ifc_eth_extended_cntrs_grp_data_layout_bits eth_extended_cntrs_grp_data_layout; 11176 struct mlx5_ifc_eth_per_prio_grp_data_layout_bits eth_per_prio_grp_data_layout; 11177 struct mlx5_ifc_eth_per_tc_prio_grp_data_layout_bits eth_per_tc_prio_grp_data_layout; 11178 struct mlx5_ifc_eth_per_tc_congest_prio_grp_data_layout_bits eth_per_tc_congest_prio_grp_data_layout; 11179 struct mlx5_ifc_lane_2_module_mapping_bits lane_2_module_mapping; 11180 struct mlx5_ifc_pamp_reg_bits pamp_reg; 11181 struct mlx5_ifc_paos_reg_bits paos_reg; 11182 struct mlx5_ifc_pcap_reg_bits pcap_reg; 11183 struct mlx5_ifc_pddr_monitor_opcode_bits pddr_monitor_opcode; 11184 struct mlx5_ifc_pddr_reg_bits pddr_reg; 11185 struct mlx5_ifc_pddr_troubleshooting_page_bits pddr_troubleshooting_page; 11186 struct mlx5_ifc_peir_reg_bits peir_reg; 11187 struct mlx5_ifc_pelc_reg_bits pelc_reg; 11188 struct mlx5_ifc_pfcc_reg_bits pfcc_reg; 11189 struct mlx5_ifc_ib_port_cntrs_grp_data_layout_bits ib_port_cntrs_grp_data_layout; 11190 struct mlx5_ifc_phys_layer_cntrs_bits phys_layer_cntrs; 11191 struct mlx5_ifc_pifr_reg_bits pifr_reg; 11192 struct mlx5_ifc_pipg_reg_bits pipg_reg; 11193 struct mlx5_ifc_plbf_reg_bits plbf_reg; 11194 struct mlx5_ifc_plib_reg_bits plib_reg; 11195 struct mlx5_ifc_plpc_reg_bits plpc_reg; 11196 struct mlx5_ifc_pmaos_reg_bits pmaos_reg; 11197 struct mlx5_ifc_pmlp_reg_bits pmlp_reg; 11198 struct mlx5_ifc_pmlpn_reg_bits pmlpn_reg; 11199 struct mlx5_ifc_pmpc_reg_bits pmpc_reg; 11200 struct mlx5_ifc_pmpe_reg_bits pmpe_reg; 11201 struct mlx5_ifc_pmpr_reg_bits pmpr_reg; 11202 struct mlx5_ifc_pmtu_reg_bits pmtu_reg; 11203 struct mlx5_ifc_ppad_reg_bits ppad_reg; 11204 struct mlx5_ifc_ppcnt_reg_bits ppcnt_reg; 11205 struct mlx5_ifc_mpein_reg_bits mpein_reg; 11206 struct mlx5_ifc_mpcnt_reg_bits mpcnt_reg; 11207 struct mlx5_ifc_pplm_reg_bits pplm_reg; 11208 struct mlx5_ifc_pplr_reg_bits pplr_reg; 11209 struct mlx5_ifc_ppsc_reg_bits ppsc_reg; 11210 struct mlx5_ifc_pqdr_reg_bits pqdr_reg; 11211 struct mlx5_ifc_pspa_reg_bits pspa_reg; 11212 struct mlx5_ifc_ptas_reg_bits ptas_reg; 11213 struct mlx5_ifc_ptys_reg_bits ptys_reg; 11214 struct mlx5_ifc_mlcr_reg_bits mlcr_reg; 11215 struct mlx5_ifc_pude_reg_bits pude_reg; 11216 struct mlx5_ifc_pvlc_reg_bits pvlc_reg; 11217 struct mlx5_ifc_slrg_reg_bits slrg_reg; 11218 struct mlx5_ifc_sltp_reg_bits sltp_reg; 11219 struct mlx5_ifc_mtpps_reg_bits mtpps_reg; 11220 struct mlx5_ifc_mtppse_reg_bits mtppse_reg; 11221 struct mlx5_ifc_fpga_access_reg_bits fpga_access_reg; 11222 struct mlx5_ifc_fpga_ctrl_bits fpga_ctrl_bits; 11223 struct mlx5_ifc_fpga_cap_bits fpga_cap_bits; 11224 struct mlx5_ifc_mcqi_reg_bits mcqi_reg; 11225 struct mlx5_ifc_mcc_reg_bits mcc_reg; 11226 struct mlx5_ifc_mcda_reg_bits mcda_reg; 11227 struct mlx5_ifc_mirc_reg_bits mirc_reg; 11228 struct mlx5_ifc_mfrl_reg_bits mfrl_reg; 11229 struct mlx5_ifc_mtutc_reg_bits mtutc_reg; 11230 struct mlx5_ifc_mrtc_reg_bits mrtc_reg; 11231 struct mlx5_ifc_mtcap_reg_bits mtcap_reg; 11232 struct mlx5_ifc_mtmp_reg_bits mtmp_reg; 11233 u8 reserved_at_0[0x60e0]; 11234 }; 11235 11236 union mlx5_ifc_debug_enhancements_document_bits { 11237 struct mlx5_ifc_health_buffer_bits health_buffer; 11238 u8 reserved_at_0[0x200]; 11239 }; 11240 11241 union mlx5_ifc_uplink_pci_interface_document_bits { 11242 struct mlx5_ifc_initial_seg_bits initial_seg; 11243 u8 reserved_at_0[0x20060]; 11244 }; 11245 11246 struct mlx5_ifc_set_flow_table_root_out_bits { 11247 u8 status[0x8]; 11248 u8 reserved_at_8[0x18]; 11249 11250 u8 syndrome[0x20]; 11251 11252 u8 reserved_at_40[0x40]; 11253 }; 11254 11255 struct mlx5_ifc_set_flow_table_root_in_bits { 11256 u8 opcode[0x10]; 11257 u8 reserved_at_10[0x10]; 11258 11259 u8 reserved_at_20[0x10]; 11260 u8 op_mod[0x10]; 11261 11262 u8 other_vport[0x1]; 11263 u8 reserved_at_41[0xf]; 11264 u8 vport_number[0x10]; 11265 11266 u8 reserved_at_60[0x20]; 11267 11268 u8 table_type[0x8]; 11269 u8 reserved_at_88[0x7]; 11270 u8 table_of_other_vport[0x1]; 11271 u8 table_vport_number[0x10]; 11272 11273 u8 reserved_at_a0[0x8]; 11274 u8 table_id[0x18]; 11275 11276 u8 reserved_at_c0[0x8]; 11277 u8 underlay_qpn[0x18]; 11278 u8 table_eswitch_owner_vhca_id_valid[0x1]; 11279 u8 reserved_at_e1[0xf]; 11280 u8 table_eswitch_owner_vhca_id[0x10]; 11281 u8 reserved_at_100[0x100]; 11282 }; 11283 11284 enum { 11285 MLX5_MODIFY_FLOW_TABLE_MISS_TABLE_ID = (1UL << 0), 11286 MLX5_MODIFY_FLOW_TABLE_LAG_NEXT_TABLE_ID = (1UL << 15), 11287 }; 11288 11289 struct mlx5_ifc_modify_flow_table_out_bits { 11290 u8 status[0x8]; 11291 u8 reserved_at_8[0x18]; 11292 11293 u8 syndrome[0x20]; 11294 11295 u8 reserved_at_40[0x40]; 11296 }; 11297 11298 struct mlx5_ifc_modify_flow_table_in_bits { 11299 u8 opcode[0x10]; 11300 u8 reserved_at_10[0x10]; 11301 11302 u8 reserved_at_20[0x10]; 11303 u8 op_mod[0x10]; 11304 11305 u8 other_vport[0x1]; 11306 u8 reserved_at_41[0xf]; 11307 u8 vport_number[0x10]; 11308 11309 u8 reserved_at_60[0x10]; 11310 u8 modify_field_select[0x10]; 11311 11312 u8 table_type[0x8]; 11313 u8 reserved_at_88[0x18]; 11314 11315 u8 reserved_at_a0[0x8]; 11316 u8 table_id[0x18]; 11317 11318 struct mlx5_ifc_flow_table_context_bits flow_table_context; 11319 }; 11320 11321 struct mlx5_ifc_ets_tcn_config_reg_bits { 11322 u8 g[0x1]; 11323 u8 b[0x1]; 11324 u8 r[0x1]; 11325 u8 reserved_at_3[0x9]; 11326 u8 group[0x4]; 11327 u8 reserved_at_10[0x9]; 11328 u8 bw_allocation[0x7]; 11329 11330 u8 reserved_at_20[0xc]; 11331 u8 max_bw_units[0x4]; 11332 u8 reserved_at_30[0x8]; 11333 u8 max_bw_value[0x8]; 11334 }; 11335 11336 struct mlx5_ifc_ets_global_config_reg_bits { 11337 u8 reserved_at_0[0x2]; 11338 u8 r[0x1]; 11339 u8 reserved_at_3[0x1d]; 11340 11341 u8 reserved_at_20[0xc]; 11342 u8 max_bw_units[0x4]; 11343 u8 reserved_at_30[0x8]; 11344 u8 max_bw_value[0x8]; 11345 }; 11346 11347 struct mlx5_ifc_qetc_reg_bits { 11348 u8 reserved_at_0[0x8]; 11349 u8 port_number[0x8]; 11350 u8 reserved_at_10[0x30]; 11351 11352 struct mlx5_ifc_ets_tcn_config_reg_bits tc_configuration[0x8]; 11353 struct mlx5_ifc_ets_global_config_reg_bits global_configuration; 11354 }; 11355 11356 struct mlx5_ifc_qpdpm_dscp_reg_bits { 11357 u8 e[0x1]; 11358 u8 reserved_at_01[0x0b]; 11359 u8 prio[0x04]; 11360 }; 11361 11362 struct mlx5_ifc_qpdpm_reg_bits { 11363 u8 reserved_at_0[0x8]; 11364 u8 local_port[0x8]; 11365 u8 reserved_at_10[0x10]; 11366 struct mlx5_ifc_qpdpm_dscp_reg_bits dscp[64]; 11367 }; 11368 11369 struct mlx5_ifc_qpts_reg_bits { 11370 u8 reserved_at_0[0x8]; 11371 u8 local_port[0x8]; 11372 u8 reserved_at_10[0x2d]; 11373 u8 trust_state[0x3]; 11374 }; 11375 11376 struct mlx5_ifc_pptb_reg_bits { 11377 u8 reserved_at_0[0x2]; 11378 u8 mm[0x2]; 11379 u8 reserved_at_4[0x4]; 11380 u8 local_port[0x8]; 11381 u8 reserved_at_10[0x6]; 11382 u8 cm[0x1]; 11383 u8 um[0x1]; 11384 u8 pm[0x8]; 11385 11386 u8 prio_x_buff[0x20]; 11387 11388 u8 pm_msb[0x8]; 11389 u8 reserved_at_48[0x10]; 11390 u8 ctrl_buff[0x4]; 11391 u8 untagged_buff[0x4]; 11392 }; 11393 11394 struct mlx5_ifc_sbcam_reg_bits { 11395 u8 reserved_at_0[0x8]; 11396 u8 feature_group[0x8]; 11397 u8 reserved_at_10[0x8]; 11398 u8 access_reg_group[0x8]; 11399 11400 u8 reserved_at_20[0x20]; 11401 11402 u8 sb_access_reg_cap_mask[4][0x20]; 11403 11404 u8 reserved_at_c0[0x80]; 11405 11406 u8 sb_feature_cap_mask[4][0x20]; 11407 11408 u8 reserved_at_1c0[0x40]; 11409 11410 u8 cap_total_buffer_size[0x20]; 11411 11412 u8 cap_cell_size[0x10]; 11413 u8 cap_max_pg_buffers[0x8]; 11414 u8 cap_num_pool_supported[0x8]; 11415 11416 u8 reserved_at_240[0x8]; 11417 u8 cap_sbsr_stat_size[0x8]; 11418 u8 cap_max_tclass_data[0x8]; 11419 u8 cap_max_cpu_ingress_tclass_sb[0x8]; 11420 }; 11421 11422 struct mlx5_ifc_pbmc_reg_bits { 11423 u8 reserved_at_0[0x8]; 11424 u8 local_port[0x8]; 11425 u8 reserved_at_10[0x10]; 11426 11427 u8 xoff_timer_value[0x10]; 11428 u8 xoff_refresh[0x10]; 11429 11430 u8 reserved_at_40[0x9]; 11431 u8 fullness_threshold[0x7]; 11432 u8 port_buffer_size[0x10]; 11433 11434 struct mlx5_ifc_bufferx_reg_bits buffer[10]; 11435 11436 u8 reserved_at_2e0[0x80]; 11437 }; 11438 11439 struct mlx5_ifc_sbpr_reg_bits { 11440 u8 desc[0x1]; 11441 u8 snap[0x1]; 11442 u8 reserved_at_2[0x4]; 11443 u8 dir[0x2]; 11444 u8 reserved_at_8[0x14]; 11445 u8 pool[0x4]; 11446 11447 u8 infi_size[0x1]; 11448 u8 reserved_at_21[0x7]; 11449 u8 size[0x18]; 11450 11451 u8 reserved_at_40[0x1c]; 11452 u8 mode[0x4]; 11453 11454 u8 reserved_at_60[0x8]; 11455 u8 buff_occupancy[0x18]; 11456 11457 u8 clr[0x1]; 11458 u8 reserved_at_81[0x7]; 11459 u8 max_buff_occupancy[0x18]; 11460 11461 u8 reserved_at_a0[0x8]; 11462 u8 ext_buff_occupancy[0x18]; 11463 }; 11464 11465 struct mlx5_ifc_sbcm_reg_bits { 11466 u8 desc[0x1]; 11467 u8 snap[0x1]; 11468 u8 reserved_at_2[0x6]; 11469 u8 local_port[0x8]; 11470 u8 pnat[0x2]; 11471 u8 pg_buff[0x6]; 11472 u8 reserved_at_18[0x6]; 11473 u8 dir[0x2]; 11474 11475 u8 reserved_at_20[0x1f]; 11476 u8 exc[0x1]; 11477 11478 u8 reserved_at_40[0x40]; 11479 11480 u8 reserved_at_80[0x8]; 11481 u8 buff_occupancy[0x18]; 11482 11483 u8 clr[0x1]; 11484 u8 reserved_at_a1[0x7]; 11485 u8 max_buff_occupancy[0x18]; 11486 11487 u8 reserved_at_c0[0x8]; 11488 u8 min_buff[0x18]; 11489 11490 u8 infi_max[0x1]; 11491 u8 reserved_at_e1[0x7]; 11492 u8 max_buff[0x18]; 11493 11494 u8 reserved_at_100[0x20]; 11495 11496 u8 reserved_at_120[0x1c]; 11497 u8 pool[0x4]; 11498 }; 11499 11500 struct mlx5_ifc_qtct_reg_bits { 11501 u8 reserved_at_0[0x8]; 11502 u8 port_number[0x8]; 11503 u8 reserved_at_10[0xd]; 11504 u8 prio[0x3]; 11505 11506 u8 reserved_at_20[0x1d]; 11507 u8 tclass[0x3]; 11508 }; 11509 11510 struct mlx5_ifc_mcia_reg_bits { 11511 u8 l[0x1]; 11512 u8 reserved_at_1[0x7]; 11513 u8 module[0x8]; 11514 u8 reserved_at_10[0x8]; 11515 u8 status[0x8]; 11516 11517 u8 i2c_device_address[0x8]; 11518 u8 page_number[0x8]; 11519 u8 device_address[0x10]; 11520 11521 u8 reserved_at_40[0x10]; 11522 u8 size[0x10]; 11523 11524 u8 reserved_at_60[0x20]; 11525 11526 u8 dword_0[0x20]; 11527 u8 dword_1[0x20]; 11528 u8 dword_2[0x20]; 11529 u8 dword_3[0x20]; 11530 u8 dword_4[0x20]; 11531 u8 dword_5[0x20]; 11532 u8 dword_6[0x20]; 11533 u8 dword_7[0x20]; 11534 u8 dword_8[0x20]; 11535 u8 dword_9[0x20]; 11536 u8 dword_10[0x20]; 11537 u8 dword_11[0x20]; 11538 }; 11539 11540 struct mlx5_ifc_dcbx_param_bits { 11541 u8 dcbx_cee_cap[0x1]; 11542 u8 dcbx_ieee_cap[0x1]; 11543 u8 dcbx_standby_cap[0x1]; 11544 u8 reserved_at_3[0x5]; 11545 u8 port_number[0x8]; 11546 u8 reserved_at_10[0xa]; 11547 u8 max_application_table_size[6]; 11548 u8 reserved_at_20[0x15]; 11549 u8 version_oper[0x3]; 11550 u8 reserved_at_38[5]; 11551 u8 version_admin[0x3]; 11552 u8 willing_admin[0x1]; 11553 u8 reserved_at_41[0x3]; 11554 u8 pfc_cap_oper[0x4]; 11555 u8 reserved_at_48[0x4]; 11556 u8 pfc_cap_admin[0x4]; 11557 u8 reserved_at_50[0x4]; 11558 u8 num_of_tc_oper[0x4]; 11559 u8 reserved_at_58[0x4]; 11560 u8 num_of_tc_admin[0x4]; 11561 u8 remote_willing[0x1]; 11562 u8 reserved_at_61[3]; 11563 u8 remote_pfc_cap[4]; 11564 u8 reserved_at_68[0x14]; 11565 u8 remote_num_of_tc[0x4]; 11566 u8 reserved_at_80[0x18]; 11567 u8 error[0x8]; 11568 u8 reserved_at_a0[0x160]; 11569 }; 11570 11571 enum { 11572 MLX5_LAG_PORT_SELECT_MODE_QUEUE_AFFINITY = 0, 11573 MLX5_LAG_PORT_SELECT_MODE_PORT_SELECT_FT = 1, 11574 MLX5_LAG_PORT_SELECT_MODE_PORT_SELECT_MPESW = 2, 11575 }; 11576 11577 struct mlx5_ifc_lagc_bits { 11578 u8 fdb_selection_mode[0x1]; 11579 u8 reserved_at_1[0x14]; 11580 u8 port_select_mode[0x3]; 11581 u8 reserved_at_18[0x5]; 11582 u8 lag_state[0x3]; 11583 11584 u8 reserved_at_20[0xc]; 11585 u8 active_port[0x4]; 11586 u8 reserved_at_30[0x4]; 11587 u8 tx_remap_affinity_2[0x4]; 11588 u8 reserved_at_38[0x4]; 11589 u8 tx_remap_affinity_1[0x4]; 11590 }; 11591 11592 struct mlx5_ifc_create_lag_out_bits { 11593 u8 status[0x8]; 11594 u8 reserved_at_8[0x18]; 11595 11596 u8 syndrome[0x20]; 11597 11598 u8 reserved_at_40[0x40]; 11599 }; 11600 11601 struct mlx5_ifc_create_lag_in_bits { 11602 u8 opcode[0x10]; 11603 u8 reserved_at_10[0x10]; 11604 11605 u8 reserved_at_20[0x10]; 11606 u8 op_mod[0x10]; 11607 11608 struct mlx5_ifc_lagc_bits ctx; 11609 }; 11610 11611 struct mlx5_ifc_modify_lag_out_bits { 11612 u8 status[0x8]; 11613 u8 reserved_at_8[0x18]; 11614 11615 u8 syndrome[0x20]; 11616 11617 u8 reserved_at_40[0x40]; 11618 }; 11619 11620 struct mlx5_ifc_modify_lag_in_bits { 11621 u8 opcode[0x10]; 11622 u8 reserved_at_10[0x10]; 11623 11624 u8 reserved_at_20[0x10]; 11625 u8 op_mod[0x10]; 11626 11627 u8 reserved_at_40[0x20]; 11628 u8 field_select[0x20]; 11629 11630 struct mlx5_ifc_lagc_bits ctx; 11631 }; 11632 11633 struct mlx5_ifc_query_lag_out_bits { 11634 u8 status[0x8]; 11635 u8 reserved_at_8[0x18]; 11636 11637 u8 syndrome[0x20]; 11638 11639 struct mlx5_ifc_lagc_bits ctx; 11640 }; 11641 11642 struct mlx5_ifc_query_lag_in_bits { 11643 u8 opcode[0x10]; 11644 u8 reserved_at_10[0x10]; 11645 11646 u8 reserved_at_20[0x10]; 11647 u8 op_mod[0x10]; 11648 11649 u8 reserved_at_40[0x40]; 11650 }; 11651 11652 struct mlx5_ifc_destroy_lag_out_bits { 11653 u8 status[0x8]; 11654 u8 reserved_at_8[0x18]; 11655 11656 u8 syndrome[0x20]; 11657 11658 u8 reserved_at_40[0x40]; 11659 }; 11660 11661 struct mlx5_ifc_destroy_lag_in_bits { 11662 u8 opcode[0x10]; 11663 u8 reserved_at_10[0x10]; 11664 11665 u8 reserved_at_20[0x10]; 11666 u8 op_mod[0x10]; 11667 11668 u8 reserved_at_40[0x40]; 11669 }; 11670 11671 struct mlx5_ifc_create_vport_lag_out_bits { 11672 u8 status[0x8]; 11673 u8 reserved_at_8[0x18]; 11674 11675 u8 syndrome[0x20]; 11676 11677 u8 reserved_at_40[0x40]; 11678 }; 11679 11680 struct mlx5_ifc_create_vport_lag_in_bits { 11681 u8 opcode[0x10]; 11682 u8 reserved_at_10[0x10]; 11683 11684 u8 reserved_at_20[0x10]; 11685 u8 op_mod[0x10]; 11686 11687 u8 reserved_at_40[0x40]; 11688 }; 11689 11690 struct mlx5_ifc_destroy_vport_lag_out_bits { 11691 u8 status[0x8]; 11692 u8 reserved_at_8[0x18]; 11693 11694 u8 syndrome[0x20]; 11695 11696 u8 reserved_at_40[0x40]; 11697 }; 11698 11699 struct mlx5_ifc_destroy_vport_lag_in_bits { 11700 u8 opcode[0x10]; 11701 u8 reserved_at_10[0x10]; 11702 11703 u8 reserved_at_20[0x10]; 11704 u8 op_mod[0x10]; 11705 11706 u8 reserved_at_40[0x40]; 11707 }; 11708 11709 enum { 11710 MLX5_MODIFY_MEMIC_OP_MOD_ALLOC, 11711 MLX5_MODIFY_MEMIC_OP_MOD_DEALLOC, 11712 }; 11713 11714 struct mlx5_ifc_modify_memic_in_bits { 11715 u8 opcode[0x10]; 11716 u8 uid[0x10]; 11717 11718 u8 reserved_at_20[0x10]; 11719 u8 op_mod[0x10]; 11720 11721 u8 reserved_at_40[0x20]; 11722 11723 u8 reserved_at_60[0x18]; 11724 u8 memic_operation_type[0x8]; 11725 11726 u8 memic_start_addr[0x40]; 11727 11728 u8 reserved_at_c0[0x140]; 11729 }; 11730 11731 struct mlx5_ifc_modify_memic_out_bits { 11732 u8 status[0x8]; 11733 u8 reserved_at_8[0x18]; 11734 11735 u8 syndrome[0x20]; 11736 11737 u8 reserved_at_40[0x40]; 11738 11739 u8 memic_operation_addr[0x40]; 11740 11741 u8 reserved_at_c0[0x140]; 11742 }; 11743 11744 struct mlx5_ifc_alloc_memic_in_bits { 11745 u8 opcode[0x10]; 11746 u8 reserved_at_10[0x10]; 11747 11748 u8 reserved_at_20[0x10]; 11749 u8 op_mod[0x10]; 11750 11751 u8 reserved_at_30[0x20]; 11752 11753 u8 reserved_at_40[0x18]; 11754 u8 log_memic_addr_alignment[0x8]; 11755 11756 u8 range_start_addr[0x40]; 11757 11758 u8 range_size[0x20]; 11759 11760 u8 memic_size[0x20]; 11761 }; 11762 11763 struct mlx5_ifc_alloc_memic_out_bits { 11764 u8 status[0x8]; 11765 u8 reserved_at_8[0x18]; 11766 11767 u8 syndrome[0x20]; 11768 11769 u8 memic_start_addr[0x40]; 11770 }; 11771 11772 struct mlx5_ifc_dealloc_memic_in_bits { 11773 u8 opcode[0x10]; 11774 u8 reserved_at_10[0x10]; 11775 11776 u8 reserved_at_20[0x10]; 11777 u8 op_mod[0x10]; 11778 11779 u8 reserved_at_40[0x40]; 11780 11781 u8 memic_start_addr[0x40]; 11782 11783 u8 memic_size[0x20]; 11784 11785 u8 reserved_at_e0[0x20]; 11786 }; 11787 11788 struct mlx5_ifc_dealloc_memic_out_bits { 11789 u8 status[0x8]; 11790 u8 reserved_at_8[0x18]; 11791 11792 u8 syndrome[0x20]; 11793 11794 u8 reserved_at_40[0x40]; 11795 }; 11796 11797 struct mlx5_ifc_umem_bits { 11798 u8 reserved_at_0[0x80]; 11799 11800 u8 ats[0x1]; 11801 u8 reserved_at_81[0x1a]; 11802 u8 log_page_size[0x5]; 11803 11804 u8 page_offset[0x20]; 11805 11806 u8 num_of_mtt[0x40]; 11807 11808 struct mlx5_ifc_mtt_bits mtt[]; 11809 }; 11810 11811 struct mlx5_ifc_uctx_bits { 11812 u8 cap[0x20]; 11813 11814 u8 reserved_at_20[0x160]; 11815 }; 11816 11817 struct mlx5_ifc_sw_icm_bits { 11818 u8 modify_field_select[0x40]; 11819 11820 u8 reserved_at_40[0x18]; 11821 u8 log_sw_icm_size[0x8]; 11822 11823 u8 reserved_at_60[0x20]; 11824 11825 u8 sw_icm_start_addr[0x40]; 11826 11827 u8 reserved_at_c0[0x140]; 11828 }; 11829 11830 struct mlx5_ifc_geneve_tlv_option_bits { 11831 u8 modify_field_select[0x40]; 11832 11833 u8 reserved_at_40[0x18]; 11834 u8 geneve_option_fte_index[0x8]; 11835 11836 u8 option_class[0x10]; 11837 u8 option_type[0x8]; 11838 u8 reserved_at_78[0x3]; 11839 u8 option_data_length[0x5]; 11840 11841 u8 reserved_at_80[0x180]; 11842 }; 11843 11844 struct mlx5_ifc_create_umem_in_bits { 11845 u8 opcode[0x10]; 11846 u8 uid[0x10]; 11847 11848 u8 reserved_at_20[0x10]; 11849 u8 op_mod[0x10]; 11850 11851 u8 reserved_at_40[0x40]; 11852 11853 struct mlx5_ifc_umem_bits umem; 11854 }; 11855 11856 struct mlx5_ifc_create_umem_out_bits { 11857 u8 status[0x8]; 11858 u8 reserved_at_8[0x18]; 11859 11860 u8 syndrome[0x20]; 11861 11862 u8 reserved_at_40[0x8]; 11863 u8 umem_id[0x18]; 11864 11865 u8 reserved_at_60[0x20]; 11866 }; 11867 11868 struct mlx5_ifc_destroy_umem_in_bits { 11869 u8 opcode[0x10]; 11870 u8 uid[0x10]; 11871 11872 u8 reserved_at_20[0x10]; 11873 u8 op_mod[0x10]; 11874 11875 u8 reserved_at_40[0x8]; 11876 u8 umem_id[0x18]; 11877 11878 u8 reserved_at_60[0x20]; 11879 }; 11880 11881 struct mlx5_ifc_destroy_umem_out_bits { 11882 u8 status[0x8]; 11883 u8 reserved_at_8[0x18]; 11884 11885 u8 syndrome[0x20]; 11886 11887 u8 reserved_at_40[0x40]; 11888 }; 11889 11890 struct mlx5_ifc_create_uctx_in_bits { 11891 u8 opcode[0x10]; 11892 u8 reserved_at_10[0x10]; 11893 11894 u8 reserved_at_20[0x10]; 11895 u8 op_mod[0x10]; 11896 11897 u8 reserved_at_40[0x40]; 11898 11899 struct mlx5_ifc_uctx_bits uctx; 11900 }; 11901 11902 struct mlx5_ifc_create_uctx_out_bits { 11903 u8 status[0x8]; 11904 u8 reserved_at_8[0x18]; 11905 11906 u8 syndrome[0x20]; 11907 11908 u8 reserved_at_40[0x10]; 11909 u8 uid[0x10]; 11910 11911 u8 reserved_at_60[0x20]; 11912 }; 11913 11914 struct mlx5_ifc_destroy_uctx_in_bits { 11915 u8 opcode[0x10]; 11916 u8 reserved_at_10[0x10]; 11917 11918 u8 reserved_at_20[0x10]; 11919 u8 op_mod[0x10]; 11920 11921 u8 reserved_at_40[0x10]; 11922 u8 uid[0x10]; 11923 11924 u8 reserved_at_60[0x20]; 11925 }; 11926 11927 struct mlx5_ifc_destroy_uctx_out_bits { 11928 u8 status[0x8]; 11929 u8 reserved_at_8[0x18]; 11930 11931 u8 syndrome[0x20]; 11932 11933 u8 reserved_at_40[0x40]; 11934 }; 11935 11936 struct mlx5_ifc_create_sw_icm_in_bits { 11937 struct mlx5_ifc_general_obj_in_cmd_hdr_bits hdr; 11938 struct mlx5_ifc_sw_icm_bits sw_icm; 11939 }; 11940 11941 struct mlx5_ifc_create_geneve_tlv_option_in_bits { 11942 struct mlx5_ifc_general_obj_in_cmd_hdr_bits hdr; 11943 struct mlx5_ifc_geneve_tlv_option_bits geneve_tlv_opt; 11944 }; 11945 11946 struct mlx5_ifc_mtrc_string_db_param_bits { 11947 u8 string_db_base_address[0x20]; 11948 11949 u8 reserved_at_20[0x8]; 11950 u8 string_db_size[0x18]; 11951 }; 11952 11953 struct mlx5_ifc_mtrc_cap_bits { 11954 u8 trace_owner[0x1]; 11955 u8 trace_to_memory[0x1]; 11956 u8 reserved_at_2[0x4]; 11957 u8 trc_ver[0x2]; 11958 u8 reserved_at_8[0x14]; 11959 u8 num_string_db[0x4]; 11960 11961 u8 first_string_trace[0x8]; 11962 u8 num_string_trace[0x8]; 11963 u8 reserved_at_30[0x28]; 11964 11965 u8 log_max_trace_buffer_size[0x8]; 11966 11967 u8 reserved_at_60[0x20]; 11968 11969 struct mlx5_ifc_mtrc_string_db_param_bits string_db_param[8]; 11970 11971 u8 reserved_at_280[0x180]; 11972 }; 11973 11974 struct mlx5_ifc_mtrc_conf_bits { 11975 u8 reserved_at_0[0x1c]; 11976 u8 trace_mode[0x4]; 11977 u8 reserved_at_20[0x18]; 11978 u8 log_trace_buffer_size[0x8]; 11979 u8 trace_mkey[0x20]; 11980 u8 reserved_at_60[0x3a0]; 11981 }; 11982 11983 struct mlx5_ifc_mtrc_stdb_bits { 11984 u8 string_db_index[0x4]; 11985 u8 reserved_at_4[0x4]; 11986 u8 read_size[0x18]; 11987 u8 start_offset[0x20]; 11988 u8 string_db_data[]; 11989 }; 11990 11991 struct mlx5_ifc_mtrc_ctrl_bits { 11992 u8 trace_status[0x2]; 11993 u8 reserved_at_2[0x2]; 11994 u8 arm_event[0x1]; 11995 u8 reserved_at_5[0xb]; 11996 u8 modify_field_select[0x10]; 11997 u8 reserved_at_20[0x2b]; 11998 u8 current_timestamp52_32[0x15]; 11999 u8 current_timestamp31_0[0x20]; 12000 u8 reserved_at_80[0x180]; 12001 }; 12002 12003 struct mlx5_ifc_host_params_context_bits { 12004 u8 host_number[0x8]; 12005 u8 reserved_at_8[0x7]; 12006 u8 host_pf_disabled[0x1]; 12007 u8 host_num_of_vfs[0x10]; 12008 12009 u8 host_total_vfs[0x10]; 12010 u8 host_pci_bus[0x10]; 12011 12012 u8 reserved_at_40[0x10]; 12013 u8 host_pci_device[0x10]; 12014 12015 u8 reserved_at_60[0x10]; 12016 u8 host_pci_function[0x10]; 12017 12018 u8 reserved_at_80[0x180]; 12019 }; 12020 12021 struct mlx5_ifc_query_esw_functions_in_bits { 12022 u8 opcode[0x10]; 12023 u8 reserved_at_10[0x10]; 12024 12025 u8 reserved_at_20[0x10]; 12026 u8 op_mod[0x10]; 12027 12028 u8 reserved_at_40[0x40]; 12029 }; 12030 12031 struct mlx5_ifc_query_esw_functions_out_bits { 12032 u8 status[0x8]; 12033 u8 reserved_at_8[0x18]; 12034 12035 u8 syndrome[0x20]; 12036 12037 u8 reserved_at_40[0x40]; 12038 12039 struct mlx5_ifc_host_params_context_bits host_params_context; 12040 12041 u8 reserved_at_280[0x180]; 12042 u8 host_sf_enable[][0x40]; 12043 }; 12044 12045 struct mlx5_ifc_sf_partition_bits { 12046 u8 reserved_at_0[0x10]; 12047 u8 log_num_sf[0x8]; 12048 u8 log_sf_bar_size[0x8]; 12049 }; 12050 12051 struct mlx5_ifc_query_sf_partitions_out_bits { 12052 u8 status[0x8]; 12053 u8 reserved_at_8[0x18]; 12054 12055 u8 syndrome[0x20]; 12056 12057 u8 reserved_at_40[0x18]; 12058 u8 num_sf_partitions[0x8]; 12059 12060 u8 reserved_at_60[0x20]; 12061 12062 struct mlx5_ifc_sf_partition_bits sf_partition[]; 12063 }; 12064 12065 struct mlx5_ifc_query_sf_partitions_in_bits { 12066 u8 opcode[0x10]; 12067 u8 reserved_at_10[0x10]; 12068 12069 u8 reserved_at_20[0x10]; 12070 u8 op_mod[0x10]; 12071 12072 u8 reserved_at_40[0x40]; 12073 }; 12074 12075 struct mlx5_ifc_dealloc_sf_out_bits { 12076 u8 status[0x8]; 12077 u8 reserved_at_8[0x18]; 12078 12079 u8 syndrome[0x20]; 12080 12081 u8 reserved_at_40[0x40]; 12082 }; 12083 12084 struct mlx5_ifc_dealloc_sf_in_bits { 12085 u8 opcode[0x10]; 12086 u8 reserved_at_10[0x10]; 12087 12088 u8 reserved_at_20[0x10]; 12089 u8 op_mod[0x10]; 12090 12091 u8 reserved_at_40[0x10]; 12092 u8 function_id[0x10]; 12093 12094 u8 reserved_at_60[0x20]; 12095 }; 12096 12097 struct mlx5_ifc_alloc_sf_out_bits { 12098 u8 status[0x8]; 12099 u8 reserved_at_8[0x18]; 12100 12101 u8 syndrome[0x20]; 12102 12103 u8 reserved_at_40[0x40]; 12104 }; 12105 12106 struct mlx5_ifc_alloc_sf_in_bits { 12107 u8 opcode[0x10]; 12108 u8 reserved_at_10[0x10]; 12109 12110 u8 reserved_at_20[0x10]; 12111 u8 op_mod[0x10]; 12112 12113 u8 reserved_at_40[0x10]; 12114 u8 function_id[0x10]; 12115 12116 u8 reserved_at_60[0x20]; 12117 }; 12118 12119 struct mlx5_ifc_affiliated_event_header_bits { 12120 u8 reserved_at_0[0x10]; 12121 u8 obj_type[0x10]; 12122 12123 u8 obj_id[0x20]; 12124 }; 12125 12126 enum { 12127 MLX5_HCA_CAP_GENERAL_OBJECT_TYPES_ENCRYPTION_KEY = BIT_ULL(0xc), 12128 MLX5_HCA_CAP_GENERAL_OBJECT_TYPES_IPSEC = BIT_ULL(0x13), 12129 MLX5_HCA_CAP_GENERAL_OBJECT_TYPES_SAMPLER = BIT_ULL(0x20), 12130 MLX5_HCA_CAP_GENERAL_OBJECT_TYPES_FLOW_METER_ASO = BIT_ULL(0x24), 12131 }; 12132 12133 enum { 12134 MLX5_GENERAL_OBJECT_TYPES_ENCRYPTION_KEY = 0xc, 12135 MLX5_GENERAL_OBJECT_TYPES_IPSEC = 0x13, 12136 MLX5_GENERAL_OBJECT_TYPES_SAMPLER = 0x20, 12137 MLX5_GENERAL_OBJECT_TYPES_FLOW_METER_ASO = 0x24, 12138 MLX5_GENERAL_OBJECT_TYPES_MACSEC = 0x27, 12139 MLX5_GENERAL_OBJECT_TYPES_INT_KEK = 0x47, 12140 MLX5_GENERAL_OBJECT_TYPES_FLOW_TABLE_ALIAS = 0xff15, 12141 }; 12142 12143 enum { 12144 MLX5_IPSEC_OBJECT_ICV_LEN_16B, 12145 }; 12146 12147 enum { 12148 MLX5_IPSEC_ASO_REG_C_0_1 = 0x0, 12149 MLX5_IPSEC_ASO_REG_C_2_3 = 0x1, 12150 MLX5_IPSEC_ASO_REG_C_4_5 = 0x2, 12151 MLX5_IPSEC_ASO_REG_C_6_7 = 0x3, 12152 }; 12153 12154 enum { 12155 MLX5_IPSEC_ASO_MODE = 0x0, 12156 MLX5_IPSEC_ASO_REPLAY_PROTECTION = 0x1, 12157 MLX5_IPSEC_ASO_INC_SN = 0x2, 12158 }; 12159 12160 enum { 12161 MLX5_IPSEC_ASO_REPLAY_WIN_32BIT = 0x0, 12162 MLX5_IPSEC_ASO_REPLAY_WIN_64BIT = 0x1, 12163 MLX5_IPSEC_ASO_REPLAY_WIN_128BIT = 0x2, 12164 MLX5_IPSEC_ASO_REPLAY_WIN_256BIT = 0x3, 12165 }; 12166 12167 struct mlx5_ifc_ipsec_aso_bits { 12168 u8 valid[0x1]; 12169 u8 reserved_at_201[0x1]; 12170 u8 mode[0x2]; 12171 u8 window_sz[0x2]; 12172 u8 soft_lft_arm[0x1]; 12173 u8 hard_lft_arm[0x1]; 12174 u8 remove_flow_enable[0x1]; 12175 u8 esn_event_arm[0x1]; 12176 u8 reserved_at_20a[0x16]; 12177 12178 u8 remove_flow_pkt_cnt[0x20]; 12179 12180 u8 remove_flow_soft_lft[0x20]; 12181 12182 u8 reserved_at_260[0x80]; 12183 12184 u8 mode_parameter[0x20]; 12185 12186 u8 replay_protection_window[0x100]; 12187 }; 12188 12189 struct mlx5_ifc_ipsec_obj_bits { 12190 u8 modify_field_select[0x40]; 12191 u8 full_offload[0x1]; 12192 u8 reserved_at_41[0x1]; 12193 u8 esn_en[0x1]; 12194 u8 esn_overlap[0x1]; 12195 u8 reserved_at_44[0x2]; 12196 u8 icv_length[0x2]; 12197 u8 reserved_at_48[0x4]; 12198 u8 aso_return_reg[0x4]; 12199 u8 reserved_at_50[0x10]; 12200 12201 u8 esn_msb[0x20]; 12202 12203 u8 reserved_at_80[0x8]; 12204 u8 dekn[0x18]; 12205 12206 u8 salt[0x20]; 12207 12208 u8 implicit_iv[0x40]; 12209 12210 u8 reserved_at_100[0x8]; 12211 u8 ipsec_aso_access_pd[0x18]; 12212 u8 reserved_at_120[0xe0]; 12213 12214 struct mlx5_ifc_ipsec_aso_bits ipsec_aso; 12215 }; 12216 12217 struct mlx5_ifc_create_ipsec_obj_in_bits { 12218 struct mlx5_ifc_general_obj_in_cmd_hdr_bits general_obj_in_cmd_hdr; 12219 struct mlx5_ifc_ipsec_obj_bits ipsec_object; 12220 }; 12221 12222 enum { 12223 MLX5_MODIFY_IPSEC_BITMASK_ESN_OVERLAP = BIT(0), 12224 MLX5_MODIFY_IPSEC_BITMASK_ESN_MSB = BIT(1), 12225 }; 12226 12227 struct mlx5_ifc_query_ipsec_obj_out_bits { 12228 struct mlx5_ifc_general_obj_out_cmd_hdr_bits general_obj_out_cmd_hdr; 12229 struct mlx5_ifc_ipsec_obj_bits ipsec_object; 12230 }; 12231 12232 struct mlx5_ifc_modify_ipsec_obj_in_bits { 12233 struct mlx5_ifc_general_obj_in_cmd_hdr_bits general_obj_in_cmd_hdr; 12234 struct mlx5_ifc_ipsec_obj_bits ipsec_object; 12235 }; 12236 12237 enum { 12238 MLX5_MACSEC_ASO_REPLAY_PROTECTION = 0x1, 12239 }; 12240 12241 enum { 12242 MLX5_MACSEC_ASO_REPLAY_WIN_32BIT = 0x0, 12243 MLX5_MACSEC_ASO_REPLAY_WIN_64BIT = 0x1, 12244 MLX5_MACSEC_ASO_REPLAY_WIN_128BIT = 0x2, 12245 MLX5_MACSEC_ASO_REPLAY_WIN_256BIT = 0x3, 12246 }; 12247 12248 #define MLX5_MACSEC_ASO_INC_SN 0x2 12249 #define MLX5_MACSEC_ASO_REG_C_4_5 0x2 12250 12251 struct mlx5_ifc_macsec_aso_bits { 12252 u8 valid[0x1]; 12253 u8 reserved_at_1[0x1]; 12254 u8 mode[0x2]; 12255 u8 window_size[0x2]; 12256 u8 soft_lifetime_arm[0x1]; 12257 u8 hard_lifetime_arm[0x1]; 12258 u8 remove_flow_enable[0x1]; 12259 u8 epn_event_arm[0x1]; 12260 u8 reserved_at_a[0x16]; 12261 12262 u8 remove_flow_packet_count[0x20]; 12263 12264 u8 remove_flow_soft_lifetime[0x20]; 12265 12266 u8 reserved_at_60[0x80]; 12267 12268 u8 mode_parameter[0x20]; 12269 12270 u8 replay_protection_window[8][0x20]; 12271 }; 12272 12273 struct mlx5_ifc_macsec_offload_obj_bits { 12274 u8 modify_field_select[0x40]; 12275 12276 u8 confidentiality_en[0x1]; 12277 u8 reserved_at_41[0x1]; 12278 u8 epn_en[0x1]; 12279 u8 epn_overlap[0x1]; 12280 u8 reserved_at_44[0x2]; 12281 u8 confidentiality_offset[0x2]; 12282 u8 reserved_at_48[0x4]; 12283 u8 aso_return_reg[0x4]; 12284 u8 reserved_at_50[0x10]; 12285 12286 u8 epn_msb[0x20]; 12287 12288 u8 reserved_at_80[0x8]; 12289 u8 dekn[0x18]; 12290 12291 u8 reserved_at_a0[0x20]; 12292 12293 u8 sci[0x40]; 12294 12295 u8 reserved_at_100[0x8]; 12296 u8 macsec_aso_access_pd[0x18]; 12297 12298 u8 reserved_at_120[0x60]; 12299 12300 u8 salt[3][0x20]; 12301 12302 u8 reserved_at_1e0[0x20]; 12303 12304 struct mlx5_ifc_macsec_aso_bits macsec_aso; 12305 }; 12306 12307 struct mlx5_ifc_create_macsec_obj_in_bits { 12308 struct mlx5_ifc_general_obj_in_cmd_hdr_bits general_obj_in_cmd_hdr; 12309 struct mlx5_ifc_macsec_offload_obj_bits macsec_object; 12310 }; 12311 12312 struct mlx5_ifc_modify_macsec_obj_in_bits { 12313 struct mlx5_ifc_general_obj_in_cmd_hdr_bits general_obj_in_cmd_hdr; 12314 struct mlx5_ifc_macsec_offload_obj_bits macsec_object; 12315 }; 12316 12317 enum { 12318 MLX5_MODIFY_MACSEC_BITMASK_EPN_OVERLAP = BIT(0), 12319 MLX5_MODIFY_MACSEC_BITMASK_EPN_MSB = BIT(1), 12320 }; 12321 12322 struct mlx5_ifc_query_macsec_obj_out_bits { 12323 struct mlx5_ifc_general_obj_out_cmd_hdr_bits general_obj_out_cmd_hdr; 12324 struct mlx5_ifc_macsec_offload_obj_bits macsec_object; 12325 }; 12326 12327 struct mlx5_ifc_wrapped_dek_bits { 12328 u8 gcm_iv[0x60]; 12329 12330 u8 reserved_at_60[0x20]; 12331 12332 u8 const0[0x1]; 12333 u8 key_size[0x1]; 12334 u8 reserved_at_82[0x2]; 12335 u8 key2_invalid[0x1]; 12336 u8 reserved_at_85[0x3]; 12337 u8 pd[0x18]; 12338 12339 u8 key_purpose[0x5]; 12340 u8 reserved_at_a5[0x13]; 12341 u8 kek_id[0x8]; 12342 12343 u8 reserved_at_c0[0x40]; 12344 12345 u8 key1[0x8][0x20]; 12346 12347 u8 key2[0x8][0x20]; 12348 12349 u8 reserved_at_300[0x40]; 12350 12351 u8 const1[0x1]; 12352 u8 reserved_at_341[0x1f]; 12353 12354 u8 reserved_at_360[0x20]; 12355 12356 u8 auth_tag[0x80]; 12357 }; 12358 12359 struct mlx5_ifc_encryption_key_obj_bits { 12360 u8 modify_field_select[0x40]; 12361 12362 u8 state[0x8]; 12363 u8 sw_wrapped[0x1]; 12364 u8 reserved_at_49[0xb]; 12365 u8 key_size[0x4]; 12366 u8 reserved_at_58[0x4]; 12367 u8 key_purpose[0x4]; 12368 12369 u8 reserved_at_60[0x8]; 12370 u8 pd[0x18]; 12371 12372 u8 reserved_at_80[0x100]; 12373 12374 u8 opaque[0x40]; 12375 12376 u8 reserved_at_1c0[0x40]; 12377 12378 u8 key[8][0x80]; 12379 12380 u8 sw_wrapped_dek[8][0x80]; 12381 12382 u8 reserved_at_a00[0x600]; 12383 }; 12384 12385 struct mlx5_ifc_create_encryption_key_in_bits { 12386 struct mlx5_ifc_general_obj_in_cmd_hdr_bits general_obj_in_cmd_hdr; 12387 struct mlx5_ifc_encryption_key_obj_bits encryption_key_object; 12388 }; 12389 12390 struct mlx5_ifc_modify_encryption_key_in_bits { 12391 struct mlx5_ifc_general_obj_in_cmd_hdr_bits general_obj_in_cmd_hdr; 12392 struct mlx5_ifc_encryption_key_obj_bits encryption_key_object; 12393 }; 12394 12395 enum { 12396 MLX5_FLOW_METER_MODE_BYTES_IP_LENGTH = 0x0, 12397 MLX5_FLOW_METER_MODE_BYTES_CALC_WITH_L2 = 0x1, 12398 MLX5_FLOW_METER_MODE_BYTES_CALC_WITH_L2_IPG = 0x2, 12399 MLX5_FLOW_METER_MODE_NUM_PACKETS = 0x3, 12400 }; 12401 12402 struct mlx5_ifc_flow_meter_parameters_bits { 12403 u8 valid[0x1]; 12404 u8 bucket_overflow[0x1]; 12405 u8 start_color[0x2]; 12406 u8 both_buckets_on_green[0x1]; 12407 u8 reserved_at_5[0x1]; 12408 u8 meter_mode[0x2]; 12409 u8 reserved_at_8[0x18]; 12410 12411 u8 reserved_at_20[0x20]; 12412 12413 u8 reserved_at_40[0x3]; 12414 u8 cbs_exponent[0x5]; 12415 u8 cbs_mantissa[0x8]; 12416 u8 reserved_at_50[0x3]; 12417 u8 cir_exponent[0x5]; 12418 u8 cir_mantissa[0x8]; 12419 12420 u8 reserved_at_60[0x20]; 12421 12422 u8 reserved_at_80[0x3]; 12423 u8 ebs_exponent[0x5]; 12424 u8 ebs_mantissa[0x8]; 12425 u8 reserved_at_90[0x3]; 12426 u8 eir_exponent[0x5]; 12427 u8 eir_mantissa[0x8]; 12428 12429 u8 reserved_at_a0[0x60]; 12430 }; 12431 12432 struct mlx5_ifc_flow_meter_aso_obj_bits { 12433 u8 modify_field_select[0x40]; 12434 12435 u8 reserved_at_40[0x40]; 12436 12437 u8 reserved_at_80[0x8]; 12438 u8 meter_aso_access_pd[0x18]; 12439 12440 u8 reserved_at_a0[0x160]; 12441 12442 struct mlx5_ifc_flow_meter_parameters_bits flow_meter_parameters[2]; 12443 }; 12444 12445 struct mlx5_ifc_create_flow_meter_aso_obj_in_bits { 12446 struct mlx5_ifc_general_obj_in_cmd_hdr_bits hdr; 12447 struct mlx5_ifc_flow_meter_aso_obj_bits flow_meter_aso_obj; 12448 }; 12449 12450 struct mlx5_ifc_int_kek_obj_bits { 12451 u8 modify_field_select[0x40]; 12452 12453 u8 state[0x8]; 12454 u8 auto_gen[0x1]; 12455 u8 reserved_at_49[0xb]; 12456 u8 key_size[0x4]; 12457 u8 reserved_at_58[0x8]; 12458 12459 u8 reserved_at_60[0x8]; 12460 u8 pd[0x18]; 12461 12462 u8 reserved_at_80[0x180]; 12463 u8 key[8][0x80]; 12464 12465 u8 reserved_at_600[0x200]; 12466 }; 12467 12468 struct mlx5_ifc_create_int_kek_obj_in_bits { 12469 struct mlx5_ifc_general_obj_in_cmd_hdr_bits general_obj_in_cmd_hdr; 12470 struct mlx5_ifc_int_kek_obj_bits int_kek_object; 12471 }; 12472 12473 struct mlx5_ifc_create_int_kek_obj_out_bits { 12474 struct mlx5_ifc_general_obj_out_cmd_hdr_bits general_obj_out_cmd_hdr; 12475 struct mlx5_ifc_int_kek_obj_bits int_kek_object; 12476 }; 12477 12478 struct mlx5_ifc_sampler_obj_bits { 12479 u8 modify_field_select[0x40]; 12480 12481 u8 table_type[0x8]; 12482 u8 level[0x8]; 12483 u8 reserved_at_50[0xf]; 12484 u8 ignore_flow_level[0x1]; 12485 12486 u8 sample_ratio[0x20]; 12487 12488 u8 reserved_at_80[0x8]; 12489 u8 sample_table_id[0x18]; 12490 12491 u8 reserved_at_a0[0x8]; 12492 u8 default_table_id[0x18]; 12493 12494 u8 sw_steering_icm_address_rx[0x40]; 12495 u8 sw_steering_icm_address_tx[0x40]; 12496 12497 u8 reserved_at_140[0xa0]; 12498 }; 12499 12500 struct mlx5_ifc_create_sampler_obj_in_bits { 12501 struct mlx5_ifc_general_obj_in_cmd_hdr_bits general_obj_in_cmd_hdr; 12502 struct mlx5_ifc_sampler_obj_bits sampler_object; 12503 }; 12504 12505 struct mlx5_ifc_query_sampler_obj_out_bits { 12506 struct mlx5_ifc_general_obj_out_cmd_hdr_bits general_obj_out_cmd_hdr; 12507 struct mlx5_ifc_sampler_obj_bits sampler_object; 12508 }; 12509 12510 enum { 12511 MLX5_GENERAL_OBJECT_TYPE_ENCRYPTION_KEY_KEY_SIZE_128 = 0x0, 12512 MLX5_GENERAL_OBJECT_TYPE_ENCRYPTION_KEY_KEY_SIZE_256 = 0x1, 12513 }; 12514 12515 enum { 12516 MLX5_GENERAL_OBJECT_TYPE_ENCRYPTION_KEY_PURPOSE_TLS = 0x1, 12517 MLX5_GENERAL_OBJECT_TYPE_ENCRYPTION_KEY_PURPOSE_IPSEC = 0x2, 12518 MLX5_GENERAL_OBJECT_TYPE_ENCRYPTION_KEY_PURPOSE_MACSEC = 0x4, 12519 }; 12520 12521 struct mlx5_ifc_tls_static_params_bits { 12522 u8 const_2[0x2]; 12523 u8 tls_version[0x4]; 12524 u8 const_1[0x2]; 12525 u8 reserved_at_8[0x14]; 12526 u8 encryption_standard[0x4]; 12527 12528 u8 reserved_at_20[0x20]; 12529 12530 u8 initial_record_number[0x40]; 12531 12532 u8 resync_tcp_sn[0x20]; 12533 12534 u8 gcm_iv[0x20]; 12535 12536 u8 implicit_iv[0x40]; 12537 12538 u8 reserved_at_100[0x8]; 12539 u8 dek_index[0x18]; 12540 12541 u8 reserved_at_120[0xe0]; 12542 }; 12543 12544 struct mlx5_ifc_tls_progress_params_bits { 12545 u8 next_record_tcp_sn[0x20]; 12546 12547 u8 hw_resync_tcp_sn[0x20]; 12548 12549 u8 record_tracker_state[0x2]; 12550 u8 auth_state[0x2]; 12551 u8 reserved_at_44[0x4]; 12552 u8 hw_offset_record_number[0x18]; 12553 }; 12554 12555 enum { 12556 MLX5_MTT_PERM_READ = 1 << 0, 12557 MLX5_MTT_PERM_WRITE = 1 << 1, 12558 MLX5_MTT_PERM_RW = MLX5_MTT_PERM_READ | MLX5_MTT_PERM_WRITE, 12559 }; 12560 12561 enum { 12562 MLX5_SUSPEND_VHCA_IN_OP_MOD_SUSPEND_INITIATOR = 0x0, 12563 MLX5_SUSPEND_VHCA_IN_OP_MOD_SUSPEND_RESPONDER = 0x1, 12564 }; 12565 12566 struct mlx5_ifc_suspend_vhca_in_bits { 12567 u8 opcode[0x10]; 12568 u8 uid[0x10]; 12569 12570 u8 reserved_at_20[0x10]; 12571 u8 op_mod[0x10]; 12572 12573 u8 reserved_at_40[0x10]; 12574 u8 vhca_id[0x10]; 12575 12576 u8 reserved_at_60[0x20]; 12577 }; 12578 12579 struct mlx5_ifc_suspend_vhca_out_bits { 12580 u8 status[0x8]; 12581 u8 reserved_at_8[0x18]; 12582 12583 u8 syndrome[0x20]; 12584 12585 u8 reserved_at_40[0x40]; 12586 }; 12587 12588 enum { 12589 MLX5_RESUME_VHCA_IN_OP_MOD_RESUME_RESPONDER = 0x0, 12590 MLX5_RESUME_VHCA_IN_OP_MOD_RESUME_INITIATOR = 0x1, 12591 }; 12592 12593 struct mlx5_ifc_resume_vhca_in_bits { 12594 u8 opcode[0x10]; 12595 u8 uid[0x10]; 12596 12597 u8 reserved_at_20[0x10]; 12598 u8 op_mod[0x10]; 12599 12600 u8 reserved_at_40[0x10]; 12601 u8 vhca_id[0x10]; 12602 12603 u8 reserved_at_60[0x20]; 12604 }; 12605 12606 struct mlx5_ifc_resume_vhca_out_bits { 12607 u8 status[0x8]; 12608 u8 reserved_at_8[0x18]; 12609 12610 u8 syndrome[0x20]; 12611 12612 u8 reserved_at_40[0x40]; 12613 }; 12614 12615 struct mlx5_ifc_query_vhca_migration_state_in_bits { 12616 u8 opcode[0x10]; 12617 u8 uid[0x10]; 12618 12619 u8 reserved_at_20[0x10]; 12620 u8 op_mod[0x10]; 12621 12622 u8 incremental[0x1]; 12623 u8 chunk[0x1]; 12624 u8 reserved_at_42[0xe]; 12625 u8 vhca_id[0x10]; 12626 12627 u8 reserved_at_60[0x20]; 12628 }; 12629 12630 struct mlx5_ifc_query_vhca_migration_state_out_bits { 12631 u8 status[0x8]; 12632 u8 reserved_at_8[0x18]; 12633 12634 u8 syndrome[0x20]; 12635 12636 u8 reserved_at_40[0x40]; 12637 12638 u8 required_umem_size[0x20]; 12639 12640 u8 reserved_at_a0[0x20]; 12641 12642 u8 remaining_total_size[0x40]; 12643 12644 u8 reserved_at_100[0x100]; 12645 }; 12646 12647 struct mlx5_ifc_save_vhca_state_in_bits { 12648 u8 opcode[0x10]; 12649 u8 uid[0x10]; 12650 12651 u8 reserved_at_20[0x10]; 12652 u8 op_mod[0x10]; 12653 12654 u8 incremental[0x1]; 12655 u8 set_track[0x1]; 12656 u8 reserved_at_42[0xe]; 12657 u8 vhca_id[0x10]; 12658 12659 u8 reserved_at_60[0x20]; 12660 12661 u8 va[0x40]; 12662 12663 u8 mkey[0x20]; 12664 12665 u8 size[0x20]; 12666 }; 12667 12668 struct mlx5_ifc_save_vhca_state_out_bits { 12669 u8 status[0x8]; 12670 u8 reserved_at_8[0x18]; 12671 12672 u8 syndrome[0x20]; 12673 12674 u8 actual_image_size[0x20]; 12675 12676 u8 next_required_umem_size[0x20]; 12677 }; 12678 12679 struct mlx5_ifc_load_vhca_state_in_bits { 12680 u8 opcode[0x10]; 12681 u8 uid[0x10]; 12682 12683 u8 reserved_at_20[0x10]; 12684 u8 op_mod[0x10]; 12685 12686 u8 reserved_at_40[0x10]; 12687 u8 vhca_id[0x10]; 12688 12689 u8 reserved_at_60[0x20]; 12690 12691 u8 va[0x40]; 12692 12693 u8 mkey[0x20]; 12694 12695 u8 size[0x20]; 12696 }; 12697 12698 struct mlx5_ifc_load_vhca_state_out_bits { 12699 u8 status[0x8]; 12700 u8 reserved_at_8[0x18]; 12701 12702 u8 syndrome[0x20]; 12703 12704 u8 reserved_at_40[0x40]; 12705 }; 12706 12707 struct mlx5_ifc_adv_virtualization_cap_bits { 12708 u8 reserved_at_0[0x3]; 12709 u8 pg_track_log_max_num[0x5]; 12710 u8 pg_track_max_num_range[0x8]; 12711 u8 pg_track_log_min_addr_space[0x8]; 12712 u8 pg_track_log_max_addr_space[0x8]; 12713 12714 u8 reserved_at_20[0x3]; 12715 u8 pg_track_log_min_msg_size[0x5]; 12716 u8 reserved_at_28[0x3]; 12717 u8 pg_track_log_max_msg_size[0x5]; 12718 u8 reserved_at_30[0x3]; 12719 u8 pg_track_log_min_page_size[0x5]; 12720 u8 reserved_at_38[0x3]; 12721 u8 pg_track_log_max_page_size[0x5]; 12722 12723 u8 reserved_at_40[0x7c0]; 12724 }; 12725 12726 struct mlx5_ifc_page_track_report_entry_bits { 12727 u8 dirty_address_high[0x20]; 12728 12729 u8 dirty_address_low[0x20]; 12730 }; 12731 12732 enum { 12733 MLX5_PAGE_TRACK_STATE_TRACKING, 12734 MLX5_PAGE_TRACK_STATE_REPORTING, 12735 MLX5_PAGE_TRACK_STATE_ERROR, 12736 }; 12737 12738 struct mlx5_ifc_page_track_range_bits { 12739 u8 start_address[0x40]; 12740 12741 u8 length[0x40]; 12742 }; 12743 12744 struct mlx5_ifc_page_track_bits { 12745 u8 modify_field_select[0x40]; 12746 12747 u8 reserved_at_40[0x10]; 12748 u8 vhca_id[0x10]; 12749 12750 u8 reserved_at_60[0x20]; 12751 12752 u8 state[0x4]; 12753 u8 track_type[0x4]; 12754 u8 log_addr_space_size[0x8]; 12755 u8 reserved_at_90[0x3]; 12756 u8 log_page_size[0x5]; 12757 u8 reserved_at_98[0x3]; 12758 u8 log_msg_size[0x5]; 12759 12760 u8 reserved_at_a0[0x8]; 12761 u8 reporting_qpn[0x18]; 12762 12763 u8 reserved_at_c0[0x18]; 12764 u8 num_ranges[0x8]; 12765 12766 u8 reserved_at_e0[0x20]; 12767 12768 u8 range_start_address[0x40]; 12769 12770 u8 length[0x40]; 12771 12772 struct mlx5_ifc_page_track_range_bits track_range[0]; 12773 }; 12774 12775 struct mlx5_ifc_create_page_track_obj_in_bits { 12776 struct mlx5_ifc_general_obj_in_cmd_hdr_bits general_obj_in_cmd_hdr; 12777 struct mlx5_ifc_page_track_bits obj_context; 12778 }; 12779 12780 struct mlx5_ifc_modify_page_track_obj_in_bits { 12781 struct mlx5_ifc_general_obj_in_cmd_hdr_bits general_obj_in_cmd_hdr; 12782 struct mlx5_ifc_page_track_bits obj_context; 12783 }; 12784 12785 struct mlx5_ifc_query_page_track_obj_out_bits { 12786 struct mlx5_ifc_general_obj_out_cmd_hdr_bits general_obj_out_cmd_hdr; 12787 struct mlx5_ifc_page_track_bits obj_context; 12788 }; 12789 12790 struct mlx5_ifc_msecq_reg_bits { 12791 u8 reserved_at_0[0x20]; 12792 12793 u8 reserved_at_20[0x12]; 12794 u8 network_option[0x2]; 12795 u8 local_ssm_code[0x4]; 12796 u8 local_enhanced_ssm_code[0x8]; 12797 12798 u8 local_clock_identity[0x40]; 12799 12800 u8 reserved_at_80[0x180]; 12801 }; 12802 12803 enum { 12804 MLX5_MSEES_FIELD_SELECT_ENABLE = BIT(0), 12805 MLX5_MSEES_FIELD_SELECT_ADMIN_STATUS = BIT(1), 12806 MLX5_MSEES_FIELD_SELECT_ADMIN_FREQ_MEASURE = BIT(2), 12807 }; 12808 12809 enum mlx5_msees_admin_status { 12810 MLX5_MSEES_ADMIN_STATUS_FREE_RUNNING = 0x0, 12811 MLX5_MSEES_ADMIN_STATUS_TRACK = 0x1, 12812 }; 12813 12814 enum mlx5_msees_oper_status { 12815 MLX5_MSEES_OPER_STATUS_FREE_RUNNING = 0x0, 12816 MLX5_MSEES_OPER_STATUS_SELF_TRACK = 0x1, 12817 MLX5_MSEES_OPER_STATUS_OTHER_TRACK = 0x2, 12818 MLX5_MSEES_OPER_STATUS_HOLDOVER = 0x3, 12819 MLX5_MSEES_OPER_STATUS_FAIL_HOLDOVER = 0x4, 12820 MLX5_MSEES_OPER_STATUS_FAIL_FREE_RUNNING = 0x5, 12821 }; 12822 12823 enum mlx5_msees_failure_reason { 12824 MLX5_MSEES_FAILURE_REASON_UNDEFINED_ERROR = 0x0, 12825 MLX5_MSEES_FAILURE_REASON_PORT_DOWN = 0x1, 12826 MLX5_MSEES_FAILURE_REASON_TOO_HIGH_FREQUENCY_DIFF = 0x2, 12827 MLX5_MSEES_FAILURE_REASON_NET_SYNCHRONIZER_DEVICE_ERROR = 0x3, 12828 MLX5_MSEES_FAILURE_REASON_LACK_OF_RESOURCES = 0x4, 12829 }; 12830 12831 struct mlx5_ifc_msees_reg_bits { 12832 u8 reserved_at_0[0x8]; 12833 u8 local_port[0x8]; 12834 u8 pnat[0x2]; 12835 u8 lp_msb[0x2]; 12836 u8 reserved_at_14[0xc]; 12837 12838 u8 field_select[0x20]; 12839 12840 u8 admin_status[0x4]; 12841 u8 oper_status[0x4]; 12842 u8 ho_acq[0x1]; 12843 u8 reserved_at_49[0xc]; 12844 u8 admin_freq_measure[0x1]; 12845 u8 oper_freq_measure[0x1]; 12846 u8 failure_reason[0x9]; 12847 12848 u8 frequency_diff[0x20]; 12849 12850 u8 reserved_at_80[0x180]; 12851 }; 12852 12853 #endif /* MLX5_IFC_H */ 12854