1 /* 2 * Copyright (c) 2013-2015, Mellanox Technologies, Ltd. All rights reserved. 3 * 4 * This software is available to you under a choice of one of two 5 * licenses. You may choose to be licensed under the terms of the GNU 6 * General Public License (GPL) Version 2, available from the file 7 * COPYING in the main directory of this source tree, or the 8 * OpenIB.org BSD license below: 9 * 10 * Redistribution and use in source and binary forms, with or 11 * without modification, are permitted provided that the following 12 * conditions are met: 13 * 14 * - Redistributions of source code must retain the above 15 * copyright notice, this list of conditions and the following 16 * disclaimer. 17 * 18 * - Redistributions in binary form must reproduce the above 19 * copyright notice, this list of conditions and the following 20 * disclaimer in the documentation and/or other materials 21 * provided with the distribution. 22 * 23 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, 24 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF 25 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND 26 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS 27 * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN 28 * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN 29 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE 30 * SOFTWARE. 31 */ 32 #ifndef MLX5_IFC_H 33 #define MLX5_IFC_H 34 35 #include "mlx5_ifc_fpga.h" 36 37 enum { 38 MLX5_EVENT_TYPE_CODING_COMPLETION_EVENTS = 0x0, 39 MLX5_EVENT_TYPE_CODING_PATH_MIGRATED_SUCCEEDED = 0x1, 40 MLX5_EVENT_TYPE_CODING_COMMUNICATION_ESTABLISHED = 0x2, 41 MLX5_EVENT_TYPE_CODING_SEND_QUEUE_DRAINED = 0x3, 42 MLX5_EVENT_TYPE_CODING_LAST_WQE_REACHED = 0x13, 43 MLX5_EVENT_TYPE_CODING_SRQ_LIMIT = 0x14, 44 MLX5_EVENT_TYPE_CODING_DCT_ALL_CONNECTIONS_CLOSED = 0x1c, 45 MLX5_EVENT_TYPE_CODING_DCT_ACCESS_KEY_VIOLATION = 0x1d, 46 MLX5_EVENT_TYPE_CODING_CQ_ERROR = 0x4, 47 MLX5_EVENT_TYPE_CODING_LOCAL_WQ_CATASTROPHIC_ERROR = 0x5, 48 MLX5_EVENT_TYPE_CODING_PATH_MIGRATION_FAILED = 0x7, 49 MLX5_EVENT_TYPE_CODING_PAGE_FAULT_EVENT = 0xc, 50 MLX5_EVENT_TYPE_CODING_INVALID_REQUEST_LOCAL_WQ_ERROR = 0x10, 51 MLX5_EVENT_TYPE_CODING_LOCAL_ACCESS_VIOLATION_WQ_ERROR = 0x11, 52 MLX5_EVENT_TYPE_CODING_LOCAL_SRQ_CATASTROPHIC_ERROR = 0x12, 53 MLX5_EVENT_TYPE_CODING_INTERNAL_ERROR = 0x8, 54 MLX5_EVENT_TYPE_CODING_PORT_STATE_CHANGE = 0x9, 55 MLX5_EVENT_TYPE_CODING_GPIO_EVENT = 0x15, 56 MLX5_EVENT_TYPE_CODING_REMOTE_CONFIGURATION_PROTOCOL_EVENT = 0x19, 57 MLX5_EVENT_TYPE_CODING_DOORBELL_BLUEFLAME_CONGESTION_EVENT = 0x1a, 58 MLX5_EVENT_TYPE_CODING_STALL_VL_EVENT = 0x1b, 59 MLX5_EVENT_TYPE_CODING_DROPPED_PACKET_LOGGED_EVENT = 0x1f, 60 MLX5_EVENT_TYPE_CODING_COMMAND_INTERFACE_COMPLETION = 0xa, 61 MLX5_EVENT_TYPE_CODING_PAGE_REQUEST = 0xb, 62 MLX5_EVENT_TYPE_CODING_FPGA_ERROR = 0x20, 63 MLX5_EVENT_TYPE_CODING_FPGA_QP_ERROR = 0x21 64 }; 65 66 enum { 67 MLX5_SET_HCA_CAP_OP_MOD_GENERAL_DEVICE = 0x0, 68 MLX5_SET_HCA_CAP_OP_MOD_ETHERNET_OFFLOADS = 0x1, 69 MLX5_SET_HCA_CAP_OP_MOD_ODP = 0x2, 70 MLX5_SET_HCA_CAP_OP_MOD_ATOMIC = 0x3, 71 MLX5_SET_HCA_CAP_OP_MOD_ROCE = 0x4, 72 MLX5_SET_HCA_CAP_OP_MOD_IPSEC = 0x15, 73 MLX5_SET_HCA_CAP_OP_MOD_GENERAL_DEVICE2 = 0x20, 74 MLX5_SET_HCA_CAP_OP_MOD_PORT_SELECTION = 0x25, 75 }; 76 77 enum { 78 MLX5_SHARED_RESOURCE_UID = 0xffff, 79 }; 80 81 enum { 82 MLX5_OBJ_TYPE_SW_ICM = 0x0008, 83 MLX5_OBJ_TYPE_HEADER_MODIFY_ARGUMENT = 0x23, 84 }; 85 86 enum { 87 MLX5_GENERAL_OBJ_TYPES_CAP_SW_ICM = (1ULL << MLX5_OBJ_TYPE_SW_ICM), 88 MLX5_GENERAL_OBJ_TYPES_CAP_GENEVE_TLV_OPT = (1ULL << 11), 89 MLX5_GENERAL_OBJ_TYPES_CAP_VIRTIO_NET_Q = (1ULL << 13), 90 MLX5_GENERAL_OBJ_TYPES_CAP_HEADER_MODIFY_ARGUMENT = 91 (1ULL << MLX5_OBJ_TYPE_HEADER_MODIFY_ARGUMENT), 92 MLX5_GENERAL_OBJ_TYPES_CAP_MACSEC_OFFLOAD = (1ULL << 39), 93 }; 94 95 enum { 96 MLX5_OBJ_TYPE_GENEVE_TLV_OPT = 0x000b, 97 MLX5_OBJ_TYPE_VIRTIO_NET_Q = 0x000d, 98 MLX5_OBJ_TYPE_VIRTIO_Q_COUNTERS = 0x001c, 99 MLX5_OBJ_TYPE_MATCH_DEFINER = 0x0018, 100 MLX5_OBJ_TYPE_PAGE_TRACK = 0x46, 101 MLX5_OBJ_TYPE_MKEY = 0xff01, 102 MLX5_OBJ_TYPE_QP = 0xff02, 103 MLX5_OBJ_TYPE_PSV = 0xff03, 104 MLX5_OBJ_TYPE_RMP = 0xff04, 105 MLX5_OBJ_TYPE_XRC_SRQ = 0xff05, 106 MLX5_OBJ_TYPE_RQ = 0xff06, 107 MLX5_OBJ_TYPE_SQ = 0xff07, 108 MLX5_OBJ_TYPE_TIR = 0xff08, 109 MLX5_OBJ_TYPE_TIS = 0xff09, 110 MLX5_OBJ_TYPE_DCT = 0xff0a, 111 MLX5_OBJ_TYPE_XRQ = 0xff0b, 112 MLX5_OBJ_TYPE_RQT = 0xff0e, 113 MLX5_OBJ_TYPE_FLOW_COUNTER = 0xff0f, 114 MLX5_OBJ_TYPE_CQ = 0xff10, 115 }; 116 117 enum { 118 MLX5_CMD_OP_QUERY_HCA_CAP = 0x100, 119 MLX5_CMD_OP_QUERY_ADAPTER = 0x101, 120 MLX5_CMD_OP_INIT_HCA = 0x102, 121 MLX5_CMD_OP_TEARDOWN_HCA = 0x103, 122 MLX5_CMD_OP_ENABLE_HCA = 0x104, 123 MLX5_CMD_OP_DISABLE_HCA = 0x105, 124 MLX5_CMD_OP_QUERY_PAGES = 0x107, 125 MLX5_CMD_OP_MANAGE_PAGES = 0x108, 126 MLX5_CMD_OP_SET_HCA_CAP = 0x109, 127 MLX5_CMD_OP_QUERY_ISSI = 0x10a, 128 MLX5_CMD_OP_SET_ISSI = 0x10b, 129 MLX5_CMD_OP_SET_DRIVER_VERSION = 0x10d, 130 MLX5_CMD_OP_QUERY_SF_PARTITION = 0x111, 131 MLX5_CMD_OP_ALLOC_SF = 0x113, 132 MLX5_CMD_OP_DEALLOC_SF = 0x114, 133 MLX5_CMD_OP_SUSPEND_VHCA = 0x115, 134 MLX5_CMD_OP_RESUME_VHCA = 0x116, 135 MLX5_CMD_OP_QUERY_VHCA_MIGRATION_STATE = 0x117, 136 MLX5_CMD_OP_SAVE_VHCA_STATE = 0x118, 137 MLX5_CMD_OP_LOAD_VHCA_STATE = 0x119, 138 MLX5_CMD_OP_CREATE_MKEY = 0x200, 139 MLX5_CMD_OP_QUERY_MKEY = 0x201, 140 MLX5_CMD_OP_DESTROY_MKEY = 0x202, 141 MLX5_CMD_OP_QUERY_SPECIAL_CONTEXTS = 0x203, 142 MLX5_CMD_OP_PAGE_FAULT_RESUME = 0x204, 143 MLX5_CMD_OP_ALLOC_MEMIC = 0x205, 144 MLX5_CMD_OP_DEALLOC_MEMIC = 0x206, 145 MLX5_CMD_OP_MODIFY_MEMIC = 0x207, 146 MLX5_CMD_OP_CREATE_EQ = 0x301, 147 MLX5_CMD_OP_DESTROY_EQ = 0x302, 148 MLX5_CMD_OP_QUERY_EQ = 0x303, 149 MLX5_CMD_OP_GEN_EQE = 0x304, 150 MLX5_CMD_OP_CREATE_CQ = 0x400, 151 MLX5_CMD_OP_DESTROY_CQ = 0x401, 152 MLX5_CMD_OP_QUERY_CQ = 0x402, 153 MLX5_CMD_OP_MODIFY_CQ = 0x403, 154 MLX5_CMD_OP_CREATE_QP = 0x500, 155 MLX5_CMD_OP_DESTROY_QP = 0x501, 156 MLX5_CMD_OP_RST2INIT_QP = 0x502, 157 MLX5_CMD_OP_INIT2RTR_QP = 0x503, 158 MLX5_CMD_OP_RTR2RTS_QP = 0x504, 159 MLX5_CMD_OP_RTS2RTS_QP = 0x505, 160 MLX5_CMD_OP_SQERR2RTS_QP = 0x506, 161 MLX5_CMD_OP_2ERR_QP = 0x507, 162 MLX5_CMD_OP_2RST_QP = 0x50a, 163 MLX5_CMD_OP_QUERY_QP = 0x50b, 164 MLX5_CMD_OP_SQD_RTS_QP = 0x50c, 165 MLX5_CMD_OP_INIT2INIT_QP = 0x50e, 166 MLX5_CMD_OP_CREATE_PSV = 0x600, 167 MLX5_CMD_OP_DESTROY_PSV = 0x601, 168 MLX5_CMD_OP_CREATE_SRQ = 0x700, 169 MLX5_CMD_OP_DESTROY_SRQ = 0x701, 170 MLX5_CMD_OP_QUERY_SRQ = 0x702, 171 MLX5_CMD_OP_ARM_RQ = 0x703, 172 MLX5_CMD_OP_CREATE_XRC_SRQ = 0x705, 173 MLX5_CMD_OP_DESTROY_XRC_SRQ = 0x706, 174 MLX5_CMD_OP_QUERY_XRC_SRQ = 0x707, 175 MLX5_CMD_OP_ARM_XRC_SRQ = 0x708, 176 MLX5_CMD_OP_CREATE_DCT = 0x710, 177 MLX5_CMD_OP_DESTROY_DCT = 0x711, 178 MLX5_CMD_OP_DRAIN_DCT = 0x712, 179 MLX5_CMD_OP_QUERY_DCT = 0x713, 180 MLX5_CMD_OP_ARM_DCT_FOR_KEY_VIOLATION = 0x714, 181 MLX5_CMD_OP_CREATE_XRQ = 0x717, 182 MLX5_CMD_OP_DESTROY_XRQ = 0x718, 183 MLX5_CMD_OP_QUERY_XRQ = 0x719, 184 MLX5_CMD_OP_ARM_XRQ = 0x71a, 185 MLX5_CMD_OP_QUERY_XRQ_DC_PARAMS_ENTRY = 0x725, 186 MLX5_CMD_OP_SET_XRQ_DC_PARAMS_ENTRY = 0x726, 187 MLX5_CMD_OP_QUERY_XRQ_ERROR_PARAMS = 0x727, 188 MLX5_CMD_OP_RELEASE_XRQ_ERROR = 0x729, 189 MLX5_CMD_OP_MODIFY_XRQ = 0x72a, 190 MLX5_CMD_OP_QUERY_ESW_FUNCTIONS = 0x740, 191 MLX5_CMD_OP_QUERY_VPORT_STATE = 0x750, 192 MLX5_CMD_OP_MODIFY_VPORT_STATE = 0x751, 193 MLX5_CMD_OP_QUERY_ESW_VPORT_CONTEXT = 0x752, 194 MLX5_CMD_OP_MODIFY_ESW_VPORT_CONTEXT = 0x753, 195 MLX5_CMD_OP_QUERY_NIC_VPORT_CONTEXT = 0x754, 196 MLX5_CMD_OP_MODIFY_NIC_VPORT_CONTEXT = 0x755, 197 MLX5_CMD_OP_QUERY_ROCE_ADDRESS = 0x760, 198 MLX5_CMD_OP_SET_ROCE_ADDRESS = 0x761, 199 MLX5_CMD_OP_QUERY_HCA_VPORT_CONTEXT = 0x762, 200 MLX5_CMD_OP_MODIFY_HCA_VPORT_CONTEXT = 0x763, 201 MLX5_CMD_OP_QUERY_HCA_VPORT_GID = 0x764, 202 MLX5_CMD_OP_QUERY_HCA_VPORT_PKEY = 0x765, 203 MLX5_CMD_OP_QUERY_VNIC_ENV = 0x76f, 204 MLX5_CMD_OP_QUERY_VPORT_COUNTER = 0x770, 205 MLX5_CMD_OP_ALLOC_Q_COUNTER = 0x771, 206 MLX5_CMD_OP_DEALLOC_Q_COUNTER = 0x772, 207 MLX5_CMD_OP_QUERY_Q_COUNTER = 0x773, 208 MLX5_CMD_OP_SET_MONITOR_COUNTER = 0x774, 209 MLX5_CMD_OP_ARM_MONITOR_COUNTER = 0x775, 210 MLX5_CMD_OP_SET_PP_RATE_LIMIT = 0x780, 211 MLX5_CMD_OP_QUERY_RATE_LIMIT = 0x781, 212 MLX5_CMD_OP_CREATE_SCHEDULING_ELEMENT = 0x782, 213 MLX5_CMD_OP_DESTROY_SCHEDULING_ELEMENT = 0x783, 214 MLX5_CMD_OP_QUERY_SCHEDULING_ELEMENT = 0x784, 215 MLX5_CMD_OP_MODIFY_SCHEDULING_ELEMENT = 0x785, 216 MLX5_CMD_OP_CREATE_QOS_PARA_VPORT = 0x786, 217 MLX5_CMD_OP_DESTROY_QOS_PARA_VPORT = 0x787, 218 MLX5_CMD_OP_ALLOC_PD = 0x800, 219 MLX5_CMD_OP_DEALLOC_PD = 0x801, 220 MLX5_CMD_OP_ALLOC_UAR = 0x802, 221 MLX5_CMD_OP_DEALLOC_UAR = 0x803, 222 MLX5_CMD_OP_CONFIG_INT_MODERATION = 0x804, 223 MLX5_CMD_OP_ACCESS_REG = 0x805, 224 MLX5_CMD_OP_ATTACH_TO_MCG = 0x806, 225 MLX5_CMD_OP_DETACH_FROM_MCG = 0x807, 226 MLX5_CMD_OP_GET_DROPPED_PACKET_LOG = 0x80a, 227 MLX5_CMD_OP_MAD_IFC = 0x50d, 228 MLX5_CMD_OP_QUERY_MAD_DEMUX = 0x80b, 229 MLX5_CMD_OP_SET_MAD_DEMUX = 0x80c, 230 MLX5_CMD_OP_NOP = 0x80d, 231 MLX5_CMD_OP_ALLOC_XRCD = 0x80e, 232 MLX5_CMD_OP_DEALLOC_XRCD = 0x80f, 233 MLX5_CMD_OP_ALLOC_TRANSPORT_DOMAIN = 0x816, 234 MLX5_CMD_OP_DEALLOC_TRANSPORT_DOMAIN = 0x817, 235 MLX5_CMD_OP_QUERY_CONG_STATUS = 0x822, 236 MLX5_CMD_OP_MODIFY_CONG_STATUS = 0x823, 237 MLX5_CMD_OP_QUERY_CONG_PARAMS = 0x824, 238 MLX5_CMD_OP_MODIFY_CONG_PARAMS = 0x825, 239 MLX5_CMD_OP_QUERY_CONG_STATISTICS = 0x826, 240 MLX5_CMD_OP_ADD_VXLAN_UDP_DPORT = 0x827, 241 MLX5_CMD_OP_DELETE_VXLAN_UDP_DPORT = 0x828, 242 MLX5_CMD_OP_SET_L2_TABLE_ENTRY = 0x829, 243 MLX5_CMD_OP_QUERY_L2_TABLE_ENTRY = 0x82a, 244 MLX5_CMD_OP_DELETE_L2_TABLE_ENTRY = 0x82b, 245 MLX5_CMD_OP_SET_WOL_ROL = 0x830, 246 MLX5_CMD_OP_QUERY_WOL_ROL = 0x831, 247 MLX5_CMD_OP_CREATE_LAG = 0x840, 248 MLX5_CMD_OP_MODIFY_LAG = 0x841, 249 MLX5_CMD_OP_QUERY_LAG = 0x842, 250 MLX5_CMD_OP_DESTROY_LAG = 0x843, 251 MLX5_CMD_OP_CREATE_VPORT_LAG = 0x844, 252 MLX5_CMD_OP_DESTROY_VPORT_LAG = 0x845, 253 MLX5_CMD_OP_CREATE_TIR = 0x900, 254 MLX5_CMD_OP_MODIFY_TIR = 0x901, 255 MLX5_CMD_OP_DESTROY_TIR = 0x902, 256 MLX5_CMD_OP_QUERY_TIR = 0x903, 257 MLX5_CMD_OP_CREATE_SQ = 0x904, 258 MLX5_CMD_OP_MODIFY_SQ = 0x905, 259 MLX5_CMD_OP_DESTROY_SQ = 0x906, 260 MLX5_CMD_OP_QUERY_SQ = 0x907, 261 MLX5_CMD_OP_CREATE_RQ = 0x908, 262 MLX5_CMD_OP_MODIFY_RQ = 0x909, 263 MLX5_CMD_OP_SET_DELAY_DROP_PARAMS = 0x910, 264 MLX5_CMD_OP_DESTROY_RQ = 0x90a, 265 MLX5_CMD_OP_QUERY_RQ = 0x90b, 266 MLX5_CMD_OP_CREATE_RMP = 0x90c, 267 MLX5_CMD_OP_MODIFY_RMP = 0x90d, 268 MLX5_CMD_OP_DESTROY_RMP = 0x90e, 269 MLX5_CMD_OP_QUERY_RMP = 0x90f, 270 MLX5_CMD_OP_CREATE_TIS = 0x912, 271 MLX5_CMD_OP_MODIFY_TIS = 0x913, 272 MLX5_CMD_OP_DESTROY_TIS = 0x914, 273 MLX5_CMD_OP_QUERY_TIS = 0x915, 274 MLX5_CMD_OP_CREATE_RQT = 0x916, 275 MLX5_CMD_OP_MODIFY_RQT = 0x917, 276 MLX5_CMD_OP_DESTROY_RQT = 0x918, 277 MLX5_CMD_OP_QUERY_RQT = 0x919, 278 MLX5_CMD_OP_SET_FLOW_TABLE_ROOT = 0x92f, 279 MLX5_CMD_OP_CREATE_FLOW_TABLE = 0x930, 280 MLX5_CMD_OP_DESTROY_FLOW_TABLE = 0x931, 281 MLX5_CMD_OP_QUERY_FLOW_TABLE = 0x932, 282 MLX5_CMD_OP_CREATE_FLOW_GROUP = 0x933, 283 MLX5_CMD_OP_DESTROY_FLOW_GROUP = 0x934, 284 MLX5_CMD_OP_QUERY_FLOW_GROUP = 0x935, 285 MLX5_CMD_OP_SET_FLOW_TABLE_ENTRY = 0x936, 286 MLX5_CMD_OP_QUERY_FLOW_TABLE_ENTRY = 0x937, 287 MLX5_CMD_OP_DELETE_FLOW_TABLE_ENTRY = 0x938, 288 MLX5_CMD_OP_ALLOC_FLOW_COUNTER = 0x939, 289 MLX5_CMD_OP_DEALLOC_FLOW_COUNTER = 0x93a, 290 MLX5_CMD_OP_QUERY_FLOW_COUNTER = 0x93b, 291 MLX5_CMD_OP_MODIFY_FLOW_TABLE = 0x93c, 292 MLX5_CMD_OP_ALLOC_PACKET_REFORMAT_CONTEXT = 0x93d, 293 MLX5_CMD_OP_DEALLOC_PACKET_REFORMAT_CONTEXT = 0x93e, 294 MLX5_CMD_OP_QUERY_PACKET_REFORMAT_CONTEXT = 0x93f, 295 MLX5_CMD_OP_ALLOC_MODIFY_HEADER_CONTEXT = 0x940, 296 MLX5_CMD_OP_DEALLOC_MODIFY_HEADER_CONTEXT = 0x941, 297 MLX5_CMD_OP_QUERY_MODIFY_HEADER_CONTEXT = 0x942, 298 MLX5_CMD_OP_FPGA_CREATE_QP = 0x960, 299 MLX5_CMD_OP_FPGA_MODIFY_QP = 0x961, 300 MLX5_CMD_OP_FPGA_QUERY_QP = 0x962, 301 MLX5_CMD_OP_FPGA_DESTROY_QP = 0x963, 302 MLX5_CMD_OP_FPGA_QUERY_QP_COUNTERS = 0x964, 303 MLX5_CMD_OP_CREATE_GENERAL_OBJECT = 0xa00, 304 MLX5_CMD_OP_MODIFY_GENERAL_OBJECT = 0xa01, 305 MLX5_CMD_OP_QUERY_GENERAL_OBJECT = 0xa02, 306 MLX5_CMD_OP_DESTROY_GENERAL_OBJECT = 0xa03, 307 MLX5_CMD_OP_CREATE_UCTX = 0xa04, 308 MLX5_CMD_OP_DESTROY_UCTX = 0xa06, 309 MLX5_CMD_OP_CREATE_UMEM = 0xa08, 310 MLX5_CMD_OP_DESTROY_UMEM = 0xa0a, 311 MLX5_CMD_OP_SYNC_STEERING = 0xb00, 312 MLX5_CMD_OP_QUERY_VHCA_STATE = 0xb0d, 313 MLX5_CMD_OP_MODIFY_VHCA_STATE = 0xb0e, 314 MLX5_CMD_OP_SYNC_CRYPTO = 0xb12, 315 MLX5_CMD_OP_ALLOW_OTHER_VHCA_ACCESS = 0xb16, 316 MLX5_CMD_OP_MAX 317 }; 318 319 /* Valid range for general commands that don't work over an object */ 320 enum { 321 MLX5_CMD_OP_GENERAL_START = 0xb00, 322 MLX5_CMD_OP_GENERAL_END = 0xd00, 323 }; 324 325 enum { 326 MLX5_FT_NIC_RX_2_NIC_RX_RDMA = BIT(0), 327 MLX5_FT_NIC_TX_RDMA_2_NIC_TX = BIT(1), 328 }; 329 330 enum { 331 MLX5_CMD_OP_MOD_UPDATE_HEADER_MODIFY_ARGUMENT = 0x1, 332 }; 333 334 struct mlx5_ifc_flow_table_fields_supported_bits { 335 u8 outer_dmac[0x1]; 336 u8 outer_smac[0x1]; 337 u8 outer_ether_type[0x1]; 338 u8 outer_ip_version[0x1]; 339 u8 outer_first_prio[0x1]; 340 u8 outer_first_cfi[0x1]; 341 u8 outer_first_vid[0x1]; 342 u8 outer_ipv4_ttl[0x1]; 343 u8 outer_second_prio[0x1]; 344 u8 outer_second_cfi[0x1]; 345 u8 outer_second_vid[0x1]; 346 u8 reserved_at_b[0x1]; 347 u8 outer_sip[0x1]; 348 u8 outer_dip[0x1]; 349 u8 outer_frag[0x1]; 350 u8 outer_ip_protocol[0x1]; 351 u8 outer_ip_ecn[0x1]; 352 u8 outer_ip_dscp[0x1]; 353 u8 outer_udp_sport[0x1]; 354 u8 outer_udp_dport[0x1]; 355 u8 outer_tcp_sport[0x1]; 356 u8 outer_tcp_dport[0x1]; 357 u8 outer_tcp_flags[0x1]; 358 u8 outer_gre_protocol[0x1]; 359 u8 outer_gre_key[0x1]; 360 u8 outer_vxlan_vni[0x1]; 361 u8 outer_geneve_vni[0x1]; 362 u8 outer_geneve_oam[0x1]; 363 u8 outer_geneve_protocol_type[0x1]; 364 u8 outer_geneve_opt_len[0x1]; 365 u8 source_vhca_port[0x1]; 366 u8 source_eswitch_port[0x1]; 367 368 u8 inner_dmac[0x1]; 369 u8 inner_smac[0x1]; 370 u8 inner_ether_type[0x1]; 371 u8 inner_ip_version[0x1]; 372 u8 inner_first_prio[0x1]; 373 u8 inner_first_cfi[0x1]; 374 u8 inner_first_vid[0x1]; 375 u8 reserved_at_27[0x1]; 376 u8 inner_second_prio[0x1]; 377 u8 inner_second_cfi[0x1]; 378 u8 inner_second_vid[0x1]; 379 u8 reserved_at_2b[0x1]; 380 u8 inner_sip[0x1]; 381 u8 inner_dip[0x1]; 382 u8 inner_frag[0x1]; 383 u8 inner_ip_protocol[0x1]; 384 u8 inner_ip_ecn[0x1]; 385 u8 inner_ip_dscp[0x1]; 386 u8 inner_udp_sport[0x1]; 387 u8 inner_udp_dport[0x1]; 388 u8 inner_tcp_sport[0x1]; 389 u8 inner_tcp_dport[0x1]; 390 u8 inner_tcp_flags[0x1]; 391 u8 reserved_at_37[0x9]; 392 393 u8 geneve_tlv_option_0_data[0x1]; 394 u8 geneve_tlv_option_0_exist[0x1]; 395 u8 reserved_at_42[0x3]; 396 u8 outer_first_mpls_over_udp[0x4]; 397 u8 outer_first_mpls_over_gre[0x4]; 398 u8 inner_first_mpls[0x4]; 399 u8 outer_first_mpls[0x4]; 400 u8 reserved_at_55[0x2]; 401 u8 outer_esp_spi[0x1]; 402 u8 reserved_at_58[0x2]; 403 u8 bth_dst_qp[0x1]; 404 u8 reserved_at_5b[0x5]; 405 406 u8 reserved_at_60[0x18]; 407 u8 metadata_reg_c_7[0x1]; 408 u8 metadata_reg_c_6[0x1]; 409 u8 metadata_reg_c_5[0x1]; 410 u8 metadata_reg_c_4[0x1]; 411 u8 metadata_reg_c_3[0x1]; 412 u8 metadata_reg_c_2[0x1]; 413 u8 metadata_reg_c_1[0x1]; 414 u8 metadata_reg_c_0[0x1]; 415 }; 416 417 /* Table 2170 - Flow Table Fields Supported 2 Format */ 418 struct mlx5_ifc_flow_table_fields_supported_2_bits { 419 u8 reserved_at_0[0x2]; 420 u8 inner_l4_type[0x1]; 421 u8 outer_l4_type[0x1]; 422 u8 reserved_at_4[0xa]; 423 u8 bth_opcode[0x1]; 424 u8 reserved_at_f[0x1]; 425 u8 tunnel_header_0_1[0x1]; 426 u8 reserved_at_11[0xf]; 427 428 u8 reserved_at_20[0x60]; 429 }; 430 431 struct mlx5_ifc_flow_table_prop_layout_bits { 432 u8 ft_support[0x1]; 433 u8 reserved_at_1[0x1]; 434 u8 flow_counter[0x1]; 435 u8 flow_modify_en[0x1]; 436 u8 modify_root[0x1]; 437 u8 identified_miss_table_mode[0x1]; 438 u8 flow_table_modify[0x1]; 439 u8 reformat[0x1]; 440 u8 decap[0x1]; 441 u8 reset_root_to_default[0x1]; 442 u8 pop_vlan[0x1]; 443 u8 push_vlan[0x1]; 444 u8 reserved_at_c[0x1]; 445 u8 pop_vlan_2[0x1]; 446 u8 push_vlan_2[0x1]; 447 u8 reformat_and_vlan_action[0x1]; 448 u8 reserved_at_10[0x1]; 449 u8 sw_owner[0x1]; 450 u8 reformat_l3_tunnel_to_l2[0x1]; 451 u8 reformat_l2_to_l3_tunnel[0x1]; 452 u8 reformat_and_modify_action[0x1]; 453 u8 ignore_flow_level[0x1]; 454 u8 reserved_at_16[0x1]; 455 u8 table_miss_action_domain[0x1]; 456 u8 termination_table[0x1]; 457 u8 reformat_and_fwd_to_table[0x1]; 458 u8 reserved_at_1a[0x2]; 459 u8 ipsec_encrypt[0x1]; 460 u8 ipsec_decrypt[0x1]; 461 u8 sw_owner_v2[0x1]; 462 u8 reserved_at_1f[0x1]; 463 464 u8 termination_table_raw_traffic[0x1]; 465 u8 reserved_at_21[0x1]; 466 u8 log_max_ft_size[0x6]; 467 u8 log_max_modify_header_context[0x8]; 468 u8 max_modify_header_actions[0x8]; 469 u8 max_ft_level[0x8]; 470 471 u8 reformat_add_esp_trasport[0x1]; 472 u8 reformat_l2_to_l3_esp_tunnel[0x1]; 473 u8 reformat_add_esp_transport_over_udp[0x1]; 474 u8 reformat_del_esp_trasport[0x1]; 475 u8 reformat_l3_esp_tunnel_to_l2[0x1]; 476 u8 reformat_del_esp_transport_over_udp[0x1]; 477 u8 execute_aso[0x1]; 478 u8 reserved_at_47[0x19]; 479 480 u8 reserved_at_60[0x2]; 481 u8 reformat_insert[0x1]; 482 u8 reformat_remove[0x1]; 483 u8 macsec_encrypt[0x1]; 484 u8 macsec_decrypt[0x1]; 485 u8 reserved_at_66[0x2]; 486 u8 reformat_add_macsec[0x1]; 487 u8 reformat_remove_macsec[0x1]; 488 u8 reserved_at_6a[0xe]; 489 u8 log_max_ft_num[0x8]; 490 491 u8 reserved_at_80[0x10]; 492 u8 log_max_flow_counter[0x8]; 493 u8 log_max_destination[0x8]; 494 495 u8 reserved_at_a0[0x18]; 496 u8 log_max_flow[0x8]; 497 498 u8 reserved_at_c0[0x40]; 499 500 struct mlx5_ifc_flow_table_fields_supported_bits ft_field_support; 501 502 struct mlx5_ifc_flow_table_fields_supported_bits ft_field_bitmask_support; 503 }; 504 505 struct mlx5_ifc_odp_per_transport_service_cap_bits { 506 u8 send[0x1]; 507 u8 receive[0x1]; 508 u8 write[0x1]; 509 u8 read[0x1]; 510 u8 atomic[0x1]; 511 u8 srq_receive[0x1]; 512 u8 reserved_at_6[0x1a]; 513 }; 514 515 struct mlx5_ifc_ipv4_layout_bits { 516 u8 reserved_at_0[0x60]; 517 518 u8 ipv4[0x20]; 519 }; 520 521 struct mlx5_ifc_ipv6_layout_bits { 522 u8 ipv6[16][0x8]; 523 }; 524 525 union mlx5_ifc_ipv6_layout_ipv4_layout_auto_bits { 526 struct mlx5_ifc_ipv6_layout_bits ipv6_layout; 527 struct mlx5_ifc_ipv4_layout_bits ipv4_layout; 528 u8 reserved_at_0[0x80]; 529 }; 530 531 enum { 532 MLX5_PACKET_L4_TYPE_NONE, 533 MLX5_PACKET_L4_TYPE_TCP, 534 MLX5_PACKET_L4_TYPE_UDP, 535 }; 536 537 struct mlx5_ifc_fte_match_set_lyr_2_4_bits { 538 u8 smac_47_16[0x20]; 539 540 u8 smac_15_0[0x10]; 541 u8 ethertype[0x10]; 542 543 u8 dmac_47_16[0x20]; 544 545 u8 dmac_15_0[0x10]; 546 u8 first_prio[0x3]; 547 u8 first_cfi[0x1]; 548 u8 first_vid[0xc]; 549 550 u8 ip_protocol[0x8]; 551 u8 ip_dscp[0x6]; 552 u8 ip_ecn[0x2]; 553 u8 cvlan_tag[0x1]; 554 u8 svlan_tag[0x1]; 555 u8 frag[0x1]; 556 u8 ip_version[0x4]; 557 u8 tcp_flags[0x9]; 558 559 u8 tcp_sport[0x10]; 560 u8 tcp_dport[0x10]; 561 562 u8 l4_type[0x2]; 563 u8 reserved_at_c2[0xe]; 564 u8 ipv4_ihl[0x4]; 565 u8 reserved_at_c4[0x4]; 566 567 u8 ttl_hoplimit[0x8]; 568 569 u8 udp_sport[0x10]; 570 u8 udp_dport[0x10]; 571 572 union mlx5_ifc_ipv6_layout_ipv4_layout_auto_bits src_ipv4_src_ipv6; 573 574 union mlx5_ifc_ipv6_layout_ipv4_layout_auto_bits dst_ipv4_dst_ipv6; 575 }; 576 577 struct mlx5_ifc_nvgre_key_bits { 578 u8 hi[0x18]; 579 u8 lo[0x8]; 580 }; 581 582 union mlx5_ifc_gre_key_bits { 583 struct mlx5_ifc_nvgre_key_bits nvgre; 584 u8 key[0x20]; 585 }; 586 587 struct mlx5_ifc_fte_match_set_misc_bits { 588 u8 gre_c_present[0x1]; 589 u8 reserved_at_1[0x1]; 590 u8 gre_k_present[0x1]; 591 u8 gre_s_present[0x1]; 592 u8 source_vhca_port[0x4]; 593 u8 source_sqn[0x18]; 594 595 u8 source_eswitch_owner_vhca_id[0x10]; 596 u8 source_port[0x10]; 597 598 u8 outer_second_prio[0x3]; 599 u8 outer_second_cfi[0x1]; 600 u8 outer_second_vid[0xc]; 601 u8 inner_second_prio[0x3]; 602 u8 inner_second_cfi[0x1]; 603 u8 inner_second_vid[0xc]; 604 605 u8 outer_second_cvlan_tag[0x1]; 606 u8 inner_second_cvlan_tag[0x1]; 607 u8 outer_second_svlan_tag[0x1]; 608 u8 inner_second_svlan_tag[0x1]; 609 u8 reserved_at_64[0xc]; 610 u8 gre_protocol[0x10]; 611 612 union mlx5_ifc_gre_key_bits gre_key; 613 614 u8 vxlan_vni[0x18]; 615 u8 bth_opcode[0x8]; 616 617 u8 geneve_vni[0x18]; 618 u8 reserved_at_d8[0x6]; 619 u8 geneve_tlv_option_0_exist[0x1]; 620 u8 geneve_oam[0x1]; 621 622 u8 reserved_at_e0[0xc]; 623 u8 outer_ipv6_flow_label[0x14]; 624 625 u8 reserved_at_100[0xc]; 626 u8 inner_ipv6_flow_label[0x14]; 627 628 u8 reserved_at_120[0xa]; 629 u8 geneve_opt_len[0x6]; 630 u8 geneve_protocol_type[0x10]; 631 632 u8 reserved_at_140[0x8]; 633 u8 bth_dst_qp[0x18]; 634 u8 inner_esp_spi[0x20]; 635 u8 outer_esp_spi[0x20]; 636 u8 reserved_at_1a0[0x60]; 637 }; 638 639 struct mlx5_ifc_fte_match_mpls_bits { 640 u8 mpls_label[0x14]; 641 u8 mpls_exp[0x3]; 642 u8 mpls_s_bos[0x1]; 643 u8 mpls_ttl[0x8]; 644 }; 645 646 struct mlx5_ifc_fte_match_set_misc2_bits { 647 struct mlx5_ifc_fte_match_mpls_bits outer_first_mpls; 648 649 struct mlx5_ifc_fte_match_mpls_bits inner_first_mpls; 650 651 struct mlx5_ifc_fte_match_mpls_bits outer_first_mpls_over_gre; 652 653 struct mlx5_ifc_fte_match_mpls_bits outer_first_mpls_over_udp; 654 655 u8 metadata_reg_c_7[0x20]; 656 657 u8 metadata_reg_c_6[0x20]; 658 659 u8 metadata_reg_c_5[0x20]; 660 661 u8 metadata_reg_c_4[0x20]; 662 663 u8 metadata_reg_c_3[0x20]; 664 665 u8 metadata_reg_c_2[0x20]; 666 667 u8 metadata_reg_c_1[0x20]; 668 669 u8 metadata_reg_c_0[0x20]; 670 671 u8 metadata_reg_a[0x20]; 672 673 u8 reserved_at_1a0[0x8]; 674 675 u8 macsec_syndrome[0x8]; 676 u8 ipsec_syndrome[0x8]; 677 u8 reserved_at_1b8[0x8]; 678 679 u8 reserved_at_1c0[0x40]; 680 }; 681 682 struct mlx5_ifc_fte_match_set_misc3_bits { 683 u8 inner_tcp_seq_num[0x20]; 684 685 u8 outer_tcp_seq_num[0x20]; 686 687 u8 inner_tcp_ack_num[0x20]; 688 689 u8 outer_tcp_ack_num[0x20]; 690 691 u8 reserved_at_80[0x8]; 692 u8 outer_vxlan_gpe_vni[0x18]; 693 694 u8 outer_vxlan_gpe_next_protocol[0x8]; 695 u8 outer_vxlan_gpe_flags[0x8]; 696 u8 reserved_at_b0[0x10]; 697 698 u8 icmp_header_data[0x20]; 699 700 u8 icmpv6_header_data[0x20]; 701 702 u8 icmp_type[0x8]; 703 u8 icmp_code[0x8]; 704 u8 icmpv6_type[0x8]; 705 u8 icmpv6_code[0x8]; 706 707 u8 geneve_tlv_option_0_data[0x20]; 708 709 u8 gtpu_teid[0x20]; 710 711 u8 gtpu_msg_type[0x8]; 712 u8 gtpu_msg_flags[0x8]; 713 u8 reserved_at_170[0x10]; 714 715 u8 gtpu_dw_2[0x20]; 716 717 u8 gtpu_first_ext_dw_0[0x20]; 718 719 u8 gtpu_dw_0[0x20]; 720 721 u8 reserved_at_1e0[0x20]; 722 }; 723 724 struct mlx5_ifc_fte_match_set_misc4_bits { 725 u8 prog_sample_field_value_0[0x20]; 726 727 u8 prog_sample_field_id_0[0x20]; 728 729 u8 prog_sample_field_value_1[0x20]; 730 731 u8 prog_sample_field_id_1[0x20]; 732 733 u8 prog_sample_field_value_2[0x20]; 734 735 u8 prog_sample_field_id_2[0x20]; 736 737 u8 prog_sample_field_value_3[0x20]; 738 739 u8 prog_sample_field_id_3[0x20]; 740 741 u8 reserved_at_100[0x100]; 742 }; 743 744 struct mlx5_ifc_fte_match_set_misc5_bits { 745 u8 macsec_tag_0[0x20]; 746 747 u8 macsec_tag_1[0x20]; 748 749 u8 macsec_tag_2[0x20]; 750 751 u8 macsec_tag_3[0x20]; 752 753 u8 tunnel_header_0[0x20]; 754 755 u8 tunnel_header_1[0x20]; 756 757 u8 tunnel_header_2[0x20]; 758 759 u8 tunnel_header_3[0x20]; 760 761 u8 reserved_at_100[0x100]; 762 }; 763 764 struct mlx5_ifc_cmd_pas_bits { 765 u8 pa_h[0x20]; 766 767 u8 pa_l[0x14]; 768 u8 reserved_at_34[0xc]; 769 }; 770 771 struct mlx5_ifc_uint64_bits { 772 u8 hi[0x20]; 773 774 u8 lo[0x20]; 775 }; 776 777 enum { 778 MLX5_ADS_STAT_RATE_NO_LIMIT = 0x0, 779 MLX5_ADS_STAT_RATE_2_5GBPS = 0x7, 780 MLX5_ADS_STAT_RATE_10GBPS = 0x8, 781 MLX5_ADS_STAT_RATE_30GBPS = 0x9, 782 MLX5_ADS_STAT_RATE_5GBPS = 0xa, 783 MLX5_ADS_STAT_RATE_20GBPS = 0xb, 784 MLX5_ADS_STAT_RATE_40GBPS = 0xc, 785 MLX5_ADS_STAT_RATE_60GBPS = 0xd, 786 MLX5_ADS_STAT_RATE_80GBPS = 0xe, 787 MLX5_ADS_STAT_RATE_120GBPS = 0xf, 788 }; 789 790 struct mlx5_ifc_ads_bits { 791 u8 fl[0x1]; 792 u8 free_ar[0x1]; 793 u8 reserved_at_2[0xe]; 794 u8 pkey_index[0x10]; 795 796 u8 reserved_at_20[0x8]; 797 u8 grh[0x1]; 798 u8 mlid[0x7]; 799 u8 rlid[0x10]; 800 801 u8 ack_timeout[0x5]; 802 u8 reserved_at_45[0x3]; 803 u8 src_addr_index[0x8]; 804 u8 reserved_at_50[0x4]; 805 u8 stat_rate[0x4]; 806 u8 hop_limit[0x8]; 807 808 u8 reserved_at_60[0x4]; 809 u8 tclass[0x8]; 810 u8 flow_label[0x14]; 811 812 u8 rgid_rip[16][0x8]; 813 814 u8 reserved_at_100[0x4]; 815 u8 f_dscp[0x1]; 816 u8 f_ecn[0x1]; 817 u8 reserved_at_106[0x1]; 818 u8 f_eth_prio[0x1]; 819 u8 ecn[0x2]; 820 u8 dscp[0x6]; 821 u8 udp_sport[0x10]; 822 823 u8 dei_cfi[0x1]; 824 u8 eth_prio[0x3]; 825 u8 sl[0x4]; 826 u8 vhca_port_num[0x8]; 827 u8 rmac_47_32[0x10]; 828 829 u8 rmac_31_0[0x20]; 830 }; 831 832 struct mlx5_ifc_flow_table_nic_cap_bits { 833 u8 nic_rx_multi_path_tirs[0x1]; 834 u8 nic_rx_multi_path_tirs_fts[0x1]; 835 u8 allow_sniffer_and_nic_rx_shared_tir[0x1]; 836 u8 reserved_at_3[0x4]; 837 u8 sw_owner_reformat_supported[0x1]; 838 u8 reserved_at_8[0x18]; 839 840 u8 encap_general_header[0x1]; 841 u8 reserved_at_21[0xa]; 842 u8 log_max_packet_reformat_context[0x5]; 843 u8 reserved_at_30[0x6]; 844 u8 max_encap_header_size[0xa]; 845 u8 reserved_at_40[0x1c0]; 846 847 struct mlx5_ifc_flow_table_prop_layout_bits flow_table_properties_nic_receive; 848 849 struct mlx5_ifc_flow_table_prop_layout_bits flow_table_properties_nic_receive_rdma; 850 851 struct mlx5_ifc_flow_table_prop_layout_bits flow_table_properties_nic_receive_sniffer; 852 853 struct mlx5_ifc_flow_table_prop_layout_bits flow_table_properties_nic_transmit; 854 855 struct mlx5_ifc_flow_table_prop_layout_bits flow_table_properties_nic_transmit_rdma; 856 857 struct mlx5_ifc_flow_table_prop_layout_bits flow_table_properties_nic_transmit_sniffer; 858 859 u8 reserved_at_e00[0x600]; 860 861 struct mlx5_ifc_flow_table_fields_supported_2_bits ft_field_support_2_nic_receive; 862 863 u8 reserved_at_1480[0x80]; 864 865 struct mlx5_ifc_flow_table_fields_supported_2_bits ft_field_support_2_nic_receive_rdma; 866 867 u8 reserved_at_1580[0x280]; 868 869 struct mlx5_ifc_flow_table_fields_supported_2_bits ft_field_support_2_nic_transmit_rdma; 870 871 u8 reserved_at_1880[0x780]; 872 873 u8 sw_steering_nic_rx_action_drop_icm_address[0x40]; 874 875 u8 sw_steering_nic_tx_action_drop_icm_address[0x40]; 876 877 u8 sw_steering_nic_tx_action_allow_icm_address[0x40]; 878 879 u8 reserved_at_20c0[0x5f40]; 880 }; 881 882 struct mlx5_ifc_port_selection_cap_bits { 883 u8 reserved_at_0[0x10]; 884 u8 port_select_flow_table[0x1]; 885 u8 reserved_at_11[0x1]; 886 u8 port_select_flow_table_bypass[0x1]; 887 u8 reserved_at_13[0xd]; 888 889 u8 reserved_at_20[0x1e0]; 890 891 struct mlx5_ifc_flow_table_prop_layout_bits flow_table_properties_port_selection; 892 893 struct mlx5_ifc_flow_table_fields_supported_2_bits ft_field_support_2_port_selection; 894 895 u8 reserved_at_480[0x7b80]; 896 }; 897 898 enum { 899 MLX5_FDB_TO_VPORT_REG_C_0 = 0x01, 900 MLX5_FDB_TO_VPORT_REG_C_1 = 0x02, 901 MLX5_FDB_TO_VPORT_REG_C_2 = 0x04, 902 MLX5_FDB_TO_VPORT_REG_C_3 = 0x08, 903 MLX5_FDB_TO_VPORT_REG_C_4 = 0x10, 904 MLX5_FDB_TO_VPORT_REG_C_5 = 0x20, 905 MLX5_FDB_TO_VPORT_REG_C_6 = 0x40, 906 MLX5_FDB_TO_VPORT_REG_C_7 = 0x80, 907 }; 908 909 struct mlx5_ifc_flow_table_eswitch_cap_bits { 910 u8 fdb_to_vport_reg_c_id[0x8]; 911 u8 reserved_at_8[0x5]; 912 u8 fdb_uplink_hairpin[0x1]; 913 u8 fdb_multi_path_any_table_limit_regc[0x1]; 914 u8 reserved_at_f[0x3]; 915 u8 fdb_multi_path_any_table[0x1]; 916 u8 reserved_at_13[0x2]; 917 u8 fdb_modify_header_fwd_to_table[0x1]; 918 u8 fdb_ipv4_ttl_modify[0x1]; 919 u8 flow_source[0x1]; 920 u8 reserved_at_18[0x2]; 921 u8 multi_fdb_encap[0x1]; 922 u8 egress_acl_forward_to_vport[0x1]; 923 u8 fdb_multi_path_to_table[0x1]; 924 u8 reserved_at_1d[0x3]; 925 926 u8 reserved_at_20[0x1e0]; 927 928 struct mlx5_ifc_flow_table_prop_layout_bits flow_table_properties_nic_esw_fdb; 929 930 struct mlx5_ifc_flow_table_prop_layout_bits flow_table_properties_esw_acl_ingress; 931 932 struct mlx5_ifc_flow_table_prop_layout_bits flow_table_properties_esw_acl_egress; 933 934 u8 reserved_at_800[0xC00]; 935 936 struct mlx5_ifc_flow_table_fields_supported_2_bits ft_field_support_2_esw_fdb; 937 938 struct mlx5_ifc_flow_table_fields_supported_2_bits ft_field_bitmask_support_2_esw_fdb; 939 940 u8 reserved_at_1500[0x300]; 941 942 u8 sw_steering_fdb_action_drop_icm_address_rx[0x40]; 943 944 u8 sw_steering_fdb_action_drop_icm_address_tx[0x40]; 945 946 u8 sw_steering_uplink_icm_address_rx[0x40]; 947 948 u8 sw_steering_uplink_icm_address_tx[0x40]; 949 950 u8 reserved_at_1900[0x6700]; 951 }; 952 953 enum { 954 MLX5_COUNTER_SOURCE_ESWITCH = 0x0, 955 MLX5_COUNTER_FLOW_ESWITCH = 0x1, 956 }; 957 958 struct mlx5_ifc_e_switch_cap_bits { 959 u8 vport_svlan_strip[0x1]; 960 u8 vport_cvlan_strip[0x1]; 961 u8 vport_svlan_insert[0x1]; 962 u8 vport_cvlan_insert_if_not_exist[0x1]; 963 u8 vport_cvlan_insert_overwrite[0x1]; 964 u8 reserved_at_5[0x1]; 965 u8 vport_cvlan_insert_always[0x1]; 966 u8 esw_shared_ingress_acl[0x1]; 967 u8 esw_uplink_ingress_acl[0x1]; 968 u8 root_ft_on_other_esw[0x1]; 969 u8 reserved_at_a[0xf]; 970 u8 esw_functions_changed[0x1]; 971 u8 reserved_at_1a[0x1]; 972 u8 ecpf_vport_exists[0x1]; 973 u8 counter_eswitch_affinity[0x1]; 974 u8 merged_eswitch[0x1]; 975 u8 nic_vport_node_guid_modify[0x1]; 976 u8 nic_vport_port_guid_modify[0x1]; 977 978 u8 vxlan_encap_decap[0x1]; 979 u8 nvgre_encap_decap[0x1]; 980 u8 reserved_at_22[0x1]; 981 u8 log_max_fdb_encap_uplink[0x5]; 982 u8 reserved_at_21[0x3]; 983 u8 log_max_packet_reformat_context[0x5]; 984 u8 reserved_2b[0x6]; 985 u8 max_encap_header_size[0xa]; 986 987 u8 reserved_at_40[0xb]; 988 u8 log_max_esw_sf[0x5]; 989 u8 esw_sf_base_id[0x10]; 990 991 u8 reserved_at_60[0x7a0]; 992 993 }; 994 995 struct mlx5_ifc_qos_cap_bits { 996 u8 packet_pacing[0x1]; 997 u8 esw_scheduling[0x1]; 998 u8 esw_bw_share[0x1]; 999 u8 esw_rate_limit[0x1]; 1000 u8 reserved_at_4[0x1]; 1001 u8 packet_pacing_burst_bound[0x1]; 1002 u8 packet_pacing_typical_size[0x1]; 1003 u8 reserved_at_7[0x1]; 1004 u8 nic_sq_scheduling[0x1]; 1005 u8 nic_bw_share[0x1]; 1006 u8 nic_rate_limit[0x1]; 1007 u8 packet_pacing_uid[0x1]; 1008 u8 log_esw_max_sched_depth[0x4]; 1009 u8 reserved_at_10[0x10]; 1010 1011 u8 reserved_at_20[0xb]; 1012 u8 log_max_qos_nic_queue_group[0x5]; 1013 u8 reserved_at_30[0x10]; 1014 1015 u8 packet_pacing_max_rate[0x20]; 1016 1017 u8 packet_pacing_min_rate[0x20]; 1018 1019 u8 reserved_at_80[0x10]; 1020 u8 packet_pacing_rate_table_size[0x10]; 1021 1022 u8 esw_element_type[0x10]; 1023 u8 esw_tsar_type[0x10]; 1024 1025 u8 reserved_at_c0[0x10]; 1026 u8 max_qos_para_vport[0x10]; 1027 1028 u8 max_tsar_bw_share[0x20]; 1029 1030 u8 reserved_at_100[0x20]; 1031 1032 u8 reserved_at_120[0x3]; 1033 u8 log_meter_aso_granularity[0x5]; 1034 u8 reserved_at_128[0x3]; 1035 u8 log_meter_aso_max_alloc[0x5]; 1036 u8 reserved_at_130[0x3]; 1037 u8 log_max_num_meter_aso[0x5]; 1038 u8 reserved_at_138[0x8]; 1039 1040 u8 reserved_at_140[0x6c0]; 1041 }; 1042 1043 struct mlx5_ifc_debug_cap_bits { 1044 u8 core_dump_general[0x1]; 1045 u8 core_dump_qp[0x1]; 1046 u8 reserved_at_2[0x7]; 1047 u8 resource_dump[0x1]; 1048 u8 reserved_at_a[0x16]; 1049 1050 u8 reserved_at_20[0x2]; 1051 u8 stall_detect[0x1]; 1052 u8 reserved_at_23[0x1d]; 1053 1054 u8 reserved_at_40[0x7c0]; 1055 }; 1056 1057 struct mlx5_ifc_per_protocol_networking_offload_caps_bits { 1058 u8 csum_cap[0x1]; 1059 u8 vlan_cap[0x1]; 1060 u8 lro_cap[0x1]; 1061 u8 lro_psh_flag[0x1]; 1062 u8 lro_time_stamp[0x1]; 1063 u8 reserved_at_5[0x2]; 1064 u8 wqe_vlan_insert[0x1]; 1065 u8 self_lb_en_modifiable[0x1]; 1066 u8 reserved_at_9[0x2]; 1067 u8 max_lso_cap[0x5]; 1068 u8 multi_pkt_send_wqe[0x2]; 1069 u8 wqe_inline_mode[0x2]; 1070 u8 rss_ind_tbl_cap[0x4]; 1071 u8 reg_umr_sq[0x1]; 1072 u8 scatter_fcs[0x1]; 1073 u8 enhanced_multi_pkt_send_wqe[0x1]; 1074 u8 tunnel_lso_const_out_ip_id[0x1]; 1075 u8 tunnel_lro_gre[0x1]; 1076 u8 tunnel_lro_vxlan[0x1]; 1077 u8 tunnel_stateless_gre[0x1]; 1078 u8 tunnel_stateless_vxlan[0x1]; 1079 1080 u8 swp[0x1]; 1081 u8 swp_csum[0x1]; 1082 u8 swp_lso[0x1]; 1083 u8 cqe_checksum_full[0x1]; 1084 u8 tunnel_stateless_geneve_tx[0x1]; 1085 u8 tunnel_stateless_mpls_over_udp[0x1]; 1086 u8 tunnel_stateless_mpls_over_gre[0x1]; 1087 u8 tunnel_stateless_vxlan_gpe[0x1]; 1088 u8 tunnel_stateless_ipv4_over_vxlan[0x1]; 1089 u8 tunnel_stateless_ip_over_ip[0x1]; 1090 u8 insert_trailer[0x1]; 1091 u8 reserved_at_2b[0x1]; 1092 u8 tunnel_stateless_ip_over_ip_rx[0x1]; 1093 u8 tunnel_stateless_ip_over_ip_tx[0x1]; 1094 u8 reserved_at_2e[0x2]; 1095 u8 max_vxlan_udp_ports[0x8]; 1096 u8 reserved_at_38[0x6]; 1097 u8 max_geneve_opt_len[0x1]; 1098 u8 tunnel_stateless_geneve_rx[0x1]; 1099 1100 u8 reserved_at_40[0x10]; 1101 u8 lro_min_mss_size[0x10]; 1102 1103 u8 reserved_at_60[0x120]; 1104 1105 u8 lro_timer_supported_periods[4][0x20]; 1106 1107 u8 reserved_at_200[0x600]; 1108 }; 1109 1110 enum { 1111 MLX5_TIMESTAMP_FORMAT_CAP_FREE_RUNNING = 0x0, 1112 MLX5_TIMESTAMP_FORMAT_CAP_REAL_TIME = 0x1, 1113 MLX5_TIMESTAMP_FORMAT_CAP_FREE_RUNNING_AND_REAL_TIME = 0x2, 1114 }; 1115 1116 struct mlx5_ifc_roce_cap_bits { 1117 u8 roce_apm[0x1]; 1118 u8 reserved_at_1[0x3]; 1119 u8 sw_r_roce_src_udp_port[0x1]; 1120 u8 fl_rc_qp_when_roce_disabled[0x1]; 1121 u8 fl_rc_qp_when_roce_enabled[0x1]; 1122 u8 roce_cc_general[0x1]; 1123 u8 qp_ooo_transmit_default[0x1]; 1124 u8 reserved_at_9[0x15]; 1125 u8 qp_ts_format[0x2]; 1126 1127 u8 reserved_at_20[0x60]; 1128 1129 u8 reserved_at_80[0xc]; 1130 u8 l3_type[0x4]; 1131 u8 reserved_at_90[0x8]; 1132 u8 roce_version[0x8]; 1133 1134 u8 reserved_at_a0[0x10]; 1135 u8 r_roce_dest_udp_port[0x10]; 1136 1137 u8 r_roce_max_src_udp_port[0x10]; 1138 u8 r_roce_min_src_udp_port[0x10]; 1139 1140 u8 reserved_at_e0[0x10]; 1141 u8 roce_address_table_size[0x10]; 1142 1143 u8 reserved_at_100[0x700]; 1144 }; 1145 1146 struct mlx5_ifc_sync_steering_in_bits { 1147 u8 opcode[0x10]; 1148 u8 uid[0x10]; 1149 1150 u8 reserved_at_20[0x10]; 1151 u8 op_mod[0x10]; 1152 1153 u8 reserved_at_40[0xc0]; 1154 }; 1155 1156 struct mlx5_ifc_sync_steering_out_bits { 1157 u8 status[0x8]; 1158 u8 reserved_at_8[0x18]; 1159 1160 u8 syndrome[0x20]; 1161 1162 u8 reserved_at_40[0x40]; 1163 }; 1164 1165 struct mlx5_ifc_sync_crypto_in_bits { 1166 u8 opcode[0x10]; 1167 u8 uid[0x10]; 1168 1169 u8 reserved_at_20[0x10]; 1170 u8 op_mod[0x10]; 1171 1172 u8 reserved_at_40[0x20]; 1173 1174 u8 reserved_at_60[0x10]; 1175 u8 crypto_type[0x10]; 1176 1177 u8 reserved_at_80[0x80]; 1178 }; 1179 1180 struct mlx5_ifc_sync_crypto_out_bits { 1181 u8 status[0x8]; 1182 u8 reserved_at_8[0x18]; 1183 1184 u8 syndrome[0x20]; 1185 1186 u8 reserved_at_40[0x40]; 1187 }; 1188 1189 struct mlx5_ifc_device_mem_cap_bits { 1190 u8 memic[0x1]; 1191 u8 reserved_at_1[0x1f]; 1192 1193 u8 reserved_at_20[0xb]; 1194 u8 log_min_memic_alloc_size[0x5]; 1195 u8 reserved_at_30[0x8]; 1196 u8 log_max_memic_addr_alignment[0x8]; 1197 1198 u8 memic_bar_start_addr[0x40]; 1199 1200 u8 memic_bar_size[0x20]; 1201 1202 u8 max_memic_size[0x20]; 1203 1204 u8 steering_sw_icm_start_address[0x40]; 1205 1206 u8 reserved_at_100[0x8]; 1207 u8 log_header_modify_sw_icm_size[0x8]; 1208 u8 reserved_at_110[0x2]; 1209 u8 log_sw_icm_alloc_granularity[0x6]; 1210 u8 log_steering_sw_icm_size[0x8]; 1211 1212 u8 log_indirect_encap_sw_icm_size[0x8]; 1213 u8 reserved_at_128[0x10]; 1214 u8 log_header_modify_pattern_sw_icm_size[0x8]; 1215 1216 u8 header_modify_sw_icm_start_address[0x40]; 1217 1218 u8 reserved_at_180[0x40]; 1219 1220 u8 header_modify_pattern_sw_icm_start_address[0x40]; 1221 1222 u8 memic_operations[0x20]; 1223 1224 u8 reserved_at_220[0x20]; 1225 1226 u8 indirect_encap_sw_icm_start_address[0x40]; 1227 1228 u8 reserved_at_280[0x580]; 1229 }; 1230 1231 struct mlx5_ifc_device_event_cap_bits { 1232 u8 user_affiliated_events[4][0x40]; 1233 1234 u8 user_unaffiliated_events[4][0x40]; 1235 }; 1236 1237 struct mlx5_ifc_virtio_emulation_cap_bits { 1238 u8 desc_tunnel_offload_type[0x1]; 1239 u8 eth_frame_offload_type[0x1]; 1240 u8 virtio_version_1_0[0x1]; 1241 u8 device_features_bits_mask[0xd]; 1242 u8 event_mode[0x8]; 1243 u8 virtio_queue_type[0x8]; 1244 1245 u8 max_tunnel_desc[0x10]; 1246 u8 reserved_at_30[0x3]; 1247 u8 log_doorbell_stride[0x5]; 1248 u8 reserved_at_38[0x3]; 1249 u8 log_doorbell_bar_size[0x5]; 1250 1251 u8 doorbell_bar_offset[0x40]; 1252 1253 u8 max_emulated_devices[0x8]; 1254 u8 max_num_virtio_queues[0x18]; 1255 1256 u8 reserved_at_a0[0x20]; 1257 1258 u8 reserved_at_c0[0x13]; 1259 u8 desc_group_mkey_supported[0x1]; 1260 u8 freeze_to_rdy_supported[0x1]; 1261 u8 reserved_at_d5[0xb]; 1262 1263 u8 reserved_at_e0[0x20]; 1264 1265 u8 umem_1_buffer_param_a[0x20]; 1266 1267 u8 umem_1_buffer_param_b[0x20]; 1268 1269 u8 umem_2_buffer_param_a[0x20]; 1270 1271 u8 umem_2_buffer_param_b[0x20]; 1272 1273 u8 umem_3_buffer_param_a[0x20]; 1274 1275 u8 umem_3_buffer_param_b[0x20]; 1276 1277 u8 reserved_at_1c0[0x640]; 1278 }; 1279 1280 enum { 1281 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_QP_1_BYTE = 0x0, 1282 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_QP_2_BYTES = 0x2, 1283 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_QP_4_BYTES = 0x4, 1284 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_QP_8_BYTES = 0x8, 1285 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_QP_16_BYTES = 0x10, 1286 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_QP_32_BYTES = 0x20, 1287 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_QP_64_BYTES = 0x40, 1288 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_QP_128_BYTES = 0x80, 1289 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_QP_256_BYTES = 0x100, 1290 }; 1291 1292 enum { 1293 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_DC_1_BYTE = 0x1, 1294 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_DC_2_BYTES = 0x2, 1295 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_DC_4_BYTES = 0x4, 1296 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_DC_8_BYTES = 0x8, 1297 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_DC_16_BYTES = 0x10, 1298 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_DC_32_BYTES = 0x20, 1299 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_DC_64_BYTES = 0x40, 1300 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_DC_128_BYTES = 0x80, 1301 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_DC_256_BYTES = 0x100, 1302 }; 1303 1304 struct mlx5_ifc_atomic_caps_bits { 1305 u8 reserved_at_0[0x40]; 1306 1307 u8 atomic_req_8B_endianness_mode[0x2]; 1308 u8 reserved_at_42[0x4]; 1309 u8 supported_atomic_req_8B_endianness_mode_1[0x1]; 1310 1311 u8 reserved_at_47[0x19]; 1312 1313 u8 reserved_at_60[0x20]; 1314 1315 u8 reserved_at_80[0x10]; 1316 u8 atomic_operations[0x10]; 1317 1318 u8 reserved_at_a0[0x10]; 1319 u8 atomic_size_qp[0x10]; 1320 1321 u8 reserved_at_c0[0x10]; 1322 u8 atomic_size_dc[0x10]; 1323 1324 u8 reserved_at_e0[0x720]; 1325 }; 1326 1327 struct mlx5_ifc_odp_cap_bits { 1328 u8 reserved_at_0[0x40]; 1329 1330 u8 sig[0x1]; 1331 u8 reserved_at_41[0x1f]; 1332 1333 u8 reserved_at_60[0x20]; 1334 1335 struct mlx5_ifc_odp_per_transport_service_cap_bits rc_odp_caps; 1336 1337 struct mlx5_ifc_odp_per_transport_service_cap_bits uc_odp_caps; 1338 1339 struct mlx5_ifc_odp_per_transport_service_cap_bits ud_odp_caps; 1340 1341 struct mlx5_ifc_odp_per_transport_service_cap_bits xrc_odp_caps; 1342 1343 struct mlx5_ifc_odp_per_transport_service_cap_bits dc_odp_caps; 1344 1345 u8 reserved_at_120[0x6E0]; 1346 }; 1347 1348 struct mlx5_ifc_tls_cap_bits { 1349 u8 tls_1_2_aes_gcm_128[0x1]; 1350 u8 tls_1_3_aes_gcm_128[0x1]; 1351 u8 tls_1_2_aes_gcm_256[0x1]; 1352 u8 tls_1_3_aes_gcm_256[0x1]; 1353 u8 reserved_at_4[0x1c]; 1354 1355 u8 reserved_at_20[0x7e0]; 1356 }; 1357 1358 struct mlx5_ifc_ipsec_cap_bits { 1359 u8 ipsec_full_offload[0x1]; 1360 u8 ipsec_crypto_offload[0x1]; 1361 u8 ipsec_esn[0x1]; 1362 u8 ipsec_crypto_esp_aes_gcm_256_encrypt[0x1]; 1363 u8 ipsec_crypto_esp_aes_gcm_128_encrypt[0x1]; 1364 u8 ipsec_crypto_esp_aes_gcm_256_decrypt[0x1]; 1365 u8 ipsec_crypto_esp_aes_gcm_128_decrypt[0x1]; 1366 u8 reserved_at_7[0x4]; 1367 u8 log_max_ipsec_offload[0x5]; 1368 u8 reserved_at_10[0x10]; 1369 1370 u8 min_log_ipsec_full_replay_window[0x8]; 1371 u8 max_log_ipsec_full_replay_window[0x8]; 1372 u8 reserved_at_30[0x7d0]; 1373 }; 1374 1375 struct mlx5_ifc_macsec_cap_bits { 1376 u8 macsec_epn[0x1]; 1377 u8 reserved_at_1[0x2]; 1378 u8 macsec_crypto_esp_aes_gcm_256_encrypt[0x1]; 1379 u8 macsec_crypto_esp_aes_gcm_128_encrypt[0x1]; 1380 u8 macsec_crypto_esp_aes_gcm_256_decrypt[0x1]; 1381 u8 macsec_crypto_esp_aes_gcm_128_decrypt[0x1]; 1382 u8 reserved_at_7[0x4]; 1383 u8 log_max_macsec_offload[0x5]; 1384 u8 reserved_at_10[0x10]; 1385 1386 u8 min_log_macsec_full_replay_window[0x8]; 1387 u8 max_log_macsec_full_replay_window[0x8]; 1388 u8 reserved_at_30[0x10]; 1389 1390 u8 reserved_at_40[0x7c0]; 1391 }; 1392 1393 enum { 1394 MLX5_WQ_TYPE_LINKED_LIST = 0x0, 1395 MLX5_WQ_TYPE_CYCLIC = 0x1, 1396 MLX5_WQ_TYPE_LINKED_LIST_STRIDING_RQ = 0x2, 1397 MLX5_WQ_TYPE_CYCLIC_STRIDING_RQ = 0x3, 1398 }; 1399 1400 enum { 1401 MLX5_WQ_END_PAD_MODE_NONE = 0x0, 1402 MLX5_WQ_END_PAD_MODE_ALIGN = 0x1, 1403 }; 1404 1405 enum { 1406 MLX5_CMD_HCA_CAP_GID_TABLE_SIZE_8_GID_ENTRIES = 0x0, 1407 MLX5_CMD_HCA_CAP_GID_TABLE_SIZE_16_GID_ENTRIES = 0x1, 1408 MLX5_CMD_HCA_CAP_GID_TABLE_SIZE_32_GID_ENTRIES = 0x2, 1409 MLX5_CMD_HCA_CAP_GID_TABLE_SIZE_64_GID_ENTRIES = 0x3, 1410 MLX5_CMD_HCA_CAP_GID_TABLE_SIZE_128_GID_ENTRIES = 0x4, 1411 }; 1412 1413 enum { 1414 MLX5_CMD_HCA_CAP_PKEY_TABLE_SIZE_128_ENTRIES = 0x0, 1415 MLX5_CMD_HCA_CAP_PKEY_TABLE_SIZE_256_ENTRIES = 0x1, 1416 MLX5_CMD_HCA_CAP_PKEY_TABLE_SIZE_512_ENTRIES = 0x2, 1417 MLX5_CMD_HCA_CAP_PKEY_TABLE_SIZE_1K_ENTRIES = 0x3, 1418 MLX5_CMD_HCA_CAP_PKEY_TABLE_SIZE_2K_ENTRIES = 0x4, 1419 MLX5_CMD_HCA_CAP_PKEY_TABLE_SIZE_4K_ENTRIES = 0x5, 1420 }; 1421 1422 enum { 1423 MLX5_CMD_HCA_CAP_PORT_TYPE_IB = 0x0, 1424 MLX5_CMD_HCA_CAP_PORT_TYPE_ETHERNET = 0x1, 1425 }; 1426 1427 enum { 1428 MLX5_CMD_HCA_CAP_CMDIF_CHECKSUM_DISABLED = 0x0, 1429 MLX5_CMD_HCA_CAP_CMDIF_CHECKSUM_INITIAL_STATE = 0x1, 1430 MLX5_CMD_HCA_CAP_CMDIF_CHECKSUM_ENABLED = 0x3, 1431 }; 1432 1433 enum { 1434 MLX5_CAP_PORT_TYPE_IB = 0x0, 1435 MLX5_CAP_PORT_TYPE_ETH = 0x1, 1436 }; 1437 1438 enum { 1439 MLX5_CAP_UMR_FENCE_STRONG = 0x0, 1440 MLX5_CAP_UMR_FENCE_SMALL = 0x1, 1441 MLX5_CAP_UMR_FENCE_NONE = 0x2, 1442 }; 1443 1444 enum { 1445 MLX5_FLEX_PARSER_GENEVE_ENABLED = 1 << 3, 1446 MLX5_FLEX_PARSER_MPLS_OVER_GRE_ENABLED = 1 << 4, 1447 MLX5_FLEX_PARSER_MPLS_OVER_UDP_ENABLED = 1 << 5, 1448 MLX5_FLEX_PARSER_VXLAN_GPE_ENABLED = 1 << 7, 1449 MLX5_FLEX_PARSER_ICMP_V4_ENABLED = 1 << 8, 1450 MLX5_FLEX_PARSER_ICMP_V6_ENABLED = 1 << 9, 1451 MLX5_FLEX_PARSER_GENEVE_TLV_OPTION_0_ENABLED = 1 << 10, 1452 MLX5_FLEX_PARSER_GTPU_ENABLED = 1 << 11, 1453 MLX5_FLEX_PARSER_GTPU_DW_2_ENABLED = 1 << 16, 1454 MLX5_FLEX_PARSER_GTPU_FIRST_EXT_DW_0_ENABLED = 1 << 17, 1455 MLX5_FLEX_PARSER_GTPU_DW_0_ENABLED = 1 << 18, 1456 MLX5_FLEX_PARSER_GTPU_TEID_ENABLED = 1 << 19, 1457 }; 1458 1459 enum { 1460 MLX5_UCTX_CAP_RAW_TX = 1UL << 0, 1461 MLX5_UCTX_CAP_INTERNAL_DEV_RES = 1UL << 1, 1462 }; 1463 1464 #define MLX5_FC_BULK_SIZE_FACTOR 128 1465 1466 enum mlx5_fc_bulk_alloc_bitmask { 1467 MLX5_FC_BULK_128 = (1 << 0), 1468 MLX5_FC_BULK_256 = (1 << 1), 1469 MLX5_FC_BULK_512 = (1 << 2), 1470 MLX5_FC_BULK_1024 = (1 << 3), 1471 MLX5_FC_BULK_2048 = (1 << 4), 1472 MLX5_FC_BULK_4096 = (1 << 5), 1473 MLX5_FC_BULK_8192 = (1 << 6), 1474 MLX5_FC_BULK_16384 = (1 << 7), 1475 }; 1476 1477 #define MLX5_FC_BULK_NUM_FCS(fc_enum) (MLX5_FC_BULK_SIZE_FACTOR * (fc_enum)) 1478 1479 #define MLX5_FT_MAX_MULTIPATH_LEVEL 63 1480 1481 enum { 1482 MLX5_STEERING_FORMAT_CONNECTX_5 = 0, 1483 MLX5_STEERING_FORMAT_CONNECTX_6DX = 1, 1484 MLX5_STEERING_FORMAT_CONNECTX_7 = 2, 1485 }; 1486 1487 struct mlx5_ifc_cmd_hca_cap_bits { 1488 u8 reserved_at_0[0x6]; 1489 u8 page_request_disable[0x1]; 1490 u8 reserved_at_7[0x9]; 1491 u8 shared_object_to_user_object_allowed[0x1]; 1492 u8 reserved_at_13[0xe]; 1493 u8 vhca_resource_manager[0x1]; 1494 1495 u8 hca_cap_2[0x1]; 1496 u8 create_lag_when_not_master_up[0x1]; 1497 u8 dtor[0x1]; 1498 u8 event_on_vhca_state_teardown_request[0x1]; 1499 u8 event_on_vhca_state_in_use[0x1]; 1500 u8 event_on_vhca_state_active[0x1]; 1501 u8 event_on_vhca_state_allocated[0x1]; 1502 u8 event_on_vhca_state_invalid[0x1]; 1503 u8 reserved_at_28[0x8]; 1504 u8 vhca_id[0x10]; 1505 1506 u8 reserved_at_40[0x40]; 1507 1508 u8 log_max_srq_sz[0x8]; 1509 u8 log_max_qp_sz[0x8]; 1510 u8 event_cap[0x1]; 1511 u8 reserved_at_91[0x2]; 1512 u8 isolate_vl_tc_new[0x1]; 1513 u8 reserved_at_94[0x4]; 1514 u8 prio_tag_required[0x1]; 1515 u8 reserved_at_99[0x2]; 1516 u8 log_max_qp[0x5]; 1517 1518 u8 reserved_at_a0[0x3]; 1519 u8 ece_support[0x1]; 1520 u8 reserved_at_a4[0x5]; 1521 u8 reg_c_preserve[0x1]; 1522 u8 reserved_at_aa[0x1]; 1523 u8 log_max_srq[0x5]; 1524 u8 reserved_at_b0[0x1]; 1525 u8 uplink_follow[0x1]; 1526 u8 ts_cqe_to_dest_cqn[0x1]; 1527 u8 reserved_at_b3[0x6]; 1528 u8 go_back_n[0x1]; 1529 u8 reserved_at_ba[0x6]; 1530 1531 u8 max_sgl_for_optimized_performance[0x8]; 1532 u8 log_max_cq_sz[0x8]; 1533 u8 relaxed_ordering_write_umr[0x1]; 1534 u8 relaxed_ordering_read_umr[0x1]; 1535 u8 reserved_at_d2[0x7]; 1536 u8 virtio_net_device_emualtion_manager[0x1]; 1537 u8 virtio_blk_device_emualtion_manager[0x1]; 1538 u8 log_max_cq[0x5]; 1539 1540 u8 log_max_eq_sz[0x8]; 1541 u8 relaxed_ordering_write[0x1]; 1542 u8 relaxed_ordering_read_pci_enabled[0x1]; 1543 u8 log_max_mkey[0x6]; 1544 u8 reserved_at_f0[0x6]; 1545 u8 terminate_scatter_list_mkey[0x1]; 1546 u8 repeated_mkey[0x1]; 1547 u8 dump_fill_mkey[0x1]; 1548 u8 reserved_at_f9[0x2]; 1549 u8 fast_teardown[0x1]; 1550 u8 log_max_eq[0x4]; 1551 1552 u8 max_indirection[0x8]; 1553 u8 fixed_buffer_size[0x1]; 1554 u8 log_max_mrw_sz[0x7]; 1555 u8 force_teardown[0x1]; 1556 u8 reserved_at_111[0x1]; 1557 u8 log_max_bsf_list_size[0x6]; 1558 u8 umr_extended_translation_offset[0x1]; 1559 u8 null_mkey[0x1]; 1560 u8 log_max_klm_list_size[0x6]; 1561 1562 u8 reserved_at_120[0x2]; 1563 u8 qpc_extension[0x1]; 1564 u8 reserved_at_123[0x7]; 1565 u8 log_max_ra_req_dc[0x6]; 1566 u8 reserved_at_130[0x2]; 1567 u8 eth_wqe_too_small[0x1]; 1568 u8 reserved_at_133[0x6]; 1569 u8 vnic_env_cq_overrun[0x1]; 1570 u8 log_max_ra_res_dc[0x6]; 1571 1572 u8 reserved_at_140[0x5]; 1573 u8 release_all_pages[0x1]; 1574 u8 must_not_use[0x1]; 1575 u8 reserved_at_147[0x2]; 1576 u8 roce_accl[0x1]; 1577 u8 log_max_ra_req_qp[0x6]; 1578 u8 reserved_at_150[0xa]; 1579 u8 log_max_ra_res_qp[0x6]; 1580 1581 u8 end_pad[0x1]; 1582 u8 cc_query_allowed[0x1]; 1583 u8 cc_modify_allowed[0x1]; 1584 u8 start_pad[0x1]; 1585 u8 cache_line_128byte[0x1]; 1586 u8 reserved_at_165[0x4]; 1587 u8 rts2rts_qp_counters_set_id[0x1]; 1588 u8 reserved_at_16a[0x2]; 1589 u8 vnic_env_int_rq_oob[0x1]; 1590 u8 sbcam_reg[0x1]; 1591 u8 reserved_at_16e[0x1]; 1592 u8 qcam_reg[0x1]; 1593 u8 gid_table_size[0x10]; 1594 1595 u8 out_of_seq_cnt[0x1]; 1596 u8 vport_counters[0x1]; 1597 u8 retransmission_q_counters[0x1]; 1598 u8 debug[0x1]; 1599 u8 modify_rq_counter_set_id[0x1]; 1600 u8 rq_delay_drop[0x1]; 1601 u8 max_qp_cnt[0xa]; 1602 u8 pkey_table_size[0x10]; 1603 1604 u8 vport_group_manager[0x1]; 1605 u8 vhca_group_manager[0x1]; 1606 u8 ib_virt[0x1]; 1607 u8 eth_virt[0x1]; 1608 u8 vnic_env_queue_counters[0x1]; 1609 u8 ets[0x1]; 1610 u8 nic_flow_table[0x1]; 1611 u8 eswitch_manager[0x1]; 1612 u8 device_memory[0x1]; 1613 u8 mcam_reg[0x1]; 1614 u8 pcam_reg[0x1]; 1615 u8 local_ca_ack_delay[0x5]; 1616 u8 port_module_event[0x1]; 1617 u8 enhanced_error_q_counters[0x1]; 1618 u8 ports_check[0x1]; 1619 u8 reserved_at_1b3[0x1]; 1620 u8 disable_link_up[0x1]; 1621 u8 beacon_led[0x1]; 1622 u8 port_type[0x2]; 1623 u8 num_ports[0x8]; 1624 1625 u8 reserved_at_1c0[0x1]; 1626 u8 pps[0x1]; 1627 u8 pps_modify[0x1]; 1628 u8 log_max_msg[0x5]; 1629 u8 reserved_at_1c8[0x4]; 1630 u8 max_tc[0x4]; 1631 u8 temp_warn_event[0x1]; 1632 u8 dcbx[0x1]; 1633 u8 general_notification_event[0x1]; 1634 u8 reserved_at_1d3[0x2]; 1635 u8 fpga[0x1]; 1636 u8 rol_s[0x1]; 1637 u8 rol_g[0x1]; 1638 u8 reserved_at_1d8[0x1]; 1639 u8 wol_s[0x1]; 1640 u8 wol_g[0x1]; 1641 u8 wol_a[0x1]; 1642 u8 wol_b[0x1]; 1643 u8 wol_m[0x1]; 1644 u8 wol_u[0x1]; 1645 u8 wol_p[0x1]; 1646 1647 u8 stat_rate_support[0x10]; 1648 u8 reserved_at_1f0[0x1]; 1649 u8 pci_sync_for_fw_update_event[0x1]; 1650 u8 reserved_at_1f2[0x6]; 1651 u8 init2_lag_tx_port_affinity[0x1]; 1652 u8 reserved_at_1fa[0x3]; 1653 u8 cqe_version[0x4]; 1654 1655 u8 compact_address_vector[0x1]; 1656 u8 striding_rq[0x1]; 1657 u8 reserved_at_202[0x1]; 1658 u8 ipoib_enhanced_offloads[0x1]; 1659 u8 ipoib_basic_offloads[0x1]; 1660 u8 reserved_at_205[0x1]; 1661 u8 repeated_block_disabled[0x1]; 1662 u8 umr_modify_entity_size_disabled[0x1]; 1663 u8 umr_modify_atomic_disabled[0x1]; 1664 u8 umr_indirect_mkey_disabled[0x1]; 1665 u8 umr_fence[0x2]; 1666 u8 dc_req_scat_data_cqe[0x1]; 1667 u8 reserved_at_20d[0x2]; 1668 u8 drain_sigerr[0x1]; 1669 u8 cmdif_checksum[0x2]; 1670 u8 sigerr_cqe[0x1]; 1671 u8 reserved_at_213[0x1]; 1672 u8 wq_signature[0x1]; 1673 u8 sctr_data_cqe[0x1]; 1674 u8 reserved_at_216[0x1]; 1675 u8 sho[0x1]; 1676 u8 tph[0x1]; 1677 u8 rf[0x1]; 1678 u8 dct[0x1]; 1679 u8 qos[0x1]; 1680 u8 eth_net_offloads[0x1]; 1681 u8 roce[0x1]; 1682 u8 atomic[0x1]; 1683 u8 reserved_at_21f[0x1]; 1684 1685 u8 cq_oi[0x1]; 1686 u8 cq_resize[0x1]; 1687 u8 cq_moderation[0x1]; 1688 u8 cq_period_mode_modify[0x1]; 1689 u8 reserved_at_224[0x2]; 1690 u8 cq_eq_remap[0x1]; 1691 u8 pg[0x1]; 1692 u8 block_lb_mc[0x1]; 1693 u8 reserved_at_229[0x1]; 1694 u8 scqe_break_moderation[0x1]; 1695 u8 cq_period_start_from_cqe[0x1]; 1696 u8 cd[0x1]; 1697 u8 reserved_at_22d[0x1]; 1698 u8 apm[0x1]; 1699 u8 vector_calc[0x1]; 1700 u8 umr_ptr_rlky[0x1]; 1701 u8 imaicl[0x1]; 1702 u8 qp_packet_based[0x1]; 1703 u8 reserved_at_233[0x3]; 1704 u8 qkv[0x1]; 1705 u8 pkv[0x1]; 1706 u8 set_deth_sqpn[0x1]; 1707 u8 reserved_at_239[0x3]; 1708 u8 xrc[0x1]; 1709 u8 ud[0x1]; 1710 u8 uc[0x1]; 1711 u8 rc[0x1]; 1712 1713 u8 uar_4k[0x1]; 1714 u8 reserved_at_241[0x7]; 1715 u8 fl_rc_qp_when_roce_disabled[0x1]; 1716 u8 regexp_params[0x1]; 1717 u8 uar_sz[0x6]; 1718 u8 port_selection_cap[0x1]; 1719 u8 reserved_at_251[0x1]; 1720 u8 umem_uid_0[0x1]; 1721 u8 reserved_at_253[0x5]; 1722 u8 log_pg_sz[0x8]; 1723 1724 u8 bf[0x1]; 1725 u8 driver_version[0x1]; 1726 u8 pad_tx_eth_packet[0x1]; 1727 u8 reserved_at_263[0x3]; 1728 u8 mkey_by_name[0x1]; 1729 u8 reserved_at_267[0x4]; 1730 1731 u8 log_bf_reg_size[0x5]; 1732 1733 u8 reserved_at_270[0x3]; 1734 u8 qp_error_syndrome[0x1]; 1735 u8 reserved_at_274[0x2]; 1736 u8 lag_dct[0x2]; 1737 u8 lag_tx_port_affinity[0x1]; 1738 u8 lag_native_fdb_selection[0x1]; 1739 u8 reserved_at_27a[0x1]; 1740 u8 lag_master[0x1]; 1741 u8 num_lag_ports[0x4]; 1742 1743 u8 reserved_at_280[0x10]; 1744 u8 max_wqe_sz_sq[0x10]; 1745 1746 u8 reserved_at_2a0[0xb]; 1747 u8 shampo[0x1]; 1748 u8 reserved_at_2ac[0x4]; 1749 u8 max_wqe_sz_rq[0x10]; 1750 1751 u8 max_flow_counter_31_16[0x10]; 1752 u8 max_wqe_sz_sq_dc[0x10]; 1753 1754 u8 reserved_at_2e0[0x7]; 1755 u8 max_qp_mcg[0x19]; 1756 1757 u8 reserved_at_300[0x10]; 1758 u8 flow_counter_bulk_alloc[0x8]; 1759 u8 log_max_mcg[0x8]; 1760 1761 u8 reserved_at_320[0x3]; 1762 u8 log_max_transport_domain[0x5]; 1763 u8 reserved_at_328[0x2]; 1764 u8 relaxed_ordering_read[0x1]; 1765 u8 log_max_pd[0x5]; 1766 u8 reserved_at_330[0x6]; 1767 u8 pci_sync_for_fw_update_with_driver_unload[0x1]; 1768 u8 vnic_env_cnt_steering_fail[0x1]; 1769 u8 vport_counter_local_loopback[0x1]; 1770 u8 q_counter_aggregation[0x1]; 1771 u8 q_counter_other_vport[0x1]; 1772 u8 log_max_xrcd[0x5]; 1773 1774 u8 nic_receive_steering_discard[0x1]; 1775 u8 receive_discard_vport_down[0x1]; 1776 u8 transmit_discard_vport_down[0x1]; 1777 u8 eq_overrun_count[0x1]; 1778 u8 reserved_at_344[0x1]; 1779 u8 invalid_command_count[0x1]; 1780 u8 quota_exceeded_count[0x1]; 1781 u8 reserved_at_347[0x1]; 1782 u8 log_max_flow_counter_bulk[0x8]; 1783 u8 max_flow_counter_15_0[0x10]; 1784 1785 1786 u8 reserved_at_360[0x3]; 1787 u8 log_max_rq[0x5]; 1788 u8 reserved_at_368[0x3]; 1789 u8 log_max_sq[0x5]; 1790 u8 reserved_at_370[0x3]; 1791 u8 log_max_tir[0x5]; 1792 u8 reserved_at_378[0x3]; 1793 u8 log_max_tis[0x5]; 1794 1795 u8 basic_cyclic_rcv_wqe[0x1]; 1796 u8 reserved_at_381[0x2]; 1797 u8 log_max_rmp[0x5]; 1798 u8 reserved_at_388[0x3]; 1799 u8 log_max_rqt[0x5]; 1800 u8 reserved_at_390[0x3]; 1801 u8 log_max_rqt_size[0x5]; 1802 u8 reserved_at_398[0x3]; 1803 u8 log_max_tis_per_sq[0x5]; 1804 1805 u8 ext_stride_num_range[0x1]; 1806 u8 roce_rw_supported[0x1]; 1807 u8 log_max_current_uc_list_wr_supported[0x1]; 1808 u8 log_max_stride_sz_rq[0x5]; 1809 u8 reserved_at_3a8[0x3]; 1810 u8 log_min_stride_sz_rq[0x5]; 1811 u8 reserved_at_3b0[0x3]; 1812 u8 log_max_stride_sz_sq[0x5]; 1813 u8 reserved_at_3b8[0x3]; 1814 u8 log_min_stride_sz_sq[0x5]; 1815 1816 u8 hairpin[0x1]; 1817 u8 reserved_at_3c1[0x2]; 1818 u8 log_max_hairpin_queues[0x5]; 1819 u8 reserved_at_3c8[0x3]; 1820 u8 log_max_hairpin_wq_data_sz[0x5]; 1821 u8 reserved_at_3d0[0x3]; 1822 u8 log_max_hairpin_num_packets[0x5]; 1823 u8 reserved_at_3d8[0x3]; 1824 u8 log_max_wq_sz[0x5]; 1825 1826 u8 nic_vport_change_event[0x1]; 1827 u8 disable_local_lb_uc[0x1]; 1828 u8 disable_local_lb_mc[0x1]; 1829 u8 log_min_hairpin_wq_data_sz[0x5]; 1830 u8 reserved_at_3e8[0x1]; 1831 u8 silent_mode[0x1]; 1832 u8 vhca_state[0x1]; 1833 u8 log_max_vlan_list[0x5]; 1834 u8 reserved_at_3f0[0x3]; 1835 u8 log_max_current_mc_list[0x5]; 1836 u8 reserved_at_3f8[0x3]; 1837 u8 log_max_current_uc_list[0x5]; 1838 1839 u8 general_obj_types[0x40]; 1840 1841 u8 sq_ts_format[0x2]; 1842 u8 rq_ts_format[0x2]; 1843 u8 steering_format_version[0x4]; 1844 u8 create_qp_start_hint[0x18]; 1845 1846 u8 reserved_at_460[0x1]; 1847 u8 ats[0x1]; 1848 u8 cross_vhca_rqt[0x1]; 1849 u8 log_max_uctx[0x5]; 1850 u8 reserved_at_468[0x1]; 1851 u8 crypto[0x1]; 1852 u8 ipsec_offload[0x1]; 1853 u8 log_max_umem[0x5]; 1854 u8 max_num_eqs[0x10]; 1855 1856 u8 reserved_at_480[0x1]; 1857 u8 tls_tx[0x1]; 1858 u8 tls_rx[0x1]; 1859 u8 log_max_l2_table[0x5]; 1860 u8 reserved_at_488[0x8]; 1861 u8 log_uar_page_sz[0x10]; 1862 1863 u8 reserved_at_4a0[0x20]; 1864 u8 device_frequency_mhz[0x20]; 1865 u8 device_frequency_khz[0x20]; 1866 1867 u8 reserved_at_500[0x20]; 1868 u8 num_of_uars_per_page[0x20]; 1869 1870 u8 flex_parser_protocols[0x20]; 1871 1872 u8 max_geneve_tlv_options[0x8]; 1873 u8 reserved_at_568[0x3]; 1874 u8 max_geneve_tlv_option_data_len[0x5]; 1875 u8 reserved_at_570[0x9]; 1876 u8 adv_virtualization[0x1]; 1877 u8 reserved_at_57a[0x6]; 1878 1879 u8 reserved_at_580[0xb]; 1880 u8 log_max_dci_stream_channels[0x5]; 1881 u8 reserved_at_590[0x3]; 1882 u8 log_max_dci_errored_streams[0x5]; 1883 u8 reserved_at_598[0x8]; 1884 1885 u8 reserved_at_5a0[0x10]; 1886 u8 enhanced_cqe_compression[0x1]; 1887 u8 reserved_at_5b1[0x2]; 1888 u8 log_max_dek[0x5]; 1889 u8 reserved_at_5b8[0x4]; 1890 u8 mini_cqe_resp_stride_index[0x1]; 1891 u8 cqe_128_always[0x1]; 1892 u8 cqe_compression_128[0x1]; 1893 u8 cqe_compression[0x1]; 1894 1895 u8 cqe_compression_timeout[0x10]; 1896 u8 cqe_compression_max_num[0x10]; 1897 1898 u8 reserved_at_5e0[0x8]; 1899 u8 flex_parser_id_gtpu_dw_0[0x4]; 1900 u8 reserved_at_5ec[0x4]; 1901 u8 tag_matching[0x1]; 1902 u8 rndv_offload_rc[0x1]; 1903 u8 rndv_offload_dc[0x1]; 1904 u8 log_tag_matching_list_sz[0x5]; 1905 u8 reserved_at_5f8[0x3]; 1906 u8 log_max_xrq[0x5]; 1907 1908 u8 affiliate_nic_vport_criteria[0x8]; 1909 u8 native_port_num[0x8]; 1910 u8 num_vhca_ports[0x8]; 1911 u8 flex_parser_id_gtpu_teid[0x4]; 1912 u8 reserved_at_61c[0x2]; 1913 u8 sw_owner_id[0x1]; 1914 u8 reserved_at_61f[0x1]; 1915 1916 u8 max_num_of_monitor_counters[0x10]; 1917 u8 num_ppcnt_monitor_counters[0x10]; 1918 1919 u8 max_num_sf[0x10]; 1920 u8 num_q_monitor_counters[0x10]; 1921 1922 u8 reserved_at_660[0x20]; 1923 1924 u8 sf[0x1]; 1925 u8 sf_set_partition[0x1]; 1926 u8 reserved_at_682[0x1]; 1927 u8 log_max_sf[0x5]; 1928 u8 apu[0x1]; 1929 u8 reserved_at_689[0x4]; 1930 u8 migration[0x1]; 1931 u8 reserved_at_68e[0x2]; 1932 u8 log_min_sf_size[0x8]; 1933 u8 max_num_sf_partitions[0x8]; 1934 1935 u8 uctx_cap[0x20]; 1936 1937 u8 reserved_at_6c0[0x4]; 1938 u8 flex_parser_id_geneve_tlv_option_0[0x4]; 1939 u8 flex_parser_id_icmp_dw1[0x4]; 1940 u8 flex_parser_id_icmp_dw0[0x4]; 1941 u8 flex_parser_id_icmpv6_dw1[0x4]; 1942 u8 flex_parser_id_icmpv6_dw0[0x4]; 1943 u8 flex_parser_id_outer_first_mpls_over_gre[0x4]; 1944 u8 flex_parser_id_outer_first_mpls_over_udp_label[0x4]; 1945 1946 u8 max_num_match_definer[0x10]; 1947 u8 sf_base_id[0x10]; 1948 1949 u8 flex_parser_id_gtpu_dw_2[0x4]; 1950 u8 flex_parser_id_gtpu_first_ext_dw_0[0x4]; 1951 u8 num_total_dynamic_vf_msix[0x18]; 1952 u8 reserved_at_720[0x14]; 1953 u8 dynamic_msix_table_size[0xc]; 1954 u8 reserved_at_740[0xc]; 1955 u8 min_dynamic_vf_msix_table_size[0x4]; 1956 u8 reserved_at_750[0x4]; 1957 u8 max_dynamic_vf_msix_table_size[0xc]; 1958 1959 u8 reserved_at_760[0x3]; 1960 u8 log_max_num_header_modify_argument[0x5]; 1961 u8 reserved_at_768[0x4]; 1962 u8 log_header_modify_argument_granularity[0x4]; 1963 u8 reserved_at_770[0x3]; 1964 u8 log_header_modify_argument_max_alloc[0x5]; 1965 u8 reserved_at_778[0x8]; 1966 1967 u8 vhca_tunnel_commands[0x40]; 1968 u8 match_definer_format_supported[0x40]; 1969 }; 1970 1971 enum { 1972 MLX5_CROSS_VHCA_OBJ_TO_OBJ_SUPPORTED_LOCAL_FLOW_TABLE_TO_REMOTE_FLOW_TABLE_MISS = 0x80000, 1973 MLX5_CROSS_VHCA_OBJ_TO_OBJ_SUPPORTED_LOCAL_FLOW_TABLE_ROOT_TO_REMOTE_FLOW_TABLE = (1ULL << 20), 1974 }; 1975 1976 enum { 1977 MLX5_ALLOWED_OBJ_FOR_OTHER_VHCA_ACCESS_FLOW_TABLE = 0x200, 1978 }; 1979 1980 struct mlx5_ifc_cmd_hca_cap_2_bits { 1981 u8 reserved_at_0[0x80]; 1982 1983 u8 migratable[0x1]; 1984 u8 reserved_at_81[0x1f]; 1985 1986 u8 max_reformat_insert_size[0x8]; 1987 u8 max_reformat_insert_offset[0x8]; 1988 u8 max_reformat_remove_size[0x8]; 1989 u8 max_reformat_remove_offset[0x8]; 1990 1991 u8 reserved_at_c0[0x8]; 1992 u8 migration_multi_load[0x1]; 1993 u8 migration_tracking_state[0x1]; 1994 u8 reserved_at_ca[0x6]; 1995 u8 migration_in_chunks[0x1]; 1996 u8 reserved_at_d1[0xf]; 1997 1998 u8 cross_vhca_object_to_object_supported[0x20]; 1999 2000 u8 allowed_object_for_other_vhca_access[0x40]; 2001 2002 u8 reserved_at_140[0x60]; 2003 2004 u8 flow_table_type_2_type[0x8]; 2005 u8 reserved_at_1a8[0x3]; 2006 u8 log_min_mkey_entity_size[0x5]; 2007 u8 reserved_at_1b0[0x10]; 2008 2009 u8 reserved_at_1c0[0x60]; 2010 2011 u8 reserved_at_220[0x1]; 2012 u8 sw_vhca_id_valid[0x1]; 2013 u8 sw_vhca_id[0xe]; 2014 u8 reserved_at_230[0x10]; 2015 2016 u8 reserved_at_240[0xb]; 2017 u8 ts_cqe_metadata_size2wqe_counter[0x5]; 2018 u8 reserved_at_250[0x10]; 2019 2020 u8 reserved_at_260[0x120]; 2021 u8 reserved_at_380[0xb]; 2022 u8 min_mkey_log_entity_size_fixed_buffer[0x5]; 2023 u8 ec_vf_vport_base[0x10]; 2024 2025 u8 reserved_at_3a0[0x10]; 2026 u8 max_rqt_vhca_id[0x10]; 2027 2028 u8 reserved_at_3c0[0x20]; 2029 2030 u8 reserved_at_3e0[0x10]; 2031 u8 pcc_ifa2[0x1]; 2032 u8 reserved_at_3f1[0xf]; 2033 2034 u8 reserved_at_400[0x1]; 2035 u8 min_mkey_log_entity_size_fixed_buffer_valid[0x1]; 2036 u8 reserved_at_402[0x1e]; 2037 2038 u8 reserved_at_420[0x3e0]; 2039 }; 2040 2041 enum mlx5_ifc_flow_destination_type { 2042 MLX5_IFC_FLOW_DESTINATION_TYPE_VPORT = 0x0, 2043 MLX5_IFC_FLOW_DESTINATION_TYPE_FLOW_TABLE = 0x1, 2044 MLX5_IFC_FLOW_DESTINATION_TYPE_TIR = 0x2, 2045 MLX5_IFC_FLOW_DESTINATION_TYPE_FLOW_SAMPLER = 0x6, 2046 MLX5_IFC_FLOW_DESTINATION_TYPE_UPLINK = 0x8, 2047 MLX5_IFC_FLOW_DESTINATION_TYPE_TABLE_TYPE = 0xA, 2048 }; 2049 2050 enum mlx5_flow_table_miss_action { 2051 MLX5_FLOW_TABLE_MISS_ACTION_DEF, 2052 MLX5_FLOW_TABLE_MISS_ACTION_FWD, 2053 MLX5_FLOW_TABLE_MISS_ACTION_SWITCH_DOMAIN, 2054 }; 2055 2056 struct mlx5_ifc_dest_format_struct_bits { 2057 u8 destination_type[0x8]; 2058 u8 destination_id[0x18]; 2059 2060 u8 destination_eswitch_owner_vhca_id_valid[0x1]; 2061 u8 packet_reformat[0x1]; 2062 u8 reserved_at_22[0x6]; 2063 u8 destination_table_type[0x8]; 2064 u8 destination_eswitch_owner_vhca_id[0x10]; 2065 }; 2066 2067 struct mlx5_ifc_flow_counter_list_bits { 2068 u8 flow_counter_id[0x20]; 2069 2070 u8 reserved_at_20[0x20]; 2071 }; 2072 2073 struct mlx5_ifc_extended_dest_format_bits { 2074 struct mlx5_ifc_dest_format_struct_bits destination_entry; 2075 2076 u8 packet_reformat_id[0x20]; 2077 2078 u8 reserved_at_60[0x20]; 2079 }; 2080 2081 union mlx5_ifc_dest_format_struct_flow_counter_list_auto_bits { 2082 struct mlx5_ifc_extended_dest_format_bits extended_dest_format; 2083 struct mlx5_ifc_flow_counter_list_bits flow_counter_list; 2084 }; 2085 2086 struct mlx5_ifc_fte_match_param_bits { 2087 struct mlx5_ifc_fte_match_set_lyr_2_4_bits outer_headers; 2088 2089 struct mlx5_ifc_fte_match_set_misc_bits misc_parameters; 2090 2091 struct mlx5_ifc_fte_match_set_lyr_2_4_bits inner_headers; 2092 2093 struct mlx5_ifc_fte_match_set_misc2_bits misc_parameters_2; 2094 2095 struct mlx5_ifc_fte_match_set_misc3_bits misc_parameters_3; 2096 2097 struct mlx5_ifc_fte_match_set_misc4_bits misc_parameters_4; 2098 2099 struct mlx5_ifc_fte_match_set_misc5_bits misc_parameters_5; 2100 2101 u8 reserved_at_e00[0x200]; 2102 }; 2103 2104 enum { 2105 MLX5_RX_HASH_FIELD_SELECT_SELECTED_FIELDS_SRC_IP = 0x0, 2106 MLX5_RX_HASH_FIELD_SELECT_SELECTED_FIELDS_DST_IP = 0x1, 2107 MLX5_RX_HASH_FIELD_SELECT_SELECTED_FIELDS_L4_SPORT = 0x2, 2108 MLX5_RX_HASH_FIELD_SELECT_SELECTED_FIELDS_L4_DPORT = 0x3, 2109 MLX5_RX_HASH_FIELD_SELECT_SELECTED_FIELDS_IPSEC_SPI = 0x4, 2110 }; 2111 2112 struct mlx5_ifc_rx_hash_field_select_bits { 2113 u8 l3_prot_type[0x1]; 2114 u8 l4_prot_type[0x1]; 2115 u8 selected_fields[0x1e]; 2116 }; 2117 2118 enum { 2119 MLX5_WQ_WQ_TYPE_WQ_LINKED_LIST = 0x0, 2120 MLX5_WQ_WQ_TYPE_WQ_CYCLIC = 0x1, 2121 }; 2122 2123 enum { 2124 MLX5_WQ_END_PADDING_MODE_END_PAD_NONE = 0x0, 2125 MLX5_WQ_END_PADDING_MODE_END_PAD_ALIGN = 0x1, 2126 }; 2127 2128 struct mlx5_ifc_wq_bits { 2129 u8 wq_type[0x4]; 2130 u8 wq_signature[0x1]; 2131 u8 end_padding_mode[0x2]; 2132 u8 cd_slave[0x1]; 2133 u8 reserved_at_8[0x18]; 2134 2135 u8 hds_skip_first_sge[0x1]; 2136 u8 log2_hds_buf_size[0x3]; 2137 u8 reserved_at_24[0x7]; 2138 u8 page_offset[0x5]; 2139 u8 lwm[0x10]; 2140 2141 u8 reserved_at_40[0x8]; 2142 u8 pd[0x18]; 2143 2144 u8 reserved_at_60[0x8]; 2145 u8 uar_page[0x18]; 2146 2147 u8 dbr_addr[0x40]; 2148 2149 u8 hw_counter[0x20]; 2150 2151 u8 sw_counter[0x20]; 2152 2153 u8 reserved_at_100[0xc]; 2154 u8 log_wq_stride[0x4]; 2155 u8 reserved_at_110[0x3]; 2156 u8 log_wq_pg_sz[0x5]; 2157 u8 reserved_at_118[0x3]; 2158 u8 log_wq_sz[0x5]; 2159 2160 u8 dbr_umem_valid[0x1]; 2161 u8 wq_umem_valid[0x1]; 2162 u8 reserved_at_122[0x1]; 2163 u8 log_hairpin_num_packets[0x5]; 2164 u8 reserved_at_128[0x3]; 2165 u8 log_hairpin_data_sz[0x5]; 2166 2167 u8 reserved_at_130[0x4]; 2168 u8 log_wqe_num_of_strides[0x4]; 2169 u8 two_byte_shift_en[0x1]; 2170 u8 reserved_at_139[0x4]; 2171 u8 log_wqe_stride_size[0x3]; 2172 2173 u8 reserved_at_140[0x80]; 2174 2175 u8 headers_mkey[0x20]; 2176 2177 u8 shampo_enable[0x1]; 2178 u8 reserved_at_1e1[0x4]; 2179 u8 log_reservation_size[0x3]; 2180 u8 reserved_at_1e8[0x5]; 2181 u8 log_max_num_of_packets_per_reservation[0x3]; 2182 u8 reserved_at_1f0[0x6]; 2183 u8 log_headers_entry_size[0x2]; 2184 u8 reserved_at_1f8[0x4]; 2185 u8 log_headers_buffer_entry_num[0x4]; 2186 2187 u8 reserved_at_200[0x400]; 2188 2189 struct mlx5_ifc_cmd_pas_bits pas[]; 2190 }; 2191 2192 struct mlx5_ifc_rq_num_bits { 2193 u8 reserved_at_0[0x8]; 2194 u8 rq_num[0x18]; 2195 }; 2196 2197 struct mlx5_ifc_rq_vhca_bits { 2198 u8 reserved_at_0[0x8]; 2199 u8 rq_num[0x18]; 2200 u8 reserved_at_20[0x10]; 2201 u8 rq_vhca_id[0x10]; 2202 }; 2203 2204 struct mlx5_ifc_mac_address_layout_bits { 2205 u8 reserved_at_0[0x10]; 2206 u8 mac_addr_47_32[0x10]; 2207 2208 u8 mac_addr_31_0[0x20]; 2209 }; 2210 2211 struct mlx5_ifc_vlan_layout_bits { 2212 u8 reserved_at_0[0x14]; 2213 u8 vlan[0x0c]; 2214 2215 u8 reserved_at_20[0x20]; 2216 }; 2217 2218 struct mlx5_ifc_cong_control_r_roce_ecn_np_bits { 2219 u8 reserved_at_0[0xa0]; 2220 2221 u8 min_time_between_cnps[0x20]; 2222 2223 u8 reserved_at_c0[0x12]; 2224 u8 cnp_dscp[0x6]; 2225 u8 reserved_at_d8[0x4]; 2226 u8 cnp_prio_mode[0x1]; 2227 u8 cnp_802p_prio[0x3]; 2228 2229 u8 reserved_at_e0[0x720]; 2230 }; 2231 2232 struct mlx5_ifc_cong_control_r_roce_ecn_rp_bits { 2233 u8 reserved_at_0[0x60]; 2234 2235 u8 reserved_at_60[0x4]; 2236 u8 clamp_tgt_rate[0x1]; 2237 u8 reserved_at_65[0x3]; 2238 u8 clamp_tgt_rate_after_time_inc[0x1]; 2239 u8 reserved_at_69[0x17]; 2240 2241 u8 reserved_at_80[0x20]; 2242 2243 u8 rpg_time_reset[0x20]; 2244 2245 u8 rpg_byte_reset[0x20]; 2246 2247 u8 rpg_threshold[0x20]; 2248 2249 u8 rpg_max_rate[0x20]; 2250 2251 u8 rpg_ai_rate[0x20]; 2252 2253 u8 rpg_hai_rate[0x20]; 2254 2255 u8 rpg_gd[0x20]; 2256 2257 u8 rpg_min_dec_fac[0x20]; 2258 2259 u8 rpg_min_rate[0x20]; 2260 2261 u8 reserved_at_1c0[0xe0]; 2262 2263 u8 rate_to_set_on_first_cnp[0x20]; 2264 2265 u8 dce_tcp_g[0x20]; 2266 2267 u8 dce_tcp_rtt[0x20]; 2268 2269 u8 rate_reduce_monitor_period[0x20]; 2270 2271 u8 reserved_at_320[0x20]; 2272 2273 u8 initial_alpha_value[0x20]; 2274 2275 u8 reserved_at_360[0x4a0]; 2276 }; 2277 2278 struct mlx5_ifc_cong_control_r_roce_general_bits { 2279 u8 reserved_at_0[0x80]; 2280 2281 u8 reserved_at_80[0x10]; 2282 u8 rtt_resp_dscp_valid[0x1]; 2283 u8 reserved_at_91[0x9]; 2284 u8 rtt_resp_dscp[0x6]; 2285 2286 u8 reserved_at_a0[0x760]; 2287 }; 2288 2289 struct mlx5_ifc_cong_control_802_1qau_rp_bits { 2290 u8 reserved_at_0[0x80]; 2291 2292 u8 rppp_max_rps[0x20]; 2293 2294 u8 rpg_time_reset[0x20]; 2295 2296 u8 rpg_byte_reset[0x20]; 2297 2298 u8 rpg_threshold[0x20]; 2299 2300 u8 rpg_max_rate[0x20]; 2301 2302 u8 rpg_ai_rate[0x20]; 2303 2304 u8 rpg_hai_rate[0x20]; 2305 2306 u8 rpg_gd[0x20]; 2307 2308 u8 rpg_min_dec_fac[0x20]; 2309 2310 u8 rpg_min_rate[0x20]; 2311 2312 u8 reserved_at_1c0[0x640]; 2313 }; 2314 2315 enum { 2316 MLX5_RESIZE_FIELD_SELECT_RESIZE_FIELD_SELECT_LOG_CQ_SIZE = 0x1, 2317 MLX5_RESIZE_FIELD_SELECT_RESIZE_FIELD_SELECT_PAGE_OFFSET = 0x2, 2318 MLX5_RESIZE_FIELD_SELECT_RESIZE_FIELD_SELECT_LOG_PAGE_SIZE = 0x4, 2319 }; 2320 2321 struct mlx5_ifc_resize_field_select_bits { 2322 u8 resize_field_select[0x20]; 2323 }; 2324 2325 struct mlx5_ifc_resource_dump_bits { 2326 u8 more_dump[0x1]; 2327 u8 inline_dump[0x1]; 2328 u8 reserved_at_2[0xa]; 2329 u8 seq_num[0x4]; 2330 u8 segment_type[0x10]; 2331 2332 u8 reserved_at_20[0x10]; 2333 u8 vhca_id[0x10]; 2334 2335 u8 index1[0x20]; 2336 2337 u8 index2[0x20]; 2338 2339 u8 num_of_obj1[0x10]; 2340 u8 num_of_obj2[0x10]; 2341 2342 u8 reserved_at_a0[0x20]; 2343 2344 u8 device_opaque[0x40]; 2345 2346 u8 mkey[0x20]; 2347 2348 u8 size[0x20]; 2349 2350 u8 address[0x40]; 2351 2352 u8 inline_data[52][0x20]; 2353 }; 2354 2355 struct mlx5_ifc_resource_dump_menu_record_bits { 2356 u8 reserved_at_0[0x4]; 2357 u8 num_of_obj2_supports_active[0x1]; 2358 u8 num_of_obj2_supports_all[0x1]; 2359 u8 must_have_num_of_obj2[0x1]; 2360 u8 support_num_of_obj2[0x1]; 2361 u8 num_of_obj1_supports_active[0x1]; 2362 u8 num_of_obj1_supports_all[0x1]; 2363 u8 must_have_num_of_obj1[0x1]; 2364 u8 support_num_of_obj1[0x1]; 2365 u8 must_have_index2[0x1]; 2366 u8 support_index2[0x1]; 2367 u8 must_have_index1[0x1]; 2368 u8 support_index1[0x1]; 2369 u8 segment_type[0x10]; 2370 2371 u8 segment_name[4][0x20]; 2372 2373 u8 index1_name[4][0x20]; 2374 2375 u8 index2_name[4][0x20]; 2376 }; 2377 2378 struct mlx5_ifc_resource_dump_segment_header_bits { 2379 u8 length_dw[0x10]; 2380 u8 segment_type[0x10]; 2381 }; 2382 2383 struct mlx5_ifc_resource_dump_command_segment_bits { 2384 struct mlx5_ifc_resource_dump_segment_header_bits segment_header; 2385 2386 u8 segment_called[0x10]; 2387 u8 vhca_id[0x10]; 2388 2389 u8 index1[0x20]; 2390 2391 u8 index2[0x20]; 2392 2393 u8 num_of_obj1[0x10]; 2394 u8 num_of_obj2[0x10]; 2395 }; 2396 2397 struct mlx5_ifc_resource_dump_error_segment_bits { 2398 struct mlx5_ifc_resource_dump_segment_header_bits segment_header; 2399 2400 u8 reserved_at_20[0x10]; 2401 u8 syndrome_id[0x10]; 2402 2403 u8 reserved_at_40[0x40]; 2404 2405 u8 error[8][0x20]; 2406 }; 2407 2408 struct mlx5_ifc_resource_dump_info_segment_bits { 2409 struct mlx5_ifc_resource_dump_segment_header_bits segment_header; 2410 2411 u8 reserved_at_20[0x18]; 2412 u8 dump_version[0x8]; 2413 2414 u8 hw_version[0x20]; 2415 2416 u8 fw_version[0x20]; 2417 }; 2418 2419 struct mlx5_ifc_resource_dump_menu_segment_bits { 2420 struct mlx5_ifc_resource_dump_segment_header_bits segment_header; 2421 2422 u8 reserved_at_20[0x10]; 2423 u8 num_of_records[0x10]; 2424 2425 struct mlx5_ifc_resource_dump_menu_record_bits record[]; 2426 }; 2427 2428 struct mlx5_ifc_resource_dump_resource_segment_bits { 2429 struct mlx5_ifc_resource_dump_segment_header_bits segment_header; 2430 2431 u8 reserved_at_20[0x20]; 2432 2433 u8 index1[0x20]; 2434 2435 u8 index2[0x20]; 2436 2437 u8 payload[][0x20]; 2438 }; 2439 2440 struct mlx5_ifc_resource_dump_terminate_segment_bits { 2441 struct mlx5_ifc_resource_dump_segment_header_bits segment_header; 2442 }; 2443 2444 struct mlx5_ifc_menu_resource_dump_response_bits { 2445 struct mlx5_ifc_resource_dump_info_segment_bits info; 2446 struct mlx5_ifc_resource_dump_command_segment_bits cmd; 2447 struct mlx5_ifc_resource_dump_menu_segment_bits menu; 2448 struct mlx5_ifc_resource_dump_terminate_segment_bits terminate; 2449 }; 2450 2451 enum { 2452 MLX5_MODIFY_FIELD_SELECT_MODIFY_FIELD_SELECT_CQ_PERIOD = 0x1, 2453 MLX5_MODIFY_FIELD_SELECT_MODIFY_FIELD_SELECT_CQ_MAX_COUNT = 0x2, 2454 MLX5_MODIFY_FIELD_SELECT_MODIFY_FIELD_SELECT_OI = 0x4, 2455 MLX5_MODIFY_FIELD_SELECT_MODIFY_FIELD_SELECT_C_EQN = 0x8, 2456 }; 2457 2458 struct mlx5_ifc_modify_field_select_bits { 2459 u8 modify_field_select[0x20]; 2460 }; 2461 2462 struct mlx5_ifc_field_select_r_roce_np_bits { 2463 u8 field_select_r_roce_np[0x20]; 2464 }; 2465 2466 struct mlx5_ifc_field_select_r_roce_rp_bits { 2467 u8 field_select_r_roce_rp[0x20]; 2468 }; 2469 2470 enum { 2471 MLX5_FIELD_SELECT_802_1QAU_RP_FIELD_SELECT_8021QAURP_RPPP_MAX_RPS = 0x4, 2472 MLX5_FIELD_SELECT_802_1QAU_RP_FIELD_SELECT_8021QAURP_RPG_TIME_RESET = 0x8, 2473 MLX5_FIELD_SELECT_802_1QAU_RP_FIELD_SELECT_8021QAURP_RPG_BYTE_RESET = 0x10, 2474 MLX5_FIELD_SELECT_802_1QAU_RP_FIELD_SELECT_8021QAURP_RPG_THRESHOLD = 0x20, 2475 MLX5_FIELD_SELECT_802_1QAU_RP_FIELD_SELECT_8021QAURP_RPG_MAX_RATE = 0x40, 2476 MLX5_FIELD_SELECT_802_1QAU_RP_FIELD_SELECT_8021QAURP_RPG_AI_RATE = 0x80, 2477 MLX5_FIELD_SELECT_802_1QAU_RP_FIELD_SELECT_8021QAURP_RPG_HAI_RATE = 0x100, 2478 MLX5_FIELD_SELECT_802_1QAU_RP_FIELD_SELECT_8021QAURP_RPG_GD = 0x200, 2479 MLX5_FIELD_SELECT_802_1QAU_RP_FIELD_SELECT_8021QAURP_RPG_MIN_DEC_FAC = 0x400, 2480 MLX5_FIELD_SELECT_802_1QAU_RP_FIELD_SELECT_8021QAURP_RPG_MIN_RATE = 0x800, 2481 }; 2482 2483 struct mlx5_ifc_field_select_802_1qau_rp_bits { 2484 u8 field_select_8021qaurp[0x20]; 2485 }; 2486 2487 struct mlx5_ifc_phys_layer_cntrs_bits { 2488 u8 time_since_last_clear_high[0x20]; 2489 2490 u8 time_since_last_clear_low[0x20]; 2491 2492 u8 symbol_errors_high[0x20]; 2493 2494 u8 symbol_errors_low[0x20]; 2495 2496 u8 sync_headers_errors_high[0x20]; 2497 2498 u8 sync_headers_errors_low[0x20]; 2499 2500 u8 edpl_bip_errors_lane0_high[0x20]; 2501 2502 u8 edpl_bip_errors_lane0_low[0x20]; 2503 2504 u8 edpl_bip_errors_lane1_high[0x20]; 2505 2506 u8 edpl_bip_errors_lane1_low[0x20]; 2507 2508 u8 edpl_bip_errors_lane2_high[0x20]; 2509 2510 u8 edpl_bip_errors_lane2_low[0x20]; 2511 2512 u8 edpl_bip_errors_lane3_high[0x20]; 2513 2514 u8 edpl_bip_errors_lane3_low[0x20]; 2515 2516 u8 fc_fec_corrected_blocks_lane0_high[0x20]; 2517 2518 u8 fc_fec_corrected_blocks_lane0_low[0x20]; 2519 2520 u8 fc_fec_corrected_blocks_lane1_high[0x20]; 2521 2522 u8 fc_fec_corrected_blocks_lane1_low[0x20]; 2523 2524 u8 fc_fec_corrected_blocks_lane2_high[0x20]; 2525 2526 u8 fc_fec_corrected_blocks_lane2_low[0x20]; 2527 2528 u8 fc_fec_corrected_blocks_lane3_high[0x20]; 2529 2530 u8 fc_fec_corrected_blocks_lane3_low[0x20]; 2531 2532 u8 fc_fec_uncorrectable_blocks_lane0_high[0x20]; 2533 2534 u8 fc_fec_uncorrectable_blocks_lane0_low[0x20]; 2535 2536 u8 fc_fec_uncorrectable_blocks_lane1_high[0x20]; 2537 2538 u8 fc_fec_uncorrectable_blocks_lane1_low[0x20]; 2539 2540 u8 fc_fec_uncorrectable_blocks_lane2_high[0x20]; 2541 2542 u8 fc_fec_uncorrectable_blocks_lane2_low[0x20]; 2543 2544 u8 fc_fec_uncorrectable_blocks_lane3_high[0x20]; 2545 2546 u8 fc_fec_uncorrectable_blocks_lane3_low[0x20]; 2547 2548 u8 rs_fec_corrected_blocks_high[0x20]; 2549 2550 u8 rs_fec_corrected_blocks_low[0x20]; 2551 2552 u8 rs_fec_uncorrectable_blocks_high[0x20]; 2553 2554 u8 rs_fec_uncorrectable_blocks_low[0x20]; 2555 2556 u8 rs_fec_no_errors_blocks_high[0x20]; 2557 2558 u8 rs_fec_no_errors_blocks_low[0x20]; 2559 2560 u8 rs_fec_single_error_blocks_high[0x20]; 2561 2562 u8 rs_fec_single_error_blocks_low[0x20]; 2563 2564 u8 rs_fec_corrected_symbols_total_high[0x20]; 2565 2566 u8 rs_fec_corrected_symbols_total_low[0x20]; 2567 2568 u8 rs_fec_corrected_symbols_lane0_high[0x20]; 2569 2570 u8 rs_fec_corrected_symbols_lane0_low[0x20]; 2571 2572 u8 rs_fec_corrected_symbols_lane1_high[0x20]; 2573 2574 u8 rs_fec_corrected_symbols_lane1_low[0x20]; 2575 2576 u8 rs_fec_corrected_symbols_lane2_high[0x20]; 2577 2578 u8 rs_fec_corrected_symbols_lane2_low[0x20]; 2579 2580 u8 rs_fec_corrected_symbols_lane3_high[0x20]; 2581 2582 u8 rs_fec_corrected_symbols_lane3_low[0x20]; 2583 2584 u8 link_down_events[0x20]; 2585 2586 u8 successful_recovery_events[0x20]; 2587 2588 u8 reserved_at_640[0x180]; 2589 }; 2590 2591 struct mlx5_ifc_phys_layer_statistical_cntrs_bits { 2592 u8 time_since_last_clear_high[0x20]; 2593 2594 u8 time_since_last_clear_low[0x20]; 2595 2596 u8 phy_received_bits_high[0x20]; 2597 2598 u8 phy_received_bits_low[0x20]; 2599 2600 u8 phy_symbol_errors_high[0x20]; 2601 2602 u8 phy_symbol_errors_low[0x20]; 2603 2604 u8 phy_corrected_bits_high[0x20]; 2605 2606 u8 phy_corrected_bits_low[0x20]; 2607 2608 u8 phy_corrected_bits_lane0_high[0x20]; 2609 2610 u8 phy_corrected_bits_lane0_low[0x20]; 2611 2612 u8 phy_corrected_bits_lane1_high[0x20]; 2613 2614 u8 phy_corrected_bits_lane1_low[0x20]; 2615 2616 u8 phy_corrected_bits_lane2_high[0x20]; 2617 2618 u8 phy_corrected_bits_lane2_low[0x20]; 2619 2620 u8 phy_corrected_bits_lane3_high[0x20]; 2621 2622 u8 phy_corrected_bits_lane3_low[0x20]; 2623 2624 u8 reserved_at_200[0x5c0]; 2625 }; 2626 2627 struct mlx5_ifc_ib_port_cntrs_grp_data_layout_bits { 2628 u8 symbol_error_counter[0x10]; 2629 2630 u8 link_error_recovery_counter[0x8]; 2631 2632 u8 link_downed_counter[0x8]; 2633 2634 u8 port_rcv_errors[0x10]; 2635 2636 u8 port_rcv_remote_physical_errors[0x10]; 2637 2638 u8 port_rcv_switch_relay_errors[0x10]; 2639 2640 u8 port_xmit_discards[0x10]; 2641 2642 u8 port_xmit_constraint_errors[0x8]; 2643 2644 u8 port_rcv_constraint_errors[0x8]; 2645 2646 u8 reserved_at_70[0x8]; 2647 2648 u8 link_overrun_errors[0x8]; 2649 2650 u8 reserved_at_80[0x10]; 2651 2652 u8 vl_15_dropped[0x10]; 2653 2654 u8 reserved_at_a0[0x80]; 2655 2656 u8 port_xmit_wait[0x20]; 2657 }; 2658 2659 struct mlx5_ifc_eth_per_tc_prio_grp_data_layout_bits { 2660 u8 transmit_queue_high[0x20]; 2661 2662 u8 transmit_queue_low[0x20]; 2663 2664 u8 no_buffer_discard_uc_high[0x20]; 2665 2666 u8 no_buffer_discard_uc_low[0x20]; 2667 2668 u8 reserved_at_80[0x740]; 2669 }; 2670 2671 struct mlx5_ifc_eth_per_tc_congest_prio_grp_data_layout_bits { 2672 u8 wred_discard_high[0x20]; 2673 2674 u8 wred_discard_low[0x20]; 2675 2676 u8 ecn_marked_tc_high[0x20]; 2677 2678 u8 ecn_marked_tc_low[0x20]; 2679 2680 u8 reserved_at_80[0x740]; 2681 }; 2682 2683 struct mlx5_ifc_eth_per_prio_grp_data_layout_bits { 2684 u8 rx_octets_high[0x20]; 2685 2686 u8 rx_octets_low[0x20]; 2687 2688 u8 reserved_at_40[0xc0]; 2689 2690 u8 rx_frames_high[0x20]; 2691 2692 u8 rx_frames_low[0x20]; 2693 2694 u8 tx_octets_high[0x20]; 2695 2696 u8 tx_octets_low[0x20]; 2697 2698 u8 reserved_at_180[0xc0]; 2699 2700 u8 tx_frames_high[0x20]; 2701 2702 u8 tx_frames_low[0x20]; 2703 2704 u8 rx_pause_high[0x20]; 2705 2706 u8 rx_pause_low[0x20]; 2707 2708 u8 rx_pause_duration_high[0x20]; 2709 2710 u8 rx_pause_duration_low[0x20]; 2711 2712 u8 tx_pause_high[0x20]; 2713 2714 u8 tx_pause_low[0x20]; 2715 2716 u8 tx_pause_duration_high[0x20]; 2717 2718 u8 tx_pause_duration_low[0x20]; 2719 2720 u8 rx_pause_transition_high[0x20]; 2721 2722 u8 rx_pause_transition_low[0x20]; 2723 2724 u8 rx_discards_high[0x20]; 2725 2726 u8 rx_discards_low[0x20]; 2727 2728 u8 device_stall_minor_watermark_cnt_high[0x20]; 2729 2730 u8 device_stall_minor_watermark_cnt_low[0x20]; 2731 2732 u8 device_stall_critical_watermark_cnt_high[0x20]; 2733 2734 u8 device_stall_critical_watermark_cnt_low[0x20]; 2735 2736 u8 reserved_at_480[0x340]; 2737 }; 2738 2739 struct mlx5_ifc_eth_extended_cntrs_grp_data_layout_bits { 2740 u8 port_transmit_wait_high[0x20]; 2741 2742 u8 port_transmit_wait_low[0x20]; 2743 2744 u8 reserved_at_40[0x100]; 2745 2746 u8 rx_buffer_almost_full_high[0x20]; 2747 2748 u8 rx_buffer_almost_full_low[0x20]; 2749 2750 u8 rx_buffer_full_high[0x20]; 2751 2752 u8 rx_buffer_full_low[0x20]; 2753 2754 u8 rx_icrc_encapsulated_high[0x20]; 2755 2756 u8 rx_icrc_encapsulated_low[0x20]; 2757 2758 u8 reserved_at_200[0x5c0]; 2759 }; 2760 2761 struct mlx5_ifc_eth_3635_cntrs_grp_data_layout_bits { 2762 u8 dot3stats_alignment_errors_high[0x20]; 2763 2764 u8 dot3stats_alignment_errors_low[0x20]; 2765 2766 u8 dot3stats_fcs_errors_high[0x20]; 2767 2768 u8 dot3stats_fcs_errors_low[0x20]; 2769 2770 u8 dot3stats_single_collision_frames_high[0x20]; 2771 2772 u8 dot3stats_single_collision_frames_low[0x20]; 2773 2774 u8 dot3stats_multiple_collision_frames_high[0x20]; 2775 2776 u8 dot3stats_multiple_collision_frames_low[0x20]; 2777 2778 u8 dot3stats_sqe_test_errors_high[0x20]; 2779 2780 u8 dot3stats_sqe_test_errors_low[0x20]; 2781 2782 u8 dot3stats_deferred_transmissions_high[0x20]; 2783 2784 u8 dot3stats_deferred_transmissions_low[0x20]; 2785 2786 u8 dot3stats_late_collisions_high[0x20]; 2787 2788 u8 dot3stats_late_collisions_low[0x20]; 2789 2790 u8 dot3stats_excessive_collisions_high[0x20]; 2791 2792 u8 dot3stats_excessive_collisions_low[0x20]; 2793 2794 u8 dot3stats_internal_mac_transmit_errors_high[0x20]; 2795 2796 u8 dot3stats_internal_mac_transmit_errors_low[0x20]; 2797 2798 u8 dot3stats_carrier_sense_errors_high[0x20]; 2799 2800 u8 dot3stats_carrier_sense_errors_low[0x20]; 2801 2802 u8 dot3stats_frame_too_longs_high[0x20]; 2803 2804 u8 dot3stats_frame_too_longs_low[0x20]; 2805 2806 u8 dot3stats_internal_mac_receive_errors_high[0x20]; 2807 2808 u8 dot3stats_internal_mac_receive_errors_low[0x20]; 2809 2810 u8 dot3stats_symbol_errors_high[0x20]; 2811 2812 u8 dot3stats_symbol_errors_low[0x20]; 2813 2814 u8 dot3control_in_unknown_opcodes_high[0x20]; 2815 2816 u8 dot3control_in_unknown_opcodes_low[0x20]; 2817 2818 u8 dot3in_pause_frames_high[0x20]; 2819 2820 u8 dot3in_pause_frames_low[0x20]; 2821 2822 u8 dot3out_pause_frames_high[0x20]; 2823 2824 u8 dot3out_pause_frames_low[0x20]; 2825 2826 u8 reserved_at_400[0x3c0]; 2827 }; 2828 2829 struct mlx5_ifc_eth_2819_cntrs_grp_data_layout_bits { 2830 u8 ether_stats_drop_events_high[0x20]; 2831 2832 u8 ether_stats_drop_events_low[0x20]; 2833 2834 u8 ether_stats_octets_high[0x20]; 2835 2836 u8 ether_stats_octets_low[0x20]; 2837 2838 u8 ether_stats_pkts_high[0x20]; 2839 2840 u8 ether_stats_pkts_low[0x20]; 2841 2842 u8 ether_stats_broadcast_pkts_high[0x20]; 2843 2844 u8 ether_stats_broadcast_pkts_low[0x20]; 2845 2846 u8 ether_stats_multicast_pkts_high[0x20]; 2847 2848 u8 ether_stats_multicast_pkts_low[0x20]; 2849 2850 u8 ether_stats_crc_align_errors_high[0x20]; 2851 2852 u8 ether_stats_crc_align_errors_low[0x20]; 2853 2854 u8 ether_stats_undersize_pkts_high[0x20]; 2855 2856 u8 ether_stats_undersize_pkts_low[0x20]; 2857 2858 u8 ether_stats_oversize_pkts_high[0x20]; 2859 2860 u8 ether_stats_oversize_pkts_low[0x20]; 2861 2862 u8 ether_stats_fragments_high[0x20]; 2863 2864 u8 ether_stats_fragments_low[0x20]; 2865 2866 u8 ether_stats_jabbers_high[0x20]; 2867 2868 u8 ether_stats_jabbers_low[0x20]; 2869 2870 u8 ether_stats_collisions_high[0x20]; 2871 2872 u8 ether_stats_collisions_low[0x20]; 2873 2874 u8 ether_stats_pkts64octets_high[0x20]; 2875 2876 u8 ether_stats_pkts64octets_low[0x20]; 2877 2878 u8 ether_stats_pkts65to127octets_high[0x20]; 2879 2880 u8 ether_stats_pkts65to127octets_low[0x20]; 2881 2882 u8 ether_stats_pkts128to255octets_high[0x20]; 2883 2884 u8 ether_stats_pkts128to255octets_low[0x20]; 2885 2886 u8 ether_stats_pkts256to511octets_high[0x20]; 2887 2888 u8 ether_stats_pkts256to511octets_low[0x20]; 2889 2890 u8 ether_stats_pkts512to1023octets_high[0x20]; 2891 2892 u8 ether_stats_pkts512to1023octets_low[0x20]; 2893 2894 u8 ether_stats_pkts1024to1518octets_high[0x20]; 2895 2896 u8 ether_stats_pkts1024to1518octets_low[0x20]; 2897 2898 u8 ether_stats_pkts1519to2047octets_high[0x20]; 2899 2900 u8 ether_stats_pkts1519to2047octets_low[0x20]; 2901 2902 u8 ether_stats_pkts2048to4095octets_high[0x20]; 2903 2904 u8 ether_stats_pkts2048to4095octets_low[0x20]; 2905 2906 u8 ether_stats_pkts4096to8191octets_high[0x20]; 2907 2908 u8 ether_stats_pkts4096to8191octets_low[0x20]; 2909 2910 u8 ether_stats_pkts8192to10239octets_high[0x20]; 2911 2912 u8 ether_stats_pkts8192to10239octets_low[0x20]; 2913 2914 u8 reserved_at_540[0x280]; 2915 }; 2916 2917 struct mlx5_ifc_eth_2863_cntrs_grp_data_layout_bits { 2918 u8 if_in_octets_high[0x20]; 2919 2920 u8 if_in_octets_low[0x20]; 2921 2922 u8 if_in_ucast_pkts_high[0x20]; 2923 2924 u8 if_in_ucast_pkts_low[0x20]; 2925 2926 u8 if_in_discards_high[0x20]; 2927 2928 u8 if_in_discards_low[0x20]; 2929 2930 u8 if_in_errors_high[0x20]; 2931 2932 u8 if_in_errors_low[0x20]; 2933 2934 u8 if_in_unknown_protos_high[0x20]; 2935 2936 u8 if_in_unknown_protos_low[0x20]; 2937 2938 u8 if_out_octets_high[0x20]; 2939 2940 u8 if_out_octets_low[0x20]; 2941 2942 u8 if_out_ucast_pkts_high[0x20]; 2943 2944 u8 if_out_ucast_pkts_low[0x20]; 2945 2946 u8 if_out_discards_high[0x20]; 2947 2948 u8 if_out_discards_low[0x20]; 2949 2950 u8 if_out_errors_high[0x20]; 2951 2952 u8 if_out_errors_low[0x20]; 2953 2954 u8 if_in_multicast_pkts_high[0x20]; 2955 2956 u8 if_in_multicast_pkts_low[0x20]; 2957 2958 u8 if_in_broadcast_pkts_high[0x20]; 2959 2960 u8 if_in_broadcast_pkts_low[0x20]; 2961 2962 u8 if_out_multicast_pkts_high[0x20]; 2963 2964 u8 if_out_multicast_pkts_low[0x20]; 2965 2966 u8 if_out_broadcast_pkts_high[0x20]; 2967 2968 u8 if_out_broadcast_pkts_low[0x20]; 2969 2970 u8 reserved_at_340[0x480]; 2971 }; 2972 2973 struct mlx5_ifc_eth_802_3_cntrs_grp_data_layout_bits { 2974 u8 a_frames_transmitted_ok_high[0x20]; 2975 2976 u8 a_frames_transmitted_ok_low[0x20]; 2977 2978 u8 a_frames_received_ok_high[0x20]; 2979 2980 u8 a_frames_received_ok_low[0x20]; 2981 2982 u8 a_frame_check_sequence_errors_high[0x20]; 2983 2984 u8 a_frame_check_sequence_errors_low[0x20]; 2985 2986 u8 a_alignment_errors_high[0x20]; 2987 2988 u8 a_alignment_errors_low[0x20]; 2989 2990 u8 a_octets_transmitted_ok_high[0x20]; 2991 2992 u8 a_octets_transmitted_ok_low[0x20]; 2993 2994 u8 a_octets_received_ok_high[0x20]; 2995 2996 u8 a_octets_received_ok_low[0x20]; 2997 2998 u8 a_multicast_frames_xmitted_ok_high[0x20]; 2999 3000 u8 a_multicast_frames_xmitted_ok_low[0x20]; 3001 3002 u8 a_broadcast_frames_xmitted_ok_high[0x20]; 3003 3004 u8 a_broadcast_frames_xmitted_ok_low[0x20]; 3005 3006 u8 a_multicast_frames_received_ok_high[0x20]; 3007 3008 u8 a_multicast_frames_received_ok_low[0x20]; 3009 3010 u8 a_broadcast_frames_received_ok_high[0x20]; 3011 3012 u8 a_broadcast_frames_received_ok_low[0x20]; 3013 3014 u8 a_in_range_length_errors_high[0x20]; 3015 3016 u8 a_in_range_length_errors_low[0x20]; 3017 3018 u8 a_out_of_range_length_field_high[0x20]; 3019 3020 u8 a_out_of_range_length_field_low[0x20]; 3021 3022 u8 a_frame_too_long_errors_high[0x20]; 3023 3024 u8 a_frame_too_long_errors_low[0x20]; 3025 3026 u8 a_symbol_error_during_carrier_high[0x20]; 3027 3028 u8 a_symbol_error_during_carrier_low[0x20]; 3029 3030 u8 a_mac_control_frames_transmitted_high[0x20]; 3031 3032 u8 a_mac_control_frames_transmitted_low[0x20]; 3033 3034 u8 a_mac_control_frames_received_high[0x20]; 3035 3036 u8 a_mac_control_frames_received_low[0x20]; 3037 3038 u8 a_unsupported_opcodes_received_high[0x20]; 3039 3040 u8 a_unsupported_opcodes_received_low[0x20]; 3041 3042 u8 a_pause_mac_ctrl_frames_received_high[0x20]; 3043 3044 u8 a_pause_mac_ctrl_frames_received_low[0x20]; 3045 3046 u8 a_pause_mac_ctrl_frames_transmitted_high[0x20]; 3047 3048 u8 a_pause_mac_ctrl_frames_transmitted_low[0x20]; 3049 3050 u8 reserved_at_4c0[0x300]; 3051 }; 3052 3053 struct mlx5_ifc_pcie_perf_cntrs_grp_data_layout_bits { 3054 u8 life_time_counter_high[0x20]; 3055 3056 u8 life_time_counter_low[0x20]; 3057 3058 u8 rx_errors[0x20]; 3059 3060 u8 tx_errors[0x20]; 3061 3062 u8 l0_to_recovery_eieos[0x20]; 3063 3064 u8 l0_to_recovery_ts[0x20]; 3065 3066 u8 l0_to_recovery_framing[0x20]; 3067 3068 u8 l0_to_recovery_retrain[0x20]; 3069 3070 u8 crc_error_dllp[0x20]; 3071 3072 u8 crc_error_tlp[0x20]; 3073 3074 u8 tx_overflow_buffer_pkt_high[0x20]; 3075 3076 u8 tx_overflow_buffer_pkt_low[0x20]; 3077 3078 u8 outbound_stalled_reads[0x20]; 3079 3080 u8 outbound_stalled_writes[0x20]; 3081 3082 u8 outbound_stalled_reads_events[0x20]; 3083 3084 u8 outbound_stalled_writes_events[0x20]; 3085 3086 u8 reserved_at_200[0x5c0]; 3087 }; 3088 3089 struct mlx5_ifc_cmd_inter_comp_event_bits { 3090 u8 command_completion_vector[0x20]; 3091 3092 u8 reserved_at_20[0xc0]; 3093 }; 3094 3095 struct mlx5_ifc_stall_vl_event_bits { 3096 u8 reserved_at_0[0x18]; 3097 u8 port_num[0x1]; 3098 u8 reserved_at_19[0x3]; 3099 u8 vl[0x4]; 3100 3101 u8 reserved_at_20[0xa0]; 3102 }; 3103 3104 struct mlx5_ifc_db_bf_congestion_event_bits { 3105 u8 event_subtype[0x8]; 3106 u8 reserved_at_8[0x8]; 3107 u8 congestion_level[0x8]; 3108 u8 reserved_at_18[0x8]; 3109 3110 u8 reserved_at_20[0xa0]; 3111 }; 3112 3113 struct mlx5_ifc_gpio_event_bits { 3114 u8 reserved_at_0[0x60]; 3115 3116 u8 gpio_event_hi[0x20]; 3117 3118 u8 gpio_event_lo[0x20]; 3119 3120 u8 reserved_at_a0[0x40]; 3121 }; 3122 3123 struct mlx5_ifc_port_state_change_event_bits { 3124 u8 reserved_at_0[0x40]; 3125 3126 u8 port_num[0x4]; 3127 u8 reserved_at_44[0x1c]; 3128 3129 u8 reserved_at_60[0x80]; 3130 }; 3131 3132 struct mlx5_ifc_dropped_packet_logged_bits { 3133 u8 reserved_at_0[0xe0]; 3134 }; 3135 3136 struct mlx5_ifc_default_timeout_bits { 3137 u8 to_multiplier[0x3]; 3138 u8 reserved_at_3[0x9]; 3139 u8 to_value[0x14]; 3140 }; 3141 3142 struct mlx5_ifc_dtor_reg_bits { 3143 u8 reserved_at_0[0x20]; 3144 3145 struct mlx5_ifc_default_timeout_bits pcie_toggle_to; 3146 3147 u8 reserved_at_40[0x60]; 3148 3149 struct mlx5_ifc_default_timeout_bits health_poll_to; 3150 3151 struct mlx5_ifc_default_timeout_bits full_crdump_to; 3152 3153 struct mlx5_ifc_default_timeout_bits fw_reset_to; 3154 3155 struct mlx5_ifc_default_timeout_bits flush_on_err_to; 3156 3157 struct mlx5_ifc_default_timeout_bits pci_sync_update_to; 3158 3159 struct mlx5_ifc_default_timeout_bits tear_down_to; 3160 3161 struct mlx5_ifc_default_timeout_bits fsm_reactivate_to; 3162 3163 struct mlx5_ifc_default_timeout_bits reclaim_pages_to; 3164 3165 struct mlx5_ifc_default_timeout_bits reclaim_vfs_pages_to; 3166 3167 struct mlx5_ifc_default_timeout_bits reset_unload_to; 3168 3169 u8 reserved_at_1c0[0x20]; 3170 }; 3171 3172 enum { 3173 MLX5_CQ_ERROR_SYNDROME_CQ_OVERRUN = 0x1, 3174 MLX5_CQ_ERROR_SYNDROME_CQ_ACCESS_VIOLATION_ERROR = 0x2, 3175 }; 3176 3177 struct mlx5_ifc_cq_error_bits { 3178 u8 reserved_at_0[0x8]; 3179 u8 cqn[0x18]; 3180 3181 u8 reserved_at_20[0x20]; 3182 3183 u8 reserved_at_40[0x18]; 3184 u8 syndrome[0x8]; 3185 3186 u8 reserved_at_60[0x80]; 3187 }; 3188 3189 struct mlx5_ifc_rdma_page_fault_event_bits { 3190 u8 bytes_committed[0x20]; 3191 3192 u8 r_key[0x20]; 3193 3194 u8 reserved_at_40[0x10]; 3195 u8 packet_len[0x10]; 3196 3197 u8 rdma_op_len[0x20]; 3198 3199 u8 rdma_va[0x40]; 3200 3201 u8 reserved_at_c0[0x5]; 3202 u8 rdma[0x1]; 3203 u8 write[0x1]; 3204 u8 requestor[0x1]; 3205 u8 qp_number[0x18]; 3206 }; 3207 3208 struct mlx5_ifc_wqe_associated_page_fault_event_bits { 3209 u8 bytes_committed[0x20]; 3210 3211 u8 reserved_at_20[0x10]; 3212 u8 wqe_index[0x10]; 3213 3214 u8 reserved_at_40[0x10]; 3215 u8 len[0x10]; 3216 3217 u8 reserved_at_60[0x60]; 3218 3219 u8 reserved_at_c0[0x5]; 3220 u8 rdma[0x1]; 3221 u8 write_read[0x1]; 3222 u8 requestor[0x1]; 3223 u8 qpn[0x18]; 3224 }; 3225 3226 struct mlx5_ifc_qp_events_bits { 3227 u8 reserved_at_0[0xa0]; 3228 3229 u8 type[0x8]; 3230 u8 reserved_at_a8[0x18]; 3231 3232 u8 reserved_at_c0[0x8]; 3233 u8 qpn_rqn_sqn[0x18]; 3234 }; 3235 3236 struct mlx5_ifc_dct_events_bits { 3237 u8 reserved_at_0[0xc0]; 3238 3239 u8 reserved_at_c0[0x8]; 3240 u8 dct_number[0x18]; 3241 }; 3242 3243 struct mlx5_ifc_comp_event_bits { 3244 u8 reserved_at_0[0xc0]; 3245 3246 u8 reserved_at_c0[0x8]; 3247 u8 cq_number[0x18]; 3248 }; 3249 3250 enum { 3251 MLX5_QPC_STATE_RST = 0x0, 3252 MLX5_QPC_STATE_INIT = 0x1, 3253 MLX5_QPC_STATE_RTR = 0x2, 3254 MLX5_QPC_STATE_RTS = 0x3, 3255 MLX5_QPC_STATE_SQER = 0x4, 3256 MLX5_QPC_STATE_ERR = 0x6, 3257 MLX5_QPC_STATE_SQD = 0x7, 3258 MLX5_QPC_STATE_SUSPENDED = 0x9, 3259 }; 3260 3261 enum { 3262 MLX5_QPC_ST_RC = 0x0, 3263 MLX5_QPC_ST_UC = 0x1, 3264 MLX5_QPC_ST_UD = 0x2, 3265 MLX5_QPC_ST_XRC = 0x3, 3266 MLX5_QPC_ST_DCI = 0x5, 3267 MLX5_QPC_ST_QP0 = 0x7, 3268 MLX5_QPC_ST_QP1 = 0x8, 3269 MLX5_QPC_ST_RAW_DATAGRAM = 0x9, 3270 MLX5_QPC_ST_REG_UMR = 0xc, 3271 }; 3272 3273 enum { 3274 MLX5_QPC_PM_STATE_ARMED = 0x0, 3275 MLX5_QPC_PM_STATE_REARM = 0x1, 3276 MLX5_QPC_PM_STATE_RESERVED = 0x2, 3277 MLX5_QPC_PM_STATE_MIGRATED = 0x3, 3278 }; 3279 3280 enum { 3281 MLX5_QPC_OFFLOAD_TYPE_RNDV = 0x1, 3282 }; 3283 3284 enum { 3285 MLX5_QPC_END_PADDING_MODE_SCATTER_AS_IS = 0x0, 3286 MLX5_QPC_END_PADDING_MODE_PAD_TO_CACHE_LINE_ALIGNMENT = 0x1, 3287 }; 3288 3289 enum { 3290 MLX5_QPC_MTU_256_BYTES = 0x1, 3291 MLX5_QPC_MTU_512_BYTES = 0x2, 3292 MLX5_QPC_MTU_1K_BYTES = 0x3, 3293 MLX5_QPC_MTU_2K_BYTES = 0x4, 3294 MLX5_QPC_MTU_4K_BYTES = 0x5, 3295 MLX5_QPC_MTU_RAW_ETHERNET_QP = 0x7, 3296 }; 3297 3298 enum { 3299 MLX5_QPC_ATOMIC_MODE_IB_SPEC = 0x1, 3300 MLX5_QPC_ATOMIC_MODE_ONLY_8B = 0x2, 3301 MLX5_QPC_ATOMIC_MODE_UP_TO_8B = 0x3, 3302 MLX5_QPC_ATOMIC_MODE_UP_TO_16B = 0x4, 3303 MLX5_QPC_ATOMIC_MODE_UP_TO_32B = 0x5, 3304 MLX5_QPC_ATOMIC_MODE_UP_TO_64B = 0x6, 3305 MLX5_QPC_ATOMIC_MODE_UP_TO_128B = 0x7, 3306 MLX5_QPC_ATOMIC_MODE_UP_TO_256B = 0x8, 3307 }; 3308 3309 enum { 3310 MLX5_QPC_CS_REQ_DISABLE = 0x0, 3311 MLX5_QPC_CS_REQ_UP_TO_32B = 0x11, 3312 MLX5_QPC_CS_REQ_UP_TO_64B = 0x22, 3313 }; 3314 3315 enum { 3316 MLX5_QPC_CS_RES_DISABLE = 0x0, 3317 MLX5_QPC_CS_RES_UP_TO_32B = 0x1, 3318 MLX5_QPC_CS_RES_UP_TO_64B = 0x2, 3319 }; 3320 3321 enum { 3322 MLX5_TIMESTAMP_FORMAT_FREE_RUNNING = 0x0, 3323 MLX5_TIMESTAMP_FORMAT_DEFAULT = 0x1, 3324 MLX5_TIMESTAMP_FORMAT_REAL_TIME = 0x2, 3325 }; 3326 3327 struct mlx5_ifc_qpc_bits { 3328 u8 state[0x4]; 3329 u8 lag_tx_port_affinity[0x4]; 3330 u8 st[0x8]; 3331 u8 reserved_at_10[0x2]; 3332 u8 isolate_vl_tc[0x1]; 3333 u8 pm_state[0x2]; 3334 u8 reserved_at_15[0x1]; 3335 u8 req_e2e_credit_mode[0x2]; 3336 u8 offload_type[0x4]; 3337 u8 end_padding_mode[0x2]; 3338 u8 reserved_at_1e[0x2]; 3339 3340 u8 wq_signature[0x1]; 3341 u8 block_lb_mc[0x1]; 3342 u8 atomic_like_write_en[0x1]; 3343 u8 latency_sensitive[0x1]; 3344 u8 reserved_at_24[0x1]; 3345 u8 drain_sigerr[0x1]; 3346 u8 reserved_at_26[0x2]; 3347 u8 pd[0x18]; 3348 3349 u8 mtu[0x3]; 3350 u8 log_msg_max[0x5]; 3351 u8 reserved_at_48[0x1]; 3352 u8 log_rq_size[0x4]; 3353 u8 log_rq_stride[0x3]; 3354 u8 no_sq[0x1]; 3355 u8 log_sq_size[0x4]; 3356 u8 reserved_at_55[0x1]; 3357 u8 retry_mode[0x2]; 3358 u8 ts_format[0x2]; 3359 u8 reserved_at_5a[0x1]; 3360 u8 rlky[0x1]; 3361 u8 ulp_stateless_offload_mode[0x4]; 3362 3363 u8 counter_set_id[0x8]; 3364 u8 uar_page[0x18]; 3365 3366 u8 reserved_at_80[0x8]; 3367 u8 user_index[0x18]; 3368 3369 u8 reserved_at_a0[0x3]; 3370 u8 log_page_size[0x5]; 3371 u8 remote_qpn[0x18]; 3372 3373 struct mlx5_ifc_ads_bits primary_address_path; 3374 3375 struct mlx5_ifc_ads_bits secondary_address_path; 3376 3377 u8 log_ack_req_freq[0x4]; 3378 u8 reserved_at_384[0x4]; 3379 u8 log_sra_max[0x3]; 3380 u8 reserved_at_38b[0x2]; 3381 u8 retry_count[0x3]; 3382 u8 rnr_retry[0x3]; 3383 u8 reserved_at_393[0x1]; 3384 u8 fre[0x1]; 3385 u8 cur_rnr_retry[0x3]; 3386 u8 cur_retry_count[0x3]; 3387 u8 reserved_at_39b[0x5]; 3388 3389 u8 reserved_at_3a0[0x20]; 3390 3391 u8 reserved_at_3c0[0x8]; 3392 u8 next_send_psn[0x18]; 3393 3394 u8 reserved_at_3e0[0x3]; 3395 u8 log_num_dci_stream_channels[0x5]; 3396 u8 cqn_snd[0x18]; 3397 3398 u8 reserved_at_400[0x3]; 3399 u8 log_num_dci_errored_streams[0x5]; 3400 u8 deth_sqpn[0x18]; 3401 3402 u8 reserved_at_420[0x20]; 3403 3404 u8 reserved_at_440[0x8]; 3405 u8 last_acked_psn[0x18]; 3406 3407 u8 reserved_at_460[0x8]; 3408 u8 ssn[0x18]; 3409 3410 u8 reserved_at_480[0x8]; 3411 u8 log_rra_max[0x3]; 3412 u8 reserved_at_48b[0x1]; 3413 u8 atomic_mode[0x4]; 3414 u8 rre[0x1]; 3415 u8 rwe[0x1]; 3416 u8 rae[0x1]; 3417 u8 reserved_at_493[0x1]; 3418 u8 page_offset[0x6]; 3419 u8 reserved_at_49a[0x3]; 3420 u8 cd_slave_receive[0x1]; 3421 u8 cd_slave_send[0x1]; 3422 u8 cd_master[0x1]; 3423 3424 u8 reserved_at_4a0[0x3]; 3425 u8 min_rnr_nak[0x5]; 3426 u8 next_rcv_psn[0x18]; 3427 3428 u8 reserved_at_4c0[0x8]; 3429 u8 xrcd[0x18]; 3430 3431 u8 reserved_at_4e0[0x8]; 3432 u8 cqn_rcv[0x18]; 3433 3434 u8 dbr_addr[0x40]; 3435 3436 u8 q_key[0x20]; 3437 3438 u8 reserved_at_560[0x5]; 3439 u8 rq_type[0x3]; 3440 u8 srqn_rmpn_xrqn[0x18]; 3441 3442 u8 reserved_at_580[0x8]; 3443 u8 rmsn[0x18]; 3444 3445 u8 hw_sq_wqebb_counter[0x10]; 3446 u8 sw_sq_wqebb_counter[0x10]; 3447 3448 u8 hw_rq_counter[0x20]; 3449 3450 u8 sw_rq_counter[0x20]; 3451 3452 u8 reserved_at_600[0x20]; 3453 3454 u8 reserved_at_620[0xf]; 3455 u8 cgs[0x1]; 3456 u8 cs_req[0x8]; 3457 u8 cs_res[0x8]; 3458 3459 u8 dc_access_key[0x40]; 3460 3461 u8 reserved_at_680[0x3]; 3462 u8 dbr_umem_valid[0x1]; 3463 3464 u8 reserved_at_684[0xbc]; 3465 }; 3466 3467 struct mlx5_ifc_roce_addr_layout_bits { 3468 u8 source_l3_address[16][0x8]; 3469 3470 u8 reserved_at_80[0x3]; 3471 u8 vlan_valid[0x1]; 3472 u8 vlan_id[0xc]; 3473 u8 source_mac_47_32[0x10]; 3474 3475 u8 source_mac_31_0[0x20]; 3476 3477 u8 reserved_at_c0[0x14]; 3478 u8 roce_l3_type[0x4]; 3479 u8 roce_version[0x8]; 3480 3481 u8 reserved_at_e0[0x20]; 3482 }; 3483 3484 struct mlx5_ifc_crypto_cap_bits { 3485 u8 reserved_at_0[0x3]; 3486 u8 synchronize_dek[0x1]; 3487 u8 int_kek_manual[0x1]; 3488 u8 int_kek_auto[0x1]; 3489 u8 reserved_at_6[0x1a]; 3490 3491 u8 reserved_at_20[0x3]; 3492 u8 log_dek_max_alloc[0x5]; 3493 u8 reserved_at_28[0x3]; 3494 u8 log_max_num_deks[0x5]; 3495 u8 reserved_at_30[0x10]; 3496 3497 u8 reserved_at_40[0x20]; 3498 3499 u8 reserved_at_60[0x3]; 3500 u8 log_dek_granularity[0x5]; 3501 u8 reserved_at_68[0x3]; 3502 u8 log_max_num_int_kek[0x5]; 3503 u8 sw_wrapped_dek[0x10]; 3504 3505 u8 reserved_at_80[0x780]; 3506 }; 3507 3508 union mlx5_ifc_hca_cap_union_bits { 3509 struct mlx5_ifc_cmd_hca_cap_bits cmd_hca_cap; 3510 struct mlx5_ifc_cmd_hca_cap_2_bits cmd_hca_cap_2; 3511 struct mlx5_ifc_odp_cap_bits odp_cap; 3512 struct mlx5_ifc_atomic_caps_bits atomic_caps; 3513 struct mlx5_ifc_roce_cap_bits roce_cap; 3514 struct mlx5_ifc_per_protocol_networking_offload_caps_bits per_protocol_networking_offload_caps; 3515 struct mlx5_ifc_flow_table_nic_cap_bits flow_table_nic_cap; 3516 struct mlx5_ifc_flow_table_eswitch_cap_bits flow_table_eswitch_cap; 3517 struct mlx5_ifc_e_switch_cap_bits e_switch_cap; 3518 struct mlx5_ifc_port_selection_cap_bits port_selection_cap; 3519 struct mlx5_ifc_qos_cap_bits qos_cap; 3520 struct mlx5_ifc_debug_cap_bits debug_cap; 3521 struct mlx5_ifc_fpga_cap_bits fpga_cap; 3522 struct mlx5_ifc_tls_cap_bits tls_cap; 3523 struct mlx5_ifc_device_mem_cap_bits device_mem_cap; 3524 struct mlx5_ifc_virtio_emulation_cap_bits virtio_emulation_cap; 3525 struct mlx5_ifc_macsec_cap_bits macsec_cap; 3526 struct mlx5_ifc_crypto_cap_bits crypto_cap; 3527 struct mlx5_ifc_ipsec_cap_bits ipsec_cap; 3528 u8 reserved_at_0[0x8000]; 3529 }; 3530 3531 enum { 3532 MLX5_FLOW_CONTEXT_ACTION_ALLOW = 0x1, 3533 MLX5_FLOW_CONTEXT_ACTION_DROP = 0x2, 3534 MLX5_FLOW_CONTEXT_ACTION_FWD_DEST = 0x4, 3535 MLX5_FLOW_CONTEXT_ACTION_COUNT = 0x8, 3536 MLX5_FLOW_CONTEXT_ACTION_PACKET_REFORMAT = 0x10, 3537 MLX5_FLOW_CONTEXT_ACTION_DECAP = 0x20, 3538 MLX5_FLOW_CONTEXT_ACTION_MOD_HDR = 0x40, 3539 MLX5_FLOW_CONTEXT_ACTION_VLAN_POP = 0x80, 3540 MLX5_FLOW_CONTEXT_ACTION_VLAN_PUSH = 0x100, 3541 MLX5_FLOW_CONTEXT_ACTION_VLAN_POP_2 = 0x400, 3542 MLX5_FLOW_CONTEXT_ACTION_VLAN_PUSH_2 = 0x800, 3543 MLX5_FLOW_CONTEXT_ACTION_CRYPTO_DECRYPT = 0x1000, 3544 MLX5_FLOW_CONTEXT_ACTION_CRYPTO_ENCRYPT = 0x2000, 3545 MLX5_FLOW_CONTEXT_ACTION_EXECUTE_ASO = 0x4000, 3546 }; 3547 3548 enum { 3549 MLX5_FLOW_CONTEXT_FLOW_SOURCE_ANY_VPORT = 0x0, 3550 MLX5_FLOW_CONTEXT_FLOW_SOURCE_UPLINK = 0x1, 3551 MLX5_FLOW_CONTEXT_FLOW_SOURCE_LOCAL_VPORT = 0x2, 3552 }; 3553 3554 enum { 3555 MLX5_FLOW_CONTEXT_ENCRYPT_DECRYPT_TYPE_IPSEC = 0x0, 3556 MLX5_FLOW_CONTEXT_ENCRYPT_DECRYPT_TYPE_MACSEC = 0x1, 3557 }; 3558 3559 struct mlx5_ifc_vlan_bits { 3560 u8 ethtype[0x10]; 3561 u8 prio[0x3]; 3562 u8 cfi[0x1]; 3563 u8 vid[0xc]; 3564 }; 3565 3566 enum { 3567 MLX5_FLOW_METER_COLOR_RED = 0x0, 3568 MLX5_FLOW_METER_COLOR_YELLOW = 0x1, 3569 MLX5_FLOW_METER_COLOR_GREEN = 0x2, 3570 MLX5_FLOW_METER_COLOR_UNDEFINED = 0x3, 3571 }; 3572 3573 enum { 3574 MLX5_EXE_ASO_FLOW_METER = 0x2, 3575 }; 3576 3577 struct mlx5_ifc_exe_aso_ctrl_flow_meter_bits { 3578 u8 return_reg_id[0x4]; 3579 u8 aso_type[0x4]; 3580 u8 reserved_at_8[0x14]; 3581 u8 action[0x1]; 3582 u8 init_color[0x2]; 3583 u8 meter_id[0x1]; 3584 }; 3585 3586 union mlx5_ifc_exe_aso_ctrl { 3587 struct mlx5_ifc_exe_aso_ctrl_flow_meter_bits exe_aso_ctrl_flow_meter; 3588 }; 3589 3590 struct mlx5_ifc_execute_aso_bits { 3591 u8 valid[0x1]; 3592 u8 reserved_at_1[0x7]; 3593 u8 aso_object_id[0x18]; 3594 3595 union mlx5_ifc_exe_aso_ctrl exe_aso_ctrl; 3596 }; 3597 3598 struct mlx5_ifc_flow_context_bits { 3599 struct mlx5_ifc_vlan_bits push_vlan; 3600 3601 u8 group_id[0x20]; 3602 3603 u8 reserved_at_40[0x8]; 3604 u8 flow_tag[0x18]; 3605 3606 u8 reserved_at_60[0x10]; 3607 u8 action[0x10]; 3608 3609 u8 extended_destination[0x1]; 3610 u8 uplink_hairpin_en[0x1]; 3611 u8 flow_source[0x2]; 3612 u8 encrypt_decrypt_type[0x4]; 3613 u8 destination_list_size[0x18]; 3614 3615 u8 reserved_at_a0[0x8]; 3616 u8 flow_counter_list_size[0x18]; 3617 3618 u8 packet_reformat_id[0x20]; 3619 3620 u8 modify_header_id[0x20]; 3621 3622 struct mlx5_ifc_vlan_bits push_vlan_2; 3623 3624 u8 encrypt_decrypt_obj_id[0x20]; 3625 u8 reserved_at_140[0xc0]; 3626 3627 struct mlx5_ifc_fte_match_param_bits match_value; 3628 3629 struct mlx5_ifc_execute_aso_bits execute_aso[4]; 3630 3631 u8 reserved_at_1300[0x500]; 3632 3633 union mlx5_ifc_dest_format_struct_flow_counter_list_auto_bits destination[]; 3634 }; 3635 3636 enum { 3637 MLX5_XRC_SRQC_STATE_GOOD = 0x0, 3638 MLX5_XRC_SRQC_STATE_ERROR = 0x1, 3639 }; 3640 3641 struct mlx5_ifc_xrc_srqc_bits { 3642 u8 state[0x4]; 3643 u8 log_xrc_srq_size[0x4]; 3644 u8 reserved_at_8[0x18]; 3645 3646 u8 wq_signature[0x1]; 3647 u8 cont_srq[0x1]; 3648 u8 reserved_at_22[0x1]; 3649 u8 rlky[0x1]; 3650 u8 basic_cyclic_rcv_wqe[0x1]; 3651 u8 log_rq_stride[0x3]; 3652 u8 xrcd[0x18]; 3653 3654 u8 page_offset[0x6]; 3655 u8 reserved_at_46[0x1]; 3656 u8 dbr_umem_valid[0x1]; 3657 u8 cqn[0x18]; 3658 3659 u8 reserved_at_60[0x20]; 3660 3661 u8 user_index_equal_xrc_srqn[0x1]; 3662 u8 reserved_at_81[0x1]; 3663 u8 log_page_size[0x6]; 3664 u8 user_index[0x18]; 3665 3666 u8 reserved_at_a0[0x20]; 3667 3668 u8 reserved_at_c0[0x8]; 3669 u8 pd[0x18]; 3670 3671 u8 lwm[0x10]; 3672 u8 wqe_cnt[0x10]; 3673 3674 u8 reserved_at_100[0x40]; 3675 3676 u8 db_record_addr_h[0x20]; 3677 3678 u8 db_record_addr_l[0x1e]; 3679 u8 reserved_at_17e[0x2]; 3680 3681 u8 reserved_at_180[0x80]; 3682 }; 3683 3684 struct mlx5_ifc_vnic_diagnostic_statistics_bits { 3685 u8 counter_error_queues[0x20]; 3686 3687 u8 total_error_queues[0x20]; 3688 3689 u8 send_queue_priority_update_flow[0x20]; 3690 3691 u8 reserved_at_60[0x20]; 3692 3693 u8 nic_receive_steering_discard[0x40]; 3694 3695 u8 receive_discard_vport_down[0x40]; 3696 3697 u8 transmit_discard_vport_down[0x40]; 3698 3699 u8 async_eq_overrun[0x20]; 3700 3701 u8 comp_eq_overrun[0x20]; 3702 3703 u8 reserved_at_180[0x20]; 3704 3705 u8 invalid_command[0x20]; 3706 3707 u8 quota_exceeded_command[0x20]; 3708 3709 u8 internal_rq_out_of_buffer[0x20]; 3710 3711 u8 cq_overrun[0x20]; 3712 3713 u8 eth_wqe_too_small[0x20]; 3714 3715 u8 reserved_at_220[0xc0]; 3716 3717 u8 generated_pkt_steering_fail[0x40]; 3718 3719 u8 handled_pkt_steering_fail[0x40]; 3720 3721 u8 reserved_at_360[0xc80]; 3722 }; 3723 3724 struct mlx5_ifc_traffic_counter_bits { 3725 u8 packets[0x40]; 3726 3727 u8 octets[0x40]; 3728 }; 3729 3730 struct mlx5_ifc_tisc_bits { 3731 u8 strict_lag_tx_port_affinity[0x1]; 3732 u8 tls_en[0x1]; 3733 u8 reserved_at_2[0x2]; 3734 u8 lag_tx_port_affinity[0x04]; 3735 3736 u8 reserved_at_8[0x4]; 3737 u8 prio[0x4]; 3738 u8 reserved_at_10[0x10]; 3739 3740 u8 reserved_at_20[0x100]; 3741 3742 u8 reserved_at_120[0x8]; 3743 u8 transport_domain[0x18]; 3744 3745 u8 reserved_at_140[0x8]; 3746 u8 underlay_qpn[0x18]; 3747 3748 u8 reserved_at_160[0x8]; 3749 u8 pd[0x18]; 3750 3751 u8 reserved_at_180[0x380]; 3752 }; 3753 3754 enum { 3755 MLX5_TIRC_DISP_TYPE_DIRECT = 0x0, 3756 MLX5_TIRC_DISP_TYPE_INDIRECT = 0x1, 3757 }; 3758 3759 enum { 3760 MLX5_TIRC_PACKET_MERGE_MASK_IPV4_LRO = BIT(0), 3761 MLX5_TIRC_PACKET_MERGE_MASK_IPV6_LRO = BIT(1), 3762 }; 3763 3764 enum { 3765 MLX5_RX_HASH_FN_NONE = 0x0, 3766 MLX5_RX_HASH_FN_INVERTED_XOR8 = 0x1, 3767 MLX5_RX_HASH_FN_TOEPLITZ = 0x2, 3768 }; 3769 3770 enum { 3771 MLX5_TIRC_SELF_LB_BLOCK_BLOCK_UNICAST = 0x1, 3772 MLX5_TIRC_SELF_LB_BLOCK_BLOCK_MULTICAST = 0x2, 3773 }; 3774 3775 struct mlx5_ifc_tirc_bits { 3776 u8 reserved_at_0[0x20]; 3777 3778 u8 disp_type[0x4]; 3779 u8 tls_en[0x1]; 3780 u8 reserved_at_25[0x1b]; 3781 3782 u8 reserved_at_40[0x40]; 3783 3784 u8 reserved_at_80[0x4]; 3785 u8 lro_timeout_period_usecs[0x10]; 3786 u8 packet_merge_mask[0x4]; 3787 u8 lro_max_ip_payload_size[0x8]; 3788 3789 u8 reserved_at_a0[0x40]; 3790 3791 u8 reserved_at_e0[0x8]; 3792 u8 inline_rqn[0x18]; 3793 3794 u8 rx_hash_symmetric[0x1]; 3795 u8 reserved_at_101[0x1]; 3796 u8 tunneled_offload_en[0x1]; 3797 u8 reserved_at_103[0x5]; 3798 u8 indirect_table[0x18]; 3799 3800 u8 rx_hash_fn[0x4]; 3801 u8 reserved_at_124[0x2]; 3802 u8 self_lb_block[0x2]; 3803 u8 transport_domain[0x18]; 3804 3805 u8 rx_hash_toeplitz_key[10][0x20]; 3806 3807 struct mlx5_ifc_rx_hash_field_select_bits rx_hash_field_selector_outer; 3808 3809 struct mlx5_ifc_rx_hash_field_select_bits rx_hash_field_selector_inner; 3810 3811 u8 reserved_at_2c0[0x4c0]; 3812 }; 3813 3814 enum { 3815 MLX5_SRQC_STATE_GOOD = 0x0, 3816 MLX5_SRQC_STATE_ERROR = 0x1, 3817 }; 3818 3819 struct mlx5_ifc_srqc_bits { 3820 u8 state[0x4]; 3821 u8 log_srq_size[0x4]; 3822 u8 reserved_at_8[0x18]; 3823 3824 u8 wq_signature[0x1]; 3825 u8 cont_srq[0x1]; 3826 u8 reserved_at_22[0x1]; 3827 u8 rlky[0x1]; 3828 u8 reserved_at_24[0x1]; 3829 u8 log_rq_stride[0x3]; 3830 u8 xrcd[0x18]; 3831 3832 u8 page_offset[0x6]; 3833 u8 reserved_at_46[0x2]; 3834 u8 cqn[0x18]; 3835 3836 u8 reserved_at_60[0x20]; 3837 3838 u8 reserved_at_80[0x2]; 3839 u8 log_page_size[0x6]; 3840 u8 reserved_at_88[0x18]; 3841 3842 u8 reserved_at_a0[0x20]; 3843 3844 u8 reserved_at_c0[0x8]; 3845 u8 pd[0x18]; 3846 3847 u8 lwm[0x10]; 3848 u8 wqe_cnt[0x10]; 3849 3850 u8 reserved_at_100[0x40]; 3851 3852 u8 dbr_addr[0x40]; 3853 3854 u8 reserved_at_180[0x80]; 3855 }; 3856 3857 enum { 3858 MLX5_SQC_STATE_RST = 0x0, 3859 MLX5_SQC_STATE_RDY = 0x1, 3860 MLX5_SQC_STATE_ERR = 0x3, 3861 }; 3862 3863 struct mlx5_ifc_sqc_bits { 3864 u8 rlky[0x1]; 3865 u8 cd_master[0x1]; 3866 u8 fre[0x1]; 3867 u8 flush_in_error_en[0x1]; 3868 u8 allow_multi_pkt_send_wqe[0x1]; 3869 u8 min_wqe_inline_mode[0x3]; 3870 u8 state[0x4]; 3871 u8 reg_umr[0x1]; 3872 u8 allow_swp[0x1]; 3873 u8 hairpin[0x1]; 3874 u8 reserved_at_f[0xb]; 3875 u8 ts_format[0x2]; 3876 u8 reserved_at_1c[0x4]; 3877 3878 u8 reserved_at_20[0x8]; 3879 u8 user_index[0x18]; 3880 3881 u8 reserved_at_40[0x8]; 3882 u8 cqn[0x18]; 3883 3884 u8 reserved_at_60[0x8]; 3885 u8 hairpin_peer_rq[0x18]; 3886 3887 u8 reserved_at_80[0x10]; 3888 u8 hairpin_peer_vhca[0x10]; 3889 3890 u8 reserved_at_a0[0x20]; 3891 3892 u8 reserved_at_c0[0x8]; 3893 u8 ts_cqe_to_dest_cqn[0x18]; 3894 3895 u8 reserved_at_e0[0x10]; 3896 u8 packet_pacing_rate_limit_index[0x10]; 3897 u8 tis_lst_sz[0x10]; 3898 u8 qos_queue_group_id[0x10]; 3899 3900 u8 reserved_at_120[0x40]; 3901 3902 u8 reserved_at_160[0x8]; 3903 u8 tis_num_0[0x18]; 3904 3905 struct mlx5_ifc_wq_bits wq; 3906 }; 3907 3908 enum { 3909 SCHEDULING_CONTEXT_ELEMENT_TYPE_TSAR = 0x0, 3910 SCHEDULING_CONTEXT_ELEMENT_TYPE_VPORT = 0x1, 3911 SCHEDULING_CONTEXT_ELEMENT_TYPE_VPORT_TC = 0x2, 3912 SCHEDULING_CONTEXT_ELEMENT_TYPE_PARA_VPORT_TC = 0x3, 3913 SCHEDULING_CONTEXT_ELEMENT_TYPE_QUEUE_GROUP = 0x4, 3914 }; 3915 3916 enum { 3917 ELEMENT_TYPE_CAP_MASK_TASR = 1 << 0, 3918 ELEMENT_TYPE_CAP_MASK_VPORT = 1 << 1, 3919 ELEMENT_TYPE_CAP_MASK_VPORT_TC = 1 << 2, 3920 ELEMENT_TYPE_CAP_MASK_PARA_VPORT_TC = 1 << 3, 3921 }; 3922 3923 struct mlx5_ifc_scheduling_context_bits { 3924 u8 element_type[0x8]; 3925 u8 reserved_at_8[0x18]; 3926 3927 u8 element_attributes[0x20]; 3928 3929 u8 parent_element_id[0x20]; 3930 3931 u8 reserved_at_60[0x40]; 3932 3933 u8 bw_share[0x20]; 3934 3935 u8 max_average_bw[0x20]; 3936 3937 u8 reserved_at_e0[0x120]; 3938 }; 3939 3940 struct mlx5_ifc_rqtc_bits { 3941 u8 reserved_at_0[0xa0]; 3942 3943 u8 reserved_at_a0[0x5]; 3944 u8 list_q_type[0x3]; 3945 u8 reserved_at_a8[0x8]; 3946 u8 rqt_max_size[0x10]; 3947 3948 u8 rq_vhca_id_format[0x1]; 3949 u8 reserved_at_c1[0xf]; 3950 u8 rqt_actual_size[0x10]; 3951 3952 u8 reserved_at_e0[0x6a0]; 3953 3954 union { 3955 DECLARE_FLEX_ARRAY(struct mlx5_ifc_rq_num_bits, rq_num); 3956 DECLARE_FLEX_ARRAY(struct mlx5_ifc_rq_vhca_bits, rq_vhca); 3957 }; 3958 }; 3959 3960 enum { 3961 MLX5_RQC_MEM_RQ_TYPE_MEMORY_RQ_INLINE = 0x0, 3962 MLX5_RQC_MEM_RQ_TYPE_MEMORY_RQ_RMP = 0x1, 3963 }; 3964 3965 enum { 3966 MLX5_RQC_STATE_RST = 0x0, 3967 MLX5_RQC_STATE_RDY = 0x1, 3968 MLX5_RQC_STATE_ERR = 0x3, 3969 }; 3970 3971 enum { 3972 MLX5_RQC_SHAMPO_NO_MATCH_ALIGNMENT_GRANULARITY_BYTE = 0x0, 3973 MLX5_RQC_SHAMPO_NO_MATCH_ALIGNMENT_GRANULARITY_STRIDE = 0x1, 3974 MLX5_RQC_SHAMPO_NO_MATCH_ALIGNMENT_GRANULARITY_PAGE = 0x2, 3975 }; 3976 3977 enum { 3978 MLX5_RQC_SHAMPO_MATCH_CRITERIA_TYPE_NO_MATCH = 0x0, 3979 MLX5_RQC_SHAMPO_MATCH_CRITERIA_TYPE_EXTENDED = 0x1, 3980 MLX5_RQC_SHAMPO_MATCH_CRITERIA_TYPE_FIVE_TUPLE = 0x2, 3981 }; 3982 3983 struct mlx5_ifc_rqc_bits { 3984 u8 rlky[0x1]; 3985 u8 delay_drop_en[0x1]; 3986 u8 scatter_fcs[0x1]; 3987 u8 vsd[0x1]; 3988 u8 mem_rq_type[0x4]; 3989 u8 state[0x4]; 3990 u8 reserved_at_c[0x1]; 3991 u8 flush_in_error_en[0x1]; 3992 u8 hairpin[0x1]; 3993 u8 reserved_at_f[0xb]; 3994 u8 ts_format[0x2]; 3995 u8 reserved_at_1c[0x4]; 3996 3997 u8 reserved_at_20[0x8]; 3998 u8 user_index[0x18]; 3999 4000 u8 reserved_at_40[0x8]; 4001 u8 cqn[0x18]; 4002 4003 u8 counter_set_id[0x8]; 4004 u8 reserved_at_68[0x18]; 4005 4006 u8 reserved_at_80[0x8]; 4007 u8 rmpn[0x18]; 4008 4009 u8 reserved_at_a0[0x8]; 4010 u8 hairpin_peer_sq[0x18]; 4011 4012 u8 reserved_at_c0[0x10]; 4013 u8 hairpin_peer_vhca[0x10]; 4014 4015 u8 reserved_at_e0[0x46]; 4016 u8 shampo_no_match_alignment_granularity[0x2]; 4017 u8 reserved_at_128[0x6]; 4018 u8 shampo_match_criteria_type[0x2]; 4019 u8 reservation_timeout[0x10]; 4020 4021 u8 reserved_at_140[0x40]; 4022 4023 struct mlx5_ifc_wq_bits wq; 4024 }; 4025 4026 enum { 4027 MLX5_RMPC_STATE_RDY = 0x1, 4028 MLX5_RMPC_STATE_ERR = 0x3, 4029 }; 4030 4031 struct mlx5_ifc_rmpc_bits { 4032 u8 reserved_at_0[0x8]; 4033 u8 state[0x4]; 4034 u8 reserved_at_c[0x14]; 4035 4036 u8 basic_cyclic_rcv_wqe[0x1]; 4037 u8 reserved_at_21[0x1f]; 4038 4039 u8 reserved_at_40[0x140]; 4040 4041 struct mlx5_ifc_wq_bits wq; 4042 }; 4043 4044 enum { 4045 VHCA_ID_TYPE_HW = 0, 4046 VHCA_ID_TYPE_SW = 1, 4047 }; 4048 4049 struct mlx5_ifc_nic_vport_context_bits { 4050 u8 reserved_at_0[0x5]; 4051 u8 min_wqe_inline_mode[0x3]; 4052 u8 reserved_at_8[0x15]; 4053 u8 disable_mc_local_lb[0x1]; 4054 u8 disable_uc_local_lb[0x1]; 4055 u8 roce_en[0x1]; 4056 4057 u8 arm_change_event[0x1]; 4058 u8 reserved_at_21[0x1a]; 4059 u8 event_on_mtu[0x1]; 4060 u8 event_on_promisc_change[0x1]; 4061 u8 event_on_vlan_change[0x1]; 4062 u8 event_on_mc_address_change[0x1]; 4063 u8 event_on_uc_address_change[0x1]; 4064 4065 u8 vhca_id_type[0x1]; 4066 u8 reserved_at_41[0xb]; 4067 u8 affiliation_criteria[0x4]; 4068 u8 affiliated_vhca_id[0x10]; 4069 4070 u8 reserved_at_60[0xa0]; 4071 4072 u8 reserved_at_100[0x1]; 4073 u8 sd_group[0x3]; 4074 u8 reserved_at_104[0x1c]; 4075 4076 u8 reserved_at_120[0x10]; 4077 u8 mtu[0x10]; 4078 4079 u8 system_image_guid[0x40]; 4080 u8 port_guid[0x40]; 4081 u8 node_guid[0x40]; 4082 4083 u8 reserved_at_200[0x140]; 4084 u8 qkey_violation_counter[0x10]; 4085 u8 reserved_at_350[0x430]; 4086 4087 u8 promisc_uc[0x1]; 4088 u8 promisc_mc[0x1]; 4089 u8 promisc_all[0x1]; 4090 u8 reserved_at_783[0x2]; 4091 u8 allowed_list_type[0x3]; 4092 u8 reserved_at_788[0xc]; 4093 u8 allowed_list_size[0xc]; 4094 4095 struct mlx5_ifc_mac_address_layout_bits permanent_address; 4096 4097 u8 reserved_at_7e0[0x20]; 4098 4099 u8 current_uc_mac_address[][0x40]; 4100 }; 4101 4102 enum { 4103 MLX5_MKC_ACCESS_MODE_PA = 0x0, 4104 MLX5_MKC_ACCESS_MODE_MTT = 0x1, 4105 MLX5_MKC_ACCESS_MODE_KLMS = 0x2, 4106 MLX5_MKC_ACCESS_MODE_KSM = 0x3, 4107 MLX5_MKC_ACCESS_MODE_SW_ICM = 0x4, 4108 MLX5_MKC_ACCESS_MODE_MEMIC = 0x5, 4109 }; 4110 4111 struct mlx5_ifc_mkc_bits { 4112 u8 reserved_at_0[0x1]; 4113 u8 free[0x1]; 4114 u8 reserved_at_2[0x1]; 4115 u8 access_mode_4_2[0x3]; 4116 u8 reserved_at_6[0x7]; 4117 u8 relaxed_ordering_write[0x1]; 4118 u8 reserved_at_e[0x1]; 4119 u8 small_fence_on_rdma_read_response[0x1]; 4120 u8 umr_en[0x1]; 4121 u8 a[0x1]; 4122 u8 rw[0x1]; 4123 u8 rr[0x1]; 4124 u8 lw[0x1]; 4125 u8 lr[0x1]; 4126 u8 access_mode_1_0[0x2]; 4127 u8 reserved_at_18[0x2]; 4128 u8 ma_translation_mode[0x2]; 4129 u8 reserved_at_1c[0x4]; 4130 4131 u8 qpn[0x18]; 4132 u8 mkey_7_0[0x8]; 4133 4134 u8 reserved_at_40[0x20]; 4135 4136 u8 length64[0x1]; 4137 u8 bsf_en[0x1]; 4138 u8 sync_umr[0x1]; 4139 u8 reserved_at_63[0x2]; 4140 u8 expected_sigerr_count[0x1]; 4141 u8 reserved_at_66[0x1]; 4142 u8 en_rinval[0x1]; 4143 u8 pd[0x18]; 4144 4145 u8 start_addr[0x40]; 4146 4147 u8 len[0x40]; 4148 4149 u8 bsf_octword_size[0x20]; 4150 4151 u8 reserved_at_120[0x80]; 4152 4153 u8 translations_octword_size[0x20]; 4154 4155 u8 reserved_at_1c0[0x19]; 4156 u8 relaxed_ordering_read[0x1]; 4157 u8 reserved_at_1d9[0x1]; 4158 u8 log_page_size[0x5]; 4159 4160 u8 reserved_at_1e0[0x20]; 4161 }; 4162 4163 struct mlx5_ifc_pkey_bits { 4164 u8 reserved_at_0[0x10]; 4165 u8 pkey[0x10]; 4166 }; 4167 4168 struct mlx5_ifc_array128_auto_bits { 4169 u8 array128_auto[16][0x8]; 4170 }; 4171 4172 struct mlx5_ifc_hca_vport_context_bits { 4173 u8 field_select[0x20]; 4174 4175 u8 reserved_at_20[0xe0]; 4176 4177 u8 sm_virt_aware[0x1]; 4178 u8 has_smi[0x1]; 4179 u8 has_raw[0x1]; 4180 u8 grh_required[0x1]; 4181 u8 reserved_at_104[0xc]; 4182 u8 port_physical_state[0x4]; 4183 u8 vport_state_policy[0x4]; 4184 u8 port_state[0x4]; 4185 u8 vport_state[0x4]; 4186 4187 u8 reserved_at_120[0x20]; 4188 4189 u8 system_image_guid[0x40]; 4190 4191 u8 port_guid[0x40]; 4192 4193 u8 node_guid[0x40]; 4194 4195 u8 cap_mask1[0x20]; 4196 4197 u8 cap_mask1_field_select[0x20]; 4198 4199 u8 cap_mask2[0x20]; 4200 4201 u8 cap_mask2_field_select[0x20]; 4202 4203 u8 reserved_at_280[0x80]; 4204 4205 u8 lid[0x10]; 4206 u8 reserved_at_310[0x4]; 4207 u8 init_type_reply[0x4]; 4208 u8 lmc[0x3]; 4209 u8 subnet_timeout[0x5]; 4210 4211 u8 sm_lid[0x10]; 4212 u8 sm_sl[0x4]; 4213 u8 reserved_at_334[0xc]; 4214 4215 u8 qkey_violation_counter[0x10]; 4216 u8 pkey_violation_counter[0x10]; 4217 4218 u8 reserved_at_360[0xca0]; 4219 }; 4220 4221 struct mlx5_ifc_esw_vport_context_bits { 4222 u8 fdb_to_vport_reg_c[0x1]; 4223 u8 reserved_at_1[0x2]; 4224 u8 vport_svlan_strip[0x1]; 4225 u8 vport_cvlan_strip[0x1]; 4226 u8 vport_svlan_insert[0x1]; 4227 u8 vport_cvlan_insert[0x2]; 4228 u8 fdb_to_vport_reg_c_id[0x8]; 4229 u8 reserved_at_10[0x10]; 4230 4231 u8 reserved_at_20[0x20]; 4232 4233 u8 svlan_cfi[0x1]; 4234 u8 svlan_pcp[0x3]; 4235 u8 svlan_id[0xc]; 4236 u8 cvlan_cfi[0x1]; 4237 u8 cvlan_pcp[0x3]; 4238 u8 cvlan_id[0xc]; 4239 4240 u8 reserved_at_60[0x720]; 4241 4242 u8 sw_steering_vport_icm_address_rx[0x40]; 4243 4244 u8 sw_steering_vport_icm_address_tx[0x40]; 4245 }; 4246 4247 enum { 4248 MLX5_EQC_STATUS_OK = 0x0, 4249 MLX5_EQC_STATUS_EQ_WRITE_FAILURE = 0xa, 4250 }; 4251 4252 enum { 4253 MLX5_EQC_ST_ARMED = 0x9, 4254 MLX5_EQC_ST_FIRED = 0xa, 4255 }; 4256 4257 struct mlx5_ifc_eqc_bits { 4258 u8 status[0x4]; 4259 u8 reserved_at_4[0x9]; 4260 u8 ec[0x1]; 4261 u8 oi[0x1]; 4262 u8 reserved_at_f[0x5]; 4263 u8 st[0x4]; 4264 u8 reserved_at_18[0x8]; 4265 4266 u8 reserved_at_20[0x20]; 4267 4268 u8 reserved_at_40[0x14]; 4269 u8 page_offset[0x6]; 4270 u8 reserved_at_5a[0x6]; 4271 4272 u8 reserved_at_60[0x3]; 4273 u8 log_eq_size[0x5]; 4274 u8 uar_page[0x18]; 4275 4276 u8 reserved_at_80[0x20]; 4277 4278 u8 reserved_at_a0[0x14]; 4279 u8 intr[0xc]; 4280 4281 u8 reserved_at_c0[0x3]; 4282 u8 log_page_size[0x5]; 4283 u8 reserved_at_c8[0x18]; 4284 4285 u8 reserved_at_e0[0x60]; 4286 4287 u8 reserved_at_140[0x8]; 4288 u8 consumer_counter[0x18]; 4289 4290 u8 reserved_at_160[0x8]; 4291 u8 producer_counter[0x18]; 4292 4293 u8 reserved_at_180[0x80]; 4294 }; 4295 4296 enum { 4297 MLX5_DCTC_STATE_ACTIVE = 0x0, 4298 MLX5_DCTC_STATE_DRAINING = 0x1, 4299 MLX5_DCTC_STATE_DRAINED = 0x2, 4300 }; 4301 4302 enum { 4303 MLX5_DCTC_CS_RES_DISABLE = 0x0, 4304 MLX5_DCTC_CS_RES_NA = 0x1, 4305 MLX5_DCTC_CS_RES_UP_TO_64B = 0x2, 4306 }; 4307 4308 enum { 4309 MLX5_DCTC_MTU_256_BYTES = 0x1, 4310 MLX5_DCTC_MTU_512_BYTES = 0x2, 4311 MLX5_DCTC_MTU_1K_BYTES = 0x3, 4312 MLX5_DCTC_MTU_2K_BYTES = 0x4, 4313 MLX5_DCTC_MTU_4K_BYTES = 0x5, 4314 }; 4315 4316 struct mlx5_ifc_dctc_bits { 4317 u8 reserved_at_0[0x4]; 4318 u8 state[0x4]; 4319 u8 reserved_at_8[0x18]; 4320 4321 u8 reserved_at_20[0x8]; 4322 u8 user_index[0x18]; 4323 4324 u8 reserved_at_40[0x8]; 4325 u8 cqn[0x18]; 4326 4327 u8 counter_set_id[0x8]; 4328 u8 atomic_mode[0x4]; 4329 u8 rre[0x1]; 4330 u8 rwe[0x1]; 4331 u8 rae[0x1]; 4332 u8 atomic_like_write_en[0x1]; 4333 u8 latency_sensitive[0x1]; 4334 u8 rlky[0x1]; 4335 u8 free_ar[0x1]; 4336 u8 reserved_at_73[0xd]; 4337 4338 u8 reserved_at_80[0x8]; 4339 u8 cs_res[0x8]; 4340 u8 reserved_at_90[0x3]; 4341 u8 min_rnr_nak[0x5]; 4342 u8 reserved_at_98[0x8]; 4343 4344 u8 reserved_at_a0[0x8]; 4345 u8 srqn_xrqn[0x18]; 4346 4347 u8 reserved_at_c0[0x8]; 4348 u8 pd[0x18]; 4349 4350 u8 tclass[0x8]; 4351 u8 reserved_at_e8[0x4]; 4352 u8 flow_label[0x14]; 4353 4354 u8 dc_access_key[0x40]; 4355 4356 u8 reserved_at_140[0x5]; 4357 u8 mtu[0x3]; 4358 u8 port[0x8]; 4359 u8 pkey_index[0x10]; 4360 4361 u8 reserved_at_160[0x8]; 4362 u8 my_addr_index[0x8]; 4363 u8 reserved_at_170[0x8]; 4364 u8 hop_limit[0x8]; 4365 4366 u8 dc_access_key_violation_count[0x20]; 4367 4368 u8 reserved_at_1a0[0x14]; 4369 u8 dei_cfi[0x1]; 4370 u8 eth_prio[0x3]; 4371 u8 ecn[0x2]; 4372 u8 dscp[0x6]; 4373 4374 u8 reserved_at_1c0[0x20]; 4375 u8 ece[0x20]; 4376 }; 4377 4378 enum { 4379 MLX5_CQC_STATUS_OK = 0x0, 4380 MLX5_CQC_STATUS_CQ_OVERFLOW = 0x9, 4381 MLX5_CQC_STATUS_CQ_WRITE_FAIL = 0xa, 4382 }; 4383 4384 enum { 4385 MLX5_CQC_CQE_SZ_64_BYTES = 0x0, 4386 MLX5_CQC_CQE_SZ_128_BYTES = 0x1, 4387 }; 4388 4389 enum { 4390 MLX5_CQC_ST_SOLICITED_NOTIFICATION_REQUEST_ARMED = 0x6, 4391 MLX5_CQC_ST_NOTIFICATION_REQUEST_ARMED = 0x9, 4392 MLX5_CQC_ST_FIRED = 0xa, 4393 }; 4394 4395 enum mlx5_cq_period_mode { 4396 MLX5_CQ_PERIOD_MODE_START_FROM_EQE = 0x0, 4397 MLX5_CQ_PERIOD_MODE_START_FROM_CQE = 0x1, 4398 MLX5_CQ_PERIOD_NUM_MODES, 4399 }; 4400 4401 struct mlx5_ifc_cqc_bits { 4402 u8 status[0x4]; 4403 u8 reserved_at_4[0x2]; 4404 u8 dbr_umem_valid[0x1]; 4405 u8 apu_cq[0x1]; 4406 u8 cqe_sz[0x3]; 4407 u8 cc[0x1]; 4408 u8 reserved_at_c[0x1]; 4409 u8 scqe_break_moderation_en[0x1]; 4410 u8 oi[0x1]; 4411 u8 cq_period_mode[0x2]; 4412 u8 cqe_comp_en[0x1]; 4413 u8 mini_cqe_res_format[0x2]; 4414 u8 st[0x4]; 4415 u8 reserved_at_18[0x6]; 4416 u8 cqe_compression_layout[0x2]; 4417 4418 u8 reserved_at_20[0x20]; 4419 4420 u8 reserved_at_40[0x14]; 4421 u8 page_offset[0x6]; 4422 u8 reserved_at_5a[0x6]; 4423 4424 u8 reserved_at_60[0x3]; 4425 u8 log_cq_size[0x5]; 4426 u8 uar_page[0x18]; 4427 4428 u8 reserved_at_80[0x4]; 4429 u8 cq_period[0xc]; 4430 u8 cq_max_count[0x10]; 4431 4432 u8 c_eqn_or_apu_element[0x20]; 4433 4434 u8 reserved_at_c0[0x3]; 4435 u8 log_page_size[0x5]; 4436 u8 reserved_at_c8[0x18]; 4437 4438 u8 reserved_at_e0[0x20]; 4439 4440 u8 reserved_at_100[0x8]; 4441 u8 last_notified_index[0x18]; 4442 4443 u8 reserved_at_120[0x8]; 4444 u8 last_solicit_index[0x18]; 4445 4446 u8 reserved_at_140[0x8]; 4447 u8 consumer_counter[0x18]; 4448 4449 u8 reserved_at_160[0x8]; 4450 u8 producer_counter[0x18]; 4451 4452 u8 reserved_at_180[0x40]; 4453 4454 u8 dbr_addr[0x40]; 4455 }; 4456 4457 union mlx5_ifc_cong_control_roce_ecn_auto_bits { 4458 struct mlx5_ifc_cong_control_802_1qau_rp_bits cong_control_802_1qau_rp; 4459 struct mlx5_ifc_cong_control_r_roce_ecn_rp_bits cong_control_r_roce_ecn_rp; 4460 struct mlx5_ifc_cong_control_r_roce_ecn_np_bits cong_control_r_roce_ecn_np; 4461 struct mlx5_ifc_cong_control_r_roce_general_bits cong_control_r_roce_general; 4462 u8 reserved_at_0[0x800]; 4463 }; 4464 4465 struct mlx5_ifc_query_adapter_param_block_bits { 4466 u8 reserved_at_0[0xc0]; 4467 4468 u8 reserved_at_c0[0x8]; 4469 u8 ieee_vendor_id[0x18]; 4470 4471 u8 reserved_at_e0[0x10]; 4472 u8 vsd_vendor_id[0x10]; 4473 4474 u8 vsd[208][0x8]; 4475 4476 u8 vsd_contd_psid[16][0x8]; 4477 }; 4478 4479 enum { 4480 MLX5_XRQC_STATE_GOOD = 0x0, 4481 MLX5_XRQC_STATE_ERROR = 0x1, 4482 }; 4483 4484 enum { 4485 MLX5_XRQC_TOPOLOGY_NO_SPECIAL_TOPOLOGY = 0x0, 4486 MLX5_XRQC_TOPOLOGY_TAG_MATCHING = 0x1, 4487 }; 4488 4489 enum { 4490 MLX5_XRQC_OFFLOAD_RNDV = 0x1, 4491 }; 4492 4493 struct mlx5_ifc_tag_matching_topology_context_bits { 4494 u8 log_matching_list_sz[0x4]; 4495 u8 reserved_at_4[0xc]; 4496 u8 append_next_index[0x10]; 4497 4498 u8 sw_phase_cnt[0x10]; 4499 u8 hw_phase_cnt[0x10]; 4500 4501 u8 reserved_at_40[0x40]; 4502 }; 4503 4504 struct mlx5_ifc_xrqc_bits { 4505 u8 state[0x4]; 4506 u8 rlkey[0x1]; 4507 u8 reserved_at_5[0xf]; 4508 u8 topology[0x4]; 4509 u8 reserved_at_18[0x4]; 4510 u8 offload[0x4]; 4511 4512 u8 reserved_at_20[0x8]; 4513 u8 user_index[0x18]; 4514 4515 u8 reserved_at_40[0x8]; 4516 u8 cqn[0x18]; 4517 4518 u8 reserved_at_60[0xa0]; 4519 4520 struct mlx5_ifc_tag_matching_topology_context_bits tag_matching_topology_context; 4521 4522 u8 reserved_at_180[0x280]; 4523 4524 struct mlx5_ifc_wq_bits wq; 4525 }; 4526 4527 union mlx5_ifc_modify_field_select_resize_field_select_auto_bits { 4528 struct mlx5_ifc_modify_field_select_bits modify_field_select; 4529 struct mlx5_ifc_resize_field_select_bits resize_field_select; 4530 u8 reserved_at_0[0x20]; 4531 }; 4532 4533 union mlx5_ifc_field_select_802_1_r_roce_auto_bits { 4534 struct mlx5_ifc_field_select_802_1qau_rp_bits field_select_802_1qau_rp; 4535 struct mlx5_ifc_field_select_r_roce_rp_bits field_select_r_roce_rp; 4536 struct mlx5_ifc_field_select_r_roce_np_bits field_select_r_roce_np; 4537 u8 reserved_at_0[0x20]; 4538 }; 4539 4540 union mlx5_ifc_eth_cntrs_grp_data_layout_auto_bits { 4541 struct mlx5_ifc_eth_802_3_cntrs_grp_data_layout_bits eth_802_3_cntrs_grp_data_layout; 4542 struct mlx5_ifc_eth_2863_cntrs_grp_data_layout_bits eth_2863_cntrs_grp_data_layout; 4543 struct mlx5_ifc_eth_2819_cntrs_grp_data_layout_bits eth_2819_cntrs_grp_data_layout; 4544 struct mlx5_ifc_eth_3635_cntrs_grp_data_layout_bits eth_3635_cntrs_grp_data_layout; 4545 struct mlx5_ifc_eth_extended_cntrs_grp_data_layout_bits eth_extended_cntrs_grp_data_layout; 4546 struct mlx5_ifc_eth_per_prio_grp_data_layout_bits eth_per_prio_grp_data_layout; 4547 struct mlx5_ifc_eth_per_tc_prio_grp_data_layout_bits eth_per_tc_prio_grp_data_layout; 4548 struct mlx5_ifc_eth_per_tc_congest_prio_grp_data_layout_bits eth_per_tc_congest_prio_grp_data_layout; 4549 struct mlx5_ifc_ib_port_cntrs_grp_data_layout_bits ib_port_cntrs_grp_data_layout; 4550 struct mlx5_ifc_phys_layer_cntrs_bits phys_layer_cntrs; 4551 struct mlx5_ifc_phys_layer_statistical_cntrs_bits phys_layer_statistical_cntrs; 4552 u8 reserved_at_0[0x7c0]; 4553 }; 4554 4555 union mlx5_ifc_pcie_cntrs_grp_data_layout_auto_bits { 4556 struct mlx5_ifc_pcie_perf_cntrs_grp_data_layout_bits pcie_perf_cntrs_grp_data_layout; 4557 u8 reserved_at_0[0x7c0]; 4558 }; 4559 4560 union mlx5_ifc_event_auto_bits { 4561 struct mlx5_ifc_comp_event_bits comp_event; 4562 struct mlx5_ifc_dct_events_bits dct_events; 4563 struct mlx5_ifc_qp_events_bits qp_events; 4564 struct mlx5_ifc_wqe_associated_page_fault_event_bits wqe_associated_page_fault_event; 4565 struct mlx5_ifc_rdma_page_fault_event_bits rdma_page_fault_event; 4566 struct mlx5_ifc_cq_error_bits cq_error; 4567 struct mlx5_ifc_dropped_packet_logged_bits dropped_packet_logged; 4568 struct mlx5_ifc_port_state_change_event_bits port_state_change_event; 4569 struct mlx5_ifc_gpio_event_bits gpio_event; 4570 struct mlx5_ifc_db_bf_congestion_event_bits db_bf_congestion_event; 4571 struct mlx5_ifc_stall_vl_event_bits stall_vl_event; 4572 struct mlx5_ifc_cmd_inter_comp_event_bits cmd_inter_comp_event; 4573 u8 reserved_at_0[0xe0]; 4574 }; 4575 4576 struct mlx5_ifc_health_buffer_bits { 4577 u8 reserved_at_0[0x100]; 4578 4579 u8 assert_existptr[0x20]; 4580 4581 u8 assert_callra[0x20]; 4582 4583 u8 reserved_at_140[0x20]; 4584 4585 u8 time[0x20]; 4586 4587 u8 fw_version[0x20]; 4588 4589 u8 hw_id[0x20]; 4590 4591 u8 rfr[0x1]; 4592 u8 reserved_at_1c1[0x3]; 4593 u8 valid[0x1]; 4594 u8 severity[0x3]; 4595 u8 reserved_at_1c8[0x18]; 4596 4597 u8 irisc_index[0x8]; 4598 u8 synd[0x8]; 4599 u8 ext_synd[0x10]; 4600 }; 4601 4602 struct mlx5_ifc_register_loopback_control_bits { 4603 u8 no_lb[0x1]; 4604 u8 reserved_at_1[0x7]; 4605 u8 port[0x8]; 4606 u8 reserved_at_10[0x10]; 4607 4608 u8 reserved_at_20[0x60]; 4609 }; 4610 4611 struct mlx5_ifc_vport_tc_element_bits { 4612 u8 traffic_class[0x4]; 4613 u8 reserved_at_4[0xc]; 4614 u8 vport_number[0x10]; 4615 }; 4616 4617 struct mlx5_ifc_vport_element_bits { 4618 u8 reserved_at_0[0x10]; 4619 u8 vport_number[0x10]; 4620 }; 4621 4622 enum { 4623 TSAR_ELEMENT_TSAR_TYPE_DWRR = 0x0, 4624 TSAR_ELEMENT_TSAR_TYPE_ROUND_ROBIN = 0x1, 4625 TSAR_ELEMENT_TSAR_TYPE_ETS = 0x2, 4626 }; 4627 4628 struct mlx5_ifc_tsar_element_bits { 4629 u8 reserved_at_0[0x8]; 4630 u8 tsar_type[0x8]; 4631 u8 reserved_at_10[0x10]; 4632 }; 4633 4634 enum { 4635 MLX5_TEARDOWN_HCA_OUT_FORCE_STATE_SUCCESS = 0x0, 4636 MLX5_TEARDOWN_HCA_OUT_FORCE_STATE_FAIL = 0x1, 4637 }; 4638 4639 struct mlx5_ifc_teardown_hca_out_bits { 4640 u8 status[0x8]; 4641 u8 reserved_at_8[0x18]; 4642 4643 u8 syndrome[0x20]; 4644 4645 u8 reserved_at_40[0x3f]; 4646 4647 u8 state[0x1]; 4648 }; 4649 4650 enum { 4651 MLX5_TEARDOWN_HCA_IN_PROFILE_GRACEFUL_CLOSE = 0x0, 4652 MLX5_TEARDOWN_HCA_IN_PROFILE_FORCE_CLOSE = 0x1, 4653 MLX5_TEARDOWN_HCA_IN_PROFILE_PREPARE_FAST_TEARDOWN = 0x2, 4654 }; 4655 4656 struct mlx5_ifc_teardown_hca_in_bits { 4657 u8 opcode[0x10]; 4658 u8 reserved_at_10[0x10]; 4659 4660 u8 reserved_at_20[0x10]; 4661 u8 op_mod[0x10]; 4662 4663 u8 reserved_at_40[0x10]; 4664 u8 profile[0x10]; 4665 4666 u8 reserved_at_60[0x20]; 4667 }; 4668 4669 struct mlx5_ifc_sqerr2rts_qp_out_bits { 4670 u8 status[0x8]; 4671 u8 reserved_at_8[0x18]; 4672 4673 u8 syndrome[0x20]; 4674 4675 u8 reserved_at_40[0x40]; 4676 }; 4677 4678 struct mlx5_ifc_sqerr2rts_qp_in_bits { 4679 u8 opcode[0x10]; 4680 u8 uid[0x10]; 4681 4682 u8 reserved_at_20[0x10]; 4683 u8 op_mod[0x10]; 4684 4685 u8 reserved_at_40[0x8]; 4686 u8 qpn[0x18]; 4687 4688 u8 reserved_at_60[0x20]; 4689 4690 u8 opt_param_mask[0x20]; 4691 4692 u8 reserved_at_a0[0x20]; 4693 4694 struct mlx5_ifc_qpc_bits qpc; 4695 4696 u8 reserved_at_800[0x80]; 4697 }; 4698 4699 struct mlx5_ifc_sqd2rts_qp_out_bits { 4700 u8 status[0x8]; 4701 u8 reserved_at_8[0x18]; 4702 4703 u8 syndrome[0x20]; 4704 4705 u8 reserved_at_40[0x40]; 4706 }; 4707 4708 struct mlx5_ifc_sqd2rts_qp_in_bits { 4709 u8 opcode[0x10]; 4710 u8 uid[0x10]; 4711 4712 u8 reserved_at_20[0x10]; 4713 u8 op_mod[0x10]; 4714 4715 u8 reserved_at_40[0x8]; 4716 u8 qpn[0x18]; 4717 4718 u8 reserved_at_60[0x20]; 4719 4720 u8 opt_param_mask[0x20]; 4721 4722 u8 reserved_at_a0[0x20]; 4723 4724 struct mlx5_ifc_qpc_bits qpc; 4725 4726 u8 reserved_at_800[0x80]; 4727 }; 4728 4729 struct mlx5_ifc_set_roce_address_out_bits { 4730 u8 status[0x8]; 4731 u8 reserved_at_8[0x18]; 4732 4733 u8 syndrome[0x20]; 4734 4735 u8 reserved_at_40[0x40]; 4736 }; 4737 4738 struct mlx5_ifc_set_roce_address_in_bits { 4739 u8 opcode[0x10]; 4740 u8 reserved_at_10[0x10]; 4741 4742 u8 reserved_at_20[0x10]; 4743 u8 op_mod[0x10]; 4744 4745 u8 roce_address_index[0x10]; 4746 u8 reserved_at_50[0xc]; 4747 u8 vhca_port_num[0x4]; 4748 4749 u8 reserved_at_60[0x20]; 4750 4751 struct mlx5_ifc_roce_addr_layout_bits roce_address; 4752 }; 4753 4754 struct mlx5_ifc_set_mad_demux_out_bits { 4755 u8 status[0x8]; 4756 u8 reserved_at_8[0x18]; 4757 4758 u8 syndrome[0x20]; 4759 4760 u8 reserved_at_40[0x40]; 4761 }; 4762 4763 enum { 4764 MLX5_SET_MAD_DEMUX_IN_DEMUX_MODE_PASS_ALL = 0x0, 4765 MLX5_SET_MAD_DEMUX_IN_DEMUX_MODE_SELECTIVE = 0x2, 4766 }; 4767 4768 struct mlx5_ifc_set_mad_demux_in_bits { 4769 u8 opcode[0x10]; 4770 u8 reserved_at_10[0x10]; 4771 4772 u8 reserved_at_20[0x10]; 4773 u8 op_mod[0x10]; 4774 4775 u8 reserved_at_40[0x20]; 4776 4777 u8 reserved_at_60[0x6]; 4778 u8 demux_mode[0x2]; 4779 u8 reserved_at_68[0x18]; 4780 }; 4781 4782 struct mlx5_ifc_set_l2_table_entry_out_bits { 4783 u8 status[0x8]; 4784 u8 reserved_at_8[0x18]; 4785 4786 u8 syndrome[0x20]; 4787 4788 u8 reserved_at_40[0x40]; 4789 }; 4790 4791 struct mlx5_ifc_set_l2_table_entry_in_bits { 4792 u8 opcode[0x10]; 4793 u8 reserved_at_10[0x10]; 4794 4795 u8 reserved_at_20[0x10]; 4796 u8 op_mod[0x10]; 4797 4798 u8 reserved_at_40[0x60]; 4799 4800 u8 reserved_at_a0[0x8]; 4801 u8 table_index[0x18]; 4802 4803 u8 reserved_at_c0[0x20]; 4804 4805 u8 reserved_at_e0[0x10]; 4806 u8 silent_mode_valid[0x1]; 4807 u8 silent_mode[0x1]; 4808 u8 reserved_at_f2[0x1]; 4809 u8 vlan_valid[0x1]; 4810 u8 vlan[0xc]; 4811 4812 struct mlx5_ifc_mac_address_layout_bits mac_address; 4813 4814 u8 reserved_at_140[0xc0]; 4815 }; 4816 4817 struct mlx5_ifc_set_issi_out_bits { 4818 u8 status[0x8]; 4819 u8 reserved_at_8[0x18]; 4820 4821 u8 syndrome[0x20]; 4822 4823 u8 reserved_at_40[0x40]; 4824 }; 4825 4826 struct mlx5_ifc_set_issi_in_bits { 4827 u8 opcode[0x10]; 4828 u8 reserved_at_10[0x10]; 4829 4830 u8 reserved_at_20[0x10]; 4831 u8 op_mod[0x10]; 4832 4833 u8 reserved_at_40[0x10]; 4834 u8 current_issi[0x10]; 4835 4836 u8 reserved_at_60[0x20]; 4837 }; 4838 4839 struct mlx5_ifc_set_hca_cap_out_bits { 4840 u8 status[0x8]; 4841 u8 reserved_at_8[0x18]; 4842 4843 u8 syndrome[0x20]; 4844 4845 u8 reserved_at_40[0x40]; 4846 }; 4847 4848 struct mlx5_ifc_set_hca_cap_in_bits { 4849 u8 opcode[0x10]; 4850 u8 reserved_at_10[0x10]; 4851 4852 u8 reserved_at_20[0x10]; 4853 u8 op_mod[0x10]; 4854 4855 u8 other_function[0x1]; 4856 u8 ec_vf_function[0x1]; 4857 u8 reserved_at_42[0xe]; 4858 u8 function_id[0x10]; 4859 4860 u8 reserved_at_60[0x20]; 4861 4862 union mlx5_ifc_hca_cap_union_bits capability; 4863 }; 4864 4865 enum { 4866 MLX5_SET_FTE_MODIFY_ENABLE_MASK_ACTION = 0x0, 4867 MLX5_SET_FTE_MODIFY_ENABLE_MASK_FLOW_TAG = 0x1, 4868 MLX5_SET_FTE_MODIFY_ENABLE_MASK_DESTINATION_LIST = 0x2, 4869 MLX5_SET_FTE_MODIFY_ENABLE_MASK_FLOW_COUNTERS = 0x3, 4870 MLX5_SET_FTE_MODIFY_ENABLE_MASK_IPSEC_OBJ_ID = 0x4 4871 }; 4872 4873 struct mlx5_ifc_set_fte_out_bits { 4874 u8 status[0x8]; 4875 u8 reserved_at_8[0x18]; 4876 4877 u8 syndrome[0x20]; 4878 4879 u8 reserved_at_40[0x40]; 4880 }; 4881 4882 struct mlx5_ifc_set_fte_in_bits { 4883 u8 opcode[0x10]; 4884 u8 reserved_at_10[0x10]; 4885 4886 u8 reserved_at_20[0x10]; 4887 u8 op_mod[0x10]; 4888 4889 u8 other_vport[0x1]; 4890 u8 reserved_at_41[0xf]; 4891 u8 vport_number[0x10]; 4892 4893 u8 reserved_at_60[0x20]; 4894 4895 u8 table_type[0x8]; 4896 u8 reserved_at_88[0x18]; 4897 4898 u8 reserved_at_a0[0x8]; 4899 u8 table_id[0x18]; 4900 4901 u8 ignore_flow_level[0x1]; 4902 u8 reserved_at_c1[0x17]; 4903 u8 modify_enable_mask[0x8]; 4904 4905 u8 reserved_at_e0[0x20]; 4906 4907 u8 flow_index[0x20]; 4908 4909 u8 reserved_at_120[0xe0]; 4910 4911 struct mlx5_ifc_flow_context_bits flow_context; 4912 }; 4913 4914 struct mlx5_ifc_rts2rts_qp_out_bits { 4915 u8 status[0x8]; 4916 u8 reserved_at_8[0x18]; 4917 4918 u8 syndrome[0x20]; 4919 4920 u8 reserved_at_40[0x20]; 4921 u8 ece[0x20]; 4922 }; 4923 4924 struct mlx5_ifc_rts2rts_qp_in_bits { 4925 u8 opcode[0x10]; 4926 u8 uid[0x10]; 4927 4928 u8 reserved_at_20[0x10]; 4929 u8 op_mod[0x10]; 4930 4931 u8 reserved_at_40[0x8]; 4932 u8 qpn[0x18]; 4933 4934 u8 reserved_at_60[0x20]; 4935 4936 u8 opt_param_mask[0x20]; 4937 4938 u8 ece[0x20]; 4939 4940 struct mlx5_ifc_qpc_bits qpc; 4941 4942 u8 reserved_at_800[0x80]; 4943 }; 4944 4945 struct mlx5_ifc_rtr2rts_qp_out_bits { 4946 u8 status[0x8]; 4947 u8 reserved_at_8[0x18]; 4948 4949 u8 syndrome[0x20]; 4950 4951 u8 reserved_at_40[0x20]; 4952 u8 ece[0x20]; 4953 }; 4954 4955 struct mlx5_ifc_rtr2rts_qp_in_bits { 4956 u8 opcode[0x10]; 4957 u8 uid[0x10]; 4958 4959 u8 reserved_at_20[0x10]; 4960 u8 op_mod[0x10]; 4961 4962 u8 reserved_at_40[0x8]; 4963 u8 qpn[0x18]; 4964 4965 u8 reserved_at_60[0x20]; 4966 4967 u8 opt_param_mask[0x20]; 4968 4969 u8 ece[0x20]; 4970 4971 struct mlx5_ifc_qpc_bits qpc; 4972 4973 u8 reserved_at_800[0x80]; 4974 }; 4975 4976 struct mlx5_ifc_rst2init_qp_out_bits { 4977 u8 status[0x8]; 4978 u8 reserved_at_8[0x18]; 4979 4980 u8 syndrome[0x20]; 4981 4982 u8 reserved_at_40[0x20]; 4983 u8 ece[0x20]; 4984 }; 4985 4986 struct mlx5_ifc_rst2init_qp_in_bits { 4987 u8 opcode[0x10]; 4988 u8 uid[0x10]; 4989 4990 u8 reserved_at_20[0x10]; 4991 u8 op_mod[0x10]; 4992 4993 u8 reserved_at_40[0x8]; 4994 u8 qpn[0x18]; 4995 4996 u8 reserved_at_60[0x20]; 4997 4998 u8 opt_param_mask[0x20]; 4999 5000 u8 ece[0x20]; 5001 5002 struct mlx5_ifc_qpc_bits qpc; 5003 5004 u8 reserved_at_800[0x80]; 5005 }; 5006 5007 struct mlx5_ifc_query_xrq_out_bits { 5008 u8 status[0x8]; 5009 u8 reserved_at_8[0x18]; 5010 5011 u8 syndrome[0x20]; 5012 5013 u8 reserved_at_40[0x40]; 5014 5015 struct mlx5_ifc_xrqc_bits xrq_context; 5016 }; 5017 5018 struct mlx5_ifc_query_xrq_in_bits { 5019 u8 opcode[0x10]; 5020 u8 reserved_at_10[0x10]; 5021 5022 u8 reserved_at_20[0x10]; 5023 u8 op_mod[0x10]; 5024 5025 u8 reserved_at_40[0x8]; 5026 u8 xrqn[0x18]; 5027 5028 u8 reserved_at_60[0x20]; 5029 }; 5030 5031 struct mlx5_ifc_query_xrc_srq_out_bits { 5032 u8 status[0x8]; 5033 u8 reserved_at_8[0x18]; 5034 5035 u8 syndrome[0x20]; 5036 5037 u8 reserved_at_40[0x40]; 5038 5039 struct mlx5_ifc_xrc_srqc_bits xrc_srq_context_entry; 5040 5041 u8 reserved_at_280[0x600]; 5042 5043 u8 pas[][0x40]; 5044 }; 5045 5046 struct mlx5_ifc_query_xrc_srq_in_bits { 5047 u8 opcode[0x10]; 5048 u8 reserved_at_10[0x10]; 5049 5050 u8 reserved_at_20[0x10]; 5051 u8 op_mod[0x10]; 5052 5053 u8 reserved_at_40[0x8]; 5054 u8 xrc_srqn[0x18]; 5055 5056 u8 reserved_at_60[0x20]; 5057 }; 5058 5059 enum { 5060 MLX5_QUERY_VPORT_STATE_OUT_STATE_DOWN = 0x0, 5061 MLX5_QUERY_VPORT_STATE_OUT_STATE_UP = 0x1, 5062 }; 5063 5064 struct mlx5_ifc_query_vport_state_out_bits { 5065 u8 status[0x8]; 5066 u8 reserved_at_8[0x18]; 5067 5068 u8 syndrome[0x20]; 5069 5070 u8 reserved_at_40[0x20]; 5071 5072 u8 reserved_at_60[0x18]; 5073 u8 admin_state[0x4]; 5074 u8 state[0x4]; 5075 }; 5076 5077 enum { 5078 MLX5_VPORT_STATE_OP_MOD_VNIC_VPORT = 0x0, 5079 MLX5_VPORT_STATE_OP_MOD_ESW_VPORT = 0x1, 5080 MLX5_VPORT_STATE_OP_MOD_UPLINK = 0x2, 5081 }; 5082 5083 struct mlx5_ifc_arm_monitor_counter_in_bits { 5084 u8 opcode[0x10]; 5085 u8 uid[0x10]; 5086 5087 u8 reserved_at_20[0x10]; 5088 u8 op_mod[0x10]; 5089 5090 u8 reserved_at_40[0x20]; 5091 5092 u8 reserved_at_60[0x20]; 5093 }; 5094 5095 struct mlx5_ifc_arm_monitor_counter_out_bits { 5096 u8 status[0x8]; 5097 u8 reserved_at_8[0x18]; 5098 5099 u8 syndrome[0x20]; 5100 5101 u8 reserved_at_40[0x40]; 5102 }; 5103 5104 enum { 5105 MLX5_QUERY_MONITOR_CNT_TYPE_PPCNT = 0x0, 5106 MLX5_QUERY_MONITOR_CNT_TYPE_Q_COUNTER = 0x1, 5107 }; 5108 5109 enum mlx5_monitor_counter_ppcnt { 5110 MLX5_QUERY_MONITOR_PPCNT_IN_RANGE_LENGTH_ERRORS = 0x0, 5111 MLX5_QUERY_MONITOR_PPCNT_OUT_OF_RANGE_LENGTH_FIELD = 0x1, 5112 MLX5_QUERY_MONITOR_PPCNT_FRAME_TOO_LONG_ERRORS = 0x2, 5113 MLX5_QUERY_MONITOR_PPCNT_FRAME_CHECK_SEQUENCE_ERRORS = 0x3, 5114 MLX5_QUERY_MONITOR_PPCNT_ALIGNMENT_ERRORS = 0x4, 5115 MLX5_QUERY_MONITOR_PPCNT_IF_OUT_DISCARDS = 0x5, 5116 }; 5117 5118 enum { 5119 MLX5_QUERY_MONITOR_Q_COUNTER_RX_OUT_OF_BUFFER = 0x4, 5120 }; 5121 5122 struct mlx5_ifc_monitor_counter_output_bits { 5123 u8 reserved_at_0[0x4]; 5124 u8 type[0x4]; 5125 u8 reserved_at_8[0x8]; 5126 u8 counter[0x10]; 5127 5128 u8 counter_group_id[0x20]; 5129 }; 5130 5131 #define MLX5_CMD_SET_MONITOR_NUM_PPCNT_COUNTER_SET1 (6) 5132 #define MLX5_CMD_SET_MONITOR_NUM_Q_COUNTERS_SET1 (1) 5133 #define MLX5_CMD_SET_MONITOR_NUM_COUNTER (MLX5_CMD_SET_MONITOR_NUM_PPCNT_COUNTER_SET1 +\ 5134 MLX5_CMD_SET_MONITOR_NUM_Q_COUNTERS_SET1) 5135 5136 struct mlx5_ifc_set_monitor_counter_in_bits { 5137 u8 opcode[0x10]; 5138 u8 uid[0x10]; 5139 5140 u8 reserved_at_20[0x10]; 5141 u8 op_mod[0x10]; 5142 5143 u8 reserved_at_40[0x10]; 5144 u8 num_of_counters[0x10]; 5145 5146 u8 reserved_at_60[0x20]; 5147 5148 struct mlx5_ifc_monitor_counter_output_bits monitor_counter[MLX5_CMD_SET_MONITOR_NUM_COUNTER]; 5149 }; 5150 5151 struct mlx5_ifc_set_monitor_counter_out_bits { 5152 u8 status[0x8]; 5153 u8 reserved_at_8[0x18]; 5154 5155 u8 syndrome[0x20]; 5156 5157 u8 reserved_at_40[0x40]; 5158 }; 5159 5160 struct mlx5_ifc_query_vport_state_in_bits { 5161 u8 opcode[0x10]; 5162 u8 reserved_at_10[0x10]; 5163 5164 u8 reserved_at_20[0x10]; 5165 u8 op_mod[0x10]; 5166 5167 u8 other_vport[0x1]; 5168 u8 reserved_at_41[0xf]; 5169 u8 vport_number[0x10]; 5170 5171 u8 reserved_at_60[0x20]; 5172 }; 5173 5174 struct mlx5_ifc_query_vnic_env_out_bits { 5175 u8 status[0x8]; 5176 u8 reserved_at_8[0x18]; 5177 5178 u8 syndrome[0x20]; 5179 5180 u8 reserved_at_40[0x40]; 5181 5182 struct mlx5_ifc_vnic_diagnostic_statistics_bits vport_env; 5183 }; 5184 5185 enum { 5186 MLX5_QUERY_VNIC_ENV_IN_OP_MOD_VPORT_DIAG_STATISTICS = 0x0, 5187 }; 5188 5189 struct mlx5_ifc_query_vnic_env_in_bits { 5190 u8 opcode[0x10]; 5191 u8 reserved_at_10[0x10]; 5192 5193 u8 reserved_at_20[0x10]; 5194 u8 op_mod[0x10]; 5195 5196 u8 other_vport[0x1]; 5197 u8 reserved_at_41[0xf]; 5198 u8 vport_number[0x10]; 5199 5200 u8 reserved_at_60[0x20]; 5201 }; 5202 5203 struct mlx5_ifc_query_vport_counter_out_bits { 5204 u8 status[0x8]; 5205 u8 reserved_at_8[0x18]; 5206 5207 u8 syndrome[0x20]; 5208 5209 u8 reserved_at_40[0x40]; 5210 5211 struct mlx5_ifc_traffic_counter_bits received_errors; 5212 5213 struct mlx5_ifc_traffic_counter_bits transmit_errors; 5214 5215 struct mlx5_ifc_traffic_counter_bits received_ib_unicast; 5216 5217 struct mlx5_ifc_traffic_counter_bits transmitted_ib_unicast; 5218 5219 struct mlx5_ifc_traffic_counter_bits received_ib_multicast; 5220 5221 struct mlx5_ifc_traffic_counter_bits transmitted_ib_multicast; 5222 5223 struct mlx5_ifc_traffic_counter_bits received_eth_broadcast; 5224 5225 struct mlx5_ifc_traffic_counter_bits transmitted_eth_broadcast; 5226 5227 struct mlx5_ifc_traffic_counter_bits received_eth_unicast; 5228 5229 struct mlx5_ifc_traffic_counter_bits transmitted_eth_unicast; 5230 5231 struct mlx5_ifc_traffic_counter_bits received_eth_multicast; 5232 5233 struct mlx5_ifc_traffic_counter_bits transmitted_eth_multicast; 5234 5235 struct mlx5_ifc_traffic_counter_bits local_loopback; 5236 5237 u8 reserved_at_700[0x980]; 5238 }; 5239 5240 enum { 5241 MLX5_QUERY_VPORT_COUNTER_IN_OP_MOD_VPORT_COUNTERS = 0x0, 5242 }; 5243 5244 struct mlx5_ifc_query_vport_counter_in_bits { 5245 u8 opcode[0x10]; 5246 u8 reserved_at_10[0x10]; 5247 5248 u8 reserved_at_20[0x10]; 5249 u8 op_mod[0x10]; 5250 5251 u8 other_vport[0x1]; 5252 u8 reserved_at_41[0xb]; 5253 u8 port_num[0x4]; 5254 u8 vport_number[0x10]; 5255 5256 u8 reserved_at_60[0x60]; 5257 5258 u8 clear[0x1]; 5259 u8 reserved_at_c1[0x1f]; 5260 5261 u8 reserved_at_e0[0x20]; 5262 }; 5263 5264 struct mlx5_ifc_query_tis_out_bits { 5265 u8 status[0x8]; 5266 u8 reserved_at_8[0x18]; 5267 5268 u8 syndrome[0x20]; 5269 5270 u8 reserved_at_40[0x40]; 5271 5272 struct mlx5_ifc_tisc_bits tis_context; 5273 }; 5274 5275 struct mlx5_ifc_query_tis_in_bits { 5276 u8 opcode[0x10]; 5277 u8 reserved_at_10[0x10]; 5278 5279 u8 reserved_at_20[0x10]; 5280 u8 op_mod[0x10]; 5281 5282 u8 reserved_at_40[0x8]; 5283 u8 tisn[0x18]; 5284 5285 u8 reserved_at_60[0x20]; 5286 }; 5287 5288 struct mlx5_ifc_query_tir_out_bits { 5289 u8 status[0x8]; 5290 u8 reserved_at_8[0x18]; 5291 5292 u8 syndrome[0x20]; 5293 5294 u8 reserved_at_40[0xc0]; 5295 5296 struct mlx5_ifc_tirc_bits tir_context; 5297 }; 5298 5299 struct mlx5_ifc_query_tir_in_bits { 5300 u8 opcode[0x10]; 5301 u8 reserved_at_10[0x10]; 5302 5303 u8 reserved_at_20[0x10]; 5304 u8 op_mod[0x10]; 5305 5306 u8 reserved_at_40[0x8]; 5307 u8 tirn[0x18]; 5308 5309 u8 reserved_at_60[0x20]; 5310 }; 5311 5312 struct mlx5_ifc_query_srq_out_bits { 5313 u8 status[0x8]; 5314 u8 reserved_at_8[0x18]; 5315 5316 u8 syndrome[0x20]; 5317 5318 u8 reserved_at_40[0x40]; 5319 5320 struct mlx5_ifc_srqc_bits srq_context_entry; 5321 5322 u8 reserved_at_280[0x600]; 5323 5324 u8 pas[][0x40]; 5325 }; 5326 5327 struct mlx5_ifc_query_srq_in_bits { 5328 u8 opcode[0x10]; 5329 u8 reserved_at_10[0x10]; 5330 5331 u8 reserved_at_20[0x10]; 5332 u8 op_mod[0x10]; 5333 5334 u8 reserved_at_40[0x8]; 5335 u8 srqn[0x18]; 5336 5337 u8 reserved_at_60[0x20]; 5338 }; 5339 5340 struct mlx5_ifc_query_sq_out_bits { 5341 u8 status[0x8]; 5342 u8 reserved_at_8[0x18]; 5343 5344 u8 syndrome[0x20]; 5345 5346 u8 reserved_at_40[0xc0]; 5347 5348 struct mlx5_ifc_sqc_bits sq_context; 5349 }; 5350 5351 struct mlx5_ifc_query_sq_in_bits { 5352 u8 opcode[0x10]; 5353 u8 reserved_at_10[0x10]; 5354 5355 u8 reserved_at_20[0x10]; 5356 u8 op_mod[0x10]; 5357 5358 u8 reserved_at_40[0x8]; 5359 u8 sqn[0x18]; 5360 5361 u8 reserved_at_60[0x20]; 5362 }; 5363 5364 struct mlx5_ifc_query_special_contexts_out_bits { 5365 u8 status[0x8]; 5366 u8 reserved_at_8[0x18]; 5367 5368 u8 syndrome[0x20]; 5369 5370 u8 dump_fill_mkey[0x20]; 5371 5372 u8 resd_lkey[0x20]; 5373 5374 u8 null_mkey[0x20]; 5375 5376 u8 terminate_scatter_list_mkey[0x20]; 5377 5378 u8 repeated_mkey[0x20]; 5379 5380 u8 reserved_at_a0[0x20]; 5381 }; 5382 5383 struct mlx5_ifc_query_special_contexts_in_bits { 5384 u8 opcode[0x10]; 5385 u8 reserved_at_10[0x10]; 5386 5387 u8 reserved_at_20[0x10]; 5388 u8 op_mod[0x10]; 5389 5390 u8 reserved_at_40[0x40]; 5391 }; 5392 5393 struct mlx5_ifc_query_scheduling_element_out_bits { 5394 u8 opcode[0x10]; 5395 u8 reserved_at_10[0x10]; 5396 5397 u8 reserved_at_20[0x10]; 5398 u8 op_mod[0x10]; 5399 5400 u8 reserved_at_40[0xc0]; 5401 5402 struct mlx5_ifc_scheduling_context_bits scheduling_context; 5403 5404 u8 reserved_at_300[0x100]; 5405 }; 5406 5407 enum { 5408 SCHEDULING_HIERARCHY_E_SWITCH = 0x2, 5409 SCHEDULING_HIERARCHY_NIC = 0x3, 5410 }; 5411 5412 struct mlx5_ifc_query_scheduling_element_in_bits { 5413 u8 opcode[0x10]; 5414 u8 reserved_at_10[0x10]; 5415 5416 u8 reserved_at_20[0x10]; 5417 u8 op_mod[0x10]; 5418 5419 u8 scheduling_hierarchy[0x8]; 5420 u8 reserved_at_48[0x18]; 5421 5422 u8 scheduling_element_id[0x20]; 5423 5424 u8 reserved_at_80[0x180]; 5425 }; 5426 5427 struct mlx5_ifc_query_rqt_out_bits { 5428 u8 status[0x8]; 5429 u8 reserved_at_8[0x18]; 5430 5431 u8 syndrome[0x20]; 5432 5433 u8 reserved_at_40[0xc0]; 5434 5435 struct mlx5_ifc_rqtc_bits rqt_context; 5436 }; 5437 5438 struct mlx5_ifc_query_rqt_in_bits { 5439 u8 opcode[0x10]; 5440 u8 reserved_at_10[0x10]; 5441 5442 u8 reserved_at_20[0x10]; 5443 u8 op_mod[0x10]; 5444 5445 u8 reserved_at_40[0x8]; 5446 u8 rqtn[0x18]; 5447 5448 u8 reserved_at_60[0x20]; 5449 }; 5450 5451 struct mlx5_ifc_query_rq_out_bits { 5452 u8 status[0x8]; 5453 u8 reserved_at_8[0x18]; 5454 5455 u8 syndrome[0x20]; 5456 5457 u8 reserved_at_40[0xc0]; 5458 5459 struct mlx5_ifc_rqc_bits rq_context; 5460 }; 5461 5462 struct mlx5_ifc_query_rq_in_bits { 5463 u8 opcode[0x10]; 5464 u8 reserved_at_10[0x10]; 5465 5466 u8 reserved_at_20[0x10]; 5467 u8 op_mod[0x10]; 5468 5469 u8 reserved_at_40[0x8]; 5470 u8 rqn[0x18]; 5471 5472 u8 reserved_at_60[0x20]; 5473 }; 5474 5475 struct mlx5_ifc_query_roce_address_out_bits { 5476 u8 status[0x8]; 5477 u8 reserved_at_8[0x18]; 5478 5479 u8 syndrome[0x20]; 5480 5481 u8 reserved_at_40[0x40]; 5482 5483 struct mlx5_ifc_roce_addr_layout_bits roce_address; 5484 }; 5485 5486 struct mlx5_ifc_query_roce_address_in_bits { 5487 u8 opcode[0x10]; 5488 u8 reserved_at_10[0x10]; 5489 5490 u8 reserved_at_20[0x10]; 5491 u8 op_mod[0x10]; 5492 5493 u8 roce_address_index[0x10]; 5494 u8 reserved_at_50[0xc]; 5495 u8 vhca_port_num[0x4]; 5496 5497 u8 reserved_at_60[0x20]; 5498 }; 5499 5500 struct mlx5_ifc_query_rmp_out_bits { 5501 u8 status[0x8]; 5502 u8 reserved_at_8[0x18]; 5503 5504 u8 syndrome[0x20]; 5505 5506 u8 reserved_at_40[0xc0]; 5507 5508 struct mlx5_ifc_rmpc_bits rmp_context; 5509 }; 5510 5511 struct mlx5_ifc_query_rmp_in_bits { 5512 u8 opcode[0x10]; 5513 u8 reserved_at_10[0x10]; 5514 5515 u8 reserved_at_20[0x10]; 5516 u8 op_mod[0x10]; 5517 5518 u8 reserved_at_40[0x8]; 5519 u8 rmpn[0x18]; 5520 5521 u8 reserved_at_60[0x20]; 5522 }; 5523 5524 struct mlx5_ifc_cqe_error_syndrome_bits { 5525 u8 hw_error_syndrome[0x8]; 5526 u8 hw_syndrome_type[0x4]; 5527 u8 reserved_at_c[0x4]; 5528 u8 vendor_error_syndrome[0x8]; 5529 u8 syndrome[0x8]; 5530 }; 5531 5532 struct mlx5_ifc_qp_context_extension_bits { 5533 u8 reserved_at_0[0x60]; 5534 5535 struct mlx5_ifc_cqe_error_syndrome_bits error_syndrome; 5536 5537 u8 reserved_at_80[0x580]; 5538 }; 5539 5540 struct mlx5_ifc_qpc_extension_and_pas_list_in_bits { 5541 struct mlx5_ifc_qp_context_extension_bits qpc_data_extension; 5542 5543 u8 pas[0][0x40]; 5544 }; 5545 5546 struct mlx5_ifc_qp_pas_list_in_bits { 5547 struct mlx5_ifc_cmd_pas_bits pas[0]; 5548 }; 5549 5550 union mlx5_ifc_qp_pas_or_qpc_ext_and_pas_bits { 5551 struct mlx5_ifc_qp_pas_list_in_bits qp_pas_list; 5552 struct mlx5_ifc_qpc_extension_and_pas_list_in_bits qpc_ext_and_pas_list; 5553 }; 5554 5555 struct mlx5_ifc_query_qp_out_bits { 5556 u8 status[0x8]; 5557 u8 reserved_at_8[0x18]; 5558 5559 u8 syndrome[0x20]; 5560 5561 u8 reserved_at_40[0x40]; 5562 5563 u8 opt_param_mask[0x20]; 5564 5565 u8 ece[0x20]; 5566 5567 struct mlx5_ifc_qpc_bits qpc; 5568 5569 u8 reserved_at_800[0x80]; 5570 5571 union mlx5_ifc_qp_pas_or_qpc_ext_and_pas_bits qp_pas_or_qpc_ext_and_pas; 5572 }; 5573 5574 struct mlx5_ifc_query_qp_in_bits { 5575 u8 opcode[0x10]; 5576 u8 reserved_at_10[0x10]; 5577 5578 u8 reserved_at_20[0x10]; 5579 u8 op_mod[0x10]; 5580 5581 u8 qpc_ext[0x1]; 5582 u8 reserved_at_41[0x7]; 5583 u8 qpn[0x18]; 5584 5585 u8 reserved_at_60[0x20]; 5586 }; 5587 5588 struct mlx5_ifc_query_q_counter_out_bits { 5589 u8 status[0x8]; 5590 u8 reserved_at_8[0x18]; 5591 5592 u8 syndrome[0x20]; 5593 5594 u8 reserved_at_40[0x40]; 5595 5596 u8 rx_write_requests[0x20]; 5597 5598 u8 reserved_at_a0[0x20]; 5599 5600 u8 rx_read_requests[0x20]; 5601 5602 u8 reserved_at_e0[0x20]; 5603 5604 u8 rx_atomic_requests[0x20]; 5605 5606 u8 reserved_at_120[0x20]; 5607 5608 u8 rx_dct_connect[0x20]; 5609 5610 u8 reserved_at_160[0x20]; 5611 5612 u8 out_of_buffer[0x20]; 5613 5614 u8 reserved_at_1a0[0x20]; 5615 5616 u8 out_of_sequence[0x20]; 5617 5618 u8 reserved_at_1e0[0x20]; 5619 5620 u8 duplicate_request[0x20]; 5621 5622 u8 reserved_at_220[0x20]; 5623 5624 u8 rnr_nak_retry_err[0x20]; 5625 5626 u8 reserved_at_260[0x20]; 5627 5628 u8 packet_seq_err[0x20]; 5629 5630 u8 reserved_at_2a0[0x20]; 5631 5632 u8 implied_nak_seq_err[0x20]; 5633 5634 u8 reserved_at_2e0[0x20]; 5635 5636 u8 local_ack_timeout_err[0x20]; 5637 5638 u8 reserved_at_320[0xa0]; 5639 5640 u8 resp_local_length_error[0x20]; 5641 5642 u8 req_local_length_error[0x20]; 5643 5644 u8 resp_local_qp_error[0x20]; 5645 5646 u8 local_operation_error[0x20]; 5647 5648 u8 resp_local_protection[0x20]; 5649 5650 u8 req_local_protection[0x20]; 5651 5652 u8 resp_cqe_error[0x20]; 5653 5654 u8 req_cqe_error[0x20]; 5655 5656 u8 req_mw_binding[0x20]; 5657 5658 u8 req_bad_response[0x20]; 5659 5660 u8 req_remote_invalid_request[0x20]; 5661 5662 u8 resp_remote_invalid_request[0x20]; 5663 5664 u8 req_remote_access_errors[0x20]; 5665 5666 u8 resp_remote_access_errors[0x20]; 5667 5668 u8 req_remote_operation_errors[0x20]; 5669 5670 u8 req_transport_retries_exceeded[0x20]; 5671 5672 u8 cq_overflow[0x20]; 5673 5674 u8 resp_cqe_flush_error[0x20]; 5675 5676 u8 req_cqe_flush_error[0x20]; 5677 5678 u8 reserved_at_620[0x20]; 5679 5680 u8 roce_adp_retrans[0x20]; 5681 5682 u8 roce_adp_retrans_to[0x20]; 5683 5684 u8 roce_slow_restart[0x20]; 5685 5686 u8 roce_slow_restart_cnps[0x20]; 5687 5688 u8 roce_slow_restart_trans[0x20]; 5689 5690 u8 reserved_at_6e0[0x120]; 5691 }; 5692 5693 struct mlx5_ifc_query_q_counter_in_bits { 5694 u8 opcode[0x10]; 5695 u8 reserved_at_10[0x10]; 5696 5697 u8 reserved_at_20[0x10]; 5698 u8 op_mod[0x10]; 5699 5700 u8 other_vport[0x1]; 5701 u8 reserved_at_41[0xf]; 5702 u8 vport_number[0x10]; 5703 5704 u8 reserved_at_60[0x60]; 5705 5706 u8 clear[0x1]; 5707 u8 aggregate[0x1]; 5708 u8 reserved_at_c2[0x1e]; 5709 5710 u8 reserved_at_e0[0x18]; 5711 u8 counter_set_id[0x8]; 5712 }; 5713 5714 struct mlx5_ifc_query_pages_out_bits { 5715 u8 status[0x8]; 5716 u8 reserved_at_8[0x18]; 5717 5718 u8 syndrome[0x20]; 5719 5720 u8 embedded_cpu_function[0x1]; 5721 u8 reserved_at_41[0xf]; 5722 u8 function_id[0x10]; 5723 5724 u8 num_pages[0x20]; 5725 }; 5726 5727 enum { 5728 MLX5_QUERY_PAGES_IN_OP_MOD_BOOT_PAGES = 0x1, 5729 MLX5_QUERY_PAGES_IN_OP_MOD_INIT_PAGES = 0x2, 5730 MLX5_QUERY_PAGES_IN_OP_MOD_REGULAR_PAGES = 0x3, 5731 }; 5732 5733 struct mlx5_ifc_query_pages_in_bits { 5734 u8 opcode[0x10]; 5735 u8 reserved_at_10[0x10]; 5736 5737 u8 reserved_at_20[0x10]; 5738 u8 op_mod[0x10]; 5739 5740 u8 embedded_cpu_function[0x1]; 5741 u8 reserved_at_41[0xf]; 5742 u8 function_id[0x10]; 5743 5744 u8 reserved_at_60[0x20]; 5745 }; 5746 5747 struct mlx5_ifc_query_nic_vport_context_out_bits { 5748 u8 status[0x8]; 5749 u8 reserved_at_8[0x18]; 5750 5751 u8 syndrome[0x20]; 5752 5753 u8 reserved_at_40[0x40]; 5754 5755 struct mlx5_ifc_nic_vport_context_bits nic_vport_context; 5756 }; 5757 5758 struct mlx5_ifc_query_nic_vport_context_in_bits { 5759 u8 opcode[0x10]; 5760 u8 reserved_at_10[0x10]; 5761 5762 u8 reserved_at_20[0x10]; 5763 u8 op_mod[0x10]; 5764 5765 u8 other_vport[0x1]; 5766 u8 reserved_at_41[0xf]; 5767 u8 vport_number[0x10]; 5768 5769 u8 reserved_at_60[0x5]; 5770 u8 allowed_list_type[0x3]; 5771 u8 reserved_at_68[0x18]; 5772 }; 5773 5774 struct mlx5_ifc_query_mkey_out_bits { 5775 u8 status[0x8]; 5776 u8 reserved_at_8[0x18]; 5777 5778 u8 syndrome[0x20]; 5779 5780 u8 reserved_at_40[0x40]; 5781 5782 struct mlx5_ifc_mkc_bits memory_key_mkey_entry; 5783 5784 u8 reserved_at_280[0x600]; 5785 5786 u8 bsf0_klm0_pas_mtt0_1[16][0x8]; 5787 5788 u8 bsf1_klm1_pas_mtt2_3[16][0x8]; 5789 }; 5790 5791 struct mlx5_ifc_query_mkey_in_bits { 5792 u8 opcode[0x10]; 5793 u8 reserved_at_10[0x10]; 5794 5795 u8 reserved_at_20[0x10]; 5796 u8 op_mod[0x10]; 5797 5798 u8 reserved_at_40[0x8]; 5799 u8 mkey_index[0x18]; 5800 5801 u8 pg_access[0x1]; 5802 u8 reserved_at_61[0x1f]; 5803 }; 5804 5805 struct mlx5_ifc_query_mad_demux_out_bits { 5806 u8 status[0x8]; 5807 u8 reserved_at_8[0x18]; 5808 5809 u8 syndrome[0x20]; 5810 5811 u8 reserved_at_40[0x40]; 5812 5813 u8 mad_dumux_parameters_block[0x20]; 5814 }; 5815 5816 struct mlx5_ifc_query_mad_demux_in_bits { 5817 u8 opcode[0x10]; 5818 u8 reserved_at_10[0x10]; 5819 5820 u8 reserved_at_20[0x10]; 5821 u8 op_mod[0x10]; 5822 5823 u8 reserved_at_40[0x40]; 5824 }; 5825 5826 struct mlx5_ifc_query_l2_table_entry_out_bits { 5827 u8 status[0x8]; 5828 u8 reserved_at_8[0x18]; 5829 5830 u8 syndrome[0x20]; 5831 5832 u8 reserved_at_40[0xa0]; 5833 5834 u8 reserved_at_e0[0x13]; 5835 u8 vlan_valid[0x1]; 5836 u8 vlan[0xc]; 5837 5838 struct mlx5_ifc_mac_address_layout_bits mac_address; 5839 5840 u8 reserved_at_140[0xc0]; 5841 }; 5842 5843 struct mlx5_ifc_query_l2_table_entry_in_bits { 5844 u8 opcode[0x10]; 5845 u8 reserved_at_10[0x10]; 5846 5847 u8 reserved_at_20[0x10]; 5848 u8 op_mod[0x10]; 5849 5850 u8 reserved_at_40[0x60]; 5851 5852 u8 reserved_at_a0[0x8]; 5853 u8 table_index[0x18]; 5854 5855 u8 reserved_at_c0[0x140]; 5856 }; 5857 5858 struct mlx5_ifc_query_issi_out_bits { 5859 u8 status[0x8]; 5860 u8 reserved_at_8[0x18]; 5861 5862 u8 syndrome[0x20]; 5863 5864 u8 reserved_at_40[0x10]; 5865 u8 current_issi[0x10]; 5866 5867 u8 reserved_at_60[0xa0]; 5868 5869 u8 reserved_at_100[76][0x8]; 5870 u8 supported_issi_dw0[0x20]; 5871 }; 5872 5873 struct mlx5_ifc_query_issi_in_bits { 5874 u8 opcode[0x10]; 5875 u8 reserved_at_10[0x10]; 5876 5877 u8 reserved_at_20[0x10]; 5878 u8 op_mod[0x10]; 5879 5880 u8 reserved_at_40[0x40]; 5881 }; 5882 5883 struct mlx5_ifc_set_driver_version_out_bits { 5884 u8 status[0x8]; 5885 u8 reserved_0[0x18]; 5886 5887 u8 syndrome[0x20]; 5888 u8 reserved_1[0x40]; 5889 }; 5890 5891 struct mlx5_ifc_set_driver_version_in_bits { 5892 u8 opcode[0x10]; 5893 u8 reserved_0[0x10]; 5894 5895 u8 reserved_1[0x10]; 5896 u8 op_mod[0x10]; 5897 5898 u8 reserved_2[0x40]; 5899 u8 driver_version[64][0x8]; 5900 }; 5901 5902 struct mlx5_ifc_query_hca_vport_pkey_out_bits { 5903 u8 status[0x8]; 5904 u8 reserved_at_8[0x18]; 5905 5906 u8 syndrome[0x20]; 5907 5908 u8 reserved_at_40[0x40]; 5909 5910 struct mlx5_ifc_pkey_bits pkey[]; 5911 }; 5912 5913 struct mlx5_ifc_query_hca_vport_pkey_in_bits { 5914 u8 opcode[0x10]; 5915 u8 reserved_at_10[0x10]; 5916 5917 u8 reserved_at_20[0x10]; 5918 u8 op_mod[0x10]; 5919 5920 u8 other_vport[0x1]; 5921 u8 reserved_at_41[0xb]; 5922 u8 port_num[0x4]; 5923 u8 vport_number[0x10]; 5924 5925 u8 reserved_at_60[0x10]; 5926 u8 pkey_index[0x10]; 5927 }; 5928 5929 enum { 5930 MLX5_HCA_VPORT_SEL_PORT_GUID = 1 << 0, 5931 MLX5_HCA_VPORT_SEL_NODE_GUID = 1 << 1, 5932 MLX5_HCA_VPORT_SEL_STATE_POLICY = 1 << 2, 5933 }; 5934 5935 struct mlx5_ifc_query_hca_vport_gid_out_bits { 5936 u8 status[0x8]; 5937 u8 reserved_at_8[0x18]; 5938 5939 u8 syndrome[0x20]; 5940 5941 u8 reserved_at_40[0x20]; 5942 5943 u8 gids_num[0x10]; 5944 u8 reserved_at_70[0x10]; 5945 5946 struct mlx5_ifc_array128_auto_bits gid[]; 5947 }; 5948 5949 struct mlx5_ifc_query_hca_vport_gid_in_bits { 5950 u8 opcode[0x10]; 5951 u8 reserved_at_10[0x10]; 5952 5953 u8 reserved_at_20[0x10]; 5954 u8 op_mod[0x10]; 5955 5956 u8 other_vport[0x1]; 5957 u8 reserved_at_41[0xb]; 5958 u8 port_num[0x4]; 5959 u8 vport_number[0x10]; 5960 5961 u8 reserved_at_60[0x10]; 5962 u8 gid_index[0x10]; 5963 }; 5964 5965 struct mlx5_ifc_query_hca_vport_context_out_bits { 5966 u8 status[0x8]; 5967 u8 reserved_at_8[0x18]; 5968 5969 u8 syndrome[0x20]; 5970 5971 u8 reserved_at_40[0x40]; 5972 5973 struct mlx5_ifc_hca_vport_context_bits hca_vport_context; 5974 }; 5975 5976 struct mlx5_ifc_query_hca_vport_context_in_bits { 5977 u8 opcode[0x10]; 5978 u8 reserved_at_10[0x10]; 5979 5980 u8 reserved_at_20[0x10]; 5981 u8 op_mod[0x10]; 5982 5983 u8 other_vport[0x1]; 5984 u8 reserved_at_41[0xb]; 5985 u8 port_num[0x4]; 5986 u8 vport_number[0x10]; 5987 5988 u8 reserved_at_60[0x20]; 5989 }; 5990 5991 struct mlx5_ifc_query_hca_cap_out_bits { 5992 u8 status[0x8]; 5993 u8 reserved_at_8[0x18]; 5994 5995 u8 syndrome[0x20]; 5996 5997 u8 reserved_at_40[0x40]; 5998 5999 union mlx5_ifc_hca_cap_union_bits capability; 6000 }; 6001 6002 struct mlx5_ifc_query_hca_cap_in_bits { 6003 u8 opcode[0x10]; 6004 u8 reserved_at_10[0x10]; 6005 6006 u8 reserved_at_20[0x10]; 6007 u8 op_mod[0x10]; 6008 6009 u8 other_function[0x1]; 6010 u8 ec_vf_function[0x1]; 6011 u8 reserved_at_42[0xe]; 6012 u8 function_id[0x10]; 6013 6014 u8 reserved_at_60[0x20]; 6015 }; 6016 6017 struct mlx5_ifc_other_hca_cap_bits { 6018 u8 roce[0x1]; 6019 u8 reserved_at_1[0x27f]; 6020 }; 6021 6022 struct mlx5_ifc_query_other_hca_cap_out_bits { 6023 u8 status[0x8]; 6024 u8 reserved_at_8[0x18]; 6025 6026 u8 syndrome[0x20]; 6027 6028 u8 reserved_at_40[0x40]; 6029 6030 struct mlx5_ifc_other_hca_cap_bits other_capability; 6031 }; 6032 6033 struct mlx5_ifc_query_other_hca_cap_in_bits { 6034 u8 opcode[0x10]; 6035 u8 reserved_at_10[0x10]; 6036 6037 u8 reserved_at_20[0x10]; 6038 u8 op_mod[0x10]; 6039 6040 u8 reserved_at_40[0x10]; 6041 u8 function_id[0x10]; 6042 6043 u8 reserved_at_60[0x20]; 6044 }; 6045 6046 struct mlx5_ifc_modify_other_hca_cap_out_bits { 6047 u8 status[0x8]; 6048 u8 reserved_at_8[0x18]; 6049 6050 u8 syndrome[0x20]; 6051 6052 u8 reserved_at_40[0x40]; 6053 }; 6054 6055 struct mlx5_ifc_modify_other_hca_cap_in_bits { 6056 u8 opcode[0x10]; 6057 u8 reserved_at_10[0x10]; 6058 6059 u8 reserved_at_20[0x10]; 6060 u8 op_mod[0x10]; 6061 6062 u8 reserved_at_40[0x10]; 6063 u8 function_id[0x10]; 6064 u8 field_select[0x20]; 6065 6066 struct mlx5_ifc_other_hca_cap_bits other_capability; 6067 }; 6068 6069 struct mlx5_ifc_flow_table_context_bits { 6070 u8 reformat_en[0x1]; 6071 u8 decap_en[0x1]; 6072 u8 sw_owner[0x1]; 6073 u8 termination_table[0x1]; 6074 u8 table_miss_action[0x4]; 6075 u8 level[0x8]; 6076 u8 reserved_at_10[0x8]; 6077 u8 log_size[0x8]; 6078 6079 u8 reserved_at_20[0x8]; 6080 u8 table_miss_id[0x18]; 6081 6082 u8 reserved_at_40[0x8]; 6083 u8 lag_master_next_table_id[0x18]; 6084 6085 u8 reserved_at_60[0x60]; 6086 6087 u8 sw_owner_icm_root_1[0x40]; 6088 6089 u8 sw_owner_icm_root_0[0x40]; 6090 6091 }; 6092 6093 struct mlx5_ifc_query_flow_table_out_bits { 6094 u8 status[0x8]; 6095 u8 reserved_at_8[0x18]; 6096 6097 u8 syndrome[0x20]; 6098 6099 u8 reserved_at_40[0x80]; 6100 6101 struct mlx5_ifc_flow_table_context_bits flow_table_context; 6102 }; 6103 6104 struct mlx5_ifc_query_flow_table_in_bits { 6105 u8 opcode[0x10]; 6106 u8 reserved_at_10[0x10]; 6107 6108 u8 reserved_at_20[0x10]; 6109 u8 op_mod[0x10]; 6110 6111 u8 reserved_at_40[0x40]; 6112 6113 u8 table_type[0x8]; 6114 u8 reserved_at_88[0x18]; 6115 6116 u8 reserved_at_a0[0x8]; 6117 u8 table_id[0x18]; 6118 6119 u8 reserved_at_c0[0x140]; 6120 }; 6121 6122 struct mlx5_ifc_query_fte_out_bits { 6123 u8 status[0x8]; 6124 u8 reserved_at_8[0x18]; 6125 6126 u8 syndrome[0x20]; 6127 6128 u8 reserved_at_40[0x1c0]; 6129 6130 struct mlx5_ifc_flow_context_bits flow_context; 6131 }; 6132 6133 struct mlx5_ifc_query_fte_in_bits { 6134 u8 opcode[0x10]; 6135 u8 reserved_at_10[0x10]; 6136 6137 u8 reserved_at_20[0x10]; 6138 u8 op_mod[0x10]; 6139 6140 u8 reserved_at_40[0x40]; 6141 6142 u8 table_type[0x8]; 6143 u8 reserved_at_88[0x18]; 6144 6145 u8 reserved_at_a0[0x8]; 6146 u8 table_id[0x18]; 6147 6148 u8 reserved_at_c0[0x40]; 6149 6150 u8 flow_index[0x20]; 6151 6152 u8 reserved_at_120[0xe0]; 6153 }; 6154 6155 struct mlx5_ifc_match_definer_format_0_bits { 6156 u8 reserved_at_0[0x100]; 6157 6158 u8 metadata_reg_c_0[0x20]; 6159 6160 u8 metadata_reg_c_1[0x20]; 6161 6162 u8 outer_dmac_47_16[0x20]; 6163 6164 u8 outer_dmac_15_0[0x10]; 6165 u8 outer_ethertype[0x10]; 6166 6167 u8 reserved_at_180[0x1]; 6168 u8 sx_sniffer[0x1]; 6169 u8 functional_lb[0x1]; 6170 u8 outer_ip_frag[0x1]; 6171 u8 outer_qp_type[0x2]; 6172 u8 outer_encap_type[0x2]; 6173 u8 port_number[0x2]; 6174 u8 outer_l3_type[0x2]; 6175 u8 outer_l4_type[0x2]; 6176 u8 outer_first_vlan_type[0x2]; 6177 u8 outer_first_vlan_prio[0x3]; 6178 u8 outer_first_vlan_cfi[0x1]; 6179 u8 outer_first_vlan_vid[0xc]; 6180 6181 u8 outer_l4_type_ext[0x4]; 6182 u8 reserved_at_1a4[0x2]; 6183 u8 outer_ipsec_layer[0x2]; 6184 u8 outer_l2_type[0x2]; 6185 u8 force_lb[0x1]; 6186 u8 outer_l2_ok[0x1]; 6187 u8 outer_l3_ok[0x1]; 6188 u8 outer_l4_ok[0x1]; 6189 u8 outer_second_vlan_type[0x2]; 6190 u8 outer_second_vlan_prio[0x3]; 6191 u8 outer_second_vlan_cfi[0x1]; 6192 u8 outer_second_vlan_vid[0xc]; 6193 6194 u8 outer_smac_47_16[0x20]; 6195 6196 u8 outer_smac_15_0[0x10]; 6197 u8 inner_ipv4_checksum_ok[0x1]; 6198 u8 inner_l4_checksum_ok[0x1]; 6199 u8 outer_ipv4_checksum_ok[0x1]; 6200 u8 outer_l4_checksum_ok[0x1]; 6201 u8 inner_l3_ok[0x1]; 6202 u8 inner_l4_ok[0x1]; 6203 u8 outer_l3_ok_duplicate[0x1]; 6204 u8 outer_l4_ok_duplicate[0x1]; 6205 u8 outer_tcp_cwr[0x1]; 6206 u8 outer_tcp_ece[0x1]; 6207 u8 outer_tcp_urg[0x1]; 6208 u8 outer_tcp_ack[0x1]; 6209 u8 outer_tcp_psh[0x1]; 6210 u8 outer_tcp_rst[0x1]; 6211 u8 outer_tcp_syn[0x1]; 6212 u8 outer_tcp_fin[0x1]; 6213 }; 6214 6215 struct mlx5_ifc_match_definer_format_22_bits { 6216 u8 reserved_at_0[0x100]; 6217 6218 u8 outer_ip_src_addr[0x20]; 6219 6220 u8 outer_ip_dest_addr[0x20]; 6221 6222 u8 outer_l4_sport[0x10]; 6223 u8 outer_l4_dport[0x10]; 6224 6225 u8 reserved_at_160[0x1]; 6226 u8 sx_sniffer[0x1]; 6227 u8 functional_lb[0x1]; 6228 u8 outer_ip_frag[0x1]; 6229 u8 outer_qp_type[0x2]; 6230 u8 outer_encap_type[0x2]; 6231 u8 port_number[0x2]; 6232 u8 outer_l3_type[0x2]; 6233 u8 outer_l4_type[0x2]; 6234 u8 outer_first_vlan_type[0x2]; 6235 u8 outer_first_vlan_prio[0x3]; 6236 u8 outer_first_vlan_cfi[0x1]; 6237 u8 outer_first_vlan_vid[0xc]; 6238 6239 u8 metadata_reg_c_0[0x20]; 6240 6241 u8 outer_dmac_47_16[0x20]; 6242 6243 u8 outer_smac_47_16[0x20]; 6244 6245 u8 outer_smac_15_0[0x10]; 6246 u8 outer_dmac_15_0[0x10]; 6247 }; 6248 6249 struct mlx5_ifc_match_definer_format_23_bits { 6250 u8 reserved_at_0[0x100]; 6251 6252 u8 inner_ip_src_addr[0x20]; 6253 6254 u8 inner_ip_dest_addr[0x20]; 6255 6256 u8 inner_l4_sport[0x10]; 6257 u8 inner_l4_dport[0x10]; 6258 6259 u8 reserved_at_160[0x1]; 6260 u8 sx_sniffer[0x1]; 6261 u8 functional_lb[0x1]; 6262 u8 inner_ip_frag[0x1]; 6263 u8 inner_qp_type[0x2]; 6264 u8 inner_encap_type[0x2]; 6265 u8 port_number[0x2]; 6266 u8 inner_l3_type[0x2]; 6267 u8 inner_l4_type[0x2]; 6268 u8 inner_first_vlan_type[0x2]; 6269 u8 inner_first_vlan_prio[0x3]; 6270 u8 inner_first_vlan_cfi[0x1]; 6271 u8 inner_first_vlan_vid[0xc]; 6272 6273 u8 tunnel_header_0[0x20]; 6274 6275 u8 inner_dmac_47_16[0x20]; 6276 6277 u8 inner_smac_47_16[0x20]; 6278 6279 u8 inner_smac_15_0[0x10]; 6280 u8 inner_dmac_15_0[0x10]; 6281 }; 6282 6283 struct mlx5_ifc_match_definer_format_29_bits { 6284 u8 reserved_at_0[0xc0]; 6285 6286 u8 outer_ip_dest_addr[0x80]; 6287 6288 u8 outer_ip_src_addr[0x80]; 6289 6290 u8 outer_l4_sport[0x10]; 6291 u8 outer_l4_dport[0x10]; 6292 6293 u8 reserved_at_1e0[0x20]; 6294 }; 6295 6296 struct mlx5_ifc_match_definer_format_30_bits { 6297 u8 reserved_at_0[0xa0]; 6298 6299 u8 outer_ip_dest_addr[0x80]; 6300 6301 u8 outer_ip_src_addr[0x80]; 6302 6303 u8 outer_dmac_47_16[0x20]; 6304 6305 u8 outer_smac_47_16[0x20]; 6306 6307 u8 outer_smac_15_0[0x10]; 6308 u8 outer_dmac_15_0[0x10]; 6309 }; 6310 6311 struct mlx5_ifc_match_definer_format_31_bits { 6312 u8 reserved_at_0[0xc0]; 6313 6314 u8 inner_ip_dest_addr[0x80]; 6315 6316 u8 inner_ip_src_addr[0x80]; 6317 6318 u8 inner_l4_sport[0x10]; 6319 u8 inner_l4_dport[0x10]; 6320 6321 u8 reserved_at_1e0[0x20]; 6322 }; 6323 6324 struct mlx5_ifc_match_definer_format_32_bits { 6325 u8 reserved_at_0[0xa0]; 6326 6327 u8 inner_ip_dest_addr[0x80]; 6328 6329 u8 inner_ip_src_addr[0x80]; 6330 6331 u8 inner_dmac_47_16[0x20]; 6332 6333 u8 inner_smac_47_16[0x20]; 6334 6335 u8 inner_smac_15_0[0x10]; 6336 u8 inner_dmac_15_0[0x10]; 6337 }; 6338 6339 enum { 6340 MLX5_IFC_DEFINER_FORMAT_ID_SELECT = 61, 6341 }; 6342 6343 #define MLX5_IFC_DEFINER_FORMAT_OFFSET_UNUSED 0x0 6344 #define MLX5_IFC_DEFINER_FORMAT_OFFSET_OUTER_ETH_PKT_LEN 0x48 6345 #define MLX5_IFC_DEFINER_DW_SELECTORS_NUM 9 6346 #define MLX5_IFC_DEFINER_BYTE_SELECTORS_NUM 8 6347 6348 struct mlx5_ifc_match_definer_match_mask_bits { 6349 u8 reserved_at_1c0[5][0x20]; 6350 u8 match_dw_8[0x20]; 6351 u8 match_dw_7[0x20]; 6352 u8 match_dw_6[0x20]; 6353 u8 match_dw_5[0x20]; 6354 u8 match_dw_4[0x20]; 6355 u8 match_dw_3[0x20]; 6356 u8 match_dw_2[0x20]; 6357 u8 match_dw_1[0x20]; 6358 u8 match_dw_0[0x20]; 6359 6360 u8 match_byte_7[0x8]; 6361 u8 match_byte_6[0x8]; 6362 u8 match_byte_5[0x8]; 6363 u8 match_byte_4[0x8]; 6364 6365 u8 match_byte_3[0x8]; 6366 u8 match_byte_2[0x8]; 6367 u8 match_byte_1[0x8]; 6368 u8 match_byte_0[0x8]; 6369 }; 6370 6371 struct mlx5_ifc_match_definer_bits { 6372 u8 modify_field_select[0x40]; 6373 6374 u8 reserved_at_40[0x40]; 6375 6376 u8 reserved_at_80[0x10]; 6377 u8 format_id[0x10]; 6378 6379 u8 reserved_at_a0[0x60]; 6380 6381 u8 format_select_dw3[0x8]; 6382 u8 format_select_dw2[0x8]; 6383 u8 format_select_dw1[0x8]; 6384 u8 format_select_dw0[0x8]; 6385 6386 u8 format_select_dw7[0x8]; 6387 u8 format_select_dw6[0x8]; 6388 u8 format_select_dw5[0x8]; 6389 u8 format_select_dw4[0x8]; 6390 6391 u8 reserved_at_100[0x18]; 6392 u8 format_select_dw8[0x8]; 6393 6394 u8 reserved_at_120[0x20]; 6395 6396 u8 format_select_byte3[0x8]; 6397 u8 format_select_byte2[0x8]; 6398 u8 format_select_byte1[0x8]; 6399 u8 format_select_byte0[0x8]; 6400 6401 u8 format_select_byte7[0x8]; 6402 u8 format_select_byte6[0x8]; 6403 u8 format_select_byte5[0x8]; 6404 u8 format_select_byte4[0x8]; 6405 6406 u8 reserved_at_180[0x40]; 6407 6408 union { 6409 struct { 6410 u8 match_mask[16][0x20]; 6411 }; 6412 struct mlx5_ifc_match_definer_match_mask_bits match_mask_format; 6413 }; 6414 }; 6415 6416 struct mlx5_ifc_general_obj_create_param_bits { 6417 u8 alias_object[0x1]; 6418 u8 reserved_at_1[0x2]; 6419 u8 log_obj_range[0x5]; 6420 u8 reserved_at_8[0x18]; 6421 }; 6422 6423 struct mlx5_ifc_general_obj_query_param_bits { 6424 u8 alias_object[0x1]; 6425 u8 obj_offset[0x1f]; 6426 }; 6427 6428 struct mlx5_ifc_general_obj_in_cmd_hdr_bits { 6429 u8 opcode[0x10]; 6430 u8 uid[0x10]; 6431 6432 u8 vhca_tunnel_id[0x10]; 6433 u8 obj_type[0x10]; 6434 6435 u8 obj_id[0x20]; 6436 6437 union { 6438 struct mlx5_ifc_general_obj_create_param_bits create; 6439 struct mlx5_ifc_general_obj_query_param_bits query; 6440 } op_param; 6441 }; 6442 6443 struct mlx5_ifc_general_obj_out_cmd_hdr_bits { 6444 u8 status[0x8]; 6445 u8 reserved_at_8[0x18]; 6446 6447 u8 syndrome[0x20]; 6448 6449 u8 obj_id[0x20]; 6450 6451 u8 reserved_at_60[0x20]; 6452 }; 6453 6454 struct mlx5_ifc_allow_other_vhca_access_in_bits { 6455 u8 opcode[0x10]; 6456 u8 uid[0x10]; 6457 u8 reserved_at_20[0x10]; 6458 u8 op_mod[0x10]; 6459 u8 reserved_at_40[0x50]; 6460 u8 object_type_to_be_accessed[0x10]; 6461 u8 object_id_to_be_accessed[0x20]; 6462 u8 reserved_at_c0[0x40]; 6463 union { 6464 u8 access_key_raw[0x100]; 6465 u8 access_key[8][0x20]; 6466 }; 6467 }; 6468 6469 struct mlx5_ifc_allow_other_vhca_access_out_bits { 6470 u8 status[0x8]; 6471 u8 reserved_at_8[0x18]; 6472 u8 syndrome[0x20]; 6473 u8 reserved_at_40[0x40]; 6474 }; 6475 6476 struct mlx5_ifc_modify_header_arg_bits { 6477 u8 reserved_at_0[0x80]; 6478 6479 u8 reserved_at_80[0x8]; 6480 u8 access_pd[0x18]; 6481 }; 6482 6483 struct mlx5_ifc_create_modify_header_arg_in_bits { 6484 struct mlx5_ifc_general_obj_in_cmd_hdr_bits hdr; 6485 struct mlx5_ifc_modify_header_arg_bits arg; 6486 }; 6487 6488 struct mlx5_ifc_create_match_definer_in_bits { 6489 struct mlx5_ifc_general_obj_in_cmd_hdr_bits general_obj_in_cmd_hdr; 6490 6491 struct mlx5_ifc_match_definer_bits obj_context; 6492 }; 6493 6494 struct mlx5_ifc_create_match_definer_out_bits { 6495 struct mlx5_ifc_general_obj_out_cmd_hdr_bits general_obj_out_cmd_hdr; 6496 }; 6497 6498 struct mlx5_ifc_alias_context_bits { 6499 u8 vhca_id_to_be_accessed[0x10]; 6500 u8 reserved_at_10[0xd]; 6501 u8 status[0x3]; 6502 u8 object_id_to_be_accessed[0x20]; 6503 u8 reserved_at_40[0x40]; 6504 union { 6505 u8 access_key_raw[0x100]; 6506 u8 access_key[8][0x20]; 6507 }; 6508 u8 metadata[0x80]; 6509 }; 6510 6511 struct mlx5_ifc_create_alias_obj_in_bits { 6512 struct mlx5_ifc_general_obj_in_cmd_hdr_bits hdr; 6513 struct mlx5_ifc_alias_context_bits alias_ctx; 6514 }; 6515 6516 enum { 6517 MLX5_QUERY_FLOW_GROUP_OUT_MATCH_CRITERIA_ENABLE_OUTER_HEADERS = 0x0, 6518 MLX5_QUERY_FLOW_GROUP_OUT_MATCH_CRITERIA_ENABLE_MISC_PARAMETERS = 0x1, 6519 MLX5_QUERY_FLOW_GROUP_OUT_MATCH_CRITERIA_ENABLE_INNER_HEADERS = 0x2, 6520 MLX5_QUERY_FLOW_GROUP_IN_MATCH_CRITERIA_ENABLE_MISC_PARAMETERS_2 = 0x3, 6521 MLX5_QUERY_FLOW_GROUP_IN_MATCH_CRITERIA_ENABLE_MISC_PARAMETERS_3 = 0x4, 6522 MLX5_QUERY_FLOW_GROUP_IN_MATCH_CRITERIA_ENABLE_MISC_PARAMETERS_4 = 0x5, 6523 MLX5_QUERY_FLOW_GROUP_IN_MATCH_CRITERIA_ENABLE_MISC_PARAMETERS_5 = 0x6, 6524 }; 6525 6526 struct mlx5_ifc_query_flow_group_out_bits { 6527 u8 status[0x8]; 6528 u8 reserved_at_8[0x18]; 6529 6530 u8 syndrome[0x20]; 6531 6532 u8 reserved_at_40[0xa0]; 6533 6534 u8 start_flow_index[0x20]; 6535 6536 u8 reserved_at_100[0x20]; 6537 6538 u8 end_flow_index[0x20]; 6539 6540 u8 reserved_at_140[0xa0]; 6541 6542 u8 reserved_at_1e0[0x18]; 6543 u8 match_criteria_enable[0x8]; 6544 6545 struct mlx5_ifc_fte_match_param_bits match_criteria; 6546 6547 u8 reserved_at_1200[0xe00]; 6548 }; 6549 6550 struct mlx5_ifc_query_flow_group_in_bits { 6551 u8 opcode[0x10]; 6552 u8 reserved_at_10[0x10]; 6553 6554 u8 reserved_at_20[0x10]; 6555 u8 op_mod[0x10]; 6556 6557 u8 reserved_at_40[0x40]; 6558 6559 u8 table_type[0x8]; 6560 u8 reserved_at_88[0x18]; 6561 6562 u8 reserved_at_a0[0x8]; 6563 u8 table_id[0x18]; 6564 6565 u8 group_id[0x20]; 6566 6567 u8 reserved_at_e0[0x120]; 6568 }; 6569 6570 struct mlx5_ifc_query_flow_counter_out_bits { 6571 u8 status[0x8]; 6572 u8 reserved_at_8[0x18]; 6573 6574 u8 syndrome[0x20]; 6575 6576 u8 reserved_at_40[0x40]; 6577 6578 struct mlx5_ifc_traffic_counter_bits flow_statistics[]; 6579 }; 6580 6581 struct mlx5_ifc_query_flow_counter_in_bits { 6582 u8 opcode[0x10]; 6583 u8 reserved_at_10[0x10]; 6584 6585 u8 reserved_at_20[0x10]; 6586 u8 op_mod[0x10]; 6587 6588 u8 reserved_at_40[0x80]; 6589 6590 u8 clear[0x1]; 6591 u8 reserved_at_c1[0xf]; 6592 u8 num_of_counters[0x10]; 6593 6594 u8 flow_counter_id[0x20]; 6595 }; 6596 6597 struct mlx5_ifc_query_esw_vport_context_out_bits { 6598 u8 status[0x8]; 6599 u8 reserved_at_8[0x18]; 6600 6601 u8 syndrome[0x20]; 6602 6603 u8 reserved_at_40[0x40]; 6604 6605 struct mlx5_ifc_esw_vport_context_bits esw_vport_context; 6606 }; 6607 6608 struct mlx5_ifc_query_esw_vport_context_in_bits { 6609 u8 opcode[0x10]; 6610 u8 reserved_at_10[0x10]; 6611 6612 u8 reserved_at_20[0x10]; 6613 u8 op_mod[0x10]; 6614 6615 u8 other_vport[0x1]; 6616 u8 reserved_at_41[0xf]; 6617 u8 vport_number[0x10]; 6618 6619 u8 reserved_at_60[0x20]; 6620 }; 6621 6622 struct mlx5_ifc_modify_esw_vport_context_out_bits { 6623 u8 status[0x8]; 6624 u8 reserved_at_8[0x18]; 6625 6626 u8 syndrome[0x20]; 6627 6628 u8 reserved_at_40[0x40]; 6629 }; 6630 6631 struct mlx5_ifc_esw_vport_context_fields_select_bits { 6632 u8 reserved_at_0[0x1b]; 6633 u8 fdb_to_vport_reg_c_id[0x1]; 6634 u8 vport_cvlan_insert[0x1]; 6635 u8 vport_svlan_insert[0x1]; 6636 u8 vport_cvlan_strip[0x1]; 6637 u8 vport_svlan_strip[0x1]; 6638 }; 6639 6640 struct mlx5_ifc_modify_esw_vport_context_in_bits { 6641 u8 opcode[0x10]; 6642 u8 reserved_at_10[0x10]; 6643 6644 u8 reserved_at_20[0x10]; 6645 u8 op_mod[0x10]; 6646 6647 u8 other_vport[0x1]; 6648 u8 reserved_at_41[0xf]; 6649 u8 vport_number[0x10]; 6650 6651 struct mlx5_ifc_esw_vport_context_fields_select_bits field_select; 6652 6653 struct mlx5_ifc_esw_vport_context_bits esw_vport_context; 6654 }; 6655 6656 struct mlx5_ifc_query_eq_out_bits { 6657 u8 status[0x8]; 6658 u8 reserved_at_8[0x18]; 6659 6660 u8 syndrome[0x20]; 6661 6662 u8 reserved_at_40[0x40]; 6663 6664 struct mlx5_ifc_eqc_bits eq_context_entry; 6665 6666 u8 reserved_at_280[0x40]; 6667 6668 u8 event_bitmask[0x40]; 6669 6670 u8 reserved_at_300[0x580]; 6671 6672 u8 pas[][0x40]; 6673 }; 6674 6675 struct mlx5_ifc_query_eq_in_bits { 6676 u8 opcode[0x10]; 6677 u8 reserved_at_10[0x10]; 6678 6679 u8 reserved_at_20[0x10]; 6680 u8 op_mod[0x10]; 6681 6682 u8 reserved_at_40[0x18]; 6683 u8 eq_number[0x8]; 6684 6685 u8 reserved_at_60[0x20]; 6686 }; 6687 6688 struct mlx5_ifc_packet_reformat_context_in_bits { 6689 u8 reformat_type[0x8]; 6690 u8 reserved_at_8[0x4]; 6691 u8 reformat_param_0[0x4]; 6692 u8 reserved_at_10[0x6]; 6693 u8 reformat_data_size[0xa]; 6694 6695 u8 reformat_param_1[0x8]; 6696 u8 reserved_at_28[0x8]; 6697 u8 reformat_data[2][0x8]; 6698 6699 u8 more_reformat_data[][0x8]; 6700 }; 6701 6702 struct mlx5_ifc_query_packet_reformat_context_out_bits { 6703 u8 status[0x8]; 6704 u8 reserved_at_8[0x18]; 6705 6706 u8 syndrome[0x20]; 6707 6708 u8 reserved_at_40[0xa0]; 6709 6710 struct mlx5_ifc_packet_reformat_context_in_bits packet_reformat_context[]; 6711 }; 6712 6713 struct mlx5_ifc_query_packet_reformat_context_in_bits { 6714 u8 opcode[0x10]; 6715 u8 reserved_at_10[0x10]; 6716 6717 u8 reserved_at_20[0x10]; 6718 u8 op_mod[0x10]; 6719 6720 u8 packet_reformat_id[0x20]; 6721 6722 u8 reserved_at_60[0xa0]; 6723 }; 6724 6725 struct mlx5_ifc_alloc_packet_reformat_context_out_bits { 6726 u8 status[0x8]; 6727 u8 reserved_at_8[0x18]; 6728 6729 u8 syndrome[0x20]; 6730 6731 u8 packet_reformat_id[0x20]; 6732 6733 u8 reserved_at_60[0x20]; 6734 }; 6735 6736 enum { 6737 MLX5_REFORMAT_CONTEXT_ANCHOR_MAC_START = 0x1, 6738 MLX5_REFORMAT_CONTEXT_ANCHOR_IP_START = 0x7, 6739 MLX5_REFORMAT_CONTEXT_ANCHOR_TCP_UDP_START = 0x9, 6740 }; 6741 6742 enum mlx5_reformat_ctx_type { 6743 MLX5_REFORMAT_TYPE_L2_TO_VXLAN = 0x0, 6744 MLX5_REFORMAT_TYPE_L2_TO_NVGRE = 0x1, 6745 MLX5_REFORMAT_TYPE_L2_TO_L2_TUNNEL = 0x2, 6746 MLX5_REFORMAT_TYPE_L3_TUNNEL_TO_L2 = 0x3, 6747 MLX5_REFORMAT_TYPE_L2_TO_L3_TUNNEL = 0x4, 6748 MLX5_REFORMAT_TYPE_ADD_ESP_TRANSPORT_OVER_IPV4 = 0x5, 6749 MLX5_REFORMAT_TYPE_L2_TO_L3_ESP_TUNNEL = 0x6, 6750 MLX5_REFORMAT_TYPE_ADD_ESP_TRANSPORT_OVER_UDPV4 = 0x7, 6751 MLX5_REFORMAT_TYPE_DEL_ESP_TRANSPORT = 0x8, 6752 MLX5_REFORMAT_TYPE_L3_ESP_TUNNEL_TO_L2 = 0x9, 6753 MLX5_REFORMAT_TYPE_DEL_ESP_TRANSPORT_OVER_UDP = 0xa, 6754 MLX5_REFORMAT_TYPE_ADD_ESP_TRANSPORT_OVER_IPV6 = 0xb, 6755 MLX5_REFORMAT_TYPE_ADD_ESP_TRANSPORT_OVER_UDPV6 = 0xc, 6756 MLX5_REFORMAT_TYPE_INSERT_HDR = 0xf, 6757 MLX5_REFORMAT_TYPE_REMOVE_HDR = 0x10, 6758 MLX5_REFORMAT_TYPE_ADD_MACSEC = 0x11, 6759 MLX5_REFORMAT_TYPE_DEL_MACSEC = 0x12, 6760 }; 6761 6762 struct mlx5_ifc_alloc_packet_reformat_context_in_bits { 6763 u8 opcode[0x10]; 6764 u8 reserved_at_10[0x10]; 6765 6766 u8 reserved_at_20[0x10]; 6767 u8 op_mod[0x10]; 6768 6769 u8 reserved_at_40[0xa0]; 6770 6771 struct mlx5_ifc_packet_reformat_context_in_bits packet_reformat_context; 6772 }; 6773 6774 struct mlx5_ifc_dealloc_packet_reformat_context_out_bits { 6775 u8 status[0x8]; 6776 u8 reserved_at_8[0x18]; 6777 6778 u8 syndrome[0x20]; 6779 6780 u8 reserved_at_40[0x40]; 6781 }; 6782 6783 struct mlx5_ifc_dealloc_packet_reformat_context_in_bits { 6784 u8 opcode[0x10]; 6785 u8 reserved_at_10[0x10]; 6786 6787 u8 reserved_20[0x10]; 6788 u8 op_mod[0x10]; 6789 6790 u8 packet_reformat_id[0x20]; 6791 6792 u8 reserved_60[0x20]; 6793 }; 6794 6795 struct mlx5_ifc_set_action_in_bits { 6796 u8 action_type[0x4]; 6797 u8 field[0xc]; 6798 u8 reserved_at_10[0x3]; 6799 u8 offset[0x5]; 6800 u8 reserved_at_18[0x3]; 6801 u8 length[0x5]; 6802 6803 u8 data[0x20]; 6804 }; 6805 6806 struct mlx5_ifc_add_action_in_bits { 6807 u8 action_type[0x4]; 6808 u8 field[0xc]; 6809 u8 reserved_at_10[0x10]; 6810 6811 u8 data[0x20]; 6812 }; 6813 6814 struct mlx5_ifc_copy_action_in_bits { 6815 u8 action_type[0x4]; 6816 u8 src_field[0xc]; 6817 u8 reserved_at_10[0x3]; 6818 u8 src_offset[0x5]; 6819 u8 reserved_at_18[0x3]; 6820 u8 length[0x5]; 6821 6822 u8 reserved_at_20[0x4]; 6823 u8 dst_field[0xc]; 6824 u8 reserved_at_30[0x3]; 6825 u8 dst_offset[0x5]; 6826 u8 reserved_at_38[0x8]; 6827 }; 6828 6829 union mlx5_ifc_set_add_copy_action_in_auto_bits { 6830 struct mlx5_ifc_set_action_in_bits set_action_in; 6831 struct mlx5_ifc_add_action_in_bits add_action_in; 6832 struct mlx5_ifc_copy_action_in_bits copy_action_in; 6833 u8 reserved_at_0[0x40]; 6834 }; 6835 6836 enum { 6837 MLX5_ACTION_TYPE_SET = 0x1, 6838 MLX5_ACTION_TYPE_ADD = 0x2, 6839 MLX5_ACTION_TYPE_COPY = 0x3, 6840 }; 6841 6842 enum { 6843 MLX5_ACTION_IN_FIELD_OUT_SMAC_47_16 = 0x1, 6844 MLX5_ACTION_IN_FIELD_OUT_SMAC_15_0 = 0x2, 6845 MLX5_ACTION_IN_FIELD_OUT_ETHERTYPE = 0x3, 6846 MLX5_ACTION_IN_FIELD_OUT_DMAC_47_16 = 0x4, 6847 MLX5_ACTION_IN_FIELD_OUT_DMAC_15_0 = 0x5, 6848 MLX5_ACTION_IN_FIELD_OUT_IP_DSCP = 0x6, 6849 MLX5_ACTION_IN_FIELD_OUT_TCP_FLAGS = 0x7, 6850 MLX5_ACTION_IN_FIELD_OUT_TCP_SPORT = 0x8, 6851 MLX5_ACTION_IN_FIELD_OUT_TCP_DPORT = 0x9, 6852 MLX5_ACTION_IN_FIELD_OUT_IP_TTL = 0xa, 6853 MLX5_ACTION_IN_FIELD_OUT_UDP_SPORT = 0xb, 6854 MLX5_ACTION_IN_FIELD_OUT_UDP_DPORT = 0xc, 6855 MLX5_ACTION_IN_FIELD_OUT_SIPV6_127_96 = 0xd, 6856 MLX5_ACTION_IN_FIELD_OUT_SIPV6_95_64 = 0xe, 6857 MLX5_ACTION_IN_FIELD_OUT_SIPV6_63_32 = 0xf, 6858 MLX5_ACTION_IN_FIELD_OUT_SIPV6_31_0 = 0x10, 6859 MLX5_ACTION_IN_FIELD_OUT_DIPV6_127_96 = 0x11, 6860 MLX5_ACTION_IN_FIELD_OUT_DIPV6_95_64 = 0x12, 6861 MLX5_ACTION_IN_FIELD_OUT_DIPV6_63_32 = 0x13, 6862 MLX5_ACTION_IN_FIELD_OUT_DIPV6_31_0 = 0x14, 6863 MLX5_ACTION_IN_FIELD_OUT_SIPV4 = 0x15, 6864 MLX5_ACTION_IN_FIELD_OUT_DIPV4 = 0x16, 6865 MLX5_ACTION_IN_FIELD_OUT_FIRST_VID = 0x17, 6866 MLX5_ACTION_IN_FIELD_OUT_IPV6_HOPLIMIT = 0x47, 6867 MLX5_ACTION_IN_FIELD_METADATA_REG_A = 0x49, 6868 MLX5_ACTION_IN_FIELD_METADATA_REG_B = 0x50, 6869 MLX5_ACTION_IN_FIELD_METADATA_REG_C_0 = 0x51, 6870 MLX5_ACTION_IN_FIELD_METADATA_REG_C_1 = 0x52, 6871 MLX5_ACTION_IN_FIELD_METADATA_REG_C_2 = 0x53, 6872 MLX5_ACTION_IN_FIELD_METADATA_REG_C_3 = 0x54, 6873 MLX5_ACTION_IN_FIELD_METADATA_REG_C_4 = 0x55, 6874 MLX5_ACTION_IN_FIELD_METADATA_REG_C_5 = 0x56, 6875 MLX5_ACTION_IN_FIELD_METADATA_REG_C_6 = 0x57, 6876 MLX5_ACTION_IN_FIELD_METADATA_REG_C_7 = 0x58, 6877 MLX5_ACTION_IN_FIELD_OUT_TCP_SEQ_NUM = 0x59, 6878 MLX5_ACTION_IN_FIELD_OUT_TCP_ACK_NUM = 0x5B, 6879 MLX5_ACTION_IN_FIELD_IPSEC_SYNDROME = 0x5D, 6880 MLX5_ACTION_IN_FIELD_OUT_EMD_47_32 = 0x6F, 6881 MLX5_ACTION_IN_FIELD_OUT_EMD_31_0 = 0x70, 6882 }; 6883 6884 struct mlx5_ifc_alloc_modify_header_context_out_bits { 6885 u8 status[0x8]; 6886 u8 reserved_at_8[0x18]; 6887 6888 u8 syndrome[0x20]; 6889 6890 u8 modify_header_id[0x20]; 6891 6892 u8 reserved_at_60[0x20]; 6893 }; 6894 6895 struct mlx5_ifc_alloc_modify_header_context_in_bits { 6896 u8 opcode[0x10]; 6897 u8 reserved_at_10[0x10]; 6898 6899 u8 reserved_at_20[0x10]; 6900 u8 op_mod[0x10]; 6901 6902 u8 reserved_at_40[0x20]; 6903 6904 u8 table_type[0x8]; 6905 u8 reserved_at_68[0x10]; 6906 u8 num_of_actions[0x8]; 6907 6908 union mlx5_ifc_set_add_copy_action_in_auto_bits actions[]; 6909 }; 6910 6911 struct mlx5_ifc_dealloc_modify_header_context_out_bits { 6912 u8 status[0x8]; 6913 u8 reserved_at_8[0x18]; 6914 6915 u8 syndrome[0x20]; 6916 6917 u8 reserved_at_40[0x40]; 6918 }; 6919 6920 struct mlx5_ifc_dealloc_modify_header_context_in_bits { 6921 u8 opcode[0x10]; 6922 u8 reserved_at_10[0x10]; 6923 6924 u8 reserved_at_20[0x10]; 6925 u8 op_mod[0x10]; 6926 6927 u8 modify_header_id[0x20]; 6928 6929 u8 reserved_at_60[0x20]; 6930 }; 6931 6932 struct mlx5_ifc_query_modify_header_context_in_bits { 6933 u8 opcode[0x10]; 6934 u8 uid[0x10]; 6935 6936 u8 reserved_at_20[0x10]; 6937 u8 op_mod[0x10]; 6938 6939 u8 modify_header_id[0x20]; 6940 6941 u8 reserved_at_60[0xa0]; 6942 }; 6943 6944 struct mlx5_ifc_query_dct_out_bits { 6945 u8 status[0x8]; 6946 u8 reserved_at_8[0x18]; 6947 6948 u8 syndrome[0x20]; 6949 6950 u8 reserved_at_40[0x40]; 6951 6952 struct mlx5_ifc_dctc_bits dct_context_entry; 6953 6954 u8 reserved_at_280[0x180]; 6955 }; 6956 6957 struct mlx5_ifc_query_dct_in_bits { 6958 u8 opcode[0x10]; 6959 u8 reserved_at_10[0x10]; 6960 6961 u8 reserved_at_20[0x10]; 6962 u8 op_mod[0x10]; 6963 6964 u8 reserved_at_40[0x8]; 6965 u8 dctn[0x18]; 6966 6967 u8 reserved_at_60[0x20]; 6968 }; 6969 6970 struct mlx5_ifc_query_cq_out_bits { 6971 u8 status[0x8]; 6972 u8 reserved_at_8[0x18]; 6973 6974 u8 syndrome[0x20]; 6975 6976 u8 reserved_at_40[0x40]; 6977 6978 struct mlx5_ifc_cqc_bits cq_context; 6979 6980 u8 reserved_at_280[0x600]; 6981 6982 u8 pas[][0x40]; 6983 }; 6984 6985 struct mlx5_ifc_query_cq_in_bits { 6986 u8 opcode[0x10]; 6987 u8 reserved_at_10[0x10]; 6988 6989 u8 reserved_at_20[0x10]; 6990 u8 op_mod[0x10]; 6991 6992 u8 reserved_at_40[0x8]; 6993 u8 cqn[0x18]; 6994 6995 u8 reserved_at_60[0x20]; 6996 }; 6997 6998 struct mlx5_ifc_query_cong_status_out_bits { 6999 u8 status[0x8]; 7000 u8 reserved_at_8[0x18]; 7001 7002 u8 syndrome[0x20]; 7003 7004 u8 reserved_at_40[0x20]; 7005 7006 u8 enable[0x1]; 7007 u8 tag_enable[0x1]; 7008 u8 reserved_at_62[0x1e]; 7009 }; 7010 7011 struct mlx5_ifc_query_cong_status_in_bits { 7012 u8 opcode[0x10]; 7013 u8 reserved_at_10[0x10]; 7014 7015 u8 reserved_at_20[0x10]; 7016 u8 op_mod[0x10]; 7017 7018 u8 reserved_at_40[0x18]; 7019 u8 priority[0x4]; 7020 u8 cong_protocol[0x4]; 7021 7022 u8 reserved_at_60[0x20]; 7023 }; 7024 7025 struct mlx5_ifc_query_cong_statistics_out_bits { 7026 u8 status[0x8]; 7027 u8 reserved_at_8[0x18]; 7028 7029 u8 syndrome[0x20]; 7030 7031 u8 reserved_at_40[0x40]; 7032 7033 u8 rp_cur_flows[0x20]; 7034 7035 u8 sum_flows[0x20]; 7036 7037 u8 rp_cnp_ignored_high[0x20]; 7038 7039 u8 rp_cnp_ignored_low[0x20]; 7040 7041 u8 rp_cnp_handled_high[0x20]; 7042 7043 u8 rp_cnp_handled_low[0x20]; 7044 7045 u8 reserved_at_140[0x100]; 7046 7047 u8 time_stamp_high[0x20]; 7048 7049 u8 time_stamp_low[0x20]; 7050 7051 u8 accumulators_period[0x20]; 7052 7053 u8 np_ecn_marked_roce_packets_high[0x20]; 7054 7055 u8 np_ecn_marked_roce_packets_low[0x20]; 7056 7057 u8 np_cnp_sent_high[0x20]; 7058 7059 u8 np_cnp_sent_low[0x20]; 7060 7061 u8 reserved_at_320[0x560]; 7062 }; 7063 7064 struct mlx5_ifc_query_cong_statistics_in_bits { 7065 u8 opcode[0x10]; 7066 u8 reserved_at_10[0x10]; 7067 7068 u8 reserved_at_20[0x10]; 7069 u8 op_mod[0x10]; 7070 7071 u8 clear[0x1]; 7072 u8 reserved_at_41[0x1f]; 7073 7074 u8 reserved_at_60[0x20]; 7075 }; 7076 7077 struct mlx5_ifc_query_cong_params_out_bits { 7078 u8 status[0x8]; 7079 u8 reserved_at_8[0x18]; 7080 7081 u8 syndrome[0x20]; 7082 7083 u8 reserved_at_40[0x40]; 7084 7085 union mlx5_ifc_cong_control_roce_ecn_auto_bits congestion_parameters; 7086 }; 7087 7088 struct mlx5_ifc_query_cong_params_in_bits { 7089 u8 opcode[0x10]; 7090 u8 reserved_at_10[0x10]; 7091 7092 u8 reserved_at_20[0x10]; 7093 u8 op_mod[0x10]; 7094 7095 u8 reserved_at_40[0x1c]; 7096 u8 cong_protocol[0x4]; 7097 7098 u8 reserved_at_60[0x20]; 7099 }; 7100 7101 struct mlx5_ifc_query_adapter_out_bits { 7102 u8 status[0x8]; 7103 u8 reserved_at_8[0x18]; 7104 7105 u8 syndrome[0x20]; 7106 7107 u8 reserved_at_40[0x40]; 7108 7109 struct mlx5_ifc_query_adapter_param_block_bits query_adapter_struct; 7110 }; 7111 7112 struct mlx5_ifc_query_adapter_in_bits { 7113 u8 opcode[0x10]; 7114 u8 reserved_at_10[0x10]; 7115 7116 u8 reserved_at_20[0x10]; 7117 u8 op_mod[0x10]; 7118 7119 u8 reserved_at_40[0x40]; 7120 }; 7121 7122 struct mlx5_ifc_qp_2rst_out_bits { 7123 u8 status[0x8]; 7124 u8 reserved_at_8[0x18]; 7125 7126 u8 syndrome[0x20]; 7127 7128 u8 reserved_at_40[0x40]; 7129 }; 7130 7131 struct mlx5_ifc_qp_2rst_in_bits { 7132 u8 opcode[0x10]; 7133 u8 uid[0x10]; 7134 7135 u8 reserved_at_20[0x10]; 7136 u8 op_mod[0x10]; 7137 7138 u8 reserved_at_40[0x8]; 7139 u8 qpn[0x18]; 7140 7141 u8 reserved_at_60[0x20]; 7142 }; 7143 7144 struct mlx5_ifc_qp_2err_out_bits { 7145 u8 status[0x8]; 7146 u8 reserved_at_8[0x18]; 7147 7148 u8 syndrome[0x20]; 7149 7150 u8 reserved_at_40[0x40]; 7151 }; 7152 7153 struct mlx5_ifc_qp_2err_in_bits { 7154 u8 opcode[0x10]; 7155 u8 uid[0x10]; 7156 7157 u8 reserved_at_20[0x10]; 7158 u8 op_mod[0x10]; 7159 7160 u8 reserved_at_40[0x8]; 7161 u8 qpn[0x18]; 7162 7163 u8 reserved_at_60[0x20]; 7164 }; 7165 7166 struct mlx5_ifc_page_fault_resume_out_bits { 7167 u8 status[0x8]; 7168 u8 reserved_at_8[0x18]; 7169 7170 u8 syndrome[0x20]; 7171 7172 u8 reserved_at_40[0x40]; 7173 }; 7174 7175 struct mlx5_ifc_page_fault_resume_in_bits { 7176 u8 opcode[0x10]; 7177 u8 reserved_at_10[0x10]; 7178 7179 u8 reserved_at_20[0x10]; 7180 u8 op_mod[0x10]; 7181 7182 u8 error[0x1]; 7183 u8 reserved_at_41[0x4]; 7184 u8 page_fault_type[0x3]; 7185 u8 wq_number[0x18]; 7186 7187 u8 reserved_at_60[0x8]; 7188 u8 token[0x18]; 7189 }; 7190 7191 struct mlx5_ifc_nop_out_bits { 7192 u8 status[0x8]; 7193 u8 reserved_at_8[0x18]; 7194 7195 u8 syndrome[0x20]; 7196 7197 u8 reserved_at_40[0x40]; 7198 }; 7199 7200 struct mlx5_ifc_nop_in_bits { 7201 u8 opcode[0x10]; 7202 u8 reserved_at_10[0x10]; 7203 7204 u8 reserved_at_20[0x10]; 7205 u8 op_mod[0x10]; 7206 7207 u8 reserved_at_40[0x40]; 7208 }; 7209 7210 struct mlx5_ifc_modify_vport_state_out_bits { 7211 u8 status[0x8]; 7212 u8 reserved_at_8[0x18]; 7213 7214 u8 syndrome[0x20]; 7215 7216 u8 reserved_at_40[0x40]; 7217 }; 7218 7219 struct mlx5_ifc_modify_vport_state_in_bits { 7220 u8 opcode[0x10]; 7221 u8 reserved_at_10[0x10]; 7222 7223 u8 reserved_at_20[0x10]; 7224 u8 op_mod[0x10]; 7225 7226 u8 other_vport[0x1]; 7227 u8 reserved_at_41[0xf]; 7228 u8 vport_number[0x10]; 7229 7230 u8 reserved_at_60[0x18]; 7231 u8 admin_state[0x4]; 7232 u8 reserved_at_7c[0x4]; 7233 }; 7234 7235 struct mlx5_ifc_modify_tis_out_bits { 7236 u8 status[0x8]; 7237 u8 reserved_at_8[0x18]; 7238 7239 u8 syndrome[0x20]; 7240 7241 u8 reserved_at_40[0x40]; 7242 }; 7243 7244 struct mlx5_ifc_modify_tis_bitmask_bits { 7245 u8 reserved_at_0[0x20]; 7246 7247 u8 reserved_at_20[0x1d]; 7248 u8 lag_tx_port_affinity[0x1]; 7249 u8 strict_lag_tx_port_affinity[0x1]; 7250 u8 prio[0x1]; 7251 }; 7252 7253 struct mlx5_ifc_modify_tis_in_bits { 7254 u8 opcode[0x10]; 7255 u8 uid[0x10]; 7256 7257 u8 reserved_at_20[0x10]; 7258 u8 op_mod[0x10]; 7259 7260 u8 reserved_at_40[0x8]; 7261 u8 tisn[0x18]; 7262 7263 u8 reserved_at_60[0x20]; 7264 7265 struct mlx5_ifc_modify_tis_bitmask_bits bitmask; 7266 7267 u8 reserved_at_c0[0x40]; 7268 7269 struct mlx5_ifc_tisc_bits ctx; 7270 }; 7271 7272 struct mlx5_ifc_modify_tir_bitmask_bits { 7273 u8 reserved_at_0[0x20]; 7274 7275 u8 reserved_at_20[0x1b]; 7276 u8 self_lb_en[0x1]; 7277 u8 reserved_at_3c[0x1]; 7278 u8 hash[0x1]; 7279 u8 reserved_at_3e[0x1]; 7280 u8 packet_merge[0x1]; 7281 }; 7282 7283 struct mlx5_ifc_modify_tir_out_bits { 7284 u8 status[0x8]; 7285 u8 reserved_at_8[0x18]; 7286 7287 u8 syndrome[0x20]; 7288 7289 u8 reserved_at_40[0x40]; 7290 }; 7291 7292 struct mlx5_ifc_modify_tir_in_bits { 7293 u8 opcode[0x10]; 7294 u8 uid[0x10]; 7295 7296 u8 reserved_at_20[0x10]; 7297 u8 op_mod[0x10]; 7298 7299 u8 reserved_at_40[0x8]; 7300 u8 tirn[0x18]; 7301 7302 u8 reserved_at_60[0x20]; 7303 7304 struct mlx5_ifc_modify_tir_bitmask_bits bitmask; 7305 7306 u8 reserved_at_c0[0x40]; 7307 7308 struct mlx5_ifc_tirc_bits ctx; 7309 }; 7310 7311 struct mlx5_ifc_modify_sq_out_bits { 7312 u8 status[0x8]; 7313 u8 reserved_at_8[0x18]; 7314 7315 u8 syndrome[0x20]; 7316 7317 u8 reserved_at_40[0x40]; 7318 }; 7319 7320 struct mlx5_ifc_modify_sq_in_bits { 7321 u8 opcode[0x10]; 7322 u8 uid[0x10]; 7323 7324 u8 reserved_at_20[0x10]; 7325 u8 op_mod[0x10]; 7326 7327 u8 sq_state[0x4]; 7328 u8 reserved_at_44[0x4]; 7329 u8 sqn[0x18]; 7330 7331 u8 reserved_at_60[0x20]; 7332 7333 u8 modify_bitmask[0x40]; 7334 7335 u8 reserved_at_c0[0x40]; 7336 7337 struct mlx5_ifc_sqc_bits ctx; 7338 }; 7339 7340 struct mlx5_ifc_modify_scheduling_element_out_bits { 7341 u8 status[0x8]; 7342 u8 reserved_at_8[0x18]; 7343 7344 u8 syndrome[0x20]; 7345 7346 u8 reserved_at_40[0x1c0]; 7347 }; 7348 7349 enum { 7350 MODIFY_SCHEDULING_ELEMENT_IN_MODIFY_BITMASK_BW_SHARE = 0x1, 7351 MODIFY_SCHEDULING_ELEMENT_IN_MODIFY_BITMASK_MAX_AVERAGE_BW = 0x2, 7352 }; 7353 7354 struct mlx5_ifc_modify_scheduling_element_in_bits { 7355 u8 opcode[0x10]; 7356 u8 reserved_at_10[0x10]; 7357 7358 u8 reserved_at_20[0x10]; 7359 u8 op_mod[0x10]; 7360 7361 u8 scheduling_hierarchy[0x8]; 7362 u8 reserved_at_48[0x18]; 7363 7364 u8 scheduling_element_id[0x20]; 7365 7366 u8 reserved_at_80[0x20]; 7367 7368 u8 modify_bitmask[0x20]; 7369 7370 u8 reserved_at_c0[0x40]; 7371 7372 struct mlx5_ifc_scheduling_context_bits scheduling_context; 7373 7374 u8 reserved_at_300[0x100]; 7375 }; 7376 7377 struct mlx5_ifc_modify_rqt_out_bits { 7378 u8 status[0x8]; 7379 u8 reserved_at_8[0x18]; 7380 7381 u8 syndrome[0x20]; 7382 7383 u8 reserved_at_40[0x40]; 7384 }; 7385 7386 struct mlx5_ifc_rqt_bitmask_bits { 7387 u8 reserved_at_0[0x20]; 7388 7389 u8 reserved_at_20[0x1f]; 7390 u8 rqn_list[0x1]; 7391 }; 7392 7393 struct mlx5_ifc_modify_rqt_in_bits { 7394 u8 opcode[0x10]; 7395 u8 uid[0x10]; 7396 7397 u8 reserved_at_20[0x10]; 7398 u8 op_mod[0x10]; 7399 7400 u8 reserved_at_40[0x8]; 7401 u8 rqtn[0x18]; 7402 7403 u8 reserved_at_60[0x20]; 7404 7405 struct mlx5_ifc_rqt_bitmask_bits bitmask; 7406 7407 u8 reserved_at_c0[0x40]; 7408 7409 struct mlx5_ifc_rqtc_bits ctx; 7410 }; 7411 7412 struct mlx5_ifc_modify_rq_out_bits { 7413 u8 status[0x8]; 7414 u8 reserved_at_8[0x18]; 7415 7416 u8 syndrome[0x20]; 7417 7418 u8 reserved_at_40[0x40]; 7419 }; 7420 7421 enum { 7422 MLX5_MODIFY_RQ_IN_MODIFY_BITMASK_VSD = 1ULL << 1, 7423 MLX5_MODIFY_RQ_IN_MODIFY_BITMASK_SCATTER_FCS = 1ULL << 2, 7424 MLX5_MODIFY_RQ_IN_MODIFY_BITMASK_RQ_COUNTER_SET_ID = 1ULL << 3, 7425 }; 7426 7427 struct mlx5_ifc_modify_rq_in_bits { 7428 u8 opcode[0x10]; 7429 u8 uid[0x10]; 7430 7431 u8 reserved_at_20[0x10]; 7432 u8 op_mod[0x10]; 7433 7434 u8 rq_state[0x4]; 7435 u8 reserved_at_44[0x4]; 7436 u8 rqn[0x18]; 7437 7438 u8 reserved_at_60[0x20]; 7439 7440 u8 modify_bitmask[0x40]; 7441 7442 u8 reserved_at_c0[0x40]; 7443 7444 struct mlx5_ifc_rqc_bits ctx; 7445 }; 7446 7447 struct mlx5_ifc_modify_rmp_out_bits { 7448 u8 status[0x8]; 7449 u8 reserved_at_8[0x18]; 7450 7451 u8 syndrome[0x20]; 7452 7453 u8 reserved_at_40[0x40]; 7454 }; 7455 7456 struct mlx5_ifc_rmp_bitmask_bits { 7457 u8 reserved_at_0[0x20]; 7458 7459 u8 reserved_at_20[0x1f]; 7460 u8 lwm[0x1]; 7461 }; 7462 7463 struct mlx5_ifc_modify_rmp_in_bits { 7464 u8 opcode[0x10]; 7465 u8 uid[0x10]; 7466 7467 u8 reserved_at_20[0x10]; 7468 u8 op_mod[0x10]; 7469 7470 u8 rmp_state[0x4]; 7471 u8 reserved_at_44[0x4]; 7472 u8 rmpn[0x18]; 7473 7474 u8 reserved_at_60[0x20]; 7475 7476 struct mlx5_ifc_rmp_bitmask_bits bitmask; 7477 7478 u8 reserved_at_c0[0x40]; 7479 7480 struct mlx5_ifc_rmpc_bits ctx; 7481 }; 7482 7483 struct mlx5_ifc_modify_nic_vport_context_out_bits { 7484 u8 status[0x8]; 7485 u8 reserved_at_8[0x18]; 7486 7487 u8 syndrome[0x20]; 7488 7489 u8 reserved_at_40[0x40]; 7490 }; 7491 7492 struct mlx5_ifc_modify_nic_vport_field_select_bits { 7493 u8 reserved_at_0[0x12]; 7494 u8 affiliation[0x1]; 7495 u8 reserved_at_13[0x1]; 7496 u8 disable_uc_local_lb[0x1]; 7497 u8 disable_mc_local_lb[0x1]; 7498 u8 node_guid[0x1]; 7499 u8 port_guid[0x1]; 7500 u8 min_inline[0x1]; 7501 u8 mtu[0x1]; 7502 u8 change_event[0x1]; 7503 u8 promisc[0x1]; 7504 u8 permanent_address[0x1]; 7505 u8 addresses_list[0x1]; 7506 u8 roce_en[0x1]; 7507 u8 reserved_at_1f[0x1]; 7508 }; 7509 7510 struct mlx5_ifc_modify_nic_vport_context_in_bits { 7511 u8 opcode[0x10]; 7512 u8 reserved_at_10[0x10]; 7513 7514 u8 reserved_at_20[0x10]; 7515 u8 op_mod[0x10]; 7516 7517 u8 other_vport[0x1]; 7518 u8 reserved_at_41[0xf]; 7519 u8 vport_number[0x10]; 7520 7521 struct mlx5_ifc_modify_nic_vport_field_select_bits field_select; 7522 7523 u8 reserved_at_80[0x780]; 7524 7525 struct mlx5_ifc_nic_vport_context_bits nic_vport_context; 7526 }; 7527 7528 struct mlx5_ifc_modify_hca_vport_context_out_bits { 7529 u8 status[0x8]; 7530 u8 reserved_at_8[0x18]; 7531 7532 u8 syndrome[0x20]; 7533 7534 u8 reserved_at_40[0x40]; 7535 }; 7536 7537 struct mlx5_ifc_modify_hca_vport_context_in_bits { 7538 u8 opcode[0x10]; 7539 u8 reserved_at_10[0x10]; 7540 7541 u8 reserved_at_20[0x10]; 7542 u8 op_mod[0x10]; 7543 7544 u8 other_vport[0x1]; 7545 u8 reserved_at_41[0xb]; 7546 u8 port_num[0x4]; 7547 u8 vport_number[0x10]; 7548 7549 u8 reserved_at_60[0x20]; 7550 7551 struct mlx5_ifc_hca_vport_context_bits hca_vport_context; 7552 }; 7553 7554 struct mlx5_ifc_modify_cq_out_bits { 7555 u8 status[0x8]; 7556 u8 reserved_at_8[0x18]; 7557 7558 u8 syndrome[0x20]; 7559 7560 u8 reserved_at_40[0x40]; 7561 }; 7562 7563 enum { 7564 MLX5_MODIFY_CQ_IN_OP_MOD_MODIFY_CQ = 0x0, 7565 MLX5_MODIFY_CQ_IN_OP_MOD_RESIZE_CQ = 0x1, 7566 }; 7567 7568 struct mlx5_ifc_modify_cq_in_bits { 7569 u8 opcode[0x10]; 7570 u8 uid[0x10]; 7571 7572 u8 reserved_at_20[0x10]; 7573 u8 op_mod[0x10]; 7574 7575 u8 reserved_at_40[0x8]; 7576 u8 cqn[0x18]; 7577 7578 union mlx5_ifc_modify_field_select_resize_field_select_auto_bits modify_field_select_resize_field_select; 7579 7580 struct mlx5_ifc_cqc_bits cq_context; 7581 7582 u8 reserved_at_280[0x60]; 7583 7584 u8 cq_umem_valid[0x1]; 7585 u8 reserved_at_2e1[0x1f]; 7586 7587 u8 reserved_at_300[0x580]; 7588 7589 u8 pas[][0x40]; 7590 }; 7591 7592 struct mlx5_ifc_modify_cong_status_out_bits { 7593 u8 status[0x8]; 7594 u8 reserved_at_8[0x18]; 7595 7596 u8 syndrome[0x20]; 7597 7598 u8 reserved_at_40[0x40]; 7599 }; 7600 7601 struct mlx5_ifc_modify_cong_status_in_bits { 7602 u8 opcode[0x10]; 7603 u8 reserved_at_10[0x10]; 7604 7605 u8 reserved_at_20[0x10]; 7606 u8 op_mod[0x10]; 7607 7608 u8 reserved_at_40[0x18]; 7609 u8 priority[0x4]; 7610 u8 cong_protocol[0x4]; 7611 7612 u8 enable[0x1]; 7613 u8 tag_enable[0x1]; 7614 u8 reserved_at_62[0x1e]; 7615 }; 7616 7617 struct mlx5_ifc_modify_cong_params_out_bits { 7618 u8 status[0x8]; 7619 u8 reserved_at_8[0x18]; 7620 7621 u8 syndrome[0x20]; 7622 7623 u8 reserved_at_40[0x40]; 7624 }; 7625 7626 struct mlx5_ifc_modify_cong_params_in_bits { 7627 u8 opcode[0x10]; 7628 u8 reserved_at_10[0x10]; 7629 7630 u8 reserved_at_20[0x10]; 7631 u8 op_mod[0x10]; 7632 7633 u8 reserved_at_40[0x1c]; 7634 u8 cong_protocol[0x4]; 7635 7636 union mlx5_ifc_field_select_802_1_r_roce_auto_bits field_select; 7637 7638 u8 reserved_at_80[0x80]; 7639 7640 union mlx5_ifc_cong_control_roce_ecn_auto_bits congestion_parameters; 7641 }; 7642 7643 struct mlx5_ifc_manage_pages_out_bits { 7644 u8 status[0x8]; 7645 u8 reserved_at_8[0x18]; 7646 7647 u8 syndrome[0x20]; 7648 7649 u8 output_num_entries[0x20]; 7650 7651 u8 reserved_at_60[0x20]; 7652 7653 u8 pas[][0x40]; 7654 }; 7655 7656 enum { 7657 MLX5_MANAGE_PAGES_IN_OP_MOD_ALLOCATION_FAIL = 0x0, 7658 MLX5_MANAGE_PAGES_IN_OP_MOD_ALLOCATION_SUCCESS = 0x1, 7659 MLX5_MANAGE_PAGES_IN_OP_MOD_HCA_RETURN_PAGES = 0x2, 7660 }; 7661 7662 struct mlx5_ifc_manage_pages_in_bits { 7663 u8 opcode[0x10]; 7664 u8 reserved_at_10[0x10]; 7665 7666 u8 reserved_at_20[0x10]; 7667 u8 op_mod[0x10]; 7668 7669 u8 embedded_cpu_function[0x1]; 7670 u8 reserved_at_41[0xf]; 7671 u8 function_id[0x10]; 7672 7673 u8 input_num_entries[0x20]; 7674 7675 u8 pas[][0x40]; 7676 }; 7677 7678 struct mlx5_ifc_mad_ifc_out_bits { 7679 u8 status[0x8]; 7680 u8 reserved_at_8[0x18]; 7681 7682 u8 syndrome[0x20]; 7683 7684 u8 reserved_at_40[0x40]; 7685 7686 u8 response_mad_packet[256][0x8]; 7687 }; 7688 7689 struct mlx5_ifc_mad_ifc_in_bits { 7690 u8 opcode[0x10]; 7691 u8 reserved_at_10[0x10]; 7692 7693 u8 reserved_at_20[0x10]; 7694 u8 op_mod[0x10]; 7695 7696 u8 remote_lid[0x10]; 7697 u8 reserved_at_50[0x8]; 7698 u8 port[0x8]; 7699 7700 u8 reserved_at_60[0x20]; 7701 7702 u8 mad[256][0x8]; 7703 }; 7704 7705 struct mlx5_ifc_init_hca_out_bits { 7706 u8 status[0x8]; 7707 u8 reserved_at_8[0x18]; 7708 7709 u8 syndrome[0x20]; 7710 7711 u8 reserved_at_40[0x40]; 7712 }; 7713 7714 struct mlx5_ifc_init_hca_in_bits { 7715 u8 opcode[0x10]; 7716 u8 reserved_at_10[0x10]; 7717 7718 u8 reserved_at_20[0x10]; 7719 u8 op_mod[0x10]; 7720 7721 u8 reserved_at_40[0x20]; 7722 7723 u8 reserved_at_60[0x2]; 7724 u8 sw_vhca_id[0xe]; 7725 u8 reserved_at_70[0x10]; 7726 7727 u8 sw_owner_id[4][0x20]; 7728 }; 7729 7730 struct mlx5_ifc_init2rtr_qp_out_bits { 7731 u8 status[0x8]; 7732 u8 reserved_at_8[0x18]; 7733 7734 u8 syndrome[0x20]; 7735 7736 u8 reserved_at_40[0x20]; 7737 u8 ece[0x20]; 7738 }; 7739 7740 struct mlx5_ifc_init2rtr_qp_in_bits { 7741 u8 opcode[0x10]; 7742 u8 uid[0x10]; 7743 7744 u8 reserved_at_20[0x10]; 7745 u8 op_mod[0x10]; 7746 7747 u8 reserved_at_40[0x8]; 7748 u8 qpn[0x18]; 7749 7750 u8 reserved_at_60[0x20]; 7751 7752 u8 opt_param_mask[0x20]; 7753 7754 u8 ece[0x20]; 7755 7756 struct mlx5_ifc_qpc_bits qpc; 7757 7758 u8 reserved_at_800[0x80]; 7759 }; 7760 7761 struct mlx5_ifc_init2init_qp_out_bits { 7762 u8 status[0x8]; 7763 u8 reserved_at_8[0x18]; 7764 7765 u8 syndrome[0x20]; 7766 7767 u8 reserved_at_40[0x20]; 7768 u8 ece[0x20]; 7769 }; 7770 7771 struct mlx5_ifc_init2init_qp_in_bits { 7772 u8 opcode[0x10]; 7773 u8 uid[0x10]; 7774 7775 u8 reserved_at_20[0x10]; 7776 u8 op_mod[0x10]; 7777 7778 u8 reserved_at_40[0x8]; 7779 u8 qpn[0x18]; 7780 7781 u8 reserved_at_60[0x20]; 7782 7783 u8 opt_param_mask[0x20]; 7784 7785 u8 ece[0x20]; 7786 7787 struct mlx5_ifc_qpc_bits qpc; 7788 7789 u8 reserved_at_800[0x80]; 7790 }; 7791 7792 struct mlx5_ifc_get_dropped_packet_log_out_bits { 7793 u8 status[0x8]; 7794 u8 reserved_at_8[0x18]; 7795 7796 u8 syndrome[0x20]; 7797 7798 u8 reserved_at_40[0x40]; 7799 7800 u8 packet_headers_log[128][0x8]; 7801 7802 u8 packet_syndrome[64][0x8]; 7803 }; 7804 7805 struct mlx5_ifc_get_dropped_packet_log_in_bits { 7806 u8 opcode[0x10]; 7807 u8 reserved_at_10[0x10]; 7808 7809 u8 reserved_at_20[0x10]; 7810 u8 op_mod[0x10]; 7811 7812 u8 reserved_at_40[0x40]; 7813 }; 7814 7815 struct mlx5_ifc_gen_eqe_in_bits { 7816 u8 opcode[0x10]; 7817 u8 reserved_at_10[0x10]; 7818 7819 u8 reserved_at_20[0x10]; 7820 u8 op_mod[0x10]; 7821 7822 u8 reserved_at_40[0x18]; 7823 u8 eq_number[0x8]; 7824 7825 u8 reserved_at_60[0x20]; 7826 7827 u8 eqe[64][0x8]; 7828 }; 7829 7830 struct mlx5_ifc_gen_eq_out_bits { 7831 u8 status[0x8]; 7832 u8 reserved_at_8[0x18]; 7833 7834 u8 syndrome[0x20]; 7835 7836 u8 reserved_at_40[0x40]; 7837 }; 7838 7839 struct mlx5_ifc_enable_hca_out_bits { 7840 u8 status[0x8]; 7841 u8 reserved_at_8[0x18]; 7842 7843 u8 syndrome[0x20]; 7844 7845 u8 reserved_at_40[0x20]; 7846 }; 7847 7848 struct mlx5_ifc_enable_hca_in_bits { 7849 u8 opcode[0x10]; 7850 u8 reserved_at_10[0x10]; 7851 7852 u8 reserved_at_20[0x10]; 7853 u8 op_mod[0x10]; 7854 7855 u8 embedded_cpu_function[0x1]; 7856 u8 reserved_at_41[0xf]; 7857 u8 function_id[0x10]; 7858 7859 u8 reserved_at_60[0x20]; 7860 }; 7861 7862 struct mlx5_ifc_drain_dct_out_bits { 7863 u8 status[0x8]; 7864 u8 reserved_at_8[0x18]; 7865 7866 u8 syndrome[0x20]; 7867 7868 u8 reserved_at_40[0x40]; 7869 }; 7870 7871 struct mlx5_ifc_drain_dct_in_bits { 7872 u8 opcode[0x10]; 7873 u8 uid[0x10]; 7874 7875 u8 reserved_at_20[0x10]; 7876 u8 op_mod[0x10]; 7877 7878 u8 reserved_at_40[0x8]; 7879 u8 dctn[0x18]; 7880 7881 u8 reserved_at_60[0x20]; 7882 }; 7883 7884 struct mlx5_ifc_disable_hca_out_bits { 7885 u8 status[0x8]; 7886 u8 reserved_at_8[0x18]; 7887 7888 u8 syndrome[0x20]; 7889 7890 u8 reserved_at_40[0x20]; 7891 }; 7892 7893 struct mlx5_ifc_disable_hca_in_bits { 7894 u8 opcode[0x10]; 7895 u8 reserved_at_10[0x10]; 7896 7897 u8 reserved_at_20[0x10]; 7898 u8 op_mod[0x10]; 7899 7900 u8 embedded_cpu_function[0x1]; 7901 u8 reserved_at_41[0xf]; 7902 u8 function_id[0x10]; 7903 7904 u8 reserved_at_60[0x20]; 7905 }; 7906 7907 struct mlx5_ifc_detach_from_mcg_out_bits { 7908 u8 status[0x8]; 7909 u8 reserved_at_8[0x18]; 7910 7911 u8 syndrome[0x20]; 7912 7913 u8 reserved_at_40[0x40]; 7914 }; 7915 7916 struct mlx5_ifc_detach_from_mcg_in_bits { 7917 u8 opcode[0x10]; 7918 u8 uid[0x10]; 7919 7920 u8 reserved_at_20[0x10]; 7921 u8 op_mod[0x10]; 7922 7923 u8 reserved_at_40[0x8]; 7924 u8 qpn[0x18]; 7925 7926 u8 reserved_at_60[0x20]; 7927 7928 u8 multicast_gid[16][0x8]; 7929 }; 7930 7931 struct mlx5_ifc_destroy_xrq_out_bits { 7932 u8 status[0x8]; 7933 u8 reserved_at_8[0x18]; 7934 7935 u8 syndrome[0x20]; 7936 7937 u8 reserved_at_40[0x40]; 7938 }; 7939 7940 struct mlx5_ifc_destroy_xrq_in_bits { 7941 u8 opcode[0x10]; 7942 u8 uid[0x10]; 7943 7944 u8 reserved_at_20[0x10]; 7945 u8 op_mod[0x10]; 7946 7947 u8 reserved_at_40[0x8]; 7948 u8 xrqn[0x18]; 7949 7950 u8 reserved_at_60[0x20]; 7951 }; 7952 7953 struct mlx5_ifc_destroy_xrc_srq_out_bits { 7954 u8 status[0x8]; 7955 u8 reserved_at_8[0x18]; 7956 7957 u8 syndrome[0x20]; 7958 7959 u8 reserved_at_40[0x40]; 7960 }; 7961 7962 struct mlx5_ifc_destroy_xrc_srq_in_bits { 7963 u8 opcode[0x10]; 7964 u8 uid[0x10]; 7965 7966 u8 reserved_at_20[0x10]; 7967 u8 op_mod[0x10]; 7968 7969 u8 reserved_at_40[0x8]; 7970 u8 xrc_srqn[0x18]; 7971 7972 u8 reserved_at_60[0x20]; 7973 }; 7974 7975 struct mlx5_ifc_destroy_tis_out_bits { 7976 u8 status[0x8]; 7977 u8 reserved_at_8[0x18]; 7978 7979 u8 syndrome[0x20]; 7980 7981 u8 reserved_at_40[0x40]; 7982 }; 7983 7984 struct mlx5_ifc_destroy_tis_in_bits { 7985 u8 opcode[0x10]; 7986 u8 uid[0x10]; 7987 7988 u8 reserved_at_20[0x10]; 7989 u8 op_mod[0x10]; 7990 7991 u8 reserved_at_40[0x8]; 7992 u8 tisn[0x18]; 7993 7994 u8 reserved_at_60[0x20]; 7995 }; 7996 7997 struct mlx5_ifc_destroy_tir_out_bits { 7998 u8 status[0x8]; 7999 u8 reserved_at_8[0x18]; 8000 8001 u8 syndrome[0x20]; 8002 8003 u8 reserved_at_40[0x40]; 8004 }; 8005 8006 struct mlx5_ifc_destroy_tir_in_bits { 8007 u8 opcode[0x10]; 8008 u8 uid[0x10]; 8009 8010 u8 reserved_at_20[0x10]; 8011 u8 op_mod[0x10]; 8012 8013 u8 reserved_at_40[0x8]; 8014 u8 tirn[0x18]; 8015 8016 u8 reserved_at_60[0x20]; 8017 }; 8018 8019 struct mlx5_ifc_destroy_srq_out_bits { 8020 u8 status[0x8]; 8021 u8 reserved_at_8[0x18]; 8022 8023 u8 syndrome[0x20]; 8024 8025 u8 reserved_at_40[0x40]; 8026 }; 8027 8028 struct mlx5_ifc_destroy_srq_in_bits { 8029 u8 opcode[0x10]; 8030 u8 uid[0x10]; 8031 8032 u8 reserved_at_20[0x10]; 8033 u8 op_mod[0x10]; 8034 8035 u8 reserved_at_40[0x8]; 8036 u8 srqn[0x18]; 8037 8038 u8 reserved_at_60[0x20]; 8039 }; 8040 8041 struct mlx5_ifc_destroy_sq_out_bits { 8042 u8 status[0x8]; 8043 u8 reserved_at_8[0x18]; 8044 8045 u8 syndrome[0x20]; 8046 8047 u8 reserved_at_40[0x40]; 8048 }; 8049 8050 struct mlx5_ifc_destroy_sq_in_bits { 8051 u8 opcode[0x10]; 8052 u8 uid[0x10]; 8053 8054 u8 reserved_at_20[0x10]; 8055 u8 op_mod[0x10]; 8056 8057 u8 reserved_at_40[0x8]; 8058 u8 sqn[0x18]; 8059 8060 u8 reserved_at_60[0x20]; 8061 }; 8062 8063 struct mlx5_ifc_destroy_scheduling_element_out_bits { 8064 u8 status[0x8]; 8065 u8 reserved_at_8[0x18]; 8066 8067 u8 syndrome[0x20]; 8068 8069 u8 reserved_at_40[0x1c0]; 8070 }; 8071 8072 struct mlx5_ifc_destroy_scheduling_element_in_bits { 8073 u8 opcode[0x10]; 8074 u8 reserved_at_10[0x10]; 8075 8076 u8 reserved_at_20[0x10]; 8077 u8 op_mod[0x10]; 8078 8079 u8 scheduling_hierarchy[0x8]; 8080 u8 reserved_at_48[0x18]; 8081 8082 u8 scheduling_element_id[0x20]; 8083 8084 u8 reserved_at_80[0x180]; 8085 }; 8086 8087 struct mlx5_ifc_destroy_rqt_out_bits { 8088 u8 status[0x8]; 8089 u8 reserved_at_8[0x18]; 8090 8091 u8 syndrome[0x20]; 8092 8093 u8 reserved_at_40[0x40]; 8094 }; 8095 8096 struct mlx5_ifc_destroy_rqt_in_bits { 8097 u8 opcode[0x10]; 8098 u8 uid[0x10]; 8099 8100 u8 reserved_at_20[0x10]; 8101 u8 op_mod[0x10]; 8102 8103 u8 reserved_at_40[0x8]; 8104 u8 rqtn[0x18]; 8105 8106 u8 reserved_at_60[0x20]; 8107 }; 8108 8109 struct mlx5_ifc_destroy_rq_out_bits { 8110 u8 status[0x8]; 8111 u8 reserved_at_8[0x18]; 8112 8113 u8 syndrome[0x20]; 8114 8115 u8 reserved_at_40[0x40]; 8116 }; 8117 8118 struct mlx5_ifc_destroy_rq_in_bits { 8119 u8 opcode[0x10]; 8120 u8 uid[0x10]; 8121 8122 u8 reserved_at_20[0x10]; 8123 u8 op_mod[0x10]; 8124 8125 u8 reserved_at_40[0x8]; 8126 u8 rqn[0x18]; 8127 8128 u8 reserved_at_60[0x20]; 8129 }; 8130 8131 struct mlx5_ifc_set_delay_drop_params_in_bits { 8132 u8 opcode[0x10]; 8133 u8 reserved_at_10[0x10]; 8134 8135 u8 reserved_at_20[0x10]; 8136 u8 op_mod[0x10]; 8137 8138 u8 reserved_at_40[0x20]; 8139 8140 u8 reserved_at_60[0x10]; 8141 u8 delay_drop_timeout[0x10]; 8142 }; 8143 8144 struct mlx5_ifc_set_delay_drop_params_out_bits { 8145 u8 status[0x8]; 8146 u8 reserved_at_8[0x18]; 8147 8148 u8 syndrome[0x20]; 8149 8150 u8 reserved_at_40[0x40]; 8151 }; 8152 8153 struct mlx5_ifc_destroy_rmp_out_bits { 8154 u8 status[0x8]; 8155 u8 reserved_at_8[0x18]; 8156 8157 u8 syndrome[0x20]; 8158 8159 u8 reserved_at_40[0x40]; 8160 }; 8161 8162 struct mlx5_ifc_destroy_rmp_in_bits { 8163 u8 opcode[0x10]; 8164 u8 uid[0x10]; 8165 8166 u8 reserved_at_20[0x10]; 8167 u8 op_mod[0x10]; 8168 8169 u8 reserved_at_40[0x8]; 8170 u8 rmpn[0x18]; 8171 8172 u8 reserved_at_60[0x20]; 8173 }; 8174 8175 struct mlx5_ifc_destroy_qp_out_bits { 8176 u8 status[0x8]; 8177 u8 reserved_at_8[0x18]; 8178 8179 u8 syndrome[0x20]; 8180 8181 u8 reserved_at_40[0x40]; 8182 }; 8183 8184 struct mlx5_ifc_destroy_qp_in_bits { 8185 u8 opcode[0x10]; 8186 u8 uid[0x10]; 8187 8188 u8 reserved_at_20[0x10]; 8189 u8 op_mod[0x10]; 8190 8191 u8 reserved_at_40[0x8]; 8192 u8 qpn[0x18]; 8193 8194 u8 reserved_at_60[0x20]; 8195 }; 8196 8197 struct mlx5_ifc_destroy_psv_out_bits { 8198 u8 status[0x8]; 8199 u8 reserved_at_8[0x18]; 8200 8201 u8 syndrome[0x20]; 8202 8203 u8 reserved_at_40[0x40]; 8204 }; 8205 8206 struct mlx5_ifc_destroy_psv_in_bits { 8207 u8 opcode[0x10]; 8208 u8 reserved_at_10[0x10]; 8209 8210 u8 reserved_at_20[0x10]; 8211 u8 op_mod[0x10]; 8212 8213 u8 reserved_at_40[0x8]; 8214 u8 psvn[0x18]; 8215 8216 u8 reserved_at_60[0x20]; 8217 }; 8218 8219 struct mlx5_ifc_destroy_mkey_out_bits { 8220 u8 status[0x8]; 8221 u8 reserved_at_8[0x18]; 8222 8223 u8 syndrome[0x20]; 8224 8225 u8 reserved_at_40[0x40]; 8226 }; 8227 8228 struct mlx5_ifc_destroy_mkey_in_bits { 8229 u8 opcode[0x10]; 8230 u8 uid[0x10]; 8231 8232 u8 reserved_at_20[0x10]; 8233 u8 op_mod[0x10]; 8234 8235 u8 reserved_at_40[0x8]; 8236 u8 mkey_index[0x18]; 8237 8238 u8 reserved_at_60[0x20]; 8239 }; 8240 8241 struct mlx5_ifc_destroy_flow_table_out_bits { 8242 u8 status[0x8]; 8243 u8 reserved_at_8[0x18]; 8244 8245 u8 syndrome[0x20]; 8246 8247 u8 reserved_at_40[0x40]; 8248 }; 8249 8250 struct mlx5_ifc_destroy_flow_table_in_bits { 8251 u8 opcode[0x10]; 8252 u8 reserved_at_10[0x10]; 8253 8254 u8 reserved_at_20[0x10]; 8255 u8 op_mod[0x10]; 8256 8257 u8 other_vport[0x1]; 8258 u8 reserved_at_41[0xf]; 8259 u8 vport_number[0x10]; 8260 8261 u8 reserved_at_60[0x20]; 8262 8263 u8 table_type[0x8]; 8264 u8 reserved_at_88[0x18]; 8265 8266 u8 reserved_at_a0[0x8]; 8267 u8 table_id[0x18]; 8268 8269 u8 reserved_at_c0[0x140]; 8270 }; 8271 8272 struct mlx5_ifc_destroy_flow_group_out_bits { 8273 u8 status[0x8]; 8274 u8 reserved_at_8[0x18]; 8275 8276 u8 syndrome[0x20]; 8277 8278 u8 reserved_at_40[0x40]; 8279 }; 8280 8281 struct mlx5_ifc_destroy_flow_group_in_bits { 8282 u8 opcode[0x10]; 8283 u8 reserved_at_10[0x10]; 8284 8285 u8 reserved_at_20[0x10]; 8286 u8 op_mod[0x10]; 8287 8288 u8 other_vport[0x1]; 8289 u8 reserved_at_41[0xf]; 8290 u8 vport_number[0x10]; 8291 8292 u8 reserved_at_60[0x20]; 8293 8294 u8 table_type[0x8]; 8295 u8 reserved_at_88[0x18]; 8296 8297 u8 reserved_at_a0[0x8]; 8298 u8 table_id[0x18]; 8299 8300 u8 group_id[0x20]; 8301 8302 u8 reserved_at_e0[0x120]; 8303 }; 8304 8305 struct mlx5_ifc_destroy_eq_out_bits { 8306 u8 status[0x8]; 8307 u8 reserved_at_8[0x18]; 8308 8309 u8 syndrome[0x20]; 8310 8311 u8 reserved_at_40[0x40]; 8312 }; 8313 8314 struct mlx5_ifc_destroy_eq_in_bits { 8315 u8 opcode[0x10]; 8316 u8 reserved_at_10[0x10]; 8317 8318 u8 reserved_at_20[0x10]; 8319 u8 op_mod[0x10]; 8320 8321 u8 reserved_at_40[0x18]; 8322 u8 eq_number[0x8]; 8323 8324 u8 reserved_at_60[0x20]; 8325 }; 8326 8327 struct mlx5_ifc_destroy_dct_out_bits { 8328 u8 status[0x8]; 8329 u8 reserved_at_8[0x18]; 8330 8331 u8 syndrome[0x20]; 8332 8333 u8 reserved_at_40[0x40]; 8334 }; 8335 8336 struct mlx5_ifc_destroy_dct_in_bits { 8337 u8 opcode[0x10]; 8338 u8 uid[0x10]; 8339 8340 u8 reserved_at_20[0x10]; 8341 u8 op_mod[0x10]; 8342 8343 u8 reserved_at_40[0x8]; 8344 u8 dctn[0x18]; 8345 8346 u8 reserved_at_60[0x20]; 8347 }; 8348 8349 struct mlx5_ifc_destroy_cq_out_bits { 8350 u8 status[0x8]; 8351 u8 reserved_at_8[0x18]; 8352 8353 u8 syndrome[0x20]; 8354 8355 u8 reserved_at_40[0x40]; 8356 }; 8357 8358 struct mlx5_ifc_destroy_cq_in_bits { 8359 u8 opcode[0x10]; 8360 u8 uid[0x10]; 8361 8362 u8 reserved_at_20[0x10]; 8363 u8 op_mod[0x10]; 8364 8365 u8 reserved_at_40[0x8]; 8366 u8 cqn[0x18]; 8367 8368 u8 reserved_at_60[0x20]; 8369 }; 8370 8371 struct mlx5_ifc_delete_vxlan_udp_dport_out_bits { 8372 u8 status[0x8]; 8373 u8 reserved_at_8[0x18]; 8374 8375 u8 syndrome[0x20]; 8376 8377 u8 reserved_at_40[0x40]; 8378 }; 8379 8380 struct mlx5_ifc_delete_vxlan_udp_dport_in_bits { 8381 u8 opcode[0x10]; 8382 u8 reserved_at_10[0x10]; 8383 8384 u8 reserved_at_20[0x10]; 8385 u8 op_mod[0x10]; 8386 8387 u8 reserved_at_40[0x20]; 8388 8389 u8 reserved_at_60[0x10]; 8390 u8 vxlan_udp_port[0x10]; 8391 }; 8392 8393 struct mlx5_ifc_delete_l2_table_entry_out_bits { 8394 u8 status[0x8]; 8395 u8 reserved_at_8[0x18]; 8396 8397 u8 syndrome[0x20]; 8398 8399 u8 reserved_at_40[0x40]; 8400 }; 8401 8402 struct mlx5_ifc_delete_l2_table_entry_in_bits { 8403 u8 opcode[0x10]; 8404 u8 reserved_at_10[0x10]; 8405 8406 u8 reserved_at_20[0x10]; 8407 u8 op_mod[0x10]; 8408 8409 u8 reserved_at_40[0x60]; 8410 8411 u8 reserved_at_a0[0x8]; 8412 u8 table_index[0x18]; 8413 8414 u8 reserved_at_c0[0x140]; 8415 }; 8416 8417 struct mlx5_ifc_delete_fte_out_bits { 8418 u8 status[0x8]; 8419 u8 reserved_at_8[0x18]; 8420 8421 u8 syndrome[0x20]; 8422 8423 u8 reserved_at_40[0x40]; 8424 }; 8425 8426 struct mlx5_ifc_delete_fte_in_bits { 8427 u8 opcode[0x10]; 8428 u8 reserved_at_10[0x10]; 8429 8430 u8 reserved_at_20[0x10]; 8431 u8 op_mod[0x10]; 8432 8433 u8 other_vport[0x1]; 8434 u8 reserved_at_41[0xf]; 8435 u8 vport_number[0x10]; 8436 8437 u8 reserved_at_60[0x20]; 8438 8439 u8 table_type[0x8]; 8440 u8 reserved_at_88[0x18]; 8441 8442 u8 reserved_at_a0[0x8]; 8443 u8 table_id[0x18]; 8444 8445 u8 reserved_at_c0[0x40]; 8446 8447 u8 flow_index[0x20]; 8448 8449 u8 reserved_at_120[0xe0]; 8450 }; 8451 8452 struct mlx5_ifc_dealloc_xrcd_out_bits { 8453 u8 status[0x8]; 8454 u8 reserved_at_8[0x18]; 8455 8456 u8 syndrome[0x20]; 8457 8458 u8 reserved_at_40[0x40]; 8459 }; 8460 8461 struct mlx5_ifc_dealloc_xrcd_in_bits { 8462 u8 opcode[0x10]; 8463 u8 uid[0x10]; 8464 8465 u8 reserved_at_20[0x10]; 8466 u8 op_mod[0x10]; 8467 8468 u8 reserved_at_40[0x8]; 8469 u8 xrcd[0x18]; 8470 8471 u8 reserved_at_60[0x20]; 8472 }; 8473 8474 struct mlx5_ifc_dealloc_uar_out_bits { 8475 u8 status[0x8]; 8476 u8 reserved_at_8[0x18]; 8477 8478 u8 syndrome[0x20]; 8479 8480 u8 reserved_at_40[0x40]; 8481 }; 8482 8483 struct mlx5_ifc_dealloc_uar_in_bits { 8484 u8 opcode[0x10]; 8485 u8 uid[0x10]; 8486 8487 u8 reserved_at_20[0x10]; 8488 u8 op_mod[0x10]; 8489 8490 u8 reserved_at_40[0x8]; 8491 u8 uar[0x18]; 8492 8493 u8 reserved_at_60[0x20]; 8494 }; 8495 8496 struct mlx5_ifc_dealloc_transport_domain_out_bits { 8497 u8 status[0x8]; 8498 u8 reserved_at_8[0x18]; 8499 8500 u8 syndrome[0x20]; 8501 8502 u8 reserved_at_40[0x40]; 8503 }; 8504 8505 struct mlx5_ifc_dealloc_transport_domain_in_bits { 8506 u8 opcode[0x10]; 8507 u8 uid[0x10]; 8508 8509 u8 reserved_at_20[0x10]; 8510 u8 op_mod[0x10]; 8511 8512 u8 reserved_at_40[0x8]; 8513 u8 transport_domain[0x18]; 8514 8515 u8 reserved_at_60[0x20]; 8516 }; 8517 8518 struct mlx5_ifc_dealloc_q_counter_out_bits { 8519 u8 status[0x8]; 8520 u8 reserved_at_8[0x18]; 8521 8522 u8 syndrome[0x20]; 8523 8524 u8 reserved_at_40[0x40]; 8525 }; 8526 8527 struct mlx5_ifc_dealloc_q_counter_in_bits { 8528 u8 opcode[0x10]; 8529 u8 reserved_at_10[0x10]; 8530 8531 u8 reserved_at_20[0x10]; 8532 u8 op_mod[0x10]; 8533 8534 u8 reserved_at_40[0x18]; 8535 u8 counter_set_id[0x8]; 8536 8537 u8 reserved_at_60[0x20]; 8538 }; 8539 8540 struct mlx5_ifc_dealloc_pd_out_bits { 8541 u8 status[0x8]; 8542 u8 reserved_at_8[0x18]; 8543 8544 u8 syndrome[0x20]; 8545 8546 u8 reserved_at_40[0x40]; 8547 }; 8548 8549 struct mlx5_ifc_dealloc_pd_in_bits { 8550 u8 opcode[0x10]; 8551 u8 uid[0x10]; 8552 8553 u8 reserved_at_20[0x10]; 8554 u8 op_mod[0x10]; 8555 8556 u8 reserved_at_40[0x8]; 8557 u8 pd[0x18]; 8558 8559 u8 reserved_at_60[0x20]; 8560 }; 8561 8562 struct mlx5_ifc_dealloc_flow_counter_out_bits { 8563 u8 status[0x8]; 8564 u8 reserved_at_8[0x18]; 8565 8566 u8 syndrome[0x20]; 8567 8568 u8 reserved_at_40[0x40]; 8569 }; 8570 8571 struct mlx5_ifc_dealloc_flow_counter_in_bits { 8572 u8 opcode[0x10]; 8573 u8 reserved_at_10[0x10]; 8574 8575 u8 reserved_at_20[0x10]; 8576 u8 op_mod[0x10]; 8577 8578 u8 flow_counter_id[0x20]; 8579 8580 u8 reserved_at_60[0x20]; 8581 }; 8582 8583 struct mlx5_ifc_create_xrq_out_bits { 8584 u8 status[0x8]; 8585 u8 reserved_at_8[0x18]; 8586 8587 u8 syndrome[0x20]; 8588 8589 u8 reserved_at_40[0x8]; 8590 u8 xrqn[0x18]; 8591 8592 u8 reserved_at_60[0x20]; 8593 }; 8594 8595 struct mlx5_ifc_create_xrq_in_bits { 8596 u8 opcode[0x10]; 8597 u8 uid[0x10]; 8598 8599 u8 reserved_at_20[0x10]; 8600 u8 op_mod[0x10]; 8601 8602 u8 reserved_at_40[0x40]; 8603 8604 struct mlx5_ifc_xrqc_bits xrq_context; 8605 }; 8606 8607 struct mlx5_ifc_create_xrc_srq_out_bits { 8608 u8 status[0x8]; 8609 u8 reserved_at_8[0x18]; 8610 8611 u8 syndrome[0x20]; 8612 8613 u8 reserved_at_40[0x8]; 8614 u8 xrc_srqn[0x18]; 8615 8616 u8 reserved_at_60[0x20]; 8617 }; 8618 8619 struct mlx5_ifc_create_xrc_srq_in_bits { 8620 u8 opcode[0x10]; 8621 u8 uid[0x10]; 8622 8623 u8 reserved_at_20[0x10]; 8624 u8 op_mod[0x10]; 8625 8626 u8 reserved_at_40[0x40]; 8627 8628 struct mlx5_ifc_xrc_srqc_bits xrc_srq_context_entry; 8629 8630 u8 reserved_at_280[0x60]; 8631 8632 u8 xrc_srq_umem_valid[0x1]; 8633 u8 reserved_at_2e1[0x1f]; 8634 8635 u8 reserved_at_300[0x580]; 8636 8637 u8 pas[][0x40]; 8638 }; 8639 8640 struct mlx5_ifc_create_tis_out_bits { 8641 u8 status[0x8]; 8642 u8 reserved_at_8[0x18]; 8643 8644 u8 syndrome[0x20]; 8645 8646 u8 reserved_at_40[0x8]; 8647 u8 tisn[0x18]; 8648 8649 u8 reserved_at_60[0x20]; 8650 }; 8651 8652 struct mlx5_ifc_create_tis_in_bits { 8653 u8 opcode[0x10]; 8654 u8 uid[0x10]; 8655 8656 u8 reserved_at_20[0x10]; 8657 u8 op_mod[0x10]; 8658 8659 u8 reserved_at_40[0xc0]; 8660 8661 struct mlx5_ifc_tisc_bits ctx; 8662 }; 8663 8664 struct mlx5_ifc_create_tir_out_bits { 8665 u8 status[0x8]; 8666 u8 icm_address_63_40[0x18]; 8667 8668 u8 syndrome[0x20]; 8669 8670 u8 icm_address_39_32[0x8]; 8671 u8 tirn[0x18]; 8672 8673 u8 icm_address_31_0[0x20]; 8674 }; 8675 8676 struct mlx5_ifc_create_tir_in_bits { 8677 u8 opcode[0x10]; 8678 u8 uid[0x10]; 8679 8680 u8 reserved_at_20[0x10]; 8681 u8 op_mod[0x10]; 8682 8683 u8 reserved_at_40[0xc0]; 8684 8685 struct mlx5_ifc_tirc_bits ctx; 8686 }; 8687 8688 struct mlx5_ifc_create_srq_out_bits { 8689 u8 status[0x8]; 8690 u8 reserved_at_8[0x18]; 8691 8692 u8 syndrome[0x20]; 8693 8694 u8 reserved_at_40[0x8]; 8695 u8 srqn[0x18]; 8696 8697 u8 reserved_at_60[0x20]; 8698 }; 8699 8700 struct mlx5_ifc_create_srq_in_bits { 8701 u8 opcode[0x10]; 8702 u8 uid[0x10]; 8703 8704 u8 reserved_at_20[0x10]; 8705 u8 op_mod[0x10]; 8706 8707 u8 reserved_at_40[0x40]; 8708 8709 struct mlx5_ifc_srqc_bits srq_context_entry; 8710 8711 u8 reserved_at_280[0x600]; 8712 8713 u8 pas[][0x40]; 8714 }; 8715 8716 struct mlx5_ifc_create_sq_out_bits { 8717 u8 status[0x8]; 8718 u8 reserved_at_8[0x18]; 8719 8720 u8 syndrome[0x20]; 8721 8722 u8 reserved_at_40[0x8]; 8723 u8 sqn[0x18]; 8724 8725 u8 reserved_at_60[0x20]; 8726 }; 8727 8728 struct mlx5_ifc_create_sq_in_bits { 8729 u8 opcode[0x10]; 8730 u8 uid[0x10]; 8731 8732 u8 reserved_at_20[0x10]; 8733 u8 op_mod[0x10]; 8734 8735 u8 reserved_at_40[0xc0]; 8736 8737 struct mlx5_ifc_sqc_bits ctx; 8738 }; 8739 8740 struct mlx5_ifc_create_scheduling_element_out_bits { 8741 u8 status[0x8]; 8742 u8 reserved_at_8[0x18]; 8743 8744 u8 syndrome[0x20]; 8745 8746 u8 reserved_at_40[0x40]; 8747 8748 u8 scheduling_element_id[0x20]; 8749 8750 u8 reserved_at_a0[0x160]; 8751 }; 8752 8753 struct mlx5_ifc_create_scheduling_element_in_bits { 8754 u8 opcode[0x10]; 8755 u8 reserved_at_10[0x10]; 8756 8757 u8 reserved_at_20[0x10]; 8758 u8 op_mod[0x10]; 8759 8760 u8 scheduling_hierarchy[0x8]; 8761 u8 reserved_at_48[0x18]; 8762 8763 u8 reserved_at_60[0xa0]; 8764 8765 struct mlx5_ifc_scheduling_context_bits scheduling_context; 8766 8767 u8 reserved_at_300[0x100]; 8768 }; 8769 8770 struct mlx5_ifc_create_rqt_out_bits { 8771 u8 status[0x8]; 8772 u8 reserved_at_8[0x18]; 8773 8774 u8 syndrome[0x20]; 8775 8776 u8 reserved_at_40[0x8]; 8777 u8 rqtn[0x18]; 8778 8779 u8 reserved_at_60[0x20]; 8780 }; 8781 8782 struct mlx5_ifc_create_rqt_in_bits { 8783 u8 opcode[0x10]; 8784 u8 uid[0x10]; 8785 8786 u8 reserved_at_20[0x10]; 8787 u8 op_mod[0x10]; 8788 8789 u8 reserved_at_40[0xc0]; 8790 8791 struct mlx5_ifc_rqtc_bits rqt_context; 8792 }; 8793 8794 struct mlx5_ifc_create_rq_out_bits { 8795 u8 status[0x8]; 8796 u8 reserved_at_8[0x18]; 8797 8798 u8 syndrome[0x20]; 8799 8800 u8 reserved_at_40[0x8]; 8801 u8 rqn[0x18]; 8802 8803 u8 reserved_at_60[0x20]; 8804 }; 8805 8806 struct mlx5_ifc_create_rq_in_bits { 8807 u8 opcode[0x10]; 8808 u8 uid[0x10]; 8809 8810 u8 reserved_at_20[0x10]; 8811 u8 op_mod[0x10]; 8812 8813 u8 reserved_at_40[0xc0]; 8814 8815 struct mlx5_ifc_rqc_bits ctx; 8816 }; 8817 8818 struct mlx5_ifc_create_rmp_out_bits { 8819 u8 status[0x8]; 8820 u8 reserved_at_8[0x18]; 8821 8822 u8 syndrome[0x20]; 8823 8824 u8 reserved_at_40[0x8]; 8825 u8 rmpn[0x18]; 8826 8827 u8 reserved_at_60[0x20]; 8828 }; 8829 8830 struct mlx5_ifc_create_rmp_in_bits { 8831 u8 opcode[0x10]; 8832 u8 uid[0x10]; 8833 8834 u8 reserved_at_20[0x10]; 8835 u8 op_mod[0x10]; 8836 8837 u8 reserved_at_40[0xc0]; 8838 8839 struct mlx5_ifc_rmpc_bits ctx; 8840 }; 8841 8842 struct mlx5_ifc_create_qp_out_bits { 8843 u8 status[0x8]; 8844 u8 reserved_at_8[0x18]; 8845 8846 u8 syndrome[0x20]; 8847 8848 u8 reserved_at_40[0x8]; 8849 u8 qpn[0x18]; 8850 8851 u8 ece[0x20]; 8852 }; 8853 8854 struct mlx5_ifc_create_qp_in_bits { 8855 u8 opcode[0x10]; 8856 u8 uid[0x10]; 8857 8858 u8 reserved_at_20[0x10]; 8859 u8 op_mod[0x10]; 8860 8861 u8 qpc_ext[0x1]; 8862 u8 reserved_at_41[0x7]; 8863 u8 input_qpn[0x18]; 8864 8865 u8 reserved_at_60[0x20]; 8866 u8 opt_param_mask[0x20]; 8867 8868 u8 ece[0x20]; 8869 8870 struct mlx5_ifc_qpc_bits qpc; 8871 8872 u8 reserved_at_800[0x60]; 8873 8874 u8 wq_umem_valid[0x1]; 8875 u8 reserved_at_861[0x1f]; 8876 8877 u8 pas[][0x40]; 8878 }; 8879 8880 struct mlx5_ifc_create_psv_out_bits { 8881 u8 status[0x8]; 8882 u8 reserved_at_8[0x18]; 8883 8884 u8 syndrome[0x20]; 8885 8886 u8 reserved_at_40[0x40]; 8887 8888 u8 reserved_at_80[0x8]; 8889 u8 psv0_index[0x18]; 8890 8891 u8 reserved_at_a0[0x8]; 8892 u8 psv1_index[0x18]; 8893 8894 u8 reserved_at_c0[0x8]; 8895 u8 psv2_index[0x18]; 8896 8897 u8 reserved_at_e0[0x8]; 8898 u8 psv3_index[0x18]; 8899 }; 8900 8901 struct mlx5_ifc_create_psv_in_bits { 8902 u8 opcode[0x10]; 8903 u8 reserved_at_10[0x10]; 8904 8905 u8 reserved_at_20[0x10]; 8906 u8 op_mod[0x10]; 8907 8908 u8 num_psv[0x4]; 8909 u8 reserved_at_44[0x4]; 8910 u8 pd[0x18]; 8911 8912 u8 reserved_at_60[0x20]; 8913 }; 8914 8915 struct mlx5_ifc_create_mkey_out_bits { 8916 u8 status[0x8]; 8917 u8 reserved_at_8[0x18]; 8918 8919 u8 syndrome[0x20]; 8920 8921 u8 reserved_at_40[0x8]; 8922 u8 mkey_index[0x18]; 8923 8924 u8 reserved_at_60[0x20]; 8925 }; 8926 8927 struct mlx5_ifc_create_mkey_in_bits { 8928 u8 opcode[0x10]; 8929 u8 uid[0x10]; 8930 8931 u8 reserved_at_20[0x10]; 8932 u8 op_mod[0x10]; 8933 8934 u8 reserved_at_40[0x20]; 8935 8936 u8 pg_access[0x1]; 8937 u8 mkey_umem_valid[0x1]; 8938 u8 reserved_at_62[0x1e]; 8939 8940 struct mlx5_ifc_mkc_bits memory_key_mkey_entry; 8941 8942 u8 reserved_at_280[0x80]; 8943 8944 u8 translations_octword_actual_size[0x20]; 8945 8946 u8 reserved_at_320[0x560]; 8947 8948 u8 klm_pas_mtt[][0x20]; 8949 }; 8950 8951 enum { 8952 MLX5_FLOW_TABLE_TYPE_NIC_RX = 0x0, 8953 MLX5_FLOW_TABLE_TYPE_NIC_TX = 0x1, 8954 MLX5_FLOW_TABLE_TYPE_ESW_EGRESS_ACL = 0x2, 8955 MLX5_FLOW_TABLE_TYPE_ESW_INGRESS_ACL = 0x3, 8956 MLX5_FLOW_TABLE_TYPE_FDB = 0X4, 8957 MLX5_FLOW_TABLE_TYPE_SNIFFER_RX = 0X5, 8958 MLX5_FLOW_TABLE_TYPE_SNIFFER_TX = 0X6, 8959 }; 8960 8961 struct mlx5_ifc_create_flow_table_out_bits { 8962 u8 status[0x8]; 8963 u8 icm_address_63_40[0x18]; 8964 8965 u8 syndrome[0x20]; 8966 8967 u8 icm_address_39_32[0x8]; 8968 u8 table_id[0x18]; 8969 8970 u8 icm_address_31_0[0x20]; 8971 }; 8972 8973 struct mlx5_ifc_create_flow_table_in_bits { 8974 u8 opcode[0x10]; 8975 u8 uid[0x10]; 8976 8977 u8 reserved_at_20[0x10]; 8978 u8 op_mod[0x10]; 8979 8980 u8 other_vport[0x1]; 8981 u8 reserved_at_41[0xf]; 8982 u8 vport_number[0x10]; 8983 8984 u8 reserved_at_60[0x20]; 8985 8986 u8 table_type[0x8]; 8987 u8 reserved_at_88[0x18]; 8988 8989 u8 reserved_at_a0[0x20]; 8990 8991 struct mlx5_ifc_flow_table_context_bits flow_table_context; 8992 }; 8993 8994 struct mlx5_ifc_create_flow_group_out_bits { 8995 u8 status[0x8]; 8996 u8 reserved_at_8[0x18]; 8997 8998 u8 syndrome[0x20]; 8999 9000 u8 reserved_at_40[0x8]; 9001 u8 group_id[0x18]; 9002 9003 u8 reserved_at_60[0x20]; 9004 }; 9005 9006 enum { 9007 MLX5_CREATE_FLOW_GROUP_IN_GROUP_TYPE_TCAM_SUBTABLE = 0x0, 9008 MLX5_CREATE_FLOW_GROUP_IN_GROUP_TYPE_HASH_SPLIT = 0x1, 9009 }; 9010 9011 enum { 9012 MLX5_CREATE_FLOW_GROUP_IN_MATCH_CRITERIA_ENABLE_OUTER_HEADERS = 0x0, 9013 MLX5_CREATE_FLOW_GROUP_IN_MATCH_CRITERIA_ENABLE_MISC_PARAMETERS = 0x1, 9014 MLX5_CREATE_FLOW_GROUP_IN_MATCH_CRITERIA_ENABLE_INNER_HEADERS = 0x2, 9015 MLX5_CREATE_FLOW_GROUP_IN_MATCH_CRITERIA_ENABLE_MISC_PARAMETERS_2 = 0x3, 9016 }; 9017 9018 struct mlx5_ifc_create_flow_group_in_bits { 9019 u8 opcode[0x10]; 9020 u8 reserved_at_10[0x10]; 9021 9022 u8 reserved_at_20[0x10]; 9023 u8 op_mod[0x10]; 9024 9025 u8 other_vport[0x1]; 9026 u8 reserved_at_41[0xf]; 9027 u8 vport_number[0x10]; 9028 9029 u8 reserved_at_60[0x20]; 9030 9031 u8 table_type[0x8]; 9032 u8 reserved_at_88[0x4]; 9033 u8 group_type[0x4]; 9034 u8 reserved_at_90[0x10]; 9035 9036 u8 reserved_at_a0[0x8]; 9037 u8 table_id[0x18]; 9038 9039 u8 source_eswitch_owner_vhca_id_valid[0x1]; 9040 9041 u8 reserved_at_c1[0x1f]; 9042 9043 u8 start_flow_index[0x20]; 9044 9045 u8 reserved_at_100[0x20]; 9046 9047 u8 end_flow_index[0x20]; 9048 9049 u8 reserved_at_140[0x10]; 9050 u8 match_definer_id[0x10]; 9051 9052 u8 reserved_at_160[0x80]; 9053 9054 u8 reserved_at_1e0[0x18]; 9055 u8 match_criteria_enable[0x8]; 9056 9057 struct mlx5_ifc_fte_match_param_bits match_criteria; 9058 9059 u8 reserved_at_1200[0xe00]; 9060 }; 9061 9062 struct mlx5_ifc_create_eq_out_bits { 9063 u8 status[0x8]; 9064 u8 reserved_at_8[0x18]; 9065 9066 u8 syndrome[0x20]; 9067 9068 u8 reserved_at_40[0x18]; 9069 u8 eq_number[0x8]; 9070 9071 u8 reserved_at_60[0x20]; 9072 }; 9073 9074 struct mlx5_ifc_create_eq_in_bits { 9075 u8 opcode[0x10]; 9076 u8 uid[0x10]; 9077 9078 u8 reserved_at_20[0x10]; 9079 u8 op_mod[0x10]; 9080 9081 u8 reserved_at_40[0x40]; 9082 9083 struct mlx5_ifc_eqc_bits eq_context_entry; 9084 9085 u8 reserved_at_280[0x40]; 9086 9087 u8 event_bitmask[4][0x40]; 9088 9089 u8 reserved_at_3c0[0x4c0]; 9090 9091 u8 pas[][0x40]; 9092 }; 9093 9094 struct mlx5_ifc_create_dct_out_bits { 9095 u8 status[0x8]; 9096 u8 reserved_at_8[0x18]; 9097 9098 u8 syndrome[0x20]; 9099 9100 u8 reserved_at_40[0x8]; 9101 u8 dctn[0x18]; 9102 9103 u8 ece[0x20]; 9104 }; 9105 9106 struct mlx5_ifc_create_dct_in_bits { 9107 u8 opcode[0x10]; 9108 u8 uid[0x10]; 9109 9110 u8 reserved_at_20[0x10]; 9111 u8 op_mod[0x10]; 9112 9113 u8 reserved_at_40[0x40]; 9114 9115 struct mlx5_ifc_dctc_bits dct_context_entry; 9116 9117 u8 reserved_at_280[0x180]; 9118 }; 9119 9120 struct mlx5_ifc_create_cq_out_bits { 9121 u8 status[0x8]; 9122 u8 reserved_at_8[0x18]; 9123 9124 u8 syndrome[0x20]; 9125 9126 u8 reserved_at_40[0x8]; 9127 u8 cqn[0x18]; 9128 9129 u8 reserved_at_60[0x20]; 9130 }; 9131 9132 struct mlx5_ifc_create_cq_in_bits { 9133 u8 opcode[0x10]; 9134 u8 uid[0x10]; 9135 9136 u8 reserved_at_20[0x10]; 9137 u8 op_mod[0x10]; 9138 9139 u8 reserved_at_40[0x40]; 9140 9141 struct mlx5_ifc_cqc_bits cq_context; 9142 9143 u8 reserved_at_280[0x60]; 9144 9145 u8 cq_umem_valid[0x1]; 9146 u8 reserved_at_2e1[0x59f]; 9147 9148 u8 pas[][0x40]; 9149 }; 9150 9151 struct mlx5_ifc_config_int_moderation_out_bits { 9152 u8 status[0x8]; 9153 u8 reserved_at_8[0x18]; 9154 9155 u8 syndrome[0x20]; 9156 9157 u8 reserved_at_40[0x4]; 9158 u8 min_delay[0xc]; 9159 u8 int_vector[0x10]; 9160 9161 u8 reserved_at_60[0x20]; 9162 }; 9163 9164 enum { 9165 MLX5_CONFIG_INT_MODERATION_IN_OP_MOD_WRITE = 0x0, 9166 MLX5_CONFIG_INT_MODERATION_IN_OP_MOD_READ = 0x1, 9167 }; 9168 9169 struct mlx5_ifc_config_int_moderation_in_bits { 9170 u8 opcode[0x10]; 9171 u8 reserved_at_10[0x10]; 9172 9173 u8 reserved_at_20[0x10]; 9174 u8 op_mod[0x10]; 9175 9176 u8 reserved_at_40[0x4]; 9177 u8 min_delay[0xc]; 9178 u8 int_vector[0x10]; 9179 9180 u8 reserved_at_60[0x20]; 9181 }; 9182 9183 struct mlx5_ifc_attach_to_mcg_out_bits { 9184 u8 status[0x8]; 9185 u8 reserved_at_8[0x18]; 9186 9187 u8 syndrome[0x20]; 9188 9189 u8 reserved_at_40[0x40]; 9190 }; 9191 9192 struct mlx5_ifc_attach_to_mcg_in_bits { 9193 u8 opcode[0x10]; 9194 u8 uid[0x10]; 9195 9196 u8 reserved_at_20[0x10]; 9197 u8 op_mod[0x10]; 9198 9199 u8 reserved_at_40[0x8]; 9200 u8 qpn[0x18]; 9201 9202 u8 reserved_at_60[0x20]; 9203 9204 u8 multicast_gid[16][0x8]; 9205 }; 9206 9207 struct mlx5_ifc_arm_xrq_out_bits { 9208 u8 status[0x8]; 9209 u8 reserved_at_8[0x18]; 9210 9211 u8 syndrome[0x20]; 9212 9213 u8 reserved_at_40[0x40]; 9214 }; 9215 9216 struct mlx5_ifc_arm_xrq_in_bits { 9217 u8 opcode[0x10]; 9218 u8 reserved_at_10[0x10]; 9219 9220 u8 reserved_at_20[0x10]; 9221 u8 op_mod[0x10]; 9222 9223 u8 reserved_at_40[0x8]; 9224 u8 xrqn[0x18]; 9225 9226 u8 reserved_at_60[0x10]; 9227 u8 lwm[0x10]; 9228 }; 9229 9230 struct mlx5_ifc_arm_xrc_srq_out_bits { 9231 u8 status[0x8]; 9232 u8 reserved_at_8[0x18]; 9233 9234 u8 syndrome[0x20]; 9235 9236 u8 reserved_at_40[0x40]; 9237 }; 9238 9239 enum { 9240 MLX5_ARM_XRC_SRQ_IN_OP_MOD_XRC_SRQ = 0x1, 9241 }; 9242 9243 struct mlx5_ifc_arm_xrc_srq_in_bits { 9244 u8 opcode[0x10]; 9245 u8 uid[0x10]; 9246 9247 u8 reserved_at_20[0x10]; 9248 u8 op_mod[0x10]; 9249 9250 u8 reserved_at_40[0x8]; 9251 u8 xrc_srqn[0x18]; 9252 9253 u8 reserved_at_60[0x10]; 9254 u8 lwm[0x10]; 9255 }; 9256 9257 struct mlx5_ifc_arm_rq_out_bits { 9258 u8 status[0x8]; 9259 u8 reserved_at_8[0x18]; 9260 9261 u8 syndrome[0x20]; 9262 9263 u8 reserved_at_40[0x40]; 9264 }; 9265 9266 enum { 9267 MLX5_ARM_RQ_IN_OP_MOD_SRQ = 0x1, 9268 MLX5_ARM_RQ_IN_OP_MOD_XRQ = 0x2, 9269 }; 9270 9271 struct mlx5_ifc_arm_rq_in_bits { 9272 u8 opcode[0x10]; 9273 u8 uid[0x10]; 9274 9275 u8 reserved_at_20[0x10]; 9276 u8 op_mod[0x10]; 9277 9278 u8 reserved_at_40[0x8]; 9279 u8 srq_number[0x18]; 9280 9281 u8 reserved_at_60[0x10]; 9282 u8 lwm[0x10]; 9283 }; 9284 9285 struct mlx5_ifc_arm_dct_out_bits { 9286 u8 status[0x8]; 9287 u8 reserved_at_8[0x18]; 9288 9289 u8 syndrome[0x20]; 9290 9291 u8 reserved_at_40[0x40]; 9292 }; 9293 9294 struct mlx5_ifc_arm_dct_in_bits { 9295 u8 opcode[0x10]; 9296 u8 reserved_at_10[0x10]; 9297 9298 u8 reserved_at_20[0x10]; 9299 u8 op_mod[0x10]; 9300 9301 u8 reserved_at_40[0x8]; 9302 u8 dct_number[0x18]; 9303 9304 u8 reserved_at_60[0x20]; 9305 }; 9306 9307 struct mlx5_ifc_alloc_xrcd_out_bits { 9308 u8 status[0x8]; 9309 u8 reserved_at_8[0x18]; 9310 9311 u8 syndrome[0x20]; 9312 9313 u8 reserved_at_40[0x8]; 9314 u8 xrcd[0x18]; 9315 9316 u8 reserved_at_60[0x20]; 9317 }; 9318 9319 struct mlx5_ifc_alloc_xrcd_in_bits { 9320 u8 opcode[0x10]; 9321 u8 uid[0x10]; 9322 9323 u8 reserved_at_20[0x10]; 9324 u8 op_mod[0x10]; 9325 9326 u8 reserved_at_40[0x40]; 9327 }; 9328 9329 struct mlx5_ifc_alloc_uar_out_bits { 9330 u8 status[0x8]; 9331 u8 reserved_at_8[0x18]; 9332 9333 u8 syndrome[0x20]; 9334 9335 u8 reserved_at_40[0x8]; 9336 u8 uar[0x18]; 9337 9338 u8 reserved_at_60[0x20]; 9339 }; 9340 9341 struct mlx5_ifc_alloc_uar_in_bits { 9342 u8 opcode[0x10]; 9343 u8 uid[0x10]; 9344 9345 u8 reserved_at_20[0x10]; 9346 u8 op_mod[0x10]; 9347 9348 u8 reserved_at_40[0x40]; 9349 }; 9350 9351 struct mlx5_ifc_alloc_transport_domain_out_bits { 9352 u8 status[0x8]; 9353 u8 reserved_at_8[0x18]; 9354 9355 u8 syndrome[0x20]; 9356 9357 u8 reserved_at_40[0x8]; 9358 u8 transport_domain[0x18]; 9359 9360 u8 reserved_at_60[0x20]; 9361 }; 9362 9363 struct mlx5_ifc_alloc_transport_domain_in_bits { 9364 u8 opcode[0x10]; 9365 u8 uid[0x10]; 9366 9367 u8 reserved_at_20[0x10]; 9368 u8 op_mod[0x10]; 9369 9370 u8 reserved_at_40[0x40]; 9371 }; 9372 9373 struct mlx5_ifc_alloc_q_counter_out_bits { 9374 u8 status[0x8]; 9375 u8 reserved_at_8[0x18]; 9376 9377 u8 syndrome[0x20]; 9378 9379 u8 reserved_at_40[0x18]; 9380 u8 counter_set_id[0x8]; 9381 9382 u8 reserved_at_60[0x20]; 9383 }; 9384 9385 struct mlx5_ifc_alloc_q_counter_in_bits { 9386 u8 opcode[0x10]; 9387 u8 uid[0x10]; 9388 9389 u8 reserved_at_20[0x10]; 9390 u8 op_mod[0x10]; 9391 9392 u8 reserved_at_40[0x40]; 9393 }; 9394 9395 struct mlx5_ifc_alloc_pd_out_bits { 9396 u8 status[0x8]; 9397 u8 reserved_at_8[0x18]; 9398 9399 u8 syndrome[0x20]; 9400 9401 u8 reserved_at_40[0x8]; 9402 u8 pd[0x18]; 9403 9404 u8 reserved_at_60[0x20]; 9405 }; 9406 9407 struct mlx5_ifc_alloc_pd_in_bits { 9408 u8 opcode[0x10]; 9409 u8 uid[0x10]; 9410 9411 u8 reserved_at_20[0x10]; 9412 u8 op_mod[0x10]; 9413 9414 u8 reserved_at_40[0x40]; 9415 }; 9416 9417 struct mlx5_ifc_alloc_flow_counter_out_bits { 9418 u8 status[0x8]; 9419 u8 reserved_at_8[0x18]; 9420 9421 u8 syndrome[0x20]; 9422 9423 u8 flow_counter_id[0x20]; 9424 9425 u8 reserved_at_60[0x20]; 9426 }; 9427 9428 struct mlx5_ifc_alloc_flow_counter_in_bits { 9429 u8 opcode[0x10]; 9430 u8 reserved_at_10[0x10]; 9431 9432 u8 reserved_at_20[0x10]; 9433 u8 op_mod[0x10]; 9434 9435 u8 reserved_at_40[0x33]; 9436 u8 flow_counter_bulk_log_size[0x5]; 9437 u8 flow_counter_bulk[0x8]; 9438 }; 9439 9440 struct mlx5_ifc_add_vxlan_udp_dport_out_bits { 9441 u8 status[0x8]; 9442 u8 reserved_at_8[0x18]; 9443 9444 u8 syndrome[0x20]; 9445 9446 u8 reserved_at_40[0x40]; 9447 }; 9448 9449 struct mlx5_ifc_add_vxlan_udp_dport_in_bits { 9450 u8 opcode[0x10]; 9451 u8 reserved_at_10[0x10]; 9452 9453 u8 reserved_at_20[0x10]; 9454 u8 op_mod[0x10]; 9455 9456 u8 reserved_at_40[0x20]; 9457 9458 u8 reserved_at_60[0x10]; 9459 u8 vxlan_udp_port[0x10]; 9460 }; 9461 9462 struct mlx5_ifc_set_pp_rate_limit_out_bits { 9463 u8 status[0x8]; 9464 u8 reserved_at_8[0x18]; 9465 9466 u8 syndrome[0x20]; 9467 9468 u8 reserved_at_40[0x40]; 9469 }; 9470 9471 struct mlx5_ifc_set_pp_rate_limit_context_bits { 9472 u8 rate_limit[0x20]; 9473 9474 u8 burst_upper_bound[0x20]; 9475 9476 u8 reserved_at_40[0x10]; 9477 u8 typical_packet_size[0x10]; 9478 9479 u8 reserved_at_60[0x120]; 9480 }; 9481 9482 struct mlx5_ifc_set_pp_rate_limit_in_bits { 9483 u8 opcode[0x10]; 9484 u8 uid[0x10]; 9485 9486 u8 reserved_at_20[0x10]; 9487 u8 op_mod[0x10]; 9488 9489 u8 reserved_at_40[0x10]; 9490 u8 rate_limit_index[0x10]; 9491 9492 u8 reserved_at_60[0x20]; 9493 9494 struct mlx5_ifc_set_pp_rate_limit_context_bits ctx; 9495 }; 9496 9497 struct mlx5_ifc_access_register_out_bits { 9498 u8 status[0x8]; 9499 u8 reserved_at_8[0x18]; 9500 9501 u8 syndrome[0x20]; 9502 9503 u8 reserved_at_40[0x40]; 9504 9505 u8 register_data[][0x20]; 9506 }; 9507 9508 enum { 9509 MLX5_ACCESS_REGISTER_IN_OP_MOD_WRITE = 0x0, 9510 MLX5_ACCESS_REGISTER_IN_OP_MOD_READ = 0x1, 9511 }; 9512 9513 struct mlx5_ifc_access_register_in_bits { 9514 u8 opcode[0x10]; 9515 u8 reserved_at_10[0x10]; 9516 9517 u8 reserved_at_20[0x10]; 9518 u8 op_mod[0x10]; 9519 9520 u8 reserved_at_40[0x10]; 9521 u8 register_id[0x10]; 9522 9523 u8 argument[0x20]; 9524 9525 u8 register_data[][0x20]; 9526 }; 9527 9528 struct mlx5_ifc_sltp_reg_bits { 9529 u8 status[0x4]; 9530 u8 version[0x4]; 9531 u8 local_port[0x8]; 9532 u8 pnat[0x2]; 9533 u8 reserved_at_12[0x2]; 9534 u8 lane[0x4]; 9535 u8 reserved_at_18[0x8]; 9536 9537 u8 reserved_at_20[0x20]; 9538 9539 u8 reserved_at_40[0x7]; 9540 u8 polarity[0x1]; 9541 u8 ob_tap0[0x8]; 9542 u8 ob_tap1[0x8]; 9543 u8 ob_tap2[0x8]; 9544 9545 u8 reserved_at_60[0xc]; 9546 u8 ob_preemp_mode[0x4]; 9547 u8 ob_reg[0x8]; 9548 u8 ob_bias[0x8]; 9549 9550 u8 reserved_at_80[0x20]; 9551 }; 9552 9553 struct mlx5_ifc_slrg_reg_bits { 9554 u8 status[0x4]; 9555 u8 version[0x4]; 9556 u8 local_port[0x8]; 9557 u8 pnat[0x2]; 9558 u8 reserved_at_12[0x2]; 9559 u8 lane[0x4]; 9560 u8 reserved_at_18[0x8]; 9561 9562 u8 time_to_link_up[0x10]; 9563 u8 reserved_at_30[0xc]; 9564 u8 grade_lane_speed[0x4]; 9565 9566 u8 grade_version[0x8]; 9567 u8 grade[0x18]; 9568 9569 u8 reserved_at_60[0x4]; 9570 u8 height_grade_type[0x4]; 9571 u8 height_grade[0x18]; 9572 9573 u8 height_dz[0x10]; 9574 u8 height_dv[0x10]; 9575 9576 u8 reserved_at_a0[0x10]; 9577 u8 height_sigma[0x10]; 9578 9579 u8 reserved_at_c0[0x20]; 9580 9581 u8 reserved_at_e0[0x4]; 9582 u8 phase_grade_type[0x4]; 9583 u8 phase_grade[0x18]; 9584 9585 u8 reserved_at_100[0x8]; 9586 u8 phase_eo_pos[0x8]; 9587 u8 reserved_at_110[0x8]; 9588 u8 phase_eo_neg[0x8]; 9589 9590 u8 ffe_set_tested[0x10]; 9591 u8 test_errors_per_lane[0x10]; 9592 }; 9593 9594 struct mlx5_ifc_pvlc_reg_bits { 9595 u8 reserved_at_0[0x8]; 9596 u8 local_port[0x8]; 9597 u8 reserved_at_10[0x10]; 9598 9599 u8 reserved_at_20[0x1c]; 9600 u8 vl_hw_cap[0x4]; 9601 9602 u8 reserved_at_40[0x1c]; 9603 u8 vl_admin[0x4]; 9604 9605 u8 reserved_at_60[0x1c]; 9606 u8 vl_operational[0x4]; 9607 }; 9608 9609 struct mlx5_ifc_pude_reg_bits { 9610 u8 swid[0x8]; 9611 u8 local_port[0x8]; 9612 u8 reserved_at_10[0x4]; 9613 u8 admin_status[0x4]; 9614 u8 reserved_at_18[0x4]; 9615 u8 oper_status[0x4]; 9616 9617 u8 reserved_at_20[0x60]; 9618 }; 9619 9620 struct mlx5_ifc_ptys_reg_bits { 9621 u8 reserved_at_0[0x1]; 9622 u8 an_disable_admin[0x1]; 9623 u8 an_disable_cap[0x1]; 9624 u8 reserved_at_3[0x5]; 9625 u8 local_port[0x8]; 9626 u8 reserved_at_10[0xd]; 9627 u8 proto_mask[0x3]; 9628 9629 u8 an_status[0x4]; 9630 u8 reserved_at_24[0xc]; 9631 u8 data_rate_oper[0x10]; 9632 9633 u8 ext_eth_proto_capability[0x20]; 9634 9635 u8 eth_proto_capability[0x20]; 9636 9637 u8 ib_link_width_capability[0x10]; 9638 u8 ib_proto_capability[0x10]; 9639 9640 u8 ext_eth_proto_admin[0x20]; 9641 9642 u8 eth_proto_admin[0x20]; 9643 9644 u8 ib_link_width_admin[0x10]; 9645 u8 ib_proto_admin[0x10]; 9646 9647 u8 ext_eth_proto_oper[0x20]; 9648 9649 u8 eth_proto_oper[0x20]; 9650 9651 u8 ib_link_width_oper[0x10]; 9652 u8 ib_proto_oper[0x10]; 9653 9654 u8 reserved_at_160[0x1c]; 9655 u8 connector_type[0x4]; 9656 9657 u8 eth_proto_lp_advertise[0x20]; 9658 9659 u8 reserved_at_1a0[0x60]; 9660 }; 9661 9662 struct mlx5_ifc_mlcr_reg_bits { 9663 u8 reserved_at_0[0x8]; 9664 u8 local_port[0x8]; 9665 u8 reserved_at_10[0x20]; 9666 9667 u8 beacon_duration[0x10]; 9668 u8 reserved_at_40[0x10]; 9669 9670 u8 beacon_remain[0x10]; 9671 }; 9672 9673 struct mlx5_ifc_ptas_reg_bits { 9674 u8 reserved_at_0[0x20]; 9675 9676 u8 algorithm_options[0x10]; 9677 u8 reserved_at_30[0x4]; 9678 u8 repetitions_mode[0x4]; 9679 u8 num_of_repetitions[0x8]; 9680 9681 u8 grade_version[0x8]; 9682 u8 height_grade_type[0x4]; 9683 u8 phase_grade_type[0x4]; 9684 u8 height_grade_weight[0x8]; 9685 u8 phase_grade_weight[0x8]; 9686 9687 u8 gisim_measure_bits[0x10]; 9688 u8 adaptive_tap_measure_bits[0x10]; 9689 9690 u8 ber_bath_high_error_threshold[0x10]; 9691 u8 ber_bath_mid_error_threshold[0x10]; 9692 9693 u8 ber_bath_low_error_threshold[0x10]; 9694 u8 one_ratio_high_threshold[0x10]; 9695 9696 u8 one_ratio_high_mid_threshold[0x10]; 9697 u8 one_ratio_low_mid_threshold[0x10]; 9698 9699 u8 one_ratio_low_threshold[0x10]; 9700 u8 ndeo_error_threshold[0x10]; 9701 9702 u8 mixer_offset_step_size[0x10]; 9703 u8 reserved_at_110[0x8]; 9704 u8 mix90_phase_for_voltage_bath[0x8]; 9705 9706 u8 mixer_offset_start[0x10]; 9707 u8 mixer_offset_end[0x10]; 9708 9709 u8 reserved_at_140[0x15]; 9710 u8 ber_test_time[0xb]; 9711 }; 9712 9713 struct mlx5_ifc_pspa_reg_bits { 9714 u8 swid[0x8]; 9715 u8 local_port[0x8]; 9716 u8 sub_port[0x8]; 9717 u8 reserved_at_18[0x8]; 9718 9719 u8 reserved_at_20[0x20]; 9720 }; 9721 9722 struct mlx5_ifc_pqdr_reg_bits { 9723 u8 reserved_at_0[0x8]; 9724 u8 local_port[0x8]; 9725 u8 reserved_at_10[0x5]; 9726 u8 prio[0x3]; 9727 u8 reserved_at_18[0x6]; 9728 u8 mode[0x2]; 9729 9730 u8 reserved_at_20[0x20]; 9731 9732 u8 reserved_at_40[0x10]; 9733 u8 min_threshold[0x10]; 9734 9735 u8 reserved_at_60[0x10]; 9736 u8 max_threshold[0x10]; 9737 9738 u8 reserved_at_80[0x10]; 9739 u8 mark_probability_denominator[0x10]; 9740 9741 u8 reserved_at_a0[0x60]; 9742 }; 9743 9744 struct mlx5_ifc_ppsc_reg_bits { 9745 u8 reserved_at_0[0x8]; 9746 u8 local_port[0x8]; 9747 u8 reserved_at_10[0x10]; 9748 9749 u8 reserved_at_20[0x60]; 9750 9751 u8 reserved_at_80[0x1c]; 9752 u8 wrps_admin[0x4]; 9753 9754 u8 reserved_at_a0[0x1c]; 9755 u8 wrps_status[0x4]; 9756 9757 u8 reserved_at_c0[0x8]; 9758 u8 up_threshold[0x8]; 9759 u8 reserved_at_d0[0x8]; 9760 u8 down_threshold[0x8]; 9761 9762 u8 reserved_at_e0[0x20]; 9763 9764 u8 reserved_at_100[0x1c]; 9765 u8 srps_admin[0x4]; 9766 9767 u8 reserved_at_120[0x1c]; 9768 u8 srps_status[0x4]; 9769 9770 u8 reserved_at_140[0x40]; 9771 }; 9772 9773 struct mlx5_ifc_pplr_reg_bits { 9774 u8 reserved_at_0[0x8]; 9775 u8 local_port[0x8]; 9776 u8 reserved_at_10[0x10]; 9777 9778 u8 reserved_at_20[0x8]; 9779 u8 lb_cap[0x8]; 9780 u8 reserved_at_30[0x8]; 9781 u8 lb_en[0x8]; 9782 }; 9783 9784 struct mlx5_ifc_pplm_reg_bits { 9785 u8 reserved_at_0[0x8]; 9786 u8 local_port[0x8]; 9787 u8 reserved_at_10[0x10]; 9788 9789 u8 reserved_at_20[0x20]; 9790 9791 u8 port_profile_mode[0x8]; 9792 u8 static_port_profile[0x8]; 9793 u8 active_port_profile[0x8]; 9794 u8 reserved_at_58[0x8]; 9795 9796 u8 retransmission_active[0x8]; 9797 u8 fec_mode_active[0x18]; 9798 9799 u8 rs_fec_correction_bypass_cap[0x4]; 9800 u8 reserved_at_84[0x8]; 9801 u8 fec_override_cap_56g[0x4]; 9802 u8 fec_override_cap_100g[0x4]; 9803 u8 fec_override_cap_50g[0x4]; 9804 u8 fec_override_cap_25g[0x4]; 9805 u8 fec_override_cap_10g_40g[0x4]; 9806 9807 u8 rs_fec_correction_bypass_admin[0x4]; 9808 u8 reserved_at_a4[0x8]; 9809 u8 fec_override_admin_56g[0x4]; 9810 u8 fec_override_admin_100g[0x4]; 9811 u8 fec_override_admin_50g[0x4]; 9812 u8 fec_override_admin_25g[0x4]; 9813 u8 fec_override_admin_10g_40g[0x4]; 9814 9815 u8 fec_override_cap_400g_8x[0x10]; 9816 u8 fec_override_cap_200g_4x[0x10]; 9817 9818 u8 fec_override_cap_100g_2x[0x10]; 9819 u8 fec_override_cap_50g_1x[0x10]; 9820 9821 u8 fec_override_admin_400g_8x[0x10]; 9822 u8 fec_override_admin_200g_4x[0x10]; 9823 9824 u8 fec_override_admin_100g_2x[0x10]; 9825 u8 fec_override_admin_50g_1x[0x10]; 9826 9827 u8 fec_override_cap_800g_8x[0x10]; 9828 u8 fec_override_cap_400g_4x[0x10]; 9829 9830 u8 fec_override_cap_200g_2x[0x10]; 9831 u8 fec_override_cap_100g_1x[0x10]; 9832 9833 u8 reserved_at_180[0xa0]; 9834 9835 u8 fec_override_admin_800g_8x[0x10]; 9836 u8 fec_override_admin_400g_4x[0x10]; 9837 9838 u8 fec_override_admin_200g_2x[0x10]; 9839 u8 fec_override_admin_100g_1x[0x10]; 9840 9841 u8 reserved_at_260[0x20]; 9842 }; 9843 9844 struct mlx5_ifc_ppcnt_reg_bits { 9845 u8 swid[0x8]; 9846 u8 local_port[0x8]; 9847 u8 pnat[0x2]; 9848 u8 reserved_at_12[0x8]; 9849 u8 grp[0x6]; 9850 9851 u8 clr[0x1]; 9852 u8 reserved_at_21[0x1c]; 9853 u8 prio_tc[0x3]; 9854 9855 union mlx5_ifc_eth_cntrs_grp_data_layout_auto_bits counter_set; 9856 }; 9857 9858 struct mlx5_ifc_mpein_reg_bits { 9859 u8 reserved_at_0[0x2]; 9860 u8 depth[0x6]; 9861 u8 pcie_index[0x8]; 9862 u8 node[0x8]; 9863 u8 reserved_at_18[0x8]; 9864 9865 u8 capability_mask[0x20]; 9866 9867 u8 reserved_at_40[0x8]; 9868 u8 link_width_enabled[0x8]; 9869 u8 link_speed_enabled[0x10]; 9870 9871 u8 lane0_physical_position[0x8]; 9872 u8 link_width_active[0x8]; 9873 u8 link_speed_active[0x10]; 9874 9875 u8 num_of_pfs[0x10]; 9876 u8 num_of_vfs[0x10]; 9877 9878 u8 bdf0[0x10]; 9879 u8 reserved_at_b0[0x10]; 9880 9881 u8 max_read_request_size[0x4]; 9882 u8 max_payload_size[0x4]; 9883 u8 reserved_at_c8[0x5]; 9884 u8 pwr_status[0x3]; 9885 u8 port_type[0x4]; 9886 u8 reserved_at_d4[0xb]; 9887 u8 lane_reversal[0x1]; 9888 9889 u8 reserved_at_e0[0x14]; 9890 u8 pci_power[0xc]; 9891 9892 u8 reserved_at_100[0x20]; 9893 9894 u8 device_status[0x10]; 9895 u8 port_state[0x8]; 9896 u8 reserved_at_138[0x8]; 9897 9898 u8 reserved_at_140[0x10]; 9899 u8 receiver_detect_result[0x10]; 9900 9901 u8 reserved_at_160[0x20]; 9902 }; 9903 9904 struct mlx5_ifc_mpcnt_reg_bits { 9905 u8 reserved_at_0[0x8]; 9906 u8 pcie_index[0x8]; 9907 u8 reserved_at_10[0xa]; 9908 u8 grp[0x6]; 9909 9910 u8 clr[0x1]; 9911 u8 reserved_at_21[0x1f]; 9912 9913 union mlx5_ifc_pcie_cntrs_grp_data_layout_auto_bits counter_set; 9914 }; 9915 9916 struct mlx5_ifc_ppad_reg_bits { 9917 u8 reserved_at_0[0x3]; 9918 u8 single_mac[0x1]; 9919 u8 reserved_at_4[0x4]; 9920 u8 local_port[0x8]; 9921 u8 mac_47_32[0x10]; 9922 9923 u8 mac_31_0[0x20]; 9924 9925 u8 reserved_at_40[0x40]; 9926 }; 9927 9928 struct mlx5_ifc_pmtu_reg_bits { 9929 u8 reserved_at_0[0x8]; 9930 u8 local_port[0x8]; 9931 u8 reserved_at_10[0x10]; 9932 9933 u8 max_mtu[0x10]; 9934 u8 reserved_at_30[0x10]; 9935 9936 u8 admin_mtu[0x10]; 9937 u8 reserved_at_50[0x10]; 9938 9939 u8 oper_mtu[0x10]; 9940 u8 reserved_at_70[0x10]; 9941 }; 9942 9943 struct mlx5_ifc_pmpr_reg_bits { 9944 u8 reserved_at_0[0x8]; 9945 u8 module[0x8]; 9946 u8 reserved_at_10[0x10]; 9947 9948 u8 reserved_at_20[0x18]; 9949 u8 attenuation_5g[0x8]; 9950 9951 u8 reserved_at_40[0x18]; 9952 u8 attenuation_7g[0x8]; 9953 9954 u8 reserved_at_60[0x18]; 9955 u8 attenuation_12g[0x8]; 9956 }; 9957 9958 struct mlx5_ifc_pmpe_reg_bits { 9959 u8 reserved_at_0[0x8]; 9960 u8 module[0x8]; 9961 u8 reserved_at_10[0xc]; 9962 u8 module_status[0x4]; 9963 9964 u8 reserved_at_20[0x60]; 9965 }; 9966 9967 struct mlx5_ifc_pmpc_reg_bits { 9968 u8 module_state_updated[32][0x8]; 9969 }; 9970 9971 struct mlx5_ifc_pmlpn_reg_bits { 9972 u8 reserved_at_0[0x4]; 9973 u8 mlpn_status[0x4]; 9974 u8 local_port[0x8]; 9975 u8 reserved_at_10[0x10]; 9976 9977 u8 e[0x1]; 9978 u8 reserved_at_21[0x1f]; 9979 }; 9980 9981 struct mlx5_ifc_pmlp_reg_bits { 9982 u8 rxtx[0x1]; 9983 u8 reserved_at_1[0x7]; 9984 u8 local_port[0x8]; 9985 u8 reserved_at_10[0x8]; 9986 u8 width[0x8]; 9987 9988 u8 lane0_module_mapping[0x20]; 9989 9990 u8 lane1_module_mapping[0x20]; 9991 9992 u8 lane2_module_mapping[0x20]; 9993 9994 u8 lane3_module_mapping[0x20]; 9995 9996 u8 reserved_at_a0[0x160]; 9997 }; 9998 9999 struct mlx5_ifc_pmaos_reg_bits { 10000 u8 reserved_at_0[0x8]; 10001 u8 module[0x8]; 10002 u8 reserved_at_10[0x4]; 10003 u8 admin_status[0x4]; 10004 u8 reserved_at_18[0x4]; 10005 u8 oper_status[0x4]; 10006 10007 u8 ase[0x1]; 10008 u8 ee[0x1]; 10009 u8 reserved_at_22[0x1c]; 10010 u8 e[0x2]; 10011 10012 u8 reserved_at_40[0x40]; 10013 }; 10014 10015 struct mlx5_ifc_plpc_reg_bits { 10016 u8 reserved_at_0[0x4]; 10017 u8 profile_id[0xc]; 10018 u8 reserved_at_10[0x4]; 10019 u8 proto_mask[0x4]; 10020 u8 reserved_at_18[0x8]; 10021 10022 u8 reserved_at_20[0x10]; 10023 u8 lane_speed[0x10]; 10024 10025 u8 reserved_at_40[0x17]; 10026 u8 lpbf[0x1]; 10027 u8 fec_mode_policy[0x8]; 10028 10029 u8 retransmission_capability[0x8]; 10030 u8 fec_mode_capability[0x18]; 10031 10032 u8 retransmission_support_admin[0x8]; 10033 u8 fec_mode_support_admin[0x18]; 10034 10035 u8 retransmission_request_admin[0x8]; 10036 u8 fec_mode_request_admin[0x18]; 10037 10038 u8 reserved_at_c0[0x80]; 10039 }; 10040 10041 struct mlx5_ifc_plib_reg_bits { 10042 u8 reserved_at_0[0x8]; 10043 u8 local_port[0x8]; 10044 u8 reserved_at_10[0x8]; 10045 u8 ib_port[0x8]; 10046 10047 u8 reserved_at_20[0x60]; 10048 }; 10049 10050 struct mlx5_ifc_plbf_reg_bits { 10051 u8 reserved_at_0[0x8]; 10052 u8 local_port[0x8]; 10053 u8 reserved_at_10[0xd]; 10054 u8 lbf_mode[0x3]; 10055 10056 u8 reserved_at_20[0x20]; 10057 }; 10058 10059 struct mlx5_ifc_pipg_reg_bits { 10060 u8 reserved_at_0[0x8]; 10061 u8 local_port[0x8]; 10062 u8 reserved_at_10[0x10]; 10063 10064 u8 dic[0x1]; 10065 u8 reserved_at_21[0x19]; 10066 u8 ipg[0x4]; 10067 u8 reserved_at_3e[0x2]; 10068 }; 10069 10070 struct mlx5_ifc_pifr_reg_bits { 10071 u8 reserved_at_0[0x8]; 10072 u8 local_port[0x8]; 10073 u8 reserved_at_10[0x10]; 10074 10075 u8 reserved_at_20[0xe0]; 10076 10077 u8 port_filter[8][0x20]; 10078 10079 u8 port_filter_update_en[8][0x20]; 10080 }; 10081 10082 struct mlx5_ifc_pfcc_reg_bits { 10083 u8 reserved_at_0[0x8]; 10084 u8 local_port[0x8]; 10085 u8 reserved_at_10[0xb]; 10086 u8 ppan_mask_n[0x1]; 10087 u8 minor_stall_mask[0x1]; 10088 u8 critical_stall_mask[0x1]; 10089 u8 reserved_at_1e[0x2]; 10090 10091 u8 ppan[0x4]; 10092 u8 reserved_at_24[0x4]; 10093 u8 prio_mask_tx[0x8]; 10094 u8 reserved_at_30[0x8]; 10095 u8 prio_mask_rx[0x8]; 10096 10097 u8 pptx[0x1]; 10098 u8 aptx[0x1]; 10099 u8 pptx_mask_n[0x1]; 10100 u8 reserved_at_43[0x5]; 10101 u8 pfctx[0x8]; 10102 u8 reserved_at_50[0x10]; 10103 10104 u8 pprx[0x1]; 10105 u8 aprx[0x1]; 10106 u8 pprx_mask_n[0x1]; 10107 u8 reserved_at_63[0x5]; 10108 u8 pfcrx[0x8]; 10109 u8 reserved_at_70[0x10]; 10110 10111 u8 device_stall_minor_watermark[0x10]; 10112 u8 device_stall_critical_watermark[0x10]; 10113 10114 u8 reserved_at_a0[0x60]; 10115 }; 10116 10117 struct mlx5_ifc_pelc_reg_bits { 10118 u8 op[0x4]; 10119 u8 reserved_at_4[0x4]; 10120 u8 local_port[0x8]; 10121 u8 reserved_at_10[0x10]; 10122 10123 u8 op_admin[0x8]; 10124 u8 op_capability[0x8]; 10125 u8 op_request[0x8]; 10126 u8 op_active[0x8]; 10127 10128 u8 admin[0x40]; 10129 10130 u8 capability[0x40]; 10131 10132 u8 request[0x40]; 10133 10134 u8 active[0x40]; 10135 10136 u8 reserved_at_140[0x80]; 10137 }; 10138 10139 struct mlx5_ifc_peir_reg_bits { 10140 u8 reserved_at_0[0x8]; 10141 u8 local_port[0x8]; 10142 u8 reserved_at_10[0x10]; 10143 10144 u8 reserved_at_20[0xc]; 10145 u8 error_count[0x4]; 10146 u8 reserved_at_30[0x10]; 10147 10148 u8 reserved_at_40[0xc]; 10149 u8 lane[0x4]; 10150 u8 reserved_at_50[0x8]; 10151 u8 error_type[0x8]; 10152 }; 10153 10154 struct mlx5_ifc_mpegc_reg_bits { 10155 u8 reserved_at_0[0x30]; 10156 u8 field_select[0x10]; 10157 10158 u8 tx_overflow_sense[0x1]; 10159 u8 mark_cqe[0x1]; 10160 u8 mark_cnp[0x1]; 10161 u8 reserved_at_43[0x1b]; 10162 u8 tx_lossy_overflow_oper[0x2]; 10163 10164 u8 reserved_at_60[0x100]; 10165 }; 10166 10167 struct mlx5_ifc_mpir_reg_bits { 10168 u8 sdm[0x1]; 10169 u8 reserved_at_1[0x1b]; 10170 u8 host_buses[0x4]; 10171 10172 u8 reserved_at_20[0x20]; 10173 10174 u8 local_port[0x8]; 10175 u8 reserved_at_28[0x18]; 10176 10177 u8 reserved_at_60[0x20]; 10178 }; 10179 10180 enum { 10181 MLX5_MTUTC_FREQ_ADJ_UNITS_PPB = 0x0, 10182 MLX5_MTUTC_FREQ_ADJ_UNITS_SCALED_PPM = 0x1, 10183 }; 10184 10185 enum { 10186 MLX5_MTUTC_OPERATION_SET_TIME_IMMEDIATE = 0x1, 10187 MLX5_MTUTC_OPERATION_ADJUST_TIME = 0x2, 10188 MLX5_MTUTC_OPERATION_ADJUST_FREQ_UTC = 0x3, 10189 }; 10190 10191 struct mlx5_ifc_mtutc_reg_bits { 10192 u8 reserved_at_0[0x5]; 10193 u8 freq_adj_units[0x3]; 10194 u8 reserved_at_8[0x3]; 10195 u8 log_max_freq_adjustment[0x5]; 10196 10197 u8 reserved_at_10[0xc]; 10198 u8 operation[0x4]; 10199 10200 u8 freq_adjustment[0x20]; 10201 10202 u8 reserved_at_40[0x40]; 10203 10204 u8 utc_sec[0x20]; 10205 10206 u8 reserved_at_a0[0x2]; 10207 u8 utc_nsec[0x1e]; 10208 10209 u8 time_adjustment[0x20]; 10210 }; 10211 10212 struct mlx5_ifc_pcam_enhanced_features_bits { 10213 u8 reserved_at_0[0x48]; 10214 u8 fec_100G_per_lane_in_pplm[0x1]; 10215 u8 reserved_at_49[0x1f]; 10216 u8 fec_50G_per_lane_in_pplm[0x1]; 10217 u8 reserved_at_69[0x4]; 10218 u8 rx_icrc_encapsulated_counter[0x1]; 10219 u8 reserved_at_6e[0x4]; 10220 u8 ptys_extended_ethernet[0x1]; 10221 u8 reserved_at_73[0x3]; 10222 u8 pfcc_mask[0x1]; 10223 u8 reserved_at_77[0x3]; 10224 u8 per_lane_error_counters[0x1]; 10225 u8 rx_buffer_fullness_counters[0x1]; 10226 u8 ptys_connector_type[0x1]; 10227 u8 reserved_at_7d[0x1]; 10228 u8 ppcnt_discard_group[0x1]; 10229 u8 ppcnt_statistical_group[0x1]; 10230 }; 10231 10232 struct mlx5_ifc_pcam_regs_5000_to_507f_bits { 10233 u8 port_access_reg_cap_mask_127_to_96[0x20]; 10234 u8 port_access_reg_cap_mask_95_to_64[0x20]; 10235 10236 u8 port_access_reg_cap_mask_63_to_36[0x1c]; 10237 u8 pplm[0x1]; 10238 u8 port_access_reg_cap_mask_34_to_32[0x3]; 10239 10240 u8 port_access_reg_cap_mask_31_to_13[0x13]; 10241 u8 pbmc[0x1]; 10242 u8 pptb[0x1]; 10243 u8 port_access_reg_cap_mask_10_to_09[0x2]; 10244 u8 ppcnt[0x1]; 10245 u8 port_access_reg_cap_mask_07_to_00[0x8]; 10246 }; 10247 10248 struct mlx5_ifc_pcam_reg_bits { 10249 u8 reserved_at_0[0x8]; 10250 u8 feature_group[0x8]; 10251 u8 reserved_at_10[0x8]; 10252 u8 access_reg_group[0x8]; 10253 10254 u8 reserved_at_20[0x20]; 10255 10256 union { 10257 struct mlx5_ifc_pcam_regs_5000_to_507f_bits regs_5000_to_507f; 10258 u8 reserved_at_0[0x80]; 10259 } port_access_reg_cap_mask; 10260 10261 u8 reserved_at_c0[0x80]; 10262 10263 union { 10264 struct mlx5_ifc_pcam_enhanced_features_bits enhanced_features; 10265 u8 reserved_at_0[0x80]; 10266 } feature_cap_mask; 10267 10268 u8 reserved_at_1c0[0xc0]; 10269 }; 10270 10271 struct mlx5_ifc_mcam_enhanced_features_bits { 10272 u8 reserved_at_0[0x50]; 10273 u8 mtutc_freq_adj_units[0x1]; 10274 u8 mtutc_time_adjustment_extended_range[0x1]; 10275 u8 reserved_at_52[0xb]; 10276 u8 mcia_32dwords[0x1]; 10277 u8 out_pulse_duration_ns[0x1]; 10278 u8 npps_period[0x1]; 10279 u8 reserved_at_60[0xa]; 10280 u8 reset_state[0x1]; 10281 u8 ptpcyc2realtime_modify[0x1]; 10282 u8 reserved_at_6c[0x2]; 10283 u8 pci_status_and_power[0x1]; 10284 u8 reserved_at_6f[0x5]; 10285 u8 mark_tx_action_cnp[0x1]; 10286 u8 mark_tx_action_cqe[0x1]; 10287 u8 dynamic_tx_overflow[0x1]; 10288 u8 reserved_at_77[0x4]; 10289 u8 pcie_outbound_stalled[0x1]; 10290 u8 tx_overflow_buffer_pkt[0x1]; 10291 u8 mtpps_enh_out_per_adj[0x1]; 10292 u8 mtpps_fs[0x1]; 10293 u8 pcie_performance_group[0x1]; 10294 }; 10295 10296 struct mlx5_ifc_mcam_access_reg_bits { 10297 u8 reserved_at_0[0x1c]; 10298 u8 mcda[0x1]; 10299 u8 mcc[0x1]; 10300 u8 mcqi[0x1]; 10301 u8 mcqs[0x1]; 10302 10303 u8 regs_95_to_90[0x6]; 10304 u8 mpir[0x1]; 10305 u8 regs_88_to_87[0x2]; 10306 u8 mpegc[0x1]; 10307 u8 mtutc[0x1]; 10308 u8 regs_84_to_68[0x11]; 10309 u8 tracer_registers[0x4]; 10310 10311 u8 regs_63_to_46[0x12]; 10312 u8 mrtc[0x1]; 10313 u8 regs_44_to_41[0x4]; 10314 u8 mfrl[0x1]; 10315 u8 regs_39_to_32[0x8]; 10316 10317 u8 regs_31_to_11[0x15]; 10318 u8 mtmp[0x1]; 10319 u8 regs_9_to_0[0xa]; 10320 }; 10321 10322 struct mlx5_ifc_mcam_access_reg_bits1 { 10323 u8 regs_127_to_96[0x20]; 10324 10325 u8 regs_95_to_64[0x20]; 10326 10327 u8 regs_63_to_32[0x20]; 10328 10329 u8 regs_31_to_0[0x20]; 10330 }; 10331 10332 struct mlx5_ifc_mcam_access_reg_bits2 { 10333 u8 regs_127_to_99[0x1d]; 10334 u8 mirc[0x1]; 10335 u8 regs_97_to_96[0x2]; 10336 10337 u8 regs_95_to_87[0x09]; 10338 u8 synce_registers[0x2]; 10339 u8 regs_84_to_64[0x15]; 10340 10341 u8 regs_63_to_32[0x20]; 10342 10343 u8 regs_31_to_0[0x20]; 10344 }; 10345 10346 struct mlx5_ifc_mcam_reg_bits { 10347 u8 reserved_at_0[0x8]; 10348 u8 feature_group[0x8]; 10349 u8 reserved_at_10[0x8]; 10350 u8 access_reg_group[0x8]; 10351 10352 u8 reserved_at_20[0x20]; 10353 10354 union { 10355 struct mlx5_ifc_mcam_access_reg_bits access_regs; 10356 struct mlx5_ifc_mcam_access_reg_bits1 access_regs1; 10357 struct mlx5_ifc_mcam_access_reg_bits2 access_regs2; 10358 u8 reserved_at_0[0x80]; 10359 } mng_access_reg_cap_mask; 10360 10361 u8 reserved_at_c0[0x80]; 10362 10363 union { 10364 struct mlx5_ifc_mcam_enhanced_features_bits enhanced_features; 10365 u8 reserved_at_0[0x80]; 10366 } mng_feature_cap_mask; 10367 10368 u8 reserved_at_1c0[0x80]; 10369 }; 10370 10371 struct mlx5_ifc_qcam_access_reg_cap_mask { 10372 u8 qcam_access_reg_cap_mask_127_to_20[0x6C]; 10373 u8 qpdpm[0x1]; 10374 u8 qcam_access_reg_cap_mask_18_to_4[0x0F]; 10375 u8 qdpm[0x1]; 10376 u8 qpts[0x1]; 10377 u8 qcap[0x1]; 10378 u8 qcam_access_reg_cap_mask_0[0x1]; 10379 }; 10380 10381 struct mlx5_ifc_qcam_qos_feature_cap_mask { 10382 u8 qcam_qos_feature_cap_mask_127_to_1[0x7F]; 10383 u8 qpts_trust_both[0x1]; 10384 }; 10385 10386 struct mlx5_ifc_qcam_reg_bits { 10387 u8 reserved_at_0[0x8]; 10388 u8 feature_group[0x8]; 10389 u8 reserved_at_10[0x8]; 10390 u8 access_reg_group[0x8]; 10391 u8 reserved_at_20[0x20]; 10392 10393 union { 10394 struct mlx5_ifc_qcam_access_reg_cap_mask reg_cap; 10395 u8 reserved_at_0[0x80]; 10396 } qos_access_reg_cap_mask; 10397 10398 u8 reserved_at_c0[0x80]; 10399 10400 union { 10401 struct mlx5_ifc_qcam_qos_feature_cap_mask feature_cap; 10402 u8 reserved_at_0[0x80]; 10403 } qos_feature_cap_mask; 10404 10405 u8 reserved_at_1c0[0x80]; 10406 }; 10407 10408 struct mlx5_ifc_core_dump_reg_bits { 10409 u8 reserved_at_0[0x18]; 10410 u8 core_dump_type[0x8]; 10411 10412 u8 reserved_at_20[0x30]; 10413 u8 vhca_id[0x10]; 10414 10415 u8 reserved_at_60[0x8]; 10416 u8 qpn[0x18]; 10417 u8 reserved_at_80[0x180]; 10418 }; 10419 10420 struct mlx5_ifc_pcap_reg_bits { 10421 u8 reserved_at_0[0x8]; 10422 u8 local_port[0x8]; 10423 u8 reserved_at_10[0x10]; 10424 10425 u8 port_capability_mask[4][0x20]; 10426 }; 10427 10428 struct mlx5_ifc_paos_reg_bits { 10429 u8 swid[0x8]; 10430 u8 local_port[0x8]; 10431 u8 reserved_at_10[0x4]; 10432 u8 admin_status[0x4]; 10433 u8 reserved_at_18[0x4]; 10434 u8 oper_status[0x4]; 10435 10436 u8 ase[0x1]; 10437 u8 ee[0x1]; 10438 u8 reserved_at_22[0x1c]; 10439 u8 e[0x2]; 10440 10441 u8 reserved_at_40[0x40]; 10442 }; 10443 10444 struct mlx5_ifc_pamp_reg_bits { 10445 u8 reserved_at_0[0x8]; 10446 u8 opamp_group[0x8]; 10447 u8 reserved_at_10[0xc]; 10448 u8 opamp_group_type[0x4]; 10449 10450 u8 start_index[0x10]; 10451 u8 reserved_at_30[0x4]; 10452 u8 num_of_indices[0xc]; 10453 10454 u8 index_data[18][0x10]; 10455 }; 10456 10457 struct mlx5_ifc_pcmr_reg_bits { 10458 u8 reserved_at_0[0x8]; 10459 u8 local_port[0x8]; 10460 u8 reserved_at_10[0x10]; 10461 10462 u8 entropy_force_cap[0x1]; 10463 u8 entropy_calc_cap[0x1]; 10464 u8 entropy_gre_calc_cap[0x1]; 10465 u8 reserved_at_23[0xf]; 10466 u8 rx_ts_over_crc_cap[0x1]; 10467 u8 reserved_at_33[0xb]; 10468 u8 fcs_cap[0x1]; 10469 u8 reserved_at_3f[0x1]; 10470 10471 u8 entropy_force[0x1]; 10472 u8 entropy_calc[0x1]; 10473 u8 entropy_gre_calc[0x1]; 10474 u8 reserved_at_43[0xf]; 10475 u8 rx_ts_over_crc[0x1]; 10476 u8 reserved_at_53[0xb]; 10477 u8 fcs_chk[0x1]; 10478 u8 reserved_at_5f[0x1]; 10479 }; 10480 10481 struct mlx5_ifc_lane_2_module_mapping_bits { 10482 u8 reserved_at_0[0x4]; 10483 u8 rx_lane[0x4]; 10484 u8 reserved_at_8[0x4]; 10485 u8 tx_lane[0x4]; 10486 u8 reserved_at_10[0x8]; 10487 u8 module[0x8]; 10488 }; 10489 10490 struct mlx5_ifc_bufferx_reg_bits { 10491 u8 reserved_at_0[0x6]; 10492 u8 lossy[0x1]; 10493 u8 epsb[0x1]; 10494 u8 reserved_at_8[0x8]; 10495 u8 size[0x10]; 10496 10497 u8 xoff_threshold[0x10]; 10498 u8 xon_threshold[0x10]; 10499 }; 10500 10501 struct mlx5_ifc_set_node_in_bits { 10502 u8 node_description[64][0x8]; 10503 }; 10504 10505 struct mlx5_ifc_register_power_settings_bits { 10506 u8 reserved_at_0[0x18]; 10507 u8 power_settings_level[0x8]; 10508 10509 u8 reserved_at_20[0x60]; 10510 }; 10511 10512 struct mlx5_ifc_register_host_endianness_bits { 10513 u8 he[0x1]; 10514 u8 reserved_at_1[0x1f]; 10515 10516 u8 reserved_at_20[0x60]; 10517 }; 10518 10519 struct mlx5_ifc_umr_pointer_desc_argument_bits { 10520 u8 reserved_at_0[0x20]; 10521 10522 u8 mkey[0x20]; 10523 10524 u8 addressh_63_32[0x20]; 10525 10526 u8 addressl_31_0[0x20]; 10527 }; 10528 10529 struct mlx5_ifc_ud_adrs_vector_bits { 10530 u8 dc_key[0x40]; 10531 10532 u8 ext[0x1]; 10533 u8 reserved_at_41[0x7]; 10534 u8 destination_qp_dct[0x18]; 10535 10536 u8 static_rate[0x4]; 10537 u8 sl_eth_prio[0x4]; 10538 u8 fl[0x1]; 10539 u8 mlid[0x7]; 10540 u8 rlid_udp_sport[0x10]; 10541 10542 u8 reserved_at_80[0x20]; 10543 10544 u8 rmac_47_16[0x20]; 10545 10546 u8 rmac_15_0[0x10]; 10547 u8 tclass[0x8]; 10548 u8 hop_limit[0x8]; 10549 10550 u8 reserved_at_e0[0x1]; 10551 u8 grh[0x1]; 10552 u8 reserved_at_e2[0x2]; 10553 u8 src_addr_index[0x8]; 10554 u8 flow_label[0x14]; 10555 10556 u8 rgid_rip[16][0x8]; 10557 }; 10558 10559 struct mlx5_ifc_pages_req_event_bits { 10560 u8 reserved_at_0[0x10]; 10561 u8 function_id[0x10]; 10562 10563 u8 num_pages[0x20]; 10564 10565 u8 reserved_at_40[0xa0]; 10566 }; 10567 10568 struct mlx5_ifc_eqe_bits { 10569 u8 reserved_at_0[0x8]; 10570 u8 event_type[0x8]; 10571 u8 reserved_at_10[0x8]; 10572 u8 event_sub_type[0x8]; 10573 10574 u8 reserved_at_20[0xe0]; 10575 10576 union mlx5_ifc_event_auto_bits event_data; 10577 10578 u8 reserved_at_1e0[0x10]; 10579 u8 signature[0x8]; 10580 u8 reserved_at_1f8[0x7]; 10581 u8 owner[0x1]; 10582 }; 10583 10584 enum { 10585 MLX5_CMD_QUEUE_ENTRY_TYPE_PCIE_CMD_IF_TRANSPORT = 0x7, 10586 }; 10587 10588 struct mlx5_ifc_cmd_queue_entry_bits { 10589 u8 type[0x8]; 10590 u8 reserved_at_8[0x18]; 10591 10592 u8 input_length[0x20]; 10593 10594 u8 input_mailbox_pointer_63_32[0x20]; 10595 10596 u8 input_mailbox_pointer_31_9[0x17]; 10597 u8 reserved_at_77[0x9]; 10598 10599 u8 command_input_inline_data[16][0x8]; 10600 10601 u8 command_output_inline_data[16][0x8]; 10602 10603 u8 output_mailbox_pointer_63_32[0x20]; 10604 10605 u8 output_mailbox_pointer_31_9[0x17]; 10606 u8 reserved_at_1b7[0x9]; 10607 10608 u8 output_length[0x20]; 10609 10610 u8 token[0x8]; 10611 u8 signature[0x8]; 10612 u8 reserved_at_1f0[0x8]; 10613 u8 status[0x7]; 10614 u8 ownership[0x1]; 10615 }; 10616 10617 struct mlx5_ifc_cmd_out_bits { 10618 u8 status[0x8]; 10619 u8 reserved_at_8[0x18]; 10620 10621 u8 syndrome[0x20]; 10622 10623 u8 command_output[0x20]; 10624 }; 10625 10626 struct mlx5_ifc_cmd_in_bits { 10627 u8 opcode[0x10]; 10628 u8 reserved_at_10[0x10]; 10629 10630 u8 reserved_at_20[0x10]; 10631 u8 op_mod[0x10]; 10632 10633 u8 command[][0x20]; 10634 }; 10635 10636 struct mlx5_ifc_cmd_if_box_bits { 10637 u8 mailbox_data[512][0x8]; 10638 10639 u8 reserved_at_1000[0x180]; 10640 10641 u8 next_pointer_63_32[0x20]; 10642 10643 u8 next_pointer_31_10[0x16]; 10644 u8 reserved_at_11b6[0xa]; 10645 10646 u8 block_number[0x20]; 10647 10648 u8 reserved_at_11e0[0x8]; 10649 u8 token[0x8]; 10650 u8 ctrl_signature[0x8]; 10651 u8 signature[0x8]; 10652 }; 10653 10654 struct mlx5_ifc_mtt_bits { 10655 u8 ptag_63_32[0x20]; 10656 10657 u8 ptag_31_8[0x18]; 10658 u8 reserved_at_38[0x6]; 10659 u8 wr_en[0x1]; 10660 u8 rd_en[0x1]; 10661 }; 10662 10663 struct mlx5_ifc_query_wol_rol_out_bits { 10664 u8 status[0x8]; 10665 u8 reserved_at_8[0x18]; 10666 10667 u8 syndrome[0x20]; 10668 10669 u8 reserved_at_40[0x10]; 10670 u8 rol_mode[0x8]; 10671 u8 wol_mode[0x8]; 10672 10673 u8 reserved_at_60[0x20]; 10674 }; 10675 10676 struct mlx5_ifc_query_wol_rol_in_bits { 10677 u8 opcode[0x10]; 10678 u8 reserved_at_10[0x10]; 10679 10680 u8 reserved_at_20[0x10]; 10681 u8 op_mod[0x10]; 10682 10683 u8 reserved_at_40[0x40]; 10684 }; 10685 10686 struct mlx5_ifc_set_wol_rol_out_bits { 10687 u8 status[0x8]; 10688 u8 reserved_at_8[0x18]; 10689 10690 u8 syndrome[0x20]; 10691 10692 u8 reserved_at_40[0x40]; 10693 }; 10694 10695 struct mlx5_ifc_set_wol_rol_in_bits { 10696 u8 opcode[0x10]; 10697 u8 reserved_at_10[0x10]; 10698 10699 u8 reserved_at_20[0x10]; 10700 u8 op_mod[0x10]; 10701 10702 u8 rol_mode_valid[0x1]; 10703 u8 wol_mode_valid[0x1]; 10704 u8 reserved_at_42[0xe]; 10705 u8 rol_mode[0x8]; 10706 u8 wol_mode[0x8]; 10707 10708 u8 reserved_at_60[0x20]; 10709 }; 10710 10711 enum { 10712 MLX5_INITIAL_SEG_NIC_INTERFACE_FULL_DRIVER = 0x0, 10713 MLX5_INITIAL_SEG_NIC_INTERFACE_DISABLED = 0x1, 10714 MLX5_INITIAL_SEG_NIC_INTERFACE_NO_DRAM_NIC = 0x2, 10715 MLX5_INITIAL_SEG_NIC_INTERFACE_SW_RESET = 0x7, 10716 }; 10717 10718 enum { 10719 MLX5_INITIAL_SEG_NIC_INTERFACE_SUPPORTED_FULL_DRIVER = 0x0, 10720 MLX5_INITIAL_SEG_NIC_INTERFACE_SUPPORTED_DISABLED = 0x1, 10721 MLX5_INITIAL_SEG_NIC_INTERFACE_SUPPORTED_NO_DRAM_NIC = 0x2, 10722 }; 10723 10724 enum { 10725 MLX5_INITIAL_SEG_HEALTH_SYNDROME_FW_INTERNAL_ERR = 0x1, 10726 MLX5_INITIAL_SEG_HEALTH_SYNDROME_DEAD_IRISC = 0x7, 10727 MLX5_INITIAL_SEG_HEALTH_SYNDROME_HW_FATAL_ERR = 0x8, 10728 MLX5_INITIAL_SEG_HEALTH_SYNDROME_FW_CRC_ERR = 0x9, 10729 MLX5_INITIAL_SEG_HEALTH_SYNDROME_ICM_FETCH_PCI_ERR = 0xa, 10730 MLX5_INITIAL_SEG_HEALTH_SYNDROME_ICM_PAGE_ERR = 0xb, 10731 MLX5_INITIAL_SEG_HEALTH_SYNDROME_ASYNCHRONOUS_EQ_BUF_OVERRUN = 0xc, 10732 MLX5_INITIAL_SEG_HEALTH_SYNDROME_EQ_IN_ERR = 0xd, 10733 MLX5_INITIAL_SEG_HEALTH_SYNDROME_EQ_INV = 0xe, 10734 MLX5_INITIAL_SEG_HEALTH_SYNDROME_FFSER_ERR = 0xf, 10735 MLX5_INITIAL_SEG_HEALTH_SYNDROME_HIGH_TEMP_ERR = 0x10, 10736 MLX5_INITIAL_SEG_HEALTH_SYNDROME_ICM_PCI_POISONED_ERR = 0x12, 10737 }; 10738 10739 struct mlx5_ifc_initial_seg_bits { 10740 u8 fw_rev_minor[0x10]; 10741 u8 fw_rev_major[0x10]; 10742 10743 u8 cmd_interface_rev[0x10]; 10744 u8 fw_rev_subminor[0x10]; 10745 10746 u8 reserved_at_40[0x40]; 10747 10748 u8 cmdq_phy_addr_63_32[0x20]; 10749 10750 u8 cmdq_phy_addr_31_12[0x14]; 10751 u8 reserved_at_b4[0x2]; 10752 u8 nic_interface[0x2]; 10753 u8 log_cmdq_size[0x4]; 10754 u8 log_cmdq_stride[0x4]; 10755 10756 u8 command_doorbell_vector[0x20]; 10757 10758 u8 reserved_at_e0[0xf00]; 10759 10760 u8 initializing[0x1]; 10761 u8 reserved_at_fe1[0x4]; 10762 u8 nic_interface_supported[0x3]; 10763 u8 embedded_cpu[0x1]; 10764 u8 reserved_at_fe9[0x17]; 10765 10766 struct mlx5_ifc_health_buffer_bits health_buffer; 10767 10768 u8 no_dram_nic_offset[0x20]; 10769 10770 u8 reserved_at_1220[0x6e40]; 10771 10772 u8 reserved_at_8060[0x1f]; 10773 u8 clear_int[0x1]; 10774 10775 u8 health_syndrome[0x8]; 10776 u8 health_counter[0x18]; 10777 10778 u8 reserved_at_80a0[0x17fc0]; 10779 }; 10780 10781 struct mlx5_ifc_mtpps_reg_bits { 10782 u8 reserved_at_0[0xc]; 10783 u8 cap_number_of_pps_pins[0x4]; 10784 u8 reserved_at_10[0x4]; 10785 u8 cap_max_num_of_pps_in_pins[0x4]; 10786 u8 reserved_at_18[0x4]; 10787 u8 cap_max_num_of_pps_out_pins[0x4]; 10788 10789 u8 reserved_at_20[0x13]; 10790 u8 cap_log_min_npps_period[0x5]; 10791 u8 reserved_at_38[0x3]; 10792 u8 cap_log_min_out_pulse_duration_ns[0x5]; 10793 10794 u8 reserved_at_40[0x4]; 10795 u8 cap_pin_3_mode[0x4]; 10796 u8 reserved_at_48[0x4]; 10797 u8 cap_pin_2_mode[0x4]; 10798 u8 reserved_at_50[0x4]; 10799 u8 cap_pin_1_mode[0x4]; 10800 u8 reserved_at_58[0x4]; 10801 u8 cap_pin_0_mode[0x4]; 10802 10803 u8 reserved_at_60[0x4]; 10804 u8 cap_pin_7_mode[0x4]; 10805 u8 reserved_at_68[0x4]; 10806 u8 cap_pin_6_mode[0x4]; 10807 u8 reserved_at_70[0x4]; 10808 u8 cap_pin_5_mode[0x4]; 10809 u8 reserved_at_78[0x4]; 10810 u8 cap_pin_4_mode[0x4]; 10811 10812 u8 field_select[0x20]; 10813 u8 reserved_at_a0[0x20]; 10814 10815 u8 npps_period[0x40]; 10816 10817 u8 enable[0x1]; 10818 u8 reserved_at_101[0xb]; 10819 u8 pattern[0x4]; 10820 u8 reserved_at_110[0x4]; 10821 u8 pin_mode[0x4]; 10822 u8 pin[0x8]; 10823 10824 u8 reserved_at_120[0x2]; 10825 u8 out_pulse_duration_ns[0x1e]; 10826 10827 u8 time_stamp[0x40]; 10828 10829 u8 out_pulse_duration[0x10]; 10830 u8 out_periodic_adjustment[0x10]; 10831 u8 enhanced_out_periodic_adjustment[0x20]; 10832 10833 u8 reserved_at_1c0[0x20]; 10834 }; 10835 10836 struct mlx5_ifc_mtppse_reg_bits { 10837 u8 reserved_at_0[0x18]; 10838 u8 pin[0x8]; 10839 u8 event_arm[0x1]; 10840 u8 reserved_at_21[0x1b]; 10841 u8 event_generation_mode[0x4]; 10842 u8 reserved_at_40[0x40]; 10843 }; 10844 10845 struct mlx5_ifc_mcqs_reg_bits { 10846 u8 last_index_flag[0x1]; 10847 u8 reserved_at_1[0x7]; 10848 u8 fw_device[0x8]; 10849 u8 component_index[0x10]; 10850 10851 u8 reserved_at_20[0x10]; 10852 u8 identifier[0x10]; 10853 10854 u8 reserved_at_40[0x17]; 10855 u8 component_status[0x5]; 10856 u8 component_update_state[0x4]; 10857 10858 u8 last_update_state_changer_type[0x4]; 10859 u8 last_update_state_changer_host_id[0x4]; 10860 u8 reserved_at_68[0x18]; 10861 }; 10862 10863 struct mlx5_ifc_mcqi_cap_bits { 10864 u8 supported_info_bitmask[0x20]; 10865 10866 u8 component_size[0x20]; 10867 10868 u8 max_component_size[0x20]; 10869 10870 u8 log_mcda_word_size[0x4]; 10871 u8 reserved_at_64[0xc]; 10872 u8 mcda_max_write_size[0x10]; 10873 10874 u8 rd_en[0x1]; 10875 u8 reserved_at_81[0x1]; 10876 u8 match_chip_id[0x1]; 10877 u8 match_psid[0x1]; 10878 u8 check_user_timestamp[0x1]; 10879 u8 match_base_guid_mac[0x1]; 10880 u8 reserved_at_86[0x1a]; 10881 }; 10882 10883 struct mlx5_ifc_mcqi_version_bits { 10884 u8 reserved_at_0[0x2]; 10885 u8 build_time_valid[0x1]; 10886 u8 user_defined_time_valid[0x1]; 10887 u8 reserved_at_4[0x14]; 10888 u8 version_string_length[0x8]; 10889 10890 u8 version[0x20]; 10891 10892 u8 build_time[0x40]; 10893 10894 u8 user_defined_time[0x40]; 10895 10896 u8 build_tool_version[0x20]; 10897 10898 u8 reserved_at_e0[0x20]; 10899 10900 u8 version_string[92][0x8]; 10901 }; 10902 10903 struct mlx5_ifc_mcqi_activation_method_bits { 10904 u8 pending_server_ac_power_cycle[0x1]; 10905 u8 pending_server_dc_power_cycle[0x1]; 10906 u8 pending_server_reboot[0x1]; 10907 u8 pending_fw_reset[0x1]; 10908 u8 auto_activate[0x1]; 10909 u8 all_hosts_sync[0x1]; 10910 u8 device_hw_reset[0x1]; 10911 u8 reserved_at_7[0x19]; 10912 }; 10913 10914 union mlx5_ifc_mcqi_reg_data_bits { 10915 struct mlx5_ifc_mcqi_cap_bits mcqi_caps; 10916 struct mlx5_ifc_mcqi_version_bits mcqi_version; 10917 struct mlx5_ifc_mcqi_activation_method_bits mcqi_activation_mathod; 10918 }; 10919 10920 struct mlx5_ifc_mcqi_reg_bits { 10921 u8 read_pending_component[0x1]; 10922 u8 reserved_at_1[0xf]; 10923 u8 component_index[0x10]; 10924 10925 u8 reserved_at_20[0x20]; 10926 10927 u8 reserved_at_40[0x1b]; 10928 u8 info_type[0x5]; 10929 10930 u8 info_size[0x20]; 10931 10932 u8 offset[0x20]; 10933 10934 u8 reserved_at_a0[0x10]; 10935 u8 data_size[0x10]; 10936 10937 union mlx5_ifc_mcqi_reg_data_bits data[]; 10938 }; 10939 10940 struct mlx5_ifc_mcc_reg_bits { 10941 u8 reserved_at_0[0x4]; 10942 u8 time_elapsed_since_last_cmd[0xc]; 10943 u8 reserved_at_10[0x8]; 10944 u8 instruction[0x8]; 10945 10946 u8 reserved_at_20[0x10]; 10947 u8 component_index[0x10]; 10948 10949 u8 reserved_at_40[0x8]; 10950 u8 update_handle[0x18]; 10951 10952 u8 handle_owner_type[0x4]; 10953 u8 handle_owner_host_id[0x4]; 10954 u8 reserved_at_68[0x1]; 10955 u8 control_progress[0x7]; 10956 u8 error_code[0x8]; 10957 u8 reserved_at_78[0x4]; 10958 u8 control_state[0x4]; 10959 10960 u8 component_size[0x20]; 10961 10962 u8 reserved_at_a0[0x60]; 10963 }; 10964 10965 struct mlx5_ifc_mcda_reg_bits { 10966 u8 reserved_at_0[0x8]; 10967 u8 update_handle[0x18]; 10968 10969 u8 offset[0x20]; 10970 10971 u8 reserved_at_40[0x10]; 10972 u8 size[0x10]; 10973 10974 u8 reserved_at_60[0x20]; 10975 10976 u8 data[][0x20]; 10977 }; 10978 10979 enum { 10980 MLX5_MFRL_REG_RESET_STATE_IDLE = 0, 10981 MLX5_MFRL_REG_RESET_STATE_IN_NEGOTIATION = 1, 10982 MLX5_MFRL_REG_RESET_STATE_RESET_IN_PROGRESS = 2, 10983 MLX5_MFRL_REG_RESET_STATE_NEG_TIMEOUT = 3, 10984 MLX5_MFRL_REG_RESET_STATE_NACK = 4, 10985 MLX5_MFRL_REG_RESET_STATE_UNLOAD_TIMEOUT = 5, 10986 }; 10987 10988 enum { 10989 MLX5_MFRL_REG_RESET_TYPE_FULL_CHIP = BIT(0), 10990 MLX5_MFRL_REG_RESET_TYPE_NET_PORT_ALIVE = BIT(1), 10991 }; 10992 10993 enum { 10994 MLX5_MFRL_REG_RESET_LEVEL0 = BIT(0), 10995 MLX5_MFRL_REG_RESET_LEVEL3 = BIT(3), 10996 MLX5_MFRL_REG_RESET_LEVEL6 = BIT(6), 10997 }; 10998 10999 struct mlx5_ifc_mfrl_reg_bits { 11000 u8 reserved_at_0[0x20]; 11001 11002 u8 reserved_at_20[0x2]; 11003 u8 pci_sync_for_fw_update_start[0x1]; 11004 u8 pci_sync_for_fw_update_resp[0x2]; 11005 u8 rst_type_sel[0x3]; 11006 u8 reserved_at_28[0x4]; 11007 u8 reset_state[0x4]; 11008 u8 reset_type[0x8]; 11009 u8 reset_level[0x8]; 11010 }; 11011 11012 struct mlx5_ifc_mirc_reg_bits { 11013 u8 reserved_at_0[0x18]; 11014 u8 status_code[0x8]; 11015 11016 u8 reserved_at_20[0x20]; 11017 }; 11018 11019 struct mlx5_ifc_pddr_monitor_opcode_bits { 11020 u8 reserved_at_0[0x10]; 11021 u8 monitor_opcode[0x10]; 11022 }; 11023 11024 union mlx5_ifc_pddr_troubleshooting_page_status_opcode_auto_bits { 11025 struct mlx5_ifc_pddr_monitor_opcode_bits pddr_monitor_opcode; 11026 u8 reserved_at_0[0x20]; 11027 }; 11028 11029 enum { 11030 /* Monitor opcodes */ 11031 MLX5_PDDR_REG_TRBLSH_GROUP_OPCODE_MONITOR = 0x0, 11032 }; 11033 11034 struct mlx5_ifc_pddr_troubleshooting_page_bits { 11035 u8 reserved_at_0[0x10]; 11036 u8 group_opcode[0x10]; 11037 11038 union mlx5_ifc_pddr_troubleshooting_page_status_opcode_auto_bits status_opcode; 11039 11040 u8 reserved_at_40[0x20]; 11041 11042 u8 status_message[59][0x20]; 11043 }; 11044 11045 union mlx5_ifc_pddr_reg_page_data_auto_bits { 11046 struct mlx5_ifc_pddr_troubleshooting_page_bits pddr_troubleshooting_page; 11047 u8 reserved_at_0[0x7c0]; 11048 }; 11049 11050 enum { 11051 MLX5_PDDR_REG_PAGE_SELECT_TROUBLESHOOTING_INFO_PAGE = 0x1, 11052 }; 11053 11054 struct mlx5_ifc_pddr_reg_bits { 11055 u8 reserved_at_0[0x8]; 11056 u8 local_port[0x8]; 11057 u8 pnat[0x2]; 11058 u8 reserved_at_12[0xe]; 11059 11060 u8 reserved_at_20[0x18]; 11061 u8 page_select[0x8]; 11062 11063 union mlx5_ifc_pddr_reg_page_data_auto_bits page_data; 11064 }; 11065 11066 struct mlx5_ifc_mrtc_reg_bits { 11067 u8 time_synced[0x1]; 11068 u8 reserved_at_1[0x1f]; 11069 11070 u8 reserved_at_20[0x20]; 11071 11072 u8 time_h[0x20]; 11073 11074 u8 time_l[0x20]; 11075 }; 11076 11077 struct mlx5_ifc_mtcap_reg_bits { 11078 u8 reserved_at_0[0x19]; 11079 u8 sensor_count[0x7]; 11080 11081 u8 reserved_at_20[0x20]; 11082 11083 u8 sensor_map[0x40]; 11084 }; 11085 11086 struct mlx5_ifc_mtmp_reg_bits { 11087 u8 reserved_at_0[0x14]; 11088 u8 sensor_index[0xc]; 11089 11090 u8 reserved_at_20[0x10]; 11091 u8 temperature[0x10]; 11092 11093 u8 mte[0x1]; 11094 u8 mtr[0x1]; 11095 u8 reserved_at_42[0xe]; 11096 u8 max_temperature[0x10]; 11097 11098 u8 tee[0x2]; 11099 u8 reserved_at_62[0xe]; 11100 u8 temp_threshold_hi[0x10]; 11101 11102 u8 reserved_at_80[0x10]; 11103 u8 temp_threshold_lo[0x10]; 11104 11105 u8 reserved_at_a0[0x20]; 11106 11107 u8 sensor_name_hi[0x20]; 11108 u8 sensor_name_lo[0x20]; 11109 }; 11110 11111 union mlx5_ifc_ports_control_registers_document_bits { 11112 struct mlx5_ifc_bufferx_reg_bits bufferx_reg; 11113 struct mlx5_ifc_eth_2819_cntrs_grp_data_layout_bits eth_2819_cntrs_grp_data_layout; 11114 struct mlx5_ifc_eth_2863_cntrs_grp_data_layout_bits eth_2863_cntrs_grp_data_layout; 11115 struct mlx5_ifc_eth_3635_cntrs_grp_data_layout_bits eth_3635_cntrs_grp_data_layout; 11116 struct mlx5_ifc_eth_802_3_cntrs_grp_data_layout_bits eth_802_3_cntrs_grp_data_layout; 11117 struct mlx5_ifc_eth_extended_cntrs_grp_data_layout_bits eth_extended_cntrs_grp_data_layout; 11118 struct mlx5_ifc_eth_per_prio_grp_data_layout_bits eth_per_prio_grp_data_layout; 11119 struct mlx5_ifc_eth_per_tc_prio_grp_data_layout_bits eth_per_tc_prio_grp_data_layout; 11120 struct mlx5_ifc_eth_per_tc_congest_prio_grp_data_layout_bits eth_per_tc_congest_prio_grp_data_layout; 11121 struct mlx5_ifc_lane_2_module_mapping_bits lane_2_module_mapping; 11122 struct mlx5_ifc_pamp_reg_bits pamp_reg; 11123 struct mlx5_ifc_paos_reg_bits paos_reg; 11124 struct mlx5_ifc_pcap_reg_bits pcap_reg; 11125 struct mlx5_ifc_pddr_monitor_opcode_bits pddr_monitor_opcode; 11126 struct mlx5_ifc_pddr_reg_bits pddr_reg; 11127 struct mlx5_ifc_pddr_troubleshooting_page_bits pddr_troubleshooting_page; 11128 struct mlx5_ifc_peir_reg_bits peir_reg; 11129 struct mlx5_ifc_pelc_reg_bits pelc_reg; 11130 struct mlx5_ifc_pfcc_reg_bits pfcc_reg; 11131 struct mlx5_ifc_ib_port_cntrs_grp_data_layout_bits ib_port_cntrs_grp_data_layout; 11132 struct mlx5_ifc_phys_layer_cntrs_bits phys_layer_cntrs; 11133 struct mlx5_ifc_pifr_reg_bits pifr_reg; 11134 struct mlx5_ifc_pipg_reg_bits pipg_reg; 11135 struct mlx5_ifc_plbf_reg_bits plbf_reg; 11136 struct mlx5_ifc_plib_reg_bits plib_reg; 11137 struct mlx5_ifc_plpc_reg_bits plpc_reg; 11138 struct mlx5_ifc_pmaos_reg_bits pmaos_reg; 11139 struct mlx5_ifc_pmlp_reg_bits pmlp_reg; 11140 struct mlx5_ifc_pmlpn_reg_bits pmlpn_reg; 11141 struct mlx5_ifc_pmpc_reg_bits pmpc_reg; 11142 struct mlx5_ifc_pmpe_reg_bits pmpe_reg; 11143 struct mlx5_ifc_pmpr_reg_bits pmpr_reg; 11144 struct mlx5_ifc_pmtu_reg_bits pmtu_reg; 11145 struct mlx5_ifc_ppad_reg_bits ppad_reg; 11146 struct mlx5_ifc_ppcnt_reg_bits ppcnt_reg; 11147 struct mlx5_ifc_mpein_reg_bits mpein_reg; 11148 struct mlx5_ifc_mpcnt_reg_bits mpcnt_reg; 11149 struct mlx5_ifc_pplm_reg_bits pplm_reg; 11150 struct mlx5_ifc_pplr_reg_bits pplr_reg; 11151 struct mlx5_ifc_ppsc_reg_bits ppsc_reg; 11152 struct mlx5_ifc_pqdr_reg_bits pqdr_reg; 11153 struct mlx5_ifc_pspa_reg_bits pspa_reg; 11154 struct mlx5_ifc_ptas_reg_bits ptas_reg; 11155 struct mlx5_ifc_ptys_reg_bits ptys_reg; 11156 struct mlx5_ifc_mlcr_reg_bits mlcr_reg; 11157 struct mlx5_ifc_pude_reg_bits pude_reg; 11158 struct mlx5_ifc_pvlc_reg_bits pvlc_reg; 11159 struct mlx5_ifc_slrg_reg_bits slrg_reg; 11160 struct mlx5_ifc_sltp_reg_bits sltp_reg; 11161 struct mlx5_ifc_mtpps_reg_bits mtpps_reg; 11162 struct mlx5_ifc_mtppse_reg_bits mtppse_reg; 11163 struct mlx5_ifc_fpga_access_reg_bits fpga_access_reg; 11164 struct mlx5_ifc_fpga_ctrl_bits fpga_ctrl_bits; 11165 struct mlx5_ifc_fpga_cap_bits fpga_cap_bits; 11166 struct mlx5_ifc_mcqi_reg_bits mcqi_reg; 11167 struct mlx5_ifc_mcc_reg_bits mcc_reg; 11168 struct mlx5_ifc_mcda_reg_bits mcda_reg; 11169 struct mlx5_ifc_mirc_reg_bits mirc_reg; 11170 struct mlx5_ifc_mfrl_reg_bits mfrl_reg; 11171 struct mlx5_ifc_mtutc_reg_bits mtutc_reg; 11172 struct mlx5_ifc_mrtc_reg_bits mrtc_reg; 11173 struct mlx5_ifc_mtcap_reg_bits mtcap_reg; 11174 struct mlx5_ifc_mtmp_reg_bits mtmp_reg; 11175 u8 reserved_at_0[0x60e0]; 11176 }; 11177 11178 union mlx5_ifc_debug_enhancements_document_bits { 11179 struct mlx5_ifc_health_buffer_bits health_buffer; 11180 u8 reserved_at_0[0x200]; 11181 }; 11182 11183 union mlx5_ifc_uplink_pci_interface_document_bits { 11184 struct mlx5_ifc_initial_seg_bits initial_seg; 11185 u8 reserved_at_0[0x20060]; 11186 }; 11187 11188 struct mlx5_ifc_set_flow_table_root_out_bits { 11189 u8 status[0x8]; 11190 u8 reserved_at_8[0x18]; 11191 11192 u8 syndrome[0x20]; 11193 11194 u8 reserved_at_40[0x40]; 11195 }; 11196 11197 struct mlx5_ifc_set_flow_table_root_in_bits { 11198 u8 opcode[0x10]; 11199 u8 reserved_at_10[0x10]; 11200 11201 u8 reserved_at_20[0x10]; 11202 u8 op_mod[0x10]; 11203 11204 u8 other_vport[0x1]; 11205 u8 reserved_at_41[0xf]; 11206 u8 vport_number[0x10]; 11207 11208 u8 reserved_at_60[0x20]; 11209 11210 u8 table_type[0x8]; 11211 u8 reserved_at_88[0x7]; 11212 u8 table_of_other_vport[0x1]; 11213 u8 table_vport_number[0x10]; 11214 11215 u8 reserved_at_a0[0x8]; 11216 u8 table_id[0x18]; 11217 11218 u8 reserved_at_c0[0x8]; 11219 u8 underlay_qpn[0x18]; 11220 u8 table_eswitch_owner_vhca_id_valid[0x1]; 11221 u8 reserved_at_e1[0xf]; 11222 u8 table_eswitch_owner_vhca_id[0x10]; 11223 u8 reserved_at_100[0x100]; 11224 }; 11225 11226 enum { 11227 MLX5_MODIFY_FLOW_TABLE_MISS_TABLE_ID = (1UL << 0), 11228 MLX5_MODIFY_FLOW_TABLE_LAG_NEXT_TABLE_ID = (1UL << 15), 11229 }; 11230 11231 struct mlx5_ifc_modify_flow_table_out_bits { 11232 u8 status[0x8]; 11233 u8 reserved_at_8[0x18]; 11234 11235 u8 syndrome[0x20]; 11236 11237 u8 reserved_at_40[0x40]; 11238 }; 11239 11240 struct mlx5_ifc_modify_flow_table_in_bits { 11241 u8 opcode[0x10]; 11242 u8 reserved_at_10[0x10]; 11243 11244 u8 reserved_at_20[0x10]; 11245 u8 op_mod[0x10]; 11246 11247 u8 other_vport[0x1]; 11248 u8 reserved_at_41[0xf]; 11249 u8 vport_number[0x10]; 11250 11251 u8 reserved_at_60[0x10]; 11252 u8 modify_field_select[0x10]; 11253 11254 u8 table_type[0x8]; 11255 u8 reserved_at_88[0x18]; 11256 11257 u8 reserved_at_a0[0x8]; 11258 u8 table_id[0x18]; 11259 11260 struct mlx5_ifc_flow_table_context_bits flow_table_context; 11261 }; 11262 11263 struct mlx5_ifc_ets_tcn_config_reg_bits { 11264 u8 g[0x1]; 11265 u8 b[0x1]; 11266 u8 r[0x1]; 11267 u8 reserved_at_3[0x9]; 11268 u8 group[0x4]; 11269 u8 reserved_at_10[0x9]; 11270 u8 bw_allocation[0x7]; 11271 11272 u8 reserved_at_20[0xc]; 11273 u8 max_bw_units[0x4]; 11274 u8 reserved_at_30[0x8]; 11275 u8 max_bw_value[0x8]; 11276 }; 11277 11278 struct mlx5_ifc_ets_global_config_reg_bits { 11279 u8 reserved_at_0[0x2]; 11280 u8 r[0x1]; 11281 u8 reserved_at_3[0x1d]; 11282 11283 u8 reserved_at_20[0xc]; 11284 u8 max_bw_units[0x4]; 11285 u8 reserved_at_30[0x8]; 11286 u8 max_bw_value[0x8]; 11287 }; 11288 11289 struct mlx5_ifc_qetc_reg_bits { 11290 u8 reserved_at_0[0x8]; 11291 u8 port_number[0x8]; 11292 u8 reserved_at_10[0x30]; 11293 11294 struct mlx5_ifc_ets_tcn_config_reg_bits tc_configuration[0x8]; 11295 struct mlx5_ifc_ets_global_config_reg_bits global_configuration; 11296 }; 11297 11298 struct mlx5_ifc_qpdpm_dscp_reg_bits { 11299 u8 e[0x1]; 11300 u8 reserved_at_01[0x0b]; 11301 u8 prio[0x04]; 11302 }; 11303 11304 struct mlx5_ifc_qpdpm_reg_bits { 11305 u8 reserved_at_0[0x8]; 11306 u8 local_port[0x8]; 11307 u8 reserved_at_10[0x10]; 11308 struct mlx5_ifc_qpdpm_dscp_reg_bits dscp[64]; 11309 }; 11310 11311 struct mlx5_ifc_qpts_reg_bits { 11312 u8 reserved_at_0[0x8]; 11313 u8 local_port[0x8]; 11314 u8 reserved_at_10[0x2d]; 11315 u8 trust_state[0x3]; 11316 }; 11317 11318 struct mlx5_ifc_pptb_reg_bits { 11319 u8 reserved_at_0[0x2]; 11320 u8 mm[0x2]; 11321 u8 reserved_at_4[0x4]; 11322 u8 local_port[0x8]; 11323 u8 reserved_at_10[0x6]; 11324 u8 cm[0x1]; 11325 u8 um[0x1]; 11326 u8 pm[0x8]; 11327 11328 u8 prio_x_buff[0x20]; 11329 11330 u8 pm_msb[0x8]; 11331 u8 reserved_at_48[0x10]; 11332 u8 ctrl_buff[0x4]; 11333 u8 untagged_buff[0x4]; 11334 }; 11335 11336 struct mlx5_ifc_sbcam_reg_bits { 11337 u8 reserved_at_0[0x8]; 11338 u8 feature_group[0x8]; 11339 u8 reserved_at_10[0x8]; 11340 u8 access_reg_group[0x8]; 11341 11342 u8 reserved_at_20[0x20]; 11343 11344 u8 sb_access_reg_cap_mask[4][0x20]; 11345 11346 u8 reserved_at_c0[0x80]; 11347 11348 u8 sb_feature_cap_mask[4][0x20]; 11349 11350 u8 reserved_at_1c0[0x40]; 11351 11352 u8 cap_total_buffer_size[0x20]; 11353 11354 u8 cap_cell_size[0x10]; 11355 u8 cap_max_pg_buffers[0x8]; 11356 u8 cap_num_pool_supported[0x8]; 11357 11358 u8 reserved_at_240[0x8]; 11359 u8 cap_sbsr_stat_size[0x8]; 11360 u8 cap_max_tclass_data[0x8]; 11361 u8 cap_max_cpu_ingress_tclass_sb[0x8]; 11362 }; 11363 11364 struct mlx5_ifc_pbmc_reg_bits { 11365 u8 reserved_at_0[0x8]; 11366 u8 local_port[0x8]; 11367 u8 reserved_at_10[0x10]; 11368 11369 u8 xoff_timer_value[0x10]; 11370 u8 xoff_refresh[0x10]; 11371 11372 u8 reserved_at_40[0x9]; 11373 u8 fullness_threshold[0x7]; 11374 u8 port_buffer_size[0x10]; 11375 11376 struct mlx5_ifc_bufferx_reg_bits buffer[10]; 11377 11378 u8 reserved_at_2e0[0x80]; 11379 }; 11380 11381 struct mlx5_ifc_sbpr_reg_bits { 11382 u8 desc[0x1]; 11383 u8 snap[0x1]; 11384 u8 reserved_at_2[0x4]; 11385 u8 dir[0x2]; 11386 u8 reserved_at_8[0x14]; 11387 u8 pool[0x4]; 11388 11389 u8 infi_size[0x1]; 11390 u8 reserved_at_21[0x7]; 11391 u8 size[0x18]; 11392 11393 u8 reserved_at_40[0x1c]; 11394 u8 mode[0x4]; 11395 11396 u8 reserved_at_60[0x8]; 11397 u8 buff_occupancy[0x18]; 11398 11399 u8 clr[0x1]; 11400 u8 reserved_at_81[0x7]; 11401 u8 max_buff_occupancy[0x18]; 11402 11403 u8 reserved_at_a0[0x8]; 11404 u8 ext_buff_occupancy[0x18]; 11405 }; 11406 11407 struct mlx5_ifc_sbcm_reg_bits { 11408 u8 desc[0x1]; 11409 u8 snap[0x1]; 11410 u8 reserved_at_2[0x6]; 11411 u8 local_port[0x8]; 11412 u8 pnat[0x2]; 11413 u8 pg_buff[0x6]; 11414 u8 reserved_at_18[0x6]; 11415 u8 dir[0x2]; 11416 11417 u8 reserved_at_20[0x1f]; 11418 u8 exc[0x1]; 11419 11420 u8 reserved_at_40[0x40]; 11421 11422 u8 reserved_at_80[0x8]; 11423 u8 buff_occupancy[0x18]; 11424 11425 u8 clr[0x1]; 11426 u8 reserved_at_a1[0x7]; 11427 u8 max_buff_occupancy[0x18]; 11428 11429 u8 reserved_at_c0[0x8]; 11430 u8 min_buff[0x18]; 11431 11432 u8 infi_max[0x1]; 11433 u8 reserved_at_e1[0x7]; 11434 u8 max_buff[0x18]; 11435 11436 u8 reserved_at_100[0x20]; 11437 11438 u8 reserved_at_120[0x1c]; 11439 u8 pool[0x4]; 11440 }; 11441 11442 struct mlx5_ifc_qtct_reg_bits { 11443 u8 reserved_at_0[0x8]; 11444 u8 port_number[0x8]; 11445 u8 reserved_at_10[0xd]; 11446 u8 prio[0x3]; 11447 11448 u8 reserved_at_20[0x1d]; 11449 u8 tclass[0x3]; 11450 }; 11451 11452 struct mlx5_ifc_mcia_reg_bits { 11453 u8 l[0x1]; 11454 u8 reserved_at_1[0x7]; 11455 u8 module[0x8]; 11456 u8 reserved_at_10[0x8]; 11457 u8 status[0x8]; 11458 11459 u8 i2c_device_address[0x8]; 11460 u8 page_number[0x8]; 11461 u8 device_address[0x10]; 11462 11463 u8 reserved_at_40[0x10]; 11464 u8 size[0x10]; 11465 11466 u8 reserved_at_60[0x20]; 11467 11468 u8 dword_0[0x20]; 11469 u8 dword_1[0x20]; 11470 u8 dword_2[0x20]; 11471 u8 dword_3[0x20]; 11472 u8 dword_4[0x20]; 11473 u8 dword_5[0x20]; 11474 u8 dword_6[0x20]; 11475 u8 dword_7[0x20]; 11476 u8 dword_8[0x20]; 11477 u8 dword_9[0x20]; 11478 u8 dword_10[0x20]; 11479 u8 dword_11[0x20]; 11480 }; 11481 11482 struct mlx5_ifc_dcbx_param_bits { 11483 u8 dcbx_cee_cap[0x1]; 11484 u8 dcbx_ieee_cap[0x1]; 11485 u8 dcbx_standby_cap[0x1]; 11486 u8 reserved_at_3[0x5]; 11487 u8 port_number[0x8]; 11488 u8 reserved_at_10[0xa]; 11489 u8 max_application_table_size[6]; 11490 u8 reserved_at_20[0x15]; 11491 u8 version_oper[0x3]; 11492 u8 reserved_at_38[5]; 11493 u8 version_admin[0x3]; 11494 u8 willing_admin[0x1]; 11495 u8 reserved_at_41[0x3]; 11496 u8 pfc_cap_oper[0x4]; 11497 u8 reserved_at_48[0x4]; 11498 u8 pfc_cap_admin[0x4]; 11499 u8 reserved_at_50[0x4]; 11500 u8 num_of_tc_oper[0x4]; 11501 u8 reserved_at_58[0x4]; 11502 u8 num_of_tc_admin[0x4]; 11503 u8 remote_willing[0x1]; 11504 u8 reserved_at_61[3]; 11505 u8 remote_pfc_cap[4]; 11506 u8 reserved_at_68[0x14]; 11507 u8 remote_num_of_tc[0x4]; 11508 u8 reserved_at_80[0x18]; 11509 u8 error[0x8]; 11510 u8 reserved_at_a0[0x160]; 11511 }; 11512 11513 enum { 11514 MLX5_LAG_PORT_SELECT_MODE_QUEUE_AFFINITY = 0, 11515 MLX5_LAG_PORT_SELECT_MODE_PORT_SELECT_FT = 1, 11516 MLX5_LAG_PORT_SELECT_MODE_PORT_SELECT_MPESW = 2, 11517 }; 11518 11519 struct mlx5_ifc_lagc_bits { 11520 u8 fdb_selection_mode[0x1]; 11521 u8 reserved_at_1[0x14]; 11522 u8 port_select_mode[0x3]; 11523 u8 reserved_at_18[0x5]; 11524 u8 lag_state[0x3]; 11525 11526 u8 reserved_at_20[0xc]; 11527 u8 active_port[0x4]; 11528 u8 reserved_at_30[0x4]; 11529 u8 tx_remap_affinity_2[0x4]; 11530 u8 reserved_at_38[0x4]; 11531 u8 tx_remap_affinity_1[0x4]; 11532 }; 11533 11534 struct mlx5_ifc_create_lag_out_bits { 11535 u8 status[0x8]; 11536 u8 reserved_at_8[0x18]; 11537 11538 u8 syndrome[0x20]; 11539 11540 u8 reserved_at_40[0x40]; 11541 }; 11542 11543 struct mlx5_ifc_create_lag_in_bits { 11544 u8 opcode[0x10]; 11545 u8 reserved_at_10[0x10]; 11546 11547 u8 reserved_at_20[0x10]; 11548 u8 op_mod[0x10]; 11549 11550 struct mlx5_ifc_lagc_bits ctx; 11551 }; 11552 11553 struct mlx5_ifc_modify_lag_out_bits { 11554 u8 status[0x8]; 11555 u8 reserved_at_8[0x18]; 11556 11557 u8 syndrome[0x20]; 11558 11559 u8 reserved_at_40[0x40]; 11560 }; 11561 11562 struct mlx5_ifc_modify_lag_in_bits { 11563 u8 opcode[0x10]; 11564 u8 reserved_at_10[0x10]; 11565 11566 u8 reserved_at_20[0x10]; 11567 u8 op_mod[0x10]; 11568 11569 u8 reserved_at_40[0x20]; 11570 u8 field_select[0x20]; 11571 11572 struct mlx5_ifc_lagc_bits ctx; 11573 }; 11574 11575 struct mlx5_ifc_query_lag_out_bits { 11576 u8 status[0x8]; 11577 u8 reserved_at_8[0x18]; 11578 11579 u8 syndrome[0x20]; 11580 11581 struct mlx5_ifc_lagc_bits ctx; 11582 }; 11583 11584 struct mlx5_ifc_query_lag_in_bits { 11585 u8 opcode[0x10]; 11586 u8 reserved_at_10[0x10]; 11587 11588 u8 reserved_at_20[0x10]; 11589 u8 op_mod[0x10]; 11590 11591 u8 reserved_at_40[0x40]; 11592 }; 11593 11594 struct mlx5_ifc_destroy_lag_out_bits { 11595 u8 status[0x8]; 11596 u8 reserved_at_8[0x18]; 11597 11598 u8 syndrome[0x20]; 11599 11600 u8 reserved_at_40[0x40]; 11601 }; 11602 11603 struct mlx5_ifc_destroy_lag_in_bits { 11604 u8 opcode[0x10]; 11605 u8 reserved_at_10[0x10]; 11606 11607 u8 reserved_at_20[0x10]; 11608 u8 op_mod[0x10]; 11609 11610 u8 reserved_at_40[0x40]; 11611 }; 11612 11613 struct mlx5_ifc_create_vport_lag_out_bits { 11614 u8 status[0x8]; 11615 u8 reserved_at_8[0x18]; 11616 11617 u8 syndrome[0x20]; 11618 11619 u8 reserved_at_40[0x40]; 11620 }; 11621 11622 struct mlx5_ifc_create_vport_lag_in_bits { 11623 u8 opcode[0x10]; 11624 u8 reserved_at_10[0x10]; 11625 11626 u8 reserved_at_20[0x10]; 11627 u8 op_mod[0x10]; 11628 11629 u8 reserved_at_40[0x40]; 11630 }; 11631 11632 struct mlx5_ifc_destroy_vport_lag_out_bits { 11633 u8 status[0x8]; 11634 u8 reserved_at_8[0x18]; 11635 11636 u8 syndrome[0x20]; 11637 11638 u8 reserved_at_40[0x40]; 11639 }; 11640 11641 struct mlx5_ifc_destroy_vport_lag_in_bits { 11642 u8 opcode[0x10]; 11643 u8 reserved_at_10[0x10]; 11644 11645 u8 reserved_at_20[0x10]; 11646 u8 op_mod[0x10]; 11647 11648 u8 reserved_at_40[0x40]; 11649 }; 11650 11651 enum { 11652 MLX5_MODIFY_MEMIC_OP_MOD_ALLOC, 11653 MLX5_MODIFY_MEMIC_OP_MOD_DEALLOC, 11654 }; 11655 11656 struct mlx5_ifc_modify_memic_in_bits { 11657 u8 opcode[0x10]; 11658 u8 uid[0x10]; 11659 11660 u8 reserved_at_20[0x10]; 11661 u8 op_mod[0x10]; 11662 11663 u8 reserved_at_40[0x20]; 11664 11665 u8 reserved_at_60[0x18]; 11666 u8 memic_operation_type[0x8]; 11667 11668 u8 memic_start_addr[0x40]; 11669 11670 u8 reserved_at_c0[0x140]; 11671 }; 11672 11673 struct mlx5_ifc_modify_memic_out_bits { 11674 u8 status[0x8]; 11675 u8 reserved_at_8[0x18]; 11676 11677 u8 syndrome[0x20]; 11678 11679 u8 reserved_at_40[0x40]; 11680 11681 u8 memic_operation_addr[0x40]; 11682 11683 u8 reserved_at_c0[0x140]; 11684 }; 11685 11686 struct mlx5_ifc_alloc_memic_in_bits { 11687 u8 opcode[0x10]; 11688 u8 reserved_at_10[0x10]; 11689 11690 u8 reserved_at_20[0x10]; 11691 u8 op_mod[0x10]; 11692 11693 u8 reserved_at_30[0x20]; 11694 11695 u8 reserved_at_40[0x18]; 11696 u8 log_memic_addr_alignment[0x8]; 11697 11698 u8 range_start_addr[0x40]; 11699 11700 u8 range_size[0x20]; 11701 11702 u8 memic_size[0x20]; 11703 }; 11704 11705 struct mlx5_ifc_alloc_memic_out_bits { 11706 u8 status[0x8]; 11707 u8 reserved_at_8[0x18]; 11708 11709 u8 syndrome[0x20]; 11710 11711 u8 memic_start_addr[0x40]; 11712 }; 11713 11714 struct mlx5_ifc_dealloc_memic_in_bits { 11715 u8 opcode[0x10]; 11716 u8 reserved_at_10[0x10]; 11717 11718 u8 reserved_at_20[0x10]; 11719 u8 op_mod[0x10]; 11720 11721 u8 reserved_at_40[0x40]; 11722 11723 u8 memic_start_addr[0x40]; 11724 11725 u8 memic_size[0x20]; 11726 11727 u8 reserved_at_e0[0x20]; 11728 }; 11729 11730 struct mlx5_ifc_dealloc_memic_out_bits { 11731 u8 status[0x8]; 11732 u8 reserved_at_8[0x18]; 11733 11734 u8 syndrome[0x20]; 11735 11736 u8 reserved_at_40[0x40]; 11737 }; 11738 11739 struct mlx5_ifc_umem_bits { 11740 u8 reserved_at_0[0x80]; 11741 11742 u8 ats[0x1]; 11743 u8 reserved_at_81[0x1a]; 11744 u8 log_page_size[0x5]; 11745 11746 u8 page_offset[0x20]; 11747 11748 u8 num_of_mtt[0x40]; 11749 11750 struct mlx5_ifc_mtt_bits mtt[]; 11751 }; 11752 11753 struct mlx5_ifc_uctx_bits { 11754 u8 cap[0x20]; 11755 11756 u8 reserved_at_20[0x160]; 11757 }; 11758 11759 struct mlx5_ifc_sw_icm_bits { 11760 u8 modify_field_select[0x40]; 11761 11762 u8 reserved_at_40[0x18]; 11763 u8 log_sw_icm_size[0x8]; 11764 11765 u8 reserved_at_60[0x20]; 11766 11767 u8 sw_icm_start_addr[0x40]; 11768 11769 u8 reserved_at_c0[0x140]; 11770 }; 11771 11772 struct mlx5_ifc_geneve_tlv_option_bits { 11773 u8 modify_field_select[0x40]; 11774 11775 u8 reserved_at_40[0x18]; 11776 u8 geneve_option_fte_index[0x8]; 11777 11778 u8 option_class[0x10]; 11779 u8 option_type[0x8]; 11780 u8 reserved_at_78[0x3]; 11781 u8 option_data_length[0x5]; 11782 11783 u8 reserved_at_80[0x180]; 11784 }; 11785 11786 struct mlx5_ifc_create_umem_in_bits { 11787 u8 opcode[0x10]; 11788 u8 uid[0x10]; 11789 11790 u8 reserved_at_20[0x10]; 11791 u8 op_mod[0x10]; 11792 11793 u8 reserved_at_40[0x40]; 11794 11795 struct mlx5_ifc_umem_bits umem; 11796 }; 11797 11798 struct mlx5_ifc_create_umem_out_bits { 11799 u8 status[0x8]; 11800 u8 reserved_at_8[0x18]; 11801 11802 u8 syndrome[0x20]; 11803 11804 u8 reserved_at_40[0x8]; 11805 u8 umem_id[0x18]; 11806 11807 u8 reserved_at_60[0x20]; 11808 }; 11809 11810 struct mlx5_ifc_destroy_umem_in_bits { 11811 u8 opcode[0x10]; 11812 u8 uid[0x10]; 11813 11814 u8 reserved_at_20[0x10]; 11815 u8 op_mod[0x10]; 11816 11817 u8 reserved_at_40[0x8]; 11818 u8 umem_id[0x18]; 11819 11820 u8 reserved_at_60[0x20]; 11821 }; 11822 11823 struct mlx5_ifc_destroy_umem_out_bits { 11824 u8 status[0x8]; 11825 u8 reserved_at_8[0x18]; 11826 11827 u8 syndrome[0x20]; 11828 11829 u8 reserved_at_40[0x40]; 11830 }; 11831 11832 struct mlx5_ifc_create_uctx_in_bits { 11833 u8 opcode[0x10]; 11834 u8 reserved_at_10[0x10]; 11835 11836 u8 reserved_at_20[0x10]; 11837 u8 op_mod[0x10]; 11838 11839 u8 reserved_at_40[0x40]; 11840 11841 struct mlx5_ifc_uctx_bits uctx; 11842 }; 11843 11844 struct mlx5_ifc_create_uctx_out_bits { 11845 u8 status[0x8]; 11846 u8 reserved_at_8[0x18]; 11847 11848 u8 syndrome[0x20]; 11849 11850 u8 reserved_at_40[0x10]; 11851 u8 uid[0x10]; 11852 11853 u8 reserved_at_60[0x20]; 11854 }; 11855 11856 struct mlx5_ifc_destroy_uctx_in_bits { 11857 u8 opcode[0x10]; 11858 u8 reserved_at_10[0x10]; 11859 11860 u8 reserved_at_20[0x10]; 11861 u8 op_mod[0x10]; 11862 11863 u8 reserved_at_40[0x10]; 11864 u8 uid[0x10]; 11865 11866 u8 reserved_at_60[0x20]; 11867 }; 11868 11869 struct mlx5_ifc_destroy_uctx_out_bits { 11870 u8 status[0x8]; 11871 u8 reserved_at_8[0x18]; 11872 11873 u8 syndrome[0x20]; 11874 11875 u8 reserved_at_40[0x40]; 11876 }; 11877 11878 struct mlx5_ifc_create_sw_icm_in_bits { 11879 struct mlx5_ifc_general_obj_in_cmd_hdr_bits hdr; 11880 struct mlx5_ifc_sw_icm_bits sw_icm; 11881 }; 11882 11883 struct mlx5_ifc_create_geneve_tlv_option_in_bits { 11884 struct mlx5_ifc_general_obj_in_cmd_hdr_bits hdr; 11885 struct mlx5_ifc_geneve_tlv_option_bits geneve_tlv_opt; 11886 }; 11887 11888 struct mlx5_ifc_mtrc_string_db_param_bits { 11889 u8 string_db_base_address[0x20]; 11890 11891 u8 reserved_at_20[0x8]; 11892 u8 string_db_size[0x18]; 11893 }; 11894 11895 struct mlx5_ifc_mtrc_cap_bits { 11896 u8 trace_owner[0x1]; 11897 u8 trace_to_memory[0x1]; 11898 u8 reserved_at_2[0x4]; 11899 u8 trc_ver[0x2]; 11900 u8 reserved_at_8[0x14]; 11901 u8 num_string_db[0x4]; 11902 11903 u8 first_string_trace[0x8]; 11904 u8 num_string_trace[0x8]; 11905 u8 reserved_at_30[0x28]; 11906 11907 u8 log_max_trace_buffer_size[0x8]; 11908 11909 u8 reserved_at_60[0x20]; 11910 11911 struct mlx5_ifc_mtrc_string_db_param_bits string_db_param[8]; 11912 11913 u8 reserved_at_280[0x180]; 11914 }; 11915 11916 struct mlx5_ifc_mtrc_conf_bits { 11917 u8 reserved_at_0[0x1c]; 11918 u8 trace_mode[0x4]; 11919 u8 reserved_at_20[0x18]; 11920 u8 log_trace_buffer_size[0x8]; 11921 u8 trace_mkey[0x20]; 11922 u8 reserved_at_60[0x3a0]; 11923 }; 11924 11925 struct mlx5_ifc_mtrc_stdb_bits { 11926 u8 string_db_index[0x4]; 11927 u8 reserved_at_4[0x4]; 11928 u8 read_size[0x18]; 11929 u8 start_offset[0x20]; 11930 u8 string_db_data[]; 11931 }; 11932 11933 struct mlx5_ifc_mtrc_ctrl_bits { 11934 u8 trace_status[0x2]; 11935 u8 reserved_at_2[0x2]; 11936 u8 arm_event[0x1]; 11937 u8 reserved_at_5[0xb]; 11938 u8 modify_field_select[0x10]; 11939 u8 reserved_at_20[0x2b]; 11940 u8 current_timestamp52_32[0x15]; 11941 u8 current_timestamp31_0[0x20]; 11942 u8 reserved_at_80[0x180]; 11943 }; 11944 11945 struct mlx5_ifc_host_params_context_bits { 11946 u8 host_number[0x8]; 11947 u8 reserved_at_8[0x7]; 11948 u8 host_pf_disabled[0x1]; 11949 u8 host_num_of_vfs[0x10]; 11950 11951 u8 host_total_vfs[0x10]; 11952 u8 host_pci_bus[0x10]; 11953 11954 u8 reserved_at_40[0x10]; 11955 u8 host_pci_device[0x10]; 11956 11957 u8 reserved_at_60[0x10]; 11958 u8 host_pci_function[0x10]; 11959 11960 u8 reserved_at_80[0x180]; 11961 }; 11962 11963 struct mlx5_ifc_query_esw_functions_in_bits { 11964 u8 opcode[0x10]; 11965 u8 reserved_at_10[0x10]; 11966 11967 u8 reserved_at_20[0x10]; 11968 u8 op_mod[0x10]; 11969 11970 u8 reserved_at_40[0x40]; 11971 }; 11972 11973 struct mlx5_ifc_query_esw_functions_out_bits { 11974 u8 status[0x8]; 11975 u8 reserved_at_8[0x18]; 11976 11977 u8 syndrome[0x20]; 11978 11979 u8 reserved_at_40[0x40]; 11980 11981 struct mlx5_ifc_host_params_context_bits host_params_context; 11982 11983 u8 reserved_at_280[0x180]; 11984 u8 host_sf_enable[][0x40]; 11985 }; 11986 11987 struct mlx5_ifc_sf_partition_bits { 11988 u8 reserved_at_0[0x10]; 11989 u8 log_num_sf[0x8]; 11990 u8 log_sf_bar_size[0x8]; 11991 }; 11992 11993 struct mlx5_ifc_query_sf_partitions_out_bits { 11994 u8 status[0x8]; 11995 u8 reserved_at_8[0x18]; 11996 11997 u8 syndrome[0x20]; 11998 11999 u8 reserved_at_40[0x18]; 12000 u8 num_sf_partitions[0x8]; 12001 12002 u8 reserved_at_60[0x20]; 12003 12004 struct mlx5_ifc_sf_partition_bits sf_partition[]; 12005 }; 12006 12007 struct mlx5_ifc_query_sf_partitions_in_bits { 12008 u8 opcode[0x10]; 12009 u8 reserved_at_10[0x10]; 12010 12011 u8 reserved_at_20[0x10]; 12012 u8 op_mod[0x10]; 12013 12014 u8 reserved_at_40[0x40]; 12015 }; 12016 12017 struct mlx5_ifc_dealloc_sf_out_bits { 12018 u8 status[0x8]; 12019 u8 reserved_at_8[0x18]; 12020 12021 u8 syndrome[0x20]; 12022 12023 u8 reserved_at_40[0x40]; 12024 }; 12025 12026 struct mlx5_ifc_dealloc_sf_in_bits { 12027 u8 opcode[0x10]; 12028 u8 reserved_at_10[0x10]; 12029 12030 u8 reserved_at_20[0x10]; 12031 u8 op_mod[0x10]; 12032 12033 u8 reserved_at_40[0x10]; 12034 u8 function_id[0x10]; 12035 12036 u8 reserved_at_60[0x20]; 12037 }; 12038 12039 struct mlx5_ifc_alloc_sf_out_bits { 12040 u8 status[0x8]; 12041 u8 reserved_at_8[0x18]; 12042 12043 u8 syndrome[0x20]; 12044 12045 u8 reserved_at_40[0x40]; 12046 }; 12047 12048 struct mlx5_ifc_alloc_sf_in_bits { 12049 u8 opcode[0x10]; 12050 u8 reserved_at_10[0x10]; 12051 12052 u8 reserved_at_20[0x10]; 12053 u8 op_mod[0x10]; 12054 12055 u8 reserved_at_40[0x10]; 12056 u8 function_id[0x10]; 12057 12058 u8 reserved_at_60[0x20]; 12059 }; 12060 12061 struct mlx5_ifc_affiliated_event_header_bits { 12062 u8 reserved_at_0[0x10]; 12063 u8 obj_type[0x10]; 12064 12065 u8 obj_id[0x20]; 12066 }; 12067 12068 enum { 12069 MLX5_HCA_CAP_GENERAL_OBJECT_TYPES_ENCRYPTION_KEY = BIT_ULL(0xc), 12070 MLX5_HCA_CAP_GENERAL_OBJECT_TYPES_IPSEC = BIT_ULL(0x13), 12071 MLX5_HCA_CAP_GENERAL_OBJECT_TYPES_SAMPLER = BIT_ULL(0x20), 12072 MLX5_HCA_CAP_GENERAL_OBJECT_TYPES_FLOW_METER_ASO = BIT_ULL(0x24), 12073 }; 12074 12075 enum { 12076 MLX5_GENERAL_OBJECT_TYPES_ENCRYPTION_KEY = 0xc, 12077 MLX5_GENERAL_OBJECT_TYPES_IPSEC = 0x13, 12078 MLX5_GENERAL_OBJECT_TYPES_SAMPLER = 0x20, 12079 MLX5_GENERAL_OBJECT_TYPES_FLOW_METER_ASO = 0x24, 12080 MLX5_GENERAL_OBJECT_TYPES_MACSEC = 0x27, 12081 MLX5_GENERAL_OBJECT_TYPES_INT_KEK = 0x47, 12082 MLX5_GENERAL_OBJECT_TYPES_FLOW_TABLE_ALIAS = 0xff15, 12083 }; 12084 12085 enum { 12086 MLX5_IPSEC_OBJECT_ICV_LEN_16B, 12087 }; 12088 12089 enum { 12090 MLX5_IPSEC_ASO_REG_C_0_1 = 0x0, 12091 MLX5_IPSEC_ASO_REG_C_2_3 = 0x1, 12092 MLX5_IPSEC_ASO_REG_C_4_5 = 0x2, 12093 MLX5_IPSEC_ASO_REG_C_6_7 = 0x3, 12094 }; 12095 12096 enum { 12097 MLX5_IPSEC_ASO_MODE = 0x0, 12098 MLX5_IPSEC_ASO_REPLAY_PROTECTION = 0x1, 12099 MLX5_IPSEC_ASO_INC_SN = 0x2, 12100 }; 12101 12102 enum { 12103 MLX5_IPSEC_ASO_REPLAY_WIN_32BIT = 0x0, 12104 MLX5_IPSEC_ASO_REPLAY_WIN_64BIT = 0x1, 12105 MLX5_IPSEC_ASO_REPLAY_WIN_128BIT = 0x2, 12106 MLX5_IPSEC_ASO_REPLAY_WIN_256BIT = 0x3, 12107 }; 12108 12109 struct mlx5_ifc_ipsec_aso_bits { 12110 u8 valid[0x1]; 12111 u8 reserved_at_201[0x1]; 12112 u8 mode[0x2]; 12113 u8 window_sz[0x2]; 12114 u8 soft_lft_arm[0x1]; 12115 u8 hard_lft_arm[0x1]; 12116 u8 remove_flow_enable[0x1]; 12117 u8 esn_event_arm[0x1]; 12118 u8 reserved_at_20a[0x16]; 12119 12120 u8 remove_flow_pkt_cnt[0x20]; 12121 12122 u8 remove_flow_soft_lft[0x20]; 12123 12124 u8 reserved_at_260[0x80]; 12125 12126 u8 mode_parameter[0x20]; 12127 12128 u8 replay_protection_window[0x100]; 12129 }; 12130 12131 struct mlx5_ifc_ipsec_obj_bits { 12132 u8 modify_field_select[0x40]; 12133 u8 full_offload[0x1]; 12134 u8 reserved_at_41[0x1]; 12135 u8 esn_en[0x1]; 12136 u8 esn_overlap[0x1]; 12137 u8 reserved_at_44[0x2]; 12138 u8 icv_length[0x2]; 12139 u8 reserved_at_48[0x4]; 12140 u8 aso_return_reg[0x4]; 12141 u8 reserved_at_50[0x10]; 12142 12143 u8 esn_msb[0x20]; 12144 12145 u8 reserved_at_80[0x8]; 12146 u8 dekn[0x18]; 12147 12148 u8 salt[0x20]; 12149 12150 u8 implicit_iv[0x40]; 12151 12152 u8 reserved_at_100[0x8]; 12153 u8 ipsec_aso_access_pd[0x18]; 12154 u8 reserved_at_120[0xe0]; 12155 12156 struct mlx5_ifc_ipsec_aso_bits ipsec_aso; 12157 }; 12158 12159 struct mlx5_ifc_create_ipsec_obj_in_bits { 12160 struct mlx5_ifc_general_obj_in_cmd_hdr_bits general_obj_in_cmd_hdr; 12161 struct mlx5_ifc_ipsec_obj_bits ipsec_object; 12162 }; 12163 12164 enum { 12165 MLX5_MODIFY_IPSEC_BITMASK_ESN_OVERLAP = BIT(0), 12166 MLX5_MODIFY_IPSEC_BITMASK_ESN_MSB = BIT(1), 12167 }; 12168 12169 struct mlx5_ifc_query_ipsec_obj_out_bits { 12170 struct mlx5_ifc_general_obj_out_cmd_hdr_bits general_obj_out_cmd_hdr; 12171 struct mlx5_ifc_ipsec_obj_bits ipsec_object; 12172 }; 12173 12174 struct mlx5_ifc_modify_ipsec_obj_in_bits { 12175 struct mlx5_ifc_general_obj_in_cmd_hdr_bits general_obj_in_cmd_hdr; 12176 struct mlx5_ifc_ipsec_obj_bits ipsec_object; 12177 }; 12178 12179 enum { 12180 MLX5_MACSEC_ASO_REPLAY_PROTECTION = 0x1, 12181 }; 12182 12183 enum { 12184 MLX5_MACSEC_ASO_REPLAY_WIN_32BIT = 0x0, 12185 MLX5_MACSEC_ASO_REPLAY_WIN_64BIT = 0x1, 12186 MLX5_MACSEC_ASO_REPLAY_WIN_128BIT = 0x2, 12187 MLX5_MACSEC_ASO_REPLAY_WIN_256BIT = 0x3, 12188 }; 12189 12190 #define MLX5_MACSEC_ASO_INC_SN 0x2 12191 #define MLX5_MACSEC_ASO_REG_C_4_5 0x2 12192 12193 struct mlx5_ifc_macsec_aso_bits { 12194 u8 valid[0x1]; 12195 u8 reserved_at_1[0x1]; 12196 u8 mode[0x2]; 12197 u8 window_size[0x2]; 12198 u8 soft_lifetime_arm[0x1]; 12199 u8 hard_lifetime_arm[0x1]; 12200 u8 remove_flow_enable[0x1]; 12201 u8 epn_event_arm[0x1]; 12202 u8 reserved_at_a[0x16]; 12203 12204 u8 remove_flow_packet_count[0x20]; 12205 12206 u8 remove_flow_soft_lifetime[0x20]; 12207 12208 u8 reserved_at_60[0x80]; 12209 12210 u8 mode_parameter[0x20]; 12211 12212 u8 replay_protection_window[8][0x20]; 12213 }; 12214 12215 struct mlx5_ifc_macsec_offload_obj_bits { 12216 u8 modify_field_select[0x40]; 12217 12218 u8 confidentiality_en[0x1]; 12219 u8 reserved_at_41[0x1]; 12220 u8 epn_en[0x1]; 12221 u8 epn_overlap[0x1]; 12222 u8 reserved_at_44[0x2]; 12223 u8 confidentiality_offset[0x2]; 12224 u8 reserved_at_48[0x4]; 12225 u8 aso_return_reg[0x4]; 12226 u8 reserved_at_50[0x10]; 12227 12228 u8 epn_msb[0x20]; 12229 12230 u8 reserved_at_80[0x8]; 12231 u8 dekn[0x18]; 12232 12233 u8 reserved_at_a0[0x20]; 12234 12235 u8 sci[0x40]; 12236 12237 u8 reserved_at_100[0x8]; 12238 u8 macsec_aso_access_pd[0x18]; 12239 12240 u8 reserved_at_120[0x60]; 12241 12242 u8 salt[3][0x20]; 12243 12244 u8 reserved_at_1e0[0x20]; 12245 12246 struct mlx5_ifc_macsec_aso_bits macsec_aso; 12247 }; 12248 12249 struct mlx5_ifc_create_macsec_obj_in_bits { 12250 struct mlx5_ifc_general_obj_in_cmd_hdr_bits general_obj_in_cmd_hdr; 12251 struct mlx5_ifc_macsec_offload_obj_bits macsec_object; 12252 }; 12253 12254 struct mlx5_ifc_modify_macsec_obj_in_bits { 12255 struct mlx5_ifc_general_obj_in_cmd_hdr_bits general_obj_in_cmd_hdr; 12256 struct mlx5_ifc_macsec_offload_obj_bits macsec_object; 12257 }; 12258 12259 enum { 12260 MLX5_MODIFY_MACSEC_BITMASK_EPN_OVERLAP = BIT(0), 12261 MLX5_MODIFY_MACSEC_BITMASK_EPN_MSB = BIT(1), 12262 }; 12263 12264 struct mlx5_ifc_query_macsec_obj_out_bits { 12265 struct mlx5_ifc_general_obj_out_cmd_hdr_bits general_obj_out_cmd_hdr; 12266 struct mlx5_ifc_macsec_offload_obj_bits macsec_object; 12267 }; 12268 12269 struct mlx5_ifc_wrapped_dek_bits { 12270 u8 gcm_iv[0x60]; 12271 12272 u8 reserved_at_60[0x20]; 12273 12274 u8 const0[0x1]; 12275 u8 key_size[0x1]; 12276 u8 reserved_at_82[0x2]; 12277 u8 key2_invalid[0x1]; 12278 u8 reserved_at_85[0x3]; 12279 u8 pd[0x18]; 12280 12281 u8 key_purpose[0x5]; 12282 u8 reserved_at_a5[0x13]; 12283 u8 kek_id[0x8]; 12284 12285 u8 reserved_at_c0[0x40]; 12286 12287 u8 key1[0x8][0x20]; 12288 12289 u8 key2[0x8][0x20]; 12290 12291 u8 reserved_at_300[0x40]; 12292 12293 u8 const1[0x1]; 12294 u8 reserved_at_341[0x1f]; 12295 12296 u8 reserved_at_360[0x20]; 12297 12298 u8 auth_tag[0x80]; 12299 }; 12300 12301 struct mlx5_ifc_encryption_key_obj_bits { 12302 u8 modify_field_select[0x40]; 12303 12304 u8 state[0x8]; 12305 u8 sw_wrapped[0x1]; 12306 u8 reserved_at_49[0xb]; 12307 u8 key_size[0x4]; 12308 u8 reserved_at_58[0x4]; 12309 u8 key_purpose[0x4]; 12310 12311 u8 reserved_at_60[0x8]; 12312 u8 pd[0x18]; 12313 12314 u8 reserved_at_80[0x100]; 12315 12316 u8 opaque[0x40]; 12317 12318 u8 reserved_at_1c0[0x40]; 12319 12320 u8 key[8][0x80]; 12321 12322 u8 sw_wrapped_dek[8][0x80]; 12323 12324 u8 reserved_at_a00[0x600]; 12325 }; 12326 12327 struct mlx5_ifc_create_encryption_key_in_bits { 12328 struct mlx5_ifc_general_obj_in_cmd_hdr_bits general_obj_in_cmd_hdr; 12329 struct mlx5_ifc_encryption_key_obj_bits encryption_key_object; 12330 }; 12331 12332 struct mlx5_ifc_modify_encryption_key_in_bits { 12333 struct mlx5_ifc_general_obj_in_cmd_hdr_bits general_obj_in_cmd_hdr; 12334 struct mlx5_ifc_encryption_key_obj_bits encryption_key_object; 12335 }; 12336 12337 enum { 12338 MLX5_FLOW_METER_MODE_BYTES_IP_LENGTH = 0x0, 12339 MLX5_FLOW_METER_MODE_BYTES_CALC_WITH_L2 = 0x1, 12340 MLX5_FLOW_METER_MODE_BYTES_CALC_WITH_L2_IPG = 0x2, 12341 MLX5_FLOW_METER_MODE_NUM_PACKETS = 0x3, 12342 }; 12343 12344 struct mlx5_ifc_flow_meter_parameters_bits { 12345 u8 valid[0x1]; 12346 u8 bucket_overflow[0x1]; 12347 u8 start_color[0x2]; 12348 u8 both_buckets_on_green[0x1]; 12349 u8 reserved_at_5[0x1]; 12350 u8 meter_mode[0x2]; 12351 u8 reserved_at_8[0x18]; 12352 12353 u8 reserved_at_20[0x20]; 12354 12355 u8 reserved_at_40[0x3]; 12356 u8 cbs_exponent[0x5]; 12357 u8 cbs_mantissa[0x8]; 12358 u8 reserved_at_50[0x3]; 12359 u8 cir_exponent[0x5]; 12360 u8 cir_mantissa[0x8]; 12361 12362 u8 reserved_at_60[0x20]; 12363 12364 u8 reserved_at_80[0x3]; 12365 u8 ebs_exponent[0x5]; 12366 u8 ebs_mantissa[0x8]; 12367 u8 reserved_at_90[0x3]; 12368 u8 eir_exponent[0x5]; 12369 u8 eir_mantissa[0x8]; 12370 12371 u8 reserved_at_a0[0x60]; 12372 }; 12373 12374 struct mlx5_ifc_flow_meter_aso_obj_bits { 12375 u8 modify_field_select[0x40]; 12376 12377 u8 reserved_at_40[0x40]; 12378 12379 u8 reserved_at_80[0x8]; 12380 u8 meter_aso_access_pd[0x18]; 12381 12382 u8 reserved_at_a0[0x160]; 12383 12384 struct mlx5_ifc_flow_meter_parameters_bits flow_meter_parameters[2]; 12385 }; 12386 12387 struct mlx5_ifc_create_flow_meter_aso_obj_in_bits { 12388 struct mlx5_ifc_general_obj_in_cmd_hdr_bits hdr; 12389 struct mlx5_ifc_flow_meter_aso_obj_bits flow_meter_aso_obj; 12390 }; 12391 12392 struct mlx5_ifc_int_kek_obj_bits { 12393 u8 modify_field_select[0x40]; 12394 12395 u8 state[0x8]; 12396 u8 auto_gen[0x1]; 12397 u8 reserved_at_49[0xb]; 12398 u8 key_size[0x4]; 12399 u8 reserved_at_58[0x8]; 12400 12401 u8 reserved_at_60[0x8]; 12402 u8 pd[0x18]; 12403 12404 u8 reserved_at_80[0x180]; 12405 u8 key[8][0x80]; 12406 12407 u8 reserved_at_600[0x200]; 12408 }; 12409 12410 struct mlx5_ifc_create_int_kek_obj_in_bits { 12411 struct mlx5_ifc_general_obj_in_cmd_hdr_bits general_obj_in_cmd_hdr; 12412 struct mlx5_ifc_int_kek_obj_bits int_kek_object; 12413 }; 12414 12415 struct mlx5_ifc_create_int_kek_obj_out_bits { 12416 struct mlx5_ifc_general_obj_out_cmd_hdr_bits general_obj_out_cmd_hdr; 12417 struct mlx5_ifc_int_kek_obj_bits int_kek_object; 12418 }; 12419 12420 struct mlx5_ifc_sampler_obj_bits { 12421 u8 modify_field_select[0x40]; 12422 12423 u8 table_type[0x8]; 12424 u8 level[0x8]; 12425 u8 reserved_at_50[0xf]; 12426 u8 ignore_flow_level[0x1]; 12427 12428 u8 sample_ratio[0x20]; 12429 12430 u8 reserved_at_80[0x8]; 12431 u8 sample_table_id[0x18]; 12432 12433 u8 reserved_at_a0[0x8]; 12434 u8 default_table_id[0x18]; 12435 12436 u8 sw_steering_icm_address_rx[0x40]; 12437 u8 sw_steering_icm_address_tx[0x40]; 12438 12439 u8 reserved_at_140[0xa0]; 12440 }; 12441 12442 struct mlx5_ifc_create_sampler_obj_in_bits { 12443 struct mlx5_ifc_general_obj_in_cmd_hdr_bits general_obj_in_cmd_hdr; 12444 struct mlx5_ifc_sampler_obj_bits sampler_object; 12445 }; 12446 12447 struct mlx5_ifc_query_sampler_obj_out_bits { 12448 struct mlx5_ifc_general_obj_out_cmd_hdr_bits general_obj_out_cmd_hdr; 12449 struct mlx5_ifc_sampler_obj_bits sampler_object; 12450 }; 12451 12452 enum { 12453 MLX5_GENERAL_OBJECT_TYPE_ENCRYPTION_KEY_KEY_SIZE_128 = 0x0, 12454 MLX5_GENERAL_OBJECT_TYPE_ENCRYPTION_KEY_KEY_SIZE_256 = 0x1, 12455 }; 12456 12457 enum { 12458 MLX5_GENERAL_OBJECT_TYPE_ENCRYPTION_KEY_PURPOSE_TLS = 0x1, 12459 MLX5_GENERAL_OBJECT_TYPE_ENCRYPTION_KEY_PURPOSE_IPSEC = 0x2, 12460 MLX5_GENERAL_OBJECT_TYPE_ENCRYPTION_KEY_PURPOSE_MACSEC = 0x4, 12461 }; 12462 12463 struct mlx5_ifc_tls_static_params_bits { 12464 u8 const_2[0x2]; 12465 u8 tls_version[0x4]; 12466 u8 const_1[0x2]; 12467 u8 reserved_at_8[0x14]; 12468 u8 encryption_standard[0x4]; 12469 12470 u8 reserved_at_20[0x20]; 12471 12472 u8 initial_record_number[0x40]; 12473 12474 u8 resync_tcp_sn[0x20]; 12475 12476 u8 gcm_iv[0x20]; 12477 12478 u8 implicit_iv[0x40]; 12479 12480 u8 reserved_at_100[0x8]; 12481 u8 dek_index[0x18]; 12482 12483 u8 reserved_at_120[0xe0]; 12484 }; 12485 12486 struct mlx5_ifc_tls_progress_params_bits { 12487 u8 next_record_tcp_sn[0x20]; 12488 12489 u8 hw_resync_tcp_sn[0x20]; 12490 12491 u8 record_tracker_state[0x2]; 12492 u8 auth_state[0x2]; 12493 u8 reserved_at_44[0x4]; 12494 u8 hw_offset_record_number[0x18]; 12495 }; 12496 12497 enum { 12498 MLX5_MTT_PERM_READ = 1 << 0, 12499 MLX5_MTT_PERM_WRITE = 1 << 1, 12500 MLX5_MTT_PERM_RW = MLX5_MTT_PERM_READ | MLX5_MTT_PERM_WRITE, 12501 }; 12502 12503 enum { 12504 MLX5_SUSPEND_VHCA_IN_OP_MOD_SUSPEND_INITIATOR = 0x0, 12505 MLX5_SUSPEND_VHCA_IN_OP_MOD_SUSPEND_RESPONDER = 0x1, 12506 }; 12507 12508 struct mlx5_ifc_suspend_vhca_in_bits { 12509 u8 opcode[0x10]; 12510 u8 uid[0x10]; 12511 12512 u8 reserved_at_20[0x10]; 12513 u8 op_mod[0x10]; 12514 12515 u8 reserved_at_40[0x10]; 12516 u8 vhca_id[0x10]; 12517 12518 u8 reserved_at_60[0x20]; 12519 }; 12520 12521 struct mlx5_ifc_suspend_vhca_out_bits { 12522 u8 status[0x8]; 12523 u8 reserved_at_8[0x18]; 12524 12525 u8 syndrome[0x20]; 12526 12527 u8 reserved_at_40[0x40]; 12528 }; 12529 12530 enum { 12531 MLX5_RESUME_VHCA_IN_OP_MOD_RESUME_RESPONDER = 0x0, 12532 MLX5_RESUME_VHCA_IN_OP_MOD_RESUME_INITIATOR = 0x1, 12533 }; 12534 12535 struct mlx5_ifc_resume_vhca_in_bits { 12536 u8 opcode[0x10]; 12537 u8 uid[0x10]; 12538 12539 u8 reserved_at_20[0x10]; 12540 u8 op_mod[0x10]; 12541 12542 u8 reserved_at_40[0x10]; 12543 u8 vhca_id[0x10]; 12544 12545 u8 reserved_at_60[0x20]; 12546 }; 12547 12548 struct mlx5_ifc_resume_vhca_out_bits { 12549 u8 status[0x8]; 12550 u8 reserved_at_8[0x18]; 12551 12552 u8 syndrome[0x20]; 12553 12554 u8 reserved_at_40[0x40]; 12555 }; 12556 12557 struct mlx5_ifc_query_vhca_migration_state_in_bits { 12558 u8 opcode[0x10]; 12559 u8 uid[0x10]; 12560 12561 u8 reserved_at_20[0x10]; 12562 u8 op_mod[0x10]; 12563 12564 u8 incremental[0x1]; 12565 u8 chunk[0x1]; 12566 u8 reserved_at_42[0xe]; 12567 u8 vhca_id[0x10]; 12568 12569 u8 reserved_at_60[0x20]; 12570 }; 12571 12572 struct mlx5_ifc_query_vhca_migration_state_out_bits { 12573 u8 status[0x8]; 12574 u8 reserved_at_8[0x18]; 12575 12576 u8 syndrome[0x20]; 12577 12578 u8 reserved_at_40[0x40]; 12579 12580 u8 required_umem_size[0x20]; 12581 12582 u8 reserved_at_a0[0x20]; 12583 12584 u8 remaining_total_size[0x40]; 12585 12586 u8 reserved_at_100[0x100]; 12587 }; 12588 12589 struct mlx5_ifc_save_vhca_state_in_bits { 12590 u8 opcode[0x10]; 12591 u8 uid[0x10]; 12592 12593 u8 reserved_at_20[0x10]; 12594 u8 op_mod[0x10]; 12595 12596 u8 incremental[0x1]; 12597 u8 set_track[0x1]; 12598 u8 reserved_at_42[0xe]; 12599 u8 vhca_id[0x10]; 12600 12601 u8 reserved_at_60[0x20]; 12602 12603 u8 va[0x40]; 12604 12605 u8 mkey[0x20]; 12606 12607 u8 size[0x20]; 12608 }; 12609 12610 struct mlx5_ifc_save_vhca_state_out_bits { 12611 u8 status[0x8]; 12612 u8 reserved_at_8[0x18]; 12613 12614 u8 syndrome[0x20]; 12615 12616 u8 actual_image_size[0x20]; 12617 12618 u8 next_required_umem_size[0x20]; 12619 }; 12620 12621 struct mlx5_ifc_load_vhca_state_in_bits { 12622 u8 opcode[0x10]; 12623 u8 uid[0x10]; 12624 12625 u8 reserved_at_20[0x10]; 12626 u8 op_mod[0x10]; 12627 12628 u8 reserved_at_40[0x10]; 12629 u8 vhca_id[0x10]; 12630 12631 u8 reserved_at_60[0x20]; 12632 12633 u8 va[0x40]; 12634 12635 u8 mkey[0x20]; 12636 12637 u8 size[0x20]; 12638 }; 12639 12640 struct mlx5_ifc_load_vhca_state_out_bits { 12641 u8 status[0x8]; 12642 u8 reserved_at_8[0x18]; 12643 12644 u8 syndrome[0x20]; 12645 12646 u8 reserved_at_40[0x40]; 12647 }; 12648 12649 struct mlx5_ifc_adv_virtualization_cap_bits { 12650 u8 reserved_at_0[0x3]; 12651 u8 pg_track_log_max_num[0x5]; 12652 u8 pg_track_max_num_range[0x8]; 12653 u8 pg_track_log_min_addr_space[0x8]; 12654 u8 pg_track_log_max_addr_space[0x8]; 12655 12656 u8 reserved_at_20[0x3]; 12657 u8 pg_track_log_min_msg_size[0x5]; 12658 u8 reserved_at_28[0x3]; 12659 u8 pg_track_log_max_msg_size[0x5]; 12660 u8 reserved_at_30[0x3]; 12661 u8 pg_track_log_min_page_size[0x5]; 12662 u8 reserved_at_38[0x3]; 12663 u8 pg_track_log_max_page_size[0x5]; 12664 12665 u8 reserved_at_40[0x7c0]; 12666 }; 12667 12668 struct mlx5_ifc_page_track_report_entry_bits { 12669 u8 dirty_address_high[0x20]; 12670 12671 u8 dirty_address_low[0x20]; 12672 }; 12673 12674 enum { 12675 MLX5_PAGE_TRACK_STATE_TRACKING, 12676 MLX5_PAGE_TRACK_STATE_REPORTING, 12677 MLX5_PAGE_TRACK_STATE_ERROR, 12678 }; 12679 12680 struct mlx5_ifc_page_track_range_bits { 12681 u8 start_address[0x40]; 12682 12683 u8 length[0x40]; 12684 }; 12685 12686 struct mlx5_ifc_page_track_bits { 12687 u8 modify_field_select[0x40]; 12688 12689 u8 reserved_at_40[0x10]; 12690 u8 vhca_id[0x10]; 12691 12692 u8 reserved_at_60[0x20]; 12693 12694 u8 state[0x4]; 12695 u8 track_type[0x4]; 12696 u8 log_addr_space_size[0x8]; 12697 u8 reserved_at_90[0x3]; 12698 u8 log_page_size[0x5]; 12699 u8 reserved_at_98[0x3]; 12700 u8 log_msg_size[0x5]; 12701 12702 u8 reserved_at_a0[0x8]; 12703 u8 reporting_qpn[0x18]; 12704 12705 u8 reserved_at_c0[0x18]; 12706 u8 num_ranges[0x8]; 12707 12708 u8 reserved_at_e0[0x20]; 12709 12710 u8 range_start_address[0x40]; 12711 12712 u8 length[0x40]; 12713 12714 struct mlx5_ifc_page_track_range_bits track_range[0]; 12715 }; 12716 12717 struct mlx5_ifc_create_page_track_obj_in_bits { 12718 struct mlx5_ifc_general_obj_in_cmd_hdr_bits general_obj_in_cmd_hdr; 12719 struct mlx5_ifc_page_track_bits obj_context; 12720 }; 12721 12722 struct mlx5_ifc_modify_page_track_obj_in_bits { 12723 struct mlx5_ifc_general_obj_in_cmd_hdr_bits general_obj_in_cmd_hdr; 12724 struct mlx5_ifc_page_track_bits obj_context; 12725 }; 12726 12727 struct mlx5_ifc_query_page_track_obj_out_bits { 12728 struct mlx5_ifc_general_obj_out_cmd_hdr_bits general_obj_out_cmd_hdr; 12729 struct mlx5_ifc_page_track_bits obj_context; 12730 }; 12731 12732 struct mlx5_ifc_msecq_reg_bits { 12733 u8 reserved_at_0[0x20]; 12734 12735 u8 reserved_at_20[0x12]; 12736 u8 network_option[0x2]; 12737 u8 local_ssm_code[0x4]; 12738 u8 local_enhanced_ssm_code[0x8]; 12739 12740 u8 local_clock_identity[0x40]; 12741 12742 u8 reserved_at_80[0x180]; 12743 }; 12744 12745 enum { 12746 MLX5_MSEES_FIELD_SELECT_ENABLE = BIT(0), 12747 MLX5_MSEES_FIELD_SELECT_ADMIN_STATUS = BIT(1), 12748 MLX5_MSEES_FIELD_SELECT_ADMIN_FREQ_MEASURE = BIT(2), 12749 }; 12750 12751 enum mlx5_msees_admin_status { 12752 MLX5_MSEES_ADMIN_STATUS_FREE_RUNNING = 0x0, 12753 MLX5_MSEES_ADMIN_STATUS_TRACK = 0x1, 12754 }; 12755 12756 enum mlx5_msees_oper_status { 12757 MLX5_MSEES_OPER_STATUS_FREE_RUNNING = 0x0, 12758 MLX5_MSEES_OPER_STATUS_SELF_TRACK = 0x1, 12759 MLX5_MSEES_OPER_STATUS_OTHER_TRACK = 0x2, 12760 MLX5_MSEES_OPER_STATUS_HOLDOVER = 0x3, 12761 MLX5_MSEES_OPER_STATUS_FAIL_HOLDOVER = 0x4, 12762 MLX5_MSEES_OPER_STATUS_FAIL_FREE_RUNNING = 0x5, 12763 }; 12764 12765 enum mlx5_msees_failure_reason { 12766 MLX5_MSEES_FAILURE_REASON_UNDEFINED_ERROR = 0x0, 12767 MLX5_MSEES_FAILURE_REASON_PORT_DOWN = 0x1, 12768 MLX5_MSEES_FAILURE_REASON_TOO_HIGH_FREQUENCY_DIFF = 0x2, 12769 MLX5_MSEES_FAILURE_REASON_NET_SYNCHRONIZER_DEVICE_ERROR = 0x3, 12770 MLX5_MSEES_FAILURE_REASON_LACK_OF_RESOURCES = 0x4, 12771 }; 12772 12773 struct mlx5_ifc_msees_reg_bits { 12774 u8 reserved_at_0[0x8]; 12775 u8 local_port[0x8]; 12776 u8 pnat[0x2]; 12777 u8 lp_msb[0x2]; 12778 u8 reserved_at_14[0xc]; 12779 12780 u8 field_select[0x20]; 12781 12782 u8 admin_status[0x4]; 12783 u8 oper_status[0x4]; 12784 u8 ho_acq[0x1]; 12785 u8 reserved_at_49[0xc]; 12786 u8 admin_freq_measure[0x1]; 12787 u8 oper_freq_measure[0x1]; 12788 u8 failure_reason[0x9]; 12789 12790 u8 frequency_diff[0x20]; 12791 12792 u8 reserved_at_80[0x180]; 12793 }; 12794 12795 #endif /* MLX5_IFC_H */ 12796