1 /* 2 * Copyright (c) 2013-2015, Mellanox Technologies, Ltd. All rights reserved. 3 * 4 * This software is available to you under a choice of one of two 5 * licenses. You may choose to be licensed under the terms of the GNU 6 * General Public License (GPL) Version 2, available from the file 7 * COPYING in the main directory of this source tree, or the 8 * OpenIB.org BSD license below: 9 * 10 * Redistribution and use in source and binary forms, with or 11 * without modification, are permitted provided that the following 12 * conditions are met: 13 * 14 * - Redistributions of source code must retain the above 15 * copyright notice, this list of conditions and the following 16 * disclaimer. 17 * 18 * - Redistributions in binary form must reproduce the above 19 * copyright notice, this list of conditions and the following 20 * disclaimer in the documentation and/or other materials 21 * provided with the distribution. 22 * 23 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, 24 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF 25 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND 26 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS 27 * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN 28 * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN 29 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE 30 * SOFTWARE. 31 */ 32 #ifndef MLX5_IFC_H 33 #define MLX5_IFC_H 34 35 #include "mlx5_ifc_fpga.h" 36 37 enum { 38 MLX5_EVENT_TYPE_CODING_COMPLETION_EVENTS = 0x0, 39 MLX5_EVENT_TYPE_CODING_PATH_MIGRATED_SUCCEEDED = 0x1, 40 MLX5_EVENT_TYPE_CODING_COMMUNICATION_ESTABLISHED = 0x2, 41 MLX5_EVENT_TYPE_CODING_SEND_QUEUE_DRAINED = 0x3, 42 MLX5_EVENT_TYPE_CODING_LAST_WQE_REACHED = 0x13, 43 MLX5_EVENT_TYPE_CODING_SRQ_LIMIT = 0x14, 44 MLX5_EVENT_TYPE_CODING_DCT_ALL_CONNECTIONS_CLOSED = 0x1c, 45 MLX5_EVENT_TYPE_CODING_DCT_ACCESS_KEY_VIOLATION = 0x1d, 46 MLX5_EVENT_TYPE_CODING_CQ_ERROR = 0x4, 47 MLX5_EVENT_TYPE_CODING_LOCAL_WQ_CATASTROPHIC_ERROR = 0x5, 48 MLX5_EVENT_TYPE_CODING_PATH_MIGRATION_FAILED = 0x7, 49 MLX5_EVENT_TYPE_CODING_PAGE_FAULT_EVENT = 0xc, 50 MLX5_EVENT_TYPE_CODING_INVALID_REQUEST_LOCAL_WQ_ERROR = 0x10, 51 MLX5_EVENT_TYPE_CODING_LOCAL_ACCESS_VIOLATION_WQ_ERROR = 0x11, 52 MLX5_EVENT_TYPE_CODING_LOCAL_SRQ_CATASTROPHIC_ERROR = 0x12, 53 MLX5_EVENT_TYPE_CODING_INTERNAL_ERROR = 0x8, 54 MLX5_EVENT_TYPE_CODING_PORT_STATE_CHANGE = 0x9, 55 MLX5_EVENT_TYPE_CODING_GPIO_EVENT = 0x15, 56 MLX5_EVENT_TYPE_CODING_REMOTE_CONFIGURATION_PROTOCOL_EVENT = 0x19, 57 MLX5_EVENT_TYPE_CODING_DOORBELL_BLUEFLAME_CONGESTION_EVENT = 0x1a, 58 MLX5_EVENT_TYPE_CODING_STALL_VL_EVENT = 0x1b, 59 MLX5_EVENT_TYPE_CODING_DROPPED_PACKET_LOGGED_EVENT = 0x1f, 60 MLX5_EVENT_TYPE_CODING_COMMAND_INTERFACE_COMPLETION = 0xa, 61 MLX5_EVENT_TYPE_CODING_PAGE_REQUEST = 0xb, 62 MLX5_EVENT_TYPE_CODING_FPGA_ERROR = 0x20, 63 MLX5_EVENT_TYPE_CODING_FPGA_QP_ERROR = 0x21 64 }; 65 66 enum { 67 MLX5_SET_HCA_CAP_OP_MOD_GENERAL_DEVICE = 0x0, 68 MLX5_SET_HCA_CAP_OP_MOD_ETHERNET_OFFLOADS = 0x1, 69 MLX5_SET_HCA_CAP_OP_MOD_ODP = 0x2, 70 MLX5_SET_HCA_CAP_OP_MOD_ATOMIC = 0x3, 71 MLX5_SET_HCA_CAP_OP_MOD_ROCE = 0x4, 72 MLX5_SET_HCA_CAP_OP_MOD_IPSEC = 0x15, 73 MLX5_SET_HCA_CAP_OP_MOD_GENERAL_DEVICE2 = 0x20, 74 MLX5_SET_HCA_CAP_OP_MOD_PORT_SELECTION = 0x25, 75 }; 76 77 enum { 78 MLX5_SHARED_RESOURCE_UID = 0xffff, 79 }; 80 81 enum { 82 MLX5_OBJ_TYPE_SW_ICM = 0x0008, 83 MLX5_OBJ_TYPE_GENEVE_TLV_OPT = 0x000b, 84 MLX5_OBJ_TYPE_VIRTIO_NET_Q = 0x000d, 85 MLX5_OBJ_TYPE_VIRTIO_Q_COUNTERS = 0x001c, 86 MLX5_OBJ_TYPE_MATCH_DEFINER = 0x0018, 87 MLX5_OBJ_TYPE_HEADER_MODIFY_ARGUMENT = 0x23, 88 MLX5_OBJ_TYPE_STC = 0x0040, 89 MLX5_OBJ_TYPE_RTC = 0x0041, 90 MLX5_OBJ_TYPE_STE = 0x0042, 91 MLX5_OBJ_TYPE_MODIFY_HDR_PATTERN = 0x0043, 92 MLX5_OBJ_TYPE_PAGE_TRACK = 0x46, 93 MLX5_OBJ_TYPE_MKEY = 0xff01, 94 MLX5_OBJ_TYPE_QP = 0xff02, 95 MLX5_OBJ_TYPE_PSV = 0xff03, 96 MLX5_OBJ_TYPE_RMP = 0xff04, 97 MLX5_OBJ_TYPE_XRC_SRQ = 0xff05, 98 MLX5_OBJ_TYPE_RQ = 0xff06, 99 MLX5_OBJ_TYPE_SQ = 0xff07, 100 MLX5_OBJ_TYPE_TIR = 0xff08, 101 MLX5_OBJ_TYPE_TIS = 0xff09, 102 MLX5_OBJ_TYPE_DCT = 0xff0a, 103 MLX5_OBJ_TYPE_XRQ = 0xff0b, 104 MLX5_OBJ_TYPE_RQT = 0xff0e, 105 MLX5_OBJ_TYPE_FLOW_COUNTER = 0xff0f, 106 MLX5_OBJ_TYPE_CQ = 0xff10, 107 MLX5_OBJ_TYPE_FT_ALIAS = 0xff15, 108 }; 109 110 enum { 111 MLX5_GENERAL_OBJ_TYPES_CAP_SW_ICM = (1ULL << MLX5_OBJ_TYPE_SW_ICM), 112 MLX5_GENERAL_OBJ_TYPES_CAP_GENEVE_TLV_OPT = (1ULL << 11), 113 MLX5_GENERAL_OBJ_TYPES_CAP_VIRTIO_NET_Q = (1ULL << 13), 114 MLX5_GENERAL_OBJ_TYPES_CAP_HEADER_MODIFY_ARGUMENT = 115 (1ULL << MLX5_OBJ_TYPE_HEADER_MODIFY_ARGUMENT), 116 MLX5_GENERAL_OBJ_TYPES_CAP_MACSEC_OFFLOAD = (1ULL << 39), 117 }; 118 119 enum { 120 MLX5_CMD_OP_QUERY_HCA_CAP = 0x100, 121 MLX5_CMD_OP_QUERY_ADAPTER = 0x101, 122 MLX5_CMD_OP_INIT_HCA = 0x102, 123 MLX5_CMD_OP_TEARDOWN_HCA = 0x103, 124 MLX5_CMD_OP_ENABLE_HCA = 0x104, 125 MLX5_CMD_OP_DISABLE_HCA = 0x105, 126 MLX5_CMD_OP_QUERY_PAGES = 0x107, 127 MLX5_CMD_OP_MANAGE_PAGES = 0x108, 128 MLX5_CMD_OP_SET_HCA_CAP = 0x109, 129 MLX5_CMD_OP_QUERY_ISSI = 0x10a, 130 MLX5_CMD_OP_SET_ISSI = 0x10b, 131 MLX5_CMD_OP_SET_DRIVER_VERSION = 0x10d, 132 MLX5_CMD_OP_QUERY_SF_PARTITION = 0x111, 133 MLX5_CMD_OP_ALLOC_SF = 0x113, 134 MLX5_CMD_OP_DEALLOC_SF = 0x114, 135 MLX5_CMD_OP_SUSPEND_VHCA = 0x115, 136 MLX5_CMD_OP_RESUME_VHCA = 0x116, 137 MLX5_CMD_OP_QUERY_VHCA_MIGRATION_STATE = 0x117, 138 MLX5_CMD_OP_SAVE_VHCA_STATE = 0x118, 139 MLX5_CMD_OP_LOAD_VHCA_STATE = 0x119, 140 MLX5_CMD_OP_CREATE_MKEY = 0x200, 141 MLX5_CMD_OP_QUERY_MKEY = 0x201, 142 MLX5_CMD_OP_DESTROY_MKEY = 0x202, 143 MLX5_CMD_OP_QUERY_SPECIAL_CONTEXTS = 0x203, 144 MLX5_CMD_OP_PAGE_FAULT_RESUME = 0x204, 145 MLX5_CMD_OP_ALLOC_MEMIC = 0x205, 146 MLX5_CMD_OP_DEALLOC_MEMIC = 0x206, 147 MLX5_CMD_OP_MODIFY_MEMIC = 0x207, 148 MLX5_CMD_OP_CREATE_EQ = 0x301, 149 MLX5_CMD_OP_DESTROY_EQ = 0x302, 150 MLX5_CMD_OP_QUERY_EQ = 0x303, 151 MLX5_CMD_OP_GEN_EQE = 0x304, 152 MLX5_CMD_OP_CREATE_CQ = 0x400, 153 MLX5_CMD_OP_DESTROY_CQ = 0x401, 154 MLX5_CMD_OP_QUERY_CQ = 0x402, 155 MLX5_CMD_OP_MODIFY_CQ = 0x403, 156 MLX5_CMD_OP_CREATE_QP = 0x500, 157 MLX5_CMD_OP_DESTROY_QP = 0x501, 158 MLX5_CMD_OP_RST2INIT_QP = 0x502, 159 MLX5_CMD_OP_INIT2RTR_QP = 0x503, 160 MLX5_CMD_OP_RTR2RTS_QP = 0x504, 161 MLX5_CMD_OP_RTS2RTS_QP = 0x505, 162 MLX5_CMD_OP_SQERR2RTS_QP = 0x506, 163 MLX5_CMD_OP_2ERR_QP = 0x507, 164 MLX5_CMD_OP_2RST_QP = 0x50a, 165 MLX5_CMD_OP_QUERY_QP = 0x50b, 166 MLX5_CMD_OP_SQD_RTS_QP = 0x50c, 167 MLX5_CMD_OP_INIT2INIT_QP = 0x50e, 168 MLX5_CMD_OP_CREATE_PSV = 0x600, 169 MLX5_CMD_OP_DESTROY_PSV = 0x601, 170 MLX5_CMD_OP_CREATE_SRQ = 0x700, 171 MLX5_CMD_OP_DESTROY_SRQ = 0x701, 172 MLX5_CMD_OP_QUERY_SRQ = 0x702, 173 MLX5_CMD_OP_ARM_RQ = 0x703, 174 MLX5_CMD_OP_CREATE_XRC_SRQ = 0x705, 175 MLX5_CMD_OP_DESTROY_XRC_SRQ = 0x706, 176 MLX5_CMD_OP_QUERY_XRC_SRQ = 0x707, 177 MLX5_CMD_OP_ARM_XRC_SRQ = 0x708, 178 MLX5_CMD_OP_CREATE_DCT = 0x710, 179 MLX5_CMD_OP_DESTROY_DCT = 0x711, 180 MLX5_CMD_OP_DRAIN_DCT = 0x712, 181 MLX5_CMD_OP_QUERY_DCT = 0x713, 182 MLX5_CMD_OP_ARM_DCT_FOR_KEY_VIOLATION = 0x714, 183 MLX5_CMD_OP_CREATE_XRQ = 0x717, 184 MLX5_CMD_OP_DESTROY_XRQ = 0x718, 185 MLX5_CMD_OP_QUERY_XRQ = 0x719, 186 MLX5_CMD_OP_ARM_XRQ = 0x71a, 187 MLX5_CMD_OP_QUERY_XRQ_DC_PARAMS_ENTRY = 0x725, 188 MLX5_CMD_OP_SET_XRQ_DC_PARAMS_ENTRY = 0x726, 189 MLX5_CMD_OP_QUERY_XRQ_ERROR_PARAMS = 0x727, 190 MLX5_CMD_OP_RELEASE_XRQ_ERROR = 0x729, 191 MLX5_CMD_OP_MODIFY_XRQ = 0x72a, 192 MLX5_CMD_OP_QUERY_ESW_FUNCTIONS = 0x740, 193 MLX5_CMD_OP_QUERY_VPORT_STATE = 0x750, 194 MLX5_CMD_OP_MODIFY_VPORT_STATE = 0x751, 195 MLX5_CMD_OP_QUERY_ESW_VPORT_CONTEXT = 0x752, 196 MLX5_CMD_OP_MODIFY_ESW_VPORT_CONTEXT = 0x753, 197 MLX5_CMD_OP_QUERY_NIC_VPORT_CONTEXT = 0x754, 198 MLX5_CMD_OP_MODIFY_NIC_VPORT_CONTEXT = 0x755, 199 MLX5_CMD_OP_QUERY_ROCE_ADDRESS = 0x760, 200 MLX5_CMD_OP_SET_ROCE_ADDRESS = 0x761, 201 MLX5_CMD_OP_QUERY_HCA_VPORT_CONTEXT = 0x762, 202 MLX5_CMD_OP_MODIFY_HCA_VPORT_CONTEXT = 0x763, 203 MLX5_CMD_OP_QUERY_HCA_VPORT_GID = 0x764, 204 MLX5_CMD_OP_QUERY_HCA_VPORT_PKEY = 0x765, 205 MLX5_CMD_OP_QUERY_VNIC_ENV = 0x76f, 206 MLX5_CMD_OP_QUERY_VPORT_COUNTER = 0x770, 207 MLX5_CMD_OP_ALLOC_Q_COUNTER = 0x771, 208 MLX5_CMD_OP_DEALLOC_Q_COUNTER = 0x772, 209 MLX5_CMD_OP_QUERY_Q_COUNTER = 0x773, 210 MLX5_CMD_OP_SET_MONITOR_COUNTER = 0x774, 211 MLX5_CMD_OP_ARM_MONITOR_COUNTER = 0x775, 212 MLX5_CMD_OP_SET_PP_RATE_LIMIT = 0x780, 213 MLX5_CMD_OP_QUERY_RATE_LIMIT = 0x781, 214 MLX5_CMD_OP_CREATE_SCHEDULING_ELEMENT = 0x782, 215 MLX5_CMD_OP_DESTROY_SCHEDULING_ELEMENT = 0x783, 216 MLX5_CMD_OP_QUERY_SCHEDULING_ELEMENT = 0x784, 217 MLX5_CMD_OP_MODIFY_SCHEDULING_ELEMENT = 0x785, 218 MLX5_CMD_OP_CREATE_QOS_PARA_VPORT = 0x786, 219 MLX5_CMD_OP_DESTROY_QOS_PARA_VPORT = 0x787, 220 MLX5_CMD_OP_ALLOC_PD = 0x800, 221 MLX5_CMD_OP_DEALLOC_PD = 0x801, 222 MLX5_CMD_OP_ALLOC_UAR = 0x802, 223 MLX5_CMD_OP_DEALLOC_UAR = 0x803, 224 MLX5_CMD_OP_CONFIG_INT_MODERATION = 0x804, 225 MLX5_CMD_OP_ACCESS_REG = 0x805, 226 MLX5_CMD_OP_ATTACH_TO_MCG = 0x806, 227 MLX5_CMD_OP_DETACH_FROM_MCG = 0x807, 228 MLX5_CMD_OP_GET_DROPPED_PACKET_LOG = 0x80a, 229 MLX5_CMD_OP_MAD_IFC = 0x50d, 230 MLX5_CMD_OP_QUERY_MAD_DEMUX = 0x80b, 231 MLX5_CMD_OP_SET_MAD_DEMUX = 0x80c, 232 MLX5_CMD_OP_NOP = 0x80d, 233 MLX5_CMD_OP_ALLOC_XRCD = 0x80e, 234 MLX5_CMD_OP_DEALLOC_XRCD = 0x80f, 235 MLX5_CMD_OP_ALLOC_TRANSPORT_DOMAIN = 0x816, 236 MLX5_CMD_OP_DEALLOC_TRANSPORT_DOMAIN = 0x817, 237 MLX5_CMD_OP_QUERY_CONG_STATUS = 0x822, 238 MLX5_CMD_OP_MODIFY_CONG_STATUS = 0x823, 239 MLX5_CMD_OP_QUERY_CONG_PARAMS = 0x824, 240 MLX5_CMD_OP_MODIFY_CONG_PARAMS = 0x825, 241 MLX5_CMD_OP_QUERY_CONG_STATISTICS = 0x826, 242 MLX5_CMD_OP_ADD_VXLAN_UDP_DPORT = 0x827, 243 MLX5_CMD_OP_DELETE_VXLAN_UDP_DPORT = 0x828, 244 MLX5_CMD_OP_SET_L2_TABLE_ENTRY = 0x829, 245 MLX5_CMD_OP_QUERY_L2_TABLE_ENTRY = 0x82a, 246 MLX5_CMD_OP_DELETE_L2_TABLE_ENTRY = 0x82b, 247 MLX5_CMD_OP_SET_WOL_ROL = 0x830, 248 MLX5_CMD_OP_QUERY_WOL_ROL = 0x831, 249 MLX5_CMD_OP_CREATE_LAG = 0x840, 250 MLX5_CMD_OP_MODIFY_LAG = 0x841, 251 MLX5_CMD_OP_QUERY_LAG = 0x842, 252 MLX5_CMD_OP_DESTROY_LAG = 0x843, 253 MLX5_CMD_OP_CREATE_VPORT_LAG = 0x844, 254 MLX5_CMD_OP_DESTROY_VPORT_LAG = 0x845, 255 MLX5_CMD_OP_CREATE_TIR = 0x900, 256 MLX5_CMD_OP_MODIFY_TIR = 0x901, 257 MLX5_CMD_OP_DESTROY_TIR = 0x902, 258 MLX5_CMD_OP_QUERY_TIR = 0x903, 259 MLX5_CMD_OP_CREATE_SQ = 0x904, 260 MLX5_CMD_OP_MODIFY_SQ = 0x905, 261 MLX5_CMD_OP_DESTROY_SQ = 0x906, 262 MLX5_CMD_OP_QUERY_SQ = 0x907, 263 MLX5_CMD_OP_CREATE_RQ = 0x908, 264 MLX5_CMD_OP_MODIFY_RQ = 0x909, 265 MLX5_CMD_OP_SET_DELAY_DROP_PARAMS = 0x910, 266 MLX5_CMD_OP_DESTROY_RQ = 0x90a, 267 MLX5_CMD_OP_QUERY_RQ = 0x90b, 268 MLX5_CMD_OP_CREATE_RMP = 0x90c, 269 MLX5_CMD_OP_MODIFY_RMP = 0x90d, 270 MLX5_CMD_OP_DESTROY_RMP = 0x90e, 271 MLX5_CMD_OP_QUERY_RMP = 0x90f, 272 MLX5_CMD_OP_CREATE_TIS = 0x912, 273 MLX5_CMD_OP_MODIFY_TIS = 0x913, 274 MLX5_CMD_OP_DESTROY_TIS = 0x914, 275 MLX5_CMD_OP_QUERY_TIS = 0x915, 276 MLX5_CMD_OP_CREATE_RQT = 0x916, 277 MLX5_CMD_OP_MODIFY_RQT = 0x917, 278 MLX5_CMD_OP_DESTROY_RQT = 0x918, 279 MLX5_CMD_OP_QUERY_RQT = 0x919, 280 MLX5_CMD_OP_SET_FLOW_TABLE_ROOT = 0x92f, 281 MLX5_CMD_OP_CREATE_FLOW_TABLE = 0x930, 282 MLX5_CMD_OP_DESTROY_FLOW_TABLE = 0x931, 283 MLX5_CMD_OP_QUERY_FLOW_TABLE = 0x932, 284 MLX5_CMD_OP_CREATE_FLOW_GROUP = 0x933, 285 MLX5_CMD_OP_DESTROY_FLOW_GROUP = 0x934, 286 MLX5_CMD_OP_QUERY_FLOW_GROUP = 0x935, 287 MLX5_CMD_OP_SET_FLOW_TABLE_ENTRY = 0x936, 288 MLX5_CMD_OP_QUERY_FLOW_TABLE_ENTRY = 0x937, 289 MLX5_CMD_OP_DELETE_FLOW_TABLE_ENTRY = 0x938, 290 MLX5_CMD_OP_ALLOC_FLOW_COUNTER = 0x939, 291 MLX5_CMD_OP_DEALLOC_FLOW_COUNTER = 0x93a, 292 MLX5_CMD_OP_QUERY_FLOW_COUNTER = 0x93b, 293 MLX5_CMD_OP_MODIFY_FLOW_TABLE = 0x93c, 294 MLX5_CMD_OP_ALLOC_PACKET_REFORMAT_CONTEXT = 0x93d, 295 MLX5_CMD_OP_DEALLOC_PACKET_REFORMAT_CONTEXT = 0x93e, 296 MLX5_CMD_OP_QUERY_PACKET_REFORMAT_CONTEXT = 0x93f, 297 MLX5_CMD_OP_ALLOC_MODIFY_HEADER_CONTEXT = 0x940, 298 MLX5_CMD_OP_DEALLOC_MODIFY_HEADER_CONTEXT = 0x941, 299 MLX5_CMD_OP_QUERY_MODIFY_HEADER_CONTEXT = 0x942, 300 MLX5_CMD_OP_FPGA_CREATE_QP = 0x960, 301 MLX5_CMD_OP_FPGA_MODIFY_QP = 0x961, 302 MLX5_CMD_OP_FPGA_QUERY_QP = 0x962, 303 MLX5_CMD_OP_FPGA_DESTROY_QP = 0x963, 304 MLX5_CMD_OP_FPGA_QUERY_QP_COUNTERS = 0x964, 305 MLX5_CMD_OP_CREATE_GENERAL_OBJECT = 0xa00, 306 MLX5_CMD_OP_MODIFY_GENERAL_OBJECT = 0xa01, 307 MLX5_CMD_OP_QUERY_GENERAL_OBJECT = 0xa02, 308 MLX5_CMD_OP_DESTROY_GENERAL_OBJECT = 0xa03, 309 MLX5_CMD_OP_CREATE_UCTX = 0xa04, 310 MLX5_CMD_OP_DESTROY_UCTX = 0xa06, 311 MLX5_CMD_OP_CREATE_UMEM = 0xa08, 312 MLX5_CMD_OP_DESTROY_UMEM = 0xa0a, 313 MLX5_CMD_OP_SYNC_STEERING = 0xb00, 314 MLX5_CMD_OP_QUERY_VHCA_STATE = 0xb0d, 315 MLX5_CMD_OP_MODIFY_VHCA_STATE = 0xb0e, 316 MLX5_CMD_OP_SYNC_CRYPTO = 0xb12, 317 MLX5_CMD_OP_ALLOW_OTHER_VHCA_ACCESS = 0xb16, 318 MLX5_CMD_OP_GENERATE_WQE = 0xb17, 319 MLX5_CMD_OP_MAX 320 }; 321 322 /* Valid range for general commands that don't work over an object */ 323 enum { 324 MLX5_CMD_OP_GENERAL_START = 0xb00, 325 MLX5_CMD_OP_GENERAL_END = 0xd00, 326 }; 327 328 enum { 329 MLX5_FT_NIC_RX_2_NIC_RX_RDMA = BIT(0), 330 MLX5_FT_NIC_TX_RDMA_2_NIC_TX = BIT(1), 331 }; 332 333 enum { 334 MLX5_CMD_OP_MOD_UPDATE_HEADER_MODIFY_ARGUMENT = 0x1, 335 }; 336 337 struct mlx5_ifc_flow_table_fields_supported_bits { 338 u8 outer_dmac[0x1]; 339 u8 outer_smac[0x1]; 340 u8 outer_ether_type[0x1]; 341 u8 outer_ip_version[0x1]; 342 u8 outer_first_prio[0x1]; 343 u8 outer_first_cfi[0x1]; 344 u8 outer_first_vid[0x1]; 345 u8 outer_ipv4_ttl[0x1]; 346 u8 outer_second_prio[0x1]; 347 u8 outer_second_cfi[0x1]; 348 u8 outer_second_vid[0x1]; 349 u8 reserved_at_b[0x1]; 350 u8 outer_sip[0x1]; 351 u8 outer_dip[0x1]; 352 u8 outer_frag[0x1]; 353 u8 outer_ip_protocol[0x1]; 354 u8 outer_ip_ecn[0x1]; 355 u8 outer_ip_dscp[0x1]; 356 u8 outer_udp_sport[0x1]; 357 u8 outer_udp_dport[0x1]; 358 u8 outer_tcp_sport[0x1]; 359 u8 outer_tcp_dport[0x1]; 360 u8 outer_tcp_flags[0x1]; 361 u8 outer_gre_protocol[0x1]; 362 u8 outer_gre_key[0x1]; 363 u8 outer_vxlan_vni[0x1]; 364 u8 outer_geneve_vni[0x1]; 365 u8 outer_geneve_oam[0x1]; 366 u8 outer_geneve_protocol_type[0x1]; 367 u8 outer_geneve_opt_len[0x1]; 368 u8 source_vhca_port[0x1]; 369 u8 source_eswitch_port[0x1]; 370 371 u8 inner_dmac[0x1]; 372 u8 inner_smac[0x1]; 373 u8 inner_ether_type[0x1]; 374 u8 inner_ip_version[0x1]; 375 u8 inner_first_prio[0x1]; 376 u8 inner_first_cfi[0x1]; 377 u8 inner_first_vid[0x1]; 378 u8 reserved_at_27[0x1]; 379 u8 inner_second_prio[0x1]; 380 u8 inner_second_cfi[0x1]; 381 u8 inner_second_vid[0x1]; 382 u8 reserved_at_2b[0x1]; 383 u8 inner_sip[0x1]; 384 u8 inner_dip[0x1]; 385 u8 inner_frag[0x1]; 386 u8 inner_ip_protocol[0x1]; 387 u8 inner_ip_ecn[0x1]; 388 u8 inner_ip_dscp[0x1]; 389 u8 inner_udp_sport[0x1]; 390 u8 inner_udp_dport[0x1]; 391 u8 inner_tcp_sport[0x1]; 392 u8 inner_tcp_dport[0x1]; 393 u8 inner_tcp_flags[0x1]; 394 u8 reserved_at_37[0x9]; 395 396 u8 geneve_tlv_option_0_data[0x1]; 397 u8 geneve_tlv_option_0_exist[0x1]; 398 u8 reserved_at_42[0x3]; 399 u8 outer_first_mpls_over_udp[0x4]; 400 u8 outer_first_mpls_over_gre[0x4]; 401 u8 inner_first_mpls[0x4]; 402 u8 outer_first_mpls[0x4]; 403 u8 reserved_at_55[0x2]; 404 u8 outer_esp_spi[0x1]; 405 u8 reserved_at_58[0x2]; 406 u8 bth_dst_qp[0x1]; 407 u8 reserved_at_5b[0x5]; 408 409 u8 reserved_at_60[0x18]; 410 u8 metadata_reg_c_7[0x1]; 411 u8 metadata_reg_c_6[0x1]; 412 u8 metadata_reg_c_5[0x1]; 413 u8 metadata_reg_c_4[0x1]; 414 u8 metadata_reg_c_3[0x1]; 415 u8 metadata_reg_c_2[0x1]; 416 u8 metadata_reg_c_1[0x1]; 417 u8 metadata_reg_c_0[0x1]; 418 }; 419 420 /* Table 2170 - Flow Table Fields Supported 2 Format */ 421 struct mlx5_ifc_flow_table_fields_supported_2_bits { 422 u8 reserved_at_0[0x2]; 423 u8 inner_l4_type[0x1]; 424 u8 outer_l4_type[0x1]; 425 u8 reserved_at_4[0xa]; 426 u8 bth_opcode[0x1]; 427 u8 reserved_at_f[0x1]; 428 u8 tunnel_header_0_1[0x1]; 429 u8 reserved_at_11[0xf]; 430 431 u8 reserved_at_20[0x60]; 432 }; 433 434 struct mlx5_ifc_flow_table_prop_layout_bits { 435 u8 ft_support[0x1]; 436 u8 reserved_at_1[0x1]; 437 u8 flow_counter[0x1]; 438 u8 flow_modify_en[0x1]; 439 u8 modify_root[0x1]; 440 u8 identified_miss_table_mode[0x1]; 441 u8 flow_table_modify[0x1]; 442 u8 reformat[0x1]; 443 u8 decap[0x1]; 444 u8 reset_root_to_default[0x1]; 445 u8 pop_vlan[0x1]; 446 u8 push_vlan[0x1]; 447 u8 reserved_at_c[0x1]; 448 u8 pop_vlan_2[0x1]; 449 u8 push_vlan_2[0x1]; 450 u8 reformat_and_vlan_action[0x1]; 451 u8 reserved_at_10[0x1]; 452 u8 sw_owner[0x1]; 453 u8 reformat_l3_tunnel_to_l2[0x1]; 454 u8 reformat_l2_to_l3_tunnel[0x1]; 455 u8 reformat_and_modify_action[0x1]; 456 u8 ignore_flow_level[0x1]; 457 u8 reserved_at_16[0x1]; 458 u8 table_miss_action_domain[0x1]; 459 u8 termination_table[0x1]; 460 u8 reformat_and_fwd_to_table[0x1]; 461 u8 reserved_at_1a[0x2]; 462 u8 ipsec_encrypt[0x1]; 463 u8 ipsec_decrypt[0x1]; 464 u8 sw_owner_v2[0x1]; 465 u8 reserved_at_1f[0x1]; 466 467 u8 termination_table_raw_traffic[0x1]; 468 u8 reserved_at_21[0x1]; 469 u8 log_max_ft_size[0x6]; 470 u8 log_max_modify_header_context[0x8]; 471 u8 max_modify_header_actions[0x8]; 472 u8 max_ft_level[0x8]; 473 474 u8 reformat_add_esp_trasport[0x1]; 475 u8 reformat_l2_to_l3_esp_tunnel[0x1]; 476 u8 reformat_add_esp_transport_over_udp[0x1]; 477 u8 reformat_del_esp_trasport[0x1]; 478 u8 reformat_l3_esp_tunnel_to_l2[0x1]; 479 u8 reformat_del_esp_transport_over_udp[0x1]; 480 u8 execute_aso[0x1]; 481 u8 reserved_at_47[0x19]; 482 483 u8 reserved_at_60[0x2]; 484 u8 reformat_insert[0x1]; 485 u8 reformat_remove[0x1]; 486 u8 macsec_encrypt[0x1]; 487 u8 macsec_decrypt[0x1]; 488 u8 reserved_at_66[0x2]; 489 u8 reformat_add_macsec[0x1]; 490 u8 reformat_remove_macsec[0x1]; 491 u8 reparse[0x1]; 492 u8 reserved_at_6b[0x1]; 493 u8 cross_vhca_object[0x1]; 494 u8 reformat_l2_to_l3_audp_tunnel[0x1]; 495 u8 reformat_l3_audp_tunnel_to_l2[0x1]; 496 u8 ignore_flow_level_rtc_valid[0x1]; 497 u8 reserved_at_70[0x8]; 498 u8 log_max_ft_num[0x8]; 499 500 u8 reserved_at_80[0x10]; 501 u8 log_max_flow_counter[0x8]; 502 u8 log_max_destination[0x8]; 503 504 u8 reserved_at_a0[0x18]; 505 u8 log_max_flow[0x8]; 506 507 u8 reserved_at_c0[0x40]; 508 509 struct mlx5_ifc_flow_table_fields_supported_bits ft_field_support; 510 511 struct mlx5_ifc_flow_table_fields_supported_bits ft_field_bitmask_support; 512 }; 513 514 struct mlx5_ifc_odp_per_transport_service_cap_bits { 515 u8 send[0x1]; 516 u8 receive[0x1]; 517 u8 write[0x1]; 518 u8 read[0x1]; 519 u8 atomic[0x1]; 520 u8 srq_receive[0x1]; 521 u8 reserved_at_6[0x1a]; 522 }; 523 524 struct mlx5_ifc_ipv4_layout_bits { 525 u8 reserved_at_0[0x60]; 526 527 u8 ipv4[0x20]; 528 }; 529 530 struct mlx5_ifc_ipv6_layout_bits { 531 u8 ipv6[16][0x8]; 532 }; 533 534 struct mlx5_ifc_ipv6_simple_layout_bits { 535 u8 ipv6_127_96[0x20]; 536 u8 ipv6_95_64[0x20]; 537 u8 ipv6_63_32[0x20]; 538 u8 ipv6_31_0[0x20]; 539 }; 540 541 union mlx5_ifc_ipv6_layout_ipv4_layout_auto_bits { 542 struct mlx5_ifc_ipv6_simple_layout_bits ipv6_simple_layout; 543 struct mlx5_ifc_ipv6_layout_bits ipv6_layout; 544 struct mlx5_ifc_ipv4_layout_bits ipv4_layout; 545 u8 reserved_at_0[0x80]; 546 }; 547 548 enum { 549 MLX5_PACKET_L4_TYPE_NONE, 550 MLX5_PACKET_L4_TYPE_TCP, 551 MLX5_PACKET_L4_TYPE_UDP, 552 }; 553 554 struct mlx5_ifc_fte_match_set_lyr_2_4_bits { 555 u8 smac_47_16[0x20]; 556 557 u8 smac_15_0[0x10]; 558 u8 ethertype[0x10]; 559 560 u8 dmac_47_16[0x20]; 561 562 u8 dmac_15_0[0x10]; 563 u8 first_prio[0x3]; 564 u8 first_cfi[0x1]; 565 u8 first_vid[0xc]; 566 567 u8 ip_protocol[0x8]; 568 u8 ip_dscp[0x6]; 569 u8 ip_ecn[0x2]; 570 u8 cvlan_tag[0x1]; 571 u8 svlan_tag[0x1]; 572 u8 frag[0x1]; 573 u8 ip_version[0x4]; 574 u8 tcp_flags[0x9]; 575 576 u8 tcp_sport[0x10]; 577 u8 tcp_dport[0x10]; 578 579 u8 l4_type[0x2]; 580 u8 reserved_at_c2[0xe]; 581 u8 ipv4_ihl[0x4]; 582 u8 reserved_at_c4[0x4]; 583 584 u8 ttl_hoplimit[0x8]; 585 586 u8 udp_sport[0x10]; 587 u8 udp_dport[0x10]; 588 589 union mlx5_ifc_ipv6_layout_ipv4_layout_auto_bits src_ipv4_src_ipv6; 590 591 union mlx5_ifc_ipv6_layout_ipv4_layout_auto_bits dst_ipv4_dst_ipv6; 592 }; 593 594 struct mlx5_ifc_nvgre_key_bits { 595 u8 hi[0x18]; 596 u8 lo[0x8]; 597 }; 598 599 union mlx5_ifc_gre_key_bits { 600 struct mlx5_ifc_nvgre_key_bits nvgre; 601 u8 key[0x20]; 602 }; 603 604 struct mlx5_ifc_fte_match_set_misc_bits { 605 u8 gre_c_present[0x1]; 606 u8 reserved_at_1[0x1]; 607 u8 gre_k_present[0x1]; 608 u8 gre_s_present[0x1]; 609 u8 source_vhca_port[0x4]; 610 u8 source_sqn[0x18]; 611 612 u8 source_eswitch_owner_vhca_id[0x10]; 613 u8 source_port[0x10]; 614 615 u8 outer_second_prio[0x3]; 616 u8 outer_second_cfi[0x1]; 617 u8 outer_second_vid[0xc]; 618 u8 inner_second_prio[0x3]; 619 u8 inner_second_cfi[0x1]; 620 u8 inner_second_vid[0xc]; 621 622 u8 outer_second_cvlan_tag[0x1]; 623 u8 inner_second_cvlan_tag[0x1]; 624 u8 outer_second_svlan_tag[0x1]; 625 u8 inner_second_svlan_tag[0x1]; 626 u8 reserved_at_64[0xc]; 627 u8 gre_protocol[0x10]; 628 629 union mlx5_ifc_gre_key_bits gre_key; 630 631 u8 vxlan_vni[0x18]; 632 u8 bth_opcode[0x8]; 633 634 u8 geneve_vni[0x18]; 635 u8 reserved_at_d8[0x6]; 636 u8 geneve_tlv_option_0_exist[0x1]; 637 u8 geneve_oam[0x1]; 638 639 u8 reserved_at_e0[0xc]; 640 u8 outer_ipv6_flow_label[0x14]; 641 642 u8 reserved_at_100[0xc]; 643 u8 inner_ipv6_flow_label[0x14]; 644 645 u8 reserved_at_120[0xa]; 646 u8 geneve_opt_len[0x6]; 647 u8 geneve_protocol_type[0x10]; 648 649 u8 reserved_at_140[0x8]; 650 u8 bth_dst_qp[0x18]; 651 u8 inner_esp_spi[0x20]; 652 u8 outer_esp_spi[0x20]; 653 u8 reserved_at_1a0[0x60]; 654 }; 655 656 struct mlx5_ifc_fte_match_mpls_bits { 657 u8 mpls_label[0x14]; 658 u8 mpls_exp[0x3]; 659 u8 mpls_s_bos[0x1]; 660 u8 mpls_ttl[0x8]; 661 }; 662 663 struct mlx5_ifc_fte_match_set_misc2_bits { 664 struct mlx5_ifc_fte_match_mpls_bits outer_first_mpls; 665 666 struct mlx5_ifc_fte_match_mpls_bits inner_first_mpls; 667 668 struct mlx5_ifc_fte_match_mpls_bits outer_first_mpls_over_gre; 669 670 struct mlx5_ifc_fte_match_mpls_bits outer_first_mpls_over_udp; 671 672 u8 metadata_reg_c_7[0x20]; 673 674 u8 metadata_reg_c_6[0x20]; 675 676 u8 metadata_reg_c_5[0x20]; 677 678 u8 metadata_reg_c_4[0x20]; 679 680 u8 metadata_reg_c_3[0x20]; 681 682 u8 metadata_reg_c_2[0x20]; 683 684 u8 metadata_reg_c_1[0x20]; 685 686 u8 metadata_reg_c_0[0x20]; 687 688 u8 metadata_reg_a[0x20]; 689 690 u8 reserved_at_1a0[0x8]; 691 692 u8 macsec_syndrome[0x8]; 693 u8 ipsec_syndrome[0x8]; 694 u8 reserved_at_1b8[0x8]; 695 696 u8 reserved_at_1c0[0x40]; 697 }; 698 699 struct mlx5_ifc_fte_match_set_misc3_bits { 700 u8 inner_tcp_seq_num[0x20]; 701 702 u8 outer_tcp_seq_num[0x20]; 703 704 u8 inner_tcp_ack_num[0x20]; 705 706 u8 outer_tcp_ack_num[0x20]; 707 708 u8 reserved_at_80[0x8]; 709 u8 outer_vxlan_gpe_vni[0x18]; 710 711 u8 outer_vxlan_gpe_next_protocol[0x8]; 712 u8 outer_vxlan_gpe_flags[0x8]; 713 u8 reserved_at_b0[0x10]; 714 715 u8 icmp_header_data[0x20]; 716 717 u8 icmpv6_header_data[0x20]; 718 719 u8 icmp_type[0x8]; 720 u8 icmp_code[0x8]; 721 u8 icmpv6_type[0x8]; 722 u8 icmpv6_code[0x8]; 723 724 u8 geneve_tlv_option_0_data[0x20]; 725 726 u8 gtpu_teid[0x20]; 727 728 u8 gtpu_msg_type[0x8]; 729 u8 gtpu_msg_flags[0x8]; 730 u8 reserved_at_170[0x10]; 731 732 u8 gtpu_dw_2[0x20]; 733 734 u8 gtpu_first_ext_dw_0[0x20]; 735 736 u8 gtpu_dw_0[0x20]; 737 738 u8 reserved_at_1e0[0x20]; 739 }; 740 741 struct mlx5_ifc_fte_match_set_misc4_bits { 742 u8 prog_sample_field_value_0[0x20]; 743 744 u8 prog_sample_field_id_0[0x20]; 745 746 u8 prog_sample_field_value_1[0x20]; 747 748 u8 prog_sample_field_id_1[0x20]; 749 750 u8 prog_sample_field_value_2[0x20]; 751 752 u8 prog_sample_field_id_2[0x20]; 753 754 u8 prog_sample_field_value_3[0x20]; 755 756 u8 prog_sample_field_id_3[0x20]; 757 758 u8 reserved_at_100[0x100]; 759 }; 760 761 struct mlx5_ifc_fte_match_set_misc5_bits { 762 u8 macsec_tag_0[0x20]; 763 764 u8 macsec_tag_1[0x20]; 765 766 u8 macsec_tag_2[0x20]; 767 768 u8 macsec_tag_3[0x20]; 769 770 u8 tunnel_header_0[0x20]; 771 772 u8 tunnel_header_1[0x20]; 773 774 u8 tunnel_header_2[0x20]; 775 776 u8 tunnel_header_3[0x20]; 777 778 u8 reserved_at_100[0x100]; 779 }; 780 781 struct mlx5_ifc_cmd_pas_bits { 782 u8 pa_h[0x20]; 783 784 u8 pa_l[0x14]; 785 u8 reserved_at_34[0xc]; 786 }; 787 788 struct mlx5_ifc_uint64_bits { 789 u8 hi[0x20]; 790 791 u8 lo[0x20]; 792 }; 793 794 enum { 795 MLX5_ADS_STAT_RATE_NO_LIMIT = 0x0, 796 MLX5_ADS_STAT_RATE_2_5GBPS = 0x7, 797 MLX5_ADS_STAT_RATE_10GBPS = 0x8, 798 MLX5_ADS_STAT_RATE_30GBPS = 0x9, 799 MLX5_ADS_STAT_RATE_5GBPS = 0xa, 800 MLX5_ADS_STAT_RATE_20GBPS = 0xb, 801 MLX5_ADS_STAT_RATE_40GBPS = 0xc, 802 MLX5_ADS_STAT_RATE_60GBPS = 0xd, 803 MLX5_ADS_STAT_RATE_80GBPS = 0xe, 804 MLX5_ADS_STAT_RATE_120GBPS = 0xf, 805 }; 806 807 struct mlx5_ifc_ads_bits { 808 u8 fl[0x1]; 809 u8 free_ar[0x1]; 810 u8 reserved_at_2[0xe]; 811 u8 pkey_index[0x10]; 812 813 u8 plane_index[0x8]; 814 u8 grh[0x1]; 815 u8 mlid[0x7]; 816 u8 rlid[0x10]; 817 818 u8 ack_timeout[0x5]; 819 u8 reserved_at_45[0x3]; 820 u8 src_addr_index[0x8]; 821 u8 reserved_at_50[0x4]; 822 u8 stat_rate[0x4]; 823 u8 hop_limit[0x8]; 824 825 u8 reserved_at_60[0x4]; 826 u8 tclass[0x8]; 827 u8 flow_label[0x14]; 828 829 u8 rgid_rip[16][0x8]; 830 831 u8 reserved_at_100[0x4]; 832 u8 f_dscp[0x1]; 833 u8 f_ecn[0x1]; 834 u8 reserved_at_106[0x1]; 835 u8 f_eth_prio[0x1]; 836 u8 ecn[0x2]; 837 u8 dscp[0x6]; 838 u8 udp_sport[0x10]; 839 840 u8 dei_cfi[0x1]; 841 u8 eth_prio[0x3]; 842 u8 sl[0x4]; 843 u8 vhca_port_num[0x8]; 844 u8 rmac_47_32[0x10]; 845 846 u8 rmac_31_0[0x20]; 847 }; 848 849 struct mlx5_ifc_flow_table_nic_cap_bits { 850 u8 nic_rx_multi_path_tirs[0x1]; 851 u8 nic_rx_multi_path_tirs_fts[0x1]; 852 u8 allow_sniffer_and_nic_rx_shared_tir[0x1]; 853 u8 reserved_at_3[0x4]; 854 u8 sw_owner_reformat_supported[0x1]; 855 u8 reserved_at_8[0x18]; 856 857 u8 encap_general_header[0x1]; 858 u8 reserved_at_21[0xa]; 859 u8 log_max_packet_reformat_context[0x5]; 860 u8 reserved_at_30[0x6]; 861 u8 max_encap_header_size[0xa]; 862 u8 reserved_at_40[0x1c0]; 863 864 struct mlx5_ifc_flow_table_prop_layout_bits flow_table_properties_nic_receive; 865 866 struct mlx5_ifc_flow_table_prop_layout_bits flow_table_properties_nic_receive_rdma; 867 868 struct mlx5_ifc_flow_table_prop_layout_bits flow_table_properties_nic_receive_sniffer; 869 870 struct mlx5_ifc_flow_table_prop_layout_bits flow_table_properties_nic_transmit; 871 872 struct mlx5_ifc_flow_table_prop_layout_bits flow_table_properties_nic_transmit_rdma; 873 874 struct mlx5_ifc_flow_table_prop_layout_bits flow_table_properties_nic_transmit_sniffer; 875 876 u8 reserved_at_e00[0x600]; 877 878 struct mlx5_ifc_flow_table_fields_supported_2_bits ft_field_support_2_nic_receive; 879 880 u8 reserved_at_1480[0x80]; 881 882 struct mlx5_ifc_flow_table_fields_supported_2_bits ft_field_support_2_nic_receive_rdma; 883 884 u8 reserved_at_1580[0x280]; 885 886 struct mlx5_ifc_flow_table_fields_supported_2_bits ft_field_support_2_nic_transmit_rdma; 887 888 u8 reserved_at_1880[0x780]; 889 890 u8 sw_steering_nic_rx_action_drop_icm_address[0x40]; 891 892 u8 sw_steering_nic_tx_action_drop_icm_address[0x40]; 893 894 u8 sw_steering_nic_tx_action_allow_icm_address[0x40]; 895 896 u8 reserved_at_20c0[0x5f40]; 897 }; 898 899 struct mlx5_ifc_port_selection_cap_bits { 900 u8 reserved_at_0[0x10]; 901 u8 port_select_flow_table[0x1]; 902 u8 reserved_at_11[0x1]; 903 u8 port_select_flow_table_bypass[0x1]; 904 u8 reserved_at_13[0xd]; 905 906 u8 reserved_at_20[0x1e0]; 907 908 struct mlx5_ifc_flow_table_prop_layout_bits flow_table_properties_port_selection; 909 910 struct mlx5_ifc_flow_table_fields_supported_2_bits ft_field_support_2_port_selection; 911 912 u8 reserved_at_480[0x7b80]; 913 }; 914 915 enum { 916 MLX5_FDB_TO_VPORT_REG_C_0 = 0x01, 917 MLX5_FDB_TO_VPORT_REG_C_1 = 0x02, 918 MLX5_FDB_TO_VPORT_REG_C_2 = 0x04, 919 MLX5_FDB_TO_VPORT_REG_C_3 = 0x08, 920 MLX5_FDB_TO_VPORT_REG_C_4 = 0x10, 921 MLX5_FDB_TO_VPORT_REG_C_5 = 0x20, 922 MLX5_FDB_TO_VPORT_REG_C_6 = 0x40, 923 MLX5_FDB_TO_VPORT_REG_C_7 = 0x80, 924 }; 925 926 struct mlx5_ifc_flow_table_eswitch_cap_bits { 927 u8 fdb_to_vport_reg_c_id[0x8]; 928 u8 reserved_at_8[0x5]; 929 u8 fdb_uplink_hairpin[0x1]; 930 u8 fdb_multi_path_any_table_limit_regc[0x1]; 931 u8 reserved_at_f[0x1]; 932 u8 fdb_dynamic_tunnel[0x1]; 933 u8 reserved_at_11[0x1]; 934 u8 fdb_multi_path_any_table[0x1]; 935 u8 reserved_at_13[0x2]; 936 u8 fdb_modify_header_fwd_to_table[0x1]; 937 u8 fdb_ipv4_ttl_modify[0x1]; 938 u8 flow_source[0x1]; 939 u8 reserved_at_18[0x2]; 940 u8 multi_fdb_encap[0x1]; 941 u8 egress_acl_forward_to_vport[0x1]; 942 u8 fdb_multi_path_to_table[0x1]; 943 u8 reserved_at_1d[0x3]; 944 945 u8 reserved_at_20[0x1e0]; 946 947 struct mlx5_ifc_flow_table_prop_layout_bits flow_table_properties_nic_esw_fdb; 948 949 struct mlx5_ifc_flow_table_prop_layout_bits flow_table_properties_esw_acl_ingress; 950 951 struct mlx5_ifc_flow_table_prop_layout_bits flow_table_properties_esw_acl_egress; 952 953 u8 reserved_at_800[0xC00]; 954 955 struct mlx5_ifc_flow_table_fields_supported_2_bits ft_field_support_2_esw_fdb; 956 957 struct mlx5_ifc_flow_table_fields_supported_2_bits ft_field_bitmask_support_2_esw_fdb; 958 959 u8 reserved_at_1500[0x300]; 960 961 u8 sw_steering_fdb_action_drop_icm_address_rx[0x40]; 962 963 u8 sw_steering_fdb_action_drop_icm_address_tx[0x40]; 964 965 u8 sw_steering_uplink_icm_address_rx[0x40]; 966 967 u8 sw_steering_uplink_icm_address_tx[0x40]; 968 969 u8 reserved_at_1900[0x6700]; 970 }; 971 972 struct mlx5_ifc_wqe_based_flow_table_cap_bits { 973 u8 reserved_at_0[0x3]; 974 u8 log_max_num_ste[0x5]; 975 u8 reserved_at_8[0x3]; 976 u8 log_max_num_stc[0x5]; 977 u8 reserved_at_10[0x3]; 978 u8 log_max_num_rtc[0x5]; 979 u8 reserved_at_18[0x3]; 980 u8 log_max_num_header_modify_pattern[0x5]; 981 982 u8 rtc_hash_split_table[0x1]; 983 u8 rtc_linear_lookup_table[0x1]; 984 u8 reserved_at_22[0x1]; 985 u8 stc_alloc_log_granularity[0x5]; 986 u8 reserved_at_28[0x3]; 987 u8 stc_alloc_log_max[0x5]; 988 u8 reserved_at_30[0x3]; 989 u8 ste_alloc_log_granularity[0x5]; 990 u8 reserved_at_38[0x3]; 991 u8 ste_alloc_log_max[0x5]; 992 993 u8 reserved_at_40[0xb]; 994 u8 rtc_reparse_mode[0x5]; 995 u8 reserved_at_50[0x3]; 996 u8 rtc_index_mode[0x5]; 997 u8 reserved_at_58[0x3]; 998 u8 rtc_log_depth_max[0x5]; 999 1000 u8 reserved_at_60[0x10]; 1001 u8 ste_format[0x10]; 1002 1003 u8 stc_action_type[0x80]; 1004 1005 u8 header_insert_type[0x10]; 1006 u8 header_remove_type[0x10]; 1007 1008 u8 trivial_match_definer[0x20]; 1009 1010 u8 reserved_at_140[0x1b]; 1011 u8 rtc_max_num_hash_definer_gen_wqe[0x5]; 1012 1013 u8 reserved_at_160[0x18]; 1014 u8 access_index_mode[0x8]; 1015 1016 u8 reserved_at_180[0x10]; 1017 u8 ste_format_gen_wqe[0x10]; 1018 1019 u8 linear_match_definer_reg_c3[0x20]; 1020 1021 u8 fdb_jump_to_tir_stc[0x1]; 1022 u8 reserved_at_1c1[0x1f]; 1023 }; 1024 1025 struct mlx5_ifc_esw_cap_bits { 1026 u8 reserved_at_0[0x1d]; 1027 u8 merged_eswitch[0x1]; 1028 u8 reserved_at_1e[0x2]; 1029 1030 u8 reserved_at_20[0x40]; 1031 1032 u8 esw_manager_vport_number_valid[0x1]; 1033 u8 reserved_at_61[0xf]; 1034 u8 esw_manager_vport_number[0x10]; 1035 1036 u8 reserved_at_80[0x780]; 1037 }; 1038 1039 enum { 1040 MLX5_COUNTER_SOURCE_ESWITCH = 0x0, 1041 MLX5_COUNTER_FLOW_ESWITCH = 0x1, 1042 }; 1043 1044 struct mlx5_ifc_e_switch_cap_bits { 1045 u8 vport_svlan_strip[0x1]; 1046 u8 vport_cvlan_strip[0x1]; 1047 u8 vport_svlan_insert[0x1]; 1048 u8 vport_cvlan_insert_if_not_exist[0x1]; 1049 u8 vport_cvlan_insert_overwrite[0x1]; 1050 u8 reserved_at_5[0x1]; 1051 u8 vport_cvlan_insert_always[0x1]; 1052 u8 esw_shared_ingress_acl[0x1]; 1053 u8 esw_uplink_ingress_acl[0x1]; 1054 u8 root_ft_on_other_esw[0x1]; 1055 u8 reserved_at_a[0xf]; 1056 u8 esw_functions_changed[0x1]; 1057 u8 reserved_at_1a[0x1]; 1058 u8 ecpf_vport_exists[0x1]; 1059 u8 counter_eswitch_affinity[0x1]; 1060 u8 merged_eswitch[0x1]; 1061 u8 nic_vport_node_guid_modify[0x1]; 1062 u8 nic_vport_port_guid_modify[0x1]; 1063 1064 u8 vxlan_encap_decap[0x1]; 1065 u8 nvgre_encap_decap[0x1]; 1066 u8 reserved_at_22[0x1]; 1067 u8 log_max_fdb_encap_uplink[0x5]; 1068 u8 reserved_at_21[0x3]; 1069 u8 log_max_packet_reformat_context[0x5]; 1070 u8 reserved_2b[0x6]; 1071 u8 max_encap_header_size[0xa]; 1072 1073 u8 reserved_at_40[0xb]; 1074 u8 log_max_esw_sf[0x5]; 1075 u8 esw_sf_base_id[0x10]; 1076 1077 u8 reserved_at_60[0x7a0]; 1078 1079 }; 1080 1081 struct mlx5_ifc_qos_cap_bits { 1082 u8 packet_pacing[0x1]; 1083 u8 esw_scheduling[0x1]; 1084 u8 esw_bw_share[0x1]; 1085 u8 esw_rate_limit[0x1]; 1086 u8 reserved_at_4[0x1]; 1087 u8 packet_pacing_burst_bound[0x1]; 1088 u8 packet_pacing_typical_size[0x1]; 1089 u8 reserved_at_7[0x1]; 1090 u8 nic_sq_scheduling[0x1]; 1091 u8 nic_bw_share[0x1]; 1092 u8 nic_rate_limit[0x1]; 1093 u8 packet_pacing_uid[0x1]; 1094 u8 log_esw_max_sched_depth[0x4]; 1095 u8 reserved_at_10[0x10]; 1096 1097 u8 reserved_at_20[0xb]; 1098 u8 log_max_qos_nic_queue_group[0x5]; 1099 u8 reserved_at_30[0x10]; 1100 1101 u8 packet_pacing_max_rate[0x20]; 1102 1103 u8 packet_pacing_min_rate[0x20]; 1104 1105 u8 reserved_at_80[0x10]; 1106 u8 packet_pacing_rate_table_size[0x10]; 1107 1108 u8 esw_element_type[0x10]; 1109 u8 esw_tsar_type[0x10]; 1110 1111 u8 reserved_at_c0[0x10]; 1112 u8 max_qos_para_vport[0x10]; 1113 1114 u8 max_tsar_bw_share[0x20]; 1115 1116 u8 reserved_at_100[0x20]; 1117 1118 u8 reserved_at_120[0x3]; 1119 u8 log_meter_aso_granularity[0x5]; 1120 u8 reserved_at_128[0x3]; 1121 u8 log_meter_aso_max_alloc[0x5]; 1122 u8 reserved_at_130[0x3]; 1123 u8 log_max_num_meter_aso[0x5]; 1124 u8 reserved_at_138[0x8]; 1125 1126 u8 reserved_at_140[0x6c0]; 1127 }; 1128 1129 struct mlx5_ifc_debug_cap_bits { 1130 u8 core_dump_general[0x1]; 1131 u8 core_dump_qp[0x1]; 1132 u8 reserved_at_2[0x7]; 1133 u8 resource_dump[0x1]; 1134 u8 reserved_at_a[0x16]; 1135 1136 u8 reserved_at_20[0x2]; 1137 u8 stall_detect[0x1]; 1138 u8 reserved_at_23[0x1d]; 1139 1140 u8 reserved_at_40[0x7c0]; 1141 }; 1142 1143 struct mlx5_ifc_per_protocol_networking_offload_caps_bits { 1144 u8 csum_cap[0x1]; 1145 u8 vlan_cap[0x1]; 1146 u8 lro_cap[0x1]; 1147 u8 lro_psh_flag[0x1]; 1148 u8 lro_time_stamp[0x1]; 1149 u8 reserved_at_5[0x2]; 1150 u8 wqe_vlan_insert[0x1]; 1151 u8 self_lb_en_modifiable[0x1]; 1152 u8 reserved_at_9[0x2]; 1153 u8 max_lso_cap[0x5]; 1154 u8 multi_pkt_send_wqe[0x2]; 1155 u8 wqe_inline_mode[0x2]; 1156 u8 rss_ind_tbl_cap[0x4]; 1157 u8 reg_umr_sq[0x1]; 1158 u8 scatter_fcs[0x1]; 1159 u8 enhanced_multi_pkt_send_wqe[0x1]; 1160 u8 tunnel_lso_const_out_ip_id[0x1]; 1161 u8 tunnel_lro_gre[0x1]; 1162 u8 tunnel_lro_vxlan[0x1]; 1163 u8 tunnel_stateless_gre[0x1]; 1164 u8 tunnel_stateless_vxlan[0x1]; 1165 1166 u8 swp[0x1]; 1167 u8 swp_csum[0x1]; 1168 u8 swp_lso[0x1]; 1169 u8 cqe_checksum_full[0x1]; 1170 u8 tunnel_stateless_geneve_tx[0x1]; 1171 u8 tunnel_stateless_mpls_over_udp[0x1]; 1172 u8 tunnel_stateless_mpls_over_gre[0x1]; 1173 u8 tunnel_stateless_vxlan_gpe[0x1]; 1174 u8 tunnel_stateless_ipv4_over_vxlan[0x1]; 1175 u8 tunnel_stateless_ip_over_ip[0x1]; 1176 u8 insert_trailer[0x1]; 1177 u8 reserved_at_2b[0x1]; 1178 u8 tunnel_stateless_ip_over_ip_rx[0x1]; 1179 u8 tunnel_stateless_ip_over_ip_tx[0x1]; 1180 u8 reserved_at_2e[0x2]; 1181 u8 max_vxlan_udp_ports[0x8]; 1182 u8 swp_csum_l4_partial[0x1]; 1183 u8 reserved_at_39[0x5]; 1184 u8 max_geneve_opt_len[0x1]; 1185 u8 tunnel_stateless_geneve_rx[0x1]; 1186 1187 u8 reserved_at_40[0x10]; 1188 u8 lro_min_mss_size[0x10]; 1189 1190 u8 reserved_at_60[0x120]; 1191 1192 u8 lro_timer_supported_periods[4][0x20]; 1193 1194 u8 reserved_at_200[0x600]; 1195 }; 1196 1197 enum { 1198 MLX5_TIMESTAMP_FORMAT_CAP_FREE_RUNNING = 0x0, 1199 MLX5_TIMESTAMP_FORMAT_CAP_REAL_TIME = 0x1, 1200 MLX5_TIMESTAMP_FORMAT_CAP_FREE_RUNNING_AND_REAL_TIME = 0x2, 1201 }; 1202 1203 struct mlx5_ifc_roce_cap_bits { 1204 u8 roce_apm[0x1]; 1205 u8 reserved_at_1[0x3]; 1206 u8 sw_r_roce_src_udp_port[0x1]; 1207 u8 fl_rc_qp_when_roce_disabled[0x1]; 1208 u8 fl_rc_qp_when_roce_enabled[0x1]; 1209 u8 roce_cc_general[0x1]; 1210 u8 qp_ooo_transmit_default[0x1]; 1211 u8 reserved_at_9[0x15]; 1212 u8 qp_ts_format[0x2]; 1213 1214 u8 reserved_at_20[0x60]; 1215 1216 u8 reserved_at_80[0xc]; 1217 u8 l3_type[0x4]; 1218 u8 reserved_at_90[0x8]; 1219 u8 roce_version[0x8]; 1220 1221 u8 reserved_at_a0[0x10]; 1222 u8 r_roce_dest_udp_port[0x10]; 1223 1224 u8 r_roce_max_src_udp_port[0x10]; 1225 u8 r_roce_min_src_udp_port[0x10]; 1226 1227 u8 reserved_at_e0[0x10]; 1228 u8 roce_address_table_size[0x10]; 1229 1230 u8 reserved_at_100[0x700]; 1231 }; 1232 1233 struct mlx5_ifc_sync_steering_in_bits { 1234 u8 opcode[0x10]; 1235 u8 uid[0x10]; 1236 1237 u8 reserved_at_20[0x10]; 1238 u8 op_mod[0x10]; 1239 1240 u8 reserved_at_40[0xc0]; 1241 }; 1242 1243 struct mlx5_ifc_sync_steering_out_bits { 1244 u8 status[0x8]; 1245 u8 reserved_at_8[0x18]; 1246 1247 u8 syndrome[0x20]; 1248 1249 u8 reserved_at_40[0x40]; 1250 }; 1251 1252 struct mlx5_ifc_sync_crypto_in_bits { 1253 u8 opcode[0x10]; 1254 u8 uid[0x10]; 1255 1256 u8 reserved_at_20[0x10]; 1257 u8 op_mod[0x10]; 1258 1259 u8 reserved_at_40[0x20]; 1260 1261 u8 reserved_at_60[0x10]; 1262 u8 crypto_type[0x10]; 1263 1264 u8 reserved_at_80[0x80]; 1265 }; 1266 1267 struct mlx5_ifc_sync_crypto_out_bits { 1268 u8 status[0x8]; 1269 u8 reserved_at_8[0x18]; 1270 1271 u8 syndrome[0x20]; 1272 1273 u8 reserved_at_40[0x40]; 1274 }; 1275 1276 struct mlx5_ifc_device_mem_cap_bits { 1277 u8 memic[0x1]; 1278 u8 reserved_at_1[0x1f]; 1279 1280 u8 reserved_at_20[0xb]; 1281 u8 log_min_memic_alloc_size[0x5]; 1282 u8 reserved_at_30[0x8]; 1283 u8 log_max_memic_addr_alignment[0x8]; 1284 1285 u8 memic_bar_start_addr[0x40]; 1286 1287 u8 memic_bar_size[0x20]; 1288 1289 u8 max_memic_size[0x20]; 1290 1291 u8 steering_sw_icm_start_address[0x40]; 1292 1293 u8 reserved_at_100[0x8]; 1294 u8 log_header_modify_sw_icm_size[0x8]; 1295 u8 reserved_at_110[0x2]; 1296 u8 log_sw_icm_alloc_granularity[0x6]; 1297 u8 log_steering_sw_icm_size[0x8]; 1298 1299 u8 log_indirect_encap_sw_icm_size[0x8]; 1300 u8 reserved_at_128[0x10]; 1301 u8 log_header_modify_pattern_sw_icm_size[0x8]; 1302 1303 u8 header_modify_sw_icm_start_address[0x40]; 1304 1305 u8 reserved_at_180[0x40]; 1306 1307 u8 header_modify_pattern_sw_icm_start_address[0x40]; 1308 1309 u8 memic_operations[0x20]; 1310 1311 u8 reserved_at_220[0x20]; 1312 1313 u8 indirect_encap_sw_icm_start_address[0x40]; 1314 1315 u8 reserved_at_280[0x580]; 1316 }; 1317 1318 struct mlx5_ifc_device_event_cap_bits { 1319 u8 user_affiliated_events[4][0x40]; 1320 1321 u8 user_unaffiliated_events[4][0x40]; 1322 }; 1323 1324 struct mlx5_ifc_virtio_emulation_cap_bits { 1325 u8 desc_tunnel_offload_type[0x1]; 1326 u8 eth_frame_offload_type[0x1]; 1327 u8 virtio_version_1_0[0x1]; 1328 u8 device_features_bits_mask[0xd]; 1329 u8 event_mode[0x8]; 1330 u8 virtio_queue_type[0x8]; 1331 1332 u8 max_tunnel_desc[0x10]; 1333 u8 reserved_at_30[0x3]; 1334 u8 log_doorbell_stride[0x5]; 1335 u8 reserved_at_38[0x3]; 1336 u8 log_doorbell_bar_size[0x5]; 1337 1338 u8 doorbell_bar_offset[0x40]; 1339 1340 u8 max_emulated_devices[0x8]; 1341 u8 max_num_virtio_queues[0x18]; 1342 1343 u8 reserved_at_a0[0x20]; 1344 1345 u8 reserved_at_c0[0x13]; 1346 u8 desc_group_mkey_supported[0x1]; 1347 u8 freeze_to_rdy_supported[0x1]; 1348 u8 reserved_at_d5[0xb]; 1349 1350 u8 reserved_at_e0[0x20]; 1351 1352 u8 umem_1_buffer_param_a[0x20]; 1353 1354 u8 umem_1_buffer_param_b[0x20]; 1355 1356 u8 umem_2_buffer_param_a[0x20]; 1357 1358 u8 umem_2_buffer_param_b[0x20]; 1359 1360 u8 umem_3_buffer_param_a[0x20]; 1361 1362 u8 umem_3_buffer_param_b[0x20]; 1363 1364 u8 reserved_at_1c0[0x640]; 1365 }; 1366 1367 enum { 1368 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_QP_1_BYTE = 0x0, 1369 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_QP_2_BYTES = 0x2, 1370 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_QP_4_BYTES = 0x4, 1371 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_QP_8_BYTES = 0x8, 1372 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_QP_16_BYTES = 0x10, 1373 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_QP_32_BYTES = 0x20, 1374 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_QP_64_BYTES = 0x40, 1375 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_QP_128_BYTES = 0x80, 1376 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_QP_256_BYTES = 0x100, 1377 }; 1378 1379 enum { 1380 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_DC_1_BYTE = 0x1, 1381 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_DC_2_BYTES = 0x2, 1382 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_DC_4_BYTES = 0x4, 1383 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_DC_8_BYTES = 0x8, 1384 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_DC_16_BYTES = 0x10, 1385 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_DC_32_BYTES = 0x20, 1386 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_DC_64_BYTES = 0x40, 1387 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_DC_128_BYTES = 0x80, 1388 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_DC_256_BYTES = 0x100, 1389 }; 1390 1391 struct mlx5_ifc_atomic_caps_bits { 1392 u8 reserved_at_0[0x40]; 1393 1394 u8 atomic_req_8B_endianness_mode[0x2]; 1395 u8 reserved_at_42[0x4]; 1396 u8 supported_atomic_req_8B_endianness_mode_1[0x1]; 1397 1398 u8 reserved_at_47[0x19]; 1399 1400 u8 reserved_at_60[0x20]; 1401 1402 u8 reserved_at_80[0x10]; 1403 u8 atomic_operations[0x10]; 1404 1405 u8 reserved_at_a0[0x10]; 1406 u8 atomic_size_qp[0x10]; 1407 1408 u8 reserved_at_c0[0x10]; 1409 u8 atomic_size_dc[0x10]; 1410 1411 u8 reserved_at_e0[0x720]; 1412 }; 1413 1414 struct mlx5_ifc_odp_cap_bits { 1415 u8 reserved_at_0[0x40]; 1416 1417 u8 sig[0x1]; 1418 u8 reserved_at_41[0x1f]; 1419 1420 u8 reserved_at_60[0x20]; 1421 1422 struct mlx5_ifc_odp_per_transport_service_cap_bits rc_odp_caps; 1423 1424 struct mlx5_ifc_odp_per_transport_service_cap_bits uc_odp_caps; 1425 1426 struct mlx5_ifc_odp_per_transport_service_cap_bits ud_odp_caps; 1427 1428 struct mlx5_ifc_odp_per_transport_service_cap_bits xrc_odp_caps; 1429 1430 struct mlx5_ifc_odp_per_transport_service_cap_bits dc_odp_caps; 1431 1432 u8 reserved_at_120[0x6E0]; 1433 }; 1434 1435 struct mlx5_ifc_tls_cap_bits { 1436 u8 tls_1_2_aes_gcm_128[0x1]; 1437 u8 tls_1_3_aes_gcm_128[0x1]; 1438 u8 tls_1_2_aes_gcm_256[0x1]; 1439 u8 tls_1_3_aes_gcm_256[0x1]; 1440 u8 reserved_at_4[0x1c]; 1441 1442 u8 reserved_at_20[0x7e0]; 1443 }; 1444 1445 struct mlx5_ifc_ipsec_cap_bits { 1446 u8 ipsec_full_offload[0x1]; 1447 u8 ipsec_crypto_offload[0x1]; 1448 u8 ipsec_esn[0x1]; 1449 u8 ipsec_crypto_esp_aes_gcm_256_encrypt[0x1]; 1450 u8 ipsec_crypto_esp_aes_gcm_128_encrypt[0x1]; 1451 u8 ipsec_crypto_esp_aes_gcm_256_decrypt[0x1]; 1452 u8 ipsec_crypto_esp_aes_gcm_128_decrypt[0x1]; 1453 u8 reserved_at_7[0x4]; 1454 u8 log_max_ipsec_offload[0x5]; 1455 u8 reserved_at_10[0x10]; 1456 1457 u8 min_log_ipsec_full_replay_window[0x8]; 1458 u8 max_log_ipsec_full_replay_window[0x8]; 1459 u8 reserved_at_30[0x7d0]; 1460 }; 1461 1462 struct mlx5_ifc_macsec_cap_bits { 1463 u8 macsec_epn[0x1]; 1464 u8 reserved_at_1[0x2]; 1465 u8 macsec_crypto_esp_aes_gcm_256_encrypt[0x1]; 1466 u8 macsec_crypto_esp_aes_gcm_128_encrypt[0x1]; 1467 u8 macsec_crypto_esp_aes_gcm_256_decrypt[0x1]; 1468 u8 macsec_crypto_esp_aes_gcm_128_decrypt[0x1]; 1469 u8 reserved_at_7[0x4]; 1470 u8 log_max_macsec_offload[0x5]; 1471 u8 reserved_at_10[0x10]; 1472 1473 u8 min_log_macsec_full_replay_window[0x8]; 1474 u8 max_log_macsec_full_replay_window[0x8]; 1475 u8 reserved_at_30[0x10]; 1476 1477 u8 reserved_at_40[0x7c0]; 1478 }; 1479 1480 enum { 1481 MLX5_WQ_TYPE_LINKED_LIST = 0x0, 1482 MLX5_WQ_TYPE_CYCLIC = 0x1, 1483 MLX5_WQ_TYPE_LINKED_LIST_STRIDING_RQ = 0x2, 1484 MLX5_WQ_TYPE_CYCLIC_STRIDING_RQ = 0x3, 1485 }; 1486 1487 enum { 1488 MLX5_WQ_END_PAD_MODE_NONE = 0x0, 1489 MLX5_WQ_END_PAD_MODE_ALIGN = 0x1, 1490 }; 1491 1492 enum { 1493 MLX5_CMD_HCA_CAP_GID_TABLE_SIZE_8_GID_ENTRIES = 0x0, 1494 MLX5_CMD_HCA_CAP_GID_TABLE_SIZE_16_GID_ENTRIES = 0x1, 1495 MLX5_CMD_HCA_CAP_GID_TABLE_SIZE_32_GID_ENTRIES = 0x2, 1496 MLX5_CMD_HCA_CAP_GID_TABLE_SIZE_64_GID_ENTRIES = 0x3, 1497 MLX5_CMD_HCA_CAP_GID_TABLE_SIZE_128_GID_ENTRIES = 0x4, 1498 }; 1499 1500 enum { 1501 MLX5_CMD_HCA_CAP_PKEY_TABLE_SIZE_128_ENTRIES = 0x0, 1502 MLX5_CMD_HCA_CAP_PKEY_TABLE_SIZE_256_ENTRIES = 0x1, 1503 MLX5_CMD_HCA_CAP_PKEY_TABLE_SIZE_512_ENTRIES = 0x2, 1504 MLX5_CMD_HCA_CAP_PKEY_TABLE_SIZE_1K_ENTRIES = 0x3, 1505 MLX5_CMD_HCA_CAP_PKEY_TABLE_SIZE_2K_ENTRIES = 0x4, 1506 MLX5_CMD_HCA_CAP_PKEY_TABLE_SIZE_4K_ENTRIES = 0x5, 1507 }; 1508 1509 enum { 1510 MLX5_CMD_HCA_CAP_PORT_TYPE_IB = 0x0, 1511 MLX5_CMD_HCA_CAP_PORT_TYPE_ETHERNET = 0x1, 1512 }; 1513 1514 enum { 1515 MLX5_CMD_HCA_CAP_CMDIF_CHECKSUM_DISABLED = 0x0, 1516 MLX5_CMD_HCA_CAP_CMDIF_CHECKSUM_INITIAL_STATE = 0x1, 1517 MLX5_CMD_HCA_CAP_CMDIF_CHECKSUM_ENABLED = 0x3, 1518 }; 1519 1520 enum { 1521 MLX5_CAP_PORT_TYPE_IB = 0x0, 1522 MLX5_CAP_PORT_TYPE_ETH = 0x1, 1523 }; 1524 1525 enum { 1526 MLX5_CAP_UMR_FENCE_STRONG = 0x0, 1527 MLX5_CAP_UMR_FENCE_SMALL = 0x1, 1528 MLX5_CAP_UMR_FENCE_NONE = 0x2, 1529 }; 1530 1531 enum { 1532 MLX5_FLEX_IPV4_OVER_VXLAN_ENABLED = 1 << 0, 1533 MLX5_FLEX_IPV6_OVER_VXLAN_ENABLED = 1 << 1, 1534 MLX5_FLEX_IPV6_OVER_IP_ENABLED = 1 << 2, 1535 MLX5_FLEX_PARSER_GENEVE_ENABLED = 1 << 3, 1536 MLX5_FLEX_PARSER_MPLS_OVER_GRE_ENABLED = 1 << 4, 1537 MLX5_FLEX_PARSER_MPLS_OVER_UDP_ENABLED = 1 << 5, 1538 MLX5_FLEX_P_BIT_VXLAN_GPE_ENABLED = 1 << 6, 1539 MLX5_FLEX_PARSER_VXLAN_GPE_ENABLED = 1 << 7, 1540 MLX5_FLEX_PARSER_ICMP_V4_ENABLED = 1 << 8, 1541 MLX5_FLEX_PARSER_ICMP_V6_ENABLED = 1 << 9, 1542 MLX5_FLEX_PARSER_GENEVE_TLV_OPTION_0_ENABLED = 1 << 10, 1543 MLX5_FLEX_PARSER_GTPU_ENABLED = 1 << 11, 1544 MLX5_FLEX_PARSER_GTPU_DW_2_ENABLED = 1 << 16, 1545 MLX5_FLEX_PARSER_GTPU_FIRST_EXT_DW_0_ENABLED = 1 << 17, 1546 MLX5_FLEX_PARSER_GTPU_DW_0_ENABLED = 1 << 18, 1547 MLX5_FLEX_PARSER_GTPU_TEID_ENABLED = 1 << 19, 1548 }; 1549 1550 enum { 1551 MLX5_UCTX_CAP_RAW_TX = 1UL << 0, 1552 MLX5_UCTX_CAP_INTERNAL_DEV_RES = 1UL << 1, 1553 }; 1554 1555 #define MLX5_FC_BULK_SIZE_FACTOR 128 1556 1557 enum mlx5_fc_bulk_alloc_bitmask { 1558 MLX5_FC_BULK_128 = (1 << 0), 1559 MLX5_FC_BULK_256 = (1 << 1), 1560 MLX5_FC_BULK_512 = (1 << 2), 1561 MLX5_FC_BULK_1024 = (1 << 3), 1562 MLX5_FC_BULK_2048 = (1 << 4), 1563 MLX5_FC_BULK_4096 = (1 << 5), 1564 MLX5_FC_BULK_8192 = (1 << 6), 1565 MLX5_FC_BULK_16384 = (1 << 7), 1566 }; 1567 1568 #define MLX5_FC_BULK_NUM_FCS(fc_enum) (MLX5_FC_BULK_SIZE_FACTOR * (fc_enum)) 1569 1570 #define MLX5_FT_MAX_MULTIPATH_LEVEL 63 1571 1572 enum { 1573 MLX5_STEERING_FORMAT_CONNECTX_5 = 0, 1574 MLX5_STEERING_FORMAT_CONNECTX_6DX = 1, 1575 MLX5_STEERING_FORMAT_CONNECTX_7 = 2, 1576 }; 1577 1578 struct mlx5_ifc_cmd_hca_cap_bits { 1579 u8 reserved_at_0[0x6]; 1580 u8 page_request_disable[0x1]; 1581 u8 reserved_at_7[0x9]; 1582 u8 shared_object_to_user_object_allowed[0x1]; 1583 u8 reserved_at_13[0xe]; 1584 u8 vhca_resource_manager[0x1]; 1585 1586 u8 hca_cap_2[0x1]; 1587 u8 create_lag_when_not_master_up[0x1]; 1588 u8 dtor[0x1]; 1589 u8 event_on_vhca_state_teardown_request[0x1]; 1590 u8 event_on_vhca_state_in_use[0x1]; 1591 u8 event_on_vhca_state_active[0x1]; 1592 u8 event_on_vhca_state_allocated[0x1]; 1593 u8 event_on_vhca_state_invalid[0x1]; 1594 u8 reserved_at_28[0x8]; 1595 u8 vhca_id[0x10]; 1596 1597 u8 reserved_at_40[0x40]; 1598 1599 u8 log_max_srq_sz[0x8]; 1600 u8 log_max_qp_sz[0x8]; 1601 u8 event_cap[0x1]; 1602 u8 reserved_at_91[0x2]; 1603 u8 isolate_vl_tc_new[0x1]; 1604 u8 reserved_at_94[0x4]; 1605 u8 prio_tag_required[0x1]; 1606 u8 reserved_at_99[0x2]; 1607 u8 log_max_qp[0x5]; 1608 1609 u8 reserved_at_a0[0x3]; 1610 u8 ece_support[0x1]; 1611 u8 reserved_at_a4[0x5]; 1612 u8 reg_c_preserve[0x1]; 1613 u8 reserved_at_aa[0x1]; 1614 u8 log_max_srq[0x5]; 1615 u8 reserved_at_b0[0x1]; 1616 u8 uplink_follow[0x1]; 1617 u8 ts_cqe_to_dest_cqn[0x1]; 1618 u8 reserved_at_b3[0x6]; 1619 u8 go_back_n[0x1]; 1620 u8 reserved_at_ba[0x6]; 1621 1622 u8 max_sgl_for_optimized_performance[0x8]; 1623 u8 log_max_cq_sz[0x8]; 1624 u8 relaxed_ordering_write_umr[0x1]; 1625 u8 relaxed_ordering_read_umr[0x1]; 1626 u8 reserved_at_d2[0x7]; 1627 u8 virtio_net_device_emualtion_manager[0x1]; 1628 u8 virtio_blk_device_emualtion_manager[0x1]; 1629 u8 log_max_cq[0x5]; 1630 1631 u8 log_max_eq_sz[0x8]; 1632 u8 relaxed_ordering_write[0x1]; 1633 u8 relaxed_ordering_read_pci_enabled[0x1]; 1634 u8 log_max_mkey[0x6]; 1635 u8 reserved_at_f0[0x6]; 1636 u8 terminate_scatter_list_mkey[0x1]; 1637 u8 repeated_mkey[0x1]; 1638 u8 dump_fill_mkey[0x1]; 1639 u8 reserved_at_f9[0x2]; 1640 u8 fast_teardown[0x1]; 1641 u8 log_max_eq[0x4]; 1642 1643 u8 max_indirection[0x8]; 1644 u8 fixed_buffer_size[0x1]; 1645 u8 log_max_mrw_sz[0x7]; 1646 u8 force_teardown[0x1]; 1647 u8 reserved_at_111[0x1]; 1648 u8 log_max_bsf_list_size[0x6]; 1649 u8 umr_extended_translation_offset[0x1]; 1650 u8 null_mkey[0x1]; 1651 u8 log_max_klm_list_size[0x6]; 1652 1653 u8 reserved_at_120[0x2]; 1654 u8 qpc_extension[0x1]; 1655 u8 reserved_at_123[0x7]; 1656 u8 log_max_ra_req_dc[0x6]; 1657 u8 reserved_at_130[0x2]; 1658 u8 eth_wqe_too_small[0x1]; 1659 u8 reserved_at_133[0x6]; 1660 u8 vnic_env_cq_overrun[0x1]; 1661 u8 log_max_ra_res_dc[0x6]; 1662 1663 u8 reserved_at_140[0x5]; 1664 u8 release_all_pages[0x1]; 1665 u8 must_not_use[0x1]; 1666 u8 reserved_at_147[0x2]; 1667 u8 roce_accl[0x1]; 1668 u8 log_max_ra_req_qp[0x6]; 1669 u8 reserved_at_150[0xa]; 1670 u8 log_max_ra_res_qp[0x6]; 1671 1672 u8 end_pad[0x1]; 1673 u8 cc_query_allowed[0x1]; 1674 u8 cc_modify_allowed[0x1]; 1675 u8 start_pad[0x1]; 1676 u8 cache_line_128byte[0x1]; 1677 u8 reserved_at_165[0x4]; 1678 u8 rts2rts_qp_counters_set_id[0x1]; 1679 u8 reserved_at_16a[0x2]; 1680 u8 vnic_env_int_rq_oob[0x1]; 1681 u8 sbcam_reg[0x1]; 1682 u8 reserved_at_16e[0x1]; 1683 u8 qcam_reg[0x1]; 1684 u8 gid_table_size[0x10]; 1685 1686 u8 out_of_seq_cnt[0x1]; 1687 u8 vport_counters[0x1]; 1688 u8 retransmission_q_counters[0x1]; 1689 u8 debug[0x1]; 1690 u8 modify_rq_counter_set_id[0x1]; 1691 u8 rq_delay_drop[0x1]; 1692 u8 max_qp_cnt[0xa]; 1693 u8 pkey_table_size[0x10]; 1694 1695 u8 vport_group_manager[0x1]; 1696 u8 vhca_group_manager[0x1]; 1697 u8 ib_virt[0x1]; 1698 u8 eth_virt[0x1]; 1699 u8 vnic_env_queue_counters[0x1]; 1700 u8 ets[0x1]; 1701 u8 nic_flow_table[0x1]; 1702 u8 eswitch_manager[0x1]; 1703 u8 device_memory[0x1]; 1704 u8 mcam_reg[0x1]; 1705 u8 pcam_reg[0x1]; 1706 u8 local_ca_ack_delay[0x5]; 1707 u8 port_module_event[0x1]; 1708 u8 enhanced_error_q_counters[0x1]; 1709 u8 ports_check[0x1]; 1710 u8 reserved_at_1b3[0x1]; 1711 u8 disable_link_up[0x1]; 1712 u8 beacon_led[0x1]; 1713 u8 port_type[0x2]; 1714 u8 num_ports[0x8]; 1715 1716 u8 reserved_at_1c0[0x1]; 1717 u8 pps[0x1]; 1718 u8 pps_modify[0x1]; 1719 u8 log_max_msg[0x5]; 1720 u8 reserved_at_1c8[0x4]; 1721 u8 max_tc[0x4]; 1722 u8 temp_warn_event[0x1]; 1723 u8 dcbx[0x1]; 1724 u8 general_notification_event[0x1]; 1725 u8 reserved_at_1d3[0x2]; 1726 u8 fpga[0x1]; 1727 u8 rol_s[0x1]; 1728 u8 rol_g[0x1]; 1729 u8 reserved_at_1d8[0x1]; 1730 u8 wol_s[0x1]; 1731 u8 wol_g[0x1]; 1732 u8 wol_a[0x1]; 1733 u8 wol_b[0x1]; 1734 u8 wol_m[0x1]; 1735 u8 wol_u[0x1]; 1736 u8 wol_p[0x1]; 1737 1738 u8 stat_rate_support[0x10]; 1739 u8 reserved_at_1f0[0x1]; 1740 u8 pci_sync_for_fw_update_event[0x1]; 1741 u8 reserved_at_1f2[0x6]; 1742 u8 init2_lag_tx_port_affinity[0x1]; 1743 u8 reserved_at_1fa[0x2]; 1744 u8 wqe_based_flow_table_update_cap[0x1]; 1745 u8 cqe_version[0x4]; 1746 1747 u8 compact_address_vector[0x1]; 1748 u8 striding_rq[0x1]; 1749 u8 reserved_at_202[0x1]; 1750 u8 ipoib_enhanced_offloads[0x1]; 1751 u8 ipoib_basic_offloads[0x1]; 1752 u8 reserved_at_205[0x1]; 1753 u8 repeated_block_disabled[0x1]; 1754 u8 umr_modify_entity_size_disabled[0x1]; 1755 u8 umr_modify_atomic_disabled[0x1]; 1756 u8 umr_indirect_mkey_disabled[0x1]; 1757 u8 umr_fence[0x2]; 1758 u8 dc_req_scat_data_cqe[0x1]; 1759 u8 reserved_at_20d[0x2]; 1760 u8 drain_sigerr[0x1]; 1761 u8 cmdif_checksum[0x2]; 1762 u8 sigerr_cqe[0x1]; 1763 u8 reserved_at_213[0x1]; 1764 u8 wq_signature[0x1]; 1765 u8 sctr_data_cqe[0x1]; 1766 u8 reserved_at_216[0x1]; 1767 u8 sho[0x1]; 1768 u8 tph[0x1]; 1769 u8 rf[0x1]; 1770 u8 dct[0x1]; 1771 u8 qos[0x1]; 1772 u8 eth_net_offloads[0x1]; 1773 u8 roce[0x1]; 1774 u8 atomic[0x1]; 1775 u8 reserved_at_21f[0x1]; 1776 1777 u8 cq_oi[0x1]; 1778 u8 cq_resize[0x1]; 1779 u8 cq_moderation[0x1]; 1780 u8 cq_period_mode_modify[0x1]; 1781 u8 reserved_at_224[0x2]; 1782 u8 cq_eq_remap[0x1]; 1783 u8 pg[0x1]; 1784 u8 block_lb_mc[0x1]; 1785 u8 reserved_at_229[0x1]; 1786 u8 scqe_break_moderation[0x1]; 1787 u8 cq_period_start_from_cqe[0x1]; 1788 u8 cd[0x1]; 1789 u8 reserved_at_22d[0x1]; 1790 u8 apm[0x1]; 1791 u8 vector_calc[0x1]; 1792 u8 umr_ptr_rlky[0x1]; 1793 u8 imaicl[0x1]; 1794 u8 qp_packet_based[0x1]; 1795 u8 reserved_at_233[0x3]; 1796 u8 qkv[0x1]; 1797 u8 pkv[0x1]; 1798 u8 set_deth_sqpn[0x1]; 1799 u8 reserved_at_239[0x3]; 1800 u8 xrc[0x1]; 1801 u8 ud[0x1]; 1802 u8 uc[0x1]; 1803 u8 rc[0x1]; 1804 1805 u8 uar_4k[0x1]; 1806 u8 reserved_at_241[0x7]; 1807 u8 fl_rc_qp_when_roce_disabled[0x1]; 1808 u8 regexp_params[0x1]; 1809 u8 uar_sz[0x6]; 1810 u8 port_selection_cap[0x1]; 1811 u8 reserved_at_251[0x1]; 1812 u8 umem_uid_0[0x1]; 1813 u8 reserved_at_253[0x5]; 1814 u8 log_pg_sz[0x8]; 1815 1816 u8 bf[0x1]; 1817 u8 driver_version[0x1]; 1818 u8 pad_tx_eth_packet[0x1]; 1819 u8 reserved_at_263[0x3]; 1820 u8 mkey_by_name[0x1]; 1821 u8 reserved_at_267[0x4]; 1822 1823 u8 log_bf_reg_size[0x5]; 1824 1825 u8 reserved_at_270[0x3]; 1826 u8 qp_error_syndrome[0x1]; 1827 u8 reserved_at_274[0x2]; 1828 u8 lag_dct[0x2]; 1829 u8 lag_tx_port_affinity[0x1]; 1830 u8 lag_native_fdb_selection[0x1]; 1831 u8 reserved_at_27a[0x1]; 1832 u8 lag_master[0x1]; 1833 u8 num_lag_ports[0x4]; 1834 1835 u8 reserved_at_280[0x10]; 1836 u8 max_wqe_sz_sq[0x10]; 1837 1838 u8 reserved_at_2a0[0xb]; 1839 u8 shampo[0x1]; 1840 u8 reserved_at_2ac[0x4]; 1841 u8 max_wqe_sz_rq[0x10]; 1842 1843 u8 max_flow_counter_31_16[0x10]; 1844 u8 max_wqe_sz_sq_dc[0x10]; 1845 1846 u8 reserved_at_2e0[0x7]; 1847 u8 max_qp_mcg[0x19]; 1848 1849 u8 reserved_at_300[0x10]; 1850 u8 flow_counter_bulk_alloc[0x8]; 1851 u8 log_max_mcg[0x8]; 1852 1853 u8 reserved_at_320[0x3]; 1854 u8 log_max_transport_domain[0x5]; 1855 u8 reserved_at_328[0x2]; 1856 u8 relaxed_ordering_read[0x1]; 1857 u8 log_max_pd[0x5]; 1858 u8 reserved_at_330[0x6]; 1859 u8 pci_sync_for_fw_update_with_driver_unload[0x1]; 1860 u8 vnic_env_cnt_steering_fail[0x1]; 1861 u8 vport_counter_local_loopback[0x1]; 1862 u8 q_counter_aggregation[0x1]; 1863 u8 q_counter_other_vport[0x1]; 1864 u8 log_max_xrcd[0x5]; 1865 1866 u8 nic_receive_steering_discard[0x1]; 1867 u8 receive_discard_vport_down[0x1]; 1868 u8 transmit_discard_vport_down[0x1]; 1869 u8 eq_overrun_count[0x1]; 1870 u8 reserved_at_344[0x1]; 1871 u8 invalid_command_count[0x1]; 1872 u8 quota_exceeded_count[0x1]; 1873 u8 reserved_at_347[0x1]; 1874 u8 log_max_flow_counter_bulk[0x8]; 1875 u8 max_flow_counter_15_0[0x10]; 1876 1877 1878 u8 reserved_at_360[0x3]; 1879 u8 log_max_rq[0x5]; 1880 u8 reserved_at_368[0x3]; 1881 u8 log_max_sq[0x5]; 1882 u8 reserved_at_370[0x3]; 1883 u8 log_max_tir[0x5]; 1884 u8 reserved_at_378[0x3]; 1885 u8 log_max_tis[0x5]; 1886 1887 u8 basic_cyclic_rcv_wqe[0x1]; 1888 u8 reserved_at_381[0x2]; 1889 u8 log_max_rmp[0x5]; 1890 u8 reserved_at_388[0x3]; 1891 u8 log_max_rqt[0x5]; 1892 u8 reserved_at_390[0x3]; 1893 u8 log_max_rqt_size[0x5]; 1894 u8 reserved_at_398[0x3]; 1895 u8 log_max_tis_per_sq[0x5]; 1896 1897 u8 ext_stride_num_range[0x1]; 1898 u8 roce_rw_supported[0x1]; 1899 u8 log_max_current_uc_list_wr_supported[0x1]; 1900 u8 log_max_stride_sz_rq[0x5]; 1901 u8 reserved_at_3a8[0x3]; 1902 u8 log_min_stride_sz_rq[0x5]; 1903 u8 reserved_at_3b0[0x3]; 1904 u8 log_max_stride_sz_sq[0x5]; 1905 u8 reserved_at_3b8[0x3]; 1906 u8 log_min_stride_sz_sq[0x5]; 1907 1908 u8 hairpin[0x1]; 1909 u8 reserved_at_3c1[0x2]; 1910 u8 log_max_hairpin_queues[0x5]; 1911 u8 reserved_at_3c8[0x3]; 1912 u8 log_max_hairpin_wq_data_sz[0x5]; 1913 u8 reserved_at_3d0[0x3]; 1914 u8 log_max_hairpin_num_packets[0x5]; 1915 u8 reserved_at_3d8[0x3]; 1916 u8 log_max_wq_sz[0x5]; 1917 1918 u8 nic_vport_change_event[0x1]; 1919 u8 disable_local_lb_uc[0x1]; 1920 u8 disable_local_lb_mc[0x1]; 1921 u8 log_min_hairpin_wq_data_sz[0x5]; 1922 u8 reserved_at_3e8[0x1]; 1923 u8 silent_mode[0x1]; 1924 u8 vhca_state[0x1]; 1925 u8 log_max_vlan_list[0x5]; 1926 u8 reserved_at_3f0[0x3]; 1927 u8 log_max_current_mc_list[0x5]; 1928 u8 reserved_at_3f8[0x3]; 1929 u8 log_max_current_uc_list[0x5]; 1930 1931 u8 general_obj_types[0x40]; 1932 1933 u8 sq_ts_format[0x2]; 1934 u8 rq_ts_format[0x2]; 1935 u8 steering_format_version[0x4]; 1936 u8 create_qp_start_hint[0x18]; 1937 1938 u8 reserved_at_460[0x1]; 1939 u8 ats[0x1]; 1940 u8 cross_vhca_rqt[0x1]; 1941 u8 log_max_uctx[0x5]; 1942 u8 reserved_at_468[0x1]; 1943 u8 crypto[0x1]; 1944 u8 ipsec_offload[0x1]; 1945 u8 log_max_umem[0x5]; 1946 u8 max_num_eqs[0x10]; 1947 1948 u8 reserved_at_480[0x1]; 1949 u8 tls_tx[0x1]; 1950 u8 tls_rx[0x1]; 1951 u8 log_max_l2_table[0x5]; 1952 u8 reserved_at_488[0x8]; 1953 u8 log_uar_page_sz[0x10]; 1954 1955 u8 reserved_at_4a0[0x20]; 1956 u8 device_frequency_mhz[0x20]; 1957 u8 device_frequency_khz[0x20]; 1958 1959 u8 reserved_at_500[0x20]; 1960 u8 num_of_uars_per_page[0x20]; 1961 1962 u8 flex_parser_protocols[0x20]; 1963 1964 u8 max_geneve_tlv_options[0x8]; 1965 u8 reserved_at_568[0x3]; 1966 u8 max_geneve_tlv_option_data_len[0x5]; 1967 u8 reserved_at_570[0x9]; 1968 u8 adv_virtualization[0x1]; 1969 u8 reserved_at_57a[0x6]; 1970 1971 u8 reserved_at_580[0xb]; 1972 u8 log_max_dci_stream_channels[0x5]; 1973 u8 reserved_at_590[0x3]; 1974 u8 log_max_dci_errored_streams[0x5]; 1975 u8 reserved_at_598[0x8]; 1976 1977 u8 reserved_at_5a0[0x10]; 1978 u8 enhanced_cqe_compression[0x1]; 1979 u8 reserved_at_5b1[0x2]; 1980 u8 log_max_dek[0x5]; 1981 u8 reserved_at_5b8[0x4]; 1982 u8 mini_cqe_resp_stride_index[0x1]; 1983 u8 cqe_128_always[0x1]; 1984 u8 cqe_compression_128[0x1]; 1985 u8 cqe_compression[0x1]; 1986 1987 u8 cqe_compression_timeout[0x10]; 1988 u8 cqe_compression_max_num[0x10]; 1989 1990 u8 reserved_at_5e0[0x8]; 1991 u8 flex_parser_id_gtpu_dw_0[0x4]; 1992 u8 reserved_at_5ec[0x4]; 1993 u8 tag_matching[0x1]; 1994 u8 rndv_offload_rc[0x1]; 1995 u8 rndv_offload_dc[0x1]; 1996 u8 log_tag_matching_list_sz[0x5]; 1997 u8 reserved_at_5f8[0x3]; 1998 u8 log_max_xrq[0x5]; 1999 2000 u8 affiliate_nic_vport_criteria[0x8]; 2001 u8 native_port_num[0x8]; 2002 u8 num_vhca_ports[0x8]; 2003 u8 flex_parser_id_gtpu_teid[0x4]; 2004 u8 reserved_at_61c[0x2]; 2005 u8 sw_owner_id[0x1]; 2006 u8 reserved_at_61f[0x1]; 2007 2008 u8 max_num_of_monitor_counters[0x10]; 2009 u8 num_ppcnt_monitor_counters[0x10]; 2010 2011 u8 max_num_sf[0x10]; 2012 u8 num_q_monitor_counters[0x10]; 2013 2014 u8 reserved_at_660[0x20]; 2015 2016 u8 sf[0x1]; 2017 u8 sf_set_partition[0x1]; 2018 u8 reserved_at_682[0x1]; 2019 u8 log_max_sf[0x5]; 2020 u8 apu[0x1]; 2021 u8 reserved_at_689[0x4]; 2022 u8 migration[0x1]; 2023 u8 reserved_at_68e[0x2]; 2024 u8 log_min_sf_size[0x8]; 2025 u8 max_num_sf_partitions[0x8]; 2026 2027 u8 uctx_cap[0x20]; 2028 2029 u8 reserved_at_6c0[0x4]; 2030 u8 flex_parser_id_geneve_tlv_option_0[0x4]; 2031 u8 flex_parser_id_icmp_dw1[0x4]; 2032 u8 flex_parser_id_icmp_dw0[0x4]; 2033 u8 flex_parser_id_icmpv6_dw1[0x4]; 2034 u8 flex_parser_id_icmpv6_dw0[0x4]; 2035 u8 flex_parser_id_outer_first_mpls_over_gre[0x4]; 2036 u8 flex_parser_id_outer_first_mpls_over_udp_label[0x4]; 2037 2038 u8 max_num_match_definer[0x10]; 2039 u8 sf_base_id[0x10]; 2040 2041 u8 flex_parser_id_gtpu_dw_2[0x4]; 2042 u8 flex_parser_id_gtpu_first_ext_dw_0[0x4]; 2043 u8 num_total_dynamic_vf_msix[0x18]; 2044 u8 reserved_at_720[0x14]; 2045 u8 dynamic_msix_table_size[0xc]; 2046 u8 reserved_at_740[0xc]; 2047 u8 min_dynamic_vf_msix_table_size[0x4]; 2048 u8 reserved_at_750[0x4]; 2049 u8 max_dynamic_vf_msix_table_size[0xc]; 2050 2051 u8 reserved_at_760[0x3]; 2052 u8 log_max_num_header_modify_argument[0x5]; 2053 u8 log_header_modify_argument_granularity_offset[0x4]; 2054 u8 log_header_modify_argument_granularity[0x4]; 2055 u8 reserved_at_770[0x3]; 2056 u8 log_header_modify_argument_max_alloc[0x5]; 2057 u8 reserved_at_778[0x8]; 2058 2059 u8 vhca_tunnel_commands[0x40]; 2060 u8 match_definer_format_supported[0x40]; 2061 }; 2062 2063 enum { 2064 MLX5_CROSS_VHCA_OBJ_TO_OBJ_SUPPORTED_LOCAL_FLOW_TABLE_TO_REMOTE_FLOW_TABLE_MISS = 0x80000, 2065 MLX5_CROSS_VHCA_OBJ_TO_OBJ_SUPPORTED_LOCAL_FLOW_TABLE_ROOT_TO_REMOTE_FLOW_TABLE = (1ULL << 20), 2066 }; 2067 2068 enum { 2069 MLX5_ALLOWED_OBJ_FOR_OTHER_VHCA_ACCESS_FLOW_TABLE = 0x200, 2070 }; 2071 2072 struct mlx5_ifc_cmd_hca_cap_2_bits { 2073 u8 reserved_at_0[0x80]; 2074 2075 u8 migratable[0x1]; 2076 u8 reserved_at_81[0x1f]; 2077 2078 u8 max_reformat_insert_size[0x8]; 2079 u8 max_reformat_insert_offset[0x8]; 2080 u8 max_reformat_remove_size[0x8]; 2081 u8 max_reformat_remove_offset[0x8]; 2082 2083 u8 reserved_at_c0[0x8]; 2084 u8 migration_multi_load[0x1]; 2085 u8 migration_tracking_state[0x1]; 2086 u8 multiplane_qp_ud[0x1]; 2087 u8 reserved_at_cb[0x5]; 2088 u8 migration_in_chunks[0x1]; 2089 u8 reserved_at_d1[0x1]; 2090 u8 sf_eq_usage[0x1]; 2091 u8 reserved_at_d3[0xd]; 2092 2093 u8 cross_vhca_object_to_object_supported[0x20]; 2094 2095 u8 allowed_object_for_other_vhca_access[0x40]; 2096 2097 u8 reserved_at_140[0x60]; 2098 2099 u8 flow_table_type_2_type[0x8]; 2100 u8 reserved_at_1a8[0x2]; 2101 u8 format_select_dw_8_6_ext[0x1]; 2102 u8 log_min_mkey_entity_size[0x5]; 2103 u8 reserved_at_1b0[0x10]; 2104 2105 u8 reserved_at_1c0[0x60]; 2106 2107 u8 reserved_at_220[0x1]; 2108 u8 sw_vhca_id_valid[0x1]; 2109 u8 sw_vhca_id[0xe]; 2110 u8 reserved_at_230[0x10]; 2111 2112 u8 reserved_at_240[0xb]; 2113 u8 ts_cqe_metadata_size2wqe_counter[0x5]; 2114 u8 reserved_at_250[0x10]; 2115 2116 u8 reserved_at_260[0x120]; 2117 2118 u8 format_select_dw_gtpu_dw_0[0x8]; 2119 u8 format_select_dw_gtpu_dw_1[0x8]; 2120 u8 format_select_dw_gtpu_dw_2[0x8]; 2121 u8 format_select_dw_gtpu_first_ext_dw_0[0x8]; 2122 2123 u8 generate_wqe_type[0x20]; 2124 2125 u8 reserved_at_2c0[0xc0]; 2126 2127 u8 reserved_at_380[0xb]; 2128 u8 min_mkey_log_entity_size_fixed_buffer[0x5]; 2129 u8 ec_vf_vport_base[0x10]; 2130 2131 u8 reserved_at_3a0[0x10]; 2132 u8 max_rqt_vhca_id[0x10]; 2133 2134 u8 reserved_at_3c0[0x20]; 2135 2136 u8 reserved_at_3e0[0x10]; 2137 u8 pcc_ifa2[0x1]; 2138 u8 reserved_at_3f1[0xf]; 2139 2140 u8 reserved_at_400[0x1]; 2141 u8 min_mkey_log_entity_size_fixed_buffer_valid[0x1]; 2142 u8 reserved_at_402[0xe]; 2143 u8 return_reg_id[0x10]; 2144 2145 u8 reserved_at_420[0x1c]; 2146 u8 flow_table_hash_type[0x4]; 2147 2148 u8 reserved_at_440[0x8]; 2149 u8 max_num_eqs_24b[0x18]; 2150 u8 reserved_at_460[0x3a0]; 2151 }; 2152 2153 enum mlx5_ifc_flow_destination_type { 2154 MLX5_IFC_FLOW_DESTINATION_TYPE_VPORT = 0x0, 2155 MLX5_IFC_FLOW_DESTINATION_TYPE_FLOW_TABLE = 0x1, 2156 MLX5_IFC_FLOW_DESTINATION_TYPE_TIR = 0x2, 2157 MLX5_IFC_FLOW_DESTINATION_TYPE_FLOW_SAMPLER = 0x6, 2158 MLX5_IFC_FLOW_DESTINATION_TYPE_UPLINK = 0x8, 2159 MLX5_IFC_FLOW_DESTINATION_TYPE_TABLE_TYPE = 0xA, 2160 }; 2161 2162 enum mlx5_flow_table_miss_action { 2163 MLX5_FLOW_TABLE_MISS_ACTION_DEF, 2164 MLX5_FLOW_TABLE_MISS_ACTION_FWD, 2165 MLX5_FLOW_TABLE_MISS_ACTION_SWITCH_DOMAIN, 2166 }; 2167 2168 struct mlx5_ifc_dest_format_struct_bits { 2169 u8 destination_type[0x8]; 2170 u8 destination_id[0x18]; 2171 2172 u8 destination_eswitch_owner_vhca_id_valid[0x1]; 2173 u8 packet_reformat[0x1]; 2174 u8 reserved_at_22[0x6]; 2175 u8 destination_table_type[0x8]; 2176 u8 destination_eswitch_owner_vhca_id[0x10]; 2177 }; 2178 2179 struct mlx5_ifc_flow_counter_list_bits { 2180 u8 flow_counter_id[0x20]; 2181 2182 u8 reserved_at_20[0x20]; 2183 }; 2184 2185 struct mlx5_ifc_extended_dest_format_bits { 2186 struct mlx5_ifc_dest_format_struct_bits destination_entry; 2187 2188 u8 packet_reformat_id[0x20]; 2189 2190 u8 reserved_at_60[0x20]; 2191 }; 2192 2193 union mlx5_ifc_dest_format_flow_counter_list_auto_bits { 2194 struct mlx5_ifc_extended_dest_format_bits extended_dest_format; 2195 struct mlx5_ifc_flow_counter_list_bits flow_counter_list; 2196 }; 2197 2198 struct mlx5_ifc_fte_match_param_bits { 2199 struct mlx5_ifc_fte_match_set_lyr_2_4_bits outer_headers; 2200 2201 struct mlx5_ifc_fte_match_set_misc_bits misc_parameters; 2202 2203 struct mlx5_ifc_fte_match_set_lyr_2_4_bits inner_headers; 2204 2205 struct mlx5_ifc_fte_match_set_misc2_bits misc_parameters_2; 2206 2207 struct mlx5_ifc_fte_match_set_misc3_bits misc_parameters_3; 2208 2209 struct mlx5_ifc_fte_match_set_misc4_bits misc_parameters_4; 2210 2211 struct mlx5_ifc_fte_match_set_misc5_bits misc_parameters_5; 2212 2213 u8 reserved_at_e00[0x200]; 2214 }; 2215 2216 enum { 2217 MLX5_RX_HASH_FIELD_SELECT_SELECTED_FIELDS_SRC_IP = 0x0, 2218 MLX5_RX_HASH_FIELD_SELECT_SELECTED_FIELDS_DST_IP = 0x1, 2219 MLX5_RX_HASH_FIELD_SELECT_SELECTED_FIELDS_L4_SPORT = 0x2, 2220 MLX5_RX_HASH_FIELD_SELECT_SELECTED_FIELDS_L4_DPORT = 0x3, 2221 MLX5_RX_HASH_FIELD_SELECT_SELECTED_FIELDS_IPSEC_SPI = 0x4, 2222 }; 2223 2224 struct mlx5_ifc_rx_hash_field_select_bits { 2225 u8 l3_prot_type[0x1]; 2226 u8 l4_prot_type[0x1]; 2227 u8 selected_fields[0x1e]; 2228 }; 2229 2230 enum { 2231 MLX5_WQ_WQ_TYPE_WQ_LINKED_LIST = 0x0, 2232 MLX5_WQ_WQ_TYPE_WQ_CYCLIC = 0x1, 2233 }; 2234 2235 enum { 2236 MLX5_WQ_END_PADDING_MODE_END_PAD_NONE = 0x0, 2237 MLX5_WQ_END_PADDING_MODE_END_PAD_ALIGN = 0x1, 2238 }; 2239 2240 struct mlx5_ifc_wq_bits { 2241 u8 wq_type[0x4]; 2242 u8 wq_signature[0x1]; 2243 u8 end_padding_mode[0x2]; 2244 u8 cd_slave[0x1]; 2245 u8 reserved_at_8[0x18]; 2246 2247 u8 hds_skip_first_sge[0x1]; 2248 u8 log2_hds_buf_size[0x3]; 2249 u8 reserved_at_24[0x7]; 2250 u8 page_offset[0x5]; 2251 u8 lwm[0x10]; 2252 2253 u8 reserved_at_40[0x8]; 2254 u8 pd[0x18]; 2255 2256 u8 reserved_at_60[0x8]; 2257 u8 uar_page[0x18]; 2258 2259 u8 dbr_addr[0x40]; 2260 2261 u8 hw_counter[0x20]; 2262 2263 u8 sw_counter[0x20]; 2264 2265 u8 reserved_at_100[0xc]; 2266 u8 log_wq_stride[0x4]; 2267 u8 reserved_at_110[0x3]; 2268 u8 log_wq_pg_sz[0x5]; 2269 u8 reserved_at_118[0x3]; 2270 u8 log_wq_sz[0x5]; 2271 2272 u8 dbr_umem_valid[0x1]; 2273 u8 wq_umem_valid[0x1]; 2274 u8 reserved_at_122[0x1]; 2275 u8 log_hairpin_num_packets[0x5]; 2276 u8 reserved_at_128[0x3]; 2277 u8 log_hairpin_data_sz[0x5]; 2278 2279 u8 reserved_at_130[0x4]; 2280 u8 log_wqe_num_of_strides[0x4]; 2281 u8 two_byte_shift_en[0x1]; 2282 u8 reserved_at_139[0x4]; 2283 u8 log_wqe_stride_size[0x3]; 2284 2285 u8 dbr_umem_id[0x20]; 2286 u8 wq_umem_id[0x20]; 2287 2288 u8 wq_umem_offset[0x40]; 2289 2290 u8 headers_mkey[0x20]; 2291 2292 u8 shampo_enable[0x1]; 2293 u8 reserved_at_1e1[0x4]; 2294 u8 log_reservation_size[0x3]; 2295 u8 reserved_at_1e8[0x5]; 2296 u8 log_max_num_of_packets_per_reservation[0x3]; 2297 u8 reserved_at_1f0[0x6]; 2298 u8 log_headers_entry_size[0x2]; 2299 u8 reserved_at_1f8[0x4]; 2300 u8 log_headers_buffer_entry_num[0x4]; 2301 2302 u8 reserved_at_200[0x400]; 2303 2304 struct mlx5_ifc_cmd_pas_bits pas[]; 2305 }; 2306 2307 struct mlx5_ifc_rq_num_bits { 2308 u8 reserved_at_0[0x8]; 2309 u8 rq_num[0x18]; 2310 }; 2311 2312 struct mlx5_ifc_rq_vhca_bits { 2313 u8 reserved_at_0[0x8]; 2314 u8 rq_num[0x18]; 2315 u8 reserved_at_20[0x10]; 2316 u8 rq_vhca_id[0x10]; 2317 }; 2318 2319 struct mlx5_ifc_mac_address_layout_bits { 2320 u8 reserved_at_0[0x10]; 2321 u8 mac_addr_47_32[0x10]; 2322 2323 u8 mac_addr_31_0[0x20]; 2324 }; 2325 2326 struct mlx5_ifc_vlan_layout_bits { 2327 u8 reserved_at_0[0x14]; 2328 u8 vlan[0x0c]; 2329 2330 u8 reserved_at_20[0x20]; 2331 }; 2332 2333 struct mlx5_ifc_cong_control_r_roce_ecn_np_bits { 2334 u8 reserved_at_0[0xa0]; 2335 2336 u8 min_time_between_cnps[0x20]; 2337 2338 u8 reserved_at_c0[0x12]; 2339 u8 cnp_dscp[0x6]; 2340 u8 reserved_at_d8[0x4]; 2341 u8 cnp_prio_mode[0x1]; 2342 u8 cnp_802p_prio[0x3]; 2343 2344 u8 reserved_at_e0[0x720]; 2345 }; 2346 2347 struct mlx5_ifc_cong_control_r_roce_ecn_rp_bits { 2348 u8 reserved_at_0[0x60]; 2349 2350 u8 reserved_at_60[0x4]; 2351 u8 clamp_tgt_rate[0x1]; 2352 u8 reserved_at_65[0x3]; 2353 u8 clamp_tgt_rate_after_time_inc[0x1]; 2354 u8 reserved_at_69[0x17]; 2355 2356 u8 reserved_at_80[0x20]; 2357 2358 u8 rpg_time_reset[0x20]; 2359 2360 u8 rpg_byte_reset[0x20]; 2361 2362 u8 rpg_threshold[0x20]; 2363 2364 u8 rpg_max_rate[0x20]; 2365 2366 u8 rpg_ai_rate[0x20]; 2367 2368 u8 rpg_hai_rate[0x20]; 2369 2370 u8 rpg_gd[0x20]; 2371 2372 u8 rpg_min_dec_fac[0x20]; 2373 2374 u8 rpg_min_rate[0x20]; 2375 2376 u8 reserved_at_1c0[0xe0]; 2377 2378 u8 rate_to_set_on_first_cnp[0x20]; 2379 2380 u8 dce_tcp_g[0x20]; 2381 2382 u8 dce_tcp_rtt[0x20]; 2383 2384 u8 rate_reduce_monitor_period[0x20]; 2385 2386 u8 reserved_at_320[0x20]; 2387 2388 u8 initial_alpha_value[0x20]; 2389 2390 u8 reserved_at_360[0x4a0]; 2391 }; 2392 2393 struct mlx5_ifc_cong_control_r_roce_general_bits { 2394 u8 reserved_at_0[0x80]; 2395 2396 u8 reserved_at_80[0x10]; 2397 u8 rtt_resp_dscp_valid[0x1]; 2398 u8 reserved_at_91[0x9]; 2399 u8 rtt_resp_dscp[0x6]; 2400 2401 u8 reserved_at_a0[0x760]; 2402 }; 2403 2404 struct mlx5_ifc_cong_control_802_1qau_rp_bits { 2405 u8 reserved_at_0[0x80]; 2406 2407 u8 rppp_max_rps[0x20]; 2408 2409 u8 rpg_time_reset[0x20]; 2410 2411 u8 rpg_byte_reset[0x20]; 2412 2413 u8 rpg_threshold[0x20]; 2414 2415 u8 rpg_max_rate[0x20]; 2416 2417 u8 rpg_ai_rate[0x20]; 2418 2419 u8 rpg_hai_rate[0x20]; 2420 2421 u8 rpg_gd[0x20]; 2422 2423 u8 rpg_min_dec_fac[0x20]; 2424 2425 u8 rpg_min_rate[0x20]; 2426 2427 u8 reserved_at_1c0[0x640]; 2428 }; 2429 2430 enum { 2431 MLX5_RESIZE_FIELD_SELECT_RESIZE_FIELD_SELECT_LOG_CQ_SIZE = 0x1, 2432 MLX5_RESIZE_FIELD_SELECT_RESIZE_FIELD_SELECT_PAGE_OFFSET = 0x2, 2433 MLX5_RESIZE_FIELD_SELECT_RESIZE_FIELD_SELECT_LOG_PAGE_SIZE = 0x4, 2434 }; 2435 2436 struct mlx5_ifc_resize_field_select_bits { 2437 u8 resize_field_select[0x20]; 2438 }; 2439 2440 struct mlx5_ifc_resource_dump_bits { 2441 u8 more_dump[0x1]; 2442 u8 inline_dump[0x1]; 2443 u8 reserved_at_2[0xa]; 2444 u8 seq_num[0x4]; 2445 u8 segment_type[0x10]; 2446 2447 u8 reserved_at_20[0x10]; 2448 u8 vhca_id[0x10]; 2449 2450 u8 index1[0x20]; 2451 2452 u8 index2[0x20]; 2453 2454 u8 num_of_obj1[0x10]; 2455 u8 num_of_obj2[0x10]; 2456 2457 u8 reserved_at_a0[0x20]; 2458 2459 u8 device_opaque[0x40]; 2460 2461 u8 mkey[0x20]; 2462 2463 u8 size[0x20]; 2464 2465 u8 address[0x40]; 2466 2467 u8 inline_data[52][0x20]; 2468 }; 2469 2470 struct mlx5_ifc_resource_dump_menu_record_bits { 2471 u8 reserved_at_0[0x4]; 2472 u8 num_of_obj2_supports_active[0x1]; 2473 u8 num_of_obj2_supports_all[0x1]; 2474 u8 must_have_num_of_obj2[0x1]; 2475 u8 support_num_of_obj2[0x1]; 2476 u8 num_of_obj1_supports_active[0x1]; 2477 u8 num_of_obj1_supports_all[0x1]; 2478 u8 must_have_num_of_obj1[0x1]; 2479 u8 support_num_of_obj1[0x1]; 2480 u8 must_have_index2[0x1]; 2481 u8 support_index2[0x1]; 2482 u8 must_have_index1[0x1]; 2483 u8 support_index1[0x1]; 2484 u8 segment_type[0x10]; 2485 2486 u8 segment_name[4][0x20]; 2487 2488 u8 index1_name[4][0x20]; 2489 2490 u8 index2_name[4][0x20]; 2491 }; 2492 2493 struct mlx5_ifc_resource_dump_segment_header_bits { 2494 u8 length_dw[0x10]; 2495 u8 segment_type[0x10]; 2496 }; 2497 2498 struct mlx5_ifc_resource_dump_command_segment_bits { 2499 struct mlx5_ifc_resource_dump_segment_header_bits segment_header; 2500 2501 u8 segment_called[0x10]; 2502 u8 vhca_id[0x10]; 2503 2504 u8 index1[0x20]; 2505 2506 u8 index2[0x20]; 2507 2508 u8 num_of_obj1[0x10]; 2509 u8 num_of_obj2[0x10]; 2510 }; 2511 2512 struct mlx5_ifc_resource_dump_error_segment_bits { 2513 struct mlx5_ifc_resource_dump_segment_header_bits segment_header; 2514 2515 u8 reserved_at_20[0x10]; 2516 u8 syndrome_id[0x10]; 2517 2518 u8 reserved_at_40[0x40]; 2519 2520 u8 error[8][0x20]; 2521 }; 2522 2523 struct mlx5_ifc_resource_dump_info_segment_bits { 2524 struct mlx5_ifc_resource_dump_segment_header_bits segment_header; 2525 2526 u8 reserved_at_20[0x18]; 2527 u8 dump_version[0x8]; 2528 2529 u8 hw_version[0x20]; 2530 2531 u8 fw_version[0x20]; 2532 }; 2533 2534 struct mlx5_ifc_resource_dump_menu_segment_bits { 2535 struct mlx5_ifc_resource_dump_segment_header_bits segment_header; 2536 2537 u8 reserved_at_20[0x10]; 2538 u8 num_of_records[0x10]; 2539 2540 struct mlx5_ifc_resource_dump_menu_record_bits record[]; 2541 }; 2542 2543 struct mlx5_ifc_resource_dump_resource_segment_bits { 2544 struct mlx5_ifc_resource_dump_segment_header_bits segment_header; 2545 2546 u8 reserved_at_20[0x20]; 2547 2548 u8 index1[0x20]; 2549 2550 u8 index2[0x20]; 2551 2552 u8 payload[][0x20]; 2553 }; 2554 2555 struct mlx5_ifc_resource_dump_terminate_segment_bits { 2556 struct mlx5_ifc_resource_dump_segment_header_bits segment_header; 2557 }; 2558 2559 struct mlx5_ifc_menu_resource_dump_response_bits { 2560 struct mlx5_ifc_resource_dump_info_segment_bits info; 2561 struct mlx5_ifc_resource_dump_command_segment_bits cmd; 2562 struct mlx5_ifc_resource_dump_menu_segment_bits menu; 2563 struct mlx5_ifc_resource_dump_terminate_segment_bits terminate; 2564 }; 2565 2566 enum { 2567 MLX5_MODIFY_FIELD_SELECT_MODIFY_FIELD_SELECT_CQ_PERIOD = 0x1, 2568 MLX5_MODIFY_FIELD_SELECT_MODIFY_FIELD_SELECT_CQ_MAX_COUNT = 0x2, 2569 MLX5_MODIFY_FIELD_SELECT_MODIFY_FIELD_SELECT_OI = 0x4, 2570 MLX5_MODIFY_FIELD_SELECT_MODIFY_FIELD_SELECT_C_EQN = 0x8, 2571 }; 2572 2573 struct mlx5_ifc_modify_field_select_bits { 2574 u8 modify_field_select[0x20]; 2575 }; 2576 2577 struct mlx5_ifc_field_select_r_roce_np_bits { 2578 u8 field_select_r_roce_np[0x20]; 2579 }; 2580 2581 struct mlx5_ifc_field_select_r_roce_rp_bits { 2582 u8 field_select_r_roce_rp[0x20]; 2583 }; 2584 2585 enum { 2586 MLX5_FIELD_SELECT_802_1QAU_RP_FIELD_SELECT_8021QAURP_RPPP_MAX_RPS = 0x4, 2587 MLX5_FIELD_SELECT_802_1QAU_RP_FIELD_SELECT_8021QAURP_RPG_TIME_RESET = 0x8, 2588 MLX5_FIELD_SELECT_802_1QAU_RP_FIELD_SELECT_8021QAURP_RPG_BYTE_RESET = 0x10, 2589 MLX5_FIELD_SELECT_802_1QAU_RP_FIELD_SELECT_8021QAURP_RPG_THRESHOLD = 0x20, 2590 MLX5_FIELD_SELECT_802_1QAU_RP_FIELD_SELECT_8021QAURP_RPG_MAX_RATE = 0x40, 2591 MLX5_FIELD_SELECT_802_1QAU_RP_FIELD_SELECT_8021QAURP_RPG_AI_RATE = 0x80, 2592 MLX5_FIELD_SELECT_802_1QAU_RP_FIELD_SELECT_8021QAURP_RPG_HAI_RATE = 0x100, 2593 MLX5_FIELD_SELECT_802_1QAU_RP_FIELD_SELECT_8021QAURP_RPG_GD = 0x200, 2594 MLX5_FIELD_SELECT_802_1QAU_RP_FIELD_SELECT_8021QAURP_RPG_MIN_DEC_FAC = 0x400, 2595 MLX5_FIELD_SELECT_802_1QAU_RP_FIELD_SELECT_8021QAURP_RPG_MIN_RATE = 0x800, 2596 }; 2597 2598 struct mlx5_ifc_field_select_802_1qau_rp_bits { 2599 u8 field_select_8021qaurp[0x20]; 2600 }; 2601 2602 struct mlx5_ifc_phys_layer_cntrs_bits { 2603 u8 time_since_last_clear_high[0x20]; 2604 2605 u8 time_since_last_clear_low[0x20]; 2606 2607 u8 symbol_errors_high[0x20]; 2608 2609 u8 symbol_errors_low[0x20]; 2610 2611 u8 sync_headers_errors_high[0x20]; 2612 2613 u8 sync_headers_errors_low[0x20]; 2614 2615 u8 edpl_bip_errors_lane0_high[0x20]; 2616 2617 u8 edpl_bip_errors_lane0_low[0x20]; 2618 2619 u8 edpl_bip_errors_lane1_high[0x20]; 2620 2621 u8 edpl_bip_errors_lane1_low[0x20]; 2622 2623 u8 edpl_bip_errors_lane2_high[0x20]; 2624 2625 u8 edpl_bip_errors_lane2_low[0x20]; 2626 2627 u8 edpl_bip_errors_lane3_high[0x20]; 2628 2629 u8 edpl_bip_errors_lane3_low[0x20]; 2630 2631 u8 fc_fec_corrected_blocks_lane0_high[0x20]; 2632 2633 u8 fc_fec_corrected_blocks_lane0_low[0x20]; 2634 2635 u8 fc_fec_corrected_blocks_lane1_high[0x20]; 2636 2637 u8 fc_fec_corrected_blocks_lane1_low[0x20]; 2638 2639 u8 fc_fec_corrected_blocks_lane2_high[0x20]; 2640 2641 u8 fc_fec_corrected_blocks_lane2_low[0x20]; 2642 2643 u8 fc_fec_corrected_blocks_lane3_high[0x20]; 2644 2645 u8 fc_fec_corrected_blocks_lane3_low[0x20]; 2646 2647 u8 fc_fec_uncorrectable_blocks_lane0_high[0x20]; 2648 2649 u8 fc_fec_uncorrectable_blocks_lane0_low[0x20]; 2650 2651 u8 fc_fec_uncorrectable_blocks_lane1_high[0x20]; 2652 2653 u8 fc_fec_uncorrectable_blocks_lane1_low[0x20]; 2654 2655 u8 fc_fec_uncorrectable_blocks_lane2_high[0x20]; 2656 2657 u8 fc_fec_uncorrectable_blocks_lane2_low[0x20]; 2658 2659 u8 fc_fec_uncorrectable_blocks_lane3_high[0x20]; 2660 2661 u8 fc_fec_uncorrectable_blocks_lane3_low[0x20]; 2662 2663 u8 rs_fec_corrected_blocks_high[0x20]; 2664 2665 u8 rs_fec_corrected_blocks_low[0x20]; 2666 2667 u8 rs_fec_uncorrectable_blocks_high[0x20]; 2668 2669 u8 rs_fec_uncorrectable_blocks_low[0x20]; 2670 2671 u8 rs_fec_no_errors_blocks_high[0x20]; 2672 2673 u8 rs_fec_no_errors_blocks_low[0x20]; 2674 2675 u8 rs_fec_single_error_blocks_high[0x20]; 2676 2677 u8 rs_fec_single_error_blocks_low[0x20]; 2678 2679 u8 rs_fec_corrected_symbols_total_high[0x20]; 2680 2681 u8 rs_fec_corrected_symbols_total_low[0x20]; 2682 2683 u8 rs_fec_corrected_symbols_lane0_high[0x20]; 2684 2685 u8 rs_fec_corrected_symbols_lane0_low[0x20]; 2686 2687 u8 rs_fec_corrected_symbols_lane1_high[0x20]; 2688 2689 u8 rs_fec_corrected_symbols_lane1_low[0x20]; 2690 2691 u8 rs_fec_corrected_symbols_lane2_high[0x20]; 2692 2693 u8 rs_fec_corrected_symbols_lane2_low[0x20]; 2694 2695 u8 rs_fec_corrected_symbols_lane3_high[0x20]; 2696 2697 u8 rs_fec_corrected_symbols_lane3_low[0x20]; 2698 2699 u8 link_down_events[0x20]; 2700 2701 u8 successful_recovery_events[0x20]; 2702 2703 u8 reserved_at_640[0x180]; 2704 }; 2705 2706 struct mlx5_ifc_phys_layer_statistical_cntrs_bits { 2707 u8 time_since_last_clear_high[0x20]; 2708 2709 u8 time_since_last_clear_low[0x20]; 2710 2711 u8 phy_received_bits_high[0x20]; 2712 2713 u8 phy_received_bits_low[0x20]; 2714 2715 u8 phy_symbol_errors_high[0x20]; 2716 2717 u8 phy_symbol_errors_low[0x20]; 2718 2719 u8 phy_corrected_bits_high[0x20]; 2720 2721 u8 phy_corrected_bits_low[0x20]; 2722 2723 u8 phy_corrected_bits_lane0_high[0x20]; 2724 2725 u8 phy_corrected_bits_lane0_low[0x20]; 2726 2727 u8 phy_corrected_bits_lane1_high[0x20]; 2728 2729 u8 phy_corrected_bits_lane1_low[0x20]; 2730 2731 u8 phy_corrected_bits_lane2_high[0x20]; 2732 2733 u8 phy_corrected_bits_lane2_low[0x20]; 2734 2735 u8 phy_corrected_bits_lane3_high[0x20]; 2736 2737 u8 phy_corrected_bits_lane3_low[0x20]; 2738 2739 u8 reserved_at_200[0x5c0]; 2740 }; 2741 2742 struct mlx5_ifc_ib_port_cntrs_grp_data_layout_bits { 2743 u8 symbol_error_counter[0x10]; 2744 2745 u8 link_error_recovery_counter[0x8]; 2746 2747 u8 link_downed_counter[0x8]; 2748 2749 u8 port_rcv_errors[0x10]; 2750 2751 u8 port_rcv_remote_physical_errors[0x10]; 2752 2753 u8 port_rcv_switch_relay_errors[0x10]; 2754 2755 u8 port_xmit_discards[0x10]; 2756 2757 u8 port_xmit_constraint_errors[0x8]; 2758 2759 u8 port_rcv_constraint_errors[0x8]; 2760 2761 u8 reserved_at_70[0x8]; 2762 2763 u8 link_overrun_errors[0x8]; 2764 2765 u8 reserved_at_80[0x10]; 2766 2767 u8 vl_15_dropped[0x10]; 2768 2769 u8 reserved_at_a0[0x80]; 2770 2771 u8 port_xmit_wait[0x20]; 2772 }; 2773 2774 struct mlx5_ifc_ib_ext_port_cntrs_grp_data_layout_bits { 2775 u8 reserved_at_0[0x300]; 2776 2777 u8 port_xmit_data_high[0x20]; 2778 2779 u8 port_xmit_data_low[0x20]; 2780 2781 u8 port_rcv_data_high[0x20]; 2782 2783 u8 port_rcv_data_low[0x20]; 2784 2785 u8 port_xmit_pkts_high[0x20]; 2786 2787 u8 port_xmit_pkts_low[0x20]; 2788 2789 u8 port_rcv_pkts_high[0x20]; 2790 2791 u8 port_rcv_pkts_low[0x20]; 2792 2793 u8 reserved_at_400[0x80]; 2794 2795 u8 port_unicast_xmit_pkts_high[0x20]; 2796 2797 u8 port_unicast_xmit_pkts_low[0x20]; 2798 2799 u8 port_multicast_xmit_pkts_high[0x20]; 2800 2801 u8 port_multicast_xmit_pkts_low[0x20]; 2802 2803 u8 port_unicast_rcv_pkts_high[0x20]; 2804 2805 u8 port_unicast_rcv_pkts_low[0x20]; 2806 2807 u8 port_multicast_rcv_pkts_high[0x20]; 2808 2809 u8 port_multicast_rcv_pkts_low[0x20]; 2810 2811 u8 reserved_at_580[0x240]; 2812 }; 2813 2814 struct mlx5_ifc_eth_per_tc_prio_grp_data_layout_bits { 2815 u8 transmit_queue_high[0x20]; 2816 2817 u8 transmit_queue_low[0x20]; 2818 2819 u8 no_buffer_discard_uc_high[0x20]; 2820 2821 u8 no_buffer_discard_uc_low[0x20]; 2822 2823 u8 reserved_at_80[0x740]; 2824 }; 2825 2826 struct mlx5_ifc_eth_per_tc_congest_prio_grp_data_layout_bits { 2827 u8 wred_discard_high[0x20]; 2828 2829 u8 wred_discard_low[0x20]; 2830 2831 u8 ecn_marked_tc_high[0x20]; 2832 2833 u8 ecn_marked_tc_low[0x20]; 2834 2835 u8 reserved_at_80[0x740]; 2836 }; 2837 2838 struct mlx5_ifc_eth_per_prio_grp_data_layout_bits { 2839 u8 rx_octets_high[0x20]; 2840 2841 u8 rx_octets_low[0x20]; 2842 2843 u8 reserved_at_40[0xc0]; 2844 2845 u8 rx_frames_high[0x20]; 2846 2847 u8 rx_frames_low[0x20]; 2848 2849 u8 tx_octets_high[0x20]; 2850 2851 u8 tx_octets_low[0x20]; 2852 2853 u8 reserved_at_180[0xc0]; 2854 2855 u8 tx_frames_high[0x20]; 2856 2857 u8 tx_frames_low[0x20]; 2858 2859 u8 rx_pause_high[0x20]; 2860 2861 u8 rx_pause_low[0x20]; 2862 2863 u8 rx_pause_duration_high[0x20]; 2864 2865 u8 rx_pause_duration_low[0x20]; 2866 2867 u8 tx_pause_high[0x20]; 2868 2869 u8 tx_pause_low[0x20]; 2870 2871 u8 tx_pause_duration_high[0x20]; 2872 2873 u8 tx_pause_duration_low[0x20]; 2874 2875 u8 rx_pause_transition_high[0x20]; 2876 2877 u8 rx_pause_transition_low[0x20]; 2878 2879 u8 rx_discards_high[0x20]; 2880 2881 u8 rx_discards_low[0x20]; 2882 2883 u8 device_stall_minor_watermark_cnt_high[0x20]; 2884 2885 u8 device_stall_minor_watermark_cnt_low[0x20]; 2886 2887 u8 device_stall_critical_watermark_cnt_high[0x20]; 2888 2889 u8 device_stall_critical_watermark_cnt_low[0x20]; 2890 2891 u8 reserved_at_480[0x340]; 2892 }; 2893 2894 struct mlx5_ifc_eth_extended_cntrs_grp_data_layout_bits { 2895 u8 port_transmit_wait_high[0x20]; 2896 2897 u8 port_transmit_wait_low[0x20]; 2898 2899 u8 reserved_at_40[0x100]; 2900 2901 u8 rx_buffer_almost_full_high[0x20]; 2902 2903 u8 rx_buffer_almost_full_low[0x20]; 2904 2905 u8 rx_buffer_full_high[0x20]; 2906 2907 u8 rx_buffer_full_low[0x20]; 2908 2909 u8 rx_icrc_encapsulated_high[0x20]; 2910 2911 u8 rx_icrc_encapsulated_low[0x20]; 2912 2913 u8 reserved_at_200[0x5c0]; 2914 }; 2915 2916 struct mlx5_ifc_eth_3635_cntrs_grp_data_layout_bits { 2917 u8 dot3stats_alignment_errors_high[0x20]; 2918 2919 u8 dot3stats_alignment_errors_low[0x20]; 2920 2921 u8 dot3stats_fcs_errors_high[0x20]; 2922 2923 u8 dot3stats_fcs_errors_low[0x20]; 2924 2925 u8 dot3stats_single_collision_frames_high[0x20]; 2926 2927 u8 dot3stats_single_collision_frames_low[0x20]; 2928 2929 u8 dot3stats_multiple_collision_frames_high[0x20]; 2930 2931 u8 dot3stats_multiple_collision_frames_low[0x20]; 2932 2933 u8 dot3stats_sqe_test_errors_high[0x20]; 2934 2935 u8 dot3stats_sqe_test_errors_low[0x20]; 2936 2937 u8 dot3stats_deferred_transmissions_high[0x20]; 2938 2939 u8 dot3stats_deferred_transmissions_low[0x20]; 2940 2941 u8 dot3stats_late_collisions_high[0x20]; 2942 2943 u8 dot3stats_late_collisions_low[0x20]; 2944 2945 u8 dot3stats_excessive_collisions_high[0x20]; 2946 2947 u8 dot3stats_excessive_collisions_low[0x20]; 2948 2949 u8 dot3stats_internal_mac_transmit_errors_high[0x20]; 2950 2951 u8 dot3stats_internal_mac_transmit_errors_low[0x20]; 2952 2953 u8 dot3stats_carrier_sense_errors_high[0x20]; 2954 2955 u8 dot3stats_carrier_sense_errors_low[0x20]; 2956 2957 u8 dot3stats_frame_too_longs_high[0x20]; 2958 2959 u8 dot3stats_frame_too_longs_low[0x20]; 2960 2961 u8 dot3stats_internal_mac_receive_errors_high[0x20]; 2962 2963 u8 dot3stats_internal_mac_receive_errors_low[0x20]; 2964 2965 u8 dot3stats_symbol_errors_high[0x20]; 2966 2967 u8 dot3stats_symbol_errors_low[0x20]; 2968 2969 u8 dot3control_in_unknown_opcodes_high[0x20]; 2970 2971 u8 dot3control_in_unknown_opcodes_low[0x20]; 2972 2973 u8 dot3in_pause_frames_high[0x20]; 2974 2975 u8 dot3in_pause_frames_low[0x20]; 2976 2977 u8 dot3out_pause_frames_high[0x20]; 2978 2979 u8 dot3out_pause_frames_low[0x20]; 2980 2981 u8 reserved_at_400[0x3c0]; 2982 }; 2983 2984 struct mlx5_ifc_eth_2819_cntrs_grp_data_layout_bits { 2985 u8 ether_stats_drop_events_high[0x20]; 2986 2987 u8 ether_stats_drop_events_low[0x20]; 2988 2989 u8 ether_stats_octets_high[0x20]; 2990 2991 u8 ether_stats_octets_low[0x20]; 2992 2993 u8 ether_stats_pkts_high[0x20]; 2994 2995 u8 ether_stats_pkts_low[0x20]; 2996 2997 u8 ether_stats_broadcast_pkts_high[0x20]; 2998 2999 u8 ether_stats_broadcast_pkts_low[0x20]; 3000 3001 u8 ether_stats_multicast_pkts_high[0x20]; 3002 3003 u8 ether_stats_multicast_pkts_low[0x20]; 3004 3005 u8 ether_stats_crc_align_errors_high[0x20]; 3006 3007 u8 ether_stats_crc_align_errors_low[0x20]; 3008 3009 u8 ether_stats_undersize_pkts_high[0x20]; 3010 3011 u8 ether_stats_undersize_pkts_low[0x20]; 3012 3013 u8 ether_stats_oversize_pkts_high[0x20]; 3014 3015 u8 ether_stats_oversize_pkts_low[0x20]; 3016 3017 u8 ether_stats_fragments_high[0x20]; 3018 3019 u8 ether_stats_fragments_low[0x20]; 3020 3021 u8 ether_stats_jabbers_high[0x20]; 3022 3023 u8 ether_stats_jabbers_low[0x20]; 3024 3025 u8 ether_stats_collisions_high[0x20]; 3026 3027 u8 ether_stats_collisions_low[0x20]; 3028 3029 u8 ether_stats_pkts64octets_high[0x20]; 3030 3031 u8 ether_stats_pkts64octets_low[0x20]; 3032 3033 u8 ether_stats_pkts65to127octets_high[0x20]; 3034 3035 u8 ether_stats_pkts65to127octets_low[0x20]; 3036 3037 u8 ether_stats_pkts128to255octets_high[0x20]; 3038 3039 u8 ether_stats_pkts128to255octets_low[0x20]; 3040 3041 u8 ether_stats_pkts256to511octets_high[0x20]; 3042 3043 u8 ether_stats_pkts256to511octets_low[0x20]; 3044 3045 u8 ether_stats_pkts512to1023octets_high[0x20]; 3046 3047 u8 ether_stats_pkts512to1023octets_low[0x20]; 3048 3049 u8 ether_stats_pkts1024to1518octets_high[0x20]; 3050 3051 u8 ether_stats_pkts1024to1518octets_low[0x20]; 3052 3053 u8 ether_stats_pkts1519to2047octets_high[0x20]; 3054 3055 u8 ether_stats_pkts1519to2047octets_low[0x20]; 3056 3057 u8 ether_stats_pkts2048to4095octets_high[0x20]; 3058 3059 u8 ether_stats_pkts2048to4095octets_low[0x20]; 3060 3061 u8 ether_stats_pkts4096to8191octets_high[0x20]; 3062 3063 u8 ether_stats_pkts4096to8191octets_low[0x20]; 3064 3065 u8 ether_stats_pkts8192to10239octets_high[0x20]; 3066 3067 u8 ether_stats_pkts8192to10239octets_low[0x20]; 3068 3069 u8 reserved_at_540[0x280]; 3070 }; 3071 3072 struct mlx5_ifc_eth_2863_cntrs_grp_data_layout_bits { 3073 u8 if_in_octets_high[0x20]; 3074 3075 u8 if_in_octets_low[0x20]; 3076 3077 u8 if_in_ucast_pkts_high[0x20]; 3078 3079 u8 if_in_ucast_pkts_low[0x20]; 3080 3081 u8 if_in_discards_high[0x20]; 3082 3083 u8 if_in_discards_low[0x20]; 3084 3085 u8 if_in_errors_high[0x20]; 3086 3087 u8 if_in_errors_low[0x20]; 3088 3089 u8 if_in_unknown_protos_high[0x20]; 3090 3091 u8 if_in_unknown_protos_low[0x20]; 3092 3093 u8 if_out_octets_high[0x20]; 3094 3095 u8 if_out_octets_low[0x20]; 3096 3097 u8 if_out_ucast_pkts_high[0x20]; 3098 3099 u8 if_out_ucast_pkts_low[0x20]; 3100 3101 u8 if_out_discards_high[0x20]; 3102 3103 u8 if_out_discards_low[0x20]; 3104 3105 u8 if_out_errors_high[0x20]; 3106 3107 u8 if_out_errors_low[0x20]; 3108 3109 u8 if_in_multicast_pkts_high[0x20]; 3110 3111 u8 if_in_multicast_pkts_low[0x20]; 3112 3113 u8 if_in_broadcast_pkts_high[0x20]; 3114 3115 u8 if_in_broadcast_pkts_low[0x20]; 3116 3117 u8 if_out_multicast_pkts_high[0x20]; 3118 3119 u8 if_out_multicast_pkts_low[0x20]; 3120 3121 u8 if_out_broadcast_pkts_high[0x20]; 3122 3123 u8 if_out_broadcast_pkts_low[0x20]; 3124 3125 u8 reserved_at_340[0x480]; 3126 }; 3127 3128 struct mlx5_ifc_eth_802_3_cntrs_grp_data_layout_bits { 3129 u8 a_frames_transmitted_ok_high[0x20]; 3130 3131 u8 a_frames_transmitted_ok_low[0x20]; 3132 3133 u8 a_frames_received_ok_high[0x20]; 3134 3135 u8 a_frames_received_ok_low[0x20]; 3136 3137 u8 a_frame_check_sequence_errors_high[0x20]; 3138 3139 u8 a_frame_check_sequence_errors_low[0x20]; 3140 3141 u8 a_alignment_errors_high[0x20]; 3142 3143 u8 a_alignment_errors_low[0x20]; 3144 3145 u8 a_octets_transmitted_ok_high[0x20]; 3146 3147 u8 a_octets_transmitted_ok_low[0x20]; 3148 3149 u8 a_octets_received_ok_high[0x20]; 3150 3151 u8 a_octets_received_ok_low[0x20]; 3152 3153 u8 a_multicast_frames_xmitted_ok_high[0x20]; 3154 3155 u8 a_multicast_frames_xmitted_ok_low[0x20]; 3156 3157 u8 a_broadcast_frames_xmitted_ok_high[0x20]; 3158 3159 u8 a_broadcast_frames_xmitted_ok_low[0x20]; 3160 3161 u8 a_multicast_frames_received_ok_high[0x20]; 3162 3163 u8 a_multicast_frames_received_ok_low[0x20]; 3164 3165 u8 a_broadcast_frames_received_ok_high[0x20]; 3166 3167 u8 a_broadcast_frames_received_ok_low[0x20]; 3168 3169 u8 a_in_range_length_errors_high[0x20]; 3170 3171 u8 a_in_range_length_errors_low[0x20]; 3172 3173 u8 a_out_of_range_length_field_high[0x20]; 3174 3175 u8 a_out_of_range_length_field_low[0x20]; 3176 3177 u8 a_frame_too_long_errors_high[0x20]; 3178 3179 u8 a_frame_too_long_errors_low[0x20]; 3180 3181 u8 a_symbol_error_during_carrier_high[0x20]; 3182 3183 u8 a_symbol_error_during_carrier_low[0x20]; 3184 3185 u8 a_mac_control_frames_transmitted_high[0x20]; 3186 3187 u8 a_mac_control_frames_transmitted_low[0x20]; 3188 3189 u8 a_mac_control_frames_received_high[0x20]; 3190 3191 u8 a_mac_control_frames_received_low[0x20]; 3192 3193 u8 a_unsupported_opcodes_received_high[0x20]; 3194 3195 u8 a_unsupported_opcodes_received_low[0x20]; 3196 3197 u8 a_pause_mac_ctrl_frames_received_high[0x20]; 3198 3199 u8 a_pause_mac_ctrl_frames_received_low[0x20]; 3200 3201 u8 a_pause_mac_ctrl_frames_transmitted_high[0x20]; 3202 3203 u8 a_pause_mac_ctrl_frames_transmitted_low[0x20]; 3204 3205 u8 reserved_at_4c0[0x300]; 3206 }; 3207 3208 struct mlx5_ifc_pcie_perf_cntrs_grp_data_layout_bits { 3209 u8 life_time_counter_high[0x20]; 3210 3211 u8 life_time_counter_low[0x20]; 3212 3213 u8 rx_errors[0x20]; 3214 3215 u8 tx_errors[0x20]; 3216 3217 u8 l0_to_recovery_eieos[0x20]; 3218 3219 u8 l0_to_recovery_ts[0x20]; 3220 3221 u8 l0_to_recovery_framing[0x20]; 3222 3223 u8 l0_to_recovery_retrain[0x20]; 3224 3225 u8 crc_error_dllp[0x20]; 3226 3227 u8 crc_error_tlp[0x20]; 3228 3229 u8 tx_overflow_buffer_pkt_high[0x20]; 3230 3231 u8 tx_overflow_buffer_pkt_low[0x20]; 3232 3233 u8 outbound_stalled_reads[0x20]; 3234 3235 u8 outbound_stalled_writes[0x20]; 3236 3237 u8 outbound_stalled_reads_events[0x20]; 3238 3239 u8 outbound_stalled_writes_events[0x20]; 3240 3241 u8 reserved_at_200[0x5c0]; 3242 }; 3243 3244 struct mlx5_ifc_cmd_inter_comp_event_bits { 3245 u8 command_completion_vector[0x20]; 3246 3247 u8 reserved_at_20[0xc0]; 3248 }; 3249 3250 struct mlx5_ifc_stall_vl_event_bits { 3251 u8 reserved_at_0[0x18]; 3252 u8 port_num[0x1]; 3253 u8 reserved_at_19[0x3]; 3254 u8 vl[0x4]; 3255 3256 u8 reserved_at_20[0xa0]; 3257 }; 3258 3259 struct mlx5_ifc_db_bf_congestion_event_bits { 3260 u8 event_subtype[0x8]; 3261 u8 reserved_at_8[0x8]; 3262 u8 congestion_level[0x8]; 3263 u8 reserved_at_18[0x8]; 3264 3265 u8 reserved_at_20[0xa0]; 3266 }; 3267 3268 struct mlx5_ifc_gpio_event_bits { 3269 u8 reserved_at_0[0x60]; 3270 3271 u8 gpio_event_hi[0x20]; 3272 3273 u8 gpio_event_lo[0x20]; 3274 3275 u8 reserved_at_a0[0x40]; 3276 }; 3277 3278 struct mlx5_ifc_port_state_change_event_bits { 3279 u8 reserved_at_0[0x40]; 3280 3281 u8 port_num[0x4]; 3282 u8 reserved_at_44[0x1c]; 3283 3284 u8 reserved_at_60[0x80]; 3285 }; 3286 3287 struct mlx5_ifc_dropped_packet_logged_bits { 3288 u8 reserved_at_0[0xe0]; 3289 }; 3290 3291 struct mlx5_ifc_default_timeout_bits { 3292 u8 to_multiplier[0x3]; 3293 u8 reserved_at_3[0x9]; 3294 u8 to_value[0x14]; 3295 }; 3296 3297 struct mlx5_ifc_dtor_reg_bits { 3298 u8 reserved_at_0[0x20]; 3299 3300 struct mlx5_ifc_default_timeout_bits pcie_toggle_to; 3301 3302 u8 reserved_at_40[0x60]; 3303 3304 struct mlx5_ifc_default_timeout_bits health_poll_to; 3305 3306 struct mlx5_ifc_default_timeout_bits full_crdump_to; 3307 3308 struct mlx5_ifc_default_timeout_bits fw_reset_to; 3309 3310 struct mlx5_ifc_default_timeout_bits flush_on_err_to; 3311 3312 struct mlx5_ifc_default_timeout_bits pci_sync_update_to; 3313 3314 struct mlx5_ifc_default_timeout_bits tear_down_to; 3315 3316 struct mlx5_ifc_default_timeout_bits fsm_reactivate_to; 3317 3318 struct mlx5_ifc_default_timeout_bits reclaim_pages_to; 3319 3320 struct mlx5_ifc_default_timeout_bits reclaim_vfs_pages_to; 3321 3322 struct mlx5_ifc_default_timeout_bits reset_unload_to; 3323 3324 u8 reserved_at_1c0[0x20]; 3325 }; 3326 3327 enum { 3328 MLX5_CQ_ERROR_SYNDROME_CQ_OVERRUN = 0x1, 3329 MLX5_CQ_ERROR_SYNDROME_CQ_ACCESS_VIOLATION_ERROR = 0x2, 3330 }; 3331 3332 struct mlx5_ifc_cq_error_bits { 3333 u8 reserved_at_0[0x8]; 3334 u8 cqn[0x18]; 3335 3336 u8 reserved_at_20[0x20]; 3337 3338 u8 reserved_at_40[0x18]; 3339 u8 syndrome[0x8]; 3340 3341 u8 reserved_at_60[0x80]; 3342 }; 3343 3344 struct mlx5_ifc_rdma_page_fault_event_bits { 3345 u8 bytes_committed[0x20]; 3346 3347 u8 r_key[0x20]; 3348 3349 u8 reserved_at_40[0x10]; 3350 u8 packet_len[0x10]; 3351 3352 u8 rdma_op_len[0x20]; 3353 3354 u8 rdma_va[0x40]; 3355 3356 u8 reserved_at_c0[0x5]; 3357 u8 rdma[0x1]; 3358 u8 write[0x1]; 3359 u8 requestor[0x1]; 3360 u8 qp_number[0x18]; 3361 }; 3362 3363 struct mlx5_ifc_wqe_associated_page_fault_event_bits { 3364 u8 bytes_committed[0x20]; 3365 3366 u8 reserved_at_20[0x10]; 3367 u8 wqe_index[0x10]; 3368 3369 u8 reserved_at_40[0x10]; 3370 u8 len[0x10]; 3371 3372 u8 reserved_at_60[0x60]; 3373 3374 u8 reserved_at_c0[0x5]; 3375 u8 rdma[0x1]; 3376 u8 write_read[0x1]; 3377 u8 requestor[0x1]; 3378 u8 qpn[0x18]; 3379 }; 3380 3381 struct mlx5_ifc_qp_events_bits { 3382 u8 reserved_at_0[0xa0]; 3383 3384 u8 type[0x8]; 3385 u8 reserved_at_a8[0x18]; 3386 3387 u8 reserved_at_c0[0x8]; 3388 u8 qpn_rqn_sqn[0x18]; 3389 }; 3390 3391 struct mlx5_ifc_dct_events_bits { 3392 u8 reserved_at_0[0xc0]; 3393 3394 u8 reserved_at_c0[0x8]; 3395 u8 dct_number[0x18]; 3396 }; 3397 3398 struct mlx5_ifc_comp_event_bits { 3399 u8 reserved_at_0[0xc0]; 3400 3401 u8 reserved_at_c0[0x8]; 3402 u8 cq_number[0x18]; 3403 }; 3404 3405 enum { 3406 MLX5_QPC_STATE_RST = 0x0, 3407 MLX5_QPC_STATE_INIT = 0x1, 3408 MLX5_QPC_STATE_RTR = 0x2, 3409 MLX5_QPC_STATE_RTS = 0x3, 3410 MLX5_QPC_STATE_SQER = 0x4, 3411 MLX5_QPC_STATE_ERR = 0x6, 3412 MLX5_QPC_STATE_SQD = 0x7, 3413 MLX5_QPC_STATE_SUSPENDED = 0x9, 3414 }; 3415 3416 enum { 3417 MLX5_QPC_ST_RC = 0x0, 3418 MLX5_QPC_ST_UC = 0x1, 3419 MLX5_QPC_ST_UD = 0x2, 3420 MLX5_QPC_ST_XRC = 0x3, 3421 MLX5_QPC_ST_DCI = 0x5, 3422 MLX5_QPC_ST_QP0 = 0x7, 3423 MLX5_QPC_ST_QP1 = 0x8, 3424 MLX5_QPC_ST_RAW_DATAGRAM = 0x9, 3425 MLX5_QPC_ST_REG_UMR = 0xc, 3426 }; 3427 3428 enum { 3429 MLX5_QPC_PM_STATE_ARMED = 0x0, 3430 MLX5_QPC_PM_STATE_REARM = 0x1, 3431 MLX5_QPC_PM_STATE_RESERVED = 0x2, 3432 MLX5_QPC_PM_STATE_MIGRATED = 0x3, 3433 }; 3434 3435 enum { 3436 MLX5_QPC_OFFLOAD_TYPE_RNDV = 0x1, 3437 }; 3438 3439 enum { 3440 MLX5_QPC_END_PADDING_MODE_SCATTER_AS_IS = 0x0, 3441 MLX5_QPC_END_PADDING_MODE_PAD_TO_CACHE_LINE_ALIGNMENT = 0x1, 3442 }; 3443 3444 enum { 3445 MLX5_QPC_MTU_256_BYTES = 0x1, 3446 MLX5_QPC_MTU_512_BYTES = 0x2, 3447 MLX5_QPC_MTU_1K_BYTES = 0x3, 3448 MLX5_QPC_MTU_2K_BYTES = 0x4, 3449 MLX5_QPC_MTU_4K_BYTES = 0x5, 3450 MLX5_QPC_MTU_RAW_ETHERNET_QP = 0x7, 3451 }; 3452 3453 enum { 3454 MLX5_QPC_ATOMIC_MODE_IB_SPEC = 0x1, 3455 MLX5_QPC_ATOMIC_MODE_ONLY_8B = 0x2, 3456 MLX5_QPC_ATOMIC_MODE_UP_TO_8B = 0x3, 3457 MLX5_QPC_ATOMIC_MODE_UP_TO_16B = 0x4, 3458 MLX5_QPC_ATOMIC_MODE_UP_TO_32B = 0x5, 3459 MLX5_QPC_ATOMIC_MODE_UP_TO_64B = 0x6, 3460 MLX5_QPC_ATOMIC_MODE_UP_TO_128B = 0x7, 3461 MLX5_QPC_ATOMIC_MODE_UP_TO_256B = 0x8, 3462 }; 3463 3464 enum { 3465 MLX5_QPC_CS_REQ_DISABLE = 0x0, 3466 MLX5_QPC_CS_REQ_UP_TO_32B = 0x11, 3467 MLX5_QPC_CS_REQ_UP_TO_64B = 0x22, 3468 }; 3469 3470 enum { 3471 MLX5_QPC_CS_RES_DISABLE = 0x0, 3472 MLX5_QPC_CS_RES_UP_TO_32B = 0x1, 3473 MLX5_QPC_CS_RES_UP_TO_64B = 0x2, 3474 }; 3475 3476 enum { 3477 MLX5_TIMESTAMP_FORMAT_FREE_RUNNING = 0x0, 3478 MLX5_TIMESTAMP_FORMAT_DEFAULT = 0x1, 3479 MLX5_TIMESTAMP_FORMAT_REAL_TIME = 0x2, 3480 }; 3481 3482 struct mlx5_ifc_qpc_bits { 3483 u8 state[0x4]; 3484 u8 lag_tx_port_affinity[0x4]; 3485 u8 st[0x8]; 3486 u8 reserved_at_10[0x2]; 3487 u8 isolate_vl_tc[0x1]; 3488 u8 pm_state[0x2]; 3489 u8 reserved_at_15[0x1]; 3490 u8 req_e2e_credit_mode[0x2]; 3491 u8 offload_type[0x4]; 3492 u8 end_padding_mode[0x2]; 3493 u8 reserved_at_1e[0x2]; 3494 3495 u8 wq_signature[0x1]; 3496 u8 block_lb_mc[0x1]; 3497 u8 atomic_like_write_en[0x1]; 3498 u8 latency_sensitive[0x1]; 3499 u8 reserved_at_24[0x1]; 3500 u8 drain_sigerr[0x1]; 3501 u8 reserved_at_26[0x2]; 3502 u8 pd[0x18]; 3503 3504 u8 mtu[0x3]; 3505 u8 log_msg_max[0x5]; 3506 u8 reserved_at_48[0x1]; 3507 u8 log_rq_size[0x4]; 3508 u8 log_rq_stride[0x3]; 3509 u8 no_sq[0x1]; 3510 u8 log_sq_size[0x4]; 3511 u8 reserved_at_55[0x1]; 3512 u8 retry_mode[0x2]; 3513 u8 ts_format[0x2]; 3514 u8 reserved_at_5a[0x1]; 3515 u8 rlky[0x1]; 3516 u8 ulp_stateless_offload_mode[0x4]; 3517 3518 u8 counter_set_id[0x8]; 3519 u8 uar_page[0x18]; 3520 3521 u8 reserved_at_80[0x8]; 3522 u8 user_index[0x18]; 3523 3524 u8 reserved_at_a0[0x3]; 3525 u8 log_page_size[0x5]; 3526 u8 remote_qpn[0x18]; 3527 3528 struct mlx5_ifc_ads_bits primary_address_path; 3529 3530 struct mlx5_ifc_ads_bits secondary_address_path; 3531 3532 u8 log_ack_req_freq[0x4]; 3533 u8 reserved_at_384[0x4]; 3534 u8 log_sra_max[0x3]; 3535 u8 reserved_at_38b[0x2]; 3536 u8 retry_count[0x3]; 3537 u8 rnr_retry[0x3]; 3538 u8 reserved_at_393[0x1]; 3539 u8 fre[0x1]; 3540 u8 cur_rnr_retry[0x3]; 3541 u8 cur_retry_count[0x3]; 3542 u8 reserved_at_39b[0x5]; 3543 3544 u8 reserved_at_3a0[0x20]; 3545 3546 u8 reserved_at_3c0[0x8]; 3547 u8 next_send_psn[0x18]; 3548 3549 u8 reserved_at_3e0[0x3]; 3550 u8 log_num_dci_stream_channels[0x5]; 3551 u8 cqn_snd[0x18]; 3552 3553 u8 reserved_at_400[0x3]; 3554 u8 log_num_dci_errored_streams[0x5]; 3555 u8 deth_sqpn[0x18]; 3556 3557 u8 reserved_at_420[0x20]; 3558 3559 u8 reserved_at_440[0x8]; 3560 u8 last_acked_psn[0x18]; 3561 3562 u8 reserved_at_460[0x8]; 3563 u8 ssn[0x18]; 3564 3565 u8 reserved_at_480[0x8]; 3566 u8 log_rra_max[0x3]; 3567 u8 reserved_at_48b[0x1]; 3568 u8 atomic_mode[0x4]; 3569 u8 rre[0x1]; 3570 u8 rwe[0x1]; 3571 u8 rae[0x1]; 3572 u8 reserved_at_493[0x1]; 3573 u8 page_offset[0x6]; 3574 u8 reserved_at_49a[0x3]; 3575 u8 cd_slave_receive[0x1]; 3576 u8 cd_slave_send[0x1]; 3577 u8 cd_master[0x1]; 3578 3579 u8 reserved_at_4a0[0x3]; 3580 u8 min_rnr_nak[0x5]; 3581 u8 next_rcv_psn[0x18]; 3582 3583 u8 reserved_at_4c0[0x8]; 3584 u8 xrcd[0x18]; 3585 3586 u8 reserved_at_4e0[0x8]; 3587 u8 cqn_rcv[0x18]; 3588 3589 u8 dbr_addr[0x40]; 3590 3591 u8 q_key[0x20]; 3592 3593 u8 reserved_at_560[0x5]; 3594 u8 rq_type[0x3]; 3595 u8 srqn_rmpn_xrqn[0x18]; 3596 3597 u8 reserved_at_580[0x8]; 3598 u8 rmsn[0x18]; 3599 3600 u8 hw_sq_wqebb_counter[0x10]; 3601 u8 sw_sq_wqebb_counter[0x10]; 3602 3603 u8 hw_rq_counter[0x20]; 3604 3605 u8 sw_rq_counter[0x20]; 3606 3607 u8 reserved_at_600[0x20]; 3608 3609 u8 reserved_at_620[0xf]; 3610 u8 cgs[0x1]; 3611 u8 cs_req[0x8]; 3612 u8 cs_res[0x8]; 3613 3614 u8 dc_access_key[0x40]; 3615 3616 u8 reserved_at_680[0x3]; 3617 u8 dbr_umem_valid[0x1]; 3618 3619 u8 reserved_at_684[0xbc]; 3620 }; 3621 3622 struct mlx5_ifc_roce_addr_layout_bits { 3623 u8 source_l3_address[16][0x8]; 3624 3625 u8 reserved_at_80[0x3]; 3626 u8 vlan_valid[0x1]; 3627 u8 vlan_id[0xc]; 3628 u8 source_mac_47_32[0x10]; 3629 3630 u8 source_mac_31_0[0x20]; 3631 3632 u8 reserved_at_c0[0x14]; 3633 u8 roce_l3_type[0x4]; 3634 u8 roce_version[0x8]; 3635 3636 u8 reserved_at_e0[0x20]; 3637 }; 3638 3639 struct mlx5_ifc_crypto_cap_bits { 3640 u8 reserved_at_0[0x3]; 3641 u8 synchronize_dek[0x1]; 3642 u8 int_kek_manual[0x1]; 3643 u8 int_kek_auto[0x1]; 3644 u8 reserved_at_6[0x1a]; 3645 3646 u8 reserved_at_20[0x3]; 3647 u8 log_dek_max_alloc[0x5]; 3648 u8 reserved_at_28[0x3]; 3649 u8 log_max_num_deks[0x5]; 3650 u8 reserved_at_30[0x10]; 3651 3652 u8 reserved_at_40[0x20]; 3653 3654 u8 reserved_at_60[0x3]; 3655 u8 log_dek_granularity[0x5]; 3656 u8 reserved_at_68[0x3]; 3657 u8 log_max_num_int_kek[0x5]; 3658 u8 sw_wrapped_dek[0x10]; 3659 3660 u8 reserved_at_80[0x780]; 3661 }; 3662 3663 union mlx5_ifc_hca_cap_union_bits { 3664 struct mlx5_ifc_cmd_hca_cap_bits cmd_hca_cap; 3665 struct mlx5_ifc_cmd_hca_cap_2_bits cmd_hca_cap_2; 3666 struct mlx5_ifc_odp_cap_bits odp_cap; 3667 struct mlx5_ifc_atomic_caps_bits atomic_caps; 3668 struct mlx5_ifc_roce_cap_bits roce_cap; 3669 struct mlx5_ifc_per_protocol_networking_offload_caps_bits per_protocol_networking_offload_caps; 3670 struct mlx5_ifc_flow_table_nic_cap_bits flow_table_nic_cap; 3671 struct mlx5_ifc_flow_table_eswitch_cap_bits flow_table_eswitch_cap; 3672 struct mlx5_ifc_wqe_based_flow_table_cap_bits wqe_based_flow_table_cap; 3673 struct mlx5_ifc_esw_cap_bits esw_cap; 3674 struct mlx5_ifc_e_switch_cap_bits e_switch_cap; 3675 struct mlx5_ifc_port_selection_cap_bits port_selection_cap; 3676 struct mlx5_ifc_qos_cap_bits qos_cap; 3677 struct mlx5_ifc_debug_cap_bits debug_cap; 3678 struct mlx5_ifc_fpga_cap_bits fpga_cap; 3679 struct mlx5_ifc_tls_cap_bits tls_cap; 3680 struct mlx5_ifc_device_mem_cap_bits device_mem_cap; 3681 struct mlx5_ifc_virtio_emulation_cap_bits virtio_emulation_cap; 3682 struct mlx5_ifc_macsec_cap_bits macsec_cap; 3683 struct mlx5_ifc_crypto_cap_bits crypto_cap; 3684 struct mlx5_ifc_ipsec_cap_bits ipsec_cap; 3685 u8 reserved_at_0[0x8000]; 3686 }; 3687 3688 enum { 3689 MLX5_FLOW_CONTEXT_ACTION_ALLOW = 0x1, 3690 MLX5_FLOW_CONTEXT_ACTION_DROP = 0x2, 3691 MLX5_FLOW_CONTEXT_ACTION_FWD_DEST = 0x4, 3692 MLX5_FLOW_CONTEXT_ACTION_COUNT = 0x8, 3693 MLX5_FLOW_CONTEXT_ACTION_PACKET_REFORMAT = 0x10, 3694 MLX5_FLOW_CONTEXT_ACTION_DECAP = 0x20, 3695 MLX5_FLOW_CONTEXT_ACTION_MOD_HDR = 0x40, 3696 MLX5_FLOW_CONTEXT_ACTION_VLAN_POP = 0x80, 3697 MLX5_FLOW_CONTEXT_ACTION_VLAN_PUSH = 0x100, 3698 MLX5_FLOW_CONTEXT_ACTION_VLAN_POP_2 = 0x400, 3699 MLX5_FLOW_CONTEXT_ACTION_VLAN_PUSH_2 = 0x800, 3700 MLX5_FLOW_CONTEXT_ACTION_CRYPTO_DECRYPT = 0x1000, 3701 MLX5_FLOW_CONTEXT_ACTION_CRYPTO_ENCRYPT = 0x2000, 3702 MLX5_FLOW_CONTEXT_ACTION_EXECUTE_ASO = 0x4000, 3703 }; 3704 3705 enum { 3706 MLX5_FLOW_CONTEXT_FLOW_SOURCE_ANY_VPORT = 0x0, 3707 MLX5_FLOW_CONTEXT_FLOW_SOURCE_UPLINK = 0x1, 3708 MLX5_FLOW_CONTEXT_FLOW_SOURCE_LOCAL_VPORT = 0x2, 3709 }; 3710 3711 enum { 3712 MLX5_FLOW_CONTEXT_ENCRYPT_DECRYPT_TYPE_IPSEC = 0x0, 3713 MLX5_FLOW_CONTEXT_ENCRYPT_DECRYPT_TYPE_MACSEC = 0x1, 3714 }; 3715 3716 struct mlx5_ifc_vlan_bits { 3717 u8 ethtype[0x10]; 3718 u8 prio[0x3]; 3719 u8 cfi[0x1]; 3720 u8 vid[0xc]; 3721 }; 3722 3723 enum { 3724 MLX5_FLOW_METER_COLOR_RED = 0x0, 3725 MLX5_FLOW_METER_COLOR_YELLOW = 0x1, 3726 MLX5_FLOW_METER_COLOR_GREEN = 0x2, 3727 MLX5_FLOW_METER_COLOR_UNDEFINED = 0x3, 3728 }; 3729 3730 enum { 3731 MLX5_EXE_ASO_FLOW_METER = 0x2, 3732 }; 3733 3734 struct mlx5_ifc_exe_aso_ctrl_flow_meter_bits { 3735 u8 return_reg_id[0x4]; 3736 u8 aso_type[0x4]; 3737 u8 reserved_at_8[0x14]; 3738 u8 action[0x1]; 3739 u8 init_color[0x2]; 3740 u8 meter_id[0x1]; 3741 }; 3742 3743 union mlx5_ifc_exe_aso_ctrl { 3744 struct mlx5_ifc_exe_aso_ctrl_flow_meter_bits exe_aso_ctrl_flow_meter; 3745 }; 3746 3747 struct mlx5_ifc_execute_aso_bits { 3748 u8 valid[0x1]; 3749 u8 reserved_at_1[0x7]; 3750 u8 aso_object_id[0x18]; 3751 3752 union mlx5_ifc_exe_aso_ctrl exe_aso_ctrl; 3753 }; 3754 3755 struct mlx5_ifc_flow_context_bits { 3756 struct mlx5_ifc_vlan_bits push_vlan; 3757 3758 u8 group_id[0x20]; 3759 3760 u8 reserved_at_40[0x8]; 3761 u8 flow_tag[0x18]; 3762 3763 u8 reserved_at_60[0x10]; 3764 u8 action[0x10]; 3765 3766 u8 extended_destination[0x1]; 3767 u8 uplink_hairpin_en[0x1]; 3768 u8 flow_source[0x2]; 3769 u8 encrypt_decrypt_type[0x4]; 3770 u8 destination_list_size[0x18]; 3771 3772 u8 reserved_at_a0[0x8]; 3773 u8 flow_counter_list_size[0x18]; 3774 3775 u8 packet_reformat_id[0x20]; 3776 3777 u8 modify_header_id[0x20]; 3778 3779 struct mlx5_ifc_vlan_bits push_vlan_2; 3780 3781 u8 encrypt_decrypt_obj_id[0x20]; 3782 u8 reserved_at_140[0xc0]; 3783 3784 struct mlx5_ifc_fte_match_param_bits match_value; 3785 3786 struct mlx5_ifc_execute_aso_bits execute_aso[4]; 3787 3788 u8 reserved_at_1300[0x500]; 3789 3790 union mlx5_ifc_dest_format_flow_counter_list_auto_bits destination[]; 3791 }; 3792 3793 enum { 3794 MLX5_XRC_SRQC_STATE_GOOD = 0x0, 3795 MLX5_XRC_SRQC_STATE_ERROR = 0x1, 3796 }; 3797 3798 struct mlx5_ifc_xrc_srqc_bits { 3799 u8 state[0x4]; 3800 u8 log_xrc_srq_size[0x4]; 3801 u8 reserved_at_8[0x18]; 3802 3803 u8 wq_signature[0x1]; 3804 u8 cont_srq[0x1]; 3805 u8 reserved_at_22[0x1]; 3806 u8 rlky[0x1]; 3807 u8 basic_cyclic_rcv_wqe[0x1]; 3808 u8 log_rq_stride[0x3]; 3809 u8 xrcd[0x18]; 3810 3811 u8 page_offset[0x6]; 3812 u8 reserved_at_46[0x1]; 3813 u8 dbr_umem_valid[0x1]; 3814 u8 cqn[0x18]; 3815 3816 u8 reserved_at_60[0x20]; 3817 3818 u8 user_index_equal_xrc_srqn[0x1]; 3819 u8 reserved_at_81[0x1]; 3820 u8 log_page_size[0x6]; 3821 u8 user_index[0x18]; 3822 3823 u8 reserved_at_a0[0x20]; 3824 3825 u8 reserved_at_c0[0x8]; 3826 u8 pd[0x18]; 3827 3828 u8 lwm[0x10]; 3829 u8 wqe_cnt[0x10]; 3830 3831 u8 reserved_at_100[0x40]; 3832 3833 u8 db_record_addr_h[0x20]; 3834 3835 u8 db_record_addr_l[0x1e]; 3836 u8 reserved_at_17e[0x2]; 3837 3838 u8 reserved_at_180[0x80]; 3839 }; 3840 3841 struct mlx5_ifc_vnic_diagnostic_statistics_bits { 3842 u8 counter_error_queues[0x20]; 3843 3844 u8 total_error_queues[0x20]; 3845 3846 u8 send_queue_priority_update_flow[0x20]; 3847 3848 u8 reserved_at_60[0x20]; 3849 3850 u8 nic_receive_steering_discard[0x40]; 3851 3852 u8 receive_discard_vport_down[0x40]; 3853 3854 u8 transmit_discard_vport_down[0x40]; 3855 3856 u8 async_eq_overrun[0x20]; 3857 3858 u8 comp_eq_overrun[0x20]; 3859 3860 u8 reserved_at_180[0x20]; 3861 3862 u8 invalid_command[0x20]; 3863 3864 u8 quota_exceeded_command[0x20]; 3865 3866 u8 internal_rq_out_of_buffer[0x20]; 3867 3868 u8 cq_overrun[0x20]; 3869 3870 u8 eth_wqe_too_small[0x20]; 3871 3872 u8 reserved_at_220[0xc0]; 3873 3874 u8 generated_pkt_steering_fail[0x40]; 3875 3876 u8 handled_pkt_steering_fail[0x40]; 3877 3878 u8 reserved_at_360[0xc80]; 3879 }; 3880 3881 struct mlx5_ifc_traffic_counter_bits { 3882 u8 packets[0x40]; 3883 3884 u8 octets[0x40]; 3885 }; 3886 3887 struct mlx5_ifc_tisc_bits { 3888 u8 strict_lag_tx_port_affinity[0x1]; 3889 u8 tls_en[0x1]; 3890 u8 reserved_at_2[0x2]; 3891 u8 lag_tx_port_affinity[0x04]; 3892 3893 u8 reserved_at_8[0x4]; 3894 u8 prio[0x4]; 3895 u8 reserved_at_10[0x10]; 3896 3897 u8 reserved_at_20[0x100]; 3898 3899 u8 reserved_at_120[0x8]; 3900 u8 transport_domain[0x18]; 3901 3902 u8 reserved_at_140[0x8]; 3903 u8 underlay_qpn[0x18]; 3904 3905 u8 reserved_at_160[0x8]; 3906 u8 pd[0x18]; 3907 3908 u8 reserved_at_180[0x380]; 3909 }; 3910 3911 enum { 3912 MLX5_TIRC_DISP_TYPE_DIRECT = 0x0, 3913 MLX5_TIRC_DISP_TYPE_INDIRECT = 0x1, 3914 }; 3915 3916 enum { 3917 MLX5_TIRC_PACKET_MERGE_MASK_IPV4_LRO = BIT(0), 3918 MLX5_TIRC_PACKET_MERGE_MASK_IPV6_LRO = BIT(1), 3919 }; 3920 3921 enum { 3922 MLX5_RX_HASH_FN_NONE = 0x0, 3923 MLX5_RX_HASH_FN_INVERTED_XOR8 = 0x1, 3924 MLX5_RX_HASH_FN_TOEPLITZ = 0x2, 3925 }; 3926 3927 enum { 3928 MLX5_TIRC_SELF_LB_BLOCK_BLOCK_UNICAST = 0x1, 3929 MLX5_TIRC_SELF_LB_BLOCK_BLOCK_MULTICAST = 0x2, 3930 }; 3931 3932 struct mlx5_ifc_tirc_bits { 3933 u8 reserved_at_0[0x20]; 3934 3935 u8 disp_type[0x4]; 3936 u8 tls_en[0x1]; 3937 u8 reserved_at_25[0x1b]; 3938 3939 u8 reserved_at_40[0x40]; 3940 3941 u8 reserved_at_80[0x4]; 3942 u8 lro_timeout_period_usecs[0x10]; 3943 u8 packet_merge_mask[0x4]; 3944 u8 lro_max_ip_payload_size[0x8]; 3945 3946 u8 reserved_at_a0[0x40]; 3947 3948 u8 reserved_at_e0[0x8]; 3949 u8 inline_rqn[0x18]; 3950 3951 u8 rx_hash_symmetric[0x1]; 3952 u8 reserved_at_101[0x1]; 3953 u8 tunneled_offload_en[0x1]; 3954 u8 reserved_at_103[0x5]; 3955 u8 indirect_table[0x18]; 3956 3957 u8 rx_hash_fn[0x4]; 3958 u8 reserved_at_124[0x2]; 3959 u8 self_lb_block[0x2]; 3960 u8 transport_domain[0x18]; 3961 3962 u8 rx_hash_toeplitz_key[10][0x20]; 3963 3964 struct mlx5_ifc_rx_hash_field_select_bits rx_hash_field_selector_outer; 3965 3966 struct mlx5_ifc_rx_hash_field_select_bits rx_hash_field_selector_inner; 3967 3968 u8 reserved_at_2c0[0x4c0]; 3969 }; 3970 3971 enum { 3972 MLX5_SRQC_STATE_GOOD = 0x0, 3973 MLX5_SRQC_STATE_ERROR = 0x1, 3974 }; 3975 3976 struct mlx5_ifc_srqc_bits { 3977 u8 state[0x4]; 3978 u8 log_srq_size[0x4]; 3979 u8 reserved_at_8[0x18]; 3980 3981 u8 wq_signature[0x1]; 3982 u8 cont_srq[0x1]; 3983 u8 reserved_at_22[0x1]; 3984 u8 rlky[0x1]; 3985 u8 reserved_at_24[0x1]; 3986 u8 log_rq_stride[0x3]; 3987 u8 xrcd[0x18]; 3988 3989 u8 page_offset[0x6]; 3990 u8 reserved_at_46[0x2]; 3991 u8 cqn[0x18]; 3992 3993 u8 reserved_at_60[0x20]; 3994 3995 u8 reserved_at_80[0x2]; 3996 u8 log_page_size[0x6]; 3997 u8 reserved_at_88[0x18]; 3998 3999 u8 reserved_at_a0[0x20]; 4000 4001 u8 reserved_at_c0[0x8]; 4002 u8 pd[0x18]; 4003 4004 u8 lwm[0x10]; 4005 u8 wqe_cnt[0x10]; 4006 4007 u8 reserved_at_100[0x40]; 4008 4009 u8 dbr_addr[0x40]; 4010 4011 u8 reserved_at_180[0x80]; 4012 }; 4013 4014 enum { 4015 MLX5_SQC_STATE_RST = 0x0, 4016 MLX5_SQC_STATE_RDY = 0x1, 4017 MLX5_SQC_STATE_ERR = 0x3, 4018 }; 4019 4020 struct mlx5_ifc_sqc_bits { 4021 u8 rlky[0x1]; 4022 u8 cd_master[0x1]; 4023 u8 fre[0x1]; 4024 u8 flush_in_error_en[0x1]; 4025 u8 allow_multi_pkt_send_wqe[0x1]; 4026 u8 min_wqe_inline_mode[0x3]; 4027 u8 state[0x4]; 4028 u8 reg_umr[0x1]; 4029 u8 allow_swp[0x1]; 4030 u8 hairpin[0x1]; 4031 u8 non_wire[0x1]; 4032 u8 reserved_at_10[0xa]; 4033 u8 ts_format[0x2]; 4034 u8 reserved_at_1c[0x4]; 4035 4036 u8 reserved_at_20[0x8]; 4037 u8 user_index[0x18]; 4038 4039 u8 reserved_at_40[0x8]; 4040 u8 cqn[0x18]; 4041 4042 u8 reserved_at_60[0x8]; 4043 u8 hairpin_peer_rq[0x18]; 4044 4045 u8 reserved_at_80[0x10]; 4046 u8 hairpin_peer_vhca[0x10]; 4047 4048 u8 reserved_at_a0[0x20]; 4049 4050 u8 reserved_at_c0[0x8]; 4051 u8 ts_cqe_to_dest_cqn[0x18]; 4052 4053 u8 reserved_at_e0[0x10]; 4054 u8 packet_pacing_rate_limit_index[0x10]; 4055 u8 tis_lst_sz[0x10]; 4056 u8 qos_queue_group_id[0x10]; 4057 4058 u8 reserved_at_120[0x40]; 4059 4060 u8 reserved_at_160[0x8]; 4061 u8 tis_num_0[0x18]; 4062 4063 struct mlx5_ifc_wq_bits wq; 4064 }; 4065 4066 enum { 4067 SCHEDULING_CONTEXT_ELEMENT_TYPE_TSAR = 0x0, 4068 SCHEDULING_CONTEXT_ELEMENT_TYPE_VPORT = 0x1, 4069 SCHEDULING_CONTEXT_ELEMENT_TYPE_VPORT_TC = 0x2, 4070 SCHEDULING_CONTEXT_ELEMENT_TYPE_PARA_VPORT_TC = 0x3, 4071 SCHEDULING_CONTEXT_ELEMENT_TYPE_QUEUE_GROUP = 0x4, 4072 }; 4073 4074 enum { 4075 ELEMENT_TYPE_CAP_MASK_TSAR = 1 << 0, 4076 ELEMENT_TYPE_CAP_MASK_VPORT = 1 << 1, 4077 ELEMENT_TYPE_CAP_MASK_VPORT_TC = 1 << 2, 4078 ELEMENT_TYPE_CAP_MASK_PARA_VPORT_TC = 1 << 3, 4079 }; 4080 4081 struct mlx5_ifc_scheduling_context_bits { 4082 u8 element_type[0x8]; 4083 u8 reserved_at_8[0x18]; 4084 4085 u8 element_attributes[0x20]; 4086 4087 u8 parent_element_id[0x20]; 4088 4089 u8 reserved_at_60[0x40]; 4090 4091 u8 bw_share[0x20]; 4092 4093 u8 max_average_bw[0x20]; 4094 4095 u8 reserved_at_e0[0x120]; 4096 }; 4097 4098 struct mlx5_ifc_rqtc_bits { 4099 u8 reserved_at_0[0xa0]; 4100 4101 u8 reserved_at_a0[0x5]; 4102 u8 list_q_type[0x3]; 4103 u8 reserved_at_a8[0x8]; 4104 u8 rqt_max_size[0x10]; 4105 4106 u8 rq_vhca_id_format[0x1]; 4107 u8 reserved_at_c1[0xf]; 4108 u8 rqt_actual_size[0x10]; 4109 4110 u8 reserved_at_e0[0x6a0]; 4111 4112 union { 4113 DECLARE_FLEX_ARRAY(struct mlx5_ifc_rq_num_bits, rq_num); 4114 DECLARE_FLEX_ARRAY(struct mlx5_ifc_rq_vhca_bits, rq_vhca); 4115 }; 4116 }; 4117 4118 enum { 4119 MLX5_RQC_MEM_RQ_TYPE_MEMORY_RQ_INLINE = 0x0, 4120 MLX5_RQC_MEM_RQ_TYPE_MEMORY_RQ_RMP = 0x1, 4121 }; 4122 4123 enum { 4124 MLX5_RQC_STATE_RST = 0x0, 4125 MLX5_RQC_STATE_RDY = 0x1, 4126 MLX5_RQC_STATE_ERR = 0x3, 4127 }; 4128 4129 enum { 4130 MLX5_RQC_SHAMPO_NO_MATCH_ALIGNMENT_GRANULARITY_BYTE = 0x0, 4131 MLX5_RQC_SHAMPO_NO_MATCH_ALIGNMENT_GRANULARITY_STRIDE = 0x1, 4132 MLX5_RQC_SHAMPO_NO_MATCH_ALIGNMENT_GRANULARITY_PAGE = 0x2, 4133 }; 4134 4135 enum { 4136 MLX5_RQC_SHAMPO_MATCH_CRITERIA_TYPE_NO_MATCH = 0x0, 4137 MLX5_RQC_SHAMPO_MATCH_CRITERIA_TYPE_EXTENDED = 0x1, 4138 MLX5_RQC_SHAMPO_MATCH_CRITERIA_TYPE_FIVE_TUPLE = 0x2, 4139 }; 4140 4141 struct mlx5_ifc_rqc_bits { 4142 u8 rlky[0x1]; 4143 u8 delay_drop_en[0x1]; 4144 u8 scatter_fcs[0x1]; 4145 u8 vsd[0x1]; 4146 u8 mem_rq_type[0x4]; 4147 u8 state[0x4]; 4148 u8 reserved_at_c[0x1]; 4149 u8 flush_in_error_en[0x1]; 4150 u8 hairpin[0x1]; 4151 u8 reserved_at_f[0xb]; 4152 u8 ts_format[0x2]; 4153 u8 reserved_at_1c[0x4]; 4154 4155 u8 reserved_at_20[0x8]; 4156 u8 user_index[0x18]; 4157 4158 u8 reserved_at_40[0x8]; 4159 u8 cqn[0x18]; 4160 4161 u8 counter_set_id[0x8]; 4162 u8 reserved_at_68[0x18]; 4163 4164 u8 reserved_at_80[0x8]; 4165 u8 rmpn[0x18]; 4166 4167 u8 reserved_at_a0[0x8]; 4168 u8 hairpin_peer_sq[0x18]; 4169 4170 u8 reserved_at_c0[0x10]; 4171 u8 hairpin_peer_vhca[0x10]; 4172 4173 u8 reserved_at_e0[0x46]; 4174 u8 shampo_no_match_alignment_granularity[0x2]; 4175 u8 reserved_at_128[0x6]; 4176 u8 shampo_match_criteria_type[0x2]; 4177 u8 reservation_timeout[0x10]; 4178 4179 u8 reserved_at_140[0x40]; 4180 4181 struct mlx5_ifc_wq_bits wq; 4182 }; 4183 4184 enum { 4185 MLX5_RMPC_STATE_RDY = 0x1, 4186 MLX5_RMPC_STATE_ERR = 0x3, 4187 }; 4188 4189 struct mlx5_ifc_rmpc_bits { 4190 u8 reserved_at_0[0x8]; 4191 u8 state[0x4]; 4192 u8 reserved_at_c[0x14]; 4193 4194 u8 basic_cyclic_rcv_wqe[0x1]; 4195 u8 reserved_at_21[0x1f]; 4196 4197 u8 reserved_at_40[0x140]; 4198 4199 struct mlx5_ifc_wq_bits wq; 4200 }; 4201 4202 enum { 4203 VHCA_ID_TYPE_HW = 0, 4204 VHCA_ID_TYPE_SW = 1, 4205 }; 4206 4207 struct mlx5_ifc_nic_vport_context_bits { 4208 u8 reserved_at_0[0x5]; 4209 u8 min_wqe_inline_mode[0x3]; 4210 u8 reserved_at_8[0x15]; 4211 u8 disable_mc_local_lb[0x1]; 4212 u8 disable_uc_local_lb[0x1]; 4213 u8 roce_en[0x1]; 4214 4215 u8 arm_change_event[0x1]; 4216 u8 reserved_at_21[0x1a]; 4217 u8 event_on_mtu[0x1]; 4218 u8 event_on_promisc_change[0x1]; 4219 u8 event_on_vlan_change[0x1]; 4220 u8 event_on_mc_address_change[0x1]; 4221 u8 event_on_uc_address_change[0x1]; 4222 4223 u8 vhca_id_type[0x1]; 4224 u8 reserved_at_41[0xb]; 4225 u8 affiliation_criteria[0x4]; 4226 u8 affiliated_vhca_id[0x10]; 4227 4228 u8 reserved_at_60[0xa0]; 4229 4230 u8 reserved_at_100[0x1]; 4231 u8 sd_group[0x3]; 4232 u8 reserved_at_104[0x1c]; 4233 4234 u8 reserved_at_120[0x10]; 4235 u8 mtu[0x10]; 4236 4237 u8 system_image_guid[0x40]; 4238 u8 port_guid[0x40]; 4239 u8 node_guid[0x40]; 4240 4241 u8 reserved_at_200[0x140]; 4242 u8 qkey_violation_counter[0x10]; 4243 u8 reserved_at_350[0x430]; 4244 4245 u8 promisc_uc[0x1]; 4246 u8 promisc_mc[0x1]; 4247 u8 promisc_all[0x1]; 4248 u8 reserved_at_783[0x2]; 4249 u8 allowed_list_type[0x3]; 4250 u8 reserved_at_788[0xc]; 4251 u8 allowed_list_size[0xc]; 4252 4253 struct mlx5_ifc_mac_address_layout_bits permanent_address; 4254 4255 u8 reserved_at_7e0[0x20]; 4256 4257 u8 current_uc_mac_address[][0x40]; 4258 }; 4259 4260 enum { 4261 MLX5_MKC_ACCESS_MODE_PA = 0x0, 4262 MLX5_MKC_ACCESS_MODE_MTT = 0x1, 4263 MLX5_MKC_ACCESS_MODE_KLMS = 0x2, 4264 MLX5_MKC_ACCESS_MODE_KSM = 0x3, 4265 MLX5_MKC_ACCESS_MODE_SW_ICM = 0x4, 4266 MLX5_MKC_ACCESS_MODE_MEMIC = 0x5, 4267 }; 4268 4269 struct mlx5_ifc_mkc_bits { 4270 u8 reserved_at_0[0x1]; 4271 u8 free[0x1]; 4272 u8 reserved_at_2[0x1]; 4273 u8 access_mode_4_2[0x3]; 4274 u8 reserved_at_6[0x7]; 4275 u8 relaxed_ordering_write[0x1]; 4276 u8 reserved_at_e[0x1]; 4277 u8 small_fence_on_rdma_read_response[0x1]; 4278 u8 umr_en[0x1]; 4279 u8 a[0x1]; 4280 u8 rw[0x1]; 4281 u8 rr[0x1]; 4282 u8 lw[0x1]; 4283 u8 lr[0x1]; 4284 u8 access_mode_1_0[0x2]; 4285 u8 reserved_at_18[0x2]; 4286 u8 ma_translation_mode[0x2]; 4287 u8 reserved_at_1c[0x4]; 4288 4289 u8 qpn[0x18]; 4290 u8 mkey_7_0[0x8]; 4291 4292 u8 reserved_at_40[0x20]; 4293 4294 u8 length64[0x1]; 4295 u8 bsf_en[0x1]; 4296 u8 sync_umr[0x1]; 4297 u8 reserved_at_63[0x2]; 4298 u8 expected_sigerr_count[0x1]; 4299 u8 reserved_at_66[0x1]; 4300 u8 en_rinval[0x1]; 4301 u8 pd[0x18]; 4302 4303 u8 start_addr[0x40]; 4304 4305 u8 len[0x40]; 4306 4307 u8 bsf_octword_size[0x20]; 4308 4309 u8 reserved_at_120[0x80]; 4310 4311 u8 translations_octword_size[0x20]; 4312 4313 u8 reserved_at_1c0[0x19]; 4314 u8 relaxed_ordering_read[0x1]; 4315 u8 reserved_at_1d9[0x1]; 4316 u8 log_page_size[0x5]; 4317 4318 u8 reserved_at_1e0[0x20]; 4319 }; 4320 4321 struct mlx5_ifc_pkey_bits { 4322 u8 reserved_at_0[0x10]; 4323 u8 pkey[0x10]; 4324 }; 4325 4326 struct mlx5_ifc_array128_auto_bits { 4327 u8 array128_auto[16][0x8]; 4328 }; 4329 4330 struct mlx5_ifc_hca_vport_context_bits { 4331 u8 field_select[0x20]; 4332 4333 u8 reserved_at_20[0xe0]; 4334 4335 u8 sm_virt_aware[0x1]; 4336 u8 has_smi[0x1]; 4337 u8 has_raw[0x1]; 4338 u8 grh_required[0x1]; 4339 u8 reserved_at_104[0x4]; 4340 u8 num_port_plane[0x8]; 4341 u8 port_physical_state[0x4]; 4342 u8 vport_state_policy[0x4]; 4343 u8 port_state[0x4]; 4344 u8 vport_state[0x4]; 4345 4346 u8 reserved_at_120[0x20]; 4347 4348 u8 system_image_guid[0x40]; 4349 4350 u8 port_guid[0x40]; 4351 4352 u8 node_guid[0x40]; 4353 4354 u8 cap_mask1[0x20]; 4355 4356 u8 cap_mask1_field_select[0x20]; 4357 4358 u8 cap_mask2[0x20]; 4359 4360 u8 cap_mask2_field_select[0x20]; 4361 4362 u8 reserved_at_280[0x80]; 4363 4364 u8 lid[0x10]; 4365 u8 reserved_at_310[0x4]; 4366 u8 init_type_reply[0x4]; 4367 u8 lmc[0x3]; 4368 u8 subnet_timeout[0x5]; 4369 4370 u8 sm_lid[0x10]; 4371 u8 sm_sl[0x4]; 4372 u8 reserved_at_334[0xc]; 4373 4374 u8 qkey_violation_counter[0x10]; 4375 u8 pkey_violation_counter[0x10]; 4376 4377 u8 reserved_at_360[0xca0]; 4378 }; 4379 4380 struct mlx5_ifc_esw_vport_context_bits { 4381 u8 fdb_to_vport_reg_c[0x1]; 4382 u8 reserved_at_1[0x2]; 4383 u8 vport_svlan_strip[0x1]; 4384 u8 vport_cvlan_strip[0x1]; 4385 u8 vport_svlan_insert[0x1]; 4386 u8 vport_cvlan_insert[0x2]; 4387 u8 fdb_to_vport_reg_c_id[0x8]; 4388 u8 reserved_at_10[0x10]; 4389 4390 u8 reserved_at_20[0x20]; 4391 4392 u8 svlan_cfi[0x1]; 4393 u8 svlan_pcp[0x3]; 4394 u8 svlan_id[0xc]; 4395 u8 cvlan_cfi[0x1]; 4396 u8 cvlan_pcp[0x3]; 4397 u8 cvlan_id[0xc]; 4398 4399 u8 reserved_at_60[0x720]; 4400 4401 u8 sw_steering_vport_icm_address_rx[0x40]; 4402 4403 u8 sw_steering_vport_icm_address_tx[0x40]; 4404 }; 4405 4406 enum { 4407 MLX5_EQC_STATUS_OK = 0x0, 4408 MLX5_EQC_STATUS_EQ_WRITE_FAILURE = 0xa, 4409 }; 4410 4411 enum { 4412 MLX5_EQC_ST_ARMED = 0x9, 4413 MLX5_EQC_ST_FIRED = 0xa, 4414 }; 4415 4416 struct mlx5_ifc_eqc_bits { 4417 u8 status[0x4]; 4418 u8 reserved_at_4[0x9]; 4419 u8 ec[0x1]; 4420 u8 oi[0x1]; 4421 u8 reserved_at_f[0x5]; 4422 u8 st[0x4]; 4423 u8 reserved_at_18[0x8]; 4424 4425 u8 reserved_at_20[0x20]; 4426 4427 u8 reserved_at_40[0x14]; 4428 u8 page_offset[0x6]; 4429 u8 reserved_at_5a[0x6]; 4430 4431 u8 reserved_at_60[0x3]; 4432 u8 log_eq_size[0x5]; 4433 u8 uar_page[0x18]; 4434 4435 u8 reserved_at_80[0x20]; 4436 4437 u8 reserved_at_a0[0x14]; 4438 u8 intr[0xc]; 4439 4440 u8 reserved_at_c0[0x3]; 4441 u8 log_page_size[0x5]; 4442 u8 reserved_at_c8[0x18]; 4443 4444 u8 reserved_at_e0[0x60]; 4445 4446 u8 reserved_at_140[0x8]; 4447 u8 consumer_counter[0x18]; 4448 4449 u8 reserved_at_160[0x8]; 4450 u8 producer_counter[0x18]; 4451 4452 u8 reserved_at_180[0x80]; 4453 }; 4454 4455 enum { 4456 MLX5_DCTC_STATE_ACTIVE = 0x0, 4457 MLX5_DCTC_STATE_DRAINING = 0x1, 4458 MLX5_DCTC_STATE_DRAINED = 0x2, 4459 }; 4460 4461 enum { 4462 MLX5_DCTC_CS_RES_DISABLE = 0x0, 4463 MLX5_DCTC_CS_RES_NA = 0x1, 4464 MLX5_DCTC_CS_RES_UP_TO_64B = 0x2, 4465 }; 4466 4467 enum { 4468 MLX5_DCTC_MTU_256_BYTES = 0x1, 4469 MLX5_DCTC_MTU_512_BYTES = 0x2, 4470 MLX5_DCTC_MTU_1K_BYTES = 0x3, 4471 MLX5_DCTC_MTU_2K_BYTES = 0x4, 4472 MLX5_DCTC_MTU_4K_BYTES = 0x5, 4473 }; 4474 4475 struct mlx5_ifc_dctc_bits { 4476 u8 reserved_at_0[0x4]; 4477 u8 state[0x4]; 4478 u8 reserved_at_8[0x18]; 4479 4480 u8 reserved_at_20[0x8]; 4481 u8 user_index[0x18]; 4482 4483 u8 reserved_at_40[0x8]; 4484 u8 cqn[0x18]; 4485 4486 u8 counter_set_id[0x8]; 4487 u8 atomic_mode[0x4]; 4488 u8 rre[0x1]; 4489 u8 rwe[0x1]; 4490 u8 rae[0x1]; 4491 u8 atomic_like_write_en[0x1]; 4492 u8 latency_sensitive[0x1]; 4493 u8 rlky[0x1]; 4494 u8 free_ar[0x1]; 4495 u8 reserved_at_73[0xd]; 4496 4497 u8 reserved_at_80[0x8]; 4498 u8 cs_res[0x8]; 4499 u8 reserved_at_90[0x3]; 4500 u8 min_rnr_nak[0x5]; 4501 u8 reserved_at_98[0x8]; 4502 4503 u8 reserved_at_a0[0x8]; 4504 u8 srqn_xrqn[0x18]; 4505 4506 u8 reserved_at_c0[0x8]; 4507 u8 pd[0x18]; 4508 4509 u8 tclass[0x8]; 4510 u8 reserved_at_e8[0x4]; 4511 u8 flow_label[0x14]; 4512 4513 u8 dc_access_key[0x40]; 4514 4515 u8 reserved_at_140[0x5]; 4516 u8 mtu[0x3]; 4517 u8 port[0x8]; 4518 u8 pkey_index[0x10]; 4519 4520 u8 reserved_at_160[0x8]; 4521 u8 my_addr_index[0x8]; 4522 u8 reserved_at_170[0x8]; 4523 u8 hop_limit[0x8]; 4524 4525 u8 dc_access_key_violation_count[0x20]; 4526 4527 u8 reserved_at_1a0[0x14]; 4528 u8 dei_cfi[0x1]; 4529 u8 eth_prio[0x3]; 4530 u8 ecn[0x2]; 4531 u8 dscp[0x6]; 4532 4533 u8 reserved_at_1c0[0x20]; 4534 u8 ece[0x20]; 4535 }; 4536 4537 enum { 4538 MLX5_CQC_STATUS_OK = 0x0, 4539 MLX5_CQC_STATUS_CQ_OVERFLOW = 0x9, 4540 MLX5_CQC_STATUS_CQ_WRITE_FAIL = 0xa, 4541 }; 4542 4543 enum { 4544 MLX5_CQC_CQE_SZ_64_BYTES = 0x0, 4545 MLX5_CQC_CQE_SZ_128_BYTES = 0x1, 4546 }; 4547 4548 enum { 4549 MLX5_CQC_ST_SOLICITED_NOTIFICATION_REQUEST_ARMED = 0x6, 4550 MLX5_CQC_ST_NOTIFICATION_REQUEST_ARMED = 0x9, 4551 MLX5_CQC_ST_FIRED = 0xa, 4552 }; 4553 4554 enum mlx5_cq_period_mode { 4555 MLX5_CQ_PERIOD_MODE_START_FROM_EQE = 0x0, 4556 MLX5_CQ_PERIOD_MODE_START_FROM_CQE = 0x1, 4557 MLX5_CQ_PERIOD_NUM_MODES, 4558 }; 4559 4560 struct mlx5_ifc_cqc_bits { 4561 u8 status[0x4]; 4562 u8 reserved_at_4[0x2]; 4563 u8 dbr_umem_valid[0x1]; 4564 u8 apu_cq[0x1]; 4565 u8 cqe_sz[0x3]; 4566 u8 cc[0x1]; 4567 u8 reserved_at_c[0x1]; 4568 u8 scqe_break_moderation_en[0x1]; 4569 u8 oi[0x1]; 4570 u8 cq_period_mode[0x2]; 4571 u8 cqe_comp_en[0x1]; 4572 u8 mini_cqe_res_format[0x2]; 4573 u8 st[0x4]; 4574 u8 reserved_at_18[0x6]; 4575 u8 cqe_compression_layout[0x2]; 4576 4577 u8 reserved_at_20[0x20]; 4578 4579 u8 reserved_at_40[0x14]; 4580 u8 page_offset[0x6]; 4581 u8 reserved_at_5a[0x6]; 4582 4583 u8 reserved_at_60[0x3]; 4584 u8 log_cq_size[0x5]; 4585 u8 uar_page[0x18]; 4586 4587 u8 reserved_at_80[0x4]; 4588 u8 cq_period[0xc]; 4589 u8 cq_max_count[0x10]; 4590 4591 u8 c_eqn_or_apu_element[0x20]; 4592 4593 u8 reserved_at_c0[0x3]; 4594 u8 log_page_size[0x5]; 4595 u8 reserved_at_c8[0x18]; 4596 4597 u8 reserved_at_e0[0x20]; 4598 4599 u8 reserved_at_100[0x8]; 4600 u8 last_notified_index[0x18]; 4601 4602 u8 reserved_at_120[0x8]; 4603 u8 last_solicit_index[0x18]; 4604 4605 u8 reserved_at_140[0x8]; 4606 u8 consumer_counter[0x18]; 4607 4608 u8 reserved_at_160[0x8]; 4609 u8 producer_counter[0x18]; 4610 4611 u8 reserved_at_180[0x40]; 4612 4613 u8 dbr_addr[0x40]; 4614 }; 4615 4616 union mlx5_ifc_cong_control_roce_ecn_auto_bits { 4617 struct mlx5_ifc_cong_control_802_1qau_rp_bits cong_control_802_1qau_rp; 4618 struct mlx5_ifc_cong_control_r_roce_ecn_rp_bits cong_control_r_roce_ecn_rp; 4619 struct mlx5_ifc_cong_control_r_roce_ecn_np_bits cong_control_r_roce_ecn_np; 4620 struct mlx5_ifc_cong_control_r_roce_general_bits cong_control_r_roce_general; 4621 u8 reserved_at_0[0x800]; 4622 }; 4623 4624 struct mlx5_ifc_query_adapter_param_block_bits { 4625 u8 reserved_at_0[0xc0]; 4626 4627 u8 reserved_at_c0[0x8]; 4628 u8 ieee_vendor_id[0x18]; 4629 4630 u8 reserved_at_e0[0x10]; 4631 u8 vsd_vendor_id[0x10]; 4632 4633 u8 vsd[208][0x8]; 4634 4635 u8 vsd_contd_psid[16][0x8]; 4636 }; 4637 4638 enum { 4639 MLX5_XRQC_STATE_GOOD = 0x0, 4640 MLX5_XRQC_STATE_ERROR = 0x1, 4641 }; 4642 4643 enum { 4644 MLX5_XRQC_TOPOLOGY_NO_SPECIAL_TOPOLOGY = 0x0, 4645 MLX5_XRQC_TOPOLOGY_TAG_MATCHING = 0x1, 4646 }; 4647 4648 enum { 4649 MLX5_XRQC_OFFLOAD_RNDV = 0x1, 4650 }; 4651 4652 struct mlx5_ifc_tag_matching_topology_context_bits { 4653 u8 log_matching_list_sz[0x4]; 4654 u8 reserved_at_4[0xc]; 4655 u8 append_next_index[0x10]; 4656 4657 u8 sw_phase_cnt[0x10]; 4658 u8 hw_phase_cnt[0x10]; 4659 4660 u8 reserved_at_40[0x40]; 4661 }; 4662 4663 struct mlx5_ifc_xrqc_bits { 4664 u8 state[0x4]; 4665 u8 rlkey[0x1]; 4666 u8 reserved_at_5[0xf]; 4667 u8 topology[0x4]; 4668 u8 reserved_at_18[0x4]; 4669 u8 offload[0x4]; 4670 4671 u8 reserved_at_20[0x8]; 4672 u8 user_index[0x18]; 4673 4674 u8 reserved_at_40[0x8]; 4675 u8 cqn[0x18]; 4676 4677 u8 reserved_at_60[0xa0]; 4678 4679 struct mlx5_ifc_tag_matching_topology_context_bits tag_matching_topology_context; 4680 4681 u8 reserved_at_180[0x280]; 4682 4683 struct mlx5_ifc_wq_bits wq; 4684 }; 4685 4686 union mlx5_ifc_modify_field_select_resize_field_select_auto_bits { 4687 struct mlx5_ifc_modify_field_select_bits modify_field_select; 4688 struct mlx5_ifc_resize_field_select_bits resize_field_select; 4689 u8 reserved_at_0[0x20]; 4690 }; 4691 4692 union mlx5_ifc_field_select_802_1_r_roce_auto_bits { 4693 struct mlx5_ifc_field_select_802_1qau_rp_bits field_select_802_1qau_rp; 4694 struct mlx5_ifc_field_select_r_roce_rp_bits field_select_r_roce_rp; 4695 struct mlx5_ifc_field_select_r_roce_np_bits field_select_r_roce_np; 4696 u8 reserved_at_0[0x20]; 4697 }; 4698 4699 union mlx5_ifc_eth_cntrs_grp_data_layout_auto_bits { 4700 struct mlx5_ifc_eth_802_3_cntrs_grp_data_layout_bits eth_802_3_cntrs_grp_data_layout; 4701 struct mlx5_ifc_eth_2863_cntrs_grp_data_layout_bits eth_2863_cntrs_grp_data_layout; 4702 struct mlx5_ifc_eth_2819_cntrs_grp_data_layout_bits eth_2819_cntrs_grp_data_layout; 4703 struct mlx5_ifc_eth_3635_cntrs_grp_data_layout_bits eth_3635_cntrs_grp_data_layout; 4704 struct mlx5_ifc_eth_extended_cntrs_grp_data_layout_bits eth_extended_cntrs_grp_data_layout; 4705 struct mlx5_ifc_eth_per_prio_grp_data_layout_bits eth_per_prio_grp_data_layout; 4706 struct mlx5_ifc_eth_per_tc_prio_grp_data_layout_bits eth_per_tc_prio_grp_data_layout; 4707 struct mlx5_ifc_eth_per_tc_congest_prio_grp_data_layout_bits eth_per_tc_congest_prio_grp_data_layout; 4708 struct mlx5_ifc_ib_port_cntrs_grp_data_layout_bits ib_port_cntrs_grp_data_layout; 4709 struct mlx5_ifc_ib_ext_port_cntrs_grp_data_layout_bits ib_ext_port_cntrs_grp_data_layout; 4710 struct mlx5_ifc_phys_layer_cntrs_bits phys_layer_cntrs; 4711 struct mlx5_ifc_phys_layer_statistical_cntrs_bits phys_layer_statistical_cntrs; 4712 u8 reserved_at_0[0x7c0]; 4713 }; 4714 4715 union mlx5_ifc_pcie_cntrs_grp_data_layout_auto_bits { 4716 struct mlx5_ifc_pcie_perf_cntrs_grp_data_layout_bits pcie_perf_cntrs_grp_data_layout; 4717 u8 reserved_at_0[0x7c0]; 4718 }; 4719 4720 union mlx5_ifc_event_auto_bits { 4721 struct mlx5_ifc_comp_event_bits comp_event; 4722 struct mlx5_ifc_dct_events_bits dct_events; 4723 struct mlx5_ifc_qp_events_bits qp_events; 4724 struct mlx5_ifc_wqe_associated_page_fault_event_bits wqe_associated_page_fault_event; 4725 struct mlx5_ifc_rdma_page_fault_event_bits rdma_page_fault_event; 4726 struct mlx5_ifc_cq_error_bits cq_error; 4727 struct mlx5_ifc_dropped_packet_logged_bits dropped_packet_logged; 4728 struct mlx5_ifc_port_state_change_event_bits port_state_change_event; 4729 struct mlx5_ifc_gpio_event_bits gpio_event; 4730 struct mlx5_ifc_db_bf_congestion_event_bits db_bf_congestion_event; 4731 struct mlx5_ifc_stall_vl_event_bits stall_vl_event; 4732 struct mlx5_ifc_cmd_inter_comp_event_bits cmd_inter_comp_event; 4733 u8 reserved_at_0[0xe0]; 4734 }; 4735 4736 struct mlx5_ifc_health_buffer_bits { 4737 u8 reserved_at_0[0x100]; 4738 4739 u8 assert_existptr[0x20]; 4740 4741 u8 assert_callra[0x20]; 4742 4743 u8 reserved_at_140[0x20]; 4744 4745 u8 time[0x20]; 4746 4747 u8 fw_version[0x20]; 4748 4749 u8 hw_id[0x20]; 4750 4751 u8 rfr[0x1]; 4752 u8 reserved_at_1c1[0x3]; 4753 u8 valid[0x1]; 4754 u8 severity[0x3]; 4755 u8 reserved_at_1c8[0x18]; 4756 4757 u8 irisc_index[0x8]; 4758 u8 synd[0x8]; 4759 u8 ext_synd[0x10]; 4760 }; 4761 4762 struct mlx5_ifc_register_loopback_control_bits { 4763 u8 no_lb[0x1]; 4764 u8 reserved_at_1[0x7]; 4765 u8 port[0x8]; 4766 u8 reserved_at_10[0x10]; 4767 4768 u8 reserved_at_20[0x60]; 4769 }; 4770 4771 struct mlx5_ifc_vport_tc_element_bits { 4772 u8 traffic_class[0x4]; 4773 u8 reserved_at_4[0xc]; 4774 u8 vport_number[0x10]; 4775 }; 4776 4777 struct mlx5_ifc_vport_element_bits { 4778 u8 reserved_at_0[0x10]; 4779 u8 vport_number[0x10]; 4780 }; 4781 4782 enum { 4783 TSAR_ELEMENT_TSAR_TYPE_DWRR = 0x0, 4784 TSAR_ELEMENT_TSAR_TYPE_ROUND_ROBIN = 0x1, 4785 TSAR_ELEMENT_TSAR_TYPE_ETS = 0x2, 4786 }; 4787 4788 struct mlx5_ifc_tsar_element_bits { 4789 u8 reserved_at_0[0x8]; 4790 u8 tsar_type[0x8]; 4791 u8 reserved_at_10[0x10]; 4792 }; 4793 4794 enum { 4795 MLX5_TEARDOWN_HCA_OUT_FORCE_STATE_SUCCESS = 0x0, 4796 MLX5_TEARDOWN_HCA_OUT_FORCE_STATE_FAIL = 0x1, 4797 }; 4798 4799 struct mlx5_ifc_teardown_hca_out_bits { 4800 u8 status[0x8]; 4801 u8 reserved_at_8[0x18]; 4802 4803 u8 syndrome[0x20]; 4804 4805 u8 reserved_at_40[0x3f]; 4806 4807 u8 state[0x1]; 4808 }; 4809 4810 enum { 4811 MLX5_TEARDOWN_HCA_IN_PROFILE_GRACEFUL_CLOSE = 0x0, 4812 MLX5_TEARDOWN_HCA_IN_PROFILE_FORCE_CLOSE = 0x1, 4813 MLX5_TEARDOWN_HCA_IN_PROFILE_PREPARE_FAST_TEARDOWN = 0x2, 4814 }; 4815 4816 struct mlx5_ifc_teardown_hca_in_bits { 4817 u8 opcode[0x10]; 4818 u8 reserved_at_10[0x10]; 4819 4820 u8 reserved_at_20[0x10]; 4821 u8 op_mod[0x10]; 4822 4823 u8 reserved_at_40[0x10]; 4824 u8 profile[0x10]; 4825 4826 u8 reserved_at_60[0x20]; 4827 }; 4828 4829 struct mlx5_ifc_sqerr2rts_qp_out_bits { 4830 u8 status[0x8]; 4831 u8 reserved_at_8[0x18]; 4832 4833 u8 syndrome[0x20]; 4834 4835 u8 reserved_at_40[0x40]; 4836 }; 4837 4838 struct mlx5_ifc_sqerr2rts_qp_in_bits { 4839 u8 opcode[0x10]; 4840 u8 uid[0x10]; 4841 4842 u8 reserved_at_20[0x10]; 4843 u8 op_mod[0x10]; 4844 4845 u8 reserved_at_40[0x8]; 4846 u8 qpn[0x18]; 4847 4848 u8 reserved_at_60[0x20]; 4849 4850 u8 opt_param_mask[0x20]; 4851 4852 u8 reserved_at_a0[0x20]; 4853 4854 struct mlx5_ifc_qpc_bits qpc; 4855 4856 u8 reserved_at_800[0x80]; 4857 }; 4858 4859 struct mlx5_ifc_sqd2rts_qp_out_bits { 4860 u8 status[0x8]; 4861 u8 reserved_at_8[0x18]; 4862 4863 u8 syndrome[0x20]; 4864 4865 u8 reserved_at_40[0x40]; 4866 }; 4867 4868 struct mlx5_ifc_sqd2rts_qp_in_bits { 4869 u8 opcode[0x10]; 4870 u8 uid[0x10]; 4871 4872 u8 reserved_at_20[0x10]; 4873 u8 op_mod[0x10]; 4874 4875 u8 reserved_at_40[0x8]; 4876 u8 qpn[0x18]; 4877 4878 u8 reserved_at_60[0x20]; 4879 4880 u8 opt_param_mask[0x20]; 4881 4882 u8 reserved_at_a0[0x20]; 4883 4884 struct mlx5_ifc_qpc_bits qpc; 4885 4886 u8 reserved_at_800[0x80]; 4887 }; 4888 4889 struct mlx5_ifc_set_roce_address_out_bits { 4890 u8 status[0x8]; 4891 u8 reserved_at_8[0x18]; 4892 4893 u8 syndrome[0x20]; 4894 4895 u8 reserved_at_40[0x40]; 4896 }; 4897 4898 struct mlx5_ifc_set_roce_address_in_bits { 4899 u8 opcode[0x10]; 4900 u8 reserved_at_10[0x10]; 4901 4902 u8 reserved_at_20[0x10]; 4903 u8 op_mod[0x10]; 4904 4905 u8 roce_address_index[0x10]; 4906 u8 reserved_at_50[0xc]; 4907 u8 vhca_port_num[0x4]; 4908 4909 u8 reserved_at_60[0x20]; 4910 4911 struct mlx5_ifc_roce_addr_layout_bits roce_address; 4912 }; 4913 4914 struct mlx5_ifc_set_mad_demux_out_bits { 4915 u8 status[0x8]; 4916 u8 reserved_at_8[0x18]; 4917 4918 u8 syndrome[0x20]; 4919 4920 u8 reserved_at_40[0x40]; 4921 }; 4922 4923 enum { 4924 MLX5_SET_MAD_DEMUX_IN_DEMUX_MODE_PASS_ALL = 0x0, 4925 MLX5_SET_MAD_DEMUX_IN_DEMUX_MODE_SELECTIVE = 0x2, 4926 }; 4927 4928 struct mlx5_ifc_set_mad_demux_in_bits { 4929 u8 opcode[0x10]; 4930 u8 reserved_at_10[0x10]; 4931 4932 u8 reserved_at_20[0x10]; 4933 u8 op_mod[0x10]; 4934 4935 u8 reserved_at_40[0x20]; 4936 4937 u8 reserved_at_60[0x6]; 4938 u8 demux_mode[0x2]; 4939 u8 reserved_at_68[0x18]; 4940 }; 4941 4942 struct mlx5_ifc_set_l2_table_entry_out_bits { 4943 u8 status[0x8]; 4944 u8 reserved_at_8[0x18]; 4945 4946 u8 syndrome[0x20]; 4947 4948 u8 reserved_at_40[0x40]; 4949 }; 4950 4951 struct mlx5_ifc_set_l2_table_entry_in_bits { 4952 u8 opcode[0x10]; 4953 u8 reserved_at_10[0x10]; 4954 4955 u8 reserved_at_20[0x10]; 4956 u8 op_mod[0x10]; 4957 4958 u8 reserved_at_40[0x60]; 4959 4960 u8 reserved_at_a0[0x8]; 4961 u8 table_index[0x18]; 4962 4963 u8 reserved_at_c0[0x20]; 4964 4965 u8 reserved_at_e0[0x10]; 4966 u8 silent_mode_valid[0x1]; 4967 u8 silent_mode[0x1]; 4968 u8 reserved_at_f2[0x1]; 4969 u8 vlan_valid[0x1]; 4970 u8 vlan[0xc]; 4971 4972 struct mlx5_ifc_mac_address_layout_bits mac_address; 4973 4974 u8 reserved_at_140[0xc0]; 4975 }; 4976 4977 struct mlx5_ifc_set_issi_out_bits { 4978 u8 status[0x8]; 4979 u8 reserved_at_8[0x18]; 4980 4981 u8 syndrome[0x20]; 4982 4983 u8 reserved_at_40[0x40]; 4984 }; 4985 4986 struct mlx5_ifc_set_issi_in_bits { 4987 u8 opcode[0x10]; 4988 u8 reserved_at_10[0x10]; 4989 4990 u8 reserved_at_20[0x10]; 4991 u8 op_mod[0x10]; 4992 4993 u8 reserved_at_40[0x10]; 4994 u8 current_issi[0x10]; 4995 4996 u8 reserved_at_60[0x20]; 4997 }; 4998 4999 struct mlx5_ifc_set_hca_cap_out_bits { 5000 u8 status[0x8]; 5001 u8 reserved_at_8[0x18]; 5002 5003 u8 syndrome[0x20]; 5004 5005 u8 reserved_at_40[0x40]; 5006 }; 5007 5008 struct mlx5_ifc_set_hca_cap_in_bits { 5009 u8 opcode[0x10]; 5010 u8 reserved_at_10[0x10]; 5011 5012 u8 reserved_at_20[0x10]; 5013 u8 op_mod[0x10]; 5014 5015 u8 other_function[0x1]; 5016 u8 ec_vf_function[0x1]; 5017 u8 reserved_at_42[0xe]; 5018 u8 function_id[0x10]; 5019 5020 u8 reserved_at_60[0x20]; 5021 5022 union mlx5_ifc_hca_cap_union_bits capability; 5023 }; 5024 5025 enum { 5026 MLX5_SET_FTE_MODIFY_ENABLE_MASK_ACTION = 0x0, 5027 MLX5_SET_FTE_MODIFY_ENABLE_MASK_FLOW_TAG = 0x1, 5028 MLX5_SET_FTE_MODIFY_ENABLE_MASK_DESTINATION_LIST = 0x2, 5029 MLX5_SET_FTE_MODIFY_ENABLE_MASK_FLOW_COUNTERS = 0x3, 5030 MLX5_SET_FTE_MODIFY_ENABLE_MASK_IPSEC_OBJ_ID = 0x4 5031 }; 5032 5033 struct mlx5_ifc_set_fte_out_bits { 5034 u8 status[0x8]; 5035 u8 reserved_at_8[0x18]; 5036 5037 u8 syndrome[0x20]; 5038 5039 u8 reserved_at_40[0x40]; 5040 }; 5041 5042 struct mlx5_ifc_set_fte_in_bits { 5043 u8 opcode[0x10]; 5044 u8 reserved_at_10[0x10]; 5045 5046 u8 reserved_at_20[0x10]; 5047 u8 op_mod[0x10]; 5048 5049 u8 other_vport[0x1]; 5050 u8 reserved_at_41[0xf]; 5051 u8 vport_number[0x10]; 5052 5053 u8 reserved_at_60[0x20]; 5054 5055 u8 table_type[0x8]; 5056 u8 reserved_at_88[0x18]; 5057 5058 u8 reserved_at_a0[0x8]; 5059 u8 table_id[0x18]; 5060 5061 u8 ignore_flow_level[0x1]; 5062 u8 reserved_at_c1[0x17]; 5063 u8 modify_enable_mask[0x8]; 5064 5065 u8 reserved_at_e0[0x20]; 5066 5067 u8 flow_index[0x20]; 5068 5069 u8 reserved_at_120[0xe0]; 5070 5071 struct mlx5_ifc_flow_context_bits flow_context; 5072 }; 5073 5074 struct mlx5_ifc_dest_format_bits { 5075 u8 destination_type[0x8]; 5076 u8 destination_id[0x18]; 5077 5078 u8 destination_eswitch_owner_vhca_id_valid[0x1]; 5079 u8 packet_reformat[0x1]; 5080 u8 reserved_at_22[0xe]; 5081 u8 destination_eswitch_owner_vhca_id[0x10]; 5082 }; 5083 5084 struct mlx5_ifc_rts2rts_qp_out_bits { 5085 u8 status[0x8]; 5086 u8 reserved_at_8[0x18]; 5087 5088 u8 syndrome[0x20]; 5089 5090 u8 reserved_at_40[0x20]; 5091 u8 ece[0x20]; 5092 }; 5093 5094 struct mlx5_ifc_rts2rts_qp_in_bits { 5095 u8 opcode[0x10]; 5096 u8 uid[0x10]; 5097 5098 u8 reserved_at_20[0x10]; 5099 u8 op_mod[0x10]; 5100 5101 u8 reserved_at_40[0x8]; 5102 u8 qpn[0x18]; 5103 5104 u8 reserved_at_60[0x20]; 5105 5106 u8 opt_param_mask[0x20]; 5107 5108 u8 ece[0x20]; 5109 5110 struct mlx5_ifc_qpc_bits qpc; 5111 5112 u8 reserved_at_800[0x80]; 5113 }; 5114 5115 struct mlx5_ifc_rtr2rts_qp_out_bits { 5116 u8 status[0x8]; 5117 u8 reserved_at_8[0x18]; 5118 5119 u8 syndrome[0x20]; 5120 5121 u8 reserved_at_40[0x20]; 5122 u8 ece[0x20]; 5123 }; 5124 5125 struct mlx5_ifc_rtr2rts_qp_in_bits { 5126 u8 opcode[0x10]; 5127 u8 uid[0x10]; 5128 5129 u8 reserved_at_20[0x10]; 5130 u8 op_mod[0x10]; 5131 5132 u8 reserved_at_40[0x8]; 5133 u8 qpn[0x18]; 5134 5135 u8 reserved_at_60[0x20]; 5136 5137 u8 opt_param_mask[0x20]; 5138 5139 u8 ece[0x20]; 5140 5141 struct mlx5_ifc_qpc_bits qpc; 5142 5143 u8 reserved_at_800[0x80]; 5144 }; 5145 5146 struct mlx5_ifc_rst2init_qp_out_bits { 5147 u8 status[0x8]; 5148 u8 reserved_at_8[0x18]; 5149 5150 u8 syndrome[0x20]; 5151 5152 u8 reserved_at_40[0x20]; 5153 u8 ece[0x20]; 5154 }; 5155 5156 struct mlx5_ifc_rst2init_qp_in_bits { 5157 u8 opcode[0x10]; 5158 u8 uid[0x10]; 5159 5160 u8 reserved_at_20[0x10]; 5161 u8 op_mod[0x10]; 5162 5163 u8 reserved_at_40[0x8]; 5164 u8 qpn[0x18]; 5165 5166 u8 reserved_at_60[0x20]; 5167 5168 u8 opt_param_mask[0x20]; 5169 5170 u8 ece[0x20]; 5171 5172 struct mlx5_ifc_qpc_bits qpc; 5173 5174 u8 reserved_at_800[0x80]; 5175 }; 5176 5177 struct mlx5_ifc_query_xrq_out_bits { 5178 u8 status[0x8]; 5179 u8 reserved_at_8[0x18]; 5180 5181 u8 syndrome[0x20]; 5182 5183 u8 reserved_at_40[0x40]; 5184 5185 struct mlx5_ifc_xrqc_bits xrq_context; 5186 }; 5187 5188 struct mlx5_ifc_query_xrq_in_bits { 5189 u8 opcode[0x10]; 5190 u8 reserved_at_10[0x10]; 5191 5192 u8 reserved_at_20[0x10]; 5193 u8 op_mod[0x10]; 5194 5195 u8 reserved_at_40[0x8]; 5196 u8 xrqn[0x18]; 5197 5198 u8 reserved_at_60[0x20]; 5199 }; 5200 5201 struct mlx5_ifc_query_xrc_srq_out_bits { 5202 u8 status[0x8]; 5203 u8 reserved_at_8[0x18]; 5204 5205 u8 syndrome[0x20]; 5206 5207 u8 reserved_at_40[0x40]; 5208 5209 struct mlx5_ifc_xrc_srqc_bits xrc_srq_context_entry; 5210 5211 u8 reserved_at_280[0x600]; 5212 5213 u8 pas[][0x40]; 5214 }; 5215 5216 struct mlx5_ifc_query_xrc_srq_in_bits { 5217 u8 opcode[0x10]; 5218 u8 reserved_at_10[0x10]; 5219 5220 u8 reserved_at_20[0x10]; 5221 u8 op_mod[0x10]; 5222 5223 u8 reserved_at_40[0x8]; 5224 u8 xrc_srqn[0x18]; 5225 5226 u8 reserved_at_60[0x20]; 5227 }; 5228 5229 enum { 5230 MLX5_QUERY_VPORT_STATE_OUT_STATE_DOWN = 0x0, 5231 MLX5_QUERY_VPORT_STATE_OUT_STATE_UP = 0x1, 5232 }; 5233 5234 struct mlx5_ifc_query_vport_state_out_bits { 5235 u8 status[0x8]; 5236 u8 reserved_at_8[0x18]; 5237 5238 u8 syndrome[0x20]; 5239 5240 u8 reserved_at_40[0x20]; 5241 5242 u8 reserved_at_60[0x18]; 5243 u8 admin_state[0x4]; 5244 u8 state[0x4]; 5245 }; 5246 5247 enum { 5248 MLX5_VPORT_STATE_OP_MOD_VNIC_VPORT = 0x0, 5249 MLX5_VPORT_STATE_OP_MOD_ESW_VPORT = 0x1, 5250 MLX5_VPORT_STATE_OP_MOD_UPLINK = 0x2, 5251 }; 5252 5253 struct mlx5_ifc_arm_monitor_counter_in_bits { 5254 u8 opcode[0x10]; 5255 u8 uid[0x10]; 5256 5257 u8 reserved_at_20[0x10]; 5258 u8 op_mod[0x10]; 5259 5260 u8 reserved_at_40[0x20]; 5261 5262 u8 reserved_at_60[0x20]; 5263 }; 5264 5265 struct mlx5_ifc_arm_monitor_counter_out_bits { 5266 u8 status[0x8]; 5267 u8 reserved_at_8[0x18]; 5268 5269 u8 syndrome[0x20]; 5270 5271 u8 reserved_at_40[0x40]; 5272 }; 5273 5274 enum { 5275 MLX5_QUERY_MONITOR_CNT_TYPE_PPCNT = 0x0, 5276 MLX5_QUERY_MONITOR_CNT_TYPE_Q_COUNTER = 0x1, 5277 }; 5278 5279 enum mlx5_monitor_counter_ppcnt { 5280 MLX5_QUERY_MONITOR_PPCNT_IN_RANGE_LENGTH_ERRORS = 0x0, 5281 MLX5_QUERY_MONITOR_PPCNT_OUT_OF_RANGE_LENGTH_FIELD = 0x1, 5282 MLX5_QUERY_MONITOR_PPCNT_FRAME_TOO_LONG_ERRORS = 0x2, 5283 MLX5_QUERY_MONITOR_PPCNT_FRAME_CHECK_SEQUENCE_ERRORS = 0x3, 5284 MLX5_QUERY_MONITOR_PPCNT_ALIGNMENT_ERRORS = 0x4, 5285 MLX5_QUERY_MONITOR_PPCNT_IF_OUT_DISCARDS = 0x5, 5286 }; 5287 5288 enum { 5289 MLX5_QUERY_MONITOR_Q_COUNTER_RX_OUT_OF_BUFFER = 0x4, 5290 }; 5291 5292 struct mlx5_ifc_monitor_counter_output_bits { 5293 u8 reserved_at_0[0x4]; 5294 u8 type[0x4]; 5295 u8 reserved_at_8[0x8]; 5296 u8 counter[0x10]; 5297 5298 u8 counter_group_id[0x20]; 5299 }; 5300 5301 #define MLX5_CMD_SET_MONITOR_NUM_PPCNT_COUNTER_SET1 (6) 5302 #define MLX5_CMD_SET_MONITOR_NUM_Q_COUNTERS_SET1 (1) 5303 #define MLX5_CMD_SET_MONITOR_NUM_COUNTER (MLX5_CMD_SET_MONITOR_NUM_PPCNT_COUNTER_SET1 +\ 5304 MLX5_CMD_SET_MONITOR_NUM_Q_COUNTERS_SET1) 5305 5306 struct mlx5_ifc_set_monitor_counter_in_bits { 5307 u8 opcode[0x10]; 5308 u8 uid[0x10]; 5309 5310 u8 reserved_at_20[0x10]; 5311 u8 op_mod[0x10]; 5312 5313 u8 reserved_at_40[0x10]; 5314 u8 num_of_counters[0x10]; 5315 5316 u8 reserved_at_60[0x20]; 5317 5318 struct mlx5_ifc_monitor_counter_output_bits monitor_counter[MLX5_CMD_SET_MONITOR_NUM_COUNTER]; 5319 }; 5320 5321 struct mlx5_ifc_set_monitor_counter_out_bits { 5322 u8 status[0x8]; 5323 u8 reserved_at_8[0x18]; 5324 5325 u8 syndrome[0x20]; 5326 5327 u8 reserved_at_40[0x40]; 5328 }; 5329 5330 struct mlx5_ifc_query_vport_state_in_bits { 5331 u8 opcode[0x10]; 5332 u8 reserved_at_10[0x10]; 5333 5334 u8 reserved_at_20[0x10]; 5335 u8 op_mod[0x10]; 5336 5337 u8 other_vport[0x1]; 5338 u8 reserved_at_41[0xf]; 5339 u8 vport_number[0x10]; 5340 5341 u8 reserved_at_60[0x20]; 5342 }; 5343 5344 struct mlx5_ifc_query_vnic_env_out_bits { 5345 u8 status[0x8]; 5346 u8 reserved_at_8[0x18]; 5347 5348 u8 syndrome[0x20]; 5349 5350 u8 reserved_at_40[0x40]; 5351 5352 struct mlx5_ifc_vnic_diagnostic_statistics_bits vport_env; 5353 }; 5354 5355 enum { 5356 MLX5_QUERY_VNIC_ENV_IN_OP_MOD_VPORT_DIAG_STATISTICS = 0x0, 5357 }; 5358 5359 struct mlx5_ifc_query_vnic_env_in_bits { 5360 u8 opcode[0x10]; 5361 u8 reserved_at_10[0x10]; 5362 5363 u8 reserved_at_20[0x10]; 5364 u8 op_mod[0x10]; 5365 5366 u8 other_vport[0x1]; 5367 u8 reserved_at_41[0xf]; 5368 u8 vport_number[0x10]; 5369 5370 u8 reserved_at_60[0x20]; 5371 }; 5372 5373 struct mlx5_ifc_query_vport_counter_out_bits { 5374 u8 status[0x8]; 5375 u8 reserved_at_8[0x18]; 5376 5377 u8 syndrome[0x20]; 5378 5379 u8 reserved_at_40[0x40]; 5380 5381 struct mlx5_ifc_traffic_counter_bits received_errors; 5382 5383 struct mlx5_ifc_traffic_counter_bits transmit_errors; 5384 5385 struct mlx5_ifc_traffic_counter_bits received_ib_unicast; 5386 5387 struct mlx5_ifc_traffic_counter_bits transmitted_ib_unicast; 5388 5389 struct mlx5_ifc_traffic_counter_bits received_ib_multicast; 5390 5391 struct mlx5_ifc_traffic_counter_bits transmitted_ib_multicast; 5392 5393 struct mlx5_ifc_traffic_counter_bits received_eth_broadcast; 5394 5395 struct mlx5_ifc_traffic_counter_bits transmitted_eth_broadcast; 5396 5397 struct mlx5_ifc_traffic_counter_bits received_eth_unicast; 5398 5399 struct mlx5_ifc_traffic_counter_bits transmitted_eth_unicast; 5400 5401 struct mlx5_ifc_traffic_counter_bits received_eth_multicast; 5402 5403 struct mlx5_ifc_traffic_counter_bits transmitted_eth_multicast; 5404 5405 struct mlx5_ifc_traffic_counter_bits local_loopback; 5406 5407 u8 reserved_at_700[0x980]; 5408 }; 5409 5410 enum { 5411 MLX5_QUERY_VPORT_COUNTER_IN_OP_MOD_VPORT_COUNTERS = 0x0, 5412 }; 5413 5414 struct mlx5_ifc_query_vport_counter_in_bits { 5415 u8 opcode[0x10]; 5416 u8 reserved_at_10[0x10]; 5417 5418 u8 reserved_at_20[0x10]; 5419 u8 op_mod[0x10]; 5420 5421 u8 other_vport[0x1]; 5422 u8 reserved_at_41[0xb]; 5423 u8 port_num[0x4]; 5424 u8 vport_number[0x10]; 5425 5426 u8 reserved_at_60[0x60]; 5427 5428 u8 clear[0x1]; 5429 u8 reserved_at_c1[0x1f]; 5430 5431 u8 reserved_at_e0[0x20]; 5432 }; 5433 5434 struct mlx5_ifc_query_tis_out_bits { 5435 u8 status[0x8]; 5436 u8 reserved_at_8[0x18]; 5437 5438 u8 syndrome[0x20]; 5439 5440 u8 reserved_at_40[0x40]; 5441 5442 struct mlx5_ifc_tisc_bits tis_context; 5443 }; 5444 5445 struct mlx5_ifc_query_tis_in_bits { 5446 u8 opcode[0x10]; 5447 u8 reserved_at_10[0x10]; 5448 5449 u8 reserved_at_20[0x10]; 5450 u8 op_mod[0x10]; 5451 5452 u8 reserved_at_40[0x8]; 5453 u8 tisn[0x18]; 5454 5455 u8 reserved_at_60[0x20]; 5456 }; 5457 5458 struct mlx5_ifc_query_tir_out_bits { 5459 u8 status[0x8]; 5460 u8 reserved_at_8[0x18]; 5461 5462 u8 syndrome[0x20]; 5463 5464 u8 reserved_at_40[0xc0]; 5465 5466 struct mlx5_ifc_tirc_bits tir_context; 5467 }; 5468 5469 struct mlx5_ifc_query_tir_in_bits { 5470 u8 opcode[0x10]; 5471 u8 reserved_at_10[0x10]; 5472 5473 u8 reserved_at_20[0x10]; 5474 u8 op_mod[0x10]; 5475 5476 u8 reserved_at_40[0x8]; 5477 u8 tirn[0x18]; 5478 5479 u8 reserved_at_60[0x20]; 5480 }; 5481 5482 struct mlx5_ifc_query_srq_out_bits { 5483 u8 status[0x8]; 5484 u8 reserved_at_8[0x18]; 5485 5486 u8 syndrome[0x20]; 5487 5488 u8 reserved_at_40[0x40]; 5489 5490 struct mlx5_ifc_srqc_bits srq_context_entry; 5491 5492 u8 reserved_at_280[0x600]; 5493 5494 u8 pas[][0x40]; 5495 }; 5496 5497 struct mlx5_ifc_query_srq_in_bits { 5498 u8 opcode[0x10]; 5499 u8 reserved_at_10[0x10]; 5500 5501 u8 reserved_at_20[0x10]; 5502 u8 op_mod[0x10]; 5503 5504 u8 reserved_at_40[0x8]; 5505 u8 srqn[0x18]; 5506 5507 u8 reserved_at_60[0x20]; 5508 }; 5509 5510 struct mlx5_ifc_query_sq_out_bits { 5511 u8 status[0x8]; 5512 u8 reserved_at_8[0x18]; 5513 5514 u8 syndrome[0x20]; 5515 5516 u8 reserved_at_40[0xc0]; 5517 5518 struct mlx5_ifc_sqc_bits sq_context; 5519 }; 5520 5521 struct mlx5_ifc_query_sq_in_bits { 5522 u8 opcode[0x10]; 5523 u8 reserved_at_10[0x10]; 5524 5525 u8 reserved_at_20[0x10]; 5526 u8 op_mod[0x10]; 5527 5528 u8 reserved_at_40[0x8]; 5529 u8 sqn[0x18]; 5530 5531 u8 reserved_at_60[0x20]; 5532 }; 5533 5534 struct mlx5_ifc_query_special_contexts_out_bits { 5535 u8 status[0x8]; 5536 u8 reserved_at_8[0x18]; 5537 5538 u8 syndrome[0x20]; 5539 5540 u8 dump_fill_mkey[0x20]; 5541 5542 u8 resd_lkey[0x20]; 5543 5544 u8 null_mkey[0x20]; 5545 5546 u8 terminate_scatter_list_mkey[0x20]; 5547 5548 u8 repeated_mkey[0x20]; 5549 5550 u8 reserved_at_a0[0x20]; 5551 }; 5552 5553 struct mlx5_ifc_query_special_contexts_in_bits { 5554 u8 opcode[0x10]; 5555 u8 reserved_at_10[0x10]; 5556 5557 u8 reserved_at_20[0x10]; 5558 u8 op_mod[0x10]; 5559 5560 u8 reserved_at_40[0x40]; 5561 }; 5562 5563 struct mlx5_ifc_query_scheduling_element_out_bits { 5564 u8 opcode[0x10]; 5565 u8 reserved_at_10[0x10]; 5566 5567 u8 reserved_at_20[0x10]; 5568 u8 op_mod[0x10]; 5569 5570 u8 reserved_at_40[0xc0]; 5571 5572 struct mlx5_ifc_scheduling_context_bits scheduling_context; 5573 5574 u8 reserved_at_300[0x100]; 5575 }; 5576 5577 enum { 5578 SCHEDULING_HIERARCHY_E_SWITCH = 0x2, 5579 SCHEDULING_HIERARCHY_NIC = 0x3, 5580 }; 5581 5582 struct mlx5_ifc_query_scheduling_element_in_bits { 5583 u8 opcode[0x10]; 5584 u8 reserved_at_10[0x10]; 5585 5586 u8 reserved_at_20[0x10]; 5587 u8 op_mod[0x10]; 5588 5589 u8 scheduling_hierarchy[0x8]; 5590 u8 reserved_at_48[0x18]; 5591 5592 u8 scheduling_element_id[0x20]; 5593 5594 u8 reserved_at_80[0x180]; 5595 }; 5596 5597 struct mlx5_ifc_query_rqt_out_bits { 5598 u8 status[0x8]; 5599 u8 reserved_at_8[0x18]; 5600 5601 u8 syndrome[0x20]; 5602 5603 u8 reserved_at_40[0xc0]; 5604 5605 struct mlx5_ifc_rqtc_bits rqt_context; 5606 }; 5607 5608 struct mlx5_ifc_query_rqt_in_bits { 5609 u8 opcode[0x10]; 5610 u8 reserved_at_10[0x10]; 5611 5612 u8 reserved_at_20[0x10]; 5613 u8 op_mod[0x10]; 5614 5615 u8 reserved_at_40[0x8]; 5616 u8 rqtn[0x18]; 5617 5618 u8 reserved_at_60[0x20]; 5619 }; 5620 5621 struct mlx5_ifc_query_rq_out_bits { 5622 u8 status[0x8]; 5623 u8 reserved_at_8[0x18]; 5624 5625 u8 syndrome[0x20]; 5626 5627 u8 reserved_at_40[0xc0]; 5628 5629 struct mlx5_ifc_rqc_bits rq_context; 5630 }; 5631 5632 struct mlx5_ifc_query_rq_in_bits { 5633 u8 opcode[0x10]; 5634 u8 reserved_at_10[0x10]; 5635 5636 u8 reserved_at_20[0x10]; 5637 u8 op_mod[0x10]; 5638 5639 u8 reserved_at_40[0x8]; 5640 u8 rqn[0x18]; 5641 5642 u8 reserved_at_60[0x20]; 5643 }; 5644 5645 struct mlx5_ifc_query_roce_address_out_bits { 5646 u8 status[0x8]; 5647 u8 reserved_at_8[0x18]; 5648 5649 u8 syndrome[0x20]; 5650 5651 u8 reserved_at_40[0x40]; 5652 5653 struct mlx5_ifc_roce_addr_layout_bits roce_address; 5654 }; 5655 5656 struct mlx5_ifc_query_roce_address_in_bits { 5657 u8 opcode[0x10]; 5658 u8 reserved_at_10[0x10]; 5659 5660 u8 reserved_at_20[0x10]; 5661 u8 op_mod[0x10]; 5662 5663 u8 roce_address_index[0x10]; 5664 u8 reserved_at_50[0xc]; 5665 u8 vhca_port_num[0x4]; 5666 5667 u8 reserved_at_60[0x20]; 5668 }; 5669 5670 struct mlx5_ifc_query_rmp_out_bits { 5671 u8 status[0x8]; 5672 u8 reserved_at_8[0x18]; 5673 5674 u8 syndrome[0x20]; 5675 5676 u8 reserved_at_40[0xc0]; 5677 5678 struct mlx5_ifc_rmpc_bits rmp_context; 5679 }; 5680 5681 struct mlx5_ifc_query_rmp_in_bits { 5682 u8 opcode[0x10]; 5683 u8 reserved_at_10[0x10]; 5684 5685 u8 reserved_at_20[0x10]; 5686 u8 op_mod[0x10]; 5687 5688 u8 reserved_at_40[0x8]; 5689 u8 rmpn[0x18]; 5690 5691 u8 reserved_at_60[0x20]; 5692 }; 5693 5694 struct mlx5_ifc_cqe_error_syndrome_bits { 5695 u8 hw_error_syndrome[0x8]; 5696 u8 hw_syndrome_type[0x4]; 5697 u8 reserved_at_c[0x4]; 5698 u8 vendor_error_syndrome[0x8]; 5699 u8 syndrome[0x8]; 5700 }; 5701 5702 struct mlx5_ifc_qp_context_extension_bits { 5703 u8 reserved_at_0[0x60]; 5704 5705 struct mlx5_ifc_cqe_error_syndrome_bits error_syndrome; 5706 5707 u8 reserved_at_80[0x580]; 5708 }; 5709 5710 struct mlx5_ifc_qpc_extension_and_pas_list_in_bits { 5711 struct mlx5_ifc_qp_context_extension_bits qpc_data_extension; 5712 5713 u8 pas[0][0x40]; 5714 }; 5715 5716 struct mlx5_ifc_qp_pas_list_in_bits { 5717 struct mlx5_ifc_cmd_pas_bits pas[0]; 5718 }; 5719 5720 union mlx5_ifc_qp_pas_or_qpc_ext_and_pas_bits { 5721 struct mlx5_ifc_qp_pas_list_in_bits qp_pas_list; 5722 struct mlx5_ifc_qpc_extension_and_pas_list_in_bits qpc_ext_and_pas_list; 5723 }; 5724 5725 struct mlx5_ifc_query_qp_out_bits { 5726 u8 status[0x8]; 5727 u8 reserved_at_8[0x18]; 5728 5729 u8 syndrome[0x20]; 5730 5731 u8 reserved_at_40[0x40]; 5732 5733 u8 opt_param_mask[0x20]; 5734 5735 u8 ece[0x20]; 5736 5737 struct mlx5_ifc_qpc_bits qpc; 5738 5739 u8 reserved_at_800[0x80]; 5740 5741 union mlx5_ifc_qp_pas_or_qpc_ext_and_pas_bits qp_pas_or_qpc_ext_and_pas; 5742 }; 5743 5744 struct mlx5_ifc_query_qp_in_bits { 5745 u8 opcode[0x10]; 5746 u8 reserved_at_10[0x10]; 5747 5748 u8 reserved_at_20[0x10]; 5749 u8 op_mod[0x10]; 5750 5751 u8 qpc_ext[0x1]; 5752 u8 reserved_at_41[0x7]; 5753 u8 qpn[0x18]; 5754 5755 u8 reserved_at_60[0x20]; 5756 }; 5757 5758 struct mlx5_ifc_query_q_counter_out_bits { 5759 u8 status[0x8]; 5760 u8 reserved_at_8[0x18]; 5761 5762 u8 syndrome[0x20]; 5763 5764 u8 reserved_at_40[0x40]; 5765 5766 u8 rx_write_requests[0x20]; 5767 5768 u8 reserved_at_a0[0x20]; 5769 5770 u8 rx_read_requests[0x20]; 5771 5772 u8 reserved_at_e0[0x20]; 5773 5774 u8 rx_atomic_requests[0x20]; 5775 5776 u8 reserved_at_120[0x20]; 5777 5778 u8 rx_dct_connect[0x20]; 5779 5780 u8 reserved_at_160[0x20]; 5781 5782 u8 out_of_buffer[0x20]; 5783 5784 u8 reserved_at_1a0[0x20]; 5785 5786 u8 out_of_sequence[0x20]; 5787 5788 u8 reserved_at_1e0[0x20]; 5789 5790 u8 duplicate_request[0x20]; 5791 5792 u8 reserved_at_220[0x20]; 5793 5794 u8 rnr_nak_retry_err[0x20]; 5795 5796 u8 reserved_at_260[0x20]; 5797 5798 u8 packet_seq_err[0x20]; 5799 5800 u8 reserved_at_2a0[0x20]; 5801 5802 u8 implied_nak_seq_err[0x20]; 5803 5804 u8 reserved_at_2e0[0x20]; 5805 5806 u8 local_ack_timeout_err[0x20]; 5807 5808 u8 reserved_at_320[0x60]; 5809 5810 u8 req_rnr_retries_exceeded[0x20]; 5811 5812 u8 reserved_at_3a0[0x20]; 5813 5814 u8 resp_local_length_error[0x20]; 5815 5816 u8 req_local_length_error[0x20]; 5817 5818 u8 resp_local_qp_error[0x20]; 5819 5820 u8 local_operation_error[0x20]; 5821 5822 u8 resp_local_protection[0x20]; 5823 5824 u8 req_local_protection[0x20]; 5825 5826 u8 resp_cqe_error[0x20]; 5827 5828 u8 req_cqe_error[0x20]; 5829 5830 u8 req_mw_binding[0x20]; 5831 5832 u8 req_bad_response[0x20]; 5833 5834 u8 req_remote_invalid_request[0x20]; 5835 5836 u8 resp_remote_invalid_request[0x20]; 5837 5838 u8 req_remote_access_errors[0x20]; 5839 5840 u8 resp_remote_access_errors[0x20]; 5841 5842 u8 req_remote_operation_errors[0x20]; 5843 5844 u8 req_transport_retries_exceeded[0x20]; 5845 5846 u8 cq_overflow[0x20]; 5847 5848 u8 resp_cqe_flush_error[0x20]; 5849 5850 u8 req_cqe_flush_error[0x20]; 5851 5852 u8 reserved_at_620[0x20]; 5853 5854 u8 roce_adp_retrans[0x20]; 5855 5856 u8 roce_adp_retrans_to[0x20]; 5857 5858 u8 roce_slow_restart[0x20]; 5859 5860 u8 roce_slow_restart_cnps[0x20]; 5861 5862 u8 roce_slow_restart_trans[0x20]; 5863 5864 u8 reserved_at_6e0[0x120]; 5865 }; 5866 5867 struct mlx5_ifc_query_q_counter_in_bits { 5868 u8 opcode[0x10]; 5869 u8 reserved_at_10[0x10]; 5870 5871 u8 reserved_at_20[0x10]; 5872 u8 op_mod[0x10]; 5873 5874 u8 other_vport[0x1]; 5875 u8 reserved_at_41[0xf]; 5876 u8 vport_number[0x10]; 5877 5878 u8 reserved_at_60[0x60]; 5879 5880 u8 clear[0x1]; 5881 u8 aggregate[0x1]; 5882 u8 reserved_at_c2[0x1e]; 5883 5884 u8 reserved_at_e0[0x18]; 5885 u8 counter_set_id[0x8]; 5886 }; 5887 5888 struct mlx5_ifc_query_pages_out_bits { 5889 u8 status[0x8]; 5890 u8 reserved_at_8[0x18]; 5891 5892 u8 syndrome[0x20]; 5893 5894 u8 embedded_cpu_function[0x1]; 5895 u8 reserved_at_41[0xf]; 5896 u8 function_id[0x10]; 5897 5898 u8 num_pages[0x20]; 5899 }; 5900 5901 enum { 5902 MLX5_QUERY_PAGES_IN_OP_MOD_BOOT_PAGES = 0x1, 5903 MLX5_QUERY_PAGES_IN_OP_MOD_INIT_PAGES = 0x2, 5904 MLX5_QUERY_PAGES_IN_OP_MOD_REGULAR_PAGES = 0x3, 5905 }; 5906 5907 struct mlx5_ifc_query_pages_in_bits { 5908 u8 opcode[0x10]; 5909 u8 reserved_at_10[0x10]; 5910 5911 u8 reserved_at_20[0x10]; 5912 u8 op_mod[0x10]; 5913 5914 u8 embedded_cpu_function[0x1]; 5915 u8 reserved_at_41[0xf]; 5916 u8 function_id[0x10]; 5917 5918 u8 reserved_at_60[0x20]; 5919 }; 5920 5921 struct mlx5_ifc_query_nic_vport_context_out_bits { 5922 u8 status[0x8]; 5923 u8 reserved_at_8[0x18]; 5924 5925 u8 syndrome[0x20]; 5926 5927 u8 reserved_at_40[0x40]; 5928 5929 struct mlx5_ifc_nic_vport_context_bits nic_vport_context; 5930 }; 5931 5932 struct mlx5_ifc_query_nic_vport_context_in_bits { 5933 u8 opcode[0x10]; 5934 u8 reserved_at_10[0x10]; 5935 5936 u8 reserved_at_20[0x10]; 5937 u8 op_mod[0x10]; 5938 5939 u8 other_vport[0x1]; 5940 u8 reserved_at_41[0xf]; 5941 u8 vport_number[0x10]; 5942 5943 u8 reserved_at_60[0x5]; 5944 u8 allowed_list_type[0x3]; 5945 u8 reserved_at_68[0x18]; 5946 }; 5947 5948 struct mlx5_ifc_query_mkey_out_bits { 5949 u8 status[0x8]; 5950 u8 reserved_at_8[0x18]; 5951 5952 u8 syndrome[0x20]; 5953 5954 u8 reserved_at_40[0x40]; 5955 5956 struct mlx5_ifc_mkc_bits memory_key_mkey_entry; 5957 5958 u8 reserved_at_280[0x600]; 5959 5960 u8 bsf0_klm0_pas_mtt0_1[16][0x8]; 5961 5962 u8 bsf1_klm1_pas_mtt2_3[16][0x8]; 5963 }; 5964 5965 struct mlx5_ifc_query_mkey_in_bits { 5966 u8 opcode[0x10]; 5967 u8 reserved_at_10[0x10]; 5968 5969 u8 reserved_at_20[0x10]; 5970 u8 op_mod[0x10]; 5971 5972 u8 reserved_at_40[0x8]; 5973 u8 mkey_index[0x18]; 5974 5975 u8 pg_access[0x1]; 5976 u8 reserved_at_61[0x1f]; 5977 }; 5978 5979 struct mlx5_ifc_query_mad_demux_out_bits { 5980 u8 status[0x8]; 5981 u8 reserved_at_8[0x18]; 5982 5983 u8 syndrome[0x20]; 5984 5985 u8 reserved_at_40[0x40]; 5986 5987 u8 mad_dumux_parameters_block[0x20]; 5988 }; 5989 5990 struct mlx5_ifc_query_mad_demux_in_bits { 5991 u8 opcode[0x10]; 5992 u8 reserved_at_10[0x10]; 5993 5994 u8 reserved_at_20[0x10]; 5995 u8 op_mod[0x10]; 5996 5997 u8 reserved_at_40[0x40]; 5998 }; 5999 6000 struct mlx5_ifc_query_l2_table_entry_out_bits { 6001 u8 status[0x8]; 6002 u8 reserved_at_8[0x18]; 6003 6004 u8 syndrome[0x20]; 6005 6006 u8 reserved_at_40[0xa0]; 6007 6008 u8 reserved_at_e0[0x13]; 6009 u8 vlan_valid[0x1]; 6010 u8 vlan[0xc]; 6011 6012 struct mlx5_ifc_mac_address_layout_bits mac_address; 6013 6014 u8 reserved_at_140[0xc0]; 6015 }; 6016 6017 struct mlx5_ifc_query_l2_table_entry_in_bits { 6018 u8 opcode[0x10]; 6019 u8 reserved_at_10[0x10]; 6020 6021 u8 reserved_at_20[0x10]; 6022 u8 op_mod[0x10]; 6023 6024 u8 reserved_at_40[0x60]; 6025 6026 u8 reserved_at_a0[0x8]; 6027 u8 table_index[0x18]; 6028 6029 u8 reserved_at_c0[0x140]; 6030 }; 6031 6032 struct mlx5_ifc_query_issi_out_bits { 6033 u8 status[0x8]; 6034 u8 reserved_at_8[0x18]; 6035 6036 u8 syndrome[0x20]; 6037 6038 u8 reserved_at_40[0x10]; 6039 u8 current_issi[0x10]; 6040 6041 u8 reserved_at_60[0xa0]; 6042 6043 u8 reserved_at_100[76][0x8]; 6044 u8 supported_issi_dw0[0x20]; 6045 }; 6046 6047 struct mlx5_ifc_query_issi_in_bits { 6048 u8 opcode[0x10]; 6049 u8 reserved_at_10[0x10]; 6050 6051 u8 reserved_at_20[0x10]; 6052 u8 op_mod[0x10]; 6053 6054 u8 reserved_at_40[0x40]; 6055 }; 6056 6057 struct mlx5_ifc_set_driver_version_out_bits { 6058 u8 status[0x8]; 6059 u8 reserved_0[0x18]; 6060 6061 u8 syndrome[0x20]; 6062 u8 reserved_1[0x40]; 6063 }; 6064 6065 struct mlx5_ifc_set_driver_version_in_bits { 6066 u8 opcode[0x10]; 6067 u8 reserved_0[0x10]; 6068 6069 u8 reserved_1[0x10]; 6070 u8 op_mod[0x10]; 6071 6072 u8 reserved_2[0x40]; 6073 u8 driver_version[64][0x8]; 6074 }; 6075 6076 struct mlx5_ifc_query_hca_vport_pkey_out_bits { 6077 u8 status[0x8]; 6078 u8 reserved_at_8[0x18]; 6079 6080 u8 syndrome[0x20]; 6081 6082 u8 reserved_at_40[0x40]; 6083 6084 struct mlx5_ifc_pkey_bits pkey[]; 6085 }; 6086 6087 struct mlx5_ifc_query_hca_vport_pkey_in_bits { 6088 u8 opcode[0x10]; 6089 u8 reserved_at_10[0x10]; 6090 6091 u8 reserved_at_20[0x10]; 6092 u8 op_mod[0x10]; 6093 6094 u8 other_vport[0x1]; 6095 u8 reserved_at_41[0xb]; 6096 u8 port_num[0x4]; 6097 u8 vport_number[0x10]; 6098 6099 u8 reserved_at_60[0x10]; 6100 u8 pkey_index[0x10]; 6101 }; 6102 6103 enum { 6104 MLX5_HCA_VPORT_SEL_PORT_GUID = 1 << 0, 6105 MLX5_HCA_VPORT_SEL_NODE_GUID = 1 << 1, 6106 MLX5_HCA_VPORT_SEL_STATE_POLICY = 1 << 2, 6107 }; 6108 6109 struct mlx5_ifc_query_hca_vport_gid_out_bits { 6110 u8 status[0x8]; 6111 u8 reserved_at_8[0x18]; 6112 6113 u8 syndrome[0x20]; 6114 6115 u8 reserved_at_40[0x20]; 6116 6117 u8 gids_num[0x10]; 6118 u8 reserved_at_70[0x10]; 6119 6120 struct mlx5_ifc_array128_auto_bits gid[]; 6121 }; 6122 6123 struct mlx5_ifc_query_hca_vport_gid_in_bits { 6124 u8 opcode[0x10]; 6125 u8 reserved_at_10[0x10]; 6126 6127 u8 reserved_at_20[0x10]; 6128 u8 op_mod[0x10]; 6129 6130 u8 other_vport[0x1]; 6131 u8 reserved_at_41[0xb]; 6132 u8 port_num[0x4]; 6133 u8 vport_number[0x10]; 6134 6135 u8 reserved_at_60[0x10]; 6136 u8 gid_index[0x10]; 6137 }; 6138 6139 struct mlx5_ifc_query_hca_vport_context_out_bits { 6140 u8 status[0x8]; 6141 u8 reserved_at_8[0x18]; 6142 6143 u8 syndrome[0x20]; 6144 6145 u8 reserved_at_40[0x40]; 6146 6147 struct mlx5_ifc_hca_vport_context_bits hca_vport_context; 6148 }; 6149 6150 struct mlx5_ifc_query_hca_vport_context_in_bits { 6151 u8 opcode[0x10]; 6152 u8 reserved_at_10[0x10]; 6153 6154 u8 reserved_at_20[0x10]; 6155 u8 op_mod[0x10]; 6156 6157 u8 other_vport[0x1]; 6158 u8 reserved_at_41[0xb]; 6159 u8 port_num[0x4]; 6160 u8 vport_number[0x10]; 6161 6162 u8 reserved_at_60[0x20]; 6163 }; 6164 6165 struct mlx5_ifc_query_hca_cap_out_bits { 6166 u8 status[0x8]; 6167 u8 reserved_at_8[0x18]; 6168 6169 u8 syndrome[0x20]; 6170 6171 u8 reserved_at_40[0x40]; 6172 6173 union mlx5_ifc_hca_cap_union_bits capability; 6174 }; 6175 6176 struct mlx5_ifc_query_hca_cap_in_bits { 6177 u8 opcode[0x10]; 6178 u8 reserved_at_10[0x10]; 6179 6180 u8 reserved_at_20[0x10]; 6181 u8 op_mod[0x10]; 6182 6183 u8 other_function[0x1]; 6184 u8 ec_vf_function[0x1]; 6185 u8 reserved_at_42[0xe]; 6186 u8 function_id[0x10]; 6187 6188 u8 reserved_at_60[0x20]; 6189 }; 6190 6191 struct mlx5_ifc_other_hca_cap_bits { 6192 u8 roce[0x1]; 6193 u8 reserved_at_1[0x27f]; 6194 }; 6195 6196 struct mlx5_ifc_query_other_hca_cap_out_bits { 6197 u8 status[0x8]; 6198 u8 reserved_at_8[0x18]; 6199 6200 u8 syndrome[0x20]; 6201 6202 u8 reserved_at_40[0x40]; 6203 6204 struct mlx5_ifc_other_hca_cap_bits other_capability; 6205 }; 6206 6207 struct mlx5_ifc_query_other_hca_cap_in_bits { 6208 u8 opcode[0x10]; 6209 u8 reserved_at_10[0x10]; 6210 6211 u8 reserved_at_20[0x10]; 6212 u8 op_mod[0x10]; 6213 6214 u8 reserved_at_40[0x10]; 6215 u8 function_id[0x10]; 6216 6217 u8 reserved_at_60[0x20]; 6218 }; 6219 6220 struct mlx5_ifc_modify_other_hca_cap_out_bits { 6221 u8 status[0x8]; 6222 u8 reserved_at_8[0x18]; 6223 6224 u8 syndrome[0x20]; 6225 6226 u8 reserved_at_40[0x40]; 6227 }; 6228 6229 struct mlx5_ifc_modify_other_hca_cap_in_bits { 6230 u8 opcode[0x10]; 6231 u8 reserved_at_10[0x10]; 6232 6233 u8 reserved_at_20[0x10]; 6234 u8 op_mod[0x10]; 6235 6236 u8 reserved_at_40[0x10]; 6237 u8 function_id[0x10]; 6238 u8 field_select[0x20]; 6239 6240 struct mlx5_ifc_other_hca_cap_bits other_capability; 6241 }; 6242 6243 struct mlx5_ifc_flow_table_context_bits { 6244 u8 reformat_en[0x1]; 6245 u8 decap_en[0x1]; 6246 u8 sw_owner[0x1]; 6247 u8 termination_table[0x1]; 6248 u8 table_miss_action[0x4]; 6249 u8 level[0x8]; 6250 u8 rtc_valid[0x1]; 6251 u8 reserved_at_11[0x7]; 6252 u8 log_size[0x8]; 6253 6254 u8 reserved_at_20[0x8]; 6255 u8 table_miss_id[0x18]; 6256 6257 u8 reserved_at_40[0x8]; 6258 u8 lag_master_next_table_id[0x18]; 6259 6260 u8 reserved_at_60[0x60]; 6261 union { 6262 struct { 6263 u8 sw_owner_icm_root_1[0x40]; 6264 6265 u8 sw_owner_icm_root_0[0x40]; 6266 } sws; 6267 struct { 6268 u8 rtc_id_0[0x20]; 6269 6270 u8 rtc_id_1[0x20]; 6271 6272 u8 reserved_at_100[0x40]; 6273 6274 } hws; 6275 }; 6276 }; 6277 6278 struct mlx5_ifc_query_flow_table_out_bits { 6279 u8 status[0x8]; 6280 u8 reserved_at_8[0x18]; 6281 6282 u8 syndrome[0x20]; 6283 6284 u8 reserved_at_40[0x80]; 6285 6286 struct mlx5_ifc_flow_table_context_bits flow_table_context; 6287 }; 6288 6289 struct mlx5_ifc_query_flow_table_in_bits { 6290 u8 opcode[0x10]; 6291 u8 reserved_at_10[0x10]; 6292 6293 u8 reserved_at_20[0x10]; 6294 u8 op_mod[0x10]; 6295 6296 u8 reserved_at_40[0x40]; 6297 6298 u8 table_type[0x8]; 6299 u8 reserved_at_88[0x18]; 6300 6301 u8 reserved_at_a0[0x8]; 6302 u8 table_id[0x18]; 6303 6304 u8 reserved_at_c0[0x140]; 6305 }; 6306 6307 struct mlx5_ifc_query_fte_out_bits { 6308 u8 status[0x8]; 6309 u8 reserved_at_8[0x18]; 6310 6311 u8 syndrome[0x20]; 6312 6313 u8 reserved_at_40[0x1c0]; 6314 6315 struct mlx5_ifc_flow_context_bits flow_context; 6316 }; 6317 6318 struct mlx5_ifc_query_fte_in_bits { 6319 u8 opcode[0x10]; 6320 u8 reserved_at_10[0x10]; 6321 6322 u8 reserved_at_20[0x10]; 6323 u8 op_mod[0x10]; 6324 6325 u8 reserved_at_40[0x40]; 6326 6327 u8 table_type[0x8]; 6328 u8 reserved_at_88[0x18]; 6329 6330 u8 reserved_at_a0[0x8]; 6331 u8 table_id[0x18]; 6332 6333 u8 reserved_at_c0[0x40]; 6334 6335 u8 flow_index[0x20]; 6336 6337 u8 reserved_at_120[0xe0]; 6338 }; 6339 6340 struct mlx5_ifc_match_definer_format_0_bits { 6341 u8 reserved_at_0[0x100]; 6342 6343 u8 metadata_reg_c_0[0x20]; 6344 6345 u8 metadata_reg_c_1[0x20]; 6346 6347 u8 outer_dmac_47_16[0x20]; 6348 6349 u8 outer_dmac_15_0[0x10]; 6350 u8 outer_ethertype[0x10]; 6351 6352 u8 reserved_at_180[0x1]; 6353 u8 sx_sniffer[0x1]; 6354 u8 functional_lb[0x1]; 6355 u8 outer_ip_frag[0x1]; 6356 u8 outer_qp_type[0x2]; 6357 u8 outer_encap_type[0x2]; 6358 u8 port_number[0x2]; 6359 u8 outer_l3_type[0x2]; 6360 u8 outer_l4_type[0x2]; 6361 u8 outer_first_vlan_type[0x2]; 6362 u8 outer_first_vlan_prio[0x3]; 6363 u8 outer_first_vlan_cfi[0x1]; 6364 u8 outer_first_vlan_vid[0xc]; 6365 6366 u8 outer_l4_type_ext[0x4]; 6367 u8 reserved_at_1a4[0x2]; 6368 u8 outer_ipsec_layer[0x2]; 6369 u8 outer_l2_type[0x2]; 6370 u8 force_lb[0x1]; 6371 u8 outer_l2_ok[0x1]; 6372 u8 outer_l3_ok[0x1]; 6373 u8 outer_l4_ok[0x1]; 6374 u8 outer_second_vlan_type[0x2]; 6375 u8 outer_second_vlan_prio[0x3]; 6376 u8 outer_second_vlan_cfi[0x1]; 6377 u8 outer_second_vlan_vid[0xc]; 6378 6379 u8 outer_smac_47_16[0x20]; 6380 6381 u8 outer_smac_15_0[0x10]; 6382 u8 inner_ipv4_checksum_ok[0x1]; 6383 u8 inner_l4_checksum_ok[0x1]; 6384 u8 outer_ipv4_checksum_ok[0x1]; 6385 u8 outer_l4_checksum_ok[0x1]; 6386 u8 inner_l3_ok[0x1]; 6387 u8 inner_l4_ok[0x1]; 6388 u8 outer_l3_ok_duplicate[0x1]; 6389 u8 outer_l4_ok_duplicate[0x1]; 6390 u8 outer_tcp_cwr[0x1]; 6391 u8 outer_tcp_ece[0x1]; 6392 u8 outer_tcp_urg[0x1]; 6393 u8 outer_tcp_ack[0x1]; 6394 u8 outer_tcp_psh[0x1]; 6395 u8 outer_tcp_rst[0x1]; 6396 u8 outer_tcp_syn[0x1]; 6397 u8 outer_tcp_fin[0x1]; 6398 }; 6399 6400 struct mlx5_ifc_match_definer_format_22_bits { 6401 u8 reserved_at_0[0x100]; 6402 6403 u8 outer_ip_src_addr[0x20]; 6404 6405 u8 outer_ip_dest_addr[0x20]; 6406 6407 u8 outer_l4_sport[0x10]; 6408 u8 outer_l4_dport[0x10]; 6409 6410 u8 reserved_at_160[0x1]; 6411 u8 sx_sniffer[0x1]; 6412 u8 functional_lb[0x1]; 6413 u8 outer_ip_frag[0x1]; 6414 u8 outer_qp_type[0x2]; 6415 u8 outer_encap_type[0x2]; 6416 u8 port_number[0x2]; 6417 u8 outer_l3_type[0x2]; 6418 u8 outer_l4_type[0x2]; 6419 u8 outer_first_vlan_type[0x2]; 6420 u8 outer_first_vlan_prio[0x3]; 6421 u8 outer_first_vlan_cfi[0x1]; 6422 u8 outer_first_vlan_vid[0xc]; 6423 6424 u8 metadata_reg_c_0[0x20]; 6425 6426 u8 outer_dmac_47_16[0x20]; 6427 6428 u8 outer_smac_47_16[0x20]; 6429 6430 u8 outer_smac_15_0[0x10]; 6431 u8 outer_dmac_15_0[0x10]; 6432 }; 6433 6434 struct mlx5_ifc_match_definer_format_23_bits { 6435 u8 reserved_at_0[0x100]; 6436 6437 u8 inner_ip_src_addr[0x20]; 6438 6439 u8 inner_ip_dest_addr[0x20]; 6440 6441 u8 inner_l4_sport[0x10]; 6442 u8 inner_l4_dport[0x10]; 6443 6444 u8 reserved_at_160[0x1]; 6445 u8 sx_sniffer[0x1]; 6446 u8 functional_lb[0x1]; 6447 u8 inner_ip_frag[0x1]; 6448 u8 inner_qp_type[0x2]; 6449 u8 inner_encap_type[0x2]; 6450 u8 port_number[0x2]; 6451 u8 inner_l3_type[0x2]; 6452 u8 inner_l4_type[0x2]; 6453 u8 inner_first_vlan_type[0x2]; 6454 u8 inner_first_vlan_prio[0x3]; 6455 u8 inner_first_vlan_cfi[0x1]; 6456 u8 inner_first_vlan_vid[0xc]; 6457 6458 u8 tunnel_header_0[0x20]; 6459 6460 u8 inner_dmac_47_16[0x20]; 6461 6462 u8 inner_smac_47_16[0x20]; 6463 6464 u8 inner_smac_15_0[0x10]; 6465 u8 inner_dmac_15_0[0x10]; 6466 }; 6467 6468 struct mlx5_ifc_match_definer_format_29_bits { 6469 u8 reserved_at_0[0xc0]; 6470 6471 u8 outer_ip_dest_addr[0x80]; 6472 6473 u8 outer_ip_src_addr[0x80]; 6474 6475 u8 outer_l4_sport[0x10]; 6476 u8 outer_l4_dport[0x10]; 6477 6478 u8 reserved_at_1e0[0x20]; 6479 }; 6480 6481 struct mlx5_ifc_match_definer_format_30_bits { 6482 u8 reserved_at_0[0xa0]; 6483 6484 u8 outer_ip_dest_addr[0x80]; 6485 6486 u8 outer_ip_src_addr[0x80]; 6487 6488 u8 outer_dmac_47_16[0x20]; 6489 6490 u8 outer_smac_47_16[0x20]; 6491 6492 u8 outer_smac_15_0[0x10]; 6493 u8 outer_dmac_15_0[0x10]; 6494 }; 6495 6496 struct mlx5_ifc_match_definer_format_31_bits { 6497 u8 reserved_at_0[0xc0]; 6498 6499 u8 inner_ip_dest_addr[0x80]; 6500 6501 u8 inner_ip_src_addr[0x80]; 6502 6503 u8 inner_l4_sport[0x10]; 6504 u8 inner_l4_dport[0x10]; 6505 6506 u8 reserved_at_1e0[0x20]; 6507 }; 6508 6509 struct mlx5_ifc_match_definer_format_32_bits { 6510 u8 reserved_at_0[0xa0]; 6511 6512 u8 inner_ip_dest_addr[0x80]; 6513 6514 u8 inner_ip_src_addr[0x80]; 6515 6516 u8 inner_dmac_47_16[0x20]; 6517 6518 u8 inner_smac_47_16[0x20]; 6519 6520 u8 inner_smac_15_0[0x10]; 6521 u8 inner_dmac_15_0[0x10]; 6522 }; 6523 6524 enum { 6525 MLX5_IFC_DEFINER_FORMAT_ID_SELECT = 61, 6526 }; 6527 6528 #define MLX5_IFC_DEFINER_FORMAT_OFFSET_UNUSED 0x0 6529 #define MLX5_IFC_DEFINER_FORMAT_OFFSET_OUTER_ETH_PKT_LEN 0x48 6530 #define MLX5_IFC_DEFINER_DW_SELECTORS_NUM 9 6531 #define MLX5_IFC_DEFINER_BYTE_SELECTORS_NUM 8 6532 6533 struct mlx5_ifc_match_definer_match_mask_bits { 6534 u8 reserved_at_1c0[5][0x20]; 6535 u8 match_dw_8[0x20]; 6536 u8 match_dw_7[0x20]; 6537 u8 match_dw_6[0x20]; 6538 u8 match_dw_5[0x20]; 6539 u8 match_dw_4[0x20]; 6540 u8 match_dw_3[0x20]; 6541 u8 match_dw_2[0x20]; 6542 u8 match_dw_1[0x20]; 6543 u8 match_dw_0[0x20]; 6544 6545 u8 match_byte_7[0x8]; 6546 u8 match_byte_6[0x8]; 6547 u8 match_byte_5[0x8]; 6548 u8 match_byte_4[0x8]; 6549 6550 u8 match_byte_3[0x8]; 6551 u8 match_byte_2[0x8]; 6552 u8 match_byte_1[0x8]; 6553 u8 match_byte_0[0x8]; 6554 }; 6555 6556 struct mlx5_ifc_match_definer_bits { 6557 u8 modify_field_select[0x40]; 6558 6559 u8 reserved_at_40[0x40]; 6560 6561 u8 reserved_at_80[0x10]; 6562 u8 format_id[0x10]; 6563 6564 u8 reserved_at_a0[0x60]; 6565 6566 u8 format_select_dw3[0x8]; 6567 u8 format_select_dw2[0x8]; 6568 u8 format_select_dw1[0x8]; 6569 u8 format_select_dw0[0x8]; 6570 6571 u8 format_select_dw7[0x8]; 6572 u8 format_select_dw6[0x8]; 6573 u8 format_select_dw5[0x8]; 6574 u8 format_select_dw4[0x8]; 6575 6576 u8 reserved_at_100[0x18]; 6577 u8 format_select_dw8[0x8]; 6578 6579 u8 reserved_at_120[0x20]; 6580 6581 u8 format_select_byte3[0x8]; 6582 u8 format_select_byte2[0x8]; 6583 u8 format_select_byte1[0x8]; 6584 u8 format_select_byte0[0x8]; 6585 6586 u8 format_select_byte7[0x8]; 6587 u8 format_select_byte6[0x8]; 6588 u8 format_select_byte5[0x8]; 6589 u8 format_select_byte4[0x8]; 6590 6591 u8 reserved_at_180[0x40]; 6592 6593 union { 6594 struct { 6595 u8 match_mask[16][0x20]; 6596 }; 6597 struct mlx5_ifc_match_definer_match_mask_bits match_mask_format; 6598 }; 6599 }; 6600 6601 struct mlx5_ifc_general_obj_create_param_bits { 6602 u8 alias_object[0x1]; 6603 u8 reserved_at_1[0x2]; 6604 u8 log_obj_range[0x5]; 6605 u8 reserved_at_8[0x18]; 6606 }; 6607 6608 struct mlx5_ifc_general_obj_query_param_bits { 6609 u8 alias_object[0x1]; 6610 u8 obj_offset[0x1f]; 6611 }; 6612 6613 struct mlx5_ifc_general_obj_in_cmd_hdr_bits { 6614 u8 opcode[0x10]; 6615 u8 uid[0x10]; 6616 6617 u8 vhca_tunnel_id[0x10]; 6618 u8 obj_type[0x10]; 6619 6620 u8 obj_id[0x20]; 6621 6622 union { 6623 struct mlx5_ifc_general_obj_create_param_bits create; 6624 struct mlx5_ifc_general_obj_query_param_bits query; 6625 } op_param; 6626 }; 6627 6628 struct mlx5_ifc_general_obj_out_cmd_hdr_bits { 6629 u8 status[0x8]; 6630 u8 reserved_at_8[0x18]; 6631 6632 u8 syndrome[0x20]; 6633 6634 u8 obj_id[0x20]; 6635 6636 u8 reserved_at_60[0x20]; 6637 }; 6638 6639 struct mlx5_ifc_allow_other_vhca_access_in_bits { 6640 u8 opcode[0x10]; 6641 u8 uid[0x10]; 6642 u8 reserved_at_20[0x10]; 6643 u8 op_mod[0x10]; 6644 u8 reserved_at_40[0x50]; 6645 u8 object_type_to_be_accessed[0x10]; 6646 u8 object_id_to_be_accessed[0x20]; 6647 u8 reserved_at_c0[0x40]; 6648 union { 6649 u8 access_key_raw[0x100]; 6650 u8 access_key[8][0x20]; 6651 }; 6652 }; 6653 6654 struct mlx5_ifc_allow_other_vhca_access_out_bits { 6655 u8 status[0x8]; 6656 u8 reserved_at_8[0x18]; 6657 u8 syndrome[0x20]; 6658 u8 reserved_at_40[0x40]; 6659 }; 6660 6661 struct mlx5_ifc_modify_header_arg_bits { 6662 u8 reserved_at_0[0x80]; 6663 6664 u8 reserved_at_80[0x8]; 6665 u8 access_pd[0x18]; 6666 }; 6667 6668 struct mlx5_ifc_create_modify_header_arg_in_bits { 6669 struct mlx5_ifc_general_obj_in_cmd_hdr_bits hdr; 6670 struct mlx5_ifc_modify_header_arg_bits arg; 6671 }; 6672 6673 struct mlx5_ifc_create_match_definer_in_bits { 6674 struct mlx5_ifc_general_obj_in_cmd_hdr_bits general_obj_in_cmd_hdr; 6675 6676 struct mlx5_ifc_match_definer_bits obj_context; 6677 }; 6678 6679 struct mlx5_ifc_create_match_definer_out_bits { 6680 struct mlx5_ifc_general_obj_out_cmd_hdr_bits general_obj_out_cmd_hdr; 6681 }; 6682 6683 struct mlx5_ifc_alias_context_bits { 6684 u8 vhca_id_to_be_accessed[0x10]; 6685 u8 reserved_at_10[0xd]; 6686 u8 status[0x3]; 6687 u8 object_id_to_be_accessed[0x20]; 6688 u8 reserved_at_40[0x40]; 6689 union { 6690 u8 access_key_raw[0x100]; 6691 u8 access_key[8][0x20]; 6692 }; 6693 u8 metadata[0x80]; 6694 }; 6695 6696 struct mlx5_ifc_create_alias_obj_in_bits { 6697 struct mlx5_ifc_general_obj_in_cmd_hdr_bits hdr; 6698 struct mlx5_ifc_alias_context_bits alias_ctx; 6699 }; 6700 6701 enum { 6702 MLX5_QUERY_FLOW_GROUP_OUT_MATCH_CRITERIA_ENABLE_OUTER_HEADERS = 0x0, 6703 MLX5_QUERY_FLOW_GROUP_OUT_MATCH_CRITERIA_ENABLE_MISC_PARAMETERS = 0x1, 6704 MLX5_QUERY_FLOW_GROUP_OUT_MATCH_CRITERIA_ENABLE_INNER_HEADERS = 0x2, 6705 MLX5_QUERY_FLOW_GROUP_IN_MATCH_CRITERIA_ENABLE_MISC_PARAMETERS_2 = 0x3, 6706 MLX5_QUERY_FLOW_GROUP_IN_MATCH_CRITERIA_ENABLE_MISC_PARAMETERS_3 = 0x4, 6707 MLX5_QUERY_FLOW_GROUP_IN_MATCH_CRITERIA_ENABLE_MISC_PARAMETERS_4 = 0x5, 6708 MLX5_QUERY_FLOW_GROUP_IN_MATCH_CRITERIA_ENABLE_MISC_PARAMETERS_5 = 0x6, 6709 }; 6710 6711 struct mlx5_ifc_query_flow_group_out_bits { 6712 u8 status[0x8]; 6713 u8 reserved_at_8[0x18]; 6714 6715 u8 syndrome[0x20]; 6716 6717 u8 reserved_at_40[0xa0]; 6718 6719 u8 start_flow_index[0x20]; 6720 6721 u8 reserved_at_100[0x20]; 6722 6723 u8 end_flow_index[0x20]; 6724 6725 u8 reserved_at_140[0xa0]; 6726 6727 u8 reserved_at_1e0[0x18]; 6728 u8 match_criteria_enable[0x8]; 6729 6730 struct mlx5_ifc_fte_match_param_bits match_criteria; 6731 6732 u8 reserved_at_1200[0xe00]; 6733 }; 6734 6735 struct mlx5_ifc_query_flow_group_in_bits { 6736 u8 opcode[0x10]; 6737 u8 reserved_at_10[0x10]; 6738 6739 u8 reserved_at_20[0x10]; 6740 u8 op_mod[0x10]; 6741 6742 u8 reserved_at_40[0x40]; 6743 6744 u8 table_type[0x8]; 6745 u8 reserved_at_88[0x18]; 6746 6747 u8 reserved_at_a0[0x8]; 6748 u8 table_id[0x18]; 6749 6750 u8 group_id[0x20]; 6751 6752 u8 reserved_at_e0[0x120]; 6753 }; 6754 6755 struct mlx5_ifc_query_flow_counter_out_bits { 6756 u8 status[0x8]; 6757 u8 reserved_at_8[0x18]; 6758 6759 u8 syndrome[0x20]; 6760 6761 u8 reserved_at_40[0x40]; 6762 6763 struct mlx5_ifc_traffic_counter_bits flow_statistics[]; 6764 }; 6765 6766 struct mlx5_ifc_query_flow_counter_in_bits { 6767 u8 opcode[0x10]; 6768 u8 reserved_at_10[0x10]; 6769 6770 u8 reserved_at_20[0x10]; 6771 u8 op_mod[0x10]; 6772 6773 u8 reserved_at_40[0x80]; 6774 6775 u8 clear[0x1]; 6776 u8 reserved_at_c1[0xf]; 6777 u8 num_of_counters[0x10]; 6778 6779 u8 flow_counter_id[0x20]; 6780 }; 6781 6782 struct mlx5_ifc_query_esw_vport_context_out_bits { 6783 u8 status[0x8]; 6784 u8 reserved_at_8[0x18]; 6785 6786 u8 syndrome[0x20]; 6787 6788 u8 reserved_at_40[0x40]; 6789 6790 struct mlx5_ifc_esw_vport_context_bits esw_vport_context; 6791 }; 6792 6793 struct mlx5_ifc_query_esw_vport_context_in_bits { 6794 u8 opcode[0x10]; 6795 u8 reserved_at_10[0x10]; 6796 6797 u8 reserved_at_20[0x10]; 6798 u8 op_mod[0x10]; 6799 6800 u8 other_vport[0x1]; 6801 u8 reserved_at_41[0xf]; 6802 u8 vport_number[0x10]; 6803 6804 u8 reserved_at_60[0x20]; 6805 }; 6806 6807 struct mlx5_ifc_modify_esw_vport_context_out_bits { 6808 u8 status[0x8]; 6809 u8 reserved_at_8[0x18]; 6810 6811 u8 syndrome[0x20]; 6812 6813 u8 reserved_at_40[0x40]; 6814 }; 6815 6816 struct mlx5_ifc_esw_vport_context_fields_select_bits { 6817 u8 reserved_at_0[0x1b]; 6818 u8 fdb_to_vport_reg_c_id[0x1]; 6819 u8 vport_cvlan_insert[0x1]; 6820 u8 vport_svlan_insert[0x1]; 6821 u8 vport_cvlan_strip[0x1]; 6822 u8 vport_svlan_strip[0x1]; 6823 }; 6824 6825 struct mlx5_ifc_modify_esw_vport_context_in_bits { 6826 u8 opcode[0x10]; 6827 u8 reserved_at_10[0x10]; 6828 6829 u8 reserved_at_20[0x10]; 6830 u8 op_mod[0x10]; 6831 6832 u8 other_vport[0x1]; 6833 u8 reserved_at_41[0xf]; 6834 u8 vport_number[0x10]; 6835 6836 struct mlx5_ifc_esw_vport_context_fields_select_bits field_select; 6837 6838 struct mlx5_ifc_esw_vport_context_bits esw_vport_context; 6839 }; 6840 6841 struct mlx5_ifc_query_eq_out_bits { 6842 u8 status[0x8]; 6843 u8 reserved_at_8[0x18]; 6844 6845 u8 syndrome[0x20]; 6846 6847 u8 reserved_at_40[0x40]; 6848 6849 struct mlx5_ifc_eqc_bits eq_context_entry; 6850 6851 u8 reserved_at_280[0x40]; 6852 6853 u8 event_bitmask[0x40]; 6854 6855 u8 reserved_at_300[0x580]; 6856 6857 u8 pas[][0x40]; 6858 }; 6859 6860 struct mlx5_ifc_query_eq_in_bits { 6861 u8 opcode[0x10]; 6862 u8 reserved_at_10[0x10]; 6863 6864 u8 reserved_at_20[0x10]; 6865 u8 op_mod[0x10]; 6866 6867 u8 reserved_at_40[0x18]; 6868 u8 eq_number[0x8]; 6869 6870 u8 reserved_at_60[0x20]; 6871 }; 6872 6873 struct mlx5_ifc_packet_reformat_context_in_bits { 6874 u8 reformat_type[0x8]; 6875 u8 reserved_at_8[0x4]; 6876 u8 reformat_param_0[0x4]; 6877 u8 reserved_at_10[0x6]; 6878 u8 reformat_data_size[0xa]; 6879 6880 u8 reformat_param_1[0x8]; 6881 u8 reserved_at_28[0x8]; 6882 u8 reformat_data[2][0x8]; 6883 6884 u8 more_reformat_data[][0x8]; 6885 }; 6886 6887 struct mlx5_ifc_query_packet_reformat_context_out_bits { 6888 u8 status[0x8]; 6889 u8 reserved_at_8[0x18]; 6890 6891 u8 syndrome[0x20]; 6892 6893 u8 reserved_at_40[0xa0]; 6894 6895 struct mlx5_ifc_packet_reformat_context_in_bits packet_reformat_context[]; 6896 }; 6897 6898 struct mlx5_ifc_query_packet_reformat_context_in_bits { 6899 u8 opcode[0x10]; 6900 u8 reserved_at_10[0x10]; 6901 6902 u8 reserved_at_20[0x10]; 6903 u8 op_mod[0x10]; 6904 6905 u8 packet_reformat_id[0x20]; 6906 6907 u8 reserved_at_60[0xa0]; 6908 }; 6909 6910 struct mlx5_ifc_alloc_packet_reformat_context_out_bits { 6911 u8 status[0x8]; 6912 u8 reserved_at_8[0x18]; 6913 6914 u8 syndrome[0x20]; 6915 6916 u8 packet_reformat_id[0x20]; 6917 6918 u8 reserved_at_60[0x20]; 6919 }; 6920 6921 enum { 6922 MLX5_REFORMAT_CONTEXT_ANCHOR_MAC_START = 0x1, 6923 MLX5_REFORMAT_CONTEXT_ANCHOR_IP_START = 0x7, 6924 MLX5_REFORMAT_CONTEXT_ANCHOR_TCP_UDP_START = 0x9, 6925 }; 6926 6927 enum mlx5_reformat_ctx_type { 6928 MLX5_REFORMAT_TYPE_L2_TO_VXLAN = 0x0, 6929 MLX5_REFORMAT_TYPE_L2_TO_NVGRE = 0x1, 6930 MLX5_REFORMAT_TYPE_L2_TO_L2_TUNNEL = 0x2, 6931 MLX5_REFORMAT_TYPE_L3_TUNNEL_TO_L2 = 0x3, 6932 MLX5_REFORMAT_TYPE_L2_TO_L3_TUNNEL = 0x4, 6933 MLX5_REFORMAT_TYPE_ADD_ESP_TRANSPORT_OVER_IPV4 = 0x5, 6934 MLX5_REFORMAT_TYPE_L2_TO_L3_ESP_TUNNEL = 0x6, 6935 MLX5_REFORMAT_TYPE_ADD_ESP_TRANSPORT_OVER_UDPV4 = 0x7, 6936 MLX5_REFORMAT_TYPE_DEL_ESP_TRANSPORT = 0x8, 6937 MLX5_REFORMAT_TYPE_L3_ESP_TUNNEL_TO_L2 = 0x9, 6938 MLX5_REFORMAT_TYPE_DEL_ESP_TRANSPORT_OVER_UDP = 0xa, 6939 MLX5_REFORMAT_TYPE_ADD_ESP_TRANSPORT_OVER_IPV6 = 0xb, 6940 MLX5_REFORMAT_TYPE_ADD_ESP_TRANSPORT_OVER_UDPV6 = 0xc, 6941 MLX5_REFORMAT_TYPE_INSERT_HDR = 0xf, 6942 MLX5_REFORMAT_TYPE_REMOVE_HDR = 0x10, 6943 MLX5_REFORMAT_TYPE_ADD_MACSEC = 0x11, 6944 MLX5_REFORMAT_TYPE_DEL_MACSEC = 0x12, 6945 }; 6946 6947 struct mlx5_ifc_alloc_packet_reformat_context_in_bits { 6948 u8 opcode[0x10]; 6949 u8 reserved_at_10[0x10]; 6950 6951 u8 reserved_at_20[0x10]; 6952 u8 op_mod[0x10]; 6953 6954 u8 reserved_at_40[0xa0]; 6955 6956 struct mlx5_ifc_packet_reformat_context_in_bits packet_reformat_context; 6957 }; 6958 6959 struct mlx5_ifc_dealloc_packet_reformat_context_out_bits { 6960 u8 status[0x8]; 6961 u8 reserved_at_8[0x18]; 6962 6963 u8 syndrome[0x20]; 6964 6965 u8 reserved_at_40[0x40]; 6966 }; 6967 6968 struct mlx5_ifc_dealloc_packet_reformat_context_in_bits { 6969 u8 opcode[0x10]; 6970 u8 reserved_at_10[0x10]; 6971 6972 u8 reserved_20[0x10]; 6973 u8 op_mod[0x10]; 6974 6975 u8 packet_reformat_id[0x20]; 6976 6977 u8 reserved_60[0x20]; 6978 }; 6979 6980 struct mlx5_ifc_set_action_in_bits { 6981 u8 action_type[0x4]; 6982 u8 field[0xc]; 6983 u8 reserved_at_10[0x3]; 6984 u8 offset[0x5]; 6985 u8 reserved_at_18[0x3]; 6986 u8 length[0x5]; 6987 6988 u8 data[0x20]; 6989 }; 6990 6991 struct mlx5_ifc_add_action_in_bits { 6992 u8 action_type[0x4]; 6993 u8 field[0xc]; 6994 u8 reserved_at_10[0x10]; 6995 6996 u8 data[0x20]; 6997 }; 6998 6999 struct mlx5_ifc_copy_action_in_bits { 7000 u8 action_type[0x4]; 7001 u8 src_field[0xc]; 7002 u8 reserved_at_10[0x3]; 7003 u8 src_offset[0x5]; 7004 u8 reserved_at_18[0x3]; 7005 u8 length[0x5]; 7006 7007 u8 reserved_at_20[0x4]; 7008 u8 dst_field[0xc]; 7009 u8 reserved_at_30[0x3]; 7010 u8 dst_offset[0x5]; 7011 u8 reserved_at_38[0x8]; 7012 }; 7013 7014 union mlx5_ifc_set_add_copy_action_in_auto_bits { 7015 struct mlx5_ifc_set_action_in_bits set_action_in; 7016 struct mlx5_ifc_add_action_in_bits add_action_in; 7017 struct mlx5_ifc_copy_action_in_bits copy_action_in; 7018 u8 reserved_at_0[0x40]; 7019 }; 7020 7021 enum { 7022 MLX5_ACTION_TYPE_SET = 0x1, 7023 MLX5_ACTION_TYPE_ADD = 0x2, 7024 MLX5_ACTION_TYPE_COPY = 0x3, 7025 }; 7026 7027 enum { 7028 MLX5_ACTION_IN_FIELD_OUT_SMAC_47_16 = 0x1, 7029 MLX5_ACTION_IN_FIELD_OUT_SMAC_15_0 = 0x2, 7030 MLX5_ACTION_IN_FIELD_OUT_ETHERTYPE = 0x3, 7031 MLX5_ACTION_IN_FIELD_OUT_DMAC_47_16 = 0x4, 7032 MLX5_ACTION_IN_FIELD_OUT_DMAC_15_0 = 0x5, 7033 MLX5_ACTION_IN_FIELD_OUT_IP_DSCP = 0x6, 7034 MLX5_ACTION_IN_FIELD_OUT_TCP_FLAGS = 0x7, 7035 MLX5_ACTION_IN_FIELD_OUT_TCP_SPORT = 0x8, 7036 MLX5_ACTION_IN_FIELD_OUT_TCP_DPORT = 0x9, 7037 MLX5_ACTION_IN_FIELD_OUT_IP_TTL = 0xa, 7038 MLX5_ACTION_IN_FIELD_OUT_UDP_SPORT = 0xb, 7039 MLX5_ACTION_IN_FIELD_OUT_UDP_DPORT = 0xc, 7040 MLX5_ACTION_IN_FIELD_OUT_SIPV6_127_96 = 0xd, 7041 MLX5_ACTION_IN_FIELD_OUT_SIPV6_95_64 = 0xe, 7042 MLX5_ACTION_IN_FIELD_OUT_SIPV6_63_32 = 0xf, 7043 MLX5_ACTION_IN_FIELD_OUT_SIPV6_31_0 = 0x10, 7044 MLX5_ACTION_IN_FIELD_OUT_DIPV6_127_96 = 0x11, 7045 MLX5_ACTION_IN_FIELD_OUT_DIPV6_95_64 = 0x12, 7046 MLX5_ACTION_IN_FIELD_OUT_DIPV6_63_32 = 0x13, 7047 MLX5_ACTION_IN_FIELD_OUT_DIPV6_31_0 = 0x14, 7048 MLX5_ACTION_IN_FIELD_OUT_SIPV4 = 0x15, 7049 MLX5_ACTION_IN_FIELD_OUT_DIPV4 = 0x16, 7050 MLX5_ACTION_IN_FIELD_OUT_FIRST_VID = 0x17, 7051 MLX5_ACTION_IN_FIELD_OUT_IPV6_HOPLIMIT = 0x47, 7052 MLX5_ACTION_IN_FIELD_METADATA_REG_A = 0x49, 7053 MLX5_ACTION_IN_FIELD_METADATA_REG_B = 0x50, 7054 MLX5_ACTION_IN_FIELD_METADATA_REG_C_0 = 0x51, 7055 MLX5_ACTION_IN_FIELD_METADATA_REG_C_1 = 0x52, 7056 MLX5_ACTION_IN_FIELD_METADATA_REG_C_2 = 0x53, 7057 MLX5_ACTION_IN_FIELD_METADATA_REG_C_3 = 0x54, 7058 MLX5_ACTION_IN_FIELD_METADATA_REG_C_4 = 0x55, 7059 MLX5_ACTION_IN_FIELD_METADATA_REG_C_5 = 0x56, 7060 MLX5_ACTION_IN_FIELD_METADATA_REG_C_6 = 0x57, 7061 MLX5_ACTION_IN_FIELD_METADATA_REG_C_7 = 0x58, 7062 MLX5_ACTION_IN_FIELD_OUT_TCP_SEQ_NUM = 0x59, 7063 MLX5_ACTION_IN_FIELD_OUT_TCP_ACK_NUM = 0x5B, 7064 MLX5_ACTION_IN_FIELD_IPSEC_SYNDROME = 0x5D, 7065 MLX5_ACTION_IN_FIELD_OUT_EMD_47_32 = 0x6F, 7066 MLX5_ACTION_IN_FIELD_OUT_EMD_31_0 = 0x70, 7067 }; 7068 7069 struct mlx5_ifc_alloc_modify_header_context_out_bits { 7070 u8 status[0x8]; 7071 u8 reserved_at_8[0x18]; 7072 7073 u8 syndrome[0x20]; 7074 7075 u8 modify_header_id[0x20]; 7076 7077 u8 reserved_at_60[0x20]; 7078 }; 7079 7080 struct mlx5_ifc_alloc_modify_header_context_in_bits { 7081 u8 opcode[0x10]; 7082 u8 reserved_at_10[0x10]; 7083 7084 u8 reserved_at_20[0x10]; 7085 u8 op_mod[0x10]; 7086 7087 u8 reserved_at_40[0x20]; 7088 7089 u8 table_type[0x8]; 7090 u8 reserved_at_68[0x10]; 7091 u8 num_of_actions[0x8]; 7092 7093 union mlx5_ifc_set_add_copy_action_in_auto_bits actions[]; 7094 }; 7095 7096 struct mlx5_ifc_dealloc_modify_header_context_out_bits { 7097 u8 status[0x8]; 7098 u8 reserved_at_8[0x18]; 7099 7100 u8 syndrome[0x20]; 7101 7102 u8 reserved_at_40[0x40]; 7103 }; 7104 7105 struct mlx5_ifc_dealloc_modify_header_context_in_bits { 7106 u8 opcode[0x10]; 7107 u8 reserved_at_10[0x10]; 7108 7109 u8 reserved_at_20[0x10]; 7110 u8 op_mod[0x10]; 7111 7112 u8 modify_header_id[0x20]; 7113 7114 u8 reserved_at_60[0x20]; 7115 }; 7116 7117 struct mlx5_ifc_query_modify_header_context_in_bits { 7118 u8 opcode[0x10]; 7119 u8 uid[0x10]; 7120 7121 u8 reserved_at_20[0x10]; 7122 u8 op_mod[0x10]; 7123 7124 u8 modify_header_id[0x20]; 7125 7126 u8 reserved_at_60[0xa0]; 7127 }; 7128 7129 struct mlx5_ifc_query_dct_out_bits { 7130 u8 status[0x8]; 7131 u8 reserved_at_8[0x18]; 7132 7133 u8 syndrome[0x20]; 7134 7135 u8 reserved_at_40[0x40]; 7136 7137 struct mlx5_ifc_dctc_bits dct_context_entry; 7138 7139 u8 reserved_at_280[0x180]; 7140 }; 7141 7142 struct mlx5_ifc_query_dct_in_bits { 7143 u8 opcode[0x10]; 7144 u8 reserved_at_10[0x10]; 7145 7146 u8 reserved_at_20[0x10]; 7147 u8 op_mod[0x10]; 7148 7149 u8 reserved_at_40[0x8]; 7150 u8 dctn[0x18]; 7151 7152 u8 reserved_at_60[0x20]; 7153 }; 7154 7155 struct mlx5_ifc_query_cq_out_bits { 7156 u8 status[0x8]; 7157 u8 reserved_at_8[0x18]; 7158 7159 u8 syndrome[0x20]; 7160 7161 u8 reserved_at_40[0x40]; 7162 7163 struct mlx5_ifc_cqc_bits cq_context; 7164 7165 u8 reserved_at_280[0x600]; 7166 7167 u8 pas[][0x40]; 7168 }; 7169 7170 struct mlx5_ifc_query_cq_in_bits { 7171 u8 opcode[0x10]; 7172 u8 reserved_at_10[0x10]; 7173 7174 u8 reserved_at_20[0x10]; 7175 u8 op_mod[0x10]; 7176 7177 u8 reserved_at_40[0x8]; 7178 u8 cqn[0x18]; 7179 7180 u8 reserved_at_60[0x20]; 7181 }; 7182 7183 struct mlx5_ifc_query_cong_status_out_bits { 7184 u8 status[0x8]; 7185 u8 reserved_at_8[0x18]; 7186 7187 u8 syndrome[0x20]; 7188 7189 u8 reserved_at_40[0x20]; 7190 7191 u8 enable[0x1]; 7192 u8 tag_enable[0x1]; 7193 u8 reserved_at_62[0x1e]; 7194 }; 7195 7196 struct mlx5_ifc_query_cong_status_in_bits { 7197 u8 opcode[0x10]; 7198 u8 reserved_at_10[0x10]; 7199 7200 u8 reserved_at_20[0x10]; 7201 u8 op_mod[0x10]; 7202 7203 u8 reserved_at_40[0x18]; 7204 u8 priority[0x4]; 7205 u8 cong_protocol[0x4]; 7206 7207 u8 reserved_at_60[0x20]; 7208 }; 7209 7210 struct mlx5_ifc_query_cong_statistics_out_bits { 7211 u8 status[0x8]; 7212 u8 reserved_at_8[0x18]; 7213 7214 u8 syndrome[0x20]; 7215 7216 u8 reserved_at_40[0x40]; 7217 7218 u8 rp_cur_flows[0x20]; 7219 7220 u8 sum_flows[0x20]; 7221 7222 u8 rp_cnp_ignored_high[0x20]; 7223 7224 u8 rp_cnp_ignored_low[0x20]; 7225 7226 u8 rp_cnp_handled_high[0x20]; 7227 7228 u8 rp_cnp_handled_low[0x20]; 7229 7230 u8 reserved_at_140[0x100]; 7231 7232 u8 time_stamp_high[0x20]; 7233 7234 u8 time_stamp_low[0x20]; 7235 7236 u8 accumulators_period[0x20]; 7237 7238 u8 np_ecn_marked_roce_packets_high[0x20]; 7239 7240 u8 np_ecn_marked_roce_packets_low[0x20]; 7241 7242 u8 np_cnp_sent_high[0x20]; 7243 7244 u8 np_cnp_sent_low[0x20]; 7245 7246 u8 reserved_at_320[0x560]; 7247 }; 7248 7249 struct mlx5_ifc_query_cong_statistics_in_bits { 7250 u8 opcode[0x10]; 7251 u8 reserved_at_10[0x10]; 7252 7253 u8 reserved_at_20[0x10]; 7254 u8 op_mod[0x10]; 7255 7256 u8 clear[0x1]; 7257 u8 reserved_at_41[0x1f]; 7258 7259 u8 reserved_at_60[0x20]; 7260 }; 7261 7262 struct mlx5_ifc_query_cong_params_out_bits { 7263 u8 status[0x8]; 7264 u8 reserved_at_8[0x18]; 7265 7266 u8 syndrome[0x20]; 7267 7268 u8 reserved_at_40[0x40]; 7269 7270 union mlx5_ifc_cong_control_roce_ecn_auto_bits congestion_parameters; 7271 }; 7272 7273 struct mlx5_ifc_query_cong_params_in_bits { 7274 u8 opcode[0x10]; 7275 u8 reserved_at_10[0x10]; 7276 7277 u8 reserved_at_20[0x10]; 7278 u8 op_mod[0x10]; 7279 7280 u8 reserved_at_40[0x1c]; 7281 u8 cong_protocol[0x4]; 7282 7283 u8 reserved_at_60[0x20]; 7284 }; 7285 7286 struct mlx5_ifc_query_adapter_out_bits { 7287 u8 status[0x8]; 7288 u8 reserved_at_8[0x18]; 7289 7290 u8 syndrome[0x20]; 7291 7292 u8 reserved_at_40[0x40]; 7293 7294 struct mlx5_ifc_query_adapter_param_block_bits query_adapter_struct; 7295 }; 7296 7297 struct mlx5_ifc_query_adapter_in_bits { 7298 u8 opcode[0x10]; 7299 u8 reserved_at_10[0x10]; 7300 7301 u8 reserved_at_20[0x10]; 7302 u8 op_mod[0x10]; 7303 7304 u8 reserved_at_40[0x40]; 7305 }; 7306 7307 struct mlx5_ifc_qp_2rst_out_bits { 7308 u8 status[0x8]; 7309 u8 reserved_at_8[0x18]; 7310 7311 u8 syndrome[0x20]; 7312 7313 u8 reserved_at_40[0x40]; 7314 }; 7315 7316 struct mlx5_ifc_qp_2rst_in_bits { 7317 u8 opcode[0x10]; 7318 u8 uid[0x10]; 7319 7320 u8 reserved_at_20[0x10]; 7321 u8 op_mod[0x10]; 7322 7323 u8 reserved_at_40[0x8]; 7324 u8 qpn[0x18]; 7325 7326 u8 reserved_at_60[0x20]; 7327 }; 7328 7329 struct mlx5_ifc_qp_2err_out_bits { 7330 u8 status[0x8]; 7331 u8 reserved_at_8[0x18]; 7332 7333 u8 syndrome[0x20]; 7334 7335 u8 reserved_at_40[0x40]; 7336 }; 7337 7338 struct mlx5_ifc_qp_2err_in_bits { 7339 u8 opcode[0x10]; 7340 u8 uid[0x10]; 7341 7342 u8 reserved_at_20[0x10]; 7343 u8 op_mod[0x10]; 7344 7345 u8 reserved_at_40[0x8]; 7346 u8 qpn[0x18]; 7347 7348 u8 reserved_at_60[0x20]; 7349 }; 7350 7351 struct mlx5_ifc_page_fault_resume_out_bits { 7352 u8 status[0x8]; 7353 u8 reserved_at_8[0x18]; 7354 7355 u8 syndrome[0x20]; 7356 7357 u8 reserved_at_40[0x40]; 7358 }; 7359 7360 struct mlx5_ifc_page_fault_resume_in_bits { 7361 u8 opcode[0x10]; 7362 u8 reserved_at_10[0x10]; 7363 7364 u8 reserved_at_20[0x10]; 7365 u8 op_mod[0x10]; 7366 7367 u8 error[0x1]; 7368 u8 reserved_at_41[0x4]; 7369 u8 page_fault_type[0x3]; 7370 u8 wq_number[0x18]; 7371 7372 u8 reserved_at_60[0x8]; 7373 u8 token[0x18]; 7374 }; 7375 7376 struct mlx5_ifc_nop_out_bits { 7377 u8 status[0x8]; 7378 u8 reserved_at_8[0x18]; 7379 7380 u8 syndrome[0x20]; 7381 7382 u8 reserved_at_40[0x40]; 7383 }; 7384 7385 struct mlx5_ifc_nop_in_bits { 7386 u8 opcode[0x10]; 7387 u8 reserved_at_10[0x10]; 7388 7389 u8 reserved_at_20[0x10]; 7390 u8 op_mod[0x10]; 7391 7392 u8 reserved_at_40[0x40]; 7393 }; 7394 7395 struct mlx5_ifc_modify_vport_state_out_bits { 7396 u8 status[0x8]; 7397 u8 reserved_at_8[0x18]; 7398 7399 u8 syndrome[0x20]; 7400 7401 u8 reserved_at_40[0x40]; 7402 }; 7403 7404 struct mlx5_ifc_modify_vport_state_in_bits { 7405 u8 opcode[0x10]; 7406 u8 reserved_at_10[0x10]; 7407 7408 u8 reserved_at_20[0x10]; 7409 u8 op_mod[0x10]; 7410 7411 u8 other_vport[0x1]; 7412 u8 reserved_at_41[0xf]; 7413 u8 vport_number[0x10]; 7414 7415 u8 reserved_at_60[0x18]; 7416 u8 admin_state[0x4]; 7417 u8 reserved_at_7c[0x4]; 7418 }; 7419 7420 struct mlx5_ifc_modify_tis_out_bits { 7421 u8 status[0x8]; 7422 u8 reserved_at_8[0x18]; 7423 7424 u8 syndrome[0x20]; 7425 7426 u8 reserved_at_40[0x40]; 7427 }; 7428 7429 struct mlx5_ifc_modify_tis_bitmask_bits { 7430 u8 reserved_at_0[0x20]; 7431 7432 u8 reserved_at_20[0x1d]; 7433 u8 lag_tx_port_affinity[0x1]; 7434 u8 strict_lag_tx_port_affinity[0x1]; 7435 u8 prio[0x1]; 7436 }; 7437 7438 struct mlx5_ifc_modify_tis_in_bits { 7439 u8 opcode[0x10]; 7440 u8 uid[0x10]; 7441 7442 u8 reserved_at_20[0x10]; 7443 u8 op_mod[0x10]; 7444 7445 u8 reserved_at_40[0x8]; 7446 u8 tisn[0x18]; 7447 7448 u8 reserved_at_60[0x20]; 7449 7450 struct mlx5_ifc_modify_tis_bitmask_bits bitmask; 7451 7452 u8 reserved_at_c0[0x40]; 7453 7454 struct mlx5_ifc_tisc_bits ctx; 7455 }; 7456 7457 struct mlx5_ifc_modify_tir_bitmask_bits { 7458 u8 reserved_at_0[0x20]; 7459 7460 u8 reserved_at_20[0x1b]; 7461 u8 self_lb_en[0x1]; 7462 u8 reserved_at_3c[0x1]; 7463 u8 hash[0x1]; 7464 u8 reserved_at_3e[0x1]; 7465 u8 packet_merge[0x1]; 7466 }; 7467 7468 struct mlx5_ifc_modify_tir_out_bits { 7469 u8 status[0x8]; 7470 u8 reserved_at_8[0x18]; 7471 7472 u8 syndrome[0x20]; 7473 7474 u8 reserved_at_40[0x40]; 7475 }; 7476 7477 struct mlx5_ifc_modify_tir_in_bits { 7478 u8 opcode[0x10]; 7479 u8 uid[0x10]; 7480 7481 u8 reserved_at_20[0x10]; 7482 u8 op_mod[0x10]; 7483 7484 u8 reserved_at_40[0x8]; 7485 u8 tirn[0x18]; 7486 7487 u8 reserved_at_60[0x20]; 7488 7489 struct mlx5_ifc_modify_tir_bitmask_bits bitmask; 7490 7491 u8 reserved_at_c0[0x40]; 7492 7493 struct mlx5_ifc_tirc_bits ctx; 7494 }; 7495 7496 struct mlx5_ifc_modify_sq_out_bits { 7497 u8 status[0x8]; 7498 u8 reserved_at_8[0x18]; 7499 7500 u8 syndrome[0x20]; 7501 7502 u8 reserved_at_40[0x40]; 7503 }; 7504 7505 struct mlx5_ifc_modify_sq_in_bits { 7506 u8 opcode[0x10]; 7507 u8 uid[0x10]; 7508 7509 u8 reserved_at_20[0x10]; 7510 u8 op_mod[0x10]; 7511 7512 u8 sq_state[0x4]; 7513 u8 reserved_at_44[0x4]; 7514 u8 sqn[0x18]; 7515 7516 u8 reserved_at_60[0x20]; 7517 7518 u8 modify_bitmask[0x40]; 7519 7520 u8 reserved_at_c0[0x40]; 7521 7522 struct mlx5_ifc_sqc_bits ctx; 7523 }; 7524 7525 struct mlx5_ifc_modify_scheduling_element_out_bits { 7526 u8 status[0x8]; 7527 u8 reserved_at_8[0x18]; 7528 7529 u8 syndrome[0x20]; 7530 7531 u8 reserved_at_40[0x1c0]; 7532 }; 7533 7534 enum { 7535 MODIFY_SCHEDULING_ELEMENT_IN_MODIFY_BITMASK_BW_SHARE = 0x1, 7536 MODIFY_SCHEDULING_ELEMENT_IN_MODIFY_BITMASK_MAX_AVERAGE_BW = 0x2, 7537 }; 7538 7539 struct mlx5_ifc_modify_scheduling_element_in_bits { 7540 u8 opcode[0x10]; 7541 u8 reserved_at_10[0x10]; 7542 7543 u8 reserved_at_20[0x10]; 7544 u8 op_mod[0x10]; 7545 7546 u8 scheduling_hierarchy[0x8]; 7547 u8 reserved_at_48[0x18]; 7548 7549 u8 scheduling_element_id[0x20]; 7550 7551 u8 reserved_at_80[0x20]; 7552 7553 u8 modify_bitmask[0x20]; 7554 7555 u8 reserved_at_c0[0x40]; 7556 7557 struct mlx5_ifc_scheduling_context_bits scheduling_context; 7558 7559 u8 reserved_at_300[0x100]; 7560 }; 7561 7562 struct mlx5_ifc_modify_rqt_out_bits { 7563 u8 status[0x8]; 7564 u8 reserved_at_8[0x18]; 7565 7566 u8 syndrome[0x20]; 7567 7568 u8 reserved_at_40[0x40]; 7569 }; 7570 7571 struct mlx5_ifc_rqt_bitmask_bits { 7572 u8 reserved_at_0[0x20]; 7573 7574 u8 reserved_at_20[0x1f]; 7575 u8 rqn_list[0x1]; 7576 }; 7577 7578 struct mlx5_ifc_modify_rqt_in_bits { 7579 u8 opcode[0x10]; 7580 u8 uid[0x10]; 7581 7582 u8 reserved_at_20[0x10]; 7583 u8 op_mod[0x10]; 7584 7585 u8 reserved_at_40[0x8]; 7586 u8 rqtn[0x18]; 7587 7588 u8 reserved_at_60[0x20]; 7589 7590 struct mlx5_ifc_rqt_bitmask_bits bitmask; 7591 7592 u8 reserved_at_c0[0x40]; 7593 7594 struct mlx5_ifc_rqtc_bits ctx; 7595 }; 7596 7597 struct mlx5_ifc_modify_rq_out_bits { 7598 u8 status[0x8]; 7599 u8 reserved_at_8[0x18]; 7600 7601 u8 syndrome[0x20]; 7602 7603 u8 reserved_at_40[0x40]; 7604 }; 7605 7606 enum { 7607 MLX5_MODIFY_RQ_IN_MODIFY_BITMASK_VSD = 1ULL << 1, 7608 MLX5_MODIFY_RQ_IN_MODIFY_BITMASK_SCATTER_FCS = 1ULL << 2, 7609 MLX5_MODIFY_RQ_IN_MODIFY_BITMASK_RQ_COUNTER_SET_ID = 1ULL << 3, 7610 }; 7611 7612 struct mlx5_ifc_modify_rq_in_bits { 7613 u8 opcode[0x10]; 7614 u8 uid[0x10]; 7615 7616 u8 reserved_at_20[0x10]; 7617 u8 op_mod[0x10]; 7618 7619 u8 rq_state[0x4]; 7620 u8 reserved_at_44[0x4]; 7621 u8 rqn[0x18]; 7622 7623 u8 reserved_at_60[0x20]; 7624 7625 u8 modify_bitmask[0x40]; 7626 7627 u8 reserved_at_c0[0x40]; 7628 7629 struct mlx5_ifc_rqc_bits ctx; 7630 }; 7631 7632 struct mlx5_ifc_modify_rmp_out_bits { 7633 u8 status[0x8]; 7634 u8 reserved_at_8[0x18]; 7635 7636 u8 syndrome[0x20]; 7637 7638 u8 reserved_at_40[0x40]; 7639 }; 7640 7641 struct mlx5_ifc_rmp_bitmask_bits { 7642 u8 reserved_at_0[0x20]; 7643 7644 u8 reserved_at_20[0x1f]; 7645 u8 lwm[0x1]; 7646 }; 7647 7648 struct mlx5_ifc_modify_rmp_in_bits { 7649 u8 opcode[0x10]; 7650 u8 uid[0x10]; 7651 7652 u8 reserved_at_20[0x10]; 7653 u8 op_mod[0x10]; 7654 7655 u8 rmp_state[0x4]; 7656 u8 reserved_at_44[0x4]; 7657 u8 rmpn[0x18]; 7658 7659 u8 reserved_at_60[0x20]; 7660 7661 struct mlx5_ifc_rmp_bitmask_bits bitmask; 7662 7663 u8 reserved_at_c0[0x40]; 7664 7665 struct mlx5_ifc_rmpc_bits ctx; 7666 }; 7667 7668 struct mlx5_ifc_modify_nic_vport_context_out_bits { 7669 u8 status[0x8]; 7670 u8 reserved_at_8[0x18]; 7671 7672 u8 syndrome[0x20]; 7673 7674 u8 reserved_at_40[0x40]; 7675 }; 7676 7677 struct mlx5_ifc_modify_nic_vport_field_select_bits { 7678 u8 reserved_at_0[0x12]; 7679 u8 affiliation[0x1]; 7680 u8 reserved_at_13[0x1]; 7681 u8 disable_uc_local_lb[0x1]; 7682 u8 disable_mc_local_lb[0x1]; 7683 u8 node_guid[0x1]; 7684 u8 port_guid[0x1]; 7685 u8 min_inline[0x1]; 7686 u8 mtu[0x1]; 7687 u8 change_event[0x1]; 7688 u8 promisc[0x1]; 7689 u8 permanent_address[0x1]; 7690 u8 addresses_list[0x1]; 7691 u8 roce_en[0x1]; 7692 u8 reserved_at_1f[0x1]; 7693 }; 7694 7695 struct mlx5_ifc_modify_nic_vport_context_in_bits { 7696 u8 opcode[0x10]; 7697 u8 reserved_at_10[0x10]; 7698 7699 u8 reserved_at_20[0x10]; 7700 u8 op_mod[0x10]; 7701 7702 u8 other_vport[0x1]; 7703 u8 reserved_at_41[0xf]; 7704 u8 vport_number[0x10]; 7705 7706 struct mlx5_ifc_modify_nic_vport_field_select_bits field_select; 7707 7708 u8 reserved_at_80[0x780]; 7709 7710 struct mlx5_ifc_nic_vport_context_bits nic_vport_context; 7711 }; 7712 7713 struct mlx5_ifc_modify_hca_vport_context_out_bits { 7714 u8 status[0x8]; 7715 u8 reserved_at_8[0x18]; 7716 7717 u8 syndrome[0x20]; 7718 7719 u8 reserved_at_40[0x40]; 7720 }; 7721 7722 struct mlx5_ifc_modify_hca_vport_context_in_bits { 7723 u8 opcode[0x10]; 7724 u8 reserved_at_10[0x10]; 7725 7726 u8 reserved_at_20[0x10]; 7727 u8 op_mod[0x10]; 7728 7729 u8 other_vport[0x1]; 7730 u8 reserved_at_41[0xb]; 7731 u8 port_num[0x4]; 7732 u8 vport_number[0x10]; 7733 7734 u8 reserved_at_60[0x20]; 7735 7736 struct mlx5_ifc_hca_vport_context_bits hca_vport_context; 7737 }; 7738 7739 struct mlx5_ifc_modify_cq_out_bits { 7740 u8 status[0x8]; 7741 u8 reserved_at_8[0x18]; 7742 7743 u8 syndrome[0x20]; 7744 7745 u8 reserved_at_40[0x40]; 7746 }; 7747 7748 enum { 7749 MLX5_MODIFY_CQ_IN_OP_MOD_MODIFY_CQ = 0x0, 7750 MLX5_MODIFY_CQ_IN_OP_MOD_RESIZE_CQ = 0x1, 7751 }; 7752 7753 struct mlx5_ifc_modify_cq_in_bits { 7754 u8 opcode[0x10]; 7755 u8 uid[0x10]; 7756 7757 u8 reserved_at_20[0x10]; 7758 u8 op_mod[0x10]; 7759 7760 u8 reserved_at_40[0x8]; 7761 u8 cqn[0x18]; 7762 7763 union mlx5_ifc_modify_field_select_resize_field_select_auto_bits modify_field_select_resize_field_select; 7764 7765 struct mlx5_ifc_cqc_bits cq_context; 7766 7767 u8 reserved_at_280[0x60]; 7768 7769 u8 cq_umem_valid[0x1]; 7770 u8 reserved_at_2e1[0x1f]; 7771 7772 u8 reserved_at_300[0x580]; 7773 7774 u8 pas[][0x40]; 7775 }; 7776 7777 struct mlx5_ifc_modify_cong_status_out_bits { 7778 u8 status[0x8]; 7779 u8 reserved_at_8[0x18]; 7780 7781 u8 syndrome[0x20]; 7782 7783 u8 reserved_at_40[0x40]; 7784 }; 7785 7786 struct mlx5_ifc_modify_cong_status_in_bits { 7787 u8 opcode[0x10]; 7788 u8 reserved_at_10[0x10]; 7789 7790 u8 reserved_at_20[0x10]; 7791 u8 op_mod[0x10]; 7792 7793 u8 reserved_at_40[0x18]; 7794 u8 priority[0x4]; 7795 u8 cong_protocol[0x4]; 7796 7797 u8 enable[0x1]; 7798 u8 tag_enable[0x1]; 7799 u8 reserved_at_62[0x1e]; 7800 }; 7801 7802 struct mlx5_ifc_modify_cong_params_out_bits { 7803 u8 status[0x8]; 7804 u8 reserved_at_8[0x18]; 7805 7806 u8 syndrome[0x20]; 7807 7808 u8 reserved_at_40[0x40]; 7809 }; 7810 7811 struct mlx5_ifc_modify_cong_params_in_bits { 7812 u8 opcode[0x10]; 7813 u8 reserved_at_10[0x10]; 7814 7815 u8 reserved_at_20[0x10]; 7816 u8 op_mod[0x10]; 7817 7818 u8 reserved_at_40[0x1c]; 7819 u8 cong_protocol[0x4]; 7820 7821 union mlx5_ifc_field_select_802_1_r_roce_auto_bits field_select; 7822 7823 u8 reserved_at_80[0x80]; 7824 7825 union mlx5_ifc_cong_control_roce_ecn_auto_bits congestion_parameters; 7826 }; 7827 7828 struct mlx5_ifc_manage_pages_out_bits { 7829 u8 status[0x8]; 7830 u8 reserved_at_8[0x18]; 7831 7832 u8 syndrome[0x20]; 7833 7834 u8 output_num_entries[0x20]; 7835 7836 u8 reserved_at_60[0x20]; 7837 7838 u8 pas[][0x40]; 7839 }; 7840 7841 enum { 7842 MLX5_MANAGE_PAGES_IN_OP_MOD_ALLOCATION_FAIL = 0x0, 7843 MLX5_MANAGE_PAGES_IN_OP_MOD_ALLOCATION_SUCCESS = 0x1, 7844 MLX5_MANAGE_PAGES_IN_OP_MOD_HCA_RETURN_PAGES = 0x2, 7845 }; 7846 7847 struct mlx5_ifc_manage_pages_in_bits { 7848 u8 opcode[0x10]; 7849 u8 reserved_at_10[0x10]; 7850 7851 u8 reserved_at_20[0x10]; 7852 u8 op_mod[0x10]; 7853 7854 u8 embedded_cpu_function[0x1]; 7855 u8 reserved_at_41[0xf]; 7856 u8 function_id[0x10]; 7857 7858 u8 input_num_entries[0x20]; 7859 7860 u8 pas[][0x40]; 7861 }; 7862 7863 struct mlx5_ifc_mad_ifc_out_bits { 7864 u8 status[0x8]; 7865 u8 reserved_at_8[0x18]; 7866 7867 u8 syndrome[0x20]; 7868 7869 u8 reserved_at_40[0x40]; 7870 7871 u8 response_mad_packet[256][0x8]; 7872 }; 7873 7874 struct mlx5_ifc_mad_ifc_in_bits { 7875 u8 opcode[0x10]; 7876 u8 reserved_at_10[0x10]; 7877 7878 u8 reserved_at_20[0x10]; 7879 u8 op_mod[0x10]; 7880 7881 u8 remote_lid[0x10]; 7882 u8 plane_index[0x8]; 7883 u8 port[0x8]; 7884 7885 u8 reserved_at_60[0x20]; 7886 7887 u8 mad[256][0x8]; 7888 }; 7889 7890 struct mlx5_ifc_init_hca_out_bits { 7891 u8 status[0x8]; 7892 u8 reserved_at_8[0x18]; 7893 7894 u8 syndrome[0x20]; 7895 7896 u8 reserved_at_40[0x40]; 7897 }; 7898 7899 struct mlx5_ifc_init_hca_in_bits { 7900 u8 opcode[0x10]; 7901 u8 reserved_at_10[0x10]; 7902 7903 u8 reserved_at_20[0x10]; 7904 u8 op_mod[0x10]; 7905 7906 u8 reserved_at_40[0x20]; 7907 7908 u8 reserved_at_60[0x2]; 7909 u8 sw_vhca_id[0xe]; 7910 u8 reserved_at_70[0x10]; 7911 7912 u8 sw_owner_id[4][0x20]; 7913 }; 7914 7915 struct mlx5_ifc_init2rtr_qp_out_bits { 7916 u8 status[0x8]; 7917 u8 reserved_at_8[0x18]; 7918 7919 u8 syndrome[0x20]; 7920 7921 u8 reserved_at_40[0x20]; 7922 u8 ece[0x20]; 7923 }; 7924 7925 struct mlx5_ifc_init2rtr_qp_in_bits { 7926 u8 opcode[0x10]; 7927 u8 uid[0x10]; 7928 7929 u8 reserved_at_20[0x10]; 7930 u8 op_mod[0x10]; 7931 7932 u8 reserved_at_40[0x8]; 7933 u8 qpn[0x18]; 7934 7935 u8 reserved_at_60[0x20]; 7936 7937 u8 opt_param_mask[0x20]; 7938 7939 u8 ece[0x20]; 7940 7941 struct mlx5_ifc_qpc_bits qpc; 7942 7943 u8 reserved_at_800[0x80]; 7944 }; 7945 7946 struct mlx5_ifc_init2init_qp_out_bits { 7947 u8 status[0x8]; 7948 u8 reserved_at_8[0x18]; 7949 7950 u8 syndrome[0x20]; 7951 7952 u8 reserved_at_40[0x20]; 7953 u8 ece[0x20]; 7954 }; 7955 7956 struct mlx5_ifc_init2init_qp_in_bits { 7957 u8 opcode[0x10]; 7958 u8 uid[0x10]; 7959 7960 u8 reserved_at_20[0x10]; 7961 u8 op_mod[0x10]; 7962 7963 u8 reserved_at_40[0x8]; 7964 u8 qpn[0x18]; 7965 7966 u8 reserved_at_60[0x20]; 7967 7968 u8 opt_param_mask[0x20]; 7969 7970 u8 ece[0x20]; 7971 7972 struct mlx5_ifc_qpc_bits qpc; 7973 7974 u8 reserved_at_800[0x80]; 7975 }; 7976 7977 struct mlx5_ifc_get_dropped_packet_log_out_bits { 7978 u8 status[0x8]; 7979 u8 reserved_at_8[0x18]; 7980 7981 u8 syndrome[0x20]; 7982 7983 u8 reserved_at_40[0x40]; 7984 7985 u8 packet_headers_log[128][0x8]; 7986 7987 u8 packet_syndrome[64][0x8]; 7988 }; 7989 7990 struct mlx5_ifc_get_dropped_packet_log_in_bits { 7991 u8 opcode[0x10]; 7992 u8 reserved_at_10[0x10]; 7993 7994 u8 reserved_at_20[0x10]; 7995 u8 op_mod[0x10]; 7996 7997 u8 reserved_at_40[0x40]; 7998 }; 7999 8000 struct mlx5_ifc_gen_eqe_in_bits { 8001 u8 opcode[0x10]; 8002 u8 reserved_at_10[0x10]; 8003 8004 u8 reserved_at_20[0x10]; 8005 u8 op_mod[0x10]; 8006 8007 u8 reserved_at_40[0x18]; 8008 u8 eq_number[0x8]; 8009 8010 u8 reserved_at_60[0x20]; 8011 8012 u8 eqe[64][0x8]; 8013 }; 8014 8015 struct mlx5_ifc_gen_eq_out_bits { 8016 u8 status[0x8]; 8017 u8 reserved_at_8[0x18]; 8018 8019 u8 syndrome[0x20]; 8020 8021 u8 reserved_at_40[0x40]; 8022 }; 8023 8024 struct mlx5_ifc_enable_hca_out_bits { 8025 u8 status[0x8]; 8026 u8 reserved_at_8[0x18]; 8027 8028 u8 syndrome[0x20]; 8029 8030 u8 reserved_at_40[0x20]; 8031 }; 8032 8033 struct mlx5_ifc_enable_hca_in_bits { 8034 u8 opcode[0x10]; 8035 u8 reserved_at_10[0x10]; 8036 8037 u8 reserved_at_20[0x10]; 8038 u8 op_mod[0x10]; 8039 8040 u8 embedded_cpu_function[0x1]; 8041 u8 reserved_at_41[0xf]; 8042 u8 function_id[0x10]; 8043 8044 u8 reserved_at_60[0x20]; 8045 }; 8046 8047 struct mlx5_ifc_drain_dct_out_bits { 8048 u8 status[0x8]; 8049 u8 reserved_at_8[0x18]; 8050 8051 u8 syndrome[0x20]; 8052 8053 u8 reserved_at_40[0x40]; 8054 }; 8055 8056 struct mlx5_ifc_drain_dct_in_bits { 8057 u8 opcode[0x10]; 8058 u8 uid[0x10]; 8059 8060 u8 reserved_at_20[0x10]; 8061 u8 op_mod[0x10]; 8062 8063 u8 reserved_at_40[0x8]; 8064 u8 dctn[0x18]; 8065 8066 u8 reserved_at_60[0x20]; 8067 }; 8068 8069 struct mlx5_ifc_disable_hca_out_bits { 8070 u8 status[0x8]; 8071 u8 reserved_at_8[0x18]; 8072 8073 u8 syndrome[0x20]; 8074 8075 u8 reserved_at_40[0x20]; 8076 }; 8077 8078 struct mlx5_ifc_disable_hca_in_bits { 8079 u8 opcode[0x10]; 8080 u8 reserved_at_10[0x10]; 8081 8082 u8 reserved_at_20[0x10]; 8083 u8 op_mod[0x10]; 8084 8085 u8 embedded_cpu_function[0x1]; 8086 u8 reserved_at_41[0xf]; 8087 u8 function_id[0x10]; 8088 8089 u8 reserved_at_60[0x20]; 8090 }; 8091 8092 struct mlx5_ifc_detach_from_mcg_out_bits { 8093 u8 status[0x8]; 8094 u8 reserved_at_8[0x18]; 8095 8096 u8 syndrome[0x20]; 8097 8098 u8 reserved_at_40[0x40]; 8099 }; 8100 8101 struct mlx5_ifc_detach_from_mcg_in_bits { 8102 u8 opcode[0x10]; 8103 u8 uid[0x10]; 8104 8105 u8 reserved_at_20[0x10]; 8106 u8 op_mod[0x10]; 8107 8108 u8 reserved_at_40[0x8]; 8109 u8 qpn[0x18]; 8110 8111 u8 reserved_at_60[0x20]; 8112 8113 u8 multicast_gid[16][0x8]; 8114 }; 8115 8116 struct mlx5_ifc_destroy_xrq_out_bits { 8117 u8 status[0x8]; 8118 u8 reserved_at_8[0x18]; 8119 8120 u8 syndrome[0x20]; 8121 8122 u8 reserved_at_40[0x40]; 8123 }; 8124 8125 struct mlx5_ifc_destroy_xrq_in_bits { 8126 u8 opcode[0x10]; 8127 u8 uid[0x10]; 8128 8129 u8 reserved_at_20[0x10]; 8130 u8 op_mod[0x10]; 8131 8132 u8 reserved_at_40[0x8]; 8133 u8 xrqn[0x18]; 8134 8135 u8 reserved_at_60[0x20]; 8136 }; 8137 8138 struct mlx5_ifc_destroy_xrc_srq_out_bits { 8139 u8 status[0x8]; 8140 u8 reserved_at_8[0x18]; 8141 8142 u8 syndrome[0x20]; 8143 8144 u8 reserved_at_40[0x40]; 8145 }; 8146 8147 struct mlx5_ifc_destroy_xrc_srq_in_bits { 8148 u8 opcode[0x10]; 8149 u8 uid[0x10]; 8150 8151 u8 reserved_at_20[0x10]; 8152 u8 op_mod[0x10]; 8153 8154 u8 reserved_at_40[0x8]; 8155 u8 xrc_srqn[0x18]; 8156 8157 u8 reserved_at_60[0x20]; 8158 }; 8159 8160 struct mlx5_ifc_destroy_tis_out_bits { 8161 u8 status[0x8]; 8162 u8 reserved_at_8[0x18]; 8163 8164 u8 syndrome[0x20]; 8165 8166 u8 reserved_at_40[0x40]; 8167 }; 8168 8169 struct mlx5_ifc_destroy_tis_in_bits { 8170 u8 opcode[0x10]; 8171 u8 uid[0x10]; 8172 8173 u8 reserved_at_20[0x10]; 8174 u8 op_mod[0x10]; 8175 8176 u8 reserved_at_40[0x8]; 8177 u8 tisn[0x18]; 8178 8179 u8 reserved_at_60[0x20]; 8180 }; 8181 8182 struct mlx5_ifc_destroy_tir_out_bits { 8183 u8 status[0x8]; 8184 u8 reserved_at_8[0x18]; 8185 8186 u8 syndrome[0x20]; 8187 8188 u8 reserved_at_40[0x40]; 8189 }; 8190 8191 struct mlx5_ifc_destroy_tir_in_bits { 8192 u8 opcode[0x10]; 8193 u8 uid[0x10]; 8194 8195 u8 reserved_at_20[0x10]; 8196 u8 op_mod[0x10]; 8197 8198 u8 reserved_at_40[0x8]; 8199 u8 tirn[0x18]; 8200 8201 u8 reserved_at_60[0x20]; 8202 }; 8203 8204 struct mlx5_ifc_destroy_srq_out_bits { 8205 u8 status[0x8]; 8206 u8 reserved_at_8[0x18]; 8207 8208 u8 syndrome[0x20]; 8209 8210 u8 reserved_at_40[0x40]; 8211 }; 8212 8213 struct mlx5_ifc_destroy_srq_in_bits { 8214 u8 opcode[0x10]; 8215 u8 uid[0x10]; 8216 8217 u8 reserved_at_20[0x10]; 8218 u8 op_mod[0x10]; 8219 8220 u8 reserved_at_40[0x8]; 8221 u8 srqn[0x18]; 8222 8223 u8 reserved_at_60[0x20]; 8224 }; 8225 8226 struct mlx5_ifc_destroy_sq_out_bits { 8227 u8 status[0x8]; 8228 u8 reserved_at_8[0x18]; 8229 8230 u8 syndrome[0x20]; 8231 8232 u8 reserved_at_40[0x40]; 8233 }; 8234 8235 struct mlx5_ifc_destroy_sq_in_bits { 8236 u8 opcode[0x10]; 8237 u8 uid[0x10]; 8238 8239 u8 reserved_at_20[0x10]; 8240 u8 op_mod[0x10]; 8241 8242 u8 reserved_at_40[0x8]; 8243 u8 sqn[0x18]; 8244 8245 u8 reserved_at_60[0x20]; 8246 }; 8247 8248 struct mlx5_ifc_destroy_scheduling_element_out_bits { 8249 u8 status[0x8]; 8250 u8 reserved_at_8[0x18]; 8251 8252 u8 syndrome[0x20]; 8253 8254 u8 reserved_at_40[0x1c0]; 8255 }; 8256 8257 struct mlx5_ifc_destroy_scheduling_element_in_bits { 8258 u8 opcode[0x10]; 8259 u8 reserved_at_10[0x10]; 8260 8261 u8 reserved_at_20[0x10]; 8262 u8 op_mod[0x10]; 8263 8264 u8 scheduling_hierarchy[0x8]; 8265 u8 reserved_at_48[0x18]; 8266 8267 u8 scheduling_element_id[0x20]; 8268 8269 u8 reserved_at_80[0x180]; 8270 }; 8271 8272 struct mlx5_ifc_destroy_rqt_out_bits { 8273 u8 status[0x8]; 8274 u8 reserved_at_8[0x18]; 8275 8276 u8 syndrome[0x20]; 8277 8278 u8 reserved_at_40[0x40]; 8279 }; 8280 8281 struct mlx5_ifc_destroy_rqt_in_bits { 8282 u8 opcode[0x10]; 8283 u8 uid[0x10]; 8284 8285 u8 reserved_at_20[0x10]; 8286 u8 op_mod[0x10]; 8287 8288 u8 reserved_at_40[0x8]; 8289 u8 rqtn[0x18]; 8290 8291 u8 reserved_at_60[0x20]; 8292 }; 8293 8294 struct mlx5_ifc_destroy_rq_out_bits { 8295 u8 status[0x8]; 8296 u8 reserved_at_8[0x18]; 8297 8298 u8 syndrome[0x20]; 8299 8300 u8 reserved_at_40[0x40]; 8301 }; 8302 8303 struct mlx5_ifc_destroy_rq_in_bits { 8304 u8 opcode[0x10]; 8305 u8 uid[0x10]; 8306 8307 u8 reserved_at_20[0x10]; 8308 u8 op_mod[0x10]; 8309 8310 u8 reserved_at_40[0x8]; 8311 u8 rqn[0x18]; 8312 8313 u8 reserved_at_60[0x20]; 8314 }; 8315 8316 struct mlx5_ifc_set_delay_drop_params_in_bits { 8317 u8 opcode[0x10]; 8318 u8 reserved_at_10[0x10]; 8319 8320 u8 reserved_at_20[0x10]; 8321 u8 op_mod[0x10]; 8322 8323 u8 reserved_at_40[0x20]; 8324 8325 u8 reserved_at_60[0x10]; 8326 u8 delay_drop_timeout[0x10]; 8327 }; 8328 8329 struct mlx5_ifc_set_delay_drop_params_out_bits { 8330 u8 status[0x8]; 8331 u8 reserved_at_8[0x18]; 8332 8333 u8 syndrome[0x20]; 8334 8335 u8 reserved_at_40[0x40]; 8336 }; 8337 8338 struct mlx5_ifc_destroy_rmp_out_bits { 8339 u8 status[0x8]; 8340 u8 reserved_at_8[0x18]; 8341 8342 u8 syndrome[0x20]; 8343 8344 u8 reserved_at_40[0x40]; 8345 }; 8346 8347 struct mlx5_ifc_destroy_rmp_in_bits { 8348 u8 opcode[0x10]; 8349 u8 uid[0x10]; 8350 8351 u8 reserved_at_20[0x10]; 8352 u8 op_mod[0x10]; 8353 8354 u8 reserved_at_40[0x8]; 8355 u8 rmpn[0x18]; 8356 8357 u8 reserved_at_60[0x20]; 8358 }; 8359 8360 struct mlx5_ifc_destroy_qp_out_bits { 8361 u8 status[0x8]; 8362 u8 reserved_at_8[0x18]; 8363 8364 u8 syndrome[0x20]; 8365 8366 u8 reserved_at_40[0x40]; 8367 }; 8368 8369 struct mlx5_ifc_destroy_qp_in_bits { 8370 u8 opcode[0x10]; 8371 u8 uid[0x10]; 8372 8373 u8 reserved_at_20[0x10]; 8374 u8 op_mod[0x10]; 8375 8376 u8 reserved_at_40[0x8]; 8377 u8 qpn[0x18]; 8378 8379 u8 reserved_at_60[0x20]; 8380 }; 8381 8382 struct mlx5_ifc_destroy_psv_out_bits { 8383 u8 status[0x8]; 8384 u8 reserved_at_8[0x18]; 8385 8386 u8 syndrome[0x20]; 8387 8388 u8 reserved_at_40[0x40]; 8389 }; 8390 8391 struct mlx5_ifc_destroy_psv_in_bits { 8392 u8 opcode[0x10]; 8393 u8 reserved_at_10[0x10]; 8394 8395 u8 reserved_at_20[0x10]; 8396 u8 op_mod[0x10]; 8397 8398 u8 reserved_at_40[0x8]; 8399 u8 psvn[0x18]; 8400 8401 u8 reserved_at_60[0x20]; 8402 }; 8403 8404 struct mlx5_ifc_destroy_mkey_out_bits { 8405 u8 status[0x8]; 8406 u8 reserved_at_8[0x18]; 8407 8408 u8 syndrome[0x20]; 8409 8410 u8 reserved_at_40[0x40]; 8411 }; 8412 8413 struct mlx5_ifc_destroy_mkey_in_bits { 8414 u8 opcode[0x10]; 8415 u8 uid[0x10]; 8416 8417 u8 reserved_at_20[0x10]; 8418 u8 op_mod[0x10]; 8419 8420 u8 reserved_at_40[0x8]; 8421 u8 mkey_index[0x18]; 8422 8423 u8 reserved_at_60[0x20]; 8424 }; 8425 8426 struct mlx5_ifc_destroy_flow_table_out_bits { 8427 u8 status[0x8]; 8428 u8 reserved_at_8[0x18]; 8429 8430 u8 syndrome[0x20]; 8431 8432 u8 reserved_at_40[0x40]; 8433 }; 8434 8435 struct mlx5_ifc_destroy_flow_table_in_bits { 8436 u8 opcode[0x10]; 8437 u8 reserved_at_10[0x10]; 8438 8439 u8 reserved_at_20[0x10]; 8440 u8 op_mod[0x10]; 8441 8442 u8 other_vport[0x1]; 8443 u8 reserved_at_41[0xf]; 8444 u8 vport_number[0x10]; 8445 8446 u8 reserved_at_60[0x20]; 8447 8448 u8 table_type[0x8]; 8449 u8 reserved_at_88[0x18]; 8450 8451 u8 reserved_at_a0[0x8]; 8452 u8 table_id[0x18]; 8453 8454 u8 reserved_at_c0[0x140]; 8455 }; 8456 8457 struct mlx5_ifc_destroy_flow_group_out_bits { 8458 u8 status[0x8]; 8459 u8 reserved_at_8[0x18]; 8460 8461 u8 syndrome[0x20]; 8462 8463 u8 reserved_at_40[0x40]; 8464 }; 8465 8466 struct mlx5_ifc_destroy_flow_group_in_bits { 8467 u8 opcode[0x10]; 8468 u8 reserved_at_10[0x10]; 8469 8470 u8 reserved_at_20[0x10]; 8471 u8 op_mod[0x10]; 8472 8473 u8 other_vport[0x1]; 8474 u8 reserved_at_41[0xf]; 8475 u8 vport_number[0x10]; 8476 8477 u8 reserved_at_60[0x20]; 8478 8479 u8 table_type[0x8]; 8480 u8 reserved_at_88[0x18]; 8481 8482 u8 reserved_at_a0[0x8]; 8483 u8 table_id[0x18]; 8484 8485 u8 group_id[0x20]; 8486 8487 u8 reserved_at_e0[0x120]; 8488 }; 8489 8490 struct mlx5_ifc_destroy_eq_out_bits { 8491 u8 status[0x8]; 8492 u8 reserved_at_8[0x18]; 8493 8494 u8 syndrome[0x20]; 8495 8496 u8 reserved_at_40[0x40]; 8497 }; 8498 8499 struct mlx5_ifc_destroy_eq_in_bits { 8500 u8 opcode[0x10]; 8501 u8 reserved_at_10[0x10]; 8502 8503 u8 reserved_at_20[0x10]; 8504 u8 op_mod[0x10]; 8505 8506 u8 reserved_at_40[0x18]; 8507 u8 eq_number[0x8]; 8508 8509 u8 reserved_at_60[0x20]; 8510 }; 8511 8512 struct mlx5_ifc_destroy_dct_out_bits { 8513 u8 status[0x8]; 8514 u8 reserved_at_8[0x18]; 8515 8516 u8 syndrome[0x20]; 8517 8518 u8 reserved_at_40[0x40]; 8519 }; 8520 8521 struct mlx5_ifc_destroy_dct_in_bits { 8522 u8 opcode[0x10]; 8523 u8 uid[0x10]; 8524 8525 u8 reserved_at_20[0x10]; 8526 u8 op_mod[0x10]; 8527 8528 u8 reserved_at_40[0x8]; 8529 u8 dctn[0x18]; 8530 8531 u8 reserved_at_60[0x20]; 8532 }; 8533 8534 struct mlx5_ifc_destroy_cq_out_bits { 8535 u8 status[0x8]; 8536 u8 reserved_at_8[0x18]; 8537 8538 u8 syndrome[0x20]; 8539 8540 u8 reserved_at_40[0x40]; 8541 }; 8542 8543 struct mlx5_ifc_destroy_cq_in_bits { 8544 u8 opcode[0x10]; 8545 u8 uid[0x10]; 8546 8547 u8 reserved_at_20[0x10]; 8548 u8 op_mod[0x10]; 8549 8550 u8 reserved_at_40[0x8]; 8551 u8 cqn[0x18]; 8552 8553 u8 reserved_at_60[0x20]; 8554 }; 8555 8556 struct mlx5_ifc_delete_vxlan_udp_dport_out_bits { 8557 u8 status[0x8]; 8558 u8 reserved_at_8[0x18]; 8559 8560 u8 syndrome[0x20]; 8561 8562 u8 reserved_at_40[0x40]; 8563 }; 8564 8565 struct mlx5_ifc_delete_vxlan_udp_dport_in_bits { 8566 u8 opcode[0x10]; 8567 u8 reserved_at_10[0x10]; 8568 8569 u8 reserved_at_20[0x10]; 8570 u8 op_mod[0x10]; 8571 8572 u8 reserved_at_40[0x20]; 8573 8574 u8 reserved_at_60[0x10]; 8575 u8 vxlan_udp_port[0x10]; 8576 }; 8577 8578 struct mlx5_ifc_delete_l2_table_entry_out_bits { 8579 u8 status[0x8]; 8580 u8 reserved_at_8[0x18]; 8581 8582 u8 syndrome[0x20]; 8583 8584 u8 reserved_at_40[0x40]; 8585 }; 8586 8587 struct mlx5_ifc_delete_l2_table_entry_in_bits { 8588 u8 opcode[0x10]; 8589 u8 reserved_at_10[0x10]; 8590 8591 u8 reserved_at_20[0x10]; 8592 u8 op_mod[0x10]; 8593 8594 u8 reserved_at_40[0x60]; 8595 8596 u8 reserved_at_a0[0x8]; 8597 u8 table_index[0x18]; 8598 8599 u8 reserved_at_c0[0x140]; 8600 }; 8601 8602 struct mlx5_ifc_delete_fte_out_bits { 8603 u8 status[0x8]; 8604 u8 reserved_at_8[0x18]; 8605 8606 u8 syndrome[0x20]; 8607 8608 u8 reserved_at_40[0x40]; 8609 }; 8610 8611 struct mlx5_ifc_delete_fte_in_bits { 8612 u8 opcode[0x10]; 8613 u8 reserved_at_10[0x10]; 8614 8615 u8 reserved_at_20[0x10]; 8616 u8 op_mod[0x10]; 8617 8618 u8 other_vport[0x1]; 8619 u8 reserved_at_41[0xf]; 8620 u8 vport_number[0x10]; 8621 8622 u8 reserved_at_60[0x20]; 8623 8624 u8 table_type[0x8]; 8625 u8 reserved_at_88[0x18]; 8626 8627 u8 reserved_at_a0[0x8]; 8628 u8 table_id[0x18]; 8629 8630 u8 reserved_at_c0[0x40]; 8631 8632 u8 flow_index[0x20]; 8633 8634 u8 reserved_at_120[0xe0]; 8635 }; 8636 8637 struct mlx5_ifc_dealloc_xrcd_out_bits { 8638 u8 status[0x8]; 8639 u8 reserved_at_8[0x18]; 8640 8641 u8 syndrome[0x20]; 8642 8643 u8 reserved_at_40[0x40]; 8644 }; 8645 8646 struct mlx5_ifc_dealloc_xrcd_in_bits { 8647 u8 opcode[0x10]; 8648 u8 uid[0x10]; 8649 8650 u8 reserved_at_20[0x10]; 8651 u8 op_mod[0x10]; 8652 8653 u8 reserved_at_40[0x8]; 8654 u8 xrcd[0x18]; 8655 8656 u8 reserved_at_60[0x20]; 8657 }; 8658 8659 struct mlx5_ifc_dealloc_uar_out_bits { 8660 u8 status[0x8]; 8661 u8 reserved_at_8[0x18]; 8662 8663 u8 syndrome[0x20]; 8664 8665 u8 reserved_at_40[0x40]; 8666 }; 8667 8668 struct mlx5_ifc_dealloc_uar_in_bits { 8669 u8 opcode[0x10]; 8670 u8 uid[0x10]; 8671 8672 u8 reserved_at_20[0x10]; 8673 u8 op_mod[0x10]; 8674 8675 u8 reserved_at_40[0x8]; 8676 u8 uar[0x18]; 8677 8678 u8 reserved_at_60[0x20]; 8679 }; 8680 8681 struct mlx5_ifc_dealloc_transport_domain_out_bits { 8682 u8 status[0x8]; 8683 u8 reserved_at_8[0x18]; 8684 8685 u8 syndrome[0x20]; 8686 8687 u8 reserved_at_40[0x40]; 8688 }; 8689 8690 struct mlx5_ifc_dealloc_transport_domain_in_bits { 8691 u8 opcode[0x10]; 8692 u8 uid[0x10]; 8693 8694 u8 reserved_at_20[0x10]; 8695 u8 op_mod[0x10]; 8696 8697 u8 reserved_at_40[0x8]; 8698 u8 transport_domain[0x18]; 8699 8700 u8 reserved_at_60[0x20]; 8701 }; 8702 8703 struct mlx5_ifc_dealloc_q_counter_out_bits { 8704 u8 status[0x8]; 8705 u8 reserved_at_8[0x18]; 8706 8707 u8 syndrome[0x20]; 8708 8709 u8 reserved_at_40[0x40]; 8710 }; 8711 8712 struct mlx5_ifc_dealloc_q_counter_in_bits { 8713 u8 opcode[0x10]; 8714 u8 reserved_at_10[0x10]; 8715 8716 u8 reserved_at_20[0x10]; 8717 u8 op_mod[0x10]; 8718 8719 u8 reserved_at_40[0x18]; 8720 u8 counter_set_id[0x8]; 8721 8722 u8 reserved_at_60[0x20]; 8723 }; 8724 8725 struct mlx5_ifc_dealloc_pd_out_bits { 8726 u8 status[0x8]; 8727 u8 reserved_at_8[0x18]; 8728 8729 u8 syndrome[0x20]; 8730 8731 u8 reserved_at_40[0x40]; 8732 }; 8733 8734 struct mlx5_ifc_dealloc_pd_in_bits { 8735 u8 opcode[0x10]; 8736 u8 uid[0x10]; 8737 8738 u8 reserved_at_20[0x10]; 8739 u8 op_mod[0x10]; 8740 8741 u8 reserved_at_40[0x8]; 8742 u8 pd[0x18]; 8743 8744 u8 reserved_at_60[0x20]; 8745 }; 8746 8747 struct mlx5_ifc_dealloc_flow_counter_out_bits { 8748 u8 status[0x8]; 8749 u8 reserved_at_8[0x18]; 8750 8751 u8 syndrome[0x20]; 8752 8753 u8 reserved_at_40[0x40]; 8754 }; 8755 8756 struct mlx5_ifc_dealloc_flow_counter_in_bits { 8757 u8 opcode[0x10]; 8758 u8 reserved_at_10[0x10]; 8759 8760 u8 reserved_at_20[0x10]; 8761 u8 op_mod[0x10]; 8762 8763 u8 flow_counter_id[0x20]; 8764 8765 u8 reserved_at_60[0x20]; 8766 }; 8767 8768 struct mlx5_ifc_create_xrq_out_bits { 8769 u8 status[0x8]; 8770 u8 reserved_at_8[0x18]; 8771 8772 u8 syndrome[0x20]; 8773 8774 u8 reserved_at_40[0x8]; 8775 u8 xrqn[0x18]; 8776 8777 u8 reserved_at_60[0x20]; 8778 }; 8779 8780 struct mlx5_ifc_create_xrq_in_bits { 8781 u8 opcode[0x10]; 8782 u8 uid[0x10]; 8783 8784 u8 reserved_at_20[0x10]; 8785 u8 op_mod[0x10]; 8786 8787 u8 reserved_at_40[0x40]; 8788 8789 struct mlx5_ifc_xrqc_bits xrq_context; 8790 }; 8791 8792 struct mlx5_ifc_create_xrc_srq_out_bits { 8793 u8 status[0x8]; 8794 u8 reserved_at_8[0x18]; 8795 8796 u8 syndrome[0x20]; 8797 8798 u8 reserved_at_40[0x8]; 8799 u8 xrc_srqn[0x18]; 8800 8801 u8 reserved_at_60[0x20]; 8802 }; 8803 8804 struct mlx5_ifc_create_xrc_srq_in_bits { 8805 u8 opcode[0x10]; 8806 u8 uid[0x10]; 8807 8808 u8 reserved_at_20[0x10]; 8809 u8 op_mod[0x10]; 8810 8811 u8 reserved_at_40[0x40]; 8812 8813 struct mlx5_ifc_xrc_srqc_bits xrc_srq_context_entry; 8814 8815 u8 reserved_at_280[0x60]; 8816 8817 u8 xrc_srq_umem_valid[0x1]; 8818 u8 reserved_at_2e1[0x1f]; 8819 8820 u8 reserved_at_300[0x580]; 8821 8822 u8 pas[][0x40]; 8823 }; 8824 8825 struct mlx5_ifc_create_tis_out_bits { 8826 u8 status[0x8]; 8827 u8 reserved_at_8[0x18]; 8828 8829 u8 syndrome[0x20]; 8830 8831 u8 reserved_at_40[0x8]; 8832 u8 tisn[0x18]; 8833 8834 u8 reserved_at_60[0x20]; 8835 }; 8836 8837 struct mlx5_ifc_create_tis_in_bits { 8838 u8 opcode[0x10]; 8839 u8 uid[0x10]; 8840 8841 u8 reserved_at_20[0x10]; 8842 u8 op_mod[0x10]; 8843 8844 u8 reserved_at_40[0xc0]; 8845 8846 struct mlx5_ifc_tisc_bits ctx; 8847 }; 8848 8849 struct mlx5_ifc_create_tir_out_bits { 8850 u8 status[0x8]; 8851 u8 icm_address_63_40[0x18]; 8852 8853 u8 syndrome[0x20]; 8854 8855 u8 icm_address_39_32[0x8]; 8856 u8 tirn[0x18]; 8857 8858 u8 icm_address_31_0[0x20]; 8859 }; 8860 8861 struct mlx5_ifc_create_tir_in_bits { 8862 u8 opcode[0x10]; 8863 u8 uid[0x10]; 8864 8865 u8 reserved_at_20[0x10]; 8866 u8 op_mod[0x10]; 8867 8868 u8 reserved_at_40[0xc0]; 8869 8870 struct mlx5_ifc_tirc_bits ctx; 8871 }; 8872 8873 struct mlx5_ifc_create_srq_out_bits { 8874 u8 status[0x8]; 8875 u8 reserved_at_8[0x18]; 8876 8877 u8 syndrome[0x20]; 8878 8879 u8 reserved_at_40[0x8]; 8880 u8 srqn[0x18]; 8881 8882 u8 reserved_at_60[0x20]; 8883 }; 8884 8885 struct mlx5_ifc_create_srq_in_bits { 8886 u8 opcode[0x10]; 8887 u8 uid[0x10]; 8888 8889 u8 reserved_at_20[0x10]; 8890 u8 op_mod[0x10]; 8891 8892 u8 reserved_at_40[0x40]; 8893 8894 struct mlx5_ifc_srqc_bits srq_context_entry; 8895 8896 u8 reserved_at_280[0x600]; 8897 8898 u8 pas[][0x40]; 8899 }; 8900 8901 struct mlx5_ifc_create_sq_out_bits { 8902 u8 status[0x8]; 8903 u8 reserved_at_8[0x18]; 8904 8905 u8 syndrome[0x20]; 8906 8907 u8 reserved_at_40[0x8]; 8908 u8 sqn[0x18]; 8909 8910 u8 reserved_at_60[0x20]; 8911 }; 8912 8913 struct mlx5_ifc_create_sq_in_bits { 8914 u8 opcode[0x10]; 8915 u8 uid[0x10]; 8916 8917 u8 reserved_at_20[0x10]; 8918 u8 op_mod[0x10]; 8919 8920 u8 reserved_at_40[0xc0]; 8921 8922 struct mlx5_ifc_sqc_bits ctx; 8923 }; 8924 8925 struct mlx5_ifc_create_scheduling_element_out_bits { 8926 u8 status[0x8]; 8927 u8 reserved_at_8[0x18]; 8928 8929 u8 syndrome[0x20]; 8930 8931 u8 reserved_at_40[0x40]; 8932 8933 u8 scheduling_element_id[0x20]; 8934 8935 u8 reserved_at_a0[0x160]; 8936 }; 8937 8938 struct mlx5_ifc_create_scheduling_element_in_bits { 8939 u8 opcode[0x10]; 8940 u8 reserved_at_10[0x10]; 8941 8942 u8 reserved_at_20[0x10]; 8943 u8 op_mod[0x10]; 8944 8945 u8 scheduling_hierarchy[0x8]; 8946 u8 reserved_at_48[0x18]; 8947 8948 u8 reserved_at_60[0xa0]; 8949 8950 struct mlx5_ifc_scheduling_context_bits scheduling_context; 8951 8952 u8 reserved_at_300[0x100]; 8953 }; 8954 8955 struct mlx5_ifc_create_rqt_out_bits { 8956 u8 status[0x8]; 8957 u8 reserved_at_8[0x18]; 8958 8959 u8 syndrome[0x20]; 8960 8961 u8 reserved_at_40[0x8]; 8962 u8 rqtn[0x18]; 8963 8964 u8 reserved_at_60[0x20]; 8965 }; 8966 8967 struct mlx5_ifc_create_rqt_in_bits { 8968 u8 opcode[0x10]; 8969 u8 uid[0x10]; 8970 8971 u8 reserved_at_20[0x10]; 8972 u8 op_mod[0x10]; 8973 8974 u8 reserved_at_40[0xc0]; 8975 8976 struct mlx5_ifc_rqtc_bits rqt_context; 8977 }; 8978 8979 struct mlx5_ifc_create_rq_out_bits { 8980 u8 status[0x8]; 8981 u8 reserved_at_8[0x18]; 8982 8983 u8 syndrome[0x20]; 8984 8985 u8 reserved_at_40[0x8]; 8986 u8 rqn[0x18]; 8987 8988 u8 reserved_at_60[0x20]; 8989 }; 8990 8991 struct mlx5_ifc_create_rq_in_bits { 8992 u8 opcode[0x10]; 8993 u8 uid[0x10]; 8994 8995 u8 reserved_at_20[0x10]; 8996 u8 op_mod[0x10]; 8997 8998 u8 reserved_at_40[0xc0]; 8999 9000 struct mlx5_ifc_rqc_bits ctx; 9001 }; 9002 9003 struct mlx5_ifc_create_rmp_out_bits { 9004 u8 status[0x8]; 9005 u8 reserved_at_8[0x18]; 9006 9007 u8 syndrome[0x20]; 9008 9009 u8 reserved_at_40[0x8]; 9010 u8 rmpn[0x18]; 9011 9012 u8 reserved_at_60[0x20]; 9013 }; 9014 9015 struct mlx5_ifc_create_rmp_in_bits { 9016 u8 opcode[0x10]; 9017 u8 uid[0x10]; 9018 9019 u8 reserved_at_20[0x10]; 9020 u8 op_mod[0x10]; 9021 9022 u8 reserved_at_40[0xc0]; 9023 9024 struct mlx5_ifc_rmpc_bits ctx; 9025 }; 9026 9027 struct mlx5_ifc_create_qp_out_bits { 9028 u8 status[0x8]; 9029 u8 reserved_at_8[0x18]; 9030 9031 u8 syndrome[0x20]; 9032 9033 u8 reserved_at_40[0x8]; 9034 u8 qpn[0x18]; 9035 9036 u8 ece[0x20]; 9037 }; 9038 9039 struct mlx5_ifc_create_qp_in_bits { 9040 u8 opcode[0x10]; 9041 u8 uid[0x10]; 9042 9043 u8 reserved_at_20[0x10]; 9044 u8 op_mod[0x10]; 9045 9046 u8 qpc_ext[0x1]; 9047 u8 reserved_at_41[0x7]; 9048 u8 input_qpn[0x18]; 9049 9050 u8 reserved_at_60[0x20]; 9051 u8 opt_param_mask[0x20]; 9052 9053 u8 ece[0x20]; 9054 9055 struct mlx5_ifc_qpc_bits qpc; 9056 9057 u8 wq_umem_offset[0x40]; 9058 9059 u8 wq_umem_id[0x20]; 9060 9061 u8 wq_umem_valid[0x1]; 9062 u8 reserved_at_861[0x1f]; 9063 9064 u8 pas[][0x40]; 9065 }; 9066 9067 struct mlx5_ifc_create_psv_out_bits { 9068 u8 status[0x8]; 9069 u8 reserved_at_8[0x18]; 9070 9071 u8 syndrome[0x20]; 9072 9073 u8 reserved_at_40[0x40]; 9074 9075 u8 reserved_at_80[0x8]; 9076 u8 psv0_index[0x18]; 9077 9078 u8 reserved_at_a0[0x8]; 9079 u8 psv1_index[0x18]; 9080 9081 u8 reserved_at_c0[0x8]; 9082 u8 psv2_index[0x18]; 9083 9084 u8 reserved_at_e0[0x8]; 9085 u8 psv3_index[0x18]; 9086 }; 9087 9088 struct mlx5_ifc_create_psv_in_bits { 9089 u8 opcode[0x10]; 9090 u8 reserved_at_10[0x10]; 9091 9092 u8 reserved_at_20[0x10]; 9093 u8 op_mod[0x10]; 9094 9095 u8 num_psv[0x4]; 9096 u8 reserved_at_44[0x4]; 9097 u8 pd[0x18]; 9098 9099 u8 reserved_at_60[0x20]; 9100 }; 9101 9102 struct mlx5_ifc_create_mkey_out_bits { 9103 u8 status[0x8]; 9104 u8 reserved_at_8[0x18]; 9105 9106 u8 syndrome[0x20]; 9107 9108 u8 reserved_at_40[0x8]; 9109 u8 mkey_index[0x18]; 9110 9111 u8 reserved_at_60[0x20]; 9112 }; 9113 9114 struct mlx5_ifc_create_mkey_in_bits { 9115 u8 opcode[0x10]; 9116 u8 uid[0x10]; 9117 9118 u8 reserved_at_20[0x10]; 9119 u8 op_mod[0x10]; 9120 9121 u8 reserved_at_40[0x20]; 9122 9123 u8 pg_access[0x1]; 9124 u8 mkey_umem_valid[0x1]; 9125 u8 reserved_at_62[0x1e]; 9126 9127 struct mlx5_ifc_mkc_bits memory_key_mkey_entry; 9128 9129 u8 reserved_at_280[0x80]; 9130 9131 u8 translations_octword_actual_size[0x20]; 9132 9133 u8 reserved_at_320[0x560]; 9134 9135 u8 klm_pas_mtt[][0x20]; 9136 }; 9137 9138 enum { 9139 MLX5_FLOW_TABLE_TYPE_NIC_RX = 0x0, 9140 MLX5_FLOW_TABLE_TYPE_NIC_TX = 0x1, 9141 MLX5_FLOW_TABLE_TYPE_ESW_EGRESS_ACL = 0x2, 9142 MLX5_FLOW_TABLE_TYPE_ESW_INGRESS_ACL = 0x3, 9143 MLX5_FLOW_TABLE_TYPE_FDB = 0X4, 9144 MLX5_FLOW_TABLE_TYPE_SNIFFER_RX = 0X5, 9145 MLX5_FLOW_TABLE_TYPE_SNIFFER_TX = 0X6, 9146 }; 9147 9148 struct mlx5_ifc_create_flow_table_out_bits { 9149 u8 status[0x8]; 9150 u8 icm_address_63_40[0x18]; 9151 9152 u8 syndrome[0x20]; 9153 9154 u8 icm_address_39_32[0x8]; 9155 u8 table_id[0x18]; 9156 9157 u8 icm_address_31_0[0x20]; 9158 }; 9159 9160 struct mlx5_ifc_create_flow_table_in_bits { 9161 u8 opcode[0x10]; 9162 u8 uid[0x10]; 9163 9164 u8 reserved_at_20[0x10]; 9165 u8 op_mod[0x10]; 9166 9167 u8 other_vport[0x1]; 9168 u8 reserved_at_41[0xf]; 9169 u8 vport_number[0x10]; 9170 9171 u8 reserved_at_60[0x20]; 9172 9173 u8 table_type[0x8]; 9174 u8 reserved_at_88[0x18]; 9175 9176 u8 reserved_at_a0[0x20]; 9177 9178 struct mlx5_ifc_flow_table_context_bits flow_table_context; 9179 }; 9180 9181 struct mlx5_ifc_create_flow_group_out_bits { 9182 u8 status[0x8]; 9183 u8 reserved_at_8[0x18]; 9184 9185 u8 syndrome[0x20]; 9186 9187 u8 reserved_at_40[0x8]; 9188 u8 group_id[0x18]; 9189 9190 u8 reserved_at_60[0x20]; 9191 }; 9192 9193 enum { 9194 MLX5_CREATE_FLOW_GROUP_IN_GROUP_TYPE_TCAM_SUBTABLE = 0x0, 9195 MLX5_CREATE_FLOW_GROUP_IN_GROUP_TYPE_HASH_SPLIT = 0x1, 9196 }; 9197 9198 enum { 9199 MLX5_CREATE_FLOW_GROUP_IN_MATCH_CRITERIA_ENABLE_OUTER_HEADERS = 0x0, 9200 MLX5_CREATE_FLOW_GROUP_IN_MATCH_CRITERIA_ENABLE_MISC_PARAMETERS = 0x1, 9201 MLX5_CREATE_FLOW_GROUP_IN_MATCH_CRITERIA_ENABLE_INNER_HEADERS = 0x2, 9202 MLX5_CREATE_FLOW_GROUP_IN_MATCH_CRITERIA_ENABLE_MISC_PARAMETERS_2 = 0x3, 9203 }; 9204 9205 struct mlx5_ifc_create_flow_group_in_bits { 9206 u8 opcode[0x10]; 9207 u8 reserved_at_10[0x10]; 9208 9209 u8 reserved_at_20[0x10]; 9210 u8 op_mod[0x10]; 9211 9212 u8 other_vport[0x1]; 9213 u8 reserved_at_41[0xf]; 9214 u8 vport_number[0x10]; 9215 9216 u8 reserved_at_60[0x20]; 9217 9218 u8 table_type[0x8]; 9219 u8 reserved_at_88[0x4]; 9220 u8 group_type[0x4]; 9221 u8 reserved_at_90[0x10]; 9222 9223 u8 reserved_at_a0[0x8]; 9224 u8 table_id[0x18]; 9225 9226 u8 source_eswitch_owner_vhca_id_valid[0x1]; 9227 9228 u8 reserved_at_c1[0x1f]; 9229 9230 u8 start_flow_index[0x20]; 9231 9232 u8 reserved_at_100[0x20]; 9233 9234 u8 end_flow_index[0x20]; 9235 9236 u8 reserved_at_140[0x10]; 9237 u8 match_definer_id[0x10]; 9238 9239 u8 reserved_at_160[0x80]; 9240 9241 u8 reserved_at_1e0[0x18]; 9242 u8 match_criteria_enable[0x8]; 9243 9244 struct mlx5_ifc_fte_match_param_bits match_criteria; 9245 9246 u8 reserved_at_1200[0xe00]; 9247 }; 9248 9249 struct mlx5_ifc_create_eq_out_bits { 9250 u8 status[0x8]; 9251 u8 reserved_at_8[0x18]; 9252 9253 u8 syndrome[0x20]; 9254 9255 u8 reserved_at_40[0x18]; 9256 u8 eq_number[0x8]; 9257 9258 u8 reserved_at_60[0x20]; 9259 }; 9260 9261 struct mlx5_ifc_create_eq_in_bits { 9262 u8 opcode[0x10]; 9263 u8 uid[0x10]; 9264 9265 u8 reserved_at_20[0x10]; 9266 u8 op_mod[0x10]; 9267 9268 u8 reserved_at_40[0x40]; 9269 9270 struct mlx5_ifc_eqc_bits eq_context_entry; 9271 9272 u8 reserved_at_280[0x40]; 9273 9274 u8 event_bitmask[4][0x40]; 9275 9276 u8 reserved_at_3c0[0x4c0]; 9277 9278 u8 pas[][0x40]; 9279 }; 9280 9281 struct mlx5_ifc_create_dct_out_bits { 9282 u8 status[0x8]; 9283 u8 reserved_at_8[0x18]; 9284 9285 u8 syndrome[0x20]; 9286 9287 u8 reserved_at_40[0x8]; 9288 u8 dctn[0x18]; 9289 9290 u8 ece[0x20]; 9291 }; 9292 9293 struct mlx5_ifc_create_dct_in_bits { 9294 u8 opcode[0x10]; 9295 u8 uid[0x10]; 9296 9297 u8 reserved_at_20[0x10]; 9298 u8 op_mod[0x10]; 9299 9300 u8 reserved_at_40[0x40]; 9301 9302 struct mlx5_ifc_dctc_bits dct_context_entry; 9303 9304 u8 reserved_at_280[0x180]; 9305 }; 9306 9307 struct mlx5_ifc_create_cq_out_bits { 9308 u8 status[0x8]; 9309 u8 reserved_at_8[0x18]; 9310 9311 u8 syndrome[0x20]; 9312 9313 u8 reserved_at_40[0x8]; 9314 u8 cqn[0x18]; 9315 9316 u8 reserved_at_60[0x20]; 9317 }; 9318 9319 struct mlx5_ifc_create_cq_in_bits { 9320 u8 opcode[0x10]; 9321 u8 uid[0x10]; 9322 9323 u8 reserved_at_20[0x10]; 9324 u8 op_mod[0x10]; 9325 9326 u8 reserved_at_40[0x40]; 9327 9328 struct mlx5_ifc_cqc_bits cq_context; 9329 9330 u8 reserved_at_280[0x60]; 9331 9332 u8 cq_umem_valid[0x1]; 9333 u8 reserved_at_2e1[0x59f]; 9334 9335 u8 pas[][0x40]; 9336 }; 9337 9338 struct mlx5_ifc_config_int_moderation_out_bits { 9339 u8 status[0x8]; 9340 u8 reserved_at_8[0x18]; 9341 9342 u8 syndrome[0x20]; 9343 9344 u8 reserved_at_40[0x4]; 9345 u8 min_delay[0xc]; 9346 u8 int_vector[0x10]; 9347 9348 u8 reserved_at_60[0x20]; 9349 }; 9350 9351 enum { 9352 MLX5_CONFIG_INT_MODERATION_IN_OP_MOD_WRITE = 0x0, 9353 MLX5_CONFIG_INT_MODERATION_IN_OP_MOD_READ = 0x1, 9354 }; 9355 9356 struct mlx5_ifc_config_int_moderation_in_bits { 9357 u8 opcode[0x10]; 9358 u8 reserved_at_10[0x10]; 9359 9360 u8 reserved_at_20[0x10]; 9361 u8 op_mod[0x10]; 9362 9363 u8 reserved_at_40[0x4]; 9364 u8 min_delay[0xc]; 9365 u8 int_vector[0x10]; 9366 9367 u8 reserved_at_60[0x20]; 9368 }; 9369 9370 struct mlx5_ifc_attach_to_mcg_out_bits { 9371 u8 status[0x8]; 9372 u8 reserved_at_8[0x18]; 9373 9374 u8 syndrome[0x20]; 9375 9376 u8 reserved_at_40[0x40]; 9377 }; 9378 9379 struct mlx5_ifc_attach_to_mcg_in_bits { 9380 u8 opcode[0x10]; 9381 u8 uid[0x10]; 9382 9383 u8 reserved_at_20[0x10]; 9384 u8 op_mod[0x10]; 9385 9386 u8 reserved_at_40[0x8]; 9387 u8 qpn[0x18]; 9388 9389 u8 reserved_at_60[0x20]; 9390 9391 u8 multicast_gid[16][0x8]; 9392 }; 9393 9394 struct mlx5_ifc_arm_xrq_out_bits { 9395 u8 status[0x8]; 9396 u8 reserved_at_8[0x18]; 9397 9398 u8 syndrome[0x20]; 9399 9400 u8 reserved_at_40[0x40]; 9401 }; 9402 9403 struct mlx5_ifc_arm_xrq_in_bits { 9404 u8 opcode[0x10]; 9405 u8 reserved_at_10[0x10]; 9406 9407 u8 reserved_at_20[0x10]; 9408 u8 op_mod[0x10]; 9409 9410 u8 reserved_at_40[0x8]; 9411 u8 xrqn[0x18]; 9412 9413 u8 reserved_at_60[0x10]; 9414 u8 lwm[0x10]; 9415 }; 9416 9417 struct mlx5_ifc_arm_xrc_srq_out_bits { 9418 u8 status[0x8]; 9419 u8 reserved_at_8[0x18]; 9420 9421 u8 syndrome[0x20]; 9422 9423 u8 reserved_at_40[0x40]; 9424 }; 9425 9426 enum { 9427 MLX5_ARM_XRC_SRQ_IN_OP_MOD_XRC_SRQ = 0x1, 9428 }; 9429 9430 struct mlx5_ifc_arm_xrc_srq_in_bits { 9431 u8 opcode[0x10]; 9432 u8 uid[0x10]; 9433 9434 u8 reserved_at_20[0x10]; 9435 u8 op_mod[0x10]; 9436 9437 u8 reserved_at_40[0x8]; 9438 u8 xrc_srqn[0x18]; 9439 9440 u8 reserved_at_60[0x10]; 9441 u8 lwm[0x10]; 9442 }; 9443 9444 struct mlx5_ifc_arm_rq_out_bits { 9445 u8 status[0x8]; 9446 u8 reserved_at_8[0x18]; 9447 9448 u8 syndrome[0x20]; 9449 9450 u8 reserved_at_40[0x40]; 9451 }; 9452 9453 enum { 9454 MLX5_ARM_RQ_IN_OP_MOD_SRQ = 0x1, 9455 MLX5_ARM_RQ_IN_OP_MOD_XRQ = 0x2, 9456 }; 9457 9458 struct mlx5_ifc_arm_rq_in_bits { 9459 u8 opcode[0x10]; 9460 u8 uid[0x10]; 9461 9462 u8 reserved_at_20[0x10]; 9463 u8 op_mod[0x10]; 9464 9465 u8 reserved_at_40[0x8]; 9466 u8 srq_number[0x18]; 9467 9468 u8 reserved_at_60[0x10]; 9469 u8 lwm[0x10]; 9470 }; 9471 9472 struct mlx5_ifc_arm_dct_out_bits { 9473 u8 status[0x8]; 9474 u8 reserved_at_8[0x18]; 9475 9476 u8 syndrome[0x20]; 9477 9478 u8 reserved_at_40[0x40]; 9479 }; 9480 9481 struct mlx5_ifc_arm_dct_in_bits { 9482 u8 opcode[0x10]; 9483 u8 reserved_at_10[0x10]; 9484 9485 u8 reserved_at_20[0x10]; 9486 u8 op_mod[0x10]; 9487 9488 u8 reserved_at_40[0x8]; 9489 u8 dct_number[0x18]; 9490 9491 u8 reserved_at_60[0x20]; 9492 }; 9493 9494 struct mlx5_ifc_alloc_xrcd_out_bits { 9495 u8 status[0x8]; 9496 u8 reserved_at_8[0x18]; 9497 9498 u8 syndrome[0x20]; 9499 9500 u8 reserved_at_40[0x8]; 9501 u8 xrcd[0x18]; 9502 9503 u8 reserved_at_60[0x20]; 9504 }; 9505 9506 struct mlx5_ifc_alloc_xrcd_in_bits { 9507 u8 opcode[0x10]; 9508 u8 uid[0x10]; 9509 9510 u8 reserved_at_20[0x10]; 9511 u8 op_mod[0x10]; 9512 9513 u8 reserved_at_40[0x40]; 9514 }; 9515 9516 struct mlx5_ifc_alloc_uar_out_bits { 9517 u8 status[0x8]; 9518 u8 reserved_at_8[0x18]; 9519 9520 u8 syndrome[0x20]; 9521 9522 u8 reserved_at_40[0x8]; 9523 u8 uar[0x18]; 9524 9525 u8 reserved_at_60[0x20]; 9526 }; 9527 9528 struct mlx5_ifc_alloc_uar_in_bits { 9529 u8 opcode[0x10]; 9530 u8 uid[0x10]; 9531 9532 u8 reserved_at_20[0x10]; 9533 u8 op_mod[0x10]; 9534 9535 u8 reserved_at_40[0x40]; 9536 }; 9537 9538 struct mlx5_ifc_alloc_transport_domain_out_bits { 9539 u8 status[0x8]; 9540 u8 reserved_at_8[0x18]; 9541 9542 u8 syndrome[0x20]; 9543 9544 u8 reserved_at_40[0x8]; 9545 u8 transport_domain[0x18]; 9546 9547 u8 reserved_at_60[0x20]; 9548 }; 9549 9550 struct mlx5_ifc_alloc_transport_domain_in_bits { 9551 u8 opcode[0x10]; 9552 u8 uid[0x10]; 9553 9554 u8 reserved_at_20[0x10]; 9555 u8 op_mod[0x10]; 9556 9557 u8 reserved_at_40[0x40]; 9558 }; 9559 9560 struct mlx5_ifc_alloc_q_counter_out_bits { 9561 u8 status[0x8]; 9562 u8 reserved_at_8[0x18]; 9563 9564 u8 syndrome[0x20]; 9565 9566 u8 reserved_at_40[0x18]; 9567 u8 counter_set_id[0x8]; 9568 9569 u8 reserved_at_60[0x20]; 9570 }; 9571 9572 struct mlx5_ifc_alloc_q_counter_in_bits { 9573 u8 opcode[0x10]; 9574 u8 uid[0x10]; 9575 9576 u8 reserved_at_20[0x10]; 9577 u8 op_mod[0x10]; 9578 9579 u8 reserved_at_40[0x40]; 9580 }; 9581 9582 struct mlx5_ifc_alloc_pd_out_bits { 9583 u8 status[0x8]; 9584 u8 reserved_at_8[0x18]; 9585 9586 u8 syndrome[0x20]; 9587 9588 u8 reserved_at_40[0x8]; 9589 u8 pd[0x18]; 9590 9591 u8 reserved_at_60[0x20]; 9592 }; 9593 9594 struct mlx5_ifc_alloc_pd_in_bits { 9595 u8 opcode[0x10]; 9596 u8 uid[0x10]; 9597 9598 u8 reserved_at_20[0x10]; 9599 u8 op_mod[0x10]; 9600 9601 u8 reserved_at_40[0x40]; 9602 }; 9603 9604 struct mlx5_ifc_alloc_flow_counter_out_bits { 9605 u8 status[0x8]; 9606 u8 reserved_at_8[0x18]; 9607 9608 u8 syndrome[0x20]; 9609 9610 u8 flow_counter_id[0x20]; 9611 9612 u8 reserved_at_60[0x20]; 9613 }; 9614 9615 struct mlx5_ifc_alloc_flow_counter_in_bits { 9616 u8 opcode[0x10]; 9617 u8 reserved_at_10[0x10]; 9618 9619 u8 reserved_at_20[0x10]; 9620 u8 op_mod[0x10]; 9621 9622 u8 reserved_at_40[0x33]; 9623 u8 flow_counter_bulk_log_size[0x5]; 9624 u8 flow_counter_bulk[0x8]; 9625 }; 9626 9627 struct mlx5_ifc_add_vxlan_udp_dport_out_bits { 9628 u8 status[0x8]; 9629 u8 reserved_at_8[0x18]; 9630 9631 u8 syndrome[0x20]; 9632 9633 u8 reserved_at_40[0x40]; 9634 }; 9635 9636 struct mlx5_ifc_add_vxlan_udp_dport_in_bits { 9637 u8 opcode[0x10]; 9638 u8 reserved_at_10[0x10]; 9639 9640 u8 reserved_at_20[0x10]; 9641 u8 op_mod[0x10]; 9642 9643 u8 reserved_at_40[0x20]; 9644 9645 u8 reserved_at_60[0x10]; 9646 u8 vxlan_udp_port[0x10]; 9647 }; 9648 9649 struct mlx5_ifc_set_pp_rate_limit_out_bits { 9650 u8 status[0x8]; 9651 u8 reserved_at_8[0x18]; 9652 9653 u8 syndrome[0x20]; 9654 9655 u8 reserved_at_40[0x40]; 9656 }; 9657 9658 struct mlx5_ifc_set_pp_rate_limit_context_bits { 9659 u8 rate_limit[0x20]; 9660 9661 u8 burst_upper_bound[0x20]; 9662 9663 u8 reserved_at_40[0x10]; 9664 u8 typical_packet_size[0x10]; 9665 9666 u8 reserved_at_60[0x120]; 9667 }; 9668 9669 struct mlx5_ifc_set_pp_rate_limit_in_bits { 9670 u8 opcode[0x10]; 9671 u8 uid[0x10]; 9672 9673 u8 reserved_at_20[0x10]; 9674 u8 op_mod[0x10]; 9675 9676 u8 reserved_at_40[0x10]; 9677 u8 rate_limit_index[0x10]; 9678 9679 u8 reserved_at_60[0x20]; 9680 9681 struct mlx5_ifc_set_pp_rate_limit_context_bits ctx; 9682 }; 9683 9684 struct mlx5_ifc_access_register_out_bits { 9685 u8 status[0x8]; 9686 u8 reserved_at_8[0x18]; 9687 9688 u8 syndrome[0x20]; 9689 9690 u8 reserved_at_40[0x40]; 9691 9692 u8 register_data[][0x20]; 9693 }; 9694 9695 enum { 9696 MLX5_ACCESS_REGISTER_IN_OP_MOD_WRITE = 0x0, 9697 MLX5_ACCESS_REGISTER_IN_OP_MOD_READ = 0x1, 9698 }; 9699 9700 struct mlx5_ifc_access_register_in_bits { 9701 u8 opcode[0x10]; 9702 u8 reserved_at_10[0x10]; 9703 9704 u8 reserved_at_20[0x10]; 9705 u8 op_mod[0x10]; 9706 9707 u8 reserved_at_40[0x10]; 9708 u8 register_id[0x10]; 9709 9710 u8 argument[0x20]; 9711 9712 u8 register_data[][0x20]; 9713 }; 9714 9715 struct mlx5_ifc_sltp_reg_bits { 9716 u8 status[0x4]; 9717 u8 version[0x4]; 9718 u8 local_port[0x8]; 9719 u8 pnat[0x2]; 9720 u8 reserved_at_12[0x2]; 9721 u8 lane[0x4]; 9722 u8 reserved_at_18[0x8]; 9723 9724 u8 reserved_at_20[0x20]; 9725 9726 u8 reserved_at_40[0x7]; 9727 u8 polarity[0x1]; 9728 u8 ob_tap0[0x8]; 9729 u8 ob_tap1[0x8]; 9730 u8 ob_tap2[0x8]; 9731 9732 u8 reserved_at_60[0xc]; 9733 u8 ob_preemp_mode[0x4]; 9734 u8 ob_reg[0x8]; 9735 u8 ob_bias[0x8]; 9736 9737 u8 reserved_at_80[0x20]; 9738 }; 9739 9740 struct mlx5_ifc_slrg_reg_bits { 9741 u8 status[0x4]; 9742 u8 version[0x4]; 9743 u8 local_port[0x8]; 9744 u8 pnat[0x2]; 9745 u8 reserved_at_12[0x2]; 9746 u8 lane[0x4]; 9747 u8 reserved_at_18[0x8]; 9748 9749 u8 time_to_link_up[0x10]; 9750 u8 reserved_at_30[0xc]; 9751 u8 grade_lane_speed[0x4]; 9752 9753 u8 grade_version[0x8]; 9754 u8 grade[0x18]; 9755 9756 u8 reserved_at_60[0x4]; 9757 u8 height_grade_type[0x4]; 9758 u8 height_grade[0x18]; 9759 9760 u8 height_dz[0x10]; 9761 u8 height_dv[0x10]; 9762 9763 u8 reserved_at_a0[0x10]; 9764 u8 height_sigma[0x10]; 9765 9766 u8 reserved_at_c0[0x20]; 9767 9768 u8 reserved_at_e0[0x4]; 9769 u8 phase_grade_type[0x4]; 9770 u8 phase_grade[0x18]; 9771 9772 u8 reserved_at_100[0x8]; 9773 u8 phase_eo_pos[0x8]; 9774 u8 reserved_at_110[0x8]; 9775 u8 phase_eo_neg[0x8]; 9776 9777 u8 ffe_set_tested[0x10]; 9778 u8 test_errors_per_lane[0x10]; 9779 }; 9780 9781 struct mlx5_ifc_pvlc_reg_bits { 9782 u8 reserved_at_0[0x8]; 9783 u8 local_port[0x8]; 9784 u8 reserved_at_10[0x10]; 9785 9786 u8 reserved_at_20[0x1c]; 9787 u8 vl_hw_cap[0x4]; 9788 9789 u8 reserved_at_40[0x1c]; 9790 u8 vl_admin[0x4]; 9791 9792 u8 reserved_at_60[0x1c]; 9793 u8 vl_operational[0x4]; 9794 }; 9795 9796 struct mlx5_ifc_pude_reg_bits { 9797 u8 swid[0x8]; 9798 u8 local_port[0x8]; 9799 u8 reserved_at_10[0x4]; 9800 u8 admin_status[0x4]; 9801 u8 reserved_at_18[0x4]; 9802 u8 oper_status[0x4]; 9803 9804 u8 reserved_at_20[0x60]; 9805 }; 9806 9807 struct mlx5_ifc_ptys_reg_bits { 9808 u8 reserved_at_0[0x1]; 9809 u8 an_disable_admin[0x1]; 9810 u8 an_disable_cap[0x1]; 9811 u8 reserved_at_3[0x5]; 9812 u8 local_port[0x8]; 9813 u8 reserved_at_10[0x8]; 9814 u8 plane_ind[0x4]; 9815 u8 reserved_at_1c[0x1]; 9816 u8 proto_mask[0x3]; 9817 9818 u8 an_status[0x4]; 9819 u8 reserved_at_24[0xc]; 9820 u8 data_rate_oper[0x10]; 9821 9822 u8 ext_eth_proto_capability[0x20]; 9823 9824 u8 eth_proto_capability[0x20]; 9825 9826 u8 ib_link_width_capability[0x10]; 9827 u8 ib_proto_capability[0x10]; 9828 9829 u8 ext_eth_proto_admin[0x20]; 9830 9831 u8 eth_proto_admin[0x20]; 9832 9833 u8 ib_link_width_admin[0x10]; 9834 u8 ib_proto_admin[0x10]; 9835 9836 u8 ext_eth_proto_oper[0x20]; 9837 9838 u8 eth_proto_oper[0x20]; 9839 9840 u8 ib_link_width_oper[0x10]; 9841 u8 ib_proto_oper[0x10]; 9842 9843 u8 reserved_at_160[0x1c]; 9844 u8 connector_type[0x4]; 9845 9846 u8 eth_proto_lp_advertise[0x20]; 9847 9848 u8 reserved_at_1a0[0x60]; 9849 }; 9850 9851 struct mlx5_ifc_mlcr_reg_bits { 9852 u8 reserved_at_0[0x8]; 9853 u8 local_port[0x8]; 9854 u8 reserved_at_10[0x20]; 9855 9856 u8 beacon_duration[0x10]; 9857 u8 reserved_at_40[0x10]; 9858 9859 u8 beacon_remain[0x10]; 9860 }; 9861 9862 struct mlx5_ifc_ptas_reg_bits { 9863 u8 reserved_at_0[0x20]; 9864 9865 u8 algorithm_options[0x10]; 9866 u8 reserved_at_30[0x4]; 9867 u8 repetitions_mode[0x4]; 9868 u8 num_of_repetitions[0x8]; 9869 9870 u8 grade_version[0x8]; 9871 u8 height_grade_type[0x4]; 9872 u8 phase_grade_type[0x4]; 9873 u8 height_grade_weight[0x8]; 9874 u8 phase_grade_weight[0x8]; 9875 9876 u8 gisim_measure_bits[0x10]; 9877 u8 adaptive_tap_measure_bits[0x10]; 9878 9879 u8 ber_bath_high_error_threshold[0x10]; 9880 u8 ber_bath_mid_error_threshold[0x10]; 9881 9882 u8 ber_bath_low_error_threshold[0x10]; 9883 u8 one_ratio_high_threshold[0x10]; 9884 9885 u8 one_ratio_high_mid_threshold[0x10]; 9886 u8 one_ratio_low_mid_threshold[0x10]; 9887 9888 u8 one_ratio_low_threshold[0x10]; 9889 u8 ndeo_error_threshold[0x10]; 9890 9891 u8 mixer_offset_step_size[0x10]; 9892 u8 reserved_at_110[0x8]; 9893 u8 mix90_phase_for_voltage_bath[0x8]; 9894 9895 u8 mixer_offset_start[0x10]; 9896 u8 mixer_offset_end[0x10]; 9897 9898 u8 reserved_at_140[0x15]; 9899 u8 ber_test_time[0xb]; 9900 }; 9901 9902 struct mlx5_ifc_pspa_reg_bits { 9903 u8 swid[0x8]; 9904 u8 local_port[0x8]; 9905 u8 sub_port[0x8]; 9906 u8 reserved_at_18[0x8]; 9907 9908 u8 reserved_at_20[0x20]; 9909 }; 9910 9911 struct mlx5_ifc_pqdr_reg_bits { 9912 u8 reserved_at_0[0x8]; 9913 u8 local_port[0x8]; 9914 u8 reserved_at_10[0x5]; 9915 u8 prio[0x3]; 9916 u8 reserved_at_18[0x6]; 9917 u8 mode[0x2]; 9918 9919 u8 reserved_at_20[0x20]; 9920 9921 u8 reserved_at_40[0x10]; 9922 u8 min_threshold[0x10]; 9923 9924 u8 reserved_at_60[0x10]; 9925 u8 max_threshold[0x10]; 9926 9927 u8 reserved_at_80[0x10]; 9928 u8 mark_probability_denominator[0x10]; 9929 9930 u8 reserved_at_a0[0x60]; 9931 }; 9932 9933 struct mlx5_ifc_ppsc_reg_bits { 9934 u8 reserved_at_0[0x8]; 9935 u8 local_port[0x8]; 9936 u8 reserved_at_10[0x10]; 9937 9938 u8 reserved_at_20[0x60]; 9939 9940 u8 reserved_at_80[0x1c]; 9941 u8 wrps_admin[0x4]; 9942 9943 u8 reserved_at_a0[0x1c]; 9944 u8 wrps_status[0x4]; 9945 9946 u8 reserved_at_c0[0x8]; 9947 u8 up_threshold[0x8]; 9948 u8 reserved_at_d0[0x8]; 9949 u8 down_threshold[0x8]; 9950 9951 u8 reserved_at_e0[0x20]; 9952 9953 u8 reserved_at_100[0x1c]; 9954 u8 srps_admin[0x4]; 9955 9956 u8 reserved_at_120[0x1c]; 9957 u8 srps_status[0x4]; 9958 9959 u8 reserved_at_140[0x40]; 9960 }; 9961 9962 struct mlx5_ifc_pplr_reg_bits { 9963 u8 reserved_at_0[0x8]; 9964 u8 local_port[0x8]; 9965 u8 reserved_at_10[0x10]; 9966 9967 u8 reserved_at_20[0x8]; 9968 u8 lb_cap[0x8]; 9969 u8 reserved_at_30[0x8]; 9970 u8 lb_en[0x8]; 9971 }; 9972 9973 struct mlx5_ifc_pplm_reg_bits { 9974 u8 reserved_at_0[0x8]; 9975 u8 local_port[0x8]; 9976 u8 reserved_at_10[0x10]; 9977 9978 u8 reserved_at_20[0x20]; 9979 9980 u8 port_profile_mode[0x8]; 9981 u8 static_port_profile[0x8]; 9982 u8 active_port_profile[0x8]; 9983 u8 reserved_at_58[0x8]; 9984 9985 u8 retransmission_active[0x8]; 9986 u8 fec_mode_active[0x18]; 9987 9988 u8 rs_fec_correction_bypass_cap[0x4]; 9989 u8 reserved_at_84[0x8]; 9990 u8 fec_override_cap_56g[0x4]; 9991 u8 fec_override_cap_100g[0x4]; 9992 u8 fec_override_cap_50g[0x4]; 9993 u8 fec_override_cap_25g[0x4]; 9994 u8 fec_override_cap_10g_40g[0x4]; 9995 9996 u8 rs_fec_correction_bypass_admin[0x4]; 9997 u8 reserved_at_a4[0x8]; 9998 u8 fec_override_admin_56g[0x4]; 9999 u8 fec_override_admin_100g[0x4]; 10000 u8 fec_override_admin_50g[0x4]; 10001 u8 fec_override_admin_25g[0x4]; 10002 u8 fec_override_admin_10g_40g[0x4]; 10003 10004 u8 fec_override_cap_400g_8x[0x10]; 10005 u8 fec_override_cap_200g_4x[0x10]; 10006 10007 u8 fec_override_cap_100g_2x[0x10]; 10008 u8 fec_override_cap_50g_1x[0x10]; 10009 10010 u8 fec_override_admin_400g_8x[0x10]; 10011 u8 fec_override_admin_200g_4x[0x10]; 10012 10013 u8 fec_override_admin_100g_2x[0x10]; 10014 u8 fec_override_admin_50g_1x[0x10]; 10015 10016 u8 fec_override_cap_800g_8x[0x10]; 10017 u8 fec_override_cap_400g_4x[0x10]; 10018 10019 u8 fec_override_cap_200g_2x[0x10]; 10020 u8 fec_override_cap_100g_1x[0x10]; 10021 10022 u8 reserved_at_180[0xa0]; 10023 10024 u8 fec_override_admin_800g_8x[0x10]; 10025 u8 fec_override_admin_400g_4x[0x10]; 10026 10027 u8 fec_override_admin_200g_2x[0x10]; 10028 u8 fec_override_admin_100g_1x[0x10]; 10029 10030 u8 reserved_at_260[0x20]; 10031 }; 10032 10033 struct mlx5_ifc_ppcnt_reg_bits { 10034 u8 swid[0x8]; 10035 u8 local_port[0x8]; 10036 u8 pnat[0x2]; 10037 u8 reserved_at_12[0x8]; 10038 u8 grp[0x6]; 10039 10040 u8 clr[0x1]; 10041 u8 reserved_at_21[0x13]; 10042 u8 plane_ind[0x4]; 10043 u8 reserved_at_38[0x3]; 10044 u8 prio_tc[0x5]; 10045 10046 union mlx5_ifc_eth_cntrs_grp_data_layout_auto_bits counter_set; 10047 }; 10048 10049 struct mlx5_ifc_mpein_reg_bits { 10050 u8 reserved_at_0[0x2]; 10051 u8 depth[0x6]; 10052 u8 pcie_index[0x8]; 10053 u8 node[0x8]; 10054 u8 reserved_at_18[0x8]; 10055 10056 u8 capability_mask[0x20]; 10057 10058 u8 reserved_at_40[0x8]; 10059 u8 link_width_enabled[0x8]; 10060 u8 link_speed_enabled[0x10]; 10061 10062 u8 lane0_physical_position[0x8]; 10063 u8 link_width_active[0x8]; 10064 u8 link_speed_active[0x10]; 10065 10066 u8 num_of_pfs[0x10]; 10067 u8 num_of_vfs[0x10]; 10068 10069 u8 bdf0[0x10]; 10070 u8 reserved_at_b0[0x10]; 10071 10072 u8 max_read_request_size[0x4]; 10073 u8 max_payload_size[0x4]; 10074 u8 reserved_at_c8[0x5]; 10075 u8 pwr_status[0x3]; 10076 u8 port_type[0x4]; 10077 u8 reserved_at_d4[0xb]; 10078 u8 lane_reversal[0x1]; 10079 10080 u8 reserved_at_e0[0x14]; 10081 u8 pci_power[0xc]; 10082 10083 u8 reserved_at_100[0x20]; 10084 10085 u8 device_status[0x10]; 10086 u8 port_state[0x8]; 10087 u8 reserved_at_138[0x8]; 10088 10089 u8 reserved_at_140[0x10]; 10090 u8 receiver_detect_result[0x10]; 10091 10092 u8 reserved_at_160[0x20]; 10093 }; 10094 10095 struct mlx5_ifc_mpcnt_reg_bits { 10096 u8 reserved_at_0[0x8]; 10097 u8 pcie_index[0x8]; 10098 u8 reserved_at_10[0xa]; 10099 u8 grp[0x6]; 10100 10101 u8 clr[0x1]; 10102 u8 reserved_at_21[0x1f]; 10103 10104 union mlx5_ifc_pcie_cntrs_grp_data_layout_auto_bits counter_set; 10105 }; 10106 10107 struct mlx5_ifc_ppad_reg_bits { 10108 u8 reserved_at_0[0x3]; 10109 u8 single_mac[0x1]; 10110 u8 reserved_at_4[0x4]; 10111 u8 local_port[0x8]; 10112 u8 mac_47_32[0x10]; 10113 10114 u8 mac_31_0[0x20]; 10115 10116 u8 reserved_at_40[0x40]; 10117 }; 10118 10119 struct mlx5_ifc_pmtu_reg_bits { 10120 u8 reserved_at_0[0x8]; 10121 u8 local_port[0x8]; 10122 u8 reserved_at_10[0x10]; 10123 10124 u8 max_mtu[0x10]; 10125 u8 reserved_at_30[0x10]; 10126 10127 u8 admin_mtu[0x10]; 10128 u8 reserved_at_50[0x10]; 10129 10130 u8 oper_mtu[0x10]; 10131 u8 reserved_at_70[0x10]; 10132 }; 10133 10134 struct mlx5_ifc_pmpr_reg_bits { 10135 u8 reserved_at_0[0x8]; 10136 u8 module[0x8]; 10137 u8 reserved_at_10[0x10]; 10138 10139 u8 reserved_at_20[0x18]; 10140 u8 attenuation_5g[0x8]; 10141 10142 u8 reserved_at_40[0x18]; 10143 u8 attenuation_7g[0x8]; 10144 10145 u8 reserved_at_60[0x18]; 10146 u8 attenuation_12g[0x8]; 10147 }; 10148 10149 struct mlx5_ifc_pmpe_reg_bits { 10150 u8 reserved_at_0[0x8]; 10151 u8 module[0x8]; 10152 u8 reserved_at_10[0xc]; 10153 u8 module_status[0x4]; 10154 10155 u8 reserved_at_20[0x60]; 10156 }; 10157 10158 struct mlx5_ifc_pmpc_reg_bits { 10159 u8 module_state_updated[32][0x8]; 10160 }; 10161 10162 struct mlx5_ifc_pmlpn_reg_bits { 10163 u8 reserved_at_0[0x4]; 10164 u8 mlpn_status[0x4]; 10165 u8 local_port[0x8]; 10166 u8 reserved_at_10[0x10]; 10167 10168 u8 e[0x1]; 10169 u8 reserved_at_21[0x1f]; 10170 }; 10171 10172 struct mlx5_ifc_pmlp_reg_bits { 10173 u8 rxtx[0x1]; 10174 u8 reserved_at_1[0x7]; 10175 u8 local_port[0x8]; 10176 u8 reserved_at_10[0x8]; 10177 u8 width[0x8]; 10178 10179 u8 lane0_module_mapping[0x20]; 10180 10181 u8 lane1_module_mapping[0x20]; 10182 10183 u8 lane2_module_mapping[0x20]; 10184 10185 u8 lane3_module_mapping[0x20]; 10186 10187 u8 reserved_at_a0[0x160]; 10188 }; 10189 10190 struct mlx5_ifc_pmaos_reg_bits { 10191 u8 reserved_at_0[0x8]; 10192 u8 module[0x8]; 10193 u8 reserved_at_10[0x4]; 10194 u8 admin_status[0x4]; 10195 u8 reserved_at_18[0x4]; 10196 u8 oper_status[0x4]; 10197 10198 u8 ase[0x1]; 10199 u8 ee[0x1]; 10200 u8 reserved_at_22[0x1c]; 10201 u8 e[0x2]; 10202 10203 u8 reserved_at_40[0x40]; 10204 }; 10205 10206 struct mlx5_ifc_plpc_reg_bits { 10207 u8 reserved_at_0[0x4]; 10208 u8 profile_id[0xc]; 10209 u8 reserved_at_10[0x4]; 10210 u8 proto_mask[0x4]; 10211 u8 reserved_at_18[0x8]; 10212 10213 u8 reserved_at_20[0x10]; 10214 u8 lane_speed[0x10]; 10215 10216 u8 reserved_at_40[0x17]; 10217 u8 lpbf[0x1]; 10218 u8 fec_mode_policy[0x8]; 10219 10220 u8 retransmission_capability[0x8]; 10221 u8 fec_mode_capability[0x18]; 10222 10223 u8 retransmission_support_admin[0x8]; 10224 u8 fec_mode_support_admin[0x18]; 10225 10226 u8 retransmission_request_admin[0x8]; 10227 u8 fec_mode_request_admin[0x18]; 10228 10229 u8 reserved_at_c0[0x80]; 10230 }; 10231 10232 struct mlx5_ifc_plib_reg_bits { 10233 u8 reserved_at_0[0x8]; 10234 u8 local_port[0x8]; 10235 u8 reserved_at_10[0x8]; 10236 u8 ib_port[0x8]; 10237 10238 u8 reserved_at_20[0x60]; 10239 }; 10240 10241 struct mlx5_ifc_plbf_reg_bits { 10242 u8 reserved_at_0[0x8]; 10243 u8 local_port[0x8]; 10244 u8 reserved_at_10[0xd]; 10245 u8 lbf_mode[0x3]; 10246 10247 u8 reserved_at_20[0x20]; 10248 }; 10249 10250 struct mlx5_ifc_pipg_reg_bits { 10251 u8 reserved_at_0[0x8]; 10252 u8 local_port[0x8]; 10253 u8 reserved_at_10[0x10]; 10254 10255 u8 dic[0x1]; 10256 u8 reserved_at_21[0x19]; 10257 u8 ipg[0x4]; 10258 u8 reserved_at_3e[0x2]; 10259 }; 10260 10261 struct mlx5_ifc_pifr_reg_bits { 10262 u8 reserved_at_0[0x8]; 10263 u8 local_port[0x8]; 10264 u8 reserved_at_10[0x10]; 10265 10266 u8 reserved_at_20[0xe0]; 10267 10268 u8 port_filter[8][0x20]; 10269 10270 u8 port_filter_update_en[8][0x20]; 10271 }; 10272 10273 struct mlx5_ifc_pfcc_reg_bits { 10274 u8 reserved_at_0[0x8]; 10275 u8 local_port[0x8]; 10276 u8 reserved_at_10[0xb]; 10277 u8 ppan_mask_n[0x1]; 10278 u8 minor_stall_mask[0x1]; 10279 u8 critical_stall_mask[0x1]; 10280 u8 reserved_at_1e[0x2]; 10281 10282 u8 ppan[0x4]; 10283 u8 reserved_at_24[0x4]; 10284 u8 prio_mask_tx[0x8]; 10285 u8 reserved_at_30[0x8]; 10286 u8 prio_mask_rx[0x8]; 10287 10288 u8 pptx[0x1]; 10289 u8 aptx[0x1]; 10290 u8 pptx_mask_n[0x1]; 10291 u8 reserved_at_43[0x5]; 10292 u8 pfctx[0x8]; 10293 u8 reserved_at_50[0x10]; 10294 10295 u8 pprx[0x1]; 10296 u8 aprx[0x1]; 10297 u8 pprx_mask_n[0x1]; 10298 u8 reserved_at_63[0x5]; 10299 u8 pfcrx[0x8]; 10300 u8 reserved_at_70[0x10]; 10301 10302 u8 device_stall_minor_watermark[0x10]; 10303 u8 device_stall_critical_watermark[0x10]; 10304 10305 u8 reserved_at_a0[0x60]; 10306 }; 10307 10308 struct mlx5_ifc_pelc_reg_bits { 10309 u8 op[0x4]; 10310 u8 reserved_at_4[0x4]; 10311 u8 local_port[0x8]; 10312 u8 reserved_at_10[0x10]; 10313 10314 u8 op_admin[0x8]; 10315 u8 op_capability[0x8]; 10316 u8 op_request[0x8]; 10317 u8 op_active[0x8]; 10318 10319 u8 admin[0x40]; 10320 10321 u8 capability[0x40]; 10322 10323 u8 request[0x40]; 10324 10325 u8 active[0x40]; 10326 10327 u8 reserved_at_140[0x80]; 10328 }; 10329 10330 struct mlx5_ifc_peir_reg_bits { 10331 u8 reserved_at_0[0x8]; 10332 u8 local_port[0x8]; 10333 u8 reserved_at_10[0x10]; 10334 10335 u8 reserved_at_20[0xc]; 10336 u8 error_count[0x4]; 10337 u8 reserved_at_30[0x10]; 10338 10339 u8 reserved_at_40[0xc]; 10340 u8 lane[0x4]; 10341 u8 reserved_at_50[0x8]; 10342 u8 error_type[0x8]; 10343 }; 10344 10345 struct mlx5_ifc_mpegc_reg_bits { 10346 u8 reserved_at_0[0x30]; 10347 u8 field_select[0x10]; 10348 10349 u8 tx_overflow_sense[0x1]; 10350 u8 mark_cqe[0x1]; 10351 u8 mark_cnp[0x1]; 10352 u8 reserved_at_43[0x1b]; 10353 u8 tx_lossy_overflow_oper[0x2]; 10354 10355 u8 reserved_at_60[0x100]; 10356 }; 10357 10358 struct mlx5_ifc_mpir_reg_bits { 10359 u8 sdm[0x1]; 10360 u8 reserved_at_1[0x1b]; 10361 u8 host_buses[0x4]; 10362 10363 u8 reserved_at_20[0x20]; 10364 10365 u8 local_port[0x8]; 10366 u8 reserved_at_28[0x18]; 10367 10368 u8 reserved_at_60[0x20]; 10369 }; 10370 10371 enum { 10372 MLX5_MTUTC_FREQ_ADJ_UNITS_PPB = 0x0, 10373 MLX5_MTUTC_FREQ_ADJ_UNITS_SCALED_PPM = 0x1, 10374 }; 10375 10376 enum { 10377 MLX5_MTUTC_OPERATION_SET_TIME_IMMEDIATE = 0x1, 10378 MLX5_MTUTC_OPERATION_ADJUST_TIME = 0x2, 10379 MLX5_MTUTC_OPERATION_ADJUST_FREQ_UTC = 0x3, 10380 }; 10381 10382 struct mlx5_ifc_mtutc_reg_bits { 10383 u8 reserved_at_0[0x5]; 10384 u8 freq_adj_units[0x3]; 10385 u8 reserved_at_8[0x3]; 10386 u8 log_max_freq_adjustment[0x5]; 10387 10388 u8 reserved_at_10[0xc]; 10389 u8 operation[0x4]; 10390 10391 u8 freq_adjustment[0x20]; 10392 10393 u8 reserved_at_40[0x40]; 10394 10395 u8 utc_sec[0x20]; 10396 10397 u8 reserved_at_a0[0x2]; 10398 u8 utc_nsec[0x1e]; 10399 10400 u8 time_adjustment[0x20]; 10401 }; 10402 10403 struct mlx5_ifc_pcam_enhanced_features_bits { 10404 u8 reserved_at_0[0x48]; 10405 u8 fec_100G_per_lane_in_pplm[0x1]; 10406 u8 reserved_at_49[0x1f]; 10407 u8 fec_50G_per_lane_in_pplm[0x1]; 10408 u8 reserved_at_69[0x4]; 10409 u8 rx_icrc_encapsulated_counter[0x1]; 10410 u8 reserved_at_6e[0x4]; 10411 u8 ptys_extended_ethernet[0x1]; 10412 u8 reserved_at_73[0x3]; 10413 u8 pfcc_mask[0x1]; 10414 u8 reserved_at_77[0x3]; 10415 u8 per_lane_error_counters[0x1]; 10416 u8 rx_buffer_fullness_counters[0x1]; 10417 u8 ptys_connector_type[0x1]; 10418 u8 reserved_at_7d[0x1]; 10419 u8 ppcnt_discard_group[0x1]; 10420 u8 ppcnt_statistical_group[0x1]; 10421 }; 10422 10423 struct mlx5_ifc_pcam_regs_5000_to_507f_bits { 10424 u8 port_access_reg_cap_mask_127_to_96[0x20]; 10425 u8 port_access_reg_cap_mask_95_to_64[0x20]; 10426 10427 u8 port_access_reg_cap_mask_63_to_36[0x1c]; 10428 u8 pplm[0x1]; 10429 u8 port_access_reg_cap_mask_34_to_32[0x3]; 10430 10431 u8 port_access_reg_cap_mask_31_to_13[0x13]; 10432 u8 pbmc[0x1]; 10433 u8 pptb[0x1]; 10434 u8 port_access_reg_cap_mask_10_to_09[0x2]; 10435 u8 ppcnt[0x1]; 10436 u8 port_access_reg_cap_mask_07_to_00[0x8]; 10437 }; 10438 10439 struct mlx5_ifc_pcam_reg_bits { 10440 u8 reserved_at_0[0x8]; 10441 u8 feature_group[0x8]; 10442 u8 reserved_at_10[0x8]; 10443 u8 access_reg_group[0x8]; 10444 10445 u8 reserved_at_20[0x20]; 10446 10447 union { 10448 struct mlx5_ifc_pcam_regs_5000_to_507f_bits regs_5000_to_507f; 10449 u8 reserved_at_0[0x80]; 10450 } port_access_reg_cap_mask; 10451 10452 u8 reserved_at_c0[0x80]; 10453 10454 union { 10455 struct mlx5_ifc_pcam_enhanced_features_bits enhanced_features; 10456 u8 reserved_at_0[0x80]; 10457 } feature_cap_mask; 10458 10459 u8 reserved_at_1c0[0xc0]; 10460 }; 10461 10462 struct mlx5_ifc_mcam_enhanced_features_bits { 10463 u8 reserved_at_0[0x50]; 10464 u8 mtutc_freq_adj_units[0x1]; 10465 u8 mtutc_time_adjustment_extended_range[0x1]; 10466 u8 reserved_at_52[0xb]; 10467 u8 mcia_32dwords[0x1]; 10468 u8 out_pulse_duration_ns[0x1]; 10469 u8 npps_period[0x1]; 10470 u8 reserved_at_60[0xa]; 10471 u8 reset_state[0x1]; 10472 u8 ptpcyc2realtime_modify[0x1]; 10473 u8 reserved_at_6c[0x2]; 10474 u8 pci_status_and_power[0x1]; 10475 u8 reserved_at_6f[0x5]; 10476 u8 mark_tx_action_cnp[0x1]; 10477 u8 mark_tx_action_cqe[0x1]; 10478 u8 dynamic_tx_overflow[0x1]; 10479 u8 reserved_at_77[0x4]; 10480 u8 pcie_outbound_stalled[0x1]; 10481 u8 tx_overflow_buffer_pkt[0x1]; 10482 u8 mtpps_enh_out_per_adj[0x1]; 10483 u8 mtpps_fs[0x1]; 10484 u8 pcie_performance_group[0x1]; 10485 }; 10486 10487 struct mlx5_ifc_mcam_access_reg_bits { 10488 u8 reserved_at_0[0x1c]; 10489 u8 mcda[0x1]; 10490 u8 mcc[0x1]; 10491 u8 mcqi[0x1]; 10492 u8 mcqs[0x1]; 10493 10494 u8 regs_95_to_90[0x6]; 10495 u8 mpir[0x1]; 10496 u8 regs_88_to_87[0x2]; 10497 u8 mpegc[0x1]; 10498 u8 mtutc[0x1]; 10499 u8 regs_84_to_68[0x11]; 10500 u8 tracer_registers[0x4]; 10501 10502 u8 regs_63_to_46[0x12]; 10503 u8 mrtc[0x1]; 10504 u8 regs_44_to_41[0x4]; 10505 u8 mfrl[0x1]; 10506 u8 regs_39_to_32[0x8]; 10507 10508 u8 regs_31_to_11[0x15]; 10509 u8 mtmp[0x1]; 10510 u8 regs_9_to_0[0xa]; 10511 }; 10512 10513 struct mlx5_ifc_mcam_access_reg_bits1 { 10514 u8 regs_127_to_96[0x20]; 10515 10516 u8 regs_95_to_64[0x20]; 10517 10518 u8 regs_63_to_32[0x20]; 10519 10520 u8 regs_31_to_0[0x20]; 10521 }; 10522 10523 struct mlx5_ifc_mcam_access_reg_bits2 { 10524 u8 regs_127_to_99[0x1d]; 10525 u8 mirc[0x1]; 10526 u8 regs_97_to_96[0x2]; 10527 10528 u8 regs_95_to_87[0x09]; 10529 u8 synce_registers[0x2]; 10530 u8 regs_84_to_64[0x15]; 10531 10532 u8 regs_63_to_32[0x20]; 10533 10534 u8 regs_31_to_0[0x20]; 10535 }; 10536 10537 struct mlx5_ifc_mcam_access_reg_bits3 { 10538 u8 regs_127_to_96[0x20]; 10539 10540 u8 regs_95_to_64[0x20]; 10541 10542 u8 regs_63_to_32[0x20]; 10543 10544 u8 regs_31_to_2[0x1e]; 10545 u8 mtctr[0x1]; 10546 u8 mtptm[0x1]; 10547 }; 10548 10549 struct mlx5_ifc_mcam_reg_bits { 10550 u8 reserved_at_0[0x8]; 10551 u8 feature_group[0x8]; 10552 u8 reserved_at_10[0x8]; 10553 u8 access_reg_group[0x8]; 10554 10555 u8 reserved_at_20[0x20]; 10556 10557 union { 10558 struct mlx5_ifc_mcam_access_reg_bits access_regs; 10559 struct mlx5_ifc_mcam_access_reg_bits1 access_regs1; 10560 struct mlx5_ifc_mcam_access_reg_bits2 access_regs2; 10561 struct mlx5_ifc_mcam_access_reg_bits3 access_regs3; 10562 u8 reserved_at_0[0x80]; 10563 } mng_access_reg_cap_mask; 10564 10565 u8 reserved_at_c0[0x80]; 10566 10567 union { 10568 struct mlx5_ifc_mcam_enhanced_features_bits enhanced_features; 10569 u8 reserved_at_0[0x80]; 10570 } mng_feature_cap_mask; 10571 10572 u8 reserved_at_1c0[0x80]; 10573 }; 10574 10575 struct mlx5_ifc_qcam_access_reg_cap_mask { 10576 u8 qcam_access_reg_cap_mask_127_to_20[0x6C]; 10577 u8 qpdpm[0x1]; 10578 u8 qcam_access_reg_cap_mask_18_to_4[0x0F]; 10579 u8 qdpm[0x1]; 10580 u8 qpts[0x1]; 10581 u8 qcap[0x1]; 10582 u8 qcam_access_reg_cap_mask_0[0x1]; 10583 }; 10584 10585 struct mlx5_ifc_qcam_qos_feature_cap_mask { 10586 u8 qcam_qos_feature_cap_mask_127_to_1[0x7F]; 10587 u8 qpts_trust_both[0x1]; 10588 }; 10589 10590 struct mlx5_ifc_qcam_reg_bits { 10591 u8 reserved_at_0[0x8]; 10592 u8 feature_group[0x8]; 10593 u8 reserved_at_10[0x8]; 10594 u8 access_reg_group[0x8]; 10595 u8 reserved_at_20[0x20]; 10596 10597 union { 10598 struct mlx5_ifc_qcam_access_reg_cap_mask reg_cap; 10599 u8 reserved_at_0[0x80]; 10600 } qos_access_reg_cap_mask; 10601 10602 u8 reserved_at_c0[0x80]; 10603 10604 union { 10605 struct mlx5_ifc_qcam_qos_feature_cap_mask feature_cap; 10606 u8 reserved_at_0[0x80]; 10607 } qos_feature_cap_mask; 10608 10609 u8 reserved_at_1c0[0x80]; 10610 }; 10611 10612 struct mlx5_ifc_core_dump_reg_bits { 10613 u8 reserved_at_0[0x18]; 10614 u8 core_dump_type[0x8]; 10615 10616 u8 reserved_at_20[0x30]; 10617 u8 vhca_id[0x10]; 10618 10619 u8 reserved_at_60[0x8]; 10620 u8 qpn[0x18]; 10621 u8 reserved_at_80[0x180]; 10622 }; 10623 10624 struct mlx5_ifc_pcap_reg_bits { 10625 u8 reserved_at_0[0x8]; 10626 u8 local_port[0x8]; 10627 u8 reserved_at_10[0x10]; 10628 10629 u8 port_capability_mask[4][0x20]; 10630 }; 10631 10632 struct mlx5_ifc_paos_reg_bits { 10633 u8 swid[0x8]; 10634 u8 local_port[0x8]; 10635 u8 reserved_at_10[0x4]; 10636 u8 admin_status[0x4]; 10637 u8 reserved_at_18[0x4]; 10638 u8 oper_status[0x4]; 10639 10640 u8 ase[0x1]; 10641 u8 ee[0x1]; 10642 u8 reserved_at_22[0x1c]; 10643 u8 e[0x2]; 10644 10645 u8 reserved_at_40[0x40]; 10646 }; 10647 10648 struct mlx5_ifc_pamp_reg_bits { 10649 u8 reserved_at_0[0x8]; 10650 u8 opamp_group[0x8]; 10651 u8 reserved_at_10[0xc]; 10652 u8 opamp_group_type[0x4]; 10653 10654 u8 start_index[0x10]; 10655 u8 reserved_at_30[0x4]; 10656 u8 num_of_indices[0xc]; 10657 10658 u8 index_data[18][0x10]; 10659 }; 10660 10661 struct mlx5_ifc_pcmr_reg_bits { 10662 u8 reserved_at_0[0x8]; 10663 u8 local_port[0x8]; 10664 u8 reserved_at_10[0x10]; 10665 10666 u8 entropy_force_cap[0x1]; 10667 u8 entropy_calc_cap[0x1]; 10668 u8 entropy_gre_calc_cap[0x1]; 10669 u8 reserved_at_23[0xf]; 10670 u8 rx_ts_over_crc_cap[0x1]; 10671 u8 reserved_at_33[0xb]; 10672 u8 fcs_cap[0x1]; 10673 u8 reserved_at_3f[0x1]; 10674 10675 u8 entropy_force[0x1]; 10676 u8 entropy_calc[0x1]; 10677 u8 entropy_gre_calc[0x1]; 10678 u8 reserved_at_43[0xf]; 10679 u8 rx_ts_over_crc[0x1]; 10680 u8 reserved_at_53[0xb]; 10681 u8 fcs_chk[0x1]; 10682 u8 reserved_at_5f[0x1]; 10683 }; 10684 10685 struct mlx5_ifc_lane_2_module_mapping_bits { 10686 u8 reserved_at_0[0x4]; 10687 u8 rx_lane[0x4]; 10688 u8 reserved_at_8[0x4]; 10689 u8 tx_lane[0x4]; 10690 u8 reserved_at_10[0x8]; 10691 u8 module[0x8]; 10692 }; 10693 10694 struct mlx5_ifc_bufferx_reg_bits { 10695 u8 reserved_at_0[0x6]; 10696 u8 lossy[0x1]; 10697 u8 epsb[0x1]; 10698 u8 reserved_at_8[0x8]; 10699 u8 size[0x10]; 10700 10701 u8 xoff_threshold[0x10]; 10702 u8 xon_threshold[0x10]; 10703 }; 10704 10705 struct mlx5_ifc_set_node_in_bits { 10706 u8 node_description[64][0x8]; 10707 }; 10708 10709 struct mlx5_ifc_register_power_settings_bits { 10710 u8 reserved_at_0[0x18]; 10711 u8 power_settings_level[0x8]; 10712 10713 u8 reserved_at_20[0x60]; 10714 }; 10715 10716 struct mlx5_ifc_register_host_endianness_bits { 10717 u8 he[0x1]; 10718 u8 reserved_at_1[0x1f]; 10719 10720 u8 reserved_at_20[0x60]; 10721 }; 10722 10723 struct mlx5_ifc_umr_pointer_desc_argument_bits { 10724 u8 reserved_at_0[0x20]; 10725 10726 u8 mkey[0x20]; 10727 10728 u8 addressh_63_32[0x20]; 10729 10730 u8 addressl_31_0[0x20]; 10731 }; 10732 10733 struct mlx5_ifc_ud_adrs_vector_bits { 10734 u8 dc_key[0x40]; 10735 10736 u8 ext[0x1]; 10737 u8 reserved_at_41[0x7]; 10738 u8 destination_qp_dct[0x18]; 10739 10740 u8 static_rate[0x4]; 10741 u8 sl_eth_prio[0x4]; 10742 u8 fl[0x1]; 10743 u8 mlid[0x7]; 10744 u8 rlid_udp_sport[0x10]; 10745 10746 u8 reserved_at_80[0x20]; 10747 10748 u8 rmac_47_16[0x20]; 10749 10750 u8 rmac_15_0[0x10]; 10751 u8 tclass[0x8]; 10752 u8 hop_limit[0x8]; 10753 10754 u8 reserved_at_e0[0x1]; 10755 u8 grh[0x1]; 10756 u8 reserved_at_e2[0x2]; 10757 u8 src_addr_index[0x8]; 10758 u8 flow_label[0x14]; 10759 10760 u8 rgid_rip[16][0x8]; 10761 }; 10762 10763 struct mlx5_ifc_pages_req_event_bits { 10764 u8 reserved_at_0[0x10]; 10765 u8 function_id[0x10]; 10766 10767 u8 num_pages[0x20]; 10768 10769 u8 reserved_at_40[0xa0]; 10770 }; 10771 10772 struct mlx5_ifc_eqe_bits { 10773 u8 reserved_at_0[0x8]; 10774 u8 event_type[0x8]; 10775 u8 reserved_at_10[0x8]; 10776 u8 event_sub_type[0x8]; 10777 10778 u8 reserved_at_20[0xe0]; 10779 10780 union mlx5_ifc_event_auto_bits event_data; 10781 10782 u8 reserved_at_1e0[0x10]; 10783 u8 signature[0x8]; 10784 u8 reserved_at_1f8[0x7]; 10785 u8 owner[0x1]; 10786 }; 10787 10788 enum { 10789 MLX5_CMD_QUEUE_ENTRY_TYPE_PCIE_CMD_IF_TRANSPORT = 0x7, 10790 }; 10791 10792 struct mlx5_ifc_cmd_queue_entry_bits { 10793 u8 type[0x8]; 10794 u8 reserved_at_8[0x18]; 10795 10796 u8 input_length[0x20]; 10797 10798 u8 input_mailbox_pointer_63_32[0x20]; 10799 10800 u8 input_mailbox_pointer_31_9[0x17]; 10801 u8 reserved_at_77[0x9]; 10802 10803 u8 command_input_inline_data[16][0x8]; 10804 10805 u8 command_output_inline_data[16][0x8]; 10806 10807 u8 output_mailbox_pointer_63_32[0x20]; 10808 10809 u8 output_mailbox_pointer_31_9[0x17]; 10810 u8 reserved_at_1b7[0x9]; 10811 10812 u8 output_length[0x20]; 10813 10814 u8 token[0x8]; 10815 u8 signature[0x8]; 10816 u8 reserved_at_1f0[0x8]; 10817 u8 status[0x7]; 10818 u8 ownership[0x1]; 10819 }; 10820 10821 struct mlx5_ifc_cmd_out_bits { 10822 u8 status[0x8]; 10823 u8 reserved_at_8[0x18]; 10824 10825 u8 syndrome[0x20]; 10826 10827 u8 command_output[0x20]; 10828 }; 10829 10830 struct mlx5_ifc_cmd_in_bits { 10831 u8 opcode[0x10]; 10832 u8 reserved_at_10[0x10]; 10833 10834 u8 reserved_at_20[0x10]; 10835 u8 op_mod[0x10]; 10836 10837 u8 command[][0x20]; 10838 }; 10839 10840 struct mlx5_ifc_cmd_if_box_bits { 10841 u8 mailbox_data[512][0x8]; 10842 10843 u8 reserved_at_1000[0x180]; 10844 10845 u8 next_pointer_63_32[0x20]; 10846 10847 u8 next_pointer_31_10[0x16]; 10848 u8 reserved_at_11b6[0xa]; 10849 10850 u8 block_number[0x20]; 10851 10852 u8 reserved_at_11e0[0x8]; 10853 u8 token[0x8]; 10854 u8 ctrl_signature[0x8]; 10855 u8 signature[0x8]; 10856 }; 10857 10858 struct mlx5_ifc_mtt_bits { 10859 u8 ptag_63_32[0x20]; 10860 10861 u8 ptag_31_8[0x18]; 10862 u8 reserved_at_38[0x6]; 10863 u8 wr_en[0x1]; 10864 u8 rd_en[0x1]; 10865 }; 10866 10867 struct mlx5_ifc_query_wol_rol_out_bits { 10868 u8 status[0x8]; 10869 u8 reserved_at_8[0x18]; 10870 10871 u8 syndrome[0x20]; 10872 10873 u8 reserved_at_40[0x10]; 10874 u8 rol_mode[0x8]; 10875 u8 wol_mode[0x8]; 10876 10877 u8 reserved_at_60[0x20]; 10878 }; 10879 10880 struct mlx5_ifc_query_wol_rol_in_bits { 10881 u8 opcode[0x10]; 10882 u8 reserved_at_10[0x10]; 10883 10884 u8 reserved_at_20[0x10]; 10885 u8 op_mod[0x10]; 10886 10887 u8 reserved_at_40[0x40]; 10888 }; 10889 10890 struct mlx5_ifc_set_wol_rol_out_bits { 10891 u8 status[0x8]; 10892 u8 reserved_at_8[0x18]; 10893 10894 u8 syndrome[0x20]; 10895 10896 u8 reserved_at_40[0x40]; 10897 }; 10898 10899 struct mlx5_ifc_set_wol_rol_in_bits { 10900 u8 opcode[0x10]; 10901 u8 reserved_at_10[0x10]; 10902 10903 u8 reserved_at_20[0x10]; 10904 u8 op_mod[0x10]; 10905 10906 u8 rol_mode_valid[0x1]; 10907 u8 wol_mode_valid[0x1]; 10908 u8 reserved_at_42[0xe]; 10909 u8 rol_mode[0x8]; 10910 u8 wol_mode[0x8]; 10911 10912 u8 reserved_at_60[0x20]; 10913 }; 10914 10915 enum { 10916 MLX5_INITIAL_SEG_NIC_INTERFACE_FULL_DRIVER = 0x0, 10917 MLX5_INITIAL_SEG_NIC_INTERFACE_DISABLED = 0x1, 10918 MLX5_INITIAL_SEG_NIC_INTERFACE_NO_DRAM_NIC = 0x2, 10919 MLX5_INITIAL_SEG_NIC_INTERFACE_SW_RESET = 0x7, 10920 }; 10921 10922 enum { 10923 MLX5_INITIAL_SEG_NIC_INTERFACE_SUPPORTED_FULL_DRIVER = 0x0, 10924 MLX5_INITIAL_SEG_NIC_INTERFACE_SUPPORTED_DISABLED = 0x1, 10925 MLX5_INITIAL_SEG_NIC_INTERFACE_SUPPORTED_NO_DRAM_NIC = 0x2, 10926 }; 10927 10928 enum { 10929 MLX5_INITIAL_SEG_HEALTH_SYNDROME_FW_INTERNAL_ERR = 0x1, 10930 MLX5_INITIAL_SEG_HEALTH_SYNDROME_DEAD_IRISC = 0x7, 10931 MLX5_INITIAL_SEG_HEALTH_SYNDROME_HW_FATAL_ERR = 0x8, 10932 MLX5_INITIAL_SEG_HEALTH_SYNDROME_FW_CRC_ERR = 0x9, 10933 MLX5_INITIAL_SEG_HEALTH_SYNDROME_ICM_FETCH_PCI_ERR = 0xa, 10934 MLX5_INITIAL_SEG_HEALTH_SYNDROME_ICM_PAGE_ERR = 0xb, 10935 MLX5_INITIAL_SEG_HEALTH_SYNDROME_ASYNCHRONOUS_EQ_BUF_OVERRUN = 0xc, 10936 MLX5_INITIAL_SEG_HEALTH_SYNDROME_EQ_IN_ERR = 0xd, 10937 MLX5_INITIAL_SEG_HEALTH_SYNDROME_EQ_INV = 0xe, 10938 MLX5_INITIAL_SEG_HEALTH_SYNDROME_FFSER_ERR = 0xf, 10939 MLX5_INITIAL_SEG_HEALTH_SYNDROME_HIGH_TEMP_ERR = 0x10, 10940 MLX5_INITIAL_SEG_HEALTH_SYNDROME_ICM_PCI_POISONED_ERR = 0x12, 10941 }; 10942 10943 struct mlx5_ifc_initial_seg_bits { 10944 u8 fw_rev_minor[0x10]; 10945 u8 fw_rev_major[0x10]; 10946 10947 u8 cmd_interface_rev[0x10]; 10948 u8 fw_rev_subminor[0x10]; 10949 10950 u8 reserved_at_40[0x40]; 10951 10952 u8 cmdq_phy_addr_63_32[0x20]; 10953 10954 u8 cmdq_phy_addr_31_12[0x14]; 10955 u8 reserved_at_b4[0x2]; 10956 u8 nic_interface[0x2]; 10957 u8 log_cmdq_size[0x4]; 10958 u8 log_cmdq_stride[0x4]; 10959 10960 u8 command_doorbell_vector[0x20]; 10961 10962 u8 reserved_at_e0[0xf00]; 10963 10964 u8 initializing[0x1]; 10965 u8 reserved_at_fe1[0x4]; 10966 u8 nic_interface_supported[0x3]; 10967 u8 embedded_cpu[0x1]; 10968 u8 reserved_at_fe9[0x17]; 10969 10970 struct mlx5_ifc_health_buffer_bits health_buffer; 10971 10972 u8 no_dram_nic_offset[0x20]; 10973 10974 u8 reserved_at_1220[0x6e40]; 10975 10976 u8 reserved_at_8060[0x1f]; 10977 u8 clear_int[0x1]; 10978 10979 u8 health_syndrome[0x8]; 10980 u8 health_counter[0x18]; 10981 10982 u8 reserved_at_80a0[0x17fc0]; 10983 }; 10984 10985 struct mlx5_ifc_mtpps_reg_bits { 10986 u8 reserved_at_0[0xc]; 10987 u8 cap_number_of_pps_pins[0x4]; 10988 u8 reserved_at_10[0x4]; 10989 u8 cap_max_num_of_pps_in_pins[0x4]; 10990 u8 reserved_at_18[0x4]; 10991 u8 cap_max_num_of_pps_out_pins[0x4]; 10992 10993 u8 reserved_at_20[0x13]; 10994 u8 cap_log_min_npps_period[0x5]; 10995 u8 reserved_at_38[0x3]; 10996 u8 cap_log_min_out_pulse_duration_ns[0x5]; 10997 10998 u8 reserved_at_40[0x4]; 10999 u8 cap_pin_3_mode[0x4]; 11000 u8 reserved_at_48[0x4]; 11001 u8 cap_pin_2_mode[0x4]; 11002 u8 reserved_at_50[0x4]; 11003 u8 cap_pin_1_mode[0x4]; 11004 u8 reserved_at_58[0x4]; 11005 u8 cap_pin_0_mode[0x4]; 11006 11007 u8 reserved_at_60[0x4]; 11008 u8 cap_pin_7_mode[0x4]; 11009 u8 reserved_at_68[0x4]; 11010 u8 cap_pin_6_mode[0x4]; 11011 u8 reserved_at_70[0x4]; 11012 u8 cap_pin_5_mode[0x4]; 11013 u8 reserved_at_78[0x4]; 11014 u8 cap_pin_4_mode[0x4]; 11015 11016 u8 field_select[0x20]; 11017 u8 reserved_at_a0[0x20]; 11018 11019 u8 npps_period[0x40]; 11020 11021 u8 enable[0x1]; 11022 u8 reserved_at_101[0xb]; 11023 u8 pattern[0x4]; 11024 u8 reserved_at_110[0x4]; 11025 u8 pin_mode[0x4]; 11026 u8 pin[0x8]; 11027 11028 u8 reserved_at_120[0x2]; 11029 u8 out_pulse_duration_ns[0x1e]; 11030 11031 u8 time_stamp[0x40]; 11032 11033 u8 out_pulse_duration[0x10]; 11034 u8 out_periodic_adjustment[0x10]; 11035 u8 enhanced_out_periodic_adjustment[0x20]; 11036 11037 u8 reserved_at_1c0[0x20]; 11038 }; 11039 11040 struct mlx5_ifc_mtppse_reg_bits { 11041 u8 reserved_at_0[0x18]; 11042 u8 pin[0x8]; 11043 u8 event_arm[0x1]; 11044 u8 reserved_at_21[0x1b]; 11045 u8 event_generation_mode[0x4]; 11046 u8 reserved_at_40[0x40]; 11047 }; 11048 11049 struct mlx5_ifc_mcqs_reg_bits { 11050 u8 last_index_flag[0x1]; 11051 u8 reserved_at_1[0x7]; 11052 u8 fw_device[0x8]; 11053 u8 component_index[0x10]; 11054 11055 u8 reserved_at_20[0x10]; 11056 u8 identifier[0x10]; 11057 11058 u8 reserved_at_40[0x17]; 11059 u8 component_status[0x5]; 11060 u8 component_update_state[0x4]; 11061 11062 u8 last_update_state_changer_type[0x4]; 11063 u8 last_update_state_changer_host_id[0x4]; 11064 u8 reserved_at_68[0x18]; 11065 }; 11066 11067 struct mlx5_ifc_mcqi_cap_bits { 11068 u8 supported_info_bitmask[0x20]; 11069 11070 u8 component_size[0x20]; 11071 11072 u8 max_component_size[0x20]; 11073 11074 u8 log_mcda_word_size[0x4]; 11075 u8 reserved_at_64[0xc]; 11076 u8 mcda_max_write_size[0x10]; 11077 11078 u8 rd_en[0x1]; 11079 u8 reserved_at_81[0x1]; 11080 u8 match_chip_id[0x1]; 11081 u8 match_psid[0x1]; 11082 u8 check_user_timestamp[0x1]; 11083 u8 match_base_guid_mac[0x1]; 11084 u8 reserved_at_86[0x1a]; 11085 }; 11086 11087 struct mlx5_ifc_mcqi_version_bits { 11088 u8 reserved_at_0[0x2]; 11089 u8 build_time_valid[0x1]; 11090 u8 user_defined_time_valid[0x1]; 11091 u8 reserved_at_4[0x14]; 11092 u8 version_string_length[0x8]; 11093 11094 u8 version[0x20]; 11095 11096 u8 build_time[0x40]; 11097 11098 u8 user_defined_time[0x40]; 11099 11100 u8 build_tool_version[0x20]; 11101 11102 u8 reserved_at_e0[0x20]; 11103 11104 u8 version_string[92][0x8]; 11105 }; 11106 11107 struct mlx5_ifc_mcqi_activation_method_bits { 11108 u8 pending_server_ac_power_cycle[0x1]; 11109 u8 pending_server_dc_power_cycle[0x1]; 11110 u8 pending_server_reboot[0x1]; 11111 u8 pending_fw_reset[0x1]; 11112 u8 auto_activate[0x1]; 11113 u8 all_hosts_sync[0x1]; 11114 u8 device_hw_reset[0x1]; 11115 u8 reserved_at_7[0x19]; 11116 }; 11117 11118 union mlx5_ifc_mcqi_reg_data_bits { 11119 struct mlx5_ifc_mcqi_cap_bits mcqi_caps; 11120 struct mlx5_ifc_mcqi_version_bits mcqi_version; 11121 struct mlx5_ifc_mcqi_activation_method_bits mcqi_activation_mathod; 11122 }; 11123 11124 struct mlx5_ifc_mcqi_reg_bits { 11125 u8 read_pending_component[0x1]; 11126 u8 reserved_at_1[0xf]; 11127 u8 component_index[0x10]; 11128 11129 u8 reserved_at_20[0x20]; 11130 11131 u8 reserved_at_40[0x1b]; 11132 u8 info_type[0x5]; 11133 11134 u8 info_size[0x20]; 11135 11136 u8 offset[0x20]; 11137 11138 u8 reserved_at_a0[0x10]; 11139 u8 data_size[0x10]; 11140 11141 union mlx5_ifc_mcqi_reg_data_bits data[]; 11142 }; 11143 11144 struct mlx5_ifc_mcc_reg_bits { 11145 u8 reserved_at_0[0x4]; 11146 u8 time_elapsed_since_last_cmd[0xc]; 11147 u8 reserved_at_10[0x8]; 11148 u8 instruction[0x8]; 11149 11150 u8 reserved_at_20[0x10]; 11151 u8 component_index[0x10]; 11152 11153 u8 reserved_at_40[0x8]; 11154 u8 update_handle[0x18]; 11155 11156 u8 handle_owner_type[0x4]; 11157 u8 handle_owner_host_id[0x4]; 11158 u8 reserved_at_68[0x1]; 11159 u8 control_progress[0x7]; 11160 u8 error_code[0x8]; 11161 u8 reserved_at_78[0x4]; 11162 u8 control_state[0x4]; 11163 11164 u8 component_size[0x20]; 11165 11166 u8 reserved_at_a0[0x60]; 11167 }; 11168 11169 struct mlx5_ifc_mcda_reg_bits { 11170 u8 reserved_at_0[0x8]; 11171 u8 update_handle[0x18]; 11172 11173 u8 offset[0x20]; 11174 11175 u8 reserved_at_40[0x10]; 11176 u8 size[0x10]; 11177 11178 u8 reserved_at_60[0x20]; 11179 11180 u8 data[][0x20]; 11181 }; 11182 11183 enum { 11184 MLX5_MFRL_REG_RESET_STATE_IDLE = 0, 11185 MLX5_MFRL_REG_RESET_STATE_IN_NEGOTIATION = 1, 11186 MLX5_MFRL_REG_RESET_STATE_RESET_IN_PROGRESS = 2, 11187 MLX5_MFRL_REG_RESET_STATE_NEG_TIMEOUT = 3, 11188 MLX5_MFRL_REG_RESET_STATE_NACK = 4, 11189 MLX5_MFRL_REG_RESET_STATE_UNLOAD_TIMEOUT = 5, 11190 }; 11191 11192 enum { 11193 MLX5_MFRL_REG_RESET_TYPE_FULL_CHIP = BIT(0), 11194 MLX5_MFRL_REG_RESET_TYPE_NET_PORT_ALIVE = BIT(1), 11195 }; 11196 11197 enum { 11198 MLX5_MFRL_REG_RESET_LEVEL0 = BIT(0), 11199 MLX5_MFRL_REG_RESET_LEVEL3 = BIT(3), 11200 MLX5_MFRL_REG_RESET_LEVEL6 = BIT(6), 11201 }; 11202 11203 struct mlx5_ifc_mfrl_reg_bits { 11204 u8 reserved_at_0[0x20]; 11205 11206 u8 reserved_at_20[0x2]; 11207 u8 pci_sync_for_fw_update_start[0x1]; 11208 u8 pci_sync_for_fw_update_resp[0x2]; 11209 u8 rst_type_sel[0x3]; 11210 u8 reserved_at_28[0x4]; 11211 u8 reset_state[0x4]; 11212 u8 reset_type[0x8]; 11213 u8 reset_level[0x8]; 11214 }; 11215 11216 struct mlx5_ifc_mirc_reg_bits { 11217 u8 reserved_at_0[0x18]; 11218 u8 status_code[0x8]; 11219 11220 u8 reserved_at_20[0x20]; 11221 }; 11222 11223 struct mlx5_ifc_pddr_monitor_opcode_bits { 11224 u8 reserved_at_0[0x10]; 11225 u8 monitor_opcode[0x10]; 11226 }; 11227 11228 union mlx5_ifc_pddr_troubleshooting_page_status_opcode_auto_bits { 11229 struct mlx5_ifc_pddr_monitor_opcode_bits pddr_monitor_opcode; 11230 u8 reserved_at_0[0x20]; 11231 }; 11232 11233 enum { 11234 /* Monitor opcodes */ 11235 MLX5_PDDR_REG_TRBLSH_GROUP_OPCODE_MONITOR = 0x0, 11236 }; 11237 11238 struct mlx5_ifc_pddr_troubleshooting_page_bits { 11239 u8 reserved_at_0[0x10]; 11240 u8 group_opcode[0x10]; 11241 11242 union mlx5_ifc_pddr_troubleshooting_page_status_opcode_auto_bits status_opcode; 11243 11244 u8 reserved_at_40[0x20]; 11245 11246 u8 status_message[59][0x20]; 11247 }; 11248 11249 union mlx5_ifc_pddr_reg_page_data_auto_bits { 11250 struct mlx5_ifc_pddr_troubleshooting_page_bits pddr_troubleshooting_page; 11251 u8 reserved_at_0[0x7c0]; 11252 }; 11253 11254 enum { 11255 MLX5_PDDR_REG_PAGE_SELECT_TROUBLESHOOTING_INFO_PAGE = 0x1, 11256 }; 11257 11258 struct mlx5_ifc_pddr_reg_bits { 11259 u8 reserved_at_0[0x8]; 11260 u8 local_port[0x8]; 11261 u8 pnat[0x2]; 11262 u8 reserved_at_12[0xe]; 11263 11264 u8 reserved_at_20[0x18]; 11265 u8 page_select[0x8]; 11266 11267 union mlx5_ifc_pddr_reg_page_data_auto_bits page_data; 11268 }; 11269 11270 struct mlx5_ifc_mrtc_reg_bits { 11271 u8 time_synced[0x1]; 11272 u8 reserved_at_1[0x1f]; 11273 11274 u8 reserved_at_20[0x20]; 11275 11276 u8 time_h[0x20]; 11277 11278 u8 time_l[0x20]; 11279 }; 11280 11281 struct mlx5_ifc_mtcap_reg_bits { 11282 u8 reserved_at_0[0x19]; 11283 u8 sensor_count[0x7]; 11284 11285 u8 reserved_at_20[0x20]; 11286 11287 u8 sensor_map[0x40]; 11288 }; 11289 11290 struct mlx5_ifc_mtmp_reg_bits { 11291 u8 reserved_at_0[0x14]; 11292 u8 sensor_index[0xc]; 11293 11294 u8 reserved_at_20[0x10]; 11295 u8 temperature[0x10]; 11296 11297 u8 mte[0x1]; 11298 u8 mtr[0x1]; 11299 u8 reserved_at_42[0xe]; 11300 u8 max_temperature[0x10]; 11301 11302 u8 tee[0x2]; 11303 u8 reserved_at_62[0xe]; 11304 u8 temp_threshold_hi[0x10]; 11305 11306 u8 reserved_at_80[0x10]; 11307 u8 temp_threshold_lo[0x10]; 11308 11309 u8 reserved_at_a0[0x20]; 11310 11311 u8 sensor_name_hi[0x20]; 11312 u8 sensor_name_lo[0x20]; 11313 }; 11314 11315 struct mlx5_ifc_mtptm_reg_bits { 11316 u8 reserved_at_0[0x10]; 11317 u8 psta[0x1]; 11318 u8 reserved_at_11[0xf]; 11319 11320 u8 reserved_at_20[0x60]; 11321 }; 11322 11323 enum { 11324 MLX5_MTCTR_REQUEST_NOP = 0x0, 11325 MLX5_MTCTR_REQUEST_PTM_ROOT_CLOCK = 0x1, 11326 MLX5_MTCTR_REQUEST_FREE_RUNNING_COUNTER = 0x2, 11327 MLX5_MTCTR_REQUEST_REAL_TIME_CLOCK = 0x3, 11328 }; 11329 11330 struct mlx5_ifc_mtctr_reg_bits { 11331 u8 first_clock_timestamp_request[0x8]; 11332 u8 second_clock_timestamp_request[0x8]; 11333 u8 reserved_at_10[0x10]; 11334 11335 u8 first_clock_valid[0x1]; 11336 u8 second_clock_valid[0x1]; 11337 u8 reserved_at_22[0x1e]; 11338 11339 u8 first_clock_timestamp[0x40]; 11340 u8 second_clock_timestamp[0x40]; 11341 }; 11342 11343 union mlx5_ifc_ports_control_registers_document_bits { 11344 struct mlx5_ifc_bufferx_reg_bits bufferx_reg; 11345 struct mlx5_ifc_eth_2819_cntrs_grp_data_layout_bits eth_2819_cntrs_grp_data_layout; 11346 struct mlx5_ifc_eth_2863_cntrs_grp_data_layout_bits eth_2863_cntrs_grp_data_layout; 11347 struct mlx5_ifc_eth_3635_cntrs_grp_data_layout_bits eth_3635_cntrs_grp_data_layout; 11348 struct mlx5_ifc_eth_802_3_cntrs_grp_data_layout_bits eth_802_3_cntrs_grp_data_layout; 11349 struct mlx5_ifc_eth_extended_cntrs_grp_data_layout_bits eth_extended_cntrs_grp_data_layout; 11350 struct mlx5_ifc_eth_per_prio_grp_data_layout_bits eth_per_prio_grp_data_layout; 11351 struct mlx5_ifc_eth_per_tc_prio_grp_data_layout_bits eth_per_tc_prio_grp_data_layout; 11352 struct mlx5_ifc_eth_per_tc_congest_prio_grp_data_layout_bits eth_per_tc_congest_prio_grp_data_layout; 11353 struct mlx5_ifc_lane_2_module_mapping_bits lane_2_module_mapping; 11354 struct mlx5_ifc_pamp_reg_bits pamp_reg; 11355 struct mlx5_ifc_paos_reg_bits paos_reg; 11356 struct mlx5_ifc_pcap_reg_bits pcap_reg; 11357 struct mlx5_ifc_pddr_monitor_opcode_bits pddr_monitor_opcode; 11358 struct mlx5_ifc_pddr_reg_bits pddr_reg; 11359 struct mlx5_ifc_pddr_troubleshooting_page_bits pddr_troubleshooting_page; 11360 struct mlx5_ifc_peir_reg_bits peir_reg; 11361 struct mlx5_ifc_pelc_reg_bits pelc_reg; 11362 struct mlx5_ifc_pfcc_reg_bits pfcc_reg; 11363 struct mlx5_ifc_ib_port_cntrs_grp_data_layout_bits ib_port_cntrs_grp_data_layout; 11364 struct mlx5_ifc_phys_layer_cntrs_bits phys_layer_cntrs; 11365 struct mlx5_ifc_pifr_reg_bits pifr_reg; 11366 struct mlx5_ifc_pipg_reg_bits pipg_reg; 11367 struct mlx5_ifc_plbf_reg_bits plbf_reg; 11368 struct mlx5_ifc_plib_reg_bits plib_reg; 11369 struct mlx5_ifc_plpc_reg_bits plpc_reg; 11370 struct mlx5_ifc_pmaos_reg_bits pmaos_reg; 11371 struct mlx5_ifc_pmlp_reg_bits pmlp_reg; 11372 struct mlx5_ifc_pmlpn_reg_bits pmlpn_reg; 11373 struct mlx5_ifc_pmpc_reg_bits pmpc_reg; 11374 struct mlx5_ifc_pmpe_reg_bits pmpe_reg; 11375 struct mlx5_ifc_pmpr_reg_bits pmpr_reg; 11376 struct mlx5_ifc_pmtu_reg_bits pmtu_reg; 11377 struct mlx5_ifc_ppad_reg_bits ppad_reg; 11378 struct mlx5_ifc_ppcnt_reg_bits ppcnt_reg; 11379 struct mlx5_ifc_mpein_reg_bits mpein_reg; 11380 struct mlx5_ifc_mpcnt_reg_bits mpcnt_reg; 11381 struct mlx5_ifc_pplm_reg_bits pplm_reg; 11382 struct mlx5_ifc_pplr_reg_bits pplr_reg; 11383 struct mlx5_ifc_ppsc_reg_bits ppsc_reg; 11384 struct mlx5_ifc_pqdr_reg_bits pqdr_reg; 11385 struct mlx5_ifc_pspa_reg_bits pspa_reg; 11386 struct mlx5_ifc_ptas_reg_bits ptas_reg; 11387 struct mlx5_ifc_ptys_reg_bits ptys_reg; 11388 struct mlx5_ifc_mlcr_reg_bits mlcr_reg; 11389 struct mlx5_ifc_pude_reg_bits pude_reg; 11390 struct mlx5_ifc_pvlc_reg_bits pvlc_reg; 11391 struct mlx5_ifc_slrg_reg_bits slrg_reg; 11392 struct mlx5_ifc_sltp_reg_bits sltp_reg; 11393 struct mlx5_ifc_mtpps_reg_bits mtpps_reg; 11394 struct mlx5_ifc_mtppse_reg_bits mtppse_reg; 11395 struct mlx5_ifc_fpga_access_reg_bits fpga_access_reg; 11396 struct mlx5_ifc_fpga_ctrl_bits fpga_ctrl_bits; 11397 struct mlx5_ifc_fpga_cap_bits fpga_cap_bits; 11398 struct mlx5_ifc_mcqi_reg_bits mcqi_reg; 11399 struct mlx5_ifc_mcc_reg_bits mcc_reg; 11400 struct mlx5_ifc_mcda_reg_bits mcda_reg; 11401 struct mlx5_ifc_mirc_reg_bits mirc_reg; 11402 struct mlx5_ifc_mfrl_reg_bits mfrl_reg; 11403 struct mlx5_ifc_mtutc_reg_bits mtutc_reg; 11404 struct mlx5_ifc_mrtc_reg_bits mrtc_reg; 11405 struct mlx5_ifc_mtcap_reg_bits mtcap_reg; 11406 struct mlx5_ifc_mtmp_reg_bits mtmp_reg; 11407 struct mlx5_ifc_mtptm_reg_bits mtptm_reg; 11408 struct mlx5_ifc_mtctr_reg_bits mtctr_reg; 11409 u8 reserved_at_0[0x60e0]; 11410 }; 11411 11412 union mlx5_ifc_debug_enhancements_document_bits { 11413 struct mlx5_ifc_health_buffer_bits health_buffer; 11414 u8 reserved_at_0[0x200]; 11415 }; 11416 11417 union mlx5_ifc_uplink_pci_interface_document_bits { 11418 struct mlx5_ifc_initial_seg_bits initial_seg; 11419 u8 reserved_at_0[0x20060]; 11420 }; 11421 11422 struct mlx5_ifc_set_flow_table_root_out_bits { 11423 u8 status[0x8]; 11424 u8 reserved_at_8[0x18]; 11425 11426 u8 syndrome[0x20]; 11427 11428 u8 reserved_at_40[0x40]; 11429 }; 11430 11431 struct mlx5_ifc_set_flow_table_root_in_bits { 11432 u8 opcode[0x10]; 11433 u8 reserved_at_10[0x10]; 11434 11435 u8 reserved_at_20[0x10]; 11436 u8 op_mod[0x10]; 11437 11438 u8 other_vport[0x1]; 11439 u8 reserved_at_41[0xf]; 11440 u8 vport_number[0x10]; 11441 11442 u8 reserved_at_60[0x20]; 11443 11444 u8 table_type[0x8]; 11445 u8 reserved_at_88[0x7]; 11446 u8 table_of_other_vport[0x1]; 11447 u8 table_vport_number[0x10]; 11448 11449 u8 reserved_at_a0[0x8]; 11450 u8 table_id[0x18]; 11451 11452 u8 reserved_at_c0[0x8]; 11453 u8 underlay_qpn[0x18]; 11454 u8 table_eswitch_owner_vhca_id_valid[0x1]; 11455 u8 reserved_at_e1[0xf]; 11456 u8 table_eswitch_owner_vhca_id[0x10]; 11457 u8 reserved_at_100[0x100]; 11458 }; 11459 11460 enum { 11461 MLX5_MODIFY_FLOW_TABLE_MISS_TABLE_ID = (1UL << 0), 11462 MLX5_MODIFY_FLOW_TABLE_LAG_NEXT_TABLE_ID = (1UL << 15), 11463 }; 11464 11465 struct mlx5_ifc_modify_flow_table_out_bits { 11466 u8 status[0x8]; 11467 u8 reserved_at_8[0x18]; 11468 11469 u8 syndrome[0x20]; 11470 11471 u8 reserved_at_40[0x40]; 11472 }; 11473 11474 struct mlx5_ifc_modify_flow_table_in_bits { 11475 u8 opcode[0x10]; 11476 u8 reserved_at_10[0x10]; 11477 11478 u8 reserved_at_20[0x10]; 11479 u8 op_mod[0x10]; 11480 11481 u8 other_vport[0x1]; 11482 u8 reserved_at_41[0xf]; 11483 u8 vport_number[0x10]; 11484 11485 u8 reserved_at_60[0x10]; 11486 u8 modify_field_select[0x10]; 11487 11488 u8 table_type[0x8]; 11489 u8 reserved_at_88[0x18]; 11490 11491 u8 reserved_at_a0[0x8]; 11492 u8 table_id[0x18]; 11493 11494 struct mlx5_ifc_flow_table_context_bits flow_table_context; 11495 }; 11496 11497 struct mlx5_ifc_ets_tcn_config_reg_bits { 11498 u8 g[0x1]; 11499 u8 b[0x1]; 11500 u8 r[0x1]; 11501 u8 reserved_at_3[0x9]; 11502 u8 group[0x4]; 11503 u8 reserved_at_10[0x9]; 11504 u8 bw_allocation[0x7]; 11505 11506 u8 reserved_at_20[0xc]; 11507 u8 max_bw_units[0x4]; 11508 u8 reserved_at_30[0x8]; 11509 u8 max_bw_value[0x8]; 11510 }; 11511 11512 struct mlx5_ifc_ets_global_config_reg_bits { 11513 u8 reserved_at_0[0x2]; 11514 u8 r[0x1]; 11515 u8 reserved_at_3[0x1d]; 11516 11517 u8 reserved_at_20[0xc]; 11518 u8 max_bw_units[0x4]; 11519 u8 reserved_at_30[0x8]; 11520 u8 max_bw_value[0x8]; 11521 }; 11522 11523 struct mlx5_ifc_qetc_reg_bits { 11524 u8 reserved_at_0[0x8]; 11525 u8 port_number[0x8]; 11526 u8 reserved_at_10[0x30]; 11527 11528 struct mlx5_ifc_ets_tcn_config_reg_bits tc_configuration[0x8]; 11529 struct mlx5_ifc_ets_global_config_reg_bits global_configuration; 11530 }; 11531 11532 struct mlx5_ifc_qpdpm_dscp_reg_bits { 11533 u8 e[0x1]; 11534 u8 reserved_at_01[0x0b]; 11535 u8 prio[0x04]; 11536 }; 11537 11538 struct mlx5_ifc_qpdpm_reg_bits { 11539 u8 reserved_at_0[0x8]; 11540 u8 local_port[0x8]; 11541 u8 reserved_at_10[0x10]; 11542 struct mlx5_ifc_qpdpm_dscp_reg_bits dscp[64]; 11543 }; 11544 11545 struct mlx5_ifc_qpts_reg_bits { 11546 u8 reserved_at_0[0x8]; 11547 u8 local_port[0x8]; 11548 u8 reserved_at_10[0x2d]; 11549 u8 trust_state[0x3]; 11550 }; 11551 11552 struct mlx5_ifc_pptb_reg_bits { 11553 u8 reserved_at_0[0x2]; 11554 u8 mm[0x2]; 11555 u8 reserved_at_4[0x4]; 11556 u8 local_port[0x8]; 11557 u8 reserved_at_10[0x6]; 11558 u8 cm[0x1]; 11559 u8 um[0x1]; 11560 u8 pm[0x8]; 11561 11562 u8 prio_x_buff[0x20]; 11563 11564 u8 pm_msb[0x8]; 11565 u8 reserved_at_48[0x10]; 11566 u8 ctrl_buff[0x4]; 11567 u8 untagged_buff[0x4]; 11568 }; 11569 11570 struct mlx5_ifc_sbcam_reg_bits { 11571 u8 reserved_at_0[0x8]; 11572 u8 feature_group[0x8]; 11573 u8 reserved_at_10[0x8]; 11574 u8 access_reg_group[0x8]; 11575 11576 u8 reserved_at_20[0x20]; 11577 11578 u8 sb_access_reg_cap_mask[4][0x20]; 11579 11580 u8 reserved_at_c0[0x80]; 11581 11582 u8 sb_feature_cap_mask[4][0x20]; 11583 11584 u8 reserved_at_1c0[0x40]; 11585 11586 u8 cap_total_buffer_size[0x20]; 11587 11588 u8 cap_cell_size[0x10]; 11589 u8 cap_max_pg_buffers[0x8]; 11590 u8 cap_num_pool_supported[0x8]; 11591 11592 u8 reserved_at_240[0x8]; 11593 u8 cap_sbsr_stat_size[0x8]; 11594 u8 cap_max_tclass_data[0x8]; 11595 u8 cap_max_cpu_ingress_tclass_sb[0x8]; 11596 }; 11597 11598 struct mlx5_ifc_pbmc_reg_bits { 11599 u8 reserved_at_0[0x8]; 11600 u8 local_port[0x8]; 11601 u8 reserved_at_10[0x10]; 11602 11603 u8 xoff_timer_value[0x10]; 11604 u8 xoff_refresh[0x10]; 11605 11606 u8 reserved_at_40[0x9]; 11607 u8 fullness_threshold[0x7]; 11608 u8 port_buffer_size[0x10]; 11609 11610 struct mlx5_ifc_bufferx_reg_bits buffer[10]; 11611 11612 u8 reserved_at_2e0[0x80]; 11613 }; 11614 11615 struct mlx5_ifc_sbpr_reg_bits { 11616 u8 desc[0x1]; 11617 u8 snap[0x1]; 11618 u8 reserved_at_2[0x4]; 11619 u8 dir[0x2]; 11620 u8 reserved_at_8[0x14]; 11621 u8 pool[0x4]; 11622 11623 u8 infi_size[0x1]; 11624 u8 reserved_at_21[0x7]; 11625 u8 size[0x18]; 11626 11627 u8 reserved_at_40[0x1c]; 11628 u8 mode[0x4]; 11629 11630 u8 reserved_at_60[0x8]; 11631 u8 buff_occupancy[0x18]; 11632 11633 u8 clr[0x1]; 11634 u8 reserved_at_81[0x7]; 11635 u8 max_buff_occupancy[0x18]; 11636 11637 u8 reserved_at_a0[0x8]; 11638 u8 ext_buff_occupancy[0x18]; 11639 }; 11640 11641 struct mlx5_ifc_sbcm_reg_bits { 11642 u8 desc[0x1]; 11643 u8 snap[0x1]; 11644 u8 reserved_at_2[0x6]; 11645 u8 local_port[0x8]; 11646 u8 pnat[0x2]; 11647 u8 pg_buff[0x6]; 11648 u8 reserved_at_18[0x6]; 11649 u8 dir[0x2]; 11650 11651 u8 reserved_at_20[0x1f]; 11652 u8 exc[0x1]; 11653 11654 u8 reserved_at_40[0x40]; 11655 11656 u8 reserved_at_80[0x8]; 11657 u8 buff_occupancy[0x18]; 11658 11659 u8 clr[0x1]; 11660 u8 reserved_at_a1[0x7]; 11661 u8 max_buff_occupancy[0x18]; 11662 11663 u8 reserved_at_c0[0x8]; 11664 u8 min_buff[0x18]; 11665 11666 u8 infi_max[0x1]; 11667 u8 reserved_at_e1[0x7]; 11668 u8 max_buff[0x18]; 11669 11670 u8 reserved_at_100[0x20]; 11671 11672 u8 reserved_at_120[0x1c]; 11673 u8 pool[0x4]; 11674 }; 11675 11676 struct mlx5_ifc_qtct_reg_bits { 11677 u8 reserved_at_0[0x8]; 11678 u8 port_number[0x8]; 11679 u8 reserved_at_10[0xd]; 11680 u8 prio[0x3]; 11681 11682 u8 reserved_at_20[0x1d]; 11683 u8 tclass[0x3]; 11684 }; 11685 11686 struct mlx5_ifc_mcia_reg_bits { 11687 u8 l[0x1]; 11688 u8 reserved_at_1[0x7]; 11689 u8 module[0x8]; 11690 u8 reserved_at_10[0x8]; 11691 u8 status[0x8]; 11692 11693 u8 i2c_device_address[0x8]; 11694 u8 page_number[0x8]; 11695 u8 device_address[0x10]; 11696 11697 u8 reserved_at_40[0x10]; 11698 u8 size[0x10]; 11699 11700 u8 reserved_at_60[0x20]; 11701 11702 u8 dword_0[0x20]; 11703 u8 dword_1[0x20]; 11704 u8 dword_2[0x20]; 11705 u8 dword_3[0x20]; 11706 u8 dword_4[0x20]; 11707 u8 dword_5[0x20]; 11708 u8 dword_6[0x20]; 11709 u8 dword_7[0x20]; 11710 u8 dword_8[0x20]; 11711 u8 dword_9[0x20]; 11712 u8 dword_10[0x20]; 11713 u8 dword_11[0x20]; 11714 }; 11715 11716 struct mlx5_ifc_dcbx_param_bits { 11717 u8 dcbx_cee_cap[0x1]; 11718 u8 dcbx_ieee_cap[0x1]; 11719 u8 dcbx_standby_cap[0x1]; 11720 u8 reserved_at_3[0x5]; 11721 u8 port_number[0x8]; 11722 u8 reserved_at_10[0xa]; 11723 u8 max_application_table_size[6]; 11724 u8 reserved_at_20[0x15]; 11725 u8 version_oper[0x3]; 11726 u8 reserved_at_38[5]; 11727 u8 version_admin[0x3]; 11728 u8 willing_admin[0x1]; 11729 u8 reserved_at_41[0x3]; 11730 u8 pfc_cap_oper[0x4]; 11731 u8 reserved_at_48[0x4]; 11732 u8 pfc_cap_admin[0x4]; 11733 u8 reserved_at_50[0x4]; 11734 u8 num_of_tc_oper[0x4]; 11735 u8 reserved_at_58[0x4]; 11736 u8 num_of_tc_admin[0x4]; 11737 u8 remote_willing[0x1]; 11738 u8 reserved_at_61[3]; 11739 u8 remote_pfc_cap[4]; 11740 u8 reserved_at_68[0x14]; 11741 u8 remote_num_of_tc[0x4]; 11742 u8 reserved_at_80[0x18]; 11743 u8 error[0x8]; 11744 u8 reserved_at_a0[0x160]; 11745 }; 11746 11747 enum { 11748 MLX5_LAG_PORT_SELECT_MODE_QUEUE_AFFINITY = 0, 11749 MLX5_LAG_PORT_SELECT_MODE_PORT_SELECT_FT = 1, 11750 MLX5_LAG_PORT_SELECT_MODE_PORT_SELECT_MPESW = 2, 11751 }; 11752 11753 struct mlx5_ifc_lagc_bits { 11754 u8 fdb_selection_mode[0x1]; 11755 u8 reserved_at_1[0x14]; 11756 u8 port_select_mode[0x3]; 11757 u8 reserved_at_18[0x5]; 11758 u8 lag_state[0x3]; 11759 11760 u8 reserved_at_20[0xc]; 11761 u8 active_port[0x4]; 11762 u8 reserved_at_30[0x4]; 11763 u8 tx_remap_affinity_2[0x4]; 11764 u8 reserved_at_38[0x4]; 11765 u8 tx_remap_affinity_1[0x4]; 11766 }; 11767 11768 struct mlx5_ifc_create_lag_out_bits { 11769 u8 status[0x8]; 11770 u8 reserved_at_8[0x18]; 11771 11772 u8 syndrome[0x20]; 11773 11774 u8 reserved_at_40[0x40]; 11775 }; 11776 11777 struct mlx5_ifc_create_lag_in_bits { 11778 u8 opcode[0x10]; 11779 u8 reserved_at_10[0x10]; 11780 11781 u8 reserved_at_20[0x10]; 11782 u8 op_mod[0x10]; 11783 11784 struct mlx5_ifc_lagc_bits ctx; 11785 }; 11786 11787 struct mlx5_ifc_modify_lag_out_bits { 11788 u8 status[0x8]; 11789 u8 reserved_at_8[0x18]; 11790 11791 u8 syndrome[0x20]; 11792 11793 u8 reserved_at_40[0x40]; 11794 }; 11795 11796 struct mlx5_ifc_modify_lag_in_bits { 11797 u8 opcode[0x10]; 11798 u8 reserved_at_10[0x10]; 11799 11800 u8 reserved_at_20[0x10]; 11801 u8 op_mod[0x10]; 11802 11803 u8 reserved_at_40[0x20]; 11804 u8 field_select[0x20]; 11805 11806 struct mlx5_ifc_lagc_bits ctx; 11807 }; 11808 11809 struct mlx5_ifc_query_lag_out_bits { 11810 u8 status[0x8]; 11811 u8 reserved_at_8[0x18]; 11812 11813 u8 syndrome[0x20]; 11814 11815 struct mlx5_ifc_lagc_bits ctx; 11816 }; 11817 11818 struct mlx5_ifc_query_lag_in_bits { 11819 u8 opcode[0x10]; 11820 u8 reserved_at_10[0x10]; 11821 11822 u8 reserved_at_20[0x10]; 11823 u8 op_mod[0x10]; 11824 11825 u8 reserved_at_40[0x40]; 11826 }; 11827 11828 struct mlx5_ifc_destroy_lag_out_bits { 11829 u8 status[0x8]; 11830 u8 reserved_at_8[0x18]; 11831 11832 u8 syndrome[0x20]; 11833 11834 u8 reserved_at_40[0x40]; 11835 }; 11836 11837 struct mlx5_ifc_destroy_lag_in_bits { 11838 u8 opcode[0x10]; 11839 u8 reserved_at_10[0x10]; 11840 11841 u8 reserved_at_20[0x10]; 11842 u8 op_mod[0x10]; 11843 11844 u8 reserved_at_40[0x40]; 11845 }; 11846 11847 struct mlx5_ifc_create_vport_lag_out_bits { 11848 u8 status[0x8]; 11849 u8 reserved_at_8[0x18]; 11850 11851 u8 syndrome[0x20]; 11852 11853 u8 reserved_at_40[0x40]; 11854 }; 11855 11856 struct mlx5_ifc_create_vport_lag_in_bits { 11857 u8 opcode[0x10]; 11858 u8 reserved_at_10[0x10]; 11859 11860 u8 reserved_at_20[0x10]; 11861 u8 op_mod[0x10]; 11862 11863 u8 reserved_at_40[0x40]; 11864 }; 11865 11866 struct mlx5_ifc_destroy_vport_lag_out_bits { 11867 u8 status[0x8]; 11868 u8 reserved_at_8[0x18]; 11869 11870 u8 syndrome[0x20]; 11871 11872 u8 reserved_at_40[0x40]; 11873 }; 11874 11875 struct mlx5_ifc_destroy_vport_lag_in_bits { 11876 u8 opcode[0x10]; 11877 u8 reserved_at_10[0x10]; 11878 11879 u8 reserved_at_20[0x10]; 11880 u8 op_mod[0x10]; 11881 11882 u8 reserved_at_40[0x40]; 11883 }; 11884 11885 enum { 11886 MLX5_MODIFY_MEMIC_OP_MOD_ALLOC, 11887 MLX5_MODIFY_MEMIC_OP_MOD_DEALLOC, 11888 }; 11889 11890 struct mlx5_ifc_modify_memic_in_bits { 11891 u8 opcode[0x10]; 11892 u8 uid[0x10]; 11893 11894 u8 reserved_at_20[0x10]; 11895 u8 op_mod[0x10]; 11896 11897 u8 reserved_at_40[0x20]; 11898 11899 u8 reserved_at_60[0x18]; 11900 u8 memic_operation_type[0x8]; 11901 11902 u8 memic_start_addr[0x40]; 11903 11904 u8 reserved_at_c0[0x140]; 11905 }; 11906 11907 struct mlx5_ifc_modify_memic_out_bits { 11908 u8 status[0x8]; 11909 u8 reserved_at_8[0x18]; 11910 11911 u8 syndrome[0x20]; 11912 11913 u8 reserved_at_40[0x40]; 11914 11915 u8 memic_operation_addr[0x40]; 11916 11917 u8 reserved_at_c0[0x140]; 11918 }; 11919 11920 struct mlx5_ifc_alloc_memic_in_bits { 11921 u8 opcode[0x10]; 11922 u8 reserved_at_10[0x10]; 11923 11924 u8 reserved_at_20[0x10]; 11925 u8 op_mod[0x10]; 11926 11927 u8 reserved_at_30[0x20]; 11928 11929 u8 reserved_at_40[0x18]; 11930 u8 log_memic_addr_alignment[0x8]; 11931 11932 u8 range_start_addr[0x40]; 11933 11934 u8 range_size[0x20]; 11935 11936 u8 memic_size[0x20]; 11937 }; 11938 11939 struct mlx5_ifc_alloc_memic_out_bits { 11940 u8 status[0x8]; 11941 u8 reserved_at_8[0x18]; 11942 11943 u8 syndrome[0x20]; 11944 11945 u8 memic_start_addr[0x40]; 11946 }; 11947 11948 struct mlx5_ifc_dealloc_memic_in_bits { 11949 u8 opcode[0x10]; 11950 u8 reserved_at_10[0x10]; 11951 11952 u8 reserved_at_20[0x10]; 11953 u8 op_mod[0x10]; 11954 11955 u8 reserved_at_40[0x40]; 11956 11957 u8 memic_start_addr[0x40]; 11958 11959 u8 memic_size[0x20]; 11960 11961 u8 reserved_at_e0[0x20]; 11962 }; 11963 11964 struct mlx5_ifc_dealloc_memic_out_bits { 11965 u8 status[0x8]; 11966 u8 reserved_at_8[0x18]; 11967 11968 u8 syndrome[0x20]; 11969 11970 u8 reserved_at_40[0x40]; 11971 }; 11972 11973 struct mlx5_ifc_umem_bits { 11974 u8 reserved_at_0[0x80]; 11975 11976 u8 ats[0x1]; 11977 u8 reserved_at_81[0x1a]; 11978 u8 log_page_size[0x5]; 11979 11980 u8 page_offset[0x20]; 11981 11982 u8 num_of_mtt[0x40]; 11983 11984 struct mlx5_ifc_mtt_bits mtt[]; 11985 }; 11986 11987 struct mlx5_ifc_uctx_bits { 11988 u8 cap[0x20]; 11989 11990 u8 reserved_at_20[0x160]; 11991 }; 11992 11993 struct mlx5_ifc_sw_icm_bits { 11994 u8 modify_field_select[0x40]; 11995 11996 u8 reserved_at_40[0x18]; 11997 u8 log_sw_icm_size[0x8]; 11998 11999 u8 reserved_at_60[0x20]; 12000 12001 u8 sw_icm_start_addr[0x40]; 12002 12003 u8 reserved_at_c0[0x140]; 12004 }; 12005 12006 struct mlx5_ifc_geneve_tlv_option_bits { 12007 u8 modify_field_select[0x40]; 12008 12009 u8 reserved_at_40[0x18]; 12010 u8 geneve_option_fte_index[0x8]; 12011 12012 u8 option_class[0x10]; 12013 u8 option_type[0x8]; 12014 u8 reserved_at_78[0x3]; 12015 u8 option_data_length[0x5]; 12016 12017 u8 reserved_at_80[0x180]; 12018 }; 12019 12020 struct mlx5_ifc_create_umem_in_bits { 12021 u8 opcode[0x10]; 12022 u8 uid[0x10]; 12023 12024 u8 reserved_at_20[0x10]; 12025 u8 op_mod[0x10]; 12026 12027 u8 reserved_at_40[0x40]; 12028 12029 struct mlx5_ifc_umem_bits umem; 12030 }; 12031 12032 struct mlx5_ifc_create_umem_out_bits { 12033 u8 status[0x8]; 12034 u8 reserved_at_8[0x18]; 12035 12036 u8 syndrome[0x20]; 12037 12038 u8 reserved_at_40[0x8]; 12039 u8 umem_id[0x18]; 12040 12041 u8 reserved_at_60[0x20]; 12042 }; 12043 12044 struct mlx5_ifc_destroy_umem_in_bits { 12045 u8 opcode[0x10]; 12046 u8 uid[0x10]; 12047 12048 u8 reserved_at_20[0x10]; 12049 u8 op_mod[0x10]; 12050 12051 u8 reserved_at_40[0x8]; 12052 u8 umem_id[0x18]; 12053 12054 u8 reserved_at_60[0x20]; 12055 }; 12056 12057 struct mlx5_ifc_destroy_umem_out_bits { 12058 u8 status[0x8]; 12059 u8 reserved_at_8[0x18]; 12060 12061 u8 syndrome[0x20]; 12062 12063 u8 reserved_at_40[0x40]; 12064 }; 12065 12066 struct mlx5_ifc_create_uctx_in_bits { 12067 u8 opcode[0x10]; 12068 u8 reserved_at_10[0x10]; 12069 12070 u8 reserved_at_20[0x10]; 12071 u8 op_mod[0x10]; 12072 12073 u8 reserved_at_40[0x40]; 12074 12075 struct mlx5_ifc_uctx_bits uctx; 12076 }; 12077 12078 struct mlx5_ifc_create_uctx_out_bits { 12079 u8 status[0x8]; 12080 u8 reserved_at_8[0x18]; 12081 12082 u8 syndrome[0x20]; 12083 12084 u8 reserved_at_40[0x10]; 12085 u8 uid[0x10]; 12086 12087 u8 reserved_at_60[0x20]; 12088 }; 12089 12090 struct mlx5_ifc_destroy_uctx_in_bits { 12091 u8 opcode[0x10]; 12092 u8 reserved_at_10[0x10]; 12093 12094 u8 reserved_at_20[0x10]; 12095 u8 op_mod[0x10]; 12096 12097 u8 reserved_at_40[0x10]; 12098 u8 uid[0x10]; 12099 12100 u8 reserved_at_60[0x20]; 12101 }; 12102 12103 struct mlx5_ifc_destroy_uctx_out_bits { 12104 u8 status[0x8]; 12105 u8 reserved_at_8[0x18]; 12106 12107 u8 syndrome[0x20]; 12108 12109 u8 reserved_at_40[0x40]; 12110 }; 12111 12112 struct mlx5_ifc_create_sw_icm_in_bits { 12113 struct mlx5_ifc_general_obj_in_cmd_hdr_bits hdr; 12114 struct mlx5_ifc_sw_icm_bits sw_icm; 12115 }; 12116 12117 struct mlx5_ifc_create_geneve_tlv_option_in_bits { 12118 struct mlx5_ifc_general_obj_in_cmd_hdr_bits hdr; 12119 struct mlx5_ifc_geneve_tlv_option_bits geneve_tlv_opt; 12120 }; 12121 12122 struct mlx5_ifc_mtrc_string_db_param_bits { 12123 u8 string_db_base_address[0x20]; 12124 12125 u8 reserved_at_20[0x8]; 12126 u8 string_db_size[0x18]; 12127 }; 12128 12129 struct mlx5_ifc_mtrc_cap_bits { 12130 u8 trace_owner[0x1]; 12131 u8 trace_to_memory[0x1]; 12132 u8 reserved_at_2[0x4]; 12133 u8 trc_ver[0x2]; 12134 u8 reserved_at_8[0x14]; 12135 u8 num_string_db[0x4]; 12136 12137 u8 first_string_trace[0x8]; 12138 u8 num_string_trace[0x8]; 12139 u8 reserved_at_30[0x28]; 12140 12141 u8 log_max_trace_buffer_size[0x8]; 12142 12143 u8 reserved_at_60[0x20]; 12144 12145 struct mlx5_ifc_mtrc_string_db_param_bits string_db_param[8]; 12146 12147 u8 reserved_at_280[0x180]; 12148 }; 12149 12150 struct mlx5_ifc_mtrc_conf_bits { 12151 u8 reserved_at_0[0x1c]; 12152 u8 trace_mode[0x4]; 12153 u8 reserved_at_20[0x18]; 12154 u8 log_trace_buffer_size[0x8]; 12155 u8 trace_mkey[0x20]; 12156 u8 reserved_at_60[0x3a0]; 12157 }; 12158 12159 struct mlx5_ifc_mtrc_stdb_bits { 12160 u8 string_db_index[0x4]; 12161 u8 reserved_at_4[0x4]; 12162 u8 read_size[0x18]; 12163 u8 start_offset[0x20]; 12164 u8 string_db_data[]; 12165 }; 12166 12167 struct mlx5_ifc_mtrc_ctrl_bits { 12168 u8 trace_status[0x2]; 12169 u8 reserved_at_2[0x2]; 12170 u8 arm_event[0x1]; 12171 u8 reserved_at_5[0xb]; 12172 u8 modify_field_select[0x10]; 12173 u8 reserved_at_20[0x2b]; 12174 u8 current_timestamp52_32[0x15]; 12175 u8 current_timestamp31_0[0x20]; 12176 u8 reserved_at_80[0x180]; 12177 }; 12178 12179 struct mlx5_ifc_host_params_context_bits { 12180 u8 host_number[0x8]; 12181 u8 reserved_at_8[0x7]; 12182 u8 host_pf_disabled[0x1]; 12183 u8 host_num_of_vfs[0x10]; 12184 12185 u8 host_total_vfs[0x10]; 12186 u8 host_pci_bus[0x10]; 12187 12188 u8 reserved_at_40[0x10]; 12189 u8 host_pci_device[0x10]; 12190 12191 u8 reserved_at_60[0x10]; 12192 u8 host_pci_function[0x10]; 12193 12194 u8 reserved_at_80[0x180]; 12195 }; 12196 12197 struct mlx5_ifc_query_esw_functions_in_bits { 12198 u8 opcode[0x10]; 12199 u8 reserved_at_10[0x10]; 12200 12201 u8 reserved_at_20[0x10]; 12202 u8 op_mod[0x10]; 12203 12204 u8 reserved_at_40[0x40]; 12205 }; 12206 12207 struct mlx5_ifc_query_esw_functions_out_bits { 12208 u8 status[0x8]; 12209 u8 reserved_at_8[0x18]; 12210 12211 u8 syndrome[0x20]; 12212 12213 u8 reserved_at_40[0x40]; 12214 12215 struct mlx5_ifc_host_params_context_bits host_params_context; 12216 12217 u8 reserved_at_280[0x180]; 12218 u8 host_sf_enable[][0x40]; 12219 }; 12220 12221 struct mlx5_ifc_sf_partition_bits { 12222 u8 reserved_at_0[0x10]; 12223 u8 log_num_sf[0x8]; 12224 u8 log_sf_bar_size[0x8]; 12225 }; 12226 12227 struct mlx5_ifc_query_sf_partitions_out_bits { 12228 u8 status[0x8]; 12229 u8 reserved_at_8[0x18]; 12230 12231 u8 syndrome[0x20]; 12232 12233 u8 reserved_at_40[0x18]; 12234 u8 num_sf_partitions[0x8]; 12235 12236 u8 reserved_at_60[0x20]; 12237 12238 struct mlx5_ifc_sf_partition_bits sf_partition[]; 12239 }; 12240 12241 struct mlx5_ifc_query_sf_partitions_in_bits { 12242 u8 opcode[0x10]; 12243 u8 reserved_at_10[0x10]; 12244 12245 u8 reserved_at_20[0x10]; 12246 u8 op_mod[0x10]; 12247 12248 u8 reserved_at_40[0x40]; 12249 }; 12250 12251 struct mlx5_ifc_dealloc_sf_out_bits { 12252 u8 status[0x8]; 12253 u8 reserved_at_8[0x18]; 12254 12255 u8 syndrome[0x20]; 12256 12257 u8 reserved_at_40[0x40]; 12258 }; 12259 12260 struct mlx5_ifc_dealloc_sf_in_bits { 12261 u8 opcode[0x10]; 12262 u8 reserved_at_10[0x10]; 12263 12264 u8 reserved_at_20[0x10]; 12265 u8 op_mod[0x10]; 12266 12267 u8 reserved_at_40[0x10]; 12268 u8 function_id[0x10]; 12269 12270 u8 reserved_at_60[0x20]; 12271 }; 12272 12273 struct mlx5_ifc_alloc_sf_out_bits { 12274 u8 status[0x8]; 12275 u8 reserved_at_8[0x18]; 12276 12277 u8 syndrome[0x20]; 12278 12279 u8 reserved_at_40[0x40]; 12280 }; 12281 12282 struct mlx5_ifc_alloc_sf_in_bits { 12283 u8 opcode[0x10]; 12284 u8 reserved_at_10[0x10]; 12285 12286 u8 reserved_at_20[0x10]; 12287 u8 op_mod[0x10]; 12288 12289 u8 reserved_at_40[0x10]; 12290 u8 function_id[0x10]; 12291 12292 u8 reserved_at_60[0x20]; 12293 }; 12294 12295 struct mlx5_ifc_affiliated_event_header_bits { 12296 u8 reserved_at_0[0x10]; 12297 u8 obj_type[0x10]; 12298 12299 u8 obj_id[0x20]; 12300 }; 12301 12302 enum { 12303 MLX5_HCA_CAP_GENERAL_OBJECT_TYPES_ENCRYPTION_KEY = BIT_ULL(0xc), 12304 MLX5_HCA_CAP_GENERAL_OBJECT_TYPES_IPSEC = BIT_ULL(0x13), 12305 MLX5_HCA_CAP_GENERAL_OBJECT_TYPES_SAMPLER = BIT_ULL(0x20), 12306 MLX5_HCA_CAP_GENERAL_OBJECT_TYPES_FLOW_METER_ASO = BIT_ULL(0x24), 12307 }; 12308 12309 enum { 12310 MLX5_GENERAL_OBJECT_TYPES_ENCRYPTION_KEY = 0xc, 12311 MLX5_GENERAL_OBJECT_TYPES_IPSEC = 0x13, 12312 MLX5_GENERAL_OBJECT_TYPES_SAMPLER = 0x20, 12313 MLX5_GENERAL_OBJECT_TYPES_FLOW_METER_ASO = 0x24, 12314 MLX5_GENERAL_OBJECT_TYPES_MACSEC = 0x27, 12315 MLX5_GENERAL_OBJECT_TYPES_INT_KEK = 0x47, 12316 MLX5_GENERAL_OBJECT_TYPES_FLOW_TABLE_ALIAS = 0xff15, 12317 }; 12318 12319 enum { 12320 MLX5_IPSEC_OBJECT_ICV_LEN_16B, 12321 }; 12322 12323 enum { 12324 MLX5_IPSEC_ASO_REG_C_0_1 = 0x0, 12325 MLX5_IPSEC_ASO_REG_C_2_3 = 0x1, 12326 MLX5_IPSEC_ASO_REG_C_4_5 = 0x2, 12327 MLX5_IPSEC_ASO_REG_C_6_7 = 0x3, 12328 }; 12329 12330 enum { 12331 MLX5_IPSEC_ASO_MODE = 0x0, 12332 MLX5_IPSEC_ASO_REPLAY_PROTECTION = 0x1, 12333 MLX5_IPSEC_ASO_INC_SN = 0x2, 12334 }; 12335 12336 enum { 12337 MLX5_IPSEC_ASO_REPLAY_WIN_32BIT = 0x0, 12338 MLX5_IPSEC_ASO_REPLAY_WIN_64BIT = 0x1, 12339 MLX5_IPSEC_ASO_REPLAY_WIN_128BIT = 0x2, 12340 MLX5_IPSEC_ASO_REPLAY_WIN_256BIT = 0x3, 12341 }; 12342 12343 struct mlx5_ifc_ipsec_aso_bits { 12344 u8 valid[0x1]; 12345 u8 reserved_at_201[0x1]; 12346 u8 mode[0x2]; 12347 u8 window_sz[0x2]; 12348 u8 soft_lft_arm[0x1]; 12349 u8 hard_lft_arm[0x1]; 12350 u8 remove_flow_enable[0x1]; 12351 u8 esn_event_arm[0x1]; 12352 u8 reserved_at_20a[0x16]; 12353 12354 u8 remove_flow_pkt_cnt[0x20]; 12355 12356 u8 remove_flow_soft_lft[0x20]; 12357 12358 u8 reserved_at_260[0x80]; 12359 12360 u8 mode_parameter[0x20]; 12361 12362 u8 replay_protection_window[0x100]; 12363 }; 12364 12365 struct mlx5_ifc_ipsec_obj_bits { 12366 u8 modify_field_select[0x40]; 12367 u8 full_offload[0x1]; 12368 u8 reserved_at_41[0x1]; 12369 u8 esn_en[0x1]; 12370 u8 esn_overlap[0x1]; 12371 u8 reserved_at_44[0x2]; 12372 u8 icv_length[0x2]; 12373 u8 reserved_at_48[0x4]; 12374 u8 aso_return_reg[0x4]; 12375 u8 reserved_at_50[0x10]; 12376 12377 u8 esn_msb[0x20]; 12378 12379 u8 reserved_at_80[0x8]; 12380 u8 dekn[0x18]; 12381 12382 u8 salt[0x20]; 12383 12384 u8 implicit_iv[0x40]; 12385 12386 u8 reserved_at_100[0x8]; 12387 u8 ipsec_aso_access_pd[0x18]; 12388 u8 reserved_at_120[0xe0]; 12389 12390 struct mlx5_ifc_ipsec_aso_bits ipsec_aso; 12391 }; 12392 12393 struct mlx5_ifc_create_ipsec_obj_in_bits { 12394 struct mlx5_ifc_general_obj_in_cmd_hdr_bits general_obj_in_cmd_hdr; 12395 struct mlx5_ifc_ipsec_obj_bits ipsec_object; 12396 }; 12397 12398 enum { 12399 MLX5_MODIFY_IPSEC_BITMASK_ESN_OVERLAP = BIT(0), 12400 MLX5_MODIFY_IPSEC_BITMASK_ESN_MSB = BIT(1), 12401 }; 12402 12403 struct mlx5_ifc_query_ipsec_obj_out_bits { 12404 struct mlx5_ifc_general_obj_out_cmd_hdr_bits general_obj_out_cmd_hdr; 12405 struct mlx5_ifc_ipsec_obj_bits ipsec_object; 12406 }; 12407 12408 struct mlx5_ifc_modify_ipsec_obj_in_bits { 12409 struct mlx5_ifc_general_obj_in_cmd_hdr_bits general_obj_in_cmd_hdr; 12410 struct mlx5_ifc_ipsec_obj_bits ipsec_object; 12411 }; 12412 12413 enum { 12414 MLX5_MACSEC_ASO_REPLAY_PROTECTION = 0x1, 12415 }; 12416 12417 enum { 12418 MLX5_MACSEC_ASO_REPLAY_WIN_32BIT = 0x0, 12419 MLX5_MACSEC_ASO_REPLAY_WIN_64BIT = 0x1, 12420 MLX5_MACSEC_ASO_REPLAY_WIN_128BIT = 0x2, 12421 MLX5_MACSEC_ASO_REPLAY_WIN_256BIT = 0x3, 12422 }; 12423 12424 #define MLX5_MACSEC_ASO_INC_SN 0x2 12425 #define MLX5_MACSEC_ASO_REG_C_4_5 0x2 12426 12427 struct mlx5_ifc_macsec_aso_bits { 12428 u8 valid[0x1]; 12429 u8 reserved_at_1[0x1]; 12430 u8 mode[0x2]; 12431 u8 window_size[0x2]; 12432 u8 soft_lifetime_arm[0x1]; 12433 u8 hard_lifetime_arm[0x1]; 12434 u8 remove_flow_enable[0x1]; 12435 u8 epn_event_arm[0x1]; 12436 u8 reserved_at_a[0x16]; 12437 12438 u8 remove_flow_packet_count[0x20]; 12439 12440 u8 remove_flow_soft_lifetime[0x20]; 12441 12442 u8 reserved_at_60[0x80]; 12443 12444 u8 mode_parameter[0x20]; 12445 12446 u8 replay_protection_window[8][0x20]; 12447 }; 12448 12449 struct mlx5_ifc_macsec_offload_obj_bits { 12450 u8 modify_field_select[0x40]; 12451 12452 u8 confidentiality_en[0x1]; 12453 u8 reserved_at_41[0x1]; 12454 u8 epn_en[0x1]; 12455 u8 epn_overlap[0x1]; 12456 u8 reserved_at_44[0x2]; 12457 u8 confidentiality_offset[0x2]; 12458 u8 reserved_at_48[0x4]; 12459 u8 aso_return_reg[0x4]; 12460 u8 reserved_at_50[0x10]; 12461 12462 u8 epn_msb[0x20]; 12463 12464 u8 reserved_at_80[0x8]; 12465 u8 dekn[0x18]; 12466 12467 u8 reserved_at_a0[0x20]; 12468 12469 u8 sci[0x40]; 12470 12471 u8 reserved_at_100[0x8]; 12472 u8 macsec_aso_access_pd[0x18]; 12473 12474 u8 reserved_at_120[0x60]; 12475 12476 u8 salt[3][0x20]; 12477 12478 u8 reserved_at_1e0[0x20]; 12479 12480 struct mlx5_ifc_macsec_aso_bits macsec_aso; 12481 }; 12482 12483 struct mlx5_ifc_create_macsec_obj_in_bits { 12484 struct mlx5_ifc_general_obj_in_cmd_hdr_bits general_obj_in_cmd_hdr; 12485 struct mlx5_ifc_macsec_offload_obj_bits macsec_object; 12486 }; 12487 12488 struct mlx5_ifc_modify_macsec_obj_in_bits { 12489 struct mlx5_ifc_general_obj_in_cmd_hdr_bits general_obj_in_cmd_hdr; 12490 struct mlx5_ifc_macsec_offload_obj_bits macsec_object; 12491 }; 12492 12493 enum { 12494 MLX5_MODIFY_MACSEC_BITMASK_EPN_OVERLAP = BIT(0), 12495 MLX5_MODIFY_MACSEC_BITMASK_EPN_MSB = BIT(1), 12496 }; 12497 12498 struct mlx5_ifc_query_macsec_obj_out_bits { 12499 struct mlx5_ifc_general_obj_out_cmd_hdr_bits general_obj_out_cmd_hdr; 12500 struct mlx5_ifc_macsec_offload_obj_bits macsec_object; 12501 }; 12502 12503 struct mlx5_ifc_wrapped_dek_bits { 12504 u8 gcm_iv[0x60]; 12505 12506 u8 reserved_at_60[0x20]; 12507 12508 u8 const0[0x1]; 12509 u8 key_size[0x1]; 12510 u8 reserved_at_82[0x2]; 12511 u8 key2_invalid[0x1]; 12512 u8 reserved_at_85[0x3]; 12513 u8 pd[0x18]; 12514 12515 u8 key_purpose[0x5]; 12516 u8 reserved_at_a5[0x13]; 12517 u8 kek_id[0x8]; 12518 12519 u8 reserved_at_c0[0x40]; 12520 12521 u8 key1[0x8][0x20]; 12522 12523 u8 key2[0x8][0x20]; 12524 12525 u8 reserved_at_300[0x40]; 12526 12527 u8 const1[0x1]; 12528 u8 reserved_at_341[0x1f]; 12529 12530 u8 reserved_at_360[0x20]; 12531 12532 u8 auth_tag[0x80]; 12533 }; 12534 12535 struct mlx5_ifc_encryption_key_obj_bits { 12536 u8 modify_field_select[0x40]; 12537 12538 u8 state[0x8]; 12539 u8 sw_wrapped[0x1]; 12540 u8 reserved_at_49[0xb]; 12541 u8 key_size[0x4]; 12542 u8 reserved_at_58[0x4]; 12543 u8 key_purpose[0x4]; 12544 12545 u8 reserved_at_60[0x8]; 12546 u8 pd[0x18]; 12547 12548 u8 reserved_at_80[0x100]; 12549 12550 u8 opaque[0x40]; 12551 12552 u8 reserved_at_1c0[0x40]; 12553 12554 u8 key[8][0x80]; 12555 12556 u8 sw_wrapped_dek[8][0x80]; 12557 12558 u8 reserved_at_a00[0x600]; 12559 }; 12560 12561 struct mlx5_ifc_create_encryption_key_in_bits { 12562 struct mlx5_ifc_general_obj_in_cmd_hdr_bits general_obj_in_cmd_hdr; 12563 struct mlx5_ifc_encryption_key_obj_bits encryption_key_object; 12564 }; 12565 12566 struct mlx5_ifc_modify_encryption_key_in_bits { 12567 struct mlx5_ifc_general_obj_in_cmd_hdr_bits general_obj_in_cmd_hdr; 12568 struct mlx5_ifc_encryption_key_obj_bits encryption_key_object; 12569 }; 12570 12571 enum { 12572 MLX5_FLOW_METER_MODE_BYTES_IP_LENGTH = 0x0, 12573 MLX5_FLOW_METER_MODE_BYTES_CALC_WITH_L2 = 0x1, 12574 MLX5_FLOW_METER_MODE_BYTES_CALC_WITH_L2_IPG = 0x2, 12575 MLX5_FLOW_METER_MODE_NUM_PACKETS = 0x3, 12576 }; 12577 12578 struct mlx5_ifc_flow_meter_parameters_bits { 12579 u8 valid[0x1]; 12580 u8 bucket_overflow[0x1]; 12581 u8 start_color[0x2]; 12582 u8 both_buckets_on_green[0x1]; 12583 u8 reserved_at_5[0x1]; 12584 u8 meter_mode[0x2]; 12585 u8 reserved_at_8[0x18]; 12586 12587 u8 reserved_at_20[0x20]; 12588 12589 u8 reserved_at_40[0x3]; 12590 u8 cbs_exponent[0x5]; 12591 u8 cbs_mantissa[0x8]; 12592 u8 reserved_at_50[0x3]; 12593 u8 cir_exponent[0x5]; 12594 u8 cir_mantissa[0x8]; 12595 12596 u8 reserved_at_60[0x20]; 12597 12598 u8 reserved_at_80[0x3]; 12599 u8 ebs_exponent[0x5]; 12600 u8 ebs_mantissa[0x8]; 12601 u8 reserved_at_90[0x3]; 12602 u8 eir_exponent[0x5]; 12603 u8 eir_mantissa[0x8]; 12604 12605 u8 reserved_at_a0[0x60]; 12606 }; 12607 12608 struct mlx5_ifc_flow_meter_aso_obj_bits { 12609 u8 modify_field_select[0x40]; 12610 12611 u8 reserved_at_40[0x40]; 12612 12613 u8 reserved_at_80[0x8]; 12614 u8 meter_aso_access_pd[0x18]; 12615 12616 u8 reserved_at_a0[0x160]; 12617 12618 struct mlx5_ifc_flow_meter_parameters_bits flow_meter_parameters[2]; 12619 }; 12620 12621 struct mlx5_ifc_create_flow_meter_aso_obj_in_bits { 12622 struct mlx5_ifc_general_obj_in_cmd_hdr_bits hdr; 12623 struct mlx5_ifc_flow_meter_aso_obj_bits flow_meter_aso_obj; 12624 }; 12625 12626 struct mlx5_ifc_int_kek_obj_bits { 12627 u8 modify_field_select[0x40]; 12628 12629 u8 state[0x8]; 12630 u8 auto_gen[0x1]; 12631 u8 reserved_at_49[0xb]; 12632 u8 key_size[0x4]; 12633 u8 reserved_at_58[0x8]; 12634 12635 u8 reserved_at_60[0x8]; 12636 u8 pd[0x18]; 12637 12638 u8 reserved_at_80[0x180]; 12639 u8 key[8][0x80]; 12640 12641 u8 reserved_at_600[0x200]; 12642 }; 12643 12644 struct mlx5_ifc_create_int_kek_obj_in_bits { 12645 struct mlx5_ifc_general_obj_in_cmd_hdr_bits general_obj_in_cmd_hdr; 12646 struct mlx5_ifc_int_kek_obj_bits int_kek_object; 12647 }; 12648 12649 struct mlx5_ifc_create_int_kek_obj_out_bits { 12650 struct mlx5_ifc_general_obj_out_cmd_hdr_bits general_obj_out_cmd_hdr; 12651 struct mlx5_ifc_int_kek_obj_bits int_kek_object; 12652 }; 12653 12654 struct mlx5_ifc_sampler_obj_bits { 12655 u8 modify_field_select[0x40]; 12656 12657 u8 table_type[0x8]; 12658 u8 level[0x8]; 12659 u8 reserved_at_50[0xf]; 12660 u8 ignore_flow_level[0x1]; 12661 12662 u8 sample_ratio[0x20]; 12663 12664 u8 reserved_at_80[0x8]; 12665 u8 sample_table_id[0x18]; 12666 12667 u8 reserved_at_a0[0x8]; 12668 u8 default_table_id[0x18]; 12669 12670 u8 sw_steering_icm_address_rx[0x40]; 12671 u8 sw_steering_icm_address_tx[0x40]; 12672 12673 u8 reserved_at_140[0xa0]; 12674 }; 12675 12676 struct mlx5_ifc_create_sampler_obj_in_bits { 12677 struct mlx5_ifc_general_obj_in_cmd_hdr_bits general_obj_in_cmd_hdr; 12678 struct mlx5_ifc_sampler_obj_bits sampler_object; 12679 }; 12680 12681 struct mlx5_ifc_query_sampler_obj_out_bits { 12682 struct mlx5_ifc_general_obj_out_cmd_hdr_bits general_obj_out_cmd_hdr; 12683 struct mlx5_ifc_sampler_obj_bits sampler_object; 12684 }; 12685 12686 enum { 12687 MLX5_GENERAL_OBJECT_TYPE_ENCRYPTION_KEY_KEY_SIZE_128 = 0x0, 12688 MLX5_GENERAL_OBJECT_TYPE_ENCRYPTION_KEY_KEY_SIZE_256 = 0x1, 12689 }; 12690 12691 enum { 12692 MLX5_GENERAL_OBJECT_TYPE_ENCRYPTION_KEY_PURPOSE_TLS = 0x1, 12693 MLX5_GENERAL_OBJECT_TYPE_ENCRYPTION_KEY_PURPOSE_IPSEC = 0x2, 12694 MLX5_GENERAL_OBJECT_TYPE_ENCRYPTION_KEY_PURPOSE_MACSEC = 0x4, 12695 }; 12696 12697 struct mlx5_ifc_tls_static_params_bits { 12698 u8 const_2[0x2]; 12699 u8 tls_version[0x4]; 12700 u8 const_1[0x2]; 12701 u8 reserved_at_8[0x14]; 12702 u8 encryption_standard[0x4]; 12703 12704 u8 reserved_at_20[0x20]; 12705 12706 u8 initial_record_number[0x40]; 12707 12708 u8 resync_tcp_sn[0x20]; 12709 12710 u8 gcm_iv[0x20]; 12711 12712 u8 implicit_iv[0x40]; 12713 12714 u8 reserved_at_100[0x8]; 12715 u8 dek_index[0x18]; 12716 12717 u8 reserved_at_120[0xe0]; 12718 }; 12719 12720 struct mlx5_ifc_tls_progress_params_bits { 12721 u8 next_record_tcp_sn[0x20]; 12722 12723 u8 hw_resync_tcp_sn[0x20]; 12724 12725 u8 record_tracker_state[0x2]; 12726 u8 auth_state[0x2]; 12727 u8 reserved_at_44[0x4]; 12728 u8 hw_offset_record_number[0x18]; 12729 }; 12730 12731 enum { 12732 MLX5_MTT_PERM_READ = 1 << 0, 12733 MLX5_MTT_PERM_WRITE = 1 << 1, 12734 MLX5_MTT_PERM_RW = MLX5_MTT_PERM_READ | MLX5_MTT_PERM_WRITE, 12735 }; 12736 12737 enum { 12738 MLX5_SUSPEND_VHCA_IN_OP_MOD_SUSPEND_INITIATOR = 0x0, 12739 MLX5_SUSPEND_VHCA_IN_OP_MOD_SUSPEND_RESPONDER = 0x1, 12740 }; 12741 12742 struct mlx5_ifc_suspend_vhca_in_bits { 12743 u8 opcode[0x10]; 12744 u8 uid[0x10]; 12745 12746 u8 reserved_at_20[0x10]; 12747 u8 op_mod[0x10]; 12748 12749 u8 reserved_at_40[0x10]; 12750 u8 vhca_id[0x10]; 12751 12752 u8 reserved_at_60[0x20]; 12753 }; 12754 12755 struct mlx5_ifc_suspend_vhca_out_bits { 12756 u8 status[0x8]; 12757 u8 reserved_at_8[0x18]; 12758 12759 u8 syndrome[0x20]; 12760 12761 u8 reserved_at_40[0x40]; 12762 }; 12763 12764 enum { 12765 MLX5_RESUME_VHCA_IN_OP_MOD_RESUME_RESPONDER = 0x0, 12766 MLX5_RESUME_VHCA_IN_OP_MOD_RESUME_INITIATOR = 0x1, 12767 }; 12768 12769 struct mlx5_ifc_resume_vhca_in_bits { 12770 u8 opcode[0x10]; 12771 u8 uid[0x10]; 12772 12773 u8 reserved_at_20[0x10]; 12774 u8 op_mod[0x10]; 12775 12776 u8 reserved_at_40[0x10]; 12777 u8 vhca_id[0x10]; 12778 12779 u8 reserved_at_60[0x20]; 12780 }; 12781 12782 struct mlx5_ifc_resume_vhca_out_bits { 12783 u8 status[0x8]; 12784 u8 reserved_at_8[0x18]; 12785 12786 u8 syndrome[0x20]; 12787 12788 u8 reserved_at_40[0x40]; 12789 }; 12790 12791 struct mlx5_ifc_query_vhca_migration_state_in_bits { 12792 u8 opcode[0x10]; 12793 u8 uid[0x10]; 12794 12795 u8 reserved_at_20[0x10]; 12796 u8 op_mod[0x10]; 12797 12798 u8 incremental[0x1]; 12799 u8 chunk[0x1]; 12800 u8 reserved_at_42[0xe]; 12801 u8 vhca_id[0x10]; 12802 12803 u8 reserved_at_60[0x20]; 12804 }; 12805 12806 struct mlx5_ifc_query_vhca_migration_state_out_bits { 12807 u8 status[0x8]; 12808 u8 reserved_at_8[0x18]; 12809 12810 u8 syndrome[0x20]; 12811 12812 u8 reserved_at_40[0x40]; 12813 12814 u8 required_umem_size[0x20]; 12815 12816 u8 reserved_at_a0[0x20]; 12817 12818 u8 remaining_total_size[0x40]; 12819 12820 u8 reserved_at_100[0x100]; 12821 }; 12822 12823 struct mlx5_ifc_save_vhca_state_in_bits { 12824 u8 opcode[0x10]; 12825 u8 uid[0x10]; 12826 12827 u8 reserved_at_20[0x10]; 12828 u8 op_mod[0x10]; 12829 12830 u8 incremental[0x1]; 12831 u8 set_track[0x1]; 12832 u8 reserved_at_42[0xe]; 12833 u8 vhca_id[0x10]; 12834 12835 u8 reserved_at_60[0x20]; 12836 12837 u8 va[0x40]; 12838 12839 u8 mkey[0x20]; 12840 12841 u8 size[0x20]; 12842 }; 12843 12844 struct mlx5_ifc_save_vhca_state_out_bits { 12845 u8 status[0x8]; 12846 u8 reserved_at_8[0x18]; 12847 12848 u8 syndrome[0x20]; 12849 12850 u8 actual_image_size[0x20]; 12851 12852 u8 next_required_umem_size[0x20]; 12853 }; 12854 12855 struct mlx5_ifc_load_vhca_state_in_bits { 12856 u8 opcode[0x10]; 12857 u8 uid[0x10]; 12858 12859 u8 reserved_at_20[0x10]; 12860 u8 op_mod[0x10]; 12861 12862 u8 reserved_at_40[0x10]; 12863 u8 vhca_id[0x10]; 12864 12865 u8 reserved_at_60[0x20]; 12866 12867 u8 va[0x40]; 12868 12869 u8 mkey[0x20]; 12870 12871 u8 size[0x20]; 12872 }; 12873 12874 struct mlx5_ifc_load_vhca_state_out_bits { 12875 u8 status[0x8]; 12876 u8 reserved_at_8[0x18]; 12877 12878 u8 syndrome[0x20]; 12879 12880 u8 reserved_at_40[0x40]; 12881 }; 12882 12883 struct mlx5_ifc_adv_virtualization_cap_bits { 12884 u8 reserved_at_0[0x3]; 12885 u8 pg_track_log_max_num[0x5]; 12886 u8 pg_track_max_num_range[0x8]; 12887 u8 pg_track_log_min_addr_space[0x8]; 12888 u8 pg_track_log_max_addr_space[0x8]; 12889 12890 u8 reserved_at_20[0x3]; 12891 u8 pg_track_log_min_msg_size[0x5]; 12892 u8 reserved_at_28[0x3]; 12893 u8 pg_track_log_max_msg_size[0x5]; 12894 u8 reserved_at_30[0x3]; 12895 u8 pg_track_log_min_page_size[0x5]; 12896 u8 reserved_at_38[0x3]; 12897 u8 pg_track_log_max_page_size[0x5]; 12898 12899 u8 reserved_at_40[0x7c0]; 12900 }; 12901 12902 struct mlx5_ifc_page_track_report_entry_bits { 12903 u8 dirty_address_high[0x20]; 12904 12905 u8 dirty_address_low[0x20]; 12906 }; 12907 12908 enum { 12909 MLX5_PAGE_TRACK_STATE_TRACKING, 12910 MLX5_PAGE_TRACK_STATE_REPORTING, 12911 MLX5_PAGE_TRACK_STATE_ERROR, 12912 }; 12913 12914 struct mlx5_ifc_page_track_range_bits { 12915 u8 start_address[0x40]; 12916 12917 u8 length[0x40]; 12918 }; 12919 12920 struct mlx5_ifc_page_track_bits { 12921 u8 modify_field_select[0x40]; 12922 12923 u8 reserved_at_40[0x10]; 12924 u8 vhca_id[0x10]; 12925 12926 u8 reserved_at_60[0x20]; 12927 12928 u8 state[0x4]; 12929 u8 track_type[0x4]; 12930 u8 log_addr_space_size[0x8]; 12931 u8 reserved_at_90[0x3]; 12932 u8 log_page_size[0x5]; 12933 u8 reserved_at_98[0x3]; 12934 u8 log_msg_size[0x5]; 12935 12936 u8 reserved_at_a0[0x8]; 12937 u8 reporting_qpn[0x18]; 12938 12939 u8 reserved_at_c0[0x18]; 12940 u8 num_ranges[0x8]; 12941 12942 u8 reserved_at_e0[0x20]; 12943 12944 u8 range_start_address[0x40]; 12945 12946 u8 length[0x40]; 12947 12948 struct mlx5_ifc_page_track_range_bits track_range[0]; 12949 }; 12950 12951 struct mlx5_ifc_create_page_track_obj_in_bits { 12952 struct mlx5_ifc_general_obj_in_cmd_hdr_bits general_obj_in_cmd_hdr; 12953 struct mlx5_ifc_page_track_bits obj_context; 12954 }; 12955 12956 struct mlx5_ifc_modify_page_track_obj_in_bits { 12957 struct mlx5_ifc_general_obj_in_cmd_hdr_bits general_obj_in_cmd_hdr; 12958 struct mlx5_ifc_page_track_bits obj_context; 12959 }; 12960 12961 struct mlx5_ifc_query_page_track_obj_out_bits { 12962 struct mlx5_ifc_general_obj_out_cmd_hdr_bits general_obj_out_cmd_hdr; 12963 struct mlx5_ifc_page_track_bits obj_context; 12964 }; 12965 12966 struct mlx5_ifc_msecq_reg_bits { 12967 u8 reserved_at_0[0x20]; 12968 12969 u8 reserved_at_20[0x12]; 12970 u8 network_option[0x2]; 12971 u8 local_ssm_code[0x4]; 12972 u8 local_enhanced_ssm_code[0x8]; 12973 12974 u8 local_clock_identity[0x40]; 12975 12976 u8 reserved_at_80[0x180]; 12977 }; 12978 12979 enum { 12980 MLX5_MSEES_FIELD_SELECT_ENABLE = BIT(0), 12981 MLX5_MSEES_FIELD_SELECT_ADMIN_STATUS = BIT(1), 12982 MLX5_MSEES_FIELD_SELECT_ADMIN_FREQ_MEASURE = BIT(2), 12983 }; 12984 12985 enum mlx5_msees_admin_status { 12986 MLX5_MSEES_ADMIN_STATUS_FREE_RUNNING = 0x0, 12987 MLX5_MSEES_ADMIN_STATUS_TRACK = 0x1, 12988 }; 12989 12990 enum mlx5_msees_oper_status { 12991 MLX5_MSEES_OPER_STATUS_FREE_RUNNING = 0x0, 12992 MLX5_MSEES_OPER_STATUS_SELF_TRACK = 0x1, 12993 MLX5_MSEES_OPER_STATUS_OTHER_TRACK = 0x2, 12994 MLX5_MSEES_OPER_STATUS_HOLDOVER = 0x3, 12995 MLX5_MSEES_OPER_STATUS_FAIL_HOLDOVER = 0x4, 12996 MLX5_MSEES_OPER_STATUS_FAIL_FREE_RUNNING = 0x5, 12997 }; 12998 12999 enum mlx5_msees_failure_reason { 13000 MLX5_MSEES_FAILURE_REASON_UNDEFINED_ERROR = 0x0, 13001 MLX5_MSEES_FAILURE_REASON_PORT_DOWN = 0x1, 13002 MLX5_MSEES_FAILURE_REASON_TOO_HIGH_FREQUENCY_DIFF = 0x2, 13003 MLX5_MSEES_FAILURE_REASON_NET_SYNCHRONIZER_DEVICE_ERROR = 0x3, 13004 MLX5_MSEES_FAILURE_REASON_LACK_OF_RESOURCES = 0x4, 13005 }; 13006 13007 struct mlx5_ifc_msees_reg_bits { 13008 u8 reserved_at_0[0x8]; 13009 u8 local_port[0x8]; 13010 u8 pnat[0x2]; 13011 u8 lp_msb[0x2]; 13012 u8 reserved_at_14[0xc]; 13013 13014 u8 field_select[0x20]; 13015 13016 u8 admin_status[0x4]; 13017 u8 oper_status[0x4]; 13018 u8 ho_acq[0x1]; 13019 u8 reserved_at_49[0xc]; 13020 u8 admin_freq_measure[0x1]; 13021 u8 oper_freq_measure[0x1]; 13022 u8 failure_reason[0x9]; 13023 13024 u8 frequency_diff[0x20]; 13025 13026 u8 reserved_at_80[0x180]; 13027 }; 13028 13029 #endif /* MLX5_IFC_H */ 13030