1 /* 2 * Copyright (c) 2013-2015, Mellanox Technologies, Ltd. All rights reserved. 3 * 4 * This software is available to you under a choice of one of two 5 * licenses. You may choose to be licensed under the terms of the GNU 6 * General Public License (GPL) Version 2, available from the file 7 * COPYING in the main directory of this source tree, or the 8 * OpenIB.org BSD license below: 9 * 10 * Redistribution and use in source and binary forms, with or 11 * without modification, are permitted provided that the following 12 * conditions are met: 13 * 14 * - Redistributions of source code must retain the above 15 * copyright notice, this list of conditions and the following 16 * disclaimer. 17 * 18 * - Redistributions in binary form must reproduce the above 19 * copyright notice, this list of conditions and the following 20 * disclaimer in the documentation and/or other materials 21 * provided with the distribution. 22 * 23 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, 24 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF 25 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND 26 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS 27 * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN 28 * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN 29 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE 30 * SOFTWARE. 31 */ 32 #ifndef MLX5_IFC_H 33 #define MLX5_IFC_H 34 35 #include "mlx5_ifc_fpga.h" 36 37 enum { 38 MLX5_EVENT_TYPE_CODING_COMPLETION_EVENTS = 0x0, 39 MLX5_EVENT_TYPE_CODING_PATH_MIGRATED_SUCCEEDED = 0x1, 40 MLX5_EVENT_TYPE_CODING_COMMUNICATION_ESTABLISHED = 0x2, 41 MLX5_EVENT_TYPE_CODING_SEND_QUEUE_DRAINED = 0x3, 42 MLX5_EVENT_TYPE_CODING_LAST_WQE_REACHED = 0x13, 43 MLX5_EVENT_TYPE_CODING_SRQ_LIMIT = 0x14, 44 MLX5_EVENT_TYPE_CODING_DCT_ALL_CONNECTIONS_CLOSED = 0x1c, 45 MLX5_EVENT_TYPE_CODING_DCT_ACCESS_KEY_VIOLATION = 0x1d, 46 MLX5_EVENT_TYPE_CODING_CQ_ERROR = 0x4, 47 MLX5_EVENT_TYPE_CODING_LOCAL_WQ_CATASTROPHIC_ERROR = 0x5, 48 MLX5_EVENT_TYPE_CODING_PATH_MIGRATION_FAILED = 0x7, 49 MLX5_EVENT_TYPE_CODING_PAGE_FAULT_EVENT = 0xc, 50 MLX5_EVENT_TYPE_CODING_INVALID_REQUEST_LOCAL_WQ_ERROR = 0x10, 51 MLX5_EVENT_TYPE_CODING_LOCAL_ACCESS_VIOLATION_WQ_ERROR = 0x11, 52 MLX5_EVENT_TYPE_CODING_LOCAL_SRQ_CATASTROPHIC_ERROR = 0x12, 53 MLX5_EVENT_TYPE_CODING_INTERNAL_ERROR = 0x8, 54 MLX5_EVENT_TYPE_CODING_PORT_STATE_CHANGE = 0x9, 55 MLX5_EVENT_TYPE_CODING_GPIO_EVENT = 0x15, 56 MLX5_EVENT_TYPE_CODING_REMOTE_CONFIGURATION_PROTOCOL_EVENT = 0x19, 57 MLX5_EVENT_TYPE_CODING_DOORBELL_BLUEFLAME_CONGESTION_EVENT = 0x1a, 58 MLX5_EVENT_TYPE_CODING_STALL_VL_EVENT = 0x1b, 59 MLX5_EVENT_TYPE_CODING_DROPPED_PACKET_LOGGED_EVENT = 0x1f, 60 MLX5_EVENT_TYPE_CODING_COMMAND_INTERFACE_COMPLETION = 0xa, 61 MLX5_EVENT_TYPE_CODING_PAGE_REQUEST = 0xb, 62 MLX5_EVENT_TYPE_CODING_FPGA_ERROR = 0x20, 63 MLX5_EVENT_TYPE_CODING_FPGA_QP_ERROR = 0x21 64 }; 65 66 enum { 67 MLX5_SET_HCA_CAP_OP_MOD_GENERAL_DEVICE = 0x0, 68 MLX5_SET_HCA_CAP_OP_MOD_ODP = 0x2, 69 MLX5_SET_HCA_CAP_OP_MOD_ATOMIC = 0x3, 70 MLX5_SET_HCA_CAP_OP_MOD_ROCE = 0x4, 71 }; 72 73 enum { 74 MLX5_SHARED_RESOURCE_UID = 0xffff, 75 }; 76 77 enum { 78 MLX5_OBJ_TYPE_SW_ICM = 0x0008, 79 }; 80 81 enum { 82 MLX5_GENERAL_OBJ_TYPES_CAP_SW_ICM = (1ULL << MLX5_OBJ_TYPE_SW_ICM), 83 MLX5_GENERAL_OBJ_TYPES_CAP_GENEVE_TLV_OPT = (1ULL << 11), 84 MLX5_GENERAL_OBJ_TYPES_CAP_VIRTIO_NET_Q = (1ULL << 13), 85 }; 86 87 enum { 88 MLX5_OBJ_TYPE_GENEVE_TLV_OPT = 0x000b, 89 MLX5_OBJ_TYPE_VIRTIO_NET_Q = 0x000d, 90 MLX5_OBJ_TYPE_MATCH_DEFINER = 0x0018, 91 MLX5_OBJ_TYPE_MKEY = 0xff01, 92 MLX5_OBJ_TYPE_QP = 0xff02, 93 MLX5_OBJ_TYPE_PSV = 0xff03, 94 MLX5_OBJ_TYPE_RMP = 0xff04, 95 MLX5_OBJ_TYPE_XRC_SRQ = 0xff05, 96 MLX5_OBJ_TYPE_RQ = 0xff06, 97 MLX5_OBJ_TYPE_SQ = 0xff07, 98 MLX5_OBJ_TYPE_TIR = 0xff08, 99 MLX5_OBJ_TYPE_TIS = 0xff09, 100 MLX5_OBJ_TYPE_DCT = 0xff0a, 101 MLX5_OBJ_TYPE_XRQ = 0xff0b, 102 MLX5_OBJ_TYPE_RQT = 0xff0e, 103 MLX5_OBJ_TYPE_FLOW_COUNTER = 0xff0f, 104 MLX5_OBJ_TYPE_CQ = 0xff10, 105 }; 106 107 enum { 108 MLX5_CMD_OP_QUERY_HCA_CAP = 0x100, 109 MLX5_CMD_OP_QUERY_ADAPTER = 0x101, 110 MLX5_CMD_OP_INIT_HCA = 0x102, 111 MLX5_CMD_OP_TEARDOWN_HCA = 0x103, 112 MLX5_CMD_OP_ENABLE_HCA = 0x104, 113 MLX5_CMD_OP_DISABLE_HCA = 0x105, 114 MLX5_CMD_OP_QUERY_PAGES = 0x107, 115 MLX5_CMD_OP_MANAGE_PAGES = 0x108, 116 MLX5_CMD_OP_SET_HCA_CAP = 0x109, 117 MLX5_CMD_OP_QUERY_ISSI = 0x10a, 118 MLX5_CMD_OP_SET_ISSI = 0x10b, 119 MLX5_CMD_OP_SET_DRIVER_VERSION = 0x10d, 120 MLX5_CMD_OP_QUERY_SF_PARTITION = 0x111, 121 MLX5_CMD_OP_ALLOC_SF = 0x113, 122 MLX5_CMD_OP_DEALLOC_SF = 0x114, 123 MLX5_CMD_OP_SUSPEND_VHCA = 0x115, 124 MLX5_CMD_OP_RESUME_VHCA = 0x116, 125 MLX5_CMD_OP_QUERY_VHCA_MIGRATION_STATE = 0x117, 126 MLX5_CMD_OP_SAVE_VHCA_STATE = 0x118, 127 MLX5_CMD_OP_LOAD_VHCA_STATE = 0x119, 128 MLX5_CMD_OP_CREATE_MKEY = 0x200, 129 MLX5_CMD_OP_QUERY_MKEY = 0x201, 130 MLX5_CMD_OP_DESTROY_MKEY = 0x202, 131 MLX5_CMD_OP_QUERY_SPECIAL_CONTEXTS = 0x203, 132 MLX5_CMD_OP_PAGE_FAULT_RESUME = 0x204, 133 MLX5_CMD_OP_ALLOC_MEMIC = 0x205, 134 MLX5_CMD_OP_DEALLOC_MEMIC = 0x206, 135 MLX5_CMD_OP_MODIFY_MEMIC = 0x207, 136 MLX5_CMD_OP_CREATE_EQ = 0x301, 137 MLX5_CMD_OP_DESTROY_EQ = 0x302, 138 MLX5_CMD_OP_QUERY_EQ = 0x303, 139 MLX5_CMD_OP_GEN_EQE = 0x304, 140 MLX5_CMD_OP_CREATE_CQ = 0x400, 141 MLX5_CMD_OP_DESTROY_CQ = 0x401, 142 MLX5_CMD_OP_QUERY_CQ = 0x402, 143 MLX5_CMD_OP_MODIFY_CQ = 0x403, 144 MLX5_CMD_OP_CREATE_QP = 0x500, 145 MLX5_CMD_OP_DESTROY_QP = 0x501, 146 MLX5_CMD_OP_RST2INIT_QP = 0x502, 147 MLX5_CMD_OP_INIT2RTR_QP = 0x503, 148 MLX5_CMD_OP_RTR2RTS_QP = 0x504, 149 MLX5_CMD_OP_RTS2RTS_QP = 0x505, 150 MLX5_CMD_OP_SQERR2RTS_QP = 0x506, 151 MLX5_CMD_OP_2ERR_QP = 0x507, 152 MLX5_CMD_OP_2RST_QP = 0x50a, 153 MLX5_CMD_OP_QUERY_QP = 0x50b, 154 MLX5_CMD_OP_SQD_RTS_QP = 0x50c, 155 MLX5_CMD_OP_INIT2INIT_QP = 0x50e, 156 MLX5_CMD_OP_CREATE_PSV = 0x600, 157 MLX5_CMD_OP_DESTROY_PSV = 0x601, 158 MLX5_CMD_OP_CREATE_SRQ = 0x700, 159 MLX5_CMD_OP_DESTROY_SRQ = 0x701, 160 MLX5_CMD_OP_QUERY_SRQ = 0x702, 161 MLX5_CMD_OP_ARM_RQ = 0x703, 162 MLX5_CMD_OP_CREATE_XRC_SRQ = 0x705, 163 MLX5_CMD_OP_DESTROY_XRC_SRQ = 0x706, 164 MLX5_CMD_OP_QUERY_XRC_SRQ = 0x707, 165 MLX5_CMD_OP_ARM_XRC_SRQ = 0x708, 166 MLX5_CMD_OP_CREATE_DCT = 0x710, 167 MLX5_CMD_OP_DESTROY_DCT = 0x711, 168 MLX5_CMD_OP_DRAIN_DCT = 0x712, 169 MLX5_CMD_OP_QUERY_DCT = 0x713, 170 MLX5_CMD_OP_ARM_DCT_FOR_KEY_VIOLATION = 0x714, 171 MLX5_CMD_OP_CREATE_XRQ = 0x717, 172 MLX5_CMD_OP_DESTROY_XRQ = 0x718, 173 MLX5_CMD_OP_QUERY_XRQ = 0x719, 174 MLX5_CMD_OP_ARM_XRQ = 0x71a, 175 MLX5_CMD_OP_QUERY_XRQ_DC_PARAMS_ENTRY = 0x725, 176 MLX5_CMD_OP_SET_XRQ_DC_PARAMS_ENTRY = 0x726, 177 MLX5_CMD_OP_QUERY_XRQ_ERROR_PARAMS = 0x727, 178 MLX5_CMD_OP_RELEASE_XRQ_ERROR = 0x729, 179 MLX5_CMD_OP_MODIFY_XRQ = 0x72a, 180 MLX5_CMD_OP_QUERY_ESW_FUNCTIONS = 0x740, 181 MLX5_CMD_OP_QUERY_VPORT_STATE = 0x750, 182 MLX5_CMD_OP_MODIFY_VPORT_STATE = 0x751, 183 MLX5_CMD_OP_QUERY_ESW_VPORT_CONTEXT = 0x752, 184 MLX5_CMD_OP_MODIFY_ESW_VPORT_CONTEXT = 0x753, 185 MLX5_CMD_OP_QUERY_NIC_VPORT_CONTEXT = 0x754, 186 MLX5_CMD_OP_MODIFY_NIC_VPORT_CONTEXT = 0x755, 187 MLX5_CMD_OP_QUERY_ROCE_ADDRESS = 0x760, 188 MLX5_CMD_OP_SET_ROCE_ADDRESS = 0x761, 189 MLX5_CMD_OP_QUERY_HCA_VPORT_CONTEXT = 0x762, 190 MLX5_CMD_OP_MODIFY_HCA_VPORT_CONTEXT = 0x763, 191 MLX5_CMD_OP_QUERY_HCA_VPORT_GID = 0x764, 192 MLX5_CMD_OP_QUERY_HCA_VPORT_PKEY = 0x765, 193 MLX5_CMD_OP_QUERY_VNIC_ENV = 0x76f, 194 MLX5_CMD_OP_QUERY_VPORT_COUNTER = 0x770, 195 MLX5_CMD_OP_ALLOC_Q_COUNTER = 0x771, 196 MLX5_CMD_OP_DEALLOC_Q_COUNTER = 0x772, 197 MLX5_CMD_OP_QUERY_Q_COUNTER = 0x773, 198 MLX5_CMD_OP_SET_MONITOR_COUNTER = 0x774, 199 MLX5_CMD_OP_ARM_MONITOR_COUNTER = 0x775, 200 MLX5_CMD_OP_SET_PP_RATE_LIMIT = 0x780, 201 MLX5_CMD_OP_QUERY_RATE_LIMIT = 0x781, 202 MLX5_CMD_OP_CREATE_SCHEDULING_ELEMENT = 0x782, 203 MLX5_CMD_OP_DESTROY_SCHEDULING_ELEMENT = 0x783, 204 MLX5_CMD_OP_QUERY_SCHEDULING_ELEMENT = 0x784, 205 MLX5_CMD_OP_MODIFY_SCHEDULING_ELEMENT = 0x785, 206 MLX5_CMD_OP_CREATE_QOS_PARA_VPORT = 0x786, 207 MLX5_CMD_OP_DESTROY_QOS_PARA_VPORT = 0x787, 208 MLX5_CMD_OP_ALLOC_PD = 0x800, 209 MLX5_CMD_OP_DEALLOC_PD = 0x801, 210 MLX5_CMD_OP_ALLOC_UAR = 0x802, 211 MLX5_CMD_OP_DEALLOC_UAR = 0x803, 212 MLX5_CMD_OP_CONFIG_INT_MODERATION = 0x804, 213 MLX5_CMD_OP_ACCESS_REG = 0x805, 214 MLX5_CMD_OP_ATTACH_TO_MCG = 0x806, 215 MLX5_CMD_OP_DETACH_FROM_MCG = 0x807, 216 MLX5_CMD_OP_GET_DROPPED_PACKET_LOG = 0x80a, 217 MLX5_CMD_OP_MAD_IFC = 0x50d, 218 MLX5_CMD_OP_QUERY_MAD_DEMUX = 0x80b, 219 MLX5_CMD_OP_SET_MAD_DEMUX = 0x80c, 220 MLX5_CMD_OP_NOP = 0x80d, 221 MLX5_CMD_OP_ALLOC_XRCD = 0x80e, 222 MLX5_CMD_OP_DEALLOC_XRCD = 0x80f, 223 MLX5_CMD_OP_ALLOC_TRANSPORT_DOMAIN = 0x816, 224 MLX5_CMD_OP_DEALLOC_TRANSPORT_DOMAIN = 0x817, 225 MLX5_CMD_OP_QUERY_CONG_STATUS = 0x822, 226 MLX5_CMD_OP_MODIFY_CONG_STATUS = 0x823, 227 MLX5_CMD_OP_QUERY_CONG_PARAMS = 0x824, 228 MLX5_CMD_OP_MODIFY_CONG_PARAMS = 0x825, 229 MLX5_CMD_OP_QUERY_CONG_STATISTICS = 0x826, 230 MLX5_CMD_OP_ADD_VXLAN_UDP_DPORT = 0x827, 231 MLX5_CMD_OP_DELETE_VXLAN_UDP_DPORT = 0x828, 232 MLX5_CMD_OP_SET_L2_TABLE_ENTRY = 0x829, 233 MLX5_CMD_OP_QUERY_L2_TABLE_ENTRY = 0x82a, 234 MLX5_CMD_OP_DELETE_L2_TABLE_ENTRY = 0x82b, 235 MLX5_CMD_OP_SET_WOL_ROL = 0x830, 236 MLX5_CMD_OP_QUERY_WOL_ROL = 0x831, 237 MLX5_CMD_OP_CREATE_LAG = 0x840, 238 MLX5_CMD_OP_MODIFY_LAG = 0x841, 239 MLX5_CMD_OP_QUERY_LAG = 0x842, 240 MLX5_CMD_OP_DESTROY_LAG = 0x843, 241 MLX5_CMD_OP_CREATE_VPORT_LAG = 0x844, 242 MLX5_CMD_OP_DESTROY_VPORT_LAG = 0x845, 243 MLX5_CMD_OP_CREATE_TIR = 0x900, 244 MLX5_CMD_OP_MODIFY_TIR = 0x901, 245 MLX5_CMD_OP_DESTROY_TIR = 0x902, 246 MLX5_CMD_OP_QUERY_TIR = 0x903, 247 MLX5_CMD_OP_CREATE_SQ = 0x904, 248 MLX5_CMD_OP_MODIFY_SQ = 0x905, 249 MLX5_CMD_OP_DESTROY_SQ = 0x906, 250 MLX5_CMD_OP_QUERY_SQ = 0x907, 251 MLX5_CMD_OP_CREATE_RQ = 0x908, 252 MLX5_CMD_OP_MODIFY_RQ = 0x909, 253 MLX5_CMD_OP_SET_DELAY_DROP_PARAMS = 0x910, 254 MLX5_CMD_OP_DESTROY_RQ = 0x90a, 255 MLX5_CMD_OP_QUERY_RQ = 0x90b, 256 MLX5_CMD_OP_CREATE_RMP = 0x90c, 257 MLX5_CMD_OP_MODIFY_RMP = 0x90d, 258 MLX5_CMD_OP_DESTROY_RMP = 0x90e, 259 MLX5_CMD_OP_QUERY_RMP = 0x90f, 260 MLX5_CMD_OP_CREATE_TIS = 0x912, 261 MLX5_CMD_OP_MODIFY_TIS = 0x913, 262 MLX5_CMD_OP_DESTROY_TIS = 0x914, 263 MLX5_CMD_OP_QUERY_TIS = 0x915, 264 MLX5_CMD_OP_CREATE_RQT = 0x916, 265 MLX5_CMD_OP_MODIFY_RQT = 0x917, 266 MLX5_CMD_OP_DESTROY_RQT = 0x918, 267 MLX5_CMD_OP_QUERY_RQT = 0x919, 268 MLX5_CMD_OP_SET_FLOW_TABLE_ROOT = 0x92f, 269 MLX5_CMD_OP_CREATE_FLOW_TABLE = 0x930, 270 MLX5_CMD_OP_DESTROY_FLOW_TABLE = 0x931, 271 MLX5_CMD_OP_QUERY_FLOW_TABLE = 0x932, 272 MLX5_CMD_OP_CREATE_FLOW_GROUP = 0x933, 273 MLX5_CMD_OP_DESTROY_FLOW_GROUP = 0x934, 274 MLX5_CMD_OP_QUERY_FLOW_GROUP = 0x935, 275 MLX5_CMD_OP_SET_FLOW_TABLE_ENTRY = 0x936, 276 MLX5_CMD_OP_QUERY_FLOW_TABLE_ENTRY = 0x937, 277 MLX5_CMD_OP_DELETE_FLOW_TABLE_ENTRY = 0x938, 278 MLX5_CMD_OP_ALLOC_FLOW_COUNTER = 0x939, 279 MLX5_CMD_OP_DEALLOC_FLOW_COUNTER = 0x93a, 280 MLX5_CMD_OP_QUERY_FLOW_COUNTER = 0x93b, 281 MLX5_CMD_OP_MODIFY_FLOW_TABLE = 0x93c, 282 MLX5_CMD_OP_ALLOC_PACKET_REFORMAT_CONTEXT = 0x93d, 283 MLX5_CMD_OP_DEALLOC_PACKET_REFORMAT_CONTEXT = 0x93e, 284 MLX5_CMD_OP_QUERY_PACKET_REFORMAT_CONTEXT = 0x93f, 285 MLX5_CMD_OP_ALLOC_MODIFY_HEADER_CONTEXT = 0x940, 286 MLX5_CMD_OP_DEALLOC_MODIFY_HEADER_CONTEXT = 0x941, 287 MLX5_CMD_OP_QUERY_MODIFY_HEADER_CONTEXT = 0x942, 288 MLX5_CMD_OP_FPGA_CREATE_QP = 0x960, 289 MLX5_CMD_OP_FPGA_MODIFY_QP = 0x961, 290 MLX5_CMD_OP_FPGA_QUERY_QP = 0x962, 291 MLX5_CMD_OP_FPGA_DESTROY_QP = 0x963, 292 MLX5_CMD_OP_FPGA_QUERY_QP_COUNTERS = 0x964, 293 MLX5_CMD_OP_CREATE_GENERAL_OBJECT = 0xa00, 294 MLX5_CMD_OP_MODIFY_GENERAL_OBJECT = 0xa01, 295 MLX5_CMD_OP_QUERY_GENERAL_OBJECT = 0xa02, 296 MLX5_CMD_OP_DESTROY_GENERAL_OBJECT = 0xa03, 297 MLX5_CMD_OP_CREATE_UCTX = 0xa04, 298 MLX5_CMD_OP_DESTROY_UCTX = 0xa06, 299 MLX5_CMD_OP_CREATE_UMEM = 0xa08, 300 MLX5_CMD_OP_DESTROY_UMEM = 0xa0a, 301 MLX5_CMD_OP_SYNC_STEERING = 0xb00, 302 MLX5_CMD_OP_QUERY_VHCA_STATE = 0xb0d, 303 MLX5_CMD_OP_MODIFY_VHCA_STATE = 0xb0e, 304 MLX5_CMD_OP_MAX 305 }; 306 307 /* Valid range for general commands that don't work over an object */ 308 enum { 309 MLX5_CMD_OP_GENERAL_START = 0xb00, 310 MLX5_CMD_OP_GENERAL_END = 0xd00, 311 }; 312 313 struct mlx5_ifc_flow_table_fields_supported_bits { 314 u8 outer_dmac[0x1]; 315 u8 outer_smac[0x1]; 316 u8 outer_ether_type[0x1]; 317 u8 outer_ip_version[0x1]; 318 u8 outer_first_prio[0x1]; 319 u8 outer_first_cfi[0x1]; 320 u8 outer_first_vid[0x1]; 321 u8 outer_ipv4_ttl[0x1]; 322 u8 outer_second_prio[0x1]; 323 u8 outer_second_cfi[0x1]; 324 u8 outer_second_vid[0x1]; 325 u8 reserved_at_b[0x1]; 326 u8 outer_sip[0x1]; 327 u8 outer_dip[0x1]; 328 u8 outer_frag[0x1]; 329 u8 outer_ip_protocol[0x1]; 330 u8 outer_ip_ecn[0x1]; 331 u8 outer_ip_dscp[0x1]; 332 u8 outer_udp_sport[0x1]; 333 u8 outer_udp_dport[0x1]; 334 u8 outer_tcp_sport[0x1]; 335 u8 outer_tcp_dport[0x1]; 336 u8 outer_tcp_flags[0x1]; 337 u8 outer_gre_protocol[0x1]; 338 u8 outer_gre_key[0x1]; 339 u8 outer_vxlan_vni[0x1]; 340 u8 outer_geneve_vni[0x1]; 341 u8 outer_geneve_oam[0x1]; 342 u8 outer_geneve_protocol_type[0x1]; 343 u8 outer_geneve_opt_len[0x1]; 344 u8 source_vhca_port[0x1]; 345 u8 source_eswitch_port[0x1]; 346 347 u8 inner_dmac[0x1]; 348 u8 inner_smac[0x1]; 349 u8 inner_ether_type[0x1]; 350 u8 inner_ip_version[0x1]; 351 u8 inner_first_prio[0x1]; 352 u8 inner_first_cfi[0x1]; 353 u8 inner_first_vid[0x1]; 354 u8 reserved_at_27[0x1]; 355 u8 inner_second_prio[0x1]; 356 u8 inner_second_cfi[0x1]; 357 u8 inner_second_vid[0x1]; 358 u8 reserved_at_2b[0x1]; 359 u8 inner_sip[0x1]; 360 u8 inner_dip[0x1]; 361 u8 inner_frag[0x1]; 362 u8 inner_ip_protocol[0x1]; 363 u8 inner_ip_ecn[0x1]; 364 u8 inner_ip_dscp[0x1]; 365 u8 inner_udp_sport[0x1]; 366 u8 inner_udp_dport[0x1]; 367 u8 inner_tcp_sport[0x1]; 368 u8 inner_tcp_dport[0x1]; 369 u8 inner_tcp_flags[0x1]; 370 u8 reserved_at_37[0x9]; 371 372 u8 geneve_tlv_option_0_data[0x1]; 373 u8 geneve_tlv_option_0_exist[0x1]; 374 u8 reserved_at_42[0x3]; 375 u8 outer_first_mpls_over_udp[0x4]; 376 u8 outer_first_mpls_over_gre[0x4]; 377 u8 inner_first_mpls[0x4]; 378 u8 outer_first_mpls[0x4]; 379 u8 reserved_at_55[0x2]; 380 u8 outer_esp_spi[0x1]; 381 u8 reserved_at_58[0x2]; 382 u8 bth_dst_qp[0x1]; 383 u8 reserved_at_5b[0x5]; 384 385 u8 reserved_at_60[0x18]; 386 u8 metadata_reg_c_7[0x1]; 387 u8 metadata_reg_c_6[0x1]; 388 u8 metadata_reg_c_5[0x1]; 389 u8 metadata_reg_c_4[0x1]; 390 u8 metadata_reg_c_3[0x1]; 391 u8 metadata_reg_c_2[0x1]; 392 u8 metadata_reg_c_1[0x1]; 393 u8 metadata_reg_c_0[0x1]; 394 }; 395 396 struct mlx5_ifc_flow_table_fields_supported_2_bits { 397 u8 reserved_at_0[0xe]; 398 u8 bth_opcode[0x1]; 399 u8 reserved_at_f[0x11]; 400 401 u8 reserved_at_20[0x60]; 402 }; 403 404 struct mlx5_ifc_flow_table_prop_layout_bits { 405 u8 ft_support[0x1]; 406 u8 reserved_at_1[0x1]; 407 u8 flow_counter[0x1]; 408 u8 flow_modify_en[0x1]; 409 u8 modify_root[0x1]; 410 u8 identified_miss_table_mode[0x1]; 411 u8 flow_table_modify[0x1]; 412 u8 reformat[0x1]; 413 u8 decap[0x1]; 414 u8 reserved_at_9[0x1]; 415 u8 pop_vlan[0x1]; 416 u8 push_vlan[0x1]; 417 u8 reserved_at_c[0x1]; 418 u8 pop_vlan_2[0x1]; 419 u8 push_vlan_2[0x1]; 420 u8 reformat_and_vlan_action[0x1]; 421 u8 reserved_at_10[0x1]; 422 u8 sw_owner[0x1]; 423 u8 reformat_l3_tunnel_to_l2[0x1]; 424 u8 reformat_l2_to_l3_tunnel[0x1]; 425 u8 reformat_and_modify_action[0x1]; 426 u8 ignore_flow_level[0x1]; 427 u8 reserved_at_16[0x1]; 428 u8 table_miss_action_domain[0x1]; 429 u8 termination_table[0x1]; 430 u8 reformat_and_fwd_to_table[0x1]; 431 u8 reserved_at_1a[0x2]; 432 u8 ipsec_encrypt[0x1]; 433 u8 ipsec_decrypt[0x1]; 434 u8 sw_owner_v2[0x1]; 435 u8 reserved_at_1f[0x1]; 436 437 u8 termination_table_raw_traffic[0x1]; 438 u8 reserved_at_21[0x1]; 439 u8 log_max_ft_size[0x6]; 440 u8 log_max_modify_header_context[0x8]; 441 u8 max_modify_header_actions[0x8]; 442 u8 max_ft_level[0x8]; 443 444 u8 reserved_at_40[0x20]; 445 446 u8 reserved_at_60[0x2]; 447 u8 reformat_insert[0x1]; 448 u8 reformat_remove[0x1]; 449 u8 reserver_at_64[0x14]; 450 u8 log_max_ft_num[0x8]; 451 452 u8 reserved_at_80[0x10]; 453 u8 log_max_flow_counter[0x8]; 454 u8 log_max_destination[0x8]; 455 456 u8 reserved_at_a0[0x18]; 457 u8 log_max_flow[0x8]; 458 459 u8 reserved_at_c0[0x40]; 460 461 struct mlx5_ifc_flow_table_fields_supported_bits ft_field_support; 462 463 struct mlx5_ifc_flow_table_fields_supported_bits ft_field_bitmask_support; 464 }; 465 466 struct mlx5_ifc_odp_per_transport_service_cap_bits { 467 u8 send[0x1]; 468 u8 receive[0x1]; 469 u8 write[0x1]; 470 u8 read[0x1]; 471 u8 atomic[0x1]; 472 u8 srq_receive[0x1]; 473 u8 reserved_at_6[0x1a]; 474 }; 475 476 struct mlx5_ifc_fte_match_set_lyr_2_4_bits { 477 u8 smac_47_16[0x20]; 478 479 u8 smac_15_0[0x10]; 480 u8 ethertype[0x10]; 481 482 u8 dmac_47_16[0x20]; 483 484 u8 dmac_15_0[0x10]; 485 u8 first_prio[0x3]; 486 u8 first_cfi[0x1]; 487 u8 first_vid[0xc]; 488 489 u8 ip_protocol[0x8]; 490 u8 ip_dscp[0x6]; 491 u8 ip_ecn[0x2]; 492 u8 cvlan_tag[0x1]; 493 u8 svlan_tag[0x1]; 494 u8 frag[0x1]; 495 u8 ip_version[0x4]; 496 u8 tcp_flags[0x9]; 497 498 u8 tcp_sport[0x10]; 499 u8 tcp_dport[0x10]; 500 501 u8 reserved_at_c0[0x10]; 502 u8 ipv4_ihl[0x4]; 503 u8 reserved_at_c4[0x4]; 504 505 u8 ttl_hoplimit[0x8]; 506 507 u8 udp_sport[0x10]; 508 u8 udp_dport[0x10]; 509 510 union mlx5_ifc_ipv6_layout_ipv4_layout_auto_bits src_ipv4_src_ipv6; 511 512 union mlx5_ifc_ipv6_layout_ipv4_layout_auto_bits dst_ipv4_dst_ipv6; 513 }; 514 515 struct mlx5_ifc_nvgre_key_bits { 516 u8 hi[0x18]; 517 u8 lo[0x8]; 518 }; 519 520 union mlx5_ifc_gre_key_bits { 521 struct mlx5_ifc_nvgre_key_bits nvgre; 522 u8 key[0x20]; 523 }; 524 525 struct mlx5_ifc_fte_match_set_misc_bits { 526 u8 gre_c_present[0x1]; 527 u8 reserved_at_1[0x1]; 528 u8 gre_k_present[0x1]; 529 u8 gre_s_present[0x1]; 530 u8 source_vhca_port[0x4]; 531 u8 source_sqn[0x18]; 532 533 u8 source_eswitch_owner_vhca_id[0x10]; 534 u8 source_port[0x10]; 535 536 u8 outer_second_prio[0x3]; 537 u8 outer_second_cfi[0x1]; 538 u8 outer_second_vid[0xc]; 539 u8 inner_second_prio[0x3]; 540 u8 inner_second_cfi[0x1]; 541 u8 inner_second_vid[0xc]; 542 543 u8 outer_second_cvlan_tag[0x1]; 544 u8 inner_second_cvlan_tag[0x1]; 545 u8 outer_second_svlan_tag[0x1]; 546 u8 inner_second_svlan_tag[0x1]; 547 u8 reserved_at_64[0xc]; 548 u8 gre_protocol[0x10]; 549 550 union mlx5_ifc_gre_key_bits gre_key; 551 552 u8 vxlan_vni[0x18]; 553 u8 bth_opcode[0x8]; 554 555 u8 geneve_vni[0x18]; 556 u8 reserved_at_d8[0x6]; 557 u8 geneve_tlv_option_0_exist[0x1]; 558 u8 geneve_oam[0x1]; 559 560 u8 reserved_at_e0[0xc]; 561 u8 outer_ipv6_flow_label[0x14]; 562 563 u8 reserved_at_100[0xc]; 564 u8 inner_ipv6_flow_label[0x14]; 565 566 u8 reserved_at_120[0xa]; 567 u8 geneve_opt_len[0x6]; 568 u8 geneve_protocol_type[0x10]; 569 570 u8 reserved_at_140[0x8]; 571 u8 bth_dst_qp[0x18]; 572 u8 reserved_at_160[0x20]; 573 u8 outer_esp_spi[0x20]; 574 u8 reserved_at_1a0[0x60]; 575 }; 576 577 struct mlx5_ifc_fte_match_mpls_bits { 578 u8 mpls_label[0x14]; 579 u8 mpls_exp[0x3]; 580 u8 mpls_s_bos[0x1]; 581 u8 mpls_ttl[0x8]; 582 }; 583 584 struct mlx5_ifc_fte_match_set_misc2_bits { 585 struct mlx5_ifc_fte_match_mpls_bits outer_first_mpls; 586 587 struct mlx5_ifc_fte_match_mpls_bits inner_first_mpls; 588 589 struct mlx5_ifc_fte_match_mpls_bits outer_first_mpls_over_gre; 590 591 struct mlx5_ifc_fte_match_mpls_bits outer_first_mpls_over_udp; 592 593 u8 metadata_reg_c_7[0x20]; 594 595 u8 metadata_reg_c_6[0x20]; 596 597 u8 metadata_reg_c_5[0x20]; 598 599 u8 metadata_reg_c_4[0x20]; 600 601 u8 metadata_reg_c_3[0x20]; 602 603 u8 metadata_reg_c_2[0x20]; 604 605 u8 metadata_reg_c_1[0x20]; 606 607 u8 metadata_reg_c_0[0x20]; 608 609 u8 metadata_reg_a[0x20]; 610 611 u8 reserved_at_1a0[0x60]; 612 }; 613 614 struct mlx5_ifc_fte_match_set_misc3_bits { 615 u8 inner_tcp_seq_num[0x20]; 616 617 u8 outer_tcp_seq_num[0x20]; 618 619 u8 inner_tcp_ack_num[0x20]; 620 621 u8 outer_tcp_ack_num[0x20]; 622 623 u8 reserved_at_80[0x8]; 624 u8 outer_vxlan_gpe_vni[0x18]; 625 626 u8 outer_vxlan_gpe_next_protocol[0x8]; 627 u8 outer_vxlan_gpe_flags[0x8]; 628 u8 reserved_at_b0[0x10]; 629 630 u8 icmp_header_data[0x20]; 631 632 u8 icmpv6_header_data[0x20]; 633 634 u8 icmp_type[0x8]; 635 u8 icmp_code[0x8]; 636 u8 icmpv6_type[0x8]; 637 u8 icmpv6_code[0x8]; 638 639 u8 geneve_tlv_option_0_data[0x20]; 640 641 u8 gtpu_teid[0x20]; 642 643 u8 gtpu_msg_type[0x8]; 644 u8 gtpu_msg_flags[0x8]; 645 u8 reserved_at_170[0x10]; 646 647 u8 gtpu_dw_2[0x20]; 648 649 u8 gtpu_first_ext_dw_0[0x20]; 650 651 u8 gtpu_dw_0[0x20]; 652 653 u8 reserved_at_1e0[0x20]; 654 }; 655 656 struct mlx5_ifc_fte_match_set_misc4_bits { 657 u8 prog_sample_field_value_0[0x20]; 658 659 u8 prog_sample_field_id_0[0x20]; 660 661 u8 prog_sample_field_value_1[0x20]; 662 663 u8 prog_sample_field_id_1[0x20]; 664 665 u8 prog_sample_field_value_2[0x20]; 666 667 u8 prog_sample_field_id_2[0x20]; 668 669 u8 prog_sample_field_value_3[0x20]; 670 671 u8 prog_sample_field_id_3[0x20]; 672 673 u8 reserved_at_100[0x100]; 674 }; 675 676 struct mlx5_ifc_fte_match_set_misc5_bits { 677 u8 macsec_tag_0[0x20]; 678 679 u8 macsec_tag_1[0x20]; 680 681 u8 macsec_tag_2[0x20]; 682 683 u8 macsec_tag_3[0x20]; 684 685 u8 tunnel_header_0[0x20]; 686 687 u8 tunnel_header_1[0x20]; 688 689 u8 tunnel_header_2[0x20]; 690 691 u8 tunnel_header_3[0x20]; 692 693 u8 reserved_at_100[0x100]; 694 }; 695 696 struct mlx5_ifc_cmd_pas_bits { 697 u8 pa_h[0x20]; 698 699 u8 pa_l[0x14]; 700 u8 reserved_at_34[0xc]; 701 }; 702 703 struct mlx5_ifc_uint64_bits { 704 u8 hi[0x20]; 705 706 u8 lo[0x20]; 707 }; 708 709 enum { 710 MLX5_ADS_STAT_RATE_NO_LIMIT = 0x0, 711 MLX5_ADS_STAT_RATE_2_5GBPS = 0x7, 712 MLX5_ADS_STAT_RATE_10GBPS = 0x8, 713 MLX5_ADS_STAT_RATE_30GBPS = 0x9, 714 MLX5_ADS_STAT_RATE_5GBPS = 0xa, 715 MLX5_ADS_STAT_RATE_20GBPS = 0xb, 716 MLX5_ADS_STAT_RATE_40GBPS = 0xc, 717 MLX5_ADS_STAT_RATE_60GBPS = 0xd, 718 MLX5_ADS_STAT_RATE_80GBPS = 0xe, 719 MLX5_ADS_STAT_RATE_120GBPS = 0xf, 720 }; 721 722 struct mlx5_ifc_ads_bits { 723 u8 fl[0x1]; 724 u8 free_ar[0x1]; 725 u8 reserved_at_2[0xe]; 726 u8 pkey_index[0x10]; 727 728 u8 reserved_at_20[0x8]; 729 u8 grh[0x1]; 730 u8 mlid[0x7]; 731 u8 rlid[0x10]; 732 733 u8 ack_timeout[0x5]; 734 u8 reserved_at_45[0x3]; 735 u8 src_addr_index[0x8]; 736 u8 reserved_at_50[0x4]; 737 u8 stat_rate[0x4]; 738 u8 hop_limit[0x8]; 739 740 u8 reserved_at_60[0x4]; 741 u8 tclass[0x8]; 742 u8 flow_label[0x14]; 743 744 u8 rgid_rip[16][0x8]; 745 746 u8 reserved_at_100[0x4]; 747 u8 f_dscp[0x1]; 748 u8 f_ecn[0x1]; 749 u8 reserved_at_106[0x1]; 750 u8 f_eth_prio[0x1]; 751 u8 ecn[0x2]; 752 u8 dscp[0x6]; 753 u8 udp_sport[0x10]; 754 755 u8 dei_cfi[0x1]; 756 u8 eth_prio[0x3]; 757 u8 sl[0x4]; 758 u8 vhca_port_num[0x8]; 759 u8 rmac_47_32[0x10]; 760 761 u8 rmac_31_0[0x20]; 762 }; 763 764 struct mlx5_ifc_flow_table_nic_cap_bits { 765 u8 nic_rx_multi_path_tirs[0x1]; 766 u8 nic_rx_multi_path_tirs_fts[0x1]; 767 u8 allow_sniffer_and_nic_rx_shared_tir[0x1]; 768 u8 reserved_at_3[0x4]; 769 u8 sw_owner_reformat_supported[0x1]; 770 u8 reserved_at_8[0x18]; 771 772 u8 encap_general_header[0x1]; 773 u8 reserved_at_21[0xa]; 774 u8 log_max_packet_reformat_context[0x5]; 775 u8 reserved_at_30[0x6]; 776 u8 max_encap_header_size[0xa]; 777 u8 reserved_at_40[0x1c0]; 778 779 struct mlx5_ifc_flow_table_prop_layout_bits flow_table_properties_nic_receive; 780 781 struct mlx5_ifc_flow_table_prop_layout_bits flow_table_properties_nic_receive_rdma; 782 783 struct mlx5_ifc_flow_table_prop_layout_bits flow_table_properties_nic_receive_sniffer; 784 785 struct mlx5_ifc_flow_table_prop_layout_bits flow_table_properties_nic_transmit; 786 787 struct mlx5_ifc_flow_table_prop_layout_bits flow_table_properties_nic_transmit_rdma; 788 789 struct mlx5_ifc_flow_table_prop_layout_bits flow_table_properties_nic_transmit_sniffer; 790 791 u8 reserved_at_e00[0x700]; 792 793 struct mlx5_ifc_flow_table_fields_supported_2_bits ft_field_support_2_nic_receive_rdma; 794 795 u8 reserved_at_1580[0x280]; 796 797 struct mlx5_ifc_flow_table_fields_supported_2_bits ft_field_support_2_nic_transmit_rdma; 798 799 u8 reserved_at_1880[0x780]; 800 801 u8 sw_steering_nic_rx_action_drop_icm_address[0x40]; 802 803 u8 sw_steering_nic_tx_action_drop_icm_address[0x40]; 804 805 u8 sw_steering_nic_tx_action_allow_icm_address[0x40]; 806 807 u8 reserved_at_20c0[0x5f40]; 808 }; 809 810 struct mlx5_ifc_port_selection_cap_bits { 811 u8 reserved_at_0[0x10]; 812 u8 port_select_flow_table[0x1]; 813 u8 reserved_at_11[0xf]; 814 815 u8 reserved_at_20[0x1e0]; 816 817 struct mlx5_ifc_flow_table_prop_layout_bits flow_table_properties_port_selection; 818 819 u8 reserved_at_400[0x7c00]; 820 }; 821 822 enum { 823 MLX5_FDB_TO_VPORT_REG_C_0 = 0x01, 824 MLX5_FDB_TO_VPORT_REG_C_1 = 0x02, 825 MLX5_FDB_TO_VPORT_REG_C_2 = 0x04, 826 MLX5_FDB_TO_VPORT_REG_C_3 = 0x08, 827 MLX5_FDB_TO_VPORT_REG_C_4 = 0x10, 828 MLX5_FDB_TO_VPORT_REG_C_5 = 0x20, 829 MLX5_FDB_TO_VPORT_REG_C_6 = 0x40, 830 MLX5_FDB_TO_VPORT_REG_C_7 = 0x80, 831 }; 832 833 struct mlx5_ifc_flow_table_eswitch_cap_bits { 834 u8 fdb_to_vport_reg_c_id[0x8]; 835 u8 reserved_at_8[0xd]; 836 u8 fdb_modify_header_fwd_to_table[0x1]; 837 u8 fdb_ipv4_ttl_modify[0x1]; 838 u8 flow_source[0x1]; 839 u8 reserved_at_18[0x2]; 840 u8 multi_fdb_encap[0x1]; 841 u8 egress_acl_forward_to_vport[0x1]; 842 u8 fdb_multi_path_to_table[0x1]; 843 u8 reserved_at_1d[0x3]; 844 845 u8 reserved_at_20[0x1e0]; 846 847 struct mlx5_ifc_flow_table_prop_layout_bits flow_table_properties_nic_esw_fdb; 848 849 struct mlx5_ifc_flow_table_prop_layout_bits flow_table_properties_esw_acl_ingress; 850 851 struct mlx5_ifc_flow_table_prop_layout_bits flow_table_properties_esw_acl_egress; 852 853 u8 reserved_at_800[0x1000]; 854 855 u8 sw_steering_fdb_action_drop_icm_address_rx[0x40]; 856 857 u8 sw_steering_fdb_action_drop_icm_address_tx[0x40]; 858 859 u8 sw_steering_uplink_icm_address_rx[0x40]; 860 861 u8 sw_steering_uplink_icm_address_tx[0x40]; 862 863 u8 reserved_at_1900[0x6700]; 864 }; 865 866 enum { 867 MLX5_COUNTER_SOURCE_ESWITCH = 0x0, 868 MLX5_COUNTER_FLOW_ESWITCH = 0x1, 869 }; 870 871 struct mlx5_ifc_e_switch_cap_bits { 872 u8 vport_svlan_strip[0x1]; 873 u8 vport_cvlan_strip[0x1]; 874 u8 vport_svlan_insert[0x1]; 875 u8 vport_cvlan_insert_if_not_exist[0x1]; 876 u8 vport_cvlan_insert_overwrite[0x1]; 877 u8 reserved_at_5[0x2]; 878 u8 esw_shared_ingress_acl[0x1]; 879 u8 esw_uplink_ingress_acl[0x1]; 880 u8 root_ft_on_other_esw[0x1]; 881 u8 reserved_at_a[0xf]; 882 u8 esw_functions_changed[0x1]; 883 u8 reserved_at_1a[0x1]; 884 u8 ecpf_vport_exists[0x1]; 885 u8 counter_eswitch_affinity[0x1]; 886 u8 merged_eswitch[0x1]; 887 u8 nic_vport_node_guid_modify[0x1]; 888 u8 nic_vport_port_guid_modify[0x1]; 889 890 u8 vxlan_encap_decap[0x1]; 891 u8 nvgre_encap_decap[0x1]; 892 u8 reserved_at_22[0x1]; 893 u8 log_max_fdb_encap_uplink[0x5]; 894 u8 reserved_at_21[0x3]; 895 u8 log_max_packet_reformat_context[0x5]; 896 u8 reserved_2b[0x6]; 897 u8 max_encap_header_size[0xa]; 898 899 u8 reserved_at_40[0xb]; 900 u8 log_max_esw_sf[0x5]; 901 u8 esw_sf_base_id[0x10]; 902 903 u8 reserved_at_60[0x7a0]; 904 905 }; 906 907 struct mlx5_ifc_qos_cap_bits { 908 u8 packet_pacing[0x1]; 909 u8 esw_scheduling[0x1]; 910 u8 esw_bw_share[0x1]; 911 u8 esw_rate_limit[0x1]; 912 u8 reserved_at_4[0x1]; 913 u8 packet_pacing_burst_bound[0x1]; 914 u8 packet_pacing_typical_size[0x1]; 915 u8 reserved_at_7[0x1]; 916 u8 nic_sq_scheduling[0x1]; 917 u8 nic_bw_share[0x1]; 918 u8 nic_rate_limit[0x1]; 919 u8 packet_pacing_uid[0x1]; 920 u8 log_esw_max_sched_depth[0x4]; 921 u8 reserved_at_10[0x10]; 922 923 u8 reserved_at_20[0xb]; 924 u8 log_max_qos_nic_queue_group[0x5]; 925 u8 reserved_at_30[0x10]; 926 927 u8 packet_pacing_max_rate[0x20]; 928 929 u8 packet_pacing_min_rate[0x20]; 930 931 u8 reserved_at_80[0x10]; 932 u8 packet_pacing_rate_table_size[0x10]; 933 934 u8 esw_element_type[0x10]; 935 u8 esw_tsar_type[0x10]; 936 937 u8 reserved_at_c0[0x10]; 938 u8 max_qos_para_vport[0x10]; 939 940 u8 max_tsar_bw_share[0x20]; 941 942 u8 reserved_at_100[0x700]; 943 }; 944 945 struct mlx5_ifc_debug_cap_bits { 946 u8 core_dump_general[0x1]; 947 u8 core_dump_qp[0x1]; 948 u8 reserved_at_2[0x7]; 949 u8 resource_dump[0x1]; 950 u8 reserved_at_a[0x16]; 951 952 u8 reserved_at_20[0x2]; 953 u8 stall_detect[0x1]; 954 u8 reserved_at_23[0x1d]; 955 956 u8 reserved_at_40[0x7c0]; 957 }; 958 959 struct mlx5_ifc_per_protocol_networking_offload_caps_bits { 960 u8 csum_cap[0x1]; 961 u8 vlan_cap[0x1]; 962 u8 lro_cap[0x1]; 963 u8 lro_psh_flag[0x1]; 964 u8 lro_time_stamp[0x1]; 965 u8 reserved_at_5[0x2]; 966 u8 wqe_vlan_insert[0x1]; 967 u8 self_lb_en_modifiable[0x1]; 968 u8 reserved_at_9[0x2]; 969 u8 max_lso_cap[0x5]; 970 u8 multi_pkt_send_wqe[0x2]; 971 u8 wqe_inline_mode[0x2]; 972 u8 rss_ind_tbl_cap[0x4]; 973 u8 reg_umr_sq[0x1]; 974 u8 scatter_fcs[0x1]; 975 u8 enhanced_multi_pkt_send_wqe[0x1]; 976 u8 tunnel_lso_const_out_ip_id[0x1]; 977 u8 tunnel_lro_gre[0x1]; 978 u8 tunnel_lro_vxlan[0x1]; 979 u8 tunnel_stateless_gre[0x1]; 980 u8 tunnel_stateless_vxlan[0x1]; 981 982 u8 swp[0x1]; 983 u8 swp_csum[0x1]; 984 u8 swp_lso[0x1]; 985 u8 cqe_checksum_full[0x1]; 986 u8 tunnel_stateless_geneve_tx[0x1]; 987 u8 tunnel_stateless_mpls_over_udp[0x1]; 988 u8 tunnel_stateless_mpls_over_gre[0x1]; 989 u8 tunnel_stateless_vxlan_gpe[0x1]; 990 u8 tunnel_stateless_ipv4_over_vxlan[0x1]; 991 u8 tunnel_stateless_ip_over_ip[0x1]; 992 u8 insert_trailer[0x1]; 993 u8 reserved_at_2b[0x1]; 994 u8 tunnel_stateless_ip_over_ip_rx[0x1]; 995 u8 tunnel_stateless_ip_over_ip_tx[0x1]; 996 u8 reserved_at_2e[0x2]; 997 u8 max_vxlan_udp_ports[0x8]; 998 u8 reserved_at_38[0x6]; 999 u8 max_geneve_opt_len[0x1]; 1000 u8 tunnel_stateless_geneve_rx[0x1]; 1001 1002 u8 reserved_at_40[0x10]; 1003 u8 lro_min_mss_size[0x10]; 1004 1005 u8 reserved_at_60[0x120]; 1006 1007 u8 lro_timer_supported_periods[4][0x20]; 1008 1009 u8 reserved_at_200[0x600]; 1010 }; 1011 1012 enum { 1013 MLX5_TIMESTAMP_FORMAT_CAP_FREE_RUNNING = 0x0, 1014 MLX5_TIMESTAMP_FORMAT_CAP_REAL_TIME = 0x1, 1015 MLX5_TIMESTAMP_FORMAT_CAP_FREE_RUNNING_AND_REAL_TIME = 0x2, 1016 }; 1017 1018 struct mlx5_ifc_roce_cap_bits { 1019 u8 roce_apm[0x1]; 1020 u8 reserved_at_1[0x3]; 1021 u8 sw_r_roce_src_udp_port[0x1]; 1022 u8 fl_rc_qp_when_roce_disabled[0x1]; 1023 u8 fl_rc_qp_when_roce_enabled[0x1]; 1024 u8 reserved_at_7[0x17]; 1025 u8 qp_ts_format[0x2]; 1026 1027 u8 reserved_at_20[0x60]; 1028 1029 u8 reserved_at_80[0xc]; 1030 u8 l3_type[0x4]; 1031 u8 reserved_at_90[0x8]; 1032 u8 roce_version[0x8]; 1033 1034 u8 reserved_at_a0[0x10]; 1035 u8 r_roce_dest_udp_port[0x10]; 1036 1037 u8 r_roce_max_src_udp_port[0x10]; 1038 u8 r_roce_min_src_udp_port[0x10]; 1039 1040 u8 reserved_at_e0[0x10]; 1041 u8 roce_address_table_size[0x10]; 1042 1043 u8 reserved_at_100[0x700]; 1044 }; 1045 1046 struct mlx5_ifc_sync_steering_in_bits { 1047 u8 opcode[0x10]; 1048 u8 uid[0x10]; 1049 1050 u8 reserved_at_20[0x10]; 1051 u8 op_mod[0x10]; 1052 1053 u8 reserved_at_40[0xc0]; 1054 }; 1055 1056 struct mlx5_ifc_sync_steering_out_bits { 1057 u8 status[0x8]; 1058 u8 reserved_at_8[0x18]; 1059 1060 u8 syndrome[0x20]; 1061 1062 u8 reserved_at_40[0x40]; 1063 }; 1064 1065 struct mlx5_ifc_device_mem_cap_bits { 1066 u8 memic[0x1]; 1067 u8 reserved_at_1[0x1f]; 1068 1069 u8 reserved_at_20[0xb]; 1070 u8 log_min_memic_alloc_size[0x5]; 1071 u8 reserved_at_30[0x8]; 1072 u8 log_max_memic_addr_alignment[0x8]; 1073 1074 u8 memic_bar_start_addr[0x40]; 1075 1076 u8 memic_bar_size[0x20]; 1077 1078 u8 max_memic_size[0x20]; 1079 1080 u8 steering_sw_icm_start_address[0x40]; 1081 1082 u8 reserved_at_100[0x8]; 1083 u8 log_header_modify_sw_icm_size[0x8]; 1084 u8 reserved_at_110[0x2]; 1085 u8 log_sw_icm_alloc_granularity[0x6]; 1086 u8 log_steering_sw_icm_size[0x8]; 1087 1088 u8 reserved_at_120[0x20]; 1089 1090 u8 header_modify_sw_icm_start_address[0x40]; 1091 1092 u8 reserved_at_180[0x80]; 1093 1094 u8 memic_operations[0x20]; 1095 1096 u8 reserved_at_220[0x5e0]; 1097 }; 1098 1099 struct mlx5_ifc_device_event_cap_bits { 1100 u8 user_affiliated_events[4][0x40]; 1101 1102 u8 user_unaffiliated_events[4][0x40]; 1103 }; 1104 1105 struct mlx5_ifc_virtio_emulation_cap_bits { 1106 u8 desc_tunnel_offload_type[0x1]; 1107 u8 eth_frame_offload_type[0x1]; 1108 u8 virtio_version_1_0[0x1]; 1109 u8 device_features_bits_mask[0xd]; 1110 u8 event_mode[0x8]; 1111 u8 virtio_queue_type[0x8]; 1112 1113 u8 max_tunnel_desc[0x10]; 1114 u8 reserved_at_30[0x3]; 1115 u8 log_doorbell_stride[0x5]; 1116 u8 reserved_at_38[0x3]; 1117 u8 log_doorbell_bar_size[0x5]; 1118 1119 u8 doorbell_bar_offset[0x40]; 1120 1121 u8 max_emulated_devices[0x8]; 1122 u8 max_num_virtio_queues[0x18]; 1123 1124 u8 reserved_at_a0[0x60]; 1125 1126 u8 umem_1_buffer_param_a[0x20]; 1127 1128 u8 umem_1_buffer_param_b[0x20]; 1129 1130 u8 umem_2_buffer_param_a[0x20]; 1131 1132 u8 umem_2_buffer_param_b[0x20]; 1133 1134 u8 umem_3_buffer_param_a[0x20]; 1135 1136 u8 umem_3_buffer_param_b[0x20]; 1137 1138 u8 reserved_at_1c0[0x640]; 1139 }; 1140 1141 enum { 1142 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_QP_1_BYTE = 0x0, 1143 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_QP_2_BYTES = 0x2, 1144 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_QP_4_BYTES = 0x4, 1145 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_QP_8_BYTES = 0x8, 1146 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_QP_16_BYTES = 0x10, 1147 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_QP_32_BYTES = 0x20, 1148 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_QP_64_BYTES = 0x40, 1149 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_QP_128_BYTES = 0x80, 1150 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_QP_256_BYTES = 0x100, 1151 }; 1152 1153 enum { 1154 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_DC_1_BYTE = 0x1, 1155 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_DC_2_BYTES = 0x2, 1156 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_DC_4_BYTES = 0x4, 1157 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_DC_8_BYTES = 0x8, 1158 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_DC_16_BYTES = 0x10, 1159 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_DC_32_BYTES = 0x20, 1160 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_DC_64_BYTES = 0x40, 1161 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_DC_128_BYTES = 0x80, 1162 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_DC_256_BYTES = 0x100, 1163 }; 1164 1165 struct mlx5_ifc_atomic_caps_bits { 1166 u8 reserved_at_0[0x40]; 1167 1168 u8 atomic_req_8B_endianness_mode[0x2]; 1169 u8 reserved_at_42[0x4]; 1170 u8 supported_atomic_req_8B_endianness_mode_1[0x1]; 1171 1172 u8 reserved_at_47[0x19]; 1173 1174 u8 reserved_at_60[0x20]; 1175 1176 u8 reserved_at_80[0x10]; 1177 u8 atomic_operations[0x10]; 1178 1179 u8 reserved_at_a0[0x10]; 1180 u8 atomic_size_qp[0x10]; 1181 1182 u8 reserved_at_c0[0x10]; 1183 u8 atomic_size_dc[0x10]; 1184 1185 u8 reserved_at_e0[0x720]; 1186 }; 1187 1188 struct mlx5_ifc_odp_cap_bits { 1189 u8 reserved_at_0[0x40]; 1190 1191 u8 sig[0x1]; 1192 u8 reserved_at_41[0x1f]; 1193 1194 u8 reserved_at_60[0x20]; 1195 1196 struct mlx5_ifc_odp_per_transport_service_cap_bits rc_odp_caps; 1197 1198 struct mlx5_ifc_odp_per_transport_service_cap_bits uc_odp_caps; 1199 1200 struct mlx5_ifc_odp_per_transport_service_cap_bits ud_odp_caps; 1201 1202 struct mlx5_ifc_odp_per_transport_service_cap_bits xrc_odp_caps; 1203 1204 struct mlx5_ifc_odp_per_transport_service_cap_bits dc_odp_caps; 1205 1206 u8 reserved_at_120[0x6E0]; 1207 }; 1208 1209 struct mlx5_ifc_calc_op { 1210 u8 reserved_at_0[0x10]; 1211 u8 reserved_at_10[0x9]; 1212 u8 op_swap_endianness[0x1]; 1213 u8 op_min[0x1]; 1214 u8 op_xor[0x1]; 1215 u8 op_or[0x1]; 1216 u8 op_and[0x1]; 1217 u8 op_max[0x1]; 1218 u8 op_add[0x1]; 1219 }; 1220 1221 struct mlx5_ifc_vector_calc_cap_bits { 1222 u8 calc_matrix[0x1]; 1223 u8 reserved_at_1[0x1f]; 1224 u8 reserved_at_20[0x8]; 1225 u8 max_vec_count[0x8]; 1226 u8 reserved_at_30[0xd]; 1227 u8 max_chunk_size[0x3]; 1228 struct mlx5_ifc_calc_op calc0; 1229 struct mlx5_ifc_calc_op calc1; 1230 struct mlx5_ifc_calc_op calc2; 1231 struct mlx5_ifc_calc_op calc3; 1232 1233 u8 reserved_at_c0[0x720]; 1234 }; 1235 1236 struct mlx5_ifc_tls_cap_bits { 1237 u8 tls_1_2_aes_gcm_128[0x1]; 1238 u8 tls_1_3_aes_gcm_128[0x1]; 1239 u8 tls_1_2_aes_gcm_256[0x1]; 1240 u8 tls_1_3_aes_gcm_256[0x1]; 1241 u8 reserved_at_4[0x1c]; 1242 1243 u8 reserved_at_20[0x7e0]; 1244 }; 1245 1246 struct mlx5_ifc_ipsec_cap_bits { 1247 u8 ipsec_full_offload[0x1]; 1248 u8 ipsec_crypto_offload[0x1]; 1249 u8 ipsec_esn[0x1]; 1250 u8 ipsec_crypto_esp_aes_gcm_256_encrypt[0x1]; 1251 u8 ipsec_crypto_esp_aes_gcm_128_encrypt[0x1]; 1252 u8 ipsec_crypto_esp_aes_gcm_256_decrypt[0x1]; 1253 u8 ipsec_crypto_esp_aes_gcm_128_decrypt[0x1]; 1254 u8 reserved_at_7[0x4]; 1255 u8 log_max_ipsec_offload[0x5]; 1256 u8 reserved_at_10[0x10]; 1257 1258 u8 min_log_ipsec_full_replay_window[0x8]; 1259 u8 max_log_ipsec_full_replay_window[0x8]; 1260 u8 reserved_at_30[0x7d0]; 1261 }; 1262 1263 enum { 1264 MLX5_WQ_TYPE_LINKED_LIST = 0x0, 1265 MLX5_WQ_TYPE_CYCLIC = 0x1, 1266 MLX5_WQ_TYPE_LINKED_LIST_STRIDING_RQ = 0x2, 1267 MLX5_WQ_TYPE_CYCLIC_STRIDING_RQ = 0x3, 1268 }; 1269 1270 enum { 1271 MLX5_WQ_END_PAD_MODE_NONE = 0x0, 1272 MLX5_WQ_END_PAD_MODE_ALIGN = 0x1, 1273 }; 1274 1275 enum { 1276 MLX5_CMD_HCA_CAP_GID_TABLE_SIZE_8_GID_ENTRIES = 0x0, 1277 MLX5_CMD_HCA_CAP_GID_TABLE_SIZE_16_GID_ENTRIES = 0x1, 1278 MLX5_CMD_HCA_CAP_GID_TABLE_SIZE_32_GID_ENTRIES = 0x2, 1279 MLX5_CMD_HCA_CAP_GID_TABLE_SIZE_64_GID_ENTRIES = 0x3, 1280 MLX5_CMD_HCA_CAP_GID_TABLE_SIZE_128_GID_ENTRIES = 0x4, 1281 }; 1282 1283 enum { 1284 MLX5_CMD_HCA_CAP_PKEY_TABLE_SIZE_128_ENTRIES = 0x0, 1285 MLX5_CMD_HCA_CAP_PKEY_TABLE_SIZE_256_ENTRIES = 0x1, 1286 MLX5_CMD_HCA_CAP_PKEY_TABLE_SIZE_512_ENTRIES = 0x2, 1287 MLX5_CMD_HCA_CAP_PKEY_TABLE_SIZE_1K_ENTRIES = 0x3, 1288 MLX5_CMD_HCA_CAP_PKEY_TABLE_SIZE_2K_ENTRIES = 0x4, 1289 MLX5_CMD_HCA_CAP_PKEY_TABLE_SIZE_4K_ENTRIES = 0x5, 1290 }; 1291 1292 enum { 1293 MLX5_CMD_HCA_CAP_PORT_TYPE_IB = 0x0, 1294 MLX5_CMD_HCA_CAP_PORT_TYPE_ETHERNET = 0x1, 1295 }; 1296 1297 enum { 1298 MLX5_CMD_HCA_CAP_CMDIF_CHECKSUM_DISABLED = 0x0, 1299 MLX5_CMD_HCA_CAP_CMDIF_CHECKSUM_INITIAL_STATE = 0x1, 1300 MLX5_CMD_HCA_CAP_CMDIF_CHECKSUM_ENABLED = 0x3, 1301 }; 1302 1303 enum { 1304 MLX5_CAP_PORT_TYPE_IB = 0x0, 1305 MLX5_CAP_PORT_TYPE_ETH = 0x1, 1306 }; 1307 1308 enum { 1309 MLX5_CAP_UMR_FENCE_STRONG = 0x0, 1310 MLX5_CAP_UMR_FENCE_SMALL = 0x1, 1311 MLX5_CAP_UMR_FENCE_NONE = 0x2, 1312 }; 1313 1314 enum { 1315 MLX5_FLEX_PARSER_GENEVE_ENABLED = 1 << 3, 1316 MLX5_FLEX_PARSER_MPLS_OVER_GRE_ENABLED = 1 << 4, 1317 MLX5_FLEX_PARSER_MPLS_OVER_UDP_ENABLED = 1 << 5, 1318 MLX5_FLEX_PARSER_VXLAN_GPE_ENABLED = 1 << 7, 1319 MLX5_FLEX_PARSER_ICMP_V4_ENABLED = 1 << 8, 1320 MLX5_FLEX_PARSER_ICMP_V6_ENABLED = 1 << 9, 1321 MLX5_FLEX_PARSER_GENEVE_TLV_OPTION_0_ENABLED = 1 << 10, 1322 MLX5_FLEX_PARSER_GTPU_ENABLED = 1 << 11, 1323 MLX5_FLEX_PARSER_GTPU_DW_2_ENABLED = 1 << 16, 1324 MLX5_FLEX_PARSER_GTPU_FIRST_EXT_DW_0_ENABLED = 1 << 17, 1325 MLX5_FLEX_PARSER_GTPU_DW_0_ENABLED = 1 << 18, 1326 MLX5_FLEX_PARSER_GTPU_TEID_ENABLED = 1 << 19, 1327 }; 1328 1329 enum { 1330 MLX5_UCTX_CAP_RAW_TX = 1UL << 0, 1331 MLX5_UCTX_CAP_INTERNAL_DEV_RES = 1UL << 1, 1332 }; 1333 1334 #define MLX5_FC_BULK_SIZE_FACTOR 128 1335 1336 enum mlx5_fc_bulk_alloc_bitmask { 1337 MLX5_FC_BULK_128 = (1 << 0), 1338 MLX5_FC_BULK_256 = (1 << 1), 1339 MLX5_FC_BULK_512 = (1 << 2), 1340 MLX5_FC_BULK_1024 = (1 << 3), 1341 MLX5_FC_BULK_2048 = (1 << 4), 1342 MLX5_FC_BULK_4096 = (1 << 5), 1343 MLX5_FC_BULK_8192 = (1 << 6), 1344 MLX5_FC_BULK_16384 = (1 << 7), 1345 }; 1346 1347 #define MLX5_FC_BULK_NUM_FCS(fc_enum) (MLX5_FC_BULK_SIZE_FACTOR * (fc_enum)) 1348 1349 #define MLX5_FT_MAX_MULTIPATH_LEVEL 63 1350 1351 enum { 1352 MLX5_STEERING_FORMAT_CONNECTX_5 = 0, 1353 MLX5_STEERING_FORMAT_CONNECTX_6DX = 1, 1354 MLX5_STEERING_FORMAT_CONNECTX_7 = 2, 1355 }; 1356 1357 struct mlx5_ifc_cmd_hca_cap_bits { 1358 u8 reserved_at_0[0x1f]; 1359 u8 vhca_resource_manager[0x1]; 1360 1361 u8 hca_cap_2[0x1]; 1362 u8 create_lag_when_not_master_up[0x1]; 1363 u8 dtor[0x1]; 1364 u8 event_on_vhca_state_teardown_request[0x1]; 1365 u8 event_on_vhca_state_in_use[0x1]; 1366 u8 event_on_vhca_state_active[0x1]; 1367 u8 event_on_vhca_state_allocated[0x1]; 1368 u8 event_on_vhca_state_invalid[0x1]; 1369 u8 reserved_at_28[0x8]; 1370 u8 vhca_id[0x10]; 1371 1372 u8 reserved_at_40[0x40]; 1373 1374 u8 log_max_srq_sz[0x8]; 1375 u8 log_max_qp_sz[0x8]; 1376 u8 event_cap[0x1]; 1377 u8 reserved_at_91[0x2]; 1378 u8 isolate_vl_tc_new[0x1]; 1379 u8 reserved_at_94[0x4]; 1380 u8 prio_tag_required[0x1]; 1381 u8 reserved_at_99[0x2]; 1382 u8 log_max_qp[0x5]; 1383 1384 u8 reserved_at_a0[0x3]; 1385 u8 ece_support[0x1]; 1386 u8 reserved_at_a4[0x5]; 1387 u8 reg_c_preserve[0x1]; 1388 u8 reserved_at_aa[0x1]; 1389 u8 log_max_srq[0x5]; 1390 u8 reserved_at_b0[0x1]; 1391 u8 uplink_follow[0x1]; 1392 u8 ts_cqe_to_dest_cqn[0x1]; 1393 u8 reserved_at_b3[0x7]; 1394 u8 shampo[0x1]; 1395 u8 reserved_at_bb[0x5]; 1396 1397 u8 max_sgl_for_optimized_performance[0x8]; 1398 u8 log_max_cq_sz[0x8]; 1399 u8 relaxed_ordering_write_umr[0x1]; 1400 u8 relaxed_ordering_read_umr[0x1]; 1401 u8 reserved_at_d2[0x7]; 1402 u8 virtio_net_device_emualtion_manager[0x1]; 1403 u8 virtio_blk_device_emualtion_manager[0x1]; 1404 u8 log_max_cq[0x5]; 1405 1406 u8 log_max_eq_sz[0x8]; 1407 u8 relaxed_ordering_write[0x1]; 1408 u8 relaxed_ordering_read[0x1]; 1409 u8 log_max_mkey[0x6]; 1410 u8 reserved_at_f0[0x8]; 1411 u8 dump_fill_mkey[0x1]; 1412 u8 reserved_at_f9[0x2]; 1413 u8 fast_teardown[0x1]; 1414 u8 log_max_eq[0x4]; 1415 1416 u8 max_indirection[0x8]; 1417 u8 fixed_buffer_size[0x1]; 1418 u8 log_max_mrw_sz[0x7]; 1419 u8 force_teardown[0x1]; 1420 u8 reserved_at_111[0x1]; 1421 u8 log_max_bsf_list_size[0x6]; 1422 u8 umr_extended_translation_offset[0x1]; 1423 u8 null_mkey[0x1]; 1424 u8 log_max_klm_list_size[0x6]; 1425 1426 u8 reserved_at_120[0xa]; 1427 u8 log_max_ra_req_dc[0x6]; 1428 u8 reserved_at_130[0xa]; 1429 u8 log_max_ra_res_dc[0x6]; 1430 1431 u8 reserved_at_140[0x5]; 1432 u8 release_all_pages[0x1]; 1433 u8 must_not_use[0x1]; 1434 u8 reserved_at_147[0x2]; 1435 u8 roce_accl[0x1]; 1436 u8 log_max_ra_req_qp[0x6]; 1437 u8 reserved_at_150[0xa]; 1438 u8 log_max_ra_res_qp[0x6]; 1439 1440 u8 end_pad[0x1]; 1441 u8 cc_query_allowed[0x1]; 1442 u8 cc_modify_allowed[0x1]; 1443 u8 start_pad[0x1]; 1444 u8 cache_line_128byte[0x1]; 1445 u8 reserved_at_165[0x4]; 1446 u8 rts2rts_qp_counters_set_id[0x1]; 1447 u8 reserved_at_16a[0x2]; 1448 u8 vnic_env_int_rq_oob[0x1]; 1449 u8 sbcam_reg[0x1]; 1450 u8 reserved_at_16e[0x1]; 1451 u8 qcam_reg[0x1]; 1452 u8 gid_table_size[0x10]; 1453 1454 u8 out_of_seq_cnt[0x1]; 1455 u8 vport_counters[0x1]; 1456 u8 retransmission_q_counters[0x1]; 1457 u8 debug[0x1]; 1458 u8 modify_rq_counter_set_id[0x1]; 1459 u8 rq_delay_drop[0x1]; 1460 u8 max_qp_cnt[0xa]; 1461 u8 pkey_table_size[0x10]; 1462 1463 u8 vport_group_manager[0x1]; 1464 u8 vhca_group_manager[0x1]; 1465 u8 ib_virt[0x1]; 1466 u8 eth_virt[0x1]; 1467 u8 vnic_env_queue_counters[0x1]; 1468 u8 ets[0x1]; 1469 u8 nic_flow_table[0x1]; 1470 u8 eswitch_manager[0x1]; 1471 u8 device_memory[0x1]; 1472 u8 mcam_reg[0x1]; 1473 u8 pcam_reg[0x1]; 1474 u8 local_ca_ack_delay[0x5]; 1475 u8 port_module_event[0x1]; 1476 u8 enhanced_error_q_counters[0x1]; 1477 u8 ports_check[0x1]; 1478 u8 reserved_at_1b3[0x1]; 1479 u8 disable_link_up[0x1]; 1480 u8 beacon_led[0x1]; 1481 u8 port_type[0x2]; 1482 u8 num_ports[0x8]; 1483 1484 u8 reserved_at_1c0[0x1]; 1485 u8 pps[0x1]; 1486 u8 pps_modify[0x1]; 1487 u8 log_max_msg[0x5]; 1488 u8 reserved_at_1c8[0x4]; 1489 u8 max_tc[0x4]; 1490 u8 temp_warn_event[0x1]; 1491 u8 dcbx[0x1]; 1492 u8 general_notification_event[0x1]; 1493 u8 reserved_at_1d3[0x2]; 1494 u8 fpga[0x1]; 1495 u8 rol_s[0x1]; 1496 u8 rol_g[0x1]; 1497 u8 reserved_at_1d8[0x1]; 1498 u8 wol_s[0x1]; 1499 u8 wol_g[0x1]; 1500 u8 wol_a[0x1]; 1501 u8 wol_b[0x1]; 1502 u8 wol_m[0x1]; 1503 u8 wol_u[0x1]; 1504 u8 wol_p[0x1]; 1505 1506 u8 stat_rate_support[0x10]; 1507 u8 reserved_at_1f0[0x1]; 1508 u8 pci_sync_for_fw_update_event[0x1]; 1509 u8 reserved_at_1f2[0x6]; 1510 u8 init2_lag_tx_port_affinity[0x1]; 1511 u8 reserved_at_1fa[0x3]; 1512 u8 cqe_version[0x4]; 1513 1514 u8 compact_address_vector[0x1]; 1515 u8 striding_rq[0x1]; 1516 u8 reserved_at_202[0x1]; 1517 u8 ipoib_enhanced_offloads[0x1]; 1518 u8 ipoib_basic_offloads[0x1]; 1519 u8 reserved_at_205[0x1]; 1520 u8 repeated_block_disabled[0x1]; 1521 u8 umr_modify_entity_size_disabled[0x1]; 1522 u8 umr_modify_atomic_disabled[0x1]; 1523 u8 umr_indirect_mkey_disabled[0x1]; 1524 u8 umr_fence[0x2]; 1525 u8 dc_req_scat_data_cqe[0x1]; 1526 u8 reserved_at_20d[0x2]; 1527 u8 drain_sigerr[0x1]; 1528 u8 cmdif_checksum[0x2]; 1529 u8 sigerr_cqe[0x1]; 1530 u8 reserved_at_213[0x1]; 1531 u8 wq_signature[0x1]; 1532 u8 sctr_data_cqe[0x1]; 1533 u8 reserved_at_216[0x1]; 1534 u8 sho[0x1]; 1535 u8 tph[0x1]; 1536 u8 rf[0x1]; 1537 u8 dct[0x1]; 1538 u8 qos[0x1]; 1539 u8 eth_net_offloads[0x1]; 1540 u8 roce[0x1]; 1541 u8 atomic[0x1]; 1542 u8 reserved_at_21f[0x1]; 1543 1544 u8 cq_oi[0x1]; 1545 u8 cq_resize[0x1]; 1546 u8 cq_moderation[0x1]; 1547 u8 reserved_at_223[0x3]; 1548 u8 cq_eq_remap[0x1]; 1549 u8 pg[0x1]; 1550 u8 block_lb_mc[0x1]; 1551 u8 reserved_at_229[0x1]; 1552 u8 scqe_break_moderation[0x1]; 1553 u8 cq_period_start_from_cqe[0x1]; 1554 u8 cd[0x1]; 1555 u8 reserved_at_22d[0x1]; 1556 u8 apm[0x1]; 1557 u8 vector_calc[0x1]; 1558 u8 umr_ptr_rlky[0x1]; 1559 u8 imaicl[0x1]; 1560 u8 qp_packet_based[0x1]; 1561 u8 reserved_at_233[0x3]; 1562 u8 qkv[0x1]; 1563 u8 pkv[0x1]; 1564 u8 set_deth_sqpn[0x1]; 1565 u8 reserved_at_239[0x3]; 1566 u8 xrc[0x1]; 1567 u8 ud[0x1]; 1568 u8 uc[0x1]; 1569 u8 rc[0x1]; 1570 1571 u8 uar_4k[0x1]; 1572 u8 reserved_at_241[0x9]; 1573 u8 uar_sz[0x6]; 1574 u8 port_selection_cap[0x1]; 1575 u8 reserved_at_248[0x1]; 1576 u8 umem_uid_0[0x1]; 1577 u8 reserved_at_250[0x5]; 1578 u8 log_pg_sz[0x8]; 1579 1580 u8 bf[0x1]; 1581 u8 driver_version[0x1]; 1582 u8 pad_tx_eth_packet[0x1]; 1583 u8 reserved_at_263[0x3]; 1584 u8 mkey_by_name[0x1]; 1585 u8 reserved_at_267[0x4]; 1586 1587 u8 log_bf_reg_size[0x5]; 1588 1589 u8 reserved_at_270[0x6]; 1590 u8 lag_dct[0x2]; 1591 u8 lag_tx_port_affinity[0x1]; 1592 u8 lag_native_fdb_selection[0x1]; 1593 u8 reserved_at_27a[0x1]; 1594 u8 lag_master[0x1]; 1595 u8 num_lag_ports[0x4]; 1596 1597 u8 reserved_at_280[0x10]; 1598 u8 max_wqe_sz_sq[0x10]; 1599 1600 u8 reserved_at_2a0[0x10]; 1601 u8 max_wqe_sz_rq[0x10]; 1602 1603 u8 max_flow_counter_31_16[0x10]; 1604 u8 max_wqe_sz_sq_dc[0x10]; 1605 1606 u8 reserved_at_2e0[0x7]; 1607 u8 max_qp_mcg[0x19]; 1608 1609 u8 reserved_at_300[0x10]; 1610 u8 flow_counter_bulk_alloc[0x8]; 1611 u8 log_max_mcg[0x8]; 1612 1613 u8 reserved_at_320[0x3]; 1614 u8 log_max_transport_domain[0x5]; 1615 u8 reserved_at_328[0x3]; 1616 u8 log_max_pd[0x5]; 1617 u8 reserved_at_330[0xb]; 1618 u8 log_max_xrcd[0x5]; 1619 1620 u8 nic_receive_steering_discard[0x1]; 1621 u8 receive_discard_vport_down[0x1]; 1622 u8 transmit_discard_vport_down[0x1]; 1623 u8 reserved_at_343[0x5]; 1624 u8 log_max_flow_counter_bulk[0x8]; 1625 u8 max_flow_counter_15_0[0x10]; 1626 1627 1628 u8 reserved_at_360[0x3]; 1629 u8 log_max_rq[0x5]; 1630 u8 reserved_at_368[0x3]; 1631 u8 log_max_sq[0x5]; 1632 u8 reserved_at_370[0x3]; 1633 u8 log_max_tir[0x5]; 1634 u8 reserved_at_378[0x3]; 1635 u8 log_max_tis[0x5]; 1636 1637 u8 basic_cyclic_rcv_wqe[0x1]; 1638 u8 reserved_at_381[0x2]; 1639 u8 log_max_rmp[0x5]; 1640 u8 reserved_at_388[0x3]; 1641 u8 log_max_rqt[0x5]; 1642 u8 reserved_at_390[0x3]; 1643 u8 log_max_rqt_size[0x5]; 1644 u8 reserved_at_398[0x3]; 1645 u8 log_max_tis_per_sq[0x5]; 1646 1647 u8 ext_stride_num_range[0x1]; 1648 u8 roce_rw_supported[0x1]; 1649 u8 log_max_current_uc_list_wr_supported[0x1]; 1650 u8 log_max_stride_sz_rq[0x5]; 1651 u8 reserved_at_3a8[0x3]; 1652 u8 log_min_stride_sz_rq[0x5]; 1653 u8 reserved_at_3b0[0x3]; 1654 u8 log_max_stride_sz_sq[0x5]; 1655 u8 reserved_at_3b8[0x3]; 1656 u8 log_min_stride_sz_sq[0x5]; 1657 1658 u8 hairpin[0x1]; 1659 u8 reserved_at_3c1[0x2]; 1660 u8 log_max_hairpin_queues[0x5]; 1661 u8 reserved_at_3c8[0x3]; 1662 u8 log_max_hairpin_wq_data_sz[0x5]; 1663 u8 reserved_at_3d0[0x3]; 1664 u8 log_max_hairpin_num_packets[0x5]; 1665 u8 reserved_at_3d8[0x3]; 1666 u8 log_max_wq_sz[0x5]; 1667 1668 u8 nic_vport_change_event[0x1]; 1669 u8 disable_local_lb_uc[0x1]; 1670 u8 disable_local_lb_mc[0x1]; 1671 u8 log_min_hairpin_wq_data_sz[0x5]; 1672 u8 reserved_at_3e8[0x2]; 1673 u8 vhca_state[0x1]; 1674 u8 log_max_vlan_list[0x5]; 1675 u8 reserved_at_3f0[0x3]; 1676 u8 log_max_current_mc_list[0x5]; 1677 u8 reserved_at_3f8[0x3]; 1678 u8 log_max_current_uc_list[0x5]; 1679 1680 u8 general_obj_types[0x40]; 1681 1682 u8 sq_ts_format[0x2]; 1683 u8 rq_ts_format[0x2]; 1684 u8 steering_format_version[0x4]; 1685 u8 create_qp_start_hint[0x18]; 1686 1687 u8 reserved_at_460[0x3]; 1688 u8 log_max_uctx[0x5]; 1689 u8 reserved_at_468[0x2]; 1690 u8 ipsec_offload[0x1]; 1691 u8 log_max_umem[0x5]; 1692 u8 max_num_eqs[0x10]; 1693 1694 u8 reserved_at_480[0x1]; 1695 u8 tls_tx[0x1]; 1696 u8 tls_rx[0x1]; 1697 u8 log_max_l2_table[0x5]; 1698 u8 reserved_at_488[0x8]; 1699 u8 log_uar_page_sz[0x10]; 1700 1701 u8 reserved_at_4a0[0x20]; 1702 u8 device_frequency_mhz[0x20]; 1703 u8 device_frequency_khz[0x20]; 1704 1705 u8 reserved_at_500[0x20]; 1706 u8 num_of_uars_per_page[0x20]; 1707 1708 u8 flex_parser_protocols[0x20]; 1709 1710 u8 max_geneve_tlv_options[0x8]; 1711 u8 reserved_at_568[0x3]; 1712 u8 max_geneve_tlv_option_data_len[0x5]; 1713 u8 reserved_at_570[0x10]; 1714 1715 u8 reserved_at_580[0xb]; 1716 u8 log_max_dci_stream_channels[0x5]; 1717 u8 reserved_at_590[0x3]; 1718 u8 log_max_dci_errored_streams[0x5]; 1719 u8 reserved_at_598[0x8]; 1720 1721 u8 reserved_at_5a0[0x13]; 1722 u8 log_max_dek[0x5]; 1723 u8 reserved_at_5b8[0x4]; 1724 u8 mini_cqe_resp_stride_index[0x1]; 1725 u8 cqe_128_always[0x1]; 1726 u8 cqe_compression_128[0x1]; 1727 u8 cqe_compression[0x1]; 1728 1729 u8 cqe_compression_timeout[0x10]; 1730 u8 cqe_compression_max_num[0x10]; 1731 1732 u8 reserved_at_5e0[0x8]; 1733 u8 flex_parser_id_gtpu_dw_0[0x4]; 1734 u8 reserved_at_5ec[0x4]; 1735 u8 tag_matching[0x1]; 1736 u8 rndv_offload_rc[0x1]; 1737 u8 rndv_offload_dc[0x1]; 1738 u8 log_tag_matching_list_sz[0x5]; 1739 u8 reserved_at_5f8[0x3]; 1740 u8 log_max_xrq[0x5]; 1741 1742 u8 affiliate_nic_vport_criteria[0x8]; 1743 u8 native_port_num[0x8]; 1744 u8 num_vhca_ports[0x8]; 1745 u8 flex_parser_id_gtpu_teid[0x4]; 1746 u8 reserved_at_61c[0x2]; 1747 u8 sw_owner_id[0x1]; 1748 u8 reserved_at_61f[0x1]; 1749 1750 u8 max_num_of_monitor_counters[0x10]; 1751 u8 num_ppcnt_monitor_counters[0x10]; 1752 1753 u8 max_num_sf[0x10]; 1754 u8 num_q_monitor_counters[0x10]; 1755 1756 u8 reserved_at_660[0x20]; 1757 1758 u8 sf[0x1]; 1759 u8 sf_set_partition[0x1]; 1760 u8 reserved_at_682[0x1]; 1761 u8 log_max_sf[0x5]; 1762 u8 apu[0x1]; 1763 u8 reserved_at_689[0x4]; 1764 u8 migration[0x1]; 1765 u8 reserved_at_68e[0x2]; 1766 u8 log_min_sf_size[0x8]; 1767 u8 max_num_sf_partitions[0x8]; 1768 1769 u8 uctx_cap[0x20]; 1770 1771 u8 reserved_at_6c0[0x4]; 1772 u8 flex_parser_id_geneve_tlv_option_0[0x4]; 1773 u8 flex_parser_id_icmp_dw1[0x4]; 1774 u8 flex_parser_id_icmp_dw0[0x4]; 1775 u8 flex_parser_id_icmpv6_dw1[0x4]; 1776 u8 flex_parser_id_icmpv6_dw0[0x4]; 1777 u8 flex_parser_id_outer_first_mpls_over_gre[0x4]; 1778 u8 flex_parser_id_outer_first_mpls_over_udp_label[0x4]; 1779 1780 u8 max_num_match_definer[0x10]; 1781 u8 sf_base_id[0x10]; 1782 1783 u8 flex_parser_id_gtpu_dw_2[0x4]; 1784 u8 flex_parser_id_gtpu_first_ext_dw_0[0x4]; 1785 u8 num_total_dynamic_vf_msix[0x18]; 1786 u8 reserved_at_720[0x14]; 1787 u8 dynamic_msix_table_size[0xc]; 1788 u8 reserved_at_740[0xc]; 1789 u8 min_dynamic_vf_msix_table_size[0x4]; 1790 u8 reserved_at_750[0x4]; 1791 u8 max_dynamic_vf_msix_table_size[0xc]; 1792 1793 u8 reserved_at_760[0x20]; 1794 u8 vhca_tunnel_commands[0x40]; 1795 u8 match_definer_format_supported[0x40]; 1796 }; 1797 1798 struct mlx5_ifc_cmd_hca_cap_2_bits { 1799 u8 reserved_at_0[0xa0]; 1800 1801 u8 max_reformat_insert_size[0x8]; 1802 u8 max_reformat_insert_offset[0x8]; 1803 u8 max_reformat_remove_size[0x8]; 1804 u8 max_reformat_remove_offset[0x8]; 1805 1806 u8 reserved_at_c0[0x740]; 1807 }; 1808 1809 enum mlx5_ifc_flow_destination_type { 1810 MLX5_IFC_FLOW_DESTINATION_TYPE_VPORT = 0x0, 1811 MLX5_IFC_FLOW_DESTINATION_TYPE_FLOW_TABLE = 0x1, 1812 MLX5_IFC_FLOW_DESTINATION_TYPE_TIR = 0x2, 1813 MLX5_IFC_FLOW_DESTINATION_TYPE_FLOW_SAMPLER = 0x6, 1814 MLX5_IFC_FLOW_DESTINATION_TYPE_UPLINK = 0x8, 1815 }; 1816 1817 enum mlx5_flow_table_miss_action { 1818 MLX5_FLOW_TABLE_MISS_ACTION_DEF, 1819 MLX5_FLOW_TABLE_MISS_ACTION_FWD, 1820 MLX5_FLOW_TABLE_MISS_ACTION_SWITCH_DOMAIN, 1821 }; 1822 1823 struct mlx5_ifc_dest_format_struct_bits { 1824 u8 destination_type[0x8]; 1825 u8 destination_id[0x18]; 1826 1827 u8 destination_eswitch_owner_vhca_id_valid[0x1]; 1828 u8 packet_reformat[0x1]; 1829 u8 reserved_at_22[0xe]; 1830 u8 destination_eswitch_owner_vhca_id[0x10]; 1831 }; 1832 1833 struct mlx5_ifc_flow_counter_list_bits { 1834 u8 flow_counter_id[0x20]; 1835 1836 u8 reserved_at_20[0x20]; 1837 }; 1838 1839 struct mlx5_ifc_extended_dest_format_bits { 1840 struct mlx5_ifc_dest_format_struct_bits destination_entry; 1841 1842 u8 packet_reformat_id[0x20]; 1843 1844 u8 reserved_at_60[0x20]; 1845 }; 1846 1847 union mlx5_ifc_dest_format_struct_flow_counter_list_auto_bits { 1848 struct mlx5_ifc_extended_dest_format_bits extended_dest_format; 1849 struct mlx5_ifc_flow_counter_list_bits flow_counter_list; 1850 }; 1851 1852 struct mlx5_ifc_fte_match_param_bits { 1853 struct mlx5_ifc_fte_match_set_lyr_2_4_bits outer_headers; 1854 1855 struct mlx5_ifc_fte_match_set_misc_bits misc_parameters; 1856 1857 struct mlx5_ifc_fte_match_set_lyr_2_4_bits inner_headers; 1858 1859 struct mlx5_ifc_fte_match_set_misc2_bits misc_parameters_2; 1860 1861 struct mlx5_ifc_fte_match_set_misc3_bits misc_parameters_3; 1862 1863 struct mlx5_ifc_fte_match_set_misc4_bits misc_parameters_4; 1864 1865 struct mlx5_ifc_fte_match_set_misc5_bits misc_parameters_5; 1866 1867 u8 reserved_at_e00[0x200]; 1868 }; 1869 1870 enum { 1871 MLX5_RX_HASH_FIELD_SELECT_SELECTED_FIELDS_SRC_IP = 0x0, 1872 MLX5_RX_HASH_FIELD_SELECT_SELECTED_FIELDS_DST_IP = 0x1, 1873 MLX5_RX_HASH_FIELD_SELECT_SELECTED_FIELDS_L4_SPORT = 0x2, 1874 MLX5_RX_HASH_FIELD_SELECT_SELECTED_FIELDS_L4_DPORT = 0x3, 1875 MLX5_RX_HASH_FIELD_SELECT_SELECTED_FIELDS_IPSEC_SPI = 0x4, 1876 }; 1877 1878 struct mlx5_ifc_rx_hash_field_select_bits { 1879 u8 l3_prot_type[0x1]; 1880 u8 l4_prot_type[0x1]; 1881 u8 selected_fields[0x1e]; 1882 }; 1883 1884 enum { 1885 MLX5_WQ_WQ_TYPE_WQ_LINKED_LIST = 0x0, 1886 MLX5_WQ_WQ_TYPE_WQ_CYCLIC = 0x1, 1887 }; 1888 1889 enum { 1890 MLX5_WQ_END_PADDING_MODE_END_PAD_NONE = 0x0, 1891 MLX5_WQ_END_PADDING_MODE_END_PAD_ALIGN = 0x1, 1892 }; 1893 1894 struct mlx5_ifc_wq_bits { 1895 u8 wq_type[0x4]; 1896 u8 wq_signature[0x1]; 1897 u8 end_padding_mode[0x2]; 1898 u8 cd_slave[0x1]; 1899 u8 reserved_at_8[0x18]; 1900 1901 u8 hds_skip_first_sge[0x1]; 1902 u8 log2_hds_buf_size[0x3]; 1903 u8 reserved_at_24[0x7]; 1904 u8 page_offset[0x5]; 1905 u8 lwm[0x10]; 1906 1907 u8 reserved_at_40[0x8]; 1908 u8 pd[0x18]; 1909 1910 u8 reserved_at_60[0x8]; 1911 u8 uar_page[0x18]; 1912 1913 u8 dbr_addr[0x40]; 1914 1915 u8 hw_counter[0x20]; 1916 1917 u8 sw_counter[0x20]; 1918 1919 u8 reserved_at_100[0xc]; 1920 u8 log_wq_stride[0x4]; 1921 u8 reserved_at_110[0x3]; 1922 u8 log_wq_pg_sz[0x5]; 1923 u8 reserved_at_118[0x3]; 1924 u8 log_wq_sz[0x5]; 1925 1926 u8 dbr_umem_valid[0x1]; 1927 u8 wq_umem_valid[0x1]; 1928 u8 reserved_at_122[0x1]; 1929 u8 log_hairpin_num_packets[0x5]; 1930 u8 reserved_at_128[0x3]; 1931 u8 log_hairpin_data_sz[0x5]; 1932 1933 u8 reserved_at_130[0x4]; 1934 u8 log_wqe_num_of_strides[0x4]; 1935 u8 two_byte_shift_en[0x1]; 1936 u8 reserved_at_139[0x4]; 1937 u8 log_wqe_stride_size[0x3]; 1938 1939 u8 reserved_at_140[0x80]; 1940 1941 u8 headers_mkey[0x20]; 1942 1943 u8 shampo_enable[0x1]; 1944 u8 reserved_at_1e1[0x4]; 1945 u8 log_reservation_size[0x3]; 1946 u8 reserved_at_1e8[0x5]; 1947 u8 log_max_num_of_packets_per_reservation[0x3]; 1948 u8 reserved_at_1f0[0x6]; 1949 u8 log_headers_entry_size[0x2]; 1950 u8 reserved_at_1f8[0x4]; 1951 u8 log_headers_buffer_entry_num[0x4]; 1952 1953 u8 reserved_at_200[0x400]; 1954 1955 struct mlx5_ifc_cmd_pas_bits pas[]; 1956 }; 1957 1958 struct mlx5_ifc_rq_num_bits { 1959 u8 reserved_at_0[0x8]; 1960 u8 rq_num[0x18]; 1961 }; 1962 1963 struct mlx5_ifc_mac_address_layout_bits { 1964 u8 reserved_at_0[0x10]; 1965 u8 mac_addr_47_32[0x10]; 1966 1967 u8 mac_addr_31_0[0x20]; 1968 }; 1969 1970 struct mlx5_ifc_vlan_layout_bits { 1971 u8 reserved_at_0[0x14]; 1972 u8 vlan[0x0c]; 1973 1974 u8 reserved_at_20[0x20]; 1975 }; 1976 1977 struct mlx5_ifc_cong_control_r_roce_ecn_np_bits { 1978 u8 reserved_at_0[0xa0]; 1979 1980 u8 min_time_between_cnps[0x20]; 1981 1982 u8 reserved_at_c0[0x12]; 1983 u8 cnp_dscp[0x6]; 1984 u8 reserved_at_d8[0x4]; 1985 u8 cnp_prio_mode[0x1]; 1986 u8 cnp_802p_prio[0x3]; 1987 1988 u8 reserved_at_e0[0x720]; 1989 }; 1990 1991 struct mlx5_ifc_cong_control_r_roce_ecn_rp_bits { 1992 u8 reserved_at_0[0x60]; 1993 1994 u8 reserved_at_60[0x4]; 1995 u8 clamp_tgt_rate[0x1]; 1996 u8 reserved_at_65[0x3]; 1997 u8 clamp_tgt_rate_after_time_inc[0x1]; 1998 u8 reserved_at_69[0x17]; 1999 2000 u8 reserved_at_80[0x20]; 2001 2002 u8 rpg_time_reset[0x20]; 2003 2004 u8 rpg_byte_reset[0x20]; 2005 2006 u8 rpg_threshold[0x20]; 2007 2008 u8 rpg_max_rate[0x20]; 2009 2010 u8 rpg_ai_rate[0x20]; 2011 2012 u8 rpg_hai_rate[0x20]; 2013 2014 u8 rpg_gd[0x20]; 2015 2016 u8 rpg_min_dec_fac[0x20]; 2017 2018 u8 rpg_min_rate[0x20]; 2019 2020 u8 reserved_at_1c0[0xe0]; 2021 2022 u8 rate_to_set_on_first_cnp[0x20]; 2023 2024 u8 dce_tcp_g[0x20]; 2025 2026 u8 dce_tcp_rtt[0x20]; 2027 2028 u8 rate_reduce_monitor_period[0x20]; 2029 2030 u8 reserved_at_320[0x20]; 2031 2032 u8 initial_alpha_value[0x20]; 2033 2034 u8 reserved_at_360[0x4a0]; 2035 }; 2036 2037 struct mlx5_ifc_cong_control_802_1qau_rp_bits { 2038 u8 reserved_at_0[0x80]; 2039 2040 u8 rppp_max_rps[0x20]; 2041 2042 u8 rpg_time_reset[0x20]; 2043 2044 u8 rpg_byte_reset[0x20]; 2045 2046 u8 rpg_threshold[0x20]; 2047 2048 u8 rpg_max_rate[0x20]; 2049 2050 u8 rpg_ai_rate[0x20]; 2051 2052 u8 rpg_hai_rate[0x20]; 2053 2054 u8 rpg_gd[0x20]; 2055 2056 u8 rpg_min_dec_fac[0x20]; 2057 2058 u8 rpg_min_rate[0x20]; 2059 2060 u8 reserved_at_1c0[0x640]; 2061 }; 2062 2063 enum { 2064 MLX5_RESIZE_FIELD_SELECT_RESIZE_FIELD_SELECT_LOG_CQ_SIZE = 0x1, 2065 MLX5_RESIZE_FIELD_SELECT_RESIZE_FIELD_SELECT_PAGE_OFFSET = 0x2, 2066 MLX5_RESIZE_FIELD_SELECT_RESIZE_FIELD_SELECT_LOG_PAGE_SIZE = 0x4, 2067 }; 2068 2069 struct mlx5_ifc_resize_field_select_bits { 2070 u8 resize_field_select[0x20]; 2071 }; 2072 2073 struct mlx5_ifc_resource_dump_bits { 2074 u8 more_dump[0x1]; 2075 u8 inline_dump[0x1]; 2076 u8 reserved_at_2[0xa]; 2077 u8 seq_num[0x4]; 2078 u8 segment_type[0x10]; 2079 2080 u8 reserved_at_20[0x10]; 2081 u8 vhca_id[0x10]; 2082 2083 u8 index1[0x20]; 2084 2085 u8 index2[0x20]; 2086 2087 u8 num_of_obj1[0x10]; 2088 u8 num_of_obj2[0x10]; 2089 2090 u8 reserved_at_a0[0x20]; 2091 2092 u8 device_opaque[0x40]; 2093 2094 u8 mkey[0x20]; 2095 2096 u8 size[0x20]; 2097 2098 u8 address[0x40]; 2099 2100 u8 inline_data[52][0x20]; 2101 }; 2102 2103 struct mlx5_ifc_resource_dump_menu_record_bits { 2104 u8 reserved_at_0[0x4]; 2105 u8 num_of_obj2_supports_active[0x1]; 2106 u8 num_of_obj2_supports_all[0x1]; 2107 u8 must_have_num_of_obj2[0x1]; 2108 u8 support_num_of_obj2[0x1]; 2109 u8 num_of_obj1_supports_active[0x1]; 2110 u8 num_of_obj1_supports_all[0x1]; 2111 u8 must_have_num_of_obj1[0x1]; 2112 u8 support_num_of_obj1[0x1]; 2113 u8 must_have_index2[0x1]; 2114 u8 support_index2[0x1]; 2115 u8 must_have_index1[0x1]; 2116 u8 support_index1[0x1]; 2117 u8 segment_type[0x10]; 2118 2119 u8 segment_name[4][0x20]; 2120 2121 u8 index1_name[4][0x20]; 2122 2123 u8 index2_name[4][0x20]; 2124 }; 2125 2126 struct mlx5_ifc_resource_dump_segment_header_bits { 2127 u8 length_dw[0x10]; 2128 u8 segment_type[0x10]; 2129 }; 2130 2131 struct mlx5_ifc_resource_dump_command_segment_bits { 2132 struct mlx5_ifc_resource_dump_segment_header_bits segment_header; 2133 2134 u8 segment_called[0x10]; 2135 u8 vhca_id[0x10]; 2136 2137 u8 index1[0x20]; 2138 2139 u8 index2[0x20]; 2140 2141 u8 num_of_obj1[0x10]; 2142 u8 num_of_obj2[0x10]; 2143 }; 2144 2145 struct mlx5_ifc_resource_dump_error_segment_bits { 2146 struct mlx5_ifc_resource_dump_segment_header_bits segment_header; 2147 2148 u8 reserved_at_20[0x10]; 2149 u8 syndrome_id[0x10]; 2150 2151 u8 reserved_at_40[0x40]; 2152 2153 u8 error[8][0x20]; 2154 }; 2155 2156 struct mlx5_ifc_resource_dump_info_segment_bits { 2157 struct mlx5_ifc_resource_dump_segment_header_bits segment_header; 2158 2159 u8 reserved_at_20[0x18]; 2160 u8 dump_version[0x8]; 2161 2162 u8 hw_version[0x20]; 2163 2164 u8 fw_version[0x20]; 2165 }; 2166 2167 struct mlx5_ifc_resource_dump_menu_segment_bits { 2168 struct mlx5_ifc_resource_dump_segment_header_bits segment_header; 2169 2170 u8 reserved_at_20[0x10]; 2171 u8 num_of_records[0x10]; 2172 2173 struct mlx5_ifc_resource_dump_menu_record_bits record[]; 2174 }; 2175 2176 struct mlx5_ifc_resource_dump_resource_segment_bits { 2177 struct mlx5_ifc_resource_dump_segment_header_bits segment_header; 2178 2179 u8 reserved_at_20[0x20]; 2180 2181 u8 index1[0x20]; 2182 2183 u8 index2[0x20]; 2184 2185 u8 payload[][0x20]; 2186 }; 2187 2188 struct mlx5_ifc_resource_dump_terminate_segment_bits { 2189 struct mlx5_ifc_resource_dump_segment_header_bits segment_header; 2190 }; 2191 2192 struct mlx5_ifc_menu_resource_dump_response_bits { 2193 struct mlx5_ifc_resource_dump_info_segment_bits info; 2194 struct mlx5_ifc_resource_dump_command_segment_bits cmd; 2195 struct mlx5_ifc_resource_dump_menu_segment_bits menu; 2196 struct mlx5_ifc_resource_dump_terminate_segment_bits terminate; 2197 }; 2198 2199 enum { 2200 MLX5_MODIFY_FIELD_SELECT_MODIFY_FIELD_SELECT_CQ_PERIOD = 0x1, 2201 MLX5_MODIFY_FIELD_SELECT_MODIFY_FIELD_SELECT_CQ_MAX_COUNT = 0x2, 2202 MLX5_MODIFY_FIELD_SELECT_MODIFY_FIELD_SELECT_OI = 0x4, 2203 MLX5_MODIFY_FIELD_SELECT_MODIFY_FIELD_SELECT_C_EQN = 0x8, 2204 }; 2205 2206 struct mlx5_ifc_modify_field_select_bits { 2207 u8 modify_field_select[0x20]; 2208 }; 2209 2210 struct mlx5_ifc_field_select_r_roce_np_bits { 2211 u8 field_select_r_roce_np[0x20]; 2212 }; 2213 2214 struct mlx5_ifc_field_select_r_roce_rp_bits { 2215 u8 field_select_r_roce_rp[0x20]; 2216 }; 2217 2218 enum { 2219 MLX5_FIELD_SELECT_802_1QAU_RP_FIELD_SELECT_8021QAURP_RPPP_MAX_RPS = 0x4, 2220 MLX5_FIELD_SELECT_802_1QAU_RP_FIELD_SELECT_8021QAURP_RPG_TIME_RESET = 0x8, 2221 MLX5_FIELD_SELECT_802_1QAU_RP_FIELD_SELECT_8021QAURP_RPG_BYTE_RESET = 0x10, 2222 MLX5_FIELD_SELECT_802_1QAU_RP_FIELD_SELECT_8021QAURP_RPG_THRESHOLD = 0x20, 2223 MLX5_FIELD_SELECT_802_1QAU_RP_FIELD_SELECT_8021QAURP_RPG_MAX_RATE = 0x40, 2224 MLX5_FIELD_SELECT_802_1QAU_RP_FIELD_SELECT_8021QAURP_RPG_AI_RATE = 0x80, 2225 MLX5_FIELD_SELECT_802_1QAU_RP_FIELD_SELECT_8021QAURP_RPG_HAI_RATE = 0x100, 2226 MLX5_FIELD_SELECT_802_1QAU_RP_FIELD_SELECT_8021QAURP_RPG_GD = 0x200, 2227 MLX5_FIELD_SELECT_802_1QAU_RP_FIELD_SELECT_8021QAURP_RPG_MIN_DEC_FAC = 0x400, 2228 MLX5_FIELD_SELECT_802_1QAU_RP_FIELD_SELECT_8021QAURP_RPG_MIN_RATE = 0x800, 2229 }; 2230 2231 struct mlx5_ifc_field_select_802_1qau_rp_bits { 2232 u8 field_select_8021qaurp[0x20]; 2233 }; 2234 2235 struct mlx5_ifc_phys_layer_cntrs_bits { 2236 u8 time_since_last_clear_high[0x20]; 2237 2238 u8 time_since_last_clear_low[0x20]; 2239 2240 u8 symbol_errors_high[0x20]; 2241 2242 u8 symbol_errors_low[0x20]; 2243 2244 u8 sync_headers_errors_high[0x20]; 2245 2246 u8 sync_headers_errors_low[0x20]; 2247 2248 u8 edpl_bip_errors_lane0_high[0x20]; 2249 2250 u8 edpl_bip_errors_lane0_low[0x20]; 2251 2252 u8 edpl_bip_errors_lane1_high[0x20]; 2253 2254 u8 edpl_bip_errors_lane1_low[0x20]; 2255 2256 u8 edpl_bip_errors_lane2_high[0x20]; 2257 2258 u8 edpl_bip_errors_lane2_low[0x20]; 2259 2260 u8 edpl_bip_errors_lane3_high[0x20]; 2261 2262 u8 edpl_bip_errors_lane3_low[0x20]; 2263 2264 u8 fc_fec_corrected_blocks_lane0_high[0x20]; 2265 2266 u8 fc_fec_corrected_blocks_lane0_low[0x20]; 2267 2268 u8 fc_fec_corrected_blocks_lane1_high[0x20]; 2269 2270 u8 fc_fec_corrected_blocks_lane1_low[0x20]; 2271 2272 u8 fc_fec_corrected_blocks_lane2_high[0x20]; 2273 2274 u8 fc_fec_corrected_blocks_lane2_low[0x20]; 2275 2276 u8 fc_fec_corrected_blocks_lane3_high[0x20]; 2277 2278 u8 fc_fec_corrected_blocks_lane3_low[0x20]; 2279 2280 u8 fc_fec_uncorrectable_blocks_lane0_high[0x20]; 2281 2282 u8 fc_fec_uncorrectable_blocks_lane0_low[0x20]; 2283 2284 u8 fc_fec_uncorrectable_blocks_lane1_high[0x20]; 2285 2286 u8 fc_fec_uncorrectable_blocks_lane1_low[0x20]; 2287 2288 u8 fc_fec_uncorrectable_blocks_lane2_high[0x20]; 2289 2290 u8 fc_fec_uncorrectable_blocks_lane2_low[0x20]; 2291 2292 u8 fc_fec_uncorrectable_blocks_lane3_high[0x20]; 2293 2294 u8 fc_fec_uncorrectable_blocks_lane3_low[0x20]; 2295 2296 u8 rs_fec_corrected_blocks_high[0x20]; 2297 2298 u8 rs_fec_corrected_blocks_low[0x20]; 2299 2300 u8 rs_fec_uncorrectable_blocks_high[0x20]; 2301 2302 u8 rs_fec_uncorrectable_blocks_low[0x20]; 2303 2304 u8 rs_fec_no_errors_blocks_high[0x20]; 2305 2306 u8 rs_fec_no_errors_blocks_low[0x20]; 2307 2308 u8 rs_fec_single_error_blocks_high[0x20]; 2309 2310 u8 rs_fec_single_error_blocks_low[0x20]; 2311 2312 u8 rs_fec_corrected_symbols_total_high[0x20]; 2313 2314 u8 rs_fec_corrected_symbols_total_low[0x20]; 2315 2316 u8 rs_fec_corrected_symbols_lane0_high[0x20]; 2317 2318 u8 rs_fec_corrected_symbols_lane0_low[0x20]; 2319 2320 u8 rs_fec_corrected_symbols_lane1_high[0x20]; 2321 2322 u8 rs_fec_corrected_symbols_lane1_low[0x20]; 2323 2324 u8 rs_fec_corrected_symbols_lane2_high[0x20]; 2325 2326 u8 rs_fec_corrected_symbols_lane2_low[0x20]; 2327 2328 u8 rs_fec_corrected_symbols_lane3_high[0x20]; 2329 2330 u8 rs_fec_corrected_symbols_lane3_low[0x20]; 2331 2332 u8 link_down_events[0x20]; 2333 2334 u8 successful_recovery_events[0x20]; 2335 2336 u8 reserved_at_640[0x180]; 2337 }; 2338 2339 struct mlx5_ifc_phys_layer_statistical_cntrs_bits { 2340 u8 time_since_last_clear_high[0x20]; 2341 2342 u8 time_since_last_clear_low[0x20]; 2343 2344 u8 phy_received_bits_high[0x20]; 2345 2346 u8 phy_received_bits_low[0x20]; 2347 2348 u8 phy_symbol_errors_high[0x20]; 2349 2350 u8 phy_symbol_errors_low[0x20]; 2351 2352 u8 phy_corrected_bits_high[0x20]; 2353 2354 u8 phy_corrected_bits_low[0x20]; 2355 2356 u8 phy_corrected_bits_lane0_high[0x20]; 2357 2358 u8 phy_corrected_bits_lane0_low[0x20]; 2359 2360 u8 phy_corrected_bits_lane1_high[0x20]; 2361 2362 u8 phy_corrected_bits_lane1_low[0x20]; 2363 2364 u8 phy_corrected_bits_lane2_high[0x20]; 2365 2366 u8 phy_corrected_bits_lane2_low[0x20]; 2367 2368 u8 phy_corrected_bits_lane3_high[0x20]; 2369 2370 u8 phy_corrected_bits_lane3_low[0x20]; 2371 2372 u8 reserved_at_200[0x5c0]; 2373 }; 2374 2375 struct mlx5_ifc_ib_port_cntrs_grp_data_layout_bits { 2376 u8 symbol_error_counter[0x10]; 2377 2378 u8 link_error_recovery_counter[0x8]; 2379 2380 u8 link_downed_counter[0x8]; 2381 2382 u8 port_rcv_errors[0x10]; 2383 2384 u8 port_rcv_remote_physical_errors[0x10]; 2385 2386 u8 port_rcv_switch_relay_errors[0x10]; 2387 2388 u8 port_xmit_discards[0x10]; 2389 2390 u8 port_xmit_constraint_errors[0x8]; 2391 2392 u8 port_rcv_constraint_errors[0x8]; 2393 2394 u8 reserved_at_70[0x8]; 2395 2396 u8 link_overrun_errors[0x8]; 2397 2398 u8 reserved_at_80[0x10]; 2399 2400 u8 vl_15_dropped[0x10]; 2401 2402 u8 reserved_at_a0[0x80]; 2403 2404 u8 port_xmit_wait[0x20]; 2405 }; 2406 2407 struct mlx5_ifc_eth_per_tc_prio_grp_data_layout_bits { 2408 u8 transmit_queue_high[0x20]; 2409 2410 u8 transmit_queue_low[0x20]; 2411 2412 u8 no_buffer_discard_uc_high[0x20]; 2413 2414 u8 no_buffer_discard_uc_low[0x20]; 2415 2416 u8 reserved_at_80[0x740]; 2417 }; 2418 2419 struct mlx5_ifc_eth_per_tc_congest_prio_grp_data_layout_bits { 2420 u8 wred_discard_high[0x20]; 2421 2422 u8 wred_discard_low[0x20]; 2423 2424 u8 ecn_marked_tc_high[0x20]; 2425 2426 u8 ecn_marked_tc_low[0x20]; 2427 2428 u8 reserved_at_80[0x740]; 2429 }; 2430 2431 struct mlx5_ifc_eth_per_prio_grp_data_layout_bits { 2432 u8 rx_octets_high[0x20]; 2433 2434 u8 rx_octets_low[0x20]; 2435 2436 u8 reserved_at_40[0xc0]; 2437 2438 u8 rx_frames_high[0x20]; 2439 2440 u8 rx_frames_low[0x20]; 2441 2442 u8 tx_octets_high[0x20]; 2443 2444 u8 tx_octets_low[0x20]; 2445 2446 u8 reserved_at_180[0xc0]; 2447 2448 u8 tx_frames_high[0x20]; 2449 2450 u8 tx_frames_low[0x20]; 2451 2452 u8 rx_pause_high[0x20]; 2453 2454 u8 rx_pause_low[0x20]; 2455 2456 u8 rx_pause_duration_high[0x20]; 2457 2458 u8 rx_pause_duration_low[0x20]; 2459 2460 u8 tx_pause_high[0x20]; 2461 2462 u8 tx_pause_low[0x20]; 2463 2464 u8 tx_pause_duration_high[0x20]; 2465 2466 u8 tx_pause_duration_low[0x20]; 2467 2468 u8 rx_pause_transition_high[0x20]; 2469 2470 u8 rx_pause_transition_low[0x20]; 2471 2472 u8 rx_discards_high[0x20]; 2473 2474 u8 rx_discards_low[0x20]; 2475 2476 u8 device_stall_minor_watermark_cnt_high[0x20]; 2477 2478 u8 device_stall_minor_watermark_cnt_low[0x20]; 2479 2480 u8 device_stall_critical_watermark_cnt_high[0x20]; 2481 2482 u8 device_stall_critical_watermark_cnt_low[0x20]; 2483 2484 u8 reserved_at_480[0x340]; 2485 }; 2486 2487 struct mlx5_ifc_eth_extended_cntrs_grp_data_layout_bits { 2488 u8 port_transmit_wait_high[0x20]; 2489 2490 u8 port_transmit_wait_low[0x20]; 2491 2492 u8 reserved_at_40[0x100]; 2493 2494 u8 rx_buffer_almost_full_high[0x20]; 2495 2496 u8 rx_buffer_almost_full_low[0x20]; 2497 2498 u8 rx_buffer_full_high[0x20]; 2499 2500 u8 rx_buffer_full_low[0x20]; 2501 2502 u8 rx_icrc_encapsulated_high[0x20]; 2503 2504 u8 rx_icrc_encapsulated_low[0x20]; 2505 2506 u8 reserved_at_200[0x5c0]; 2507 }; 2508 2509 struct mlx5_ifc_eth_3635_cntrs_grp_data_layout_bits { 2510 u8 dot3stats_alignment_errors_high[0x20]; 2511 2512 u8 dot3stats_alignment_errors_low[0x20]; 2513 2514 u8 dot3stats_fcs_errors_high[0x20]; 2515 2516 u8 dot3stats_fcs_errors_low[0x20]; 2517 2518 u8 dot3stats_single_collision_frames_high[0x20]; 2519 2520 u8 dot3stats_single_collision_frames_low[0x20]; 2521 2522 u8 dot3stats_multiple_collision_frames_high[0x20]; 2523 2524 u8 dot3stats_multiple_collision_frames_low[0x20]; 2525 2526 u8 dot3stats_sqe_test_errors_high[0x20]; 2527 2528 u8 dot3stats_sqe_test_errors_low[0x20]; 2529 2530 u8 dot3stats_deferred_transmissions_high[0x20]; 2531 2532 u8 dot3stats_deferred_transmissions_low[0x20]; 2533 2534 u8 dot3stats_late_collisions_high[0x20]; 2535 2536 u8 dot3stats_late_collisions_low[0x20]; 2537 2538 u8 dot3stats_excessive_collisions_high[0x20]; 2539 2540 u8 dot3stats_excessive_collisions_low[0x20]; 2541 2542 u8 dot3stats_internal_mac_transmit_errors_high[0x20]; 2543 2544 u8 dot3stats_internal_mac_transmit_errors_low[0x20]; 2545 2546 u8 dot3stats_carrier_sense_errors_high[0x20]; 2547 2548 u8 dot3stats_carrier_sense_errors_low[0x20]; 2549 2550 u8 dot3stats_frame_too_longs_high[0x20]; 2551 2552 u8 dot3stats_frame_too_longs_low[0x20]; 2553 2554 u8 dot3stats_internal_mac_receive_errors_high[0x20]; 2555 2556 u8 dot3stats_internal_mac_receive_errors_low[0x20]; 2557 2558 u8 dot3stats_symbol_errors_high[0x20]; 2559 2560 u8 dot3stats_symbol_errors_low[0x20]; 2561 2562 u8 dot3control_in_unknown_opcodes_high[0x20]; 2563 2564 u8 dot3control_in_unknown_opcodes_low[0x20]; 2565 2566 u8 dot3in_pause_frames_high[0x20]; 2567 2568 u8 dot3in_pause_frames_low[0x20]; 2569 2570 u8 dot3out_pause_frames_high[0x20]; 2571 2572 u8 dot3out_pause_frames_low[0x20]; 2573 2574 u8 reserved_at_400[0x3c0]; 2575 }; 2576 2577 struct mlx5_ifc_eth_2819_cntrs_grp_data_layout_bits { 2578 u8 ether_stats_drop_events_high[0x20]; 2579 2580 u8 ether_stats_drop_events_low[0x20]; 2581 2582 u8 ether_stats_octets_high[0x20]; 2583 2584 u8 ether_stats_octets_low[0x20]; 2585 2586 u8 ether_stats_pkts_high[0x20]; 2587 2588 u8 ether_stats_pkts_low[0x20]; 2589 2590 u8 ether_stats_broadcast_pkts_high[0x20]; 2591 2592 u8 ether_stats_broadcast_pkts_low[0x20]; 2593 2594 u8 ether_stats_multicast_pkts_high[0x20]; 2595 2596 u8 ether_stats_multicast_pkts_low[0x20]; 2597 2598 u8 ether_stats_crc_align_errors_high[0x20]; 2599 2600 u8 ether_stats_crc_align_errors_low[0x20]; 2601 2602 u8 ether_stats_undersize_pkts_high[0x20]; 2603 2604 u8 ether_stats_undersize_pkts_low[0x20]; 2605 2606 u8 ether_stats_oversize_pkts_high[0x20]; 2607 2608 u8 ether_stats_oversize_pkts_low[0x20]; 2609 2610 u8 ether_stats_fragments_high[0x20]; 2611 2612 u8 ether_stats_fragments_low[0x20]; 2613 2614 u8 ether_stats_jabbers_high[0x20]; 2615 2616 u8 ether_stats_jabbers_low[0x20]; 2617 2618 u8 ether_stats_collisions_high[0x20]; 2619 2620 u8 ether_stats_collisions_low[0x20]; 2621 2622 u8 ether_stats_pkts64octets_high[0x20]; 2623 2624 u8 ether_stats_pkts64octets_low[0x20]; 2625 2626 u8 ether_stats_pkts65to127octets_high[0x20]; 2627 2628 u8 ether_stats_pkts65to127octets_low[0x20]; 2629 2630 u8 ether_stats_pkts128to255octets_high[0x20]; 2631 2632 u8 ether_stats_pkts128to255octets_low[0x20]; 2633 2634 u8 ether_stats_pkts256to511octets_high[0x20]; 2635 2636 u8 ether_stats_pkts256to511octets_low[0x20]; 2637 2638 u8 ether_stats_pkts512to1023octets_high[0x20]; 2639 2640 u8 ether_stats_pkts512to1023octets_low[0x20]; 2641 2642 u8 ether_stats_pkts1024to1518octets_high[0x20]; 2643 2644 u8 ether_stats_pkts1024to1518octets_low[0x20]; 2645 2646 u8 ether_stats_pkts1519to2047octets_high[0x20]; 2647 2648 u8 ether_stats_pkts1519to2047octets_low[0x20]; 2649 2650 u8 ether_stats_pkts2048to4095octets_high[0x20]; 2651 2652 u8 ether_stats_pkts2048to4095octets_low[0x20]; 2653 2654 u8 ether_stats_pkts4096to8191octets_high[0x20]; 2655 2656 u8 ether_stats_pkts4096to8191octets_low[0x20]; 2657 2658 u8 ether_stats_pkts8192to10239octets_high[0x20]; 2659 2660 u8 ether_stats_pkts8192to10239octets_low[0x20]; 2661 2662 u8 reserved_at_540[0x280]; 2663 }; 2664 2665 struct mlx5_ifc_eth_2863_cntrs_grp_data_layout_bits { 2666 u8 if_in_octets_high[0x20]; 2667 2668 u8 if_in_octets_low[0x20]; 2669 2670 u8 if_in_ucast_pkts_high[0x20]; 2671 2672 u8 if_in_ucast_pkts_low[0x20]; 2673 2674 u8 if_in_discards_high[0x20]; 2675 2676 u8 if_in_discards_low[0x20]; 2677 2678 u8 if_in_errors_high[0x20]; 2679 2680 u8 if_in_errors_low[0x20]; 2681 2682 u8 if_in_unknown_protos_high[0x20]; 2683 2684 u8 if_in_unknown_protos_low[0x20]; 2685 2686 u8 if_out_octets_high[0x20]; 2687 2688 u8 if_out_octets_low[0x20]; 2689 2690 u8 if_out_ucast_pkts_high[0x20]; 2691 2692 u8 if_out_ucast_pkts_low[0x20]; 2693 2694 u8 if_out_discards_high[0x20]; 2695 2696 u8 if_out_discards_low[0x20]; 2697 2698 u8 if_out_errors_high[0x20]; 2699 2700 u8 if_out_errors_low[0x20]; 2701 2702 u8 if_in_multicast_pkts_high[0x20]; 2703 2704 u8 if_in_multicast_pkts_low[0x20]; 2705 2706 u8 if_in_broadcast_pkts_high[0x20]; 2707 2708 u8 if_in_broadcast_pkts_low[0x20]; 2709 2710 u8 if_out_multicast_pkts_high[0x20]; 2711 2712 u8 if_out_multicast_pkts_low[0x20]; 2713 2714 u8 if_out_broadcast_pkts_high[0x20]; 2715 2716 u8 if_out_broadcast_pkts_low[0x20]; 2717 2718 u8 reserved_at_340[0x480]; 2719 }; 2720 2721 struct mlx5_ifc_eth_802_3_cntrs_grp_data_layout_bits { 2722 u8 a_frames_transmitted_ok_high[0x20]; 2723 2724 u8 a_frames_transmitted_ok_low[0x20]; 2725 2726 u8 a_frames_received_ok_high[0x20]; 2727 2728 u8 a_frames_received_ok_low[0x20]; 2729 2730 u8 a_frame_check_sequence_errors_high[0x20]; 2731 2732 u8 a_frame_check_sequence_errors_low[0x20]; 2733 2734 u8 a_alignment_errors_high[0x20]; 2735 2736 u8 a_alignment_errors_low[0x20]; 2737 2738 u8 a_octets_transmitted_ok_high[0x20]; 2739 2740 u8 a_octets_transmitted_ok_low[0x20]; 2741 2742 u8 a_octets_received_ok_high[0x20]; 2743 2744 u8 a_octets_received_ok_low[0x20]; 2745 2746 u8 a_multicast_frames_xmitted_ok_high[0x20]; 2747 2748 u8 a_multicast_frames_xmitted_ok_low[0x20]; 2749 2750 u8 a_broadcast_frames_xmitted_ok_high[0x20]; 2751 2752 u8 a_broadcast_frames_xmitted_ok_low[0x20]; 2753 2754 u8 a_multicast_frames_received_ok_high[0x20]; 2755 2756 u8 a_multicast_frames_received_ok_low[0x20]; 2757 2758 u8 a_broadcast_frames_received_ok_high[0x20]; 2759 2760 u8 a_broadcast_frames_received_ok_low[0x20]; 2761 2762 u8 a_in_range_length_errors_high[0x20]; 2763 2764 u8 a_in_range_length_errors_low[0x20]; 2765 2766 u8 a_out_of_range_length_field_high[0x20]; 2767 2768 u8 a_out_of_range_length_field_low[0x20]; 2769 2770 u8 a_frame_too_long_errors_high[0x20]; 2771 2772 u8 a_frame_too_long_errors_low[0x20]; 2773 2774 u8 a_symbol_error_during_carrier_high[0x20]; 2775 2776 u8 a_symbol_error_during_carrier_low[0x20]; 2777 2778 u8 a_mac_control_frames_transmitted_high[0x20]; 2779 2780 u8 a_mac_control_frames_transmitted_low[0x20]; 2781 2782 u8 a_mac_control_frames_received_high[0x20]; 2783 2784 u8 a_mac_control_frames_received_low[0x20]; 2785 2786 u8 a_unsupported_opcodes_received_high[0x20]; 2787 2788 u8 a_unsupported_opcodes_received_low[0x20]; 2789 2790 u8 a_pause_mac_ctrl_frames_received_high[0x20]; 2791 2792 u8 a_pause_mac_ctrl_frames_received_low[0x20]; 2793 2794 u8 a_pause_mac_ctrl_frames_transmitted_high[0x20]; 2795 2796 u8 a_pause_mac_ctrl_frames_transmitted_low[0x20]; 2797 2798 u8 reserved_at_4c0[0x300]; 2799 }; 2800 2801 struct mlx5_ifc_pcie_perf_cntrs_grp_data_layout_bits { 2802 u8 life_time_counter_high[0x20]; 2803 2804 u8 life_time_counter_low[0x20]; 2805 2806 u8 rx_errors[0x20]; 2807 2808 u8 tx_errors[0x20]; 2809 2810 u8 l0_to_recovery_eieos[0x20]; 2811 2812 u8 l0_to_recovery_ts[0x20]; 2813 2814 u8 l0_to_recovery_framing[0x20]; 2815 2816 u8 l0_to_recovery_retrain[0x20]; 2817 2818 u8 crc_error_dllp[0x20]; 2819 2820 u8 crc_error_tlp[0x20]; 2821 2822 u8 tx_overflow_buffer_pkt_high[0x20]; 2823 2824 u8 tx_overflow_buffer_pkt_low[0x20]; 2825 2826 u8 outbound_stalled_reads[0x20]; 2827 2828 u8 outbound_stalled_writes[0x20]; 2829 2830 u8 outbound_stalled_reads_events[0x20]; 2831 2832 u8 outbound_stalled_writes_events[0x20]; 2833 2834 u8 reserved_at_200[0x5c0]; 2835 }; 2836 2837 struct mlx5_ifc_cmd_inter_comp_event_bits { 2838 u8 command_completion_vector[0x20]; 2839 2840 u8 reserved_at_20[0xc0]; 2841 }; 2842 2843 struct mlx5_ifc_stall_vl_event_bits { 2844 u8 reserved_at_0[0x18]; 2845 u8 port_num[0x1]; 2846 u8 reserved_at_19[0x3]; 2847 u8 vl[0x4]; 2848 2849 u8 reserved_at_20[0xa0]; 2850 }; 2851 2852 struct mlx5_ifc_db_bf_congestion_event_bits { 2853 u8 event_subtype[0x8]; 2854 u8 reserved_at_8[0x8]; 2855 u8 congestion_level[0x8]; 2856 u8 reserved_at_18[0x8]; 2857 2858 u8 reserved_at_20[0xa0]; 2859 }; 2860 2861 struct mlx5_ifc_gpio_event_bits { 2862 u8 reserved_at_0[0x60]; 2863 2864 u8 gpio_event_hi[0x20]; 2865 2866 u8 gpio_event_lo[0x20]; 2867 2868 u8 reserved_at_a0[0x40]; 2869 }; 2870 2871 struct mlx5_ifc_port_state_change_event_bits { 2872 u8 reserved_at_0[0x40]; 2873 2874 u8 port_num[0x4]; 2875 u8 reserved_at_44[0x1c]; 2876 2877 u8 reserved_at_60[0x80]; 2878 }; 2879 2880 struct mlx5_ifc_dropped_packet_logged_bits { 2881 u8 reserved_at_0[0xe0]; 2882 }; 2883 2884 struct mlx5_ifc_default_timeout_bits { 2885 u8 to_multiplier[0x3]; 2886 u8 reserved_at_3[0x9]; 2887 u8 to_value[0x14]; 2888 }; 2889 2890 struct mlx5_ifc_dtor_reg_bits { 2891 u8 reserved_at_0[0x20]; 2892 2893 struct mlx5_ifc_default_timeout_bits pcie_toggle_to; 2894 2895 u8 reserved_at_40[0x60]; 2896 2897 struct mlx5_ifc_default_timeout_bits health_poll_to; 2898 2899 struct mlx5_ifc_default_timeout_bits full_crdump_to; 2900 2901 struct mlx5_ifc_default_timeout_bits fw_reset_to; 2902 2903 struct mlx5_ifc_default_timeout_bits flush_on_err_to; 2904 2905 struct mlx5_ifc_default_timeout_bits pci_sync_update_to; 2906 2907 struct mlx5_ifc_default_timeout_bits tear_down_to; 2908 2909 struct mlx5_ifc_default_timeout_bits fsm_reactivate_to; 2910 2911 struct mlx5_ifc_default_timeout_bits reclaim_pages_to; 2912 2913 struct mlx5_ifc_default_timeout_bits reclaim_vfs_pages_to; 2914 2915 u8 reserved_at_1c0[0x40]; 2916 }; 2917 2918 enum { 2919 MLX5_CQ_ERROR_SYNDROME_CQ_OVERRUN = 0x1, 2920 MLX5_CQ_ERROR_SYNDROME_CQ_ACCESS_VIOLATION_ERROR = 0x2, 2921 }; 2922 2923 struct mlx5_ifc_cq_error_bits { 2924 u8 reserved_at_0[0x8]; 2925 u8 cqn[0x18]; 2926 2927 u8 reserved_at_20[0x20]; 2928 2929 u8 reserved_at_40[0x18]; 2930 u8 syndrome[0x8]; 2931 2932 u8 reserved_at_60[0x80]; 2933 }; 2934 2935 struct mlx5_ifc_rdma_page_fault_event_bits { 2936 u8 bytes_committed[0x20]; 2937 2938 u8 r_key[0x20]; 2939 2940 u8 reserved_at_40[0x10]; 2941 u8 packet_len[0x10]; 2942 2943 u8 rdma_op_len[0x20]; 2944 2945 u8 rdma_va[0x40]; 2946 2947 u8 reserved_at_c0[0x5]; 2948 u8 rdma[0x1]; 2949 u8 write[0x1]; 2950 u8 requestor[0x1]; 2951 u8 qp_number[0x18]; 2952 }; 2953 2954 struct mlx5_ifc_wqe_associated_page_fault_event_bits { 2955 u8 bytes_committed[0x20]; 2956 2957 u8 reserved_at_20[0x10]; 2958 u8 wqe_index[0x10]; 2959 2960 u8 reserved_at_40[0x10]; 2961 u8 len[0x10]; 2962 2963 u8 reserved_at_60[0x60]; 2964 2965 u8 reserved_at_c0[0x5]; 2966 u8 rdma[0x1]; 2967 u8 write_read[0x1]; 2968 u8 requestor[0x1]; 2969 u8 qpn[0x18]; 2970 }; 2971 2972 struct mlx5_ifc_qp_events_bits { 2973 u8 reserved_at_0[0xa0]; 2974 2975 u8 type[0x8]; 2976 u8 reserved_at_a8[0x18]; 2977 2978 u8 reserved_at_c0[0x8]; 2979 u8 qpn_rqn_sqn[0x18]; 2980 }; 2981 2982 struct mlx5_ifc_dct_events_bits { 2983 u8 reserved_at_0[0xc0]; 2984 2985 u8 reserved_at_c0[0x8]; 2986 u8 dct_number[0x18]; 2987 }; 2988 2989 struct mlx5_ifc_comp_event_bits { 2990 u8 reserved_at_0[0xc0]; 2991 2992 u8 reserved_at_c0[0x8]; 2993 u8 cq_number[0x18]; 2994 }; 2995 2996 enum { 2997 MLX5_QPC_STATE_RST = 0x0, 2998 MLX5_QPC_STATE_INIT = 0x1, 2999 MLX5_QPC_STATE_RTR = 0x2, 3000 MLX5_QPC_STATE_RTS = 0x3, 3001 MLX5_QPC_STATE_SQER = 0x4, 3002 MLX5_QPC_STATE_ERR = 0x6, 3003 MLX5_QPC_STATE_SQD = 0x7, 3004 MLX5_QPC_STATE_SUSPENDED = 0x9, 3005 }; 3006 3007 enum { 3008 MLX5_QPC_ST_RC = 0x0, 3009 MLX5_QPC_ST_UC = 0x1, 3010 MLX5_QPC_ST_UD = 0x2, 3011 MLX5_QPC_ST_XRC = 0x3, 3012 MLX5_QPC_ST_DCI = 0x5, 3013 MLX5_QPC_ST_QP0 = 0x7, 3014 MLX5_QPC_ST_QP1 = 0x8, 3015 MLX5_QPC_ST_RAW_DATAGRAM = 0x9, 3016 MLX5_QPC_ST_REG_UMR = 0xc, 3017 }; 3018 3019 enum { 3020 MLX5_QPC_PM_STATE_ARMED = 0x0, 3021 MLX5_QPC_PM_STATE_REARM = 0x1, 3022 MLX5_QPC_PM_STATE_RESERVED = 0x2, 3023 MLX5_QPC_PM_STATE_MIGRATED = 0x3, 3024 }; 3025 3026 enum { 3027 MLX5_QPC_OFFLOAD_TYPE_RNDV = 0x1, 3028 }; 3029 3030 enum { 3031 MLX5_QPC_END_PADDING_MODE_SCATTER_AS_IS = 0x0, 3032 MLX5_QPC_END_PADDING_MODE_PAD_TO_CACHE_LINE_ALIGNMENT = 0x1, 3033 }; 3034 3035 enum { 3036 MLX5_QPC_MTU_256_BYTES = 0x1, 3037 MLX5_QPC_MTU_512_BYTES = 0x2, 3038 MLX5_QPC_MTU_1K_BYTES = 0x3, 3039 MLX5_QPC_MTU_2K_BYTES = 0x4, 3040 MLX5_QPC_MTU_4K_BYTES = 0x5, 3041 MLX5_QPC_MTU_RAW_ETHERNET_QP = 0x7, 3042 }; 3043 3044 enum { 3045 MLX5_QPC_ATOMIC_MODE_IB_SPEC = 0x1, 3046 MLX5_QPC_ATOMIC_MODE_ONLY_8B = 0x2, 3047 MLX5_QPC_ATOMIC_MODE_UP_TO_8B = 0x3, 3048 MLX5_QPC_ATOMIC_MODE_UP_TO_16B = 0x4, 3049 MLX5_QPC_ATOMIC_MODE_UP_TO_32B = 0x5, 3050 MLX5_QPC_ATOMIC_MODE_UP_TO_64B = 0x6, 3051 MLX5_QPC_ATOMIC_MODE_UP_TO_128B = 0x7, 3052 MLX5_QPC_ATOMIC_MODE_UP_TO_256B = 0x8, 3053 }; 3054 3055 enum { 3056 MLX5_QPC_CS_REQ_DISABLE = 0x0, 3057 MLX5_QPC_CS_REQ_UP_TO_32B = 0x11, 3058 MLX5_QPC_CS_REQ_UP_TO_64B = 0x22, 3059 }; 3060 3061 enum { 3062 MLX5_QPC_CS_RES_DISABLE = 0x0, 3063 MLX5_QPC_CS_RES_UP_TO_32B = 0x1, 3064 MLX5_QPC_CS_RES_UP_TO_64B = 0x2, 3065 }; 3066 3067 enum { 3068 MLX5_TIMESTAMP_FORMAT_FREE_RUNNING = 0x0, 3069 MLX5_TIMESTAMP_FORMAT_DEFAULT = 0x1, 3070 MLX5_TIMESTAMP_FORMAT_REAL_TIME = 0x2, 3071 }; 3072 3073 struct mlx5_ifc_qpc_bits { 3074 u8 state[0x4]; 3075 u8 lag_tx_port_affinity[0x4]; 3076 u8 st[0x8]; 3077 u8 reserved_at_10[0x2]; 3078 u8 isolate_vl_tc[0x1]; 3079 u8 pm_state[0x2]; 3080 u8 reserved_at_15[0x1]; 3081 u8 req_e2e_credit_mode[0x2]; 3082 u8 offload_type[0x4]; 3083 u8 end_padding_mode[0x2]; 3084 u8 reserved_at_1e[0x2]; 3085 3086 u8 wq_signature[0x1]; 3087 u8 block_lb_mc[0x1]; 3088 u8 atomic_like_write_en[0x1]; 3089 u8 latency_sensitive[0x1]; 3090 u8 reserved_at_24[0x1]; 3091 u8 drain_sigerr[0x1]; 3092 u8 reserved_at_26[0x2]; 3093 u8 pd[0x18]; 3094 3095 u8 mtu[0x3]; 3096 u8 log_msg_max[0x5]; 3097 u8 reserved_at_48[0x1]; 3098 u8 log_rq_size[0x4]; 3099 u8 log_rq_stride[0x3]; 3100 u8 no_sq[0x1]; 3101 u8 log_sq_size[0x4]; 3102 u8 reserved_at_55[0x3]; 3103 u8 ts_format[0x2]; 3104 u8 reserved_at_5a[0x1]; 3105 u8 rlky[0x1]; 3106 u8 ulp_stateless_offload_mode[0x4]; 3107 3108 u8 counter_set_id[0x8]; 3109 u8 uar_page[0x18]; 3110 3111 u8 reserved_at_80[0x8]; 3112 u8 user_index[0x18]; 3113 3114 u8 reserved_at_a0[0x3]; 3115 u8 log_page_size[0x5]; 3116 u8 remote_qpn[0x18]; 3117 3118 struct mlx5_ifc_ads_bits primary_address_path; 3119 3120 struct mlx5_ifc_ads_bits secondary_address_path; 3121 3122 u8 log_ack_req_freq[0x4]; 3123 u8 reserved_at_384[0x4]; 3124 u8 log_sra_max[0x3]; 3125 u8 reserved_at_38b[0x2]; 3126 u8 retry_count[0x3]; 3127 u8 rnr_retry[0x3]; 3128 u8 reserved_at_393[0x1]; 3129 u8 fre[0x1]; 3130 u8 cur_rnr_retry[0x3]; 3131 u8 cur_retry_count[0x3]; 3132 u8 reserved_at_39b[0x5]; 3133 3134 u8 reserved_at_3a0[0x20]; 3135 3136 u8 reserved_at_3c0[0x8]; 3137 u8 next_send_psn[0x18]; 3138 3139 u8 reserved_at_3e0[0x3]; 3140 u8 log_num_dci_stream_channels[0x5]; 3141 u8 cqn_snd[0x18]; 3142 3143 u8 reserved_at_400[0x3]; 3144 u8 log_num_dci_errored_streams[0x5]; 3145 u8 deth_sqpn[0x18]; 3146 3147 u8 reserved_at_420[0x20]; 3148 3149 u8 reserved_at_440[0x8]; 3150 u8 last_acked_psn[0x18]; 3151 3152 u8 reserved_at_460[0x8]; 3153 u8 ssn[0x18]; 3154 3155 u8 reserved_at_480[0x8]; 3156 u8 log_rra_max[0x3]; 3157 u8 reserved_at_48b[0x1]; 3158 u8 atomic_mode[0x4]; 3159 u8 rre[0x1]; 3160 u8 rwe[0x1]; 3161 u8 rae[0x1]; 3162 u8 reserved_at_493[0x1]; 3163 u8 page_offset[0x6]; 3164 u8 reserved_at_49a[0x3]; 3165 u8 cd_slave_receive[0x1]; 3166 u8 cd_slave_send[0x1]; 3167 u8 cd_master[0x1]; 3168 3169 u8 reserved_at_4a0[0x3]; 3170 u8 min_rnr_nak[0x5]; 3171 u8 next_rcv_psn[0x18]; 3172 3173 u8 reserved_at_4c0[0x8]; 3174 u8 xrcd[0x18]; 3175 3176 u8 reserved_at_4e0[0x8]; 3177 u8 cqn_rcv[0x18]; 3178 3179 u8 dbr_addr[0x40]; 3180 3181 u8 q_key[0x20]; 3182 3183 u8 reserved_at_560[0x5]; 3184 u8 rq_type[0x3]; 3185 u8 srqn_rmpn_xrqn[0x18]; 3186 3187 u8 reserved_at_580[0x8]; 3188 u8 rmsn[0x18]; 3189 3190 u8 hw_sq_wqebb_counter[0x10]; 3191 u8 sw_sq_wqebb_counter[0x10]; 3192 3193 u8 hw_rq_counter[0x20]; 3194 3195 u8 sw_rq_counter[0x20]; 3196 3197 u8 reserved_at_600[0x20]; 3198 3199 u8 reserved_at_620[0xf]; 3200 u8 cgs[0x1]; 3201 u8 cs_req[0x8]; 3202 u8 cs_res[0x8]; 3203 3204 u8 dc_access_key[0x40]; 3205 3206 u8 reserved_at_680[0x3]; 3207 u8 dbr_umem_valid[0x1]; 3208 3209 u8 reserved_at_684[0xbc]; 3210 }; 3211 3212 struct mlx5_ifc_roce_addr_layout_bits { 3213 u8 source_l3_address[16][0x8]; 3214 3215 u8 reserved_at_80[0x3]; 3216 u8 vlan_valid[0x1]; 3217 u8 vlan_id[0xc]; 3218 u8 source_mac_47_32[0x10]; 3219 3220 u8 source_mac_31_0[0x20]; 3221 3222 u8 reserved_at_c0[0x14]; 3223 u8 roce_l3_type[0x4]; 3224 u8 roce_version[0x8]; 3225 3226 u8 reserved_at_e0[0x20]; 3227 }; 3228 3229 struct mlx5_ifc_shampo_cap_bits { 3230 u8 reserved_at_0[0x3]; 3231 u8 shampo_log_max_reservation_size[0x5]; 3232 u8 reserved_at_8[0x3]; 3233 u8 shampo_log_min_reservation_size[0x5]; 3234 u8 shampo_min_mss_size[0x10]; 3235 3236 u8 reserved_at_20[0x3]; 3237 u8 shampo_max_log_headers_entry_size[0x5]; 3238 u8 reserved_at_28[0x18]; 3239 3240 u8 reserved_at_40[0x7c0]; 3241 }; 3242 3243 union mlx5_ifc_hca_cap_union_bits { 3244 struct mlx5_ifc_cmd_hca_cap_bits cmd_hca_cap; 3245 struct mlx5_ifc_cmd_hca_cap_2_bits cmd_hca_cap_2; 3246 struct mlx5_ifc_odp_cap_bits odp_cap; 3247 struct mlx5_ifc_atomic_caps_bits atomic_caps; 3248 struct mlx5_ifc_roce_cap_bits roce_cap; 3249 struct mlx5_ifc_per_protocol_networking_offload_caps_bits per_protocol_networking_offload_caps; 3250 struct mlx5_ifc_flow_table_nic_cap_bits flow_table_nic_cap; 3251 struct mlx5_ifc_flow_table_eswitch_cap_bits flow_table_eswitch_cap; 3252 struct mlx5_ifc_e_switch_cap_bits e_switch_cap; 3253 struct mlx5_ifc_port_selection_cap_bits port_selection_cap; 3254 struct mlx5_ifc_vector_calc_cap_bits vector_calc_cap; 3255 struct mlx5_ifc_qos_cap_bits qos_cap; 3256 struct mlx5_ifc_debug_cap_bits debug_cap; 3257 struct mlx5_ifc_fpga_cap_bits fpga_cap; 3258 struct mlx5_ifc_tls_cap_bits tls_cap; 3259 struct mlx5_ifc_device_mem_cap_bits device_mem_cap; 3260 struct mlx5_ifc_virtio_emulation_cap_bits virtio_emulation_cap; 3261 struct mlx5_ifc_shampo_cap_bits shampo_cap; 3262 u8 reserved_at_0[0x8000]; 3263 }; 3264 3265 enum { 3266 MLX5_FLOW_CONTEXT_ACTION_ALLOW = 0x1, 3267 MLX5_FLOW_CONTEXT_ACTION_DROP = 0x2, 3268 MLX5_FLOW_CONTEXT_ACTION_FWD_DEST = 0x4, 3269 MLX5_FLOW_CONTEXT_ACTION_COUNT = 0x8, 3270 MLX5_FLOW_CONTEXT_ACTION_PACKET_REFORMAT = 0x10, 3271 MLX5_FLOW_CONTEXT_ACTION_DECAP = 0x20, 3272 MLX5_FLOW_CONTEXT_ACTION_MOD_HDR = 0x40, 3273 MLX5_FLOW_CONTEXT_ACTION_VLAN_POP = 0x80, 3274 MLX5_FLOW_CONTEXT_ACTION_VLAN_PUSH = 0x100, 3275 MLX5_FLOW_CONTEXT_ACTION_VLAN_POP_2 = 0x400, 3276 MLX5_FLOW_CONTEXT_ACTION_VLAN_PUSH_2 = 0x800, 3277 MLX5_FLOW_CONTEXT_ACTION_IPSEC_DECRYPT = 0x1000, 3278 MLX5_FLOW_CONTEXT_ACTION_IPSEC_ENCRYPT = 0x2000, 3279 }; 3280 3281 enum { 3282 MLX5_FLOW_CONTEXT_FLOW_SOURCE_ANY_VPORT = 0x0, 3283 MLX5_FLOW_CONTEXT_FLOW_SOURCE_UPLINK = 0x1, 3284 MLX5_FLOW_CONTEXT_FLOW_SOURCE_LOCAL_VPORT = 0x2, 3285 }; 3286 3287 struct mlx5_ifc_vlan_bits { 3288 u8 ethtype[0x10]; 3289 u8 prio[0x3]; 3290 u8 cfi[0x1]; 3291 u8 vid[0xc]; 3292 }; 3293 3294 struct mlx5_ifc_flow_context_bits { 3295 struct mlx5_ifc_vlan_bits push_vlan; 3296 3297 u8 group_id[0x20]; 3298 3299 u8 reserved_at_40[0x8]; 3300 u8 flow_tag[0x18]; 3301 3302 u8 reserved_at_60[0x10]; 3303 u8 action[0x10]; 3304 3305 u8 extended_destination[0x1]; 3306 u8 reserved_at_81[0x1]; 3307 u8 flow_source[0x2]; 3308 u8 reserved_at_84[0x4]; 3309 u8 destination_list_size[0x18]; 3310 3311 u8 reserved_at_a0[0x8]; 3312 u8 flow_counter_list_size[0x18]; 3313 3314 u8 packet_reformat_id[0x20]; 3315 3316 u8 modify_header_id[0x20]; 3317 3318 struct mlx5_ifc_vlan_bits push_vlan_2; 3319 3320 u8 ipsec_obj_id[0x20]; 3321 u8 reserved_at_140[0xc0]; 3322 3323 struct mlx5_ifc_fte_match_param_bits match_value; 3324 3325 u8 reserved_at_1200[0x600]; 3326 3327 union mlx5_ifc_dest_format_struct_flow_counter_list_auto_bits destination[]; 3328 }; 3329 3330 enum { 3331 MLX5_XRC_SRQC_STATE_GOOD = 0x0, 3332 MLX5_XRC_SRQC_STATE_ERROR = 0x1, 3333 }; 3334 3335 struct mlx5_ifc_xrc_srqc_bits { 3336 u8 state[0x4]; 3337 u8 log_xrc_srq_size[0x4]; 3338 u8 reserved_at_8[0x18]; 3339 3340 u8 wq_signature[0x1]; 3341 u8 cont_srq[0x1]; 3342 u8 reserved_at_22[0x1]; 3343 u8 rlky[0x1]; 3344 u8 basic_cyclic_rcv_wqe[0x1]; 3345 u8 log_rq_stride[0x3]; 3346 u8 xrcd[0x18]; 3347 3348 u8 page_offset[0x6]; 3349 u8 reserved_at_46[0x1]; 3350 u8 dbr_umem_valid[0x1]; 3351 u8 cqn[0x18]; 3352 3353 u8 reserved_at_60[0x20]; 3354 3355 u8 user_index_equal_xrc_srqn[0x1]; 3356 u8 reserved_at_81[0x1]; 3357 u8 log_page_size[0x6]; 3358 u8 user_index[0x18]; 3359 3360 u8 reserved_at_a0[0x20]; 3361 3362 u8 reserved_at_c0[0x8]; 3363 u8 pd[0x18]; 3364 3365 u8 lwm[0x10]; 3366 u8 wqe_cnt[0x10]; 3367 3368 u8 reserved_at_100[0x40]; 3369 3370 u8 db_record_addr_h[0x20]; 3371 3372 u8 db_record_addr_l[0x1e]; 3373 u8 reserved_at_17e[0x2]; 3374 3375 u8 reserved_at_180[0x80]; 3376 }; 3377 3378 struct mlx5_ifc_vnic_diagnostic_statistics_bits { 3379 u8 counter_error_queues[0x20]; 3380 3381 u8 total_error_queues[0x20]; 3382 3383 u8 send_queue_priority_update_flow[0x20]; 3384 3385 u8 reserved_at_60[0x20]; 3386 3387 u8 nic_receive_steering_discard[0x40]; 3388 3389 u8 receive_discard_vport_down[0x40]; 3390 3391 u8 transmit_discard_vport_down[0x40]; 3392 3393 u8 reserved_at_140[0xa0]; 3394 3395 u8 internal_rq_out_of_buffer[0x20]; 3396 3397 u8 reserved_at_200[0xe00]; 3398 }; 3399 3400 struct mlx5_ifc_traffic_counter_bits { 3401 u8 packets[0x40]; 3402 3403 u8 octets[0x40]; 3404 }; 3405 3406 struct mlx5_ifc_tisc_bits { 3407 u8 strict_lag_tx_port_affinity[0x1]; 3408 u8 tls_en[0x1]; 3409 u8 reserved_at_2[0x2]; 3410 u8 lag_tx_port_affinity[0x04]; 3411 3412 u8 reserved_at_8[0x4]; 3413 u8 prio[0x4]; 3414 u8 reserved_at_10[0x10]; 3415 3416 u8 reserved_at_20[0x100]; 3417 3418 u8 reserved_at_120[0x8]; 3419 u8 transport_domain[0x18]; 3420 3421 u8 reserved_at_140[0x8]; 3422 u8 underlay_qpn[0x18]; 3423 3424 u8 reserved_at_160[0x8]; 3425 u8 pd[0x18]; 3426 3427 u8 reserved_at_180[0x380]; 3428 }; 3429 3430 enum { 3431 MLX5_TIRC_DISP_TYPE_DIRECT = 0x0, 3432 MLX5_TIRC_DISP_TYPE_INDIRECT = 0x1, 3433 }; 3434 3435 enum { 3436 MLX5_TIRC_PACKET_MERGE_MASK_IPV4_LRO = BIT(0), 3437 MLX5_TIRC_PACKET_MERGE_MASK_IPV6_LRO = BIT(1), 3438 }; 3439 3440 enum { 3441 MLX5_RX_HASH_FN_NONE = 0x0, 3442 MLX5_RX_HASH_FN_INVERTED_XOR8 = 0x1, 3443 MLX5_RX_HASH_FN_TOEPLITZ = 0x2, 3444 }; 3445 3446 enum { 3447 MLX5_TIRC_SELF_LB_BLOCK_BLOCK_UNICAST = 0x1, 3448 MLX5_TIRC_SELF_LB_BLOCK_BLOCK_MULTICAST = 0x2, 3449 }; 3450 3451 struct mlx5_ifc_tirc_bits { 3452 u8 reserved_at_0[0x20]; 3453 3454 u8 disp_type[0x4]; 3455 u8 tls_en[0x1]; 3456 u8 reserved_at_25[0x1b]; 3457 3458 u8 reserved_at_40[0x40]; 3459 3460 u8 reserved_at_80[0x4]; 3461 u8 lro_timeout_period_usecs[0x10]; 3462 u8 packet_merge_mask[0x4]; 3463 u8 lro_max_ip_payload_size[0x8]; 3464 3465 u8 reserved_at_a0[0x40]; 3466 3467 u8 reserved_at_e0[0x8]; 3468 u8 inline_rqn[0x18]; 3469 3470 u8 rx_hash_symmetric[0x1]; 3471 u8 reserved_at_101[0x1]; 3472 u8 tunneled_offload_en[0x1]; 3473 u8 reserved_at_103[0x5]; 3474 u8 indirect_table[0x18]; 3475 3476 u8 rx_hash_fn[0x4]; 3477 u8 reserved_at_124[0x2]; 3478 u8 self_lb_block[0x2]; 3479 u8 transport_domain[0x18]; 3480 3481 u8 rx_hash_toeplitz_key[10][0x20]; 3482 3483 struct mlx5_ifc_rx_hash_field_select_bits rx_hash_field_selector_outer; 3484 3485 struct mlx5_ifc_rx_hash_field_select_bits rx_hash_field_selector_inner; 3486 3487 u8 reserved_at_2c0[0x4c0]; 3488 }; 3489 3490 enum { 3491 MLX5_SRQC_STATE_GOOD = 0x0, 3492 MLX5_SRQC_STATE_ERROR = 0x1, 3493 }; 3494 3495 struct mlx5_ifc_srqc_bits { 3496 u8 state[0x4]; 3497 u8 log_srq_size[0x4]; 3498 u8 reserved_at_8[0x18]; 3499 3500 u8 wq_signature[0x1]; 3501 u8 cont_srq[0x1]; 3502 u8 reserved_at_22[0x1]; 3503 u8 rlky[0x1]; 3504 u8 reserved_at_24[0x1]; 3505 u8 log_rq_stride[0x3]; 3506 u8 xrcd[0x18]; 3507 3508 u8 page_offset[0x6]; 3509 u8 reserved_at_46[0x2]; 3510 u8 cqn[0x18]; 3511 3512 u8 reserved_at_60[0x20]; 3513 3514 u8 reserved_at_80[0x2]; 3515 u8 log_page_size[0x6]; 3516 u8 reserved_at_88[0x18]; 3517 3518 u8 reserved_at_a0[0x20]; 3519 3520 u8 reserved_at_c0[0x8]; 3521 u8 pd[0x18]; 3522 3523 u8 lwm[0x10]; 3524 u8 wqe_cnt[0x10]; 3525 3526 u8 reserved_at_100[0x40]; 3527 3528 u8 dbr_addr[0x40]; 3529 3530 u8 reserved_at_180[0x80]; 3531 }; 3532 3533 enum { 3534 MLX5_SQC_STATE_RST = 0x0, 3535 MLX5_SQC_STATE_RDY = 0x1, 3536 MLX5_SQC_STATE_ERR = 0x3, 3537 }; 3538 3539 struct mlx5_ifc_sqc_bits { 3540 u8 rlky[0x1]; 3541 u8 cd_master[0x1]; 3542 u8 fre[0x1]; 3543 u8 flush_in_error_en[0x1]; 3544 u8 allow_multi_pkt_send_wqe[0x1]; 3545 u8 min_wqe_inline_mode[0x3]; 3546 u8 state[0x4]; 3547 u8 reg_umr[0x1]; 3548 u8 allow_swp[0x1]; 3549 u8 hairpin[0x1]; 3550 u8 reserved_at_f[0xb]; 3551 u8 ts_format[0x2]; 3552 u8 reserved_at_1c[0x4]; 3553 3554 u8 reserved_at_20[0x8]; 3555 u8 user_index[0x18]; 3556 3557 u8 reserved_at_40[0x8]; 3558 u8 cqn[0x18]; 3559 3560 u8 reserved_at_60[0x8]; 3561 u8 hairpin_peer_rq[0x18]; 3562 3563 u8 reserved_at_80[0x10]; 3564 u8 hairpin_peer_vhca[0x10]; 3565 3566 u8 reserved_at_a0[0x20]; 3567 3568 u8 reserved_at_c0[0x8]; 3569 u8 ts_cqe_to_dest_cqn[0x18]; 3570 3571 u8 reserved_at_e0[0x10]; 3572 u8 packet_pacing_rate_limit_index[0x10]; 3573 u8 tis_lst_sz[0x10]; 3574 u8 qos_queue_group_id[0x10]; 3575 3576 u8 reserved_at_120[0x40]; 3577 3578 u8 reserved_at_160[0x8]; 3579 u8 tis_num_0[0x18]; 3580 3581 struct mlx5_ifc_wq_bits wq; 3582 }; 3583 3584 enum { 3585 SCHEDULING_CONTEXT_ELEMENT_TYPE_TSAR = 0x0, 3586 SCHEDULING_CONTEXT_ELEMENT_TYPE_VPORT = 0x1, 3587 SCHEDULING_CONTEXT_ELEMENT_TYPE_VPORT_TC = 0x2, 3588 SCHEDULING_CONTEXT_ELEMENT_TYPE_PARA_VPORT_TC = 0x3, 3589 SCHEDULING_CONTEXT_ELEMENT_TYPE_QUEUE_GROUP = 0x4, 3590 }; 3591 3592 enum { 3593 ELEMENT_TYPE_CAP_MASK_TASR = 1 << 0, 3594 ELEMENT_TYPE_CAP_MASK_VPORT = 1 << 1, 3595 ELEMENT_TYPE_CAP_MASK_VPORT_TC = 1 << 2, 3596 ELEMENT_TYPE_CAP_MASK_PARA_VPORT_TC = 1 << 3, 3597 }; 3598 3599 struct mlx5_ifc_scheduling_context_bits { 3600 u8 element_type[0x8]; 3601 u8 reserved_at_8[0x18]; 3602 3603 u8 element_attributes[0x20]; 3604 3605 u8 parent_element_id[0x20]; 3606 3607 u8 reserved_at_60[0x40]; 3608 3609 u8 bw_share[0x20]; 3610 3611 u8 max_average_bw[0x20]; 3612 3613 u8 reserved_at_e0[0x120]; 3614 }; 3615 3616 struct mlx5_ifc_rqtc_bits { 3617 u8 reserved_at_0[0xa0]; 3618 3619 u8 reserved_at_a0[0x5]; 3620 u8 list_q_type[0x3]; 3621 u8 reserved_at_a8[0x8]; 3622 u8 rqt_max_size[0x10]; 3623 3624 u8 rq_vhca_id_format[0x1]; 3625 u8 reserved_at_c1[0xf]; 3626 u8 rqt_actual_size[0x10]; 3627 3628 u8 reserved_at_e0[0x6a0]; 3629 3630 struct mlx5_ifc_rq_num_bits rq_num[]; 3631 }; 3632 3633 enum { 3634 MLX5_RQC_MEM_RQ_TYPE_MEMORY_RQ_INLINE = 0x0, 3635 MLX5_RQC_MEM_RQ_TYPE_MEMORY_RQ_RMP = 0x1, 3636 }; 3637 3638 enum { 3639 MLX5_RQC_STATE_RST = 0x0, 3640 MLX5_RQC_STATE_RDY = 0x1, 3641 MLX5_RQC_STATE_ERR = 0x3, 3642 }; 3643 3644 enum { 3645 MLX5_RQC_SHAMPO_NO_MATCH_ALIGNMENT_GRANULARITY_BYTE = 0x0, 3646 MLX5_RQC_SHAMPO_NO_MATCH_ALIGNMENT_GRANULARITY_STRIDE = 0x1, 3647 MLX5_RQC_SHAMPO_NO_MATCH_ALIGNMENT_GRANULARITY_PAGE = 0x2, 3648 }; 3649 3650 enum { 3651 MLX5_RQC_SHAMPO_MATCH_CRITERIA_TYPE_NO_MATCH = 0x0, 3652 MLX5_RQC_SHAMPO_MATCH_CRITERIA_TYPE_EXTENDED = 0x1, 3653 MLX5_RQC_SHAMPO_MATCH_CRITERIA_TYPE_FIVE_TUPLE = 0x2, 3654 }; 3655 3656 struct mlx5_ifc_rqc_bits { 3657 u8 rlky[0x1]; 3658 u8 delay_drop_en[0x1]; 3659 u8 scatter_fcs[0x1]; 3660 u8 vsd[0x1]; 3661 u8 mem_rq_type[0x4]; 3662 u8 state[0x4]; 3663 u8 reserved_at_c[0x1]; 3664 u8 flush_in_error_en[0x1]; 3665 u8 hairpin[0x1]; 3666 u8 reserved_at_f[0xb]; 3667 u8 ts_format[0x2]; 3668 u8 reserved_at_1c[0x4]; 3669 3670 u8 reserved_at_20[0x8]; 3671 u8 user_index[0x18]; 3672 3673 u8 reserved_at_40[0x8]; 3674 u8 cqn[0x18]; 3675 3676 u8 counter_set_id[0x8]; 3677 u8 reserved_at_68[0x18]; 3678 3679 u8 reserved_at_80[0x8]; 3680 u8 rmpn[0x18]; 3681 3682 u8 reserved_at_a0[0x8]; 3683 u8 hairpin_peer_sq[0x18]; 3684 3685 u8 reserved_at_c0[0x10]; 3686 u8 hairpin_peer_vhca[0x10]; 3687 3688 u8 reserved_at_e0[0x46]; 3689 u8 shampo_no_match_alignment_granularity[0x2]; 3690 u8 reserved_at_128[0x6]; 3691 u8 shampo_match_criteria_type[0x2]; 3692 u8 reservation_timeout[0x10]; 3693 3694 u8 reserved_at_140[0x40]; 3695 3696 struct mlx5_ifc_wq_bits wq; 3697 }; 3698 3699 enum { 3700 MLX5_RMPC_STATE_RDY = 0x1, 3701 MLX5_RMPC_STATE_ERR = 0x3, 3702 }; 3703 3704 struct mlx5_ifc_rmpc_bits { 3705 u8 reserved_at_0[0x8]; 3706 u8 state[0x4]; 3707 u8 reserved_at_c[0x14]; 3708 3709 u8 basic_cyclic_rcv_wqe[0x1]; 3710 u8 reserved_at_21[0x1f]; 3711 3712 u8 reserved_at_40[0x140]; 3713 3714 struct mlx5_ifc_wq_bits wq; 3715 }; 3716 3717 struct mlx5_ifc_nic_vport_context_bits { 3718 u8 reserved_at_0[0x5]; 3719 u8 min_wqe_inline_mode[0x3]; 3720 u8 reserved_at_8[0x15]; 3721 u8 disable_mc_local_lb[0x1]; 3722 u8 disable_uc_local_lb[0x1]; 3723 u8 roce_en[0x1]; 3724 3725 u8 arm_change_event[0x1]; 3726 u8 reserved_at_21[0x1a]; 3727 u8 event_on_mtu[0x1]; 3728 u8 event_on_promisc_change[0x1]; 3729 u8 event_on_vlan_change[0x1]; 3730 u8 event_on_mc_address_change[0x1]; 3731 u8 event_on_uc_address_change[0x1]; 3732 3733 u8 reserved_at_40[0xc]; 3734 3735 u8 affiliation_criteria[0x4]; 3736 u8 affiliated_vhca_id[0x10]; 3737 3738 u8 reserved_at_60[0xd0]; 3739 3740 u8 mtu[0x10]; 3741 3742 u8 system_image_guid[0x40]; 3743 u8 port_guid[0x40]; 3744 u8 node_guid[0x40]; 3745 3746 u8 reserved_at_200[0x140]; 3747 u8 qkey_violation_counter[0x10]; 3748 u8 reserved_at_350[0x430]; 3749 3750 u8 promisc_uc[0x1]; 3751 u8 promisc_mc[0x1]; 3752 u8 promisc_all[0x1]; 3753 u8 reserved_at_783[0x2]; 3754 u8 allowed_list_type[0x3]; 3755 u8 reserved_at_788[0xc]; 3756 u8 allowed_list_size[0xc]; 3757 3758 struct mlx5_ifc_mac_address_layout_bits permanent_address; 3759 3760 u8 reserved_at_7e0[0x20]; 3761 3762 u8 current_uc_mac_address[][0x40]; 3763 }; 3764 3765 enum { 3766 MLX5_MKC_ACCESS_MODE_PA = 0x0, 3767 MLX5_MKC_ACCESS_MODE_MTT = 0x1, 3768 MLX5_MKC_ACCESS_MODE_KLMS = 0x2, 3769 MLX5_MKC_ACCESS_MODE_KSM = 0x3, 3770 MLX5_MKC_ACCESS_MODE_SW_ICM = 0x4, 3771 MLX5_MKC_ACCESS_MODE_MEMIC = 0x5, 3772 }; 3773 3774 struct mlx5_ifc_mkc_bits { 3775 u8 reserved_at_0[0x1]; 3776 u8 free[0x1]; 3777 u8 reserved_at_2[0x1]; 3778 u8 access_mode_4_2[0x3]; 3779 u8 reserved_at_6[0x7]; 3780 u8 relaxed_ordering_write[0x1]; 3781 u8 reserved_at_e[0x1]; 3782 u8 small_fence_on_rdma_read_response[0x1]; 3783 u8 umr_en[0x1]; 3784 u8 a[0x1]; 3785 u8 rw[0x1]; 3786 u8 rr[0x1]; 3787 u8 lw[0x1]; 3788 u8 lr[0x1]; 3789 u8 access_mode_1_0[0x2]; 3790 u8 reserved_at_18[0x8]; 3791 3792 u8 qpn[0x18]; 3793 u8 mkey_7_0[0x8]; 3794 3795 u8 reserved_at_40[0x20]; 3796 3797 u8 length64[0x1]; 3798 u8 bsf_en[0x1]; 3799 u8 sync_umr[0x1]; 3800 u8 reserved_at_63[0x2]; 3801 u8 expected_sigerr_count[0x1]; 3802 u8 reserved_at_66[0x1]; 3803 u8 en_rinval[0x1]; 3804 u8 pd[0x18]; 3805 3806 u8 start_addr[0x40]; 3807 3808 u8 len[0x40]; 3809 3810 u8 bsf_octword_size[0x20]; 3811 3812 u8 reserved_at_120[0x80]; 3813 3814 u8 translations_octword_size[0x20]; 3815 3816 u8 reserved_at_1c0[0x19]; 3817 u8 relaxed_ordering_read[0x1]; 3818 u8 reserved_at_1d9[0x1]; 3819 u8 log_page_size[0x5]; 3820 3821 u8 reserved_at_1e0[0x20]; 3822 }; 3823 3824 struct mlx5_ifc_pkey_bits { 3825 u8 reserved_at_0[0x10]; 3826 u8 pkey[0x10]; 3827 }; 3828 3829 struct mlx5_ifc_array128_auto_bits { 3830 u8 array128_auto[16][0x8]; 3831 }; 3832 3833 struct mlx5_ifc_hca_vport_context_bits { 3834 u8 field_select[0x20]; 3835 3836 u8 reserved_at_20[0xe0]; 3837 3838 u8 sm_virt_aware[0x1]; 3839 u8 has_smi[0x1]; 3840 u8 has_raw[0x1]; 3841 u8 grh_required[0x1]; 3842 u8 reserved_at_104[0xc]; 3843 u8 port_physical_state[0x4]; 3844 u8 vport_state_policy[0x4]; 3845 u8 port_state[0x4]; 3846 u8 vport_state[0x4]; 3847 3848 u8 reserved_at_120[0x20]; 3849 3850 u8 system_image_guid[0x40]; 3851 3852 u8 port_guid[0x40]; 3853 3854 u8 node_guid[0x40]; 3855 3856 u8 cap_mask1[0x20]; 3857 3858 u8 cap_mask1_field_select[0x20]; 3859 3860 u8 cap_mask2[0x20]; 3861 3862 u8 cap_mask2_field_select[0x20]; 3863 3864 u8 reserved_at_280[0x80]; 3865 3866 u8 lid[0x10]; 3867 u8 reserved_at_310[0x4]; 3868 u8 init_type_reply[0x4]; 3869 u8 lmc[0x3]; 3870 u8 subnet_timeout[0x5]; 3871 3872 u8 sm_lid[0x10]; 3873 u8 sm_sl[0x4]; 3874 u8 reserved_at_334[0xc]; 3875 3876 u8 qkey_violation_counter[0x10]; 3877 u8 pkey_violation_counter[0x10]; 3878 3879 u8 reserved_at_360[0xca0]; 3880 }; 3881 3882 struct mlx5_ifc_esw_vport_context_bits { 3883 u8 fdb_to_vport_reg_c[0x1]; 3884 u8 reserved_at_1[0x2]; 3885 u8 vport_svlan_strip[0x1]; 3886 u8 vport_cvlan_strip[0x1]; 3887 u8 vport_svlan_insert[0x1]; 3888 u8 vport_cvlan_insert[0x2]; 3889 u8 fdb_to_vport_reg_c_id[0x8]; 3890 u8 reserved_at_10[0x10]; 3891 3892 u8 reserved_at_20[0x20]; 3893 3894 u8 svlan_cfi[0x1]; 3895 u8 svlan_pcp[0x3]; 3896 u8 svlan_id[0xc]; 3897 u8 cvlan_cfi[0x1]; 3898 u8 cvlan_pcp[0x3]; 3899 u8 cvlan_id[0xc]; 3900 3901 u8 reserved_at_60[0x720]; 3902 3903 u8 sw_steering_vport_icm_address_rx[0x40]; 3904 3905 u8 sw_steering_vport_icm_address_tx[0x40]; 3906 }; 3907 3908 enum { 3909 MLX5_EQC_STATUS_OK = 0x0, 3910 MLX5_EQC_STATUS_EQ_WRITE_FAILURE = 0xa, 3911 }; 3912 3913 enum { 3914 MLX5_EQC_ST_ARMED = 0x9, 3915 MLX5_EQC_ST_FIRED = 0xa, 3916 }; 3917 3918 struct mlx5_ifc_eqc_bits { 3919 u8 status[0x4]; 3920 u8 reserved_at_4[0x9]; 3921 u8 ec[0x1]; 3922 u8 oi[0x1]; 3923 u8 reserved_at_f[0x5]; 3924 u8 st[0x4]; 3925 u8 reserved_at_18[0x8]; 3926 3927 u8 reserved_at_20[0x20]; 3928 3929 u8 reserved_at_40[0x14]; 3930 u8 page_offset[0x6]; 3931 u8 reserved_at_5a[0x6]; 3932 3933 u8 reserved_at_60[0x3]; 3934 u8 log_eq_size[0x5]; 3935 u8 uar_page[0x18]; 3936 3937 u8 reserved_at_80[0x20]; 3938 3939 u8 reserved_at_a0[0x14]; 3940 u8 intr[0xc]; 3941 3942 u8 reserved_at_c0[0x3]; 3943 u8 log_page_size[0x5]; 3944 u8 reserved_at_c8[0x18]; 3945 3946 u8 reserved_at_e0[0x60]; 3947 3948 u8 reserved_at_140[0x8]; 3949 u8 consumer_counter[0x18]; 3950 3951 u8 reserved_at_160[0x8]; 3952 u8 producer_counter[0x18]; 3953 3954 u8 reserved_at_180[0x80]; 3955 }; 3956 3957 enum { 3958 MLX5_DCTC_STATE_ACTIVE = 0x0, 3959 MLX5_DCTC_STATE_DRAINING = 0x1, 3960 MLX5_DCTC_STATE_DRAINED = 0x2, 3961 }; 3962 3963 enum { 3964 MLX5_DCTC_CS_RES_DISABLE = 0x0, 3965 MLX5_DCTC_CS_RES_NA = 0x1, 3966 MLX5_DCTC_CS_RES_UP_TO_64B = 0x2, 3967 }; 3968 3969 enum { 3970 MLX5_DCTC_MTU_256_BYTES = 0x1, 3971 MLX5_DCTC_MTU_512_BYTES = 0x2, 3972 MLX5_DCTC_MTU_1K_BYTES = 0x3, 3973 MLX5_DCTC_MTU_2K_BYTES = 0x4, 3974 MLX5_DCTC_MTU_4K_BYTES = 0x5, 3975 }; 3976 3977 struct mlx5_ifc_dctc_bits { 3978 u8 reserved_at_0[0x4]; 3979 u8 state[0x4]; 3980 u8 reserved_at_8[0x18]; 3981 3982 u8 reserved_at_20[0x8]; 3983 u8 user_index[0x18]; 3984 3985 u8 reserved_at_40[0x8]; 3986 u8 cqn[0x18]; 3987 3988 u8 counter_set_id[0x8]; 3989 u8 atomic_mode[0x4]; 3990 u8 rre[0x1]; 3991 u8 rwe[0x1]; 3992 u8 rae[0x1]; 3993 u8 atomic_like_write_en[0x1]; 3994 u8 latency_sensitive[0x1]; 3995 u8 rlky[0x1]; 3996 u8 free_ar[0x1]; 3997 u8 reserved_at_73[0xd]; 3998 3999 u8 reserved_at_80[0x8]; 4000 u8 cs_res[0x8]; 4001 u8 reserved_at_90[0x3]; 4002 u8 min_rnr_nak[0x5]; 4003 u8 reserved_at_98[0x8]; 4004 4005 u8 reserved_at_a0[0x8]; 4006 u8 srqn_xrqn[0x18]; 4007 4008 u8 reserved_at_c0[0x8]; 4009 u8 pd[0x18]; 4010 4011 u8 tclass[0x8]; 4012 u8 reserved_at_e8[0x4]; 4013 u8 flow_label[0x14]; 4014 4015 u8 dc_access_key[0x40]; 4016 4017 u8 reserved_at_140[0x5]; 4018 u8 mtu[0x3]; 4019 u8 port[0x8]; 4020 u8 pkey_index[0x10]; 4021 4022 u8 reserved_at_160[0x8]; 4023 u8 my_addr_index[0x8]; 4024 u8 reserved_at_170[0x8]; 4025 u8 hop_limit[0x8]; 4026 4027 u8 dc_access_key_violation_count[0x20]; 4028 4029 u8 reserved_at_1a0[0x14]; 4030 u8 dei_cfi[0x1]; 4031 u8 eth_prio[0x3]; 4032 u8 ecn[0x2]; 4033 u8 dscp[0x6]; 4034 4035 u8 reserved_at_1c0[0x20]; 4036 u8 ece[0x20]; 4037 }; 4038 4039 enum { 4040 MLX5_CQC_STATUS_OK = 0x0, 4041 MLX5_CQC_STATUS_CQ_OVERFLOW = 0x9, 4042 MLX5_CQC_STATUS_CQ_WRITE_FAIL = 0xa, 4043 }; 4044 4045 enum { 4046 MLX5_CQC_CQE_SZ_64_BYTES = 0x0, 4047 MLX5_CQC_CQE_SZ_128_BYTES = 0x1, 4048 }; 4049 4050 enum { 4051 MLX5_CQC_ST_SOLICITED_NOTIFICATION_REQUEST_ARMED = 0x6, 4052 MLX5_CQC_ST_NOTIFICATION_REQUEST_ARMED = 0x9, 4053 MLX5_CQC_ST_FIRED = 0xa, 4054 }; 4055 4056 enum { 4057 MLX5_CQ_PERIOD_MODE_START_FROM_EQE = 0x0, 4058 MLX5_CQ_PERIOD_MODE_START_FROM_CQE = 0x1, 4059 MLX5_CQ_PERIOD_NUM_MODES 4060 }; 4061 4062 struct mlx5_ifc_cqc_bits { 4063 u8 status[0x4]; 4064 u8 reserved_at_4[0x2]; 4065 u8 dbr_umem_valid[0x1]; 4066 u8 apu_cq[0x1]; 4067 u8 cqe_sz[0x3]; 4068 u8 cc[0x1]; 4069 u8 reserved_at_c[0x1]; 4070 u8 scqe_break_moderation_en[0x1]; 4071 u8 oi[0x1]; 4072 u8 cq_period_mode[0x2]; 4073 u8 cqe_comp_en[0x1]; 4074 u8 mini_cqe_res_format[0x2]; 4075 u8 st[0x4]; 4076 u8 reserved_at_18[0x8]; 4077 4078 u8 reserved_at_20[0x20]; 4079 4080 u8 reserved_at_40[0x14]; 4081 u8 page_offset[0x6]; 4082 u8 reserved_at_5a[0x6]; 4083 4084 u8 reserved_at_60[0x3]; 4085 u8 log_cq_size[0x5]; 4086 u8 uar_page[0x18]; 4087 4088 u8 reserved_at_80[0x4]; 4089 u8 cq_period[0xc]; 4090 u8 cq_max_count[0x10]; 4091 4092 u8 c_eqn_or_apu_element[0x20]; 4093 4094 u8 reserved_at_c0[0x3]; 4095 u8 log_page_size[0x5]; 4096 u8 reserved_at_c8[0x18]; 4097 4098 u8 reserved_at_e0[0x20]; 4099 4100 u8 reserved_at_100[0x8]; 4101 u8 last_notified_index[0x18]; 4102 4103 u8 reserved_at_120[0x8]; 4104 u8 last_solicit_index[0x18]; 4105 4106 u8 reserved_at_140[0x8]; 4107 u8 consumer_counter[0x18]; 4108 4109 u8 reserved_at_160[0x8]; 4110 u8 producer_counter[0x18]; 4111 4112 u8 reserved_at_180[0x40]; 4113 4114 u8 dbr_addr[0x40]; 4115 }; 4116 4117 union mlx5_ifc_cong_control_roce_ecn_auto_bits { 4118 struct mlx5_ifc_cong_control_802_1qau_rp_bits cong_control_802_1qau_rp; 4119 struct mlx5_ifc_cong_control_r_roce_ecn_rp_bits cong_control_r_roce_ecn_rp; 4120 struct mlx5_ifc_cong_control_r_roce_ecn_np_bits cong_control_r_roce_ecn_np; 4121 u8 reserved_at_0[0x800]; 4122 }; 4123 4124 struct mlx5_ifc_query_adapter_param_block_bits { 4125 u8 reserved_at_0[0xc0]; 4126 4127 u8 reserved_at_c0[0x8]; 4128 u8 ieee_vendor_id[0x18]; 4129 4130 u8 reserved_at_e0[0x10]; 4131 u8 vsd_vendor_id[0x10]; 4132 4133 u8 vsd[208][0x8]; 4134 4135 u8 vsd_contd_psid[16][0x8]; 4136 }; 4137 4138 enum { 4139 MLX5_XRQC_STATE_GOOD = 0x0, 4140 MLX5_XRQC_STATE_ERROR = 0x1, 4141 }; 4142 4143 enum { 4144 MLX5_XRQC_TOPOLOGY_NO_SPECIAL_TOPOLOGY = 0x0, 4145 MLX5_XRQC_TOPOLOGY_TAG_MATCHING = 0x1, 4146 }; 4147 4148 enum { 4149 MLX5_XRQC_OFFLOAD_RNDV = 0x1, 4150 }; 4151 4152 struct mlx5_ifc_tag_matching_topology_context_bits { 4153 u8 log_matching_list_sz[0x4]; 4154 u8 reserved_at_4[0xc]; 4155 u8 append_next_index[0x10]; 4156 4157 u8 sw_phase_cnt[0x10]; 4158 u8 hw_phase_cnt[0x10]; 4159 4160 u8 reserved_at_40[0x40]; 4161 }; 4162 4163 struct mlx5_ifc_xrqc_bits { 4164 u8 state[0x4]; 4165 u8 rlkey[0x1]; 4166 u8 reserved_at_5[0xf]; 4167 u8 topology[0x4]; 4168 u8 reserved_at_18[0x4]; 4169 u8 offload[0x4]; 4170 4171 u8 reserved_at_20[0x8]; 4172 u8 user_index[0x18]; 4173 4174 u8 reserved_at_40[0x8]; 4175 u8 cqn[0x18]; 4176 4177 u8 reserved_at_60[0xa0]; 4178 4179 struct mlx5_ifc_tag_matching_topology_context_bits tag_matching_topology_context; 4180 4181 u8 reserved_at_180[0x280]; 4182 4183 struct mlx5_ifc_wq_bits wq; 4184 }; 4185 4186 union mlx5_ifc_modify_field_select_resize_field_select_auto_bits { 4187 struct mlx5_ifc_modify_field_select_bits modify_field_select; 4188 struct mlx5_ifc_resize_field_select_bits resize_field_select; 4189 u8 reserved_at_0[0x20]; 4190 }; 4191 4192 union mlx5_ifc_field_select_802_1_r_roce_auto_bits { 4193 struct mlx5_ifc_field_select_802_1qau_rp_bits field_select_802_1qau_rp; 4194 struct mlx5_ifc_field_select_r_roce_rp_bits field_select_r_roce_rp; 4195 struct mlx5_ifc_field_select_r_roce_np_bits field_select_r_roce_np; 4196 u8 reserved_at_0[0x20]; 4197 }; 4198 4199 union mlx5_ifc_eth_cntrs_grp_data_layout_auto_bits { 4200 struct mlx5_ifc_eth_802_3_cntrs_grp_data_layout_bits eth_802_3_cntrs_grp_data_layout; 4201 struct mlx5_ifc_eth_2863_cntrs_grp_data_layout_bits eth_2863_cntrs_grp_data_layout; 4202 struct mlx5_ifc_eth_2819_cntrs_grp_data_layout_bits eth_2819_cntrs_grp_data_layout; 4203 struct mlx5_ifc_eth_3635_cntrs_grp_data_layout_bits eth_3635_cntrs_grp_data_layout; 4204 struct mlx5_ifc_eth_extended_cntrs_grp_data_layout_bits eth_extended_cntrs_grp_data_layout; 4205 struct mlx5_ifc_eth_per_prio_grp_data_layout_bits eth_per_prio_grp_data_layout; 4206 struct mlx5_ifc_eth_per_tc_prio_grp_data_layout_bits eth_per_tc_prio_grp_data_layout; 4207 struct mlx5_ifc_eth_per_tc_congest_prio_grp_data_layout_bits eth_per_tc_congest_prio_grp_data_layout; 4208 struct mlx5_ifc_ib_port_cntrs_grp_data_layout_bits ib_port_cntrs_grp_data_layout; 4209 struct mlx5_ifc_phys_layer_cntrs_bits phys_layer_cntrs; 4210 struct mlx5_ifc_phys_layer_statistical_cntrs_bits phys_layer_statistical_cntrs; 4211 u8 reserved_at_0[0x7c0]; 4212 }; 4213 4214 union mlx5_ifc_pcie_cntrs_grp_data_layout_auto_bits { 4215 struct mlx5_ifc_pcie_perf_cntrs_grp_data_layout_bits pcie_perf_cntrs_grp_data_layout; 4216 u8 reserved_at_0[0x7c0]; 4217 }; 4218 4219 union mlx5_ifc_event_auto_bits { 4220 struct mlx5_ifc_comp_event_bits comp_event; 4221 struct mlx5_ifc_dct_events_bits dct_events; 4222 struct mlx5_ifc_qp_events_bits qp_events; 4223 struct mlx5_ifc_wqe_associated_page_fault_event_bits wqe_associated_page_fault_event; 4224 struct mlx5_ifc_rdma_page_fault_event_bits rdma_page_fault_event; 4225 struct mlx5_ifc_cq_error_bits cq_error; 4226 struct mlx5_ifc_dropped_packet_logged_bits dropped_packet_logged; 4227 struct mlx5_ifc_port_state_change_event_bits port_state_change_event; 4228 struct mlx5_ifc_gpio_event_bits gpio_event; 4229 struct mlx5_ifc_db_bf_congestion_event_bits db_bf_congestion_event; 4230 struct mlx5_ifc_stall_vl_event_bits stall_vl_event; 4231 struct mlx5_ifc_cmd_inter_comp_event_bits cmd_inter_comp_event; 4232 u8 reserved_at_0[0xe0]; 4233 }; 4234 4235 struct mlx5_ifc_health_buffer_bits { 4236 u8 reserved_at_0[0x100]; 4237 4238 u8 assert_existptr[0x20]; 4239 4240 u8 assert_callra[0x20]; 4241 4242 u8 reserved_at_140[0x20]; 4243 4244 u8 time[0x20]; 4245 4246 u8 fw_version[0x20]; 4247 4248 u8 hw_id[0x20]; 4249 4250 u8 rfr[0x1]; 4251 u8 reserved_at_1c1[0x3]; 4252 u8 valid[0x1]; 4253 u8 severity[0x3]; 4254 u8 reserved_at_1c8[0x18]; 4255 4256 u8 irisc_index[0x8]; 4257 u8 synd[0x8]; 4258 u8 ext_synd[0x10]; 4259 }; 4260 4261 struct mlx5_ifc_register_loopback_control_bits { 4262 u8 no_lb[0x1]; 4263 u8 reserved_at_1[0x7]; 4264 u8 port[0x8]; 4265 u8 reserved_at_10[0x10]; 4266 4267 u8 reserved_at_20[0x60]; 4268 }; 4269 4270 struct mlx5_ifc_vport_tc_element_bits { 4271 u8 traffic_class[0x4]; 4272 u8 reserved_at_4[0xc]; 4273 u8 vport_number[0x10]; 4274 }; 4275 4276 struct mlx5_ifc_vport_element_bits { 4277 u8 reserved_at_0[0x10]; 4278 u8 vport_number[0x10]; 4279 }; 4280 4281 enum { 4282 TSAR_ELEMENT_TSAR_TYPE_DWRR = 0x0, 4283 TSAR_ELEMENT_TSAR_TYPE_ROUND_ROBIN = 0x1, 4284 TSAR_ELEMENT_TSAR_TYPE_ETS = 0x2, 4285 }; 4286 4287 struct mlx5_ifc_tsar_element_bits { 4288 u8 reserved_at_0[0x8]; 4289 u8 tsar_type[0x8]; 4290 u8 reserved_at_10[0x10]; 4291 }; 4292 4293 enum { 4294 MLX5_TEARDOWN_HCA_OUT_FORCE_STATE_SUCCESS = 0x0, 4295 MLX5_TEARDOWN_HCA_OUT_FORCE_STATE_FAIL = 0x1, 4296 }; 4297 4298 struct mlx5_ifc_teardown_hca_out_bits { 4299 u8 status[0x8]; 4300 u8 reserved_at_8[0x18]; 4301 4302 u8 syndrome[0x20]; 4303 4304 u8 reserved_at_40[0x3f]; 4305 4306 u8 state[0x1]; 4307 }; 4308 4309 enum { 4310 MLX5_TEARDOWN_HCA_IN_PROFILE_GRACEFUL_CLOSE = 0x0, 4311 MLX5_TEARDOWN_HCA_IN_PROFILE_FORCE_CLOSE = 0x1, 4312 MLX5_TEARDOWN_HCA_IN_PROFILE_PREPARE_FAST_TEARDOWN = 0x2, 4313 }; 4314 4315 struct mlx5_ifc_teardown_hca_in_bits { 4316 u8 opcode[0x10]; 4317 u8 reserved_at_10[0x10]; 4318 4319 u8 reserved_at_20[0x10]; 4320 u8 op_mod[0x10]; 4321 4322 u8 reserved_at_40[0x10]; 4323 u8 profile[0x10]; 4324 4325 u8 reserved_at_60[0x20]; 4326 }; 4327 4328 struct mlx5_ifc_sqerr2rts_qp_out_bits { 4329 u8 status[0x8]; 4330 u8 reserved_at_8[0x18]; 4331 4332 u8 syndrome[0x20]; 4333 4334 u8 reserved_at_40[0x40]; 4335 }; 4336 4337 struct mlx5_ifc_sqerr2rts_qp_in_bits { 4338 u8 opcode[0x10]; 4339 u8 uid[0x10]; 4340 4341 u8 reserved_at_20[0x10]; 4342 u8 op_mod[0x10]; 4343 4344 u8 reserved_at_40[0x8]; 4345 u8 qpn[0x18]; 4346 4347 u8 reserved_at_60[0x20]; 4348 4349 u8 opt_param_mask[0x20]; 4350 4351 u8 reserved_at_a0[0x20]; 4352 4353 struct mlx5_ifc_qpc_bits qpc; 4354 4355 u8 reserved_at_800[0x80]; 4356 }; 4357 4358 struct mlx5_ifc_sqd2rts_qp_out_bits { 4359 u8 status[0x8]; 4360 u8 reserved_at_8[0x18]; 4361 4362 u8 syndrome[0x20]; 4363 4364 u8 reserved_at_40[0x40]; 4365 }; 4366 4367 struct mlx5_ifc_sqd2rts_qp_in_bits { 4368 u8 opcode[0x10]; 4369 u8 uid[0x10]; 4370 4371 u8 reserved_at_20[0x10]; 4372 u8 op_mod[0x10]; 4373 4374 u8 reserved_at_40[0x8]; 4375 u8 qpn[0x18]; 4376 4377 u8 reserved_at_60[0x20]; 4378 4379 u8 opt_param_mask[0x20]; 4380 4381 u8 reserved_at_a0[0x20]; 4382 4383 struct mlx5_ifc_qpc_bits qpc; 4384 4385 u8 reserved_at_800[0x80]; 4386 }; 4387 4388 struct mlx5_ifc_set_roce_address_out_bits { 4389 u8 status[0x8]; 4390 u8 reserved_at_8[0x18]; 4391 4392 u8 syndrome[0x20]; 4393 4394 u8 reserved_at_40[0x40]; 4395 }; 4396 4397 struct mlx5_ifc_set_roce_address_in_bits { 4398 u8 opcode[0x10]; 4399 u8 reserved_at_10[0x10]; 4400 4401 u8 reserved_at_20[0x10]; 4402 u8 op_mod[0x10]; 4403 4404 u8 roce_address_index[0x10]; 4405 u8 reserved_at_50[0xc]; 4406 u8 vhca_port_num[0x4]; 4407 4408 u8 reserved_at_60[0x20]; 4409 4410 struct mlx5_ifc_roce_addr_layout_bits roce_address; 4411 }; 4412 4413 struct mlx5_ifc_set_mad_demux_out_bits { 4414 u8 status[0x8]; 4415 u8 reserved_at_8[0x18]; 4416 4417 u8 syndrome[0x20]; 4418 4419 u8 reserved_at_40[0x40]; 4420 }; 4421 4422 enum { 4423 MLX5_SET_MAD_DEMUX_IN_DEMUX_MODE_PASS_ALL = 0x0, 4424 MLX5_SET_MAD_DEMUX_IN_DEMUX_MODE_SELECTIVE = 0x2, 4425 }; 4426 4427 struct mlx5_ifc_set_mad_demux_in_bits { 4428 u8 opcode[0x10]; 4429 u8 reserved_at_10[0x10]; 4430 4431 u8 reserved_at_20[0x10]; 4432 u8 op_mod[0x10]; 4433 4434 u8 reserved_at_40[0x20]; 4435 4436 u8 reserved_at_60[0x6]; 4437 u8 demux_mode[0x2]; 4438 u8 reserved_at_68[0x18]; 4439 }; 4440 4441 struct mlx5_ifc_set_l2_table_entry_out_bits { 4442 u8 status[0x8]; 4443 u8 reserved_at_8[0x18]; 4444 4445 u8 syndrome[0x20]; 4446 4447 u8 reserved_at_40[0x40]; 4448 }; 4449 4450 struct mlx5_ifc_set_l2_table_entry_in_bits { 4451 u8 opcode[0x10]; 4452 u8 reserved_at_10[0x10]; 4453 4454 u8 reserved_at_20[0x10]; 4455 u8 op_mod[0x10]; 4456 4457 u8 reserved_at_40[0x60]; 4458 4459 u8 reserved_at_a0[0x8]; 4460 u8 table_index[0x18]; 4461 4462 u8 reserved_at_c0[0x20]; 4463 4464 u8 reserved_at_e0[0x13]; 4465 u8 vlan_valid[0x1]; 4466 u8 vlan[0xc]; 4467 4468 struct mlx5_ifc_mac_address_layout_bits mac_address; 4469 4470 u8 reserved_at_140[0xc0]; 4471 }; 4472 4473 struct mlx5_ifc_set_issi_out_bits { 4474 u8 status[0x8]; 4475 u8 reserved_at_8[0x18]; 4476 4477 u8 syndrome[0x20]; 4478 4479 u8 reserved_at_40[0x40]; 4480 }; 4481 4482 struct mlx5_ifc_set_issi_in_bits { 4483 u8 opcode[0x10]; 4484 u8 reserved_at_10[0x10]; 4485 4486 u8 reserved_at_20[0x10]; 4487 u8 op_mod[0x10]; 4488 4489 u8 reserved_at_40[0x10]; 4490 u8 current_issi[0x10]; 4491 4492 u8 reserved_at_60[0x20]; 4493 }; 4494 4495 struct mlx5_ifc_set_hca_cap_out_bits { 4496 u8 status[0x8]; 4497 u8 reserved_at_8[0x18]; 4498 4499 u8 syndrome[0x20]; 4500 4501 u8 reserved_at_40[0x40]; 4502 }; 4503 4504 struct mlx5_ifc_set_hca_cap_in_bits { 4505 u8 opcode[0x10]; 4506 u8 reserved_at_10[0x10]; 4507 4508 u8 reserved_at_20[0x10]; 4509 u8 op_mod[0x10]; 4510 4511 u8 other_function[0x1]; 4512 u8 reserved_at_41[0xf]; 4513 u8 function_id[0x10]; 4514 4515 u8 reserved_at_60[0x20]; 4516 4517 union mlx5_ifc_hca_cap_union_bits capability; 4518 }; 4519 4520 enum { 4521 MLX5_SET_FTE_MODIFY_ENABLE_MASK_ACTION = 0x0, 4522 MLX5_SET_FTE_MODIFY_ENABLE_MASK_FLOW_TAG = 0x1, 4523 MLX5_SET_FTE_MODIFY_ENABLE_MASK_DESTINATION_LIST = 0x2, 4524 MLX5_SET_FTE_MODIFY_ENABLE_MASK_FLOW_COUNTERS = 0x3, 4525 MLX5_SET_FTE_MODIFY_ENABLE_MASK_IPSEC_OBJ_ID = 0x4 4526 }; 4527 4528 struct mlx5_ifc_set_fte_out_bits { 4529 u8 status[0x8]; 4530 u8 reserved_at_8[0x18]; 4531 4532 u8 syndrome[0x20]; 4533 4534 u8 reserved_at_40[0x40]; 4535 }; 4536 4537 struct mlx5_ifc_set_fte_in_bits { 4538 u8 opcode[0x10]; 4539 u8 reserved_at_10[0x10]; 4540 4541 u8 reserved_at_20[0x10]; 4542 u8 op_mod[0x10]; 4543 4544 u8 other_vport[0x1]; 4545 u8 reserved_at_41[0xf]; 4546 u8 vport_number[0x10]; 4547 4548 u8 reserved_at_60[0x20]; 4549 4550 u8 table_type[0x8]; 4551 u8 reserved_at_88[0x18]; 4552 4553 u8 reserved_at_a0[0x8]; 4554 u8 table_id[0x18]; 4555 4556 u8 ignore_flow_level[0x1]; 4557 u8 reserved_at_c1[0x17]; 4558 u8 modify_enable_mask[0x8]; 4559 4560 u8 reserved_at_e0[0x20]; 4561 4562 u8 flow_index[0x20]; 4563 4564 u8 reserved_at_120[0xe0]; 4565 4566 struct mlx5_ifc_flow_context_bits flow_context; 4567 }; 4568 4569 struct mlx5_ifc_rts2rts_qp_out_bits { 4570 u8 status[0x8]; 4571 u8 reserved_at_8[0x18]; 4572 4573 u8 syndrome[0x20]; 4574 4575 u8 reserved_at_40[0x20]; 4576 u8 ece[0x20]; 4577 }; 4578 4579 struct mlx5_ifc_rts2rts_qp_in_bits { 4580 u8 opcode[0x10]; 4581 u8 uid[0x10]; 4582 4583 u8 reserved_at_20[0x10]; 4584 u8 op_mod[0x10]; 4585 4586 u8 reserved_at_40[0x8]; 4587 u8 qpn[0x18]; 4588 4589 u8 reserved_at_60[0x20]; 4590 4591 u8 opt_param_mask[0x20]; 4592 4593 u8 ece[0x20]; 4594 4595 struct mlx5_ifc_qpc_bits qpc; 4596 4597 u8 reserved_at_800[0x80]; 4598 }; 4599 4600 struct mlx5_ifc_rtr2rts_qp_out_bits { 4601 u8 status[0x8]; 4602 u8 reserved_at_8[0x18]; 4603 4604 u8 syndrome[0x20]; 4605 4606 u8 reserved_at_40[0x20]; 4607 u8 ece[0x20]; 4608 }; 4609 4610 struct mlx5_ifc_rtr2rts_qp_in_bits { 4611 u8 opcode[0x10]; 4612 u8 uid[0x10]; 4613 4614 u8 reserved_at_20[0x10]; 4615 u8 op_mod[0x10]; 4616 4617 u8 reserved_at_40[0x8]; 4618 u8 qpn[0x18]; 4619 4620 u8 reserved_at_60[0x20]; 4621 4622 u8 opt_param_mask[0x20]; 4623 4624 u8 ece[0x20]; 4625 4626 struct mlx5_ifc_qpc_bits qpc; 4627 4628 u8 reserved_at_800[0x80]; 4629 }; 4630 4631 struct mlx5_ifc_rst2init_qp_out_bits { 4632 u8 status[0x8]; 4633 u8 reserved_at_8[0x18]; 4634 4635 u8 syndrome[0x20]; 4636 4637 u8 reserved_at_40[0x20]; 4638 u8 ece[0x20]; 4639 }; 4640 4641 struct mlx5_ifc_rst2init_qp_in_bits { 4642 u8 opcode[0x10]; 4643 u8 uid[0x10]; 4644 4645 u8 reserved_at_20[0x10]; 4646 u8 op_mod[0x10]; 4647 4648 u8 reserved_at_40[0x8]; 4649 u8 qpn[0x18]; 4650 4651 u8 reserved_at_60[0x20]; 4652 4653 u8 opt_param_mask[0x20]; 4654 4655 u8 ece[0x20]; 4656 4657 struct mlx5_ifc_qpc_bits qpc; 4658 4659 u8 reserved_at_800[0x80]; 4660 }; 4661 4662 struct mlx5_ifc_query_xrq_out_bits { 4663 u8 status[0x8]; 4664 u8 reserved_at_8[0x18]; 4665 4666 u8 syndrome[0x20]; 4667 4668 u8 reserved_at_40[0x40]; 4669 4670 struct mlx5_ifc_xrqc_bits xrq_context; 4671 }; 4672 4673 struct mlx5_ifc_query_xrq_in_bits { 4674 u8 opcode[0x10]; 4675 u8 reserved_at_10[0x10]; 4676 4677 u8 reserved_at_20[0x10]; 4678 u8 op_mod[0x10]; 4679 4680 u8 reserved_at_40[0x8]; 4681 u8 xrqn[0x18]; 4682 4683 u8 reserved_at_60[0x20]; 4684 }; 4685 4686 struct mlx5_ifc_query_xrc_srq_out_bits { 4687 u8 status[0x8]; 4688 u8 reserved_at_8[0x18]; 4689 4690 u8 syndrome[0x20]; 4691 4692 u8 reserved_at_40[0x40]; 4693 4694 struct mlx5_ifc_xrc_srqc_bits xrc_srq_context_entry; 4695 4696 u8 reserved_at_280[0x600]; 4697 4698 u8 pas[][0x40]; 4699 }; 4700 4701 struct mlx5_ifc_query_xrc_srq_in_bits { 4702 u8 opcode[0x10]; 4703 u8 reserved_at_10[0x10]; 4704 4705 u8 reserved_at_20[0x10]; 4706 u8 op_mod[0x10]; 4707 4708 u8 reserved_at_40[0x8]; 4709 u8 xrc_srqn[0x18]; 4710 4711 u8 reserved_at_60[0x20]; 4712 }; 4713 4714 enum { 4715 MLX5_QUERY_VPORT_STATE_OUT_STATE_DOWN = 0x0, 4716 MLX5_QUERY_VPORT_STATE_OUT_STATE_UP = 0x1, 4717 }; 4718 4719 struct mlx5_ifc_query_vport_state_out_bits { 4720 u8 status[0x8]; 4721 u8 reserved_at_8[0x18]; 4722 4723 u8 syndrome[0x20]; 4724 4725 u8 reserved_at_40[0x20]; 4726 4727 u8 reserved_at_60[0x18]; 4728 u8 admin_state[0x4]; 4729 u8 state[0x4]; 4730 }; 4731 4732 enum { 4733 MLX5_VPORT_STATE_OP_MOD_VNIC_VPORT = 0x0, 4734 MLX5_VPORT_STATE_OP_MOD_ESW_VPORT = 0x1, 4735 MLX5_VPORT_STATE_OP_MOD_UPLINK = 0x2, 4736 }; 4737 4738 struct mlx5_ifc_arm_monitor_counter_in_bits { 4739 u8 opcode[0x10]; 4740 u8 uid[0x10]; 4741 4742 u8 reserved_at_20[0x10]; 4743 u8 op_mod[0x10]; 4744 4745 u8 reserved_at_40[0x20]; 4746 4747 u8 reserved_at_60[0x20]; 4748 }; 4749 4750 struct mlx5_ifc_arm_monitor_counter_out_bits { 4751 u8 status[0x8]; 4752 u8 reserved_at_8[0x18]; 4753 4754 u8 syndrome[0x20]; 4755 4756 u8 reserved_at_40[0x40]; 4757 }; 4758 4759 enum { 4760 MLX5_QUERY_MONITOR_CNT_TYPE_PPCNT = 0x0, 4761 MLX5_QUERY_MONITOR_CNT_TYPE_Q_COUNTER = 0x1, 4762 }; 4763 4764 enum mlx5_monitor_counter_ppcnt { 4765 MLX5_QUERY_MONITOR_PPCNT_IN_RANGE_LENGTH_ERRORS = 0x0, 4766 MLX5_QUERY_MONITOR_PPCNT_OUT_OF_RANGE_LENGTH_FIELD = 0x1, 4767 MLX5_QUERY_MONITOR_PPCNT_FRAME_TOO_LONG_ERRORS = 0x2, 4768 MLX5_QUERY_MONITOR_PPCNT_FRAME_CHECK_SEQUENCE_ERRORS = 0x3, 4769 MLX5_QUERY_MONITOR_PPCNT_ALIGNMENT_ERRORS = 0x4, 4770 MLX5_QUERY_MONITOR_PPCNT_IF_OUT_DISCARDS = 0x5, 4771 }; 4772 4773 enum { 4774 MLX5_QUERY_MONITOR_Q_COUNTER_RX_OUT_OF_BUFFER = 0x4, 4775 }; 4776 4777 struct mlx5_ifc_monitor_counter_output_bits { 4778 u8 reserved_at_0[0x4]; 4779 u8 type[0x4]; 4780 u8 reserved_at_8[0x8]; 4781 u8 counter[0x10]; 4782 4783 u8 counter_group_id[0x20]; 4784 }; 4785 4786 #define MLX5_CMD_SET_MONITOR_NUM_PPCNT_COUNTER_SET1 (6) 4787 #define MLX5_CMD_SET_MONITOR_NUM_Q_COUNTERS_SET1 (1) 4788 #define MLX5_CMD_SET_MONITOR_NUM_COUNTER (MLX5_CMD_SET_MONITOR_NUM_PPCNT_COUNTER_SET1 +\ 4789 MLX5_CMD_SET_MONITOR_NUM_Q_COUNTERS_SET1) 4790 4791 struct mlx5_ifc_set_monitor_counter_in_bits { 4792 u8 opcode[0x10]; 4793 u8 uid[0x10]; 4794 4795 u8 reserved_at_20[0x10]; 4796 u8 op_mod[0x10]; 4797 4798 u8 reserved_at_40[0x10]; 4799 u8 num_of_counters[0x10]; 4800 4801 u8 reserved_at_60[0x20]; 4802 4803 struct mlx5_ifc_monitor_counter_output_bits monitor_counter[MLX5_CMD_SET_MONITOR_NUM_COUNTER]; 4804 }; 4805 4806 struct mlx5_ifc_set_monitor_counter_out_bits { 4807 u8 status[0x8]; 4808 u8 reserved_at_8[0x18]; 4809 4810 u8 syndrome[0x20]; 4811 4812 u8 reserved_at_40[0x40]; 4813 }; 4814 4815 struct mlx5_ifc_query_vport_state_in_bits { 4816 u8 opcode[0x10]; 4817 u8 reserved_at_10[0x10]; 4818 4819 u8 reserved_at_20[0x10]; 4820 u8 op_mod[0x10]; 4821 4822 u8 other_vport[0x1]; 4823 u8 reserved_at_41[0xf]; 4824 u8 vport_number[0x10]; 4825 4826 u8 reserved_at_60[0x20]; 4827 }; 4828 4829 struct mlx5_ifc_query_vnic_env_out_bits { 4830 u8 status[0x8]; 4831 u8 reserved_at_8[0x18]; 4832 4833 u8 syndrome[0x20]; 4834 4835 u8 reserved_at_40[0x40]; 4836 4837 struct mlx5_ifc_vnic_diagnostic_statistics_bits vport_env; 4838 }; 4839 4840 enum { 4841 MLX5_QUERY_VNIC_ENV_IN_OP_MOD_VPORT_DIAG_STATISTICS = 0x0, 4842 }; 4843 4844 struct mlx5_ifc_query_vnic_env_in_bits { 4845 u8 opcode[0x10]; 4846 u8 reserved_at_10[0x10]; 4847 4848 u8 reserved_at_20[0x10]; 4849 u8 op_mod[0x10]; 4850 4851 u8 other_vport[0x1]; 4852 u8 reserved_at_41[0xf]; 4853 u8 vport_number[0x10]; 4854 4855 u8 reserved_at_60[0x20]; 4856 }; 4857 4858 struct mlx5_ifc_query_vport_counter_out_bits { 4859 u8 status[0x8]; 4860 u8 reserved_at_8[0x18]; 4861 4862 u8 syndrome[0x20]; 4863 4864 u8 reserved_at_40[0x40]; 4865 4866 struct mlx5_ifc_traffic_counter_bits received_errors; 4867 4868 struct mlx5_ifc_traffic_counter_bits transmit_errors; 4869 4870 struct mlx5_ifc_traffic_counter_bits received_ib_unicast; 4871 4872 struct mlx5_ifc_traffic_counter_bits transmitted_ib_unicast; 4873 4874 struct mlx5_ifc_traffic_counter_bits received_ib_multicast; 4875 4876 struct mlx5_ifc_traffic_counter_bits transmitted_ib_multicast; 4877 4878 struct mlx5_ifc_traffic_counter_bits received_eth_broadcast; 4879 4880 struct mlx5_ifc_traffic_counter_bits transmitted_eth_broadcast; 4881 4882 struct mlx5_ifc_traffic_counter_bits received_eth_unicast; 4883 4884 struct mlx5_ifc_traffic_counter_bits transmitted_eth_unicast; 4885 4886 struct mlx5_ifc_traffic_counter_bits received_eth_multicast; 4887 4888 struct mlx5_ifc_traffic_counter_bits transmitted_eth_multicast; 4889 4890 u8 reserved_at_680[0xa00]; 4891 }; 4892 4893 enum { 4894 MLX5_QUERY_VPORT_COUNTER_IN_OP_MOD_VPORT_COUNTERS = 0x0, 4895 }; 4896 4897 struct mlx5_ifc_query_vport_counter_in_bits { 4898 u8 opcode[0x10]; 4899 u8 reserved_at_10[0x10]; 4900 4901 u8 reserved_at_20[0x10]; 4902 u8 op_mod[0x10]; 4903 4904 u8 other_vport[0x1]; 4905 u8 reserved_at_41[0xb]; 4906 u8 port_num[0x4]; 4907 u8 vport_number[0x10]; 4908 4909 u8 reserved_at_60[0x60]; 4910 4911 u8 clear[0x1]; 4912 u8 reserved_at_c1[0x1f]; 4913 4914 u8 reserved_at_e0[0x20]; 4915 }; 4916 4917 struct mlx5_ifc_query_tis_out_bits { 4918 u8 status[0x8]; 4919 u8 reserved_at_8[0x18]; 4920 4921 u8 syndrome[0x20]; 4922 4923 u8 reserved_at_40[0x40]; 4924 4925 struct mlx5_ifc_tisc_bits tis_context; 4926 }; 4927 4928 struct mlx5_ifc_query_tis_in_bits { 4929 u8 opcode[0x10]; 4930 u8 reserved_at_10[0x10]; 4931 4932 u8 reserved_at_20[0x10]; 4933 u8 op_mod[0x10]; 4934 4935 u8 reserved_at_40[0x8]; 4936 u8 tisn[0x18]; 4937 4938 u8 reserved_at_60[0x20]; 4939 }; 4940 4941 struct mlx5_ifc_query_tir_out_bits { 4942 u8 status[0x8]; 4943 u8 reserved_at_8[0x18]; 4944 4945 u8 syndrome[0x20]; 4946 4947 u8 reserved_at_40[0xc0]; 4948 4949 struct mlx5_ifc_tirc_bits tir_context; 4950 }; 4951 4952 struct mlx5_ifc_query_tir_in_bits { 4953 u8 opcode[0x10]; 4954 u8 reserved_at_10[0x10]; 4955 4956 u8 reserved_at_20[0x10]; 4957 u8 op_mod[0x10]; 4958 4959 u8 reserved_at_40[0x8]; 4960 u8 tirn[0x18]; 4961 4962 u8 reserved_at_60[0x20]; 4963 }; 4964 4965 struct mlx5_ifc_query_srq_out_bits { 4966 u8 status[0x8]; 4967 u8 reserved_at_8[0x18]; 4968 4969 u8 syndrome[0x20]; 4970 4971 u8 reserved_at_40[0x40]; 4972 4973 struct mlx5_ifc_srqc_bits srq_context_entry; 4974 4975 u8 reserved_at_280[0x600]; 4976 4977 u8 pas[][0x40]; 4978 }; 4979 4980 struct mlx5_ifc_query_srq_in_bits { 4981 u8 opcode[0x10]; 4982 u8 reserved_at_10[0x10]; 4983 4984 u8 reserved_at_20[0x10]; 4985 u8 op_mod[0x10]; 4986 4987 u8 reserved_at_40[0x8]; 4988 u8 srqn[0x18]; 4989 4990 u8 reserved_at_60[0x20]; 4991 }; 4992 4993 struct mlx5_ifc_query_sq_out_bits { 4994 u8 status[0x8]; 4995 u8 reserved_at_8[0x18]; 4996 4997 u8 syndrome[0x20]; 4998 4999 u8 reserved_at_40[0xc0]; 5000 5001 struct mlx5_ifc_sqc_bits sq_context; 5002 }; 5003 5004 struct mlx5_ifc_query_sq_in_bits { 5005 u8 opcode[0x10]; 5006 u8 reserved_at_10[0x10]; 5007 5008 u8 reserved_at_20[0x10]; 5009 u8 op_mod[0x10]; 5010 5011 u8 reserved_at_40[0x8]; 5012 u8 sqn[0x18]; 5013 5014 u8 reserved_at_60[0x20]; 5015 }; 5016 5017 struct mlx5_ifc_query_special_contexts_out_bits { 5018 u8 status[0x8]; 5019 u8 reserved_at_8[0x18]; 5020 5021 u8 syndrome[0x20]; 5022 5023 u8 dump_fill_mkey[0x20]; 5024 5025 u8 resd_lkey[0x20]; 5026 5027 u8 null_mkey[0x20]; 5028 5029 u8 reserved_at_a0[0x60]; 5030 }; 5031 5032 struct mlx5_ifc_query_special_contexts_in_bits { 5033 u8 opcode[0x10]; 5034 u8 reserved_at_10[0x10]; 5035 5036 u8 reserved_at_20[0x10]; 5037 u8 op_mod[0x10]; 5038 5039 u8 reserved_at_40[0x40]; 5040 }; 5041 5042 struct mlx5_ifc_query_scheduling_element_out_bits { 5043 u8 opcode[0x10]; 5044 u8 reserved_at_10[0x10]; 5045 5046 u8 reserved_at_20[0x10]; 5047 u8 op_mod[0x10]; 5048 5049 u8 reserved_at_40[0xc0]; 5050 5051 struct mlx5_ifc_scheduling_context_bits scheduling_context; 5052 5053 u8 reserved_at_300[0x100]; 5054 }; 5055 5056 enum { 5057 SCHEDULING_HIERARCHY_E_SWITCH = 0x2, 5058 SCHEDULING_HIERARCHY_NIC = 0x3, 5059 }; 5060 5061 struct mlx5_ifc_query_scheduling_element_in_bits { 5062 u8 opcode[0x10]; 5063 u8 reserved_at_10[0x10]; 5064 5065 u8 reserved_at_20[0x10]; 5066 u8 op_mod[0x10]; 5067 5068 u8 scheduling_hierarchy[0x8]; 5069 u8 reserved_at_48[0x18]; 5070 5071 u8 scheduling_element_id[0x20]; 5072 5073 u8 reserved_at_80[0x180]; 5074 }; 5075 5076 struct mlx5_ifc_query_rqt_out_bits { 5077 u8 status[0x8]; 5078 u8 reserved_at_8[0x18]; 5079 5080 u8 syndrome[0x20]; 5081 5082 u8 reserved_at_40[0xc0]; 5083 5084 struct mlx5_ifc_rqtc_bits rqt_context; 5085 }; 5086 5087 struct mlx5_ifc_query_rqt_in_bits { 5088 u8 opcode[0x10]; 5089 u8 reserved_at_10[0x10]; 5090 5091 u8 reserved_at_20[0x10]; 5092 u8 op_mod[0x10]; 5093 5094 u8 reserved_at_40[0x8]; 5095 u8 rqtn[0x18]; 5096 5097 u8 reserved_at_60[0x20]; 5098 }; 5099 5100 struct mlx5_ifc_query_rq_out_bits { 5101 u8 status[0x8]; 5102 u8 reserved_at_8[0x18]; 5103 5104 u8 syndrome[0x20]; 5105 5106 u8 reserved_at_40[0xc0]; 5107 5108 struct mlx5_ifc_rqc_bits rq_context; 5109 }; 5110 5111 struct mlx5_ifc_query_rq_in_bits { 5112 u8 opcode[0x10]; 5113 u8 reserved_at_10[0x10]; 5114 5115 u8 reserved_at_20[0x10]; 5116 u8 op_mod[0x10]; 5117 5118 u8 reserved_at_40[0x8]; 5119 u8 rqn[0x18]; 5120 5121 u8 reserved_at_60[0x20]; 5122 }; 5123 5124 struct mlx5_ifc_query_roce_address_out_bits { 5125 u8 status[0x8]; 5126 u8 reserved_at_8[0x18]; 5127 5128 u8 syndrome[0x20]; 5129 5130 u8 reserved_at_40[0x40]; 5131 5132 struct mlx5_ifc_roce_addr_layout_bits roce_address; 5133 }; 5134 5135 struct mlx5_ifc_query_roce_address_in_bits { 5136 u8 opcode[0x10]; 5137 u8 reserved_at_10[0x10]; 5138 5139 u8 reserved_at_20[0x10]; 5140 u8 op_mod[0x10]; 5141 5142 u8 roce_address_index[0x10]; 5143 u8 reserved_at_50[0xc]; 5144 u8 vhca_port_num[0x4]; 5145 5146 u8 reserved_at_60[0x20]; 5147 }; 5148 5149 struct mlx5_ifc_query_rmp_out_bits { 5150 u8 status[0x8]; 5151 u8 reserved_at_8[0x18]; 5152 5153 u8 syndrome[0x20]; 5154 5155 u8 reserved_at_40[0xc0]; 5156 5157 struct mlx5_ifc_rmpc_bits rmp_context; 5158 }; 5159 5160 struct mlx5_ifc_query_rmp_in_bits { 5161 u8 opcode[0x10]; 5162 u8 reserved_at_10[0x10]; 5163 5164 u8 reserved_at_20[0x10]; 5165 u8 op_mod[0x10]; 5166 5167 u8 reserved_at_40[0x8]; 5168 u8 rmpn[0x18]; 5169 5170 u8 reserved_at_60[0x20]; 5171 }; 5172 5173 struct mlx5_ifc_query_qp_out_bits { 5174 u8 status[0x8]; 5175 u8 reserved_at_8[0x18]; 5176 5177 u8 syndrome[0x20]; 5178 5179 u8 reserved_at_40[0x40]; 5180 5181 u8 opt_param_mask[0x20]; 5182 5183 u8 ece[0x20]; 5184 5185 struct mlx5_ifc_qpc_bits qpc; 5186 5187 u8 reserved_at_800[0x80]; 5188 5189 u8 pas[][0x40]; 5190 }; 5191 5192 struct mlx5_ifc_query_qp_in_bits { 5193 u8 opcode[0x10]; 5194 u8 reserved_at_10[0x10]; 5195 5196 u8 reserved_at_20[0x10]; 5197 u8 op_mod[0x10]; 5198 5199 u8 reserved_at_40[0x8]; 5200 u8 qpn[0x18]; 5201 5202 u8 reserved_at_60[0x20]; 5203 }; 5204 5205 struct mlx5_ifc_query_q_counter_out_bits { 5206 u8 status[0x8]; 5207 u8 reserved_at_8[0x18]; 5208 5209 u8 syndrome[0x20]; 5210 5211 u8 reserved_at_40[0x40]; 5212 5213 u8 rx_write_requests[0x20]; 5214 5215 u8 reserved_at_a0[0x20]; 5216 5217 u8 rx_read_requests[0x20]; 5218 5219 u8 reserved_at_e0[0x20]; 5220 5221 u8 rx_atomic_requests[0x20]; 5222 5223 u8 reserved_at_120[0x20]; 5224 5225 u8 rx_dct_connect[0x20]; 5226 5227 u8 reserved_at_160[0x20]; 5228 5229 u8 out_of_buffer[0x20]; 5230 5231 u8 reserved_at_1a0[0x20]; 5232 5233 u8 out_of_sequence[0x20]; 5234 5235 u8 reserved_at_1e0[0x20]; 5236 5237 u8 duplicate_request[0x20]; 5238 5239 u8 reserved_at_220[0x20]; 5240 5241 u8 rnr_nak_retry_err[0x20]; 5242 5243 u8 reserved_at_260[0x20]; 5244 5245 u8 packet_seq_err[0x20]; 5246 5247 u8 reserved_at_2a0[0x20]; 5248 5249 u8 implied_nak_seq_err[0x20]; 5250 5251 u8 reserved_at_2e0[0x20]; 5252 5253 u8 local_ack_timeout_err[0x20]; 5254 5255 u8 reserved_at_320[0xa0]; 5256 5257 u8 resp_local_length_error[0x20]; 5258 5259 u8 req_local_length_error[0x20]; 5260 5261 u8 resp_local_qp_error[0x20]; 5262 5263 u8 local_operation_error[0x20]; 5264 5265 u8 resp_local_protection[0x20]; 5266 5267 u8 req_local_protection[0x20]; 5268 5269 u8 resp_cqe_error[0x20]; 5270 5271 u8 req_cqe_error[0x20]; 5272 5273 u8 req_mw_binding[0x20]; 5274 5275 u8 req_bad_response[0x20]; 5276 5277 u8 req_remote_invalid_request[0x20]; 5278 5279 u8 resp_remote_invalid_request[0x20]; 5280 5281 u8 req_remote_access_errors[0x20]; 5282 5283 u8 resp_remote_access_errors[0x20]; 5284 5285 u8 req_remote_operation_errors[0x20]; 5286 5287 u8 req_transport_retries_exceeded[0x20]; 5288 5289 u8 cq_overflow[0x20]; 5290 5291 u8 resp_cqe_flush_error[0x20]; 5292 5293 u8 req_cqe_flush_error[0x20]; 5294 5295 u8 reserved_at_620[0x20]; 5296 5297 u8 roce_adp_retrans[0x20]; 5298 5299 u8 roce_adp_retrans_to[0x20]; 5300 5301 u8 roce_slow_restart[0x20]; 5302 5303 u8 roce_slow_restart_cnps[0x20]; 5304 5305 u8 roce_slow_restart_trans[0x20]; 5306 5307 u8 reserved_at_6e0[0x120]; 5308 }; 5309 5310 struct mlx5_ifc_query_q_counter_in_bits { 5311 u8 opcode[0x10]; 5312 u8 reserved_at_10[0x10]; 5313 5314 u8 reserved_at_20[0x10]; 5315 u8 op_mod[0x10]; 5316 5317 u8 reserved_at_40[0x80]; 5318 5319 u8 clear[0x1]; 5320 u8 reserved_at_c1[0x1f]; 5321 5322 u8 reserved_at_e0[0x18]; 5323 u8 counter_set_id[0x8]; 5324 }; 5325 5326 struct mlx5_ifc_query_pages_out_bits { 5327 u8 status[0x8]; 5328 u8 reserved_at_8[0x18]; 5329 5330 u8 syndrome[0x20]; 5331 5332 u8 embedded_cpu_function[0x1]; 5333 u8 reserved_at_41[0xf]; 5334 u8 function_id[0x10]; 5335 5336 u8 num_pages[0x20]; 5337 }; 5338 5339 enum { 5340 MLX5_QUERY_PAGES_IN_OP_MOD_BOOT_PAGES = 0x1, 5341 MLX5_QUERY_PAGES_IN_OP_MOD_INIT_PAGES = 0x2, 5342 MLX5_QUERY_PAGES_IN_OP_MOD_REGULAR_PAGES = 0x3, 5343 }; 5344 5345 struct mlx5_ifc_query_pages_in_bits { 5346 u8 opcode[0x10]; 5347 u8 reserved_at_10[0x10]; 5348 5349 u8 reserved_at_20[0x10]; 5350 u8 op_mod[0x10]; 5351 5352 u8 embedded_cpu_function[0x1]; 5353 u8 reserved_at_41[0xf]; 5354 u8 function_id[0x10]; 5355 5356 u8 reserved_at_60[0x20]; 5357 }; 5358 5359 struct mlx5_ifc_query_nic_vport_context_out_bits { 5360 u8 status[0x8]; 5361 u8 reserved_at_8[0x18]; 5362 5363 u8 syndrome[0x20]; 5364 5365 u8 reserved_at_40[0x40]; 5366 5367 struct mlx5_ifc_nic_vport_context_bits nic_vport_context; 5368 }; 5369 5370 struct mlx5_ifc_query_nic_vport_context_in_bits { 5371 u8 opcode[0x10]; 5372 u8 reserved_at_10[0x10]; 5373 5374 u8 reserved_at_20[0x10]; 5375 u8 op_mod[0x10]; 5376 5377 u8 other_vport[0x1]; 5378 u8 reserved_at_41[0xf]; 5379 u8 vport_number[0x10]; 5380 5381 u8 reserved_at_60[0x5]; 5382 u8 allowed_list_type[0x3]; 5383 u8 reserved_at_68[0x18]; 5384 }; 5385 5386 struct mlx5_ifc_query_mkey_out_bits { 5387 u8 status[0x8]; 5388 u8 reserved_at_8[0x18]; 5389 5390 u8 syndrome[0x20]; 5391 5392 u8 reserved_at_40[0x40]; 5393 5394 struct mlx5_ifc_mkc_bits memory_key_mkey_entry; 5395 5396 u8 reserved_at_280[0x600]; 5397 5398 u8 bsf0_klm0_pas_mtt0_1[16][0x8]; 5399 5400 u8 bsf1_klm1_pas_mtt2_3[16][0x8]; 5401 }; 5402 5403 struct mlx5_ifc_query_mkey_in_bits { 5404 u8 opcode[0x10]; 5405 u8 reserved_at_10[0x10]; 5406 5407 u8 reserved_at_20[0x10]; 5408 u8 op_mod[0x10]; 5409 5410 u8 reserved_at_40[0x8]; 5411 u8 mkey_index[0x18]; 5412 5413 u8 pg_access[0x1]; 5414 u8 reserved_at_61[0x1f]; 5415 }; 5416 5417 struct mlx5_ifc_query_mad_demux_out_bits { 5418 u8 status[0x8]; 5419 u8 reserved_at_8[0x18]; 5420 5421 u8 syndrome[0x20]; 5422 5423 u8 reserved_at_40[0x40]; 5424 5425 u8 mad_dumux_parameters_block[0x20]; 5426 }; 5427 5428 struct mlx5_ifc_query_mad_demux_in_bits { 5429 u8 opcode[0x10]; 5430 u8 reserved_at_10[0x10]; 5431 5432 u8 reserved_at_20[0x10]; 5433 u8 op_mod[0x10]; 5434 5435 u8 reserved_at_40[0x40]; 5436 }; 5437 5438 struct mlx5_ifc_query_l2_table_entry_out_bits { 5439 u8 status[0x8]; 5440 u8 reserved_at_8[0x18]; 5441 5442 u8 syndrome[0x20]; 5443 5444 u8 reserved_at_40[0xa0]; 5445 5446 u8 reserved_at_e0[0x13]; 5447 u8 vlan_valid[0x1]; 5448 u8 vlan[0xc]; 5449 5450 struct mlx5_ifc_mac_address_layout_bits mac_address; 5451 5452 u8 reserved_at_140[0xc0]; 5453 }; 5454 5455 struct mlx5_ifc_query_l2_table_entry_in_bits { 5456 u8 opcode[0x10]; 5457 u8 reserved_at_10[0x10]; 5458 5459 u8 reserved_at_20[0x10]; 5460 u8 op_mod[0x10]; 5461 5462 u8 reserved_at_40[0x60]; 5463 5464 u8 reserved_at_a0[0x8]; 5465 u8 table_index[0x18]; 5466 5467 u8 reserved_at_c0[0x140]; 5468 }; 5469 5470 struct mlx5_ifc_query_issi_out_bits { 5471 u8 status[0x8]; 5472 u8 reserved_at_8[0x18]; 5473 5474 u8 syndrome[0x20]; 5475 5476 u8 reserved_at_40[0x10]; 5477 u8 current_issi[0x10]; 5478 5479 u8 reserved_at_60[0xa0]; 5480 5481 u8 reserved_at_100[76][0x8]; 5482 u8 supported_issi_dw0[0x20]; 5483 }; 5484 5485 struct mlx5_ifc_query_issi_in_bits { 5486 u8 opcode[0x10]; 5487 u8 reserved_at_10[0x10]; 5488 5489 u8 reserved_at_20[0x10]; 5490 u8 op_mod[0x10]; 5491 5492 u8 reserved_at_40[0x40]; 5493 }; 5494 5495 struct mlx5_ifc_set_driver_version_out_bits { 5496 u8 status[0x8]; 5497 u8 reserved_0[0x18]; 5498 5499 u8 syndrome[0x20]; 5500 u8 reserved_1[0x40]; 5501 }; 5502 5503 struct mlx5_ifc_set_driver_version_in_bits { 5504 u8 opcode[0x10]; 5505 u8 reserved_0[0x10]; 5506 5507 u8 reserved_1[0x10]; 5508 u8 op_mod[0x10]; 5509 5510 u8 reserved_2[0x40]; 5511 u8 driver_version[64][0x8]; 5512 }; 5513 5514 struct mlx5_ifc_query_hca_vport_pkey_out_bits { 5515 u8 status[0x8]; 5516 u8 reserved_at_8[0x18]; 5517 5518 u8 syndrome[0x20]; 5519 5520 u8 reserved_at_40[0x40]; 5521 5522 struct mlx5_ifc_pkey_bits pkey[]; 5523 }; 5524 5525 struct mlx5_ifc_query_hca_vport_pkey_in_bits { 5526 u8 opcode[0x10]; 5527 u8 reserved_at_10[0x10]; 5528 5529 u8 reserved_at_20[0x10]; 5530 u8 op_mod[0x10]; 5531 5532 u8 other_vport[0x1]; 5533 u8 reserved_at_41[0xb]; 5534 u8 port_num[0x4]; 5535 u8 vport_number[0x10]; 5536 5537 u8 reserved_at_60[0x10]; 5538 u8 pkey_index[0x10]; 5539 }; 5540 5541 enum { 5542 MLX5_HCA_VPORT_SEL_PORT_GUID = 1 << 0, 5543 MLX5_HCA_VPORT_SEL_NODE_GUID = 1 << 1, 5544 MLX5_HCA_VPORT_SEL_STATE_POLICY = 1 << 2, 5545 }; 5546 5547 struct mlx5_ifc_query_hca_vport_gid_out_bits { 5548 u8 status[0x8]; 5549 u8 reserved_at_8[0x18]; 5550 5551 u8 syndrome[0x20]; 5552 5553 u8 reserved_at_40[0x20]; 5554 5555 u8 gids_num[0x10]; 5556 u8 reserved_at_70[0x10]; 5557 5558 struct mlx5_ifc_array128_auto_bits gid[]; 5559 }; 5560 5561 struct mlx5_ifc_query_hca_vport_gid_in_bits { 5562 u8 opcode[0x10]; 5563 u8 reserved_at_10[0x10]; 5564 5565 u8 reserved_at_20[0x10]; 5566 u8 op_mod[0x10]; 5567 5568 u8 other_vport[0x1]; 5569 u8 reserved_at_41[0xb]; 5570 u8 port_num[0x4]; 5571 u8 vport_number[0x10]; 5572 5573 u8 reserved_at_60[0x10]; 5574 u8 gid_index[0x10]; 5575 }; 5576 5577 struct mlx5_ifc_query_hca_vport_context_out_bits { 5578 u8 status[0x8]; 5579 u8 reserved_at_8[0x18]; 5580 5581 u8 syndrome[0x20]; 5582 5583 u8 reserved_at_40[0x40]; 5584 5585 struct mlx5_ifc_hca_vport_context_bits hca_vport_context; 5586 }; 5587 5588 struct mlx5_ifc_query_hca_vport_context_in_bits { 5589 u8 opcode[0x10]; 5590 u8 reserved_at_10[0x10]; 5591 5592 u8 reserved_at_20[0x10]; 5593 u8 op_mod[0x10]; 5594 5595 u8 other_vport[0x1]; 5596 u8 reserved_at_41[0xb]; 5597 u8 port_num[0x4]; 5598 u8 vport_number[0x10]; 5599 5600 u8 reserved_at_60[0x20]; 5601 }; 5602 5603 struct mlx5_ifc_query_hca_cap_out_bits { 5604 u8 status[0x8]; 5605 u8 reserved_at_8[0x18]; 5606 5607 u8 syndrome[0x20]; 5608 5609 u8 reserved_at_40[0x40]; 5610 5611 union mlx5_ifc_hca_cap_union_bits capability; 5612 }; 5613 5614 struct mlx5_ifc_query_hca_cap_in_bits { 5615 u8 opcode[0x10]; 5616 u8 reserved_at_10[0x10]; 5617 5618 u8 reserved_at_20[0x10]; 5619 u8 op_mod[0x10]; 5620 5621 u8 other_function[0x1]; 5622 u8 reserved_at_41[0xf]; 5623 u8 function_id[0x10]; 5624 5625 u8 reserved_at_60[0x20]; 5626 }; 5627 5628 struct mlx5_ifc_other_hca_cap_bits { 5629 u8 roce[0x1]; 5630 u8 reserved_at_1[0x27f]; 5631 }; 5632 5633 struct mlx5_ifc_query_other_hca_cap_out_bits { 5634 u8 status[0x8]; 5635 u8 reserved_at_8[0x18]; 5636 5637 u8 syndrome[0x20]; 5638 5639 u8 reserved_at_40[0x40]; 5640 5641 struct mlx5_ifc_other_hca_cap_bits other_capability; 5642 }; 5643 5644 struct mlx5_ifc_query_other_hca_cap_in_bits { 5645 u8 opcode[0x10]; 5646 u8 reserved_at_10[0x10]; 5647 5648 u8 reserved_at_20[0x10]; 5649 u8 op_mod[0x10]; 5650 5651 u8 reserved_at_40[0x10]; 5652 u8 function_id[0x10]; 5653 5654 u8 reserved_at_60[0x20]; 5655 }; 5656 5657 struct mlx5_ifc_modify_other_hca_cap_out_bits { 5658 u8 status[0x8]; 5659 u8 reserved_at_8[0x18]; 5660 5661 u8 syndrome[0x20]; 5662 5663 u8 reserved_at_40[0x40]; 5664 }; 5665 5666 struct mlx5_ifc_modify_other_hca_cap_in_bits { 5667 u8 opcode[0x10]; 5668 u8 reserved_at_10[0x10]; 5669 5670 u8 reserved_at_20[0x10]; 5671 u8 op_mod[0x10]; 5672 5673 u8 reserved_at_40[0x10]; 5674 u8 function_id[0x10]; 5675 u8 field_select[0x20]; 5676 5677 struct mlx5_ifc_other_hca_cap_bits other_capability; 5678 }; 5679 5680 struct mlx5_ifc_flow_table_context_bits { 5681 u8 reformat_en[0x1]; 5682 u8 decap_en[0x1]; 5683 u8 sw_owner[0x1]; 5684 u8 termination_table[0x1]; 5685 u8 table_miss_action[0x4]; 5686 u8 level[0x8]; 5687 u8 reserved_at_10[0x8]; 5688 u8 log_size[0x8]; 5689 5690 u8 reserved_at_20[0x8]; 5691 u8 table_miss_id[0x18]; 5692 5693 u8 reserved_at_40[0x8]; 5694 u8 lag_master_next_table_id[0x18]; 5695 5696 u8 reserved_at_60[0x60]; 5697 5698 u8 sw_owner_icm_root_1[0x40]; 5699 5700 u8 sw_owner_icm_root_0[0x40]; 5701 5702 }; 5703 5704 struct mlx5_ifc_query_flow_table_out_bits { 5705 u8 status[0x8]; 5706 u8 reserved_at_8[0x18]; 5707 5708 u8 syndrome[0x20]; 5709 5710 u8 reserved_at_40[0x80]; 5711 5712 struct mlx5_ifc_flow_table_context_bits flow_table_context; 5713 }; 5714 5715 struct mlx5_ifc_query_flow_table_in_bits { 5716 u8 opcode[0x10]; 5717 u8 reserved_at_10[0x10]; 5718 5719 u8 reserved_at_20[0x10]; 5720 u8 op_mod[0x10]; 5721 5722 u8 reserved_at_40[0x40]; 5723 5724 u8 table_type[0x8]; 5725 u8 reserved_at_88[0x18]; 5726 5727 u8 reserved_at_a0[0x8]; 5728 u8 table_id[0x18]; 5729 5730 u8 reserved_at_c0[0x140]; 5731 }; 5732 5733 struct mlx5_ifc_query_fte_out_bits { 5734 u8 status[0x8]; 5735 u8 reserved_at_8[0x18]; 5736 5737 u8 syndrome[0x20]; 5738 5739 u8 reserved_at_40[0x1c0]; 5740 5741 struct mlx5_ifc_flow_context_bits flow_context; 5742 }; 5743 5744 struct mlx5_ifc_query_fte_in_bits { 5745 u8 opcode[0x10]; 5746 u8 reserved_at_10[0x10]; 5747 5748 u8 reserved_at_20[0x10]; 5749 u8 op_mod[0x10]; 5750 5751 u8 reserved_at_40[0x40]; 5752 5753 u8 table_type[0x8]; 5754 u8 reserved_at_88[0x18]; 5755 5756 u8 reserved_at_a0[0x8]; 5757 u8 table_id[0x18]; 5758 5759 u8 reserved_at_c0[0x40]; 5760 5761 u8 flow_index[0x20]; 5762 5763 u8 reserved_at_120[0xe0]; 5764 }; 5765 5766 struct mlx5_ifc_match_definer_format_0_bits { 5767 u8 reserved_at_0[0x100]; 5768 5769 u8 metadata_reg_c_0[0x20]; 5770 5771 u8 metadata_reg_c_1[0x20]; 5772 5773 u8 outer_dmac_47_16[0x20]; 5774 5775 u8 outer_dmac_15_0[0x10]; 5776 u8 outer_ethertype[0x10]; 5777 5778 u8 reserved_at_180[0x1]; 5779 u8 sx_sniffer[0x1]; 5780 u8 functional_lb[0x1]; 5781 u8 outer_ip_frag[0x1]; 5782 u8 outer_qp_type[0x2]; 5783 u8 outer_encap_type[0x2]; 5784 u8 port_number[0x2]; 5785 u8 outer_l3_type[0x2]; 5786 u8 outer_l4_type[0x2]; 5787 u8 outer_first_vlan_type[0x2]; 5788 u8 outer_first_vlan_prio[0x3]; 5789 u8 outer_first_vlan_cfi[0x1]; 5790 u8 outer_first_vlan_vid[0xc]; 5791 5792 u8 outer_l4_type_ext[0x4]; 5793 u8 reserved_at_1a4[0x2]; 5794 u8 outer_ipsec_layer[0x2]; 5795 u8 outer_l2_type[0x2]; 5796 u8 force_lb[0x1]; 5797 u8 outer_l2_ok[0x1]; 5798 u8 outer_l3_ok[0x1]; 5799 u8 outer_l4_ok[0x1]; 5800 u8 outer_second_vlan_type[0x2]; 5801 u8 outer_second_vlan_prio[0x3]; 5802 u8 outer_second_vlan_cfi[0x1]; 5803 u8 outer_second_vlan_vid[0xc]; 5804 5805 u8 outer_smac_47_16[0x20]; 5806 5807 u8 outer_smac_15_0[0x10]; 5808 u8 inner_ipv4_checksum_ok[0x1]; 5809 u8 inner_l4_checksum_ok[0x1]; 5810 u8 outer_ipv4_checksum_ok[0x1]; 5811 u8 outer_l4_checksum_ok[0x1]; 5812 u8 inner_l3_ok[0x1]; 5813 u8 inner_l4_ok[0x1]; 5814 u8 outer_l3_ok_duplicate[0x1]; 5815 u8 outer_l4_ok_duplicate[0x1]; 5816 u8 outer_tcp_cwr[0x1]; 5817 u8 outer_tcp_ece[0x1]; 5818 u8 outer_tcp_urg[0x1]; 5819 u8 outer_tcp_ack[0x1]; 5820 u8 outer_tcp_psh[0x1]; 5821 u8 outer_tcp_rst[0x1]; 5822 u8 outer_tcp_syn[0x1]; 5823 u8 outer_tcp_fin[0x1]; 5824 }; 5825 5826 struct mlx5_ifc_match_definer_format_22_bits { 5827 u8 reserved_at_0[0x100]; 5828 5829 u8 outer_ip_src_addr[0x20]; 5830 5831 u8 outer_ip_dest_addr[0x20]; 5832 5833 u8 outer_l4_sport[0x10]; 5834 u8 outer_l4_dport[0x10]; 5835 5836 u8 reserved_at_160[0x1]; 5837 u8 sx_sniffer[0x1]; 5838 u8 functional_lb[0x1]; 5839 u8 outer_ip_frag[0x1]; 5840 u8 outer_qp_type[0x2]; 5841 u8 outer_encap_type[0x2]; 5842 u8 port_number[0x2]; 5843 u8 outer_l3_type[0x2]; 5844 u8 outer_l4_type[0x2]; 5845 u8 outer_first_vlan_type[0x2]; 5846 u8 outer_first_vlan_prio[0x3]; 5847 u8 outer_first_vlan_cfi[0x1]; 5848 u8 outer_first_vlan_vid[0xc]; 5849 5850 u8 metadata_reg_c_0[0x20]; 5851 5852 u8 outer_dmac_47_16[0x20]; 5853 5854 u8 outer_smac_47_16[0x20]; 5855 5856 u8 outer_smac_15_0[0x10]; 5857 u8 outer_dmac_15_0[0x10]; 5858 }; 5859 5860 struct mlx5_ifc_match_definer_format_23_bits { 5861 u8 reserved_at_0[0x100]; 5862 5863 u8 inner_ip_src_addr[0x20]; 5864 5865 u8 inner_ip_dest_addr[0x20]; 5866 5867 u8 inner_l4_sport[0x10]; 5868 u8 inner_l4_dport[0x10]; 5869 5870 u8 reserved_at_160[0x1]; 5871 u8 sx_sniffer[0x1]; 5872 u8 functional_lb[0x1]; 5873 u8 inner_ip_frag[0x1]; 5874 u8 inner_qp_type[0x2]; 5875 u8 inner_encap_type[0x2]; 5876 u8 port_number[0x2]; 5877 u8 inner_l3_type[0x2]; 5878 u8 inner_l4_type[0x2]; 5879 u8 inner_first_vlan_type[0x2]; 5880 u8 inner_first_vlan_prio[0x3]; 5881 u8 inner_first_vlan_cfi[0x1]; 5882 u8 inner_first_vlan_vid[0xc]; 5883 5884 u8 tunnel_header_0[0x20]; 5885 5886 u8 inner_dmac_47_16[0x20]; 5887 5888 u8 inner_smac_47_16[0x20]; 5889 5890 u8 inner_smac_15_0[0x10]; 5891 u8 inner_dmac_15_0[0x10]; 5892 }; 5893 5894 struct mlx5_ifc_match_definer_format_29_bits { 5895 u8 reserved_at_0[0xc0]; 5896 5897 u8 outer_ip_dest_addr[0x80]; 5898 5899 u8 outer_ip_src_addr[0x80]; 5900 5901 u8 outer_l4_sport[0x10]; 5902 u8 outer_l4_dport[0x10]; 5903 5904 u8 reserved_at_1e0[0x20]; 5905 }; 5906 5907 struct mlx5_ifc_match_definer_format_30_bits { 5908 u8 reserved_at_0[0xa0]; 5909 5910 u8 outer_ip_dest_addr[0x80]; 5911 5912 u8 outer_ip_src_addr[0x80]; 5913 5914 u8 outer_dmac_47_16[0x20]; 5915 5916 u8 outer_smac_47_16[0x20]; 5917 5918 u8 outer_smac_15_0[0x10]; 5919 u8 outer_dmac_15_0[0x10]; 5920 }; 5921 5922 struct mlx5_ifc_match_definer_format_31_bits { 5923 u8 reserved_at_0[0xc0]; 5924 5925 u8 inner_ip_dest_addr[0x80]; 5926 5927 u8 inner_ip_src_addr[0x80]; 5928 5929 u8 inner_l4_sport[0x10]; 5930 u8 inner_l4_dport[0x10]; 5931 5932 u8 reserved_at_1e0[0x20]; 5933 }; 5934 5935 struct mlx5_ifc_match_definer_format_32_bits { 5936 u8 reserved_at_0[0xa0]; 5937 5938 u8 inner_ip_dest_addr[0x80]; 5939 5940 u8 inner_ip_src_addr[0x80]; 5941 5942 u8 inner_dmac_47_16[0x20]; 5943 5944 u8 inner_smac_47_16[0x20]; 5945 5946 u8 inner_smac_15_0[0x10]; 5947 u8 inner_dmac_15_0[0x10]; 5948 }; 5949 5950 struct mlx5_ifc_match_definer_bits { 5951 u8 modify_field_select[0x40]; 5952 5953 u8 reserved_at_40[0x40]; 5954 5955 u8 reserved_at_80[0x10]; 5956 u8 format_id[0x10]; 5957 5958 u8 reserved_at_a0[0x160]; 5959 5960 u8 match_mask[16][0x20]; 5961 }; 5962 5963 struct mlx5_ifc_general_obj_in_cmd_hdr_bits { 5964 u8 opcode[0x10]; 5965 u8 uid[0x10]; 5966 5967 u8 vhca_tunnel_id[0x10]; 5968 u8 obj_type[0x10]; 5969 5970 u8 obj_id[0x20]; 5971 5972 u8 reserved_at_60[0x20]; 5973 }; 5974 5975 struct mlx5_ifc_general_obj_out_cmd_hdr_bits { 5976 u8 status[0x8]; 5977 u8 reserved_at_8[0x18]; 5978 5979 u8 syndrome[0x20]; 5980 5981 u8 obj_id[0x20]; 5982 5983 u8 reserved_at_60[0x20]; 5984 }; 5985 5986 struct mlx5_ifc_create_match_definer_in_bits { 5987 struct mlx5_ifc_general_obj_in_cmd_hdr_bits general_obj_in_cmd_hdr; 5988 5989 struct mlx5_ifc_match_definer_bits obj_context; 5990 }; 5991 5992 struct mlx5_ifc_create_match_definer_out_bits { 5993 struct mlx5_ifc_general_obj_out_cmd_hdr_bits general_obj_out_cmd_hdr; 5994 }; 5995 5996 enum { 5997 MLX5_QUERY_FLOW_GROUP_OUT_MATCH_CRITERIA_ENABLE_OUTER_HEADERS = 0x0, 5998 MLX5_QUERY_FLOW_GROUP_OUT_MATCH_CRITERIA_ENABLE_MISC_PARAMETERS = 0x1, 5999 MLX5_QUERY_FLOW_GROUP_OUT_MATCH_CRITERIA_ENABLE_INNER_HEADERS = 0x2, 6000 MLX5_QUERY_FLOW_GROUP_IN_MATCH_CRITERIA_ENABLE_MISC_PARAMETERS_2 = 0x3, 6001 MLX5_QUERY_FLOW_GROUP_IN_MATCH_CRITERIA_ENABLE_MISC_PARAMETERS_3 = 0x4, 6002 MLX5_QUERY_FLOW_GROUP_IN_MATCH_CRITERIA_ENABLE_MISC_PARAMETERS_4 = 0x5, 6003 MLX5_QUERY_FLOW_GROUP_IN_MATCH_CRITERIA_ENABLE_MISC_PARAMETERS_5 = 0x6, 6004 }; 6005 6006 struct mlx5_ifc_query_flow_group_out_bits { 6007 u8 status[0x8]; 6008 u8 reserved_at_8[0x18]; 6009 6010 u8 syndrome[0x20]; 6011 6012 u8 reserved_at_40[0xa0]; 6013 6014 u8 start_flow_index[0x20]; 6015 6016 u8 reserved_at_100[0x20]; 6017 6018 u8 end_flow_index[0x20]; 6019 6020 u8 reserved_at_140[0xa0]; 6021 6022 u8 reserved_at_1e0[0x18]; 6023 u8 match_criteria_enable[0x8]; 6024 6025 struct mlx5_ifc_fte_match_param_bits match_criteria; 6026 6027 u8 reserved_at_1200[0xe00]; 6028 }; 6029 6030 struct mlx5_ifc_query_flow_group_in_bits { 6031 u8 opcode[0x10]; 6032 u8 reserved_at_10[0x10]; 6033 6034 u8 reserved_at_20[0x10]; 6035 u8 op_mod[0x10]; 6036 6037 u8 reserved_at_40[0x40]; 6038 6039 u8 table_type[0x8]; 6040 u8 reserved_at_88[0x18]; 6041 6042 u8 reserved_at_a0[0x8]; 6043 u8 table_id[0x18]; 6044 6045 u8 group_id[0x20]; 6046 6047 u8 reserved_at_e0[0x120]; 6048 }; 6049 6050 struct mlx5_ifc_query_flow_counter_out_bits { 6051 u8 status[0x8]; 6052 u8 reserved_at_8[0x18]; 6053 6054 u8 syndrome[0x20]; 6055 6056 u8 reserved_at_40[0x40]; 6057 6058 struct mlx5_ifc_traffic_counter_bits flow_statistics[]; 6059 }; 6060 6061 struct mlx5_ifc_query_flow_counter_in_bits { 6062 u8 opcode[0x10]; 6063 u8 reserved_at_10[0x10]; 6064 6065 u8 reserved_at_20[0x10]; 6066 u8 op_mod[0x10]; 6067 6068 u8 reserved_at_40[0x80]; 6069 6070 u8 clear[0x1]; 6071 u8 reserved_at_c1[0xf]; 6072 u8 num_of_counters[0x10]; 6073 6074 u8 flow_counter_id[0x20]; 6075 }; 6076 6077 struct mlx5_ifc_query_esw_vport_context_out_bits { 6078 u8 status[0x8]; 6079 u8 reserved_at_8[0x18]; 6080 6081 u8 syndrome[0x20]; 6082 6083 u8 reserved_at_40[0x40]; 6084 6085 struct mlx5_ifc_esw_vport_context_bits esw_vport_context; 6086 }; 6087 6088 struct mlx5_ifc_query_esw_vport_context_in_bits { 6089 u8 opcode[0x10]; 6090 u8 reserved_at_10[0x10]; 6091 6092 u8 reserved_at_20[0x10]; 6093 u8 op_mod[0x10]; 6094 6095 u8 other_vport[0x1]; 6096 u8 reserved_at_41[0xf]; 6097 u8 vport_number[0x10]; 6098 6099 u8 reserved_at_60[0x20]; 6100 }; 6101 6102 struct mlx5_ifc_modify_esw_vport_context_out_bits { 6103 u8 status[0x8]; 6104 u8 reserved_at_8[0x18]; 6105 6106 u8 syndrome[0x20]; 6107 6108 u8 reserved_at_40[0x40]; 6109 }; 6110 6111 struct mlx5_ifc_esw_vport_context_fields_select_bits { 6112 u8 reserved_at_0[0x1b]; 6113 u8 fdb_to_vport_reg_c_id[0x1]; 6114 u8 vport_cvlan_insert[0x1]; 6115 u8 vport_svlan_insert[0x1]; 6116 u8 vport_cvlan_strip[0x1]; 6117 u8 vport_svlan_strip[0x1]; 6118 }; 6119 6120 struct mlx5_ifc_modify_esw_vport_context_in_bits { 6121 u8 opcode[0x10]; 6122 u8 reserved_at_10[0x10]; 6123 6124 u8 reserved_at_20[0x10]; 6125 u8 op_mod[0x10]; 6126 6127 u8 other_vport[0x1]; 6128 u8 reserved_at_41[0xf]; 6129 u8 vport_number[0x10]; 6130 6131 struct mlx5_ifc_esw_vport_context_fields_select_bits field_select; 6132 6133 struct mlx5_ifc_esw_vport_context_bits esw_vport_context; 6134 }; 6135 6136 struct mlx5_ifc_query_eq_out_bits { 6137 u8 status[0x8]; 6138 u8 reserved_at_8[0x18]; 6139 6140 u8 syndrome[0x20]; 6141 6142 u8 reserved_at_40[0x40]; 6143 6144 struct mlx5_ifc_eqc_bits eq_context_entry; 6145 6146 u8 reserved_at_280[0x40]; 6147 6148 u8 event_bitmask[0x40]; 6149 6150 u8 reserved_at_300[0x580]; 6151 6152 u8 pas[][0x40]; 6153 }; 6154 6155 struct mlx5_ifc_query_eq_in_bits { 6156 u8 opcode[0x10]; 6157 u8 reserved_at_10[0x10]; 6158 6159 u8 reserved_at_20[0x10]; 6160 u8 op_mod[0x10]; 6161 6162 u8 reserved_at_40[0x18]; 6163 u8 eq_number[0x8]; 6164 6165 u8 reserved_at_60[0x20]; 6166 }; 6167 6168 struct mlx5_ifc_packet_reformat_context_in_bits { 6169 u8 reformat_type[0x8]; 6170 u8 reserved_at_8[0x4]; 6171 u8 reformat_param_0[0x4]; 6172 u8 reserved_at_10[0x6]; 6173 u8 reformat_data_size[0xa]; 6174 6175 u8 reformat_param_1[0x8]; 6176 u8 reserved_at_28[0x8]; 6177 u8 reformat_data[2][0x8]; 6178 6179 u8 more_reformat_data[][0x8]; 6180 }; 6181 6182 struct mlx5_ifc_query_packet_reformat_context_out_bits { 6183 u8 status[0x8]; 6184 u8 reserved_at_8[0x18]; 6185 6186 u8 syndrome[0x20]; 6187 6188 u8 reserved_at_40[0xa0]; 6189 6190 struct mlx5_ifc_packet_reformat_context_in_bits packet_reformat_context[]; 6191 }; 6192 6193 struct mlx5_ifc_query_packet_reformat_context_in_bits { 6194 u8 opcode[0x10]; 6195 u8 reserved_at_10[0x10]; 6196 6197 u8 reserved_at_20[0x10]; 6198 u8 op_mod[0x10]; 6199 6200 u8 packet_reformat_id[0x20]; 6201 6202 u8 reserved_at_60[0xa0]; 6203 }; 6204 6205 struct mlx5_ifc_alloc_packet_reformat_context_out_bits { 6206 u8 status[0x8]; 6207 u8 reserved_at_8[0x18]; 6208 6209 u8 syndrome[0x20]; 6210 6211 u8 packet_reformat_id[0x20]; 6212 6213 u8 reserved_at_60[0x20]; 6214 }; 6215 6216 enum { 6217 MLX5_REFORMAT_CONTEXT_ANCHOR_MAC_START = 0x1, 6218 MLX5_REFORMAT_CONTEXT_ANCHOR_IP_START = 0x7, 6219 MLX5_REFORMAT_CONTEXT_ANCHOR_TCP_UDP_START = 0x9, 6220 }; 6221 6222 enum mlx5_reformat_ctx_type { 6223 MLX5_REFORMAT_TYPE_L2_TO_VXLAN = 0x0, 6224 MLX5_REFORMAT_TYPE_L2_TO_NVGRE = 0x1, 6225 MLX5_REFORMAT_TYPE_L2_TO_L2_TUNNEL = 0x2, 6226 MLX5_REFORMAT_TYPE_L3_TUNNEL_TO_L2 = 0x3, 6227 MLX5_REFORMAT_TYPE_L2_TO_L3_TUNNEL = 0x4, 6228 MLX5_REFORMAT_TYPE_INSERT_HDR = 0xf, 6229 MLX5_REFORMAT_TYPE_REMOVE_HDR = 0x10, 6230 }; 6231 6232 struct mlx5_ifc_alloc_packet_reformat_context_in_bits { 6233 u8 opcode[0x10]; 6234 u8 reserved_at_10[0x10]; 6235 6236 u8 reserved_at_20[0x10]; 6237 u8 op_mod[0x10]; 6238 6239 u8 reserved_at_40[0xa0]; 6240 6241 struct mlx5_ifc_packet_reformat_context_in_bits packet_reformat_context; 6242 }; 6243 6244 struct mlx5_ifc_dealloc_packet_reformat_context_out_bits { 6245 u8 status[0x8]; 6246 u8 reserved_at_8[0x18]; 6247 6248 u8 syndrome[0x20]; 6249 6250 u8 reserved_at_40[0x40]; 6251 }; 6252 6253 struct mlx5_ifc_dealloc_packet_reformat_context_in_bits { 6254 u8 opcode[0x10]; 6255 u8 reserved_at_10[0x10]; 6256 6257 u8 reserved_20[0x10]; 6258 u8 op_mod[0x10]; 6259 6260 u8 packet_reformat_id[0x20]; 6261 6262 u8 reserved_60[0x20]; 6263 }; 6264 6265 struct mlx5_ifc_set_action_in_bits { 6266 u8 action_type[0x4]; 6267 u8 field[0xc]; 6268 u8 reserved_at_10[0x3]; 6269 u8 offset[0x5]; 6270 u8 reserved_at_18[0x3]; 6271 u8 length[0x5]; 6272 6273 u8 data[0x20]; 6274 }; 6275 6276 struct mlx5_ifc_add_action_in_bits { 6277 u8 action_type[0x4]; 6278 u8 field[0xc]; 6279 u8 reserved_at_10[0x10]; 6280 6281 u8 data[0x20]; 6282 }; 6283 6284 struct mlx5_ifc_copy_action_in_bits { 6285 u8 action_type[0x4]; 6286 u8 src_field[0xc]; 6287 u8 reserved_at_10[0x3]; 6288 u8 src_offset[0x5]; 6289 u8 reserved_at_18[0x3]; 6290 u8 length[0x5]; 6291 6292 u8 reserved_at_20[0x4]; 6293 u8 dst_field[0xc]; 6294 u8 reserved_at_30[0x3]; 6295 u8 dst_offset[0x5]; 6296 u8 reserved_at_38[0x8]; 6297 }; 6298 6299 union mlx5_ifc_set_add_copy_action_in_auto_bits { 6300 struct mlx5_ifc_set_action_in_bits set_action_in; 6301 struct mlx5_ifc_add_action_in_bits add_action_in; 6302 struct mlx5_ifc_copy_action_in_bits copy_action_in; 6303 u8 reserved_at_0[0x40]; 6304 }; 6305 6306 enum { 6307 MLX5_ACTION_TYPE_SET = 0x1, 6308 MLX5_ACTION_TYPE_ADD = 0x2, 6309 MLX5_ACTION_TYPE_COPY = 0x3, 6310 }; 6311 6312 enum { 6313 MLX5_ACTION_IN_FIELD_OUT_SMAC_47_16 = 0x1, 6314 MLX5_ACTION_IN_FIELD_OUT_SMAC_15_0 = 0x2, 6315 MLX5_ACTION_IN_FIELD_OUT_ETHERTYPE = 0x3, 6316 MLX5_ACTION_IN_FIELD_OUT_DMAC_47_16 = 0x4, 6317 MLX5_ACTION_IN_FIELD_OUT_DMAC_15_0 = 0x5, 6318 MLX5_ACTION_IN_FIELD_OUT_IP_DSCP = 0x6, 6319 MLX5_ACTION_IN_FIELD_OUT_TCP_FLAGS = 0x7, 6320 MLX5_ACTION_IN_FIELD_OUT_TCP_SPORT = 0x8, 6321 MLX5_ACTION_IN_FIELD_OUT_TCP_DPORT = 0x9, 6322 MLX5_ACTION_IN_FIELD_OUT_IP_TTL = 0xa, 6323 MLX5_ACTION_IN_FIELD_OUT_UDP_SPORT = 0xb, 6324 MLX5_ACTION_IN_FIELD_OUT_UDP_DPORT = 0xc, 6325 MLX5_ACTION_IN_FIELD_OUT_SIPV6_127_96 = 0xd, 6326 MLX5_ACTION_IN_FIELD_OUT_SIPV6_95_64 = 0xe, 6327 MLX5_ACTION_IN_FIELD_OUT_SIPV6_63_32 = 0xf, 6328 MLX5_ACTION_IN_FIELD_OUT_SIPV6_31_0 = 0x10, 6329 MLX5_ACTION_IN_FIELD_OUT_DIPV6_127_96 = 0x11, 6330 MLX5_ACTION_IN_FIELD_OUT_DIPV6_95_64 = 0x12, 6331 MLX5_ACTION_IN_FIELD_OUT_DIPV6_63_32 = 0x13, 6332 MLX5_ACTION_IN_FIELD_OUT_DIPV6_31_0 = 0x14, 6333 MLX5_ACTION_IN_FIELD_OUT_SIPV4 = 0x15, 6334 MLX5_ACTION_IN_FIELD_OUT_DIPV4 = 0x16, 6335 MLX5_ACTION_IN_FIELD_OUT_FIRST_VID = 0x17, 6336 MLX5_ACTION_IN_FIELD_OUT_IPV6_HOPLIMIT = 0x47, 6337 MLX5_ACTION_IN_FIELD_METADATA_REG_A = 0x49, 6338 MLX5_ACTION_IN_FIELD_METADATA_REG_B = 0x50, 6339 MLX5_ACTION_IN_FIELD_METADATA_REG_C_0 = 0x51, 6340 MLX5_ACTION_IN_FIELD_METADATA_REG_C_1 = 0x52, 6341 MLX5_ACTION_IN_FIELD_METADATA_REG_C_2 = 0x53, 6342 MLX5_ACTION_IN_FIELD_METADATA_REG_C_3 = 0x54, 6343 MLX5_ACTION_IN_FIELD_METADATA_REG_C_4 = 0x55, 6344 MLX5_ACTION_IN_FIELD_METADATA_REG_C_5 = 0x56, 6345 MLX5_ACTION_IN_FIELD_METADATA_REG_C_6 = 0x57, 6346 MLX5_ACTION_IN_FIELD_METADATA_REG_C_7 = 0x58, 6347 MLX5_ACTION_IN_FIELD_OUT_TCP_SEQ_NUM = 0x59, 6348 MLX5_ACTION_IN_FIELD_OUT_TCP_ACK_NUM = 0x5B, 6349 MLX5_ACTION_IN_FIELD_IPSEC_SYNDROME = 0x5D, 6350 MLX5_ACTION_IN_FIELD_OUT_EMD_47_32 = 0x6F, 6351 MLX5_ACTION_IN_FIELD_OUT_EMD_31_0 = 0x70, 6352 }; 6353 6354 struct mlx5_ifc_alloc_modify_header_context_out_bits { 6355 u8 status[0x8]; 6356 u8 reserved_at_8[0x18]; 6357 6358 u8 syndrome[0x20]; 6359 6360 u8 modify_header_id[0x20]; 6361 6362 u8 reserved_at_60[0x20]; 6363 }; 6364 6365 struct mlx5_ifc_alloc_modify_header_context_in_bits { 6366 u8 opcode[0x10]; 6367 u8 reserved_at_10[0x10]; 6368 6369 u8 reserved_at_20[0x10]; 6370 u8 op_mod[0x10]; 6371 6372 u8 reserved_at_40[0x20]; 6373 6374 u8 table_type[0x8]; 6375 u8 reserved_at_68[0x10]; 6376 u8 num_of_actions[0x8]; 6377 6378 union mlx5_ifc_set_add_copy_action_in_auto_bits actions[]; 6379 }; 6380 6381 struct mlx5_ifc_dealloc_modify_header_context_out_bits { 6382 u8 status[0x8]; 6383 u8 reserved_at_8[0x18]; 6384 6385 u8 syndrome[0x20]; 6386 6387 u8 reserved_at_40[0x40]; 6388 }; 6389 6390 struct mlx5_ifc_dealloc_modify_header_context_in_bits { 6391 u8 opcode[0x10]; 6392 u8 reserved_at_10[0x10]; 6393 6394 u8 reserved_at_20[0x10]; 6395 u8 op_mod[0x10]; 6396 6397 u8 modify_header_id[0x20]; 6398 6399 u8 reserved_at_60[0x20]; 6400 }; 6401 6402 struct mlx5_ifc_query_modify_header_context_in_bits { 6403 u8 opcode[0x10]; 6404 u8 uid[0x10]; 6405 6406 u8 reserved_at_20[0x10]; 6407 u8 op_mod[0x10]; 6408 6409 u8 modify_header_id[0x20]; 6410 6411 u8 reserved_at_60[0xa0]; 6412 }; 6413 6414 struct mlx5_ifc_query_dct_out_bits { 6415 u8 status[0x8]; 6416 u8 reserved_at_8[0x18]; 6417 6418 u8 syndrome[0x20]; 6419 6420 u8 reserved_at_40[0x40]; 6421 6422 struct mlx5_ifc_dctc_bits dct_context_entry; 6423 6424 u8 reserved_at_280[0x180]; 6425 }; 6426 6427 struct mlx5_ifc_query_dct_in_bits { 6428 u8 opcode[0x10]; 6429 u8 reserved_at_10[0x10]; 6430 6431 u8 reserved_at_20[0x10]; 6432 u8 op_mod[0x10]; 6433 6434 u8 reserved_at_40[0x8]; 6435 u8 dctn[0x18]; 6436 6437 u8 reserved_at_60[0x20]; 6438 }; 6439 6440 struct mlx5_ifc_query_cq_out_bits { 6441 u8 status[0x8]; 6442 u8 reserved_at_8[0x18]; 6443 6444 u8 syndrome[0x20]; 6445 6446 u8 reserved_at_40[0x40]; 6447 6448 struct mlx5_ifc_cqc_bits cq_context; 6449 6450 u8 reserved_at_280[0x600]; 6451 6452 u8 pas[][0x40]; 6453 }; 6454 6455 struct mlx5_ifc_query_cq_in_bits { 6456 u8 opcode[0x10]; 6457 u8 reserved_at_10[0x10]; 6458 6459 u8 reserved_at_20[0x10]; 6460 u8 op_mod[0x10]; 6461 6462 u8 reserved_at_40[0x8]; 6463 u8 cqn[0x18]; 6464 6465 u8 reserved_at_60[0x20]; 6466 }; 6467 6468 struct mlx5_ifc_query_cong_status_out_bits { 6469 u8 status[0x8]; 6470 u8 reserved_at_8[0x18]; 6471 6472 u8 syndrome[0x20]; 6473 6474 u8 reserved_at_40[0x20]; 6475 6476 u8 enable[0x1]; 6477 u8 tag_enable[0x1]; 6478 u8 reserved_at_62[0x1e]; 6479 }; 6480 6481 struct mlx5_ifc_query_cong_status_in_bits { 6482 u8 opcode[0x10]; 6483 u8 reserved_at_10[0x10]; 6484 6485 u8 reserved_at_20[0x10]; 6486 u8 op_mod[0x10]; 6487 6488 u8 reserved_at_40[0x18]; 6489 u8 priority[0x4]; 6490 u8 cong_protocol[0x4]; 6491 6492 u8 reserved_at_60[0x20]; 6493 }; 6494 6495 struct mlx5_ifc_query_cong_statistics_out_bits { 6496 u8 status[0x8]; 6497 u8 reserved_at_8[0x18]; 6498 6499 u8 syndrome[0x20]; 6500 6501 u8 reserved_at_40[0x40]; 6502 6503 u8 rp_cur_flows[0x20]; 6504 6505 u8 sum_flows[0x20]; 6506 6507 u8 rp_cnp_ignored_high[0x20]; 6508 6509 u8 rp_cnp_ignored_low[0x20]; 6510 6511 u8 rp_cnp_handled_high[0x20]; 6512 6513 u8 rp_cnp_handled_low[0x20]; 6514 6515 u8 reserved_at_140[0x100]; 6516 6517 u8 time_stamp_high[0x20]; 6518 6519 u8 time_stamp_low[0x20]; 6520 6521 u8 accumulators_period[0x20]; 6522 6523 u8 np_ecn_marked_roce_packets_high[0x20]; 6524 6525 u8 np_ecn_marked_roce_packets_low[0x20]; 6526 6527 u8 np_cnp_sent_high[0x20]; 6528 6529 u8 np_cnp_sent_low[0x20]; 6530 6531 u8 reserved_at_320[0x560]; 6532 }; 6533 6534 struct mlx5_ifc_query_cong_statistics_in_bits { 6535 u8 opcode[0x10]; 6536 u8 reserved_at_10[0x10]; 6537 6538 u8 reserved_at_20[0x10]; 6539 u8 op_mod[0x10]; 6540 6541 u8 clear[0x1]; 6542 u8 reserved_at_41[0x1f]; 6543 6544 u8 reserved_at_60[0x20]; 6545 }; 6546 6547 struct mlx5_ifc_query_cong_params_out_bits { 6548 u8 status[0x8]; 6549 u8 reserved_at_8[0x18]; 6550 6551 u8 syndrome[0x20]; 6552 6553 u8 reserved_at_40[0x40]; 6554 6555 union mlx5_ifc_cong_control_roce_ecn_auto_bits congestion_parameters; 6556 }; 6557 6558 struct mlx5_ifc_query_cong_params_in_bits { 6559 u8 opcode[0x10]; 6560 u8 reserved_at_10[0x10]; 6561 6562 u8 reserved_at_20[0x10]; 6563 u8 op_mod[0x10]; 6564 6565 u8 reserved_at_40[0x1c]; 6566 u8 cong_protocol[0x4]; 6567 6568 u8 reserved_at_60[0x20]; 6569 }; 6570 6571 struct mlx5_ifc_query_adapter_out_bits { 6572 u8 status[0x8]; 6573 u8 reserved_at_8[0x18]; 6574 6575 u8 syndrome[0x20]; 6576 6577 u8 reserved_at_40[0x40]; 6578 6579 struct mlx5_ifc_query_adapter_param_block_bits query_adapter_struct; 6580 }; 6581 6582 struct mlx5_ifc_query_adapter_in_bits { 6583 u8 opcode[0x10]; 6584 u8 reserved_at_10[0x10]; 6585 6586 u8 reserved_at_20[0x10]; 6587 u8 op_mod[0x10]; 6588 6589 u8 reserved_at_40[0x40]; 6590 }; 6591 6592 struct mlx5_ifc_qp_2rst_out_bits { 6593 u8 status[0x8]; 6594 u8 reserved_at_8[0x18]; 6595 6596 u8 syndrome[0x20]; 6597 6598 u8 reserved_at_40[0x40]; 6599 }; 6600 6601 struct mlx5_ifc_qp_2rst_in_bits { 6602 u8 opcode[0x10]; 6603 u8 uid[0x10]; 6604 6605 u8 reserved_at_20[0x10]; 6606 u8 op_mod[0x10]; 6607 6608 u8 reserved_at_40[0x8]; 6609 u8 qpn[0x18]; 6610 6611 u8 reserved_at_60[0x20]; 6612 }; 6613 6614 struct mlx5_ifc_qp_2err_out_bits { 6615 u8 status[0x8]; 6616 u8 reserved_at_8[0x18]; 6617 6618 u8 syndrome[0x20]; 6619 6620 u8 reserved_at_40[0x40]; 6621 }; 6622 6623 struct mlx5_ifc_qp_2err_in_bits { 6624 u8 opcode[0x10]; 6625 u8 uid[0x10]; 6626 6627 u8 reserved_at_20[0x10]; 6628 u8 op_mod[0x10]; 6629 6630 u8 reserved_at_40[0x8]; 6631 u8 qpn[0x18]; 6632 6633 u8 reserved_at_60[0x20]; 6634 }; 6635 6636 struct mlx5_ifc_page_fault_resume_out_bits { 6637 u8 status[0x8]; 6638 u8 reserved_at_8[0x18]; 6639 6640 u8 syndrome[0x20]; 6641 6642 u8 reserved_at_40[0x40]; 6643 }; 6644 6645 struct mlx5_ifc_page_fault_resume_in_bits { 6646 u8 opcode[0x10]; 6647 u8 reserved_at_10[0x10]; 6648 6649 u8 reserved_at_20[0x10]; 6650 u8 op_mod[0x10]; 6651 6652 u8 error[0x1]; 6653 u8 reserved_at_41[0x4]; 6654 u8 page_fault_type[0x3]; 6655 u8 wq_number[0x18]; 6656 6657 u8 reserved_at_60[0x8]; 6658 u8 token[0x18]; 6659 }; 6660 6661 struct mlx5_ifc_nop_out_bits { 6662 u8 status[0x8]; 6663 u8 reserved_at_8[0x18]; 6664 6665 u8 syndrome[0x20]; 6666 6667 u8 reserved_at_40[0x40]; 6668 }; 6669 6670 struct mlx5_ifc_nop_in_bits { 6671 u8 opcode[0x10]; 6672 u8 reserved_at_10[0x10]; 6673 6674 u8 reserved_at_20[0x10]; 6675 u8 op_mod[0x10]; 6676 6677 u8 reserved_at_40[0x40]; 6678 }; 6679 6680 struct mlx5_ifc_modify_vport_state_out_bits { 6681 u8 status[0x8]; 6682 u8 reserved_at_8[0x18]; 6683 6684 u8 syndrome[0x20]; 6685 6686 u8 reserved_at_40[0x40]; 6687 }; 6688 6689 struct mlx5_ifc_modify_vport_state_in_bits { 6690 u8 opcode[0x10]; 6691 u8 reserved_at_10[0x10]; 6692 6693 u8 reserved_at_20[0x10]; 6694 u8 op_mod[0x10]; 6695 6696 u8 other_vport[0x1]; 6697 u8 reserved_at_41[0xf]; 6698 u8 vport_number[0x10]; 6699 6700 u8 reserved_at_60[0x18]; 6701 u8 admin_state[0x4]; 6702 u8 reserved_at_7c[0x4]; 6703 }; 6704 6705 struct mlx5_ifc_modify_tis_out_bits { 6706 u8 status[0x8]; 6707 u8 reserved_at_8[0x18]; 6708 6709 u8 syndrome[0x20]; 6710 6711 u8 reserved_at_40[0x40]; 6712 }; 6713 6714 struct mlx5_ifc_modify_tis_bitmask_bits { 6715 u8 reserved_at_0[0x20]; 6716 6717 u8 reserved_at_20[0x1d]; 6718 u8 lag_tx_port_affinity[0x1]; 6719 u8 strict_lag_tx_port_affinity[0x1]; 6720 u8 prio[0x1]; 6721 }; 6722 6723 struct mlx5_ifc_modify_tis_in_bits { 6724 u8 opcode[0x10]; 6725 u8 uid[0x10]; 6726 6727 u8 reserved_at_20[0x10]; 6728 u8 op_mod[0x10]; 6729 6730 u8 reserved_at_40[0x8]; 6731 u8 tisn[0x18]; 6732 6733 u8 reserved_at_60[0x20]; 6734 6735 struct mlx5_ifc_modify_tis_bitmask_bits bitmask; 6736 6737 u8 reserved_at_c0[0x40]; 6738 6739 struct mlx5_ifc_tisc_bits ctx; 6740 }; 6741 6742 struct mlx5_ifc_modify_tir_bitmask_bits { 6743 u8 reserved_at_0[0x20]; 6744 6745 u8 reserved_at_20[0x1b]; 6746 u8 self_lb_en[0x1]; 6747 u8 reserved_at_3c[0x1]; 6748 u8 hash[0x1]; 6749 u8 reserved_at_3e[0x1]; 6750 u8 packet_merge[0x1]; 6751 }; 6752 6753 struct mlx5_ifc_modify_tir_out_bits { 6754 u8 status[0x8]; 6755 u8 reserved_at_8[0x18]; 6756 6757 u8 syndrome[0x20]; 6758 6759 u8 reserved_at_40[0x40]; 6760 }; 6761 6762 struct mlx5_ifc_modify_tir_in_bits { 6763 u8 opcode[0x10]; 6764 u8 uid[0x10]; 6765 6766 u8 reserved_at_20[0x10]; 6767 u8 op_mod[0x10]; 6768 6769 u8 reserved_at_40[0x8]; 6770 u8 tirn[0x18]; 6771 6772 u8 reserved_at_60[0x20]; 6773 6774 struct mlx5_ifc_modify_tir_bitmask_bits bitmask; 6775 6776 u8 reserved_at_c0[0x40]; 6777 6778 struct mlx5_ifc_tirc_bits ctx; 6779 }; 6780 6781 struct mlx5_ifc_modify_sq_out_bits { 6782 u8 status[0x8]; 6783 u8 reserved_at_8[0x18]; 6784 6785 u8 syndrome[0x20]; 6786 6787 u8 reserved_at_40[0x40]; 6788 }; 6789 6790 struct mlx5_ifc_modify_sq_in_bits { 6791 u8 opcode[0x10]; 6792 u8 uid[0x10]; 6793 6794 u8 reserved_at_20[0x10]; 6795 u8 op_mod[0x10]; 6796 6797 u8 sq_state[0x4]; 6798 u8 reserved_at_44[0x4]; 6799 u8 sqn[0x18]; 6800 6801 u8 reserved_at_60[0x20]; 6802 6803 u8 modify_bitmask[0x40]; 6804 6805 u8 reserved_at_c0[0x40]; 6806 6807 struct mlx5_ifc_sqc_bits ctx; 6808 }; 6809 6810 struct mlx5_ifc_modify_scheduling_element_out_bits { 6811 u8 status[0x8]; 6812 u8 reserved_at_8[0x18]; 6813 6814 u8 syndrome[0x20]; 6815 6816 u8 reserved_at_40[0x1c0]; 6817 }; 6818 6819 enum { 6820 MODIFY_SCHEDULING_ELEMENT_IN_MODIFY_BITMASK_BW_SHARE = 0x1, 6821 MODIFY_SCHEDULING_ELEMENT_IN_MODIFY_BITMASK_MAX_AVERAGE_BW = 0x2, 6822 }; 6823 6824 struct mlx5_ifc_modify_scheduling_element_in_bits { 6825 u8 opcode[0x10]; 6826 u8 reserved_at_10[0x10]; 6827 6828 u8 reserved_at_20[0x10]; 6829 u8 op_mod[0x10]; 6830 6831 u8 scheduling_hierarchy[0x8]; 6832 u8 reserved_at_48[0x18]; 6833 6834 u8 scheduling_element_id[0x20]; 6835 6836 u8 reserved_at_80[0x20]; 6837 6838 u8 modify_bitmask[0x20]; 6839 6840 u8 reserved_at_c0[0x40]; 6841 6842 struct mlx5_ifc_scheduling_context_bits scheduling_context; 6843 6844 u8 reserved_at_300[0x100]; 6845 }; 6846 6847 struct mlx5_ifc_modify_rqt_out_bits { 6848 u8 status[0x8]; 6849 u8 reserved_at_8[0x18]; 6850 6851 u8 syndrome[0x20]; 6852 6853 u8 reserved_at_40[0x40]; 6854 }; 6855 6856 struct mlx5_ifc_rqt_bitmask_bits { 6857 u8 reserved_at_0[0x20]; 6858 6859 u8 reserved_at_20[0x1f]; 6860 u8 rqn_list[0x1]; 6861 }; 6862 6863 struct mlx5_ifc_modify_rqt_in_bits { 6864 u8 opcode[0x10]; 6865 u8 uid[0x10]; 6866 6867 u8 reserved_at_20[0x10]; 6868 u8 op_mod[0x10]; 6869 6870 u8 reserved_at_40[0x8]; 6871 u8 rqtn[0x18]; 6872 6873 u8 reserved_at_60[0x20]; 6874 6875 struct mlx5_ifc_rqt_bitmask_bits bitmask; 6876 6877 u8 reserved_at_c0[0x40]; 6878 6879 struct mlx5_ifc_rqtc_bits ctx; 6880 }; 6881 6882 struct mlx5_ifc_modify_rq_out_bits { 6883 u8 status[0x8]; 6884 u8 reserved_at_8[0x18]; 6885 6886 u8 syndrome[0x20]; 6887 6888 u8 reserved_at_40[0x40]; 6889 }; 6890 6891 enum { 6892 MLX5_MODIFY_RQ_IN_MODIFY_BITMASK_VSD = 1ULL << 1, 6893 MLX5_MODIFY_RQ_IN_MODIFY_BITMASK_SCATTER_FCS = 1ULL << 2, 6894 MLX5_MODIFY_RQ_IN_MODIFY_BITMASK_RQ_COUNTER_SET_ID = 1ULL << 3, 6895 }; 6896 6897 struct mlx5_ifc_modify_rq_in_bits { 6898 u8 opcode[0x10]; 6899 u8 uid[0x10]; 6900 6901 u8 reserved_at_20[0x10]; 6902 u8 op_mod[0x10]; 6903 6904 u8 rq_state[0x4]; 6905 u8 reserved_at_44[0x4]; 6906 u8 rqn[0x18]; 6907 6908 u8 reserved_at_60[0x20]; 6909 6910 u8 modify_bitmask[0x40]; 6911 6912 u8 reserved_at_c0[0x40]; 6913 6914 struct mlx5_ifc_rqc_bits ctx; 6915 }; 6916 6917 struct mlx5_ifc_modify_rmp_out_bits { 6918 u8 status[0x8]; 6919 u8 reserved_at_8[0x18]; 6920 6921 u8 syndrome[0x20]; 6922 6923 u8 reserved_at_40[0x40]; 6924 }; 6925 6926 struct mlx5_ifc_rmp_bitmask_bits { 6927 u8 reserved_at_0[0x20]; 6928 6929 u8 reserved_at_20[0x1f]; 6930 u8 lwm[0x1]; 6931 }; 6932 6933 struct mlx5_ifc_modify_rmp_in_bits { 6934 u8 opcode[0x10]; 6935 u8 uid[0x10]; 6936 6937 u8 reserved_at_20[0x10]; 6938 u8 op_mod[0x10]; 6939 6940 u8 rmp_state[0x4]; 6941 u8 reserved_at_44[0x4]; 6942 u8 rmpn[0x18]; 6943 6944 u8 reserved_at_60[0x20]; 6945 6946 struct mlx5_ifc_rmp_bitmask_bits bitmask; 6947 6948 u8 reserved_at_c0[0x40]; 6949 6950 struct mlx5_ifc_rmpc_bits ctx; 6951 }; 6952 6953 struct mlx5_ifc_modify_nic_vport_context_out_bits { 6954 u8 status[0x8]; 6955 u8 reserved_at_8[0x18]; 6956 6957 u8 syndrome[0x20]; 6958 6959 u8 reserved_at_40[0x40]; 6960 }; 6961 6962 struct mlx5_ifc_modify_nic_vport_field_select_bits { 6963 u8 reserved_at_0[0x12]; 6964 u8 affiliation[0x1]; 6965 u8 reserved_at_13[0x1]; 6966 u8 disable_uc_local_lb[0x1]; 6967 u8 disable_mc_local_lb[0x1]; 6968 u8 node_guid[0x1]; 6969 u8 port_guid[0x1]; 6970 u8 min_inline[0x1]; 6971 u8 mtu[0x1]; 6972 u8 change_event[0x1]; 6973 u8 promisc[0x1]; 6974 u8 permanent_address[0x1]; 6975 u8 addresses_list[0x1]; 6976 u8 roce_en[0x1]; 6977 u8 reserved_at_1f[0x1]; 6978 }; 6979 6980 struct mlx5_ifc_modify_nic_vport_context_in_bits { 6981 u8 opcode[0x10]; 6982 u8 reserved_at_10[0x10]; 6983 6984 u8 reserved_at_20[0x10]; 6985 u8 op_mod[0x10]; 6986 6987 u8 other_vport[0x1]; 6988 u8 reserved_at_41[0xf]; 6989 u8 vport_number[0x10]; 6990 6991 struct mlx5_ifc_modify_nic_vport_field_select_bits field_select; 6992 6993 u8 reserved_at_80[0x780]; 6994 6995 struct mlx5_ifc_nic_vport_context_bits nic_vport_context; 6996 }; 6997 6998 struct mlx5_ifc_modify_hca_vport_context_out_bits { 6999 u8 status[0x8]; 7000 u8 reserved_at_8[0x18]; 7001 7002 u8 syndrome[0x20]; 7003 7004 u8 reserved_at_40[0x40]; 7005 }; 7006 7007 struct mlx5_ifc_modify_hca_vport_context_in_bits { 7008 u8 opcode[0x10]; 7009 u8 reserved_at_10[0x10]; 7010 7011 u8 reserved_at_20[0x10]; 7012 u8 op_mod[0x10]; 7013 7014 u8 other_vport[0x1]; 7015 u8 reserved_at_41[0xb]; 7016 u8 port_num[0x4]; 7017 u8 vport_number[0x10]; 7018 7019 u8 reserved_at_60[0x20]; 7020 7021 struct mlx5_ifc_hca_vport_context_bits hca_vport_context; 7022 }; 7023 7024 struct mlx5_ifc_modify_cq_out_bits { 7025 u8 status[0x8]; 7026 u8 reserved_at_8[0x18]; 7027 7028 u8 syndrome[0x20]; 7029 7030 u8 reserved_at_40[0x40]; 7031 }; 7032 7033 enum { 7034 MLX5_MODIFY_CQ_IN_OP_MOD_MODIFY_CQ = 0x0, 7035 MLX5_MODIFY_CQ_IN_OP_MOD_RESIZE_CQ = 0x1, 7036 }; 7037 7038 struct mlx5_ifc_modify_cq_in_bits { 7039 u8 opcode[0x10]; 7040 u8 uid[0x10]; 7041 7042 u8 reserved_at_20[0x10]; 7043 u8 op_mod[0x10]; 7044 7045 u8 reserved_at_40[0x8]; 7046 u8 cqn[0x18]; 7047 7048 union mlx5_ifc_modify_field_select_resize_field_select_auto_bits modify_field_select_resize_field_select; 7049 7050 struct mlx5_ifc_cqc_bits cq_context; 7051 7052 u8 reserved_at_280[0x60]; 7053 7054 u8 cq_umem_valid[0x1]; 7055 u8 reserved_at_2e1[0x1f]; 7056 7057 u8 reserved_at_300[0x580]; 7058 7059 u8 pas[][0x40]; 7060 }; 7061 7062 struct mlx5_ifc_modify_cong_status_out_bits { 7063 u8 status[0x8]; 7064 u8 reserved_at_8[0x18]; 7065 7066 u8 syndrome[0x20]; 7067 7068 u8 reserved_at_40[0x40]; 7069 }; 7070 7071 struct mlx5_ifc_modify_cong_status_in_bits { 7072 u8 opcode[0x10]; 7073 u8 reserved_at_10[0x10]; 7074 7075 u8 reserved_at_20[0x10]; 7076 u8 op_mod[0x10]; 7077 7078 u8 reserved_at_40[0x18]; 7079 u8 priority[0x4]; 7080 u8 cong_protocol[0x4]; 7081 7082 u8 enable[0x1]; 7083 u8 tag_enable[0x1]; 7084 u8 reserved_at_62[0x1e]; 7085 }; 7086 7087 struct mlx5_ifc_modify_cong_params_out_bits { 7088 u8 status[0x8]; 7089 u8 reserved_at_8[0x18]; 7090 7091 u8 syndrome[0x20]; 7092 7093 u8 reserved_at_40[0x40]; 7094 }; 7095 7096 struct mlx5_ifc_modify_cong_params_in_bits { 7097 u8 opcode[0x10]; 7098 u8 reserved_at_10[0x10]; 7099 7100 u8 reserved_at_20[0x10]; 7101 u8 op_mod[0x10]; 7102 7103 u8 reserved_at_40[0x1c]; 7104 u8 cong_protocol[0x4]; 7105 7106 union mlx5_ifc_field_select_802_1_r_roce_auto_bits field_select; 7107 7108 u8 reserved_at_80[0x80]; 7109 7110 union mlx5_ifc_cong_control_roce_ecn_auto_bits congestion_parameters; 7111 }; 7112 7113 struct mlx5_ifc_manage_pages_out_bits { 7114 u8 status[0x8]; 7115 u8 reserved_at_8[0x18]; 7116 7117 u8 syndrome[0x20]; 7118 7119 u8 output_num_entries[0x20]; 7120 7121 u8 reserved_at_60[0x20]; 7122 7123 u8 pas[][0x40]; 7124 }; 7125 7126 enum { 7127 MLX5_MANAGE_PAGES_IN_OP_MOD_ALLOCATION_FAIL = 0x0, 7128 MLX5_MANAGE_PAGES_IN_OP_MOD_ALLOCATION_SUCCESS = 0x1, 7129 MLX5_MANAGE_PAGES_IN_OP_MOD_HCA_RETURN_PAGES = 0x2, 7130 }; 7131 7132 struct mlx5_ifc_manage_pages_in_bits { 7133 u8 opcode[0x10]; 7134 u8 reserved_at_10[0x10]; 7135 7136 u8 reserved_at_20[0x10]; 7137 u8 op_mod[0x10]; 7138 7139 u8 embedded_cpu_function[0x1]; 7140 u8 reserved_at_41[0xf]; 7141 u8 function_id[0x10]; 7142 7143 u8 input_num_entries[0x20]; 7144 7145 u8 pas[][0x40]; 7146 }; 7147 7148 struct mlx5_ifc_mad_ifc_out_bits { 7149 u8 status[0x8]; 7150 u8 reserved_at_8[0x18]; 7151 7152 u8 syndrome[0x20]; 7153 7154 u8 reserved_at_40[0x40]; 7155 7156 u8 response_mad_packet[256][0x8]; 7157 }; 7158 7159 struct mlx5_ifc_mad_ifc_in_bits { 7160 u8 opcode[0x10]; 7161 u8 reserved_at_10[0x10]; 7162 7163 u8 reserved_at_20[0x10]; 7164 u8 op_mod[0x10]; 7165 7166 u8 remote_lid[0x10]; 7167 u8 reserved_at_50[0x8]; 7168 u8 port[0x8]; 7169 7170 u8 reserved_at_60[0x20]; 7171 7172 u8 mad[256][0x8]; 7173 }; 7174 7175 struct mlx5_ifc_init_hca_out_bits { 7176 u8 status[0x8]; 7177 u8 reserved_at_8[0x18]; 7178 7179 u8 syndrome[0x20]; 7180 7181 u8 reserved_at_40[0x40]; 7182 }; 7183 7184 struct mlx5_ifc_init_hca_in_bits { 7185 u8 opcode[0x10]; 7186 u8 reserved_at_10[0x10]; 7187 7188 u8 reserved_at_20[0x10]; 7189 u8 op_mod[0x10]; 7190 7191 u8 reserved_at_40[0x40]; 7192 u8 sw_owner_id[4][0x20]; 7193 }; 7194 7195 struct mlx5_ifc_init2rtr_qp_out_bits { 7196 u8 status[0x8]; 7197 u8 reserved_at_8[0x18]; 7198 7199 u8 syndrome[0x20]; 7200 7201 u8 reserved_at_40[0x20]; 7202 u8 ece[0x20]; 7203 }; 7204 7205 struct mlx5_ifc_init2rtr_qp_in_bits { 7206 u8 opcode[0x10]; 7207 u8 uid[0x10]; 7208 7209 u8 reserved_at_20[0x10]; 7210 u8 op_mod[0x10]; 7211 7212 u8 reserved_at_40[0x8]; 7213 u8 qpn[0x18]; 7214 7215 u8 reserved_at_60[0x20]; 7216 7217 u8 opt_param_mask[0x20]; 7218 7219 u8 ece[0x20]; 7220 7221 struct mlx5_ifc_qpc_bits qpc; 7222 7223 u8 reserved_at_800[0x80]; 7224 }; 7225 7226 struct mlx5_ifc_init2init_qp_out_bits { 7227 u8 status[0x8]; 7228 u8 reserved_at_8[0x18]; 7229 7230 u8 syndrome[0x20]; 7231 7232 u8 reserved_at_40[0x20]; 7233 u8 ece[0x20]; 7234 }; 7235 7236 struct mlx5_ifc_init2init_qp_in_bits { 7237 u8 opcode[0x10]; 7238 u8 uid[0x10]; 7239 7240 u8 reserved_at_20[0x10]; 7241 u8 op_mod[0x10]; 7242 7243 u8 reserved_at_40[0x8]; 7244 u8 qpn[0x18]; 7245 7246 u8 reserved_at_60[0x20]; 7247 7248 u8 opt_param_mask[0x20]; 7249 7250 u8 ece[0x20]; 7251 7252 struct mlx5_ifc_qpc_bits qpc; 7253 7254 u8 reserved_at_800[0x80]; 7255 }; 7256 7257 struct mlx5_ifc_get_dropped_packet_log_out_bits { 7258 u8 status[0x8]; 7259 u8 reserved_at_8[0x18]; 7260 7261 u8 syndrome[0x20]; 7262 7263 u8 reserved_at_40[0x40]; 7264 7265 u8 packet_headers_log[128][0x8]; 7266 7267 u8 packet_syndrome[64][0x8]; 7268 }; 7269 7270 struct mlx5_ifc_get_dropped_packet_log_in_bits { 7271 u8 opcode[0x10]; 7272 u8 reserved_at_10[0x10]; 7273 7274 u8 reserved_at_20[0x10]; 7275 u8 op_mod[0x10]; 7276 7277 u8 reserved_at_40[0x40]; 7278 }; 7279 7280 struct mlx5_ifc_gen_eqe_in_bits { 7281 u8 opcode[0x10]; 7282 u8 reserved_at_10[0x10]; 7283 7284 u8 reserved_at_20[0x10]; 7285 u8 op_mod[0x10]; 7286 7287 u8 reserved_at_40[0x18]; 7288 u8 eq_number[0x8]; 7289 7290 u8 reserved_at_60[0x20]; 7291 7292 u8 eqe[64][0x8]; 7293 }; 7294 7295 struct mlx5_ifc_gen_eq_out_bits { 7296 u8 status[0x8]; 7297 u8 reserved_at_8[0x18]; 7298 7299 u8 syndrome[0x20]; 7300 7301 u8 reserved_at_40[0x40]; 7302 }; 7303 7304 struct mlx5_ifc_enable_hca_out_bits { 7305 u8 status[0x8]; 7306 u8 reserved_at_8[0x18]; 7307 7308 u8 syndrome[0x20]; 7309 7310 u8 reserved_at_40[0x20]; 7311 }; 7312 7313 struct mlx5_ifc_enable_hca_in_bits { 7314 u8 opcode[0x10]; 7315 u8 reserved_at_10[0x10]; 7316 7317 u8 reserved_at_20[0x10]; 7318 u8 op_mod[0x10]; 7319 7320 u8 embedded_cpu_function[0x1]; 7321 u8 reserved_at_41[0xf]; 7322 u8 function_id[0x10]; 7323 7324 u8 reserved_at_60[0x20]; 7325 }; 7326 7327 struct mlx5_ifc_drain_dct_out_bits { 7328 u8 status[0x8]; 7329 u8 reserved_at_8[0x18]; 7330 7331 u8 syndrome[0x20]; 7332 7333 u8 reserved_at_40[0x40]; 7334 }; 7335 7336 struct mlx5_ifc_drain_dct_in_bits { 7337 u8 opcode[0x10]; 7338 u8 uid[0x10]; 7339 7340 u8 reserved_at_20[0x10]; 7341 u8 op_mod[0x10]; 7342 7343 u8 reserved_at_40[0x8]; 7344 u8 dctn[0x18]; 7345 7346 u8 reserved_at_60[0x20]; 7347 }; 7348 7349 struct mlx5_ifc_disable_hca_out_bits { 7350 u8 status[0x8]; 7351 u8 reserved_at_8[0x18]; 7352 7353 u8 syndrome[0x20]; 7354 7355 u8 reserved_at_40[0x20]; 7356 }; 7357 7358 struct mlx5_ifc_disable_hca_in_bits { 7359 u8 opcode[0x10]; 7360 u8 reserved_at_10[0x10]; 7361 7362 u8 reserved_at_20[0x10]; 7363 u8 op_mod[0x10]; 7364 7365 u8 embedded_cpu_function[0x1]; 7366 u8 reserved_at_41[0xf]; 7367 u8 function_id[0x10]; 7368 7369 u8 reserved_at_60[0x20]; 7370 }; 7371 7372 struct mlx5_ifc_detach_from_mcg_out_bits { 7373 u8 status[0x8]; 7374 u8 reserved_at_8[0x18]; 7375 7376 u8 syndrome[0x20]; 7377 7378 u8 reserved_at_40[0x40]; 7379 }; 7380 7381 struct mlx5_ifc_detach_from_mcg_in_bits { 7382 u8 opcode[0x10]; 7383 u8 uid[0x10]; 7384 7385 u8 reserved_at_20[0x10]; 7386 u8 op_mod[0x10]; 7387 7388 u8 reserved_at_40[0x8]; 7389 u8 qpn[0x18]; 7390 7391 u8 reserved_at_60[0x20]; 7392 7393 u8 multicast_gid[16][0x8]; 7394 }; 7395 7396 struct mlx5_ifc_destroy_xrq_out_bits { 7397 u8 status[0x8]; 7398 u8 reserved_at_8[0x18]; 7399 7400 u8 syndrome[0x20]; 7401 7402 u8 reserved_at_40[0x40]; 7403 }; 7404 7405 struct mlx5_ifc_destroy_xrq_in_bits { 7406 u8 opcode[0x10]; 7407 u8 uid[0x10]; 7408 7409 u8 reserved_at_20[0x10]; 7410 u8 op_mod[0x10]; 7411 7412 u8 reserved_at_40[0x8]; 7413 u8 xrqn[0x18]; 7414 7415 u8 reserved_at_60[0x20]; 7416 }; 7417 7418 struct mlx5_ifc_destroy_xrc_srq_out_bits { 7419 u8 status[0x8]; 7420 u8 reserved_at_8[0x18]; 7421 7422 u8 syndrome[0x20]; 7423 7424 u8 reserved_at_40[0x40]; 7425 }; 7426 7427 struct mlx5_ifc_destroy_xrc_srq_in_bits { 7428 u8 opcode[0x10]; 7429 u8 uid[0x10]; 7430 7431 u8 reserved_at_20[0x10]; 7432 u8 op_mod[0x10]; 7433 7434 u8 reserved_at_40[0x8]; 7435 u8 xrc_srqn[0x18]; 7436 7437 u8 reserved_at_60[0x20]; 7438 }; 7439 7440 struct mlx5_ifc_destroy_tis_out_bits { 7441 u8 status[0x8]; 7442 u8 reserved_at_8[0x18]; 7443 7444 u8 syndrome[0x20]; 7445 7446 u8 reserved_at_40[0x40]; 7447 }; 7448 7449 struct mlx5_ifc_destroy_tis_in_bits { 7450 u8 opcode[0x10]; 7451 u8 uid[0x10]; 7452 7453 u8 reserved_at_20[0x10]; 7454 u8 op_mod[0x10]; 7455 7456 u8 reserved_at_40[0x8]; 7457 u8 tisn[0x18]; 7458 7459 u8 reserved_at_60[0x20]; 7460 }; 7461 7462 struct mlx5_ifc_destroy_tir_out_bits { 7463 u8 status[0x8]; 7464 u8 reserved_at_8[0x18]; 7465 7466 u8 syndrome[0x20]; 7467 7468 u8 reserved_at_40[0x40]; 7469 }; 7470 7471 struct mlx5_ifc_destroy_tir_in_bits { 7472 u8 opcode[0x10]; 7473 u8 uid[0x10]; 7474 7475 u8 reserved_at_20[0x10]; 7476 u8 op_mod[0x10]; 7477 7478 u8 reserved_at_40[0x8]; 7479 u8 tirn[0x18]; 7480 7481 u8 reserved_at_60[0x20]; 7482 }; 7483 7484 struct mlx5_ifc_destroy_srq_out_bits { 7485 u8 status[0x8]; 7486 u8 reserved_at_8[0x18]; 7487 7488 u8 syndrome[0x20]; 7489 7490 u8 reserved_at_40[0x40]; 7491 }; 7492 7493 struct mlx5_ifc_destroy_srq_in_bits { 7494 u8 opcode[0x10]; 7495 u8 uid[0x10]; 7496 7497 u8 reserved_at_20[0x10]; 7498 u8 op_mod[0x10]; 7499 7500 u8 reserved_at_40[0x8]; 7501 u8 srqn[0x18]; 7502 7503 u8 reserved_at_60[0x20]; 7504 }; 7505 7506 struct mlx5_ifc_destroy_sq_out_bits { 7507 u8 status[0x8]; 7508 u8 reserved_at_8[0x18]; 7509 7510 u8 syndrome[0x20]; 7511 7512 u8 reserved_at_40[0x40]; 7513 }; 7514 7515 struct mlx5_ifc_destroy_sq_in_bits { 7516 u8 opcode[0x10]; 7517 u8 uid[0x10]; 7518 7519 u8 reserved_at_20[0x10]; 7520 u8 op_mod[0x10]; 7521 7522 u8 reserved_at_40[0x8]; 7523 u8 sqn[0x18]; 7524 7525 u8 reserved_at_60[0x20]; 7526 }; 7527 7528 struct mlx5_ifc_destroy_scheduling_element_out_bits { 7529 u8 status[0x8]; 7530 u8 reserved_at_8[0x18]; 7531 7532 u8 syndrome[0x20]; 7533 7534 u8 reserved_at_40[0x1c0]; 7535 }; 7536 7537 struct mlx5_ifc_destroy_scheduling_element_in_bits { 7538 u8 opcode[0x10]; 7539 u8 reserved_at_10[0x10]; 7540 7541 u8 reserved_at_20[0x10]; 7542 u8 op_mod[0x10]; 7543 7544 u8 scheduling_hierarchy[0x8]; 7545 u8 reserved_at_48[0x18]; 7546 7547 u8 scheduling_element_id[0x20]; 7548 7549 u8 reserved_at_80[0x180]; 7550 }; 7551 7552 struct mlx5_ifc_destroy_rqt_out_bits { 7553 u8 status[0x8]; 7554 u8 reserved_at_8[0x18]; 7555 7556 u8 syndrome[0x20]; 7557 7558 u8 reserved_at_40[0x40]; 7559 }; 7560 7561 struct mlx5_ifc_destroy_rqt_in_bits { 7562 u8 opcode[0x10]; 7563 u8 uid[0x10]; 7564 7565 u8 reserved_at_20[0x10]; 7566 u8 op_mod[0x10]; 7567 7568 u8 reserved_at_40[0x8]; 7569 u8 rqtn[0x18]; 7570 7571 u8 reserved_at_60[0x20]; 7572 }; 7573 7574 struct mlx5_ifc_destroy_rq_out_bits { 7575 u8 status[0x8]; 7576 u8 reserved_at_8[0x18]; 7577 7578 u8 syndrome[0x20]; 7579 7580 u8 reserved_at_40[0x40]; 7581 }; 7582 7583 struct mlx5_ifc_destroy_rq_in_bits { 7584 u8 opcode[0x10]; 7585 u8 uid[0x10]; 7586 7587 u8 reserved_at_20[0x10]; 7588 u8 op_mod[0x10]; 7589 7590 u8 reserved_at_40[0x8]; 7591 u8 rqn[0x18]; 7592 7593 u8 reserved_at_60[0x20]; 7594 }; 7595 7596 struct mlx5_ifc_set_delay_drop_params_in_bits { 7597 u8 opcode[0x10]; 7598 u8 reserved_at_10[0x10]; 7599 7600 u8 reserved_at_20[0x10]; 7601 u8 op_mod[0x10]; 7602 7603 u8 reserved_at_40[0x20]; 7604 7605 u8 reserved_at_60[0x10]; 7606 u8 delay_drop_timeout[0x10]; 7607 }; 7608 7609 struct mlx5_ifc_set_delay_drop_params_out_bits { 7610 u8 status[0x8]; 7611 u8 reserved_at_8[0x18]; 7612 7613 u8 syndrome[0x20]; 7614 7615 u8 reserved_at_40[0x40]; 7616 }; 7617 7618 struct mlx5_ifc_destroy_rmp_out_bits { 7619 u8 status[0x8]; 7620 u8 reserved_at_8[0x18]; 7621 7622 u8 syndrome[0x20]; 7623 7624 u8 reserved_at_40[0x40]; 7625 }; 7626 7627 struct mlx5_ifc_destroy_rmp_in_bits { 7628 u8 opcode[0x10]; 7629 u8 uid[0x10]; 7630 7631 u8 reserved_at_20[0x10]; 7632 u8 op_mod[0x10]; 7633 7634 u8 reserved_at_40[0x8]; 7635 u8 rmpn[0x18]; 7636 7637 u8 reserved_at_60[0x20]; 7638 }; 7639 7640 struct mlx5_ifc_destroy_qp_out_bits { 7641 u8 status[0x8]; 7642 u8 reserved_at_8[0x18]; 7643 7644 u8 syndrome[0x20]; 7645 7646 u8 reserved_at_40[0x40]; 7647 }; 7648 7649 struct mlx5_ifc_destroy_qp_in_bits { 7650 u8 opcode[0x10]; 7651 u8 uid[0x10]; 7652 7653 u8 reserved_at_20[0x10]; 7654 u8 op_mod[0x10]; 7655 7656 u8 reserved_at_40[0x8]; 7657 u8 qpn[0x18]; 7658 7659 u8 reserved_at_60[0x20]; 7660 }; 7661 7662 struct mlx5_ifc_destroy_psv_out_bits { 7663 u8 status[0x8]; 7664 u8 reserved_at_8[0x18]; 7665 7666 u8 syndrome[0x20]; 7667 7668 u8 reserved_at_40[0x40]; 7669 }; 7670 7671 struct mlx5_ifc_destroy_psv_in_bits { 7672 u8 opcode[0x10]; 7673 u8 reserved_at_10[0x10]; 7674 7675 u8 reserved_at_20[0x10]; 7676 u8 op_mod[0x10]; 7677 7678 u8 reserved_at_40[0x8]; 7679 u8 psvn[0x18]; 7680 7681 u8 reserved_at_60[0x20]; 7682 }; 7683 7684 struct mlx5_ifc_destroy_mkey_out_bits { 7685 u8 status[0x8]; 7686 u8 reserved_at_8[0x18]; 7687 7688 u8 syndrome[0x20]; 7689 7690 u8 reserved_at_40[0x40]; 7691 }; 7692 7693 struct mlx5_ifc_destroy_mkey_in_bits { 7694 u8 opcode[0x10]; 7695 u8 uid[0x10]; 7696 7697 u8 reserved_at_20[0x10]; 7698 u8 op_mod[0x10]; 7699 7700 u8 reserved_at_40[0x8]; 7701 u8 mkey_index[0x18]; 7702 7703 u8 reserved_at_60[0x20]; 7704 }; 7705 7706 struct mlx5_ifc_destroy_flow_table_out_bits { 7707 u8 status[0x8]; 7708 u8 reserved_at_8[0x18]; 7709 7710 u8 syndrome[0x20]; 7711 7712 u8 reserved_at_40[0x40]; 7713 }; 7714 7715 struct mlx5_ifc_destroy_flow_table_in_bits { 7716 u8 opcode[0x10]; 7717 u8 reserved_at_10[0x10]; 7718 7719 u8 reserved_at_20[0x10]; 7720 u8 op_mod[0x10]; 7721 7722 u8 other_vport[0x1]; 7723 u8 reserved_at_41[0xf]; 7724 u8 vport_number[0x10]; 7725 7726 u8 reserved_at_60[0x20]; 7727 7728 u8 table_type[0x8]; 7729 u8 reserved_at_88[0x18]; 7730 7731 u8 reserved_at_a0[0x8]; 7732 u8 table_id[0x18]; 7733 7734 u8 reserved_at_c0[0x140]; 7735 }; 7736 7737 struct mlx5_ifc_destroy_flow_group_out_bits { 7738 u8 status[0x8]; 7739 u8 reserved_at_8[0x18]; 7740 7741 u8 syndrome[0x20]; 7742 7743 u8 reserved_at_40[0x40]; 7744 }; 7745 7746 struct mlx5_ifc_destroy_flow_group_in_bits { 7747 u8 opcode[0x10]; 7748 u8 reserved_at_10[0x10]; 7749 7750 u8 reserved_at_20[0x10]; 7751 u8 op_mod[0x10]; 7752 7753 u8 other_vport[0x1]; 7754 u8 reserved_at_41[0xf]; 7755 u8 vport_number[0x10]; 7756 7757 u8 reserved_at_60[0x20]; 7758 7759 u8 table_type[0x8]; 7760 u8 reserved_at_88[0x18]; 7761 7762 u8 reserved_at_a0[0x8]; 7763 u8 table_id[0x18]; 7764 7765 u8 group_id[0x20]; 7766 7767 u8 reserved_at_e0[0x120]; 7768 }; 7769 7770 struct mlx5_ifc_destroy_eq_out_bits { 7771 u8 status[0x8]; 7772 u8 reserved_at_8[0x18]; 7773 7774 u8 syndrome[0x20]; 7775 7776 u8 reserved_at_40[0x40]; 7777 }; 7778 7779 struct mlx5_ifc_destroy_eq_in_bits { 7780 u8 opcode[0x10]; 7781 u8 reserved_at_10[0x10]; 7782 7783 u8 reserved_at_20[0x10]; 7784 u8 op_mod[0x10]; 7785 7786 u8 reserved_at_40[0x18]; 7787 u8 eq_number[0x8]; 7788 7789 u8 reserved_at_60[0x20]; 7790 }; 7791 7792 struct mlx5_ifc_destroy_dct_out_bits { 7793 u8 status[0x8]; 7794 u8 reserved_at_8[0x18]; 7795 7796 u8 syndrome[0x20]; 7797 7798 u8 reserved_at_40[0x40]; 7799 }; 7800 7801 struct mlx5_ifc_destroy_dct_in_bits { 7802 u8 opcode[0x10]; 7803 u8 uid[0x10]; 7804 7805 u8 reserved_at_20[0x10]; 7806 u8 op_mod[0x10]; 7807 7808 u8 reserved_at_40[0x8]; 7809 u8 dctn[0x18]; 7810 7811 u8 reserved_at_60[0x20]; 7812 }; 7813 7814 struct mlx5_ifc_destroy_cq_out_bits { 7815 u8 status[0x8]; 7816 u8 reserved_at_8[0x18]; 7817 7818 u8 syndrome[0x20]; 7819 7820 u8 reserved_at_40[0x40]; 7821 }; 7822 7823 struct mlx5_ifc_destroy_cq_in_bits { 7824 u8 opcode[0x10]; 7825 u8 uid[0x10]; 7826 7827 u8 reserved_at_20[0x10]; 7828 u8 op_mod[0x10]; 7829 7830 u8 reserved_at_40[0x8]; 7831 u8 cqn[0x18]; 7832 7833 u8 reserved_at_60[0x20]; 7834 }; 7835 7836 struct mlx5_ifc_delete_vxlan_udp_dport_out_bits { 7837 u8 status[0x8]; 7838 u8 reserved_at_8[0x18]; 7839 7840 u8 syndrome[0x20]; 7841 7842 u8 reserved_at_40[0x40]; 7843 }; 7844 7845 struct mlx5_ifc_delete_vxlan_udp_dport_in_bits { 7846 u8 opcode[0x10]; 7847 u8 reserved_at_10[0x10]; 7848 7849 u8 reserved_at_20[0x10]; 7850 u8 op_mod[0x10]; 7851 7852 u8 reserved_at_40[0x20]; 7853 7854 u8 reserved_at_60[0x10]; 7855 u8 vxlan_udp_port[0x10]; 7856 }; 7857 7858 struct mlx5_ifc_delete_l2_table_entry_out_bits { 7859 u8 status[0x8]; 7860 u8 reserved_at_8[0x18]; 7861 7862 u8 syndrome[0x20]; 7863 7864 u8 reserved_at_40[0x40]; 7865 }; 7866 7867 struct mlx5_ifc_delete_l2_table_entry_in_bits { 7868 u8 opcode[0x10]; 7869 u8 reserved_at_10[0x10]; 7870 7871 u8 reserved_at_20[0x10]; 7872 u8 op_mod[0x10]; 7873 7874 u8 reserved_at_40[0x60]; 7875 7876 u8 reserved_at_a0[0x8]; 7877 u8 table_index[0x18]; 7878 7879 u8 reserved_at_c0[0x140]; 7880 }; 7881 7882 struct mlx5_ifc_delete_fte_out_bits { 7883 u8 status[0x8]; 7884 u8 reserved_at_8[0x18]; 7885 7886 u8 syndrome[0x20]; 7887 7888 u8 reserved_at_40[0x40]; 7889 }; 7890 7891 struct mlx5_ifc_delete_fte_in_bits { 7892 u8 opcode[0x10]; 7893 u8 reserved_at_10[0x10]; 7894 7895 u8 reserved_at_20[0x10]; 7896 u8 op_mod[0x10]; 7897 7898 u8 other_vport[0x1]; 7899 u8 reserved_at_41[0xf]; 7900 u8 vport_number[0x10]; 7901 7902 u8 reserved_at_60[0x20]; 7903 7904 u8 table_type[0x8]; 7905 u8 reserved_at_88[0x18]; 7906 7907 u8 reserved_at_a0[0x8]; 7908 u8 table_id[0x18]; 7909 7910 u8 reserved_at_c0[0x40]; 7911 7912 u8 flow_index[0x20]; 7913 7914 u8 reserved_at_120[0xe0]; 7915 }; 7916 7917 struct mlx5_ifc_dealloc_xrcd_out_bits { 7918 u8 status[0x8]; 7919 u8 reserved_at_8[0x18]; 7920 7921 u8 syndrome[0x20]; 7922 7923 u8 reserved_at_40[0x40]; 7924 }; 7925 7926 struct mlx5_ifc_dealloc_xrcd_in_bits { 7927 u8 opcode[0x10]; 7928 u8 uid[0x10]; 7929 7930 u8 reserved_at_20[0x10]; 7931 u8 op_mod[0x10]; 7932 7933 u8 reserved_at_40[0x8]; 7934 u8 xrcd[0x18]; 7935 7936 u8 reserved_at_60[0x20]; 7937 }; 7938 7939 struct mlx5_ifc_dealloc_uar_out_bits { 7940 u8 status[0x8]; 7941 u8 reserved_at_8[0x18]; 7942 7943 u8 syndrome[0x20]; 7944 7945 u8 reserved_at_40[0x40]; 7946 }; 7947 7948 struct mlx5_ifc_dealloc_uar_in_bits { 7949 u8 opcode[0x10]; 7950 u8 uid[0x10]; 7951 7952 u8 reserved_at_20[0x10]; 7953 u8 op_mod[0x10]; 7954 7955 u8 reserved_at_40[0x8]; 7956 u8 uar[0x18]; 7957 7958 u8 reserved_at_60[0x20]; 7959 }; 7960 7961 struct mlx5_ifc_dealloc_transport_domain_out_bits { 7962 u8 status[0x8]; 7963 u8 reserved_at_8[0x18]; 7964 7965 u8 syndrome[0x20]; 7966 7967 u8 reserved_at_40[0x40]; 7968 }; 7969 7970 struct mlx5_ifc_dealloc_transport_domain_in_bits { 7971 u8 opcode[0x10]; 7972 u8 uid[0x10]; 7973 7974 u8 reserved_at_20[0x10]; 7975 u8 op_mod[0x10]; 7976 7977 u8 reserved_at_40[0x8]; 7978 u8 transport_domain[0x18]; 7979 7980 u8 reserved_at_60[0x20]; 7981 }; 7982 7983 struct mlx5_ifc_dealloc_q_counter_out_bits { 7984 u8 status[0x8]; 7985 u8 reserved_at_8[0x18]; 7986 7987 u8 syndrome[0x20]; 7988 7989 u8 reserved_at_40[0x40]; 7990 }; 7991 7992 struct mlx5_ifc_dealloc_q_counter_in_bits { 7993 u8 opcode[0x10]; 7994 u8 reserved_at_10[0x10]; 7995 7996 u8 reserved_at_20[0x10]; 7997 u8 op_mod[0x10]; 7998 7999 u8 reserved_at_40[0x18]; 8000 u8 counter_set_id[0x8]; 8001 8002 u8 reserved_at_60[0x20]; 8003 }; 8004 8005 struct mlx5_ifc_dealloc_pd_out_bits { 8006 u8 status[0x8]; 8007 u8 reserved_at_8[0x18]; 8008 8009 u8 syndrome[0x20]; 8010 8011 u8 reserved_at_40[0x40]; 8012 }; 8013 8014 struct mlx5_ifc_dealloc_pd_in_bits { 8015 u8 opcode[0x10]; 8016 u8 uid[0x10]; 8017 8018 u8 reserved_at_20[0x10]; 8019 u8 op_mod[0x10]; 8020 8021 u8 reserved_at_40[0x8]; 8022 u8 pd[0x18]; 8023 8024 u8 reserved_at_60[0x20]; 8025 }; 8026 8027 struct mlx5_ifc_dealloc_flow_counter_out_bits { 8028 u8 status[0x8]; 8029 u8 reserved_at_8[0x18]; 8030 8031 u8 syndrome[0x20]; 8032 8033 u8 reserved_at_40[0x40]; 8034 }; 8035 8036 struct mlx5_ifc_dealloc_flow_counter_in_bits { 8037 u8 opcode[0x10]; 8038 u8 reserved_at_10[0x10]; 8039 8040 u8 reserved_at_20[0x10]; 8041 u8 op_mod[0x10]; 8042 8043 u8 flow_counter_id[0x20]; 8044 8045 u8 reserved_at_60[0x20]; 8046 }; 8047 8048 struct mlx5_ifc_create_xrq_out_bits { 8049 u8 status[0x8]; 8050 u8 reserved_at_8[0x18]; 8051 8052 u8 syndrome[0x20]; 8053 8054 u8 reserved_at_40[0x8]; 8055 u8 xrqn[0x18]; 8056 8057 u8 reserved_at_60[0x20]; 8058 }; 8059 8060 struct mlx5_ifc_create_xrq_in_bits { 8061 u8 opcode[0x10]; 8062 u8 uid[0x10]; 8063 8064 u8 reserved_at_20[0x10]; 8065 u8 op_mod[0x10]; 8066 8067 u8 reserved_at_40[0x40]; 8068 8069 struct mlx5_ifc_xrqc_bits xrq_context; 8070 }; 8071 8072 struct mlx5_ifc_create_xrc_srq_out_bits { 8073 u8 status[0x8]; 8074 u8 reserved_at_8[0x18]; 8075 8076 u8 syndrome[0x20]; 8077 8078 u8 reserved_at_40[0x8]; 8079 u8 xrc_srqn[0x18]; 8080 8081 u8 reserved_at_60[0x20]; 8082 }; 8083 8084 struct mlx5_ifc_create_xrc_srq_in_bits { 8085 u8 opcode[0x10]; 8086 u8 uid[0x10]; 8087 8088 u8 reserved_at_20[0x10]; 8089 u8 op_mod[0x10]; 8090 8091 u8 reserved_at_40[0x40]; 8092 8093 struct mlx5_ifc_xrc_srqc_bits xrc_srq_context_entry; 8094 8095 u8 reserved_at_280[0x60]; 8096 8097 u8 xrc_srq_umem_valid[0x1]; 8098 u8 reserved_at_2e1[0x1f]; 8099 8100 u8 reserved_at_300[0x580]; 8101 8102 u8 pas[][0x40]; 8103 }; 8104 8105 struct mlx5_ifc_create_tis_out_bits { 8106 u8 status[0x8]; 8107 u8 reserved_at_8[0x18]; 8108 8109 u8 syndrome[0x20]; 8110 8111 u8 reserved_at_40[0x8]; 8112 u8 tisn[0x18]; 8113 8114 u8 reserved_at_60[0x20]; 8115 }; 8116 8117 struct mlx5_ifc_create_tis_in_bits { 8118 u8 opcode[0x10]; 8119 u8 uid[0x10]; 8120 8121 u8 reserved_at_20[0x10]; 8122 u8 op_mod[0x10]; 8123 8124 u8 reserved_at_40[0xc0]; 8125 8126 struct mlx5_ifc_tisc_bits ctx; 8127 }; 8128 8129 struct mlx5_ifc_create_tir_out_bits { 8130 u8 status[0x8]; 8131 u8 icm_address_63_40[0x18]; 8132 8133 u8 syndrome[0x20]; 8134 8135 u8 icm_address_39_32[0x8]; 8136 u8 tirn[0x18]; 8137 8138 u8 icm_address_31_0[0x20]; 8139 }; 8140 8141 struct mlx5_ifc_create_tir_in_bits { 8142 u8 opcode[0x10]; 8143 u8 uid[0x10]; 8144 8145 u8 reserved_at_20[0x10]; 8146 u8 op_mod[0x10]; 8147 8148 u8 reserved_at_40[0xc0]; 8149 8150 struct mlx5_ifc_tirc_bits ctx; 8151 }; 8152 8153 struct mlx5_ifc_create_srq_out_bits { 8154 u8 status[0x8]; 8155 u8 reserved_at_8[0x18]; 8156 8157 u8 syndrome[0x20]; 8158 8159 u8 reserved_at_40[0x8]; 8160 u8 srqn[0x18]; 8161 8162 u8 reserved_at_60[0x20]; 8163 }; 8164 8165 struct mlx5_ifc_create_srq_in_bits { 8166 u8 opcode[0x10]; 8167 u8 uid[0x10]; 8168 8169 u8 reserved_at_20[0x10]; 8170 u8 op_mod[0x10]; 8171 8172 u8 reserved_at_40[0x40]; 8173 8174 struct mlx5_ifc_srqc_bits srq_context_entry; 8175 8176 u8 reserved_at_280[0x600]; 8177 8178 u8 pas[][0x40]; 8179 }; 8180 8181 struct mlx5_ifc_create_sq_out_bits { 8182 u8 status[0x8]; 8183 u8 reserved_at_8[0x18]; 8184 8185 u8 syndrome[0x20]; 8186 8187 u8 reserved_at_40[0x8]; 8188 u8 sqn[0x18]; 8189 8190 u8 reserved_at_60[0x20]; 8191 }; 8192 8193 struct mlx5_ifc_create_sq_in_bits { 8194 u8 opcode[0x10]; 8195 u8 uid[0x10]; 8196 8197 u8 reserved_at_20[0x10]; 8198 u8 op_mod[0x10]; 8199 8200 u8 reserved_at_40[0xc0]; 8201 8202 struct mlx5_ifc_sqc_bits ctx; 8203 }; 8204 8205 struct mlx5_ifc_create_scheduling_element_out_bits { 8206 u8 status[0x8]; 8207 u8 reserved_at_8[0x18]; 8208 8209 u8 syndrome[0x20]; 8210 8211 u8 reserved_at_40[0x40]; 8212 8213 u8 scheduling_element_id[0x20]; 8214 8215 u8 reserved_at_a0[0x160]; 8216 }; 8217 8218 struct mlx5_ifc_create_scheduling_element_in_bits { 8219 u8 opcode[0x10]; 8220 u8 reserved_at_10[0x10]; 8221 8222 u8 reserved_at_20[0x10]; 8223 u8 op_mod[0x10]; 8224 8225 u8 scheduling_hierarchy[0x8]; 8226 u8 reserved_at_48[0x18]; 8227 8228 u8 reserved_at_60[0xa0]; 8229 8230 struct mlx5_ifc_scheduling_context_bits scheduling_context; 8231 8232 u8 reserved_at_300[0x100]; 8233 }; 8234 8235 struct mlx5_ifc_create_rqt_out_bits { 8236 u8 status[0x8]; 8237 u8 reserved_at_8[0x18]; 8238 8239 u8 syndrome[0x20]; 8240 8241 u8 reserved_at_40[0x8]; 8242 u8 rqtn[0x18]; 8243 8244 u8 reserved_at_60[0x20]; 8245 }; 8246 8247 struct mlx5_ifc_create_rqt_in_bits { 8248 u8 opcode[0x10]; 8249 u8 uid[0x10]; 8250 8251 u8 reserved_at_20[0x10]; 8252 u8 op_mod[0x10]; 8253 8254 u8 reserved_at_40[0xc0]; 8255 8256 struct mlx5_ifc_rqtc_bits rqt_context; 8257 }; 8258 8259 struct mlx5_ifc_create_rq_out_bits { 8260 u8 status[0x8]; 8261 u8 reserved_at_8[0x18]; 8262 8263 u8 syndrome[0x20]; 8264 8265 u8 reserved_at_40[0x8]; 8266 u8 rqn[0x18]; 8267 8268 u8 reserved_at_60[0x20]; 8269 }; 8270 8271 struct mlx5_ifc_create_rq_in_bits { 8272 u8 opcode[0x10]; 8273 u8 uid[0x10]; 8274 8275 u8 reserved_at_20[0x10]; 8276 u8 op_mod[0x10]; 8277 8278 u8 reserved_at_40[0xc0]; 8279 8280 struct mlx5_ifc_rqc_bits ctx; 8281 }; 8282 8283 struct mlx5_ifc_create_rmp_out_bits { 8284 u8 status[0x8]; 8285 u8 reserved_at_8[0x18]; 8286 8287 u8 syndrome[0x20]; 8288 8289 u8 reserved_at_40[0x8]; 8290 u8 rmpn[0x18]; 8291 8292 u8 reserved_at_60[0x20]; 8293 }; 8294 8295 struct mlx5_ifc_create_rmp_in_bits { 8296 u8 opcode[0x10]; 8297 u8 uid[0x10]; 8298 8299 u8 reserved_at_20[0x10]; 8300 u8 op_mod[0x10]; 8301 8302 u8 reserved_at_40[0xc0]; 8303 8304 struct mlx5_ifc_rmpc_bits ctx; 8305 }; 8306 8307 struct mlx5_ifc_create_qp_out_bits { 8308 u8 status[0x8]; 8309 u8 reserved_at_8[0x18]; 8310 8311 u8 syndrome[0x20]; 8312 8313 u8 reserved_at_40[0x8]; 8314 u8 qpn[0x18]; 8315 8316 u8 ece[0x20]; 8317 }; 8318 8319 struct mlx5_ifc_create_qp_in_bits { 8320 u8 opcode[0x10]; 8321 u8 uid[0x10]; 8322 8323 u8 reserved_at_20[0x10]; 8324 u8 op_mod[0x10]; 8325 8326 u8 reserved_at_40[0x8]; 8327 u8 input_qpn[0x18]; 8328 8329 u8 reserved_at_60[0x20]; 8330 u8 opt_param_mask[0x20]; 8331 8332 u8 ece[0x20]; 8333 8334 struct mlx5_ifc_qpc_bits qpc; 8335 8336 u8 reserved_at_800[0x60]; 8337 8338 u8 wq_umem_valid[0x1]; 8339 u8 reserved_at_861[0x1f]; 8340 8341 u8 pas[][0x40]; 8342 }; 8343 8344 struct mlx5_ifc_create_psv_out_bits { 8345 u8 status[0x8]; 8346 u8 reserved_at_8[0x18]; 8347 8348 u8 syndrome[0x20]; 8349 8350 u8 reserved_at_40[0x40]; 8351 8352 u8 reserved_at_80[0x8]; 8353 u8 psv0_index[0x18]; 8354 8355 u8 reserved_at_a0[0x8]; 8356 u8 psv1_index[0x18]; 8357 8358 u8 reserved_at_c0[0x8]; 8359 u8 psv2_index[0x18]; 8360 8361 u8 reserved_at_e0[0x8]; 8362 u8 psv3_index[0x18]; 8363 }; 8364 8365 struct mlx5_ifc_create_psv_in_bits { 8366 u8 opcode[0x10]; 8367 u8 reserved_at_10[0x10]; 8368 8369 u8 reserved_at_20[0x10]; 8370 u8 op_mod[0x10]; 8371 8372 u8 num_psv[0x4]; 8373 u8 reserved_at_44[0x4]; 8374 u8 pd[0x18]; 8375 8376 u8 reserved_at_60[0x20]; 8377 }; 8378 8379 struct mlx5_ifc_create_mkey_out_bits { 8380 u8 status[0x8]; 8381 u8 reserved_at_8[0x18]; 8382 8383 u8 syndrome[0x20]; 8384 8385 u8 reserved_at_40[0x8]; 8386 u8 mkey_index[0x18]; 8387 8388 u8 reserved_at_60[0x20]; 8389 }; 8390 8391 struct mlx5_ifc_create_mkey_in_bits { 8392 u8 opcode[0x10]; 8393 u8 uid[0x10]; 8394 8395 u8 reserved_at_20[0x10]; 8396 u8 op_mod[0x10]; 8397 8398 u8 reserved_at_40[0x20]; 8399 8400 u8 pg_access[0x1]; 8401 u8 mkey_umem_valid[0x1]; 8402 u8 reserved_at_62[0x1e]; 8403 8404 struct mlx5_ifc_mkc_bits memory_key_mkey_entry; 8405 8406 u8 reserved_at_280[0x80]; 8407 8408 u8 translations_octword_actual_size[0x20]; 8409 8410 u8 reserved_at_320[0x560]; 8411 8412 u8 klm_pas_mtt[][0x20]; 8413 }; 8414 8415 enum { 8416 MLX5_FLOW_TABLE_TYPE_NIC_RX = 0x0, 8417 MLX5_FLOW_TABLE_TYPE_NIC_TX = 0x1, 8418 MLX5_FLOW_TABLE_TYPE_ESW_EGRESS_ACL = 0x2, 8419 MLX5_FLOW_TABLE_TYPE_ESW_INGRESS_ACL = 0x3, 8420 MLX5_FLOW_TABLE_TYPE_FDB = 0X4, 8421 MLX5_FLOW_TABLE_TYPE_SNIFFER_RX = 0X5, 8422 MLX5_FLOW_TABLE_TYPE_SNIFFER_TX = 0X6, 8423 }; 8424 8425 struct mlx5_ifc_create_flow_table_out_bits { 8426 u8 status[0x8]; 8427 u8 icm_address_63_40[0x18]; 8428 8429 u8 syndrome[0x20]; 8430 8431 u8 icm_address_39_32[0x8]; 8432 u8 table_id[0x18]; 8433 8434 u8 icm_address_31_0[0x20]; 8435 }; 8436 8437 struct mlx5_ifc_create_flow_table_in_bits { 8438 u8 opcode[0x10]; 8439 u8 reserved_at_10[0x10]; 8440 8441 u8 reserved_at_20[0x10]; 8442 u8 op_mod[0x10]; 8443 8444 u8 other_vport[0x1]; 8445 u8 reserved_at_41[0xf]; 8446 u8 vport_number[0x10]; 8447 8448 u8 reserved_at_60[0x20]; 8449 8450 u8 table_type[0x8]; 8451 u8 reserved_at_88[0x18]; 8452 8453 u8 reserved_at_a0[0x20]; 8454 8455 struct mlx5_ifc_flow_table_context_bits flow_table_context; 8456 }; 8457 8458 struct mlx5_ifc_create_flow_group_out_bits { 8459 u8 status[0x8]; 8460 u8 reserved_at_8[0x18]; 8461 8462 u8 syndrome[0x20]; 8463 8464 u8 reserved_at_40[0x8]; 8465 u8 group_id[0x18]; 8466 8467 u8 reserved_at_60[0x20]; 8468 }; 8469 8470 enum { 8471 MLX5_CREATE_FLOW_GROUP_IN_GROUP_TYPE_TCAM_SUBTABLE = 0x0, 8472 MLX5_CREATE_FLOW_GROUP_IN_GROUP_TYPE_HASH_SPLIT = 0x1, 8473 }; 8474 8475 enum { 8476 MLX5_CREATE_FLOW_GROUP_IN_MATCH_CRITERIA_ENABLE_OUTER_HEADERS = 0x0, 8477 MLX5_CREATE_FLOW_GROUP_IN_MATCH_CRITERIA_ENABLE_MISC_PARAMETERS = 0x1, 8478 MLX5_CREATE_FLOW_GROUP_IN_MATCH_CRITERIA_ENABLE_INNER_HEADERS = 0x2, 8479 MLX5_CREATE_FLOW_GROUP_IN_MATCH_CRITERIA_ENABLE_MISC_PARAMETERS_2 = 0x3, 8480 }; 8481 8482 struct mlx5_ifc_create_flow_group_in_bits { 8483 u8 opcode[0x10]; 8484 u8 reserved_at_10[0x10]; 8485 8486 u8 reserved_at_20[0x10]; 8487 u8 op_mod[0x10]; 8488 8489 u8 other_vport[0x1]; 8490 u8 reserved_at_41[0xf]; 8491 u8 vport_number[0x10]; 8492 8493 u8 reserved_at_60[0x20]; 8494 8495 u8 table_type[0x8]; 8496 u8 reserved_at_88[0x4]; 8497 u8 group_type[0x4]; 8498 u8 reserved_at_90[0x10]; 8499 8500 u8 reserved_at_a0[0x8]; 8501 u8 table_id[0x18]; 8502 8503 u8 source_eswitch_owner_vhca_id_valid[0x1]; 8504 8505 u8 reserved_at_c1[0x1f]; 8506 8507 u8 start_flow_index[0x20]; 8508 8509 u8 reserved_at_100[0x20]; 8510 8511 u8 end_flow_index[0x20]; 8512 8513 u8 reserved_at_140[0x10]; 8514 u8 match_definer_id[0x10]; 8515 8516 u8 reserved_at_160[0x80]; 8517 8518 u8 reserved_at_1e0[0x18]; 8519 u8 match_criteria_enable[0x8]; 8520 8521 struct mlx5_ifc_fte_match_param_bits match_criteria; 8522 8523 u8 reserved_at_1200[0xe00]; 8524 }; 8525 8526 struct mlx5_ifc_create_eq_out_bits { 8527 u8 status[0x8]; 8528 u8 reserved_at_8[0x18]; 8529 8530 u8 syndrome[0x20]; 8531 8532 u8 reserved_at_40[0x18]; 8533 u8 eq_number[0x8]; 8534 8535 u8 reserved_at_60[0x20]; 8536 }; 8537 8538 struct mlx5_ifc_create_eq_in_bits { 8539 u8 opcode[0x10]; 8540 u8 uid[0x10]; 8541 8542 u8 reserved_at_20[0x10]; 8543 u8 op_mod[0x10]; 8544 8545 u8 reserved_at_40[0x40]; 8546 8547 struct mlx5_ifc_eqc_bits eq_context_entry; 8548 8549 u8 reserved_at_280[0x40]; 8550 8551 u8 event_bitmask[4][0x40]; 8552 8553 u8 reserved_at_3c0[0x4c0]; 8554 8555 u8 pas[][0x40]; 8556 }; 8557 8558 struct mlx5_ifc_create_dct_out_bits { 8559 u8 status[0x8]; 8560 u8 reserved_at_8[0x18]; 8561 8562 u8 syndrome[0x20]; 8563 8564 u8 reserved_at_40[0x8]; 8565 u8 dctn[0x18]; 8566 8567 u8 ece[0x20]; 8568 }; 8569 8570 struct mlx5_ifc_create_dct_in_bits { 8571 u8 opcode[0x10]; 8572 u8 uid[0x10]; 8573 8574 u8 reserved_at_20[0x10]; 8575 u8 op_mod[0x10]; 8576 8577 u8 reserved_at_40[0x40]; 8578 8579 struct mlx5_ifc_dctc_bits dct_context_entry; 8580 8581 u8 reserved_at_280[0x180]; 8582 }; 8583 8584 struct mlx5_ifc_create_cq_out_bits { 8585 u8 status[0x8]; 8586 u8 reserved_at_8[0x18]; 8587 8588 u8 syndrome[0x20]; 8589 8590 u8 reserved_at_40[0x8]; 8591 u8 cqn[0x18]; 8592 8593 u8 reserved_at_60[0x20]; 8594 }; 8595 8596 struct mlx5_ifc_create_cq_in_bits { 8597 u8 opcode[0x10]; 8598 u8 uid[0x10]; 8599 8600 u8 reserved_at_20[0x10]; 8601 u8 op_mod[0x10]; 8602 8603 u8 reserved_at_40[0x40]; 8604 8605 struct mlx5_ifc_cqc_bits cq_context; 8606 8607 u8 reserved_at_280[0x60]; 8608 8609 u8 cq_umem_valid[0x1]; 8610 u8 reserved_at_2e1[0x59f]; 8611 8612 u8 pas[][0x40]; 8613 }; 8614 8615 struct mlx5_ifc_config_int_moderation_out_bits { 8616 u8 status[0x8]; 8617 u8 reserved_at_8[0x18]; 8618 8619 u8 syndrome[0x20]; 8620 8621 u8 reserved_at_40[0x4]; 8622 u8 min_delay[0xc]; 8623 u8 int_vector[0x10]; 8624 8625 u8 reserved_at_60[0x20]; 8626 }; 8627 8628 enum { 8629 MLX5_CONFIG_INT_MODERATION_IN_OP_MOD_WRITE = 0x0, 8630 MLX5_CONFIG_INT_MODERATION_IN_OP_MOD_READ = 0x1, 8631 }; 8632 8633 struct mlx5_ifc_config_int_moderation_in_bits { 8634 u8 opcode[0x10]; 8635 u8 reserved_at_10[0x10]; 8636 8637 u8 reserved_at_20[0x10]; 8638 u8 op_mod[0x10]; 8639 8640 u8 reserved_at_40[0x4]; 8641 u8 min_delay[0xc]; 8642 u8 int_vector[0x10]; 8643 8644 u8 reserved_at_60[0x20]; 8645 }; 8646 8647 struct mlx5_ifc_attach_to_mcg_out_bits { 8648 u8 status[0x8]; 8649 u8 reserved_at_8[0x18]; 8650 8651 u8 syndrome[0x20]; 8652 8653 u8 reserved_at_40[0x40]; 8654 }; 8655 8656 struct mlx5_ifc_attach_to_mcg_in_bits { 8657 u8 opcode[0x10]; 8658 u8 uid[0x10]; 8659 8660 u8 reserved_at_20[0x10]; 8661 u8 op_mod[0x10]; 8662 8663 u8 reserved_at_40[0x8]; 8664 u8 qpn[0x18]; 8665 8666 u8 reserved_at_60[0x20]; 8667 8668 u8 multicast_gid[16][0x8]; 8669 }; 8670 8671 struct mlx5_ifc_arm_xrq_out_bits { 8672 u8 status[0x8]; 8673 u8 reserved_at_8[0x18]; 8674 8675 u8 syndrome[0x20]; 8676 8677 u8 reserved_at_40[0x40]; 8678 }; 8679 8680 struct mlx5_ifc_arm_xrq_in_bits { 8681 u8 opcode[0x10]; 8682 u8 reserved_at_10[0x10]; 8683 8684 u8 reserved_at_20[0x10]; 8685 u8 op_mod[0x10]; 8686 8687 u8 reserved_at_40[0x8]; 8688 u8 xrqn[0x18]; 8689 8690 u8 reserved_at_60[0x10]; 8691 u8 lwm[0x10]; 8692 }; 8693 8694 struct mlx5_ifc_arm_xrc_srq_out_bits { 8695 u8 status[0x8]; 8696 u8 reserved_at_8[0x18]; 8697 8698 u8 syndrome[0x20]; 8699 8700 u8 reserved_at_40[0x40]; 8701 }; 8702 8703 enum { 8704 MLX5_ARM_XRC_SRQ_IN_OP_MOD_XRC_SRQ = 0x1, 8705 }; 8706 8707 struct mlx5_ifc_arm_xrc_srq_in_bits { 8708 u8 opcode[0x10]; 8709 u8 uid[0x10]; 8710 8711 u8 reserved_at_20[0x10]; 8712 u8 op_mod[0x10]; 8713 8714 u8 reserved_at_40[0x8]; 8715 u8 xrc_srqn[0x18]; 8716 8717 u8 reserved_at_60[0x10]; 8718 u8 lwm[0x10]; 8719 }; 8720 8721 struct mlx5_ifc_arm_rq_out_bits { 8722 u8 status[0x8]; 8723 u8 reserved_at_8[0x18]; 8724 8725 u8 syndrome[0x20]; 8726 8727 u8 reserved_at_40[0x40]; 8728 }; 8729 8730 enum { 8731 MLX5_ARM_RQ_IN_OP_MOD_SRQ = 0x1, 8732 MLX5_ARM_RQ_IN_OP_MOD_XRQ = 0x2, 8733 }; 8734 8735 struct mlx5_ifc_arm_rq_in_bits { 8736 u8 opcode[0x10]; 8737 u8 uid[0x10]; 8738 8739 u8 reserved_at_20[0x10]; 8740 u8 op_mod[0x10]; 8741 8742 u8 reserved_at_40[0x8]; 8743 u8 srq_number[0x18]; 8744 8745 u8 reserved_at_60[0x10]; 8746 u8 lwm[0x10]; 8747 }; 8748 8749 struct mlx5_ifc_arm_dct_out_bits { 8750 u8 status[0x8]; 8751 u8 reserved_at_8[0x18]; 8752 8753 u8 syndrome[0x20]; 8754 8755 u8 reserved_at_40[0x40]; 8756 }; 8757 8758 struct mlx5_ifc_arm_dct_in_bits { 8759 u8 opcode[0x10]; 8760 u8 reserved_at_10[0x10]; 8761 8762 u8 reserved_at_20[0x10]; 8763 u8 op_mod[0x10]; 8764 8765 u8 reserved_at_40[0x8]; 8766 u8 dct_number[0x18]; 8767 8768 u8 reserved_at_60[0x20]; 8769 }; 8770 8771 struct mlx5_ifc_alloc_xrcd_out_bits { 8772 u8 status[0x8]; 8773 u8 reserved_at_8[0x18]; 8774 8775 u8 syndrome[0x20]; 8776 8777 u8 reserved_at_40[0x8]; 8778 u8 xrcd[0x18]; 8779 8780 u8 reserved_at_60[0x20]; 8781 }; 8782 8783 struct mlx5_ifc_alloc_xrcd_in_bits { 8784 u8 opcode[0x10]; 8785 u8 uid[0x10]; 8786 8787 u8 reserved_at_20[0x10]; 8788 u8 op_mod[0x10]; 8789 8790 u8 reserved_at_40[0x40]; 8791 }; 8792 8793 struct mlx5_ifc_alloc_uar_out_bits { 8794 u8 status[0x8]; 8795 u8 reserved_at_8[0x18]; 8796 8797 u8 syndrome[0x20]; 8798 8799 u8 reserved_at_40[0x8]; 8800 u8 uar[0x18]; 8801 8802 u8 reserved_at_60[0x20]; 8803 }; 8804 8805 struct mlx5_ifc_alloc_uar_in_bits { 8806 u8 opcode[0x10]; 8807 u8 uid[0x10]; 8808 8809 u8 reserved_at_20[0x10]; 8810 u8 op_mod[0x10]; 8811 8812 u8 reserved_at_40[0x40]; 8813 }; 8814 8815 struct mlx5_ifc_alloc_transport_domain_out_bits { 8816 u8 status[0x8]; 8817 u8 reserved_at_8[0x18]; 8818 8819 u8 syndrome[0x20]; 8820 8821 u8 reserved_at_40[0x8]; 8822 u8 transport_domain[0x18]; 8823 8824 u8 reserved_at_60[0x20]; 8825 }; 8826 8827 struct mlx5_ifc_alloc_transport_domain_in_bits { 8828 u8 opcode[0x10]; 8829 u8 uid[0x10]; 8830 8831 u8 reserved_at_20[0x10]; 8832 u8 op_mod[0x10]; 8833 8834 u8 reserved_at_40[0x40]; 8835 }; 8836 8837 struct mlx5_ifc_alloc_q_counter_out_bits { 8838 u8 status[0x8]; 8839 u8 reserved_at_8[0x18]; 8840 8841 u8 syndrome[0x20]; 8842 8843 u8 reserved_at_40[0x18]; 8844 u8 counter_set_id[0x8]; 8845 8846 u8 reserved_at_60[0x20]; 8847 }; 8848 8849 struct mlx5_ifc_alloc_q_counter_in_bits { 8850 u8 opcode[0x10]; 8851 u8 uid[0x10]; 8852 8853 u8 reserved_at_20[0x10]; 8854 u8 op_mod[0x10]; 8855 8856 u8 reserved_at_40[0x40]; 8857 }; 8858 8859 struct mlx5_ifc_alloc_pd_out_bits { 8860 u8 status[0x8]; 8861 u8 reserved_at_8[0x18]; 8862 8863 u8 syndrome[0x20]; 8864 8865 u8 reserved_at_40[0x8]; 8866 u8 pd[0x18]; 8867 8868 u8 reserved_at_60[0x20]; 8869 }; 8870 8871 struct mlx5_ifc_alloc_pd_in_bits { 8872 u8 opcode[0x10]; 8873 u8 uid[0x10]; 8874 8875 u8 reserved_at_20[0x10]; 8876 u8 op_mod[0x10]; 8877 8878 u8 reserved_at_40[0x40]; 8879 }; 8880 8881 struct mlx5_ifc_alloc_flow_counter_out_bits { 8882 u8 status[0x8]; 8883 u8 reserved_at_8[0x18]; 8884 8885 u8 syndrome[0x20]; 8886 8887 u8 flow_counter_id[0x20]; 8888 8889 u8 reserved_at_60[0x20]; 8890 }; 8891 8892 struct mlx5_ifc_alloc_flow_counter_in_bits { 8893 u8 opcode[0x10]; 8894 u8 reserved_at_10[0x10]; 8895 8896 u8 reserved_at_20[0x10]; 8897 u8 op_mod[0x10]; 8898 8899 u8 reserved_at_40[0x38]; 8900 u8 flow_counter_bulk[0x8]; 8901 }; 8902 8903 struct mlx5_ifc_add_vxlan_udp_dport_out_bits { 8904 u8 status[0x8]; 8905 u8 reserved_at_8[0x18]; 8906 8907 u8 syndrome[0x20]; 8908 8909 u8 reserved_at_40[0x40]; 8910 }; 8911 8912 struct mlx5_ifc_add_vxlan_udp_dport_in_bits { 8913 u8 opcode[0x10]; 8914 u8 reserved_at_10[0x10]; 8915 8916 u8 reserved_at_20[0x10]; 8917 u8 op_mod[0x10]; 8918 8919 u8 reserved_at_40[0x20]; 8920 8921 u8 reserved_at_60[0x10]; 8922 u8 vxlan_udp_port[0x10]; 8923 }; 8924 8925 struct mlx5_ifc_set_pp_rate_limit_out_bits { 8926 u8 status[0x8]; 8927 u8 reserved_at_8[0x18]; 8928 8929 u8 syndrome[0x20]; 8930 8931 u8 reserved_at_40[0x40]; 8932 }; 8933 8934 struct mlx5_ifc_set_pp_rate_limit_context_bits { 8935 u8 rate_limit[0x20]; 8936 8937 u8 burst_upper_bound[0x20]; 8938 8939 u8 reserved_at_40[0x10]; 8940 u8 typical_packet_size[0x10]; 8941 8942 u8 reserved_at_60[0x120]; 8943 }; 8944 8945 struct mlx5_ifc_set_pp_rate_limit_in_bits { 8946 u8 opcode[0x10]; 8947 u8 uid[0x10]; 8948 8949 u8 reserved_at_20[0x10]; 8950 u8 op_mod[0x10]; 8951 8952 u8 reserved_at_40[0x10]; 8953 u8 rate_limit_index[0x10]; 8954 8955 u8 reserved_at_60[0x20]; 8956 8957 struct mlx5_ifc_set_pp_rate_limit_context_bits ctx; 8958 }; 8959 8960 struct mlx5_ifc_access_register_out_bits { 8961 u8 status[0x8]; 8962 u8 reserved_at_8[0x18]; 8963 8964 u8 syndrome[0x20]; 8965 8966 u8 reserved_at_40[0x40]; 8967 8968 u8 register_data[][0x20]; 8969 }; 8970 8971 enum { 8972 MLX5_ACCESS_REGISTER_IN_OP_MOD_WRITE = 0x0, 8973 MLX5_ACCESS_REGISTER_IN_OP_MOD_READ = 0x1, 8974 }; 8975 8976 struct mlx5_ifc_access_register_in_bits { 8977 u8 opcode[0x10]; 8978 u8 reserved_at_10[0x10]; 8979 8980 u8 reserved_at_20[0x10]; 8981 u8 op_mod[0x10]; 8982 8983 u8 reserved_at_40[0x10]; 8984 u8 register_id[0x10]; 8985 8986 u8 argument[0x20]; 8987 8988 u8 register_data[][0x20]; 8989 }; 8990 8991 struct mlx5_ifc_sltp_reg_bits { 8992 u8 status[0x4]; 8993 u8 version[0x4]; 8994 u8 local_port[0x8]; 8995 u8 pnat[0x2]; 8996 u8 reserved_at_12[0x2]; 8997 u8 lane[0x4]; 8998 u8 reserved_at_18[0x8]; 8999 9000 u8 reserved_at_20[0x20]; 9001 9002 u8 reserved_at_40[0x7]; 9003 u8 polarity[0x1]; 9004 u8 ob_tap0[0x8]; 9005 u8 ob_tap1[0x8]; 9006 u8 ob_tap2[0x8]; 9007 9008 u8 reserved_at_60[0xc]; 9009 u8 ob_preemp_mode[0x4]; 9010 u8 ob_reg[0x8]; 9011 u8 ob_bias[0x8]; 9012 9013 u8 reserved_at_80[0x20]; 9014 }; 9015 9016 struct mlx5_ifc_slrg_reg_bits { 9017 u8 status[0x4]; 9018 u8 version[0x4]; 9019 u8 local_port[0x8]; 9020 u8 pnat[0x2]; 9021 u8 reserved_at_12[0x2]; 9022 u8 lane[0x4]; 9023 u8 reserved_at_18[0x8]; 9024 9025 u8 time_to_link_up[0x10]; 9026 u8 reserved_at_30[0xc]; 9027 u8 grade_lane_speed[0x4]; 9028 9029 u8 grade_version[0x8]; 9030 u8 grade[0x18]; 9031 9032 u8 reserved_at_60[0x4]; 9033 u8 height_grade_type[0x4]; 9034 u8 height_grade[0x18]; 9035 9036 u8 height_dz[0x10]; 9037 u8 height_dv[0x10]; 9038 9039 u8 reserved_at_a0[0x10]; 9040 u8 height_sigma[0x10]; 9041 9042 u8 reserved_at_c0[0x20]; 9043 9044 u8 reserved_at_e0[0x4]; 9045 u8 phase_grade_type[0x4]; 9046 u8 phase_grade[0x18]; 9047 9048 u8 reserved_at_100[0x8]; 9049 u8 phase_eo_pos[0x8]; 9050 u8 reserved_at_110[0x8]; 9051 u8 phase_eo_neg[0x8]; 9052 9053 u8 ffe_set_tested[0x10]; 9054 u8 test_errors_per_lane[0x10]; 9055 }; 9056 9057 struct mlx5_ifc_pvlc_reg_bits { 9058 u8 reserved_at_0[0x8]; 9059 u8 local_port[0x8]; 9060 u8 reserved_at_10[0x10]; 9061 9062 u8 reserved_at_20[0x1c]; 9063 u8 vl_hw_cap[0x4]; 9064 9065 u8 reserved_at_40[0x1c]; 9066 u8 vl_admin[0x4]; 9067 9068 u8 reserved_at_60[0x1c]; 9069 u8 vl_operational[0x4]; 9070 }; 9071 9072 struct mlx5_ifc_pude_reg_bits { 9073 u8 swid[0x8]; 9074 u8 local_port[0x8]; 9075 u8 reserved_at_10[0x4]; 9076 u8 admin_status[0x4]; 9077 u8 reserved_at_18[0x4]; 9078 u8 oper_status[0x4]; 9079 9080 u8 reserved_at_20[0x60]; 9081 }; 9082 9083 struct mlx5_ifc_ptys_reg_bits { 9084 u8 reserved_at_0[0x1]; 9085 u8 an_disable_admin[0x1]; 9086 u8 an_disable_cap[0x1]; 9087 u8 reserved_at_3[0x5]; 9088 u8 local_port[0x8]; 9089 u8 reserved_at_10[0xd]; 9090 u8 proto_mask[0x3]; 9091 9092 u8 an_status[0x4]; 9093 u8 reserved_at_24[0xc]; 9094 u8 data_rate_oper[0x10]; 9095 9096 u8 ext_eth_proto_capability[0x20]; 9097 9098 u8 eth_proto_capability[0x20]; 9099 9100 u8 ib_link_width_capability[0x10]; 9101 u8 ib_proto_capability[0x10]; 9102 9103 u8 ext_eth_proto_admin[0x20]; 9104 9105 u8 eth_proto_admin[0x20]; 9106 9107 u8 ib_link_width_admin[0x10]; 9108 u8 ib_proto_admin[0x10]; 9109 9110 u8 ext_eth_proto_oper[0x20]; 9111 9112 u8 eth_proto_oper[0x20]; 9113 9114 u8 ib_link_width_oper[0x10]; 9115 u8 ib_proto_oper[0x10]; 9116 9117 u8 reserved_at_160[0x1c]; 9118 u8 connector_type[0x4]; 9119 9120 u8 eth_proto_lp_advertise[0x20]; 9121 9122 u8 reserved_at_1a0[0x60]; 9123 }; 9124 9125 struct mlx5_ifc_mlcr_reg_bits { 9126 u8 reserved_at_0[0x8]; 9127 u8 local_port[0x8]; 9128 u8 reserved_at_10[0x20]; 9129 9130 u8 beacon_duration[0x10]; 9131 u8 reserved_at_40[0x10]; 9132 9133 u8 beacon_remain[0x10]; 9134 }; 9135 9136 struct mlx5_ifc_ptas_reg_bits { 9137 u8 reserved_at_0[0x20]; 9138 9139 u8 algorithm_options[0x10]; 9140 u8 reserved_at_30[0x4]; 9141 u8 repetitions_mode[0x4]; 9142 u8 num_of_repetitions[0x8]; 9143 9144 u8 grade_version[0x8]; 9145 u8 height_grade_type[0x4]; 9146 u8 phase_grade_type[0x4]; 9147 u8 height_grade_weight[0x8]; 9148 u8 phase_grade_weight[0x8]; 9149 9150 u8 gisim_measure_bits[0x10]; 9151 u8 adaptive_tap_measure_bits[0x10]; 9152 9153 u8 ber_bath_high_error_threshold[0x10]; 9154 u8 ber_bath_mid_error_threshold[0x10]; 9155 9156 u8 ber_bath_low_error_threshold[0x10]; 9157 u8 one_ratio_high_threshold[0x10]; 9158 9159 u8 one_ratio_high_mid_threshold[0x10]; 9160 u8 one_ratio_low_mid_threshold[0x10]; 9161 9162 u8 one_ratio_low_threshold[0x10]; 9163 u8 ndeo_error_threshold[0x10]; 9164 9165 u8 mixer_offset_step_size[0x10]; 9166 u8 reserved_at_110[0x8]; 9167 u8 mix90_phase_for_voltage_bath[0x8]; 9168 9169 u8 mixer_offset_start[0x10]; 9170 u8 mixer_offset_end[0x10]; 9171 9172 u8 reserved_at_140[0x15]; 9173 u8 ber_test_time[0xb]; 9174 }; 9175 9176 struct mlx5_ifc_pspa_reg_bits { 9177 u8 swid[0x8]; 9178 u8 local_port[0x8]; 9179 u8 sub_port[0x8]; 9180 u8 reserved_at_18[0x8]; 9181 9182 u8 reserved_at_20[0x20]; 9183 }; 9184 9185 struct mlx5_ifc_pqdr_reg_bits { 9186 u8 reserved_at_0[0x8]; 9187 u8 local_port[0x8]; 9188 u8 reserved_at_10[0x5]; 9189 u8 prio[0x3]; 9190 u8 reserved_at_18[0x6]; 9191 u8 mode[0x2]; 9192 9193 u8 reserved_at_20[0x20]; 9194 9195 u8 reserved_at_40[0x10]; 9196 u8 min_threshold[0x10]; 9197 9198 u8 reserved_at_60[0x10]; 9199 u8 max_threshold[0x10]; 9200 9201 u8 reserved_at_80[0x10]; 9202 u8 mark_probability_denominator[0x10]; 9203 9204 u8 reserved_at_a0[0x60]; 9205 }; 9206 9207 struct mlx5_ifc_ppsc_reg_bits { 9208 u8 reserved_at_0[0x8]; 9209 u8 local_port[0x8]; 9210 u8 reserved_at_10[0x10]; 9211 9212 u8 reserved_at_20[0x60]; 9213 9214 u8 reserved_at_80[0x1c]; 9215 u8 wrps_admin[0x4]; 9216 9217 u8 reserved_at_a0[0x1c]; 9218 u8 wrps_status[0x4]; 9219 9220 u8 reserved_at_c0[0x8]; 9221 u8 up_threshold[0x8]; 9222 u8 reserved_at_d0[0x8]; 9223 u8 down_threshold[0x8]; 9224 9225 u8 reserved_at_e0[0x20]; 9226 9227 u8 reserved_at_100[0x1c]; 9228 u8 srps_admin[0x4]; 9229 9230 u8 reserved_at_120[0x1c]; 9231 u8 srps_status[0x4]; 9232 9233 u8 reserved_at_140[0x40]; 9234 }; 9235 9236 struct mlx5_ifc_pplr_reg_bits { 9237 u8 reserved_at_0[0x8]; 9238 u8 local_port[0x8]; 9239 u8 reserved_at_10[0x10]; 9240 9241 u8 reserved_at_20[0x8]; 9242 u8 lb_cap[0x8]; 9243 u8 reserved_at_30[0x8]; 9244 u8 lb_en[0x8]; 9245 }; 9246 9247 struct mlx5_ifc_pplm_reg_bits { 9248 u8 reserved_at_0[0x8]; 9249 u8 local_port[0x8]; 9250 u8 reserved_at_10[0x10]; 9251 9252 u8 reserved_at_20[0x20]; 9253 9254 u8 port_profile_mode[0x8]; 9255 u8 static_port_profile[0x8]; 9256 u8 active_port_profile[0x8]; 9257 u8 reserved_at_58[0x8]; 9258 9259 u8 retransmission_active[0x8]; 9260 u8 fec_mode_active[0x18]; 9261 9262 u8 rs_fec_correction_bypass_cap[0x4]; 9263 u8 reserved_at_84[0x8]; 9264 u8 fec_override_cap_56g[0x4]; 9265 u8 fec_override_cap_100g[0x4]; 9266 u8 fec_override_cap_50g[0x4]; 9267 u8 fec_override_cap_25g[0x4]; 9268 u8 fec_override_cap_10g_40g[0x4]; 9269 9270 u8 rs_fec_correction_bypass_admin[0x4]; 9271 u8 reserved_at_a4[0x8]; 9272 u8 fec_override_admin_56g[0x4]; 9273 u8 fec_override_admin_100g[0x4]; 9274 u8 fec_override_admin_50g[0x4]; 9275 u8 fec_override_admin_25g[0x4]; 9276 u8 fec_override_admin_10g_40g[0x4]; 9277 9278 u8 fec_override_cap_400g_8x[0x10]; 9279 u8 fec_override_cap_200g_4x[0x10]; 9280 9281 u8 fec_override_cap_100g_2x[0x10]; 9282 u8 fec_override_cap_50g_1x[0x10]; 9283 9284 u8 fec_override_admin_400g_8x[0x10]; 9285 u8 fec_override_admin_200g_4x[0x10]; 9286 9287 u8 fec_override_admin_100g_2x[0x10]; 9288 u8 fec_override_admin_50g_1x[0x10]; 9289 9290 u8 reserved_at_140[0x140]; 9291 }; 9292 9293 struct mlx5_ifc_ppcnt_reg_bits { 9294 u8 swid[0x8]; 9295 u8 local_port[0x8]; 9296 u8 pnat[0x2]; 9297 u8 reserved_at_12[0x8]; 9298 u8 grp[0x6]; 9299 9300 u8 clr[0x1]; 9301 u8 reserved_at_21[0x1c]; 9302 u8 prio_tc[0x3]; 9303 9304 union mlx5_ifc_eth_cntrs_grp_data_layout_auto_bits counter_set; 9305 }; 9306 9307 struct mlx5_ifc_mpein_reg_bits { 9308 u8 reserved_at_0[0x2]; 9309 u8 depth[0x6]; 9310 u8 pcie_index[0x8]; 9311 u8 node[0x8]; 9312 u8 reserved_at_18[0x8]; 9313 9314 u8 capability_mask[0x20]; 9315 9316 u8 reserved_at_40[0x8]; 9317 u8 link_width_enabled[0x8]; 9318 u8 link_speed_enabled[0x10]; 9319 9320 u8 lane0_physical_position[0x8]; 9321 u8 link_width_active[0x8]; 9322 u8 link_speed_active[0x10]; 9323 9324 u8 num_of_pfs[0x10]; 9325 u8 num_of_vfs[0x10]; 9326 9327 u8 bdf0[0x10]; 9328 u8 reserved_at_b0[0x10]; 9329 9330 u8 max_read_request_size[0x4]; 9331 u8 max_payload_size[0x4]; 9332 u8 reserved_at_c8[0x5]; 9333 u8 pwr_status[0x3]; 9334 u8 port_type[0x4]; 9335 u8 reserved_at_d4[0xb]; 9336 u8 lane_reversal[0x1]; 9337 9338 u8 reserved_at_e0[0x14]; 9339 u8 pci_power[0xc]; 9340 9341 u8 reserved_at_100[0x20]; 9342 9343 u8 device_status[0x10]; 9344 u8 port_state[0x8]; 9345 u8 reserved_at_138[0x8]; 9346 9347 u8 reserved_at_140[0x10]; 9348 u8 receiver_detect_result[0x10]; 9349 9350 u8 reserved_at_160[0x20]; 9351 }; 9352 9353 struct mlx5_ifc_mpcnt_reg_bits { 9354 u8 reserved_at_0[0x8]; 9355 u8 pcie_index[0x8]; 9356 u8 reserved_at_10[0xa]; 9357 u8 grp[0x6]; 9358 9359 u8 clr[0x1]; 9360 u8 reserved_at_21[0x1f]; 9361 9362 union mlx5_ifc_pcie_cntrs_grp_data_layout_auto_bits counter_set; 9363 }; 9364 9365 struct mlx5_ifc_ppad_reg_bits { 9366 u8 reserved_at_0[0x3]; 9367 u8 single_mac[0x1]; 9368 u8 reserved_at_4[0x4]; 9369 u8 local_port[0x8]; 9370 u8 mac_47_32[0x10]; 9371 9372 u8 mac_31_0[0x20]; 9373 9374 u8 reserved_at_40[0x40]; 9375 }; 9376 9377 struct mlx5_ifc_pmtu_reg_bits { 9378 u8 reserved_at_0[0x8]; 9379 u8 local_port[0x8]; 9380 u8 reserved_at_10[0x10]; 9381 9382 u8 max_mtu[0x10]; 9383 u8 reserved_at_30[0x10]; 9384 9385 u8 admin_mtu[0x10]; 9386 u8 reserved_at_50[0x10]; 9387 9388 u8 oper_mtu[0x10]; 9389 u8 reserved_at_70[0x10]; 9390 }; 9391 9392 struct mlx5_ifc_pmpr_reg_bits { 9393 u8 reserved_at_0[0x8]; 9394 u8 module[0x8]; 9395 u8 reserved_at_10[0x10]; 9396 9397 u8 reserved_at_20[0x18]; 9398 u8 attenuation_5g[0x8]; 9399 9400 u8 reserved_at_40[0x18]; 9401 u8 attenuation_7g[0x8]; 9402 9403 u8 reserved_at_60[0x18]; 9404 u8 attenuation_12g[0x8]; 9405 }; 9406 9407 struct mlx5_ifc_pmpe_reg_bits { 9408 u8 reserved_at_0[0x8]; 9409 u8 module[0x8]; 9410 u8 reserved_at_10[0xc]; 9411 u8 module_status[0x4]; 9412 9413 u8 reserved_at_20[0x60]; 9414 }; 9415 9416 struct mlx5_ifc_pmpc_reg_bits { 9417 u8 module_state_updated[32][0x8]; 9418 }; 9419 9420 struct mlx5_ifc_pmlpn_reg_bits { 9421 u8 reserved_at_0[0x4]; 9422 u8 mlpn_status[0x4]; 9423 u8 local_port[0x8]; 9424 u8 reserved_at_10[0x10]; 9425 9426 u8 e[0x1]; 9427 u8 reserved_at_21[0x1f]; 9428 }; 9429 9430 struct mlx5_ifc_pmlp_reg_bits { 9431 u8 rxtx[0x1]; 9432 u8 reserved_at_1[0x7]; 9433 u8 local_port[0x8]; 9434 u8 reserved_at_10[0x8]; 9435 u8 width[0x8]; 9436 9437 u8 lane0_module_mapping[0x20]; 9438 9439 u8 lane1_module_mapping[0x20]; 9440 9441 u8 lane2_module_mapping[0x20]; 9442 9443 u8 lane3_module_mapping[0x20]; 9444 9445 u8 reserved_at_a0[0x160]; 9446 }; 9447 9448 struct mlx5_ifc_pmaos_reg_bits { 9449 u8 reserved_at_0[0x8]; 9450 u8 module[0x8]; 9451 u8 reserved_at_10[0x4]; 9452 u8 admin_status[0x4]; 9453 u8 reserved_at_18[0x4]; 9454 u8 oper_status[0x4]; 9455 9456 u8 ase[0x1]; 9457 u8 ee[0x1]; 9458 u8 reserved_at_22[0x1c]; 9459 u8 e[0x2]; 9460 9461 u8 reserved_at_40[0x40]; 9462 }; 9463 9464 struct mlx5_ifc_plpc_reg_bits { 9465 u8 reserved_at_0[0x4]; 9466 u8 profile_id[0xc]; 9467 u8 reserved_at_10[0x4]; 9468 u8 proto_mask[0x4]; 9469 u8 reserved_at_18[0x8]; 9470 9471 u8 reserved_at_20[0x10]; 9472 u8 lane_speed[0x10]; 9473 9474 u8 reserved_at_40[0x17]; 9475 u8 lpbf[0x1]; 9476 u8 fec_mode_policy[0x8]; 9477 9478 u8 retransmission_capability[0x8]; 9479 u8 fec_mode_capability[0x18]; 9480 9481 u8 retransmission_support_admin[0x8]; 9482 u8 fec_mode_support_admin[0x18]; 9483 9484 u8 retransmission_request_admin[0x8]; 9485 u8 fec_mode_request_admin[0x18]; 9486 9487 u8 reserved_at_c0[0x80]; 9488 }; 9489 9490 struct mlx5_ifc_plib_reg_bits { 9491 u8 reserved_at_0[0x8]; 9492 u8 local_port[0x8]; 9493 u8 reserved_at_10[0x8]; 9494 u8 ib_port[0x8]; 9495 9496 u8 reserved_at_20[0x60]; 9497 }; 9498 9499 struct mlx5_ifc_plbf_reg_bits { 9500 u8 reserved_at_0[0x8]; 9501 u8 local_port[0x8]; 9502 u8 reserved_at_10[0xd]; 9503 u8 lbf_mode[0x3]; 9504 9505 u8 reserved_at_20[0x20]; 9506 }; 9507 9508 struct mlx5_ifc_pipg_reg_bits { 9509 u8 reserved_at_0[0x8]; 9510 u8 local_port[0x8]; 9511 u8 reserved_at_10[0x10]; 9512 9513 u8 dic[0x1]; 9514 u8 reserved_at_21[0x19]; 9515 u8 ipg[0x4]; 9516 u8 reserved_at_3e[0x2]; 9517 }; 9518 9519 struct mlx5_ifc_pifr_reg_bits { 9520 u8 reserved_at_0[0x8]; 9521 u8 local_port[0x8]; 9522 u8 reserved_at_10[0x10]; 9523 9524 u8 reserved_at_20[0xe0]; 9525 9526 u8 port_filter[8][0x20]; 9527 9528 u8 port_filter_update_en[8][0x20]; 9529 }; 9530 9531 struct mlx5_ifc_pfcc_reg_bits { 9532 u8 reserved_at_0[0x8]; 9533 u8 local_port[0x8]; 9534 u8 reserved_at_10[0xb]; 9535 u8 ppan_mask_n[0x1]; 9536 u8 minor_stall_mask[0x1]; 9537 u8 critical_stall_mask[0x1]; 9538 u8 reserved_at_1e[0x2]; 9539 9540 u8 ppan[0x4]; 9541 u8 reserved_at_24[0x4]; 9542 u8 prio_mask_tx[0x8]; 9543 u8 reserved_at_30[0x8]; 9544 u8 prio_mask_rx[0x8]; 9545 9546 u8 pptx[0x1]; 9547 u8 aptx[0x1]; 9548 u8 pptx_mask_n[0x1]; 9549 u8 reserved_at_43[0x5]; 9550 u8 pfctx[0x8]; 9551 u8 reserved_at_50[0x10]; 9552 9553 u8 pprx[0x1]; 9554 u8 aprx[0x1]; 9555 u8 pprx_mask_n[0x1]; 9556 u8 reserved_at_63[0x5]; 9557 u8 pfcrx[0x8]; 9558 u8 reserved_at_70[0x10]; 9559 9560 u8 device_stall_minor_watermark[0x10]; 9561 u8 device_stall_critical_watermark[0x10]; 9562 9563 u8 reserved_at_a0[0x60]; 9564 }; 9565 9566 struct mlx5_ifc_pelc_reg_bits { 9567 u8 op[0x4]; 9568 u8 reserved_at_4[0x4]; 9569 u8 local_port[0x8]; 9570 u8 reserved_at_10[0x10]; 9571 9572 u8 op_admin[0x8]; 9573 u8 op_capability[0x8]; 9574 u8 op_request[0x8]; 9575 u8 op_active[0x8]; 9576 9577 u8 admin[0x40]; 9578 9579 u8 capability[0x40]; 9580 9581 u8 request[0x40]; 9582 9583 u8 active[0x40]; 9584 9585 u8 reserved_at_140[0x80]; 9586 }; 9587 9588 struct mlx5_ifc_peir_reg_bits { 9589 u8 reserved_at_0[0x8]; 9590 u8 local_port[0x8]; 9591 u8 reserved_at_10[0x10]; 9592 9593 u8 reserved_at_20[0xc]; 9594 u8 error_count[0x4]; 9595 u8 reserved_at_30[0x10]; 9596 9597 u8 reserved_at_40[0xc]; 9598 u8 lane[0x4]; 9599 u8 reserved_at_50[0x8]; 9600 u8 error_type[0x8]; 9601 }; 9602 9603 struct mlx5_ifc_mpegc_reg_bits { 9604 u8 reserved_at_0[0x30]; 9605 u8 field_select[0x10]; 9606 9607 u8 tx_overflow_sense[0x1]; 9608 u8 mark_cqe[0x1]; 9609 u8 mark_cnp[0x1]; 9610 u8 reserved_at_43[0x1b]; 9611 u8 tx_lossy_overflow_oper[0x2]; 9612 9613 u8 reserved_at_60[0x100]; 9614 }; 9615 9616 enum { 9617 MLX5_MTUTC_OPERATION_SET_TIME_IMMEDIATE = 0x1, 9618 MLX5_MTUTC_OPERATION_ADJUST_TIME = 0x2, 9619 MLX5_MTUTC_OPERATION_ADJUST_FREQ_UTC = 0x3, 9620 }; 9621 9622 struct mlx5_ifc_mtutc_reg_bits { 9623 u8 reserved_at_0[0x1c]; 9624 u8 operation[0x4]; 9625 9626 u8 freq_adjustment[0x20]; 9627 9628 u8 reserved_at_40[0x40]; 9629 9630 u8 utc_sec[0x20]; 9631 9632 u8 reserved_at_a0[0x2]; 9633 u8 utc_nsec[0x1e]; 9634 9635 u8 time_adjustment[0x20]; 9636 }; 9637 9638 struct mlx5_ifc_pcam_enhanced_features_bits { 9639 u8 reserved_at_0[0x68]; 9640 u8 fec_50G_per_lane_in_pplm[0x1]; 9641 u8 reserved_at_69[0x4]; 9642 u8 rx_icrc_encapsulated_counter[0x1]; 9643 u8 reserved_at_6e[0x4]; 9644 u8 ptys_extended_ethernet[0x1]; 9645 u8 reserved_at_73[0x3]; 9646 u8 pfcc_mask[0x1]; 9647 u8 reserved_at_77[0x3]; 9648 u8 per_lane_error_counters[0x1]; 9649 u8 rx_buffer_fullness_counters[0x1]; 9650 u8 ptys_connector_type[0x1]; 9651 u8 reserved_at_7d[0x1]; 9652 u8 ppcnt_discard_group[0x1]; 9653 u8 ppcnt_statistical_group[0x1]; 9654 }; 9655 9656 struct mlx5_ifc_pcam_regs_5000_to_507f_bits { 9657 u8 port_access_reg_cap_mask_127_to_96[0x20]; 9658 u8 port_access_reg_cap_mask_95_to_64[0x20]; 9659 9660 u8 port_access_reg_cap_mask_63_to_36[0x1c]; 9661 u8 pplm[0x1]; 9662 u8 port_access_reg_cap_mask_34_to_32[0x3]; 9663 9664 u8 port_access_reg_cap_mask_31_to_13[0x13]; 9665 u8 pbmc[0x1]; 9666 u8 pptb[0x1]; 9667 u8 port_access_reg_cap_mask_10_to_09[0x2]; 9668 u8 ppcnt[0x1]; 9669 u8 port_access_reg_cap_mask_07_to_00[0x8]; 9670 }; 9671 9672 struct mlx5_ifc_pcam_reg_bits { 9673 u8 reserved_at_0[0x8]; 9674 u8 feature_group[0x8]; 9675 u8 reserved_at_10[0x8]; 9676 u8 access_reg_group[0x8]; 9677 9678 u8 reserved_at_20[0x20]; 9679 9680 union { 9681 struct mlx5_ifc_pcam_regs_5000_to_507f_bits regs_5000_to_507f; 9682 u8 reserved_at_0[0x80]; 9683 } port_access_reg_cap_mask; 9684 9685 u8 reserved_at_c0[0x80]; 9686 9687 union { 9688 struct mlx5_ifc_pcam_enhanced_features_bits enhanced_features; 9689 u8 reserved_at_0[0x80]; 9690 } feature_cap_mask; 9691 9692 u8 reserved_at_1c0[0xc0]; 9693 }; 9694 9695 struct mlx5_ifc_mcam_enhanced_features_bits { 9696 u8 reserved_at_0[0x5d]; 9697 u8 mcia_32dwords[0x1]; 9698 u8 reserved_at_5e[0xc]; 9699 u8 reset_state[0x1]; 9700 u8 ptpcyc2realtime_modify[0x1]; 9701 u8 reserved_at_6c[0x2]; 9702 u8 pci_status_and_power[0x1]; 9703 u8 reserved_at_6f[0x5]; 9704 u8 mark_tx_action_cnp[0x1]; 9705 u8 mark_tx_action_cqe[0x1]; 9706 u8 dynamic_tx_overflow[0x1]; 9707 u8 reserved_at_77[0x4]; 9708 u8 pcie_outbound_stalled[0x1]; 9709 u8 tx_overflow_buffer_pkt[0x1]; 9710 u8 mtpps_enh_out_per_adj[0x1]; 9711 u8 mtpps_fs[0x1]; 9712 u8 pcie_performance_group[0x1]; 9713 }; 9714 9715 struct mlx5_ifc_mcam_access_reg_bits { 9716 u8 reserved_at_0[0x1c]; 9717 u8 mcda[0x1]; 9718 u8 mcc[0x1]; 9719 u8 mcqi[0x1]; 9720 u8 mcqs[0x1]; 9721 9722 u8 regs_95_to_87[0x9]; 9723 u8 mpegc[0x1]; 9724 u8 mtutc[0x1]; 9725 u8 regs_84_to_68[0x11]; 9726 u8 tracer_registers[0x4]; 9727 9728 u8 regs_63_to_46[0x12]; 9729 u8 mrtc[0x1]; 9730 u8 regs_44_to_32[0xd]; 9731 9732 u8 regs_31_to_0[0x20]; 9733 }; 9734 9735 struct mlx5_ifc_mcam_access_reg_bits1 { 9736 u8 regs_127_to_96[0x20]; 9737 9738 u8 regs_95_to_64[0x20]; 9739 9740 u8 regs_63_to_32[0x20]; 9741 9742 u8 regs_31_to_0[0x20]; 9743 }; 9744 9745 struct mlx5_ifc_mcam_access_reg_bits2 { 9746 u8 regs_127_to_99[0x1d]; 9747 u8 mirc[0x1]; 9748 u8 regs_97_to_96[0x2]; 9749 9750 u8 regs_95_to_64[0x20]; 9751 9752 u8 regs_63_to_32[0x20]; 9753 9754 u8 regs_31_to_0[0x20]; 9755 }; 9756 9757 struct mlx5_ifc_mcam_reg_bits { 9758 u8 reserved_at_0[0x8]; 9759 u8 feature_group[0x8]; 9760 u8 reserved_at_10[0x8]; 9761 u8 access_reg_group[0x8]; 9762 9763 u8 reserved_at_20[0x20]; 9764 9765 union { 9766 struct mlx5_ifc_mcam_access_reg_bits access_regs; 9767 struct mlx5_ifc_mcam_access_reg_bits1 access_regs1; 9768 struct mlx5_ifc_mcam_access_reg_bits2 access_regs2; 9769 u8 reserved_at_0[0x80]; 9770 } mng_access_reg_cap_mask; 9771 9772 u8 reserved_at_c0[0x80]; 9773 9774 union { 9775 struct mlx5_ifc_mcam_enhanced_features_bits enhanced_features; 9776 u8 reserved_at_0[0x80]; 9777 } mng_feature_cap_mask; 9778 9779 u8 reserved_at_1c0[0x80]; 9780 }; 9781 9782 struct mlx5_ifc_qcam_access_reg_cap_mask { 9783 u8 qcam_access_reg_cap_mask_127_to_20[0x6C]; 9784 u8 qpdpm[0x1]; 9785 u8 qcam_access_reg_cap_mask_18_to_4[0x0F]; 9786 u8 qdpm[0x1]; 9787 u8 qpts[0x1]; 9788 u8 qcap[0x1]; 9789 u8 qcam_access_reg_cap_mask_0[0x1]; 9790 }; 9791 9792 struct mlx5_ifc_qcam_qos_feature_cap_mask { 9793 u8 qcam_qos_feature_cap_mask_127_to_1[0x7F]; 9794 u8 qpts_trust_both[0x1]; 9795 }; 9796 9797 struct mlx5_ifc_qcam_reg_bits { 9798 u8 reserved_at_0[0x8]; 9799 u8 feature_group[0x8]; 9800 u8 reserved_at_10[0x8]; 9801 u8 access_reg_group[0x8]; 9802 u8 reserved_at_20[0x20]; 9803 9804 union { 9805 struct mlx5_ifc_qcam_access_reg_cap_mask reg_cap; 9806 u8 reserved_at_0[0x80]; 9807 } qos_access_reg_cap_mask; 9808 9809 u8 reserved_at_c0[0x80]; 9810 9811 union { 9812 struct mlx5_ifc_qcam_qos_feature_cap_mask feature_cap; 9813 u8 reserved_at_0[0x80]; 9814 } qos_feature_cap_mask; 9815 9816 u8 reserved_at_1c0[0x80]; 9817 }; 9818 9819 struct mlx5_ifc_core_dump_reg_bits { 9820 u8 reserved_at_0[0x18]; 9821 u8 core_dump_type[0x8]; 9822 9823 u8 reserved_at_20[0x30]; 9824 u8 vhca_id[0x10]; 9825 9826 u8 reserved_at_60[0x8]; 9827 u8 qpn[0x18]; 9828 u8 reserved_at_80[0x180]; 9829 }; 9830 9831 struct mlx5_ifc_pcap_reg_bits { 9832 u8 reserved_at_0[0x8]; 9833 u8 local_port[0x8]; 9834 u8 reserved_at_10[0x10]; 9835 9836 u8 port_capability_mask[4][0x20]; 9837 }; 9838 9839 struct mlx5_ifc_paos_reg_bits { 9840 u8 swid[0x8]; 9841 u8 local_port[0x8]; 9842 u8 reserved_at_10[0x4]; 9843 u8 admin_status[0x4]; 9844 u8 reserved_at_18[0x4]; 9845 u8 oper_status[0x4]; 9846 9847 u8 ase[0x1]; 9848 u8 ee[0x1]; 9849 u8 reserved_at_22[0x1c]; 9850 u8 e[0x2]; 9851 9852 u8 reserved_at_40[0x40]; 9853 }; 9854 9855 struct mlx5_ifc_pamp_reg_bits { 9856 u8 reserved_at_0[0x8]; 9857 u8 opamp_group[0x8]; 9858 u8 reserved_at_10[0xc]; 9859 u8 opamp_group_type[0x4]; 9860 9861 u8 start_index[0x10]; 9862 u8 reserved_at_30[0x4]; 9863 u8 num_of_indices[0xc]; 9864 9865 u8 index_data[18][0x10]; 9866 }; 9867 9868 struct mlx5_ifc_pcmr_reg_bits { 9869 u8 reserved_at_0[0x8]; 9870 u8 local_port[0x8]; 9871 u8 reserved_at_10[0x10]; 9872 9873 u8 entropy_force_cap[0x1]; 9874 u8 entropy_calc_cap[0x1]; 9875 u8 entropy_gre_calc_cap[0x1]; 9876 u8 reserved_at_23[0xf]; 9877 u8 rx_ts_over_crc_cap[0x1]; 9878 u8 reserved_at_33[0xb]; 9879 u8 fcs_cap[0x1]; 9880 u8 reserved_at_3f[0x1]; 9881 9882 u8 entropy_force[0x1]; 9883 u8 entropy_calc[0x1]; 9884 u8 entropy_gre_calc[0x1]; 9885 u8 reserved_at_43[0xf]; 9886 u8 rx_ts_over_crc[0x1]; 9887 u8 reserved_at_53[0xb]; 9888 u8 fcs_chk[0x1]; 9889 u8 reserved_at_5f[0x1]; 9890 }; 9891 9892 struct mlx5_ifc_lane_2_module_mapping_bits { 9893 u8 reserved_at_0[0x4]; 9894 u8 rx_lane[0x4]; 9895 u8 reserved_at_8[0x4]; 9896 u8 tx_lane[0x4]; 9897 u8 reserved_at_10[0x8]; 9898 u8 module[0x8]; 9899 }; 9900 9901 struct mlx5_ifc_bufferx_reg_bits { 9902 u8 reserved_at_0[0x6]; 9903 u8 lossy[0x1]; 9904 u8 epsb[0x1]; 9905 u8 reserved_at_8[0x8]; 9906 u8 size[0x10]; 9907 9908 u8 xoff_threshold[0x10]; 9909 u8 xon_threshold[0x10]; 9910 }; 9911 9912 struct mlx5_ifc_set_node_in_bits { 9913 u8 node_description[64][0x8]; 9914 }; 9915 9916 struct mlx5_ifc_register_power_settings_bits { 9917 u8 reserved_at_0[0x18]; 9918 u8 power_settings_level[0x8]; 9919 9920 u8 reserved_at_20[0x60]; 9921 }; 9922 9923 struct mlx5_ifc_register_host_endianness_bits { 9924 u8 he[0x1]; 9925 u8 reserved_at_1[0x1f]; 9926 9927 u8 reserved_at_20[0x60]; 9928 }; 9929 9930 struct mlx5_ifc_umr_pointer_desc_argument_bits { 9931 u8 reserved_at_0[0x20]; 9932 9933 u8 mkey[0x20]; 9934 9935 u8 addressh_63_32[0x20]; 9936 9937 u8 addressl_31_0[0x20]; 9938 }; 9939 9940 struct mlx5_ifc_ud_adrs_vector_bits { 9941 u8 dc_key[0x40]; 9942 9943 u8 ext[0x1]; 9944 u8 reserved_at_41[0x7]; 9945 u8 destination_qp_dct[0x18]; 9946 9947 u8 static_rate[0x4]; 9948 u8 sl_eth_prio[0x4]; 9949 u8 fl[0x1]; 9950 u8 mlid[0x7]; 9951 u8 rlid_udp_sport[0x10]; 9952 9953 u8 reserved_at_80[0x20]; 9954 9955 u8 rmac_47_16[0x20]; 9956 9957 u8 rmac_15_0[0x10]; 9958 u8 tclass[0x8]; 9959 u8 hop_limit[0x8]; 9960 9961 u8 reserved_at_e0[0x1]; 9962 u8 grh[0x1]; 9963 u8 reserved_at_e2[0x2]; 9964 u8 src_addr_index[0x8]; 9965 u8 flow_label[0x14]; 9966 9967 u8 rgid_rip[16][0x8]; 9968 }; 9969 9970 struct mlx5_ifc_pages_req_event_bits { 9971 u8 reserved_at_0[0x10]; 9972 u8 function_id[0x10]; 9973 9974 u8 num_pages[0x20]; 9975 9976 u8 reserved_at_40[0xa0]; 9977 }; 9978 9979 struct mlx5_ifc_eqe_bits { 9980 u8 reserved_at_0[0x8]; 9981 u8 event_type[0x8]; 9982 u8 reserved_at_10[0x8]; 9983 u8 event_sub_type[0x8]; 9984 9985 u8 reserved_at_20[0xe0]; 9986 9987 union mlx5_ifc_event_auto_bits event_data; 9988 9989 u8 reserved_at_1e0[0x10]; 9990 u8 signature[0x8]; 9991 u8 reserved_at_1f8[0x7]; 9992 u8 owner[0x1]; 9993 }; 9994 9995 enum { 9996 MLX5_CMD_QUEUE_ENTRY_TYPE_PCIE_CMD_IF_TRANSPORT = 0x7, 9997 }; 9998 9999 struct mlx5_ifc_cmd_queue_entry_bits { 10000 u8 type[0x8]; 10001 u8 reserved_at_8[0x18]; 10002 10003 u8 input_length[0x20]; 10004 10005 u8 input_mailbox_pointer_63_32[0x20]; 10006 10007 u8 input_mailbox_pointer_31_9[0x17]; 10008 u8 reserved_at_77[0x9]; 10009 10010 u8 command_input_inline_data[16][0x8]; 10011 10012 u8 command_output_inline_data[16][0x8]; 10013 10014 u8 output_mailbox_pointer_63_32[0x20]; 10015 10016 u8 output_mailbox_pointer_31_9[0x17]; 10017 u8 reserved_at_1b7[0x9]; 10018 10019 u8 output_length[0x20]; 10020 10021 u8 token[0x8]; 10022 u8 signature[0x8]; 10023 u8 reserved_at_1f0[0x8]; 10024 u8 status[0x7]; 10025 u8 ownership[0x1]; 10026 }; 10027 10028 struct mlx5_ifc_cmd_out_bits { 10029 u8 status[0x8]; 10030 u8 reserved_at_8[0x18]; 10031 10032 u8 syndrome[0x20]; 10033 10034 u8 command_output[0x20]; 10035 }; 10036 10037 struct mlx5_ifc_cmd_in_bits { 10038 u8 opcode[0x10]; 10039 u8 reserved_at_10[0x10]; 10040 10041 u8 reserved_at_20[0x10]; 10042 u8 op_mod[0x10]; 10043 10044 u8 command[][0x20]; 10045 }; 10046 10047 struct mlx5_ifc_cmd_if_box_bits { 10048 u8 mailbox_data[512][0x8]; 10049 10050 u8 reserved_at_1000[0x180]; 10051 10052 u8 next_pointer_63_32[0x20]; 10053 10054 u8 next_pointer_31_10[0x16]; 10055 u8 reserved_at_11b6[0xa]; 10056 10057 u8 block_number[0x20]; 10058 10059 u8 reserved_at_11e0[0x8]; 10060 u8 token[0x8]; 10061 u8 ctrl_signature[0x8]; 10062 u8 signature[0x8]; 10063 }; 10064 10065 struct mlx5_ifc_mtt_bits { 10066 u8 ptag_63_32[0x20]; 10067 10068 u8 ptag_31_8[0x18]; 10069 u8 reserved_at_38[0x6]; 10070 u8 wr_en[0x1]; 10071 u8 rd_en[0x1]; 10072 }; 10073 10074 struct mlx5_ifc_query_wol_rol_out_bits { 10075 u8 status[0x8]; 10076 u8 reserved_at_8[0x18]; 10077 10078 u8 syndrome[0x20]; 10079 10080 u8 reserved_at_40[0x10]; 10081 u8 rol_mode[0x8]; 10082 u8 wol_mode[0x8]; 10083 10084 u8 reserved_at_60[0x20]; 10085 }; 10086 10087 struct mlx5_ifc_query_wol_rol_in_bits { 10088 u8 opcode[0x10]; 10089 u8 reserved_at_10[0x10]; 10090 10091 u8 reserved_at_20[0x10]; 10092 u8 op_mod[0x10]; 10093 10094 u8 reserved_at_40[0x40]; 10095 }; 10096 10097 struct mlx5_ifc_set_wol_rol_out_bits { 10098 u8 status[0x8]; 10099 u8 reserved_at_8[0x18]; 10100 10101 u8 syndrome[0x20]; 10102 10103 u8 reserved_at_40[0x40]; 10104 }; 10105 10106 struct mlx5_ifc_set_wol_rol_in_bits { 10107 u8 opcode[0x10]; 10108 u8 reserved_at_10[0x10]; 10109 10110 u8 reserved_at_20[0x10]; 10111 u8 op_mod[0x10]; 10112 10113 u8 rol_mode_valid[0x1]; 10114 u8 wol_mode_valid[0x1]; 10115 u8 reserved_at_42[0xe]; 10116 u8 rol_mode[0x8]; 10117 u8 wol_mode[0x8]; 10118 10119 u8 reserved_at_60[0x20]; 10120 }; 10121 10122 enum { 10123 MLX5_INITIAL_SEG_NIC_INTERFACE_FULL_DRIVER = 0x0, 10124 MLX5_INITIAL_SEG_NIC_INTERFACE_DISABLED = 0x1, 10125 MLX5_INITIAL_SEG_NIC_INTERFACE_NO_DRAM_NIC = 0x2, 10126 }; 10127 10128 enum { 10129 MLX5_INITIAL_SEG_NIC_INTERFACE_SUPPORTED_FULL_DRIVER = 0x0, 10130 MLX5_INITIAL_SEG_NIC_INTERFACE_SUPPORTED_DISABLED = 0x1, 10131 MLX5_INITIAL_SEG_NIC_INTERFACE_SUPPORTED_NO_DRAM_NIC = 0x2, 10132 }; 10133 10134 enum { 10135 MLX5_INITIAL_SEG_HEALTH_SYNDROME_FW_INTERNAL_ERR = 0x1, 10136 MLX5_INITIAL_SEG_HEALTH_SYNDROME_DEAD_IRISC = 0x7, 10137 MLX5_INITIAL_SEG_HEALTH_SYNDROME_HW_FATAL_ERR = 0x8, 10138 MLX5_INITIAL_SEG_HEALTH_SYNDROME_FW_CRC_ERR = 0x9, 10139 MLX5_INITIAL_SEG_HEALTH_SYNDROME_ICM_FETCH_PCI_ERR = 0xa, 10140 MLX5_INITIAL_SEG_HEALTH_SYNDROME_ICM_PAGE_ERR = 0xb, 10141 MLX5_INITIAL_SEG_HEALTH_SYNDROME_ASYNCHRONOUS_EQ_BUF_OVERRUN = 0xc, 10142 MLX5_INITIAL_SEG_HEALTH_SYNDROME_EQ_IN_ERR = 0xd, 10143 MLX5_INITIAL_SEG_HEALTH_SYNDROME_EQ_INV = 0xe, 10144 MLX5_INITIAL_SEG_HEALTH_SYNDROME_FFSER_ERR = 0xf, 10145 MLX5_INITIAL_SEG_HEALTH_SYNDROME_HIGH_TEMP_ERR = 0x10, 10146 }; 10147 10148 struct mlx5_ifc_initial_seg_bits { 10149 u8 fw_rev_minor[0x10]; 10150 u8 fw_rev_major[0x10]; 10151 10152 u8 cmd_interface_rev[0x10]; 10153 u8 fw_rev_subminor[0x10]; 10154 10155 u8 reserved_at_40[0x40]; 10156 10157 u8 cmdq_phy_addr_63_32[0x20]; 10158 10159 u8 cmdq_phy_addr_31_12[0x14]; 10160 u8 reserved_at_b4[0x2]; 10161 u8 nic_interface[0x2]; 10162 u8 log_cmdq_size[0x4]; 10163 u8 log_cmdq_stride[0x4]; 10164 10165 u8 command_doorbell_vector[0x20]; 10166 10167 u8 reserved_at_e0[0xf00]; 10168 10169 u8 initializing[0x1]; 10170 u8 reserved_at_fe1[0x4]; 10171 u8 nic_interface_supported[0x3]; 10172 u8 embedded_cpu[0x1]; 10173 u8 reserved_at_fe9[0x17]; 10174 10175 struct mlx5_ifc_health_buffer_bits health_buffer; 10176 10177 u8 no_dram_nic_offset[0x20]; 10178 10179 u8 reserved_at_1220[0x6e40]; 10180 10181 u8 reserved_at_8060[0x1f]; 10182 u8 clear_int[0x1]; 10183 10184 u8 health_syndrome[0x8]; 10185 u8 health_counter[0x18]; 10186 10187 u8 reserved_at_80a0[0x17fc0]; 10188 }; 10189 10190 struct mlx5_ifc_mtpps_reg_bits { 10191 u8 reserved_at_0[0xc]; 10192 u8 cap_number_of_pps_pins[0x4]; 10193 u8 reserved_at_10[0x4]; 10194 u8 cap_max_num_of_pps_in_pins[0x4]; 10195 u8 reserved_at_18[0x4]; 10196 u8 cap_max_num_of_pps_out_pins[0x4]; 10197 10198 u8 reserved_at_20[0x24]; 10199 u8 cap_pin_3_mode[0x4]; 10200 u8 reserved_at_48[0x4]; 10201 u8 cap_pin_2_mode[0x4]; 10202 u8 reserved_at_50[0x4]; 10203 u8 cap_pin_1_mode[0x4]; 10204 u8 reserved_at_58[0x4]; 10205 u8 cap_pin_0_mode[0x4]; 10206 10207 u8 reserved_at_60[0x4]; 10208 u8 cap_pin_7_mode[0x4]; 10209 u8 reserved_at_68[0x4]; 10210 u8 cap_pin_6_mode[0x4]; 10211 u8 reserved_at_70[0x4]; 10212 u8 cap_pin_5_mode[0x4]; 10213 u8 reserved_at_78[0x4]; 10214 u8 cap_pin_4_mode[0x4]; 10215 10216 u8 field_select[0x20]; 10217 u8 reserved_at_a0[0x60]; 10218 10219 u8 enable[0x1]; 10220 u8 reserved_at_101[0xb]; 10221 u8 pattern[0x4]; 10222 u8 reserved_at_110[0x4]; 10223 u8 pin_mode[0x4]; 10224 u8 pin[0x8]; 10225 10226 u8 reserved_at_120[0x20]; 10227 10228 u8 time_stamp[0x40]; 10229 10230 u8 out_pulse_duration[0x10]; 10231 u8 out_periodic_adjustment[0x10]; 10232 u8 enhanced_out_periodic_adjustment[0x20]; 10233 10234 u8 reserved_at_1c0[0x20]; 10235 }; 10236 10237 struct mlx5_ifc_mtppse_reg_bits { 10238 u8 reserved_at_0[0x18]; 10239 u8 pin[0x8]; 10240 u8 event_arm[0x1]; 10241 u8 reserved_at_21[0x1b]; 10242 u8 event_generation_mode[0x4]; 10243 u8 reserved_at_40[0x40]; 10244 }; 10245 10246 struct mlx5_ifc_mcqs_reg_bits { 10247 u8 last_index_flag[0x1]; 10248 u8 reserved_at_1[0x7]; 10249 u8 fw_device[0x8]; 10250 u8 component_index[0x10]; 10251 10252 u8 reserved_at_20[0x10]; 10253 u8 identifier[0x10]; 10254 10255 u8 reserved_at_40[0x17]; 10256 u8 component_status[0x5]; 10257 u8 component_update_state[0x4]; 10258 10259 u8 last_update_state_changer_type[0x4]; 10260 u8 last_update_state_changer_host_id[0x4]; 10261 u8 reserved_at_68[0x18]; 10262 }; 10263 10264 struct mlx5_ifc_mcqi_cap_bits { 10265 u8 supported_info_bitmask[0x20]; 10266 10267 u8 component_size[0x20]; 10268 10269 u8 max_component_size[0x20]; 10270 10271 u8 log_mcda_word_size[0x4]; 10272 u8 reserved_at_64[0xc]; 10273 u8 mcda_max_write_size[0x10]; 10274 10275 u8 rd_en[0x1]; 10276 u8 reserved_at_81[0x1]; 10277 u8 match_chip_id[0x1]; 10278 u8 match_psid[0x1]; 10279 u8 check_user_timestamp[0x1]; 10280 u8 match_base_guid_mac[0x1]; 10281 u8 reserved_at_86[0x1a]; 10282 }; 10283 10284 struct mlx5_ifc_mcqi_version_bits { 10285 u8 reserved_at_0[0x2]; 10286 u8 build_time_valid[0x1]; 10287 u8 user_defined_time_valid[0x1]; 10288 u8 reserved_at_4[0x14]; 10289 u8 version_string_length[0x8]; 10290 10291 u8 version[0x20]; 10292 10293 u8 build_time[0x40]; 10294 10295 u8 user_defined_time[0x40]; 10296 10297 u8 build_tool_version[0x20]; 10298 10299 u8 reserved_at_e0[0x20]; 10300 10301 u8 version_string[92][0x8]; 10302 }; 10303 10304 struct mlx5_ifc_mcqi_activation_method_bits { 10305 u8 pending_server_ac_power_cycle[0x1]; 10306 u8 pending_server_dc_power_cycle[0x1]; 10307 u8 pending_server_reboot[0x1]; 10308 u8 pending_fw_reset[0x1]; 10309 u8 auto_activate[0x1]; 10310 u8 all_hosts_sync[0x1]; 10311 u8 device_hw_reset[0x1]; 10312 u8 reserved_at_7[0x19]; 10313 }; 10314 10315 union mlx5_ifc_mcqi_reg_data_bits { 10316 struct mlx5_ifc_mcqi_cap_bits mcqi_caps; 10317 struct mlx5_ifc_mcqi_version_bits mcqi_version; 10318 struct mlx5_ifc_mcqi_activation_method_bits mcqi_activation_mathod; 10319 }; 10320 10321 struct mlx5_ifc_mcqi_reg_bits { 10322 u8 read_pending_component[0x1]; 10323 u8 reserved_at_1[0xf]; 10324 u8 component_index[0x10]; 10325 10326 u8 reserved_at_20[0x20]; 10327 10328 u8 reserved_at_40[0x1b]; 10329 u8 info_type[0x5]; 10330 10331 u8 info_size[0x20]; 10332 10333 u8 offset[0x20]; 10334 10335 u8 reserved_at_a0[0x10]; 10336 u8 data_size[0x10]; 10337 10338 union mlx5_ifc_mcqi_reg_data_bits data[]; 10339 }; 10340 10341 struct mlx5_ifc_mcc_reg_bits { 10342 u8 reserved_at_0[0x4]; 10343 u8 time_elapsed_since_last_cmd[0xc]; 10344 u8 reserved_at_10[0x8]; 10345 u8 instruction[0x8]; 10346 10347 u8 reserved_at_20[0x10]; 10348 u8 component_index[0x10]; 10349 10350 u8 reserved_at_40[0x8]; 10351 u8 update_handle[0x18]; 10352 10353 u8 handle_owner_type[0x4]; 10354 u8 handle_owner_host_id[0x4]; 10355 u8 reserved_at_68[0x1]; 10356 u8 control_progress[0x7]; 10357 u8 error_code[0x8]; 10358 u8 reserved_at_78[0x4]; 10359 u8 control_state[0x4]; 10360 10361 u8 component_size[0x20]; 10362 10363 u8 reserved_at_a0[0x60]; 10364 }; 10365 10366 struct mlx5_ifc_mcda_reg_bits { 10367 u8 reserved_at_0[0x8]; 10368 u8 update_handle[0x18]; 10369 10370 u8 offset[0x20]; 10371 10372 u8 reserved_at_40[0x10]; 10373 u8 size[0x10]; 10374 10375 u8 reserved_at_60[0x20]; 10376 10377 u8 data[][0x20]; 10378 }; 10379 10380 enum { 10381 MLX5_MFRL_REG_RESET_STATE_IDLE = 0, 10382 MLX5_MFRL_REG_RESET_STATE_IN_NEGOTIATION = 1, 10383 MLX5_MFRL_REG_RESET_STATE_RESET_IN_PROGRESS = 2, 10384 MLX5_MFRL_REG_RESET_STATE_TIMEOUT = 3, 10385 MLX5_MFRL_REG_RESET_STATE_NACK = 4, 10386 }; 10387 10388 enum { 10389 MLX5_MFRL_REG_RESET_TYPE_FULL_CHIP = BIT(0), 10390 MLX5_MFRL_REG_RESET_TYPE_NET_PORT_ALIVE = BIT(1), 10391 }; 10392 10393 enum { 10394 MLX5_MFRL_REG_RESET_LEVEL0 = BIT(0), 10395 MLX5_MFRL_REG_RESET_LEVEL3 = BIT(3), 10396 MLX5_MFRL_REG_RESET_LEVEL6 = BIT(6), 10397 }; 10398 10399 struct mlx5_ifc_mfrl_reg_bits { 10400 u8 reserved_at_0[0x20]; 10401 10402 u8 reserved_at_20[0x2]; 10403 u8 pci_sync_for_fw_update_start[0x1]; 10404 u8 pci_sync_for_fw_update_resp[0x2]; 10405 u8 rst_type_sel[0x3]; 10406 u8 reserved_at_28[0x4]; 10407 u8 reset_state[0x4]; 10408 u8 reset_type[0x8]; 10409 u8 reset_level[0x8]; 10410 }; 10411 10412 struct mlx5_ifc_mirc_reg_bits { 10413 u8 reserved_at_0[0x18]; 10414 u8 status_code[0x8]; 10415 10416 u8 reserved_at_20[0x20]; 10417 }; 10418 10419 struct mlx5_ifc_pddr_monitor_opcode_bits { 10420 u8 reserved_at_0[0x10]; 10421 u8 monitor_opcode[0x10]; 10422 }; 10423 10424 union mlx5_ifc_pddr_troubleshooting_page_status_opcode_auto_bits { 10425 struct mlx5_ifc_pddr_monitor_opcode_bits pddr_monitor_opcode; 10426 u8 reserved_at_0[0x20]; 10427 }; 10428 10429 enum { 10430 /* Monitor opcodes */ 10431 MLX5_PDDR_REG_TRBLSH_GROUP_OPCODE_MONITOR = 0x0, 10432 }; 10433 10434 struct mlx5_ifc_pddr_troubleshooting_page_bits { 10435 u8 reserved_at_0[0x10]; 10436 u8 group_opcode[0x10]; 10437 10438 union mlx5_ifc_pddr_troubleshooting_page_status_opcode_auto_bits status_opcode; 10439 10440 u8 reserved_at_40[0x20]; 10441 10442 u8 status_message[59][0x20]; 10443 }; 10444 10445 union mlx5_ifc_pddr_reg_page_data_auto_bits { 10446 struct mlx5_ifc_pddr_troubleshooting_page_bits pddr_troubleshooting_page; 10447 u8 reserved_at_0[0x7c0]; 10448 }; 10449 10450 enum { 10451 MLX5_PDDR_REG_PAGE_SELECT_TROUBLESHOOTING_INFO_PAGE = 0x1, 10452 }; 10453 10454 struct mlx5_ifc_pddr_reg_bits { 10455 u8 reserved_at_0[0x8]; 10456 u8 local_port[0x8]; 10457 u8 pnat[0x2]; 10458 u8 reserved_at_12[0xe]; 10459 10460 u8 reserved_at_20[0x18]; 10461 u8 page_select[0x8]; 10462 10463 union mlx5_ifc_pddr_reg_page_data_auto_bits page_data; 10464 }; 10465 10466 struct mlx5_ifc_mrtc_reg_bits { 10467 u8 time_synced[0x1]; 10468 u8 reserved_at_1[0x1f]; 10469 10470 u8 reserved_at_20[0x20]; 10471 10472 u8 time_h[0x20]; 10473 10474 u8 time_l[0x20]; 10475 }; 10476 10477 union mlx5_ifc_ports_control_registers_document_bits { 10478 struct mlx5_ifc_bufferx_reg_bits bufferx_reg; 10479 struct mlx5_ifc_eth_2819_cntrs_grp_data_layout_bits eth_2819_cntrs_grp_data_layout; 10480 struct mlx5_ifc_eth_2863_cntrs_grp_data_layout_bits eth_2863_cntrs_grp_data_layout; 10481 struct mlx5_ifc_eth_3635_cntrs_grp_data_layout_bits eth_3635_cntrs_grp_data_layout; 10482 struct mlx5_ifc_eth_802_3_cntrs_grp_data_layout_bits eth_802_3_cntrs_grp_data_layout; 10483 struct mlx5_ifc_eth_extended_cntrs_grp_data_layout_bits eth_extended_cntrs_grp_data_layout; 10484 struct mlx5_ifc_eth_per_prio_grp_data_layout_bits eth_per_prio_grp_data_layout; 10485 struct mlx5_ifc_eth_per_tc_prio_grp_data_layout_bits eth_per_tc_prio_grp_data_layout; 10486 struct mlx5_ifc_eth_per_tc_congest_prio_grp_data_layout_bits eth_per_tc_congest_prio_grp_data_layout; 10487 struct mlx5_ifc_lane_2_module_mapping_bits lane_2_module_mapping; 10488 struct mlx5_ifc_pamp_reg_bits pamp_reg; 10489 struct mlx5_ifc_paos_reg_bits paos_reg; 10490 struct mlx5_ifc_pcap_reg_bits pcap_reg; 10491 struct mlx5_ifc_pddr_monitor_opcode_bits pddr_monitor_opcode; 10492 struct mlx5_ifc_pddr_reg_bits pddr_reg; 10493 struct mlx5_ifc_pddr_troubleshooting_page_bits pddr_troubleshooting_page; 10494 struct mlx5_ifc_peir_reg_bits peir_reg; 10495 struct mlx5_ifc_pelc_reg_bits pelc_reg; 10496 struct mlx5_ifc_pfcc_reg_bits pfcc_reg; 10497 struct mlx5_ifc_ib_port_cntrs_grp_data_layout_bits ib_port_cntrs_grp_data_layout; 10498 struct mlx5_ifc_phys_layer_cntrs_bits phys_layer_cntrs; 10499 struct mlx5_ifc_pifr_reg_bits pifr_reg; 10500 struct mlx5_ifc_pipg_reg_bits pipg_reg; 10501 struct mlx5_ifc_plbf_reg_bits plbf_reg; 10502 struct mlx5_ifc_plib_reg_bits plib_reg; 10503 struct mlx5_ifc_plpc_reg_bits plpc_reg; 10504 struct mlx5_ifc_pmaos_reg_bits pmaos_reg; 10505 struct mlx5_ifc_pmlp_reg_bits pmlp_reg; 10506 struct mlx5_ifc_pmlpn_reg_bits pmlpn_reg; 10507 struct mlx5_ifc_pmpc_reg_bits pmpc_reg; 10508 struct mlx5_ifc_pmpe_reg_bits pmpe_reg; 10509 struct mlx5_ifc_pmpr_reg_bits pmpr_reg; 10510 struct mlx5_ifc_pmtu_reg_bits pmtu_reg; 10511 struct mlx5_ifc_ppad_reg_bits ppad_reg; 10512 struct mlx5_ifc_ppcnt_reg_bits ppcnt_reg; 10513 struct mlx5_ifc_mpein_reg_bits mpein_reg; 10514 struct mlx5_ifc_mpcnt_reg_bits mpcnt_reg; 10515 struct mlx5_ifc_pplm_reg_bits pplm_reg; 10516 struct mlx5_ifc_pplr_reg_bits pplr_reg; 10517 struct mlx5_ifc_ppsc_reg_bits ppsc_reg; 10518 struct mlx5_ifc_pqdr_reg_bits pqdr_reg; 10519 struct mlx5_ifc_pspa_reg_bits pspa_reg; 10520 struct mlx5_ifc_ptas_reg_bits ptas_reg; 10521 struct mlx5_ifc_ptys_reg_bits ptys_reg; 10522 struct mlx5_ifc_mlcr_reg_bits mlcr_reg; 10523 struct mlx5_ifc_pude_reg_bits pude_reg; 10524 struct mlx5_ifc_pvlc_reg_bits pvlc_reg; 10525 struct mlx5_ifc_slrg_reg_bits slrg_reg; 10526 struct mlx5_ifc_sltp_reg_bits sltp_reg; 10527 struct mlx5_ifc_mtpps_reg_bits mtpps_reg; 10528 struct mlx5_ifc_mtppse_reg_bits mtppse_reg; 10529 struct mlx5_ifc_fpga_access_reg_bits fpga_access_reg; 10530 struct mlx5_ifc_fpga_ctrl_bits fpga_ctrl_bits; 10531 struct mlx5_ifc_fpga_cap_bits fpga_cap_bits; 10532 struct mlx5_ifc_mcqi_reg_bits mcqi_reg; 10533 struct mlx5_ifc_mcc_reg_bits mcc_reg; 10534 struct mlx5_ifc_mcda_reg_bits mcda_reg; 10535 struct mlx5_ifc_mirc_reg_bits mirc_reg; 10536 struct mlx5_ifc_mfrl_reg_bits mfrl_reg; 10537 struct mlx5_ifc_mtutc_reg_bits mtutc_reg; 10538 struct mlx5_ifc_mrtc_reg_bits mrtc_reg; 10539 u8 reserved_at_0[0x60e0]; 10540 }; 10541 10542 union mlx5_ifc_debug_enhancements_document_bits { 10543 struct mlx5_ifc_health_buffer_bits health_buffer; 10544 u8 reserved_at_0[0x200]; 10545 }; 10546 10547 union mlx5_ifc_uplink_pci_interface_document_bits { 10548 struct mlx5_ifc_initial_seg_bits initial_seg; 10549 u8 reserved_at_0[0x20060]; 10550 }; 10551 10552 struct mlx5_ifc_set_flow_table_root_out_bits { 10553 u8 status[0x8]; 10554 u8 reserved_at_8[0x18]; 10555 10556 u8 syndrome[0x20]; 10557 10558 u8 reserved_at_40[0x40]; 10559 }; 10560 10561 struct mlx5_ifc_set_flow_table_root_in_bits { 10562 u8 opcode[0x10]; 10563 u8 reserved_at_10[0x10]; 10564 10565 u8 reserved_at_20[0x10]; 10566 u8 op_mod[0x10]; 10567 10568 u8 other_vport[0x1]; 10569 u8 reserved_at_41[0xf]; 10570 u8 vport_number[0x10]; 10571 10572 u8 reserved_at_60[0x20]; 10573 10574 u8 table_type[0x8]; 10575 u8 reserved_at_88[0x7]; 10576 u8 table_of_other_vport[0x1]; 10577 u8 table_vport_number[0x10]; 10578 10579 u8 reserved_at_a0[0x8]; 10580 u8 table_id[0x18]; 10581 10582 u8 reserved_at_c0[0x8]; 10583 u8 underlay_qpn[0x18]; 10584 u8 table_eswitch_owner_vhca_id_valid[0x1]; 10585 u8 reserved_at_e1[0xf]; 10586 u8 table_eswitch_owner_vhca_id[0x10]; 10587 u8 reserved_at_100[0x100]; 10588 }; 10589 10590 enum { 10591 MLX5_MODIFY_FLOW_TABLE_MISS_TABLE_ID = (1UL << 0), 10592 MLX5_MODIFY_FLOW_TABLE_LAG_NEXT_TABLE_ID = (1UL << 15), 10593 }; 10594 10595 struct mlx5_ifc_modify_flow_table_out_bits { 10596 u8 status[0x8]; 10597 u8 reserved_at_8[0x18]; 10598 10599 u8 syndrome[0x20]; 10600 10601 u8 reserved_at_40[0x40]; 10602 }; 10603 10604 struct mlx5_ifc_modify_flow_table_in_bits { 10605 u8 opcode[0x10]; 10606 u8 reserved_at_10[0x10]; 10607 10608 u8 reserved_at_20[0x10]; 10609 u8 op_mod[0x10]; 10610 10611 u8 other_vport[0x1]; 10612 u8 reserved_at_41[0xf]; 10613 u8 vport_number[0x10]; 10614 10615 u8 reserved_at_60[0x10]; 10616 u8 modify_field_select[0x10]; 10617 10618 u8 table_type[0x8]; 10619 u8 reserved_at_88[0x18]; 10620 10621 u8 reserved_at_a0[0x8]; 10622 u8 table_id[0x18]; 10623 10624 struct mlx5_ifc_flow_table_context_bits flow_table_context; 10625 }; 10626 10627 struct mlx5_ifc_ets_tcn_config_reg_bits { 10628 u8 g[0x1]; 10629 u8 b[0x1]; 10630 u8 r[0x1]; 10631 u8 reserved_at_3[0x9]; 10632 u8 group[0x4]; 10633 u8 reserved_at_10[0x9]; 10634 u8 bw_allocation[0x7]; 10635 10636 u8 reserved_at_20[0xc]; 10637 u8 max_bw_units[0x4]; 10638 u8 reserved_at_30[0x8]; 10639 u8 max_bw_value[0x8]; 10640 }; 10641 10642 struct mlx5_ifc_ets_global_config_reg_bits { 10643 u8 reserved_at_0[0x2]; 10644 u8 r[0x1]; 10645 u8 reserved_at_3[0x1d]; 10646 10647 u8 reserved_at_20[0xc]; 10648 u8 max_bw_units[0x4]; 10649 u8 reserved_at_30[0x8]; 10650 u8 max_bw_value[0x8]; 10651 }; 10652 10653 struct mlx5_ifc_qetc_reg_bits { 10654 u8 reserved_at_0[0x8]; 10655 u8 port_number[0x8]; 10656 u8 reserved_at_10[0x30]; 10657 10658 struct mlx5_ifc_ets_tcn_config_reg_bits tc_configuration[0x8]; 10659 struct mlx5_ifc_ets_global_config_reg_bits global_configuration; 10660 }; 10661 10662 struct mlx5_ifc_qpdpm_dscp_reg_bits { 10663 u8 e[0x1]; 10664 u8 reserved_at_01[0x0b]; 10665 u8 prio[0x04]; 10666 }; 10667 10668 struct mlx5_ifc_qpdpm_reg_bits { 10669 u8 reserved_at_0[0x8]; 10670 u8 local_port[0x8]; 10671 u8 reserved_at_10[0x10]; 10672 struct mlx5_ifc_qpdpm_dscp_reg_bits dscp[64]; 10673 }; 10674 10675 struct mlx5_ifc_qpts_reg_bits { 10676 u8 reserved_at_0[0x8]; 10677 u8 local_port[0x8]; 10678 u8 reserved_at_10[0x2d]; 10679 u8 trust_state[0x3]; 10680 }; 10681 10682 struct mlx5_ifc_pptb_reg_bits { 10683 u8 reserved_at_0[0x2]; 10684 u8 mm[0x2]; 10685 u8 reserved_at_4[0x4]; 10686 u8 local_port[0x8]; 10687 u8 reserved_at_10[0x6]; 10688 u8 cm[0x1]; 10689 u8 um[0x1]; 10690 u8 pm[0x8]; 10691 10692 u8 prio_x_buff[0x20]; 10693 10694 u8 pm_msb[0x8]; 10695 u8 reserved_at_48[0x10]; 10696 u8 ctrl_buff[0x4]; 10697 u8 untagged_buff[0x4]; 10698 }; 10699 10700 struct mlx5_ifc_sbcam_reg_bits { 10701 u8 reserved_at_0[0x8]; 10702 u8 feature_group[0x8]; 10703 u8 reserved_at_10[0x8]; 10704 u8 access_reg_group[0x8]; 10705 10706 u8 reserved_at_20[0x20]; 10707 10708 u8 sb_access_reg_cap_mask[4][0x20]; 10709 10710 u8 reserved_at_c0[0x80]; 10711 10712 u8 sb_feature_cap_mask[4][0x20]; 10713 10714 u8 reserved_at_1c0[0x40]; 10715 10716 u8 cap_total_buffer_size[0x20]; 10717 10718 u8 cap_cell_size[0x10]; 10719 u8 cap_max_pg_buffers[0x8]; 10720 u8 cap_num_pool_supported[0x8]; 10721 10722 u8 reserved_at_240[0x8]; 10723 u8 cap_sbsr_stat_size[0x8]; 10724 u8 cap_max_tclass_data[0x8]; 10725 u8 cap_max_cpu_ingress_tclass_sb[0x8]; 10726 }; 10727 10728 struct mlx5_ifc_pbmc_reg_bits { 10729 u8 reserved_at_0[0x8]; 10730 u8 local_port[0x8]; 10731 u8 reserved_at_10[0x10]; 10732 10733 u8 xoff_timer_value[0x10]; 10734 u8 xoff_refresh[0x10]; 10735 10736 u8 reserved_at_40[0x9]; 10737 u8 fullness_threshold[0x7]; 10738 u8 port_buffer_size[0x10]; 10739 10740 struct mlx5_ifc_bufferx_reg_bits buffer[10]; 10741 10742 u8 reserved_at_2e0[0x80]; 10743 }; 10744 10745 struct mlx5_ifc_qtct_reg_bits { 10746 u8 reserved_at_0[0x8]; 10747 u8 port_number[0x8]; 10748 u8 reserved_at_10[0xd]; 10749 u8 prio[0x3]; 10750 10751 u8 reserved_at_20[0x1d]; 10752 u8 tclass[0x3]; 10753 }; 10754 10755 struct mlx5_ifc_mcia_reg_bits { 10756 u8 l[0x1]; 10757 u8 reserved_at_1[0x7]; 10758 u8 module[0x8]; 10759 u8 reserved_at_10[0x8]; 10760 u8 status[0x8]; 10761 10762 u8 i2c_device_address[0x8]; 10763 u8 page_number[0x8]; 10764 u8 device_address[0x10]; 10765 10766 u8 reserved_at_40[0x10]; 10767 u8 size[0x10]; 10768 10769 u8 reserved_at_60[0x20]; 10770 10771 u8 dword_0[0x20]; 10772 u8 dword_1[0x20]; 10773 u8 dword_2[0x20]; 10774 u8 dword_3[0x20]; 10775 u8 dword_4[0x20]; 10776 u8 dword_5[0x20]; 10777 u8 dword_6[0x20]; 10778 u8 dword_7[0x20]; 10779 u8 dword_8[0x20]; 10780 u8 dword_9[0x20]; 10781 u8 dword_10[0x20]; 10782 u8 dword_11[0x20]; 10783 }; 10784 10785 struct mlx5_ifc_dcbx_param_bits { 10786 u8 dcbx_cee_cap[0x1]; 10787 u8 dcbx_ieee_cap[0x1]; 10788 u8 dcbx_standby_cap[0x1]; 10789 u8 reserved_at_3[0x5]; 10790 u8 port_number[0x8]; 10791 u8 reserved_at_10[0xa]; 10792 u8 max_application_table_size[6]; 10793 u8 reserved_at_20[0x15]; 10794 u8 version_oper[0x3]; 10795 u8 reserved_at_38[5]; 10796 u8 version_admin[0x3]; 10797 u8 willing_admin[0x1]; 10798 u8 reserved_at_41[0x3]; 10799 u8 pfc_cap_oper[0x4]; 10800 u8 reserved_at_48[0x4]; 10801 u8 pfc_cap_admin[0x4]; 10802 u8 reserved_at_50[0x4]; 10803 u8 num_of_tc_oper[0x4]; 10804 u8 reserved_at_58[0x4]; 10805 u8 num_of_tc_admin[0x4]; 10806 u8 remote_willing[0x1]; 10807 u8 reserved_at_61[3]; 10808 u8 remote_pfc_cap[4]; 10809 u8 reserved_at_68[0x14]; 10810 u8 remote_num_of_tc[0x4]; 10811 u8 reserved_at_80[0x18]; 10812 u8 error[0x8]; 10813 u8 reserved_at_a0[0x160]; 10814 }; 10815 10816 enum { 10817 MLX5_LAG_PORT_SELECT_MODE_QUEUE_AFFINITY = 0, 10818 MLX5_LAG_PORT_SELECT_MODE_PORT_SELECT_FT = 1, 10819 MLX5_LAG_PORT_SELECT_MODE_PORT_SELECT_MPESW = 2, 10820 }; 10821 10822 struct mlx5_ifc_lagc_bits { 10823 u8 fdb_selection_mode[0x1]; 10824 u8 reserved_at_1[0x14]; 10825 u8 port_select_mode[0x3]; 10826 u8 reserved_at_18[0x5]; 10827 u8 lag_state[0x3]; 10828 10829 u8 reserved_at_20[0x14]; 10830 u8 tx_remap_affinity_2[0x4]; 10831 u8 reserved_at_38[0x4]; 10832 u8 tx_remap_affinity_1[0x4]; 10833 }; 10834 10835 struct mlx5_ifc_create_lag_out_bits { 10836 u8 status[0x8]; 10837 u8 reserved_at_8[0x18]; 10838 10839 u8 syndrome[0x20]; 10840 10841 u8 reserved_at_40[0x40]; 10842 }; 10843 10844 struct mlx5_ifc_create_lag_in_bits { 10845 u8 opcode[0x10]; 10846 u8 reserved_at_10[0x10]; 10847 10848 u8 reserved_at_20[0x10]; 10849 u8 op_mod[0x10]; 10850 10851 struct mlx5_ifc_lagc_bits ctx; 10852 }; 10853 10854 struct mlx5_ifc_modify_lag_out_bits { 10855 u8 status[0x8]; 10856 u8 reserved_at_8[0x18]; 10857 10858 u8 syndrome[0x20]; 10859 10860 u8 reserved_at_40[0x40]; 10861 }; 10862 10863 struct mlx5_ifc_modify_lag_in_bits { 10864 u8 opcode[0x10]; 10865 u8 reserved_at_10[0x10]; 10866 10867 u8 reserved_at_20[0x10]; 10868 u8 op_mod[0x10]; 10869 10870 u8 reserved_at_40[0x20]; 10871 u8 field_select[0x20]; 10872 10873 struct mlx5_ifc_lagc_bits ctx; 10874 }; 10875 10876 struct mlx5_ifc_query_lag_out_bits { 10877 u8 status[0x8]; 10878 u8 reserved_at_8[0x18]; 10879 10880 u8 syndrome[0x20]; 10881 10882 struct mlx5_ifc_lagc_bits ctx; 10883 }; 10884 10885 struct mlx5_ifc_query_lag_in_bits { 10886 u8 opcode[0x10]; 10887 u8 reserved_at_10[0x10]; 10888 10889 u8 reserved_at_20[0x10]; 10890 u8 op_mod[0x10]; 10891 10892 u8 reserved_at_40[0x40]; 10893 }; 10894 10895 struct mlx5_ifc_destroy_lag_out_bits { 10896 u8 status[0x8]; 10897 u8 reserved_at_8[0x18]; 10898 10899 u8 syndrome[0x20]; 10900 10901 u8 reserved_at_40[0x40]; 10902 }; 10903 10904 struct mlx5_ifc_destroy_lag_in_bits { 10905 u8 opcode[0x10]; 10906 u8 reserved_at_10[0x10]; 10907 10908 u8 reserved_at_20[0x10]; 10909 u8 op_mod[0x10]; 10910 10911 u8 reserved_at_40[0x40]; 10912 }; 10913 10914 struct mlx5_ifc_create_vport_lag_out_bits { 10915 u8 status[0x8]; 10916 u8 reserved_at_8[0x18]; 10917 10918 u8 syndrome[0x20]; 10919 10920 u8 reserved_at_40[0x40]; 10921 }; 10922 10923 struct mlx5_ifc_create_vport_lag_in_bits { 10924 u8 opcode[0x10]; 10925 u8 reserved_at_10[0x10]; 10926 10927 u8 reserved_at_20[0x10]; 10928 u8 op_mod[0x10]; 10929 10930 u8 reserved_at_40[0x40]; 10931 }; 10932 10933 struct mlx5_ifc_destroy_vport_lag_out_bits { 10934 u8 status[0x8]; 10935 u8 reserved_at_8[0x18]; 10936 10937 u8 syndrome[0x20]; 10938 10939 u8 reserved_at_40[0x40]; 10940 }; 10941 10942 struct mlx5_ifc_destroy_vport_lag_in_bits { 10943 u8 opcode[0x10]; 10944 u8 reserved_at_10[0x10]; 10945 10946 u8 reserved_at_20[0x10]; 10947 u8 op_mod[0x10]; 10948 10949 u8 reserved_at_40[0x40]; 10950 }; 10951 10952 enum { 10953 MLX5_MODIFY_MEMIC_OP_MOD_ALLOC, 10954 MLX5_MODIFY_MEMIC_OP_MOD_DEALLOC, 10955 }; 10956 10957 struct mlx5_ifc_modify_memic_in_bits { 10958 u8 opcode[0x10]; 10959 u8 uid[0x10]; 10960 10961 u8 reserved_at_20[0x10]; 10962 u8 op_mod[0x10]; 10963 10964 u8 reserved_at_40[0x20]; 10965 10966 u8 reserved_at_60[0x18]; 10967 u8 memic_operation_type[0x8]; 10968 10969 u8 memic_start_addr[0x40]; 10970 10971 u8 reserved_at_c0[0x140]; 10972 }; 10973 10974 struct mlx5_ifc_modify_memic_out_bits { 10975 u8 status[0x8]; 10976 u8 reserved_at_8[0x18]; 10977 10978 u8 syndrome[0x20]; 10979 10980 u8 reserved_at_40[0x40]; 10981 10982 u8 memic_operation_addr[0x40]; 10983 10984 u8 reserved_at_c0[0x140]; 10985 }; 10986 10987 struct mlx5_ifc_alloc_memic_in_bits { 10988 u8 opcode[0x10]; 10989 u8 reserved_at_10[0x10]; 10990 10991 u8 reserved_at_20[0x10]; 10992 u8 op_mod[0x10]; 10993 10994 u8 reserved_at_30[0x20]; 10995 10996 u8 reserved_at_40[0x18]; 10997 u8 log_memic_addr_alignment[0x8]; 10998 10999 u8 range_start_addr[0x40]; 11000 11001 u8 range_size[0x20]; 11002 11003 u8 memic_size[0x20]; 11004 }; 11005 11006 struct mlx5_ifc_alloc_memic_out_bits { 11007 u8 status[0x8]; 11008 u8 reserved_at_8[0x18]; 11009 11010 u8 syndrome[0x20]; 11011 11012 u8 memic_start_addr[0x40]; 11013 }; 11014 11015 struct mlx5_ifc_dealloc_memic_in_bits { 11016 u8 opcode[0x10]; 11017 u8 reserved_at_10[0x10]; 11018 11019 u8 reserved_at_20[0x10]; 11020 u8 op_mod[0x10]; 11021 11022 u8 reserved_at_40[0x40]; 11023 11024 u8 memic_start_addr[0x40]; 11025 11026 u8 memic_size[0x20]; 11027 11028 u8 reserved_at_e0[0x20]; 11029 }; 11030 11031 struct mlx5_ifc_dealloc_memic_out_bits { 11032 u8 status[0x8]; 11033 u8 reserved_at_8[0x18]; 11034 11035 u8 syndrome[0x20]; 11036 11037 u8 reserved_at_40[0x40]; 11038 }; 11039 11040 struct mlx5_ifc_umem_bits { 11041 u8 reserved_at_0[0x80]; 11042 11043 u8 reserved_at_80[0x1b]; 11044 u8 log_page_size[0x5]; 11045 11046 u8 page_offset[0x20]; 11047 11048 u8 num_of_mtt[0x40]; 11049 11050 struct mlx5_ifc_mtt_bits mtt[]; 11051 }; 11052 11053 struct mlx5_ifc_uctx_bits { 11054 u8 cap[0x20]; 11055 11056 u8 reserved_at_20[0x160]; 11057 }; 11058 11059 struct mlx5_ifc_sw_icm_bits { 11060 u8 modify_field_select[0x40]; 11061 11062 u8 reserved_at_40[0x18]; 11063 u8 log_sw_icm_size[0x8]; 11064 11065 u8 reserved_at_60[0x20]; 11066 11067 u8 sw_icm_start_addr[0x40]; 11068 11069 u8 reserved_at_c0[0x140]; 11070 }; 11071 11072 struct mlx5_ifc_geneve_tlv_option_bits { 11073 u8 modify_field_select[0x40]; 11074 11075 u8 reserved_at_40[0x18]; 11076 u8 geneve_option_fte_index[0x8]; 11077 11078 u8 option_class[0x10]; 11079 u8 option_type[0x8]; 11080 u8 reserved_at_78[0x3]; 11081 u8 option_data_length[0x5]; 11082 11083 u8 reserved_at_80[0x180]; 11084 }; 11085 11086 struct mlx5_ifc_create_umem_in_bits { 11087 u8 opcode[0x10]; 11088 u8 uid[0x10]; 11089 11090 u8 reserved_at_20[0x10]; 11091 u8 op_mod[0x10]; 11092 11093 u8 reserved_at_40[0x40]; 11094 11095 struct mlx5_ifc_umem_bits umem; 11096 }; 11097 11098 struct mlx5_ifc_create_umem_out_bits { 11099 u8 status[0x8]; 11100 u8 reserved_at_8[0x18]; 11101 11102 u8 syndrome[0x20]; 11103 11104 u8 reserved_at_40[0x8]; 11105 u8 umem_id[0x18]; 11106 11107 u8 reserved_at_60[0x20]; 11108 }; 11109 11110 struct mlx5_ifc_destroy_umem_in_bits { 11111 u8 opcode[0x10]; 11112 u8 uid[0x10]; 11113 11114 u8 reserved_at_20[0x10]; 11115 u8 op_mod[0x10]; 11116 11117 u8 reserved_at_40[0x8]; 11118 u8 umem_id[0x18]; 11119 11120 u8 reserved_at_60[0x20]; 11121 }; 11122 11123 struct mlx5_ifc_destroy_umem_out_bits { 11124 u8 status[0x8]; 11125 u8 reserved_at_8[0x18]; 11126 11127 u8 syndrome[0x20]; 11128 11129 u8 reserved_at_40[0x40]; 11130 }; 11131 11132 struct mlx5_ifc_create_uctx_in_bits { 11133 u8 opcode[0x10]; 11134 u8 reserved_at_10[0x10]; 11135 11136 u8 reserved_at_20[0x10]; 11137 u8 op_mod[0x10]; 11138 11139 u8 reserved_at_40[0x40]; 11140 11141 struct mlx5_ifc_uctx_bits uctx; 11142 }; 11143 11144 struct mlx5_ifc_create_uctx_out_bits { 11145 u8 status[0x8]; 11146 u8 reserved_at_8[0x18]; 11147 11148 u8 syndrome[0x20]; 11149 11150 u8 reserved_at_40[0x10]; 11151 u8 uid[0x10]; 11152 11153 u8 reserved_at_60[0x20]; 11154 }; 11155 11156 struct mlx5_ifc_destroy_uctx_in_bits { 11157 u8 opcode[0x10]; 11158 u8 reserved_at_10[0x10]; 11159 11160 u8 reserved_at_20[0x10]; 11161 u8 op_mod[0x10]; 11162 11163 u8 reserved_at_40[0x10]; 11164 u8 uid[0x10]; 11165 11166 u8 reserved_at_60[0x20]; 11167 }; 11168 11169 struct mlx5_ifc_destroy_uctx_out_bits { 11170 u8 status[0x8]; 11171 u8 reserved_at_8[0x18]; 11172 11173 u8 syndrome[0x20]; 11174 11175 u8 reserved_at_40[0x40]; 11176 }; 11177 11178 struct mlx5_ifc_create_sw_icm_in_bits { 11179 struct mlx5_ifc_general_obj_in_cmd_hdr_bits hdr; 11180 struct mlx5_ifc_sw_icm_bits sw_icm; 11181 }; 11182 11183 struct mlx5_ifc_create_geneve_tlv_option_in_bits { 11184 struct mlx5_ifc_general_obj_in_cmd_hdr_bits hdr; 11185 struct mlx5_ifc_geneve_tlv_option_bits geneve_tlv_opt; 11186 }; 11187 11188 struct mlx5_ifc_mtrc_string_db_param_bits { 11189 u8 string_db_base_address[0x20]; 11190 11191 u8 reserved_at_20[0x8]; 11192 u8 string_db_size[0x18]; 11193 }; 11194 11195 struct mlx5_ifc_mtrc_cap_bits { 11196 u8 trace_owner[0x1]; 11197 u8 trace_to_memory[0x1]; 11198 u8 reserved_at_2[0x4]; 11199 u8 trc_ver[0x2]; 11200 u8 reserved_at_8[0x14]; 11201 u8 num_string_db[0x4]; 11202 11203 u8 first_string_trace[0x8]; 11204 u8 num_string_trace[0x8]; 11205 u8 reserved_at_30[0x28]; 11206 11207 u8 log_max_trace_buffer_size[0x8]; 11208 11209 u8 reserved_at_60[0x20]; 11210 11211 struct mlx5_ifc_mtrc_string_db_param_bits string_db_param[8]; 11212 11213 u8 reserved_at_280[0x180]; 11214 }; 11215 11216 struct mlx5_ifc_mtrc_conf_bits { 11217 u8 reserved_at_0[0x1c]; 11218 u8 trace_mode[0x4]; 11219 u8 reserved_at_20[0x18]; 11220 u8 log_trace_buffer_size[0x8]; 11221 u8 trace_mkey[0x20]; 11222 u8 reserved_at_60[0x3a0]; 11223 }; 11224 11225 struct mlx5_ifc_mtrc_stdb_bits { 11226 u8 string_db_index[0x4]; 11227 u8 reserved_at_4[0x4]; 11228 u8 read_size[0x18]; 11229 u8 start_offset[0x20]; 11230 u8 string_db_data[]; 11231 }; 11232 11233 struct mlx5_ifc_mtrc_ctrl_bits { 11234 u8 trace_status[0x2]; 11235 u8 reserved_at_2[0x2]; 11236 u8 arm_event[0x1]; 11237 u8 reserved_at_5[0xb]; 11238 u8 modify_field_select[0x10]; 11239 u8 reserved_at_20[0x2b]; 11240 u8 current_timestamp52_32[0x15]; 11241 u8 current_timestamp31_0[0x20]; 11242 u8 reserved_at_80[0x180]; 11243 }; 11244 11245 struct mlx5_ifc_host_params_context_bits { 11246 u8 host_number[0x8]; 11247 u8 reserved_at_8[0x7]; 11248 u8 host_pf_disabled[0x1]; 11249 u8 host_num_of_vfs[0x10]; 11250 11251 u8 host_total_vfs[0x10]; 11252 u8 host_pci_bus[0x10]; 11253 11254 u8 reserved_at_40[0x10]; 11255 u8 host_pci_device[0x10]; 11256 11257 u8 reserved_at_60[0x10]; 11258 u8 host_pci_function[0x10]; 11259 11260 u8 reserved_at_80[0x180]; 11261 }; 11262 11263 struct mlx5_ifc_query_esw_functions_in_bits { 11264 u8 opcode[0x10]; 11265 u8 reserved_at_10[0x10]; 11266 11267 u8 reserved_at_20[0x10]; 11268 u8 op_mod[0x10]; 11269 11270 u8 reserved_at_40[0x40]; 11271 }; 11272 11273 struct mlx5_ifc_query_esw_functions_out_bits { 11274 u8 status[0x8]; 11275 u8 reserved_at_8[0x18]; 11276 11277 u8 syndrome[0x20]; 11278 11279 u8 reserved_at_40[0x40]; 11280 11281 struct mlx5_ifc_host_params_context_bits host_params_context; 11282 11283 u8 reserved_at_280[0x180]; 11284 u8 host_sf_enable[][0x40]; 11285 }; 11286 11287 struct mlx5_ifc_sf_partition_bits { 11288 u8 reserved_at_0[0x10]; 11289 u8 log_num_sf[0x8]; 11290 u8 log_sf_bar_size[0x8]; 11291 }; 11292 11293 struct mlx5_ifc_query_sf_partitions_out_bits { 11294 u8 status[0x8]; 11295 u8 reserved_at_8[0x18]; 11296 11297 u8 syndrome[0x20]; 11298 11299 u8 reserved_at_40[0x18]; 11300 u8 num_sf_partitions[0x8]; 11301 11302 u8 reserved_at_60[0x20]; 11303 11304 struct mlx5_ifc_sf_partition_bits sf_partition[]; 11305 }; 11306 11307 struct mlx5_ifc_query_sf_partitions_in_bits { 11308 u8 opcode[0x10]; 11309 u8 reserved_at_10[0x10]; 11310 11311 u8 reserved_at_20[0x10]; 11312 u8 op_mod[0x10]; 11313 11314 u8 reserved_at_40[0x40]; 11315 }; 11316 11317 struct mlx5_ifc_dealloc_sf_out_bits { 11318 u8 status[0x8]; 11319 u8 reserved_at_8[0x18]; 11320 11321 u8 syndrome[0x20]; 11322 11323 u8 reserved_at_40[0x40]; 11324 }; 11325 11326 struct mlx5_ifc_dealloc_sf_in_bits { 11327 u8 opcode[0x10]; 11328 u8 reserved_at_10[0x10]; 11329 11330 u8 reserved_at_20[0x10]; 11331 u8 op_mod[0x10]; 11332 11333 u8 reserved_at_40[0x10]; 11334 u8 function_id[0x10]; 11335 11336 u8 reserved_at_60[0x20]; 11337 }; 11338 11339 struct mlx5_ifc_alloc_sf_out_bits { 11340 u8 status[0x8]; 11341 u8 reserved_at_8[0x18]; 11342 11343 u8 syndrome[0x20]; 11344 11345 u8 reserved_at_40[0x40]; 11346 }; 11347 11348 struct mlx5_ifc_alloc_sf_in_bits { 11349 u8 opcode[0x10]; 11350 u8 reserved_at_10[0x10]; 11351 11352 u8 reserved_at_20[0x10]; 11353 u8 op_mod[0x10]; 11354 11355 u8 reserved_at_40[0x10]; 11356 u8 function_id[0x10]; 11357 11358 u8 reserved_at_60[0x20]; 11359 }; 11360 11361 struct mlx5_ifc_affiliated_event_header_bits { 11362 u8 reserved_at_0[0x10]; 11363 u8 obj_type[0x10]; 11364 11365 u8 obj_id[0x20]; 11366 }; 11367 11368 enum { 11369 MLX5_HCA_CAP_GENERAL_OBJECT_TYPES_ENCRYPTION_KEY = BIT_ULL(0xc), 11370 MLX5_HCA_CAP_GENERAL_OBJECT_TYPES_IPSEC = BIT_ULL(0x13), 11371 MLX5_HCA_CAP_GENERAL_OBJECT_TYPES_SAMPLER = BIT_ULL(0x20), 11372 }; 11373 11374 enum { 11375 MLX5_GENERAL_OBJECT_TYPES_ENCRYPTION_KEY = 0xc, 11376 MLX5_GENERAL_OBJECT_TYPES_IPSEC = 0x13, 11377 MLX5_GENERAL_OBJECT_TYPES_SAMPLER = 0x20, 11378 }; 11379 11380 enum { 11381 MLX5_IPSEC_OBJECT_ICV_LEN_16B, 11382 }; 11383 11384 struct mlx5_ifc_ipsec_obj_bits { 11385 u8 modify_field_select[0x40]; 11386 u8 full_offload[0x1]; 11387 u8 reserved_at_41[0x1]; 11388 u8 esn_en[0x1]; 11389 u8 esn_overlap[0x1]; 11390 u8 reserved_at_44[0x2]; 11391 u8 icv_length[0x2]; 11392 u8 reserved_at_48[0x4]; 11393 u8 aso_return_reg[0x4]; 11394 u8 reserved_at_50[0x10]; 11395 11396 u8 esn_msb[0x20]; 11397 11398 u8 reserved_at_80[0x8]; 11399 u8 dekn[0x18]; 11400 11401 u8 salt[0x20]; 11402 11403 u8 implicit_iv[0x40]; 11404 11405 u8 reserved_at_100[0x700]; 11406 }; 11407 11408 struct mlx5_ifc_create_ipsec_obj_in_bits { 11409 struct mlx5_ifc_general_obj_in_cmd_hdr_bits general_obj_in_cmd_hdr; 11410 struct mlx5_ifc_ipsec_obj_bits ipsec_object; 11411 }; 11412 11413 enum { 11414 MLX5_MODIFY_IPSEC_BITMASK_ESN_OVERLAP = BIT(0), 11415 MLX5_MODIFY_IPSEC_BITMASK_ESN_MSB = BIT(1), 11416 }; 11417 11418 struct mlx5_ifc_query_ipsec_obj_out_bits { 11419 struct mlx5_ifc_general_obj_out_cmd_hdr_bits general_obj_out_cmd_hdr; 11420 struct mlx5_ifc_ipsec_obj_bits ipsec_object; 11421 }; 11422 11423 struct mlx5_ifc_modify_ipsec_obj_in_bits { 11424 struct mlx5_ifc_general_obj_in_cmd_hdr_bits general_obj_in_cmd_hdr; 11425 struct mlx5_ifc_ipsec_obj_bits ipsec_object; 11426 }; 11427 11428 struct mlx5_ifc_encryption_key_obj_bits { 11429 u8 modify_field_select[0x40]; 11430 11431 u8 reserved_at_40[0x14]; 11432 u8 key_size[0x4]; 11433 u8 reserved_at_58[0x4]; 11434 u8 key_type[0x4]; 11435 11436 u8 reserved_at_60[0x8]; 11437 u8 pd[0x18]; 11438 11439 u8 reserved_at_80[0x180]; 11440 u8 key[8][0x20]; 11441 11442 u8 reserved_at_300[0x500]; 11443 }; 11444 11445 struct mlx5_ifc_create_encryption_key_in_bits { 11446 struct mlx5_ifc_general_obj_in_cmd_hdr_bits general_obj_in_cmd_hdr; 11447 struct mlx5_ifc_encryption_key_obj_bits encryption_key_object; 11448 }; 11449 11450 struct mlx5_ifc_sampler_obj_bits { 11451 u8 modify_field_select[0x40]; 11452 11453 u8 table_type[0x8]; 11454 u8 level[0x8]; 11455 u8 reserved_at_50[0xf]; 11456 u8 ignore_flow_level[0x1]; 11457 11458 u8 sample_ratio[0x20]; 11459 11460 u8 reserved_at_80[0x8]; 11461 u8 sample_table_id[0x18]; 11462 11463 u8 reserved_at_a0[0x8]; 11464 u8 default_table_id[0x18]; 11465 11466 u8 sw_steering_icm_address_rx[0x40]; 11467 u8 sw_steering_icm_address_tx[0x40]; 11468 11469 u8 reserved_at_140[0xa0]; 11470 }; 11471 11472 struct mlx5_ifc_create_sampler_obj_in_bits { 11473 struct mlx5_ifc_general_obj_in_cmd_hdr_bits general_obj_in_cmd_hdr; 11474 struct mlx5_ifc_sampler_obj_bits sampler_object; 11475 }; 11476 11477 struct mlx5_ifc_query_sampler_obj_out_bits { 11478 struct mlx5_ifc_general_obj_out_cmd_hdr_bits general_obj_out_cmd_hdr; 11479 struct mlx5_ifc_sampler_obj_bits sampler_object; 11480 }; 11481 11482 enum { 11483 MLX5_GENERAL_OBJECT_TYPE_ENCRYPTION_KEY_KEY_SIZE_128 = 0x0, 11484 MLX5_GENERAL_OBJECT_TYPE_ENCRYPTION_KEY_KEY_SIZE_256 = 0x1, 11485 }; 11486 11487 enum { 11488 MLX5_GENERAL_OBJECT_TYPE_ENCRYPTION_KEY_TYPE_TLS = 0x1, 11489 MLX5_GENERAL_OBJECT_TYPE_ENCRYPTION_KEY_TYPE_IPSEC = 0x2, 11490 }; 11491 11492 struct mlx5_ifc_tls_static_params_bits { 11493 u8 const_2[0x2]; 11494 u8 tls_version[0x4]; 11495 u8 const_1[0x2]; 11496 u8 reserved_at_8[0x14]; 11497 u8 encryption_standard[0x4]; 11498 11499 u8 reserved_at_20[0x20]; 11500 11501 u8 initial_record_number[0x40]; 11502 11503 u8 resync_tcp_sn[0x20]; 11504 11505 u8 gcm_iv[0x20]; 11506 11507 u8 implicit_iv[0x40]; 11508 11509 u8 reserved_at_100[0x8]; 11510 u8 dek_index[0x18]; 11511 11512 u8 reserved_at_120[0xe0]; 11513 }; 11514 11515 struct mlx5_ifc_tls_progress_params_bits { 11516 u8 next_record_tcp_sn[0x20]; 11517 11518 u8 hw_resync_tcp_sn[0x20]; 11519 11520 u8 record_tracker_state[0x2]; 11521 u8 auth_state[0x2]; 11522 u8 reserved_at_44[0x4]; 11523 u8 hw_offset_record_number[0x18]; 11524 }; 11525 11526 enum { 11527 MLX5_MTT_PERM_READ = 1 << 0, 11528 MLX5_MTT_PERM_WRITE = 1 << 1, 11529 MLX5_MTT_PERM_RW = MLX5_MTT_PERM_READ | MLX5_MTT_PERM_WRITE, 11530 }; 11531 11532 enum { 11533 MLX5_SUSPEND_VHCA_IN_OP_MOD_SUSPEND_INITIATOR = 0x0, 11534 MLX5_SUSPEND_VHCA_IN_OP_MOD_SUSPEND_RESPONDER = 0x1, 11535 }; 11536 11537 struct mlx5_ifc_suspend_vhca_in_bits { 11538 u8 opcode[0x10]; 11539 u8 uid[0x10]; 11540 11541 u8 reserved_at_20[0x10]; 11542 u8 op_mod[0x10]; 11543 11544 u8 reserved_at_40[0x10]; 11545 u8 vhca_id[0x10]; 11546 11547 u8 reserved_at_60[0x20]; 11548 }; 11549 11550 struct mlx5_ifc_suspend_vhca_out_bits { 11551 u8 status[0x8]; 11552 u8 reserved_at_8[0x18]; 11553 11554 u8 syndrome[0x20]; 11555 11556 u8 reserved_at_40[0x40]; 11557 }; 11558 11559 enum { 11560 MLX5_RESUME_VHCA_IN_OP_MOD_RESUME_RESPONDER = 0x0, 11561 MLX5_RESUME_VHCA_IN_OP_MOD_RESUME_INITIATOR = 0x1, 11562 }; 11563 11564 struct mlx5_ifc_resume_vhca_in_bits { 11565 u8 opcode[0x10]; 11566 u8 uid[0x10]; 11567 11568 u8 reserved_at_20[0x10]; 11569 u8 op_mod[0x10]; 11570 11571 u8 reserved_at_40[0x10]; 11572 u8 vhca_id[0x10]; 11573 11574 u8 reserved_at_60[0x20]; 11575 }; 11576 11577 struct mlx5_ifc_resume_vhca_out_bits { 11578 u8 status[0x8]; 11579 u8 reserved_at_8[0x18]; 11580 11581 u8 syndrome[0x20]; 11582 11583 u8 reserved_at_40[0x40]; 11584 }; 11585 11586 struct mlx5_ifc_query_vhca_migration_state_in_bits { 11587 u8 opcode[0x10]; 11588 u8 uid[0x10]; 11589 11590 u8 reserved_at_20[0x10]; 11591 u8 op_mod[0x10]; 11592 11593 u8 reserved_at_40[0x10]; 11594 u8 vhca_id[0x10]; 11595 11596 u8 reserved_at_60[0x20]; 11597 }; 11598 11599 struct mlx5_ifc_query_vhca_migration_state_out_bits { 11600 u8 status[0x8]; 11601 u8 reserved_at_8[0x18]; 11602 11603 u8 syndrome[0x20]; 11604 11605 u8 reserved_at_40[0x40]; 11606 11607 u8 required_umem_size[0x20]; 11608 11609 u8 reserved_at_a0[0x160]; 11610 }; 11611 11612 struct mlx5_ifc_save_vhca_state_in_bits { 11613 u8 opcode[0x10]; 11614 u8 uid[0x10]; 11615 11616 u8 reserved_at_20[0x10]; 11617 u8 op_mod[0x10]; 11618 11619 u8 reserved_at_40[0x10]; 11620 u8 vhca_id[0x10]; 11621 11622 u8 reserved_at_60[0x20]; 11623 11624 u8 va[0x40]; 11625 11626 u8 mkey[0x20]; 11627 11628 u8 size[0x20]; 11629 }; 11630 11631 struct mlx5_ifc_save_vhca_state_out_bits { 11632 u8 status[0x8]; 11633 u8 reserved_at_8[0x18]; 11634 11635 u8 syndrome[0x20]; 11636 11637 u8 actual_image_size[0x20]; 11638 11639 u8 reserved_at_60[0x20]; 11640 }; 11641 11642 struct mlx5_ifc_load_vhca_state_in_bits { 11643 u8 opcode[0x10]; 11644 u8 uid[0x10]; 11645 11646 u8 reserved_at_20[0x10]; 11647 u8 op_mod[0x10]; 11648 11649 u8 reserved_at_40[0x10]; 11650 u8 vhca_id[0x10]; 11651 11652 u8 reserved_at_60[0x20]; 11653 11654 u8 va[0x40]; 11655 11656 u8 mkey[0x20]; 11657 11658 u8 size[0x20]; 11659 }; 11660 11661 struct mlx5_ifc_load_vhca_state_out_bits { 11662 u8 status[0x8]; 11663 u8 reserved_at_8[0x18]; 11664 11665 u8 syndrome[0x20]; 11666 11667 u8 reserved_at_40[0x40]; 11668 }; 11669 11670 #endif /* MLX5_IFC_H */ 11671