1 /* 2 * Copyright (c) 2013-2015, Mellanox Technologies, Ltd. All rights reserved. 3 * 4 * This software is available to you under a choice of one of two 5 * licenses. You may choose to be licensed under the terms of the GNU 6 * General Public License (GPL) Version 2, available from the file 7 * COPYING in the main directory of this source tree, or the 8 * OpenIB.org BSD license below: 9 * 10 * Redistribution and use in source and binary forms, with or 11 * without modification, are permitted provided that the following 12 * conditions are met: 13 * 14 * - Redistributions of source code must retain the above 15 * copyright notice, this list of conditions and the following 16 * disclaimer. 17 * 18 * - Redistributions in binary form must reproduce the above 19 * copyright notice, this list of conditions and the following 20 * disclaimer in the documentation and/or other materials 21 * provided with the distribution. 22 * 23 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, 24 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF 25 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND 26 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS 27 * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN 28 * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN 29 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE 30 * SOFTWARE. 31 */ 32 #ifndef MLX5_IFC_H 33 #define MLX5_IFC_H 34 35 #include "mlx5_ifc_fpga.h" 36 37 enum { 38 MLX5_EVENT_TYPE_CODING_COMPLETION_EVENTS = 0x0, 39 MLX5_EVENT_TYPE_CODING_PATH_MIGRATED_SUCCEEDED = 0x1, 40 MLX5_EVENT_TYPE_CODING_COMMUNICATION_ESTABLISHED = 0x2, 41 MLX5_EVENT_TYPE_CODING_SEND_QUEUE_DRAINED = 0x3, 42 MLX5_EVENT_TYPE_CODING_LAST_WQE_REACHED = 0x13, 43 MLX5_EVENT_TYPE_CODING_SRQ_LIMIT = 0x14, 44 MLX5_EVENT_TYPE_CODING_DCT_ALL_CONNECTIONS_CLOSED = 0x1c, 45 MLX5_EVENT_TYPE_CODING_DCT_ACCESS_KEY_VIOLATION = 0x1d, 46 MLX5_EVENT_TYPE_CODING_CQ_ERROR = 0x4, 47 MLX5_EVENT_TYPE_CODING_LOCAL_WQ_CATASTROPHIC_ERROR = 0x5, 48 MLX5_EVENT_TYPE_CODING_PATH_MIGRATION_FAILED = 0x7, 49 MLX5_EVENT_TYPE_CODING_PAGE_FAULT_EVENT = 0xc, 50 MLX5_EVENT_TYPE_CODING_INVALID_REQUEST_LOCAL_WQ_ERROR = 0x10, 51 MLX5_EVENT_TYPE_CODING_LOCAL_ACCESS_VIOLATION_WQ_ERROR = 0x11, 52 MLX5_EVENT_TYPE_CODING_LOCAL_SRQ_CATASTROPHIC_ERROR = 0x12, 53 MLX5_EVENT_TYPE_CODING_INTERNAL_ERROR = 0x8, 54 MLX5_EVENT_TYPE_CODING_PORT_STATE_CHANGE = 0x9, 55 MLX5_EVENT_TYPE_CODING_GPIO_EVENT = 0x15, 56 MLX5_EVENT_TYPE_CODING_REMOTE_CONFIGURATION_PROTOCOL_EVENT = 0x19, 57 MLX5_EVENT_TYPE_CODING_DOORBELL_BLUEFLAME_CONGESTION_EVENT = 0x1a, 58 MLX5_EVENT_TYPE_CODING_STALL_VL_EVENT = 0x1b, 59 MLX5_EVENT_TYPE_CODING_DROPPED_PACKET_LOGGED_EVENT = 0x1f, 60 MLX5_EVENT_TYPE_CODING_COMMAND_INTERFACE_COMPLETION = 0xa, 61 MLX5_EVENT_TYPE_CODING_PAGE_REQUEST = 0xb, 62 MLX5_EVENT_TYPE_CODING_FPGA_ERROR = 0x20, 63 MLX5_EVENT_TYPE_CODING_FPGA_QP_ERROR = 0x21 64 }; 65 66 enum { 67 MLX5_MODIFY_TIR_BITMASK_LRO = 0x0, 68 MLX5_MODIFY_TIR_BITMASK_INDIRECT_TABLE = 0x1, 69 MLX5_MODIFY_TIR_BITMASK_HASH = 0x2, 70 MLX5_MODIFY_TIR_BITMASK_TUNNELED_OFFLOAD_EN = 0x3 71 }; 72 73 enum { 74 MLX5_SET_HCA_CAP_OP_MOD_GENERAL_DEVICE = 0x0, 75 MLX5_SET_HCA_CAP_OP_MOD_ODP = 0x2, 76 MLX5_SET_HCA_CAP_OP_MOD_ATOMIC = 0x3, 77 }; 78 79 enum { 80 MLX5_SHARED_RESOURCE_UID = 0xffff, 81 }; 82 83 enum { 84 MLX5_CMD_OP_QUERY_HCA_CAP = 0x100, 85 MLX5_CMD_OP_QUERY_ADAPTER = 0x101, 86 MLX5_CMD_OP_INIT_HCA = 0x102, 87 MLX5_CMD_OP_TEARDOWN_HCA = 0x103, 88 MLX5_CMD_OP_ENABLE_HCA = 0x104, 89 MLX5_CMD_OP_DISABLE_HCA = 0x105, 90 MLX5_CMD_OP_QUERY_PAGES = 0x107, 91 MLX5_CMD_OP_MANAGE_PAGES = 0x108, 92 MLX5_CMD_OP_SET_HCA_CAP = 0x109, 93 MLX5_CMD_OP_QUERY_ISSI = 0x10a, 94 MLX5_CMD_OP_SET_ISSI = 0x10b, 95 MLX5_CMD_OP_SET_DRIVER_VERSION = 0x10d, 96 MLX5_CMD_OP_CREATE_MKEY = 0x200, 97 MLX5_CMD_OP_QUERY_MKEY = 0x201, 98 MLX5_CMD_OP_DESTROY_MKEY = 0x202, 99 MLX5_CMD_OP_QUERY_SPECIAL_CONTEXTS = 0x203, 100 MLX5_CMD_OP_PAGE_FAULT_RESUME = 0x204, 101 MLX5_CMD_OP_ALLOC_MEMIC = 0x205, 102 MLX5_CMD_OP_DEALLOC_MEMIC = 0x206, 103 MLX5_CMD_OP_CREATE_EQ = 0x301, 104 MLX5_CMD_OP_DESTROY_EQ = 0x302, 105 MLX5_CMD_OP_QUERY_EQ = 0x303, 106 MLX5_CMD_OP_GEN_EQE = 0x304, 107 MLX5_CMD_OP_CREATE_CQ = 0x400, 108 MLX5_CMD_OP_DESTROY_CQ = 0x401, 109 MLX5_CMD_OP_QUERY_CQ = 0x402, 110 MLX5_CMD_OP_MODIFY_CQ = 0x403, 111 MLX5_CMD_OP_CREATE_QP = 0x500, 112 MLX5_CMD_OP_DESTROY_QP = 0x501, 113 MLX5_CMD_OP_RST2INIT_QP = 0x502, 114 MLX5_CMD_OP_INIT2RTR_QP = 0x503, 115 MLX5_CMD_OP_RTR2RTS_QP = 0x504, 116 MLX5_CMD_OP_RTS2RTS_QP = 0x505, 117 MLX5_CMD_OP_SQERR2RTS_QP = 0x506, 118 MLX5_CMD_OP_2ERR_QP = 0x507, 119 MLX5_CMD_OP_2RST_QP = 0x50a, 120 MLX5_CMD_OP_QUERY_QP = 0x50b, 121 MLX5_CMD_OP_SQD_RTS_QP = 0x50c, 122 MLX5_CMD_OP_INIT2INIT_QP = 0x50e, 123 MLX5_CMD_OP_CREATE_PSV = 0x600, 124 MLX5_CMD_OP_DESTROY_PSV = 0x601, 125 MLX5_CMD_OP_CREATE_SRQ = 0x700, 126 MLX5_CMD_OP_DESTROY_SRQ = 0x701, 127 MLX5_CMD_OP_QUERY_SRQ = 0x702, 128 MLX5_CMD_OP_ARM_RQ = 0x703, 129 MLX5_CMD_OP_CREATE_XRC_SRQ = 0x705, 130 MLX5_CMD_OP_DESTROY_XRC_SRQ = 0x706, 131 MLX5_CMD_OP_QUERY_XRC_SRQ = 0x707, 132 MLX5_CMD_OP_ARM_XRC_SRQ = 0x708, 133 MLX5_CMD_OP_CREATE_DCT = 0x710, 134 MLX5_CMD_OP_DESTROY_DCT = 0x711, 135 MLX5_CMD_OP_DRAIN_DCT = 0x712, 136 MLX5_CMD_OP_QUERY_DCT = 0x713, 137 MLX5_CMD_OP_ARM_DCT_FOR_KEY_VIOLATION = 0x714, 138 MLX5_CMD_OP_CREATE_XRQ = 0x717, 139 MLX5_CMD_OP_DESTROY_XRQ = 0x718, 140 MLX5_CMD_OP_QUERY_XRQ = 0x719, 141 MLX5_CMD_OP_ARM_XRQ = 0x71a, 142 MLX5_CMD_OP_QUERY_XRQ_DC_PARAMS_ENTRY = 0x725, 143 MLX5_CMD_OP_SET_XRQ_DC_PARAMS_ENTRY = 0x726, 144 MLX5_CMD_OP_QUERY_XRQ_ERROR_PARAMS = 0x727, 145 MLX5_CMD_OP_QUERY_VPORT_STATE = 0x750, 146 MLX5_CMD_OP_MODIFY_VPORT_STATE = 0x751, 147 MLX5_CMD_OP_QUERY_ESW_VPORT_CONTEXT = 0x752, 148 MLX5_CMD_OP_MODIFY_ESW_VPORT_CONTEXT = 0x753, 149 MLX5_CMD_OP_QUERY_NIC_VPORT_CONTEXT = 0x754, 150 MLX5_CMD_OP_MODIFY_NIC_VPORT_CONTEXT = 0x755, 151 MLX5_CMD_OP_QUERY_ROCE_ADDRESS = 0x760, 152 MLX5_CMD_OP_SET_ROCE_ADDRESS = 0x761, 153 MLX5_CMD_OP_QUERY_HCA_VPORT_CONTEXT = 0x762, 154 MLX5_CMD_OP_MODIFY_HCA_VPORT_CONTEXT = 0x763, 155 MLX5_CMD_OP_QUERY_HCA_VPORT_GID = 0x764, 156 MLX5_CMD_OP_QUERY_HCA_VPORT_PKEY = 0x765, 157 MLX5_CMD_OP_QUERY_VNIC_ENV = 0x76f, 158 MLX5_CMD_OP_QUERY_VPORT_COUNTER = 0x770, 159 MLX5_CMD_OP_ALLOC_Q_COUNTER = 0x771, 160 MLX5_CMD_OP_DEALLOC_Q_COUNTER = 0x772, 161 MLX5_CMD_OP_QUERY_Q_COUNTER = 0x773, 162 MLX5_CMD_OP_SET_MONITOR_COUNTER = 0x774, 163 MLX5_CMD_OP_ARM_MONITOR_COUNTER = 0x775, 164 MLX5_CMD_OP_SET_PP_RATE_LIMIT = 0x780, 165 MLX5_CMD_OP_QUERY_RATE_LIMIT = 0x781, 166 MLX5_CMD_OP_CREATE_SCHEDULING_ELEMENT = 0x782, 167 MLX5_CMD_OP_DESTROY_SCHEDULING_ELEMENT = 0x783, 168 MLX5_CMD_OP_QUERY_SCHEDULING_ELEMENT = 0x784, 169 MLX5_CMD_OP_MODIFY_SCHEDULING_ELEMENT = 0x785, 170 MLX5_CMD_OP_CREATE_QOS_PARA_VPORT = 0x786, 171 MLX5_CMD_OP_DESTROY_QOS_PARA_VPORT = 0x787, 172 MLX5_CMD_OP_ALLOC_PD = 0x800, 173 MLX5_CMD_OP_DEALLOC_PD = 0x801, 174 MLX5_CMD_OP_ALLOC_UAR = 0x802, 175 MLX5_CMD_OP_DEALLOC_UAR = 0x803, 176 MLX5_CMD_OP_CONFIG_INT_MODERATION = 0x804, 177 MLX5_CMD_OP_ACCESS_REG = 0x805, 178 MLX5_CMD_OP_ATTACH_TO_MCG = 0x806, 179 MLX5_CMD_OP_DETACH_FROM_MCG = 0x807, 180 MLX5_CMD_OP_GET_DROPPED_PACKET_LOG = 0x80a, 181 MLX5_CMD_OP_MAD_IFC = 0x50d, 182 MLX5_CMD_OP_QUERY_MAD_DEMUX = 0x80b, 183 MLX5_CMD_OP_SET_MAD_DEMUX = 0x80c, 184 MLX5_CMD_OP_NOP = 0x80d, 185 MLX5_CMD_OP_ALLOC_XRCD = 0x80e, 186 MLX5_CMD_OP_DEALLOC_XRCD = 0x80f, 187 MLX5_CMD_OP_ALLOC_TRANSPORT_DOMAIN = 0x816, 188 MLX5_CMD_OP_DEALLOC_TRANSPORT_DOMAIN = 0x817, 189 MLX5_CMD_OP_QUERY_CONG_STATUS = 0x822, 190 MLX5_CMD_OP_MODIFY_CONG_STATUS = 0x823, 191 MLX5_CMD_OP_QUERY_CONG_PARAMS = 0x824, 192 MLX5_CMD_OP_MODIFY_CONG_PARAMS = 0x825, 193 MLX5_CMD_OP_QUERY_CONG_STATISTICS = 0x826, 194 MLX5_CMD_OP_ADD_VXLAN_UDP_DPORT = 0x827, 195 MLX5_CMD_OP_DELETE_VXLAN_UDP_DPORT = 0x828, 196 MLX5_CMD_OP_SET_L2_TABLE_ENTRY = 0x829, 197 MLX5_CMD_OP_QUERY_L2_TABLE_ENTRY = 0x82a, 198 MLX5_CMD_OP_DELETE_L2_TABLE_ENTRY = 0x82b, 199 MLX5_CMD_OP_SET_WOL_ROL = 0x830, 200 MLX5_CMD_OP_QUERY_WOL_ROL = 0x831, 201 MLX5_CMD_OP_CREATE_LAG = 0x840, 202 MLX5_CMD_OP_MODIFY_LAG = 0x841, 203 MLX5_CMD_OP_QUERY_LAG = 0x842, 204 MLX5_CMD_OP_DESTROY_LAG = 0x843, 205 MLX5_CMD_OP_CREATE_VPORT_LAG = 0x844, 206 MLX5_CMD_OP_DESTROY_VPORT_LAG = 0x845, 207 MLX5_CMD_OP_CREATE_TIR = 0x900, 208 MLX5_CMD_OP_MODIFY_TIR = 0x901, 209 MLX5_CMD_OP_DESTROY_TIR = 0x902, 210 MLX5_CMD_OP_QUERY_TIR = 0x903, 211 MLX5_CMD_OP_CREATE_SQ = 0x904, 212 MLX5_CMD_OP_MODIFY_SQ = 0x905, 213 MLX5_CMD_OP_DESTROY_SQ = 0x906, 214 MLX5_CMD_OP_QUERY_SQ = 0x907, 215 MLX5_CMD_OP_CREATE_RQ = 0x908, 216 MLX5_CMD_OP_MODIFY_RQ = 0x909, 217 MLX5_CMD_OP_SET_DELAY_DROP_PARAMS = 0x910, 218 MLX5_CMD_OP_DESTROY_RQ = 0x90a, 219 MLX5_CMD_OP_QUERY_RQ = 0x90b, 220 MLX5_CMD_OP_CREATE_RMP = 0x90c, 221 MLX5_CMD_OP_MODIFY_RMP = 0x90d, 222 MLX5_CMD_OP_DESTROY_RMP = 0x90e, 223 MLX5_CMD_OP_QUERY_RMP = 0x90f, 224 MLX5_CMD_OP_CREATE_TIS = 0x912, 225 MLX5_CMD_OP_MODIFY_TIS = 0x913, 226 MLX5_CMD_OP_DESTROY_TIS = 0x914, 227 MLX5_CMD_OP_QUERY_TIS = 0x915, 228 MLX5_CMD_OP_CREATE_RQT = 0x916, 229 MLX5_CMD_OP_MODIFY_RQT = 0x917, 230 MLX5_CMD_OP_DESTROY_RQT = 0x918, 231 MLX5_CMD_OP_QUERY_RQT = 0x919, 232 MLX5_CMD_OP_SET_FLOW_TABLE_ROOT = 0x92f, 233 MLX5_CMD_OP_CREATE_FLOW_TABLE = 0x930, 234 MLX5_CMD_OP_DESTROY_FLOW_TABLE = 0x931, 235 MLX5_CMD_OP_QUERY_FLOW_TABLE = 0x932, 236 MLX5_CMD_OP_CREATE_FLOW_GROUP = 0x933, 237 MLX5_CMD_OP_DESTROY_FLOW_GROUP = 0x934, 238 MLX5_CMD_OP_QUERY_FLOW_GROUP = 0x935, 239 MLX5_CMD_OP_SET_FLOW_TABLE_ENTRY = 0x936, 240 MLX5_CMD_OP_QUERY_FLOW_TABLE_ENTRY = 0x937, 241 MLX5_CMD_OP_DELETE_FLOW_TABLE_ENTRY = 0x938, 242 MLX5_CMD_OP_ALLOC_FLOW_COUNTER = 0x939, 243 MLX5_CMD_OP_DEALLOC_FLOW_COUNTER = 0x93a, 244 MLX5_CMD_OP_QUERY_FLOW_COUNTER = 0x93b, 245 MLX5_CMD_OP_MODIFY_FLOW_TABLE = 0x93c, 246 MLX5_CMD_OP_ALLOC_PACKET_REFORMAT_CONTEXT = 0x93d, 247 MLX5_CMD_OP_DEALLOC_PACKET_REFORMAT_CONTEXT = 0x93e, 248 MLX5_CMD_OP_QUERY_PACKET_REFORMAT_CONTEXT = 0x93f, 249 MLX5_CMD_OP_ALLOC_MODIFY_HEADER_CONTEXT = 0x940, 250 MLX5_CMD_OP_DEALLOC_MODIFY_HEADER_CONTEXT = 0x941, 251 MLX5_CMD_OP_QUERY_MODIFY_HEADER_CONTEXT = 0x942, 252 MLX5_CMD_OP_FPGA_CREATE_QP = 0x960, 253 MLX5_CMD_OP_FPGA_MODIFY_QP = 0x961, 254 MLX5_CMD_OP_FPGA_QUERY_QP = 0x962, 255 MLX5_CMD_OP_FPGA_DESTROY_QP = 0x963, 256 MLX5_CMD_OP_FPGA_QUERY_QP_COUNTERS = 0x964, 257 MLX5_CMD_OP_CREATE_GENERAL_OBJECT = 0xa00, 258 MLX5_CMD_OP_MODIFY_GENERAL_OBJECT = 0xa01, 259 MLX5_CMD_OP_QUERY_GENERAL_OBJECT = 0xa02, 260 MLX5_CMD_OP_DESTROY_GENERAL_OBJECT = 0xa03, 261 MLX5_CMD_OP_CREATE_UCTX = 0xa04, 262 MLX5_CMD_OP_DESTROY_UCTX = 0xa06, 263 MLX5_CMD_OP_CREATE_UMEM = 0xa08, 264 MLX5_CMD_OP_DESTROY_UMEM = 0xa0a, 265 MLX5_CMD_OP_MAX 266 }; 267 268 /* Valid range for general commands that don't work over an object */ 269 enum { 270 MLX5_CMD_OP_GENERAL_START = 0xb00, 271 MLX5_CMD_OP_GENERAL_END = 0xd00, 272 }; 273 274 struct mlx5_ifc_flow_table_fields_supported_bits { 275 u8 outer_dmac[0x1]; 276 u8 outer_smac[0x1]; 277 u8 outer_ether_type[0x1]; 278 u8 outer_ip_version[0x1]; 279 u8 outer_first_prio[0x1]; 280 u8 outer_first_cfi[0x1]; 281 u8 outer_first_vid[0x1]; 282 u8 outer_ipv4_ttl[0x1]; 283 u8 outer_second_prio[0x1]; 284 u8 outer_second_cfi[0x1]; 285 u8 outer_second_vid[0x1]; 286 u8 reserved_at_b[0x1]; 287 u8 outer_sip[0x1]; 288 u8 outer_dip[0x1]; 289 u8 outer_frag[0x1]; 290 u8 outer_ip_protocol[0x1]; 291 u8 outer_ip_ecn[0x1]; 292 u8 outer_ip_dscp[0x1]; 293 u8 outer_udp_sport[0x1]; 294 u8 outer_udp_dport[0x1]; 295 u8 outer_tcp_sport[0x1]; 296 u8 outer_tcp_dport[0x1]; 297 u8 outer_tcp_flags[0x1]; 298 u8 outer_gre_protocol[0x1]; 299 u8 outer_gre_key[0x1]; 300 u8 outer_vxlan_vni[0x1]; 301 u8 reserved_at_1a[0x5]; 302 u8 source_eswitch_port[0x1]; 303 304 u8 inner_dmac[0x1]; 305 u8 inner_smac[0x1]; 306 u8 inner_ether_type[0x1]; 307 u8 inner_ip_version[0x1]; 308 u8 inner_first_prio[0x1]; 309 u8 inner_first_cfi[0x1]; 310 u8 inner_first_vid[0x1]; 311 u8 reserved_at_27[0x1]; 312 u8 inner_second_prio[0x1]; 313 u8 inner_second_cfi[0x1]; 314 u8 inner_second_vid[0x1]; 315 u8 reserved_at_2b[0x1]; 316 u8 inner_sip[0x1]; 317 u8 inner_dip[0x1]; 318 u8 inner_frag[0x1]; 319 u8 inner_ip_protocol[0x1]; 320 u8 inner_ip_ecn[0x1]; 321 u8 inner_ip_dscp[0x1]; 322 u8 inner_udp_sport[0x1]; 323 u8 inner_udp_dport[0x1]; 324 u8 inner_tcp_sport[0x1]; 325 u8 inner_tcp_dport[0x1]; 326 u8 inner_tcp_flags[0x1]; 327 u8 reserved_at_37[0x9]; 328 329 u8 reserved_at_40[0x5]; 330 u8 outer_first_mpls_over_udp[0x4]; 331 u8 outer_first_mpls_over_gre[0x4]; 332 u8 inner_first_mpls[0x4]; 333 u8 outer_first_mpls[0x4]; 334 u8 reserved_at_55[0x2]; 335 u8 outer_esp_spi[0x1]; 336 u8 reserved_at_58[0x2]; 337 u8 bth_dst_qp[0x1]; 338 339 u8 reserved_at_5b[0x25]; 340 }; 341 342 struct mlx5_ifc_flow_table_prop_layout_bits { 343 u8 ft_support[0x1]; 344 u8 reserved_at_1[0x1]; 345 u8 flow_counter[0x1]; 346 u8 flow_modify_en[0x1]; 347 u8 modify_root[0x1]; 348 u8 identified_miss_table_mode[0x1]; 349 u8 flow_table_modify[0x1]; 350 u8 reformat[0x1]; 351 u8 decap[0x1]; 352 u8 reserved_at_9[0x1]; 353 u8 pop_vlan[0x1]; 354 u8 push_vlan[0x1]; 355 u8 reserved_at_c[0x1]; 356 u8 pop_vlan_2[0x1]; 357 u8 push_vlan_2[0x1]; 358 u8 reformat_and_vlan_action[0x1]; 359 u8 reserved_at_10[0x2]; 360 u8 reformat_l3_tunnel_to_l2[0x1]; 361 u8 reformat_l2_to_l3_tunnel[0x1]; 362 u8 reformat_and_modify_action[0x1]; 363 u8 reserved_at_15[0xb]; 364 u8 reserved_at_20[0x2]; 365 u8 log_max_ft_size[0x6]; 366 u8 log_max_modify_header_context[0x8]; 367 u8 max_modify_header_actions[0x8]; 368 u8 max_ft_level[0x8]; 369 370 u8 reserved_at_40[0x20]; 371 372 u8 reserved_at_60[0x18]; 373 u8 log_max_ft_num[0x8]; 374 375 u8 reserved_at_80[0x18]; 376 u8 log_max_destination[0x8]; 377 378 u8 log_max_flow_counter[0x8]; 379 u8 reserved_at_a8[0x10]; 380 u8 log_max_flow[0x8]; 381 382 u8 reserved_at_c0[0x40]; 383 384 struct mlx5_ifc_flow_table_fields_supported_bits ft_field_support; 385 386 struct mlx5_ifc_flow_table_fields_supported_bits ft_field_bitmask_support; 387 }; 388 389 struct mlx5_ifc_odp_per_transport_service_cap_bits { 390 u8 send[0x1]; 391 u8 receive[0x1]; 392 u8 write[0x1]; 393 u8 read[0x1]; 394 u8 atomic[0x1]; 395 u8 srq_receive[0x1]; 396 u8 reserved_at_6[0x1a]; 397 }; 398 399 struct mlx5_ifc_fte_match_set_lyr_2_4_bits { 400 u8 smac_47_16[0x20]; 401 402 u8 smac_15_0[0x10]; 403 u8 ethertype[0x10]; 404 405 u8 dmac_47_16[0x20]; 406 407 u8 dmac_15_0[0x10]; 408 u8 first_prio[0x3]; 409 u8 first_cfi[0x1]; 410 u8 first_vid[0xc]; 411 412 u8 ip_protocol[0x8]; 413 u8 ip_dscp[0x6]; 414 u8 ip_ecn[0x2]; 415 u8 cvlan_tag[0x1]; 416 u8 svlan_tag[0x1]; 417 u8 frag[0x1]; 418 u8 ip_version[0x4]; 419 u8 tcp_flags[0x9]; 420 421 u8 tcp_sport[0x10]; 422 u8 tcp_dport[0x10]; 423 424 u8 reserved_at_c0[0x18]; 425 u8 ttl_hoplimit[0x8]; 426 427 u8 udp_sport[0x10]; 428 u8 udp_dport[0x10]; 429 430 union mlx5_ifc_ipv6_layout_ipv4_layout_auto_bits src_ipv4_src_ipv6; 431 432 union mlx5_ifc_ipv6_layout_ipv4_layout_auto_bits dst_ipv4_dst_ipv6; 433 }; 434 435 struct mlx5_ifc_nvgre_key_bits { 436 u8 hi[0x18]; 437 u8 lo[0x8]; 438 }; 439 440 union mlx5_ifc_gre_key_bits { 441 struct mlx5_ifc_nvgre_key_bits nvgre; 442 u8 key[0x20]; 443 }; 444 445 struct mlx5_ifc_fte_match_set_misc_bits { 446 u8 reserved_at_0[0x8]; 447 u8 source_sqn[0x18]; 448 449 u8 source_eswitch_owner_vhca_id[0x10]; 450 u8 source_port[0x10]; 451 452 u8 outer_second_prio[0x3]; 453 u8 outer_second_cfi[0x1]; 454 u8 outer_second_vid[0xc]; 455 u8 inner_second_prio[0x3]; 456 u8 inner_second_cfi[0x1]; 457 u8 inner_second_vid[0xc]; 458 459 u8 outer_second_cvlan_tag[0x1]; 460 u8 inner_second_cvlan_tag[0x1]; 461 u8 outer_second_svlan_tag[0x1]; 462 u8 inner_second_svlan_tag[0x1]; 463 u8 reserved_at_64[0xc]; 464 u8 gre_protocol[0x10]; 465 466 union mlx5_ifc_gre_key_bits gre_key; 467 468 u8 vxlan_vni[0x18]; 469 u8 reserved_at_b8[0x8]; 470 471 u8 reserved_at_c0[0x20]; 472 473 u8 reserved_at_e0[0xc]; 474 u8 outer_ipv6_flow_label[0x14]; 475 476 u8 reserved_at_100[0xc]; 477 u8 inner_ipv6_flow_label[0x14]; 478 479 u8 reserved_at_120[0x28]; 480 u8 bth_dst_qp[0x18]; 481 u8 reserved_at_160[0x20]; 482 u8 outer_esp_spi[0x20]; 483 u8 reserved_at_1a0[0x60]; 484 }; 485 486 struct mlx5_ifc_fte_match_mpls_bits { 487 u8 mpls_label[0x14]; 488 u8 mpls_exp[0x3]; 489 u8 mpls_s_bos[0x1]; 490 u8 mpls_ttl[0x8]; 491 }; 492 493 struct mlx5_ifc_fte_match_set_misc2_bits { 494 struct mlx5_ifc_fte_match_mpls_bits outer_first_mpls; 495 496 struct mlx5_ifc_fte_match_mpls_bits inner_first_mpls; 497 498 struct mlx5_ifc_fte_match_mpls_bits outer_first_mpls_over_gre; 499 500 struct mlx5_ifc_fte_match_mpls_bits outer_first_mpls_over_udp; 501 502 u8 reserved_at_80[0x100]; 503 504 u8 metadata_reg_a[0x20]; 505 506 u8 reserved_at_1a0[0x60]; 507 }; 508 509 struct mlx5_ifc_cmd_pas_bits { 510 u8 pa_h[0x20]; 511 512 u8 pa_l[0x14]; 513 u8 reserved_at_34[0xc]; 514 }; 515 516 struct mlx5_ifc_uint64_bits { 517 u8 hi[0x20]; 518 519 u8 lo[0x20]; 520 }; 521 522 enum { 523 MLX5_ADS_STAT_RATE_NO_LIMIT = 0x0, 524 MLX5_ADS_STAT_RATE_2_5GBPS = 0x7, 525 MLX5_ADS_STAT_RATE_10GBPS = 0x8, 526 MLX5_ADS_STAT_RATE_30GBPS = 0x9, 527 MLX5_ADS_STAT_RATE_5GBPS = 0xa, 528 MLX5_ADS_STAT_RATE_20GBPS = 0xb, 529 MLX5_ADS_STAT_RATE_40GBPS = 0xc, 530 MLX5_ADS_STAT_RATE_60GBPS = 0xd, 531 MLX5_ADS_STAT_RATE_80GBPS = 0xe, 532 MLX5_ADS_STAT_RATE_120GBPS = 0xf, 533 }; 534 535 struct mlx5_ifc_ads_bits { 536 u8 fl[0x1]; 537 u8 free_ar[0x1]; 538 u8 reserved_at_2[0xe]; 539 u8 pkey_index[0x10]; 540 541 u8 reserved_at_20[0x8]; 542 u8 grh[0x1]; 543 u8 mlid[0x7]; 544 u8 rlid[0x10]; 545 546 u8 ack_timeout[0x5]; 547 u8 reserved_at_45[0x3]; 548 u8 src_addr_index[0x8]; 549 u8 reserved_at_50[0x4]; 550 u8 stat_rate[0x4]; 551 u8 hop_limit[0x8]; 552 553 u8 reserved_at_60[0x4]; 554 u8 tclass[0x8]; 555 u8 flow_label[0x14]; 556 557 u8 rgid_rip[16][0x8]; 558 559 u8 reserved_at_100[0x4]; 560 u8 f_dscp[0x1]; 561 u8 f_ecn[0x1]; 562 u8 reserved_at_106[0x1]; 563 u8 f_eth_prio[0x1]; 564 u8 ecn[0x2]; 565 u8 dscp[0x6]; 566 u8 udp_sport[0x10]; 567 568 u8 dei_cfi[0x1]; 569 u8 eth_prio[0x3]; 570 u8 sl[0x4]; 571 u8 vhca_port_num[0x8]; 572 u8 rmac_47_32[0x10]; 573 574 u8 rmac_31_0[0x20]; 575 }; 576 577 struct mlx5_ifc_flow_table_nic_cap_bits { 578 u8 nic_rx_multi_path_tirs[0x1]; 579 u8 nic_rx_multi_path_tirs_fts[0x1]; 580 u8 allow_sniffer_and_nic_rx_shared_tir[0x1]; 581 u8 reserved_at_3[0x1d]; 582 u8 encap_general_header[0x1]; 583 u8 reserved_at_21[0xa]; 584 u8 log_max_packet_reformat_context[0x5]; 585 u8 reserved_at_30[0x6]; 586 u8 max_encap_header_size[0xa]; 587 u8 reserved_at_40[0x1c0]; 588 589 struct mlx5_ifc_flow_table_prop_layout_bits flow_table_properties_nic_receive; 590 591 u8 reserved_at_400[0x200]; 592 593 struct mlx5_ifc_flow_table_prop_layout_bits flow_table_properties_nic_receive_sniffer; 594 595 struct mlx5_ifc_flow_table_prop_layout_bits flow_table_properties_nic_transmit; 596 597 u8 reserved_at_a00[0x200]; 598 599 struct mlx5_ifc_flow_table_prop_layout_bits flow_table_properties_nic_transmit_sniffer; 600 601 u8 reserved_at_e00[0x7200]; 602 }; 603 604 struct mlx5_ifc_flow_table_eswitch_cap_bits { 605 u8 reserved_at_0[0x1a]; 606 u8 multi_fdb_encap[0x1]; 607 u8 reserved_at_1b[0x1]; 608 u8 fdb_multi_path_to_table[0x1]; 609 u8 reserved_at_1d[0x3]; 610 611 u8 reserved_at_20[0x1e0]; 612 613 struct mlx5_ifc_flow_table_prop_layout_bits flow_table_properties_nic_esw_fdb; 614 615 struct mlx5_ifc_flow_table_prop_layout_bits flow_table_properties_esw_acl_ingress; 616 617 struct mlx5_ifc_flow_table_prop_layout_bits flow_table_properties_esw_acl_egress; 618 619 u8 reserved_at_800[0x7800]; 620 }; 621 622 enum { 623 MLX5_COUNTER_SOURCE_ESWITCH = 0x0, 624 MLX5_COUNTER_FLOW_ESWITCH = 0x1, 625 }; 626 627 struct mlx5_ifc_e_switch_cap_bits { 628 u8 vport_svlan_strip[0x1]; 629 u8 vport_cvlan_strip[0x1]; 630 u8 vport_svlan_insert[0x1]; 631 u8 vport_cvlan_insert_if_not_exist[0x1]; 632 u8 vport_cvlan_insert_overwrite[0x1]; 633 u8 reserved_at_5[0x17]; 634 u8 counter_eswitch_affinity[0x1]; 635 u8 merged_eswitch[0x1]; 636 u8 nic_vport_node_guid_modify[0x1]; 637 u8 nic_vport_port_guid_modify[0x1]; 638 639 u8 vxlan_encap_decap[0x1]; 640 u8 nvgre_encap_decap[0x1]; 641 u8 reserved_at_22[0x1]; 642 u8 log_max_fdb_encap_uplink[0x5]; 643 u8 reserved_at_21[0x3]; 644 u8 log_max_packet_reformat_context[0x5]; 645 u8 reserved_2b[0x6]; 646 u8 max_encap_header_size[0xa]; 647 648 u8 reserved_40[0x7c0]; 649 650 }; 651 652 struct mlx5_ifc_qos_cap_bits { 653 u8 packet_pacing[0x1]; 654 u8 esw_scheduling[0x1]; 655 u8 esw_bw_share[0x1]; 656 u8 esw_rate_limit[0x1]; 657 u8 reserved_at_4[0x1]; 658 u8 packet_pacing_burst_bound[0x1]; 659 u8 packet_pacing_typical_size[0x1]; 660 u8 reserved_at_7[0x19]; 661 662 u8 reserved_at_20[0x20]; 663 664 u8 packet_pacing_max_rate[0x20]; 665 666 u8 packet_pacing_min_rate[0x20]; 667 668 u8 reserved_at_80[0x10]; 669 u8 packet_pacing_rate_table_size[0x10]; 670 671 u8 esw_element_type[0x10]; 672 u8 esw_tsar_type[0x10]; 673 674 u8 reserved_at_c0[0x10]; 675 u8 max_qos_para_vport[0x10]; 676 677 u8 max_tsar_bw_share[0x20]; 678 679 u8 reserved_at_100[0x700]; 680 }; 681 682 struct mlx5_ifc_debug_cap_bits { 683 u8 reserved_at_0[0x20]; 684 685 u8 reserved_at_20[0x2]; 686 u8 stall_detect[0x1]; 687 u8 reserved_at_23[0x1d]; 688 689 u8 reserved_at_40[0x7c0]; 690 }; 691 692 struct mlx5_ifc_per_protocol_networking_offload_caps_bits { 693 u8 csum_cap[0x1]; 694 u8 vlan_cap[0x1]; 695 u8 lro_cap[0x1]; 696 u8 lro_psh_flag[0x1]; 697 u8 lro_time_stamp[0x1]; 698 u8 reserved_at_5[0x2]; 699 u8 wqe_vlan_insert[0x1]; 700 u8 self_lb_en_modifiable[0x1]; 701 u8 reserved_at_9[0x2]; 702 u8 max_lso_cap[0x5]; 703 u8 multi_pkt_send_wqe[0x2]; 704 u8 wqe_inline_mode[0x2]; 705 u8 rss_ind_tbl_cap[0x4]; 706 u8 reg_umr_sq[0x1]; 707 u8 scatter_fcs[0x1]; 708 u8 enhanced_multi_pkt_send_wqe[0x1]; 709 u8 tunnel_lso_const_out_ip_id[0x1]; 710 u8 reserved_at_1c[0x2]; 711 u8 tunnel_stateless_gre[0x1]; 712 u8 tunnel_stateless_vxlan[0x1]; 713 714 u8 swp[0x1]; 715 u8 swp_csum[0x1]; 716 u8 swp_lso[0x1]; 717 u8 reserved_at_23[0xd]; 718 u8 max_vxlan_udp_ports[0x8]; 719 u8 reserved_at_38[0x6]; 720 u8 max_geneve_opt_len[0x1]; 721 u8 tunnel_stateless_geneve_rx[0x1]; 722 723 u8 reserved_at_40[0x10]; 724 u8 lro_min_mss_size[0x10]; 725 726 u8 reserved_at_60[0x120]; 727 728 u8 lro_timer_supported_periods[4][0x20]; 729 730 u8 reserved_at_200[0x600]; 731 }; 732 733 struct mlx5_ifc_roce_cap_bits { 734 u8 roce_apm[0x1]; 735 u8 reserved_at_1[0x1f]; 736 737 u8 reserved_at_20[0x60]; 738 739 u8 reserved_at_80[0xc]; 740 u8 l3_type[0x4]; 741 u8 reserved_at_90[0x8]; 742 u8 roce_version[0x8]; 743 744 u8 reserved_at_a0[0x10]; 745 u8 r_roce_dest_udp_port[0x10]; 746 747 u8 r_roce_max_src_udp_port[0x10]; 748 u8 r_roce_min_src_udp_port[0x10]; 749 750 u8 reserved_at_e0[0x10]; 751 u8 roce_address_table_size[0x10]; 752 753 u8 reserved_at_100[0x700]; 754 }; 755 756 struct mlx5_ifc_device_mem_cap_bits { 757 u8 memic[0x1]; 758 u8 reserved_at_1[0x1f]; 759 760 u8 reserved_at_20[0xb]; 761 u8 log_min_memic_alloc_size[0x5]; 762 u8 reserved_at_30[0x8]; 763 u8 log_max_memic_addr_alignment[0x8]; 764 765 u8 memic_bar_start_addr[0x40]; 766 767 u8 memic_bar_size[0x20]; 768 769 u8 max_memic_size[0x20]; 770 771 u8 reserved_at_c0[0x740]; 772 }; 773 774 enum { 775 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_QP_1_BYTE = 0x0, 776 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_QP_2_BYTES = 0x2, 777 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_QP_4_BYTES = 0x4, 778 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_QP_8_BYTES = 0x8, 779 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_QP_16_BYTES = 0x10, 780 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_QP_32_BYTES = 0x20, 781 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_QP_64_BYTES = 0x40, 782 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_QP_128_BYTES = 0x80, 783 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_QP_256_BYTES = 0x100, 784 }; 785 786 enum { 787 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_DC_1_BYTE = 0x1, 788 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_DC_2_BYTES = 0x2, 789 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_DC_4_BYTES = 0x4, 790 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_DC_8_BYTES = 0x8, 791 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_DC_16_BYTES = 0x10, 792 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_DC_32_BYTES = 0x20, 793 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_DC_64_BYTES = 0x40, 794 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_DC_128_BYTES = 0x80, 795 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_DC_256_BYTES = 0x100, 796 }; 797 798 struct mlx5_ifc_atomic_caps_bits { 799 u8 reserved_at_0[0x40]; 800 801 u8 atomic_req_8B_endianness_mode[0x2]; 802 u8 reserved_at_42[0x4]; 803 u8 supported_atomic_req_8B_endianness_mode_1[0x1]; 804 805 u8 reserved_at_47[0x19]; 806 807 u8 reserved_at_60[0x20]; 808 809 u8 reserved_at_80[0x10]; 810 u8 atomic_operations[0x10]; 811 812 u8 reserved_at_a0[0x10]; 813 u8 atomic_size_qp[0x10]; 814 815 u8 reserved_at_c0[0x10]; 816 u8 atomic_size_dc[0x10]; 817 818 u8 reserved_at_e0[0x720]; 819 }; 820 821 struct mlx5_ifc_odp_cap_bits { 822 u8 reserved_at_0[0x40]; 823 824 u8 sig[0x1]; 825 u8 reserved_at_41[0x1f]; 826 827 u8 reserved_at_60[0x20]; 828 829 struct mlx5_ifc_odp_per_transport_service_cap_bits rc_odp_caps; 830 831 struct mlx5_ifc_odp_per_transport_service_cap_bits uc_odp_caps; 832 833 struct mlx5_ifc_odp_per_transport_service_cap_bits ud_odp_caps; 834 835 struct mlx5_ifc_odp_per_transport_service_cap_bits xrc_odp_caps; 836 837 u8 reserved_at_100[0x700]; 838 }; 839 840 struct mlx5_ifc_calc_op { 841 u8 reserved_at_0[0x10]; 842 u8 reserved_at_10[0x9]; 843 u8 op_swap_endianness[0x1]; 844 u8 op_min[0x1]; 845 u8 op_xor[0x1]; 846 u8 op_or[0x1]; 847 u8 op_and[0x1]; 848 u8 op_max[0x1]; 849 u8 op_add[0x1]; 850 }; 851 852 struct mlx5_ifc_vector_calc_cap_bits { 853 u8 calc_matrix[0x1]; 854 u8 reserved_at_1[0x1f]; 855 u8 reserved_at_20[0x8]; 856 u8 max_vec_count[0x8]; 857 u8 reserved_at_30[0xd]; 858 u8 max_chunk_size[0x3]; 859 struct mlx5_ifc_calc_op calc0; 860 struct mlx5_ifc_calc_op calc1; 861 struct mlx5_ifc_calc_op calc2; 862 struct mlx5_ifc_calc_op calc3; 863 864 u8 reserved_at_c0[0x720]; 865 }; 866 867 enum { 868 MLX5_WQ_TYPE_LINKED_LIST = 0x0, 869 MLX5_WQ_TYPE_CYCLIC = 0x1, 870 MLX5_WQ_TYPE_LINKED_LIST_STRIDING_RQ = 0x2, 871 MLX5_WQ_TYPE_CYCLIC_STRIDING_RQ = 0x3, 872 }; 873 874 enum { 875 MLX5_WQ_END_PAD_MODE_NONE = 0x0, 876 MLX5_WQ_END_PAD_MODE_ALIGN = 0x1, 877 }; 878 879 enum { 880 MLX5_CMD_HCA_CAP_GID_TABLE_SIZE_8_GID_ENTRIES = 0x0, 881 MLX5_CMD_HCA_CAP_GID_TABLE_SIZE_16_GID_ENTRIES = 0x1, 882 MLX5_CMD_HCA_CAP_GID_TABLE_SIZE_32_GID_ENTRIES = 0x2, 883 MLX5_CMD_HCA_CAP_GID_TABLE_SIZE_64_GID_ENTRIES = 0x3, 884 MLX5_CMD_HCA_CAP_GID_TABLE_SIZE_128_GID_ENTRIES = 0x4, 885 }; 886 887 enum { 888 MLX5_CMD_HCA_CAP_PKEY_TABLE_SIZE_128_ENTRIES = 0x0, 889 MLX5_CMD_HCA_CAP_PKEY_TABLE_SIZE_256_ENTRIES = 0x1, 890 MLX5_CMD_HCA_CAP_PKEY_TABLE_SIZE_512_ENTRIES = 0x2, 891 MLX5_CMD_HCA_CAP_PKEY_TABLE_SIZE_1K_ENTRIES = 0x3, 892 MLX5_CMD_HCA_CAP_PKEY_TABLE_SIZE_2K_ENTRIES = 0x4, 893 MLX5_CMD_HCA_CAP_PKEY_TABLE_SIZE_4K_ENTRIES = 0x5, 894 }; 895 896 enum { 897 MLX5_CMD_HCA_CAP_PORT_TYPE_IB = 0x0, 898 MLX5_CMD_HCA_CAP_PORT_TYPE_ETHERNET = 0x1, 899 }; 900 901 enum { 902 MLX5_CMD_HCA_CAP_CMDIF_CHECKSUM_DISABLED = 0x0, 903 MLX5_CMD_HCA_CAP_CMDIF_CHECKSUM_INITIAL_STATE = 0x1, 904 MLX5_CMD_HCA_CAP_CMDIF_CHECKSUM_ENABLED = 0x3, 905 }; 906 907 enum { 908 MLX5_CAP_PORT_TYPE_IB = 0x0, 909 MLX5_CAP_PORT_TYPE_ETH = 0x1, 910 }; 911 912 enum { 913 MLX5_CAP_UMR_FENCE_STRONG = 0x0, 914 MLX5_CAP_UMR_FENCE_SMALL = 0x1, 915 MLX5_CAP_UMR_FENCE_NONE = 0x2, 916 }; 917 918 enum { 919 MLX5_UCTX_CAP_RAW_TX = 1UL << 0, 920 }; 921 922 struct mlx5_ifc_cmd_hca_cap_bits { 923 u8 reserved_at_0[0x30]; 924 u8 vhca_id[0x10]; 925 926 u8 reserved_at_40[0x40]; 927 928 u8 log_max_srq_sz[0x8]; 929 u8 log_max_qp_sz[0x8]; 930 u8 reserved_at_90[0xb]; 931 u8 log_max_qp[0x5]; 932 933 u8 reserved_at_a0[0xb]; 934 u8 log_max_srq[0x5]; 935 u8 reserved_at_b0[0x10]; 936 937 u8 reserved_at_c0[0x8]; 938 u8 log_max_cq_sz[0x8]; 939 u8 reserved_at_d0[0xb]; 940 u8 log_max_cq[0x5]; 941 942 u8 log_max_eq_sz[0x8]; 943 u8 reserved_at_e8[0x2]; 944 u8 log_max_mkey[0x6]; 945 u8 reserved_at_f0[0x8]; 946 u8 dump_fill_mkey[0x1]; 947 u8 reserved_at_f9[0x2]; 948 u8 fast_teardown[0x1]; 949 u8 log_max_eq[0x4]; 950 951 u8 max_indirection[0x8]; 952 u8 fixed_buffer_size[0x1]; 953 u8 log_max_mrw_sz[0x7]; 954 u8 force_teardown[0x1]; 955 u8 reserved_at_111[0x1]; 956 u8 log_max_bsf_list_size[0x6]; 957 u8 umr_extended_translation_offset[0x1]; 958 u8 null_mkey[0x1]; 959 u8 log_max_klm_list_size[0x6]; 960 961 u8 reserved_at_120[0xa]; 962 u8 log_max_ra_req_dc[0x6]; 963 u8 reserved_at_130[0xa]; 964 u8 log_max_ra_res_dc[0x6]; 965 966 u8 reserved_at_140[0xa]; 967 u8 log_max_ra_req_qp[0x6]; 968 u8 reserved_at_150[0xa]; 969 u8 log_max_ra_res_qp[0x6]; 970 971 u8 end_pad[0x1]; 972 u8 cc_query_allowed[0x1]; 973 u8 cc_modify_allowed[0x1]; 974 u8 start_pad[0x1]; 975 u8 cache_line_128byte[0x1]; 976 u8 reserved_at_165[0xa]; 977 u8 qcam_reg[0x1]; 978 u8 gid_table_size[0x10]; 979 980 u8 out_of_seq_cnt[0x1]; 981 u8 vport_counters[0x1]; 982 u8 retransmission_q_counters[0x1]; 983 u8 debug[0x1]; 984 u8 modify_rq_counter_set_id[0x1]; 985 u8 rq_delay_drop[0x1]; 986 u8 max_qp_cnt[0xa]; 987 u8 pkey_table_size[0x10]; 988 989 u8 vport_group_manager[0x1]; 990 u8 vhca_group_manager[0x1]; 991 u8 ib_virt[0x1]; 992 u8 eth_virt[0x1]; 993 u8 vnic_env_queue_counters[0x1]; 994 u8 ets[0x1]; 995 u8 nic_flow_table[0x1]; 996 u8 eswitch_manager[0x1]; 997 u8 device_memory[0x1]; 998 u8 mcam_reg[0x1]; 999 u8 pcam_reg[0x1]; 1000 u8 local_ca_ack_delay[0x5]; 1001 u8 port_module_event[0x1]; 1002 u8 enhanced_error_q_counters[0x1]; 1003 u8 ports_check[0x1]; 1004 u8 reserved_at_1b3[0x1]; 1005 u8 disable_link_up[0x1]; 1006 u8 beacon_led[0x1]; 1007 u8 port_type[0x2]; 1008 u8 num_ports[0x8]; 1009 1010 u8 reserved_at_1c0[0x1]; 1011 u8 pps[0x1]; 1012 u8 pps_modify[0x1]; 1013 u8 log_max_msg[0x5]; 1014 u8 reserved_at_1c8[0x4]; 1015 u8 max_tc[0x4]; 1016 u8 temp_warn_event[0x1]; 1017 u8 dcbx[0x1]; 1018 u8 general_notification_event[0x1]; 1019 u8 reserved_at_1d3[0x2]; 1020 u8 fpga[0x1]; 1021 u8 rol_s[0x1]; 1022 u8 rol_g[0x1]; 1023 u8 reserved_at_1d8[0x1]; 1024 u8 wol_s[0x1]; 1025 u8 wol_g[0x1]; 1026 u8 wol_a[0x1]; 1027 u8 wol_b[0x1]; 1028 u8 wol_m[0x1]; 1029 u8 wol_u[0x1]; 1030 u8 wol_p[0x1]; 1031 1032 u8 stat_rate_support[0x10]; 1033 u8 reserved_at_1f0[0xc]; 1034 u8 cqe_version[0x4]; 1035 1036 u8 compact_address_vector[0x1]; 1037 u8 striding_rq[0x1]; 1038 u8 reserved_at_202[0x1]; 1039 u8 ipoib_enhanced_offloads[0x1]; 1040 u8 ipoib_basic_offloads[0x1]; 1041 u8 reserved_at_205[0x1]; 1042 u8 repeated_block_disabled[0x1]; 1043 u8 umr_modify_entity_size_disabled[0x1]; 1044 u8 umr_modify_atomic_disabled[0x1]; 1045 u8 umr_indirect_mkey_disabled[0x1]; 1046 u8 umr_fence[0x2]; 1047 u8 dc_req_scat_data_cqe[0x1]; 1048 u8 reserved_at_20d[0x2]; 1049 u8 drain_sigerr[0x1]; 1050 u8 cmdif_checksum[0x2]; 1051 u8 sigerr_cqe[0x1]; 1052 u8 reserved_at_213[0x1]; 1053 u8 wq_signature[0x1]; 1054 u8 sctr_data_cqe[0x1]; 1055 u8 reserved_at_216[0x1]; 1056 u8 sho[0x1]; 1057 u8 tph[0x1]; 1058 u8 rf[0x1]; 1059 u8 dct[0x1]; 1060 u8 qos[0x1]; 1061 u8 eth_net_offloads[0x1]; 1062 u8 roce[0x1]; 1063 u8 atomic[0x1]; 1064 u8 reserved_at_21f[0x1]; 1065 1066 u8 cq_oi[0x1]; 1067 u8 cq_resize[0x1]; 1068 u8 cq_moderation[0x1]; 1069 u8 reserved_at_223[0x3]; 1070 u8 cq_eq_remap[0x1]; 1071 u8 pg[0x1]; 1072 u8 block_lb_mc[0x1]; 1073 u8 reserved_at_229[0x1]; 1074 u8 scqe_break_moderation[0x1]; 1075 u8 cq_period_start_from_cqe[0x1]; 1076 u8 cd[0x1]; 1077 u8 reserved_at_22d[0x1]; 1078 u8 apm[0x1]; 1079 u8 vector_calc[0x1]; 1080 u8 umr_ptr_rlky[0x1]; 1081 u8 imaicl[0x1]; 1082 u8 qp_packet_based[0x1]; 1083 u8 reserved_at_233[0x3]; 1084 u8 qkv[0x1]; 1085 u8 pkv[0x1]; 1086 u8 set_deth_sqpn[0x1]; 1087 u8 reserved_at_239[0x3]; 1088 u8 xrc[0x1]; 1089 u8 ud[0x1]; 1090 u8 uc[0x1]; 1091 u8 rc[0x1]; 1092 1093 u8 uar_4k[0x1]; 1094 u8 reserved_at_241[0x9]; 1095 u8 uar_sz[0x6]; 1096 u8 reserved_at_250[0x8]; 1097 u8 log_pg_sz[0x8]; 1098 1099 u8 bf[0x1]; 1100 u8 driver_version[0x1]; 1101 u8 pad_tx_eth_packet[0x1]; 1102 u8 reserved_at_263[0x8]; 1103 u8 log_bf_reg_size[0x5]; 1104 1105 u8 reserved_at_270[0xb]; 1106 u8 lag_master[0x1]; 1107 u8 num_lag_ports[0x4]; 1108 1109 u8 reserved_at_280[0x10]; 1110 u8 max_wqe_sz_sq[0x10]; 1111 1112 u8 reserved_at_2a0[0x10]; 1113 u8 max_wqe_sz_rq[0x10]; 1114 1115 u8 max_flow_counter_31_16[0x10]; 1116 u8 max_wqe_sz_sq_dc[0x10]; 1117 1118 u8 reserved_at_2e0[0x7]; 1119 u8 max_qp_mcg[0x19]; 1120 1121 u8 reserved_at_300[0x18]; 1122 u8 log_max_mcg[0x8]; 1123 1124 u8 reserved_at_320[0x3]; 1125 u8 log_max_transport_domain[0x5]; 1126 u8 reserved_at_328[0x3]; 1127 u8 log_max_pd[0x5]; 1128 u8 reserved_at_330[0xb]; 1129 u8 log_max_xrcd[0x5]; 1130 1131 u8 nic_receive_steering_discard[0x1]; 1132 u8 receive_discard_vport_down[0x1]; 1133 u8 transmit_discard_vport_down[0x1]; 1134 u8 reserved_at_343[0x5]; 1135 u8 log_max_flow_counter_bulk[0x8]; 1136 u8 max_flow_counter_15_0[0x10]; 1137 1138 1139 u8 reserved_at_360[0x3]; 1140 u8 log_max_rq[0x5]; 1141 u8 reserved_at_368[0x3]; 1142 u8 log_max_sq[0x5]; 1143 u8 reserved_at_370[0x3]; 1144 u8 log_max_tir[0x5]; 1145 u8 reserved_at_378[0x3]; 1146 u8 log_max_tis[0x5]; 1147 1148 u8 basic_cyclic_rcv_wqe[0x1]; 1149 u8 reserved_at_381[0x2]; 1150 u8 log_max_rmp[0x5]; 1151 u8 reserved_at_388[0x3]; 1152 u8 log_max_rqt[0x5]; 1153 u8 reserved_at_390[0x3]; 1154 u8 log_max_rqt_size[0x5]; 1155 u8 reserved_at_398[0x3]; 1156 u8 log_max_tis_per_sq[0x5]; 1157 1158 u8 ext_stride_num_range[0x1]; 1159 u8 reserved_at_3a1[0x2]; 1160 u8 log_max_stride_sz_rq[0x5]; 1161 u8 reserved_at_3a8[0x3]; 1162 u8 log_min_stride_sz_rq[0x5]; 1163 u8 reserved_at_3b0[0x3]; 1164 u8 log_max_stride_sz_sq[0x5]; 1165 u8 reserved_at_3b8[0x3]; 1166 u8 log_min_stride_sz_sq[0x5]; 1167 1168 u8 hairpin[0x1]; 1169 u8 reserved_at_3c1[0x2]; 1170 u8 log_max_hairpin_queues[0x5]; 1171 u8 reserved_at_3c8[0x3]; 1172 u8 log_max_hairpin_wq_data_sz[0x5]; 1173 u8 reserved_at_3d0[0x3]; 1174 u8 log_max_hairpin_num_packets[0x5]; 1175 u8 reserved_at_3d8[0x3]; 1176 u8 log_max_wq_sz[0x5]; 1177 1178 u8 nic_vport_change_event[0x1]; 1179 u8 disable_local_lb_uc[0x1]; 1180 u8 disable_local_lb_mc[0x1]; 1181 u8 log_min_hairpin_wq_data_sz[0x5]; 1182 u8 reserved_at_3e8[0x3]; 1183 u8 log_max_vlan_list[0x5]; 1184 u8 reserved_at_3f0[0x3]; 1185 u8 log_max_current_mc_list[0x5]; 1186 u8 reserved_at_3f8[0x3]; 1187 u8 log_max_current_uc_list[0x5]; 1188 1189 u8 general_obj_types[0x40]; 1190 1191 u8 reserved_at_440[0x20]; 1192 1193 u8 reserved_at_460[0x3]; 1194 u8 log_max_uctx[0x5]; 1195 u8 reserved_at_468[0x3]; 1196 u8 log_max_umem[0x5]; 1197 u8 max_num_eqs[0x10]; 1198 1199 u8 reserved_at_480[0x3]; 1200 u8 log_max_l2_table[0x5]; 1201 u8 reserved_at_488[0x8]; 1202 u8 log_uar_page_sz[0x10]; 1203 1204 u8 reserved_at_4a0[0x20]; 1205 u8 device_frequency_mhz[0x20]; 1206 u8 device_frequency_khz[0x20]; 1207 1208 u8 reserved_at_500[0x20]; 1209 u8 num_of_uars_per_page[0x20]; 1210 1211 u8 flex_parser_protocols[0x20]; 1212 u8 reserved_at_560[0x20]; 1213 1214 u8 reserved_at_580[0x3c]; 1215 u8 mini_cqe_resp_stride_index[0x1]; 1216 u8 cqe_128_always[0x1]; 1217 u8 cqe_compression_128[0x1]; 1218 u8 cqe_compression[0x1]; 1219 1220 u8 cqe_compression_timeout[0x10]; 1221 u8 cqe_compression_max_num[0x10]; 1222 1223 u8 reserved_at_5e0[0x10]; 1224 u8 tag_matching[0x1]; 1225 u8 rndv_offload_rc[0x1]; 1226 u8 rndv_offload_dc[0x1]; 1227 u8 log_tag_matching_list_sz[0x5]; 1228 u8 reserved_at_5f8[0x3]; 1229 u8 log_max_xrq[0x5]; 1230 1231 u8 affiliate_nic_vport_criteria[0x8]; 1232 u8 native_port_num[0x8]; 1233 u8 num_vhca_ports[0x8]; 1234 u8 reserved_at_618[0x6]; 1235 u8 sw_owner_id[0x1]; 1236 u8 reserved_at_61f[0x1]; 1237 1238 u8 max_num_of_monitor_counters[0x10]; 1239 u8 num_ppcnt_monitor_counters[0x10]; 1240 1241 u8 reserved_at_640[0x10]; 1242 u8 num_q_monitor_counters[0x10]; 1243 1244 u8 reserved_at_660[0x40]; 1245 1246 u8 uctx_cap[0x20]; 1247 1248 u8 reserved_at_6c0[0x140]; 1249 }; 1250 1251 enum mlx5_flow_destination_type { 1252 MLX5_FLOW_DESTINATION_TYPE_VPORT = 0x0, 1253 MLX5_FLOW_DESTINATION_TYPE_FLOW_TABLE = 0x1, 1254 MLX5_FLOW_DESTINATION_TYPE_TIR = 0x2, 1255 1256 MLX5_FLOW_DESTINATION_TYPE_PORT = 0x99, 1257 MLX5_FLOW_DESTINATION_TYPE_COUNTER = 0x100, 1258 MLX5_FLOW_DESTINATION_TYPE_FLOW_TABLE_NUM = 0x101, 1259 }; 1260 1261 struct mlx5_ifc_dest_format_struct_bits { 1262 u8 destination_type[0x8]; 1263 u8 destination_id[0x18]; 1264 1265 u8 destination_eswitch_owner_vhca_id_valid[0x1]; 1266 u8 packet_reformat[0x1]; 1267 u8 reserved_at_22[0xe]; 1268 u8 destination_eswitch_owner_vhca_id[0x10]; 1269 }; 1270 1271 struct mlx5_ifc_flow_counter_list_bits { 1272 u8 flow_counter_id[0x20]; 1273 1274 u8 reserved_at_20[0x20]; 1275 }; 1276 1277 struct mlx5_ifc_extended_dest_format_bits { 1278 struct mlx5_ifc_dest_format_struct_bits destination_entry; 1279 1280 u8 packet_reformat_id[0x20]; 1281 1282 u8 reserved_at_60[0x20]; 1283 }; 1284 1285 union mlx5_ifc_dest_format_struct_flow_counter_list_auto_bits { 1286 struct mlx5_ifc_dest_format_struct_bits dest_format_struct; 1287 struct mlx5_ifc_flow_counter_list_bits flow_counter_list; 1288 u8 reserved_at_0[0x40]; 1289 }; 1290 1291 struct mlx5_ifc_fte_match_param_bits { 1292 struct mlx5_ifc_fte_match_set_lyr_2_4_bits outer_headers; 1293 1294 struct mlx5_ifc_fte_match_set_misc_bits misc_parameters; 1295 1296 struct mlx5_ifc_fte_match_set_lyr_2_4_bits inner_headers; 1297 1298 struct mlx5_ifc_fte_match_set_misc2_bits misc_parameters_2; 1299 1300 u8 reserved_at_800[0x800]; 1301 }; 1302 1303 enum { 1304 MLX5_RX_HASH_FIELD_SELECT_SELECTED_FIELDS_SRC_IP = 0x0, 1305 MLX5_RX_HASH_FIELD_SELECT_SELECTED_FIELDS_DST_IP = 0x1, 1306 MLX5_RX_HASH_FIELD_SELECT_SELECTED_FIELDS_L4_SPORT = 0x2, 1307 MLX5_RX_HASH_FIELD_SELECT_SELECTED_FIELDS_L4_DPORT = 0x3, 1308 MLX5_RX_HASH_FIELD_SELECT_SELECTED_FIELDS_IPSEC_SPI = 0x4, 1309 }; 1310 1311 struct mlx5_ifc_rx_hash_field_select_bits { 1312 u8 l3_prot_type[0x1]; 1313 u8 l4_prot_type[0x1]; 1314 u8 selected_fields[0x1e]; 1315 }; 1316 1317 enum { 1318 MLX5_WQ_WQ_TYPE_WQ_LINKED_LIST = 0x0, 1319 MLX5_WQ_WQ_TYPE_WQ_CYCLIC = 0x1, 1320 }; 1321 1322 enum { 1323 MLX5_WQ_END_PADDING_MODE_END_PAD_NONE = 0x0, 1324 MLX5_WQ_END_PADDING_MODE_END_PAD_ALIGN = 0x1, 1325 }; 1326 1327 struct mlx5_ifc_wq_bits { 1328 u8 wq_type[0x4]; 1329 u8 wq_signature[0x1]; 1330 u8 end_padding_mode[0x2]; 1331 u8 cd_slave[0x1]; 1332 u8 reserved_at_8[0x18]; 1333 1334 u8 hds_skip_first_sge[0x1]; 1335 u8 log2_hds_buf_size[0x3]; 1336 u8 reserved_at_24[0x7]; 1337 u8 page_offset[0x5]; 1338 u8 lwm[0x10]; 1339 1340 u8 reserved_at_40[0x8]; 1341 u8 pd[0x18]; 1342 1343 u8 reserved_at_60[0x8]; 1344 u8 uar_page[0x18]; 1345 1346 u8 dbr_addr[0x40]; 1347 1348 u8 hw_counter[0x20]; 1349 1350 u8 sw_counter[0x20]; 1351 1352 u8 reserved_at_100[0xc]; 1353 u8 log_wq_stride[0x4]; 1354 u8 reserved_at_110[0x3]; 1355 u8 log_wq_pg_sz[0x5]; 1356 u8 reserved_at_118[0x3]; 1357 u8 log_wq_sz[0x5]; 1358 1359 u8 dbr_umem_valid[0x1]; 1360 u8 wq_umem_valid[0x1]; 1361 u8 reserved_at_122[0x1]; 1362 u8 log_hairpin_num_packets[0x5]; 1363 u8 reserved_at_128[0x3]; 1364 u8 log_hairpin_data_sz[0x5]; 1365 1366 u8 reserved_at_130[0x4]; 1367 u8 log_wqe_num_of_strides[0x4]; 1368 u8 two_byte_shift_en[0x1]; 1369 u8 reserved_at_139[0x4]; 1370 u8 log_wqe_stride_size[0x3]; 1371 1372 u8 reserved_at_140[0x4c0]; 1373 1374 struct mlx5_ifc_cmd_pas_bits pas[0]; 1375 }; 1376 1377 struct mlx5_ifc_rq_num_bits { 1378 u8 reserved_at_0[0x8]; 1379 u8 rq_num[0x18]; 1380 }; 1381 1382 struct mlx5_ifc_mac_address_layout_bits { 1383 u8 reserved_at_0[0x10]; 1384 u8 mac_addr_47_32[0x10]; 1385 1386 u8 mac_addr_31_0[0x20]; 1387 }; 1388 1389 struct mlx5_ifc_vlan_layout_bits { 1390 u8 reserved_at_0[0x14]; 1391 u8 vlan[0x0c]; 1392 1393 u8 reserved_at_20[0x20]; 1394 }; 1395 1396 struct mlx5_ifc_cong_control_r_roce_ecn_np_bits { 1397 u8 reserved_at_0[0xa0]; 1398 1399 u8 min_time_between_cnps[0x20]; 1400 1401 u8 reserved_at_c0[0x12]; 1402 u8 cnp_dscp[0x6]; 1403 u8 reserved_at_d8[0x4]; 1404 u8 cnp_prio_mode[0x1]; 1405 u8 cnp_802p_prio[0x3]; 1406 1407 u8 reserved_at_e0[0x720]; 1408 }; 1409 1410 struct mlx5_ifc_cong_control_r_roce_ecn_rp_bits { 1411 u8 reserved_at_0[0x60]; 1412 1413 u8 reserved_at_60[0x4]; 1414 u8 clamp_tgt_rate[0x1]; 1415 u8 reserved_at_65[0x3]; 1416 u8 clamp_tgt_rate_after_time_inc[0x1]; 1417 u8 reserved_at_69[0x17]; 1418 1419 u8 reserved_at_80[0x20]; 1420 1421 u8 rpg_time_reset[0x20]; 1422 1423 u8 rpg_byte_reset[0x20]; 1424 1425 u8 rpg_threshold[0x20]; 1426 1427 u8 rpg_max_rate[0x20]; 1428 1429 u8 rpg_ai_rate[0x20]; 1430 1431 u8 rpg_hai_rate[0x20]; 1432 1433 u8 rpg_gd[0x20]; 1434 1435 u8 rpg_min_dec_fac[0x20]; 1436 1437 u8 rpg_min_rate[0x20]; 1438 1439 u8 reserved_at_1c0[0xe0]; 1440 1441 u8 rate_to_set_on_first_cnp[0x20]; 1442 1443 u8 dce_tcp_g[0x20]; 1444 1445 u8 dce_tcp_rtt[0x20]; 1446 1447 u8 rate_reduce_monitor_period[0x20]; 1448 1449 u8 reserved_at_320[0x20]; 1450 1451 u8 initial_alpha_value[0x20]; 1452 1453 u8 reserved_at_360[0x4a0]; 1454 }; 1455 1456 struct mlx5_ifc_cong_control_802_1qau_rp_bits { 1457 u8 reserved_at_0[0x80]; 1458 1459 u8 rppp_max_rps[0x20]; 1460 1461 u8 rpg_time_reset[0x20]; 1462 1463 u8 rpg_byte_reset[0x20]; 1464 1465 u8 rpg_threshold[0x20]; 1466 1467 u8 rpg_max_rate[0x20]; 1468 1469 u8 rpg_ai_rate[0x20]; 1470 1471 u8 rpg_hai_rate[0x20]; 1472 1473 u8 rpg_gd[0x20]; 1474 1475 u8 rpg_min_dec_fac[0x20]; 1476 1477 u8 rpg_min_rate[0x20]; 1478 1479 u8 reserved_at_1c0[0x640]; 1480 }; 1481 1482 enum { 1483 MLX5_RESIZE_FIELD_SELECT_RESIZE_FIELD_SELECT_LOG_CQ_SIZE = 0x1, 1484 MLX5_RESIZE_FIELD_SELECT_RESIZE_FIELD_SELECT_PAGE_OFFSET = 0x2, 1485 MLX5_RESIZE_FIELD_SELECT_RESIZE_FIELD_SELECT_LOG_PAGE_SIZE = 0x4, 1486 }; 1487 1488 struct mlx5_ifc_resize_field_select_bits { 1489 u8 resize_field_select[0x20]; 1490 }; 1491 1492 enum { 1493 MLX5_MODIFY_FIELD_SELECT_MODIFY_FIELD_SELECT_CQ_PERIOD = 0x1, 1494 MLX5_MODIFY_FIELD_SELECT_MODIFY_FIELD_SELECT_CQ_MAX_COUNT = 0x2, 1495 MLX5_MODIFY_FIELD_SELECT_MODIFY_FIELD_SELECT_OI = 0x4, 1496 MLX5_MODIFY_FIELD_SELECT_MODIFY_FIELD_SELECT_C_EQN = 0x8, 1497 }; 1498 1499 struct mlx5_ifc_modify_field_select_bits { 1500 u8 modify_field_select[0x20]; 1501 }; 1502 1503 struct mlx5_ifc_field_select_r_roce_np_bits { 1504 u8 field_select_r_roce_np[0x20]; 1505 }; 1506 1507 struct mlx5_ifc_field_select_r_roce_rp_bits { 1508 u8 field_select_r_roce_rp[0x20]; 1509 }; 1510 1511 enum { 1512 MLX5_FIELD_SELECT_802_1QAU_RP_FIELD_SELECT_8021QAURP_RPPP_MAX_RPS = 0x4, 1513 MLX5_FIELD_SELECT_802_1QAU_RP_FIELD_SELECT_8021QAURP_RPG_TIME_RESET = 0x8, 1514 MLX5_FIELD_SELECT_802_1QAU_RP_FIELD_SELECT_8021QAURP_RPG_BYTE_RESET = 0x10, 1515 MLX5_FIELD_SELECT_802_1QAU_RP_FIELD_SELECT_8021QAURP_RPG_THRESHOLD = 0x20, 1516 MLX5_FIELD_SELECT_802_1QAU_RP_FIELD_SELECT_8021QAURP_RPG_MAX_RATE = 0x40, 1517 MLX5_FIELD_SELECT_802_1QAU_RP_FIELD_SELECT_8021QAURP_RPG_AI_RATE = 0x80, 1518 MLX5_FIELD_SELECT_802_1QAU_RP_FIELD_SELECT_8021QAURP_RPG_HAI_RATE = 0x100, 1519 MLX5_FIELD_SELECT_802_1QAU_RP_FIELD_SELECT_8021QAURP_RPG_GD = 0x200, 1520 MLX5_FIELD_SELECT_802_1QAU_RP_FIELD_SELECT_8021QAURP_RPG_MIN_DEC_FAC = 0x400, 1521 MLX5_FIELD_SELECT_802_1QAU_RP_FIELD_SELECT_8021QAURP_RPG_MIN_RATE = 0x800, 1522 }; 1523 1524 struct mlx5_ifc_field_select_802_1qau_rp_bits { 1525 u8 field_select_8021qaurp[0x20]; 1526 }; 1527 1528 struct mlx5_ifc_phys_layer_cntrs_bits { 1529 u8 time_since_last_clear_high[0x20]; 1530 1531 u8 time_since_last_clear_low[0x20]; 1532 1533 u8 symbol_errors_high[0x20]; 1534 1535 u8 symbol_errors_low[0x20]; 1536 1537 u8 sync_headers_errors_high[0x20]; 1538 1539 u8 sync_headers_errors_low[0x20]; 1540 1541 u8 edpl_bip_errors_lane0_high[0x20]; 1542 1543 u8 edpl_bip_errors_lane0_low[0x20]; 1544 1545 u8 edpl_bip_errors_lane1_high[0x20]; 1546 1547 u8 edpl_bip_errors_lane1_low[0x20]; 1548 1549 u8 edpl_bip_errors_lane2_high[0x20]; 1550 1551 u8 edpl_bip_errors_lane2_low[0x20]; 1552 1553 u8 edpl_bip_errors_lane3_high[0x20]; 1554 1555 u8 edpl_bip_errors_lane3_low[0x20]; 1556 1557 u8 fc_fec_corrected_blocks_lane0_high[0x20]; 1558 1559 u8 fc_fec_corrected_blocks_lane0_low[0x20]; 1560 1561 u8 fc_fec_corrected_blocks_lane1_high[0x20]; 1562 1563 u8 fc_fec_corrected_blocks_lane1_low[0x20]; 1564 1565 u8 fc_fec_corrected_blocks_lane2_high[0x20]; 1566 1567 u8 fc_fec_corrected_blocks_lane2_low[0x20]; 1568 1569 u8 fc_fec_corrected_blocks_lane3_high[0x20]; 1570 1571 u8 fc_fec_corrected_blocks_lane3_low[0x20]; 1572 1573 u8 fc_fec_uncorrectable_blocks_lane0_high[0x20]; 1574 1575 u8 fc_fec_uncorrectable_blocks_lane0_low[0x20]; 1576 1577 u8 fc_fec_uncorrectable_blocks_lane1_high[0x20]; 1578 1579 u8 fc_fec_uncorrectable_blocks_lane1_low[0x20]; 1580 1581 u8 fc_fec_uncorrectable_blocks_lane2_high[0x20]; 1582 1583 u8 fc_fec_uncorrectable_blocks_lane2_low[0x20]; 1584 1585 u8 fc_fec_uncorrectable_blocks_lane3_high[0x20]; 1586 1587 u8 fc_fec_uncorrectable_blocks_lane3_low[0x20]; 1588 1589 u8 rs_fec_corrected_blocks_high[0x20]; 1590 1591 u8 rs_fec_corrected_blocks_low[0x20]; 1592 1593 u8 rs_fec_uncorrectable_blocks_high[0x20]; 1594 1595 u8 rs_fec_uncorrectable_blocks_low[0x20]; 1596 1597 u8 rs_fec_no_errors_blocks_high[0x20]; 1598 1599 u8 rs_fec_no_errors_blocks_low[0x20]; 1600 1601 u8 rs_fec_single_error_blocks_high[0x20]; 1602 1603 u8 rs_fec_single_error_blocks_low[0x20]; 1604 1605 u8 rs_fec_corrected_symbols_total_high[0x20]; 1606 1607 u8 rs_fec_corrected_symbols_total_low[0x20]; 1608 1609 u8 rs_fec_corrected_symbols_lane0_high[0x20]; 1610 1611 u8 rs_fec_corrected_symbols_lane0_low[0x20]; 1612 1613 u8 rs_fec_corrected_symbols_lane1_high[0x20]; 1614 1615 u8 rs_fec_corrected_symbols_lane1_low[0x20]; 1616 1617 u8 rs_fec_corrected_symbols_lane2_high[0x20]; 1618 1619 u8 rs_fec_corrected_symbols_lane2_low[0x20]; 1620 1621 u8 rs_fec_corrected_symbols_lane3_high[0x20]; 1622 1623 u8 rs_fec_corrected_symbols_lane3_low[0x20]; 1624 1625 u8 link_down_events[0x20]; 1626 1627 u8 successful_recovery_events[0x20]; 1628 1629 u8 reserved_at_640[0x180]; 1630 }; 1631 1632 struct mlx5_ifc_phys_layer_statistical_cntrs_bits { 1633 u8 time_since_last_clear_high[0x20]; 1634 1635 u8 time_since_last_clear_low[0x20]; 1636 1637 u8 phy_received_bits_high[0x20]; 1638 1639 u8 phy_received_bits_low[0x20]; 1640 1641 u8 phy_symbol_errors_high[0x20]; 1642 1643 u8 phy_symbol_errors_low[0x20]; 1644 1645 u8 phy_corrected_bits_high[0x20]; 1646 1647 u8 phy_corrected_bits_low[0x20]; 1648 1649 u8 phy_corrected_bits_lane0_high[0x20]; 1650 1651 u8 phy_corrected_bits_lane0_low[0x20]; 1652 1653 u8 phy_corrected_bits_lane1_high[0x20]; 1654 1655 u8 phy_corrected_bits_lane1_low[0x20]; 1656 1657 u8 phy_corrected_bits_lane2_high[0x20]; 1658 1659 u8 phy_corrected_bits_lane2_low[0x20]; 1660 1661 u8 phy_corrected_bits_lane3_high[0x20]; 1662 1663 u8 phy_corrected_bits_lane3_low[0x20]; 1664 1665 u8 reserved_at_200[0x5c0]; 1666 }; 1667 1668 struct mlx5_ifc_ib_port_cntrs_grp_data_layout_bits { 1669 u8 symbol_error_counter[0x10]; 1670 1671 u8 link_error_recovery_counter[0x8]; 1672 1673 u8 link_downed_counter[0x8]; 1674 1675 u8 port_rcv_errors[0x10]; 1676 1677 u8 port_rcv_remote_physical_errors[0x10]; 1678 1679 u8 port_rcv_switch_relay_errors[0x10]; 1680 1681 u8 port_xmit_discards[0x10]; 1682 1683 u8 port_xmit_constraint_errors[0x8]; 1684 1685 u8 port_rcv_constraint_errors[0x8]; 1686 1687 u8 reserved_at_70[0x8]; 1688 1689 u8 link_overrun_errors[0x8]; 1690 1691 u8 reserved_at_80[0x10]; 1692 1693 u8 vl_15_dropped[0x10]; 1694 1695 u8 reserved_at_a0[0x80]; 1696 1697 u8 port_xmit_wait[0x20]; 1698 }; 1699 1700 struct mlx5_ifc_eth_per_traffic_grp_data_layout_bits { 1701 u8 transmit_queue_high[0x20]; 1702 1703 u8 transmit_queue_low[0x20]; 1704 1705 u8 reserved_at_40[0x780]; 1706 }; 1707 1708 struct mlx5_ifc_eth_per_prio_grp_data_layout_bits { 1709 u8 rx_octets_high[0x20]; 1710 1711 u8 rx_octets_low[0x20]; 1712 1713 u8 reserved_at_40[0xc0]; 1714 1715 u8 rx_frames_high[0x20]; 1716 1717 u8 rx_frames_low[0x20]; 1718 1719 u8 tx_octets_high[0x20]; 1720 1721 u8 tx_octets_low[0x20]; 1722 1723 u8 reserved_at_180[0xc0]; 1724 1725 u8 tx_frames_high[0x20]; 1726 1727 u8 tx_frames_low[0x20]; 1728 1729 u8 rx_pause_high[0x20]; 1730 1731 u8 rx_pause_low[0x20]; 1732 1733 u8 rx_pause_duration_high[0x20]; 1734 1735 u8 rx_pause_duration_low[0x20]; 1736 1737 u8 tx_pause_high[0x20]; 1738 1739 u8 tx_pause_low[0x20]; 1740 1741 u8 tx_pause_duration_high[0x20]; 1742 1743 u8 tx_pause_duration_low[0x20]; 1744 1745 u8 rx_pause_transition_high[0x20]; 1746 1747 u8 rx_pause_transition_low[0x20]; 1748 1749 u8 reserved_at_3c0[0x40]; 1750 1751 u8 device_stall_minor_watermark_cnt_high[0x20]; 1752 1753 u8 device_stall_minor_watermark_cnt_low[0x20]; 1754 1755 u8 device_stall_critical_watermark_cnt_high[0x20]; 1756 1757 u8 device_stall_critical_watermark_cnt_low[0x20]; 1758 1759 u8 reserved_at_480[0x340]; 1760 }; 1761 1762 struct mlx5_ifc_eth_extended_cntrs_grp_data_layout_bits { 1763 u8 port_transmit_wait_high[0x20]; 1764 1765 u8 port_transmit_wait_low[0x20]; 1766 1767 u8 reserved_at_40[0x100]; 1768 1769 u8 rx_buffer_almost_full_high[0x20]; 1770 1771 u8 rx_buffer_almost_full_low[0x20]; 1772 1773 u8 rx_buffer_full_high[0x20]; 1774 1775 u8 rx_buffer_full_low[0x20]; 1776 1777 u8 rx_icrc_encapsulated_high[0x20]; 1778 1779 u8 rx_icrc_encapsulated_low[0x20]; 1780 1781 u8 reserved_at_200[0x5c0]; 1782 }; 1783 1784 struct mlx5_ifc_eth_3635_cntrs_grp_data_layout_bits { 1785 u8 dot3stats_alignment_errors_high[0x20]; 1786 1787 u8 dot3stats_alignment_errors_low[0x20]; 1788 1789 u8 dot3stats_fcs_errors_high[0x20]; 1790 1791 u8 dot3stats_fcs_errors_low[0x20]; 1792 1793 u8 dot3stats_single_collision_frames_high[0x20]; 1794 1795 u8 dot3stats_single_collision_frames_low[0x20]; 1796 1797 u8 dot3stats_multiple_collision_frames_high[0x20]; 1798 1799 u8 dot3stats_multiple_collision_frames_low[0x20]; 1800 1801 u8 dot3stats_sqe_test_errors_high[0x20]; 1802 1803 u8 dot3stats_sqe_test_errors_low[0x20]; 1804 1805 u8 dot3stats_deferred_transmissions_high[0x20]; 1806 1807 u8 dot3stats_deferred_transmissions_low[0x20]; 1808 1809 u8 dot3stats_late_collisions_high[0x20]; 1810 1811 u8 dot3stats_late_collisions_low[0x20]; 1812 1813 u8 dot3stats_excessive_collisions_high[0x20]; 1814 1815 u8 dot3stats_excessive_collisions_low[0x20]; 1816 1817 u8 dot3stats_internal_mac_transmit_errors_high[0x20]; 1818 1819 u8 dot3stats_internal_mac_transmit_errors_low[0x20]; 1820 1821 u8 dot3stats_carrier_sense_errors_high[0x20]; 1822 1823 u8 dot3stats_carrier_sense_errors_low[0x20]; 1824 1825 u8 dot3stats_frame_too_longs_high[0x20]; 1826 1827 u8 dot3stats_frame_too_longs_low[0x20]; 1828 1829 u8 dot3stats_internal_mac_receive_errors_high[0x20]; 1830 1831 u8 dot3stats_internal_mac_receive_errors_low[0x20]; 1832 1833 u8 dot3stats_symbol_errors_high[0x20]; 1834 1835 u8 dot3stats_symbol_errors_low[0x20]; 1836 1837 u8 dot3control_in_unknown_opcodes_high[0x20]; 1838 1839 u8 dot3control_in_unknown_opcodes_low[0x20]; 1840 1841 u8 dot3in_pause_frames_high[0x20]; 1842 1843 u8 dot3in_pause_frames_low[0x20]; 1844 1845 u8 dot3out_pause_frames_high[0x20]; 1846 1847 u8 dot3out_pause_frames_low[0x20]; 1848 1849 u8 reserved_at_400[0x3c0]; 1850 }; 1851 1852 struct mlx5_ifc_eth_2819_cntrs_grp_data_layout_bits { 1853 u8 ether_stats_drop_events_high[0x20]; 1854 1855 u8 ether_stats_drop_events_low[0x20]; 1856 1857 u8 ether_stats_octets_high[0x20]; 1858 1859 u8 ether_stats_octets_low[0x20]; 1860 1861 u8 ether_stats_pkts_high[0x20]; 1862 1863 u8 ether_stats_pkts_low[0x20]; 1864 1865 u8 ether_stats_broadcast_pkts_high[0x20]; 1866 1867 u8 ether_stats_broadcast_pkts_low[0x20]; 1868 1869 u8 ether_stats_multicast_pkts_high[0x20]; 1870 1871 u8 ether_stats_multicast_pkts_low[0x20]; 1872 1873 u8 ether_stats_crc_align_errors_high[0x20]; 1874 1875 u8 ether_stats_crc_align_errors_low[0x20]; 1876 1877 u8 ether_stats_undersize_pkts_high[0x20]; 1878 1879 u8 ether_stats_undersize_pkts_low[0x20]; 1880 1881 u8 ether_stats_oversize_pkts_high[0x20]; 1882 1883 u8 ether_stats_oversize_pkts_low[0x20]; 1884 1885 u8 ether_stats_fragments_high[0x20]; 1886 1887 u8 ether_stats_fragments_low[0x20]; 1888 1889 u8 ether_stats_jabbers_high[0x20]; 1890 1891 u8 ether_stats_jabbers_low[0x20]; 1892 1893 u8 ether_stats_collisions_high[0x20]; 1894 1895 u8 ether_stats_collisions_low[0x20]; 1896 1897 u8 ether_stats_pkts64octets_high[0x20]; 1898 1899 u8 ether_stats_pkts64octets_low[0x20]; 1900 1901 u8 ether_stats_pkts65to127octets_high[0x20]; 1902 1903 u8 ether_stats_pkts65to127octets_low[0x20]; 1904 1905 u8 ether_stats_pkts128to255octets_high[0x20]; 1906 1907 u8 ether_stats_pkts128to255octets_low[0x20]; 1908 1909 u8 ether_stats_pkts256to511octets_high[0x20]; 1910 1911 u8 ether_stats_pkts256to511octets_low[0x20]; 1912 1913 u8 ether_stats_pkts512to1023octets_high[0x20]; 1914 1915 u8 ether_stats_pkts512to1023octets_low[0x20]; 1916 1917 u8 ether_stats_pkts1024to1518octets_high[0x20]; 1918 1919 u8 ether_stats_pkts1024to1518octets_low[0x20]; 1920 1921 u8 ether_stats_pkts1519to2047octets_high[0x20]; 1922 1923 u8 ether_stats_pkts1519to2047octets_low[0x20]; 1924 1925 u8 ether_stats_pkts2048to4095octets_high[0x20]; 1926 1927 u8 ether_stats_pkts2048to4095octets_low[0x20]; 1928 1929 u8 ether_stats_pkts4096to8191octets_high[0x20]; 1930 1931 u8 ether_stats_pkts4096to8191octets_low[0x20]; 1932 1933 u8 ether_stats_pkts8192to10239octets_high[0x20]; 1934 1935 u8 ether_stats_pkts8192to10239octets_low[0x20]; 1936 1937 u8 reserved_at_540[0x280]; 1938 }; 1939 1940 struct mlx5_ifc_eth_2863_cntrs_grp_data_layout_bits { 1941 u8 if_in_octets_high[0x20]; 1942 1943 u8 if_in_octets_low[0x20]; 1944 1945 u8 if_in_ucast_pkts_high[0x20]; 1946 1947 u8 if_in_ucast_pkts_low[0x20]; 1948 1949 u8 if_in_discards_high[0x20]; 1950 1951 u8 if_in_discards_low[0x20]; 1952 1953 u8 if_in_errors_high[0x20]; 1954 1955 u8 if_in_errors_low[0x20]; 1956 1957 u8 if_in_unknown_protos_high[0x20]; 1958 1959 u8 if_in_unknown_protos_low[0x20]; 1960 1961 u8 if_out_octets_high[0x20]; 1962 1963 u8 if_out_octets_low[0x20]; 1964 1965 u8 if_out_ucast_pkts_high[0x20]; 1966 1967 u8 if_out_ucast_pkts_low[0x20]; 1968 1969 u8 if_out_discards_high[0x20]; 1970 1971 u8 if_out_discards_low[0x20]; 1972 1973 u8 if_out_errors_high[0x20]; 1974 1975 u8 if_out_errors_low[0x20]; 1976 1977 u8 if_in_multicast_pkts_high[0x20]; 1978 1979 u8 if_in_multicast_pkts_low[0x20]; 1980 1981 u8 if_in_broadcast_pkts_high[0x20]; 1982 1983 u8 if_in_broadcast_pkts_low[0x20]; 1984 1985 u8 if_out_multicast_pkts_high[0x20]; 1986 1987 u8 if_out_multicast_pkts_low[0x20]; 1988 1989 u8 if_out_broadcast_pkts_high[0x20]; 1990 1991 u8 if_out_broadcast_pkts_low[0x20]; 1992 1993 u8 reserved_at_340[0x480]; 1994 }; 1995 1996 struct mlx5_ifc_eth_802_3_cntrs_grp_data_layout_bits { 1997 u8 a_frames_transmitted_ok_high[0x20]; 1998 1999 u8 a_frames_transmitted_ok_low[0x20]; 2000 2001 u8 a_frames_received_ok_high[0x20]; 2002 2003 u8 a_frames_received_ok_low[0x20]; 2004 2005 u8 a_frame_check_sequence_errors_high[0x20]; 2006 2007 u8 a_frame_check_sequence_errors_low[0x20]; 2008 2009 u8 a_alignment_errors_high[0x20]; 2010 2011 u8 a_alignment_errors_low[0x20]; 2012 2013 u8 a_octets_transmitted_ok_high[0x20]; 2014 2015 u8 a_octets_transmitted_ok_low[0x20]; 2016 2017 u8 a_octets_received_ok_high[0x20]; 2018 2019 u8 a_octets_received_ok_low[0x20]; 2020 2021 u8 a_multicast_frames_xmitted_ok_high[0x20]; 2022 2023 u8 a_multicast_frames_xmitted_ok_low[0x20]; 2024 2025 u8 a_broadcast_frames_xmitted_ok_high[0x20]; 2026 2027 u8 a_broadcast_frames_xmitted_ok_low[0x20]; 2028 2029 u8 a_multicast_frames_received_ok_high[0x20]; 2030 2031 u8 a_multicast_frames_received_ok_low[0x20]; 2032 2033 u8 a_broadcast_frames_received_ok_high[0x20]; 2034 2035 u8 a_broadcast_frames_received_ok_low[0x20]; 2036 2037 u8 a_in_range_length_errors_high[0x20]; 2038 2039 u8 a_in_range_length_errors_low[0x20]; 2040 2041 u8 a_out_of_range_length_field_high[0x20]; 2042 2043 u8 a_out_of_range_length_field_low[0x20]; 2044 2045 u8 a_frame_too_long_errors_high[0x20]; 2046 2047 u8 a_frame_too_long_errors_low[0x20]; 2048 2049 u8 a_symbol_error_during_carrier_high[0x20]; 2050 2051 u8 a_symbol_error_during_carrier_low[0x20]; 2052 2053 u8 a_mac_control_frames_transmitted_high[0x20]; 2054 2055 u8 a_mac_control_frames_transmitted_low[0x20]; 2056 2057 u8 a_mac_control_frames_received_high[0x20]; 2058 2059 u8 a_mac_control_frames_received_low[0x20]; 2060 2061 u8 a_unsupported_opcodes_received_high[0x20]; 2062 2063 u8 a_unsupported_opcodes_received_low[0x20]; 2064 2065 u8 a_pause_mac_ctrl_frames_received_high[0x20]; 2066 2067 u8 a_pause_mac_ctrl_frames_received_low[0x20]; 2068 2069 u8 a_pause_mac_ctrl_frames_transmitted_high[0x20]; 2070 2071 u8 a_pause_mac_ctrl_frames_transmitted_low[0x20]; 2072 2073 u8 reserved_at_4c0[0x300]; 2074 }; 2075 2076 struct mlx5_ifc_pcie_perf_cntrs_grp_data_layout_bits { 2077 u8 life_time_counter_high[0x20]; 2078 2079 u8 life_time_counter_low[0x20]; 2080 2081 u8 rx_errors[0x20]; 2082 2083 u8 tx_errors[0x20]; 2084 2085 u8 l0_to_recovery_eieos[0x20]; 2086 2087 u8 l0_to_recovery_ts[0x20]; 2088 2089 u8 l0_to_recovery_framing[0x20]; 2090 2091 u8 l0_to_recovery_retrain[0x20]; 2092 2093 u8 crc_error_dllp[0x20]; 2094 2095 u8 crc_error_tlp[0x20]; 2096 2097 u8 tx_overflow_buffer_pkt_high[0x20]; 2098 2099 u8 tx_overflow_buffer_pkt_low[0x20]; 2100 2101 u8 outbound_stalled_reads[0x20]; 2102 2103 u8 outbound_stalled_writes[0x20]; 2104 2105 u8 outbound_stalled_reads_events[0x20]; 2106 2107 u8 outbound_stalled_writes_events[0x20]; 2108 2109 u8 reserved_at_200[0x5c0]; 2110 }; 2111 2112 struct mlx5_ifc_cmd_inter_comp_event_bits { 2113 u8 command_completion_vector[0x20]; 2114 2115 u8 reserved_at_20[0xc0]; 2116 }; 2117 2118 struct mlx5_ifc_stall_vl_event_bits { 2119 u8 reserved_at_0[0x18]; 2120 u8 port_num[0x1]; 2121 u8 reserved_at_19[0x3]; 2122 u8 vl[0x4]; 2123 2124 u8 reserved_at_20[0xa0]; 2125 }; 2126 2127 struct mlx5_ifc_db_bf_congestion_event_bits { 2128 u8 event_subtype[0x8]; 2129 u8 reserved_at_8[0x8]; 2130 u8 congestion_level[0x8]; 2131 u8 reserved_at_18[0x8]; 2132 2133 u8 reserved_at_20[0xa0]; 2134 }; 2135 2136 struct mlx5_ifc_gpio_event_bits { 2137 u8 reserved_at_0[0x60]; 2138 2139 u8 gpio_event_hi[0x20]; 2140 2141 u8 gpio_event_lo[0x20]; 2142 2143 u8 reserved_at_a0[0x40]; 2144 }; 2145 2146 struct mlx5_ifc_port_state_change_event_bits { 2147 u8 reserved_at_0[0x40]; 2148 2149 u8 port_num[0x4]; 2150 u8 reserved_at_44[0x1c]; 2151 2152 u8 reserved_at_60[0x80]; 2153 }; 2154 2155 struct mlx5_ifc_dropped_packet_logged_bits { 2156 u8 reserved_at_0[0xe0]; 2157 }; 2158 2159 enum { 2160 MLX5_CQ_ERROR_SYNDROME_CQ_OVERRUN = 0x1, 2161 MLX5_CQ_ERROR_SYNDROME_CQ_ACCESS_VIOLATION_ERROR = 0x2, 2162 }; 2163 2164 struct mlx5_ifc_cq_error_bits { 2165 u8 reserved_at_0[0x8]; 2166 u8 cqn[0x18]; 2167 2168 u8 reserved_at_20[0x20]; 2169 2170 u8 reserved_at_40[0x18]; 2171 u8 syndrome[0x8]; 2172 2173 u8 reserved_at_60[0x80]; 2174 }; 2175 2176 struct mlx5_ifc_rdma_page_fault_event_bits { 2177 u8 bytes_committed[0x20]; 2178 2179 u8 r_key[0x20]; 2180 2181 u8 reserved_at_40[0x10]; 2182 u8 packet_len[0x10]; 2183 2184 u8 rdma_op_len[0x20]; 2185 2186 u8 rdma_va[0x40]; 2187 2188 u8 reserved_at_c0[0x5]; 2189 u8 rdma[0x1]; 2190 u8 write[0x1]; 2191 u8 requestor[0x1]; 2192 u8 qp_number[0x18]; 2193 }; 2194 2195 struct mlx5_ifc_wqe_associated_page_fault_event_bits { 2196 u8 bytes_committed[0x20]; 2197 2198 u8 reserved_at_20[0x10]; 2199 u8 wqe_index[0x10]; 2200 2201 u8 reserved_at_40[0x10]; 2202 u8 len[0x10]; 2203 2204 u8 reserved_at_60[0x60]; 2205 2206 u8 reserved_at_c0[0x5]; 2207 u8 rdma[0x1]; 2208 u8 write_read[0x1]; 2209 u8 requestor[0x1]; 2210 u8 qpn[0x18]; 2211 }; 2212 2213 struct mlx5_ifc_qp_events_bits { 2214 u8 reserved_at_0[0xa0]; 2215 2216 u8 type[0x8]; 2217 u8 reserved_at_a8[0x18]; 2218 2219 u8 reserved_at_c0[0x8]; 2220 u8 qpn_rqn_sqn[0x18]; 2221 }; 2222 2223 struct mlx5_ifc_dct_events_bits { 2224 u8 reserved_at_0[0xc0]; 2225 2226 u8 reserved_at_c0[0x8]; 2227 u8 dct_number[0x18]; 2228 }; 2229 2230 struct mlx5_ifc_comp_event_bits { 2231 u8 reserved_at_0[0xc0]; 2232 2233 u8 reserved_at_c0[0x8]; 2234 u8 cq_number[0x18]; 2235 }; 2236 2237 enum { 2238 MLX5_QPC_STATE_RST = 0x0, 2239 MLX5_QPC_STATE_INIT = 0x1, 2240 MLX5_QPC_STATE_RTR = 0x2, 2241 MLX5_QPC_STATE_RTS = 0x3, 2242 MLX5_QPC_STATE_SQER = 0x4, 2243 MLX5_QPC_STATE_ERR = 0x6, 2244 MLX5_QPC_STATE_SQD = 0x7, 2245 MLX5_QPC_STATE_SUSPENDED = 0x9, 2246 }; 2247 2248 enum { 2249 MLX5_QPC_ST_RC = 0x0, 2250 MLX5_QPC_ST_UC = 0x1, 2251 MLX5_QPC_ST_UD = 0x2, 2252 MLX5_QPC_ST_XRC = 0x3, 2253 MLX5_QPC_ST_DCI = 0x5, 2254 MLX5_QPC_ST_QP0 = 0x7, 2255 MLX5_QPC_ST_QP1 = 0x8, 2256 MLX5_QPC_ST_RAW_DATAGRAM = 0x9, 2257 MLX5_QPC_ST_REG_UMR = 0xc, 2258 }; 2259 2260 enum { 2261 MLX5_QPC_PM_STATE_ARMED = 0x0, 2262 MLX5_QPC_PM_STATE_REARM = 0x1, 2263 MLX5_QPC_PM_STATE_RESERVED = 0x2, 2264 MLX5_QPC_PM_STATE_MIGRATED = 0x3, 2265 }; 2266 2267 enum { 2268 MLX5_QPC_OFFLOAD_TYPE_RNDV = 0x1, 2269 }; 2270 2271 enum { 2272 MLX5_QPC_END_PADDING_MODE_SCATTER_AS_IS = 0x0, 2273 MLX5_QPC_END_PADDING_MODE_PAD_TO_CACHE_LINE_ALIGNMENT = 0x1, 2274 }; 2275 2276 enum { 2277 MLX5_QPC_MTU_256_BYTES = 0x1, 2278 MLX5_QPC_MTU_512_BYTES = 0x2, 2279 MLX5_QPC_MTU_1K_BYTES = 0x3, 2280 MLX5_QPC_MTU_2K_BYTES = 0x4, 2281 MLX5_QPC_MTU_4K_BYTES = 0x5, 2282 MLX5_QPC_MTU_RAW_ETHERNET_QP = 0x7, 2283 }; 2284 2285 enum { 2286 MLX5_QPC_ATOMIC_MODE_IB_SPEC = 0x1, 2287 MLX5_QPC_ATOMIC_MODE_ONLY_8B = 0x2, 2288 MLX5_QPC_ATOMIC_MODE_UP_TO_8B = 0x3, 2289 MLX5_QPC_ATOMIC_MODE_UP_TO_16B = 0x4, 2290 MLX5_QPC_ATOMIC_MODE_UP_TO_32B = 0x5, 2291 MLX5_QPC_ATOMIC_MODE_UP_TO_64B = 0x6, 2292 MLX5_QPC_ATOMIC_MODE_UP_TO_128B = 0x7, 2293 MLX5_QPC_ATOMIC_MODE_UP_TO_256B = 0x8, 2294 }; 2295 2296 enum { 2297 MLX5_QPC_CS_REQ_DISABLE = 0x0, 2298 MLX5_QPC_CS_REQ_UP_TO_32B = 0x11, 2299 MLX5_QPC_CS_REQ_UP_TO_64B = 0x22, 2300 }; 2301 2302 enum { 2303 MLX5_QPC_CS_RES_DISABLE = 0x0, 2304 MLX5_QPC_CS_RES_UP_TO_32B = 0x1, 2305 MLX5_QPC_CS_RES_UP_TO_64B = 0x2, 2306 }; 2307 2308 struct mlx5_ifc_qpc_bits { 2309 u8 state[0x4]; 2310 u8 lag_tx_port_affinity[0x4]; 2311 u8 st[0x8]; 2312 u8 reserved_at_10[0x3]; 2313 u8 pm_state[0x2]; 2314 u8 reserved_at_15[0x1]; 2315 u8 req_e2e_credit_mode[0x2]; 2316 u8 offload_type[0x4]; 2317 u8 end_padding_mode[0x2]; 2318 u8 reserved_at_1e[0x2]; 2319 2320 u8 wq_signature[0x1]; 2321 u8 block_lb_mc[0x1]; 2322 u8 atomic_like_write_en[0x1]; 2323 u8 latency_sensitive[0x1]; 2324 u8 reserved_at_24[0x1]; 2325 u8 drain_sigerr[0x1]; 2326 u8 reserved_at_26[0x2]; 2327 u8 pd[0x18]; 2328 2329 u8 mtu[0x3]; 2330 u8 log_msg_max[0x5]; 2331 u8 reserved_at_48[0x1]; 2332 u8 log_rq_size[0x4]; 2333 u8 log_rq_stride[0x3]; 2334 u8 no_sq[0x1]; 2335 u8 log_sq_size[0x4]; 2336 u8 reserved_at_55[0x6]; 2337 u8 rlky[0x1]; 2338 u8 ulp_stateless_offload_mode[0x4]; 2339 2340 u8 counter_set_id[0x8]; 2341 u8 uar_page[0x18]; 2342 2343 u8 reserved_at_80[0x8]; 2344 u8 user_index[0x18]; 2345 2346 u8 reserved_at_a0[0x3]; 2347 u8 log_page_size[0x5]; 2348 u8 remote_qpn[0x18]; 2349 2350 struct mlx5_ifc_ads_bits primary_address_path; 2351 2352 struct mlx5_ifc_ads_bits secondary_address_path; 2353 2354 u8 log_ack_req_freq[0x4]; 2355 u8 reserved_at_384[0x4]; 2356 u8 log_sra_max[0x3]; 2357 u8 reserved_at_38b[0x2]; 2358 u8 retry_count[0x3]; 2359 u8 rnr_retry[0x3]; 2360 u8 reserved_at_393[0x1]; 2361 u8 fre[0x1]; 2362 u8 cur_rnr_retry[0x3]; 2363 u8 cur_retry_count[0x3]; 2364 u8 reserved_at_39b[0x5]; 2365 2366 u8 reserved_at_3a0[0x20]; 2367 2368 u8 reserved_at_3c0[0x8]; 2369 u8 next_send_psn[0x18]; 2370 2371 u8 reserved_at_3e0[0x8]; 2372 u8 cqn_snd[0x18]; 2373 2374 u8 reserved_at_400[0x8]; 2375 u8 deth_sqpn[0x18]; 2376 2377 u8 reserved_at_420[0x20]; 2378 2379 u8 reserved_at_440[0x8]; 2380 u8 last_acked_psn[0x18]; 2381 2382 u8 reserved_at_460[0x8]; 2383 u8 ssn[0x18]; 2384 2385 u8 reserved_at_480[0x8]; 2386 u8 log_rra_max[0x3]; 2387 u8 reserved_at_48b[0x1]; 2388 u8 atomic_mode[0x4]; 2389 u8 rre[0x1]; 2390 u8 rwe[0x1]; 2391 u8 rae[0x1]; 2392 u8 reserved_at_493[0x1]; 2393 u8 page_offset[0x6]; 2394 u8 reserved_at_49a[0x3]; 2395 u8 cd_slave_receive[0x1]; 2396 u8 cd_slave_send[0x1]; 2397 u8 cd_master[0x1]; 2398 2399 u8 reserved_at_4a0[0x3]; 2400 u8 min_rnr_nak[0x5]; 2401 u8 next_rcv_psn[0x18]; 2402 2403 u8 reserved_at_4c0[0x8]; 2404 u8 xrcd[0x18]; 2405 2406 u8 reserved_at_4e0[0x8]; 2407 u8 cqn_rcv[0x18]; 2408 2409 u8 dbr_addr[0x40]; 2410 2411 u8 q_key[0x20]; 2412 2413 u8 reserved_at_560[0x5]; 2414 u8 rq_type[0x3]; 2415 u8 srqn_rmpn_xrqn[0x18]; 2416 2417 u8 reserved_at_580[0x8]; 2418 u8 rmsn[0x18]; 2419 2420 u8 hw_sq_wqebb_counter[0x10]; 2421 u8 sw_sq_wqebb_counter[0x10]; 2422 2423 u8 hw_rq_counter[0x20]; 2424 2425 u8 sw_rq_counter[0x20]; 2426 2427 u8 reserved_at_600[0x20]; 2428 2429 u8 reserved_at_620[0xf]; 2430 u8 cgs[0x1]; 2431 u8 cs_req[0x8]; 2432 u8 cs_res[0x8]; 2433 2434 u8 dc_access_key[0x40]; 2435 2436 u8 reserved_at_680[0x3]; 2437 u8 dbr_umem_valid[0x1]; 2438 2439 u8 reserved_at_684[0xbc]; 2440 }; 2441 2442 struct mlx5_ifc_roce_addr_layout_bits { 2443 u8 source_l3_address[16][0x8]; 2444 2445 u8 reserved_at_80[0x3]; 2446 u8 vlan_valid[0x1]; 2447 u8 vlan_id[0xc]; 2448 u8 source_mac_47_32[0x10]; 2449 2450 u8 source_mac_31_0[0x20]; 2451 2452 u8 reserved_at_c0[0x14]; 2453 u8 roce_l3_type[0x4]; 2454 u8 roce_version[0x8]; 2455 2456 u8 reserved_at_e0[0x20]; 2457 }; 2458 2459 union mlx5_ifc_hca_cap_union_bits { 2460 struct mlx5_ifc_cmd_hca_cap_bits cmd_hca_cap; 2461 struct mlx5_ifc_odp_cap_bits odp_cap; 2462 struct mlx5_ifc_atomic_caps_bits atomic_caps; 2463 struct mlx5_ifc_roce_cap_bits roce_cap; 2464 struct mlx5_ifc_per_protocol_networking_offload_caps_bits per_protocol_networking_offload_caps; 2465 struct mlx5_ifc_flow_table_nic_cap_bits flow_table_nic_cap; 2466 struct mlx5_ifc_flow_table_eswitch_cap_bits flow_table_eswitch_cap; 2467 struct mlx5_ifc_e_switch_cap_bits e_switch_cap; 2468 struct mlx5_ifc_vector_calc_cap_bits vector_calc_cap; 2469 struct mlx5_ifc_qos_cap_bits qos_cap; 2470 struct mlx5_ifc_fpga_cap_bits fpga_cap; 2471 u8 reserved_at_0[0x8000]; 2472 }; 2473 2474 enum { 2475 MLX5_FLOW_CONTEXT_ACTION_ALLOW = 0x1, 2476 MLX5_FLOW_CONTEXT_ACTION_DROP = 0x2, 2477 MLX5_FLOW_CONTEXT_ACTION_FWD_DEST = 0x4, 2478 MLX5_FLOW_CONTEXT_ACTION_COUNT = 0x8, 2479 MLX5_FLOW_CONTEXT_ACTION_PACKET_REFORMAT = 0x10, 2480 MLX5_FLOW_CONTEXT_ACTION_DECAP = 0x20, 2481 MLX5_FLOW_CONTEXT_ACTION_MOD_HDR = 0x40, 2482 MLX5_FLOW_CONTEXT_ACTION_VLAN_POP = 0x80, 2483 MLX5_FLOW_CONTEXT_ACTION_VLAN_PUSH = 0x100, 2484 MLX5_FLOW_CONTEXT_ACTION_VLAN_POP_2 = 0x400, 2485 MLX5_FLOW_CONTEXT_ACTION_VLAN_PUSH_2 = 0x800, 2486 }; 2487 2488 struct mlx5_ifc_vlan_bits { 2489 u8 ethtype[0x10]; 2490 u8 prio[0x3]; 2491 u8 cfi[0x1]; 2492 u8 vid[0xc]; 2493 }; 2494 2495 struct mlx5_ifc_flow_context_bits { 2496 struct mlx5_ifc_vlan_bits push_vlan; 2497 2498 u8 group_id[0x20]; 2499 2500 u8 reserved_at_40[0x8]; 2501 u8 flow_tag[0x18]; 2502 2503 u8 reserved_at_60[0x10]; 2504 u8 action[0x10]; 2505 2506 u8 extended_destination[0x1]; 2507 u8 reserved_at_80[0x7]; 2508 u8 destination_list_size[0x18]; 2509 2510 u8 reserved_at_a0[0x8]; 2511 u8 flow_counter_list_size[0x18]; 2512 2513 u8 packet_reformat_id[0x20]; 2514 2515 u8 modify_header_id[0x20]; 2516 2517 struct mlx5_ifc_vlan_bits push_vlan_2; 2518 2519 u8 reserved_at_120[0xe0]; 2520 2521 struct mlx5_ifc_fte_match_param_bits match_value; 2522 2523 u8 reserved_at_1200[0x600]; 2524 2525 union mlx5_ifc_dest_format_struct_flow_counter_list_auto_bits destination[0]; 2526 }; 2527 2528 enum { 2529 MLX5_XRC_SRQC_STATE_GOOD = 0x0, 2530 MLX5_XRC_SRQC_STATE_ERROR = 0x1, 2531 }; 2532 2533 struct mlx5_ifc_xrc_srqc_bits { 2534 u8 state[0x4]; 2535 u8 log_xrc_srq_size[0x4]; 2536 u8 reserved_at_8[0x18]; 2537 2538 u8 wq_signature[0x1]; 2539 u8 cont_srq[0x1]; 2540 u8 reserved_at_22[0x1]; 2541 u8 rlky[0x1]; 2542 u8 basic_cyclic_rcv_wqe[0x1]; 2543 u8 log_rq_stride[0x3]; 2544 u8 xrcd[0x18]; 2545 2546 u8 page_offset[0x6]; 2547 u8 reserved_at_46[0x1]; 2548 u8 dbr_umem_valid[0x1]; 2549 u8 cqn[0x18]; 2550 2551 u8 reserved_at_60[0x20]; 2552 2553 u8 user_index_equal_xrc_srqn[0x1]; 2554 u8 reserved_at_81[0x1]; 2555 u8 log_page_size[0x6]; 2556 u8 user_index[0x18]; 2557 2558 u8 reserved_at_a0[0x20]; 2559 2560 u8 reserved_at_c0[0x8]; 2561 u8 pd[0x18]; 2562 2563 u8 lwm[0x10]; 2564 u8 wqe_cnt[0x10]; 2565 2566 u8 reserved_at_100[0x40]; 2567 2568 u8 db_record_addr_h[0x20]; 2569 2570 u8 db_record_addr_l[0x1e]; 2571 u8 reserved_at_17e[0x2]; 2572 2573 u8 reserved_at_180[0x80]; 2574 }; 2575 2576 struct mlx5_ifc_vnic_diagnostic_statistics_bits { 2577 u8 counter_error_queues[0x20]; 2578 2579 u8 total_error_queues[0x20]; 2580 2581 u8 send_queue_priority_update_flow[0x20]; 2582 2583 u8 reserved_at_60[0x20]; 2584 2585 u8 nic_receive_steering_discard[0x40]; 2586 2587 u8 receive_discard_vport_down[0x40]; 2588 2589 u8 transmit_discard_vport_down[0x40]; 2590 2591 u8 reserved_at_140[0xec0]; 2592 }; 2593 2594 struct mlx5_ifc_traffic_counter_bits { 2595 u8 packets[0x40]; 2596 2597 u8 octets[0x40]; 2598 }; 2599 2600 struct mlx5_ifc_tisc_bits { 2601 u8 strict_lag_tx_port_affinity[0x1]; 2602 u8 reserved_at_1[0x3]; 2603 u8 lag_tx_port_affinity[0x04]; 2604 2605 u8 reserved_at_8[0x4]; 2606 u8 prio[0x4]; 2607 u8 reserved_at_10[0x10]; 2608 2609 u8 reserved_at_20[0x100]; 2610 2611 u8 reserved_at_120[0x8]; 2612 u8 transport_domain[0x18]; 2613 2614 u8 reserved_at_140[0x8]; 2615 u8 underlay_qpn[0x18]; 2616 u8 reserved_at_160[0x3a0]; 2617 }; 2618 2619 enum { 2620 MLX5_TIRC_DISP_TYPE_DIRECT = 0x0, 2621 MLX5_TIRC_DISP_TYPE_INDIRECT = 0x1, 2622 }; 2623 2624 enum { 2625 MLX5_TIRC_LRO_ENABLE_MASK_IPV4_LRO = 0x1, 2626 MLX5_TIRC_LRO_ENABLE_MASK_IPV6_LRO = 0x2, 2627 }; 2628 2629 enum { 2630 MLX5_RX_HASH_FN_NONE = 0x0, 2631 MLX5_RX_HASH_FN_INVERTED_XOR8 = 0x1, 2632 MLX5_RX_HASH_FN_TOEPLITZ = 0x2, 2633 }; 2634 2635 enum { 2636 MLX5_TIRC_SELF_LB_BLOCK_BLOCK_UNICAST = 0x1, 2637 MLX5_TIRC_SELF_LB_BLOCK_BLOCK_MULTICAST = 0x2, 2638 }; 2639 2640 struct mlx5_ifc_tirc_bits { 2641 u8 reserved_at_0[0x20]; 2642 2643 u8 disp_type[0x4]; 2644 u8 reserved_at_24[0x1c]; 2645 2646 u8 reserved_at_40[0x40]; 2647 2648 u8 reserved_at_80[0x4]; 2649 u8 lro_timeout_period_usecs[0x10]; 2650 u8 lro_enable_mask[0x4]; 2651 u8 lro_max_ip_payload_size[0x8]; 2652 2653 u8 reserved_at_a0[0x40]; 2654 2655 u8 reserved_at_e0[0x8]; 2656 u8 inline_rqn[0x18]; 2657 2658 u8 rx_hash_symmetric[0x1]; 2659 u8 reserved_at_101[0x1]; 2660 u8 tunneled_offload_en[0x1]; 2661 u8 reserved_at_103[0x5]; 2662 u8 indirect_table[0x18]; 2663 2664 u8 rx_hash_fn[0x4]; 2665 u8 reserved_at_124[0x2]; 2666 u8 self_lb_block[0x2]; 2667 u8 transport_domain[0x18]; 2668 2669 u8 rx_hash_toeplitz_key[10][0x20]; 2670 2671 struct mlx5_ifc_rx_hash_field_select_bits rx_hash_field_selector_outer; 2672 2673 struct mlx5_ifc_rx_hash_field_select_bits rx_hash_field_selector_inner; 2674 2675 u8 reserved_at_2c0[0x4c0]; 2676 }; 2677 2678 enum { 2679 MLX5_SRQC_STATE_GOOD = 0x0, 2680 MLX5_SRQC_STATE_ERROR = 0x1, 2681 }; 2682 2683 struct mlx5_ifc_srqc_bits { 2684 u8 state[0x4]; 2685 u8 log_srq_size[0x4]; 2686 u8 reserved_at_8[0x18]; 2687 2688 u8 wq_signature[0x1]; 2689 u8 cont_srq[0x1]; 2690 u8 reserved_at_22[0x1]; 2691 u8 rlky[0x1]; 2692 u8 reserved_at_24[0x1]; 2693 u8 log_rq_stride[0x3]; 2694 u8 xrcd[0x18]; 2695 2696 u8 page_offset[0x6]; 2697 u8 reserved_at_46[0x2]; 2698 u8 cqn[0x18]; 2699 2700 u8 reserved_at_60[0x20]; 2701 2702 u8 reserved_at_80[0x2]; 2703 u8 log_page_size[0x6]; 2704 u8 reserved_at_88[0x18]; 2705 2706 u8 reserved_at_a0[0x20]; 2707 2708 u8 reserved_at_c0[0x8]; 2709 u8 pd[0x18]; 2710 2711 u8 lwm[0x10]; 2712 u8 wqe_cnt[0x10]; 2713 2714 u8 reserved_at_100[0x40]; 2715 2716 u8 dbr_addr[0x40]; 2717 2718 u8 reserved_at_180[0x80]; 2719 }; 2720 2721 enum { 2722 MLX5_SQC_STATE_RST = 0x0, 2723 MLX5_SQC_STATE_RDY = 0x1, 2724 MLX5_SQC_STATE_ERR = 0x3, 2725 }; 2726 2727 struct mlx5_ifc_sqc_bits { 2728 u8 rlky[0x1]; 2729 u8 cd_master[0x1]; 2730 u8 fre[0x1]; 2731 u8 flush_in_error_en[0x1]; 2732 u8 allow_multi_pkt_send_wqe[0x1]; 2733 u8 min_wqe_inline_mode[0x3]; 2734 u8 state[0x4]; 2735 u8 reg_umr[0x1]; 2736 u8 allow_swp[0x1]; 2737 u8 hairpin[0x1]; 2738 u8 reserved_at_f[0x11]; 2739 2740 u8 reserved_at_20[0x8]; 2741 u8 user_index[0x18]; 2742 2743 u8 reserved_at_40[0x8]; 2744 u8 cqn[0x18]; 2745 2746 u8 reserved_at_60[0x8]; 2747 u8 hairpin_peer_rq[0x18]; 2748 2749 u8 reserved_at_80[0x10]; 2750 u8 hairpin_peer_vhca[0x10]; 2751 2752 u8 reserved_at_a0[0x50]; 2753 2754 u8 packet_pacing_rate_limit_index[0x10]; 2755 u8 tis_lst_sz[0x10]; 2756 u8 reserved_at_110[0x10]; 2757 2758 u8 reserved_at_120[0x40]; 2759 2760 u8 reserved_at_160[0x8]; 2761 u8 tis_num_0[0x18]; 2762 2763 struct mlx5_ifc_wq_bits wq; 2764 }; 2765 2766 enum { 2767 SCHEDULING_CONTEXT_ELEMENT_TYPE_TSAR = 0x0, 2768 SCHEDULING_CONTEXT_ELEMENT_TYPE_VPORT = 0x1, 2769 SCHEDULING_CONTEXT_ELEMENT_TYPE_VPORT_TC = 0x2, 2770 SCHEDULING_CONTEXT_ELEMENT_TYPE_PARA_VPORT_TC = 0x3, 2771 }; 2772 2773 struct mlx5_ifc_scheduling_context_bits { 2774 u8 element_type[0x8]; 2775 u8 reserved_at_8[0x18]; 2776 2777 u8 element_attributes[0x20]; 2778 2779 u8 parent_element_id[0x20]; 2780 2781 u8 reserved_at_60[0x40]; 2782 2783 u8 bw_share[0x20]; 2784 2785 u8 max_average_bw[0x20]; 2786 2787 u8 reserved_at_e0[0x120]; 2788 }; 2789 2790 struct mlx5_ifc_rqtc_bits { 2791 u8 reserved_at_0[0xa0]; 2792 2793 u8 reserved_at_a0[0x10]; 2794 u8 rqt_max_size[0x10]; 2795 2796 u8 reserved_at_c0[0x10]; 2797 u8 rqt_actual_size[0x10]; 2798 2799 u8 reserved_at_e0[0x6a0]; 2800 2801 struct mlx5_ifc_rq_num_bits rq_num[0]; 2802 }; 2803 2804 enum { 2805 MLX5_RQC_MEM_RQ_TYPE_MEMORY_RQ_INLINE = 0x0, 2806 MLX5_RQC_MEM_RQ_TYPE_MEMORY_RQ_RMP = 0x1, 2807 }; 2808 2809 enum { 2810 MLX5_RQC_STATE_RST = 0x0, 2811 MLX5_RQC_STATE_RDY = 0x1, 2812 MLX5_RQC_STATE_ERR = 0x3, 2813 }; 2814 2815 struct mlx5_ifc_rqc_bits { 2816 u8 rlky[0x1]; 2817 u8 delay_drop_en[0x1]; 2818 u8 scatter_fcs[0x1]; 2819 u8 vsd[0x1]; 2820 u8 mem_rq_type[0x4]; 2821 u8 state[0x4]; 2822 u8 reserved_at_c[0x1]; 2823 u8 flush_in_error_en[0x1]; 2824 u8 hairpin[0x1]; 2825 u8 reserved_at_f[0x11]; 2826 2827 u8 reserved_at_20[0x8]; 2828 u8 user_index[0x18]; 2829 2830 u8 reserved_at_40[0x8]; 2831 u8 cqn[0x18]; 2832 2833 u8 counter_set_id[0x8]; 2834 u8 reserved_at_68[0x18]; 2835 2836 u8 reserved_at_80[0x8]; 2837 u8 rmpn[0x18]; 2838 2839 u8 reserved_at_a0[0x8]; 2840 u8 hairpin_peer_sq[0x18]; 2841 2842 u8 reserved_at_c0[0x10]; 2843 u8 hairpin_peer_vhca[0x10]; 2844 2845 u8 reserved_at_e0[0xa0]; 2846 2847 struct mlx5_ifc_wq_bits wq; 2848 }; 2849 2850 enum { 2851 MLX5_RMPC_STATE_RDY = 0x1, 2852 MLX5_RMPC_STATE_ERR = 0x3, 2853 }; 2854 2855 struct mlx5_ifc_rmpc_bits { 2856 u8 reserved_at_0[0x8]; 2857 u8 state[0x4]; 2858 u8 reserved_at_c[0x14]; 2859 2860 u8 basic_cyclic_rcv_wqe[0x1]; 2861 u8 reserved_at_21[0x1f]; 2862 2863 u8 reserved_at_40[0x140]; 2864 2865 struct mlx5_ifc_wq_bits wq; 2866 }; 2867 2868 struct mlx5_ifc_nic_vport_context_bits { 2869 u8 reserved_at_0[0x5]; 2870 u8 min_wqe_inline_mode[0x3]; 2871 u8 reserved_at_8[0x15]; 2872 u8 disable_mc_local_lb[0x1]; 2873 u8 disable_uc_local_lb[0x1]; 2874 u8 roce_en[0x1]; 2875 2876 u8 arm_change_event[0x1]; 2877 u8 reserved_at_21[0x1a]; 2878 u8 event_on_mtu[0x1]; 2879 u8 event_on_promisc_change[0x1]; 2880 u8 event_on_vlan_change[0x1]; 2881 u8 event_on_mc_address_change[0x1]; 2882 u8 event_on_uc_address_change[0x1]; 2883 2884 u8 reserved_at_40[0xc]; 2885 2886 u8 affiliation_criteria[0x4]; 2887 u8 affiliated_vhca_id[0x10]; 2888 2889 u8 reserved_at_60[0xd0]; 2890 2891 u8 mtu[0x10]; 2892 2893 u8 system_image_guid[0x40]; 2894 u8 port_guid[0x40]; 2895 u8 node_guid[0x40]; 2896 2897 u8 reserved_at_200[0x140]; 2898 u8 qkey_violation_counter[0x10]; 2899 u8 reserved_at_350[0x430]; 2900 2901 u8 promisc_uc[0x1]; 2902 u8 promisc_mc[0x1]; 2903 u8 promisc_all[0x1]; 2904 u8 reserved_at_783[0x2]; 2905 u8 allowed_list_type[0x3]; 2906 u8 reserved_at_788[0xc]; 2907 u8 allowed_list_size[0xc]; 2908 2909 struct mlx5_ifc_mac_address_layout_bits permanent_address; 2910 2911 u8 reserved_at_7e0[0x20]; 2912 2913 u8 current_uc_mac_address[0][0x40]; 2914 }; 2915 2916 enum { 2917 MLX5_MKC_ACCESS_MODE_PA = 0x0, 2918 MLX5_MKC_ACCESS_MODE_MTT = 0x1, 2919 MLX5_MKC_ACCESS_MODE_KLMS = 0x2, 2920 MLX5_MKC_ACCESS_MODE_KSM = 0x3, 2921 MLX5_MKC_ACCESS_MODE_MEMIC = 0x5, 2922 }; 2923 2924 struct mlx5_ifc_mkc_bits { 2925 u8 reserved_at_0[0x1]; 2926 u8 free[0x1]; 2927 u8 reserved_at_2[0x1]; 2928 u8 access_mode_4_2[0x3]; 2929 u8 reserved_at_6[0x7]; 2930 u8 relaxed_ordering_write[0x1]; 2931 u8 reserved_at_e[0x1]; 2932 u8 small_fence_on_rdma_read_response[0x1]; 2933 u8 umr_en[0x1]; 2934 u8 a[0x1]; 2935 u8 rw[0x1]; 2936 u8 rr[0x1]; 2937 u8 lw[0x1]; 2938 u8 lr[0x1]; 2939 u8 access_mode_1_0[0x2]; 2940 u8 reserved_at_18[0x8]; 2941 2942 u8 qpn[0x18]; 2943 u8 mkey_7_0[0x8]; 2944 2945 u8 reserved_at_40[0x20]; 2946 2947 u8 length64[0x1]; 2948 u8 bsf_en[0x1]; 2949 u8 sync_umr[0x1]; 2950 u8 reserved_at_63[0x2]; 2951 u8 expected_sigerr_count[0x1]; 2952 u8 reserved_at_66[0x1]; 2953 u8 en_rinval[0x1]; 2954 u8 pd[0x18]; 2955 2956 u8 start_addr[0x40]; 2957 2958 u8 len[0x40]; 2959 2960 u8 bsf_octword_size[0x20]; 2961 2962 u8 reserved_at_120[0x80]; 2963 2964 u8 translations_octword_size[0x20]; 2965 2966 u8 reserved_at_1c0[0x1b]; 2967 u8 log_page_size[0x5]; 2968 2969 u8 reserved_at_1e0[0x20]; 2970 }; 2971 2972 struct mlx5_ifc_pkey_bits { 2973 u8 reserved_at_0[0x10]; 2974 u8 pkey[0x10]; 2975 }; 2976 2977 struct mlx5_ifc_array128_auto_bits { 2978 u8 array128_auto[16][0x8]; 2979 }; 2980 2981 struct mlx5_ifc_hca_vport_context_bits { 2982 u8 field_select[0x20]; 2983 2984 u8 reserved_at_20[0xe0]; 2985 2986 u8 sm_virt_aware[0x1]; 2987 u8 has_smi[0x1]; 2988 u8 has_raw[0x1]; 2989 u8 grh_required[0x1]; 2990 u8 reserved_at_104[0xc]; 2991 u8 port_physical_state[0x4]; 2992 u8 vport_state_policy[0x4]; 2993 u8 port_state[0x4]; 2994 u8 vport_state[0x4]; 2995 2996 u8 reserved_at_120[0x20]; 2997 2998 u8 system_image_guid[0x40]; 2999 3000 u8 port_guid[0x40]; 3001 3002 u8 node_guid[0x40]; 3003 3004 u8 cap_mask1[0x20]; 3005 3006 u8 cap_mask1_field_select[0x20]; 3007 3008 u8 cap_mask2[0x20]; 3009 3010 u8 cap_mask2_field_select[0x20]; 3011 3012 u8 reserved_at_280[0x80]; 3013 3014 u8 lid[0x10]; 3015 u8 reserved_at_310[0x4]; 3016 u8 init_type_reply[0x4]; 3017 u8 lmc[0x3]; 3018 u8 subnet_timeout[0x5]; 3019 3020 u8 sm_lid[0x10]; 3021 u8 sm_sl[0x4]; 3022 u8 reserved_at_334[0xc]; 3023 3024 u8 qkey_violation_counter[0x10]; 3025 u8 pkey_violation_counter[0x10]; 3026 3027 u8 reserved_at_360[0xca0]; 3028 }; 3029 3030 struct mlx5_ifc_esw_vport_context_bits { 3031 u8 reserved_at_0[0x3]; 3032 u8 vport_svlan_strip[0x1]; 3033 u8 vport_cvlan_strip[0x1]; 3034 u8 vport_svlan_insert[0x1]; 3035 u8 vport_cvlan_insert[0x2]; 3036 u8 reserved_at_8[0x18]; 3037 3038 u8 reserved_at_20[0x20]; 3039 3040 u8 svlan_cfi[0x1]; 3041 u8 svlan_pcp[0x3]; 3042 u8 svlan_id[0xc]; 3043 u8 cvlan_cfi[0x1]; 3044 u8 cvlan_pcp[0x3]; 3045 u8 cvlan_id[0xc]; 3046 3047 u8 reserved_at_60[0x7a0]; 3048 }; 3049 3050 enum { 3051 MLX5_EQC_STATUS_OK = 0x0, 3052 MLX5_EQC_STATUS_EQ_WRITE_FAILURE = 0xa, 3053 }; 3054 3055 enum { 3056 MLX5_EQC_ST_ARMED = 0x9, 3057 MLX5_EQC_ST_FIRED = 0xa, 3058 }; 3059 3060 struct mlx5_ifc_eqc_bits { 3061 u8 status[0x4]; 3062 u8 reserved_at_4[0x9]; 3063 u8 ec[0x1]; 3064 u8 oi[0x1]; 3065 u8 reserved_at_f[0x5]; 3066 u8 st[0x4]; 3067 u8 reserved_at_18[0x8]; 3068 3069 u8 reserved_at_20[0x20]; 3070 3071 u8 reserved_at_40[0x14]; 3072 u8 page_offset[0x6]; 3073 u8 reserved_at_5a[0x6]; 3074 3075 u8 reserved_at_60[0x3]; 3076 u8 log_eq_size[0x5]; 3077 u8 uar_page[0x18]; 3078 3079 u8 reserved_at_80[0x20]; 3080 3081 u8 reserved_at_a0[0x18]; 3082 u8 intr[0x8]; 3083 3084 u8 reserved_at_c0[0x3]; 3085 u8 log_page_size[0x5]; 3086 u8 reserved_at_c8[0x18]; 3087 3088 u8 reserved_at_e0[0x60]; 3089 3090 u8 reserved_at_140[0x8]; 3091 u8 consumer_counter[0x18]; 3092 3093 u8 reserved_at_160[0x8]; 3094 u8 producer_counter[0x18]; 3095 3096 u8 reserved_at_180[0x80]; 3097 }; 3098 3099 enum { 3100 MLX5_DCTC_STATE_ACTIVE = 0x0, 3101 MLX5_DCTC_STATE_DRAINING = 0x1, 3102 MLX5_DCTC_STATE_DRAINED = 0x2, 3103 }; 3104 3105 enum { 3106 MLX5_DCTC_CS_RES_DISABLE = 0x0, 3107 MLX5_DCTC_CS_RES_NA = 0x1, 3108 MLX5_DCTC_CS_RES_UP_TO_64B = 0x2, 3109 }; 3110 3111 enum { 3112 MLX5_DCTC_MTU_256_BYTES = 0x1, 3113 MLX5_DCTC_MTU_512_BYTES = 0x2, 3114 MLX5_DCTC_MTU_1K_BYTES = 0x3, 3115 MLX5_DCTC_MTU_2K_BYTES = 0x4, 3116 MLX5_DCTC_MTU_4K_BYTES = 0x5, 3117 }; 3118 3119 struct mlx5_ifc_dctc_bits { 3120 u8 reserved_at_0[0x4]; 3121 u8 state[0x4]; 3122 u8 reserved_at_8[0x18]; 3123 3124 u8 reserved_at_20[0x8]; 3125 u8 user_index[0x18]; 3126 3127 u8 reserved_at_40[0x8]; 3128 u8 cqn[0x18]; 3129 3130 u8 counter_set_id[0x8]; 3131 u8 atomic_mode[0x4]; 3132 u8 rre[0x1]; 3133 u8 rwe[0x1]; 3134 u8 rae[0x1]; 3135 u8 atomic_like_write_en[0x1]; 3136 u8 latency_sensitive[0x1]; 3137 u8 rlky[0x1]; 3138 u8 free_ar[0x1]; 3139 u8 reserved_at_73[0xd]; 3140 3141 u8 reserved_at_80[0x8]; 3142 u8 cs_res[0x8]; 3143 u8 reserved_at_90[0x3]; 3144 u8 min_rnr_nak[0x5]; 3145 u8 reserved_at_98[0x8]; 3146 3147 u8 reserved_at_a0[0x8]; 3148 u8 srqn_xrqn[0x18]; 3149 3150 u8 reserved_at_c0[0x8]; 3151 u8 pd[0x18]; 3152 3153 u8 tclass[0x8]; 3154 u8 reserved_at_e8[0x4]; 3155 u8 flow_label[0x14]; 3156 3157 u8 dc_access_key[0x40]; 3158 3159 u8 reserved_at_140[0x5]; 3160 u8 mtu[0x3]; 3161 u8 port[0x8]; 3162 u8 pkey_index[0x10]; 3163 3164 u8 reserved_at_160[0x8]; 3165 u8 my_addr_index[0x8]; 3166 u8 reserved_at_170[0x8]; 3167 u8 hop_limit[0x8]; 3168 3169 u8 dc_access_key_violation_count[0x20]; 3170 3171 u8 reserved_at_1a0[0x14]; 3172 u8 dei_cfi[0x1]; 3173 u8 eth_prio[0x3]; 3174 u8 ecn[0x2]; 3175 u8 dscp[0x6]; 3176 3177 u8 reserved_at_1c0[0x40]; 3178 }; 3179 3180 enum { 3181 MLX5_CQC_STATUS_OK = 0x0, 3182 MLX5_CQC_STATUS_CQ_OVERFLOW = 0x9, 3183 MLX5_CQC_STATUS_CQ_WRITE_FAIL = 0xa, 3184 }; 3185 3186 enum { 3187 MLX5_CQC_CQE_SZ_64_BYTES = 0x0, 3188 MLX5_CQC_CQE_SZ_128_BYTES = 0x1, 3189 }; 3190 3191 enum { 3192 MLX5_CQC_ST_SOLICITED_NOTIFICATION_REQUEST_ARMED = 0x6, 3193 MLX5_CQC_ST_NOTIFICATION_REQUEST_ARMED = 0x9, 3194 MLX5_CQC_ST_FIRED = 0xa, 3195 }; 3196 3197 enum { 3198 MLX5_CQ_PERIOD_MODE_START_FROM_EQE = 0x0, 3199 MLX5_CQ_PERIOD_MODE_START_FROM_CQE = 0x1, 3200 MLX5_CQ_PERIOD_NUM_MODES 3201 }; 3202 3203 struct mlx5_ifc_cqc_bits { 3204 u8 status[0x4]; 3205 u8 reserved_at_4[0x2]; 3206 u8 dbr_umem_valid[0x1]; 3207 u8 reserved_at_7[0x1]; 3208 u8 cqe_sz[0x3]; 3209 u8 cc[0x1]; 3210 u8 reserved_at_c[0x1]; 3211 u8 scqe_break_moderation_en[0x1]; 3212 u8 oi[0x1]; 3213 u8 cq_period_mode[0x2]; 3214 u8 cqe_comp_en[0x1]; 3215 u8 mini_cqe_res_format[0x2]; 3216 u8 st[0x4]; 3217 u8 reserved_at_18[0x8]; 3218 3219 u8 reserved_at_20[0x20]; 3220 3221 u8 reserved_at_40[0x14]; 3222 u8 page_offset[0x6]; 3223 u8 reserved_at_5a[0x6]; 3224 3225 u8 reserved_at_60[0x3]; 3226 u8 log_cq_size[0x5]; 3227 u8 uar_page[0x18]; 3228 3229 u8 reserved_at_80[0x4]; 3230 u8 cq_period[0xc]; 3231 u8 cq_max_count[0x10]; 3232 3233 u8 reserved_at_a0[0x18]; 3234 u8 c_eqn[0x8]; 3235 3236 u8 reserved_at_c0[0x3]; 3237 u8 log_page_size[0x5]; 3238 u8 reserved_at_c8[0x18]; 3239 3240 u8 reserved_at_e0[0x20]; 3241 3242 u8 reserved_at_100[0x8]; 3243 u8 last_notified_index[0x18]; 3244 3245 u8 reserved_at_120[0x8]; 3246 u8 last_solicit_index[0x18]; 3247 3248 u8 reserved_at_140[0x8]; 3249 u8 consumer_counter[0x18]; 3250 3251 u8 reserved_at_160[0x8]; 3252 u8 producer_counter[0x18]; 3253 3254 u8 reserved_at_180[0x40]; 3255 3256 u8 dbr_addr[0x40]; 3257 }; 3258 3259 union mlx5_ifc_cong_control_roce_ecn_auto_bits { 3260 struct mlx5_ifc_cong_control_802_1qau_rp_bits cong_control_802_1qau_rp; 3261 struct mlx5_ifc_cong_control_r_roce_ecn_rp_bits cong_control_r_roce_ecn_rp; 3262 struct mlx5_ifc_cong_control_r_roce_ecn_np_bits cong_control_r_roce_ecn_np; 3263 u8 reserved_at_0[0x800]; 3264 }; 3265 3266 struct mlx5_ifc_query_adapter_param_block_bits { 3267 u8 reserved_at_0[0xc0]; 3268 3269 u8 reserved_at_c0[0x8]; 3270 u8 ieee_vendor_id[0x18]; 3271 3272 u8 reserved_at_e0[0x10]; 3273 u8 vsd_vendor_id[0x10]; 3274 3275 u8 vsd[208][0x8]; 3276 3277 u8 vsd_contd_psid[16][0x8]; 3278 }; 3279 3280 enum { 3281 MLX5_XRQC_STATE_GOOD = 0x0, 3282 MLX5_XRQC_STATE_ERROR = 0x1, 3283 }; 3284 3285 enum { 3286 MLX5_XRQC_TOPOLOGY_NO_SPECIAL_TOPOLOGY = 0x0, 3287 MLX5_XRQC_TOPOLOGY_TAG_MATCHING = 0x1, 3288 }; 3289 3290 enum { 3291 MLX5_XRQC_OFFLOAD_RNDV = 0x1, 3292 }; 3293 3294 struct mlx5_ifc_tag_matching_topology_context_bits { 3295 u8 log_matching_list_sz[0x4]; 3296 u8 reserved_at_4[0xc]; 3297 u8 append_next_index[0x10]; 3298 3299 u8 sw_phase_cnt[0x10]; 3300 u8 hw_phase_cnt[0x10]; 3301 3302 u8 reserved_at_40[0x40]; 3303 }; 3304 3305 struct mlx5_ifc_xrqc_bits { 3306 u8 state[0x4]; 3307 u8 rlkey[0x1]; 3308 u8 reserved_at_5[0xf]; 3309 u8 topology[0x4]; 3310 u8 reserved_at_18[0x4]; 3311 u8 offload[0x4]; 3312 3313 u8 reserved_at_20[0x8]; 3314 u8 user_index[0x18]; 3315 3316 u8 reserved_at_40[0x8]; 3317 u8 cqn[0x18]; 3318 3319 u8 reserved_at_60[0xa0]; 3320 3321 struct mlx5_ifc_tag_matching_topology_context_bits tag_matching_topology_context; 3322 3323 u8 reserved_at_180[0x280]; 3324 3325 struct mlx5_ifc_wq_bits wq; 3326 }; 3327 3328 union mlx5_ifc_modify_field_select_resize_field_select_auto_bits { 3329 struct mlx5_ifc_modify_field_select_bits modify_field_select; 3330 struct mlx5_ifc_resize_field_select_bits resize_field_select; 3331 u8 reserved_at_0[0x20]; 3332 }; 3333 3334 union mlx5_ifc_field_select_802_1_r_roce_auto_bits { 3335 struct mlx5_ifc_field_select_802_1qau_rp_bits field_select_802_1qau_rp; 3336 struct mlx5_ifc_field_select_r_roce_rp_bits field_select_r_roce_rp; 3337 struct mlx5_ifc_field_select_r_roce_np_bits field_select_r_roce_np; 3338 u8 reserved_at_0[0x20]; 3339 }; 3340 3341 union mlx5_ifc_eth_cntrs_grp_data_layout_auto_bits { 3342 struct mlx5_ifc_eth_802_3_cntrs_grp_data_layout_bits eth_802_3_cntrs_grp_data_layout; 3343 struct mlx5_ifc_eth_2863_cntrs_grp_data_layout_bits eth_2863_cntrs_grp_data_layout; 3344 struct mlx5_ifc_eth_2819_cntrs_grp_data_layout_bits eth_2819_cntrs_grp_data_layout; 3345 struct mlx5_ifc_eth_3635_cntrs_grp_data_layout_bits eth_3635_cntrs_grp_data_layout; 3346 struct mlx5_ifc_eth_extended_cntrs_grp_data_layout_bits eth_extended_cntrs_grp_data_layout; 3347 struct mlx5_ifc_eth_per_prio_grp_data_layout_bits eth_per_prio_grp_data_layout; 3348 struct mlx5_ifc_eth_per_traffic_grp_data_layout_bits eth_per_traffic_grp_data_layout; 3349 struct mlx5_ifc_ib_port_cntrs_grp_data_layout_bits ib_port_cntrs_grp_data_layout; 3350 struct mlx5_ifc_phys_layer_cntrs_bits phys_layer_cntrs; 3351 struct mlx5_ifc_phys_layer_statistical_cntrs_bits phys_layer_statistical_cntrs; 3352 u8 reserved_at_0[0x7c0]; 3353 }; 3354 3355 union mlx5_ifc_pcie_cntrs_grp_data_layout_auto_bits { 3356 struct mlx5_ifc_pcie_perf_cntrs_grp_data_layout_bits pcie_perf_cntrs_grp_data_layout; 3357 u8 reserved_at_0[0x7c0]; 3358 }; 3359 3360 union mlx5_ifc_event_auto_bits { 3361 struct mlx5_ifc_comp_event_bits comp_event; 3362 struct mlx5_ifc_dct_events_bits dct_events; 3363 struct mlx5_ifc_qp_events_bits qp_events; 3364 struct mlx5_ifc_wqe_associated_page_fault_event_bits wqe_associated_page_fault_event; 3365 struct mlx5_ifc_rdma_page_fault_event_bits rdma_page_fault_event; 3366 struct mlx5_ifc_cq_error_bits cq_error; 3367 struct mlx5_ifc_dropped_packet_logged_bits dropped_packet_logged; 3368 struct mlx5_ifc_port_state_change_event_bits port_state_change_event; 3369 struct mlx5_ifc_gpio_event_bits gpio_event; 3370 struct mlx5_ifc_db_bf_congestion_event_bits db_bf_congestion_event; 3371 struct mlx5_ifc_stall_vl_event_bits stall_vl_event; 3372 struct mlx5_ifc_cmd_inter_comp_event_bits cmd_inter_comp_event; 3373 u8 reserved_at_0[0xe0]; 3374 }; 3375 3376 struct mlx5_ifc_health_buffer_bits { 3377 u8 reserved_at_0[0x100]; 3378 3379 u8 assert_existptr[0x20]; 3380 3381 u8 assert_callra[0x20]; 3382 3383 u8 reserved_at_140[0x40]; 3384 3385 u8 fw_version[0x20]; 3386 3387 u8 hw_id[0x20]; 3388 3389 u8 reserved_at_1c0[0x20]; 3390 3391 u8 irisc_index[0x8]; 3392 u8 synd[0x8]; 3393 u8 ext_synd[0x10]; 3394 }; 3395 3396 struct mlx5_ifc_register_loopback_control_bits { 3397 u8 no_lb[0x1]; 3398 u8 reserved_at_1[0x7]; 3399 u8 port[0x8]; 3400 u8 reserved_at_10[0x10]; 3401 3402 u8 reserved_at_20[0x60]; 3403 }; 3404 3405 struct mlx5_ifc_vport_tc_element_bits { 3406 u8 traffic_class[0x4]; 3407 u8 reserved_at_4[0xc]; 3408 u8 vport_number[0x10]; 3409 }; 3410 3411 struct mlx5_ifc_vport_element_bits { 3412 u8 reserved_at_0[0x10]; 3413 u8 vport_number[0x10]; 3414 }; 3415 3416 enum { 3417 TSAR_ELEMENT_TSAR_TYPE_DWRR = 0x0, 3418 TSAR_ELEMENT_TSAR_TYPE_ROUND_ROBIN = 0x1, 3419 TSAR_ELEMENT_TSAR_TYPE_ETS = 0x2, 3420 }; 3421 3422 struct mlx5_ifc_tsar_element_bits { 3423 u8 reserved_at_0[0x8]; 3424 u8 tsar_type[0x8]; 3425 u8 reserved_at_10[0x10]; 3426 }; 3427 3428 enum { 3429 MLX5_TEARDOWN_HCA_OUT_FORCE_STATE_SUCCESS = 0x0, 3430 MLX5_TEARDOWN_HCA_OUT_FORCE_STATE_FAIL = 0x1, 3431 }; 3432 3433 struct mlx5_ifc_teardown_hca_out_bits { 3434 u8 status[0x8]; 3435 u8 reserved_at_8[0x18]; 3436 3437 u8 syndrome[0x20]; 3438 3439 u8 reserved_at_40[0x3f]; 3440 3441 u8 state[0x1]; 3442 }; 3443 3444 enum { 3445 MLX5_TEARDOWN_HCA_IN_PROFILE_GRACEFUL_CLOSE = 0x0, 3446 MLX5_TEARDOWN_HCA_IN_PROFILE_FORCE_CLOSE = 0x1, 3447 MLX5_TEARDOWN_HCA_IN_PROFILE_PREPARE_FAST_TEARDOWN = 0x2, 3448 }; 3449 3450 struct mlx5_ifc_teardown_hca_in_bits { 3451 u8 opcode[0x10]; 3452 u8 reserved_at_10[0x10]; 3453 3454 u8 reserved_at_20[0x10]; 3455 u8 op_mod[0x10]; 3456 3457 u8 reserved_at_40[0x10]; 3458 u8 profile[0x10]; 3459 3460 u8 reserved_at_60[0x20]; 3461 }; 3462 3463 struct mlx5_ifc_sqerr2rts_qp_out_bits { 3464 u8 status[0x8]; 3465 u8 reserved_at_8[0x18]; 3466 3467 u8 syndrome[0x20]; 3468 3469 u8 reserved_at_40[0x40]; 3470 }; 3471 3472 struct mlx5_ifc_sqerr2rts_qp_in_bits { 3473 u8 opcode[0x10]; 3474 u8 uid[0x10]; 3475 3476 u8 reserved_at_20[0x10]; 3477 u8 op_mod[0x10]; 3478 3479 u8 reserved_at_40[0x8]; 3480 u8 qpn[0x18]; 3481 3482 u8 reserved_at_60[0x20]; 3483 3484 u8 opt_param_mask[0x20]; 3485 3486 u8 reserved_at_a0[0x20]; 3487 3488 struct mlx5_ifc_qpc_bits qpc; 3489 3490 u8 reserved_at_800[0x80]; 3491 }; 3492 3493 struct mlx5_ifc_sqd2rts_qp_out_bits { 3494 u8 status[0x8]; 3495 u8 reserved_at_8[0x18]; 3496 3497 u8 syndrome[0x20]; 3498 3499 u8 reserved_at_40[0x40]; 3500 }; 3501 3502 struct mlx5_ifc_sqd2rts_qp_in_bits { 3503 u8 opcode[0x10]; 3504 u8 uid[0x10]; 3505 3506 u8 reserved_at_20[0x10]; 3507 u8 op_mod[0x10]; 3508 3509 u8 reserved_at_40[0x8]; 3510 u8 qpn[0x18]; 3511 3512 u8 reserved_at_60[0x20]; 3513 3514 u8 opt_param_mask[0x20]; 3515 3516 u8 reserved_at_a0[0x20]; 3517 3518 struct mlx5_ifc_qpc_bits qpc; 3519 3520 u8 reserved_at_800[0x80]; 3521 }; 3522 3523 struct mlx5_ifc_set_roce_address_out_bits { 3524 u8 status[0x8]; 3525 u8 reserved_at_8[0x18]; 3526 3527 u8 syndrome[0x20]; 3528 3529 u8 reserved_at_40[0x40]; 3530 }; 3531 3532 struct mlx5_ifc_set_roce_address_in_bits { 3533 u8 opcode[0x10]; 3534 u8 reserved_at_10[0x10]; 3535 3536 u8 reserved_at_20[0x10]; 3537 u8 op_mod[0x10]; 3538 3539 u8 roce_address_index[0x10]; 3540 u8 reserved_at_50[0xc]; 3541 u8 vhca_port_num[0x4]; 3542 3543 u8 reserved_at_60[0x20]; 3544 3545 struct mlx5_ifc_roce_addr_layout_bits roce_address; 3546 }; 3547 3548 struct mlx5_ifc_set_mad_demux_out_bits { 3549 u8 status[0x8]; 3550 u8 reserved_at_8[0x18]; 3551 3552 u8 syndrome[0x20]; 3553 3554 u8 reserved_at_40[0x40]; 3555 }; 3556 3557 enum { 3558 MLX5_SET_MAD_DEMUX_IN_DEMUX_MODE_PASS_ALL = 0x0, 3559 MLX5_SET_MAD_DEMUX_IN_DEMUX_MODE_SELECTIVE = 0x2, 3560 }; 3561 3562 struct mlx5_ifc_set_mad_demux_in_bits { 3563 u8 opcode[0x10]; 3564 u8 reserved_at_10[0x10]; 3565 3566 u8 reserved_at_20[0x10]; 3567 u8 op_mod[0x10]; 3568 3569 u8 reserved_at_40[0x20]; 3570 3571 u8 reserved_at_60[0x6]; 3572 u8 demux_mode[0x2]; 3573 u8 reserved_at_68[0x18]; 3574 }; 3575 3576 struct mlx5_ifc_set_l2_table_entry_out_bits { 3577 u8 status[0x8]; 3578 u8 reserved_at_8[0x18]; 3579 3580 u8 syndrome[0x20]; 3581 3582 u8 reserved_at_40[0x40]; 3583 }; 3584 3585 struct mlx5_ifc_set_l2_table_entry_in_bits { 3586 u8 opcode[0x10]; 3587 u8 reserved_at_10[0x10]; 3588 3589 u8 reserved_at_20[0x10]; 3590 u8 op_mod[0x10]; 3591 3592 u8 reserved_at_40[0x60]; 3593 3594 u8 reserved_at_a0[0x8]; 3595 u8 table_index[0x18]; 3596 3597 u8 reserved_at_c0[0x20]; 3598 3599 u8 reserved_at_e0[0x13]; 3600 u8 vlan_valid[0x1]; 3601 u8 vlan[0xc]; 3602 3603 struct mlx5_ifc_mac_address_layout_bits mac_address; 3604 3605 u8 reserved_at_140[0xc0]; 3606 }; 3607 3608 struct mlx5_ifc_set_issi_out_bits { 3609 u8 status[0x8]; 3610 u8 reserved_at_8[0x18]; 3611 3612 u8 syndrome[0x20]; 3613 3614 u8 reserved_at_40[0x40]; 3615 }; 3616 3617 struct mlx5_ifc_set_issi_in_bits { 3618 u8 opcode[0x10]; 3619 u8 reserved_at_10[0x10]; 3620 3621 u8 reserved_at_20[0x10]; 3622 u8 op_mod[0x10]; 3623 3624 u8 reserved_at_40[0x10]; 3625 u8 current_issi[0x10]; 3626 3627 u8 reserved_at_60[0x20]; 3628 }; 3629 3630 struct mlx5_ifc_set_hca_cap_out_bits { 3631 u8 status[0x8]; 3632 u8 reserved_at_8[0x18]; 3633 3634 u8 syndrome[0x20]; 3635 3636 u8 reserved_at_40[0x40]; 3637 }; 3638 3639 struct mlx5_ifc_set_hca_cap_in_bits { 3640 u8 opcode[0x10]; 3641 u8 reserved_at_10[0x10]; 3642 3643 u8 reserved_at_20[0x10]; 3644 u8 op_mod[0x10]; 3645 3646 u8 reserved_at_40[0x40]; 3647 3648 union mlx5_ifc_hca_cap_union_bits capability; 3649 }; 3650 3651 enum { 3652 MLX5_SET_FTE_MODIFY_ENABLE_MASK_ACTION = 0x0, 3653 MLX5_SET_FTE_MODIFY_ENABLE_MASK_FLOW_TAG = 0x1, 3654 MLX5_SET_FTE_MODIFY_ENABLE_MASK_DESTINATION_LIST = 0x2, 3655 MLX5_SET_FTE_MODIFY_ENABLE_MASK_FLOW_COUNTERS = 0x3 3656 }; 3657 3658 struct mlx5_ifc_set_fte_out_bits { 3659 u8 status[0x8]; 3660 u8 reserved_at_8[0x18]; 3661 3662 u8 syndrome[0x20]; 3663 3664 u8 reserved_at_40[0x40]; 3665 }; 3666 3667 struct mlx5_ifc_set_fte_in_bits { 3668 u8 opcode[0x10]; 3669 u8 reserved_at_10[0x10]; 3670 3671 u8 reserved_at_20[0x10]; 3672 u8 op_mod[0x10]; 3673 3674 u8 other_vport[0x1]; 3675 u8 reserved_at_41[0xf]; 3676 u8 vport_number[0x10]; 3677 3678 u8 reserved_at_60[0x20]; 3679 3680 u8 table_type[0x8]; 3681 u8 reserved_at_88[0x18]; 3682 3683 u8 reserved_at_a0[0x8]; 3684 u8 table_id[0x18]; 3685 3686 u8 reserved_at_c0[0x18]; 3687 u8 modify_enable_mask[0x8]; 3688 3689 u8 reserved_at_e0[0x20]; 3690 3691 u8 flow_index[0x20]; 3692 3693 u8 reserved_at_120[0xe0]; 3694 3695 struct mlx5_ifc_flow_context_bits flow_context; 3696 }; 3697 3698 struct mlx5_ifc_rts2rts_qp_out_bits { 3699 u8 status[0x8]; 3700 u8 reserved_at_8[0x18]; 3701 3702 u8 syndrome[0x20]; 3703 3704 u8 reserved_at_40[0x40]; 3705 }; 3706 3707 struct mlx5_ifc_rts2rts_qp_in_bits { 3708 u8 opcode[0x10]; 3709 u8 uid[0x10]; 3710 3711 u8 reserved_at_20[0x10]; 3712 u8 op_mod[0x10]; 3713 3714 u8 reserved_at_40[0x8]; 3715 u8 qpn[0x18]; 3716 3717 u8 reserved_at_60[0x20]; 3718 3719 u8 opt_param_mask[0x20]; 3720 3721 u8 reserved_at_a0[0x20]; 3722 3723 struct mlx5_ifc_qpc_bits qpc; 3724 3725 u8 reserved_at_800[0x80]; 3726 }; 3727 3728 struct mlx5_ifc_rtr2rts_qp_out_bits { 3729 u8 status[0x8]; 3730 u8 reserved_at_8[0x18]; 3731 3732 u8 syndrome[0x20]; 3733 3734 u8 reserved_at_40[0x40]; 3735 }; 3736 3737 struct mlx5_ifc_rtr2rts_qp_in_bits { 3738 u8 opcode[0x10]; 3739 u8 uid[0x10]; 3740 3741 u8 reserved_at_20[0x10]; 3742 u8 op_mod[0x10]; 3743 3744 u8 reserved_at_40[0x8]; 3745 u8 qpn[0x18]; 3746 3747 u8 reserved_at_60[0x20]; 3748 3749 u8 opt_param_mask[0x20]; 3750 3751 u8 reserved_at_a0[0x20]; 3752 3753 struct mlx5_ifc_qpc_bits qpc; 3754 3755 u8 reserved_at_800[0x80]; 3756 }; 3757 3758 struct mlx5_ifc_rst2init_qp_out_bits { 3759 u8 status[0x8]; 3760 u8 reserved_at_8[0x18]; 3761 3762 u8 syndrome[0x20]; 3763 3764 u8 reserved_at_40[0x40]; 3765 }; 3766 3767 struct mlx5_ifc_rst2init_qp_in_bits { 3768 u8 opcode[0x10]; 3769 u8 uid[0x10]; 3770 3771 u8 reserved_at_20[0x10]; 3772 u8 op_mod[0x10]; 3773 3774 u8 reserved_at_40[0x8]; 3775 u8 qpn[0x18]; 3776 3777 u8 reserved_at_60[0x20]; 3778 3779 u8 opt_param_mask[0x20]; 3780 3781 u8 reserved_at_a0[0x20]; 3782 3783 struct mlx5_ifc_qpc_bits qpc; 3784 3785 u8 reserved_at_800[0x80]; 3786 }; 3787 3788 struct mlx5_ifc_query_xrq_out_bits { 3789 u8 status[0x8]; 3790 u8 reserved_at_8[0x18]; 3791 3792 u8 syndrome[0x20]; 3793 3794 u8 reserved_at_40[0x40]; 3795 3796 struct mlx5_ifc_xrqc_bits xrq_context; 3797 }; 3798 3799 struct mlx5_ifc_query_xrq_in_bits { 3800 u8 opcode[0x10]; 3801 u8 reserved_at_10[0x10]; 3802 3803 u8 reserved_at_20[0x10]; 3804 u8 op_mod[0x10]; 3805 3806 u8 reserved_at_40[0x8]; 3807 u8 xrqn[0x18]; 3808 3809 u8 reserved_at_60[0x20]; 3810 }; 3811 3812 struct mlx5_ifc_query_xrc_srq_out_bits { 3813 u8 status[0x8]; 3814 u8 reserved_at_8[0x18]; 3815 3816 u8 syndrome[0x20]; 3817 3818 u8 reserved_at_40[0x40]; 3819 3820 struct mlx5_ifc_xrc_srqc_bits xrc_srq_context_entry; 3821 3822 u8 reserved_at_280[0x600]; 3823 3824 u8 pas[0][0x40]; 3825 }; 3826 3827 struct mlx5_ifc_query_xrc_srq_in_bits { 3828 u8 opcode[0x10]; 3829 u8 reserved_at_10[0x10]; 3830 3831 u8 reserved_at_20[0x10]; 3832 u8 op_mod[0x10]; 3833 3834 u8 reserved_at_40[0x8]; 3835 u8 xrc_srqn[0x18]; 3836 3837 u8 reserved_at_60[0x20]; 3838 }; 3839 3840 enum { 3841 MLX5_QUERY_VPORT_STATE_OUT_STATE_DOWN = 0x0, 3842 MLX5_QUERY_VPORT_STATE_OUT_STATE_UP = 0x1, 3843 }; 3844 3845 struct mlx5_ifc_query_vport_state_out_bits { 3846 u8 status[0x8]; 3847 u8 reserved_at_8[0x18]; 3848 3849 u8 syndrome[0x20]; 3850 3851 u8 reserved_at_40[0x20]; 3852 3853 u8 reserved_at_60[0x18]; 3854 u8 admin_state[0x4]; 3855 u8 state[0x4]; 3856 }; 3857 3858 enum { 3859 MLX5_VPORT_STATE_OP_MOD_VNIC_VPORT = 0x0, 3860 MLX5_VPORT_STATE_OP_MOD_ESW_VPORT = 0x1, 3861 }; 3862 3863 struct mlx5_ifc_arm_monitor_counter_in_bits { 3864 u8 opcode[0x10]; 3865 u8 uid[0x10]; 3866 3867 u8 reserved_at_20[0x10]; 3868 u8 op_mod[0x10]; 3869 3870 u8 reserved_at_40[0x20]; 3871 3872 u8 reserved_at_60[0x20]; 3873 }; 3874 3875 struct mlx5_ifc_arm_monitor_counter_out_bits { 3876 u8 status[0x8]; 3877 u8 reserved_at_8[0x18]; 3878 3879 u8 syndrome[0x20]; 3880 3881 u8 reserved_at_40[0x40]; 3882 }; 3883 3884 enum { 3885 MLX5_QUERY_MONITOR_CNT_TYPE_PPCNT = 0x0, 3886 MLX5_QUERY_MONITOR_CNT_TYPE_Q_COUNTER = 0x1, 3887 }; 3888 3889 enum mlx5_monitor_counter_ppcnt { 3890 MLX5_QUERY_MONITOR_PPCNT_IN_RANGE_LENGTH_ERRORS = 0x0, 3891 MLX5_QUERY_MONITOR_PPCNT_OUT_OF_RANGE_LENGTH_FIELD = 0x1, 3892 MLX5_QUERY_MONITOR_PPCNT_FRAME_TOO_LONG_ERRORS = 0x2, 3893 MLX5_QUERY_MONITOR_PPCNT_FRAME_CHECK_SEQUENCE_ERRORS = 0x3, 3894 MLX5_QUERY_MONITOR_PPCNT_ALIGNMENT_ERRORS = 0x4, 3895 MLX5_QUERY_MONITOR_PPCNT_IF_OUT_DISCARDS = 0x5, 3896 }; 3897 3898 enum { 3899 MLX5_QUERY_MONITOR_Q_COUNTER_RX_OUT_OF_BUFFER = 0x4, 3900 }; 3901 3902 struct mlx5_ifc_monitor_counter_output_bits { 3903 u8 reserved_at_0[0x4]; 3904 u8 type[0x4]; 3905 u8 reserved_at_8[0x8]; 3906 u8 counter[0x10]; 3907 3908 u8 counter_group_id[0x20]; 3909 }; 3910 3911 #define MLX5_CMD_SET_MONITOR_NUM_PPCNT_COUNTER_SET1 (6) 3912 #define MLX5_CMD_SET_MONITOR_NUM_Q_COUNTERS_SET1 (1) 3913 #define MLX5_CMD_SET_MONITOR_NUM_COUNTER (MLX5_CMD_SET_MONITOR_NUM_PPCNT_COUNTER_SET1 +\ 3914 MLX5_CMD_SET_MONITOR_NUM_Q_COUNTERS_SET1) 3915 3916 struct mlx5_ifc_set_monitor_counter_in_bits { 3917 u8 opcode[0x10]; 3918 u8 uid[0x10]; 3919 3920 u8 reserved_at_20[0x10]; 3921 u8 op_mod[0x10]; 3922 3923 u8 reserved_at_40[0x10]; 3924 u8 num_of_counters[0x10]; 3925 3926 u8 reserved_at_60[0x20]; 3927 3928 struct mlx5_ifc_monitor_counter_output_bits monitor_counter[MLX5_CMD_SET_MONITOR_NUM_COUNTER]; 3929 }; 3930 3931 struct mlx5_ifc_set_monitor_counter_out_bits { 3932 u8 status[0x8]; 3933 u8 reserved_at_8[0x18]; 3934 3935 u8 syndrome[0x20]; 3936 3937 u8 reserved_at_40[0x40]; 3938 }; 3939 3940 struct mlx5_ifc_query_vport_state_in_bits { 3941 u8 opcode[0x10]; 3942 u8 reserved_at_10[0x10]; 3943 3944 u8 reserved_at_20[0x10]; 3945 u8 op_mod[0x10]; 3946 3947 u8 other_vport[0x1]; 3948 u8 reserved_at_41[0xf]; 3949 u8 vport_number[0x10]; 3950 3951 u8 reserved_at_60[0x20]; 3952 }; 3953 3954 struct mlx5_ifc_query_vnic_env_out_bits { 3955 u8 status[0x8]; 3956 u8 reserved_at_8[0x18]; 3957 3958 u8 syndrome[0x20]; 3959 3960 u8 reserved_at_40[0x40]; 3961 3962 struct mlx5_ifc_vnic_diagnostic_statistics_bits vport_env; 3963 }; 3964 3965 enum { 3966 MLX5_QUERY_VNIC_ENV_IN_OP_MOD_VPORT_DIAG_STATISTICS = 0x0, 3967 }; 3968 3969 struct mlx5_ifc_query_vnic_env_in_bits { 3970 u8 opcode[0x10]; 3971 u8 reserved_at_10[0x10]; 3972 3973 u8 reserved_at_20[0x10]; 3974 u8 op_mod[0x10]; 3975 3976 u8 other_vport[0x1]; 3977 u8 reserved_at_41[0xf]; 3978 u8 vport_number[0x10]; 3979 3980 u8 reserved_at_60[0x20]; 3981 }; 3982 3983 struct mlx5_ifc_query_vport_counter_out_bits { 3984 u8 status[0x8]; 3985 u8 reserved_at_8[0x18]; 3986 3987 u8 syndrome[0x20]; 3988 3989 u8 reserved_at_40[0x40]; 3990 3991 struct mlx5_ifc_traffic_counter_bits received_errors; 3992 3993 struct mlx5_ifc_traffic_counter_bits transmit_errors; 3994 3995 struct mlx5_ifc_traffic_counter_bits received_ib_unicast; 3996 3997 struct mlx5_ifc_traffic_counter_bits transmitted_ib_unicast; 3998 3999 struct mlx5_ifc_traffic_counter_bits received_ib_multicast; 4000 4001 struct mlx5_ifc_traffic_counter_bits transmitted_ib_multicast; 4002 4003 struct mlx5_ifc_traffic_counter_bits received_eth_broadcast; 4004 4005 struct mlx5_ifc_traffic_counter_bits transmitted_eth_broadcast; 4006 4007 struct mlx5_ifc_traffic_counter_bits received_eth_unicast; 4008 4009 struct mlx5_ifc_traffic_counter_bits transmitted_eth_unicast; 4010 4011 struct mlx5_ifc_traffic_counter_bits received_eth_multicast; 4012 4013 struct mlx5_ifc_traffic_counter_bits transmitted_eth_multicast; 4014 4015 u8 reserved_at_680[0xa00]; 4016 }; 4017 4018 enum { 4019 MLX5_QUERY_VPORT_COUNTER_IN_OP_MOD_VPORT_COUNTERS = 0x0, 4020 }; 4021 4022 struct mlx5_ifc_query_vport_counter_in_bits { 4023 u8 opcode[0x10]; 4024 u8 reserved_at_10[0x10]; 4025 4026 u8 reserved_at_20[0x10]; 4027 u8 op_mod[0x10]; 4028 4029 u8 other_vport[0x1]; 4030 u8 reserved_at_41[0xb]; 4031 u8 port_num[0x4]; 4032 u8 vport_number[0x10]; 4033 4034 u8 reserved_at_60[0x60]; 4035 4036 u8 clear[0x1]; 4037 u8 reserved_at_c1[0x1f]; 4038 4039 u8 reserved_at_e0[0x20]; 4040 }; 4041 4042 struct mlx5_ifc_query_tis_out_bits { 4043 u8 status[0x8]; 4044 u8 reserved_at_8[0x18]; 4045 4046 u8 syndrome[0x20]; 4047 4048 u8 reserved_at_40[0x40]; 4049 4050 struct mlx5_ifc_tisc_bits tis_context; 4051 }; 4052 4053 struct mlx5_ifc_query_tis_in_bits { 4054 u8 opcode[0x10]; 4055 u8 reserved_at_10[0x10]; 4056 4057 u8 reserved_at_20[0x10]; 4058 u8 op_mod[0x10]; 4059 4060 u8 reserved_at_40[0x8]; 4061 u8 tisn[0x18]; 4062 4063 u8 reserved_at_60[0x20]; 4064 }; 4065 4066 struct mlx5_ifc_query_tir_out_bits { 4067 u8 status[0x8]; 4068 u8 reserved_at_8[0x18]; 4069 4070 u8 syndrome[0x20]; 4071 4072 u8 reserved_at_40[0xc0]; 4073 4074 struct mlx5_ifc_tirc_bits tir_context; 4075 }; 4076 4077 struct mlx5_ifc_query_tir_in_bits { 4078 u8 opcode[0x10]; 4079 u8 reserved_at_10[0x10]; 4080 4081 u8 reserved_at_20[0x10]; 4082 u8 op_mod[0x10]; 4083 4084 u8 reserved_at_40[0x8]; 4085 u8 tirn[0x18]; 4086 4087 u8 reserved_at_60[0x20]; 4088 }; 4089 4090 struct mlx5_ifc_query_srq_out_bits { 4091 u8 status[0x8]; 4092 u8 reserved_at_8[0x18]; 4093 4094 u8 syndrome[0x20]; 4095 4096 u8 reserved_at_40[0x40]; 4097 4098 struct mlx5_ifc_srqc_bits srq_context_entry; 4099 4100 u8 reserved_at_280[0x600]; 4101 4102 u8 pas[0][0x40]; 4103 }; 4104 4105 struct mlx5_ifc_query_srq_in_bits { 4106 u8 opcode[0x10]; 4107 u8 reserved_at_10[0x10]; 4108 4109 u8 reserved_at_20[0x10]; 4110 u8 op_mod[0x10]; 4111 4112 u8 reserved_at_40[0x8]; 4113 u8 srqn[0x18]; 4114 4115 u8 reserved_at_60[0x20]; 4116 }; 4117 4118 struct mlx5_ifc_query_sq_out_bits { 4119 u8 status[0x8]; 4120 u8 reserved_at_8[0x18]; 4121 4122 u8 syndrome[0x20]; 4123 4124 u8 reserved_at_40[0xc0]; 4125 4126 struct mlx5_ifc_sqc_bits sq_context; 4127 }; 4128 4129 struct mlx5_ifc_query_sq_in_bits { 4130 u8 opcode[0x10]; 4131 u8 reserved_at_10[0x10]; 4132 4133 u8 reserved_at_20[0x10]; 4134 u8 op_mod[0x10]; 4135 4136 u8 reserved_at_40[0x8]; 4137 u8 sqn[0x18]; 4138 4139 u8 reserved_at_60[0x20]; 4140 }; 4141 4142 struct mlx5_ifc_query_special_contexts_out_bits { 4143 u8 status[0x8]; 4144 u8 reserved_at_8[0x18]; 4145 4146 u8 syndrome[0x20]; 4147 4148 u8 dump_fill_mkey[0x20]; 4149 4150 u8 resd_lkey[0x20]; 4151 4152 u8 null_mkey[0x20]; 4153 4154 u8 reserved_at_a0[0x60]; 4155 }; 4156 4157 struct mlx5_ifc_query_special_contexts_in_bits { 4158 u8 opcode[0x10]; 4159 u8 reserved_at_10[0x10]; 4160 4161 u8 reserved_at_20[0x10]; 4162 u8 op_mod[0x10]; 4163 4164 u8 reserved_at_40[0x40]; 4165 }; 4166 4167 struct mlx5_ifc_query_scheduling_element_out_bits { 4168 u8 opcode[0x10]; 4169 u8 reserved_at_10[0x10]; 4170 4171 u8 reserved_at_20[0x10]; 4172 u8 op_mod[0x10]; 4173 4174 u8 reserved_at_40[0xc0]; 4175 4176 struct mlx5_ifc_scheduling_context_bits scheduling_context; 4177 4178 u8 reserved_at_300[0x100]; 4179 }; 4180 4181 enum { 4182 SCHEDULING_HIERARCHY_E_SWITCH = 0x2, 4183 }; 4184 4185 struct mlx5_ifc_query_scheduling_element_in_bits { 4186 u8 opcode[0x10]; 4187 u8 reserved_at_10[0x10]; 4188 4189 u8 reserved_at_20[0x10]; 4190 u8 op_mod[0x10]; 4191 4192 u8 scheduling_hierarchy[0x8]; 4193 u8 reserved_at_48[0x18]; 4194 4195 u8 scheduling_element_id[0x20]; 4196 4197 u8 reserved_at_80[0x180]; 4198 }; 4199 4200 struct mlx5_ifc_query_rqt_out_bits { 4201 u8 status[0x8]; 4202 u8 reserved_at_8[0x18]; 4203 4204 u8 syndrome[0x20]; 4205 4206 u8 reserved_at_40[0xc0]; 4207 4208 struct mlx5_ifc_rqtc_bits rqt_context; 4209 }; 4210 4211 struct mlx5_ifc_query_rqt_in_bits { 4212 u8 opcode[0x10]; 4213 u8 reserved_at_10[0x10]; 4214 4215 u8 reserved_at_20[0x10]; 4216 u8 op_mod[0x10]; 4217 4218 u8 reserved_at_40[0x8]; 4219 u8 rqtn[0x18]; 4220 4221 u8 reserved_at_60[0x20]; 4222 }; 4223 4224 struct mlx5_ifc_query_rq_out_bits { 4225 u8 status[0x8]; 4226 u8 reserved_at_8[0x18]; 4227 4228 u8 syndrome[0x20]; 4229 4230 u8 reserved_at_40[0xc0]; 4231 4232 struct mlx5_ifc_rqc_bits rq_context; 4233 }; 4234 4235 struct mlx5_ifc_query_rq_in_bits { 4236 u8 opcode[0x10]; 4237 u8 reserved_at_10[0x10]; 4238 4239 u8 reserved_at_20[0x10]; 4240 u8 op_mod[0x10]; 4241 4242 u8 reserved_at_40[0x8]; 4243 u8 rqn[0x18]; 4244 4245 u8 reserved_at_60[0x20]; 4246 }; 4247 4248 struct mlx5_ifc_query_roce_address_out_bits { 4249 u8 status[0x8]; 4250 u8 reserved_at_8[0x18]; 4251 4252 u8 syndrome[0x20]; 4253 4254 u8 reserved_at_40[0x40]; 4255 4256 struct mlx5_ifc_roce_addr_layout_bits roce_address; 4257 }; 4258 4259 struct mlx5_ifc_query_roce_address_in_bits { 4260 u8 opcode[0x10]; 4261 u8 reserved_at_10[0x10]; 4262 4263 u8 reserved_at_20[0x10]; 4264 u8 op_mod[0x10]; 4265 4266 u8 roce_address_index[0x10]; 4267 u8 reserved_at_50[0xc]; 4268 u8 vhca_port_num[0x4]; 4269 4270 u8 reserved_at_60[0x20]; 4271 }; 4272 4273 struct mlx5_ifc_query_rmp_out_bits { 4274 u8 status[0x8]; 4275 u8 reserved_at_8[0x18]; 4276 4277 u8 syndrome[0x20]; 4278 4279 u8 reserved_at_40[0xc0]; 4280 4281 struct mlx5_ifc_rmpc_bits rmp_context; 4282 }; 4283 4284 struct mlx5_ifc_query_rmp_in_bits { 4285 u8 opcode[0x10]; 4286 u8 reserved_at_10[0x10]; 4287 4288 u8 reserved_at_20[0x10]; 4289 u8 op_mod[0x10]; 4290 4291 u8 reserved_at_40[0x8]; 4292 u8 rmpn[0x18]; 4293 4294 u8 reserved_at_60[0x20]; 4295 }; 4296 4297 struct mlx5_ifc_query_qp_out_bits { 4298 u8 status[0x8]; 4299 u8 reserved_at_8[0x18]; 4300 4301 u8 syndrome[0x20]; 4302 4303 u8 reserved_at_40[0x40]; 4304 4305 u8 opt_param_mask[0x20]; 4306 4307 u8 reserved_at_a0[0x20]; 4308 4309 struct mlx5_ifc_qpc_bits qpc; 4310 4311 u8 reserved_at_800[0x80]; 4312 4313 u8 pas[0][0x40]; 4314 }; 4315 4316 struct mlx5_ifc_query_qp_in_bits { 4317 u8 opcode[0x10]; 4318 u8 reserved_at_10[0x10]; 4319 4320 u8 reserved_at_20[0x10]; 4321 u8 op_mod[0x10]; 4322 4323 u8 reserved_at_40[0x8]; 4324 u8 qpn[0x18]; 4325 4326 u8 reserved_at_60[0x20]; 4327 }; 4328 4329 struct mlx5_ifc_query_q_counter_out_bits { 4330 u8 status[0x8]; 4331 u8 reserved_at_8[0x18]; 4332 4333 u8 syndrome[0x20]; 4334 4335 u8 reserved_at_40[0x40]; 4336 4337 u8 rx_write_requests[0x20]; 4338 4339 u8 reserved_at_a0[0x20]; 4340 4341 u8 rx_read_requests[0x20]; 4342 4343 u8 reserved_at_e0[0x20]; 4344 4345 u8 rx_atomic_requests[0x20]; 4346 4347 u8 reserved_at_120[0x20]; 4348 4349 u8 rx_dct_connect[0x20]; 4350 4351 u8 reserved_at_160[0x20]; 4352 4353 u8 out_of_buffer[0x20]; 4354 4355 u8 reserved_at_1a0[0x20]; 4356 4357 u8 out_of_sequence[0x20]; 4358 4359 u8 reserved_at_1e0[0x20]; 4360 4361 u8 duplicate_request[0x20]; 4362 4363 u8 reserved_at_220[0x20]; 4364 4365 u8 rnr_nak_retry_err[0x20]; 4366 4367 u8 reserved_at_260[0x20]; 4368 4369 u8 packet_seq_err[0x20]; 4370 4371 u8 reserved_at_2a0[0x20]; 4372 4373 u8 implied_nak_seq_err[0x20]; 4374 4375 u8 reserved_at_2e0[0x20]; 4376 4377 u8 local_ack_timeout_err[0x20]; 4378 4379 u8 reserved_at_320[0xa0]; 4380 4381 u8 resp_local_length_error[0x20]; 4382 4383 u8 req_local_length_error[0x20]; 4384 4385 u8 resp_local_qp_error[0x20]; 4386 4387 u8 local_operation_error[0x20]; 4388 4389 u8 resp_local_protection[0x20]; 4390 4391 u8 req_local_protection[0x20]; 4392 4393 u8 resp_cqe_error[0x20]; 4394 4395 u8 req_cqe_error[0x20]; 4396 4397 u8 req_mw_binding[0x20]; 4398 4399 u8 req_bad_response[0x20]; 4400 4401 u8 req_remote_invalid_request[0x20]; 4402 4403 u8 resp_remote_invalid_request[0x20]; 4404 4405 u8 req_remote_access_errors[0x20]; 4406 4407 u8 resp_remote_access_errors[0x20]; 4408 4409 u8 req_remote_operation_errors[0x20]; 4410 4411 u8 req_transport_retries_exceeded[0x20]; 4412 4413 u8 cq_overflow[0x20]; 4414 4415 u8 resp_cqe_flush_error[0x20]; 4416 4417 u8 req_cqe_flush_error[0x20]; 4418 4419 u8 reserved_at_620[0x1e0]; 4420 }; 4421 4422 struct mlx5_ifc_query_q_counter_in_bits { 4423 u8 opcode[0x10]; 4424 u8 reserved_at_10[0x10]; 4425 4426 u8 reserved_at_20[0x10]; 4427 u8 op_mod[0x10]; 4428 4429 u8 reserved_at_40[0x80]; 4430 4431 u8 clear[0x1]; 4432 u8 reserved_at_c1[0x1f]; 4433 4434 u8 reserved_at_e0[0x18]; 4435 u8 counter_set_id[0x8]; 4436 }; 4437 4438 struct mlx5_ifc_query_pages_out_bits { 4439 u8 status[0x8]; 4440 u8 reserved_at_8[0x18]; 4441 4442 u8 syndrome[0x20]; 4443 4444 u8 reserved_at_40[0x10]; 4445 u8 function_id[0x10]; 4446 4447 u8 num_pages[0x20]; 4448 }; 4449 4450 enum { 4451 MLX5_QUERY_PAGES_IN_OP_MOD_BOOT_PAGES = 0x1, 4452 MLX5_QUERY_PAGES_IN_OP_MOD_INIT_PAGES = 0x2, 4453 MLX5_QUERY_PAGES_IN_OP_MOD_REGULAR_PAGES = 0x3, 4454 }; 4455 4456 struct mlx5_ifc_query_pages_in_bits { 4457 u8 opcode[0x10]; 4458 u8 reserved_at_10[0x10]; 4459 4460 u8 reserved_at_20[0x10]; 4461 u8 op_mod[0x10]; 4462 4463 u8 reserved_at_40[0x10]; 4464 u8 function_id[0x10]; 4465 4466 u8 reserved_at_60[0x20]; 4467 }; 4468 4469 struct mlx5_ifc_query_nic_vport_context_out_bits { 4470 u8 status[0x8]; 4471 u8 reserved_at_8[0x18]; 4472 4473 u8 syndrome[0x20]; 4474 4475 u8 reserved_at_40[0x40]; 4476 4477 struct mlx5_ifc_nic_vport_context_bits nic_vport_context; 4478 }; 4479 4480 struct mlx5_ifc_query_nic_vport_context_in_bits { 4481 u8 opcode[0x10]; 4482 u8 reserved_at_10[0x10]; 4483 4484 u8 reserved_at_20[0x10]; 4485 u8 op_mod[0x10]; 4486 4487 u8 other_vport[0x1]; 4488 u8 reserved_at_41[0xf]; 4489 u8 vport_number[0x10]; 4490 4491 u8 reserved_at_60[0x5]; 4492 u8 allowed_list_type[0x3]; 4493 u8 reserved_at_68[0x18]; 4494 }; 4495 4496 struct mlx5_ifc_query_mkey_out_bits { 4497 u8 status[0x8]; 4498 u8 reserved_at_8[0x18]; 4499 4500 u8 syndrome[0x20]; 4501 4502 u8 reserved_at_40[0x40]; 4503 4504 struct mlx5_ifc_mkc_bits memory_key_mkey_entry; 4505 4506 u8 reserved_at_280[0x600]; 4507 4508 u8 bsf0_klm0_pas_mtt0_1[16][0x8]; 4509 4510 u8 bsf1_klm1_pas_mtt2_3[16][0x8]; 4511 }; 4512 4513 struct mlx5_ifc_query_mkey_in_bits { 4514 u8 opcode[0x10]; 4515 u8 reserved_at_10[0x10]; 4516 4517 u8 reserved_at_20[0x10]; 4518 u8 op_mod[0x10]; 4519 4520 u8 reserved_at_40[0x8]; 4521 u8 mkey_index[0x18]; 4522 4523 u8 pg_access[0x1]; 4524 u8 reserved_at_61[0x1f]; 4525 }; 4526 4527 struct mlx5_ifc_query_mad_demux_out_bits { 4528 u8 status[0x8]; 4529 u8 reserved_at_8[0x18]; 4530 4531 u8 syndrome[0x20]; 4532 4533 u8 reserved_at_40[0x40]; 4534 4535 u8 mad_dumux_parameters_block[0x20]; 4536 }; 4537 4538 struct mlx5_ifc_query_mad_demux_in_bits { 4539 u8 opcode[0x10]; 4540 u8 reserved_at_10[0x10]; 4541 4542 u8 reserved_at_20[0x10]; 4543 u8 op_mod[0x10]; 4544 4545 u8 reserved_at_40[0x40]; 4546 }; 4547 4548 struct mlx5_ifc_query_l2_table_entry_out_bits { 4549 u8 status[0x8]; 4550 u8 reserved_at_8[0x18]; 4551 4552 u8 syndrome[0x20]; 4553 4554 u8 reserved_at_40[0xa0]; 4555 4556 u8 reserved_at_e0[0x13]; 4557 u8 vlan_valid[0x1]; 4558 u8 vlan[0xc]; 4559 4560 struct mlx5_ifc_mac_address_layout_bits mac_address; 4561 4562 u8 reserved_at_140[0xc0]; 4563 }; 4564 4565 struct mlx5_ifc_query_l2_table_entry_in_bits { 4566 u8 opcode[0x10]; 4567 u8 reserved_at_10[0x10]; 4568 4569 u8 reserved_at_20[0x10]; 4570 u8 op_mod[0x10]; 4571 4572 u8 reserved_at_40[0x60]; 4573 4574 u8 reserved_at_a0[0x8]; 4575 u8 table_index[0x18]; 4576 4577 u8 reserved_at_c0[0x140]; 4578 }; 4579 4580 struct mlx5_ifc_query_issi_out_bits { 4581 u8 status[0x8]; 4582 u8 reserved_at_8[0x18]; 4583 4584 u8 syndrome[0x20]; 4585 4586 u8 reserved_at_40[0x10]; 4587 u8 current_issi[0x10]; 4588 4589 u8 reserved_at_60[0xa0]; 4590 4591 u8 reserved_at_100[76][0x8]; 4592 u8 supported_issi_dw0[0x20]; 4593 }; 4594 4595 struct mlx5_ifc_query_issi_in_bits { 4596 u8 opcode[0x10]; 4597 u8 reserved_at_10[0x10]; 4598 4599 u8 reserved_at_20[0x10]; 4600 u8 op_mod[0x10]; 4601 4602 u8 reserved_at_40[0x40]; 4603 }; 4604 4605 struct mlx5_ifc_set_driver_version_out_bits { 4606 u8 status[0x8]; 4607 u8 reserved_0[0x18]; 4608 4609 u8 syndrome[0x20]; 4610 u8 reserved_1[0x40]; 4611 }; 4612 4613 struct mlx5_ifc_set_driver_version_in_bits { 4614 u8 opcode[0x10]; 4615 u8 reserved_0[0x10]; 4616 4617 u8 reserved_1[0x10]; 4618 u8 op_mod[0x10]; 4619 4620 u8 reserved_2[0x40]; 4621 u8 driver_version[64][0x8]; 4622 }; 4623 4624 struct mlx5_ifc_query_hca_vport_pkey_out_bits { 4625 u8 status[0x8]; 4626 u8 reserved_at_8[0x18]; 4627 4628 u8 syndrome[0x20]; 4629 4630 u8 reserved_at_40[0x40]; 4631 4632 struct mlx5_ifc_pkey_bits pkey[0]; 4633 }; 4634 4635 struct mlx5_ifc_query_hca_vport_pkey_in_bits { 4636 u8 opcode[0x10]; 4637 u8 reserved_at_10[0x10]; 4638 4639 u8 reserved_at_20[0x10]; 4640 u8 op_mod[0x10]; 4641 4642 u8 other_vport[0x1]; 4643 u8 reserved_at_41[0xb]; 4644 u8 port_num[0x4]; 4645 u8 vport_number[0x10]; 4646 4647 u8 reserved_at_60[0x10]; 4648 u8 pkey_index[0x10]; 4649 }; 4650 4651 enum { 4652 MLX5_HCA_VPORT_SEL_PORT_GUID = 1 << 0, 4653 MLX5_HCA_VPORT_SEL_NODE_GUID = 1 << 1, 4654 MLX5_HCA_VPORT_SEL_STATE_POLICY = 1 << 2, 4655 }; 4656 4657 struct mlx5_ifc_query_hca_vport_gid_out_bits { 4658 u8 status[0x8]; 4659 u8 reserved_at_8[0x18]; 4660 4661 u8 syndrome[0x20]; 4662 4663 u8 reserved_at_40[0x20]; 4664 4665 u8 gids_num[0x10]; 4666 u8 reserved_at_70[0x10]; 4667 4668 struct mlx5_ifc_array128_auto_bits gid[0]; 4669 }; 4670 4671 struct mlx5_ifc_query_hca_vport_gid_in_bits { 4672 u8 opcode[0x10]; 4673 u8 reserved_at_10[0x10]; 4674 4675 u8 reserved_at_20[0x10]; 4676 u8 op_mod[0x10]; 4677 4678 u8 other_vport[0x1]; 4679 u8 reserved_at_41[0xb]; 4680 u8 port_num[0x4]; 4681 u8 vport_number[0x10]; 4682 4683 u8 reserved_at_60[0x10]; 4684 u8 gid_index[0x10]; 4685 }; 4686 4687 struct mlx5_ifc_query_hca_vport_context_out_bits { 4688 u8 status[0x8]; 4689 u8 reserved_at_8[0x18]; 4690 4691 u8 syndrome[0x20]; 4692 4693 u8 reserved_at_40[0x40]; 4694 4695 struct mlx5_ifc_hca_vport_context_bits hca_vport_context; 4696 }; 4697 4698 struct mlx5_ifc_query_hca_vport_context_in_bits { 4699 u8 opcode[0x10]; 4700 u8 reserved_at_10[0x10]; 4701 4702 u8 reserved_at_20[0x10]; 4703 u8 op_mod[0x10]; 4704 4705 u8 other_vport[0x1]; 4706 u8 reserved_at_41[0xb]; 4707 u8 port_num[0x4]; 4708 u8 vport_number[0x10]; 4709 4710 u8 reserved_at_60[0x20]; 4711 }; 4712 4713 struct mlx5_ifc_query_hca_cap_out_bits { 4714 u8 status[0x8]; 4715 u8 reserved_at_8[0x18]; 4716 4717 u8 syndrome[0x20]; 4718 4719 u8 reserved_at_40[0x40]; 4720 4721 union mlx5_ifc_hca_cap_union_bits capability; 4722 }; 4723 4724 struct mlx5_ifc_query_hca_cap_in_bits { 4725 u8 opcode[0x10]; 4726 u8 reserved_at_10[0x10]; 4727 4728 u8 reserved_at_20[0x10]; 4729 u8 op_mod[0x10]; 4730 4731 u8 reserved_at_40[0x40]; 4732 }; 4733 4734 struct mlx5_ifc_query_flow_table_out_bits { 4735 u8 status[0x8]; 4736 u8 reserved_at_8[0x18]; 4737 4738 u8 syndrome[0x20]; 4739 4740 u8 reserved_at_40[0x80]; 4741 4742 u8 reserved_at_c0[0x8]; 4743 u8 level[0x8]; 4744 u8 reserved_at_d0[0x8]; 4745 u8 log_size[0x8]; 4746 4747 u8 reserved_at_e0[0x120]; 4748 }; 4749 4750 struct mlx5_ifc_query_flow_table_in_bits { 4751 u8 opcode[0x10]; 4752 u8 reserved_at_10[0x10]; 4753 4754 u8 reserved_at_20[0x10]; 4755 u8 op_mod[0x10]; 4756 4757 u8 reserved_at_40[0x40]; 4758 4759 u8 table_type[0x8]; 4760 u8 reserved_at_88[0x18]; 4761 4762 u8 reserved_at_a0[0x8]; 4763 u8 table_id[0x18]; 4764 4765 u8 reserved_at_c0[0x140]; 4766 }; 4767 4768 struct mlx5_ifc_query_fte_out_bits { 4769 u8 status[0x8]; 4770 u8 reserved_at_8[0x18]; 4771 4772 u8 syndrome[0x20]; 4773 4774 u8 reserved_at_40[0x1c0]; 4775 4776 struct mlx5_ifc_flow_context_bits flow_context; 4777 }; 4778 4779 struct mlx5_ifc_query_fte_in_bits { 4780 u8 opcode[0x10]; 4781 u8 reserved_at_10[0x10]; 4782 4783 u8 reserved_at_20[0x10]; 4784 u8 op_mod[0x10]; 4785 4786 u8 reserved_at_40[0x40]; 4787 4788 u8 table_type[0x8]; 4789 u8 reserved_at_88[0x18]; 4790 4791 u8 reserved_at_a0[0x8]; 4792 u8 table_id[0x18]; 4793 4794 u8 reserved_at_c0[0x40]; 4795 4796 u8 flow_index[0x20]; 4797 4798 u8 reserved_at_120[0xe0]; 4799 }; 4800 4801 enum { 4802 MLX5_QUERY_FLOW_GROUP_OUT_MATCH_CRITERIA_ENABLE_OUTER_HEADERS = 0x0, 4803 MLX5_QUERY_FLOW_GROUP_OUT_MATCH_CRITERIA_ENABLE_MISC_PARAMETERS = 0x1, 4804 MLX5_QUERY_FLOW_GROUP_OUT_MATCH_CRITERIA_ENABLE_INNER_HEADERS = 0x2, 4805 MLX5_QUERY_FLOW_GROUP_IN_MATCH_CRITERIA_ENABLE_MISC_PARAMETERS_2 = 0x3, 4806 }; 4807 4808 struct mlx5_ifc_query_flow_group_out_bits { 4809 u8 status[0x8]; 4810 u8 reserved_at_8[0x18]; 4811 4812 u8 syndrome[0x20]; 4813 4814 u8 reserved_at_40[0xa0]; 4815 4816 u8 start_flow_index[0x20]; 4817 4818 u8 reserved_at_100[0x20]; 4819 4820 u8 end_flow_index[0x20]; 4821 4822 u8 reserved_at_140[0xa0]; 4823 4824 u8 reserved_at_1e0[0x18]; 4825 u8 match_criteria_enable[0x8]; 4826 4827 struct mlx5_ifc_fte_match_param_bits match_criteria; 4828 4829 u8 reserved_at_1200[0xe00]; 4830 }; 4831 4832 struct mlx5_ifc_query_flow_group_in_bits { 4833 u8 opcode[0x10]; 4834 u8 reserved_at_10[0x10]; 4835 4836 u8 reserved_at_20[0x10]; 4837 u8 op_mod[0x10]; 4838 4839 u8 reserved_at_40[0x40]; 4840 4841 u8 table_type[0x8]; 4842 u8 reserved_at_88[0x18]; 4843 4844 u8 reserved_at_a0[0x8]; 4845 u8 table_id[0x18]; 4846 4847 u8 group_id[0x20]; 4848 4849 u8 reserved_at_e0[0x120]; 4850 }; 4851 4852 struct mlx5_ifc_query_flow_counter_out_bits { 4853 u8 status[0x8]; 4854 u8 reserved_at_8[0x18]; 4855 4856 u8 syndrome[0x20]; 4857 4858 u8 reserved_at_40[0x40]; 4859 4860 struct mlx5_ifc_traffic_counter_bits flow_statistics[0]; 4861 }; 4862 4863 struct mlx5_ifc_query_flow_counter_in_bits { 4864 u8 opcode[0x10]; 4865 u8 reserved_at_10[0x10]; 4866 4867 u8 reserved_at_20[0x10]; 4868 u8 op_mod[0x10]; 4869 4870 u8 reserved_at_40[0x80]; 4871 4872 u8 clear[0x1]; 4873 u8 reserved_at_c1[0xf]; 4874 u8 num_of_counters[0x10]; 4875 4876 u8 flow_counter_id[0x20]; 4877 }; 4878 4879 struct mlx5_ifc_query_esw_vport_context_out_bits { 4880 u8 status[0x8]; 4881 u8 reserved_at_8[0x18]; 4882 4883 u8 syndrome[0x20]; 4884 4885 u8 reserved_at_40[0x40]; 4886 4887 struct mlx5_ifc_esw_vport_context_bits esw_vport_context; 4888 }; 4889 4890 struct mlx5_ifc_query_esw_vport_context_in_bits { 4891 u8 opcode[0x10]; 4892 u8 reserved_at_10[0x10]; 4893 4894 u8 reserved_at_20[0x10]; 4895 u8 op_mod[0x10]; 4896 4897 u8 other_vport[0x1]; 4898 u8 reserved_at_41[0xf]; 4899 u8 vport_number[0x10]; 4900 4901 u8 reserved_at_60[0x20]; 4902 }; 4903 4904 struct mlx5_ifc_modify_esw_vport_context_out_bits { 4905 u8 status[0x8]; 4906 u8 reserved_at_8[0x18]; 4907 4908 u8 syndrome[0x20]; 4909 4910 u8 reserved_at_40[0x40]; 4911 }; 4912 4913 struct mlx5_ifc_esw_vport_context_fields_select_bits { 4914 u8 reserved_at_0[0x1c]; 4915 u8 vport_cvlan_insert[0x1]; 4916 u8 vport_svlan_insert[0x1]; 4917 u8 vport_cvlan_strip[0x1]; 4918 u8 vport_svlan_strip[0x1]; 4919 }; 4920 4921 struct mlx5_ifc_modify_esw_vport_context_in_bits { 4922 u8 opcode[0x10]; 4923 u8 reserved_at_10[0x10]; 4924 4925 u8 reserved_at_20[0x10]; 4926 u8 op_mod[0x10]; 4927 4928 u8 other_vport[0x1]; 4929 u8 reserved_at_41[0xf]; 4930 u8 vport_number[0x10]; 4931 4932 struct mlx5_ifc_esw_vport_context_fields_select_bits field_select; 4933 4934 struct mlx5_ifc_esw_vport_context_bits esw_vport_context; 4935 }; 4936 4937 struct mlx5_ifc_query_eq_out_bits { 4938 u8 status[0x8]; 4939 u8 reserved_at_8[0x18]; 4940 4941 u8 syndrome[0x20]; 4942 4943 u8 reserved_at_40[0x40]; 4944 4945 struct mlx5_ifc_eqc_bits eq_context_entry; 4946 4947 u8 reserved_at_280[0x40]; 4948 4949 u8 event_bitmask[0x40]; 4950 4951 u8 reserved_at_300[0x580]; 4952 4953 u8 pas[0][0x40]; 4954 }; 4955 4956 struct mlx5_ifc_query_eq_in_bits { 4957 u8 opcode[0x10]; 4958 u8 reserved_at_10[0x10]; 4959 4960 u8 reserved_at_20[0x10]; 4961 u8 op_mod[0x10]; 4962 4963 u8 reserved_at_40[0x18]; 4964 u8 eq_number[0x8]; 4965 4966 u8 reserved_at_60[0x20]; 4967 }; 4968 4969 struct mlx5_ifc_packet_reformat_context_in_bits { 4970 u8 reserved_at_0[0x5]; 4971 u8 reformat_type[0x3]; 4972 u8 reserved_at_8[0xe]; 4973 u8 reformat_data_size[0xa]; 4974 4975 u8 reserved_at_20[0x10]; 4976 u8 reformat_data[2][0x8]; 4977 4978 u8 more_reformat_data[0][0x8]; 4979 }; 4980 4981 struct mlx5_ifc_query_packet_reformat_context_out_bits { 4982 u8 status[0x8]; 4983 u8 reserved_at_8[0x18]; 4984 4985 u8 syndrome[0x20]; 4986 4987 u8 reserved_at_40[0xa0]; 4988 4989 struct mlx5_ifc_packet_reformat_context_in_bits packet_reformat_context[0]; 4990 }; 4991 4992 struct mlx5_ifc_query_packet_reformat_context_in_bits { 4993 u8 opcode[0x10]; 4994 u8 reserved_at_10[0x10]; 4995 4996 u8 reserved_at_20[0x10]; 4997 u8 op_mod[0x10]; 4998 4999 u8 packet_reformat_id[0x20]; 5000 5001 u8 reserved_at_60[0xa0]; 5002 }; 5003 5004 struct mlx5_ifc_alloc_packet_reformat_context_out_bits { 5005 u8 status[0x8]; 5006 u8 reserved_at_8[0x18]; 5007 5008 u8 syndrome[0x20]; 5009 5010 u8 packet_reformat_id[0x20]; 5011 5012 u8 reserved_at_60[0x20]; 5013 }; 5014 5015 enum { 5016 MLX5_REFORMAT_TYPE_L2_TO_VXLAN = 0x0, 5017 MLX5_REFORMAT_TYPE_L2_TO_NVGRE = 0x1, 5018 MLX5_REFORMAT_TYPE_L2_TO_L2_TUNNEL = 0x2, 5019 MLX5_REFORMAT_TYPE_L3_TUNNEL_TO_L2 = 0x3, 5020 MLX5_REFORMAT_TYPE_L2_TO_L3_TUNNEL = 0x4, 5021 }; 5022 5023 struct mlx5_ifc_alloc_packet_reformat_context_in_bits { 5024 u8 opcode[0x10]; 5025 u8 reserved_at_10[0x10]; 5026 5027 u8 reserved_at_20[0x10]; 5028 u8 op_mod[0x10]; 5029 5030 u8 reserved_at_40[0xa0]; 5031 5032 struct mlx5_ifc_packet_reformat_context_in_bits packet_reformat_context; 5033 }; 5034 5035 struct mlx5_ifc_dealloc_packet_reformat_context_out_bits { 5036 u8 status[0x8]; 5037 u8 reserved_at_8[0x18]; 5038 5039 u8 syndrome[0x20]; 5040 5041 u8 reserved_at_40[0x40]; 5042 }; 5043 5044 struct mlx5_ifc_dealloc_packet_reformat_context_in_bits { 5045 u8 opcode[0x10]; 5046 u8 reserved_at_10[0x10]; 5047 5048 u8 reserved_20[0x10]; 5049 u8 op_mod[0x10]; 5050 5051 u8 packet_reformat_id[0x20]; 5052 5053 u8 reserved_60[0x20]; 5054 }; 5055 5056 struct mlx5_ifc_set_action_in_bits { 5057 u8 action_type[0x4]; 5058 u8 field[0xc]; 5059 u8 reserved_at_10[0x3]; 5060 u8 offset[0x5]; 5061 u8 reserved_at_18[0x3]; 5062 u8 length[0x5]; 5063 5064 u8 data[0x20]; 5065 }; 5066 5067 struct mlx5_ifc_add_action_in_bits { 5068 u8 action_type[0x4]; 5069 u8 field[0xc]; 5070 u8 reserved_at_10[0x10]; 5071 5072 u8 data[0x20]; 5073 }; 5074 5075 union mlx5_ifc_set_action_in_add_action_in_auto_bits { 5076 struct mlx5_ifc_set_action_in_bits set_action_in; 5077 struct mlx5_ifc_add_action_in_bits add_action_in; 5078 u8 reserved_at_0[0x40]; 5079 }; 5080 5081 enum { 5082 MLX5_ACTION_TYPE_SET = 0x1, 5083 MLX5_ACTION_TYPE_ADD = 0x2, 5084 }; 5085 5086 enum { 5087 MLX5_ACTION_IN_FIELD_OUT_SMAC_47_16 = 0x1, 5088 MLX5_ACTION_IN_FIELD_OUT_SMAC_15_0 = 0x2, 5089 MLX5_ACTION_IN_FIELD_OUT_ETHERTYPE = 0x3, 5090 MLX5_ACTION_IN_FIELD_OUT_DMAC_47_16 = 0x4, 5091 MLX5_ACTION_IN_FIELD_OUT_DMAC_15_0 = 0x5, 5092 MLX5_ACTION_IN_FIELD_OUT_IP_DSCP = 0x6, 5093 MLX5_ACTION_IN_FIELD_OUT_TCP_FLAGS = 0x7, 5094 MLX5_ACTION_IN_FIELD_OUT_TCP_SPORT = 0x8, 5095 MLX5_ACTION_IN_FIELD_OUT_TCP_DPORT = 0x9, 5096 MLX5_ACTION_IN_FIELD_OUT_IP_TTL = 0xa, 5097 MLX5_ACTION_IN_FIELD_OUT_UDP_SPORT = 0xb, 5098 MLX5_ACTION_IN_FIELD_OUT_UDP_DPORT = 0xc, 5099 MLX5_ACTION_IN_FIELD_OUT_SIPV6_127_96 = 0xd, 5100 MLX5_ACTION_IN_FIELD_OUT_SIPV6_95_64 = 0xe, 5101 MLX5_ACTION_IN_FIELD_OUT_SIPV6_63_32 = 0xf, 5102 MLX5_ACTION_IN_FIELD_OUT_SIPV6_31_0 = 0x10, 5103 MLX5_ACTION_IN_FIELD_OUT_DIPV6_127_96 = 0x11, 5104 MLX5_ACTION_IN_FIELD_OUT_DIPV6_95_64 = 0x12, 5105 MLX5_ACTION_IN_FIELD_OUT_DIPV6_63_32 = 0x13, 5106 MLX5_ACTION_IN_FIELD_OUT_DIPV6_31_0 = 0x14, 5107 MLX5_ACTION_IN_FIELD_OUT_SIPV4 = 0x15, 5108 MLX5_ACTION_IN_FIELD_OUT_DIPV4 = 0x16, 5109 MLX5_ACTION_IN_FIELD_OUT_IPV6_HOPLIMIT = 0x47, 5110 }; 5111 5112 struct mlx5_ifc_alloc_modify_header_context_out_bits { 5113 u8 status[0x8]; 5114 u8 reserved_at_8[0x18]; 5115 5116 u8 syndrome[0x20]; 5117 5118 u8 modify_header_id[0x20]; 5119 5120 u8 reserved_at_60[0x20]; 5121 }; 5122 5123 struct mlx5_ifc_alloc_modify_header_context_in_bits { 5124 u8 opcode[0x10]; 5125 u8 reserved_at_10[0x10]; 5126 5127 u8 reserved_at_20[0x10]; 5128 u8 op_mod[0x10]; 5129 5130 u8 reserved_at_40[0x20]; 5131 5132 u8 table_type[0x8]; 5133 u8 reserved_at_68[0x10]; 5134 u8 num_of_actions[0x8]; 5135 5136 union mlx5_ifc_set_action_in_add_action_in_auto_bits actions[0]; 5137 }; 5138 5139 struct mlx5_ifc_dealloc_modify_header_context_out_bits { 5140 u8 status[0x8]; 5141 u8 reserved_at_8[0x18]; 5142 5143 u8 syndrome[0x20]; 5144 5145 u8 reserved_at_40[0x40]; 5146 }; 5147 5148 struct mlx5_ifc_dealloc_modify_header_context_in_bits { 5149 u8 opcode[0x10]; 5150 u8 reserved_at_10[0x10]; 5151 5152 u8 reserved_at_20[0x10]; 5153 u8 op_mod[0x10]; 5154 5155 u8 modify_header_id[0x20]; 5156 5157 u8 reserved_at_60[0x20]; 5158 }; 5159 5160 struct mlx5_ifc_query_dct_out_bits { 5161 u8 status[0x8]; 5162 u8 reserved_at_8[0x18]; 5163 5164 u8 syndrome[0x20]; 5165 5166 u8 reserved_at_40[0x40]; 5167 5168 struct mlx5_ifc_dctc_bits dct_context_entry; 5169 5170 u8 reserved_at_280[0x180]; 5171 }; 5172 5173 struct mlx5_ifc_query_dct_in_bits { 5174 u8 opcode[0x10]; 5175 u8 reserved_at_10[0x10]; 5176 5177 u8 reserved_at_20[0x10]; 5178 u8 op_mod[0x10]; 5179 5180 u8 reserved_at_40[0x8]; 5181 u8 dctn[0x18]; 5182 5183 u8 reserved_at_60[0x20]; 5184 }; 5185 5186 struct mlx5_ifc_query_cq_out_bits { 5187 u8 status[0x8]; 5188 u8 reserved_at_8[0x18]; 5189 5190 u8 syndrome[0x20]; 5191 5192 u8 reserved_at_40[0x40]; 5193 5194 struct mlx5_ifc_cqc_bits cq_context; 5195 5196 u8 reserved_at_280[0x600]; 5197 5198 u8 pas[0][0x40]; 5199 }; 5200 5201 struct mlx5_ifc_query_cq_in_bits { 5202 u8 opcode[0x10]; 5203 u8 reserved_at_10[0x10]; 5204 5205 u8 reserved_at_20[0x10]; 5206 u8 op_mod[0x10]; 5207 5208 u8 reserved_at_40[0x8]; 5209 u8 cqn[0x18]; 5210 5211 u8 reserved_at_60[0x20]; 5212 }; 5213 5214 struct mlx5_ifc_query_cong_status_out_bits { 5215 u8 status[0x8]; 5216 u8 reserved_at_8[0x18]; 5217 5218 u8 syndrome[0x20]; 5219 5220 u8 reserved_at_40[0x20]; 5221 5222 u8 enable[0x1]; 5223 u8 tag_enable[0x1]; 5224 u8 reserved_at_62[0x1e]; 5225 }; 5226 5227 struct mlx5_ifc_query_cong_status_in_bits { 5228 u8 opcode[0x10]; 5229 u8 reserved_at_10[0x10]; 5230 5231 u8 reserved_at_20[0x10]; 5232 u8 op_mod[0x10]; 5233 5234 u8 reserved_at_40[0x18]; 5235 u8 priority[0x4]; 5236 u8 cong_protocol[0x4]; 5237 5238 u8 reserved_at_60[0x20]; 5239 }; 5240 5241 struct mlx5_ifc_query_cong_statistics_out_bits { 5242 u8 status[0x8]; 5243 u8 reserved_at_8[0x18]; 5244 5245 u8 syndrome[0x20]; 5246 5247 u8 reserved_at_40[0x40]; 5248 5249 u8 rp_cur_flows[0x20]; 5250 5251 u8 sum_flows[0x20]; 5252 5253 u8 rp_cnp_ignored_high[0x20]; 5254 5255 u8 rp_cnp_ignored_low[0x20]; 5256 5257 u8 rp_cnp_handled_high[0x20]; 5258 5259 u8 rp_cnp_handled_low[0x20]; 5260 5261 u8 reserved_at_140[0x100]; 5262 5263 u8 time_stamp_high[0x20]; 5264 5265 u8 time_stamp_low[0x20]; 5266 5267 u8 accumulators_period[0x20]; 5268 5269 u8 np_ecn_marked_roce_packets_high[0x20]; 5270 5271 u8 np_ecn_marked_roce_packets_low[0x20]; 5272 5273 u8 np_cnp_sent_high[0x20]; 5274 5275 u8 np_cnp_sent_low[0x20]; 5276 5277 u8 reserved_at_320[0x560]; 5278 }; 5279 5280 struct mlx5_ifc_query_cong_statistics_in_bits { 5281 u8 opcode[0x10]; 5282 u8 reserved_at_10[0x10]; 5283 5284 u8 reserved_at_20[0x10]; 5285 u8 op_mod[0x10]; 5286 5287 u8 clear[0x1]; 5288 u8 reserved_at_41[0x1f]; 5289 5290 u8 reserved_at_60[0x20]; 5291 }; 5292 5293 struct mlx5_ifc_query_cong_params_out_bits { 5294 u8 status[0x8]; 5295 u8 reserved_at_8[0x18]; 5296 5297 u8 syndrome[0x20]; 5298 5299 u8 reserved_at_40[0x40]; 5300 5301 union mlx5_ifc_cong_control_roce_ecn_auto_bits congestion_parameters; 5302 }; 5303 5304 struct mlx5_ifc_query_cong_params_in_bits { 5305 u8 opcode[0x10]; 5306 u8 reserved_at_10[0x10]; 5307 5308 u8 reserved_at_20[0x10]; 5309 u8 op_mod[0x10]; 5310 5311 u8 reserved_at_40[0x1c]; 5312 u8 cong_protocol[0x4]; 5313 5314 u8 reserved_at_60[0x20]; 5315 }; 5316 5317 struct mlx5_ifc_query_adapter_out_bits { 5318 u8 status[0x8]; 5319 u8 reserved_at_8[0x18]; 5320 5321 u8 syndrome[0x20]; 5322 5323 u8 reserved_at_40[0x40]; 5324 5325 struct mlx5_ifc_query_adapter_param_block_bits query_adapter_struct; 5326 }; 5327 5328 struct mlx5_ifc_query_adapter_in_bits { 5329 u8 opcode[0x10]; 5330 u8 reserved_at_10[0x10]; 5331 5332 u8 reserved_at_20[0x10]; 5333 u8 op_mod[0x10]; 5334 5335 u8 reserved_at_40[0x40]; 5336 }; 5337 5338 struct mlx5_ifc_qp_2rst_out_bits { 5339 u8 status[0x8]; 5340 u8 reserved_at_8[0x18]; 5341 5342 u8 syndrome[0x20]; 5343 5344 u8 reserved_at_40[0x40]; 5345 }; 5346 5347 struct mlx5_ifc_qp_2rst_in_bits { 5348 u8 opcode[0x10]; 5349 u8 uid[0x10]; 5350 5351 u8 reserved_at_20[0x10]; 5352 u8 op_mod[0x10]; 5353 5354 u8 reserved_at_40[0x8]; 5355 u8 qpn[0x18]; 5356 5357 u8 reserved_at_60[0x20]; 5358 }; 5359 5360 struct mlx5_ifc_qp_2err_out_bits { 5361 u8 status[0x8]; 5362 u8 reserved_at_8[0x18]; 5363 5364 u8 syndrome[0x20]; 5365 5366 u8 reserved_at_40[0x40]; 5367 }; 5368 5369 struct mlx5_ifc_qp_2err_in_bits { 5370 u8 opcode[0x10]; 5371 u8 uid[0x10]; 5372 5373 u8 reserved_at_20[0x10]; 5374 u8 op_mod[0x10]; 5375 5376 u8 reserved_at_40[0x8]; 5377 u8 qpn[0x18]; 5378 5379 u8 reserved_at_60[0x20]; 5380 }; 5381 5382 struct mlx5_ifc_page_fault_resume_out_bits { 5383 u8 status[0x8]; 5384 u8 reserved_at_8[0x18]; 5385 5386 u8 syndrome[0x20]; 5387 5388 u8 reserved_at_40[0x40]; 5389 }; 5390 5391 struct mlx5_ifc_page_fault_resume_in_bits { 5392 u8 opcode[0x10]; 5393 u8 reserved_at_10[0x10]; 5394 5395 u8 reserved_at_20[0x10]; 5396 u8 op_mod[0x10]; 5397 5398 u8 error[0x1]; 5399 u8 reserved_at_41[0x4]; 5400 u8 page_fault_type[0x3]; 5401 u8 wq_number[0x18]; 5402 5403 u8 reserved_at_60[0x8]; 5404 u8 token[0x18]; 5405 }; 5406 5407 struct mlx5_ifc_nop_out_bits { 5408 u8 status[0x8]; 5409 u8 reserved_at_8[0x18]; 5410 5411 u8 syndrome[0x20]; 5412 5413 u8 reserved_at_40[0x40]; 5414 }; 5415 5416 struct mlx5_ifc_nop_in_bits { 5417 u8 opcode[0x10]; 5418 u8 reserved_at_10[0x10]; 5419 5420 u8 reserved_at_20[0x10]; 5421 u8 op_mod[0x10]; 5422 5423 u8 reserved_at_40[0x40]; 5424 }; 5425 5426 struct mlx5_ifc_modify_vport_state_out_bits { 5427 u8 status[0x8]; 5428 u8 reserved_at_8[0x18]; 5429 5430 u8 syndrome[0x20]; 5431 5432 u8 reserved_at_40[0x40]; 5433 }; 5434 5435 struct mlx5_ifc_modify_vport_state_in_bits { 5436 u8 opcode[0x10]; 5437 u8 reserved_at_10[0x10]; 5438 5439 u8 reserved_at_20[0x10]; 5440 u8 op_mod[0x10]; 5441 5442 u8 other_vport[0x1]; 5443 u8 reserved_at_41[0xf]; 5444 u8 vport_number[0x10]; 5445 5446 u8 reserved_at_60[0x18]; 5447 u8 admin_state[0x4]; 5448 u8 reserved_at_7c[0x4]; 5449 }; 5450 5451 struct mlx5_ifc_modify_tis_out_bits { 5452 u8 status[0x8]; 5453 u8 reserved_at_8[0x18]; 5454 5455 u8 syndrome[0x20]; 5456 5457 u8 reserved_at_40[0x40]; 5458 }; 5459 5460 struct mlx5_ifc_modify_tis_bitmask_bits { 5461 u8 reserved_at_0[0x20]; 5462 5463 u8 reserved_at_20[0x1d]; 5464 u8 lag_tx_port_affinity[0x1]; 5465 u8 strict_lag_tx_port_affinity[0x1]; 5466 u8 prio[0x1]; 5467 }; 5468 5469 struct mlx5_ifc_modify_tis_in_bits { 5470 u8 opcode[0x10]; 5471 u8 uid[0x10]; 5472 5473 u8 reserved_at_20[0x10]; 5474 u8 op_mod[0x10]; 5475 5476 u8 reserved_at_40[0x8]; 5477 u8 tisn[0x18]; 5478 5479 u8 reserved_at_60[0x20]; 5480 5481 struct mlx5_ifc_modify_tis_bitmask_bits bitmask; 5482 5483 u8 reserved_at_c0[0x40]; 5484 5485 struct mlx5_ifc_tisc_bits ctx; 5486 }; 5487 5488 struct mlx5_ifc_modify_tir_bitmask_bits { 5489 u8 reserved_at_0[0x20]; 5490 5491 u8 reserved_at_20[0x1b]; 5492 u8 self_lb_en[0x1]; 5493 u8 reserved_at_3c[0x1]; 5494 u8 hash[0x1]; 5495 u8 reserved_at_3e[0x1]; 5496 u8 lro[0x1]; 5497 }; 5498 5499 struct mlx5_ifc_modify_tir_out_bits { 5500 u8 status[0x8]; 5501 u8 reserved_at_8[0x18]; 5502 5503 u8 syndrome[0x20]; 5504 5505 u8 reserved_at_40[0x40]; 5506 }; 5507 5508 struct mlx5_ifc_modify_tir_in_bits { 5509 u8 opcode[0x10]; 5510 u8 uid[0x10]; 5511 5512 u8 reserved_at_20[0x10]; 5513 u8 op_mod[0x10]; 5514 5515 u8 reserved_at_40[0x8]; 5516 u8 tirn[0x18]; 5517 5518 u8 reserved_at_60[0x20]; 5519 5520 struct mlx5_ifc_modify_tir_bitmask_bits bitmask; 5521 5522 u8 reserved_at_c0[0x40]; 5523 5524 struct mlx5_ifc_tirc_bits ctx; 5525 }; 5526 5527 struct mlx5_ifc_modify_sq_out_bits { 5528 u8 status[0x8]; 5529 u8 reserved_at_8[0x18]; 5530 5531 u8 syndrome[0x20]; 5532 5533 u8 reserved_at_40[0x40]; 5534 }; 5535 5536 struct mlx5_ifc_modify_sq_in_bits { 5537 u8 opcode[0x10]; 5538 u8 uid[0x10]; 5539 5540 u8 reserved_at_20[0x10]; 5541 u8 op_mod[0x10]; 5542 5543 u8 sq_state[0x4]; 5544 u8 reserved_at_44[0x4]; 5545 u8 sqn[0x18]; 5546 5547 u8 reserved_at_60[0x20]; 5548 5549 u8 modify_bitmask[0x40]; 5550 5551 u8 reserved_at_c0[0x40]; 5552 5553 struct mlx5_ifc_sqc_bits ctx; 5554 }; 5555 5556 struct mlx5_ifc_modify_scheduling_element_out_bits { 5557 u8 status[0x8]; 5558 u8 reserved_at_8[0x18]; 5559 5560 u8 syndrome[0x20]; 5561 5562 u8 reserved_at_40[0x1c0]; 5563 }; 5564 5565 enum { 5566 MODIFY_SCHEDULING_ELEMENT_IN_MODIFY_BITMASK_BW_SHARE = 0x1, 5567 MODIFY_SCHEDULING_ELEMENT_IN_MODIFY_BITMASK_MAX_AVERAGE_BW = 0x2, 5568 }; 5569 5570 struct mlx5_ifc_modify_scheduling_element_in_bits { 5571 u8 opcode[0x10]; 5572 u8 reserved_at_10[0x10]; 5573 5574 u8 reserved_at_20[0x10]; 5575 u8 op_mod[0x10]; 5576 5577 u8 scheduling_hierarchy[0x8]; 5578 u8 reserved_at_48[0x18]; 5579 5580 u8 scheduling_element_id[0x20]; 5581 5582 u8 reserved_at_80[0x20]; 5583 5584 u8 modify_bitmask[0x20]; 5585 5586 u8 reserved_at_c0[0x40]; 5587 5588 struct mlx5_ifc_scheduling_context_bits scheduling_context; 5589 5590 u8 reserved_at_300[0x100]; 5591 }; 5592 5593 struct mlx5_ifc_modify_rqt_out_bits { 5594 u8 status[0x8]; 5595 u8 reserved_at_8[0x18]; 5596 5597 u8 syndrome[0x20]; 5598 5599 u8 reserved_at_40[0x40]; 5600 }; 5601 5602 struct mlx5_ifc_rqt_bitmask_bits { 5603 u8 reserved_at_0[0x20]; 5604 5605 u8 reserved_at_20[0x1f]; 5606 u8 rqn_list[0x1]; 5607 }; 5608 5609 struct mlx5_ifc_modify_rqt_in_bits { 5610 u8 opcode[0x10]; 5611 u8 uid[0x10]; 5612 5613 u8 reserved_at_20[0x10]; 5614 u8 op_mod[0x10]; 5615 5616 u8 reserved_at_40[0x8]; 5617 u8 rqtn[0x18]; 5618 5619 u8 reserved_at_60[0x20]; 5620 5621 struct mlx5_ifc_rqt_bitmask_bits bitmask; 5622 5623 u8 reserved_at_c0[0x40]; 5624 5625 struct mlx5_ifc_rqtc_bits ctx; 5626 }; 5627 5628 struct mlx5_ifc_modify_rq_out_bits { 5629 u8 status[0x8]; 5630 u8 reserved_at_8[0x18]; 5631 5632 u8 syndrome[0x20]; 5633 5634 u8 reserved_at_40[0x40]; 5635 }; 5636 5637 enum { 5638 MLX5_MODIFY_RQ_IN_MODIFY_BITMASK_VSD = 1ULL << 1, 5639 MLX5_MODIFY_RQ_IN_MODIFY_BITMASK_SCATTER_FCS = 1ULL << 2, 5640 MLX5_MODIFY_RQ_IN_MODIFY_BITMASK_RQ_COUNTER_SET_ID = 1ULL << 3, 5641 }; 5642 5643 struct mlx5_ifc_modify_rq_in_bits { 5644 u8 opcode[0x10]; 5645 u8 uid[0x10]; 5646 5647 u8 reserved_at_20[0x10]; 5648 u8 op_mod[0x10]; 5649 5650 u8 rq_state[0x4]; 5651 u8 reserved_at_44[0x4]; 5652 u8 rqn[0x18]; 5653 5654 u8 reserved_at_60[0x20]; 5655 5656 u8 modify_bitmask[0x40]; 5657 5658 u8 reserved_at_c0[0x40]; 5659 5660 struct mlx5_ifc_rqc_bits ctx; 5661 }; 5662 5663 struct mlx5_ifc_modify_rmp_out_bits { 5664 u8 status[0x8]; 5665 u8 reserved_at_8[0x18]; 5666 5667 u8 syndrome[0x20]; 5668 5669 u8 reserved_at_40[0x40]; 5670 }; 5671 5672 struct mlx5_ifc_rmp_bitmask_bits { 5673 u8 reserved_at_0[0x20]; 5674 5675 u8 reserved_at_20[0x1f]; 5676 u8 lwm[0x1]; 5677 }; 5678 5679 struct mlx5_ifc_modify_rmp_in_bits { 5680 u8 opcode[0x10]; 5681 u8 uid[0x10]; 5682 5683 u8 reserved_at_20[0x10]; 5684 u8 op_mod[0x10]; 5685 5686 u8 rmp_state[0x4]; 5687 u8 reserved_at_44[0x4]; 5688 u8 rmpn[0x18]; 5689 5690 u8 reserved_at_60[0x20]; 5691 5692 struct mlx5_ifc_rmp_bitmask_bits bitmask; 5693 5694 u8 reserved_at_c0[0x40]; 5695 5696 struct mlx5_ifc_rmpc_bits ctx; 5697 }; 5698 5699 struct mlx5_ifc_modify_nic_vport_context_out_bits { 5700 u8 status[0x8]; 5701 u8 reserved_at_8[0x18]; 5702 5703 u8 syndrome[0x20]; 5704 5705 u8 reserved_at_40[0x40]; 5706 }; 5707 5708 struct mlx5_ifc_modify_nic_vport_field_select_bits { 5709 u8 reserved_at_0[0x12]; 5710 u8 affiliation[0x1]; 5711 u8 reserved_at_13[0x1]; 5712 u8 disable_uc_local_lb[0x1]; 5713 u8 disable_mc_local_lb[0x1]; 5714 u8 node_guid[0x1]; 5715 u8 port_guid[0x1]; 5716 u8 min_inline[0x1]; 5717 u8 mtu[0x1]; 5718 u8 change_event[0x1]; 5719 u8 promisc[0x1]; 5720 u8 permanent_address[0x1]; 5721 u8 addresses_list[0x1]; 5722 u8 roce_en[0x1]; 5723 u8 reserved_at_1f[0x1]; 5724 }; 5725 5726 struct mlx5_ifc_modify_nic_vport_context_in_bits { 5727 u8 opcode[0x10]; 5728 u8 reserved_at_10[0x10]; 5729 5730 u8 reserved_at_20[0x10]; 5731 u8 op_mod[0x10]; 5732 5733 u8 other_vport[0x1]; 5734 u8 reserved_at_41[0xf]; 5735 u8 vport_number[0x10]; 5736 5737 struct mlx5_ifc_modify_nic_vport_field_select_bits field_select; 5738 5739 u8 reserved_at_80[0x780]; 5740 5741 struct mlx5_ifc_nic_vport_context_bits nic_vport_context; 5742 }; 5743 5744 struct mlx5_ifc_modify_hca_vport_context_out_bits { 5745 u8 status[0x8]; 5746 u8 reserved_at_8[0x18]; 5747 5748 u8 syndrome[0x20]; 5749 5750 u8 reserved_at_40[0x40]; 5751 }; 5752 5753 struct mlx5_ifc_modify_hca_vport_context_in_bits { 5754 u8 opcode[0x10]; 5755 u8 reserved_at_10[0x10]; 5756 5757 u8 reserved_at_20[0x10]; 5758 u8 op_mod[0x10]; 5759 5760 u8 other_vport[0x1]; 5761 u8 reserved_at_41[0xb]; 5762 u8 port_num[0x4]; 5763 u8 vport_number[0x10]; 5764 5765 u8 reserved_at_60[0x20]; 5766 5767 struct mlx5_ifc_hca_vport_context_bits hca_vport_context; 5768 }; 5769 5770 struct mlx5_ifc_modify_cq_out_bits { 5771 u8 status[0x8]; 5772 u8 reserved_at_8[0x18]; 5773 5774 u8 syndrome[0x20]; 5775 5776 u8 reserved_at_40[0x40]; 5777 }; 5778 5779 enum { 5780 MLX5_MODIFY_CQ_IN_OP_MOD_MODIFY_CQ = 0x0, 5781 MLX5_MODIFY_CQ_IN_OP_MOD_RESIZE_CQ = 0x1, 5782 }; 5783 5784 struct mlx5_ifc_modify_cq_in_bits { 5785 u8 opcode[0x10]; 5786 u8 uid[0x10]; 5787 5788 u8 reserved_at_20[0x10]; 5789 u8 op_mod[0x10]; 5790 5791 u8 reserved_at_40[0x8]; 5792 u8 cqn[0x18]; 5793 5794 union mlx5_ifc_modify_field_select_resize_field_select_auto_bits modify_field_select_resize_field_select; 5795 5796 struct mlx5_ifc_cqc_bits cq_context; 5797 5798 u8 reserved_at_280[0x40]; 5799 5800 u8 cq_umem_valid[0x1]; 5801 u8 reserved_at_2c1[0x5bf]; 5802 5803 u8 pas[0][0x40]; 5804 }; 5805 5806 struct mlx5_ifc_modify_cong_status_out_bits { 5807 u8 status[0x8]; 5808 u8 reserved_at_8[0x18]; 5809 5810 u8 syndrome[0x20]; 5811 5812 u8 reserved_at_40[0x40]; 5813 }; 5814 5815 struct mlx5_ifc_modify_cong_status_in_bits { 5816 u8 opcode[0x10]; 5817 u8 reserved_at_10[0x10]; 5818 5819 u8 reserved_at_20[0x10]; 5820 u8 op_mod[0x10]; 5821 5822 u8 reserved_at_40[0x18]; 5823 u8 priority[0x4]; 5824 u8 cong_protocol[0x4]; 5825 5826 u8 enable[0x1]; 5827 u8 tag_enable[0x1]; 5828 u8 reserved_at_62[0x1e]; 5829 }; 5830 5831 struct mlx5_ifc_modify_cong_params_out_bits { 5832 u8 status[0x8]; 5833 u8 reserved_at_8[0x18]; 5834 5835 u8 syndrome[0x20]; 5836 5837 u8 reserved_at_40[0x40]; 5838 }; 5839 5840 struct mlx5_ifc_modify_cong_params_in_bits { 5841 u8 opcode[0x10]; 5842 u8 reserved_at_10[0x10]; 5843 5844 u8 reserved_at_20[0x10]; 5845 u8 op_mod[0x10]; 5846 5847 u8 reserved_at_40[0x1c]; 5848 u8 cong_protocol[0x4]; 5849 5850 union mlx5_ifc_field_select_802_1_r_roce_auto_bits field_select; 5851 5852 u8 reserved_at_80[0x80]; 5853 5854 union mlx5_ifc_cong_control_roce_ecn_auto_bits congestion_parameters; 5855 }; 5856 5857 struct mlx5_ifc_manage_pages_out_bits { 5858 u8 status[0x8]; 5859 u8 reserved_at_8[0x18]; 5860 5861 u8 syndrome[0x20]; 5862 5863 u8 output_num_entries[0x20]; 5864 5865 u8 reserved_at_60[0x20]; 5866 5867 u8 pas[0][0x40]; 5868 }; 5869 5870 enum { 5871 MLX5_MANAGE_PAGES_IN_OP_MOD_ALLOCATION_FAIL = 0x0, 5872 MLX5_MANAGE_PAGES_IN_OP_MOD_ALLOCATION_SUCCESS = 0x1, 5873 MLX5_MANAGE_PAGES_IN_OP_MOD_HCA_RETURN_PAGES = 0x2, 5874 }; 5875 5876 struct mlx5_ifc_manage_pages_in_bits { 5877 u8 opcode[0x10]; 5878 u8 reserved_at_10[0x10]; 5879 5880 u8 reserved_at_20[0x10]; 5881 u8 op_mod[0x10]; 5882 5883 u8 reserved_at_40[0x10]; 5884 u8 function_id[0x10]; 5885 5886 u8 input_num_entries[0x20]; 5887 5888 u8 pas[0][0x40]; 5889 }; 5890 5891 struct mlx5_ifc_mad_ifc_out_bits { 5892 u8 status[0x8]; 5893 u8 reserved_at_8[0x18]; 5894 5895 u8 syndrome[0x20]; 5896 5897 u8 reserved_at_40[0x40]; 5898 5899 u8 response_mad_packet[256][0x8]; 5900 }; 5901 5902 struct mlx5_ifc_mad_ifc_in_bits { 5903 u8 opcode[0x10]; 5904 u8 reserved_at_10[0x10]; 5905 5906 u8 reserved_at_20[0x10]; 5907 u8 op_mod[0x10]; 5908 5909 u8 remote_lid[0x10]; 5910 u8 reserved_at_50[0x8]; 5911 u8 port[0x8]; 5912 5913 u8 reserved_at_60[0x20]; 5914 5915 u8 mad[256][0x8]; 5916 }; 5917 5918 struct mlx5_ifc_init_hca_out_bits { 5919 u8 status[0x8]; 5920 u8 reserved_at_8[0x18]; 5921 5922 u8 syndrome[0x20]; 5923 5924 u8 reserved_at_40[0x40]; 5925 }; 5926 5927 struct mlx5_ifc_init_hca_in_bits { 5928 u8 opcode[0x10]; 5929 u8 reserved_at_10[0x10]; 5930 5931 u8 reserved_at_20[0x10]; 5932 u8 op_mod[0x10]; 5933 5934 u8 reserved_at_40[0x40]; 5935 u8 sw_owner_id[4][0x20]; 5936 }; 5937 5938 struct mlx5_ifc_init2rtr_qp_out_bits { 5939 u8 status[0x8]; 5940 u8 reserved_at_8[0x18]; 5941 5942 u8 syndrome[0x20]; 5943 5944 u8 reserved_at_40[0x40]; 5945 }; 5946 5947 struct mlx5_ifc_init2rtr_qp_in_bits { 5948 u8 opcode[0x10]; 5949 u8 uid[0x10]; 5950 5951 u8 reserved_at_20[0x10]; 5952 u8 op_mod[0x10]; 5953 5954 u8 reserved_at_40[0x8]; 5955 u8 qpn[0x18]; 5956 5957 u8 reserved_at_60[0x20]; 5958 5959 u8 opt_param_mask[0x20]; 5960 5961 u8 reserved_at_a0[0x20]; 5962 5963 struct mlx5_ifc_qpc_bits qpc; 5964 5965 u8 reserved_at_800[0x80]; 5966 }; 5967 5968 struct mlx5_ifc_init2init_qp_out_bits { 5969 u8 status[0x8]; 5970 u8 reserved_at_8[0x18]; 5971 5972 u8 syndrome[0x20]; 5973 5974 u8 reserved_at_40[0x40]; 5975 }; 5976 5977 struct mlx5_ifc_init2init_qp_in_bits { 5978 u8 opcode[0x10]; 5979 u8 uid[0x10]; 5980 5981 u8 reserved_at_20[0x10]; 5982 u8 op_mod[0x10]; 5983 5984 u8 reserved_at_40[0x8]; 5985 u8 qpn[0x18]; 5986 5987 u8 reserved_at_60[0x20]; 5988 5989 u8 opt_param_mask[0x20]; 5990 5991 u8 reserved_at_a0[0x20]; 5992 5993 struct mlx5_ifc_qpc_bits qpc; 5994 5995 u8 reserved_at_800[0x80]; 5996 }; 5997 5998 struct mlx5_ifc_get_dropped_packet_log_out_bits { 5999 u8 status[0x8]; 6000 u8 reserved_at_8[0x18]; 6001 6002 u8 syndrome[0x20]; 6003 6004 u8 reserved_at_40[0x40]; 6005 6006 u8 packet_headers_log[128][0x8]; 6007 6008 u8 packet_syndrome[64][0x8]; 6009 }; 6010 6011 struct mlx5_ifc_get_dropped_packet_log_in_bits { 6012 u8 opcode[0x10]; 6013 u8 reserved_at_10[0x10]; 6014 6015 u8 reserved_at_20[0x10]; 6016 u8 op_mod[0x10]; 6017 6018 u8 reserved_at_40[0x40]; 6019 }; 6020 6021 struct mlx5_ifc_gen_eqe_in_bits { 6022 u8 opcode[0x10]; 6023 u8 reserved_at_10[0x10]; 6024 6025 u8 reserved_at_20[0x10]; 6026 u8 op_mod[0x10]; 6027 6028 u8 reserved_at_40[0x18]; 6029 u8 eq_number[0x8]; 6030 6031 u8 reserved_at_60[0x20]; 6032 6033 u8 eqe[64][0x8]; 6034 }; 6035 6036 struct mlx5_ifc_gen_eq_out_bits { 6037 u8 status[0x8]; 6038 u8 reserved_at_8[0x18]; 6039 6040 u8 syndrome[0x20]; 6041 6042 u8 reserved_at_40[0x40]; 6043 }; 6044 6045 struct mlx5_ifc_enable_hca_out_bits { 6046 u8 status[0x8]; 6047 u8 reserved_at_8[0x18]; 6048 6049 u8 syndrome[0x20]; 6050 6051 u8 reserved_at_40[0x20]; 6052 }; 6053 6054 struct mlx5_ifc_enable_hca_in_bits { 6055 u8 opcode[0x10]; 6056 u8 reserved_at_10[0x10]; 6057 6058 u8 reserved_at_20[0x10]; 6059 u8 op_mod[0x10]; 6060 6061 u8 reserved_at_40[0x10]; 6062 u8 function_id[0x10]; 6063 6064 u8 reserved_at_60[0x20]; 6065 }; 6066 6067 struct mlx5_ifc_drain_dct_out_bits { 6068 u8 status[0x8]; 6069 u8 reserved_at_8[0x18]; 6070 6071 u8 syndrome[0x20]; 6072 6073 u8 reserved_at_40[0x40]; 6074 }; 6075 6076 struct mlx5_ifc_drain_dct_in_bits { 6077 u8 opcode[0x10]; 6078 u8 uid[0x10]; 6079 6080 u8 reserved_at_20[0x10]; 6081 u8 op_mod[0x10]; 6082 6083 u8 reserved_at_40[0x8]; 6084 u8 dctn[0x18]; 6085 6086 u8 reserved_at_60[0x20]; 6087 }; 6088 6089 struct mlx5_ifc_disable_hca_out_bits { 6090 u8 status[0x8]; 6091 u8 reserved_at_8[0x18]; 6092 6093 u8 syndrome[0x20]; 6094 6095 u8 reserved_at_40[0x20]; 6096 }; 6097 6098 struct mlx5_ifc_disable_hca_in_bits { 6099 u8 opcode[0x10]; 6100 u8 reserved_at_10[0x10]; 6101 6102 u8 reserved_at_20[0x10]; 6103 u8 op_mod[0x10]; 6104 6105 u8 reserved_at_40[0x10]; 6106 u8 function_id[0x10]; 6107 6108 u8 reserved_at_60[0x20]; 6109 }; 6110 6111 struct mlx5_ifc_detach_from_mcg_out_bits { 6112 u8 status[0x8]; 6113 u8 reserved_at_8[0x18]; 6114 6115 u8 syndrome[0x20]; 6116 6117 u8 reserved_at_40[0x40]; 6118 }; 6119 6120 struct mlx5_ifc_detach_from_mcg_in_bits { 6121 u8 opcode[0x10]; 6122 u8 uid[0x10]; 6123 6124 u8 reserved_at_20[0x10]; 6125 u8 op_mod[0x10]; 6126 6127 u8 reserved_at_40[0x8]; 6128 u8 qpn[0x18]; 6129 6130 u8 reserved_at_60[0x20]; 6131 6132 u8 multicast_gid[16][0x8]; 6133 }; 6134 6135 struct mlx5_ifc_destroy_xrq_out_bits { 6136 u8 status[0x8]; 6137 u8 reserved_at_8[0x18]; 6138 6139 u8 syndrome[0x20]; 6140 6141 u8 reserved_at_40[0x40]; 6142 }; 6143 6144 struct mlx5_ifc_destroy_xrq_in_bits { 6145 u8 opcode[0x10]; 6146 u8 uid[0x10]; 6147 6148 u8 reserved_at_20[0x10]; 6149 u8 op_mod[0x10]; 6150 6151 u8 reserved_at_40[0x8]; 6152 u8 xrqn[0x18]; 6153 6154 u8 reserved_at_60[0x20]; 6155 }; 6156 6157 struct mlx5_ifc_destroy_xrc_srq_out_bits { 6158 u8 status[0x8]; 6159 u8 reserved_at_8[0x18]; 6160 6161 u8 syndrome[0x20]; 6162 6163 u8 reserved_at_40[0x40]; 6164 }; 6165 6166 struct mlx5_ifc_destroy_xrc_srq_in_bits { 6167 u8 opcode[0x10]; 6168 u8 uid[0x10]; 6169 6170 u8 reserved_at_20[0x10]; 6171 u8 op_mod[0x10]; 6172 6173 u8 reserved_at_40[0x8]; 6174 u8 xrc_srqn[0x18]; 6175 6176 u8 reserved_at_60[0x20]; 6177 }; 6178 6179 struct mlx5_ifc_destroy_tis_out_bits { 6180 u8 status[0x8]; 6181 u8 reserved_at_8[0x18]; 6182 6183 u8 syndrome[0x20]; 6184 6185 u8 reserved_at_40[0x40]; 6186 }; 6187 6188 struct mlx5_ifc_destroy_tis_in_bits { 6189 u8 opcode[0x10]; 6190 u8 uid[0x10]; 6191 6192 u8 reserved_at_20[0x10]; 6193 u8 op_mod[0x10]; 6194 6195 u8 reserved_at_40[0x8]; 6196 u8 tisn[0x18]; 6197 6198 u8 reserved_at_60[0x20]; 6199 }; 6200 6201 struct mlx5_ifc_destroy_tir_out_bits { 6202 u8 status[0x8]; 6203 u8 reserved_at_8[0x18]; 6204 6205 u8 syndrome[0x20]; 6206 6207 u8 reserved_at_40[0x40]; 6208 }; 6209 6210 struct mlx5_ifc_destroy_tir_in_bits { 6211 u8 opcode[0x10]; 6212 u8 uid[0x10]; 6213 6214 u8 reserved_at_20[0x10]; 6215 u8 op_mod[0x10]; 6216 6217 u8 reserved_at_40[0x8]; 6218 u8 tirn[0x18]; 6219 6220 u8 reserved_at_60[0x20]; 6221 }; 6222 6223 struct mlx5_ifc_destroy_srq_out_bits { 6224 u8 status[0x8]; 6225 u8 reserved_at_8[0x18]; 6226 6227 u8 syndrome[0x20]; 6228 6229 u8 reserved_at_40[0x40]; 6230 }; 6231 6232 struct mlx5_ifc_destroy_srq_in_bits { 6233 u8 opcode[0x10]; 6234 u8 uid[0x10]; 6235 6236 u8 reserved_at_20[0x10]; 6237 u8 op_mod[0x10]; 6238 6239 u8 reserved_at_40[0x8]; 6240 u8 srqn[0x18]; 6241 6242 u8 reserved_at_60[0x20]; 6243 }; 6244 6245 struct mlx5_ifc_destroy_sq_out_bits { 6246 u8 status[0x8]; 6247 u8 reserved_at_8[0x18]; 6248 6249 u8 syndrome[0x20]; 6250 6251 u8 reserved_at_40[0x40]; 6252 }; 6253 6254 struct mlx5_ifc_destroy_sq_in_bits { 6255 u8 opcode[0x10]; 6256 u8 uid[0x10]; 6257 6258 u8 reserved_at_20[0x10]; 6259 u8 op_mod[0x10]; 6260 6261 u8 reserved_at_40[0x8]; 6262 u8 sqn[0x18]; 6263 6264 u8 reserved_at_60[0x20]; 6265 }; 6266 6267 struct mlx5_ifc_destroy_scheduling_element_out_bits { 6268 u8 status[0x8]; 6269 u8 reserved_at_8[0x18]; 6270 6271 u8 syndrome[0x20]; 6272 6273 u8 reserved_at_40[0x1c0]; 6274 }; 6275 6276 struct mlx5_ifc_destroy_scheduling_element_in_bits { 6277 u8 opcode[0x10]; 6278 u8 reserved_at_10[0x10]; 6279 6280 u8 reserved_at_20[0x10]; 6281 u8 op_mod[0x10]; 6282 6283 u8 scheduling_hierarchy[0x8]; 6284 u8 reserved_at_48[0x18]; 6285 6286 u8 scheduling_element_id[0x20]; 6287 6288 u8 reserved_at_80[0x180]; 6289 }; 6290 6291 struct mlx5_ifc_destroy_rqt_out_bits { 6292 u8 status[0x8]; 6293 u8 reserved_at_8[0x18]; 6294 6295 u8 syndrome[0x20]; 6296 6297 u8 reserved_at_40[0x40]; 6298 }; 6299 6300 struct mlx5_ifc_destroy_rqt_in_bits { 6301 u8 opcode[0x10]; 6302 u8 uid[0x10]; 6303 6304 u8 reserved_at_20[0x10]; 6305 u8 op_mod[0x10]; 6306 6307 u8 reserved_at_40[0x8]; 6308 u8 rqtn[0x18]; 6309 6310 u8 reserved_at_60[0x20]; 6311 }; 6312 6313 struct mlx5_ifc_destroy_rq_out_bits { 6314 u8 status[0x8]; 6315 u8 reserved_at_8[0x18]; 6316 6317 u8 syndrome[0x20]; 6318 6319 u8 reserved_at_40[0x40]; 6320 }; 6321 6322 struct mlx5_ifc_destroy_rq_in_bits { 6323 u8 opcode[0x10]; 6324 u8 uid[0x10]; 6325 6326 u8 reserved_at_20[0x10]; 6327 u8 op_mod[0x10]; 6328 6329 u8 reserved_at_40[0x8]; 6330 u8 rqn[0x18]; 6331 6332 u8 reserved_at_60[0x20]; 6333 }; 6334 6335 struct mlx5_ifc_set_delay_drop_params_in_bits { 6336 u8 opcode[0x10]; 6337 u8 reserved_at_10[0x10]; 6338 6339 u8 reserved_at_20[0x10]; 6340 u8 op_mod[0x10]; 6341 6342 u8 reserved_at_40[0x20]; 6343 6344 u8 reserved_at_60[0x10]; 6345 u8 delay_drop_timeout[0x10]; 6346 }; 6347 6348 struct mlx5_ifc_set_delay_drop_params_out_bits { 6349 u8 status[0x8]; 6350 u8 reserved_at_8[0x18]; 6351 6352 u8 syndrome[0x20]; 6353 6354 u8 reserved_at_40[0x40]; 6355 }; 6356 6357 struct mlx5_ifc_destroy_rmp_out_bits { 6358 u8 status[0x8]; 6359 u8 reserved_at_8[0x18]; 6360 6361 u8 syndrome[0x20]; 6362 6363 u8 reserved_at_40[0x40]; 6364 }; 6365 6366 struct mlx5_ifc_destroy_rmp_in_bits { 6367 u8 opcode[0x10]; 6368 u8 uid[0x10]; 6369 6370 u8 reserved_at_20[0x10]; 6371 u8 op_mod[0x10]; 6372 6373 u8 reserved_at_40[0x8]; 6374 u8 rmpn[0x18]; 6375 6376 u8 reserved_at_60[0x20]; 6377 }; 6378 6379 struct mlx5_ifc_destroy_qp_out_bits { 6380 u8 status[0x8]; 6381 u8 reserved_at_8[0x18]; 6382 6383 u8 syndrome[0x20]; 6384 6385 u8 reserved_at_40[0x40]; 6386 }; 6387 6388 struct mlx5_ifc_destroy_qp_in_bits { 6389 u8 opcode[0x10]; 6390 u8 uid[0x10]; 6391 6392 u8 reserved_at_20[0x10]; 6393 u8 op_mod[0x10]; 6394 6395 u8 reserved_at_40[0x8]; 6396 u8 qpn[0x18]; 6397 6398 u8 reserved_at_60[0x20]; 6399 }; 6400 6401 struct mlx5_ifc_destroy_psv_out_bits { 6402 u8 status[0x8]; 6403 u8 reserved_at_8[0x18]; 6404 6405 u8 syndrome[0x20]; 6406 6407 u8 reserved_at_40[0x40]; 6408 }; 6409 6410 struct mlx5_ifc_destroy_psv_in_bits { 6411 u8 opcode[0x10]; 6412 u8 reserved_at_10[0x10]; 6413 6414 u8 reserved_at_20[0x10]; 6415 u8 op_mod[0x10]; 6416 6417 u8 reserved_at_40[0x8]; 6418 u8 psvn[0x18]; 6419 6420 u8 reserved_at_60[0x20]; 6421 }; 6422 6423 struct mlx5_ifc_destroy_mkey_out_bits { 6424 u8 status[0x8]; 6425 u8 reserved_at_8[0x18]; 6426 6427 u8 syndrome[0x20]; 6428 6429 u8 reserved_at_40[0x40]; 6430 }; 6431 6432 struct mlx5_ifc_destroy_mkey_in_bits { 6433 u8 opcode[0x10]; 6434 u8 reserved_at_10[0x10]; 6435 6436 u8 reserved_at_20[0x10]; 6437 u8 op_mod[0x10]; 6438 6439 u8 reserved_at_40[0x8]; 6440 u8 mkey_index[0x18]; 6441 6442 u8 reserved_at_60[0x20]; 6443 }; 6444 6445 struct mlx5_ifc_destroy_flow_table_out_bits { 6446 u8 status[0x8]; 6447 u8 reserved_at_8[0x18]; 6448 6449 u8 syndrome[0x20]; 6450 6451 u8 reserved_at_40[0x40]; 6452 }; 6453 6454 struct mlx5_ifc_destroy_flow_table_in_bits { 6455 u8 opcode[0x10]; 6456 u8 reserved_at_10[0x10]; 6457 6458 u8 reserved_at_20[0x10]; 6459 u8 op_mod[0x10]; 6460 6461 u8 other_vport[0x1]; 6462 u8 reserved_at_41[0xf]; 6463 u8 vport_number[0x10]; 6464 6465 u8 reserved_at_60[0x20]; 6466 6467 u8 table_type[0x8]; 6468 u8 reserved_at_88[0x18]; 6469 6470 u8 reserved_at_a0[0x8]; 6471 u8 table_id[0x18]; 6472 6473 u8 reserved_at_c0[0x140]; 6474 }; 6475 6476 struct mlx5_ifc_destroy_flow_group_out_bits { 6477 u8 status[0x8]; 6478 u8 reserved_at_8[0x18]; 6479 6480 u8 syndrome[0x20]; 6481 6482 u8 reserved_at_40[0x40]; 6483 }; 6484 6485 struct mlx5_ifc_destroy_flow_group_in_bits { 6486 u8 opcode[0x10]; 6487 u8 reserved_at_10[0x10]; 6488 6489 u8 reserved_at_20[0x10]; 6490 u8 op_mod[0x10]; 6491 6492 u8 other_vport[0x1]; 6493 u8 reserved_at_41[0xf]; 6494 u8 vport_number[0x10]; 6495 6496 u8 reserved_at_60[0x20]; 6497 6498 u8 table_type[0x8]; 6499 u8 reserved_at_88[0x18]; 6500 6501 u8 reserved_at_a0[0x8]; 6502 u8 table_id[0x18]; 6503 6504 u8 group_id[0x20]; 6505 6506 u8 reserved_at_e0[0x120]; 6507 }; 6508 6509 struct mlx5_ifc_destroy_eq_out_bits { 6510 u8 status[0x8]; 6511 u8 reserved_at_8[0x18]; 6512 6513 u8 syndrome[0x20]; 6514 6515 u8 reserved_at_40[0x40]; 6516 }; 6517 6518 struct mlx5_ifc_destroy_eq_in_bits { 6519 u8 opcode[0x10]; 6520 u8 reserved_at_10[0x10]; 6521 6522 u8 reserved_at_20[0x10]; 6523 u8 op_mod[0x10]; 6524 6525 u8 reserved_at_40[0x18]; 6526 u8 eq_number[0x8]; 6527 6528 u8 reserved_at_60[0x20]; 6529 }; 6530 6531 struct mlx5_ifc_destroy_dct_out_bits { 6532 u8 status[0x8]; 6533 u8 reserved_at_8[0x18]; 6534 6535 u8 syndrome[0x20]; 6536 6537 u8 reserved_at_40[0x40]; 6538 }; 6539 6540 struct mlx5_ifc_destroy_dct_in_bits { 6541 u8 opcode[0x10]; 6542 u8 uid[0x10]; 6543 6544 u8 reserved_at_20[0x10]; 6545 u8 op_mod[0x10]; 6546 6547 u8 reserved_at_40[0x8]; 6548 u8 dctn[0x18]; 6549 6550 u8 reserved_at_60[0x20]; 6551 }; 6552 6553 struct mlx5_ifc_destroy_cq_out_bits { 6554 u8 status[0x8]; 6555 u8 reserved_at_8[0x18]; 6556 6557 u8 syndrome[0x20]; 6558 6559 u8 reserved_at_40[0x40]; 6560 }; 6561 6562 struct mlx5_ifc_destroy_cq_in_bits { 6563 u8 opcode[0x10]; 6564 u8 uid[0x10]; 6565 6566 u8 reserved_at_20[0x10]; 6567 u8 op_mod[0x10]; 6568 6569 u8 reserved_at_40[0x8]; 6570 u8 cqn[0x18]; 6571 6572 u8 reserved_at_60[0x20]; 6573 }; 6574 6575 struct mlx5_ifc_delete_vxlan_udp_dport_out_bits { 6576 u8 status[0x8]; 6577 u8 reserved_at_8[0x18]; 6578 6579 u8 syndrome[0x20]; 6580 6581 u8 reserved_at_40[0x40]; 6582 }; 6583 6584 struct mlx5_ifc_delete_vxlan_udp_dport_in_bits { 6585 u8 opcode[0x10]; 6586 u8 reserved_at_10[0x10]; 6587 6588 u8 reserved_at_20[0x10]; 6589 u8 op_mod[0x10]; 6590 6591 u8 reserved_at_40[0x20]; 6592 6593 u8 reserved_at_60[0x10]; 6594 u8 vxlan_udp_port[0x10]; 6595 }; 6596 6597 struct mlx5_ifc_delete_l2_table_entry_out_bits { 6598 u8 status[0x8]; 6599 u8 reserved_at_8[0x18]; 6600 6601 u8 syndrome[0x20]; 6602 6603 u8 reserved_at_40[0x40]; 6604 }; 6605 6606 struct mlx5_ifc_delete_l2_table_entry_in_bits { 6607 u8 opcode[0x10]; 6608 u8 reserved_at_10[0x10]; 6609 6610 u8 reserved_at_20[0x10]; 6611 u8 op_mod[0x10]; 6612 6613 u8 reserved_at_40[0x60]; 6614 6615 u8 reserved_at_a0[0x8]; 6616 u8 table_index[0x18]; 6617 6618 u8 reserved_at_c0[0x140]; 6619 }; 6620 6621 struct mlx5_ifc_delete_fte_out_bits { 6622 u8 status[0x8]; 6623 u8 reserved_at_8[0x18]; 6624 6625 u8 syndrome[0x20]; 6626 6627 u8 reserved_at_40[0x40]; 6628 }; 6629 6630 struct mlx5_ifc_delete_fte_in_bits { 6631 u8 opcode[0x10]; 6632 u8 reserved_at_10[0x10]; 6633 6634 u8 reserved_at_20[0x10]; 6635 u8 op_mod[0x10]; 6636 6637 u8 other_vport[0x1]; 6638 u8 reserved_at_41[0xf]; 6639 u8 vport_number[0x10]; 6640 6641 u8 reserved_at_60[0x20]; 6642 6643 u8 table_type[0x8]; 6644 u8 reserved_at_88[0x18]; 6645 6646 u8 reserved_at_a0[0x8]; 6647 u8 table_id[0x18]; 6648 6649 u8 reserved_at_c0[0x40]; 6650 6651 u8 flow_index[0x20]; 6652 6653 u8 reserved_at_120[0xe0]; 6654 }; 6655 6656 struct mlx5_ifc_dealloc_xrcd_out_bits { 6657 u8 status[0x8]; 6658 u8 reserved_at_8[0x18]; 6659 6660 u8 syndrome[0x20]; 6661 6662 u8 reserved_at_40[0x40]; 6663 }; 6664 6665 struct mlx5_ifc_dealloc_xrcd_in_bits { 6666 u8 opcode[0x10]; 6667 u8 uid[0x10]; 6668 6669 u8 reserved_at_20[0x10]; 6670 u8 op_mod[0x10]; 6671 6672 u8 reserved_at_40[0x8]; 6673 u8 xrcd[0x18]; 6674 6675 u8 reserved_at_60[0x20]; 6676 }; 6677 6678 struct mlx5_ifc_dealloc_uar_out_bits { 6679 u8 status[0x8]; 6680 u8 reserved_at_8[0x18]; 6681 6682 u8 syndrome[0x20]; 6683 6684 u8 reserved_at_40[0x40]; 6685 }; 6686 6687 struct mlx5_ifc_dealloc_uar_in_bits { 6688 u8 opcode[0x10]; 6689 u8 reserved_at_10[0x10]; 6690 6691 u8 reserved_at_20[0x10]; 6692 u8 op_mod[0x10]; 6693 6694 u8 reserved_at_40[0x8]; 6695 u8 uar[0x18]; 6696 6697 u8 reserved_at_60[0x20]; 6698 }; 6699 6700 struct mlx5_ifc_dealloc_transport_domain_out_bits { 6701 u8 status[0x8]; 6702 u8 reserved_at_8[0x18]; 6703 6704 u8 syndrome[0x20]; 6705 6706 u8 reserved_at_40[0x40]; 6707 }; 6708 6709 struct mlx5_ifc_dealloc_transport_domain_in_bits { 6710 u8 opcode[0x10]; 6711 u8 uid[0x10]; 6712 6713 u8 reserved_at_20[0x10]; 6714 u8 op_mod[0x10]; 6715 6716 u8 reserved_at_40[0x8]; 6717 u8 transport_domain[0x18]; 6718 6719 u8 reserved_at_60[0x20]; 6720 }; 6721 6722 struct mlx5_ifc_dealloc_q_counter_out_bits { 6723 u8 status[0x8]; 6724 u8 reserved_at_8[0x18]; 6725 6726 u8 syndrome[0x20]; 6727 6728 u8 reserved_at_40[0x40]; 6729 }; 6730 6731 struct mlx5_ifc_dealloc_q_counter_in_bits { 6732 u8 opcode[0x10]; 6733 u8 reserved_at_10[0x10]; 6734 6735 u8 reserved_at_20[0x10]; 6736 u8 op_mod[0x10]; 6737 6738 u8 reserved_at_40[0x18]; 6739 u8 counter_set_id[0x8]; 6740 6741 u8 reserved_at_60[0x20]; 6742 }; 6743 6744 struct mlx5_ifc_dealloc_pd_out_bits { 6745 u8 status[0x8]; 6746 u8 reserved_at_8[0x18]; 6747 6748 u8 syndrome[0x20]; 6749 6750 u8 reserved_at_40[0x40]; 6751 }; 6752 6753 struct mlx5_ifc_dealloc_pd_in_bits { 6754 u8 opcode[0x10]; 6755 u8 uid[0x10]; 6756 6757 u8 reserved_at_20[0x10]; 6758 u8 op_mod[0x10]; 6759 6760 u8 reserved_at_40[0x8]; 6761 u8 pd[0x18]; 6762 6763 u8 reserved_at_60[0x20]; 6764 }; 6765 6766 struct mlx5_ifc_dealloc_flow_counter_out_bits { 6767 u8 status[0x8]; 6768 u8 reserved_at_8[0x18]; 6769 6770 u8 syndrome[0x20]; 6771 6772 u8 reserved_at_40[0x40]; 6773 }; 6774 6775 struct mlx5_ifc_dealloc_flow_counter_in_bits { 6776 u8 opcode[0x10]; 6777 u8 reserved_at_10[0x10]; 6778 6779 u8 reserved_at_20[0x10]; 6780 u8 op_mod[0x10]; 6781 6782 u8 flow_counter_id[0x20]; 6783 6784 u8 reserved_at_60[0x20]; 6785 }; 6786 6787 struct mlx5_ifc_create_xrq_out_bits { 6788 u8 status[0x8]; 6789 u8 reserved_at_8[0x18]; 6790 6791 u8 syndrome[0x20]; 6792 6793 u8 reserved_at_40[0x8]; 6794 u8 xrqn[0x18]; 6795 6796 u8 reserved_at_60[0x20]; 6797 }; 6798 6799 struct mlx5_ifc_create_xrq_in_bits { 6800 u8 opcode[0x10]; 6801 u8 uid[0x10]; 6802 6803 u8 reserved_at_20[0x10]; 6804 u8 op_mod[0x10]; 6805 6806 u8 reserved_at_40[0x40]; 6807 6808 struct mlx5_ifc_xrqc_bits xrq_context; 6809 }; 6810 6811 struct mlx5_ifc_create_xrc_srq_out_bits { 6812 u8 status[0x8]; 6813 u8 reserved_at_8[0x18]; 6814 6815 u8 syndrome[0x20]; 6816 6817 u8 reserved_at_40[0x8]; 6818 u8 xrc_srqn[0x18]; 6819 6820 u8 reserved_at_60[0x20]; 6821 }; 6822 6823 struct mlx5_ifc_create_xrc_srq_in_bits { 6824 u8 opcode[0x10]; 6825 u8 uid[0x10]; 6826 6827 u8 reserved_at_20[0x10]; 6828 u8 op_mod[0x10]; 6829 6830 u8 reserved_at_40[0x40]; 6831 6832 struct mlx5_ifc_xrc_srqc_bits xrc_srq_context_entry; 6833 6834 u8 reserved_at_280[0x60]; 6835 6836 u8 xrc_srq_umem_valid[0x1]; 6837 u8 reserved_at_2e1[0x1f]; 6838 6839 u8 reserved_at_300[0x580]; 6840 6841 u8 pas[0][0x40]; 6842 }; 6843 6844 struct mlx5_ifc_create_tis_out_bits { 6845 u8 status[0x8]; 6846 u8 reserved_at_8[0x18]; 6847 6848 u8 syndrome[0x20]; 6849 6850 u8 reserved_at_40[0x8]; 6851 u8 tisn[0x18]; 6852 6853 u8 reserved_at_60[0x20]; 6854 }; 6855 6856 struct mlx5_ifc_create_tis_in_bits { 6857 u8 opcode[0x10]; 6858 u8 uid[0x10]; 6859 6860 u8 reserved_at_20[0x10]; 6861 u8 op_mod[0x10]; 6862 6863 u8 reserved_at_40[0xc0]; 6864 6865 struct mlx5_ifc_tisc_bits ctx; 6866 }; 6867 6868 struct mlx5_ifc_create_tir_out_bits { 6869 u8 status[0x8]; 6870 u8 reserved_at_8[0x18]; 6871 6872 u8 syndrome[0x20]; 6873 6874 u8 reserved_at_40[0x8]; 6875 u8 tirn[0x18]; 6876 6877 u8 reserved_at_60[0x20]; 6878 }; 6879 6880 struct mlx5_ifc_create_tir_in_bits { 6881 u8 opcode[0x10]; 6882 u8 uid[0x10]; 6883 6884 u8 reserved_at_20[0x10]; 6885 u8 op_mod[0x10]; 6886 6887 u8 reserved_at_40[0xc0]; 6888 6889 struct mlx5_ifc_tirc_bits ctx; 6890 }; 6891 6892 struct mlx5_ifc_create_srq_out_bits { 6893 u8 status[0x8]; 6894 u8 reserved_at_8[0x18]; 6895 6896 u8 syndrome[0x20]; 6897 6898 u8 reserved_at_40[0x8]; 6899 u8 srqn[0x18]; 6900 6901 u8 reserved_at_60[0x20]; 6902 }; 6903 6904 struct mlx5_ifc_create_srq_in_bits { 6905 u8 opcode[0x10]; 6906 u8 uid[0x10]; 6907 6908 u8 reserved_at_20[0x10]; 6909 u8 op_mod[0x10]; 6910 6911 u8 reserved_at_40[0x40]; 6912 6913 struct mlx5_ifc_srqc_bits srq_context_entry; 6914 6915 u8 reserved_at_280[0x600]; 6916 6917 u8 pas[0][0x40]; 6918 }; 6919 6920 struct mlx5_ifc_create_sq_out_bits { 6921 u8 status[0x8]; 6922 u8 reserved_at_8[0x18]; 6923 6924 u8 syndrome[0x20]; 6925 6926 u8 reserved_at_40[0x8]; 6927 u8 sqn[0x18]; 6928 6929 u8 reserved_at_60[0x20]; 6930 }; 6931 6932 struct mlx5_ifc_create_sq_in_bits { 6933 u8 opcode[0x10]; 6934 u8 uid[0x10]; 6935 6936 u8 reserved_at_20[0x10]; 6937 u8 op_mod[0x10]; 6938 6939 u8 reserved_at_40[0xc0]; 6940 6941 struct mlx5_ifc_sqc_bits ctx; 6942 }; 6943 6944 struct mlx5_ifc_create_scheduling_element_out_bits { 6945 u8 status[0x8]; 6946 u8 reserved_at_8[0x18]; 6947 6948 u8 syndrome[0x20]; 6949 6950 u8 reserved_at_40[0x40]; 6951 6952 u8 scheduling_element_id[0x20]; 6953 6954 u8 reserved_at_a0[0x160]; 6955 }; 6956 6957 struct mlx5_ifc_create_scheduling_element_in_bits { 6958 u8 opcode[0x10]; 6959 u8 reserved_at_10[0x10]; 6960 6961 u8 reserved_at_20[0x10]; 6962 u8 op_mod[0x10]; 6963 6964 u8 scheduling_hierarchy[0x8]; 6965 u8 reserved_at_48[0x18]; 6966 6967 u8 reserved_at_60[0xa0]; 6968 6969 struct mlx5_ifc_scheduling_context_bits scheduling_context; 6970 6971 u8 reserved_at_300[0x100]; 6972 }; 6973 6974 struct mlx5_ifc_create_rqt_out_bits { 6975 u8 status[0x8]; 6976 u8 reserved_at_8[0x18]; 6977 6978 u8 syndrome[0x20]; 6979 6980 u8 reserved_at_40[0x8]; 6981 u8 rqtn[0x18]; 6982 6983 u8 reserved_at_60[0x20]; 6984 }; 6985 6986 struct mlx5_ifc_create_rqt_in_bits { 6987 u8 opcode[0x10]; 6988 u8 uid[0x10]; 6989 6990 u8 reserved_at_20[0x10]; 6991 u8 op_mod[0x10]; 6992 6993 u8 reserved_at_40[0xc0]; 6994 6995 struct mlx5_ifc_rqtc_bits rqt_context; 6996 }; 6997 6998 struct mlx5_ifc_create_rq_out_bits { 6999 u8 status[0x8]; 7000 u8 reserved_at_8[0x18]; 7001 7002 u8 syndrome[0x20]; 7003 7004 u8 reserved_at_40[0x8]; 7005 u8 rqn[0x18]; 7006 7007 u8 reserved_at_60[0x20]; 7008 }; 7009 7010 struct mlx5_ifc_create_rq_in_bits { 7011 u8 opcode[0x10]; 7012 u8 uid[0x10]; 7013 7014 u8 reserved_at_20[0x10]; 7015 u8 op_mod[0x10]; 7016 7017 u8 reserved_at_40[0xc0]; 7018 7019 struct mlx5_ifc_rqc_bits ctx; 7020 }; 7021 7022 struct mlx5_ifc_create_rmp_out_bits { 7023 u8 status[0x8]; 7024 u8 reserved_at_8[0x18]; 7025 7026 u8 syndrome[0x20]; 7027 7028 u8 reserved_at_40[0x8]; 7029 u8 rmpn[0x18]; 7030 7031 u8 reserved_at_60[0x20]; 7032 }; 7033 7034 struct mlx5_ifc_create_rmp_in_bits { 7035 u8 opcode[0x10]; 7036 u8 uid[0x10]; 7037 7038 u8 reserved_at_20[0x10]; 7039 u8 op_mod[0x10]; 7040 7041 u8 reserved_at_40[0xc0]; 7042 7043 struct mlx5_ifc_rmpc_bits ctx; 7044 }; 7045 7046 struct mlx5_ifc_create_qp_out_bits { 7047 u8 status[0x8]; 7048 u8 reserved_at_8[0x18]; 7049 7050 u8 syndrome[0x20]; 7051 7052 u8 reserved_at_40[0x8]; 7053 u8 qpn[0x18]; 7054 7055 u8 reserved_at_60[0x20]; 7056 }; 7057 7058 struct mlx5_ifc_create_qp_in_bits { 7059 u8 opcode[0x10]; 7060 u8 uid[0x10]; 7061 7062 u8 reserved_at_20[0x10]; 7063 u8 op_mod[0x10]; 7064 7065 u8 reserved_at_40[0x40]; 7066 7067 u8 opt_param_mask[0x20]; 7068 7069 u8 reserved_at_a0[0x20]; 7070 7071 struct mlx5_ifc_qpc_bits qpc; 7072 7073 u8 reserved_at_800[0x60]; 7074 7075 u8 wq_umem_valid[0x1]; 7076 u8 reserved_at_861[0x1f]; 7077 7078 u8 pas[0][0x40]; 7079 }; 7080 7081 struct mlx5_ifc_create_psv_out_bits { 7082 u8 status[0x8]; 7083 u8 reserved_at_8[0x18]; 7084 7085 u8 syndrome[0x20]; 7086 7087 u8 reserved_at_40[0x40]; 7088 7089 u8 reserved_at_80[0x8]; 7090 u8 psv0_index[0x18]; 7091 7092 u8 reserved_at_a0[0x8]; 7093 u8 psv1_index[0x18]; 7094 7095 u8 reserved_at_c0[0x8]; 7096 u8 psv2_index[0x18]; 7097 7098 u8 reserved_at_e0[0x8]; 7099 u8 psv3_index[0x18]; 7100 }; 7101 7102 struct mlx5_ifc_create_psv_in_bits { 7103 u8 opcode[0x10]; 7104 u8 reserved_at_10[0x10]; 7105 7106 u8 reserved_at_20[0x10]; 7107 u8 op_mod[0x10]; 7108 7109 u8 num_psv[0x4]; 7110 u8 reserved_at_44[0x4]; 7111 u8 pd[0x18]; 7112 7113 u8 reserved_at_60[0x20]; 7114 }; 7115 7116 struct mlx5_ifc_create_mkey_out_bits { 7117 u8 status[0x8]; 7118 u8 reserved_at_8[0x18]; 7119 7120 u8 syndrome[0x20]; 7121 7122 u8 reserved_at_40[0x8]; 7123 u8 mkey_index[0x18]; 7124 7125 u8 reserved_at_60[0x20]; 7126 }; 7127 7128 struct mlx5_ifc_create_mkey_in_bits { 7129 u8 opcode[0x10]; 7130 u8 reserved_at_10[0x10]; 7131 7132 u8 reserved_at_20[0x10]; 7133 u8 op_mod[0x10]; 7134 7135 u8 reserved_at_40[0x20]; 7136 7137 u8 pg_access[0x1]; 7138 u8 mkey_umem_valid[0x1]; 7139 u8 reserved_at_62[0x1e]; 7140 7141 struct mlx5_ifc_mkc_bits memory_key_mkey_entry; 7142 7143 u8 reserved_at_280[0x80]; 7144 7145 u8 translations_octword_actual_size[0x20]; 7146 7147 u8 reserved_at_320[0x560]; 7148 7149 u8 klm_pas_mtt[0][0x20]; 7150 }; 7151 7152 struct mlx5_ifc_create_flow_table_out_bits { 7153 u8 status[0x8]; 7154 u8 reserved_at_8[0x18]; 7155 7156 u8 syndrome[0x20]; 7157 7158 u8 reserved_at_40[0x8]; 7159 u8 table_id[0x18]; 7160 7161 u8 reserved_at_60[0x20]; 7162 }; 7163 7164 struct mlx5_ifc_flow_table_context_bits { 7165 u8 reformat_en[0x1]; 7166 u8 decap_en[0x1]; 7167 u8 reserved_at_2[0x2]; 7168 u8 table_miss_action[0x4]; 7169 u8 level[0x8]; 7170 u8 reserved_at_10[0x8]; 7171 u8 log_size[0x8]; 7172 7173 u8 reserved_at_20[0x8]; 7174 u8 table_miss_id[0x18]; 7175 7176 u8 reserved_at_40[0x8]; 7177 u8 lag_master_next_table_id[0x18]; 7178 7179 u8 reserved_at_60[0xe0]; 7180 }; 7181 7182 struct mlx5_ifc_create_flow_table_in_bits { 7183 u8 opcode[0x10]; 7184 u8 reserved_at_10[0x10]; 7185 7186 u8 reserved_at_20[0x10]; 7187 u8 op_mod[0x10]; 7188 7189 u8 other_vport[0x1]; 7190 u8 reserved_at_41[0xf]; 7191 u8 vport_number[0x10]; 7192 7193 u8 reserved_at_60[0x20]; 7194 7195 u8 table_type[0x8]; 7196 u8 reserved_at_88[0x18]; 7197 7198 u8 reserved_at_a0[0x20]; 7199 7200 struct mlx5_ifc_flow_table_context_bits flow_table_context; 7201 }; 7202 7203 struct mlx5_ifc_create_flow_group_out_bits { 7204 u8 status[0x8]; 7205 u8 reserved_at_8[0x18]; 7206 7207 u8 syndrome[0x20]; 7208 7209 u8 reserved_at_40[0x8]; 7210 u8 group_id[0x18]; 7211 7212 u8 reserved_at_60[0x20]; 7213 }; 7214 7215 enum { 7216 MLX5_CREATE_FLOW_GROUP_IN_MATCH_CRITERIA_ENABLE_OUTER_HEADERS = 0x0, 7217 MLX5_CREATE_FLOW_GROUP_IN_MATCH_CRITERIA_ENABLE_MISC_PARAMETERS = 0x1, 7218 MLX5_CREATE_FLOW_GROUP_IN_MATCH_CRITERIA_ENABLE_INNER_HEADERS = 0x2, 7219 MLX5_CREATE_FLOW_GROUP_IN_MATCH_CRITERIA_ENABLE_MISC_PARAMETERS_2 = 0x3, 7220 }; 7221 7222 struct mlx5_ifc_create_flow_group_in_bits { 7223 u8 opcode[0x10]; 7224 u8 reserved_at_10[0x10]; 7225 7226 u8 reserved_at_20[0x10]; 7227 u8 op_mod[0x10]; 7228 7229 u8 other_vport[0x1]; 7230 u8 reserved_at_41[0xf]; 7231 u8 vport_number[0x10]; 7232 7233 u8 reserved_at_60[0x20]; 7234 7235 u8 table_type[0x8]; 7236 u8 reserved_at_88[0x18]; 7237 7238 u8 reserved_at_a0[0x8]; 7239 u8 table_id[0x18]; 7240 7241 u8 source_eswitch_owner_vhca_id_valid[0x1]; 7242 7243 u8 reserved_at_c1[0x1f]; 7244 7245 u8 start_flow_index[0x20]; 7246 7247 u8 reserved_at_100[0x20]; 7248 7249 u8 end_flow_index[0x20]; 7250 7251 u8 reserved_at_140[0xa0]; 7252 7253 u8 reserved_at_1e0[0x18]; 7254 u8 match_criteria_enable[0x8]; 7255 7256 struct mlx5_ifc_fte_match_param_bits match_criteria; 7257 7258 u8 reserved_at_1200[0xe00]; 7259 }; 7260 7261 struct mlx5_ifc_create_eq_out_bits { 7262 u8 status[0x8]; 7263 u8 reserved_at_8[0x18]; 7264 7265 u8 syndrome[0x20]; 7266 7267 u8 reserved_at_40[0x18]; 7268 u8 eq_number[0x8]; 7269 7270 u8 reserved_at_60[0x20]; 7271 }; 7272 7273 struct mlx5_ifc_create_eq_in_bits { 7274 u8 opcode[0x10]; 7275 u8 reserved_at_10[0x10]; 7276 7277 u8 reserved_at_20[0x10]; 7278 u8 op_mod[0x10]; 7279 7280 u8 reserved_at_40[0x40]; 7281 7282 struct mlx5_ifc_eqc_bits eq_context_entry; 7283 7284 u8 reserved_at_280[0x40]; 7285 7286 u8 event_bitmask[0x40]; 7287 7288 u8 reserved_at_300[0x580]; 7289 7290 u8 pas[0][0x40]; 7291 }; 7292 7293 struct mlx5_ifc_create_dct_out_bits { 7294 u8 status[0x8]; 7295 u8 reserved_at_8[0x18]; 7296 7297 u8 syndrome[0x20]; 7298 7299 u8 reserved_at_40[0x8]; 7300 u8 dctn[0x18]; 7301 7302 u8 reserved_at_60[0x20]; 7303 }; 7304 7305 struct mlx5_ifc_create_dct_in_bits { 7306 u8 opcode[0x10]; 7307 u8 uid[0x10]; 7308 7309 u8 reserved_at_20[0x10]; 7310 u8 op_mod[0x10]; 7311 7312 u8 reserved_at_40[0x40]; 7313 7314 struct mlx5_ifc_dctc_bits dct_context_entry; 7315 7316 u8 reserved_at_280[0x180]; 7317 }; 7318 7319 struct mlx5_ifc_create_cq_out_bits { 7320 u8 status[0x8]; 7321 u8 reserved_at_8[0x18]; 7322 7323 u8 syndrome[0x20]; 7324 7325 u8 reserved_at_40[0x8]; 7326 u8 cqn[0x18]; 7327 7328 u8 reserved_at_60[0x20]; 7329 }; 7330 7331 struct mlx5_ifc_create_cq_in_bits { 7332 u8 opcode[0x10]; 7333 u8 uid[0x10]; 7334 7335 u8 reserved_at_20[0x10]; 7336 u8 op_mod[0x10]; 7337 7338 u8 reserved_at_40[0x40]; 7339 7340 struct mlx5_ifc_cqc_bits cq_context; 7341 7342 u8 reserved_at_280[0x60]; 7343 7344 u8 cq_umem_valid[0x1]; 7345 u8 reserved_at_2e1[0x59f]; 7346 7347 u8 pas[0][0x40]; 7348 }; 7349 7350 struct mlx5_ifc_config_int_moderation_out_bits { 7351 u8 status[0x8]; 7352 u8 reserved_at_8[0x18]; 7353 7354 u8 syndrome[0x20]; 7355 7356 u8 reserved_at_40[0x4]; 7357 u8 min_delay[0xc]; 7358 u8 int_vector[0x10]; 7359 7360 u8 reserved_at_60[0x20]; 7361 }; 7362 7363 enum { 7364 MLX5_CONFIG_INT_MODERATION_IN_OP_MOD_WRITE = 0x0, 7365 MLX5_CONFIG_INT_MODERATION_IN_OP_MOD_READ = 0x1, 7366 }; 7367 7368 struct mlx5_ifc_config_int_moderation_in_bits { 7369 u8 opcode[0x10]; 7370 u8 reserved_at_10[0x10]; 7371 7372 u8 reserved_at_20[0x10]; 7373 u8 op_mod[0x10]; 7374 7375 u8 reserved_at_40[0x4]; 7376 u8 min_delay[0xc]; 7377 u8 int_vector[0x10]; 7378 7379 u8 reserved_at_60[0x20]; 7380 }; 7381 7382 struct mlx5_ifc_attach_to_mcg_out_bits { 7383 u8 status[0x8]; 7384 u8 reserved_at_8[0x18]; 7385 7386 u8 syndrome[0x20]; 7387 7388 u8 reserved_at_40[0x40]; 7389 }; 7390 7391 struct mlx5_ifc_attach_to_mcg_in_bits { 7392 u8 opcode[0x10]; 7393 u8 uid[0x10]; 7394 7395 u8 reserved_at_20[0x10]; 7396 u8 op_mod[0x10]; 7397 7398 u8 reserved_at_40[0x8]; 7399 u8 qpn[0x18]; 7400 7401 u8 reserved_at_60[0x20]; 7402 7403 u8 multicast_gid[16][0x8]; 7404 }; 7405 7406 struct mlx5_ifc_arm_xrq_out_bits { 7407 u8 status[0x8]; 7408 u8 reserved_at_8[0x18]; 7409 7410 u8 syndrome[0x20]; 7411 7412 u8 reserved_at_40[0x40]; 7413 }; 7414 7415 struct mlx5_ifc_arm_xrq_in_bits { 7416 u8 opcode[0x10]; 7417 u8 reserved_at_10[0x10]; 7418 7419 u8 reserved_at_20[0x10]; 7420 u8 op_mod[0x10]; 7421 7422 u8 reserved_at_40[0x8]; 7423 u8 xrqn[0x18]; 7424 7425 u8 reserved_at_60[0x10]; 7426 u8 lwm[0x10]; 7427 }; 7428 7429 struct mlx5_ifc_arm_xrc_srq_out_bits { 7430 u8 status[0x8]; 7431 u8 reserved_at_8[0x18]; 7432 7433 u8 syndrome[0x20]; 7434 7435 u8 reserved_at_40[0x40]; 7436 }; 7437 7438 enum { 7439 MLX5_ARM_XRC_SRQ_IN_OP_MOD_XRC_SRQ = 0x1, 7440 }; 7441 7442 struct mlx5_ifc_arm_xrc_srq_in_bits { 7443 u8 opcode[0x10]; 7444 u8 uid[0x10]; 7445 7446 u8 reserved_at_20[0x10]; 7447 u8 op_mod[0x10]; 7448 7449 u8 reserved_at_40[0x8]; 7450 u8 xrc_srqn[0x18]; 7451 7452 u8 reserved_at_60[0x10]; 7453 u8 lwm[0x10]; 7454 }; 7455 7456 struct mlx5_ifc_arm_rq_out_bits { 7457 u8 status[0x8]; 7458 u8 reserved_at_8[0x18]; 7459 7460 u8 syndrome[0x20]; 7461 7462 u8 reserved_at_40[0x40]; 7463 }; 7464 7465 enum { 7466 MLX5_ARM_RQ_IN_OP_MOD_SRQ = 0x1, 7467 MLX5_ARM_RQ_IN_OP_MOD_XRQ = 0x2, 7468 }; 7469 7470 struct mlx5_ifc_arm_rq_in_bits { 7471 u8 opcode[0x10]; 7472 u8 uid[0x10]; 7473 7474 u8 reserved_at_20[0x10]; 7475 u8 op_mod[0x10]; 7476 7477 u8 reserved_at_40[0x8]; 7478 u8 srq_number[0x18]; 7479 7480 u8 reserved_at_60[0x10]; 7481 u8 lwm[0x10]; 7482 }; 7483 7484 struct mlx5_ifc_arm_dct_out_bits { 7485 u8 status[0x8]; 7486 u8 reserved_at_8[0x18]; 7487 7488 u8 syndrome[0x20]; 7489 7490 u8 reserved_at_40[0x40]; 7491 }; 7492 7493 struct mlx5_ifc_arm_dct_in_bits { 7494 u8 opcode[0x10]; 7495 u8 reserved_at_10[0x10]; 7496 7497 u8 reserved_at_20[0x10]; 7498 u8 op_mod[0x10]; 7499 7500 u8 reserved_at_40[0x8]; 7501 u8 dct_number[0x18]; 7502 7503 u8 reserved_at_60[0x20]; 7504 }; 7505 7506 struct mlx5_ifc_alloc_xrcd_out_bits { 7507 u8 status[0x8]; 7508 u8 reserved_at_8[0x18]; 7509 7510 u8 syndrome[0x20]; 7511 7512 u8 reserved_at_40[0x8]; 7513 u8 xrcd[0x18]; 7514 7515 u8 reserved_at_60[0x20]; 7516 }; 7517 7518 struct mlx5_ifc_alloc_xrcd_in_bits { 7519 u8 opcode[0x10]; 7520 u8 uid[0x10]; 7521 7522 u8 reserved_at_20[0x10]; 7523 u8 op_mod[0x10]; 7524 7525 u8 reserved_at_40[0x40]; 7526 }; 7527 7528 struct mlx5_ifc_alloc_uar_out_bits { 7529 u8 status[0x8]; 7530 u8 reserved_at_8[0x18]; 7531 7532 u8 syndrome[0x20]; 7533 7534 u8 reserved_at_40[0x8]; 7535 u8 uar[0x18]; 7536 7537 u8 reserved_at_60[0x20]; 7538 }; 7539 7540 struct mlx5_ifc_alloc_uar_in_bits { 7541 u8 opcode[0x10]; 7542 u8 reserved_at_10[0x10]; 7543 7544 u8 reserved_at_20[0x10]; 7545 u8 op_mod[0x10]; 7546 7547 u8 reserved_at_40[0x40]; 7548 }; 7549 7550 struct mlx5_ifc_alloc_transport_domain_out_bits { 7551 u8 status[0x8]; 7552 u8 reserved_at_8[0x18]; 7553 7554 u8 syndrome[0x20]; 7555 7556 u8 reserved_at_40[0x8]; 7557 u8 transport_domain[0x18]; 7558 7559 u8 reserved_at_60[0x20]; 7560 }; 7561 7562 struct mlx5_ifc_alloc_transport_domain_in_bits { 7563 u8 opcode[0x10]; 7564 u8 uid[0x10]; 7565 7566 u8 reserved_at_20[0x10]; 7567 u8 op_mod[0x10]; 7568 7569 u8 reserved_at_40[0x40]; 7570 }; 7571 7572 struct mlx5_ifc_alloc_q_counter_out_bits { 7573 u8 status[0x8]; 7574 u8 reserved_at_8[0x18]; 7575 7576 u8 syndrome[0x20]; 7577 7578 u8 reserved_at_40[0x18]; 7579 u8 counter_set_id[0x8]; 7580 7581 u8 reserved_at_60[0x20]; 7582 }; 7583 7584 struct mlx5_ifc_alloc_q_counter_in_bits { 7585 u8 opcode[0x10]; 7586 u8 uid[0x10]; 7587 7588 u8 reserved_at_20[0x10]; 7589 u8 op_mod[0x10]; 7590 7591 u8 reserved_at_40[0x40]; 7592 }; 7593 7594 struct mlx5_ifc_alloc_pd_out_bits { 7595 u8 status[0x8]; 7596 u8 reserved_at_8[0x18]; 7597 7598 u8 syndrome[0x20]; 7599 7600 u8 reserved_at_40[0x8]; 7601 u8 pd[0x18]; 7602 7603 u8 reserved_at_60[0x20]; 7604 }; 7605 7606 struct mlx5_ifc_alloc_pd_in_bits { 7607 u8 opcode[0x10]; 7608 u8 uid[0x10]; 7609 7610 u8 reserved_at_20[0x10]; 7611 u8 op_mod[0x10]; 7612 7613 u8 reserved_at_40[0x40]; 7614 }; 7615 7616 struct mlx5_ifc_alloc_flow_counter_out_bits { 7617 u8 status[0x8]; 7618 u8 reserved_at_8[0x18]; 7619 7620 u8 syndrome[0x20]; 7621 7622 u8 flow_counter_id[0x20]; 7623 7624 u8 reserved_at_60[0x20]; 7625 }; 7626 7627 struct mlx5_ifc_alloc_flow_counter_in_bits { 7628 u8 opcode[0x10]; 7629 u8 reserved_at_10[0x10]; 7630 7631 u8 reserved_at_20[0x10]; 7632 u8 op_mod[0x10]; 7633 7634 u8 reserved_at_40[0x40]; 7635 }; 7636 7637 struct mlx5_ifc_add_vxlan_udp_dport_out_bits { 7638 u8 status[0x8]; 7639 u8 reserved_at_8[0x18]; 7640 7641 u8 syndrome[0x20]; 7642 7643 u8 reserved_at_40[0x40]; 7644 }; 7645 7646 struct mlx5_ifc_add_vxlan_udp_dport_in_bits { 7647 u8 opcode[0x10]; 7648 u8 reserved_at_10[0x10]; 7649 7650 u8 reserved_at_20[0x10]; 7651 u8 op_mod[0x10]; 7652 7653 u8 reserved_at_40[0x20]; 7654 7655 u8 reserved_at_60[0x10]; 7656 u8 vxlan_udp_port[0x10]; 7657 }; 7658 7659 struct mlx5_ifc_set_pp_rate_limit_out_bits { 7660 u8 status[0x8]; 7661 u8 reserved_at_8[0x18]; 7662 7663 u8 syndrome[0x20]; 7664 7665 u8 reserved_at_40[0x40]; 7666 }; 7667 7668 struct mlx5_ifc_set_pp_rate_limit_in_bits { 7669 u8 opcode[0x10]; 7670 u8 reserved_at_10[0x10]; 7671 7672 u8 reserved_at_20[0x10]; 7673 u8 op_mod[0x10]; 7674 7675 u8 reserved_at_40[0x10]; 7676 u8 rate_limit_index[0x10]; 7677 7678 u8 reserved_at_60[0x20]; 7679 7680 u8 rate_limit[0x20]; 7681 7682 u8 burst_upper_bound[0x20]; 7683 7684 u8 reserved_at_c0[0x10]; 7685 u8 typical_packet_size[0x10]; 7686 7687 u8 reserved_at_e0[0x120]; 7688 }; 7689 7690 struct mlx5_ifc_access_register_out_bits { 7691 u8 status[0x8]; 7692 u8 reserved_at_8[0x18]; 7693 7694 u8 syndrome[0x20]; 7695 7696 u8 reserved_at_40[0x40]; 7697 7698 u8 register_data[0][0x20]; 7699 }; 7700 7701 enum { 7702 MLX5_ACCESS_REGISTER_IN_OP_MOD_WRITE = 0x0, 7703 MLX5_ACCESS_REGISTER_IN_OP_MOD_READ = 0x1, 7704 }; 7705 7706 struct mlx5_ifc_access_register_in_bits { 7707 u8 opcode[0x10]; 7708 u8 reserved_at_10[0x10]; 7709 7710 u8 reserved_at_20[0x10]; 7711 u8 op_mod[0x10]; 7712 7713 u8 reserved_at_40[0x10]; 7714 u8 register_id[0x10]; 7715 7716 u8 argument[0x20]; 7717 7718 u8 register_data[0][0x20]; 7719 }; 7720 7721 struct mlx5_ifc_sltp_reg_bits { 7722 u8 status[0x4]; 7723 u8 version[0x4]; 7724 u8 local_port[0x8]; 7725 u8 pnat[0x2]; 7726 u8 reserved_at_12[0x2]; 7727 u8 lane[0x4]; 7728 u8 reserved_at_18[0x8]; 7729 7730 u8 reserved_at_20[0x20]; 7731 7732 u8 reserved_at_40[0x7]; 7733 u8 polarity[0x1]; 7734 u8 ob_tap0[0x8]; 7735 u8 ob_tap1[0x8]; 7736 u8 ob_tap2[0x8]; 7737 7738 u8 reserved_at_60[0xc]; 7739 u8 ob_preemp_mode[0x4]; 7740 u8 ob_reg[0x8]; 7741 u8 ob_bias[0x8]; 7742 7743 u8 reserved_at_80[0x20]; 7744 }; 7745 7746 struct mlx5_ifc_slrg_reg_bits { 7747 u8 status[0x4]; 7748 u8 version[0x4]; 7749 u8 local_port[0x8]; 7750 u8 pnat[0x2]; 7751 u8 reserved_at_12[0x2]; 7752 u8 lane[0x4]; 7753 u8 reserved_at_18[0x8]; 7754 7755 u8 time_to_link_up[0x10]; 7756 u8 reserved_at_30[0xc]; 7757 u8 grade_lane_speed[0x4]; 7758 7759 u8 grade_version[0x8]; 7760 u8 grade[0x18]; 7761 7762 u8 reserved_at_60[0x4]; 7763 u8 height_grade_type[0x4]; 7764 u8 height_grade[0x18]; 7765 7766 u8 height_dz[0x10]; 7767 u8 height_dv[0x10]; 7768 7769 u8 reserved_at_a0[0x10]; 7770 u8 height_sigma[0x10]; 7771 7772 u8 reserved_at_c0[0x20]; 7773 7774 u8 reserved_at_e0[0x4]; 7775 u8 phase_grade_type[0x4]; 7776 u8 phase_grade[0x18]; 7777 7778 u8 reserved_at_100[0x8]; 7779 u8 phase_eo_pos[0x8]; 7780 u8 reserved_at_110[0x8]; 7781 u8 phase_eo_neg[0x8]; 7782 7783 u8 ffe_set_tested[0x10]; 7784 u8 test_errors_per_lane[0x10]; 7785 }; 7786 7787 struct mlx5_ifc_pvlc_reg_bits { 7788 u8 reserved_at_0[0x8]; 7789 u8 local_port[0x8]; 7790 u8 reserved_at_10[0x10]; 7791 7792 u8 reserved_at_20[0x1c]; 7793 u8 vl_hw_cap[0x4]; 7794 7795 u8 reserved_at_40[0x1c]; 7796 u8 vl_admin[0x4]; 7797 7798 u8 reserved_at_60[0x1c]; 7799 u8 vl_operational[0x4]; 7800 }; 7801 7802 struct mlx5_ifc_pude_reg_bits { 7803 u8 swid[0x8]; 7804 u8 local_port[0x8]; 7805 u8 reserved_at_10[0x4]; 7806 u8 admin_status[0x4]; 7807 u8 reserved_at_18[0x4]; 7808 u8 oper_status[0x4]; 7809 7810 u8 reserved_at_20[0x60]; 7811 }; 7812 7813 struct mlx5_ifc_ptys_reg_bits { 7814 u8 reserved_at_0[0x1]; 7815 u8 an_disable_admin[0x1]; 7816 u8 an_disable_cap[0x1]; 7817 u8 reserved_at_3[0x5]; 7818 u8 local_port[0x8]; 7819 u8 reserved_at_10[0xd]; 7820 u8 proto_mask[0x3]; 7821 7822 u8 an_status[0x4]; 7823 u8 reserved_at_24[0x3c]; 7824 7825 u8 eth_proto_capability[0x20]; 7826 7827 u8 ib_link_width_capability[0x10]; 7828 u8 ib_proto_capability[0x10]; 7829 7830 u8 reserved_at_a0[0x20]; 7831 7832 u8 eth_proto_admin[0x20]; 7833 7834 u8 ib_link_width_admin[0x10]; 7835 u8 ib_proto_admin[0x10]; 7836 7837 u8 reserved_at_100[0x20]; 7838 7839 u8 eth_proto_oper[0x20]; 7840 7841 u8 ib_link_width_oper[0x10]; 7842 u8 ib_proto_oper[0x10]; 7843 7844 u8 reserved_at_160[0x1c]; 7845 u8 connector_type[0x4]; 7846 7847 u8 eth_proto_lp_advertise[0x20]; 7848 7849 u8 reserved_at_1a0[0x60]; 7850 }; 7851 7852 struct mlx5_ifc_mlcr_reg_bits { 7853 u8 reserved_at_0[0x8]; 7854 u8 local_port[0x8]; 7855 u8 reserved_at_10[0x20]; 7856 7857 u8 beacon_duration[0x10]; 7858 u8 reserved_at_40[0x10]; 7859 7860 u8 beacon_remain[0x10]; 7861 }; 7862 7863 struct mlx5_ifc_ptas_reg_bits { 7864 u8 reserved_at_0[0x20]; 7865 7866 u8 algorithm_options[0x10]; 7867 u8 reserved_at_30[0x4]; 7868 u8 repetitions_mode[0x4]; 7869 u8 num_of_repetitions[0x8]; 7870 7871 u8 grade_version[0x8]; 7872 u8 height_grade_type[0x4]; 7873 u8 phase_grade_type[0x4]; 7874 u8 height_grade_weight[0x8]; 7875 u8 phase_grade_weight[0x8]; 7876 7877 u8 gisim_measure_bits[0x10]; 7878 u8 adaptive_tap_measure_bits[0x10]; 7879 7880 u8 ber_bath_high_error_threshold[0x10]; 7881 u8 ber_bath_mid_error_threshold[0x10]; 7882 7883 u8 ber_bath_low_error_threshold[0x10]; 7884 u8 one_ratio_high_threshold[0x10]; 7885 7886 u8 one_ratio_high_mid_threshold[0x10]; 7887 u8 one_ratio_low_mid_threshold[0x10]; 7888 7889 u8 one_ratio_low_threshold[0x10]; 7890 u8 ndeo_error_threshold[0x10]; 7891 7892 u8 mixer_offset_step_size[0x10]; 7893 u8 reserved_at_110[0x8]; 7894 u8 mix90_phase_for_voltage_bath[0x8]; 7895 7896 u8 mixer_offset_start[0x10]; 7897 u8 mixer_offset_end[0x10]; 7898 7899 u8 reserved_at_140[0x15]; 7900 u8 ber_test_time[0xb]; 7901 }; 7902 7903 struct mlx5_ifc_pspa_reg_bits { 7904 u8 swid[0x8]; 7905 u8 local_port[0x8]; 7906 u8 sub_port[0x8]; 7907 u8 reserved_at_18[0x8]; 7908 7909 u8 reserved_at_20[0x20]; 7910 }; 7911 7912 struct mlx5_ifc_pqdr_reg_bits { 7913 u8 reserved_at_0[0x8]; 7914 u8 local_port[0x8]; 7915 u8 reserved_at_10[0x5]; 7916 u8 prio[0x3]; 7917 u8 reserved_at_18[0x6]; 7918 u8 mode[0x2]; 7919 7920 u8 reserved_at_20[0x20]; 7921 7922 u8 reserved_at_40[0x10]; 7923 u8 min_threshold[0x10]; 7924 7925 u8 reserved_at_60[0x10]; 7926 u8 max_threshold[0x10]; 7927 7928 u8 reserved_at_80[0x10]; 7929 u8 mark_probability_denominator[0x10]; 7930 7931 u8 reserved_at_a0[0x60]; 7932 }; 7933 7934 struct mlx5_ifc_ppsc_reg_bits { 7935 u8 reserved_at_0[0x8]; 7936 u8 local_port[0x8]; 7937 u8 reserved_at_10[0x10]; 7938 7939 u8 reserved_at_20[0x60]; 7940 7941 u8 reserved_at_80[0x1c]; 7942 u8 wrps_admin[0x4]; 7943 7944 u8 reserved_at_a0[0x1c]; 7945 u8 wrps_status[0x4]; 7946 7947 u8 reserved_at_c0[0x8]; 7948 u8 up_threshold[0x8]; 7949 u8 reserved_at_d0[0x8]; 7950 u8 down_threshold[0x8]; 7951 7952 u8 reserved_at_e0[0x20]; 7953 7954 u8 reserved_at_100[0x1c]; 7955 u8 srps_admin[0x4]; 7956 7957 u8 reserved_at_120[0x1c]; 7958 u8 srps_status[0x4]; 7959 7960 u8 reserved_at_140[0x40]; 7961 }; 7962 7963 struct mlx5_ifc_pplr_reg_bits { 7964 u8 reserved_at_0[0x8]; 7965 u8 local_port[0x8]; 7966 u8 reserved_at_10[0x10]; 7967 7968 u8 reserved_at_20[0x8]; 7969 u8 lb_cap[0x8]; 7970 u8 reserved_at_30[0x8]; 7971 u8 lb_en[0x8]; 7972 }; 7973 7974 struct mlx5_ifc_pplm_reg_bits { 7975 u8 reserved_at_0[0x8]; 7976 u8 local_port[0x8]; 7977 u8 reserved_at_10[0x10]; 7978 7979 u8 reserved_at_20[0x20]; 7980 7981 u8 port_profile_mode[0x8]; 7982 u8 static_port_profile[0x8]; 7983 u8 active_port_profile[0x8]; 7984 u8 reserved_at_58[0x8]; 7985 7986 u8 retransmission_active[0x8]; 7987 u8 fec_mode_active[0x18]; 7988 7989 u8 rs_fec_correction_bypass_cap[0x4]; 7990 u8 reserved_at_84[0x8]; 7991 u8 fec_override_cap_56g[0x4]; 7992 u8 fec_override_cap_100g[0x4]; 7993 u8 fec_override_cap_50g[0x4]; 7994 u8 fec_override_cap_25g[0x4]; 7995 u8 fec_override_cap_10g_40g[0x4]; 7996 7997 u8 rs_fec_correction_bypass_admin[0x4]; 7998 u8 reserved_at_a4[0x8]; 7999 u8 fec_override_admin_56g[0x4]; 8000 u8 fec_override_admin_100g[0x4]; 8001 u8 fec_override_admin_50g[0x4]; 8002 u8 fec_override_admin_25g[0x4]; 8003 u8 fec_override_admin_10g_40g[0x4]; 8004 }; 8005 8006 struct mlx5_ifc_ppcnt_reg_bits { 8007 u8 swid[0x8]; 8008 u8 local_port[0x8]; 8009 u8 pnat[0x2]; 8010 u8 reserved_at_12[0x8]; 8011 u8 grp[0x6]; 8012 8013 u8 clr[0x1]; 8014 u8 reserved_at_21[0x1c]; 8015 u8 prio_tc[0x3]; 8016 8017 union mlx5_ifc_eth_cntrs_grp_data_layout_auto_bits counter_set; 8018 }; 8019 8020 struct mlx5_ifc_mpcnt_reg_bits { 8021 u8 reserved_at_0[0x8]; 8022 u8 pcie_index[0x8]; 8023 u8 reserved_at_10[0xa]; 8024 u8 grp[0x6]; 8025 8026 u8 clr[0x1]; 8027 u8 reserved_at_21[0x1f]; 8028 8029 union mlx5_ifc_pcie_cntrs_grp_data_layout_auto_bits counter_set; 8030 }; 8031 8032 struct mlx5_ifc_ppad_reg_bits { 8033 u8 reserved_at_0[0x3]; 8034 u8 single_mac[0x1]; 8035 u8 reserved_at_4[0x4]; 8036 u8 local_port[0x8]; 8037 u8 mac_47_32[0x10]; 8038 8039 u8 mac_31_0[0x20]; 8040 8041 u8 reserved_at_40[0x40]; 8042 }; 8043 8044 struct mlx5_ifc_pmtu_reg_bits { 8045 u8 reserved_at_0[0x8]; 8046 u8 local_port[0x8]; 8047 u8 reserved_at_10[0x10]; 8048 8049 u8 max_mtu[0x10]; 8050 u8 reserved_at_30[0x10]; 8051 8052 u8 admin_mtu[0x10]; 8053 u8 reserved_at_50[0x10]; 8054 8055 u8 oper_mtu[0x10]; 8056 u8 reserved_at_70[0x10]; 8057 }; 8058 8059 struct mlx5_ifc_pmpr_reg_bits { 8060 u8 reserved_at_0[0x8]; 8061 u8 module[0x8]; 8062 u8 reserved_at_10[0x10]; 8063 8064 u8 reserved_at_20[0x18]; 8065 u8 attenuation_5g[0x8]; 8066 8067 u8 reserved_at_40[0x18]; 8068 u8 attenuation_7g[0x8]; 8069 8070 u8 reserved_at_60[0x18]; 8071 u8 attenuation_12g[0x8]; 8072 }; 8073 8074 struct mlx5_ifc_pmpe_reg_bits { 8075 u8 reserved_at_0[0x8]; 8076 u8 module[0x8]; 8077 u8 reserved_at_10[0xc]; 8078 u8 module_status[0x4]; 8079 8080 u8 reserved_at_20[0x60]; 8081 }; 8082 8083 struct mlx5_ifc_pmpc_reg_bits { 8084 u8 module_state_updated[32][0x8]; 8085 }; 8086 8087 struct mlx5_ifc_pmlpn_reg_bits { 8088 u8 reserved_at_0[0x4]; 8089 u8 mlpn_status[0x4]; 8090 u8 local_port[0x8]; 8091 u8 reserved_at_10[0x10]; 8092 8093 u8 e[0x1]; 8094 u8 reserved_at_21[0x1f]; 8095 }; 8096 8097 struct mlx5_ifc_pmlp_reg_bits { 8098 u8 rxtx[0x1]; 8099 u8 reserved_at_1[0x7]; 8100 u8 local_port[0x8]; 8101 u8 reserved_at_10[0x8]; 8102 u8 width[0x8]; 8103 8104 u8 lane0_module_mapping[0x20]; 8105 8106 u8 lane1_module_mapping[0x20]; 8107 8108 u8 lane2_module_mapping[0x20]; 8109 8110 u8 lane3_module_mapping[0x20]; 8111 8112 u8 reserved_at_a0[0x160]; 8113 }; 8114 8115 struct mlx5_ifc_pmaos_reg_bits { 8116 u8 reserved_at_0[0x8]; 8117 u8 module[0x8]; 8118 u8 reserved_at_10[0x4]; 8119 u8 admin_status[0x4]; 8120 u8 reserved_at_18[0x4]; 8121 u8 oper_status[0x4]; 8122 8123 u8 ase[0x1]; 8124 u8 ee[0x1]; 8125 u8 reserved_at_22[0x1c]; 8126 u8 e[0x2]; 8127 8128 u8 reserved_at_40[0x40]; 8129 }; 8130 8131 struct mlx5_ifc_plpc_reg_bits { 8132 u8 reserved_at_0[0x4]; 8133 u8 profile_id[0xc]; 8134 u8 reserved_at_10[0x4]; 8135 u8 proto_mask[0x4]; 8136 u8 reserved_at_18[0x8]; 8137 8138 u8 reserved_at_20[0x10]; 8139 u8 lane_speed[0x10]; 8140 8141 u8 reserved_at_40[0x17]; 8142 u8 lpbf[0x1]; 8143 u8 fec_mode_policy[0x8]; 8144 8145 u8 retransmission_capability[0x8]; 8146 u8 fec_mode_capability[0x18]; 8147 8148 u8 retransmission_support_admin[0x8]; 8149 u8 fec_mode_support_admin[0x18]; 8150 8151 u8 retransmission_request_admin[0x8]; 8152 u8 fec_mode_request_admin[0x18]; 8153 8154 u8 reserved_at_c0[0x80]; 8155 }; 8156 8157 struct mlx5_ifc_plib_reg_bits { 8158 u8 reserved_at_0[0x8]; 8159 u8 local_port[0x8]; 8160 u8 reserved_at_10[0x8]; 8161 u8 ib_port[0x8]; 8162 8163 u8 reserved_at_20[0x60]; 8164 }; 8165 8166 struct mlx5_ifc_plbf_reg_bits { 8167 u8 reserved_at_0[0x8]; 8168 u8 local_port[0x8]; 8169 u8 reserved_at_10[0xd]; 8170 u8 lbf_mode[0x3]; 8171 8172 u8 reserved_at_20[0x20]; 8173 }; 8174 8175 struct mlx5_ifc_pipg_reg_bits { 8176 u8 reserved_at_0[0x8]; 8177 u8 local_port[0x8]; 8178 u8 reserved_at_10[0x10]; 8179 8180 u8 dic[0x1]; 8181 u8 reserved_at_21[0x19]; 8182 u8 ipg[0x4]; 8183 u8 reserved_at_3e[0x2]; 8184 }; 8185 8186 struct mlx5_ifc_pifr_reg_bits { 8187 u8 reserved_at_0[0x8]; 8188 u8 local_port[0x8]; 8189 u8 reserved_at_10[0x10]; 8190 8191 u8 reserved_at_20[0xe0]; 8192 8193 u8 port_filter[8][0x20]; 8194 8195 u8 port_filter_update_en[8][0x20]; 8196 }; 8197 8198 struct mlx5_ifc_pfcc_reg_bits { 8199 u8 reserved_at_0[0x8]; 8200 u8 local_port[0x8]; 8201 u8 reserved_at_10[0xb]; 8202 u8 ppan_mask_n[0x1]; 8203 u8 minor_stall_mask[0x1]; 8204 u8 critical_stall_mask[0x1]; 8205 u8 reserved_at_1e[0x2]; 8206 8207 u8 ppan[0x4]; 8208 u8 reserved_at_24[0x4]; 8209 u8 prio_mask_tx[0x8]; 8210 u8 reserved_at_30[0x8]; 8211 u8 prio_mask_rx[0x8]; 8212 8213 u8 pptx[0x1]; 8214 u8 aptx[0x1]; 8215 u8 pptx_mask_n[0x1]; 8216 u8 reserved_at_43[0x5]; 8217 u8 pfctx[0x8]; 8218 u8 reserved_at_50[0x10]; 8219 8220 u8 pprx[0x1]; 8221 u8 aprx[0x1]; 8222 u8 pprx_mask_n[0x1]; 8223 u8 reserved_at_63[0x5]; 8224 u8 pfcrx[0x8]; 8225 u8 reserved_at_70[0x10]; 8226 8227 u8 device_stall_minor_watermark[0x10]; 8228 u8 device_stall_critical_watermark[0x10]; 8229 8230 u8 reserved_at_a0[0x60]; 8231 }; 8232 8233 struct mlx5_ifc_pelc_reg_bits { 8234 u8 op[0x4]; 8235 u8 reserved_at_4[0x4]; 8236 u8 local_port[0x8]; 8237 u8 reserved_at_10[0x10]; 8238 8239 u8 op_admin[0x8]; 8240 u8 op_capability[0x8]; 8241 u8 op_request[0x8]; 8242 u8 op_active[0x8]; 8243 8244 u8 admin[0x40]; 8245 8246 u8 capability[0x40]; 8247 8248 u8 request[0x40]; 8249 8250 u8 active[0x40]; 8251 8252 u8 reserved_at_140[0x80]; 8253 }; 8254 8255 struct mlx5_ifc_peir_reg_bits { 8256 u8 reserved_at_0[0x8]; 8257 u8 local_port[0x8]; 8258 u8 reserved_at_10[0x10]; 8259 8260 u8 reserved_at_20[0xc]; 8261 u8 error_count[0x4]; 8262 u8 reserved_at_30[0x10]; 8263 8264 u8 reserved_at_40[0xc]; 8265 u8 lane[0x4]; 8266 u8 reserved_at_50[0x8]; 8267 u8 error_type[0x8]; 8268 }; 8269 8270 struct mlx5_ifc_mpegc_reg_bits { 8271 u8 reserved_at_0[0x30]; 8272 u8 field_select[0x10]; 8273 8274 u8 tx_overflow_sense[0x1]; 8275 u8 mark_cqe[0x1]; 8276 u8 mark_cnp[0x1]; 8277 u8 reserved_at_43[0x1b]; 8278 u8 tx_lossy_overflow_oper[0x2]; 8279 8280 u8 reserved_at_60[0x100]; 8281 }; 8282 8283 struct mlx5_ifc_pcam_enhanced_features_bits { 8284 u8 reserved_at_0[0x6d]; 8285 u8 rx_icrc_encapsulated_counter[0x1]; 8286 u8 reserved_at_6e[0x8]; 8287 u8 pfcc_mask[0x1]; 8288 u8 reserved_at_77[0x3]; 8289 u8 per_lane_error_counters[0x1]; 8290 u8 rx_buffer_fullness_counters[0x1]; 8291 u8 ptys_connector_type[0x1]; 8292 u8 reserved_at_7d[0x1]; 8293 u8 ppcnt_discard_group[0x1]; 8294 u8 ppcnt_statistical_group[0x1]; 8295 }; 8296 8297 struct mlx5_ifc_pcam_regs_5000_to_507f_bits { 8298 u8 port_access_reg_cap_mask_127_to_96[0x20]; 8299 u8 port_access_reg_cap_mask_95_to_64[0x20]; 8300 8301 u8 port_access_reg_cap_mask_63_to_36[0x1c]; 8302 u8 pplm[0x1]; 8303 u8 port_access_reg_cap_mask_34_to_32[0x3]; 8304 8305 u8 port_access_reg_cap_mask_31_to_13[0x13]; 8306 u8 pbmc[0x1]; 8307 u8 pptb[0x1]; 8308 u8 port_access_reg_cap_mask_10_to_09[0x2]; 8309 u8 ppcnt[0x1]; 8310 u8 port_access_reg_cap_mask_07_to_00[0x8]; 8311 }; 8312 8313 struct mlx5_ifc_pcam_reg_bits { 8314 u8 reserved_at_0[0x8]; 8315 u8 feature_group[0x8]; 8316 u8 reserved_at_10[0x8]; 8317 u8 access_reg_group[0x8]; 8318 8319 u8 reserved_at_20[0x20]; 8320 8321 union { 8322 struct mlx5_ifc_pcam_regs_5000_to_507f_bits regs_5000_to_507f; 8323 u8 reserved_at_0[0x80]; 8324 } port_access_reg_cap_mask; 8325 8326 u8 reserved_at_c0[0x80]; 8327 8328 union { 8329 struct mlx5_ifc_pcam_enhanced_features_bits enhanced_features; 8330 u8 reserved_at_0[0x80]; 8331 } feature_cap_mask; 8332 8333 u8 reserved_at_1c0[0xc0]; 8334 }; 8335 8336 struct mlx5_ifc_mcam_enhanced_features_bits { 8337 u8 reserved_at_0[0x74]; 8338 u8 mark_tx_action_cnp[0x1]; 8339 u8 mark_tx_action_cqe[0x1]; 8340 u8 dynamic_tx_overflow[0x1]; 8341 u8 reserved_at_77[0x4]; 8342 u8 pcie_outbound_stalled[0x1]; 8343 u8 tx_overflow_buffer_pkt[0x1]; 8344 u8 mtpps_enh_out_per_adj[0x1]; 8345 u8 mtpps_fs[0x1]; 8346 u8 pcie_performance_group[0x1]; 8347 }; 8348 8349 struct mlx5_ifc_mcam_access_reg_bits { 8350 u8 reserved_at_0[0x1c]; 8351 u8 mcda[0x1]; 8352 u8 mcc[0x1]; 8353 u8 mcqi[0x1]; 8354 u8 reserved_at_1f[0x1]; 8355 8356 u8 regs_95_to_87[0x9]; 8357 u8 mpegc[0x1]; 8358 u8 regs_85_to_68[0x12]; 8359 u8 tracer_registers[0x4]; 8360 8361 u8 regs_63_to_32[0x20]; 8362 u8 regs_31_to_0[0x20]; 8363 }; 8364 8365 struct mlx5_ifc_mcam_reg_bits { 8366 u8 reserved_at_0[0x8]; 8367 u8 feature_group[0x8]; 8368 u8 reserved_at_10[0x8]; 8369 u8 access_reg_group[0x8]; 8370 8371 u8 reserved_at_20[0x20]; 8372 8373 union { 8374 struct mlx5_ifc_mcam_access_reg_bits access_regs; 8375 u8 reserved_at_0[0x80]; 8376 } mng_access_reg_cap_mask; 8377 8378 u8 reserved_at_c0[0x80]; 8379 8380 union { 8381 struct mlx5_ifc_mcam_enhanced_features_bits enhanced_features; 8382 u8 reserved_at_0[0x80]; 8383 } mng_feature_cap_mask; 8384 8385 u8 reserved_at_1c0[0x80]; 8386 }; 8387 8388 struct mlx5_ifc_qcam_access_reg_cap_mask { 8389 u8 qcam_access_reg_cap_mask_127_to_20[0x6C]; 8390 u8 qpdpm[0x1]; 8391 u8 qcam_access_reg_cap_mask_18_to_4[0x0F]; 8392 u8 qdpm[0x1]; 8393 u8 qpts[0x1]; 8394 u8 qcap[0x1]; 8395 u8 qcam_access_reg_cap_mask_0[0x1]; 8396 }; 8397 8398 struct mlx5_ifc_qcam_qos_feature_cap_mask { 8399 u8 qcam_qos_feature_cap_mask_127_to_1[0x7F]; 8400 u8 qpts_trust_both[0x1]; 8401 }; 8402 8403 struct mlx5_ifc_qcam_reg_bits { 8404 u8 reserved_at_0[0x8]; 8405 u8 feature_group[0x8]; 8406 u8 reserved_at_10[0x8]; 8407 u8 access_reg_group[0x8]; 8408 u8 reserved_at_20[0x20]; 8409 8410 union { 8411 struct mlx5_ifc_qcam_access_reg_cap_mask reg_cap; 8412 u8 reserved_at_0[0x80]; 8413 } qos_access_reg_cap_mask; 8414 8415 u8 reserved_at_c0[0x80]; 8416 8417 union { 8418 struct mlx5_ifc_qcam_qos_feature_cap_mask feature_cap; 8419 u8 reserved_at_0[0x80]; 8420 } qos_feature_cap_mask; 8421 8422 u8 reserved_at_1c0[0x80]; 8423 }; 8424 8425 struct mlx5_ifc_pcap_reg_bits { 8426 u8 reserved_at_0[0x8]; 8427 u8 local_port[0x8]; 8428 u8 reserved_at_10[0x10]; 8429 8430 u8 port_capability_mask[4][0x20]; 8431 }; 8432 8433 struct mlx5_ifc_paos_reg_bits { 8434 u8 swid[0x8]; 8435 u8 local_port[0x8]; 8436 u8 reserved_at_10[0x4]; 8437 u8 admin_status[0x4]; 8438 u8 reserved_at_18[0x4]; 8439 u8 oper_status[0x4]; 8440 8441 u8 ase[0x1]; 8442 u8 ee[0x1]; 8443 u8 reserved_at_22[0x1c]; 8444 u8 e[0x2]; 8445 8446 u8 reserved_at_40[0x40]; 8447 }; 8448 8449 struct mlx5_ifc_pamp_reg_bits { 8450 u8 reserved_at_0[0x8]; 8451 u8 opamp_group[0x8]; 8452 u8 reserved_at_10[0xc]; 8453 u8 opamp_group_type[0x4]; 8454 8455 u8 start_index[0x10]; 8456 u8 reserved_at_30[0x4]; 8457 u8 num_of_indices[0xc]; 8458 8459 u8 index_data[18][0x10]; 8460 }; 8461 8462 struct mlx5_ifc_pcmr_reg_bits { 8463 u8 reserved_at_0[0x8]; 8464 u8 local_port[0x8]; 8465 u8 reserved_at_10[0x2e]; 8466 u8 fcs_cap[0x1]; 8467 u8 reserved_at_3f[0x1f]; 8468 u8 fcs_chk[0x1]; 8469 u8 reserved_at_5f[0x1]; 8470 }; 8471 8472 struct mlx5_ifc_lane_2_module_mapping_bits { 8473 u8 reserved_at_0[0x6]; 8474 u8 rx_lane[0x2]; 8475 u8 reserved_at_8[0x6]; 8476 u8 tx_lane[0x2]; 8477 u8 reserved_at_10[0x8]; 8478 u8 module[0x8]; 8479 }; 8480 8481 struct mlx5_ifc_bufferx_reg_bits { 8482 u8 reserved_at_0[0x6]; 8483 u8 lossy[0x1]; 8484 u8 epsb[0x1]; 8485 u8 reserved_at_8[0xc]; 8486 u8 size[0xc]; 8487 8488 u8 xoff_threshold[0x10]; 8489 u8 xon_threshold[0x10]; 8490 }; 8491 8492 struct mlx5_ifc_set_node_in_bits { 8493 u8 node_description[64][0x8]; 8494 }; 8495 8496 struct mlx5_ifc_register_power_settings_bits { 8497 u8 reserved_at_0[0x18]; 8498 u8 power_settings_level[0x8]; 8499 8500 u8 reserved_at_20[0x60]; 8501 }; 8502 8503 struct mlx5_ifc_register_host_endianness_bits { 8504 u8 he[0x1]; 8505 u8 reserved_at_1[0x1f]; 8506 8507 u8 reserved_at_20[0x60]; 8508 }; 8509 8510 struct mlx5_ifc_umr_pointer_desc_argument_bits { 8511 u8 reserved_at_0[0x20]; 8512 8513 u8 mkey[0x20]; 8514 8515 u8 addressh_63_32[0x20]; 8516 8517 u8 addressl_31_0[0x20]; 8518 }; 8519 8520 struct mlx5_ifc_ud_adrs_vector_bits { 8521 u8 dc_key[0x40]; 8522 8523 u8 ext[0x1]; 8524 u8 reserved_at_41[0x7]; 8525 u8 destination_qp_dct[0x18]; 8526 8527 u8 static_rate[0x4]; 8528 u8 sl_eth_prio[0x4]; 8529 u8 fl[0x1]; 8530 u8 mlid[0x7]; 8531 u8 rlid_udp_sport[0x10]; 8532 8533 u8 reserved_at_80[0x20]; 8534 8535 u8 rmac_47_16[0x20]; 8536 8537 u8 rmac_15_0[0x10]; 8538 u8 tclass[0x8]; 8539 u8 hop_limit[0x8]; 8540 8541 u8 reserved_at_e0[0x1]; 8542 u8 grh[0x1]; 8543 u8 reserved_at_e2[0x2]; 8544 u8 src_addr_index[0x8]; 8545 u8 flow_label[0x14]; 8546 8547 u8 rgid_rip[16][0x8]; 8548 }; 8549 8550 struct mlx5_ifc_pages_req_event_bits { 8551 u8 reserved_at_0[0x10]; 8552 u8 function_id[0x10]; 8553 8554 u8 num_pages[0x20]; 8555 8556 u8 reserved_at_40[0xa0]; 8557 }; 8558 8559 struct mlx5_ifc_eqe_bits { 8560 u8 reserved_at_0[0x8]; 8561 u8 event_type[0x8]; 8562 u8 reserved_at_10[0x8]; 8563 u8 event_sub_type[0x8]; 8564 8565 u8 reserved_at_20[0xe0]; 8566 8567 union mlx5_ifc_event_auto_bits event_data; 8568 8569 u8 reserved_at_1e0[0x10]; 8570 u8 signature[0x8]; 8571 u8 reserved_at_1f8[0x7]; 8572 u8 owner[0x1]; 8573 }; 8574 8575 enum { 8576 MLX5_CMD_QUEUE_ENTRY_TYPE_PCIE_CMD_IF_TRANSPORT = 0x7, 8577 }; 8578 8579 struct mlx5_ifc_cmd_queue_entry_bits { 8580 u8 type[0x8]; 8581 u8 reserved_at_8[0x18]; 8582 8583 u8 input_length[0x20]; 8584 8585 u8 input_mailbox_pointer_63_32[0x20]; 8586 8587 u8 input_mailbox_pointer_31_9[0x17]; 8588 u8 reserved_at_77[0x9]; 8589 8590 u8 command_input_inline_data[16][0x8]; 8591 8592 u8 command_output_inline_data[16][0x8]; 8593 8594 u8 output_mailbox_pointer_63_32[0x20]; 8595 8596 u8 output_mailbox_pointer_31_9[0x17]; 8597 u8 reserved_at_1b7[0x9]; 8598 8599 u8 output_length[0x20]; 8600 8601 u8 token[0x8]; 8602 u8 signature[0x8]; 8603 u8 reserved_at_1f0[0x8]; 8604 u8 status[0x7]; 8605 u8 ownership[0x1]; 8606 }; 8607 8608 struct mlx5_ifc_cmd_out_bits { 8609 u8 status[0x8]; 8610 u8 reserved_at_8[0x18]; 8611 8612 u8 syndrome[0x20]; 8613 8614 u8 command_output[0x20]; 8615 }; 8616 8617 struct mlx5_ifc_cmd_in_bits { 8618 u8 opcode[0x10]; 8619 u8 reserved_at_10[0x10]; 8620 8621 u8 reserved_at_20[0x10]; 8622 u8 op_mod[0x10]; 8623 8624 u8 command[0][0x20]; 8625 }; 8626 8627 struct mlx5_ifc_cmd_if_box_bits { 8628 u8 mailbox_data[512][0x8]; 8629 8630 u8 reserved_at_1000[0x180]; 8631 8632 u8 next_pointer_63_32[0x20]; 8633 8634 u8 next_pointer_31_10[0x16]; 8635 u8 reserved_at_11b6[0xa]; 8636 8637 u8 block_number[0x20]; 8638 8639 u8 reserved_at_11e0[0x8]; 8640 u8 token[0x8]; 8641 u8 ctrl_signature[0x8]; 8642 u8 signature[0x8]; 8643 }; 8644 8645 struct mlx5_ifc_mtt_bits { 8646 u8 ptag_63_32[0x20]; 8647 8648 u8 ptag_31_8[0x18]; 8649 u8 reserved_at_38[0x6]; 8650 u8 wr_en[0x1]; 8651 u8 rd_en[0x1]; 8652 }; 8653 8654 struct mlx5_ifc_query_wol_rol_out_bits { 8655 u8 status[0x8]; 8656 u8 reserved_at_8[0x18]; 8657 8658 u8 syndrome[0x20]; 8659 8660 u8 reserved_at_40[0x10]; 8661 u8 rol_mode[0x8]; 8662 u8 wol_mode[0x8]; 8663 8664 u8 reserved_at_60[0x20]; 8665 }; 8666 8667 struct mlx5_ifc_query_wol_rol_in_bits { 8668 u8 opcode[0x10]; 8669 u8 reserved_at_10[0x10]; 8670 8671 u8 reserved_at_20[0x10]; 8672 u8 op_mod[0x10]; 8673 8674 u8 reserved_at_40[0x40]; 8675 }; 8676 8677 struct mlx5_ifc_set_wol_rol_out_bits { 8678 u8 status[0x8]; 8679 u8 reserved_at_8[0x18]; 8680 8681 u8 syndrome[0x20]; 8682 8683 u8 reserved_at_40[0x40]; 8684 }; 8685 8686 struct mlx5_ifc_set_wol_rol_in_bits { 8687 u8 opcode[0x10]; 8688 u8 reserved_at_10[0x10]; 8689 8690 u8 reserved_at_20[0x10]; 8691 u8 op_mod[0x10]; 8692 8693 u8 rol_mode_valid[0x1]; 8694 u8 wol_mode_valid[0x1]; 8695 u8 reserved_at_42[0xe]; 8696 u8 rol_mode[0x8]; 8697 u8 wol_mode[0x8]; 8698 8699 u8 reserved_at_60[0x20]; 8700 }; 8701 8702 enum { 8703 MLX5_INITIAL_SEG_NIC_INTERFACE_FULL_DRIVER = 0x0, 8704 MLX5_INITIAL_SEG_NIC_INTERFACE_DISABLED = 0x1, 8705 MLX5_INITIAL_SEG_NIC_INTERFACE_NO_DRAM_NIC = 0x2, 8706 }; 8707 8708 enum { 8709 MLX5_INITIAL_SEG_NIC_INTERFACE_SUPPORTED_FULL_DRIVER = 0x0, 8710 MLX5_INITIAL_SEG_NIC_INTERFACE_SUPPORTED_DISABLED = 0x1, 8711 MLX5_INITIAL_SEG_NIC_INTERFACE_SUPPORTED_NO_DRAM_NIC = 0x2, 8712 }; 8713 8714 enum { 8715 MLX5_INITIAL_SEG_HEALTH_SYNDROME_FW_INTERNAL_ERR = 0x1, 8716 MLX5_INITIAL_SEG_HEALTH_SYNDROME_DEAD_IRISC = 0x7, 8717 MLX5_INITIAL_SEG_HEALTH_SYNDROME_HW_FATAL_ERR = 0x8, 8718 MLX5_INITIAL_SEG_HEALTH_SYNDROME_FW_CRC_ERR = 0x9, 8719 MLX5_INITIAL_SEG_HEALTH_SYNDROME_ICM_FETCH_PCI_ERR = 0xa, 8720 MLX5_INITIAL_SEG_HEALTH_SYNDROME_ICM_PAGE_ERR = 0xb, 8721 MLX5_INITIAL_SEG_HEALTH_SYNDROME_ASYNCHRONOUS_EQ_BUF_OVERRUN = 0xc, 8722 MLX5_INITIAL_SEG_HEALTH_SYNDROME_EQ_IN_ERR = 0xd, 8723 MLX5_INITIAL_SEG_HEALTH_SYNDROME_EQ_INV = 0xe, 8724 MLX5_INITIAL_SEG_HEALTH_SYNDROME_FFSER_ERR = 0xf, 8725 MLX5_INITIAL_SEG_HEALTH_SYNDROME_HIGH_TEMP_ERR = 0x10, 8726 }; 8727 8728 struct mlx5_ifc_initial_seg_bits { 8729 u8 fw_rev_minor[0x10]; 8730 u8 fw_rev_major[0x10]; 8731 8732 u8 cmd_interface_rev[0x10]; 8733 u8 fw_rev_subminor[0x10]; 8734 8735 u8 reserved_at_40[0x40]; 8736 8737 u8 cmdq_phy_addr_63_32[0x20]; 8738 8739 u8 cmdq_phy_addr_31_12[0x14]; 8740 u8 reserved_at_b4[0x2]; 8741 u8 nic_interface[0x2]; 8742 u8 log_cmdq_size[0x4]; 8743 u8 log_cmdq_stride[0x4]; 8744 8745 u8 command_doorbell_vector[0x20]; 8746 8747 u8 reserved_at_e0[0xf00]; 8748 8749 u8 initializing[0x1]; 8750 u8 reserved_at_fe1[0x4]; 8751 u8 nic_interface_supported[0x3]; 8752 u8 reserved_at_fe8[0x18]; 8753 8754 struct mlx5_ifc_health_buffer_bits health_buffer; 8755 8756 u8 no_dram_nic_offset[0x20]; 8757 8758 u8 reserved_at_1220[0x6e40]; 8759 8760 u8 reserved_at_8060[0x1f]; 8761 u8 clear_int[0x1]; 8762 8763 u8 health_syndrome[0x8]; 8764 u8 health_counter[0x18]; 8765 8766 u8 reserved_at_80a0[0x17fc0]; 8767 }; 8768 8769 struct mlx5_ifc_mtpps_reg_bits { 8770 u8 reserved_at_0[0xc]; 8771 u8 cap_number_of_pps_pins[0x4]; 8772 u8 reserved_at_10[0x4]; 8773 u8 cap_max_num_of_pps_in_pins[0x4]; 8774 u8 reserved_at_18[0x4]; 8775 u8 cap_max_num_of_pps_out_pins[0x4]; 8776 8777 u8 reserved_at_20[0x24]; 8778 u8 cap_pin_3_mode[0x4]; 8779 u8 reserved_at_48[0x4]; 8780 u8 cap_pin_2_mode[0x4]; 8781 u8 reserved_at_50[0x4]; 8782 u8 cap_pin_1_mode[0x4]; 8783 u8 reserved_at_58[0x4]; 8784 u8 cap_pin_0_mode[0x4]; 8785 8786 u8 reserved_at_60[0x4]; 8787 u8 cap_pin_7_mode[0x4]; 8788 u8 reserved_at_68[0x4]; 8789 u8 cap_pin_6_mode[0x4]; 8790 u8 reserved_at_70[0x4]; 8791 u8 cap_pin_5_mode[0x4]; 8792 u8 reserved_at_78[0x4]; 8793 u8 cap_pin_4_mode[0x4]; 8794 8795 u8 field_select[0x20]; 8796 u8 reserved_at_a0[0x60]; 8797 8798 u8 enable[0x1]; 8799 u8 reserved_at_101[0xb]; 8800 u8 pattern[0x4]; 8801 u8 reserved_at_110[0x4]; 8802 u8 pin_mode[0x4]; 8803 u8 pin[0x8]; 8804 8805 u8 reserved_at_120[0x20]; 8806 8807 u8 time_stamp[0x40]; 8808 8809 u8 out_pulse_duration[0x10]; 8810 u8 out_periodic_adjustment[0x10]; 8811 u8 enhanced_out_periodic_adjustment[0x20]; 8812 8813 u8 reserved_at_1c0[0x20]; 8814 }; 8815 8816 struct mlx5_ifc_mtppse_reg_bits { 8817 u8 reserved_at_0[0x18]; 8818 u8 pin[0x8]; 8819 u8 event_arm[0x1]; 8820 u8 reserved_at_21[0x1b]; 8821 u8 event_generation_mode[0x4]; 8822 u8 reserved_at_40[0x40]; 8823 }; 8824 8825 struct mlx5_ifc_mcqi_cap_bits { 8826 u8 supported_info_bitmask[0x20]; 8827 8828 u8 component_size[0x20]; 8829 8830 u8 max_component_size[0x20]; 8831 8832 u8 log_mcda_word_size[0x4]; 8833 u8 reserved_at_64[0xc]; 8834 u8 mcda_max_write_size[0x10]; 8835 8836 u8 rd_en[0x1]; 8837 u8 reserved_at_81[0x1]; 8838 u8 match_chip_id[0x1]; 8839 u8 match_psid[0x1]; 8840 u8 check_user_timestamp[0x1]; 8841 u8 match_base_guid_mac[0x1]; 8842 u8 reserved_at_86[0x1a]; 8843 }; 8844 8845 struct mlx5_ifc_mcqi_reg_bits { 8846 u8 read_pending_component[0x1]; 8847 u8 reserved_at_1[0xf]; 8848 u8 component_index[0x10]; 8849 8850 u8 reserved_at_20[0x20]; 8851 8852 u8 reserved_at_40[0x1b]; 8853 u8 info_type[0x5]; 8854 8855 u8 info_size[0x20]; 8856 8857 u8 offset[0x20]; 8858 8859 u8 reserved_at_a0[0x10]; 8860 u8 data_size[0x10]; 8861 8862 u8 data[0][0x20]; 8863 }; 8864 8865 struct mlx5_ifc_mcc_reg_bits { 8866 u8 reserved_at_0[0x4]; 8867 u8 time_elapsed_since_last_cmd[0xc]; 8868 u8 reserved_at_10[0x8]; 8869 u8 instruction[0x8]; 8870 8871 u8 reserved_at_20[0x10]; 8872 u8 component_index[0x10]; 8873 8874 u8 reserved_at_40[0x8]; 8875 u8 update_handle[0x18]; 8876 8877 u8 handle_owner_type[0x4]; 8878 u8 handle_owner_host_id[0x4]; 8879 u8 reserved_at_68[0x1]; 8880 u8 control_progress[0x7]; 8881 u8 error_code[0x8]; 8882 u8 reserved_at_78[0x4]; 8883 u8 control_state[0x4]; 8884 8885 u8 component_size[0x20]; 8886 8887 u8 reserved_at_a0[0x60]; 8888 }; 8889 8890 struct mlx5_ifc_mcda_reg_bits { 8891 u8 reserved_at_0[0x8]; 8892 u8 update_handle[0x18]; 8893 8894 u8 offset[0x20]; 8895 8896 u8 reserved_at_40[0x10]; 8897 u8 size[0x10]; 8898 8899 u8 reserved_at_60[0x20]; 8900 8901 u8 data[0][0x20]; 8902 }; 8903 8904 union mlx5_ifc_ports_control_registers_document_bits { 8905 struct mlx5_ifc_bufferx_reg_bits bufferx_reg; 8906 struct mlx5_ifc_eth_2819_cntrs_grp_data_layout_bits eth_2819_cntrs_grp_data_layout; 8907 struct mlx5_ifc_eth_2863_cntrs_grp_data_layout_bits eth_2863_cntrs_grp_data_layout; 8908 struct mlx5_ifc_eth_3635_cntrs_grp_data_layout_bits eth_3635_cntrs_grp_data_layout; 8909 struct mlx5_ifc_eth_802_3_cntrs_grp_data_layout_bits eth_802_3_cntrs_grp_data_layout; 8910 struct mlx5_ifc_eth_extended_cntrs_grp_data_layout_bits eth_extended_cntrs_grp_data_layout; 8911 struct mlx5_ifc_eth_per_prio_grp_data_layout_bits eth_per_prio_grp_data_layout; 8912 struct mlx5_ifc_eth_per_traffic_grp_data_layout_bits eth_per_traffic_grp_data_layout; 8913 struct mlx5_ifc_lane_2_module_mapping_bits lane_2_module_mapping; 8914 struct mlx5_ifc_pamp_reg_bits pamp_reg; 8915 struct mlx5_ifc_paos_reg_bits paos_reg; 8916 struct mlx5_ifc_pcap_reg_bits pcap_reg; 8917 struct mlx5_ifc_peir_reg_bits peir_reg; 8918 struct mlx5_ifc_pelc_reg_bits pelc_reg; 8919 struct mlx5_ifc_pfcc_reg_bits pfcc_reg; 8920 struct mlx5_ifc_ib_port_cntrs_grp_data_layout_bits ib_port_cntrs_grp_data_layout; 8921 struct mlx5_ifc_phys_layer_cntrs_bits phys_layer_cntrs; 8922 struct mlx5_ifc_pifr_reg_bits pifr_reg; 8923 struct mlx5_ifc_pipg_reg_bits pipg_reg; 8924 struct mlx5_ifc_plbf_reg_bits plbf_reg; 8925 struct mlx5_ifc_plib_reg_bits plib_reg; 8926 struct mlx5_ifc_plpc_reg_bits plpc_reg; 8927 struct mlx5_ifc_pmaos_reg_bits pmaos_reg; 8928 struct mlx5_ifc_pmlp_reg_bits pmlp_reg; 8929 struct mlx5_ifc_pmlpn_reg_bits pmlpn_reg; 8930 struct mlx5_ifc_pmpc_reg_bits pmpc_reg; 8931 struct mlx5_ifc_pmpe_reg_bits pmpe_reg; 8932 struct mlx5_ifc_pmpr_reg_bits pmpr_reg; 8933 struct mlx5_ifc_pmtu_reg_bits pmtu_reg; 8934 struct mlx5_ifc_ppad_reg_bits ppad_reg; 8935 struct mlx5_ifc_ppcnt_reg_bits ppcnt_reg; 8936 struct mlx5_ifc_mpcnt_reg_bits mpcnt_reg; 8937 struct mlx5_ifc_pplm_reg_bits pplm_reg; 8938 struct mlx5_ifc_pplr_reg_bits pplr_reg; 8939 struct mlx5_ifc_ppsc_reg_bits ppsc_reg; 8940 struct mlx5_ifc_pqdr_reg_bits pqdr_reg; 8941 struct mlx5_ifc_pspa_reg_bits pspa_reg; 8942 struct mlx5_ifc_ptas_reg_bits ptas_reg; 8943 struct mlx5_ifc_ptys_reg_bits ptys_reg; 8944 struct mlx5_ifc_mlcr_reg_bits mlcr_reg; 8945 struct mlx5_ifc_pude_reg_bits pude_reg; 8946 struct mlx5_ifc_pvlc_reg_bits pvlc_reg; 8947 struct mlx5_ifc_slrg_reg_bits slrg_reg; 8948 struct mlx5_ifc_sltp_reg_bits sltp_reg; 8949 struct mlx5_ifc_mtpps_reg_bits mtpps_reg; 8950 struct mlx5_ifc_mtppse_reg_bits mtppse_reg; 8951 struct mlx5_ifc_fpga_access_reg_bits fpga_access_reg; 8952 struct mlx5_ifc_fpga_ctrl_bits fpga_ctrl_bits; 8953 struct mlx5_ifc_fpga_cap_bits fpga_cap_bits; 8954 struct mlx5_ifc_mcqi_reg_bits mcqi_reg; 8955 struct mlx5_ifc_mcc_reg_bits mcc_reg; 8956 struct mlx5_ifc_mcda_reg_bits mcda_reg; 8957 u8 reserved_at_0[0x60e0]; 8958 }; 8959 8960 union mlx5_ifc_debug_enhancements_document_bits { 8961 struct mlx5_ifc_health_buffer_bits health_buffer; 8962 u8 reserved_at_0[0x200]; 8963 }; 8964 8965 union mlx5_ifc_uplink_pci_interface_document_bits { 8966 struct mlx5_ifc_initial_seg_bits initial_seg; 8967 u8 reserved_at_0[0x20060]; 8968 }; 8969 8970 struct mlx5_ifc_set_flow_table_root_out_bits { 8971 u8 status[0x8]; 8972 u8 reserved_at_8[0x18]; 8973 8974 u8 syndrome[0x20]; 8975 8976 u8 reserved_at_40[0x40]; 8977 }; 8978 8979 struct mlx5_ifc_set_flow_table_root_in_bits { 8980 u8 opcode[0x10]; 8981 u8 reserved_at_10[0x10]; 8982 8983 u8 reserved_at_20[0x10]; 8984 u8 op_mod[0x10]; 8985 8986 u8 other_vport[0x1]; 8987 u8 reserved_at_41[0xf]; 8988 u8 vport_number[0x10]; 8989 8990 u8 reserved_at_60[0x20]; 8991 8992 u8 table_type[0x8]; 8993 u8 reserved_at_88[0x18]; 8994 8995 u8 reserved_at_a0[0x8]; 8996 u8 table_id[0x18]; 8997 8998 u8 reserved_at_c0[0x8]; 8999 u8 underlay_qpn[0x18]; 9000 u8 reserved_at_e0[0x120]; 9001 }; 9002 9003 enum { 9004 MLX5_MODIFY_FLOW_TABLE_MISS_TABLE_ID = (1UL << 0), 9005 MLX5_MODIFY_FLOW_TABLE_LAG_NEXT_TABLE_ID = (1UL << 15), 9006 }; 9007 9008 struct mlx5_ifc_modify_flow_table_out_bits { 9009 u8 status[0x8]; 9010 u8 reserved_at_8[0x18]; 9011 9012 u8 syndrome[0x20]; 9013 9014 u8 reserved_at_40[0x40]; 9015 }; 9016 9017 struct mlx5_ifc_modify_flow_table_in_bits { 9018 u8 opcode[0x10]; 9019 u8 reserved_at_10[0x10]; 9020 9021 u8 reserved_at_20[0x10]; 9022 u8 op_mod[0x10]; 9023 9024 u8 other_vport[0x1]; 9025 u8 reserved_at_41[0xf]; 9026 u8 vport_number[0x10]; 9027 9028 u8 reserved_at_60[0x10]; 9029 u8 modify_field_select[0x10]; 9030 9031 u8 table_type[0x8]; 9032 u8 reserved_at_88[0x18]; 9033 9034 u8 reserved_at_a0[0x8]; 9035 u8 table_id[0x18]; 9036 9037 struct mlx5_ifc_flow_table_context_bits flow_table_context; 9038 }; 9039 9040 struct mlx5_ifc_ets_tcn_config_reg_bits { 9041 u8 g[0x1]; 9042 u8 b[0x1]; 9043 u8 r[0x1]; 9044 u8 reserved_at_3[0x9]; 9045 u8 group[0x4]; 9046 u8 reserved_at_10[0x9]; 9047 u8 bw_allocation[0x7]; 9048 9049 u8 reserved_at_20[0xc]; 9050 u8 max_bw_units[0x4]; 9051 u8 reserved_at_30[0x8]; 9052 u8 max_bw_value[0x8]; 9053 }; 9054 9055 struct mlx5_ifc_ets_global_config_reg_bits { 9056 u8 reserved_at_0[0x2]; 9057 u8 r[0x1]; 9058 u8 reserved_at_3[0x1d]; 9059 9060 u8 reserved_at_20[0xc]; 9061 u8 max_bw_units[0x4]; 9062 u8 reserved_at_30[0x8]; 9063 u8 max_bw_value[0x8]; 9064 }; 9065 9066 struct mlx5_ifc_qetc_reg_bits { 9067 u8 reserved_at_0[0x8]; 9068 u8 port_number[0x8]; 9069 u8 reserved_at_10[0x30]; 9070 9071 struct mlx5_ifc_ets_tcn_config_reg_bits tc_configuration[0x8]; 9072 struct mlx5_ifc_ets_global_config_reg_bits global_configuration; 9073 }; 9074 9075 struct mlx5_ifc_qpdpm_dscp_reg_bits { 9076 u8 e[0x1]; 9077 u8 reserved_at_01[0x0b]; 9078 u8 prio[0x04]; 9079 }; 9080 9081 struct mlx5_ifc_qpdpm_reg_bits { 9082 u8 reserved_at_0[0x8]; 9083 u8 local_port[0x8]; 9084 u8 reserved_at_10[0x10]; 9085 struct mlx5_ifc_qpdpm_dscp_reg_bits dscp[64]; 9086 }; 9087 9088 struct mlx5_ifc_qpts_reg_bits { 9089 u8 reserved_at_0[0x8]; 9090 u8 local_port[0x8]; 9091 u8 reserved_at_10[0x2d]; 9092 u8 trust_state[0x3]; 9093 }; 9094 9095 struct mlx5_ifc_pptb_reg_bits { 9096 u8 reserved_at_0[0x2]; 9097 u8 mm[0x2]; 9098 u8 reserved_at_4[0x4]; 9099 u8 local_port[0x8]; 9100 u8 reserved_at_10[0x6]; 9101 u8 cm[0x1]; 9102 u8 um[0x1]; 9103 u8 pm[0x8]; 9104 9105 u8 prio_x_buff[0x20]; 9106 9107 u8 pm_msb[0x8]; 9108 u8 reserved_at_48[0x10]; 9109 u8 ctrl_buff[0x4]; 9110 u8 untagged_buff[0x4]; 9111 }; 9112 9113 struct mlx5_ifc_pbmc_reg_bits { 9114 u8 reserved_at_0[0x8]; 9115 u8 local_port[0x8]; 9116 u8 reserved_at_10[0x10]; 9117 9118 u8 xoff_timer_value[0x10]; 9119 u8 xoff_refresh[0x10]; 9120 9121 u8 reserved_at_40[0x9]; 9122 u8 fullness_threshold[0x7]; 9123 u8 port_buffer_size[0x10]; 9124 9125 struct mlx5_ifc_bufferx_reg_bits buffer[10]; 9126 9127 u8 reserved_at_2e0[0x40]; 9128 }; 9129 9130 struct mlx5_ifc_qtct_reg_bits { 9131 u8 reserved_at_0[0x8]; 9132 u8 port_number[0x8]; 9133 u8 reserved_at_10[0xd]; 9134 u8 prio[0x3]; 9135 9136 u8 reserved_at_20[0x1d]; 9137 u8 tclass[0x3]; 9138 }; 9139 9140 struct mlx5_ifc_mcia_reg_bits { 9141 u8 l[0x1]; 9142 u8 reserved_at_1[0x7]; 9143 u8 module[0x8]; 9144 u8 reserved_at_10[0x8]; 9145 u8 status[0x8]; 9146 9147 u8 i2c_device_address[0x8]; 9148 u8 page_number[0x8]; 9149 u8 device_address[0x10]; 9150 9151 u8 reserved_at_40[0x10]; 9152 u8 size[0x10]; 9153 9154 u8 reserved_at_60[0x20]; 9155 9156 u8 dword_0[0x20]; 9157 u8 dword_1[0x20]; 9158 u8 dword_2[0x20]; 9159 u8 dword_3[0x20]; 9160 u8 dword_4[0x20]; 9161 u8 dword_5[0x20]; 9162 u8 dword_6[0x20]; 9163 u8 dword_7[0x20]; 9164 u8 dword_8[0x20]; 9165 u8 dword_9[0x20]; 9166 u8 dword_10[0x20]; 9167 u8 dword_11[0x20]; 9168 }; 9169 9170 struct mlx5_ifc_dcbx_param_bits { 9171 u8 dcbx_cee_cap[0x1]; 9172 u8 dcbx_ieee_cap[0x1]; 9173 u8 dcbx_standby_cap[0x1]; 9174 u8 reserved_at_3[0x5]; 9175 u8 port_number[0x8]; 9176 u8 reserved_at_10[0xa]; 9177 u8 max_application_table_size[6]; 9178 u8 reserved_at_20[0x15]; 9179 u8 version_oper[0x3]; 9180 u8 reserved_at_38[5]; 9181 u8 version_admin[0x3]; 9182 u8 willing_admin[0x1]; 9183 u8 reserved_at_41[0x3]; 9184 u8 pfc_cap_oper[0x4]; 9185 u8 reserved_at_48[0x4]; 9186 u8 pfc_cap_admin[0x4]; 9187 u8 reserved_at_50[0x4]; 9188 u8 num_of_tc_oper[0x4]; 9189 u8 reserved_at_58[0x4]; 9190 u8 num_of_tc_admin[0x4]; 9191 u8 remote_willing[0x1]; 9192 u8 reserved_at_61[3]; 9193 u8 remote_pfc_cap[4]; 9194 u8 reserved_at_68[0x14]; 9195 u8 remote_num_of_tc[0x4]; 9196 u8 reserved_at_80[0x18]; 9197 u8 error[0x8]; 9198 u8 reserved_at_a0[0x160]; 9199 }; 9200 9201 struct mlx5_ifc_lagc_bits { 9202 u8 reserved_at_0[0x1d]; 9203 u8 lag_state[0x3]; 9204 9205 u8 reserved_at_20[0x14]; 9206 u8 tx_remap_affinity_2[0x4]; 9207 u8 reserved_at_38[0x4]; 9208 u8 tx_remap_affinity_1[0x4]; 9209 }; 9210 9211 struct mlx5_ifc_create_lag_out_bits { 9212 u8 status[0x8]; 9213 u8 reserved_at_8[0x18]; 9214 9215 u8 syndrome[0x20]; 9216 9217 u8 reserved_at_40[0x40]; 9218 }; 9219 9220 struct mlx5_ifc_create_lag_in_bits { 9221 u8 opcode[0x10]; 9222 u8 reserved_at_10[0x10]; 9223 9224 u8 reserved_at_20[0x10]; 9225 u8 op_mod[0x10]; 9226 9227 struct mlx5_ifc_lagc_bits ctx; 9228 }; 9229 9230 struct mlx5_ifc_modify_lag_out_bits { 9231 u8 status[0x8]; 9232 u8 reserved_at_8[0x18]; 9233 9234 u8 syndrome[0x20]; 9235 9236 u8 reserved_at_40[0x40]; 9237 }; 9238 9239 struct mlx5_ifc_modify_lag_in_bits { 9240 u8 opcode[0x10]; 9241 u8 reserved_at_10[0x10]; 9242 9243 u8 reserved_at_20[0x10]; 9244 u8 op_mod[0x10]; 9245 9246 u8 reserved_at_40[0x20]; 9247 u8 field_select[0x20]; 9248 9249 struct mlx5_ifc_lagc_bits ctx; 9250 }; 9251 9252 struct mlx5_ifc_query_lag_out_bits { 9253 u8 status[0x8]; 9254 u8 reserved_at_8[0x18]; 9255 9256 u8 syndrome[0x20]; 9257 9258 u8 reserved_at_40[0x40]; 9259 9260 struct mlx5_ifc_lagc_bits ctx; 9261 }; 9262 9263 struct mlx5_ifc_query_lag_in_bits { 9264 u8 opcode[0x10]; 9265 u8 reserved_at_10[0x10]; 9266 9267 u8 reserved_at_20[0x10]; 9268 u8 op_mod[0x10]; 9269 9270 u8 reserved_at_40[0x40]; 9271 }; 9272 9273 struct mlx5_ifc_destroy_lag_out_bits { 9274 u8 status[0x8]; 9275 u8 reserved_at_8[0x18]; 9276 9277 u8 syndrome[0x20]; 9278 9279 u8 reserved_at_40[0x40]; 9280 }; 9281 9282 struct mlx5_ifc_destroy_lag_in_bits { 9283 u8 opcode[0x10]; 9284 u8 reserved_at_10[0x10]; 9285 9286 u8 reserved_at_20[0x10]; 9287 u8 op_mod[0x10]; 9288 9289 u8 reserved_at_40[0x40]; 9290 }; 9291 9292 struct mlx5_ifc_create_vport_lag_out_bits { 9293 u8 status[0x8]; 9294 u8 reserved_at_8[0x18]; 9295 9296 u8 syndrome[0x20]; 9297 9298 u8 reserved_at_40[0x40]; 9299 }; 9300 9301 struct mlx5_ifc_create_vport_lag_in_bits { 9302 u8 opcode[0x10]; 9303 u8 reserved_at_10[0x10]; 9304 9305 u8 reserved_at_20[0x10]; 9306 u8 op_mod[0x10]; 9307 9308 u8 reserved_at_40[0x40]; 9309 }; 9310 9311 struct mlx5_ifc_destroy_vport_lag_out_bits { 9312 u8 status[0x8]; 9313 u8 reserved_at_8[0x18]; 9314 9315 u8 syndrome[0x20]; 9316 9317 u8 reserved_at_40[0x40]; 9318 }; 9319 9320 struct mlx5_ifc_destroy_vport_lag_in_bits { 9321 u8 opcode[0x10]; 9322 u8 reserved_at_10[0x10]; 9323 9324 u8 reserved_at_20[0x10]; 9325 u8 op_mod[0x10]; 9326 9327 u8 reserved_at_40[0x40]; 9328 }; 9329 9330 struct mlx5_ifc_alloc_memic_in_bits { 9331 u8 opcode[0x10]; 9332 u8 reserved_at_10[0x10]; 9333 9334 u8 reserved_at_20[0x10]; 9335 u8 op_mod[0x10]; 9336 9337 u8 reserved_at_30[0x20]; 9338 9339 u8 reserved_at_40[0x18]; 9340 u8 log_memic_addr_alignment[0x8]; 9341 9342 u8 range_start_addr[0x40]; 9343 9344 u8 range_size[0x20]; 9345 9346 u8 memic_size[0x20]; 9347 }; 9348 9349 struct mlx5_ifc_alloc_memic_out_bits { 9350 u8 status[0x8]; 9351 u8 reserved_at_8[0x18]; 9352 9353 u8 syndrome[0x20]; 9354 9355 u8 memic_start_addr[0x40]; 9356 }; 9357 9358 struct mlx5_ifc_dealloc_memic_in_bits { 9359 u8 opcode[0x10]; 9360 u8 reserved_at_10[0x10]; 9361 9362 u8 reserved_at_20[0x10]; 9363 u8 op_mod[0x10]; 9364 9365 u8 reserved_at_40[0x40]; 9366 9367 u8 memic_start_addr[0x40]; 9368 9369 u8 memic_size[0x20]; 9370 9371 u8 reserved_at_e0[0x20]; 9372 }; 9373 9374 struct mlx5_ifc_dealloc_memic_out_bits { 9375 u8 status[0x8]; 9376 u8 reserved_at_8[0x18]; 9377 9378 u8 syndrome[0x20]; 9379 9380 u8 reserved_at_40[0x40]; 9381 }; 9382 9383 struct mlx5_ifc_general_obj_in_cmd_hdr_bits { 9384 u8 opcode[0x10]; 9385 u8 uid[0x10]; 9386 9387 u8 reserved_at_20[0x10]; 9388 u8 obj_type[0x10]; 9389 9390 u8 obj_id[0x20]; 9391 9392 u8 reserved_at_60[0x20]; 9393 }; 9394 9395 struct mlx5_ifc_general_obj_out_cmd_hdr_bits { 9396 u8 status[0x8]; 9397 u8 reserved_at_8[0x18]; 9398 9399 u8 syndrome[0x20]; 9400 9401 u8 obj_id[0x20]; 9402 9403 u8 reserved_at_60[0x20]; 9404 }; 9405 9406 struct mlx5_ifc_umem_bits { 9407 u8 reserved_at_0[0x80]; 9408 9409 u8 reserved_at_80[0x1b]; 9410 u8 log_page_size[0x5]; 9411 9412 u8 page_offset[0x20]; 9413 9414 u8 num_of_mtt[0x40]; 9415 9416 struct mlx5_ifc_mtt_bits mtt[0]; 9417 }; 9418 9419 struct mlx5_ifc_uctx_bits { 9420 u8 cap[0x20]; 9421 9422 u8 reserved_at_20[0x160]; 9423 }; 9424 9425 struct mlx5_ifc_create_umem_in_bits { 9426 u8 opcode[0x10]; 9427 u8 uid[0x10]; 9428 9429 u8 reserved_at_20[0x10]; 9430 u8 op_mod[0x10]; 9431 9432 u8 reserved_at_40[0x40]; 9433 9434 struct mlx5_ifc_umem_bits umem; 9435 }; 9436 9437 struct mlx5_ifc_create_uctx_in_bits { 9438 u8 opcode[0x10]; 9439 u8 reserved_at_10[0x10]; 9440 9441 u8 reserved_at_20[0x10]; 9442 u8 op_mod[0x10]; 9443 9444 u8 reserved_at_40[0x40]; 9445 9446 struct mlx5_ifc_uctx_bits uctx; 9447 }; 9448 9449 struct mlx5_ifc_destroy_uctx_in_bits { 9450 u8 opcode[0x10]; 9451 u8 reserved_at_10[0x10]; 9452 9453 u8 reserved_at_20[0x10]; 9454 u8 op_mod[0x10]; 9455 9456 u8 reserved_at_40[0x10]; 9457 u8 uid[0x10]; 9458 9459 u8 reserved_at_60[0x20]; 9460 }; 9461 9462 struct mlx5_ifc_mtrc_string_db_param_bits { 9463 u8 string_db_base_address[0x20]; 9464 9465 u8 reserved_at_20[0x8]; 9466 u8 string_db_size[0x18]; 9467 }; 9468 9469 struct mlx5_ifc_mtrc_cap_bits { 9470 u8 trace_owner[0x1]; 9471 u8 trace_to_memory[0x1]; 9472 u8 reserved_at_2[0x4]; 9473 u8 trc_ver[0x2]; 9474 u8 reserved_at_8[0x14]; 9475 u8 num_string_db[0x4]; 9476 9477 u8 first_string_trace[0x8]; 9478 u8 num_string_trace[0x8]; 9479 u8 reserved_at_30[0x28]; 9480 9481 u8 log_max_trace_buffer_size[0x8]; 9482 9483 u8 reserved_at_60[0x20]; 9484 9485 struct mlx5_ifc_mtrc_string_db_param_bits string_db_param[8]; 9486 9487 u8 reserved_at_280[0x180]; 9488 }; 9489 9490 struct mlx5_ifc_mtrc_conf_bits { 9491 u8 reserved_at_0[0x1c]; 9492 u8 trace_mode[0x4]; 9493 u8 reserved_at_20[0x18]; 9494 u8 log_trace_buffer_size[0x8]; 9495 u8 trace_mkey[0x20]; 9496 u8 reserved_at_60[0x3a0]; 9497 }; 9498 9499 struct mlx5_ifc_mtrc_stdb_bits { 9500 u8 string_db_index[0x4]; 9501 u8 reserved_at_4[0x4]; 9502 u8 read_size[0x18]; 9503 u8 start_offset[0x20]; 9504 u8 string_db_data[0]; 9505 }; 9506 9507 struct mlx5_ifc_mtrc_ctrl_bits { 9508 u8 trace_status[0x2]; 9509 u8 reserved_at_2[0x2]; 9510 u8 arm_event[0x1]; 9511 u8 reserved_at_5[0xb]; 9512 u8 modify_field_select[0x10]; 9513 u8 reserved_at_20[0x2b]; 9514 u8 current_timestamp52_32[0x15]; 9515 u8 current_timestamp31_0[0x20]; 9516 u8 reserved_at_80[0x180]; 9517 }; 9518 9519 #endif /* MLX5_IFC_H */ 9520