1 /* 2 * Copyright (c) 2013-2015, Mellanox Technologies, Ltd. All rights reserved. 3 * 4 * This software is available to you under a choice of one of two 5 * licenses. You may choose to be licensed under the terms of the GNU 6 * General Public License (GPL) Version 2, available from the file 7 * COPYING in the main directory of this source tree, or the 8 * OpenIB.org BSD license below: 9 * 10 * Redistribution and use in source and binary forms, with or 11 * without modification, are permitted provided that the following 12 * conditions are met: 13 * 14 * - Redistributions of source code must retain the above 15 * copyright notice, this list of conditions and the following 16 * disclaimer. 17 * 18 * - Redistributions in binary form must reproduce the above 19 * copyright notice, this list of conditions and the following 20 * disclaimer in the documentation and/or other materials 21 * provided with the distribution. 22 * 23 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, 24 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF 25 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND 26 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS 27 * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN 28 * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN 29 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE 30 * SOFTWARE. 31 */ 32 #ifndef MLX5_IFC_H 33 #define MLX5_IFC_H 34 35 #include "mlx5_ifc_fpga.h" 36 37 enum { 38 MLX5_EVENT_TYPE_CODING_COMPLETION_EVENTS = 0x0, 39 MLX5_EVENT_TYPE_CODING_PATH_MIGRATED_SUCCEEDED = 0x1, 40 MLX5_EVENT_TYPE_CODING_COMMUNICATION_ESTABLISHED = 0x2, 41 MLX5_EVENT_TYPE_CODING_SEND_QUEUE_DRAINED = 0x3, 42 MLX5_EVENT_TYPE_CODING_LAST_WQE_REACHED = 0x13, 43 MLX5_EVENT_TYPE_CODING_SRQ_LIMIT = 0x14, 44 MLX5_EVENT_TYPE_CODING_DCT_ALL_CONNECTIONS_CLOSED = 0x1c, 45 MLX5_EVENT_TYPE_CODING_DCT_ACCESS_KEY_VIOLATION = 0x1d, 46 MLX5_EVENT_TYPE_CODING_CQ_ERROR = 0x4, 47 MLX5_EVENT_TYPE_CODING_LOCAL_WQ_CATASTROPHIC_ERROR = 0x5, 48 MLX5_EVENT_TYPE_CODING_PATH_MIGRATION_FAILED = 0x7, 49 MLX5_EVENT_TYPE_CODING_PAGE_FAULT_EVENT = 0xc, 50 MLX5_EVENT_TYPE_CODING_INVALID_REQUEST_LOCAL_WQ_ERROR = 0x10, 51 MLX5_EVENT_TYPE_CODING_LOCAL_ACCESS_VIOLATION_WQ_ERROR = 0x11, 52 MLX5_EVENT_TYPE_CODING_LOCAL_SRQ_CATASTROPHIC_ERROR = 0x12, 53 MLX5_EVENT_TYPE_CODING_INTERNAL_ERROR = 0x8, 54 MLX5_EVENT_TYPE_CODING_PORT_STATE_CHANGE = 0x9, 55 MLX5_EVENT_TYPE_CODING_GPIO_EVENT = 0x15, 56 MLX5_EVENT_TYPE_CODING_REMOTE_CONFIGURATION_PROTOCOL_EVENT = 0x19, 57 MLX5_EVENT_TYPE_CODING_DOORBELL_BLUEFLAME_CONGESTION_EVENT = 0x1a, 58 MLX5_EVENT_TYPE_CODING_STALL_VL_EVENT = 0x1b, 59 MLX5_EVENT_TYPE_CODING_DROPPED_PACKET_LOGGED_EVENT = 0x1f, 60 MLX5_EVENT_TYPE_CODING_COMMAND_INTERFACE_COMPLETION = 0xa, 61 MLX5_EVENT_TYPE_CODING_PAGE_REQUEST = 0xb, 62 MLX5_EVENT_TYPE_CODING_FPGA_ERROR = 0x20, 63 }; 64 65 enum { 66 MLX5_MODIFY_TIR_BITMASK_LRO = 0x0, 67 MLX5_MODIFY_TIR_BITMASK_INDIRECT_TABLE = 0x1, 68 MLX5_MODIFY_TIR_BITMASK_HASH = 0x2, 69 MLX5_MODIFY_TIR_BITMASK_TUNNELED_OFFLOAD_EN = 0x3 70 }; 71 72 enum { 73 MLX5_SET_HCA_CAP_OP_MOD_GENERAL_DEVICE = 0x0, 74 MLX5_SET_HCA_CAP_OP_MOD_ATOMIC = 0x3, 75 }; 76 77 enum { 78 MLX5_CMD_OP_QUERY_HCA_CAP = 0x100, 79 MLX5_CMD_OP_QUERY_ADAPTER = 0x101, 80 MLX5_CMD_OP_INIT_HCA = 0x102, 81 MLX5_CMD_OP_TEARDOWN_HCA = 0x103, 82 MLX5_CMD_OP_ENABLE_HCA = 0x104, 83 MLX5_CMD_OP_DISABLE_HCA = 0x105, 84 MLX5_CMD_OP_QUERY_PAGES = 0x107, 85 MLX5_CMD_OP_MANAGE_PAGES = 0x108, 86 MLX5_CMD_OP_SET_HCA_CAP = 0x109, 87 MLX5_CMD_OP_QUERY_ISSI = 0x10a, 88 MLX5_CMD_OP_SET_ISSI = 0x10b, 89 MLX5_CMD_OP_SET_DRIVER_VERSION = 0x10d, 90 MLX5_CMD_OP_CREATE_MKEY = 0x200, 91 MLX5_CMD_OP_QUERY_MKEY = 0x201, 92 MLX5_CMD_OP_DESTROY_MKEY = 0x202, 93 MLX5_CMD_OP_QUERY_SPECIAL_CONTEXTS = 0x203, 94 MLX5_CMD_OP_PAGE_FAULT_RESUME = 0x204, 95 MLX5_CMD_OP_CREATE_EQ = 0x301, 96 MLX5_CMD_OP_DESTROY_EQ = 0x302, 97 MLX5_CMD_OP_QUERY_EQ = 0x303, 98 MLX5_CMD_OP_GEN_EQE = 0x304, 99 MLX5_CMD_OP_CREATE_CQ = 0x400, 100 MLX5_CMD_OP_DESTROY_CQ = 0x401, 101 MLX5_CMD_OP_QUERY_CQ = 0x402, 102 MLX5_CMD_OP_MODIFY_CQ = 0x403, 103 MLX5_CMD_OP_CREATE_QP = 0x500, 104 MLX5_CMD_OP_DESTROY_QP = 0x501, 105 MLX5_CMD_OP_RST2INIT_QP = 0x502, 106 MLX5_CMD_OP_INIT2RTR_QP = 0x503, 107 MLX5_CMD_OP_RTR2RTS_QP = 0x504, 108 MLX5_CMD_OP_RTS2RTS_QP = 0x505, 109 MLX5_CMD_OP_SQERR2RTS_QP = 0x506, 110 MLX5_CMD_OP_2ERR_QP = 0x507, 111 MLX5_CMD_OP_2RST_QP = 0x50a, 112 MLX5_CMD_OP_QUERY_QP = 0x50b, 113 MLX5_CMD_OP_SQD_RTS_QP = 0x50c, 114 MLX5_CMD_OP_INIT2INIT_QP = 0x50e, 115 MLX5_CMD_OP_CREATE_PSV = 0x600, 116 MLX5_CMD_OP_DESTROY_PSV = 0x601, 117 MLX5_CMD_OP_CREATE_SRQ = 0x700, 118 MLX5_CMD_OP_DESTROY_SRQ = 0x701, 119 MLX5_CMD_OP_QUERY_SRQ = 0x702, 120 MLX5_CMD_OP_ARM_RQ = 0x703, 121 MLX5_CMD_OP_CREATE_XRC_SRQ = 0x705, 122 MLX5_CMD_OP_DESTROY_XRC_SRQ = 0x706, 123 MLX5_CMD_OP_QUERY_XRC_SRQ = 0x707, 124 MLX5_CMD_OP_ARM_XRC_SRQ = 0x708, 125 MLX5_CMD_OP_CREATE_DCT = 0x710, 126 MLX5_CMD_OP_DESTROY_DCT = 0x711, 127 MLX5_CMD_OP_DRAIN_DCT = 0x712, 128 MLX5_CMD_OP_QUERY_DCT = 0x713, 129 MLX5_CMD_OP_ARM_DCT_FOR_KEY_VIOLATION = 0x714, 130 MLX5_CMD_OP_CREATE_XRQ = 0x717, 131 MLX5_CMD_OP_DESTROY_XRQ = 0x718, 132 MLX5_CMD_OP_QUERY_XRQ = 0x719, 133 MLX5_CMD_OP_ARM_XRQ = 0x71a, 134 MLX5_CMD_OP_QUERY_VPORT_STATE = 0x750, 135 MLX5_CMD_OP_MODIFY_VPORT_STATE = 0x751, 136 MLX5_CMD_OP_QUERY_ESW_VPORT_CONTEXT = 0x752, 137 MLX5_CMD_OP_MODIFY_ESW_VPORT_CONTEXT = 0x753, 138 MLX5_CMD_OP_QUERY_NIC_VPORT_CONTEXT = 0x754, 139 MLX5_CMD_OP_MODIFY_NIC_VPORT_CONTEXT = 0x755, 140 MLX5_CMD_OP_QUERY_ROCE_ADDRESS = 0x760, 141 MLX5_CMD_OP_SET_ROCE_ADDRESS = 0x761, 142 MLX5_CMD_OP_QUERY_HCA_VPORT_CONTEXT = 0x762, 143 MLX5_CMD_OP_MODIFY_HCA_VPORT_CONTEXT = 0x763, 144 MLX5_CMD_OP_QUERY_HCA_VPORT_GID = 0x764, 145 MLX5_CMD_OP_QUERY_HCA_VPORT_PKEY = 0x765, 146 MLX5_CMD_OP_QUERY_VPORT_COUNTER = 0x770, 147 MLX5_CMD_OP_ALLOC_Q_COUNTER = 0x771, 148 MLX5_CMD_OP_DEALLOC_Q_COUNTER = 0x772, 149 MLX5_CMD_OP_QUERY_Q_COUNTER = 0x773, 150 MLX5_CMD_OP_SET_PP_RATE_LIMIT = 0x780, 151 MLX5_CMD_OP_QUERY_RATE_LIMIT = 0x781, 152 MLX5_CMD_OP_CREATE_SCHEDULING_ELEMENT = 0x782, 153 MLX5_CMD_OP_DESTROY_SCHEDULING_ELEMENT = 0x783, 154 MLX5_CMD_OP_QUERY_SCHEDULING_ELEMENT = 0x784, 155 MLX5_CMD_OP_MODIFY_SCHEDULING_ELEMENT = 0x785, 156 MLX5_CMD_OP_CREATE_QOS_PARA_VPORT = 0x786, 157 MLX5_CMD_OP_DESTROY_QOS_PARA_VPORT = 0x787, 158 MLX5_CMD_OP_ALLOC_PD = 0x800, 159 MLX5_CMD_OP_DEALLOC_PD = 0x801, 160 MLX5_CMD_OP_ALLOC_UAR = 0x802, 161 MLX5_CMD_OP_DEALLOC_UAR = 0x803, 162 MLX5_CMD_OP_CONFIG_INT_MODERATION = 0x804, 163 MLX5_CMD_OP_ACCESS_REG = 0x805, 164 MLX5_CMD_OP_ATTACH_TO_MCG = 0x806, 165 MLX5_CMD_OP_DETACH_FROM_MCG = 0x807, 166 MLX5_CMD_OP_GET_DROPPED_PACKET_LOG = 0x80a, 167 MLX5_CMD_OP_MAD_IFC = 0x50d, 168 MLX5_CMD_OP_QUERY_MAD_DEMUX = 0x80b, 169 MLX5_CMD_OP_SET_MAD_DEMUX = 0x80c, 170 MLX5_CMD_OP_NOP = 0x80d, 171 MLX5_CMD_OP_ALLOC_XRCD = 0x80e, 172 MLX5_CMD_OP_DEALLOC_XRCD = 0x80f, 173 MLX5_CMD_OP_ALLOC_TRANSPORT_DOMAIN = 0x816, 174 MLX5_CMD_OP_DEALLOC_TRANSPORT_DOMAIN = 0x817, 175 MLX5_CMD_OP_QUERY_CONG_STATUS = 0x822, 176 MLX5_CMD_OP_MODIFY_CONG_STATUS = 0x823, 177 MLX5_CMD_OP_QUERY_CONG_PARAMS = 0x824, 178 MLX5_CMD_OP_MODIFY_CONG_PARAMS = 0x825, 179 MLX5_CMD_OP_QUERY_CONG_STATISTICS = 0x826, 180 MLX5_CMD_OP_ADD_VXLAN_UDP_DPORT = 0x827, 181 MLX5_CMD_OP_DELETE_VXLAN_UDP_DPORT = 0x828, 182 MLX5_CMD_OP_SET_L2_TABLE_ENTRY = 0x829, 183 MLX5_CMD_OP_QUERY_L2_TABLE_ENTRY = 0x82a, 184 MLX5_CMD_OP_DELETE_L2_TABLE_ENTRY = 0x82b, 185 MLX5_CMD_OP_SET_WOL_ROL = 0x830, 186 MLX5_CMD_OP_QUERY_WOL_ROL = 0x831, 187 MLX5_CMD_OP_CREATE_LAG = 0x840, 188 MLX5_CMD_OP_MODIFY_LAG = 0x841, 189 MLX5_CMD_OP_QUERY_LAG = 0x842, 190 MLX5_CMD_OP_DESTROY_LAG = 0x843, 191 MLX5_CMD_OP_CREATE_VPORT_LAG = 0x844, 192 MLX5_CMD_OP_DESTROY_VPORT_LAG = 0x845, 193 MLX5_CMD_OP_CREATE_TIR = 0x900, 194 MLX5_CMD_OP_MODIFY_TIR = 0x901, 195 MLX5_CMD_OP_DESTROY_TIR = 0x902, 196 MLX5_CMD_OP_QUERY_TIR = 0x903, 197 MLX5_CMD_OP_CREATE_SQ = 0x904, 198 MLX5_CMD_OP_MODIFY_SQ = 0x905, 199 MLX5_CMD_OP_DESTROY_SQ = 0x906, 200 MLX5_CMD_OP_QUERY_SQ = 0x907, 201 MLX5_CMD_OP_CREATE_RQ = 0x908, 202 MLX5_CMD_OP_MODIFY_RQ = 0x909, 203 MLX5_CMD_OP_SET_DELAY_DROP_PARAMS = 0x910, 204 MLX5_CMD_OP_DESTROY_RQ = 0x90a, 205 MLX5_CMD_OP_QUERY_RQ = 0x90b, 206 MLX5_CMD_OP_CREATE_RMP = 0x90c, 207 MLX5_CMD_OP_MODIFY_RMP = 0x90d, 208 MLX5_CMD_OP_DESTROY_RMP = 0x90e, 209 MLX5_CMD_OP_QUERY_RMP = 0x90f, 210 MLX5_CMD_OP_CREATE_TIS = 0x912, 211 MLX5_CMD_OP_MODIFY_TIS = 0x913, 212 MLX5_CMD_OP_DESTROY_TIS = 0x914, 213 MLX5_CMD_OP_QUERY_TIS = 0x915, 214 MLX5_CMD_OP_CREATE_RQT = 0x916, 215 MLX5_CMD_OP_MODIFY_RQT = 0x917, 216 MLX5_CMD_OP_DESTROY_RQT = 0x918, 217 MLX5_CMD_OP_QUERY_RQT = 0x919, 218 MLX5_CMD_OP_SET_FLOW_TABLE_ROOT = 0x92f, 219 MLX5_CMD_OP_CREATE_FLOW_TABLE = 0x930, 220 MLX5_CMD_OP_DESTROY_FLOW_TABLE = 0x931, 221 MLX5_CMD_OP_QUERY_FLOW_TABLE = 0x932, 222 MLX5_CMD_OP_CREATE_FLOW_GROUP = 0x933, 223 MLX5_CMD_OP_DESTROY_FLOW_GROUP = 0x934, 224 MLX5_CMD_OP_QUERY_FLOW_GROUP = 0x935, 225 MLX5_CMD_OP_SET_FLOW_TABLE_ENTRY = 0x936, 226 MLX5_CMD_OP_QUERY_FLOW_TABLE_ENTRY = 0x937, 227 MLX5_CMD_OP_DELETE_FLOW_TABLE_ENTRY = 0x938, 228 MLX5_CMD_OP_ALLOC_FLOW_COUNTER = 0x939, 229 MLX5_CMD_OP_DEALLOC_FLOW_COUNTER = 0x93a, 230 MLX5_CMD_OP_QUERY_FLOW_COUNTER = 0x93b, 231 MLX5_CMD_OP_MODIFY_FLOW_TABLE = 0x93c, 232 MLX5_CMD_OP_ALLOC_ENCAP_HEADER = 0x93d, 233 MLX5_CMD_OP_DEALLOC_ENCAP_HEADER = 0x93e, 234 MLX5_CMD_OP_ALLOC_MODIFY_HEADER_CONTEXT = 0x940, 235 MLX5_CMD_OP_DEALLOC_MODIFY_HEADER_CONTEXT = 0x941, 236 MLX5_CMD_OP_FPGA_CREATE_QP = 0x960, 237 MLX5_CMD_OP_FPGA_MODIFY_QP = 0x961, 238 MLX5_CMD_OP_FPGA_QUERY_QP = 0x962, 239 MLX5_CMD_OP_FPGA_DESTROY_QP = 0x963, 240 MLX5_CMD_OP_FPGA_QUERY_QP_COUNTERS = 0x964, 241 MLX5_CMD_OP_MAX 242 }; 243 244 struct mlx5_ifc_flow_table_fields_supported_bits { 245 u8 outer_dmac[0x1]; 246 u8 outer_smac[0x1]; 247 u8 outer_ether_type[0x1]; 248 u8 outer_ip_version[0x1]; 249 u8 outer_first_prio[0x1]; 250 u8 outer_first_cfi[0x1]; 251 u8 outer_first_vid[0x1]; 252 u8 outer_ipv4_ttl[0x1]; 253 u8 outer_second_prio[0x1]; 254 u8 outer_second_cfi[0x1]; 255 u8 outer_second_vid[0x1]; 256 u8 reserved_at_b[0x1]; 257 u8 outer_sip[0x1]; 258 u8 outer_dip[0x1]; 259 u8 outer_frag[0x1]; 260 u8 outer_ip_protocol[0x1]; 261 u8 outer_ip_ecn[0x1]; 262 u8 outer_ip_dscp[0x1]; 263 u8 outer_udp_sport[0x1]; 264 u8 outer_udp_dport[0x1]; 265 u8 outer_tcp_sport[0x1]; 266 u8 outer_tcp_dport[0x1]; 267 u8 outer_tcp_flags[0x1]; 268 u8 outer_gre_protocol[0x1]; 269 u8 outer_gre_key[0x1]; 270 u8 outer_vxlan_vni[0x1]; 271 u8 reserved_at_1a[0x5]; 272 u8 source_eswitch_port[0x1]; 273 274 u8 inner_dmac[0x1]; 275 u8 inner_smac[0x1]; 276 u8 inner_ether_type[0x1]; 277 u8 inner_ip_version[0x1]; 278 u8 inner_first_prio[0x1]; 279 u8 inner_first_cfi[0x1]; 280 u8 inner_first_vid[0x1]; 281 u8 reserved_at_27[0x1]; 282 u8 inner_second_prio[0x1]; 283 u8 inner_second_cfi[0x1]; 284 u8 inner_second_vid[0x1]; 285 u8 reserved_at_2b[0x1]; 286 u8 inner_sip[0x1]; 287 u8 inner_dip[0x1]; 288 u8 inner_frag[0x1]; 289 u8 inner_ip_protocol[0x1]; 290 u8 inner_ip_ecn[0x1]; 291 u8 inner_ip_dscp[0x1]; 292 u8 inner_udp_sport[0x1]; 293 u8 inner_udp_dport[0x1]; 294 u8 inner_tcp_sport[0x1]; 295 u8 inner_tcp_dport[0x1]; 296 u8 inner_tcp_flags[0x1]; 297 u8 reserved_at_37[0x9]; 298 u8 reserved_at_40[0x1a]; 299 u8 bth_dst_qp[0x1]; 300 301 u8 reserved_at_5b[0x25]; 302 }; 303 304 struct mlx5_ifc_flow_table_prop_layout_bits { 305 u8 ft_support[0x1]; 306 u8 reserved_at_1[0x1]; 307 u8 flow_counter[0x1]; 308 u8 flow_modify_en[0x1]; 309 u8 modify_root[0x1]; 310 u8 identified_miss_table_mode[0x1]; 311 u8 flow_table_modify[0x1]; 312 u8 encap[0x1]; 313 u8 decap[0x1]; 314 u8 reserved_at_9[0x17]; 315 316 u8 reserved_at_20[0x2]; 317 u8 log_max_ft_size[0x6]; 318 u8 log_max_modify_header_context[0x8]; 319 u8 max_modify_header_actions[0x8]; 320 u8 max_ft_level[0x8]; 321 322 u8 reserved_at_40[0x20]; 323 324 u8 reserved_at_60[0x18]; 325 u8 log_max_ft_num[0x8]; 326 327 u8 reserved_at_80[0x18]; 328 u8 log_max_destination[0x8]; 329 330 u8 log_max_flow_counter[0x8]; 331 u8 reserved_at_a8[0x10]; 332 u8 log_max_flow[0x8]; 333 334 u8 reserved_at_c0[0x40]; 335 336 struct mlx5_ifc_flow_table_fields_supported_bits ft_field_support; 337 338 struct mlx5_ifc_flow_table_fields_supported_bits ft_field_bitmask_support; 339 }; 340 341 struct mlx5_ifc_odp_per_transport_service_cap_bits { 342 u8 send[0x1]; 343 u8 receive[0x1]; 344 u8 write[0x1]; 345 u8 read[0x1]; 346 u8 atomic[0x1]; 347 u8 srq_receive[0x1]; 348 u8 reserved_at_6[0x1a]; 349 }; 350 351 struct mlx5_ifc_ipv4_layout_bits { 352 u8 reserved_at_0[0x60]; 353 354 u8 ipv4[0x20]; 355 }; 356 357 struct mlx5_ifc_ipv6_layout_bits { 358 u8 ipv6[16][0x8]; 359 }; 360 361 union mlx5_ifc_ipv6_layout_ipv4_layout_auto_bits { 362 struct mlx5_ifc_ipv6_layout_bits ipv6_layout; 363 struct mlx5_ifc_ipv4_layout_bits ipv4_layout; 364 u8 reserved_at_0[0x80]; 365 }; 366 367 struct mlx5_ifc_fte_match_set_lyr_2_4_bits { 368 u8 smac_47_16[0x20]; 369 370 u8 smac_15_0[0x10]; 371 u8 ethertype[0x10]; 372 373 u8 dmac_47_16[0x20]; 374 375 u8 dmac_15_0[0x10]; 376 u8 first_prio[0x3]; 377 u8 first_cfi[0x1]; 378 u8 first_vid[0xc]; 379 380 u8 ip_protocol[0x8]; 381 u8 ip_dscp[0x6]; 382 u8 ip_ecn[0x2]; 383 u8 cvlan_tag[0x1]; 384 u8 svlan_tag[0x1]; 385 u8 frag[0x1]; 386 u8 ip_version[0x4]; 387 u8 tcp_flags[0x9]; 388 389 u8 tcp_sport[0x10]; 390 u8 tcp_dport[0x10]; 391 392 u8 reserved_at_c0[0x18]; 393 u8 ttl_hoplimit[0x8]; 394 395 u8 udp_sport[0x10]; 396 u8 udp_dport[0x10]; 397 398 union mlx5_ifc_ipv6_layout_ipv4_layout_auto_bits src_ipv4_src_ipv6; 399 400 union mlx5_ifc_ipv6_layout_ipv4_layout_auto_bits dst_ipv4_dst_ipv6; 401 }; 402 403 struct mlx5_ifc_fte_match_set_misc_bits { 404 u8 reserved_at_0[0x8]; 405 u8 source_sqn[0x18]; 406 407 u8 reserved_at_20[0x10]; 408 u8 source_port[0x10]; 409 410 u8 outer_second_prio[0x3]; 411 u8 outer_second_cfi[0x1]; 412 u8 outer_second_vid[0xc]; 413 u8 inner_second_prio[0x3]; 414 u8 inner_second_cfi[0x1]; 415 u8 inner_second_vid[0xc]; 416 417 u8 outer_second_cvlan_tag[0x1]; 418 u8 inner_second_cvlan_tag[0x1]; 419 u8 outer_second_svlan_tag[0x1]; 420 u8 inner_second_svlan_tag[0x1]; 421 u8 reserved_at_64[0xc]; 422 u8 gre_protocol[0x10]; 423 424 u8 gre_key_h[0x18]; 425 u8 gre_key_l[0x8]; 426 427 u8 vxlan_vni[0x18]; 428 u8 reserved_at_b8[0x8]; 429 430 u8 reserved_at_c0[0x20]; 431 432 u8 reserved_at_e0[0xc]; 433 u8 outer_ipv6_flow_label[0x14]; 434 435 u8 reserved_at_100[0xc]; 436 u8 inner_ipv6_flow_label[0x14]; 437 438 u8 reserved_at_120[0x28]; 439 u8 bth_dst_qp[0x18]; 440 u8 reserved_at_160[0xa0]; 441 }; 442 443 struct mlx5_ifc_cmd_pas_bits { 444 u8 pa_h[0x20]; 445 446 u8 pa_l[0x14]; 447 u8 reserved_at_34[0xc]; 448 }; 449 450 struct mlx5_ifc_uint64_bits { 451 u8 hi[0x20]; 452 453 u8 lo[0x20]; 454 }; 455 456 enum { 457 MLX5_ADS_STAT_RATE_NO_LIMIT = 0x0, 458 MLX5_ADS_STAT_RATE_2_5GBPS = 0x7, 459 MLX5_ADS_STAT_RATE_10GBPS = 0x8, 460 MLX5_ADS_STAT_RATE_30GBPS = 0x9, 461 MLX5_ADS_STAT_RATE_5GBPS = 0xa, 462 MLX5_ADS_STAT_RATE_20GBPS = 0xb, 463 MLX5_ADS_STAT_RATE_40GBPS = 0xc, 464 MLX5_ADS_STAT_RATE_60GBPS = 0xd, 465 MLX5_ADS_STAT_RATE_80GBPS = 0xe, 466 MLX5_ADS_STAT_RATE_120GBPS = 0xf, 467 }; 468 469 struct mlx5_ifc_ads_bits { 470 u8 fl[0x1]; 471 u8 free_ar[0x1]; 472 u8 reserved_at_2[0xe]; 473 u8 pkey_index[0x10]; 474 475 u8 reserved_at_20[0x8]; 476 u8 grh[0x1]; 477 u8 mlid[0x7]; 478 u8 rlid[0x10]; 479 480 u8 ack_timeout[0x5]; 481 u8 reserved_at_45[0x3]; 482 u8 src_addr_index[0x8]; 483 u8 reserved_at_50[0x4]; 484 u8 stat_rate[0x4]; 485 u8 hop_limit[0x8]; 486 487 u8 reserved_at_60[0x4]; 488 u8 tclass[0x8]; 489 u8 flow_label[0x14]; 490 491 u8 rgid_rip[16][0x8]; 492 493 u8 reserved_at_100[0x4]; 494 u8 f_dscp[0x1]; 495 u8 f_ecn[0x1]; 496 u8 reserved_at_106[0x1]; 497 u8 f_eth_prio[0x1]; 498 u8 ecn[0x2]; 499 u8 dscp[0x6]; 500 u8 udp_sport[0x10]; 501 502 u8 dei_cfi[0x1]; 503 u8 eth_prio[0x3]; 504 u8 sl[0x4]; 505 u8 port[0x8]; 506 u8 rmac_47_32[0x10]; 507 508 u8 rmac_31_0[0x20]; 509 }; 510 511 struct mlx5_ifc_flow_table_nic_cap_bits { 512 u8 nic_rx_multi_path_tirs[0x1]; 513 u8 nic_rx_multi_path_tirs_fts[0x1]; 514 u8 allow_sniffer_and_nic_rx_shared_tir[0x1]; 515 u8 reserved_at_3[0x1fd]; 516 517 struct mlx5_ifc_flow_table_prop_layout_bits flow_table_properties_nic_receive; 518 519 u8 reserved_at_400[0x200]; 520 521 struct mlx5_ifc_flow_table_prop_layout_bits flow_table_properties_nic_receive_sniffer; 522 523 struct mlx5_ifc_flow_table_prop_layout_bits flow_table_properties_nic_transmit; 524 525 u8 reserved_at_a00[0x200]; 526 527 struct mlx5_ifc_flow_table_prop_layout_bits flow_table_properties_nic_transmit_sniffer; 528 529 u8 reserved_at_e00[0x7200]; 530 }; 531 532 struct mlx5_ifc_flow_table_eswitch_cap_bits { 533 u8 reserved_at_0[0x200]; 534 535 struct mlx5_ifc_flow_table_prop_layout_bits flow_table_properties_nic_esw_fdb; 536 537 struct mlx5_ifc_flow_table_prop_layout_bits flow_table_properties_esw_acl_ingress; 538 539 struct mlx5_ifc_flow_table_prop_layout_bits flow_table_properties_esw_acl_egress; 540 541 u8 reserved_at_800[0x7800]; 542 }; 543 544 struct mlx5_ifc_e_switch_cap_bits { 545 u8 vport_svlan_strip[0x1]; 546 u8 vport_cvlan_strip[0x1]; 547 u8 vport_svlan_insert[0x1]; 548 u8 vport_cvlan_insert_if_not_exist[0x1]; 549 u8 vport_cvlan_insert_overwrite[0x1]; 550 u8 reserved_at_5[0x19]; 551 u8 nic_vport_node_guid_modify[0x1]; 552 u8 nic_vport_port_guid_modify[0x1]; 553 554 u8 vxlan_encap_decap[0x1]; 555 u8 nvgre_encap_decap[0x1]; 556 u8 reserved_at_22[0x9]; 557 u8 log_max_encap_headers[0x5]; 558 u8 reserved_2b[0x6]; 559 u8 max_encap_header_size[0xa]; 560 561 u8 reserved_40[0x7c0]; 562 563 }; 564 565 struct mlx5_ifc_qos_cap_bits { 566 u8 packet_pacing[0x1]; 567 u8 esw_scheduling[0x1]; 568 u8 esw_bw_share[0x1]; 569 u8 esw_rate_limit[0x1]; 570 u8 reserved_at_4[0x1c]; 571 572 u8 reserved_at_20[0x20]; 573 574 u8 packet_pacing_max_rate[0x20]; 575 576 u8 packet_pacing_min_rate[0x20]; 577 578 u8 reserved_at_80[0x10]; 579 u8 packet_pacing_rate_table_size[0x10]; 580 581 u8 esw_element_type[0x10]; 582 u8 esw_tsar_type[0x10]; 583 584 u8 reserved_at_c0[0x10]; 585 u8 max_qos_para_vport[0x10]; 586 587 u8 max_tsar_bw_share[0x20]; 588 589 u8 reserved_at_100[0x700]; 590 }; 591 592 struct mlx5_ifc_per_protocol_networking_offload_caps_bits { 593 u8 csum_cap[0x1]; 594 u8 vlan_cap[0x1]; 595 u8 lro_cap[0x1]; 596 u8 lro_psh_flag[0x1]; 597 u8 lro_time_stamp[0x1]; 598 u8 reserved_at_5[0x2]; 599 u8 wqe_vlan_insert[0x1]; 600 u8 self_lb_en_modifiable[0x1]; 601 u8 reserved_at_9[0x2]; 602 u8 max_lso_cap[0x5]; 603 u8 multi_pkt_send_wqe[0x2]; 604 u8 wqe_inline_mode[0x2]; 605 u8 rss_ind_tbl_cap[0x4]; 606 u8 reg_umr_sq[0x1]; 607 u8 scatter_fcs[0x1]; 608 u8 enhanced_multi_pkt_send_wqe[0x1]; 609 u8 tunnel_lso_const_out_ip_id[0x1]; 610 u8 reserved_at_1c[0x2]; 611 u8 tunnel_stateless_gre[0x1]; 612 u8 tunnel_stateless_vxlan[0x1]; 613 614 u8 swp[0x1]; 615 u8 swp_csum[0x1]; 616 u8 swp_lso[0x1]; 617 u8 reserved_at_23[0x1b]; 618 u8 max_geneve_opt_len[0x1]; 619 u8 tunnel_stateless_geneve_rx[0x1]; 620 621 u8 reserved_at_40[0x10]; 622 u8 lro_min_mss_size[0x10]; 623 624 u8 reserved_at_60[0x120]; 625 626 u8 lro_timer_supported_periods[4][0x20]; 627 628 u8 reserved_at_200[0x600]; 629 }; 630 631 struct mlx5_ifc_roce_cap_bits { 632 u8 roce_apm[0x1]; 633 u8 reserved_at_1[0x1f]; 634 635 u8 reserved_at_20[0x60]; 636 637 u8 reserved_at_80[0xc]; 638 u8 l3_type[0x4]; 639 u8 reserved_at_90[0x8]; 640 u8 roce_version[0x8]; 641 642 u8 reserved_at_a0[0x10]; 643 u8 r_roce_dest_udp_port[0x10]; 644 645 u8 r_roce_max_src_udp_port[0x10]; 646 u8 r_roce_min_src_udp_port[0x10]; 647 648 u8 reserved_at_e0[0x10]; 649 u8 roce_address_table_size[0x10]; 650 651 u8 reserved_at_100[0x700]; 652 }; 653 654 enum { 655 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_QP_1_BYTE = 0x0, 656 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_QP_2_BYTES = 0x2, 657 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_QP_4_BYTES = 0x4, 658 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_QP_8_BYTES = 0x8, 659 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_QP_16_BYTES = 0x10, 660 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_QP_32_BYTES = 0x20, 661 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_QP_64_BYTES = 0x40, 662 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_QP_128_BYTES = 0x80, 663 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_QP_256_BYTES = 0x100, 664 }; 665 666 enum { 667 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_DC_1_BYTE = 0x1, 668 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_DC_2_BYTES = 0x2, 669 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_DC_4_BYTES = 0x4, 670 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_DC_8_BYTES = 0x8, 671 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_DC_16_BYTES = 0x10, 672 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_DC_32_BYTES = 0x20, 673 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_DC_64_BYTES = 0x40, 674 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_DC_128_BYTES = 0x80, 675 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_DC_256_BYTES = 0x100, 676 }; 677 678 struct mlx5_ifc_atomic_caps_bits { 679 u8 reserved_at_0[0x40]; 680 681 u8 atomic_req_8B_endianness_mode[0x2]; 682 u8 reserved_at_42[0x4]; 683 u8 supported_atomic_req_8B_endianness_mode_1[0x1]; 684 685 u8 reserved_at_47[0x19]; 686 687 u8 reserved_at_60[0x20]; 688 689 u8 reserved_at_80[0x10]; 690 u8 atomic_operations[0x10]; 691 692 u8 reserved_at_a0[0x10]; 693 u8 atomic_size_qp[0x10]; 694 695 u8 reserved_at_c0[0x10]; 696 u8 atomic_size_dc[0x10]; 697 698 u8 reserved_at_e0[0x720]; 699 }; 700 701 struct mlx5_ifc_odp_cap_bits { 702 u8 reserved_at_0[0x40]; 703 704 u8 sig[0x1]; 705 u8 reserved_at_41[0x1f]; 706 707 u8 reserved_at_60[0x20]; 708 709 struct mlx5_ifc_odp_per_transport_service_cap_bits rc_odp_caps; 710 711 struct mlx5_ifc_odp_per_transport_service_cap_bits uc_odp_caps; 712 713 struct mlx5_ifc_odp_per_transport_service_cap_bits ud_odp_caps; 714 715 u8 reserved_at_e0[0x720]; 716 }; 717 718 struct mlx5_ifc_calc_op { 719 u8 reserved_at_0[0x10]; 720 u8 reserved_at_10[0x9]; 721 u8 op_swap_endianness[0x1]; 722 u8 op_min[0x1]; 723 u8 op_xor[0x1]; 724 u8 op_or[0x1]; 725 u8 op_and[0x1]; 726 u8 op_max[0x1]; 727 u8 op_add[0x1]; 728 }; 729 730 struct mlx5_ifc_vector_calc_cap_bits { 731 u8 calc_matrix[0x1]; 732 u8 reserved_at_1[0x1f]; 733 u8 reserved_at_20[0x8]; 734 u8 max_vec_count[0x8]; 735 u8 reserved_at_30[0xd]; 736 u8 max_chunk_size[0x3]; 737 struct mlx5_ifc_calc_op calc0; 738 struct mlx5_ifc_calc_op calc1; 739 struct mlx5_ifc_calc_op calc2; 740 struct mlx5_ifc_calc_op calc3; 741 742 u8 reserved_at_e0[0x720]; 743 }; 744 745 enum { 746 MLX5_WQ_TYPE_LINKED_LIST = 0x0, 747 MLX5_WQ_TYPE_CYCLIC = 0x1, 748 MLX5_WQ_TYPE_LINKED_LIST_STRIDING_RQ = 0x2, 749 MLX5_WQ_TYPE_CYCLIC_STRIDING_RQ = 0x3, 750 }; 751 752 enum { 753 MLX5_WQ_END_PAD_MODE_NONE = 0x0, 754 MLX5_WQ_END_PAD_MODE_ALIGN = 0x1, 755 }; 756 757 enum { 758 MLX5_CMD_HCA_CAP_GID_TABLE_SIZE_8_GID_ENTRIES = 0x0, 759 MLX5_CMD_HCA_CAP_GID_TABLE_SIZE_16_GID_ENTRIES = 0x1, 760 MLX5_CMD_HCA_CAP_GID_TABLE_SIZE_32_GID_ENTRIES = 0x2, 761 MLX5_CMD_HCA_CAP_GID_TABLE_SIZE_64_GID_ENTRIES = 0x3, 762 MLX5_CMD_HCA_CAP_GID_TABLE_SIZE_128_GID_ENTRIES = 0x4, 763 }; 764 765 enum { 766 MLX5_CMD_HCA_CAP_PKEY_TABLE_SIZE_128_ENTRIES = 0x0, 767 MLX5_CMD_HCA_CAP_PKEY_TABLE_SIZE_256_ENTRIES = 0x1, 768 MLX5_CMD_HCA_CAP_PKEY_TABLE_SIZE_512_ENTRIES = 0x2, 769 MLX5_CMD_HCA_CAP_PKEY_TABLE_SIZE_1K_ENTRIES = 0x3, 770 MLX5_CMD_HCA_CAP_PKEY_TABLE_SIZE_2K_ENTRIES = 0x4, 771 MLX5_CMD_HCA_CAP_PKEY_TABLE_SIZE_4K_ENTRIES = 0x5, 772 }; 773 774 enum { 775 MLX5_CMD_HCA_CAP_PORT_TYPE_IB = 0x0, 776 MLX5_CMD_HCA_CAP_PORT_TYPE_ETHERNET = 0x1, 777 }; 778 779 enum { 780 MLX5_CMD_HCA_CAP_CMDIF_CHECKSUM_DISABLED = 0x0, 781 MLX5_CMD_HCA_CAP_CMDIF_CHECKSUM_INITIAL_STATE = 0x1, 782 MLX5_CMD_HCA_CAP_CMDIF_CHECKSUM_ENABLED = 0x3, 783 }; 784 785 enum { 786 MLX5_CAP_PORT_TYPE_IB = 0x0, 787 MLX5_CAP_PORT_TYPE_ETH = 0x1, 788 }; 789 790 enum { 791 MLX5_CAP_UMR_FENCE_STRONG = 0x0, 792 MLX5_CAP_UMR_FENCE_SMALL = 0x1, 793 MLX5_CAP_UMR_FENCE_NONE = 0x2, 794 }; 795 796 struct mlx5_ifc_cmd_hca_cap_bits { 797 u8 reserved_at_0[0x80]; 798 799 u8 log_max_srq_sz[0x8]; 800 u8 log_max_qp_sz[0x8]; 801 u8 reserved_at_90[0xb]; 802 u8 log_max_qp[0x5]; 803 804 u8 reserved_at_a0[0xb]; 805 u8 log_max_srq[0x5]; 806 u8 reserved_at_b0[0x10]; 807 808 u8 reserved_at_c0[0x8]; 809 u8 log_max_cq_sz[0x8]; 810 u8 reserved_at_d0[0xb]; 811 u8 log_max_cq[0x5]; 812 813 u8 log_max_eq_sz[0x8]; 814 u8 reserved_at_e8[0x2]; 815 u8 log_max_mkey[0x6]; 816 u8 reserved_at_f0[0xc]; 817 u8 log_max_eq[0x4]; 818 819 u8 max_indirection[0x8]; 820 u8 fixed_buffer_size[0x1]; 821 u8 log_max_mrw_sz[0x7]; 822 u8 force_teardown[0x1]; 823 u8 reserved_at_111[0x1]; 824 u8 log_max_bsf_list_size[0x6]; 825 u8 umr_extended_translation_offset[0x1]; 826 u8 null_mkey[0x1]; 827 u8 log_max_klm_list_size[0x6]; 828 829 u8 reserved_at_120[0xa]; 830 u8 log_max_ra_req_dc[0x6]; 831 u8 reserved_at_130[0xa]; 832 u8 log_max_ra_res_dc[0x6]; 833 834 u8 reserved_at_140[0xa]; 835 u8 log_max_ra_req_qp[0x6]; 836 u8 reserved_at_150[0xa]; 837 u8 log_max_ra_res_qp[0x6]; 838 839 u8 end_pad[0x1]; 840 u8 cc_query_allowed[0x1]; 841 u8 cc_modify_allowed[0x1]; 842 u8 start_pad[0x1]; 843 u8 cache_line_128byte[0x1]; 844 u8 reserved_at_165[0xa]; 845 u8 qcam_reg[0x1]; 846 u8 gid_table_size[0x10]; 847 848 u8 out_of_seq_cnt[0x1]; 849 u8 vport_counters[0x1]; 850 u8 retransmission_q_counters[0x1]; 851 u8 reserved_at_183[0x1]; 852 u8 modify_rq_counter_set_id[0x1]; 853 u8 rq_delay_drop[0x1]; 854 u8 max_qp_cnt[0xa]; 855 u8 pkey_table_size[0x10]; 856 857 u8 vport_group_manager[0x1]; 858 u8 vhca_group_manager[0x1]; 859 u8 ib_virt[0x1]; 860 u8 eth_virt[0x1]; 861 u8 reserved_at_1a4[0x1]; 862 u8 ets[0x1]; 863 u8 nic_flow_table[0x1]; 864 u8 eswitch_flow_table[0x1]; 865 u8 early_vf_enable[0x1]; 866 u8 mcam_reg[0x1]; 867 u8 pcam_reg[0x1]; 868 u8 local_ca_ack_delay[0x5]; 869 u8 port_module_event[0x1]; 870 u8 enhanced_error_q_counters[0x1]; 871 u8 ports_check[0x1]; 872 u8 reserved_at_1b3[0x1]; 873 u8 disable_link_up[0x1]; 874 u8 beacon_led[0x1]; 875 u8 port_type[0x2]; 876 u8 num_ports[0x8]; 877 878 u8 reserved_at_1c0[0x1]; 879 u8 pps[0x1]; 880 u8 pps_modify[0x1]; 881 u8 log_max_msg[0x5]; 882 u8 reserved_at_1c8[0x4]; 883 u8 max_tc[0x4]; 884 u8 reserved_at_1d0[0x1]; 885 u8 dcbx[0x1]; 886 u8 general_notification_event[0x1]; 887 u8 reserved_at_1d3[0x2]; 888 u8 fpga[0x1]; 889 u8 rol_s[0x1]; 890 u8 rol_g[0x1]; 891 u8 reserved_at_1d8[0x1]; 892 u8 wol_s[0x1]; 893 u8 wol_g[0x1]; 894 u8 wol_a[0x1]; 895 u8 wol_b[0x1]; 896 u8 wol_m[0x1]; 897 u8 wol_u[0x1]; 898 u8 wol_p[0x1]; 899 900 u8 stat_rate_support[0x10]; 901 u8 reserved_at_1f0[0xc]; 902 u8 cqe_version[0x4]; 903 904 u8 compact_address_vector[0x1]; 905 u8 striding_rq[0x1]; 906 u8 reserved_at_202[0x1]; 907 u8 ipoib_enhanced_offloads[0x1]; 908 u8 ipoib_basic_offloads[0x1]; 909 u8 reserved_at_205[0x5]; 910 u8 umr_fence[0x2]; 911 u8 reserved_at_20c[0x3]; 912 u8 drain_sigerr[0x1]; 913 u8 cmdif_checksum[0x2]; 914 u8 sigerr_cqe[0x1]; 915 u8 reserved_at_213[0x1]; 916 u8 wq_signature[0x1]; 917 u8 sctr_data_cqe[0x1]; 918 u8 reserved_at_216[0x1]; 919 u8 sho[0x1]; 920 u8 tph[0x1]; 921 u8 rf[0x1]; 922 u8 dct[0x1]; 923 u8 qos[0x1]; 924 u8 eth_net_offloads[0x1]; 925 u8 roce[0x1]; 926 u8 atomic[0x1]; 927 u8 reserved_at_21f[0x1]; 928 929 u8 cq_oi[0x1]; 930 u8 cq_resize[0x1]; 931 u8 cq_moderation[0x1]; 932 u8 reserved_at_223[0x3]; 933 u8 cq_eq_remap[0x1]; 934 u8 pg[0x1]; 935 u8 block_lb_mc[0x1]; 936 u8 reserved_at_229[0x1]; 937 u8 scqe_break_moderation[0x1]; 938 u8 cq_period_start_from_cqe[0x1]; 939 u8 cd[0x1]; 940 u8 reserved_at_22d[0x1]; 941 u8 apm[0x1]; 942 u8 vector_calc[0x1]; 943 u8 umr_ptr_rlky[0x1]; 944 u8 imaicl[0x1]; 945 u8 reserved_at_232[0x4]; 946 u8 qkv[0x1]; 947 u8 pkv[0x1]; 948 u8 set_deth_sqpn[0x1]; 949 u8 reserved_at_239[0x3]; 950 u8 xrc[0x1]; 951 u8 ud[0x1]; 952 u8 uc[0x1]; 953 u8 rc[0x1]; 954 955 u8 uar_4k[0x1]; 956 u8 reserved_at_241[0x9]; 957 u8 uar_sz[0x6]; 958 u8 reserved_at_250[0x8]; 959 u8 log_pg_sz[0x8]; 960 961 u8 bf[0x1]; 962 u8 driver_version[0x1]; 963 u8 pad_tx_eth_packet[0x1]; 964 u8 reserved_at_263[0x8]; 965 u8 log_bf_reg_size[0x5]; 966 967 u8 reserved_at_270[0xb]; 968 u8 lag_master[0x1]; 969 u8 num_lag_ports[0x4]; 970 971 u8 reserved_at_280[0x10]; 972 u8 max_wqe_sz_sq[0x10]; 973 974 u8 reserved_at_2a0[0x10]; 975 u8 max_wqe_sz_rq[0x10]; 976 977 u8 max_flow_counter_31_16[0x10]; 978 u8 max_wqe_sz_sq_dc[0x10]; 979 980 u8 reserved_at_2e0[0x7]; 981 u8 max_qp_mcg[0x19]; 982 983 u8 reserved_at_300[0x18]; 984 u8 log_max_mcg[0x8]; 985 986 u8 reserved_at_320[0x3]; 987 u8 log_max_transport_domain[0x5]; 988 u8 reserved_at_328[0x3]; 989 u8 log_max_pd[0x5]; 990 u8 reserved_at_330[0xb]; 991 u8 log_max_xrcd[0x5]; 992 993 u8 reserved_at_340[0x8]; 994 u8 log_max_flow_counter_bulk[0x8]; 995 u8 max_flow_counter_15_0[0x10]; 996 997 998 u8 reserved_at_360[0x3]; 999 u8 log_max_rq[0x5]; 1000 u8 reserved_at_368[0x3]; 1001 u8 log_max_sq[0x5]; 1002 u8 reserved_at_370[0x3]; 1003 u8 log_max_tir[0x5]; 1004 u8 reserved_at_378[0x3]; 1005 u8 log_max_tis[0x5]; 1006 1007 u8 basic_cyclic_rcv_wqe[0x1]; 1008 u8 reserved_at_381[0x2]; 1009 u8 log_max_rmp[0x5]; 1010 u8 reserved_at_388[0x3]; 1011 u8 log_max_rqt[0x5]; 1012 u8 reserved_at_390[0x3]; 1013 u8 log_max_rqt_size[0x5]; 1014 u8 reserved_at_398[0x3]; 1015 u8 log_max_tis_per_sq[0x5]; 1016 1017 u8 reserved_at_3a0[0x3]; 1018 u8 log_max_stride_sz_rq[0x5]; 1019 u8 reserved_at_3a8[0x3]; 1020 u8 log_min_stride_sz_rq[0x5]; 1021 u8 reserved_at_3b0[0x3]; 1022 u8 log_max_stride_sz_sq[0x5]; 1023 u8 reserved_at_3b8[0x3]; 1024 u8 log_min_stride_sz_sq[0x5]; 1025 1026 u8 reserved_at_3c0[0x1b]; 1027 u8 log_max_wq_sz[0x5]; 1028 1029 u8 nic_vport_change_event[0x1]; 1030 u8 disable_local_lb_uc[0x1]; 1031 u8 disable_local_lb_mc[0x1]; 1032 u8 reserved_at_3e3[0x8]; 1033 u8 log_max_vlan_list[0x5]; 1034 u8 reserved_at_3f0[0x3]; 1035 u8 log_max_current_mc_list[0x5]; 1036 u8 reserved_at_3f8[0x3]; 1037 u8 log_max_current_uc_list[0x5]; 1038 1039 u8 reserved_at_400[0x80]; 1040 1041 u8 reserved_at_480[0x3]; 1042 u8 log_max_l2_table[0x5]; 1043 u8 reserved_at_488[0x8]; 1044 u8 log_uar_page_sz[0x10]; 1045 1046 u8 reserved_at_4a0[0x20]; 1047 u8 device_frequency_mhz[0x20]; 1048 u8 device_frequency_khz[0x20]; 1049 1050 u8 reserved_at_500[0x20]; 1051 u8 num_of_uars_per_page[0x20]; 1052 u8 reserved_at_540[0x40]; 1053 1054 u8 reserved_at_580[0x3d]; 1055 u8 cqe_128_always[0x1]; 1056 u8 cqe_compression_128[0x1]; 1057 u8 cqe_compression[0x1]; 1058 1059 u8 cqe_compression_timeout[0x10]; 1060 u8 cqe_compression_max_num[0x10]; 1061 1062 u8 reserved_at_5e0[0x10]; 1063 u8 tag_matching[0x1]; 1064 u8 rndv_offload_rc[0x1]; 1065 u8 rndv_offload_dc[0x1]; 1066 u8 log_tag_matching_list_sz[0x5]; 1067 u8 reserved_at_5f8[0x3]; 1068 u8 log_max_xrq[0x5]; 1069 1070 u8 reserved_at_600[0x200]; 1071 }; 1072 1073 enum mlx5_flow_destination_type { 1074 MLX5_FLOW_DESTINATION_TYPE_VPORT = 0x0, 1075 MLX5_FLOW_DESTINATION_TYPE_FLOW_TABLE = 0x1, 1076 MLX5_FLOW_DESTINATION_TYPE_TIR = 0x2, 1077 1078 MLX5_FLOW_DESTINATION_TYPE_COUNTER = 0x100, 1079 }; 1080 1081 struct mlx5_ifc_dest_format_struct_bits { 1082 u8 destination_type[0x8]; 1083 u8 destination_id[0x18]; 1084 1085 u8 reserved_at_20[0x20]; 1086 }; 1087 1088 struct mlx5_ifc_flow_counter_list_bits { 1089 u8 flow_counter_id[0x20]; 1090 1091 u8 reserved_at_20[0x20]; 1092 }; 1093 1094 union mlx5_ifc_dest_format_struct_flow_counter_list_auto_bits { 1095 struct mlx5_ifc_dest_format_struct_bits dest_format_struct; 1096 struct mlx5_ifc_flow_counter_list_bits flow_counter_list; 1097 u8 reserved_at_0[0x40]; 1098 }; 1099 1100 struct mlx5_ifc_fte_match_param_bits { 1101 struct mlx5_ifc_fte_match_set_lyr_2_4_bits outer_headers; 1102 1103 struct mlx5_ifc_fte_match_set_misc_bits misc_parameters; 1104 1105 struct mlx5_ifc_fte_match_set_lyr_2_4_bits inner_headers; 1106 1107 u8 reserved_at_600[0xa00]; 1108 }; 1109 1110 enum { 1111 MLX5_RX_HASH_FIELD_SELECT_SELECTED_FIELDS_SRC_IP = 0x0, 1112 MLX5_RX_HASH_FIELD_SELECT_SELECTED_FIELDS_DST_IP = 0x1, 1113 MLX5_RX_HASH_FIELD_SELECT_SELECTED_FIELDS_L4_SPORT = 0x2, 1114 MLX5_RX_HASH_FIELD_SELECT_SELECTED_FIELDS_L4_DPORT = 0x3, 1115 MLX5_RX_HASH_FIELD_SELECT_SELECTED_FIELDS_IPSEC_SPI = 0x4, 1116 }; 1117 1118 struct mlx5_ifc_rx_hash_field_select_bits { 1119 u8 l3_prot_type[0x1]; 1120 u8 l4_prot_type[0x1]; 1121 u8 selected_fields[0x1e]; 1122 }; 1123 1124 enum { 1125 MLX5_WQ_WQ_TYPE_WQ_LINKED_LIST = 0x0, 1126 MLX5_WQ_WQ_TYPE_WQ_CYCLIC = 0x1, 1127 }; 1128 1129 enum { 1130 MLX5_WQ_END_PADDING_MODE_END_PAD_NONE = 0x0, 1131 MLX5_WQ_END_PADDING_MODE_END_PAD_ALIGN = 0x1, 1132 }; 1133 1134 struct mlx5_ifc_wq_bits { 1135 u8 wq_type[0x4]; 1136 u8 wq_signature[0x1]; 1137 u8 end_padding_mode[0x2]; 1138 u8 cd_slave[0x1]; 1139 u8 reserved_at_8[0x18]; 1140 1141 u8 hds_skip_first_sge[0x1]; 1142 u8 log2_hds_buf_size[0x3]; 1143 u8 reserved_at_24[0x7]; 1144 u8 page_offset[0x5]; 1145 u8 lwm[0x10]; 1146 1147 u8 reserved_at_40[0x8]; 1148 u8 pd[0x18]; 1149 1150 u8 reserved_at_60[0x8]; 1151 u8 uar_page[0x18]; 1152 1153 u8 dbr_addr[0x40]; 1154 1155 u8 hw_counter[0x20]; 1156 1157 u8 sw_counter[0x20]; 1158 1159 u8 reserved_at_100[0xc]; 1160 u8 log_wq_stride[0x4]; 1161 u8 reserved_at_110[0x3]; 1162 u8 log_wq_pg_sz[0x5]; 1163 u8 reserved_at_118[0x3]; 1164 u8 log_wq_sz[0x5]; 1165 1166 u8 reserved_at_120[0x15]; 1167 u8 log_wqe_num_of_strides[0x3]; 1168 u8 two_byte_shift_en[0x1]; 1169 u8 reserved_at_139[0x4]; 1170 u8 log_wqe_stride_size[0x3]; 1171 1172 u8 reserved_at_140[0x4c0]; 1173 1174 struct mlx5_ifc_cmd_pas_bits pas[0]; 1175 }; 1176 1177 struct mlx5_ifc_rq_num_bits { 1178 u8 reserved_at_0[0x8]; 1179 u8 rq_num[0x18]; 1180 }; 1181 1182 struct mlx5_ifc_mac_address_layout_bits { 1183 u8 reserved_at_0[0x10]; 1184 u8 mac_addr_47_32[0x10]; 1185 1186 u8 mac_addr_31_0[0x20]; 1187 }; 1188 1189 struct mlx5_ifc_vlan_layout_bits { 1190 u8 reserved_at_0[0x14]; 1191 u8 vlan[0x0c]; 1192 1193 u8 reserved_at_20[0x20]; 1194 }; 1195 1196 struct mlx5_ifc_cong_control_r_roce_ecn_np_bits { 1197 u8 reserved_at_0[0xa0]; 1198 1199 u8 min_time_between_cnps[0x20]; 1200 1201 u8 reserved_at_c0[0x12]; 1202 u8 cnp_dscp[0x6]; 1203 u8 reserved_at_d8[0x4]; 1204 u8 cnp_prio_mode[0x1]; 1205 u8 cnp_802p_prio[0x3]; 1206 1207 u8 reserved_at_e0[0x720]; 1208 }; 1209 1210 struct mlx5_ifc_cong_control_r_roce_ecn_rp_bits { 1211 u8 reserved_at_0[0x60]; 1212 1213 u8 reserved_at_60[0x4]; 1214 u8 clamp_tgt_rate[0x1]; 1215 u8 reserved_at_65[0x3]; 1216 u8 clamp_tgt_rate_after_time_inc[0x1]; 1217 u8 reserved_at_69[0x17]; 1218 1219 u8 reserved_at_80[0x20]; 1220 1221 u8 rpg_time_reset[0x20]; 1222 1223 u8 rpg_byte_reset[0x20]; 1224 1225 u8 rpg_threshold[0x20]; 1226 1227 u8 rpg_max_rate[0x20]; 1228 1229 u8 rpg_ai_rate[0x20]; 1230 1231 u8 rpg_hai_rate[0x20]; 1232 1233 u8 rpg_gd[0x20]; 1234 1235 u8 rpg_min_dec_fac[0x20]; 1236 1237 u8 rpg_min_rate[0x20]; 1238 1239 u8 reserved_at_1c0[0xe0]; 1240 1241 u8 rate_to_set_on_first_cnp[0x20]; 1242 1243 u8 dce_tcp_g[0x20]; 1244 1245 u8 dce_tcp_rtt[0x20]; 1246 1247 u8 rate_reduce_monitor_period[0x20]; 1248 1249 u8 reserved_at_320[0x20]; 1250 1251 u8 initial_alpha_value[0x20]; 1252 1253 u8 reserved_at_360[0x4a0]; 1254 }; 1255 1256 struct mlx5_ifc_cong_control_802_1qau_rp_bits { 1257 u8 reserved_at_0[0x80]; 1258 1259 u8 rppp_max_rps[0x20]; 1260 1261 u8 rpg_time_reset[0x20]; 1262 1263 u8 rpg_byte_reset[0x20]; 1264 1265 u8 rpg_threshold[0x20]; 1266 1267 u8 rpg_max_rate[0x20]; 1268 1269 u8 rpg_ai_rate[0x20]; 1270 1271 u8 rpg_hai_rate[0x20]; 1272 1273 u8 rpg_gd[0x20]; 1274 1275 u8 rpg_min_dec_fac[0x20]; 1276 1277 u8 rpg_min_rate[0x20]; 1278 1279 u8 reserved_at_1c0[0x640]; 1280 }; 1281 1282 enum { 1283 MLX5_RESIZE_FIELD_SELECT_RESIZE_FIELD_SELECT_LOG_CQ_SIZE = 0x1, 1284 MLX5_RESIZE_FIELD_SELECT_RESIZE_FIELD_SELECT_PAGE_OFFSET = 0x2, 1285 MLX5_RESIZE_FIELD_SELECT_RESIZE_FIELD_SELECT_LOG_PAGE_SIZE = 0x4, 1286 }; 1287 1288 struct mlx5_ifc_resize_field_select_bits { 1289 u8 resize_field_select[0x20]; 1290 }; 1291 1292 enum { 1293 MLX5_MODIFY_FIELD_SELECT_MODIFY_FIELD_SELECT_CQ_PERIOD = 0x1, 1294 MLX5_MODIFY_FIELD_SELECT_MODIFY_FIELD_SELECT_CQ_MAX_COUNT = 0x2, 1295 MLX5_MODIFY_FIELD_SELECT_MODIFY_FIELD_SELECT_OI = 0x4, 1296 MLX5_MODIFY_FIELD_SELECT_MODIFY_FIELD_SELECT_C_EQN = 0x8, 1297 }; 1298 1299 struct mlx5_ifc_modify_field_select_bits { 1300 u8 modify_field_select[0x20]; 1301 }; 1302 1303 struct mlx5_ifc_field_select_r_roce_np_bits { 1304 u8 field_select_r_roce_np[0x20]; 1305 }; 1306 1307 struct mlx5_ifc_field_select_r_roce_rp_bits { 1308 u8 field_select_r_roce_rp[0x20]; 1309 }; 1310 1311 enum { 1312 MLX5_FIELD_SELECT_802_1QAU_RP_FIELD_SELECT_8021QAURP_RPPP_MAX_RPS = 0x4, 1313 MLX5_FIELD_SELECT_802_1QAU_RP_FIELD_SELECT_8021QAURP_RPG_TIME_RESET = 0x8, 1314 MLX5_FIELD_SELECT_802_1QAU_RP_FIELD_SELECT_8021QAURP_RPG_BYTE_RESET = 0x10, 1315 MLX5_FIELD_SELECT_802_1QAU_RP_FIELD_SELECT_8021QAURP_RPG_THRESHOLD = 0x20, 1316 MLX5_FIELD_SELECT_802_1QAU_RP_FIELD_SELECT_8021QAURP_RPG_MAX_RATE = 0x40, 1317 MLX5_FIELD_SELECT_802_1QAU_RP_FIELD_SELECT_8021QAURP_RPG_AI_RATE = 0x80, 1318 MLX5_FIELD_SELECT_802_1QAU_RP_FIELD_SELECT_8021QAURP_RPG_HAI_RATE = 0x100, 1319 MLX5_FIELD_SELECT_802_1QAU_RP_FIELD_SELECT_8021QAURP_RPG_GD = 0x200, 1320 MLX5_FIELD_SELECT_802_1QAU_RP_FIELD_SELECT_8021QAURP_RPG_MIN_DEC_FAC = 0x400, 1321 MLX5_FIELD_SELECT_802_1QAU_RP_FIELD_SELECT_8021QAURP_RPG_MIN_RATE = 0x800, 1322 }; 1323 1324 struct mlx5_ifc_field_select_802_1qau_rp_bits { 1325 u8 field_select_8021qaurp[0x20]; 1326 }; 1327 1328 struct mlx5_ifc_phys_layer_cntrs_bits { 1329 u8 time_since_last_clear_high[0x20]; 1330 1331 u8 time_since_last_clear_low[0x20]; 1332 1333 u8 symbol_errors_high[0x20]; 1334 1335 u8 symbol_errors_low[0x20]; 1336 1337 u8 sync_headers_errors_high[0x20]; 1338 1339 u8 sync_headers_errors_low[0x20]; 1340 1341 u8 edpl_bip_errors_lane0_high[0x20]; 1342 1343 u8 edpl_bip_errors_lane0_low[0x20]; 1344 1345 u8 edpl_bip_errors_lane1_high[0x20]; 1346 1347 u8 edpl_bip_errors_lane1_low[0x20]; 1348 1349 u8 edpl_bip_errors_lane2_high[0x20]; 1350 1351 u8 edpl_bip_errors_lane2_low[0x20]; 1352 1353 u8 edpl_bip_errors_lane3_high[0x20]; 1354 1355 u8 edpl_bip_errors_lane3_low[0x20]; 1356 1357 u8 fc_fec_corrected_blocks_lane0_high[0x20]; 1358 1359 u8 fc_fec_corrected_blocks_lane0_low[0x20]; 1360 1361 u8 fc_fec_corrected_blocks_lane1_high[0x20]; 1362 1363 u8 fc_fec_corrected_blocks_lane1_low[0x20]; 1364 1365 u8 fc_fec_corrected_blocks_lane2_high[0x20]; 1366 1367 u8 fc_fec_corrected_blocks_lane2_low[0x20]; 1368 1369 u8 fc_fec_corrected_blocks_lane3_high[0x20]; 1370 1371 u8 fc_fec_corrected_blocks_lane3_low[0x20]; 1372 1373 u8 fc_fec_uncorrectable_blocks_lane0_high[0x20]; 1374 1375 u8 fc_fec_uncorrectable_blocks_lane0_low[0x20]; 1376 1377 u8 fc_fec_uncorrectable_blocks_lane1_high[0x20]; 1378 1379 u8 fc_fec_uncorrectable_blocks_lane1_low[0x20]; 1380 1381 u8 fc_fec_uncorrectable_blocks_lane2_high[0x20]; 1382 1383 u8 fc_fec_uncorrectable_blocks_lane2_low[0x20]; 1384 1385 u8 fc_fec_uncorrectable_blocks_lane3_high[0x20]; 1386 1387 u8 fc_fec_uncorrectable_blocks_lane3_low[0x20]; 1388 1389 u8 rs_fec_corrected_blocks_high[0x20]; 1390 1391 u8 rs_fec_corrected_blocks_low[0x20]; 1392 1393 u8 rs_fec_uncorrectable_blocks_high[0x20]; 1394 1395 u8 rs_fec_uncorrectable_blocks_low[0x20]; 1396 1397 u8 rs_fec_no_errors_blocks_high[0x20]; 1398 1399 u8 rs_fec_no_errors_blocks_low[0x20]; 1400 1401 u8 rs_fec_single_error_blocks_high[0x20]; 1402 1403 u8 rs_fec_single_error_blocks_low[0x20]; 1404 1405 u8 rs_fec_corrected_symbols_total_high[0x20]; 1406 1407 u8 rs_fec_corrected_symbols_total_low[0x20]; 1408 1409 u8 rs_fec_corrected_symbols_lane0_high[0x20]; 1410 1411 u8 rs_fec_corrected_symbols_lane0_low[0x20]; 1412 1413 u8 rs_fec_corrected_symbols_lane1_high[0x20]; 1414 1415 u8 rs_fec_corrected_symbols_lane1_low[0x20]; 1416 1417 u8 rs_fec_corrected_symbols_lane2_high[0x20]; 1418 1419 u8 rs_fec_corrected_symbols_lane2_low[0x20]; 1420 1421 u8 rs_fec_corrected_symbols_lane3_high[0x20]; 1422 1423 u8 rs_fec_corrected_symbols_lane3_low[0x20]; 1424 1425 u8 link_down_events[0x20]; 1426 1427 u8 successful_recovery_events[0x20]; 1428 1429 u8 reserved_at_640[0x180]; 1430 }; 1431 1432 struct mlx5_ifc_phys_layer_statistical_cntrs_bits { 1433 u8 time_since_last_clear_high[0x20]; 1434 1435 u8 time_since_last_clear_low[0x20]; 1436 1437 u8 phy_received_bits_high[0x20]; 1438 1439 u8 phy_received_bits_low[0x20]; 1440 1441 u8 phy_symbol_errors_high[0x20]; 1442 1443 u8 phy_symbol_errors_low[0x20]; 1444 1445 u8 phy_corrected_bits_high[0x20]; 1446 1447 u8 phy_corrected_bits_low[0x20]; 1448 1449 u8 phy_corrected_bits_lane0_high[0x20]; 1450 1451 u8 phy_corrected_bits_lane0_low[0x20]; 1452 1453 u8 phy_corrected_bits_lane1_high[0x20]; 1454 1455 u8 phy_corrected_bits_lane1_low[0x20]; 1456 1457 u8 phy_corrected_bits_lane2_high[0x20]; 1458 1459 u8 phy_corrected_bits_lane2_low[0x20]; 1460 1461 u8 phy_corrected_bits_lane3_high[0x20]; 1462 1463 u8 phy_corrected_bits_lane3_low[0x20]; 1464 1465 u8 reserved_at_200[0x5c0]; 1466 }; 1467 1468 struct mlx5_ifc_ib_port_cntrs_grp_data_layout_bits { 1469 u8 symbol_error_counter[0x10]; 1470 1471 u8 link_error_recovery_counter[0x8]; 1472 1473 u8 link_downed_counter[0x8]; 1474 1475 u8 port_rcv_errors[0x10]; 1476 1477 u8 port_rcv_remote_physical_errors[0x10]; 1478 1479 u8 port_rcv_switch_relay_errors[0x10]; 1480 1481 u8 port_xmit_discards[0x10]; 1482 1483 u8 port_xmit_constraint_errors[0x8]; 1484 1485 u8 port_rcv_constraint_errors[0x8]; 1486 1487 u8 reserved_at_70[0x8]; 1488 1489 u8 link_overrun_errors[0x8]; 1490 1491 u8 reserved_at_80[0x10]; 1492 1493 u8 vl_15_dropped[0x10]; 1494 1495 u8 reserved_at_a0[0x80]; 1496 1497 u8 port_xmit_wait[0x20]; 1498 }; 1499 1500 struct mlx5_ifc_eth_per_traffic_grp_data_layout_bits { 1501 u8 transmit_queue_high[0x20]; 1502 1503 u8 transmit_queue_low[0x20]; 1504 1505 u8 reserved_at_40[0x780]; 1506 }; 1507 1508 struct mlx5_ifc_eth_per_prio_grp_data_layout_bits { 1509 u8 rx_octets_high[0x20]; 1510 1511 u8 rx_octets_low[0x20]; 1512 1513 u8 reserved_at_40[0xc0]; 1514 1515 u8 rx_frames_high[0x20]; 1516 1517 u8 rx_frames_low[0x20]; 1518 1519 u8 tx_octets_high[0x20]; 1520 1521 u8 tx_octets_low[0x20]; 1522 1523 u8 reserved_at_180[0xc0]; 1524 1525 u8 tx_frames_high[0x20]; 1526 1527 u8 tx_frames_low[0x20]; 1528 1529 u8 rx_pause_high[0x20]; 1530 1531 u8 rx_pause_low[0x20]; 1532 1533 u8 rx_pause_duration_high[0x20]; 1534 1535 u8 rx_pause_duration_low[0x20]; 1536 1537 u8 tx_pause_high[0x20]; 1538 1539 u8 tx_pause_low[0x20]; 1540 1541 u8 tx_pause_duration_high[0x20]; 1542 1543 u8 tx_pause_duration_low[0x20]; 1544 1545 u8 rx_pause_transition_high[0x20]; 1546 1547 u8 rx_pause_transition_low[0x20]; 1548 1549 u8 reserved_at_3c0[0x400]; 1550 }; 1551 1552 struct mlx5_ifc_eth_extended_cntrs_grp_data_layout_bits { 1553 u8 port_transmit_wait_high[0x20]; 1554 1555 u8 port_transmit_wait_low[0x20]; 1556 1557 u8 reserved_at_40[0x100]; 1558 1559 u8 rx_buffer_almost_full_high[0x20]; 1560 1561 u8 rx_buffer_almost_full_low[0x20]; 1562 1563 u8 rx_buffer_full_high[0x20]; 1564 1565 u8 rx_buffer_full_low[0x20]; 1566 1567 u8 reserved_at_1c0[0x600]; 1568 }; 1569 1570 struct mlx5_ifc_eth_3635_cntrs_grp_data_layout_bits { 1571 u8 dot3stats_alignment_errors_high[0x20]; 1572 1573 u8 dot3stats_alignment_errors_low[0x20]; 1574 1575 u8 dot3stats_fcs_errors_high[0x20]; 1576 1577 u8 dot3stats_fcs_errors_low[0x20]; 1578 1579 u8 dot3stats_single_collision_frames_high[0x20]; 1580 1581 u8 dot3stats_single_collision_frames_low[0x20]; 1582 1583 u8 dot3stats_multiple_collision_frames_high[0x20]; 1584 1585 u8 dot3stats_multiple_collision_frames_low[0x20]; 1586 1587 u8 dot3stats_sqe_test_errors_high[0x20]; 1588 1589 u8 dot3stats_sqe_test_errors_low[0x20]; 1590 1591 u8 dot3stats_deferred_transmissions_high[0x20]; 1592 1593 u8 dot3stats_deferred_transmissions_low[0x20]; 1594 1595 u8 dot3stats_late_collisions_high[0x20]; 1596 1597 u8 dot3stats_late_collisions_low[0x20]; 1598 1599 u8 dot3stats_excessive_collisions_high[0x20]; 1600 1601 u8 dot3stats_excessive_collisions_low[0x20]; 1602 1603 u8 dot3stats_internal_mac_transmit_errors_high[0x20]; 1604 1605 u8 dot3stats_internal_mac_transmit_errors_low[0x20]; 1606 1607 u8 dot3stats_carrier_sense_errors_high[0x20]; 1608 1609 u8 dot3stats_carrier_sense_errors_low[0x20]; 1610 1611 u8 dot3stats_frame_too_longs_high[0x20]; 1612 1613 u8 dot3stats_frame_too_longs_low[0x20]; 1614 1615 u8 dot3stats_internal_mac_receive_errors_high[0x20]; 1616 1617 u8 dot3stats_internal_mac_receive_errors_low[0x20]; 1618 1619 u8 dot3stats_symbol_errors_high[0x20]; 1620 1621 u8 dot3stats_symbol_errors_low[0x20]; 1622 1623 u8 dot3control_in_unknown_opcodes_high[0x20]; 1624 1625 u8 dot3control_in_unknown_opcodes_low[0x20]; 1626 1627 u8 dot3in_pause_frames_high[0x20]; 1628 1629 u8 dot3in_pause_frames_low[0x20]; 1630 1631 u8 dot3out_pause_frames_high[0x20]; 1632 1633 u8 dot3out_pause_frames_low[0x20]; 1634 1635 u8 reserved_at_400[0x3c0]; 1636 }; 1637 1638 struct mlx5_ifc_eth_2819_cntrs_grp_data_layout_bits { 1639 u8 ether_stats_drop_events_high[0x20]; 1640 1641 u8 ether_stats_drop_events_low[0x20]; 1642 1643 u8 ether_stats_octets_high[0x20]; 1644 1645 u8 ether_stats_octets_low[0x20]; 1646 1647 u8 ether_stats_pkts_high[0x20]; 1648 1649 u8 ether_stats_pkts_low[0x20]; 1650 1651 u8 ether_stats_broadcast_pkts_high[0x20]; 1652 1653 u8 ether_stats_broadcast_pkts_low[0x20]; 1654 1655 u8 ether_stats_multicast_pkts_high[0x20]; 1656 1657 u8 ether_stats_multicast_pkts_low[0x20]; 1658 1659 u8 ether_stats_crc_align_errors_high[0x20]; 1660 1661 u8 ether_stats_crc_align_errors_low[0x20]; 1662 1663 u8 ether_stats_undersize_pkts_high[0x20]; 1664 1665 u8 ether_stats_undersize_pkts_low[0x20]; 1666 1667 u8 ether_stats_oversize_pkts_high[0x20]; 1668 1669 u8 ether_stats_oversize_pkts_low[0x20]; 1670 1671 u8 ether_stats_fragments_high[0x20]; 1672 1673 u8 ether_stats_fragments_low[0x20]; 1674 1675 u8 ether_stats_jabbers_high[0x20]; 1676 1677 u8 ether_stats_jabbers_low[0x20]; 1678 1679 u8 ether_stats_collisions_high[0x20]; 1680 1681 u8 ether_stats_collisions_low[0x20]; 1682 1683 u8 ether_stats_pkts64octets_high[0x20]; 1684 1685 u8 ether_stats_pkts64octets_low[0x20]; 1686 1687 u8 ether_stats_pkts65to127octets_high[0x20]; 1688 1689 u8 ether_stats_pkts65to127octets_low[0x20]; 1690 1691 u8 ether_stats_pkts128to255octets_high[0x20]; 1692 1693 u8 ether_stats_pkts128to255octets_low[0x20]; 1694 1695 u8 ether_stats_pkts256to511octets_high[0x20]; 1696 1697 u8 ether_stats_pkts256to511octets_low[0x20]; 1698 1699 u8 ether_stats_pkts512to1023octets_high[0x20]; 1700 1701 u8 ether_stats_pkts512to1023octets_low[0x20]; 1702 1703 u8 ether_stats_pkts1024to1518octets_high[0x20]; 1704 1705 u8 ether_stats_pkts1024to1518octets_low[0x20]; 1706 1707 u8 ether_stats_pkts1519to2047octets_high[0x20]; 1708 1709 u8 ether_stats_pkts1519to2047octets_low[0x20]; 1710 1711 u8 ether_stats_pkts2048to4095octets_high[0x20]; 1712 1713 u8 ether_stats_pkts2048to4095octets_low[0x20]; 1714 1715 u8 ether_stats_pkts4096to8191octets_high[0x20]; 1716 1717 u8 ether_stats_pkts4096to8191octets_low[0x20]; 1718 1719 u8 ether_stats_pkts8192to10239octets_high[0x20]; 1720 1721 u8 ether_stats_pkts8192to10239octets_low[0x20]; 1722 1723 u8 reserved_at_540[0x280]; 1724 }; 1725 1726 struct mlx5_ifc_eth_2863_cntrs_grp_data_layout_bits { 1727 u8 if_in_octets_high[0x20]; 1728 1729 u8 if_in_octets_low[0x20]; 1730 1731 u8 if_in_ucast_pkts_high[0x20]; 1732 1733 u8 if_in_ucast_pkts_low[0x20]; 1734 1735 u8 if_in_discards_high[0x20]; 1736 1737 u8 if_in_discards_low[0x20]; 1738 1739 u8 if_in_errors_high[0x20]; 1740 1741 u8 if_in_errors_low[0x20]; 1742 1743 u8 if_in_unknown_protos_high[0x20]; 1744 1745 u8 if_in_unknown_protos_low[0x20]; 1746 1747 u8 if_out_octets_high[0x20]; 1748 1749 u8 if_out_octets_low[0x20]; 1750 1751 u8 if_out_ucast_pkts_high[0x20]; 1752 1753 u8 if_out_ucast_pkts_low[0x20]; 1754 1755 u8 if_out_discards_high[0x20]; 1756 1757 u8 if_out_discards_low[0x20]; 1758 1759 u8 if_out_errors_high[0x20]; 1760 1761 u8 if_out_errors_low[0x20]; 1762 1763 u8 if_in_multicast_pkts_high[0x20]; 1764 1765 u8 if_in_multicast_pkts_low[0x20]; 1766 1767 u8 if_in_broadcast_pkts_high[0x20]; 1768 1769 u8 if_in_broadcast_pkts_low[0x20]; 1770 1771 u8 if_out_multicast_pkts_high[0x20]; 1772 1773 u8 if_out_multicast_pkts_low[0x20]; 1774 1775 u8 if_out_broadcast_pkts_high[0x20]; 1776 1777 u8 if_out_broadcast_pkts_low[0x20]; 1778 1779 u8 reserved_at_340[0x480]; 1780 }; 1781 1782 struct mlx5_ifc_eth_802_3_cntrs_grp_data_layout_bits { 1783 u8 a_frames_transmitted_ok_high[0x20]; 1784 1785 u8 a_frames_transmitted_ok_low[0x20]; 1786 1787 u8 a_frames_received_ok_high[0x20]; 1788 1789 u8 a_frames_received_ok_low[0x20]; 1790 1791 u8 a_frame_check_sequence_errors_high[0x20]; 1792 1793 u8 a_frame_check_sequence_errors_low[0x20]; 1794 1795 u8 a_alignment_errors_high[0x20]; 1796 1797 u8 a_alignment_errors_low[0x20]; 1798 1799 u8 a_octets_transmitted_ok_high[0x20]; 1800 1801 u8 a_octets_transmitted_ok_low[0x20]; 1802 1803 u8 a_octets_received_ok_high[0x20]; 1804 1805 u8 a_octets_received_ok_low[0x20]; 1806 1807 u8 a_multicast_frames_xmitted_ok_high[0x20]; 1808 1809 u8 a_multicast_frames_xmitted_ok_low[0x20]; 1810 1811 u8 a_broadcast_frames_xmitted_ok_high[0x20]; 1812 1813 u8 a_broadcast_frames_xmitted_ok_low[0x20]; 1814 1815 u8 a_multicast_frames_received_ok_high[0x20]; 1816 1817 u8 a_multicast_frames_received_ok_low[0x20]; 1818 1819 u8 a_broadcast_frames_received_ok_high[0x20]; 1820 1821 u8 a_broadcast_frames_received_ok_low[0x20]; 1822 1823 u8 a_in_range_length_errors_high[0x20]; 1824 1825 u8 a_in_range_length_errors_low[0x20]; 1826 1827 u8 a_out_of_range_length_field_high[0x20]; 1828 1829 u8 a_out_of_range_length_field_low[0x20]; 1830 1831 u8 a_frame_too_long_errors_high[0x20]; 1832 1833 u8 a_frame_too_long_errors_low[0x20]; 1834 1835 u8 a_symbol_error_during_carrier_high[0x20]; 1836 1837 u8 a_symbol_error_during_carrier_low[0x20]; 1838 1839 u8 a_mac_control_frames_transmitted_high[0x20]; 1840 1841 u8 a_mac_control_frames_transmitted_low[0x20]; 1842 1843 u8 a_mac_control_frames_received_high[0x20]; 1844 1845 u8 a_mac_control_frames_received_low[0x20]; 1846 1847 u8 a_unsupported_opcodes_received_high[0x20]; 1848 1849 u8 a_unsupported_opcodes_received_low[0x20]; 1850 1851 u8 a_pause_mac_ctrl_frames_received_high[0x20]; 1852 1853 u8 a_pause_mac_ctrl_frames_received_low[0x20]; 1854 1855 u8 a_pause_mac_ctrl_frames_transmitted_high[0x20]; 1856 1857 u8 a_pause_mac_ctrl_frames_transmitted_low[0x20]; 1858 1859 u8 reserved_at_4c0[0x300]; 1860 }; 1861 1862 struct mlx5_ifc_pcie_perf_cntrs_grp_data_layout_bits { 1863 u8 life_time_counter_high[0x20]; 1864 1865 u8 life_time_counter_low[0x20]; 1866 1867 u8 rx_errors[0x20]; 1868 1869 u8 tx_errors[0x20]; 1870 1871 u8 l0_to_recovery_eieos[0x20]; 1872 1873 u8 l0_to_recovery_ts[0x20]; 1874 1875 u8 l0_to_recovery_framing[0x20]; 1876 1877 u8 l0_to_recovery_retrain[0x20]; 1878 1879 u8 crc_error_dllp[0x20]; 1880 1881 u8 crc_error_tlp[0x20]; 1882 1883 u8 tx_overflow_buffer_pkt_high[0x20]; 1884 1885 u8 tx_overflow_buffer_pkt_low[0x20]; 1886 1887 u8 outbound_stalled_reads[0x20]; 1888 1889 u8 outbound_stalled_writes[0x20]; 1890 1891 u8 outbound_stalled_reads_events[0x20]; 1892 1893 u8 outbound_stalled_writes_events[0x20]; 1894 1895 u8 reserved_at_200[0x5c0]; 1896 }; 1897 1898 struct mlx5_ifc_cmd_inter_comp_event_bits { 1899 u8 command_completion_vector[0x20]; 1900 1901 u8 reserved_at_20[0xc0]; 1902 }; 1903 1904 struct mlx5_ifc_stall_vl_event_bits { 1905 u8 reserved_at_0[0x18]; 1906 u8 port_num[0x1]; 1907 u8 reserved_at_19[0x3]; 1908 u8 vl[0x4]; 1909 1910 u8 reserved_at_20[0xa0]; 1911 }; 1912 1913 struct mlx5_ifc_db_bf_congestion_event_bits { 1914 u8 event_subtype[0x8]; 1915 u8 reserved_at_8[0x8]; 1916 u8 congestion_level[0x8]; 1917 u8 reserved_at_18[0x8]; 1918 1919 u8 reserved_at_20[0xa0]; 1920 }; 1921 1922 struct mlx5_ifc_gpio_event_bits { 1923 u8 reserved_at_0[0x60]; 1924 1925 u8 gpio_event_hi[0x20]; 1926 1927 u8 gpio_event_lo[0x20]; 1928 1929 u8 reserved_at_a0[0x40]; 1930 }; 1931 1932 struct mlx5_ifc_port_state_change_event_bits { 1933 u8 reserved_at_0[0x40]; 1934 1935 u8 port_num[0x4]; 1936 u8 reserved_at_44[0x1c]; 1937 1938 u8 reserved_at_60[0x80]; 1939 }; 1940 1941 struct mlx5_ifc_dropped_packet_logged_bits { 1942 u8 reserved_at_0[0xe0]; 1943 }; 1944 1945 enum { 1946 MLX5_CQ_ERROR_SYNDROME_CQ_OVERRUN = 0x1, 1947 MLX5_CQ_ERROR_SYNDROME_CQ_ACCESS_VIOLATION_ERROR = 0x2, 1948 }; 1949 1950 struct mlx5_ifc_cq_error_bits { 1951 u8 reserved_at_0[0x8]; 1952 u8 cqn[0x18]; 1953 1954 u8 reserved_at_20[0x20]; 1955 1956 u8 reserved_at_40[0x18]; 1957 u8 syndrome[0x8]; 1958 1959 u8 reserved_at_60[0x80]; 1960 }; 1961 1962 struct mlx5_ifc_rdma_page_fault_event_bits { 1963 u8 bytes_committed[0x20]; 1964 1965 u8 r_key[0x20]; 1966 1967 u8 reserved_at_40[0x10]; 1968 u8 packet_len[0x10]; 1969 1970 u8 rdma_op_len[0x20]; 1971 1972 u8 rdma_va[0x40]; 1973 1974 u8 reserved_at_c0[0x5]; 1975 u8 rdma[0x1]; 1976 u8 write[0x1]; 1977 u8 requestor[0x1]; 1978 u8 qp_number[0x18]; 1979 }; 1980 1981 struct mlx5_ifc_wqe_associated_page_fault_event_bits { 1982 u8 bytes_committed[0x20]; 1983 1984 u8 reserved_at_20[0x10]; 1985 u8 wqe_index[0x10]; 1986 1987 u8 reserved_at_40[0x10]; 1988 u8 len[0x10]; 1989 1990 u8 reserved_at_60[0x60]; 1991 1992 u8 reserved_at_c0[0x5]; 1993 u8 rdma[0x1]; 1994 u8 write_read[0x1]; 1995 u8 requestor[0x1]; 1996 u8 qpn[0x18]; 1997 }; 1998 1999 struct mlx5_ifc_qp_events_bits { 2000 u8 reserved_at_0[0xa0]; 2001 2002 u8 type[0x8]; 2003 u8 reserved_at_a8[0x18]; 2004 2005 u8 reserved_at_c0[0x8]; 2006 u8 qpn_rqn_sqn[0x18]; 2007 }; 2008 2009 struct mlx5_ifc_dct_events_bits { 2010 u8 reserved_at_0[0xc0]; 2011 2012 u8 reserved_at_c0[0x8]; 2013 u8 dct_number[0x18]; 2014 }; 2015 2016 struct mlx5_ifc_comp_event_bits { 2017 u8 reserved_at_0[0xc0]; 2018 2019 u8 reserved_at_c0[0x8]; 2020 u8 cq_number[0x18]; 2021 }; 2022 2023 enum { 2024 MLX5_QPC_STATE_RST = 0x0, 2025 MLX5_QPC_STATE_INIT = 0x1, 2026 MLX5_QPC_STATE_RTR = 0x2, 2027 MLX5_QPC_STATE_RTS = 0x3, 2028 MLX5_QPC_STATE_SQER = 0x4, 2029 MLX5_QPC_STATE_ERR = 0x6, 2030 MLX5_QPC_STATE_SQD = 0x7, 2031 MLX5_QPC_STATE_SUSPENDED = 0x9, 2032 }; 2033 2034 enum { 2035 MLX5_QPC_ST_RC = 0x0, 2036 MLX5_QPC_ST_UC = 0x1, 2037 MLX5_QPC_ST_UD = 0x2, 2038 MLX5_QPC_ST_XRC = 0x3, 2039 MLX5_QPC_ST_DCI = 0x5, 2040 MLX5_QPC_ST_QP0 = 0x7, 2041 MLX5_QPC_ST_QP1 = 0x8, 2042 MLX5_QPC_ST_RAW_DATAGRAM = 0x9, 2043 MLX5_QPC_ST_REG_UMR = 0xc, 2044 }; 2045 2046 enum { 2047 MLX5_QPC_PM_STATE_ARMED = 0x0, 2048 MLX5_QPC_PM_STATE_REARM = 0x1, 2049 MLX5_QPC_PM_STATE_RESERVED = 0x2, 2050 MLX5_QPC_PM_STATE_MIGRATED = 0x3, 2051 }; 2052 2053 enum { 2054 MLX5_QPC_OFFLOAD_TYPE_RNDV = 0x1, 2055 }; 2056 2057 enum { 2058 MLX5_QPC_END_PADDING_MODE_SCATTER_AS_IS = 0x0, 2059 MLX5_QPC_END_PADDING_MODE_PAD_TO_CACHE_LINE_ALIGNMENT = 0x1, 2060 }; 2061 2062 enum { 2063 MLX5_QPC_MTU_256_BYTES = 0x1, 2064 MLX5_QPC_MTU_512_BYTES = 0x2, 2065 MLX5_QPC_MTU_1K_BYTES = 0x3, 2066 MLX5_QPC_MTU_2K_BYTES = 0x4, 2067 MLX5_QPC_MTU_4K_BYTES = 0x5, 2068 MLX5_QPC_MTU_RAW_ETHERNET_QP = 0x7, 2069 }; 2070 2071 enum { 2072 MLX5_QPC_ATOMIC_MODE_IB_SPEC = 0x1, 2073 MLX5_QPC_ATOMIC_MODE_ONLY_8B = 0x2, 2074 MLX5_QPC_ATOMIC_MODE_UP_TO_8B = 0x3, 2075 MLX5_QPC_ATOMIC_MODE_UP_TO_16B = 0x4, 2076 MLX5_QPC_ATOMIC_MODE_UP_TO_32B = 0x5, 2077 MLX5_QPC_ATOMIC_MODE_UP_TO_64B = 0x6, 2078 MLX5_QPC_ATOMIC_MODE_UP_TO_128B = 0x7, 2079 MLX5_QPC_ATOMIC_MODE_UP_TO_256B = 0x8, 2080 }; 2081 2082 enum { 2083 MLX5_QPC_CS_REQ_DISABLE = 0x0, 2084 MLX5_QPC_CS_REQ_UP_TO_32B = 0x11, 2085 MLX5_QPC_CS_REQ_UP_TO_64B = 0x22, 2086 }; 2087 2088 enum { 2089 MLX5_QPC_CS_RES_DISABLE = 0x0, 2090 MLX5_QPC_CS_RES_UP_TO_32B = 0x1, 2091 MLX5_QPC_CS_RES_UP_TO_64B = 0x2, 2092 }; 2093 2094 struct mlx5_ifc_qpc_bits { 2095 u8 state[0x4]; 2096 u8 lag_tx_port_affinity[0x4]; 2097 u8 st[0x8]; 2098 u8 reserved_at_10[0x3]; 2099 u8 pm_state[0x2]; 2100 u8 reserved_at_15[0x3]; 2101 u8 offload_type[0x4]; 2102 u8 end_padding_mode[0x2]; 2103 u8 reserved_at_1e[0x2]; 2104 2105 u8 wq_signature[0x1]; 2106 u8 block_lb_mc[0x1]; 2107 u8 atomic_like_write_en[0x1]; 2108 u8 latency_sensitive[0x1]; 2109 u8 reserved_at_24[0x1]; 2110 u8 drain_sigerr[0x1]; 2111 u8 reserved_at_26[0x2]; 2112 u8 pd[0x18]; 2113 2114 u8 mtu[0x3]; 2115 u8 log_msg_max[0x5]; 2116 u8 reserved_at_48[0x1]; 2117 u8 log_rq_size[0x4]; 2118 u8 log_rq_stride[0x3]; 2119 u8 no_sq[0x1]; 2120 u8 log_sq_size[0x4]; 2121 u8 reserved_at_55[0x6]; 2122 u8 rlky[0x1]; 2123 u8 ulp_stateless_offload_mode[0x4]; 2124 2125 u8 counter_set_id[0x8]; 2126 u8 uar_page[0x18]; 2127 2128 u8 reserved_at_80[0x8]; 2129 u8 user_index[0x18]; 2130 2131 u8 reserved_at_a0[0x3]; 2132 u8 log_page_size[0x5]; 2133 u8 remote_qpn[0x18]; 2134 2135 struct mlx5_ifc_ads_bits primary_address_path; 2136 2137 struct mlx5_ifc_ads_bits secondary_address_path; 2138 2139 u8 log_ack_req_freq[0x4]; 2140 u8 reserved_at_384[0x4]; 2141 u8 log_sra_max[0x3]; 2142 u8 reserved_at_38b[0x2]; 2143 u8 retry_count[0x3]; 2144 u8 rnr_retry[0x3]; 2145 u8 reserved_at_393[0x1]; 2146 u8 fre[0x1]; 2147 u8 cur_rnr_retry[0x3]; 2148 u8 cur_retry_count[0x3]; 2149 u8 reserved_at_39b[0x5]; 2150 2151 u8 reserved_at_3a0[0x20]; 2152 2153 u8 reserved_at_3c0[0x8]; 2154 u8 next_send_psn[0x18]; 2155 2156 u8 reserved_at_3e0[0x8]; 2157 u8 cqn_snd[0x18]; 2158 2159 u8 reserved_at_400[0x8]; 2160 u8 deth_sqpn[0x18]; 2161 2162 u8 reserved_at_420[0x20]; 2163 2164 u8 reserved_at_440[0x8]; 2165 u8 last_acked_psn[0x18]; 2166 2167 u8 reserved_at_460[0x8]; 2168 u8 ssn[0x18]; 2169 2170 u8 reserved_at_480[0x8]; 2171 u8 log_rra_max[0x3]; 2172 u8 reserved_at_48b[0x1]; 2173 u8 atomic_mode[0x4]; 2174 u8 rre[0x1]; 2175 u8 rwe[0x1]; 2176 u8 rae[0x1]; 2177 u8 reserved_at_493[0x1]; 2178 u8 page_offset[0x6]; 2179 u8 reserved_at_49a[0x3]; 2180 u8 cd_slave_receive[0x1]; 2181 u8 cd_slave_send[0x1]; 2182 u8 cd_master[0x1]; 2183 2184 u8 reserved_at_4a0[0x3]; 2185 u8 min_rnr_nak[0x5]; 2186 u8 next_rcv_psn[0x18]; 2187 2188 u8 reserved_at_4c0[0x8]; 2189 u8 xrcd[0x18]; 2190 2191 u8 reserved_at_4e0[0x8]; 2192 u8 cqn_rcv[0x18]; 2193 2194 u8 dbr_addr[0x40]; 2195 2196 u8 q_key[0x20]; 2197 2198 u8 reserved_at_560[0x5]; 2199 u8 rq_type[0x3]; 2200 u8 srqn_rmpn_xrqn[0x18]; 2201 2202 u8 reserved_at_580[0x8]; 2203 u8 rmsn[0x18]; 2204 2205 u8 hw_sq_wqebb_counter[0x10]; 2206 u8 sw_sq_wqebb_counter[0x10]; 2207 2208 u8 hw_rq_counter[0x20]; 2209 2210 u8 sw_rq_counter[0x20]; 2211 2212 u8 reserved_at_600[0x20]; 2213 2214 u8 reserved_at_620[0xf]; 2215 u8 cgs[0x1]; 2216 u8 cs_req[0x8]; 2217 u8 cs_res[0x8]; 2218 2219 u8 dc_access_key[0x40]; 2220 2221 u8 reserved_at_680[0xc0]; 2222 }; 2223 2224 struct mlx5_ifc_roce_addr_layout_bits { 2225 u8 source_l3_address[16][0x8]; 2226 2227 u8 reserved_at_80[0x3]; 2228 u8 vlan_valid[0x1]; 2229 u8 vlan_id[0xc]; 2230 u8 source_mac_47_32[0x10]; 2231 2232 u8 source_mac_31_0[0x20]; 2233 2234 u8 reserved_at_c0[0x14]; 2235 u8 roce_l3_type[0x4]; 2236 u8 roce_version[0x8]; 2237 2238 u8 reserved_at_e0[0x20]; 2239 }; 2240 2241 union mlx5_ifc_hca_cap_union_bits { 2242 struct mlx5_ifc_cmd_hca_cap_bits cmd_hca_cap; 2243 struct mlx5_ifc_odp_cap_bits odp_cap; 2244 struct mlx5_ifc_atomic_caps_bits atomic_caps; 2245 struct mlx5_ifc_roce_cap_bits roce_cap; 2246 struct mlx5_ifc_per_protocol_networking_offload_caps_bits per_protocol_networking_offload_caps; 2247 struct mlx5_ifc_flow_table_nic_cap_bits flow_table_nic_cap; 2248 struct mlx5_ifc_flow_table_eswitch_cap_bits flow_table_eswitch_cap; 2249 struct mlx5_ifc_e_switch_cap_bits e_switch_cap; 2250 struct mlx5_ifc_vector_calc_cap_bits vector_calc_cap; 2251 struct mlx5_ifc_qos_cap_bits qos_cap; 2252 struct mlx5_ifc_fpga_cap_bits fpga_cap; 2253 u8 reserved_at_0[0x8000]; 2254 }; 2255 2256 enum { 2257 MLX5_FLOW_CONTEXT_ACTION_ALLOW = 0x1, 2258 MLX5_FLOW_CONTEXT_ACTION_DROP = 0x2, 2259 MLX5_FLOW_CONTEXT_ACTION_FWD_DEST = 0x4, 2260 MLX5_FLOW_CONTEXT_ACTION_COUNT = 0x8, 2261 MLX5_FLOW_CONTEXT_ACTION_ENCAP = 0x10, 2262 MLX5_FLOW_CONTEXT_ACTION_DECAP = 0x20, 2263 MLX5_FLOW_CONTEXT_ACTION_MOD_HDR = 0x40, 2264 }; 2265 2266 struct mlx5_ifc_flow_context_bits { 2267 u8 reserved_at_0[0x20]; 2268 2269 u8 group_id[0x20]; 2270 2271 u8 reserved_at_40[0x8]; 2272 u8 flow_tag[0x18]; 2273 2274 u8 reserved_at_60[0x10]; 2275 u8 action[0x10]; 2276 2277 u8 reserved_at_80[0x8]; 2278 u8 destination_list_size[0x18]; 2279 2280 u8 reserved_at_a0[0x8]; 2281 u8 flow_counter_list_size[0x18]; 2282 2283 u8 encap_id[0x20]; 2284 2285 u8 modify_header_id[0x20]; 2286 2287 u8 reserved_at_100[0x100]; 2288 2289 struct mlx5_ifc_fte_match_param_bits match_value; 2290 2291 u8 reserved_at_1200[0x600]; 2292 2293 union mlx5_ifc_dest_format_struct_flow_counter_list_auto_bits destination[0]; 2294 }; 2295 2296 enum { 2297 MLX5_XRC_SRQC_STATE_GOOD = 0x0, 2298 MLX5_XRC_SRQC_STATE_ERROR = 0x1, 2299 }; 2300 2301 struct mlx5_ifc_xrc_srqc_bits { 2302 u8 state[0x4]; 2303 u8 log_xrc_srq_size[0x4]; 2304 u8 reserved_at_8[0x18]; 2305 2306 u8 wq_signature[0x1]; 2307 u8 cont_srq[0x1]; 2308 u8 reserved_at_22[0x1]; 2309 u8 rlky[0x1]; 2310 u8 basic_cyclic_rcv_wqe[0x1]; 2311 u8 log_rq_stride[0x3]; 2312 u8 xrcd[0x18]; 2313 2314 u8 page_offset[0x6]; 2315 u8 reserved_at_46[0x2]; 2316 u8 cqn[0x18]; 2317 2318 u8 reserved_at_60[0x20]; 2319 2320 u8 user_index_equal_xrc_srqn[0x1]; 2321 u8 reserved_at_81[0x1]; 2322 u8 log_page_size[0x6]; 2323 u8 user_index[0x18]; 2324 2325 u8 reserved_at_a0[0x20]; 2326 2327 u8 reserved_at_c0[0x8]; 2328 u8 pd[0x18]; 2329 2330 u8 lwm[0x10]; 2331 u8 wqe_cnt[0x10]; 2332 2333 u8 reserved_at_100[0x40]; 2334 2335 u8 db_record_addr_h[0x20]; 2336 2337 u8 db_record_addr_l[0x1e]; 2338 u8 reserved_at_17e[0x2]; 2339 2340 u8 reserved_at_180[0x80]; 2341 }; 2342 2343 struct mlx5_ifc_traffic_counter_bits { 2344 u8 packets[0x40]; 2345 2346 u8 octets[0x40]; 2347 }; 2348 2349 struct mlx5_ifc_tisc_bits { 2350 u8 strict_lag_tx_port_affinity[0x1]; 2351 u8 reserved_at_1[0x3]; 2352 u8 lag_tx_port_affinity[0x04]; 2353 2354 u8 reserved_at_8[0x4]; 2355 u8 prio[0x4]; 2356 u8 reserved_at_10[0x10]; 2357 2358 u8 reserved_at_20[0x100]; 2359 2360 u8 reserved_at_120[0x8]; 2361 u8 transport_domain[0x18]; 2362 2363 u8 reserved_at_140[0x8]; 2364 u8 underlay_qpn[0x18]; 2365 u8 reserved_at_160[0x3a0]; 2366 }; 2367 2368 enum { 2369 MLX5_TIRC_DISP_TYPE_DIRECT = 0x0, 2370 MLX5_TIRC_DISP_TYPE_INDIRECT = 0x1, 2371 }; 2372 2373 enum { 2374 MLX5_TIRC_LRO_ENABLE_MASK_IPV4_LRO = 0x1, 2375 MLX5_TIRC_LRO_ENABLE_MASK_IPV6_LRO = 0x2, 2376 }; 2377 2378 enum { 2379 MLX5_RX_HASH_FN_NONE = 0x0, 2380 MLX5_RX_HASH_FN_INVERTED_XOR8 = 0x1, 2381 MLX5_RX_HASH_FN_TOEPLITZ = 0x2, 2382 }; 2383 2384 enum { 2385 MLX5_TIRC_SELF_LB_BLOCK_BLOCK_UNICAST_ = 0x1, 2386 MLX5_TIRC_SELF_LB_BLOCK_BLOCK_MULTICAST_ = 0x2, 2387 }; 2388 2389 struct mlx5_ifc_tirc_bits { 2390 u8 reserved_at_0[0x20]; 2391 2392 u8 disp_type[0x4]; 2393 u8 reserved_at_24[0x1c]; 2394 2395 u8 reserved_at_40[0x40]; 2396 2397 u8 reserved_at_80[0x4]; 2398 u8 lro_timeout_period_usecs[0x10]; 2399 u8 lro_enable_mask[0x4]; 2400 u8 lro_max_ip_payload_size[0x8]; 2401 2402 u8 reserved_at_a0[0x40]; 2403 2404 u8 reserved_at_e0[0x8]; 2405 u8 inline_rqn[0x18]; 2406 2407 u8 rx_hash_symmetric[0x1]; 2408 u8 reserved_at_101[0x1]; 2409 u8 tunneled_offload_en[0x1]; 2410 u8 reserved_at_103[0x5]; 2411 u8 indirect_table[0x18]; 2412 2413 u8 rx_hash_fn[0x4]; 2414 u8 reserved_at_124[0x2]; 2415 u8 self_lb_block[0x2]; 2416 u8 transport_domain[0x18]; 2417 2418 u8 rx_hash_toeplitz_key[10][0x20]; 2419 2420 struct mlx5_ifc_rx_hash_field_select_bits rx_hash_field_selector_outer; 2421 2422 struct mlx5_ifc_rx_hash_field_select_bits rx_hash_field_selector_inner; 2423 2424 u8 reserved_at_2c0[0x4c0]; 2425 }; 2426 2427 enum { 2428 MLX5_SRQC_STATE_GOOD = 0x0, 2429 MLX5_SRQC_STATE_ERROR = 0x1, 2430 }; 2431 2432 struct mlx5_ifc_srqc_bits { 2433 u8 state[0x4]; 2434 u8 log_srq_size[0x4]; 2435 u8 reserved_at_8[0x18]; 2436 2437 u8 wq_signature[0x1]; 2438 u8 cont_srq[0x1]; 2439 u8 reserved_at_22[0x1]; 2440 u8 rlky[0x1]; 2441 u8 reserved_at_24[0x1]; 2442 u8 log_rq_stride[0x3]; 2443 u8 xrcd[0x18]; 2444 2445 u8 page_offset[0x6]; 2446 u8 reserved_at_46[0x2]; 2447 u8 cqn[0x18]; 2448 2449 u8 reserved_at_60[0x20]; 2450 2451 u8 reserved_at_80[0x2]; 2452 u8 log_page_size[0x6]; 2453 u8 reserved_at_88[0x18]; 2454 2455 u8 reserved_at_a0[0x20]; 2456 2457 u8 reserved_at_c0[0x8]; 2458 u8 pd[0x18]; 2459 2460 u8 lwm[0x10]; 2461 u8 wqe_cnt[0x10]; 2462 2463 u8 reserved_at_100[0x40]; 2464 2465 u8 dbr_addr[0x40]; 2466 2467 u8 reserved_at_180[0x80]; 2468 }; 2469 2470 enum { 2471 MLX5_SQC_STATE_RST = 0x0, 2472 MLX5_SQC_STATE_RDY = 0x1, 2473 MLX5_SQC_STATE_ERR = 0x3, 2474 }; 2475 2476 struct mlx5_ifc_sqc_bits { 2477 u8 rlky[0x1]; 2478 u8 cd_master[0x1]; 2479 u8 fre[0x1]; 2480 u8 flush_in_error_en[0x1]; 2481 u8 allow_multi_pkt_send_wqe[0x1]; 2482 u8 min_wqe_inline_mode[0x3]; 2483 u8 state[0x4]; 2484 u8 reg_umr[0x1]; 2485 u8 allow_swp[0x1]; 2486 u8 reserved_at_e[0x12]; 2487 2488 u8 reserved_at_20[0x8]; 2489 u8 user_index[0x18]; 2490 2491 u8 reserved_at_40[0x8]; 2492 u8 cqn[0x18]; 2493 2494 u8 reserved_at_60[0x90]; 2495 2496 u8 packet_pacing_rate_limit_index[0x10]; 2497 u8 tis_lst_sz[0x10]; 2498 u8 reserved_at_110[0x10]; 2499 2500 u8 reserved_at_120[0x40]; 2501 2502 u8 reserved_at_160[0x8]; 2503 u8 tis_num_0[0x18]; 2504 2505 struct mlx5_ifc_wq_bits wq; 2506 }; 2507 2508 enum { 2509 SCHEDULING_CONTEXT_ELEMENT_TYPE_TSAR = 0x0, 2510 SCHEDULING_CONTEXT_ELEMENT_TYPE_VPORT = 0x1, 2511 SCHEDULING_CONTEXT_ELEMENT_TYPE_VPORT_TC = 0x2, 2512 SCHEDULING_CONTEXT_ELEMENT_TYPE_PARA_VPORT_TC = 0x3, 2513 }; 2514 2515 struct mlx5_ifc_scheduling_context_bits { 2516 u8 element_type[0x8]; 2517 u8 reserved_at_8[0x18]; 2518 2519 u8 element_attributes[0x20]; 2520 2521 u8 parent_element_id[0x20]; 2522 2523 u8 reserved_at_60[0x40]; 2524 2525 u8 bw_share[0x20]; 2526 2527 u8 max_average_bw[0x20]; 2528 2529 u8 reserved_at_e0[0x120]; 2530 }; 2531 2532 struct mlx5_ifc_rqtc_bits { 2533 u8 reserved_at_0[0xa0]; 2534 2535 u8 reserved_at_a0[0x10]; 2536 u8 rqt_max_size[0x10]; 2537 2538 u8 reserved_at_c0[0x10]; 2539 u8 rqt_actual_size[0x10]; 2540 2541 u8 reserved_at_e0[0x6a0]; 2542 2543 struct mlx5_ifc_rq_num_bits rq_num[0]; 2544 }; 2545 2546 enum { 2547 MLX5_RQC_MEM_RQ_TYPE_MEMORY_RQ_INLINE = 0x0, 2548 MLX5_RQC_MEM_RQ_TYPE_MEMORY_RQ_RMP = 0x1, 2549 }; 2550 2551 enum { 2552 MLX5_RQC_STATE_RST = 0x0, 2553 MLX5_RQC_STATE_RDY = 0x1, 2554 MLX5_RQC_STATE_ERR = 0x3, 2555 }; 2556 2557 struct mlx5_ifc_rqc_bits { 2558 u8 rlky[0x1]; 2559 u8 delay_drop_en[0x1]; 2560 u8 scatter_fcs[0x1]; 2561 u8 vsd[0x1]; 2562 u8 mem_rq_type[0x4]; 2563 u8 state[0x4]; 2564 u8 reserved_at_c[0x1]; 2565 u8 flush_in_error_en[0x1]; 2566 u8 reserved_at_e[0x12]; 2567 2568 u8 reserved_at_20[0x8]; 2569 u8 user_index[0x18]; 2570 2571 u8 reserved_at_40[0x8]; 2572 u8 cqn[0x18]; 2573 2574 u8 counter_set_id[0x8]; 2575 u8 reserved_at_68[0x18]; 2576 2577 u8 reserved_at_80[0x8]; 2578 u8 rmpn[0x18]; 2579 2580 u8 reserved_at_a0[0xe0]; 2581 2582 struct mlx5_ifc_wq_bits wq; 2583 }; 2584 2585 enum { 2586 MLX5_RMPC_STATE_RDY = 0x1, 2587 MLX5_RMPC_STATE_ERR = 0x3, 2588 }; 2589 2590 struct mlx5_ifc_rmpc_bits { 2591 u8 reserved_at_0[0x8]; 2592 u8 state[0x4]; 2593 u8 reserved_at_c[0x14]; 2594 2595 u8 basic_cyclic_rcv_wqe[0x1]; 2596 u8 reserved_at_21[0x1f]; 2597 2598 u8 reserved_at_40[0x140]; 2599 2600 struct mlx5_ifc_wq_bits wq; 2601 }; 2602 2603 struct mlx5_ifc_nic_vport_context_bits { 2604 u8 reserved_at_0[0x5]; 2605 u8 min_wqe_inline_mode[0x3]; 2606 u8 reserved_at_8[0x15]; 2607 u8 disable_mc_local_lb[0x1]; 2608 u8 disable_uc_local_lb[0x1]; 2609 u8 roce_en[0x1]; 2610 2611 u8 arm_change_event[0x1]; 2612 u8 reserved_at_21[0x1a]; 2613 u8 event_on_mtu[0x1]; 2614 u8 event_on_promisc_change[0x1]; 2615 u8 event_on_vlan_change[0x1]; 2616 u8 event_on_mc_address_change[0x1]; 2617 u8 event_on_uc_address_change[0x1]; 2618 2619 u8 reserved_at_40[0xf0]; 2620 2621 u8 mtu[0x10]; 2622 2623 u8 system_image_guid[0x40]; 2624 u8 port_guid[0x40]; 2625 u8 node_guid[0x40]; 2626 2627 u8 reserved_at_200[0x140]; 2628 u8 qkey_violation_counter[0x10]; 2629 u8 reserved_at_350[0x430]; 2630 2631 u8 promisc_uc[0x1]; 2632 u8 promisc_mc[0x1]; 2633 u8 promisc_all[0x1]; 2634 u8 reserved_at_783[0x2]; 2635 u8 allowed_list_type[0x3]; 2636 u8 reserved_at_788[0xc]; 2637 u8 allowed_list_size[0xc]; 2638 2639 struct mlx5_ifc_mac_address_layout_bits permanent_address; 2640 2641 u8 reserved_at_7e0[0x20]; 2642 2643 u8 current_uc_mac_address[0][0x40]; 2644 }; 2645 2646 enum { 2647 MLX5_MKC_ACCESS_MODE_PA = 0x0, 2648 MLX5_MKC_ACCESS_MODE_MTT = 0x1, 2649 MLX5_MKC_ACCESS_MODE_KLMS = 0x2, 2650 MLX5_MKC_ACCESS_MODE_KSM = 0x3, 2651 }; 2652 2653 struct mlx5_ifc_mkc_bits { 2654 u8 reserved_at_0[0x1]; 2655 u8 free[0x1]; 2656 u8 reserved_at_2[0xd]; 2657 u8 small_fence_on_rdma_read_response[0x1]; 2658 u8 umr_en[0x1]; 2659 u8 a[0x1]; 2660 u8 rw[0x1]; 2661 u8 rr[0x1]; 2662 u8 lw[0x1]; 2663 u8 lr[0x1]; 2664 u8 access_mode[0x2]; 2665 u8 reserved_at_18[0x8]; 2666 2667 u8 qpn[0x18]; 2668 u8 mkey_7_0[0x8]; 2669 2670 u8 reserved_at_40[0x20]; 2671 2672 u8 length64[0x1]; 2673 u8 bsf_en[0x1]; 2674 u8 sync_umr[0x1]; 2675 u8 reserved_at_63[0x2]; 2676 u8 expected_sigerr_count[0x1]; 2677 u8 reserved_at_66[0x1]; 2678 u8 en_rinval[0x1]; 2679 u8 pd[0x18]; 2680 2681 u8 start_addr[0x40]; 2682 2683 u8 len[0x40]; 2684 2685 u8 bsf_octword_size[0x20]; 2686 2687 u8 reserved_at_120[0x80]; 2688 2689 u8 translations_octword_size[0x20]; 2690 2691 u8 reserved_at_1c0[0x1b]; 2692 u8 log_page_size[0x5]; 2693 2694 u8 reserved_at_1e0[0x20]; 2695 }; 2696 2697 struct mlx5_ifc_pkey_bits { 2698 u8 reserved_at_0[0x10]; 2699 u8 pkey[0x10]; 2700 }; 2701 2702 struct mlx5_ifc_array128_auto_bits { 2703 u8 array128_auto[16][0x8]; 2704 }; 2705 2706 struct mlx5_ifc_hca_vport_context_bits { 2707 u8 field_select[0x20]; 2708 2709 u8 reserved_at_20[0xe0]; 2710 2711 u8 sm_virt_aware[0x1]; 2712 u8 has_smi[0x1]; 2713 u8 has_raw[0x1]; 2714 u8 grh_required[0x1]; 2715 u8 reserved_at_104[0xc]; 2716 u8 port_physical_state[0x4]; 2717 u8 vport_state_policy[0x4]; 2718 u8 port_state[0x4]; 2719 u8 vport_state[0x4]; 2720 2721 u8 reserved_at_120[0x20]; 2722 2723 u8 system_image_guid[0x40]; 2724 2725 u8 port_guid[0x40]; 2726 2727 u8 node_guid[0x40]; 2728 2729 u8 cap_mask1[0x20]; 2730 2731 u8 cap_mask1_field_select[0x20]; 2732 2733 u8 cap_mask2[0x20]; 2734 2735 u8 cap_mask2_field_select[0x20]; 2736 2737 u8 reserved_at_280[0x80]; 2738 2739 u8 lid[0x10]; 2740 u8 reserved_at_310[0x4]; 2741 u8 init_type_reply[0x4]; 2742 u8 lmc[0x3]; 2743 u8 subnet_timeout[0x5]; 2744 2745 u8 sm_lid[0x10]; 2746 u8 sm_sl[0x4]; 2747 u8 reserved_at_334[0xc]; 2748 2749 u8 qkey_violation_counter[0x10]; 2750 u8 pkey_violation_counter[0x10]; 2751 2752 u8 reserved_at_360[0xca0]; 2753 }; 2754 2755 struct mlx5_ifc_esw_vport_context_bits { 2756 u8 reserved_at_0[0x3]; 2757 u8 vport_svlan_strip[0x1]; 2758 u8 vport_cvlan_strip[0x1]; 2759 u8 vport_svlan_insert[0x1]; 2760 u8 vport_cvlan_insert[0x2]; 2761 u8 reserved_at_8[0x18]; 2762 2763 u8 reserved_at_20[0x20]; 2764 2765 u8 svlan_cfi[0x1]; 2766 u8 svlan_pcp[0x3]; 2767 u8 svlan_id[0xc]; 2768 u8 cvlan_cfi[0x1]; 2769 u8 cvlan_pcp[0x3]; 2770 u8 cvlan_id[0xc]; 2771 2772 u8 reserved_at_60[0x7a0]; 2773 }; 2774 2775 enum { 2776 MLX5_EQC_STATUS_OK = 0x0, 2777 MLX5_EQC_STATUS_EQ_WRITE_FAILURE = 0xa, 2778 }; 2779 2780 enum { 2781 MLX5_EQC_ST_ARMED = 0x9, 2782 MLX5_EQC_ST_FIRED = 0xa, 2783 }; 2784 2785 struct mlx5_ifc_eqc_bits { 2786 u8 status[0x4]; 2787 u8 reserved_at_4[0x9]; 2788 u8 ec[0x1]; 2789 u8 oi[0x1]; 2790 u8 reserved_at_f[0x5]; 2791 u8 st[0x4]; 2792 u8 reserved_at_18[0x8]; 2793 2794 u8 reserved_at_20[0x20]; 2795 2796 u8 reserved_at_40[0x14]; 2797 u8 page_offset[0x6]; 2798 u8 reserved_at_5a[0x6]; 2799 2800 u8 reserved_at_60[0x3]; 2801 u8 log_eq_size[0x5]; 2802 u8 uar_page[0x18]; 2803 2804 u8 reserved_at_80[0x20]; 2805 2806 u8 reserved_at_a0[0x18]; 2807 u8 intr[0x8]; 2808 2809 u8 reserved_at_c0[0x3]; 2810 u8 log_page_size[0x5]; 2811 u8 reserved_at_c8[0x18]; 2812 2813 u8 reserved_at_e0[0x60]; 2814 2815 u8 reserved_at_140[0x8]; 2816 u8 consumer_counter[0x18]; 2817 2818 u8 reserved_at_160[0x8]; 2819 u8 producer_counter[0x18]; 2820 2821 u8 reserved_at_180[0x80]; 2822 }; 2823 2824 enum { 2825 MLX5_DCTC_STATE_ACTIVE = 0x0, 2826 MLX5_DCTC_STATE_DRAINING = 0x1, 2827 MLX5_DCTC_STATE_DRAINED = 0x2, 2828 }; 2829 2830 enum { 2831 MLX5_DCTC_CS_RES_DISABLE = 0x0, 2832 MLX5_DCTC_CS_RES_NA = 0x1, 2833 MLX5_DCTC_CS_RES_UP_TO_64B = 0x2, 2834 }; 2835 2836 enum { 2837 MLX5_DCTC_MTU_256_BYTES = 0x1, 2838 MLX5_DCTC_MTU_512_BYTES = 0x2, 2839 MLX5_DCTC_MTU_1K_BYTES = 0x3, 2840 MLX5_DCTC_MTU_2K_BYTES = 0x4, 2841 MLX5_DCTC_MTU_4K_BYTES = 0x5, 2842 }; 2843 2844 struct mlx5_ifc_dctc_bits { 2845 u8 reserved_at_0[0x4]; 2846 u8 state[0x4]; 2847 u8 reserved_at_8[0x18]; 2848 2849 u8 reserved_at_20[0x8]; 2850 u8 user_index[0x18]; 2851 2852 u8 reserved_at_40[0x8]; 2853 u8 cqn[0x18]; 2854 2855 u8 counter_set_id[0x8]; 2856 u8 atomic_mode[0x4]; 2857 u8 rre[0x1]; 2858 u8 rwe[0x1]; 2859 u8 rae[0x1]; 2860 u8 atomic_like_write_en[0x1]; 2861 u8 latency_sensitive[0x1]; 2862 u8 rlky[0x1]; 2863 u8 free_ar[0x1]; 2864 u8 reserved_at_73[0xd]; 2865 2866 u8 reserved_at_80[0x8]; 2867 u8 cs_res[0x8]; 2868 u8 reserved_at_90[0x3]; 2869 u8 min_rnr_nak[0x5]; 2870 u8 reserved_at_98[0x8]; 2871 2872 u8 reserved_at_a0[0x8]; 2873 u8 srqn_xrqn[0x18]; 2874 2875 u8 reserved_at_c0[0x8]; 2876 u8 pd[0x18]; 2877 2878 u8 tclass[0x8]; 2879 u8 reserved_at_e8[0x4]; 2880 u8 flow_label[0x14]; 2881 2882 u8 dc_access_key[0x40]; 2883 2884 u8 reserved_at_140[0x5]; 2885 u8 mtu[0x3]; 2886 u8 port[0x8]; 2887 u8 pkey_index[0x10]; 2888 2889 u8 reserved_at_160[0x8]; 2890 u8 my_addr_index[0x8]; 2891 u8 reserved_at_170[0x8]; 2892 u8 hop_limit[0x8]; 2893 2894 u8 dc_access_key_violation_count[0x20]; 2895 2896 u8 reserved_at_1a0[0x14]; 2897 u8 dei_cfi[0x1]; 2898 u8 eth_prio[0x3]; 2899 u8 ecn[0x2]; 2900 u8 dscp[0x6]; 2901 2902 u8 reserved_at_1c0[0x40]; 2903 }; 2904 2905 enum { 2906 MLX5_CQC_STATUS_OK = 0x0, 2907 MLX5_CQC_STATUS_CQ_OVERFLOW = 0x9, 2908 MLX5_CQC_STATUS_CQ_WRITE_FAIL = 0xa, 2909 }; 2910 2911 enum { 2912 MLX5_CQC_CQE_SZ_64_BYTES = 0x0, 2913 MLX5_CQC_CQE_SZ_128_BYTES = 0x1, 2914 }; 2915 2916 enum { 2917 MLX5_CQC_ST_SOLICITED_NOTIFICATION_REQUEST_ARMED = 0x6, 2918 MLX5_CQC_ST_NOTIFICATION_REQUEST_ARMED = 0x9, 2919 MLX5_CQC_ST_FIRED = 0xa, 2920 }; 2921 2922 enum { 2923 MLX5_CQ_PERIOD_MODE_START_FROM_EQE = 0x0, 2924 MLX5_CQ_PERIOD_MODE_START_FROM_CQE = 0x1, 2925 MLX5_CQ_PERIOD_NUM_MODES 2926 }; 2927 2928 struct mlx5_ifc_cqc_bits { 2929 u8 status[0x4]; 2930 u8 reserved_at_4[0x4]; 2931 u8 cqe_sz[0x3]; 2932 u8 cc[0x1]; 2933 u8 reserved_at_c[0x1]; 2934 u8 scqe_break_moderation_en[0x1]; 2935 u8 oi[0x1]; 2936 u8 cq_period_mode[0x2]; 2937 u8 cqe_comp_en[0x1]; 2938 u8 mini_cqe_res_format[0x2]; 2939 u8 st[0x4]; 2940 u8 reserved_at_18[0x8]; 2941 2942 u8 reserved_at_20[0x20]; 2943 2944 u8 reserved_at_40[0x14]; 2945 u8 page_offset[0x6]; 2946 u8 reserved_at_5a[0x6]; 2947 2948 u8 reserved_at_60[0x3]; 2949 u8 log_cq_size[0x5]; 2950 u8 uar_page[0x18]; 2951 2952 u8 reserved_at_80[0x4]; 2953 u8 cq_period[0xc]; 2954 u8 cq_max_count[0x10]; 2955 2956 u8 reserved_at_a0[0x18]; 2957 u8 c_eqn[0x8]; 2958 2959 u8 reserved_at_c0[0x3]; 2960 u8 log_page_size[0x5]; 2961 u8 reserved_at_c8[0x18]; 2962 2963 u8 reserved_at_e0[0x20]; 2964 2965 u8 reserved_at_100[0x8]; 2966 u8 last_notified_index[0x18]; 2967 2968 u8 reserved_at_120[0x8]; 2969 u8 last_solicit_index[0x18]; 2970 2971 u8 reserved_at_140[0x8]; 2972 u8 consumer_counter[0x18]; 2973 2974 u8 reserved_at_160[0x8]; 2975 u8 producer_counter[0x18]; 2976 2977 u8 reserved_at_180[0x40]; 2978 2979 u8 dbr_addr[0x40]; 2980 }; 2981 2982 union mlx5_ifc_cong_control_roce_ecn_auto_bits { 2983 struct mlx5_ifc_cong_control_802_1qau_rp_bits cong_control_802_1qau_rp; 2984 struct mlx5_ifc_cong_control_r_roce_ecn_rp_bits cong_control_r_roce_ecn_rp; 2985 struct mlx5_ifc_cong_control_r_roce_ecn_np_bits cong_control_r_roce_ecn_np; 2986 u8 reserved_at_0[0x800]; 2987 }; 2988 2989 struct mlx5_ifc_query_adapter_param_block_bits { 2990 u8 reserved_at_0[0xc0]; 2991 2992 u8 reserved_at_c0[0x8]; 2993 u8 ieee_vendor_id[0x18]; 2994 2995 u8 reserved_at_e0[0x10]; 2996 u8 vsd_vendor_id[0x10]; 2997 2998 u8 vsd[208][0x8]; 2999 3000 u8 vsd_contd_psid[16][0x8]; 3001 }; 3002 3003 enum { 3004 MLX5_XRQC_STATE_GOOD = 0x0, 3005 MLX5_XRQC_STATE_ERROR = 0x1, 3006 }; 3007 3008 enum { 3009 MLX5_XRQC_TOPOLOGY_NO_SPECIAL_TOPOLOGY = 0x0, 3010 MLX5_XRQC_TOPOLOGY_TAG_MATCHING = 0x1, 3011 }; 3012 3013 enum { 3014 MLX5_XRQC_OFFLOAD_RNDV = 0x1, 3015 }; 3016 3017 struct mlx5_ifc_tag_matching_topology_context_bits { 3018 u8 log_matching_list_sz[0x4]; 3019 u8 reserved_at_4[0xc]; 3020 u8 append_next_index[0x10]; 3021 3022 u8 sw_phase_cnt[0x10]; 3023 u8 hw_phase_cnt[0x10]; 3024 3025 u8 reserved_at_40[0x40]; 3026 }; 3027 3028 struct mlx5_ifc_xrqc_bits { 3029 u8 state[0x4]; 3030 u8 rlkey[0x1]; 3031 u8 reserved_at_5[0xf]; 3032 u8 topology[0x4]; 3033 u8 reserved_at_18[0x4]; 3034 u8 offload[0x4]; 3035 3036 u8 reserved_at_20[0x8]; 3037 u8 user_index[0x18]; 3038 3039 u8 reserved_at_40[0x8]; 3040 u8 cqn[0x18]; 3041 3042 u8 reserved_at_60[0xa0]; 3043 3044 struct mlx5_ifc_tag_matching_topology_context_bits tag_matching_topology_context; 3045 3046 u8 reserved_at_180[0x280]; 3047 3048 struct mlx5_ifc_wq_bits wq; 3049 }; 3050 3051 union mlx5_ifc_modify_field_select_resize_field_select_auto_bits { 3052 struct mlx5_ifc_modify_field_select_bits modify_field_select; 3053 struct mlx5_ifc_resize_field_select_bits resize_field_select; 3054 u8 reserved_at_0[0x20]; 3055 }; 3056 3057 union mlx5_ifc_field_select_802_1_r_roce_auto_bits { 3058 struct mlx5_ifc_field_select_802_1qau_rp_bits field_select_802_1qau_rp; 3059 struct mlx5_ifc_field_select_r_roce_rp_bits field_select_r_roce_rp; 3060 struct mlx5_ifc_field_select_r_roce_np_bits field_select_r_roce_np; 3061 u8 reserved_at_0[0x20]; 3062 }; 3063 3064 union mlx5_ifc_eth_cntrs_grp_data_layout_auto_bits { 3065 struct mlx5_ifc_eth_802_3_cntrs_grp_data_layout_bits eth_802_3_cntrs_grp_data_layout; 3066 struct mlx5_ifc_eth_2863_cntrs_grp_data_layout_bits eth_2863_cntrs_grp_data_layout; 3067 struct mlx5_ifc_eth_2819_cntrs_grp_data_layout_bits eth_2819_cntrs_grp_data_layout; 3068 struct mlx5_ifc_eth_3635_cntrs_grp_data_layout_bits eth_3635_cntrs_grp_data_layout; 3069 struct mlx5_ifc_eth_extended_cntrs_grp_data_layout_bits eth_extended_cntrs_grp_data_layout; 3070 struct mlx5_ifc_eth_per_prio_grp_data_layout_bits eth_per_prio_grp_data_layout; 3071 struct mlx5_ifc_eth_per_traffic_grp_data_layout_bits eth_per_traffic_grp_data_layout; 3072 struct mlx5_ifc_ib_port_cntrs_grp_data_layout_bits ib_port_cntrs_grp_data_layout; 3073 struct mlx5_ifc_phys_layer_cntrs_bits phys_layer_cntrs; 3074 struct mlx5_ifc_phys_layer_statistical_cntrs_bits phys_layer_statistical_cntrs; 3075 u8 reserved_at_0[0x7c0]; 3076 }; 3077 3078 union mlx5_ifc_pcie_cntrs_grp_data_layout_auto_bits { 3079 struct mlx5_ifc_pcie_perf_cntrs_grp_data_layout_bits pcie_perf_cntrs_grp_data_layout; 3080 u8 reserved_at_0[0x7c0]; 3081 }; 3082 3083 union mlx5_ifc_event_auto_bits { 3084 struct mlx5_ifc_comp_event_bits comp_event; 3085 struct mlx5_ifc_dct_events_bits dct_events; 3086 struct mlx5_ifc_qp_events_bits qp_events; 3087 struct mlx5_ifc_wqe_associated_page_fault_event_bits wqe_associated_page_fault_event; 3088 struct mlx5_ifc_rdma_page_fault_event_bits rdma_page_fault_event; 3089 struct mlx5_ifc_cq_error_bits cq_error; 3090 struct mlx5_ifc_dropped_packet_logged_bits dropped_packet_logged; 3091 struct mlx5_ifc_port_state_change_event_bits port_state_change_event; 3092 struct mlx5_ifc_gpio_event_bits gpio_event; 3093 struct mlx5_ifc_db_bf_congestion_event_bits db_bf_congestion_event; 3094 struct mlx5_ifc_stall_vl_event_bits stall_vl_event; 3095 struct mlx5_ifc_cmd_inter_comp_event_bits cmd_inter_comp_event; 3096 u8 reserved_at_0[0xe0]; 3097 }; 3098 3099 struct mlx5_ifc_health_buffer_bits { 3100 u8 reserved_at_0[0x100]; 3101 3102 u8 assert_existptr[0x20]; 3103 3104 u8 assert_callra[0x20]; 3105 3106 u8 reserved_at_140[0x40]; 3107 3108 u8 fw_version[0x20]; 3109 3110 u8 hw_id[0x20]; 3111 3112 u8 reserved_at_1c0[0x20]; 3113 3114 u8 irisc_index[0x8]; 3115 u8 synd[0x8]; 3116 u8 ext_synd[0x10]; 3117 }; 3118 3119 struct mlx5_ifc_register_loopback_control_bits { 3120 u8 no_lb[0x1]; 3121 u8 reserved_at_1[0x7]; 3122 u8 port[0x8]; 3123 u8 reserved_at_10[0x10]; 3124 3125 u8 reserved_at_20[0x60]; 3126 }; 3127 3128 struct mlx5_ifc_vport_tc_element_bits { 3129 u8 traffic_class[0x4]; 3130 u8 reserved_at_4[0xc]; 3131 u8 vport_number[0x10]; 3132 }; 3133 3134 struct mlx5_ifc_vport_element_bits { 3135 u8 reserved_at_0[0x10]; 3136 u8 vport_number[0x10]; 3137 }; 3138 3139 enum { 3140 TSAR_ELEMENT_TSAR_TYPE_DWRR = 0x0, 3141 TSAR_ELEMENT_TSAR_TYPE_ROUND_ROBIN = 0x1, 3142 TSAR_ELEMENT_TSAR_TYPE_ETS = 0x2, 3143 }; 3144 3145 struct mlx5_ifc_tsar_element_bits { 3146 u8 reserved_at_0[0x8]; 3147 u8 tsar_type[0x8]; 3148 u8 reserved_at_10[0x10]; 3149 }; 3150 3151 enum { 3152 MLX5_TEARDOWN_HCA_OUT_FORCE_STATE_SUCCESS = 0x0, 3153 MLX5_TEARDOWN_HCA_OUT_FORCE_STATE_FAIL = 0x1, 3154 }; 3155 3156 struct mlx5_ifc_teardown_hca_out_bits { 3157 u8 status[0x8]; 3158 u8 reserved_at_8[0x18]; 3159 3160 u8 syndrome[0x20]; 3161 3162 u8 reserved_at_40[0x3f]; 3163 3164 u8 force_state[0x1]; 3165 }; 3166 3167 enum { 3168 MLX5_TEARDOWN_HCA_IN_PROFILE_GRACEFUL_CLOSE = 0x0, 3169 MLX5_TEARDOWN_HCA_IN_PROFILE_FORCE_CLOSE = 0x1, 3170 }; 3171 3172 struct mlx5_ifc_teardown_hca_in_bits { 3173 u8 opcode[0x10]; 3174 u8 reserved_at_10[0x10]; 3175 3176 u8 reserved_at_20[0x10]; 3177 u8 op_mod[0x10]; 3178 3179 u8 reserved_at_40[0x10]; 3180 u8 profile[0x10]; 3181 3182 u8 reserved_at_60[0x20]; 3183 }; 3184 3185 struct mlx5_ifc_sqerr2rts_qp_out_bits { 3186 u8 status[0x8]; 3187 u8 reserved_at_8[0x18]; 3188 3189 u8 syndrome[0x20]; 3190 3191 u8 reserved_at_40[0x40]; 3192 }; 3193 3194 struct mlx5_ifc_sqerr2rts_qp_in_bits { 3195 u8 opcode[0x10]; 3196 u8 reserved_at_10[0x10]; 3197 3198 u8 reserved_at_20[0x10]; 3199 u8 op_mod[0x10]; 3200 3201 u8 reserved_at_40[0x8]; 3202 u8 qpn[0x18]; 3203 3204 u8 reserved_at_60[0x20]; 3205 3206 u8 opt_param_mask[0x20]; 3207 3208 u8 reserved_at_a0[0x20]; 3209 3210 struct mlx5_ifc_qpc_bits qpc; 3211 3212 u8 reserved_at_800[0x80]; 3213 }; 3214 3215 struct mlx5_ifc_sqd2rts_qp_out_bits { 3216 u8 status[0x8]; 3217 u8 reserved_at_8[0x18]; 3218 3219 u8 syndrome[0x20]; 3220 3221 u8 reserved_at_40[0x40]; 3222 }; 3223 3224 struct mlx5_ifc_sqd2rts_qp_in_bits { 3225 u8 opcode[0x10]; 3226 u8 reserved_at_10[0x10]; 3227 3228 u8 reserved_at_20[0x10]; 3229 u8 op_mod[0x10]; 3230 3231 u8 reserved_at_40[0x8]; 3232 u8 qpn[0x18]; 3233 3234 u8 reserved_at_60[0x20]; 3235 3236 u8 opt_param_mask[0x20]; 3237 3238 u8 reserved_at_a0[0x20]; 3239 3240 struct mlx5_ifc_qpc_bits qpc; 3241 3242 u8 reserved_at_800[0x80]; 3243 }; 3244 3245 struct mlx5_ifc_set_roce_address_out_bits { 3246 u8 status[0x8]; 3247 u8 reserved_at_8[0x18]; 3248 3249 u8 syndrome[0x20]; 3250 3251 u8 reserved_at_40[0x40]; 3252 }; 3253 3254 struct mlx5_ifc_set_roce_address_in_bits { 3255 u8 opcode[0x10]; 3256 u8 reserved_at_10[0x10]; 3257 3258 u8 reserved_at_20[0x10]; 3259 u8 op_mod[0x10]; 3260 3261 u8 roce_address_index[0x10]; 3262 u8 reserved_at_50[0x10]; 3263 3264 u8 reserved_at_60[0x20]; 3265 3266 struct mlx5_ifc_roce_addr_layout_bits roce_address; 3267 }; 3268 3269 struct mlx5_ifc_set_mad_demux_out_bits { 3270 u8 status[0x8]; 3271 u8 reserved_at_8[0x18]; 3272 3273 u8 syndrome[0x20]; 3274 3275 u8 reserved_at_40[0x40]; 3276 }; 3277 3278 enum { 3279 MLX5_SET_MAD_DEMUX_IN_DEMUX_MODE_PASS_ALL = 0x0, 3280 MLX5_SET_MAD_DEMUX_IN_DEMUX_MODE_SELECTIVE = 0x2, 3281 }; 3282 3283 struct mlx5_ifc_set_mad_demux_in_bits { 3284 u8 opcode[0x10]; 3285 u8 reserved_at_10[0x10]; 3286 3287 u8 reserved_at_20[0x10]; 3288 u8 op_mod[0x10]; 3289 3290 u8 reserved_at_40[0x20]; 3291 3292 u8 reserved_at_60[0x6]; 3293 u8 demux_mode[0x2]; 3294 u8 reserved_at_68[0x18]; 3295 }; 3296 3297 struct mlx5_ifc_set_l2_table_entry_out_bits { 3298 u8 status[0x8]; 3299 u8 reserved_at_8[0x18]; 3300 3301 u8 syndrome[0x20]; 3302 3303 u8 reserved_at_40[0x40]; 3304 }; 3305 3306 struct mlx5_ifc_set_l2_table_entry_in_bits { 3307 u8 opcode[0x10]; 3308 u8 reserved_at_10[0x10]; 3309 3310 u8 reserved_at_20[0x10]; 3311 u8 op_mod[0x10]; 3312 3313 u8 reserved_at_40[0x60]; 3314 3315 u8 reserved_at_a0[0x8]; 3316 u8 table_index[0x18]; 3317 3318 u8 reserved_at_c0[0x20]; 3319 3320 u8 reserved_at_e0[0x13]; 3321 u8 vlan_valid[0x1]; 3322 u8 vlan[0xc]; 3323 3324 struct mlx5_ifc_mac_address_layout_bits mac_address; 3325 3326 u8 reserved_at_140[0xc0]; 3327 }; 3328 3329 struct mlx5_ifc_set_issi_out_bits { 3330 u8 status[0x8]; 3331 u8 reserved_at_8[0x18]; 3332 3333 u8 syndrome[0x20]; 3334 3335 u8 reserved_at_40[0x40]; 3336 }; 3337 3338 struct mlx5_ifc_set_issi_in_bits { 3339 u8 opcode[0x10]; 3340 u8 reserved_at_10[0x10]; 3341 3342 u8 reserved_at_20[0x10]; 3343 u8 op_mod[0x10]; 3344 3345 u8 reserved_at_40[0x10]; 3346 u8 current_issi[0x10]; 3347 3348 u8 reserved_at_60[0x20]; 3349 }; 3350 3351 struct mlx5_ifc_set_hca_cap_out_bits { 3352 u8 status[0x8]; 3353 u8 reserved_at_8[0x18]; 3354 3355 u8 syndrome[0x20]; 3356 3357 u8 reserved_at_40[0x40]; 3358 }; 3359 3360 struct mlx5_ifc_set_hca_cap_in_bits { 3361 u8 opcode[0x10]; 3362 u8 reserved_at_10[0x10]; 3363 3364 u8 reserved_at_20[0x10]; 3365 u8 op_mod[0x10]; 3366 3367 u8 reserved_at_40[0x40]; 3368 3369 union mlx5_ifc_hca_cap_union_bits capability; 3370 }; 3371 3372 enum { 3373 MLX5_SET_FTE_MODIFY_ENABLE_MASK_ACTION = 0x0, 3374 MLX5_SET_FTE_MODIFY_ENABLE_MASK_FLOW_TAG = 0x1, 3375 MLX5_SET_FTE_MODIFY_ENABLE_MASK_DESTINATION_LIST = 0x2, 3376 MLX5_SET_FTE_MODIFY_ENABLE_MASK_FLOW_COUNTERS = 0x3 3377 }; 3378 3379 struct mlx5_ifc_set_fte_out_bits { 3380 u8 status[0x8]; 3381 u8 reserved_at_8[0x18]; 3382 3383 u8 syndrome[0x20]; 3384 3385 u8 reserved_at_40[0x40]; 3386 }; 3387 3388 struct mlx5_ifc_set_fte_in_bits { 3389 u8 opcode[0x10]; 3390 u8 reserved_at_10[0x10]; 3391 3392 u8 reserved_at_20[0x10]; 3393 u8 op_mod[0x10]; 3394 3395 u8 other_vport[0x1]; 3396 u8 reserved_at_41[0xf]; 3397 u8 vport_number[0x10]; 3398 3399 u8 reserved_at_60[0x20]; 3400 3401 u8 table_type[0x8]; 3402 u8 reserved_at_88[0x18]; 3403 3404 u8 reserved_at_a0[0x8]; 3405 u8 table_id[0x18]; 3406 3407 u8 reserved_at_c0[0x18]; 3408 u8 modify_enable_mask[0x8]; 3409 3410 u8 reserved_at_e0[0x20]; 3411 3412 u8 flow_index[0x20]; 3413 3414 u8 reserved_at_120[0xe0]; 3415 3416 struct mlx5_ifc_flow_context_bits flow_context; 3417 }; 3418 3419 struct mlx5_ifc_rts2rts_qp_out_bits { 3420 u8 status[0x8]; 3421 u8 reserved_at_8[0x18]; 3422 3423 u8 syndrome[0x20]; 3424 3425 u8 reserved_at_40[0x40]; 3426 }; 3427 3428 struct mlx5_ifc_rts2rts_qp_in_bits { 3429 u8 opcode[0x10]; 3430 u8 reserved_at_10[0x10]; 3431 3432 u8 reserved_at_20[0x10]; 3433 u8 op_mod[0x10]; 3434 3435 u8 reserved_at_40[0x8]; 3436 u8 qpn[0x18]; 3437 3438 u8 reserved_at_60[0x20]; 3439 3440 u8 opt_param_mask[0x20]; 3441 3442 u8 reserved_at_a0[0x20]; 3443 3444 struct mlx5_ifc_qpc_bits qpc; 3445 3446 u8 reserved_at_800[0x80]; 3447 }; 3448 3449 struct mlx5_ifc_rtr2rts_qp_out_bits { 3450 u8 status[0x8]; 3451 u8 reserved_at_8[0x18]; 3452 3453 u8 syndrome[0x20]; 3454 3455 u8 reserved_at_40[0x40]; 3456 }; 3457 3458 struct mlx5_ifc_rtr2rts_qp_in_bits { 3459 u8 opcode[0x10]; 3460 u8 reserved_at_10[0x10]; 3461 3462 u8 reserved_at_20[0x10]; 3463 u8 op_mod[0x10]; 3464 3465 u8 reserved_at_40[0x8]; 3466 u8 qpn[0x18]; 3467 3468 u8 reserved_at_60[0x20]; 3469 3470 u8 opt_param_mask[0x20]; 3471 3472 u8 reserved_at_a0[0x20]; 3473 3474 struct mlx5_ifc_qpc_bits qpc; 3475 3476 u8 reserved_at_800[0x80]; 3477 }; 3478 3479 struct mlx5_ifc_rst2init_qp_out_bits { 3480 u8 status[0x8]; 3481 u8 reserved_at_8[0x18]; 3482 3483 u8 syndrome[0x20]; 3484 3485 u8 reserved_at_40[0x40]; 3486 }; 3487 3488 struct mlx5_ifc_rst2init_qp_in_bits { 3489 u8 opcode[0x10]; 3490 u8 reserved_at_10[0x10]; 3491 3492 u8 reserved_at_20[0x10]; 3493 u8 op_mod[0x10]; 3494 3495 u8 reserved_at_40[0x8]; 3496 u8 qpn[0x18]; 3497 3498 u8 reserved_at_60[0x20]; 3499 3500 u8 opt_param_mask[0x20]; 3501 3502 u8 reserved_at_a0[0x20]; 3503 3504 struct mlx5_ifc_qpc_bits qpc; 3505 3506 u8 reserved_at_800[0x80]; 3507 }; 3508 3509 struct mlx5_ifc_query_xrq_out_bits { 3510 u8 status[0x8]; 3511 u8 reserved_at_8[0x18]; 3512 3513 u8 syndrome[0x20]; 3514 3515 u8 reserved_at_40[0x40]; 3516 3517 struct mlx5_ifc_xrqc_bits xrq_context; 3518 }; 3519 3520 struct mlx5_ifc_query_xrq_in_bits { 3521 u8 opcode[0x10]; 3522 u8 reserved_at_10[0x10]; 3523 3524 u8 reserved_at_20[0x10]; 3525 u8 op_mod[0x10]; 3526 3527 u8 reserved_at_40[0x8]; 3528 u8 xrqn[0x18]; 3529 3530 u8 reserved_at_60[0x20]; 3531 }; 3532 3533 struct mlx5_ifc_query_xrc_srq_out_bits { 3534 u8 status[0x8]; 3535 u8 reserved_at_8[0x18]; 3536 3537 u8 syndrome[0x20]; 3538 3539 u8 reserved_at_40[0x40]; 3540 3541 struct mlx5_ifc_xrc_srqc_bits xrc_srq_context_entry; 3542 3543 u8 reserved_at_280[0x600]; 3544 3545 u8 pas[0][0x40]; 3546 }; 3547 3548 struct mlx5_ifc_query_xrc_srq_in_bits { 3549 u8 opcode[0x10]; 3550 u8 reserved_at_10[0x10]; 3551 3552 u8 reserved_at_20[0x10]; 3553 u8 op_mod[0x10]; 3554 3555 u8 reserved_at_40[0x8]; 3556 u8 xrc_srqn[0x18]; 3557 3558 u8 reserved_at_60[0x20]; 3559 }; 3560 3561 enum { 3562 MLX5_QUERY_VPORT_STATE_OUT_STATE_DOWN = 0x0, 3563 MLX5_QUERY_VPORT_STATE_OUT_STATE_UP = 0x1, 3564 }; 3565 3566 struct mlx5_ifc_query_vport_state_out_bits { 3567 u8 status[0x8]; 3568 u8 reserved_at_8[0x18]; 3569 3570 u8 syndrome[0x20]; 3571 3572 u8 reserved_at_40[0x20]; 3573 3574 u8 reserved_at_60[0x18]; 3575 u8 admin_state[0x4]; 3576 u8 state[0x4]; 3577 }; 3578 3579 enum { 3580 MLX5_QUERY_VPORT_STATE_IN_OP_MOD_VNIC_VPORT = 0x0, 3581 MLX5_QUERY_VPORT_STATE_IN_OP_MOD_ESW_VPORT = 0x1, 3582 }; 3583 3584 struct mlx5_ifc_query_vport_state_in_bits { 3585 u8 opcode[0x10]; 3586 u8 reserved_at_10[0x10]; 3587 3588 u8 reserved_at_20[0x10]; 3589 u8 op_mod[0x10]; 3590 3591 u8 other_vport[0x1]; 3592 u8 reserved_at_41[0xf]; 3593 u8 vport_number[0x10]; 3594 3595 u8 reserved_at_60[0x20]; 3596 }; 3597 3598 struct mlx5_ifc_query_vport_counter_out_bits { 3599 u8 status[0x8]; 3600 u8 reserved_at_8[0x18]; 3601 3602 u8 syndrome[0x20]; 3603 3604 u8 reserved_at_40[0x40]; 3605 3606 struct mlx5_ifc_traffic_counter_bits received_errors; 3607 3608 struct mlx5_ifc_traffic_counter_bits transmit_errors; 3609 3610 struct mlx5_ifc_traffic_counter_bits received_ib_unicast; 3611 3612 struct mlx5_ifc_traffic_counter_bits transmitted_ib_unicast; 3613 3614 struct mlx5_ifc_traffic_counter_bits received_ib_multicast; 3615 3616 struct mlx5_ifc_traffic_counter_bits transmitted_ib_multicast; 3617 3618 struct mlx5_ifc_traffic_counter_bits received_eth_broadcast; 3619 3620 struct mlx5_ifc_traffic_counter_bits transmitted_eth_broadcast; 3621 3622 struct mlx5_ifc_traffic_counter_bits received_eth_unicast; 3623 3624 struct mlx5_ifc_traffic_counter_bits transmitted_eth_unicast; 3625 3626 struct mlx5_ifc_traffic_counter_bits received_eth_multicast; 3627 3628 struct mlx5_ifc_traffic_counter_bits transmitted_eth_multicast; 3629 3630 u8 reserved_at_680[0xa00]; 3631 }; 3632 3633 enum { 3634 MLX5_QUERY_VPORT_COUNTER_IN_OP_MOD_VPORT_COUNTERS = 0x0, 3635 }; 3636 3637 struct mlx5_ifc_query_vport_counter_in_bits { 3638 u8 opcode[0x10]; 3639 u8 reserved_at_10[0x10]; 3640 3641 u8 reserved_at_20[0x10]; 3642 u8 op_mod[0x10]; 3643 3644 u8 other_vport[0x1]; 3645 u8 reserved_at_41[0xb]; 3646 u8 port_num[0x4]; 3647 u8 vport_number[0x10]; 3648 3649 u8 reserved_at_60[0x60]; 3650 3651 u8 clear[0x1]; 3652 u8 reserved_at_c1[0x1f]; 3653 3654 u8 reserved_at_e0[0x20]; 3655 }; 3656 3657 struct mlx5_ifc_query_tis_out_bits { 3658 u8 status[0x8]; 3659 u8 reserved_at_8[0x18]; 3660 3661 u8 syndrome[0x20]; 3662 3663 u8 reserved_at_40[0x40]; 3664 3665 struct mlx5_ifc_tisc_bits tis_context; 3666 }; 3667 3668 struct mlx5_ifc_query_tis_in_bits { 3669 u8 opcode[0x10]; 3670 u8 reserved_at_10[0x10]; 3671 3672 u8 reserved_at_20[0x10]; 3673 u8 op_mod[0x10]; 3674 3675 u8 reserved_at_40[0x8]; 3676 u8 tisn[0x18]; 3677 3678 u8 reserved_at_60[0x20]; 3679 }; 3680 3681 struct mlx5_ifc_query_tir_out_bits { 3682 u8 status[0x8]; 3683 u8 reserved_at_8[0x18]; 3684 3685 u8 syndrome[0x20]; 3686 3687 u8 reserved_at_40[0xc0]; 3688 3689 struct mlx5_ifc_tirc_bits tir_context; 3690 }; 3691 3692 struct mlx5_ifc_query_tir_in_bits { 3693 u8 opcode[0x10]; 3694 u8 reserved_at_10[0x10]; 3695 3696 u8 reserved_at_20[0x10]; 3697 u8 op_mod[0x10]; 3698 3699 u8 reserved_at_40[0x8]; 3700 u8 tirn[0x18]; 3701 3702 u8 reserved_at_60[0x20]; 3703 }; 3704 3705 struct mlx5_ifc_query_srq_out_bits { 3706 u8 status[0x8]; 3707 u8 reserved_at_8[0x18]; 3708 3709 u8 syndrome[0x20]; 3710 3711 u8 reserved_at_40[0x40]; 3712 3713 struct mlx5_ifc_srqc_bits srq_context_entry; 3714 3715 u8 reserved_at_280[0x600]; 3716 3717 u8 pas[0][0x40]; 3718 }; 3719 3720 struct mlx5_ifc_query_srq_in_bits { 3721 u8 opcode[0x10]; 3722 u8 reserved_at_10[0x10]; 3723 3724 u8 reserved_at_20[0x10]; 3725 u8 op_mod[0x10]; 3726 3727 u8 reserved_at_40[0x8]; 3728 u8 srqn[0x18]; 3729 3730 u8 reserved_at_60[0x20]; 3731 }; 3732 3733 struct mlx5_ifc_query_sq_out_bits { 3734 u8 status[0x8]; 3735 u8 reserved_at_8[0x18]; 3736 3737 u8 syndrome[0x20]; 3738 3739 u8 reserved_at_40[0xc0]; 3740 3741 struct mlx5_ifc_sqc_bits sq_context; 3742 }; 3743 3744 struct mlx5_ifc_query_sq_in_bits { 3745 u8 opcode[0x10]; 3746 u8 reserved_at_10[0x10]; 3747 3748 u8 reserved_at_20[0x10]; 3749 u8 op_mod[0x10]; 3750 3751 u8 reserved_at_40[0x8]; 3752 u8 sqn[0x18]; 3753 3754 u8 reserved_at_60[0x20]; 3755 }; 3756 3757 struct mlx5_ifc_query_special_contexts_out_bits { 3758 u8 status[0x8]; 3759 u8 reserved_at_8[0x18]; 3760 3761 u8 syndrome[0x20]; 3762 3763 u8 dump_fill_mkey[0x20]; 3764 3765 u8 resd_lkey[0x20]; 3766 3767 u8 null_mkey[0x20]; 3768 3769 u8 reserved_at_a0[0x60]; 3770 }; 3771 3772 struct mlx5_ifc_query_special_contexts_in_bits { 3773 u8 opcode[0x10]; 3774 u8 reserved_at_10[0x10]; 3775 3776 u8 reserved_at_20[0x10]; 3777 u8 op_mod[0x10]; 3778 3779 u8 reserved_at_40[0x40]; 3780 }; 3781 3782 struct mlx5_ifc_query_scheduling_element_out_bits { 3783 u8 opcode[0x10]; 3784 u8 reserved_at_10[0x10]; 3785 3786 u8 reserved_at_20[0x10]; 3787 u8 op_mod[0x10]; 3788 3789 u8 reserved_at_40[0xc0]; 3790 3791 struct mlx5_ifc_scheduling_context_bits scheduling_context; 3792 3793 u8 reserved_at_300[0x100]; 3794 }; 3795 3796 enum { 3797 SCHEDULING_HIERARCHY_E_SWITCH = 0x2, 3798 }; 3799 3800 struct mlx5_ifc_query_scheduling_element_in_bits { 3801 u8 opcode[0x10]; 3802 u8 reserved_at_10[0x10]; 3803 3804 u8 reserved_at_20[0x10]; 3805 u8 op_mod[0x10]; 3806 3807 u8 scheduling_hierarchy[0x8]; 3808 u8 reserved_at_48[0x18]; 3809 3810 u8 scheduling_element_id[0x20]; 3811 3812 u8 reserved_at_80[0x180]; 3813 }; 3814 3815 struct mlx5_ifc_query_rqt_out_bits { 3816 u8 status[0x8]; 3817 u8 reserved_at_8[0x18]; 3818 3819 u8 syndrome[0x20]; 3820 3821 u8 reserved_at_40[0xc0]; 3822 3823 struct mlx5_ifc_rqtc_bits rqt_context; 3824 }; 3825 3826 struct mlx5_ifc_query_rqt_in_bits { 3827 u8 opcode[0x10]; 3828 u8 reserved_at_10[0x10]; 3829 3830 u8 reserved_at_20[0x10]; 3831 u8 op_mod[0x10]; 3832 3833 u8 reserved_at_40[0x8]; 3834 u8 rqtn[0x18]; 3835 3836 u8 reserved_at_60[0x20]; 3837 }; 3838 3839 struct mlx5_ifc_query_rq_out_bits { 3840 u8 status[0x8]; 3841 u8 reserved_at_8[0x18]; 3842 3843 u8 syndrome[0x20]; 3844 3845 u8 reserved_at_40[0xc0]; 3846 3847 struct mlx5_ifc_rqc_bits rq_context; 3848 }; 3849 3850 struct mlx5_ifc_query_rq_in_bits { 3851 u8 opcode[0x10]; 3852 u8 reserved_at_10[0x10]; 3853 3854 u8 reserved_at_20[0x10]; 3855 u8 op_mod[0x10]; 3856 3857 u8 reserved_at_40[0x8]; 3858 u8 rqn[0x18]; 3859 3860 u8 reserved_at_60[0x20]; 3861 }; 3862 3863 struct mlx5_ifc_query_roce_address_out_bits { 3864 u8 status[0x8]; 3865 u8 reserved_at_8[0x18]; 3866 3867 u8 syndrome[0x20]; 3868 3869 u8 reserved_at_40[0x40]; 3870 3871 struct mlx5_ifc_roce_addr_layout_bits roce_address; 3872 }; 3873 3874 struct mlx5_ifc_query_roce_address_in_bits { 3875 u8 opcode[0x10]; 3876 u8 reserved_at_10[0x10]; 3877 3878 u8 reserved_at_20[0x10]; 3879 u8 op_mod[0x10]; 3880 3881 u8 roce_address_index[0x10]; 3882 u8 reserved_at_50[0x10]; 3883 3884 u8 reserved_at_60[0x20]; 3885 }; 3886 3887 struct mlx5_ifc_query_rmp_out_bits { 3888 u8 status[0x8]; 3889 u8 reserved_at_8[0x18]; 3890 3891 u8 syndrome[0x20]; 3892 3893 u8 reserved_at_40[0xc0]; 3894 3895 struct mlx5_ifc_rmpc_bits rmp_context; 3896 }; 3897 3898 struct mlx5_ifc_query_rmp_in_bits { 3899 u8 opcode[0x10]; 3900 u8 reserved_at_10[0x10]; 3901 3902 u8 reserved_at_20[0x10]; 3903 u8 op_mod[0x10]; 3904 3905 u8 reserved_at_40[0x8]; 3906 u8 rmpn[0x18]; 3907 3908 u8 reserved_at_60[0x20]; 3909 }; 3910 3911 struct mlx5_ifc_query_qp_out_bits { 3912 u8 status[0x8]; 3913 u8 reserved_at_8[0x18]; 3914 3915 u8 syndrome[0x20]; 3916 3917 u8 reserved_at_40[0x40]; 3918 3919 u8 opt_param_mask[0x20]; 3920 3921 u8 reserved_at_a0[0x20]; 3922 3923 struct mlx5_ifc_qpc_bits qpc; 3924 3925 u8 reserved_at_800[0x80]; 3926 3927 u8 pas[0][0x40]; 3928 }; 3929 3930 struct mlx5_ifc_query_qp_in_bits { 3931 u8 opcode[0x10]; 3932 u8 reserved_at_10[0x10]; 3933 3934 u8 reserved_at_20[0x10]; 3935 u8 op_mod[0x10]; 3936 3937 u8 reserved_at_40[0x8]; 3938 u8 qpn[0x18]; 3939 3940 u8 reserved_at_60[0x20]; 3941 }; 3942 3943 struct mlx5_ifc_query_q_counter_out_bits { 3944 u8 status[0x8]; 3945 u8 reserved_at_8[0x18]; 3946 3947 u8 syndrome[0x20]; 3948 3949 u8 reserved_at_40[0x40]; 3950 3951 u8 rx_write_requests[0x20]; 3952 3953 u8 reserved_at_a0[0x20]; 3954 3955 u8 rx_read_requests[0x20]; 3956 3957 u8 reserved_at_e0[0x20]; 3958 3959 u8 rx_atomic_requests[0x20]; 3960 3961 u8 reserved_at_120[0x20]; 3962 3963 u8 rx_dct_connect[0x20]; 3964 3965 u8 reserved_at_160[0x20]; 3966 3967 u8 out_of_buffer[0x20]; 3968 3969 u8 reserved_at_1a0[0x20]; 3970 3971 u8 out_of_sequence[0x20]; 3972 3973 u8 reserved_at_1e0[0x20]; 3974 3975 u8 duplicate_request[0x20]; 3976 3977 u8 reserved_at_220[0x20]; 3978 3979 u8 rnr_nak_retry_err[0x20]; 3980 3981 u8 reserved_at_260[0x20]; 3982 3983 u8 packet_seq_err[0x20]; 3984 3985 u8 reserved_at_2a0[0x20]; 3986 3987 u8 implied_nak_seq_err[0x20]; 3988 3989 u8 reserved_at_2e0[0x20]; 3990 3991 u8 local_ack_timeout_err[0x20]; 3992 3993 u8 reserved_at_320[0xa0]; 3994 3995 u8 resp_local_length_error[0x20]; 3996 3997 u8 req_local_length_error[0x20]; 3998 3999 u8 resp_local_qp_error[0x20]; 4000 4001 u8 local_operation_error[0x20]; 4002 4003 u8 resp_local_protection[0x20]; 4004 4005 u8 req_local_protection[0x20]; 4006 4007 u8 resp_cqe_error[0x20]; 4008 4009 u8 req_cqe_error[0x20]; 4010 4011 u8 req_mw_binding[0x20]; 4012 4013 u8 req_bad_response[0x20]; 4014 4015 u8 req_remote_invalid_request[0x20]; 4016 4017 u8 resp_remote_invalid_request[0x20]; 4018 4019 u8 req_remote_access_errors[0x20]; 4020 4021 u8 resp_remote_access_errors[0x20]; 4022 4023 u8 req_remote_operation_errors[0x20]; 4024 4025 u8 req_transport_retries_exceeded[0x20]; 4026 4027 u8 cq_overflow[0x20]; 4028 4029 u8 resp_cqe_flush_error[0x20]; 4030 4031 u8 req_cqe_flush_error[0x20]; 4032 4033 u8 reserved_at_620[0x1e0]; 4034 }; 4035 4036 struct mlx5_ifc_query_q_counter_in_bits { 4037 u8 opcode[0x10]; 4038 u8 reserved_at_10[0x10]; 4039 4040 u8 reserved_at_20[0x10]; 4041 u8 op_mod[0x10]; 4042 4043 u8 reserved_at_40[0x80]; 4044 4045 u8 clear[0x1]; 4046 u8 reserved_at_c1[0x1f]; 4047 4048 u8 reserved_at_e0[0x18]; 4049 u8 counter_set_id[0x8]; 4050 }; 4051 4052 struct mlx5_ifc_query_pages_out_bits { 4053 u8 status[0x8]; 4054 u8 reserved_at_8[0x18]; 4055 4056 u8 syndrome[0x20]; 4057 4058 u8 reserved_at_40[0x10]; 4059 u8 function_id[0x10]; 4060 4061 u8 num_pages[0x20]; 4062 }; 4063 4064 enum { 4065 MLX5_QUERY_PAGES_IN_OP_MOD_BOOT_PAGES = 0x1, 4066 MLX5_QUERY_PAGES_IN_OP_MOD_INIT_PAGES = 0x2, 4067 MLX5_QUERY_PAGES_IN_OP_MOD_REGULAR_PAGES = 0x3, 4068 }; 4069 4070 struct mlx5_ifc_query_pages_in_bits { 4071 u8 opcode[0x10]; 4072 u8 reserved_at_10[0x10]; 4073 4074 u8 reserved_at_20[0x10]; 4075 u8 op_mod[0x10]; 4076 4077 u8 reserved_at_40[0x10]; 4078 u8 function_id[0x10]; 4079 4080 u8 reserved_at_60[0x20]; 4081 }; 4082 4083 struct mlx5_ifc_query_nic_vport_context_out_bits { 4084 u8 status[0x8]; 4085 u8 reserved_at_8[0x18]; 4086 4087 u8 syndrome[0x20]; 4088 4089 u8 reserved_at_40[0x40]; 4090 4091 struct mlx5_ifc_nic_vport_context_bits nic_vport_context; 4092 }; 4093 4094 struct mlx5_ifc_query_nic_vport_context_in_bits { 4095 u8 opcode[0x10]; 4096 u8 reserved_at_10[0x10]; 4097 4098 u8 reserved_at_20[0x10]; 4099 u8 op_mod[0x10]; 4100 4101 u8 other_vport[0x1]; 4102 u8 reserved_at_41[0xf]; 4103 u8 vport_number[0x10]; 4104 4105 u8 reserved_at_60[0x5]; 4106 u8 allowed_list_type[0x3]; 4107 u8 reserved_at_68[0x18]; 4108 }; 4109 4110 struct mlx5_ifc_query_mkey_out_bits { 4111 u8 status[0x8]; 4112 u8 reserved_at_8[0x18]; 4113 4114 u8 syndrome[0x20]; 4115 4116 u8 reserved_at_40[0x40]; 4117 4118 struct mlx5_ifc_mkc_bits memory_key_mkey_entry; 4119 4120 u8 reserved_at_280[0x600]; 4121 4122 u8 bsf0_klm0_pas_mtt0_1[16][0x8]; 4123 4124 u8 bsf1_klm1_pas_mtt2_3[16][0x8]; 4125 }; 4126 4127 struct mlx5_ifc_query_mkey_in_bits { 4128 u8 opcode[0x10]; 4129 u8 reserved_at_10[0x10]; 4130 4131 u8 reserved_at_20[0x10]; 4132 u8 op_mod[0x10]; 4133 4134 u8 reserved_at_40[0x8]; 4135 u8 mkey_index[0x18]; 4136 4137 u8 pg_access[0x1]; 4138 u8 reserved_at_61[0x1f]; 4139 }; 4140 4141 struct mlx5_ifc_query_mad_demux_out_bits { 4142 u8 status[0x8]; 4143 u8 reserved_at_8[0x18]; 4144 4145 u8 syndrome[0x20]; 4146 4147 u8 reserved_at_40[0x40]; 4148 4149 u8 mad_dumux_parameters_block[0x20]; 4150 }; 4151 4152 struct mlx5_ifc_query_mad_demux_in_bits { 4153 u8 opcode[0x10]; 4154 u8 reserved_at_10[0x10]; 4155 4156 u8 reserved_at_20[0x10]; 4157 u8 op_mod[0x10]; 4158 4159 u8 reserved_at_40[0x40]; 4160 }; 4161 4162 struct mlx5_ifc_query_l2_table_entry_out_bits { 4163 u8 status[0x8]; 4164 u8 reserved_at_8[0x18]; 4165 4166 u8 syndrome[0x20]; 4167 4168 u8 reserved_at_40[0xa0]; 4169 4170 u8 reserved_at_e0[0x13]; 4171 u8 vlan_valid[0x1]; 4172 u8 vlan[0xc]; 4173 4174 struct mlx5_ifc_mac_address_layout_bits mac_address; 4175 4176 u8 reserved_at_140[0xc0]; 4177 }; 4178 4179 struct mlx5_ifc_query_l2_table_entry_in_bits { 4180 u8 opcode[0x10]; 4181 u8 reserved_at_10[0x10]; 4182 4183 u8 reserved_at_20[0x10]; 4184 u8 op_mod[0x10]; 4185 4186 u8 reserved_at_40[0x60]; 4187 4188 u8 reserved_at_a0[0x8]; 4189 u8 table_index[0x18]; 4190 4191 u8 reserved_at_c0[0x140]; 4192 }; 4193 4194 struct mlx5_ifc_query_issi_out_bits { 4195 u8 status[0x8]; 4196 u8 reserved_at_8[0x18]; 4197 4198 u8 syndrome[0x20]; 4199 4200 u8 reserved_at_40[0x10]; 4201 u8 current_issi[0x10]; 4202 4203 u8 reserved_at_60[0xa0]; 4204 4205 u8 reserved_at_100[76][0x8]; 4206 u8 supported_issi_dw0[0x20]; 4207 }; 4208 4209 struct mlx5_ifc_query_issi_in_bits { 4210 u8 opcode[0x10]; 4211 u8 reserved_at_10[0x10]; 4212 4213 u8 reserved_at_20[0x10]; 4214 u8 op_mod[0x10]; 4215 4216 u8 reserved_at_40[0x40]; 4217 }; 4218 4219 struct mlx5_ifc_set_driver_version_out_bits { 4220 u8 status[0x8]; 4221 u8 reserved_0[0x18]; 4222 4223 u8 syndrome[0x20]; 4224 u8 reserved_1[0x40]; 4225 }; 4226 4227 struct mlx5_ifc_set_driver_version_in_bits { 4228 u8 opcode[0x10]; 4229 u8 reserved_0[0x10]; 4230 4231 u8 reserved_1[0x10]; 4232 u8 op_mod[0x10]; 4233 4234 u8 reserved_2[0x40]; 4235 u8 driver_version[64][0x8]; 4236 }; 4237 4238 struct mlx5_ifc_query_hca_vport_pkey_out_bits { 4239 u8 status[0x8]; 4240 u8 reserved_at_8[0x18]; 4241 4242 u8 syndrome[0x20]; 4243 4244 u8 reserved_at_40[0x40]; 4245 4246 struct mlx5_ifc_pkey_bits pkey[0]; 4247 }; 4248 4249 struct mlx5_ifc_query_hca_vport_pkey_in_bits { 4250 u8 opcode[0x10]; 4251 u8 reserved_at_10[0x10]; 4252 4253 u8 reserved_at_20[0x10]; 4254 u8 op_mod[0x10]; 4255 4256 u8 other_vport[0x1]; 4257 u8 reserved_at_41[0xb]; 4258 u8 port_num[0x4]; 4259 u8 vport_number[0x10]; 4260 4261 u8 reserved_at_60[0x10]; 4262 u8 pkey_index[0x10]; 4263 }; 4264 4265 enum { 4266 MLX5_HCA_VPORT_SEL_PORT_GUID = 1 << 0, 4267 MLX5_HCA_VPORT_SEL_NODE_GUID = 1 << 1, 4268 MLX5_HCA_VPORT_SEL_STATE_POLICY = 1 << 2, 4269 }; 4270 4271 struct mlx5_ifc_query_hca_vport_gid_out_bits { 4272 u8 status[0x8]; 4273 u8 reserved_at_8[0x18]; 4274 4275 u8 syndrome[0x20]; 4276 4277 u8 reserved_at_40[0x20]; 4278 4279 u8 gids_num[0x10]; 4280 u8 reserved_at_70[0x10]; 4281 4282 struct mlx5_ifc_array128_auto_bits gid[0]; 4283 }; 4284 4285 struct mlx5_ifc_query_hca_vport_gid_in_bits { 4286 u8 opcode[0x10]; 4287 u8 reserved_at_10[0x10]; 4288 4289 u8 reserved_at_20[0x10]; 4290 u8 op_mod[0x10]; 4291 4292 u8 other_vport[0x1]; 4293 u8 reserved_at_41[0xb]; 4294 u8 port_num[0x4]; 4295 u8 vport_number[0x10]; 4296 4297 u8 reserved_at_60[0x10]; 4298 u8 gid_index[0x10]; 4299 }; 4300 4301 struct mlx5_ifc_query_hca_vport_context_out_bits { 4302 u8 status[0x8]; 4303 u8 reserved_at_8[0x18]; 4304 4305 u8 syndrome[0x20]; 4306 4307 u8 reserved_at_40[0x40]; 4308 4309 struct mlx5_ifc_hca_vport_context_bits hca_vport_context; 4310 }; 4311 4312 struct mlx5_ifc_query_hca_vport_context_in_bits { 4313 u8 opcode[0x10]; 4314 u8 reserved_at_10[0x10]; 4315 4316 u8 reserved_at_20[0x10]; 4317 u8 op_mod[0x10]; 4318 4319 u8 other_vport[0x1]; 4320 u8 reserved_at_41[0xb]; 4321 u8 port_num[0x4]; 4322 u8 vport_number[0x10]; 4323 4324 u8 reserved_at_60[0x20]; 4325 }; 4326 4327 struct mlx5_ifc_query_hca_cap_out_bits { 4328 u8 status[0x8]; 4329 u8 reserved_at_8[0x18]; 4330 4331 u8 syndrome[0x20]; 4332 4333 u8 reserved_at_40[0x40]; 4334 4335 union mlx5_ifc_hca_cap_union_bits capability; 4336 }; 4337 4338 struct mlx5_ifc_query_hca_cap_in_bits { 4339 u8 opcode[0x10]; 4340 u8 reserved_at_10[0x10]; 4341 4342 u8 reserved_at_20[0x10]; 4343 u8 op_mod[0x10]; 4344 4345 u8 reserved_at_40[0x40]; 4346 }; 4347 4348 struct mlx5_ifc_query_flow_table_out_bits { 4349 u8 status[0x8]; 4350 u8 reserved_at_8[0x18]; 4351 4352 u8 syndrome[0x20]; 4353 4354 u8 reserved_at_40[0x80]; 4355 4356 u8 reserved_at_c0[0x8]; 4357 u8 level[0x8]; 4358 u8 reserved_at_d0[0x8]; 4359 u8 log_size[0x8]; 4360 4361 u8 reserved_at_e0[0x120]; 4362 }; 4363 4364 struct mlx5_ifc_query_flow_table_in_bits { 4365 u8 opcode[0x10]; 4366 u8 reserved_at_10[0x10]; 4367 4368 u8 reserved_at_20[0x10]; 4369 u8 op_mod[0x10]; 4370 4371 u8 reserved_at_40[0x40]; 4372 4373 u8 table_type[0x8]; 4374 u8 reserved_at_88[0x18]; 4375 4376 u8 reserved_at_a0[0x8]; 4377 u8 table_id[0x18]; 4378 4379 u8 reserved_at_c0[0x140]; 4380 }; 4381 4382 struct mlx5_ifc_query_fte_out_bits { 4383 u8 status[0x8]; 4384 u8 reserved_at_8[0x18]; 4385 4386 u8 syndrome[0x20]; 4387 4388 u8 reserved_at_40[0x1c0]; 4389 4390 struct mlx5_ifc_flow_context_bits flow_context; 4391 }; 4392 4393 struct mlx5_ifc_query_fte_in_bits { 4394 u8 opcode[0x10]; 4395 u8 reserved_at_10[0x10]; 4396 4397 u8 reserved_at_20[0x10]; 4398 u8 op_mod[0x10]; 4399 4400 u8 reserved_at_40[0x40]; 4401 4402 u8 table_type[0x8]; 4403 u8 reserved_at_88[0x18]; 4404 4405 u8 reserved_at_a0[0x8]; 4406 u8 table_id[0x18]; 4407 4408 u8 reserved_at_c0[0x40]; 4409 4410 u8 flow_index[0x20]; 4411 4412 u8 reserved_at_120[0xe0]; 4413 }; 4414 4415 enum { 4416 MLX5_QUERY_FLOW_GROUP_OUT_MATCH_CRITERIA_ENABLE_OUTER_HEADERS = 0x0, 4417 MLX5_QUERY_FLOW_GROUP_OUT_MATCH_CRITERIA_ENABLE_MISC_PARAMETERS = 0x1, 4418 MLX5_QUERY_FLOW_GROUP_OUT_MATCH_CRITERIA_ENABLE_INNER_HEADERS = 0x2, 4419 }; 4420 4421 struct mlx5_ifc_query_flow_group_out_bits { 4422 u8 status[0x8]; 4423 u8 reserved_at_8[0x18]; 4424 4425 u8 syndrome[0x20]; 4426 4427 u8 reserved_at_40[0xa0]; 4428 4429 u8 start_flow_index[0x20]; 4430 4431 u8 reserved_at_100[0x20]; 4432 4433 u8 end_flow_index[0x20]; 4434 4435 u8 reserved_at_140[0xa0]; 4436 4437 u8 reserved_at_1e0[0x18]; 4438 u8 match_criteria_enable[0x8]; 4439 4440 struct mlx5_ifc_fte_match_param_bits match_criteria; 4441 4442 u8 reserved_at_1200[0xe00]; 4443 }; 4444 4445 struct mlx5_ifc_query_flow_group_in_bits { 4446 u8 opcode[0x10]; 4447 u8 reserved_at_10[0x10]; 4448 4449 u8 reserved_at_20[0x10]; 4450 u8 op_mod[0x10]; 4451 4452 u8 reserved_at_40[0x40]; 4453 4454 u8 table_type[0x8]; 4455 u8 reserved_at_88[0x18]; 4456 4457 u8 reserved_at_a0[0x8]; 4458 u8 table_id[0x18]; 4459 4460 u8 group_id[0x20]; 4461 4462 u8 reserved_at_e0[0x120]; 4463 }; 4464 4465 struct mlx5_ifc_query_flow_counter_out_bits { 4466 u8 status[0x8]; 4467 u8 reserved_at_8[0x18]; 4468 4469 u8 syndrome[0x20]; 4470 4471 u8 reserved_at_40[0x40]; 4472 4473 struct mlx5_ifc_traffic_counter_bits flow_statistics[0]; 4474 }; 4475 4476 struct mlx5_ifc_query_flow_counter_in_bits { 4477 u8 opcode[0x10]; 4478 u8 reserved_at_10[0x10]; 4479 4480 u8 reserved_at_20[0x10]; 4481 u8 op_mod[0x10]; 4482 4483 u8 reserved_at_40[0x80]; 4484 4485 u8 clear[0x1]; 4486 u8 reserved_at_c1[0xf]; 4487 u8 num_of_counters[0x10]; 4488 4489 u8 flow_counter_id[0x20]; 4490 }; 4491 4492 struct mlx5_ifc_query_esw_vport_context_out_bits { 4493 u8 status[0x8]; 4494 u8 reserved_at_8[0x18]; 4495 4496 u8 syndrome[0x20]; 4497 4498 u8 reserved_at_40[0x40]; 4499 4500 struct mlx5_ifc_esw_vport_context_bits esw_vport_context; 4501 }; 4502 4503 struct mlx5_ifc_query_esw_vport_context_in_bits { 4504 u8 opcode[0x10]; 4505 u8 reserved_at_10[0x10]; 4506 4507 u8 reserved_at_20[0x10]; 4508 u8 op_mod[0x10]; 4509 4510 u8 other_vport[0x1]; 4511 u8 reserved_at_41[0xf]; 4512 u8 vport_number[0x10]; 4513 4514 u8 reserved_at_60[0x20]; 4515 }; 4516 4517 struct mlx5_ifc_modify_esw_vport_context_out_bits { 4518 u8 status[0x8]; 4519 u8 reserved_at_8[0x18]; 4520 4521 u8 syndrome[0x20]; 4522 4523 u8 reserved_at_40[0x40]; 4524 }; 4525 4526 struct mlx5_ifc_esw_vport_context_fields_select_bits { 4527 u8 reserved_at_0[0x1c]; 4528 u8 vport_cvlan_insert[0x1]; 4529 u8 vport_svlan_insert[0x1]; 4530 u8 vport_cvlan_strip[0x1]; 4531 u8 vport_svlan_strip[0x1]; 4532 }; 4533 4534 struct mlx5_ifc_modify_esw_vport_context_in_bits { 4535 u8 opcode[0x10]; 4536 u8 reserved_at_10[0x10]; 4537 4538 u8 reserved_at_20[0x10]; 4539 u8 op_mod[0x10]; 4540 4541 u8 other_vport[0x1]; 4542 u8 reserved_at_41[0xf]; 4543 u8 vport_number[0x10]; 4544 4545 struct mlx5_ifc_esw_vport_context_fields_select_bits field_select; 4546 4547 struct mlx5_ifc_esw_vport_context_bits esw_vport_context; 4548 }; 4549 4550 struct mlx5_ifc_query_eq_out_bits { 4551 u8 status[0x8]; 4552 u8 reserved_at_8[0x18]; 4553 4554 u8 syndrome[0x20]; 4555 4556 u8 reserved_at_40[0x40]; 4557 4558 struct mlx5_ifc_eqc_bits eq_context_entry; 4559 4560 u8 reserved_at_280[0x40]; 4561 4562 u8 event_bitmask[0x40]; 4563 4564 u8 reserved_at_300[0x580]; 4565 4566 u8 pas[0][0x40]; 4567 }; 4568 4569 struct mlx5_ifc_query_eq_in_bits { 4570 u8 opcode[0x10]; 4571 u8 reserved_at_10[0x10]; 4572 4573 u8 reserved_at_20[0x10]; 4574 u8 op_mod[0x10]; 4575 4576 u8 reserved_at_40[0x18]; 4577 u8 eq_number[0x8]; 4578 4579 u8 reserved_at_60[0x20]; 4580 }; 4581 4582 struct mlx5_ifc_encap_header_in_bits { 4583 u8 reserved_at_0[0x5]; 4584 u8 header_type[0x3]; 4585 u8 reserved_at_8[0xe]; 4586 u8 encap_header_size[0xa]; 4587 4588 u8 reserved_at_20[0x10]; 4589 u8 encap_header[2][0x8]; 4590 4591 u8 more_encap_header[0][0x8]; 4592 }; 4593 4594 struct mlx5_ifc_query_encap_header_out_bits { 4595 u8 status[0x8]; 4596 u8 reserved_at_8[0x18]; 4597 4598 u8 syndrome[0x20]; 4599 4600 u8 reserved_at_40[0xa0]; 4601 4602 struct mlx5_ifc_encap_header_in_bits encap_header[0]; 4603 }; 4604 4605 struct mlx5_ifc_query_encap_header_in_bits { 4606 u8 opcode[0x10]; 4607 u8 reserved_at_10[0x10]; 4608 4609 u8 reserved_at_20[0x10]; 4610 u8 op_mod[0x10]; 4611 4612 u8 encap_id[0x20]; 4613 4614 u8 reserved_at_60[0xa0]; 4615 }; 4616 4617 struct mlx5_ifc_alloc_encap_header_out_bits { 4618 u8 status[0x8]; 4619 u8 reserved_at_8[0x18]; 4620 4621 u8 syndrome[0x20]; 4622 4623 u8 encap_id[0x20]; 4624 4625 u8 reserved_at_60[0x20]; 4626 }; 4627 4628 struct mlx5_ifc_alloc_encap_header_in_bits { 4629 u8 opcode[0x10]; 4630 u8 reserved_at_10[0x10]; 4631 4632 u8 reserved_at_20[0x10]; 4633 u8 op_mod[0x10]; 4634 4635 u8 reserved_at_40[0xa0]; 4636 4637 struct mlx5_ifc_encap_header_in_bits encap_header; 4638 }; 4639 4640 struct mlx5_ifc_dealloc_encap_header_out_bits { 4641 u8 status[0x8]; 4642 u8 reserved_at_8[0x18]; 4643 4644 u8 syndrome[0x20]; 4645 4646 u8 reserved_at_40[0x40]; 4647 }; 4648 4649 struct mlx5_ifc_dealloc_encap_header_in_bits { 4650 u8 opcode[0x10]; 4651 u8 reserved_at_10[0x10]; 4652 4653 u8 reserved_20[0x10]; 4654 u8 op_mod[0x10]; 4655 4656 u8 encap_id[0x20]; 4657 4658 u8 reserved_60[0x20]; 4659 }; 4660 4661 struct mlx5_ifc_set_action_in_bits { 4662 u8 action_type[0x4]; 4663 u8 field[0xc]; 4664 u8 reserved_at_10[0x3]; 4665 u8 offset[0x5]; 4666 u8 reserved_at_18[0x3]; 4667 u8 length[0x5]; 4668 4669 u8 data[0x20]; 4670 }; 4671 4672 struct mlx5_ifc_add_action_in_bits { 4673 u8 action_type[0x4]; 4674 u8 field[0xc]; 4675 u8 reserved_at_10[0x10]; 4676 4677 u8 data[0x20]; 4678 }; 4679 4680 union mlx5_ifc_set_action_in_add_action_in_auto_bits { 4681 struct mlx5_ifc_set_action_in_bits set_action_in; 4682 struct mlx5_ifc_add_action_in_bits add_action_in; 4683 u8 reserved_at_0[0x40]; 4684 }; 4685 4686 enum { 4687 MLX5_ACTION_TYPE_SET = 0x1, 4688 MLX5_ACTION_TYPE_ADD = 0x2, 4689 }; 4690 4691 enum { 4692 MLX5_ACTION_IN_FIELD_OUT_SMAC_47_16 = 0x1, 4693 MLX5_ACTION_IN_FIELD_OUT_SMAC_15_0 = 0x2, 4694 MLX5_ACTION_IN_FIELD_OUT_ETHERTYPE = 0x3, 4695 MLX5_ACTION_IN_FIELD_OUT_DMAC_47_16 = 0x4, 4696 MLX5_ACTION_IN_FIELD_OUT_DMAC_15_0 = 0x5, 4697 MLX5_ACTION_IN_FIELD_OUT_IP_DSCP = 0x6, 4698 MLX5_ACTION_IN_FIELD_OUT_TCP_FLAGS = 0x7, 4699 MLX5_ACTION_IN_FIELD_OUT_TCP_SPORT = 0x8, 4700 MLX5_ACTION_IN_FIELD_OUT_TCP_DPORT = 0x9, 4701 MLX5_ACTION_IN_FIELD_OUT_IP_TTL = 0xa, 4702 MLX5_ACTION_IN_FIELD_OUT_UDP_SPORT = 0xb, 4703 MLX5_ACTION_IN_FIELD_OUT_UDP_DPORT = 0xc, 4704 MLX5_ACTION_IN_FIELD_OUT_SIPV6_127_96 = 0xd, 4705 MLX5_ACTION_IN_FIELD_OUT_SIPV6_95_64 = 0xe, 4706 MLX5_ACTION_IN_FIELD_OUT_SIPV6_63_32 = 0xf, 4707 MLX5_ACTION_IN_FIELD_OUT_SIPV6_31_0 = 0x10, 4708 MLX5_ACTION_IN_FIELD_OUT_DIPV6_127_96 = 0x11, 4709 MLX5_ACTION_IN_FIELD_OUT_DIPV6_95_64 = 0x12, 4710 MLX5_ACTION_IN_FIELD_OUT_DIPV6_63_32 = 0x13, 4711 MLX5_ACTION_IN_FIELD_OUT_DIPV6_31_0 = 0x14, 4712 MLX5_ACTION_IN_FIELD_OUT_SIPV4 = 0x15, 4713 MLX5_ACTION_IN_FIELD_OUT_DIPV4 = 0x16, 4714 MLX5_ACTION_IN_FIELD_OUT_IPV6_HOPLIMIT = 0x47, 4715 }; 4716 4717 struct mlx5_ifc_alloc_modify_header_context_out_bits { 4718 u8 status[0x8]; 4719 u8 reserved_at_8[0x18]; 4720 4721 u8 syndrome[0x20]; 4722 4723 u8 modify_header_id[0x20]; 4724 4725 u8 reserved_at_60[0x20]; 4726 }; 4727 4728 struct mlx5_ifc_alloc_modify_header_context_in_bits { 4729 u8 opcode[0x10]; 4730 u8 reserved_at_10[0x10]; 4731 4732 u8 reserved_at_20[0x10]; 4733 u8 op_mod[0x10]; 4734 4735 u8 reserved_at_40[0x20]; 4736 4737 u8 table_type[0x8]; 4738 u8 reserved_at_68[0x10]; 4739 u8 num_of_actions[0x8]; 4740 4741 union mlx5_ifc_set_action_in_add_action_in_auto_bits actions[0]; 4742 }; 4743 4744 struct mlx5_ifc_dealloc_modify_header_context_out_bits { 4745 u8 status[0x8]; 4746 u8 reserved_at_8[0x18]; 4747 4748 u8 syndrome[0x20]; 4749 4750 u8 reserved_at_40[0x40]; 4751 }; 4752 4753 struct mlx5_ifc_dealloc_modify_header_context_in_bits { 4754 u8 opcode[0x10]; 4755 u8 reserved_at_10[0x10]; 4756 4757 u8 reserved_at_20[0x10]; 4758 u8 op_mod[0x10]; 4759 4760 u8 modify_header_id[0x20]; 4761 4762 u8 reserved_at_60[0x20]; 4763 }; 4764 4765 struct mlx5_ifc_query_dct_out_bits { 4766 u8 status[0x8]; 4767 u8 reserved_at_8[0x18]; 4768 4769 u8 syndrome[0x20]; 4770 4771 u8 reserved_at_40[0x40]; 4772 4773 struct mlx5_ifc_dctc_bits dct_context_entry; 4774 4775 u8 reserved_at_280[0x180]; 4776 }; 4777 4778 struct mlx5_ifc_query_dct_in_bits { 4779 u8 opcode[0x10]; 4780 u8 reserved_at_10[0x10]; 4781 4782 u8 reserved_at_20[0x10]; 4783 u8 op_mod[0x10]; 4784 4785 u8 reserved_at_40[0x8]; 4786 u8 dctn[0x18]; 4787 4788 u8 reserved_at_60[0x20]; 4789 }; 4790 4791 struct mlx5_ifc_query_cq_out_bits { 4792 u8 status[0x8]; 4793 u8 reserved_at_8[0x18]; 4794 4795 u8 syndrome[0x20]; 4796 4797 u8 reserved_at_40[0x40]; 4798 4799 struct mlx5_ifc_cqc_bits cq_context; 4800 4801 u8 reserved_at_280[0x600]; 4802 4803 u8 pas[0][0x40]; 4804 }; 4805 4806 struct mlx5_ifc_query_cq_in_bits { 4807 u8 opcode[0x10]; 4808 u8 reserved_at_10[0x10]; 4809 4810 u8 reserved_at_20[0x10]; 4811 u8 op_mod[0x10]; 4812 4813 u8 reserved_at_40[0x8]; 4814 u8 cqn[0x18]; 4815 4816 u8 reserved_at_60[0x20]; 4817 }; 4818 4819 struct mlx5_ifc_query_cong_status_out_bits { 4820 u8 status[0x8]; 4821 u8 reserved_at_8[0x18]; 4822 4823 u8 syndrome[0x20]; 4824 4825 u8 reserved_at_40[0x20]; 4826 4827 u8 enable[0x1]; 4828 u8 tag_enable[0x1]; 4829 u8 reserved_at_62[0x1e]; 4830 }; 4831 4832 struct mlx5_ifc_query_cong_status_in_bits { 4833 u8 opcode[0x10]; 4834 u8 reserved_at_10[0x10]; 4835 4836 u8 reserved_at_20[0x10]; 4837 u8 op_mod[0x10]; 4838 4839 u8 reserved_at_40[0x18]; 4840 u8 priority[0x4]; 4841 u8 cong_protocol[0x4]; 4842 4843 u8 reserved_at_60[0x20]; 4844 }; 4845 4846 struct mlx5_ifc_query_cong_statistics_out_bits { 4847 u8 status[0x8]; 4848 u8 reserved_at_8[0x18]; 4849 4850 u8 syndrome[0x20]; 4851 4852 u8 reserved_at_40[0x40]; 4853 4854 u8 rp_cur_flows[0x20]; 4855 4856 u8 sum_flows[0x20]; 4857 4858 u8 rp_cnp_ignored_high[0x20]; 4859 4860 u8 rp_cnp_ignored_low[0x20]; 4861 4862 u8 rp_cnp_handled_high[0x20]; 4863 4864 u8 rp_cnp_handled_low[0x20]; 4865 4866 u8 reserved_at_140[0x100]; 4867 4868 u8 time_stamp_high[0x20]; 4869 4870 u8 time_stamp_low[0x20]; 4871 4872 u8 accumulators_period[0x20]; 4873 4874 u8 np_ecn_marked_roce_packets_high[0x20]; 4875 4876 u8 np_ecn_marked_roce_packets_low[0x20]; 4877 4878 u8 np_cnp_sent_high[0x20]; 4879 4880 u8 np_cnp_sent_low[0x20]; 4881 4882 u8 reserved_at_320[0x560]; 4883 }; 4884 4885 struct mlx5_ifc_query_cong_statistics_in_bits { 4886 u8 opcode[0x10]; 4887 u8 reserved_at_10[0x10]; 4888 4889 u8 reserved_at_20[0x10]; 4890 u8 op_mod[0x10]; 4891 4892 u8 clear[0x1]; 4893 u8 reserved_at_41[0x1f]; 4894 4895 u8 reserved_at_60[0x20]; 4896 }; 4897 4898 struct mlx5_ifc_query_cong_params_out_bits { 4899 u8 status[0x8]; 4900 u8 reserved_at_8[0x18]; 4901 4902 u8 syndrome[0x20]; 4903 4904 u8 reserved_at_40[0x40]; 4905 4906 union mlx5_ifc_cong_control_roce_ecn_auto_bits congestion_parameters; 4907 }; 4908 4909 struct mlx5_ifc_query_cong_params_in_bits { 4910 u8 opcode[0x10]; 4911 u8 reserved_at_10[0x10]; 4912 4913 u8 reserved_at_20[0x10]; 4914 u8 op_mod[0x10]; 4915 4916 u8 reserved_at_40[0x1c]; 4917 u8 cong_protocol[0x4]; 4918 4919 u8 reserved_at_60[0x20]; 4920 }; 4921 4922 struct mlx5_ifc_query_adapter_out_bits { 4923 u8 status[0x8]; 4924 u8 reserved_at_8[0x18]; 4925 4926 u8 syndrome[0x20]; 4927 4928 u8 reserved_at_40[0x40]; 4929 4930 struct mlx5_ifc_query_adapter_param_block_bits query_adapter_struct; 4931 }; 4932 4933 struct mlx5_ifc_query_adapter_in_bits { 4934 u8 opcode[0x10]; 4935 u8 reserved_at_10[0x10]; 4936 4937 u8 reserved_at_20[0x10]; 4938 u8 op_mod[0x10]; 4939 4940 u8 reserved_at_40[0x40]; 4941 }; 4942 4943 struct mlx5_ifc_qp_2rst_out_bits { 4944 u8 status[0x8]; 4945 u8 reserved_at_8[0x18]; 4946 4947 u8 syndrome[0x20]; 4948 4949 u8 reserved_at_40[0x40]; 4950 }; 4951 4952 struct mlx5_ifc_qp_2rst_in_bits { 4953 u8 opcode[0x10]; 4954 u8 reserved_at_10[0x10]; 4955 4956 u8 reserved_at_20[0x10]; 4957 u8 op_mod[0x10]; 4958 4959 u8 reserved_at_40[0x8]; 4960 u8 qpn[0x18]; 4961 4962 u8 reserved_at_60[0x20]; 4963 }; 4964 4965 struct mlx5_ifc_qp_2err_out_bits { 4966 u8 status[0x8]; 4967 u8 reserved_at_8[0x18]; 4968 4969 u8 syndrome[0x20]; 4970 4971 u8 reserved_at_40[0x40]; 4972 }; 4973 4974 struct mlx5_ifc_qp_2err_in_bits { 4975 u8 opcode[0x10]; 4976 u8 reserved_at_10[0x10]; 4977 4978 u8 reserved_at_20[0x10]; 4979 u8 op_mod[0x10]; 4980 4981 u8 reserved_at_40[0x8]; 4982 u8 qpn[0x18]; 4983 4984 u8 reserved_at_60[0x20]; 4985 }; 4986 4987 struct mlx5_ifc_page_fault_resume_out_bits { 4988 u8 status[0x8]; 4989 u8 reserved_at_8[0x18]; 4990 4991 u8 syndrome[0x20]; 4992 4993 u8 reserved_at_40[0x40]; 4994 }; 4995 4996 struct mlx5_ifc_page_fault_resume_in_bits { 4997 u8 opcode[0x10]; 4998 u8 reserved_at_10[0x10]; 4999 5000 u8 reserved_at_20[0x10]; 5001 u8 op_mod[0x10]; 5002 5003 u8 error[0x1]; 5004 u8 reserved_at_41[0x4]; 5005 u8 page_fault_type[0x3]; 5006 u8 wq_number[0x18]; 5007 5008 u8 reserved_at_60[0x8]; 5009 u8 token[0x18]; 5010 }; 5011 5012 struct mlx5_ifc_nop_out_bits { 5013 u8 status[0x8]; 5014 u8 reserved_at_8[0x18]; 5015 5016 u8 syndrome[0x20]; 5017 5018 u8 reserved_at_40[0x40]; 5019 }; 5020 5021 struct mlx5_ifc_nop_in_bits { 5022 u8 opcode[0x10]; 5023 u8 reserved_at_10[0x10]; 5024 5025 u8 reserved_at_20[0x10]; 5026 u8 op_mod[0x10]; 5027 5028 u8 reserved_at_40[0x40]; 5029 }; 5030 5031 struct mlx5_ifc_modify_vport_state_out_bits { 5032 u8 status[0x8]; 5033 u8 reserved_at_8[0x18]; 5034 5035 u8 syndrome[0x20]; 5036 5037 u8 reserved_at_40[0x40]; 5038 }; 5039 5040 struct mlx5_ifc_modify_vport_state_in_bits { 5041 u8 opcode[0x10]; 5042 u8 reserved_at_10[0x10]; 5043 5044 u8 reserved_at_20[0x10]; 5045 u8 op_mod[0x10]; 5046 5047 u8 other_vport[0x1]; 5048 u8 reserved_at_41[0xf]; 5049 u8 vport_number[0x10]; 5050 5051 u8 reserved_at_60[0x18]; 5052 u8 admin_state[0x4]; 5053 u8 reserved_at_7c[0x4]; 5054 }; 5055 5056 struct mlx5_ifc_modify_tis_out_bits { 5057 u8 status[0x8]; 5058 u8 reserved_at_8[0x18]; 5059 5060 u8 syndrome[0x20]; 5061 5062 u8 reserved_at_40[0x40]; 5063 }; 5064 5065 struct mlx5_ifc_modify_tis_bitmask_bits { 5066 u8 reserved_at_0[0x20]; 5067 5068 u8 reserved_at_20[0x1d]; 5069 u8 lag_tx_port_affinity[0x1]; 5070 u8 strict_lag_tx_port_affinity[0x1]; 5071 u8 prio[0x1]; 5072 }; 5073 5074 struct mlx5_ifc_modify_tis_in_bits { 5075 u8 opcode[0x10]; 5076 u8 reserved_at_10[0x10]; 5077 5078 u8 reserved_at_20[0x10]; 5079 u8 op_mod[0x10]; 5080 5081 u8 reserved_at_40[0x8]; 5082 u8 tisn[0x18]; 5083 5084 u8 reserved_at_60[0x20]; 5085 5086 struct mlx5_ifc_modify_tis_bitmask_bits bitmask; 5087 5088 u8 reserved_at_c0[0x40]; 5089 5090 struct mlx5_ifc_tisc_bits ctx; 5091 }; 5092 5093 struct mlx5_ifc_modify_tir_bitmask_bits { 5094 u8 reserved_at_0[0x20]; 5095 5096 u8 reserved_at_20[0x1b]; 5097 u8 self_lb_en[0x1]; 5098 u8 reserved_at_3c[0x1]; 5099 u8 hash[0x1]; 5100 u8 reserved_at_3e[0x1]; 5101 u8 lro[0x1]; 5102 }; 5103 5104 struct mlx5_ifc_modify_tir_out_bits { 5105 u8 status[0x8]; 5106 u8 reserved_at_8[0x18]; 5107 5108 u8 syndrome[0x20]; 5109 5110 u8 reserved_at_40[0x40]; 5111 }; 5112 5113 struct mlx5_ifc_modify_tir_in_bits { 5114 u8 opcode[0x10]; 5115 u8 reserved_at_10[0x10]; 5116 5117 u8 reserved_at_20[0x10]; 5118 u8 op_mod[0x10]; 5119 5120 u8 reserved_at_40[0x8]; 5121 u8 tirn[0x18]; 5122 5123 u8 reserved_at_60[0x20]; 5124 5125 struct mlx5_ifc_modify_tir_bitmask_bits bitmask; 5126 5127 u8 reserved_at_c0[0x40]; 5128 5129 struct mlx5_ifc_tirc_bits ctx; 5130 }; 5131 5132 struct mlx5_ifc_modify_sq_out_bits { 5133 u8 status[0x8]; 5134 u8 reserved_at_8[0x18]; 5135 5136 u8 syndrome[0x20]; 5137 5138 u8 reserved_at_40[0x40]; 5139 }; 5140 5141 struct mlx5_ifc_modify_sq_in_bits { 5142 u8 opcode[0x10]; 5143 u8 reserved_at_10[0x10]; 5144 5145 u8 reserved_at_20[0x10]; 5146 u8 op_mod[0x10]; 5147 5148 u8 sq_state[0x4]; 5149 u8 reserved_at_44[0x4]; 5150 u8 sqn[0x18]; 5151 5152 u8 reserved_at_60[0x20]; 5153 5154 u8 modify_bitmask[0x40]; 5155 5156 u8 reserved_at_c0[0x40]; 5157 5158 struct mlx5_ifc_sqc_bits ctx; 5159 }; 5160 5161 struct mlx5_ifc_modify_scheduling_element_out_bits { 5162 u8 status[0x8]; 5163 u8 reserved_at_8[0x18]; 5164 5165 u8 syndrome[0x20]; 5166 5167 u8 reserved_at_40[0x1c0]; 5168 }; 5169 5170 enum { 5171 MODIFY_SCHEDULING_ELEMENT_IN_MODIFY_BITMASK_BW_SHARE = 0x1, 5172 MODIFY_SCHEDULING_ELEMENT_IN_MODIFY_BITMASK_MAX_AVERAGE_BW = 0x2, 5173 }; 5174 5175 struct mlx5_ifc_modify_scheduling_element_in_bits { 5176 u8 opcode[0x10]; 5177 u8 reserved_at_10[0x10]; 5178 5179 u8 reserved_at_20[0x10]; 5180 u8 op_mod[0x10]; 5181 5182 u8 scheduling_hierarchy[0x8]; 5183 u8 reserved_at_48[0x18]; 5184 5185 u8 scheduling_element_id[0x20]; 5186 5187 u8 reserved_at_80[0x20]; 5188 5189 u8 modify_bitmask[0x20]; 5190 5191 u8 reserved_at_c0[0x40]; 5192 5193 struct mlx5_ifc_scheduling_context_bits scheduling_context; 5194 5195 u8 reserved_at_300[0x100]; 5196 }; 5197 5198 struct mlx5_ifc_modify_rqt_out_bits { 5199 u8 status[0x8]; 5200 u8 reserved_at_8[0x18]; 5201 5202 u8 syndrome[0x20]; 5203 5204 u8 reserved_at_40[0x40]; 5205 }; 5206 5207 struct mlx5_ifc_rqt_bitmask_bits { 5208 u8 reserved_at_0[0x20]; 5209 5210 u8 reserved_at_20[0x1f]; 5211 u8 rqn_list[0x1]; 5212 }; 5213 5214 struct mlx5_ifc_modify_rqt_in_bits { 5215 u8 opcode[0x10]; 5216 u8 reserved_at_10[0x10]; 5217 5218 u8 reserved_at_20[0x10]; 5219 u8 op_mod[0x10]; 5220 5221 u8 reserved_at_40[0x8]; 5222 u8 rqtn[0x18]; 5223 5224 u8 reserved_at_60[0x20]; 5225 5226 struct mlx5_ifc_rqt_bitmask_bits bitmask; 5227 5228 u8 reserved_at_c0[0x40]; 5229 5230 struct mlx5_ifc_rqtc_bits ctx; 5231 }; 5232 5233 struct mlx5_ifc_modify_rq_out_bits { 5234 u8 status[0x8]; 5235 u8 reserved_at_8[0x18]; 5236 5237 u8 syndrome[0x20]; 5238 5239 u8 reserved_at_40[0x40]; 5240 }; 5241 5242 enum { 5243 MLX5_MODIFY_RQ_IN_MODIFY_BITMASK_VSD = 1ULL << 1, 5244 MLX5_MODIFY_RQ_IN_MODIFY_BITMASK_SCATTER_FCS = 1ULL << 2, 5245 MLX5_MODIFY_RQ_IN_MODIFY_BITMASK_RQ_COUNTER_SET_ID = 1ULL << 3, 5246 }; 5247 5248 struct mlx5_ifc_modify_rq_in_bits { 5249 u8 opcode[0x10]; 5250 u8 reserved_at_10[0x10]; 5251 5252 u8 reserved_at_20[0x10]; 5253 u8 op_mod[0x10]; 5254 5255 u8 rq_state[0x4]; 5256 u8 reserved_at_44[0x4]; 5257 u8 rqn[0x18]; 5258 5259 u8 reserved_at_60[0x20]; 5260 5261 u8 modify_bitmask[0x40]; 5262 5263 u8 reserved_at_c0[0x40]; 5264 5265 struct mlx5_ifc_rqc_bits ctx; 5266 }; 5267 5268 struct mlx5_ifc_modify_rmp_out_bits { 5269 u8 status[0x8]; 5270 u8 reserved_at_8[0x18]; 5271 5272 u8 syndrome[0x20]; 5273 5274 u8 reserved_at_40[0x40]; 5275 }; 5276 5277 struct mlx5_ifc_rmp_bitmask_bits { 5278 u8 reserved_at_0[0x20]; 5279 5280 u8 reserved_at_20[0x1f]; 5281 u8 lwm[0x1]; 5282 }; 5283 5284 struct mlx5_ifc_modify_rmp_in_bits { 5285 u8 opcode[0x10]; 5286 u8 reserved_at_10[0x10]; 5287 5288 u8 reserved_at_20[0x10]; 5289 u8 op_mod[0x10]; 5290 5291 u8 rmp_state[0x4]; 5292 u8 reserved_at_44[0x4]; 5293 u8 rmpn[0x18]; 5294 5295 u8 reserved_at_60[0x20]; 5296 5297 struct mlx5_ifc_rmp_bitmask_bits bitmask; 5298 5299 u8 reserved_at_c0[0x40]; 5300 5301 struct mlx5_ifc_rmpc_bits ctx; 5302 }; 5303 5304 struct mlx5_ifc_modify_nic_vport_context_out_bits { 5305 u8 status[0x8]; 5306 u8 reserved_at_8[0x18]; 5307 5308 u8 syndrome[0x20]; 5309 5310 u8 reserved_at_40[0x40]; 5311 }; 5312 5313 struct mlx5_ifc_modify_nic_vport_field_select_bits { 5314 u8 reserved_at_0[0x14]; 5315 u8 disable_uc_local_lb[0x1]; 5316 u8 disable_mc_local_lb[0x1]; 5317 u8 node_guid[0x1]; 5318 u8 port_guid[0x1]; 5319 u8 min_inline[0x1]; 5320 u8 mtu[0x1]; 5321 u8 change_event[0x1]; 5322 u8 promisc[0x1]; 5323 u8 permanent_address[0x1]; 5324 u8 addresses_list[0x1]; 5325 u8 roce_en[0x1]; 5326 u8 reserved_at_1f[0x1]; 5327 }; 5328 5329 struct mlx5_ifc_modify_nic_vport_context_in_bits { 5330 u8 opcode[0x10]; 5331 u8 reserved_at_10[0x10]; 5332 5333 u8 reserved_at_20[0x10]; 5334 u8 op_mod[0x10]; 5335 5336 u8 other_vport[0x1]; 5337 u8 reserved_at_41[0xf]; 5338 u8 vport_number[0x10]; 5339 5340 struct mlx5_ifc_modify_nic_vport_field_select_bits field_select; 5341 5342 u8 reserved_at_80[0x780]; 5343 5344 struct mlx5_ifc_nic_vport_context_bits nic_vport_context; 5345 }; 5346 5347 struct mlx5_ifc_modify_hca_vport_context_out_bits { 5348 u8 status[0x8]; 5349 u8 reserved_at_8[0x18]; 5350 5351 u8 syndrome[0x20]; 5352 5353 u8 reserved_at_40[0x40]; 5354 }; 5355 5356 struct mlx5_ifc_modify_hca_vport_context_in_bits { 5357 u8 opcode[0x10]; 5358 u8 reserved_at_10[0x10]; 5359 5360 u8 reserved_at_20[0x10]; 5361 u8 op_mod[0x10]; 5362 5363 u8 other_vport[0x1]; 5364 u8 reserved_at_41[0xb]; 5365 u8 port_num[0x4]; 5366 u8 vport_number[0x10]; 5367 5368 u8 reserved_at_60[0x20]; 5369 5370 struct mlx5_ifc_hca_vport_context_bits hca_vport_context; 5371 }; 5372 5373 struct mlx5_ifc_modify_cq_out_bits { 5374 u8 status[0x8]; 5375 u8 reserved_at_8[0x18]; 5376 5377 u8 syndrome[0x20]; 5378 5379 u8 reserved_at_40[0x40]; 5380 }; 5381 5382 enum { 5383 MLX5_MODIFY_CQ_IN_OP_MOD_MODIFY_CQ = 0x0, 5384 MLX5_MODIFY_CQ_IN_OP_MOD_RESIZE_CQ = 0x1, 5385 }; 5386 5387 struct mlx5_ifc_modify_cq_in_bits { 5388 u8 opcode[0x10]; 5389 u8 reserved_at_10[0x10]; 5390 5391 u8 reserved_at_20[0x10]; 5392 u8 op_mod[0x10]; 5393 5394 u8 reserved_at_40[0x8]; 5395 u8 cqn[0x18]; 5396 5397 union mlx5_ifc_modify_field_select_resize_field_select_auto_bits modify_field_select_resize_field_select; 5398 5399 struct mlx5_ifc_cqc_bits cq_context; 5400 5401 u8 reserved_at_280[0x600]; 5402 5403 u8 pas[0][0x40]; 5404 }; 5405 5406 struct mlx5_ifc_modify_cong_status_out_bits { 5407 u8 status[0x8]; 5408 u8 reserved_at_8[0x18]; 5409 5410 u8 syndrome[0x20]; 5411 5412 u8 reserved_at_40[0x40]; 5413 }; 5414 5415 struct mlx5_ifc_modify_cong_status_in_bits { 5416 u8 opcode[0x10]; 5417 u8 reserved_at_10[0x10]; 5418 5419 u8 reserved_at_20[0x10]; 5420 u8 op_mod[0x10]; 5421 5422 u8 reserved_at_40[0x18]; 5423 u8 priority[0x4]; 5424 u8 cong_protocol[0x4]; 5425 5426 u8 enable[0x1]; 5427 u8 tag_enable[0x1]; 5428 u8 reserved_at_62[0x1e]; 5429 }; 5430 5431 struct mlx5_ifc_modify_cong_params_out_bits { 5432 u8 status[0x8]; 5433 u8 reserved_at_8[0x18]; 5434 5435 u8 syndrome[0x20]; 5436 5437 u8 reserved_at_40[0x40]; 5438 }; 5439 5440 struct mlx5_ifc_modify_cong_params_in_bits { 5441 u8 opcode[0x10]; 5442 u8 reserved_at_10[0x10]; 5443 5444 u8 reserved_at_20[0x10]; 5445 u8 op_mod[0x10]; 5446 5447 u8 reserved_at_40[0x1c]; 5448 u8 cong_protocol[0x4]; 5449 5450 union mlx5_ifc_field_select_802_1_r_roce_auto_bits field_select; 5451 5452 u8 reserved_at_80[0x80]; 5453 5454 union mlx5_ifc_cong_control_roce_ecn_auto_bits congestion_parameters; 5455 }; 5456 5457 struct mlx5_ifc_manage_pages_out_bits { 5458 u8 status[0x8]; 5459 u8 reserved_at_8[0x18]; 5460 5461 u8 syndrome[0x20]; 5462 5463 u8 output_num_entries[0x20]; 5464 5465 u8 reserved_at_60[0x20]; 5466 5467 u8 pas[0][0x40]; 5468 }; 5469 5470 enum { 5471 MLX5_MANAGE_PAGES_IN_OP_MOD_ALLOCATION_FAIL = 0x0, 5472 MLX5_MANAGE_PAGES_IN_OP_MOD_ALLOCATION_SUCCESS = 0x1, 5473 MLX5_MANAGE_PAGES_IN_OP_MOD_HCA_RETURN_PAGES = 0x2, 5474 }; 5475 5476 struct mlx5_ifc_manage_pages_in_bits { 5477 u8 opcode[0x10]; 5478 u8 reserved_at_10[0x10]; 5479 5480 u8 reserved_at_20[0x10]; 5481 u8 op_mod[0x10]; 5482 5483 u8 reserved_at_40[0x10]; 5484 u8 function_id[0x10]; 5485 5486 u8 input_num_entries[0x20]; 5487 5488 u8 pas[0][0x40]; 5489 }; 5490 5491 struct mlx5_ifc_mad_ifc_out_bits { 5492 u8 status[0x8]; 5493 u8 reserved_at_8[0x18]; 5494 5495 u8 syndrome[0x20]; 5496 5497 u8 reserved_at_40[0x40]; 5498 5499 u8 response_mad_packet[256][0x8]; 5500 }; 5501 5502 struct mlx5_ifc_mad_ifc_in_bits { 5503 u8 opcode[0x10]; 5504 u8 reserved_at_10[0x10]; 5505 5506 u8 reserved_at_20[0x10]; 5507 u8 op_mod[0x10]; 5508 5509 u8 remote_lid[0x10]; 5510 u8 reserved_at_50[0x8]; 5511 u8 port[0x8]; 5512 5513 u8 reserved_at_60[0x20]; 5514 5515 u8 mad[256][0x8]; 5516 }; 5517 5518 struct mlx5_ifc_init_hca_out_bits { 5519 u8 status[0x8]; 5520 u8 reserved_at_8[0x18]; 5521 5522 u8 syndrome[0x20]; 5523 5524 u8 reserved_at_40[0x40]; 5525 }; 5526 5527 struct mlx5_ifc_init_hca_in_bits { 5528 u8 opcode[0x10]; 5529 u8 reserved_at_10[0x10]; 5530 5531 u8 reserved_at_20[0x10]; 5532 u8 op_mod[0x10]; 5533 5534 u8 reserved_at_40[0x40]; 5535 }; 5536 5537 struct mlx5_ifc_init2rtr_qp_out_bits { 5538 u8 status[0x8]; 5539 u8 reserved_at_8[0x18]; 5540 5541 u8 syndrome[0x20]; 5542 5543 u8 reserved_at_40[0x40]; 5544 }; 5545 5546 struct mlx5_ifc_init2rtr_qp_in_bits { 5547 u8 opcode[0x10]; 5548 u8 reserved_at_10[0x10]; 5549 5550 u8 reserved_at_20[0x10]; 5551 u8 op_mod[0x10]; 5552 5553 u8 reserved_at_40[0x8]; 5554 u8 qpn[0x18]; 5555 5556 u8 reserved_at_60[0x20]; 5557 5558 u8 opt_param_mask[0x20]; 5559 5560 u8 reserved_at_a0[0x20]; 5561 5562 struct mlx5_ifc_qpc_bits qpc; 5563 5564 u8 reserved_at_800[0x80]; 5565 }; 5566 5567 struct mlx5_ifc_init2init_qp_out_bits { 5568 u8 status[0x8]; 5569 u8 reserved_at_8[0x18]; 5570 5571 u8 syndrome[0x20]; 5572 5573 u8 reserved_at_40[0x40]; 5574 }; 5575 5576 struct mlx5_ifc_init2init_qp_in_bits { 5577 u8 opcode[0x10]; 5578 u8 reserved_at_10[0x10]; 5579 5580 u8 reserved_at_20[0x10]; 5581 u8 op_mod[0x10]; 5582 5583 u8 reserved_at_40[0x8]; 5584 u8 qpn[0x18]; 5585 5586 u8 reserved_at_60[0x20]; 5587 5588 u8 opt_param_mask[0x20]; 5589 5590 u8 reserved_at_a0[0x20]; 5591 5592 struct mlx5_ifc_qpc_bits qpc; 5593 5594 u8 reserved_at_800[0x80]; 5595 }; 5596 5597 struct mlx5_ifc_get_dropped_packet_log_out_bits { 5598 u8 status[0x8]; 5599 u8 reserved_at_8[0x18]; 5600 5601 u8 syndrome[0x20]; 5602 5603 u8 reserved_at_40[0x40]; 5604 5605 u8 packet_headers_log[128][0x8]; 5606 5607 u8 packet_syndrome[64][0x8]; 5608 }; 5609 5610 struct mlx5_ifc_get_dropped_packet_log_in_bits { 5611 u8 opcode[0x10]; 5612 u8 reserved_at_10[0x10]; 5613 5614 u8 reserved_at_20[0x10]; 5615 u8 op_mod[0x10]; 5616 5617 u8 reserved_at_40[0x40]; 5618 }; 5619 5620 struct mlx5_ifc_gen_eqe_in_bits { 5621 u8 opcode[0x10]; 5622 u8 reserved_at_10[0x10]; 5623 5624 u8 reserved_at_20[0x10]; 5625 u8 op_mod[0x10]; 5626 5627 u8 reserved_at_40[0x18]; 5628 u8 eq_number[0x8]; 5629 5630 u8 reserved_at_60[0x20]; 5631 5632 u8 eqe[64][0x8]; 5633 }; 5634 5635 struct mlx5_ifc_gen_eq_out_bits { 5636 u8 status[0x8]; 5637 u8 reserved_at_8[0x18]; 5638 5639 u8 syndrome[0x20]; 5640 5641 u8 reserved_at_40[0x40]; 5642 }; 5643 5644 struct mlx5_ifc_enable_hca_out_bits { 5645 u8 status[0x8]; 5646 u8 reserved_at_8[0x18]; 5647 5648 u8 syndrome[0x20]; 5649 5650 u8 reserved_at_40[0x20]; 5651 }; 5652 5653 struct mlx5_ifc_enable_hca_in_bits { 5654 u8 opcode[0x10]; 5655 u8 reserved_at_10[0x10]; 5656 5657 u8 reserved_at_20[0x10]; 5658 u8 op_mod[0x10]; 5659 5660 u8 reserved_at_40[0x10]; 5661 u8 function_id[0x10]; 5662 5663 u8 reserved_at_60[0x20]; 5664 }; 5665 5666 struct mlx5_ifc_drain_dct_out_bits { 5667 u8 status[0x8]; 5668 u8 reserved_at_8[0x18]; 5669 5670 u8 syndrome[0x20]; 5671 5672 u8 reserved_at_40[0x40]; 5673 }; 5674 5675 struct mlx5_ifc_drain_dct_in_bits { 5676 u8 opcode[0x10]; 5677 u8 reserved_at_10[0x10]; 5678 5679 u8 reserved_at_20[0x10]; 5680 u8 op_mod[0x10]; 5681 5682 u8 reserved_at_40[0x8]; 5683 u8 dctn[0x18]; 5684 5685 u8 reserved_at_60[0x20]; 5686 }; 5687 5688 struct mlx5_ifc_disable_hca_out_bits { 5689 u8 status[0x8]; 5690 u8 reserved_at_8[0x18]; 5691 5692 u8 syndrome[0x20]; 5693 5694 u8 reserved_at_40[0x20]; 5695 }; 5696 5697 struct mlx5_ifc_disable_hca_in_bits { 5698 u8 opcode[0x10]; 5699 u8 reserved_at_10[0x10]; 5700 5701 u8 reserved_at_20[0x10]; 5702 u8 op_mod[0x10]; 5703 5704 u8 reserved_at_40[0x10]; 5705 u8 function_id[0x10]; 5706 5707 u8 reserved_at_60[0x20]; 5708 }; 5709 5710 struct mlx5_ifc_detach_from_mcg_out_bits { 5711 u8 status[0x8]; 5712 u8 reserved_at_8[0x18]; 5713 5714 u8 syndrome[0x20]; 5715 5716 u8 reserved_at_40[0x40]; 5717 }; 5718 5719 struct mlx5_ifc_detach_from_mcg_in_bits { 5720 u8 opcode[0x10]; 5721 u8 reserved_at_10[0x10]; 5722 5723 u8 reserved_at_20[0x10]; 5724 u8 op_mod[0x10]; 5725 5726 u8 reserved_at_40[0x8]; 5727 u8 qpn[0x18]; 5728 5729 u8 reserved_at_60[0x20]; 5730 5731 u8 multicast_gid[16][0x8]; 5732 }; 5733 5734 struct mlx5_ifc_destroy_xrq_out_bits { 5735 u8 status[0x8]; 5736 u8 reserved_at_8[0x18]; 5737 5738 u8 syndrome[0x20]; 5739 5740 u8 reserved_at_40[0x40]; 5741 }; 5742 5743 struct mlx5_ifc_destroy_xrq_in_bits { 5744 u8 opcode[0x10]; 5745 u8 reserved_at_10[0x10]; 5746 5747 u8 reserved_at_20[0x10]; 5748 u8 op_mod[0x10]; 5749 5750 u8 reserved_at_40[0x8]; 5751 u8 xrqn[0x18]; 5752 5753 u8 reserved_at_60[0x20]; 5754 }; 5755 5756 struct mlx5_ifc_destroy_xrc_srq_out_bits { 5757 u8 status[0x8]; 5758 u8 reserved_at_8[0x18]; 5759 5760 u8 syndrome[0x20]; 5761 5762 u8 reserved_at_40[0x40]; 5763 }; 5764 5765 struct mlx5_ifc_destroy_xrc_srq_in_bits { 5766 u8 opcode[0x10]; 5767 u8 reserved_at_10[0x10]; 5768 5769 u8 reserved_at_20[0x10]; 5770 u8 op_mod[0x10]; 5771 5772 u8 reserved_at_40[0x8]; 5773 u8 xrc_srqn[0x18]; 5774 5775 u8 reserved_at_60[0x20]; 5776 }; 5777 5778 struct mlx5_ifc_destroy_tis_out_bits { 5779 u8 status[0x8]; 5780 u8 reserved_at_8[0x18]; 5781 5782 u8 syndrome[0x20]; 5783 5784 u8 reserved_at_40[0x40]; 5785 }; 5786 5787 struct mlx5_ifc_destroy_tis_in_bits { 5788 u8 opcode[0x10]; 5789 u8 reserved_at_10[0x10]; 5790 5791 u8 reserved_at_20[0x10]; 5792 u8 op_mod[0x10]; 5793 5794 u8 reserved_at_40[0x8]; 5795 u8 tisn[0x18]; 5796 5797 u8 reserved_at_60[0x20]; 5798 }; 5799 5800 struct mlx5_ifc_destroy_tir_out_bits { 5801 u8 status[0x8]; 5802 u8 reserved_at_8[0x18]; 5803 5804 u8 syndrome[0x20]; 5805 5806 u8 reserved_at_40[0x40]; 5807 }; 5808 5809 struct mlx5_ifc_destroy_tir_in_bits { 5810 u8 opcode[0x10]; 5811 u8 reserved_at_10[0x10]; 5812 5813 u8 reserved_at_20[0x10]; 5814 u8 op_mod[0x10]; 5815 5816 u8 reserved_at_40[0x8]; 5817 u8 tirn[0x18]; 5818 5819 u8 reserved_at_60[0x20]; 5820 }; 5821 5822 struct mlx5_ifc_destroy_srq_out_bits { 5823 u8 status[0x8]; 5824 u8 reserved_at_8[0x18]; 5825 5826 u8 syndrome[0x20]; 5827 5828 u8 reserved_at_40[0x40]; 5829 }; 5830 5831 struct mlx5_ifc_destroy_srq_in_bits { 5832 u8 opcode[0x10]; 5833 u8 reserved_at_10[0x10]; 5834 5835 u8 reserved_at_20[0x10]; 5836 u8 op_mod[0x10]; 5837 5838 u8 reserved_at_40[0x8]; 5839 u8 srqn[0x18]; 5840 5841 u8 reserved_at_60[0x20]; 5842 }; 5843 5844 struct mlx5_ifc_destroy_sq_out_bits { 5845 u8 status[0x8]; 5846 u8 reserved_at_8[0x18]; 5847 5848 u8 syndrome[0x20]; 5849 5850 u8 reserved_at_40[0x40]; 5851 }; 5852 5853 struct mlx5_ifc_destroy_sq_in_bits { 5854 u8 opcode[0x10]; 5855 u8 reserved_at_10[0x10]; 5856 5857 u8 reserved_at_20[0x10]; 5858 u8 op_mod[0x10]; 5859 5860 u8 reserved_at_40[0x8]; 5861 u8 sqn[0x18]; 5862 5863 u8 reserved_at_60[0x20]; 5864 }; 5865 5866 struct mlx5_ifc_destroy_scheduling_element_out_bits { 5867 u8 status[0x8]; 5868 u8 reserved_at_8[0x18]; 5869 5870 u8 syndrome[0x20]; 5871 5872 u8 reserved_at_40[0x1c0]; 5873 }; 5874 5875 struct mlx5_ifc_destroy_scheduling_element_in_bits { 5876 u8 opcode[0x10]; 5877 u8 reserved_at_10[0x10]; 5878 5879 u8 reserved_at_20[0x10]; 5880 u8 op_mod[0x10]; 5881 5882 u8 scheduling_hierarchy[0x8]; 5883 u8 reserved_at_48[0x18]; 5884 5885 u8 scheduling_element_id[0x20]; 5886 5887 u8 reserved_at_80[0x180]; 5888 }; 5889 5890 struct mlx5_ifc_destroy_rqt_out_bits { 5891 u8 status[0x8]; 5892 u8 reserved_at_8[0x18]; 5893 5894 u8 syndrome[0x20]; 5895 5896 u8 reserved_at_40[0x40]; 5897 }; 5898 5899 struct mlx5_ifc_destroy_rqt_in_bits { 5900 u8 opcode[0x10]; 5901 u8 reserved_at_10[0x10]; 5902 5903 u8 reserved_at_20[0x10]; 5904 u8 op_mod[0x10]; 5905 5906 u8 reserved_at_40[0x8]; 5907 u8 rqtn[0x18]; 5908 5909 u8 reserved_at_60[0x20]; 5910 }; 5911 5912 struct mlx5_ifc_destroy_rq_out_bits { 5913 u8 status[0x8]; 5914 u8 reserved_at_8[0x18]; 5915 5916 u8 syndrome[0x20]; 5917 5918 u8 reserved_at_40[0x40]; 5919 }; 5920 5921 struct mlx5_ifc_destroy_rq_in_bits { 5922 u8 opcode[0x10]; 5923 u8 reserved_at_10[0x10]; 5924 5925 u8 reserved_at_20[0x10]; 5926 u8 op_mod[0x10]; 5927 5928 u8 reserved_at_40[0x8]; 5929 u8 rqn[0x18]; 5930 5931 u8 reserved_at_60[0x20]; 5932 }; 5933 5934 struct mlx5_ifc_set_delay_drop_params_in_bits { 5935 u8 opcode[0x10]; 5936 u8 reserved_at_10[0x10]; 5937 5938 u8 reserved_at_20[0x10]; 5939 u8 op_mod[0x10]; 5940 5941 u8 reserved_at_40[0x20]; 5942 5943 u8 reserved_at_60[0x10]; 5944 u8 delay_drop_timeout[0x10]; 5945 }; 5946 5947 struct mlx5_ifc_set_delay_drop_params_out_bits { 5948 u8 status[0x8]; 5949 u8 reserved_at_8[0x18]; 5950 5951 u8 syndrome[0x20]; 5952 5953 u8 reserved_at_40[0x40]; 5954 }; 5955 5956 struct mlx5_ifc_destroy_rmp_out_bits { 5957 u8 status[0x8]; 5958 u8 reserved_at_8[0x18]; 5959 5960 u8 syndrome[0x20]; 5961 5962 u8 reserved_at_40[0x40]; 5963 }; 5964 5965 struct mlx5_ifc_destroy_rmp_in_bits { 5966 u8 opcode[0x10]; 5967 u8 reserved_at_10[0x10]; 5968 5969 u8 reserved_at_20[0x10]; 5970 u8 op_mod[0x10]; 5971 5972 u8 reserved_at_40[0x8]; 5973 u8 rmpn[0x18]; 5974 5975 u8 reserved_at_60[0x20]; 5976 }; 5977 5978 struct mlx5_ifc_destroy_qp_out_bits { 5979 u8 status[0x8]; 5980 u8 reserved_at_8[0x18]; 5981 5982 u8 syndrome[0x20]; 5983 5984 u8 reserved_at_40[0x40]; 5985 }; 5986 5987 struct mlx5_ifc_destroy_qp_in_bits { 5988 u8 opcode[0x10]; 5989 u8 reserved_at_10[0x10]; 5990 5991 u8 reserved_at_20[0x10]; 5992 u8 op_mod[0x10]; 5993 5994 u8 reserved_at_40[0x8]; 5995 u8 qpn[0x18]; 5996 5997 u8 reserved_at_60[0x20]; 5998 }; 5999 6000 struct mlx5_ifc_destroy_psv_out_bits { 6001 u8 status[0x8]; 6002 u8 reserved_at_8[0x18]; 6003 6004 u8 syndrome[0x20]; 6005 6006 u8 reserved_at_40[0x40]; 6007 }; 6008 6009 struct mlx5_ifc_destroy_psv_in_bits { 6010 u8 opcode[0x10]; 6011 u8 reserved_at_10[0x10]; 6012 6013 u8 reserved_at_20[0x10]; 6014 u8 op_mod[0x10]; 6015 6016 u8 reserved_at_40[0x8]; 6017 u8 psvn[0x18]; 6018 6019 u8 reserved_at_60[0x20]; 6020 }; 6021 6022 struct mlx5_ifc_destroy_mkey_out_bits { 6023 u8 status[0x8]; 6024 u8 reserved_at_8[0x18]; 6025 6026 u8 syndrome[0x20]; 6027 6028 u8 reserved_at_40[0x40]; 6029 }; 6030 6031 struct mlx5_ifc_destroy_mkey_in_bits { 6032 u8 opcode[0x10]; 6033 u8 reserved_at_10[0x10]; 6034 6035 u8 reserved_at_20[0x10]; 6036 u8 op_mod[0x10]; 6037 6038 u8 reserved_at_40[0x8]; 6039 u8 mkey_index[0x18]; 6040 6041 u8 reserved_at_60[0x20]; 6042 }; 6043 6044 struct mlx5_ifc_destroy_flow_table_out_bits { 6045 u8 status[0x8]; 6046 u8 reserved_at_8[0x18]; 6047 6048 u8 syndrome[0x20]; 6049 6050 u8 reserved_at_40[0x40]; 6051 }; 6052 6053 struct mlx5_ifc_destroy_flow_table_in_bits { 6054 u8 opcode[0x10]; 6055 u8 reserved_at_10[0x10]; 6056 6057 u8 reserved_at_20[0x10]; 6058 u8 op_mod[0x10]; 6059 6060 u8 other_vport[0x1]; 6061 u8 reserved_at_41[0xf]; 6062 u8 vport_number[0x10]; 6063 6064 u8 reserved_at_60[0x20]; 6065 6066 u8 table_type[0x8]; 6067 u8 reserved_at_88[0x18]; 6068 6069 u8 reserved_at_a0[0x8]; 6070 u8 table_id[0x18]; 6071 6072 u8 reserved_at_c0[0x140]; 6073 }; 6074 6075 struct mlx5_ifc_destroy_flow_group_out_bits { 6076 u8 status[0x8]; 6077 u8 reserved_at_8[0x18]; 6078 6079 u8 syndrome[0x20]; 6080 6081 u8 reserved_at_40[0x40]; 6082 }; 6083 6084 struct mlx5_ifc_destroy_flow_group_in_bits { 6085 u8 opcode[0x10]; 6086 u8 reserved_at_10[0x10]; 6087 6088 u8 reserved_at_20[0x10]; 6089 u8 op_mod[0x10]; 6090 6091 u8 other_vport[0x1]; 6092 u8 reserved_at_41[0xf]; 6093 u8 vport_number[0x10]; 6094 6095 u8 reserved_at_60[0x20]; 6096 6097 u8 table_type[0x8]; 6098 u8 reserved_at_88[0x18]; 6099 6100 u8 reserved_at_a0[0x8]; 6101 u8 table_id[0x18]; 6102 6103 u8 group_id[0x20]; 6104 6105 u8 reserved_at_e0[0x120]; 6106 }; 6107 6108 struct mlx5_ifc_destroy_eq_out_bits { 6109 u8 status[0x8]; 6110 u8 reserved_at_8[0x18]; 6111 6112 u8 syndrome[0x20]; 6113 6114 u8 reserved_at_40[0x40]; 6115 }; 6116 6117 struct mlx5_ifc_destroy_eq_in_bits { 6118 u8 opcode[0x10]; 6119 u8 reserved_at_10[0x10]; 6120 6121 u8 reserved_at_20[0x10]; 6122 u8 op_mod[0x10]; 6123 6124 u8 reserved_at_40[0x18]; 6125 u8 eq_number[0x8]; 6126 6127 u8 reserved_at_60[0x20]; 6128 }; 6129 6130 struct mlx5_ifc_destroy_dct_out_bits { 6131 u8 status[0x8]; 6132 u8 reserved_at_8[0x18]; 6133 6134 u8 syndrome[0x20]; 6135 6136 u8 reserved_at_40[0x40]; 6137 }; 6138 6139 struct mlx5_ifc_destroy_dct_in_bits { 6140 u8 opcode[0x10]; 6141 u8 reserved_at_10[0x10]; 6142 6143 u8 reserved_at_20[0x10]; 6144 u8 op_mod[0x10]; 6145 6146 u8 reserved_at_40[0x8]; 6147 u8 dctn[0x18]; 6148 6149 u8 reserved_at_60[0x20]; 6150 }; 6151 6152 struct mlx5_ifc_destroy_cq_out_bits { 6153 u8 status[0x8]; 6154 u8 reserved_at_8[0x18]; 6155 6156 u8 syndrome[0x20]; 6157 6158 u8 reserved_at_40[0x40]; 6159 }; 6160 6161 struct mlx5_ifc_destroy_cq_in_bits { 6162 u8 opcode[0x10]; 6163 u8 reserved_at_10[0x10]; 6164 6165 u8 reserved_at_20[0x10]; 6166 u8 op_mod[0x10]; 6167 6168 u8 reserved_at_40[0x8]; 6169 u8 cqn[0x18]; 6170 6171 u8 reserved_at_60[0x20]; 6172 }; 6173 6174 struct mlx5_ifc_delete_vxlan_udp_dport_out_bits { 6175 u8 status[0x8]; 6176 u8 reserved_at_8[0x18]; 6177 6178 u8 syndrome[0x20]; 6179 6180 u8 reserved_at_40[0x40]; 6181 }; 6182 6183 struct mlx5_ifc_delete_vxlan_udp_dport_in_bits { 6184 u8 opcode[0x10]; 6185 u8 reserved_at_10[0x10]; 6186 6187 u8 reserved_at_20[0x10]; 6188 u8 op_mod[0x10]; 6189 6190 u8 reserved_at_40[0x20]; 6191 6192 u8 reserved_at_60[0x10]; 6193 u8 vxlan_udp_port[0x10]; 6194 }; 6195 6196 struct mlx5_ifc_delete_l2_table_entry_out_bits { 6197 u8 status[0x8]; 6198 u8 reserved_at_8[0x18]; 6199 6200 u8 syndrome[0x20]; 6201 6202 u8 reserved_at_40[0x40]; 6203 }; 6204 6205 struct mlx5_ifc_delete_l2_table_entry_in_bits { 6206 u8 opcode[0x10]; 6207 u8 reserved_at_10[0x10]; 6208 6209 u8 reserved_at_20[0x10]; 6210 u8 op_mod[0x10]; 6211 6212 u8 reserved_at_40[0x60]; 6213 6214 u8 reserved_at_a0[0x8]; 6215 u8 table_index[0x18]; 6216 6217 u8 reserved_at_c0[0x140]; 6218 }; 6219 6220 struct mlx5_ifc_delete_fte_out_bits { 6221 u8 status[0x8]; 6222 u8 reserved_at_8[0x18]; 6223 6224 u8 syndrome[0x20]; 6225 6226 u8 reserved_at_40[0x40]; 6227 }; 6228 6229 struct mlx5_ifc_delete_fte_in_bits { 6230 u8 opcode[0x10]; 6231 u8 reserved_at_10[0x10]; 6232 6233 u8 reserved_at_20[0x10]; 6234 u8 op_mod[0x10]; 6235 6236 u8 other_vport[0x1]; 6237 u8 reserved_at_41[0xf]; 6238 u8 vport_number[0x10]; 6239 6240 u8 reserved_at_60[0x20]; 6241 6242 u8 table_type[0x8]; 6243 u8 reserved_at_88[0x18]; 6244 6245 u8 reserved_at_a0[0x8]; 6246 u8 table_id[0x18]; 6247 6248 u8 reserved_at_c0[0x40]; 6249 6250 u8 flow_index[0x20]; 6251 6252 u8 reserved_at_120[0xe0]; 6253 }; 6254 6255 struct mlx5_ifc_dealloc_xrcd_out_bits { 6256 u8 status[0x8]; 6257 u8 reserved_at_8[0x18]; 6258 6259 u8 syndrome[0x20]; 6260 6261 u8 reserved_at_40[0x40]; 6262 }; 6263 6264 struct mlx5_ifc_dealloc_xrcd_in_bits { 6265 u8 opcode[0x10]; 6266 u8 reserved_at_10[0x10]; 6267 6268 u8 reserved_at_20[0x10]; 6269 u8 op_mod[0x10]; 6270 6271 u8 reserved_at_40[0x8]; 6272 u8 xrcd[0x18]; 6273 6274 u8 reserved_at_60[0x20]; 6275 }; 6276 6277 struct mlx5_ifc_dealloc_uar_out_bits { 6278 u8 status[0x8]; 6279 u8 reserved_at_8[0x18]; 6280 6281 u8 syndrome[0x20]; 6282 6283 u8 reserved_at_40[0x40]; 6284 }; 6285 6286 struct mlx5_ifc_dealloc_uar_in_bits { 6287 u8 opcode[0x10]; 6288 u8 reserved_at_10[0x10]; 6289 6290 u8 reserved_at_20[0x10]; 6291 u8 op_mod[0x10]; 6292 6293 u8 reserved_at_40[0x8]; 6294 u8 uar[0x18]; 6295 6296 u8 reserved_at_60[0x20]; 6297 }; 6298 6299 struct mlx5_ifc_dealloc_transport_domain_out_bits { 6300 u8 status[0x8]; 6301 u8 reserved_at_8[0x18]; 6302 6303 u8 syndrome[0x20]; 6304 6305 u8 reserved_at_40[0x40]; 6306 }; 6307 6308 struct mlx5_ifc_dealloc_transport_domain_in_bits { 6309 u8 opcode[0x10]; 6310 u8 reserved_at_10[0x10]; 6311 6312 u8 reserved_at_20[0x10]; 6313 u8 op_mod[0x10]; 6314 6315 u8 reserved_at_40[0x8]; 6316 u8 transport_domain[0x18]; 6317 6318 u8 reserved_at_60[0x20]; 6319 }; 6320 6321 struct mlx5_ifc_dealloc_q_counter_out_bits { 6322 u8 status[0x8]; 6323 u8 reserved_at_8[0x18]; 6324 6325 u8 syndrome[0x20]; 6326 6327 u8 reserved_at_40[0x40]; 6328 }; 6329 6330 struct mlx5_ifc_dealloc_q_counter_in_bits { 6331 u8 opcode[0x10]; 6332 u8 reserved_at_10[0x10]; 6333 6334 u8 reserved_at_20[0x10]; 6335 u8 op_mod[0x10]; 6336 6337 u8 reserved_at_40[0x18]; 6338 u8 counter_set_id[0x8]; 6339 6340 u8 reserved_at_60[0x20]; 6341 }; 6342 6343 struct mlx5_ifc_dealloc_pd_out_bits { 6344 u8 status[0x8]; 6345 u8 reserved_at_8[0x18]; 6346 6347 u8 syndrome[0x20]; 6348 6349 u8 reserved_at_40[0x40]; 6350 }; 6351 6352 struct mlx5_ifc_dealloc_pd_in_bits { 6353 u8 opcode[0x10]; 6354 u8 reserved_at_10[0x10]; 6355 6356 u8 reserved_at_20[0x10]; 6357 u8 op_mod[0x10]; 6358 6359 u8 reserved_at_40[0x8]; 6360 u8 pd[0x18]; 6361 6362 u8 reserved_at_60[0x20]; 6363 }; 6364 6365 struct mlx5_ifc_dealloc_flow_counter_out_bits { 6366 u8 status[0x8]; 6367 u8 reserved_at_8[0x18]; 6368 6369 u8 syndrome[0x20]; 6370 6371 u8 reserved_at_40[0x40]; 6372 }; 6373 6374 struct mlx5_ifc_dealloc_flow_counter_in_bits { 6375 u8 opcode[0x10]; 6376 u8 reserved_at_10[0x10]; 6377 6378 u8 reserved_at_20[0x10]; 6379 u8 op_mod[0x10]; 6380 6381 u8 flow_counter_id[0x20]; 6382 6383 u8 reserved_at_60[0x20]; 6384 }; 6385 6386 struct mlx5_ifc_create_xrq_out_bits { 6387 u8 status[0x8]; 6388 u8 reserved_at_8[0x18]; 6389 6390 u8 syndrome[0x20]; 6391 6392 u8 reserved_at_40[0x8]; 6393 u8 xrqn[0x18]; 6394 6395 u8 reserved_at_60[0x20]; 6396 }; 6397 6398 struct mlx5_ifc_create_xrq_in_bits { 6399 u8 opcode[0x10]; 6400 u8 reserved_at_10[0x10]; 6401 6402 u8 reserved_at_20[0x10]; 6403 u8 op_mod[0x10]; 6404 6405 u8 reserved_at_40[0x40]; 6406 6407 struct mlx5_ifc_xrqc_bits xrq_context; 6408 }; 6409 6410 struct mlx5_ifc_create_xrc_srq_out_bits { 6411 u8 status[0x8]; 6412 u8 reserved_at_8[0x18]; 6413 6414 u8 syndrome[0x20]; 6415 6416 u8 reserved_at_40[0x8]; 6417 u8 xrc_srqn[0x18]; 6418 6419 u8 reserved_at_60[0x20]; 6420 }; 6421 6422 struct mlx5_ifc_create_xrc_srq_in_bits { 6423 u8 opcode[0x10]; 6424 u8 reserved_at_10[0x10]; 6425 6426 u8 reserved_at_20[0x10]; 6427 u8 op_mod[0x10]; 6428 6429 u8 reserved_at_40[0x40]; 6430 6431 struct mlx5_ifc_xrc_srqc_bits xrc_srq_context_entry; 6432 6433 u8 reserved_at_280[0x600]; 6434 6435 u8 pas[0][0x40]; 6436 }; 6437 6438 struct mlx5_ifc_create_tis_out_bits { 6439 u8 status[0x8]; 6440 u8 reserved_at_8[0x18]; 6441 6442 u8 syndrome[0x20]; 6443 6444 u8 reserved_at_40[0x8]; 6445 u8 tisn[0x18]; 6446 6447 u8 reserved_at_60[0x20]; 6448 }; 6449 6450 struct mlx5_ifc_create_tis_in_bits { 6451 u8 opcode[0x10]; 6452 u8 reserved_at_10[0x10]; 6453 6454 u8 reserved_at_20[0x10]; 6455 u8 op_mod[0x10]; 6456 6457 u8 reserved_at_40[0xc0]; 6458 6459 struct mlx5_ifc_tisc_bits ctx; 6460 }; 6461 6462 struct mlx5_ifc_create_tir_out_bits { 6463 u8 status[0x8]; 6464 u8 reserved_at_8[0x18]; 6465 6466 u8 syndrome[0x20]; 6467 6468 u8 reserved_at_40[0x8]; 6469 u8 tirn[0x18]; 6470 6471 u8 reserved_at_60[0x20]; 6472 }; 6473 6474 struct mlx5_ifc_create_tir_in_bits { 6475 u8 opcode[0x10]; 6476 u8 reserved_at_10[0x10]; 6477 6478 u8 reserved_at_20[0x10]; 6479 u8 op_mod[0x10]; 6480 6481 u8 reserved_at_40[0xc0]; 6482 6483 struct mlx5_ifc_tirc_bits ctx; 6484 }; 6485 6486 struct mlx5_ifc_create_srq_out_bits { 6487 u8 status[0x8]; 6488 u8 reserved_at_8[0x18]; 6489 6490 u8 syndrome[0x20]; 6491 6492 u8 reserved_at_40[0x8]; 6493 u8 srqn[0x18]; 6494 6495 u8 reserved_at_60[0x20]; 6496 }; 6497 6498 struct mlx5_ifc_create_srq_in_bits { 6499 u8 opcode[0x10]; 6500 u8 reserved_at_10[0x10]; 6501 6502 u8 reserved_at_20[0x10]; 6503 u8 op_mod[0x10]; 6504 6505 u8 reserved_at_40[0x40]; 6506 6507 struct mlx5_ifc_srqc_bits srq_context_entry; 6508 6509 u8 reserved_at_280[0x600]; 6510 6511 u8 pas[0][0x40]; 6512 }; 6513 6514 struct mlx5_ifc_create_sq_out_bits { 6515 u8 status[0x8]; 6516 u8 reserved_at_8[0x18]; 6517 6518 u8 syndrome[0x20]; 6519 6520 u8 reserved_at_40[0x8]; 6521 u8 sqn[0x18]; 6522 6523 u8 reserved_at_60[0x20]; 6524 }; 6525 6526 struct mlx5_ifc_create_sq_in_bits { 6527 u8 opcode[0x10]; 6528 u8 reserved_at_10[0x10]; 6529 6530 u8 reserved_at_20[0x10]; 6531 u8 op_mod[0x10]; 6532 6533 u8 reserved_at_40[0xc0]; 6534 6535 struct mlx5_ifc_sqc_bits ctx; 6536 }; 6537 6538 struct mlx5_ifc_create_scheduling_element_out_bits { 6539 u8 status[0x8]; 6540 u8 reserved_at_8[0x18]; 6541 6542 u8 syndrome[0x20]; 6543 6544 u8 reserved_at_40[0x40]; 6545 6546 u8 scheduling_element_id[0x20]; 6547 6548 u8 reserved_at_a0[0x160]; 6549 }; 6550 6551 struct mlx5_ifc_create_scheduling_element_in_bits { 6552 u8 opcode[0x10]; 6553 u8 reserved_at_10[0x10]; 6554 6555 u8 reserved_at_20[0x10]; 6556 u8 op_mod[0x10]; 6557 6558 u8 scheduling_hierarchy[0x8]; 6559 u8 reserved_at_48[0x18]; 6560 6561 u8 reserved_at_60[0xa0]; 6562 6563 struct mlx5_ifc_scheduling_context_bits scheduling_context; 6564 6565 u8 reserved_at_300[0x100]; 6566 }; 6567 6568 struct mlx5_ifc_create_rqt_out_bits { 6569 u8 status[0x8]; 6570 u8 reserved_at_8[0x18]; 6571 6572 u8 syndrome[0x20]; 6573 6574 u8 reserved_at_40[0x8]; 6575 u8 rqtn[0x18]; 6576 6577 u8 reserved_at_60[0x20]; 6578 }; 6579 6580 struct mlx5_ifc_create_rqt_in_bits { 6581 u8 opcode[0x10]; 6582 u8 reserved_at_10[0x10]; 6583 6584 u8 reserved_at_20[0x10]; 6585 u8 op_mod[0x10]; 6586 6587 u8 reserved_at_40[0xc0]; 6588 6589 struct mlx5_ifc_rqtc_bits rqt_context; 6590 }; 6591 6592 struct mlx5_ifc_create_rq_out_bits { 6593 u8 status[0x8]; 6594 u8 reserved_at_8[0x18]; 6595 6596 u8 syndrome[0x20]; 6597 6598 u8 reserved_at_40[0x8]; 6599 u8 rqn[0x18]; 6600 6601 u8 reserved_at_60[0x20]; 6602 }; 6603 6604 struct mlx5_ifc_create_rq_in_bits { 6605 u8 opcode[0x10]; 6606 u8 reserved_at_10[0x10]; 6607 6608 u8 reserved_at_20[0x10]; 6609 u8 op_mod[0x10]; 6610 6611 u8 reserved_at_40[0xc0]; 6612 6613 struct mlx5_ifc_rqc_bits ctx; 6614 }; 6615 6616 struct mlx5_ifc_create_rmp_out_bits { 6617 u8 status[0x8]; 6618 u8 reserved_at_8[0x18]; 6619 6620 u8 syndrome[0x20]; 6621 6622 u8 reserved_at_40[0x8]; 6623 u8 rmpn[0x18]; 6624 6625 u8 reserved_at_60[0x20]; 6626 }; 6627 6628 struct mlx5_ifc_create_rmp_in_bits { 6629 u8 opcode[0x10]; 6630 u8 reserved_at_10[0x10]; 6631 6632 u8 reserved_at_20[0x10]; 6633 u8 op_mod[0x10]; 6634 6635 u8 reserved_at_40[0xc0]; 6636 6637 struct mlx5_ifc_rmpc_bits ctx; 6638 }; 6639 6640 struct mlx5_ifc_create_qp_out_bits { 6641 u8 status[0x8]; 6642 u8 reserved_at_8[0x18]; 6643 6644 u8 syndrome[0x20]; 6645 6646 u8 reserved_at_40[0x8]; 6647 u8 qpn[0x18]; 6648 6649 u8 reserved_at_60[0x20]; 6650 }; 6651 6652 struct mlx5_ifc_create_qp_in_bits { 6653 u8 opcode[0x10]; 6654 u8 reserved_at_10[0x10]; 6655 6656 u8 reserved_at_20[0x10]; 6657 u8 op_mod[0x10]; 6658 6659 u8 reserved_at_40[0x40]; 6660 6661 u8 opt_param_mask[0x20]; 6662 6663 u8 reserved_at_a0[0x20]; 6664 6665 struct mlx5_ifc_qpc_bits qpc; 6666 6667 u8 reserved_at_800[0x80]; 6668 6669 u8 pas[0][0x40]; 6670 }; 6671 6672 struct mlx5_ifc_create_psv_out_bits { 6673 u8 status[0x8]; 6674 u8 reserved_at_8[0x18]; 6675 6676 u8 syndrome[0x20]; 6677 6678 u8 reserved_at_40[0x40]; 6679 6680 u8 reserved_at_80[0x8]; 6681 u8 psv0_index[0x18]; 6682 6683 u8 reserved_at_a0[0x8]; 6684 u8 psv1_index[0x18]; 6685 6686 u8 reserved_at_c0[0x8]; 6687 u8 psv2_index[0x18]; 6688 6689 u8 reserved_at_e0[0x8]; 6690 u8 psv3_index[0x18]; 6691 }; 6692 6693 struct mlx5_ifc_create_psv_in_bits { 6694 u8 opcode[0x10]; 6695 u8 reserved_at_10[0x10]; 6696 6697 u8 reserved_at_20[0x10]; 6698 u8 op_mod[0x10]; 6699 6700 u8 num_psv[0x4]; 6701 u8 reserved_at_44[0x4]; 6702 u8 pd[0x18]; 6703 6704 u8 reserved_at_60[0x20]; 6705 }; 6706 6707 struct mlx5_ifc_create_mkey_out_bits { 6708 u8 status[0x8]; 6709 u8 reserved_at_8[0x18]; 6710 6711 u8 syndrome[0x20]; 6712 6713 u8 reserved_at_40[0x8]; 6714 u8 mkey_index[0x18]; 6715 6716 u8 reserved_at_60[0x20]; 6717 }; 6718 6719 struct mlx5_ifc_create_mkey_in_bits { 6720 u8 opcode[0x10]; 6721 u8 reserved_at_10[0x10]; 6722 6723 u8 reserved_at_20[0x10]; 6724 u8 op_mod[0x10]; 6725 6726 u8 reserved_at_40[0x20]; 6727 6728 u8 pg_access[0x1]; 6729 u8 reserved_at_61[0x1f]; 6730 6731 struct mlx5_ifc_mkc_bits memory_key_mkey_entry; 6732 6733 u8 reserved_at_280[0x80]; 6734 6735 u8 translations_octword_actual_size[0x20]; 6736 6737 u8 reserved_at_320[0x560]; 6738 6739 u8 klm_pas_mtt[0][0x20]; 6740 }; 6741 6742 struct mlx5_ifc_create_flow_table_out_bits { 6743 u8 status[0x8]; 6744 u8 reserved_at_8[0x18]; 6745 6746 u8 syndrome[0x20]; 6747 6748 u8 reserved_at_40[0x8]; 6749 u8 table_id[0x18]; 6750 6751 u8 reserved_at_60[0x20]; 6752 }; 6753 6754 struct mlx5_ifc_flow_table_context_bits { 6755 u8 encap_en[0x1]; 6756 u8 decap_en[0x1]; 6757 u8 reserved_at_2[0x2]; 6758 u8 table_miss_action[0x4]; 6759 u8 level[0x8]; 6760 u8 reserved_at_10[0x8]; 6761 u8 log_size[0x8]; 6762 6763 u8 reserved_at_20[0x8]; 6764 u8 table_miss_id[0x18]; 6765 6766 u8 reserved_at_40[0x8]; 6767 u8 lag_master_next_table_id[0x18]; 6768 6769 u8 reserved_at_60[0xe0]; 6770 }; 6771 6772 struct mlx5_ifc_create_flow_table_in_bits { 6773 u8 opcode[0x10]; 6774 u8 reserved_at_10[0x10]; 6775 6776 u8 reserved_at_20[0x10]; 6777 u8 op_mod[0x10]; 6778 6779 u8 other_vport[0x1]; 6780 u8 reserved_at_41[0xf]; 6781 u8 vport_number[0x10]; 6782 6783 u8 reserved_at_60[0x20]; 6784 6785 u8 table_type[0x8]; 6786 u8 reserved_at_88[0x18]; 6787 6788 u8 reserved_at_a0[0x20]; 6789 6790 struct mlx5_ifc_flow_table_context_bits flow_table_context; 6791 }; 6792 6793 struct mlx5_ifc_create_flow_group_out_bits { 6794 u8 status[0x8]; 6795 u8 reserved_at_8[0x18]; 6796 6797 u8 syndrome[0x20]; 6798 6799 u8 reserved_at_40[0x8]; 6800 u8 group_id[0x18]; 6801 6802 u8 reserved_at_60[0x20]; 6803 }; 6804 6805 enum { 6806 MLX5_CREATE_FLOW_GROUP_IN_MATCH_CRITERIA_ENABLE_OUTER_HEADERS = 0x0, 6807 MLX5_CREATE_FLOW_GROUP_IN_MATCH_CRITERIA_ENABLE_MISC_PARAMETERS = 0x1, 6808 MLX5_CREATE_FLOW_GROUP_IN_MATCH_CRITERIA_ENABLE_INNER_HEADERS = 0x2, 6809 }; 6810 6811 struct mlx5_ifc_create_flow_group_in_bits { 6812 u8 opcode[0x10]; 6813 u8 reserved_at_10[0x10]; 6814 6815 u8 reserved_at_20[0x10]; 6816 u8 op_mod[0x10]; 6817 6818 u8 other_vport[0x1]; 6819 u8 reserved_at_41[0xf]; 6820 u8 vport_number[0x10]; 6821 6822 u8 reserved_at_60[0x20]; 6823 6824 u8 table_type[0x8]; 6825 u8 reserved_at_88[0x18]; 6826 6827 u8 reserved_at_a0[0x8]; 6828 u8 table_id[0x18]; 6829 6830 u8 reserved_at_c0[0x20]; 6831 6832 u8 start_flow_index[0x20]; 6833 6834 u8 reserved_at_100[0x20]; 6835 6836 u8 end_flow_index[0x20]; 6837 6838 u8 reserved_at_140[0xa0]; 6839 6840 u8 reserved_at_1e0[0x18]; 6841 u8 match_criteria_enable[0x8]; 6842 6843 struct mlx5_ifc_fte_match_param_bits match_criteria; 6844 6845 u8 reserved_at_1200[0xe00]; 6846 }; 6847 6848 struct mlx5_ifc_create_eq_out_bits { 6849 u8 status[0x8]; 6850 u8 reserved_at_8[0x18]; 6851 6852 u8 syndrome[0x20]; 6853 6854 u8 reserved_at_40[0x18]; 6855 u8 eq_number[0x8]; 6856 6857 u8 reserved_at_60[0x20]; 6858 }; 6859 6860 struct mlx5_ifc_create_eq_in_bits { 6861 u8 opcode[0x10]; 6862 u8 reserved_at_10[0x10]; 6863 6864 u8 reserved_at_20[0x10]; 6865 u8 op_mod[0x10]; 6866 6867 u8 reserved_at_40[0x40]; 6868 6869 struct mlx5_ifc_eqc_bits eq_context_entry; 6870 6871 u8 reserved_at_280[0x40]; 6872 6873 u8 event_bitmask[0x40]; 6874 6875 u8 reserved_at_300[0x580]; 6876 6877 u8 pas[0][0x40]; 6878 }; 6879 6880 struct mlx5_ifc_create_dct_out_bits { 6881 u8 status[0x8]; 6882 u8 reserved_at_8[0x18]; 6883 6884 u8 syndrome[0x20]; 6885 6886 u8 reserved_at_40[0x8]; 6887 u8 dctn[0x18]; 6888 6889 u8 reserved_at_60[0x20]; 6890 }; 6891 6892 struct mlx5_ifc_create_dct_in_bits { 6893 u8 opcode[0x10]; 6894 u8 reserved_at_10[0x10]; 6895 6896 u8 reserved_at_20[0x10]; 6897 u8 op_mod[0x10]; 6898 6899 u8 reserved_at_40[0x40]; 6900 6901 struct mlx5_ifc_dctc_bits dct_context_entry; 6902 6903 u8 reserved_at_280[0x180]; 6904 }; 6905 6906 struct mlx5_ifc_create_cq_out_bits { 6907 u8 status[0x8]; 6908 u8 reserved_at_8[0x18]; 6909 6910 u8 syndrome[0x20]; 6911 6912 u8 reserved_at_40[0x8]; 6913 u8 cqn[0x18]; 6914 6915 u8 reserved_at_60[0x20]; 6916 }; 6917 6918 struct mlx5_ifc_create_cq_in_bits { 6919 u8 opcode[0x10]; 6920 u8 reserved_at_10[0x10]; 6921 6922 u8 reserved_at_20[0x10]; 6923 u8 op_mod[0x10]; 6924 6925 u8 reserved_at_40[0x40]; 6926 6927 struct mlx5_ifc_cqc_bits cq_context; 6928 6929 u8 reserved_at_280[0x600]; 6930 6931 u8 pas[0][0x40]; 6932 }; 6933 6934 struct mlx5_ifc_config_int_moderation_out_bits { 6935 u8 status[0x8]; 6936 u8 reserved_at_8[0x18]; 6937 6938 u8 syndrome[0x20]; 6939 6940 u8 reserved_at_40[0x4]; 6941 u8 min_delay[0xc]; 6942 u8 int_vector[0x10]; 6943 6944 u8 reserved_at_60[0x20]; 6945 }; 6946 6947 enum { 6948 MLX5_CONFIG_INT_MODERATION_IN_OP_MOD_WRITE = 0x0, 6949 MLX5_CONFIG_INT_MODERATION_IN_OP_MOD_READ = 0x1, 6950 }; 6951 6952 struct mlx5_ifc_config_int_moderation_in_bits { 6953 u8 opcode[0x10]; 6954 u8 reserved_at_10[0x10]; 6955 6956 u8 reserved_at_20[0x10]; 6957 u8 op_mod[0x10]; 6958 6959 u8 reserved_at_40[0x4]; 6960 u8 min_delay[0xc]; 6961 u8 int_vector[0x10]; 6962 6963 u8 reserved_at_60[0x20]; 6964 }; 6965 6966 struct mlx5_ifc_attach_to_mcg_out_bits { 6967 u8 status[0x8]; 6968 u8 reserved_at_8[0x18]; 6969 6970 u8 syndrome[0x20]; 6971 6972 u8 reserved_at_40[0x40]; 6973 }; 6974 6975 struct mlx5_ifc_attach_to_mcg_in_bits { 6976 u8 opcode[0x10]; 6977 u8 reserved_at_10[0x10]; 6978 6979 u8 reserved_at_20[0x10]; 6980 u8 op_mod[0x10]; 6981 6982 u8 reserved_at_40[0x8]; 6983 u8 qpn[0x18]; 6984 6985 u8 reserved_at_60[0x20]; 6986 6987 u8 multicast_gid[16][0x8]; 6988 }; 6989 6990 struct mlx5_ifc_arm_xrq_out_bits { 6991 u8 status[0x8]; 6992 u8 reserved_at_8[0x18]; 6993 6994 u8 syndrome[0x20]; 6995 6996 u8 reserved_at_40[0x40]; 6997 }; 6998 6999 struct mlx5_ifc_arm_xrq_in_bits { 7000 u8 opcode[0x10]; 7001 u8 reserved_at_10[0x10]; 7002 7003 u8 reserved_at_20[0x10]; 7004 u8 op_mod[0x10]; 7005 7006 u8 reserved_at_40[0x8]; 7007 u8 xrqn[0x18]; 7008 7009 u8 reserved_at_60[0x10]; 7010 u8 lwm[0x10]; 7011 }; 7012 7013 struct mlx5_ifc_arm_xrc_srq_out_bits { 7014 u8 status[0x8]; 7015 u8 reserved_at_8[0x18]; 7016 7017 u8 syndrome[0x20]; 7018 7019 u8 reserved_at_40[0x40]; 7020 }; 7021 7022 enum { 7023 MLX5_ARM_XRC_SRQ_IN_OP_MOD_XRC_SRQ = 0x1, 7024 }; 7025 7026 struct mlx5_ifc_arm_xrc_srq_in_bits { 7027 u8 opcode[0x10]; 7028 u8 reserved_at_10[0x10]; 7029 7030 u8 reserved_at_20[0x10]; 7031 u8 op_mod[0x10]; 7032 7033 u8 reserved_at_40[0x8]; 7034 u8 xrc_srqn[0x18]; 7035 7036 u8 reserved_at_60[0x10]; 7037 u8 lwm[0x10]; 7038 }; 7039 7040 struct mlx5_ifc_arm_rq_out_bits { 7041 u8 status[0x8]; 7042 u8 reserved_at_8[0x18]; 7043 7044 u8 syndrome[0x20]; 7045 7046 u8 reserved_at_40[0x40]; 7047 }; 7048 7049 enum { 7050 MLX5_ARM_RQ_IN_OP_MOD_SRQ = 0x1, 7051 MLX5_ARM_RQ_IN_OP_MOD_XRQ = 0x2, 7052 }; 7053 7054 struct mlx5_ifc_arm_rq_in_bits { 7055 u8 opcode[0x10]; 7056 u8 reserved_at_10[0x10]; 7057 7058 u8 reserved_at_20[0x10]; 7059 u8 op_mod[0x10]; 7060 7061 u8 reserved_at_40[0x8]; 7062 u8 srq_number[0x18]; 7063 7064 u8 reserved_at_60[0x10]; 7065 u8 lwm[0x10]; 7066 }; 7067 7068 struct mlx5_ifc_arm_dct_out_bits { 7069 u8 status[0x8]; 7070 u8 reserved_at_8[0x18]; 7071 7072 u8 syndrome[0x20]; 7073 7074 u8 reserved_at_40[0x40]; 7075 }; 7076 7077 struct mlx5_ifc_arm_dct_in_bits { 7078 u8 opcode[0x10]; 7079 u8 reserved_at_10[0x10]; 7080 7081 u8 reserved_at_20[0x10]; 7082 u8 op_mod[0x10]; 7083 7084 u8 reserved_at_40[0x8]; 7085 u8 dct_number[0x18]; 7086 7087 u8 reserved_at_60[0x20]; 7088 }; 7089 7090 struct mlx5_ifc_alloc_xrcd_out_bits { 7091 u8 status[0x8]; 7092 u8 reserved_at_8[0x18]; 7093 7094 u8 syndrome[0x20]; 7095 7096 u8 reserved_at_40[0x8]; 7097 u8 xrcd[0x18]; 7098 7099 u8 reserved_at_60[0x20]; 7100 }; 7101 7102 struct mlx5_ifc_alloc_xrcd_in_bits { 7103 u8 opcode[0x10]; 7104 u8 reserved_at_10[0x10]; 7105 7106 u8 reserved_at_20[0x10]; 7107 u8 op_mod[0x10]; 7108 7109 u8 reserved_at_40[0x40]; 7110 }; 7111 7112 struct mlx5_ifc_alloc_uar_out_bits { 7113 u8 status[0x8]; 7114 u8 reserved_at_8[0x18]; 7115 7116 u8 syndrome[0x20]; 7117 7118 u8 reserved_at_40[0x8]; 7119 u8 uar[0x18]; 7120 7121 u8 reserved_at_60[0x20]; 7122 }; 7123 7124 struct mlx5_ifc_alloc_uar_in_bits { 7125 u8 opcode[0x10]; 7126 u8 reserved_at_10[0x10]; 7127 7128 u8 reserved_at_20[0x10]; 7129 u8 op_mod[0x10]; 7130 7131 u8 reserved_at_40[0x40]; 7132 }; 7133 7134 struct mlx5_ifc_alloc_transport_domain_out_bits { 7135 u8 status[0x8]; 7136 u8 reserved_at_8[0x18]; 7137 7138 u8 syndrome[0x20]; 7139 7140 u8 reserved_at_40[0x8]; 7141 u8 transport_domain[0x18]; 7142 7143 u8 reserved_at_60[0x20]; 7144 }; 7145 7146 struct mlx5_ifc_alloc_transport_domain_in_bits { 7147 u8 opcode[0x10]; 7148 u8 reserved_at_10[0x10]; 7149 7150 u8 reserved_at_20[0x10]; 7151 u8 op_mod[0x10]; 7152 7153 u8 reserved_at_40[0x40]; 7154 }; 7155 7156 struct mlx5_ifc_alloc_q_counter_out_bits { 7157 u8 status[0x8]; 7158 u8 reserved_at_8[0x18]; 7159 7160 u8 syndrome[0x20]; 7161 7162 u8 reserved_at_40[0x18]; 7163 u8 counter_set_id[0x8]; 7164 7165 u8 reserved_at_60[0x20]; 7166 }; 7167 7168 struct mlx5_ifc_alloc_q_counter_in_bits { 7169 u8 opcode[0x10]; 7170 u8 reserved_at_10[0x10]; 7171 7172 u8 reserved_at_20[0x10]; 7173 u8 op_mod[0x10]; 7174 7175 u8 reserved_at_40[0x40]; 7176 }; 7177 7178 struct mlx5_ifc_alloc_pd_out_bits { 7179 u8 status[0x8]; 7180 u8 reserved_at_8[0x18]; 7181 7182 u8 syndrome[0x20]; 7183 7184 u8 reserved_at_40[0x8]; 7185 u8 pd[0x18]; 7186 7187 u8 reserved_at_60[0x20]; 7188 }; 7189 7190 struct mlx5_ifc_alloc_pd_in_bits { 7191 u8 opcode[0x10]; 7192 u8 reserved_at_10[0x10]; 7193 7194 u8 reserved_at_20[0x10]; 7195 u8 op_mod[0x10]; 7196 7197 u8 reserved_at_40[0x40]; 7198 }; 7199 7200 struct mlx5_ifc_alloc_flow_counter_out_bits { 7201 u8 status[0x8]; 7202 u8 reserved_at_8[0x18]; 7203 7204 u8 syndrome[0x20]; 7205 7206 u8 flow_counter_id[0x20]; 7207 7208 u8 reserved_at_60[0x20]; 7209 }; 7210 7211 struct mlx5_ifc_alloc_flow_counter_in_bits { 7212 u8 opcode[0x10]; 7213 u8 reserved_at_10[0x10]; 7214 7215 u8 reserved_at_20[0x10]; 7216 u8 op_mod[0x10]; 7217 7218 u8 reserved_at_40[0x40]; 7219 }; 7220 7221 struct mlx5_ifc_add_vxlan_udp_dport_out_bits { 7222 u8 status[0x8]; 7223 u8 reserved_at_8[0x18]; 7224 7225 u8 syndrome[0x20]; 7226 7227 u8 reserved_at_40[0x40]; 7228 }; 7229 7230 struct mlx5_ifc_add_vxlan_udp_dport_in_bits { 7231 u8 opcode[0x10]; 7232 u8 reserved_at_10[0x10]; 7233 7234 u8 reserved_at_20[0x10]; 7235 u8 op_mod[0x10]; 7236 7237 u8 reserved_at_40[0x20]; 7238 7239 u8 reserved_at_60[0x10]; 7240 u8 vxlan_udp_port[0x10]; 7241 }; 7242 7243 struct mlx5_ifc_set_pp_rate_limit_out_bits { 7244 u8 status[0x8]; 7245 u8 reserved_at_8[0x18]; 7246 7247 u8 syndrome[0x20]; 7248 7249 u8 reserved_at_40[0x40]; 7250 }; 7251 7252 struct mlx5_ifc_set_pp_rate_limit_in_bits { 7253 u8 opcode[0x10]; 7254 u8 reserved_at_10[0x10]; 7255 7256 u8 reserved_at_20[0x10]; 7257 u8 op_mod[0x10]; 7258 7259 u8 reserved_at_40[0x10]; 7260 u8 rate_limit_index[0x10]; 7261 7262 u8 reserved_at_60[0x20]; 7263 7264 u8 rate_limit[0x20]; 7265 7266 u8 reserved_at_a0[0x160]; 7267 }; 7268 7269 struct mlx5_ifc_access_register_out_bits { 7270 u8 status[0x8]; 7271 u8 reserved_at_8[0x18]; 7272 7273 u8 syndrome[0x20]; 7274 7275 u8 reserved_at_40[0x40]; 7276 7277 u8 register_data[0][0x20]; 7278 }; 7279 7280 enum { 7281 MLX5_ACCESS_REGISTER_IN_OP_MOD_WRITE = 0x0, 7282 MLX5_ACCESS_REGISTER_IN_OP_MOD_READ = 0x1, 7283 }; 7284 7285 struct mlx5_ifc_access_register_in_bits { 7286 u8 opcode[0x10]; 7287 u8 reserved_at_10[0x10]; 7288 7289 u8 reserved_at_20[0x10]; 7290 u8 op_mod[0x10]; 7291 7292 u8 reserved_at_40[0x10]; 7293 u8 register_id[0x10]; 7294 7295 u8 argument[0x20]; 7296 7297 u8 register_data[0][0x20]; 7298 }; 7299 7300 struct mlx5_ifc_sltp_reg_bits { 7301 u8 status[0x4]; 7302 u8 version[0x4]; 7303 u8 local_port[0x8]; 7304 u8 pnat[0x2]; 7305 u8 reserved_at_12[0x2]; 7306 u8 lane[0x4]; 7307 u8 reserved_at_18[0x8]; 7308 7309 u8 reserved_at_20[0x20]; 7310 7311 u8 reserved_at_40[0x7]; 7312 u8 polarity[0x1]; 7313 u8 ob_tap0[0x8]; 7314 u8 ob_tap1[0x8]; 7315 u8 ob_tap2[0x8]; 7316 7317 u8 reserved_at_60[0xc]; 7318 u8 ob_preemp_mode[0x4]; 7319 u8 ob_reg[0x8]; 7320 u8 ob_bias[0x8]; 7321 7322 u8 reserved_at_80[0x20]; 7323 }; 7324 7325 struct mlx5_ifc_slrg_reg_bits { 7326 u8 status[0x4]; 7327 u8 version[0x4]; 7328 u8 local_port[0x8]; 7329 u8 pnat[0x2]; 7330 u8 reserved_at_12[0x2]; 7331 u8 lane[0x4]; 7332 u8 reserved_at_18[0x8]; 7333 7334 u8 time_to_link_up[0x10]; 7335 u8 reserved_at_30[0xc]; 7336 u8 grade_lane_speed[0x4]; 7337 7338 u8 grade_version[0x8]; 7339 u8 grade[0x18]; 7340 7341 u8 reserved_at_60[0x4]; 7342 u8 height_grade_type[0x4]; 7343 u8 height_grade[0x18]; 7344 7345 u8 height_dz[0x10]; 7346 u8 height_dv[0x10]; 7347 7348 u8 reserved_at_a0[0x10]; 7349 u8 height_sigma[0x10]; 7350 7351 u8 reserved_at_c0[0x20]; 7352 7353 u8 reserved_at_e0[0x4]; 7354 u8 phase_grade_type[0x4]; 7355 u8 phase_grade[0x18]; 7356 7357 u8 reserved_at_100[0x8]; 7358 u8 phase_eo_pos[0x8]; 7359 u8 reserved_at_110[0x8]; 7360 u8 phase_eo_neg[0x8]; 7361 7362 u8 ffe_set_tested[0x10]; 7363 u8 test_errors_per_lane[0x10]; 7364 }; 7365 7366 struct mlx5_ifc_pvlc_reg_bits { 7367 u8 reserved_at_0[0x8]; 7368 u8 local_port[0x8]; 7369 u8 reserved_at_10[0x10]; 7370 7371 u8 reserved_at_20[0x1c]; 7372 u8 vl_hw_cap[0x4]; 7373 7374 u8 reserved_at_40[0x1c]; 7375 u8 vl_admin[0x4]; 7376 7377 u8 reserved_at_60[0x1c]; 7378 u8 vl_operational[0x4]; 7379 }; 7380 7381 struct mlx5_ifc_pude_reg_bits { 7382 u8 swid[0x8]; 7383 u8 local_port[0x8]; 7384 u8 reserved_at_10[0x4]; 7385 u8 admin_status[0x4]; 7386 u8 reserved_at_18[0x4]; 7387 u8 oper_status[0x4]; 7388 7389 u8 reserved_at_20[0x60]; 7390 }; 7391 7392 struct mlx5_ifc_ptys_reg_bits { 7393 u8 reserved_at_0[0x1]; 7394 u8 an_disable_admin[0x1]; 7395 u8 an_disable_cap[0x1]; 7396 u8 reserved_at_3[0x5]; 7397 u8 local_port[0x8]; 7398 u8 reserved_at_10[0xd]; 7399 u8 proto_mask[0x3]; 7400 7401 u8 an_status[0x4]; 7402 u8 reserved_at_24[0x3c]; 7403 7404 u8 eth_proto_capability[0x20]; 7405 7406 u8 ib_link_width_capability[0x10]; 7407 u8 ib_proto_capability[0x10]; 7408 7409 u8 reserved_at_a0[0x20]; 7410 7411 u8 eth_proto_admin[0x20]; 7412 7413 u8 ib_link_width_admin[0x10]; 7414 u8 ib_proto_admin[0x10]; 7415 7416 u8 reserved_at_100[0x20]; 7417 7418 u8 eth_proto_oper[0x20]; 7419 7420 u8 ib_link_width_oper[0x10]; 7421 u8 ib_proto_oper[0x10]; 7422 7423 u8 reserved_at_160[0x1c]; 7424 u8 connector_type[0x4]; 7425 7426 u8 eth_proto_lp_advertise[0x20]; 7427 7428 u8 reserved_at_1a0[0x60]; 7429 }; 7430 7431 struct mlx5_ifc_mlcr_reg_bits { 7432 u8 reserved_at_0[0x8]; 7433 u8 local_port[0x8]; 7434 u8 reserved_at_10[0x20]; 7435 7436 u8 beacon_duration[0x10]; 7437 u8 reserved_at_40[0x10]; 7438 7439 u8 beacon_remain[0x10]; 7440 }; 7441 7442 struct mlx5_ifc_ptas_reg_bits { 7443 u8 reserved_at_0[0x20]; 7444 7445 u8 algorithm_options[0x10]; 7446 u8 reserved_at_30[0x4]; 7447 u8 repetitions_mode[0x4]; 7448 u8 num_of_repetitions[0x8]; 7449 7450 u8 grade_version[0x8]; 7451 u8 height_grade_type[0x4]; 7452 u8 phase_grade_type[0x4]; 7453 u8 height_grade_weight[0x8]; 7454 u8 phase_grade_weight[0x8]; 7455 7456 u8 gisim_measure_bits[0x10]; 7457 u8 adaptive_tap_measure_bits[0x10]; 7458 7459 u8 ber_bath_high_error_threshold[0x10]; 7460 u8 ber_bath_mid_error_threshold[0x10]; 7461 7462 u8 ber_bath_low_error_threshold[0x10]; 7463 u8 one_ratio_high_threshold[0x10]; 7464 7465 u8 one_ratio_high_mid_threshold[0x10]; 7466 u8 one_ratio_low_mid_threshold[0x10]; 7467 7468 u8 one_ratio_low_threshold[0x10]; 7469 u8 ndeo_error_threshold[0x10]; 7470 7471 u8 mixer_offset_step_size[0x10]; 7472 u8 reserved_at_110[0x8]; 7473 u8 mix90_phase_for_voltage_bath[0x8]; 7474 7475 u8 mixer_offset_start[0x10]; 7476 u8 mixer_offset_end[0x10]; 7477 7478 u8 reserved_at_140[0x15]; 7479 u8 ber_test_time[0xb]; 7480 }; 7481 7482 struct mlx5_ifc_pspa_reg_bits { 7483 u8 swid[0x8]; 7484 u8 local_port[0x8]; 7485 u8 sub_port[0x8]; 7486 u8 reserved_at_18[0x8]; 7487 7488 u8 reserved_at_20[0x20]; 7489 }; 7490 7491 struct mlx5_ifc_pqdr_reg_bits { 7492 u8 reserved_at_0[0x8]; 7493 u8 local_port[0x8]; 7494 u8 reserved_at_10[0x5]; 7495 u8 prio[0x3]; 7496 u8 reserved_at_18[0x6]; 7497 u8 mode[0x2]; 7498 7499 u8 reserved_at_20[0x20]; 7500 7501 u8 reserved_at_40[0x10]; 7502 u8 min_threshold[0x10]; 7503 7504 u8 reserved_at_60[0x10]; 7505 u8 max_threshold[0x10]; 7506 7507 u8 reserved_at_80[0x10]; 7508 u8 mark_probability_denominator[0x10]; 7509 7510 u8 reserved_at_a0[0x60]; 7511 }; 7512 7513 struct mlx5_ifc_ppsc_reg_bits { 7514 u8 reserved_at_0[0x8]; 7515 u8 local_port[0x8]; 7516 u8 reserved_at_10[0x10]; 7517 7518 u8 reserved_at_20[0x60]; 7519 7520 u8 reserved_at_80[0x1c]; 7521 u8 wrps_admin[0x4]; 7522 7523 u8 reserved_at_a0[0x1c]; 7524 u8 wrps_status[0x4]; 7525 7526 u8 reserved_at_c0[0x8]; 7527 u8 up_threshold[0x8]; 7528 u8 reserved_at_d0[0x8]; 7529 u8 down_threshold[0x8]; 7530 7531 u8 reserved_at_e0[0x20]; 7532 7533 u8 reserved_at_100[0x1c]; 7534 u8 srps_admin[0x4]; 7535 7536 u8 reserved_at_120[0x1c]; 7537 u8 srps_status[0x4]; 7538 7539 u8 reserved_at_140[0x40]; 7540 }; 7541 7542 struct mlx5_ifc_pplr_reg_bits { 7543 u8 reserved_at_0[0x8]; 7544 u8 local_port[0x8]; 7545 u8 reserved_at_10[0x10]; 7546 7547 u8 reserved_at_20[0x8]; 7548 u8 lb_cap[0x8]; 7549 u8 reserved_at_30[0x8]; 7550 u8 lb_en[0x8]; 7551 }; 7552 7553 struct mlx5_ifc_pplm_reg_bits { 7554 u8 reserved_at_0[0x8]; 7555 u8 local_port[0x8]; 7556 u8 reserved_at_10[0x10]; 7557 7558 u8 reserved_at_20[0x20]; 7559 7560 u8 port_profile_mode[0x8]; 7561 u8 static_port_profile[0x8]; 7562 u8 active_port_profile[0x8]; 7563 u8 reserved_at_58[0x8]; 7564 7565 u8 retransmission_active[0x8]; 7566 u8 fec_mode_active[0x18]; 7567 7568 u8 reserved_at_80[0x20]; 7569 }; 7570 7571 struct mlx5_ifc_ppcnt_reg_bits { 7572 u8 swid[0x8]; 7573 u8 local_port[0x8]; 7574 u8 pnat[0x2]; 7575 u8 reserved_at_12[0x8]; 7576 u8 grp[0x6]; 7577 7578 u8 clr[0x1]; 7579 u8 reserved_at_21[0x1c]; 7580 u8 prio_tc[0x3]; 7581 7582 union mlx5_ifc_eth_cntrs_grp_data_layout_auto_bits counter_set; 7583 }; 7584 7585 struct mlx5_ifc_mpcnt_reg_bits { 7586 u8 reserved_at_0[0x8]; 7587 u8 pcie_index[0x8]; 7588 u8 reserved_at_10[0xa]; 7589 u8 grp[0x6]; 7590 7591 u8 clr[0x1]; 7592 u8 reserved_at_21[0x1f]; 7593 7594 union mlx5_ifc_pcie_cntrs_grp_data_layout_auto_bits counter_set; 7595 }; 7596 7597 struct mlx5_ifc_ppad_reg_bits { 7598 u8 reserved_at_0[0x3]; 7599 u8 single_mac[0x1]; 7600 u8 reserved_at_4[0x4]; 7601 u8 local_port[0x8]; 7602 u8 mac_47_32[0x10]; 7603 7604 u8 mac_31_0[0x20]; 7605 7606 u8 reserved_at_40[0x40]; 7607 }; 7608 7609 struct mlx5_ifc_pmtu_reg_bits { 7610 u8 reserved_at_0[0x8]; 7611 u8 local_port[0x8]; 7612 u8 reserved_at_10[0x10]; 7613 7614 u8 max_mtu[0x10]; 7615 u8 reserved_at_30[0x10]; 7616 7617 u8 admin_mtu[0x10]; 7618 u8 reserved_at_50[0x10]; 7619 7620 u8 oper_mtu[0x10]; 7621 u8 reserved_at_70[0x10]; 7622 }; 7623 7624 struct mlx5_ifc_pmpr_reg_bits { 7625 u8 reserved_at_0[0x8]; 7626 u8 module[0x8]; 7627 u8 reserved_at_10[0x10]; 7628 7629 u8 reserved_at_20[0x18]; 7630 u8 attenuation_5g[0x8]; 7631 7632 u8 reserved_at_40[0x18]; 7633 u8 attenuation_7g[0x8]; 7634 7635 u8 reserved_at_60[0x18]; 7636 u8 attenuation_12g[0x8]; 7637 }; 7638 7639 struct mlx5_ifc_pmpe_reg_bits { 7640 u8 reserved_at_0[0x8]; 7641 u8 module[0x8]; 7642 u8 reserved_at_10[0xc]; 7643 u8 module_status[0x4]; 7644 7645 u8 reserved_at_20[0x60]; 7646 }; 7647 7648 struct mlx5_ifc_pmpc_reg_bits { 7649 u8 module_state_updated[32][0x8]; 7650 }; 7651 7652 struct mlx5_ifc_pmlpn_reg_bits { 7653 u8 reserved_at_0[0x4]; 7654 u8 mlpn_status[0x4]; 7655 u8 local_port[0x8]; 7656 u8 reserved_at_10[0x10]; 7657 7658 u8 e[0x1]; 7659 u8 reserved_at_21[0x1f]; 7660 }; 7661 7662 struct mlx5_ifc_pmlp_reg_bits { 7663 u8 rxtx[0x1]; 7664 u8 reserved_at_1[0x7]; 7665 u8 local_port[0x8]; 7666 u8 reserved_at_10[0x8]; 7667 u8 width[0x8]; 7668 7669 u8 lane0_module_mapping[0x20]; 7670 7671 u8 lane1_module_mapping[0x20]; 7672 7673 u8 lane2_module_mapping[0x20]; 7674 7675 u8 lane3_module_mapping[0x20]; 7676 7677 u8 reserved_at_a0[0x160]; 7678 }; 7679 7680 struct mlx5_ifc_pmaos_reg_bits { 7681 u8 reserved_at_0[0x8]; 7682 u8 module[0x8]; 7683 u8 reserved_at_10[0x4]; 7684 u8 admin_status[0x4]; 7685 u8 reserved_at_18[0x4]; 7686 u8 oper_status[0x4]; 7687 7688 u8 ase[0x1]; 7689 u8 ee[0x1]; 7690 u8 reserved_at_22[0x1c]; 7691 u8 e[0x2]; 7692 7693 u8 reserved_at_40[0x40]; 7694 }; 7695 7696 struct mlx5_ifc_plpc_reg_bits { 7697 u8 reserved_at_0[0x4]; 7698 u8 profile_id[0xc]; 7699 u8 reserved_at_10[0x4]; 7700 u8 proto_mask[0x4]; 7701 u8 reserved_at_18[0x8]; 7702 7703 u8 reserved_at_20[0x10]; 7704 u8 lane_speed[0x10]; 7705 7706 u8 reserved_at_40[0x17]; 7707 u8 lpbf[0x1]; 7708 u8 fec_mode_policy[0x8]; 7709 7710 u8 retransmission_capability[0x8]; 7711 u8 fec_mode_capability[0x18]; 7712 7713 u8 retransmission_support_admin[0x8]; 7714 u8 fec_mode_support_admin[0x18]; 7715 7716 u8 retransmission_request_admin[0x8]; 7717 u8 fec_mode_request_admin[0x18]; 7718 7719 u8 reserved_at_c0[0x80]; 7720 }; 7721 7722 struct mlx5_ifc_plib_reg_bits { 7723 u8 reserved_at_0[0x8]; 7724 u8 local_port[0x8]; 7725 u8 reserved_at_10[0x8]; 7726 u8 ib_port[0x8]; 7727 7728 u8 reserved_at_20[0x60]; 7729 }; 7730 7731 struct mlx5_ifc_plbf_reg_bits { 7732 u8 reserved_at_0[0x8]; 7733 u8 local_port[0x8]; 7734 u8 reserved_at_10[0xd]; 7735 u8 lbf_mode[0x3]; 7736 7737 u8 reserved_at_20[0x20]; 7738 }; 7739 7740 struct mlx5_ifc_pipg_reg_bits { 7741 u8 reserved_at_0[0x8]; 7742 u8 local_port[0x8]; 7743 u8 reserved_at_10[0x10]; 7744 7745 u8 dic[0x1]; 7746 u8 reserved_at_21[0x19]; 7747 u8 ipg[0x4]; 7748 u8 reserved_at_3e[0x2]; 7749 }; 7750 7751 struct mlx5_ifc_pifr_reg_bits { 7752 u8 reserved_at_0[0x8]; 7753 u8 local_port[0x8]; 7754 u8 reserved_at_10[0x10]; 7755 7756 u8 reserved_at_20[0xe0]; 7757 7758 u8 port_filter[8][0x20]; 7759 7760 u8 port_filter_update_en[8][0x20]; 7761 }; 7762 7763 struct mlx5_ifc_pfcc_reg_bits { 7764 u8 reserved_at_0[0x8]; 7765 u8 local_port[0x8]; 7766 u8 reserved_at_10[0x10]; 7767 7768 u8 ppan[0x4]; 7769 u8 reserved_at_24[0x4]; 7770 u8 prio_mask_tx[0x8]; 7771 u8 reserved_at_30[0x8]; 7772 u8 prio_mask_rx[0x8]; 7773 7774 u8 pptx[0x1]; 7775 u8 aptx[0x1]; 7776 u8 reserved_at_42[0x6]; 7777 u8 pfctx[0x8]; 7778 u8 reserved_at_50[0x10]; 7779 7780 u8 pprx[0x1]; 7781 u8 aprx[0x1]; 7782 u8 reserved_at_62[0x6]; 7783 u8 pfcrx[0x8]; 7784 u8 reserved_at_70[0x10]; 7785 7786 u8 reserved_at_80[0x80]; 7787 }; 7788 7789 struct mlx5_ifc_pelc_reg_bits { 7790 u8 op[0x4]; 7791 u8 reserved_at_4[0x4]; 7792 u8 local_port[0x8]; 7793 u8 reserved_at_10[0x10]; 7794 7795 u8 op_admin[0x8]; 7796 u8 op_capability[0x8]; 7797 u8 op_request[0x8]; 7798 u8 op_active[0x8]; 7799 7800 u8 admin[0x40]; 7801 7802 u8 capability[0x40]; 7803 7804 u8 request[0x40]; 7805 7806 u8 active[0x40]; 7807 7808 u8 reserved_at_140[0x80]; 7809 }; 7810 7811 struct mlx5_ifc_peir_reg_bits { 7812 u8 reserved_at_0[0x8]; 7813 u8 local_port[0x8]; 7814 u8 reserved_at_10[0x10]; 7815 7816 u8 reserved_at_20[0xc]; 7817 u8 error_count[0x4]; 7818 u8 reserved_at_30[0x10]; 7819 7820 u8 reserved_at_40[0xc]; 7821 u8 lane[0x4]; 7822 u8 reserved_at_50[0x8]; 7823 u8 error_type[0x8]; 7824 }; 7825 7826 struct mlx5_ifc_pcam_enhanced_features_bits { 7827 u8 reserved_at_0[0x7b]; 7828 7829 u8 rx_buffer_fullness_counters[0x1]; 7830 u8 ptys_connector_type[0x1]; 7831 u8 reserved_at_7d[0x1]; 7832 u8 ppcnt_discard_group[0x1]; 7833 u8 ppcnt_statistical_group[0x1]; 7834 }; 7835 7836 struct mlx5_ifc_pcam_reg_bits { 7837 u8 reserved_at_0[0x8]; 7838 u8 feature_group[0x8]; 7839 u8 reserved_at_10[0x8]; 7840 u8 access_reg_group[0x8]; 7841 7842 u8 reserved_at_20[0x20]; 7843 7844 union { 7845 u8 reserved_at_0[0x80]; 7846 } port_access_reg_cap_mask; 7847 7848 u8 reserved_at_c0[0x80]; 7849 7850 union { 7851 struct mlx5_ifc_pcam_enhanced_features_bits enhanced_features; 7852 u8 reserved_at_0[0x80]; 7853 } feature_cap_mask; 7854 7855 u8 reserved_at_1c0[0xc0]; 7856 }; 7857 7858 struct mlx5_ifc_mcam_enhanced_features_bits { 7859 u8 reserved_at_0[0x7b]; 7860 u8 pcie_outbound_stalled[0x1]; 7861 u8 tx_overflow_buffer_pkt[0x1]; 7862 u8 mtpps_enh_out_per_adj[0x1]; 7863 u8 mtpps_fs[0x1]; 7864 u8 pcie_performance_group[0x1]; 7865 }; 7866 7867 struct mlx5_ifc_mcam_access_reg_bits { 7868 u8 reserved_at_0[0x1c]; 7869 u8 mcda[0x1]; 7870 u8 mcc[0x1]; 7871 u8 mcqi[0x1]; 7872 u8 reserved_at_1f[0x1]; 7873 7874 u8 regs_95_to_64[0x20]; 7875 u8 regs_63_to_32[0x20]; 7876 u8 regs_31_to_0[0x20]; 7877 }; 7878 7879 struct mlx5_ifc_mcam_reg_bits { 7880 u8 reserved_at_0[0x8]; 7881 u8 feature_group[0x8]; 7882 u8 reserved_at_10[0x8]; 7883 u8 access_reg_group[0x8]; 7884 7885 u8 reserved_at_20[0x20]; 7886 7887 union { 7888 struct mlx5_ifc_mcam_access_reg_bits access_regs; 7889 u8 reserved_at_0[0x80]; 7890 } mng_access_reg_cap_mask; 7891 7892 u8 reserved_at_c0[0x80]; 7893 7894 union { 7895 struct mlx5_ifc_mcam_enhanced_features_bits enhanced_features; 7896 u8 reserved_at_0[0x80]; 7897 } mng_feature_cap_mask; 7898 7899 u8 reserved_at_1c0[0x80]; 7900 }; 7901 7902 struct mlx5_ifc_qcam_access_reg_cap_mask { 7903 u8 qcam_access_reg_cap_mask_127_to_20[0x6C]; 7904 u8 qpdpm[0x1]; 7905 u8 qcam_access_reg_cap_mask_18_to_4[0x0F]; 7906 u8 qdpm[0x1]; 7907 u8 qpts[0x1]; 7908 u8 qcap[0x1]; 7909 u8 qcam_access_reg_cap_mask_0[0x1]; 7910 }; 7911 7912 struct mlx5_ifc_qcam_qos_feature_cap_mask { 7913 u8 qcam_qos_feature_cap_mask_127_to_1[0x7F]; 7914 u8 qpts_trust_both[0x1]; 7915 }; 7916 7917 struct mlx5_ifc_qcam_reg_bits { 7918 u8 reserved_at_0[0x8]; 7919 u8 feature_group[0x8]; 7920 u8 reserved_at_10[0x8]; 7921 u8 access_reg_group[0x8]; 7922 u8 reserved_at_20[0x20]; 7923 7924 union { 7925 struct mlx5_ifc_qcam_access_reg_cap_mask reg_cap; 7926 u8 reserved_at_0[0x80]; 7927 } qos_access_reg_cap_mask; 7928 7929 u8 reserved_at_c0[0x80]; 7930 7931 union { 7932 struct mlx5_ifc_qcam_qos_feature_cap_mask feature_cap; 7933 u8 reserved_at_0[0x80]; 7934 } qos_feature_cap_mask; 7935 7936 u8 reserved_at_1c0[0x80]; 7937 }; 7938 7939 struct mlx5_ifc_pcap_reg_bits { 7940 u8 reserved_at_0[0x8]; 7941 u8 local_port[0x8]; 7942 u8 reserved_at_10[0x10]; 7943 7944 u8 port_capability_mask[4][0x20]; 7945 }; 7946 7947 struct mlx5_ifc_paos_reg_bits { 7948 u8 swid[0x8]; 7949 u8 local_port[0x8]; 7950 u8 reserved_at_10[0x4]; 7951 u8 admin_status[0x4]; 7952 u8 reserved_at_18[0x4]; 7953 u8 oper_status[0x4]; 7954 7955 u8 ase[0x1]; 7956 u8 ee[0x1]; 7957 u8 reserved_at_22[0x1c]; 7958 u8 e[0x2]; 7959 7960 u8 reserved_at_40[0x40]; 7961 }; 7962 7963 struct mlx5_ifc_pamp_reg_bits { 7964 u8 reserved_at_0[0x8]; 7965 u8 opamp_group[0x8]; 7966 u8 reserved_at_10[0xc]; 7967 u8 opamp_group_type[0x4]; 7968 7969 u8 start_index[0x10]; 7970 u8 reserved_at_30[0x4]; 7971 u8 num_of_indices[0xc]; 7972 7973 u8 index_data[18][0x10]; 7974 }; 7975 7976 struct mlx5_ifc_pcmr_reg_bits { 7977 u8 reserved_at_0[0x8]; 7978 u8 local_port[0x8]; 7979 u8 reserved_at_10[0x2e]; 7980 u8 fcs_cap[0x1]; 7981 u8 reserved_at_3f[0x1f]; 7982 u8 fcs_chk[0x1]; 7983 u8 reserved_at_5f[0x1]; 7984 }; 7985 7986 struct mlx5_ifc_lane_2_module_mapping_bits { 7987 u8 reserved_at_0[0x6]; 7988 u8 rx_lane[0x2]; 7989 u8 reserved_at_8[0x6]; 7990 u8 tx_lane[0x2]; 7991 u8 reserved_at_10[0x8]; 7992 u8 module[0x8]; 7993 }; 7994 7995 struct mlx5_ifc_bufferx_reg_bits { 7996 u8 reserved_at_0[0x6]; 7997 u8 lossy[0x1]; 7998 u8 epsb[0x1]; 7999 u8 reserved_at_8[0xc]; 8000 u8 size[0xc]; 8001 8002 u8 xoff_threshold[0x10]; 8003 u8 xon_threshold[0x10]; 8004 }; 8005 8006 struct mlx5_ifc_set_node_in_bits { 8007 u8 node_description[64][0x8]; 8008 }; 8009 8010 struct mlx5_ifc_register_power_settings_bits { 8011 u8 reserved_at_0[0x18]; 8012 u8 power_settings_level[0x8]; 8013 8014 u8 reserved_at_20[0x60]; 8015 }; 8016 8017 struct mlx5_ifc_register_host_endianness_bits { 8018 u8 he[0x1]; 8019 u8 reserved_at_1[0x1f]; 8020 8021 u8 reserved_at_20[0x60]; 8022 }; 8023 8024 struct mlx5_ifc_umr_pointer_desc_argument_bits { 8025 u8 reserved_at_0[0x20]; 8026 8027 u8 mkey[0x20]; 8028 8029 u8 addressh_63_32[0x20]; 8030 8031 u8 addressl_31_0[0x20]; 8032 }; 8033 8034 struct mlx5_ifc_ud_adrs_vector_bits { 8035 u8 dc_key[0x40]; 8036 8037 u8 ext[0x1]; 8038 u8 reserved_at_41[0x7]; 8039 u8 destination_qp_dct[0x18]; 8040 8041 u8 static_rate[0x4]; 8042 u8 sl_eth_prio[0x4]; 8043 u8 fl[0x1]; 8044 u8 mlid[0x7]; 8045 u8 rlid_udp_sport[0x10]; 8046 8047 u8 reserved_at_80[0x20]; 8048 8049 u8 rmac_47_16[0x20]; 8050 8051 u8 rmac_15_0[0x10]; 8052 u8 tclass[0x8]; 8053 u8 hop_limit[0x8]; 8054 8055 u8 reserved_at_e0[0x1]; 8056 u8 grh[0x1]; 8057 u8 reserved_at_e2[0x2]; 8058 u8 src_addr_index[0x8]; 8059 u8 flow_label[0x14]; 8060 8061 u8 rgid_rip[16][0x8]; 8062 }; 8063 8064 struct mlx5_ifc_pages_req_event_bits { 8065 u8 reserved_at_0[0x10]; 8066 u8 function_id[0x10]; 8067 8068 u8 num_pages[0x20]; 8069 8070 u8 reserved_at_40[0xa0]; 8071 }; 8072 8073 struct mlx5_ifc_eqe_bits { 8074 u8 reserved_at_0[0x8]; 8075 u8 event_type[0x8]; 8076 u8 reserved_at_10[0x8]; 8077 u8 event_sub_type[0x8]; 8078 8079 u8 reserved_at_20[0xe0]; 8080 8081 union mlx5_ifc_event_auto_bits event_data; 8082 8083 u8 reserved_at_1e0[0x10]; 8084 u8 signature[0x8]; 8085 u8 reserved_at_1f8[0x7]; 8086 u8 owner[0x1]; 8087 }; 8088 8089 enum { 8090 MLX5_CMD_QUEUE_ENTRY_TYPE_PCIE_CMD_IF_TRANSPORT = 0x7, 8091 }; 8092 8093 struct mlx5_ifc_cmd_queue_entry_bits { 8094 u8 type[0x8]; 8095 u8 reserved_at_8[0x18]; 8096 8097 u8 input_length[0x20]; 8098 8099 u8 input_mailbox_pointer_63_32[0x20]; 8100 8101 u8 input_mailbox_pointer_31_9[0x17]; 8102 u8 reserved_at_77[0x9]; 8103 8104 u8 command_input_inline_data[16][0x8]; 8105 8106 u8 command_output_inline_data[16][0x8]; 8107 8108 u8 output_mailbox_pointer_63_32[0x20]; 8109 8110 u8 output_mailbox_pointer_31_9[0x17]; 8111 u8 reserved_at_1b7[0x9]; 8112 8113 u8 output_length[0x20]; 8114 8115 u8 token[0x8]; 8116 u8 signature[0x8]; 8117 u8 reserved_at_1f0[0x8]; 8118 u8 status[0x7]; 8119 u8 ownership[0x1]; 8120 }; 8121 8122 struct mlx5_ifc_cmd_out_bits { 8123 u8 status[0x8]; 8124 u8 reserved_at_8[0x18]; 8125 8126 u8 syndrome[0x20]; 8127 8128 u8 command_output[0x20]; 8129 }; 8130 8131 struct mlx5_ifc_cmd_in_bits { 8132 u8 opcode[0x10]; 8133 u8 reserved_at_10[0x10]; 8134 8135 u8 reserved_at_20[0x10]; 8136 u8 op_mod[0x10]; 8137 8138 u8 command[0][0x20]; 8139 }; 8140 8141 struct mlx5_ifc_cmd_if_box_bits { 8142 u8 mailbox_data[512][0x8]; 8143 8144 u8 reserved_at_1000[0x180]; 8145 8146 u8 next_pointer_63_32[0x20]; 8147 8148 u8 next_pointer_31_10[0x16]; 8149 u8 reserved_at_11b6[0xa]; 8150 8151 u8 block_number[0x20]; 8152 8153 u8 reserved_at_11e0[0x8]; 8154 u8 token[0x8]; 8155 u8 ctrl_signature[0x8]; 8156 u8 signature[0x8]; 8157 }; 8158 8159 struct mlx5_ifc_mtt_bits { 8160 u8 ptag_63_32[0x20]; 8161 8162 u8 ptag_31_8[0x18]; 8163 u8 reserved_at_38[0x6]; 8164 u8 wr_en[0x1]; 8165 u8 rd_en[0x1]; 8166 }; 8167 8168 struct mlx5_ifc_query_wol_rol_out_bits { 8169 u8 status[0x8]; 8170 u8 reserved_at_8[0x18]; 8171 8172 u8 syndrome[0x20]; 8173 8174 u8 reserved_at_40[0x10]; 8175 u8 rol_mode[0x8]; 8176 u8 wol_mode[0x8]; 8177 8178 u8 reserved_at_60[0x20]; 8179 }; 8180 8181 struct mlx5_ifc_query_wol_rol_in_bits { 8182 u8 opcode[0x10]; 8183 u8 reserved_at_10[0x10]; 8184 8185 u8 reserved_at_20[0x10]; 8186 u8 op_mod[0x10]; 8187 8188 u8 reserved_at_40[0x40]; 8189 }; 8190 8191 struct mlx5_ifc_set_wol_rol_out_bits { 8192 u8 status[0x8]; 8193 u8 reserved_at_8[0x18]; 8194 8195 u8 syndrome[0x20]; 8196 8197 u8 reserved_at_40[0x40]; 8198 }; 8199 8200 struct mlx5_ifc_set_wol_rol_in_bits { 8201 u8 opcode[0x10]; 8202 u8 reserved_at_10[0x10]; 8203 8204 u8 reserved_at_20[0x10]; 8205 u8 op_mod[0x10]; 8206 8207 u8 rol_mode_valid[0x1]; 8208 u8 wol_mode_valid[0x1]; 8209 u8 reserved_at_42[0xe]; 8210 u8 rol_mode[0x8]; 8211 u8 wol_mode[0x8]; 8212 8213 u8 reserved_at_60[0x20]; 8214 }; 8215 8216 enum { 8217 MLX5_INITIAL_SEG_NIC_INTERFACE_FULL_DRIVER = 0x0, 8218 MLX5_INITIAL_SEG_NIC_INTERFACE_DISABLED = 0x1, 8219 MLX5_INITIAL_SEG_NIC_INTERFACE_NO_DRAM_NIC = 0x2, 8220 }; 8221 8222 enum { 8223 MLX5_INITIAL_SEG_NIC_INTERFACE_SUPPORTED_FULL_DRIVER = 0x0, 8224 MLX5_INITIAL_SEG_NIC_INTERFACE_SUPPORTED_DISABLED = 0x1, 8225 MLX5_INITIAL_SEG_NIC_INTERFACE_SUPPORTED_NO_DRAM_NIC = 0x2, 8226 }; 8227 8228 enum { 8229 MLX5_INITIAL_SEG_HEALTH_SYNDROME_FW_INTERNAL_ERR = 0x1, 8230 MLX5_INITIAL_SEG_HEALTH_SYNDROME_DEAD_IRISC = 0x7, 8231 MLX5_INITIAL_SEG_HEALTH_SYNDROME_HW_FATAL_ERR = 0x8, 8232 MLX5_INITIAL_SEG_HEALTH_SYNDROME_FW_CRC_ERR = 0x9, 8233 MLX5_INITIAL_SEG_HEALTH_SYNDROME_ICM_FETCH_PCI_ERR = 0xa, 8234 MLX5_INITIAL_SEG_HEALTH_SYNDROME_ICM_PAGE_ERR = 0xb, 8235 MLX5_INITIAL_SEG_HEALTH_SYNDROME_ASYNCHRONOUS_EQ_BUF_OVERRUN = 0xc, 8236 MLX5_INITIAL_SEG_HEALTH_SYNDROME_EQ_IN_ERR = 0xd, 8237 MLX5_INITIAL_SEG_HEALTH_SYNDROME_EQ_INV = 0xe, 8238 MLX5_INITIAL_SEG_HEALTH_SYNDROME_FFSER_ERR = 0xf, 8239 MLX5_INITIAL_SEG_HEALTH_SYNDROME_HIGH_TEMP_ERR = 0x10, 8240 }; 8241 8242 struct mlx5_ifc_initial_seg_bits { 8243 u8 fw_rev_minor[0x10]; 8244 u8 fw_rev_major[0x10]; 8245 8246 u8 cmd_interface_rev[0x10]; 8247 u8 fw_rev_subminor[0x10]; 8248 8249 u8 reserved_at_40[0x40]; 8250 8251 u8 cmdq_phy_addr_63_32[0x20]; 8252 8253 u8 cmdq_phy_addr_31_12[0x14]; 8254 u8 reserved_at_b4[0x2]; 8255 u8 nic_interface[0x2]; 8256 u8 log_cmdq_size[0x4]; 8257 u8 log_cmdq_stride[0x4]; 8258 8259 u8 command_doorbell_vector[0x20]; 8260 8261 u8 reserved_at_e0[0xf00]; 8262 8263 u8 initializing[0x1]; 8264 u8 reserved_at_fe1[0x4]; 8265 u8 nic_interface_supported[0x3]; 8266 u8 reserved_at_fe8[0x18]; 8267 8268 struct mlx5_ifc_health_buffer_bits health_buffer; 8269 8270 u8 no_dram_nic_offset[0x20]; 8271 8272 u8 reserved_at_1220[0x6e40]; 8273 8274 u8 reserved_at_8060[0x1f]; 8275 u8 clear_int[0x1]; 8276 8277 u8 health_syndrome[0x8]; 8278 u8 health_counter[0x18]; 8279 8280 u8 reserved_at_80a0[0x17fc0]; 8281 }; 8282 8283 struct mlx5_ifc_mtpps_reg_bits { 8284 u8 reserved_at_0[0xc]; 8285 u8 cap_number_of_pps_pins[0x4]; 8286 u8 reserved_at_10[0x4]; 8287 u8 cap_max_num_of_pps_in_pins[0x4]; 8288 u8 reserved_at_18[0x4]; 8289 u8 cap_max_num_of_pps_out_pins[0x4]; 8290 8291 u8 reserved_at_20[0x24]; 8292 u8 cap_pin_3_mode[0x4]; 8293 u8 reserved_at_48[0x4]; 8294 u8 cap_pin_2_mode[0x4]; 8295 u8 reserved_at_50[0x4]; 8296 u8 cap_pin_1_mode[0x4]; 8297 u8 reserved_at_58[0x4]; 8298 u8 cap_pin_0_mode[0x4]; 8299 8300 u8 reserved_at_60[0x4]; 8301 u8 cap_pin_7_mode[0x4]; 8302 u8 reserved_at_68[0x4]; 8303 u8 cap_pin_6_mode[0x4]; 8304 u8 reserved_at_70[0x4]; 8305 u8 cap_pin_5_mode[0x4]; 8306 u8 reserved_at_78[0x4]; 8307 u8 cap_pin_4_mode[0x4]; 8308 8309 u8 field_select[0x20]; 8310 u8 reserved_at_a0[0x60]; 8311 8312 u8 enable[0x1]; 8313 u8 reserved_at_101[0xb]; 8314 u8 pattern[0x4]; 8315 u8 reserved_at_110[0x4]; 8316 u8 pin_mode[0x4]; 8317 u8 pin[0x8]; 8318 8319 u8 reserved_at_120[0x20]; 8320 8321 u8 time_stamp[0x40]; 8322 8323 u8 out_pulse_duration[0x10]; 8324 u8 out_periodic_adjustment[0x10]; 8325 u8 enhanced_out_periodic_adjustment[0x20]; 8326 8327 u8 reserved_at_1c0[0x20]; 8328 }; 8329 8330 struct mlx5_ifc_mtppse_reg_bits { 8331 u8 reserved_at_0[0x18]; 8332 u8 pin[0x8]; 8333 u8 event_arm[0x1]; 8334 u8 reserved_at_21[0x1b]; 8335 u8 event_generation_mode[0x4]; 8336 u8 reserved_at_40[0x40]; 8337 }; 8338 8339 struct mlx5_ifc_mcqi_cap_bits { 8340 u8 supported_info_bitmask[0x20]; 8341 8342 u8 component_size[0x20]; 8343 8344 u8 max_component_size[0x20]; 8345 8346 u8 log_mcda_word_size[0x4]; 8347 u8 reserved_at_64[0xc]; 8348 u8 mcda_max_write_size[0x10]; 8349 8350 u8 rd_en[0x1]; 8351 u8 reserved_at_81[0x1]; 8352 u8 match_chip_id[0x1]; 8353 u8 match_psid[0x1]; 8354 u8 check_user_timestamp[0x1]; 8355 u8 match_base_guid_mac[0x1]; 8356 u8 reserved_at_86[0x1a]; 8357 }; 8358 8359 struct mlx5_ifc_mcqi_reg_bits { 8360 u8 read_pending_component[0x1]; 8361 u8 reserved_at_1[0xf]; 8362 u8 component_index[0x10]; 8363 8364 u8 reserved_at_20[0x20]; 8365 8366 u8 reserved_at_40[0x1b]; 8367 u8 info_type[0x5]; 8368 8369 u8 info_size[0x20]; 8370 8371 u8 offset[0x20]; 8372 8373 u8 reserved_at_a0[0x10]; 8374 u8 data_size[0x10]; 8375 8376 u8 data[0][0x20]; 8377 }; 8378 8379 struct mlx5_ifc_mcc_reg_bits { 8380 u8 reserved_at_0[0x4]; 8381 u8 time_elapsed_since_last_cmd[0xc]; 8382 u8 reserved_at_10[0x8]; 8383 u8 instruction[0x8]; 8384 8385 u8 reserved_at_20[0x10]; 8386 u8 component_index[0x10]; 8387 8388 u8 reserved_at_40[0x8]; 8389 u8 update_handle[0x18]; 8390 8391 u8 handle_owner_type[0x4]; 8392 u8 handle_owner_host_id[0x4]; 8393 u8 reserved_at_68[0x1]; 8394 u8 control_progress[0x7]; 8395 u8 error_code[0x8]; 8396 u8 reserved_at_78[0x4]; 8397 u8 control_state[0x4]; 8398 8399 u8 component_size[0x20]; 8400 8401 u8 reserved_at_a0[0x60]; 8402 }; 8403 8404 struct mlx5_ifc_mcda_reg_bits { 8405 u8 reserved_at_0[0x8]; 8406 u8 update_handle[0x18]; 8407 8408 u8 offset[0x20]; 8409 8410 u8 reserved_at_40[0x10]; 8411 u8 size[0x10]; 8412 8413 u8 reserved_at_60[0x20]; 8414 8415 u8 data[0][0x20]; 8416 }; 8417 8418 union mlx5_ifc_ports_control_registers_document_bits { 8419 struct mlx5_ifc_bufferx_reg_bits bufferx_reg; 8420 struct mlx5_ifc_eth_2819_cntrs_grp_data_layout_bits eth_2819_cntrs_grp_data_layout; 8421 struct mlx5_ifc_eth_2863_cntrs_grp_data_layout_bits eth_2863_cntrs_grp_data_layout; 8422 struct mlx5_ifc_eth_3635_cntrs_grp_data_layout_bits eth_3635_cntrs_grp_data_layout; 8423 struct mlx5_ifc_eth_802_3_cntrs_grp_data_layout_bits eth_802_3_cntrs_grp_data_layout; 8424 struct mlx5_ifc_eth_extended_cntrs_grp_data_layout_bits eth_extended_cntrs_grp_data_layout; 8425 struct mlx5_ifc_eth_per_prio_grp_data_layout_bits eth_per_prio_grp_data_layout; 8426 struct mlx5_ifc_eth_per_traffic_grp_data_layout_bits eth_per_traffic_grp_data_layout; 8427 struct mlx5_ifc_lane_2_module_mapping_bits lane_2_module_mapping; 8428 struct mlx5_ifc_pamp_reg_bits pamp_reg; 8429 struct mlx5_ifc_paos_reg_bits paos_reg; 8430 struct mlx5_ifc_pcap_reg_bits pcap_reg; 8431 struct mlx5_ifc_peir_reg_bits peir_reg; 8432 struct mlx5_ifc_pelc_reg_bits pelc_reg; 8433 struct mlx5_ifc_pfcc_reg_bits pfcc_reg; 8434 struct mlx5_ifc_ib_port_cntrs_grp_data_layout_bits ib_port_cntrs_grp_data_layout; 8435 struct mlx5_ifc_phys_layer_cntrs_bits phys_layer_cntrs; 8436 struct mlx5_ifc_pifr_reg_bits pifr_reg; 8437 struct mlx5_ifc_pipg_reg_bits pipg_reg; 8438 struct mlx5_ifc_plbf_reg_bits plbf_reg; 8439 struct mlx5_ifc_plib_reg_bits plib_reg; 8440 struct mlx5_ifc_plpc_reg_bits plpc_reg; 8441 struct mlx5_ifc_pmaos_reg_bits pmaos_reg; 8442 struct mlx5_ifc_pmlp_reg_bits pmlp_reg; 8443 struct mlx5_ifc_pmlpn_reg_bits pmlpn_reg; 8444 struct mlx5_ifc_pmpc_reg_bits pmpc_reg; 8445 struct mlx5_ifc_pmpe_reg_bits pmpe_reg; 8446 struct mlx5_ifc_pmpr_reg_bits pmpr_reg; 8447 struct mlx5_ifc_pmtu_reg_bits pmtu_reg; 8448 struct mlx5_ifc_ppad_reg_bits ppad_reg; 8449 struct mlx5_ifc_ppcnt_reg_bits ppcnt_reg; 8450 struct mlx5_ifc_mpcnt_reg_bits mpcnt_reg; 8451 struct mlx5_ifc_pplm_reg_bits pplm_reg; 8452 struct mlx5_ifc_pplr_reg_bits pplr_reg; 8453 struct mlx5_ifc_ppsc_reg_bits ppsc_reg; 8454 struct mlx5_ifc_pqdr_reg_bits pqdr_reg; 8455 struct mlx5_ifc_pspa_reg_bits pspa_reg; 8456 struct mlx5_ifc_ptas_reg_bits ptas_reg; 8457 struct mlx5_ifc_ptys_reg_bits ptys_reg; 8458 struct mlx5_ifc_mlcr_reg_bits mlcr_reg; 8459 struct mlx5_ifc_pude_reg_bits pude_reg; 8460 struct mlx5_ifc_pvlc_reg_bits pvlc_reg; 8461 struct mlx5_ifc_slrg_reg_bits slrg_reg; 8462 struct mlx5_ifc_sltp_reg_bits sltp_reg; 8463 struct mlx5_ifc_mtpps_reg_bits mtpps_reg; 8464 struct mlx5_ifc_mtppse_reg_bits mtppse_reg; 8465 struct mlx5_ifc_fpga_access_reg_bits fpga_access_reg; 8466 struct mlx5_ifc_fpga_ctrl_bits fpga_ctrl_bits; 8467 struct mlx5_ifc_fpga_cap_bits fpga_cap_bits; 8468 struct mlx5_ifc_mcqi_reg_bits mcqi_reg; 8469 struct mlx5_ifc_mcc_reg_bits mcc_reg; 8470 struct mlx5_ifc_mcda_reg_bits mcda_reg; 8471 u8 reserved_at_0[0x60e0]; 8472 }; 8473 8474 union mlx5_ifc_debug_enhancements_document_bits { 8475 struct mlx5_ifc_health_buffer_bits health_buffer; 8476 u8 reserved_at_0[0x200]; 8477 }; 8478 8479 union mlx5_ifc_uplink_pci_interface_document_bits { 8480 struct mlx5_ifc_initial_seg_bits initial_seg; 8481 u8 reserved_at_0[0x20060]; 8482 }; 8483 8484 struct mlx5_ifc_set_flow_table_root_out_bits { 8485 u8 status[0x8]; 8486 u8 reserved_at_8[0x18]; 8487 8488 u8 syndrome[0x20]; 8489 8490 u8 reserved_at_40[0x40]; 8491 }; 8492 8493 struct mlx5_ifc_set_flow_table_root_in_bits { 8494 u8 opcode[0x10]; 8495 u8 reserved_at_10[0x10]; 8496 8497 u8 reserved_at_20[0x10]; 8498 u8 op_mod[0x10]; 8499 8500 u8 other_vport[0x1]; 8501 u8 reserved_at_41[0xf]; 8502 u8 vport_number[0x10]; 8503 8504 u8 reserved_at_60[0x20]; 8505 8506 u8 table_type[0x8]; 8507 u8 reserved_at_88[0x18]; 8508 8509 u8 reserved_at_a0[0x8]; 8510 u8 table_id[0x18]; 8511 8512 u8 reserved_at_c0[0x8]; 8513 u8 underlay_qpn[0x18]; 8514 u8 reserved_at_e0[0x120]; 8515 }; 8516 8517 enum { 8518 MLX5_MODIFY_FLOW_TABLE_MISS_TABLE_ID = (1UL << 0), 8519 MLX5_MODIFY_FLOW_TABLE_LAG_NEXT_TABLE_ID = (1UL << 15), 8520 }; 8521 8522 struct mlx5_ifc_modify_flow_table_out_bits { 8523 u8 status[0x8]; 8524 u8 reserved_at_8[0x18]; 8525 8526 u8 syndrome[0x20]; 8527 8528 u8 reserved_at_40[0x40]; 8529 }; 8530 8531 struct mlx5_ifc_modify_flow_table_in_bits { 8532 u8 opcode[0x10]; 8533 u8 reserved_at_10[0x10]; 8534 8535 u8 reserved_at_20[0x10]; 8536 u8 op_mod[0x10]; 8537 8538 u8 other_vport[0x1]; 8539 u8 reserved_at_41[0xf]; 8540 u8 vport_number[0x10]; 8541 8542 u8 reserved_at_60[0x10]; 8543 u8 modify_field_select[0x10]; 8544 8545 u8 table_type[0x8]; 8546 u8 reserved_at_88[0x18]; 8547 8548 u8 reserved_at_a0[0x8]; 8549 u8 table_id[0x18]; 8550 8551 struct mlx5_ifc_flow_table_context_bits flow_table_context; 8552 }; 8553 8554 struct mlx5_ifc_ets_tcn_config_reg_bits { 8555 u8 g[0x1]; 8556 u8 b[0x1]; 8557 u8 r[0x1]; 8558 u8 reserved_at_3[0x9]; 8559 u8 group[0x4]; 8560 u8 reserved_at_10[0x9]; 8561 u8 bw_allocation[0x7]; 8562 8563 u8 reserved_at_20[0xc]; 8564 u8 max_bw_units[0x4]; 8565 u8 reserved_at_30[0x8]; 8566 u8 max_bw_value[0x8]; 8567 }; 8568 8569 struct mlx5_ifc_ets_global_config_reg_bits { 8570 u8 reserved_at_0[0x2]; 8571 u8 r[0x1]; 8572 u8 reserved_at_3[0x1d]; 8573 8574 u8 reserved_at_20[0xc]; 8575 u8 max_bw_units[0x4]; 8576 u8 reserved_at_30[0x8]; 8577 u8 max_bw_value[0x8]; 8578 }; 8579 8580 struct mlx5_ifc_qetc_reg_bits { 8581 u8 reserved_at_0[0x8]; 8582 u8 port_number[0x8]; 8583 u8 reserved_at_10[0x30]; 8584 8585 struct mlx5_ifc_ets_tcn_config_reg_bits tc_configuration[0x8]; 8586 struct mlx5_ifc_ets_global_config_reg_bits global_configuration; 8587 }; 8588 8589 struct mlx5_ifc_qpdpm_dscp_reg_bits { 8590 u8 e[0x1]; 8591 u8 reserved_at_01[0x0b]; 8592 u8 prio[0x04]; 8593 }; 8594 8595 struct mlx5_ifc_qpdpm_reg_bits { 8596 u8 reserved_at_0[0x8]; 8597 u8 local_port[0x8]; 8598 u8 reserved_at_10[0x10]; 8599 struct mlx5_ifc_qpdpm_dscp_reg_bits dscp[64]; 8600 }; 8601 8602 struct mlx5_ifc_qpts_reg_bits { 8603 u8 reserved_at_0[0x8]; 8604 u8 local_port[0x8]; 8605 u8 reserved_at_10[0x2d]; 8606 u8 trust_state[0x3]; 8607 }; 8608 8609 struct mlx5_ifc_qtct_reg_bits { 8610 u8 reserved_at_0[0x8]; 8611 u8 port_number[0x8]; 8612 u8 reserved_at_10[0xd]; 8613 u8 prio[0x3]; 8614 8615 u8 reserved_at_20[0x1d]; 8616 u8 tclass[0x3]; 8617 }; 8618 8619 struct mlx5_ifc_mcia_reg_bits { 8620 u8 l[0x1]; 8621 u8 reserved_at_1[0x7]; 8622 u8 module[0x8]; 8623 u8 reserved_at_10[0x8]; 8624 u8 status[0x8]; 8625 8626 u8 i2c_device_address[0x8]; 8627 u8 page_number[0x8]; 8628 u8 device_address[0x10]; 8629 8630 u8 reserved_at_40[0x10]; 8631 u8 size[0x10]; 8632 8633 u8 reserved_at_60[0x20]; 8634 8635 u8 dword_0[0x20]; 8636 u8 dword_1[0x20]; 8637 u8 dword_2[0x20]; 8638 u8 dword_3[0x20]; 8639 u8 dword_4[0x20]; 8640 u8 dword_5[0x20]; 8641 u8 dword_6[0x20]; 8642 u8 dword_7[0x20]; 8643 u8 dword_8[0x20]; 8644 u8 dword_9[0x20]; 8645 u8 dword_10[0x20]; 8646 u8 dword_11[0x20]; 8647 }; 8648 8649 struct mlx5_ifc_dcbx_param_bits { 8650 u8 dcbx_cee_cap[0x1]; 8651 u8 dcbx_ieee_cap[0x1]; 8652 u8 dcbx_standby_cap[0x1]; 8653 u8 reserved_at_0[0x5]; 8654 u8 port_number[0x8]; 8655 u8 reserved_at_10[0xa]; 8656 u8 max_application_table_size[6]; 8657 u8 reserved_at_20[0x15]; 8658 u8 version_oper[0x3]; 8659 u8 reserved_at_38[5]; 8660 u8 version_admin[0x3]; 8661 u8 willing_admin[0x1]; 8662 u8 reserved_at_41[0x3]; 8663 u8 pfc_cap_oper[0x4]; 8664 u8 reserved_at_48[0x4]; 8665 u8 pfc_cap_admin[0x4]; 8666 u8 reserved_at_50[0x4]; 8667 u8 num_of_tc_oper[0x4]; 8668 u8 reserved_at_58[0x4]; 8669 u8 num_of_tc_admin[0x4]; 8670 u8 remote_willing[0x1]; 8671 u8 reserved_at_61[3]; 8672 u8 remote_pfc_cap[4]; 8673 u8 reserved_at_68[0x14]; 8674 u8 remote_num_of_tc[0x4]; 8675 u8 reserved_at_80[0x18]; 8676 u8 error[0x8]; 8677 u8 reserved_at_a0[0x160]; 8678 }; 8679 8680 struct mlx5_ifc_lagc_bits { 8681 u8 reserved_at_0[0x1d]; 8682 u8 lag_state[0x3]; 8683 8684 u8 reserved_at_20[0x14]; 8685 u8 tx_remap_affinity_2[0x4]; 8686 u8 reserved_at_38[0x4]; 8687 u8 tx_remap_affinity_1[0x4]; 8688 }; 8689 8690 struct mlx5_ifc_create_lag_out_bits { 8691 u8 status[0x8]; 8692 u8 reserved_at_8[0x18]; 8693 8694 u8 syndrome[0x20]; 8695 8696 u8 reserved_at_40[0x40]; 8697 }; 8698 8699 struct mlx5_ifc_create_lag_in_bits { 8700 u8 opcode[0x10]; 8701 u8 reserved_at_10[0x10]; 8702 8703 u8 reserved_at_20[0x10]; 8704 u8 op_mod[0x10]; 8705 8706 struct mlx5_ifc_lagc_bits ctx; 8707 }; 8708 8709 struct mlx5_ifc_modify_lag_out_bits { 8710 u8 status[0x8]; 8711 u8 reserved_at_8[0x18]; 8712 8713 u8 syndrome[0x20]; 8714 8715 u8 reserved_at_40[0x40]; 8716 }; 8717 8718 struct mlx5_ifc_modify_lag_in_bits { 8719 u8 opcode[0x10]; 8720 u8 reserved_at_10[0x10]; 8721 8722 u8 reserved_at_20[0x10]; 8723 u8 op_mod[0x10]; 8724 8725 u8 reserved_at_40[0x20]; 8726 u8 field_select[0x20]; 8727 8728 struct mlx5_ifc_lagc_bits ctx; 8729 }; 8730 8731 struct mlx5_ifc_query_lag_out_bits { 8732 u8 status[0x8]; 8733 u8 reserved_at_8[0x18]; 8734 8735 u8 syndrome[0x20]; 8736 8737 u8 reserved_at_40[0x40]; 8738 8739 struct mlx5_ifc_lagc_bits ctx; 8740 }; 8741 8742 struct mlx5_ifc_query_lag_in_bits { 8743 u8 opcode[0x10]; 8744 u8 reserved_at_10[0x10]; 8745 8746 u8 reserved_at_20[0x10]; 8747 u8 op_mod[0x10]; 8748 8749 u8 reserved_at_40[0x40]; 8750 }; 8751 8752 struct mlx5_ifc_destroy_lag_out_bits { 8753 u8 status[0x8]; 8754 u8 reserved_at_8[0x18]; 8755 8756 u8 syndrome[0x20]; 8757 8758 u8 reserved_at_40[0x40]; 8759 }; 8760 8761 struct mlx5_ifc_destroy_lag_in_bits { 8762 u8 opcode[0x10]; 8763 u8 reserved_at_10[0x10]; 8764 8765 u8 reserved_at_20[0x10]; 8766 u8 op_mod[0x10]; 8767 8768 u8 reserved_at_40[0x40]; 8769 }; 8770 8771 struct mlx5_ifc_create_vport_lag_out_bits { 8772 u8 status[0x8]; 8773 u8 reserved_at_8[0x18]; 8774 8775 u8 syndrome[0x20]; 8776 8777 u8 reserved_at_40[0x40]; 8778 }; 8779 8780 struct mlx5_ifc_create_vport_lag_in_bits { 8781 u8 opcode[0x10]; 8782 u8 reserved_at_10[0x10]; 8783 8784 u8 reserved_at_20[0x10]; 8785 u8 op_mod[0x10]; 8786 8787 u8 reserved_at_40[0x40]; 8788 }; 8789 8790 struct mlx5_ifc_destroy_vport_lag_out_bits { 8791 u8 status[0x8]; 8792 u8 reserved_at_8[0x18]; 8793 8794 u8 syndrome[0x20]; 8795 8796 u8 reserved_at_40[0x40]; 8797 }; 8798 8799 struct mlx5_ifc_destroy_vport_lag_in_bits { 8800 u8 opcode[0x10]; 8801 u8 reserved_at_10[0x10]; 8802 8803 u8 reserved_at_20[0x10]; 8804 u8 op_mod[0x10]; 8805 8806 u8 reserved_at_40[0x40]; 8807 }; 8808 8809 #endif /* MLX5_IFC_H */ 8810