1 /* 2 * Copyright (c) 2013-2015, Mellanox Technologies, Ltd. All rights reserved. 3 * 4 * This software is available to you under a choice of one of two 5 * licenses. You may choose to be licensed under the terms of the GNU 6 * General Public License (GPL) Version 2, available from the file 7 * COPYING in the main directory of this source tree, or the 8 * OpenIB.org BSD license below: 9 * 10 * Redistribution and use in source and binary forms, with or 11 * without modification, are permitted provided that the following 12 * conditions are met: 13 * 14 * - Redistributions of source code must retain the above 15 * copyright notice, this list of conditions and the following 16 * disclaimer. 17 * 18 * - Redistributions in binary form must reproduce the above 19 * copyright notice, this list of conditions and the following 20 * disclaimer in the documentation and/or other materials 21 * provided with the distribution. 22 * 23 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, 24 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF 25 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND 26 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS 27 * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN 28 * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN 29 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE 30 * SOFTWARE. 31 */ 32 #ifndef MLX5_IFC_H 33 #define MLX5_IFC_H 34 35 enum { 36 MLX5_EVENT_TYPE_CODING_COMPLETION_EVENTS = 0x0, 37 MLX5_EVENT_TYPE_CODING_PATH_MIGRATED_SUCCEEDED = 0x1, 38 MLX5_EVENT_TYPE_CODING_COMMUNICATION_ESTABLISHED = 0x2, 39 MLX5_EVENT_TYPE_CODING_SEND_QUEUE_DRAINED = 0x3, 40 MLX5_EVENT_TYPE_CODING_LAST_WQE_REACHED = 0x13, 41 MLX5_EVENT_TYPE_CODING_SRQ_LIMIT = 0x14, 42 MLX5_EVENT_TYPE_CODING_DCT_ALL_CONNECTIONS_CLOSED = 0x1c, 43 MLX5_EVENT_TYPE_CODING_DCT_ACCESS_KEY_VIOLATION = 0x1d, 44 MLX5_EVENT_TYPE_CODING_CQ_ERROR = 0x4, 45 MLX5_EVENT_TYPE_CODING_LOCAL_WQ_CATASTROPHIC_ERROR = 0x5, 46 MLX5_EVENT_TYPE_CODING_PATH_MIGRATION_FAILED = 0x7, 47 MLX5_EVENT_TYPE_CODING_PAGE_FAULT_EVENT = 0xc, 48 MLX5_EVENT_TYPE_CODING_INVALID_REQUEST_LOCAL_WQ_ERROR = 0x10, 49 MLX5_EVENT_TYPE_CODING_LOCAL_ACCESS_VIOLATION_WQ_ERROR = 0x11, 50 MLX5_EVENT_TYPE_CODING_LOCAL_SRQ_CATASTROPHIC_ERROR = 0x12, 51 MLX5_EVENT_TYPE_CODING_INTERNAL_ERROR = 0x8, 52 MLX5_EVENT_TYPE_CODING_PORT_STATE_CHANGE = 0x9, 53 MLX5_EVENT_TYPE_CODING_GPIO_EVENT = 0x15, 54 MLX5_EVENT_TYPE_CODING_REMOTE_CONFIGURATION_PROTOCOL_EVENT = 0x19, 55 MLX5_EVENT_TYPE_CODING_DOORBELL_BLUEFLAME_CONGESTION_EVENT = 0x1a, 56 MLX5_EVENT_TYPE_CODING_STALL_VL_EVENT = 0x1b, 57 MLX5_EVENT_TYPE_CODING_DROPPED_PACKET_LOGGED_EVENT = 0x1f, 58 MLX5_EVENT_TYPE_CODING_COMMAND_INTERFACE_COMPLETION = 0xa, 59 MLX5_EVENT_TYPE_CODING_PAGE_REQUEST = 0xb 60 }; 61 62 enum { 63 MLX5_MODIFY_TIR_BITMASK_LRO = 0x0, 64 MLX5_MODIFY_TIR_BITMASK_INDIRECT_TABLE = 0x1, 65 MLX5_MODIFY_TIR_BITMASK_HASH = 0x2, 66 MLX5_MODIFY_TIR_BITMASK_TUNNELED_OFFLOAD_EN = 0x3 67 }; 68 69 enum { 70 MLX5_SET_HCA_CAP_OP_MOD_GENERAL_DEVICE = 0x0, 71 MLX5_SET_HCA_CAP_OP_MOD_ATOMIC = 0x3, 72 }; 73 74 enum { 75 MLX5_CMD_OP_QUERY_HCA_CAP = 0x100, 76 MLX5_CMD_OP_QUERY_ADAPTER = 0x101, 77 MLX5_CMD_OP_INIT_HCA = 0x102, 78 MLX5_CMD_OP_TEARDOWN_HCA = 0x103, 79 MLX5_CMD_OP_ENABLE_HCA = 0x104, 80 MLX5_CMD_OP_DISABLE_HCA = 0x105, 81 MLX5_CMD_OP_QUERY_PAGES = 0x107, 82 MLX5_CMD_OP_MANAGE_PAGES = 0x108, 83 MLX5_CMD_OP_SET_HCA_CAP = 0x109, 84 MLX5_CMD_OP_QUERY_ISSI = 0x10a, 85 MLX5_CMD_OP_SET_ISSI = 0x10b, 86 MLX5_CMD_OP_CREATE_MKEY = 0x200, 87 MLX5_CMD_OP_QUERY_MKEY = 0x201, 88 MLX5_CMD_OP_DESTROY_MKEY = 0x202, 89 MLX5_CMD_OP_QUERY_SPECIAL_CONTEXTS = 0x203, 90 MLX5_CMD_OP_PAGE_FAULT_RESUME = 0x204, 91 MLX5_CMD_OP_CREATE_EQ = 0x301, 92 MLX5_CMD_OP_DESTROY_EQ = 0x302, 93 MLX5_CMD_OP_QUERY_EQ = 0x303, 94 MLX5_CMD_OP_GEN_EQE = 0x304, 95 MLX5_CMD_OP_CREATE_CQ = 0x400, 96 MLX5_CMD_OP_DESTROY_CQ = 0x401, 97 MLX5_CMD_OP_QUERY_CQ = 0x402, 98 MLX5_CMD_OP_MODIFY_CQ = 0x403, 99 MLX5_CMD_OP_CREATE_QP = 0x500, 100 MLX5_CMD_OP_DESTROY_QP = 0x501, 101 MLX5_CMD_OP_RST2INIT_QP = 0x502, 102 MLX5_CMD_OP_INIT2RTR_QP = 0x503, 103 MLX5_CMD_OP_RTR2RTS_QP = 0x504, 104 MLX5_CMD_OP_RTS2RTS_QP = 0x505, 105 MLX5_CMD_OP_SQERR2RTS_QP = 0x506, 106 MLX5_CMD_OP_2ERR_QP = 0x507, 107 MLX5_CMD_OP_2RST_QP = 0x50a, 108 MLX5_CMD_OP_QUERY_QP = 0x50b, 109 MLX5_CMD_OP_SQD_RTS_QP = 0x50c, 110 MLX5_CMD_OP_INIT2INIT_QP = 0x50e, 111 MLX5_CMD_OP_CREATE_PSV = 0x600, 112 MLX5_CMD_OP_DESTROY_PSV = 0x601, 113 MLX5_CMD_OP_CREATE_SRQ = 0x700, 114 MLX5_CMD_OP_DESTROY_SRQ = 0x701, 115 MLX5_CMD_OP_QUERY_SRQ = 0x702, 116 MLX5_CMD_OP_ARM_RQ = 0x703, 117 MLX5_CMD_OP_CREATE_XRC_SRQ = 0x705, 118 MLX5_CMD_OP_DESTROY_XRC_SRQ = 0x706, 119 MLX5_CMD_OP_QUERY_XRC_SRQ = 0x707, 120 MLX5_CMD_OP_ARM_XRC_SRQ = 0x708, 121 MLX5_CMD_OP_CREATE_DCT = 0x710, 122 MLX5_CMD_OP_DESTROY_DCT = 0x711, 123 MLX5_CMD_OP_DRAIN_DCT = 0x712, 124 MLX5_CMD_OP_QUERY_DCT = 0x713, 125 MLX5_CMD_OP_ARM_DCT_FOR_KEY_VIOLATION = 0x714, 126 MLX5_CMD_OP_QUERY_VPORT_STATE = 0x750, 127 MLX5_CMD_OP_MODIFY_VPORT_STATE = 0x751, 128 MLX5_CMD_OP_QUERY_ESW_VPORT_CONTEXT = 0x752, 129 MLX5_CMD_OP_MODIFY_ESW_VPORT_CONTEXT = 0x753, 130 MLX5_CMD_OP_QUERY_NIC_VPORT_CONTEXT = 0x754, 131 MLX5_CMD_OP_MODIFY_NIC_VPORT_CONTEXT = 0x755, 132 MLX5_CMD_OP_QUERY_ROCE_ADDRESS = 0x760, 133 MLX5_CMD_OP_SET_ROCE_ADDRESS = 0x761, 134 MLX5_CMD_OP_QUERY_HCA_VPORT_CONTEXT = 0x762, 135 MLX5_CMD_OP_MODIFY_HCA_VPORT_CONTEXT = 0x763, 136 MLX5_CMD_OP_QUERY_HCA_VPORT_GID = 0x764, 137 MLX5_CMD_OP_QUERY_HCA_VPORT_PKEY = 0x765, 138 MLX5_CMD_OP_QUERY_VPORT_COUNTER = 0x770, 139 MLX5_CMD_OP_ALLOC_Q_COUNTER = 0x771, 140 MLX5_CMD_OP_DEALLOC_Q_COUNTER = 0x772, 141 MLX5_CMD_OP_QUERY_Q_COUNTER = 0x773, 142 MLX5_CMD_OP_ALLOC_PD = 0x800, 143 MLX5_CMD_OP_DEALLOC_PD = 0x801, 144 MLX5_CMD_OP_ALLOC_UAR = 0x802, 145 MLX5_CMD_OP_DEALLOC_UAR = 0x803, 146 MLX5_CMD_OP_CONFIG_INT_MODERATION = 0x804, 147 MLX5_CMD_OP_ACCESS_REG = 0x805, 148 MLX5_CMD_OP_ATTACH_TO_MCG = 0x806, 149 MLX5_CMD_OP_DETTACH_FROM_MCG = 0x807, 150 MLX5_CMD_OP_GET_DROPPED_PACKET_LOG = 0x80a, 151 MLX5_CMD_OP_MAD_IFC = 0x50d, 152 MLX5_CMD_OP_QUERY_MAD_DEMUX = 0x80b, 153 MLX5_CMD_OP_SET_MAD_DEMUX = 0x80c, 154 MLX5_CMD_OP_NOP = 0x80d, 155 MLX5_CMD_OP_ALLOC_XRCD = 0x80e, 156 MLX5_CMD_OP_DEALLOC_XRCD = 0x80f, 157 MLX5_CMD_OP_ALLOC_TRANSPORT_DOMAIN = 0x816, 158 MLX5_CMD_OP_DEALLOC_TRANSPORT_DOMAIN = 0x817, 159 MLX5_CMD_OP_QUERY_CONG_STATUS = 0x822, 160 MLX5_CMD_OP_MODIFY_CONG_STATUS = 0x823, 161 MLX5_CMD_OP_QUERY_CONG_PARAMS = 0x824, 162 MLX5_CMD_OP_MODIFY_CONG_PARAMS = 0x825, 163 MLX5_CMD_OP_QUERY_CONG_STATISTICS = 0x826, 164 MLX5_CMD_OP_ADD_VXLAN_UDP_DPORT = 0x827, 165 MLX5_CMD_OP_DELETE_VXLAN_UDP_DPORT = 0x828, 166 MLX5_CMD_OP_SET_L2_TABLE_ENTRY = 0x829, 167 MLX5_CMD_OP_QUERY_L2_TABLE_ENTRY = 0x82a, 168 MLX5_CMD_OP_DELETE_L2_TABLE_ENTRY = 0x82b, 169 MLX5_CMD_OP_SET_WOL_ROL = 0x830, 170 MLX5_CMD_OP_QUERY_WOL_ROL = 0x831, 171 MLX5_CMD_OP_CREATE_TIR = 0x900, 172 MLX5_CMD_OP_MODIFY_TIR = 0x901, 173 MLX5_CMD_OP_DESTROY_TIR = 0x902, 174 MLX5_CMD_OP_QUERY_TIR = 0x903, 175 MLX5_CMD_OP_CREATE_SQ = 0x904, 176 MLX5_CMD_OP_MODIFY_SQ = 0x905, 177 MLX5_CMD_OP_DESTROY_SQ = 0x906, 178 MLX5_CMD_OP_QUERY_SQ = 0x907, 179 MLX5_CMD_OP_CREATE_RQ = 0x908, 180 MLX5_CMD_OP_MODIFY_RQ = 0x909, 181 MLX5_CMD_OP_DESTROY_RQ = 0x90a, 182 MLX5_CMD_OP_QUERY_RQ = 0x90b, 183 MLX5_CMD_OP_CREATE_RMP = 0x90c, 184 MLX5_CMD_OP_MODIFY_RMP = 0x90d, 185 MLX5_CMD_OP_DESTROY_RMP = 0x90e, 186 MLX5_CMD_OP_QUERY_RMP = 0x90f, 187 MLX5_CMD_OP_CREATE_TIS = 0x912, 188 MLX5_CMD_OP_MODIFY_TIS = 0x913, 189 MLX5_CMD_OP_DESTROY_TIS = 0x914, 190 MLX5_CMD_OP_QUERY_TIS = 0x915, 191 MLX5_CMD_OP_CREATE_RQT = 0x916, 192 MLX5_CMD_OP_MODIFY_RQT = 0x917, 193 MLX5_CMD_OP_DESTROY_RQT = 0x918, 194 MLX5_CMD_OP_QUERY_RQT = 0x919, 195 MLX5_CMD_OP_SET_FLOW_TABLE_ROOT = 0x92f, 196 MLX5_CMD_OP_CREATE_FLOW_TABLE = 0x930, 197 MLX5_CMD_OP_DESTROY_FLOW_TABLE = 0x931, 198 MLX5_CMD_OP_QUERY_FLOW_TABLE = 0x932, 199 MLX5_CMD_OP_CREATE_FLOW_GROUP = 0x933, 200 MLX5_CMD_OP_DESTROY_FLOW_GROUP = 0x934, 201 MLX5_CMD_OP_QUERY_FLOW_GROUP = 0x935, 202 MLX5_CMD_OP_SET_FLOW_TABLE_ENTRY = 0x936, 203 MLX5_CMD_OP_QUERY_FLOW_TABLE_ENTRY = 0x937, 204 MLX5_CMD_OP_DELETE_FLOW_TABLE_ENTRY = 0x938, 205 MLX5_CMD_OP_ALLOC_FLOW_COUNTER = 0x939, 206 MLX5_CMD_OP_DEALLOC_FLOW_COUNTER = 0x93a, 207 MLX5_CMD_OP_QUERY_FLOW_COUNTER = 0x93b, 208 MLX5_CMD_OP_MODIFY_FLOW_TABLE = 0x93c, 209 MLX5_CMD_OP_MAX 210 }; 211 212 struct mlx5_ifc_flow_table_fields_supported_bits { 213 u8 outer_dmac[0x1]; 214 u8 outer_smac[0x1]; 215 u8 outer_ether_type[0x1]; 216 u8 reserved_at_3[0x1]; 217 u8 outer_first_prio[0x1]; 218 u8 outer_first_cfi[0x1]; 219 u8 outer_first_vid[0x1]; 220 u8 reserved_at_7[0x1]; 221 u8 outer_second_prio[0x1]; 222 u8 outer_second_cfi[0x1]; 223 u8 outer_second_vid[0x1]; 224 u8 reserved_at_b[0x1]; 225 u8 outer_sip[0x1]; 226 u8 outer_dip[0x1]; 227 u8 outer_frag[0x1]; 228 u8 outer_ip_protocol[0x1]; 229 u8 outer_ip_ecn[0x1]; 230 u8 outer_ip_dscp[0x1]; 231 u8 outer_udp_sport[0x1]; 232 u8 outer_udp_dport[0x1]; 233 u8 outer_tcp_sport[0x1]; 234 u8 outer_tcp_dport[0x1]; 235 u8 outer_tcp_flags[0x1]; 236 u8 outer_gre_protocol[0x1]; 237 u8 outer_gre_key[0x1]; 238 u8 outer_vxlan_vni[0x1]; 239 u8 reserved_at_1a[0x5]; 240 u8 source_eswitch_port[0x1]; 241 242 u8 inner_dmac[0x1]; 243 u8 inner_smac[0x1]; 244 u8 inner_ether_type[0x1]; 245 u8 reserved_at_23[0x1]; 246 u8 inner_first_prio[0x1]; 247 u8 inner_first_cfi[0x1]; 248 u8 inner_first_vid[0x1]; 249 u8 reserved_at_27[0x1]; 250 u8 inner_second_prio[0x1]; 251 u8 inner_second_cfi[0x1]; 252 u8 inner_second_vid[0x1]; 253 u8 reserved_at_2b[0x1]; 254 u8 inner_sip[0x1]; 255 u8 inner_dip[0x1]; 256 u8 inner_frag[0x1]; 257 u8 inner_ip_protocol[0x1]; 258 u8 inner_ip_ecn[0x1]; 259 u8 inner_ip_dscp[0x1]; 260 u8 inner_udp_sport[0x1]; 261 u8 inner_udp_dport[0x1]; 262 u8 inner_tcp_sport[0x1]; 263 u8 inner_tcp_dport[0x1]; 264 u8 inner_tcp_flags[0x1]; 265 u8 reserved_at_37[0x9]; 266 267 u8 reserved_at_40[0x40]; 268 }; 269 270 struct mlx5_ifc_flow_table_prop_layout_bits { 271 u8 ft_support[0x1]; 272 u8 reserved_at_1[0x1]; 273 u8 flow_counter[0x1]; 274 u8 flow_modify_en[0x1]; 275 u8 modify_root[0x1]; 276 u8 identified_miss_table_mode[0x1]; 277 u8 flow_table_modify[0x1]; 278 u8 reserved_at_7[0x19]; 279 280 u8 reserved_at_20[0x2]; 281 u8 log_max_ft_size[0x6]; 282 u8 reserved_at_28[0x10]; 283 u8 max_ft_level[0x8]; 284 285 u8 reserved_at_40[0x20]; 286 287 u8 reserved_at_60[0x18]; 288 u8 log_max_ft_num[0x8]; 289 290 u8 reserved_at_80[0x18]; 291 u8 log_max_destination[0x8]; 292 293 u8 reserved_at_a0[0x18]; 294 u8 log_max_flow[0x8]; 295 296 u8 reserved_at_c0[0x40]; 297 298 struct mlx5_ifc_flow_table_fields_supported_bits ft_field_support; 299 300 struct mlx5_ifc_flow_table_fields_supported_bits ft_field_bitmask_support; 301 }; 302 303 struct mlx5_ifc_odp_per_transport_service_cap_bits { 304 u8 send[0x1]; 305 u8 receive[0x1]; 306 u8 write[0x1]; 307 u8 read[0x1]; 308 u8 reserved_at_4[0x1]; 309 u8 srq_receive[0x1]; 310 u8 reserved_at_6[0x1a]; 311 }; 312 313 struct mlx5_ifc_ipv4_layout_bits { 314 u8 reserved_at_0[0x60]; 315 316 u8 ipv4[0x20]; 317 }; 318 319 struct mlx5_ifc_ipv6_layout_bits { 320 u8 ipv6[16][0x8]; 321 }; 322 323 union mlx5_ifc_ipv6_layout_ipv4_layout_auto_bits { 324 struct mlx5_ifc_ipv6_layout_bits ipv6_layout; 325 struct mlx5_ifc_ipv4_layout_bits ipv4_layout; 326 u8 reserved_at_0[0x80]; 327 }; 328 329 struct mlx5_ifc_fte_match_set_lyr_2_4_bits { 330 u8 smac_47_16[0x20]; 331 332 u8 smac_15_0[0x10]; 333 u8 ethertype[0x10]; 334 335 u8 dmac_47_16[0x20]; 336 337 u8 dmac_15_0[0x10]; 338 u8 first_prio[0x3]; 339 u8 first_cfi[0x1]; 340 u8 first_vid[0xc]; 341 342 u8 ip_protocol[0x8]; 343 u8 ip_dscp[0x6]; 344 u8 ip_ecn[0x2]; 345 u8 vlan_tag[0x1]; 346 u8 reserved_at_91[0x1]; 347 u8 frag[0x1]; 348 u8 reserved_at_93[0x4]; 349 u8 tcp_flags[0x9]; 350 351 u8 tcp_sport[0x10]; 352 u8 tcp_dport[0x10]; 353 354 u8 reserved_at_c0[0x20]; 355 356 u8 udp_sport[0x10]; 357 u8 udp_dport[0x10]; 358 359 union mlx5_ifc_ipv6_layout_ipv4_layout_auto_bits src_ipv4_src_ipv6; 360 361 union mlx5_ifc_ipv6_layout_ipv4_layout_auto_bits dst_ipv4_dst_ipv6; 362 }; 363 364 struct mlx5_ifc_fte_match_set_misc_bits { 365 u8 reserved_at_0[0x20]; 366 367 u8 reserved_at_20[0x10]; 368 u8 source_port[0x10]; 369 370 u8 outer_second_prio[0x3]; 371 u8 outer_second_cfi[0x1]; 372 u8 outer_second_vid[0xc]; 373 u8 inner_second_prio[0x3]; 374 u8 inner_second_cfi[0x1]; 375 u8 inner_second_vid[0xc]; 376 377 u8 outer_second_vlan_tag[0x1]; 378 u8 inner_second_vlan_tag[0x1]; 379 u8 reserved_at_62[0xe]; 380 u8 gre_protocol[0x10]; 381 382 u8 gre_key_h[0x18]; 383 u8 gre_key_l[0x8]; 384 385 u8 vxlan_vni[0x18]; 386 u8 reserved_at_b8[0x8]; 387 388 u8 reserved_at_c0[0x20]; 389 390 u8 reserved_at_e0[0xc]; 391 u8 outer_ipv6_flow_label[0x14]; 392 393 u8 reserved_at_100[0xc]; 394 u8 inner_ipv6_flow_label[0x14]; 395 396 u8 reserved_at_120[0xe0]; 397 }; 398 399 struct mlx5_ifc_cmd_pas_bits { 400 u8 pa_h[0x20]; 401 402 u8 pa_l[0x14]; 403 u8 reserved_at_34[0xc]; 404 }; 405 406 struct mlx5_ifc_uint64_bits { 407 u8 hi[0x20]; 408 409 u8 lo[0x20]; 410 }; 411 412 enum { 413 MLX5_ADS_STAT_RATE_NO_LIMIT = 0x0, 414 MLX5_ADS_STAT_RATE_2_5GBPS = 0x7, 415 MLX5_ADS_STAT_RATE_10GBPS = 0x8, 416 MLX5_ADS_STAT_RATE_30GBPS = 0x9, 417 MLX5_ADS_STAT_RATE_5GBPS = 0xa, 418 MLX5_ADS_STAT_RATE_20GBPS = 0xb, 419 MLX5_ADS_STAT_RATE_40GBPS = 0xc, 420 MLX5_ADS_STAT_RATE_60GBPS = 0xd, 421 MLX5_ADS_STAT_RATE_80GBPS = 0xe, 422 MLX5_ADS_STAT_RATE_120GBPS = 0xf, 423 }; 424 425 struct mlx5_ifc_ads_bits { 426 u8 fl[0x1]; 427 u8 free_ar[0x1]; 428 u8 reserved_at_2[0xe]; 429 u8 pkey_index[0x10]; 430 431 u8 reserved_at_20[0x8]; 432 u8 grh[0x1]; 433 u8 mlid[0x7]; 434 u8 rlid[0x10]; 435 436 u8 ack_timeout[0x5]; 437 u8 reserved_at_45[0x3]; 438 u8 src_addr_index[0x8]; 439 u8 reserved_at_50[0x4]; 440 u8 stat_rate[0x4]; 441 u8 hop_limit[0x8]; 442 443 u8 reserved_at_60[0x4]; 444 u8 tclass[0x8]; 445 u8 flow_label[0x14]; 446 447 u8 rgid_rip[16][0x8]; 448 449 u8 reserved_at_100[0x4]; 450 u8 f_dscp[0x1]; 451 u8 f_ecn[0x1]; 452 u8 reserved_at_106[0x1]; 453 u8 f_eth_prio[0x1]; 454 u8 ecn[0x2]; 455 u8 dscp[0x6]; 456 u8 udp_sport[0x10]; 457 458 u8 dei_cfi[0x1]; 459 u8 eth_prio[0x3]; 460 u8 sl[0x4]; 461 u8 port[0x8]; 462 u8 rmac_47_32[0x10]; 463 464 u8 rmac_31_0[0x20]; 465 }; 466 467 struct mlx5_ifc_flow_table_nic_cap_bits { 468 u8 nic_rx_multi_path_tirs[0x1]; 469 u8 reserved_at_1[0x1ff]; 470 471 struct mlx5_ifc_flow_table_prop_layout_bits flow_table_properties_nic_receive; 472 473 u8 reserved_at_400[0x200]; 474 475 struct mlx5_ifc_flow_table_prop_layout_bits flow_table_properties_nic_receive_sniffer; 476 477 struct mlx5_ifc_flow_table_prop_layout_bits flow_table_properties_nic_transmit; 478 479 u8 reserved_at_a00[0x200]; 480 481 struct mlx5_ifc_flow_table_prop_layout_bits flow_table_properties_nic_transmit_sniffer; 482 483 u8 reserved_at_e00[0x7200]; 484 }; 485 486 struct mlx5_ifc_flow_table_eswitch_cap_bits { 487 u8 reserved_at_0[0x200]; 488 489 struct mlx5_ifc_flow_table_prop_layout_bits flow_table_properties_nic_esw_fdb; 490 491 struct mlx5_ifc_flow_table_prop_layout_bits flow_table_properties_esw_acl_ingress; 492 493 struct mlx5_ifc_flow_table_prop_layout_bits flow_table_properties_esw_acl_egress; 494 495 u8 reserved_at_800[0x7800]; 496 }; 497 498 struct mlx5_ifc_e_switch_cap_bits { 499 u8 vport_svlan_strip[0x1]; 500 u8 vport_cvlan_strip[0x1]; 501 u8 vport_svlan_insert[0x1]; 502 u8 vport_cvlan_insert_if_not_exist[0x1]; 503 u8 vport_cvlan_insert_overwrite[0x1]; 504 u8 reserved_at_5[0x19]; 505 u8 nic_vport_node_guid_modify[0x1]; 506 u8 nic_vport_port_guid_modify[0x1]; 507 508 u8 reserved_at_20[0x7e0]; 509 }; 510 511 struct mlx5_ifc_per_protocol_networking_offload_caps_bits { 512 u8 csum_cap[0x1]; 513 u8 vlan_cap[0x1]; 514 u8 lro_cap[0x1]; 515 u8 lro_psh_flag[0x1]; 516 u8 lro_time_stamp[0x1]; 517 u8 reserved_at_5[0x3]; 518 u8 self_lb_en_modifiable[0x1]; 519 u8 reserved_at_9[0x2]; 520 u8 max_lso_cap[0x5]; 521 u8 reserved_at_10[0x4]; 522 u8 rss_ind_tbl_cap[0x4]; 523 u8 reg_umr_sq[0x1]; 524 u8 scatter_fcs[0x1]; 525 u8 reserved_at_1a[0x1]; 526 u8 tunnel_lso_const_out_ip_id[0x1]; 527 u8 reserved_at_1c[0x2]; 528 u8 tunnel_statless_gre[0x1]; 529 u8 tunnel_stateless_vxlan[0x1]; 530 531 u8 reserved_at_20[0x20]; 532 533 u8 reserved_at_40[0x10]; 534 u8 lro_min_mss_size[0x10]; 535 536 u8 reserved_at_60[0x120]; 537 538 u8 lro_timer_supported_periods[4][0x20]; 539 540 u8 reserved_at_200[0x600]; 541 }; 542 543 struct mlx5_ifc_roce_cap_bits { 544 u8 roce_apm[0x1]; 545 u8 reserved_at_1[0x1f]; 546 547 u8 reserved_at_20[0x60]; 548 549 u8 reserved_at_80[0xc]; 550 u8 l3_type[0x4]; 551 u8 reserved_at_90[0x8]; 552 u8 roce_version[0x8]; 553 554 u8 reserved_at_a0[0x10]; 555 u8 r_roce_dest_udp_port[0x10]; 556 557 u8 r_roce_max_src_udp_port[0x10]; 558 u8 r_roce_min_src_udp_port[0x10]; 559 560 u8 reserved_at_e0[0x10]; 561 u8 roce_address_table_size[0x10]; 562 563 u8 reserved_at_100[0x700]; 564 }; 565 566 enum { 567 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_QP_1_BYTE = 0x0, 568 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_QP_2_BYTES = 0x2, 569 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_QP_4_BYTES = 0x4, 570 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_QP_8_BYTES = 0x8, 571 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_QP_16_BYTES = 0x10, 572 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_QP_32_BYTES = 0x20, 573 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_QP_64_BYTES = 0x40, 574 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_QP_128_BYTES = 0x80, 575 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_QP_256_BYTES = 0x100, 576 }; 577 578 enum { 579 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_DC_1_BYTE = 0x1, 580 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_DC_2_BYTES = 0x2, 581 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_DC_4_BYTES = 0x4, 582 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_DC_8_BYTES = 0x8, 583 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_DC_16_BYTES = 0x10, 584 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_DC_32_BYTES = 0x20, 585 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_DC_64_BYTES = 0x40, 586 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_DC_128_BYTES = 0x80, 587 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_DC_256_BYTES = 0x100, 588 }; 589 590 struct mlx5_ifc_atomic_caps_bits { 591 u8 reserved_at_0[0x40]; 592 593 u8 atomic_req_8B_endianess_mode[0x2]; 594 u8 reserved_at_42[0x4]; 595 u8 supported_atomic_req_8B_endianess_mode_1[0x1]; 596 597 u8 reserved_at_47[0x19]; 598 599 u8 reserved_at_60[0x20]; 600 601 u8 reserved_at_80[0x10]; 602 u8 atomic_operations[0x10]; 603 604 u8 reserved_at_a0[0x10]; 605 u8 atomic_size_qp[0x10]; 606 607 u8 reserved_at_c0[0x10]; 608 u8 atomic_size_dc[0x10]; 609 610 u8 reserved_at_e0[0x720]; 611 }; 612 613 struct mlx5_ifc_odp_cap_bits { 614 u8 reserved_at_0[0x40]; 615 616 u8 sig[0x1]; 617 u8 reserved_at_41[0x1f]; 618 619 u8 reserved_at_60[0x20]; 620 621 struct mlx5_ifc_odp_per_transport_service_cap_bits rc_odp_caps; 622 623 struct mlx5_ifc_odp_per_transport_service_cap_bits uc_odp_caps; 624 625 struct mlx5_ifc_odp_per_transport_service_cap_bits ud_odp_caps; 626 627 u8 reserved_at_e0[0x720]; 628 }; 629 630 struct mlx5_ifc_calc_op { 631 u8 reserved_at_0[0x10]; 632 u8 reserved_at_10[0x9]; 633 u8 op_swap_endianness[0x1]; 634 u8 op_min[0x1]; 635 u8 op_xor[0x1]; 636 u8 op_or[0x1]; 637 u8 op_and[0x1]; 638 u8 op_max[0x1]; 639 u8 op_add[0x1]; 640 }; 641 642 struct mlx5_ifc_vector_calc_cap_bits { 643 u8 calc_matrix[0x1]; 644 u8 reserved_at_1[0x1f]; 645 u8 reserved_at_20[0x8]; 646 u8 max_vec_count[0x8]; 647 u8 reserved_at_30[0xd]; 648 u8 max_chunk_size[0x3]; 649 struct mlx5_ifc_calc_op calc0; 650 struct mlx5_ifc_calc_op calc1; 651 struct mlx5_ifc_calc_op calc2; 652 struct mlx5_ifc_calc_op calc3; 653 654 u8 reserved_at_e0[0x720]; 655 }; 656 657 enum { 658 MLX5_WQ_TYPE_LINKED_LIST = 0x0, 659 MLX5_WQ_TYPE_CYCLIC = 0x1, 660 MLX5_WQ_TYPE_LINKED_LIST_STRIDING_RQ = 0x2, 661 }; 662 663 enum { 664 MLX5_WQ_END_PAD_MODE_NONE = 0x0, 665 MLX5_WQ_END_PAD_MODE_ALIGN = 0x1, 666 }; 667 668 enum { 669 MLX5_CMD_HCA_CAP_GID_TABLE_SIZE_8_GID_ENTRIES = 0x0, 670 MLX5_CMD_HCA_CAP_GID_TABLE_SIZE_16_GID_ENTRIES = 0x1, 671 MLX5_CMD_HCA_CAP_GID_TABLE_SIZE_32_GID_ENTRIES = 0x2, 672 MLX5_CMD_HCA_CAP_GID_TABLE_SIZE_64_GID_ENTRIES = 0x3, 673 MLX5_CMD_HCA_CAP_GID_TABLE_SIZE_128_GID_ENTRIES = 0x4, 674 }; 675 676 enum { 677 MLX5_CMD_HCA_CAP_PKEY_TABLE_SIZE_128_ENTRIES = 0x0, 678 MLX5_CMD_HCA_CAP_PKEY_TABLE_SIZE_256_ENTRIES = 0x1, 679 MLX5_CMD_HCA_CAP_PKEY_TABLE_SIZE_512_ENTRIES = 0x2, 680 MLX5_CMD_HCA_CAP_PKEY_TABLE_SIZE_1K_ENTRIES = 0x3, 681 MLX5_CMD_HCA_CAP_PKEY_TABLE_SIZE_2K_ENTRIES = 0x4, 682 MLX5_CMD_HCA_CAP_PKEY_TABLE_SIZE_4K_ENTRIES = 0x5, 683 }; 684 685 enum { 686 MLX5_CMD_HCA_CAP_PORT_TYPE_IB = 0x0, 687 MLX5_CMD_HCA_CAP_PORT_TYPE_ETHERNET = 0x1, 688 }; 689 690 enum { 691 MLX5_CMD_HCA_CAP_CMDIF_CHECKSUM_DISABLED = 0x0, 692 MLX5_CMD_HCA_CAP_CMDIF_CHECKSUM_INITIAL_STATE = 0x1, 693 MLX5_CMD_HCA_CAP_CMDIF_CHECKSUM_ENABLED = 0x3, 694 }; 695 696 enum { 697 MLX5_CAP_PORT_TYPE_IB = 0x0, 698 MLX5_CAP_PORT_TYPE_ETH = 0x1, 699 }; 700 701 struct mlx5_ifc_cmd_hca_cap_bits { 702 u8 reserved_at_0[0x80]; 703 704 u8 log_max_srq_sz[0x8]; 705 u8 log_max_qp_sz[0x8]; 706 u8 reserved_at_90[0xb]; 707 u8 log_max_qp[0x5]; 708 709 u8 reserved_at_a0[0xb]; 710 u8 log_max_srq[0x5]; 711 u8 reserved_at_b0[0x10]; 712 713 u8 reserved_at_c0[0x8]; 714 u8 log_max_cq_sz[0x8]; 715 u8 reserved_at_d0[0xb]; 716 u8 log_max_cq[0x5]; 717 718 u8 log_max_eq_sz[0x8]; 719 u8 reserved_at_e8[0x2]; 720 u8 log_max_mkey[0x6]; 721 u8 reserved_at_f0[0xc]; 722 u8 log_max_eq[0x4]; 723 724 u8 max_indirection[0x8]; 725 u8 reserved_at_108[0x1]; 726 u8 log_max_mrw_sz[0x7]; 727 u8 reserved_at_110[0x2]; 728 u8 log_max_bsf_list_size[0x6]; 729 u8 reserved_at_118[0x2]; 730 u8 log_max_klm_list_size[0x6]; 731 732 u8 reserved_at_120[0xa]; 733 u8 log_max_ra_req_dc[0x6]; 734 u8 reserved_at_130[0xa]; 735 u8 log_max_ra_res_dc[0x6]; 736 737 u8 reserved_at_140[0xa]; 738 u8 log_max_ra_req_qp[0x6]; 739 u8 reserved_at_150[0xa]; 740 u8 log_max_ra_res_qp[0x6]; 741 742 u8 pad_cap[0x1]; 743 u8 cc_query_allowed[0x1]; 744 u8 cc_modify_allowed[0x1]; 745 u8 reserved_at_163[0xd]; 746 u8 gid_table_size[0x10]; 747 748 u8 out_of_seq_cnt[0x1]; 749 u8 vport_counters[0x1]; 750 u8 reserved_at_182[0x4]; 751 u8 max_qp_cnt[0xa]; 752 u8 pkey_table_size[0x10]; 753 754 u8 vport_group_manager[0x1]; 755 u8 vhca_group_manager[0x1]; 756 u8 ib_virt[0x1]; 757 u8 eth_virt[0x1]; 758 u8 reserved_at_1a4[0x1]; 759 u8 ets[0x1]; 760 u8 nic_flow_table[0x1]; 761 u8 eswitch_flow_table[0x1]; 762 u8 early_vf_enable[0x1]; 763 u8 reserved_at_1a9[0x2]; 764 u8 local_ca_ack_delay[0x5]; 765 u8 reserved_at_1af[0x2]; 766 u8 ports_check[0x1]; 767 u8 reserved_at_1b2[0x1]; 768 u8 disable_link_up[0x1]; 769 u8 beacon_led[0x1]; 770 u8 port_type[0x2]; 771 u8 num_ports[0x8]; 772 773 u8 reserved_at_1c0[0x3]; 774 u8 log_max_msg[0x5]; 775 u8 reserved_at_1c8[0x4]; 776 u8 max_tc[0x4]; 777 u8 reserved_at_1d0[0x6]; 778 u8 rol_s[0x1]; 779 u8 rol_g[0x1]; 780 u8 reserved_at_1d8[0x1]; 781 u8 wol_s[0x1]; 782 u8 wol_g[0x1]; 783 u8 wol_a[0x1]; 784 u8 wol_b[0x1]; 785 u8 wol_m[0x1]; 786 u8 wol_u[0x1]; 787 u8 wol_p[0x1]; 788 789 u8 stat_rate_support[0x10]; 790 u8 reserved_at_1f0[0xc]; 791 u8 cqe_version[0x4]; 792 793 u8 compact_address_vector[0x1]; 794 u8 striding_rq[0x1]; 795 u8 reserved_at_201[0x2]; 796 u8 ipoib_basic_offloads[0x1]; 797 u8 reserved_at_205[0xa]; 798 u8 drain_sigerr[0x1]; 799 u8 cmdif_checksum[0x2]; 800 u8 sigerr_cqe[0x1]; 801 u8 reserved_at_213[0x1]; 802 u8 wq_signature[0x1]; 803 u8 sctr_data_cqe[0x1]; 804 u8 reserved_at_216[0x1]; 805 u8 sho[0x1]; 806 u8 tph[0x1]; 807 u8 rf[0x1]; 808 u8 dct[0x1]; 809 u8 reserved_at_21b[0x1]; 810 u8 eth_net_offloads[0x1]; 811 u8 roce[0x1]; 812 u8 atomic[0x1]; 813 u8 reserved_at_21f[0x1]; 814 815 u8 cq_oi[0x1]; 816 u8 cq_resize[0x1]; 817 u8 cq_moderation[0x1]; 818 u8 reserved_at_223[0x3]; 819 u8 cq_eq_remap[0x1]; 820 u8 pg[0x1]; 821 u8 block_lb_mc[0x1]; 822 u8 reserved_at_229[0x1]; 823 u8 scqe_break_moderation[0x1]; 824 u8 cq_period_start_from_cqe[0x1]; 825 u8 cd[0x1]; 826 u8 reserved_at_22d[0x1]; 827 u8 apm[0x1]; 828 u8 vector_calc[0x1]; 829 u8 umr_ptr_rlky[0x1]; 830 u8 imaicl[0x1]; 831 u8 reserved_at_232[0x4]; 832 u8 qkv[0x1]; 833 u8 pkv[0x1]; 834 u8 set_deth_sqpn[0x1]; 835 u8 reserved_at_239[0x3]; 836 u8 xrc[0x1]; 837 u8 ud[0x1]; 838 u8 uc[0x1]; 839 u8 rc[0x1]; 840 841 u8 reserved_at_240[0xa]; 842 u8 uar_sz[0x6]; 843 u8 reserved_at_250[0x8]; 844 u8 log_pg_sz[0x8]; 845 846 u8 bf[0x1]; 847 u8 reserved_at_261[0x1]; 848 u8 pad_tx_eth_packet[0x1]; 849 u8 reserved_at_263[0x8]; 850 u8 log_bf_reg_size[0x5]; 851 u8 reserved_at_270[0x10]; 852 853 u8 reserved_at_280[0x10]; 854 u8 max_wqe_sz_sq[0x10]; 855 856 u8 reserved_at_2a0[0x10]; 857 u8 max_wqe_sz_rq[0x10]; 858 859 u8 reserved_at_2c0[0x10]; 860 u8 max_wqe_sz_sq_dc[0x10]; 861 862 u8 reserved_at_2e0[0x7]; 863 u8 max_qp_mcg[0x19]; 864 865 u8 reserved_at_300[0x18]; 866 u8 log_max_mcg[0x8]; 867 868 u8 reserved_at_320[0x3]; 869 u8 log_max_transport_domain[0x5]; 870 u8 reserved_at_328[0x3]; 871 u8 log_max_pd[0x5]; 872 u8 reserved_at_330[0xb]; 873 u8 log_max_xrcd[0x5]; 874 875 u8 reserved_at_340[0x20]; 876 877 u8 reserved_at_360[0x3]; 878 u8 log_max_rq[0x5]; 879 u8 reserved_at_368[0x3]; 880 u8 log_max_sq[0x5]; 881 u8 reserved_at_370[0x3]; 882 u8 log_max_tir[0x5]; 883 u8 reserved_at_378[0x3]; 884 u8 log_max_tis[0x5]; 885 886 u8 basic_cyclic_rcv_wqe[0x1]; 887 u8 reserved_at_381[0x2]; 888 u8 log_max_rmp[0x5]; 889 u8 reserved_at_388[0x3]; 890 u8 log_max_rqt[0x5]; 891 u8 reserved_at_390[0x3]; 892 u8 log_max_rqt_size[0x5]; 893 u8 reserved_at_398[0x3]; 894 u8 log_max_tis_per_sq[0x5]; 895 896 u8 reserved_at_3a0[0x3]; 897 u8 log_max_stride_sz_rq[0x5]; 898 u8 reserved_at_3a8[0x3]; 899 u8 log_min_stride_sz_rq[0x5]; 900 u8 reserved_at_3b0[0x3]; 901 u8 log_max_stride_sz_sq[0x5]; 902 u8 reserved_at_3b8[0x3]; 903 u8 log_min_stride_sz_sq[0x5]; 904 905 u8 reserved_at_3c0[0x1b]; 906 u8 log_max_wq_sz[0x5]; 907 908 u8 nic_vport_change_event[0x1]; 909 u8 reserved_at_3e1[0xa]; 910 u8 log_max_vlan_list[0x5]; 911 u8 reserved_at_3f0[0x3]; 912 u8 log_max_current_mc_list[0x5]; 913 u8 reserved_at_3f8[0x3]; 914 u8 log_max_current_uc_list[0x5]; 915 916 u8 reserved_at_400[0x80]; 917 918 u8 reserved_at_480[0x3]; 919 u8 log_max_l2_table[0x5]; 920 u8 reserved_at_488[0x8]; 921 u8 log_uar_page_sz[0x10]; 922 923 u8 reserved_at_4a0[0x20]; 924 u8 device_frequency_mhz[0x20]; 925 u8 device_frequency_khz[0x20]; 926 927 u8 reserved_at_500[0x80]; 928 929 u8 reserved_at_580[0x3f]; 930 u8 cqe_compression[0x1]; 931 932 u8 cqe_compression_timeout[0x10]; 933 u8 cqe_compression_max_num[0x10]; 934 935 u8 reserved_at_5e0[0x220]; 936 }; 937 938 enum mlx5_flow_destination_type { 939 MLX5_FLOW_DESTINATION_TYPE_VPORT = 0x0, 940 MLX5_FLOW_DESTINATION_TYPE_FLOW_TABLE = 0x1, 941 MLX5_FLOW_DESTINATION_TYPE_TIR = 0x2, 942 943 MLX5_FLOW_DESTINATION_TYPE_COUNTER = 0x100, 944 }; 945 946 struct mlx5_ifc_dest_format_struct_bits { 947 u8 destination_type[0x8]; 948 u8 destination_id[0x18]; 949 950 u8 reserved_at_20[0x20]; 951 }; 952 953 struct mlx5_ifc_flow_counter_list_bits { 954 u8 reserved_at_0[0x10]; 955 u8 flow_counter_id[0x10]; 956 957 u8 reserved_at_20[0x20]; 958 }; 959 960 union mlx5_ifc_dest_format_struct_flow_counter_list_auto_bits { 961 struct mlx5_ifc_dest_format_struct_bits dest_format_struct; 962 struct mlx5_ifc_flow_counter_list_bits flow_counter_list; 963 u8 reserved_at_0[0x40]; 964 }; 965 966 struct mlx5_ifc_fte_match_param_bits { 967 struct mlx5_ifc_fte_match_set_lyr_2_4_bits outer_headers; 968 969 struct mlx5_ifc_fte_match_set_misc_bits misc_parameters; 970 971 struct mlx5_ifc_fte_match_set_lyr_2_4_bits inner_headers; 972 973 u8 reserved_at_600[0xa00]; 974 }; 975 976 enum { 977 MLX5_RX_HASH_FIELD_SELECT_SELECTED_FIELDS_SRC_IP = 0x0, 978 MLX5_RX_HASH_FIELD_SELECT_SELECTED_FIELDS_DST_IP = 0x1, 979 MLX5_RX_HASH_FIELD_SELECT_SELECTED_FIELDS_L4_SPORT = 0x2, 980 MLX5_RX_HASH_FIELD_SELECT_SELECTED_FIELDS_L4_DPORT = 0x3, 981 MLX5_RX_HASH_FIELD_SELECT_SELECTED_FIELDS_IPSEC_SPI = 0x4, 982 }; 983 984 struct mlx5_ifc_rx_hash_field_select_bits { 985 u8 l3_prot_type[0x1]; 986 u8 l4_prot_type[0x1]; 987 u8 selected_fields[0x1e]; 988 }; 989 990 enum { 991 MLX5_WQ_WQ_TYPE_WQ_LINKED_LIST = 0x0, 992 MLX5_WQ_WQ_TYPE_WQ_CYCLIC = 0x1, 993 }; 994 995 enum { 996 MLX5_WQ_END_PADDING_MODE_END_PAD_NONE = 0x0, 997 MLX5_WQ_END_PADDING_MODE_END_PAD_ALIGN = 0x1, 998 }; 999 1000 struct mlx5_ifc_wq_bits { 1001 u8 wq_type[0x4]; 1002 u8 wq_signature[0x1]; 1003 u8 end_padding_mode[0x2]; 1004 u8 cd_slave[0x1]; 1005 u8 reserved_at_8[0x18]; 1006 1007 u8 hds_skip_first_sge[0x1]; 1008 u8 log2_hds_buf_size[0x3]; 1009 u8 reserved_at_24[0x7]; 1010 u8 page_offset[0x5]; 1011 u8 lwm[0x10]; 1012 1013 u8 reserved_at_40[0x8]; 1014 u8 pd[0x18]; 1015 1016 u8 reserved_at_60[0x8]; 1017 u8 uar_page[0x18]; 1018 1019 u8 dbr_addr[0x40]; 1020 1021 u8 hw_counter[0x20]; 1022 1023 u8 sw_counter[0x20]; 1024 1025 u8 reserved_at_100[0xc]; 1026 u8 log_wq_stride[0x4]; 1027 u8 reserved_at_110[0x3]; 1028 u8 log_wq_pg_sz[0x5]; 1029 u8 reserved_at_118[0x3]; 1030 u8 log_wq_sz[0x5]; 1031 1032 u8 reserved_at_120[0x15]; 1033 u8 log_wqe_num_of_strides[0x3]; 1034 u8 two_byte_shift_en[0x1]; 1035 u8 reserved_at_139[0x4]; 1036 u8 log_wqe_stride_size[0x3]; 1037 1038 u8 reserved_at_140[0x4c0]; 1039 1040 struct mlx5_ifc_cmd_pas_bits pas[0]; 1041 }; 1042 1043 struct mlx5_ifc_rq_num_bits { 1044 u8 reserved_at_0[0x8]; 1045 u8 rq_num[0x18]; 1046 }; 1047 1048 struct mlx5_ifc_mac_address_layout_bits { 1049 u8 reserved_at_0[0x10]; 1050 u8 mac_addr_47_32[0x10]; 1051 1052 u8 mac_addr_31_0[0x20]; 1053 }; 1054 1055 struct mlx5_ifc_vlan_layout_bits { 1056 u8 reserved_at_0[0x14]; 1057 u8 vlan[0x0c]; 1058 1059 u8 reserved_at_20[0x20]; 1060 }; 1061 1062 struct mlx5_ifc_cong_control_r_roce_ecn_np_bits { 1063 u8 reserved_at_0[0xa0]; 1064 1065 u8 min_time_between_cnps[0x20]; 1066 1067 u8 reserved_at_c0[0x12]; 1068 u8 cnp_dscp[0x6]; 1069 u8 reserved_at_d8[0x5]; 1070 u8 cnp_802p_prio[0x3]; 1071 1072 u8 reserved_at_e0[0x720]; 1073 }; 1074 1075 struct mlx5_ifc_cong_control_r_roce_ecn_rp_bits { 1076 u8 reserved_at_0[0x60]; 1077 1078 u8 reserved_at_60[0x4]; 1079 u8 clamp_tgt_rate[0x1]; 1080 u8 reserved_at_65[0x3]; 1081 u8 clamp_tgt_rate_after_time_inc[0x1]; 1082 u8 reserved_at_69[0x17]; 1083 1084 u8 reserved_at_80[0x20]; 1085 1086 u8 rpg_time_reset[0x20]; 1087 1088 u8 rpg_byte_reset[0x20]; 1089 1090 u8 rpg_threshold[0x20]; 1091 1092 u8 rpg_max_rate[0x20]; 1093 1094 u8 rpg_ai_rate[0x20]; 1095 1096 u8 rpg_hai_rate[0x20]; 1097 1098 u8 rpg_gd[0x20]; 1099 1100 u8 rpg_min_dec_fac[0x20]; 1101 1102 u8 rpg_min_rate[0x20]; 1103 1104 u8 reserved_at_1c0[0xe0]; 1105 1106 u8 rate_to_set_on_first_cnp[0x20]; 1107 1108 u8 dce_tcp_g[0x20]; 1109 1110 u8 dce_tcp_rtt[0x20]; 1111 1112 u8 rate_reduce_monitor_period[0x20]; 1113 1114 u8 reserved_at_320[0x20]; 1115 1116 u8 initial_alpha_value[0x20]; 1117 1118 u8 reserved_at_360[0x4a0]; 1119 }; 1120 1121 struct mlx5_ifc_cong_control_802_1qau_rp_bits { 1122 u8 reserved_at_0[0x80]; 1123 1124 u8 rppp_max_rps[0x20]; 1125 1126 u8 rpg_time_reset[0x20]; 1127 1128 u8 rpg_byte_reset[0x20]; 1129 1130 u8 rpg_threshold[0x20]; 1131 1132 u8 rpg_max_rate[0x20]; 1133 1134 u8 rpg_ai_rate[0x20]; 1135 1136 u8 rpg_hai_rate[0x20]; 1137 1138 u8 rpg_gd[0x20]; 1139 1140 u8 rpg_min_dec_fac[0x20]; 1141 1142 u8 rpg_min_rate[0x20]; 1143 1144 u8 reserved_at_1c0[0x640]; 1145 }; 1146 1147 enum { 1148 MLX5_RESIZE_FIELD_SELECT_RESIZE_FIELD_SELECT_LOG_CQ_SIZE = 0x1, 1149 MLX5_RESIZE_FIELD_SELECT_RESIZE_FIELD_SELECT_PAGE_OFFSET = 0x2, 1150 MLX5_RESIZE_FIELD_SELECT_RESIZE_FIELD_SELECT_LOG_PAGE_SIZE = 0x4, 1151 }; 1152 1153 struct mlx5_ifc_resize_field_select_bits { 1154 u8 resize_field_select[0x20]; 1155 }; 1156 1157 enum { 1158 MLX5_MODIFY_FIELD_SELECT_MODIFY_FIELD_SELECT_CQ_PERIOD = 0x1, 1159 MLX5_MODIFY_FIELD_SELECT_MODIFY_FIELD_SELECT_CQ_MAX_COUNT = 0x2, 1160 MLX5_MODIFY_FIELD_SELECT_MODIFY_FIELD_SELECT_OI = 0x4, 1161 MLX5_MODIFY_FIELD_SELECT_MODIFY_FIELD_SELECT_C_EQN = 0x8, 1162 }; 1163 1164 struct mlx5_ifc_modify_field_select_bits { 1165 u8 modify_field_select[0x20]; 1166 }; 1167 1168 struct mlx5_ifc_field_select_r_roce_np_bits { 1169 u8 field_select_r_roce_np[0x20]; 1170 }; 1171 1172 struct mlx5_ifc_field_select_r_roce_rp_bits { 1173 u8 field_select_r_roce_rp[0x20]; 1174 }; 1175 1176 enum { 1177 MLX5_FIELD_SELECT_802_1QAU_RP_FIELD_SELECT_8021QAURP_RPPP_MAX_RPS = 0x4, 1178 MLX5_FIELD_SELECT_802_1QAU_RP_FIELD_SELECT_8021QAURP_RPG_TIME_RESET = 0x8, 1179 MLX5_FIELD_SELECT_802_1QAU_RP_FIELD_SELECT_8021QAURP_RPG_BYTE_RESET = 0x10, 1180 MLX5_FIELD_SELECT_802_1QAU_RP_FIELD_SELECT_8021QAURP_RPG_THRESHOLD = 0x20, 1181 MLX5_FIELD_SELECT_802_1QAU_RP_FIELD_SELECT_8021QAURP_RPG_MAX_RATE = 0x40, 1182 MLX5_FIELD_SELECT_802_1QAU_RP_FIELD_SELECT_8021QAURP_RPG_AI_RATE = 0x80, 1183 MLX5_FIELD_SELECT_802_1QAU_RP_FIELD_SELECT_8021QAURP_RPG_HAI_RATE = 0x100, 1184 MLX5_FIELD_SELECT_802_1QAU_RP_FIELD_SELECT_8021QAURP_RPG_GD = 0x200, 1185 MLX5_FIELD_SELECT_802_1QAU_RP_FIELD_SELECT_8021QAURP_RPG_MIN_DEC_FAC = 0x400, 1186 MLX5_FIELD_SELECT_802_1QAU_RP_FIELD_SELECT_8021QAURP_RPG_MIN_RATE = 0x800, 1187 }; 1188 1189 struct mlx5_ifc_field_select_802_1qau_rp_bits { 1190 u8 field_select_8021qaurp[0x20]; 1191 }; 1192 1193 struct mlx5_ifc_phys_layer_cntrs_bits { 1194 u8 time_since_last_clear_high[0x20]; 1195 1196 u8 time_since_last_clear_low[0x20]; 1197 1198 u8 symbol_errors_high[0x20]; 1199 1200 u8 symbol_errors_low[0x20]; 1201 1202 u8 sync_headers_errors_high[0x20]; 1203 1204 u8 sync_headers_errors_low[0x20]; 1205 1206 u8 edpl_bip_errors_lane0_high[0x20]; 1207 1208 u8 edpl_bip_errors_lane0_low[0x20]; 1209 1210 u8 edpl_bip_errors_lane1_high[0x20]; 1211 1212 u8 edpl_bip_errors_lane1_low[0x20]; 1213 1214 u8 edpl_bip_errors_lane2_high[0x20]; 1215 1216 u8 edpl_bip_errors_lane2_low[0x20]; 1217 1218 u8 edpl_bip_errors_lane3_high[0x20]; 1219 1220 u8 edpl_bip_errors_lane3_low[0x20]; 1221 1222 u8 fc_fec_corrected_blocks_lane0_high[0x20]; 1223 1224 u8 fc_fec_corrected_blocks_lane0_low[0x20]; 1225 1226 u8 fc_fec_corrected_blocks_lane1_high[0x20]; 1227 1228 u8 fc_fec_corrected_blocks_lane1_low[0x20]; 1229 1230 u8 fc_fec_corrected_blocks_lane2_high[0x20]; 1231 1232 u8 fc_fec_corrected_blocks_lane2_low[0x20]; 1233 1234 u8 fc_fec_corrected_blocks_lane3_high[0x20]; 1235 1236 u8 fc_fec_corrected_blocks_lane3_low[0x20]; 1237 1238 u8 fc_fec_uncorrectable_blocks_lane0_high[0x20]; 1239 1240 u8 fc_fec_uncorrectable_blocks_lane0_low[0x20]; 1241 1242 u8 fc_fec_uncorrectable_blocks_lane1_high[0x20]; 1243 1244 u8 fc_fec_uncorrectable_blocks_lane1_low[0x20]; 1245 1246 u8 fc_fec_uncorrectable_blocks_lane2_high[0x20]; 1247 1248 u8 fc_fec_uncorrectable_blocks_lane2_low[0x20]; 1249 1250 u8 fc_fec_uncorrectable_blocks_lane3_high[0x20]; 1251 1252 u8 fc_fec_uncorrectable_blocks_lane3_low[0x20]; 1253 1254 u8 rs_fec_corrected_blocks_high[0x20]; 1255 1256 u8 rs_fec_corrected_blocks_low[0x20]; 1257 1258 u8 rs_fec_uncorrectable_blocks_high[0x20]; 1259 1260 u8 rs_fec_uncorrectable_blocks_low[0x20]; 1261 1262 u8 rs_fec_no_errors_blocks_high[0x20]; 1263 1264 u8 rs_fec_no_errors_blocks_low[0x20]; 1265 1266 u8 rs_fec_single_error_blocks_high[0x20]; 1267 1268 u8 rs_fec_single_error_blocks_low[0x20]; 1269 1270 u8 rs_fec_corrected_symbols_total_high[0x20]; 1271 1272 u8 rs_fec_corrected_symbols_total_low[0x20]; 1273 1274 u8 rs_fec_corrected_symbols_lane0_high[0x20]; 1275 1276 u8 rs_fec_corrected_symbols_lane0_low[0x20]; 1277 1278 u8 rs_fec_corrected_symbols_lane1_high[0x20]; 1279 1280 u8 rs_fec_corrected_symbols_lane1_low[0x20]; 1281 1282 u8 rs_fec_corrected_symbols_lane2_high[0x20]; 1283 1284 u8 rs_fec_corrected_symbols_lane2_low[0x20]; 1285 1286 u8 rs_fec_corrected_symbols_lane3_high[0x20]; 1287 1288 u8 rs_fec_corrected_symbols_lane3_low[0x20]; 1289 1290 u8 link_down_events[0x20]; 1291 1292 u8 successful_recovery_events[0x20]; 1293 1294 u8 reserved_at_640[0x180]; 1295 }; 1296 1297 struct mlx5_ifc_ib_port_cntrs_grp_data_layout_bits { 1298 u8 symbol_error_counter[0x10]; 1299 1300 u8 link_error_recovery_counter[0x8]; 1301 1302 u8 link_downed_counter[0x8]; 1303 1304 u8 port_rcv_errors[0x10]; 1305 1306 u8 port_rcv_remote_physical_errors[0x10]; 1307 1308 u8 port_rcv_switch_relay_errors[0x10]; 1309 1310 u8 port_xmit_discards[0x10]; 1311 1312 u8 port_xmit_constraint_errors[0x8]; 1313 1314 u8 port_rcv_constraint_errors[0x8]; 1315 1316 u8 reserved_at_70[0x8]; 1317 1318 u8 link_overrun_errors[0x8]; 1319 1320 u8 reserved_at_80[0x10]; 1321 1322 u8 vl_15_dropped[0x10]; 1323 1324 u8 reserved_at_a0[0xa0]; 1325 }; 1326 1327 struct mlx5_ifc_eth_per_traffic_grp_data_layout_bits { 1328 u8 transmit_queue_high[0x20]; 1329 1330 u8 transmit_queue_low[0x20]; 1331 1332 u8 reserved_at_40[0x780]; 1333 }; 1334 1335 struct mlx5_ifc_eth_per_prio_grp_data_layout_bits { 1336 u8 rx_octets_high[0x20]; 1337 1338 u8 rx_octets_low[0x20]; 1339 1340 u8 reserved_at_40[0xc0]; 1341 1342 u8 rx_frames_high[0x20]; 1343 1344 u8 rx_frames_low[0x20]; 1345 1346 u8 tx_octets_high[0x20]; 1347 1348 u8 tx_octets_low[0x20]; 1349 1350 u8 reserved_at_180[0xc0]; 1351 1352 u8 tx_frames_high[0x20]; 1353 1354 u8 tx_frames_low[0x20]; 1355 1356 u8 rx_pause_high[0x20]; 1357 1358 u8 rx_pause_low[0x20]; 1359 1360 u8 rx_pause_duration_high[0x20]; 1361 1362 u8 rx_pause_duration_low[0x20]; 1363 1364 u8 tx_pause_high[0x20]; 1365 1366 u8 tx_pause_low[0x20]; 1367 1368 u8 tx_pause_duration_high[0x20]; 1369 1370 u8 tx_pause_duration_low[0x20]; 1371 1372 u8 rx_pause_transition_high[0x20]; 1373 1374 u8 rx_pause_transition_low[0x20]; 1375 1376 u8 reserved_at_3c0[0x400]; 1377 }; 1378 1379 struct mlx5_ifc_eth_extended_cntrs_grp_data_layout_bits { 1380 u8 port_transmit_wait_high[0x20]; 1381 1382 u8 port_transmit_wait_low[0x20]; 1383 1384 u8 reserved_at_40[0x780]; 1385 }; 1386 1387 struct mlx5_ifc_eth_3635_cntrs_grp_data_layout_bits { 1388 u8 dot3stats_alignment_errors_high[0x20]; 1389 1390 u8 dot3stats_alignment_errors_low[0x20]; 1391 1392 u8 dot3stats_fcs_errors_high[0x20]; 1393 1394 u8 dot3stats_fcs_errors_low[0x20]; 1395 1396 u8 dot3stats_single_collision_frames_high[0x20]; 1397 1398 u8 dot3stats_single_collision_frames_low[0x20]; 1399 1400 u8 dot3stats_multiple_collision_frames_high[0x20]; 1401 1402 u8 dot3stats_multiple_collision_frames_low[0x20]; 1403 1404 u8 dot3stats_sqe_test_errors_high[0x20]; 1405 1406 u8 dot3stats_sqe_test_errors_low[0x20]; 1407 1408 u8 dot3stats_deferred_transmissions_high[0x20]; 1409 1410 u8 dot3stats_deferred_transmissions_low[0x20]; 1411 1412 u8 dot3stats_late_collisions_high[0x20]; 1413 1414 u8 dot3stats_late_collisions_low[0x20]; 1415 1416 u8 dot3stats_excessive_collisions_high[0x20]; 1417 1418 u8 dot3stats_excessive_collisions_low[0x20]; 1419 1420 u8 dot3stats_internal_mac_transmit_errors_high[0x20]; 1421 1422 u8 dot3stats_internal_mac_transmit_errors_low[0x20]; 1423 1424 u8 dot3stats_carrier_sense_errors_high[0x20]; 1425 1426 u8 dot3stats_carrier_sense_errors_low[0x20]; 1427 1428 u8 dot3stats_frame_too_longs_high[0x20]; 1429 1430 u8 dot3stats_frame_too_longs_low[0x20]; 1431 1432 u8 dot3stats_internal_mac_receive_errors_high[0x20]; 1433 1434 u8 dot3stats_internal_mac_receive_errors_low[0x20]; 1435 1436 u8 dot3stats_symbol_errors_high[0x20]; 1437 1438 u8 dot3stats_symbol_errors_low[0x20]; 1439 1440 u8 dot3control_in_unknown_opcodes_high[0x20]; 1441 1442 u8 dot3control_in_unknown_opcodes_low[0x20]; 1443 1444 u8 dot3in_pause_frames_high[0x20]; 1445 1446 u8 dot3in_pause_frames_low[0x20]; 1447 1448 u8 dot3out_pause_frames_high[0x20]; 1449 1450 u8 dot3out_pause_frames_low[0x20]; 1451 1452 u8 reserved_at_400[0x3c0]; 1453 }; 1454 1455 struct mlx5_ifc_eth_2819_cntrs_grp_data_layout_bits { 1456 u8 ether_stats_drop_events_high[0x20]; 1457 1458 u8 ether_stats_drop_events_low[0x20]; 1459 1460 u8 ether_stats_octets_high[0x20]; 1461 1462 u8 ether_stats_octets_low[0x20]; 1463 1464 u8 ether_stats_pkts_high[0x20]; 1465 1466 u8 ether_stats_pkts_low[0x20]; 1467 1468 u8 ether_stats_broadcast_pkts_high[0x20]; 1469 1470 u8 ether_stats_broadcast_pkts_low[0x20]; 1471 1472 u8 ether_stats_multicast_pkts_high[0x20]; 1473 1474 u8 ether_stats_multicast_pkts_low[0x20]; 1475 1476 u8 ether_stats_crc_align_errors_high[0x20]; 1477 1478 u8 ether_stats_crc_align_errors_low[0x20]; 1479 1480 u8 ether_stats_undersize_pkts_high[0x20]; 1481 1482 u8 ether_stats_undersize_pkts_low[0x20]; 1483 1484 u8 ether_stats_oversize_pkts_high[0x20]; 1485 1486 u8 ether_stats_oversize_pkts_low[0x20]; 1487 1488 u8 ether_stats_fragments_high[0x20]; 1489 1490 u8 ether_stats_fragments_low[0x20]; 1491 1492 u8 ether_stats_jabbers_high[0x20]; 1493 1494 u8 ether_stats_jabbers_low[0x20]; 1495 1496 u8 ether_stats_collisions_high[0x20]; 1497 1498 u8 ether_stats_collisions_low[0x20]; 1499 1500 u8 ether_stats_pkts64octets_high[0x20]; 1501 1502 u8 ether_stats_pkts64octets_low[0x20]; 1503 1504 u8 ether_stats_pkts65to127octets_high[0x20]; 1505 1506 u8 ether_stats_pkts65to127octets_low[0x20]; 1507 1508 u8 ether_stats_pkts128to255octets_high[0x20]; 1509 1510 u8 ether_stats_pkts128to255octets_low[0x20]; 1511 1512 u8 ether_stats_pkts256to511octets_high[0x20]; 1513 1514 u8 ether_stats_pkts256to511octets_low[0x20]; 1515 1516 u8 ether_stats_pkts512to1023octets_high[0x20]; 1517 1518 u8 ether_stats_pkts512to1023octets_low[0x20]; 1519 1520 u8 ether_stats_pkts1024to1518octets_high[0x20]; 1521 1522 u8 ether_stats_pkts1024to1518octets_low[0x20]; 1523 1524 u8 ether_stats_pkts1519to2047octets_high[0x20]; 1525 1526 u8 ether_stats_pkts1519to2047octets_low[0x20]; 1527 1528 u8 ether_stats_pkts2048to4095octets_high[0x20]; 1529 1530 u8 ether_stats_pkts2048to4095octets_low[0x20]; 1531 1532 u8 ether_stats_pkts4096to8191octets_high[0x20]; 1533 1534 u8 ether_stats_pkts4096to8191octets_low[0x20]; 1535 1536 u8 ether_stats_pkts8192to10239octets_high[0x20]; 1537 1538 u8 ether_stats_pkts8192to10239octets_low[0x20]; 1539 1540 u8 reserved_at_540[0x280]; 1541 }; 1542 1543 struct mlx5_ifc_eth_2863_cntrs_grp_data_layout_bits { 1544 u8 if_in_octets_high[0x20]; 1545 1546 u8 if_in_octets_low[0x20]; 1547 1548 u8 if_in_ucast_pkts_high[0x20]; 1549 1550 u8 if_in_ucast_pkts_low[0x20]; 1551 1552 u8 if_in_discards_high[0x20]; 1553 1554 u8 if_in_discards_low[0x20]; 1555 1556 u8 if_in_errors_high[0x20]; 1557 1558 u8 if_in_errors_low[0x20]; 1559 1560 u8 if_in_unknown_protos_high[0x20]; 1561 1562 u8 if_in_unknown_protos_low[0x20]; 1563 1564 u8 if_out_octets_high[0x20]; 1565 1566 u8 if_out_octets_low[0x20]; 1567 1568 u8 if_out_ucast_pkts_high[0x20]; 1569 1570 u8 if_out_ucast_pkts_low[0x20]; 1571 1572 u8 if_out_discards_high[0x20]; 1573 1574 u8 if_out_discards_low[0x20]; 1575 1576 u8 if_out_errors_high[0x20]; 1577 1578 u8 if_out_errors_low[0x20]; 1579 1580 u8 if_in_multicast_pkts_high[0x20]; 1581 1582 u8 if_in_multicast_pkts_low[0x20]; 1583 1584 u8 if_in_broadcast_pkts_high[0x20]; 1585 1586 u8 if_in_broadcast_pkts_low[0x20]; 1587 1588 u8 if_out_multicast_pkts_high[0x20]; 1589 1590 u8 if_out_multicast_pkts_low[0x20]; 1591 1592 u8 if_out_broadcast_pkts_high[0x20]; 1593 1594 u8 if_out_broadcast_pkts_low[0x20]; 1595 1596 u8 reserved_at_340[0x480]; 1597 }; 1598 1599 struct mlx5_ifc_eth_802_3_cntrs_grp_data_layout_bits { 1600 u8 a_frames_transmitted_ok_high[0x20]; 1601 1602 u8 a_frames_transmitted_ok_low[0x20]; 1603 1604 u8 a_frames_received_ok_high[0x20]; 1605 1606 u8 a_frames_received_ok_low[0x20]; 1607 1608 u8 a_frame_check_sequence_errors_high[0x20]; 1609 1610 u8 a_frame_check_sequence_errors_low[0x20]; 1611 1612 u8 a_alignment_errors_high[0x20]; 1613 1614 u8 a_alignment_errors_low[0x20]; 1615 1616 u8 a_octets_transmitted_ok_high[0x20]; 1617 1618 u8 a_octets_transmitted_ok_low[0x20]; 1619 1620 u8 a_octets_received_ok_high[0x20]; 1621 1622 u8 a_octets_received_ok_low[0x20]; 1623 1624 u8 a_multicast_frames_xmitted_ok_high[0x20]; 1625 1626 u8 a_multicast_frames_xmitted_ok_low[0x20]; 1627 1628 u8 a_broadcast_frames_xmitted_ok_high[0x20]; 1629 1630 u8 a_broadcast_frames_xmitted_ok_low[0x20]; 1631 1632 u8 a_multicast_frames_received_ok_high[0x20]; 1633 1634 u8 a_multicast_frames_received_ok_low[0x20]; 1635 1636 u8 a_broadcast_frames_received_ok_high[0x20]; 1637 1638 u8 a_broadcast_frames_received_ok_low[0x20]; 1639 1640 u8 a_in_range_length_errors_high[0x20]; 1641 1642 u8 a_in_range_length_errors_low[0x20]; 1643 1644 u8 a_out_of_range_length_field_high[0x20]; 1645 1646 u8 a_out_of_range_length_field_low[0x20]; 1647 1648 u8 a_frame_too_long_errors_high[0x20]; 1649 1650 u8 a_frame_too_long_errors_low[0x20]; 1651 1652 u8 a_symbol_error_during_carrier_high[0x20]; 1653 1654 u8 a_symbol_error_during_carrier_low[0x20]; 1655 1656 u8 a_mac_control_frames_transmitted_high[0x20]; 1657 1658 u8 a_mac_control_frames_transmitted_low[0x20]; 1659 1660 u8 a_mac_control_frames_received_high[0x20]; 1661 1662 u8 a_mac_control_frames_received_low[0x20]; 1663 1664 u8 a_unsupported_opcodes_received_high[0x20]; 1665 1666 u8 a_unsupported_opcodes_received_low[0x20]; 1667 1668 u8 a_pause_mac_ctrl_frames_received_high[0x20]; 1669 1670 u8 a_pause_mac_ctrl_frames_received_low[0x20]; 1671 1672 u8 a_pause_mac_ctrl_frames_transmitted_high[0x20]; 1673 1674 u8 a_pause_mac_ctrl_frames_transmitted_low[0x20]; 1675 1676 u8 reserved_at_4c0[0x300]; 1677 }; 1678 1679 struct mlx5_ifc_cmd_inter_comp_event_bits { 1680 u8 command_completion_vector[0x20]; 1681 1682 u8 reserved_at_20[0xc0]; 1683 }; 1684 1685 struct mlx5_ifc_stall_vl_event_bits { 1686 u8 reserved_at_0[0x18]; 1687 u8 port_num[0x1]; 1688 u8 reserved_at_19[0x3]; 1689 u8 vl[0x4]; 1690 1691 u8 reserved_at_20[0xa0]; 1692 }; 1693 1694 struct mlx5_ifc_db_bf_congestion_event_bits { 1695 u8 event_subtype[0x8]; 1696 u8 reserved_at_8[0x8]; 1697 u8 congestion_level[0x8]; 1698 u8 reserved_at_18[0x8]; 1699 1700 u8 reserved_at_20[0xa0]; 1701 }; 1702 1703 struct mlx5_ifc_gpio_event_bits { 1704 u8 reserved_at_0[0x60]; 1705 1706 u8 gpio_event_hi[0x20]; 1707 1708 u8 gpio_event_lo[0x20]; 1709 1710 u8 reserved_at_a0[0x40]; 1711 }; 1712 1713 struct mlx5_ifc_port_state_change_event_bits { 1714 u8 reserved_at_0[0x40]; 1715 1716 u8 port_num[0x4]; 1717 u8 reserved_at_44[0x1c]; 1718 1719 u8 reserved_at_60[0x80]; 1720 }; 1721 1722 struct mlx5_ifc_dropped_packet_logged_bits { 1723 u8 reserved_at_0[0xe0]; 1724 }; 1725 1726 enum { 1727 MLX5_CQ_ERROR_SYNDROME_CQ_OVERRUN = 0x1, 1728 MLX5_CQ_ERROR_SYNDROME_CQ_ACCESS_VIOLATION_ERROR = 0x2, 1729 }; 1730 1731 struct mlx5_ifc_cq_error_bits { 1732 u8 reserved_at_0[0x8]; 1733 u8 cqn[0x18]; 1734 1735 u8 reserved_at_20[0x20]; 1736 1737 u8 reserved_at_40[0x18]; 1738 u8 syndrome[0x8]; 1739 1740 u8 reserved_at_60[0x80]; 1741 }; 1742 1743 struct mlx5_ifc_rdma_page_fault_event_bits { 1744 u8 bytes_committed[0x20]; 1745 1746 u8 r_key[0x20]; 1747 1748 u8 reserved_at_40[0x10]; 1749 u8 packet_len[0x10]; 1750 1751 u8 rdma_op_len[0x20]; 1752 1753 u8 rdma_va[0x40]; 1754 1755 u8 reserved_at_c0[0x5]; 1756 u8 rdma[0x1]; 1757 u8 write[0x1]; 1758 u8 requestor[0x1]; 1759 u8 qp_number[0x18]; 1760 }; 1761 1762 struct mlx5_ifc_wqe_associated_page_fault_event_bits { 1763 u8 bytes_committed[0x20]; 1764 1765 u8 reserved_at_20[0x10]; 1766 u8 wqe_index[0x10]; 1767 1768 u8 reserved_at_40[0x10]; 1769 u8 len[0x10]; 1770 1771 u8 reserved_at_60[0x60]; 1772 1773 u8 reserved_at_c0[0x5]; 1774 u8 rdma[0x1]; 1775 u8 write_read[0x1]; 1776 u8 requestor[0x1]; 1777 u8 qpn[0x18]; 1778 }; 1779 1780 struct mlx5_ifc_qp_events_bits { 1781 u8 reserved_at_0[0xa0]; 1782 1783 u8 type[0x8]; 1784 u8 reserved_at_a8[0x18]; 1785 1786 u8 reserved_at_c0[0x8]; 1787 u8 qpn_rqn_sqn[0x18]; 1788 }; 1789 1790 struct mlx5_ifc_dct_events_bits { 1791 u8 reserved_at_0[0xc0]; 1792 1793 u8 reserved_at_c0[0x8]; 1794 u8 dct_number[0x18]; 1795 }; 1796 1797 struct mlx5_ifc_comp_event_bits { 1798 u8 reserved_at_0[0xc0]; 1799 1800 u8 reserved_at_c0[0x8]; 1801 u8 cq_number[0x18]; 1802 }; 1803 1804 enum { 1805 MLX5_QPC_STATE_RST = 0x0, 1806 MLX5_QPC_STATE_INIT = 0x1, 1807 MLX5_QPC_STATE_RTR = 0x2, 1808 MLX5_QPC_STATE_RTS = 0x3, 1809 MLX5_QPC_STATE_SQER = 0x4, 1810 MLX5_QPC_STATE_ERR = 0x6, 1811 MLX5_QPC_STATE_SQD = 0x7, 1812 MLX5_QPC_STATE_SUSPENDED = 0x9, 1813 }; 1814 1815 enum { 1816 MLX5_QPC_ST_RC = 0x0, 1817 MLX5_QPC_ST_UC = 0x1, 1818 MLX5_QPC_ST_UD = 0x2, 1819 MLX5_QPC_ST_XRC = 0x3, 1820 MLX5_QPC_ST_DCI = 0x5, 1821 MLX5_QPC_ST_QP0 = 0x7, 1822 MLX5_QPC_ST_QP1 = 0x8, 1823 MLX5_QPC_ST_RAW_DATAGRAM = 0x9, 1824 MLX5_QPC_ST_REG_UMR = 0xc, 1825 }; 1826 1827 enum { 1828 MLX5_QPC_PM_STATE_ARMED = 0x0, 1829 MLX5_QPC_PM_STATE_REARM = 0x1, 1830 MLX5_QPC_PM_STATE_RESERVED = 0x2, 1831 MLX5_QPC_PM_STATE_MIGRATED = 0x3, 1832 }; 1833 1834 enum { 1835 MLX5_QPC_END_PADDING_MODE_SCATTER_AS_IS = 0x0, 1836 MLX5_QPC_END_PADDING_MODE_PAD_TO_CACHE_LINE_ALIGNMENT = 0x1, 1837 }; 1838 1839 enum { 1840 MLX5_QPC_MTU_256_BYTES = 0x1, 1841 MLX5_QPC_MTU_512_BYTES = 0x2, 1842 MLX5_QPC_MTU_1K_BYTES = 0x3, 1843 MLX5_QPC_MTU_2K_BYTES = 0x4, 1844 MLX5_QPC_MTU_4K_BYTES = 0x5, 1845 MLX5_QPC_MTU_RAW_ETHERNET_QP = 0x7, 1846 }; 1847 1848 enum { 1849 MLX5_QPC_ATOMIC_MODE_IB_SPEC = 0x1, 1850 MLX5_QPC_ATOMIC_MODE_ONLY_8B = 0x2, 1851 MLX5_QPC_ATOMIC_MODE_UP_TO_8B = 0x3, 1852 MLX5_QPC_ATOMIC_MODE_UP_TO_16B = 0x4, 1853 MLX5_QPC_ATOMIC_MODE_UP_TO_32B = 0x5, 1854 MLX5_QPC_ATOMIC_MODE_UP_TO_64B = 0x6, 1855 MLX5_QPC_ATOMIC_MODE_UP_TO_128B = 0x7, 1856 MLX5_QPC_ATOMIC_MODE_UP_TO_256B = 0x8, 1857 }; 1858 1859 enum { 1860 MLX5_QPC_CS_REQ_DISABLE = 0x0, 1861 MLX5_QPC_CS_REQ_UP_TO_32B = 0x11, 1862 MLX5_QPC_CS_REQ_UP_TO_64B = 0x22, 1863 }; 1864 1865 enum { 1866 MLX5_QPC_CS_RES_DISABLE = 0x0, 1867 MLX5_QPC_CS_RES_UP_TO_32B = 0x1, 1868 MLX5_QPC_CS_RES_UP_TO_64B = 0x2, 1869 }; 1870 1871 struct mlx5_ifc_qpc_bits { 1872 u8 state[0x4]; 1873 u8 reserved_at_4[0x4]; 1874 u8 st[0x8]; 1875 u8 reserved_at_10[0x3]; 1876 u8 pm_state[0x2]; 1877 u8 reserved_at_15[0x7]; 1878 u8 end_padding_mode[0x2]; 1879 u8 reserved_at_1e[0x2]; 1880 1881 u8 wq_signature[0x1]; 1882 u8 block_lb_mc[0x1]; 1883 u8 atomic_like_write_en[0x1]; 1884 u8 latency_sensitive[0x1]; 1885 u8 reserved_at_24[0x1]; 1886 u8 drain_sigerr[0x1]; 1887 u8 reserved_at_26[0x2]; 1888 u8 pd[0x18]; 1889 1890 u8 mtu[0x3]; 1891 u8 log_msg_max[0x5]; 1892 u8 reserved_at_48[0x1]; 1893 u8 log_rq_size[0x4]; 1894 u8 log_rq_stride[0x3]; 1895 u8 no_sq[0x1]; 1896 u8 log_sq_size[0x4]; 1897 u8 reserved_at_55[0x6]; 1898 u8 rlky[0x1]; 1899 u8 ulp_stateless_offload_mode[0x4]; 1900 1901 u8 counter_set_id[0x8]; 1902 u8 uar_page[0x18]; 1903 1904 u8 reserved_at_80[0x8]; 1905 u8 user_index[0x18]; 1906 1907 u8 reserved_at_a0[0x3]; 1908 u8 log_page_size[0x5]; 1909 u8 remote_qpn[0x18]; 1910 1911 struct mlx5_ifc_ads_bits primary_address_path; 1912 1913 struct mlx5_ifc_ads_bits secondary_address_path; 1914 1915 u8 log_ack_req_freq[0x4]; 1916 u8 reserved_at_384[0x4]; 1917 u8 log_sra_max[0x3]; 1918 u8 reserved_at_38b[0x2]; 1919 u8 retry_count[0x3]; 1920 u8 rnr_retry[0x3]; 1921 u8 reserved_at_393[0x1]; 1922 u8 fre[0x1]; 1923 u8 cur_rnr_retry[0x3]; 1924 u8 cur_retry_count[0x3]; 1925 u8 reserved_at_39b[0x5]; 1926 1927 u8 reserved_at_3a0[0x20]; 1928 1929 u8 reserved_at_3c0[0x8]; 1930 u8 next_send_psn[0x18]; 1931 1932 u8 reserved_at_3e0[0x8]; 1933 u8 cqn_snd[0x18]; 1934 1935 u8 reserved_at_400[0x40]; 1936 1937 u8 reserved_at_440[0x8]; 1938 u8 last_acked_psn[0x18]; 1939 1940 u8 reserved_at_460[0x8]; 1941 u8 ssn[0x18]; 1942 1943 u8 reserved_at_480[0x8]; 1944 u8 log_rra_max[0x3]; 1945 u8 reserved_at_48b[0x1]; 1946 u8 atomic_mode[0x4]; 1947 u8 rre[0x1]; 1948 u8 rwe[0x1]; 1949 u8 rae[0x1]; 1950 u8 reserved_at_493[0x1]; 1951 u8 page_offset[0x6]; 1952 u8 reserved_at_49a[0x3]; 1953 u8 cd_slave_receive[0x1]; 1954 u8 cd_slave_send[0x1]; 1955 u8 cd_master[0x1]; 1956 1957 u8 reserved_at_4a0[0x3]; 1958 u8 min_rnr_nak[0x5]; 1959 u8 next_rcv_psn[0x18]; 1960 1961 u8 reserved_at_4c0[0x8]; 1962 u8 xrcd[0x18]; 1963 1964 u8 reserved_at_4e0[0x8]; 1965 u8 cqn_rcv[0x18]; 1966 1967 u8 dbr_addr[0x40]; 1968 1969 u8 q_key[0x20]; 1970 1971 u8 reserved_at_560[0x5]; 1972 u8 rq_type[0x3]; 1973 u8 srqn_rmpn[0x18]; 1974 1975 u8 reserved_at_580[0x8]; 1976 u8 rmsn[0x18]; 1977 1978 u8 hw_sq_wqebb_counter[0x10]; 1979 u8 sw_sq_wqebb_counter[0x10]; 1980 1981 u8 hw_rq_counter[0x20]; 1982 1983 u8 sw_rq_counter[0x20]; 1984 1985 u8 reserved_at_600[0x20]; 1986 1987 u8 reserved_at_620[0xf]; 1988 u8 cgs[0x1]; 1989 u8 cs_req[0x8]; 1990 u8 cs_res[0x8]; 1991 1992 u8 dc_access_key[0x40]; 1993 1994 u8 reserved_at_680[0xc0]; 1995 }; 1996 1997 struct mlx5_ifc_roce_addr_layout_bits { 1998 u8 source_l3_address[16][0x8]; 1999 2000 u8 reserved_at_80[0x3]; 2001 u8 vlan_valid[0x1]; 2002 u8 vlan_id[0xc]; 2003 u8 source_mac_47_32[0x10]; 2004 2005 u8 source_mac_31_0[0x20]; 2006 2007 u8 reserved_at_c0[0x14]; 2008 u8 roce_l3_type[0x4]; 2009 u8 roce_version[0x8]; 2010 2011 u8 reserved_at_e0[0x20]; 2012 }; 2013 2014 union mlx5_ifc_hca_cap_union_bits { 2015 struct mlx5_ifc_cmd_hca_cap_bits cmd_hca_cap; 2016 struct mlx5_ifc_odp_cap_bits odp_cap; 2017 struct mlx5_ifc_atomic_caps_bits atomic_caps; 2018 struct mlx5_ifc_roce_cap_bits roce_cap; 2019 struct mlx5_ifc_per_protocol_networking_offload_caps_bits per_protocol_networking_offload_caps; 2020 struct mlx5_ifc_flow_table_nic_cap_bits flow_table_nic_cap; 2021 struct mlx5_ifc_flow_table_eswitch_cap_bits flow_table_eswitch_cap; 2022 struct mlx5_ifc_e_switch_cap_bits e_switch_cap; 2023 struct mlx5_ifc_vector_calc_cap_bits vector_calc_cap; 2024 u8 reserved_at_0[0x8000]; 2025 }; 2026 2027 enum { 2028 MLX5_FLOW_CONTEXT_ACTION_ALLOW = 0x1, 2029 MLX5_FLOW_CONTEXT_ACTION_DROP = 0x2, 2030 MLX5_FLOW_CONTEXT_ACTION_FWD_DEST = 0x4, 2031 MLX5_FLOW_CONTEXT_ACTION_COUNT = 0x8, 2032 }; 2033 2034 struct mlx5_ifc_flow_context_bits { 2035 u8 reserved_at_0[0x20]; 2036 2037 u8 group_id[0x20]; 2038 2039 u8 reserved_at_40[0x8]; 2040 u8 flow_tag[0x18]; 2041 2042 u8 reserved_at_60[0x10]; 2043 u8 action[0x10]; 2044 2045 u8 reserved_at_80[0x8]; 2046 u8 destination_list_size[0x18]; 2047 2048 u8 reserved_at_a0[0x8]; 2049 u8 flow_counter_list_size[0x18]; 2050 2051 u8 reserved_at_c0[0x140]; 2052 2053 struct mlx5_ifc_fte_match_param_bits match_value; 2054 2055 u8 reserved_at_1200[0x600]; 2056 2057 union mlx5_ifc_dest_format_struct_flow_counter_list_auto_bits destination[0]; 2058 }; 2059 2060 enum { 2061 MLX5_XRC_SRQC_STATE_GOOD = 0x0, 2062 MLX5_XRC_SRQC_STATE_ERROR = 0x1, 2063 }; 2064 2065 struct mlx5_ifc_xrc_srqc_bits { 2066 u8 state[0x4]; 2067 u8 log_xrc_srq_size[0x4]; 2068 u8 reserved_at_8[0x18]; 2069 2070 u8 wq_signature[0x1]; 2071 u8 cont_srq[0x1]; 2072 u8 reserved_at_22[0x1]; 2073 u8 rlky[0x1]; 2074 u8 basic_cyclic_rcv_wqe[0x1]; 2075 u8 log_rq_stride[0x3]; 2076 u8 xrcd[0x18]; 2077 2078 u8 page_offset[0x6]; 2079 u8 reserved_at_46[0x2]; 2080 u8 cqn[0x18]; 2081 2082 u8 reserved_at_60[0x20]; 2083 2084 u8 user_index_equal_xrc_srqn[0x1]; 2085 u8 reserved_at_81[0x1]; 2086 u8 log_page_size[0x6]; 2087 u8 user_index[0x18]; 2088 2089 u8 reserved_at_a0[0x20]; 2090 2091 u8 reserved_at_c0[0x8]; 2092 u8 pd[0x18]; 2093 2094 u8 lwm[0x10]; 2095 u8 wqe_cnt[0x10]; 2096 2097 u8 reserved_at_100[0x40]; 2098 2099 u8 db_record_addr_h[0x20]; 2100 2101 u8 db_record_addr_l[0x1e]; 2102 u8 reserved_at_17e[0x2]; 2103 2104 u8 reserved_at_180[0x80]; 2105 }; 2106 2107 struct mlx5_ifc_traffic_counter_bits { 2108 u8 packets[0x40]; 2109 2110 u8 octets[0x40]; 2111 }; 2112 2113 struct mlx5_ifc_tisc_bits { 2114 u8 reserved_at_0[0xc]; 2115 u8 prio[0x4]; 2116 u8 reserved_at_10[0x10]; 2117 2118 u8 reserved_at_20[0x100]; 2119 2120 u8 reserved_at_120[0x8]; 2121 u8 transport_domain[0x18]; 2122 2123 u8 reserved_at_140[0x3c0]; 2124 }; 2125 2126 enum { 2127 MLX5_TIRC_DISP_TYPE_DIRECT = 0x0, 2128 MLX5_TIRC_DISP_TYPE_INDIRECT = 0x1, 2129 }; 2130 2131 enum { 2132 MLX5_TIRC_LRO_ENABLE_MASK_IPV4_LRO = 0x1, 2133 MLX5_TIRC_LRO_ENABLE_MASK_IPV6_LRO = 0x2, 2134 }; 2135 2136 enum { 2137 MLX5_RX_HASH_FN_NONE = 0x0, 2138 MLX5_RX_HASH_FN_INVERTED_XOR8 = 0x1, 2139 MLX5_RX_HASH_FN_TOEPLITZ = 0x2, 2140 }; 2141 2142 enum { 2143 MLX5_TIRC_SELF_LB_BLOCK_BLOCK_UNICAST_ = 0x1, 2144 MLX5_TIRC_SELF_LB_BLOCK_BLOCK_MULTICAST_ = 0x2, 2145 }; 2146 2147 struct mlx5_ifc_tirc_bits { 2148 u8 reserved_at_0[0x20]; 2149 2150 u8 disp_type[0x4]; 2151 u8 reserved_at_24[0x1c]; 2152 2153 u8 reserved_at_40[0x40]; 2154 2155 u8 reserved_at_80[0x4]; 2156 u8 lro_timeout_period_usecs[0x10]; 2157 u8 lro_enable_mask[0x4]; 2158 u8 lro_max_ip_payload_size[0x8]; 2159 2160 u8 reserved_at_a0[0x40]; 2161 2162 u8 reserved_at_e0[0x8]; 2163 u8 inline_rqn[0x18]; 2164 2165 u8 rx_hash_symmetric[0x1]; 2166 u8 reserved_at_101[0x1]; 2167 u8 tunneled_offload_en[0x1]; 2168 u8 reserved_at_103[0x5]; 2169 u8 indirect_table[0x18]; 2170 2171 u8 rx_hash_fn[0x4]; 2172 u8 reserved_at_124[0x2]; 2173 u8 self_lb_block[0x2]; 2174 u8 transport_domain[0x18]; 2175 2176 u8 rx_hash_toeplitz_key[10][0x20]; 2177 2178 struct mlx5_ifc_rx_hash_field_select_bits rx_hash_field_selector_outer; 2179 2180 struct mlx5_ifc_rx_hash_field_select_bits rx_hash_field_selector_inner; 2181 2182 u8 reserved_at_2c0[0x4c0]; 2183 }; 2184 2185 enum { 2186 MLX5_SRQC_STATE_GOOD = 0x0, 2187 MLX5_SRQC_STATE_ERROR = 0x1, 2188 }; 2189 2190 struct mlx5_ifc_srqc_bits { 2191 u8 state[0x4]; 2192 u8 log_srq_size[0x4]; 2193 u8 reserved_at_8[0x18]; 2194 2195 u8 wq_signature[0x1]; 2196 u8 cont_srq[0x1]; 2197 u8 reserved_at_22[0x1]; 2198 u8 rlky[0x1]; 2199 u8 reserved_at_24[0x1]; 2200 u8 log_rq_stride[0x3]; 2201 u8 xrcd[0x18]; 2202 2203 u8 page_offset[0x6]; 2204 u8 reserved_at_46[0x2]; 2205 u8 cqn[0x18]; 2206 2207 u8 reserved_at_60[0x20]; 2208 2209 u8 reserved_at_80[0x2]; 2210 u8 log_page_size[0x6]; 2211 u8 reserved_at_88[0x18]; 2212 2213 u8 reserved_at_a0[0x20]; 2214 2215 u8 reserved_at_c0[0x8]; 2216 u8 pd[0x18]; 2217 2218 u8 lwm[0x10]; 2219 u8 wqe_cnt[0x10]; 2220 2221 u8 reserved_at_100[0x40]; 2222 2223 u8 dbr_addr[0x40]; 2224 2225 u8 reserved_at_180[0x80]; 2226 }; 2227 2228 enum { 2229 MLX5_SQC_STATE_RST = 0x0, 2230 MLX5_SQC_STATE_RDY = 0x1, 2231 MLX5_SQC_STATE_ERR = 0x3, 2232 }; 2233 2234 struct mlx5_ifc_sqc_bits { 2235 u8 rlky[0x1]; 2236 u8 cd_master[0x1]; 2237 u8 fre[0x1]; 2238 u8 flush_in_error_en[0x1]; 2239 u8 reserved_at_4[0x4]; 2240 u8 state[0x4]; 2241 u8 reg_umr[0x1]; 2242 u8 reserved_at_d[0x13]; 2243 2244 u8 reserved_at_20[0x8]; 2245 u8 user_index[0x18]; 2246 2247 u8 reserved_at_40[0x8]; 2248 u8 cqn[0x18]; 2249 2250 u8 reserved_at_60[0xa0]; 2251 2252 u8 tis_lst_sz[0x10]; 2253 u8 reserved_at_110[0x10]; 2254 2255 u8 reserved_at_120[0x40]; 2256 2257 u8 reserved_at_160[0x8]; 2258 u8 tis_num_0[0x18]; 2259 2260 struct mlx5_ifc_wq_bits wq; 2261 }; 2262 2263 struct mlx5_ifc_rqtc_bits { 2264 u8 reserved_at_0[0xa0]; 2265 2266 u8 reserved_at_a0[0x10]; 2267 u8 rqt_max_size[0x10]; 2268 2269 u8 reserved_at_c0[0x10]; 2270 u8 rqt_actual_size[0x10]; 2271 2272 u8 reserved_at_e0[0x6a0]; 2273 2274 struct mlx5_ifc_rq_num_bits rq_num[0]; 2275 }; 2276 2277 enum { 2278 MLX5_RQC_MEM_RQ_TYPE_MEMORY_RQ_INLINE = 0x0, 2279 MLX5_RQC_MEM_RQ_TYPE_MEMORY_RQ_RMP = 0x1, 2280 }; 2281 2282 enum { 2283 MLX5_RQC_STATE_RST = 0x0, 2284 MLX5_RQC_STATE_RDY = 0x1, 2285 MLX5_RQC_STATE_ERR = 0x3, 2286 }; 2287 2288 struct mlx5_ifc_rqc_bits { 2289 u8 rlky[0x1]; 2290 u8 reserved_at_1[0x1]; 2291 u8 scatter_fcs[0x1]; 2292 u8 vsd[0x1]; 2293 u8 mem_rq_type[0x4]; 2294 u8 state[0x4]; 2295 u8 reserved_at_c[0x1]; 2296 u8 flush_in_error_en[0x1]; 2297 u8 reserved_at_e[0x12]; 2298 2299 u8 reserved_at_20[0x8]; 2300 u8 user_index[0x18]; 2301 2302 u8 reserved_at_40[0x8]; 2303 u8 cqn[0x18]; 2304 2305 u8 counter_set_id[0x8]; 2306 u8 reserved_at_68[0x18]; 2307 2308 u8 reserved_at_80[0x8]; 2309 u8 rmpn[0x18]; 2310 2311 u8 reserved_at_a0[0xe0]; 2312 2313 struct mlx5_ifc_wq_bits wq; 2314 }; 2315 2316 enum { 2317 MLX5_RMPC_STATE_RDY = 0x1, 2318 MLX5_RMPC_STATE_ERR = 0x3, 2319 }; 2320 2321 struct mlx5_ifc_rmpc_bits { 2322 u8 reserved_at_0[0x8]; 2323 u8 state[0x4]; 2324 u8 reserved_at_c[0x14]; 2325 2326 u8 basic_cyclic_rcv_wqe[0x1]; 2327 u8 reserved_at_21[0x1f]; 2328 2329 u8 reserved_at_40[0x140]; 2330 2331 struct mlx5_ifc_wq_bits wq; 2332 }; 2333 2334 struct mlx5_ifc_nic_vport_context_bits { 2335 u8 reserved_at_0[0x1f]; 2336 u8 roce_en[0x1]; 2337 2338 u8 arm_change_event[0x1]; 2339 u8 reserved_at_21[0x1a]; 2340 u8 event_on_mtu[0x1]; 2341 u8 event_on_promisc_change[0x1]; 2342 u8 event_on_vlan_change[0x1]; 2343 u8 event_on_mc_address_change[0x1]; 2344 u8 event_on_uc_address_change[0x1]; 2345 2346 u8 reserved_at_40[0xf0]; 2347 2348 u8 mtu[0x10]; 2349 2350 u8 system_image_guid[0x40]; 2351 u8 port_guid[0x40]; 2352 u8 node_guid[0x40]; 2353 2354 u8 reserved_at_200[0x140]; 2355 u8 qkey_violation_counter[0x10]; 2356 u8 reserved_at_350[0x430]; 2357 2358 u8 promisc_uc[0x1]; 2359 u8 promisc_mc[0x1]; 2360 u8 promisc_all[0x1]; 2361 u8 reserved_at_783[0x2]; 2362 u8 allowed_list_type[0x3]; 2363 u8 reserved_at_788[0xc]; 2364 u8 allowed_list_size[0xc]; 2365 2366 struct mlx5_ifc_mac_address_layout_bits permanent_address; 2367 2368 u8 reserved_at_7e0[0x20]; 2369 2370 u8 current_uc_mac_address[0][0x40]; 2371 }; 2372 2373 enum { 2374 MLX5_MKC_ACCESS_MODE_PA = 0x0, 2375 MLX5_MKC_ACCESS_MODE_MTT = 0x1, 2376 MLX5_MKC_ACCESS_MODE_KLMS = 0x2, 2377 }; 2378 2379 struct mlx5_ifc_mkc_bits { 2380 u8 reserved_at_0[0x1]; 2381 u8 free[0x1]; 2382 u8 reserved_at_2[0xd]; 2383 u8 small_fence_on_rdma_read_response[0x1]; 2384 u8 umr_en[0x1]; 2385 u8 a[0x1]; 2386 u8 rw[0x1]; 2387 u8 rr[0x1]; 2388 u8 lw[0x1]; 2389 u8 lr[0x1]; 2390 u8 access_mode[0x2]; 2391 u8 reserved_at_18[0x8]; 2392 2393 u8 qpn[0x18]; 2394 u8 mkey_7_0[0x8]; 2395 2396 u8 reserved_at_40[0x20]; 2397 2398 u8 length64[0x1]; 2399 u8 bsf_en[0x1]; 2400 u8 sync_umr[0x1]; 2401 u8 reserved_at_63[0x2]; 2402 u8 expected_sigerr_count[0x1]; 2403 u8 reserved_at_66[0x1]; 2404 u8 en_rinval[0x1]; 2405 u8 pd[0x18]; 2406 2407 u8 start_addr[0x40]; 2408 2409 u8 len[0x40]; 2410 2411 u8 bsf_octword_size[0x20]; 2412 2413 u8 reserved_at_120[0x80]; 2414 2415 u8 translations_octword_size[0x20]; 2416 2417 u8 reserved_at_1c0[0x1b]; 2418 u8 log_page_size[0x5]; 2419 2420 u8 reserved_at_1e0[0x20]; 2421 }; 2422 2423 struct mlx5_ifc_pkey_bits { 2424 u8 reserved_at_0[0x10]; 2425 u8 pkey[0x10]; 2426 }; 2427 2428 struct mlx5_ifc_array128_auto_bits { 2429 u8 array128_auto[16][0x8]; 2430 }; 2431 2432 struct mlx5_ifc_hca_vport_context_bits { 2433 u8 field_select[0x20]; 2434 2435 u8 reserved_at_20[0xe0]; 2436 2437 u8 sm_virt_aware[0x1]; 2438 u8 has_smi[0x1]; 2439 u8 has_raw[0x1]; 2440 u8 grh_required[0x1]; 2441 u8 reserved_at_104[0xc]; 2442 u8 port_physical_state[0x4]; 2443 u8 vport_state_policy[0x4]; 2444 u8 port_state[0x4]; 2445 u8 vport_state[0x4]; 2446 2447 u8 reserved_at_120[0x20]; 2448 2449 u8 system_image_guid[0x40]; 2450 2451 u8 port_guid[0x40]; 2452 2453 u8 node_guid[0x40]; 2454 2455 u8 cap_mask1[0x20]; 2456 2457 u8 cap_mask1_field_select[0x20]; 2458 2459 u8 cap_mask2[0x20]; 2460 2461 u8 cap_mask2_field_select[0x20]; 2462 2463 u8 reserved_at_280[0x80]; 2464 2465 u8 lid[0x10]; 2466 u8 reserved_at_310[0x4]; 2467 u8 init_type_reply[0x4]; 2468 u8 lmc[0x3]; 2469 u8 subnet_timeout[0x5]; 2470 2471 u8 sm_lid[0x10]; 2472 u8 sm_sl[0x4]; 2473 u8 reserved_at_334[0xc]; 2474 2475 u8 qkey_violation_counter[0x10]; 2476 u8 pkey_violation_counter[0x10]; 2477 2478 u8 reserved_at_360[0xca0]; 2479 }; 2480 2481 struct mlx5_ifc_esw_vport_context_bits { 2482 u8 reserved_at_0[0x3]; 2483 u8 vport_svlan_strip[0x1]; 2484 u8 vport_cvlan_strip[0x1]; 2485 u8 vport_svlan_insert[0x1]; 2486 u8 vport_cvlan_insert[0x2]; 2487 u8 reserved_at_8[0x18]; 2488 2489 u8 reserved_at_20[0x20]; 2490 2491 u8 svlan_cfi[0x1]; 2492 u8 svlan_pcp[0x3]; 2493 u8 svlan_id[0xc]; 2494 u8 cvlan_cfi[0x1]; 2495 u8 cvlan_pcp[0x3]; 2496 u8 cvlan_id[0xc]; 2497 2498 u8 reserved_at_60[0x7a0]; 2499 }; 2500 2501 enum { 2502 MLX5_EQC_STATUS_OK = 0x0, 2503 MLX5_EQC_STATUS_EQ_WRITE_FAILURE = 0xa, 2504 }; 2505 2506 enum { 2507 MLX5_EQC_ST_ARMED = 0x9, 2508 MLX5_EQC_ST_FIRED = 0xa, 2509 }; 2510 2511 struct mlx5_ifc_eqc_bits { 2512 u8 status[0x4]; 2513 u8 reserved_at_4[0x9]; 2514 u8 ec[0x1]; 2515 u8 oi[0x1]; 2516 u8 reserved_at_f[0x5]; 2517 u8 st[0x4]; 2518 u8 reserved_at_18[0x8]; 2519 2520 u8 reserved_at_20[0x20]; 2521 2522 u8 reserved_at_40[0x14]; 2523 u8 page_offset[0x6]; 2524 u8 reserved_at_5a[0x6]; 2525 2526 u8 reserved_at_60[0x3]; 2527 u8 log_eq_size[0x5]; 2528 u8 uar_page[0x18]; 2529 2530 u8 reserved_at_80[0x20]; 2531 2532 u8 reserved_at_a0[0x18]; 2533 u8 intr[0x8]; 2534 2535 u8 reserved_at_c0[0x3]; 2536 u8 log_page_size[0x5]; 2537 u8 reserved_at_c8[0x18]; 2538 2539 u8 reserved_at_e0[0x60]; 2540 2541 u8 reserved_at_140[0x8]; 2542 u8 consumer_counter[0x18]; 2543 2544 u8 reserved_at_160[0x8]; 2545 u8 producer_counter[0x18]; 2546 2547 u8 reserved_at_180[0x80]; 2548 }; 2549 2550 enum { 2551 MLX5_DCTC_STATE_ACTIVE = 0x0, 2552 MLX5_DCTC_STATE_DRAINING = 0x1, 2553 MLX5_DCTC_STATE_DRAINED = 0x2, 2554 }; 2555 2556 enum { 2557 MLX5_DCTC_CS_RES_DISABLE = 0x0, 2558 MLX5_DCTC_CS_RES_NA = 0x1, 2559 MLX5_DCTC_CS_RES_UP_TO_64B = 0x2, 2560 }; 2561 2562 enum { 2563 MLX5_DCTC_MTU_256_BYTES = 0x1, 2564 MLX5_DCTC_MTU_512_BYTES = 0x2, 2565 MLX5_DCTC_MTU_1K_BYTES = 0x3, 2566 MLX5_DCTC_MTU_2K_BYTES = 0x4, 2567 MLX5_DCTC_MTU_4K_BYTES = 0x5, 2568 }; 2569 2570 struct mlx5_ifc_dctc_bits { 2571 u8 reserved_at_0[0x4]; 2572 u8 state[0x4]; 2573 u8 reserved_at_8[0x18]; 2574 2575 u8 reserved_at_20[0x8]; 2576 u8 user_index[0x18]; 2577 2578 u8 reserved_at_40[0x8]; 2579 u8 cqn[0x18]; 2580 2581 u8 counter_set_id[0x8]; 2582 u8 atomic_mode[0x4]; 2583 u8 rre[0x1]; 2584 u8 rwe[0x1]; 2585 u8 rae[0x1]; 2586 u8 atomic_like_write_en[0x1]; 2587 u8 latency_sensitive[0x1]; 2588 u8 rlky[0x1]; 2589 u8 free_ar[0x1]; 2590 u8 reserved_at_73[0xd]; 2591 2592 u8 reserved_at_80[0x8]; 2593 u8 cs_res[0x8]; 2594 u8 reserved_at_90[0x3]; 2595 u8 min_rnr_nak[0x5]; 2596 u8 reserved_at_98[0x8]; 2597 2598 u8 reserved_at_a0[0x8]; 2599 u8 srqn[0x18]; 2600 2601 u8 reserved_at_c0[0x8]; 2602 u8 pd[0x18]; 2603 2604 u8 tclass[0x8]; 2605 u8 reserved_at_e8[0x4]; 2606 u8 flow_label[0x14]; 2607 2608 u8 dc_access_key[0x40]; 2609 2610 u8 reserved_at_140[0x5]; 2611 u8 mtu[0x3]; 2612 u8 port[0x8]; 2613 u8 pkey_index[0x10]; 2614 2615 u8 reserved_at_160[0x8]; 2616 u8 my_addr_index[0x8]; 2617 u8 reserved_at_170[0x8]; 2618 u8 hop_limit[0x8]; 2619 2620 u8 dc_access_key_violation_count[0x20]; 2621 2622 u8 reserved_at_1a0[0x14]; 2623 u8 dei_cfi[0x1]; 2624 u8 eth_prio[0x3]; 2625 u8 ecn[0x2]; 2626 u8 dscp[0x6]; 2627 2628 u8 reserved_at_1c0[0x40]; 2629 }; 2630 2631 enum { 2632 MLX5_CQC_STATUS_OK = 0x0, 2633 MLX5_CQC_STATUS_CQ_OVERFLOW = 0x9, 2634 MLX5_CQC_STATUS_CQ_WRITE_FAIL = 0xa, 2635 }; 2636 2637 enum { 2638 MLX5_CQC_CQE_SZ_64_BYTES = 0x0, 2639 MLX5_CQC_CQE_SZ_128_BYTES = 0x1, 2640 }; 2641 2642 enum { 2643 MLX5_CQC_ST_SOLICITED_NOTIFICATION_REQUEST_ARMED = 0x6, 2644 MLX5_CQC_ST_NOTIFICATION_REQUEST_ARMED = 0x9, 2645 MLX5_CQC_ST_FIRED = 0xa, 2646 }; 2647 2648 enum { 2649 MLX5_CQ_PERIOD_MODE_START_FROM_EQE = 0x0, 2650 MLX5_CQ_PERIOD_MODE_START_FROM_CQE = 0x1, 2651 }; 2652 2653 struct mlx5_ifc_cqc_bits { 2654 u8 status[0x4]; 2655 u8 reserved_at_4[0x4]; 2656 u8 cqe_sz[0x3]; 2657 u8 cc[0x1]; 2658 u8 reserved_at_c[0x1]; 2659 u8 scqe_break_moderation_en[0x1]; 2660 u8 oi[0x1]; 2661 u8 cq_period_mode[0x2]; 2662 u8 cqe_comp_en[0x1]; 2663 u8 mini_cqe_res_format[0x2]; 2664 u8 st[0x4]; 2665 u8 reserved_at_18[0x8]; 2666 2667 u8 reserved_at_20[0x20]; 2668 2669 u8 reserved_at_40[0x14]; 2670 u8 page_offset[0x6]; 2671 u8 reserved_at_5a[0x6]; 2672 2673 u8 reserved_at_60[0x3]; 2674 u8 log_cq_size[0x5]; 2675 u8 uar_page[0x18]; 2676 2677 u8 reserved_at_80[0x4]; 2678 u8 cq_period[0xc]; 2679 u8 cq_max_count[0x10]; 2680 2681 u8 reserved_at_a0[0x18]; 2682 u8 c_eqn[0x8]; 2683 2684 u8 reserved_at_c0[0x3]; 2685 u8 log_page_size[0x5]; 2686 u8 reserved_at_c8[0x18]; 2687 2688 u8 reserved_at_e0[0x20]; 2689 2690 u8 reserved_at_100[0x8]; 2691 u8 last_notified_index[0x18]; 2692 2693 u8 reserved_at_120[0x8]; 2694 u8 last_solicit_index[0x18]; 2695 2696 u8 reserved_at_140[0x8]; 2697 u8 consumer_counter[0x18]; 2698 2699 u8 reserved_at_160[0x8]; 2700 u8 producer_counter[0x18]; 2701 2702 u8 reserved_at_180[0x40]; 2703 2704 u8 dbr_addr[0x40]; 2705 }; 2706 2707 union mlx5_ifc_cong_control_roce_ecn_auto_bits { 2708 struct mlx5_ifc_cong_control_802_1qau_rp_bits cong_control_802_1qau_rp; 2709 struct mlx5_ifc_cong_control_r_roce_ecn_rp_bits cong_control_r_roce_ecn_rp; 2710 struct mlx5_ifc_cong_control_r_roce_ecn_np_bits cong_control_r_roce_ecn_np; 2711 u8 reserved_at_0[0x800]; 2712 }; 2713 2714 struct mlx5_ifc_query_adapter_param_block_bits { 2715 u8 reserved_at_0[0xc0]; 2716 2717 u8 reserved_at_c0[0x8]; 2718 u8 ieee_vendor_id[0x18]; 2719 2720 u8 reserved_at_e0[0x10]; 2721 u8 vsd_vendor_id[0x10]; 2722 2723 u8 vsd[208][0x8]; 2724 2725 u8 vsd_contd_psid[16][0x8]; 2726 }; 2727 2728 union mlx5_ifc_modify_field_select_resize_field_select_auto_bits { 2729 struct mlx5_ifc_modify_field_select_bits modify_field_select; 2730 struct mlx5_ifc_resize_field_select_bits resize_field_select; 2731 u8 reserved_at_0[0x20]; 2732 }; 2733 2734 union mlx5_ifc_field_select_802_1_r_roce_auto_bits { 2735 struct mlx5_ifc_field_select_802_1qau_rp_bits field_select_802_1qau_rp; 2736 struct mlx5_ifc_field_select_r_roce_rp_bits field_select_r_roce_rp; 2737 struct mlx5_ifc_field_select_r_roce_np_bits field_select_r_roce_np; 2738 u8 reserved_at_0[0x20]; 2739 }; 2740 2741 union mlx5_ifc_eth_cntrs_grp_data_layout_auto_bits { 2742 struct mlx5_ifc_eth_802_3_cntrs_grp_data_layout_bits eth_802_3_cntrs_grp_data_layout; 2743 struct mlx5_ifc_eth_2863_cntrs_grp_data_layout_bits eth_2863_cntrs_grp_data_layout; 2744 struct mlx5_ifc_eth_2819_cntrs_grp_data_layout_bits eth_2819_cntrs_grp_data_layout; 2745 struct mlx5_ifc_eth_3635_cntrs_grp_data_layout_bits eth_3635_cntrs_grp_data_layout; 2746 struct mlx5_ifc_eth_extended_cntrs_grp_data_layout_bits eth_extended_cntrs_grp_data_layout; 2747 struct mlx5_ifc_eth_per_prio_grp_data_layout_bits eth_per_prio_grp_data_layout; 2748 struct mlx5_ifc_eth_per_traffic_grp_data_layout_bits eth_per_traffic_grp_data_layout; 2749 struct mlx5_ifc_ib_port_cntrs_grp_data_layout_bits ib_port_cntrs_grp_data_layout; 2750 struct mlx5_ifc_phys_layer_cntrs_bits phys_layer_cntrs; 2751 u8 reserved_at_0[0x7c0]; 2752 }; 2753 2754 union mlx5_ifc_event_auto_bits { 2755 struct mlx5_ifc_comp_event_bits comp_event; 2756 struct mlx5_ifc_dct_events_bits dct_events; 2757 struct mlx5_ifc_qp_events_bits qp_events; 2758 struct mlx5_ifc_wqe_associated_page_fault_event_bits wqe_associated_page_fault_event; 2759 struct mlx5_ifc_rdma_page_fault_event_bits rdma_page_fault_event; 2760 struct mlx5_ifc_cq_error_bits cq_error; 2761 struct mlx5_ifc_dropped_packet_logged_bits dropped_packet_logged; 2762 struct mlx5_ifc_port_state_change_event_bits port_state_change_event; 2763 struct mlx5_ifc_gpio_event_bits gpio_event; 2764 struct mlx5_ifc_db_bf_congestion_event_bits db_bf_congestion_event; 2765 struct mlx5_ifc_stall_vl_event_bits stall_vl_event; 2766 struct mlx5_ifc_cmd_inter_comp_event_bits cmd_inter_comp_event; 2767 u8 reserved_at_0[0xe0]; 2768 }; 2769 2770 struct mlx5_ifc_health_buffer_bits { 2771 u8 reserved_at_0[0x100]; 2772 2773 u8 assert_existptr[0x20]; 2774 2775 u8 assert_callra[0x20]; 2776 2777 u8 reserved_at_140[0x40]; 2778 2779 u8 fw_version[0x20]; 2780 2781 u8 hw_id[0x20]; 2782 2783 u8 reserved_at_1c0[0x20]; 2784 2785 u8 irisc_index[0x8]; 2786 u8 synd[0x8]; 2787 u8 ext_synd[0x10]; 2788 }; 2789 2790 struct mlx5_ifc_register_loopback_control_bits { 2791 u8 no_lb[0x1]; 2792 u8 reserved_at_1[0x7]; 2793 u8 port[0x8]; 2794 u8 reserved_at_10[0x10]; 2795 2796 u8 reserved_at_20[0x60]; 2797 }; 2798 2799 struct mlx5_ifc_teardown_hca_out_bits { 2800 u8 status[0x8]; 2801 u8 reserved_at_8[0x18]; 2802 2803 u8 syndrome[0x20]; 2804 2805 u8 reserved_at_40[0x40]; 2806 }; 2807 2808 enum { 2809 MLX5_TEARDOWN_HCA_IN_PROFILE_GRACEFUL_CLOSE = 0x0, 2810 MLX5_TEARDOWN_HCA_IN_PROFILE_PANIC_CLOSE = 0x1, 2811 }; 2812 2813 struct mlx5_ifc_teardown_hca_in_bits { 2814 u8 opcode[0x10]; 2815 u8 reserved_at_10[0x10]; 2816 2817 u8 reserved_at_20[0x10]; 2818 u8 op_mod[0x10]; 2819 2820 u8 reserved_at_40[0x10]; 2821 u8 profile[0x10]; 2822 2823 u8 reserved_at_60[0x20]; 2824 }; 2825 2826 struct mlx5_ifc_sqerr2rts_qp_out_bits { 2827 u8 status[0x8]; 2828 u8 reserved_at_8[0x18]; 2829 2830 u8 syndrome[0x20]; 2831 2832 u8 reserved_at_40[0x40]; 2833 }; 2834 2835 struct mlx5_ifc_sqerr2rts_qp_in_bits { 2836 u8 opcode[0x10]; 2837 u8 reserved_at_10[0x10]; 2838 2839 u8 reserved_at_20[0x10]; 2840 u8 op_mod[0x10]; 2841 2842 u8 reserved_at_40[0x8]; 2843 u8 qpn[0x18]; 2844 2845 u8 reserved_at_60[0x20]; 2846 2847 u8 opt_param_mask[0x20]; 2848 2849 u8 reserved_at_a0[0x20]; 2850 2851 struct mlx5_ifc_qpc_bits qpc; 2852 2853 u8 reserved_at_800[0x80]; 2854 }; 2855 2856 struct mlx5_ifc_sqd2rts_qp_out_bits { 2857 u8 status[0x8]; 2858 u8 reserved_at_8[0x18]; 2859 2860 u8 syndrome[0x20]; 2861 2862 u8 reserved_at_40[0x40]; 2863 }; 2864 2865 struct mlx5_ifc_sqd2rts_qp_in_bits { 2866 u8 opcode[0x10]; 2867 u8 reserved_at_10[0x10]; 2868 2869 u8 reserved_at_20[0x10]; 2870 u8 op_mod[0x10]; 2871 2872 u8 reserved_at_40[0x8]; 2873 u8 qpn[0x18]; 2874 2875 u8 reserved_at_60[0x20]; 2876 2877 u8 opt_param_mask[0x20]; 2878 2879 u8 reserved_at_a0[0x20]; 2880 2881 struct mlx5_ifc_qpc_bits qpc; 2882 2883 u8 reserved_at_800[0x80]; 2884 }; 2885 2886 struct mlx5_ifc_set_roce_address_out_bits { 2887 u8 status[0x8]; 2888 u8 reserved_at_8[0x18]; 2889 2890 u8 syndrome[0x20]; 2891 2892 u8 reserved_at_40[0x40]; 2893 }; 2894 2895 struct mlx5_ifc_set_roce_address_in_bits { 2896 u8 opcode[0x10]; 2897 u8 reserved_at_10[0x10]; 2898 2899 u8 reserved_at_20[0x10]; 2900 u8 op_mod[0x10]; 2901 2902 u8 roce_address_index[0x10]; 2903 u8 reserved_at_50[0x10]; 2904 2905 u8 reserved_at_60[0x20]; 2906 2907 struct mlx5_ifc_roce_addr_layout_bits roce_address; 2908 }; 2909 2910 struct mlx5_ifc_set_mad_demux_out_bits { 2911 u8 status[0x8]; 2912 u8 reserved_at_8[0x18]; 2913 2914 u8 syndrome[0x20]; 2915 2916 u8 reserved_at_40[0x40]; 2917 }; 2918 2919 enum { 2920 MLX5_SET_MAD_DEMUX_IN_DEMUX_MODE_PASS_ALL = 0x0, 2921 MLX5_SET_MAD_DEMUX_IN_DEMUX_MODE_SELECTIVE = 0x2, 2922 }; 2923 2924 struct mlx5_ifc_set_mad_demux_in_bits { 2925 u8 opcode[0x10]; 2926 u8 reserved_at_10[0x10]; 2927 2928 u8 reserved_at_20[0x10]; 2929 u8 op_mod[0x10]; 2930 2931 u8 reserved_at_40[0x20]; 2932 2933 u8 reserved_at_60[0x6]; 2934 u8 demux_mode[0x2]; 2935 u8 reserved_at_68[0x18]; 2936 }; 2937 2938 struct mlx5_ifc_set_l2_table_entry_out_bits { 2939 u8 status[0x8]; 2940 u8 reserved_at_8[0x18]; 2941 2942 u8 syndrome[0x20]; 2943 2944 u8 reserved_at_40[0x40]; 2945 }; 2946 2947 struct mlx5_ifc_set_l2_table_entry_in_bits { 2948 u8 opcode[0x10]; 2949 u8 reserved_at_10[0x10]; 2950 2951 u8 reserved_at_20[0x10]; 2952 u8 op_mod[0x10]; 2953 2954 u8 reserved_at_40[0x60]; 2955 2956 u8 reserved_at_a0[0x8]; 2957 u8 table_index[0x18]; 2958 2959 u8 reserved_at_c0[0x20]; 2960 2961 u8 reserved_at_e0[0x13]; 2962 u8 vlan_valid[0x1]; 2963 u8 vlan[0xc]; 2964 2965 struct mlx5_ifc_mac_address_layout_bits mac_address; 2966 2967 u8 reserved_at_140[0xc0]; 2968 }; 2969 2970 struct mlx5_ifc_set_issi_out_bits { 2971 u8 status[0x8]; 2972 u8 reserved_at_8[0x18]; 2973 2974 u8 syndrome[0x20]; 2975 2976 u8 reserved_at_40[0x40]; 2977 }; 2978 2979 struct mlx5_ifc_set_issi_in_bits { 2980 u8 opcode[0x10]; 2981 u8 reserved_at_10[0x10]; 2982 2983 u8 reserved_at_20[0x10]; 2984 u8 op_mod[0x10]; 2985 2986 u8 reserved_at_40[0x10]; 2987 u8 current_issi[0x10]; 2988 2989 u8 reserved_at_60[0x20]; 2990 }; 2991 2992 struct mlx5_ifc_set_hca_cap_out_bits { 2993 u8 status[0x8]; 2994 u8 reserved_at_8[0x18]; 2995 2996 u8 syndrome[0x20]; 2997 2998 u8 reserved_at_40[0x40]; 2999 }; 3000 3001 struct mlx5_ifc_set_hca_cap_in_bits { 3002 u8 opcode[0x10]; 3003 u8 reserved_at_10[0x10]; 3004 3005 u8 reserved_at_20[0x10]; 3006 u8 op_mod[0x10]; 3007 3008 u8 reserved_at_40[0x40]; 3009 3010 union mlx5_ifc_hca_cap_union_bits capability; 3011 }; 3012 3013 enum { 3014 MLX5_SET_FTE_MODIFY_ENABLE_MASK_ACTION = 0x0, 3015 MLX5_SET_FTE_MODIFY_ENABLE_MASK_FLOW_TAG = 0x1, 3016 MLX5_SET_FTE_MODIFY_ENABLE_MASK_DESTINATION_LIST = 0x2, 3017 MLX5_SET_FTE_MODIFY_ENABLE_MASK_FLOW_COUNTERS = 0x3 3018 }; 3019 3020 struct mlx5_ifc_set_fte_out_bits { 3021 u8 status[0x8]; 3022 u8 reserved_at_8[0x18]; 3023 3024 u8 syndrome[0x20]; 3025 3026 u8 reserved_at_40[0x40]; 3027 }; 3028 3029 struct mlx5_ifc_set_fte_in_bits { 3030 u8 opcode[0x10]; 3031 u8 reserved_at_10[0x10]; 3032 3033 u8 reserved_at_20[0x10]; 3034 u8 op_mod[0x10]; 3035 3036 u8 other_vport[0x1]; 3037 u8 reserved_at_41[0xf]; 3038 u8 vport_number[0x10]; 3039 3040 u8 reserved_at_60[0x20]; 3041 3042 u8 table_type[0x8]; 3043 u8 reserved_at_88[0x18]; 3044 3045 u8 reserved_at_a0[0x8]; 3046 u8 table_id[0x18]; 3047 3048 u8 reserved_at_c0[0x18]; 3049 u8 modify_enable_mask[0x8]; 3050 3051 u8 reserved_at_e0[0x20]; 3052 3053 u8 flow_index[0x20]; 3054 3055 u8 reserved_at_120[0xe0]; 3056 3057 struct mlx5_ifc_flow_context_bits flow_context; 3058 }; 3059 3060 struct mlx5_ifc_rts2rts_qp_out_bits { 3061 u8 status[0x8]; 3062 u8 reserved_at_8[0x18]; 3063 3064 u8 syndrome[0x20]; 3065 3066 u8 reserved_at_40[0x40]; 3067 }; 3068 3069 struct mlx5_ifc_rts2rts_qp_in_bits { 3070 u8 opcode[0x10]; 3071 u8 reserved_at_10[0x10]; 3072 3073 u8 reserved_at_20[0x10]; 3074 u8 op_mod[0x10]; 3075 3076 u8 reserved_at_40[0x8]; 3077 u8 qpn[0x18]; 3078 3079 u8 reserved_at_60[0x20]; 3080 3081 u8 opt_param_mask[0x20]; 3082 3083 u8 reserved_at_a0[0x20]; 3084 3085 struct mlx5_ifc_qpc_bits qpc; 3086 3087 u8 reserved_at_800[0x80]; 3088 }; 3089 3090 struct mlx5_ifc_rtr2rts_qp_out_bits { 3091 u8 status[0x8]; 3092 u8 reserved_at_8[0x18]; 3093 3094 u8 syndrome[0x20]; 3095 3096 u8 reserved_at_40[0x40]; 3097 }; 3098 3099 struct mlx5_ifc_rtr2rts_qp_in_bits { 3100 u8 opcode[0x10]; 3101 u8 reserved_at_10[0x10]; 3102 3103 u8 reserved_at_20[0x10]; 3104 u8 op_mod[0x10]; 3105 3106 u8 reserved_at_40[0x8]; 3107 u8 qpn[0x18]; 3108 3109 u8 reserved_at_60[0x20]; 3110 3111 u8 opt_param_mask[0x20]; 3112 3113 u8 reserved_at_a0[0x20]; 3114 3115 struct mlx5_ifc_qpc_bits qpc; 3116 3117 u8 reserved_at_800[0x80]; 3118 }; 3119 3120 struct mlx5_ifc_rst2init_qp_out_bits { 3121 u8 status[0x8]; 3122 u8 reserved_at_8[0x18]; 3123 3124 u8 syndrome[0x20]; 3125 3126 u8 reserved_at_40[0x40]; 3127 }; 3128 3129 struct mlx5_ifc_rst2init_qp_in_bits { 3130 u8 opcode[0x10]; 3131 u8 reserved_at_10[0x10]; 3132 3133 u8 reserved_at_20[0x10]; 3134 u8 op_mod[0x10]; 3135 3136 u8 reserved_at_40[0x8]; 3137 u8 qpn[0x18]; 3138 3139 u8 reserved_at_60[0x20]; 3140 3141 u8 opt_param_mask[0x20]; 3142 3143 u8 reserved_at_a0[0x20]; 3144 3145 struct mlx5_ifc_qpc_bits qpc; 3146 3147 u8 reserved_at_800[0x80]; 3148 }; 3149 3150 struct mlx5_ifc_query_xrc_srq_out_bits { 3151 u8 status[0x8]; 3152 u8 reserved_at_8[0x18]; 3153 3154 u8 syndrome[0x20]; 3155 3156 u8 reserved_at_40[0x40]; 3157 3158 struct mlx5_ifc_xrc_srqc_bits xrc_srq_context_entry; 3159 3160 u8 reserved_at_280[0x600]; 3161 3162 u8 pas[0][0x40]; 3163 }; 3164 3165 struct mlx5_ifc_query_xrc_srq_in_bits { 3166 u8 opcode[0x10]; 3167 u8 reserved_at_10[0x10]; 3168 3169 u8 reserved_at_20[0x10]; 3170 u8 op_mod[0x10]; 3171 3172 u8 reserved_at_40[0x8]; 3173 u8 xrc_srqn[0x18]; 3174 3175 u8 reserved_at_60[0x20]; 3176 }; 3177 3178 enum { 3179 MLX5_QUERY_VPORT_STATE_OUT_STATE_DOWN = 0x0, 3180 MLX5_QUERY_VPORT_STATE_OUT_STATE_UP = 0x1, 3181 }; 3182 3183 struct mlx5_ifc_query_vport_state_out_bits { 3184 u8 status[0x8]; 3185 u8 reserved_at_8[0x18]; 3186 3187 u8 syndrome[0x20]; 3188 3189 u8 reserved_at_40[0x20]; 3190 3191 u8 reserved_at_60[0x18]; 3192 u8 admin_state[0x4]; 3193 u8 state[0x4]; 3194 }; 3195 3196 enum { 3197 MLX5_QUERY_VPORT_STATE_IN_OP_MOD_VNIC_VPORT = 0x0, 3198 MLX5_QUERY_VPORT_STATE_IN_OP_MOD_ESW_VPORT = 0x1, 3199 }; 3200 3201 struct mlx5_ifc_query_vport_state_in_bits { 3202 u8 opcode[0x10]; 3203 u8 reserved_at_10[0x10]; 3204 3205 u8 reserved_at_20[0x10]; 3206 u8 op_mod[0x10]; 3207 3208 u8 other_vport[0x1]; 3209 u8 reserved_at_41[0xf]; 3210 u8 vport_number[0x10]; 3211 3212 u8 reserved_at_60[0x20]; 3213 }; 3214 3215 struct mlx5_ifc_query_vport_counter_out_bits { 3216 u8 status[0x8]; 3217 u8 reserved_at_8[0x18]; 3218 3219 u8 syndrome[0x20]; 3220 3221 u8 reserved_at_40[0x40]; 3222 3223 struct mlx5_ifc_traffic_counter_bits received_errors; 3224 3225 struct mlx5_ifc_traffic_counter_bits transmit_errors; 3226 3227 struct mlx5_ifc_traffic_counter_bits received_ib_unicast; 3228 3229 struct mlx5_ifc_traffic_counter_bits transmitted_ib_unicast; 3230 3231 struct mlx5_ifc_traffic_counter_bits received_ib_multicast; 3232 3233 struct mlx5_ifc_traffic_counter_bits transmitted_ib_multicast; 3234 3235 struct mlx5_ifc_traffic_counter_bits received_eth_broadcast; 3236 3237 struct mlx5_ifc_traffic_counter_bits transmitted_eth_broadcast; 3238 3239 struct mlx5_ifc_traffic_counter_bits received_eth_unicast; 3240 3241 struct mlx5_ifc_traffic_counter_bits transmitted_eth_unicast; 3242 3243 struct mlx5_ifc_traffic_counter_bits received_eth_multicast; 3244 3245 struct mlx5_ifc_traffic_counter_bits transmitted_eth_multicast; 3246 3247 u8 reserved_at_680[0xa00]; 3248 }; 3249 3250 enum { 3251 MLX5_QUERY_VPORT_COUNTER_IN_OP_MOD_VPORT_COUNTERS = 0x0, 3252 }; 3253 3254 struct mlx5_ifc_query_vport_counter_in_bits { 3255 u8 opcode[0x10]; 3256 u8 reserved_at_10[0x10]; 3257 3258 u8 reserved_at_20[0x10]; 3259 u8 op_mod[0x10]; 3260 3261 u8 other_vport[0x1]; 3262 u8 reserved_at_41[0xb]; 3263 u8 port_num[0x4]; 3264 u8 vport_number[0x10]; 3265 3266 u8 reserved_at_60[0x60]; 3267 3268 u8 clear[0x1]; 3269 u8 reserved_at_c1[0x1f]; 3270 3271 u8 reserved_at_e0[0x20]; 3272 }; 3273 3274 struct mlx5_ifc_query_tis_out_bits { 3275 u8 status[0x8]; 3276 u8 reserved_at_8[0x18]; 3277 3278 u8 syndrome[0x20]; 3279 3280 u8 reserved_at_40[0x40]; 3281 3282 struct mlx5_ifc_tisc_bits tis_context; 3283 }; 3284 3285 struct mlx5_ifc_query_tis_in_bits { 3286 u8 opcode[0x10]; 3287 u8 reserved_at_10[0x10]; 3288 3289 u8 reserved_at_20[0x10]; 3290 u8 op_mod[0x10]; 3291 3292 u8 reserved_at_40[0x8]; 3293 u8 tisn[0x18]; 3294 3295 u8 reserved_at_60[0x20]; 3296 }; 3297 3298 struct mlx5_ifc_query_tir_out_bits { 3299 u8 status[0x8]; 3300 u8 reserved_at_8[0x18]; 3301 3302 u8 syndrome[0x20]; 3303 3304 u8 reserved_at_40[0xc0]; 3305 3306 struct mlx5_ifc_tirc_bits tir_context; 3307 }; 3308 3309 struct mlx5_ifc_query_tir_in_bits { 3310 u8 opcode[0x10]; 3311 u8 reserved_at_10[0x10]; 3312 3313 u8 reserved_at_20[0x10]; 3314 u8 op_mod[0x10]; 3315 3316 u8 reserved_at_40[0x8]; 3317 u8 tirn[0x18]; 3318 3319 u8 reserved_at_60[0x20]; 3320 }; 3321 3322 struct mlx5_ifc_query_srq_out_bits { 3323 u8 status[0x8]; 3324 u8 reserved_at_8[0x18]; 3325 3326 u8 syndrome[0x20]; 3327 3328 u8 reserved_at_40[0x40]; 3329 3330 struct mlx5_ifc_srqc_bits srq_context_entry; 3331 3332 u8 reserved_at_280[0x600]; 3333 3334 u8 pas[0][0x40]; 3335 }; 3336 3337 struct mlx5_ifc_query_srq_in_bits { 3338 u8 opcode[0x10]; 3339 u8 reserved_at_10[0x10]; 3340 3341 u8 reserved_at_20[0x10]; 3342 u8 op_mod[0x10]; 3343 3344 u8 reserved_at_40[0x8]; 3345 u8 srqn[0x18]; 3346 3347 u8 reserved_at_60[0x20]; 3348 }; 3349 3350 struct mlx5_ifc_query_sq_out_bits { 3351 u8 status[0x8]; 3352 u8 reserved_at_8[0x18]; 3353 3354 u8 syndrome[0x20]; 3355 3356 u8 reserved_at_40[0xc0]; 3357 3358 struct mlx5_ifc_sqc_bits sq_context; 3359 }; 3360 3361 struct mlx5_ifc_query_sq_in_bits { 3362 u8 opcode[0x10]; 3363 u8 reserved_at_10[0x10]; 3364 3365 u8 reserved_at_20[0x10]; 3366 u8 op_mod[0x10]; 3367 3368 u8 reserved_at_40[0x8]; 3369 u8 sqn[0x18]; 3370 3371 u8 reserved_at_60[0x20]; 3372 }; 3373 3374 struct mlx5_ifc_query_special_contexts_out_bits { 3375 u8 status[0x8]; 3376 u8 reserved_at_8[0x18]; 3377 3378 u8 syndrome[0x20]; 3379 3380 u8 reserved_at_40[0x20]; 3381 3382 u8 resd_lkey[0x20]; 3383 }; 3384 3385 struct mlx5_ifc_query_special_contexts_in_bits { 3386 u8 opcode[0x10]; 3387 u8 reserved_at_10[0x10]; 3388 3389 u8 reserved_at_20[0x10]; 3390 u8 op_mod[0x10]; 3391 3392 u8 reserved_at_40[0x40]; 3393 }; 3394 3395 struct mlx5_ifc_query_rqt_out_bits { 3396 u8 status[0x8]; 3397 u8 reserved_at_8[0x18]; 3398 3399 u8 syndrome[0x20]; 3400 3401 u8 reserved_at_40[0xc0]; 3402 3403 struct mlx5_ifc_rqtc_bits rqt_context; 3404 }; 3405 3406 struct mlx5_ifc_query_rqt_in_bits { 3407 u8 opcode[0x10]; 3408 u8 reserved_at_10[0x10]; 3409 3410 u8 reserved_at_20[0x10]; 3411 u8 op_mod[0x10]; 3412 3413 u8 reserved_at_40[0x8]; 3414 u8 rqtn[0x18]; 3415 3416 u8 reserved_at_60[0x20]; 3417 }; 3418 3419 struct mlx5_ifc_query_rq_out_bits { 3420 u8 status[0x8]; 3421 u8 reserved_at_8[0x18]; 3422 3423 u8 syndrome[0x20]; 3424 3425 u8 reserved_at_40[0xc0]; 3426 3427 struct mlx5_ifc_rqc_bits rq_context; 3428 }; 3429 3430 struct mlx5_ifc_query_rq_in_bits { 3431 u8 opcode[0x10]; 3432 u8 reserved_at_10[0x10]; 3433 3434 u8 reserved_at_20[0x10]; 3435 u8 op_mod[0x10]; 3436 3437 u8 reserved_at_40[0x8]; 3438 u8 rqn[0x18]; 3439 3440 u8 reserved_at_60[0x20]; 3441 }; 3442 3443 struct mlx5_ifc_query_roce_address_out_bits { 3444 u8 status[0x8]; 3445 u8 reserved_at_8[0x18]; 3446 3447 u8 syndrome[0x20]; 3448 3449 u8 reserved_at_40[0x40]; 3450 3451 struct mlx5_ifc_roce_addr_layout_bits roce_address; 3452 }; 3453 3454 struct mlx5_ifc_query_roce_address_in_bits { 3455 u8 opcode[0x10]; 3456 u8 reserved_at_10[0x10]; 3457 3458 u8 reserved_at_20[0x10]; 3459 u8 op_mod[0x10]; 3460 3461 u8 roce_address_index[0x10]; 3462 u8 reserved_at_50[0x10]; 3463 3464 u8 reserved_at_60[0x20]; 3465 }; 3466 3467 struct mlx5_ifc_query_rmp_out_bits { 3468 u8 status[0x8]; 3469 u8 reserved_at_8[0x18]; 3470 3471 u8 syndrome[0x20]; 3472 3473 u8 reserved_at_40[0xc0]; 3474 3475 struct mlx5_ifc_rmpc_bits rmp_context; 3476 }; 3477 3478 struct mlx5_ifc_query_rmp_in_bits { 3479 u8 opcode[0x10]; 3480 u8 reserved_at_10[0x10]; 3481 3482 u8 reserved_at_20[0x10]; 3483 u8 op_mod[0x10]; 3484 3485 u8 reserved_at_40[0x8]; 3486 u8 rmpn[0x18]; 3487 3488 u8 reserved_at_60[0x20]; 3489 }; 3490 3491 struct mlx5_ifc_query_qp_out_bits { 3492 u8 status[0x8]; 3493 u8 reserved_at_8[0x18]; 3494 3495 u8 syndrome[0x20]; 3496 3497 u8 reserved_at_40[0x40]; 3498 3499 u8 opt_param_mask[0x20]; 3500 3501 u8 reserved_at_a0[0x20]; 3502 3503 struct mlx5_ifc_qpc_bits qpc; 3504 3505 u8 reserved_at_800[0x80]; 3506 3507 u8 pas[0][0x40]; 3508 }; 3509 3510 struct mlx5_ifc_query_qp_in_bits { 3511 u8 opcode[0x10]; 3512 u8 reserved_at_10[0x10]; 3513 3514 u8 reserved_at_20[0x10]; 3515 u8 op_mod[0x10]; 3516 3517 u8 reserved_at_40[0x8]; 3518 u8 qpn[0x18]; 3519 3520 u8 reserved_at_60[0x20]; 3521 }; 3522 3523 struct mlx5_ifc_query_q_counter_out_bits { 3524 u8 status[0x8]; 3525 u8 reserved_at_8[0x18]; 3526 3527 u8 syndrome[0x20]; 3528 3529 u8 reserved_at_40[0x40]; 3530 3531 u8 rx_write_requests[0x20]; 3532 3533 u8 reserved_at_a0[0x20]; 3534 3535 u8 rx_read_requests[0x20]; 3536 3537 u8 reserved_at_e0[0x20]; 3538 3539 u8 rx_atomic_requests[0x20]; 3540 3541 u8 reserved_at_120[0x20]; 3542 3543 u8 rx_dct_connect[0x20]; 3544 3545 u8 reserved_at_160[0x20]; 3546 3547 u8 out_of_buffer[0x20]; 3548 3549 u8 reserved_at_1a0[0x20]; 3550 3551 u8 out_of_sequence[0x20]; 3552 3553 u8 reserved_at_1e0[0x620]; 3554 }; 3555 3556 struct mlx5_ifc_query_q_counter_in_bits { 3557 u8 opcode[0x10]; 3558 u8 reserved_at_10[0x10]; 3559 3560 u8 reserved_at_20[0x10]; 3561 u8 op_mod[0x10]; 3562 3563 u8 reserved_at_40[0x80]; 3564 3565 u8 clear[0x1]; 3566 u8 reserved_at_c1[0x1f]; 3567 3568 u8 reserved_at_e0[0x18]; 3569 u8 counter_set_id[0x8]; 3570 }; 3571 3572 struct mlx5_ifc_query_pages_out_bits { 3573 u8 status[0x8]; 3574 u8 reserved_at_8[0x18]; 3575 3576 u8 syndrome[0x20]; 3577 3578 u8 reserved_at_40[0x10]; 3579 u8 function_id[0x10]; 3580 3581 u8 num_pages[0x20]; 3582 }; 3583 3584 enum { 3585 MLX5_QUERY_PAGES_IN_OP_MOD_BOOT_PAGES = 0x1, 3586 MLX5_QUERY_PAGES_IN_OP_MOD_INIT_PAGES = 0x2, 3587 MLX5_QUERY_PAGES_IN_OP_MOD_REGULAR_PAGES = 0x3, 3588 }; 3589 3590 struct mlx5_ifc_query_pages_in_bits { 3591 u8 opcode[0x10]; 3592 u8 reserved_at_10[0x10]; 3593 3594 u8 reserved_at_20[0x10]; 3595 u8 op_mod[0x10]; 3596 3597 u8 reserved_at_40[0x10]; 3598 u8 function_id[0x10]; 3599 3600 u8 reserved_at_60[0x20]; 3601 }; 3602 3603 struct mlx5_ifc_query_nic_vport_context_out_bits { 3604 u8 status[0x8]; 3605 u8 reserved_at_8[0x18]; 3606 3607 u8 syndrome[0x20]; 3608 3609 u8 reserved_at_40[0x40]; 3610 3611 struct mlx5_ifc_nic_vport_context_bits nic_vport_context; 3612 }; 3613 3614 struct mlx5_ifc_query_nic_vport_context_in_bits { 3615 u8 opcode[0x10]; 3616 u8 reserved_at_10[0x10]; 3617 3618 u8 reserved_at_20[0x10]; 3619 u8 op_mod[0x10]; 3620 3621 u8 other_vport[0x1]; 3622 u8 reserved_at_41[0xf]; 3623 u8 vport_number[0x10]; 3624 3625 u8 reserved_at_60[0x5]; 3626 u8 allowed_list_type[0x3]; 3627 u8 reserved_at_68[0x18]; 3628 }; 3629 3630 struct mlx5_ifc_query_mkey_out_bits { 3631 u8 status[0x8]; 3632 u8 reserved_at_8[0x18]; 3633 3634 u8 syndrome[0x20]; 3635 3636 u8 reserved_at_40[0x40]; 3637 3638 struct mlx5_ifc_mkc_bits memory_key_mkey_entry; 3639 3640 u8 reserved_at_280[0x600]; 3641 3642 u8 bsf0_klm0_pas_mtt0_1[16][0x8]; 3643 3644 u8 bsf1_klm1_pas_mtt2_3[16][0x8]; 3645 }; 3646 3647 struct mlx5_ifc_query_mkey_in_bits { 3648 u8 opcode[0x10]; 3649 u8 reserved_at_10[0x10]; 3650 3651 u8 reserved_at_20[0x10]; 3652 u8 op_mod[0x10]; 3653 3654 u8 reserved_at_40[0x8]; 3655 u8 mkey_index[0x18]; 3656 3657 u8 pg_access[0x1]; 3658 u8 reserved_at_61[0x1f]; 3659 }; 3660 3661 struct mlx5_ifc_query_mad_demux_out_bits { 3662 u8 status[0x8]; 3663 u8 reserved_at_8[0x18]; 3664 3665 u8 syndrome[0x20]; 3666 3667 u8 reserved_at_40[0x40]; 3668 3669 u8 mad_dumux_parameters_block[0x20]; 3670 }; 3671 3672 struct mlx5_ifc_query_mad_demux_in_bits { 3673 u8 opcode[0x10]; 3674 u8 reserved_at_10[0x10]; 3675 3676 u8 reserved_at_20[0x10]; 3677 u8 op_mod[0x10]; 3678 3679 u8 reserved_at_40[0x40]; 3680 }; 3681 3682 struct mlx5_ifc_query_l2_table_entry_out_bits { 3683 u8 status[0x8]; 3684 u8 reserved_at_8[0x18]; 3685 3686 u8 syndrome[0x20]; 3687 3688 u8 reserved_at_40[0xa0]; 3689 3690 u8 reserved_at_e0[0x13]; 3691 u8 vlan_valid[0x1]; 3692 u8 vlan[0xc]; 3693 3694 struct mlx5_ifc_mac_address_layout_bits mac_address; 3695 3696 u8 reserved_at_140[0xc0]; 3697 }; 3698 3699 struct mlx5_ifc_query_l2_table_entry_in_bits { 3700 u8 opcode[0x10]; 3701 u8 reserved_at_10[0x10]; 3702 3703 u8 reserved_at_20[0x10]; 3704 u8 op_mod[0x10]; 3705 3706 u8 reserved_at_40[0x60]; 3707 3708 u8 reserved_at_a0[0x8]; 3709 u8 table_index[0x18]; 3710 3711 u8 reserved_at_c0[0x140]; 3712 }; 3713 3714 struct mlx5_ifc_query_issi_out_bits { 3715 u8 status[0x8]; 3716 u8 reserved_at_8[0x18]; 3717 3718 u8 syndrome[0x20]; 3719 3720 u8 reserved_at_40[0x10]; 3721 u8 current_issi[0x10]; 3722 3723 u8 reserved_at_60[0xa0]; 3724 3725 u8 reserved_at_100[76][0x8]; 3726 u8 supported_issi_dw0[0x20]; 3727 }; 3728 3729 struct mlx5_ifc_query_issi_in_bits { 3730 u8 opcode[0x10]; 3731 u8 reserved_at_10[0x10]; 3732 3733 u8 reserved_at_20[0x10]; 3734 u8 op_mod[0x10]; 3735 3736 u8 reserved_at_40[0x40]; 3737 }; 3738 3739 struct mlx5_ifc_query_hca_vport_pkey_out_bits { 3740 u8 status[0x8]; 3741 u8 reserved_at_8[0x18]; 3742 3743 u8 syndrome[0x20]; 3744 3745 u8 reserved_at_40[0x40]; 3746 3747 struct mlx5_ifc_pkey_bits pkey[0]; 3748 }; 3749 3750 struct mlx5_ifc_query_hca_vport_pkey_in_bits { 3751 u8 opcode[0x10]; 3752 u8 reserved_at_10[0x10]; 3753 3754 u8 reserved_at_20[0x10]; 3755 u8 op_mod[0x10]; 3756 3757 u8 other_vport[0x1]; 3758 u8 reserved_at_41[0xb]; 3759 u8 port_num[0x4]; 3760 u8 vport_number[0x10]; 3761 3762 u8 reserved_at_60[0x10]; 3763 u8 pkey_index[0x10]; 3764 }; 3765 3766 enum { 3767 MLX5_HCA_VPORT_SEL_PORT_GUID = 1 << 0, 3768 MLX5_HCA_VPORT_SEL_NODE_GUID = 1 << 1, 3769 MLX5_HCA_VPORT_SEL_STATE_POLICY = 1 << 2, 3770 }; 3771 3772 struct mlx5_ifc_query_hca_vport_gid_out_bits { 3773 u8 status[0x8]; 3774 u8 reserved_at_8[0x18]; 3775 3776 u8 syndrome[0x20]; 3777 3778 u8 reserved_at_40[0x20]; 3779 3780 u8 gids_num[0x10]; 3781 u8 reserved_at_70[0x10]; 3782 3783 struct mlx5_ifc_array128_auto_bits gid[0]; 3784 }; 3785 3786 struct mlx5_ifc_query_hca_vport_gid_in_bits { 3787 u8 opcode[0x10]; 3788 u8 reserved_at_10[0x10]; 3789 3790 u8 reserved_at_20[0x10]; 3791 u8 op_mod[0x10]; 3792 3793 u8 other_vport[0x1]; 3794 u8 reserved_at_41[0xb]; 3795 u8 port_num[0x4]; 3796 u8 vport_number[0x10]; 3797 3798 u8 reserved_at_60[0x10]; 3799 u8 gid_index[0x10]; 3800 }; 3801 3802 struct mlx5_ifc_query_hca_vport_context_out_bits { 3803 u8 status[0x8]; 3804 u8 reserved_at_8[0x18]; 3805 3806 u8 syndrome[0x20]; 3807 3808 u8 reserved_at_40[0x40]; 3809 3810 struct mlx5_ifc_hca_vport_context_bits hca_vport_context; 3811 }; 3812 3813 struct mlx5_ifc_query_hca_vport_context_in_bits { 3814 u8 opcode[0x10]; 3815 u8 reserved_at_10[0x10]; 3816 3817 u8 reserved_at_20[0x10]; 3818 u8 op_mod[0x10]; 3819 3820 u8 other_vport[0x1]; 3821 u8 reserved_at_41[0xb]; 3822 u8 port_num[0x4]; 3823 u8 vport_number[0x10]; 3824 3825 u8 reserved_at_60[0x20]; 3826 }; 3827 3828 struct mlx5_ifc_query_hca_cap_out_bits { 3829 u8 status[0x8]; 3830 u8 reserved_at_8[0x18]; 3831 3832 u8 syndrome[0x20]; 3833 3834 u8 reserved_at_40[0x40]; 3835 3836 union mlx5_ifc_hca_cap_union_bits capability; 3837 }; 3838 3839 struct mlx5_ifc_query_hca_cap_in_bits { 3840 u8 opcode[0x10]; 3841 u8 reserved_at_10[0x10]; 3842 3843 u8 reserved_at_20[0x10]; 3844 u8 op_mod[0x10]; 3845 3846 u8 reserved_at_40[0x40]; 3847 }; 3848 3849 struct mlx5_ifc_query_flow_table_out_bits { 3850 u8 status[0x8]; 3851 u8 reserved_at_8[0x18]; 3852 3853 u8 syndrome[0x20]; 3854 3855 u8 reserved_at_40[0x80]; 3856 3857 u8 reserved_at_c0[0x8]; 3858 u8 level[0x8]; 3859 u8 reserved_at_d0[0x8]; 3860 u8 log_size[0x8]; 3861 3862 u8 reserved_at_e0[0x120]; 3863 }; 3864 3865 struct mlx5_ifc_query_flow_table_in_bits { 3866 u8 opcode[0x10]; 3867 u8 reserved_at_10[0x10]; 3868 3869 u8 reserved_at_20[0x10]; 3870 u8 op_mod[0x10]; 3871 3872 u8 reserved_at_40[0x40]; 3873 3874 u8 table_type[0x8]; 3875 u8 reserved_at_88[0x18]; 3876 3877 u8 reserved_at_a0[0x8]; 3878 u8 table_id[0x18]; 3879 3880 u8 reserved_at_c0[0x140]; 3881 }; 3882 3883 struct mlx5_ifc_query_fte_out_bits { 3884 u8 status[0x8]; 3885 u8 reserved_at_8[0x18]; 3886 3887 u8 syndrome[0x20]; 3888 3889 u8 reserved_at_40[0x1c0]; 3890 3891 struct mlx5_ifc_flow_context_bits flow_context; 3892 }; 3893 3894 struct mlx5_ifc_query_fte_in_bits { 3895 u8 opcode[0x10]; 3896 u8 reserved_at_10[0x10]; 3897 3898 u8 reserved_at_20[0x10]; 3899 u8 op_mod[0x10]; 3900 3901 u8 reserved_at_40[0x40]; 3902 3903 u8 table_type[0x8]; 3904 u8 reserved_at_88[0x18]; 3905 3906 u8 reserved_at_a0[0x8]; 3907 u8 table_id[0x18]; 3908 3909 u8 reserved_at_c0[0x40]; 3910 3911 u8 flow_index[0x20]; 3912 3913 u8 reserved_at_120[0xe0]; 3914 }; 3915 3916 enum { 3917 MLX5_QUERY_FLOW_GROUP_OUT_MATCH_CRITERIA_ENABLE_OUTER_HEADERS = 0x0, 3918 MLX5_QUERY_FLOW_GROUP_OUT_MATCH_CRITERIA_ENABLE_MISC_PARAMETERS = 0x1, 3919 MLX5_QUERY_FLOW_GROUP_OUT_MATCH_CRITERIA_ENABLE_INNER_HEADERS = 0x2, 3920 }; 3921 3922 struct mlx5_ifc_query_flow_group_out_bits { 3923 u8 status[0x8]; 3924 u8 reserved_at_8[0x18]; 3925 3926 u8 syndrome[0x20]; 3927 3928 u8 reserved_at_40[0xa0]; 3929 3930 u8 start_flow_index[0x20]; 3931 3932 u8 reserved_at_100[0x20]; 3933 3934 u8 end_flow_index[0x20]; 3935 3936 u8 reserved_at_140[0xa0]; 3937 3938 u8 reserved_at_1e0[0x18]; 3939 u8 match_criteria_enable[0x8]; 3940 3941 struct mlx5_ifc_fte_match_param_bits match_criteria; 3942 3943 u8 reserved_at_1200[0xe00]; 3944 }; 3945 3946 struct mlx5_ifc_query_flow_group_in_bits { 3947 u8 opcode[0x10]; 3948 u8 reserved_at_10[0x10]; 3949 3950 u8 reserved_at_20[0x10]; 3951 u8 op_mod[0x10]; 3952 3953 u8 reserved_at_40[0x40]; 3954 3955 u8 table_type[0x8]; 3956 u8 reserved_at_88[0x18]; 3957 3958 u8 reserved_at_a0[0x8]; 3959 u8 table_id[0x18]; 3960 3961 u8 group_id[0x20]; 3962 3963 u8 reserved_at_e0[0x120]; 3964 }; 3965 3966 struct mlx5_ifc_query_flow_counter_out_bits { 3967 u8 status[0x8]; 3968 u8 reserved_at_8[0x18]; 3969 3970 u8 syndrome[0x20]; 3971 3972 u8 reserved_at_40[0x40]; 3973 3974 struct mlx5_ifc_traffic_counter_bits flow_statistics[0]; 3975 }; 3976 3977 struct mlx5_ifc_query_flow_counter_in_bits { 3978 u8 opcode[0x10]; 3979 u8 reserved_at_10[0x10]; 3980 3981 u8 reserved_at_20[0x10]; 3982 u8 op_mod[0x10]; 3983 3984 u8 reserved_at_40[0x80]; 3985 3986 u8 clear[0x1]; 3987 u8 reserved_at_c1[0xf]; 3988 u8 num_of_counters[0x10]; 3989 3990 u8 reserved_at_e0[0x10]; 3991 u8 flow_counter_id[0x10]; 3992 }; 3993 3994 struct mlx5_ifc_query_esw_vport_context_out_bits { 3995 u8 status[0x8]; 3996 u8 reserved_at_8[0x18]; 3997 3998 u8 syndrome[0x20]; 3999 4000 u8 reserved_at_40[0x40]; 4001 4002 struct mlx5_ifc_esw_vport_context_bits esw_vport_context; 4003 }; 4004 4005 struct mlx5_ifc_query_esw_vport_context_in_bits { 4006 u8 opcode[0x10]; 4007 u8 reserved_at_10[0x10]; 4008 4009 u8 reserved_at_20[0x10]; 4010 u8 op_mod[0x10]; 4011 4012 u8 other_vport[0x1]; 4013 u8 reserved_at_41[0xf]; 4014 u8 vport_number[0x10]; 4015 4016 u8 reserved_at_60[0x20]; 4017 }; 4018 4019 struct mlx5_ifc_modify_esw_vport_context_out_bits { 4020 u8 status[0x8]; 4021 u8 reserved_at_8[0x18]; 4022 4023 u8 syndrome[0x20]; 4024 4025 u8 reserved_at_40[0x40]; 4026 }; 4027 4028 struct mlx5_ifc_esw_vport_context_fields_select_bits { 4029 u8 reserved_at_0[0x1c]; 4030 u8 vport_cvlan_insert[0x1]; 4031 u8 vport_svlan_insert[0x1]; 4032 u8 vport_cvlan_strip[0x1]; 4033 u8 vport_svlan_strip[0x1]; 4034 }; 4035 4036 struct mlx5_ifc_modify_esw_vport_context_in_bits { 4037 u8 opcode[0x10]; 4038 u8 reserved_at_10[0x10]; 4039 4040 u8 reserved_at_20[0x10]; 4041 u8 op_mod[0x10]; 4042 4043 u8 other_vport[0x1]; 4044 u8 reserved_at_41[0xf]; 4045 u8 vport_number[0x10]; 4046 4047 struct mlx5_ifc_esw_vport_context_fields_select_bits field_select; 4048 4049 struct mlx5_ifc_esw_vport_context_bits esw_vport_context; 4050 }; 4051 4052 struct mlx5_ifc_query_eq_out_bits { 4053 u8 status[0x8]; 4054 u8 reserved_at_8[0x18]; 4055 4056 u8 syndrome[0x20]; 4057 4058 u8 reserved_at_40[0x40]; 4059 4060 struct mlx5_ifc_eqc_bits eq_context_entry; 4061 4062 u8 reserved_at_280[0x40]; 4063 4064 u8 event_bitmask[0x40]; 4065 4066 u8 reserved_at_300[0x580]; 4067 4068 u8 pas[0][0x40]; 4069 }; 4070 4071 struct mlx5_ifc_query_eq_in_bits { 4072 u8 opcode[0x10]; 4073 u8 reserved_at_10[0x10]; 4074 4075 u8 reserved_at_20[0x10]; 4076 u8 op_mod[0x10]; 4077 4078 u8 reserved_at_40[0x18]; 4079 u8 eq_number[0x8]; 4080 4081 u8 reserved_at_60[0x20]; 4082 }; 4083 4084 struct mlx5_ifc_query_dct_out_bits { 4085 u8 status[0x8]; 4086 u8 reserved_at_8[0x18]; 4087 4088 u8 syndrome[0x20]; 4089 4090 u8 reserved_at_40[0x40]; 4091 4092 struct mlx5_ifc_dctc_bits dct_context_entry; 4093 4094 u8 reserved_at_280[0x180]; 4095 }; 4096 4097 struct mlx5_ifc_query_dct_in_bits { 4098 u8 opcode[0x10]; 4099 u8 reserved_at_10[0x10]; 4100 4101 u8 reserved_at_20[0x10]; 4102 u8 op_mod[0x10]; 4103 4104 u8 reserved_at_40[0x8]; 4105 u8 dctn[0x18]; 4106 4107 u8 reserved_at_60[0x20]; 4108 }; 4109 4110 struct mlx5_ifc_query_cq_out_bits { 4111 u8 status[0x8]; 4112 u8 reserved_at_8[0x18]; 4113 4114 u8 syndrome[0x20]; 4115 4116 u8 reserved_at_40[0x40]; 4117 4118 struct mlx5_ifc_cqc_bits cq_context; 4119 4120 u8 reserved_at_280[0x600]; 4121 4122 u8 pas[0][0x40]; 4123 }; 4124 4125 struct mlx5_ifc_query_cq_in_bits { 4126 u8 opcode[0x10]; 4127 u8 reserved_at_10[0x10]; 4128 4129 u8 reserved_at_20[0x10]; 4130 u8 op_mod[0x10]; 4131 4132 u8 reserved_at_40[0x8]; 4133 u8 cqn[0x18]; 4134 4135 u8 reserved_at_60[0x20]; 4136 }; 4137 4138 struct mlx5_ifc_query_cong_status_out_bits { 4139 u8 status[0x8]; 4140 u8 reserved_at_8[0x18]; 4141 4142 u8 syndrome[0x20]; 4143 4144 u8 reserved_at_40[0x20]; 4145 4146 u8 enable[0x1]; 4147 u8 tag_enable[0x1]; 4148 u8 reserved_at_62[0x1e]; 4149 }; 4150 4151 struct mlx5_ifc_query_cong_status_in_bits { 4152 u8 opcode[0x10]; 4153 u8 reserved_at_10[0x10]; 4154 4155 u8 reserved_at_20[0x10]; 4156 u8 op_mod[0x10]; 4157 4158 u8 reserved_at_40[0x18]; 4159 u8 priority[0x4]; 4160 u8 cong_protocol[0x4]; 4161 4162 u8 reserved_at_60[0x20]; 4163 }; 4164 4165 struct mlx5_ifc_query_cong_statistics_out_bits { 4166 u8 status[0x8]; 4167 u8 reserved_at_8[0x18]; 4168 4169 u8 syndrome[0x20]; 4170 4171 u8 reserved_at_40[0x40]; 4172 4173 u8 cur_flows[0x20]; 4174 4175 u8 sum_flows[0x20]; 4176 4177 u8 cnp_ignored_high[0x20]; 4178 4179 u8 cnp_ignored_low[0x20]; 4180 4181 u8 cnp_handled_high[0x20]; 4182 4183 u8 cnp_handled_low[0x20]; 4184 4185 u8 reserved_at_140[0x100]; 4186 4187 u8 time_stamp_high[0x20]; 4188 4189 u8 time_stamp_low[0x20]; 4190 4191 u8 accumulators_period[0x20]; 4192 4193 u8 ecn_marked_roce_packets_high[0x20]; 4194 4195 u8 ecn_marked_roce_packets_low[0x20]; 4196 4197 u8 cnps_sent_high[0x20]; 4198 4199 u8 cnps_sent_low[0x20]; 4200 4201 u8 reserved_at_320[0x560]; 4202 }; 4203 4204 struct mlx5_ifc_query_cong_statistics_in_bits { 4205 u8 opcode[0x10]; 4206 u8 reserved_at_10[0x10]; 4207 4208 u8 reserved_at_20[0x10]; 4209 u8 op_mod[0x10]; 4210 4211 u8 clear[0x1]; 4212 u8 reserved_at_41[0x1f]; 4213 4214 u8 reserved_at_60[0x20]; 4215 }; 4216 4217 struct mlx5_ifc_query_cong_params_out_bits { 4218 u8 status[0x8]; 4219 u8 reserved_at_8[0x18]; 4220 4221 u8 syndrome[0x20]; 4222 4223 u8 reserved_at_40[0x40]; 4224 4225 union mlx5_ifc_cong_control_roce_ecn_auto_bits congestion_parameters; 4226 }; 4227 4228 struct mlx5_ifc_query_cong_params_in_bits { 4229 u8 opcode[0x10]; 4230 u8 reserved_at_10[0x10]; 4231 4232 u8 reserved_at_20[0x10]; 4233 u8 op_mod[0x10]; 4234 4235 u8 reserved_at_40[0x1c]; 4236 u8 cong_protocol[0x4]; 4237 4238 u8 reserved_at_60[0x20]; 4239 }; 4240 4241 struct mlx5_ifc_query_adapter_out_bits { 4242 u8 status[0x8]; 4243 u8 reserved_at_8[0x18]; 4244 4245 u8 syndrome[0x20]; 4246 4247 u8 reserved_at_40[0x40]; 4248 4249 struct mlx5_ifc_query_adapter_param_block_bits query_adapter_struct; 4250 }; 4251 4252 struct mlx5_ifc_query_adapter_in_bits { 4253 u8 opcode[0x10]; 4254 u8 reserved_at_10[0x10]; 4255 4256 u8 reserved_at_20[0x10]; 4257 u8 op_mod[0x10]; 4258 4259 u8 reserved_at_40[0x40]; 4260 }; 4261 4262 struct mlx5_ifc_qp_2rst_out_bits { 4263 u8 status[0x8]; 4264 u8 reserved_at_8[0x18]; 4265 4266 u8 syndrome[0x20]; 4267 4268 u8 reserved_at_40[0x40]; 4269 }; 4270 4271 struct mlx5_ifc_qp_2rst_in_bits { 4272 u8 opcode[0x10]; 4273 u8 reserved_at_10[0x10]; 4274 4275 u8 reserved_at_20[0x10]; 4276 u8 op_mod[0x10]; 4277 4278 u8 reserved_at_40[0x8]; 4279 u8 qpn[0x18]; 4280 4281 u8 reserved_at_60[0x20]; 4282 }; 4283 4284 struct mlx5_ifc_qp_2err_out_bits { 4285 u8 status[0x8]; 4286 u8 reserved_at_8[0x18]; 4287 4288 u8 syndrome[0x20]; 4289 4290 u8 reserved_at_40[0x40]; 4291 }; 4292 4293 struct mlx5_ifc_qp_2err_in_bits { 4294 u8 opcode[0x10]; 4295 u8 reserved_at_10[0x10]; 4296 4297 u8 reserved_at_20[0x10]; 4298 u8 op_mod[0x10]; 4299 4300 u8 reserved_at_40[0x8]; 4301 u8 qpn[0x18]; 4302 4303 u8 reserved_at_60[0x20]; 4304 }; 4305 4306 struct mlx5_ifc_page_fault_resume_out_bits { 4307 u8 status[0x8]; 4308 u8 reserved_at_8[0x18]; 4309 4310 u8 syndrome[0x20]; 4311 4312 u8 reserved_at_40[0x40]; 4313 }; 4314 4315 struct mlx5_ifc_page_fault_resume_in_bits { 4316 u8 opcode[0x10]; 4317 u8 reserved_at_10[0x10]; 4318 4319 u8 reserved_at_20[0x10]; 4320 u8 op_mod[0x10]; 4321 4322 u8 error[0x1]; 4323 u8 reserved_at_41[0x4]; 4324 u8 rdma[0x1]; 4325 u8 read_write[0x1]; 4326 u8 req_res[0x1]; 4327 u8 qpn[0x18]; 4328 4329 u8 reserved_at_60[0x20]; 4330 }; 4331 4332 struct mlx5_ifc_nop_out_bits { 4333 u8 status[0x8]; 4334 u8 reserved_at_8[0x18]; 4335 4336 u8 syndrome[0x20]; 4337 4338 u8 reserved_at_40[0x40]; 4339 }; 4340 4341 struct mlx5_ifc_nop_in_bits { 4342 u8 opcode[0x10]; 4343 u8 reserved_at_10[0x10]; 4344 4345 u8 reserved_at_20[0x10]; 4346 u8 op_mod[0x10]; 4347 4348 u8 reserved_at_40[0x40]; 4349 }; 4350 4351 struct mlx5_ifc_modify_vport_state_out_bits { 4352 u8 status[0x8]; 4353 u8 reserved_at_8[0x18]; 4354 4355 u8 syndrome[0x20]; 4356 4357 u8 reserved_at_40[0x40]; 4358 }; 4359 4360 struct mlx5_ifc_modify_vport_state_in_bits { 4361 u8 opcode[0x10]; 4362 u8 reserved_at_10[0x10]; 4363 4364 u8 reserved_at_20[0x10]; 4365 u8 op_mod[0x10]; 4366 4367 u8 other_vport[0x1]; 4368 u8 reserved_at_41[0xf]; 4369 u8 vport_number[0x10]; 4370 4371 u8 reserved_at_60[0x18]; 4372 u8 admin_state[0x4]; 4373 u8 reserved_at_7c[0x4]; 4374 }; 4375 4376 struct mlx5_ifc_modify_tis_out_bits { 4377 u8 status[0x8]; 4378 u8 reserved_at_8[0x18]; 4379 4380 u8 syndrome[0x20]; 4381 4382 u8 reserved_at_40[0x40]; 4383 }; 4384 4385 struct mlx5_ifc_modify_tis_bitmask_bits { 4386 u8 reserved_at_0[0x20]; 4387 4388 u8 reserved_at_20[0x1f]; 4389 u8 prio[0x1]; 4390 }; 4391 4392 struct mlx5_ifc_modify_tis_in_bits { 4393 u8 opcode[0x10]; 4394 u8 reserved_at_10[0x10]; 4395 4396 u8 reserved_at_20[0x10]; 4397 u8 op_mod[0x10]; 4398 4399 u8 reserved_at_40[0x8]; 4400 u8 tisn[0x18]; 4401 4402 u8 reserved_at_60[0x20]; 4403 4404 struct mlx5_ifc_modify_tis_bitmask_bits bitmask; 4405 4406 u8 reserved_at_c0[0x40]; 4407 4408 struct mlx5_ifc_tisc_bits ctx; 4409 }; 4410 4411 struct mlx5_ifc_modify_tir_bitmask_bits { 4412 u8 reserved_at_0[0x20]; 4413 4414 u8 reserved_at_20[0x1b]; 4415 u8 self_lb_en[0x1]; 4416 u8 reserved_at_3c[0x1]; 4417 u8 hash[0x1]; 4418 u8 reserved_at_3e[0x1]; 4419 u8 lro[0x1]; 4420 }; 4421 4422 struct mlx5_ifc_modify_tir_out_bits { 4423 u8 status[0x8]; 4424 u8 reserved_at_8[0x18]; 4425 4426 u8 syndrome[0x20]; 4427 4428 u8 reserved_at_40[0x40]; 4429 }; 4430 4431 struct mlx5_ifc_modify_tir_in_bits { 4432 u8 opcode[0x10]; 4433 u8 reserved_at_10[0x10]; 4434 4435 u8 reserved_at_20[0x10]; 4436 u8 op_mod[0x10]; 4437 4438 u8 reserved_at_40[0x8]; 4439 u8 tirn[0x18]; 4440 4441 u8 reserved_at_60[0x20]; 4442 4443 struct mlx5_ifc_modify_tir_bitmask_bits bitmask; 4444 4445 u8 reserved_at_c0[0x40]; 4446 4447 struct mlx5_ifc_tirc_bits ctx; 4448 }; 4449 4450 struct mlx5_ifc_modify_sq_out_bits { 4451 u8 status[0x8]; 4452 u8 reserved_at_8[0x18]; 4453 4454 u8 syndrome[0x20]; 4455 4456 u8 reserved_at_40[0x40]; 4457 }; 4458 4459 struct mlx5_ifc_modify_sq_in_bits { 4460 u8 opcode[0x10]; 4461 u8 reserved_at_10[0x10]; 4462 4463 u8 reserved_at_20[0x10]; 4464 u8 op_mod[0x10]; 4465 4466 u8 sq_state[0x4]; 4467 u8 reserved_at_44[0x4]; 4468 u8 sqn[0x18]; 4469 4470 u8 reserved_at_60[0x20]; 4471 4472 u8 modify_bitmask[0x40]; 4473 4474 u8 reserved_at_c0[0x40]; 4475 4476 struct mlx5_ifc_sqc_bits ctx; 4477 }; 4478 4479 struct mlx5_ifc_modify_rqt_out_bits { 4480 u8 status[0x8]; 4481 u8 reserved_at_8[0x18]; 4482 4483 u8 syndrome[0x20]; 4484 4485 u8 reserved_at_40[0x40]; 4486 }; 4487 4488 struct mlx5_ifc_rqt_bitmask_bits { 4489 u8 reserved_at_0[0x20]; 4490 4491 u8 reserved_at_20[0x1f]; 4492 u8 rqn_list[0x1]; 4493 }; 4494 4495 struct mlx5_ifc_modify_rqt_in_bits { 4496 u8 opcode[0x10]; 4497 u8 reserved_at_10[0x10]; 4498 4499 u8 reserved_at_20[0x10]; 4500 u8 op_mod[0x10]; 4501 4502 u8 reserved_at_40[0x8]; 4503 u8 rqtn[0x18]; 4504 4505 u8 reserved_at_60[0x20]; 4506 4507 struct mlx5_ifc_rqt_bitmask_bits bitmask; 4508 4509 u8 reserved_at_c0[0x40]; 4510 4511 struct mlx5_ifc_rqtc_bits ctx; 4512 }; 4513 4514 struct mlx5_ifc_modify_rq_out_bits { 4515 u8 status[0x8]; 4516 u8 reserved_at_8[0x18]; 4517 4518 u8 syndrome[0x20]; 4519 4520 u8 reserved_at_40[0x40]; 4521 }; 4522 4523 struct mlx5_ifc_modify_rq_in_bits { 4524 u8 opcode[0x10]; 4525 u8 reserved_at_10[0x10]; 4526 4527 u8 reserved_at_20[0x10]; 4528 u8 op_mod[0x10]; 4529 4530 u8 rq_state[0x4]; 4531 u8 reserved_at_44[0x4]; 4532 u8 rqn[0x18]; 4533 4534 u8 reserved_at_60[0x20]; 4535 4536 u8 modify_bitmask[0x40]; 4537 4538 u8 reserved_at_c0[0x40]; 4539 4540 struct mlx5_ifc_rqc_bits ctx; 4541 }; 4542 4543 struct mlx5_ifc_modify_rmp_out_bits { 4544 u8 status[0x8]; 4545 u8 reserved_at_8[0x18]; 4546 4547 u8 syndrome[0x20]; 4548 4549 u8 reserved_at_40[0x40]; 4550 }; 4551 4552 struct mlx5_ifc_rmp_bitmask_bits { 4553 u8 reserved_at_0[0x20]; 4554 4555 u8 reserved_at_20[0x1f]; 4556 u8 lwm[0x1]; 4557 }; 4558 4559 struct mlx5_ifc_modify_rmp_in_bits { 4560 u8 opcode[0x10]; 4561 u8 reserved_at_10[0x10]; 4562 4563 u8 reserved_at_20[0x10]; 4564 u8 op_mod[0x10]; 4565 4566 u8 rmp_state[0x4]; 4567 u8 reserved_at_44[0x4]; 4568 u8 rmpn[0x18]; 4569 4570 u8 reserved_at_60[0x20]; 4571 4572 struct mlx5_ifc_rmp_bitmask_bits bitmask; 4573 4574 u8 reserved_at_c0[0x40]; 4575 4576 struct mlx5_ifc_rmpc_bits ctx; 4577 }; 4578 4579 struct mlx5_ifc_modify_nic_vport_context_out_bits { 4580 u8 status[0x8]; 4581 u8 reserved_at_8[0x18]; 4582 4583 u8 syndrome[0x20]; 4584 4585 u8 reserved_at_40[0x40]; 4586 }; 4587 4588 struct mlx5_ifc_modify_nic_vport_field_select_bits { 4589 u8 reserved_at_0[0x16]; 4590 u8 node_guid[0x1]; 4591 u8 port_guid[0x1]; 4592 u8 reserved_at_18[0x1]; 4593 u8 mtu[0x1]; 4594 u8 change_event[0x1]; 4595 u8 promisc[0x1]; 4596 u8 permanent_address[0x1]; 4597 u8 addresses_list[0x1]; 4598 u8 roce_en[0x1]; 4599 u8 reserved_at_1f[0x1]; 4600 }; 4601 4602 struct mlx5_ifc_modify_nic_vport_context_in_bits { 4603 u8 opcode[0x10]; 4604 u8 reserved_at_10[0x10]; 4605 4606 u8 reserved_at_20[0x10]; 4607 u8 op_mod[0x10]; 4608 4609 u8 other_vport[0x1]; 4610 u8 reserved_at_41[0xf]; 4611 u8 vport_number[0x10]; 4612 4613 struct mlx5_ifc_modify_nic_vport_field_select_bits field_select; 4614 4615 u8 reserved_at_80[0x780]; 4616 4617 struct mlx5_ifc_nic_vport_context_bits nic_vport_context; 4618 }; 4619 4620 struct mlx5_ifc_modify_hca_vport_context_out_bits { 4621 u8 status[0x8]; 4622 u8 reserved_at_8[0x18]; 4623 4624 u8 syndrome[0x20]; 4625 4626 u8 reserved_at_40[0x40]; 4627 }; 4628 4629 struct mlx5_ifc_modify_hca_vport_context_in_bits { 4630 u8 opcode[0x10]; 4631 u8 reserved_at_10[0x10]; 4632 4633 u8 reserved_at_20[0x10]; 4634 u8 op_mod[0x10]; 4635 4636 u8 other_vport[0x1]; 4637 u8 reserved_at_41[0xb]; 4638 u8 port_num[0x4]; 4639 u8 vport_number[0x10]; 4640 4641 u8 reserved_at_60[0x20]; 4642 4643 struct mlx5_ifc_hca_vport_context_bits hca_vport_context; 4644 }; 4645 4646 struct mlx5_ifc_modify_cq_out_bits { 4647 u8 status[0x8]; 4648 u8 reserved_at_8[0x18]; 4649 4650 u8 syndrome[0x20]; 4651 4652 u8 reserved_at_40[0x40]; 4653 }; 4654 4655 enum { 4656 MLX5_MODIFY_CQ_IN_OP_MOD_MODIFY_CQ = 0x0, 4657 MLX5_MODIFY_CQ_IN_OP_MOD_RESIZE_CQ = 0x1, 4658 }; 4659 4660 struct mlx5_ifc_modify_cq_in_bits { 4661 u8 opcode[0x10]; 4662 u8 reserved_at_10[0x10]; 4663 4664 u8 reserved_at_20[0x10]; 4665 u8 op_mod[0x10]; 4666 4667 u8 reserved_at_40[0x8]; 4668 u8 cqn[0x18]; 4669 4670 union mlx5_ifc_modify_field_select_resize_field_select_auto_bits modify_field_select_resize_field_select; 4671 4672 struct mlx5_ifc_cqc_bits cq_context; 4673 4674 u8 reserved_at_280[0x600]; 4675 4676 u8 pas[0][0x40]; 4677 }; 4678 4679 struct mlx5_ifc_modify_cong_status_out_bits { 4680 u8 status[0x8]; 4681 u8 reserved_at_8[0x18]; 4682 4683 u8 syndrome[0x20]; 4684 4685 u8 reserved_at_40[0x40]; 4686 }; 4687 4688 struct mlx5_ifc_modify_cong_status_in_bits { 4689 u8 opcode[0x10]; 4690 u8 reserved_at_10[0x10]; 4691 4692 u8 reserved_at_20[0x10]; 4693 u8 op_mod[0x10]; 4694 4695 u8 reserved_at_40[0x18]; 4696 u8 priority[0x4]; 4697 u8 cong_protocol[0x4]; 4698 4699 u8 enable[0x1]; 4700 u8 tag_enable[0x1]; 4701 u8 reserved_at_62[0x1e]; 4702 }; 4703 4704 struct mlx5_ifc_modify_cong_params_out_bits { 4705 u8 status[0x8]; 4706 u8 reserved_at_8[0x18]; 4707 4708 u8 syndrome[0x20]; 4709 4710 u8 reserved_at_40[0x40]; 4711 }; 4712 4713 struct mlx5_ifc_modify_cong_params_in_bits { 4714 u8 opcode[0x10]; 4715 u8 reserved_at_10[0x10]; 4716 4717 u8 reserved_at_20[0x10]; 4718 u8 op_mod[0x10]; 4719 4720 u8 reserved_at_40[0x1c]; 4721 u8 cong_protocol[0x4]; 4722 4723 union mlx5_ifc_field_select_802_1_r_roce_auto_bits field_select; 4724 4725 u8 reserved_at_80[0x80]; 4726 4727 union mlx5_ifc_cong_control_roce_ecn_auto_bits congestion_parameters; 4728 }; 4729 4730 struct mlx5_ifc_manage_pages_out_bits { 4731 u8 status[0x8]; 4732 u8 reserved_at_8[0x18]; 4733 4734 u8 syndrome[0x20]; 4735 4736 u8 output_num_entries[0x20]; 4737 4738 u8 reserved_at_60[0x20]; 4739 4740 u8 pas[0][0x40]; 4741 }; 4742 4743 enum { 4744 MLX5_MANAGE_PAGES_IN_OP_MOD_ALLOCATION_FAIL = 0x0, 4745 MLX5_MANAGE_PAGES_IN_OP_MOD_ALLOCATION_SUCCESS = 0x1, 4746 MLX5_MANAGE_PAGES_IN_OP_MOD_HCA_RETURN_PAGES = 0x2, 4747 }; 4748 4749 struct mlx5_ifc_manage_pages_in_bits { 4750 u8 opcode[0x10]; 4751 u8 reserved_at_10[0x10]; 4752 4753 u8 reserved_at_20[0x10]; 4754 u8 op_mod[0x10]; 4755 4756 u8 reserved_at_40[0x10]; 4757 u8 function_id[0x10]; 4758 4759 u8 input_num_entries[0x20]; 4760 4761 u8 pas[0][0x40]; 4762 }; 4763 4764 struct mlx5_ifc_mad_ifc_out_bits { 4765 u8 status[0x8]; 4766 u8 reserved_at_8[0x18]; 4767 4768 u8 syndrome[0x20]; 4769 4770 u8 reserved_at_40[0x40]; 4771 4772 u8 response_mad_packet[256][0x8]; 4773 }; 4774 4775 struct mlx5_ifc_mad_ifc_in_bits { 4776 u8 opcode[0x10]; 4777 u8 reserved_at_10[0x10]; 4778 4779 u8 reserved_at_20[0x10]; 4780 u8 op_mod[0x10]; 4781 4782 u8 remote_lid[0x10]; 4783 u8 reserved_at_50[0x8]; 4784 u8 port[0x8]; 4785 4786 u8 reserved_at_60[0x20]; 4787 4788 u8 mad[256][0x8]; 4789 }; 4790 4791 struct mlx5_ifc_init_hca_out_bits { 4792 u8 status[0x8]; 4793 u8 reserved_at_8[0x18]; 4794 4795 u8 syndrome[0x20]; 4796 4797 u8 reserved_at_40[0x40]; 4798 }; 4799 4800 struct mlx5_ifc_init_hca_in_bits { 4801 u8 opcode[0x10]; 4802 u8 reserved_at_10[0x10]; 4803 4804 u8 reserved_at_20[0x10]; 4805 u8 op_mod[0x10]; 4806 4807 u8 reserved_at_40[0x40]; 4808 }; 4809 4810 struct mlx5_ifc_init2rtr_qp_out_bits { 4811 u8 status[0x8]; 4812 u8 reserved_at_8[0x18]; 4813 4814 u8 syndrome[0x20]; 4815 4816 u8 reserved_at_40[0x40]; 4817 }; 4818 4819 struct mlx5_ifc_init2rtr_qp_in_bits { 4820 u8 opcode[0x10]; 4821 u8 reserved_at_10[0x10]; 4822 4823 u8 reserved_at_20[0x10]; 4824 u8 op_mod[0x10]; 4825 4826 u8 reserved_at_40[0x8]; 4827 u8 qpn[0x18]; 4828 4829 u8 reserved_at_60[0x20]; 4830 4831 u8 opt_param_mask[0x20]; 4832 4833 u8 reserved_at_a0[0x20]; 4834 4835 struct mlx5_ifc_qpc_bits qpc; 4836 4837 u8 reserved_at_800[0x80]; 4838 }; 4839 4840 struct mlx5_ifc_init2init_qp_out_bits { 4841 u8 status[0x8]; 4842 u8 reserved_at_8[0x18]; 4843 4844 u8 syndrome[0x20]; 4845 4846 u8 reserved_at_40[0x40]; 4847 }; 4848 4849 struct mlx5_ifc_init2init_qp_in_bits { 4850 u8 opcode[0x10]; 4851 u8 reserved_at_10[0x10]; 4852 4853 u8 reserved_at_20[0x10]; 4854 u8 op_mod[0x10]; 4855 4856 u8 reserved_at_40[0x8]; 4857 u8 qpn[0x18]; 4858 4859 u8 reserved_at_60[0x20]; 4860 4861 u8 opt_param_mask[0x20]; 4862 4863 u8 reserved_at_a0[0x20]; 4864 4865 struct mlx5_ifc_qpc_bits qpc; 4866 4867 u8 reserved_at_800[0x80]; 4868 }; 4869 4870 struct mlx5_ifc_get_dropped_packet_log_out_bits { 4871 u8 status[0x8]; 4872 u8 reserved_at_8[0x18]; 4873 4874 u8 syndrome[0x20]; 4875 4876 u8 reserved_at_40[0x40]; 4877 4878 u8 packet_headers_log[128][0x8]; 4879 4880 u8 packet_syndrome[64][0x8]; 4881 }; 4882 4883 struct mlx5_ifc_get_dropped_packet_log_in_bits { 4884 u8 opcode[0x10]; 4885 u8 reserved_at_10[0x10]; 4886 4887 u8 reserved_at_20[0x10]; 4888 u8 op_mod[0x10]; 4889 4890 u8 reserved_at_40[0x40]; 4891 }; 4892 4893 struct mlx5_ifc_gen_eqe_in_bits { 4894 u8 opcode[0x10]; 4895 u8 reserved_at_10[0x10]; 4896 4897 u8 reserved_at_20[0x10]; 4898 u8 op_mod[0x10]; 4899 4900 u8 reserved_at_40[0x18]; 4901 u8 eq_number[0x8]; 4902 4903 u8 reserved_at_60[0x20]; 4904 4905 u8 eqe[64][0x8]; 4906 }; 4907 4908 struct mlx5_ifc_gen_eq_out_bits { 4909 u8 status[0x8]; 4910 u8 reserved_at_8[0x18]; 4911 4912 u8 syndrome[0x20]; 4913 4914 u8 reserved_at_40[0x40]; 4915 }; 4916 4917 struct mlx5_ifc_enable_hca_out_bits { 4918 u8 status[0x8]; 4919 u8 reserved_at_8[0x18]; 4920 4921 u8 syndrome[0x20]; 4922 4923 u8 reserved_at_40[0x20]; 4924 }; 4925 4926 struct mlx5_ifc_enable_hca_in_bits { 4927 u8 opcode[0x10]; 4928 u8 reserved_at_10[0x10]; 4929 4930 u8 reserved_at_20[0x10]; 4931 u8 op_mod[0x10]; 4932 4933 u8 reserved_at_40[0x10]; 4934 u8 function_id[0x10]; 4935 4936 u8 reserved_at_60[0x20]; 4937 }; 4938 4939 struct mlx5_ifc_drain_dct_out_bits { 4940 u8 status[0x8]; 4941 u8 reserved_at_8[0x18]; 4942 4943 u8 syndrome[0x20]; 4944 4945 u8 reserved_at_40[0x40]; 4946 }; 4947 4948 struct mlx5_ifc_drain_dct_in_bits { 4949 u8 opcode[0x10]; 4950 u8 reserved_at_10[0x10]; 4951 4952 u8 reserved_at_20[0x10]; 4953 u8 op_mod[0x10]; 4954 4955 u8 reserved_at_40[0x8]; 4956 u8 dctn[0x18]; 4957 4958 u8 reserved_at_60[0x20]; 4959 }; 4960 4961 struct mlx5_ifc_disable_hca_out_bits { 4962 u8 status[0x8]; 4963 u8 reserved_at_8[0x18]; 4964 4965 u8 syndrome[0x20]; 4966 4967 u8 reserved_at_40[0x20]; 4968 }; 4969 4970 struct mlx5_ifc_disable_hca_in_bits { 4971 u8 opcode[0x10]; 4972 u8 reserved_at_10[0x10]; 4973 4974 u8 reserved_at_20[0x10]; 4975 u8 op_mod[0x10]; 4976 4977 u8 reserved_at_40[0x10]; 4978 u8 function_id[0x10]; 4979 4980 u8 reserved_at_60[0x20]; 4981 }; 4982 4983 struct mlx5_ifc_detach_from_mcg_out_bits { 4984 u8 status[0x8]; 4985 u8 reserved_at_8[0x18]; 4986 4987 u8 syndrome[0x20]; 4988 4989 u8 reserved_at_40[0x40]; 4990 }; 4991 4992 struct mlx5_ifc_detach_from_mcg_in_bits { 4993 u8 opcode[0x10]; 4994 u8 reserved_at_10[0x10]; 4995 4996 u8 reserved_at_20[0x10]; 4997 u8 op_mod[0x10]; 4998 4999 u8 reserved_at_40[0x8]; 5000 u8 qpn[0x18]; 5001 5002 u8 reserved_at_60[0x20]; 5003 5004 u8 multicast_gid[16][0x8]; 5005 }; 5006 5007 struct mlx5_ifc_destroy_xrc_srq_out_bits { 5008 u8 status[0x8]; 5009 u8 reserved_at_8[0x18]; 5010 5011 u8 syndrome[0x20]; 5012 5013 u8 reserved_at_40[0x40]; 5014 }; 5015 5016 struct mlx5_ifc_destroy_xrc_srq_in_bits { 5017 u8 opcode[0x10]; 5018 u8 reserved_at_10[0x10]; 5019 5020 u8 reserved_at_20[0x10]; 5021 u8 op_mod[0x10]; 5022 5023 u8 reserved_at_40[0x8]; 5024 u8 xrc_srqn[0x18]; 5025 5026 u8 reserved_at_60[0x20]; 5027 }; 5028 5029 struct mlx5_ifc_destroy_tis_out_bits { 5030 u8 status[0x8]; 5031 u8 reserved_at_8[0x18]; 5032 5033 u8 syndrome[0x20]; 5034 5035 u8 reserved_at_40[0x40]; 5036 }; 5037 5038 struct mlx5_ifc_destroy_tis_in_bits { 5039 u8 opcode[0x10]; 5040 u8 reserved_at_10[0x10]; 5041 5042 u8 reserved_at_20[0x10]; 5043 u8 op_mod[0x10]; 5044 5045 u8 reserved_at_40[0x8]; 5046 u8 tisn[0x18]; 5047 5048 u8 reserved_at_60[0x20]; 5049 }; 5050 5051 struct mlx5_ifc_destroy_tir_out_bits { 5052 u8 status[0x8]; 5053 u8 reserved_at_8[0x18]; 5054 5055 u8 syndrome[0x20]; 5056 5057 u8 reserved_at_40[0x40]; 5058 }; 5059 5060 struct mlx5_ifc_destroy_tir_in_bits { 5061 u8 opcode[0x10]; 5062 u8 reserved_at_10[0x10]; 5063 5064 u8 reserved_at_20[0x10]; 5065 u8 op_mod[0x10]; 5066 5067 u8 reserved_at_40[0x8]; 5068 u8 tirn[0x18]; 5069 5070 u8 reserved_at_60[0x20]; 5071 }; 5072 5073 struct mlx5_ifc_destroy_srq_out_bits { 5074 u8 status[0x8]; 5075 u8 reserved_at_8[0x18]; 5076 5077 u8 syndrome[0x20]; 5078 5079 u8 reserved_at_40[0x40]; 5080 }; 5081 5082 struct mlx5_ifc_destroy_srq_in_bits { 5083 u8 opcode[0x10]; 5084 u8 reserved_at_10[0x10]; 5085 5086 u8 reserved_at_20[0x10]; 5087 u8 op_mod[0x10]; 5088 5089 u8 reserved_at_40[0x8]; 5090 u8 srqn[0x18]; 5091 5092 u8 reserved_at_60[0x20]; 5093 }; 5094 5095 struct mlx5_ifc_destroy_sq_out_bits { 5096 u8 status[0x8]; 5097 u8 reserved_at_8[0x18]; 5098 5099 u8 syndrome[0x20]; 5100 5101 u8 reserved_at_40[0x40]; 5102 }; 5103 5104 struct mlx5_ifc_destroy_sq_in_bits { 5105 u8 opcode[0x10]; 5106 u8 reserved_at_10[0x10]; 5107 5108 u8 reserved_at_20[0x10]; 5109 u8 op_mod[0x10]; 5110 5111 u8 reserved_at_40[0x8]; 5112 u8 sqn[0x18]; 5113 5114 u8 reserved_at_60[0x20]; 5115 }; 5116 5117 struct mlx5_ifc_destroy_rqt_out_bits { 5118 u8 status[0x8]; 5119 u8 reserved_at_8[0x18]; 5120 5121 u8 syndrome[0x20]; 5122 5123 u8 reserved_at_40[0x40]; 5124 }; 5125 5126 struct mlx5_ifc_destroy_rqt_in_bits { 5127 u8 opcode[0x10]; 5128 u8 reserved_at_10[0x10]; 5129 5130 u8 reserved_at_20[0x10]; 5131 u8 op_mod[0x10]; 5132 5133 u8 reserved_at_40[0x8]; 5134 u8 rqtn[0x18]; 5135 5136 u8 reserved_at_60[0x20]; 5137 }; 5138 5139 struct mlx5_ifc_destroy_rq_out_bits { 5140 u8 status[0x8]; 5141 u8 reserved_at_8[0x18]; 5142 5143 u8 syndrome[0x20]; 5144 5145 u8 reserved_at_40[0x40]; 5146 }; 5147 5148 struct mlx5_ifc_destroy_rq_in_bits { 5149 u8 opcode[0x10]; 5150 u8 reserved_at_10[0x10]; 5151 5152 u8 reserved_at_20[0x10]; 5153 u8 op_mod[0x10]; 5154 5155 u8 reserved_at_40[0x8]; 5156 u8 rqn[0x18]; 5157 5158 u8 reserved_at_60[0x20]; 5159 }; 5160 5161 struct mlx5_ifc_destroy_rmp_out_bits { 5162 u8 status[0x8]; 5163 u8 reserved_at_8[0x18]; 5164 5165 u8 syndrome[0x20]; 5166 5167 u8 reserved_at_40[0x40]; 5168 }; 5169 5170 struct mlx5_ifc_destroy_rmp_in_bits { 5171 u8 opcode[0x10]; 5172 u8 reserved_at_10[0x10]; 5173 5174 u8 reserved_at_20[0x10]; 5175 u8 op_mod[0x10]; 5176 5177 u8 reserved_at_40[0x8]; 5178 u8 rmpn[0x18]; 5179 5180 u8 reserved_at_60[0x20]; 5181 }; 5182 5183 struct mlx5_ifc_destroy_qp_out_bits { 5184 u8 status[0x8]; 5185 u8 reserved_at_8[0x18]; 5186 5187 u8 syndrome[0x20]; 5188 5189 u8 reserved_at_40[0x40]; 5190 }; 5191 5192 struct mlx5_ifc_destroy_qp_in_bits { 5193 u8 opcode[0x10]; 5194 u8 reserved_at_10[0x10]; 5195 5196 u8 reserved_at_20[0x10]; 5197 u8 op_mod[0x10]; 5198 5199 u8 reserved_at_40[0x8]; 5200 u8 qpn[0x18]; 5201 5202 u8 reserved_at_60[0x20]; 5203 }; 5204 5205 struct mlx5_ifc_destroy_psv_out_bits { 5206 u8 status[0x8]; 5207 u8 reserved_at_8[0x18]; 5208 5209 u8 syndrome[0x20]; 5210 5211 u8 reserved_at_40[0x40]; 5212 }; 5213 5214 struct mlx5_ifc_destroy_psv_in_bits { 5215 u8 opcode[0x10]; 5216 u8 reserved_at_10[0x10]; 5217 5218 u8 reserved_at_20[0x10]; 5219 u8 op_mod[0x10]; 5220 5221 u8 reserved_at_40[0x8]; 5222 u8 psvn[0x18]; 5223 5224 u8 reserved_at_60[0x20]; 5225 }; 5226 5227 struct mlx5_ifc_destroy_mkey_out_bits { 5228 u8 status[0x8]; 5229 u8 reserved_at_8[0x18]; 5230 5231 u8 syndrome[0x20]; 5232 5233 u8 reserved_at_40[0x40]; 5234 }; 5235 5236 struct mlx5_ifc_destroy_mkey_in_bits { 5237 u8 opcode[0x10]; 5238 u8 reserved_at_10[0x10]; 5239 5240 u8 reserved_at_20[0x10]; 5241 u8 op_mod[0x10]; 5242 5243 u8 reserved_at_40[0x8]; 5244 u8 mkey_index[0x18]; 5245 5246 u8 reserved_at_60[0x20]; 5247 }; 5248 5249 struct mlx5_ifc_destroy_flow_table_out_bits { 5250 u8 status[0x8]; 5251 u8 reserved_at_8[0x18]; 5252 5253 u8 syndrome[0x20]; 5254 5255 u8 reserved_at_40[0x40]; 5256 }; 5257 5258 struct mlx5_ifc_destroy_flow_table_in_bits { 5259 u8 opcode[0x10]; 5260 u8 reserved_at_10[0x10]; 5261 5262 u8 reserved_at_20[0x10]; 5263 u8 op_mod[0x10]; 5264 5265 u8 other_vport[0x1]; 5266 u8 reserved_at_41[0xf]; 5267 u8 vport_number[0x10]; 5268 5269 u8 reserved_at_60[0x20]; 5270 5271 u8 table_type[0x8]; 5272 u8 reserved_at_88[0x18]; 5273 5274 u8 reserved_at_a0[0x8]; 5275 u8 table_id[0x18]; 5276 5277 u8 reserved_at_c0[0x140]; 5278 }; 5279 5280 struct mlx5_ifc_destroy_flow_group_out_bits { 5281 u8 status[0x8]; 5282 u8 reserved_at_8[0x18]; 5283 5284 u8 syndrome[0x20]; 5285 5286 u8 reserved_at_40[0x40]; 5287 }; 5288 5289 struct mlx5_ifc_destroy_flow_group_in_bits { 5290 u8 opcode[0x10]; 5291 u8 reserved_at_10[0x10]; 5292 5293 u8 reserved_at_20[0x10]; 5294 u8 op_mod[0x10]; 5295 5296 u8 other_vport[0x1]; 5297 u8 reserved_at_41[0xf]; 5298 u8 vport_number[0x10]; 5299 5300 u8 reserved_at_60[0x20]; 5301 5302 u8 table_type[0x8]; 5303 u8 reserved_at_88[0x18]; 5304 5305 u8 reserved_at_a0[0x8]; 5306 u8 table_id[0x18]; 5307 5308 u8 group_id[0x20]; 5309 5310 u8 reserved_at_e0[0x120]; 5311 }; 5312 5313 struct mlx5_ifc_destroy_eq_out_bits { 5314 u8 status[0x8]; 5315 u8 reserved_at_8[0x18]; 5316 5317 u8 syndrome[0x20]; 5318 5319 u8 reserved_at_40[0x40]; 5320 }; 5321 5322 struct mlx5_ifc_destroy_eq_in_bits { 5323 u8 opcode[0x10]; 5324 u8 reserved_at_10[0x10]; 5325 5326 u8 reserved_at_20[0x10]; 5327 u8 op_mod[0x10]; 5328 5329 u8 reserved_at_40[0x18]; 5330 u8 eq_number[0x8]; 5331 5332 u8 reserved_at_60[0x20]; 5333 }; 5334 5335 struct mlx5_ifc_destroy_dct_out_bits { 5336 u8 status[0x8]; 5337 u8 reserved_at_8[0x18]; 5338 5339 u8 syndrome[0x20]; 5340 5341 u8 reserved_at_40[0x40]; 5342 }; 5343 5344 struct mlx5_ifc_destroy_dct_in_bits { 5345 u8 opcode[0x10]; 5346 u8 reserved_at_10[0x10]; 5347 5348 u8 reserved_at_20[0x10]; 5349 u8 op_mod[0x10]; 5350 5351 u8 reserved_at_40[0x8]; 5352 u8 dctn[0x18]; 5353 5354 u8 reserved_at_60[0x20]; 5355 }; 5356 5357 struct mlx5_ifc_destroy_cq_out_bits { 5358 u8 status[0x8]; 5359 u8 reserved_at_8[0x18]; 5360 5361 u8 syndrome[0x20]; 5362 5363 u8 reserved_at_40[0x40]; 5364 }; 5365 5366 struct mlx5_ifc_destroy_cq_in_bits { 5367 u8 opcode[0x10]; 5368 u8 reserved_at_10[0x10]; 5369 5370 u8 reserved_at_20[0x10]; 5371 u8 op_mod[0x10]; 5372 5373 u8 reserved_at_40[0x8]; 5374 u8 cqn[0x18]; 5375 5376 u8 reserved_at_60[0x20]; 5377 }; 5378 5379 struct mlx5_ifc_delete_vxlan_udp_dport_out_bits { 5380 u8 status[0x8]; 5381 u8 reserved_at_8[0x18]; 5382 5383 u8 syndrome[0x20]; 5384 5385 u8 reserved_at_40[0x40]; 5386 }; 5387 5388 struct mlx5_ifc_delete_vxlan_udp_dport_in_bits { 5389 u8 opcode[0x10]; 5390 u8 reserved_at_10[0x10]; 5391 5392 u8 reserved_at_20[0x10]; 5393 u8 op_mod[0x10]; 5394 5395 u8 reserved_at_40[0x20]; 5396 5397 u8 reserved_at_60[0x10]; 5398 u8 vxlan_udp_port[0x10]; 5399 }; 5400 5401 struct mlx5_ifc_delete_l2_table_entry_out_bits { 5402 u8 status[0x8]; 5403 u8 reserved_at_8[0x18]; 5404 5405 u8 syndrome[0x20]; 5406 5407 u8 reserved_at_40[0x40]; 5408 }; 5409 5410 struct mlx5_ifc_delete_l2_table_entry_in_bits { 5411 u8 opcode[0x10]; 5412 u8 reserved_at_10[0x10]; 5413 5414 u8 reserved_at_20[0x10]; 5415 u8 op_mod[0x10]; 5416 5417 u8 reserved_at_40[0x60]; 5418 5419 u8 reserved_at_a0[0x8]; 5420 u8 table_index[0x18]; 5421 5422 u8 reserved_at_c0[0x140]; 5423 }; 5424 5425 struct mlx5_ifc_delete_fte_out_bits { 5426 u8 status[0x8]; 5427 u8 reserved_at_8[0x18]; 5428 5429 u8 syndrome[0x20]; 5430 5431 u8 reserved_at_40[0x40]; 5432 }; 5433 5434 struct mlx5_ifc_delete_fte_in_bits { 5435 u8 opcode[0x10]; 5436 u8 reserved_at_10[0x10]; 5437 5438 u8 reserved_at_20[0x10]; 5439 u8 op_mod[0x10]; 5440 5441 u8 other_vport[0x1]; 5442 u8 reserved_at_41[0xf]; 5443 u8 vport_number[0x10]; 5444 5445 u8 reserved_at_60[0x20]; 5446 5447 u8 table_type[0x8]; 5448 u8 reserved_at_88[0x18]; 5449 5450 u8 reserved_at_a0[0x8]; 5451 u8 table_id[0x18]; 5452 5453 u8 reserved_at_c0[0x40]; 5454 5455 u8 flow_index[0x20]; 5456 5457 u8 reserved_at_120[0xe0]; 5458 }; 5459 5460 struct mlx5_ifc_dealloc_xrcd_out_bits { 5461 u8 status[0x8]; 5462 u8 reserved_at_8[0x18]; 5463 5464 u8 syndrome[0x20]; 5465 5466 u8 reserved_at_40[0x40]; 5467 }; 5468 5469 struct mlx5_ifc_dealloc_xrcd_in_bits { 5470 u8 opcode[0x10]; 5471 u8 reserved_at_10[0x10]; 5472 5473 u8 reserved_at_20[0x10]; 5474 u8 op_mod[0x10]; 5475 5476 u8 reserved_at_40[0x8]; 5477 u8 xrcd[0x18]; 5478 5479 u8 reserved_at_60[0x20]; 5480 }; 5481 5482 struct mlx5_ifc_dealloc_uar_out_bits { 5483 u8 status[0x8]; 5484 u8 reserved_at_8[0x18]; 5485 5486 u8 syndrome[0x20]; 5487 5488 u8 reserved_at_40[0x40]; 5489 }; 5490 5491 struct mlx5_ifc_dealloc_uar_in_bits { 5492 u8 opcode[0x10]; 5493 u8 reserved_at_10[0x10]; 5494 5495 u8 reserved_at_20[0x10]; 5496 u8 op_mod[0x10]; 5497 5498 u8 reserved_at_40[0x8]; 5499 u8 uar[0x18]; 5500 5501 u8 reserved_at_60[0x20]; 5502 }; 5503 5504 struct mlx5_ifc_dealloc_transport_domain_out_bits { 5505 u8 status[0x8]; 5506 u8 reserved_at_8[0x18]; 5507 5508 u8 syndrome[0x20]; 5509 5510 u8 reserved_at_40[0x40]; 5511 }; 5512 5513 struct mlx5_ifc_dealloc_transport_domain_in_bits { 5514 u8 opcode[0x10]; 5515 u8 reserved_at_10[0x10]; 5516 5517 u8 reserved_at_20[0x10]; 5518 u8 op_mod[0x10]; 5519 5520 u8 reserved_at_40[0x8]; 5521 u8 transport_domain[0x18]; 5522 5523 u8 reserved_at_60[0x20]; 5524 }; 5525 5526 struct mlx5_ifc_dealloc_q_counter_out_bits { 5527 u8 status[0x8]; 5528 u8 reserved_at_8[0x18]; 5529 5530 u8 syndrome[0x20]; 5531 5532 u8 reserved_at_40[0x40]; 5533 }; 5534 5535 struct mlx5_ifc_dealloc_q_counter_in_bits { 5536 u8 opcode[0x10]; 5537 u8 reserved_at_10[0x10]; 5538 5539 u8 reserved_at_20[0x10]; 5540 u8 op_mod[0x10]; 5541 5542 u8 reserved_at_40[0x18]; 5543 u8 counter_set_id[0x8]; 5544 5545 u8 reserved_at_60[0x20]; 5546 }; 5547 5548 struct mlx5_ifc_dealloc_pd_out_bits { 5549 u8 status[0x8]; 5550 u8 reserved_at_8[0x18]; 5551 5552 u8 syndrome[0x20]; 5553 5554 u8 reserved_at_40[0x40]; 5555 }; 5556 5557 struct mlx5_ifc_dealloc_pd_in_bits { 5558 u8 opcode[0x10]; 5559 u8 reserved_at_10[0x10]; 5560 5561 u8 reserved_at_20[0x10]; 5562 u8 op_mod[0x10]; 5563 5564 u8 reserved_at_40[0x8]; 5565 u8 pd[0x18]; 5566 5567 u8 reserved_at_60[0x20]; 5568 }; 5569 5570 struct mlx5_ifc_dealloc_flow_counter_out_bits { 5571 u8 status[0x8]; 5572 u8 reserved_at_8[0x18]; 5573 5574 u8 syndrome[0x20]; 5575 5576 u8 reserved_at_40[0x40]; 5577 }; 5578 5579 struct mlx5_ifc_dealloc_flow_counter_in_bits { 5580 u8 opcode[0x10]; 5581 u8 reserved_at_10[0x10]; 5582 5583 u8 reserved_at_20[0x10]; 5584 u8 op_mod[0x10]; 5585 5586 u8 reserved_at_40[0x10]; 5587 u8 flow_counter_id[0x10]; 5588 5589 u8 reserved_at_60[0x20]; 5590 }; 5591 5592 struct mlx5_ifc_create_xrc_srq_out_bits { 5593 u8 status[0x8]; 5594 u8 reserved_at_8[0x18]; 5595 5596 u8 syndrome[0x20]; 5597 5598 u8 reserved_at_40[0x8]; 5599 u8 xrc_srqn[0x18]; 5600 5601 u8 reserved_at_60[0x20]; 5602 }; 5603 5604 struct mlx5_ifc_create_xrc_srq_in_bits { 5605 u8 opcode[0x10]; 5606 u8 reserved_at_10[0x10]; 5607 5608 u8 reserved_at_20[0x10]; 5609 u8 op_mod[0x10]; 5610 5611 u8 reserved_at_40[0x40]; 5612 5613 struct mlx5_ifc_xrc_srqc_bits xrc_srq_context_entry; 5614 5615 u8 reserved_at_280[0x600]; 5616 5617 u8 pas[0][0x40]; 5618 }; 5619 5620 struct mlx5_ifc_create_tis_out_bits { 5621 u8 status[0x8]; 5622 u8 reserved_at_8[0x18]; 5623 5624 u8 syndrome[0x20]; 5625 5626 u8 reserved_at_40[0x8]; 5627 u8 tisn[0x18]; 5628 5629 u8 reserved_at_60[0x20]; 5630 }; 5631 5632 struct mlx5_ifc_create_tis_in_bits { 5633 u8 opcode[0x10]; 5634 u8 reserved_at_10[0x10]; 5635 5636 u8 reserved_at_20[0x10]; 5637 u8 op_mod[0x10]; 5638 5639 u8 reserved_at_40[0xc0]; 5640 5641 struct mlx5_ifc_tisc_bits ctx; 5642 }; 5643 5644 struct mlx5_ifc_create_tir_out_bits { 5645 u8 status[0x8]; 5646 u8 reserved_at_8[0x18]; 5647 5648 u8 syndrome[0x20]; 5649 5650 u8 reserved_at_40[0x8]; 5651 u8 tirn[0x18]; 5652 5653 u8 reserved_at_60[0x20]; 5654 }; 5655 5656 struct mlx5_ifc_create_tir_in_bits { 5657 u8 opcode[0x10]; 5658 u8 reserved_at_10[0x10]; 5659 5660 u8 reserved_at_20[0x10]; 5661 u8 op_mod[0x10]; 5662 5663 u8 reserved_at_40[0xc0]; 5664 5665 struct mlx5_ifc_tirc_bits ctx; 5666 }; 5667 5668 struct mlx5_ifc_create_srq_out_bits { 5669 u8 status[0x8]; 5670 u8 reserved_at_8[0x18]; 5671 5672 u8 syndrome[0x20]; 5673 5674 u8 reserved_at_40[0x8]; 5675 u8 srqn[0x18]; 5676 5677 u8 reserved_at_60[0x20]; 5678 }; 5679 5680 struct mlx5_ifc_create_srq_in_bits { 5681 u8 opcode[0x10]; 5682 u8 reserved_at_10[0x10]; 5683 5684 u8 reserved_at_20[0x10]; 5685 u8 op_mod[0x10]; 5686 5687 u8 reserved_at_40[0x40]; 5688 5689 struct mlx5_ifc_srqc_bits srq_context_entry; 5690 5691 u8 reserved_at_280[0x600]; 5692 5693 u8 pas[0][0x40]; 5694 }; 5695 5696 struct mlx5_ifc_create_sq_out_bits { 5697 u8 status[0x8]; 5698 u8 reserved_at_8[0x18]; 5699 5700 u8 syndrome[0x20]; 5701 5702 u8 reserved_at_40[0x8]; 5703 u8 sqn[0x18]; 5704 5705 u8 reserved_at_60[0x20]; 5706 }; 5707 5708 struct mlx5_ifc_create_sq_in_bits { 5709 u8 opcode[0x10]; 5710 u8 reserved_at_10[0x10]; 5711 5712 u8 reserved_at_20[0x10]; 5713 u8 op_mod[0x10]; 5714 5715 u8 reserved_at_40[0xc0]; 5716 5717 struct mlx5_ifc_sqc_bits ctx; 5718 }; 5719 5720 struct mlx5_ifc_create_rqt_out_bits { 5721 u8 status[0x8]; 5722 u8 reserved_at_8[0x18]; 5723 5724 u8 syndrome[0x20]; 5725 5726 u8 reserved_at_40[0x8]; 5727 u8 rqtn[0x18]; 5728 5729 u8 reserved_at_60[0x20]; 5730 }; 5731 5732 struct mlx5_ifc_create_rqt_in_bits { 5733 u8 opcode[0x10]; 5734 u8 reserved_at_10[0x10]; 5735 5736 u8 reserved_at_20[0x10]; 5737 u8 op_mod[0x10]; 5738 5739 u8 reserved_at_40[0xc0]; 5740 5741 struct mlx5_ifc_rqtc_bits rqt_context; 5742 }; 5743 5744 struct mlx5_ifc_create_rq_out_bits { 5745 u8 status[0x8]; 5746 u8 reserved_at_8[0x18]; 5747 5748 u8 syndrome[0x20]; 5749 5750 u8 reserved_at_40[0x8]; 5751 u8 rqn[0x18]; 5752 5753 u8 reserved_at_60[0x20]; 5754 }; 5755 5756 struct mlx5_ifc_create_rq_in_bits { 5757 u8 opcode[0x10]; 5758 u8 reserved_at_10[0x10]; 5759 5760 u8 reserved_at_20[0x10]; 5761 u8 op_mod[0x10]; 5762 5763 u8 reserved_at_40[0xc0]; 5764 5765 struct mlx5_ifc_rqc_bits ctx; 5766 }; 5767 5768 struct mlx5_ifc_create_rmp_out_bits { 5769 u8 status[0x8]; 5770 u8 reserved_at_8[0x18]; 5771 5772 u8 syndrome[0x20]; 5773 5774 u8 reserved_at_40[0x8]; 5775 u8 rmpn[0x18]; 5776 5777 u8 reserved_at_60[0x20]; 5778 }; 5779 5780 struct mlx5_ifc_create_rmp_in_bits { 5781 u8 opcode[0x10]; 5782 u8 reserved_at_10[0x10]; 5783 5784 u8 reserved_at_20[0x10]; 5785 u8 op_mod[0x10]; 5786 5787 u8 reserved_at_40[0xc0]; 5788 5789 struct mlx5_ifc_rmpc_bits ctx; 5790 }; 5791 5792 struct mlx5_ifc_create_qp_out_bits { 5793 u8 status[0x8]; 5794 u8 reserved_at_8[0x18]; 5795 5796 u8 syndrome[0x20]; 5797 5798 u8 reserved_at_40[0x8]; 5799 u8 qpn[0x18]; 5800 5801 u8 reserved_at_60[0x20]; 5802 }; 5803 5804 struct mlx5_ifc_create_qp_in_bits { 5805 u8 opcode[0x10]; 5806 u8 reserved_at_10[0x10]; 5807 5808 u8 reserved_at_20[0x10]; 5809 u8 op_mod[0x10]; 5810 5811 u8 reserved_at_40[0x40]; 5812 5813 u8 opt_param_mask[0x20]; 5814 5815 u8 reserved_at_a0[0x20]; 5816 5817 struct mlx5_ifc_qpc_bits qpc; 5818 5819 u8 reserved_at_800[0x80]; 5820 5821 u8 pas[0][0x40]; 5822 }; 5823 5824 struct mlx5_ifc_create_psv_out_bits { 5825 u8 status[0x8]; 5826 u8 reserved_at_8[0x18]; 5827 5828 u8 syndrome[0x20]; 5829 5830 u8 reserved_at_40[0x40]; 5831 5832 u8 reserved_at_80[0x8]; 5833 u8 psv0_index[0x18]; 5834 5835 u8 reserved_at_a0[0x8]; 5836 u8 psv1_index[0x18]; 5837 5838 u8 reserved_at_c0[0x8]; 5839 u8 psv2_index[0x18]; 5840 5841 u8 reserved_at_e0[0x8]; 5842 u8 psv3_index[0x18]; 5843 }; 5844 5845 struct mlx5_ifc_create_psv_in_bits { 5846 u8 opcode[0x10]; 5847 u8 reserved_at_10[0x10]; 5848 5849 u8 reserved_at_20[0x10]; 5850 u8 op_mod[0x10]; 5851 5852 u8 num_psv[0x4]; 5853 u8 reserved_at_44[0x4]; 5854 u8 pd[0x18]; 5855 5856 u8 reserved_at_60[0x20]; 5857 }; 5858 5859 struct mlx5_ifc_create_mkey_out_bits { 5860 u8 status[0x8]; 5861 u8 reserved_at_8[0x18]; 5862 5863 u8 syndrome[0x20]; 5864 5865 u8 reserved_at_40[0x8]; 5866 u8 mkey_index[0x18]; 5867 5868 u8 reserved_at_60[0x20]; 5869 }; 5870 5871 struct mlx5_ifc_create_mkey_in_bits { 5872 u8 opcode[0x10]; 5873 u8 reserved_at_10[0x10]; 5874 5875 u8 reserved_at_20[0x10]; 5876 u8 op_mod[0x10]; 5877 5878 u8 reserved_at_40[0x20]; 5879 5880 u8 pg_access[0x1]; 5881 u8 reserved_at_61[0x1f]; 5882 5883 struct mlx5_ifc_mkc_bits memory_key_mkey_entry; 5884 5885 u8 reserved_at_280[0x80]; 5886 5887 u8 translations_octword_actual_size[0x20]; 5888 5889 u8 reserved_at_320[0x560]; 5890 5891 u8 klm_pas_mtt[0][0x20]; 5892 }; 5893 5894 struct mlx5_ifc_create_flow_table_out_bits { 5895 u8 status[0x8]; 5896 u8 reserved_at_8[0x18]; 5897 5898 u8 syndrome[0x20]; 5899 5900 u8 reserved_at_40[0x8]; 5901 u8 table_id[0x18]; 5902 5903 u8 reserved_at_60[0x20]; 5904 }; 5905 5906 struct mlx5_ifc_create_flow_table_in_bits { 5907 u8 opcode[0x10]; 5908 u8 reserved_at_10[0x10]; 5909 5910 u8 reserved_at_20[0x10]; 5911 u8 op_mod[0x10]; 5912 5913 u8 other_vport[0x1]; 5914 u8 reserved_at_41[0xf]; 5915 u8 vport_number[0x10]; 5916 5917 u8 reserved_at_60[0x20]; 5918 5919 u8 table_type[0x8]; 5920 u8 reserved_at_88[0x18]; 5921 5922 u8 reserved_at_a0[0x20]; 5923 5924 u8 reserved_at_c0[0x4]; 5925 u8 table_miss_mode[0x4]; 5926 u8 level[0x8]; 5927 u8 reserved_at_d0[0x8]; 5928 u8 log_size[0x8]; 5929 5930 u8 reserved_at_e0[0x8]; 5931 u8 table_miss_id[0x18]; 5932 5933 u8 reserved_at_100[0x100]; 5934 }; 5935 5936 struct mlx5_ifc_create_flow_group_out_bits { 5937 u8 status[0x8]; 5938 u8 reserved_at_8[0x18]; 5939 5940 u8 syndrome[0x20]; 5941 5942 u8 reserved_at_40[0x8]; 5943 u8 group_id[0x18]; 5944 5945 u8 reserved_at_60[0x20]; 5946 }; 5947 5948 enum { 5949 MLX5_CREATE_FLOW_GROUP_IN_MATCH_CRITERIA_ENABLE_OUTER_HEADERS = 0x0, 5950 MLX5_CREATE_FLOW_GROUP_IN_MATCH_CRITERIA_ENABLE_MISC_PARAMETERS = 0x1, 5951 MLX5_CREATE_FLOW_GROUP_IN_MATCH_CRITERIA_ENABLE_INNER_HEADERS = 0x2, 5952 }; 5953 5954 struct mlx5_ifc_create_flow_group_in_bits { 5955 u8 opcode[0x10]; 5956 u8 reserved_at_10[0x10]; 5957 5958 u8 reserved_at_20[0x10]; 5959 u8 op_mod[0x10]; 5960 5961 u8 other_vport[0x1]; 5962 u8 reserved_at_41[0xf]; 5963 u8 vport_number[0x10]; 5964 5965 u8 reserved_at_60[0x20]; 5966 5967 u8 table_type[0x8]; 5968 u8 reserved_at_88[0x18]; 5969 5970 u8 reserved_at_a0[0x8]; 5971 u8 table_id[0x18]; 5972 5973 u8 reserved_at_c0[0x20]; 5974 5975 u8 start_flow_index[0x20]; 5976 5977 u8 reserved_at_100[0x20]; 5978 5979 u8 end_flow_index[0x20]; 5980 5981 u8 reserved_at_140[0xa0]; 5982 5983 u8 reserved_at_1e0[0x18]; 5984 u8 match_criteria_enable[0x8]; 5985 5986 struct mlx5_ifc_fte_match_param_bits match_criteria; 5987 5988 u8 reserved_at_1200[0xe00]; 5989 }; 5990 5991 struct mlx5_ifc_create_eq_out_bits { 5992 u8 status[0x8]; 5993 u8 reserved_at_8[0x18]; 5994 5995 u8 syndrome[0x20]; 5996 5997 u8 reserved_at_40[0x18]; 5998 u8 eq_number[0x8]; 5999 6000 u8 reserved_at_60[0x20]; 6001 }; 6002 6003 struct mlx5_ifc_create_eq_in_bits { 6004 u8 opcode[0x10]; 6005 u8 reserved_at_10[0x10]; 6006 6007 u8 reserved_at_20[0x10]; 6008 u8 op_mod[0x10]; 6009 6010 u8 reserved_at_40[0x40]; 6011 6012 struct mlx5_ifc_eqc_bits eq_context_entry; 6013 6014 u8 reserved_at_280[0x40]; 6015 6016 u8 event_bitmask[0x40]; 6017 6018 u8 reserved_at_300[0x580]; 6019 6020 u8 pas[0][0x40]; 6021 }; 6022 6023 struct mlx5_ifc_create_dct_out_bits { 6024 u8 status[0x8]; 6025 u8 reserved_at_8[0x18]; 6026 6027 u8 syndrome[0x20]; 6028 6029 u8 reserved_at_40[0x8]; 6030 u8 dctn[0x18]; 6031 6032 u8 reserved_at_60[0x20]; 6033 }; 6034 6035 struct mlx5_ifc_create_dct_in_bits { 6036 u8 opcode[0x10]; 6037 u8 reserved_at_10[0x10]; 6038 6039 u8 reserved_at_20[0x10]; 6040 u8 op_mod[0x10]; 6041 6042 u8 reserved_at_40[0x40]; 6043 6044 struct mlx5_ifc_dctc_bits dct_context_entry; 6045 6046 u8 reserved_at_280[0x180]; 6047 }; 6048 6049 struct mlx5_ifc_create_cq_out_bits { 6050 u8 status[0x8]; 6051 u8 reserved_at_8[0x18]; 6052 6053 u8 syndrome[0x20]; 6054 6055 u8 reserved_at_40[0x8]; 6056 u8 cqn[0x18]; 6057 6058 u8 reserved_at_60[0x20]; 6059 }; 6060 6061 struct mlx5_ifc_create_cq_in_bits { 6062 u8 opcode[0x10]; 6063 u8 reserved_at_10[0x10]; 6064 6065 u8 reserved_at_20[0x10]; 6066 u8 op_mod[0x10]; 6067 6068 u8 reserved_at_40[0x40]; 6069 6070 struct mlx5_ifc_cqc_bits cq_context; 6071 6072 u8 reserved_at_280[0x600]; 6073 6074 u8 pas[0][0x40]; 6075 }; 6076 6077 struct mlx5_ifc_config_int_moderation_out_bits { 6078 u8 status[0x8]; 6079 u8 reserved_at_8[0x18]; 6080 6081 u8 syndrome[0x20]; 6082 6083 u8 reserved_at_40[0x4]; 6084 u8 min_delay[0xc]; 6085 u8 int_vector[0x10]; 6086 6087 u8 reserved_at_60[0x20]; 6088 }; 6089 6090 enum { 6091 MLX5_CONFIG_INT_MODERATION_IN_OP_MOD_WRITE = 0x0, 6092 MLX5_CONFIG_INT_MODERATION_IN_OP_MOD_READ = 0x1, 6093 }; 6094 6095 struct mlx5_ifc_config_int_moderation_in_bits { 6096 u8 opcode[0x10]; 6097 u8 reserved_at_10[0x10]; 6098 6099 u8 reserved_at_20[0x10]; 6100 u8 op_mod[0x10]; 6101 6102 u8 reserved_at_40[0x4]; 6103 u8 min_delay[0xc]; 6104 u8 int_vector[0x10]; 6105 6106 u8 reserved_at_60[0x20]; 6107 }; 6108 6109 struct mlx5_ifc_attach_to_mcg_out_bits { 6110 u8 status[0x8]; 6111 u8 reserved_at_8[0x18]; 6112 6113 u8 syndrome[0x20]; 6114 6115 u8 reserved_at_40[0x40]; 6116 }; 6117 6118 struct mlx5_ifc_attach_to_mcg_in_bits { 6119 u8 opcode[0x10]; 6120 u8 reserved_at_10[0x10]; 6121 6122 u8 reserved_at_20[0x10]; 6123 u8 op_mod[0x10]; 6124 6125 u8 reserved_at_40[0x8]; 6126 u8 qpn[0x18]; 6127 6128 u8 reserved_at_60[0x20]; 6129 6130 u8 multicast_gid[16][0x8]; 6131 }; 6132 6133 struct mlx5_ifc_arm_xrc_srq_out_bits { 6134 u8 status[0x8]; 6135 u8 reserved_at_8[0x18]; 6136 6137 u8 syndrome[0x20]; 6138 6139 u8 reserved_at_40[0x40]; 6140 }; 6141 6142 enum { 6143 MLX5_ARM_XRC_SRQ_IN_OP_MOD_XRC_SRQ = 0x1, 6144 }; 6145 6146 struct mlx5_ifc_arm_xrc_srq_in_bits { 6147 u8 opcode[0x10]; 6148 u8 reserved_at_10[0x10]; 6149 6150 u8 reserved_at_20[0x10]; 6151 u8 op_mod[0x10]; 6152 6153 u8 reserved_at_40[0x8]; 6154 u8 xrc_srqn[0x18]; 6155 6156 u8 reserved_at_60[0x10]; 6157 u8 lwm[0x10]; 6158 }; 6159 6160 struct mlx5_ifc_arm_rq_out_bits { 6161 u8 status[0x8]; 6162 u8 reserved_at_8[0x18]; 6163 6164 u8 syndrome[0x20]; 6165 6166 u8 reserved_at_40[0x40]; 6167 }; 6168 6169 enum { 6170 MLX5_ARM_RQ_IN_OP_MOD_SRQ_ = 0x1, 6171 }; 6172 6173 struct mlx5_ifc_arm_rq_in_bits { 6174 u8 opcode[0x10]; 6175 u8 reserved_at_10[0x10]; 6176 6177 u8 reserved_at_20[0x10]; 6178 u8 op_mod[0x10]; 6179 6180 u8 reserved_at_40[0x8]; 6181 u8 srq_number[0x18]; 6182 6183 u8 reserved_at_60[0x10]; 6184 u8 lwm[0x10]; 6185 }; 6186 6187 struct mlx5_ifc_arm_dct_out_bits { 6188 u8 status[0x8]; 6189 u8 reserved_at_8[0x18]; 6190 6191 u8 syndrome[0x20]; 6192 6193 u8 reserved_at_40[0x40]; 6194 }; 6195 6196 struct mlx5_ifc_arm_dct_in_bits { 6197 u8 opcode[0x10]; 6198 u8 reserved_at_10[0x10]; 6199 6200 u8 reserved_at_20[0x10]; 6201 u8 op_mod[0x10]; 6202 6203 u8 reserved_at_40[0x8]; 6204 u8 dct_number[0x18]; 6205 6206 u8 reserved_at_60[0x20]; 6207 }; 6208 6209 struct mlx5_ifc_alloc_xrcd_out_bits { 6210 u8 status[0x8]; 6211 u8 reserved_at_8[0x18]; 6212 6213 u8 syndrome[0x20]; 6214 6215 u8 reserved_at_40[0x8]; 6216 u8 xrcd[0x18]; 6217 6218 u8 reserved_at_60[0x20]; 6219 }; 6220 6221 struct mlx5_ifc_alloc_xrcd_in_bits { 6222 u8 opcode[0x10]; 6223 u8 reserved_at_10[0x10]; 6224 6225 u8 reserved_at_20[0x10]; 6226 u8 op_mod[0x10]; 6227 6228 u8 reserved_at_40[0x40]; 6229 }; 6230 6231 struct mlx5_ifc_alloc_uar_out_bits { 6232 u8 status[0x8]; 6233 u8 reserved_at_8[0x18]; 6234 6235 u8 syndrome[0x20]; 6236 6237 u8 reserved_at_40[0x8]; 6238 u8 uar[0x18]; 6239 6240 u8 reserved_at_60[0x20]; 6241 }; 6242 6243 struct mlx5_ifc_alloc_uar_in_bits { 6244 u8 opcode[0x10]; 6245 u8 reserved_at_10[0x10]; 6246 6247 u8 reserved_at_20[0x10]; 6248 u8 op_mod[0x10]; 6249 6250 u8 reserved_at_40[0x40]; 6251 }; 6252 6253 struct mlx5_ifc_alloc_transport_domain_out_bits { 6254 u8 status[0x8]; 6255 u8 reserved_at_8[0x18]; 6256 6257 u8 syndrome[0x20]; 6258 6259 u8 reserved_at_40[0x8]; 6260 u8 transport_domain[0x18]; 6261 6262 u8 reserved_at_60[0x20]; 6263 }; 6264 6265 struct mlx5_ifc_alloc_transport_domain_in_bits { 6266 u8 opcode[0x10]; 6267 u8 reserved_at_10[0x10]; 6268 6269 u8 reserved_at_20[0x10]; 6270 u8 op_mod[0x10]; 6271 6272 u8 reserved_at_40[0x40]; 6273 }; 6274 6275 struct mlx5_ifc_alloc_q_counter_out_bits { 6276 u8 status[0x8]; 6277 u8 reserved_at_8[0x18]; 6278 6279 u8 syndrome[0x20]; 6280 6281 u8 reserved_at_40[0x18]; 6282 u8 counter_set_id[0x8]; 6283 6284 u8 reserved_at_60[0x20]; 6285 }; 6286 6287 struct mlx5_ifc_alloc_q_counter_in_bits { 6288 u8 opcode[0x10]; 6289 u8 reserved_at_10[0x10]; 6290 6291 u8 reserved_at_20[0x10]; 6292 u8 op_mod[0x10]; 6293 6294 u8 reserved_at_40[0x40]; 6295 }; 6296 6297 struct mlx5_ifc_alloc_pd_out_bits { 6298 u8 status[0x8]; 6299 u8 reserved_at_8[0x18]; 6300 6301 u8 syndrome[0x20]; 6302 6303 u8 reserved_at_40[0x8]; 6304 u8 pd[0x18]; 6305 6306 u8 reserved_at_60[0x20]; 6307 }; 6308 6309 struct mlx5_ifc_alloc_pd_in_bits { 6310 u8 opcode[0x10]; 6311 u8 reserved_at_10[0x10]; 6312 6313 u8 reserved_at_20[0x10]; 6314 u8 op_mod[0x10]; 6315 6316 u8 reserved_at_40[0x40]; 6317 }; 6318 6319 struct mlx5_ifc_alloc_flow_counter_out_bits { 6320 u8 status[0x8]; 6321 u8 reserved_at_8[0x18]; 6322 6323 u8 syndrome[0x20]; 6324 6325 u8 reserved_at_40[0x10]; 6326 u8 flow_counter_id[0x10]; 6327 6328 u8 reserved_at_60[0x20]; 6329 }; 6330 6331 struct mlx5_ifc_alloc_flow_counter_in_bits { 6332 u8 opcode[0x10]; 6333 u8 reserved_at_10[0x10]; 6334 6335 u8 reserved_at_20[0x10]; 6336 u8 op_mod[0x10]; 6337 6338 u8 reserved_at_40[0x40]; 6339 }; 6340 6341 struct mlx5_ifc_add_vxlan_udp_dport_out_bits { 6342 u8 status[0x8]; 6343 u8 reserved_at_8[0x18]; 6344 6345 u8 syndrome[0x20]; 6346 6347 u8 reserved_at_40[0x40]; 6348 }; 6349 6350 struct mlx5_ifc_add_vxlan_udp_dport_in_bits { 6351 u8 opcode[0x10]; 6352 u8 reserved_at_10[0x10]; 6353 6354 u8 reserved_at_20[0x10]; 6355 u8 op_mod[0x10]; 6356 6357 u8 reserved_at_40[0x20]; 6358 6359 u8 reserved_at_60[0x10]; 6360 u8 vxlan_udp_port[0x10]; 6361 }; 6362 6363 struct mlx5_ifc_access_register_out_bits { 6364 u8 status[0x8]; 6365 u8 reserved_at_8[0x18]; 6366 6367 u8 syndrome[0x20]; 6368 6369 u8 reserved_at_40[0x40]; 6370 6371 u8 register_data[0][0x20]; 6372 }; 6373 6374 enum { 6375 MLX5_ACCESS_REGISTER_IN_OP_MOD_WRITE = 0x0, 6376 MLX5_ACCESS_REGISTER_IN_OP_MOD_READ = 0x1, 6377 }; 6378 6379 struct mlx5_ifc_access_register_in_bits { 6380 u8 opcode[0x10]; 6381 u8 reserved_at_10[0x10]; 6382 6383 u8 reserved_at_20[0x10]; 6384 u8 op_mod[0x10]; 6385 6386 u8 reserved_at_40[0x10]; 6387 u8 register_id[0x10]; 6388 6389 u8 argument[0x20]; 6390 6391 u8 register_data[0][0x20]; 6392 }; 6393 6394 struct mlx5_ifc_sltp_reg_bits { 6395 u8 status[0x4]; 6396 u8 version[0x4]; 6397 u8 local_port[0x8]; 6398 u8 pnat[0x2]; 6399 u8 reserved_at_12[0x2]; 6400 u8 lane[0x4]; 6401 u8 reserved_at_18[0x8]; 6402 6403 u8 reserved_at_20[0x20]; 6404 6405 u8 reserved_at_40[0x7]; 6406 u8 polarity[0x1]; 6407 u8 ob_tap0[0x8]; 6408 u8 ob_tap1[0x8]; 6409 u8 ob_tap2[0x8]; 6410 6411 u8 reserved_at_60[0xc]; 6412 u8 ob_preemp_mode[0x4]; 6413 u8 ob_reg[0x8]; 6414 u8 ob_bias[0x8]; 6415 6416 u8 reserved_at_80[0x20]; 6417 }; 6418 6419 struct mlx5_ifc_slrg_reg_bits { 6420 u8 status[0x4]; 6421 u8 version[0x4]; 6422 u8 local_port[0x8]; 6423 u8 pnat[0x2]; 6424 u8 reserved_at_12[0x2]; 6425 u8 lane[0x4]; 6426 u8 reserved_at_18[0x8]; 6427 6428 u8 time_to_link_up[0x10]; 6429 u8 reserved_at_30[0xc]; 6430 u8 grade_lane_speed[0x4]; 6431 6432 u8 grade_version[0x8]; 6433 u8 grade[0x18]; 6434 6435 u8 reserved_at_60[0x4]; 6436 u8 height_grade_type[0x4]; 6437 u8 height_grade[0x18]; 6438 6439 u8 height_dz[0x10]; 6440 u8 height_dv[0x10]; 6441 6442 u8 reserved_at_a0[0x10]; 6443 u8 height_sigma[0x10]; 6444 6445 u8 reserved_at_c0[0x20]; 6446 6447 u8 reserved_at_e0[0x4]; 6448 u8 phase_grade_type[0x4]; 6449 u8 phase_grade[0x18]; 6450 6451 u8 reserved_at_100[0x8]; 6452 u8 phase_eo_pos[0x8]; 6453 u8 reserved_at_110[0x8]; 6454 u8 phase_eo_neg[0x8]; 6455 6456 u8 ffe_set_tested[0x10]; 6457 u8 test_errors_per_lane[0x10]; 6458 }; 6459 6460 struct mlx5_ifc_pvlc_reg_bits { 6461 u8 reserved_at_0[0x8]; 6462 u8 local_port[0x8]; 6463 u8 reserved_at_10[0x10]; 6464 6465 u8 reserved_at_20[0x1c]; 6466 u8 vl_hw_cap[0x4]; 6467 6468 u8 reserved_at_40[0x1c]; 6469 u8 vl_admin[0x4]; 6470 6471 u8 reserved_at_60[0x1c]; 6472 u8 vl_operational[0x4]; 6473 }; 6474 6475 struct mlx5_ifc_pude_reg_bits { 6476 u8 swid[0x8]; 6477 u8 local_port[0x8]; 6478 u8 reserved_at_10[0x4]; 6479 u8 admin_status[0x4]; 6480 u8 reserved_at_18[0x4]; 6481 u8 oper_status[0x4]; 6482 6483 u8 reserved_at_20[0x60]; 6484 }; 6485 6486 struct mlx5_ifc_ptys_reg_bits { 6487 u8 reserved_at_0[0x8]; 6488 u8 local_port[0x8]; 6489 u8 reserved_at_10[0xd]; 6490 u8 proto_mask[0x3]; 6491 6492 u8 reserved_at_20[0x40]; 6493 6494 u8 eth_proto_capability[0x20]; 6495 6496 u8 ib_link_width_capability[0x10]; 6497 u8 ib_proto_capability[0x10]; 6498 6499 u8 reserved_at_a0[0x20]; 6500 6501 u8 eth_proto_admin[0x20]; 6502 6503 u8 ib_link_width_admin[0x10]; 6504 u8 ib_proto_admin[0x10]; 6505 6506 u8 reserved_at_100[0x20]; 6507 6508 u8 eth_proto_oper[0x20]; 6509 6510 u8 ib_link_width_oper[0x10]; 6511 u8 ib_proto_oper[0x10]; 6512 6513 u8 reserved_at_160[0x20]; 6514 6515 u8 eth_proto_lp_advertise[0x20]; 6516 6517 u8 reserved_at_1a0[0x60]; 6518 }; 6519 6520 struct mlx5_ifc_mlcr_reg_bits { 6521 u8 reserved_at_0[0x8]; 6522 u8 local_port[0x8]; 6523 u8 reserved_at_10[0x20]; 6524 6525 u8 beacon_duration[0x10]; 6526 u8 reserved_at_40[0x10]; 6527 6528 u8 beacon_remain[0x10]; 6529 }; 6530 6531 struct mlx5_ifc_ptas_reg_bits { 6532 u8 reserved_at_0[0x20]; 6533 6534 u8 algorithm_options[0x10]; 6535 u8 reserved_at_30[0x4]; 6536 u8 repetitions_mode[0x4]; 6537 u8 num_of_repetitions[0x8]; 6538 6539 u8 grade_version[0x8]; 6540 u8 height_grade_type[0x4]; 6541 u8 phase_grade_type[0x4]; 6542 u8 height_grade_weight[0x8]; 6543 u8 phase_grade_weight[0x8]; 6544 6545 u8 gisim_measure_bits[0x10]; 6546 u8 adaptive_tap_measure_bits[0x10]; 6547 6548 u8 ber_bath_high_error_threshold[0x10]; 6549 u8 ber_bath_mid_error_threshold[0x10]; 6550 6551 u8 ber_bath_low_error_threshold[0x10]; 6552 u8 one_ratio_high_threshold[0x10]; 6553 6554 u8 one_ratio_high_mid_threshold[0x10]; 6555 u8 one_ratio_low_mid_threshold[0x10]; 6556 6557 u8 one_ratio_low_threshold[0x10]; 6558 u8 ndeo_error_threshold[0x10]; 6559 6560 u8 mixer_offset_step_size[0x10]; 6561 u8 reserved_at_110[0x8]; 6562 u8 mix90_phase_for_voltage_bath[0x8]; 6563 6564 u8 mixer_offset_start[0x10]; 6565 u8 mixer_offset_end[0x10]; 6566 6567 u8 reserved_at_140[0x15]; 6568 u8 ber_test_time[0xb]; 6569 }; 6570 6571 struct mlx5_ifc_pspa_reg_bits { 6572 u8 swid[0x8]; 6573 u8 local_port[0x8]; 6574 u8 sub_port[0x8]; 6575 u8 reserved_at_18[0x8]; 6576 6577 u8 reserved_at_20[0x20]; 6578 }; 6579 6580 struct mlx5_ifc_pqdr_reg_bits { 6581 u8 reserved_at_0[0x8]; 6582 u8 local_port[0x8]; 6583 u8 reserved_at_10[0x5]; 6584 u8 prio[0x3]; 6585 u8 reserved_at_18[0x6]; 6586 u8 mode[0x2]; 6587 6588 u8 reserved_at_20[0x20]; 6589 6590 u8 reserved_at_40[0x10]; 6591 u8 min_threshold[0x10]; 6592 6593 u8 reserved_at_60[0x10]; 6594 u8 max_threshold[0x10]; 6595 6596 u8 reserved_at_80[0x10]; 6597 u8 mark_probability_denominator[0x10]; 6598 6599 u8 reserved_at_a0[0x60]; 6600 }; 6601 6602 struct mlx5_ifc_ppsc_reg_bits { 6603 u8 reserved_at_0[0x8]; 6604 u8 local_port[0x8]; 6605 u8 reserved_at_10[0x10]; 6606 6607 u8 reserved_at_20[0x60]; 6608 6609 u8 reserved_at_80[0x1c]; 6610 u8 wrps_admin[0x4]; 6611 6612 u8 reserved_at_a0[0x1c]; 6613 u8 wrps_status[0x4]; 6614 6615 u8 reserved_at_c0[0x8]; 6616 u8 up_threshold[0x8]; 6617 u8 reserved_at_d0[0x8]; 6618 u8 down_threshold[0x8]; 6619 6620 u8 reserved_at_e0[0x20]; 6621 6622 u8 reserved_at_100[0x1c]; 6623 u8 srps_admin[0x4]; 6624 6625 u8 reserved_at_120[0x1c]; 6626 u8 srps_status[0x4]; 6627 6628 u8 reserved_at_140[0x40]; 6629 }; 6630 6631 struct mlx5_ifc_pplr_reg_bits { 6632 u8 reserved_at_0[0x8]; 6633 u8 local_port[0x8]; 6634 u8 reserved_at_10[0x10]; 6635 6636 u8 reserved_at_20[0x8]; 6637 u8 lb_cap[0x8]; 6638 u8 reserved_at_30[0x8]; 6639 u8 lb_en[0x8]; 6640 }; 6641 6642 struct mlx5_ifc_pplm_reg_bits { 6643 u8 reserved_at_0[0x8]; 6644 u8 local_port[0x8]; 6645 u8 reserved_at_10[0x10]; 6646 6647 u8 reserved_at_20[0x20]; 6648 6649 u8 port_profile_mode[0x8]; 6650 u8 static_port_profile[0x8]; 6651 u8 active_port_profile[0x8]; 6652 u8 reserved_at_58[0x8]; 6653 6654 u8 retransmission_active[0x8]; 6655 u8 fec_mode_active[0x18]; 6656 6657 u8 reserved_at_80[0x20]; 6658 }; 6659 6660 struct mlx5_ifc_ppcnt_reg_bits { 6661 u8 swid[0x8]; 6662 u8 local_port[0x8]; 6663 u8 pnat[0x2]; 6664 u8 reserved_at_12[0x8]; 6665 u8 grp[0x6]; 6666 6667 u8 clr[0x1]; 6668 u8 reserved_at_21[0x1c]; 6669 u8 prio_tc[0x3]; 6670 6671 union mlx5_ifc_eth_cntrs_grp_data_layout_auto_bits counter_set; 6672 }; 6673 6674 struct mlx5_ifc_ppad_reg_bits { 6675 u8 reserved_at_0[0x3]; 6676 u8 single_mac[0x1]; 6677 u8 reserved_at_4[0x4]; 6678 u8 local_port[0x8]; 6679 u8 mac_47_32[0x10]; 6680 6681 u8 mac_31_0[0x20]; 6682 6683 u8 reserved_at_40[0x40]; 6684 }; 6685 6686 struct mlx5_ifc_pmtu_reg_bits { 6687 u8 reserved_at_0[0x8]; 6688 u8 local_port[0x8]; 6689 u8 reserved_at_10[0x10]; 6690 6691 u8 max_mtu[0x10]; 6692 u8 reserved_at_30[0x10]; 6693 6694 u8 admin_mtu[0x10]; 6695 u8 reserved_at_50[0x10]; 6696 6697 u8 oper_mtu[0x10]; 6698 u8 reserved_at_70[0x10]; 6699 }; 6700 6701 struct mlx5_ifc_pmpr_reg_bits { 6702 u8 reserved_at_0[0x8]; 6703 u8 module[0x8]; 6704 u8 reserved_at_10[0x10]; 6705 6706 u8 reserved_at_20[0x18]; 6707 u8 attenuation_5g[0x8]; 6708 6709 u8 reserved_at_40[0x18]; 6710 u8 attenuation_7g[0x8]; 6711 6712 u8 reserved_at_60[0x18]; 6713 u8 attenuation_12g[0x8]; 6714 }; 6715 6716 struct mlx5_ifc_pmpe_reg_bits { 6717 u8 reserved_at_0[0x8]; 6718 u8 module[0x8]; 6719 u8 reserved_at_10[0xc]; 6720 u8 module_status[0x4]; 6721 6722 u8 reserved_at_20[0x60]; 6723 }; 6724 6725 struct mlx5_ifc_pmpc_reg_bits { 6726 u8 module_state_updated[32][0x8]; 6727 }; 6728 6729 struct mlx5_ifc_pmlpn_reg_bits { 6730 u8 reserved_at_0[0x4]; 6731 u8 mlpn_status[0x4]; 6732 u8 local_port[0x8]; 6733 u8 reserved_at_10[0x10]; 6734 6735 u8 e[0x1]; 6736 u8 reserved_at_21[0x1f]; 6737 }; 6738 6739 struct mlx5_ifc_pmlp_reg_bits { 6740 u8 rxtx[0x1]; 6741 u8 reserved_at_1[0x7]; 6742 u8 local_port[0x8]; 6743 u8 reserved_at_10[0x8]; 6744 u8 width[0x8]; 6745 6746 u8 lane0_module_mapping[0x20]; 6747 6748 u8 lane1_module_mapping[0x20]; 6749 6750 u8 lane2_module_mapping[0x20]; 6751 6752 u8 lane3_module_mapping[0x20]; 6753 6754 u8 reserved_at_a0[0x160]; 6755 }; 6756 6757 struct mlx5_ifc_pmaos_reg_bits { 6758 u8 reserved_at_0[0x8]; 6759 u8 module[0x8]; 6760 u8 reserved_at_10[0x4]; 6761 u8 admin_status[0x4]; 6762 u8 reserved_at_18[0x4]; 6763 u8 oper_status[0x4]; 6764 6765 u8 ase[0x1]; 6766 u8 ee[0x1]; 6767 u8 reserved_at_22[0x1c]; 6768 u8 e[0x2]; 6769 6770 u8 reserved_at_40[0x40]; 6771 }; 6772 6773 struct mlx5_ifc_plpc_reg_bits { 6774 u8 reserved_at_0[0x4]; 6775 u8 profile_id[0xc]; 6776 u8 reserved_at_10[0x4]; 6777 u8 proto_mask[0x4]; 6778 u8 reserved_at_18[0x8]; 6779 6780 u8 reserved_at_20[0x10]; 6781 u8 lane_speed[0x10]; 6782 6783 u8 reserved_at_40[0x17]; 6784 u8 lpbf[0x1]; 6785 u8 fec_mode_policy[0x8]; 6786 6787 u8 retransmission_capability[0x8]; 6788 u8 fec_mode_capability[0x18]; 6789 6790 u8 retransmission_support_admin[0x8]; 6791 u8 fec_mode_support_admin[0x18]; 6792 6793 u8 retransmission_request_admin[0x8]; 6794 u8 fec_mode_request_admin[0x18]; 6795 6796 u8 reserved_at_c0[0x80]; 6797 }; 6798 6799 struct mlx5_ifc_plib_reg_bits { 6800 u8 reserved_at_0[0x8]; 6801 u8 local_port[0x8]; 6802 u8 reserved_at_10[0x8]; 6803 u8 ib_port[0x8]; 6804 6805 u8 reserved_at_20[0x60]; 6806 }; 6807 6808 struct mlx5_ifc_plbf_reg_bits { 6809 u8 reserved_at_0[0x8]; 6810 u8 local_port[0x8]; 6811 u8 reserved_at_10[0xd]; 6812 u8 lbf_mode[0x3]; 6813 6814 u8 reserved_at_20[0x20]; 6815 }; 6816 6817 struct mlx5_ifc_pipg_reg_bits { 6818 u8 reserved_at_0[0x8]; 6819 u8 local_port[0x8]; 6820 u8 reserved_at_10[0x10]; 6821 6822 u8 dic[0x1]; 6823 u8 reserved_at_21[0x19]; 6824 u8 ipg[0x4]; 6825 u8 reserved_at_3e[0x2]; 6826 }; 6827 6828 struct mlx5_ifc_pifr_reg_bits { 6829 u8 reserved_at_0[0x8]; 6830 u8 local_port[0x8]; 6831 u8 reserved_at_10[0x10]; 6832 6833 u8 reserved_at_20[0xe0]; 6834 6835 u8 port_filter[8][0x20]; 6836 6837 u8 port_filter_update_en[8][0x20]; 6838 }; 6839 6840 struct mlx5_ifc_pfcc_reg_bits { 6841 u8 reserved_at_0[0x8]; 6842 u8 local_port[0x8]; 6843 u8 reserved_at_10[0x10]; 6844 6845 u8 ppan[0x4]; 6846 u8 reserved_at_24[0x4]; 6847 u8 prio_mask_tx[0x8]; 6848 u8 reserved_at_30[0x8]; 6849 u8 prio_mask_rx[0x8]; 6850 6851 u8 pptx[0x1]; 6852 u8 aptx[0x1]; 6853 u8 reserved_at_42[0x6]; 6854 u8 pfctx[0x8]; 6855 u8 reserved_at_50[0x10]; 6856 6857 u8 pprx[0x1]; 6858 u8 aprx[0x1]; 6859 u8 reserved_at_62[0x6]; 6860 u8 pfcrx[0x8]; 6861 u8 reserved_at_70[0x10]; 6862 6863 u8 reserved_at_80[0x80]; 6864 }; 6865 6866 struct mlx5_ifc_pelc_reg_bits { 6867 u8 op[0x4]; 6868 u8 reserved_at_4[0x4]; 6869 u8 local_port[0x8]; 6870 u8 reserved_at_10[0x10]; 6871 6872 u8 op_admin[0x8]; 6873 u8 op_capability[0x8]; 6874 u8 op_request[0x8]; 6875 u8 op_active[0x8]; 6876 6877 u8 admin[0x40]; 6878 6879 u8 capability[0x40]; 6880 6881 u8 request[0x40]; 6882 6883 u8 active[0x40]; 6884 6885 u8 reserved_at_140[0x80]; 6886 }; 6887 6888 struct mlx5_ifc_peir_reg_bits { 6889 u8 reserved_at_0[0x8]; 6890 u8 local_port[0x8]; 6891 u8 reserved_at_10[0x10]; 6892 6893 u8 reserved_at_20[0xc]; 6894 u8 error_count[0x4]; 6895 u8 reserved_at_30[0x10]; 6896 6897 u8 reserved_at_40[0xc]; 6898 u8 lane[0x4]; 6899 u8 reserved_at_50[0x8]; 6900 u8 error_type[0x8]; 6901 }; 6902 6903 struct mlx5_ifc_pcap_reg_bits { 6904 u8 reserved_at_0[0x8]; 6905 u8 local_port[0x8]; 6906 u8 reserved_at_10[0x10]; 6907 6908 u8 port_capability_mask[4][0x20]; 6909 }; 6910 6911 struct mlx5_ifc_paos_reg_bits { 6912 u8 swid[0x8]; 6913 u8 local_port[0x8]; 6914 u8 reserved_at_10[0x4]; 6915 u8 admin_status[0x4]; 6916 u8 reserved_at_18[0x4]; 6917 u8 oper_status[0x4]; 6918 6919 u8 ase[0x1]; 6920 u8 ee[0x1]; 6921 u8 reserved_at_22[0x1c]; 6922 u8 e[0x2]; 6923 6924 u8 reserved_at_40[0x40]; 6925 }; 6926 6927 struct mlx5_ifc_pamp_reg_bits { 6928 u8 reserved_at_0[0x8]; 6929 u8 opamp_group[0x8]; 6930 u8 reserved_at_10[0xc]; 6931 u8 opamp_group_type[0x4]; 6932 6933 u8 start_index[0x10]; 6934 u8 reserved_at_30[0x4]; 6935 u8 num_of_indices[0xc]; 6936 6937 u8 index_data[18][0x10]; 6938 }; 6939 6940 struct mlx5_ifc_pcmr_reg_bits { 6941 u8 reserved_at_0[0x8]; 6942 u8 local_port[0x8]; 6943 u8 reserved_at_10[0x2e]; 6944 u8 fcs_cap[0x1]; 6945 u8 reserved_at_3f[0x1f]; 6946 u8 fcs_chk[0x1]; 6947 u8 reserved_at_5f[0x1]; 6948 }; 6949 6950 struct mlx5_ifc_lane_2_module_mapping_bits { 6951 u8 reserved_at_0[0x6]; 6952 u8 rx_lane[0x2]; 6953 u8 reserved_at_8[0x6]; 6954 u8 tx_lane[0x2]; 6955 u8 reserved_at_10[0x8]; 6956 u8 module[0x8]; 6957 }; 6958 6959 struct mlx5_ifc_bufferx_reg_bits { 6960 u8 reserved_at_0[0x6]; 6961 u8 lossy[0x1]; 6962 u8 epsb[0x1]; 6963 u8 reserved_at_8[0xc]; 6964 u8 size[0xc]; 6965 6966 u8 xoff_threshold[0x10]; 6967 u8 xon_threshold[0x10]; 6968 }; 6969 6970 struct mlx5_ifc_set_node_in_bits { 6971 u8 node_description[64][0x8]; 6972 }; 6973 6974 struct mlx5_ifc_register_power_settings_bits { 6975 u8 reserved_at_0[0x18]; 6976 u8 power_settings_level[0x8]; 6977 6978 u8 reserved_at_20[0x60]; 6979 }; 6980 6981 struct mlx5_ifc_register_host_endianness_bits { 6982 u8 he[0x1]; 6983 u8 reserved_at_1[0x1f]; 6984 6985 u8 reserved_at_20[0x60]; 6986 }; 6987 6988 struct mlx5_ifc_umr_pointer_desc_argument_bits { 6989 u8 reserved_at_0[0x20]; 6990 6991 u8 mkey[0x20]; 6992 6993 u8 addressh_63_32[0x20]; 6994 6995 u8 addressl_31_0[0x20]; 6996 }; 6997 6998 struct mlx5_ifc_ud_adrs_vector_bits { 6999 u8 dc_key[0x40]; 7000 7001 u8 ext[0x1]; 7002 u8 reserved_at_41[0x7]; 7003 u8 destination_qp_dct[0x18]; 7004 7005 u8 static_rate[0x4]; 7006 u8 sl_eth_prio[0x4]; 7007 u8 fl[0x1]; 7008 u8 mlid[0x7]; 7009 u8 rlid_udp_sport[0x10]; 7010 7011 u8 reserved_at_80[0x20]; 7012 7013 u8 rmac_47_16[0x20]; 7014 7015 u8 rmac_15_0[0x10]; 7016 u8 tclass[0x8]; 7017 u8 hop_limit[0x8]; 7018 7019 u8 reserved_at_e0[0x1]; 7020 u8 grh[0x1]; 7021 u8 reserved_at_e2[0x2]; 7022 u8 src_addr_index[0x8]; 7023 u8 flow_label[0x14]; 7024 7025 u8 rgid_rip[16][0x8]; 7026 }; 7027 7028 struct mlx5_ifc_pages_req_event_bits { 7029 u8 reserved_at_0[0x10]; 7030 u8 function_id[0x10]; 7031 7032 u8 num_pages[0x20]; 7033 7034 u8 reserved_at_40[0xa0]; 7035 }; 7036 7037 struct mlx5_ifc_eqe_bits { 7038 u8 reserved_at_0[0x8]; 7039 u8 event_type[0x8]; 7040 u8 reserved_at_10[0x8]; 7041 u8 event_sub_type[0x8]; 7042 7043 u8 reserved_at_20[0xe0]; 7044 7045 union mlx5_ifc_event_auto_bits event_data; 7046 7047 u8 reserved_at_1e0[0x10]; 7048 u8 signature[0x8]; 7049 u8 reserved_at_1f8[0x7]; 7050 u8 owner[0x1]; 7051 }; 7052 7053 enum { 7054 MLX5_CMD_QUEUE_ENTRY_TYPE_PCIE_CMD_IF_TRANSPORT = 0x7, 7055 }; 7056 7057 struct mlx5_ifc_cmd_queue_entry_bits { 7058 u8 type[0x8]; 7059 u8 reserved_at_8[0x18]; 7060 7061 u8 input_length[0x20]; 7062 7063 u8 input_mailbox_pointer_63_32[0x20]; 7064 7065 u8 input_mailbox_pointer_31_9[0x17]; 7066 u8 reserved_at_77[0x9]; 7067 7068 u8 command_input_inline_data[16][0x8]; 7069 7070 u8 command_output_inline_data[16][0x8]; 7071 7072 u8 output_mailbox_pointer_63_32[0x20]; 7073 7074 u8 output_mailbox_pointer_31_9[0x17]; 7075 u8 reserved_at_1b7[0x9]; 7076 7077 u8 output_length[0x20]; 7078 7079 u8 token[0x8]; 7080 u8 signature[0x8]; 7081 u8 reserved_at_1f0[0x8]; 7082 u8 status[0x7]; 7083 u8 ownership[0x1]; 7084 }; 7085 7086 struct mlx5_ifc_cmd_out_bits { 7087 u8 status[0x8]; 7088 u8 reserved_at_8[0x18]; 7089 7090 u8 syndrome[0x20]; 7091 7092 u8 command_output[0x20]; 7093 }; 7094 7095 struct mlx5_ifc_cmd_in_bits { 7096 u8 opcode[0x10]; 7097 u8 reserved_at_10[0x10]; 7098 7099 u8 reserved_at_20[0x10]; 7100 u8 op_mod[0x10]; 7101 7102 u8 command[0][0x20]; 7103 }; 7104 7105 struct mlx5_ifc_cmd_if_box_bits { 7106 u8 mailbox_data[512][0x8]; 7107 7108 u8 reserved_at_1000[0x180]; 7109 7110 u8 next_pointer_63_32[0x20]; 7111 7112 u8 next_pointer_31_10[0x16]; 7113 u8 reserved_at_11b6[0xa]; 7114 7115 u8 block_number[0x20]; 7116 7117 u8 reserved_at_11e0[0x8]; 7118 u8 token[0x8]; 7119 u8 ctrl_signature[0x8]; 7120 u8 signature[0x8]; 7121 }; 7122 7123 struct mlx5_ifc_mtt_bits { 7124 u8 ptag_63_32[0x20]; 7125 7126 u8 ptag_31_8[0x18]; 7127 u8 reserved_at_38[0x6]; 7128 u8 wr_en[0x1]; 7129 u8 rd_en[0x1]; 7130 }; 7131 7132 struct mlx5_ifc_query_wol_rol_out_bits { 7133 u8 status[0x8]; 7134 u8 reserved_at_8[0x18]; 7135 7136 u8 syndrome[0x20]; 7137 7138 u8 reserved_at_40[0x10]; 7139 u8 rol_mode[0x8]; 7140 u8 wol_mode[0x8]; 7141 7142 u8 reserved_at_60[0x20]; 7143 }; 7144 7145 struct mlx5_ifc_query_wol_rol_in_bits { 7146 u8 opcode[0x10]; 7147 u8 reserved_at_10[0x10]; 7148 7149 u8 reserved_at_20[0x10]; 7150 u8 op_mod[0x10]; 7151 7152 u8 reserved_at_40[0x40]; 7153 }; 7154 7155 struct mlx5_ifc_set_wol_rol_out_bits { 7156 u8 status[0x8]; 7157 u8 reserved_at_8[0x18]; 7158 7159 u8 syndrome[0x20]; 7160 7161 u8 reserved_at_40[0x40]; 7162 }; 7163 7164 struct mlx5_ifc_set_wol_rol_in_bits { 7165 u8 opcode[0x10]; 7166 u8 reserved_at_10[0x10]; 7167 7168 u8 reserved_at_20[0x10]; 7169 u8 op_mod[0x10]; 7170 7171 u8 rol_mode_valid[0x1]; 7172 u8 wol_mode_valid[0x1]; 7173 u8 reserved_at_42[0xe]; 7174 u8 rol_mode[0x8]; 7175 u8 wol_mode[0x8]; 7176 7177 u8 reserved_at_60[0x20]; 7178 }; 7179 7180 enum { 7181 MLX5_INITIAL_SEG_NIC_INTERFACE_FULL_DRIVER = 0x0, 7182 MLX5_INITIAL_SEG_NIC_INTERFACE_DISABLED = 0x1, 7183 MLX5_INITIAL_SEG_NIC_INTERFACE_NO_DRAM_NIC = 0x2, 7184 }; 7185 7186 enum { 7187 MLX5_INITIAL_SEG_NIC_INTERFACE_SUPPORTED_FULL_DRIVER = 0x0, 7188 MLX5_INITIAL_SEG_NIC_INTERFACE_SUPPORTED_DISABLED = 0x1, 7189 MLX5_INITIAL_SEG_NIC_INTERFACE_SUPPORTED_NO_DRAM_NIC = 0x2, 7190 }; 7191 7192 enum { 7193 MLX5_INITIAL_SEG_HEALTH_SYNDROME_FW_INTERNAL_ERR = 0x1, 7194 MLX5_INITIAL_SEG_HEALTH_SYNDROME_DEAD_IRISC = 0x7, 7195 MLX5_INITIAL_SEG_HEALTH_SYNDROME_HW_FATAL_ERR = 0x8, 7196 MLX5_INITIAL_SEG_HEALTH_SYNDROME_FW_CRC_ERR = 0x9, 7197 MLX5_INITIAL_SEG_HEALTH_SYNDROME_ICM_FETCH_PCI_ERR = 0xa, 7198 MLX5_INITIAL_SEG_HEALTH_SYNDROME_ICM_PAGE_ERR = 0xb, 7199 MLX5_INITIAL_SEG_HEALTH_SYNDROME_ASYNCHRONOUS_EQ_BUF_OVERRUN = 0xc, 7200 MLX5_INITIAL_SEG_HEALTH_SYNDROME_EQ_IN_ERR = 0xd, 7201 MLX5_INITIAL_SEG_HEALTH_SYNDROME_EQ_INV = 0xe, 7202 MLX5_INITIAL_SEG_HEALTH_SYNDROME_FFSER_ERR = 0xf, 7203 MLX5_INITIAL_SEG_HEALTH_SYNDROME_HIGH_TEMP_ERR = 0x10, 7204 }; 7205 7206 struct mlx5_ifc_initial_seg_bits { 7207 u8 fw_rev_minor[0x10]; 7208 u8 fw_rev_major[0x10]; 7209 7210 u8 cmd_interface_rev[0x10]; 7211 u8 fw_rev_subminor[0x10]; 7212 7213 u8 reserved_at_40[0x40]; 7214 7215 u8 cmdq_phy_addr_63_32[0x20]; 7216 7217 u8 cmdq_phy_addr_31_12[0x14]; 7218 u8 reserved_at_b4[0x2]; 7219 u8 nic_interface[0x2]; 7220 u8 log_cmdq_size[0x4]; 7221 u8 log_cmdq_stride[0x4]; 7222 7223 u8 command_doorbell_vector[0x20]; 7224 7225 u8 reserved_at_e0[0xf00]; 7226 7227 u8 initializing[0x1]; 7228 u8 reserved_at_fe1[0x4]; 7229 u8 nic_interface_supported[0x3]; 7230 u8 reserved_at_fe8[0x18]; 7231 7232 struct mlx5_ifc_health_buffer_bits health_buffer; 7233 7234 u8 no_dram_nic_offset[0x20]; 7235 7236 u8 reserved_at_1220[0x6e40]; 7237 7238 u8 reserved_at_8060[0x1f]; 7239 u8 clear_int[0x1]; 7240 7241 u8 health_syndrome[0x8]; 7242 u8 health_counter[0x18]; 7243 7244 u8 reserved_at_80a0[0x17fc0]; 7245 }; 7246 7247 union mlx5_ifc_ports_control_registers_document_bits { 7248 struct mlx5_ifc_bufferx_reg_bits bufferx_reg; 7249 struct mlx5_ifc_eth_2819_cntrs_grp_data_layout_bits eth_2819_cntrs_grp_data_layout; 7250 struct mlx5_ifc_eth_2863_cntrs_grp_data_layout_bits eth_2863_cntrs_grp_data_layout; 7251 struct mlx5_ifc_eth_3635_cntrs_grp_data_layout_bits eth_3635_cntrs_grp_data_layout; 7252 struct mlx5_ifc_eth_802_3_cntrs_grp_data_layout_bits eth_802_3_cntrs_grp_data_layout; 7253 struct mlx5_ifc_eth_extended_cntrs_grp_data_layout_bits eth_extended_cntrs_grp_data_layout; 7254 struct mlx5_ifc_eth_per_prio_grp_data_layout_bits eth_per_prio_grp_data_layout; 7255 struct mlx5_ifc_eth_per_traffic_grp_data_layout_bits eth_per_traffic_grp_data_layout; 7256 struct mlx5_ifc_lane_2_module_mapping_bits lane_2_module_mapping; 7257 struct mlx5_ifc_pamp_reg_bits pamp_reg; 7258 struct mlx5_ifc_paos_reg_bits paos_reg; 7259 struct mlx5_ifc_pcap_reg_bits pcap_reg; 7260 struct mlx5_ifc_peir_reg_bits peir_reg; 7261 struct mlx5_ifc_pelc_reg_bits pelc_reg; 7262 struct mlx5_ifc_pfcc_reg_bits pfcc_reg; 7263 struct mlx5_ifc_ib_port_cntrs_grp_data_layout_bits ib_port_cntrs_grp_data_layout; 7264 struct mlx5_ifc_phys_layer_cntrs_bits phys_layer_cntrs; 7265 struct mlx5_ifc_pifr_reg_bits pifr_reg; 7266 struct mlx5_ifc_pipg_reg_bits pipg_reg; 7267 struct mlx5_ifc_plbf_reg_bits plbf_reg; 7268 struct mlx5_ifc_plib_reg_bits plib_reg; 7269 struct mlx5_ifc_plpc_reg_bits plpc_reg; 7270 struct mlx5_ifc_pmaos_reg_bits pmaos_reg; 7271 struct mlx5_ifc_pmlp_reg_bits pmlp_reg; 7272 struct mlx5_ifc_pmlpn_reg_bits pmlpn_reg; 7273 struct mlx5_ifc_pmpc_reg_bits pmpc_reg; 7274 struct mlx5_ifc_pmpe_reg_bits pmpe_reg; 7275 struct mlx5_ifc_pmpr_reg_bits pmpr_reg; 7276 struct mlx5_ifc_pmtu_reg_bits pmtu_reg; 7277 struct mlx5_ifc_ppad_reg_bits ppad_reg; 7278 struct mlx5_ifc_ppcnt_reg_bits ppcnt_reg; 7279 struct mlx5_ifc_pplm_reg_bits pplm_reg; 7280 struct mlx5_ifc_pplr_reg_bits pplr_reg; 7281 struct mlx5_ifc_ppsc_reg_bits ppsc_reg; 7282 struct mlx5_ifc_pqdr_reg_bits pqdr_reg; 7283 struct mlx5_ifc_pspa_reg_bits pspa_reg; 7284 struct mlx5_ifc_ptas_reg_bits ptas_reg; 7285 struct mlx5_ifc_ptys_reg_bits ptys_reg; 7286 struct mlx5_ifc_mlcr_reg_bits mlcr_reg; 7287 struct mlx5_ifc_pude_reg_bits pude_reg; 7288 struct mlx5_ifc_pvlc_reg_bits pvlc_reg; 7289 struct mlx5_ifc_slrg_reg_bits slrg_reg; 7290 struct mlx5_ifc_sltp_reg_bits sltp_reg; 7291 u8 reserved_at_0[0x60e0]; 7292 }; 7293 7294 union mlx5_ifc_debug_enhancements_document_bits { 7295 struct mlx5_ifc_health_buffer_bits health_buffer; 7296 u8 reserved_at_0[0x200]; 7297 }; 7298 7299 union mlx5_ifc_uplink_pci_interface_document_bits { 7300 struct mlx5_ifc_initial_seg_bits initial_seg; 7301 u8 reserved_at_0[0x20060]; 7302 }; 7303 7304 struct mlx5_ifc_set_flow_table_root_out_bits { 7305 u8 status[0x8]; 7306 u8 reserved_at_8[0x18]; 7307 7308 u8 syndrome[0x20]; 7309 7310 u8 reserved_at_40[0x40]; 7311 }; 7312 7313 struct mlx5_ifc_set_flow_table_root_in_bits { 7314 u8 opcode[0x10]; 7315 u8 reserved_at_10[0x10]; 7316 7317 u8 reserved_at_20[0x10]; 7318 u8 op_mod[0x10]; 7319 7320 u8 other_vport[0x1]; 7321 u8 reserved_at_41[0xf]; 7322 u8 vport_number[0x10]; 7323 7324 u8 reserved_at_60[0x20]; 7325 7326 u8 table_type[0x8]; 7327 u8 reserved_at_88[0x18]; 7328 7329 u8 reserved_at_a0[0x8]; 7330 u8 table_id[0x18]; 7331 7332 u8 reserved_at_c0[0x140]; 7333 }; 7334 7335 enum { 7336 MLX5_MODIFY_FLOW_TABLE_MISS_TABLE_ID = 0x1, 7337 }; 7338 7339 struct mlx5_ifc_modify_flow_table_out_bits { 7340 u8 status[0x8]; 7341 u8 reserved_at_8[0x18]; 7342 7343 u8 syndrome[0x20]; 7344 7345 u8 reserved_at_40[0x40]; 7346 }; 7347 7348 struct mlx5_ifc_modify_flow_table_in_bits { 7349 u8 opcode[0x10]; 7350 u8 reserved_at_10[0x10]; 7351 7352 u8 reserved_at_20[0x10]; 7353 u8 op_mod[0x10]; 7354 7355 u8 other_vport[0x1]; 7356 u8 reserved_at_41[0xf]; 7357 u8 vport_number[0x10]; 7358 7359 u8 reserved_at_60[0x10]; 7360 u8 modify_field_select[0x10]; 7361 7362 u8 table_type[0x8]; 7363 u8 reserved_at_88[0x18]; 7364 7365 u8 reserved_at_a0[0x8]; 7366 u8 table_id[0x18]; 7367 7368 u8 reserved_at_c0[0x4]; 7369 u8 table_miss_mode[0x4]; 7370 u8 reserved_at_c8[0x18]; 7371 7372 u8 reserved_at_e0[0x8]; 7373 u8 table_miss_id[0x18]; 7374 7375 u8 reserved_at_100[0x100]; 7376 }; 7377 7378 struct mlx5_ifc_ets_tcn_config_reg_bits { 7379 u8 g[0x1]; 7380 u8 b[0x1]; 7381 u8 r[0x1]; 7382 u8 reserved_at_3[0x9]; 7383 u8 group[0x4]; 7384 u8 reserved_at_10[0x9]; 7385 u8 bw_allocation[0x7]; 7386 7387 u8 reserved_at_20[0xc]; 7388 u8 max_bw_units[0x4]; 7389 u8 reserved_at_30[0x8]; 7390 u8 max_bw_value[0x8]; 7391 }; 7392 7393 struct mlx5_ifc_ets_global_config_reg_bits { 7394 u8 reserved_at_0[0x2]; 7395 u8 r[0x1]; 7396 u8 reserved_at_3[0x1d]; 7397 7398 u8 reserved_at_20[0xc]; 7399 u8 max_bw_units[0x4]; 7400 u8 reserved_at_30[0x8]; 7401 u8 max_bw_value[0x8]; 7402 }; 7403 7404 struct mlx5_ifc_qetc_reg_bits { 7405 u8 reserved_at_0[0x8]; 7406 u8 port_number[0x8]; 7407 u8 reserved_at_10[0x30]; 7408 7409 struct mlx5_ifc_ets_tcn_config_reg_bits tc_configuration[0x8]; 7410 struct mlx5_ifc_ets_global_config_reg_bits global_configuration; 7411 }; 7412 7413 struct mlx5_ifc_qtct_reg_bits { 7414 u8 reserved_at_0[0x8]; 7415 u8 port_number[0x8]; 7416 u8 reserved_at_10[0xd]; 7417 u8 prio[0x3]; 7418 7419 u8 reserved_at_20[0x1d]; 7420 u8 tclass[0x3]; 7421 }; 7422 7423 struct mlx5_ifc_mcia_reg_bits { 7424 u8 l[0x1]; 7425 u8 reserved_at_1[0x7]; 7426 u8 module[0x8]; 7427 u8 reserved_at_10[0x8]; 7428 u8 status[0x8]; 7429 7430 u8 i2c_device_address[0x8]; 7431 u8 page_number[0x8]; 7432 u8 device_address[0x10]; 7433 7434 u8 reserved_at_40[0x10]; 7435 u8 size[0x10]; 7436 7437 u8 reserved_at_60[0x20]; 7438 7439 u8 dword_0[0x20]; 7440 u8 dword_1[0x20]; 7441 u8 dword_2[0x20]; 7442 u8 dword_3[0x20]; 7443 u8 dword_4[0x20]; 7444 u8 dword_5[0x20]; 7445 u8 dword_6[0x20]; 7446 u8 dword_7[0x20]; 7447 u8 dword_8[0x20]; 7448 u8 dword_9[0x20]; 7449 u8 dword_10[0x20]; 7450 u8 dword_11[0x20]; 7451 }; 7452 7453 #endif /* MLX5_IFC_H */ 7454