1 /* 2 * Copyright (c) 2013-2015, Mellanox Technologies, Ltd. All rights reserved. 3 * 4 * This software is available to you under a choice of one of two 5 * licenses. You may choose to be licensed under the terms of the GNU 6 * General Public License (GPL) Version 2, available from the file 7 * COPYING in the main directory of this source tree, or the 8 * OpenIB.org BSD license below: 9 * 10 * Redistribution and use in source and binary forms, with or 11 * without modification, are permitted provided that the following 12 * conditions are met: 13 * 14 * - Redistributions of source code must retain the above 15 * copyright notice, this list of conditions and the following 16 * disclaimer. 17 * 18 * - Redistributions in binary form must reproduce the above 19 * copyright notice, this list of conditions and the following 20 * disclaimer in the documentation and/or other materials 21 * provided with the distribution. 22 * 23 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, 24 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF 25 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND 26 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS 27 * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN 28 * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN 29 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE 30 * SOFTWARE. 31 */ 32 #ifndef MLX5_IFC_H 33 #define MLX5_IFC_H 34 35 enum { 36 MLX5_EVENT_TYPE_CODING_COMPLETION_EVENTS = 0x0, 37 MLX5_EVENT_TYPE_CODING_PATH_MIGRATED_SUCCEEDED = 0x1, 38 MLX5_EVENT_TYPE_CODING_COMMUNICATION_ESTABLISHED = 0x2, 39 MLX5_EVENT_TYPE_CODING_SEND_QUEUE_DRAINED = 0x3, 40 MLX5_EVENT_TYPE_CODING_LAST_WQE_REACHED = 0x13, 41 MLX5_EVENT_TYPE_CODING_SRQ_LIMIT = 0x14, 42 MLX5_EVENT_TYPE_CODING_DCT_ALL_CONNECTIONS_CLOSED = 0x1c, 43 MLX5_EVENT_TYPE_CODING_DCT_ACCESS_KEY_VIOLATION = 0x1d, 44 MLX5_EVENT_TYPE_CODING_CQ_ERROR = 0x4, 45 MLX5_EVENT_TYPE_CODING_LOCAL_WQ_CATASTROPHIC_ERROR = 0x5, 46 MLX5_EVENT_TYPE_CODING_PATH_MIGRATION_FAILED = 0x7, 47 MLX5_EVENT_TYPE_CODING_PAGE_FAULT_EVENT = 0xc, 48 MLX5_EVENT_TYPE_CODING_INVALID_REQUEST_LOCAL_WQ_ERROR = 0x10, 49 MLX5_EVENT_TYPE_CODING_LOCAL_ACCESS_VIOLATION_WQ_ERROR = 0x11, 50 MLX5_EVENT_TYPE_CODING_LOCAL_SRQ_CATASTROPHIC_ERROR = 0x12, 51 MLX5_EVENT_TYPE_CODING_INTERNAL_ERROR = 0x8, 52 MLX5_EVENT_TYPE_CODING_PORT_STATE_CHANGE = 0x9, 53 MLX5_EVENT_TYPE_CODING_GPIO_EVENT = 0x15, 54 MLX5_EVENT_TYPE_CODING_REMOTE_CONFIGURATION_PROTOCOL_EVENT = 0x19, 55 MLX5_EVENT_TYPE_CODING_DOORBELL_BLUEFLAME_CONGESTION_EVENT = 0x1a, 56 MLX5_EVENT_TYPE_CODING_STALL_VL_EVENT = 0x1b, 57 MLX5_EVENT_TYPE_CODING_DROPPED_PACKET_LOGGED_EVENT = 0x1f, 58 MLX5_EVENT_TYPE_CODING_COMMAND_INTERFACE_COMPLETION = 0xa, 59 MLX5_EVENT_TYPE_CODING_PAGE_REQUEST = 0xb 60 }; 61 62 enum { 63 MLX5_MODIFY_TIR_BITMASK_LRO = 0x0, 64 MLX5_MODIFY_TIR_BITMASK_INDIRECT_TABLE = 0x1, 65 MLX5_MODIFY_TIR_BITMASK_HASH = 0x2, 66 MLX5_MODIFY_TIR_BITMASK_TUNNELED_OFFLOAD_EN = 0x3 67 }; 68 69 enum { 70 MLX5_SET_HCA_CAP_OP_MOD_GENERAL_DEVICE = 0x0, 71 MLX5_SET_HCA_CAP_OP_MOD_ATOMIC = 0x3, 72 }; 73 74 enum { 75 MLX5_CMD_OP_QUERY_HCA_CAP = 0x100, 76 MLX5_CMD_OP_QUERY_ADAPTER = 0x101, 77 MLX5_CMD_OP_INIT_HCA = 0x102, 78 MLX5_CMD_OP_TEARDOWN_HCA = 0x103, 79 MLX5_CMD_OP_ENABLE_HCA = 0x104, 80 MLX5_CMD_OP_DISABLE_HCA = 0x105, 81 MLX5_CMD_OP_QUERY_PAGES = 0x107, 82 MLX5_CMD_OP_MANAGE_PAGES = 0x108, 83 MLX5_CMD_OP_SET_HCA_CAP = 0x109, 84 MLX5_CMD_OP_QUERY_ISSI = 0x10a, 85 MLX5_CMD_OP_SET_ISSI = 0x10b, 86 MLX5_CMD_OP_CREATE_MKEY = 0x200, 87 MLX5_CMD_OP_QUERY_MKEY = 0x201, 88 MLX5_CMD_OP_DESTROY_MKEY = 0x202, 89 MLX5_CMD_OP_QUERY_SPECIAL_CONTEXTS = 0x203, 90 MLX5_CMD_OP_PAGE_FAULT_RESUME = 0x204, 91 MLX5_CMD_OP_CREATE_EQ = 0x301, 92 MLX5_CMD_OP_DESTROY_EQ = 0x302, 93 MLX5_CMD_OP_QUERY_EQ = 0x303, 94 MLX5_CMD_OP_GEN_EQE = 0x304, 95 MLX5_CMD_OP_CREATE_CQ = 0x400, 96 MLX5_CMD_OP_DESTROY_CQ = 0x401, 97 MLX5_CMD_OP_QUERY_CQ = 0x402, 98 MLX5_CMD_OP_MODIFY_CQ = 0x403, 99 MLX5_CMD_OP_CREATE_QP = 0x500, 100 MLX5_CMD_OP_DESTROY_QP = 0x501, 101 MLX5_CMD_OP_RST2INIT_QP = 0x502, 102 MLX5_CMD_OP_INIT2RTR_QP = 0x503, 103 MLX5_CMD_OP_RTR2RTS_QP = 0x504, 104 MLX5_CMD_OP_RTS2RTS_QP = 0x505, 105 MLX5_CMD_OP_SQERR2RTS_QP = 0x506, 106 MLX5_CMD_OP_2ERR_QP = 0x507, 107 MLX5_CMD_OP_2RST_QP = 0x50a, 108 MLX5_CMD_OP_QUERY_QP = 0x50b, 109 MLX5_CMD_OP_SQD_RTS_QP = 0x50c, 110 MLX5_CMD_OP_INIT2INIT_QP = 0x50e, 111 MLX5_CMD_OP_CREATE_PSV = 0x600, 112 MLX5_CMD_OP_DESTROY_PSV = 0x601, 113 MLX5_CMD_OP_CREATE_SRQ = 0x700, 114 MLX5_CMD_OP_DESTROY_SRQ = 0x701, 115 MLX5_CMD_OP_QUERY_SRQ = 0x702, 116 MLX5_CMD_OP_ARM_RQ = 0x703, 117 MLX5_CMD_OP_CREATE_XRC_SRQ = 0x705, 118 MLX5_CMD_OP_DESTROY_XRC_SRQ = 0x706, 119 MLX5_CMD_OP_QUERY_XRC_SRQ = 0x707, 120 MLX5_CMD_OP_ARM_XRC_SRQ = 0x708, 121 MLX5_CMD_OP_CREATE_DCT = 0x710, 122 MLX5_CMD_OP_DESTROY_DCT = 0x711, 123 MLX5_CMD_OP_DRAIN_DCT = 0x712, 124 MLX5_CMD_OP_QUERY_DCT = 0x713, 125 MLX5_CMD_OP_ARM_DCT_FOR_KEY_VIOLATION = 0x714, 126 MLX5_CMD_OP_CREATE_XRQ = 0x717, 127 MLX5_CMD_OP_DESTROY_XRQ = 0x718, 128 MLX5_CMD_OP_QUERY_XRQ = 0x719, 129 MLX5_CMD_OP_ARM_XRQ = 0x71a, 130 MLX5_CMD_OP_QUERY_VPORT_STATE = 0x750, 131 MLX5_CMD_OP_MODIFY_VPORT_STATE = 0x751, 132 MLX5_CMD_OP_QUERY_ESW_VPORT_CONTEXT = 0x752, 133 MLX5_CMD_OP_MODIFY_ESW_VPORT_CONTEXT = 0x753, 134 MLX5_CMD_OP_QUERY_NIC_VPORT_CONTEXT = 0x754, 135 MLX5_CMD_OP_MODIFY_NIC_VPORT_CONTEXT = 0x755, 136 MLX5_CMD_OP_QUERY_ROCE_ADDRESS = 0x760, 137 MLX5_CMD_OP_SET_ROCE_ADDRESS = 0x761, 138 MLX5_CMD_OP_QUERY_HCA_VPORT_CONTEXT = 0x762, 139 MLX5_CMD_OP_MODIFY_HCA_VPORT_CONTEXT = 0x763, 140 MLX5_CMD_OP_QUERY_HCA_VPORT_GID = 0x764, 141 MLX5_CMD_OP_QUERY_HCA_VPORT_PKEY = 0x765, 142 MLX5_CMD_OP_QUERY_VPORT_COUNTER = 0x770, 143 MLX5_CMD_OP_ALLOC_Q_COUNTER = 0x771, 144 MLX5_CMD_OP_DEALLOC_Q_COUNTER = 0x772, 145 MLX5_CMD_OP_QUERY_Q_COUNTER = 0x773, 146 MLX5_CMD_OP_SET_RATE_LIMIT = 0x780, 147 MLX5_CMD_OP_QUERY_RATE_LIMIT = 0x781, 148 MLX5_CMD_OP_ALLOC_PD = 0x800, 149 MLX5_CMD_OP_DEALLOC_PD = 0x801, 150 MLX5_CMD_OP_ALLOC_UAR = 0x802, 151 MLX5_CMD_OP_DEALLOC_UAR = 0x803, 152 MLX5_CMD_OP_CONFIG_INT_MODERATION = 0x804, 153 MLX5_CMD_OP_ACCESS_REG = 0x805, 154 MLX5_CMD_OP_ATTACH_TO_MCG = 0x806, 155 MLX5_CMD_OP_DETTACH_FROM_MCG = 0x807, 156 MLX5_CMD_OP_GET_DROPPED_PACKET_LOG = 0x80a, 157 MLX5_CMD_OP_MAD_IFC = 0x50d, 158 MLX5_CMD_OP_QUERY_MAD_DEMUX = 0x80b, 159 MLX5_CMD_OP_SET_MAD_DEMUX = 0x80c, 160 MLX5_CMD_OP_NOP = 0x80d, 161 MLX5_CMD_OP_ALLOC_XRCD = 0x80e, 162 MLX5_CMD_OP_DEALLOC_XRCD = 0x80f, 163 MLX5_CMD_OP_ALLOC_TRANSPORT_DOMAIN = 0x816, 164 MLX5_CMD_OP_DEALLOC_TRANSPORT_DOMAIN = 0x817, 165 MLX5_CMD_OP_QUERY_CONG_STATUS = 0x822, 166 MLX5_CMD_OP_MODIFY_CONG_STATUS = 0x823, 167 MLX5_CMD_OP_QUERY_CONG_PARAMS = 0x824, 168 MLX5_CMD_OP_MODIFY_CONG_PARAMS = 0x825, 169 MLX5_CMD_OP_QUERY_CONG_STATISTICS = 0x826, 170 MLX5_CMD_OP_ADD_VXLAN_UDP_DPORT = 0x827, 171 MLX5_CMD_OP_DELETE_VXLAN_UDP_DPORT = 0x828, 172 MLX5_CMD_OP_SET_L2_TABLE_ENTRY = 0x829, 173 MLX5_CMD_OP_QUERY_L2_TABLE_ENTRY = 0x82a, 174 MLX5_CMD_OP_DELETE_L2_TABLE_ENTRY = 0x82b, 175 MLX5_CMD_OP_SET_WOL_ROL = 0x830, 176 MLX5_CMD_OP_QUERY_WOL_ROL = 0x831, 177 MLX5_CMD_OP_CREATE_TIR = 0x900, 178 MLX5_CMD_OP_MODIFY_TIR = 0x901, 179 MLX5_CMD_OP_DESTROY_TIR = 0x902, 180 MLX5_CMD_OP_QUERY_TIR = 0x903, 181 MLX5_CMD_OP_CREATE_SQ = 0x904, 182 MLX5_CMD_OP_MODIFY_SQ = 0x905, 183 MLX5_CMD_OP_DESTROY_SQ = 0x906, 184 MLX5_CMD_OP_QUERY_SQ = 0x907, 185 MLX5_CMD_OP_CREATE_RQ = 0x908, 186 MLX5_CMD_OP_MODIFY_RQ = 0x909, 187 MLX5_CMD_OP_DESTROY_RQ = 0x90a, 188 MLX5_CMD_OP_QUERY_RQ = 0x90b, 189 MLX5_CMD_OP_CREATE_RMP = 0x90c, 190 MLX5_CMD_OP_MODIFY_RMP = 0x90d, 191 MLX5_CMD_OP_DESTROY_RMP = 0x90e, 192 MLX5_CMD_OP_QUERY_RMP = 0x90f, 193 MLX5_CMD_OP_CREATE_TIS = 0x912, 194 MLX5_CMD_OP_MODIFY_TIS = 0x913, 195 MLX5_CMD_OP_DESTROY_TIS = 0x914, 196 MLX5_CMD_OP_QUERY_TIS = 0x915, 197 MLX5_CMD_OP_CREATE_RQT = 0x916, 198 MLX5_CMD_OP_MODIFY_RQT = 0x917, 199 MLX5_CMD_OP_DESTROY_RQT = 0x918, 200 MLX5_CMD_OP_QUERY_RQT = 0x919, 201 MLX5_CMD_OP_SET_FLOW_TABLE_ROOT = 0x92f, 202 MLX5_CMD_OP_CREATE_FLOW_TABLE = 0x930, 203 MLX5_CMD_OP_DESTROY_FLOW_TABLE = 0x931, 204 MLX5_CMD_OP_QUERY_FLOW_TABLE = 0x932, 205 MLX5_CMD_OP_CREATE_FLOW_GROUP = 0x933, 206 MLX5_CMD_OP_DESTROY_FLOW_GROUP = 0x934, 207 MLX5_CMD_OP_QUERY_FLOW_GROUP = 0x935, 208 MLX5_CMD_OP_SET_FLOW_TABLE_ENTRY = 0x936, 209 MLX5_CMD_OP_QUERY_FLOW_TABLE_ENTRY = 0x937, 210 MLX5_CMD_OP_DELETE_FLOW_TABLE_ENTRY = 0x938, 211 MLX5_CMD_OP_ALLOC_FLOW_COUNTER = 0x939, 212 MLX5_CMD_OP_DEALLOC_FLOW_COUNTER = 0x93a, 213 MLX5_CMD_OP_QUERY_FLOW_COUNTER = 0x93b, 214 MLX5_CMD_OP_MODIFY_FLOW_TABLE = 0x93c, 215 MLX5_CMD_OP_MAX 216 }; 217 218 struct mlx5_ifc_flow_table_fields_supported_bits { 219 u8 outer_dmac[0x1]; 220 u8 outer_smac[0x1]; 221 u8 outer_ether_type[0x1]; 222 u8 reserved_at_3[0x1]; 223 u8 outer_first_prio[0x1]; 224 u8 outer_first_cfi[0x1]; 225 u8 outer_first_vid[0x1]; 226 u8 reserved_at_7[0x1]; 227 u8 outer_second_prio[0x1]; 228 u8 outer_second_cfi[0x1]; 229 u8 outer_second_vid[0x1]; 230 u8 reserved_at_b[0x1]; 231 u8 outer_sip[0x1]; 232 u8 outer_dip[0x1]; 233 u8 outer_frag[0x1]; 234 u8 outer_ip_protocol[0x1]; 235 u8 outer_ip_ecn[0x1]; 236 u8 outer_ip_dscp[0x1]; 237 u8 outer_udp_sport[0x1]; 238 u8 outer_udp_dport[0x1]; 239 u8 outer_tcp_sport[0x1]; 240 u8 outer_tcp_dport[0x1]; 241 u8 outer_tcp_flags[0x1]; 242 u8 outer_gre_protocol[0x1]; 243 u8 outer_gre_key[0x1]; 244 u8 outer_vxlan_vni[0x1]; 245 u8 reserved_at_1a[0x5]; 246 u8 source_eswitch_port[0x1]; 247 248 u8 inner_dmac[0x1]; 249 u8 inner_smac[0x1]; 250 u8 inner_ether_type[0x1]; 251 u8 reserved_at_23[0x1]; 252 u8 inner_first_prio[0x1]; 253 u8 inner_first_cfi[0x1]; 254 u8 inner_first_vid[0x1]; 255 u8 reserved_at_27[0x1]; 256 u8 inner_second_prio[0x1]; 257 u8 inner_second_cfi[0x1]; 258 u8 inner_second_vid[0x1]; 259 u8 reserved_at_2b[0x1]; 260 u8 inner_sip[0x1]; 261 u8 inner_dip[0x1]; 262 u8 inner_frag[0x1]; 263 u8 inner_ip_protocol[0x1]; 264 u8 inner_ip_ecn[0x1]; 265 u8 inner_ip_dscp[0x1]; 266 u8 inner_udp_sport[0x1]; 267 u8 inner_udp_dport[0x1]; 268 u8 inner_tcp_sport[0x1]; 269 u8 inner_tcp_dport[0x1]; 270 u8 inner_tcp_flags[0x1]; 271 u8 reserved_at_37[0x9]; 272 273 u8 reserved_at_40[0x40]; 274 }; 275 276 struct mlx5_ifc_flow_table_prop_layout_bits { 277 u8 ft_support[0x1]; 278 u8 reserved_at_1[0x1]; 279 u8 flow_counter[0x1]; 280 u8 flow_modify_en[0x1]; 281 u8 modify_root[0x1]; 282 u8 identified_miss_table_mode[0x1]; 283 u8 flow_table_modify[0x1]; 284 u8 reserved_at_7[0x19]; 285 286 u8 reserved_at_20[0x2]; 287 u8 log_max_ft_size[0x6]; 288 u8 reserved_at_28[0x10]; 289 u8 max_ft_level[0x8]; 290 291 u8 reserved_at_40[0x20]; 292 293 u8 reserved_at_60[0x18]; 294 u8 log_max_ft_num[0x8]; 295 296 u8 reserved_at_80[0x18]; 297 u8 log_max_destination[0x8]; 298 299 u8 reserved_at_a0[0x18]; 300 u8 log_max_flow[0x8]; 301 302 u8 reserved_at_c0[0x40]; 303 304 struct mlx5_ifc_flow_table_fields_supported_bits ft_field_support; 305 306 struct mlx5_ifc_flow_table_fields_supported_bits ft_field_bitmask_support; 307 }; 308 309 struct mlx5_ifc_odp_per_transport_service_cap_bits { 310 u8 send[0x1]; 311 u8 receive[0x1]; 312 u8 write[0x1]; 313 u8 read[0x1]; 314 u8 reserved_at_4[0x1]; 315 u8 srq_receive[0x1]; 316 u8 reserved_at_6[0x1a]; 317 }; 318 319 struct mlx5_ifc_ipv4_layout_bits { 320 u8 reserved_at_0[0x60]; 321 322 u8 ipv4[0x20]; 323 }; 324 325 struct mlx5_ifc_ipv6_layout_bits { 326 u8 ipv6[16][0x8]; 327 }; 328 329 union mlx5_ifc_ipv6_layout_ipv4_layout_auto_bits { 330 struct mlx5_ifc_ipv6_layout_bits ipv6_layout; 331 struct mlx5_ifc_ipv4_layout_bits ipv4_layout; 332 u8 reserved_at_0[0x80]; 333 }; 334 335 struct mlx5_ifc_fte_match_set_lyr_2_4_bits { 336 u8 smac_47_16[0x20]; 337 338 u8 smac_15_0[0x10]; 339 u8 ethertype[0x10]; 340 341 u8 dmac_47_16[0x20]; 342 343 u8 dmac_15_0[0x10]; 344 u8 first_prio[0x3]; 345 u8 first_cfi[0x1]; 346 u8 first_vid[0xc]; 347 348 u8 ip_protocol[0x8]; 349 u8 ip_dscp[0x6]; 350 u8 ip_ecn[0x2]; 351 u8 vlan_tag[0x1]; 352 u8 reserved_at_91[0x1]; 353 u8 frag[0x1]; 354 u8 reserved_at_93[0x4]; 355 u8 tcp_flags[0x9]; 356 357 u8 tcp_sport[0x10]; 358 u8 tcp_dport[0x10]; 359 360 u8 reserved_at_c0[0x20]; 361 362 u8 udp_sport[0x10]; 363 u8 udp_dport[0x10]; 364 365 union mlx5_ifc_ipv6_layout_ipv4_layout_auto_bits src_ipv4_src_ipv6; 366 367 union mlx5_ifc_ipv6_layout_ipv4_layout_auto_bits dst_ipv4_dst_ipv6; 368 }; 369 370 struct mlx5_ifc_fte_match_set_misc_bits { 371 u8 reserved_at_0[0x8]; 372 u8 source_sqn[0x18]; 373 374 u8 reserved_at_20[0x10]; 375 u8 source_port[0x10]; 376 377 u8 outer_second_prio[0x3]; 378 u8 outer_second_cfi[0x1]; 379 u8 outer_second_vid[0xc]; 380 u8 inner_second_prio[0x3]; 381 u8 inner_second_cfi[0x1]; 382 u8 inner_second_vid[0xc]; 383 384 u8 outer_second_vlan_tag[0x1]; 385 u8 inner_second_vlan_tag[0x1]; 386 u8 reserved_at_62[0xe]; 387 u8 gre_protocol[0x10]; 388 389 u8 gre_key_h[0x18]; 390 u8 gre_key_l[0x8]; 391 392 u8 vxlan_vni[0x18]; 393 u8 reserved_at_b8[0x8]; 394 395 u8 reserved_at_c0[0x20]; 396 397 u8 reserved_at_e0[0xc]; 398 u8 outer_ipv6_flow_label[0x14]; 399 400 u8 reserved_at_100[0xc]; 401 u8 inner_ipv6_flow_label[0x14]; 402 403 u8 reserved_at_120[0xe0]; 404 }; 405 406 struct mlx5_ifc_cmd_pas_bits { 407 u8 pa_h[0x20]; 408 409 u8 pa_l[0x14]; 410 u8 reserved_at_34[0xc]; 411 }; 412 413 struct mlx5_ifc_uint64_bits { 414 u8 hi[0x20]; 415 416 u8 lo[0x20]; 417 }; 418 419 enum { 420 MLX5_ADS_STAT_RATE_NO_LIMIT = 0x0, 421 MLX5_ADS_STAT_RATE_2_5GBPS = 0x7, 422 MLX5_ADS_STAT_RATE_10GBPS = 0x8, 423 MLX5_ADS_STAT_RATE_30GBPS = 0x9, 424 MLX5_ADS_STAT_RATE_5GBPS = 0xa, 425 MLX5_ADS_STAT_RATE_20GBPS = 0xb, 426 MLX5_ADS_STAT_RATE_40GBPS = 0xc, 427 MLX5_ADS_STAT_RATE_60GBPS = 0xd, 428 MLX5_ADS_STAT_RATE_80GBPS = 0xe, 429 MLX5_ADS_STAT_RATE_120GBPS = 0xf, 430 }; 431 432 struct mlx5_ifc_ads_bits { 433 u8 fl[0x1]; 434 u8 free_ar[0x1]; 435 u8 reserved_at_2[0xe]; 436 u8 pkey_index[0x10]; 437 438 u8 reserved_at_20[0x8]; 439 u8 grh[0x1]; 440 u8 mlid[0x7]; 441 u8 rlid[0x10]; 442 443 u8 ack_timeout[0x5]; 444 u8 reserved_at_45[0x3]; 445 u8 src_addr_index[0x8]; 446 u8 reserved_at_50[0x4]; 447 u8 stat_rate[0x4]; 448 u8 hop_limit[0x8]; 449 450 u8 reserved_at_60[0x4]; 451 u8 tclass[0x8]; 452 u8 flow_label[0x14]; 453 454 u8 rgid_rip[16][0x8]; 455 456 u8 reserved_at_100[0x4]; 457 u8 f_dscp[0x1]; 458 u8 f_ecn[0x1]; 459 u8 reserved_at_106[0x1]; 460 u8 f_eth_prio[0x1]; 461 u8 ecn[0x2]; 462 u8 dscp[0x6]; 463 u8 udp_sport[0x10]; 464 465 u8 dei_cfi[0x1]; 466 u8 eth_prio[0x3]; 467 u8 sl[0x4]; 468 u8 port[0x8]; 469 u8 rmac_47_32[0x10]; 470 471 u8 rmac_31_0[0x20]; 472 }; 473 474 struct mlx5_ifc_flow_table_nic_cap_bits { 475 u8 nic_rx_multi_path_tirs[0x1]; 476 u8 reserved_at_1[0x1ff]; 477 478 struct mlx5_ifc_flow_table_prop_layout_bits flow_table_properties_nic_receive; 479 480 u8 reserved_at_400[0x200]; 481 482 struct mlx5_ifc_flow_table_prop_layout_bits flow_table_properties_nic_receive_sniffer; 483 484 struct mlx5_ifc_flow_table_prop_layout_bits flow_table_properties_nic_transmit; 485 486 u8 reserved_at_a00[0x200]; 487 488 struct mlx5_ifc_flow_table_prop_layout_bits flow_table_properties_nic_transmit_sniffer; 489 490 u8 reserved_at_e00[0x7200]; 491 }; 492 493 struct mlx5_ifc_flow_table_eswitch_cap_bits { 494 u8 reserved_at_0[0x200]; 495 496 struct mlx5_ifc_flow_table_prop_layout_bits flow_table_properties_nic_esw_fdb; 497 498 struct mlx5_ifc_flow_table_prop_layout_bits flow_table_properties_esw_acl_ingress; 499 500 struct mlx5_ifc_flow_table_prop_layout_bits flow_table_properties_esw_acl_egress; 501 502 u8 reserved_at_800[0x7800]; 503 }; 504 505 struct mlx5_ifc_e_switch_cap_bits { 506 u8 vport_svlan_strip[0x1]; 507 u8 vport_cvlan_strip[0x1]; 508 u8 vport_svlan_insert[0x1]; 509 u8 vport_cvlan_insert_if_not_exist[0x1]; 510 u8 vport_cvlan_insert_overwrite[0x1]; 511 u8 reserved_at_5[0x19]; 512 u8 nic_vport_node_guid_modify[0x1]; 513 u8 nic_vport_port_guid_modify[0x1]; 514 515 u8 reserved_at_20[0x7e0]; 516 }; 517 518 struct mlx5_ifc_qos_cap_bits { 519 u8 packet_pacing[0x1]; 520 u8 reserved_0[0x1f]; 521 u8 reserved_1[0x20]; 522 u8 packet_pacing_max_rate[0x20]; 523 u8 packet_pacing_min_rate[0x20]; 524 u8 reserved_2[0x10]; 525 u8 packet_pacing_rate_table_size[0x10]; 526 u8 reserved_3[0x760]; 527 }; 528 529 struct mlx5_ifc_per_protocol_networking_offload_caps_bits { 530 u8 csum_cap[0x1]; 531 u8 vlan_cap[0x1]; 532 u8 lro_cap[0x1]; 533 u8 lro_psh_flag[0x1]; 534 u8 lro_time_stamp[0x1]; 535 u8 reserved_at_5[0x3]; 536 u8 self_lb_en_modifiable[0x1]; 537 u8 reserved_at_9[0x2]; 538 u8 max_lso_cap[0x5]; 539 u8 reserved_at_10[0x2]; 540 u8 wqe_inline_mode[0x2]; 541 u8 rss_ind_tbl_cap[0x4]; 542 u8 reg_umr_sq[0x1]; 543 u8 scatter_fcs[0x1]; 544 u8 reserved_at_1a[0x1]; 545 u8 tunnel_lso_const_out_ip_id[0x1]; 546 u8 reserved_at_1c[0x2]; 547 u8 tunnel_statless_gre[0x1]; 548 u8 tunnel_stateless_vxlan[0x1]; 549 550 u8 reserved_at_20[0x20]; 551 552 u8 reserved_at_40[0x10]; 553 u8 lro_min_mss_size[0x10]; 554 555 u8 reserved_at_60[0x120]; 556 557 u8 lro_timer_supported_periods[4][0x20]; 558 559 u8 reserved_at_200[0x600]; 560 }; 561 562 struct mlx5_ifc_roce_cap_bits { 563 u8 roce_apm[0x1]; 564 u8 reserved_at_1[0x1f]; 565 566 u8 reserved_at_20[0x60]; 567 568 u8 reserved_at_80[0xc]; 569 u8 l3_type[0x4]; 570 u8 reserved_at_90[0x8]; 571 u8 roce_version[0x8]; 572 573 u8 reserved_at_a0[0x10]; 574 u8 r_roce_dest_udp_port[0x10]; 575 576 u8 r_roce_max_src_udp_port[0x10]; 577 u8 r_roce_min_src_udp_port[0x10]; 578 579 u8 reserved_at_e0[0x10]; 580 u8 roce_address_table_size[0x10]; 581 582 u8 reserved_at_100[0x700]; 583 }; 584 585 enum { 586 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_QP_1_BYTE = 0x0, 587 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_QP_2_BYTES = 0x2, 588 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_QP_4_BYTES = 0x4, 589 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_QP_8_BYTES = 0x8, 590 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_QP_16_BYTES = 0x10, 591 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_QP_32_BYTES = 0x20, 592 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_QP_64_BYTES = 0x40, 593 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_QP_128_BYTES = 0x80, 594 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_QP_256_BYTES = 0x100, 595 }; 596 597 enum { 598 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_DC_1_BYTE = 0x1, 599 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_DC_2_BYTES = 0x2, 600 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_DC_4_BYTES = 0x4, 601 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_DC_8_BYTES = 0x8, 602 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_DC_16_BYTES = 0x10, 603 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_DC_32_BYTES = 0x20, 604 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_DC_64_BYTES = 0x40, 605 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_DC_128_BYTES = 0x80, 606 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_DC_256_BYTES = 0x100, 607 }; 608 609 struct mlx5_ifc_atomic_caps_bits { 610 u8 reserved_at_0[0x40]; 611 612 u8 atomic_req_8B_endianess_mode[0x2]; 613 u8 reserved_at_42[0x4]; 614 u8 supported_atomic_req_8B_endianess_mode_1[0x1]; 615 616 u8 reserved_at_47[0x19]; 617 618 u8 reserved_at_60[0x20]; 619 620 u8 reserved_at_80[0x10]; 621 u8 atomic_operations[0x10]; 622 623 u8 reserved_at_a0[0x10]; 624 u8 atomic_size_qp[0x10]; 625 626 u8 reserved_at_c0[0x10]; 627 u8 atomic_size_dc[0x10]; 628 629 u8 reserved_at_e0[0x720]; 630 }; 631 632 struct mlx5_ifc_odp_cap_bits { 633 u8 reserved_at_0[0x40]; 634 635 u8 sig[0x1]; 636 u8 reserved_at_41[0x1f]; 637 638 u8 reserved_at_60[0x20]; 639 640 struct mlx5_ifc_odp_per_transport_service_cap_bits rc_odp_caps; 641 642 struct mlx5_ifc_odp_per_transport_service_cap_bits uc_odp_caps; 643 644 struct mlx5_ifc_odp_per_transport_service_cap_bits ud_odp_caps; 645 646 u8 reserved_at_e0[0x720]; 647 }; 648 649 struct mlx5_ifc_calc_op { 650 u8 reserved_at_0[0x10]; 651 u8 reserved_at_10[0x9]; 652 u8 op_swap_endianness[0x1]; 653 u8 op_min[0x1]; 654 u8 op_xor[0x1]; 655 u8 op_or[0x1]; 656 u8 op_and[0x1]; 657 u8 op_max[0x1]; 658 u8 op_add[0x1]; 659 }; 660 661 struct mlx5_ifc_vector_calc_cap_bits { 662 u8 calc_matrix[0x1]; 663 u8 reserved_at_1[0x1f]; 664 u8 reserved_at_20[0x8]; 665 u8 max_vec_count[0x8]; 666 u8 reserved_at_30[0xd]; 667 u8 max_chunk_size[0x3]; 668 struct mlx5_ifc_calc_op calc0; 669 struct mlx5_ifc_calc_op calc1; 670 struct mlx5_ifc_calc_op calc2; 671 struct mlx5_ifc_calc_op calc3; 672 673 u8 reserved_at_e0[0x720]; 674 }; 675 676 enum { 677 MLX5_WQ_TYPE_LINKED_LIST = 0x0, 678 MLX5_WQ_TYPE_CYCLIC = 0x1, 679 MLX5_WQ_TYPE_LINKED_LIST_STRIDING_RQ = 0x2, 680 }; 681 682 enum { 683 MLX5_WQ_END_PAD_MODE_NONE = 0x0, 684 MLX5_WQ_END_PAD_MODE_ALIGN = 0x1, 685 }; 686 687 enum { 688 MLX5_CMD_HCA_CAP_GID_TABLE_SIZE_8_GID_ENTRIES = 0x0, 689 MLX5_CMD_HCA_CAP_GID_TABLE_SIZE_16_GID_ENTRIES = 0x1, 690 MLX5_CMD_HCA_CAP_GID_TABLE_SIZE_32_GID_ENTRIES = 0x2, 691 MLX5_CMD_HCA_CAP_GID_TABLE_SIZE_64_GID_ENTRIES = 0x3, 692 MLX5_CMD_HCA_CAP_GID_TABLE_SIZE_128_GID_ENTRIES = 0x4, 693 }; 694 695 enum { 696 MLX5_CMD_HCA_CAP_PKEY_TABLE_SIZE_128_ENTRIES = 0x0, 697 MLX5_CMD_HCA_CAP_PKEY_TABLE_SIZE_256_ENTRIES = 0x1, 698 MLX5_CMD_HCA_CAP_PKEY_TABLE_SIZE_512_ENTRIES = 0x2, 699 MLX5_CMD_HCA_CAP_PKEY_TABLE_SIZE_1K_ENTRIES = 0x3, 700 MLX5_CMD_HCA_CAP_PKEY_TABLE_SIZE_2K_ENTRIES = 0x4, 701 MLX5_CMD_HCA_CAP_PKEY_TABLE_SIZE_4K_ENTRIES = 0x5, 702 }; 703 704 enum { 705 MLX5_CMD_HCA_CAP_PORT_TYPE_IB = 0x0, 706 MLX5_CMD_HCA_CAP_PORT_TYPE_ETHERNET = 0x1, 707 }; 708 709 enum { 710 MLX5_CMD_HCA_CAP_CMDIF_CHECKSUM_DISABLED = 0x0, 711 MLX5_CMD_HCA_CAP_CMDIF_CHECKSUM_INITIAL_STATE = 0x1, 712 MLX5_CMD_HCA_CAP_CMDIF_CHECKSUM_ENABLED = 0x3, 713 }; 714 715 enum { 716 MLX5_CAP_PORT_TYPE_IB = 0x0, 717 MLX5_CAP_PORT_TYPE_ETH = 0x1, 718 }; 719 720 struct mlx5_ifc_cmd_hca_cap_bits { 721 u8 reserved_at_0[0x80]; 722 723 u8 log_max_srq_sz[0x8]; 724 u8 log_max_qp_sz[0x8]; 725 u8 reserved_at_90[0xb]; 726 u8 log_max_qp[0x5]; 727 728 u8 reserved_at_a0[0xb]; 729 u8 log_max_srq[0x5]; 730 u8 reserved_at_b0[0x10]; 731 732 u8 reserved_at_c0[0x8]; 733 u8 log_max_cq_sz[0x8]; 734 u8 reserved_at_d0[0xb]; 735 u8 log_max_cq[0x5]; 736 737 u8 log_max_eq_sz[0x8]; 738 u8 reserved_at_e8[0x2]; 739 u8 log_max_mkey[0x6]; 740 u8 reserved_at_f0[0xc]; 741 u8 log_max_eq[0x4]; 742 743 u8 max_indirection[0x8]; 744 u8 reserved_at_108[0x1]; 745 u8 log_max_mrw_sz[0x7]; 746 u8 reserved_at_110[0x2]; 747 u8 log_max_bsf_list_size[0x6]; 748 u8 reserved_at_118[0x2]; 749 u8 log_max_klm_list_size[0x6]; 750 751 u8 reserved_at_120[0xa]; 752 u8 log_max_ra_req_dc[0x6]; 753 u8 reserved_at_130[0xa]; 754 u8 log_max_ra_res_dc[0x6]; 755 756 u8 reserved_at_140[0xa]; 757 u8 log_max_ra_req_qp[0x6]; 758 u8 reserved_at_150[0xa]; 759 u8 log_max_ra_res_qp[0x6]; 760 761 u8 pad_cap[0x1]; 762 u8 cc_query_allowed[0x1]; 763 u8 cc_modify_allowed[0x1]; 764 u8 reserved_at_163[0xd]; 765 u8 gid_table_size[0x10]; 766 767 u8 out_of_seq_cnt[0x1]; 768 u8 vport_counters[0x1]; 769 u8 retransmission_q_counters[0x1]; 770 u8 reserved_at_183[0x3]; 771 u8 max_qp_cnt[0xa]; 772 u8 pkey_table_size[0x10]; 773 774 u8 vport_group_manager[0x1]; 775 u8 vhca_group_manager[0x1]; 776 u8 ib_virt[0x1]; 777 u8 eth_virt[0x1]; 778 u8 reserved_at_1a4[0x1]; 779 u8 ets[0x1]; 780 u8 nic_flow_table[0x1]; 781 u8 eswitch_flow_table[0x1]; 782 u8 early_vf_enable[0x1]; 783 u8 reserved_at_1a9[0x2]; 784 u8 local_ca_ack_delay[0x5]; 785 u8 reserved_at_1af[0x2]; 786 u8 ports_check[0x1]; 787 u8 reserved_at_1b2[0x1]; 788 u8 disable_link_up[0x1]; 789 u8 beacon_led[0x1]; 790 u8 port_type[0x2]; 791 u8 num_ports[0x8]; 792 793 u8 reserved_at_1c0[0x3]; 794 u8 log_max_msg[0x5]; 795 u8 reserved_at_1c8[0x4]; 796 u8 max_tc[0x4]; 797 u8 reserved_at_1d0[0x1]; 798 u8 dcbx[0x1]; 799 u8 reserved_at_1d2[0x4]; 800 u8 rol_s[0x1]; 801 u8 rol_g[0x1]; 802 u8 reserved_at_1d8[0x1]; 803 u8 wol_s[0x1]; 804 u8 wol_g[0x1]; 805 u8 wol_a[0x1]; 806 u8 wol_b[0x1]; 807 u8 wol_m[0x1]; 808 u8 wol_u[0x1]; 809 u8 wol_p[0x1]; 810 811 u8 stat_rate_support[0x10]; 812 u8 reserved_at_1f0[0xc]; 813 u8 cqe_version[0x4]; 814 815 u8 compact_address_vector[0x1]; 816 u8 striding_rq[0x1]; 817 u8 reserved_at_201[0x2]; 818 u8 ipoib_basic_offloads[0x1]; 819 u8 reserved_at_205[0xa]; 820 u8 drain_sigerr[0x1]; 821 u8 cmdif_checksum[0x2]; 822 u8 sigerr_cqe[0x1]; 823 u8 reserved_at_213[0x1]; 824 u8 wq_signature[0x1]; 825 u8 sctr_data_cqe[0x1]; 826 u8 reserved_at_216[0x1]; 827 u8 sho[0x1]; 828 u8 tph[0x1]; 829 u8 rf[0x1]; 830 u8 dct[0x1]; 831 u8 qos[0x1]; 832 u8 eth_net_offloads[0x1]; 833 u8 roce[0x1]; 834 u8 atomic[0x1]; 835 u8 reserved_at_21f[0x1]; 836 837 u8 cq_oi[0x1]; 838 u8 cq_resize[0x1]; 839 u8 cq_moderation[0x1]; 840 u8 reserved_at_223[0x3]; 841 u8 cq_eq_remap[0x1]; 842 u8 pg[0x1]; 843 u8 block_lb_mc[0x1]; 844 u8 reserved_at_229[0x1]; 845 u8 scqe_break_moderation[0x1]; 846 u8 cq_period_start_from_cqe[0x1]; 847 u8 cd[0x1]; 848 u8 reserved_at_22d[0x1]; 849 u8 apm[0x1]; 850 u8 vector_calc[0x1]; 851 u8 umr_ptr_rlky[0x1]; 852 u8 imaicl[0x1]; 853 u8 reserved_at_232[0x4]; 854 u8 qkv[0x1]; 855 u8 pkv[0x1]; 856 u8 set_deth_sqpn[0x1]; 857 u8 reserved_at_239[0x3]; 858 u8 xrc[0x1]; 859 u8 ud[0x1]; 860 u8 uc[0x1]; 861 u8 rc[0x1]; 862 863 u8 reserved_at_240[0xa]; 864 u8 uar_sz[0x6]; 865 u8 reserved_at_250[0x8]; 866 u8 log_pg_sz[0x8]; 867 868 u8 bf[0x1]; 869 u8 reserved_at_261[0x1]; 870 u8 pad_tx_eth_packet[0x1]; 871 u8 reserved_at_263[0x8]; 872 u8 log_bf_reg_size[0x5]; 873 u8 reserved_at_270[0x10]; 874 875 u8 reserved_at_280[0x10]; 876 u8 max_wqe_sz_sq[0x10]; 877 878 u8 reserved_at_2a0[0x10]; 879 u8 max_wqe_sz_rq[0x10]; 880 881 u8 reserved_at_2c0[0x10]; 882 u8 max_wqe_sz_sq_dc[0x10]; 883 884 u8 reserved_at_2e0[0x7]; 885 u8 max_qp_mcg[0x19]; 886 887 u8 reserved_at_300[0x18]; 888 u8 log_max_mcg[0x8]; 889 890 u8 reserved_at_320[0x3]; 891 u8 log_max_transport_domain[0x5]; 892 u8 reserved_at_328[0x3]; 893 u8 log_max_pd[0x5]; 894 u8 reserved_at_330[0xb]; 895 u8 log_max_xrcd[0x5]; 896 897 u8 reserved_at_340[0x8]; 898 u8 log_max_flow_counter_bulk[0x8]; 899 u8 max_flow_counter[0x10]; 900 901 902 u8 reserved_at_360[0x3]; 903 u8 log_max_rq[0x5]; 904 u8 reserved_at_368[0x3]; 905 u8 log_max_sq[0x5]; 906 u8 reserved_at_370[0x3]; 907 u8 log_max_tir[0x5]; 908 u8 reserved_at_378[0x3]; 909 u8 log_max_tis[0x5]; 910 911 u8 basic_cyclic_rcv_wqe[0x1]; 912 u8 reserved_at_381[0x2]; 913 u8 log_max_rmp[0x5]; 914 u8 reserved_at_388[0x3]; 915 u8 log_max_rqt[0x5]; 916 u8 reserved_at_390[0x3]; 917 u8 log_max_rqt_size[0x5]; 918 u8 reserved_at_398[0x3]; 919 u8 log_max_tis_per_sq[0x5]; 920 921 u8 reserved_at_3a0[0x3]; 922 u8 log_max_stride_sz_rq[0x5]; 923 u8 reserved_at_3a8[0x3]; 924 u8 log_min_stride_sz_rq[0x5]; 925 u8 reserved_at_3b0[0x3]; 926 u8 log_max_stride_sz_sq[0x5]; 927 u8 reserved_at_3b8[0x3]; 928 u8 log_min_stride_sz_sq[0x5]; 929 930 u8 reserved_at_3c0[0x1b]; 931 u8 log_max_wq_sz[0x5]; 932 933 u8 nic_vport_change_event[0x1]; 934 u8 reserved_at_3e1[0xa]; 935 u8 log_max_vlan_list[0x5]; 936 u8 reserved_at_3f0[0x3]; 937 u8 log_max_current_mc_list[0x5]; 938 u8 reserved_at_3f8[0x3]; 939 u8 log_max_current_uc_list[0x5]; 940 941 u8 reserved_at_400[0x80]; 942 943 u8 reserved_at_480[0x3]; 944 u8 log_max_l2_table[0x5]; 945 u8 reserved_at_488[0x8]; 946 u8 log_uar_page_sz[0x10]; 947 948 u8 reserved_at_4a0[0x20]; 949 u8 device_frequency_mhz[0x20]; 950 u8 device_frequency_khz[0x20]; 951 952 u8 reserved_at_500[0x80]; 953 954 u8 reserved_at_580[0x3f]; 955 u8 cqe_compression[0x1]; 956 957 u8 cqe_compression_timeout[0x10]; 958 u8 cqe_compression_max_num[0x10]; 959 960 u8 reserved_at_5e0[0x10]; 961 u8 tag_matching[0x1]; 962 u8 rndv_offload_rc[0x1]; 963 u8 rndv_offload_dc[0x1]; 964 u8 log_tag_matching_list_sz[0x5]; 965 u8 reserved_at_5e8[0x3]; 966 u8 log_max_xrq[0x5]; 967 968 u8 reserved_at_5f0[0x200]; 969 }; 970 971 enum mlx5_flow_destination_type { 972 MLX5_FLOW_DESTINATION_TYPE_VPORT = 0x0, 973 MLX5_FLOW_DESTINATION_TYPE_FLOW_TABLE = 0x1, 974 MLX5_FLOW_DESTINATION_TYPE_TIR = 0x2, 975 976 MLX5_FLOW_DESTINATION_TYPE_COUNTER = 0x100, 977 }; 978 979 struct mlx5_ifc_dest_format_struct_bits { 980 u8 destination_type[0x8]; 981 u8 destination_id[0x18]; 982 983 u8 reserved_at_20[0x20]; 984 }; 985 986 struct mlx5_ifc_flow_counter_list_bits { 987 u8 clear[0x1]; 988 u8 num_of_counters[0xf]; 989 u8 flow_counter_id[0x10]; 990 991 u8 reserved_at_20[0x20]; 992 }; 993 994 union mlx5_ifc_dest_format_struct_flow_counter_list_auto_bits { 995 struct mlx5_ifc_dest_format_struct_bits dest_format_struct; 996 struct mlx5_ifc_flow_counter_list_bits flow_counter_list; 997 u8 reserved_at_0[0x40]; 998 }; 999 1000 struct mlx5_ifc_fte_match_param_bits { 1001 struct mlx5_ifc_fte_match_set_lyr_2_4_bits outer_headers; 1002 1003 struct mlx5_ifc_fte_match_set_misc_bits misc_parameters; 1004 1005 struct mlx5_ifc_fte_match_set_lyr_2_4_bits inner_headers; 1006 1007 u8 reserved_at_600[0xa00]; 1008 }; 1009 1010 enum { 1011 MLX5_RX_HASH_FIELD_SELECT_SELECTED_FIELDS_SRC_IP = 0x0, 1012 MLX5_RX_HASH_FIELD_SELECT_SELECTED_FIELDS_DST_IP = 0x1, 1013 MLX5_RX_HASH_FIELD_SELECT_SELECTED_FIELDS_L4_SPORT = 0x2, 1014 MLX5_RX_HASH_FIELD_SELECT_SELECTED_FIELDS_L4_DPORT = 0x3, 1015 MLX5_RX_HASH_FIELD_SELECT_SELECTED_FIELDS_IPSEC_SPI = 0x4, 1016 }; 1017 1018 struct mlx5_ifc_rx_hash_field_select_bits { 1019 u8 l3_prot_type[0x1]; 1020 u8 l4_prot_type[0x1]; 1021 u8 selected_fields[0x1e]; 1022 }; 1023 1024 enum { 1025 MLX5_WQ_WQ_TYPE_WQ_LINKED_LIST = 0x0, 1026 MLX5_WQ_WQ_TYPE_WQ_CYCLIC = 0x1, 1027 }; 1028 1029 enum { 1030 MLX5_WQ_END_PADDING_MODE_END_PAD_NONE = 0x0, 1031 MLX5_WQ_END_PADDING_MODE_END_PAD_ALIGN = 0x1, 1032 }; 1033 1034 struct mlx5_ifc_wq_bits { 1035 u8 wq_type[0x4]; 1036 u8 wq_signature[0x1]; 1037 u8 end_padding_mode[0x2]; 1038 u8 cd_slave[0x1]; 1039 u8 reserved_at_8[0x18]; 1040 1041 u8 hds_skip_first_sge[0x1]; 1042 u8 log2_hds_buf_size[0x3]; 1043 u8 reserved_at_24[0x7]; 1044 u8 page_offset[0x5]; 1045 u8 lwm[0x10]; 1046 1047 u8 reserved_at_40[0x8]; 1048 u8 pd[0x18]; 1049 1050 u8 reserved_at_60[0x8]; 1051 u8 uar_page[0x18]; 1052 1053 u8 dbr_addr[0x40]; 1054 1055 u8 hw_counter[0x20]; 1056 1057 u8 sw_counter[0x20]; 1058 1059 u8 reserved_at_100[0xc]; 1060 u8 log_wq_stride[0x4]; 1061 u8 reserved_at_110[0x3]; 1062 u8 log_wq_pg_sz[0x5]; 1063 u8 reserved_at_118[0x3]; 1064 u8 log_wq_sz[0x5]; 1065 1066 u8 reserved_at_120[0x15]; 1067 u8 log_wqe_num_of_strides[0x3]; 1068 u8 two_byte_shift_en[0x1]; 1069 u8 reserved_at_139[0x4]; 1070 u8 log_wqe_stride_size[0x3]; 1071 1072 u8 reserved_at_140[0x4c0]; 1073 1074 struct mlx5_ifc_cmd_pas_bits pas[0]; 1075 }; 1076 1077 struct mlx5_ifc_rq_num_bits { 1078 u8 reserved_at_0[0x8]; 1079 u8 rq_num[0x18]; 1080 }; 1081 1082 struct mlx5_ifc_mac_address_layout_bits { 1083 u8 reserved_at_0[0x10]; 1084 u8 mac_addr_47_32[0x10]; 1085 1086 u8 mac_addr_31_0[0x20]; 1087 }; 1088 1089 struct mlx5_ifc_vlan_layout_bits { 1090 u8 reserved_at_0[0x14]; 1091 u8 vlan[0x0c]; 1092 1093 u8 reserved_at_20[0x20]; 1094 }; 1095 1096 struct mlx5_ifc_cong_control_r_roce_ecn_np_bits { 1097 u8 reserved_at_0[0xa0]; 1098 1099 u8 min_time_between_cnps[0x20]; 1100 1101 u8 reserved_at_c0[0x12]; 1102 u8 cnp_dscp[0x6]; 1103 u8 reserved_at_d8[0x5]; 1104 u8 cnp_802p_prio[0x3]; 1105 1106 u8 reserved_at_e0[0x720]; 1107 }; 1108 1109 struct mlx5_ifc_cong_control_r_roce_ecn_rp_bits { 1110 u8 reserved_at_0[0x60]; 1111 1112 u8 reserved_at_60[0x4]; 1113 u8 clamp_tgt_rate[0x1]; 1114 u8 reserved_at_65[0x3]; 1115 u8 clamp_tgt_rate_after_time_inc[0x1]; 1116 u8 reserved_at_69[0x17]; 1117 1118 u8 reserved_at_80[0x20]; 1119 1120 u8 rpg_time_reset[0x20]; 1121 1122 u8 rpg_byte_reset[0x20]; 1123 1124 u8 rpg_threshold[0x20]; 1125 1126 u8 rpg_max_rate[0x20]; 1127 1128 u8 rpg_ai_rate[0x20]; 1129 1130 u8 rpg_hai_rate[0x20]; 1131 1132 u8 rpg_gd[0x20]; 1133 1134 u8 rpg_min_dec_fac[0x20]; 1135 1136 u8 rpg_min_rate[0x20]; 1137 1138 u8 reserved_at_1c0[0xe0]; 1139 1140 u8 rate_to_set_on_first_cnp[0x20]; 1141 1142 u8 dce_tcp_g[0x20]; 1143 1144 u8 dce_tcp_rtt[0x20]; 1145 1146 u8 rate_reduce_monitor_period[0x20]; 1147 1148 u8 reserved_at_320[0x20]; 1149 1150 u8 initial_alpha_value[0x20]; 1151 1152 u8 reserved_at_360[0x4a0]; 1153 }; 1154 1155 struct mlx5_ifc_cong_control_802_1qau_rp_bits { 1156 u8 reserved_at_0[0x80]; 1157 1158 u8 rppp_max_rps[0x20]; 1159 1160 u8 rpg_time_reset[0x20]; 1161 1162 u8 rpg_byte_reset[0x20]; 1163 1164 u8 rpg_threshold[0x20]; 1165 1166 u8 rpg_max_rate[0x20]; 1167 1168 u8 rpg_ai_rate[0x20]; 1169 1170 u8 rpg_hai_rate[0x20]; 1171 1172 u8 rpg_gd[0x20]; 1173 1174 u8 rpg_min_dec_fac[0x20]; 1175 1176 u8 rpg_min_rate[0x20]; 1177 1178 u8 reserved_at_1c0[0x640]; 1179 }; 1180 1181 enum { 1182 MLX5_RESIZE_FIELD_SELECT_RESIZE_FIELD_SELECT_LOG_CQ_SIZE = 0x1, 1183 MLX5_RESIZE_FIELD_SELECT_RESIZE_FIELD_SELECT_PAGE_OFFSET = 0x2, 1184 MLX5_RESIZE_FIELD_SELECT_RESIZE_FIELD_SELECT_LOG_PAGE_SIZE = 0x4, 1185 }; 1186 1187 struct mlx5_ifc_resize_field_select_bits { 1188 u8 resize_field_select[0x20]; 1189 }; 1190 1191 enum { 1192 MLX5_MODIFY_FIELD_SELECT_MODIFY_FIELD_SELECT_CQ_PERIOD = 0x1, 1193 MLX5_MODIFY_FIELD_SELECT_MODIFY_FIELD_SELECT_CQ_MAX_COUNT = 0x2, 1194 MLX5_MODIFY_FIELD_SELECT_MODIFY_FIELD_SELECT_OI = 0x4, 1195 MLX5_MODIFY_FIELD_SELECT_MODIFY_FIELD_SELECT_C_EQN = 0x8, 1196 }; 1197 1198 struct mlx5_ifc_modify_field_select_bits { 1199 u8 modify_field_select[0x20]; 1200 }; 1201 1202 struct mlx5_ifc_field_select_r_roce_np_bits { 1203 u8 field_select_r_roce_np[0x20]; 1204 }; 1205 1206 struct mlx5_ifc_field_select_r_roce_rp_bits { 1207 u8 field_select_r_roce_rp[0x20]; 1208 }; 1209 1210 enum { 1211 MLX5_FIELD_SELECT_802_1QAU_RP_FIELD_SELECT_8021QAURP_RPPP_MAX_RPS = 0x4, 1212 MLX5_FIELD_SELECT_802_1QAU_RP_FIELD_SELECT_8021QAURP_RPG_TIME_RESET = 0x8, 1213 MLX5_FIELD_SELECT_802_1QAU_RP_FIELD_SELECT_8021QAURP_RPG_BYTE_RESET = 0x10, 1214 MLX5_FIELD_SELECT_802_1QAU_RP_FIELD_SELECT_8021QAURP_RPG_THRESHOLD = 0x20, 1215 MLX5_FIELD_SELECT_802_1QAU_RP_FIELD_SELECT_8021QAURP_RPG_MAX_RATE = 0x40, 1216 MLX5_FIELD_SELECT_802_1QAU_RP_FIELD_SELECT_8021QAURP_RPG_AI_RATE = 0x80, 1217 MLX5_FIELD_SELECT_802_1QAU_RP_FIELD_SELECT_8021QAURP_RPG_HAI_RATE = 0x100, 1218 MLX5_FIELD_SELECT_802_1QAU_RP_FIELD_SELECT_8021QAURP_RPG_GD = 0x200, 1219 MLX5_FIELD_SELECT_802_1QAU_RP_FIELD_SELECT_8021QAURP_RPG_MIN_DEC_FAC = 0x400, 1220 MLX5_FIELD_SELECT_802_1QAU_RP_FIELD_SELECT_8021QAURP_RPG_MIN_RATE = 0x800, 1221 }; 1222 1223 struct mlx5_ifc_field_select_802_1qau_rp_bits { 1224 u8 field_select_8021qaurp[0x20]; 1225 }; 1226 1227 struct mlx5_ifc_phys_layer_cntrs_bits { 1228 u8 time_since_last_clear_high[0x20]; 1229 1230 u8 time_since_last_clear_low[0x20]; 1231 1232 u8 symbol_errors_high[0x20]; 1233 1234 u8 symbol_errors_low[0x20]; 1235 1236 u8 sync_headers_errors_high[0x20]; 1237 1238 u8 sync_headers_errors_low[0x20]; 1239 1240 u8 edpl_bip_errors_lane0_high[0x20]; 1241 1242 u8 edpl_bip_errors_lane0_low[0x20]; 1243 1244 u8 edpl_bip_errors_lane1_high[0x20]; 1245 1246 u8 edpl_bip_errors_lane1_low[0x20]; 1247 1248 u8 edpl_bip_errors_lane2_high[0x20]; 1249 1250 u8 edpl_bip_errors_lane2_low[0x20]; 1251 1252 u8 edpl_bip_errors_lane3_high[0x20]; 1253 1254 u8 edpl_bip_errors_lane3_low[0x20]; 1255 1256 u8 fc_fec_corrected_blocks_lane0_high[0x20]; 1257 1258 u8 fc_fec_corrected_blocks_lane0_low[0x20]; 1259 1260 u8 fc_fec_corrected_blocks_lane1_high[0x20]; 1261 1262 u8 fc_fec_corrected_blocks_lane1_low[0x20]; 1263 1264 u8 fc_fec_corrected_blocks_lane2_high[0x20]; 1265 1266 u8 fc_fec_corrected_blocks_lane2_low[0x20]; 1267 1268 u8 fc_fec_corrected_blocks_lane3_high[0x20]; 1269 1270 u8 fc_fec_corrected_blocks_lane3_low[0x20]; 1271 1272 u8 fc_fec_uncorrectable_blocks_lane0_high[0x20]; 1273 1274 u8 fc_fec_uncorrectable_blocks_lane0_low[0x20]; 1275 1276 u8 fc_fec_uncorrectable_blocks_lane1_high[0x20]; 1277 1278 u8 fc_fec_uncorrectable_blocks_lane1_low[0x20]; 1279 1280 u8 fc_fec_uncorrectable_blocks_lane2_high[0x20]; 1281 1282 u8 fc_fec_uncorrectable_blocks_lane2_low[0x20]; 1283 1284 u8 fc_fec_uncorrectable_blocks_lane3_high[0x20]; 1285 1286 u8 fc_fec_uncorrectable_blocks_lane3_low[0x20]; 1287 1288 u8 rs_fec_corrected_blocks_high[0x20]; 1289 1290 u8 rs_fec_corrected_blocks_low[0x20]; 1291 1292 u8 rs_fec_uncorrectable_blocks_high[0x20]; 1293 1294 u8 rs_fec_uncorrectable_blocks_low[0x20]; 1295 1296 u8 rs_fec_no_errors_blocks_high[0x20]; 1297 1298 u8 rs_fec_no_errors_blocks_low[0x20]; 1299 1300 u8 rs_fec_single_error_blocks_high[0x20]; 1301 1302 u8 rs_fec_single_error_blocks_low[0x20]; 1303 1304 u8 rs_fec_corrected_symbols_total_high[0x20]; 1305 1306 u8 rs_fec_corrected_symbols_total_low[0x20]; 1307 1308 u8 rs_fec_corrected_symbols_lane0_high[0x20]; 1309 1310 u8 rs_fec_corrected_symbols_lane0_low[0x20]; 1311 1312 u8 rs_fec_corrected_symbols_lane1_high[0x20]; 1313 1314 u8 rs_fec_corrected_symbols_lane1_low[0x20]; 1315 1316 u8 rs_fec_corrected_symbols_lane2_high[0x20]; 1317 1318 u8 rs_fec_corrected_symbols_lane2_low[0x20]; 1319 1320 u8 rs_fec_corrected_symbols_lane3_high[0x20]; 1321 1322 u8 rs_fec_corrected_symbols_lane3_low[0x20]; 1323 1324 u8 link_down_events[0x20]; 1325 1326 u8 successful_recovery_events[0x20]; 1327 1328 u8 reserved_at_640[0x180]; 1329 }; 1330 1331 struct mlx5_ifc_ib_port_cntrs_grp_data_layout_bits { 1332 u8 symbol_error_counter[0x10]; 1333 1334 u8 link_error_recovery_counter[0x8]; 1335 1336 u8 link_downed_counter[0x8]; 1337 1338 u8 port_rcv_errors[0x10]; 1339 1340 u8 port_rcv_remote_physical_errors[0x10]; 1341 1342 u8 port_rcv_switch_relay_errors[0x10]; 1343 1344 u8 port_xmit_discards[0x10]; 1345 1346 u8 port_xmit_constraint_errors[0x8]; 1347 1348 u8 port_rcv_constraint_errors[0x8]; 1349 1350 u8 reserved_at_70[0x8]; 1351 1352 u8 link_overrun_errors[0x8]; 1353 1354 u8 reserved_at_80[0x10]; 1355 1356 u8 vl_15_dropped[0x10]; 1357 1358 u8 reserved_at_a0[0xa0]; 1359 }; 1360 1361 struct mlx5_ifc_eth_per_traffic_grp_data_layout_bits { 1362 u8 transmit_queue_high[0x20]; 1363 1364 u8 transmit_queue_low[0x20]; 1365 1366 u8 reserved_at_40[0x780]; 1367 }; 1368 1369 struct mlx5_ifc_eth_per_prio_grp_data_layout_bits { 1370 u8 rx_octets_high[0x20]; 1371 1372 u8 rx_octets_low[0x20]; 1373 1374 u8 reserved_at_40[0xc0]; 1375 1376 u8 rx_frames_high[0x20]; 1377 1378 u8 rx_frames_low[0x20]; 1379 1380 u8 tx_octets_high[0x20]; 1381 1382 u8 tx_octets_low[0x20]; 1383 1384 u8 reserved_at_180[0xc0]; 1385 1386 u8 tx_frames_high[0x20]; 1387 1388 u8 tx_frames_low[0x20]; 1389 1390 u8 rx_pause_high[0x20]; 1391 1392 u8 rx_pause_low[0x20]; 1393 1394 u8 rx_pause_duration_high[0x20]; 1395 1396 u8 rx_pause_duration_low[0x20]; 1397 1398 u8 tx_pause_high[0x20]; 1399 1400 u8 tx_pause_low[0x20]; 1401 1402 u8 tx_pause_duration_high[0x20]; 1403 1404 u8 tx_pause_duration_low[0x20]; 1405 1406 u8 rx_pause_transition_high[0x20]; 1407 1408 u8 rx_pause_transition_low[0x20]; 1409 1410 u8 reserved_at_3c0[0x400]; 1411 }; 1412 1413 struct mlx5_ifc_eth_extended_cntrs_grp_data_layout_bits { 1414 u8 port_transmit_wait_high[0x20]; 1415 1416 u8 port_transmit_wait_low[0x20]; 1417 1418 u8 reserved_at_40[0x780]; 1419 }; 1420 1421 struct mlx5_ifc_eth_3635_cntrs_grp_data_layout_bits { 1422 u8 dot3stats_alignment_errors_high[0x20]; 1423 1424 u8 dot3stats_alignment_errors_low[0x20]; 1425 1426 u8 dot3stats_fcs_errors_high[0x20]; 1427 1428 u8 dot3stats_fcs_errors_low[0x20]; 1429 1430 u8 dot3stats_single_collision_frames_high[0x20]; 1431 1432 u8 dot3stats_single_collision_frames_low[0x20]; 1433 1434 u8 dot3stats_multiple_collision_frames_high[0x20]; 1435 1436 u8 dot3stats_multiple_collision_frames_low[0x20]; 1437 1438 u8 dot3stats_sqe_test_errors_high[0x20]; 1439 1440 u8 dot3stats_sqe_test_errors_low[0x20]; 1441 1442 u8 dot3stats_deferred_transmissions_high[0x20]; 1443 1444 u8 dot3stats_deferred_transmissions_low[0x20]; 1445 1446 u8 dot3stats_late_collisions_high[0x20]; 1447 1448 u8 dot3stats_late_collisions_low[0x20]; 1449 1450 u8 dot3stats_excessive_collisions_high[0x20]; 1451 1452 u8 dot3stats_excessive_collisions_low[0x20]; 1453 1454 u8 dot3stats_internal_mac_transmit_errors_high[0x20]; 1455 1456 u8 dot3stats_internal_mac_transmit_errors_low[0x20]; 1457 1458 u8 dot3stats_carrier_sense_errors_high[0x20]; 1459 1460 u8 dot3stats_carrier_sense_errors_low[0x20]; 1461 1462 u8 dot3stats_frame_too_longs_high[0x20]; 1463 1464 u8 dot3stats_frame_too_longs_low[0x20]; 1465 1466 u8 dot3stats_internal_mac_receive_errors_high[0x20]; 1467 1468 u8 dot3stats_internal_mac_receive_errors_low[0x20]; 1469 1470 u8 dot3stats_symbol_errors_high[0x20]; 1471 1472 u8 dot3stats_symbol_errors_low[0x20]; 1473 1474 u8 dot3control_in_unknown_opcodes_high[0x20]; 1475 1476 u8 dot3control_in_unknown_opcodes_low[0x20]; 1477 1478 u8 dot3in_pause_frames_high[0x20]; 1479 1480 u8 dot3in_pause_frames_low[0x20]; 1481 1482 u8 dot3out_pause_frames_high[0x20]; 1483 1484 u8 dot3out_pause_frames_low[0x20]; 1485 1486 u8 reserved_at_400[0x3c0]; 1487 }; 1488 1489 struct mlx5_ifc_eth_2819_cntrs_grp_data_layout_bits { 1490 u8 ether_stats_drop_events_high[0x20]; 1491 1492 u8 ether_stats_drop_events_low[0x20]; 1493 1494 u8 ether_stats_octets_high[0x20]; 1495 1496 u8 ether_stats_octets_low[0x20]; 1497 1498 u8 ether_stats_pkts_high[0x20]; 1499 1500 u8 ether_stats_pkts_low[0x20]; 1501 1502 u8 ether_stats_broadcast_pkts_high[0x20]; 1503 1504 u8 ether_stats_broadcast_pkts_low[0x20]; 1505 1506 u8 ether_stats_multicast_pkts_high[0x20]; 1507 1508 u8 ether_stats_multicast_pkts_low[0x20]; 1509 1510 u8 ether_stats_crc_align_errors_high[0x20]; 1511 1512 u8 ether_stats_crc_align_errors_low[0x20]; 1513 1514 u8 ether_stats_undersize_pkts_high[0x20]; 1515 1516 u8 ether_stats_undersize_pkts_low[0x20]; 1517 1518 u8 ether_stats_oversize_pkts_high[0x20]; 1519 1520 u8 ether_stats_oversize_pkts_low[0x20]; 1521 1522 u8 ether_stats_fragments_high[0x20]; 1523 1524 u8 ether_stats_fragments_low[0x20]; 1525 1526 u8 ether_stats_jabbers_high[0x20]; 1527 1528 u8 ether_stats_jabbers_low[0x20]; 1529 1530 u8 ether_stats_collisions_high[0x20]; 1531 1532 u8 ether_stats_collisions_low[0x20]; 1533 1534 u8 ether_stats_pkts64octets_high[0x20]; 1535 1536 u8 ether_stats_pkts64octets_low[0x20]; 1537 1538 u8 ether_stats_pkts65to127octets_high[0x20]; 1539 1540 u8 ether_stats_pkts65to127octets_low[0x20]; 1541 1542 u8 ether_stats_pkts128to255octets_high[0x20]; 1543 1544 u8 ether_stats_pkts128to255octets_low[0x20]; 1545 1546 u8 ether_stats_pkts256to511octets_high[0x20]; 1547 1548 u8 ether_stats_pkts256to511octets_low[0x20]; 1549 1550 u8 ether_stats_pkts512to1023octets_high[0x20]; 1551 1552 u8 ether_stats_pkts512to1023octets_low[0x20]; 1553 1554 u8 ether_stats_pkts1024to1518octets_high[0x20]; 1555 1556 u8 ether_stats_pkts1024to1518octets_low[0x20]; 1557 1558 u8 ether_stats_pkts1519to2047octets_high[0x20]; 1559 1560 u8 ether_stats_pkts1519to2047octets_low[0x20]; 1561 1562 u8 ether_stats_pkts2048to4095octets_high[0x20]; 1563 1564 u8 ether_stats_pkts2048to4095octets_low[0x20]; 1565 1566 u8 ether_stats_pkts4096to8191octets_high[0x20]; 1567 1568 u8 ether_stats_pkts4096to8191octets_low[0x20]; 1569 1570 u8 ether_stats_pkts8192to10239octets_high[0x20]; 1571 1572 u8 ether_stats_pkts8192to10239octets_low[0x20]; 1573 1574 u8 reserved_at_540[0x280]; 1575 }; 1576 1577 struct mlx5_ifc_eth_2863_cntrs_grp_data_layout_bits { 1578 u8 if_in_octets_high[0x20]; 1579 1580 u8 if_in_octets_low[0x20]; 1581 1582 u8 if_in_ucast_pkts_high[0x20]; 1583 1584 u8 if_in_ucast_pkts_low[0x20]; 1585 1586 u8 if_in_discards_high[0x20]; 1587 1588 u8 if_in_discards_low[0x20]; 1589 1590 u8 if_in_errors_high[0x20]; 1591 1592 u8 if_in_errors_low[0x20]; 1593 1594 u8 if_in_unknown_protos_high[0x20]; 1595 1596 u8 if_in_unknown_protos_low[0x20]; 1597 1598 u8 if_out_octets_high[0x20]; 1599 1600 u8 if_out_octets_low[0x20]; 1601 1602 u8 if_out_ucast_pkts_high[0x20]; 1603 1604 u8 if_out_ucast_pkts_low[0x20]; 1605 1606 u8 if_out_discards_high[0x20]; 1607 1608 u8 if_out_discards_low[0x20]; 1609 1610 u8 if_out_errors_high[0x20]; 1611 1612 u8 if_out_errors_low[0x20]; 1613 1614 u8 if_in_multicast_pkts_high[0x20]; 1615 1616 u8 if_in_multicast_pkts_low[0x20]; 1617 1618 u8 if_in_broadcast_pkts_high[0x20]; 1619 1620 u8 if_in_broadcast_pkts_low[0x20]; 1621 1622 u8 if_out_multicast_pkts_high[0x20]; 1623 1624 u8 if_out_multicast_pkts_low[0x20]; 1625 1626 u8 if_out_broadcast_pkts_high[0x20]; 1627 1628 u8 if_out_broadcast_pkts_low[0x20]; 1629 1630 u8 reserved_at_340[0x480]; 1631 }; 1632 1633 struct mlx5_ifc_eth_802_3_cntrs_grp_data_layout_bits { 1634 u8 a_frames_transmitted_ok_high[0x20]; 1635 1636 u8 a_frames_transmitted_ok_low[0x20]; 1637 1638 u8 a_frames_received_ok_high[0x20]; 1639 1640 u8 a_frames_received_ok_low[0x20]; 1641 1642 u8 a_frame_check_sequence_errors_high[0x20]; 1643 1644 u8 a_frame_check_sequence_errors_low[0x20]; 1645 1646 u8 a_alignment_errors_high[0x20]; 1647 1648 u8 a_alignment_errors_low[0x20]; 1649 1650 u8 a_octets_transmitted_ok_high[0x20]; 1651 1652 u8 a_octets_transmitted_ok_low[0x20]; 1653 1654 u8 a_octets_received_ok_high[0x20]; 1655 1656 u8 a_octets_received_ok_low[0x20]; 1657 1658 u8 a_multicast_frames_xmitted_ok_high[0x20]; 1659 1660 u8 a_multicast_frames_xmitted_ok_low[0x20]; 1661 1662 u8 a_broadcast_frames_xmitted_ok_high[0x20]; 1663 1664 u8 a_broadcast_frames_xmitted_ok_low[0x20]; 1665 1666 u8 a_multicast_frames_received_ok_high[0x20]; 1667 1668 u8 a_multicast_frames_received_ok_low[0x20]; 1669 1670 u8 a_broadcast_frames_received_ok_high[0x20]; 1671 1672 u8 a_broadcast_frames_received_ok_low[0x20]; 1673 1674 u8 a_in_range_length_errors_high[0x20]; 1675 1676 u8 a_in_range_length_errors_low[0x20]; 1677 1678 u8 a_out_of_range_length_field_high[0x20]; 1679 1680 u8 a_out_of_range_length_field_low[0x20]; 1681 1682 u8 a_frame_too_long_errors_high[0x20]; 1683 1684 u8 a_frame_too_long_errors_low[0x20]; 1685 1686 u8 a_symbol_error_during_carrier_high[0x20]; 1687 1688 u8 a_symbol_error_during_carrier_low[0x20]; 1689 1690 u8 a_mac_control_frames_transmitted_high[0x20]; 1691 1692 u8 a_mac_control_frames_transmitted_low[0x20]; 1693 1694 u8 a_mac_control_frames_received_high[0x20]; 1695 1696 u8 a_mac_control_frames_received_low[0x20]; 1697 1698 u8 a_unsupported_opcodes_received_high[0x20]; 1699 1700 u8 a_unsupported_opcodes_received_low[0x20]; 1701 1702 u8 a_pause_mac_ctrl_frames_received_high[0x20]; 1703 1704 u8 a_pause_mac_ctrl_frames_received_low[0x20]; 1705 1706 u8 a_pause_mac_ctrl_frames_transmitted_high[0x20]; 1707 1708 u8 a_pause_mac_ctrl_frames_transmitted_low[0x20]; 1709 1710 u8 reserved_at_4c0[0x300]; 1711 }; 1712 1713 struct mlx5_ifc_cmd_inter_comp_event_bits { 1714 u8 command_completion_vector[0x20]; 1715 1716 u8 reserved_at_20[0xc0]; 1717 }; 1718 1719 struct mlx5_ifc_stall_vl_event_bits { 1720 u8 reserved_at_0[0x18]; 1721 u8 port_num[0x1]; 1722 u8 reserved_at_19[0x3]; 1723 u8 vl[0x4]; 1724 1725 u8 reserved_at_20[0xa0]; 1726 }; 1727 1728 struct mlx5_ifc_db_bf_congestion_event_bits { 1729 u8 event_subtype[0x8]; 1730 u8 reserved_at_8[0x8]; 1731 u8 congestion_level[0x8]; 1732 u8 reserved_at_18[0x8]; 1733 1734 u8 reserved_at_20[0xa0]; 1735 }; 1736 1737 struct mlx5_ifc_gpio_event_bits { 1738 u8 reserved_at_0[0x60]; 1739 1740 u8 gpio_event_hi[0x20]; 1741 1742 u8 gpio_event_lo[0x20]; 1743 1744 u8 reserved_at_a0[0x40]; 1745 }; 1746 1747 struct mlx5_ifc_port_state_change_event_bits { 1748 u8 reserved_at_0[0x40]; 1749 1750 u8 port_num[0x4]; 1751 u8 reserved_at_44[0x1c]; 1752 1753 u8 reserved_at_60[0x80]; 1754 }; 1755 1756 struct mlx5_ifc_dropped_packet_logged_bits { 1757 u8 reserved_at_0[0xe0]; 1758 }; 1759 1760 enum { 1761 MLX5_CQ_ERROR_SYNDROME_CQ_OVERRUN = 0x1, 1762 MLX5_CQ_ERROR_SYNDROME_CQ_ACCESS_VIOLATION_ERROR = 0x2, 1763 }; 1764 1765 struct mlx5_ifc_cq_error_bits { 1766 u8 reserved_at_0[0x8]; 1767 u8 cqn[0x18]; 1768 1769 u8 reserved_at_20[0x20]; 1770 1771 u8 reserved_at_40[0x18]; 1772 u8 syndrome[0x8]; 1773 1774 u8 reserved_at_60[0x80]; 1775 }; 1776 1777 struct mlx5_ifc_rdma_page_fault_event_bits { 1778 u8 bytes_committed[0x20]; 1779 1780 u8 r_key[0x20]; 1781 1782 u8 reserved_at_40[0x10]; 1783 u8 packet_len[0x10]; 1784 1785 u8 rdma_op_len[0x20]; 1786 1787 u8 rdma_va[0x40]; 1788 1789 u8 reserved_at_c0[0x5]; 1790 u8 rdma[0x1]; 1791 u8 write[0x1]; 1792 u8 requestor[0x1]; 1793 u8 qp_number[0x18]; 1794 }; 1795 1796 struct mlx5_ifc_wqe_associated_page_fault_event_bits { 1797 u8 bytes_committed[0x20]; 1798 1799 u8 reserved_at_20[0x10]; 1800 u8 wqe_index[0x10]; 1801 1802 u8 reserved_at_40[0x10]; 1803 u8 len[0x10]; 1804 1805 u8 reserved_at_60[0x60]; 1806 1807 u8 reserved_at_c0[0x5]; 1808 u8 rdma[0x1]; 1809 u8 write_read[0x1]; 1810 u8 requestor[0x1]; 1811 u8 qpn[0x18]; 1812 }; 1813 1814 struct mlx5_ifc_qp_events_bits { 1815 u8 reserved_at_0[0xa0]; 1816 1817 u8 type[0x8]; 1818 u8 reserved_at_a8[0x18]; 1819 1820 u8 reserved_at_c0[0x8]; 1821 u8 qpn_rqn_sqn[0x18]; 1822 }; 1823 1824 struct mlx5_ifc_dct_events_bits { 1825 u8 reserved_at_0[0xc0]; 1826 1827 u8 reserved_at_c0[0x8]; 1828 u8 dct_number[0x18]; 1829 }; 1830 1831 struct mlx5_ifc_comp_event_bits { 1832 u8 reserved_at_0[0xc0]; 1833 1834 u8 reserved_at_c0[0x8]; 1835 u8 cq_number[0x18]; 1836 }; 1837 1838 enum { 1839 MLX5_QPC_STATE_RST = 0x0, 1840 MLX5_QPC_STATE_INIT = 0x1, 1841 MLX5_QPC_STATE_RTR = 0x2, 1842 MLX5_QPC_STATE_RTS = 0x3, 1843 MLX5_QPC_STATE_SQER = 0x4, 1844 MLX5_QPC_STATE_ERR = 0x6, 1845 MLX5_QPC_STATE_SQD = 0x7, 1846 MLX5_QPC_STATE_SUSPENDED = 0x9, 1847 }; 1848 1849 enum { 1850 MLX5_QPC_ST_RC = 0x0, 1851 MLX5_QPC_ST_UC = 0x1, 1852 MLX5_QPC_ST_UD = 0x2, 1853 MLX5_QPC_ST_XRC = 0x3, 1854 MLX5_QPC_ST_DCI = 0x5, 1855 MLX5_QPC_ST_QP0 = 0x7, 1856 MLX5_QPC_ST_QP1 = 0x8, 1857 MLX5_QPC_ST_RAW_DATAGRAM = 0x9, 1858 MLX5_QPC_ST_REG_UMR = 0xc, 1859 }; 1860 1861 enum { 1862 MLX5_QPC_PM_STATE_ARMED = 0x0, 1863 MLX5_QPC_PM_STATE_REARM = 0x1, 1864 MLX5_QPC_PM_STATE_RESERVED = 0x2, 1865 MLX5_QPC_PM_STATE_MIGRATED = 0x3, 1866 }; 1867 1868 enum { 1869 MLX5_QPC_END_PADDING_MODE_SCATTER_AS_IS = 0x0, 1870 MLX5_QPC_END_PADDING_MODE_PAD_TO_CACHE_LINE_ALIGNMENT = 0x1, 1871 }; 1872 1873 enum { 1874 MLX5_QPC_MTU_256_BYTES = 0x1, 1875 MLX5_QPC_MTU_512_BYTES = 0x2, 1876 MLX5_QPC_MTU_1K_BYTES = 0x3, 1877 MLX5_QPC_MTU_2K_BYTES = 0x4, 1878 MLX5_QPC_MTU_4K_BYTES = 0x5, 1879 MLX5_QPC_MTU_RAW_ETHERNET_QP = 0x7, 1880 }; 1881 1882 enum { 1883 MLX5_QPC_ATOMIC_MODE_IB_SPEC = 0x1, 1884 MLX5_QPC_ATOMIC_MODE_ONLY_8B = 0x2, 1885 MLX5_QPC_ATOMIC_MODE_UP_TO_8B = 0x3, 1886 MLX5_QPC_ATOMIC_MODE_UP_TO_16B = 0x4, 1887 MLX5_QPC_ATOMIC_MODE_UP_TO_32B = 0x5, 1888 MLX5_QPC_ATOMIC_MODE_UP_TO_64B = 0x6, 1889 MLX5_QPC_ATOMIC_MODE_UP_TO_128B = 0x7, 1890 MLX5_QPC_ATOMIC_MODE_UP_TO_256B = 0x8, 1891 }; 1892 1893 enum { 1894 MLX5_QPC_CS_REQ_DISABLE = 0x0, 1895 MLX5_QPC_CS_REQ_UP_TO_32B = 0x11, 1896 MLX5_QPC_CS_REQ_UP_TO_64B = 0x22, 1897 }; 1898 1899 enum { 1900 MLX5_QPC_CS_RES_DISABLE = 0x0, 1901 MLX5_QPC_CS_RES_UP_TO_32B = 0x1, 1902 MLX5_QPC_CS_RES_UP_TO_64B = 0x2, 1903 }; 1904 1905 struct mlx5_ifc_qpc_bits { 1906 u8 state[0x4]; 1907 u8 reserved_at_4[0x4]; 1908 u8 st[0x8]; 1909 u8 reserved_at_10[0x3]; 1910 u8 pm_state[0x2]; 1911 u8 reserved_at_15[0x7]; 1912 u8 end_padding_mode[0x2]; 1913 u8 reserved_at_1e[0x2]; 1914 1915 u8 wq_signature[0x1]; 1916 u8 block_lb_mc[0x1]; 1917 u8 atomic_like_write_en[0x1]; 1918 u8 latency_sensitive[0x1]; 1919 u8 reserved_at_24[0x1]; 1920 u8 drain_sigerr[0x1]; 1921 u8 reserved_at_26[0x2]; 1922 u8 pd[0x18]; 1923 1924 u8 mtu[0x3]; 1925 u8 log_msg_max[0x5]; 1926 u8 reserved_at_48[0x1]; 1927 u8 log_rq_size[0x4]; 1928 u8 log_rq_stride[0x3]; 1929 u8 no_sq[0x1]; 1930 u8 log_sq_size[0x4]; 1931 u8 reserved_at_55[0x6]; 1932 u8 rlky[0x1]; 1933 u8 ulp_stateless_offload_mode[0x4]; 1934 1935 u8 counter_set_id[0x8]; 1936 u8 uar_page[0x18]; 1937 1938 u8 reserved_at_80[0x8]; 1939 u8 user_index[0x18]; 1940 1941 u8 reserved_at_a0[0x3]; 1942 u8 log_page_size[0x5]; 1943 u8 remote_qpn[0x18]; 1944 1945 struct mlx5_ifc_ads_bits primary_address_path; 1946 1947 struct mlx5_ifc_ads_bits secondary_address_path; 1948 1949 u8 log_ack_req_freq[0x4]; 1950 u8 reserved_at_384[0x4]; 1951 u8 log_sra_max[0x3]; 1952 u8 reserved_at_38b[0x2]; 1953 u8 retry_count[0x3]; 1954 u8 rnr_retry[0x3]; 1955 u8 reserved_at_393[0x1]; 1956 u8 fre[0x1]; 1957 u8 cur_rnr_retry[0x3]; 1958 u8 cur_retry_count[0x3]; 1959 u8 reserved_at_39b[0x5]; 1960 1961 u8 reserved_at_3a0[0x20]; 1962 1963 u8 reserved_at_3c0[0x8]; 1964 u8 next_send_psn[0x18]; 1965 1966 u8 reserved_at_3e0[0x8]; 1967 u8 cqn_snd[0x18]; 1968 1969 u8 reserved_at_400[0x40]; 1970 1971 u8 reserved_at_440[0x8]; 1972 u8 last_acked_psn[0x18]; 1973 1974 u8 reserved_at_460[0x8]; 1975 u8 ssn[0x18]; 1976 1977 u8 reserved_at_480[0x8]; 1978 u8 log_rra_max[0x3]; 1979 u8 reserved_at_48b[0x1]; 1980 u8 atomic_mode[0x4]; 1981 u8 rre[0x1]; 1982 u8 rwe[0x1]; 1983 u8 rae[0x1]; 1984 u8 reserved_at_493[0x1]; 1985 u8 page_offset[0x6]; 1986 u8 reserved_at_49a[0x3]; 1987 u8 cd_slave_receive[0x1]; 1988 u8 cd_slave_send[0x1]; 1989 u8 cd_master[0x1]; 1990 1991 u8 reserved_at_4a0[0x3]; 1992 u8 min_rnr_nak[0x5]; 1993 u8 next_rcv_psn[0x18]; 1994 1995 u8 reserved_at_4c0[0x8]; 1996 u8 xrcd[0x18]; 1997 1998 u8 reserved_at_4e0[0x8]; 1999 u8 cqn_rcv[0x18]; 2000 2001 u8 dbr_addr[0x40]; 2002 2003 u8 q_key[0x20]; 2004 2005 u8 reserved_at_560[0x5]; 2006 u8 rq_type[0x3]; 2007 u8 srqn_rmpn_xrqn[0x18]; 2008 2009 u8 reserved_at_580[0x8]; 2010 u8 rmsn[0x18]; 2011 2012 u8 hw_sq_wqebb_counter[0x10]; 2013 u8 sw_sq_wqebb_counter[0x10]; 2014 2015 u8 hw_rq_counter[0x20]; 2016 2017 u8 sw_rq_counter[0x20]; 2018 2019 u8 reserved_at_600[0x20]; 2020 2021 u8 reserved_at_620[0xf]; 2022 u8 cgs[0x1]; 2023 u8 cs_req[0x8]; 2024 u8 cs_res[0x8]; 2025 2026 u8 dc_access_key[0x40]; 2027 2028 u8 reserved_at_680[0xc0]; 2029 }; 2030 2031 struct mlx5_ifc_roce_addr_layout_bits { 2032 u8 source_l3_address[16][0x8]; 2033 2034 u8 reserved_at_80[0x3]; 2035 u8 vlan_valid[0x1]; 2036 u8 vlan_id[0xc]; 2037 u8 source_mac_47_32[0x10]; 2038 2039 u8 source_mac_31_0[0x20]; 2040 2041 u8 reserved_at_c0[0x14]; 2042 u8 roce_l3_type[0x4]; 2043 u8 roce_version[0x8]; 2044 2045 u8 reserved_at_e0[0x20]; 2046 }; 2047 2048 union mlx5_ifc_hca_cap_union_bits { 2049 struct mlx5_ifc_cmd_hca_cap_bits cmd_hca_cap; 2050 struct mlx5_ifc_odp_cap_bits odp_cap; 2051 struct mlx5_ifc_atomic_caps_bits atomic_caps; 2052 struct mlx5_ifc_roce_cap_bits roce_cap; 2053 struct mlx5_ifc_per_protocol_networking_offload_caps_bits per_protocol_networking_offload_caps; 2054 struct mlx5_ifc_flow_table_nic_cap_bits flow_table_nic_cap; 2055 struct mlx5_ifc_flow_table_eswitch_cap_bits flow_table_eswitch_cap; 2056 struct mlx5_ifc_e_switch_cap_bits e_switch_cap; 2057 struct mlx5_ifc_vector_calc_cap_bits vector_calc_cap; 2058 struct mlx5_ifc_qos_cap_bits qos_cap; 2059 u8 reserved_at_0[0x8000]; 2060 }; 2061 2062 enum { 2063 MLX5_FLOW_CONTEXT_ACTION_ALLOW = 0x1, 2064 MLX5_FLOW_CONTEXT_ACTION_DROP = 0x2, 2065 MLX5_FLOW_CONTEXT_ACTION_FWD_DEST = 0x4, 2066 MLX5_FLOW_CONTEXT_ACTION_COUNT = 0x8, 2067 }; 2068 2069 struct mlx5_ifc_flow_context_bits { 2070 u8 reserved_at_0[0x20]; 2071 2072 u8 group_id[0x20]; 2073 2074 u8 reserved_at_40[0x8]; 2075 u8 flow_tag[0x18]; 2076 2077 u8 reserved_at_60[0x10]; 2078 u8 action[0x10]; 2079 2080 u8 reserved_at_80[0x8]; 2081 u8 destination_list_size[0x18]; 2082 2083 u8 reserved_at_a0[0x8]; 2084 u8 flow_counter_list_size[0x18]; 2085 2086 u8 reserved_at_c0[0x140]; 2087 2088 struct mlx5_ifc_fte_match_param_bits match_value; 2089 2090 u8 reserved_at_1200[0x600]; 2091 2092 union mlx5_ifc_dest_format_struct_flow_counter_list_auto_bits destination[0]; 2093 }; 2094 2095 enum { 2096 MLX5_XRC_SRQC_STATE_GOOD = 0x0, 2097 MLX5_XRC_SRQC_STATE_ERROR = 0x1, 2098 }; 2099 2100 struct mlx5_ifc_xrc_srqc_bits { 2101 u8 state[0x4]; 2102 u8 log_xrc_srq_size[0x4]; 2103 u8 reserved_at_8[0x18]; 2104 2105 u8 wq_signature[0x1]; 2106 u8 cont_srq[0x1]; 2107 u8 reserved_at_22[0x1]; 2108 u8 rlky[0x1]; 2109 u8 basic_cyclic_rcv_wqe[0x1]; 2110 u8 log_rq_stride[0x3]; 2111 u8 xrcd[0x18]; 2112 2113 u8 page_offset[0x6]; 2114 u8 reserved_at_46[0x2]; 2115 u8 cqn[0x18]; 2116 2117 u8 reserved_at_60[0x20]; 2118 2119 u8 user_index_equal_xrc_srqn[0x1]; 2120 u8 reserved_at_81[0x1]; 2121 u8 log_page_size[0x6]; 2122 u8 user_index[0x18]; 2123 2124 u8 reserved_at_a0[0x20]; 2125 2126 u8 reserved_at_c0[0x8]; 2127 u8 pd[0x18]; 2128 2129 u8 lwm[0x10]; 2130 u8 wqe_cnt[0x10]; 2131 2132 u8 reserved_at_100[0x40]; 2133 2134 u8 db_record_addr_h[0x20]; 2135 2136 u8 db_record_addr_l[0x1e]; 2137 u8 reserved_at_17e[0x2]; 2138 2139 u8 reserved_at_180[0x80]; 2140 }; 2141 2142 struct mlx5_ifc_traffic_counter_bits { 2143 u8 packets[0x40]; 2144 2145 u8 octets[0x40]; 2146 }; 2147 2148 struct mlx5_ifc_tisc_bits { 2149 u8 reserved_at_0[0xc]; 2150 u8 prio[0x4]; 2151 u8 reserved_at_10[0x10]; 2152 2153 u8 reserved_at_20[0x100]; 2154 2155 u8 reserved_at_120[0x8]; 2156 u8 transport_domain[0x18]; 2157 2158 u8 reserved_at_140[0x3c0]; 2159 }; 2160 2161 enum { 2162 MLX5_TIRC_DISP_TYPE_DIRECT = 0x0, 2163 MLX5_TIRC_DISP_TYPE_INDIRECT = 0x1, 2164 }; 2165 2166 enum { 2167 MLX5_TIRC_LRO_ENABLE_MASK_IPV4_LRO = 0x1, 2168 MLX5_TIRC_LRO_ENABLE_MASK_IPV6_LRO = 0x2, 2169 }; 2170 2171 enum { 2172 MLX5_RX_HASH_FN_NONE = 0x0, 2173 MLX5_RX_HASH_FN_INVERTED_XOR8 = 0x1, 2174 MLX5_RX_HASH_FN_TOEPLITZ = 0x2, 2175 }; 2176 2177 enum { 2178 MLX5_TIRC_SELF_LB_BLOCK_BLOCK_UNICAST_ = 0x1, 2179 MLX5_TIRC_SELF_LB_BLOCK_BLOCK_MULTICAST_ = 0x2, 2180 }; 2181 2182 struct mlx5_ifc_tirc_bits { 2183 u8 reserved_at_0[0x20]; 2184 2185 u8 disp_type[0x4]; 2186 u8 reserved_at_24[0x1c]; 2187 2188 u8 reserved_at_40[0x40]; 2189 2190 u8 reserved_at_80[0x4]; 2191 u8 lro_timeout_period_usecs[0x10]; 2192 u8 lro_enable_mask[0x4]; 2193 u8 lro_max_ip_payload_size[0x8]; 2194 2195 u8 reserved_at_a0[0x40]; 2196 2197 u8 reserved_at_e0[0x8]; 2198 u8 inline_rqn[0x18]; 2199 2200 u8 rx_hash_symmetric[0x1]; 2201 u8 reserved_at_101[0x1]; 2202 u8 tunneled_offload_en[0x1]; 2203 u8 reserved_at_103[0x5]; 2204 u8 indirect_table[0x18]; 2205 2206 u8 rx_hash_fn[0x4]; 2207 u8 reserved_at_124[0x2]; 2208 u8 self_lb_block[0x2]; 2209 u8 transport_domain[0x18]; 2210 2211 u8 rx_hash_toeplitz_key[10][0x20]; 2212 2213 struct mlx5_ifc_rx_hash_field_select_bits rx_hash_field_selector_outer; 2214 2215 struct mlx5_ifc_rx_hash_field_select_bits rx_hash_field_selector_inner; 2216 2217 u8 reserved_at_2c0[0x4c0]; 2218 }; 2219 2220 enum { 2221 MLX5_SRQC_STATE_GOOD = 0x0, 2222 MLX5_SRQC_STATE_ERROR = 0x1, 2223 }; 2224 2225 struct mlx5_ifc_srqc_bits { 2226 u8 state[0x4]; 2227 u8 log_srq_size[0x4]; 2228 u8 reserved_at_8[0x18]; 2229 2230 u8 wq_signature[0x1]; 2231 u8 cont_srq[0x1]; 2232 u8 reserved_at_22[0x1]; 2233 u8 rlky[0x1]; 2234 u8 reserved_at_24[0x1]; 2235 u8 log_rq_stride[0x3]; 2236 u8 xrcd[0x18]; 2237 2238 u8 page_offset[0x6]; 2239 u8 reserved_at_46[0x2]; 2240 u8 cqn[0x18]; 2241 2242 u8 reserved_at_60[0x20]; 2243 2244 u8 reserved_at_80[0x2]; 2245 u8 log_page_size[0x6]; 2246 u8 reserved_at_88[0x18]; 2247 2248 u8 reserved_at_a0[0x20]; 2249 2250 u8 reserved_at_c0[0x8]; 2251 u8 pd[0x18]; 2252 2253 u8 lwm[0x10]; 2254 u8 wqe_cnt[0x10]; 2255 2256 u8 reserved_at_100[0x40]; 2257 2258 u8 dbr_addr[0x40]; 2259 2260 u8 reserved_at_180[0x80]; 2261 }; 2262 2263 enum { 2264 MLX5_SQC_STATE_RST = 0x0, 2265 MLX5_SQC_STATE_RDY = 0x1, 2266 MLX5_SQC_STATE_ERR = 0x3, 2267 }; 2268 2269 struct mlx5_ifc_sqc_bits { 2270 u8 rlky[0x1]; 2271 u8 cd_master[0x1]; 2272 u8 fre[0x1]; 2273 u8 flush_in_error_en[0x1]; 2274 u8 reserved_at_4[0x1]; 2275 u8 min_wqe_inline_mode[0x3]; 2276 u8 state[0x4]; 2277 u8 reg_umr[0x1]; 2278 u8 reserved_at_d[0x13]; 2279 2280 u8 reserved_at_20[0x8]; 2281 u8 user_index[0x18]; 2282 2283 u8 reserved_at_40[0x8]; 2284 u8 cqn[0x18]; 2285 2286 u8 reserved_at_60[0x90]; 2287 2288 u8 packet_pacing_rate_limit_index[0x10]; 2289 u8 tis_lst_sz[0x10]; 2290 u8 reserved_at_110[0x10]; 2291 2292 u8 reserved_at_120[0x40]; 2293 2294 u8 reserved_at_160[0x8]; 2295 u8 tis_num_0[0x18]; 2296 2297 struct mlx5_ifc_wq_bits wq; 2298 }; 2299 2300 struct mlx5_ifc_rqtc_bits { 2301 u8 reserved_at_0[0xa0]; 2302 2303 u8 reserved_at_a0[0x10]; 2304 u8 rqt_max_size[0x10]; 2305 2306 u8 reserved_at_c0[0x10]; 2307 u8 rqt_actual_size[0x10]; 2308 2309 u8 reserved_at_e0[0x6a0]; 2310 2311 struct mlx5_ifc_rq_num_bits rq_num[0]; 2312 }; 2313 2314 enum { 2315 MLX5_RQC_MEM_RQ_TYPE_MEMORY_RQ_INLINE = 0x0, 2316 MLX5_RQC_MEM_RQ_TYPE_MEMORY_RQ_RMP = 0x1, 2317 }; 2318 2319 enum { 2320 MLX5_RQC_STATE_RST = 0x0, 2321 MLX5_RQC_STATE_RDY = 0x1, 2322 MLX5_RQC_STATE_ERR = 0x3, 2323 }; 2324 2325 struct mlx5_ifc_rqc_bits { 2326 u8 rlky[0x1]; 2327 u8 reserved_at_1[0x1]; 2328 u8 scatter_fcs[0x1]; 2329 u8 vsd[0x1]; 2330 u8 mem_rq_type[0x4]; 2331 u8 state[0x4]; 2332 u8 reserved_at_c[0x1]; 2333 u8 flush_in_error_en[0x1]; 2334 u8 reserved_at_e[0x12]; 2335 2336 u8 reserved_at_20[0x8]; 2337 u8 user_index[0x18]; 2338 2339 u8 reserved_at_40[0x8]; 2340 u8 cqn[0x18]; 2341 2342 u8 counter_set_id[0x8]; 2343 u8 reserved_at_68[0x18]; 2344 2345 u8 reserved_at_80[0x8]; 2346 u8 rmpn[0x18]; 2347 2348 u8 reserved_at_a0[0xe0]; 2349 2350 struct mlx5_ifc_wq_bits wq; 2351 }; 2352 2353 enum { 2354 MLX5_RMPC_STATE_RDY = 0x1, 2355 MLX5_RMPC_STATE_ERR = 0x3, 2356 }; 2357 2358 struct mlx5_ifc_rmpc_bits { 2359 u8 reserved_at_0[0x8]; 2360 u8 state[0x4]; 2361 u8 reserved_at_c[0x14]; 2362 2363 u8 basic_cyclic_rcv_wqe[0x1]; 2364 u8 reserved_at_21[0x1f]; 2365 2366 u8 reserved_at_40[0x140]; 2367 2368 struct mlx5_ifc_wq_bits wq; 2369 }; 2370 2371 struct mlx5_ifc_nic_vport_context_bits { 2372 u8 reserved_at_0[0x5]; 2373 u8 min_wqe_inline_mode[0x3]; 2374 u8 reserved_at_8[0x17]; 2375 u8 roce_en[0x1]; 2376 2377 u8 arm_change_event[0x1]; 2378 u8 reserved_at_21[0x1a]; 2379 u8 event_on_mtu[0x1]; 2380 u8 event_on_promisc_change[0x1]; 2381 u8 event_on_vlan_change[0x1]; 2382 u8 event_on_mc_address_change[0x1]; 2383 u8 event_on_uc_address_change[0x1]; 2384 2385 u8 reserved_at_40[0xf0]; 2386 2387 u8 mtu[0x10]; 2388 2389 u8 system_image_guid[0x40]; 2390 u8 port_guid[0x40]; 2391 u8 node_guid[0x40]; 2392 2393 u8 reserved_at_200[0x140]; 2394 u8 qkey_violation_counter[0x10]; 2395 u8 reserved_at_350[0x430]; 2396 2397 u8 promisc_uc[0x1]; 2398 u8 promisc_mc[0x1]; 2399 u8 promisc_all[0x1]; 2400 u8 reserved_at_783[0x2]; 2401 u8 allowed_list_type[0x3]; 2402 u8 reserved_at_788[0xc]; 2403 u8 allowed_list_size[0xc]; 2404 2405 struct mlx5_ifc_mac_address_layout_bits permanent_address; 2406 2407 u8 reserved_at_7e0[0x20]; 2408 2409 u8 current_uc_mac_address[0][0x40]; 2410 }; 2411 2412 enum { 2413 MLX5_MKC_ACCESS_MODE_PA = 0x0, 2414 MLX5_MKC_ACCESS_MODE_MTT = 0x1, 2415 MLX5_MKC_ACCESS_MODE_KLMS = 0x2, 2416 }; 2417 2418 struct mlx5_ifc_mkc_bits { 2419 u8 reserved_at_0[0x1]; 2420 u8 free[0x1]; 2421 u8 reserved_at_2[0xd]; 2422 u8 small_fence_on_rdma_read_response[0x1]; 2423 u8 umr_en[0x1]; 2424 u8 a[0x1]; 2425 u8 rw[0x1]; 2426 u8 rr[0x1]; 2427 u8 lw[0x1]; 2428 u8 lr[0x1]; 2429 u8 access_mode[0x2]; 2430 u8 reserved_at_18[0x8]; 2431 2432 u8 qpn[0x18]; 2433 u8 mkey_7_0[0x8]; 2434 2435 u8 reserved_at_40[0x20]; 2436 2437 u8 length64[0x1]; 2438 u8 bsf_en[0x1]; 2439 u8 sync_umr[0x1]; 2440 u8 reserved_at_63[0x2]; 2441 u8 expected_sigerr_count[0x1]; 2442 u8 reserved_at_66[0x1]; 2443 u8 en_rinval[0x1]; 2444 u8 pd[0x18]; 2445 2446 u8 start_addr[0x40]; 2447 2448 u8 len[0x40]; 2449 2450 u8 bsf_octword_size[0x20]; 2451 2452 u8 reserved_at_120[0x80]; 2453 2454 u8 translations_octword_size[0x20]; 2455 2456 u8 reserved_at_1c0[0x1b]; 2457 u8 log_page_size[0x5]; 2458 2459 u8 reserved_at_1e0[0x20]; 2460 }; 2461 2462 struct mlx5_ifc_pkey_bits { 2463 u8 reserved_at_0[0x10]; 2464 u8 pkey[0x10]; 2465 }; 2466 2467 struct mlx5_ifc_array128_auto_bits { 2468 u8 array128_auto[16][0x8]; 2469 }; 2470 2471 struct mlx5_ifc_hca_vport_context_bits { 2472 u8 field_select[0x20]; 2473 2474 u8 reserved_at_20[0xe0]; 2475 2476 u8 sm_virt_aware[0x1]; 2477 u8 has_smi[0x1]; 2478 u8 has_raw[0x1]; 2479 u8 grh_required[0x1]; 2480 u8 reserved_at_104[0xc]; 2481 u8 port_physical_state[0x4]; 2482 u8 vport_state_policy[0x4]; 2483 u8 port_state[0x4]; 2484 u8 vport_state[0x4]; 2485 2486 u8 reserved_at_120[0x20]; 2487 2488 u8 system_image_guid[0x40]; 2489 2490 u8 port_guid[0x40]; 2491 2492 u8 node_guid[0x40]; 2493 2494 u8 cap_mask1[0x20]; 2495 2496 u8 cap_mask1_field_select[0x20]; 2497 2498 u8 cap_mask2[0x20]; 2499 2500 u8 cap_mask2_field_select[0x20]; 2501 2502 u8 reserved_at_280[0x80]; 2503 2504 u8 lid[0x10]; 2505 u8 reserved_at_310[0x4]; 2506 u8 init_type_reply[0x4]; 2507 u8 lmc[0x3]; 2508 u8 subnet_timeout[0x5]; 2509 2510 u8 sm_lid[0x10]; 2511 u8 sm_sl[0x4]; 2512 u8 reserved_at_334[0xc]; 2513 2514 u8 qkey_violation_counter[0x10]; 2515 u8 pkey_violation_counter[0x10]; 2516 2517 u8 reserved_at_360[0xca0]; 2518 }; 2519 2520 struct mlx5_ifc_esw_vport_context_bits { 2521 u8 reserved_at_0[0x3]; 2522 u8 vport_svlan_strip[0x1]; 2523 u8 vport_cvlan_strip[0x1]; 2524 u8 vport_svlan_insert[0x1]; 2525 u8 vport_cvlan_insert[0x2]; 2526 u8 reserved_at_8[0x18]; 2527 2528 u8 reserved_at_20[0x20]; 2529 2530 u8 svlan_cfi[0x1]; 2531 u8 svlan_pcp[0x3]; 2532 u8 svlan_id[0xc]; 2533 u8 cvlan_cfi[0x1]; 2534 u8 cvlan_pcp[0x3]; 2535 u8 cvlan_id[0xc]; 2536 2537 u8 reserved_at_60[0x7a0]; 2538 }; 2539 2540 enum { 2541 MLX5_EQC_STATUS_OK = 0x0, 2542 MLX5_EQC_STATUS_EQ_WRITE_FAILURE = 0xa, 2543 }; 2544 2545 enum { 2546 MLX5_EQC_ST_ARMED = 0x9, 2547 MLX5_EQC_ST_FIRED = 0xa, 2548 }; 2549 2550 struct mlx5_ifc_eqc_bits { 2551 u8 status[0x4]; 2552 u8 reserved_at_4[0x9]; 2553 u8 ec[0x1]; 2554 u8 oi[0x1]; 2555 u8 reserved_at_f[0x5]; 2556 u8 st[0x4]; 2557 u8 reserved_at_18[0x8]; 2558 2559 u8 reserved_at_20[0x20]; 2560 2561 u8 reserved_at_40[0x14]; 2562 u8 page_offset[0x6]; 2563 u8 reserved_at_5a[0x6]; 2564 2565 u8 reserved_at_60[0x3]; 2566 u8 log_eq_size[0x5]; 2567 u8 uar_page[0x18]; 2568 2569 u8 reserved_at_80[0x20]; 2570 2571 u8 reserved_at_a0[0x18]; 2572 u8 intr[0x8]; 2573 2574 u8 reserved_at_c0[0x3]; 2575 u8 log_page_size[0x5]; 2576 u8 reserved_at_c8[0x18]; 2577 2578 u8 reserved_at_e0[0x60]; 2579 2580 u8 reserved_at_140[0x8]; 2581 u8 consumer_counter[0x18]; 2582 2583 u8 reserved_at_160[0x8]; 2584 u8 producer_counter[0x18]; 2585 2586 u8 reserved_at_180[0x80]; 2587 }; 2588 2589 enum { 2590 MLX5_DCTC_STATE_ACTIVE = 0x0, 2591 MLX5_DCTC_STATE_DRAINING = 0x1, 2592 MLX5_DCTC_STATE_DRAINED = 0x2, 2593 }; 2594 2595 enum { 2596 MLX5_DCTC_CS_RES_DISABLE = 0x0, 2597 MLX5_DCTC_CS_RES_NA = 0x1, 2598 MLX5_DCTC_CS_RES_UP_TO_64B = 0x2, 2599 }; 2600 2601 enum { 2602 MLX5_DCTC_MTU_256_BYTES = 0x1, 2603 MLX5_DCTC_MTU_512_BYTES = 0x2, 2604 MLX5_DCTC_MTU_1K_BYTES = 0x3, 2605 MLX5_DCTC_MTU_2K_BYTES = 0x4, 2606 MLX5_DCTC_MTU_4K_BYTES = 0x5, 2607 }; 2608 2609 struct mlx5_ifc_dctc_bits { 2610 u8 reserved_at_0[0x4]; 2611 u8 state[0x4]; 2612 u8 reserved_at_8[0x18]; 2613 2614 u8 reserved_at_20[0x8]; 2615 u8 user_index[0x18]; 2616 2617 u8 reserved_at_40[0x8]; 2618 u8 cqn[0x18]; 2619 2620 u8 counter_set_id[0x8]; 2621 u8 atomic_mode[0x4]; 2622 u8 rre[0x1]; 2623 u8 rwe[0x1]; 2624 u8 rae[0x1]; 2625 u8 atomic_like_write_en[0x1]; 2626 u8 latency_sensitive[0x1]; 2627 u8 rlky[0x1]; 2628 u8 free_ar[0x1]; 2629 u8 reserved_at_73[0xd]; 2630 2631 u8 reserved_at_80[0x8]; 2632 u8 cs_res[0x8]; 2633 u8 reserved_at_90[0x3]; 2634 u8 min_rnr_nak[0x5]; 2635 u8 reserved_at_98[0x8]; 2636 2637 u8 reserved_at_a0[0x8]; 2638 u8 srqn_xrqn[0x18]; 2639 2640 u8 reserved_at_c0[0x8]; 2641 u8 pd[0x18]; 2642 2643 u8 tclass[0x8]; 2644 u8 reserved_at_e8[0x4]; 2645 u8 flow_label[0x14]; 2646 2647 u8 dc_access_key[0x40]; 2648 2649 u8 reserved_at_140[0x5]; 2650 u8 mtu[0x3]; 2651 u8 port[0x8]; 2652 u8 pkey_index[0x10]; 2653 2654 u8 reserved_at_160[0x8]; 2655 u8 my_addr_index[0x8]; 2656 u8 reserved_at_170[0x8]; 2657 u8 hop_limit[0x8]; 2658 2659 u8 dc_access_key_violation_count[0x20]; 2660 2661 u8 reserved_at_1a0[0x14]; 2662 u8 dei_cfi[0x1]; 2663 u8 eth_prio[0x3]; 2664 u8 ecn[0x2]; 2665 u8 dscp[0x6]; 2666 2667 u8 reserved_at_1c0[0x40]; 2668 }; 2669 2670 enum { 2671 MLX5_CQC_STATUS_OK = 0x0, 2672 MLX5_CQC_STATUS_CQ_OVERFLOW = 0x9, 2673 MLX5_CQC_STATUS_CQ_WRITE_FAIL = 0xa, 2674 }; 2675 2676 enum { 2677 MLX5_CQC_CQE_SZ_64_BYTES = 0x0, 2678 MLX5_CQC_CQE_SZ_128_BYTES = 0x1, 2679 }; 2680 2681 enum { 2682 MLX5_CQC_ST_SOLICITED_NOTIFICATION_REQUEST_ARMED = 0x6, 2683 MLX5_CQC_ST_NOTIFICATION_REQUEST_ARMED = 0x9, 2684 MLX5_CQC_ST_FIRED = 0xa, 2685 }; 2686 2687 enum { 2688 MLX5_CQ_PERIOD_MODE_START_FROM_EQE = 0x0, 2689 MLX5_CQ_PERIOD_MODE_START_FROM_CQE = 0x1, 2690 MLX5_CQ_PERIOD_NUM_MODES 2691 }; 2692 2693 struct mlx5_ifc_cqc_bits { 2694 u8 status[0x4]; 2695 u8 reserved_at_4[0x4]; 2696 u8 cqe_sz[0x3]; 2697 u8 cc[0x1]; 2698 u8 reserved_at_c[0x1]; 2699 u8 scqe_break_moderation_en[0x1]; 2700 u8 oi[0x1]; 2701 u8 cq_period_mode[0x2]; 2702 u8 cqe_comp_en[0x1]; 2703 u8 mini_cqe_res_format[0x2]; 2704 u8 st[0x4]; 2705 u8 reserved_at_18[0x8]; 2706 2707 u8 reserved_at_20[0x20]; 2708 2709 u8 reserved_at_40[0x14]; 2710 u8 page_offset[0x6]; 2711 u8 reserved_at_5a[0x6]; 2712 2713 u8 reserved_at_60[0x3]; 2714 u8 log_cq_size[0x5]; 2715 u8 uar_page[0x18]; 2716 2717 u8 reserved_at_80[0x4]; 2718 u8 cq_period[0xc]; 2719 u8 cq_max_count[0x10]; 2720 2721 u8 reserved_at_a0[0x18]; 2722 u8 c_eqn[0x8]; 2723 2724 u8 reserved_at_c0[0x3]; 2725 u8 log_page_size[0x5]; 2726 u8 reserved_at_c8[0x18]; 2727 2728 u8 reserved_at_e0[0x20]; 2729 2730 u8 reserved_at_100[0x8]; 2731 u8 last_notified_index[0x18]; 2732 2733 u8 reserved_at_120[0x8]; 2734 u8 last_solicit_index[0x18]; 2735 2736 u8 reserved_at_140[0x8]; 2737 u8 consumer_counter[0x18]; 2738 2739 u8 reserved_at_160[0x8]; 2740 u8 producer_counter[0x18]; 2741 2742 u8 reserved_at_180[0x40]; 2743 2744 u8 dbr_addr[0x40]; 2745 }; 2746 2747 union mlx5_ifc_cong_control_roce_ecn_auto_bits { 2748 struct mlx5_ifc_cong_control_802_1qau_rp_bits cong_control_802_1qau_rp; 2749 struct mlx5_ifc_cong_control_r_roce_ecn_rp_bits cong_control_r_roce_ecn_rp; 2750 struct mlx5_ifc_cong_control_r_roce_ecn_np_bits cong_control_r_roce_ecn_np; 2751 u8 reserved_at_0[0x800]; 2752 }; 2753 2754 struct mlx5_ifc_query_adapter_param_block_bits { 2755 u8 reserved_at_0[0xc0]; 2756 2757 u8 reserved_at_c0[0x8]; 2758 u8 ieee_vendor_id[0x18]; 2759 2760 u8 reserved_at_e0[0x10]; 2761 u8 vsd_vendor_id[0x10]; 2762 2763 u8 vsd[208][0x8]; 2764 2765 u8 vsd_contd_psid[16][0x8]; 2766 }; 2767 2768 enum { 2769 MLX5_XRQC_STATE_GOOD = 0x0, 2770 MLX5_XRQC_STATE_ERROR = 0x1, 2771 }; 2772 2773 enum { 2774 MLX5_XRQC_TOPOLOGY_NO_SPECIAL_TOPOLOGY = 0x0, 2775 MLX5_XRQC_TOPOLOGY_TAG_MATCHING = 0x1, 2776 }; 2777 2778 enum { 2779 MLX5_XRQC_OFFLOAD_RNDV = 0x1, 2780 }; 2781 2782 struct mlx5_ifc_tag_matching_topology_context_bits { 2783 u8 log_matching_list_sz[0x4]; 2784 u8 reserved_at_4[0xc]; 2785 u8 append_next_index[0x10]; 2786 2787 u8 sw_phase_cnt[0x10]; 2788 u8 hw_phase_cnt[0x10]; 2789 2790 u8 reserved_at_40[0x40]; 2791 }; 2792 2793 struct mlx5_ifc_xrqc_bits { 2794 u8 state[0x4]; 2795 u8 rlkey[0x1]; 2796 u8 reserved_at_5[0xf]; 2797 u8 topology[0x4]; 2798 u8 reserved_at_18[0x4]; 2799 u8 offload[0x4]; 2800 2801 u8 reserved_at_20[0x8]; 2802 u8 user_index[0x18]; 2803 2804 u8 reserved_at_40[0x8]; 2805 u8 cqn[0x18]; 2806 2807 u8 reserved_at_60[0xa0]; 2808 2809 struct mlx5_ifc_tag_matching_topology_context_bits tag_matching_topology_context; 2810 2811 u8 reserved_at_180[0x180]; 2812 2813 struct mlx5_ifc_wq_bits wq; 2814 }; 2815 2816 union mlx5_ifc_modify_field_select_resize_field_select_auto_bits { 2817 struct mlx5_ifc_modify_field_select_bits modify_field_select; 2818 struct mlx5_ifc_resize_field_select_bits resize_field_select; 2819 u8 reserved_at_0[0x20]; 2820 }; 2821 2822 union mlx5_ifc_field_select_802_1_r_roce_auto_bits { 2823 struct mlx5_ifc_field_select_802_1qau_rp_bits field_select_802_1qau_rp; 2824 struct mlx5_ifc_field_select_r_roce_rp_bits field_select_r_roce_rp; 2825 struct mlx5_ifc_field_select_r_roce_np_bits field_select_r_roce_np; 2826 u8 reserved_at_0[0x20]; 2827 }; 2828 2829 union mlx5_ifc_eth_cntrs_grp_data_layout_auto_bits { 2830 struct mlx5_ifc_eth_802_3_cntrs_grp_data_layout_bits eth_802_3_cntrs_grp_data_layout; 2831 struct mlx5_ifc_eth_2863_cntrs_grp_data_layout_bits eth_2863_cntrs_grp_data_layout; 2832 struct mlx5_ifc_eth_2819_cntrs_grp_data_layout_bits eth_2819_cntrs_grp_data_layout; 2833 struct mlx5_ifc_eth_3635_cntrs_grp_data_layout_bits eth_3635_cntrs_grp_data_layout; 2834 struct mlx5_ifc_eth_extended_cntrs_grp_data_layout_bits eth_extended_cntrs_grp_data_layout; 2835 struct mlx5_ifc_eth_per_prio_grp_data_layout_bits eth_per_prio_grp_data_layout; 2836 struct mlx5_ifc_eth_per_traffic_grp_data_layout_bits eth_per_traffic_grp_data_layout; 2837 struct mlx5_ifc_ib_port_cntrs_grp_data_layout_bits ib_port_cntrs_grp_data_layout; 2838 struct mlx5_ifc_phys_layer_cntrs_bits phys_layer_cntrs; 2839 u8 reserved_at_0[0x7c0]; 2840 }; 2841 2842 union mlx5_ifc_event_auto_bits { 2843 struct mlx5_ifc_comp_event_bits comp_event; 2844 struct mlx5_ifc_dct_events_bits dct_events; 2845 struct mlx5_ifc_qp_events_bits qp_events; 2846 struct mlx5_ifc_wqe_associated_page_fault_event_bits wqe_associated_page_fault_event; 2847 struct mlx5_ifc_rdma_page_fault_event_bits rdma_page_fault_event; 2848 struct mlx5_ifc_cq_error_bits cq_error; 2849 struct mlx5_ifc_dropped_packet_logged_bits dropped_packet_logged; 2850 struct mlx5_ifc_port_state_change_event_bits port_state_change_event; 2851 struct mlx5_ifc_gpio_event_bits gpio_event; 2852 struct mlx5_ifc_db_bf_congestion_event_bits db_bf_congestion_event; 2853 struct mlx5_ifc_stall_vl_event_bits stall_vl_event; 2854 struct mlx5_ifc_cmd_inter_comp_event_bits cmd_inter_comp_event; 2855 u8 reserved_at_0[0xe0]; 2856 }; 2857 2858 struct mlx5_ifc_health_buffer_bits { 2859 u8 reserved_at_0[0x100]; 2860 2861 u8 assert_existptr[0x20]; 2862 2863 u8 assert_callra[0x20]; 2864 2865 u8 reserved_at_140[0x40]; 2866 2867 u8 fw_version[0x20]; 2868 2869 u8 hw_id[0x20]; 2870 2871 u8 reserved_at_1c0[0x20]; 2872 2873 u8 irisc_index[0x8]; 2874 u8 synd[0x8]; 2875 u8 ext_synd[0x10]; 2876 }; 2877 2878 struct mlx5_ifc_register_loopback_control_bits { 2879 u8 no_lb[0x1]; 2880 u8 reserved_at_1[0x7]; 2881 u8 port[0x8]; 2882 u8 reserved_at_10[0x10]; 2883 2884 u8 reserved_at_20[0x60]; 2885 }; 2886 2887 struct mlx5_ifc_teardown_hca_out_bits { 2888 u8 status[0x8]; 2889 u8 reserved_at_8[0x18]; 2890 2891 u8 syndrome[0x20]; 2892 2893 u8 reserved_at_40[0x40]; 2894 }; 2895 2896 enum { 2897 MLX5_TEARDOWN_HCA_IN_PROFILE_GRACEFUL_CLOSE = 0x0, 2898 MLX5_TEARDOWN_HCA_IN_PROFILE_PANIC_CLOSE = 0x1, 2899 }; 2900 2901 struct mlx5_ifc_teardown_hca_in_bits { 2902 u8 opcode[0x10]; 2903 u8 reserved_at_10[0x10]; 2904 2905 u8 reserved_at_20[0x10]; 2906 u8 op_mod[0x10]; 2907 2908 u8 reserved_at_40[0x10]; 2909 u8 profile[0x10]; 2910 2911 u8 reserved_at_60[0x20]; 2912 }; 2913 2914 struct mlx5_ifc_sqerr2rts_qp_out_bits { 2915 u8 status[0x8]; 2916 u8 reserved_at_8[0x18]; 2917 2918 u8 syndrome[0x20]; 2919 2920 u8 reserved_at_40[0x40]; 2921 }; 2922 2923 struct mlx5_ifc_sqerr2rts_qp_in_bits { 2924 u8 opcode[0x10]; 2925 u8 reserved_at_10[0x10]; 2926 2927 u8 reserved_at_20[0x10]; 2928 u8 op_mod[0x10]; 2929 2930 u8 reserved_at_40[0x8]; 2931 u8 qpn[0x18]; 2932 2933 u8 reserved_at_60[0x20]; 2934 2935 u8 opt_param_mask[0x20]; 2936 2937 u8 reserved_at_a0[0x20]; 2938 2939 struct mlx5_ifc_qpc_bits qpc; 2940 2941 u8 reserved_at_800[0x80]; 2942 }; 2943 2944 struct mlx5_ifc_sqd2rts_qp_out_bits { 2945 u8 status[0x8]; 2946 u8 reserved_at_8[0x18]; 2947 2948 u8 syndrome[0x20]; 2949 2950 u8 reserved_at_40[0x40]; 2951 }; 2952 2953 struct mlx5_ifc_sqd2rts_qp_in_bits { 2954 u8 opcode[0x10]; 2955 u8 reserved_at_10[0x10]; 2956 2957 u8 reserved_at_20[0x10]; 2958 u8 op_mod[0x10]; 2959 2960 u8 reserved_at_40[0x8]; 2961 u8 qpn[0x18]; 2962 2963 u8 reserved_at_60[0x20]; 2964 2965 u8 opt_param_mask[0x20]; 2966 2967 u8 reserved_at_a0[0x20]; 2968 2969 struct mlx5_ifc_qpc_bits qpc; 2970 2971 u8 reserved_at_800[0x80]; 2972 }; 2973 2974 struct mlx5_ifc_set_roce_address_out_bits { 2975 u8 status[0x8]; 2976 u8 reserved_at_8[0x18]; 2977 2978 u8 syndrome[0x20]; 2979 2980 u8 reserved_at_40[0x40]; 2981 }; 2982 2983 struct mlx5_ifc_set_roce_address_in_bits { 2984 u8 opcode[0x10]; 2985 u8 reserved_at_10[0x10]; 2986 2987 u8 reserved_at_20[0x10]; 2988 u8 op_mod[0x10]; 2989 2990 u8 roce_address_index[0x10]; 2991 u8 reserved_at_50[0x10]; 2992 2993 u8 reserved_at_60[0x20]; 2994 2995 struct mlx5_ifc_roce_addr_layout_bits roce_address; 2996 }; 2997 2998 struct mlx5_ifc_set_mad_demux_out_bits { 2999 u8 status[0x8]; 3000 u8 reserved_at_8[0x18]; 3001 3002 u8 syndrome[0x20]; 3003 3004 u8 reserved_at_40[0x40]; 3005 }; 3006 3007 enum { 3008 MLX5_SET_MAD_DEMUX_IN_DEMUX_MODE_PASS_ALL = 0x0, 3009 MLX5_SET_MAD_DEMUX_IN_DEMUX_MODE_SELECTIVE = 0x2, 3010 }; 3011 3012 struct mlx5_ifc_set_mad_demux_in_bits { 3013 u8 opcode[0x10]; 3014 u8 reserved_at_10[0x10]; 3015 3016 u8 reserved_at_20[0x10]; 3017 u8 op_mod[0x10]; 3018 3019 u8 reserved_at_40[0x20]; 3020 3021 u8 reserved_at_60[0x6]; 3022 u8 demux_mode[0x2]; 3023 u8 reserved_at_68[0x18]; 3024 }; 3025 3026 struct mlx5_ifc_set_l2_table_entry_out_bits { 3027 u8 status[0x8]; 3028 u8 reserved_at_8[0x18]; 3029 3030 u8 syndrome[0x20]; 3031 3032 u8 reserved_at_40[0x40]; 3033 }; 3034 3035 struct mlx5_ifc_set_l2_table_entry_in_bits { 3036 u8 opcode[0x10]; 3037 u8 reserved_at_10[0x10]; 3038 3039 u8 reserved_at_20[0x10]; 3040 u8 op_mod[0x10]; 3041 3042 u8 reserved_at_40[0x60]; 3043 3044 u8 reserved_at_a0[0x8]; 3045 u8 table_index[0x18]; 3046 3047 u8 reserved_at_c0[0x20]; 3048 3049 u8 reserved_at_e0[0x13]; 3050 u8 vlan_valid[0x1]; 3051 u8 vlan[0xc]; 3052 3053 struct mlx5_ifc_mac_address_layout_bits mac_address; 3054 3055 u8 reserved_at_140[0xc0]; 3056 }; 3057 3058 struct mlx5_ifc_set_issi_out_bits { 3059 u8 status[0x8]; 3060 u8 reserved_at_8[0x18]; 3061 3062 u8 syndrome[0x20]; 3063 3064 u8 reserved_at_40[0x40]; 3065 }; 3066 3067 struct mlx5_ifc_set_issi_in_bits { 3068 u8 opcode[0x10]; 3069 u8 reserved_at_10[0x10]; 3070 3071 u8 reserved_at_20[0x10]; 3072 u8 op_mod[0x10]; 3073 3074 u8 reserved_at_40[0x10]; 3075 u8 current_issi[0x10]; 3076 3077 u8 reserved_at_60[0x20]; 3078 }; 3079 3080 struct mlx5_ifc_set_hca_cap_out_bits { 3081 u8 status[0x8]; 3082 u8 reserved_at_8[0x18]; 3083 3084 u8 syndrome[0x20]; 3085 3086 u8 reserved_at_40[0x40]; 3087 }; 3088 3089 struct mlx5_ifc_set_hca_cap_in_bits { 3090 u8 opcode[0x10]; 3091 u8 reserved_at_10[0x10]; 3092 3093 u8 reserved_at_20[0x10]; 3094 u8 op_mod[0x10]; 3095 3096 u8 reserved_at_40[0x40]; 3097 3098 union mlx5_ifc_hca_cap_union_bits capability; 3099 }; 3100 3101 enum { 3102 MLX5_SET_FTE_MODIFY_ENABLE_MASK_ACTION = 0x0, 3103 MLX5_SET_FTE_MODIFY_ENABLE_MASK_FLOW_TAG = 0x1, 3104 MLX5_SET_FTE_MODIFY_ENABLE_MASK_DESTINATION_LIST = 0x2, 3105 MLX5_SET_FTE_MODIFY_ENABLE_MASK_FLOW_COUNTERS = 0x3 3106 }; 3107 3108 struct mlx5_ifc_set_fte_out_bits { 3109 u8 status[0x8]; 3110 u8 reserved_at_8[0x18]; 3111 3112 u8 syndrome[0x20]; 3113 3114 u8 reserved_at_40[0x40]; 3115 }; 3116 3117 struct mlx5_ifc_set_fte_in_bits { 3118 u8 opcode[0x10]; 3119 u8 reserved_at_10[0x10]; 3120 3121 u8 reserved_at_20[0x10]; 3122 u8 op_mod[0x10]; 3123 3124 u8 other_vport[0x1]; 3125 u8 reserved_at_41[0xf]; 3126 u8 vport_number[0x10]; 3127 3128 u8 reserved_at_60[0x20]; 3129 3130 u8 table_type[0x8]; 3131 u8 reserved_at_88[0x18]; 3132 3133 u8 reserved_at_a0[0x8]; 3134 u8 table_id[0x18]; 3135 3136 u8 reserved_at_c0[0x18]; 3137 u8 modify_enable_mask[0x8]; 3138 3139 u8 reserved_at_e0[0x20]; 3140 3141 u8 flow_index[0x20]; 3142 3143 u8 reserved_at_120[0xe0]; 3144 3145 struct mlx5_ifc_flow_context_bits flow_context; 3146 }; 3147 3148 struct mlx5_ifc_rts2rts_qp_out_bits { 3149 u8 status[0x8]; 3150 u8 reserved_at_8[0x18]; 3151 3152 u8 syndrome[0x20]; 3153 3154 u8 reserved_at_40[0x40]; 3155 }; 3156 3157 struct mlx5_ifc_rts2rts_qp_in_bits { 3158 u8 opcode[0x10]; 3159 u8 reserved_at_10[0x10]; 3160 3161 u8 reserved_at_20[0x10]; 3162 u8 op_mod[0x10]; 3163 3164 u8 reserved_at_40[0x8]; 3165 u8 qpn[0x18]; 3166 3167 u8 reserved_at_60[0x20]; 3168 3169 u8 opt_param_mask[0x20]; 3170 3171 u8 reserved_at_a0[0x20]; 3172 3173 struct mlx5_ifc_qpc_bits qpc; 3174 3175 u8 reserved_at_800[0x80]; 3176 }; 3177 3178 struct mlx5_ifc_rtr2rts_qp_out_bits { 3179 u8 status[0x8]; 3180 u8 reserved_at_8[0x18]; 3181 3182 u8 syndrome[0x20]; 3183 3184 u8 reserved_at_40[0x40]; 3185 }; 3186 3187 struct mlx5_ifc_rtr2rts_qp_in_bits { 3188 u8 opcode[0x10]; 3189 u8 reserved_at_10[0x10]; 3190 3191 u8 reserved_at_20[0x10]; 3192 u8 op_mod[0x10]; 3193 3194 u8 reserved_at_40[0x8]; 3195 u8 qpn[0x18]; 3196 3197 u8 reserved_at_60[0x20]; 3198 3199 u8 opt_param_mask[0x20]; 3200 3201 u8 reserved_at_a0[0x20]; 3202 3203 struct mlx5_ifc_qpc_bits qpc; 3204 3205 u8 reserved_at_800[0x80]; 3206 }; 3207 3208 struct mlx5_ifc_rst2init_qp_out_bits { 3209 u8 status[0x8]; 3210 u8 reserved_at_8[0x18]; 3211 3212 u8 syndrome[0x20]; 3213 3214 u8 reserved_at_40[0x40]; 3215 }; 3216 3217 struct mlx5_ifc_rst2init_qp_in_bits { 3218 u8 opcode[0x10]; 3219 u8 reserved_at_10[0x10]; 3220 3221 u8 reserved_at_20[0x10]; 3222 u8 op_mod[0x10]; 3223 3224 u8 reserved_at_40[0x8]; 3225 u8 qpn[0x18]; 3226 3227 u8 reserved_at_60[0x20]; 3228 3229 u8 opt_param_mask[0x20]; 3230 3231 u8 reserved_at_a0[0x20]; 3232 3233 struct mlx5_ifc_qpc_bits qpc; 3234 3235 u8 reserved_at_800[0x80]; 3236 }; 3237 3238 struct mlx5_ifc_query_xrq_out_bits { 3239 u8 status[0x8]; 3240 u8 reserved_at_8[0x18]; 3241 3242 u8 syndrome[0x20]; 3243 3244 u8 reserved_at_40[0x40]; 3245 3246 struct mlx5_ifc_xrqc_bits xrq_context; 3247 }; 3248 3249 struct mlx5_ifc_query_xrq_in_bits { 3250 u8 opcode[0x10]; 3251 u8 reserved_at_10[0x10]; 3252 3253 u8 reserved_at_20[0x10]; 3254 u8 op_mod[0x10]; 3255 3256 u8 reserved_at_40[0x8]; 3257 u8 xrqn[0x18]; 3258 3259 u8 reserved_at_60[0x20]; 3260 }; 3261 3262 struct mlx5_ifc_query_xrc_srq_out_bits { 3263 u8 status[0x8]; 3264 u8 reserved_at_8[0x18]; 3265 3266 u8 syndrome[0x20]; 3267 3268 u8 reserved_at_40[0x40]; 3269 3270 struct mlx5_ifc_xrc_srqc_bits xrc_srq_context_entry; 3271 3272 u8 reserved_at_280[0x600]; 3273 3274 u8 pas[0][0x40]; 3275 }; 3276 3277 struct mlx5_ifc_query_xrc_srq_in_bits { 3278 u8 opcode[0x10]; 3279 u8 reserved_at_10[0x10]; 3280 3281 u8 reserved_at_20[0x10]; 3282 u8 op_mod[0x10]; 3283 3284 u8 reserved_at_40[0x8]; 3285 u8 xrc_srqn[0x18]; 3286 3287 u8 reserved_at_60[0x20]; 3288 }; 3289 3290 enum { 3291 MLX5_QUERY_VPORT_STATE_OUT_STATE_DOWN = 0x0, 3292 MLX5_QUERY_VPORT_STATE_OUT_STATE_UP = 0x1, 3293 }; 3294 3295 struct mlx5_ifc_query_vport_state_out_bits { 3296 u8 status[0x8]; 3297 u8 reserved_at_8[0x18]; 3298 3299 u8 syndrome[0x20]; 3300 3301 u8 reserved_at_40[0x20]; 3302 3303 u8 reserved_at_60[0x18]; 3304 u8 admin_state[0x4]; 3305 u8 state[0x4]; 3306 }; 3307 3308 enum { 3309 MLX5_QUERY_VPORT_STATE_IN_OP_MOD_VNIC_VPORT = 0x0, 3310 MLX5_QUERY_VPORT_STATE_IN_OP_MOD_ESW_VPORT = 0x1, 3311 }; 3312 3313 struct mlx5_ifc_query_vport_state_in_bits { 3314 u8 opcode[0x10]; 3315 u8 reserved_at_10[0x10]; 3316 3317 u8 reserved_at_20[0x10]; 3318 u8 op_mod[0x10]; 3319 3320 u8 other_vport[0x1]; 3321 u8 reserved_at_41[0xf]; 3322 u8 vport_number[0x10]; 3323 3324 u8 reserved_at_60[0x20]; 3325 }; 3326 3327 struct mlx5_ifc_query_vport_counter_out_bits { 3328 u8 status[0x8]; 3329 u8 reserved_at_8[0x18]; 3330 3331 u8 syndrome[0x20]; 3332 3333 u8 reserved_at_40[0x40]; 3334 3335 struct mlx5_ifc_traffic_counter_bits received_errors; 3336 3337 struct mlx5_ifc_traffic_counter_bits transmit_errors; 3338 3339 struct mlx5_ifc_traffic_counter_bits received_ib_unicast; 3340 3341 struct mlx5_ifc_traffic_counter_bits transmitted_ib_unicast; 3342 3343 struct mlx5_ifc_traffic_counter_bits received_ib_multicast; 3344 3345 struct mlx5_ifc_traffic_counter_bits transmitted_ib_multicast; 3346 3347 struct mlx5_ifc_traffic_counter_bits received_eth_broadcast; 3348 3349 struct mlx5_ifc_traffic_counter_bits transmitted_eth_broadcast; 3350 3351 struct mlx5_ifc_traffic_counter_bits received_eth_unicast; 3352 3353 struct mlx5_ifc_traffic_counter_bits transmitted_eth_unicast; 3354 3355 struct mlx5_ifc_traffic_counter_bits received_eth_multicast; 3356 3357 struct mlx5_ifc_traffic_counter_bits transmitted_eth_multicast; 3358 3359 u8 reserved_at_680[0xa00]; 3360 }; 3361 3362 enum { 3363 MLX5_QUERY_VPORT_COUNTER_IN_OP_MOD_VPORT_COUNTERS = 0x0, 3364 }; 3365 3366 struct mlx5_ifc_query_vport_counter_in_bits { 3367 u8 opcode[0x10]; 3368 u8 reserved_at_10[0x10]; 3369 3370 u8 reserved_at_20[0x10]; 3371 u8 op_mod[0x10]; 3372 3373 u8 other_vport[0x1]; 3374 u8 reserved_at_41[0xb]; 3375 u8 port_num[0x4]; 3376 u8 vport_number[0x10]; 3377 3378 u8 reserved_at_60[0x60]; 3379 3380 u8 clear[0x1]; 3381 u8 reserved_at_c1[0x1f]; 3382 3383 u8 reserved_at_e0[0x20]; 3384 }; 3385 3386 struct mlx5_ifc_query_tis_out_bits { 3387 u8 status[0x8]; 3388 u8 reserved_at_8[0x18]; 3389 3390 u8 syndrome[0x20]; 3391 3392 u8 reserved_at_40[0x40]; 3393 3394 struct mlx5_ifc_tisc_bits tis_context; 3395 }; 3396 3397 struct mlx5_ifc_query_tis_in_bits { 3398 u8 opcode[0x10]; 3399 u8 reserved_at_10[0x10]; 3400 3401 u8 reserved_at_20[0x10]; 3402 u8 op_mod[0x10]; 3403 3404 u8 reserved_at_40[0x8]; 3405 u8 tisn[0x18]; 3406 3407 u8 reserved_at_60[0x20]; 3408 }; 3409 3410 struct mlx5_ifc_query_tir_out_bits { 3411 u8 status[0x8]; 3412 u8 reserved_at_8[0x18]; 3413 3414 u8 syndrome[0x20]; 3415 3416 u8 reserved_at_40[0xc0]; 3417 3418 struct mlx5_ifc_tirc_bits tir_context; 3419 }; 3420 3421 struct mlx5_ifc_query_tir_in_bits { 3422 u8 opcode[0x10]; 3423 u8 reserved_at_10[0x10]; 3424 3425 u8 reserved_at_20[0x10]; 3426 u8 op_mod[0x10]; 3427 3428 u8 reserved_at_40[0x8]; 3429 u8 tirn[0x18]; 3430 3431 u8 reserved_at_60[0x20]; 3432 }; 3433 3434 struct mlx5_ifc_query_srq_out_bits { 3435 u8 status[0x8]; 3436 u8 reserved_at_8[0x18]; 3437 3438 u8 syndrome[0x20]; 3439 3440 u8 reserved_at_40[0x40]; 3441 3442 struct mlx5_ifc_srqc_bits srq_context_entry; 3443 3444 u8 reserved_at_280[0x600]; 3445 3446 u8 pas[0][0x40]; 3447 }; 3448 3449 struct mlx5_ifc_query_srq_in_bits { 3450 u8 opcode[0x10]; 3451 u8 reserved_at_10[0x10]; 3452 3453 u8 reserved_at_20[0x10]; 3454 u8 op_mod[0x10]; 3455 3456 u8 reserved_at_40[0x8]; 3457 u8 srqn[0x18]; 3458 3459 u8 reserved_at_60[0x20]; 3460 }; 3461 3462 struct mlx5_ifc_query_sq_out_bits { 3463 u8 status[0x8]; 3464 u8 reserved_at_8[0x18]; 3465 3466 u8 syndrome[0x20]; 3467 3468 u8 reserved_at_40[0xc0]; 3469 3470 struct mlx5_ifc_sqc_bits sq_context; 3471 }; 3472 3473 struct mlx5_ifc_query_sq_in_bits { 3474 u8 opcode[0x10]; 3475 u8 reserved_at_10[0x10]; 3476 3477 u8 reserved_at_20[0x10]; 3478 u8 op_mod[0x10]; 3479 3480 u8 reserved_at_40[0x8]; 3481 u8 sqn[0x18]; 3482 3483 u8 reserved_at_60[0x20]; 3484 }; 3485 3486 struct mlx5_ifc_query_special_contexts_out_bits { 3487 u8 status[0x8]; 3488 u8 reserved_at_8[0x18]; 3489 3490 u8 syndrome[0x20]; 3491 3492 u8 reserved_at_40[0x20]; 3493 3494 u8 resd_lkey[0x20]; 3495 }; 3496 3497 struct mlx5_ifc_query_special_contexts_in_bits { 3498 u8 opcode[0x10]; 3499 u8 reserved_at_10[0x10]; 3500 3501 u8 reserved_at_20[0x10]; 3502 u8 op_mod[0x10]; 3503 3504 u8 reserved_at_40[0x40]; 3505 }; 3506 3507 struct mlx5_ifc_query_rqt_out_bits { 3508 u8 status[0x8]; 3509 u8 reserved_at_8[0x18]; 3510 3511 u8 syndrome[0x20]; 3512 3513 u8 reserved_at_40[0xc0]; 3514 3515 struct mlx5_ifc_rqtc_bits rqt_context; 3516 }; 3517 3518 struct mlx5_ifc_query_rqt_in_bits { 3519 u8 opcode[0x10]; 3520 u8 reserved_at_10[0x10]; 3521 3522 u8 reserved_at_20[0x10]; 3523 u8 op_mod[0x10]; 3524 3525 u8 reserved_at_40[0x8]; 3526 u8 rqtn[0x18]; 3527 3528 u8 reserved_at_60[0x20]; 3529 }; 3530 3531 struct mlx5_ifc_query_rq_out_bits { 3532 u8 status[0x8]; 3533 u8 reserved_at_8[0x18]; 3534 3535 u8 syndrome[0x20]; 3536 3537 u8 reserved_at_40[0xc0]; 3538 3539 struct mlx5_ifc_rqc_bits rq_context; 3540 }; 3541 3542 struct mlx5_ifc_query_rq_in_bits { 3543 u8 opcode[0x10]; 3544 u8 reserved_at_10[0x10]; 3545 3546 u8 reserved_at_20[0x10]; 3547 u8 op_mod[0x10]; 3548 3549 u8 reserved_at_40[0x8]; 3550 u8 rqn[0x18]; 3551 3552 u8 reserved_at_60[0x20]; 3553 }; 3554 3555 struct mlx5_ifc_query_roce_address_out_bits { 3556 u8 status[0x8]; 3557 u8 reserved_at_8[0x18]; 3558 3559 u8 syndrome[0x20]; 3560 3561 u8 reserved_at_40[0x40]; 3562 3563 struct mlx5_ifc_roce_addr_layout_bits roce_address; 3564 }; 3565 3566 struct mlx5_ifc_query_roce_address_in_bits { 3567 u8 opcode[0x10]; 3568 u8 reserved_at_10[0x10]; 3569 3570 u8 reserved_at_20[0x10]; 3571 u8 op_mod[0x10]; 3572 3573 u8 roce_address_index[0x10]; 3574 u8 reserved_at_50[0x10]; 3575 3576 u8 reserved_at_60[0x20]; 3577 }; 3578 3579 struct mlx5_ifc_query_rmp_out_bits { 3580 u8 status[0x8]; 3581 u8 reserved_at_8[0x18]; 3582 3583 u8 syndrome[0x20]; 3584 3585 u8 reserved_at_40[0xc0]; 3586 3587 struct mlx5_ifc_rmpc_bits rmp_context; 3588 }; 3589 3590 struct mlx5_ifc_query_rmp_in_bits { 3591 u8 opcode[0x10]; 3592 u8 reserved_at_10[0x10]; 3593 3594 u8 reserved_at_20[0x10]; 3595 u8 op_mod[0x10]; 3596 3597 u8 reserved_at_40[0x8]; 3598 u8 rmpn[0x18]; 3599 3600 u8 reserved_at_60[0x20]; 3601 }; 3602 3603 struct mlx5_ifc_query_qp_out_bits { 3604 u8 status[0x8]; 3605 u8 reserved_at_8[0x18]; 3606 3607 u8 syndrome[0x20]; 3608 3609 u8 reserved_at_40[0x40]; 3610 3611 u8 opt_param_mask[0x20]; 3612 3613 u8 reserved_at_a0[0x20]; 3614 3615 struct mlx5_ifc_qpc_bits qpc; 3616 3617 u8 reserved_at_800[0x80]; 3618 3619 u8 pas[0][0x40]; 3620 }; 3621 3622 struct mlx5_ifc_query_qp_in_bits { 3623 u8 opcode[0x10]; 3624 u8 reserved_at_10[0x10]; 3625 3626 u8 reserved_at_20[0x10]; 3627 u8 op_mod[0x10]; 3628 3629 u8 reserved_at_40[0x8]; 3630 u8 qpn[0x18]; 3631 3632 u8 reserved_at_60[0x20]; 3633 }; 3634 3635 struct mlx5_ifc_query_q_counter_out_bits { 3636 u8 status[0x8]; 3637 u8 reserved_at_8[0x18]; 3638 3639 u8 syndrome[0x20]; 3640 3641 u8 reserved_at_40[0x40]; 3642 3643 u8 rx_write_requests[0x20]; 3644 3645 u8 reserved_at_a0[0x20]; 3646 3647 u8 rx_read_requests[0x20]; 3648 3649 u8 reserved_at_e0[0x20]; 3650 3651 u8 rx_atomic_requests[0x20]; 3652 3653 u8 reserved_at_120[0x20]; 3654 3655 u8 rx_dct_connect[0x20]; 3656 3657 u8 reserved_at_160[0x20]; 3658 3659 u8 out_of_buffer[0x20]; 3660 3661 u8 reserved_at_1a0[0x20]; 3662 3663 u8 out_of_sequence[0x20]; 3664 3665 u8 reserved_at_1e0[0x20]; 3666 3667 u8 duplicate_request[0x20]; 3668 3669 u8 reserved_at_220[0x20]; 3670 3671 u8 rnr_nak_retry_err[0x20]; 3672 3673 u8 reserved_at_260[0x20]; 3674 3675 u8 packet_seq_err[0x20]; 3676 3677 u8 reserved_at_2a0[0x20]; 3678 3679 u8 implied_nak_seq_err[0x20]; 3680 3681 u8 reserved_at_2e0[0x20]; 3682 3683 u8 local_ack_timeout_err[0x20]; 3684 3685 u8 reserved_at_320[0x4e0]; 3686 }; 3687 3688 struct mlx5_ifc_query_q_counter_in_bits { 3689 u8 opcode[0x10]; 3690 u8 reserved_at_10[0x10]; 3691 3692 u8 reserved_at_20[0x10]; 3693 u8 op_mod[0x10]; 3694 3695 u8 reserved_at_40[0x80]; 3696 3697 u8 clear[0x1]; 3698 u8 reserved_at_c1[0x1f]; 3699 3700 u8 reserved_at_e0[0x18]; 3701 u8 counter_set_id[0x8]; 3702 }; 3703 3704 struct mlx5_ifc_query_pages_out_bits { 3705 u8 status[0x8]; 3706 u8 reserved_at_8[0x18]; 3707 3708 u8 syndrome[0x20]; 3709 3710 u8 reserved_at_40[0x10]; 3711 u8 function_id[0x10]; 3712 3713 u8 num_pages[0x20]; 3714 }; 3715 3716 enum { 3717 MLX5_QUERY_PAGES_IN_OP_MOD_BOOT_PAGES = 0x1, 3718 MLX5_QUERY_PAGES_IN_OP_MOD_INIT_PAGES = 0x2, 3719 MLX5_QUERY_PAGES_IN_OP_MOD_REGULAR_PAGES = 0x3, 3720 }; 3721 3722 struct mlx5_ifc_query_pages_in_bits { 3723 u8 opcode[0x10]; 3724 u8 reserved_at_10[0x10]; 3725 3726 u8 reserved_at_20[0x10]; 3727 u8 op_mod[0x10]; 3728 3729 u8 reserved_at_40[0x10]; 3730 u8 function_id[0x10]; 3731 3732 u8 reserved_at_60[0x20]; 3733 }; 3734 3735 struct mlx5_ifc_query_nic_vport_context_out_bits { 3736 u8 status[0x8]; 3737 u8 reserved_at_8[0x18]; 3738 3739 u8 syndrome[0x20]; 3740 3741 u8 reserved_at_40[0x40]; 3742 3743 struct mlx5_ifc_nic_vport_context_bits nic_vport_context; 3744 }; 3745 3746 struct mlx5_ifc_query_nic_vport_context_in_bits { 3747 u8 opcode[0x10]; 3748 u8 reserved_at_10[0x10]; 3749 3750 u8 reserved_at_20[0x10]; 3751 u8 op_mod[0x10]; 3752 3753 u8 other_vport[0x1]; 3754 u8 reserved_at_41[0xf]; 3755 u8 vport_number[0x10]; 3756 3757 u8 reserved_at_60[0x5]; 3758 u8 allowed_list_type[0x3]; 3759 u8 reserved_at_68[0x18]; 3760 }; 3761 3762 struct mlx5_ifc_query_mkey_out_bits { 3763 u8 status[0x8]; 3764 u8 reserved_at_8[0x18]; 3765 3766 u8 syndrome[0x20]; 3767 3768 u8 reserved_at_40[0x40]; 3769 3770 struct mlx5_ifc_mkc_bits memory_key_mkey_entry; 3771 3772 u8 reserved_at_280[0x600]; 3773 3774 u8 bsf0_klm0_pas_mtt0_1[16][0x8]; 3775 3776 u8 bsf1_klm1_pas_mtt2_3[16][0x8]; 3777 }; 3778 3779 struct mlx5_ifc_query_mkey_in_bits { 3780 u8 opcode[0x10]; 3781 u8 reserved_at_10[0x10]; 3782 3783 u8 reserved_at_20[0x10]; 3784 u8 op_mod[0x10]; 3785 3786 u8 reserved_at_40[0x8]; 3787 u8 mkey_index[0x18]; 3788 3789 u8 pg_access[0x1]; 3790 u8 reserved_at_61[0x1f]; 3791 }; 3792 3793 struct mlx5_ifc_query_mad_demux_out_bits { 3794 u8 status[0x8]; 3795 u8 reserved_at_8[0x18]; 3796 3797 u8 syndrome[0x20]; 3798 3799 u8 reserved_at_40[0x40]; 3800 3801 u8 mad_dumux_parameters_block[0x20]; 3802 }; 3803 3804 struct mlx5_ifc_query_mad_demux_in_bits { 3805 u8 opcode[0x10]; 3806 u8 reserved_at_10[0x10]; 3807 3808 u8 reserved_at_20[0x10]; 3809 u8 op_mod[0x10]; 3810 3811 u8 reserved_at_40[0x40]; 3812 }; 3813 3814 struct mlx5_ifc_query_l2_table_entry_out_bits { 3815 u8 status[0x8]; 3816 u8 reserved_at_8[0x18]; 3817 3818 u8 syndrome[0x20]; 3819 3820 u8 reserved_at_40[0xa0]; 3821 3822 u8 reserved_at_e0[0x13]; 3823 u8 vlan_valid[0x1]; 3824 u8 vlan[0xc]; 3825 3826 struct mlx5_ifc_mac_address_layout_bits mac_address; 3827 3828 u8 reserved_at_140[0xc0]; 3829 }; 3830 3831 struct mlx5_ifc_query_l2_table_entry_in_bits { 3832 u8 opcode[0x10]; 3833 u8 reserved_at_10[0x10]; 3834 3835 u8 reserved_at_20[0x10]; 3836 u8 op_mod[0x10]; 3837 3838 u8 reserved_at_40[0x60]; 3839 3840 u8 reserved_at_a0[0x8]; 3841 u8 table_index[0x18]; 3842 3843 u8 reserved_at_c0[0x140]; 3844 }; 3845 3846 struct mlx5_ifc_query_issi_out_bits { 3847 u8 status[0x8]; 3848 u8 reserved_at_8[0x18]; 3849 3850 u8 syndrome[0x20]; 3851 3852 u8 reserved_at_40[0x10]; 3853 u8 current_issi[0x10]; 3854 3855 u8 reserved_at_60[0xa0]; 3856 3857 u8 reserved_at_100[76][0x8]; 3858 u8 supported_issi_dw0[0x20]; 3859 }; 3860 3861 struct mlx5_ifc_query_issi_in_bits { 3862 u8 opcode[0x10]; 3863 u8 reserved_at_10[0x10]; 3864 3865 u8 reserved_at_20[0x10]; 3866 u8 op_mod[0x10]; 3867 3868 u8 reserved_at_40[0x40]; 3869 }; 3870 3871 struct mlx5_ifc_query_hca_vport_pkey_out_bits { 3872 u8 status[0x8]; 3873 u8 reserved_at_8[0x18]; 3874 3875 u8 syndrome[0x20]; 3876 3877 u8 reserved_at_40[0x40]; 3878 3879 struct mlx5_ifc_pkey_bits pkey[0]; 3880 }; 3881 3882 struct mlx5_ifc_query_hca_vport_pkey_in_bits { 3883 u8 opcode[0x10]; 3884 u8 reserved_at_10[0x10]; 3885 3886 u8 reserved_at_20[0x10]; 3887 u8 op_mod[0x10]; 3888 3889 u8 other_vport[0x1]; 3890 u8 reserved_at_41[0xb]; 3891 u8 port_num[0x4]; 3892 u8 vport_number[0x10]; 3893 3894 u8 reserved_at_60[0x10]; 3895 u8 pkey_index[0x10]; 3896 }; 3897 3898 enum { 3899 MLX5_HCA_VPORT_SEL_PORT_GUID = 1 << 0, 3900 MLX5_HCA_VPORT_SEL_NODE_GUID = 1 << 1, 3901 MLX5_HCA_VPORT_SEL_STATE_POLICY = 1 << 2, 3902 }; 3903 3904 struct mlx5_ifc_query_hca_vport_gid_out_bits { 3905 u8 status[0x8]; 3906 u8 reserved_at_8[0x18]; 3907 3908 u8 syndrome[0x20]; 3909 3910 u8 reserved_at_40[0x20]; 3911 3912 u8 gids_num[0x10]; 3913 u8 reserved_at_70[0x10]; 3914 3915 struct mlx5_ifc_array128_auto_bits gid[0]; 3916 }; 3917 3918 struct mlx5_ifc_query_hca_vport_gid_in_bits { 3919 u8 opcode[0x10]; 3920 u8 reserved_at_10[0x10]; 3921 3922 u8 reserved_at_20[0x10]; 3923 u8 op_mod[0x10]; 3924 3925 u8 other_vport[0x1]; 3926 u8 reserved_at_41[0xb]; 3927 u8 port_num[0x4]; 3928 u8 vport_number[0x10]; 3929 3930 u8 reserved_at_60[0x10]; 3931 u8 gid_index[0x10]; 3932 }; 3933 3934 struct mlx5_ifc_query_hca_vport_context_out_bits { 3935 u8 status[0x8]; 3936 u8 reserved_at_8[0x18]; 3937 3938 u8 syndrome[0x20]; 3939 3940 u8 reserved_at_40[0x40]; 3941 3942 struct mlx5_ifc_hca_vport_context_bits hca_vport_context; 3943 }; 3944 3945 struct mlx5_ifc_query_hca_vport_context_in_bits { 3946 u8 opcode[0x10]; 3947 u8 reserved_at_10[0x10]; 3948 3949 u8 reserved_at_20[0x10]; 3950 u8 op_mod[0x10]; 3951 3952 u8 other_vport[0x1]; 3953 u8 reserved_at_41[0xb]; 3954 u8 port_num[0x4]; 3955 u8 vport_number[0x10]; 3956 3957 u8 reserved_at_60[0x20]; 3958 }; 3959 3960 struct mlx5_ifc_query_hca_cap_out_bits { 3961 u8 status[0x8]; 3962 u8 reserved_at_8[0x18]; 3963 3964 u8 syndrome[0x20]; 3965 3966 u8 reserved_at_40[0x40]; 3967 3968 union mlx5_ifc_hca_cap_union_bits capability; 3969 }; 3970 3971 struct mlx5_ifc_query_hca_cap_in_bits { 3972 u8 opcode[0x10]; 3973 u8 reserved_at_10[0x10]; 3974 3975 u8 reserved_at_20[0x10]; 3976 u8 op_mod[0x10]; 3977 3978 u8 reserved_at_40[0x40]; 3979 }; 3980 3981 struct mlx5_ifc_query_flow_table_out_bits { 3982 u8 status[0x8]; 3983 u8 reserved_at_8[0x18]; 3984 3985 u8 syndrome[0x20]; 3986 3987 u8 reserved_at_40[0x80]; 3988 3989 u8 reserved_at_c0[0x8]; 3990 u8 level[0x8]; 3991 u8 reserved_at_d0[0x8]; 3992 u8 log_size[0x8]; 3993 3994 u8 reserved_at_e0[0x120]; 3995 }; 3996 3997 struct mlx5_ifc_query_flow_table_in_bits { 3998 u8 opcode[0x10]; 3999 u8 reserved_at_10[0x10]; 4000 4001 u8 reserved_at_20[0x10]; 4002 u8 op_mod[0x10]; 4003 4004 u8 reserved_at_40[0x40]; 4005 4006 u8 table_type[0x8]; 4007 u8 reserved_at_88[0x18]; 4008 4009 u8 reserved_at_a0[0x8]; 4010 u8 table_id[0x18]; 4011 4012 u8 reserved_at_c0[0x140]; 4013 }; 4014 4015 struct mlx5_ifc_query_fte_out_bits { 4016 u8 status[0x8]; 4017 u8 reserved_at_8[0x18]; 4018 4019 u8 syndrome[0x20]; 4020 4021 u8 reserved_at_40[0x1c0]; 4022 4023 struct mlx5_ifc_flow_context_bits flow_context; 4024 }; 4025 4026 struct mlx5_ifc_query_fte_in_bits { 4027 u8 opcode[0x10]; 4028 u8 reserved_at_10[0x10]; 4029 4030 u8 reserved_at_20[0x10]; 4031 u8 op_mod[0x10]; 4032 4033 u8 reserved_at_40[0x40]; 4034 4035 u8 table_type[0x8]; 4036 u8 reserved_at_88[0x18]; 4037 4038 u8 reserved_at_a0[0x8]; 4039 u8 table_id[0x18]; 4040 4041 u8 reserved_at_c0[0x40]; 4042 4043 u8 flow_index[0x20]; 4044 4045 u8 reserved_at_120[0xe0]; 4046 }; 4047 4048 enum { 4049 MLX5_QUERY_FLOW_GROUP_OUT_MATCH_CRITERIA_ENABLE_OUTER_HEADERS = 0x0, 4050 MLX5_QUERY_FLOW_GROUP_OUT_MATCH_CRITERIA_ENABLE_MISC_PARAMETERS = 0x1, 4051 MLX5_QUERY_FLOW_GROUP_OUT_MATCH_CRITERIA_ENABLE_INNER_HEADERS = 0x2, 4052 }; 4053 4054 struct mlx5_ifc_query_flow_group_out_bits { 4055 u8 status[0x8]; 4056 u8 reserved_at_8[0x18]; 4057 4058 u8 syndrome[0x20]; 4059 4060 u8 reserved_at_40[0xa0]; 4061 4062 u8 start_flow_index[0x20]; 4063 4064 u8 reserved_at_100[0x20]; 4065 4066 u8 end_flow_index[0x20]; 4067 4068 u8 reserved_at_140[0xa0]; 4069 4070 u8 reserved_at_1e0[0x18]; 4071 u8 match_criteria_enable[0x8]; 4072 4073 struct mlx5_ifc_fte_match_param_bits match_criteria; 4074 4075 u8 reserved_at_1200[0xe00]; 4076 }; 4077 4078 struct mlx5_ifc_query_flow_group_in_bits { 4079 u8 opcode[0x10]; 4080 u8 reserved_at_10[0x10]; 4081 4082 u8 reserved_at_20[0x10]; 4083 u8 op_mod[0x10]; 4084 4085 u8 reserved_at_40[0x40]; 4086 4087 u8 table_type[0x8]; 4088 u8 reserved_at_88[0x18]; 4089 4090 u8 reserved_at_a0[0x8]; 4091 u8 table_id[0x18]; 4092 4093 u8 group_id[0x20]; 4094 4095 u8 reserved_at_e0[0x120]; 4096 }; 4097 4098 struct mlx5_ifc_query_flow_counter_out_bits { 4099 u8 status[0x8]; 4100 u8 reserved_at_8[0x18]; 4101 4102 u8 syndrome[0x20]; 4103 4104 u8 reserved_at_40[0x40]; 4105 4106 struct mlx5_ifc_traffic_counter_bits flow_statistics[0]; 4107 }; 4108 4109 struct mlx5_ifc_query_flow_counter_in_bits { 4110 u8 opcode[0x10]; 4111 u8 reserved_at_10[0x10]; 4112 4113 u8 reserved_at_20[0x10]; 4114 u8 op_mod[0x10]; 4115 4116 u8 reserved_at_40[0x80]; 4117 4118 u8 clear[0x1]; 4119 u8 reserved_at_c1[0xf]; 4120 u8 num_of_counters[0x10]; 4121 4122 u8 reserved_at_e0[0x10]; 4123 u8 flow_counter_id[0x10]; 4124 }; 4125 4126 struct mlx5_ifc_query_esw_vport_context_out_bits { 4127 u8 status[0x8]; 4128 u8 reserved_at_8[0x18]; 4129 4130 u8 syndrome[0x20]; 4131 4132 u8 reserved_at_40[0x40]; 4133 4134 struct mlx5_ifc_esw_vport_context_bits esw_vport_context; 4135 }; 4136 4137 struct mlx5_ifc_query_esw_vport_context_in_bits { 4138 u8 opcode[0x10]; 4139 u8 reserved_at_10[0x10]; 4140 4141 u8 reserved_at_20[0x10]; 4142 u8 op_mod[0x10]; 4143 4144 u8 other_vport[0x1]; 4145 u8 reserved_at_41[0xf]; 4146 u8 vport_number[0x10]; 4147 4148 u8 reserved_at_60[0x20]; 4149 }; 4150 4151 struct mlx5_ifc_modify_esw_vport_context_out_bits { 4152 u8 status[0x8]; 4153 u8 reserved_at_8[0x18]; 4154 4155 u8 syndrome[0x20]; 4156 4157 u8 reserved_at_40[0x40]; 4158 }; 4159 4160 struct mlx5_ifc_esw_vport_context_fields_select_bits { 4161 u8 reserved_at_0[0x1c]; 4162 u8 vport_cvlan_insert[0x1]; 4163 u8 vport_svlan_insert[0x1]; 4164 u8 vport_cvlan_strip[0x1]; 4165 u8 vport_svlan_strip[0x1]; 4166 }; 4167 4168 struct mlx5_ifc_modify_esw_vport_context_in_bits { 4169 u8 opcode[0x10]; 4170 u8 reserved_at_10[0x10]; 4171 4172 u8 reserved_at_20[0x10]; 4173 u8 op_mod[0x10]; 4174 4175 u8 other_vport[0x1]; 4176 u8 reserved_at_41[0xf]; 4177 u8 vport_number[0x10]; 4178 4179 struct mlx5_ifc_esw_vport_context_fields_select_bits field_select; 4180 4181 struct mlx5_ifc_esw_vport_context_bits esw_vport_context; 4182 }; 4183 4184 struct mlx5_ifc_query_eq_out_bits { 4185 u8 status[0x8]; 4186 u8 reserved_at_8[0x18]; 4187 4188 u8 syndrome[0x20]; 4189 4190 u8 reserved_at_40[0x40]; 4191 4192 struct mlx5_ifc_eqc_bits eq_context_entry; 4193 4194 u8 reserved_at_280[0x40]; 4195 4196 u8 event_bitmask[0x40]; 4197 4198 u8 reserved_at_300[0x580]; 4199 4200 u8 pas[0][0x40]; 4201 }; 4202 4203 struct mlx5_ifc_query_eq_in_bits { 4204 u8 opcode[0x10]; 4205 u8 reserved_at_10[0x10]; 4206 4207 u8 reserved_at_20[0x10]; 4208 u8 op_mod[0x10]; 4209 4210 u8 reserved_at_40[0x18]; 4211 u8 eq_number[0x8]; 4212 4213 u8 reserved_at_60[0x20]; 4214 }; 4215 4216 struct mlx5_ifc_query_dct_out_bits { 4217 u8 status[0x8]; 4218 u8 reserved_at_8[0x18]; 4219 4220 u8 syndrome[0x20]; 4221 4222 u8 reserved_at_40[0x40]; 4223 4224 struct mlx5_ifc_dctc_bits dct_context_entry; 4225 4226 u8 reserved_at_280[0x180]; 4227 }; 4228 4229 struct mlx5_ifc_query_dct_in_bits { 4230 u8 opcode[0x10]; 4231 u8 reserved_at_10[0x10]; 4232 4233 u8 reserved_at_20[0x10]; 4234 u8 op_mod[0x10]; 4235 4236 u8 reserved_at_40[0x8]; 4237 u8 dctn[0x18]; 4238 4239 u8 reserved_at_60[0x20]; 4240 }; 4241 4242 struct mlx5_ifc_query_cq_out_bits { 4243 u8 status[0x8]; 4244 u8 reserved_at_8[0x18]; 4245 4246 u8 syndrome[0x20]; 4247 4248 u8 reserved_at_40[0x40]; 4249 4250 struct mlx5_ifc_cqc_bits cq_context; 4251 4252 u8 reserved_at_280[0x600]; 4253 4254 u8 pas[0][0x40]; 4255 }; 4256 4257 struct mlx5_ifc_query_cq_in_bits { 4258 u8 opcode[0x10]; 4259 u8 reserved_at_10[0x10]; 4260 4261 u8 reserved_at_20[0x10]; 4262 u8 op_mod[0x10]; 4263 4264 u8 reserved_at_40[0x8]; 4265 u8 cqn[0x18]; 4266 4267 u8 reserved_at_60[0x20]; 4268 }; 4269 4270 struct mlx5_ifc_query_cong_status_out_bits { 4271 u8 status[0x8]; 4272 u8 reserved_at_8[0x18]; 4273 4274 u8 syndrome[0x20]; 4275 4276 u8 reserved_at_40[0x20]; 4277 4278 u8 enable[0x1]; 4279 u8 tag_enable[0x1]; 4280 u8 reserved_at_62[0x1e]; 4281 }; 4282 4283 struct mlx5_ifc_query_cong_status_in_bits { 4284 u8 opcode[0x10]; 4285 u8 reserved_at_10[0x10]; 4286 4287 u8 reserved_at_20[0x10]; 4288 u8 op_mod[0x10]; 4289 4290 u8 reserved_at_40[0x18]; 4291 u8 priority[0x4]; 4292 u8 cong_protocol[0x4]; 4293 4294 u8 reserved_at_60[0x20]; 4295 }; 4296 4297 struct mlx5_ifc_query_cong_statistics_out_bits { 4298 u8 status[0x8]; 4299 u8 reserved_at_8[0x18]; 4300 4301 u8 syndrome[0x20]; 4302 4303 u8 reserved_at_40[0x40]; 4304 4305 u8 cur_flows[0x20]; 4306 4307 u8 sum_flows[0x20]; 4308 4309 u8 cnp_ignored_high[0x20]; 4310 4311 u8 cnp_ignored_low[0x20]; 4312 4313 u8 cnp_handled_high[0x20]; 4314 4315 u8 cnp_handled_low[0x20]; 4316 4317 u8 reserved_at_140[0x100]; 4318 4319 u8 time_stamp_high[0x20]; 4320 4321 u8 time_stamp_low[0x20]; 4322 4323 u8 accumulators_period[0x20]; 4324 4325 u8 ecn_marked_roce_packets_high[0x20]; 4326 4327 u8 ecn_marked_roce_packets_low[0x20]; 4328 4329 u8 cnps_sent_high[0x20]; 4330 4331 u8 cnps_sent_low[0x20]; 4332 4333 u8 reserved_at_320[0x560]; 4334 }; 4335 4336 struct mlx5_ifc_query_cong_statistics_in_bits { 4337 u8 opcode[0x10]; 4338 u8 reserved_at_10[0x10]; 4339 4340 u8 reserved_at_20[0x10]; 4341 u8 op_mod[0x10]; 4342 4343 u8 clear[0x1]; 4344 u8 reserved_at_41[0x1f]; 4345 4346 u8 reserved_at_60[0x20]; 4347 }; 4348 4349 struct mlx5_ifc_query_cong_params_out_bits { 4350 u8 status[0x8]; 4351 u8 reserved_at_8[0x18]; 4352 4353 u8 syndrome[0x20]; 4354 4355 u8 reserved_at_40[0x40]; 4356 4357 union mlx5_ifc_cong_control_roce_ecn_auto_bits congestion_parameters; 4358 }; 4359 4360 struct mlx5_ifc_query_cong_params_in_bits { 4361 u8 opcode[0x10]; 4362 u8 reserved_at_10[0x10]; 4363 4364 u8 reserved_at_20[0x10]; 4365 u8 op_mod[0x10]; 4366 4367 u8 reserved_at_40[0x1c]; 4368 u8 cong_protocol[0x4]; 4369 4370 u8 reserved_at_60[0x20]; 4371 }; 4372 4373 struct mlx5_ifc_query_adapter_out_bits { 4374 u8 status[0x8]; 4375 u8 reserved_at_8[0x18]; 4376 4377 u8 syndrome[0x20]; 4378 4379 u8 reserved_at_40[0x40]; 4380 4381 struct mlx5_ifc_query_adapter_param_block_bits query_adapter_struct; 4382 }; 4383 4384 struct mlx5_ifc_query_adapter_in_bits { 4385 u8 opcode[0x10]; 4386 u8 reserved_at_10[0x10]; 4387 4388 u8 reserved_at_20[0x10]; 4389 u8 op_mod[0x10]; 4390 4391 u8 reserved_at_40[0x40]; 4392 }; 4393 4394 struct mlx5_ifc_qp_2rst_out_bits { 4395 u8 status[0x8]; 4396 u8 reserved_at_8[0x18]; 4397 4398 u8 syndrome[0x20]; 4399 4400 u8 reserved_at_40[0x40]; 4401 }; 4402 4403 struct mlx5_ifc_qp_2rst_in_bits { 4404 u8 opcode[0x10]; 4405 u8 reserved_at_10[0x10]; 4406 4407 u8 reserved_at_20[0x10]; 4408 u8 op_mod[0x10]; 4409 4410 u8 reserved_at_40[0x8]; 4411 u8 qpn[0x18]; 4412 4413 u8 reserved_at_60[0x20]; 4414 }; 4415 4416 struct mlx5_ifc_qp_2err_out_bits { 4417 u8 status[0x8]; 4418 u8 reserved_at_8[0x18]; 4419 4420 u8 syndrome[0x20]; 4421 4422 u8 reserved_at_40[0x40]; 4423 }; 4424 4425 struct mlx5_ifc_qp_2err_in_bits { 4426 u8 opcode[0x10]; 4427 u8 reserved_at_10[0x10]; 4428 4429 u8 reserved_at_20[0x10]; 4430 u8 op_mod[0x10]; 4431 4432 u8 reserved_at_40[0x8]; 4433 u8 qpn[0x18]; 4434 4435 u8 reserved_at_60[0x20]; 4436 }; 4437 4438 struct mlx5_ifc_page_fault_resume_out_bits { 4439 u8 status[0x8]; 4440 u8 reserved_at_8[0x18]; 4441 4442 u8 syndrome[0x20]; 4443 4444 u8 reserved_at_40[0x40]; 4445 }; 4446 4447 struct mlx5_ifc_page_fault_resume_in_bits { 4448 u8 opcode[0x10]; 4449 u8 reserved_at_10[0x10]; 4450 4451 u8 reserved_at_20[0x10]; 4452 u8 op_mod[0x10]; 4453 4454 u8 error[0x1]; 4455 u8 reserved_at_41[0x4]; 4456 u8 rdma[0x1]; 4457 u8 read_write[0x1]; 4458 u8 req_res[0x1]; 4459 u8 qpn[0x18]; 4460 4461 u8 reserved_at_60[0x20]; 4462 }; 4463 4464 struct mlx5_ifc_nop_out_bits { 4465 u8 status[0x8]; 4466 u8 reserved_at_8[0x18]; 4467 4468 u8 syndrome[0x20]; 4469 4470 u8 reserved_at_40[0x40]; 4471 }; 4472 4473 struct mlx5_ifc_nop_in_bits { 4474 u8 opcode[0x10]; 4475 u8 reserved_at_10[0x10]; 4476 4477 u8 reserved_at_20[0x10]; 4478 u8 op_mod[0x10]; 4479 4480 u8 reserved_at_40[0x40]; 4481 }; 4482 4483 struct mlx5_ifc_modify_vport_state_out_bits { 4484 u8 status[0x8]; 4485 u8 reserved_at_8[0x18]; 4486 4487 u8 syndrome[0x20]; 4488 4489 u8 reserved_at_40[0x40]; 4490 }; 4491 4492 struct mlx5_ifc_modify_vport_state_in_bits { 4493 u8 opcode[0x10]; 4494 u8 reserved_at_10[0x10]; 4495 4496 u8 reserved_at_20[0x10]; 4497 u8 op_mod[0x10]; 4498 4499 u8 other_vport[0x1]; 4500 u8 reserved_at_41[0xf]; 4501 u8 vport_number[0x10]; 4502 4503 u8 reserved_at_60[0x18]; 4504 u8 admin_state[0x4]; 4505 u8 reserved_at_7c[0x4]; 4506 }; 4507 4508 struct mlx5_ifc_modify_tis_out_bits { 4509 u8 status[0x8]; 4510 u8 reserved_at_8[0x18]; 4511 4512 u8 syndrome[0x20]; 4513 4514 u8 reserved_at_40[0x40]; 4515 }; 4516 4517 struct mlx5_ifc_modify_tis_bitmask_bits { 4518 u8 reserved_at_0[0x20]; 4519 4520 u8 reserved_at_20[0x1f]; 4521 u8 prio[0x1]; 4522 }; 4523 4524 struct mlx5_ifc_modify_tis_in_bits { 4525 u8 opcode[0x10]; 4526 u8 reserved_at_10[0x10]; 4527 4528 u8 reserved_at_20[0x10]; 4529 u8 op_mod[0x10]; 4530 4531 u8 reserved_at_40[0x8]; 4532 u8 tisn[0x18]; 4533 4534 u8 reserved_at_60[0x20]; 4535 4536 struct mlx5_ifc_modify_tis_bitmask_bits bitmask; 4537 4538 u8 reserved_at_c0[0x40]; 4539 4540 struct mlx5_ifc_tisc_bits ctx; 4541 }; 4542 4543 struct mlx5_ifc_modify_tir_bitmask_bits { 4544 u8 reserved_at_0[0x20]; 4545 4546 u8 reserved_at_20[0x1b]; 4547 u8 self_lb_en[0x1]; 4548 u8 reserved_at_3c[0x1]; 4549 u8 hash[0x1]; 4550 u8 reserved_at_3e[0x1]; 4551 u8 lro[0x1]; 4552 }; 4553 4554 struct mlx5_ifc_modify_tir_out_bits { 4555 u8 status[0x8]; 4556 u8 reserved_at_8[0x18]; 4557 4558 u8 syndrome[0x20]; 4559 4560 u8 reserved_at_40[0x40]; 4561 }; 4562 4563 struct mlx5_ifc_modify_tir_in_bits { 4564 u8 opcode[0x10]; 4565 u8 reserved_at_10[0x10]; 4566 4567 u8 reserved_at_20[0x10]; 4568 u8 op_mod[0x10]; 4569 4570 u8 reserved_at_40[0x8]; 4571 u8 tirn[0x18]; 4572 4573 u8 reserved_at_60[0x20]; 4574 4575 struct mlx5_ifc_modify_tir_bitmask_bits bitmask; 4576 4577 u8 reserved_at_c0[0x40]; 4578 4579 struct mlx5_ifc_tirc_bits ctx; 4580 }; 4581 4582 struct mlx5_ifc_modify_sq_out_bits { 4583 u8 status[0x8]; 4584 u8 reserved_at_8[0x18]; 4585 4586 u8 syndrome[0x20]; 4587 4588 u8 reserved_at_40[0x40]; 4589 }; 4590 4591 struct mlx5_ifc_modify_sq_in_bits { 4592 u8 opcode[0x10]; 4593 u8 reserved_at_10[0x10]; 4594 4595 u8 reserved_at_20[0x10]; 4596 u8 op_mod[0x10]; 4597 4598 u8 sq_state[0x4]; 4599 u8 reserved_at_44[0x4]; 4600 u8 sqn[0x18]; 4601 4602 u8 reserved_at_60[0x20]; 4603 4604 u8 modify_bitmask[0x40]; 4605 4606 u8 reserved_at_c0[0x40]; 4607 4608 struct mlx5_ifc_sqc_bits ctx; 4609 }; 4610 4611 struct mlx5_ifc_modify_rqt_out_bits { 4612 u8 status[0x8]; 4613 u8 reserved_at_8[0x18]; 4614 4615 u8 syndrome[0x20]; 4616 4617 u8 reserved_at_40[0x40]; 4618 }; 4619 4620 struct mlx5_ifc_rqt_bitmask_bits { 4621 u8 reserved_at_0[0x20]; 4622 4623 u8 reserved_at_20[0x1f]; 4624 u8 rqn_list[0x1]; 4625 }; 4626 4627 struct mlx5_ifc_modify_rqt_in_bits { 4628 u8 opcode[0x10]; 4629 u8 reserved_at_10[0x10]; 4630 4631 u8 reserved_at_20[0x10]; 4632 u8 op_mod[0x10]; 4633 4634 u8 reserved_at_40[0x8]; 4635 u8 rqtn[0x18]; 4636 4637 u8 reserved_at_60[0x20]; 4638 4639 struct mlx5_ifc_rqt_bitmask_bits bitmask; 4640 4641 u8 reserved_at_c0[0x40]; 4642 4643 struct mlx5_ifc_rqtc_bits ctx; 4644 }; 4645 4646 struct mlx5_ifc_modify_rq_out_bits { 4647 u8 status[0x8]; 4648 u8 reserved_at_8[0x18]; 4649 4650 u8 syndrome[0x20]; 4651 4652 u8 reserved_at_40[0x40]; 4653 }; 4654 4655 struct mlx5_ifc_modify_rq_in_bits { 4656 u8 opcode[0x10]; 4657 u8 reserved_at_10[0x10]; 4658 4659 u8 reserved_at_20[0x10]; 4660 u8 op_mod[0x10]; 4661 4662 u8 rq_state[0x4]; 4663 u8 reserved_at_44[0x4]; 4664 u8 rqn[0x18]; 4665 4666 u8 reserved_at_60[0x20]; 4667 4668 u8 modify_bitmask[0x40]; 4669 4670 u8 reserved_at_c0[0x40]; 4671 4672 struct mlx5_ifc_rqc_bits ctx; 4673 }; 4674 4675 struct mlx5_ifc_modify_rmp_out_bits { 4676 u8 status[0x8]; 4677 u8 reserved_at_8[0x18]; 4678 4679 u8 syndrome[0x20]; 4680 4681 u8 reserved_at_40[0x40]; 4682 }; 4683 4684 struct mlx5_ifc_rmp_bitmask_bits { 4685 u8 reserved_at_0[0x20]; 4686 4687 u8 reserved_at_20[0x1f]; 4688 u8 lwm[0x1]; 4689 }; 4690 4691 struct mlx5_ifc_modify_rmp_in_bits { 4692 u8 opcode[0x10]; 4693 u8 reserved_at_10[0x10]; 4694 4695 u8 reserved_at_20[0x10]; 4696 u8 op_mod[0x10]; 4697 4698 u8 rmp_state[0x4]; 4699 u8 reserved_at_44[0x4]; 4700 u8 rmpn[0x18]; 4701 4702 u8 reserved_at_60[0x20]; 4703 4704 struct mlx5_ifc_rmp_bitmask_bits bitmask; 4705 4706 u8 reserved_at_c0[0x40]; 4707 4708 struct mlx5_ifc_rmpc_bits ctx; 4709 }; 4710 4711 struct mlx5_ifc_modify_nic_vport_context_out_bits { 4712 u8 status[0x8]; 4713 u8 reserved_at_8[0x18]; 4714 4715 u8 syndrome[0x20]; 4716 4717 u8 reserved_at_40[0x40]; 4718 }; 4719 4720 struct mlx5_ifc_modify_nic_vport_field_select_bits { 4721 u8 reserved_at_0[0x16]; 4722 u8 node_guid[0x1]; 4723 u8 port_guid[0x1]; 4724 u8 reserved_at_18[0x1]; 4725 u8 mtu[0x1]; 4726 u8 change_event[0x1]; 4727 u8 promisc[0x1]; 4728 u8 permanent_address[0x1]; 4729 u8 addresses_list[0x1]; 4730 u8 roce_en[0x1]; 4731 u8 reserved_at_1f[0x1]; 4732 }; 4733 4734 struct mlx5_ifc_modify_nic_vport_context_in_bits { 4735 u8 opcode[0x10]; 4736 u8 reserved_at_10[0x10]; 4737 4738 u8 reserved_at_20[0x10]; 4739 u8 op_mod[0x10]; 4740 4741 u8 other_vport[0x1]; 4742 u8 reserved_at_41[0xf]; 4743 u8 vport_number[0x10]; 4744 4745 struct mlx5_ifc_modify_nic_vport_field_select_bits field_select; 4746 4747 u8 reserved_at_80[0x780]; 4748 4749 struct mlx5_ifc_nic_vport_context_bits nic_vport_context; 4750 }; 4751 4752 struct mlx5_ifc_modify_hca_vport_context_out_bits { 4753 u8 status[0x8]; 4754 u8 reserved_at_8[0x18]; 4755 4756 u8 syndrome[0x20]; 4757 4758 u8 reserved_at_40[0x40]; 4759 }; 4760 4761 struct mlx5_ifc_modify_hca_vport_context_in_bits { 4762 u8 opcode[0x10]; 4763 u8 reserved_at_10[0x10]; 4764 4765 u8 reserved_at_20[0x10]; 4766 u8 op_mod[0x10]; 4767 4768 u8 other_vport[0x1]; 4769 u8 reserved_at_41[0xb]; 4770 u8 port_num[0x4]; 4771 u8 vport_number[0x10]; 4772 4773 u8 reserved_at_60[0x20]; 4774 4775 struct mlx5_ifc_hca_vport_context_bits hca_vport_context; 4776 }; 4777 4778 struct mlx5_ifc_modify_cq_out_bits { 4779 u8 status[0x8]; 4780 u8 reserved_at_8[0x18]; 4781 4782 u8 syndrome[0x20]; 4783 4784 u8 reserved_at_40[0x40]; 4785 }; 4786 4787 enum { 4788 MLX5_MODIFY_CQ_IN_OP_MOD_MODIFY_CQ = 0x0, 4789 MLX5_MODIFY_CQ_IN_OP_MOD_RESIZE_CQ = 0x1, 4790 }; 4791 4792 struct mlx5_ifc_modify_cq_in_bits { 4793 u8 opcode[0x10]; 4794 u8 reserved_at_10[0x10]; 4795 4796 u8 reserved_at_20[0x10]; 4797 u8 op_mod[0x10]; 4798 4799 u8 reserved_at_40[0x8]; 4800 u8 cqn[0x18]; 4801 4802 union mlx5_ifc_modify_field_select_resize_field_select_auto_bits modify_field_select_resize_field_select; 4803 4804 struct mlx5_ifc_cqc_bits cq_context; 4805 4806 u8 reserved_at_280[0x600]; 4807 4808 u8 pas[0][0x40]; 4809 }; 4810 4811 struct mlx5_ifc_modify_cong_status_out_bits { 4812 u8 status[0x8]; 4813 u8 reserved_at_8[0x18]; 4814 4815 u8 syndrome[0x20]; 4816 4817 u8 reserved_at_40[0x40]; 4818 }; 4819 4820 struct mlx5_ifc_modify_cong_status_in_bits { 4821 u8 opcode[0x10]; 4822 u8 reserved_at_10[0x10]; 4823 4824 u8 reserved_at_20[0x10]; 4825 u8 op_mod[0x10]; 4826 4827 u8 reserved_at_40[0x18]; 4828 u8 priority[0x4]; 4829 u8 cong_protocol[0x4]; 4830 4831 u8 enable[0x1]; 4832 u8 tag_enable[0x1]; 4833 u8 reserved_at_62[0x1e]; 4834 }; 4835 4836 struct mlx5_ifc_modify_cong_params_out_bits { 4837 u8 status[0x8]; 4838 u8 reserved_at_8[0x18]; 4839 4840 u8 syndrome[0x20]; 4841 4842 u8 reserved_at_40[0x40]; 4843 }; 4844 4845 struct mlx5_ifc_modify_cong_params_in_bits { 4846 u8 opcode[0x10]; 4847 u8 reserved_at_10[0x10]; 4848 4849 u8 reserved_at_20[0x10]; 4850 u8 op_mod[0x10]; 4851 4852 u8 reserved_at_40[0x1c]; 4853 u8 cong_protocol[0x4]; 4854 4855 union mlx5_ifc_field_select_802_1_r_roce_auto_bits field_select; 4856 4857 u8 reserved_at_80[0x80]; 4858 4859 union mlx5_ifc_cong_control_roce_ecn_auto_bits congestion_parameters; 4860 }; 4861 4862 struct mlx5_ifc_manage_pages_out_bits { 4863 u8 status[0x8]; 4864 u8 reserved_at_8[0x18]; 4865 4866 u8 syndrome[0x20]; 4867 4868 u8 output_num_entries[0x20]; 4869 4870 u8 reserved_at_60[0x20]; 4871 4872 u8 pas[0][0x40]; 4873 }; 4874 4875 enum { 4876 MLX5_MANAGE_PAGES_IN_OP_MOD_ALLOCATION_FAIL = 0x0, 4877 MLX5_MANAGE_PAGES_IN_OP_MOD_ALLOCATION_SUCCESS = 0x1, 4878 MLX5_MANAGE_PAGES_IN_OP_MOD_HCA_RETURN_PAGES = 0x2, 4879 }; 4880 4881 struct mlx5_ifc_manage_pages_in_bits { 4882 u8 opcode[0x10]; 4883 u8 reserved_at_10[0x10]; 4884 4885 u8 reserved_at_20[0x10]; 4886 u8 op_mod[0x10]; 4887 4888 u8 reserved_at_40[0x10]; 4889 u8 function_id[0x10]; 4890 4891 u8 input_num_entries[0x20]; 4892 4893 u8 pas[0][0x40]; 4894 }; 4895 4896 struct mlx5_ifc_mad_ifc_out_bits { 4897 u8 status[0x8]; 4898 u8 reserved_at_8[0x18]; 4899 4900 u8 syndrome[0x20]; 4901 4902 u8 reserved_at_40[0x40]; 4903 4904 u8 response_mad_packet[256][0x8]; 4905 }; 4906 4907 struct mlx5_ifc_mad_ifc_in_bits { 4908 u8 opcode[0x10]; 4909 u8 reserved_at_10[0x10]; 4910 4911 u8 reserved_at_20[0x10]; 4912 u8 op_mod[0x10]; 4913 4914 u8 remote_lid[0x10]; 4915 u8 reserved_at_50[0x8]; 4916 u8 port[0x8]; 4917 4918 u8 reserved_at_60[0x20]; 4919 4920 u8 mad[256][0x8]; 4921 }; 4922 4923 struct mlx5_ifc_init_hca_out_bits { 4924 u8 status[0x8]; 4925 u8 reserved_at_8[0x18]; 4926 4927 u8 syndrome[0x20]; 4928 4929 u8 reserved_at_40[0x40]; 4930 }; 4931 4932 struct mlx5_ifc_init_hca_in_bits { 4933 u8 opcode[0x10]; 4934 u8 reserved_at_10[0x10]; 4935 4936 u8 reserved_at_20[0x10]; 4937 u8 op_mod[0x10]; 4938 4939 u8 reserved_at_40[0x40]; 4940 }; 4941 4942 struct mlx5_ifc_init2rtr_qp_out_bits { 4943 u8 status[0x8]; 4944 u8 reserved_at_8[0x18]; 4945 4946 u8 syndrome[0x20]; 4947 4948 u8 reserved_at_40[0x40]; 4949 }; 4950 4951 struct mlx5_ifc_init2rtr_qp_in_bits { 4952 u8 opcode[0x10]; 4953 u8 reserved_at_10[0x10]; 4954 4955 u8 reserved_at_20[0x10]; 4956 u8 op_mod[0x10]; 4957 4958 u8 reserved_at_40[0x8]; 4959 u8 qpn[0x18]; 4960 4961 u8 reserved_at_60[0x20]; 4962 4963 u8 opt_param_mask[0x20]; 4964 4965 u8 reserved_at_a0[0x20]; 4966 4967 struct mlx5_ifc_qpc_bits qpc; 4968 4969 u8 reserved_at_800[0x80]; 4970 }; 4971 4972 struct mlx5_ifc_init2init_qp_out_bits { 4973 u8 status[0x8]; 4974 u8 reserved_at_8[0x18]; 4975 4976 u8 syndrome[0x20]; 4977 4978 u8 reserved_at_40[0x40]; 4979 }; 4980 4981 struct mlx5_ifc_init2init_qp_in_bits { 4982 u8 opcode[0x10]; 4983 u8 reserved_at_10[0x10]; 4984 4985 u8 reserved_at_20[0x10]; 4986 u8 op_mod[0x10]; 4987 4988 u8 reserved_at_40[0x8]; 4989 u8 qpn[0x18]; 4990 4991 u8 reserved_at_60[0x20]; 4992 4993 u8 opt_param_mask[0x20]; 4994 4995 u8 reserved_at_a0[0x20]; 4996 4997 struct mlx5_ifc_qpc_bits qpc; 4998 4999 u8 reserved_at_800[0x80]; 5000 }; 5001 5002 struct mlx5_ifc_get_dropped_packet_log_out_bits { 5003 u8 status[0x8]; 5004 u8 reserved_at_8[0x18]; 5005 5006 u8 syndrome[0x20]; 5007 5008 u8 reserved_at_40[0x40]; 5009 5010 u8 packet_headers_log[128][0x8]; 5011 5012 u8 packet_syndrome[64][0x8]; 5013 }; 5014 5015 struct mlx5_ifc_get_dropped_packet_log_in_bits { 5016 u8 opcode[0x10]; 5017 u8 reserved_at_10[0x10]; 5018 5019 u8 reserved_at_20[0x10]; 5020 u8 op_mod[0x10]; 5021 5022 u8 reserved_at_40[0x40]; 5023 }; 5024 5025 struct mlx5_ifc_gen_eqe_in_bits { 5026 u8 opcode[0x10]; 5027 u8 reserved_at_10[0x10]; 5028 5029 u8 reserved_at_20[0x10]; 5030 u8 op_mod[0x10]; 5031 5032 u8 reserved_at_40[0x18]; 5033 u8 eq_number[0x8]; 5034 5035 u8 reserved_at_60[0x20]; 5036 5037 u8 eqe[64][0x8]; 5038 }; 5039 5040 struct mlx5_ifc_gen_eq_out_bits { 5041 u8 status[0x8]; 5042 u8 reserved_at_8[0x18]; 5043 5044 u8 syndrome[0x20]; 5045 5046 u8 reserved_at_40[0x40]; 5047 }; 5048 5049 struct mlx5_ifc_enable_hca_out_bits { 5050 u8 status[0x8]; 5051 u8 reserved_at_8[0x18]; 5052 5053 u8 syndrome[0x20]; 5054 5055 u8 reserved_at_40[0x20]; 5056 }; 5057 5058 struct mlx5_ifc_enable_hca_in_bits { 5059 u8 opcode[0x10]; 5060 u8 reserved_at_10[0x10]; 5061 5062 u8 reserved_at_20[0x10]; 5063 u8 op_mod[0x10]; 5064 5065 u8 reserved_at_40[0x10]; 5066 u8 function_id[0x10]; 5067 5068 u8 reserved_at_60[0x20]; 5069 }; 5070 5071 struct mlx5_ifc_drain_dct_out_bits { 5072 u8 status[0x8]; 5073 u8 reserved_at_8[0x18]; 5074 5075 u8 syndrome[0x20]; 5076 5077 u8 reserved_at_40[0x40]; 5078 }; 5079 5080 struct mlx5_ifc_drain_dct_in_bits { 5081 u8 opcode[0x10]; 5082 u8 reserved_at_10[0x10]; 5083 5084 u8 reserved_at_20[0x10]; 5085 u8 op_mod[0x10]; 5086 5087 u8 reserved_at_40[0x8]; 5088 u8 dctn[0x18]; 5089 5090 u8 reserved_at_60[0x20]; 5091 }; 5092 5093 struct mlx5_ifc_disable_hca_out_bits { 5094 u8 status[0x8]; 5095 u8 reserved_at_8[0x18]; 5096 5097 u8 syndrome[0x20]; 5098 5099 u8 reserved_at_40[0x20]; 5100 }; 5101 5102 struct mlx5_ifc_disable_hca_in_bits { 5103 u8 opcode[0x10]; 5104 u8 reserved_at_10[0x10]; 5105 5106 u8 reserved_at_20[0x10]; 5107 u8 op_mod[0x10]; 5108 5109 u8 reserved_at_40[0x10]; 5110 u8 function_id[0x10]; 5111 5112 u8 reserved_at_60[0x20]; 5113 }; 5114 5115 struct mlx5_ifc_detach_from_mcg_out_bits { 5116 u8 status[0x8]; 5117 u8 reserved_at_8[0x18]; 5118 5119 u8 syndrome[0x20]; 5120 5121 u8 reserved_at_40[0x40]; 5122 }; 5123 5124 struct mlx5_ifc_detach_from_mcg_in_bits { 5125 u8 opcode[0x10]; 5126 u8 reserved_at_10[0x10]; 5127 5128 u8 reserved_at_20[0x10]; 5129 u8 op_mod[0x10]; 5130 5131 u8 reserved_at_40[0x8]; 5132 u8 qpn[0x18]; 5133 5134 u8 reserved_at_60[0x20]; 5135 5136 u8 multicast_gid[16][0x8]; 5137 }; 5138 5139 struct mlx5_ifc_destroy_xrq_out_bits { 5140 u8 status[0x8]; 5141 u8 reserved_at_8[0x18]; 5142 5143 u8 syndrome[0x20]; 5144 5145 u8 reserved_at_40[0x40]; 5146 }; 5147 5148 struct mlx5_ifc_destroy_xrq_in_bits { 5149 u8 opcode[0x10]; 5150 u8 reserved_at_10[0x10]; 5151 5152 u8 reserved_at_20[0x10]; 5153 u8 op_mod[0x10]; 5154 5155 u8 reserved_at_40[0x8]; 5156 u8 xrqn[0x18]; 5157 5158 u8 reserved_at_60[0x20]; 5159 }; 5160 5161 struct mlx5_ifc_destroy_xrc_srq_out_bits { 5162 u8 status[0x8]; 5163 u8 reserved_at_8[0x18]; 5164 5165 u8 syndrome[0x20]; 5166 5167 u8 reserved_at_40[0x40]; 5168 }; 5169 5170 struct mlx5_ifc_destroy_xrc_srq_in_bits { 5171 u8 opcode[0x10]; 5172 u8 reserved_at_10[0x10]; 5173 5174 u8 reserved_at_20[0x10]; 5175 u8 op_mod[0x10]; 5176 5177 u8 reserved_at_40[0x8]; 5178 u8 xrc_srqn[0x18]; 5179 5180 u8 reserved_at_60[0x20]; 5181 }; 5182 5183 struct mlx5_ifc_destroy_tis_out_bits { 5184 u8 status[0x8]; 5185 u8 reserved_at_8[0x18]; 5186 5187 u8 syndrome[0x20]; 5188 5189 u8 reserved_at_40[0x40]; 5190 }; 5191 5192 struct mlx5_ifc_destroy_tis_in_bits { 5193 u8 opcode[0x10]; 5194 u8 reserved_at_10[0x10]; 5195 5196 u8 reserved_at_20[0x10]; 5197 u8 op_mod[0x10]; 5198 5199 u8 reserved_at_40[0x8]; 5200 u8 tisn[0x18]; 5201 5202 u8 reserved_at_60[0x20]; 5203 }; 5204 5205 struct mlx5_ifc_destroy_tir_out_bits { 5206 u8 status[0x8]; 5207 u8 reserved_at_8[0x18]; 5208 5209 u8 syndrome[0x20]; 5210 5211 u8 reserved_at_40[0x40]; 5212 }; 5213 5214 struct mlx5_ifc_destroy_tir_in_bits { 5215 u8 opcode[0x10]; 5216 u8 reserved_at_10[0x10]; 5217 5218 u8 reserved_at_20[0x10]; 5219 u8 op_mod[0x10]; 5220 5221 u8 reserved_at_40[0x8]; 5222 u8 tirn[0x18]; 5223 5224 u8 reserved_at_60[0x20]; 5225 }; 5226 5227 struct mlx5_ifc_destroy_srq_out_bits { 5228 u8 status[0x8]; 5229 u8 reserved_at_8[0x18]; 5230 5231 u8 syndrome[0x20]; 5232 5233 u8 reserved_at_40[0x40]; 5234 }; 5235 5236 struct mlx5_ifc_destroy_srq_in_bits { 5237 u8 opcode[0x10]; 5238 u8 reserved_at_10[0x10]; 5239 5240 u8 reserved_at_20[0x10]; 5241 u8 op_mod[0x10]; 5242 5243 u8 reserved_at_40[0x8]; 5244 u8 srqn[0x18]; 5245 5246 u8 reserved_at_60[0x20]; 5247 }; 5248 5249 struct mlx5_ifc_destroy_sq_out_bits { 5250 u8 status[0x8]; 5251 u8 reserved_at_8[0x18]; 5252 5253 u8 syndrome[0x20]; 5254 5255 u8 reserved_at_40[0x40]; 5256 }; 5257 5258 struct mlx5_ifc_destroy_sq_in_bits { 5259 u8 opcode[0x10]; 5260 u8 reserved_at_10[0x10]; 5261 5262 u8 reserved_at_20[0x10]; 5263 u8 op_mod[0x10]; 5264 5265 u8 reserved_at_40[0x8]; 5266 u8 sqn[0x18]; 5267 5268 u8 reserved_at_60[0x20]; 5269 }; 5270 5271 struct mlx5_ifc_destroy_rqt_out_bits { 5272 u8 status[0x8]; 5273 u8 reserved_at_8[0x18]; 5274 5275 u8 syndrome[0x20]; 5276 5277 u8 reserved_at_40[0x40]; 5278 }; 5279 5280 struct mlx5_ifc_destroy_rqt_in_bits { 5281 u8 opcode[0x10]; 5282 u8 reserved_at_10[0x10]; 5283 5284 u8 reserved_at_20[0x10]; 5285 u8 op_mod[0x10]; 5286 5287 u8 reserved_at_40[0x8]; 5288 u8 rqtn[0x18]; 5289 5290 u8 reserved_at_60[0x20]; 5291 }; 5292 5293 struct mlx5_ifc_destroy_rq_out_bits { 5294 u8 status[0x8]; 5295 u8 reserved_at_8[0x18]; 5296 5297 u8 syndrome[0x20]; 5298 5299 u8 reserved_at_40[0x40]; 5300 }; 5301 5302 struct mlx5_ifc_destroy_rq_in_bits { 5303 u8 opcode[0x10]; 5304 u8 reserved_at_10[0x10]; 5305 5306 u8 reserved_at_20[0x10]; 5307 u8 op_mod[0x10]; 5308 5309 u8 reserved_at_40[0x8]; 5310 u8 rqn[0x18]; 5311 5312 u8 reserved_at_60[0x20]; 5313 }; 5314 5315 struct mlx5_ifc_destroy_rmp_out_bits { 5316 u8 status[0x8]; 5317 u8 reserved_at_8[0x18]; 5318 5319 u8 syndrome[0x20]; 5320 5321 u8 reserved_at_40[0x40]; 5322 }; 5323 5324 struct mlx5_ifc_destroy_rmp_in_bits { 5325 u8 opcode[0x10]; 5326 u8 reserved_at_10[0x10]; 5327 5328 u8 reserved_at_20[0x10]; 5329 u8 op_mod[0x10]; 5330 5331 u8 reserved_at_40[0x8]; 5332 u8 rmpn[0x18]; 5333 5334 u8 reserved_at_60[0x20]; 5335 }; 5336 5337 struct mlx5_ifc_destroy_qp_out_bits { 5338 u8 status[0x8]; 5339 u8 reserved_at_8[0x18]; 5340 5341 u8 syndrome[0x20]; 5342 5343 u8 reserved_at_40[0x40]; 5344 }; 5345 5346 struct mlx5_ifc_destroy_qp_in_bits { 5347 u8 opcode[0x10]; 5348 u8 reserved_at_10[0x10]; 5349 5350 u8 reserved_at_20[0x10]; 5351 u8 op_mod[0x10]; 5352 5353 u8 reserved_at_40[0x8]; 5354 u8 qpn[0x18]; 5355 5356 u8 reserved_at_60[0x20]; 5357 }; 5358 5359 struct mlx5_ifc_destroy_psv_out_bits { 5360 u8 status[0x8]; 5361 u8 reserved_at_8[0x18]; 5362 5363 u8 syndrome[0x20]; 5364 5365 u8 reserved_at_40[0x40]; 5366 }; 5367 5368 struct mlx5_ifc_destroy_psv_in_bits { 5369 u8 opcode[0x10]; 5370 u8 reserved_at_10[0x10]; 5371 5372 u8 reserved_at_20[0x10]; 5373 u8 op_mod[0x10]; 5374 5375 u8 reserved_at_40[0x8]; 5376 u8 psvn[0x18]; 5377 5378 u8 reserved_at_60[0x20]; 5379 }; 5380 5381 struct mlx5_ifc_destroy_mkey_out_bits { 5382 u8 status[0x8]; 5383 u8 reserved_at_8[0x18]; 5384 5385 u8 syndrome[0x20]; 5386 5387 u8 reserved_at_40[0x40]; 5388 }; 5389 5390 struct mlx5_ifc_destroy_mkey_in_bits { 5391 u8 opcode[0x10]; 5392 u8 reserved_at_10[0x10]; 5393 5394 u8 reserved_at_20[0x10]; 5395 u8 op_mod[0x10]; 5396 5397 u8 reserved_at_40[0x8]; 5398 u8 mkey_index[0x18]; 5399 5400 u8 reserved_at_60[0x20]; 5401 }; 5402 5403 struct mlx5_ifc_destroy_flow_table_out_bits { 5404 u8 status[0x8]; 5405 u8 reserved_at_8[0x18]; 5406 5407 u8 syndrome[0x20]; 5408 5409 u8 reserved_at_40[0x40]; 5410 }; 5411 5412 struct mlx5_ifc_destroy_flow_table_in_bits { 5413 u8 opcode[0x10]; 5414 u8 reserved_at_10[0x10]; 5415 5416 u8 reserved_at_20[0x10]; 5417 u8 op_mod[0x10]; 5418 5419 u8 other_vport[0x1]; 5420 u8 reserved_at_41[0xf]; 5421 u8 vport_number[0x10]; 5422 5423 u8 reserved_at_60[0x20]; 5424 5425 u8 table_type[0x8]; 5426 u8 reserved_at_88[0x18]; 5427 5428 u8 reserved_at_a0[0x8]; 5429 u8 table_id[0x18]; 5430 5431 u8 reserved_at_c0[0x140]; 5432 }; 5433 5434 struct mlx5_ifc_destroy_flow_group_out_bits { 5435 u8 status[0x8]; 5436 u8 reserved_at_8[0x18]; 5437 5438 u8 syndrome[0x20]; 5439 5440 u8 reserved_at_40[0x40]; 5441 }; 5442 5443 struct mlx5_ifc_destroy_flow_group_in_bits { 5444 u8 opcode[0x10]; 5445 u8 reserved_at_10[0x10]; 5446 5447 u8 reserved_at_20[0x10]; 5448 u8 op_mod[0x10]; 5449 5450 u8 other_vport[0x1]; 5451 u8 reserved_at_41[0xf]; 5452 u8 vport_number[0x10]; 5453 5454 u8 reserved_at_60[0x20]; 5455 5456 u8 table_type[0x8]; 5457 u8 reserved_at_88[0x18]; 5458 5459 u8 reserved_at_a0[0x8]; 5460 u8 table_id[0x18]; 5461 5462 u8 group_id[0x20]; 5463 5464 u8 reserved_at_e0[0x120]; 5465 }; 5466 5467 struct mlx5_ifc_destroy_eq_out_bits { 5468 u8 status[0x8]; 5469 u8 reserved_at_8[0x18]; 5470 5471 u8 syndrome[0x20]; 5472 5473 u8 reserved_at_40[0x40]; 5474 }; 5475 5476 struct mlx5_ifc_destroy_eq_in_bits { 5477 u8 opcode[0x10]; 5478 u8 reserved_at_10[0x10]; 5479 5480 u8 reserved_at_20[0x10]; 5481 u8 op_mod[0x10]; 5482 5483 u8 reserved_at_40[0x18]; 5484 u8 eq_number[0x8]; 5485 5486 u8 reserved_at_60[0x20]; 5487 }; 5488 5489 struct mlx5_ifc_destroy_dct_out_bits { 5490 u8 status[0x8]; 5491 u8 reserved_at_8[0x18]; 5492 5493 u8 syndrome[0x20]; 5494 5495 u8 reserved_at_40[0x40]; 5496 }; 5497 5498 struct mlx5_ifc_destroy_dct_in_bits { 5499 u8 opcode[0x10]; 5500 u8 reserved_at_10[0x10]; 5501 5502 u8 reserved_at_20[0x10]; 5503 u8 op_mod[0x10]; 5504 5505 u8 reserved_at_40[0x8]; 5506 u8 dctn[0x18]; 5507 5508 u8 reserved_at_60[0x20]; 5509 }; 5510 5511 struct mlx5_ifc_destroy_cq_out_bits { 5512 u8 status[0x8]; 5513 u8 reserved_at_8[0x18]; 5514 5515 u8 syndrome[0x20]; 5516 5517 u8 reserved_at_40[0x40]; 5518 }; 5519 5520 struct mlx5_ifc_destroy_cq_in_bits { 5521 u8 opcode[0x10]; 5522 u8 reserved_at_10[0x10]; 5523 5524 u8 reserved_at_20[0x10]; 5525 u8 op_mod[0x10]; 5526 5527 u8 reserved_at_40[0x8]; 5528 u8 cqn[0x18]; 5529 5530 u8 reserved_at_60[0x20]; 5531 }; 5532 5533 struct mlx5_ifc_delete_vxlan_udp_dport_out_bits { 5534 u8 status[0x8]; 5535 u8 reserved_at_8[0x18]; 5536 5537 u8 syndrome[0x20]; 5538 5539 u8 reserved_at_40[0x40]; 5540 }; 5541 5542 struct mlx5_ifc_delete_vxlan_udp_dport_in_bits { 5543 u8 opcode[0x10]; 5544 u8 reserved_at_10[0x10]; 5545 5546 u8 reserved_at_20[0x10]; 5547 u8 op_mod[0x10]; 5548 5549 u8 reserved_at_40[0x20]; 5550 5551 u8 reserved_at_60[0x10]; 5552 u8 vxlan_udp_port[0x10]; 5553 }; 5554 5555 struct mlx5_ifc_delete_l2_table_entry_out_bits { 5556 u8 status[0x8]; 5557 u8 reserved_at_8[0x18]; 5558 5559 u8 syndrome[0x20]; 5560 5561 u8 reserved_at_40[0x40]; 5562 }; 5563 5564 struct mlx5_ifc_delete_l2_table_entry_in_bits { 5565 u8 opcode[0x10]; 5566 u8 reserved_at_10[0x10]; 5567 5568 u8 reserved_at_20[0x10]; 5569 u8 op_mod[0x10]; 5570 5571 u8 reserved_at_40[0x60]; 5572 5573 u8 reserved_at_a0[0x8]; 5574 u8 table_index[0x18]; 5575 5576 u8 reserved_at_c0[0x140]; 5577 }; 5578 5579 struct mlx5_ifc_delete_fte_out_bits { 5580 u8 status[0x8]; 5581 u8 reserved_at_8[0x18]; 5582 5583 u8 syndrome[0x20]; 5584 5585 u8 reserved_at_40[0x40]; 5586 }; 5587 5588 struct mlx5_ifc_delete_fte_in_bits { 5589 u8 opcode[0x10]; 5590 u8 reserved_at_10[0x10]; 5591 5592 u8 reserved_at_20[0x10]; 5593 u8 op_mod[0x10]; 5594 5595 u8 other_vport[0x1]; 5596 u8 reserved_at_41[0xf]; 5597 u8 vport_number[0x10]; 5598 5599 u8 reserved_at_60[0x20]; 5600 5601 u8 table_type[0x8]; 5602 u8 reserved_at_88[0x18]; 5603 5604 u8 reserved_at_a0[0x8]; 5605 u8 table_id[0x18]; 5606 5607 u8 reserved_at_c0[0x40]; 5608 5609 u8 flow_index[0x20]; 5610 5611 u8 reserved_at_120[0xe0]; 5612 }; 5613 5614 struct mlx5_ifc_dealloc_xrcd_out_bits { 5615 u8 status[0x8]; 5616 u8 reserved_at_8[0x18]; 5617 5618 u8 syndrome[0x20]; 5619 5620 u8 reserved_at_40[0x40]; 5621 }; 5622 5623 struct mlx5_ifc_dealloc_xrcd_in_bits { 5624 u8 opcode[0x10]; 5625 u8 reserved_at_10[0x10]; 5626 5627 u8 reserved_at_20[0x10]; 5628 u8 op_mod[0x10]; 5629 5630 u8 reserved_at_40[0x8]; 5631 u8 xrcd[0x18]; 5632 5633 u8 reserved_at_60[0x20]; 5634 }; 5635 5636 struct mlx5_ifc_dealloc_uar_out_bits { 5637 u8 status[0x8]; 5638 u8 reserved_at_8[0x18]; 5639 5640 u8 syndrome[0x20]; 5641 5642 u8 reserved_at_40[0x40]; 5643 }; 5644 5645 struct mlx5_ifc_dealloc_uar_in_bits { 5646 u8 opcode[0x10]; 5647 u8 reserved_at_10[0x10]; 5648 5649 u8 reserved_at_20[0x10]; 5650 u8 op_mod[0x10]; 5651 5652 u8 reserved_at_40[0x8]; 5653 u8 uar[0x18]; 5654 5655 u8 reserved_at_60[0x20]; 5656 }; 5657 5658 struct mlx5_ifc_dealloc_transport_domain_out_bits { 5659 u8 status[0x8]; 5660 u8 reserved_at_8[0x18]; 5661 5662 u8 syndrome[0x20]; 5663 5664 u8 reserved_at_40[0x40]; 5665 }; 5666 5667 struct mlx5_ifc_dealloc_transport_domain_in_bits { 5668 u8 opcode[0x10]; 5669 u8 reserved_at_10[0x10]; 5670 5671 u8 reserved_at_20[0x10]; 5672 u8 op_mod[0x10]; 5673 5674 u8 reserved_at_40[0x8]; 5675 u8 transport_domain[0x18]; 5676 5677 u8 reserved_at_60[0x20]; 5678 }; 5679 5680 struct mlx5_ifc_dealloc_q_counter_out_bits { 5681 u8 status[0x8]; 5682 u8 reserved_at_8[0x18]; 5683 5684 u8 syndrome[0x20]; 5685 5686 u8 reserved_at_40[0x40]; 5687 }; 5688 5689 struct mlx5_ifc_dealloc_q_counter_in_bits { 5690 u8 opcode[0x10]; 5691 u8 reserved_at_10[0x10]; 5692 5693 u8 reserved_at_20[0x10]; 5694 u8 op_mod[0x10]; 5695 5696 u8 reserved_at_40[0x18]; 5697 u8 counter_set_id[0x8]; 5698 5699 u8 reserved_at_60[0x20]; 5700 }; 5701 5702 struct mlx5_ifc_dealloc_pd_out_bits { 5703 u8 status[0x8]; 5704 u8 reserved_at_8[0x18]; 5705 5706 u8 syndrome[0x20]; 5707 5708 u8 reserved_at_40[0x40]; 5709 }; 5710 5711 struct mlx5_ifc_dealloc_pd_in_bits { 5712 u8 opcode[0x10]; 5713 u8 reserved_at_10[0x10]; 5714 5715 u8 reserved_at_20[0x10]; 5716 u8 op_mod[0x10]; 5717 5718 u8 reserved_at_40[0x8]; 5719 u8 pd[0x18]; 5720 5721 u8 reserved_at_60[0x20]; 5722 }; 5723 5724 struct mlx5_ifc_dealloc_flow_counter_out_bits { 5725 u8 status[0x8]; 5726 u8 reserved_at_8[0x18]; 5727 5728 u8 syndrome[0x20]; 5729 5730 u8 reserved_at_40[0x40]; 5731 }; 5732 5733 struct mlx5_ifc_dealloc_flow_counter_in_bits { 5734 u8 opcode[0x10]; 5735 u8 reserved_at_10[0x10]; 5736 5737 u8 reserved_at_20[0x10]; 5738 u8 op_mod[0x10]; 5739 5740 u8 reserved_at_40[0x10]; 5741 u8 flow_counter_id[0x10]; 5742 5743 u8 reserved_at_60[0x20]; 5744 }; 5745 5746 struct mlx5_ifc_create_xrq_out_bits { 5747 u8 status[0x8]; 5748 u8 reserved_at_8[0x18]; 5749 5750 u8 syndrome[0x20]; 5751 5752 u8 reserved_at_40[0x8]; 5753 u8 xrqn[0x18]; 5754 5755 u8 reserved_at_60[0x20]; 5756 }; 5757 5758 struct mlx5_ifc_create_xrq_in_bits { 5759 u8 opcode[0x10]; 5760 u8 reserved_at_10[0x10]; 5761 5762 u8 reserved_at_20[0x10]; 5763 u8 op_mod[0x10]; 5764 5765 u8 reserved_at_40[0x40]; 5766 5767 struct mlx5_ifc_xrqc_bits xrq_context; 5768 }; 5769 5770 struct mlx5_ifc_create_xrc_srq_out_bits { 5771 u8 status[0x8]; 5772 u8 reserved_at_8[0x18]; 5773 5774 u8 syndrome[0x20]; 5775 5776 u8 reserved_at_40[0x8]; 5777 u8 xrc_srqn[0x18]; 5778 5779 u8 reserved_at_60[0x20]; 5780 }; 5781 5782 struct mlx5_ifc_create_xrc_srq_in_bits { 5783 u8 opcode[0x10]; 5784 u8 reserved_at_10[0x10]; 5785 5786 u8 reserved_at_20[0x10]; 5787 u8 op_mod[0x10]; 5788 5789 u8 reserved_at_40[0x40]; 5790 5791 struct mlx5_ifc_xrc_srqc_bits xrc_srq_context_entry; 5792 5793 u8 reserved_at_280[0x600]; 5794 5795 u8 pas[0][0x40]; 5796 }; 5797 5798 struct mlx5_ifc_create_tis_out_bits { 5799 u8 status[0x8]; 5800 u8 reserved_at_8[0x18]; 5801 5802 u8 syndrome[0x20]; 5803 5804 u8 reserved_at_40[0x8]; 5805 u8 tisn[0x18]; 5806 5807 u8 reserved_at_60[0x20]; 5808 }; 5809 5810 struct mlx5_ifc_create_tis_in_bits { 5811 u8 opcode[0x10]; 5812 u8 reserved_at_10[0x10]; 5813 5814 u8 reserved_at_20[0x10]; 5815 u8 op_mod[0x10]; 5816 5817 u8 reserved_at_40[0xc0]; 5818 5819 struct mlx5_ifc_tisc_bits ctx; 5820 }; 5821 5822 struct mlx5_ifc_create_tir_out_bits { 5823 u8 status[0x8]; 5824 u8 reserved_at_8[0x18]; 5825 5826 u8 syndrome[0x20]; 5827 5828 u8 reserved_at_40[0x8]; 5829 u8 tirn[0x18]; 5830 5831 u8 reserved_at_60[0x20]; 5832 }; 5833 5834 struct mlx5_ifc_create_tir_in_bits { 5835 u8 opcode[0x10]; 5836 u8 reserved_at_10[0x10]; 5837 5838 u8 reserved_at_20[0x10]; 5839 u8 op_mod[0x10]; 5840 5841 u8 reserved_at_40[0xc0]; 5842 5843 struct mlx5_ifc_tirc_bits ctx; 5844 }; 5845 5846 struct mlx5_ifc_create_srq_out_bits { 5847 u8 status[0x8]; 5848 u8 reserved_at_8[0x18]; 5849 5850 u8 syndrome[0x20]; 5851 5852 u8 reserved_at_40[0x8]; 5853 u8 srqn[0x18]; 5854 5855 u8 reserved_at_60[0x20]; 5856 }; 5857 5858 struct mlx5_ifc_create_srq_in_bits { 5859 u8 opcode[0x10]; 5860 u8 reserved_at_10[0x10]; 5861 5862 u8 reserved_at_20[0x10]; 5863 u8 op_mod[0x10]; 5864 5865 u8 reserved_at_40[0x40]; 5866 5867 struct mlx5_ifc_srqc_bits srq_context_entry; 5868 5869 u8 reserved_at_280[0x600]; 5870 5871 u8 pas[0][0x40]; 5872 }; 5873 5874 struct mlx5_ifc_create_sq_out_bits { 5875 u8 status[0x8]; 5876 u8 reserved_at_8[0x18]; 5877 5878 u8 syndrome[0x20]; 5879 5880 u8 reserved_at_40[0x8]; 5881 u8 sqn[0x18]; 5882 5883 u8 reserved_at_60[0x20]; 5884 }; 5885 5886 struct mlx5_ifc_create_sq_in_bits { 5887 u8 opcode[0x10]; 5888 u8 reserved_at_10[0x10]; 5889 5890 u8 reserved_at_20[0x10]; 5891 u8 op_mod[0x10]; 5892 5893 u8 reserved_at_40[0xc0]; 5894 5895 struct mlx5_ifc_sqc_bits ctx; 5896 }; 5897 5898 struct mlx5_ifc_create_rqt_out_bits { 5899 u8 status[0x8]; 5900 u8 reserved_at_8[0x18]; 5901 5902 u8 syndrome[0x20]; 5903 5904 u8 reserved_at_40[0x8]; 5905 u8 rqtn[0x18]; 5906 5907 u8 reserved_at_60[0x20]; 5908 }; 5909 5910 struct mlx5_ifc_create_rqt_in_bits { 5911 u8 opcode[0x10]; 5912 u8 reserved_at_10[0x10]; 5913 5914 u8 reserved_at_20[0x10]; 5915 u8 op_mod[0x10]; 5916 5917 u8 reserved_at_40[0xc0]; 5918 5919 struct mlx5_ifc_rqtc_bits rqt_context; 5920 }; 5921 5922 struct mlx5_ifc_create_rq_out_bits { 5923 u8 status[0x8]; 5924 u8 reserved_at_8[0x18]; 5925 5926 u8 syndrome[0x20]; 5927 5928 u8 reserved_at_40[0x8]; 5929 u8 rqn[0x18]; 5930 5931 u8 reserved_at_60[0x20]; 5932 }; 5933 5934 struct mlx5_ifc_create_rq_in_bits { 5935 u8 opcode[0x10]; 5936 u8 reserved_at_10[0x10]; 5937 5938 u8 reserved_at_20[0x10]; 5939 u8 op_mod[0x10]; 5940 5941 u8 reserved_at_40[0xc0]; 5942 5943 struct mlx5_ifc_rqc_bits ctx; 5944 }; 5945 5946 struct mlx5_ifc_create_rmp_out_bits { 5947 u8 status[0x8]; 5948 u8 reserved_at_8[0x18]; 5949 5950 u8 syndrome[0x20]; 5951 5952 u8 reserved_at_40[0x8]; 5953 u8 rmpn[0x18]; 5954 5955 u8 reserved_at_60[0x20]; 5956 }; 5957 5958 struct mlx5_ifc_create_rmp_in_bits { 5959 u8 opcode[0x10]; 5960 u8 reserved_at_10[0x10]; 5961 5962 u8 reserved_at_20[0x10]; 5963 u8 op_mod[0x10]; 5964 5965 u8 reserved_at_40[0xc0]; 5966 5967 struct mlx5_ifc_rmpc_bits ctx; 5968 }; 5969 5970 struct mlx5_ifc_create_qp_out_bits { 5971 u8 status[0x8]; 5972 u8 reserved_at_8[0x18]; 5973 5974 u8 syndrome[0x20]; 5975 5976 u8 reserved_at_40[0x8]; 5977 u8 qpn[0x18]; 5978 5979 u8 reserved_at_60[0x20]; 5980 }; 5981 5982 struct mlx5_ifc_create_qp_in_bits { 5983 u8 opcode[0x10]; 5984 u8 reserved_at_10[0x10]; 5985 5986 u8 reserved_at_20[0x10]; 5987 u8 op_mod[0x10]; 5988 5989 u8 reserved_at_40[0x40]; 5990 5991 u8 opt_param_mask[0x20]; 5992 5993 u8 reserved_at_a0[0x20]; 5994 5995 struct mlx5_ifc_qpc_bits qpc; 5996 5997 u8 reserved_at_800[0x80]; 5998 5999 u8 pas[0][0x40]; 6000 }; 6001 6002 struct mlx5_ifc_create_psv_out_bits { 6003 u8 status[0x8]; 6004 u8 reserved_at_8[0x18]; 6005 6006 u8 syndrome[0x20]; 6007 6008 u8 reserved_at_40[0x40]; 6009 6010 u8 reserved_at_80[0x8]; 6011 u8 psv0_index[0x18]; 6012 6013 u8 reserved_at_a0[0x8]; 6014 u8 psv1_index[0x18]; 6015 6016 u8 reserved_at_c0[0x8]; 6017 u8 psv2_index[0x18]; 6018 6019 u8 reserved_at_e0[0x8]; 6020 u8 psv3_index[0x18]; 6021 }; 6022 6023 struct mlx5_ifc_create_psv_in_bits { 6024 u8 opcode[0x10]; 6025 u8 reserved_at_10[0x10]; 6026 6027 u8 reserved_at_20[0x10]; 6028 u8 op_mod[0x10]; 6029 6030 u8 num_psv[0x4]; 6031 u8 reserved_at_44[0x4]; 6032 u8 pd[0x18]; 6033 6034 u8 reserved_at_60[0x20]; 6035 }; 6036 6037 struct mlx5_ifc_create_mkey_out_bits { 6038 u8 status[0x8]; 6039 u8 reserved_at_8[0x18]; 6040 6041 u8 syndrome[0x20]; 6042 6043 u8 reserved_at_40[0x8]; 6044 u8 mkey_index[0x18]; 6045 6046 u8 reserved_at_60[0x20]; 6047 }; 6048 6049 struct mlx5_ifc_create_mkey_in_bits { 6050 u8 opcode[0x10]; 6051 u8 reserved_at_10[0x10]; 6052 6053 u8 reserved_at_20[0x10]; 6054 u8 op_mod[0x10]; 6055 6056 u8 reserved_at_40[0x20]; 6057 6058 u8 pg_access[0x1]; 6059 u8 reserved_at_61[0x1f]; 6060 6061 struct mlx5_ifc_mkc_bits memory_key_mkey_entry; 6062 6063 u8 reserved_at_280[0x80]; 6064 6065 u8 translations_octword_actual_size[0x20]; 6066 6067 u8 reserved_at_320[0x560]; 6068 6069 u8 klm_pas_mtt[0][0x20]; 6070 }; 6071 6072 struct mlx5_ifc_create_flow_table_out_bits { 6073 u8 status[0x8]; 6074 u8 reserved_at_8[0x18]; 6075 6076 u8 syndrome[0x20]; 6077 6078 u8 reserved_at_40[0x8]; 6079 u8 table_id[0x18]; 6080 6081 u8 reserved_at_60[0x20]; 6082 }; 6083 6084 struct mlx5_ifc_create_flow_table_in_bits { 6085 u8 opcode[0x10]; 6086 u8 reserved_at_10[0x10]; 6087 6088 u8 reserved_at_20[0x10]; 6089 u8 op_mod[0x10]; 6090 6091 u8 other_vport[0x1]; 6092 u8 reserved_at_41[0xf]; 6093 u8 vport_number[0x10]; 6094 6095 u8 reserved_at_60[0x20]; 6096 6097 u8 table_type[0x8]; 6098 u8 reserved_at_88[0x18]; 6099 6100 u8 reserved_at_a0[0x20]; 6101 6102 u8 reserved_at_c0[0x4]; 6103 u8 table_miss_mode[0x4]; 6104 u8 level[0x8]; 6105 u8 reserved_at_d0[0x8]; 6106 u8 log_size[0x8]; 6107 6108 u8 reserved_at_e0[0x8]; 6109 u8 table_miss_id[0x18]; 6110 6111 u8 reserved_at_100[0x100]; 6112 }; 6113 6114 struct mlx5_ifc_create_flow_group_out_bits { 6115 u8 status[0x8]; 6116 u8 reserved_at_8[0x18]; 6117 6118 u8 syndrome[0x20]; 6119 6120 u8 reserved_at_40[0x8]; 6121 u8 group_id[0x18]; 6122 6123 u8 reserved_at_60[0x20]; 6124 }; 6125 6126 enum { 6127 MLX5_CREATE_FLOW_GROUP_IN_MATCH_CRITERIA_ENABLE_OUTER_HEADERS = 0x0, 6128 MLX5_CREATE_FLOW_GROUP_IN_MATCH_CRITERIA_ENABLE_MISC_PARAMETERS = 0x1, 6129 MLX5_CREATE_FLOW_GROUP_IN_MATCH_CRITERIA_ENABLE_INNER_HEADERS = 0x2, 6130 }; 6131 6132 struct mlx5_ifc_create_flow_group_in_bits { 6133 u8 opcode[0x10]; 6134 u8 reserved_at_10[0x10]; 6135 6136 u8 reserved_at_20[0x10]; 6137 u8 op_mod[0x10]; 6138 6139 u8 other_vport[0x1]; 6140 u8 reserved_at_41[0xf]; 6141 u8 vport_number[0x10]; 6142 6143 u8 reserved_at_60[0x20]; 6144 6145 u8 table_type[0x8]; 6146 u8 reserved_at_88[0x18]; 6147 6148 u8 reserved_at_a0[0x8]; 6149 u8 table_id[0x18]; 6150 6151 u8 reserved_at_c0[0x20]; 6152 6153 u8 start_flow_index[0x20]; 6154 6155 u8 reserved_at_100[0x20]; 6156 6157 u8 end_flow_index[0x20]; 6158 6159 u8 reserved_at_140[0xa0]; 6160 6161 u8 reserved_at_1e0[0x18]; 6162 u8 match_criteria_enable[0x8]; 6163 6164 struct mlx5_ifc_fte_match_param_bits match_criteria; 6165 6166 u8 reserved_at_1200[0xe00]; 6167 }; 6168 6169 struct mlx5_ifc_create_eq_out_bits { 6170 u8 status[0x8]; 6171 u8 reserved_at_8[0x18]; 6172 6173 u8 syndrome[0x20]; 6174 6175 u8 reserved_at_40[0x18]; 6176 u8 eq_number[0x8]; 6177 6178 u8 reserved_at_60[0x20]; 6179 }; 6180 6181 struct mlx5_ifc_create_eq_in_bits { 6182 u8 opcode[0x10]; 6183 u8 reserved_at_10[0x10]; 6184 6185 u8 reserved_at_20[0x10]; 6186 u8 op_mod[0x10]; 6187 6188 u8 reserved_at_40[0x40]; 6189 6190 struct mlx5_ifc_eqc_bits eq_context_entry; 6191 6192 u8 reserved_at_280[0x40]; 6193 6194 u8 event_bitmask[0x40]; 6195 6196 u8 reserved_at_300[0x580]; 6197 6198 u8 pas[0][0x40]; 6199 }; 6200 6201 struct mlx5_ifc_create_dct_out_bits { 6202 u8 status[0x8]; 6203 u8 reserved_at_8[0x18]; 6204 6205 u8 syndrome[0x20]; 6206 6207 u8 reserved_at_40[0x8]; 6208 u8 dctn[0x18]; 6209 6210 u8 reserved_at_60[0x20]; 6211 }; 6212 6213 struct mlx5_ifc_create_dct_in_bits { 6214 u8 opcode[0x10]; 6215 u8 reserved_at_10[0x10]; 6216 6217 u8 reserved_at_20[0x10]; 6218 u8 op_mod[0x10]; 6219 6220 u8 reserved_at_40[0x40]; 6221 6222 struct mlx5_ifc_dctc_bits dct_context_entry; 6223 6224 u8 reserved_at_280[0x180]; 6225 }; 6226 6227 struct mlx5_ifc_create_cq_out_bits { 6228 u8 status[0x8]; 6229 u8 reserved_at_8[0x18]; 6230 6231 u8 syndrome[0x20]; 6232 6233 u8 reserved_at_40[0x8]; 6234 u8 cqn[0x18]; 6235 6236 u8 reserved_at_60[0x20]; 6237 }; 6238 6239 struct mlx5_ifc_create_cq_in_bits { 6240 u8 opcode[0x10]; 6241 u8 reserved_at_10[0x10]; 6242 6243 u8 reserved_at_20[0x10]; 6244 u8 op_mod[0x10]; 6245 6246 u8 reserved_at_40[0x40]; 6247 6248 struct mlx5_ifc_cqc_bits cq_context; 6249 6250 u8 reserved_at_280[0x600]; 6251 6252 u8 pas[0][0x40]; 6253 }; 6254 6255 struct mlx5_ifc_config_int_moderation_out_bits { 6256 u8 status[0x8]; 6257 u8 reserved_at_8[0x18]; 6258 6259 u8 syndrome[0x20]; 6260 6261 u8 reserved_at_40[0x4]; 6262 u8 min_delay[0xc]; 6263 u8 int_vector[0x10]; 6264 6265 u8 reserved_at_60[0x20]; 6266 }; 6267 6268 enum { 6269 MLX5_CONFIG_INT_MODERATION_IN_OP_MOD_WRITE = 0x0, 6270 MLX5_CONFIG_INT_MODERATION_IN_OP_MOD_READ = 0x1, 6271 }; 6272 6273 struct mlx5_ifc_config_int_moderation_in_bits { 6274 u8 opcode[0x10]; 6275 u8 reserved_at_10[0x10]; 6276 6277 u8 reserved_at_20[0x10]; 6278 u8 op_mod[0x10]; 6279 6280 u8 reserved_at_40[0x4]; 6281 u8 min_delay[0xc]; 6282 u8 int_vector[0x10]; 6283 6284 u8 reserved_at_60[0x20]; 6285 }; 6286 6287 struct mlx5_ifc_attach_to_mcg_out_bits { 6288 u8 status[0x8]; 6289 u8 reserved_at_8[0x18]; 6290 6291 u8 syndrome[0x20]; 6292 6293 u8 reserved_at_40[0x40]; 6294 }; 6295 6296 struct mlx5_ifc_attach_to_mcg_in_bits { 6297 u8 opcode[0x10]; 6298 u8 reserved_at_10[0x10]; 6299 6300 u8 reserved_at_20[0x10]; 6301 u8 op_mod[0x10]; 6302 6303 u8 reserved_at_40[0x8]; 6304 u8 qpn[0x18]; 6305 6306 u8 reserved_at_60[0x20]; 6307 6308 u8 multicast_gid[16][0x8]; 6309 }; 6310 6311 struct mlx5_ifc_arm_xrq_out_bits { 6312 u8 status[0x8]; 6313 u8 reserved_at_8[0x18]; 6314 6315 u8 syndrome[0x20]; 6316 6317 u8 reserved_at_40[0x40]; 6318 }; 6319 6320 struct mlx5_ifc_arm_xrq_in_bits { 6321 u8 opcode[0x10]; 6322 u8 reserved_at_10[0x10]; 6323 6324 u8 reserved_at_20[0x10]; 6325 u8 op_mod[0x10]; 6326 6327 u8 reserved_at_40[0x8]; 6328 u8 xrqn[0x18]; 6329 6330 u8 reserved_at_60[0x10]; 6331 u8 lwm[0x10]; 6332 }; 6333 6334 struct mlx5_ifc_arm_xrc_srq_out_bits { 6335 u8 status[0x8]; 6336 u8 reserved_at_8[0x18]; 6337 6338 u8 syndrome[0x20]; 6339 6340 u8 reserved_at_40[0x40]; 6341 }; 6342 6343 enum { 6344 MLX5_ARM_XRC_SRQ_IN_OP_MOD_XRC_SRQ = 0x1, 6345 }; 6346 6347 struct mlx5_ifc_arm_xrc_srq_in_bits { 6348 u8 opcode[0x10]; 6349 u8 reserved_at_10[0x10]; 6350 6351 u8 reserved_at_20[0x10]; 6352 u8 op_mod[0x10]; 6353 6354 u8 reserved_at_40[0x8]; 6355 u8 xrc_srqn[0x18]; 6356 6357 u8 reserved_at_60[0x10]; 6358 u8 lwm[0x10]; 6359 }; 6360 6361 struct mlx5_ifc_arm_rq_out_bits { 6362 u8 status[0x8]; 6363 u8 reserved_at_8[0x18]; 6364 6365 u8 syndrome[0x20]; 6366 6367 u8 reserved_at_40[0x40]; 6368 }; 6369 6370 enum { 6371 MLX5_ARM_RQ_IN_OP_MOD_SRQ = 0x1, 6372 MLX5_ARM_RQ_IN_OP_MOD_XRQ = 0x2, 6373 }; 6374 6375 struct mlx5_ifc_arm_rq_in_bits { 6376 u8 opcode[0x10]; 6377 u8 reserved_at_10[0x10]; 6378 6379 u8 reserved_at_20[0x10]; 6380 u8 op_mod[0x10]; 6381 6382 u8 reserved_at_40[0x8]; 6383 u8 srq_number[0x18]; 6384 6385 u8 reserved_at_60[0x10]; 6386 u8 lwm[0x10]; 6387 }; 6388 6389 struct mlx5_ifc_arm_dct_out_bits { 6390 u8 status[0x8]; 6391 u8 reserved_at_8[0x18]; 6392 6393 u8 syndrome[0x20]; 6394 6395 u8 reserved_at_40[0x40]; 6396 }; 6397 6398 struct mlx5_ifc_arm_dct_in_bits { 6399 u8 opcode[0x10]; 6400 u8 reserved_at_10[0x10]; 6401 6402 u8 reserved_at_20[0x10]; 6403 u8 op_mod[0x10]; 6404 6405 u8 reserved_at_40[0x8]; 6406 u8 dct_number[0x18]; 6407 6408 u8 reserved_at_60[0x20]; 6409 }; 6410 6411 struct mlx5_ifc_alloc_xrcd_out_bits { 6412 u8 status[0x8]; 6413 u8 reserved_at_8[0x18]; 6414 6415 u8 syndrome[0x20]; 6416 6417 u8 reserved_at_40[0x8]; 6418 u8 xrcd[0x18]; 6419 6420 u8 reserved_at_60[0x20]; 6421 }; 6422 6423 struct mlx5_ifc_alloc_xrcd_in_bits { 6424 u8 opcode[0x10]; 6425 u8 reserved_at_10[0x10]; 6426 6427 u8 reserved_at_20[0x10]; 6428 u8 op_mod[0x10]; 6429 6430 u8 reserved_at_40[0x40]; 6431 }; 6432 6433 struct mlx5_ifc_alloc_uar_out_bits { 6434 u8 status[0x8]; 6435 u8 reserved_at_8[0x18]; 6436 6437 u8 syndrome[0x20]; 6438 6439 u8 reserved_at_40[0x8]; 6440 u8 uar[0x18]; 6441 6442 u8 reserved_at_60[0x20]; 6443 }; 6444 6445 struct mlx5_ifc_alloc_uar_in_bits { 6446 u8 opcode[0x10]; 6447 u8 reserved_at_10[0x10]; 6448 6449 u8 reserved_at_20[0x10]; 6450 u8 op_mod[0x10]; 6451 6452 u8 reserved_at_40[0x40]; 6453 }; 6454 6455 struct mlx5_ifc_alloc_transport_domain_out_bits { 6456 u8 status[0x8]; 6457 u8 reserved_at_8[0x18]; 6458 6459 u8 syndrome[0x20]; 6460 6461 u8 reserved_at_40[0x8]; 6462 u8 transport_domain[0x18]; 6463 6464 u8 reserved_at_60[0x20]; 6465 }; 6466 6467 struct mlx5_ifc_alloc_transport_domain_in_bits { 6468 u8 opcode[0x10]; 6469 u8 reserved_at_10[0x10]; 6470 6471 u8 reserved_at_20[0x10]; 6472 u8 op_mod[0x10]; 6473 6474 u8 reserved_at_40[0x40]; 6475 }; 6476 6477 struct mlx5_ifc_alloc_q_counter_out_bits { 6478 u8 status[0x8]; 6479 u8 reserved_at_8[0x18]; 6480 6481 u8 syndrome[0x20]; 6482 6483 u8 reserved_at_40[0x18]; 6484 u8 counter_set_id[0x8]; 6485 6486 u8 reserved_at_60[0x20]; 6487 }; 6488 6489 struct mlx5_ifc_alloc_q_counter_in_bits { 6490 u8 opcode[0x10]; 6491 u8 reserved_at_10[0x10]; 6492 6493 u8 reserved_at_20[0x10]; 6494 u8 op_mod[0x10]; 6495 6496 u8 reserved_at_40[0x40]; 6497 }; 6498 6499 struct mlx5_ifc_alloc_pd_out_bits { 6500 u8 status[0x8]; 6501 u8 reserved_at_8[0x18]; 6502 6503 u8 syndrome[0x20]; 6504 6505 u8 reserved_at_40[0x8]; 6506 u8 pd[0x18]; 6507 6508 u8 reserved_at_60[0x20]; 6509 }; 6510 6511 struct mlx5_ifc_alloc_pd_in_bits { 6512 u8 opcode[0x10]; 6513 u8 reserved_at_10[0x10]; 6514 6515 u8 reserved_at_20[0x10]; 6516 u8 op_mod[0x10]; 6517 6518 u8 reserved_at_40[0x40]; 6519 }; 6520 6521 struct mlx5_ifc_alloc_flow_counter_out_bits { 6522 u8 status[0x8]; 6523 u8 reserved_at_8[0x18]; 6524 6525 u8 syndrome[0x20]; 6526 6527 u8 reserved_at_40[0x10]; 6528 u8 flow_counter_id[0x10]; 6529 6530 u8 reserved_at_60[0x20]; 6531 }; 6532 6533 struct mlx5_ifc_alloc_flow_counter_in_bits { 6534 u8 opcode[0x10]; 6535 u8 reserved_at_10[0x10]; 6536 6537 u8 reserved_at_20[0x10]; 6538 u8 op_mod[0x10]; 6539 6540 u8 reserved_at_40[0x40]; 6541 }; 6542 6543 struct mlx5_ifc_add_vxlan_udp_dport_out_bits { 6544 u8 status[0x8]; 6545 u8 reserved_at_8[0x18]; 6546 6547 u8 syndrome[0x20]; 6548 6549 u8 reserved_at_40[0x40]; 6550 }; 6551 6552 struct mlx5_ifc_add_vxlan_udp_dport_in_bits { 6553 u8 opcode[0x10]; 6554 u8 reserved_at_10[0x10]; 6555 6556 u8 reserved_at_20[0x10]; 6557 u8 op_mod[0x10]; 6558 6559 u8 reserved_at_40[0x20]; 6560 6561 u8 reserved_at_60[0x10]; 6562 u8 vxlan_udp_port[0x10]; 6563 }; 6564 6565 struct mlx5_ifc_set_rate_limit_out_bits { 6566 u8 status[0x8]; 6567 u8 reserved_at_8[0x18]; 6568 6569 u8 syndrome[0x20]; 6570 6571 u8 reserved_at_40[0x40]; 6572 }; 6573 6574 struct mlx5_ifc_set_rate_limit_in_bits { 6575 u8 opcode[0x10]; 6576 u8 reserved_at_10[0x10]; 6577 6578 u8 reserved_at_20[0x10]; 6579 u8 op_mod[0x10]; 6580 6581 u8 reserved_at_40[0x10]; 6582 u8 rate_limit_index[0x10]; 6583 6584 u8 reserved_at_60[0x20]; 6585 6586 u8 rate_limit[0x20]; 6587 }; 6588 6589 struct mlx5_ifc_access_register_out_bits { 6590 u8 status[0x8]; 6591 u8 reserved_at_8[0x18]; 6592 6593 u8 syndrome[0x20]; 6594 6595 u8 reserved_at_40[0x40]; 6596 6597 u8 register_data[0][0x20]; 6598 }; 6599 6600 enum { 6601 MLX5_ACCESS_REGISTER_IN_OP_MOD_WRITE = 0x0, 6602 MLX5_ACCESS_REGISTER_IN_OP_MOD_READ = 0x1, 6603 }; 6604 6605 struct mlx5_ifc_access_register_in_bits { 6606 u8 opcode[0x10]; 6607 u8 reserved_at_10[0x10]; 6608 6609 u8 reserved_at_20[0x10]; 6610 u8 op_mod[0x10]; 6611 6612 u8 reserved_at_40[0x10]; 6613 u8 register_id[0x10]; 6614 6615 u8 argument[0x20]; 6616 6617 u8 register_data[0][0x20]; 6618 }; 6619 6620 struct mlx5_ifc_sltp_reg_bits { 6621 u8 status[0x4]; 6622 u8 version[0x4]; 6623 u8 local_port[0x8]; 6624 u8 pnat[0x2]; 6625 u8 reserved_at_12[0x2]; 6626 u8 lane[0x4]; 6627 u8 reserved_at_18[0x8]; 6628 6629 u8 reserved_at_20[0x20]; 6630 6631 u8 reserved_at_40[0x7]; 6632 u8 polarity[0x1]; 6633 u8 ob_tap0[0x8]; 6634 u8 ob_tap1[0x8]; 6635 u8 ob_tap2[0x8]; 6636 6637 u8 reserved_at_60[0xc]; 6638 u8 ob_preemp_mode[0x4]; 6639 u8 ob_reg[0x8]; 6640 u8 ob_bias[0x8]; 6641 6642 u8 reserved_at_80[0x20]; 6643 }; 6644 6645 struct mlx5_ifc_slrg_reg_bits { 6646 u8 status[0x4]; 6647 u8 version[0x4]; 6648 u8 local_port[0x8]; 6649 u8 pnat[0x2]; 6650 u8 reserved_at_12[0x2]; 6651 u8 lane[0x4]; 6652 u8 reserved_at_18[0x8]; 6653 6654 u8 time_to_link_up[0x10]; 6655 u8 reserved_at_30[0xc]; 6656 u8 grade_lane_speed[0x4]; 6657 6658 u8 grade_version[0x8]; 6659 u8 grade[0x18]; 6660 6661 u8 reserved_at_60[0x4]; 6662 u8 height_grade_type[0x4]; 6663 u8 height_grade[0x18]; 6664 6665 u8 height_dz[0x10]; 6666 u8 height_dv[0x10]; 6667 6668 u8 reserved_at_a0[0x10]; 6669 u8 height_sigma[0x10]; 6670 6671 u8 reserved_at_c0[0x20]; 6672 6673 u8 reserved_at_e0[0x4]; 6674 u8 phase_grade_type[0x4]; 6675 u8 phase_grade[0x18]; 6676 6677 u8 reserved_at_100[0x8]; 6678 u8 phase_eo_pos[0x8]; 6679 u8 reserved_at_110[0x8]; 6680 u8 phase_eo_neg[0x8]; 6681 6682 u8 ffe_set_tested[0x10]; 6683 u8 test_errors_per_lane[0x10]; 6684 }; 6685 6686 struct mlx5_ifc_pvlc_reg_bits { 6687 u8 reserved_at_0[0x8]; 6688 u8 local_port[0x8]; 6689 u8 reserved_at_10[0x10]; 6690 6691 u8 reserved_at_20[0x1c]; 6692 u8 vl_hw_cap[0x4]; 6693 6694 u8 reserved_at_40[0x1c]; 6695 u8 vl_admin[0x4]; 6696 6697 u8 reserved_at_60[0x1c]; 6698 u8 vl_operational[0x4]; 6699 }; 6700 6701 struct mlx5_ifc_pude_reg_bits { 6702 u8 swid[0x8]; 6703 u8 local_port[0x8]; 6704 u8 reserved_at_10[0x4]; 6705 u8 admin_status[0x4]; 6706 u8 reserved_at_18[0x4]; 6707 u8 oper_status[0x4]; 6708 6709 u8 reserved_at_20[0x60]; 6710 }; 6711 6712 struct mlx5_ifc_ptys_reg_bits { 6713 u8 an_disable_cap[0x1]; 6714 u8 an_disable_admin[0x1]; 6715 u8 reserved_at_2[0x6]; 6716 u8 local_port[0x8]; 6717 u8 reserved_at_10[0xd]; 6718 u8 proto_mask[0x3]; 6719 6720 u8 an_status[0x4]; 6721 u8 reserved_at_24[0x3c]; 6722 6723 u8 eth_proto_capability[0x20]; 6724 6725 u8 ib_link_width_capability[0x10]; 6726 u8 ib_proto_capability[0x10]; 6727 6728 u8 reserved_at_a0[0x20]; 6729 6730 u8 eth_proto_admin[0x20]; 6731 6732 u8 ib_link_width_admin[0x10]; 6733 u8 ib_proto_admin[0x10]; 6734 6735 u8 reserved_at_100[0x20]; 6736 6737 u8 eth_proto_oper[0x20]; 6738 6739 u8 ib_link_width_oper[0x10]; 6740 u8 ib_proto_oper[0x10]; 6741 6742 u8 reserved_at_160[0x20]; 6743 6744 u8 eth_proto_lp_advertise[0x20]; 6745 6746 u8 reserved_at_1a0[0x60]; 6747 }; 6748 6749 struct mlx5_ifc_mlcr_reg_bits { 6750 u8 reserved_at_0[0x8]; 6751 u8 local_port[0x8]; 6752 u8 reserved_at_10[0x20]; 6753 6754 u8 beacon_duration[0x10]; 6755 u8 reserved_at_40[0x10]; 6756 6757 u8 beacon_remain[0x10]; 6758 }; 6759 6760 struct mlx5_ifc_ptas_reg_bits { 6761 u8 reserved_at_0[0x20]; 6762 6763 u8 algorithm_options[0x10]; 6764 u8 reserved_at_30[0x4]; 6765 u8 repetitions_mode[0x4]; 6766 u8 num_of_repetitions[0x8]; 6767 6768 u8 grade_version[0x8]; 6769 u8 height_grade_type[0x4]; 6770 u8 phase_grade_type[0x4]; 6771 u8 height_grade_weight[0x8]; 6772 u8 phase_grade_weight[0x8]; 6773 6774 u8 gisim_measure_bits[0x10]; 6775 u8 adaptive_tap_measure_bits[0x10]; 6776 6777 u8 ber_bath_high_error_threshold[0x10]; 6778 u8 ber_bath_mid_error_threshold[0x10]; 6779 6780 u8 ber_bath_low_error_threshold[0x10]; 6781 u8 one_ratio_high_threshold[0x10]; 6782 6783 u8 one_ratio_high_mid_threshold[0x10]; 6784 u8 one_ratio_low_mid_threshold[0x10]; 6785 6786 u8 one_ratio_low_threshold[0x10]; 6787 u8 ndeo_error_threshold[0x10]; 6788 6789 u8 mixer_offset_step_size[0x10]; 6790 u8 reserved_at_110[0x8]; 6791 u8 mix90_phase_for_voltage_bath[0x8]; 6792 6793 u8 mixer_offset_start[0x10]; 6794 u8 mixer_offset_end[0x10]; 6795 6796 u8 reserved_at_140[0x15]; 6797 u8 ber_test_time[0xb]; 6798 }; 6799 6800 struct mlx5_ifc_pspa_reg_bits { 6801 u8 swid[0x8]; 6802 u8 local_port[0x8]; 6803 u8 sub_port[0x8]; 6804 u8 reserved_at_18[0x8]; 6805 6806 u8 reserved_at_20[0x20]; 6807 }; 6808 6809 struct mlx5_ifc_pqdr_reg_bits { 6810 u8 reserved_at_0[0x8]; 6811 u8 local_port[0x8]; 6812 u8 reserved_at_10[0x5]; 6813 u8 prio[0x3]; 6814 u8 reserved_at_18[0x6]; 6815 u8 mode[0x2]; 6816 6817 u8 reserved_at_20[0x20]; 6818 6819 u8 reserved_at_40[0x10]; 6820 u8 min_threshold[0x10]; 6821 6822 u8 reserved_at_60[0x10]; 6823 u8 max_threshold[0x10]; 6824 6825 u8 reserved_at_80[0x10]; 6826 u8 mark_probability_denominator[0x10]; 6827 6828 u8 reserved_at_a0[0x60]; 6829 }; 6830 6831 struct mlx5_ifc_ppsc_reg_bits { 6832 u8 reserved_at_0[0x8]; 6833 u8 local_port[0x8]; 6834 u8 reserved_at_10[0x10]; 6835 6836 u8 reserved_at_20[0x60]; 6837 6838 u8 reserved_at_80[0x1c]; 6839 u8 wrps_admin[0x4]; 6840 6841 u8 reserved_at_a0[0x1c]; 6842 u8 wrps_status[0x4]; 6843 6844 u8 reserved_at_c0[0x8]; 6845 u8 up_threshold[0x8]; 6846 u8 reserved_at_d0[0x8]; 6847 u8 down_threshold[0x8]; 6848 6849 u8 reserved_at_e0[0x20]; 6850 6851 u8 reserved_at_100[0x1c]; 6852 u8 srps_admin[0x4]; 6853 6854 u8 reserved_at_120[0x1c]; 6855 u8 srps_status[0x4]; 6856 6857 u8 reserved_at_140[0x40]; 6858 }; 6859 6860 struct mlx5_ifc_pplr_reg_bits { 6861 u8 reserved_at_0[0x8]; 6862 u8 local_port[0x8]; 6863 u8 reserved_at_10[0x10]; 6864 6865 u8 reserved_at_20[0x8]; 6866 u8 lb_cap[0x8]; 6867 u8 reserved_at_30[0x8]; 6868 u8 lb_en[0x8]; 6869 }; 6870 6871 struct mlx5_ifc_pplm_reg_bits { 6872 u8 reserved_at_0[0x8]; 6873 u8 local_port[0x8]; 6874 u8 reserved_at_10[0x10]; 6875 6876 u8 reserved_at_20[0x20]; 6877 6878 u8 port_profile_mode[0x8]; 6879 u8 static_port_profile[0x8]; 6880 u8 active_port_profile[0x8]; 6881 u8 reserved_at_58[0x8]; 6882 6883 u8 retransmission_active[0x8]; 6884 u8 fec_mode_active[0x18]; 6885 6886 u8 reserved_at_80[0x20]; 6887 }; 6888 6889 struct mlx5_ifc_ppcnt_reg_bits { 6890 u8 swid[0x8]; 6891 u8 local_port[0x8]; 6892 u8 pnat[0x2]; 6893 u8 reserved_at_12[0x8]; 6894 u8 grp[0x6]; 6895 6896 u8 clr[0x1]; 6897 u8 reserved_at_21[0x1c]; 6898 u8 prio_tc[0x3]; 6899 6900 union mlx5_ifc_eth_cntrs_grp_data_layout_auto_bits counter_set; 6901 }; 6902 6903 struct mlx5_ifc_ppad_reg_bits { 6904 u8 reserved_at_0[0x3]; 6905 u8 single_mac[0x1]; 6906 u8 reserved_at_4[0x4]; 6907 u8 local_port[0x8]; 6908 u8 mac_47_32[0x10]; 6909 6910 u8 mac_31_0[0x20]; 6911 6912 u8 reserved_at_40[0x40]; 6913 }; 6914 6915 struct mlx5_ifc_pmtu_reg_bits { 6916 u8 reserved_at_0[0x8]; 6917 u8 local_port[0x8]; 6918 u8 reserved_at_10[0x10]; 6919 6920 u8 max_mtu[0x10]; 6921 u8 reserved_at_30[0x10]; 6922 6923 u8 admin_mtu[0x10]; 6924 u8 reserved_at_50[0x10]; 6925 6926 u8 oper_mtu[0x10]; 6927 u8 reserved_at_70[0x10]; 6928 }; 6929 6930 struct mlx5_ifc_pmpr_reg_bits { 6931 u8 reserved_at_0[0x8]; 6932 u8 module[0x8]; 6933 u8 reserved_at_10[0x10]; 6934 6935 u8 reserved_at_20[0x18]; 6936 u8 attenuation_5g[0x8]; 6937 6938 u8 reserved_at_40[0x18]; 6939 u8 attenuation_7g[0x8]; 6940 6941 u8 reserved_at_60[0x18]; 6942 u8 attenuation_12g[0x8]; 6943 }; 6944 6945 struct mlx5_ifc_pmpe_reg_bits { 6946 u8 reserved_at_0[0x8]; 6947 u8 module[0x8]; 6948 u8 reserved_at_10[0xc]; 6949 u8 module_status[0x4]; 6950 6951 u8 reserved_at_20[0x60]; 6952 }; 6953 6954 struct mlx5_ifc_pmpc_reg_bits { 6955 u8 module_state_updated[32][0x8]; 6956 }; 6957 6958 struct mlx5_ifc_pmlpn_reg_bits { 6959 u8 reserved_at_0[0x4]; 6960 u8 mlpn_status[0x4]; 6961 u8 local_port[0x8]; 6962 u8 reserved_at_10[0x10]; 6963 6964 u8 e[0x1]; 6965 u8 reserved_at_21[0x1f]; 6966 }; 6967 6968 struct mlx5_ifc_pmlp_reg_bits { 6969 u8 rxtx[0x1]; 6970 u8 reserved_at_1[0x7]; 6971 u8 local_port[0x8]; 6972 u8 reserved_at_10[0x8]; 6973 u8 width[0x8]; 6974 6975 u8 lane0_module_mapping[0x20]; 6976 6977 u8 lane1_module_mapping[0x20]; 6978 6979 u8 lane2_module_mapping[0x20]; 6980 6981 u8 lane3_module_mapping[0x20]; 6982 6983 u8 reserved_at_a0[0x160]; 6984 }; 6985 6986 struct mlx5_ifc_pmaos_reg_bits { 6987 u8 reserved_at_0[0x8]; 6988 u8 module[0x8]; 6989 u8 reserved_at_10[0x4]; 6990 u8 admin_status[0x4]; 6991 u8 reserved_at_18[0x4]; 6992 u8 oper_status[0x4]; 6993 6994 u8 ase[0x1]; 6995 u8 ee[0x1]; 6996 u8 reserved_at_22[0x1c]; 6997 u8 e[0x2]; 6998 6999 u8 reserved_at_40[0x40]; 7000 }; 7001 7002 struct mlx5_ifc_plpc_reg_bits { 7003 u8 reserved_at_0[0x4]; 7004 u8 profile_id[0xc]; 7005 u8 reserved_at_10[0x4]; 7006 u8 proto_mask[0x4]; 7007 u8 reserved_at_18[0x8]; 7008 7009 u8 reserved_at_20[0x10]; 7010 u8 lane_speed[0x10]; 7011 7012 u8 reserved_at_40[0x17]; 7013 u8 lpbf[0x1]; 7014 u8 fec_mode_policy[0x8]; 7015 7016 u8 retransmission_capability[0x8]; 7017 u8 fec_mode_capability[0x18]; 7018 7019 u8 retransmission_support_admin[0x8]; 7020 u8 fec_mode_support_admin[0x18]; 7021 7022 u8 retransmission_request_admin[0x8]; 7023 u8 fec_mode_request_admin[0x18]; 7024 7025 u8 reserved_at_c0[0x80]; 7026 }; 7027 7028 struct mlx5_ifc_plib_reg_bits { 7029 u8 reserved_at_0[0x8]; 7030 u8 local_port[0x8]; 7031 u8 reserved_at_10[0x8]; 7032 u8 ib_port[0x8]; 7033 7034 u8 reserved_at_20[0x60]; 7035 }; 7036 7037 struct mlx5_ifc_plbf_reg_bits { 7038 u8 reserved_at_0[0x8]; 7039 u8 local_port[0x8]; 7040 u8 reserved_at_10[0xd]; 7041 u8 lbf_mode[0x3]; 7042 7043 u8 reserved_at_20[0x20]; 7044 }; 7045 7046 struct mlx5_ifc_pipg_reg_bits { 7047 u8 reserved_at_0[0x8]; 7048 u8 local_port[0x8]; 7049 u8 reserved_at_10[0x10]; 7050 7051 u8 dic[0x1]; 7052 u8 reserved_at_21[0x19]; 7053 u8 ipg[0x4]; 7054 u8 reserved_at_3e[0x2]; 7055 }; 7056 7057 struct mlx5_ifc_pifr_reg_bits { 7058 u8 reserved_at_0[0x8]; 7059 u8 local_port[0x8]; 7060 u8 reserved_at_10[0x10]; 7061 7062 u8 reserved_at_20[0xe0]; 7063 7064 u8 port_filter[8][0x20]; 7065 7066 u8 port_filter_update_en[8][0x20]; 7067 }; 7068 7069 struct mlx5_ifc_pfcc_reg_bits { 7070 u8 reserved_at_0[0x8]; 7071 u8 local_port[0x8]; 7072 u8 reserved_at_10[0x10]; 7073 7074 u8 ppan[0x4]; 7075 u8 reserved_at_24[0x4]; 7076 u8 prio_mask_tx[0x8]; 7077 u8 reserved_at_30[0x8]; 7078 u8 prio_mask_rx[0x8]; 7079 7080 u8 pptx[0x1]; 7081 u8 aptx[0x1]; 7082 u8 reserved_at_42[0x6]; 7083 u8 pfctx[0x8]; 7084 u8 reserved_at_50[0x10]; 7085 7086 u8 pprx[0x1]; 7087 u8 aprx[0x1]; 7088 u8 reserved_at_62[0x6]; 7089 u8 pfcrx[0x8]; 7090 u8 reserved_at_70[0x10]; 7091 7092 u8 reserved_at_80[0x80]; 7093 }; 7094 7095 struct mlx5_ifc_pelc_reg_bits { 7096 u8 op[0x4]; 7097 u8 reserved_at_4[0x4]; 7098 u8 local_port[0x8]; 7099 u8 reserved_at_10[0x10]; 7100 7101 u8 op_admin[0x8]; 7102 u8 op_capability[0x8]; 7103 u8 op_request[0x8]; 7104 u8 op_active[0x8]; 7105 7106 u8 admin[0x40]; 7107 7108 u8 capability[0x40]; 7109 7110 u8 request[0x40]; 7111 7112 u8 active[0x40]; 7113 7114 u8 reserved_at_140[0x80]; 7115 }; 7116 7117 struct mlx5_ifc_peir_reg_bits { 7118 u8 reserved_at_0[0x8]; 7119 u8 local_port[0x8]; 7120 u8 reserved_at_10[0x10]; 7121 7122 u8 reserved_at_20[0xc]; 7123 u8 error_count[0x4]; 7124 u8 reserved_at_30[0x10]; 7125 7126 u8 reserved_at_40[0xc]; 7127 u8 lane[0x4]; 7128 u8 reserved_at_50[0x8]; 7129 u8 error_type[0x8]; 7130 }; 7131 7132 struct mlx5_ifc_pcap_reg_bits { 7133 u8 reserved_at_0[0x8]; 7134 u8 local_port[0x8]; 7135 u8 reserved_at_10[0x10]; 7136 7137 u8 port_capability_mask[4][0x20]; 7138 }; 7139 7140 struct mlx5_ifc_paos_reg_bits { 7141 u8 swid[0x8]; 7142 u8 local_port[0x8]; 7143 u8 reserved_at_10[0x4]; 7144 u8 admin_status[0x4]; 7145 u8 reserved_at_18[0x4]; 7146 u8 oper_status[0x4]; 7147 7148 u8 ase[0x1]; 7149 u8 ee[0x1]; 7150 u8 reserved_at_22[0x1c]; 7151 u8 e[0x2]; 7152 7153 u8 reserved_at_40[0x40]; 7154 }; 7155 7156 struct mlx5_ifc_pamp_reg_bits { 7157 u8 reserved_at_0[0x8]; 7158 u8 opamp_group[0x8]; 7159 u8 reserved_at_10[0xc]; 7160 u8 opamp_group_type[0x4]; 7161 7162 u8 start_index[0x10]; 7163 u8 reserved_at_30[0x4]; 7164 u8 num_of_indices[0xc]; 7165 7166 u8 index_data[18][0x10]; 7167 }; 7168 7169 struct mlx5_ifc_pcmr_reg_bits { 7170 u8 reserved_at_0[0x8]; 7171 u8 local_port[0x8]; 7172 u8 reserved_at_10[0x2e]; 7173 u8 fcs_cap[0x1]; 7174 u8 reserved_at_3f[0x1f]; 7175 u8 fcs_chk[0x1]; 7176 u8 reserved_at_5f[0x1]; 7177 }; 7178 7179 struct mlx5_ifc_lane_2_module_mapping_bits { 7180 u8 reserved_at_0[0x6]; 7181 u8 rx_lane[0x2]; 7182 u8 reserved_at_8[0x6]; 7183 u8 tx_lane[0x2]; 7184 u8 reserved_at_10[0x8]; 7185 u8 module[0x8]; 7186 }; 7187 7188 struct mlx5_ifc_bufferx_reg_bits { 7189 u8 reserved_at_0[0x6]; 7190 u8 lossy[0x1]; 7191 u8 epsb[0x1]; 7192 u8 reserved_at_8[0xc]; 7193 u8 size[0xc]; 7194 7195 u8 xoff_threshold[0x10]; 7196 u8 xon_threshold[0x10]; 7197 }; 7198 7199 struct mlx5_ifc_set_node_in_bits { 7200 u8 node_description[64][0x8]; 7201 }; 7202 7203 struct mlx5_ifc_register_power_settings_bits { 7204 u8 reserved_at_0[0x18]; 7205 u8 power_settings_level[0x8]; 7206 7207 u8 reserved_at_20[0x60]; 7208 }; 7209 7210 struct mlx5_ifc_register_host_endianness_bits { 7211 u8 he[0x1]; 7212 u8 reserved_at_1[0x1f]; 7213 7214 u8 reserved_at_20[0x60]; 7215 }; 7216 7217 struct mlx5_ifc_umr_pointer_desc_argument_bits { 7218 u8 reserved_at_0[0x20]; 7219 7220 u8 mkey[0x20]; 7221 7222 u8 addressh_63_32[0x20]; 7223 7224 u8 addressl_31_0[0x20]; 7225 }; 7226 7227 struct mlx5_ifc_ud_adrs_vector_bits { 7228 u8 dc_key[0x40]; 7229 7230 u8 ext[0x1]; 7231 u8 reserved_at_41[0x7]; 7232 u8 destination_qp_dct[0x18]; 7233 7234 u8 static_rate[0x4]; 7235 u8 sl_eth_prio[0x4]; 7236 u8 fl[0x1]; 7237 u8 mlid[0x7]; 7238 u8 rlid_udp_sport[0x10]; 7239 7240 u8 reserved_at_80[0x20]; 7241 7242 u8 rmac_47_16[0x20]; 7243 7244 u8 rmac_15_0[0x10]; 7245 u8 tclass[0x8]; 7246 u8 hop_limit[0x8]; 7247 7248 u8 reserved_at_e0[0x1]; 7249 u8 grh[0x1]; 7250 u8 reserved_at_e2[0x2]; 7251 u8 src_addr_index[0x8]; 7252 u8 flow_label[0x14]; 7253 7254 u8 rgid_rip[16][0x8]; 7255 }; 7256 7257 struct mlx5_ifc_pages_req_event_bits { 7258 u8 reserved_at_0[0x10]; 7259 u8 function_id[0x10]; 7260 7261 u8 num_pages[0x20]; 7262 7263 u8 reserved_at_40[0xa0]; 7264 }; 7265 7266 struct mlx5_ifc_eqe_bits { 7267 u8 reserved_at_0[0x8]; 7268 u8 event_type[0x8]; 7269 u8 reserved_at_10[0x8]; 7270 u8 event_sub_type[0x8]; 7271 7272 u8 reserved_at_20[0xe0]; 7273 7274 union mlx5_ifc_event_auto_bits event_data; 7275 7276 u8 reserved_at_1e0[0x10]; 7277 u8 signature[0x8]; 7278 u8 reserved_at_1f8[0x7]; 7279 u8 owner[0x1]; 7280 }; 7281 7282 enum { 7283 MLX5_CMD_QUEUE_ENTRY_TYPE_PCIE_CMD_IF_TRANSPORT = 0x7, 7284 }; 7285 7286 struct mlx5_ifc_cmd_queue_entry_bits { 7287 u8 type[0x8]; 7288 u8 reserved_at_8[0x18]; 7289 7290 u8 input_length[0x20]; 7291 7292 u8 input_mailbox_pointer_63_32[0x20]; 7293 7294 u8 input_mailbox_pointer_31_9[0x17]; 7295 u8 reserved_at_77[0x9]; 7296 7297 u8 command_input_inline_data[16][0x8]; 7298 7299 u8 command_output_inline_data[16][0x8]; 7300 7301 u8 output_mailbox_pointer_63_32[0x20]; 7302 7303 u8 output_mailbox_pointer_31_9[0x17]; 7304 u8 reserved_at_1b7[0x9]; 7305 7306 u8 output_length[0x20]; 7307 7308 u8 token[0x8]; 7309 u8 signature[0x8]; 7310 u8 reserved_at_1f0[0x8]; 7311 u8 status[0x7]; 7312 u8 ownership[0x1]; 7313 }; 7314 7315 struct mlx5_ifc_cmd_out_bits { 7316 u8 status[0x8]; 7317 u8 reserved_at_8[0x18]; 7318 7319 u8 syndrome[0x20]; 7320 7321 u8 command_output[0x20]; 7322 }; 7323 7324 struct mlx5_ifc_cmd_in_bits { 7325 u8 opcode[0x10]; 7326 u8 reserved_at_10[0x10]; 7327 7328 u8 reserved_at_20[0x10]; 7329 u8 op_mod[0x10]; 7330 7331 u8 command[0][0x20]; 7332 }; 7333 7334 struct mlx5_ifc_cmd_if_box_bits { 7335 u8 mailbox_data[512][0x8]; 7336 7337 u8 reserved_at_1000[0x180]; 7338 7339 u8 next_pointer_63_32[0x20]; 7340 7341 u8 next_pointer_31_10[0x16]; 7342 u8 reserved_at_11b6[0xa]; 7343 7344 u8 block_number[0x20]; 7345 7346 u8 reserved_at_11e0[0x8]; 7347 u8 token[0x8]; 7348 u8 ctrl_signature[0x8]; 7349 u8 signature[0x8]; 7350 }; 7351 7352 struct mlx5_ifc_mtt_bits { 7353 u8 ptag_63_32[0x20]; 7354 7355 u8 ptag_31_8[0x18]; 7356 u8 reserved_at_38[0x6]; 7357 u8 wr_en[0x1]; 7358 u8 rd_en[0x1]; 7359 }; 7360 7361 struct mlx5_ifc_query_wol_rol_out_bits { 7362 u8 status[0x8]; 7363 u8 reserved_at_8[0x18]; 7364 7365 u8 syndrome[0x20]; 7366 7367 u8 reserved_at_40[0x10]; 7368 u8 rol_mode[0x8]; 7369 u8 wol_mode[0x8]; 7370 7371 u8 reserved_at_60[0x20]; 7372 }; 7373 7374 struct mlx5_ifc_query_wol_rol_in_bits { 7375 u8 opcode[0x10]; 7376 u8 reserved_at_10[0x10]; 7377 7378 u8 reserved_at_20[0x10]; 7379 u8 op_mod[0x10]; 7380 7381 u8 reserved_at_40[0x40]; 7382 }; 7383 7384 struct mlx5_ifc_set_wol_rol_out_bits { 7385 u8 status[0x8]; 7386 u8 reserved_at_8[0x18]; 7387 7388 u8 syndrome[0x20]; 7389 7390 u8 reserved_at_40[0x40]; 7391 }; 7392 7393 struct mlx5_ifc_set_wol_rol_in_bits { 7394 u8 opcode[0x10]; 7395 u8 reserved_at_10[0x10]; 7396 7397 u8 reserved_at_20[0x10]; 7398 u8 op_mod[0x10]; 7399 7400 u8 rol_mode_valid[0x1]; 7401 u8 wol_mode_valid[0x1]; 7402 u8 reserved_at_42[0xe]; 7403 u8 rol_mode[0x8]; 7404 u8 wol_mode[0x8]; 7405 7406 u8 reserved_at_60[0x20]; 7407 }; 7408 7409 enum { 7410 MLX5_INITIAL_SEG_NIC_INTERFACE_FULL_DRIVER = 0x0, 7411 MLX5_INITIAL_SEG_NIC_INTERFACE_DISABLED = 0x1, 7412 MLX5_INITIAL_SEG_NIC_INTERFACE_NO_DRAM_NIC = 0x2, 7413 }; 7414 7415 enum { 7416 MLX5_INITIAL_SEG_NIC_INTERFACE_SUPPORTED_FULL_DRIVER = 0x0, 7417 MLX5_INITIAL_SEG_NIC_INTERFACE_SUPPORTED_DISABLED = 0x1, 7418 MLX5_INITIAL_SEG_NIC_INTERFACE_SUPPORTED_NO_DRAM_NIC = 0x2, 7419 }; 7420 7421 enum { 7422 MLX5_INITIAL_SEG_HEALTH_SYNDROME_FW_INTERNAL_ERR = 0x1, 7423 MLX5_INITIAL_SEG_HEALTH_SYNDROME_DEAD_IRISC = 0x7, 7424 MLX5_INITIAL_SEG_HEALTH_SYNDROME_HW_FATAL_ERR = 0x8, 7425 MLX5_INITIAL_SEG_HEALTH_SYNDROME_FW_CRC_ERR = 0x9, 7426 MLX5_INITIAL_SEG_HEALTH_SYNDROME_ICM_FETCH_PCI_ERR = 0xa, 7427 MLX5_INITIAL_SEG_HEALTH_SYNDROME_ICM_PAGE_ERR = 0xb, 7428 MLX5_INITIAL_SEG_HEALTH_SYNDROME_ASYNCHRONOUS_EQ_BUF_OVERRUN = 0xc, 7429 MLX5_INITIAL_SEG_HEALTH_SYNDROME_EQ_IN_ERR = 0xd, 7430 MLX5_INITIAL_SEG_HEALTH_SYNDROME_EQ_INV = 0xe, 7431 MLX5_INITIAL_SEG_HEALTH_SYNDROME_FFSER_ERR = 0xf, 7432 MLX5_INITIAL_SEG_HEALTH_SYNDROME_HIGH_TEMP_ERR = 0x10, 7433 }; 7434 7435 struct mlx5_ifc_initial_seg_bits { 7436 u8 fw_rev_minor[0x10]; 7437 u8 fw_rev_major[0x10]; 7438 7439 u8 cmd_interface_rev[0x10]; 7440 u8 fw_rev_subminor[0x10]; 7441 7442 u8 reserved_at_40[0x40]; 7443 7444 u8 cmdq_phy_addr_63_32[0x20]; 7445 7446 u8 cmdq_phy_addr_31_12[0x14]; 7447 u8 reserved_at_b4[0x2]; 7448 u8 nic_interface[0x2]; 7449 u8 log_cmdq_size[0x4]; 7450 u8 log_cmdq_stride[0x4]; 7451 7452 u8 command_doorbell_vector[0x20]; 7453 7454 u8 reserved_at_e0[0xf00]; 7455 7456 u8 initializing[0x1]; 7457 u8 reserved_at_fe1[0x4]; 7458 u8 nic_interface_supported[0x3]; 7459 u8 reserved_at_fe8[0x18]; 7460 7461 struct mlx5_ifc_health_buffer_bits health_buffer; 7462 7463 u8 no_dram_nic_offset[0x20]; 7464 7465 u8 reserved_at_1220[0x6e40]; 7466 7467 u8 reserved_at_8060[0x1f]; 7468 u8 clear_int[0x1]; 7469 7470 u8 health_syndrome[0x8]; 7471 u8 health_counter[0x18]; 7472 7473 u8 reserved_at_80a0[0x17fc0]; 7474 }; 7475 7476 union mlx5_ifc_ports_control_registers_document_bits { 7477 struct mlx5_ifc_bufferx_reg_bits bufferx_reg; 7478 struct mlx5_ifc_eth_2819_cntrs_grp_data_layout_bits eth_2819_cntrs_grp_data_layout; 7479 struct mlx5_ifc_eth_2863_cntrs_grp_data_layout_bits eth_2863_cntrs_grp_data_layout; 7480 struct mlx5_ifc_eth_3635_cntrs_grp_data_layout_bits eth_3635_cntrs_grp_data_layout; 7481 struct mlx5_ifc_eth_802_3_cntrs_grp_data_layout_bits eth_802_3_cntrs_grp_data_layout; 7482 struct mlx5_ifc_eth_extended_cntrs_grp_data_layout_bits eth_extended_cntrs_grp_data_layout; 7483 struct mlx5_ifc_eth_per_prio_grp_data_layout_bits eth_per_prio_grp_data_layout; 7484 struct mlx5_ifc_eth_per_traffic_grp_data_layout_bits eth_per_traffic_grp_data_layout; 7485 struct mlx5_ifc_lane_2_module_mapping_bits lane_2_module_mapping; 7486 struct mlx5_ifc_pamp_reg_bits pamp_reg; 7487 struct mlx5_ifc_paos_reg_bits paos_reg; 7488 struct mlx5_ifc_pcap_reg_bits pcap_reg; 7489 struct mlx5_ifc_peir_reg_bits peir_reg; 7490 struct mlx5_ifc_pelc_reg_bits pelc_reg; 7491 struct mlx5_ifc_pfcc_reg_bits pfcc_reg; 7492 struct mlx5_ifc_ib_port_cntrs_grp_data_layout_bits ib_port_cntrs_grp_data_layout; 7493 struct mlx5_ifc_phys_layer_cntrs_bits phys_layer_cntrs; 7494 struct mlx5_ifc_pifr_reg_bits pifr_reg; 7495 struct mlx5_ifc_pipg_reg_bits pipg_reg; 7496 struct mlx5_ifc_plbf_reg_bits plbf_reg; 7497 struct mlx5_ifc_plib_reg_bits plib_reg; 7498 struct mlx5_ifc_plpc_reg_bits plpc_reg; 7499 struct mlx5_ifc_pmaos_reg_bits pmaos_reg; 7500 struct mlx5_ifc_pmlp_reg_bits pmlp_reg; 7501 struct mlx5_ifc_pmlpn_reg_bits pmlpn_reg; 7502 struct mlx5_ifc_pmpc_reg_bits pmpc_reg; 7503 struct mlx5_ifc_pmpe_reg_bits pmpe_reg; 7504 struct mlx5_ifc_pmpr_reg_bits pmpr_reg; 7505 struct mlx5_ifc_pmtu_reg_bits pmtu_reg; 7506 struct mlx5_ifc_ppad_reg_bits ppad_reg; 7507 struct mlx5_ifc_ppcnt_reg_bits ppcnt_reg; 7508 struct mlx5_ifc_pplm_reg_bits pplm_reg; 7509 struct mlx5_ifc_pplr_reg_bits pplr_reg; 7510 struct mlx5_ifc_ppsc_reg_bits ppsc_reg; 7511 struct mlx5_ifc_pqdr_reg_bits pqdr_reg; 7512 struct mlx5_ifc_pspa_reg_bits pspa_reg; 7513 struct mlx5_ifc_ptas_reg_bits ptas_reg; 7514 struct mlx5_ifc_ptys_reg_bits ptys_reg; 7515 struct mlx5_ifc_mlcr_reg_bits mlcr_reg; 7516 struct mlx5_ifc_pude_reg_bits pude_reg; 7517 struct mlx5_ifc_pvlc_reg_bits pvlc_reg; 7518 struct mlx5_ifc_slrg_reg_bits slrg_reg; 7519 struct mlx5_ifc_sltp_reg_bits sltp_reg; 7520 u8 reserved_at_0[0x60e0]; 7521 }; 7522 7523 union mlx5_ifc_debug_enhancements_document_bits { 7524 struct mlx5_ifc_health_buffer_bits health_buffer; 7525 u8 reserved_at_0[0x200]; 7526 }; 7527 7528 union mlx5_ifc_uplink_pci_interface_document_bits { 7529 struct mlx5_ifc_initial_seg_bits initial_seg; 7530 u8 reserved_at_0[0x20060]; 7531 }; 7532 7533 struct mlx5_ifc_set_flow_table_root_out_bits { 7534 u8 status[0x8]; 7535 u8 reserved_at_8[0x18]; 7536 7537 u8 syndrome[0x20]; 7538 7539 u8 reserved_at_40[0x40]; 7540 }; 7541 7542 struct mlx5_ifc_set_flow_table_root_in_bits { 7543 u8 opcode[0x10]; 7544 u8 reserved_at_10[0x10]; 7545 7546 u8 reserved_at_20[0x10]; 7547 u8 op_mod[0x10]; 7548 7549 u8 other_vport[0x1]; 7550 u8 reserved_at_41[0xf]; 7551 u8 vport_number[0x10]; 7552 7553 u8 reserved_at_60[0x20]; 7554 7555 u8 table_type[0x8]; 7556 u8 reserved_at_88[0x18]; 7557 7558 u8 reserved_at_a0[0x8]; 7559 u8 table_id[0x18]; 7560 7561 u8 reserved_at_c0[0x140]; 7562 }; 7563 7564 enum { 7565 MLX5_MODIFY_FLOW_TABLE_MISS_TABLE_ID = 0x1, 7566 }; 7567 7568 struct mlx5_ifc_modify_flow_table_out_bits { 7569 u8 status[0x8]; 7570 u8 reserved_at_8[0x18]; 7571 7572 u8 syndrome[0x20]; 7573 7574 u8 reserved_at_40[0x40]; 7575 }; 7576 7577 struct mlx5_ifc_modify_flow_table_in_bits { 7578 u8 opcode[0x10]; 7579 u8 reserved_at_10[0x10]; 7580 7581 u8 reserved_at_20[0x10]; 7582 u8 op_mod[0x10]; 7583 7584 u8 other_vport[0x1]; 7585 u8 reserved_at_41[0xf]; 7586 u8 vport_number[0x10]; 7587 7588 u8 reserved_at_60[0x10]; 7589 u8 modify_field_select[0x10]; 7590 7591 u8 table_type[0x8]; 7592 u8 reserved_at_88[0x18]; 7593 7594 u8 reserved_at_a0[0x8]; 7595 u8 table_id[0x18]; 7596 7597 u8 reserved_at_c0[0x4]; 7598 u8 table_miss_mode[0x4]; 7599 u8 reserved_at_c8[0x18]; 7600 7601 u8 reserved_at_e0[0x8]; 7602 u8 table_miss_id[0x18]; 7603 7604 u8 reserved_at_100[0x100]; 7605 }; 7606 7607 struct mlx5_ifc_ets_tcn_config_reg_bits { 7608 u8 g[0x1]; 7609 u8 b[0x1]; 7610 u8 r[0x1]; 7611 u8 reserved_at_3[0x9]; 7612 u8 group[0x4]; 7613 u8 reserved_at_10[0x9]; 7614 u8 bw_allocation[0x7]; 7615 7616 u8 reserved_at_20[0xc]; 7617 u8 max_bw_units[0x4]; 7618 u8 reserved_at_30[0x8]; 7619 u8 max_bw_value[0x8]; 7620 }; 7621 7622 struct mlx5_ifc_ets_global_config_reg_bits { 7623 u8 reserved_at_0[0x2]; 7624 u8 r[0x1]; 7625 u8 reserved_at_3[0x1d]; 7626 7627 u8 reserved_at_20[0xc]; 7628 u8 max_bw_units[0x4]; 7629 u8 reserved_at_30[0x8]; 7630 u8 max_bw_value[0x8]; 7631 }; 7632 7633 struct mlx5_ifc_qetc_reg_bits { 7634 u8 reserved_at_0[0x8]; 7635 u8 port_number[0x8]; 7636 u8 reserved_at_10[0x30]; 7637 7638 struct mlx5_ifc_ets_tcn_config_reg_bits tc_configuration[0x8]; 7639 struct mlx5_ifc_ets_global_config_reg_bits global_configuration; 7640 }; 7641 7642 struct mlx5_ifc_qtct_reg_bits { 7643 u8 reserved_at_0[0x8]; 7644 u8 port_number[0x8]; 7645 u8 reserved_at_10[0xd]; 7646 u8 prio[0x3]; 7647 7648 u8 reserved_at_20[0x1d]; 7649 u8 tclass[0x3]; 7650 }; 7651 7652 struct mlx5_ifc_mcia_reg_bits { 7653 u8 l[0x1]; 7654 u8 reserved_at_1[0x7]; 7655 u8 module[0x8]; 7656 u8 reserved_at_10[0x8]; 7657 u8 status[0x8]; 7658 7659 u8 i2c_device_address[0x8]; 7660 u8 page_number[0x8]; 7661 u8 device_address[0x10]; 7662 7663 u8 reserved_at_40[0x10]; 7664 u8 size[0x10]; 7665 7666 u8 reserved_at_60[0x20]; 7667 7668 u8 dword_0[0x20]; 7669 u8 dword_1[0x20]; 7670 u8 dword_2[0x20]; 7671 u8 dword_3[0x20]; 7672 u8 dword_4[0x20]; 7673 u8 dword_5[0x20]; 7674 u8 dword_6[0x20]; 7675 u8 dword_7[0x20]; 7676 u8 dword_8[0x20]; 7677 u8 dword_9[0x20]; 7678 u8 dword_10[0x20]; 7679 u8 dword_11[0x20]; 7680 }; 7681 7682 struct mlx5_ifc_dcbx_param_bits { 7683 u8 dcbx_cee_cap[0x1]; 7684 u8 dcbx_ieee_cap[0x1]; 7685 u8 dcbx_standby_cap[0x1]; 7686 u8 reserved_at_0[0x5]; 7687 u8 port_number[0x8]; 7688 u8 reserved_at_10[0xa]; 7689 u8 max_application_table_size[6]; 7690 u8 reserved_at_20[0x15]; 7691 u8 version_oper[0x3]; 7692 u8 reserved_at_38[5]; 7693 u8 version_admin[0x3]; 7694 u8 willing_admin[0x1]; 7695 u8 reserved_at_41[0x3]; 7696 u8 pfc_cap_oper[0x4]; 7697 u8 reserved_at_48[0x4]; 7698 u8 pfc_cap_admin[0x4]; 7699 u8 reserved_at_50[0x4]; 7700 u8 num_of_tc_oper[0x4]; 7701 u8 reserved_at_58[0x4]; 7702 u8 num_of_tc_admin[0x4]; 7703 u8 remote_willing[0x1]; 7704 u8 reserved_at_61[3]; 7705 u8 remote_pfc_cap[4]; 7706 u8 reserved_at_68[0x14]; 7707 u8 remote_num_of_tc[0x4]; 7708 u8 reserved_at_80[0x18]; 7709 u8 error[0x8]; 7710 u8 reserved_at_a0[0x160]; 7711 }; 7712 #endif /* MLX5_IFC_H */ 7713