1 /* 2 * Copyright (c) 2013-2015, Mellanox Technologies, Ltd. All rights reserved. 3 * 4 * This software is available to you under a choice of one of two 5 * licenses. You may choose to be licensed under the terms of the GNU 6 * General Public License (GPL) Version 2, available from the file 7 * COPYING in the main directory of this source tree, or the 8 * OpenIB.org BSD license below: 9 * 10 * Redistribution and use in source and binary forms, with or 11 * without modification, are permitted provided that the following 12 * conditions are met: 13 * 14 * - Redistributions of source code must retain the above 15 * copyright notice, this list of conditions and the following 16 * disclaimer. 17 * 18 * - Redistributions in binary form must reproduce the above 19 * copyright notice, this list of conditions and the following 20 * disclaimer in the documentation and/or other materials 21 * provided with the distribution. 22 * 23 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, 24 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF 25 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND 26 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS 27 * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN 28 * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN 29 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE 30 * SOFTWARE. 31 */ 32 #ifndef MLX5_IFC_H 33 #define MLX5_IFC_H 34 35 #include "mlx5_ifc_fpga.h" 36 37 enum { 38 MLX5_EVENT_TYPE_CODING_COMPLETION_EVENTS = 0x0, 39 MLX5_EVENT_TYPE_CODING_PATH_MIGRATED_SUCCEEDED = 0x1, 40 MLX5_EVENT_TYPE_CODING_COMMUNICATION_ESTABLISHED = 0x2, 41 MLX5_EVENT_TYPE_CODING_SEND_QUEUE_DRAINED = 0x3, 42 MLX5_EVENT_TYPE_CODING_LAST_WQE_REACHED = 0x13, 43 MLX5_EVENT_TYPE_CODING_SRQ_LIMIT = 0x14, 44 MLX5_EVENT_TYPE_CODING_DCT_ALL_CONNECTIONS_CLOSED = 0x1c, 45 MLX5_EVENT_TYPE_CODING_DCT_ACCESS_KEY_VIOLATION = 0x1d, 46 MLX5_EVENT_TYPE_CODING_CQ_ERROR = 0x4, 47 MLX5_EVENT_TYPE_CODING_LOCAL_WQ_CATASTROPHIC_ERROR = 0x5, 48 MLX5_EVENT_TYPE_CODING_PATH_MIGRATION_FAILED = 0x7, 49 MLX5_EVENT_TYPE_CODING_PAGE_FAULT_EVENT = 0xc, 50 MLX5_EVENT_TYPE_CODING_INVALID_REQUEST_LOCAL_WQ_ERROR = 0x10, 51 MLX5_EVENT_TYPE_CODING_LOCAL_ACCESS_VIOLATION_WQ_ERROR = 0x11, 52 MLX5_EVENT_TYPE_CODING_LOCAL_SRQ_CATASTROPHIC_ERROR = 0x12, 53 MLX5_EVENT_TYPE_CODING_INTERNAL_ERROR = 0x8, 54 MLX5_EVENT_TYPE_CODING_PORT_STATE_CHANGE = 0x9, 55 MLX5_EVENT_TYPE_CODING_GPIO_EVENT = 0x15, 56 MLX5_EVENT_TYPE_CODING_REMOTE_CONFIGURATION_PROTOCOL_EVENT = 0x19, 57 MLX5_EVENT_TYPE_CODING_DOORBELL_BLUEFLAME_CONGESTION_EVENT = 0x1a, 58 MLX5_EVENT_TYPE_CODING_STALL_VL_EVENT = 0x1b, 59 MLX5_EVENT_TYPE_CODING_DROPPED_PACKET_LOGGED_EVENT = 0x1f, 60 MLX5_EVENT_TYPE_CODING_COMMAND_INTERFACE_COMPLETION = 0xa, 61 MLX5_EVENT_TYPE_CODING_PAGE_REQUEST = 0xb, 62 MLX5_EVENT_TYPE_CODING_FPGA_ERROR = 0x20, 63 MLX5_EVENT_TYPE_CODING_FPGA_QP_ERROR = 0x21 64 }; 65 66 enum { 67 MLX5_SET_HCA_CAP_OP_MOD_GENERAL_DEVICE = 0x0, 68 MLX5_SET_HCA_CAP_OP_MOD_ODP = 0x2, 69 MLX5_SET_HCA_CAP_OP_MOD_ATOMIC = 0x3, 70 MLX5_SET_HCA_CAP_OP_MOD_ROCE = 0x4, 71 MLX5_SET_HCA_CAP_OP_MOD_GENERAL_DEVICE2 = 0x20, 72 MLX5_SET_HCA_CAP_OP_MOD_PORT_SELECTION = 0x25, 73 }; 74 75 enum { 76 MLX5_SHARED_RESOURCE_UID = 0xffff, 77 }; 78 79 enum { 80 MLX5_OBJ_TYPE_SW_ICM = 0x0008, 81 MLX5_OBJ_TYPE_HEADER_MODIFY_ARGUMENT = 0x23, 82 }; 83 84 enum { 85 MLX5_GENERAL_OBJ_TYPES_CAP_SW_ICM = (1ULL << MLX5_OBJ_TYPE_SW_ICM), 86 MLX5_GENERAL_OBJ_TYPES_CAP_GENEVE_TLV_OPT = (1ULL << 11), 87 MLX5_GENERAL_OBJ_TYPES_CAP_VIRTIO_NET_Q = (1ULL << 13), 88 MLX5_GENERAL_OBJ_TYPES_CAP_HEADER_MODIFY_ARGUMENT = 89 (1ULL << MLX5_OBJ_TYPE_HEADER_MODIFY_ARGUMENT), 90 MLX5_GENERAL_OBJ_TYPES_CAP_MACSEC_OFFLOAD = (1ULL << 39), 91 }; 92 93 enum { 94 MLX5_OBJ_TYPE_GENEVE_TLV_OPT = 0x000b, 95 MLX5_OBJ_TYPE_VIRTIO_NET_Q = 0x000d, 96 MLX5_OBJ_TYPE_VIRTIO_Q_COUNTERS = 0x001c, 97 MLX5_OBJ_TYPE_MATCH_DEFINER = 0x0018, 98 MLX5_OBJ_TYPE_PAGE_TRACK = 0x46, 99 MLX5_OBJ_TYPE_MKEY = 0xff01, 100 MLX5_OBJ_TYPE_QP = 0xff02, 101 MLX5_OBJ_TYPE_PSV = 0xff03, 102 MLX5_OBJ_TYPE_RMP = 0xff04, 103 MLX5_OBJ_TYPE_XRC_SRQ = 0xff05, 104 MLX5_OBJ_TYPE_RQ = 0xff06, 105 MLX5_OBJ_TYPE_SQ = 0xff07, 106 MLX5_OBJ_TYPE_TIR = 0xff08, 107 MLX5_OBJ_TYPE_TIS = 0xff09, 108 MLX5_OBJ_TYPE_DCT = 0xff0a, 109 MLX5_OBJ_TYPE_XRQ = 0xff0b, 110 MLX5_OBJ_TYPE_RQT = 0xff0e, 111 MLX5_OBJ_TYPE_FLOW_COUNTER = 0xff0f, 112 MLX5_OBJ_TYPE_CQ = 0xff10, 113 }; 114 115 enum { 116 MLX5_CMD_OP_QUERY_HCA_CAP = 0x100, 117 MLX5_CMD_OP_QUERY_ADAPTER = 0x101, 118 MLX5_CMD_OP_INIT_HCA = 0x102, 119 MLX5_CMD_OP_TEARDOWN_HCA = 0x103, 120 MLX5_CMD_OP_ENABLE_HCA = 0x104, 121 MLX5_CMD_OP_DISABLE_HCA = 0x105, 122 MLX5_CMD_OP_QUERY_PAGES = 0x107, 123 MLX5_CMD_OP_MANAGE_PAGES = 0x108, 124 MLX5_CMD_OP_SET_HCA_CAP = 0x109, 125 MLX5_CMD_OP_QUERY_ISSI = 0x10a, 126 MLX5_CMD_OP_SET_ISSI = 0x10b, 127 MLX5_CMD_OP_SET_DRIVER_VERSION = 0x10d, 128 MLX5_CMD_OP_QUERY_SF_PARTITION = 0x111, 129 MLX5_CMD_OP_ALLOC_SF = 0x113, 130 MLX5_CMD_OP_DEALLOC_SF = 0x114, 131 MLX5_CMD_OP_SUSPEND_VHCA = 0x115, 132 MLX5_CMD_OP_RESUME_VHCA = 0x116, 133 MLX5_CMD_OP_QUERY_VHCA_MIGRATION_STATE = 0x117, 134 MLX5_CMD_OP_SAVE_VHCA_STATE = 0x118, 135 MLX5_CMD_OP_LOAD_VHCA_STATE = 0x119, 136 MLX5_CMD_OP_CREATE_MKEY = 0x200, 137 MLX5_CMD_OP_QUERY_MKEY = 0x201, 138 MLX5_CMD_OP_DESTROY_MKEY = 0x202, 139 MLX5_CMD_OP_QUERY_SPECIAL_CONTEXTS = 0x203, 140 MLX5_CMD_OP_PAGE_FAULT_RESUME = 0x204, 141 MLX5_CMD_OP_ALLOC_MEMIC = 0x205, 142 MLX5_CMD_OP_DEALLOC_MEMIC = 0x206, 143 MLX5_CMD_OP_MODIFY_MEMIC = 0x207, 144 MLX5_CMD_OP_CREATE_EQ = 0x301, 145 MLX5_CMD_OP_DESTROY_EQ = 0x302, 146 MLX5_CMD_OP_QUERY_EQ = 0x303, 147 MLX5_CMD_OP_GEN_EQE = 0x304, 148 MLX5_CMD_OP_CREATE_CQ = 0x400, 149 MLX5_CMD_OP_DESTROY_CQ = 0x401, 150 MLX5_CMD_OP_QUERY_CQ = 0x402, 151 MLX5_CMD_OP_MODIFY_CQ = 0x403, 152 MLX5_CMD_OP_CREATE_QP = 0x500, 153 MLX5_CMD_OP_DESTROY_QP = 0x501, 154 MLX5_CMD_OP_RST2INIT_QP = 0x502, 155 MLX5_CMD_OP_INIT2RTR_QP = 0x503, 156 MLX5_CMD_OP_RTR2RTS_QP = 0x504, 157 MLX5_CMD_OP_RTS2RTS_QP = 0x505, 158 MLX5_CMD_OP_SQERR2RTS_QP = 0x506, 159 MLX5_CMD_OP_2ERR_QP = 0x507, 160 MLX5_CMD_OP_2RST_QP = 0x50a, 161 MLX5_CMD_OP_QUERY_QP = 0x50b, 162 MLX5_CMD_OP_SQD_RTS_QP = 0x50c, 163 MLX5_CMD_OP_INIT2INIT_QP = 0x50e, 164 MLX5_CMD_OP_CREATE_PSV = 0x600, 165 MLX5_CMD_OP_DESTROY_PSV = 0x601, 166 MLX5_CMD_OP_CREATE_SRQ = 0x700, 167 MLX5_CMD_OP_DESTROY_SRQ = 0x701, 168 MLX5_CMD_OP_QUERY_SRQ = 0x702, 169 MLX5_CMD_OP_ARM_RQ = 0x703, 170 MLX5_CMD_OP_CREATE_XRC_SRQ = 0x705, 171 MLX5_CMD_OP_DESTROY_XRC_SRQ = 0x706, 172 MLX5_CMD_OP_QUERY_XRC_SRQ = 0x707, 173 MLX5_CMD_OP_ARM_XRC_SRQ = 0x708, 174 MLX5_CMD_OP_CREATE_DCT = 0x710, 175 MLX5_CMD_OP_DESTROY_DCT = 0x711, 176 MLX5_CMD_OP_DRAIN_DCT = 0x712, 177 MLX5_CMD_OP_QUERY_DCT = 0x713, 178 MLX5_CMD_OP_ARM_DCT_FOR_KEY_VIOLATION = 0x714, 179 MLX5_CMD_OP_CREATE_XRQ = 0x717, 180 MLX5_CMD_OP_DESTROY_XRQ = 0x718, 181 MLX5_CMD_OP_QUERY_XRQ = 0x719, 182 MLX5_CMD_OP_ARM_XRQ = 0x71a, 183 MLX5_CMD_OP_QUERY_XRQ_DC_PARAMS_ENTRY = 0x725, 184 MLX5_CMD_OP_SET_XRQ_DC_PARAMS_ENTRY = 0x726, 185 MLX5_CMD_OP_QUERY_XRQ_ERROR_PARAMS = 0x727, 186 MLX5_CMD_OP_RELEASE_XRQ_ERROR = 0x729, 187 MLX5_CMD_OP_MODIFY_XRQ = 0x72a, 188 MLX5_CMD_OP_QUERY_ESW_FUNCTIONS = 0x740, 189 MLX5_CMD_OP_QUERY_VPORT_STATE = 0x750, 190 MLX5_CMD_OP_MODIFY_VPORT_STATE = 0x751, 191 MLX5_CMD_OP_QUERY_ESW_VPORT_CONTEXT = 0x752, 192 MLX5_CMD_OP_MODIFY_ESW_VPORT_CONTEXT = 0x753, 193 MLX5_CMD_OP_QUERY_NIC_VPORT_CONTEXT = 0x754, 194 MLX5_CMD_OP_MODIFY_NIC_VPORT_CONTEXT = 0x755, 195 MLX5_CMD_OP_QUERY_ROCE_ADDRESS = 0x760, 196 MLX5_CMD_OP_SET_ROCE_ADDRESS = 0x761, 197 MLX5_CMD_OP_QUERY_HCA_VPORT_CONTEXT = 0x762, 198 MLX5_CMD_OP_MODIFY_HCA_VPORT_CONTEXT = 0x763, 199 MLX5_CMD_OP_QUERY_HCA_VPORT_GID = 0x764, 200 MLX5_CMD_OP_QUERY_HCA_VPORT_PKEY = 0x765, 201 MLX5_CMD_OP_QUERY_VNIC_ENV = 0x76f, 202 MLX5_CMD_OP_QUERY_VPORT_COUNTER = 0x770, 203 MLX5_CMD_OP_ALLOC_Q_COUNTER = 0x771, 204 MLX5_CMD_OP_DEALLOC_Q_COUNTER = 0x772, 205 MLX5_CMD_OP_QUERY_Q_COUNTER = 0x773, 206 MLX5_CMD_OP_SET_MONITOR_COUNTER = 0x774, 207 MLX5_CMD_OP_ARM_MONITOR_COUNTER = 0x775, 208 MLX5_CMD_OP_SET_PP_RATE_LIMIT = 0x780, 209 MLX5_CMD_OP_QUERY_RATE_LIMIT = 0x781, 210 MLX5_CMD_OP_CREATE_SCHEDULING_ELEMENT = 0x782, 211 MLX5_CMD_OP_DESTROY_SCHEDULING_ELEMENT = 0x783, 212 MLX5_CMD_OP_QUERY_SCHEDULING_ELEMENT = 0x784, 213 MLX5_CMD_OP_MODIFY_SCHEDULING_ELEMENT = 0x785, 214 MLX5_CMD_OP_CREATE_QOS_PARA_VPORT = 0x786, 215 MLX5_CMD_OP_DESTROY_QOS_PARA_VPORT = 0x787, 216 MLX5_CMD_OP_ALLOC_PD = 0x800, 217 MLX5_CMD_OP_DEALLOC_PD = 0x801, 218 MLX5_CMD_OP_ALLOC_UAR = 0x802, 219 MLX5_CMD_OP_DEALLOC_UAR = 0x803, 220 MLX5_CMD_OP_CONFIG_INT_MODERATION = 0x804, 221 MLX5_CMD_OP_ACCESS_REG = 0x805, 222 MLX5_CMD_OP_ATTACH_TO_MCG = 0x806, 223 MLX5_CMD_OP_DETACH_FROM_MCG = 0x807, 224 MLX5_CMD_OP_GET_DROPPED_PACKET_LOG = 0x80a, 225 MLX5_CMD_OP_MAD_IFC = 0x50d, 226 MLX5_CMD_OP_QUERY_MAD_DEMUX = 0x80b, 227 MLX5_CMD_OP_SET_MAD_DEMUX = 0x80c, 228 MLX5_CMD_OP_NOP = 0x80d, 229 MLX5_CMD_OP_ALLOC_XRCD = 0x80e, 230 MLX5_CMD_OP_DEALLOC_XRCD = 0x80f, 231 MLX5_CMD_OP_ALLOC_TRANSPORT_DOMAIN = 0x816, 232 MLX5_CMD_OP_DEALLOC_TRANSPORT_DOMAIN = 0x817, 233 MLX5_CMD_OP_QUERY_CONG_STATUS = 0x822, 234 MLX5_CMD_OP_MODIFY_CONG_STATUS = 0x823, 235 MLX5_CMD_OP_QUERY_CONG_PARAMS = 0x824, 236 MLX5_CMD_OP_MODIFY_CONG_PARAMS = 0x825, 237 MLX5_CMD_OP_QUERY_CONG_STATISTICS = 0x826, 238 MLX5_CMD_OP_ADD_VXLAN_UDP_DPORT = 0x827, 239 MLX5_CMD_OP_DELETE_VXLAN_UDP_DPORT = 0x828, 240 MLX5_CMD_OP_SET_L2_TABLE_ENTRY = 0x829, 241 MLX5_CMD_OP_QUERY_L2_TABLE_ENTRY = 0x82a, 242 MLX5_CMD_OP_DELETE_L2_TABLE_ENTRY = 0x82b, 243 MLX5_CMD_OP_SET_WOL_ROL = 0x830, 244 MLX5_CMD_OP_QUERY_WOL_ROL = 0x831, 245 MLX5_CMD_OP_CREATE_LAG = 0x840, 246 MLX5_CMD_OP_MODIFY_LAG = 0x841, 247 MLX5_CMD_OP_QUERY_LAG = 0x842, 248 MLX5_CMD_OP_DESTROY_LAG = 0x843, 249 MLX5_CMD_OP_CREATE_VPORT_LAG = 0x844, 250 MLX5_CMD_OP_DESTROY_VPORT_LAG = 0x845, 251 MLX5_CMD_OP_CREATE_TIR = 0x900, 252 MLX5_CMD_OP_MODIFY_TIR = 0x901, 253 MLX5_CMD_OP_DESTROY_TIR = 0x902, 254 MLX5_CMD_OP_QUERY_TIR = 0x903, 255 MLX5_CMD_OP_CREATE_SQ = 0x904, 256 MLX5_CMD_OP_MODIFY_SQ = 0x905, 257 MLX5_CMD_OP_DESTROY_SQ = 0x906, 258 MLX5_CMD_OP_QUERY_SQ = 0x907, 259 MLX5_CMD_OP_CREATE_RQ = 0x908, 260 MLX5_CMD_OP_MODIFY_RQ = 0x909, 261 MLX5_CMD_OP_SET_DELAY_DROP_PARAMS = 0x910, 262 MLX5_CMD_OP_DESTROY_RQ = 0x90a, 263 MLX5_CMD_OP_QUERY_RQ = 0x90b, 264 MLX5_CMD_OP_CREATE_RMP = 0x90c, 265 MLX5_CMD_OP_MODIFY_RMP = 0x90d, 266 MLX5_CMD_OP_DESTROY_RMP = 0x90e, 267 MLX5_CMD_OP_QUERY_RMP = 0x90f, 268 MLX5_CMD_OP_CREATE_TIS = 0x912, 269 MLX5_CMD_OP_MODIFY_TIS = 0x913, 270 MLX5_CMD_OP_DESTROY_TIS = 0x914, 271 MLX5_CMD_OP_QUERY_TIS = 0x915, 272 MLX5_CMD_OP_CREATE_RQT = 0x916, 273 MLX5_CMD_OP_MODIFY_RQT = 0x917, 274 MLX5_CMD_OP_DESTROY_RQT = 0x918, 275 MLX5_CMD_OP_QUERY_RQT = 0x919, 276 MLX5_CMD_OP_SET_FLOW_TABLE_ROOT = 0x92f, 277 MLX5_CMD_OP_CREATE_FLOW_TABLE = 0x930, 278 MLX5_CMD_OP_DESTROY_FLOW_TABLE = 0x931, 279 MLX5_CMD_OP_QUERY_FLOW_TABLE = 0x932, 280 MLX5_CMD_OP_CREATE_FLOW_GROUP = 0x933, 281 MLX5_CMD_OP_DESTROY_FLOW_GROUP = 0x934, 282 MLX5_CMD_OP_QUERY_FLOW_GROUP = 0x935, 283 MLX5_CMD_OP_SET_FLOW_TABLE_ENTRY = 0x936, 284 MLX5_CMD_OP_QUERY_FLOW_TABLE_ENTRY = 0x937, 285 MLX5_CMD_OP_DELETE_FLOW_TABLE_ENTRY = 0x938, 286 MLX5_CMD_OP_ALLOC_FLOW_COUNTER = 0x939, 287 MLX5_CMD_OP_DEALLOC_FLOW_COUNTER = 0x93a, 288 MLX5_CMD_OP_QUERY_FLOW_COUNTER = 0x93b, 289 MLX5_CMD_OP_MODIFY_FLOW_TABLE = 0x93c, 290 MLX5_CMD_OP_ALLOC_PACKET_REFORMAT_CONTEXT = 0x93d, 291 MLX5_CMD_OP_DEALLOC_PACKET_REFORMAT_CONTEXT = 0x93e, 292 MLX5_CMD_OP_QUERY_PACKET_REFORMAT_CONTEXT = 0x93f, 293 MLX5_CMD_OP_ALLOC_MODIFY_HEADER_CONTEXT = 0x940, 294 MLX5_CMD_OP_DEALLOC_MODIFY_HEADER_CONTEXT = 0x941, 295 MLX5_CMD_OP_QUERY_MODIFY_HEADER_CONTEXT = 0x942, 296 MLX5_CMD_OP_FPGA_CREATE_QP = 0x960, 297 MLX5_CMD_OP_FPGA_MODIFY_QP = 0x961, 298 MLX5_CMD_OP_FPGA_QUERY_QP = 0x962, 299 MLX5_CMD_OP_FPGA_DESTROY_QP = 0x963, 300 MLX5_CMD_OP_FPGA_QUERY_QP_COUNTERS = 0x964, 301 MLX5_CMD_OP_CREATE_GENERAL_OBJECT = 0xa00, 302 MLX5_CMD_OP_MODIFY_GENERAL_OBJECT = 0xa01, 303 MLX5_CMD_OP_QUERY_GENERAL_OBJECT = 0xa02, 304 MLX5_CMD_OP_DESTROY_GENERAL_OBJECT = 0xa03, 305 MLX5_CMD_OP_CREATE_UCTX = 0xa04, 306 MLX5_CMD_OP_DESTROY_UCTX = 0xa06, 307 MLX5_CMD_OP_CREATE_UMEM = 0xa08, 308 MLX5_CMD_OP_DESTROY_UMEM = 0xa0a, 309 MLX5_CMD_OP_SYNC_STEERING = 0xb00, 310 MLX5_CMD_OP_QUERY_VHCA_STATE = 0xb0d, 311 MLX5_CMD_OP_MODIFY_VHCA_STATE = 0xb0e, 312 MLX5_CMD_OP_SYNC_CRYPTO = 0xb12, 313 MLX5_CMD_OP_MAX 314 }; 315 316 /* Valid range for general commands that don't work over an object */ 317 enum { 318 MLX5_CMD_OP_GENERAL_START = 0xb00, 319 MLX5_CMD_OP_GENERAL_END = 0xd00, 320 }; 321 322 enum { 323 MLX5_FT_NIC_RX_2_NIC_RX_RDMA = BIT(0), 324 MLX5_FT_NIC_TX_RDMA_2_NIC_TX = BIT(1), 325 }; 326 327 enum { 328 MLX5_CMD_OP_MOD_UPDATE_HEADER_MODIFY_ARGUMENT = 0x1, 329 }; 330 331 struct mlx5_ifc_flow_table_fields_supported_bits { 332 u8 outer_dmac[0x1]; 333 u8 outer_smac[0x1]; 334 u8 outer_ether_type[0x1]; 335 u8 outer_ip_version[0x1]; 336 u8 outer_first_prio[0x1]; 337 u8 outer_first_cfi[0x1]; 338 u8 outer_first_vid[0x1]; 339 u8 outer_ipv4_ttl[0x1]; 340 u8 outer_second_prio[0x1]; 341 u8 outer_second_cfi[0x1]; 342 u8 outer_second_vid[0x1]; 343 u8 reserved_at_b[0x1]; 344 u8 outer_sip[0x1]; 345 u8 outer_dip[0x1]; 346 u8 outer_frag[0x1]; 347 u8 outer_ip_protocol[0x1]; 348 u8 outer_ip_ecn[0x1]; 349 u8 outer_ip_dscp[0x1]; 350 u8 outer_udp_sport[0x1]; 351 u8 outer_udp_dport[0x1]; 352 u8 outer_tcp_sport[0x1]; 353 u8 outer_tcp_dport[0x1]; 354 u8 outer_tcp_flags[0x1]; 355 u8 outer_gre_protocol[0x1]; 356 u8 outer_gre_key[0x1]; 357 u8 outer_vxlan_vni[0x1]; 358 u8 outer_geneve_vni[0x1]; 359 u8 outer_geneve_oam[0x1]; 360 u8 outer_geneve_protocol_type[0x1]; 361 u8 outer_geneve_opt_len[0x1]; 362 u8 source_vhca_port[0x1]; 363 u8 source_eswitch_port[0x1]; 364 365 u8 inner_dmac[0x1]; 366 u8 inner_smac[0x1]; 367 u8 inner_ether_type[0x1]; 368 u8 inner_ip_version[0x1]; 369 u8 inner_first_prio[0x1]; 370 u8 inner_first_cfi[0x1]; 371 u8 inner_first_vid[0x1]; 372 u8 reserved_at_27[0x1]; 373 u8 inner_second_prio[0x1]; 374 u8 inner_second_cfi[0x1]; 375 u8 inner_second_vid[0x1]; 376 u8 reserved_at_2b[0x1]; 377 u8 inner_sip[0x1]; 378 u8 inner_dip[0x1]; 379 u8 inner_frag[0x1]; 380 u8 inner_ip_protocol[0x1]; 381 u8 inner_ip_ecn[0x1]; 382 u8 inner_ip_dscp[0x1]; 383 u8 inner_udp_sport[0x1]; 384 u8 inner_udp_dport[0x1]; 385 u8 inner_tcp_sport[0x1]; 386 u8 inner_tcp_dport[0x1]; 387 u8 inner_tcp_flags[0x1]; 388 u8 reserved_at_37[0x9]; 389 390 u8 geneve_tlv_option_0_data[0x1]; 391 u8 geneve_tlv_option_0_exist[0x1]; 392 u8 reserved_at_42[0x3]; 393 u8 outer_first_mpls_over_udp[0x4]; 394 u8 outer_first_mpls_over_gre[0x4]; 395 u8 inner_first_mpls[0x4]; 396 u8 outer_first_mpls[0x4]; 397 u8 reserved_at_55[0x2]; 398 u8 outer_esp_spi[0x1]; 399 u8 reserved_at_58[0x2]; 400 u8 bth_dst_qp[0x1]; 401 u8 reserved_at_5b[0x5]; 402 403 u8 reserved_at_60[0x18]; 404 u8 metadata_reg_c_7[0x1]; 405 u8 metadata_reg_c_6[0x1]; 406 u8 metadata_reg_c_5[0x1]; 407 u8 metadata_reg_c_4[0x1]; 408 u8 metadata_reg_c_3[0x1]; 409 u8 metadata_reg_c_2[0x1]; 410 u8 metadata_reg_c_1[0x1]; 411 u8 metadata_reg_c_0[0x1]; 412 }; 413 414 /* Table 2170 - Flow Table Fields Supported 2 Format */ 415 struct mlx5_ifc_flow_table_fields_supported_2_bits { 416 u8 reserved_at_0[0xe]; 417 u8 bth_opcode[0x1]; 418 u8 reserved_at_f[0x1]; 419 u8 tunnel_header_0_1[0x1]; 420 u8 reserved_at_11[0xf]; 421 422 u8 reserved_at_20[0x60]; 423 }; 424 425 struct mlx5_ifc_flow_table_prop_layout_bits { 426 u8 ft_support[0x1]; 427 u8 reserved_at_1[0x1]; 428 u8 flow_counter[0x1]; 429 u8 flow_modify_en[0x1]; 430 u8 modify_root[0x1]; 431 u8 identified_miss_table_mode[0x1]; 432 u8 flow_table_modify[0x1]; 433 u8 reformat[0x1]; 434 u8 decap[0x1]; 435 u8 reserved_at_9[0x1]; 436 u8 pop_vlan[0x1]; 437 u8 push_vlan[0x1]; 438 u8 reserved_at_c[0x1]; 439 u8 pop_vlan_2[0x1]; 440 u8 push_vlan_2[0x1]; 441 u8 reformat_and_vlan_action[0x1]; 442 u8 reserved_at_10[0x1]; 443 u8 sw_owner[0x1]; 444 u8 reformat_l3_tunnel_to_l2[0x1]; 445 u8 reformat_l2_to_l3_tunnel[0x1]; 446 u8 reformat_and_modify_action[0x1]; 447 u8 ignore_flow_level[0x1]; 448 u8 reserved_at_16[0x1]; 449 u8 table_miss_action_domain[0x1]; 450 u8 termination_table[0x1]; 451 u8 reformat_and_fwd_to_table[0x1]; 452 u8 reserved_at_1a[0x2]; 453 u8 ipsec_encrypt[0x1]; 454 u8 ipsec_decrypt[0x1]; 455 u8 sw_owner_v2[0x1]; 456 u8 reserved_at_1f[0x1]; 457 458 u8 termination_table_raw_traffic[0x1]; 459 u8 reserved_at_21[0x1]; 460 u8 log_max_ft_size[0x6]; 461 u8 log_max_modify_header_context[0x8]; 462 u8 max_modify_header_actions[0x8]; 463 u8 max_ft_level[0x8]; 464 465 u8 reformat_add_esp_trasport[0x1]; 466 u8 reformat_l2_to_l3_esp_tunnel[0x1]; 467 u8 reserved_at_42[0x1]; 468 u8 reformat_del_esp_trasport[0x1]; 469 u8 reformat_l3_esp_tunnel_to_l2[0x1]; 470 u8 reserved_at_45[0x1]; 471 u8 execute_aso[0x1]; 472 u8 reserved_at_47[0x19]; 473 474 u8 reserved_at_60[0x2]; 475 u8 reformat_insert[0x1]; 476 u8 reformat_remove[0x1]; 477 u8 macsec_encrypt[0x1]; 478 u8 macsec_decrypt[0x1]; 479 u8 reserved_at_66[0x2]; 480 u8 reformat_add_macsec[0x1]; 481 u8 reformat_remove_macsec[0x1]; 482 u8 reserved_at_6a[0xe]; 483 u8 log_max_ft_num[0x8]; 484 485 u8 reserved_at_80[0x10]; 486 u8 log_max_flow_counter[0x8]; 487 u8 log_max_destination[0x8]; 488 489 u8 reserved_at_a0[0x18]; 490 u8 log_max_flow[0x8]; 491 492 u8 reserved_at_c0[0x40]; 493 494 struct mlx5_ifc_flow_table_fields_supported_bits ft_field_support; 495 496 struct mlx5_ifc_flow_table_fields_supported_bits ft_field_bitmask_support; 497 }; 498 499 struct mlx5_ifc_odp_per_transport_service_cap_bits { 500 u8 send[0x1]; 501 u8 receive[0x1]; 502 u8 write[0x1]; 503 u8 read[0x1]; 504 u8 atomic[0x1]; 505 u8 srq_receive[0x1]; 506 u8 reserved_at_6[0x1a]; 507 }; 508 509 struct mlx5_ifc_ipv4_layout_bits { 510 u8 reserved_at_0[0x60]; 511 512 u8 ipv4[0x20]; 513 }; 514 515 struct mlx5_ifc_ipv6_layout_bits { 516 u8 ipv6[16][0x8]; 517 }; 518 519 union mlx5_ifc_ipv6_layout_ipv4_layout_auto_bits { 520 struct mlx5_ifc_ipv6_layout_bits ipv6_layout; 521 struct mlx5_ifc_ipv4_layout_bits ipv4_layout; 522 u8 reserved_at_0[0x80]; 523 }; 524 525 struct mlx5_ifc_fte_match_set_lyr_2_4_bits { 526 u8 smac_47_16[0x20]; 527 528 u8 smac_15_0[0x10]; 529 u8 ethertype[0x10]; 530 531 u8 dmac_47_16[0x20]; 532 533 u8 dmac_15_0[0x10]; 534 u8 first_prio[0x3]; 535 u8 first_cfi[0x1]; 536 u8 first_vid[0xc]; 537 538 u8 ip_protocol[0x8]; 539 u8 ip_dscp[0x6]; 540 u8 ip_ecn[0x2]; 541 u8 cvlan_tag[0x1]; 542 u8 svlan_tag[0x1]; 543 u8 frag[0x1]; 544 u8 ip_version[0x4]; 545 u8 tcp_flags[0x9]; 546 547 u8 tcp_sport[0x10]; 548 u8 tcp_dport[0x10]; 549 550 u8 reserved_at_c0[0x10]; 551 u8 ipv4_ihl[0x4]; 552 u8 reserved_at_c4[0x4]; 553 554 u8 ttl_hoplimit[0x8]; 555 556 u8 udp_sport[0x10]; 557 u8 udp_dport[0x10]; 558 559 union mlx5_ifc_ipv6_layout_ipv4_layout_auto_bits src_ipv4_src_ipv6; 560 561 union mlx5_ifc_ipv6_layout_ipv4_layout_auto_bits dst_ipv4_dst_ipv6; 562 }; 563 564 struct mlx5_ifc_nvgre_key_bits { 565 u8 hi[0x18]; 566 u8 lo[0x8]; 567 }; 568 569 union mlx5_ifc_gre_key_bits { 570 struct mlx5_ifc_nvgre_key_bits nvgre; 571 u8 key[0x20]; 572 }; 573 574 struct mlx5_ifc_fte_match_set_misc_bits { 575 u8 gre_c_present[0x1]; 576 u8 reserved_at_1[0x1]; 577 u8 gre_k_present[0x1]; 578 u8 gre_s_present[0x1]; 579 u8 source_vhca_port[0x4]; 580 u8 source_sqn[0x18]; 581 582 u8 source_eswitch_owner_vhca_id[0x10]; 583 u8 source_port[0x10]; 584 585 u8 outer_second_prio[0x3]; 586 u8 outer_second_cfi[0x1]; 587 u8 outer_second_vid[0xc]; 588 u8 inner_second_prio[0x3]; 589 u8 inner_second_cfi[0x1]; 590 u8 inner_second_vid[0xc]; 591 592 u8 outer_second_cvlan_tag[0x1]; 593 u8 inner_second_cvlan_tag[0x1]; 594 u8 outer_second_svlan_tag[0x1]; 595 u8 inner_second_svlan_tag[0x1]; 596 u8 reserved_at_64[0xc]; 597 u8 gre_protocol[0x10]; 598 599 union mlx5_ifc_gre_key_bits gre_key; 600 601 u8 vxlan_vni[0x18]; 602 u8 bth_opcode[0x8]; 603 604 u8 geneve_vni[0x18]; 605 u8 reserved_at_d8[0x6]; 606 u8 geneve_tlv_option_0_exist[0x1]; 607 u8 geneve_oam[0x1]; 608 609 u8 reserved_at_e0[0xc]; 610 u8 outer_ipv6_flow_label[0x14]; 611 612 u8 reserved_at_100[0xc]; 613 u8 inner_ipv6_flow_label[0x14]; 614 615 u8 reserved_at_120[0xa]; 616 u8 geneve_opt_len[0x6]; 617 u8 geneve_protocol_type[0x10]; 618 619 u8 reserved_at_140[0x8]; 620 u8 bth_dst_qp[0x18]; 621 u8 reserved_at_160[0x20]; 622 u8 outer_esp_spi[0x20]; 623 u8 reserved_at_1a0[0x60]; 624 }; 625 626 struct mlx5_ifc_fte_match_mpls_bits { 627 u8 mpls_label[0x14]; 628 u8 mpls_exp[0x3]; 629 u8 mpls_s_bos[0x1]; 630 u8 mpls_ttl[0x8]; 631 }; 632 633 struct mlx5_ifc_fte_match_set_misc2_bits { 634 struct mlx5_ifc_fte_match_mpls_bits outer_first_mpls; 635 636 struct mlx5_ifc_fte_match_mpls_bits inner_first_mpls; 637 638 struct mlx5_ifc_fte_match_mpls_bits outer_first_mpls_over_gre; 639 640 struct mlx5_ifc_fte_match_mpls_bits outer_first_mpls_over_udp; 641 642 u8 metadata_reg_c_7[0x20]; 643 644 u8 metadata_reg_c_6[0x20]; 645 646 u8 metadata_reg_c_5[0x20]; 647 648 u8 metadata_reg_c_4[0x20]; 649 650 u8 metadata_reg_c_3[0x20]; 651 652 u8 metadata_reg_c_2[0x20]; 653 654 u8 metadata_reg_c_1[0x20]; 655 656 u8 metadata_reg_c_0[0x20]; 657 658 u8 metadata_reg_a[0x20]; 659 660 u8 reserved_at_1a0[0x8]; 661 662 u8 macsec_syndrome[0x8]; 663 u8 ipsec_syndrome[0x8]; 664 u8 reserved_at_1b8[0x8]; 665 666 u8 reserved_at_1c0[0x40]; 667 }; 668 669 struct mlx5_ifc_fte_match_set_misc3_bits { 670 u8 inner_tcp_seq_num[0x20]; 671 672 u8 outer_tcp_seq_num[0x20]; 673 674 u8 inner_tcp_ack_num[0x20]; 675 676 u8 outer_tcp_ack_num[0x20]; 677 678 u8 reserved_at_80[0x8]; 679 u8 outer_vxlan_gpe_vni[0x18]; 680 681 u8 outer_vxlan_gpe_next_protocol[0x8]; 682 u8 outer_vxlan_gpe_flags[0x8]; 683 u8 reserved_at_b0[0x10]; 684 685 u8 icmp_header_data[0x20]; 686 687 u8 icmpv6_header_data[0x20]; 688 689 u8 icmp_type[0x8]; 690 u8 icmp_code[0x8]; 691 u8 icmpv6_type[0x8]; 692 u8 icmpv6_code[0x8]; 693 694 u8 geneve_tlv_option_0_data[0x20]; 695 696 u8 gtpu_teid[0x20]; 697 698 u8 gtpu_msg_type[0x8]; 699 u8 gtpu_msg_flags[0x8]; 700 u8 reserved_at_170[0x10]; 701 702 u8 gtpu_dw_2[0x20]; 703 704 u8 gtpu_first_ext_dw_0[0x20]; 705 706 u8 gtpu_dw_0[0x20]; 707 708 u8 reserved_at_1e0[0x20]; 709 }; 710 711 struct mlx5_ifc_fte_match_set_misc4_bits { 712 u8 prog_sample_field_value_0[0x20]; 713 714 u8 prog_sample_field_id_0[0x20]; 715 716 u8 prog_sample_field_value_1[0x20]; 717 718 u8 prog_sample_field_id_1[0x20]; 719 720 u8 prog_sample_field_value_2[0x20]; 721 722 u8 prog_sample_field_id_2[0x20]; 723 724 u8 prog_sample_field_value_3[0x20]; 725 726 u8 prog_sample_field_id_3[0x20]; 727 728 u8 reserved_at_100[0x100]; 729 }; 730 731 struct mlx5_ifc_fte_match_set_misc5_bits { 732 u8 macsec_tag_0[0x20]; 733 734 u8 macsec_tag_1[0x20]; 735 736 u8 macsec_tag_2[0x20]; 737 738 u8 macsec_tag_3[0x20]; 739 740 u8 tunnel_header_0[0x20]; 741 742 u8 tunnel_header_1[0x20]; 743 744 u8 tunnel_header_2[0x20]; 745 746 u8 tunnel_header_3[0x20]; 747 748 u8 reserved_at_100[0x100]; 749 }; 750 751 struct mlx5_ifc_cmd_pas_bits { 752 u8 pa_h[0x20]; 753 754 u8 pa_l[0x14]; 755 u8 reserved_at_34[0xc]; 756 }; 757 758 struct mlx5_ifc_uint64_bits { 759 u8 hi[0x20]; 760 761 u8 lo[0x20]; 762 }; 763 764 enum { 765 MLX5_ADS_STAT_RATE_NO_LIMIT = 0x0, 766 MLX5_ADS_STAT_RATE_2_5GBPS = 0x7, 767 MLX5_ADS_STAT_RATE_10GBPS = 0x8, 768 MLX5_ADS_STAT_RATE_30GBPS = 0x9, 769 MLX5_ADS_STAT_RATE_5GBPS = 0xa, 770 MLX5_ADS_STAT_RATE_20GBPS = 0xb, 771 MLX5_ADS_STAT_RATE_40GBPS = 0xc, 772 MLX5_ADS_STAT_RATE_60GBPS = 0xd, 773 MLX5_ADS_STAT_RATE_80GBPS = 0xe, 774 MLX5_ADS_STAT_RATE_120GBPS = 0xf, 775 }; 776 777 struct mlx5_ifc_ads_bits { 778 u8 fl[0x1]; 779 u8 free_ar[0x1]; 780 u8 reserved_at_2[0xe]; 781 u8 pkey_index[0x10]; 782 783 u8 reserved_at_20[0x8]; 784 u8 grh[0x1]; 785 u8 mlid[0x7]; 786 u8 rlid[0x10]; 787 788 u8 ack_timeout[0x5]; 789 u8 reserved_at_45[0x3]; 790 u8 src_addr_index[0x8]; 791 u8 reserved_at_50[0x4]; 792 u8 stat_rate[0x4]; 793 u8 hop_limit[0x8]; 794 795 u8 reserved_at_60[0x4]; 796 u8 tclass[0x8]; 797 u8 flow_label[0x14]; 798 799 u8 rgid_rip[16][0x8]; 800 801 u8 reserved_at_100[0x4]; 802 u8 f_dscp[0x1]; 803 u8 f_ecn[0x1]; 804 u8 reserved_at_106[0x1]; 805 u8 f_eth_prio[0x1]; 806 u8 ecn[0x2]; 807 u8 dscp[0x6]; 808 u8 udp_sport[0x10]; 809 810 u8 dei_cfi[0x1]; 811 u8 eth_prio[0x3]; 812 u8 sl[0x4]; 813 u8 vhca_port_num[0x8]; 814 u8 rmac_47_32[0x10]; 815 816 u8 rmac_31_0[0x20]; 817 }; 818 819 struct mlx5_ifc_flow_table_nic_cap_bits { 820 u8 nic_rx_multi_path_tirs[0x1]; 821 u8 nic_rx_multi_path_tirs_fts[0x1]; 822 u8 allow_sniffer_and_nic_rx_shared_tir[0x1]; 823 u8 reserved_at_3[0x4]; 824 u8 sw_owner_reformat_supported[0x1]; 825 u8 reserved_at_8[0x18]; 826 827 u8 encap_general_header[0x1]; 828 u8 reserved_at_21[0xa]; 829 u8 log_max_packet_reformat_context[0x5]; 830 u8 reserved_at_30[0x6]; 831 u8 max_encap_header_size[0xa]; 832 u8 reserved_at_40[0x1c0]; 833 834 struct mlx5_ifc_flow_table_prop_layout_bits flow_table_properties_nic_receive; 835 836 struct mlx5_ifc_flow_table_prop_layout_bits flow_table_properties_nic_receive_rdma; 837 838 struct mlx5_ifc_flow_table_prop_layout_bits flow_table_properties_nic_receive_sniffer; 839 840 struct mlx5_ifc_flow_table_prop_layout_bits flow_table_properties_nic_transmit; 841 842 struct mlx5_ifc_flow_table_prop_layout_bits flow_table_properties_nic_transmit_rdma; 843 844 struct mlx5_ifc_flow_table_prop_layout_bits flow_table_properties_nic_transmit_sniffer; 845 846 u8 reserved_at_e00[0x700]; 847 848 struct mlx5_ifc_flow_table_fields_supported_2_bits ft_field_support_2_nic_receive_rdma; 849 850 u8 reserved_at_1580[0x280]; 851 852 struct mlx5_ifc_flow_table_fields_supported_2_bits ft_field_support_2_nic_transmit_rdma; 853 854 u8 reserved_at_1880[0x780]; 855 856 u8 sw_steering_nic_rx_action_drop_icm_address[0x40]; 857 858 u8 sw_steering_nic_tx_action_drop_icm_address[0x40]; 859 860 u8 sw_steering_nic_tx_action_allow_icm_address[0x40]; 861 862 u8 reserved_at_20c0[0x5f40]; 863 }; 864 865 struct mlx5_ifc_port_selection_cap_bits { 866 u8 reserved_at_0[0x10]; 867 u8 port_select_flow_table[0x1]; 868 u8 reserved_at_11[0x1]; 869 u8 port_select_flow_table_bypass[0x1]; 870 u8 reserved_at_13[0xd]; 871 872 u8 reserved_at_20[0x1e0]; 873 874 struct mlx5_ifc_flow_table_prop_layout_bits flow_table_properties_port_selection; 875 876 u8 reserved_at_400[0x7c00]; 877 }; 878 879 enum { 880 MLX5_FDB_TO_VPORT_REG_C_0 = 0x01, 881 MLX5_FDB_TO_VPORT_REG_C_1 = 0x02, 882 MLX5_FDB_TO_VPORT_REG_C_2 = 0x04, 883 MLX5_FDB_TO_VPORT_REG_C_3 = 0x08, 884 MLX5_FDB_TO_VPORT_REG_C_4 = 0x10, 885 MLX5_FDB_TO_VPORT_REG_C_5 = 0x20, 886 MLX5_FDB_TO_VPORT_REG_C_6 = 0x40, 887 MLX5_FDB_TO_VPORT_REG_C_7 = 0x80, 888 }; 889 890 struct mlx5_ifc_flow_table_eswitch_cap_bits { 891 u8 fdb_to_vport_reg_c_id[0x8]; 892 u8 reserved_at_8[0x5]; 893 u8 fdb_uplink_hairpin[0x1]; 894 u8 fdb_multi_path_any_table_limit_regc[0x1]; 895 u8 reserved_at_f[0x3]; 896 u8 fdb_multi_path_any_table[0x1]; 897 u8 reserved_at_13[0x2]; 898 u8 fdb_modify_header_fwd_to_table[0x1]; 899 u8 fdb_ipv4_ttl_modify[0x1]; 900 u8 flow_source[0x1]; 901 u8 reserved_at_18[0x2]; 902 u8 multi_fdb_encap[0x1]; 903 u8 egress_acl_forward_to_vport[0x1]; 904 u8 fdb_multi_path_to_table[0x1]; 905 u8 reserved_at_1d[0x3]; 906 907 u8 reserved_at_20[0x1e0]; 908 909 struct mlx5_ifc_flow_table_prop_layout_bits flow_table_properties_nic_esw_fdb; 910 911 struct mlx5_ifc_flow_table_prop_layout_bits flow_table_properties_esw_acl_ingress; 912 913 struct mlx5_ifc_flow_table_prop_layout_bits flow_table_properties_esw_acl_egress; 914 915 u8 reserved_at_800[0xC00]; 916 917 struct mlx5_ifc_flow_table_fields_supported_2_bits ft_field_support_2_esw_fdb; 918 919 struct mlx5_ifc_flow_table_fields_supported_2_bits ft_field_bitmask_support_2_esw_fdb; 920 921 u8 reserved_at_1500[0x300]; 922 923 u8 sw_steering_fdb_action_drop_icm_address_rx[0x40]; 924 925 u8 sw_steering_fdb_action_drop_icm_address_tx[0x40]; 926 927 u8 sw_steering_uplink_icm_address_rx[0x40]; 928 929 u8 sw_steering_uplink_icm_address_tx[0x40]; 930 931 u8 reserved_at_1900[0x6700]; 932 }; 933 934 enum { 935 MLX5_COUNTER_SOURCE_ESWITCH = 0x0, 936 MLX5_COUNTER_FLOW_ESWITCH = 0x1, 937 }; 938 939 struct mlx5_ifc_e_switch_cap_bits { 940 u8 vport_svlan_strip[0x1]; 941 u8 vport_cvlan_strip[0x1]; 942 u8 vport_svlan_insert[0x1]; 943 u8 vport_cvlan_insert_if_not_exist[0x1]; 944 u8 vport_cvlan_insert_overwrite[0x1]; 945 u8 reserved_at_5[0x1]; 946 u8 vport_cvlan_insert_always[0x1]; 947 u8 esw_shared_ingress_acl[0x1]; 948 u8 esw_uplink_ingress_acl[0x1]; 949 u8 root_ft_on_other_esw[0x1]; 950 u8 reserved_at_a[0xf]; 951 u8 esw_functions_changed[0x1]; 952 u8 reserved_at_1a[0x1]; 953 u8 ecpf_vport_exists[0x1]; 954 u8 counter_eswitch_affinity[0x1]; 955 u8 merged_eswitch[0x1]; 956 u8 nic_vport_node_guid_modify[0x1]; 957 u8 nic_vport_port_guid_modify[0x1]; 958 959 u8 vxlan_encap_decap[0x1]; 960 u8 nvgre_encap_decap[0x1]; 961 u8 reserved_at_22[0x1]; 962 u8 log_max_fdb_encap_uplink[0x5]; 963 u8 reserved_at_21[0x3]; 964 u8 log_max_packet_reformat_context[0x5]; 965 u8 reserved_2b[0x6]; 966 u8 max_encap_header_size[0xa]; 967 968 u8 reserved_at_40[0xb]; 969 u8 log_max_esw_sf[0x5]; 970 u8 esw_sf_base_id[0x10]; 971 972 u8 reserved_at_60[0x7a0]; 973 974 }; 975 976 struct mlx5_ifc_qos_cap_bits { 977 u8 packet_pacing[0x1]; 978 u8 esw_scheduling[0x1]; 979 u8 esw_bw_share[0x1]; 980 u8 esw_rate_limit[0x1]; 981 u8 reserved_at_4[0x1]; 982 u8 packet_pacing_burst_bound[0x1]; 983 u8 packet_pacing_typical_size[0x1]; 984 u8 reserved_at_7[0x1]; 985 u8 nic_sq_scheduling[0x1]; 986 u8 nic_bw_share[0x1]; 987 u8 nic_rate_limit[0x1]; 988 u8 packet_pacing_uid[0x1]; 989 u8 log_esw_max_sched_depth[0x4]; 990 u8 reserved_at_10[0x10]; 991 992 u8 reserved_at_20[0xb]; 993 u8 log_max_qos_nic_queue_group[0x5]; 994 u8 reserved_at_30[0x10]; 995 996 u8 packet_pacing_max_rate[0x20]; 997 998 u8 packet_pacing_min_rate[0x20]; 999 1000 u8 reserved_at_80[0x10]; 1001 u8 packet_pacing_rate_table_size[0x10]; 1002 1003 u8 esw_element_type[0x10]; 1004 u8 esw_tsar_type[0x10]; 1005 1006 u8 reserved_at_c0[0x10]; 1007 u8 max_qos_para_vport[0x10]; 1008 1009 u8 max_tsar_bw_share[0x20]; 1010 1011 u8 reserved_at_100[0x20]; 1012 1013 u8 reserved_at_120[0x3]; 1014 u8 log_meter_aso_granularity[0x5]; 1015 u8 reserved_at_128[0x3]; 1016 u8 log_meter_aso_max_alloc[0x5]; 1017 u8 reserved_at_130[0x3]; 1018 u8 log_max_num_meter_aso[0x5]; 1019 u8 reserved_at_138[0x8]; 1020 1021 u8 reserved_at_140[0x6c0]; 1022 }; 1023 1024 struct mlx5_ifc_debug_cap_bits { 1025 u8 core_dump_general[0x1]; 1026 u8 core_dump_qp[0x1]; 1027 u8 reserved_at_2[0x7]; 1028 u8 resource_dump[0x1]; 1029 u8 reserved_at_a[0x16]; 1030 1031 u8 reserved_at_20[0x2]; 1032 u8 stall_detect[0x1]; 1033 u8 reserved_at_23[0x1d]; 1034 1035 u8 reserved_at_40[0x7c0]; 1036 }; 1037 1038 struct mlx5_ifc_per_protocol_networking_offload_caps_bits { 1039 u8 csum_cap[0x1]; 1040 u8 vlan_cap[0x1]; 1041 u8 lro_cap[0x1]; 1042 u8 lro_psh_flag[0x1]; 1043 u8 lro_time_stamp[0x1]; 1044 u8 reserved_at_5[0x2]; 1045 u8 wqe_vlan_insert[0x1]; 1046 u8 self_lb_en_modifiable[0x1]; 1047 u8 reserved_at_9[0x2]; 1048 u8 max_lso_cap[0x5]; 1049 u8 multi_pkt_send_wqe[0x2]; 1050 u8 wqe_inline_mode[0x2]; 1051 u8 rss_ind_tbl_cap[0x4]; 1052 u8 reg_umr_sq[0x1]; 1053 u8 scatter_fcs[0x1]; 1054 u8 enhanced_multi_pkt_send_wqe[0x1]; 1055 u8 tunnel_lso_const_out_ip_id[0x1]; 1056 u8 tunnel_lro_gre[0x1]; 1057 u8 tunnel_lro_vxlan[0x1]; 1058 u8 tunnel_stateless_gre[0x1]; 1059 u8 tunnel_stateless_vxlan[0x1]; 1060 1061 u8 swp[0x1]; 1062 u8 swp_csum[0x1]; 1063 u8 swp_lso[0x1]; 1064 u8 cqe_checksum_full[0x1]; 1065 u8 tunnel_stateless_geneve_tx[0x1]; 1066 u8 tunnel_stateless_mpls_over_udp[0x1]; 1067 u8 tunnel_stateless_mpls_over_gre[0x1]; 1068 u8 tunnel_stateless_vxlan_gpe[0x1]; 1069 u8 tunnel_stateless_ipv4_over_vxlan[0x1]; 1070 u8 tunnel_stateless_ip_over_ip[0x1]; 1071 u8 insert_trailer[0x1]; 1072 u8 reserved_at_2b[0x1]; 1073 u8 tunnel_stateless_ip_over_ip_rx[0x1]; 1074 u8 tunnel_stateless_ip_over_ip_tx[0x1]; 1075 u8 reserved_at_2e[0x2]; 1076 u8 max_vxlan_udp_ports[0x8]; 1077 u8 reserved_at_38[0x6]; 1078 u8 max_geneve_opt_len[0x1]; 1079 u8 tunnel_stateless_geneve_rx[0x1]; 1080 1081 u8 reserved_at_40[0x10]; 1082 u8 lro_min_mss_size[0x10]; 1083 1084 u8 reserved_at_60[0x120]; 1085 1086 u8 lro_timer_supported_periods[4][0x20]; 1087 1088 u8 reserved_at_200[0x600]; 1089 }; 1090 1091 enum { 1092 MLX5_TIMESTAMP_FORMAT_CAP_FREE_RUNNING = 0x0, 1093 MLX5_TIMESTAMP_FORMAT_CAP_REAL_TIME = 0x1, 1094 MLX5_TIMESTAMP_FORMAT_CAP_FREE_RUNNING_AND_REAL_TIME = 0x2, 1095 }; 1096 1097 struct mlx5_ifc_roce_cap_bits { 1098 u8 roce_apm[0x1]; 1099 u8 reserved_at_1[0x3]; 1100 u8 sw_r_roce_src_udp_port[0x1]; 1101 u8 fl_rc_qp_when_roce_disabled[0x1]; 1102 u8 fl_rc_qp_when_roce_enabled[0x1]; 1103 u8 reserved_at_7[0x1]; 1104 u8 qp_ooo_transmit_default[0x1]; 1105 u8 reserved_at_9[0x15]; 1106 u8 qp_ts_format[0x2]; 1107 1108 u8 reserved_at_20[0x60]; 1109 1110 u8 reserved_at_80[0xc]; 1111 u8 l3_type[0x4]; 1112 u8 reserved_at_90[0x8]; 1113 u8 roce_version[0x8]; 1114 1115 u8 reserved_at_a0[0x10]; 1116 u8 r_roce_dest_udp_port[0x10]; 1117 1118 u8 r_roce_max_src_udp_port[0x10]; 1119 u8 r_roce_min_src_udp_port[0x10]; 1120 1121 u8 reserved_at_e0[0x10]; 1122 u8 roce_address_table_size[0x10]; 1123 1124 u8 reserved_at_100[0x700]; 1125 }; 1126 1127 struct mlx5_ifc_sync_steering_in_bits { 1128 u8 opcode[0x10]; 1129 u8 uid[0x10]; 1130 1131 u8 reserved_at_20[0x10]; 1132 u8 op_mod[0x10]; 1133 1134 u8 reserved_at_40[0xc0]; 1135 }; 1136 1137 struct mlx5_ifc_sync_steering_out_bits { 1138 u8 status[0x8]; 1139 u8 reserved_at_8[0x18]; 1140 1141 u8 syndrome[0x20]; 1142 1143 u8 reserved_at_40[0x40]; 1144 }; 1145 1146 struct mlx5_ifc_sync_crypto_in_bits { 1147 u8 opcode[0x10]; 1148 u8 uid[0x10]; 1149 1150 u8 reserved_at_20[0x10]; 1151 u8 op_mod[0x10]; 1152 1153 u8 reserved_at_40[0x20]; 1154 1155 u8 reserved_at_60[0x10]; 1156 u8 crypto_type[0x10]; 1157 1158 u8 reserved_at_80[0x80]; 1159 }; 1160 1161 struct mlx5_ifc_sync_crypto_out_bits { 1162 u8 status[0x8]; 1163 u8 reserved_at_8[0x18]; 1164 1165 u8 syndrome[0x20]; 1166 1167 u8 reserved_at_40[0x40]; 1168 }; 1169 1170 struct mlx5_ifc_device_mem_cap_bits { 1171 u8 memic[0x1]; 1172 u8 reserved_at_1[0x1f]; 1173 1174 u8 reserved_at_20[0xb]; 1175 u8 log_min_memic_alloc_size[0x5]; 1176 u8 reserved_at_30[0x8]; 1177 u8 log_max_memic_addr_alignment[0x8]; 1178 1179 u8 memic_bar_start_addr[0x40]; 1180 1181 u8 memic_bar_size[0x20]; 1182 1183 u8 max_memic_size[0x20]; 1184 1185 u8 steering_sw_icm_start_address[0x40]; 1186 1187 u8 reserved_at_100[0x8]; 1188 u8 log_header_modify_sw_icm_size[0x8]; 1189 u8 reserved_at_110[0x2]; 1190 u8 log_sw_icm_alloc_granularity[0x6]; 1191 u8 log_steering_sw_icm_size[0x8]; 1192 1193 u8 reserved_at_120[0x18]; 1194 u8 log_header_modify_pattern_sw_icm_size[0x8]; 1195 1196 u8 header_modify_sw_icm_start_address[0x40]; 1197 1198 u8 reserved_at_180[0x40]; 1199 1200 u8 header_modify_pattern_sw_icm_start_address[0x40]; 1201 1202 u8 memic_operations[0x20]; 1203 1204 u8 reserved_at_220[0x5e0]; 1205 }; 1206 1207 struct mlx5_ifc_device_event_cap_bits { 1208 u8 user_affiliated_events[4][0x40]; 1209 1210 u8 user_unaffiliated_events[4][0x40]; 1211 }; 1212 1213 struct mlx5_ifc_virtio_emulation_cap_bits { 1214 u8 desc_tunnel_offload_type[0x1]; 1215 u8 eth_frame_offload_type[0x1]; 1216 u8 virtio_version_1_0[0x1]; 1217 u8 device_features_bits_mask[0xd]; 1218 u8 event_mode[0x8]; 1219 u8 virtio_queue_type[0x8]; 1220 1221 u8 max_tunnel_desc[0x10]; 1222 u8 reserved_at_30[0x3]; 1223 u8 log_doorbell_stride[0x5]; 1224 u8 reserved_at_38[0x3]; 1225 u8 log_doorbell_bar_size[0x5]; 1226 1227 u8 doorbell_bar_offset[0x40]; 1228 1229 u8 max_emulated_devices[0x8]; 1230 u8 max_num_virtio_queues[0x18]; 1231 1232 u8 reserved_at_a0[0x60]; 1233 1234 u8 umem_1_buffer_param_a[0x20]; 1235 1236 u8 umem_1_buffer_param_b[0x20]; 1237 1238 u8 umem_2_buffer_param_a[0x20]; 1239 1240 u8 umem_2_buffer_param_b[0x20]; 1241 1242 u8 umem_3_buffer_param_a[0x20]; 1243 1244 u8 umem_3_buffer_param_b[0x20]; 1245 1246 u8 reserved_at_1c0[0x640]; 1247 }; 1248 1249 enum { 1250 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_QP_1_BYTE = 0x0, 1251 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_QP_2_BYTES = 0x2, 1252 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_QP_4_BYTES = 0x4, 1253 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_QP_8_BYTES = 0x8, 1254 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_QP_16_BYTES = 0x10, 1255 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_QP_32_BYTES = 0x20, 1256 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_QP_64_BYTES = 0x40, 1257 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_QP_128_BYTES = 0x80, 1258 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_QP_256_BYTES = 0x100, 1259 }; 1260 1261 enum { 1262 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_DC_1_BYTE = 0x1, 1263 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_DC_2_BYTES = 0x2, 1264 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_DC_4_BYTES = 0x4, 1265 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_DC_8_BYTES = 0x8, 1266 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_DC_16_BYTES = 0x10, 1267 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_DC_32_BYTES = 0x20, 1268 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_DC_64_BYTES = 0x40, 1269 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_DC_128_BYTES = 0x80, 1270 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_DC_256_BYTES = 0x100, 1271 }; 1272 1273 struct mlx5_ifc_atomic_caps_bits { 1274 u8 reserved_at_0[0x40]; 1275 1276 u8 atomic_req_8B_endianness_mode[0x2]; 1277 u8 reserved_at_42[0x4]; 1278 u8 supported_atomic_req_8B_endianness_mode_1[0x1]; 1279 1280 u8 reserved_at_47[0x19]; 1281 1282 u8 reserved_at_60[0x20]; 1283 1284 u8 reserved_at_80[0x10]; 1285 u8 atomic_operations[0x10]; 1286 1287 u8 reserved_at_a0[0x10]; 1288 u8 atomic_size_qp[0x10]; 1289 1290 u8 reserved_at_c0[0x10]; 1291 u8 atomic_size_dc[0x10]; 1292 1293 u8 reserved_at_e0[0x720]; 1294 }; 1295 1296 struct mlx5_ifc_odp_cap_bits { 1297 u8 reserved_at_0[0x40]; 1298 1299 u8 sig[0x1]; 1300 u8 reserved_at_41[0x1f]; 1301 1302 u8 reserved_at_60[0x20]; 1303 1304 struct mlx5_ifc_odp_per_transport_service_cap_bits rc_odp_caps; 1305 1306 struct mlx5_ifc_odp_per_transport_service_cap_bits uc_odp_caps; 1307 1308 struct mlx5_ifc_odp_per_transport_service_cap_bits ud_odp_caps; 1309 1310 struct mlx5_ifc_odp_per_transport_service_cap_bits xrc_odp_caps; 1311 1312 struct mlx5_ifc_odp_per_transport_service_cap_bits dc_odp_caps; 1313 1314 u8 reserved_at_120[0x6E0]; 1315 }; 1316 1317 struct mlx5_ifc_calc_op { 1318 u8 reserved_at_0[0x10]; 1319 u8 reserved_at_10[0x9]; 1320 u8 op_swap_endianness[0x1]; 1321 u8 op_min[0x1]; 1322 u8 op_xor[0x1]; 1323 u8 op_or[0x1]; 1324 u8 op_and[0x1]; 1325 u8 op_max[0x1]; 1326 u8 op_add[0x1]; 1327 }; 1328 1329 struct mlx5_ifc_vector_calc_cap_bits { 1330 u8 calc_matrix[0x1]; 1331 u8 reserved_at_1[0x1f]; 1332 u8 reserved_at_20[0x8]; 1333 u8 max_vec_count[0x8]; 1334 u8 reserved_at_30[0xd]; 1335 u8 max_chunk_size[0x3]; 1336 struct mlx5_ifc_calc_op calc0; 1337 struct mlx5_ifc_calc_op calc1; 1338 struct mlx5_ifc_calc_op calc2; 1339 struct mlx5_ifc_calc_op calc3; 1340 1341 u8 reserved_at_c0[0x720]; 1342 }; 1343 1344 struct mlx5_ifc_tls_cap_bits { 1345 u8 tls_1_2_aes_gcm_128[0x1]; 1346 u8 tls_1_3_aes_gcm_128[0x1]; 1347 u8 tls_1_2_aes_gcm_256[0x1]; 1348 u8 tls_1_3_aes_gcm_256[0x1]; 1349 u8 reserved_at_4[0x1c]; 1350 1351 u8 reserved_at_20[0x7e0]; 1352 }; 1353 1354 struct mlx5_ifc_ipsec_cap_bits { 1355 u8 ipsec_full_offload[0x1]; 1356 u8 ipsec_crypto_offload[0x1]; 1357 u8 ipsec_esn[0x1]; 1358 u8 ipsec_crypto_esp_aes_gcm_256_encrypt[0x1]; 1359 u8 ipsec_crypto_esp_aes_gcm_128_encrypt[0x1]; 1360 u8 ipsec_crypto_esp_aes_gcm_256_decrypt[0x1]; 1361 u8 ipsec_crypto_esp_aes_gcm_128_decrypt[0x1]; 1362 u8 reserved_at_7[0x4]; 1363 u8 log_max_ipsec_offload[0x5]; 1364 u8 reserved_at_10[0x10]; 1365 1366 u8 min_log_ipsec_full_replay_window[0x8]; 1367 u8 max_log_ipsec_full_replay_window[0x8]; 1368 u8 reserved_at_30[0x7d0]; 1369 }; 1370 1371 struct mlx5_ifc_macsec_cap_bits { 1372 u8 macsec_epn[0x1]; 1373 u8 reserved_at_1[0x2]; 1374 u8 macsec_crypto_esp_aes_gcm_256_encrypt[0x1]; 1375 u8 macsec_crypto_esp_aes_gcm_128_encrypt[0x1]; 1376 u8 macsec_crypto_esp_aes_gcm_256_decrypt[0x1]; 1377 u8 macsec_crypto_esp_aes_gcm_128_decrypt[0x1]; 1378 u8 reserved_at_7[0x4]; 1379 u8 log_max_macsec_offload[0x5]; 1380 u8 reserved_at_10[0x10]; 1381 1382 u8 min_log_macsec_full_replay_window[0x8]; 1383 u8 max_log_macsec_full_replay_window[0x8]; 1384 u8 reserved_at_30[0x10]; 1385 1386 u8 reserved_at_40[0x7c0]; 1387 }; 1388 1389 enum { 1390 MLX5_WQ_TYPE_LINKED_LIST = 0x0, 1391 MLX5_WQ_TYPE_CYCLIC = 0x1, 1392 MLX5_WQ_TYPE_LINKED_LIST_STRIDING_RQ = 0x2, 1393 MLX5_WQ_TYPE_CYCLIC_STRIDING_RQ = 0x3, 1394 }; 1395 1396 enum { 1397 MLX5_WQ_END_PAD_MODE_NONE = 0x0, 1398 MLX5_WQ_END_PAD_MODE_ALIGN = 0x1, 1399 }; 1400 1401 enum { 1402 MLX5_CMD_HCA_CAP_GID_TABLE_SIZE_8_GID_ENTRIES = 0x0, 1403 MLX5_CMD_HCA_CAP_GID_TABLE_SIZE_16_GID_ENTRIES = 0x1, 1404 MLX5_CMD_HCA_CAP_GID_TABLE_SIZE_32_GID_ENTRIES = 0x2, 1405 MLX5_CMD_HCA_CAP_GID_TABLE_SIZE_64_GID_ENTRIES = 0x3, 1406 MLX5_CMD_HCA_CAP_GID_TABLE_SIZE_128_GID_ENTRIES = 0x4, 1407 }; 1408 1409 enum { 1410 MLX5_CMD_HCA_CAP_PKEY_TABLE_SIZE_128_ENTRIES = 0x0, 1411 MLX5_CMD_HCA_CAP_PKEY_TABLE_SIZE_256_ENTRIES = 0x1, 1412 MLX5_CMD_HCA_CAP_PKEY_TABLE_SIZE_512_ENTRIES = 0x2, 1413 MLX5_CMD_HCA_CAP_PKEY_TABLE_SIZE_1K_ENTRIES = 0x3, 1414 MLX5_CMD_HCA_CAP_PKEY_TABLE_SIZE_2K_ENTRIES = 0x4, 1415 MLX5_CMD_HCA_CAP_PKEY_TABLE_SIZE_4K_ENTRIES = 0x5, 1416 }; 1417 1418 enum { 1419 MLX5_CMD_HCA_CAP_PORT_TYPE_IB = 0x0, 1420 MLX5_CMD_HCA_CAP_PORT_TYPE_ETHERNET = 0x1, 1421 }; 1422 1423 enum { 1424 MLX5_CMD_HCA_CAP_CMDIF_CHECKSUM_DISABLED = 0x0, 1425 MLX5_CMD_HCA_CAP_CMDIF_CHECKSUM_INITIAL_STATE = 0x1, 1426 MLX5_CMD_HCA_CAP_CMDIF_CHECKSUM_ENABLED = 0x3, 1427 }; 1428 1429 enum { 1430 MLX5_CAP_PORT_TYPE_IB = 0x0, 1431 MLX5_CAP_PORT_TYPE_ETH = 0x1, 1432 }; 1433 1434 enum { 1435 MLX5_CAP_UMR_FENCE_STRONG = 0x0, 1436 MLX5_CAP_UMR_FENCE_SMALL = 0x1, 1437 MLX5_CAP_UMR_FENCE_NONE = 0x2, 1438 }; 1439 1440 enum { 1441 MLX5_FLEX_PARSER_GENEVE_ENABLED = 1 << 3, 1442 MLX5_FLEX_PARSER_MPLS_OVER_GRE_ENABLED = 1 << 4, 1443 MLX5_FLEX_PARSER_MPLS_OVER_UDP_ENABLED = 1 << 5, 1444 MLX5_FLEX_PARSER_VXLAN_GPE_ENABLED = 1 << 7, 1445 MLX5_FLEX_PARSER_ICMP_V4_ENABLED = 1 << 8, 1446 MLX5_FLEX_PARSER_ICMP_V6_ENABLED = 1 << 9, 1447 MLX5_FLEX_PARSER_GENEVE_TLV_OPTION_0_ENABLED = 1 << 10, 1448 MLX5_FLEX_PARSER_GTPU_ENABLED = 1 << 11, 1449 MLX5_FLEX_PARSER_GTPU_DW_2_ENABLED = 1 << 16, 1450 MLX5_FLEX_PARSER_GTPU_FIRST_EXT_DW_0_ENABLED = 1 << 17, 1451 MLX5_FLEX_PARSER_GTPU_DW_0_ENABLED = 1 << 18, 1452 MLX5_FLEX_PARSER_GTPU_TEID_ENABLED = 1 << 19, 1453 }; 1454 1455 enum { 1456 MLX5_UCTX_CAP_RAW_TX = 1UL << 0, 1457 MLX5_UCTX_CAP_INTERNAL_DEV_RES = 1UL << 1, 1458 }; 1459 1460 #define MLX5_FC_BULK_SIZE_FACTOR 128 1461 1462 enum mlx5_fc_bulk_alloc_bitmask { 1463 MLX5_FC_BULK_128 = (1 << 0), 1464 MLX5_FC_BULK_256 = (1 << 1), 1465 MLX5_FC_BULK_512 = (1 << 2), 1466 MLX5_FC_BULK_1024 = (1 << 3), 1467 MLX5_FC_BULK_2048 = (1 << 4), 1468 MLX5_FC_BULK_4096 = (1 << 5), 1469 MLX5_FC_BULK_8192 = (1 << 6), 1470 MLX5_FC_BULK_16384 = (1 << 7), 1471 }; 1472 1473 #define MLX5_FC_BULK_NUM_FCS(fc_enum) (MLX5_FC_BULK_SIZE_FACTOR * (fc_enum)) 1474 1475 #define MLX5_FT_MAX_MULTIPATH_LEVEL 63 1476 1477 enum { 1478 MLX5_STEERING_FORMAT_CONNECTX_5 = 0, 1479 MLX5_STEERING_FORMAT_CONNECTX_6DX = 1, 1480 MLX5_STEERING_FORMAT_CONNECTX_7 = 2, 1481 }; 1482 1483 struct mlx5_ifc_cmd_hca_cap_bits { 1484 u8 reserved_at_0[0x10]; 1485 u8 shared_object_to_user_object_allowed[0x1]; 1486 u8 reserved_at_13[0xe]; 1487 u8 vhca_resource_manager[0x1]; 1488 1489 u8 hca_cap_2[0x1]; 1490 u8 create_lag_when_not_master_up[0x1]; 1491 u8 dtor[0x1]; 1492 u8 event_on_vhca_state_teardown_request[0x1]; 1493 u8 event_on_vhca_state_in_use[0x1]; 1494 u8 event_on_vhca_state_active[0x1]; 1495 u8 event_on_vhca_state_allocated[0x1]; 1496 u8 event_on_vhca_state_invalid[0x1]; 1497 u8 reserved_at_28[0x8]; 1498 u8 vhca_id[0x10]; 1499 1500 u8 reserved_at_40[0x40]; 1501 1502 u8 log_max_srq_sz[0x8]; 1503 u8 log_max_qp_sz[0x8]; 1504 u8 event_cap[0x1]; 1505 u8 reserved_at_91[0x2]; 1506 u8 isolate_vl_tc_new[0x1]; 1507 u8 reserved_at_94[0x4]; 1508 u8 prio_tag_required[0x1]; 1509 u8 reserved_at_99[0x2]; 1510 u8 log_max_qp[0x5]; 1511 1512 u8 reserved_at_a0[0x3]; 1513 u8 ece_support[0x1]; 1514 u8 reserved_at_a4[0x5]; 1515 u8 reg_c_preserve[0x1]; 1516 u8 reserved_at_aa[0x1]; 1517 u8 log_max_srq[0x5]; 1518 u8 reserved_at_b0[0x1]; 1519 u8 uplink_follow[0x1]; 1520 u8 ts_cqe_to_dest_cqn[0x1]; 1521 u8 reserved_at_b3[0x6]; 1522 u8 go_back_n[0x1]; 1523 u8 shampo[0x1]; 1524 u8 reserved_at_bb[0x5]; 1525 1526 u8 max_sgl_for_optimized_performance[0x8]; 1527 u8 log_max_cq_sz[0x8]; 1528 u8 relaxed_ordering_write_umr[0x1]; 1529 u8 relaxed_ordering_read_umr[0x1]; 1530 u8 reserved_at_d2[0x7]; 1531 u8 virtio_net_device_emualtion_manager[0x1]; 1532 u8 virtio_blk_device_emualtion_manager[0x1]; 1533 u8 log_max_cq[0x5]; 1534 1535 u8 log_max_eq_sz[0x8]; 1536 u8 relaxed_ordering_write[0x1]; 1537 u8 relaxed_ordering_read_pci_enabled[0x1]; 1538 u8 log_max_mkey[0x6]; 1539 u8 reserved_at_f0[0x6]; 1540 u8 terminate_scatter_list_mkey[0x1]; 1541 u8 repeated_mkey[0x1]; 1542 u8 dump_fill_mkey[0x1]; 1543 u8 reserved_at_f9[0x2]; 1544 u8 fast_teardown[0x1]; 1545 u8 log_max_eq[0x4]; 1546 1547 u8 max_indirection[0x8]; 1548 u8 fixed_buffer_size[0x1]; 1549 u8 log_max_mrw_sz[0x7]; 1550 u8 force_teardown[0x1]; 1551 u8 reserved_at_111[0x1]; 1552 u8 log_max_bsf_list_size[0x6]; 1553 u8 umr_extended_translation_offset[0x1]; 1554 u8 null_mkey[0x1]; 1555 u8 log_max_klm_list_size[0x6]; 1556 1557 u8 reserved_at_120[0x2]; 1558 u8 qpc_extension[0x1]; 1559 u8 reserved_at_123[0x7]; 1560 u8 log_max_ra_req_dc[0x6]; 1561 u8 reserved_at_130[0x2]; 1562 u8 eth_wqe_too_small[0x1]; 1563 u8 reserved_at_133[0x6]; 1564 u8 vnic_env_cq_overrun[0x1]; 1565 u8 log_max_ra_res_dc[0x6]; 1566 1567 u8 reserved_at_140[0x5]; 1568 u8 release_all_pages[0x1]; 1569 u8 must_not_use[0x1]; 1570 u8 reserved_at_147[0x2]; 1571 u8 roce_accl[0x1]; 1572 u8 log_max_ra_req_qp[0x6]; 1573 u8 reserved_at_150[0xa]; 1574 u8 log_max_ra_res_qp[0x6]; 1575 1576 u8 end_pad[0x1]; 1577 u8 cc_query_allowed[0x1]; 1578 u8 cc_modify_allowed[0x1]; 1579 u8 start_pad[0x1]; 1580 u8 cache_line_128byte[0x1]; 1581 u8 reserved_at_165[0x4]; 1582 u8 rts2rts_qp_counters_set_id[0x1]; 1583 u8 reserved_at_16a[0x2]; 1584 u8 vnic_env_int_rq_oob[0x1]; 1585 u8 sbcam_reg[0x1]; 1586 u8 reserved_at_16e[0x1]; 1587 u8 qcam_reg[0x1]; 1588 u8 gid_table_size[0x10]; 1589 1590 u8 out_of_seq_cnt[0x1]; 1591 u8 vport_counters[0x1]; 1592 u8 retransmission_q_counters[0x1]; 1593 u8 debug[0x1]; 1594 u8 modify_rq_counter_set_id[0x1]; 1595 u8 rq_delay_drop[0x1]; 1596 u8 max_qp_cnt[0xa]; 1597 u8 pkey_table_size[0x10]; 1598 1599 u8 vport_group_manager[0x1]; 1600 u8 vhca_group_manager[0x1]; 1601 u8 ib_virt[0x1]; 1602 u8 eth_virt[0x1]; 1603 u8 vnic_env_queue_counters[0x1]; 1604 u8 ets[0x1]; 1605 u8 nic_flow_table[0x1]; 1606 u8 eswitch_manager[0x1]; 1607 u8 device_memory[0x1]; 1608 u8 mcam_reg[0x1]; 1609 u8 pcam_reg[0x1]; 1610 u8 local_ca_ack_delay[0x5]; 1611 u8 port_module_event[0x1]; 1612 u8 enhanced_error_q_counters[0x1]; 1613 u8 ports_check[0x1]; 1614 u8 reserved_at_1b3[0x1]; 1615 u8 disable_link_up[0x1]; 1616 u8 beacon_led[0x1]; 1617 u8 port_type[0x2]; 1618 u8 num_ports[0x8]; 1619 1620 u8 reserved_at_1c0[0x1]; 1621 u8 pps[0x1]; 1622 u8 pps_modify[0x1]; 1623 u8 log_max_msg[0x5]; 1624 u8 reserved_at_1c8[0x4]; 1625 u8 max_tc[0x4]; 1626 u8 temp_warn_event[0x1]; 1627 u8 dcbx[0x1]; 1628 u8 general_notification_event[0x1]; 1629 u8 reserved_at_1d3[0x2]; 1630 u8 fpga[0x1]; 1631 u8 rol_s[0x1]; 1632 u8 rol_g[0x1]; 1633 u8 reserved_at_1d8[0x1]; 1634 u8 wol_s[0x1]; 1635 u8 wol_g[0x1]; 1636 u8 wol_a[0x1]; 1637 u8 wol_b[0x1]; 1638 u8 wol_m[0x1]; 1639 u8 wol_u[0x1]; 1640 u8 wol_p[0x1]; 1641 1642 u8 stat_rate_support[0x10]; 1643 u8 reserved_at_1f0[0x1]; 1644 u8 pci_sync_for_fw_update_event[0x1]; 1645 u8 reserved_at_1f2[0x6]; 1646 u8 init2_lag_tx_port_affinity[0x1]; 1647 u8 reserved_at_1fa[0x3]; 1648 u8 cqe_version[0x4]; 1649 1650 u8 compact_address_vector[0x1]; 1651 u8 striding_rq[0x1]; 1652 u8 reserved_at_202[0x1]; 1653 u8 ipoib_enhanced_offloads[0x1]; 1654 u8 ipoib_basic_offloads[0x1]; 1655 u8 reserved_at_205[0x1]; 1656 u8 repeated_block_disabled[0x1]; 1657 u8 umr_modify_entity_size_disabled[0x1]; 1658 u8 umr_modify_atomic_disabled[0x1]; 1659 u8 umr_indirect_mkey_disabled[0x1]; 1660 u8 umr_fence[0x2]; 1661 u8 dc_req_scat_data_cqe[0x1]; 1662 u8 reserved_at_20d[0x2]; 1663 u8 drain_sigerr[0x1]; 1664 u8 cmdif_checksum[0x2]; 1665 u8 sigerr_cqe[0x1]; 1666 u8 reserved_at_213[0x1]; 1667 u8 wq_signature[0x1]; 1668 u8 sctr_data_cqe[0x1]; 1669 u8 reserved_at_216[0x1]; 1670 u8 sho[0x1]; 1671 u8 tph[0x1]; 1672 u8 rf[0x1]; 1673 u8 dct[0x1]; 1674 u8 qos[0x1]; 1675 u8 eth_net_offloads[0x1]; 1676 u8 roce[0x1]; 1677 u8 atomic[0x1]; 1678 u8 reserved_at_21f[0x1]; 1679 1680 u8 cq_oi[0x1]; 1681 u8 cq_resize[0x1]; 1682 u8 cq_moderation[0x1]; 1683 u8 reserved_at_223[0x3]; 1684 u8 cq_eq_remap[0x1]; 1685 u8 pg[0x1]; 1686 u8 block_lb_mc[0x1]; 1687 u8 reserved_at_229[0x1]; 1688 u8 scqe_break_moderation[0x1]; 1689 u8 cq_period_start_from_cqe[0x1]; 1690 u8 cd[0x1]; 1691 u8 reserved_at_22d[0x1]; 1692 u8 apm[0x1]; 1693 u8 vector_calc[0x1]; 1694 u8 umr_ptr_rlky[0x1]; 1695 u8 imaicl[0x1]; 1696 u8 qp_packet_based[0x1]; 1697 u8 reserved_at_233[0x3]; 1698 u8 qkv[0x1]; 1699 u8 pkv[0x1]; 1700 u8 set_deth_sqpn[0x1]; 1701 u8 reserved_at_239[0x3]; 1702 u8 xrc[0x1]; 1703 u8 ud[0x1]; 1704 u8 uc[0x1]; 1705 u8 rc[0x1]; 1706 1707 u8 uar_4k[0x1]; 1708 u8 reserved_at_241[0x7]; 1709 u8 fl_rc_qp_when_roce_disabled[0x1]; 1710 u8 regexp_params[0x1]; 1711 u8 uar_sz[0x6]; 1712 u8 port_selection_cap[0x1]; 1713 u8 reserved_at_248[0x1]; 1714 u8 umem_uid_0[0x1]; 1715 u8 reserved_at_250[0x5]; 1716 u8 log_pg_sz[0x8]; 1717 1718 u8 bf[0x1]; 1719 u8 driver_version[0x1]; 1720 u8 pad_tx_eth_packet[0x1]; 1721 u8 reserved_at_263[0x3]; 1722 u8 mkey_by_name[0x1]; 1723 u8 reserved_at_267[0x4]; 1724 1725 u8 log_bf_reg_size[0x5]; 1726 1727 u8 reserved_at_270[0x3]; 1728 u8 qp_error_syndrome[0x1]; 1729 u8 reserved_at_274[0x2]; 1730 u8 lag_dct[0x2]; 1731 u8 lag_tx_port_affinity[0x1]; 1732 u8 lag_native_fdb_selection[0x1]; 1733 u8 reserved_at_27a[0x1]; 1734 u8 lag_master[0x1]; 1735 u8 num_lag_ports[0x4]; 1736 1737 u8 reserved_at_280[0x10]; 1738 u8 max_wqe_sz_sq[0x10]; 1739 1740 u8 reserved_at_2a0[0x10]; 1741 u8 max_wqe_sz_rq[0x10]; 1742 1743 u8 max_flow_counter_31_16[0x10]; 1744 u8 max_wqe_sz_sq_dc[0x10]; 1745 1746 u8 reserved_at_2e0[0x7]; 1747 u8 max_qp_mcg[0x19]; 1748 1749 u8 reserved_at_300[0x10]; 1750 u8 flow_counter_bulk_alloc[0x8]; 1751 u8 log_max_mcg[0x8]; 1752 1753 u8 reserved_at_320[0x3]; 1754 u8 log_max_transport_domain[0x5]; 1755 u8 reserved_at_328[0x2]; 1756 u8 relaxed_ordering_read[0x1]; 1757 u8 log_max_pd[0x5]; 1758 u8 reserved_at_330[0x9]; 1759 u8 q_counter_aggregation[0x1]; 1760 u8 q_counter_other_vport[0x1]; 1761 u8 log_max_xrcd[0x5]; 1762 1763 u8 nic_receive_steering_discard[0x1]; 1764 u8 receive_discard_vport_down[0x1]; 1765 u8 transmit_discard_vport_down[0x1]; 1766 u8 eq_overrun_count[0x1]; 1767 u8 reserved_at_344[0x1]; 1768 u8 invalid_command_count[0x1]; 1769 u8 quota_exceeded_count[0x1]; 1770 u8 reserved_at_347[0x1]; 1771 u8 log_max_flow_counter_bulk[0x8]; 1772 u8 max_flow_counter_15_0[0x10]; 1773 1774 1775 u8 reserved_at_360[0x3]; 1776 u8 log_max_rq[0x5]; 1777 u8 reserved_at_368[0x3]; 1778 u8 log_max_sq[0x5]; 1779 u8 reserved_at_370[0x3]; 1780 u8 log_max_tir[0x5]; 1781 u8 reserved_at_378[0x3]; 1782 u8 log_max_tis[0x5]; 1783 1784 u8 basic_cyclic_rcv_wqe[0x1]; 1785 u8 reserved_at_381[0x2]; 1786 u8 log_max_rmp[0x5]; 1787 u8 reserved_at_388[0x3]; 1788 u8 log_max_rqt[0x5]; 1789 u8 reserved_at_390[0x3]; 1790 u8 log_max_rqt_size[0x5]; 1791 u8 reserved_at_398[0x3]; 1792 u8 log_max_tis_per_sq[0x5]; 1793 1794 u8 ext_stride_num_range[0x1]; 1795 u8 roce_rw_supported[0x1]; 1796 u8 log_max_current_uc_list_wr_supported[0x1]; 1797 u8 log_max_stride_sz_rq[0x5]; 1798 u8 reserved_at_3a8[0x3]; 1799 u8 log_min_stride_sz_rq[0x5]; 1800 u8 reserved_at_3b0[0x3]; 1801 u8 log_max_stride_sz_sq[0x5]; 1802 u8 reserved_at_3b8[0x3]; 1803 u8 log_min_stride_sz_sq[0x5]; 1804 1805 u8 hairpin[0x1]; 1806 u8 reserved_at_3c1[0x2]; 1807 u8 log_max_hairpin_queues[0x5]; 1808 u8 reserved_at_3c8[0x3]; 1809 u8 log_max_hairpin_wq_data_sz[0x5]; 1810 u8 reserved_at_3d0[0x3]; 1811 u8 log_max_hairpin_num_packets[0x5]; 1812 u8 reserved_at_3d8[0x3]; 1813 u8 log_max_wq_sz[0x5]; 1814 1815 u8 nic_vport_change_event[0x1]; 1816 u8 disable_local_lb_uc[0x1]; 1817 u8 disable_local_lb_mc[0x1]; 1818 u8 log_min_hairpin_wq_data_sz[0x5]; 1819 u8 reserved_at_3e8[0x2]; 1820 u8 vhca_state[0x1]; 1821 u8 log_max_vlan_list[0x5]; 1822 u8 reserved_at_3f0[0x3]; 1823 u8 log_max_current_mc_list[0x5]; 1824 u8 reserved_at_3f8[0x3]; 1825 u8 log_max_current_uc_list[0x5]; 1826 1827 u8 general_obj_types[0x40]; 1828 1829 u8 sq_ts_format[0x2]; 1830 u8 rq_ts_format[0x2]; 1831 u8 steering_format_version[0x4]; 1832 u8 create_qp_start_hint[0x18]; 1833 1834 u8 reserved_at_460[0x1]; 1835 u8 ats[0x1]; 1836 u8 reserved_at_462[0x1]; 1837 u8 log_max_uctx[0x5]; 1838 u8 reserved_at_468[0x1]; 1839 u8 crypto[0x1]; 1840 u8 ipsec_offload[0x1]; 1841 u8 log_max_umem[0x5]; 1842 u8 max_num_eqs[0x10]; 1843 1844 u8 reserved_at_480[0x1]; 1845 u8 tls_tx[0x1]; 1846 u8 tls_rx[0x1]; 1847 u8 log_max_l2_table[0x5]; 1848 u8 reserved_at_488[0x8]; 1849 u8 log_uar_page_sz[0x10]; 1850 1851 u8 reserved_at_4a0[0x20]; 1852 u8 device_frequency_mhz[0x20]; 1853 u8 device_frequency_khz[0x20]; 1854 1855 u8 reserved_at_500[0x20]; 1856 u8 num_of_uars_per_page[0x20]; 1857 1858 u8 flex_parser_protocols[0x20]; 1859 1860 u8 max_geneve_tlv_options[0x8]; 1861 u8 reserved_at_568[0x3]; 1862 u8 max_geneve_tlv_option_data_len[0x5]; 1863 u8 reserved_at_570[0x9]; 1864 u8 adv_virtualization[0x1]; 1865 u8 reserved_at_57a[0x6]; 1866 1867 u8 reserved_at_580[0xb]; 1868 u8 log_max_dci_stream_channels[0x5]; 1869 u8 reserved_at_590[0x3]; 1870 u8 log_max_dci_errored_streams[0x5]; 1871 u8 reserved_at_598[0x8]; 1872 1873 u8 reserved_at_5a0[0x10]; 1874 u8 enhanced_cqe_compression[0x1]; 1875 u8 reserved_at_5b1[0x2]; 1876 u8 log_max_dek[0x5]; 1877 u8 reserved_at_5b8[0x4]; 1878 u8 mini_cqe_resp_stride_index[0x1]; 1879 u8 cqe_128_always[0x1]; 1880 u8 cqe_compression_128[0x1]; 1881 u8 cqe_compression[0x1]; 1882 1883 u8 cqe_compression_timeout[0x10]; 1884 u8 cqe_compression_max_num[0x10]; 1885 1886 u8 reserved_at_5e0[0x8]; 1887 u8 flex_parser_id_gtpu_dw_0[0x4]; 1888 u8 reserved_at_5ec[0x4]; 1889 u8 tag_matching[0x1]; 1890 u8 rndv_offload_rc[0x1]; 1891 u8 rndv_offload_dc[0x1]; 1892 u8 log_tag_matching_list_sz[0x5]; 1893 u8 reserved_at_5f8[0x3]; 1894 u8 log_max_xrq[0x5]; 1895 1896 u8 affiliate_nic_vport_criteria[0x8]; 1897 u8 native_port_num[0x8]; 1898 u8 num_vhca_ports[0x8]; 1899 u8 flex_parser_id_gtpu_teid[0x4]; 1900 u8 reserved_at_61c[0x2]; 1901 u8 sw_owner_id[0x1]; 1902 u8 reserved_at_61f[0x1]; 1903 1904 u8 max_num_of_monitor_counters[0x10]; 1905 u8 num_ppcnt_monitor_counters[0x10]; 1906 1907 u8 max_num_sf[0x10]; 1908 u8 num_q_monitor_counters[0x10]; 1909 1910 u8 reserved_at_660[0x20]; 1911 1912 u8 sf[0x1]; 1913 u8 sf_set_partition[0x1]; 1914 u8 reserved_at_682[0x1]; 1915 u8 log_max_sf[0x5]; 1916 u8 apu[0x1]; 1917 u8 reserved_at_689[0x4]; 1918 u8 migration[0x1]; 1919 u8 reserved_at_68e[0x2]; 1920 u8 log_min_sf_size[0x8]; 1921 u8 max_num_sf_partitions[0x8]; 1922 1923 u8 uctx_cap[0x20]; 1924 1925 u8 reserved_at_6c0[0x4]; 1926 u8 flex_parser_id_geneve_tlv_option_0[0x4]; 1927 u8 flex_parser_id_icmp_dw1[0x4]; 1928 u8 flex_parser_id_icmp_dw0[0x4]; 1929 u8 flex_parser_id_icmpv6_dw1[0x4]; 1930 u8 flex_parser_id_icmpv6_dw0[0x4]; 1931 u8 flex_parser_id_outer_first_mpls_over_gre[0x4]; 1932 u8 flex_parser_id_outer_first_mpls_over_udp_label[0x4]; 1933 1934 u8 max_num_match_definer[0x10]; 1935 u8 sf_base_id[0x10]; 1936 1937 u8 flex_parser_id_gtpu_dw_2[0x4]; 1938 u8 flex_parser_id_gtpu_first_ext_dw_0[0x4]; 1939 u8 num_total_dynamic_vf_msix[0x18]; 1940 u8 reserved_at_720[0x14]; 1941 u8 dynamic_msix_table_size[0xc]; 1942 u8 reserved_at_740[0xc]; 1943 u8 min_dynamic_vf_msix_table_size[0x4]; 1944 u8 reserved_at_750[0x4]; 1945 u8 max_dynamic_vf_msix_table_size[0xc]; 1946 1947 u8 reserved_at_760[0x3]; 1948 u8 log_max_num_header_modify_argument[0x5]; 1949 u8 reserved_at_768[0x4]; 1950 u8 log_header_modify_argument_granularity[0x4]; 1951 u8 reserved_at_770[0x3]; 1952 u8 log_header_modify_argument_max_alloc[0x5]; 1953 u8 reserved_at_778[0x8]; 1954 1955 u8 vhca_tunnel_commands[0x40]; 1956 u8 match_definer_format_supported[0x40]; 1957 }; 1958 1959 struct mlx5_ifc_cmd_hca_cap_2_bits { 1960 u8 reserved_at_0[0x80]; 1961 1962 u8 migratable[0x1]; 1963 u8 reserved_at_81[0x1f]; 1964 1965 u8 max_reformat_insert_size[0x8]; 1966 u8 max_reformat_insert_offset[0x8]; 1967 u8 max_reformat_remove_size[0x8]; 1968 u8 max_reformat_remove_offset[0x8]; 1969 1970 u8 reserved_at_c0[0x8]; 1971 u8 migration_multi_load[0x1]; 1972 u8 migration_tracking_state[0x1]; 1973 u8 reserved_at_ca[0x16]; 1974 1975 u8 reserved_at_e0[0xc0]; 1976 1977 u8 flow_table_type_2_type[0x8]; 1978 u8 reserved_at_1a8[0x3]; 1979 u8 log_min_mkey_entity_size[0x5]; 1980 u8 reserved_at_1b0[0x10]; 1981 1982 u8 reserved_at_1c0[0x60]; 1983 1984 u8 reserved_at_220[0x1]; 1985 u8 sw_vhca_id_valid[0x1]; 1986 u8 sw_vhca_id[0xe]; 1987 u8 reserved_at_230[0x10]; 1988 1989 u8 reserved_at_240[0xb]; 1990 u8 ts_cqe_metadata_size2wqe_counter[0x5]; 1991 u8 reserved_at_250[0x10]; 1992 1993 u8 reserved_at_260[0x5a0]; 1994 }; 1995 1996 enum mlx5_ifc_flow_destination_type { 1997 MLX5_IFC_FLOW_DESTINATION_TYPE_VPORT = 0x0, 1998 MLX5_IFC_FLOW_DESTINATION_TYPE_FLOW_TABLE = 0x1, 1999 MLX5_IFC_FLOW_DESTINATION_TYPE_TIR = 0x2, 2000 MLX5_IFC_FLOW_DESTINATION_TYPE_FLOW_SAMPLER = 0x6, 2001 MLX5_IFC_FLOW_DESTINATION_TYPE_UPLINK = 0x8, 2002 MLX5_IFC_FLOW_DESTINATION_TYPE_TABLE_TYPE = 0xA, 2003 }; 2004 2005 enum mlx5_flow_table_miss_action { 2006 MLX5_FLOW_TABLE_MISS_ACTION_DEF, 2007 MLX5_FLOW_TABLE_MISS_ACTION_FWD, 2008 MLX5_FLOW_TABLE_MISS_ACTION_SWITCH_DOMAIN, 2009 }; 2010 2011 struct mlx5_ifc_dest_format_struct_bits { 2012 u8 destination_type[0x8]; 2013 u8 destination_id[0x18]; 2014 2015 u8 destination_eswitch_owner_vhca_id_valid[0x1]; 2016 u8 packet_reformat[0x1]; 2017 u8 reserved_at_22[0x6]; 2018 u8 destination_table_type[0x8]; 2019 u8 destination_eswitch_owner_vhca_id[0x10]; 2020 }; 2021 2022 struct mlx5_ifc_flow_counter_list_bits { 2023 u8 flow_counter_id[0x20]; 2024 2025 u8 reserved_at_20[0x20]; 2026 }; 2027 2028 struct mlx5_ifc_extended_dest_format_bits { 2029 struct mlx5_ifc_dest_format_struct_bits destination_entry; 2030 2031 u8 packet_reformat_id[0x20]; 2032 2033 u8 reserved_at_60[0x20]; 2034 }; 2035 2036 union mlx5_ifc_dest_format_struct_flow_counter_list_auto_bits { 2037 struct mlx5_ifc_extended_dest_format_bits extended_dest_format; 2038 struct mlx5_ifc_flow_counter_list_bits flow_counter_list; 2039 }; 2040 2041 struct mlx5_ifc_fte_match_param_bits { 2042 struct mlx5_ifc_fte_match_set_lyr_2_4_bits outer_headers; 2043 2044 struct mlx5_ifc_fte_match_set_misc_bits misc_parameters; 2045 2046 struct mlx5_ifc_fte_match_set_lyr_2_4_bits inner_headers; 2047 2048 struct mlx5_ifc_fte_match_set_misc2_bits misc_parameters_2; 2049 2050 struct mlx5_ifc_fte_match_set_misc3_bits misc_parameters_3; 2051 2052 struct mlx5_ifc_fte_match_set_misc4_bits misc_parameters_4; 2053 2054 struct mlx5_ifc_fte_match_set_misc5_bits misc_parameters_5; 2055 2056 u8 reserved_at_e00[0x200]; 2057 }; 2058 2059 enum { 2060 MLX5_RX_HASH_FIELD_SELECT_SELECTED_FIELDS_SRC_IP = 0x0, 2061 MLX5_RX_HASH_FIELD_SELECT_SELECTED_FIELDS_DST_IP = 0x1, 2062 MLX5_RX_HASH_FIELD_SELECT_SELECTED_FIELDS_L4_SPORT = 0x2, 2063 MLX5_RX_HASH_FIELD_SELECT_SELECTED_FIELDS_L4_DPORT = 0x3, 2064 MLX5_RX_HASH_FIELD_SELECT_SELECTED_FIELDS_IPSEC_SPI = 0x4, 2065 }; 2066 2067 struct mlx5_ifc_rx_hash_field_select_bits { 2068 u8 l3_prot_type[0x1]; 2069 u8 l4_prot_type[0x1]; 2070 u8 selected_fields[0x1e]; 2071 }; 2072 2073 enum { 2074 MLX5_WQ_WQ_TYPE_WQ_LINKED_LIST = 0x0, 2075 MLX5_WQ_WQ_TYPE_WQ_CYCLIC = 0x1, 2076 }; 2077 2078 enum { 2079 MLX5_WQ_END_PADDING_MODE_END_PAD_NONE = 0x0, 2080 MLX5_WQ_END_PADDING_MODE_END_PAD_ALIGN = 0x1, 2081 }; 2082 2083 struct mlx5_ifc_wq_bits { 2084 u8 wq_type[0x4]; 2085 u8 wq_signature[0x1]; 2086 u8 end_padding_mode[0x2]; 2087 u8 cd_slave[0x1]; 2088 u8 reserved_at_8[0x18]; 2089 2090 u8 hds_skip_first_sge[0x1]; 2091 u8 log2_hds_buf_size[0x3]; 2092 u8 reserved_at_24[0x7]; 2093 u8 page_offset[0x5]; 2094 u8 lwm[0x10]; 2095 2096 u8 reserved_at_40[0x8]; 2097 u8 pd[0x18]; 2098 2099 u8 reserved_at_60[0x8]; 2100 u8 uar_page[0x18]; 2101 2102 u8 dbr_addr[0x40]; 2103 2104 u8 hw_counter[0x20]; 2105 2106 u8 sw_counter[0x20]; 2107 2108 u8 reserved_at_100[0xc]; 2109 u8 log_wq_stride[0x4]; 2110 u8 reserved_at_110[0x3]; 2111 u8 log_wq_pg_sz[0x5]; 2112 u8 reserved_at_118[0x3]; 2113 u8 log_wq_sz[0x5]; 2114 2115 u8 dbr_umem_valid[0x1]; 2116 u8 wq_umem_valid[0x1]; 2117 u8 reserved_at_122[0x1]; 2118 u8 log_hairpin_num_packets[0x5]; 2119 u8 reserved_at_128[0x3]; 2120 u8 log_hairpin_data_sz[0x5]; 2121 2122 u8 reserved_at_130[0x4]; 2123 u8 log_wqe_num_of_strides[0x4]; 2124 u8 two_byte_shift_en[0x1]; 2125 u8 reserved_at_139[0x4]; 2126 u8 log_wqe_stride_size[0x3]; 2127 2128 u8 reserved_at_140[0x80]; 2129 2130 u8 headers_mkey[0x20]; 2131 2132 u8 shampo_enable[0x1]; 2133 u8 reserved_at_1e1[0x4]; 2134 u8 log_reservation_size[0x3]; 2135 u8 reserved_at_1e8[0x5]; 2136 u8 log_max_num_of_packets_per_reservation[0x3]; 2137 u8 reserved_at_1f0[0x6]; 2138 u8 log_headers_entry_size[0x2]; 2139 u8 reserved_at_1f8[0x4]; 2140 u8 log_headers_buffer_entry_num[0x4]; 2141 2142 u8 reserved_at_200[0x400]; 2143 2144 struct mlx5_ifc_cmd_pas_bits pas[]; 2145 }; 2146 2147 struct mlx5_ifc_rq_num_bits { 2148 u8 reserved_at_0[0x8]; 2149 u8 rq_num[0x18]; 2150 }; 2151 2152 struct mlx5_ifc_mac_address_layout_bits { 2153 u8 reserved_at_0[0x10]; 2154 u8 mac_addr_47_32[0x10]; 2155 2156 u8 mac_addr_31_0[0x20]; 2157 }; 2158 2159 struct mlx5_ifc_vlan_layout_bits { 2160 u8 reserved_at_0[0x14]; 2161 u8 vlan[0x0c]; 2162 2163 u8 reserved_at_20[0x20]; 2164 }; 2165 2166 struct mlx5_ifc_cong_control_r_roce_ecn_np_bits { 2167 u8 reserved_at_0[0xa0]; 2168 2169 u8 min_time_between_cnps[0x20]; 2170 2171 u8 reserved_at_c0[0x12]; 2172 u8 cnp_dscp[0x6]; 2173 u8 reserved_at_d8[0x4]; 2174 u8 cnp_prio_mode[0x1]; 2175 u8 cnp_802p_prio[0x3]; 2176 2177 u8 reserved_at_e0[0x720]; 2178 }; 2179 2180 struct mlx5_ifc_cong_control_r_roce_ecn_rp_bits { 2181 u8 reserved_at_0[0x60]; 2182 2183 u8 reserved_at_60[0x4]; 2184 u8 clamp_tgt_rate[0x1]; 2185 u8 reserved_at_65[0x3]; 2186 u8 clamp_tgt_rate_after_time_inc[0x1]; 2187 u8 reserved_at_69[0x17]; 2188 2189 u8 reserved_at_80[0x20]; 2190 2191 u8 rpg_time_reset[0x20]; 2192 2193 u8 rpg_byte_reset[0x20]; 2194 2195 u8 rpg_threshold[0x20]; 2196 2197 u8 rpg_max_rate[0x20]; 2198 2199 u8 rpg_ai_rate[0x20]; 2200 2201 u8 rpg_hai_rate[0x20]; 2202 2203 u8 rpg_gd[0x20]; 2204 2205 u8 rpg_min_dec_fac[0x20]; 2206 2207 u8 rpg_min_rate[0x20]; 2208 2209 u8 reserved_at_1c0[0xe0]; 2210 2211 u8 rate_to_set_on_first_cnp[0x20]; 2212 2213 u8 dce_tcp_g[0x20]; 2214 2215 u8 dce_tcp_rtt[0x20]; 2216 2217 u8 rate_reduce_monitor_period[0x20]; 2218 2219 u8 reserved_at_320[0x20]; 2220 2221 u8 initial_alpha_value[0x20]; 2222 2223 u8 reserved_at_360[0x4a0]; 2224 }; 2225 2226 struct mlx5_ifc_cong_control_r_roce_general_bits { 2227 u8 reserved_at_0[0x80]; 2228 2229 u8 reserved_at_80[0x10]; 2230 u8 rtt_resp_dscp_valid[0x1]; 2231 u8 reserved_at_91[0x9]; 2232 u8 rtt_resp_dscp[0x6]; 2233 2234 u8 reserved_at_a0[0x760]; 2235 }; 2236 2237 struct mlx5_ifc_cong_control_802_1qau_rp_bits { 2238 u8 reserved_at_0[0x80]; 2239 2240 u8 rppp_max_rps[0x20]; 2241 2242 u8 rpg_time_reset[0x20]; 2243 2244 u8 rpg_byte_reset[0x20]; 2245 2246 u8 rpg_threshold[0x20]; 2247 2248 u8 rpg_max_rate[0x20]; 2249 2250 u8 rpg_ai_rate[0x20]; 2251 2252 u8 rpg_hai_rate[0x20]; 2253 2254 u8 rpg_gd[0x20]; 2255 2256 u8 rpg_min_dec_fac[0x20]; 2257 2258 u8 rpg_min_rate[0x20]; 2259 2260 u8 reserved_at_1c0[0x640]; 2261 }; 2262 2263 enum { 2264 MLX5_RESIZE_FIELD_SELECT_RESIZE_FIELD_SELECT_LOG_CQ_SIZE = 0x1, 2265 MLX5_RESIZE_FIELD_SELECT_RESIZE_FIELD_SELECT_PAGE_OFFSET = 0x2, 2266 MLX5_RESIZE_FIELD_SELECT_RESIZE_FIELD_SELECT_LOG_PAGE_SIZE = 0x4, 2267 }; 2268 2269 struct mlx5_ifc_resize_field_select_bits { 2270 u8 resize_field_select[0x20]; 2271 }; 2272 2273 struct mlx5_ifc_resource_dump_bits { 2274 u8 more_dump[0x1]; 2275 u8 inline_dump[0x1]; 2276 u8 reserved_at_2[0xa]; 2277 u8 seq_num[0x4]; 2278 u8 segment_type[0x10]; 2279 2280 u8 reserved_at_20[0x10]; 2281 u8 vhca_id[0x10]; 2282 2283 u8 index1[0x20]; 2284 2285 u8 index2[0x20]; 2286 2287 u8 num_of_obj1[0x10]; 2288 u8 num_of_obj2[0x10]; 2289 2290 u8 reserved_at_a0[0x20]; 2291 2292 u8 device_opaque[0x40]; 2293 2294 u8 mkey[0x20]; 2295 2296 u8 size[0x20]; 2297 2298 u8 address[0x40]; 2299 2300 u8 inline_data[52][0x20]; 2301 }; 2302 2303 struct mlx5_ifc_resource_dump_menu_record_bits { 2304 u8 reserved_at_0[0x4]; 2305 u8 num_of_obj2_supports_active[0x1]; 2306 u8 num_of_obj2_supports_all[0x1]; 2307 u8 must_have_num_of_obj2[0x1]; 2308 u8 support_num_of_obj2[0x1]; 2309 u8 num_of_obj1_supports_active[0x1]; 2310 u8 num_of_obj1_supports_all[0x1]; 2311 u8 must_have_num_of_obj1[0x1]; 2312 u8 support_num_of_obj1[0x1]; 2313 u8 must_have_index2[0x1]; 2314 u8 support_index2[0x1]; 2315 u8 must_have_index1[0x1]; 2316 u8 support_index1[0x1]; 2317 u8 segment_type[0x10]; 2318 2319 u8 segment_name[4][0x20]; 2320 2321 u8 index1_name[4][0x20]; 2322 2323 u8 index2_name[4][0x20]; 2324 }; 2325 2326 struct mlx5_ifc_resource_dump_segment_header_bits { 2327 u8 length_dw[0x10]; 2328 u8 segment_type[0x10]; 2329 }; 2330 2331 struct mlx5_ifc_resource_dump_command_segment_bits { 2332 struct mlx5_ifc_resource_dump_segment_header_bits segment_header; 2333 2334 u8 segment_called[0x10]; 2335 u8 vhca_id[0x10]; 2336 2337 u8 index1[0x20]; 2338 2339 u8 index2[0x20]; 2340 2341 u8 num_of_obj1[0x10]; 2342 u8 num_of_obj2[0x10]; 2343 }; 2344 2345 struct mlx5_ifc_resource_dump_error_segment_bits { 2346 struct mlx5_ifc_resource_dump_segment_header_bits segment_header; 2347 2348 u8 reserved_at_20[0x10]; 2349 u8 syndrome_id[0x10]; 2350 2351 u8 reserved_at_40[0x40]; 2352 2353 u8 error[8][0x20]; 2354 }; 2355 2356 struct mlx5_ifc_resource_dump_info_segment_bits { 2357 struct mlx5_ifc_resource_dump_segment_header_bits segment_header; 2358 2359 u8 reserved_at_20[0x18]; 2360 u8 dump_version[0x8]; 2361 2362 u8 hw_version[0x20]; 2363 2364 u8 fw_version[0x20]; 2365 }; 2366 2367 struct mlx5_ifc_resource_dump_menu_segment_bits { 2368 struct mlx5_ifc_resource_dump_segment_header_bits segment_header; 2369 2370 u8 reserved_at_20[0x10]; 2371 u8 num_of_records[0x10]; 2372 2373 struct mlx5_ifc_resource_dump_menu_record_bits record[]; 2374 }; 2375 2376 struct mlx5_ifc_resource_dump_resource_segment_bits { 2377 struct mlx5_ifc_resource_dump_segment_header_bits segment_header; 2378 2379 u8 reserved_at_20[0x20]; 2380 2381 u8 index1[0x20]; 2382 2383 u8 index2[0x20]; 2384 2385 u8 payload[][0x20]; 2386 }; 2387 2388 struct mlx5_ifc_resource_dump_terminate_segment_bits { 2389 struct mlx5_ifc_resource_dump_segment_header_bits segment_header; 2390 }; 2391 2392 struct mlx5_ifc_menu_resource_dump_response_bits { 2393 struct mlx5_ifc_resource_dump_info_segment_bits info; 2394 struct mlx5_ifc_resource_dump_command_segment_bits cmd; 2395 struct mlx5_ifc_resource_dump_menu_segment_bits menu; 2396 struct mlx5_ifc_resource_dump_terminate_segment_bits terminate; 2397 }; 2398 2399 enum { 2400 MLX5_MODIFY_FIELD_SELECT_MODIFY_FIELD_SELECT_CQ_PERIOD = 0x1, 2401 MLX5_MODIFY_FIELD_SELECT_MODIFY_FIELD_SELECT_CQ_MAX_COUNT = 0x2, 2402 MLX5_MODIFY_FIELD_SELECT_MODIFY_FIELD_SELECT_OI = 0x4, 2403 MLX5_MODIFY_FIELD_SELECT_MODIFY_FIELD_SELECT_C_EQN = 0x8, 2404 }; 2405 2406 struct mlx5_ifc_modify_field_select_bits { 2407 u8 modify_field_select[0x20]; 2408 }; 2409 2410 struct mlx5_ifc_field_select_r_roce_np_bits { 2411 u8 field_select_r_roce_np[0x20]; 2412 }; 2413 2414 struct mlx5_ifc_field_select_r_roce_rp_bits { 2415 u8 field_select_r_roce_rp[0x20]; 2416 }; 2417 2418 enum { 2419 MLX5_FIELD_SELECT_802_1QAU_RP_FIELD_SELECT_8021QAURP_RPPP_MAX_RPS = 0x4, 2420 MLX5_FIELD_SELECT_802_1QAU_RP_FIELD_SELECT_8021QAURP_RPG_TIME_RESET = 0x8, 2421 MLX5_FIELD_SELECT_802_1QAU_RP_FIELD_SELECT_8021QAURP_RPG_BYTE_RESET = 0x10, 2422 MLX5_FIELD_SELECT_802_1QAU_RP_FIELD_SELECT_8021QAURP_RPG_THRESHOLD = 0x20, 2423 MLX5_FIELD_SELECT_802_1QAU_RP_FIELD_SELECT_8021QAURP_RPG_MAX_RATE = 0x40, 2424 MLX5_FIELD_SELECT_802_1QAU_RP_FIELD_SELECT_8021QAURP_RPG_AI_RATE = 0x80, 2425 MLX5_FIELD_SELECT_802_1QAU_RP_FIELD_SELECT_8021QAURP_RPG_HAI_RATE = 0x100, 2426 MLX5_FIELD_SELECT_802_1QAU_RP_FIELD_SELECT_8021QAURP_RPG_GD = 0x200, 2427 MLX5_FIELD_SELECT_802_1QAU_RP_FIELD_SELECT_8021QAURP_RPG_MIN_DEC_FAC = 0x400, 2428 MLX5_FIELD_SELECT_802_1QAU_RP_FIELD_SELECT_8021QAURP_RPG_MIN_RATE = 0x800, 2429 }; 2430 2431 struct mlx5_ifc_field_select_802_1qau_rp_bits { 2432 u8 field_select_8021qaurp[0x20]; 2433 }; 2434 2435 struct mlx5_ifc_phys_layer_cntrs_bits { 2436 u8 time_since_last_clear_high[0x20]; 2437 2438 u8 time_since_last_clear_low[0x20]; 2439 2440 u8 symbol_errors_high[0x20]; 2441 2442 u8 symbol_errors_low[0x20]; 2443 2444 u8 sync_headers_errors_high[0x20]; 2445 2446 u8 sync_headers_errors_low[0x20]; 2447 2448 u8 edpl_bip_errors_lane0_high[0x20]; 2449 2450 u8 edpl_bip_errors_lane0_low[0x20]; 2451 2452 u8 edpl_bip_errors_lane1_high[0x20]; 2453 2454 u8 edpl_bip_errors_lane1_low[0x20]; 2455 2456 u8 edpl_bip_errors_lane2_high[0x20]; 2457 2458 u8 edpl_bip_errors_lane2_low[0x20]; 2459 2460 u8 edpl_bip_errors_lane3_high[0x20]; 2461 2462 u8 edpl_bip_errors_lane3_low[0x20]; 2463 2464 u8 fc_fec_corrected_blocks_lane0_high[0x20]; 2465 2466 u8 fc_fec_corrected_blocks_lane0_low[0x20]; 2467 2468 u8 fc_fec_corrected_blocks_lane1_high[0x20]; 2469 2470 u8 fc_fec_corrected_blocks_lane1_low[0x20]; 2471 2472 u8 fc_fec_corrected_blocks_lane2_high[0x20]; 2473 2474 u8 fc_fec_corrected_blocks_lane2_low[0x20]; 2475 2476 u8 fc_fec_corrected_blocks_lane3_high[0x20]; 2477 2478 u8 fc_fec_corrected_blocks_lane3_low[0x20]; 2479 2480 u8 fc_fec_uncorrectable_blocks_lane0_high[0x20]; 2481 2482 u8 fc_fec_uncorrectable_blocks_lane0_low[0x20]; 2483 2484 u8 fc_fec_uncorrectable_blocks_lane1_high[0x20]; 2485 2486 u8 fc_fec_uncorrectable_blocks_lane1_low[0x20]; 2487 2488 u8 fc_fec_uncorrectable_blocks_lane2_high[0x20]; 2489 2490 u8 fc_fec_uncorrectable_blocks_lane2_low[0x20]; 2491 2492 u8 fc_fec_uncorrectable_blocks_lane3_high[0x20]; 2493 2494 u8 fc_fec_uncorrectable_blocks_lane3_low[0x20]; 2495 2496 u8 rs_fec_corrected_blocks_high[0x20]; 2497 2498 u8 rs_fec_corrected_blocks_low[0x20]; 2499 2500 u8 rs_fec_uncorrectable_blocks_high[0x20]; 2501 2502 u8 rs_fec_uncorrectable_blocks_low[0x20]; 2503 2504 u8 rs_fec_no_errors_blocks_high[0x20]; 2505 2506 u8 rs_fec_no_errors_blocks_low[0x20]; 2507 2508 u8 rs_fec_single_error_blocks_high[0x20]; 2509 2510 u8 rs_fec_single_error_blocks_low[0x20]; 2511 2512 u8 rs_fec_corrected_symbols_total_high[0x20]; 2513 2514 u8 rs_fec_corrected_symbols_total_low[0x20]; 2515 2516 u8 rs_fec_corrected_symbols_lane0_high[0x20]; 2517 2518 u8 rs_fec_corrected_symbols_lane0_low[0x20]; 2519 2520 u8 rs_fec_corrected_symbols_lane1_high[0x20]; 2521 2522 u8 rs_fec_corrected_symbols_lane1_low[0x20]; 2523 2524 u8 rs_fec_corrected_symbols_lane2_high[0x20]; 2525 2526 u8 rs_fec_corrected_symbols_lane2_low[0x20]; 2527 2528 u8 rs_fec_corrected_symbols_lane3_high[0x20]; 2529 2530 u8 rs_fec_corrected_symbols_lane3_low[0x20]; 2531 2532 u8 link_down_events[0x20]; 2533 2534 u8 successful_recovery_events[0x20]; 2535 2536 u8 reserved_at_640[0x180]; 2537 }; 2538 2539 struct mlx5_ifc_phys_layer_statistical_cntrs_bits { 2540 u8 time_since_last_clear_high[0x20]; 2541 2542 u8 time_since_last_clear_low[0x20]; 2543 2544 u8 phy_received_bits_high[0x20]; 2545 2546 u8 phy_received_bits_low[0x20]; 2547 2548 u8 phy_symbol_errors_high[0x20]; 2549 2550 u8 phy_symbol_errors_low[0x20]; 2551 2552 u8 phy_corrected_bits_high[0x20]; 2553 2554 u8 phy_corrected_bits_low[0x20]; 2555 2556 u8 phy_corrected_bits_lane0_high[0x20]; 2557 2558 u8 phy_corrected_bits_lane0_low[0x20]; 2559 2560 u8 phy_corrected_bits_lane1_high[0x20]; 2561 2562 u8 phy_corrected_bits_lane1_low[0x20]; 2563 2564 u8 phy_corrected_bits_lane2_high[0x20]; 2565 2566 u8 phy_corrected_bits_lane2_low[0x20]; 2567 2568 u8 phy_corrected_bits_lane3_high[0x20]; 2569 2570 u8 phy_corrected_bits_lane3_low[0x20]; 2571 2572 u8 reserved_at_200[0x5c0]; 2573 }; 2574 2575 struct mlx5_ifc_ib_port_cntrs_grp_data_layout_bits { 2576 u8 symbol_error_counter[0x10]; 2577 2578 u8 link_error_recovery_counter[0x8]; 2579 2580 u8 link_downed_counter[0x8]; 2581 2582 u8 port_rcv_errors[0x10]; 2583 2584 u8 port_rcv_remote_physical_errors[0x10]; 2585 2586 u8 port_rcv_switch_relay_errors[0x10]; 2587 2588 u8 port_xmit_discards[0x10]; 2589 2590 u8 port_xmit_constraint_errors[0x8]; 2591 2592 u8 port_rcv_constraint_errors[0x8]; 2593 2594 u8 reserved_at_70[0x8]; 2595 2596 u8 link_overrun_errors[0x8]; 2597 2598 u8 reserved_at_80[0x10]; 2599 2600 u8 vl_15_dropped[0x10]; 2601 2602 u8 reserved_at_a0[0x80]; 2603 2604 u8 port_xmit_wait[0x20]; 2605 }; 2606 2607 struct mlx5_ifc_eth_per_tc_prio_grp_data_layout_bits { 2608 u8 transmit_queue_high[0x20]; 2609 2610 u8 transmit_queue_low[0x20]; 2611 2612 u8 no_buffer_discard_uc_high[0x20]; 2613 2614 u8 no_buffer_discard_uc_low[0x20]; 2615 2616 u8 reserved_at_80[0x740]; 2617 }; 2618 2619 struct mlx5_ifc_eth_per_tc_congest_prio_grp_data_layout_bits { 2620 u8 wred_discard_high[0x20]; 2621 2622 u8 wred_discard_low[0x20]; 2623 2624 u8 ecn_marked_tc_high[0x20]; 2625 2626 u8 ecn_marked_tc_low[0x20]; 2627 2628 u8 reserved_at_80[0x740]; 2629 }; 2630 2631 struct mlx5_ifc_eth_per_prio_grp_data_layout_bits { 2632 u8 rx_octets_high[0x20]; 2633 2634 u8 rx_octets_low[0x20]; 2635 2636 u8 reserved_at_40[0xc0]; 2637 2638 u8 rx_frames_high[0x20]; 2639 2640 u8 rx_frames_low[0x20]; 2641 2642 u8 tx_octets_high[0x20]; 2643 2644 u8 tx_octets_low[0x20]; 2645 2646 u8 reserved_at_180[0xc0]; 2647 2648 u8 tx_frames_high[0x20]; 2649 2650 u8 tx_frames_low[0x20]; 2651 2652 u8 rx_pause_high[0x20]; 2653 2654 u8 rx_pause_low[0x20]; 2655 2656 u8 rx_pause_duration_high[0x20]; 2657 2658 u8 rx_pause_duration_low[0x20]; 2659 2660 u8 tx_pause_high[0x20]; 2661 2662 u8 tx_pause_low[0x20]; 2663 2664 u8 tx_pause_duration_high[0x20]; 2665 2666 u8 tx_pause_duration_low[0x20]; 2667 2668 u8 rx_pause_transition_high[0x20]; 2669 2670 u8 rx_pause_transition_low[0x20]; 2671 2672 u8 rx_discards_high[0x20]; 2673 2674 u8 rx_discards_low[0x20]; 2675 2676 u8 device_stall_minor_watermark_cnt_high[0x20]; 2677 2678 u8 device_stall_minor_watermark_cnt_low[0x20]; 2679 2680 u8 device_stall_critical_watermark_cnt_high[0x20]; 2681 2682 u8 device_stall_critical_watermark_cnt_low[0x20]; 2683 2684 u8 reserved_at_480[0x340]; 2685 }; 2686 2687 struct mlx5_ifc_eth_extended_cntrs_grp_data_layout_bits { 2688 u8 port_transmit_wait_high[0x20]; 2689 2690 u8 port_transmit_wait_low[0x20]; 2691 2692 u8 reserved_at_40[0x100]; 2693 2694 u8 rx_buffer_almost_full_high[0x20]; 2695 2696 u8 rx_buffer_almost_full_low[0x20]; 2697 2698 u8 rx_buffer_full_high[0x20]; 2699 2700 u8 rx_buffer_full_low[0x20]; 2701 2702 u8 rx_icrc_encapsulated_high[0x20]; 2703 2704 u8 rx_icrc_encapsulated_low[0x20]; 2705 2706 u8 reserved_at_200[0x5c0]; 2707 }; 2708 2709 struct mlx5_ifc_eth_3635_cntrs_grp_data_layout_bits { 2710 u8 dot3stats_alignment_errors_high[0x20]; 2711 2712 u8 dot3stats_alignment_errors_low[0x20]; 2713 2714 u8 dot3stats_fcs_errors_high[0x20]; 2715 2716 u8 dot3stats_fcs_errors_low[0x20]; 2717 2718 u8 dot3stats_single_collision_frames_high[0x20]; 2719 2720 u8 dot3stats_single_collision_frames_low[0x20]; 2721 2722 u8 dot3stats_multiple_collision_frames_high[0x20]; 2723 2724 u8 dot3stats_multiple_collision_frames_low[0x20]; 2725 2726 u8 dot3stats_sqe_test_errors_high[0x20]; 2727 2728 u8 dot3stats_sqe_test_errors_low[0x20]; 2729 2730 u8 dot3stats_deferred_transmissions_high[0x20]; 2731 2732 u8 dot3stats_deferred_transmissions_low[0x20]; 2733 2734 u8 dot3stats_late_collisions_high[0x20]; 2735 2736 u8 dot3stats_late_collisions_low[0x20]; 2737 2738 u8 dot3stats_excessive_collisions_high[0x20]; 2739 2740 u8 dot3stats_excessive_collisions_low[0x20]; 2741 2742 u8 dot3stats_internal_mac_transmit_errors_high[0x20]; 2743 2744 u8 dot3stats_internal_mac_transmit_errors_low[0x20]; 2745 2746 u8 dot3stats_carrier_sense_errors_high[0x20]; 2747 2748 u8 dot3stats_carrier_sense_errors_low[0x20]; 2749 2750 u8 dot3stats_frame_too_longs_high[0x20]; 2751 2752 u8 dot3stats_frame_too_longs_low[0x20]; 2753 2754 u8 dot3stats_internal_mac_receive_errors_high[0x20]; 2755 2756 u8 dot3stats_internal_mac_receive_errors_low[0x20]; 2757 2758 u8 dot3stats_symbol_errors_high[0x20]; 2759 2760 u8 dot3stats_symbol_errors_low[0x20]; 2761 2762 u8 dot3control_in_unknown_opcodes_high[0x20]; 2763 2764 u8 dot3control_in_unknown_opcodes_low[0x20]; 2765 2766 u8 dot3in_pause_frames_high[0x20]; 2767 2768 u8 dot3in_pause_frames_low[0x20]; 2769 2770 u8 dot3out_pause_frames_high[0x20]; 2771 2772 u8 dot3out_pause_frames_low[0x20]; 2773 2774 u8 reserved_at_400[0x3c0]; 2775 }; 2776 2777 struct mlx5_ifc_eth_2819_cntrs_grp_data_layout_bits { 2778 u8 ether_stats_drop_events_high[0x20]; 2779 2780 u8 ether_stats_drop_events_low[0x20]; 2781 2782 u8 ether_stats_octets_high[0x20]; 2783 2784 u8 ether_stats_octets_low[0x20]; 2785 2786 u8 ether_stats_pkts_high[0x20]; 2787 2788 u8 ether_stats_pkts_low[0x20]; 2789 2790 u8 ether_stats_broadcast_pkts_high[0x20]; 2791 2792 u8 ether_stats_broadcast_pkts_low[0x20]; 2793 2794 u8 ether_stats_multicast_pkts_high[0x20]; 2795 2796 u8 ether_stats_multicast_pkts_low[0x20]; 2797 2798 u8 ether_stats_crc_align_errors_high[0x20]; 2799 2800 u8 ether_stats_crc_align_errors_low[0x20]; 2801 2802 u8 ether_stats_undersize_pkts_high[0x20]; 2803 2804 u8 ether_stats_undersize_pkts_low[0x20]; 2805 2806 u8 ether_stats_oversize_pkts_high[0x20]; 2807 2808 u8 ether_stats_oversize_pkts_low[0x20]; 2809 2810 u8 ether_stats_fragments_high[0x20]; 2811 2812 u8 ether_stats_fragments_low[0x20]; 2813 2814 u8 ether_stats_jabbers_high[0x20]; 2815 2816 u8 ether_stats_jabbers_low[0x20]; 2817 2818 u8 ether_stats_collisions_high[0x20]; 2819 2820 u8 ether_stats_collisions_low[0x20]; 2821 2822 u8 ether_stats_pkts64octets_high[0x20]; 2823 2824 u8 ether_stats_pkts64octets_low[0x20]; 2825 2826 u8 ether_stats_pkts65to127octets_high[0x20]; 2827 2828 u8 ether_stats_pkts65to127octets_low[0x20]; 2829 2830 u8 ether_stats_pkts128to255octets_high[0x20]; 2831 2832 u8 ether_stats_pkts128to255octets_low[0x20]; 2833 2834 u8 ether_stats_pkts256to511octets_high[0x20]; 2835 2836 u8 ether_stats_pkts256to511octets_low[0x20]; 2837 2838 u8 ether_stats_pkts512to1023octets_high[0x20]; 2839 2840 u8 ether_stats_pkts512to1023octets_low[0x20]; 2841 2842 u8 ether_stats_pkts1024to1518octets_high[0x20]; 2843 2844 u8 ether_stats_pkts1024to1518octets_low[0x20]; 2845 2846 u8 ether_stats_pkts1519to2047octets_high[0x20]; 2847 2848 u8 ether_stats_pkts1519to2047octets_low[0x20]; 2849 2850 u8 ether_stats_pkts2048to4095octets_high[0x20]; 2851 2852 u8 ether_stats_pkts2048to4095octets_low[0x20]; 2853 2854 u8 ether_stats_pkts4096to8191octets_high[0x20]; 2855 2856 u8 ether_stats_pkts4096to8191octets_low[0x20]; 2857 2858 u8 ether_stats_pkts8192to10239octets_high[0x20]; 2859 2860 u8 ether_stats_pkts8192to10239octets_low[0x20]; 2861 2862 u8 reserved_at_540[0x280]; 2863 }; 2864 2865 struct mlx5_ifc_eth_2863_cntrs_grp_data_layout_bits { 2866 u8 if_in_octets_high[0x20]; 2867 2868 u8 if_in_octets_low[0x20]; 2869 2870 u8 if_in_ucast_pkts_high[0x20]; 2871 2872 u8 if_in_ucast_pkts_low[0x20]; 2873 2874 u8 if_in_discards_high[0x20]; 2875 2876 u8 if_in_discards_low[0x20]; 2877 2878 u8 if_in_errors_high[0x20]; 2879 2880 u8 if_in_errors_low[0x20]; 2881 2882 u8 if_in_unknown_protos_high[0x20]; 2883 2884 u8 if_in_unknown_protos_low[0x20]; 2885 2886 u8 if_out_octets_high[0x20]; 2887 2888 u8 if_out_octets_low[0x20]; 2889 2890 u8 if_out_ucast_pkts_high[0x20]; 2891 2892 u8 if_out_ucast_pkts_low[0x20]; 2893 2894 u8 if_out_discards_high[0x20]; 2895 2896 u8 if_out_discards_low[0x20]; 2897 2898 u8 if_out_errors_high[0x20]; 2899 2900 u8 if_out_errors_low[0x20]; 2901 2902 u8 if_in_multicast_pkts_high[0x20]; 2903 2904 u8 if_in_multicast_pkts_low[0x20]; 2905 2906 u8 if_in_broadcast_pkts_high[0x20]; 2907 2908 u8 if_in_broadcast_pkts_low[0x20]; 2909 2910 u8 if_out_multicast_pkts_high[0x20]; 2911 2912 u8 if_out_multicast_pkts_low[0x20]; 2913 2914 u8 if_out_broadcast_pkts_high[0x20]; 2915 2916 u8 if_out_broadcast_pkts_low[0x20]; 2917 2918 u8 reserved_at_340[0x480]; 2919 }; 2920 2921 struct mlx5_ifc_eth_802_3_cntrs_grp_data_layout_bits { 2922 u8 a_frames_transmitted_ok_high[0x20]; 2923 2924 u8 a_frames_transmitted_ok_low[0x20]; 2925 2926 u8 a_frames_received_ok_high[0x20]; 2927 2928 u8 a_frames_received_ok_low[0x20]; 2929 2930 u8 a_frame_check_sequence_errors_high[0x20]; 2931 2932 u8 a_frame_check_sequence_errors_low[0x20]; 2933 2934 u8 a_alignment_errors_high[0x20]; 2935 2936 u8 a_alignment_errors_low[0x20]; 2937 2938 u8 a_octets_transmitted_ok_high[0x20]; 2939 2940 u8 a_octets_transmitted_ok_low[0x20]; 2941 2942 u8 a_octets_received_ok_high[0x20]; 2943 2944 u8 a_octets_received_ok_low[0x20]; 2945 2946 u8 a_multicast_frames_xmitted_ok_high[0x20]; 2947 2948 u8 a_multicast_frames_xmitted_ok_low[0x20]; 2949 2950 u8 a_broadcast_frames_xmitted_ok_high[0x20]; 2951 2952 u8 a_broadcast_frames_xmitted_ok_low[0x20]; 2953 2954 u8 a_multicast_frames_received_ok_high[0x20]; 2955 2956 u8 a_multicast_frames_received_ok_low[0x20]; 2957 2958 u8 a_broadcast_frames_received_ok_high[0x20]; 2959 2960 u8 a_broadcast_frames_received_ok_low[0x20]; 2961 2962 u8 a_in_range_length_errors_high[0x20]; 2963 2964 u8 a_in_range_length_errors_low[0x20]; 2965 2966 u8 a_out_of_range_length_field_high[0x20]; 2967 2968 u8 a_out_of_range_length_field_low[0x20]; 2969 2970 u8 a_frame_too_long_errors_high[0x20]; 2971 2972 u8 a_frame_too_long_errors_low[0x20]; 2973 2974 u8 a_symbol_error_during_carrier_high[0x20]; 2975 2976 u8 a_symbol_error_during_carrier_low[0x20]; 2977 2978 u8 a_mac_control_frames_transmitted_high[0x20]; 2979 2980 u8 a_mac_control_frames_transmitted_low[0x20]; 2981 2982 u8 a_mac_control_frames_received_high[0x20]; 2983 2984 u8 a_mac_control_frames_received_low[0x20]; 2985 2986 u8 a_unsupported_opcodes_received_high[0x20]; 2987 2988 u8 a_unsupported_opcodes_received_low[0x20]; 2989 2990 u8 a_pause_mac_ctrl_frames_received_high[0x20]; 2991 2992 u8 a_pause_mac_ctrl_frames_received_low[0x20]; 2993 2994 u8 a_pause_mac_ctrl_frames_transmitted_high[0x20]; 2995 2996 u8 a_pause_mac_ctrl_frames_transmitted_low[0x20]; 2997 2998 u8 reserved_at_4c0[0x300]; 2999 }; 3000 3001 struct mlx5_ifc_pcie_perf_cntrs_grp_data_layout_bits { 3002 u8 life_time_counter_high[0x20]; 3003 3004 u8 life_time_counter_low[0x20]; 3005 3006 u8 rx_errors[0x20]; 3007 3008 u8 tx_errors[0x20]; 3009 3010 u8 l0_to_recovery_eieos[0x20]; 3011 3012 u8 l0_to_recovery_ts[0x20]; 3013 3014 u8 l0_to_recovery_framing[0x20]; 3015 3016 u8 l0_to_recovery_retrain[0x20]; 3017 3018 u8 crc_error_dllp[0x20]; 3019 3020 u8 crc_error_tlp[0x20]; 3021 3022 u8 tx_overflow_buffer_pkt_high[0x20]; 3023 3024 u8 tx_overflow_buffer_pkt_low[0x20]; 3025 3026 u8 outbound_stalled_reads[0x20]; 3027 3028 u8 outbound_stalled_writes[0x20]; 3029 3030 u8 outbound_stalled_reads_events[0x20]; 3031 3032 u8 outbound_stalled_writes_events[0x20]; 3033 3034 u8 reserved_at_200[0x5c0]; 3035 }; 3036 3037 struct mlx5_ifc_cmd_inter_comp_event_bits { 3038 u8 command_completion_vector[0x20]; 3039 3040 u8 reserved_at_20[0xc0]; 3041 }; 3042 3043 struct mlx5_ifc_stall_vl_event_bits { 3044 u8 reserved_at_0[0x18]; 3045 u8 port_num[0x1]; 3046 u8 reserved_at_19[0x3]; 3047 u8 vl[0x4]; 3048 3049 u8 reserved_at_20[0xa0]; 3050 }; 3051 3052 struct mlx5_ifc_db_bf_congestion_event_bits { 3053 u8 event_subtype[0x8]; 3054 u8 reserved_at_8[0x8]; 3055 u8 congestion_level[0x8]; 3056 u8 reserved_at_18[0x8]; 3057 3058 u8 reserved_at_20[0xa0]; 3059 }; 3060 3061 struct mlx5_ifc_gpio_event_bits { 3062 u8 reserved_at_0[0x60]; 3063 3064 u8 gpio_event_hi[0x20]; 3065 3066 u8 gpio_event_lo[0x20]; 3067 3068 u8 reserved_at_a0[0x40]; 3069 }; 3070 3071 struct mlx5_ifc_port_state_change_event_bits { 3072 u8 reserved_at_0[0x40]; 3073 3074 u8 port_num[0x4]; 3075 u8 reserved_at_44[0x1c]; 3076 3077 u8 reserved_at_60[0x80]; 3078 }; 3079 3080 struct mlx5_ifc_dropped_packet_logged_bits { 3081 u8 reserved_at_0[0xe0]; 3082 }; 3083 3084 struct mlx5_ifc_default_timeout_bits { 3085 u8 to_multiplier[0x3]; 3086 u8 reserved_at_3[0x9]; 3087 u8 to_value[0x14]; 3088 }; 3089 3090 struct mlx5_ifc_dtor_reg_bits { 3091 u8 reserved_at_0[0x20]; 3092 3093 struct mlx5_ifc_default_timeout_bits pcie_toggle_to; 3094 3095 u8 reserved_at_40[0x60]; 3096 3097 struct mlx5_ifc_default_timeout_bits health_poll_to; 3098 3099 struct mlx5_ifc_default_timeout_bits full_crdump_to; 3100 3101 struct mlx5_ifc_default_timeout_bits fw_reset_to; 3102 3103 struct mlx5_ifc_default_timeout_bits flush_on_err_to; 3104 3105 struct mlx5_ifc_default_timeout_bits pci_sync_update_to; 3106 3107 struct mlx5_ifc_default_timeout_bits tear_down_to; 3108 3109 struct mlx5_ifc_default_timeout_bits fsm_reactivate_to; 3110 3111 struct mlx5_ifc_default_timeout_bits reclaim_pages_to; 3112 3113 struct mlx5_ifc_default_timeout_bits reclaim_vfs_pages_to; 3114 3115 u8 reserved_at_1c0[0x40]; 3116 }; 3117 3118 enum { 3119 MLX5_CQ_ERROR_SYNDROME_CQ_OVERRUN = 0x1, 3120 MLX5_CQ_ERROR_SYNDROME_CQ_ACCESS_VIOLATION_ERROR = 0x2, 3121 }; 3122 3123 struct mlx5_ifc_cq_error_bits { 3124 u8 reserved_at_0[0x8]; 3125 u8 cqn[0x18]; 3126 3127 u8 reserved_at_20[0x20]; 3128 3129 u8 reserved_at_40[0x18]; 3130 u8 syndrome[0x8]; 3131 3132 u8 reserved_at_60[0x80]; 3133 }; 3134 3135 struct mlx5_ifc_rdma_page_fault_event_bits { 3136 u8 bytes_committed[0x20]; 3137 3138 u8 r_key[0x20]; 3139 3140 u8 reserved_at_40[0x10]; 3141 u8 packet_len[0x10]; 3142 3143 u8 rdma_op_len[0x20]; 3144 3145 u8 rdma_va[0x40]; 3146 3147 u8 reserved_at_c0[0x5]; 3148 u8 rdma[0x1]; 3149 u8 write[0x1]; 3150 u8 requestor[0x1]; 3151 u8 qp_number[0x18]; 3152 }; 3153 3154 struct mlx5_ifc_wqe_associated_page_fault_event_bits { 3155 u8 bytes_committed[0x20]; 3156 3157 u8 reserved_at_20[0x10]; 3158 u8 wqe_index[0x10]; 3159 3160 u8 reserved_at_40[0x10]; 3161 u8 len[0x10]; 3162 3163 u8 reserved_at_60[0x60]; 3164 3165 u8 reserved_at_c0[0x5]; 3166 u8 rdma[0x1]; 3167 u8 write_read[0x1]; 3168 u8 requestor[0x1]; 3169 u8 qpn[0x18]; 3170 }; 3171 3172 struct mlx5_ifc_qp_events_bits { 3173 u8 reserved_at_0[0xa0]; 3174 3175 u8 type[0x8]; 3176 u8 reserved_at_a8[0x18]; 3177 3178 u8 reserved_at_c0[0x8]; 3179 u8 qpn_rqn_sqn[0x18]; 3180 }; 3181 3182 struct mlx5_ifc_dct_events_bits { 3183 u8 reserved_at_0[0xc0]; 3184 3185 u8 reserved_at_c0[0x8]; 3186 u8 dct_number[0x18]; 3187 }; 3188 3189 struct mlx5_ifc_comp_event_bits { 3190 u8 reserved_at_0[0xc0]; 3191 3192 u8 reserved_at_c0[0x8]; 3193 u8 cq_number[0x18]; 3194 }; 3195 3196 enum { 3197 MLX5_QPC_STATE_RST = 0x0, 3198 MLX5_QPC_STATE_INIT = 0x1, 3199 MLX5_QPC_STATE_RTR = 0x2, 3200 MLX5_QPC_STATE_RTS = 0x3, 3201 MLX5_QPC_STATE_SQER = 0x4, 3202 MLX5_QPC_STATE_ERR = 0x6, 3203 MLX5_QPC_STATE_SQD = 0x7, 3204 MLX5_QPC_STATE_SUSPENDED = 0x9, 3205 }; 3206 3207 enum { 3208 MLX5_QPC_ST_RC = 0x0, 3209 MLX5_QPC_ST_UC = 0x1, 3210 MLX5_QPC_ST_UD = 0x2, 3211 MLX5_QPC_ST_XRC = 0x3, 3212 MLX5_QPC_ST_DCI = 0x5, 3213 MLX5_QPC_ST_QP0 = 0x7, 3214 MLX5_QPC_ST_QP1 = 0x8, 3215 MLX5_QPC_ST_RAW_DATAGRAM = 0x9, 3216 MLX5_QPC_ST_REG_UMR = 0xc, 3217 }; 3218 3219 enum { 3220 MLX5_QPC_PM_STATE_ARMED = 0x0, 3221 MLX5_QPC_PM_STATE_REARM = 0x1, 3222 MLX5_QPC_PM_STATE_RESERVED = 0x2, 3223 MLX5_QPC_PM_STATE_MIGRATED = 0x3, 3224 }; 3225 3226 enum { 3227 MLX5_QPC_OFFLOAD_TYPE_RNDV = 0x1, 3228 }; 3229 3230 enum { 3231 MLX5_QPC_END_PADDING_MODE_SCATTER_AS_IS = 0x0, 3232 MLX5_QPC_END_PADDING_MODE_PAD_TO_CACHE_LINE_ALIGNMENT = 0x1, 3233 }; 3234 3235 enum { 3236 MLX5_QPC_MTU_256_BYTES = 0x1, 3237 MLX5_QPC_MTU_512_BYTES = 0x2, 3238 MLX5_QPC_MTU_1K_BYTES = 0x3, 3239 MLX5_QPC_MTU_2K_BYTES = 0x4, 3240 MLX5_QPC_MTU_4K_BYTES = 0x5, 3241 MLX5_QPC_MTU_RAW_ETHERNET_QP = 0x7, 3242 }; 3243 3244 enum { 3245 MLX5_QPC_ATOMIC_MODE_IB_SPEC = 0x1, 3246 MLX5_QPC_ATOMIC_MODE_ONLY_8B = 0x2, 3247 MLX5_QPC_ATOMIC_MODE_UP_TO_8B = 0x3, 3248 MLX5_QPC_ATOMIC_MODE_UP_TO_16B = 0x4, 3249 MLX5_QPC_ATOMIC_MODE_UP_TO_32B = 0x5, 3250 MLX5_QPC_ATOMIC_MODE_UP_TO_64B = 0x6, 3251 MLX5_QPC_ATOMIC_MODE_UP_TO_128B = 0x7, 3252 MLX5_QPC_ATOMIC_MODE_UP_TO_256B = 0x8, 3253 }; 3254 3255 enum { 3256 MLX5_QPC_CS_REQ_DISABLE = 0x0, 3257 MLX5_QPC_CS_REQ_UP_TO_32B = 0x11, 3258 MLX5_QPC_CS_REQ_UP_TO_64B = 0x22, 3259 }; 3260 3261 enum { 3262 MLX5_QPC_CS_RES_DISABLE = 0x0, 3263 MLX5_QPC_CS_RES_UP_TO_32B = 0x1, 3264 MLX5_QPC_CS_RES_UP_TO_64B = 0x2, 3265 }; 3266 3267 enum { 3268 MLX5_TIMESTAMP_FORMAT_FREE_RUNNING = 0x0, 3269 MLX5_TIMESTAMP_FORMAT_DEFAULT = 0x1, 3270 MLX5_TIMESTAMP_FORMAT_REAL_TIME = 0x2, 3271 }; 3272 3273 struct mlx5_ifc_qpc_bits { 3274 u8 state[0x4]; 3275 u8 lag_tx_port_affinity[0x4]; 3276 u8 st[0x8]; 3277 u8 reserved_at_10[0x2]; 3278 u8 isolate_vl_tc[0x1]; 3279 u8 pm_state[0x2]; 3280 u8 reserved_at_15[0x1]; 3281 u8 req_e2e_credit_mode[0x2]; 3282 u8 offload_type[0x4]; 3283 u8 end_padding_mode[0x2]; 3284 u8 reserved_at_1e[0x2]; 3285 3286 u8 wq_signature[0x1]; 3287 u8 block_lb_mc[0x1]; 3288 u8 atomic_like_write_en[0x1]; 3289 u8 latency_sensitive[0x1]; 3290 u8 reserved_at_24[0x1]; 3291 u8 drain_sigerr[0x1]; 3292 u8 reserved_at_26[0x2]; 3293 u8 pd[0x18]; 3294 3295 u8 mtu[0x3]; 3296 u8 log_msg_max[0x5]; 3297 u8 reserved_at_48[0x1]; 3298 u8 log_rq_size[0x4]; 3299 u8 log_rq_stride[0x3]; 3300 u8 no_sq[0x1]; 3301 u8 log_sq_size[0x4]; 3302 u8 reserved_at_55[0x1]; 3303 u8 retry_mode[0x2]; 3304 u8 ts_format[0x2]; 3305 u8 reserved_at_5a[0x1]; 3306 u8 rlky[0x1]; 3307 u8 ulp_stateless_offload_mode[0x4]; 3308 3309 u8 counter_set_id[0x8]; 3310 u8 uar_page[0x18]; 3311 3312 u8 reserved_at_80[0x8]; 3313 u8 user_index[0x18]; 3314 3315 u8 reserved_at_a0[0x3]; 3316 u8 log_page_size[0x5]; 3317 u8 remote_qpn[0x18]; 3318 3319 struct mlx5_ifc_ads_bits primary_address_path; 3320 3321 struct mlx5_ifc_ads_bits secondary_address_path; 3322 3323 u8 log_ack_req_freq[0x4]; 3324 u8 reserved_at_384[0x4]; 3325 u8 log_sra_max[0x3]; 3326 u8 reserved_at_38b[0x2]; 3327 u8 retry_count[0x3]; 3328 u8 rnr_retry[0x3]; 3329 u8 reserved_at_393[0x1]; 3330 u8 fre[0x1]; 3331 u8 cur_rnr_retry[0x3]; 3332 u8 cur_retry_count[0x3]; 3333 u8 reserved_at_39b[0x5]; 3334 3335 u8 reserved_at_3a0[0x20]; 3336 3337 u8 reserved_at_3c0[0x8]; 3338 u8 next_send_psn[0x18]; 3339 3340 u8 reserved_at_3e0[0x3]; 3341 u8 log_num_dci_stream_channels[0x5]; 3342 u8 cqn_snd[0x18]; 3343 3344 u8 reserved_at_400[0x3]; 3345 u8 log_num_dci_errored_streams[0x5]; 3346 u8 deth_sqpn[0x18]; 3347 3348 u8 reserved_at_420[0x20]; 3349 3350 u8 reserved_at_440[0x8]; 3351 u8 last_acked_psn[0x18]; 3352 3353 u8 reserved_at_460[0x8]; 3354 u8 ssn[0x18]; 3355 3356 u8 reserved_at_480[0x8]; 3357 u8 log_rra_max[0x3]; 3358 u8 reserved_at_48b[0x1]; 3359 u8 atomic_mode[0x4]; 3360 u8 rre[0x1]; 3361 u8 rwe[0x1]; 3362 u8 rae[0x1]; 3363 u8 reserved_at_493[0x1]; 3364 u8 page_offset[0x6]; 3365 u8 reserved_at_49a[0x3]; 3366 u8 cd_slave_receive[0x1]; 3367 u8 cd_slave_send[0x1]; 3368 u8 cd_master[0x1]; 3369 3370 u8 reserved_at_4a0[0x3]; 3371 u8 min_rnr_nak[0x5]; 3372 u8 next_rcv_psn[0x18]; 3373 3374 u8 reserved_at_4c0[0x8]; 3375 u8 xrcd[0x18]; 3376 3377 u8 reserved_at_4e0[0x8]; 3378 u8 cqn_rcv[0x18]; 3379 3380 u8 dbr_addr[0x40]; 3381 3382 u8 q_key[0x20]; 3383 3384 u8 reserved_at_560[0x5]; 3385 u8 rq_type[0x3]; 3386 u8 srqn_rmpn_xrqn[0x18]; 3387 3388 u8 reserved_at_580[0x8]; 3389 u8 rmsn[0x18]; 3390 3391 u8 hw_sq_wqebb_counter[0x10]; 3392 u8 sw_sq_wqebb_counter[0x10]; 3393 3394 u8 hw_rq_counter[0x20]; 3395 3396 u8 sw_rq_counter[0x20]; 3397 3398 u8 reserved_at_600[0x20]; 3399 3400 u8 reserved_at_620[0xf]; 3401 u8 cgs[0x1]; 3402 u8 cs_req[0x8]; 3403 u8 cs_res[0x8]; 3404 3405 u8 dc_access_key[0x40]; 3406 3407 u8 reserved_at_680[0x3]; 3408 u8 dbr_umem_valid[0x1]; 3409 3410 u8 reserved_at_684[0xbc]; 3411 }; 3412 3413 struct mlx5_ifc_roce_addr_layout_bits { 3414 u8 source_l3_address[16][0x8]; 3415 3416 u8 reserved_at_80[0x3]; 3417 u8 vlan_valid[0x1]; 3418 u8 vlan_id[0xc]; 3419 u8 source_mac_47_32[0x10]; 3420 3421 u8 source_mac_31_0[0x20]; 3422 3423 u8 reserved_at_c0[0x14]; 3424 u8 roce_l3_type[0x4]; 3425 u8 roce_version[0x8]; 3426 3427 u8 reserved_at_e0[0x20]; 3428 }; 3429 3430 struct mlx5_ifc_shampo_cap_bits { 3431 u8 reserved_at_0[0x3]; 3432 u8 shampo_log_max_reservation_size[0x5]; 3433 u8 reserved_at_8[0x3]; 3434 u8 shampo_log_min_reservation_size[0x5]; 3435 u8 shampo_min_mss_size[0x10]; 3436 3437 u8 reserved_at_20[0x3]; 3438 u8 shampo_max_log_headers_entry_size[0x5]; 3439 u8 reserved_at_28[0x18]; 3440 3441 u8 reserved_at_40[0x7c0]; 3442 }; 3443 3444 struct mlx5_ifc_crypto_cap_bits { 3445 u8 reserved_at_0[0x3]; 3446 u8 synchronize_dek[0x1]; 3447 u8 int_kek_manual[0x1]; 3448 u8 int_kek_auto[0x1]; 3449 u8 reserved_at_6[0x1a]; 3450 3451 u8 reserved_at_20[0x3]; 3452 u8 log_dek_max_alloc[0x5]; 3453 u8 reserved_at_28[0x3]; 3454 u8 log_max_num_deks[0x5]; 3455 u8 reserved_at_30[0x10]; 3456 3457 u8 reserved_at_40[0x20]; 3458 3459 u8 reserved_at_60[0x3]; 3460 u8 log_dek_granularity[0x5]; 3461 u8 reserved_at_68[0x3]; 3462 u8 log_max_num_int_kek[0x5]; 3463 u8 sw_wrapped_dek[0x10]; 3464 3465 u8 reserved_at_80[0x780]; 3466 }; 3467 3468 union mlx5_ifc_hca_cap_union_bits { 3469 struct mlx5_ifc_cmd_hca_cap_bits cmd_hca_cap; 3470 struct mlx5_ifc_cmd_hca_cap_2_bits cmd_hca_cap_2; 3471 struct mlx5_ifc_odp_cap_bits odp_cap; 3472 struct mlx5_ifc_atomic_caps_bits atomic_caps; 3473 struct mlx5_ifc_roce_cap_bits roce_cap; 3474 struct mlx5_ifc_per_protocol_networking_offload_caps_bits per_protocol_networking_offload_caps; 3475 struct mlx5_ifc_flow_table_nic_cap_bits flow_table_nic_cap; 3476 struct mlx5_ifc_flow_table_eswitch_cap_bits flow_table_eswitch_cap; 3477 struct mlx5_ifc_e_switch_cap_bits e_switch_cap; 3478 struct mlx5_ifc_port_selection_cap_bits port_selection_cap; 3479 struct mlx5_ifc_vector_calc_cap_bits vector_calc_cap; 3480 struct mlx5_ifc_qos_cap_bits qos_cap; 3481 struct mlx5_ifc_debug_cap_bits debug_cap; 3482 struct mlx5_ifc_fpga_cap_bits fpga_cap; 3483 struct mlx5_ifc_tls_cap_bits tls_cap; 3484 struct mlx5_ifc_device_mem_cap_bits device_mem_cap; 3485 struct mlx5_ifc_virtio_emulation_cap_bits virtio_emulation_cap; 3486 struct mlx5_ifc_shampo_cap_bits shampo_cap; 3487 struct mlx5_ifc_macsec_cap_bits macsec_cap; 3488 struct mlx5_ifc_crypto_cap_bits crypto_cap; 3489 u8 reserved_at_0[0x8000]; 3490 }; 3491 3492 enum { 3493 MLX5_FLOW_CONTEXT_ACTION_ALLOW = 0x1, 3494 MLX5_FLOW_CONTEXT_ACTION_DROP = 0x2, 3495 MLX5_FLOW_CONTEXT_ACTION_FWD_DEST = 0x4, 3496 MLX5_FLOW_CONTEXT_ACTION_COUNT = 0x8, 3497 MLX5_FLOW_CONTEXT_ACTION_PACKET_REFORMAT = 0x10, 3498 MLX5_FLOW_CONTEXT_ACTION_DECAP = 0x20, 3499 MLX5_FLOW_CONTEXT_ACTION_MOD_HDR = 0x40, 3500 MLX5_FLOW_CONTEXT_ACTION_VLAN_POP = 0x80, 3501 MLX5_FLOW_CONTEXT_ACTION_VLAN_PUSH = 0x100, 3502 MLX5_FLOW_CONTEXT_ACTION_VLAN_POP_2 = 0x400, 3503 MLX5_FLOW_CONTEXT_ACTION_VLAN_PUSH_2 = 0x800, 3504 MLX5_FLOW_CONTEXT_ACTION_CRYPTO_DECRYPT = 0x1000, 3505 MLX5_FLOW_CONTEXT_ACTION_CRYPTO_ENCRYPT = 0x2000, 3506 MLX5_FLOW_CONTEXT_ACTION_EXECUTE_ASO = 0x4000, 3507 }; 3508 3509 enum { 3510 MLX5_FLOW_CONTEXT_FLOW_SOURCE_ANY_VPORT = 0x0, 3511 MLX5_FLOW_CONTEXT_FLOW_SOURCE_UPLINK = 0x1, 3512 MLX5_FLOW_CONTEXT_FLOW_SOURCE_LOCAL_VPORT = 0x2, 3513 }; 3514 3515 enum { 3516 MLX5_FLOW_CONTEXT_ENCRYPT_DECRYPT_TYPE_IPSEC = 0x0, 3517 MLX5_FLOW_CONTEXT_ENCRYPT_DECRYPT_TYPE_MACSEC = 0x1, 3518 }; 3519 3520 struct mlx5_ifc_vlan_bits { 3521 u8 ethtype[0x10]; 3522 u8 prio[0x3]; 3523 u8 cfi[0x1]; 3524 u8 vid[0xc]; 3525 }; 3526 3527 enum { 3528 MLX5_FLOW_METER_COLOR_RED = 0x0, 3529 MLX5_FLOW_METER_COLOR_YELLOW = 0x1, 3530 MLX5_FLOW_METER_COLOR_GREEN = 0x2, 3531 MLX5_FLOW_METER_COLOR_UNDEFINED = 0x3, 3532 }; 3533 3534 enum { 3535 MLX5_EXE_ASO_FLOW_METER = 0x2, 3536 }; 3537 3538 struct mlx5_ifc_exe_aso_ctrl_flow_meter_bits { 3539 u8 return_reg_id[0x4]; 3540 u8 aso_type[0x4]; 3541 u8 reserved_at_8[0x14]; 3542 u8 action[0x1]; 3543 u8 init_color[0x2]; 3544 u8 meter_id[0x1]; 3545 }; 3546 3547 union mlx5_ifc_exe_aso_ctrl { 3548 struct mlx5_ifc_exe_aso_ctrl_flow_meter_bits exe_aso_ctrl_flow_meter; 3549 }; 3550 3551 struct mlx5_ifc_execute_aso_bits { 3552 u8 valid[0x1]; 3553 u8 reserved_at_1[0x7]; 3554 u8 aso_object_id[0x18]; 3555 3556 union mlx5_ifc_exe_aso_ctrl exe_aso_ctrl; 3557 }; 3558 3559 struct mlx5_ifc_flow_context_bits { 3560 struct mlx5_ifc_vlan_bits push_vlan; 3561 3562 u8 group_id[0x20]; 3563 3564 u8 reserved_at_40[0x8]; 3565 u8 flow_tag[0x18]; 3566 3567 u8 reserved_at_60[0x10]; 3568 u8 action[0x10]; 3569 3570 u8 extended_destination[0x1]; 3571 u8 reserved_at_81[0x1]; 3572 u8 flow_source[0x2]; 3573 u8 encrypt_decrypt_type[0x4]; 3574 u8 destination_list_size[0x18]; 3575 3576 u8 reserved_at_a0[0x8]; 3577 u8 flow_counter_list_size[0x18]; 3578 3579 u8 packet_reformat_id[0x20]; 3580 3581 u8 modify_header_id[0x20]; 3582 3583 struct mlx5_ifc_vlan_bits push_vlan_2; 3584 3585 u8 encrypt_decrypt_obj_id[0x20]; 3586 u8 reserved_at_140[0xc0]; 3587 3588 struct mlx5_ifc_fte_match_param_bits match_value; 3589 3590 struct mlx5_ifc_execute_aso_bits execute_aso[4]; 3591 3592 u8 reserved_at_1300[0x500]; 3593 3594 union mlx5_ifc_dest_format_struct_flow_counter_list_auto_bits destination[]; 3595 }; 3596 3597 enum { 3598 MLX5_XRC_SRQC_STATE_GOOD = 0x0, 3599 MLX5_XRC_SRQC_STATE_ERROR = 0x1, 3600 }; 3601 3602 struct mlx5_ifc_xrc_srqc_bits { 3603 u8 state[0x4]; 3604 u8 log_xrc_srq_size[0x4]; 3605 u8 reserved_at_8[0x18]; 3606 3607 u8 wq_signature[0x1]; 3608 u8 cont_srq[0x1]; 3609 u8 reserved_at_22[0x1]; 3610 u8 rlky[0x1]; 3611 u8 basic_cyclic_rcv_wqe[0x1]; 3612 u8 log_rq_stride[0x3]; 3613 u8 xrcd[0x18]; 3614 3615 u8 page_offset[0x6]; 3616 u8 reserved_at_46[0x1]; 3617 u8 dbr_umem_valid[0x1]; 3618 u8 cqn[0x18]; 3619 3620 u8 reserved_at_60[0x20]; 3621 3622 u8 user_index_equal_xrc_srqn[0x1]; 3623 u8 reserved_at_81[0x1]; 3624 u8 log_page_size[0x6]; 3625 u8 user_index[0x18]; 3626 3627 u8 reserved_at_a0[0x20]; 3628 3629 u8 reserved_at_c0[0x8]; 3630 u8 pd[0x18]; 3631 3632 u8 lwm[0x10]; 3633 u8 wqe_cnt[0x10]; 3634 3635 u8 reserved_at_100[0x40]; 3636 3637 u8 db_record_addr_h[0x20]; 3638 3639 u8 db_record_addr_l[0x1e]; 3640 u8 reserved_at_17e[0x2]; 3641 3642 u8 reserved_at_180[0x80]; 3643 }; 3644 3645 struct mlx5_ifc_vnic_diagnostic_statistics_bits { 3646 u8 counter_error_queues[0x20]; 3647 3648 u8 total_error_queues[0x20]; 3649 3650 u8 send_queue_priority_update_flow[0x20]; 3651 3652 u8 reserved_at_60[0x20]; 3653 3654 u8 nic_receive_steering_discard[0x40]; 3655 3656 u8 receive_discard_vport_down[0x40]; 3657 3658 u8 transmit_discard_vport_down[0x40]; 3659 3660 u8 async_eq_overrun[0x20]; 3661 3662 u8 comp_eq_overrun[0x20]; 3663 3664 u8 reserved_at_180[0x20]; 3665 3666 u8 invalid_command[0x20]; 3667 3668 u8 quota_exceeded_command[0x20]; 3669 3670 u8 internal_rq_out_of_buffer[0x20]; 3671 3672 u8 cq_overrun[0x20]; 3673 3674 u8 eth_wqe_too_small[0x20]; 3675 3676 u8 reserved_at_220[0xdc0]; 3677 }; 3678 3679 struct mlx5_ifc_traffic_counter_bits { 3680 u8 packets[0x40]; 3681 3682 u8 octets[0x40]; 3683 }; 3684 3685 struct mlx5_ifc_tisc_bits { 3686 u8 strict_lag_tx_port_affinity[0x1]; 3687 u8 tls_en[0x1]; 3688 u8 reserved_at_2[0x2]; 3689 u8 lag_tx_port_affinity[0x04]; 3690 3691 u8 reserved_at_8[0x4]; 3692 u8 prio[0x4]; 3693 u8 reserved_at_10[0x10]; 3694 3695 u8 reserved_at_20[0x100]; 3696 3697 u8 reserved_at_120[0x8]; 3698 u8 transport_domain[0x18]; 3699 3700 u8 reserved_at_140[0x8]; 3701 u8 underlay_qpn[0x18]; 3702 3703 u8 reserved_at_160[0x8]; 3704 u8 pd[0x18]; 3705 3706 u8 reserved_at_180[0x380]; 3707 }; 3708 3709 enum { 3710 MLX5_TIRC_DISP_TYPE_DIRECT = 0x0, 3711 MLX5_TIRC_DISP_TYPE_INDIRECT = 0x1, 3712 }; 3713 3714 enum { 3715 MLX5_TIRC_PACKET_MERGE_MASK_IPV4_LRO = BIT(0), 3716 MLX5_TIRC_PACKET_MERGE_MASK_IPV6_LRO = BIT(1), 3717 }; 3718 3719 enum { 3720 MLX5_RX_HASH_FN_NONE = 0x0, 3721 MLX5_RX_HASH_FN_INVERTED_XOR8 = 0x1, 3722 MLX5_RX_HASH_FN_TOEPLITZ = 0x2, 3723 }; 3724 3725 enum { 3726 MLX5_TIRC_SELF_LB_BLOCK_BLOCK_UNICAST = 0x1, 3727 MLX5_TIRC_SELF_LB_BLOCK_BLOCK_MULTICAST = 0x2, 3728 }; 3729 3730 struct mlx5_ifc_tirc_bits { 3731 u8 reserved_at_0[0x20]; 3732 3733 u8 disp_type[0x4]; 3734 u8 tls_en[0x1]; 3735 u8 reserved_at_25[0x1b]; 3736 3737 u8 reserved_at_40[0x40]; 3738 3739 u8 reserved_at_80[0x4]; 3740 u8 lro_timeout_period_usecs[0x10]; 3741 u8 packet_merge_mask[0x4]; 3742 u8 lro_max_ip_payload_size[0x8]; 3743 3744 u8 reserved_at_a0[0x40]; 3745 3746 u8 reserved_at_e0[0x8]; 3747 u8 inline_rqn[0x18]; 3748 3749 u8 rx_hash_symmetric[0x1]; 3750 u8 reserved_at_101[0x1]; 3751 u8 tunneled_offload_en[0x1]; 3752 u8 reserved_at_103[0x5]; 3753 u8 indirect_table[0x18]; 3754 3755 u8 rx_hash_fn[0x4]; 3756 u8 reserved_at_124[0x2]; 3757 u8 self_lb_block[0x2]; 3758 u8 transport_domain[0x18]; 3759 3760 u8 rx_hash_toeplitz_key[10][0x20]; 3761 3762 struct mlx5_ifc_rx_hash_field_select_bits rx_hash_field_selector_outer; 3763 3764 struct mlx5_ifc_rx_hash_field_select_bits rx_hash_field_selector_inner; 3765 3766 u8 reserved_at_2c0[0x4c0]; 3767 }; 3768 3769 enum { 3770 MLX5_SRQC_STATE_GOOD = 0x0, 3771 MLX5_SRQC_STATE_ERROR = 0x1, 3772 }; 3773 3774 struct mlx5_ifc_srqc_bits { 3775 u8 state[0x4]; 3776 u8 log_srq_size[0x4]; 3777 u8 reserved_at_8[0x18]; 3778 3779 u8 wq_signature[0x1]; 3780 u8 cont_srq[0x1]; 3781 u8 reserved_at_22[0x1]; 3782 u8 rlky[0x1]; 3783 u8 reserved_at_24[0x1]; 3784 u8 log_rq_stride[0x3]; 3785 u8 xrcd[0x18]; 3786 3787 u8 page_offset[0x6]; 3788 u8 reserved_at_46[0x2]; 3789 u8 cqn[0x18]; 3790 3791 u8 reserved_at_60[0x20]; 3792 3793 u8 reserved_at_80[0x2]; 3794 u8 log_page_size[0x6]; 3795 u8 reserved_at_88[0x18]; 3796 3797 u8 reserved_at_a0[0x20]; 3798 3799 u8 reserved_at_c0[0x8]; 3800 u8 pd[0x18]; 3801 3802 u8 lwm[0x10]; 3803 u8 wqe_cnt[0x10]; 3804 3805 u8 reserved_at_100[0x40]; 3806 3807 u8 dbr_addr[0x40]; 3808 3809 u8 reserved_at_180[0x80]; 3810 }; 3811 3812 enum { 3813 MLX5_SQC_STATE_RST = 0x0, 3814 MLX5_SQC_STATE_RDY = 0x1, 3815 MLX5_SQC_STATE_ERR = 0x3, 3816 }; 3817 3818 struct mlx5_ifc_sqc_bits { 3819 u8 rlky[0x1]; 3820 u8 cd_master[0x1]; 3821 u8 fre[0x1]; 3822 u8 flush_in_error_en[0x1]; 3823 u8 allow_multi_pkt_send_wqe[0x1]; 3824 u8 min_wqe_inline_mode[0x3]; 3825 u8 state[0x4]; 3826 u8 reg_umr[0x1]; 3827 u8 allow_swp[0x1]; 3828 u8 hairpin[0x1]; 3829 u8 reserved_at_f[0xb]; 3830 u8 ts_format[0x2]; 3831 u8 reserved_at_1c[0x4]; 3832 3833 u8 reserved_at_20[0x8]; 3834 u8 user_index[0x18]; 3835 3836 u8 reserved_at_40[0x8]; 3837 u8 cqn[0x18]; 3838 3839 u8 reserved_at_60[0x8]; 3840 u8 hairpin_peer_rq[0x18]; 3841 3842 u8 reserved_at_80[0x10]; 3843 u8 hairpin_peer_vhca[0x10]; 3844 3845 u8 reserved_at_a0[0x20]; 3846 3847 u8 reserved_at_c0[0x8]; 3848 u8 ts_cqe_to_dest_cqn[0x18]; 3849 3850 u8 reserved_at_e0[0x10]; 3851 u8 packet_pacing_rate_limit_index[0x10]; 3852 u8 tis_lst_sz[0x10]; 3853 u8 qos_queue_group_id[0x10]; 3854 3855 u8 reserved_at_120[0x40]; 3856 3857 u8 reserved_at_160[0x8]; 3858 u8 tis_num_0[0x18]; 3859 3860 struct mlx5_ifc_wq_bits wq; 3861 }; 3862 3863 enum { 3864 SCHEDULING_CONTEXT_ELEMENT_TYPE_TSAR = 0x0, 3865 SCHEDULING_CONTEXT_ELEMENT_TYPE_VPORT = 0x1, 3866 SCHEDULING_CONTEXT_ELEMENT_TYPE_VPORT_TC = 0x2, 3867 SCHEDULING_CONTEXT_ELEMENT_TYPE_PARA_VPORT_TC = 0x3, 3868 SCHEDULING_CONTEXT_ELEMENT_TYPE_QUEUE_GROUP = 0x4, 3869 }; 3870 3871 enum { 3872 ELEMENT_TYPE_CAP_MASK_TASR = 1 << 0, 3873 ELEMENT_TYPE_CAP_MASK_VPORT = 1 << 1, 3874 ELEMENT_TYPE_CAP_MASK_VPORT_TC = 1 << 2, 3875 ELEMENT_TYPE_CAP_MASK_PARA_VPORT_TC = 1 << 3, 3876 }; 3877 3878 struct mlx5_ifc_scheduling_context_bits { 3879 u8 element_type[0x8]; 3880 u8 reserved_at_8[0x18]; 3881 3882 u8 element_attributes[0x20]; 3883 3884 u8 parent_element_id[0x20]; 3885 3886 u8 reserved_at_60[0x40]; 3887 3888 u8 bw_share[0x20]; 3889 3890 u8 max_average_bw[0x20]; 3891 3892 u8 reserved_at_e0[0x120]; 3893 }; 3894 3895 struct mlx5_ifc_rqtc_bits { 3896 u8 reserved_at_0[0xa0]; 3897 3898 u8 reserved_at_a0[0x5]; 3899 u8 list_q_type[0x3]; 3900 u8 reserved_at_a8[0x8]; 3901 u8 rqt_max_size[0x10]; 3902 3903 u8 rq_vhca_id_format[0x1]; 3904 u8 reserved_at_c1[0xf]; 3905 u8 rqt_actual_size[0x10]; 3906 3907 u8 reserved_at_e0[0x6a0]; 3908 3909 struct mlx5_ifc_rq_num_bits rq_num[]; 3910 }; 3911 3912 enum { 3913 MLX5_RQC_MEM_RQ_TYPE_MEMORY_RQ_INLINE = 0x0, 3914 MLX5_RQC_MEM_RQ_TYPE_MEMORY_RQ_RMP = 0x1, 3915 }; 3916 3917 enum { 3918 MLX5_RQC_STATE_RST = 0x0, 3919 MLX5_RQC_STATE_RDY = 0x1, 3920 MLX5_RQC_STATE_ERR = 0x3, 3921 }; 3922 3923 enum { 3924 MLX5_RQC_SHAMPO_NO_MATCH_ALIGNMENT_GRANULARITY_BYTE = 0x0, 3925 MLX5_RQC_SHAMPO_NO_MATCH_ALIGNMENT_GRANULARITY_STRIDE = 0x1, 3926 MLX5_RQC_SHAMPO_NO_MATCH_ALIGNMENT_GRANULARITY_PAGE = 0x2, 3927 }; 3928 3929 enum { 3930 MLX5_RQC_SHAMPO_MATCH_CRITERIA_TYPE_NO_MATCH = 0x0, 3931 MLX5_RQC_SHAMPO_MATCH_CRITERIA_TYPE_EXTENDED = 0x1, 3932 MLX5_RQC_SHAMPO_MATCH_CRITERIA_TYPE_FIVE_TUPLE = 0x2, 3933 }; 3934 3935 struct mlx5_ifc_rqc_bits { 3936 u8 rlky[0x1]; 3937 u8 delay_drop_en[0x1]; 3938 u8 scatter_fcs[0x1]; 3939 u8 vsd[0x1]; 3940 u8 mem_rq_type[0x4]; 3941 u8 state[0x4]; 3942 u8 reserved_at_c[0x1]; 3943 u8 flush_in_error_en[0x1]; 3944 u8 hairpin[0x1]; 3945 u8 reserved_at_f[0xb]; 3946 u8 ts_format[0x2]; 3947 u8 reserved_at_1c[0x4]; 3948 3949 u8 reserved_at_20[0x8]; 3950 u8 user_index[0x18]; 3951 3952 u8 reserved_at_40[0x8]; 3953 u8 cqn[0x18]; 3954 3955 u8 counter_set_id[0x8]; 3956 u8 reserved_at_68[0x18]; 3957 3958 u8 reserved_at_80[0x8]; 3959 u8 rmpn[0x18]; 3960 3961 u8 reserved_at_a0[0x8]; 3962 u8 hairpin_peer_sq[0x18]; 3963 3964 u8 reserved_at_c0[0x10]; 3965 u8 hairpin_peer_vhca[0x10]; 3966 3967 u8 reserved_at_e0[0x46]; 3968 u8 shampo_no_match_alignment_granularity[0x2]; 3969 u8 reserved_at_128[0x6]; 3970 u8 shampo_match_criteria_type[0x2]; 3971 u8 reservation_timeout[0x10]; 3972 3973 u8 reserved_at_140[0x40]; 3974 3975 struct mlx5_ifc_wq_bits wq; 3976 }; 3977 3978 enum { 3979 MLX5_RMPC_STATE_RDY = 0x1, 3980 MLX5_RMPC_STATE_ERR = 0x3, 3981 }; 3982 3983 struct mlx5_ifc_rmpc_bits { 3984 u8 reserved_at_0[0x8]; 3985 u8 state[0x4]; 3986 u8 reserved_at_c[0x14]; 3987 3988 u8 basic_cyclic_rcv_wqe[0x1]; 3989 u8 reserved_at_21[0x1f]; 3990 3991 u8 reserved_at_40[0x140]; 3992 3993 struct mlx5_ifc_wq_bits wq; 3994 }; 3995 3996 enum { 3997 VHCA_ID_TYPE_HW = 0, 3998 VHCA_ID_TYPE_SW = 1, 3999 }; 4000 4001 struct mlx5_ifc_nic_vport_context_bits { 4002 u8 reserved_at_0[0x5]; 4003 u8 min_wqe_inline_mode[0x3]; 4004 u8 reserved_at_8[0x15]; 4005 u8 disable_mc_local_lb[0x1]; 4006 u8 disable_uc_local_lb[0x1]; 4007 u8 roce_en[0x1]; 4008 4009 u8 arm_change_event[0x1]; 4010 u8 reserved_at_21[0x1a]; 4011 u8 event_on_mtu[0x1]; 4012 u8 event_on_promisc_change[0x1]; 4013 u8 event_on_vlan_change[0x1]; 4014 u8 event_on_mc_address_change[0x1]; 4015 u8 event_on_uc_address_change[0x1]; 4016 4017 u8 vhca_id_type[0x1]; 4018 u8 reserved_at_41[0xb]; 4019 u8 affiliation_criteria[0x4]; 4020 u8 affiliated_vhca_id[0x10]; 4021 4022 u8 reserved_at_60[0xd0]; 4023 4024 u8 mtu[0x10]; 4025 4026 u8 system_image_guid[0x40]; 4027 u8 port_guid[0x40]; 4028 u8 node_guid[0x40]; 4029 4030 u8 reserved_at_200[0x140]; 4031 u8 qkey_violation_counter[0x10]; 4032 u8 reserved_at_350[0x430]; 4033 4034 u8 promisc_uc[0x1]; 4035 u8 promisc_mc[0x1]; 4036 u8 promisc_all[0x1]; 4037 u8 reserved_at_783[0x2]; 4038 u8 allowed_list_type[0x3]; 4039 u8 reserved_at_788[0xc]; 4040 u8 allowed_list_size[0xc]; 4041 4042 struct mlx5_ifc_mac_address_layout_bits permanent_address; 4043 4044 u8 reserved_at_7e0[0x20]; 4045 4046 u8 current_uc_mac_address[][0x40]; 4047 }; 4048 4049 enum { 4050 MLX5_MKC_ACCESS_MODE_PA = 0x0, 4051 MLX5_MKC_ACCESS_MODE_MTT = 0x1, 4052 MLX5_MKC_ACCESS_MODE_KLMS = 0x2, 4053 MLX5_MKC_ACCESS_MODE_KSM = 0x3, 4054 MLX5_MKC_ACCESS_MODE_SW_ICM = 0x4, 4055 MLX5_MKC_ACCESS_MODE_MEMIC = 0x5, 4056 }; 4057 4058 struct mlx5_ifc_mkc_bits { 4059 u8 reserved_at_0[0x1]; 4060 u8 free[0x1]; 4061 u8 reserved_at_2[0x1]; 4062 u8 access_mode_4_2[0x3]; 4063 u8 reserved_at_6[0x7]; 4064 u8 relaxed_ordering_write[0x1]; 4065 u8 reserved_at_e[0x1]; 4066 u8 small_fence_on_rdma_read_response[0x1]; 4067 u8 umr_en[0x1]; 4068 u8 a[0x1]; 4069 u8 rw[0x1]; 4070 u8 rr[0x1]; 4071 u8 lw[0x1]; 4072 u8 lr[0x1]; 4073 u8 access_mode_1_0[0x2]; 4074 u8 reserved_at_18[0x2]; 4075 u8 ma_translation_mode[0x2]; 4076 u8 reserved_at_1c[0x4]; 4077 4078 u8 qpn[0x18]; 4079 u8 mkey_7_0[0x8]; 4080 4081 u8 reserved_at_40[0x20]; 4082 4083 u8 length64[0x1]; 4084 u8 bsf_en[0x1]; 4085 u8 sync_umr[0x1]; 4086 u8 reserved_at_63[0x2]; 4087 u8 expected_sigerr_count[0x1]; 4088 u8 reserved_at_66[0x1]; 4089 u8 en_rinval[0x1]; 4090 u8 pd[0x18]; 4091 4092 u8 start_addr[0x40]; 4093 4094 u8 len[0x40]; 4095 4096 u8 bsf_octword_size[0x20]; 4097 4098 u8 reserved_at_120[0x80]; 4099 4100 u8 translations_octword_size[0x20]; 4101 4102 u8 reserved_at_1c0[0x19]; 4103 u8 relaxed_ordering_read[0x1]; 4104 u8 reserved_at_1d9[0x1]; 4105 u8 log_page_size[0x5]; 4106 4107 u8 reserved_at_1e0[0x20]; 4108 }; 4109 4110 struct mlx5_ifc_pkey_bits { 4111 u8 reserved_at_0[0x10]; 4112 u8 pkey[0x10]; 4113 }; 4114 4115 struct mlx5_ifc_array128_auto_bits { 4116 u8 array128_auto[16][0x8]; 4117 }; 4118 4119 struct mlx5_ifc_hca_vport_context_bits { 4120 u8 field_select[0x20]; 4121 4122 u8 reserved_at_20[0xe0]; 4123 4124 u8 sm_virt_aware[0x1]; 4125 u8 has_smi[0x1]; 4126 u8 has_raw[0x1]; 4127 u8 grh_required[0x1]; 4128 u8 reserved_at_104[0xc]; 4129 u8 port_physical_state[0x4]; 4130 u8 vport_state_policy[0x4]; 4131 u8 port_state[0x4]; 4132 u8 vport_state[0x4]; 4133 4134 u8 reserved_at_120[0x20]; 4135 4136 u8 system_image_guid[0x40]; 4137 4138 u8 port_guid[0x40]; 4139 4140 u8 node_guid[0x40]; 4141 4142 u8 cap_mask1[0x20]; 4143 4144 u8 cap_mask1_field_select[0x20]; 4145 4146 u8 cap_mask2[0x20]; 4147 4148 u8 cap_mask2_field_select[0x20]; 4149 4150 u8 reserved_at_280[0x80]; 4151 4152 u8 lid[0x10]; 4153 u8 reserved_at_310[0x4]; 4154 u8 init_type_reply[0x4]; 4155 u8 lmc[0x3]; 4156 u8 subnet_timeout[0x5]; 4157 4158 u8 sm_lid[0x10]; 4159 u8 sm_sl[0x4]; 4160 u8 reserved_at_334[0xc]; 4161 4162 u8 qkey_violation_counter[0x10]; 4163 u8 pkey_violation_counter[0x10]; 4164 4165 u8 reserved_at_360[0xca0]; 4166 }; 4167 4168 struct mlx5_ifc_esw_vport_context_bits { 4169 u8 fdb_to_vport_reg_c[0x1]; 4170 u8 reserved_at_1[0x2]; 4171 u8 vport_svlan_strip[0x1]; 4172 u8 vport_cvlan_strip[0x1]; 4173 u8 vport_svlan_insert[0x1]; 4174 u8 vport_cvlan_insert[0x2]; 4175 u8 fdb_to_vport_reg_c_id[0x8]; 4176 u8 reserved_at_10[0x10]; 4177 4178 u8 reserved_at_20[0x20]; 4179 4180 u8 svlan_cfi[0x1]; 4181 u8 svlan_pcp[0x3]; 4182 u8 svlan_id[0xc]; 4183 u8 cvlan_cfi[0x1]; 4184 u8 cvlan_pcp[0x3]; 4185 u8 cvlan_id[0xc]; 4186 4187 u8 reserved_at_60[0x720]; 4188 4189 u8 sw_steering_vport_icm_address_rx[0x40]; 4190 4191 u8 sw_steering_vport_icm_address_tx[0x40]; 4192 }; 4193 4194 enum { 4195 MLX5_EQC_STATUS_OK = 0x0, 4196 MLX5_EQC_STATUS_EQ_WRITE_FAILURE = 0xa, 4197 }; 4198 4199 enum { 4200 MLX5_EQC_ST_ARMED = 0x9, 4201 MLX5_EQC_ST_FIRED = 0xa, 4202 }; 4203 4204 struct mlx5_ifc_eqc_bits { 4205 u8 status[0x4]; 4206 u8 reserved_at_4[0x9]; 4207 u8 ec[0x1]; 4208 u8 oi[0x1]; 4209 u8 reserved_at_f[0x5]; 4210 u8 st[0x4]; 4211 u8 reserved_at_18[0x8]; 4212 4213 u8 reserved_at_20[0x20]; 4214 4215 u8 reserved_at_40[0x14]; 4216 u8 page_offset[0x6]; 4217 u8 reserved_at_5a[0x6]; 4218 4219 u8 reserved_at_60[0x3]; 4220 u8 log_eq_size[0x5]; 4221 u8 uar_page[0x18]; 4222 4223 u8 reserved_at_80[0x20]; 4224 4225 u8 reserved_at_a0[0x14]; 4226 u8 intr[0xc]; 4227 4228 u8 reserved_at_c0[0x3]; 4229 u8 log_page_size[0x5]; 4230 u8 reserved_at_c8[0x18]; 4231 4232 u8 reserved_at_e0[0x60]; 4233 4234 u8 reserved_at_140[0x8]; 4235 u8 consumer_counter[0x18]; 4236 4237 u8 reserved_at_160[0x8]; 4238 u8 producer_counter[0x18]; 4239 4240 u8 reserved_at_180[0x80]; 4241 }; 4242 4243 enum { 4244 MLX5_DCTC_STATE_ACTIVE = 0x0, 4245 MLX5_DCTC_STATE_DRAINING = 0x1, 4246 MLX5_DCTC_STATE_DRAINED = 0x2, 4247 }; 4248 4249 enum { 4250 MLX5_DCTC_CS_RES_DISABLE = 0x0, 4251 MLX5_DCTC_CS_RES_NA = 0x1, 4252 MLX5_DCTC_CS_RES_UP_TO_64B = 0x2, 4253 }; 4254 4255 enum { 4256 MLX5_DCTC_MTU_256_BYTES = 0x1, 4257 MLX5_DCTC_MTU_512_BYTES = 0x2, 4258 MLX5_DCTC_MTU_1K_BYTES = 0x3, 4259 MLX5_DCTC_MTU_2K_BYTES = 0x4, 4260 MLX5_DCTC_MTU_4K_BYTES = 0x5, 4261 }; 4262 4263 struct mlx5_ifc_dctc_bits { 4264 u8 reserved_at_0[0x4]; 4265 u8 state[0x4]; 4266 u8 reserved_at_8[0x18]; 4267 4268 u8 reserved_at_20[0x8]; 4269 u8 user_index[0x18]; 4270 4271 u8 reserved_at_40[0x8]; 4272 u8 cqn[0x18]; 4273 4274 u8 counter_set_id[0x8]; 4275 u8 atomic_mode[0x4]; 4276 u8 rre[0x1]; 4277 u8 rwe[0x1]; 4278 u8 rae[0x1]; 4279 u8 atomic_like_write_en[0x1]; 4280 u8 latency_sensitive[0x1]; 4281 u8 rlky[0x1]; 4282 u8 free_ar[0x1]; 4283 u8 reserved_at_73[0xd]; 4284 4285 u8 reserved_at_80[0x8]; 4286 u8 cs_res[0x8]; 4287 u8 reserved_at_90[0x3]; 4288 u8 min_rnr_nak[0x5]; 4289 u8 reserved_at_98[0x8]; 4290 4291 u8 reserved_at_a0[0x8]; 4292 u8 srqn_xrqn[0x18]; 4293 4294 u8 reserved_at_c0[0x8]; 4295 u8 pd[0x18]; 4296 4297 u8 tclass[0x8]; 4298 u8 reserved_at_e8[0x4]; 4299 u8 flow_label[0x14]; 4300 4301 u8 dc_access_key[0x40]; 4302 4303 u8 reserved_at_140[0x5]; 4304 u8 mtu[0x3]; 4305 u8 port[0x8]; 4306 u8 pkey_index[0x10]; 4307 4308 u8 reserved_at_160[0x8]; 4309 u8 my_addr_index[0x8]; 4310 u8 reserved_at_170[0x8]; 4311 u8 hop_limit[0x8]; 4312 4313 u8 dc_access_key_violation_count[0x20]; 4314 4315 u8 reserved_at_1a0[0x14]; 4316 u8 dei_cfi[0x1]; 4317 u8 eth_prio[0x3]; 4318 u8 ecn[0x2]; 4319 u8 dscp[0x6]; 4320 4321 u8 reserved_at_1c0[0x20]; 4322 u8 ece[0x20]; 4323 }; 4324 4325 enum { 4326 MLX5_CQC_STATUS_OK = 0x0, 4327 MLX5_CQC_STATUS_CQ_OVERFLOW = 0x9, 4328 MLX5_CQC_STATUS_CQ_WRITE_FAIL = 0xa, 4329 }; 4330 4331 enum { 4332 MLX5_CQC_CQE_SZ_64_BYTES = 0x0, 4333 MLX5_CQC_CQE_SZ_128_BYTES = 0x1, 4334 }; 4335 4336 enum { 4337 MLX5_CQC_ST_SOLICITED_NOTIFICATION_REQUEST_ARMED = 0x6, 4338 MLX5_CQC_ST_NOTIFICATION_REQUEST_ARMED = 0x9, 4339 MLX5_CQC_ST_FIRED = 0xa, 4340 }; 4341 4342 enum { 4343 MLX5_CQ_PERIOD_MODE_START_FROM_EQE = 0x0, 4344 MLX5_CQ_PERIOD_MODE_START_FROM_CQE = 0x1, 4345 MLX5_CQ_PERIOD_NUM_MODES 4346 }; 4347 4348 struct mlx5_ifc_cqc_bits { 4349 u8 status[0x4]; 4350 u8 reserved_at_4[0x2]; 4351 u8 dbr_umem_valid[0x1]; 4352 u8 apu_cq[0x1]; 4353 u8 cqe_sz[0x3]; 4354 u8 cc[0x1]; 4355 u8 reserved_at_c[0x1]; 4356 u8 scqe_break_moderation_en[0x1]; 4357 u8 oi[0x1]; 4358 u8 cq_period_mode[0x2]; 4359 u8 cqe_comp_en[0x1]; 4360 u8 mini_cqe_res_format[0x2]; 4361 u8 st[0x4]; 4362 u8 reserved_at_18[0x6]; 4363 u8 cqe_compression_layout[0x2]; 4364 4365 u8 reserved_at_20[0x20]; 4366 4367 u8 reserved_at_40[0x14]; 4368 u8 page_offset[0x6]; 4369 u8 reserved_at_5a[0x6]; 4370 4371 u8 reserved_at_60[0x3]; 4372 u8 log_cq_size[0x5]; 4373 u8 uar_page[0x18]; 4374 4375 u8 reserved_at_80[0x4]; 4376 u8 cq_period[0xc]; 4377 u8 cq_max_count[0x10]; 4378 4379 u8 c_eqn_or_apu_element[0x20]; 4380 4381 u8 reserved_at_c0[0x3]; 4382 u8 log_page_size[0x5]; 4383 u8 reserved_at_c8[0x18]; 4384 4385 u8 reserved_at_e0[0x20]; 4386 4387 u8 reserved_at_100[0x8]; 4388 u8 last_notified_index[0x18]; 4389 4390 u8 reserved_at_120[0x8]; 4391 u8 last_solicit_index[0x18]; 4392 4393 u8 reserved_at_140[0x8]; 4394 u8 consumer_counter[0x18]; 4395 4396 u8 reserved_at_160[0x8]; 4397 u8 producer_counter[0x18]; 4398 4399 u8 reserved_at_180[0x40]; 4400 4401 u8 dbr_addr[0x40]; 4402 }; 4403 4404 union mlx5_ifc_cong_control_roce_ecn_auto_bits { 4405 struct mlx5_ifc_cong_control_802_1qau_rp_bits cong_control_802_1qau_rp; 4406 struct mlx5_ifc_cong_control_r_roce_ecn_rp_bits cong_control_r_roce_ecn_rp; 4407 struct mlx5_ifc_cong_control_r_roce_ecn_np_bits cong_control_r_roce_ecn_np; 4408 struct mlx5_ifc_cong_control_r_roce_general_bits cong_control_r_roce_general; 4409 u8 reserved_at_0[0x800]; 4410 }; 4411 4412 struct mlx5_ifc_query_adapter_param_block_bits { 4413 u8 reserved_at_0[0xc0]; 4414 4415 u8 reserved_at_c0[0x8]; 4416 u8 ieee_vendor_id[0x18]; 4417 4418 u8 reserved_at_e0[0x10]; 4419 u8 vsd_vendor_id[0x10]; 4420 4421 u8 vsd[208][0x8]; 4422 4423 u8 vsd_contd_psid[16][0x8]; 4424 }; 4425 4426 enum { 4427 MLX5_XRQC_STATE_GOOD = 0x0, 4428 MLX5_XRQC_STATE_ERROR = 0x1, 4429 }; 4430 4431 enum { 4432 MLX5_XRQC_TOPOLOGY_NO_SPECIAL_TOPOLOGY = 0x0, 4433 MLX5_XRQC_TOPOLOGY_TAG_MATCHING = 0x1, 4434 }; 4435 4436 enum { 4437 MLX5_XRQC_OFFLOAD_RNDV = 0x1, 4438 }; 4439 4440 struct mlx5_ifc_tag_matching_topology_context_bits { 4441 u8 log_matching_list_sz[0x4]; 4442 u8 reserved_at_4[0xc]; 4443 u8 append_next_index[0x10]; 4444 4445 u8 sw_phase_cnt[0x10]; 4446 u8 hw_phase_cnt[0x10]; 4447 4448 u8 reserved_at_40[0x40]; 4449 }; 4450 4451 struct mlx5_ifc_xrqc_bits { 4452 u8 state[0x4]; 4453 u8 rlkey[0x1]; 4454 u8 reserved_at_5[0xf]; 4455 u8 topology[0x4]; 4456 u8 reserved_at_18[0x4]; 4457 u8 offload[0x4]; 4458 4459 u8 reserved_at_20[0x8]; 4460 u8 user_index[0x18]; 4461 4462 u8 reserved_at_40[0x8]; 4463 u8 cqn[0x18]; 4464 4465 u8 reserved_at_60[0xa0]; 4466 4467 struct mlx5_ifc_tag_matching_topology_context_bits tag_matching_topology_context; 4468 4469 u8 reserved_at_180[0x280]; 4470 4471 struct mlx5_ifc_wq_bits wq; 4472 }; 4473 4474 union mlx5_ifc_modify_field_select_resize_field_select_auto_bits { 4475 struct mlx5_ifc_modify_field_select_bits modify_field_select; 4476 struct mlx5_ifc_resize_field_select_bits resize_field_select; 4477 u8 reserved_at_0[0x20]; 4478 }; 4479 4480 union mlx5_ifc_field_select_802_1_r_roce_auto_bits { 4481 struct mlx5_ifc_field_select_802_1qau_rp_bits field_select_802_1qau_rp; 4482 struct mlx5_ifc_field_select_r_roce_rp_bits field_select_r_roce_rp; 4483 struct mlx5_ifc_field_select_r_roce_np_bits field_select_r_roce_np; 4484 u8 reserved_at_0[0x20]; 4485 }; 4486 4487 union mlx5_ifc_eth_cntrs_grp_data_layout_auto_bits { 4488 struct mlx5_ifc_eth_802_3_cntrs_grp_data_layout_bits eth_802_3_cntrs_grp_data_layout; 4489 struct mlx5_ifc_eth_2863_cntrs_grp_data_layout_bits eth_2863_cntrs_grp_data_layout; 4490 struct mlx5_ifc_eth_2819_cntrs_grp_data_layout_bits eth_2819_cntrs_grp_data_layout; 4491 struct mlx5_ifc_eth_3635_cntrs_grp_data_layout_bits eth_3635_cntrs_grp_data_layout; 4492 struct mlx5_ifc_eth_extended_cntrs_grp_data_layout_bits eth_extended_cntrs_grp_data_layout; 4493 struct mlx5_ifc_eth_per_prio_grp_data_layout_bits eth_per_prio_grp_data_layout; 4494 struct mlx5_ifc_eth_per_tc_prio_grp_data_layout_bits eth_per_tc_prio_grp_data_layout; 4495 struct mlx5_ifc_eth_per_tc_congest_prio_grp_data_layout_bits eth_per_tc_congest_prio_grp_data_layout; 4496 struct mlx5_ifc_ib_port_cntrs_grp_data_layout_bits ib_port_cntrs_grp_data_layout; 4497 struct mlx5_ifc_phys_layer_cntrs_bits phys_layer_cntrs; 4498 struct mlx5_ifc_phys_layer_statistical_cntrs_bits phys_layer_statistical_cntrs; 4499 u8 reserved_at_0[0x7c0]; 4500 }; 4501 4502 union mlx5_ifc_pcie_cntrs_grp_data_layout_auto_bits { 4503 struct mlx5_ifc_pcie_perf_cntrs_grp_data_layout_bits pcie_perf_cntrs_grp_data_layout; 4504 u8 reserved_at_0[0x7c0]; 4505 }; 4506 4507 union mlx5_ifc_event_auto_bits { 4508 struct mlx5_ifc_comp_event_bits comp_event; 4509 struct mlx5_ifc_dct_events_bits dct_events; 4510 struct mlx5_ifc_qp_events_bits qp_events; 4511 struct mlx5_ifc_wqe_associated_page_fault_event_bits wqe_associated_page_fault_event; 4512 struct mlx5_ifc_rdma_page_fault_event_bits rdma_page_fault_event; 4513 struct mlx5_ifc_cq_error_bits cq_error; 4514 struct mlx5_ifc_dropped_packet_logged_bits dropped_packet_logged; 4515 struct mlx5_ifc_port_state_change_event_bits port_state_change_event; 4516 struct mlx5_ifc_gpio_event_bits gpio_event; 4517 struct mlx5_ifc_db_bf_congestion_event_bits db_bf_congestion_event; 4518 struct mlx5_ifc_stall_vl_event_bits stall_vl_event; 4519 struct mlx5_ifc_cmd_inter_comp_event_bits cmd_inter_comp_event; 4520 u8 reserved_at_0[0xe0]; 4521 }; 4522 4523 struct mlx5_ifc_health_buffer_bits { 4524 u8 reserved_at_0[0x100]; 4525 4526 u8 assert_existptr[0x20]; 4527 4528 u8 assert_callra[0x20]; 4529 4530 u8 reserved_at_140[0x20]; 4531 4532 u8 time[0x20]; 4533 4534 u8 fw_version[0x20]; 4535 4536 u8 hw_id[0x20]; 4537 4538 u8 rfr[0x1]; 4539 u8 reserved_at_1c1[0x3]; 4540 u8 valid[0x1]; 4541 u8 severity[0x3]; 4542 u8 reserved_at_1c8[0x18]; 4543 4544 u8 irisc_index[0x8]; 4545 u8 synd[0x8]; 4546 u8 ext_synd[0x10]; 4547 }; 4548 4549 struct mlx5_ifc_register_loopback_control_bits { 4550 u8 no_lb[0x1]; 4551 u8 reserved_at_1[0x7]; 4552 u8 port[0x8]; 4553 u8 reserved_at_10[0x10]; 4554 4555 u8 reserved_at_20[0x60]; 4556 }; 4557 4558 struct mlx5_ifc_vport_tc_element_bits { 4559 u8 traffic_class[0x4]; 4560 u8 reserved_at_4[0xc]; 4561 u8 vport_number[0x10]; 4562 }; 4563 4564 struct mlx5_ifc_vport_element_bits { 4565 u8 reserved_at_0[0x10]; 4566 u8 vport_number[0x10]; 4567 }; 4568 4569 enum { 4570 TSAR_ELEMENT_TSAR_TYPE_DWRR = 0x0, 4571 TSAR_ELEMENT_TSAR_TYPE_ROUND_ROBIN = 0x1, 4572 TSAR_ELEMENT_TSAR_TYPE_ETS = 0x2, 4573 }; 4574 4575 struct mlx5_ifc_tsar_element_bits { 4576 u8 reserved_at_0[0x8]; 4577 u8 tsar_type[0x8]; 4578 u8 reserved_at_10[0x10]; 4579 }; 4580 4581 enum { 4582 MLX5_TEARDOWN_HCA_OUT_FORCE_STATE_SUCCESS = 0x0, 4583 MLX5_TEARDOWN_HCA_OUT_FORCE_STATE_FAIL = 0x1, 4584 }; 4585 4586 struct mlx5_ifc_teardown_hca_out_bits { 4587 u8 status[0x8]; 4588 u8 reserved_at_8[0x18]; 4589 4590 u8 syndrome[0x20]; 4591 4592 u8 reserved_at_40[0x3f]; 4593 4594 u8 state[0x1]; 4595 }; 4596 4597 enum { 4598 MLX5_TEARDOWN_HCA_IN_PROFILE_GRACEFUL_CLOSE = 0x0, 4599 MLX5_TEARDOWN_HCA_IN_PROFILE_FORCE_CLOSE = 0x1, 4600 MLX5_TEARDOWN_HCA_IN_PROFILE_PREPARE_FAST_TEARDOWN = 0x2, 4601 }; 4602 4603 struct mlx5_ifc_teardown_hca_in_bits { 4604 u8 opcode[0x10]; 4605 u8 reserved_at_10[0x10]; 4606 4607 u8 reserved_at_20[0x10]; 4608 u8 op_mod[0x10]; 4609 4610 u8 reserved_at_40[0x10]; 4611 u8 profile[0x10]; 4612 4613 u8 reserved_at_60[0x20]; 4614 }; 4615 4616 struct mlx5_ifc_sqerr2rts_qp_out_bits { 4617 u8 status[0x8]; 4618 u8 reserved_at_8[0x18]; 4619 4620 u8 syndrome[0x20]; 4621 4622 u8 reserved_at_40[0x40]; 4623 }; 4624 4625 struct mlx5_ifc_sqerr2rts_qp_in_bits { 4626 u8 opcode[0x10]; 4627 u8 uid[0x10]; 4628 4629 u8 reserved_at_20[0x10]; 4630 u8 op_mod[0x10]; 4631 4632 u8 reserved_at_40[0x8]; 4633 u8 qpn[0x18]; 4634 4635 u8 reserved_at_60[0x20]; 4636 4637 u8 opt_param_mask[0x20]; 4638 4639 u8 reserved_at_a0[0x20]; 4640 4641 struct mlx5_ifc_qpc_bits qpc; 4642 4643 u8 reserved_at_800[0x80]; 4644 }; 4645 4646 struct mlx5_ifc_sqd2rts_qp_out_bits { 4647 u8 status[0x8]; 4648 u8 reserved_at_8[0x18]; 4649 4650 u8 syndrome[0x20]; 4651 4652 u8 reserved_at_40[0x40]; 4653 }; 4654 4655 struct mlx5_ifc_sqd2rts_qp_in_bits { 4656 u8 opcode[0x10]; 4657 u8 uid[0x10]; 4658 4659 u8 reserved_at_20[0x10]; 4660 u8 op_mod[0x10]; 4661 4662 u8 reserved_at_40[0x8]; 4663 u8 qpn[0x18]; 4664 4665 u8 reserved_at_60[0x20]; 4666 4667 u8 opt_param_mask[0x20]; 4668 4669 u8 reserved_at_a0[0x20]; 4670 4671 struct mlx5_ifc_qpc_bits qpc; 4672 4673 u8 reserved_at_800[0x80]; 4674 }; 4675 4676 struct mlx5_ifc_set_roce_address_out_bits { 4677 u8 status[0x8]; 4678 u8 reserved_at_8[0x18]; 4679 4680 u8 syndrome[0x20]; 4681 4682 u8 reserved_at_40[0x40]; 4683 }; 4684 4685 struct mlx5_ifc_set_roce_address_in_bits { 4686 u8 opcode[0x10]; 4687 u8 reserved_at_10[0x10]; 4688 4689 u8 reserved_at_20[0x10]; 4690 u8 op_mod[0x10]; 4691 4692 u8 roce_address_index[0x10]; 4693 u8 reserved_at_50[0xc]; 4694 u8 vhca_port_num[0x4]; 4695 4696 u8 reserved_at_60[0x20]; 4697 4698 struct mlx5_ifc_roce_addr_layout_bits roce_address; 4699 }; 4700 4701 struct mlx5_ifc_set_mad_demux_out_bits { 4702 u8 status[0x8]; 4703 u8 reserved_at_8[0x18]; 4704 4705 u8 syndrome[0x20]; 4706 4707 u8 reserved_at_40[0x40]; 4708 }; 4709 4710 enum { 4711 MLX5_SET_MAD_DEMUX_IN_DEMUX_MODE_PASS_ALL = 0x0, 4712 MLX5_SET_MAD_DEMUX_IN_DEMUX_MODE_SELECTIVE = 0x2, 4713 }; 4714 4715 struct mlx5_ifc_set_mad_demux_in_bits { 4716 u8 opcode[0x10]; 4717 u8 reserved_at_10[0x10]; 4718 4719 u8 reserved_at_20[0x10]; 4720 u8 op_mod[0x10]; 4721 4722 u8 reserved_at_40[0x20]; 4723 4724 u8 reserved_at_60[0x6]; 4725 u8 demux_mode[0x2]; 4726 u8 reserved_at_68[0x18]; 4727 }; 4728 4729 struct mlx5_ifc_set_l2_table_entry_out_bits { 4730 u8 status[0x8]; 4731 u8 reserved_at_8[0x18]; 4732 4733 u8 syndrome[0x20]; 4734 4735 u8 reserved_at_40[0x40]; 4736 }; 4737 4738 struct mlx5_ifc_set_l2_table_entry_in_bits { 4739 u8 opcode[0x10]; 4740 u8 reserved_at_10[0x10]; 4741 4742 u8 reserved_at_20[0x10]; 4743 u8 op_mod[0x10]; 4744 4745 u8 reserved_at_40[0x60]; 4746 4747 u8 reserved_at_a0[0x8]; 4748 u8 table_index[0x18]; 4749 4750 u8 reserved_at_c0[0x20]; 4751 4752 u8 reserved_at_e0[0x13]; 4753 u8 vlan_valid[0x1]; 4754 u8 vlan[0xc]; 4755 4756 struct mlx5_ifc_mac_address_layout_bits mac_address; 4757 4758 u8 reserved_at_140[0xc0]; 4759 }; 4760 4761 struct mlx5_ifc_set_issi_out_bits { 4762 u8 status[0x8]; 4763 u8 reserved_at_8[0x18]; 4764 4765 u8 syndrome[0x20]; 4766 4767 u8 reserved_at_40[0x40]; 4768 }; 4769 4770 struct mlx5_ifc_set_issi_in_bits { 4771 u8 opcode[0x10]; 4772 u8 reserved_at_10[0x10]; 4773 4774 u8 reserved_at_20[0x10]; 4775 u8 op_mod[0x10]; 4776 4777 u8 reserved_at_40[0x10]; 4778 u8 current_issi[0x10]; 4779 4780 u8 reserved_at_60[0x20]; 4781 }; 4782 4783 struct mlx5_ifc_set_hca_cap_out_bits { 4784 u8 status[0x8]; 4785 u8 reserved_at_8[0x18]; 4786 4787 u8 syndrome[0x20]; 4788 4789 u8 reserved_at_40[0x40]; 4790 }; 4791 4792 struct mlx5_ifc_set_hca_cap_in_bits { 4793 u8 opcode[0x10]; 4794 u8 reserved_at_10[0x10]; 4795 4796 u8 reserved_at_20[0x10]; 4797 u8 op_mod[0x10]; 4798 4799 u8 other_function[0x1]; 4800 u8 reserved_at_41[0xf]; 4801 u8 function_id[0x10]; 4802 4803 u8 reserved_at_60[0x20]; 4804 4805 union mlx5_ifc_hca_cap_union_bits capability; 4806 }; 4807 4808 enum { 4809 MLX5_SET_FTE_MODIFY_ENABLE_MASK_ACTION = 0x0, 4810 MLX5_SET_FTE_MODIFY_ENABLE_MASK_FLOW_TAG = 0x1, 4811 MLX5_SET_FTE_MODIFY_ENABLE_MASK_DESTINATION_LIST = 0x2, 4812 MLX5_SET_FTE_MODIFY_ENABLE_MASK_FLOW_COUNTERS = 0x3, 4813 MLX5_SET_FTE_MODIFY_ENABLE_MASK_IPSEC_OBJ_ID = 0x4 4814 }; 4815 4816 struct mlx5_ifc_set_fte_out_bits { 4817 u8 status[0x8]; 4818 u8 reserved_at_8[0x18]; 4819 4820 u8 syndrome[0x20]; 4821 4822 u8 reserved_at_40[0x40]; 4823 }; 4824 4825 struct mlx5_ifc_set_fte_in_bits { 4826 u8 opcode[0x10]; 4827 u8 reserved_at_10[0x10]; 4828 4829 u8 reserved_at_20[0x10]; 4830 u8 op_mod[0x10]; 4831 4832 u8 other_vport[0x1]; 4833 u8 reserved_at_41[0xf]; 4834 u8 vport_number[0x10]; 4835 4836 u8 reserved_at_60[0x20]; 4837 4838 u8 table_type[0x8]; 4839 u8 reserved_at_88[0x18]; 4840 4841 u8 reserved_at_a0[0x8]; 4842 u8 table_id[0x18]; 4843 4844 u8 ignore_flow_level[0x1]; 4845 u8 reserved_at_c1[0x17]; 4846 u8 modify_enable_mask[0x8]; 4847 4848 u8 reserved_at_e0[0x20]; 4849 4850 u8 flow_index[0x20]; 4851 4852 u8 reserved_at_120[0xe0]; 4853 4854 struct mlx5_ifc_flow_context_bits flow_context; 4855 }; 4856 4857 struct mlx5_ifc_rts2rts_qp_out_bits { 4858 u8 status[0x8]; 4859 u8 reserved_at_8[0x18]; 4860 4861 u8 syndrome[0x20]; 4862 4863 u8 reserved_at_40[0x20]; 4864 u8 ece[0x20]; 4865 }; 4866 4867 struct mlx5_ifc_rts2rts_qp_in_bits { 4868 u8 opcode[0x10]; 4869 u8 uid[0x10]; 4870 4871 u8 reserved_at_20[0x10]; 4872 u8 op_mod[0x10]; 4873 4874 u8 reserved_at_40[0x8]; 4875 u8 qpn[0x18]; 4876 4877 u8 reserved_at_60[0x20]; 4878 4879 u8 opt_param_mask[0x20]; 4880 4881 u8 ece[0x20]; 4882 4883 struct mlx5_ifc_qpc_bits qpc; 4884 4885 u8 reserved_at_800[0x80]; 4886 }; 4887 4888 struct mlx5_ifc_rtr2rts_qp_out_bits { 4889 u8 status[0x8]; 4890 u8 reserved_at_8[0x18]; 4891 4892 u8 syndrome[0x20]; 4893 4894 u8 reserved_at_40[0x20]; 4895 u8 ece[0x20]; 4896 }; 4897 4898 struct mlx5_ifc_rtr2rts_qp_in_bits { 4899 u8 opcode[0x10]; 4900 u8 uid[0x10]; 4901 4902 u8 reserved_at_20[0x10]; 4903 u8 op_mod[0x10]; 4904 4905 u8 reserved_at_40[0x8]; 4906 u8 qpn[0x18]; 4907 4908 u8 reserved_at_60[0x20]; 4909 4910 u8 opt_param_mask[0x20]; 4911 4912 u8 ece[0x20]; 4913 4914 struct mlx5_ifc_qpc_bits qpc; 4915 4916 u8 reserved_at_800[0x80]; 4917 }; 4918 4919 struct mlx5_ifc_rst2init_qp_out_bits { 4920 u8 status[0x8]; 4921 u8 reserved_at_8[0x18]; 4922 4923 u8 syndrome[0x20]; 4924 4925 u8 reserved_at_40[0x20]; 4926 u8 ece[0x20]; 4927 }; 4928 4929 struct mlx5_ifc_rst2init_qp_in_bits { 4930 u8 opcode[0x10]; 4931 u8 uid[0x10]; 4932 4933 u8 reserved_at_20[0x10]; 4934 u8 op_mod[0x10]; 4935 4936 u8 reserved_at_40[0x8]; 4937 u8 qpn[0x18]; 4938 4939 u8 reserved_at_60[0x20]; 4940 4941 u8 opt_param_mask[0x20]; 4942 4943 u8 ece[0x20]; 4944 4945 struct mlx5_ifc_qpc_bits qpc; 4946 4947 u8 reserved_at_800[0x80]; 4948 }; 4949 4950 struct mlx5_ifc_query_xrq_out_bits { 4951 u8 status[0x8]; 4952 u8 reserved_at_8[0x18]; 4953 4954 u8 syndrome[0x20]; 4955 4956 u8 reserved_at_40[0x40]; 4957 4958 struct mlx5_ifc_xrqc_bits xrq_context; 4959 }; 4960 4961 struct mlx5_ifc_query_xrq_in_bits { 4962 u8 opcode[0x10]; 4963 u8 reserved_at_10[0x10]; 4964 4965 u8 reserved_at_20[0x10]; 4966 u8 op_mod[0x10]; 4967 4968 u8 reserved_at_40[0x8]; 4969 u8 xrqn[0x18]; 4970 4971 u8 reserved_at_60[0x20]; 4972 }; 4973 4974 struct mlx5_ifc_query_xrc_srq_out_bits { 4975 u8 status[0x8]; 4976 u8 reserved_at_8[0x18]; 4977 4978 u8 syndrome[0x20]; 4979 4980 u8 reserved_at_40[0x40]; 4981 4982 struct mlx5_ifc_xrc_srqc_bits xrc_srq_context_entry; 4983 4984 u8 reserved_at_280[0x600]; 4985 4986 u8 pas[][0x40]; 4987 }; 4988 4989 struct mlx5_ifc_query_xrc_srq_in_bits { 4990 u8 opcode[0x10]; 4991 u8 reserved_at_10[0x10]; 4992 4993 u8 reserved_at_20[0x10]; 4994 u8 op_mod[0x10]; 4995 4996 u8 reserved_at_40[0x8]; 4997 u8 xrc_srqn[0x18]; 4998 4999 u8 reserved_at_60[0x20]; 5000 }; 5001 5002 enum { 5003 MLX5_QUERY_VPORT_STATE_OUT_STATE_DOWN = 0x0, 5004 MLX5_QUERY_VPORT_STATE_OUT_STATE_UP = 0x1, 5005 }; 5006 5007 struct mlx5_ifc_query_vport_state_out_bits { 5008 u8 status[0x8]; 5009 u8 reserved_at_8[0x18]; 5010 5011 u8 syndrome[0x20]; 5012 5013 u8 reserved_at_40[0x20]; 5014 5015 u8 reserved_at_60[0x18]; 5016 u8 admin_state[0x4]; 5017 u8 state[0x4]; 5018 }; 5019 5020 enum { 5021 MLX5_VPORT_STATE_OP_MOD_VNIC_VPORT = 0x0, 5022 MLX5_VPORT_STATE_OP_MOD_ESW_VPORT = 0x1, 5023 MLX5_VPORT_STATE_OP_MOD_UPLINK = 0x2, 5024 }; 5025 5026 struct mlx5_ifc_arm_monitor_counter_in_bits { 5027 u8 opcode[0x10]; 5028 u8 uid[0x10]; 5029 5030 u8 reserved_at_20[0x10]; 5031 u8 op_mod[0x10]; 5032 5033 u8 reserved_at_40[0x20]; 5034 5035 u8 reserved_at_60[0x20]; 5036 }; 5037 5038 struct mlx5_ifc_arm_monitor_counter_out_bits { 5039 u8 status[0x8]; 5040 u8 reserved_at_8[0x18]; 5041 5042 u8 syndrome[0x20]; 5043 5044 u8 reserved_at_40[0x40]; 5045 }; 5046 5047 enum { 5048 MLX5_QUERY_MONITOR_CNT_TYPE_PPCNT = 0x0, 5049 MLX5_QUERY_MONITOR_CNT_TYPE_Q_COUNTER = 0x1, 5050 }; 5051 5052 enum mlx5_monitor_counter_ppcnt { 5053 MLX5_QUERY_MONITOR_PPCNT_IN_RANGE_LENGTH_ERRORS = 0x0, 5054 MLX5_QUERY_MONITOR_PPCNT_OUT_OF_RANGE_LENGTH_FIELD = 0x1, 5055 MLX5_QUERY_MONITOR_PPCNT_FRAME_TOO_LONG_ERRORS = 0x2, 5056 MLX5_QUERY_MONITOR_PPCNT_FRAME_CHECK_SEQUENCE_ERRORS = 0x3, 5057 MLX5_QUERY_MONITOR_PPCNT_ALIGNMENT_ERRORS = 0x4, 5058 MLX5_QUERY_MONITOR_PPCNT_IF_OUT_DISCARDS = 0x5, 5059 }; 5060 5061 enum { 5062 MLX5_QUERY_MONITOR_Q_COUNTER_RX_OUT_OF_BUFFER = 0x4, 5063 }; 5064 5065 struct mlx5_ifc_monitor_counter_output_bits { 5066 u8 reserved_at_0[0x4]; 5067 u8 type[0x4]; 5068 u8 reserved_at_8[0x8]; 5069 u8 counter[0x10]; 5070 5071 u8 counter_group_id[0x20]; 5072 }; 5073 5074 #define MLX5_CMD_SET_MONITOR_NUM_PPCNT_COUNTER_SET1 (6) 5075 #define MLX5_CMD_SET_MONITOR_NUM_Q_COUNTERS_SET1 (1) 5076 #define MLX5_CMD_SET_MONITOR_NUM_COUNTER (MLX5_CMD_SET_MONITOR_NUM_PPCNT_COUNTER_SET1 +\ 5077 MLX5_CMD_SET_MONITOR_NUM_Q_COUNTERS_SET1) 5078 5079 struct mlx5_ifc_set_monitor_counter_in_bits { 5080 u8 opcode[0x10]; 5081 u8 uid[0x10]; 5082 5083 u8 reserved_at_20[0x10]; 5084 u8 op_mod[0x10]; 5085 5086 u8 reserved_at_40[0x10]; 5087 u8 num_of_counters[0x10]; 5088 5089 u8 reserved_at_60[0x20]; 5090 5091 struct mlx5_ifc_monitor_counter_output_bits monitor_counter[MLX5_CMD_SET_MONITOR_NUM_COUNTER]; 5092 }; 5093 5094 struct mlx5_ifc_set_monitor_counter_out_bits { 5095 u8 status[0x8]; 5096 u8 reserved_at_8[0x18]; 5097 5098 u8 syndrome[0x20]; 5099 5100 u8 reserved_at_40[0x40]; 5101 }; 5102 5103 struct mlx5_ifc_query_vport_state_in_bits { 5104 u8 opcode[0x10]; 5105 u8 reserved_at_10[0x10]; 5106 5107 u8 reserved_at_20[0x10]; 5108 u8 op_mod[0x10]; 5109 5110 u8 other_vport[0x1]; 5111 u8 reserved_at_41[0xf]; 5112 u8 vport_number[0x10]; 5113 5114 u8 reserved_at_60[0x20]; 5115 }; 5116 5117 struct mlx5_ifc_query_vnic_env_out_bits { 5118 u8 status[0x8]; 5119 u8 reserved_at_8[0x18]; 5120 5121 u8 syndrome[0x20]; 5122 5123 u8 reserved_at_40[0x40]; 5124 5125 struct mlx5_ifc_vnic_diagnostic_statistics_bits vport_env; 5126 }; 5127 5128 enum { 5129 MLX5_QUERY_VNIC_ENV_IN_OP_MOD_VPORT_DIAG_STATISTICS = 0x0, 5130 }; 5131 5132 struct mlx5_ifc_query_vnic_env_in_bits { 5133 u8 opcode[0x10]; 5134 u8 reserved_at_10[0x10]; 5135 5136 u8 reserved_at_20[0x10]; 5137 u8 op_mod[0x10]; 5138 5139 u8 other_vport[0x1]; 5140 u8 reserved_at_41[0xf]; 5141 u8 vport_number[0x10]; 5142 5143 u8 reserved_at_60[0x20]; 5144 }; 5145 5146 struct mlx5_ifc_query_vport_counter_out_bits { 5147 u8 status[0x8]; 5148 u8 reserved_at_8[0x18]; 5149 5150 u8 syndrome[0x20]; 5151 5152 u8 reserved_at_40[0x40]; 5153 5154 struct mlx5_ifc_traffic_counter_bits received_errors; 5155 5156 struct mlx5_ifc_traffic_counter_bits transmit_errors; 5157 5158 struct mlx5_ifc_traffic_counter_bits received_ib_unicast; 5159 5160 struct mlx5_ifc_traffic_counter_bits transmitted_ib_unicast; 5161 5162 struct mlx5_ifc_traffic_counter_bits received_ib_multicast; 5163 5164 struct mlx5_ifc_traffic_counter_bits transmitted_ib_multicast; 5165 5166 struct mlx5_ifc_traffic_counter_bits received_eth_broadcast; 5167 5168 struct mlx5_ifc_traffic_counter_bits transmitted_eth_broadcast; 5169 5170 struct mlx5_ifc_traffic_counter_bits received_eth_unicast; 5171 5172 struct mlx5_ifc_traffic_counter_bits transmitted_eth_unicast; 5173 5174 struct mlx5_ifc_traffic_counter_bits received_eth_multicast; 5175 5176 struct mlx5_ifc_traffic_counter_bits transmitted_eth_multicast; 5177 5178 u8 reserved_at_680[0xa00]; 5179 }; 5180 5181 enum { 5182 MLX5_QUERY_VPORT_COUNTER_IN_OP_MOD_VPORT_COUNTERS = 0x0, 5183 }; 5184 5185 struct mlx5_ifc_query_vport_counter_in_bits { 5186 u8 opcode[0x10]; 5187 u8 reserved_at_10[0x10]; 5188 5189 u8 reserved_at_20[0x10]; 5190 u8 op_mod[0x10]; 5191 5192 u8 other_vport[0x1]; 5193 u8 reserved_at_41[0xb]; 5194 u8 port_num[0x4]; 5195 u8 vport_number[0x10]; 5196 5197 u8 reserved_at_60[0x60]; 5198 5199 u8 clear[0x1]; 5200 u8 reserved_at_c1[0x1f]; 5201 5202 u8 reserved_at_e0[0x20]; 5203 }; 5204 5205 struct mlx5_ifc_query_tis_out_bits { 5206 u8 status[0x8]; 5207 u8 reserved_at_8[0x18]; 5208 5209 u8 syndrome[0x20]; 5210 5211 u8 reserved_at_40[0x40]; 5212 5213 struct mlx5_ifc_tisc_bits tis_context; 5214 }; 5215 5216 struct mlx5_ifc_query_tis_in_bits { 5217 u8 opcode[0x10]; 5218 u8 reserved_at_10[0x10]; 5219 5220 u8 reserved_at_20[0x10]; 5221 u8 op_mod[0x10]; 5222 5223 u8 reserved_at_40[0x8]; 5224 u8 tisn[0x18]; 5225 5226 u8 reserved_at_60[0x20]; 5227 }; 5228 5229 struct mlx5_ifc_query_tir_out_bits { 5230 u8 status[0x8]; 5231 u8 reserved_at_8[0x18]; 5232 5233 u8 syndrome[0x20]; 5234 5235 u8 reserved_at_40[0xc0]; 5236 5237 struct mlx5_ifc_tirc_bits tir_context; 5238 }; 5239 5240 struct mlx5_ifc_query_tir_in_bits { 5241 u8 opcode[0x10]; 5242 u8 reserved_at_10[0x10]; 5243 5244 u8 reserved_at_20[0x10]; 5245 u8 op_mod[0x10]; 5246 5247 u8 reserved_at_40[0x8]; 5248 u8 tirn[0x18]; 5249 5250 u8 reserved_at_60[0x20]; 5251 }; 5252 5253 struct mlx5_ifc_query_srq_out_bits { 5254 u8 status[0x8]; 5255 u8 reserved_at_8[0x18]; 5256 5257 u8 syndrome[0x20]; 5258 5259 u8 reserved_at_40[0x40]; 5260 5261 struct mlx5_ifc_srqc_bits srq_context_entry; 5262 5263 u8 reserved_at_280[0x600]; 5264 5265 u8 pas[][0x40]; 5266 }; 5267 5268 struct mlx5_ifc_query_srq_in_bits { 5269 u8 opcode[0x10]; 5270 u8 reserved_at_10[0x10]; 5271 5272 u8 reserved_at_20[0x10]; 5273 u8 op_mod[0x10]; 5274 5275 u8 reserved_at_40[0x8]; 5276 u8 srqn[0x18]; 5277 5278 u8 reserved_at_60[0x20]; 5279 }; 5280 5281 struct mlx5_ifc_query_sq_out_bits { 5282 u8 status[0x8]; 5283 u8 reserved_at_8[0x18]; 5284 5285 u8 syndrome[0x20]; 5286 5287 u8 reserved_at_40[0xc0]; 5288 5289 struct mlx5_ifc_sqc_bits sq_context; 5290 }; 5291 5292 struct mlx5_ifc_query_sq_in_bits { 5293 u8 opcode[0x10]; 5294 u8 reserved_at_10[0x10]; 5295 5296 u8 reserved_at_20[0x10]; 5297 u8 op_mod[0x10]; 5298 5299 u8 reserved_at_40[0x8]; 5300 u8 sqn[0x18]; 5301 5302 u8 reserved_at_60[0x20]; 5303 }; 5304 5305 struct mlx5_ifc_query_special_contexts_out_bits { 5306 u8 status[0x8]; 5307 u8 reserved_at_8[0x18]; 5308 5309 u8 syndrome[0x20]; 5310 5311 u8 dump_fill_mkey[0x20]; 5312 5313 u8 resd_lkey[0x20]; 5314 5315 u8 null_mkey[0x20]; 5316 5317 u8 terminate_scatter_list_mkey[0x20]; 5318 5319 u8 repeated_mkey[0x20]; 5320 5321 u8 reserved_at_a0[0x20]; 5322 }; 5323 5324 struct mlx5_ifc_query_special_contexts_in_bits { 5325 u8 opcode[0x10]; 5326 u8 reserved_at_10[0x10]; 5327 5328 u8 reserved_at_20[0x10]; 5329 u8 op_mod[0x10]; 5330 5331 u8 reserved_at_40[0x40]; 5332 }; 5333 5334 struct mlx5_ifc_query_scheduling_element_out_bits { 5335 u8 opcode[0x10]; 5336 u8 reserved_at_10[0x10]; 5337 5338 u8 reserved_at_20[0x10]; 5339 u8 op_mod[0x10]; 5340 5341 u8 reserved_at_40[0xc0]; 5342 5343 struct mlx5_ifc_scheduling_context_bits scheduling_context; 5344 5345 u8 reserved_at_300[0x100]; 5346 }; 5347 5348 enum { 5349 SCHEDULING_HIERARCHY_E_SWITCH = 0x2, 5350 SCHEDULING_HIERARCHY_NIC = 0x3, 5351 }; 5352 5353 struct mlx5_ifc_query_scheduling_element_in_bits { 5354 u8 opcode[0x10]; 5355 u8 reserved_at_10[0x10]; 5356 5357 u8 reserved_at_20[0x10]; 5358 u8 op_mod[0x10]; 5359 5360 u8 scheduling_hierarchy[0x8]; 5361 u8 reserved_at_48[0x18]; 5362 5363 u8 scheduling_element_id[0x20]; 5364 5365 u8 reserved_at_80[0x180]; 5366 }; 5367 5368 struct mlx5_ifc_query_rqt_out_bits { 5369 u8 status[0x8]; 5370 u8 reserved_at_8[0x18]; 5371 5372 u8 syndrome[0x20]; 5373 5374 u8 reserved_at_40[0xc0]; 5375 5376 struct mlx5_ifc_rqtc_bits rqt_context; 5377 }; 5378 5379 struct mlx5_ifc_query_rqt_in_bits { 5380 u8 opcode[0x10]; 5381 u8 reserved_at_10[0x10]; 5382 5383 u8 reserved_at_20[0x10]; 5384 u8 op_mod[0x10]; 5385 5386 u8 reserved_at_40[0x8]; 5387 u8 rqtn[0x18]; 5388 5389 u8 reserved_at_60[0x20]; 5390 }; 5391 5392 struct mlx5_ifc_query_rq_out_bits { 5393 u8 status[0x8]; 5394 u8 reserved_at_8[0x18]; 5395 5396 u8 syndrome[0x20]; 5397 5398 u8 reserved_at_40[0xc0]; 5399 5400 struct mlx5_ifc_rqc_bits rq_context; 5401 }; 5402 5403 struct mlx5_ifc_query_rq_in_bits { 5404 u8 opcode[0x10]; 5405 u8 reserved_at_10[0x10]; 5406 5407 u8 reserved_at_20[0x10]; 5408 u8 op_mod[0x10]; 5409 5410 u8 reserved_at_40[0x8]; 5411 u8 rqn[0x18]; 5412 5413 u8 reserved_at_60[0x20]; 5414 }; 5415 5416 struct mlx5_ifc_query_roce_address_out_bits { 5417 u8 status[0x8]; 5418 u8 reserved_at_8[0x18]; 5419 5420 u8 syndrome[0x20]; 5421 5422 u8 reserved_at_40[0x40]; 5423 5424 struct mlx5_ifc_roce_addr_layout_bits roce_address; 5425 }; 5426 5427 struct mlx5_ifc_query_roce_address_in_bits { 5428 u8 opcode[0x10]; 5429 u8 reserved_at_10[0x10]; 5430 5431 u8 reserved_at_20[0x10]; 5432 u8 op_mod[0x10]; 5433 5434 u8 roce_address_index[0x10]; 5435 u8 reserved_at_50[0xc]; 5436 u8 vhca_port_num[0x4]; 5437 5438 u8 reserved_at_60[0x20]; 5439 }; 5440 5441 struct mlx5_ifc_query_rmp_out_bits { 5442 u8 status[0x8]; 5443 u8 reserved_at_8[0x18]; 5444 5445 u8 syndrome[0x20]; 5446 5447 u8 reserved_at_40[0xc0]; 5448 5449 struct mlx5_ifc_rmpc_bits rmp_context; 5450 }; 5451 5452 struct mlx5_ifc_query_rmp_in_bits { 5453 u8 opcode[0x10]; 5454 u8 reserved_at_10[0x10]; 5455 5456 u8 reserved_at_20[0x10]; 5457 u8 op_mod[0x10]; 5458 5459 u8 reserved_at_40[0x8]; 5460 u8 rmpn[0x18]; 5461 5462 u8 reserved_at_60[0x20]; 5463 }; 5464 5465 struct mlx5_ifc_cqe_error_syndrome_bits { 5466 u8 hw_error_syndrome[0x8]; 5467 u8 hw_syndrome_type[0x4]; 5468 u8 reserved_at_c[0x4]; 5469 u8 vendor_error_syndrome[0x8]; 5470 u8 syndrome[0x8]; 5471 }; 5472 5473 struct mlx5_ifc_qp_context_extension_bits { 5474 u8 reserved_at_0[0x60]; 5475 5476 struct mlx5_ifc_cqe_error_syndrome_bits error_syndrome; 5477 5478 u8 reserved_at_80[0x580]; 5479 }; 5480 5481 struct mlx5_ifc_qpc_extension_and_pas_list_in_bits { 5482 struct mlx5_ifc_qp_context_extension_bits qpc_data_extension; 5483 5484 u8 pas[0][0x40]; 5485 }; 5486 5487 struct mlx5_ifc_qp_pas_list_in_bits { 5488 struct mlx5_ifc_cmd_pas_bits pas[0]; 5489 }; 5490 5491 union mlx5_ifc_qp_pas_or_qpc_ext_and_pas_bits { 5492 struct mlx5_ifc_qp_pas_list_in_bits qp_pas_list; 5493 struct mlx5_ifc_qpc_extension_and_pas_list_in_bits qpc_ext_and_pas_list; 5494 }; 5495 5496 struct mlx5_ifc_query_qp_out_bits { 5497 u8 status[0x8]; 5498 u8 reserved_at_8[0x18]; 5499 5500 u8 syndrome[0x20]; 5501 5502 u8 reserved_at_40[0x40]; 5503 5504 u8 opt_param_mask[0x20]; 5505 5506 u8 ece[0x20]; 5507 5508 struct mlx5_ifc_qpc_bits qpc; 5509 5510 u8 reserved_at_800[0x80]; 5511 5512 union mlx5_ifc_qp_pas_or_qpc_ext_and_pas_bits qp_pas_or_qpc_ext_and_pas; 5513 }; 5514 5515 struct mlx5_ifc_query_qp_in_bits { 5516 u8 opcode[0x10]; 5517 u8 reserved_at_10[0x10]; 5518 5519 u8 reserved_at_20[0x10]; 5520 u8 op_mod[0x10]; 5521 5522 u8 qpc_ext[0x1]; 5523 u8 reserved_at_41[0x7]; 5524 u8 qpn[0x18]; 5525 5526 u8 reserved_at_60[0x20]; 5527 }; 5528 5529 struct mlx5_ifc_query_q_counter_out_bits { 5530 u8 status[0x8]; 5531 u8 reserved_at_8[0x18]; 5532 5533 u8 syndrome[0x20]; 5534 5535 u8 reserved_at_40[0x40]; 5536 5537 u8 rx_write_requests[0x20]; 5538 5539 u8 reserved_at_a0[0x20]; 5540 5541 u8 rx_read_requests[0x20]; 5542 5543 u8 reserved_at_e0[0x20]; 5544 5545 u8 rx_atomic_requests[0x20]; 5546 5547 u8 reserved_at_120[0x20]; 5548 5549 u8 rx_dct_connect[0x20]; 5550 5551 u8 reserved_at_160[0x20]; 5552 5553 u8 out_of_buffer[0x20]; 5554 5555 u8 reserved_at_1a0[0x20]; 5556 5557 u8 out_of_sequence[0x20]; 5558 5559 u8 reserved_at_1e0[0x20]; 5560 5561 u8 duplicate_request[0x20]; 5562 5563 u8 reserved_at_220[0x20]; 5564 5565 u8 rnr_nak_retry_err[0x20]; 5566 5567 u8 reserved_at_260[0x20]; 5568 5569 u8 packet_seq_err[0x20]; 5570 5571 u8 reserved_at_2a0[0x20]; 5572 5573 u8 implied_nak_seq_err[0x20]; 5574 5575 u8 reserved_at_2e0[0x20]; 5576 5577 u8 local_ack_timeout_err[0x20]; 5578 5579 u8 reserved_at_320[0xa0]; 5580 5581 u8 resp_local_length_error[0x20]; 5582 5583 u8 req_local_length_error[0x20]; 5584 5585 u8 resp_local_qp_error[0x20]; 5586 5587 u8 local_operation_error[0x20]; 5588 5589 u8 resp_local_protection[0x20]; 5590 5591 u8 req_local_protection[0x20]; 5592 5593 u8 resp_cqe_error[0x20]; 5594 5595 u8 req_cqe_error[0x20]; 5596 5597 u8 req_mw_binding[0x20]; 5598 5599 u8 req_bad_response[0x20]; 5600 5601 u8 req_remote_invalid_request[0x20]; 5602 5603 u8 resp_remote_invalid_request[0x20]; 5604 5605 u8 req_remote_access_errors[0x20]; 5606 5607 u8 resp_remote_access_errors[0x20]; 5608 5609 u8 req_remote_operation_errors[0x20]; 5610 5611 u8 req_transport_retries_exceeded[0x20]; 5612 5613 u8 cq_overflow[0x20]; 5614 5615 u8 resp_cqe_flush_error[0x20]; 5616 5617 u8 req_cqe_flush_error[0x20]; 5618 5619 u8 reserved_at_620[0x20]; 5620 5621 u8 roce_adp_retrans[0x20]; 5622 5623 u8 roce_adp_retrans_to[0x20]; 5624 5625 u8 roce_slow_restart[0x20]; 5626 5627 u8 roce_slow_restart_cnps[0x20]; 5628 5629 u8 roce_slow_restart_trans[0x20]; 5630 5631 u8 reserved_at_6e0[0x120]; 5632 }; 5633 5634 struct mlx5_ifc_query_q_counter_in_bits { 5635 u8 opcode[0x10]; 5636 u8 reserved_at_10[0x10]; 5637 5638 u8 reserved_at_20[0x10]; 5639 u8 op_mod[0x10]; 5640 5641 u8 other_vport[0x1]; 5642 u8 reserved_at_41[0xf]; 5643 u8 vport_number[0x10]; 5644 5645 u8 reserved_at_60[0x60]; 5646 5647 u8 clear[0x1]; 5648 u8 aggregate[0x1]; 5649 u8 reserved_at_c2[0x1e]; 5650 5651 u8 reserved_at_e0[0x18]; 5652 u8 counter_set_id[0x8]; 5653 }; 5654 5655 struct mlx5_ifc_query_pages_out_bits { 5656 u8 status[0x8]; 5657 u8 reserved_at_8[0x18]; 5658 5659 u8 syndrome[0x20]; 5660 5661 u8 embedded_cpu_function[0x1]; 5662 u8 reserved_at_41[0xf]; 5663 u8 function_id[0x10]; 5664 5665 u8 num_pages[0x20]; 5666 }; 5667 5668 enum { 5669 MLX5_QUERY_PAGES_IN_OP_MOD_BOOT_PAGES = 0x1, 5670 MLX5_QUERY_PAGES_IN_OP_MOD_INIT_PAGES = 0x2, 5671 MLX5_QUERY_PAGES_IN_OP_MOD_REGULAR_PAGES = 0x3, 5672 }; 5673 5674 struct mlx5_ifc_query_pages_in_bits { 5675 u8 opcode[0x10]; 5676 u8 reserved_at_10[0x10]; 5677 5678 u8 reserved_at_20[0x10]; 5679 u8 op_mod[0x10]; 5680 5681 u8 embedded_cpu_function[0x1]; 5682 u8 reserved_at_41[0xf]; 5683 u8 function_id[0x10]; 5684 5685 u8 reserved_at_60[0x20]; 5686 }; 5687 5688 struct mlx5_ifc_query_nic_vport_context_out_bits { 5689 u8 status[0x8]; 5690 u8 reserved_at_8[0x18]; 5691 5692 u8 syndrome[0x20]; 5693 5694 u8 reserved_at_40[0x40]; 5695 5696 struct mlx5_ifc_nic_vport_context_bits nic_vport_context; 5697 }; 5698 5699 struct mlx5_ifc_query_nic_vport_context_in_bits { 5700 u8 opcode[0x10]; 5701 u8 reserved_at_10[0x10]; 5702 5703 u8 reserved_at_20[0x10]; 5704 u8 op_mod[0x10]; 5705 5706 u8 other_vport[0x1]; 5707 u8 reserved_at_41[0xf]; 5708 u8 vport_number[0x10]; 5709 5710 u8 reserved_at_60[0x5]; 5711 u8 allowed_list_type[0x3]; 5712 u8 reserved_at_68[0x18]; 5713 }; 5714 5715 struct mlx5_ifc_query_mkey_out_bits { 5716 u8 status[0x8]; 5717 u8 reserved_at_8[0x18]; 5718 5719 u8 syndrome[0x20]; 5720 5721 u8 reserved_at_40[0x40]; 5722 5723 struct mlx5_ifc_mkc_bits memory_key_mkey_entry; 5724 5725 u8 reserved_at_280[0x600]; 5726 5727 u8 bsf0_klm0_pas_mtt0_1[16][0x8]; 5728 5729 u8 bsf1_klm1_pas_mtt2_3[16][0x8]; 5730 }; 5731 5732 struct mlx5_ifc_query_mkey_in_bits { 5733 u8 opcode[0x10]; 5734 u8 reserved_at_10[0x10]; 5735 5736 u8 reserved_at_20[0x10]; 5737 u8 op_mod[0x10]; 5738 5739 u8 reserved_at_40[0x8]; 5740 u8 mkey_index[0x18]; 5741 5742 u8 pg_access[0x1]; 5743 u8 reserved_at_61[0x1f]; 5744 }; 5745 5746 struct mlx5_ifc_query_mad_demux_out_bits { 5747 u8 status[0x8]; 5748 u8 reserved_at_8[0x18]; 5749 5750 u8 syndrome[0x20]; 5751 5752 u8 reserved_at_40[0x40]; 5753 5754 u8 mad_dumux_parameters_block[0x20]; 5755 }; 5756 5757 struct mlx5_ifc_query_mad_demux_in_bits { 5758 u8 opcode[0x10]; 5759 u8 reserved_at_10[0x10]; 5760 5761 u8 reserved_at_20[0x10]; 5762 u8 op_mod[0x10]; 5763 5764 u8 reserved_at_40[0x40]; 5765 }; 5766 5767 struct mlx5_ifc_query_l2_table_entry_out_bits { 5768 u8 status[0x8]; 5769 u8 reserved_at_8[0x18]; 5770 5771 u8 syndrome[0x20]; 5772 5773 u8 reserved_at_40[0xa0]; 5774 5775 u8 reserved_at_e0[0x13]; 5776 u8 vlan_valid[0x1]; 5777 u8 vlan[0xc]; 5778 5779 struct mlx5_ifc_mac_address_layout_bits mac_address; 5780 5781 u8 reserved_at_140[0xc0]; 5782 }; 5783 5784 struct mlx5_ifc_query_l2_table_entry_in_bits { 5785 u8 opcode[0x10]; 5786 u8 reserved_at_10[0x10]; 5787 5788 u8 reserved_at_20[0x10]; 5789 u8 op_mod[0x10]; 5790 5791 u8 reserved_at_40[0x60]; 5792 5793 u8 reserved_at_a0[0x8]; 5794 u8 table_index[0x18]; 5795 5796 u8 reserved_at_c0[0x140]; 5797 }; 5798 5799 struct mlx5_ifc_query_issi_out_bits { 5800 u8 status[0x8]; 5801 u8 reserved_at_8[0x18]; 5802 5803 u8 syndrome[0x20]; 5804 5805 u8 reserved_at_40[0x10]; 5806 u8 current_issi[0x10]; 5807 5808 u8 reserved_at_60[0xa0]; 5809 5810 u8 reserved_at_100[76][0x8]; 5811 u8 supported_issi_dw0[0x20]; 5812 }; 5813 5814 struct mlx5_ifc_query_issi_in_bits { 5815 u8 opcode[0x10]; 5816 u8 reserved_at_10[0x10]; 5817 5818 u8 reserved_at_20[0x10]; 5819 u8 op_mod[0x10]; 5820 5821 u8 reserved_at_40[0x40]; 5822 }; 5823 5824 struct mlx5_ifc_set_driver_version_out_bits { 5825 u8 status[0x8]; 5826 u8 reserved_0[0x18]; 5827 5828 u8 syndrome[0x20]; 5829 u8 reserved_1[0x40]; 5830 }; 5831 5832 struct mlx5_ifc_set_driver_version_in_bits { 5833 u8 opcode[0x10]; 5834 u8 reserved_0[0x10]; 5835 5836 u8 reserved_1[0x10]; 5837 u8 op_mod[0x10]; 5838 5839 u8 reserved_2[0x40]; 5840 u8 driver_version[64][0x8]; 5841 }; 5842 5843 struct mlx5_ifc_query_hca_vport_pkey_out_bits { 5844 u8 status[0x8]; 5845 u8 reserved_at_8[0x18]; 5846 5847 u8 syndrome[0x20]; 5848 5849 u8 reserved_at_40[0x40]; 5850 5851 struct mlx5_ifc_pkey_bits pkey[]; 5852 }; 5853 5854 struct mlx5_ifc_query_hca_vport_pkey_in_bits { 5855 u8 opcode[0x10]; 5856 u8 reserved_at_10[0x10]; 5857 5858 u8 reserved_at_20[0x10]; 5859 u8 op_mod[0x10]; 5860 5861 u8 other_vport[0x1]; 5862 u8 reserved_at_41[0xb]; 5863 u8 port_num[0x4]; 5864 u8 vport_number[0x10]; 5865 5866 u8 reserved_at_60[0x10]; 5867 u8 pkey_index[0x10]; 5868 }; 5869 5870 enum { 5871 MLX5_HCA_VPORT_SEL_PORT_GUID = 1 << 0, 5872 MLX5_HCA_VPORT_SEL_NODE_GUID = 1 << 1, 5873 MLX5_HCA_VPORT_SEL_STATE_POLICY = 1 << 2, 5874 }; 5875 5876 struct mlx5_ifc_query_hca_vport_gid_out_bits { 5877 u8 status[0x8]; 5878 u8 reserved_at_8[0x18]; 5879 5880 u8 syndrome[0x20]; 5881 5882 u8 reserved_at_40[0x20]; 5883 5884 u8 gids_num[0x10]; 5885 u8 reserved_at_70[0x10]; 5886 5887 struct mlx5_ifc_array128_auto_bits gid[]; 5888 }; 5889 5890 struct mlx5_ifc_query_hca_vport_gid_in_bits { 5891 u8 opcode[0x10]; 5892 u8 reserved_at_10[0x10]; 5893 5894 u8 reserved_at_20[0x10]; 5895 u8 op_mod[0x10]; 5896 5897 u8 other_vport[0x1]; 5898 u8 reserved_at_41[0xb]; 5899 u8 port_num[0x4]; 5900 u8 vport_number[0x10]; 5901 5902 u8 reserved_at_60[0x10]; 5903 u8 gid_index[0x10]; 5904 }; 5905 5906 struct mlx5_ifc_query_hca_vport_context_out_bits { 5907 u8 status[0x8]; 5908 u8 reserved_at_8[0x18]; 5909 5910 u8 syndrome[0x20]; 5911 5912 u8 reserved_at_40[0x40]; 5913 5914 struct mlx5_ifc_hca_vport_context_bits hca_vport_context; 5915 }; 5916 5917 struct mlx5_ifc_query_hca_vport_context_in_bits { 5918 u8 opcode[0x10]; 5919 u8 reserved_at_10[0x10]; 5920 5921 u8 reserved_at_20[0x10]; 5922 u8 op_mod[0x10]; 5923 5924 u8 other_vport[0x1]; 5925 u8 reserved_at_41[0xb]; 5926 u8 port_num[0x4]; 5927 u8 vport_number[0x10]; 5928 5929 u8 reserved_at_60[0x20]; 5930 }; 5931 5932 struct mlx5_ifc_query_hca_cap_out_bits { 5933 u8 status[0x8]; 5934 u8 reserved_at_8[0x18]; 5935 5936 u8 syndrome[0x20]; 5937 5938 u8 reserved_at_40[0x40]; 5939 5940 union mlx5_ifc_hca_cap_union_bits capability; 5941 }; 5942 5943 struct mlx5_ifc_query_hca_cap_in_bits { 5944 u8 opcode[0x10]; 5945 u8 reserved_at_10[0x10]; 5946 5947 u8 reserved_at_20[0x10]; 5948 u8 op_mod[0x10]; 5949 5950 u8 other_function[0x1]; 5951 u8 reserved_at_41[0xf]; 5952 u8 function_id[0x10]; 5953 5954 u8 reserved_at_60[0x20]; 5955 }; 5956 5957 struct mlx5_ifc_other_hca_cap_bits { 5958 u8 roce[0x1]; 5959 u8 reserved_at_1[0x27f]; 5960 }; 5961 5962 struct mlx5_ifc_query_other_hca_cap_out_bits { 5963 u8 status[0x8]; 5964 u8 reserved_at_8[0x18]; 5965 5966 u8 syndrome[0x20]; 5967 5968 u8 reserved_at_40[0x40]; 5969 5970 struct mlx5_ifc_other_hca_cap_bits other_capability; 5971 }; 5972 5973 struct mlx5_ifc_query_other_hca_cap_in_bits { 5974 u8 opcode[0x10]; 5975 u8 reserved_at_10[0x10]; 5976 5977 u8 reserved_at_20[0x10]; 5978 u8 op_mod[0x10]; 5979 5980 u8 reserved_at_40[0x10]; 5981 u8 function_id[0x10]; 5982 5983 u8 reserved_at_60[0x20]; 5984 }; 5985 5986 struct mlx5_ifc_modify_other_hca_cap_out_bits { 5987 u8 status[0x8]; 5988 u8 reserved_at_8[0x18]; 5989 5990 u8 syndrome[0x20]; 5991 5992 u8 reserved_at_40[0x40]; 5993 }; 5994 5995 struct mlx5_ifc_modify_other_hca_cap_in_bits { 5996 u8 opcode[0x10]; 5997 u8 reserved_at_10[0x10]; 5998 5999 u8 reserved_at_20[0x10]; 6000 u8 op_mod[0x10]; 6001 6002 u8 reserved_at_40[0x10]; 6003 u8 function_id[0x10]; 6004 u8 field_select[0x20]; 6005 6006 struct mlx5_ifc_other_hca_cap_bits other_capability; 6007 }; 6008 6009 struct mlx5_ifc_flow_table_context_bits { 6010 u8 reformat_en[0x1]; 6011 u8 decap_en[0x1]; 6012 u8 sw_owner[0x1]; 6013 u8 termination_table[0x1]; 6014 u8 table_miss_action[0x4]; 6015 u8 level[0x8]; 6016 u8 reserved_at_10[0x8]; 6017 u8 log_size[0x8]; 6018 6019 u8 reserved_at_20[0x8]; 6020 u8 table_miss_id[0x18]; 6021 6022 u8 reserved_at_40[0x8]; 6023 u8 lag_master_next_table_id[0x18]; 6024 6025 u8 reserved_at_60[0x60]; 6026 6027 u8 sw_owner_icm_root_1[0x40]; 6028 6029 u8 sw_owner_icm_root_0[0x40]; 6030 6031 }; 6032 6033 struct mlx5_ifc_query_flow_table_out_bits { 6034 u8 status[0x8]; 6035 u8 reserved_at_8[0x18]; 6036 6037 u8 syndrome[0x20]; 6038 6039 u8 reserved_at_40[0x80]; 6040 6041 struct mlx5_ifc_flow_table_context_bits flow_table_context; 6042 }; 6043 6044 struct mlx5_ifc_query_flow_table_in_bits { 6045 u8 opcode[0x10]; 6046 u8 reserved_at_10[0x10]; 6047 6048 u8 reserved_at_20[0x10]; 6049 u8 op_mod[0x10]; 6050 6051 u8 reserved_at_40[0x40]; 6052 6053 u8 table_type[0x8]; 6054 u8 reserved_at_88[0x18]; 6055 6056 u8 reserved_at_a0[0x8]; 6057 u8 table_id[0x18]; 6058 6059 u8 reserved_at_c0[0x140]; 6060 }; 6061 6062 struct mlx5_ifc_query_fte_out_bits { 6063 u8 status[0x8]; 6064 u8 reserved_at_8[0x18]; 6065 6066 u8 syndrome[0x20]; 6067 6068 u8 reserved_at_40[0x1c0]; 6069 6070 struct mlx5_ifc_flow_context_bits flow_context; 6071 }; 6072 6073 struct mlx5_ifc_query_fte_in_bits { 6074 u8 opcode[0x10]; 6075 u8 reserved_at_10[0x10]; 6076 6077 u8 reserved_at_20[0x10]; 6078 u8 op_mod[0x10]; 6079 6080 u8 reserved_at_40[0x40]; 6081 6082 u8 table_type[0x8]; 6083 u8 reserved_at_88[0x18]; 6084 6085 u8 reserved_at_a0[0x8]; 6086 u8 table_id[0x18]; 6087 6088 u8 reserved_at_c0[0x40]; 6089 6090 u8 flow_index[0x20]; 6091 6092 u8 reserved_at_120[0xe0]; 6093 }; 6094 6095 struct mlx5_ifc_match_definer_format_0_bits { 6096 u8 reserved_at_0[0x100]; 6097 6098 u8 metadata_reg_c_0[0x20]; 6099 6100 u8 metadata_reg_c_1[0x20]; 6101 6102 u8 outer_dmac_47_16[0x20]; 6103 6104 u8 outer_dmac_15_0[0x10]; 6105 u8 outer_ethertype[0x10]; 6106 6107 u8 reserved_at_180[0x1]; 6108 u8 sx_sniffer[0x1]; 6109 u8 functional_lb[0x1]; 6110 u8 outer_ip_frag[0x1]; 6111 u8 outer_qp_type[0x2]; 6112 u8 outer_encap_type[0x2]; 6113 u8 port_number[0x2]; 6114 u8 outer_l3_type[0x2]; 6115 u8 outer_l4_type[0x2]; 6116 u8 outer_first_vlan_type[0x2]; 6117 u8 outer_first_vlan_prio[0x3]; 6118 u8 outer_first_vlan_cfi[0x1]; 6119 u8 outer_first_vlan_vid[0xc]; 6120 6121 u8 outer_l4_type_ext[0x4]; 6122 u8 reserved_at_1a4[0x2]; 6123 u8 outer_ipsec_layer[0x2]; 6124 u8 outer_l2_type[0x2]; 6125 u8 force_lb[0x1]; 6126 u8 outer_l2_ok[0x1]; 6127 u8 outer_l3_ok[0x1]; 6128 u8 outer_l4_ok[0x1]; 6129 u8 outer_second_vlan_type[0x2]; 6130 u8 outer_second_vlan_prio[0x3]; 6131 u8 outer_second_vlan_cfi[0x1]; 6132 u8 outer_second_vlan_vid[0xc]; 6133 6134 u8 outer_smac_47_16[0x20]; 6135 6136 u8 outer_smac_15_0[0x10]; 6137 u8 inner_ipv4_checksum_ok[0x1]; 6138 u8 inner_l4_checksum_ok[0x1]; 6139 u8 outer_ipv4_checksum_ok[0x1]; 6140 u8 outer_l4_checksum_ok[0x1]; 6141 u8 inner_l3_ok[0x1]; 6142 u8 inner_l4_ok[0x1]; 6143 u8 outer_l3_ok_duplicate[0x1]; 6144 u8 outer_l4_ok_duplicate[0x1]; 6145 u8 outer_tcp_cwr[0x1]; 6146 u8 outer_tcp_ece[0x1]; 6147 u8 outer_tcp_urg[0x1]; 6148 u8 outer_tcp_ack[0x1]; 6149 u8 outer_tcp_psh[0x1]; 6150 u8 outer_tcp_rst[0x1]; 6151 u8 outer_tcp_syn[0x1]; 6152 u8 outer_tcp_fin[0x1]; 6153 }; 6154 6155 struct mlx5_ifc_match_definer_format_22_bits { 6156 u8 reserved_at_0[0x100]; 6157 6158 u8 outer_ip_src_addr[0x20]; 6159 6160 u8 outer_ip_dest_addr[0x20]; 6161 6162 u8 outer_l4_sport[0x10]; 6163 u8 outer_l4_dport[0x10]; 6164 6165 u8 reserved_at_160[0x1]; 6166 u8 sx_sniffer[0x1]; 6167 u8 functional_lb[0x1]; 6168 u8 outer_ip_frag[0x1]; 6169 u8 outer_qp_type[0x2]; 6170 u8 outer_encap_type[0x2]; 6171 u8 port_number[0x2]; 6172 u8 outer_l3_type[0x2]; 6173 u8 outer_l4_type[0x2]; 6174 u8 outer_first_vlan_type[0x2]; 6175 u8 outer_first_vlan_prio[0x3]; 6176 u8 outer_first_vlan_cfi[0x1]; 6177 u8 outer_first_vlan_vid[0xc]; 6178 6179 u8 metadata_reg_c_0[0x20]; 6180 6181 u8 outer_dmac_47_16[0x20]; 6182 6183 u8 outer_smac_47_16[0x20]; 6184 6185 u8 outer_smac_15_0[0x10]; 6186 u8 outer_dmac_15_0[0x10]; 6187 }; 6188 6189 struct mlx5_ifc_match_definer_format_23_bits { 6190 u8 reserved_at_0[0x100]; 6191 6192 u8 inner_ip_src_addr[0x20]; 6193 6194 u8 inner_ip_dest_addr[0x20]; 6195 6196 u8 inner_l4_sport[0x10]; 6197 u8 inner_l4_dport[0x10]; 6198 6199 u8 reserved_at_160[0x1]; 6200 u8 sx_sniffer[0x1]; 6201 u8 functional_lb[0x1]; 6202 u8 inner_ip_frag[0x1]; 6203 u8 inner_qp_type[0x2]; 6204 u8 inner_encap_type[0x2]; 6205 u8 port_number[0x2]; 6206 u8 inner_l3_type[0x2]; 6207 u8 inner_l4_type[0x2]; 6208 u8 inner_first_vlan_type[0x2]; 6209 u8 inner_first_vlan_prio[0x3]; 6210 u8 inner_first_vlan_cfi[0x1]; 6211 u8 inner_first_vlan_vid[0xc]; 6212 6213 u8 tunnel_header_0[0x20]; 6214 6215 u8 inner_dmac_47_16[0x20]; 6216 6217 u8 inner_smac_47_16[0x20]; 6218 6219 u8 inner_smac_15_0[0x10]; 6220 u8 inner_dmac_15_0[0x10]; 6221 }; 6222 6223 struct mlx5_ifc_match_definer_format_29_bits { 6224 u8 reserved_at_0[0xc0]; 6225 6226 u8 outer_ip_dest_addr[0x80]; 6227 6228 u8 outer_ip_src_addr[0x80]; 6229 6230 u8 outer_l4_sport[0x10]; 6231 u8 outer_l4_dport[0x10]; 6232 6233 u8 reserved_at_1e0[0x20]; 6234 }; 6235 6236 struct mlx5_ifc_match_definer_format_30_bits { 6237 u8 reserved_at_0[0xa0]; 6238 6239 u8 outer_ip_dest_addr[0x80]; 6240 6241 u8 outer_ip_src_addr[0x80]; 6242 6243 u8 outer_dmac_47_16[0x20]; 6244 6245 u8 outer_smac_47_16[0x20]; 6246 6247 u8 outer_smac_15_0[0x10]; 6248 u8 outer_dmac_15_0[0x10]; 6249 }; 6250 6251 struct mlx5_ifc_match_definer_format_31_bits { 6252 u8 reserved_at_0[0xc0]; 6253 6254 u8 inner_ip_dest_addr[0x80]; 6255 6256 u8 inner_ip_src_addr[0x80]; 6257 6258 u8 inner_l4_sport[0x10]; 6259 u8 inner_l4_dport[0x10]; 6260 6261 u8 reserved_at_1e0[0x20]; 6262 }; 6263 6264 struct mlx5_ifc_match_definer_format_32_bits { 6265 u8 reserved_at_0[0xa0]; 6266 6267 u8 inner_ip_dest_addr[0x80]; 6268 6269 u8 inner_ip_src_addr[0x80]; 6270 6271 u8 inner_dmac_47_16[0x20]; 6272 6273 u8 inner_smac_47_16[0x20]; 6274 6275 u8 inner_smac_15_0[0x10]; 6276 u8 inner_dmac_15_0[0x10]; 6277 }; 6278 6279 enum { 6280 MLX5_IFC_DEFINER_FORMAT_ID_SELECT = 61, 6281 }; 6282 6283 #define MLX5_IFC_DEFINER_FORMAT_OFFSET_UNUSED 0x0 6284 #define MLX5_IFC_DEFINER_FORMAT_OFFSET_OUTER_ETH_PKT_LEN 0x48 6285 #define MLX5_IFC_DEFINER_DW_SELECTORS_NUM 9 6286 #define MLX5_IFC_DEFINER_BYTE_SELECTORS_NUM 8 6287 6288 struct mlx5_ifc_match_definer_match_mask_bits { 6289 u8 reserved_at_1c0[5][0x20]; 6290 u8 match_dw_8[0x20]; 6291 u8 match_dw_7[0x20]; 6292 u8 match_dw_6[0x20]; 6293 u8 match_dw_5[0x20]; 6294 u8 match_dw_4[0x20]; 6295 u8 match_dw_3[0x20]; 6296 u8 match_dw_2[0x20]; 6297 u8 match_dw_1[0x20]; 6298 u8 match_dw_0[0x20]; 6299 6300 u8 match_byte_7[0x8]; 6301 u8 match_byte_6[0x8]; 6302 u8 match_byte_5[0x8]; 6303 u8 match_byte_4[0x8]; 6304 6305 u8 match_byte_3[0x8]; 6306 u8 match_byte_2[0x8]; 6307 u8 match_byte_1[0x8]; 6308 u8 match_byte_0[0x8]; 6309 }; 6310 6311 struct mlx5_ifc_match_definer_bits { 6312 u8 modify_field_select[0x40]; 6313 6314 u8 reserved_at_40[0x40]; 6315 6316 u8 reserved_at_80[0x10]; 6317 u8 format_id[0x10]; 6318 6319 u8 reserved_at_a0[0x60]; 6320 6321 u8 format_select_dw3[0x8]; 6322 u8 format_select_dw2[0x8]; 6323 u8 format_select_dw1[0x8]; 6324 u8 format_select_dw0[0x8]; 6325 6326 u8 format_select_dw7[0x8]; 6327 u8 format_select_dw6[0x8]; 6328 u8 format_select_dw5[0x8]; 6329 u8 format_select_dw4[0x8]; 6330 6331 u8 reserved_at_100[0x18]; 6332 u8 format_select_dw8[0x8]; 6333 6334 u8 reserved_at_120[0x20]; 6335 6336 u8 format_select_byte3[0x8]; 6337 u8 format_select_byte2[0x8]; 6338 u8 format_select_byte1[0x8]; 6339 u8 format_select_byte0[0x8]; 6340 6341 u8 format_select_byte7[0x8]; 6342 u8 format_select_byte6[0x8]; 6343 u8 format_select_byte5[0x8]; 6344 u8 format_select_byte4[0x8]; 6345 6346 u8 reserved_at_180[0x40]; 6347 6348 union { 6349 struct { 6350 u8 match_mask[16][0x20]; 6351 }; 6352 struct mlx5_ifc_match_definer_match_mask_bits match_mask_format; 6353 }; 6354 }; 6355 6356 struct mlx5_ifc_general_obj_create_param_bits { 6357 u8 alias_object[0x1]; 6358 u8 reserved_at_1[0x2]; 6359 u8 log_obj_range[0x5]; 6360 u8 reserved_at_8[0x18]; 6361 }; 6362 6363 struct mlx5_ifc_general_obj_query_param_bits { 6364 u8 alias_object[0x1]; 6365 u8 obj_offset[0x1f]; 6366 }; 6367 6368 struct mlx5_ifc_general_obj_in_cmd_hdr_bits { 6369 u8 opcode[0x10]; 6370 u8 uid[0x10]; 6371 6372 u8 vhca_tunnel_id[0x10]; 6373 u8 obj_type[0x10]; 6374 6375 u8 obj_id[0x20]; 6376 6377 union { 6378 struct mlx5_ifc_general_obj_create_param_bits create; 6379 struct mlx5_ifc_general_obj_query_param_bits query; 6380 } op_param; 6381 }; 6382 6383 struct mlx5_ifc_general_obj_out_cmd_hdr_bits { 6384 u8 status[0x8]; 6385 u8 reserved_at_8[0x18]; 6386 6387 u8 syndrome[0x20]; 6388 6389 u8 obj_id[0x20]; 6390 6391 u8 reserved_at_60[0x20]; 6392 }; 6393 6394 struct mlx5_ifc_modify_header_arg_bits { 6395 u8 reserved_at_0[0x80]; 6396 6397 u8 reserved_at_80[0x8]; 6398 u8 access_pd[0x18]; 6399 }; 6400 6401 struct mlx5_ifc_create_modify_header_arg_in_bits { 6402 struct mlx5_ifc_general_obj_in_cmd_hdr_bits hdr; 6403 struct mlx5_ifc_modify_header_arg_bits arg; 6404 }; 6405 6406 struct mlx5_ifc_create_match_definer_in_bits { 6407 struct mlx5_ifc_general_obj_in_cmd_hdr_bits general_obj_in_cmd_hdr; 6408 6409 struct mlx5_ifc_match_definer_bits obj_context; 6410 }; 6411 6412 struct mlx5_ifc_create_match_definer_out_bits { 6413 struct mlx5_ifc_general_obj_out_cmd_hdr_bits general_obj_out_cmd_hdr; 6414 }; 6415 6416 enum { 6417 MLX5_QUERY_FLOW_GROUP_OUT_MATCH_CRITERIA_ENABLE_OUTER_HEADERS = 0x0, 6418 MLX5_QUERY_FLOW_GROUP_OUT_MATCH_CRITERIA_ENABLE_MISC_PARAMETERS = 0x1, 6419 MLX5_QUERY_FLOW_GROUP_OUT_MATCH_CRITERIA_ENABLE_INNER_HEADERS = 0x2, 6420 MLX5_QUERY_FLOW_GROUP_IN_MATCH_CRITERIA_ENABLE_MISC_PARAMETERS_2 = 0x3, 6421 MLX5_QUERY_FLOW_GROUP_IN_MATCH_CRITERIA_ENABLE_MISC_PARAMETERS_3 = 0x4, 6422 MLX5_QUERY_FLOW_GROUP_IN_MATCH_CRITERIA_ENABLE_MISC_PARAMETERS_4 = 0x5, 6423 MLX5_QUERY_FLOW_GROUP_IN_MATCH_CRITERIA_ENABLE_MISC_PARAMETERS_5 = 0x6, 6424 }; 6425 6426 struct mlx5_ifc_query_flow_group_out_bits { 6427 u8 status[0x8]; 6428 u8 reserved_at_8[0x18]; 6429 6430 u8 syndrome[0x20]; 6431 6432 u8 reserved_at_40[0xa0]; 6433 6434 u8 start_flow_index[0x20]; 6435 6436 u8 reserved_at_100[0x20]; 6437 6438 u8 end_flow_index[0x20]; 6439 6440 u8 reserved_at_140[0xa0]; 6441 6442 u8 reserved_at_1e0[0x18]; 6443 u8 match_criteria_enable[0x8]; 6444 6445 struct mlx5_ifc_fte_match_param_bits match_criteria; 6446 6447 u8 reserved_at_1200[0xe00]; 6448 }; 6449 6450 struct mlx5_ifc_query_flow_group_in_bits { 6451 u8 opcode[0x10]; 6452 u8 reserved_at_10[0x10]; 6453 6454 u8 reserved_at_20[0x10]; 6455 u8 op_mod[0x10]; 6456 6457 u8 reserved_at_40[0x40]; 6458 6459 u8 table_type[0x8]; 6460 u8 reserved_at_88[0x18]; 6461 6462 u8 reserved_at_a0[0x8]; 6463 u8 table_id[0x18]; 6464 6465 u8 group_id[0x20]; 6466 6467 u8 reserved_at_e0[0x120]; 6468 }; 6469 6470 struct mlx5_ifc_query_flow_counter_out_bits { 6471 u8 status[0x8]; 6472 u8 reserved_at_8[0x18]; 6473 6474 u8 syndrome[0x20]; 6475 6476 u8 reserved_at_40[0x40]; 6477 6478 struct mlx5_ifc_traffic_counter_bits flow_statistics[]; 6479 }; 6480 6481 struct mlx5_ifc_query_flow_counter_in_bits { 6482 u8 opcode[0x10]; 6483 u8 reserved_at_10[0x10]; 6484 6485 u8 reserved_at_20[0x10]; 6486 u8 op_mod[0x10]; 6487 6488 u8 reserved_at_40[0x80]; 6489 6490 u8 clear[0x1]; 6491 u8 reserved_at_c1[0xf]; 6492 u8 num_of_counters[0x10]; 6493 6494 u8 flow_counter_id[0x20]; 6495 }; 6496 6497 struct mlx5_ifc_query_esw_vport_context_out_bits { 6498 u8 status[0x8]; 6499 u8 reserved_at_8[0x18]; 6500 6501 u8 syndrome[0x20]; 6502 6503 u8 reserved_at_40[0x40]; 6504 6505 struct mlx5_ifc_esw_vport_context_bits esw_vport_context; 6506 }; 6507 6508 struct mlx5_ifc_query_esw_vport_context_in_bits { 6509 u8 opcode[0x10]; 6510 u8 reserved_at_10[0x10]; 6511 6512 u8 reserved_at_20[0x10]; 6513 u8 op_mod[0x10]; 6514 6515 u8 other_vport[0x1]; 6516 u8 reserved_at_41[0xf]; 6517 u8 vport_number[0x10]; 6518 6519 u8 reserved_at_60[0x20]; 6520 }; 6521 6522 struct mlx5_ifc_modify_esw_vport_context_out_bits { 6523 u8 status[0x8]; 6524 u8 reserved_at_8[0x18]; 6525 6526 u8 syndrome[0x20]; 6527 6528 u8 reserved_at_40[0x40]; 6529 }; 6530 6531 struct mlx5_ifc_esw_vport_context_fields_select_bits { 6532 u8 reserved_at_0[0x1b]; 6533 u8 fdb_to_vport_reg_c_id[0x1]; 6534 u8 vport_cvlan_insert[0x1]; 6535 u8 vport_svlan_insert[0x1]; 6536 u8 vport_cvlan_strip[0x1]; 6537 u8 vport_svlan_strip[0x1]; 6538 }; 6539 6540 struct mlx5_ifc_modify_esw_vport_context_in_bits { 6541 u8 opcode[0x10]; 6542 u8 reserved_at_10[0x10]; 6543 6544 u8 reserved_at_20[0x10]; 6545 u8 op_mod[0x10]; 6546 6547 u8 other_vport[0x1]; 6548 u8 reserved_at_41[0xf]; 6549 u8 vport_number[0x10]; 6550 6551 struct mlx5_ifc_esw_vport_context_fields_select_bits field_select; 6552 6553 struct mlx5_ifc_esw_vport_context_bits esw_vport_context; 6554 }; 6555 6556 struct mlx5_ifc_query_eq_out_bits { 6557 u8 status[0x8]; 6558 u8 reserved_at_8[0x18]; 6559 6560 u8 syndrome[0x20]; 6561 6562 u8 reserved_at_40[0x40]; 6563 6564 struct mlx5_ifc_eqc_bits eq_context_entry; 6565 6566 u8 reserved_at_280[0x40]; 6567 6568 u8 event_bitmask[0x40]; 6569 6570 u8 reserved_at_300[0x580]; 6571 6572 u8 pas[][0x40]; 6573 }; 6574 6575 struct mlx5_ifc_query_eq_in_bits { 6576 u8 opcode[0x10]; 6577 u8 reserved_at_10[0x10]; 6578 6579 u8 reserved_at_20[0x10]; 6580 u8 op_mod[0x10]; 6581 6582 u8 reserved_at_40[0x18]; 6583 u8 eq_number[0x8]; 6584 6585 u8 reserved_at_60[0x20]; 6586 }; 6587 6588 struct mlx5_ifc_packet_reformat_context_in_bits { 6589 u8 reformat_type[0x8]; 6590 u8 reserved_at_8[0x4]; 6591 u8 reformat_param_0[0x4]; 6592 u8 reserved_at_10[0x6]; 6593 u8 reformat_data_size[0xa]; 6594 6595 u8 reformat_param_1[0x8]; 6596 u8 reserved_at_28[0x8]; 6597 u8 reformat_data[2][0x8]; 6598 6599 u8 more_reformat_data[][0x8]; 6600 }; 6601 6602 struct mlx5_ifc_query_packet_reformat_context_out_bits { 6603 u8 status[0x8]; 6604 u8 reserved_at_8[0x18]; 6605 6606 u8 syndrome[0x20]; 6607 6608 u8 reserved_at_40[0xa0]; 6609 6610 struct mlx5_ifc_packet_reformat_context_in_bits packet_reformat_context[]; 6611 }; 6612 6613 struct mlx5_ifc_query_packet_reformat_context_in_bits { 6614 u8 opcode[0x10]; 6615 u8 reserved_at_10[0x10]; 6616 6617 u8 reserved_at_20[0x10]; 6618 u8 op_mod[0x10]; 6619 6620 u8 packet_reformat_id[0x20]; 6621 6622 u8 reserved_at_60[0xa0]; 6623 }; 6624 6625 struct mlx5_ifc_alloc_packet_reformat_context_out_bits { 6626 u8 status[0x8]; 6627 u8 reserved_at_8[0x18]; 6628 6629 u8 syndrome[0x20]; 6630 6631 u8 packet_reformat_id[0x20]; 6632 6633 u8 reserved_at_60[0x20]; 6634 }; 6635 6636 enum { 6637 MLX5_REFORMAT_CONTEXT_ANCHOR_MAC_START = 0x1, 6638 MLX5_REFORMAT_CONTEXT_ANCHOR_IP_START = 0x7, 6639 MLX5_REFORMAT_CONTEXT_ANCHOR_TCP_UDP_START = 0x9, 6640 }; 6641 6642 enum mlx5_reformat_ctx_type { 6643 MLX5_REFORMAT_TYPE_L2_TO_VXLAN = 0x0, 6644 MLX5_REFORMAT_TYPE_L2_TO_NVGRE = 0x1, 6645 MLX5_REFORMAT_TYPE_L2_TO_L2_TUNNEL = 0x2, 6646 MLX5_REFORMAT_TYPE_L3_TUNNEL_TO_L2 = 0x3, 6647 MLX5_REFORMAT_TYPE_L2_TO_L3_TUNNEL = 0x4, 6648 MLX5_REFORMAT_TYPE_ADD_ESP_TRANSPORT_OVER_IPV4 = 0x5, 6649 MLX5_REFORMAT_TYPE_L2_TO_L3_ESP_TUNNEL = 0x6, 6650 MLX5_REFORMAT_TYPE_DEL_ESP_TRANSPORT = 0x8, 6651 MLX5_REFORMAT_TYPE_L3_ESP_TUNNEL_TO_L2 = 0x9, 6652 MLX5_REFORMAT_TYPE_ADD_ESP_TRANSPORT_OVER_IPV6 = 0xb, 6653 MLX5_REFORMAT_TYPE_INSERT_HDR = 0xf, 6654 MLX5_REFORMAT_TYPE_REMOVE_HDR = 0x10, 6655 MLX5_REFORMAT_TYPE_ADD_MACSEC = 0x11, 6656 MLX5_REFORMAT_TYPE_DEL_MACSEC = 0x12, 6657 }; 6658 6659 struct mlx5_ifc_alloc_packet_reformat_context_in_bits { 6660 u8 opcode[0x10]; 6661 u8 reserved_at_10[0x10]; 6662 6663 u8 reserved_at_20[0x10]; 6664 u8 op_mod[0x10]; 6665 6666 u8 reserved_at_40[0xa0]; 6667 6668 struct mlx5_ifc_packet_reformat_context_in_bits packet_reformat_context; 6669 }; 6670 6671 struct mlx5_ifc_dealloc_packet_reformat_context_out_bits { 6672 u8 status[0x8]; 6673 u8 reserved_at_8[0x18]; 6674 6675 u8 syndrome[0x20]; 6676 6677 u8 reserved_at_40[0x40]; 6678 }; 6679 6680 struct mlx5_ifc_dealloc_packet_reformat_context_in_bits { 6681 u8 opcode[0x10]; 6682 u8 reserved_at_10[0x10]; 6683 6684 u8 reserved_20[0x10]; 6685 u8 op_mod[0x10]; 6686 6687 u8 packet_reformat_id[0x20]; 6688 6689 u8 reserved_60[0x20]; 6690 }; 6691 6692 struct mlx5_ifc_set_action_in_bits { 6693 u8 action_type[0x4]; 6694 u8 field[0xc]; 6695 u8 reserved_at_10[0x3]; 6696 u8 offset[0x5]; 6697 u8 reserved_at_18[0x3]; 6698 u8 length[0x5]; 6699 6700 u8 data[0x20]; 6701 }; 6702 6703 struct mlx5_ifc_add_action_in_bits { 6704 u8 action_type[0x4]; 6705 u8 field[0xc]; 6706 u8 reserved_at_10[0x10]; 6707 6708 u8 data[0x20]; 6709 }; 6710 6711 struct mlx5_ifc_copy_action_in_bits { 6712 u8 action_type[0x4]; 6713 u8 src_field[0xc]; 6714 u8 reserved_at_10[0x3]; 6715 u8 src_offset[0x5]; 6716 u8 reserved_at_18[0x3]; 6717 u8 length[0x5]; 6718 6719 u8 reserved_at_20[0x4]; 6720 u8 dst_field[0xc]; 6721 u8 reserved_at_30[0x3]; 6722 u8 dst_offset[0x5]; 6723 u8 reserved_at_38[0x8]; 6724 }; 6725 6726 union mlx5_ifc_set_add_copy_action_in_auto_bits { 6727 struct mlx5_ifc_set_action_in_bits set_action_in; 6728 struct mlx5_ifc_add_action_in_bits add_action_in; 6729 struct mlx5_ifc_copy_action_in_bits copy_action_in; 6730 u8 reserved_at_0[0x40]; 6731 }; 6732 6733 enum { 6734 MLX5_ACTION_TYPE_SET = 0x1, 6735 MLX5_ACTION_TYPE_ADD = 0x2, 6736 MLX5_ACTION_TYPE_COPY = 0x3, 6737 }; 6738 6739 enum { 6740 MLX5_ACTION_IN_FIELD_OUT_SMAC_47_16 = 0x1, 6741 MLX5_ACTION_IN_FIELD_OUT_SMAC_15_0 = 0x2, 6742 MLX5_ACTION_IN_FIELD_OUT_ETHERTYPE = 0x3, 6743 MLX5_ACTION_IN_FIELD_OUT_DMAC_47_16 = 0x4, 6744 MLX5_ACTION_IN_FIELD_OUT_DMAC_15_0 = 0x5, 6745 MLX5_ACTION_IN_FIELD_OUT_IP_DSCP = 0x6, 6746 MLX5_ACTION_IN_FIELD_OUT_TCP_FLAGS = 0x7, 6747 MLX5_ACTION_IN_FIELD_OUT_TCP_SPORT = 0x8, 6748 MLX5_ACTION_IN_FIELD_OUT_TCP_DPORT = 0x9, 6749 MLX5_ACTION_IN_FIELD_OUT_IP_TTL = 0xa, 6750 MLX5_ACTION_IN_FIELD_OUT_UDP_SPORT = 0xb, 6751 MLX5_ACTION_IN_FIELD_OUT_UDP_DPORT = 0xc, 6752 MLX5_ACTION_IN_FIELD_OUT_SIPV6_127_96 = 0xd, 6753 MLX5_ACTION_IN_FIELD_OUT_SIPV6_95_64 = 0xe, 6754 MLX5_ACTION_IN_FIELD_OUT_SIPV6_63_32 = 0xf, 6755 MLX5_ACTION_IN_FIELD_OUT_SIPV6_31_0 = 0x10, 6756 MLX5_ACTION_IN_FIELD_OUT_DIPV6_127_96 = 0x11, 6757 MLX5_ACTION_IN_FIELD_OUT_DIPV6_95_64 = 0x12, 6758 MLX5_ACTION_IN_FIELD_OUT_DIPV6_63_32 = 0x13, 6759 MLX5_ACTION_IN_FIELD_OUT_DIPV6_31_0 = 0x14, 6760 MLX5_ACTION_IN_FIELD_OUT_SIPV4 = 0x15, 6761 MLX5_ACTION_IN_FIELD_OUT_DIPV4 = 0x16, 6762 MLX5_ACTION_IN_FIELD_OUT_FIRST_VID = 0x17, 6763 MLX5_ACTION_IN_FIELD_OUT_IPV6_HOPLIMIT = 0x47, 6764 MLX5_ACTION_IN_FIELD_METADATA_REG_A = 0x49, 6765 MLX5_ACTION_IN_FIELD_METADATA_REG_B = 0x50, 6766 MLX5_ACTION_IN_FIELD_METADATA_REG_C_0 = 0x51, 6767 MLX5_ACTION_IN_FIELD_METADATA_REG_C_1 = 0x52, 6768 MLX5_ACTION_IN_FIELD_METADATA_REG_C_2 = 0x53, 6769 MLX5_ACTION_IN_FIELD_METADATA_REG_C_3 = 0x54, 6770 MLX5_ACTION_IN_FIELD_METADATA_REG_C_4 = 0x55, 6771 MLX5_ACTION_IN_FIELD_METADATA_REG_C_5 = 0x56, 6772 MLX5_ACTION_IN_FIELD_METADATA_REG_C_6 = 0x57, 6773 MLX5_ACTION_IN_FIELD_METADATA_REG_C_7 = 0x58, 6774 MLX5_ACTION_IN_FIELD_OUT_TCP_SEQ_NUM = 0x59, 6775 MLX5_ACTION_IN_FIELD_OUT_TCP_ACK_NUM = 0x5B, 6776 MLX5_ACTION_IN_FIELD_IPSEC_SYNDROME = 0x5D, 6777 MLX5_ACTION_IN_FIELD_OUT_EMD_47_32 = 0x6F, 6778 MLX5_ACTION_IN_FIELD_OUT_EMD_31_0 = 0x70, 6779 }; 6780 6781 struct mlx5_ifc_alloc_modify_header_context_out_bits { 6782 u8 status[0x8]; 6783 u8 reserved_at_8[0x18]; 6784 6785 u8 syndrome[0x20]; 6786 6787 u8 modify_header_id[0x20]; 6788 6789 u8 reserved_at_60[0x20]; 6790 }; 6791 6792 struct mlx5_ifc_alloc_modify_header_context_in_bits { 6793 u8 opcode[0x10]; 6794 u8 reserved_at_10[0x10]; 6795 6796 u8 reserved_at_20[0x10]; 6797 u8 op_mod[0x10]; 6798 6799 u8 reserved_at_40[0x20]; 6800 6801 u8 table_type[0x8]; 6802 u8 reserved_at_68[0x10]; 6803 u8 num_of_actions[0x8]; 6804 6805 union mlx5_ifc_set_add_copy_action_in_auto_bits actions[]; 6806 }; 6807 6808 struct mlx5_ifc_dealloc_modify_header_context_out_bits { 6809 u8 status[0x8]; 6810 u8 reserved_at_8[0x18]; 6811 6812 u8 syndrome[0x20]; 6813 6814 u8 reserved_at_40[0x40]; 6815 }; 6816 6817 struct mlx5_ifc_dealloc_modify_header_context_in_bits { 6818 u8 opcode[0x10]; 6819 u8 reserved_at_10[0x10]; 6820 6821 u8 reserved_at_20[0x10]; 6822 u8 op_mod[0x10]; 6823 6824 u8 modify_header_id[0x20]; 6825 6826 u8 reserved_at_60[0x20]; 6827 }; 6828 6829 struct mlx5_ifc_query_modify_header_context_in_bits { 6830 u8 opcode[0x10]; 6831 u8 uid[0x10]; 6832 6833 u8 reserved_at_20[0x10]; 6834 u8 op_mod[0x10]; 6835 6836 u8 modify_header_id[0x20]; 6837 6838 u8 reserved_at_60[0xa0]; 6839 }; 6840 6841 struct mlx5_ifc_query_dct_out_bits { 6842 u8 status[0x8]; 6843 u8 reserved_at_8[0x18]; 6844 6845 u8 syndrome[0x20]; 6846 6847 u8 reserved_at_40[0x40]; 6848 6849 struct mlx5_ifc_dctc_bits dct_context_entry; 6850 6851 u8 reserved_at_280[0x180]; 6852 }; 6853 6854 struct mlx5_ifc_query_dct_in_bits { 6855 u8 opcode[0x10]; 6856 u8 reserved_at_10[0x10]; 6857 6858 u8 reserved_at_20[0x10]; 6859 u8 op_mod[0x10]; 6860 6861 u8 reserved_at_40[0x8]; 6862 u8 dctn[0x18]; 6863 6864 u8 reserved_at_60[0x20]; 6865 }; 6866 6867 struct mlx5_ifc_query_cq_out_bits { 6868 u8 status[0x8]; 6869 u8 reserved_at_8[0x18]; 6870 6871 u8 syndrome[0x20]; 6872 6873 u8 reserved_at_40[0x40]; 6874 6875 struct mlx5_ifc_cqc_bits cq_context; 6876 6877 u8 reserved_at_280[0x600]; 6878 6879 u8 pas[][0x40]; 6880 }; 6881 6882 struct mlx5_ifc_query_cq_in_bits { 6883 u8 opcode[0x10]; 6884 u8 reserved_at_10[0x10]; 6885 6886 u8 reserved_at_20[0x10]; 6887 u8 op_mod[0x10]; 6888 6889 u8 reserved_at_40[0x8]; 6890 u8 cqn[0x18]; 6891 6892 u8 reserved_at_60[0x20]; 6893 }; 6894 6895 struct mlx5_ifc_query_cong_status_out_bits { 6896 u8 status[0x8]; 6897 u8 reserved_at_8[0x18]; 6898 6899 u8 syndrome[0x20]; 6900 6901 u8 reserved_at_40[0x20]; 6902 6903 u8 enable[0x1]; 6904 u8 tag_enable[0x1]; 6905 u8 reserved_at_62[0x1e]; 6906 }; 6907 6908 struct mlx5_ifc_query_cong_status_in_bits { 6909 u8 opcode[0x10]; 6910 u8 reserved_at_10[0x10]; 6911 6912 u8 reserved_at_20[0x10]; 6913 u8 op_mod[0x10]; 6914 6915 u8 reserved_at_40[0x18]; 6916 u8 priority[0x4]; 6917 u8 cong_protocol[0x4]; 6918 6919 u8 reserved_at_60[0x20]; 6920 }; 6921 6922 struct mlx5_ifc_query_cong_statistics_out_bits { 6923 u8 status[0x8]; 6924 u8 reserved_at_8[0x18]; 6925 6926 u8 syndrome[0x20]; 6927 6928 u8 reserved_at_40[0x40]; 6929 6930 u8 rp_cur_flows[0x20]; 6931 6932 u8 sum_flows[0x20]; 6933 6934 u8 rp_cnp_ignored_high[0x20]; 6935 6936 u8 rp_cnp_ignored_low[0x20]; 6937 6938 u8 rp_cnp_handled_high[0x20]; 6939 6940 u8 rp_cnp_handled_low[0x20]; 6941 6942 u8 reserved_at_140[0x100]; 6943 6944 u8 time_stamp_high[0x20]; 6945 6946 u8 time_stamp_low[0x20]; 6947 6948 u8 accumulators_period[0x20]; 6949 6950 u8 np_ecn_marked_roce_packets_high[0x20]; 6951 6952 u8 np_ecn_marked_roce_packets_low[0x20]; 6953 6954 u8 np_cnp_sent_high[0x20]; 6955 6956 u8 np_cnp_sent_low[0x20]; 6957 6958 u8 reserved_at_320[0x560]; 6959 }; 6960 6961 struct mlx5_ifc_query_cong_statistics_in_bits { 6962 u8 opcode[0x10]; 6963 u8 reserved_at_10[0x10]; 6964 6965 u8 reserved_at_20[0x10]; 6966 u8 op_mod[0x10]; 6967 6968 u8 clear[0x1]; 6969 u8 reserved_at_41[0x1f]; 6970 6971 u8 reserved_at_60[0x20]; 6972 }; 6973 6974 struct mlx5_ifc_query_cong_params_out_bits { 6975 u8 status[0x8]; 6976 u8 reserved_at_8[0x18]; 6977 6978 u8 syndrome[0x20]; 6979 6980 u8 reserved_at_40[0x40]; 6981 6982 union mlx5_ifc_cong_control_roce_ecn_auto_bits congestion_parameters; 6983 }; 6984 6985 struct mlx5_ifc_query_cong_params_in_bits { 6986 u8 opcode[0x10]; 6987 u8 reserved_at_10[0x10]; 6988 6989 u8 reserved_at_20[0x10]; 6990 u8 op_mod[0x10]; 6991 6992 u8 reserved_at_40[0x1c]; 6993 u8 cong_protocol[0x4]; 6994 6995 u8 reserved_at_60[0x20]; 6996 }; 6997 6998 struct mlx5_ifc_query_adapter_out_bits { 6999 u8 status[0x8]; 7000 u8 reserved_at_8[0x18]; 7001 7002 u8 syndrome[0x20]; 7003 7004 u8 reserved_at_40[0x40]; 7005 7006 struct mlx5_ifc_query_adapter_param_block_bits query_adapter_struct; 7007 }; 7008 7009 struct mlx5_ifc_query_adapter_in_bits { 7010 u8 opcode[0x10]; 7011 u8 reserved_at_10[0x10]; 7012 7013 u8 reserved_at_20[0x10]; 7014 u8 op_mod[0x10]; 7015 7016 u8 reserved_at_40[0x40]; 7017 }; 7018 7019 struct mlx5_ifc_qp_2rst_out_bits { 7020 u8 status[0x8]; 7021 u8 reserved_at_8[0x18]; 7022 7023 u8 syndrome[0x20]; 7024 7025 u8 reserved_at_40[0x40]; 7026 }; 7027 7028 struct mlx5_ifc_qp_2rst_in_bits { 7029 u8 opcode[0x10]; 7030 u8 uid[0x10]; 7031 7032 u8 reserved_at_20[0x10]; 7033 u8 op_mod[0x10]; 7034 7035 u8 reserved_at_40[0x8]; 7036 u8 qpn[0x18]; 7037 7038 u8 reserved_at_60[0x20]; 7039 }; 7040 7041 struct mlx5_ifc_qp_2err_out_bits { 7042 u8 status[0x8]; 7043 u8 reserved_at_8[0x18]; 7044 7045 u8 syndrome[0x20]; 7046 7047 u8 reserved_at_40[0x40]; 7048 }; 7049 7050 struct mlx5_ifc_qp_2err_in_bits { 7051 u8 opcode[0x10]; 7052 u8 uid[0x10]; 7053 7054 u8 reserved_at_20[0x10]; 7055 u8 op_mod[0x10]; 7056 7057 u8 reserved_at_40[0x8]; 7058 u8 qpn[0x18]; 7059 7060 u8 reserved_at_60[0x20]; 7061 }; 7062 7063 struct mlx5_ifc_page_fault_resume_out_bits { 7064 u8 status[0x8]; 7065 u8 reserved_at_8[0x18]; 7066 7067 u8 syndrome[0x20]; 7068 7069 u8 reserved_at_40[0x40]; 7070 }; 7071 7072 struct mlx5_ifc_page_fault_resume_in_bits { 7073 u8 opcode[0x10]; 7074 u8 reserved_at_10[0x10]; 7075 7076 u8 reserved_at_20[0x10]; 7077 u8 op_mod[0x10]; 7078 7079 u8 error[0x1]; 7080 u8 reserved_at_41[0x4]; 7081 u8 page_fault_type[0x3]; 7082 u8 wq_number[0x18]; 7083 7084 u8 reserved_at_60[0x8]; 7085 u8 token[0x18]; 7086 }; 7087 7088 struct mlx5_ifc_nop_out_bits { 7089 u8 status[0x8]; 7090 u8 reserved_at_8[0x18]; 7091 7092 u8 syndrome[0x20]; 7093 7094 u8 reserved_at_40[0x40]; 7095 }; 7096 7097 struct mlx5_ifc_nop_in_bits { 7098 u8 opcode[0x10]; 7099 u8 reserved_at_10[0x10]; 7100 7101 u8 reserved_at_20[0x10]; 7102 u8 op_mod[0x10]; 7103 7104 u8 reserved_at_40[0x40]; 7105 }; 7106 7107 struct mlx5_ifc_modify_vport_state_out_bits { 7108 u8 status[0x8]; 7109 u8 reserved_at_8[0x18]; 7110 7111 u8 syndrome[0x20]; 7112 7113 u8 reserved_at_40[0x40]; 7114 }; 7115 7116 struct mlx5_ifc_modify_vport_state_in_bits { 7117 u8 opcode[0x10]; 7118 u8 reserved_at_10[0x10]; 7119 7120 u8 reserved_at_20[0x10]; 7121 u8 op_mod[0x10]; 7122 7123 u8 other_vport[0x1]; 7124 u8 reserved_at_41[0xf]; 7125 u8 vport_number[0x10]; 7126 7127 u8 reserved_at_60[0x18]; 7128 u8 admin_state[0x4]; 7129 u8 reserved_at_7c[0x4]; 7130 }; 7131 7132 struct mlx5_ifc_modify_tis_out_bits { 7133 u8 status[0x8]; 7134 u8 reserved_at_8[0x18]; 7135 7136 u8 syndrome[0x20]; 7137 7138 u8 reserved_at_40[0x40]; 7139 }; 7140 7141 struct mlx5_ifc_modify_tis_bitmask_bits { 7142 u8 reserved_at_0[0x20]; 7143 7144 u8 reserved_at_20[0x1d]; 7145 u8 lag_tx_port_affinity[0x1]; 7146 u8 strict_lag_tx_port_affinity[0x1]; 7147 u8 prio[0x1]; 7148 }; 7149 7150 struct mlx5_ifc_modify_tis_in_bits { 7151 u8 opcode[0x10]; 7152 u8 uid[0x10]; 7153 7154 u8 reserved_at_20[0x10]; 7155 u8 op_mod[0x10]; 7156 7157 u8 reserved_at_40[0x8]; 7158 u8 tisn[0x18]; 7159 7160 u8 reserved_at_60[0x20]; 7161 7162 struct mlx5_ifc_modify_tis_bitmask_bits bitmask; 7163 7164 u8 reserved_at_c0[0x40]; 7165 7166 struct mlx5_ifc_tisc_bits ctx; 7167 }; 7168 7169 struct mlx5_ifc_modify_tir_bitmask_bits { 7170 u8 reserved_at_0[0x20]; 7171 7172 u8 reserved_at_20[0x1b]; 7173 u8 self_lb_en[0x1]; 7174 u8 reserved_at_3c[0x1]; 7175 u8 hash[0x1]; 7176 u8 reserved_at_3e[0x1]; 7177 u8 packet_merge[0x1]; 7178 }; 7179 7180 struct mlx5_ifc_modify_tir_out_bits { 7181 u8 status[0x8]; 7182 u8 reserved_at_8[0x18]; 7183 7184 u8 syndrome[0x20]; 7185 7186 u8 reserved_at_40[0x40]; 7187 }; 7188 7189 struct mlx5_ifc_modify_tir_in_bits { 7190 u8 opcode[0x10]; 7191 u8 uid[0x10]; 7192 7193 u8 reserved_at_20[0x10]; 7194 u8 op_mod[0x10]; 7195 7196 u8 reserved_at_40[0x8]; 7197 u8 tirn[0x18]; 7198 7199 u8 reserved_at_60[0x20]; 7200 7201 struct mlx5_ifc_modify_tir_bitmask_bits bitmask; 7202 7203 u8 reserved_at_c0[0x40]; 7204 7205 struct mlx5_ifc_tirc_bits ctx; 7206 }; 7207 7208 struct mlx5_ifc_modify_sq_out_bits { 7209 u8 status[0x8]; 7210 u8 reserved_at_8[0x18]; 7211 7212 u8 syndrome[0x20]; 7213 7214 u8 reserved_at_40[0x40]; 7215 }; 7216 7217 struct mlx5_ifc_modify_sq_in_bits { 7218 u8 opcode[0x10]; 7219 u8 uid[0x10]; 7220 7221 u8 reserved_at_20[0x10]; 7222 u8 op_mod[0x10]; 7223 7224 u8 sq_state[0x4]; 7225 u8 reserved_at_44[0x4]; 7226 u8 sqn[0x18]; 7227 7228 u8 reserved_at_60[0x20]; 7229 7230 u8 modify_bitmask[0x40]; 7231 7232 u8 reserved_at_c0[0x40]; 7233 7234 struct mlx5_ifc_sqc_bits ctx; 7235 }; 7236 7237 struct mlx5_ifc_modify_scheduling_element_out_bits { 7238 u8 status[0x8]; 7239 u8 reserved_at_8[0x18]; 7240 7241 u8 syndrome[0x20]; 7242 7243 u8 reserved_at_40[0x1c0]; 7244 }; 7245 7246 enum { 7247 MODIFY_SCHEDULING_ELEMENT_IN_MODIFY_BITMASK_BW_SHARE = 0x1, 7248 MODIFY_SCHEDULING_ELEMENT_IN_MODIFY_BITMASK_MAX_AVERAGE_BW = 0x2, 7249 }; 7250 7251 struct mlx5_ifc_modify_scheduling_element_in_bits { 7252 u8 opcode[0x10]; 7253 u8 reserved_at_10[0x10]; 7254 7255 u8 reserved_at_20[0x10]; 7256 u8 op_mod[0x10]; 7257 7258 u8 scheduling_hierarchy[0x8]; 7259 u8 reserved_at_48[0x18]; 7260 7261 u8 scheduling_element_id[0x20]; 7262 7263 u8 reserved_at_80[0x20]; 7264 7265 u8 modify_bitmask[0x20]; 7266 7267 u8 reserved_at_c0[0x40]; 7268 7269 struct mlx5_ifc_scheduling_context_bits scheduling_context; 7270 7271 u8 reserved_at_300[0x100]; 7272 }; 7273 7274 struct mlx5_ifc_modify_rqt_out_bits { 7275 u8 status[0x8]; 7276 u8 reserved_at_8[0x18]; 7277 7278 u8 syndrome[0x20]; 7279 7280 u8 reserved_at_40[0x40]; 7281 }; 7282 7283 struct mlx5_ifc_rqt_bitmask_bits { 7284 u8 reserved_at_0[0x20]; 7285 7286 u8 reserved_at_20[0x1f]; 7287 u8 rqn_list[0x1]; 7288 }; 7289 7290 struct mlx5_ifc_modify_rqt_in_bits { 7291 u8 opcode[0x10]; 7292 u8 uid[0x10]; 7293 7294 u8 reserved_at_20[0x10]; 7295 u8 op_mod[0x10]; 7296 7297 u8 reserved_at_40[0x8]; 7298 u8 rqtn[0x18]; 7299 7300 u8 reserved_at_60[0x20]; 7301 7302 struct mlx5_ifc_rqt_bitmask_bits bitmask; 7303 7304 u8 reserved_at_c0[0x40]; 7305 7306 struct mlx5_ifc_rqtc_bits ctx; 7307 }; 7308 7309 struct mlx5_ifc_modify_rq_out_bits { 7310 u8 status[0x8]; 7311 u8 reserved_at_8[0x18]; 7312 7313 u8 syndrome[0x20]; 7314 7315 u8 reserved_at_40[0x40]; 7316 }; 7317 7318 enum { 7319 MLX5_MODIFY_RQ_IN_MODIFY_BITMASK_VSD = 1ULL << 1, 7320 MLX5_MODIFY_RQ_IN_MODIFY_BITMASK_SCATTER_FCS = 1ULL << 2, 7321 MLX5_MODIFY_RQ_IN_MODIFY_BITMASK_RQ_COUNTER_SET_ID = 1ULL << 3, 7322 }; 7323 7324 struct mlx5_ifc_modify_rq_in_bits { 7325 u8 opcode[0x10]; 7326 u8 uid[0x10]; 7327 7328 u8 reserved_at_20[0x10]; 7329 u8 op_mod[0x10]; 7330 7331 u8 rq_state[0x4]; 7332 u8 reserved_at_44[0x4]; 7333 u8 rqn[0x18]; 7334 7335 u8 reserved_at_60[0x20]; 7336 7337 u8 modify_bitmask[0x40]; 7338 7339 u8 reserved_at_c0[0x40]; 7340 7341 struct mlx5_ifc_rqc_bits ctx; 7342 }; 7343 7344 struct mlx5_ifc_modify_rmp_out_bits { 7345 u8 status[0x8]; 7346 u8 reserved_at_8[0x18]; 7347 7348 u8 syndrome[0x20]; 7349 7350 u8 reserved_at_40[0x40]; 7351 }; 7352 7353 struct mlx5_ifc_rmp_bitmask_bits { 7354 u8 reserved_at_0[0x20]; 7355 7356 u8 reserved_at_20[0x1f]; 7357 u8 lwm[0x1]; 7358 }; 7359 7360 struct mlx5_ifc_modify_rmp_in_bits { 7361 u8 opcode[0x10]; 7362 u8 uid[0x10]; 7363 7364 u8 reserved_at_20[0x10]; 7365 u8 op_mod[0x10]; 7366 7367 u8 rmp_state[0x4]; 7368 u8 reserved_at_44[0x4]; 7369 u8 rmpn[0x18]; 7370 7371 u8 reserved_at_60[0x20]; 7372 7373 struct mlx5_ifc_rmp_bitmask_bits bitmask; 7374 7375 u8 reserved_at_c0[0x40]; 7376 7377 struct mlx5_ifc_rmpc_bits ctx; 7378 }; 7379 7380 struct mlx5_ifc_modify_nic_vport_context_out_bits { 7381 u8 status[0x8]; 7382 u8 reserved_at_8[0x18]; 7383 7384 u8 syndrome[0x20]; 7385 7386 u8 reserved_at_40[0x40]; 7387 }; 7388 7389 struct mlx5_ifc_modify_nic_vport_field_select_bits { 7390 u8 reserved_at_0[0x12]; 7391 u8 affiliation[0x1]; 7392 u8 reserved_at_13[0x1]; 7393 u8 disable_uc_local_lb[0x1]; 7394 u8 disable_mc_local_lb[0x1]; 7395 u8 node_guid[0x1]; 7396 u8 port_guid[0x1]; 7397 u8 min_inline[0x1]; 7398 u8 mtu[0x1]; 7399 u8 change_event[0x1]; 7400 u8 promisc[0x1]; 7401 u8 permanent_address[0x1]; 7402 u8 addresses_list[0x1]; 7403 u8 roce_en[0x1]; 7404 u8 reserved_at_1f[0x1]; 7405 }; 7406 7407 struct mlx5_ifc_modify_nic_vport_context_in_bits { 7408 u8 opcode[0x10]; 7409 u8 reserved_at_10[0x10]; 7410 7411 u8 reserved_at_20[0x10]; 7412 u8 op_mod[0x10]; 7413 7414 u8 other_vport[0x1]; 7415 u8 reserved_at_41[0xf]; 7416 u8 vport_number[0x10]; 7417 7418 struct mlx5_ifc_modify_nic_vport_field_select_bits field_select; 7419 7420 u8 reserved_at_80[0x780]; 7421 7422 struct mlx5_ifc_nic_vport_context_bits nic_vport_context; 7423 }; 7424 7425 struct mlx5_ifc_modify_hca_vport_context_out_bits { 7426 u8 status[0x8]; 7427 u8 reserved_at_8[0x18]; 7428 7429 u8 syndrome[0x20]; 7430 7431 u8 reserved_at_40[0x40]; 7432 }; 7433 7434 struct mlx5_ifc_modify_hca_vport_context_in_bits { 7435 u8 opcode[0x10]; 7436 u8 reserved_at_10[0x10]; 7437 7438 u8 reserved_at_20[0x10]; 7439 u8 op_mod[0x10]; 7440 7441 u8 other_vport[0x1]; 7442 u8 reserved_at_41[0xb]; 7443 u8 port_num[0x4]; 7444 u8 vport_number[0x10]; 7445 7446 u8 reserved_at_60[0x20]; 7447 7448 struct mlx5_ifc_hca_vport_context_bits hca_vport_context; 7449 }; 7450 7451 struct mlx5_ifc_modify_cq_out_bits { 7452 u8 status[0x8]; 7453 u8 reserved_at_8[0x18]; 7454 7455 u8 syndrome[0x20]; 7456 7457 u8 reserved_at_40[0x40]; 7458 }; 7459 7460 enum { 7461 MLX5_MODIFY_CQ_IN_OP_MOD_MODIFY_CQ = 0x0, 7462 MLX5_MODIFY_CQ_IN_OP_MOD_RESIZE_CQ = 0x1, 7463 }; 7464 7465 struct mlx5_ifc_modify_cq_in_bits { 7466 u8 opcode[0x10]; 7467 u8 uid[0x10]; 7468 7469 u8 reserved_at_20[0x10]; 7470 u8 op_mod[0x10]; 7471 7472 u8 reserved_at_40[0x8]; 7473 u8 cqn[0x18]; 7474 7475 union mlx5_ifc_modify_field_select_resize_field_select_auto_bits modify_field_select_resize_field_select; 7476 7477 struct mlx5_ifc_cqc_bits cq_context; 7478 7479 u8 reserved_at_280[0x60]; 7480 7481 u8 cq_umem_valid[0x1]; 7482 u8 reserved_at_2e1[0x1f]; 7483 7484 u8 reserved_at_300[0x580]; 7485 7486 u8 pas[][0x40]; 7487 }; 7488 7489 struct mlx5_ifc_modify_cong_status_out_bits { 7490 u8 status[0x8]; 7491 u8 reserved_at_8[0x18]; 7492 7493 u8 syndrome[0x20]; 7494 7495 u8 reserved_at_40[0x40]; 7496 }; 7497 7498 struct mlx5_ifc_modify_cong_status_in_bits { 7499 u8 opcode[0x10]; 7500 u8 reserved_at_10[0x10]; 7501 7502 u8 reserved_at_20[0x10]; 7503 u8 op_mod[0x10]; 7504 7505 u8 reserved_at_40[0x18]; 7506 u8 priority[0x4]; 7507 u8 cong_protocol[0x4]; 7508 7509 u8 enable[0x1]; 7510 u8 tag_enable[0x1]; 7511 u8 reserved_at_62[0x1e]; 7512 }; 7513 7514 struct mlx5_ifc_modify_cong_params_out_bits { 7515 u8 status[0x8]; 7516 u8 reserved_at_8[0x18]; 7517 7518 u8 syndrome[0x20]; 7519 7520 u8 reserved_at_40[0x40]; 7521 }; 7522 7523 struct mlx5_ifc_modify_cong_params_in_bits { 7524 u8 opcode[0x10]; 7525 u8 reserved_at_10[0x10]; 7526 7527 u8 reserved_at_20[0x10]; 7528 u8 op_mod[0x10]; 7529 7530 u8 reserved_at_40[0x1c]; 7531 u8 cong_protocol[0x4]; 7532 7533 union mlx5_ifc_field_select_802_1_r_roce_auto_bits field_select; 7534 7535 u8 reserved_at_80[0x80]; 7536 7537 union mlx5_ifc_cong_control_roce_ecn_auto_bits congestion_parameters; 7538 }; 7539 7540 struct mlx5_ifc_manage_pages_out_bits { 7541 u8 status[0x8]; 7542 u8 reserved_at_8[0x18]; 7543 7544 u8 syndrome[0x20]; 7545 7546 u8 output_num_entries[0x20]; 7547 7548 u8 reserved_at_60[0x20]; 7549 7550 u8 pas[][0x40]; 7551 }; 7552 7553 enum { 7554 MLX5_MANAGE_PAGES_IN_OP_MOD_ALLOCATION_FAIL = 0x0, 7555 MLX5_MANAGE_PAGES_IN_OP_MOD_ALLOCATION_SUCCESS = 0x1, 7556 MLX5_MANAGE_PAGES_IN_OP_MOD_HCA_RETURN_PAGES = 0x2, 7557 }; 7558 7559 struct mlx5_ifc_manage_pages_in_bits { 7560 u8 opcode[0x10]; 7561 u8 reserved_at_10[0x10]; 7562 7563 u8 reserved_at_20[0x10]; 7564 u8 op_mod[0x10]; 7565 7566 u8 embedded_cpu_function[0x1]; 7567 u8 reserved_at_41[0xf]; 7568 u8 function_id[0x10]; 7569 7570 u8 input_num_entries[0x20]; 7571 7572 u8 pas[][0x40]; 7573 }; 7574 7575 struct mlx5_ifc_mad_ifc_out_bits { 7576 u8 status[0x8]; 7577 u8 reserved_at_8[0x18]; 7578 7579 u8 syndrome[0x20]; 7580 7581 u8 reserved_at_40[0x40]; 7582 7583 u8 response_mad_packet[256][0x8]; 7584 }; 7585 7586 struct mlx5_ifc_mad_ifc_in_bits { 7587 u8 opcode[0x10]; 7588 u8 reserved_at_10[0x10]; 7589 7590 u8 reserved_at_20[0x10]; 7591 u8 op_mod[0x10]; 7592 7593 u8 remote_lid[0x10]; 7594 u8 reserved_at_50[0x8]; 7595 u8 port[0x8]; 7596 7597 u8 reserved_at_60[0x20]; 7598 7599 u8 mad[256][0x8]; 7600 }; 7601 7602 struct mlx5_ifc_init_hca_out_bits { 7603 u8 status[0x8]; 7604 u8 reserved_at_8[0x18]; 7605 7606 u8 syndrome[0x20]; 7607 7608 u8 reserved_at_40[0x40]; 7609 }; 7610 7611 struct mlx5_ifc_init_hca_in_bits { 7612 u8 opcode[0x10]; 7613 u8 reserved_at_10[0x10]; 7614 7615 u8 reserved_at_20[0x10]; 7616 u8 op_mod[0x10]; 7617 7618 u8 reserved_at_40[0x20]; 7619 7620 u8 reserved_at_60[0x2]; 7621 u8 sw_vhca_id[0xe]; 7622 u8 reserved_at_70[0x10]; 7623 7624 u8 sw_owner_id[4][0x20]; 7625 }; 7626 7627 struct mlx5_ifc_init2rtr_qp_out_bits { 7628 u8 status[0x8]; 7629 u8 reserved_at_8[0x18]; 7630 7631 u8 syndrome[0x20]; 7632 7633 u8 reserved_at_40[0x20]; 7634 u8 ece[0x20]; 7635 }; 7636 7637 struct mlx5_ifc_init2rtr_qp_in_bits { 7638 u8 opcode[0x10]; 7639 u8 uid[0x10]; 7640 7641 u8 reserved_at_20[0x10]; 7642 u8 op_mod[0x10]; 7643 7644 u8 reserved_at_40[0x8]; 7645 u8 qpn[0x18]; 7646 7647 u8 reserved_at_60[0x20]; 7648 7649 u8 opt_param_mask[0x20]; 7650 7651 u8 ece[0x20]; 7652 7653 struct mlx5_ifc_qpc_bits qpc; 7654 7655 u8 reserved_at_800[0x80]; 7656 }; 7657 7658 struct mlx5_ifc_init2init_qp_out_bits { 7659 u8 status[0x8]; 7660 u8 reserved_at_8[0x18]; 7661 7662 u8 syndrome[0x20]; 7663 7664 u8 reserved_at_40[0x20]; 7665 u8 ece[0x20]; 7666 }; 7667 7668 struct mlx5_ifc_init2init_qp_in_bits { 7669 u8 opcode[0x10]; 7670 u8 uid[0x10]; 7671 7672 u8 reserved_at_20[0x10]; 7673 u8 op_mod[0x10]; 7674 7675 u8 reserved_at_40[0x8]; 7676 u8 qpn[0x18]; 7677 7678 u8 reserved_at_60[0x20]; 7679 7680 u8 opt_param_mask[0x20]; 7681 7682 u8 ece[0x20]; 7683 7684 struct mlx5_ifc_qpc_bits qpc; 7685 7686 u8 reserved_at_800[0x80]; 7687 }; 7688 7689 struct mlx5_ifc_get_dropped_packet_log_out_bits { 7690 u8 status[0x8]; 7691 u8 reserved_at_8[0x18]; 7692 7693 u8 syndrome[0x20]; 7694 7695 u8 reserved_at_40[0x40]; 7696 7697 u8 packet_headers_log[128][0x8]; 7698 7699 u8 packet_syndrome[64][0x8]; 7700 }; 7701 7702 struct mlx5_ifc_get_dropped_packet_log_in_bits { 7703 u8 opcode[0x10]; 7704 u8 reserved_at_10[0x10]; 7705 7706 u8 reserved_at_20[0x10]; 7707 u8 op_mod[0x10]; 7708 7709 u8 reserved_at_40[0x40]; 7710 }; 7711 7712 struct mlx5_ifc_gen_eqe_in_bits { 7713 u8 opcode[0x10]; 7714 u8 reserved_at_10[0x10]; 7715 7716 u8 reserved_at_20[0x10]; 7717 u8 op_mod[0x10]; 7718 7719 u8 reserved_at_40[0x18]; 7720 u8 eq_number[0x8]; 7721 7722 u8 reserved_at_60[0x20]; 7723 7724 u8 eqe[64][0x8]; 7725 }; 7726 7727 struct mlx5_ifc_gen_eq_out_bits { 7728 u8 status[0x8]; 7729 u8 reserved_at_8[0x18]; 7730 7731 u8 syndrome[0x20]; 7732 7733 u8 reserved_at_40[0x40]; 7734 }; 7735 7736 struct mlx5_ifc_enable_hca_out_bits { 7737 u8 status[0x8]; 7738 u8 reserved_at_8[0x18]; 7739 7740 u8 syndrome[0x20]; 7741 7742 u8 reserved_at_40[0x20]; 7743 }; 7744 7745 struct mlx5_ifc_enable_hca_in_bits { 7746 u8 opcode[0x10]; 7747 u8 reserved_at_10[0x10]; 7748 7749 u8 reserved_at_20[0x10]; 7750 u8 op_mod[0x10]; 7751 7752 u8 embedded_cpu_function[0x1]; 7753 u8 reserved_at_41[0xf]; 7754 u8 function_id[0x10]; 7755 7756 u8 reserved_at_60[0x20]; 7757 }; 7758 7759 struct mlx5_ifc_drain_dct_out_bits { 7760 u8 status[0x8]; 7761 u8 reserved_at_8[0x18]; 7762 7763 u8 syndrome[0x20]; 7764 7765 u8 reserved_at_40[0x40]; 7766 }; 7767 7768 struct mlx5_ifc_drain_dct_in_bits { 7769 u8 opcode[0x10]; 7770 u8 uid[0x10]; 7771 7772 u8 reserved_at_20[0x10]; 7773 u8 op_mod[0x10]; 7774 7775 u8 reserved_at_40[0x8]; 7776 u8 dctn[0x18]; 7777 7778 u8 reserved_at_60[0x20]; 7779 }; 7780 7781 struct mlx5_ifc_disable_hca_out_bits { 7782 u8 status[0x8]; 7783 u8 reserved_at_8[0x18]; 7784 7785 u8 syndrome[0x20]; 7786 7787 u8 reserved_at_40[0x20]; 7788 }; 7789 7790 struct mlx5_ifc_disable_hca_in_bits { 7791 u8 opcode[0x10]; 7792 u8 reserved_at_10[0x10]; 7793 7794 u8 reserved_at_20[0x10]; 7795 u8 op_mod[0x10]; 7796 7797 u8 embedded_cpu_function[0x1]; 7798 u8 reserved_at_41[0xf]; 7799 u8 function_id[0x10]; 7800 7801 u8 reserved_at_60[0x20]; 7802 }; 7803 7804 struct mlx5_ifc_detach_from_mcg_out_bits { 7805 u8 status[0x8]; 7806 u8 reserved_at_8[0x18]; 7807 7808 u8 syndrome[0x20]; 7809 7810 u8 reserved_at_40[0x40]; 7811 }; 7812 7813 struct mlx5_ifc_detach_from_mcg_in_bits { 7814 u8 opcode[0x10]; 7815 u8 uid[0x10]; 7816 7817 u8 reserved_at_20[0x10]; 7818 u8 op_mod[0x10]; 7819 7820 u8 reserved_at_40[0x8]; 7821 u8 qpn[0x18]; 7822 7823 u8 reserved_at_60[0x20]; 7824 7825 u8 multicast_gid[16][0x8]; 7826 }; 7827 7828 struct mlx5_ifc_destroy_xrq_out_bits { 7829 u8 status[0x8]; 7830 u8 reserved_at_8[0x18]; 7831 7832 u8 syndrome[0x20]; 7833 7834 u8 reserved_at_40[0x40]; 7835 }; 7836 7837 struct mlx5_ifc_destroy_xrq_in_bits { 7838 u8 opcode[0x10]; 7839 u8 uid[0x10]; 7840 7841 u8 reserved_at_20[0x10]; 7842 u8 op_mod[0x10]; 7843 7844 u8 reserved_at_40[0x8]; 7845 u8 xrqn[0x18]; 7846 7847 u8 reserved_at_60[0x20]; 7848 }; 7849 7850 struct mlx5_ifc_destroy_xrc_srq_out_bits { 7851 u8 status[0x8]; 7852 u8 reserved_at_8[0x18]; 7853 7854 u8 syndrome[0x20]; 7855 7856 u8 reserved_at_40[0x40]; 7857 }; 7858 7859 struct mlx5_ifc_destroy_xrc_srq_in_bits { 7860 u8 opcode[0x10]; 7861 u8 uid[0x10]; 7862 7863 u8 reserved_at_20[0x10]; 7864 u8 op_mod[0x10]; 7865 7866 u8 reserved_at_40[0x8]; 7867 u8 xrc_srqn[0x18]; 7868 7869 u8 reserved_at_60[0x20]; 7870 }; 7871 7872 struct mlx5_ifc_destroy_tis_out_bits { 7873 u8 status[0x8]; 7874 u8 reserved_at_8[0x18]; 7875 7876 u8 syndrome[0x20]; 7877 7878 u8 reserved_at_40[0x40]; 7879 }; 7880 7881 struct mlx5_ifc_destroy_tis_in_bits { 7882 u8 opcode[0x10]; 7883 u8 uid[0x10]; 7884 7885 u8 reserved_at_20[0x10]; 7886 u8 op_mod[0x10]; 7887 7888 u8 reserved_at_40[0x8]; 7889 u8 tisn[0x18]; 7890 7891 u8 reserved_at_60[0x20]; 7892 }; 7893 7894 struct mlx5_ifc_destroy_tir_out_bits { 7895 u8 status[0x8]; 7896 u8 reserved_at_8[0x18]; 7897 7898 u8 syndrome[0x20]; 7899 7900 u8 reserved_at_40[0x40]; 7901 }; 7902 7903 struct mlx5_ifc_destroy_tir_in_bits { 7904 u8 opcode[0x10]; 7905 u8 uid[0x10]; 7906 7907 u8 reserved_at_20[0x10]; 7908 u8 op_mod[0x10]; 7909 7910 u8 reserved_at_40[0x8]; 7911 u8 tirn[0x18]; 7912 7913 u8 reserved_at_60[0x20]; 7914 }; 7915 7916 struct mlx5_ifc_destroy_srq_out_bits { 7917 u8 status[0x8]; 7918 u8 reserved_at_8[0x18]; 7919 7920 u8 syndrome[0x20]; 7921 7922 u8 reserved_at_40[0x40]; 7923 }; 7924 7925 struct mlx5_ifc_destroy_srq_in_bits { 7926 u8 opcode[0x10]; 7927 u8 uid[0x10]; 7928 7929 u8 reserved_at_20[0x10]; 7930 u8 op_mod[0x10]; 7931 7932 u8 reserved_at_40[0x8]; 7933 u8 srqn[0x18]; 7934 7935 u8 reserved_at_60[0x20]; 7936 }; 7937 7938 struct mlx5_ifc_destroy_sq_out_bits { 7939 u8 status[0x8]; 7940 u8 reserved_at_8[0x18]; 7941 7942 u8 syndrome[0x20]; 7943 7944 u8 reserved_at_40[0x40]; 7945 }; 7946 7947 struct mlx5_ifc_destroy_sq_in_bits { 7948 u8 opcode[0x10]; 7949 u8 uid[0x10]; 7950 7951 u8 reserved_at_20[0x10]; 7952 u8 op_mod[0x10]; 7953 7954 u8 reserved_at_40[0x8]; 7955 u8 sqn[0x18]; 7956 7957 u8 reserved_at_60[0x20]; 7958 }; 7959 7960 struct mlx5_ifc_destroy_scheduling_element_out_bits { 7961 u8 status[0x8]; 7962 u8 reserved_at_8[0x18]; 7963 7964 u8 syndrome[0x20]; 7965 7966 u8 reserved_at_40[0x1c0]; 7967 }; 7968 7969 struct mlx5_ifc_destroy_scheduling_element_in_bits { 7970 u8 opcode[0x10]; 7971 u8 reserved_at_10[0x10]; 7972 7973 u8 reserved_at_20[0x10]; 7974 u8 op_mod[0x10]; 7975 7976 u8 scheduling_hierarchy[0x8]; 7977 u8 reserved_at_48[0x18]; 7978 7979 u8 scheduling_element_id[0x20]; 7980 7981 u8 reserved_at_80[0x180]; 7982 }; 7983 7984 struct mlx5_ifc_destroy_rqt_out_bits { 7985 u8 status[0x8]; 7986 u8 reserved_at_8[0x18]; 7987 7988 u8 syndrome[0x20]; 7989 7990 u8 reserved_at_40[0x40]; 7991 }; 7992 7993 struct mlx5_ifc_destroy_rqt_in_bits { 7994 u8 opcode[0x10]; 7995 u8 uid[0x10]; 7996 7997 u8 reserved_at_20[0x10]; 7998 u8 op_mod[0x10]; 7999 8000 u8 reserved_at_40[0x8]; 8001 u8 rqtn[0x18]; 8002 8003 u8 reserved_at_60[0x20]; 8004 }; 8005 8006 struct mlx5_ifc_destroy_rq_out_bits { 8007 u8 status[0x8]; 8008 u8 reserved_at_8[0x18]; 8009 8010 u8 syndrome[0x20]; 8011 8012 u8 reserved_at_40[0x40]; 8013 }; 8014 8015 struct mlx5_ifc_destroy_rq_in_bits { 8016 u8 opcode[0x10]; 8017 u8 uid[0x10]; 8018 8019 u8 reserved_at_20[0x10]; 8020 u8 op_mod[0x10]; 8021 8022 u8 reserved_at_40[0x8]; 8023 u8 rqn[0x18]; 8024 8025 u8 reserved_at_60[0x20]; 8026 }; 8027 8028 struct mlx5_ifc_set_delay_drop_params_in_bits { 8029 u8 opcode[0x10]; 8030 u8 reserved_at_10[0x10]; 8031 8032 u8 reserved_at_20[0x10]; 8033 u8 op_mod[0x10]; 8034 8035 u8 reserved_at_40[0x20]; 8036 8037 u8 reserved_at_60[0x10]; 8038 u8 delay_drop_timeout[0x10]; 8039 }; 8040 8041 struct mlx5_ifc_set_delay_drop_params_out_bits { 8042 u8 status[0x8]; 8043 u8 reserved_at_8[0x18]; 8044 8045 u8 syndrome[0x20]; 8046 8047 u8 reserved_at_40[0x40]; 8048 }; 8049 8050 struct mlx5_ifc_destroy_rmp_out_bits { 8051 u8 status[0x8]; 8052 u8 reserved_at_8[0x18]; 8053 8054 u8 syndrome[0x20]; 8055 8056 u8 reserved_at_40[0x40]; 8057 }; 8058 8059 struct mlx5_ifc_destroy_rmp_in_bits { 8060 u8 opcode[0x10]; 8061 u8 uid[0x10]; 8062 8063 u8 reserved_at_20[0x10]; 8064 u8 op_mod[0x10]; 8065 8066 u8 reserved_at_40[0x8]; 8067 u8 rmpn[0x18]; 8068 8069 u8 reserved_at_60[0x20]; 8070 }; 8071 8072 struct mlx5_ifc_destroy_qp_out_bits { 8073 u8 status[0x8]; 8074 u8 reserved_at_8[0x18]; 8075 8076 u8 syndrome[0x20]; 8077 8078 u8 reserved_at_40[0x40]; 8079 }; 8080 8081 struct mlx5_ifc_destroy_qp_in_bits { 8082 u8 opcode[0x10]; 8083 u8 uid[0x10]; 8084 8085 u8 reserved_at_20[0x10]; 8086 u8 op_mod[0x10]; 8087 8088 u8 reserved_at_40[0x8]; 8089 u8 qpn[0x18]; 8090 8091 u8 reserved_at_60[0x20]; 8092 }; 8093 8094 struct mlx5_ifc_destroy_psv_out_bits { 8095 u8 status[0x8]; 8096 u8 reserved_at_8[0x18]; 8097 8098 u8 syndrome[0x20]; 8099 8100 u8 reserved_at_40[0x40]; 8101 }; 8102 8103 struct mlx5_ifc_destroy_psv_in_bits { 8104 u8 opcode[0x10]; 8105 u8 reserved_at_10[0x10]; 8106 8107 u8 reserved_at_20[0x10]; 8108 u8 op_mod[0x10]; 8109 8110 u8 reserved_at_40[0x8]; 8111 u8 psvn[0x18]; 8112 8113 u8 reserved_at_60[0x20]; 8114 }; 8115 8116 struct mlx5_ifc_destroy_mkey_out_bits { 8117 u8 status[0x8]; 8118 u8 reserved_at_8[0x18]; 8119 8120 u8 syndrome[0x20]; 8121 8122 u8 reserved_at_40[0x40]; 8123 }; 8124 8125 struct mlx5_ifc_destroy_mkey_in_bits { 8126 u8 opcode[0x10]; 8127 u8 uid[0x10]; 8128 8129 u8 reserved_at_20[0x10]; 8130 u8 op_mod[0x10]; 8131 8132 u8 reserved_at_40[0x8]; 8133 u8 mkey_index[0x18]; 8134 8135 u8 reserved_at_60[0x20]; 8136 }; 8137 8138 struct mlx5_ifc_destroy_flow_table_out_bits { 8139 u8 status[0x8]; 8140 u8 reserved_at_8[0x18]; 8141 8142 u8 syndrome[0x20]; 8143 8144 u8 reserved_at_40[0x40]; 8145 }; 8146 8147 struct mlx5_ifc_destroy_flow_table_in_bits { 8148 u8 opcode[0x10]; 8149 u8 reserved_at_10[0x10]; 8150 8151 u8 reserved_at_20[0x10]; 8152 u8 op_mod[0x10]; 8153 8154 u8 other_vport[0x1]; 8155 u8 reserved_at_41[0xf]; 8156 u8 vport_number[0x10]; 8157 8158 u8 reserved_at_60[0x20]; 8159 8160 u8 table_type[0x8]; 8161 u8 reserved_at_88[0x18]; 8162 8163 u8 reserved_at_a0[0x8]; 8164 u8 table_id[0x18]; 8165 8166 u8 reserved_at_c0[0x140]; 8167 }; 8168 8169 struct mlx5_ifc_destroy_flow_group_out_bits { 8170 u8 status[0x8]; 8171 u8 reserved_at_8[0x18]; 8172 8173 u8 syndrome[0x20]; 8174 8175 u8 reserved_at_40[0x40]; 8176 }; 8177 8178 struct mlx5_ifc_destroy_flow_group_in_bits { 8179 u8 opcode[0x10]; 8180 u8 reserved_at_10[0x10]; 8181 8182 u8 reserved_at_20[0x10]; 8183 u8 op_mod[0x10]; 8184 8185 u8 other_vport[0x1]; 8186 u8 reserved_at_41[0xf]; 8187 u8 vport_number[0x10]; 8188 8189 u8 reserved_at_60[0x20]; 8190 8191 u8 table_type[0x8]; 8192 u8 reserved_at_88[0x18]; 8193 8194 u8 reserved_at_a0[0x8]; 8195 u8 table_id[0x18]; 8196 8197 u8 group_id[0x20]; 8198 8199 u8 reserved_at_e0[0x120]; 8200 }; 8201 8202 struct mlx5_ifc_destroy_eq_out_bits { 8203 u8 status[0x8]; 8204 u8 reserved_at_8[0x18]; 8205 8206 u8 syndrome[0x20]; 8207 8208 u8 reserved_at_40[0x40]; 8209 }; 8210 8211 struct mlx5_ifc_destroy_eq_in_bits { 8212 u8 opcode[0x10]; 8213 u8 reserved_at_10[0x10]; 8214 8215 u8 reserved_at_20[0x10]; 8216 u8 op_mod[0x10]; 8217 8218 u8 reserved_at_40[0x18]; 8219 u8 eq_number[0x8]; 8220 8221 u8 reserved_at_60[0x20]; 8222 }; 8223 8224 struct mlx5_ifc_destroy_dct_out_bits { 8225 u8 status[0x8]; 8226 u8 reserved_at_8[0x18]; 8227 8228 u8 syndrome[0x20]; 8229 8230 u8 reserved_at_40[0x40]; 8231 }; 8232 8233 struct mlx5_ifc_destroy_dct_in_bits { 8234 u8 opcode[0x10]; 8235 u8 uid[0x10]; 8236 8237 u8 reserved_at_20[0x10]; 8238 u8 op_mod[0x10]; 8239 8240 u8 reserved_at_40[0x8]; 8241 u8 dctn[0x18]; 8242 8243 u8 reserved_at_60[0x20]; 8244 }; 8245 8246 struct mlx5_ifc_destroy_cq_out_bits { 8247 u8 status[0x8]; 8248 u8 reserved_at_8[0x18]; 8249 8250 u8 syndrome[0x20]; 8251 8252 u8 reserved_at_40[0x40]; 8253 }; 8254 8255 struct mlx5_ifc_destroy_cq_in_bits { 8256 u8 opcode[0x10]; 8257 u8 uid[0x10]; 8258 8259 u8 reserved_at_20[0x10]; 8260 u8 op_mod[0x10]; 8261 8262 u8 reserved_at_40[0x8]; 8263 u8 cqn[0x18]; 8264 8265 u8 reserved_at_60[0x20]; 8266 }; 8267 8268 struct mlx5_ifc_delete_vxlan_udp_dport_out_bits { 8269 u8 status[0x8]; 8270 u8 reserved_at_8[0x18]; 8271 8272 u8 syndrome[0x20]; 8273 8274 u8 reserved_at_40[0x40]; 8275 }; 8276 8277 struct mlx5_ifc_delete_vxlan_udp_dport_in_bits { 8278 u8 opcode[0x10]; 8279 u8 reserved_at_10[0x10]; 8280 8281 u8 reserved_at_20[0x10]; 8282 u8 op_mod[0x10]; 8283 8284 u8 reserved_at_40[0x20]; 8285 8286 u8 reserved_at_60[0x10]; 8287 u8 vxlan_udp_port[0x10]; 8288 }; 8289 8290 struct mlx5_ifc_delete_l2_table_entry_out_bits { 8291 u8 status[0x8]; 8292 u8 reserved_at_8[0x18]; 8293 8294 u8 syndrome[0x20]; 8295 8296 u8 reserved_at_40[0x40]; 8297 }; 8298 8299 struct mlx5_ifc_delete_l2_table_entry_in_bits { 8300 u8 opcode[0x10]; 8301 u8 reserved_at_10[0x10]; 8302 8303 u8 reserved_at_20[0x10]; 8304 u8 op_mod[0x10]; 8305 8306 u8 reserved_at_40[0x60]; 8307 8308 u8 reserved_at_a0[0x8]; 8309 u8 table_index[0x18]; 8310 8311 u8 reserved_at_c0[0x140]; 8312 }; 8313 8314 struct mlx5_ifc_delete_fte_out_bits { 8315 u8 status[0x8]; 8316 u8 reserved_at_8[0x18]; 8317 8318 u8 syndrome[0x20]; 8319 8320 u8 reserved_at_40[0x40]; 8321 }; 8322 8323 struct mlx5_ifc_delete_fte_in_bits { 8324 u8 opcode[0x10]; 8325 u8 reserved_at_10[0x10]; 8326 8327 u8 reserved_at_20[0x10]; 8328 u8 op_mod[0x10]; 8329 8330 u8 other_vport[0x1]; 8331 u8 reserved_at_41[0xf]; 8332 u8 vport_number[0x10]; 8333 8334 u8 reserved_at_60[0x20]; 8335 8336 u8 table_type[0x8]; 8337 u8 reserved_at_88[0x18]; 8338 8339 u8 reserved_at_a0[0x8]; 8340 u8 table_id[0x18]; 8341 8342 u8 reserved_at_c0[0x40]; 8343 8344 u8 flow_index[0x20]; 8345 8346 u8 reserved_at_120[0xe0]; 8347 }; 8348 8349 struct mlx5_ifc_dealloc_xrcd_out_bits { 8350 u8 status[0x8]; 8351 u8 reserved_at_8[0x18]; 8352 8353 u8 syndrome[0x20]; 8354 8355 u8 reserved_at_40[0x40]; 8356 }; 8357 8358 struct mlx5_ifc_dealloc_xrcd_in_bits { 8359 u8 opcode[0x10]; 8360 u8 uid[0x10]; 8361 8362 u8 reserved_at_20[0x10]; 8363 u8 op_mod[0x10]; 8364 8365 u8 reserved_at_40[0x8]; 8366 u8 xrcd[0x18]; 8367 8368 u8 reserved_at_60[0x20]; 8369 }; 8370 8371 struct mlx5_ifc_dealloc_uar_out_bits { 8372 u8 status[0x8]; 8373 u8 reserved_at_8[0x18]; 8374 8375 u8 syndrome[0x20]; 8376 8377 u8 reserved_at_40[0x40]; 8378 }; 8379 8380 struct mlx5_ifc_dealloc_uar_in_bits { 8381 u8 opcode[0x10]; 8382 u8 uid[0x10]; 8383 8384 u8 reserved_at_20[0x10]; 8385 u8 op_mod[0x10]; 8386 8387 u8 reserved_at_40[0x8]; 8388 u8 uar[0x18]; 8389 8390 u8 reserved_at_60[0x20]; 8391 }; 8392 8393 struct mlx5_ifc_dealloc_transport_domain_out_bits { 8394 u8 status[0x8]; 8395 u8 reserved_at_8[0x18]; 8396 8397 u8 syndrome[0x20]; 8398 8399 u8 reserved_at_40[0x40]; 8400 }; 8401 8402 struct mlx5_ifc_dealloc_transport_domain_in_bits { 8403 u8 opcode[0x10]; 8404 u8 uid[0x10]; 8405 8406 u8 reserved_at_20[0x10]; 8407 u8 op_mod[0x10]; 8408 8409 u8 reserved_at_40[0x8]; 8410 u8 transport_domain[0x18]; 8411 8412 u8 reserved_at_60[0x20]; 8413 }; 8414 8415 struct mlx5_ifc_dealloc_q_counter_out_bits { 8416 u8 status[0x8]; 8417 u8 reserved_at_8[0x18]; 8418 8419 u8 syndrome[0x20]; 8420 8421 u8 reserved_at_40[0x40]; 8422 }; 8423 8424 struct mlx5_ifc_dealloc_q_counter_in_bits { 8425 u8 opcode[0x10]; 8426 u8 reserved_at_10[0x10]; 8427 8428 u8 reserved_at_20[0x10]; 8429 u8 op_mod[0x10]; 8430 8431 u8 reserved_at_40[0x18]; 8432 u8 counter_set_id[0x8]; 8433 8434 u8 reserved_at_60[0x20]; 8435 }; 8436 8437 struct mlx5_ifc_dealloc_pd_out_bits { 8438 u8 status[0x8]; 8439 u8 reserved_at_8[0x18]; 8440 8441 u8 syndrome[0x20]; 8442 8443 u8 reserved_at_40[0x40]; 8444 }; 8445 8446 struct mlx5_ifc_dealloc_pd_in_bits { 8447 u8 opcode[0x10]; 8448 u8 uid[0x10]; 8449 8450 u8 reserved_at_20[0x10]; 8451 u8 op_mod[0x10]; 8452 8453 u8 reserved_at_40[0x8]; 8454 u8 pd[0x18]; 8455 8456 u8 reserved_at_60[0x20]; 8457 }; 8458 8459 struct mlx5_ifc_dealloc_flow_counter_out_bits { 8460 u8 status[0x8]; 8461 u8 reserved_at_8[0x18]; 8462 8463 u8 syndrome[0x20]; 8464 8465 u8 reserved_at_40[0x40]; 8466 }; 8467 8468 struct mlx5_ifc_dealloc_flow_counter_in_bits { 8469 u8 opcode[0x10]; 8470 u8 reserved_at_10[0x10]; 8471 8472 u8 reserved_at_20[0x10]; 8473 u8 op_mod[0x10]; 8474 8475 u8 flow_counter_id[0x20]; 8476 8477 u8 reserved_at_60[0x20]; 8478 }; 8479 8480 struct mlx5_ifc_create_xrq_out_bits { 8481 u8 status[0x8]; 8482 u8 reserved_at_8[0x18]; 8483 8484 u8 syndrome[0x20]; 8485 8486 u8 reserved_at_40[0x8]; 8487 u8 xrqn[0x18]; 8488 8489 u8 reserved_at_60[0x20]; 8490 }; 8491 8492 struct mlx5_ifc_create_xrq_in_bits { 8493 u8 opcode[0x10]; 8494 u8 uid[0x10]; 8495 8496 u8 reserved_at_20[0x10]; 8497 u8 op_mod[0x10]; 8498 8499 u8 reserved_at_40[0x40]; 8500 8501 struct mlx5_ifc_xrqc_bits xrq_context; 8502 }; 8503 8504 struct mlx5_ifc_create_xrc_srq_out_bits { 8505 u8 status[0x8]; 8506 u8 reserved_at_8[0x18]; 8507 8508 u8 syndrome[0x20]; 8509 8510 u8 reserved_at_40[0x8]; 8511 u8 xrc_srqn[0x18]; 8512 8513 u8 reserved_at_60[0x20]; 8514 }; 8515 8516 struct mlx5_ifc_create_xrc_srq_in_bits { 8517 u8 opcode[0x10]; 8518 u8 uid[0x10]; 8519 8520 u8 reserved_at_20[0x10]; 8521 u8 op_mod[0x10]; 8522 8523 u8 reserved_at_40[0x40]; 8524 8525 struct mlx5_ifc_xrc_srqc_bits xrc_srq_context_entry; 8526 8527 u8 reserved_at_280[0x60]; 8528 8529 u8 xrc_srq_umem_valid[0x1]; 8530 u8 reserved_at_2e1[0x1f]; 8531 8532 u8 reserved_at_300[0x580]; 8533 8534 u8 pas[][0x40]; 8535 }; 8536 8537 struct mlx5_ifc_create_tis_out_bits { 8538 u8 status[0x8]; 8539 u8 reserved_at_8[0x18]; 8540 8541 u8 syndrome[0x20]; 8542 8543 u8 reserved_at_40[0x8]; 8544 u8 tisn[0x18]; 8545 8546 u8 reserved_at_60[0x20]; 8547 }; 8548 8549 struct mlx5_ifc_create_tis_in_bits { 8550 u8 opcode[0x10]; 8551 u8 uid[0x10]; 8552 8553 u8 reserved_at_20[0x10]; 8554 u8 op_mod[0x10]; 8555 8556 u8 reserved_at_40[0xc0]; 8557 8558 struct mlx5_ifc_tisc_bits ctx; 8559 }; 8560 8561 struct mlx5_ifc_create_tir_out_bits { 8562 u8 status[0x8]; 8563 u8 icm_address_63_40[0x18]; 8564 8565 u8 syndrome[0x20]; 8566 8567 u8 icm_address_39_32[0x8]; 8568 u8 tirn[0x18]; 8569 8570 u8 icm_address_31_0[0x20]; 8571 }; 8572 8573 struct mlx5_ifc_create_tir_in_bits { 8574 u8 opcode[0x10]; 8575 u8 uid[0x10]; 8576 8577 u8 reserved_at_20[0x10]; 8578 u8 op_mod[0x10]; 8579 8580 u8 reserved_at_40[0xc0]; 8581 8582 struct mlx5_ifc_tirc_bits ctx; 8583 }; 8584 8585 struct mlx5_ifc_create_srq_out_bits { 8586 u8 status[0x8]; 8587 u8 reserved_at_8[0x18]; 8588 8589 u8 syndrome[0x20]; 8590 8591 u8 reserved_at_40[0x8]; 8592 u8 srqn[0x18]; 8593 8594 u8 reserved_at_60[0x20]; 8595 }; 8596 8597 struct mlx5_ifc_create_srq_in_bits { 8598 u8 opcode[0x10]; 8599 u8 uid[0x10]; 8600 8601 u8 reserved_at_20[0x10]; 8602 u8 op_mod[0x10]; 8603 8604 u8 reserved_at_40[0x40]; 8605 8606 struct mlx5_ifc_srqc_bits srq_context_entry; 8607 8608 u8 reserved_at_280[0x600]; 8609 8610 u8 pas[][0x40]; 8611 }; 8612 8613 struct mlx5_ifc_create_sq_out_bits { 8614 u8 status[0x8]; 8615 u8 reserved_at_8[0x18]; 8616 8617 u8 syndrome[0x20]; 8618 8619 u8 reserved_at_40[0x8]; 8620 u8 sqn[0x18]; 8621 8622 u8 reserved_at_60[0x20]; 8623 }; 8624 8625 struct mlx5_ifc_create_sq_in_bits { 8626 u8 opcode[0x10]; 8627 u8 uid[0x10]; 8628 8629 u8 reserved_at_20[0x10]; 8630 u8 op_mod[0x10]; 8631 8632 u8 reserved_at_40[0xc0]; 8633 8634 struct mlx5_ifc_sqc_bits ctx; 8635 }; 8636 8637 struct mlx5_ifc_create_scheduling_element_out_bits { 8638 u8 status[0x8]; 8639 u8 reserved_at_8[0x18]; 8640 8641 u8 syndrome[0x20]; 8642 8643 u8 reserved_at_40[0x40]; 8644 8645 u8 scheduling_element_id[0x20]; 8646 8647 u8 reserved_at_a0[0x160]; 8648 }; 8649 8650 struct mlx5_ifc_create_scheduling_element_in_bits { 8651 u8 opcode[0x10]; 8652 u8 reserved_at_10[0x10]; 8653 8654 u8 reserved_at_20[0x10]; 8655 u8 op_mod[0x10]; 8656 8657 u8 scheduling_hierarchy[0x8]; 8658 u8 reserved_at_48[0x18]; 8659 8660 u8 reserved_at_60[0xa0]; 8661 8662 struct mlx5_ifc_scheduling_context_bits scheduling_context; 8663 8664 u8 reserved_at_300[0x100]; 8665 }; 8666 8667 struct mlx5_ifc_create_rqt_out_bits { 8668 u8 status[0x8]; 8669 u8 reserved_at_8[0x18]; 8670 8671 u8 syndrome[0x20]; 8672 8673 u8 reserved_at_40[0x8]; 8674 u8 rqtn[0x18]; 8675 8676 u8 reserved_at_60[0x20]; 8677 }; 8678 8679 struct mlx5_ifc_create_rqt_in_bits { 8680 u8 opcode[0x10]; 8681 u8 uid[0x10]; 8682 8683 u8 reserved_at_20[0x10]; 8684 u8 op_mod[0x10]; 8685 8686 u8 reserved_at_40[0xc0]; 8687 8688 struct mlx5_ifc_rqtc_bits rqt_context; 8689 }; 8690 8691 struct mlx5_ifc_create_rq_out_bits { 8692 u8 status[0x8]; 8693 u8 reserved_at_8[0x18]; 8694 8695 u8 syndrome[0x20]; 8696 8697 u8 reserved_at_40[0x8]; 8698 u8 rqn[0x18]; 8699 8700 u8 reserved_at_60[0x20]; 8701 }; 8702 8703 struct mlx5_ifc_create_rq_in_bits { 8704 u8 opcode[0x10]; 8705 u8 uid[0x10]; 8706 8707 u8 reserved_at_20[0x10]; 8708 u8 op_mod[0x10]; 8709 8710 u8 reserved_at_40[0xc0]; 8711 8712 struct mlx5_ifc_rqc_bits ctx; 8713 }; 8714 8715 struct mlx5_ifc_create_rmp_out_bits { 8716 u8 status[0x8]; 8717 u8 reserved_at_8[0x18]; 8718 8719 u8 syndrome[0x20]; 8720 8721 u8 reserved_at_40[0x8]; 8722 u8 rmpn[0x18]; 8723 8724 u8 reserved_at_60[0x20]; 8725 }; 8726 8727 struct mlx5_ifc_create_rmp_in_bits { 8728 u8 opcode[0x10]; 8729 u8 uid[0x10]; 8730 8731 u8 reserved_at_20[0x10]; 8732 u8 op_mod[0x10]; 8733 8734 u8 reserved_at_40[0xc0]; 8735 8736 struct mlx5_ifc_rmpc_bits ctx; 8737 }; 8738 8739 struct mlx5_ifc_create_qp_out_bits { 8740 u8 status[0x8]; 8741 u8 reserved_at_8[0x18]; 8742 8743 u8 syndrome[0x20]; 8744 8745 u8 reserved_at_40[0x8]; 8746 u8 qpn[0x18]; 8747 8748 u8 ece[0x20]; 8749 }; 8750 8751 struct mlx5_ifc_create_qp_in_bits { 8752 u8 opcode[0x10]; 8753 u8 uid[0x10]; 8754 8755 u8 reserved_at_20[0x10]; 8756 u8 op_mod[0x10]; 8757 8758 u8 qpc_ext[0x1]; 8759 u8 reserved_at_41[0x7]; 8760 u8 input_qpn[0x18]; 8761 8762 u8 reserved_at_60[0x20]; 8763 u8 opt_param_mask[0x20]; 8764 8765 u8 ece[0x20]; 8766 8767 struct mlx5_ifc_qpc_bits qpc; 8768 8769 u8 reserved_at_800[0x60]; 8770 8771 u8 wq_umem_valid[0x1]; 8772 u8 reserved_at_861[0x1f]; 8773 8774 u8 pas[][0x40]; 8775 }; 8776 8777 struct mlx5_ifc_create_psv_out_bits { 8778 u8 status[0x8]; 8779 u8 reserved_at_8[0x18]; 8780 8781 u8 syndrome[0x20]; 8782 8783 u8 reserved_at_40[0x40]; 8784 8785 u8 reserved_at_80[0x8]; 8786 u8 psv0_index[0x18]; 8787 8788 u8 reserved_at_a0[0x8]; 8789 u8 psv1_index[0x18]; 8790 8791 u8 reserved_at_c0[0x8]; 8792 u8 psv2_index[0x18]; 8793 8794 u8 reserved_at_e0[0x8]; 8795 u8 psv3_index[0x18]; 8796 }; 8797 8798 struct mlx5_ifc_create_psv_in_bits { 8799 u8 opcode[0x10]; 8800 u8 reserved_at_10[0x10]; 8801 8802 u8 reserved_at_20[0x10]; 8803 u8 op_mod[0x10]; 8804 8805 u8 num_psv[0x4]; 8806 u8 reserved_at_44[0x4]; 8807 u8 pd[0x18]; 8808 8809 u8 reserved_at_60[0x20]; 8810 }; 8811 8812 struct mlx5_ifc_create_mkey_out_bits { 8813 u8 status[0x8]; 8814 u8 reserved_at_8[0x18]; 8815 8816 u8 syndrome[0x20]; 8817 8818 u8 reserved_at_40[0x8]; 8819 u8 mkey_index[0x18]; 8820 8821 u8 reserved_at_60[0x20]; 8822 }; 8823 8824 struct mlx5_ifc_create_mkey_in_bits { 8825 u8 opcode[0x10]; 8826 u8 uid[0x10]; 8827 8828 u8 reserved_at_20[0x10]; 8829 u8 op_mod[0x10]; 8830 8831 u8 reserved_at_40[0x20]; 8832 8833 u8 pg_access[0x1]; 8834 u8 mkey_umem_valid[0x1]; 8835 u8 reserved_at_62[0x1e]; 8836 8837 struct mlx5_ifc_mkc_bits memory_key_mkey_entry; 8838 8839 u8 reserved_at_280[0x80]; 8840 8841 u8 translations_octword_actual_size[0x20]; 8842 8843 u8 reserved_at_320[0x560]; 8844 8845 u8 klm_pas_mtt[][0x20]; 8846 }; 8847 8848 enum { 8849 MLX5_FLOW_TABLE_TYPE_NIC_RX = 0x0, 8850 MLX5_FLOW_TABLE_TYPE_NIC_TX = 0x1, 8851 MLX5_FLOW_TABLE_TYPE_ESW_EGRESS_ACL = 0x2, 8852 MLX5_FLOW_TABLE_TYPE_ESW_INGRESS_ACL = 0x3, 8853 MLX5_FLOW_TABLE_TYPE_FDB = 0X4, 8854 MLX5_FLOW_TABLE_TYPE_SNIFFER_RX = 0X5, 8855 MLX5_FLOW_TABLE_TYPE_SNIFFER_TX = 0X6, 8856 }; 8857 8858 struct mlx5_ifc_create_flow_table_out_bits { 8859 u8 status[0x8]; 8860 u8 icm_address_63_40[0x18]; 8861 8862 u8 syndrome[0x20]; 8863 8864 u8 icm_address_39_32[0x8]; 8865 u8 table_id[0x18]; 8866 8867 u8 icm_address_31_0[0x20]; 8868 }; 8869 8870 struct mlx5_ifc_create_flow_table_in_bits { 8871 u8 opcode[0x10]; 8872 u8 uid[0x10]; 8873 8874 u8 reserved_at_20[0x10]; 8875 u8 op_mod[0x10]; 8876 8877 u8 other_vport[0x1]; 8878 u8 reserved_at_41[0xf]; 8879 u8 vport_number[0x10]; 8880 8881 u8 reserved_at_60[0x20]; 8882 8883 u8 table_type[0x8]; 8884 u8 reserved_at_88[0x18]; 8885 8886 u8 reserved_at_a0[0x20]; 8887 8888 struct mlx5_ifc_flow_table_context_bits flow_table_context; 8889 }; 8890 8891 struct mlx5_ifc_create_flow_group_out_bits { 8892 u8 status[0x8]; 8893 u8 reserved_at_8[0x18]; 8894 8895 u8 syndrome[0x20]; 8896 8897 u8 reserved_at_40[0x8]; 8898 u8 group_id[0x18]; 8899 8900 u8 reserved_at_60[0x20]; 8901 }; 8902 8903 enum { 8904 MLX5_CREATE_FLOW_GROUP_IN_GROUP_TYPE_TCAM_SUBTABLE = 0x0, 8905 MLX5_CREATE_FLOW_GROUP_IN_GROUP_TYPE_HASH_SPLIT = 0x1, 8906 }; 8907 8908 enum { 8909 MLX5_CREATE_FLOW_GROUP_IN_MATCH_CRITERIA_ENABLE_OUTER_HEADERS = 0x0, 8910 MLX5_CREATE_FLOW_GROUP_IN_MATCH_CRITERIA_ENABLE_MISC_PARAMETERS = 0x1, 8911 MLX5_CREATE_FLOW_GROUP_IN_MATCH_CRITERIA_ENABLE_INNER_HEADERS = 0x2, 8912 MLX5_CREATE_FLOW_GROUP_IN_MATCH_CRITERIA_ENABLE_MISC_PARAMETERS_2 = 0x3, 8913 }; 8914 8915 struct mlx5_ifc_create_flow_group_in_bits { 8916 u8 opcode[0x10]; 8917 u8 reserved_at_10[0x10]; 8918 8919 u8 reserved_at_20[0x10]; 8920 u8 op_mod[0x10]; 8921 8922 u8 other_vport[0x1]; 8923 u8 reserved_at_41[0xf]; 8924 u8 vport_number[0x10]; 8925 8926 u8 reserved_at_60[0x20]; 8927 8928 u8 table_type[0x8]; 8929 u8 reserved_at_88[0x4]; 8930 u8 group_type[0x4]; 8931 u8 reserved_at_90[0x10]; 8932 8933 u8 reserved_at_a0[0x8]; 8934 u8 table_id[0x18]; 8935 8936 u8 source_eswitch_owner_vhca_id_valid[0x1]; 8937 8938 u8 reserved_at_c1[0x1f]; 8939 8940 u8 start_flow_index[0x20]; 8941 8942 u8 reserved_at_100[0x20]; 8943 8944 u8 end_flow_index[0x20]; 8945 8946 u8 reserved_at_140[0x10]; 8947 u8 match_definer_id[0x10]; 8948 8949 u8 reserved_at_160[0x80]; 8950 8951 u8 reserved_at_1e0[0x18]; 8952 u8 match_criteria_enable[0x8]; 8953 8954 struct mlx5_ifc_fte_match_param_bits match_criteria; 8955 8956 u8 reserved_at_1200[0xe00]; 8957 }; 8958 8959 struct mlx5_ifc_create_eq_out_bits { 8960 u8 status[0x8]; 8961 u8 reserved_at_8[0x18]; 8962 8963 u8 syndrome[0x20]; 8964 8965 u8 reserved_at_40[0x18]; 8966 u8 eq_number[0x8]; 8967 8968 u8 reserved_at_60[0x20]; 8969 }; 8970 8971 struct mlx5_ifc_create_eq_in_bits { 8972 u8 opcode[0x10]; 8973 u8 uid[0x10]; 8974 8975 u8 reserved_at_20[0x10]; 8976 u8 op_mod[0x10]; 8977 8978 u8 reserved_at_40[0x40]; 8979 8980 struct mlx5_ifc_eqc_bits eq_context_entry; 8981 8982 u8 reserved_at_280[0x40]; 8983 8984 u8 event_bitmask[4][0x40]; 8985 8986 u8 reserved_at_3c0[0x4c0]; 8987 8988 u8 pas[][0x40]; 8989 }; 8990 8991 struct mlx5_ifc_create_dct_out_bits { 8992 u8 status[0x8]; 8993 u8 reserved_at_8[0x18]; 8994 8995 u8 syndrome[0x20]; 8996 8997 u8 reserved_at_40[0x8]; 8998 u8 dctn[0x18]; 8999 9000 u8 ece[0x20]; 9001 }; 9002 9003 struct mlx5_ifc_create_dct_in_bits { 9004 u8 opcode[0x10]; 9005 u8 uid[0x10]; 9006 9007 u8 reserved_at_20[0x10]; 9008 u8 op_mod[0x10]; 9009 9010 u8 reserved_at_40[0x40]; 9011 9012 struct mlx5_ifc_dctc_bits dct_context_entry; 9013 9014 u8 reserved_at_280[0x180]; 9015 }; 9016 9017 struct mlx5_ifc_create_cq_out_bits { 9018 u8 status[0x8]; 9019 u8 reserved_at_8[0x18]; 9020 9021 u8 syndrome[0x20]; 9022 9023 u8 reserved_at_40[0x8]; 9024 u8 cqn[0x18]; 9025 9026 u8 reserved_at_60[0x20]; 9027 }; 9028 9029 struct mlx5_ifc_create_cq_in_bits { 9030 u8 opcode[0x10]; 9031 u8 uid[0x10]; 9032 9033 u8 reserved_at_20[0x10]; 9034 u8 op_mod[0x10]; 9035 9036 u8 reserved_at_40[0x40]; 9037 9038 struct mlx5_ifc_cqc_bits cq_context; 9039 9040 u8 reserved_at_280[0x60]; 9041 9042 u8 cq_umem_valid[0x1]; 9043 u8 reserved_at_2e1[0x59f]; 9044 9045 u8 pas[][0x40]; 9046 }; 9047 9048 struct mlx5_ifc_config_int_moderation_out_bits { 9049 u8 status[0x8]; 9050 u8 reserved_at_8[0x18]; 9051 9052 u8 syndrome[0x20]; 9053 9054 u8 reserved_at_40[0x4]; 9055 u8 min_delay[0xc]; 9056 u8 int_vector[0x10]; 9057 9058 u8 reserved_at_60[0x20]; 9059 }; 9060 9061 enum { 9062 MLX5_CONFIG_INT_MODERATION_IN_OP_MOD_WRITE = 0x0, 9063 MLX5_CONFIG_INT_MODERATION_IN_OP_MOD_READ = 0x1, 9064 }; 9065 9066 struct mlx5_ifc_config_int_moderation_in_bits { 9067 u8 opcode[0x10]; 9068 u8 reserved_at_10[0x10]; 9069 9070 u8 reserved_at_20[0x10]; 9071 u8 op_mod[0x10]; 9072 9073 u8 reserved_at_40[0x4]; 9074 u8 min_delay[0xc]; 9075 u8 int_vector[0x10]; 9076 9077 u8 reserved_at_60[0x20]; 9078 }; 9079 9080 struct mlx5_ifc_attach_to_mcg_out_bits { 9081 u8 status[0x8]; 9082 u8 reserved_at_8[0x18]; 9083 9084 u8 syndrome[0x20]; 9085 9086 u8 reserved_at_40[0x40]; 9087 }; 9088 9089 struct mlx5_ifc_attach_to_mcg_in_bits { 9090 u8 opcode[0x10]; 9091 u8 uid[0x10]; 9092 9093 u8 reserved_at_20[0x10]; 9094 u8 op_mod[0x10]; 9095 9096 u8 reserved_at_40[0x8]; 9097 u8 qpn[0x18]; 9098 9099 u8 reserved_at_60[0x20]; 9100 9101 u8 multicast_gid[16][0x8]; 9102 }; 9103 9104 struct mlx5_ifc_arm_xrq_out_bits { 9105 u8 status[0x8]; 9106 u8 reserved_at_8[0x18]; 9107 9108 u8 syndrome[0x20]; 9109 9110 u8 reserved_at_40[0x40]; 9111 }; 9112 9113 struct mlx5_ifc_arm_xrq_in_bits { 9114 u8 opcode[0x10]; 9115 u8 reserved_at_10[0x10]; 9116 9117 u8 reserved_at_20[0x10]; 9118 u8 op_mod[0x10]; 9119 9120 u8 reserved_at_40[0x8]; 9121 u8 xrqn[0x18]; 9122 9123 u8 reserved_at_60[0x10]; 9124 u8 lwm[0x10]; 9125 }; 9126 9127 struct mlx5_ifc_arm_xrc_srq_out_bits { 9128 u8 status[0x8]; 9129 u8 reserved_at_8[0x18]; 9130 9131 u8 syndrome[0x20]; 9132 9133 u8 reserved_at_40[0x40]; 9134 }; 9135 9136 enum { 9137 MLX5_ARM_XRC_SRQ_IN_OP_MOD_XRC_SRQ = 0x1, 9138 }; 9139 9140 struct mlx5_ifc_arm_xrc_srq_in_bits { 9141 u8 opcode[0x10]; 9142 u8 uid[0x10]; 9143 9144 u8 reserved_at_20[0x10]; 9145 u8 op_mod[0x10]; 9146 9147 u8 reserved_at_40[0x8]; 9148 u8 xrc_srqn[0x18]; 9149 9150 u8 reserved_at_60[0x10]; 9151 u8 lwm[0x10]; 9152 }; 9153 9154 struct mlx5_ifc_arm_rq_out_bits { 9155 u8 status[0x8]; 9156 u8 reserved_at_8[0x18]; 9157 9158 u8 syndrome[0x20]; 9159 9160 u8 reserved_at_40[0x40]; 9161 }; 9162 9163 enum { 9164 MLX5_ARM_RQ_IN_OP_MOD_SRQ = 0x1, 9165 MLX5_ARM_RQ_IN_OP_MOD_XRQ = 0x2, 9166 }; 9167 9168 struct mlx5_ifc_arm_rq_in_bits { 9169 u8 opcode[0x10]; 9170 u8 uid[0x10]; 9171 9172 u8 reserved_at_20[0x10]; 9173 u8 op_mod[0x10]; 9174 9175 u8 reserved_at_40[0x8]; 9176 u8 srq_number[0x18]; 9177 9178 u8 reserved_at_60[0x10]; 9179 u8 lwm[0x10]; 9180 }; 9181 9182 struct mlx5_ifc_arm_dct_out_bits { 9183 u8 status[0x8]; 9184 u8 reserved_at_8[0x18]; 9185 9186 u8 syndrome[0x20]; 9187 9188 u8 reserved_at_40[0x40]; 9189 }; 9190 9191 struct mlx5_ifc_arm_dct_in_bits { 9192 u8 opcode[0x10]; 9193 u8 reserved_at_10[0x10]; 9194 9195 u8 reserved_at_20[0x10]; 9196 u8 op_mod[0x10]; 9197 9198 u8 reserved_at_40[0x8]; 9199 u8 dct_number[0x18]; 9200 9201 u8 reserved_at_60[0x20]; 9202 }; 9203 9204 struct mlx5_ifc_alloc_xrcd_out_bits { 9205 u8 status[0x8]; 9206 u8 reserved_at_8[0x18]; 9207 9208 u8 syndrome[0x20]; 9209 9210 u8 reserved_at_40[0x8]; 9211 u8 xrcd[0x18]; 9212 9213 u8 reserved_at_60[0x20]; 9214 }; 9215 9216 struct mlx5_ifc_alloc_xrcd_in_bits { 9217 u8 opcode[0x10]; 9218 u8 uid[0x10]; 9219 9220 u8 reserved_at_20[0x10]; 9221 u8 op_mod[0x10]; 9222 9223 u8 reserved_at_40[0x40]; 9224 }; 9225 9226 struct mlx5_ifc_alloc_uar_out_bits { 9227 u8 status[0x8]; 9228 u8 reserved_at_8[0x18]; 9229 9230 u8 syndrome[0x20]; 9231 9232 u8 reserved_at_40[0x8]; 9233 u8 uar[0x18]; 9234 9235 u8 reserved_at_60[0x20]; 9236 }; 9237 9238 struct mlx5_ifc_alloc_uar_in_bits { 9239 u8 opcode[0x10]; 9240 u8 uid[0x10]; 9241 9242 u8 reserved_at_20[0x10]; 9243 u8 op_mod[0x10]; 9244 9245 u8 reserved_at_40[0x40]; 9246 }; 9247 9248 struct mlx5_ifc_alloc_transport_domain_out_bits { 9249 u8 status[0x8]; 9250 u8 reserved_at_8[0x18]; 9251 9252 u8 syndrome[0x20]; 9253 9254 u8 reserved_at_40[0x8]; 9255 u8 transport_domain[0x18]; 9256 9257 u8 reserved_at_60[0x20]; 9258 }; 9259 9260 struct mlx5_ifc_alloc_transport_domain_in_bits { 9261 u8 opcode[0x10]; 9262 u8 uid[0x10]; 9263 9264 u8 reserved_at_20[0x10]; 9265 u8 op_mod[0x10]; 9266 9267 u8 reserved_at_40[0x40]; 9268 }; 9269 9270 struct mlx5_ifc_alloc_q_counter_out_bits { 9271 u8 status[0x8]; 9272 u8 reserved_at_8[0x18]; 9273 9274 u8 syndrome[0x20]; 9275 9276 u8 reserved_at_40[0x18]; 9277 u8 counter_set_id[0x8]; 9278 9279 u8 reserved_at_60[0x20]; 9280 }; 9281 9282 struct mlx5_ifc_alloc_q_counter_in_bits { 9283 u8 opcode[0x10]; 9284 u8 uid[0x10]; 9285 9286 u8 reserved_at_20[0x10]; 9287 u8 op_mod[0x10]; 9288 9289 u8 reserved_at_40[0x40]; 9290 }; 9291 9292 struct mlx5_ifc_alloc_pd_out_bits { 9293 u8 status[0x8]; 9294 u8 reserved_at_8[0x18]; 9295 9296 u8 syndrome[0x20]; 9297 9298 u8 reserved_at_40[0x8]; 9299 u8 pd[0x18]; 9300 9301 u8 reserved_at_60[0x20]; 9302 }; 9303 9304 struct mlx5_ifc_alloc_pd_in_bits { 9305 u8 opcode[0x10]; 9306 u8 uid[0x10]; 9307 9308 u8 reserved_at_20[0x10]; 9309 u8 op_mod[0x10]; 9310 9311 u8 reserved_at_40[0x40]; 9312 }; 9313 9314 struct mlx5_ifc_alloc_flow_counter_out_bits { 9315 u8 status[0x8]; 9316 u8 reserved_at_8[0x18]; 9317 9318 u8 syndrome[0x20]; 9319 9320 u8 flow_counter_id[0x20]; 9321 9322 u8 reserved_at_60[0x20]; 9323 }; 9324 9325 struct mlx5_ifc_alloc_flow_counter_in_bits { 9326 u8 opcode[0x10]; 9327 u8 reserved_at_10[0x10]; 9328 9329 u8 reserved_at_20[0x10]; 9330 u8 op_mod[0x10]; 9331 9332 u8 reserved_at_40[0x33]; 9333 u8 flow_counter_bulk_log_size[0x5]; 9334 u8 flow_counter_bulk[0x8]; 9335 }; 9336 9337 struct mlx5_ifc_add_vxlan_udp_dport_out_bits { 9338 u8 status[0x8]; 9339 u8 reserved_at_8[0x18]; 9340 9341 u8 syndrome[0x20]; 9342 9343 u8 reserved_at_40[0x40]; 9344 }; 9345 9346 struct mlx5_ifc_add_vxlan_udp_dport_in_bits { 9347 u8 opcode[0x10]; 9348 u8 reserved_at_10[0x10]; 9349 9350 u8 reserved_at_20[0x10]; 9351 u8 op_mod[0x10]; 9352 9353 u8 reserved_at_40[0x20]; 9354 9355 u8 reserved_at_60[0x10]; 9356 u8 vxlan_udp_port[0x10]; 9357 }; 9358 9359 struct mlx5_ifc_set_pp_rate_limit_out_bits { 9360 u8 status[0x8]; 9361 u8 reserved_at_8[0x18]; 9362 9363 u8 syndrome[0x20]; 9364 9365 u8 reserved_at_40[0x40]; 9366 }; 9367 9368 struct mlx5_ifc_set_pp_rate_limit_context_bits { 9369 u8 rate_limit[0x20]; 9370 9371 u8 burst_upper_bound[0x20]; 9372 9373 u8 reserved_at_40[0x10]; 9374 u8 typical_packet_size[0x10]; 9375 9376 u8 reserved_at_60[0x120]; 9377 }; 9378 9379 struct mlx5_ifc_set_pp_rate_limit_in_bits { 9380 u8 opcode[0x10]; 9381 u8 uid[0x10]; 9382 9383 u8 reserved_at_20[0x10]; 9384 u8 op_mod[0x10]; 9385 9386 u8 reserved_at_40[0x10]; 9387 u8 rate_limit_index[0x10]; 9388 9389 u8 reserved_at_60[0x20]; 9390 9391 struct mlx5_ifc_set_pp_rate_limit_context_bits ctx; 9392 }; 9393 9394 struct mlx5_ifc_access_register_out_bits { 9395 u8 status[0x8]; 9396 u8 reserved_at_8[0x18]; 9397 9398 u8 syndrome[0x20]; 9399 9400 u8 reserved_at_40[0x40]; 9401 9402 u8 register_data[][0x20]; 9403 }; 9404 9405 enum { 9406 MLX5_ACCESS_REGISTER_IN_OP_MOD_WRITE = 0x0, 9407 MLX5_ACCESS_REGISTER_IN_OP_MOD_READ = 0x1, 9408 }; 9409 9410 struct mlx5_ifc_access_register_in_bits { 9411 u8 opcode[0x10]; 9412 u8 reserved_at_10[0x10]; 9413 9414 u8 reserved_at_20[0x10]; 9415 u8 op_mod[0x10]; 9416 9417 u8 reserved_at_40[0x10]; 9418 u8 register_id[0x10]; 9419 9420 u8 argument[0x20]; 9421 9422 u8 register_data[][0x20]; 9423 }; 9424 9425 struct mlx5_ifc_sltp_reg_bits { 9426 u8 status[0x4]; 9427 u8 version[0x4]; 9428 u8 local_port[0x8]; 9429 u8 pnat[0x2]; 9430 u8 reserved_at_12[0x2]; 9431 u8 lane[0x4]; 9432 u8 reserved_at_18[0x8]; 9433 9434 u8 reserved_at_20[0x20]; 9435 9436 u8 reserved_at_40[0x7]; 9437 u8 polarity[0x1]; 9438 u8 ob_tap0[0x8]; 9439 u8 ob_tap1[0x8]; 9440 u8 ob_tap2[0x8]; 9441 9442 u8 reserved_at_60[0xc]; 9443 u8 ob_preemp_mode[0x4]; 9444 u8 ob_reg[0x8]; 9445 u8 ob_bias[0x8]; 9446 9447 u8 reserved_at_80[0x20]; 9448 }; 9449 9450 struct mlx5_ifc_slrg_reg_bits { 9451 u8 status[0x4]; 9452 u8 version[0x4]; 9453 u8 local_port[0x8]; 9454 u8 pnat[0x2]; 9455 u8 reserved_at_12[0x2]; 9456 u8 lane[0x4]; 9457 u8 reserved_at_18[0x8]; 9458 9459 u8 time_to_link_up[0x10]; 9460 u8 reserved_at_30[0xc]; 9461 u8 grade_lane_speed[0x4]; 9462 9463 u8 grade_version[0x8]; 9464 u8 grade[0x18]; 9465 9466 u8 reserved_at_60[0x4]; 9467 u8 height_grade_type[0x4]; 9468 u8 height_grade[0x18]; 9469 9470 u8 height_dz[0x10]; 9471 u8 height_dv[0x10]; 9472 9473 u8 reserved_at_a0[0x10]; 9474 u8 height_sigma[0x10]; 9475 9476 u8 reserved_at_c0[0x20]; 9477 9478 u8 reserved_at_e0[0x4]; 9479 u8 phase_grade_type[0x4]; 9480 u8 phase_grade[0x18]; 9481 9482 u8 reserved_at_100[0x8]; 9483 u8 phase_eo_pos[0x8]; 9484 u8 reserved_at_110[0x8]; 9485 u8 phase_eo_neg[0x8]; 9486 9487 u8 ffe_set_tested[0x10]; 9488 u8 test_errors_per_lane[0x10]; 9489 }; 9490 9491 struct mlx5_ifc_pvlc_reg_bits { 9492 u8 reserved_at_0[0x8]; 9493 u8 local_port[0x8]; 9494 u8 reserved_at_10[0x10]; 9495 9496 u8 reserved_at_20[0x1c]; 9497 u8 vl_hw_cap[0x4]; 9498 9499 u8 reserved_at_40[0x1c]; 9500 u8 vl_admin[0x4]; 9501 9502 u8 reserved_at_60[0x1c]; 9503 u8 vl_operational[0x4]; 9504 }; 9505 9506 struct mlx5_ifc_pude_reg_bits { 9507 u8 swid[0x8]; 9508 u8 local_port[0x8]; 9509 u8 reserved_at_10[0x4]; 9510 u8 admin_status[0x4]; 9511 u8 reserved_at_18[0x4]; 9512 u8 oper_status[0x4]; 9513 9514 u8 reserved_at_20[0x60]; 9515 }; 9516 9517 struct mlx5_ifc_ptys_reg_bits { 9518 u8 reserved_at_0[0x1]; 9519 u8 an_disable_admin[0x1]; 9520 u8 an_disable_cap[0x1]; 9521 u8 reserved_at_3[0x5]; 9522 u8 local_port[0x8]; 9523 u8 reserved_at_10[0xd]; 9524 u8 proto_mask[0x3]; 9525 9526 u8 an_status[0x4]; 9527 u8 reserved_at_24[0xc]; 9528 u8 data_rate_oper[0x10]; 9529 9530 u8 ext_eth_proto_capability[0x20]; 9531 9532 u8 eth_proto_capability[0x20]; 9533 9534 u8 ib_link_width_capability[0x10]; 9535 u8 ib_proto_capability[0x10]; 9536 9537 u8 ext_eth_proto_admin[0x20]; 9538 9539 u8 eth_proto_admin[0x20]; 9540 9541 u8 ib_link_width_admin[0x10]; 9542 u8 ib_proto_admin[0x10]; 9543 9544 u8 ext_eth_proto_oper[0x20]; 9545 9546 u8 eth_proto_oper[0x20]; 9547 9548 u8 ib_link_width_oper[0x10]; 9549 u8 ib_proto_oper[0x10]; 9550 9551 u8 reserved_at_160[0x1c]; 9552 u8 connector_type[0x4]; 9553 9554 u8 eth_proto_lp_advertise[0x20]; 9555 9556 u8 reserved_at_1a0[0x60]; 9557 }; 9558 9559 struct mlx5_ifc_mlcr_reg_bits { 9560 u8 reserved_at_0[0x8]; 9561 u8 local_port[0x8]; 9562 u8 reserved_at_10[0x20]; 9563 9564 u8 beacon_duration[0x10]; 9565 u8 reserved_at_40[0x10]; 9566 9567 u8 beacon_remain[0x10]; 9568 }; 9569 9570 struct mlx5_ifc_ptas_reg_bits { 9571 u8 reserved_at_0[0x20]; 9572 9573 u8 algorithm_options[0x10]; 9574 u8 reserved_at_30[0x4]; 9575 u8 repetitions_mode[0x4]; 9576 u8 num_of_repetitions[0x8]; 9577 9578 u8 grade_version[0x8]; 9579 u8 height_grade_type[0x4]; 9580 u8 phase_grade_type[0x4]; 9581 u8 height_grade_weight[0x8]; 9582 u8 phase_grade_weight[0x8]; 9583 9584 u8 gisim_measure_bits[0x10]; 9585 u8 adaptive_tap_measure_bits[0x10]; 9586 9587 u8 ber_bath_high_error_threshold[0x10]; 9588 u8 ber_bath_mid_error_threshold[0x10]; 9589 9590 u8 ber_bath_low_error_threshold[0x10]; 9591 u8 one_ratio_high_threshold[0x10]; 9592 9593 u8 one_ratio_high_mid_threshold[0x10]; 9594 u8 one_ratio_low_mid_threshold[0x10]; 9595 9596 u8 one_ratio_low_threshold[0x10]; 9597 u8 ndeo_error_threshold[0x10]; 9598 9599 u8 mixer_offset_step_size[0x10]; 9600 u8 reserved_at_110[0x8]; 9601 u8 mix90_phase_for_voltage_bath[0x8]; 9602 9603 u8 mixer_offset_start[0x10]; 9604 u8 mixer_offset_end[0x10]; 9605 9606 u8 reserved_at_140[0x15]; 9607 u8 ber_test_time[0xb]; 9608 }; 9609 9610 struct mlx5_ifc_pspa_reg_bits { 9611 u8 swid[0x8]; 9612 u8 local_port[0x8]; 9613 u8 sub_port[0x8]; 9614 u8 reserved_at_18[0x8]; 9615 9616 u8 reserved_at_20[0x20]; 9617 }; 9618 9619 struct mlx5_ifc_pqdr_reg_bits { 9620 u8 reserved_at_0[0x8]; 9621 u8 local_port[0x8]; 9622 u8 reserved_at_10[0x5]; 9623 u8 prio[0x3]; 9624 u8 reserved_at_18[0x6]; 9625 u8 mode[0x2]; 9626 9627 u8 reserved_at_20[0x20]; 9628 9629 u8 reserved_at_40[0x10]; 9630 u8 min_threshold[0x10]; 9631 9632 u8 reserved_at_60[0x10]; 9633 u8 max_threshold[0x10]; 9634 9635 u8 reserved_at_80[0x10]; 9636 u8 mark_probability_denominator[0x10]; 9637 9638 u8 reserved_at_a0[0x60]; 9639 }; 9640 9641 struct mlx5_ifc_ppsc_reg_bits { 9642 u8 reserved_at_0[0x8]; 9643 u8 local_port[0x8]; 9644 u8 reserved_at_10[0x10]; 9645 9646 u8 reserved_at_20[0x60]; 9647 9648 u8 reserved_at_80[0x1c]; 9649 u8 wrps_admin[0x4]; 9650 9651 u8 reserved_at_a0[0x1c]; 9652 u8 wrps_status[0x4]; 9653 9654 u8 reserved_at_c0[0x8]; 9655 u8 up_threshold[0x8]; 9656 u8 reserved_at_d0[0x8]; 9657 u8 down_threshold[0x8]; 9658 9659 u8 reserved_at_e0[0x20]; 9660 9661 u8 reserved_at_100[0x1c]; 9662 u8 srps_admin[0x4]; 9663 9664 u8 reserved_at_120[0x1c]; 9665 u8 srps_status[0x4]; 9666 9667 u8 reserved_at_140[0x40]; 9668 }; 9669 9670 struct mlx5_ifc_pplr_reg_bits { 9671 u8 reserved_at_0[0x8]; 9672 u8 local_port[0x8]; 9673 u8 reserved_at_10[0x10]; 9674 9675 u8 reserved_at_20[0x8]; 9676 u8 lb_cap[0x8]; 9677 u8 reserved_at_30[0x8]; 9678 u8 lb_en[0x8]; 9679 }; 9680 9681 struct mlx5_ifc_pplm_reg_bits { 9682 u8 reserved_at_0[0x8]; 9683 u8 local_port[0x8]; 9684 u8 reserved_at_10[0x10]; 9685 9686 u8 reserved_at_20[0x20]; 9687 9688 u8 port_profile_mode[0x8]; 9689 u8 static_port_profile[0x8]; 9690 u8 active_port_profile[0x8]; 9691 u8 reserved_at_58[0x8]; 9692 9693 u8 retransmission_active[0x8]; 9694 u8 fec_mode_active[0x18]; 9695 9696 u8 rs_fec_correction_bypass_cap[0x4]; 9697 u8 reserved_at_84[0x8]; 9698 u8 fec_override_cap_56g[0x4]; 9699 u8 fec_override_cap_100g[0x4]; 9700 u8 fec_override_cap_50g[0x4]; 9701 u8 fec_override_cap_25g[0x4]; 9702 u8 fec_override_cap_10g_40g[0x4]; 9703 9704 u8 rs_fec_correction_bypass_admin[0x4]; 9705 u8 reserved_at_a4[0x8]; 9706 u8 fec_override_admin_56g[0x4]; 9707 u8 fec_override_admin_100g[0x4]; 9708 u8 fec_override_admin_50g[0x4]; 9709 u8 fec_override_admin_25g[0x4]; 9710 u8 fec_override_admin_10g_40g[0x4]; 9711 9712 u8 fec_override_cap_400g_8x[0x10]; 9713 u8 fec_override_cap_200g_4x[0x10]; 9714 9715 u8 fec_override_cap_100g_2x[0x10]; 9716 u8 fec_override_cap_50g_1x[0x10]; 9717 9718 u8 fec_override_admin_400g_8x[0x10]; 9719 u8 fec_override_admin_200g_4x[0x10]; 9720 9721 u8 fec_override_admin_100g_2x[0x10]; 9722 u8 fec_override_admin_50g_1x[0x10]; 9723 9724 u8 reserved_at_140[0x140]; 9725 }; 9726 9727 struct mlx5_ifc_ppcnt_reg_bits { 9728 u8 swid[0x8]; 9729 u8 local_port[0x8]; 9730 u8 pnat[0x2]; 9731 u8 reserved_at_12[0x8]; 9732 u8 grp[0x6]; 9733 9734 u8 clr[0x1]; 9735 u8 reserved_at_21[0x1c]; 9736 u8 prio_tc[0x3]; 9737 9738 union mlx5_ifc_eth_cntrs_grp_data_layout_auto_bits counter_set; 9739 }; 9740 9741 struct mlx5_ifc_mpein_reg_bits { 9742 u8 reserved_at_0[0x2]; 9743 u8 depth[0x6]; 9744 u8 pcie_index[0x8]; 9745 u8 node[0x8]; 9746 u8 reserved_at_18[0x8]; 9747 9748 u8 capability_mask[0x20]; 9749 9750 u8 reserved_at_40[0x8]; 9751 u8 link_width_enabled[0x8]; 9752 u8 link_speed_enabled[0x10]; 9753 9754 u8 lane0_physical_position[0x8]; 9755 u8 link_width_active[0x8]; 9756 u8 link_speed_active[0x10]; 9757 9758 u8 num_of_pfs[0x10]; 9759 u8 num_of_vfs[0x10]; 9760 9761 u8 bdf0[0x10]; 9762 u8 reserved_at_b0[0x10]; 9763 9764 u8 max_read_request_size[0x4]; 9765 u8 max_payload_size[0x4]; 9766 u8 reserved_at_c8[0x5]; 9767 u8 pwr_status[0x3]; 9768 u8 port_type[0x4]; 9769 u8 reserved_at_d4[0xb]; 9770 u8 lane_reversal[0x1]; 9771 9772 u8 reserved_at_e0[0x14]; 9773 u8 pci_power[0xc]; 9774 9775 u8 reserved_at_100[0x20]; 9776 9777 u8 device_status[0x10]; 9778 u8 port_state[0x8]; 9779 u8 reserved_at_138[0x8]; 9780 9781 u8 reserved_at_140[0x10]; 9782 u8 receiver_detect_result[0x10]; 9783 9784 u8 reserved_at_160[0x20]; 9785 }; 9786 9787 struct mlx5_ifc_mpcnt_reg_bits { 9788 u8 reserved_at_0[0x8]; 9789 u8 pcie_index[0x8]; 9790 u8 reserved_at_10[0xa]; 9791 u8 grp[0x6]; 9792 9793 u8 clr[0x1]; 9794 u8 reserved_at_21[0x1f]; 9795 9796 union mlx5_ifc_pcie_cntrs_grp_data_layout_auto_bits counter_set; 9797 }; 9798 9799 struct mlx5_ifc_ppad_reg_bits { 9800 u8 reserved_at_0[0x3]; 9801 u8 single_mac[0x1]; 9802 u8 reserved_at_4[0x4]; 9803 u8 local_port[0x8]; 9804 u8 mac_47_32[0x10]; 9805 9806 u8 mac_31_0[0x20]; 9807 9808 u8 reserved_at_40[0x40]; 9809 }; 9810 9811 struct mlx5_ifc_pmtu_reg_bits { 9812 u8 reserved_at_0[0x8]; 9813 u8 local_port[0x8]; 9814 u8 reserved_at_10[0x10]; 9815 9816 u8 max_mtu[0x10]; 9817 u8 reserved_at_30[0x10]; 9818 9819 u8 admin_mtu[0x10]; 9820 u8 reserved_at_50[0x10]; 9821 9822 u8 oper_mtu[0x10]; 9823 u8 reserved_at_70[0x10]; 9824 }; 9825 9826 struct mlx5_ifc_pmpr_reg_bits { 9827 u8 reserved_at_0[0x8]; 9828 u8 module[0x8]; 9829 u8 reserved_at_10[0x10]; 9830 9831 u8 reserved_at_20[0x18]; 9832 u8 attenuation_5g[0x8]; 9833 9834 u8 reserved_at_40[0x18]; 9835 u8 attenuation_7g[0x8]; 9836 9837 u8 reserved_at_60[0x18]; 9838 u8 attenuation_12g[0x8]; 9839 }; 9840 9841 struct mlx5_ifc_pmpe_reg_bits { 9842 u8 reserved_at_0[0x8]; 9843 u8 module[0x8]; 9844 u8 reserved_at_10[0xc]; 9845 u8 module_status[0x4]; 9846 9847 u8 reserved_at_20[0x60]; 9848 }; 9849 9850 struct mlx5_ifc_pmpc_reg_bits { 9851 u8 module_state_updated[32][0x8]; 9852 }; 9853 9854 struct mlx5_ifc_pmlpn_reg_bits { 9855 u8 reserved_at_0[0x4]; 9856 u8 mlpn_status[0x4]; 9857 u8 local_port[0x8]; 9858 u8 reserved_at_10[0x10]; 9859 9860 u8 e[0x1]; 9861 u8 reserved_at_21[0x1f]; 9862 }; 9863 9864 struct mlx5_ifc_pmlp_reg_bits { 9865 u8 rxtx[0x1]; 9866 u8 reserved_at_1[0x7]; 9867 u8 local_port[0x8]; 9868 u8 reserved_at_10[0x8]; 9869 u8 width[0x8]; 9870 9871 u8 lane0_module_mapping[0x20]; 9872 9873 u8 lane1_module_mapping[0x20]; 9874 9875 u8 lane2_module_mapping[0x20]; 9876 9877 u8 lane3_module_mapping[0x20]; 9878 9879 u8 reserved_at_a0[0x160]; 9880 }; 9881 9882 struct mlx5_ifc_pmaos_reg_bits { 9883 u8 reserved_at_0[0x8]; 9884 u8 module[0x8]; 9885 u8 reserved_at_10[0x4]; 9886 u8 admin_status[0x4]; 9887 u8 reserved_at_18[0x4]; 9888 u8 oper_status[0x4]; 9889 9890 u8 ase[0x1]; 9891 u8 ee[0x1]; 9892 u8 reserved_at_22[0x1c]; 9893 u8 e[0x2]; 9894 9895 u8 reserved_at_40[0x40]; 9896 }; 9897 9898 struct mlx5_ifc_plpc_reg_bits { 9899 u8 reserved_at_0[0x4]; 9900 u8 profile_id[0xc]; 9901 u8 reserved_at_10[0x4]; 9902 u8 proto_mask[0x4]; 9903 u8 reserved_at_18[0x8]; 9904 9905 u8 reserved_at_20[0x10]; 9906 u8 lane_speed[0x10]; 9907 9908 u8 reserved_at_40[0x17]; 9909 u8 lpbf[0x1]; 9910 u8 fec_mode_policy[0x8]; 9911 9912 u8 retransmission_capability[0x8]; 9913 u8 fec_mode_capability[0x18]; 9914 9915 u8 retransmission_support_admin[0x8]; 9916 u8 fec_mode_support_admin[0x18]; 9917 9918 u8 retransmission_request_admin[0x8]; 9919 u8 fec_mode_request_admin[0x18]; 9920 9921 u8 reserved_at_c0[0x80]; 9922 }; 9923 9924 struct mlx5_ifc_plib_reg_bits { 9925 u8 reserved_at_0[0x8]; 9926 u8 local_port[0x8]; 9927 u8 reserved_at_10[0x8]; 9928 u8 ib_port[0x8]; 9929 9930 u8 reserved_at_20[0x60]; 9931 }; 9932 9933 struct mlx5_ifc_plbf_reg_bits { 9934 u8 reserved_at_0[0x8]; 9935 u8 local_port[0x8]; 9936 u8 reserved_at_10[0xd]; 9937 u8 lbf_mode[0x3]; 9938 9939 u8 reserved_at_20[0x20]; 9940 }; 9941 9942 struct mlx5_ifc_pipg_reg_bits { 9943 u8 reserved_at_0[0x8]; 9944 u8 local_port[0x8]; 9945 u8 reserved_at_10[0x10]; 9946 9947 u8 dic[0x1]; 9948 u8 reserved_at_21[0x19]; 9949 u8 ipg[0x4]; 9950 u8 reserved_at_3e[0x2]; 9951 }; 9952 9953 struct mlx5_ifc_pifr_reg_bits { 9954 u8 reserved_at_0[0x8]; 9955 u8 local_port[0x8]; 9956 u8 reserved_at_10[0x10]; 9957 9958 u8 reserved_at_20[0xe0]; 9959 9960 u8 port_filter[8][0x20]; 9961 9962 u8 port_filter_update_en[8][0x20]; 9963 }; 9964 9965 struct mlx5_ifc_pfcc_reg_bits { 9966 u8 reserved_at_0[0x8]; 9967 u8 local_port[0x8]; 9968 u8 reserved_at_10[0xb]; 9969 u8 ppan_mask_n[0x1]; 9970 u8 minor_stall_mask[0x1]; 9971 u8 critical_stall_mask[0x1]; 9972 u8 reserved_at_1e[0x2]; 9973 9974 u8 ppan[0x4]; 9975 u8 reserved_at_24[0x4]; 9976 u8 prio_mask_tx[0x8]; 9977 u8 reserved_at_30[0x8]; 9978 u8 prio_mask_rx[0x8]; 9979 9980 u8 pptx[0x1]; 9981 u8 aptx[0x1]; 9982 u8 pptx_mask_n[0x1]; 9983 u8 reserved_at_43[0x5]; 9984 u8 pfctx[0x8]; 9985 u8 reserved_at_50[0x10]; 9986 9987 u8 pprx[0x1]; 9988 u8 aprx[0x1]; 9989 u8 pprx_mask_n[0x1]; 9990 u8 reserved_at_63[0x5]; 9991 u8 pfcrx[0x8]; 9992 u8 reserved_at_70[0x10]; 9993 9994 u8 device_stall_minor_watermark[0x10]; 9995 u8 device_stall_critical_watermark[0x10]; 9996 9997 u8 reserved_at_a0[0x60]; 9998 }; 9999 10000 struct mlx5_ifc_pelc_reg_bits { 10001 u8 op[0x4]; 10002 u8 reserved_at_4[0x4]; 10003 u8 local_port[0x8]; 10004 u8 reserved_at_10[0x10]; 10005 10006 u8 op_admin[0x8]; 10007 u8 op_capability[0x8]; 10008 u8 op_request[0x8]; 10009 u8 op_active[0x8]; 10010 10011 u8 admin[0x40]; 10012 10013 u8 capability[0x40]; 10014 10015 u8 request[0x40]; 10016 10017 u8 active[0x40]; 10018 10019 u8 reserved_at_140[0x80]; 10020 }; 10021 10022 struct mlx5_ifc_peir_reg_bits { 10023 u8 reserved_at_0[0x8]; 10024 u8 local_port[0x8]; 10025 u8 reserved_at_10[0x10]; 10026 10027 u8 reserved_at_20[0xc]; 10028 u8 error_count[0x4]; 10029 u8 reserved_at_30[0x10]; 10030 10031 u8 reserved_at_40[0xc]; 10032 u8 lane[0x4]; 10033 u8 reserved_at_50[0x8]; 10034 u8 error_type[0x8]; 10035 }; 10036 10037 struct mlx5_ifc_mpegc_reg_bits { 10038 u8 reserved_at_0[0x30]; 10039 u8 field_select[0x10]; 10040 10041 u8 tx_overflow_sense[0x1]; 10042 u8 mark_cqe[0x1]; 10043 u8 mark_cnp[0x1]; 10044 u8 reserved_at_43[0x1b]; 10045 u8 tx_lossy_overflow_oper[0x2]; 10046 10047 u8 reserved_at_60[0x100]; 10048 }; 10049 10050 enum { 10051 MLX5_MTUTC_FREQ_ADJ_UNITS_PPB = 0x0, 10052 MLX5_MTUTC_FREQ_ADJ_UNITS_SCALED_PPM = 0x1, 10053 }; 10054 10055 enum { 10056 MLX5_MTUTC_OPERATION_SET_TIME_IMMEDIATE = 0x1, 10057 MLX5_MTUTC_OPERATION_ADJUST_TIME = 0x2, 10058 MLX5_MTUTC_OPERATION_ADJUST_FREQ_UTC = 0x3, 10059 }; 10060 10061 struct mlx5_ifc_mtutc_reg_bits { 10062 u8 reserved_at_0[0x5]; 10063 u8 freq_adj_units[0x3]; 10064 u8 reserved_at_8[0x14]; 10065 u8 operation[0x4]; 10066 10067 u8 freq_adjustment[0x20]; 10068 10069 u8 reserved_at_40[0x40]; 10070 10071 u8 utc_sec[0x20]; 10072 10073 u8 reserved_at_a0[0x2]; 10074 u8 utc_nsec[0x1e]; 10075 10076 u8 time_adjustment[0x20]; 10077 }; 10078 10079 struct mlx5_ifc_pcam_enhanced_features_bits { 10080 u8 reserved_at_0[0x68]; 10081 u8 fec_50G_per_lane_in_pplm[0x1]; 10082 u8 reserved_at_69[0x4]; 10083 u8 rx_icrc_encapsulated_counter[0x1]; 10084 u8 reserved_at_6e[0x4]; 10085 u8 ptys_extended_ethernet[0x1]; 10086 u8 reserved_at_73[0x3]; 10087 u8 pfcc_mask[0x1]; 10088 u8 reserved_at_77[0x3]; 10089 u8 per_lane_error_counters[0x1]; 10090 u8 rx_buffer_fullness_counters[0x1]; 10091 u8 ptys_connector_type[0x1]; 10092 u8 reserved_at_7d[0x1]; 10093 u8 ppcnt_discard_group[0x1]; 10094 u8 ppcnt_statistical_group[0x1]; 10095 }; 10096 10097 struct mlx5_ifc_pcam_regs_5000_to_507f_bits { 10098 u8 port_access_reg_cap_mask_127_to_96[0x20]; 10099 u8 port_access_reg_cap_mask_95_to_64[0x20]; 10100 10101 u8 port_access_reg_cap_mask_63_to_36[0x1c]; 10102 u8 pplm[0x1]; 10103 u8 port_access_reg_cap_mask_34_to_32[0x3]; 10104 10105 u8 port_access_reg_cap_mask_31_to_13[0x13]; 10106 u8 pbmc[0x1]; 10107 u8 pptb[0x1]; 10108 u8 port_access_reg_cap_mask_10_to_09[0x2]; 10109 u8 ppcnt[0x1]; 10110 u8 port_access_reg_cap_mask_07_to_00[0x8]; 10111 }; 10112 10113 struct mlx5_ifc_pcam_reg_bits { 10114 u8 reserved_at_0[0x8]; 10115 u8 feature_group[0x8]; 10116 u8 reserved_at_10[0x8]; 10117 u8 access_reg_group[0x8]; 10118 10119 u8 reserved_at_20[0x20]; 10120 10121 union { 10122 struct mlx5_ifc_pcam_regs_5000_to_507f_bits regs_5000_to_507f; 10123 u8 reserved_at_0[0x80]; 10124 } port_access_reg_cap_mask; 10125 10126 u8 reserved_at_c0[0x80]; 10127 10128 union { 10129 struct mlx5_ifc_pcam_enhanced_features_bits enhanced_features; 10130 u8 reserved_at_0[0x80]; 10131 } feature_cap_mask; 10132 10133 u8 reserved_at_1c0[0xc0]; 10134 }; 10135 10136 struct mlx5_ifc_mcam_enhanced_features_bits { 10137 u8 reserved_at_0[0x50]; 10138 u8 mtutc_freq_adj_units[0x1]; 10139 u8 mtutc_time_adjustment_extended_range[0x1]; 10140 u8 reserved_at_52[0xb]; 10141 u8 mcia_32dwords[0x1]; 10142 u8 out_pulse_duration_ns[0x1]; 10143 u8 npps_period[0x1]; 10144 u8 reserved_at_60[0xa]; 10145 u8 reset_state[0x1]; 10146 u8 ptpcyc2realtime_modify[0x1]; 10147 u8 reserved_at_6c[0x2]; 10148 u8 pci_status_and_power[0x1]; 10149 u8 reserved_at_6f[0x5]; 10150 u8 mark_tx_action_cnp[0x1]; 10151 u8 mark_tx_action_cqe[0x1]; 10152 u8 dynamic_tx_overflow[0x1]; 10153 u8 reserved_at_77[0x4]; 10154 u8 pcie_outbound_stalled[0x1]; 10155 u8 tx_overflow_buffer_pkt[0x1]; 10156 u8 mtpps_enh_out_per_adj[0x1]; 10157 u8 mtpps_fs[0x1]; 10158 u8 pcie_performance_group[0x1]; 10159 }; 10160 10161 struct mlx5_ifc_mcam_access_reg_bits { 10162 u8 reserved_at_0[0x1c]; 10163 u8 mcda[0x1]; 10164 u8 mcc[0x1]; 10165 u8 mcqi[0x1]; 10166 u8 mcqs[0x1]; 10167 10168 u8 regs_95_to_87[0x9]; 10169 u8 mpegc[0x1]; 10170 u8 mtutc[0x1]; 10171 u8 regs_84_to_68[0x11]; 10172 u8 tracer_registers[0x4]; 10173 10174 u8 regs_63_to_46[0x12]; 10175 u8 mrtc[0x1]; 10176 u8 regs_44_to_32[0xd]; 10177 10178 u8 regs_31_to_0[0x20]; 10179 }; 10180 10181 struct mlx5_ifc_mcam_access_reg_bits1 { 10182 u8 regs_127_to_96[0x20]; 10183 10184 u8 regs_95_to_64[0x20]; 10185 10186 u8 regs_63_to_32[0x20]; 10187 10188 u8 regs_31_to_0[0x20]; 10189 }; 10190 10191 struct mlx5_ifc_mcam_access_reg_bits2 { 10192 u8 regs_127_to_99[0x1d]; 10193 u8 mirc[0x1]; 10194 u8 regs_97_to_96[0x2]; 10195 10196 u8 regs_95_to_64[0x20]; 10197 10198 u8 regs_63_to_32[0x20]; 10199 10200 u8 regs_31_to_0[0x20]; 10201 }; 10202 10203 struct mlx5_ifc_mcam_reg_bits { 10204 u8 reserved_at_0[0x8]; 10205 u8 feature_group[0x8]; 10206 u8 reserved_at_10[0x8]; 10207 u8 access_reg_group[0x8]; 10208 10209 u8 reserved_at_20[0x20]; 10210 10211 union { 10212 struct mlx5_ifc_mcam_access_reg_bits access_regs; 10213 struct mlx5_ifc_mcam_access_reg_bits1 access_regs1; 10214 struct mlx5_ifc_mcam_access_reg_bits2 access_regs2; 10215 u8 reserved_at_0[0x80]; 10216 } mng_access_reg_cap_mask; 10217 10218 u8 reserved_at_c0[0x80]; 10219 10220 union { 10221 struct mlx5_ifc_mcam_enhanced_features_bits enhanced_features; 10222 u8 reserved_at_0[0x80]; 10223 } mng_feature_cap_mask; 10224 10225 u8 reserved_at_1c0[0x80]; 10226 }; 10227 10228 struct mlx5_ifc_qcam_access_reg_cap_mask { 10229 u8 qcam_access_reg_cap_mask_127_to_20[0x6C]; 10230 u8 qpdpm[0x1]; 10231 u8 qcam_access_reg_cap_mask_18_to_4[0x0F]; 10232 u8 qdpm[0x1]; 10233 u8 qpts[0x1]; 10234 u8 qcap[0x1]; 10235 u8 qcam_access_reg_cap_mask_0[0x1]; 10236 }; 10237 10238 struct mlx5_ifc_qcam_qos_feature_cap_mask { 10239 u8 qcam_qos_feature_cap_mask_127_to_1[0x7F]; 10240 u8 qpts_trust_both[0x1]; 10241 }; 10242 10243 struct mlx5_ifc_qcam_reg_bits { 10244 u8 reserved_at_0[0x8]; 10245 u8 feature_group[0x8]; 10246 u8 reserved_at_10[0x8]; 10247 u8 access_reg_group[0x8]; 10248 u8 reserved_at_20[0x20]; 10249 10250 union { 10251 struct mlx5_ifc_qcam_access_reg_cap_mask reg_cap; 10252 u8 reserved_at_0[0x80]; 10253 } qos_access_reg_cap_mask; 10254 10255 u8 reserved_at_c0[0x80]; 10256 10257 union { 10258 struct mlx5_ifc_qcam_qos_feature_cap_mask feature_cap; 10259 u8 reserved_at_0[0x80]; 10260 } qos_feature_cap_mask; 10261 10262 u8 reserved_at_1c0[0x80]; 10263 }; 10264 10265 struct mlx5_ifc_core_dump_reg_bits { 10266 u8 reserved_at_0[0x18]; 10267 u8 core_dump_type[0x8]; 10268 10269 u8 reserved_at_20[0x30]; 10270 u8 vhca_id[0x10]; 10271 10272 u8 reserved_at_60[0x8]; 10273 u8 qpn[0x18]; 10274 u8 reserved_at_80[0x180]; 10275 }; 10276 10277 struct mlx5_ifc_pcap_reg_bits { 10278 u8 reserved_at_0[0x8]; 10279 u8 local_port[0x8]; 10280 u8 reserved_at_10[0x10]; 10281 10282 u8 port_capability_mask[4][0x20]; 10283 }; 10284 10285 struct mlx5_ifc_paos_reg_bits { 10286 u8 swid[0x8]; 10287 u8 local_port[0x8]; 10288 u8 reserved_at_10[0x4]; 10289 u8 admin_status[0x4]; 10290 u8 reserved_at_18[0x4]; 10291 u8 oper_status[0x4]; 10292 10293 u8 ase[0x1]; 10294 u8 ee[0x1]; 10295 u8 reserved_at_22[0x1c]; 10296 u8 e[0x2]; 10297 10298 u8 reserved_at_40[0x40]; 10299 }; 10300 10301 struct mlx5_ifc_pamp_reg_bits { 10302 u8 reserved_at_0[0x8]; 10303 u8 opamp_group[0x8]; 10304 u8 reserved_at_10[0xc]; 10305 u8 opamp_group_type[0x4]; 10306 10307 u8 start_index[0x10]; 10308 u8 reserved_at_30[0x4]; 10309 u8 num_of_indices[0xc]; 10310 10311 u8 index_data[18][0x10]; 10312 }; 10313 10314 struct mlx5_ifc_pcmr_reg_bits { 10315 u8 reserved_at_0[0x8]; 10316 u8 local_port[0x8]; 10317 u8 reserved_at_10[0x10]; 10318 10319 u8 entropy_force_cap[0x1]; 10320 u8 entropy_calc_cap[0x1]; 10321 u8 entropy_gre_calc_cap[0x1]; 10322 u8 reserved_at_23[0xf]; 10323 u8 rx_ts_over_crc_cap[0x1]; 10324 u8 reserved_at_33[0xb]; 10325 u8 fcs_cap[0x1]; 10326 u8 reserved_at_3f[0x1]; 10327 10328 u8 entropy_force[0x1]; 10329 u8 entropy_calc[0x1]; 10330 u8 entropy_gre_calc[0x1]; 10331 u8 reserved_at_43[0xf]; 10332 u8 rx_ts_over_crc[0x1]; 10333 u8 reserved_at_53[0xb]; 10334 u8 fcs_chk[0x1]; 10335 u8 reserved_at_5f[0x1]; 10336 }; 10337 10338 struct mlx5_ifc_lane_2_module_mapping_bits { 10339 u8 reserved_at_0[0x4]; 10340 u8 rx_lane[0x4]; 10341 u8 reserved_at_8[0x4]; 10342 u8 tx_lane[0x4]; 10343 u8 reserved_at_10[0x8]; 10344 u8 module[0x8]; 10345 }; 10346 10347 struct mlx5_ifc_bufferx_reg_bits { 10348 u8 reserved_at_0[0x6]; 10349 u8 lossy[0x1]; 10350 u8 epsb[0x1]; 10351 u8 reserved_at_8[0x8]; 10352 u8 size[0x10]; 10353 10354 u8 xoff_threshold[0x10]; 10355 u8 xon_threshold[0x10]; 10356 }; 10357 10358 struct mlx5_ifc_set_node_in_bits { 10359 u8 node_description[64][0x8]; 10360 }; 10361 10362 struct mlx5_ifc_register_power_settings_bits { 10363 u8 reserved_at_0[0x18]; 10364 u8 power_settings_level[0x8]; 10365 10366 u8 reserved_at_20[0x60]; 10367 }; 10368 10369 struct mlx5_ifc_register_host_endianness_bits { 10370 u8 he[0x1]; 10371 u8 reserved_at_1[0x1f]; 10372 10373 u8 reserved_at_20[0x60]; 10374 }; 10375 10376 struct mlx5_ifc_umr_pointer_desc_argument_bits { 10377 u8 reserved_at_0[0x20]; 10378 10379 u8 mkey[0x20]; 10380 10381 u8 addressh_63_32[0x20]; 10382 10383 u8 addressl_31_0[0x20]; 10384 }; 10385 10386 struct mlx5_ifc_ud_adrs_vector_bits { 10387 u8 dc_key[0x40]; 10388 10389 u8 ext[0x1]; 10390 u8 reserved_at_41[0x7]; 10391 u8 destination_qp_dct[0x18]; 10392 10393 u8 static_rate[0x4]; 10394 u8 sl_eth_prio[0x4]; 10395 u8 fl[0x1]; 10396 u8 mlid[0x7]; 10397 u8 rlid_udp_sport[0x10]; 10398 10399 u8 reserved_at_80[0x20]; 10400 10401 u8 rmac_47_16[0x20]; 10402 10403 u8 rmac_15_0[0x10]; 10404 u8 tclass[0x8]; 10405 u8 hop_limit[0x8]; 10406 10407 u8 reserved_at_e0[0x1]; 10408 u8 grh[0x1]; 10409 u8 reserved_at_e2[0x2]; 10410 u8 src_addr_index[0x8]; 10411 u8 flow_label[0x14]; 10412 10413 u8 rgid_rip[16][0x8]; 10414 }; 10415 10416 struct mlx5_ifc_pages_req_event_bits { 10417 u8 reserved_at_0[0x10]; 10418 u8 function_id[0x10]; 10419 10420 u8 num_pages[0x20]; 10421 10422 u8 reserved_at_40[0xa0]; 10423 }; 10424 10425 struct mlx5_ifc_eqe_bits { 10426 u8 reserved_at_0[0x8]; 10427 u8 event_type[0x8]; 10428 u8 reserved_at_10[0x8]; 10429 u8 event_sub_type[0x8]; 10430 10431 u8 reserved_at_20[0xe0]; 10432 10433 union mlx5_ifc_event_auto_bits event_data; 10434 10435 u8 reserved_at_1e0[0x10]; 10436 u8 signature[0x8]; 10437 u8 reserved_at_1f8[0x7]; 10438 u8 owner[0x1]; 10439 }; 10440 10441 enum { 10442 MLX5_CMD_QUEUE_ENTRY_TYPE_PCIE_CMD_IF_TRANSPORT = 0x7, 10443 }; 10444 10445 struct mlx5_ifc_cmd_queue_entry_bits { 10446 u8 type[0x8]; 10447 u8 reserved_at_8[0x18]; 10448 10449 u8 input_length[0x20]; 10450 10451 u8 input_mailbox_pointer_63_32[0x20]; 10452 10453 u8 input_mailbox_pointer_31_9[0x17]; 10454 u8 reserved_at_77[0x9]; 10455 10456 u8 command_input_inline_data[16][0x8]; 10457 10458 u8 command_output_inline_data[16][0x8]; 10459 10460 u8 output_mailbox_pointer_63_32[0x20]; 10461 10462 u8 output_mailbox_pointer_31_9[0x17]; 10463 u8 reserved_at_1b7[0x9]; 10464 10465 u8 output_length[0x20]; 10466 10467 u8 token[0x8]; 10468 u8 signature[0x8]; 10469 u8 reserved_at_1f0[0x8]; 10470 u8 status[0x7]; 10471 u8 ownership[0x1]; 10472 }; 10473 10474 struct mlx5_ifc_cmd_out_bits { 10475 u8 status[0x8]; 10476 u8 reserved_at_8[0x18]; 10477 10478 u8 syndrome[0x20]; 10479 10480 u8 command_output[0x20]; 10481 }; 10482 10483 struct mlx5_ifc_cmd_in_bits { 10484 u8 opcode[0x10]; 10485 u8 reserved_at_10[0x10]; 10486 10487 u8 reserved_at_20[0x10]; 10488 u8 op_mod[0x10]; 10489 10490 u8 command[][0x20]; 10491 }; 10492 10493 struct mlx5_ifc_cmd_if_box_bits { 10494 u8 mailbox_data[512][0x8]; 10495 10496 u8 reserved_at_1000[0x180]; 10497 10498 u8 next_pointer_63_32[0x20]; 10499 10500 u8 next_pointer_31_10[0x16]; 10501 u8 reserved_at_11b6[0xa]; 10502 10503 u8 block_number[0x20]; 10504 10505 u8 reserved_at_11e0[0x8]; 10506 u8 token[0x8]; 10507 u8 ctrl_signature[0x8]; 10508 u8 signature[0x8]; 10509 }; 10510 10511 struct mlx5_ifc_mtt_bits { 10512 u8 ptag_63_32[0x20]; 10513 10514 u8 ptag_31_8[0x18]; 10515 u8 reserved_at_38[0x6]; 10516 u8 wr_en[0x1]; 10517 u8 rd_en[0x1]; 10518 }; 10519 10520 struct mlx5_ifc_query_wol_rol_out_bits { 10521 u8 status[0x8]; 10522 u8 reserved_at_8[0x18]; 10523 10524 u8 syndrome[0x20]; 10525 10526 u8 reserved_at_40[0x10]; 10527 u8 rol_mode[0x8]; 10528 u8 wol_mode[0x8]; 10529 10530 u8 reserved_at_60[0x20]; 10531 }; 10532 10533 struct mlx5_ifc_query_wol_rol_in_bits { 10534 u8 opcode[0x10]; 10535 u8 reserved_at_10[0x10]; 10536 10537 u8 reserved_at_20[0x10]; 10538 u8 op_mod[0x10]; 10539 10540 u8 reserved_at_40[0x40]; 10541 }; 10542 10543 struct mlx5_ifc_set_wol_rol_out_bits { 10544 u8 status[0x8]; 10545 u8 reserved_at_8[0x18]; 10546 10547 u8 syndrome[0x20]; 10548 10549 u8 reserved_at_40[0x40]; 10550 }; 10551 10552 struct mlx5_ifc_set_wol_rol_in_bits { 10553 u8 opcode[0x10]; 10554 u8 reserved_at_10[0x10]; 10555 10556 u8 reserved_at_20[0x10]; 10557 u8 op_mod[0x10]; 10558 10559 u8 rol_mode_valid[0x1]; 10560 u8 wol_mode_valid[0x1]; 10561 u8 reserved_at_42[0xe]; 10562 u8 rol_mode[0x8]; 10563 u8 wol_mode[0x8]; 10564 10565 u8 reserved_at_60[0x20]; 10566 }; 10567 10568 enum { 10569 MLX5_INITIAL_SEG_NIC_INTERFACE_FULL_DRIVER = 0x0, 10570 MLX5_INITIAL_SEG_NIC_INTERFACE_DISABLED = 0x1, 10571 MLX5_INITIAL_SEG_NIC_INTERFACE_NO_DRAM_NIC = 0x2, 10572 }; 10573 10574 enum { 10575 MLX5_INITIAL_SEG_NIC_INTERFACE_SUPPORTED_FULL_DRIVER = 0x0, 10576 MLX5_INITIAL_SEG_NIC_INTERFACE_SUPPORTED_DISABLED = 0x1, 10577 MLX5_INITIAL_SEG_NIC_INTERFACE_SUPPORTED_NO_DRAM_NIC = 0x2, 10578 }; 10579 10580 enum { 10581 MLX5_INITIAL_SEG_HEALTH_SYNDROME_FW_INTERNAL_ERR = 0x1, 10582 MLX5_INITIAL_SEG_HEALTH_SYNDROME_DEAD_IRISC = 0x7, 10583 MLX5_INITIAL_SEG_HEALTH_SYNDROME_HW_FATAL_ERR = 0x8, 10584 MLX5_INITIAL_SEG_HEALTH_SYNDROME_FW_CRC_ERR = 0x9, 10585 MLX5_INITIAL_SEG_HEALTH_SYNDROME_ICM_FETCH_PCI_ERR = 0xa, 10586 MLX5_INITIAL_SEG_HEALTH_SYNDROME_ICM_PAGE_ERR = 0xb, 10587 MLX5_INITIAL_SEG_HEALTH_SYNDROME_ASYNCHRONOUS_EQ_BUF_OVERRUN = 0xc, 10588 MLX5_INITIAL_SEG_HEALTH_SYNDROME_EQ_IN_ERR = 0xd, 10589 MLX5_INITIAL_SEG_HEALTH_SYNDROME_EQ_INV = 0xe, 10590 MLX5_INITIAL_SEG_HEALTH_SYNDROME_FFSER_ERR = 0xf, 10591 MLX5_INITIAL_SEG_HEALTH_SYNDROME_HIGH_TEMP_ERR = 0x10, 10592 }; 10593 10594 struct mlx5_ifc_initial_seg_bits { 10595 u8 fw_rev_minor[0x10]; 10596 u8 fw_rev_major[0x10]; 10597 10598 u8 cmd_interface_rev[0x10]; 10599 u8 fw_rev_subminor[0x10]; 10600 10601 u8 reserved_at_40[0x40]; 10602 10603 u8 cmdq_phy_addr_63_32[0x20]; 10604 10605 u8 cmdq_phy_addr_31_12[0x14]; 10606 u8 reserved_at_b4[0x2]; 10607 u8 nic_interface[0x2]; 10608 u8 log_cmdq_size[0x4]; 10609 u8 log_cmdq_stride[0x4]; 10610 10611 u8 command_doorbell_vector[0x20]; 10612 10613 u8 reserved_at_e0[0xf00]; 10614 10615 u8 initializing[0x1]; 10616 u8 reserved_at_fe1[0x4]; 10617 u8 nic_interface_supported[0x3]; 10618 u8 embedded_cpu[0x1]; 10619 u8 reserved_at_fe9[0x17]; 10620 10621 struct mlx5_ifc_health_buffer_bits health_buffer; 10622 10623 u8 no_dram_nic_offset[0x20]; 10624 10625 u8 reserved_at_1220[0x6e40]; 10626 10627 u8 reserved_at_8060[0x1f]; 10628 u8 clear_int[0x1]; 10629 10630 u8 health_syndrome[0x8]; 10631 u8 health_counter[0x18]; 10632 10633 u8 reserved_at_80a0[0x17fc0]; 10634 }; 10635 10636 struct mlx5_ifc_mtpps_reg_bits { 10637 u8 reserved_at_0[0xc]; 10638 u8 cap_number_of_pps_pins[0x4]; 10639 u8 reserved_at_10[0x4]; 10640 u8 cap_max_num_of_pps_in_pins[0x4]; 10641 u8 reserved_at_18[0x4]; 10642 u8 cap_max_num_of_pps_out_pins[0x4]; 10643 10644 u8 reserved_at_20[0x13]; 10645 u8 cap_log_min_npps_period[0x5]; 10646 u8 reserved_at_38[0x3]; 10647 u8 cap_log_min_out_pulse_duration_ns[0x5]; 10648 10649 u8 reserved_at_40[0x4]; 10650 u8 cap_pin_3_mode[0x4]; 10651 u8 reserved_at_48[0x4]; 10652 u8 cap_pin_2_mode[0x4]; 10653 u8 reserved_at_50[0x4]; 10654 u8 cap_pin_1_mode[0x4]; 10655 u8 reserved_at_58[0x4]; 10656 u8 cap_pin_0_mode[0x4]; 10657 10658 u8 reserved_at_60[0x4]; 10659 u8 cap_pin_7_mode[0x4]; 10660 u8 reserved_at_68[0x4]; 10661 u8 cap_pin_6_mode[0x4]; 10662 u8 reserved_at_70[0x4]; 10663 u8 cap_pin_5_mode[0x4]; 10664 u8 reserved_at_78[0x4]; 10665 u8 cap_pin_4_mode[0x4]; 10666 10667 u8 field_select[0x20]; 10668 u8 reserved_at_a0[0x20]; 10669 10670 u8 npps_period[0x40]; 10671 10672 u8 enable[0x1]; 10673 u8 reserved_at_101[0xb]; 10674 u8 pattern[0x4]; 10675 u8 reserved_at_110[0x4]; 10676 u8 pin_mode[0x4]; 10677 u8 pin[0x8]; 10678 10679 u8 reserved_at_120[0x2]; 10680 u8 out_pulse_duration_ns[0x1e]; 10681 10682 u8 time_stamp[0x40]; 10683 10684 u8 out_pulse_duration[0x10]; 10685 u8 out_periodic_adjustment[0x10]; 10686 u8 enhanced_out_periodic_adjustment[0x20]; 10687 10688 u8 reserved_at_1c0[0x20]; 10689 }; 10690 10691 struct mlx5_ifc_mtppse_reg_bits { 10692 u8 reserved_at_0[0x18]; 10693 u8 pin[0x8]; 10694 u8 event_arm[0x1]; 10695 u8 reserved_at_21[0x1b]; 10696 u8 event_generation_mode[0x4]; 10697 u8 reserved_at_40[0x40]; 10698 }; 10699 10700 struct mlx5_ifc_mcqs_reg_bits { 10701 u8 last_index_flag[0x1]; 10702 u8 reserved_at_1[0x7]; 10703 u8 fw_device[0x8]; 10704 u8 component_index[0x10]; 10705 10706 u8 reserved_at_20[0x10]; 10707 u8 identifier[0x10]; 10708 10709 u8 reserved_at_40[0x17]; 10710 u8 component_status[0x5]; 10711 u8 component_update_state[0x4]; 10712 10713 u8 last_update_state_changer_type[0x4]; 10714 u8 last_update_state_changer_host_id[0x4]; 10715 u8 reserved_at_68[0x18]; 10716 }; 10717 10718 struct mlx5_ifc_mcqi_cap_bits { 10719 u8 supported_info_bitmask[0x20]; 10720 10721 u8 component_size[0x20]; 10722 10723 u8 max_component_size[0x20]; 10724 10725 u8 log_mcda_word_size[0x4]; 10726 u8 reserved_at_64[0xc]; 10727 u8 mcda_max_write_size[0x10]; 10728 10729 u8 rd_en[0x1]; 10730 u8 reserved_at_81[0x1]; 10731 u8 match_chip_id[0x1]; 10732 u8 match_psid[0x1]; 10733 u8 check_user_timestamp[0x1]; 10734 u8 match_base_guid_mac[0x1]; 10735 u8 reserved_at_86[0x1a]; 10736 }; 10737 10738 struct mlx5_ifc_mcqi_version_bits { 10739 u8 reserved_at_0[0x2]; 10740 u8 build_time_valid[0x1]; 10741 u8 user_defined_time_valid[0x1]; 10742 u8 reserved_at_4[0x14]; 10743 u8 version_string_length[0x8]; 10744 10745 u8 version[0x20]; 10746 10747 u8 build_time[0x40]; 10748 10749 u8 user_defined_time[0x40]; 10750 10751 u8 build_tool_version[0x20]; 10752 10753 u8 reserved_at_e0[0x20]; 10754 10755 u8 version_string[92][0x8]; 10756 }; 10757 10758 struct mlx5_ifc_mcqi_activation_method_bits { 10759 u8 pending_server_ac_power_cycle[0x1]; 10760 u8 pending_server_dc_power_cycle[0x1]; 10761 u8 pending_server_reboot[0x1]; 10762 u8 pending_fw_reset[0x1]; 10763 u8 auto_activate[0x1]; 10764 u8 all_hosts_sync[0x1]; 10765 u8 device_hw_reset[0x1]; 10766 u8 reserved_at_7[0x19]; 10767 }; 10768 10769 union mlx5_ifc_mcqi_reg_data_bits { 10770 struct mlx5_ifc_mcqi_cap_bits mcqi_caps; 10771 struct mlx5_ifc_mcqi_version_bits mcqi_version; 10772 struct mlx5_ifc_mcqi_activation_method_bits mcqi_activation_mathod; 10773 }; 10774 10775 struct mlx5_ifc_mcqi_reg_bits { 10776 u8 read_pending_component[0x1]; 10777 u8 reserved_at_1[0xf]; 10778 u8 component_index[0x10]; 10779 10780 u8 reserved_at_20[0x20]; 10781 10782 u8 reserved_at_40[0x1b]; 10783 u8 info_type[0x5]; 10784 10785 u8 info_size[0x20]; 10786 10787 u8 offset[0x20]; 10788 10789 u8 reserved_at_a0[0x10]; 10790 u8 data_size[0x10]; 10791 10792 union mlx5_ifc_mcqi_reg_data_bits data[]; 10793 }; 10794 10795 struct mlx5_ifc_mcc_reg_bits { 10796 u8 reserved_at_0[0x4]; 10797 u8 time_elapsed_since_last_cmd[0xc]; 10798 u8 reserved_at_10[0x8]; 10799 u8 instruction[0x8]; 10800 10801 u8 reserved_at_20[0x10]; 10802 u8 component_index[0x10]; 10803 10804 u8 reserved_at_40[0x8]; 10805 u8 update_handle[0x18]; 10806 10807 u8 handle_owner_type[0x4]; 10808 u8 handle_owner_host_id[0x4]; 10809 u8 reserved_at_68[0x1]; 10810 u8 control_progress[0x7]; 10811 u8 error_code[0x8]; 10812 u8 reserved_at_78[0x4]; 10813 u8 control_state[0x4]; 10814 10815 u8 component_size[0x20]; 10816 10817 u8 reserved_at_a0[0x60]; 10818 }; 10819 10820 struct mlx5_ifc_mcda_reg_bits { 10821 u8 reserved_at_0[0x8]; 10822 u8 update_handle[0x18]; 10823 10824 u8 offset[0x20]; 10825 10826 u8 reserved_at_40[0x10]; 10827 u8 size[0x10]; 10828 10829 u8 reserved_at_60[0x20]; 10830 10831 u8 data[][0x20]; 10832 }; 10833 10834 enum { 10835 MLX5_MFRL_REG_RESET_STATE_IDLE = 0, 10836 MLX5_MFRL_REG_RESET_STATE_IN_NEGOTIATION = 1, 10837 MLX5_MFRL_REG_RESET_STATE_RESET_IN_PROGRESS = 2, 10838 MLX5_MFRL_REG_RESET_STATE_TIMEOUT = 3, 10839 MLX5_MFRL_REG_RESET_STATE_NACK = 4, 10840 }; 10841 10842 enum { 10843 MLX5_MFRL_REG_RESET_TYPE_FULL_CHIP = BIT(0), 10844 MLX5_MFRL_REG_RESET_TYPE_NET_PORT_ALIVE = BIT(1), 10845 }; 10846 10847 enum { 10848 MLX5_MFRL_REG_RESET_LEVEL0 = BIT(0), 10849 MLX5_MFRL_REG_RESET_LEVEL3 = BIT(3), 10850 MLX5_MFRL_REG_RESET_LEVEL6 = BIT(6), 10851 }; 10852 10853 struct mlx5_ifc_mfrl_reg_bits { 10854 u8 reserved_at_0[0x20]; 10855 10856 u8 reserved_at_20[0x2]; 10857 u8 pci_sync_for_fw_update_start[0x1]; 10858 u8 pci_sync_for_fw_update_resp[0x2]; 10859 u8 rst_type_sel[0x3]; 10860 u8 reserved_at_28[0x4]; 10861 u8 reset_state[0x4]; 10862 u8 reset_type[0x8]; 10863 u8 reset_level[0x8]; 10864 }; 10865 10866 struct mlx5_ifc_mirc_reg_bits { 10867 u8 reserved_at_0[0x18]; 10868 u8 status_code[0x8]; 10869 10870 u8 reserved_at_20[0x20]; 10871 }; 10872 10873 struct mlx5_ifc_pddr_monitor_opcode_bits { 10874 u8 reserved_at_0[0x10]; 10875 u8 monitor_opcode[0x10]; 10876 }; 10877 10878 union mlx5_ifc_pddr_troubleshooting_page_status_opcode_auto_bits { 10879 struct mlx5_ifc_pddr_monitor_opcode_bits pddr_monitor_opcode; 10880 u8 reserved_at_0[0x20]; 10881 }; 10882 10883 enum { 10884 /* Monitor opcodes */ 10885 MLX5_PDDR_REG_TRBLSH_GROUP_OPCODE_MONITOR = 0x0, 10886 }; 10887 10888 struct mlx5_ifc_pddr_troubleshooting_page_bits { 10889 u8 reserved_at_0[0x10]; 10890 u8 group_opcode[0x10]; 10891 10892 union mlx5_ifc_pddr_troubleshooting_page_status_opcode_auto_bits status_opcode; 10893 10894 u8 reserved_at_40[0x20]; 10895 10896 u8 status_message[59][0x20]; 10897 }; 10898 10899 union mlx5_ifc_pddr_reg_page_data_auto_bits { 10900 struct mlx5_ifc_pddr_troubleshooting_page_bits pddr_troubleshooting_page; 10901 u8 reserved_at_0[0x7c0]; 10902 }; 10903 10904 enum { 10905 MLX5_PDDR_REG_PAGE_SELECT_TROUBLESHOOTING_INFO_PAGE = 0x1, 10906 }; 10907 10908 struct mlx5_ifc_pddr_reg_bits { 10909 u8 reserved_at_0[0x8]; 10910 u8 local_port[0x8]; 10911 u8 pnat[0x2]; 10912 u8 reserved_at_12[0xe]; 10913 10914 u8 reserved_at_20[0x18]; 10915 u8 page_select[0x8]; 10916 10917 union mlx5_ifc_pddr_reg_page_data_auto_bits page_data; 10918 }; 10919 10920 struct mlx5_ifc_mrtc_reg_bits { 10921 u8 time_synced[0x1]; 10922 u8 reserved_at_1[0x1f]; 10923 10924 u8 reserved_at_20[0x20]; 10925 10926 u8 time_h[0x20]; 10927 10928 u8 time_l[0x20]; 10929 }; 10930 10931 struct mlx5_ifc_mtmp_reg_bits { 10932 u8 reserved_at_0[0x14]; 10933 u8 sensor_index[0xc]; 10934 10935 u8 reserved_at_20[0x10]; 10936 u8 temperature[0x10]; 10937 10938 u8 mte[0x1]; 10939 u8 mtr[0x1]; 10940 u8 reserved_at_42[0xe]; 10941 u8 max_temperature[0x10]; 10942 10943 u8 tee[0x2]; 10944 u8 reserved_at_62[0xe]; 10945 u8 temp_threshold_hi[0x10]; 10946 10947 u8 reserved_at_80[0x10]; 10948 u8 temp_threshold_lo[0x10]; 10949 10950 u8 reserved_at_a0[0x20]; 10951 10952 u8 sensor_name_hi[0x20]; 10953 u8 sensor_name_lo[0x20]; 10954 }; 10955 10956 union mlx5_ifc_ports_control_registers_document_bits { 10957 struct mlx5_ifc_bufferx_reg_bits bufferx_reg; 10958 struct mlx5_ifc_eth_2819_cntrs_grp_data_layout_bits eth_2819_cntrs_grp_data_layout; 10959 struct mlx5_ifc_eth_2863_cntrs_grp_data_layout_bits eth_2863_cntrs_grp_data_layout; 10960 struct mlx5_ifc_eth_3635_cntrs_grp_data_layout_bits eth_3635_cntrs_grp_data_layout; 10961 struct mlx5_ifc_eth_802_3_cntrs_grp_data_layout_bits eth_802_3_cntrs_grp_data_layout; 10962 struct mlx5_ifc_eth_extended_cntrs_grp_data_layout_bits eth_extended_cntrs_grp_data_layout; 10963 struct mlx5_ifc_eth_per_prio_grp_data_layout_bits eth_per_prio_grp_data_layout; 10964 struct mlx5_ifc_eth_per_tc_prio_grp_data_layout_bits eth_per_tc_prio_grp_data_layout; 10965 struct mlx5_ifc_eth_per_tc_congest_prio_grp_data_layout_bits eth_per_tc_congest_prio_grp_data_layout; 10966 struct mlx5_ifc_lane_2_module_mapping_bits lane_2_module_mapping; 10967 struct mlx5_ifc_pamp_reg_bits pamp_reg; 10968 struct mlx5_ifc_paos_reg_bits paos_reg; 10969 struct mlx5_ifc_pcap_reg_bits pcap_reg; 10970 struct mlx5_ifc_pddr_monitor_opcode_bits pddr_monitor_opcode; 10971 struct mlx5_ifc_pddr_reg_bits pddr_reg; 10972 struct mlx5_ifc_pddr_troubleshooting_page_bits pddr_troubleshooting_page; 10973 struct mlx5_ifc_peir_reg_bits peir_reg; 10974 struct mlx5_ifc_pelc_reg_bits pelc_reg; 10975 struct mlx5_ifc_pfcc_reg_bits pfcc_reg; 10976 struct mlx5_ifc_ib_port_cntrs_grp_data_layout_bits ib_port_cntrs_grp_data_layout; 10977 struct mlx5_ifc_phys_layer_cntrs_bits phys_layer_cntrs; 10978 struct mlx5_ifc_pifr_reg_bits pifr_reg; 10979 struct mlx5_ifc_pipg_reg_bits pipg_reg; 10980 struct mlx5_ifc_plbf_reg_bits plbf_reg; 10981 struct mlx5_ifc_plib_reg_bits plib_reg; 10982 struct mlx5_ifc_plpc_reg_bits plpc_reg; 10983 struct mlx5_ifc_pmaos_reg_bits pmaos_reg; 10984 struct mlx5_ifc_pmlp_reg_bits pmlp_reg; 10985 struct mlx5_ifc_pmlpn_reg_bits pmlpn_reg; 10986 struct mlx5_ifc_pmpc_reg_bits pmpc_reg; 10987 struct mlx5_ifc_pmpe_reg_bits pmpe_reg; 10988 struct mlx5_ifc_pmpr_reg_bits pmpr_reg; 10989 struct mlx5_ifc_pmtu_reg_bits pmtu_reg; 10990 struct mlx5_ifc_ppad_reg_bits ppad_reg; 10991 struct mlx5_ifc_ppcnt_reg_bits ppcnt_reg; 10992 struct mlx5_ifc_mpein_reg_bits mpein_reg; 10993 struct mlx5_ifc_mpcnt_reg_bits mpcnt_reg; 10994 struct mlx5_ifc_pplm_reg_bits pplm_reg; 10995 struct mlx5_ifc_pplr_reg_bits pplr_reg; 10996 struct mlx5_ifc_ppsc_reg_bits ppsc_reg; 10997 struct mlx5_ifc_pqdr_reg_bits pqdr_reg; 10998 struct mlx5_ifc_pspa_reg_bits pspa_reg; 10999 struct mlx5_ifc_ptas_reg_bits ptas_reg; 11000 struct mlx5_ifc_ptys_reg_bits ptys_reg; 11001 struct mlx5_ifc_mlcr_reg_bits mlcr_reg; 11002 struct mlx5_ifc_pude_reg_bits pude_reg; 11003 struct mlx5_ifc_pvlc_reg_bits pvlc_reg; 11004 struct mlx5_ifc_slrg_reg_bits slrg_reg; 11005 struct mlx5_ifc_sltp_reg_bits sltp_reg; 11006 struct mlx5_ifc_mtpps_reg_bits mtpps_reg; 11007 struct mlx5_ifc_mtppse_reg_bits mtppse_reg; 11008 struct mlx5_ifc_fpga_access_reg_bits fpga_access_reg; 11009 struct mlx5_ifc_fpga_ctrl_bits fpga_ctrl_bits; 11010 struct mlx5_ifc_fpga_cap_bits fpga_cap_bits; 11011 struct mlx5_ifc_mcqi_reg_bits mcqi_reg; 11012 struct mlx5_ifc_mcc_reg_bits mcc_reg; 11013 struct mlx5_ifc_mcda_reg_bits mcda_reg; 11014 struct mlx5_ifc_mirc_reg_bits mirc_reg; 11015 struct mlx5_ifc_mfrl_reg_bits mfrl_reg; 11016 struct mlx5_ifc_mtutc_reg_bits mtutc_reg; 11017 struct mlx5_ifc_mrtc_reg_bits mrtc_reg; 11018 struct mlx5_ifc_mtmp_reg_bits mtmp_reg; 11019 u8 reserved_at_0[0x60e0]; 11020 }; 11021 11022 union mlx5_ifc_debug_enhancements_document_bits { 11023 struct mlx5_ifc_health_buffer_bits health_buffer; 11024 u8 reserved_at_0[0x200]; 11025 }; 11026 11027 union mlx5_ifc_uplink_pci_interface_document_bits { 11028 struct mlx5_ifc_initial_seg_bits initial_seg; 11029 u8 reserved_at_0[0x20060]; 11030 }; 11031 11032 struct mlx5_ifc_set_flow_table_root_out_bits { 11033 u8 status[0x8]; 11034 u8 reserved_at_8[0x18]; 11035 11036 u8 syndrome[0x20]; 11037 11038 u8 reserved_at_40[0x40]; 11039 }; 11040 11041 struct mlx5_ifc_set_flow_table_root_in_bits { 11042 u8 opcode[0x10]; 11043 u8 reserved_at_10[0x10]; 11044 11045 u8 reserved_at_20[0x10]; 11046 u8 op_mod[0x10]; 11047 11048 u8 other_vport[0x1]; 11049 u8 reserved_at_41[0xf]; 11050 u8 vport_number[0x10]; 11051 11052 u8 reserved_at_60[0x20]; 11053 11054 u8 table_type[0x8]; 11055 u8 reserved_at_88[0x7]; 11056 u8 table_of_other_vport[0x1]; 11057 u8 table_vport_number[0x10]; 11058 11059 u8 reserved_at_a0[0x8]; 11060 u8 table_id[0x18]; 11061 11062 u8 reserved_at_c0[0x8]; 11063 u8 underlay_qpn[0x18]; 11064 u8 table_eswitch_owner_vhca_id_valid[0x1]; 11065 u8 reserved_at_e1[0xf]; 11066 u8 table_eswitch_owner_vhca_id[0x10]; 11067 u8 reserved_at_100[0x100]; 11068 }; 11069 11070 enum { 11071 MLX5_MODIFY_FLOW_TABLE_MISS_TABLE_ID = (1UL << 0), 11072 MLX5_MODIFY_FLOW_TABLE_LAG_NEXT_TABLE_ID = (1UL << 15), 11073 }; 11074 11075 struct mlx5_ifc_modify_flow_table_out_bits { 11076 u8 status[0x8]; 11077 u8 reserved_at_8[0x18]; 11078 11079 u8 syndrome[0x20]; 11080 11081 u8 reserved_at_40[0x40]; 11082 }; 11083 11084 struct mlx5_ifc_modify_flow_table_in_bits { 11085 u8 opcode[0x10]; 11086 u8 reserved_at_10[0x10]; 11087 11088 u8 reserved_at_20[0x10]; 11089 u8 op_mod[0x10]; 11090 11091 u8 other_vport[0x1]; 11092 u8 reserved_at_41[0xf]; 11093 u8 vport_number[0x10]; 11094 11095 u8 reserved_at_60[0x10]; 11096 u8 modify_field_select[0x10]; 11097 11098 u8 table_type[0x8]; 11099 u8 reserved_at_88[0x18]; 11100 11101 u8 reserved_at_a0[0x8]; 11102 u8 table_id[0x18]; 11103 11104 struct mlx5_ifc_flow_table_context_bits flow_table_context; 11105 }; 11106 11107 struct mlx5_ifc_ets_tcn_config_reg_bits { 11108 u8 g[0x1]; 11109 u8 b[0x1]; 11110 u8 r[0x1]; 11111 u8 reserved_at_3[0x9]; 11112 u8 group[0x4]; 11113 u8 reserved_at_10[0x9]; 11114 u8 bw_allocation[0x7]; 11115 11116 u8 reserved_at_20[0xc]; 11117 u8 max_bw_units[0x4]; 11118 u8 reserved_at_30[0x8]; 11119 u8 max_bw_value[0x8]; 11120 }; 11121 11122 struct mlx5_ifc_ets_global_config_reg_bits { 11123 u8 reserved_at_0[0x2]; 11124 u8 r[0x1]; 11125 u8 reserved_at_3[0x1d]; 11126 11127 u8 reserved_at_20[0xc]; 11128 u8 max_bw_units[0x4]; 11129 u8 reserved_at_30[0x8]; 11130 u8 max_bw_value[0x8]; 11131 }; 11132 11133 struct mlx5_ifc_qetc_reg_bits { 11134 u8 reserved_at_0[0x8]; 11135 u8 port_number[0x8]; 11136 u8 reserved_at_10[0x30]; 11137 11138 struct mlx5_ifc_ets_tcn_config_reg_bits tc_configuration[0x8]; 11139 struct mlx5_ifc_ets_global_config_reg_bits global_configuration; 11140 }; 11141 11142 struct mlx5_ifc_qpdpm_dscp_reg_bits { 11143 u8 e[0x1]; 11144 u8 reserved_at_01[0x0b]; 11145 u8 prio[0x04]; 11146 }; 11147 11148 struct mlx5_ifc_qpdpm_reg_bits { 11149 u8 reserved_at_0[0x8]; 11150 u8 local_port[0x8]; 11151 u8 reserved_at_10[0x10]; 11152 struct mlx5_ifc_qpdpm_dscp_reg_bits dscp[64]; 11153 }; 11154 11155 struct mlx5_ifc_qpts_reg_bits { 11156 u8 reserved_at_0[0x8]; 11157 u8 local_port[0x8]; 11158 u8 reserved_at_10[0x2d]; 11159 u8 trust_state[0x3]; 11160 }; 11161 11162 struct mlx5_ifc_pptb_reg_bits { 11163 u8 reserved_at_0[0x2]; 11164 u8 mm[0x2]; 11165 u8 reserved_at_4[0x4]; 11166 u8 local_port[0x8]; 11167 u8 reserved_at_10[0x6]; 11168 u8 cm[0x1]; 11169 u8 um[0x1]; 11170 u8 pm[0x8]; 11171 11172 u8 prio_x_buff[0x20]; 11173 11174 u8 pm_msb[0x8]; 11175 u8 reserved_at_48[0x10]; 11176 u8 ctrl_buff[0x4]; 11177 u8 untagged_buff[0x4]; 11178 }; 11179 11180 struct mlx5_ifc_sbcam_reg_bits { 11181 u8 reserved_at_0[0x8]; 11182 u8 feature_group[0x8]; 11183 u8 reserved_at_10[0x8]; 11184 u8 access_reg_group[0x8]; 11185 11186 u8 reserved_at_20[0x20]; 11187 11188 u8 sb_access_reg_cap_mask[4][0x20]; 11189 11190 u8 reserved_at_c0[0x80]; 11191 11192 u8 sb_feature_cap_mask[4][0x20]; 11193 11194 u8 reserved_at_1c0[0x40]; 11195 11196 u8 cap_total_buffer_size[0x20]; 11197 11198 u8 cap_cell_size[0x10]; 11199 u8 cap_max_pg_buffers[0x8]; 11200 u8 cap_num_pool_supported[0x8]; 11201 11202 u8 reserved_at_240[0x8]; 11203 u8 cap_sbsr_stat_size[0x8]; 11204 u8 cap_max_tclass_data[0x8]; 11205 u8 cap_max_cpu_ingress_tclass_sb[0x8]; 11206 }; 11207 11208 struct mlx5_ifc_pbmc_reg_bits { 11209 u8 reserved_at_0[0x8]; 11210 u8 local_port[0x8]; 11211 u8 reserved_at_10[0x10]; 11212 11213 u8 xoff_timer_value[0x10]; 11214 u8 xoff_refresh[0x10]; 11215 11216 u8 reserved_at_40[0x9]; 11217 u8 fullness_threshold[0x7]; 11218 u8 port_buffer_size[0x10]; 11219 11220 struct mlx5_ifc_bufferx_reg_bits buffer[10]; 11221 11222 u8 reserved_at_2e0[0x80]; 11223 }; 11224 11225 struct mlx5_ifc_sbpr_reg_bits { 11226 u8 desc[0x1]; 11227 u8 snap[0x1]; 11228 u8 reserved_at_2[0x4]; 11229 u8 dir[0x2]; 11230 u8 reserved_at_8[0x14]; 11231 u8 pool[0x4]; 11232 11233 u8 infi_size[0x1]; 11234 u8 reserved_at_21[0x7]; 11235 u8 size[0x18]; 11236 11237 u8 reserved_at_40[0x1c]; 11238 u8 mode[0x4]; 11239 11240 u8 reserved_at_60[0x8]; 11241 u8 buff_occupancy[0x18]; 11242 11243 u8 clr[0x1]; 11244 u8 reserved_at_81[0x7]; 11245 u8 max_buff_occupancy[0x18]; 11246 11247 u8 reserved_at_a0[0x8]; 11248 u8 ext_buff_occupancy[0x18]; 11249 }; 11250 11251 struct mlx5_ifc_sbcm_reg_bits { 11252 u8 desc[0x1]; 11253 u8 snap[0x1]; 11254 u8 reserved_at_2[0x6]; 11255 u8 local_port[0x8]; 11256 u8 pnat[0x2]; 11257 u8 pg_buff[0x6]; 11258 u8 reserved_at_18[0x6]; 11259 u8 dir[0x2]; 11260 11261 u8 reserved_at_20[0x1f]; 11262 u8 exc[0x1]; 11263 11264 u8 reserved_at_40[0x40]; 11265 11266 u8 reserved_at_80[0x8]; 11267 u8 buff_occupancy[0x18]; 11268 11269 u8 clr[0x1]; 11270 u8 reserved_at_a1[0x7]; 11271 u8 max_buff_occupancy[0x18]; 11272 11273 u8 reserved_at_c0[0x8]; 11274 u8 min_buff[0x18]; 11275 11276 u8 infi_max[0x1]; 11277 u8 reserved_at_e1[0x7]; 11278 u8 max_buff[0x18]; 11279 11280 u8 reserved_at_100[0x20]; 11281 11282 u8 reserved_at_120[0x1c]; 11283 u8 pool[0x4]; 11284 }; 11285 11286 struct mlx5_ifc_qtct_reg_bits { 11287 u8 reserved_at_0[0x8]; 11288 u8 port_number[0x8]; 11289 u8 reserved_at_10[0xd]; 11290 u8 prio[0x3]; 11291 11292 u8 reserved_at_20[0x1d]; 11293 u8 tclass[0x3]; 11294 }; 11295 11296 struct mlx5_ifc_mcia_reg_bits { 11297 u8 l[0x1]; 11298 u8 reserved_at_1[0x7]; 11299 u8 module[0x8]; 11300 u8 reserved_at_10[0x8]; 11301 u8 status[0x8]; 11302 11303 u8 i2c_device_address[0x8]; 11304 u8 page_number[0x8]; 11305 u8 device_address[0x10]; 11306 11307 u8 reserved_at_40[0x10]; 11308 u8 size[0x10]; 11309 11310 u8 reserved_at_60[0x20]; 11311 11312 u8 dword_0[0x20]; 11313 u8 dword_1[0x20]; 11314 u8 dword_2[0x20]; 11315 u8 dword_3[0x20]; 11316 u8 dword_4[0x20]; 11317 u8 dword_5[0x20]; 11318 u8 dword_6[0x20]; 11319 u8 dword_7[0x20]; 11320 u8 dword_8[0x20]; 11321 u8 dword_9[0x20]; 11322 u8 dword_10[0x20]; 11323 u8 dword_11[0x20]; 11324 }; 11325 11326 struct mlx5_ifc_dcbx_param_bits { 11327 u8 dcbx_cee_cap[0x1]; 11328 u8 dcbx_ieee_cap[0x1]; 11329 u8 dcbx_standby_cap[0x1]; 11330 u8 reserved_at_3[0x5]; 11331 u8 port_number[0x8]; 11332 u8 reserved_at_10[0xa]; 11333 u8 max_application_table_size[6]; 11334 u8 reserved_at_20[0x15]; 11335 u8 version_oper[0x3]; 11336 u8 reserved_at_38[5]; 11337 u8 version_admin[0x3]; 11338 u8 willing_admin[0x1]; 11339 u8 reserved_at_41[0x3]; 11340 u8 pfc_cap_oper[0x4]; 11341 u8 reserved_at_48[0x4]; 11342 u8 pfc_cap_admin[0x4]; 11343 u8 reserved_at_50[0x4]; 11344 u8 num_of_tc_oper[0x4]; 11345 u8 reserved_at_58[0x4]; 11346 u8 num_of_tc_admin[0x4]; 11347 u8 remote_willing[0x1]; 11348 u8 reserved_at_61[3]; 11349 u8 remote_pfc_cap[4]; 11350 u8 reserved_at_68[0x14]; 11351 u8 remote_num_of_tc[0x4]; 11352 u8 reserved_at_80[0x18]; 11353 u8 error[0x8]; 11354 u8 reserved_at_a0[0x160]; 11355 }; 11356 11357 enum { 11358 MLX5_LAG_PORT_SELECT_MODE_QUEUE_AFFINITY = 0, 11359 MLX5_LAG_PORT_SELECT_MODE_PORT_SELECT_FT = 1, 11360 MLX5_LAG_PORT_SELECT_MODE_PORT_SELECT_MPESW = 2, 11361 }; 11362 11363 struct mlx5_ifc_lagc_bits { 11364 u8 fdb_selection_mode[0x1]; 11365 u8 reserved_at_1[0x14]; 11366 u8 port_select_mode[0x3]; 11367 u8 reserved_at_18[0x5]; 11368 u8 lag_state[0x3]; 11369 11370 u8 reserved_at_20[0xc]; 11371 u8 active_port[0x4]; 11372 u8 reserved_at_30[0x4]; 11373 u8 tx_remap_affinity_2[0x4]; 11374 u8 reserved_at_38[0x4]; 11375 u8 tx_remap_affinity_1[0x4]; 11376 }; 11377 11378 struct mlx5_ifc_create_lag_out_bits { 11379 u8 status[0x8]; 11380 u8 reserved_at_8[0x18]; 11381 11382 u8 syndrome[0x20]; 11383 11384 u8 reserved_at_40[0x40]; 11385 }; 11386 11387 struct mlx5_ifc_create_lag_in_bits { 11388 u8 opcode[0x10]; 11389 u8 reserved_at_10[0x10]; 11390 11391 u8 reserved_at_20[0x10]; 11392 u8 op_mod[0x10]; 11393 11394 struct mlx5_ifc_lagc_bits ctx; 11395 }; 11396 11397 struct mlx5_ifc_modify_lag_out_bits { 11398 u8 status[0x8]; 11399 u8 reserved_at_8[0x18]; 11400 11401 u8 syndrome[0x20]; 11402 11403 u8 reserved_at_40[0x40]; 11404 }; 11405 11406 struct mlx5_ifc_modify_lag_in_bits { 11407 u8 opcode[0x10]; 11408 u8 reserved_at_10[0x10]; 11409 11410 u8 reserved_at_20[0x10]; 11411 u8 op_mod[0x10]; 11412 11413 u8 reserved_at_40[0x20]; 11414 u8 field_select[0x20]; 11415 11416 struct mlx5_ifc_lagc_bits ctx; 11417 }; 11418 11419 struct mlx5_ifc_query_lag_out_bits { 11420 u8 status[0x8]; 11421 u8 reserved_at_8[0x18]; 11422 11423 u8 syndrome[0x20]; 11424 11425 struct mlx5_ifc_lagc_bits ctx; 11426 }; 11427 11428 struct mlx5_ifc_query_lag_in_bits { 11429 u8 opcode[0x10]; 11430 u8 reserved_at_10[0x10]; 11431 11432 u8 reserved_at_20[0x10]; 11433 u8 op_mod[0x10]; 11434 11435 u8 reserved_at_40[0x40]; 11436 }; 11437 11438 struct mlx5_ifc_destroy_lag_out_bits { 11439 u8 status[0x8]; 11440 u8 reserved_at_8[0x18]; 11441 11442 u8 syndrome[0x20]; 11443 11444 u8 reserved_at_40[0x40]; 11445 }; 11446 11447 struct mlx5_ifc_destroy_lag_in_bits { 11448 u8 opcode[0x10]; 11449 u8 reserved_at_10[0x10]; 11450 11451 u8 reserved_at_20[0x10]; 11452 u8 op_mod[0x10]; 11453 11454 u8 reserved_at_40[0x40]; 11455 }; 11456 11457 struct mlx5_ifc_create_vport_lag_out_bits { 11458 u8 status[0x8]; 11459 u8 reserved_at_8[0x18]; 11460 11461 u8 syndrome[0x20]; 11462 11463 u8 reserved_at_40[0x40]; 11464 }; 11465 11466 struct mlx5_ifc_create_vport_lag_in_bits { 11467 u8 opcode[0x10]; 11468 u8 reserved_at_10[0x10]; 11469 11470 u8 reserved_at_20[0x10]; 11471 u8 op_mod[0x10]; 11472 11473 u8 reserved_at_40[0x40]; 11474 }; 11475 11476 struct mlx5_ifc_destroy_vport_lag_out_bits { 11477 u8 status[0x8]; 11478 u8 reserved_at_8[0x18]; 11479 11480 u8 syndrome[0x20]; 11481 11482 u8 reserved_at_40[0x40]; 11483 }; 11484 11485 struct mlx5_ifc_destroy_vport_lag_in_bits { 11486 u8 opcode[0x10]; 11487 u8 reserved_at_10[0x10]; 11488 11489 u8 reserved_at_20[0x10]; 11490 u8 op_mod[0x10]; 11491 11492 u8 reserved_at_40[0x40]; 11493 }; 11494 11495 enum { 11496 MLX5_MODIFY_MEMIC_OP_MOD_ALLOC, 11497 MLX5_MODIFY_MEMIC_OP_MOD_DEALLOC, 11498 }; 11499 11500 struct mlx5_ifc_modify_memic_in_bits { 11501 u8 opcode[0x10]; 11502 u8 uid[0x10]; 11503 11504 u8 reserved_at_20[0x10]; 11505 u8 op_mod[0x10]; 11506 11507 u8 reserved_at_40[0x20]; 11508 11509 u8 reserved_at_60[0x18]; 11510 u8 memic_operation_type[0x8]; 11511 11512 u8 memic_start_addr[0x40]; 11513 11514 u8 reserved_at_c0[0x140]; 11515 }; 11516 11517 struct mlx5_ifc_modify_memic_out_bits { 11518 u8 status[0x8]; 11519 u8 reserved_at_8[0x18]; 11520 11521 u8 syndrome[0x20]; 11522 11523 u8 reserved_at_40[0x40]; 11524 11525 u8 memic_operation_addr[0x40]; 11526 11527 u8 reserved_at_c0[0x140]; 11528 }; 11529 11530 struct mlx5_ifc_alloc_memic_in_bits { 11531 u8 opcode[0x10]; 11532 u8 reserved_at_10[0x10]; 11533 11534 u8 reserved_at_20[0x10]; 11535 u8 op_mod[0x10]; 11536 11537 u8 reserved_at_30[0x20]; 11538 11539 u8 reserved_at_40[0x18]; 11540 u8 log_memic_addr_alignment[0x8]; 11541 11542 u8 range_start_addr[0x40]; 11543 11544 u8 range_size[0x20]; 11545 11546 u8 memic_size[0x20]; 11547 }; 11548 11549 struct mlx5_ifc_alloc_memic_out_bits { 11550 u8 status[0x8]; 11551 u8 reserved_at_8[0x18]; 11552 11553 u8 syndrome[0x20]; 11554 11555 u8 memic_start_addr[0x40]; 11556 }; 11557 11558 struct mlx5_ifc_dealloc_memic_in_bits { 11559 u8 opcode[0x10]; 11560 u8 reserved_at_10[0x10]; 11561 11562 u8 reserved_at_20[0x10]; 11563 u8 op_mod[0x10]; 11564 11565 u8 reserved_at_40[0x40]; 11566 11567 u8 memic_start_addr[0x40]; 11568 11569 u8 memic_size[0x20]; 11570 11571 u8 reserved_at_e0[0x20]; 11572 }; 11573 11574 struct mlx5_ifc_dealloc_memic_out_bits { 11575 u8 status[0x8]; 11576 u8 reserved_at_8[0x18]; 11577 11578 u8 syndrome[0x20]; 11579 11580 u8 reserved_at_40[0x40]; 11581 }; 11582 11583 struct mlx5_ifc_umem_bits { 11584 u8 reserved_at_0[0x80]; 11585 11586 u8 ats[0x1]; 11587 u8 reserved_at_81[0x1a]; 11588 u8 log_page_size[0x5]; 11589 11590 u8 page_offset[0x20]; 11591 11592 u8 num_of_mtt[0x40]; 11593 11594 struct mlx5_ifc_mtt_bits mtt[]; 11595 }; 11596 11597 struct mlx5_ifc_uctx_bits { 11598 u8 cap[0x20]; 11599 11600 u8 reserved_at_20[0x160]; 11601 }; 11602 11603 struct mlx5_ifc_sw_icm_bits { 11604 u8 modify_field_select[0x40]; 11605 11606 u8 reserved_at_40[0x18]; 11607 u8 log_sw_icm_size[0x8]; 11608 11609 u8 reserved_at_60[0x20]; 11610 11611 u8 sw_icm_start_addr[0x40]; 11612 11613 u8 reserved_at_c0[0x140]; 11614 }; 11615 11616 struct mlx5_ifc_geneve_tlv_option_bits { 11617 u8 modify_field_select[0x40]; 11618 11619 u8 reserved_at_40[0x18]; 11620 u8 geneve_option_fte_index[0x8]; 11621 11622 u8 option_class[0x10]; 11623 u8 option_type[0x8]; 11624 u8 reserved_at_78[0x3]; 11625 u8 option_data_length[0x5]; 11626 11627 u8 reserved_at_80[0x180]; 11628 }; 11629 11630 struct mlx5_ifc_create_umem_in_bits { 11631 u8 opcode[0x10]; 11632 u8 uid[0x10]; 11633 11634 u8 reserved_at_20[0x10]; 11635 u8 op_mod[0x10]; 11636 11637 u8 reserved_at_40[0x40]; 11638 11639 struct mlx5_ifc_umem_bits umem; 11640 }; 11641 11642 struct mlx5_ifc_create_umem_out_bits { 11643 u8 status[0x8]; 11644 u8 reserved_at_8[0x18]; 11645 11646 u8 syndrome[0x20]; 11647 11648 u8 reserved_at_40[0x8]; 11649 u8 umem_id[0x18]; 11650 11651 u8 reserved_at_60[0x20]; 11652 }; 11653 11654 struct mlx5_ifc_destroy_umem_in_bits { 11655 u8 opcode[0x10]; 11656 u8 uid[0x10]; 11657 11658 u8 reserved_at_20[0x10]; 11659 u8 op_mod[0x10]; 11660 11661 u8 reserved_at_40[0x8]; 11662 u8 umem_id[0x18]; 11663 11664 u8 reserved_at_60[0x20]; 11665 }; 11666 11667 struct mlx5_ifc_destroy_umem_out_bits { 11668 u8 status[0x8]; 11669 u8 reserved_at_8[0x18]; 11670 11671 u8 syndrome[0x20]; 11672 11673 u8 reserved_at_40[0x40]; 11674 }; 11675 11676 struct mlx5_ifc_create_uctx_in_bits { 11677 u8 opcode[0x10]; 11678 u8 reserved_at_10[0x10]; 11679 11680 u8 reserved_at_20[0x10]; 11681 u8 op_mod[0x10]; 11682 11683 u8 reserved_at_40[0x40]; 11684 11685 struct mlx5_ifc_uctx_bits uctx; 11686 }; 11687 11688 struct mlx5_ifc_create_uctx_out_bits { 11689 u8 status[0x8]; 11690 u8 reserved_at_8[0x18]; 11691 11692 u8 syndrome[0x20]; 11693 11694 u8 reserved_at_40[0x10]; 11695 u8 uid[0x10]; 11696 11697 u8 reserved_at_60[0x20]; 11698 }; 11699 11700 struct mlx5_ifc_destroy_uctx_in_bits { 11701 u8 opcode[0x10]; 11702 u8 reserved_at_10[0x10]; 11703 11704 u8 reserved_at_20[0x10]; 11705 u8 op_mod[0x10]; 11706 11707 u8 reserved_at_40[0x10]; 11708 u8 uid[0x10]; 11709 11710 u8 reserved_at_60[0x20]; 11711 }; 11712 11713 struct mlx5_ifc_destroy_uctx_out_bits { 11714 u8 status[0x8]; 11715 u8 reserved_at_8[0x18]; 11716 11717 u8 syndrome[0x20]; 11718 11719 u8 reserved_at_40[0x40]; 11720 }; 11721 11722 struct mlx5_ifc_create_sw_icm_in_bits { 11723 struct mlx5_ifc_general_obj_in_cmd_hdr_bits hdr; 11724 struct mlx5_ifc_sw_icm_bits sw_icm; 11725 }; 11726 11727 struct mlx5_ifc_create_geneve_tlv_option_in_bits { 11728 struct mlx5_ifc_general_obj_in_cmd_hdr_bits hdr; 11729 struct mlx5_ifc_geneve_tlv_option_bits geneve_tlv_opt; 11730 }; 11731 11732 struct mlx5_ifc_mtrc_string_db_param_bits { 11733 u8 string_db_base_address[0x20]; 11734 11735 u8 reserved_at_20[0x8]; 11736 u8 string_db_size[0x18]; 11737 }; 11738 11739 struct mlx5_ifc_mtrc_cap_bits { 11740 u8 trace_owner[0x1]; 11741 u8 trace_to_memory[0x1]; 11742 u8 reserved_at_2[0x4]; 11743 u8 trc_ver[0x2]; 11744 u8 reserved_at_8[0x14]; 11745 u8 num_string_db[0x4]; 11746 11747 u8 first_string_trace[0x8]; 11748 u8 num_string_trace[0x8]; 11749 u8 reserved_at_30[0x28]; 11750 11751 u8 log_max_trace_buffer_size[0x8]; 11752 11753 u8 reserved_at_60[0x20]; 11754 11755 struct mlx5_ifc_mtrc_string_db_param_bits string_db_param[8]; 11756 11757 u8 reserved_at_280[0x180]; 11758 }; 11759 11760 struct mlx5_ifc_mtrc_conf_bits { 11761 u8 reserved_at_0[0x1c]; 11762 u8 trace_mode[0x4]; 11763 u8 reserved_at_20[0x18]; 11764 u8 log_trace_buffer_size[0x8]; 11765 u8 trace_mkey[0x20]; 11766 u8 reserved_at_60[0x3a0]; 11767 }; 11768 11769 struct mlx5_ifc_mtrc_stdb_bits { 11770 u8 string_db_index[0x4]; 11771 u8 reserved_at_4[0x4]; 11772 u8 read_size[0x18]; 11773 u8 start_offset[0x20]; 11774 u8 string_db_data[]; 11775 }; 11776 11777 struct mlx5_ifc_mtrc_ctrl_bits { 11778 u8 trace_status[0x2]; 11779 u8 reserved_at_2[0x2]; 11780 u8 arm_event[0x1]; 11781 u8 reserved_at_5[0xb]; 11782 u8 modify_field_select[0x10]; 11783 u8 reserved_at_20[0x2b]; 11784 u8 current_timestamp52_32[0x15]; 11785 u8 current_timestamp31_0[0x20]; 11786 u8 reserved_at_80[0x180]; 11787 }; 11788 11789 struct mlx5_ifc_host_params_context_bits { 11790 u8 host_number[0x8]; 11791 u8 reserved_at_8[0x7]; 11792 u8 host_pf_disabled[0x1]; 11793 u8 host_num_of_vfs[0x10]; 11794 11795 u8 host_total_vfs[0x10]; 11796 u8 host_pci_bus[0x10]; 11797 11798 u8 reserved_at_40[0x10]; 11799 u8 host_pci_device[0x10]; 11800 11801 u8 reserved_at_60[0x10]; 11802 u8 host_pci_function[0x10]; 11803 11804 u8 reserved_at_80[0x180]; 11805 }; 11806 11807 struct mlx5_ifc_query_esw_functions_in_bits { 11808 u8 opcode[0x10]; 11809 u8 reserved_at_10[0x10]; 11810 11811 u8 reserved_at_20[0x10]; 11812 u8 op_mod[0x10]; 11813 11814 u8 reserved_at_40[0x40]; 11815 }; 11816 11817 struct mlx5_ifc_query_esw_functions_out_bits { 11818 u8 status[0x8]; 11819 u8 reserved_at_8[0x18]; 11820 11821 u8 syndrome[0x20]; 11822 11823 u8 reserved_at_40[0x40]; 11824 11825 struct mlx5_ifc_host_params_context_bits host_params_context; 11826 11827 u8 reserved_at_280[0x180]; 11828 u8 host_sf_enable[][0x40]; 11829 }; 11830 11831 struct mlx5_ifc_sf_partition_bits { 11832 u8 reserved_at_0[0x10]; 11833 u8 log_num_sf[0x8]; 11834 u8 log_sf_bar_size[0x8]; 11835 }; 11836 11837 struct mlx5_ifc_query_sf_partitions_out_bits { 11838 u8 status[0x8]; 11839 u8 reserved_at_8[0x18]; 11840 11841 u8 syndrome[0x20]; 11842 11843 u8 reserved_at_40[0x18]; 11844 u8 num_sf_partitions[0x8]; 11845 11846 u8 reserved_at_60[0x20]; 11847 11848 struct mlx5_ifc_sf_partition_bits sf_partition[]; 11849 }; 11850 11851 struct mlx5_ifc_query_sf_partitions_in_bits { 11852 u8 opcode[0x10]; 11853 u8 reserved_at_10[0x10]; 11854 11855 u8 reserved_at_20[0x10]; 11856 u8 op_mod[0x10]; 11857 11858 u8 reserved_at_40[0x40]; 11859 }; 11860 11861 struct mlx5_ifc_dealloc_sf_out_bits { 11862 u8 status[0x8]; 11863 u8 reserved_at_8[0x18]; 11864 11865 u8 syndrome[0x20]; 11866 11867 u8 reserved_at_40[0x40]; 11868 }; 11869 11870 struct mlx5_ifc_dealloc_sf_in_bits { 11871 u8 opcode[0x10]; 11872 u8 reserved_at_10[0x10]; 11873 11874 u8 reserved_at_20[0x10]; 11875 u8 op_mod[0x10]; 11876 11877 u8 reserved_at_40[0x10]; 11878 u8 function_id[0x10]; 11879 11880 u8 reserved_at_60[0x20]; 11881 }; 11882 11883 struct mlx5_ifc_alloc_sf_out_bits { 11884 u8 status[0x8]; 11885 u8 reserved_at_8[0x18]; 11886 11887 u8 syndrome[0x20]; 11888 11889 u8 reserved_at_40[0x40]; 11890 }; 11891 11892 struct mlx5_ifc_alloc_sf_in_bits { 11893 u8 opcode[0x10]; 11894 u8 reserved_at_10[0x10]; 11895 11896 u8 reserved_at_20[0x10]; 11897 u8 op_mod[0x10]; 11898 11899 u8 reserved_at_40[0x10]; 11900 u8 function_id[0x10]; 11901 11902 u8 reserved_at_60[0x20]; 11903 }; 11904 11905 struct mlx5_ifc_affiliated_event_header_bits { 11906 u8 reserved_at_0[0x10]; 11907 u8 obj_type[0x10]; 11908 11909 u8 obj_id[0x20]; 11910 }; 11911 11912 enum { 11913 MLX5_HCA_CAP_GENERAL_OBJECT_TYPES_ENCRYPTION_KEY = BIT_ULL(0xc), 11914 MLX5_HCA_CAP_GENERAL_OBJECT_TYPES_IPSEC = BIT_ULL(0x13), 11915 MLX5_HCA_CAP_GENERAL_OBJECT_TYPES_SAMPLER = BIT_ULL(0x20), 11916 MLX5_HCA_CAP_GENERAL_OBJECT_TYPES_FLOW_METER_ASO = BIT_ULL(0x24), 11917 }; 11918 11919 enum { 11920 MLX5_GENERAL_OBJECT_TYPES_ENCRYPTION_KEY = 0xc, 11921 MLX5_GENERAL_OBJECT_TYPES_IPSEC = 0x13, 11922 MLX5_GENERAL_OBJECT_TYPES_SAMPLER = 0x20, 11923 MLX5_GENERAL_OBJECT_TYPES_FLOW_METER_ASO = 0x24, 11924 MLX5_GENERAL_OBJECT_TYPES_MACSEC = 0x27, 11925 MLX5_GENERAL_OBJECT_TYPES_INT_KEK = 0x47, 11926 }; 11927 11928 enum { 11929 MLX5_IPSEC_OBJECT_ICV_LEN_16B, 11930 }; 11931 11932 enum { 11933 MLX5_IPSEC_ASO_REG_C_0_1 = 0x0, 11934 MLX5_IPSEC_ASO_REG_C_2_3 = 0x1, 11935 MLX5_IPSEC_ASO_REG_C_4_5 = 0x2, 11936 MLX5_IPSEC_ASO_REG_C_6_7 = 0x3, 11937 }; 11938 11939 enum { 11940 MLX5_IPSEC_ASO_MODE = 0x0, 11941 MLX5_IPSEC_ASO_REPLAY_PROTECTION = 0x1, 11942 MLX5_IPSEC_ASO_INC_SN = 0x2, 11943 }; 11944 11945 struct mlx5_ifc_ipsec_aso_bits { 11946 u8 valid[0x1]; 11947 u8 reserved_at_201[0x1]; 11948 u8 mode[0x2]; 11949 u8 window_sz[0x2]; 11950 u8 soft_lft_arm[0x1]; 11951 u8 hard_lft_arm[0x1]; 11952 u8 remove_flow_enable[0x1]; 11953 u8 esn_event_arm[0x1]; 11954 u8 reserved_at_20a[0x16]; 11955 11956 u8 remove_flow_pkt_cnt[0x20]; 11957 11958 u8 remove_flow_soft_lft[0x20]; 11959 11960 u8 reserved_at_260[0x80]; 11961 11962 u8 mode_parameter[0x20]; 11963 11964 u8 replay_protection_window[0x100]; 11965 }; 11966 11967 struct mlx5_ifc_ipsec_obj_bits { 11968 u8 modify_field_select[0x40]; 11969 u8 full_offload[0x1]; 11970 u8 reserved_at_41[0x1]; 11971 u8 esn_en[0x1]; 11972 u8 esn_overlap[0x1]; 11973 u8 reserved_at_44[0x2]; 11974 u8 icv_length[0x2]; 11975 u8 reserved_at_48[0x4]; 11976 u8 aso_return_reg[0x4]; 11977 u8 reserved_at_50[0x10]; 11978 11979 u8 esn_msb[0x20]; 11980 11981 u8 reserved_at_80[0x8]; 11982 u8 dekn[0x18]; 11983 11984 u8 salt[0x20]; 11985 11986 u8 implicit_iv[0x40]; 11987 11988 u8 reserved_at_100[0x8]; 11989 u8 ipsec_aso_access_pd[0x18]; 11990 u8 reserved_at_120[0xe0]; 11991 11992 struct mlx5_ifc_ipsec_aso_bits ipsec_aso; 11993 }; 11994 11995 struct mlx5_ifc_create_ipsec_obj_in_bits { 11996 struct mlx5_ifc_general_obj_in_cmd_hdr_bits general_obj_in_cmd_hdr; 11997 struct mlx5_ifc_ipsec_obj_bits ipsec_object; 11998 }; 11999 12000 enum { 12001 MLX5_MODIFY_IPSEC_BITMASK_ESN_OVERLAP = BIT(0), 12002 MLX5_MODIFY_IPSEC_BITMASK_ESN_MSB = BIT(1), 12003 }; 12004 12005 struct mlx5_ifc_query_ipsec_obj_out_bits { 12006 struct mlx5_ifc_general_obj_out_cmd_hdr_bits general_obj_out_cmd_hdr; 12007 struct mlx5_ifc_ipsec_obj_bits ipsec_object; 12008 }; 12009 12010 struct mlx5_ifc_modify_ipsec_obj_in_bits { 12011 struct mlx5_ifc_general_obj_in_cmd_hdr_bits general_obj_in_cmd_hdr; 12012 struct mlx5_ifc_ipsec_obj_bits ipsec_object; 12013 }; 12014 12015 enum { 12016 MLX5_MACSEC_ASO_REPLAY_PROTECTION = 0x1, 12017 }; 12018 12019 enum { 12020 MLX5_MACSEC_ASO_REPLAY_WIN_32BIT = 0x0, 12021 MLX5_MACSEC_ASO_REPLAY_WIN_64BIT = 0x1, 12022 MLX5_MACSEC_ASO_REPLAY_WIN_128BIT = 0x2, 12023 MLX5_MACSEC_ASO_REPLAY_WIN_256BIT = 0x3, 12024 }; 12025 12026 #define MLX5_MACSEC_ASO_INC_SN 0x2 12027 #define MLX5_MACSEC_ASO_REG_C_4_5 0x2 12028 12029 struct mlx5_ifc_macsec_aso_bits { 12030 u8 valid[0x1]; 12031 u8 reserved_at_1[0x1]; 12032 u8 mode[0x2]; 12033 u8 window_size[0x2]; 12034 u8 soft_lifetime_arm[0x1]; 12035 u8 hard_lifetime_arm[0x1]; 12036 u8 remove_flow_enable[0x1]; 12037 u8 epn_event_arm[0x1]; 12038 u8 reserved_at_a[0x16]; 12039 12040 u8 remove_flow_packet_count[0x20]; 12041 12042 u8 remove_flow_soft_lifetime[0x20]; 12043 12044 u8 reserved_at_60[0x80]; 12045 12046 u8 mode_parameter[0x20]; 12047 12048 u8 replay_protection_window[8][0x20]; 12049 }; 12050 12051 struct mlx5_ifc_macsec_offload_obj_bits { 12052 u8 modify_field_select[0x40]; 12053 12054 u8 confidentiality_en[0x1]; 12055 u8 reserved_at_41[0x1]; 12056 u8 epn_en[0x1]; 12057 u8 epn_overlap[0x1]; 12058 u8 reserved_at_44[0x2]; 12059 u8 confidentiality_offset[0x2]; 12060 u8 reserved_at_48[0x4]; 12061 u8 aso_return_reg[0x4]; 12062 u8 reserved_at_50[0x10]; 12063 12064 u8 epn_msb[0x20]; 12065 12066 u8 reserved_at_80[0x8]; 12067 u8 dekn[0x18]; 12068 12069 u8 reserved_at_a0[0x20]; 12070 12071 u8 sci[0x40]; 12072 12073 u8 reserved_at_100[0x8]; 12074 u8 macsec_aso_access_pd[0x18]; 12075 12076 u8 reserved_at_120[0x60]; 12077 12078 u8 salt[3][0x20]; 12079 12080 u8 reserved_at_1e0[0x20]; 12081 12082 struct mlx5_ifc_macsec_aso_bits macsec_aso; 12083 }; 12084 12085 struct mlx5_ifc_create_macsec_obj_in_bits { 12086 struct mlx5_ifc_general_obj_in_cmd_hdr_bits general_obj_in_cmd_hdr; 12087 struct mlx5_ifc_macsec_offload_obj_bits macsec_object; 12088 }; 12089 12090 struct mlx5_ifc_modify_macsec_obj_in_bits { 12091 struct mlx5_ifc_general_obj_in_cmd_hdr_bits general_obj_in_cmd_hdr; 12092 struct mlx5_ifc_macsec_offload_obj_bits macsec_object; 12093 }; 12094 12095 enum { 12096 MLX5_MODIFY_MACSEC_BITMASK_EPN_OVERLAP = BIT(0), 12097 MLX5_MODIFY_MACSEC_BITMASK_EPN_MSB = BIT(1), 12098 }; 12099 12100 struct mlx5_ifc_query_macsec_obj_out_bits { 12101 struct mlx5_ifc_general_obj_out_cmd_hdr_bits general_obj_out_cmd_hdr; 12102 struct mlx5_ifc_macsec_offload_obj_bits macsec_object; 12103 }; 12104 12105 struct mlx5_ifc_wrapped_dek_bits { 12106 u8 gcm_iv[0x60]; 12107 12108 u8 reserved_at_60[0x20]; 12109 12110 u8 const0[0x1]; 12111 u8 key_size[0x1]; 12112 u8 reserved_at_82[0x2]; 12113 u8 key2_invalid[0x1]; 12114 u8 reserved_at_85[0x3]; 12115 u8 pd[0x18]; 12116 12117 u8 key_purpose[0x5]; 12118 u8 reserved_at_a5[0x13]; 12119 u8 kek_id[0x8]; 12120 12121 u8 reserved_at_c0[0x40]; 12122 12123 u8 key1[0x8][0x20]; 12124 12125 u8 key2[0x8][0x20]; 12126 12127 u8 reserved_at_300[0x40]; 12128 12129 u8 const1[0x1]; 12130 u8 reserved_at_341[0x1f]; 12131 12132 u8 reserved_at_360[0x20]; 12133 12134 u8 auth_tag[0x80]; 12135 }; 12136 12137 struct mlx5_ifc_encryption_key_obj_bits { 12138 u8 modify_field_select[0x40]; 12139 12140 u8 state[0x8]; 12141 u8 sw_wrapped[0x1]; 12142 u8 reserved_at_49[0xb]; 12143 u8 key_size[0x4]; 12144 u8 reserved_at_58[0x4]; 12145 u8 key_purpose[0x4]; 12146 12147 u8 reserved_at_60[0x8]; 12148 u8 pd[0x18]; 12149 12150 u8 reserved_at_80[0x100]; 12151 12152 u8 opaque[0x40]; 12153 12154 u8 reserved_at_1c0[0x40]; 12155 12156 u8 key[8][0x80]; 12157 12158 u8 sw_wrapped_dek[8][0x80]; 12159 12160 u8 reserved_at_a00[0x600]; 12161 }; 12162 12163 struct mlx5_ifc_create_encryption_key_in_bits { 12164 struct mlx5_ifc_general_obj_in_cmd_hdr_bits general_obj_in_cmd_hdr; 12165 struct mlx5_ifc_encryption_key_obj_bits encryption_key_object; 12166 }; 12167 12168 struct mlx5_ifc_modify_encryption_key_in_bits { 12169 struct mlx5_ifc_general_obj_in_cmd_hdr_bits general_obj_in_cmd_hdr; 12170 struct mlx5_ifc_encryption_key_obj_bits encryption_key_object; 12171 }; 12172 12173 enum { 12174 MLX5_FLOW_METER_MODE_BYTES_IP_LENGTH = 0x0, 12175 MLX5_FLOW_METER_MODE_BYTES_CALC_WITH_L2 = 0x1, 12176 MLX5_FLOW_METER_MODE_BYTES_CALC_WITH_L2_IPG = 0x2, 12177 MLX5_FLOW_METER_MODE_NUM_PACKETS = 0x3, 12178 }; 12179 12180 struct mlx5_ifc_flow_meter_parameters_bits { 12181 u8 valid[0x1]; 12182 u8 bucket_overflow[0x1]; 12183 u8 start_color[0x2]; 12184 u8 both_buckets_on_green[0x1]; 12185 u8 reserved_at_5[0x1]; 12186 u8 meter_mode[0x2]; 12187 u8 reserved_at_8[0x18]; 12188 12189 u8 reserved_at_20[0x20]; 12190 12191 u8 reserved_at_40[0x3]; 12192 u8 cbs_exponent[0x5]; 12193 u8 cbs_mantissa[0x8]; 12194 u8 reserved_at_50[0x3]; 12195 u8 cir_exponent[0x5]; 12196 u8 cir_mantissa[0x8]; 12197 12198 u8 reserved_at_60[0x20]; 12199 12200 u8 reserved_at_80[0x3]; 12201 u8 ebs_exponent[0x5]; 12202 u8 ebs_mantissa[0x8]; 12203 u8 reserved_at_90[0x3]; 12204 u8 eir_exponent[0x5]; 12205 u8 eir_mantissa[0x8]; 12206 12207 u8 reserved_at_a0[0x60]; 12208 }; 12209 12210 struct mlx5_ifc_flow_meter_aso_obj_bits { 12211 u8 modify_field_select[0x40]; 12212 12213 u8 reserved_at_40[0x40]; 12214 12215 u8 reserved_at_80[0x8]; 12216 u8 meter_aso_access_pd[0x18]; 12217 12218 u8 reserved_at_a0[0x160]; 12219 12220 struct mlx5_ifc_flow_meter_parameters_bits flow_meter_parameters[2]; 12221 }; 12222 12223 struct mlx5_ifc_create_flow_meter_aso_obj_in_bits { 12224 struct mlx5_ifc_general_obj_in_cmd_hdr_bits hdr; 12225 struct mlx5_ifc_flow_meter_aso_obj_bits flow_meter_aso_obj; 12226 }; 12227 12228 struct mlx5_ifc_int_kek_obj_bits { 12229 u8 modify_field_select[0x40]; 12230 12231 u8 state[0x8]; 12232 u8 auto_gen[0x1]; 12233 u8 reserved_at_49[0xb]; 12234 u8 key_size[0x4]; 12235 u8 reserved_at_58[0x8]; 12236 12237 u8 reserved_at_60[0x8]; 12238 u8 pd[0x18]; 12239 12240 u8 reserved_at_80[0x180]; 12241 u8 key[8][0x80]; 12242 12243 u8 reserved_at_600[0x200]; 12244 }; 12245 12246 struct mlx5_ifc_create_int_kek_obj_in_bits { 12247 struct mlx5_ifc_general_obj_in_cmd_hdr_bits general_obj_in_cmd_hdr; 12248 struct mlx5_ifc_int_kek_obj_bits int_kek_object; 12249 }; 12250 12251 struct mlx5_ifc_create_int_kek_obj_out_bits { 12252 struct mlx5_ifc_general_obj_out_cmd_hdr_bits general_obj_out_cmd_hdr; 12253 struct mlx5_ifc_int_kek_obj_bits int_kek_object; 12254 }; 12255 12256 struct mlx5_ifc_sampler_obj_bits { 12257 u8 modify_field_select[0x40]; 12258 12259 u8 table_type[0x8]; 12260 u8 level[0x8]; 12261 u8 reserved_at_50[0xf]; 12262 u8 ignore_flow_level[0x1]; 12263 12264 u8 sample_ratio[0x20]; 12265 12266 u8 reserved_at_80[0x8]; 12267 u8 sample_table_id[0x18]; 12268 12269 u8 reserved_at_a0[0x8]; 12270 u8 default_table_id[0x18]; 12271 12272 u8 sw_steering_icm_address_rx[0x40]; 12273 u8 sw_steering_icm_address_tx[0x40]; 12274 12275 u8 reserved_at_140[0xa0]; 12276 }; 12277 12278 struct mlx5_ifc_create_sampler_obj_in_bits { 12279 struct mlx5_ifc_general_obj_in_cmd_hdr_bits general_obj_in_cmd_hdr; 12280 struct mlx5_ifc_sampler_obj_bits sampler_object; 12281 }; 12282 12283 struct mlx5_ifc_query_sampler_obj_out_bits { 12284 struct mlx5_ifc_general_obj_out_cmd_hdr_bits general_obj_out_cmd_hdr; 12285 struct mlx5_ifc_sampler_obj_bits sampler_object; 12286 }; 12287 12288 enum { 12289 MLX5_GENERAL_OBJECT_TYPE_ENCRYPTION_KEY_KEY_SIZE_128 = 0x0, 12290 MLX5_GENERAL_OBJECT_TYPE_ENCRYPTION_KEY_KEY_SIZE_256 = 0x1, 12291 }; 12292 12293 enum { 12294 MLX5_GENERAL_OBJECT_TYPE_ENCRYPTION_KEY_PURPOSE_TLS = 0x1, 12295 MLX5_GENERAL_OBJECT_TYPE_ENCRYPTION_KEY_PURPOSE_IPSEC = 0x2, 12296 MLX5_GENERAL_OBJECT_TYPE_ENCRYPTION_KEY_PURPOSE_MACSEC = 0x4, 12297 }; 12298 12299 struct mlx5_ifc_tls_static_params_bits { 12300 u8 const_2[0x2]; 12301 u8 tls_version[0x4]; 12302 u8 const_1[0x2]; 12303 u8 reserved_at_8[0x14]; 12304 u8 encryption_standard[0x4]; 12305 12306 u8 reserved_at_20[0x20]; 12307 12308 u8 initial_record_number[0x40]; 12309 12310 u8 resync_tcp_sn[0x20]; 12311 12312 u8 gcm_iv[0x20]; 12313 12314 u8 implicit_iv[0x40]; 12315 12316 u8 reserved_at_100[0x8]; 12317 u8 dek_index[0x18]; 12318 12319 u8 reserved_at_120[0xe0]; 12320 }; 12321 12322 struct mlx5_ifc_tls_progress_params_bits { 12323 u8 next_record_tcp_sn[0x20]; 12324 12325 u8 hw_resync_tcp_sn[0x20]; 12326 12327 u8 record_tracker_state[0x2]; 12328 u8 auth_state[0x2]; 12329 u8 reserved_at_44[0x4]; 12330 u8 hw_offset_record_number[0x18]; 12331 }; 12332 12333 enum { 12334 MLX5_MTT_PERM_READ = 1 << 0, 12335 MLX5_MTT_PERM_WRITE = 1 << 1, 12336 MLX5_MTT_PERM_RW = MLX5_MTT_PERM_READ | MLX5_MTT_PERM_WRITE, 12337 }; 12338 12339 enum { 12340 MLX5_SUSPEND_VHCA_IN_OP_MOD_SUSPEND_INITIATOR = 0x0, 12341 MLX5_SUSPEND_VHCA_IN_OP_MOD_SUSPEND_RESPONDER = 0x1, 12342 }; 12343 12344 struct mlx5_ifc_suspend_vhca_in_bits { 12345 u8 opcode[0x10]; 12346 u8 uid[0x10]; 12347 12348 u8 reserved_at_20[0x10]; 12349 u8 op_mod[0x10]; 12350 12351 u8 reserved_at_40[0x10]; 12352 u8 vhca_id[0x10]; 12353 12354 u8 reserved_at_60[0x20]; 12355 }; 12356 12357 struct mlx5_ifc_suspend_vhca_out_bits { 12358 u8 status[0x8]; 12359 u8 reserved_at_8[0x18]; 12360 12361 u8 syndrome[0x20]; 12362 12363 u8 reserved_at_40[0x40]; 12364 }; 12365 12366 enum { 12367 MLX5_RESUME_VHCA_IN_OP_MOD_RESUME_RESPONDER = 0x0, 12368 MLX5_RESUME_VHCA_IN_OP_MOD_RESUME_INITIATOR = 0x1, 12369 }; 12370 12371 struct mlx5_ifc_resume_vhca_in_bits { 12372 u8 opcode[0x10]; 12373 u8 uid[0x10]; 12374 12375 u8 reserved_at_20[0x10]; 12376 u8 op_mod[0x10]; 12377 12378 u8 reserved_at_40[0x10]; 12379 u8 vhca_id[0x10]; 12380 12381 u8 reserved_at_60[0x20]; 12382 }; 12383 12384 struct mlx5_ifc_resume_vhca_out_bits { 12385 u8 status[0x8]; 12386 u8 reserved_at_8[0x18]; 12387 12388 u8 syndrome[0x20]; 12389 12390 u8 reserved_at_40[0x40]; 12391 }; 12392 12393 struct mlx5_ifc_query_vhca_migration_state_in_bits { 12394 u8 opcode[0x10]; 12395 u8 uid[0x10]; 12396 12397 u8 reserved_at_20[0x10]; 12398 u8 op_mod[0x10]; 12399 12400 u8 incremental[0x1]; 12401 u8 reserved_at_41[0xf]; 12402 u8 vhca_id[0x10]; 12403 12404 u8 reserved_at_60[0x20]; 12405 }; 12406 12407 struct mlx5_ifc_query_vhca_migration_state_out_bits { 12408 u8 status[0x8]; 12409 u8 reserved_at_8[0x18]; 12410 12411 u8 syndrome[0x20]; 12412 12413 u8 reserved_at_40[0x40]; 12414 12415 u8 required_umem_size[0x20]; 12416 12417 u8 reserved_at_a0[0x160]; 12418 }; 12419 12420 struct mlx5_ifc_save_vhca_state_in_bits { 12421 u8 opcode[0x10]; 12422 u8 uid[0x10]; 12423 12424 u8 reserved_at_20[0x10]; 12425 u8 op_mod[0x10]; 12426 12427 u8 incremental[0x1]; 12428 u8 set_track[0x1]; 12429 u8 reserved_at_42[0xe]; 12430 u8 vhca_id[0x10]; 12431 12432 u8 reserved_at_60[0x20]; 12433 12434 u8 va[0x40]; 12435 12436 u8 mkey[0x20]; 12437 12438 u8 size[0x20]; 12439 }; 12440 12441 struct mlx5_ifc_save_vhca_state_out_bits { 12442 u8 status[0x8]; 12443 u8 reserved_at_8[0x18]; 12444 12445 u8 syndrome[0x20]; 12446 12447 u8 actual_image_size[0x20]; 12448 12449 u8 reserved_at_60[0x20]; 12450 }; 12451 12452 struct mlx5_ifc_load_vhca_state_in_bits { 12453 u8 opcode[0x10]; 12454 u8 uid[0x10]; 12455 12456 u8 reserved_at_20[0x10]; 12457 u8 op_mod[0x10]; 12458 12459 u8 reserved_at_40[0x10]; 12460 u8 vhca_id[0x10]; 12461 12462 u8 reserved_at_60[0x20]; 12463 12464 u8 va[0x40]; 12465 12466 u8 mkey[0x20]; 12467 12468 u8 size[0x20]; 12469 }; 12470 12471 struct mlx5_ifc_load_vhca_state_out_bits { 12472 u8 status[0x8]; 12473 u8 reserved_at_8[0x18]; 12474 12475 u8 syndrome[0x20]; 12476 12477 u8 reserved_at_40[0x40]; 12478 }; 12479 12480 struct mlx5_ifc_adv_virtualization_cap_bits { 12481 u8 reserved_at_0[0x3]; 12482 u8 pg_track_log_max_num[0x5]; 12483 u8 pg_track_max_num_range[0x8]; 12484 u8 pg_track_log_min_addr_space[0x8]; 12485 u8 pg_track_log_max_addr_space[0x8]; 12486 12487 u8 reserved_at_20[0x3]; 12488 u8 pg_track_log_min_msg_size[0x5]; 12489 u8 reserved_at_28[0x3]; 12490 u8 pg_track_log_max_msg_size[0x5]; 12491 u8 reserved_at_30[0x3]; 12492 u8 pg_track_log_min_page_size[0x5]; 12493 u8 reserved_at_38[0x3]; 12494 u8 pg_track_log_max_page_size[0x5]; 12495 12496 u8 reserved_at_40[0x7c0]; 12497 }; 12498 12499 struct mlx5_ifc_page_track_report_entry_bits { 12500 u8 dirty_address_high[0x20]; 12501 12502 u8 dirty_address_low[0x20]; 12503 }; 12504 12505 enum { 12506 MLX5_PAGE_TRACK_STATE_TRACKING, 12507 MLX5_PAGE_TRACK_STATE_REPORTING, 12508 MLX5_PAGE_TRACK_STATE_ERROR, 12509 }; 12510 12511 struct mlx5_ifc_page_track_range_bits { 12512 u8 start_address[0x40]; 12513 12514 u8 length[0x40]; 12515 }; 12516 12517 struct mlx5_ifc_page_track_bits { 12518 u8 modify_field_select[0x40]; 12519 12520 u8 reserved_at_40[0x10]; 12521 u8 vhca_id[0x10]; 12522 12523 u8 reserved_at_60[0x20]; 12524 12525 u8 state[0x4]; 12526 u8 track_type[0x4]; 12527 u8 log_addr_space_size[0x8]; 12528 u8 reserved_at_90[0x3]; 12529 u8 log_page_size[0x5]; 12530 u8 reserved_at_98[0x3]; 12531 u8 log_msg_size[0x5]; 12532 12533 u8 reserved_at_a0[0x8]; 12534 u8 reporting_qpn[0x18]; 12535 12536 u8 reserved_at_c0[0x18]; 12537 u8 num_ranges[0x8]; 12538 12539 u8 reserved_at_e0[0x20]; 12540 12541 u8 range_start_address[0x40]; 12542 12543 u8 length[0x40]; 12544 12545 struct mlx5_ifc_page_track_range_bits track_range[0]; 12546 }; 12547 12548 struct mlx5_ifc_create_page_track_obj_in_bits { 12549 struct mlx5_ifc_general_obj_in_cmd_hdr_bits general_obj_in_cmd_hdr; 12550 struct mlx5_ifc_page_track_bits obj_context; 12551 }; 12552 12553 struct mlx5_ifc_modify_page_track_obj_in_bits { 12554 struct mlx5_ifc_general_obj_in_cmd_hdr_bits general_obj_in_cmd_hdr; 12555 struct mlx5_ifc_page_track_bits obj_context; 12556 }; 12557 12558 #endif /* MLX5_IFC_H */ 12559