1 /* 2 * Copyright (c) 2013-2015, Mellanox Technologies, Ltd. All rights reserved. 3 * 4 * This software is available to you under a choice of one of two 5 * licenses. You may choose to be licensed under the terms of the GNU 6 * General Public License (GPL) Version 2, available from the file 7 * COPYING in the main directory of this source tree, or the 8 * OpenIB.org BSD license below: 9 * 10 * Redistribution and use in source and binary forms, with or 11 * without modification, are permitted provided that the following 12 * conditions are met: 13 * 14 * - Redistributions of source code must retain the above 15 * copyright notice, this list of conditions and the following 16 * disclaimer. 17 * 18 * - Redistributions in binary form must reproduce the above 19 * copyright notice, this list of conditions and the following 20 * disclaimer in the documentation and/or other materials 21 * provided with the distribution. 22 * 23 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, 24 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF 25 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND 26 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS 27 * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN 28 * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN 29 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE 30 * SOFTWARE. 31 */ 32 #ifndef MLX5_IFC_H 33 #define MLX5_IFC_H 34 35 #include "mlx5_ifc_fpga.h" 36 37 enum { 38 MLX5_EVENT_TYPE_CODING_COMPLETION_EVENTS = 0x0, 39 MLX5_EVENT_TYPE_CODING_PATH_MIGRATED_SUCCEEDED = 0x1, 40 MLX5_EVENT_TYPE_CODING_COMMUNICATION_ESTABLISHED = 0x2, 41 MLX5_EVENT_TYPE_CODING_SEND_QUEUE_DRAINED = 0x3, 42 MLX5_EVENT_TYPE_CODING_LAST_WQE_REACHED = 0x13, 43 MLX5_EVENT_TYPE_CODING_SRQ_LIMIT = 0x14, 44 MLX5_EVENT_TYPE_CODING_DCT_ALL_CONNECTIONS_CLOSED = 0x1c, 45 MLX5_EVENT_TYPE_CODING_DCT_ACCESS_KEY_VIOLATION = 0x1d, 46 MLX5_EVENT_TYPE_CODING_CQ_ERROR = 0x4, 47 MLX5_EVENT_TYPE_CODING_LOCAL_WQ_CATASTROPHIC_ERROR = 0x5, 48 MLX5_EVENT_TYPE_CODING_PATH_MIGRATION_FAILED = 0x7, 49 MLX5_EVENT_TYPE_CODING_PAGE_FAULT_EVENT = 0xc, 50 MLX5_EVENT_TYPE_CODING_INVALID_REQUEST_LOCAL_WQ_ERROR = 0x10, 51 MLX5_EVENT_TYPE_CODING_LOCAL_ACCESS_VIOLATION_WQ_ERROR = 0x11, 52 MLX5_EVENT_TYPE_CODING_LOCAL_SRQ_CATASTROPHIC_ERROR = 0x12, 53 MLX5_EVENT_TYPE_CODING_INTERNAL_ERROR = 0x8, 54 MLX5_EVENT_TYPE_CODING_PORT_STATE_CHANGE = 0x9, 55 MLX5_EVENT_TYPE_CODING_GPIO_EVENT = 0x15, 56 MLX5_EVENT_TYPE_CODING_REMOTE_CONFIGURATION_PROTOCOL_EVENT = 0x19, 57 MLX5_EVENT_TYPE_CODING_DOORBELL_BLUEFLAME_CONGESTION_EVENT = 0x1a, 58 MLX5_EVENT_TYPE_CODING_STALL_VL_EVENT = 0x1b, 59 MLX5_EVENT_TYPE_CODING_DROPPED_PACKET_LOGGED_EVENT = 0x1f, 60 MLX5_EVENT_TYPE_CODING_COMMAND_INTERFACE_COMPLETION = 0xa, 61 MLX5_EVENT_TYPE_CODING_PAGE_REQUEST = 0xb, 62 MLX5_EVENT_TYPE_CODING_FPGA_ERROR = 0x20, 63 MLX5_EVENT_TYPE_CODING_FPGA_QP_ERROR = 0x21 64 }; 65 66 enum { 67 MLX5_MODIFY_TIR_BITMASK_LRO = 0x0, 68 MLX5_MODIFY_TIR_BITMASK_INDIRECT_TABLE = 0x1, 69 MLX5_MODIFY_TIR_BITMASK_HASH = 0x2, 70 MLX5_MODIFY_TIR_BITMASK_TUNNELED_OFFLOAD_EN = 0x3 71 }; 72 73 enum { 74 MLX5_SET_HCA_CAP_OP_MOD_GENERAL_DEVICE = 0x0, 75 MLX5_SET_HCA_CAP_OP_MOD_ATOMIC = 0x3, 76 }; 77 78 enum { 79 MLX5_GENERAL_OBJ_TYPES_CAP_UCTX = (1ULL << 4), 80 MLX5_GENERAL_OBJ_TYPES_CAP_UMEM = (1ULL << 5), 81 }; 82 83 enum { 84 MLX5_OBJ_TYPE_UCTX = 0x0004, 85 MLX5_OBJ_TYPE_UMEM = 0x0005, 86 }; 87 88 enum { 89 MLX5_CMD_OP_QUERY_HCA_CAP = 0x100, 90 MLX5_CMD_OP_QUERY_ADAPTER = 0x101, 91 MLX5_CMD_OP_INIT_HCA = 0x102, 92 MLX5_CMD_OP_TEARDOWN_HCA = 0x103, 93 MLX5_CMD_OP_ENABLE_HCA = 0x104, 94 MLX5_CMD_OP_DISABLE_HCA = 0x105, 95 MLX5_CMD_OP_QUERY_PAGES = 0x107, 96 MLX5_CMD_OP_MANAGE_PAGES = 0x108, 97 MLX5_CMD_OP_SET_HCA_CAP = 0x109, 98 MLX5_CMD_OP_QUERY_ISSI = 0x10a, 99 MLX5_CMD_OP_SET_ISSI = 0x10b, 100 MLX5_CMD_OP_SET_DRIVER_VERSION = 0x10d, 101 MLX5_CMD_OP_CREATE_MKEY = 0x200, 102 MLX5_CMD_OP_QUERY_MKEY = 0x201, 103 MLX5_CMD_OP_DESTROY_MKEY = 0x202, 104 MLX5_CMD_OP_QUERY_SPECIAL_CONTEXTS = 0x203, 105 MLX5_CMD_OP_PAGE_FAULT_RESUME = 0x204, 106 MLX5_CMD_OP_ALLOC_MEMIC = 0x205, 107 MLX5_CMD_OP_DEALLOC_MEMIC = 0x206, 108 MLX5_CMD_OP_CREATE_EQ = 0x301, 109 MLX5_CMD_OP_DESTROY_EQ = 0x302, 110 MLX5_CMD_OP_QUERY_EQ = 0x303, 111 MLX5_CMD_OP_GEN_EQE = 0x304, 112 MLX5_CMD_OP_CREATE_CQ = 0x400, 113 MLX5_CMD_OP_DESTROY_CQ = 0x401, 114 MLX5_CMD_OP_QUERY_CQ = 0x402, 115 MLX5_CMD_OP_MODIFY_CQ = 0x403, 116 MLX5_CMD_OP_CREATE_QP = 0x500, 117 MLX5_CMD_OP_DESTROY_QP = 0x501, 118 MLX5_CMD_OP_RST2INIT_QP = 0x502, 119 MLX5_CMD_OP_INIT2RTR_QP = 0x503, 120 MLX5_CMD_OP_RTR2RTS_QP = 0x504, 121 MLX5_CMD_OP_RTS2RTS_QP = 0x505, 122 MLX5_CMD_OP_SQERR2RTS_QP = 0x506, 123 MLX5_CMD_OP_2ERR_QP = 0x507, 124 MLX5_CMD_OP_2RST_QP = 0x50a, 125 MLX5_CMD_OP_QUERY_QP = 0x50b, 126 MLX5_CMD_OP_SQD_RTS_QP = 0x50c, 127 MLX5_CMD_OP_INIT2INIT_QP = 0x50e, 128 MLX5_CMD_OP_CREATE_PSV = 0x600, 129 MLX5_CMD_OP_DESTROY_PSV = 0x601, 130 MLX5_CMD_OP_CREATE_SRQ = 0x700, 131 MLX5_CMD_OP_DESTROY_SRQ = 0x701, 132 MLX5_CMD_OP_QUERY_SRQ = 0x702, 133 MLX5_CMD_OP_ARM_RQ = 0x703, 134 MLX5_CMD_OP_CREATE_XRC_SRQ = 0x705, 135 MLX5_CMD_OP_DESTROY_XRC_SRQ = 0x706, 136 MLX5_CMD_OP_QUERY_XRC_SRQ = 0x707, 137 MLX5_CMD_OP_ARM_XRC_SRQ = 0x708, 138 MLX5_CMD_OP_CREATE_DCT = 0x710, 139 MLX5_CMD_OP_DESTROY_DCT = 0x711, 140 MLX5_CMD_OP_DRAIN_DCT = 0x712, 141 MLX5_CMD_OP_QUERY_DCT = 0x713, 142 MLX5_CMD_OP_ARM_DCT_FOR_KEY_VIOLATION = 0x714, 143 MLX5_CMD_OP_CREATE_XRQ = 0x717, 144 MLX5_CMD_OP_DESTROY_XRQ = 0x718, 145 MLX5_CMD_OP_QUERY_XRQ = 0x719, 146 MLX5_CMD_OP_ARM_XRQ = 0x71a, 147 MLX5_CMD_OP_QUERY_VPORT_STATE = 0x750, 148 MLX5_CMD_OP_MODIFY_VPORT_STATE = 0x751, 149 MLX5_CMD_OP_QUERY_ESW_VPORT_CONTEXT = 0x752, 150 MLX5_CMD_OP_MODIFY_ESW_VPORT_CONTEXT = 0x753, 151 MLX5_CMD_OP_QUERY_NIC_VPORT_CONTEXT = 0x754, 152 MLX5_CMD_OP_MODIFY_NIC_VPORT_CONTEXT = 0x755, 153 MLX5_CMD_OP_QUERY_ROCE_ADDRESS = 0x760, 154 MLX5_CMD_OP_SET_ROCE_ADDRESS = 0x761, 155 MLX5_CMD_OP_QUERY_HCA_VPORT_CONTEXT = 0x762, 156 MLX5_CMD_OP_MODIFY_HCA_VPORT_CONTEXT = 0x763, 157 MLX5_CMD_OP_QUERY_HCA_VPORT_GID = 0x764, 158 MLX5_CMD_OP_QUERY_HCA_VPORT_PKEY = 0x765, 159 MLX5_CMD_OP_QUERY_VNIC_ENV = 0x76f, 160 MLX5_CMD_OP_QUERY_VPORT_COUNTER = 0x770, 161 MLX5_CMD_OP_ALLOC_Q_COUNTER = 0x771, 162 MLX5_CMD_OP_DEALLOC_Q_COUNTER = 0x772, 163 MLX5_CMD_OP_QUERY_Q_COUNTER = 0x773, 164 MLX5_CMD_OP_SET_MONITOR_COUNTER = 0x774, 165 MLX5_CMD_OP_ARM_MONITOR_COUNTER = 0x775, 166 MLX5_CMD_OP_SET_PP_RATE_LIMIT = 0x780, 167 MLX5_CMD_OP_QUERY_RATE_LIMIT = 0x781, 168 MLX5_CMD_OP_CREATE_SCHEDULING_ELEMENT = 0x782, 169 MLX5_CMD_OP_DESTROY_SCHEDULING_ELEMENT = 0x783, 170 MLX5_CMD_OP_QUERY_SCHEDULING_ELEMENT = 0x784, 171 MLX5_CMD_OP_MODIFY_SCHEDULING_ELEMENT = 0x785, 172 MLX5_CMD_OP_CREATE_QOS_PARA_VPORT = 0x786, 173 MLX5_CMD_OP_DESTROY_QOS_PARA_VPORT = 0x787, 174 MLX5_CMD_OP_ALLOC_PD = 0x800, 175 MLX5_CMD_OP_DEALLOC_PD = 0x801, 176 MLX5_CMD_OP_ALLOC_UAR = 0x802, 177 MLX5_CMD_OP_DEALLOC_UAR = 0x803, 178 MLX5_CMD_OP_CONFIG_INT_MODERATION = 0x804, 179 MLX5_CMD_OP_ACCESS_REG = 0x805, 180 MLX5_CMD_OP_ATTACH_TO_MCG = 0x806, 181 MLX5_CMD_OP_DETACH_FROM_MCG = 0x807, 182 MLX5_CMD_OP_GET_DROPPED_PACKET_LOG = 0x80a, 183 MLX5_CMD_OP_MAD_IFC = 0x50d, 184 MLX5_CMD_OP_QUERY_MAD_DEMUX = 0x80b, 185 MLX5_CMD_OP_SET_MAD_DEMUX = 0x80c, 186 MLX5_CMD_OP_NOP = 0x80d, 187 MLX5_CMD_OP_ALLOC_XRCD = 0x80e, 188 MLX5_CMD_OP_DEALLOC_XRCD = 0x80f, 189 MLX5_CMD_OP_ALLOC_TRANSPORT_DOMAIN = 0x816, 190 MLX5_CMD_OP_DEALLOC_TRANSPORT_DOMAIN = 0x817, 191 MLX5_CMD_OP_QUERY_CONG_STATUS = 0x822, 192 MLX5_CMD_OP_MODIFY_CONG_STATUS = 0x823, 193 MLX5_CMD_OP_QUERY_CONG_PARAMS = 0x824, 194 MLX5_CMD_OP_MODIFY_CONG_PARAMS = 0x825, 195 MLX5_CMD_OP_QUERY_CONG_STATISTICS = 0x826, 196 MLX5_CMD_OP_ADD_VXLAN_UDP_DPORT = 0x827, 197 MLX5_CMD_OP_DELETE_VXLAN_UDP_DPORT = 0x828, 198 MLX5_CMD_OP_SET_L2_TABLE_ENTRY = 0x829, 199 MLX5_CMD_OP_QUERY_L2_TABLE_ENTRY = 0x82a, 200 MLX5_CMD_OP_DELETE_L2_TABLE_ENTRY = 0x82b, 201 MLX5_CMD_OP_SET_WOL_ROL = 0x830, 202 MLX5_CMD_OP_QUERY_WOL_ROL = 0x831, 203 MLX5_CMD_OP_CREATE_LAG = 0x840, 204 MLX5_CMD_OP_MODIFY_LAG = 0x841, 205 MLX5_CMD_OP_QUERY_LAG = 0x842, 206 MLX5_CMD_OP_DESTROY_LAG = 0x843, 207 MLX5_CMD_OP_CREATE_VPORT_LAG = 0x844, 208 MLX5_CMD_OP_DESTROY_VPORT_LAG = 0x845, 209 MLX5_CMD_OP_CREATE_TIR = 0x900, 210 MLX5_CMD_OP_MODIFY_TIR = 0x901, 211 MLX5_CMD_OP_DESTROY_TIR = 0x902, 212 MLX5_CMD_OP_QUERY_TIR = 0x903, 213 MLX5_CMD_OP_CREATE_SQ = 0x904, 214 MLX5_CMD_OP_MODIFY_SQ = 0x905, 215 MLX5_CMD_OP_DESTROY_SQ = 0x906, 216 MLX5_CMD_OP_QUERY_SQ = 0x907, 217 MLX5_CMD_OP_CREATE_RQ = 0x908, 218 MLX5_CMD_OP_MODIFY_RQ = 0x909, 219 MLX5_CMD_OP_SET_DELAY_DROP_PARAMS = 0x910, 220 MLX5_CMD_OP_DESTROY_RQ = 0x90a, 221 MLX5_CMD_OP_QUERY_RQ = 0x90b, 222 MLX5_CMD_OP_CREATE_RMP = 0x90c, 223 MLX5_CMD_OP_MODIFY_RMP = 0x90d, 224 MLX5_CMD_OP_DESTROY_RMP = 0x90e, 225 MLX5_CMD_OP_QUERY_RMP = 0x90f, 226 MLX5_CMD_OP_CREATE_TIS = 0x912, 227 MLX5_CMD_OP_MODIFY_TIS = 0x913, 228 MLX5_CMD_OP_DESTROY_TIS = 0x914, 229 MLX5_CMD_OP_QUERY_TIS = 0x915, 230 MLX5_CMD_OP_CREATE_RQT = 0x916, 231 MLX5_CMD_OP_MODIFY_RQT = 0x917, 232 MLX5_CMD_OP_DESTROY_RQT = 0x918, 233 MLX5_CMD_OP_QUERY_RQT = 0x919, 234 MLX5_CMD_OP_SET_FLOW_TABLE_ROOT = 0x92f, 235 MLX5_CMD_OP_CREATE_FLOW_TABLE = 0x930, 236 MLX5_CMD_OP_DESTROY_FLOW_TABLE = 0x931, 237 MLX5_CMD_OP_QUERY_FLOW_TABLE = 0x932, 238 MLX5_CMD_OP_CREATE_FLOW_GROUP = 0x933, 239 MLX5_CMD_OP_DESTROY_FLOW_GROUP = 0x934, 240 MLX5_CMD_OP_QUERY_FLOW_GROUP = 0x935, 241 MLX5_CMD_OP_SET_FLOW_TABLE_ENTRY = 0x936, 242 MLX5_CMD_OP_QUERY_FLOW_TABLE_ENTRY = 0x937, 243 MLX5_CMD_OP_DELETE_FLOW_TABLE_ENTRY = 0x938, 244 MLX5_CMD_OP_ALLOC_FLOW_COUNTER = 0x939, 245 MLX5_CMD_OP_DEALLOC_FLOW_COUNTER = 0x93a, 246 MLX5_CMD_OP_QUERY_FLOW_COUNTER = 0x93b, 247 MLX5_CMD_OP_MODIFY_FLOW_TABLE = 0x93c, 248 MLX5_CMD_OP_ALLOC_PACKET_REFORMAT_CONTEXT = 0x93d, 249 MLX5_CMD_OP_DEALLOC_PACKET_REFORMAT_CONTEXT = 0x93e, 250 MLX5_CMD_OP_ALLOC_MODIFY_HEADER_CONTEXT = 0x940, 251 MLX5_CMD_OP_DEALLOC_MODIFY_HEADER_CONTEXT = 0x941, 252 MLX5_CMD_OP_QUERY_MODIFY_HEADER_CONTEXT = 0x942, 253 MLX5_CMD_OP_FPGA_CREATE_QP = 0x960, 254 MLX5_CMD_OP_FPGA_MODIFY_QP = 0x961, 255 MLX5_CMD_OP_FPGA_QUERY_QP = 0x962, 256 MLX5_CMD_OP_FPGA_DESTROY_QP = 0x963, 257 MLX5_CMD_OP_FPGA_QUERY_QP_COUNTERS = 0x964, 258 MLX5_CMD_OP_CREATE_GENERAL_OBJECT = 0xa00, 259 MLX5_CMD_OP_MODIFY_GENERAL_OBJECT = 0xa01, 260 MLX5_CMD_OP_QUERY_GENERAL_OBJECT = 0xa02, 261 MLX5_CMD_OP_DESTROY_GENERAL_OBJECT = 0xa03, 262 MLX5_CMD_OP_MAX 263 }; 264 265 struct mlx5_ifc_flow_table_fields_supported_bits { 266 u8 outer_dmac[0x1]; 267 u8 outer_smac[0x1]; 268 u8 outer_ether_type[0x1]; 269 u8 outer_ip_version[0x1]; 270 u8 outer_first_prio[0x1]; 271 u8 outer_first_cfi[0x1]; 272 u8 outer_first_vid[0x1]; 273 u8 outer_ipv4_ttl[0x1]; 274 u8 outer_second_prio[0x1]; 275 u8 outer_second_cfi[0x1]; 276 u8 outer_second_vid[0x1]; 277 u8 reserved_at_b[0x1]; 278 u8 outer_sip[0x1]; 279 u8 outer_dip[0x1]; 280 u8 outer_frag[0x1]; 281 u8 outer_ip_protocol[0x1]; 282 u8 outer_ip_ecn[0x1]; 283 u8 outer_ip_dscp[0x1]; 284 u8 outer_udp_sport[0x1]; 285 u8 outer_udp_dport[0x1]; 286 u8 outer_tcp_sport[0x1]; 287 u8 outer_tcp_dport[0x1]; 288 u8 outer_tcp_flags[0x1]; 289 u8 outer_gre_protocol[0x1]; 290 u8 outer_gre_key[0x1]; 291 u8 outer_vxlan_vni[0x1]; 292 u8 reserved_at_1a[0x5]; 293 u8 source_eswitch_port[0x1]; 294 295 u8 inner_dmac[0x1]; 296 u8 inner_smac[0x1]; 297 u8 inner_ether_type[0x1]; 298 u8 inner_ip_version[0x1]; 299 u8 inner_first_prio[0x1]; 300 u8 inner_first_cfi[0x1]; 301 u8 inner_first_vid[0x1]; 302 u8 reserved_at_27[0x1]; 303 u8 inner_second_prio[0x1]; 304 u8 inner_second_cfi[0x1]; 305 u8 inner_second_vid[0x1]; 306 u8 reserved_at_2b[0x1]; 307 u8 inner_sip[0x1]; 308 u8 inner_dip[0x1]; 309 u8 inner_frag[0x1]; 310 u8 inner_ip_protocol[0x1]; 311 u8 inner_ip_ecn[0x1]; 312 u8 inner_ip_dscp[0x1]; 313 u8 inner_udp_sport[0x1]; 314 u8 inner_udp_dport[0x1]; 315 u8 inner_tcp_sport[0x1]; 316 u8 inner_tcp_dport[0x1]; 317 u8 inner_tcp_flags[0x1]; 318 u8 reserved_at_37[0x9]; 319 320 u8 reserved_at_40[0x5]; 321 u8 outer_first_mpls_over_udp[0x4]; 322 u8 outer_first_mpls_over_gre[0x4]; 323 u8 inner_first_mpls[0x4]; 324 u8 outer_first_mpls[0x4]; 325 u8 reserved_at_55[0x2]; 326 u8 outer_esp_spi[0x1]; 327 u8 reserved_at_58[0x2]; 328 u8 bth_dst_qp[0x1]; 329 330 u8 reserved_at_5b[0x25]; 331 }; 332 333 struct mlx5_ifc_flow_table_prop_layout_bits { 334 u8 ft_support[0x1]; 335 u8 reserved_at_1[0x1]; 336 u8 flow_counter[0x1]; 337 u8 flow_modify_en[0x1]; 338 u8 modify_root[0x1]; 339 u8 identified_miss_table_mode[0x1]; 340 u8 flow_table_modify[0x1]; 341 u8 reformat[0x1]; 342 u8 decap[0x1]; 343 u8 reserved_at_9[0x1]; 344 u8 pop_vlan[0x1]; 345 u8 push_vlan[0x1]; 346 u8 reserved_at_c[0x1]; 347 u8 pop_vlan_2[0x1]; 348 u8 push_vlan_2[0x1]; 349 u8 reformat_and_vlan_action[0x1]; 350 u8 reserved_at_10[0x2]; 351 u8 reformat_l3_tunnel_to_l2[0x1]; 352 u8 reformat_l2_to_l3_tunnel[0x1]; 353 u8 reformat_and_modify_action[0x1]; 354 u8 reserved_at_15[0xb]; 355 u8 reserved_at_20[0x2]; 356 u8 log_max_ft_size[0x6]; 357 u8 log_max_modify_header_context[0x8]; 358 u8 max_modify_header_actions[0x8]; 359 u8 max_ft_level[0x8]; 360 361 u8 reserved_at_40[0x20]; 362 363 u8 reserved_at_60[0x18]; 364 u8 log_max_ft_num[0x8]; 365 366 u8 reserved_at_80[0x18]; 367 u8 log_max_destination[0x8]; 368 369 u8 log_max_flow_counter[0x8]; 370 u8 reserved_at_a8[0x10]; 371 u8 log_max_flow[0x8]; 372 373 u8 reserved_at_c0[0x40]; 374 375 struct mlx5_ifc_flow_table_fields_supported_bits ft_field_support; 376 377 struct mlx5_ifc_flow_table_fields_supported_bits ft_field_bitmask_support; 378 }; 379 380 struct mlx5_ifc_odp_per_transport_service_cap_bits { 381 u8 send[0x1]; 382 u8 receive[0x1]; 383 u8 write[0x1]; 384 u8 read[0x1]; 385 u8 atomic[0x1]; 386 u8 srq_receive[0x1]; 387 u8 reserved_at_6[0x1a]; 388 }; 389 390 struct mlx5_ifc_fte_match_set_lyr_2_4_bits { 391 u8 smac_47_16[0x20]; 392 393 u8 smac_15_0[0x10]; 394 u8 ethertype[0x10]; 395 396 u8 dmac_47_16[0x20]; 397 398 u8 dmac_15_0[0x10]; 399 u8 first_prio[0x3]; 400 u8 first_cfi[0x1]; 401 u8 first_vid[0xc]; 402 403 u8 ip_protocol[0x8]; 404 u8 ip_dscp[0x6]; 405 u8 ip_ecn[0x2]; 406 u8 cvlan_tag[0x1]; 407 u8 svlan_tag[0x1]; 408 u8 frag[0x1]; 409 u8 ip_version[0x4]; 410 u8 tcp_flags[0x9]; 411 412 u8 tcp_sport[0x10]; 413 u8 tcp_dport[0x10]; 414 415 u8 reserved_at_c0[0x18]; 416 u8 ttl_hoplimit[0x8]; 417 418 u8 udp_sport[0x10]; 419 u8 udp_dport[0x10]; 420 421 union mlx5_ifc_ipv6_layout_ipv4_layout_auto_bits src_ipv4_src_ipv6; 422 423 union mlx5_ifc_ipv6_layout_ipv4_layout_auto_bits dst_ipv4_dst_ipv6; 424 }; 425 426 struct mlx5_ifc_nvgre_key_bits { 427 u8 hi[0x18]; 428 u8 lo[0x8]; 429 }; 430 431 union mlx5_ifc_gre_key_bits { 432 struct mlx5_ifc_nvgre_key_bits nvgre; 433 u8 key[0x20]; 434 }; 435 436 struct mlx5_ifc_fte_match_set_misc_bits { 437 u8 reserved_at_0[0x8]; 438 u8 source_sqn[0x18]; 439 440 u8 source_eswitch_owner_vhca_id[0x10]; 441 u8 source_port[0x10]; 442 443 u8 outer_second_prio[0x3]; 444 u8 outer_second_cfi[0x1]; 445 u8 outer_second_vid[0xc]; 446 u8 inner_second_prio[0x3]; 447 u8 inner_second_cfi[0x1]; 448 u8 inner_second_vid[0xc]; 449 450 u8 outer_second_cvlan_tag[0x1]; 451 u8 inner_second_cvlan_tag[0x1]; 452 u8 outer_second_svlan_tag[0x1]; 453 u8 inner_second_svlan_tag[0x1]; 454 u8 reserved_at_64[0xc]; 455 u8 gre_protocol[0x10]; 456 457 union mlx5_ifc_gre_key_bits gre_key; 458 459 u8 vxlan_vni[0x18]; 460 u8 reserved_at_b8[0x8]; 461 462 u8 reserved_at_c0[0x20]; 463 464 u8 reserved_at_e0[0xc]; 465 u8 outer_ipv6_flow_label[0x14]; 466 467 u8 reserved_at_100[0xc]; 468 u8 inner_ipv6_flow_label[0x14]; 469 470 u8 reserved_at_120[0x28]; 471 u8 bth_dst_qp[0x18]; 472 u8 reserved_at_160[0x20]; 473 u8 outer_esp_spi[0x20]; 474 u8 reserved_at_1a0[0x60]; 475 }; 476 477 struct mlx5_ifc_fte_match_mpls_bits { 478 u8 mpls_label[0x14]; 479 u8 mpls_exp[0x3]; 480 u8 mpls_s_bos[0x1]; 481 u8 mpls_ttl[0x8]; 482 }; 483 484 struct mlx5_ifc_fte_match_set_misc2_bits { 485 struct mlx5_ifc_fte_match_mpls_bits outer_first_mpls; 486 487 struct mlx5_ifc_fte_match_mpls_bits inner_first_mpls; 488 489 struct mlx5_ifc_fte_match_mpls_bits outer_first_mpls_over_gre; 490 491 struct mlx5_ifc_fte_match_mpls_bits outer_first_mpls_over_udp; 492 493 u8 reserved_at_80[0x100]; 494 495 u8 metadata_reg_a[0x20]; 496 497 u8 reserved_at_1a0[0x60]; 498 }; 499 500 struct mlx5_ifc_cmd_pas_bits { 501 u8 pa_h[0x20]; 502 503 u8 pa_l[0x14]; 504 u8 reserved_at_34[0xc]; 505 }; 506 507 struct mlx5_ifc_uint64_bits { 508 u8 hi[0x20]; 509 510 u8 lo[0x20]; 511 }; 512 513 enum { 514 MLX5_ADS_STAT_RATE_NO_LIMIT = 0x0, 515 MLX5_ADS_STAT_RATE_2_5GBPS = 0x7, 516 MLX5_ADS_STAT_RATE_10GBPS = 0x8, 517 MLX5_ADS_STAT_RATE_30GBPS = 0x9, 518 MLX5_ADS_STAT_RATE_5GBPS = 0xa, 519 MLX5_ADS_STAT_RATE_20GBPS = 0xb, 520 MLX5_ADS_STAT_RATE_40GBPS = 0xc, 521 MLX5_ADS_STAT_RATE_60GBPS = 0xd, 522 MLX5_ADS_STAT_RATE_80GBPS = 0xe, 523 MLX5_ADS_STAT_RATE_120GBPS = 0xf, 524 }; 525 526 struct mlx5_ifc_ads_bits { 527 u8 fl[0x1]; 528 u8 free_ar[0x1]; 529 u8 reserved_at_2[0xe]; 530 u8 pkey_index[0x10]; 531 532 u8 reserved_at_20[0x8]; 533 u8 grh[0x1]; 534 u8 mlid[0x7]; 535 u8 rlid[0x10]; 536 537 u8 ack_timeout[0x5]; 538 u8 reserved_at_45[0x3]; 539 u8 src_addr_index[0x8]; 540 u8 reserved_at_50[0x4]; 541 u8 stat_rate[0x4]; 542 u8 hop_limit[0x8]; 543 544 u8 reserved_at_60[0x4]; 545 u8 tclass[0x8]; 546 u8 flow_label[0x14]; 547 548 u8 rgid_rip[16][0x8]; 549 550 u8 reserved_at_100[0x4]; 551 u8 f_dscp[0x1]; 552 u8 f_ecn[0x1]; 553 u8 reserved_at_106[0x1]; 554 u8 f_eth_prio[0x1]; 555 u8 ecn[0x2]; 556 u8 dscp[0x6]; 557 u8 udp_sport[0x10]; 558 559 u8 dei_cfi[0x1]; 560 u8 eth_prio[0x3]; 561 u8 sl[0x4]; 562 u8 vhca_port_num[0x8]; 563 u8 rmac_47_32[0x10]; 564 565 u8 rmac_31_0[0x20]; 566 }; 567 568 struct mlx5_ifc_flow_table_nic_cap_bits { 569 u8 nic_rx_multi_path_tirs[0x1]; 570 u8 nic_rx_multi_path_tirs_fts[0x1]; 571 u8 allow_sniffer_and_nic_rx_shared_tir[0x1]; 572 u8 reserved_at_3[0x1d]; 573 u8 encap_general_header[0x1]; 574 u8 reserved_at_21[0xa]; 575 u8 log_max_packet_reformat_context[0x5]; 576 u8 reserved_at_30[0x6]; 577 u8 max_encap_header_size[0xa]; 578 u8 reserved_at_40[0x1c0]; 579 580 struct mlx5_ifc_flow_table_prop_layout_bits flow_table_properties_nic_receive; 581 582 u8 reserved_at_400[0x200]; 583 584 struct mlx5_ifc_flow_table_prop_layout_bits flow_table_properties_nic_receive_sniffer; 585 586 struct mlx5_ifc_flow_table_prop_layout_bits flow_table_properties_nic_transmit; 587 588 u8 reserved_at_a00[0x200]; 589 590 struct mlx5_ifc_flow_table_prop_layout_bits flow_table_properties_nic_transmit_sniffer; 591 592 u8 reserved_at_e00[0x7200]; 593 }; 594 595 struct mlx5_ifc_flow_table_eswitch_cap_bits { 596 u8 reserved_at_0[0x1c]; 597 u8 fdb_multi_path_to_table[0x1]; 598 u8 reserved_at_1d[0x1]; 599 u8 multi_fdb_encap[0x1]; 600 u8 reserved_at_1f[0x1e1]; 601 602 struct mlx5_ifc_flow_table_prop_layout_bits flow_table_properties_nic_esw_fdb; 603 604 struct mlx5_ifc_flow_table_prop_layout_bits flow_table_properties_esw_acl_ingress; 605 606 struct mlx5_ifc_flow_table_prop_layout_bits flow_table_properties_esw_acl_egress; 607 608 u8 reserved_at_800[0x7800]; 609 }; 610 611 struct mlx5_ifc_e_switch_cap_bits { 612 u8 vport_svlan_strip[0x1]; 613 u8 vport_cvlan_strip[0x1]; 614 u8 vport_svlan_insert[0x1]; 615 u8 vport_cvlan_insert_if_not_exist[0x1]; 616 u8 vport_cvlan_insert_overwrite[0x1]; 617 u8 reserved_at_5[0x18]; 618 u8 merged_eswitch[0x1]; 619 u8 nic_vport_node_guid_modify[0x1]; 620 u8 nic_vport_port_guid_modify[0x1]; 621 622 u8 vxlan_encap_decap[0x1]; 623 u8 nvgre_encap_decap[0x1]; 624 u8 reserved_at_22[0x1]; 625 u8 log_max_fdb_encap_uplink[0x5]; 626 u8 reserved_at_21[0x3]; 627 u8 log_max_packet_reformat_context[0x5]; 628 u8 reserved_2b[0x6]; 629 u8 max_encap_header_size[0xa]; 630 631 u8 reserved_40[0x7c0]; 632 633 }; 634 635 struct mlx5_ifc_qos_cap_bits { 636 u8 packet_pacing[0x1]; 637 u8 esw_scheduling[0x1]; 638 u8 esw_bw_share[0x1]; 639 u8 esw_rate_limit[0x1]; 640 u8 reserved_at_4[0x1]; 641 u8 packet_pacing_burst_bound[0x1]; 642 u8 packet_pacing_typical_size[0x1]; 643 u8 reserved_at_7[0x19]; 644 645 u8 reserved_at_20[0x20]; 646 647 u8 packet_pacing_max_rate[0x20]; 648 649 u8 packet_pacing_min_rate[0x20]; 650 651 u8 reserved_at_80[0x10]; 652 u8 packet_pacing_rate_table_size[0x10]; 653 654 u8 esw_element_type[0x10]; 655 u8 esw_tsar_type[0x10]; 656 657 u8 reserved_at_c0[0x10]; 658 u8 max_qos_para_vport[0x10]; 659 660 u8 max_tsar_bw_share[0x20]; 661 662 u8 reserved_at_100[0x700]; 663 }; 664 665 struct mlx5_ifc_debug_cap_bits { 666 u8 reserved_at_0[0x20]; 667 668 u8 reserved_at_20[0x2]; 669 u8 stall_detect[0x1]; 670 u8 reserved_at_23[0x1d]; 671 672 u8 reserved_at_40[0x7c0]; 673 }; 674 675 struct mlx5_ifc_per_protocol_networking_offload_caps_bits { 676 u8 csum_cap[0x1]; 677 u8 vlan_cap[0x1]; 678 u8 lro_cap[0x1]; 679 u8 lro_psh_flag[0x1]; 680 u8 lro_time_stamp[0x1]; 681 u8 reserved_at_5[0x2]; 682 u8 wqe_vlan_insert[0x1]; 683 u8 self_lb_en_modifiable[0x1]; 684 u8 reserved_at_9[0x2]; 685 u8 max_lso_cap[0x5]; 686 u8 multi_pkt_send_wqe[0x2]; 687 u8 wqe_inline_mode[0x2]; 688 u8 rss_ind_tbl_cap[0x4]; 689 u8 reg_umr_sq[0x1]; 690 u8 scatter_fcs[0x1]; 691 u8 enhanced_multi_pkt_send_wqe[0x1]; 692 u8 tunnel_lso_const_out_ip_id[0x1]; 693 u8 reserved_at_1c[0x2]; 694 u8 tunnel_stateless_gre[0x1]; 695 u8 tunnel_stateless_vxlan[0x1]; 696 697 u8 swp[0x1]; 698 u8 swp_csum[0x1]; 699 u8 swp_lso[0x1]; 700 u8 reserved_at_23[0xd]; 701 u8 max_vxlan_udp_ports[0x8]; 702 u8 reserved_at_38[0x6]; 703 u8 max_geneve_opt_len[0x1]; 704 u8 tunnel_stateless_geneve_rx[0x1]; 705 706 u8 reserved_at_40[0x10]; 707 u8 lro_min_mss_size[0x10]; 708 709 u8 reserved_at_60[0x120]; 710 711 u8 lro_timer_supported_periods[4][0x20]; 712 713 u8 reserved_at_200[0x600]; 714 }; 715 716 struct mlx5_ifc_roce_cap_bits { 717 u8 roce_apm[0x1]; 718 u8 reserved_at_1[0x1f]; 719 720 u8 reserved_at_20[0x60]; 721 722 u8 reserved_at_80[0xc]; 723 u8 l3_type[0x4]; 724 u8 reserved_at_90[0x8]; 725 u8 roce_version[0x8]; 726 727 u8 reserved_at_a0[0x10]; 728 u8 r_roce_dest_udp_port[0x10]; 729 730 u8 r_roce_max_src_udp_port[0x10]; 731 u8 r_roce_min_src_udp_port[0x10]; 732 733 u8 reserved_at_e0[0x10]; 734 u8 roce_address_table_size[0x10]; 735 736 u8 reserved_at_100[0x700]; 737 }; 738 739 struct mlx5_ifc_device_mem_cap_bits { 740 u8 memic[0x1]; 741 u8 reserved_at_1[0x1f]; 742 743 u8 reserved_at_20[0xb]; 744 u8 log_min_memic_alloc_size[0x5]; 745 u8 reserved_at_30[0x8]; 746 u8 log_max_memic_addr_alignment[0x8]; 747 748 u8 memic_bar_start_addr[0x40]; 749 750 u8 memic_bar_size[0x20]; 751 752 u8 max_memic_size[0x20]; 753 754 u8 reserved_at_c0[0x740]; 755 }; 756 757 enum { 758 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_QP_1_BYTE = 0x0, 759 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_QP_2_BYTES = 0x2, 760 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_QP_4_BYTES = 0x4, 761 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_QP_8_BYTES = 0x8, 762 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_QP_16_BYTES = 0x10, 763 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_QP_32_BYTES = 0x20, 764 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_QP_64_BYTES = 0x40, 765 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_QP_128_BYTES = 0x80, 766 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_QP_256_BYTES = 0x100, 767 }; 768 769 enum { 770 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_DC_1_BYTE = 0x1, 771 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_DC_2_BYTES = 0x2, 772 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_DC_4_BYTES = 0x4, 773 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_DC_8_BYTES = 0x8, 774 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_DC_16_BYTES = 0x10, 775 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_DC_32_BYTES = 0x20, 776 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_DC_64_BYTES = 0x40, 777 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_DC_128_BYTES = 0x80, 778 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_DC_256_BYTES = 0x100, 779 }; 780 781 struct mlx5_ifc_atomic_caps_bits { 782 u8 reserved_at_0[0x40]; 783 784 u8 atomic_req_8B_endianness_mode[0x2]; 785 u8 reserved_at_42[0x4]; 786 u8 supported_atomic_req_8B_endianness_mode_1[0x1]; 787 788 u8 reserved_at_47[0x19]; 789 790 u8 reserved_at_60[0x20]; 791 792 u8 reserved_at_80[0x10]; 793 u8 atomic_operations[0x10]; 794 795 u8 reserved_at_a0[0x10]; 796 u8 atomic_size_qp[0x10]; 797 798 u8 reserved_at_c0[0x10]; 799 u8 atomic_size_dc[0x10]; 800 801 u8 reserved_at_e0[0x720]; 802 }; 803 804 struct mlx5_ifc_odp_cap_bits { 805 u8 reserved_at_0[0x40]; 806 807 u8 sig[0x1]; 808 u8 reserved_at_41[0x1f]; 809 810 u8 reserved_at_60[0x20]; 811 812 struct mlx5_ifc_odp_per_transport_service_cap_bits rc_odp_caps; 813 814 struct mlx5_ifc_odp_per_transport_service_cap_bits uc_odp_caps; 815 816 struct mlx5_ifc_odp_per_transport_service_cap_bits ud_odp_caps; 817 818 u8 reserved_at_e0[0x720]; 819 }; 820 821 struct mlx5_ifc_calc_op { 822 u8 reserved_at_0[0x10]; 823 u8 reserved_at_10[0x9]; 824 u8 op_swap_endianness[0x1]; 825 u8 op_min[0x1]; 826 u8 op_xor[0x1]; 827 u8 op_or[0x1]; 828 u8 op_and[0x1]; 829 u8 op_max[0x1]; 830 u8 op_add[0x1]; 831 }; 832 833 struct mlx5_ifc_vector_calc_cap_bits { 834 u8 calc_matrix[0x1]; 835 u8 reserved_at_1[0x1f]; 836 u8 reserved_at_20[0x8]; 837 u8 max_vec_count[0x8]; 838 u8 reserved_at_30[0xd]; 839 u8 max_chunk_size[0x3]; 840 struct mlx5_ifc_calc_op calc0; 841 struct mlx5_ifc_calc_op calc1; 842 struct mlx5_ifc_calc_op calc2; 843 struct mlx5_ifc_calc_op calc3; 844 845 u8 reserved_at_c0[0x720]; 846 }; 847 848 enum { 849 MLX5_WQ_TYPE_LINKED_LIST = 0x0, 850 MLX5_WQ_TYPE_CYCLIC = 0x1, 851 MLX5_WQ_TYPE_LINKED_LIST_STRIDING_RQ = 0x2, 852 MLX5_WQ_TYPE_CYCLIC_STRIDING_RQ = 0x3, 853 }; 854 855 enum { 856 MLX5_WQ_END_PAD_MODE_NONE = 0x0, 857 MLX5_WQ_END_PAD_MODE_ALIGN = 0x1, 858 }; 859 860 enum { 861 MLX5_CMD_HCA_CAP_GID_TABLE_SIZE_8_GID_ENTRIES = 0x0, 862 MLX5_CMD_HCA_CAP_GID_TABLE_SIZE_16_GID_ENTRIES = 0x1, 863 MLX5_CMD_HCA_CAP_GID_TABLE_SIZE_32_GID_ENTRIES = 0x2, 864 MLX5_CMD_HCA_CAP_GID_TABLE_SIZE_64_GID_ENTRIES = 0x3, 865 MLX5_CMD_HCA_CAP_GID_TABLE_SIZE_128_GID_ENTRIES = 0x4, 866 }; 867 868 enum { 869 MLX5_CMD_HCA_CAP_PKEY_TABLE_SIZE_128_ENTRIES = 0x0, 870 MLX5_CMD_HCA_CAP_PKEY_TABLE_SIZE_256_ENTRIES = 0x1, 871 MLX5_CMD_HCA_CAP_PKEY_TABLE_SIZE_512_ENTRIES = 0x2, 872 MLX5_CMD_HCA_CAP_PKEY_TABLE_SIZE_1K_ENTRIES = 0x3, 873 MLX5_CMD_HCA_CAP_PKEY_TABLE_SIZE_2K_ENTRIES = 0x4, 874 MLX5_CMD_HCA_CAP_PKEY_TABLE_SIZE_4K_ENTRIES = 0x5, 875 }; 876 877 enum { 878 MLX5_CMD_HCA_CAP_PORT_TYPE_IB = 0x0, 879 MLX5_CMD_HCA_CAP_PORT_TYPE_ETHERNET = 0x1, 880 }; 881 882 enum { 883 MLX5_CMD_HCA_CAP_CMDIF_CHECKSUM_DISABLED = 0x0, 884 MLX5_CMD_HCA_CAP_CMDIF_CHECKSUM_INITIAL_STATE = 0x1, 885 MLX5_CMD_HCA_CAP_CMDIF_CHECKSUM_ENABLED = 0x3, 886 }; 887 888 enum { 889 MLX5_CAP_PORT_TYPE_IB = 0x0, 890 MLX5_CAP_PORT_TYPE_ETH = 0x1, 891 }; 892 893 enum { 894 MLX5_CAP_UMR_FENCE_STRONG = 0x0, 895 MLX5_CAP_UMR_FENCE_SMALL = 0x1, 896 MLX5_CAP_UMR_FENCE_NONE = 0x2, 897 }; 898 899 enum { 900 MLX5_UCTX_CAP_RAW_TX = 1UL << 0, 901 }; 902 903 struct mlx5_ifc_cmd_hca_cap_bits { 904 u8 reserved_at_0[0x30]; 905 u8 vhca_id[0x10]; 906 907 u8 reserved_at_40[0x40]; 908 909 u8 log_max_srq_sz[0x8]; 910 u8 log_max_qp_sz[0x8]; 911 u8 reserved_at_90[0xb]; 912 u8 log_max_qp[0x5]; 913 914 u8 reserved_at_a0[0xb]; 915 u8 log_max_srq[0x5]; 916 u8 reserved_at_b0[0x10]; 917 918 u8 reserved_at_c0[0x8]; 919 u8 log_max_cq_sz[0x8]; 920 u8 reserved_at_d0[0xb]; 921 u8 log_max_cq[0x5]; 922 923 u8 log_max_eq_sz[0x8]; 924 u8 reserved_at_e8[0x2]; 925 u8 log_max_mkey[0x6]; 926 u8 reserved_at_f0[0x8]; 927 u8 dump_fill_mkey[0x1]; 928 u8 reserved_at_f9[0x2]; 929 u8 fast_teardown[0x1]; 930 u8 log_max_eq[0x4]; 931 932 u8 max_indirection[0x8]; 933 u8 fixed_buffer_size[0x1]; 934 u8 log_max_mrw_sz[0x7]; 935 u8 force_teardown[0x1]; 936 u8 reserved_at_111[0x1]; 937 u8 log_max_bsf_list_size[0x6]; 938 u8 umr_extended_translation_offset[0x1]; 939 u8 null_mkey[0x1]; 940 u8 log_max_klm_list_size[0x6]; 941 942 u8 reserved_at_120[0xa]; 943 u8 log_max_ra_req_dc[0x6]; 944 u8 reserved_at_130[0xa]; 945 u8 log_max_ra_res_dc[0x6]; 946 947 u8 reserved_at_140[0xa]; 948 u8 log_max_ra_req_qp[0x6]; 949 u8 reserved_at_150[0xa]; 950 u8 log_max_ra_res_qp[0x6]; 951 952 u8 end_pad[0x1]; 953 u8 cc_query_allowed[0x1]; 954 u8 cc_modify_allowed[0x1]; 955 u8 start_pad[0x1]; 956 u8 cache_line_128byte[0x1]; 957 u8 reserved_at_165[0xa]; 958 u8 qcam_reg[0x1]; 959 u8 gid_table_size[0x10]; 960 961 u8 out_of_seq_cnt[0x1]; 962 u8 vport_counters[0x1]; 963 u8 retransmission_q_counters[0x1]; 964 u8 debug[0x1]; 965 u8 modify_rq_counter_set_id[0x1]; 966 u8 rq_delay_drop[0x1]; 967 u8 max_qp_cnt[0xa]; 968 u8 pkey_table_size[0x10]; 969 970 u8 vport_group_manager[0x1]; 971 u8 vhca_group_manager[0x1]; 972 u8 ib_virt[0x1]; 973 u8 eth_virt[0x1]; 974 u8 vnic_env_queue_counters[0x1]; 975 u8 ets[0x1]; 976 u8 nic_flow_table[0x1]; 977 u8 eswitch_manager[0x1]; 978 u8 device_memory[0x1]; 979 u8 mcam_reg[0x1]; 980 u8 pcam_reg[0x1]; 981 u8 local_ca_ack_delay[0x5]; 982 u8 port_module_event[0x1]; 983 u8 enhanced_error_q_counters[0x1]; 984 u8 ports_check[0x1]; 985 u8 reserved_at_1b3[0x1]; 986 u8 disable_link_up[0x1]; 987 u8 beacon_led[0x1]; 988 u8 port_type[0x2]; 989 u8 num_ports[0x8]; 990 991 u8 reserved_at_1c0[0x1]; 992 u8 pps[0x1]; 993 u8 pps_modify[0x1]; 994 u8 log_max_msg[0x5]; 995 u8 reserved_at_1c8[0x4]; 996 u8 max_tc[0x4]; 997 u8 temp_warn_event[0x1]; 998 u8 dcbx[0x1]; 999 u8 general_notification_event[0x1]; 1000 u8 reserved_at_1d3[0x2]; 1001 u8 fpga[0x1]; 1002 u8 rol_s[0x1]; 1003 u8 rol_g[0x1]; 1004 u8 reserved_at_1d8[0x1]; 1005 u8 wol_s[0x1]; 1006 u8 wol_g[0x1]; 1007 u8 wol_a[0x1]; 1008 u8 wol_b[0x1]; 1009 u8 wol_m[0x1]; 1010 u8 wol_u[0x1]; 1011 u8 wol_p[0x1]; 1012 1013 u8 stat_rate_support[0x10]; 1014 u8 reserved_at_1f0[0xc]; 1015 u8 cqe_version[0x4]; 1016 1017 u8 compact_address_vector[0x1]; 1018 u8 striding_rq[0x1]; 1019 u8 reserved_at_202[0x1]; 1020 u8 ipoib_enhanced_offloads[0x1]; 1021 u8 ipoib_basic_offloads[0x1]; 1022 u8 reserved_at_205[0x1]; 1023 u8 repeated_block_disabled[0x1]; 1024 u8 umr_modify_entity_size_disabled[0x1]; 1025 u8 umr_modify_atomic_disabled[0x1]; 1026 u8 umr_indirect_mkey_disabled[0x1]; 1027 u8 umr_fence[0x2]; 1028 u8 dc_req_scat_data_cqe[0x1]; 1029 u8 reserved_at_20d[0x2]; 1030 u8 drain_sigerr[0x1]; 1031 u8 cmdif_checksum[0x2]; 1032 u8 sigerr_cqe[0x1]; 1033 u8 reserved_at_213[0x1]; 1034 u8 wq_signature[0x1]; 1035 u8 sctr_data_cqe[0x1]; 1036 u8 reserved_at_216[0x1]; 1037 u8 sho[0x1]; 1038 u8 tph[0x1]; 1039 u8 rf[0x1]; 1040 u8 dct[0x1]; 1041 u8 qos[0x1]; 1042 u8 eth_net_offloads[0x1]; 1043 u8 roce[0x1]; 1044 u8 atomic[0x1]; 1045 u8 reserved_at_21f[0x1]; 1046 1047 u8 cq_oi[0x1]; 1048 u8 cq_resize[0x1]; 1049 u8 cq_moderation[0x1]; 1050 u8 reserved_at_223[0x3]; 1051 u8 cq_eq_remap[0x1]; 1052 u8 pg[0x1]; 1053 u8 block_lb_mc[0x1]; 1054 u8 reserved_at_229[0x1]; 1055 u8 scqe_break_moderation[0x1]; 1056 u8 cq_period_start_from_cqe[0x1]; 1057 u8 cd[0x1]; 1058 u8 reserved_at_22d[0x1]; 1059 u8 apm[0x1]; 1060 u8 vector_calc[0x1]; 1061 u8 umr_ptr_rlky[0x1]; 1062 u8 imaicl[0x1]; 1063 u8 qp_packet_based[0x1]; 1064 u8 reserved_at_233[0x3]; 1065 u8 qkv[0x1]; 1066 u8 pkv[0x1]; 1067 u8 set_deth_sqpn[0x1]; 1068 u8 reserved_at_239[0x3]; 1069 u8 xrc[0x1]; 1070 u8 ud[0x1]; 1071 u8 uc[0x1]; 1072 u8 rc[0x1]; 1073 1074 u8 uar_4k[0x1]; 1075 u8 reserved_at_241[0x9]; 1076 u8 uar_sz[0x6]; 1077 u8 reserved_at_250[0x8]; 1078 u8 log_pg_sz[0x8]; 1079 1080 u8 bf[0x1]; 1081 u8 driver_version[0x1]; 1082 u8 pad_tx_eth_packet[0x1]; 1083 u8 reserved_at_263[0x8]; 1084 u8 log_bf_reg_size[0x5]; 1085 1086 u8 reserved_at_270[0xb]; 1087 u8 lag_master[0x1]; 1088 u8 num_lag_ports[0x4]; 1089 1090 u8 reserved_at_280[0x10]; 1091 u8 max_wqe_sz_sq[0x10]; 1092 1093 u8 reserved_at_2a0[0x10]; 1094 u8 max_wqe_sz_rq[0x10]; 1095 1096 u8 max_flow_counter_31_16[0x10]; 1097 u8 max_wqe_sz_sq_dc[0x10]; 1098 1099 u8 reserved_at_2e0[0x7]; 1100 u8 max_qp_mcg[0x19]; 1101 1102 u8 reserved_at_300[0x18]; 1103 u8 log_max_mcg[0x8]; 1104 1105 u8 reserved_at_320[0x3]; 1106 u8 log_max_transport_domain[0x5]; 1107 u8 reserved_at_328[0x3]; 1108 u8 log_max_pd[0x5]; 1109 u8 reserved_at_330[0xb]; 1110 u8 log_max_xrcd[0x5]; 1111 1112 u8 nic_receive_steering_discard[0x1]; 1113 u8 receive_discard_vport_down[0x1]; 1114 u8 transmit_discard_vport_down[0x1]; 1115 u8 reserved_at_343[0x5]; 1116 u8 log_max_flow_counter_bulk[0x8]; 1117 u8 max_flow_counter_15_0[0x10]; 1118 1119 1120 u8 reserved_at_360[0x3]; 1121 u8 log_max_rq[0x5]; 1122 u8 reserved_at_368[0x3]; 1123 u8 log_max_sq[0x5]; 1124 u8 reserved_at_370[0x3]; 1125 u8 log_max_tir[0x5]; 1126 u8 reserved_at_378[0x3]; 1127 u8 log_max_tis[0x5]; 1128 1129 u8 basic_cyclic_rcv_wqe[0x1]; 1130 u8 reserved_at_381[0x2]; 1131 u8 log_max_rmp[0x5]; 1132 u8 reserved_at_388[0x3]; 1133 u8 log_max_rqt[0x5]; 1134 u8 reserved_at_390[0x3]; 1135 u8 log_max_rqt_size[0x5]; 1136 u8 reserved_at_398[0x3]; 1137 u8 log_max_tis_per_sq[0x5]; 1138 1139 u8 ext_stride_num_range[0x1]; 1140 u8 reserved_at_3a1[0x2]; 1141 u8 log_max_stride_sz_rq[0x5]; 1142 u8 reserved_at_3a8[0x3]; 1143 u8 log_min_stride_sz_rq[0x5]; 1144 u8 reserved_at_3b0[0x3]; 1145 u8 log_max_stride_sz_sq[0x5]; 1146 u8 reserved_at_3b8[0x3]; 1147 u8 log_min_stride_sz_sq[0x5]; 1148 1149 u8 hairpin[0x1]; 1150 u8 reserved_at_3c1[0x2]; 1151 u8 log_max_hairpin_queues[0x5]; 1152 u8 reserved_at_3c8[0x3]; 1153 u8 log_max_hairpin_wq_data_sz[0x5]; 1154 u8 reserved_at_3d0[0x3]; 1155 u8 log_max_hairpin_num_packets[0x5]; 1156 u8 reserved_at_3d8[0x3]; 1157 u8 log_max_wq_sz[0x5]; 1158 1159 u8 nic_vport_change_event[0x1]; 1160 u8 disable_local_lb_uc[0x1]; 1161 u8 disable_local_lb_mc[0x1]; 1162 u8 log_min_hairpin_wq_data_sz[0x5]; 1163 u8 reserved_at_3e8[0x3]; 1164 u8 log_max_vlan_list[0x5]; 1165 u8 reserved_at_3f0[0x3]; 1166 u8 log_max_current_mc_list[0x5]; 1167 u8 reserved_at_3f8[0x3]; 1168 u8 log_max_current_uc_list[0x5]; 1169 1170 u8 general_obj_types[0x40]; 1171 1172 u8 reserved_at_440[0x20]; 1173 1174 u8 reserved_at_460[0x10]; 1175 u8 max_num_eqs[0x10]; 1176 1177 u8 reserved_at_480[0x3]; 1178 u8 log_max_l2_table[0x5]; 1179 u8 reserved_at_488[0x8]; 1180 u8 log_uar_page_sz[0x10]; 1181 1182 u8 reserved_at_4a0[0x20]; 1183 u8 device_frequency_mhz[0x20]; 1184 u8 device_frequency_khz[0x20]; 1185 1186 u8 reserved_at_500[0x20]; 1187 u8 num_of_uars_per_page[0x20]; 1188 1189 u8 flex_parser_protocols[0x20]; 1190 u8 reserved_at_560[0x20]; 1191 1192 u8 reserved_at_580[0x3c]; 1193 u8 mini_cqe_resp_stride_index[0x1]; 1194 u8 cqe_128_always[0x1]; 1195 u8 cqe_compression_128[0x1]; 1196 u8 cqe_compression[0x1]; 1197 1198 u8 cqe_compression_timeout[0x10]; 1199 u8 cqe_compression_max_num[0x10]; 1200 1201 u8 reserved_at_5e0[0x10]; 1202 u8 tag_matching[0x1]; 1203 u8 rndv_offload_rc[0x1]; 1204 u8 rndv_offload_dc[0x1]; 1205 u8 log_tag_matching_list_sz[0x5]; 1206 u8 reserved_at_5f8[0x3]; 1207 u8 log_max_xrq[0x5]; 1208 1209 u8 affiliate_nic_vport_criteria[0x8]; 1210 u8 native_port_num[0x8]; 1211 u8 num_vhca_ports[0x8]; 1212 u8 reserved_at_618[0x6]; 1213 u8 sw_owner_id[0x1]; 1214 u8 reserved_at_61f[0x1]; 1215 1216 u8 max_num_of_monitor_counters[0x10]; 1217 u8 num_ppcnt_monitor_counters[0x10]; 1218 1219 u8 reserved_at_640[0x10]; 1220 u8 num_q_monitor_counters[0x10]; 1221 1222 u8 reserved_at_660[0x40]; 1223 1224 u8 uctx_cap[0x20]; 1225 1226 u8 reserved_at_6c0[0x140]; 1227 }; 1228 1229 enum mlx5_flow_destination_type { 1230 MLX5_FLOW_DESTINATION_TYPE_VPORT = 0x0, 1231 MLX5_FLOW_DESTINATION_TYPE_FLOW_TABLE = 0x1, 1232 MLX5_FLOW_DESTINATION_TYPE_TIR = 0x2, 1233 1234 MLX5_FLOW_DESTINATION_TYPE_PORT = 0x99, 1235 MLX5_FLOW_DESTINATION_TYPE_COUNTER = 0x100, 1236 MLX5_FLOW_DESTINATION_TYPE_FLOW_TABLE_NUM = 0x101, 1237 }; 1238 1239 struct mlx5_ifc_dest_format_struct_bits { 1240 u8 destination_type[0x8]; 1241 u8 destination_id[0x18]; 1242 1243 u8 destination_eswitch_owner_vhca_id_valid[0x1]; 1244 u8 packet_reformat[0x1]; 1245 u8 reserved_at_22[0xe]; 1246 u8 destination_eswitch_owner_vhca_id[0x10]; 1247 }; 1248 1249 struct mlx5_ifc_flow_counter_list_bits { 1250 u8 flow_counter_id[0x20]; 1251 1252 u8 reserved_at_20[0x20]; 1253 }; 1254 1255 struct mlx5_ifc_extended_dest_format_bits { 1256 struct mlx5_ifc_dest_format_struct_bits destination_entry; 1257 1258 u8 packet_reformat_id[0x20]; 1259 1260 u8 reserved_at_60[0x20]; 1261 }; 1262 1263 union mlx5_ifc_dest_format_struct_flow_counter_list_auto_bits { 1264 struct mlx5_ifc_dest_format_struct_bits dest_format_struct; 1265 struct mlx5_ifc_flow_counter_list_bits flow_counter_list; 1266 u8 reserved_at_0[0x40]; 1267 }; 1268 1269 struct mlx5_ifc_fte_match_param_bits { 1270 struct mlx5_ifc_fte_match_set_lyr_2_4_bits outer_headers; 1271 1272 struct mlx5_ifc_fte_match_set_misc_bits misc_parameters; 1273 1274 struct mlx5_ifc_fte_match_set_lyr_2_4_bits inner_headers; 1275 1276 struct mlx5_ifc_fte_match_set_misc2_bits misc_parameters_2; 1277 1278 u8 reserved_at_800[0x800]; 1279 }; 1280 1281 enum { 1282 MLX5_RX_HASH_FIELD_SELECT_SELECTED_FIELDS_SRC_IP = 0x0, 1283 MLX5_RX_HASH_FIELD_SELECT_SELECTED_FIELDS_DST_IP = 0x1, 1284 MLX5_RX_HASH_FIELD_SELECT_SELECTED_FIELDS_L4_SPORT = 0x2, 1285 MLX5_RX_HASH_FIELD_SELECT_SELECTED_FIELDS_L4_DPORT = 0x3, 1286 MLX5_RX_HASH_FIELD_SELECT_SELECTED_FIELDS_IPSEC_SPI = 0x4, 1287 }; 1288 1289 struct mlx5_ifc_rx_hash_field_select_bits { 1290 u8 l3_prot_type[0x1]; 1291 u8 l4_prot_type[0x1]; 1292 u8 selected_fields[0x1e]; 1293 }; 1294 1295 enum { 1296 MLX5_WQ_WQ_TYPE_WQ_LINKED_LIST = 0x0, 1297 MLX5_WQ_WQ_TYPE_WQ_CYCLIC = 0x1, 1298 }; 1299 1300 enum { 1301 MLX5_WQ_END_PADDING_MODE_END_PAD_NONE = 0x0, 1302 MLX5_WQ_END_PADDING_MODE_END_PAD_ALIGN = 0x1, 1303 }; 1304 1305 struct mlx5_ifc_wq_bits { 1306 u8 wq_type[0x4]; 1307 u8 wq_signature[0x1]; 1308 u8 end_padding_mode[0x2]; 1309 u8 cd_slave[0x1]; 1310 u8 reserved_at_8[0x18]; 1311 1312 u8 hds_skip_first_sge[0x1]; 1313 u8 log2_hds_buf_size[0x3]; 1314 u8 reserved_at_24[0x7]; 1315 u8 page_offset[0x5]; 1316 u8 lwm[0x10]; 1317 1318 u8 reserved_at_40[0x8]; 1319 u8 pd[0x18]; 1320 1321 u8 reserved_at_60[0x8]; 1322 u8 uar_page[0x18]; 1323 1324 u8 dbr_addr[0x40]; 1325 1326 u8 hw_counter[0x20]; 1327 1328 u8 sw_counter[0x20]; 1329 1330 u8 reserved_at_100[0xc]; 1331 u8 log_wq_stride[0x4]; 1332 u8 reserved_at_110[0x3]; 1333 u8 log_wq_pg_sz[0x5]; 1334 u8 reserved_at_118[0x3]; 1335 u8 log_wq_sz[0x5]; 1336 1337 u8 dbr_umem_valid[0x1]; 1338 u8 wq_umem_valid[0x1]; 1339 u8 reserved_at_122[0x1]; 1340 u8 log_hairpin_num_packets[0x5]; 1341 u8 reserved_at_128[0x3]; 1342 u8 log_hairpin_data_sz[0x5]; 1343 1344 u8 reserved_at_130[0x4]; 1345 u8 log_wqe_num_of_strides[0x4]; 1346 u8 two_byte_shift_en[0x1]; 1347 u8 reserved_at_139[0x4]; 1348 u8 log_wqe_stride_size[0x3]; 1349 1350 u8 reserved_at_140[0x4c0]; 1351 1352 struct mlx5_ifc_cmd_pas_bits pas[0]; 1353 }; 1354 1355 struct mlx5_ifc_rq_num_bits { 1356 u8 reserved_at_0[0x8]; 1357 u8 rq_num[0x18]; 1358 }; 1359 1360 struct mlx5_ifc_mac_address_layout_bits { 1361 u8 reserved_at_0[0x10]; 1362 u8 mac_addr_47_32[0x10]; 1363 1364 u8 mac_addr_31_0[0x20]; 1365 }; 1366 1367 struct mlx5_ifc_vlan_layout_bits { 1368 u8 reserved_at_0[0x14]; 1369 u8 vlan[0x0c]; 1370 1371 u8 reserved_at_20[0x20]; 1372 }; 1373 1374 struct mlx5_ifc_cong_control_r_roce_ecn_np_bits { 1375 u8 reserved_at_0[0xa0]; 1376 1377 u8 min_time_between_cnps[0x20]; 1378 1379 u8 reserved_at_c0[0x12]; 1380 u8 cnp_dscp[0x6]; 1381 u8 reserved_at_d8[0x4]; 1382 u8 cnp_prio_mode[0x1]; 1383 u8 cnp_802p_prio[0x3]; 1384 1385 u8 reserved_at_e0[0x720]; 1386 }; 1387 1388 struct mlx5_ifc_cong_control_r_roce_ecn_rp_bits { 1389 u8 reserved_at_0[0x60]; 1390 1391 u8 reserved_at_60[0x4]; 1392 u8 clamp_tgt_rate[0x1]; 1393 u8 reserved_at_65[0x3]; 1394 u8 clamp_tgt_rate_after_time_inc[0x1]; 1395 u8 reserved_at_69[0x17]; 1396 1397 u8 reserved_at_80[0x20]; 1398 1399 u8 rpg_time_reset[0x20]; 1400 1401 u8 rpg_byte_reset[0x20]; 1402 1403 u8 rpg_threshold[0x20]; 1404 1405 u8 rpg_max_rate[0x20]; 1406 1407 u8 rpg_ai_rate[0x20]; 1408 1409 u8 rpg_hai_rate[0x20]; 1410 1411 u8 rpg_gd[0x20]; 1412 1413 u8 rpg_min_dec_fac[0x20]; 1414 1415 u8 rpg_min_rate[0x20]; 1416 1417 u8 reserved_at_1c0[0xe0]; 1418 1419 u8 rate_to_set_on_first_cnp[0x20]; 1420 1421 u8 dce_tcp_g[0x20]; 1422 1423 u8 dce_tcp_rtt[0x20]; 1424 1425 u8 rate_reduce_monitor_period[0x20]; 1426 1427 u8 reserved_at_320[0x20]; 1428 1429 u8 initial_alpha_value[0x20]; 1430 1431 u8 reserved_at_360[0x4a0]; 1432 }; 1433 1434 struct mlx5_ifc_cong_control_802_1qau_rp_bits { 1435 u8 reserved_at_0[0x80]; 1436 1437 u8 rppp_max_rps[0x20]; 1438 1439 u8 rpg_time_reset[0x20]; 1440 1441 u8 rpg_byte_reset[0x20]; 1442 1443 u8 rpg_threshold[0x20]; 1444 1445 u8 rpg_max_rate[0x20]; 1446 1447 u8 rpg_ai_rate[0x20]; 1448 1449 u8 rpg_hai_rate[0x20]; 1450 1451 u8 rpg_gd[0x20]; 1452 1453 u8 rpg_min_dec_fac[0x20]; 1454 1455 u8 rpg_min_rate[0x20]; 1456 1457 u8 reserved_at_1c0[0x640]; 1458 }; 1459 1460 enum { 1461 MLX5_RESIZE_FIELD_SELECT_RESIZE_FIELD_SELECT_LOG_CQ_SIZE = 0x1, 1462 MLX5_RESIZE_FIELD_SELECT_RESIZE_FIELD_SELECT_PAGE_OFFSET = 0x2, 1463 MLX5_RESIZE_FIELD_SELECT_RESIZE_FIELD_SELECT_LOG_PAGE_SIZE = 0x4, 1464 }; 1465 1466 struct mlx5_ifc_resize_field_select_bits { 1467 u8 resize_field_select[0x20]; 1468 }; 1469 1470 enum { 1471 MLX5_MODIFY_FIELD_SELECT_MODIFY_FIELD_SELECT_CQ_PERIOD = 0x1, 1472 MLX5_MODIFY_FIELD_SELECT_MODIFY_FIELD_SELECT_CQ_MAX_COUNT = 0x2, 1473 MLX5_MODIFY_FIELD_SELECT_MODIFY_FIELD_SELECT_OI = 0x4, 1474 MLX5_MODIFY_FIELD_SELECT_MODIFY_FIELD_SELECT_C_EQN = 0x8, 1475 }; 1476 1477 struct mlx5_ifc_modify_field_select_bits { 1478 u8 modify_field_select[0x20]; 1479 }; 1480 1481 struct mlx5_ifc_field_select_r_roce_np_bits { 1482 u8 field_select_r_roce_np[0x20]; 1483 }; 1484 1485 struct mlx5_ifc_field_select_r_roce_rp_bits { 1486 u8 field_select_r_roce_rp[0x20]; 1487 }; 1488 1489 enum { 1490 MLX5_FIELD_SELECT_802_1QAU_RP_FIELD_SELECT_8021QAURP_RPPP_MAX_RPS = 0x4, 1491 MLX5_FIELD_SELECT_802_1QAU_RP_FIELD_SELECT_8021QAURP_RPG_TIME_RESET = 0x8, 1492 MLX5_FIELD_SELECT_802_1QAU_RP_FIELD_SELECT_8021QAURP_RPG_BYTE_RESET = 0x10, 1493 MLX5_FIELD_SELECT_802_1QAU_RP_FIELD_SELECT_8021QAURP_RPG_THRESHOLD = 0x20, 1494 MLX5_FIELD_SELECT_802_1QAU_RP_FIELD_SELECT_8021QAURP_RPG_MAX_RATE = 0x40, 1495 MLX5_FIELD_SELECT_802_1QAU_RP_FIELD_SELECT_8021QAURP_RPG_AI_RATE = 0x80, 1496 MLX5_FIELD_SELECT_802_1QAU_RP_FIELD_SELECT_8021QAURP_RPG_HAI_RATE = 0x100, 1497 MLX5_FIELD_SELECT_802_1QAU_RP_FIELD_SELECT_8021QAURP_RPG_GD = 0x200, 1498 MLX5_FIELD_SELECT_802_1QAU_RP_FIELD_SELECT_8021QAURP_RPG_MIN_DEC_FAC = 0x400, 1499 MLX5_FIELD_SELECT_802_1QAU_RP_FIELD_SELECT_8021QAURP_RPG_MIN_RATE = 0x800, 1500 }; 1501 1502 struct mlx5_ifc_field_select_802_1qau_rp_bits { 1503 u8 field_select_8021qaurp[0x20]; 1504 }; 1505 1506 struct mlx5_ifc_phys_layer_cntrs_bits { 1507 u8 time_since_last_clear_high[0x20]; 1508 1509 u8 time_since_last_clear_low[0x20]; 1510 1511 u8 symbol_errors_high[0x20]; 1512 1513 u8 symbol_errors_low[0x20]; 1514 1515 u8 sync_headers_errors_high[0x20]; 1516 1517 u8 sync_headers_errors_low[0x20]; 1518 1519 u8 edpl_bip_errors_lane0_high[0x20]; 1520 1521 u8 edpl_bip_errors_lane0_low[0x20]; 1522 1523 u8 edpl_bip_errors_lane1_high[0x20]; 1524 1525 u8 edpl_bip_errors_lane1_low[0x20]; 1526 1527 u8 edpl_bip_errors_lane2_high[0x20]; 1528 1529 u8 edpl_bip_errors_lane2_low[0x20]; 1530 1531 u8 edpl_bip_errors_lane3_high[0x20]; 1532 1533 u8 edpl_bip_errors_lane3_low[0x20]; 1534 1535 u8 fc_fec_corrected_blocks_lane0_high[0x20]; 1536 1537 u8 fc_fec_corrected_blocks_lane0_low[0x20]; 1538 1539 u8 fc_fec_corrected_blocks_lane1_high[0x20]; 1540 1541 u8 fc_fec_corrected_blocks_lane1_low[0x20]; 1542 1543 u8 fc_fec_corrected_blocks_lane2_high[0x20]; 1544 1545 u8 fc_fec_corrected_blocks_lane2_low[0x20]; 1546 1547 u8 fc_fec_corrected_blocks_lane3_high[0x20]; 1548 1549 u8 fc_fec_corrected_blocks_lane3_low[0x20]; 1550 1551 u8 fc_fec_uncorrectable_blocks_lane0_high[0x20]; 1552 1553 u8 fc_fec_uncorrectable_blocks_lane0_low[0x20]; 1554 1555 u8 fc_fec_uncorrectable_blocks_lane1_high[0x20]; 1556 1557 u8 fc_fec_uncorrectable_blocks_lane1_low[0x20]; 1558 1559 u8 fc_fec_uncorrectable_blocks_lane2_high[0x20]; 1560 1561 u8 fc_fec_uncorrectable_blocks_lane2_low[0x20]; 1562 1563 u8 fc_fec_uncorrectable_blocks_lane3_high[0x20]; 1564 1565 u8 fc_fec_uncorrectable_blocks_lane3_low[0x20]; 1566 1567 u8 rs_fec_corrected_blocks_high[0x20]; 1568 1569 u8 rs_fec_corrected_blocks_low[0x20]; 1570 1571 u8 rs_fec_uncorrectable_blocks_high[0x20]; 1572 1573 u8 rs_fec_uncorrectable_blocks_low[0x20]; 1574 1575 u8 rs_fec_no_errors_blocks_high[0x20]; 1576 1577 u8 rs_fec_no_errors_blocks_low[0x20]; 1578 1579 u8 rs_fec_single_error_blocks_high[0x20]; 1580 1581 u8 rs_fec_single_error_blocks_low[0x20]; 1582 1583 u8 rs_fec_corrected_symbols_total_high[0x20]; 1584 1585 u8 rs_fec_corrected_symbols_total_low[0x20]; 1586 1587 u8 rs_fec_corrected_symbols_lane0_high[0x20]; 1588 1589 u8 rs_fec_corrected_symbols_lane0_low[0x20]; 1590 1591 u8 rs_fec_corrected_symbols_lane1_high[0x20]; 1592 1593 u8 rs_fec_corrected_symbols_lane1_low[0x20]; 1594 1595 u8 rs_fec_corrected_symbols_lane2_high[0x20]; 1596 1597 u8 rs_fec_corrected_symbols_lane2_low[0x20]; 1598 1599 u8 rs_fec_corrected_symbols_lane3_high[0x20]; 1600 1601 u8 rs_fec_corrected_symbols_lane3_low[0x20]; 1602 1603 u8 link_down_events[0x20]; 1604 1605 u8 successful_recovery_events[0x20]; 1606 1607 u8 reserved_at_640[0x180]; 1608 }; 1609 1610 struct mlx5_ifc_phys_layer_statistical_cntrs_bits { 1611 u8 time_since_last_clear_high[0x20]; 1612 1613 u8 time_since_last_clear_low[0x20]; 1614 1615 u8 phy_received_bits_high[0x20]; 1616 1617 u8 phy_received_bits_low[0x20]; 1618 1619 u8 phy_symbol_errors_high[0x20]; 1620 1621 u8 phy_symbol_errors_low[0x20]; 1622 1623 u8 phy_corrected_bits_high[0x20]; 1624 1625 u8 phy_corrected_bits_low[0x20]; 1626 1627 u8 phy_corrected_bits_lane0_high[0x20]; 1628 1629 u8 phy_corrected_bits_lane0_low[0x20]; 1630 1631 u8 phy_corrected_bits_lane1_high[0x20]; 1632 1633 u8 phy_corrected_bits_lane1_low[0x20]; 1634 1635 u8 phy_corrected_bits_lane2_high[0x20]; 1636 1637 u8 phy_corrected_bits_lane2_low[0x20]; 1638 1639 u8 phy_corrected_bits_lane3_high[0x20]; 1640 1641 u8 phy_corrected_bits_lane3_low[0x20]; 1642 1643 u8 reserved_at_200[0x5c0]; 1644 }; 1645 1646 struct mlx5_ifc_ib_port_cntrs_grp_data_layout_bits { 1647 u8 symbol_error_counter[0x10]; 1648 1649 u8 link_error_recovery_counter[0x8]; 1650 1651 u8 link_downed_counter[0x8]; 1652 1653 u8 port_rcv_errors[0x10]; 1654 1655 u8 port_rcv_remote_physical_errors[0x10]; 1656 1657 u8 port_rcv_switch_relay_errors[0x10]; 1658 1659 u8 port_xmit_discards[0x10]; 1660 1661 u8 port_xmit_constraint_errors[0x8]; 1662 1663 u8 port_rcv_constraint_errors[0x8]; 1664 1665 u8 reserved_at_70[0x8]; 1666 1667 u8 link_overrun_errors[0x8]; 1668 1669 u8 reserved_at_80[0x10]; 1670 1671 u8 vl_15_dropped[0x10]; 1672 1673 u8 reserved_at_a0[0x80]; 1674 1675 u8 port_xmit_wait[0x20]; 1676 }; 1677 1678 struct mlx5_ifc_eth_per_traffic_grp_data_layout_bits { 1679 u8 transmit_queue_high[0x20]; 1680 1681 u8 transmit_queue_low[0x20]; 1682 1683 u8 reserved_at_40[0x780]; 1684 }; 1685 1686 struct mlx5_ifc_eth_per_prio_grp_data_layout_bits { 1687 u8 rx_octets_high[0x20]; 1688 1689 u8 rx_octets_low[0x20]; 1690 1691 u8 reserved_at_40[0xc0]; 1692 1693 u8 rx_frames_high[0x20]; 1694 1695 u8 rx_frames_low[0x20]; 1696 1697 u8 tx_octets_high[0x20]; 1698 1699 u8 tx_octets_low[0x20]; 1700 1701 u8 reserved_at_180[0xc0]; 1702 1703 u8 tx_frames_high[0x20]; 1704 1705 u8 tx_frames_low[0x20]; 1706 1707 u8 rx_pause_high[0x20]; 1708 1709 u8 rx_pause_low[0x20]; 1710 1711 u8 rx_pause_duration_high[0x20]; 1712 1713 u8 rx_pause_duration_low[0x20]; 1714 1715 u8 tx_pause_high[0x20]; 1716 1717 u8 tx_pause_low[0x20]; 1718 1719 u8 tx_pause_duration_high[0x20]; 1720 1721 u8 tx_pause_duration_low[0x20]; 1722 1723 u8 rx_pause_transition_high[0x20]; 1724 1725 u8 rx_pause_transition_low[0x20]; 1726 1727 u8 reserved_at_3c0[0x40]; 1728 1729 u8 device_stall_minor_watermark_cnt_high[0x20]; 1730 1731 u8 device_stall_minor_watermark_cnt_low[0x20]; 1732 1733 u8 device_stall_critical_watermark_cnt_high[0x20]; 1734 1735 u8 device_stall_critical_watermark_cnt_low[0x20]; 1736 1737 u8 reserved_at_480[0x340]; 1738 }; 1739 1740 struct mlx5_ifc_eth_extended_cntrs_grp_data_layout_bits { 1741 u8 port_transmit_wait_high[0x20]; 1742 1743 u8 port_transmit_wait_low[0x20]; 1744 1745 u8 reserved_at_40[0x100]; 1746 1747 u8 rx_buffer_almost_full_high[0x20]; 1748 1749 u8 rx_buffer_almost_full_low[0x20]; 1750 1751 u8 rx_buffer_full_high[0x20]; 1752 1753 u8 rx_buffer_full_low[0x20]; 1754 1755 u8 rx_icrc_encapsulated_high[0x20]; 1756 1757 u8 rx_icrc_encapsulated_low[0x20]; 1758 1759 u8 reserved_at_200[0x5c0]; 1760 }; 1761 1762 struct mlx5_ifc_eth_3635_cntrs_grp_data_layout_bits { 1763 u8 dot3stats_alignment_errors_high[0x20]; 1764 1765 u8 dot3stats_alignment_errors_low[0x20]; 1766 1767 u8 dot3stats_fcs_errors_high[0x20]; 1768 1769 u8 dot3stats_fcs_errors_low[0x20]; 1770 1771 u8 dot3stats_single_collision_frames_high[0x20]; 1772 1773 u8 dot3stats_single_collision_frames_low[0x20]; 1774 1775 u8 dot3stats_multiple_collision_frames_high[0x20]; 1776 1777 u8 dot3stats_multiple_collision_frames_low[0x20]; 1778 1779 u8 dot3stats_sqe_test_errors_high[0x20]; 1780 1781 u8 dot3stats_sqe_test_errors_low[0x20]; 1782 1783 u8 dot3stats_deferred_transmissions_high[0x20]; 1784 1785 u8 dot3stats_deferred_transmissions_low[0x20]; 1786 1787 u8 dot3stats_late_collisions_high[0x20]; 1788 1789 u8 dot3stats_late_collisions_low[0x20]; 1790 1791 u8 dot3stats_excessive_collisions_high[0x20]; 1792 1793 u8 dot3stats_excessive_collisions_low[0x20]; 1794 1795 u8 dot3stats_internal_mac_transmit_errors_high[0x20]; 1796 1797 u8 dot3stats_internal_mac_transmit_errors_low[0x20]; 1798 1799 u8 dot3stats_carrier_sense_errors_high[0x20]; 1800 1801 u8 dot3stats_carrier_sense_errors_low[0x20]; 1802 1803 u8 dot3stats_frame_too_longs_high[0x20]; 1804 1805 u8 dot3stats_frame_too_longs_low[0x20]; 1806 1807 u8 dot3stats_internal_mac_receive_errors_high[0x20]; 1808 1809 u8 dot3stats_internal_mac_receive_errors_low[0x20]; 1810 1811 u8 dot3stats_symbol_errors_high[0x20]; 1812 1813 u8 dot3stats_symbol_errors_low[0x20]; 1814 1815 u8 dot3control_in_unknown_opcodes_high[0x20]; 1816 1817 u8 dot3control_in_unknown_opcodes_low[0x20]; 1818 1819 u8 dot3in_pause_frames_high[0x20]; 1820 1821 u8 dot3in_pause_frames_low[0x20]; 1822 1823 u8 dot3out_pause_frames_high[0x20]; 1824 1825 u8 dot3out_pause_frames_low[0x20]; 1826 1827 u8 reserved_at_400[0x3c0]; 1828 }; 1829 1830 struct mlx5_ifc_eth_2819_cntrs_grp_data_layout_bits { 1831 u8 ether_stats_drop_events_high[0x20]; 1832 1833 u8 ether_stats_drop_events_low[0x20]; 1834 1835 u8 ether_stats_octets_high[0x20]; 1836 1837 u8 ether_stats_octets_low[0x20]; 1838 1839 u8 ether_stats_pkts_high[0x20]; 1840 1841 u8 ether_stats_pkts_low[0x20]; 1842 1843 u8 ether_stats_broadcast_pkts_high[0x20]; 1844 1845 u8 ether_stats_broadcast_pkts_low[0x20]; 1846 1847 u8 ether_stats_multicast_pkts_high[0x20]; 1848 1849 u8 ether_stats_multicast_pkts_low[0x20]; 1850 1851 u8 ether_stats_crc_align_errors_high[0x20]; 1852 1853 u8 ether_stats_crc_align_errors_low[0x20]; 1854 1855 u8 ether_stats_undersize_pkts_high[0x20]; 1856 1857 u8 ether_stats_undersize_pkts_low[0x20]; 1858 1859 u8 ether_stats_oversize_pkts_high[0x20]; 1860 1861 u8 ether_stats_oversize_pkts_low[0x20]; 1862 1863 u8 ether_stats_fragments_high[0x20]; 1864 1865 u8 ether_stats_fragments_low[0x20]; 1866 1867 u8 ether_stats_jabbers_high[0x20]; 1868 1869 u8 ether_stats_jabbers_low[0x20]; 1870 1871 u8 ether_stats_collisions_high[0x20]; 1872 1873 u8 ether_stats_collisions_low[0x20]; 1874 1875 u8 ether_stats_pkts64octets_high[0x20]; 1876 1877 u8 ether_stats_pkts64octets_low[0x20]; 1878 1879 u8 ether_stats_pkts65to127octets_high[0x20]; 1880 1881 u8 ether_stats_pkts65to127octets_low[0x20]; 1882 1883 u8 ether_stats_pkts128to255octets_high[0x20]; 1884 1885 u8 ether_stats_pkts128to255octets_low[0x20]; 1886 1887 u8 ether_stats_pkts256to511octets_high[0x20]; 1888 1889 u8 ether_stats_pkts256to511octets_low[0x20]; 1890 1891 u8 ether_stats_pkts512to1023octets_high[0x20]; 1892 1893 u8 ether_stats_pkts512to1023octets_low[0x20]; 1894 1895 u8 ether_stats_pkts1024to1518octets_high[0x20]; 1896 1897 u8 ether_stats_pkts1024to1518octets_low[0x20]; 1898 1899 u8 ether_stats_pkts1519to2047octets_high[0x20]; 1900 1901 u8 ether_stats_pkts1519to2047octets_low[0x20]; 1902 1903 u8 ether_stats_pkts2048to4095octets_high[0x20]; 1904 1905 u8 ether_stats_pkts2048to4095octets_low[0x20]; 1906 1907 u8 ether_stats_pkts4096to8191octets_high[0x20]; 1908 1909 u8 ether_stats_pkts4096to8191octets_low[0x20]; 1910 1911 u8 ether_stats_pkts8192to10239octets_high[0x20]; 1912 1913 u8 ether_stats_pkts8192to10239octets_low[0x20]; 1914 1915 u8 reserved_at_540[0x280]; 1916 }; 1917 1918 struct mlx5_ifc_eth_2863_cntrs_grp_data_layout_bits { 1919 u8 if_in_octets_high[0x20]; 1920 1921 u8 if_in_octets_low[0x20]; 1922 1923 u8 if_in_ucast_pkts_high[0x20]; 1924 1925 u8 if_in_ucast_pkts_low[0x20]; 1926 1927 u8 if_in_discards_high[0x20]; 1928 1929 u8 if_in_discards_low[0x20]; 1930 1931 u8 if_in_errors_high[0x20]; 1932 1933 u8 if_in_errors_low[0x20]; 1934 1935 u8 if_in_unknown_protos_high[0x20]; 1936 1937 u8 if_in_unknown_protos_low[0x20]; 1938 1939 u8 if_out_octets_high[0x20]; 1940 1941 u8 if_out_octets_low[0x20]; 1942 1943 u8 if_out_ucast_pkts_high[0x20]; 1944 1945 u8 if_out_ucast_pkts_low[0x20]; 1946 1947 u8 if_out_discards_high[0x20]; 1948 1949 u8 if_out_discards_low[0x20]; 1950 1951 u8 if_out_errors_high[0x20]; 1952 1953 u8 if_out_errors_low[0x20]; 1954 1955 u8 if_in_multicast_pkts_high[0x20]; 1956 1957 u8 if_in_multicast_pkts_low[0x20]; 1958 1959 u8 if_in_broadcast_pkts_high[0x20]; 1960 1961 u8 if_in_broadcast_pkts_low[0x20]; 1962 1963 u8 if_out_multicast_pkts_high[0x20]; 1964 1965 u8 if_out_multicast_pkts_low[0x20]; 1966 1967 u8 if_out_broadcast_pkts_high[0x20]; 1968 1969 u8 if_out_broadcast_pkts_low[0x20]; 1970 1971 u8 reserved_at_340[0x480]; 1972 }; 1973 1974 struct mlx5_ifc_eth_802_3_cntrs_grp_data_layout_bits { 1975 u8 a_frames_transmitted_ok_high[0x20]; 1976 1977 u8 a_frames_transmitted_ok_low[0x20]; 1978 1979 u8 a_frames_received_ok_high[0x20]; 1980 1981 u8 a_frames_received_ok_low[0x20]; 1982 1983 u8 a_frame_check_sequence_errors_high[0x20]; 1984 1985 u8 a_frame_check_sequence_errors_low[0x20]; 1986 1987 u8 a_alignment_errors_high[0x20]; 1988 1989 u8 a_alignment_errors_low[0x20]; 1990 1991 u8 a_octets_transmitted_ok_high[0x20]; 1992 1993 u8 a_octets_transmitted_ok_low[0x20]; 1994 1995 u8 a_octets_received_ok_high[0x20]; 1996 1997 u8 a_octets_received_ok_low[0x20]; 1998 1999 u8 a_multicast_frames_xmitted_ok_high[0x20]; 2000 2001 u8 a_multicast_frames_xmitted_ok_low[0x20]; 2002 2003 u8 a_broadcast_frames_xmitted_ok_high[0x20]; 2004 2005 u8 a_broadcast_frames_xmitted_ok_low[0x20]; 2006 2007 u8 a_multicast_frames_received_ok_high[0x20]; 2008 2009 u8 a_multicast_frames_received_ok_low[0x20]; 2010 2011 u8 a_broadcast_frames_received_ok_high[0x20]; 2012 2013 u8 a_broadcast_frames_received_ok_low[0x20]; 2014 2015 u8 a_in_range_length_errors_high[0x20]; 2016 2017 u8 a_in_range_length_errors_low[0x20]; 2018 2019 u8 a_out_of_range_length_field_high[0x20]; 2020 2021 u8 a_out_of_range_length_field_low[0x20]; 2022 2023 u8 a_frame_too_long_errors_high[0x20]; 2024 2025 u8 a_frame_too_long_errors_low[0x20]; 2026 2027 u8 a_symbol_error_during_carrier_high[0x20]; 2028 2029 u8 a_symbol_error_during_carrier_low[0x20]; 2030 2031 u8 a_mac_control_frames_transmitted_high[0x20]; 2032 2033 u8 a_mac_control_frames_transmitted_low[0x20]; 2034 2035 u8 a_mac_control_frames_received_high[0x20]; 2036 2037 u8 a_mac_control_frames_received_low[0x20]; 2038 2039 u8 a_unsupported_opcodes_received_high[0x20]; 2040 2041 u8 a_unsupported_opcodes_received_low[0x20]; 2042 2043 u8 a_pause_mac_ctrl_frames_received_high[0x20]; 2044 2045 u8 a_pause_mac_ctrl_frames_received_low[0x20]; 2046 2047 u8 a_pause_mac_ctrl_frames_transmitted_high[0x20]; 2048 2049 u8 a_pause_mac_ctrl_frames_transmitted_low[0x20]; 2050 2051 u8 reserved_at_4c0[0x300]; 2052 }; 2053 2054 struct mlx5_ifc_pcie_perf_cntrs_grp_data_layout_bits { 2055 u8 life_time_counter_high[0x20]; 2056 2057 u8 life_time_counter_low[0x20]; 2058 2059 u8 rx_errors[0x20]; 2060 2061 u8 tx_errors[0x20]; 2062 2063 u8 l0_to_recovery_eieos[0x20]; 2064 2065 u8 l0_to_recovery_ts[0x20]; 2066 2067 u8 l0_to_recovery_framing[0x20]; 2068 2069 u8 l0_to_recovery_retrain[0x20]; 2070 2071 u8 crc_error_dllp[0x20]; 2072 2073 u8 crc_error_tlp[0x20]; 2074 2075 u8 tx_overflow_buffer_pkt_high[0x20]; 2076 2077 u8 tx_overflow_buffer_pkt_low[0x20]; 2078 2079 u8 outbound_stalled_reads[0x20]; 2080 2081 u8 outbound_stalled_writes[0x20]; 2082 2083 u8 outbound_stalled_reads_events[0x20]; 2084 2085 u8 outbound_stalled_writes_events[0x20]; 2086 2087 u8 reserved_at_200[0x5c0]; 2088 }; 2089 2090 struct mlx5_ifc_cmd_inter_comp_event_bits { 2091 u8 command_completion_vector[0x20]; 2092 2093 u8 reserved_at_20[0xc0]; 2094 }; 2095 2096 struct mlx5_ifc_stall_vl_event_bits { 2097 u8 reserved_at_0[0x18]; 2098 u8 port_num[0x1]; 2099 u8 reserved_at_19[0x3]; 2100 u8 vl[0x4]; 2101 2102 u8 reserved_at_20[0xa0]; 2103 }; 2104 2105 struct mlx5_ifc_db_bf_congestion_event_bits { 2106 u8 event_subtype[0x8]; 2107 u8 reserved_at_8[0x8]; 2108 u8 congestion_level[0x8]; 2109 u8 reserved_at_18[0x8]; 2110 2111 u8 reserved_at_20[0xa0]; 2112 }; 2113 2114 struct mlx5_ifc_gpio_event_bits { 2115 u8 reserved_at_0[0x60]; 2116 2117 u8 gpio_event_hi[0x20]; 2118 2119 u8 gpio_event_lo[0x20]; 2120 2121 u8 reserved_at_a0[0x40]; 2122 }; 2123 2124 struct mlx5_ifc_port_state_change_event_bits { 2125 u8 reserved_at_0[0x40]; 2126 2127 u8 port_num[0x4]; 2128 u8 reserved_at_44[0x1c]; 2129 2130 u8 reserved_at_60[0x80]; 2131 }; 2132 2133 struct mlx5_ifc_dropped_packet_logged_bits { 2134 u8 reserved_at_0[0xe0]; 2135 }; 2136 2137 enum { 2138 MLX5_CQ_ERROR_SYNDROME_CQ_OVERRUN = 0x1, 2139 MLX5_CQ_ERROR_SYNDROME_CQ_ACCESS_VIOLATION_ERROR = 0x2, 2140 }; 2141 2142 struct mlx5_ifc_cq_error_bits { 2143 u8 reserved_at_0[0x8]; 2144 u8 cqn[0x18]; 2145 2146 u8 reserved_at_20[0x20]; 2147 2148 u8 reserved_at_40[0x18]; 2149 u8 syndrome[0x8]; 2150 2151 u8 reserved_at_60[0x80]; 2152 }; 2153 2154 struct mlx5_ifc_rdma_page_fault_event_bits { 2155 u8 bytes_committed[0x20]; 2156 2157 u8 r_key[0x20]; 2158 2159 u8 reserved_at_40[0x10]; 2160 u8 packet_len[0x10]; 2161 2162 u8 rdma_op_len[0x20]; 2163 2164 u8 rdma_va[0x40]; 2165 2166 u8 reserved_at_c0[0x5]; 2167 u8 rdma[0x1]; 2168 u8 write[0x1]; 2169 u8 requestor[0x1]; 2170 u8 qp_number[0x18]; 2171 }; 2172 2173 struct mlx5_ifc_wqe_associated_page_fault_event_bits { 2174 u8 bytes_committed[0x20]; 2175 2176 u8 reserved_at_20[0x10]; 2177 u8 wqe_index[0x10]; 2178 2179 u8 reserved_at_40[0x10]; 2180 u8 len[0x10]; 2181 2182 u8 reserved_at_60[0x60]; 2183 2184 u8 reserved_at_c0[0x5]; 2185 u8 rdma[0x1]; 2186 u8 write_read[0x1]; 2187 u8 requestor[0x1]; 2188 u8 qpn[0x18]; 2189 }; 2190 2191 struct mlx5_ifc_qp_events_bits { 2192 u8 reserved_at_0[0xa0]; 2193 2194 u8 type[0x8]; 2195 u8 reserved_at_a8[0x18]; 2196 2197 u8 reserved_at_c0[0x8]; 2198 u8 qpn_rqn_sqn[0x18]; 2199 }; 2200 2201 struct mlx5_ifc_dct_events_bits { 2202 u8 reserved_at_0[0xc0]; 2203 2204 u8 reserved_at_c0[0x8]; 2205 u8 dct_number[0x18]; 2206 }; 2207 2208 struct mlx5_ifc_comp_event_bits { 2209 u8 reserved_at_0[0xc0]; 2210 2211 u8 reserved_at_c0[0x8]; 2212 u8 cq_number[0x18]; 2213 }; 2214 2215 enum { 2216 MLX5_QPC_STATE_RST = 0x0, 2217 MLX5_QPC_STATE_INIT = 0x1, 2218 MLX5_QPC_STATE_RTR = 0x2, 2219 MLX5_QPC_STATE_RTS = 0x3, 2220 MLX5_QPC_STATE_SQER = 0x4, 2221 MLX5_QPC_STATE_ERR = 0x6, 2222 MLX5_QPC_STATE_SQD = 0x7, 2223 MLX5_QPC_STATE_SUSPENDED = 0x9, 2224 }; 2225 2226 enum { 2227 MLX5_QPC_ST_RC = 0x0, 2228 MLX5_QPC_ST_UC = 0x1, 2229 MLX5_QPC_ST_UD = 0x2, 2230 MLX5_QPC_ST_XRC = 0x3, 2231 MLX5_QPC_ST_DCI = 0x5, 2232 MLX5_QPC_ST_QP0 = 0x7, 2233 MLX5_QPC_ST_QP1 = 0x8, 2234 MLX5_QPC_ST_RAW_DATAGRAM = 0x9, 2235 MLX5_QPC_ST_REG_UMR = 0xc, 2236 }; 2237 2238 enum { 2239 MLX5_QPC_PM_STATE_ARMED = 0x0, 2240 MLX5_QPC_PM_STATE_REARM = 0x1, 2241 MLX5_QPC_PM_STATE_RESERVED = 0x2, 2242 MLX5_QPC_PM_STATE_MIGRATED = 0x3, 2243 }; 2244 2245 enum { 2246 MLX5_QPC_OFFLOAD_TYPE_RNDV = 0x1, 2247 }; 2248 2249 enum { 2250 MLX5_QPC_END_PADDING_MODE_SCATTER_AS_IS = 0x0, 2251 MLX5_QPC_END_PADDING_MODE_PAD_TO_CACHE_LINE_ALIGNMENT = 0x1, 2252 }; 2253 2254 enum { 2255 MLX5_QPC_MTU_256_BYTES = 0x1, 2256 MLX5_QPC_MTU_512_BYTES = 0x2, 2257 MLX5_QPC_MTU_1K_BYTES = 0x3, 2258 MLX5_QPC_MTU_2K_BYTES = 0x4, 2259 MLX5_QPC_MTU_4K_BYTES = 0x5, 2260 MLX5_QPC_MTU_RAW_ETHERNET_QP = 0x7, 2261 }; 2262 2263 enum { 2264 MLX5_QPC_ATOMIC_MODE_IB_SPEC = 0x1, 2265 MLX5_QPC_ATOMIC_MODE_ONLY_8B = 0x2, 2266 MLX5_QPC_ATOMIC_MODE_UP_TO_8B = 0x3, 2267 MLX5_QPC_ATOMIC_MODE_UP_TO_16B = 0x4, 2268 MLX5_QPC_ATOMIC_MODE_UP_TO_32B = 0x5, 2269 MLX5_QPC_ATOMIC_MODE_UP_TO_64B = 0x6, 2270 MLX5_QPC_ATOMIC_MODE_UP_TO_128B = 0x7, 2271 MLX5_QPC_ATOMIC_MODE_UP_TO_256B = 0x8, 2272 }; 2273 2274 enum { 2275 MLX5_QPC_CS_REQ_DISABLE = 0x0, 2276 MLX5_QPC_CS_REQ_UP_TO_32B = 0x11, 2277 MLX5_QPC_CS_REQ_UP_TO_64B = 0x22, 2278 }; 2279 2280 enum { 2281 MLX5_QPC_CS_RES_DISABLE = 0x0, 2282 MLX5_QPC_CS_RES_UP_TO_32B = 0x1, 2283 MLX5_QPC_CS_RES_UP_TO_64B = 0x2, 2284 }; 2285 2286 struct mlx5_ifc_qpc_bits { 2287 u8 state[0x4]; 2288 u8 lag_tx_port_affinity[0x4]; 2289 u8 st[0x8]; 2290 u8 reserved_at_10[0x3]; 2291 u8 pm_state[0x2]; 2292 u8 reserved_at_15[0x1]; 2293 u8 req_e2e_credit_mode[0x2]; 2294 u8 offload_type[0x4]; 2295 u8 end_padding_mode[0x2]; 2296 u8 reserved_at_1e[0x2]; 2297 2298 u8 wq_signature[0x1]; 2299 u8 block_lb_mc[0x1]; 2300 u8 atomic_like_write_en[0x1]; 2301 u8 latency_sensitive[0x1]; 2302 u8 reserved_at_24[0x1]; 2303 u8 drain_sigerr[0x1]; 2304 u8 reserved_at_26[0x2]; 2305 u8 pd[0x18]; 2306 2307 u8 mtu[0x3]; 2308 u8 log_msg_max[0x5]; 2309 u8 reserved_at_48[0x1]; 2310 u8 log_rq_size[0x4]; 2311 u8 log_rq_stride[0x3]; 2312 u8 no_sq[0x1]; 2313 u8 log_sq_size[0x4]; 2314 u8 reserved_at_55[0x6]; 2315 u8 rlky[0x1]; 2316 u8 ulp_stateless_offload_mode[0x4]; 2317 2318 u8 counter_set_id[0x8]; 2319 u8 uar_page[0x18]; 2320 2321 u8 reserved_at_80[0x8]; 2322 u8 user_index[0x18]; 2323 2324 u8 reserved_at_a0[0x3]; 2325 u8 log_page_size[0x5]; 2326 u8 remote_qpn[0x18]; 2327 2328 struct mlx5_ifc_ads_bits primary_address_path; 2329 2330 struct mlx5_ifc_ads_bits secondary_address_path; 2331 2332 u8 log_ack_req_freq[0x4]; 2333 u8 reserved_at_384[0x4]; 2334 u8 log_sra_max[0x3]; 2335 u8 reserved_at_38b[0x2]; 2336 u8 retry_count[0x3]; 2337 u8 rnr_retry[0x3]; 2338 u8 reserved_at_393[0x1]; 2339 u8 fre[0x1]; 2340 u8 cur_rnr_retry[0x3]; 2341 u8 cur_retry_count[0x3]; 2342 u8 reserved_at_39b[0x5]; 2343 2344 u8 reserved_at_3a0[0x20]; 2345 2346 u8 reserved_at_3c0[0x8]; 2347 u8 next_send_psn[0x18]; 2348 2349 u8 reserved_at_3e0[0x8]; 2350 u8 cqn_snd[0x18]; 2351 2352 u8 reserved_at_400[0x8]; 2353 u8 deth_sqpn[0x18]; 2354 2355 u8 reserved_at_420[0x20]; 2356 2357 u8 reserved_at_440[0x8]; 2358 u8 last_acked_psn[0x18]; 2359 2360 u8 reserved_at_460[0x8]; 2361 u8 ssn[0x18]; 2362 2363 u8 reserved_at_480[0x8]; 2364 u8 log_rra_max[0x3]; 2365 u8 reserved_at_48b[0x1]; 2366 u8 atomic_mode[0x4]; 2367 u8 rre[0x1]; 2368 u8 rwe[0x1]; 2369 u8 rae[0x1]; 2370 u8 reserved_at_493[0x1]; 2371 u8 page_offset[0x6]; 2372 u8 reserved_at_49a[0x3]; 2373 u8 cd_slave_receive[0x1]; 2374 u8 cd_slave_send[0x1]; 2375 u8 cd_master[0x1]; 2376 2377 u8 reserved_at_4a0[0x3]; 2378 u8 min_rnr_nak[0x5]; 2379 u8 next_rcv_psn[0x18]; 2380 2381 u8 reserved_at_4c0[0x8]; 2382 u8 xrcd[0x18]; 2383 2384 u8 reserved_at_4e0[0x8]; 2385 u8 cqn_rcv[0x18]; 2386 2387 u8 dbr_addr[0x40]; 2388 2389 u8 q_key[0x20]; 2390 2391 u8 reserved_at_560[0x5]; 2392 u8 rq_type[0x3]; 2393 u8 srqn_rmpn_xrqn[0x18]; 2394 2395 u8 reserved_at_580[0x8]; 2396 u8 rmsn[0x18]; 2397 2398 u8 hw_sq_wqebb_counter[0x10]; 2399 u8 sw_sq_wqebb_counter[0x10]; 2400 2401 u8 hw_rq_counter[0x20]; 2402 2403 u8 sw_rq_counter[0x20]; 2404 2405 u8 reserved_at_600[0x20]; 2406 2407 u8 reserved_at_620[0xf]; 2408 u8 cgs[0x1]; 2409 u8 cs_req[0x8]; 2410 u8 cs_res[0x8]; 2411 2412 u8 dc_access_key[0x40]; 2413 2414 u8 reserved_at_680[0x3]; 2415 u8 dbr_umem_valid[0x1]; 2416 2417 u8 reserved_at_684[0xbc]; 2418 }; 2419 2420 struct mlx5_ifc_roce_addr_layout_bits { 2421 u8 source_l3_address[16][0x8]; 2422 2423 u8 reserved_at_80[0x3]; 2424 u8 vlan_valid[0x1]; 2425 u8 vlan_id[0xc]; 2426 u8 source_mac_47_32[0x10]; 2427 2428 u8 source_mac_31_0[0x20]; 2429 2430 u8 reserved_at_c0[0x14]; 2431 u8 roce_l3_type[0x4]; 2432 u8 roce_version[0x8]; 2433 2434 u8 reserved_at_e0[0x20]; 2435 }; 2436 2437 union mlx5_ifc_hca_cap_union_bits { 2438 struct mlx5_ifc_cmd_hca_cap_bits cmd_hca_cap; 2439 struct mlx5_ifc_odp_cap_bits odp_cap; 2440 struct mlx5_ifc_atomic_caps_bits atomic_caps; 2441 struct mlx5_ifc_roce_cap_bits roce_cap; 2442 struct mlx5_ifc_per_protocol_networking_offload_caps_bits per_protocol_networking_offload_caps; 2443 struct mlx5_ifc_flow_table_nic_cap_bits flow_table_nic_cap; 2444 struct mlx5_ifc_flow_table_eswitch_cap_bits flow_table_eswitch_cap; 2445 struct mlx5_ifc_e_switch_cap_bits e_switch_cap; 2446 struct mlx5_ifc_vector_calc_cap_bits vector_calc_cap; 2447 struct mlx5_ifc_qos_cap_bits qos_cap; 2448 struct mlx5_ifc_fpga_cap_bits fpga_cap; 2449 u8 reserved_at_0[0x8000]; 2450 }; 2451 2452 enum { 2453 MLX5_FLOW_CONTEXT_ACTION_ALLOW = 0x1, 2454 MLX5_FLOW_CONTEXT_ACTION_DROP = 0x2, 2455 MLX5_FLOW_CONTEXT_ACTION_FWD_DEST = 0x4, 2456 MLX5_FLOW_CONTEXT_ACTION_COUNT = 0x8, 2457 MLX5_FLOW_CONTEXT_ACTION_PACKET_REFORMAT = 0x10, 2458 MLX5_FLOW_CONTEXT_ACTION_DECAP = 0x20, 2459 MLX5_FLOW_CONTEXT_ACTION_MOD_HDR = 0x40, 2460 MLX5_FLOW_CONTEXT_ACTION_VLAN_POP = 0x80, 2461 MLX5_FLOW_CONTEXT_ACTION_VLAN_PUSH = 0x100, 2462 MLX5_FLOW_CONTEXT_ACTION_VLAN_POP_2 = 0x400, 2463 MLX5_FLOW_CONTEXT_ACTION_VLAN_PUSH_2 = 0x800, 2464 }; 2465 2466 struct mlx5_ifc_vlan_bits { 2467 u8 ethtype[0x10]; 2468 u8 prio[0x3]; 2469 u8 cfi[0x1]; 2470 u8 vid[0xc]; 2471 }; 2472 2473 struct mlx5_ifc_flow_context_bits { 2474 struct mlx5_ifc_vlan_bits push_vlan; 2475 2476 u8 group_id[0x20]; 2477 2478 u8 reserved_at_40[0x8]; 2479 u8 flow_tag[0x18]; 2480 2481 u8 reserved_at_60[0x10]; 2482 u8 action[0x10]; 2483 2484 u8 extended_destination[0x1]; 2485 u8 reserved_at_80[0x7]; 2486 u8 destination_list_size[0x18]; 2487 2488 u8 reserved_at_a0[0x8]; 2489 u8 flow_counter_list_size[0x18]; 2490 2491 u8 packet_reformat_id[0x20]; 2492 2493 u8 modify_header_id[0x20]; 2494 2495 struct mlx5_ifc_vlan_bits push_vlan_2; 2496 2497 u8 reserved_at_120[0xe0]; 2498 2499 struct mlx5_ifc_fte_match_param_bits match_value; 2500 2501 u8 reserved_at_1200[0x600]; 2502 2503 union mlx5_ifc_dest_format_struct_flow_counter_list_auto_bits destination[0]; 2504 }; 2505 2506 enum { 2507 MLX5_XRC_SRQC_STATE_GOOD = 0x0, 2508 MLX5_XRC_SRQC_STATE_ERROR = 0x1, 2509 }; 2510 2511 struct mlx5_ifc_xrc_srqc_bits { 2512 u8 state[0x4]; 2513 u8 log_xrc_srq_size[0x4]; 2514 u8 reserved_at_8[0x18]; 2515 2516 u8 wq_signature[0x1]; 2517 u8 cont_srq[0x1]; 2518 u8 reserved_at_22[0x1]; 2519 u8 rlky[0x1]; 2520 u8 basic_cyclic_rcv_wqe[0x1]; 2521 u8 log_rq_stride[0x3]; 2522 u8 xrcd[0x18]; 2523 2524 u8 page_offset[0x6]; 2525 u8 reserved_at_46[0x1]; 2526 u8 dbr_umem_valid[0x1]; 2527 u8 cqn[0x18]; 2528 2529 u8 reserved_at_60[0x20]; 2530 2531 u8 user_index_equal_xrc_srqn[0x1]; 2532 u8 reserved_at_81[0x1]; 2533 u8 log_page_size[0x6]; 2534 u8 user_index[0x18]; 2535 2536 u8 reserved_at_a0[0x20]; 2537 2538 u8 reserved_at_c0[0x8]; 2539 u8 pd[0x18]; 2540 2541 u8 lwm[0x10]; 2542 u8 wqe_cnt[0x10]; 2543 2544 u8 reserved_at_100[0x40]; 2545 2546 u8 db_record_addr_h[0x20]; 2547 2548 u8 db_record_addr_l[0x1e]; 2549 u8 reserved_at_17e[0x2]; 2550 2551 u8 reserved_at_180[0x80]; 2552 }; 2553 2554 struct mlx5_ifc_vnic_diagnostic_statistics_bits { 2555 u8 counter_error_queues[0x20]; 2556 2557 u8 total_error_queues[0x20]; 2558 2559 u8 send_queue_priority_update_flow[0x20]; 2560 2561 u8 reserved_at_60[0x20]; 2562 2563 u8 nic_receive_steering_discard[0x40]; 2564 2565 u8 receive_discard_vport_down[0x40]; 2566 2567 u8 transmit_discard_vport_down[0x40]; 2568 2569 u8 reserved_at_140[0xec0]; 2570 }; 2571 2572 struct mlx5_ifc_traffic_counter_bits { 2573 u8 packets[0x40]; 2574 2575 u8 octets[0x40]; 2576 }; 2577 2578 struct mlx5_ifc_tisc_bits { 2579 u8 strict_lag_tx_port_affinity[0x1]; 2580 u8 reserved_at_1[0x3]; 2581 u8 lag_tx_port_affinity[0x04]; 2582 2583 u8 reserved_at_8[0x4]; 2584 u8 prio[0x4]; 2585 u8 reserved_at_10[0x10]; 2586 2587 u8 reserved_at_20[0x100]; 2588 2589 u8 reserved_at_120[0x8]; 2590 u8 transport_domain[0x18]; 2591 2592 u8 reserved_at_140[0x8]; 2593 u8 underlay_qpn[0x18]; 2594 u8 reserved_at_160[0x3a0]; 2595 }; 2596 2597 enum { 2598 MLX5_TIRC_DISP_TYPE_DIRECT = 0x0, 2599 MLX5_TIRC_DISP_TYPE_INDIRECT = 0x1, 2600 }; 2601 2602 enum { 2603 MLX5_TIRC_LRO_ENABLE_MASK_IPV4_LRO = 0x1, 2604 MLX5_TIRC_LRO_ENABLE_MASK_IPV6_LRO = 0x2, 2605 }; 2606 2607 enum { 2608 MLX5_RX_HASH_FN_NONE = 0x0, 2609 MLX5_RX_HASH_FN_INVERTED_XOR8 = 0x1, 2610 MLX5_RX_HASH_FN_TOEPLITZ = 0x2, 2611 }; 2612 2613 enum { 2614 MLX5_TIRC_SELF_LB_BLOCK_BLOCK_UNICAST = 0x1, 2615 MLX5_TIRC_SELF_LB_BLOCK_BLOCK_MULTICAST = 0x2, 2616 }; 2617 2618 struct mlx5_ifc_tirc_bits { 2619 u8 reserved_at_0[0x20]; 2620 2621 u8 disp_type[0x4]; 2622 u8 reserved_at_24[0x1c]; 2623 2624 u8 reserved_at_40[0x40]; 2625 2626 u8 reserved_at_80[0x4]; 2627 u8 lro_timeout_period_usecs[0x10]; 2628 u8 lro_enable_mask[0x4]; 2629 u8 lro_max_ip_payload_size[0x8]; 2630 2631 u8 reserved_at_a0[0x40]; 2632 2633 u8 reserved_at_e0[0x8]; 2634 u8 inline_rqn[0x18]; 2635 2636 u8 rx_hash_symmetric[0x1]; 2637 u8 reserved_at_101[0x1]; 2638 u8 tunneled_offload_en[0x1]; 2639 u8 reserved_at_103[0x5]; 2640 u8 indirect_table[0x18]; 2641 2642 u8 rx_hash_fn[0x4]; 2643 u8 reserved_at_124[0x2]; 2644 u8 self_lb_block[0x2]; 2645 u8 transport_domain[0x18]; 2646 2647 u8 rx_hash_toeplitz_key[10][0x20]; 2648 2649 struct mlx5_ifc_rx_hash_field_select_bits rx_hash_field_selector_outer; 2650 2651 struct mlx5_ifc_rx_hash_field_select_bits rx_hash_field_selector_inner; 2652 2653 u8 reserved_at_2c0[0x4c0]; 2654 }; 2655 2656 enum { 2657 MLX5_SRQC_STATE_GOOD = 0x0, 2658 MLX5_SRQC_STATE_ERROR = 0x1, 2659 }; 2660 2661 struct mlx5_ifc_srqc_bits { 2662 u8 state[0x4]; 2663 u8 log_srq_size[0x4]; 2664 u8 reserved_at_8[0x18]; 2665 2666 u8 wq_signature[0x1]; 2667 u8 cont_srq[0x1]; 2668 u8 reserved_at_22[0x1]; 2669 u8 rlky[0x1]; 2670 u8 reserved_at_24[0x1]; 2671 u8 log_rq_stride[0x3]; 2672 u8 xrcd[0x18]; 2673 2674 u8 page_offset[0x6]; 2675 u8 reserved_at_46[0x2]; 2676 u8 cqn[0x18]; 2677 2678 u8 reserved_at_60[0x20]; 2679 2680 u8 reserved_at_80[0x2]; 2681 u8 log_page_size[0x6]; 2682 u8 reserved_at_88[0x18]; 2683 2684 u8 reserved_at_a0[0x20]; 2685 2686 u8 reserved_at_c0[0x8]; 2687 u8 pd[0x18]; 2688 2689 u8 lwm[0x10]; 2690 u8 wqe_cnt[0x10]; 2691 2692 u8 reserved_at_100[0x40]; 2693 2694 u8 dbr_addr[0x40]; 2695 2696 u8 reserved_at_180[0x80]; 2697 }; 2698 2699 enum { 2700 MLX5_SQC_STATE_RST = 0x0, 2701 MLX5_SQC_STATE_RDY = 0x1, 2702 MLX5_SQC_STATE_ERR = 0x3, 2703 }; 2704 2705 struct mlx5_ifc_sqc_bits { 2706 u8 rlky[0x1]; 2707 u8 cd_master[0x1]; 2708 u8 fre[0x1]; 2709 u8 flush_in_error_en[0x1]; 2710 u8 allow_multi_pkt_send_wqe[0x1]; 2711 u8 min_wqe_inline_mode[0x3]; 2712 u8 state[0x4]; 2713 u8 reg_umr[0x1]; 2714 u8 allow_swp[0x1]; 2715 u8 hairpin[0x1]; 2716 u8 reserved_at_f[0x11]; 2717 2718 u8 reserved_at_20[0x8]; 2719 u8 user_index[0x18]; 2720 2721 u8 reserved_at_40[0x8]; 2722 u8 cqn[0x18]; 2723 2724 u8 reserved_at_60[0x8]; 2725 u8 hairpin_peer_rq[0x18]; 2726 2727 u8 reserved_at_80[0x10]; 2728 u8 hairpin_peer_vhca[0x10]; 2729 2730 u8 reserved_at_a0[0x50]; 2731 2732 u8 packet_pacing_rate_limit_index[0x10]; 2733 u8 tis_lst_sz[0x10]; 2734 u8 reserved_at_110[0x10]; 2735 2736 u8 reserved_at_120[0x40]; 2737 2738 u8 reserved_at_160[0x8]; 2739 u8 tis_num_0[0x18]; 2740 2741 struct mlx5_ifc_wq_bits wq; 2742 }; 2743 2744 enum { 2745 SCHEDULING_CONTEXT_ELEMENT_TYPE_TSAR = 0x0, 2746 SCHEDULING_CONTEXT_ELEMENT_TYPE_VPORT = 0x1, 2747 SCHEDULING_CONTEXT_ELEMENT_TYPE_VPORT_TC = 0x2, 2748 SCHEDULING_CONTEXT_ELEMENT_TYPE_PARA_VPORT_TC = 0x3, 2749 }; 2750 2751 struct mlx5_ifc_scheduling_context_bits { 2752 u8 element_type[0x8]; 2753 u8 reserved_at_8[0x18]; 2754 2755 u8 element_attributes[0x20]; 2756 2757 u8 parent_element_id[0x20]; 2758 2759 u8 reserved_at_60[0x40]; 2760 2761 u8 bw_share[0x20]; 2762 2763 u8 max_average_bw[0x20]; 2764 2765 u8 reserved_at_e0[0x120]; 2766 }; 2767 2768 struct mlx5_ifc_rqtc_bits { 2769 u8 reserved_at_0[0xa0]; 2770 2771 u8 reserved_at_a0[0x10]; 2772 u8 rqt_max_size[0x10]; 2773 2774 u8 reserved_at_c0[0x10]; 2775 u8 rqt_actual_size[0x10]; 2776 2777 u8 reserved_at_e0[0x6a0]; 2778 2779 struct mlx5_ifc_rq_num_bits rq_num[0]; 2780 }; 2781 2782 enum { 2783 MLX5_RQC_MEM_RQ_TYPE_MEMORY_RQ_INLINE = 0x0, 2784 MLX5_RQC_MEM_RQ_TYPE_MEMORY_RQ_RMP = 0x1, 2785 }; 2786 2787 enum { 2788 MLX5_RQC_STATE_RST = 0x0, 2789 MLX5_RQC_STATE_RDY = 0x1, 2790 MLX5_RQC_STATE_ERR = 0x3, 2791 }; 2792 2793 struct mlx5_ifc_rqc_bits { 2794 u8 rlky[0x1]; 2795 u8 delay_drop_en[0x1]; 2796 u8 scatter_fcs[0x1]; 2797 u8 vsd[0x1]; 2798 u8 mem_rq_type[0x4]; 2799 u8 state[0x4]; 2800 u8 reserved_at_c[0x1]; 2801 u8 flush_in_error_en[0x1]; 2802 u8 hairpin[0x1]; 2803 u8 reserved_at_f[0x11]; 2804 2805 u8 reserved_at_20[0x8]; 2806 u8 user_index[0x18]; 2807 2808 u8 reserved_at_40[0x8]; 2809 u8 cqn[0x18]; 2810 2811 u8 counter_set_id[0x8]; 2812 u8 reserved_at_68[0x18]; 2813 2814 u8 reserved_at_80[0x8]; 2815 u8 rmpn[0x18]; 2816 2817 u8 reserved_at_a0[0x8]; 2818 u8 hairpin_peer_sq[0x18]; 2819 2820 u8 reserved_at_c0[0x10]; 2821 u8 hairpin_peer_vhca[0x10]; 2822 2823 u8 reserved_at_e0[0xa0]; 2824 2825 struct mlx5_ifc_wq_bits wq; 2826 }; 2827 2828 enum { 2829 MLX5_RMPC_STATE_RDY = 0x1, 2830 MLX5_RMPC_STATE_ERR = 0x3, 2831 }; 2832 2833 struct mlx5_ifc_rmpc_bits { 2834 u8 reserved_at_0[0x8]; 2835 u8 state[0x4]; 2836 u8 reserved_at_c[0x14]; 2837 2838 u8 basic_cyclic_rcv_wqe[0x1]; 2839 u8 reserved_at_21[0x1f]; 2840 2841 u8 reserved_at_40[0x140]; 2842 2843 struct mlx5_ifc_wq_bits wq; 2844 }; 2845 2846 struct mlx5_ifc_nic_vport_context_bits { 2847 u8 reserved_at_0[0x5]; 2848 u8 min_wqe_inline_mode[0x3]; 2849 u8 reserved_at_8[0x15]; 2850 u8 disable_mc_local_lb[0x1]; 2851 u8 disable_uc_local_lb[0x1]; 2852 u8 roce_en[0x1]; 2853 2854 u8 arm_change_event[0x1]; 2855 u8 reserved_at_21[0x1a]; 2856 u8 event_on_mtu[0x1]; 2857 u8 event_on_promisc_change[0x1]; 2858 u8 event_on_vlan_change[0x1]; 2859 u8 event_on_mc_address_change[0x1]; 2860 u8 event_on_uc_address_change[0x1]; 2861 2862 u8 reserved_at_40[0xc]; 2863 2864 u8 affiliation_criteria[0x4]; 2865 u8 affiliated_vhca_id[0x10]; 2866 2867 u8 reserved_at_60[0xd0]; 2868 2869 u8 mtu[0x10]; 2870 2871 u8 system_image_guid[0x40]; 2872 u8 port_guid[0x40]; 2873 u8 node_guid[0x40]; 2874 2875 u8 reserved_at_200[0x140]; 2876 u8 qkey_violation_counter[0x10]; 2877 u8 reserved_at_350[0x430]; 2878 2879 u8 promisc_uc[0x1]; 2880 u8 promisc_mc[0x1]; 2881 u8 promisc_all[0x1]; 2882 u8 reserved_at_783[0x2]; 2883 u8 allowed_list_type[0x3]; 2884 u8 reserved_at_788[0xc]; 2885 u8 allowed_list_size[0xc]; 2886 2887 struct mlx5_ifc_mac_address_layout_bits permanent_address; 2888 2889 u8 reserved_at_7e0[0x20]; 2890 2891 u8 current_uc_mac_address[0][0x40]; 2892 }; 2893 2894 enum { 2895 MLX5_MKC_ACCESS_MODE_PA = 0x0, 2896 MLX5_MKC_ACCESS_MODE_MTT = 0x1, 2897 MLX5_MKC_ACCESS_MODE_KLMS = 0x2, 2898 MLX5_MKC_ACCESS_MODE_KSM = 0x3, 2899 MLX5_MKC_ACCESS_MODE_MEMIC = 0x5, 2900 }; 2901 2902 struct mlx5_ifc_mkc_bits { 2903 u8 reserved_at_0[0x1]; 2904 u8 free[0x1]; 2905 u8 reserved_at_2[0x1]; 2906 u8 access_mode_4_2[0x3]; 2907 u8 reserved_at_6[0x7]; 2908 u8 relaxed_ordering_write[0x1]; 2909 u8 reserved_at_e[0x1]; 2910 u8 small_fence_on_rdma_read_response[0x1]; 2911 u8 umr_en[0x1]; 2912 u8 a[0x1]; 2913 u8 rw[0x1]; 2914 u8 rr[0x1]; 2915 u8 lw[0x1]; 2916 u8 lr[0x1]; 2917 u8 access_mode_1_0[0x2]; 2918 u8 reserved_at_18[0x8]; 2919 2920 u8 qpn[0x18]; 2921 u8 mkey_7_0[0x8]; 2922 2923 u8 reserved_at_40[0x20]; 2924 2925 u8 length64[0x1]; 2926 u8 bsf_en[0x1]; 2927 u8 sync_umr[0x1]; 2928 u8 reserved_at_63[0x2]; 2929 u8 expected_sigerr_count[0x1]; 2930 u8 reserved_at_66[0x1]; 2931 u8 en_rinval[0x1]; 2932 u8 pd[0x18]; 2933 2934 u8 start_addr[0x40]; 2935 2936 u8 len[0x40]; 2937 2938 u8 bsf_octword_size[0x20]; 2939 2940 u8 reserved_at_120[0x80]; 2941 2942 u8 translations_octword_size[0x20]; 2943 2944 u8 reserved_at_1c0[0x1b]; 2945 u8 log_page_size[0x5]; 2946 2947 u8 reserved_at_1e0[0x20]; 2948 }; 2949 2950 struct mlx5_ifc_pkey_bits { 2951 u8 reserved_at_0[0x10]; 2952 u8 pkey[0x10]; 2953 }; 2954 2955 struct mlx5_ifc_array128_auto_bits { 2956 u8 array128_auto[16][0x8]; 2957 }; 2958 2959 struct mlx5_ifc_hca_vport_context_bits { 2960 u8 field_select[0x20]; 2961 2962 u8 reserved_at_20[0xe0]; 2963 2964 u8 sm_virt_aware[0x1]; 2965 u8 has_smi[0x1]; 2966 u8 has_raw[0x1]; 2967 u8 grh_required[0x1]; 2968 u8 reserved_at_104[0xc]; 2969 u8 port_physical_state[0x4]; 2970 u8 vport_state_policy[0x4]; 2971 u8 port_state[0x4]; 2972 u8 vport_state[0x4]; 2973 2974 u8 reserved_at_120[0x20]; 2975 2976 u8 system_image_guid[0x40]; 2977 2978 u8 port_guid[0x40]; 2979 2980 u8 node_guid[0x40]; 2981 2982 u8 cap_mask1[0x20]; 2983 2984 u8 cap_mask1_field_select[0x20]; 2985 2986 u8 cap_mask2[0x20]; 2987 2988 u8 cap_mask2_field_select[0x20]; 2989 2990 u8 reserved_at_280[0x80]; 2991 2992 u8 lid[0x10]; 2993 u8 reserved_at_310[0x4]; 2994 u8 init_type_reply[0x4]; 2995 u8 lmc[0x3]; 2996 u8 subnet_timeout[0x5]; 2997 2998 u8 sm_lid[0x10]; 2999 u8 sm_sl[0x4]; 3000 u8 reserved_at_334[0xc]; 3001 3002 u8 qkey_violation_counter[0x10]; 3003 u8 pkey_violation_counter[0x10]; 3004 3005 u8 reserved_at_360[0xca0]; 3006 }; 3007 3008 struct mlx5_ifc_esw_vport_context_bits { 3009 u8 reserved_at_0[0x3]; 3010 u8 vport_svlan_strip[0x1]; 3011 u8 vport_cvlan_strip[0x1]; 3012 u8 vport_svlan_insert[0x1]; 3013 u8 vport_cvlan_insert[0x2]; 3014 u8 reserved_at_8[0x18]; 3015 3016 u8 reserved_at_20[0x20]; 3017 3018 u8 svlan_cfi[0x1]; 3019 u8 svlan_pcp[0x3]; 3020 u8 svlan_id[0xc]; 3021 u8 cvlan_cfi[0x1]; 3022 u8 cvlan_pcp[0x3]; 3023 u8 cvlan_id[0xc]; 3024 3025 u8 reserved_at_60[0x7a0]; 3026 }; 3027 3028 enum { 3029 MLX5_EQC_STATUS_OK = 0x0, 3030 MLX5_EQC_STATUS_EQ_WRITE_FAILURE = 0xa, 3031 }; 3032 3033 enum { 3034 MLX5_EQC_ST_ARMED = 0x9, 3035 MLX5_EQC_ST_FIRED = 0xa, 3036 }; 3037 3038 struct mlx5_ifc_eqc_bits { 3039 u8 status[0x4]; 3040 u8 reserved_at_4[0x9]; 3041 u8 ec[0x1]; 3042 u8 oi[0x1]; 3043 u8 reserved_at_f[0x5]; 3044 u8 st[0x4]; 3045 u8 reserved_at_18[0x8]; 3046 3047 u8 reserved_at_20[0x20]; 3048 3049 u8 reserved_at_40[0x14]; 3050 u8 page_offset[0x6]; 3051 u8 reserved_at_5a[0x6]; 3052 3053 u8 reserved_at_60[0x3]; 3054 u8 log_eq_size[0x5]; 3055 u8 uar_page[0x18]; 3056 3057 u8 reserved_at_80[0x20]; 3058 3059 u8 reserved_at_a0[0x18]; 3060 u8 intr[0x8]; 3061 3062 u8 reserved_at_c0[0x3]; 3063 u8 log_page_size[0x5]; 3064 u8 reserved_at_c8[0x18]; 3065 3066 u8 reserved_at_e0[0x60]; 3067 3068 u8 reserved_at_140[0x8]; 3069 u8 consumer_counter[0x18]; 3070 3071 u8 reserved_at_160[0x8]; 3072 u8 producer_counter[0x18]; 3073 3074 u8 reserved_at_180[0x80]; 3075 }; 3076 3077 enum { 3078 MLX5_DCTC_STATE_ACTIVE = 0x0, 3079 MLX5_DCTC_STATE_DRAINING = 0x1, 3080 MLX5_DCTC_STATE_DRAINED = 0x2, 3081 }; 3082 3083 enum { 3084 MLX5_DCTC_CS_RES_DISABLE = 0x0, 3085 MLX5_DCTC_CS_RES_NA = 0x1, 3086 MLX5_DCTC_CS_RES_UP_TO_64B = 0x2, 3087 }; 3088 3089 enum { 3090 MLX5_DCTC_MTU_256_BYTES = 0x1, 3091 MLX5_DCTC_MTU_512_BYTES = 0x2, 3092 MLX5_DCTC_MTU_1K_BYTES = 0x3, 3093 MLX5_DCTC_MTU_2K_BYTES = 0x4, 3094 MLX5_DCTC_MTU_4K_BYTES = 0x5, 3095 }; 3096 3097 struct mlx5_ifc_dctc_bits { 3098 u8 reserved_at_0[0x4]; 3099 u8 state[0x4]; 3100 u8 reserved_at_8[0x18]; 3101 3102 u8 reserved_at_20[0x8]; 3103 u8 user_index[0x18]; 3104 3105 u8 reserved_at_40[0x8]; 3106 u8 cqn[0x18]; 3107 3108 u8 counter_set_id[0x8]; 3109 u8 atomic_mode[0x4]; 3110 u8 rre[0x1]; 3111 u8 rwe[0x1]; 3112 u8 rae[0x1]; 3113 u8 atomic_like_write_en[0x1]; 3114 u8 latency_sensitive[0x1]; 3115 u8 rlky[0x1]; 3116 u8 free_ar[0x1]; 3117 u8 reserved_at_73[0xd]; 3118 3119 u8 reserved_at_80[0x8]; 3120 u8 cs_res[0x8]; 3121 u8 reserved_at_90[0x3]; 3122 u8 min_rnr_nak[0x5]; 3123 u8 reserved_at_98[0x8]; 3124 3125 u8 reserved_at_a0[0x8]; 3126 u8 srqn_xrqn[0x18]; 3127 3128 u8 reserved_at_c0[0x8]; 3129 u8 pd[0x18]; 3130 3131 u8 tclass[0x8]; 3132 u8 reserved_at_e8[0x4]; 3133 u8 flow_label[0x14]; 3134 3135 u8 dc_access_key[0x40]; 3136 3137 u8 reserved_at_140[0x5]; 3138 u8 mtu[0x3]; 3139 u8 port[0x8]; 3140 u8 pkey_index[0x10]; 3141 3142 u8 reserved_at_160[0x8]; 3143 u8 my_addr_index[0x8]; 3144 u8 reserved_at_170[0x8]; 3145 u8 hop_limit[0x8]; 3146 3147 u8 dc_access_key_violation_count[0x20]; 3148 3149 u8 reserved_at_1a0[0x14]; 3150 u8 dei_cfi[0x1]; 3151 u8 eth_prio[0x3]; 3152 u8 ecn[0x2]; 3153 u8 dscp[0x6]; 3154 3155 u8 reserved_at_1c0[0x40]; 3156 }; 3157 3158 enum { 3159 MLX5_CQC_STATUS_OK = 0x0, 3160 MLX5_CQC_STATUS_CQ_OVERFLOW = 0x9, 3161 MLX5_CQC_STATUS_CQ_WRITE_FAIL = 0xa, 3162 }; 3163 3164 enum { 3165 MLX5_CQC_CQE_SZ_64_BYTES = 0x0, 3166 MLX5_CQC_CQE_SZ_128_BYTES = 0x1, 3167 }; 3168 3169 enum { 3170 MLX5_CQC_ST_SOLICITED_NOTIFICATION_REQUEST_ARMED = 0x6, 3171 MLX5_CQC_ST_NOTIFICATION_REQUEST_ARMED = 0x9, 3172 MLX5_CQC_ST_FIRED = 0xa, 3173 }; 3174 3175 enum { 3176 MLX5_CQ_PERIOD_MODE_START_FROM_EQE = 0x0, 3177 MLX5_CQ_PERIOD_MODE_START_FROM_CQE = 0x1, 3178 MLX5_CQ_PERIOD_NUM_MODES 3179 }; 3180 3181 struct mlx5_ifc_cqc_bits { 3182 u8 status[0x4]; 3183 u8 reserved_at_4[0x2]; 3184 u8 dbr_umem_valid[0x1]; 3185 u8 reserved_at_7[0x1]; 3186 u8 cqe_sz[0x3]; 3187 u8 cc[0x1]; 3188 u8 reserved_at_c[0x1]; 3189 u8 scqe_break_moderation_en[0x1]; 3190 u8 oi[0x1]; 3191 u8 cq_period_mode[0x2]; 3192 u8 cqe_comp_en[0x1]; 3193 u8 mini_cqe_res_format[0x2]; 3194 u8 st[0x4]; 3195 u8 reserved_at_18[0x8]; 3196 3197 u8 reserved_at_20[0x20]; 3198 3199 u8 reserved_at_40[0x14]; 3200 u8 page_offset[0x6]; 3201 u8 reserved_at_5a[0x6]; 3202 3203 u8 reserved_at_60[0x3]; 3204 u8 log_cq_size[0x5]; 3205 u8 uar_page[0x18]; 3206 3207 u8 reserved_at_80[0x4]; 3208 u8 cq_period[0xc]; 3209 u8 cq_max_count[0x10]; 3210 3211 u8 reserved_at_a0[0x18]; 3212 u8 c_eqn[0x8]; 3213 3214 u8 reserved_at_c0[0x3]; 3215 u8 log_page_size[0x5]; 3216 u8 reserved_at_c8[0x18]; 3217 3218 u8 reserved_at_e0[0x20]; 3219 3220 u8 reserved_at_100[0x8]; 3221 u8 last_notified_index[0x18]; 3222 3223 u8 reserved_at_120[0x8]; 3224 u8 last_solicit_index[0x18]; 3225 3226 u8 reserved_at_140[0x8]; 3227 u8 consumer_counter[0x18]; 3228 3229 u8 reserved_at_160[0x8]; 3230 u8 producer_counter[0x18]; 3231 3232 u8 reserved_at_180[0x40]; 3233 3234 u8 dbr_addr[0x40]; 3235 }; 3236 3237 union mlx5_ifc_cong_control_roce_ecn_auto_bits { 3238 struct mlx5_ifc_cong_control_802_1qau_rp_bits cong_control_802_1qau_rp; 3239 struct mlx5_ifc_cong_control_r_roce_ecn_rp_bits cong_control_r_roce_ecn_rp; 3240 struct mlx5_ifc_cong_control_r_roce_ecn_np_bits cong_control_r_roce_ecn_np; 3241 u8 reserved_at_0[0x800]; 3242 }; 3243 3244 struct mlx5_ifc_query_adapter_param_block_bits { 3245 u8 reserved_at_0[0xc0]; 3246 3247 u8 reserved_at_c0[0x8]; 3248 u8 ieee_vendor_id[0x18]; 3249 3250 u8 reserved_at_e0[0x10]; 3251 u8 vsd_vendor_id[0x10]; 3252 3253 u8 vsd[208][0x8]; 3254 3255 u8 vsd_contd_psid[16][0x8]; 3256 }; 3257 3258 enum { 3259 MLX5_XRQC_STATE_GOOD = 0x0, 3260 MLX5_XRQC_STATE_ERROR = 0x1, 3261 }; 3262 3263 enum { 3264 MLX5_XRQC_TOPOLOGY_NO_SPECIAL_TOPOLOGY = 0x0, 3265 MLX5_XRQC_TOPOLOGY_TAG_MATCHING = 0x1, 3266 }; 3267 3268 enum { 3269 MLX5_XRQC_OFFLOAD_RNDV = 0x1, 3270 }; 3271 3272 struct mlx5_ifc_tag_matching_topology_context_bits { 3273 u8 log_matching_list_sz[0x4]; 3274 u8 reserved_at_4[0xc]; 3275 u8 append_next_index[0x10]; 3276 3277 u8 sw_phase_cnt[0x10]; 3278 u8 hw_phase_cnt[0x10]; 3279 3280 u8 reserved_at_40[0x40]; 3281 }; 3282 3283 struct mlx5_ifc_xrqc_bits { 3284 u8 state[0x4]; 3285 u8 rlkey[0x1]; 3286 u8 reserved_at_5[0xf]; 3287 u8 topology[0x4]; 3288 u8 reserved_at_18[0x4]; 3289 u8 offload[0x4]; 3290 3291 u8 reserved_at_20[0x8]; 3292 u8 user_index[0x18]; 3293 3294 u8 reserved_at_40[0x8]; 3295 u8 cqn[0x18]; 3296 3297 u8 reserved_at_60[0xa0]; 3298 3299 struct mlx5_ifc_tag_matching_topology_context_bits tag_matching_topology_context; 3300 3301 u8 reserved_at_180[0x280]; 3302 3303 struct mlx5_ifc_wq_bits wq; 3304 }; 3305 3306 union mlx5_ifc_modify_field_select_resize_field_select_auto_bits { 3307 struct mlx5_ifc_modify_field_select_bits modify_field_select; 3308 struct mlx5_ifc_resize_field_select_bits resize_field_select; 3309 u8 reserved_at_0[0x20]; 3310 }; 3311 3312 union mlx5_ifc_field_select_802_1_r_roce_auto_bits { 3313 struct mlx5_ifc_field_select_802_1qau_rp_bits field_select_802_1qau_rp; 3314 struct mlx5_ifc_field_select_r_roce_rp_bits field_select_r_roce_rp; 3315 struct mlx5_ifc_field_select_r_roce_np_bits field_select_r_roce_np; 3316 u8 reserved_at_0[0x20]; 3317 }; 3318 3319 union mlx5_ifc_eth_cntrs_grp_data_layout_auto_bits { 3320 struct mlx5_ifc_eth_802_3_cntrs_grp_data_layout_bits eth_802_3_cntrs_grp_data_layout; 3321 struct mlx5_ifc_eth_2863_cntrs_grp_data_layout_bits eth_2863_cntrs_grp_data_layout; 3322 struct mlx5_ifc_eth_2819_cntrs_grp_data_layout_bits eth_2819_cntrs_grp_data_layout; 3323 struct mlx5_ifc_eth_3635_cntrs_grp_data_layout_bits eth_3635_cntrs_grp_data_layout; 3324 struct mlx5_ifc_eth_extended_cntrs_grp_data_layout_bits eth_extended_cntrs_grp_data_layout; 3325 struct mlx5_ifc_eth_per_prio_grp_data_layout_bits eth_per_prio_grp_data_layout; 3326 struct mlx5_ifc_eth_per_traffic_grp_data_layout_bits eth_per_traffic_grp_data_layout; 3327 struct mlx5_ifc_ib_port_cntrs_grp_data_layout_bits ib_port_cntrs_grp_data_layout; 3328 struct mlx5_ifc_phys_layer_cntrs_bits phys_layer_cntrs; 3329 struct mlx5_ifc_phys_layer_statistical_cntrs_bits phys_layer_statistical_cntrs; 3330 u8 reserved_at_0[0x7c0]; 3331 }; 3332 3333 union mlx5_ifc_pcie_cntrs_grp_data_layout_auto_bits { 3334 struct mlx5_ifc_pcie_perf_cntrs_grp_data_layout_bits pcie_perf_cntrs_grp_data_layout; 3335 u8 reserved_at_0[0x7c0]; 3336 }; 3337 3338 union mlx5_ifc_event_auto_bits { 3339 struct mlx5_ifc_comp_event_bits comp_event; 3340 struct mlx5_ifc_dct_events_bits dct_events; 3341 struct mlx5_ifc_qp_events_bits qp_events; 3342 struct mlx5_ifc_wqe_associated_page_fault_event_bits wqe_associated_page_fault_event; 3343 struct mlx5_ifc_rdma_page_fault_event_bits rdma_page_fault_event; 3344 struct mlx5_ifc_cq_error_bits cq_error; 3345 struct mlx5_ifc_dropped_packet_logged_bits dropped_packet_logged; 3346 struct mlx5_ifc_port_state_change_event_bits port_state_change_event; 3347 struct mlx5_ifc_gpio_event_bits gpio_event; 3348 struct mlx5_ifc_db_bf_congestion_event_bits db_bf_congestion_event; 3349 struct mlx5_ifc_stall_vl_event_bits stall_vl_event; 3350 struct mlx5_ifc_cmd_inter_comp_event_bits cmd_inter_comp_event; 3351 u8 reserved_at_0[0xe0]; 3352 }; 3353 3354 struct mlx5_ifc_health_buffer_bits { 3355 u8 reserved_at_0[0x100]; 3356 3357 u8 assert_existptr[0x20]; 3358 3359 u8 assert_callra[0x20]; 3360 3361 u8 reserved_at_140[0x40]; 3362 3363 u8 fw_version[0x20]; 3364 3365 u8 hw_id[0x20]; 3366 3367 u8 reserved_at_1c0[0x20]; 3368 3369 u8 irisc_index[0x8]; 3370 u8 synd[0x8]; 3371 u8 ext_synd[0x10]; 3372 }; 3373 3374 struct mlx5_ifc_register_loopback_control_bits { 3375 u8 no_lb[0x1]; 3376 u8 reserved_at_1[0x7]; 3377 u8 port[0x8]; 3378 u8 reserved_at_10[0x10]; 3379 3380 u8 reserved_at_20[0x60]; 3381 }; 3382 3383 struct mlx5_ifc_vport_tc_element_bits { 3384 u8 traffic_class[0x4]; 3385 u8 reserved_at_4[0xc]; 3386 u8 vport_number[0x10]; 3387 }; 3388 3389 struct mlx5_ifc_vport_element_bits { 3390 u8 reserved_at_0[0x10]; 3391 u8 vport_number[0x10]; 3392 }; 3393 3394 enum { 3395 TSAR_ELEMENT_TSAR_TYPE_DWRR = 0x0, 3396 TSAR_ELEMENT_TSAR_TYPE_ROUND_ROBIN = 0x1, 3397 TSAR_ELEMENT_TSAR_TYPE_ETS = 0x2, 3398 }; 3399 3400 struct mlx5_ifc_tsar_element_bits { 3401 u8 reserved_at_0[0x8]; 3402 u8 tsar_type[0x8]; 3403 u8 reserved_at_10[0x10]; 3404 }; 3405 3406 enum { 3407 MLX5_TEARDOWN_HCA_OUT_FORCE_STATE_SUCCESS = 0x0, 3408 MLX5_TEARDOWN_HCA_OUT_FORCE_STATE_FAIL = 0x1, 3409 }; 3410 3411 struct mlx5_ifc_teardown_hca_out_bits { 3412 u8 status[0x8]; 3413 u8 reserved_at_8[0x18]; 3414 3415 u8 syndrome[0x20]; 3416 3417 u8 reserved_at_40[0x3f]; 3418 3419 u8 state[0x1]; 3420 }; 3421 3422 enum { 3423 MLX5_TEARDOWN_HCA_IN_PROFILE_GRACEFUL_CLOSE = 0x0, 3424 MLX5_TEARDOWN_HCA_IN_PROFILE_FORCE_CLOSE = 0x1, 3425 MLX5_TEARDOWN_HCA_IN_PROFILE_PREPARE_FAST_TEARDOWN = 0x2, 3426 }; 3427 3428 struct mlx5_ifc_teardown_hca_in_bits { 3429 u8 opcode[0x10]; 3430 u8 reserved_at_10[0x10]; 3431 3432 u8 reserved_at_20[0x10]; 3433 u8 op_mod[0x10]; 3434 3435 u8 reserved_at_40[0x10]; 3436 u8 profile[0x10]; 3437 3438 u8 reserved_at_60[0x20]; 3439 }; 3440 3441 struct mlx5_ifc_sqerr2rts_qp_out_bits { 3442 u8 status[0x8]; 3443 u8 reserved_at_8[0x18]; 3444 3445 u8 syndrome[0x20]; 3446 3447 u8 reserved_at_40[0x40]; 3448 }; 3449 3450 struct mlx5_ifc_sqerr2rts_qp_in_bits { 3451 u8 opcode[0x10]; 3452 u8 uid[0x10]; 3453 3454 u8 reserved_at_20[0x10]; 3455 u8 op_mod[0x10]; 3456 3457 u8 reserved_at_40[0x8]; 3458 u8 qpn[0x18]; 3459 3460 u8 reserved_at_60[0x20]; 3461 3462 u8 opt_param_mask[0x20]; 3463 3464 u8 reserved_at_a0[0x20]; 3465 3466 struct mlx5_ifc_qpc_bits qpc; 3467 3468 u8 reserved_at_800[0x80]; 3469 }; 3470 3471 struct mlx5_ifc_sqd2rts_qp_out_bits { 3472 u8 status[0x8]; 3473 u8 reserved_at_8[0x18]; 3474 3475 u8 syndrome[0x20]; 3476 3477 u8 reserved_at_40[0x40]; 3478 }; 3479 3480 struct mlx5_ifc_sqd2rts_qp_in_bits { 3481 u8 opcode[0x10]; 3482 u8 uid[0x10]; 3483 3484 u8 reserved_at_20[0x10]; 3485 u8 op_mod[0x10]; 3486 3487 u8 reserved_at_40[0x8]; 3488 u8 qpn[0x18]; 3489 3490 u8 reserved_at_60[0x20]; 3491 3492 u8 opt_param_mask[0x20]; 3493 3494 u8 reserved_at_a0[0x20]; 3495 3496 struct mlx5_ifc_qpc_bits qpc; 3497 3498 u8 reserved_at_800[0x80]; 3499 }; 3500 3501 struct mlx5_ifc_set_roce_address_out_bits { 3502 u8 status[0x8]; 3503 u8 reserved_at_8[0x18]; 3504 3505 u8 syndrome[0x20]; 3506 3507 u8 reserved_at_40[0x40]; 3508 }; 3509 3510 struct mlx5_ifc_set_roce_address_in_bits { 3511 u8 opcode[0x10]; 3512 u8 reserved_at_10[0x10]; 3513 3514 u8 reserved_at_20[0x10]; 3515 u8 op_mod[0x10]; 3516 3517 u8 roce_address_index[0x10]; 3518 u8 reserved_at_50[0xc]; 3519 u8 vhca_port_num[0x4]; 3520 3521 u8 reserved_at_60[0x20]; 3522 3523 struct mlx5_ifc_roce_addr_layout_bits roce_address; 3524 }; 3525 3526 struct mlx5_ifc_set_mad_demux_out_bits { 3527 u8 status[0x8]; 3528 u8 reserved_at_8[0x18]; 3529 3530 u8 syndrome[0x20]; 3531 3532 u8 reserved_at_40[0x40]; 3533 }; 3534 3535 enum { 3536 MLX5_SET_MAD_DEMUX_IN_DEMUX_MODE_PASS_ALL = 0x0, 3537 MLX5_SET_MAD_DEMUX_IN_DEMUX_MODE_SELECTIVE = 0x2, 3538 }; 3539 3540 struct mlx5_ifc_set_mad_demux_in_bits { 3541 u8 opcode[0x10]; 3542 u8 reserved_at_10[0x10]; 3543 3544 u8 reserved_at_20[0x10]; 3545 u8 op_mod[0x10]; 3546 3547 u8 reserved_at_40[0x20]; 3548 3549 u8 reserved_at_60[0x6]; 3550 u8 demux_mode[0x2]; 3551 u8 reserved_at_68[0x18]; 3552 }; 3553 3554 struct mlx5_ifc_set_l2_table_entry_out_bits { 3555 u8 status[0x8]; 3556 u8 reserved_at_8[0x18]; 3557 3558 u8 syndrome[0x20]; 3559 3560 u8 reserved_at_40[0x40]; 3561 }; 3562 3563 struct mlx5_ifc_set_l2_table_entry_in_bits { 3564 u8 opcode[0x10]; 3565 u8 reserved_at_10[0x10]; 3566 3567 u8 reserved_at_20[0x10]; 3568 u8 op_mod[0x10]; 3569 3570 u8 reserved_at_40[0x60]; 3571 3572 u8 reserved_at_a0[0x8]; 3573 u8 table_index[0x18]; 3574 3575 u8 reserved_at_c0[0x20]; 3576 3577 u8 reserved_at_e0[0x13]; 3578 u8 vlan_valid[0x1]; 3579 u8 vlan[0xc]; 3580 3581 struct mlx5_ifc_mac_address_layout_bits mac_address; 3582 3583 u8 reserved_at_140[0xc0]; 3584 }; 3585 3586 struct mlx5_ifc_set_issi_out_bits { 3587 u8 status[0x8]; 3588 u8 reserved_at_8[0x18]; 3589 3590 u8 syndrome[0x20]; 3591 3592 u8 reserved_at_40[0x40]; 3593 }; 3594 3595 struct mlx5_ifc_set_issi_in_bits { 3596 u8 opcode[0x10]; 3597 u8 reserved_at_10[0x10]; 3598 3599 u8 reserved_at_20[0x10]; 3600 u8 op_mod[0x10]; 3601 3602 u8 reserved_at_40[0x10]; 3603 u8 current_issi[0x10]; 3604 3605 u8 reserved_at_60[0x20]; 3606 }; 3607 3608 struct mlx5_ifc_set_hca_cap_out_bits { 3609 u8 status[0x8]; 3610 u8 reserved_at_8[0x18]; 3611 3612 u8 syndrome[0x20]; 3613 3614 u8 reserved_at_40[0x40]; 3615 }; 3616 3617 struct mlx5_ifc_set_hca_cap_in_bits { 3618 u8 opcode[0x10]; 3619 u8 reserved_at_10[0x10]; 3620 3621 u8 reserved_at_20[0x10]; 3622 u8 op_mod[0x10]; 3623 3624 u8 reserved_at_40[0x40]; 3625 3626 union mlx5_ifc_hca_cap_union_bits capability; 3627 }; 3628 3629 enum { 3630 MLX5_SET_FTE_MODIFY_ENABLE_MASK_ACTION = 0x0, 3631 MLX5_SET_FTE_MODIFY_ENABLE_MASK_FLOW_TAG = 0x1, 3632 MLX5_SET_FTE_MODIFY_ENABLE_MASK_DESTINATION_LIST = 0x2, 3633 MLX5_SET_FTE_MODIFY_ENABLE_MASK_FLOW_COUNTERS = 0x3 3634 }; 3635 3636 struct mlx5_ifc_set_fte_out_bits { 3637 u8 status[0x8]; 3638 u8 reserved_at_8[0x18]; 3639 3640 u8 syndrome[0x20]; 3641 3642 u8 reserved_at_40[0x40]; 3643 }; 3644 3645 struct mlx5_ifc_set_fte_in_bits { 3646 u8 opcode[0x10]; 3647 u8 reserved_at_10[0x10]; 3648 3649 u8 reserved_at_20[0x10]; 3650 u8 op_mod[0x10]; 3651 3652 u8 other_vport[0x1]; 3653 u8 reserved_at_41[0xf]; 3654 u8 vport_number[0x10]; 3655 3656 u8 reserved_at_60[0x20]; 3657 3658 u8 table_type[0x8]; 3659 u8 reserved_at_88[0x18]; 3660 3661 u8 reserved_at_a0[0x8]; 3662 u8 table_id[0x18]; 3663 3664 u8 reserved_at_c0[0x18]; 3665 u8 modify_enable_mask[0x8]; 3666 3667 u8 reserved_at_e0[0x20]; 3668 3669 u8 flow_index[0x20]; 3670 3671 u8 reserved_at_120[0xe0]; 3672 3673 struct mlx5_ifc_flow_context_bits flow_context; 3674 }; 3675 3676 struct mlx5_ifc_rts2rts_qp_out_bits { 3677 u8 status[0x8]; 3678 u8 reserved_at_8[0x18]; 3679 3680 u8 syndrome[0x20]; 3681 3682 u8 reserved_at_40[0x40]; 3683 }; 3684 3685 struct mlx5_ifc_rts2rts_qp_in_bits { 3686 u8 opcode[0x10]; 3687 u8 uid[0x10]; 3688 3689 u8 reserved_at_20[0x10]; 3690 u8 op_mod[0x10]; 3691 3692 u8 reserved_at_40[0x8]; 3693 u8 qpn[0x18]; 3694 3695 u8 reserved_at_60[0x20]; 3696 3697 u8 opt_param_mask[0x20]; 3698 3699 u8 reserved_at_a0[0x20]; 3700 3701 struct mlx5_ifc_qpc_bits qpc; 3702 3703 u8 reserved_at_800[0x80]; 3704 }; 3705 3706 struct mlx5_ifc_rtr2rts_qp_out_bits { 3707 u8 status[0x8]; 3708 u8 reserved_at_8[0x18]; 3709 3710 u8 syndrome[0x20]; 3711 3712 u8 reserved_at_40[0x40]; 3713 }; 3714 3715 struct mlx5_ifc_rtr2rts_qp_in_bits { 3716 u8 opcode[0x10]; 3717 u8 uid[0x10]; 3718 3719 u8 reserved_at_20[0x10]; 3720 u8 op_mod[0x10]; 3721 3722 u8 reserved_at_40[0x8]; 3723 u8 qpn[0x18]; 3724 3725 u8 reserved_at_60[0x20]; 3726 3727 u8 opt_param_mask[0x20]; 3728 3729 u8 reserved_at_a0[0x20]; 3730 3731 struct mlx5_ifc_qpc_bits qpc; 3732 3733 u8 reserved_at_800[0x80]; 3734 }; 3735 3736 struct mlx5_ifc_rst2init_qp_out_bits { 3737 u8 status[0x8]; 3738 u8 reserved_at_8[0x18]; 3739 3740 u8 syndrome[0x20]; 3741 3742 u8 reserved_at_40[0x40]; 3743 }; 3744 3745 struct mlx5_ifc_rst2init_qp_in_bits { 3746 u8 opcode[0x10]; 3747 u8 uid[0x10]; 3748 3749 u8 reserved_at_20[0x10]; 3750 u8 op_mod[0x10]; 3751 3752 u8 reserved_at_40[0x8]; 3753 u8 qpn[0x18]; 3754 3755 u8 reserved_at_60[0x20]; 3756 3757 u8 opt_param_mask[0x20]; 3758 3759 u8 reserved_at_a0[0x20]; 3760 3761 struct mlx5_ifc_qpc_bits qpc; 3762 3763 u8 reserved_at_800[0x80]; 3764 }; 3765 3766 struct mlx5_ifc_query_xrq_out_bits { 3767 u8 status[0x8]; 3768 u8 reserved_at_8[0x18]; 3769 3770 u8 syndrome[0x20]; 3771 3772 u8 reserved_at_40[0x40]; 3773 3774 struct mlx5_ifc_xrqc_bits xrq_context; 3775 }; 3776 3777 struct mlx5_ifc_query_xrq_in_bits { 3778 u8 opcode[0x10]; 3779 u8 reserved_at_10[0x10]; 3780 3781 u8 reserved_at_20[0x10]; 3782 u8 op_mod[0x10]; 3783 3784 u8 reserved_at_40[0x8]; 3785 u8 xrqn[0x18]; 3786 3787 u8 reserved_at_60[0x20]; 3788 }; 3789 3790 struct mlx5_ifc_query_xrc_srq_out_bits { 3791 u8 status[0x8]; 3792 u8 reserved_at_8[0x18]; 3793 3794 u8 syndrome[0x20]; 3795 3796 u8 reserved_at_40[0x40]; 3797 3798 struct mlx5_ifc_xrc_srqc_bits xrc_srq_context_entry; 3799 3800 u8 reserved_at_280[0x600]; 3801 3802 u8 pas[0][0x40]; 3803 }; 3804 3805 struct mlx5_ifc_query_xrc_srq_in_bits { 3806 u8 opcode[0x10]; 3807 u8 reserved_at_10[0x10]; 3808 3809 u8 reserved_at_20[0x10]; 3810 u8 op_mod[0x10]; 3811 3812 u8 reserved_at_40[0x8]; 3813 u8 xrc_srqn[0x18]; 3814 3815 u8 reserved_at_60[0x20]; 3816 }; 3817 3818 enum { 3819 MLX5_QUERY_VPORT_STATE_OUT_STATE_DOWN = 0x0, 3820 MLX5_QUERY_VPORT_STATE_OUT_STATE_UP = 0x1, 3821 }; 3822 3823 struct mlx5_ifc_query_vport_state_out_bits { 3824 u8 status[0x8]; 3825 u8 reserved_at_8[0x18]; 3826 3827 u8 syndrome[0x20]; 3828 3829 u8 reserved_at_40[0x20]; 3830 3831 u8 reserved_at_60[0x18]; 3832 u8 admin_state[0x4]; 3833 u8 state[0x4]; 3834 }; 3835 3836 enum { 3837 MLX5_VPORT_STATE_OP_MOD_VNIC_VPORT = 0x0, 3838 MLX5_VPORT_STATE_OP_MOD_ESW_VPORT = 0x1, 3839 }; 3840 3841 struct mlx5_ifc_arm_monitor_counter_in_bits { 3842 u8 opcode[0x10]; 3843 u8 uid[0x10]; 3844 3845 u8 reserved_at_20[0x10]; 3846 u8 op_mod[0x10]; 3847 3848 u8 reserved_at_40[0x20]; 3849 3850 u8 reserved_at_60[0x20]; 3851 }; 3852 3853 struct mlx5_ifc_arm_monitor_counter_out_bits { 3854 u8 status[0x8]; 3855 u8 reserved_at_8[0x18]; 3856 3857 u8 syndrome[0x20]; 3858 3859 u8 reserved_at_40[0x40]; 3860 }; 3861 3862 enum { 3863 MLX5_QUERY_MONITOR_CNT_TYPE_PPCNT = 0x0, 3864 MLX5_QUERY_MONITOR_CNT_TYPE_Q_COUNTER = 0x1, 3865 }; 3866 3867 enum mlx5_monitor_counter_ppcnt { 3868 MLX5_QUERY_MONITOR_PPCNT_IN_RANGE_LENGTH_ERRORS = 0X0, 3869 MLX5_QUERY_MONITOR_PPCNT_OUT_OF_RANGE_LENGTH_FIELD = 0X1, 3870 MLX5_QUERY_MONITOR_PPCNT_FRAME_TOO_LONG_ERRORS = 0X2, 3871 MLX5_QUERY_MONITOR_PPCNT_FRAME_CHECK_SEQUENCE_ERRORS = 0X3, 3872 MLX5_QUERY_MONITOR_PPCNT_ALIGNMENT_ERRORS = 0X4, 3873 MLX5_QUERY_MONITOR_PPCNT_IF_OUT_DISCARDS = 0X5, 3874 }; 3875 3876 enum { 3877 MLX5_QUERY_MONITOR_Q_COUNTER_RX_OUT_OF_BUFFER = 0X4, 3878 }; 3879 3880 struct mlx5_ifc_monitor_counter_output_bits { 3881 u8 reserved_at_0[0x4]; 3882 u8 type[0x4]; 3883 u8 reserved_at_8[0x8]; 3884 u8 counter[0x10]; 3885 3886 u8 counter_group_id[0x20]; 3887 }; 3888 3889 #define MLX5_CMD_SET_MONITOR_NUM_PPCNT_COUNTER_SET1 (6) 3890 #define MLX5_CMD_SET_MONITOR_NUM_Q_COUNTERS_SET1 (1) 3891 #define MLX5_CMD_SET_MONITOR_NUM_COUNTER (MLX5_CMD_SET_MONITOR_NUM_PPCNT_COUNTER_SET1 +\ 3892 MLX5_CMD_SET_MONITOR_NUM_Q_COUNTERS_SET1) 3893 3894 struct mlx5_ifc_set_monitor_counter_in_bits { 3895 u8 opcode[0x10]; 3896 u8 uid[0x10]; 3897 3898 u8 reserved_at_20[0x10]; 3899 u8 op_mod[0x10]; 3900 3901 u8 reserved_at_40[0x10]; 3902 u8 num_of_counters[0x10]; 3903 3904 u8 reserved_at_60[0x20]; 3905 3906 struct mlx5_ifc_monitor_counter_output_bits monitor_counter[MLX5_CMD_SET_MONITOR_NUM_COUNTER]; 3907 }; 3908 3909 struct mlx5_ifc_set_monitor_counter_out_bits { 3910 u8 status[0x8]; 3911 u8 reserved_at_8[0x18]; 3912 3913 u8 syndrome[0x20]; 3914 3915 u8 reserved_at_40[0x40]; 3916 }; 3917 3918 struct mlx5_ifc_query_vport_state_in_bits { 3919 u8 opcode[0x10]; 3920 u8 reserved_at_10[0x10]; 3921 3922 u8 reserved_at_20[0x10]; 3923 u8 op_mod[0x10]; 3924 3925 u8 other_vport[0x1]; 3926 u8 reserved_at_41[0xf]; 3927 u8 vport_number[0x10]; 3928 3929 u8 reserved_at_60[0x20]; 3930 }; 3931 3932 struct mlx5_ifc_query_vnic_env_out_bits { 3933 u8 status[0x8]; 3934 u8 reserved_at_8[0x18]; 3935 3936 u8 syndrome[0x20]; 3937 3938 u8 reserved_at_40[0x40]; 3939 3940 struct mlx5_ifc_vnic_diagnostic_statistics_bits vport_env; 3941 }; 3942 3943 enum { 3944 MLX5_QUERY_VNIC_ENV_IN_OP_MOD_VPORT_DIAG_STATISTICS = 0x0, 3945 }; 3946 3947 struct mlx5_ifc_query_vnic_env_in_bits { 3948 u8 opcode[0x10]; 3949 u8 reserved_at_10[0x10]; 3950 3951 u8 reserved_at_20[0x10]; 3952 u8 op_mod[0x10]; 3953 3954 u8 other_vport[0x1]; 3955 u8 reserved_at_41[0xf]; 3956 u8 vport_number[0x10]; 3957 3958 u8 reserved_at_60[0x20]; 3959 }; 3960 3961 struct mlx5_ifc_query_vport_counter_out_bits { 3962 u8 status[0x8]; 3963 u8 reserved_at_8[0x18]; 3964 3965 u8 syndrome[0x20]; 3966 3967 u8 reserved_at_40[0x40]; 3968 3969 struct mlx5_ifc_traffic_counter_bits received_errors; 3970 3971 struct mlx5_ifc_traffic_counter_bits transmit_errors; 3972 3973 struct mlx5_ifc_traffic_counter_bits received_ib_unicast; 3974 3975 struct mlx5_ifc_traffic_counter_bits transmitted_ib_unicast; 3976 3977 struct mlx5_ifc_traffic_counter_bits received_ib_multicast; 3978 3979 struct mlx5_ifc_traffic_counter_bits transmitted_ib_multicast; 3980 3981 struct mlx5_ifc_traffic_counter_bits received_eth_broadcast; 3982 3983 struct mlx5_ifc_traffic_counter_bits transmitted_eth_broadcast; 3984 3985 struct mlx5_ifc_traffic_counter_bits received_eth_unicast; 3986 3987 struct mlx5_ifc_traffic_counter_bits transmitted_eth_unicast; 3988 3989 struct mlx5_ifc_traffic_counter_bits received_eth_multicast; 3990 3991 struct mlx5_ifc_traffic_counter_bits transmitted_eth_multicast; 3992 3993 u8 reserved_at_680[0xa00]; 3994 }; 3995 3996 enum { 3997 MLX5_QUERY_VPORT_COUNTER_IN_OP_MOD_VPORT_COUNTERS = 0x0, 3998 }; 3999 4000 struct mlx5_ifc_query_vport_counter_in_bits { 4001 u8 opcode[0x10]; 4002 u8 reserved_at_10[0x10]; 4003 4004 u8 reserved_at_20[0x10]; 4005 u8 op_mod[0x10]; 4006 4007 u8 other_vport[0x1]; 4008 u8 reserved_at_41[0xb]; 4009 u8 port_num[0x4]; 4010 u8 vport_number[0x10]; 4011 4012 u8 reserved_at_60[0x60]; 4013 4014 u8 clear[0x1]; 4015 u8 reserved_at_c1[0x1f]; 4016 4017 u8 reserved_at_e0[0x20]; 4018 }; 4019 4020 struct mlx5_ifc_query_tis_out_bits { 4021 u8 status[0x8]; 4022 u8 reserved_at_8[0x18]; 4023 4024 u8 syndrome[0x20]; 4025 4026 u8 reserved_at_40[0x40]; 4027 4028 struct mlx5_ifc_tisc_bits tis_context; 4029 }; 4030 4031 struct mlx5_ifc_query_tis_in_bits { 4032 u8 opcode[0x10]; 4033 u8 reserved_at_10[0x10]; 4034 4035 u8 reserved_at_20[0x10]; 4036 u8 op_mod[0x10]; 4037 4038 u8 reserved_at_40[0x8]; 4039 u8 tisn[0x18]; 4040 4041 u8 reserved_at_60[0x20]; 4042 }; 4043 4044 struct mlx5_ifc_query_tir_out_bits { 4045 u8 status[0x8]; 4046 u8 reserved_at_8[0x18]; 4047 4048 u8 syndrome[0x20]; 4049 4050 u8 reserved_at_40[0xc0]; 4051 4052 struct mlx5_ifc_tirc_bits tir_context; 4053 }; 4054 4055 struct mlx5_ifc_query_tir_in_bits { 4056 u8 opcode[0x10]; 4057 u8 reserved_at_10[0x10]; 4058 4059 u8 reserved_at_20[0x10]; 4060 u8 op_mod[0x10]; 4061 4062 u8 reserved_at_40[0x8]; 4063 u8 tirn[0x18]; 4064 4065 u8 reserved_at_60[0x20]; 4066 }; 4067 4068 struct mlx5_ifc_query_srq_out_bits { 4069 u8 status[0x8]; 4070 u8 reserved_at_8[0x18]; 4071 4072 u8 syndrome[0x20]; 4073 4074 u8 reserved_at_40[0x40]; 4075 4076 struct mlx5_ifc_srqc_bits srq_context_entry; 4077 4078 u8 reserved_at_280[0x600]; 4079 4080 u8 pas[0][0x40]; 4081 }; 4082 4083 struct mlx5_ifc_query_srq_in_bits { 4084 u8 opcode[0x10]; 4085 u8 reserved_at_10[0x10]; 4086 4087 u8 reserved_at_20[0x10]; 4088 u8 op_mod[0x10]; 4089 4090 u8 reserved_at_40[0x8]; 4091 u8 srqn[0x18]; 4092 4093 u8 reserved_at_60[0x20]; 4094 }; 4095 4096 struct mlx5_ifc_query_sq_out_bits { 4097 u8 status[0x8]; 4098 u8 reserved_at_8[0x18]; 4099 4100 u8 syndrome[0x20]; 4101 4102 u8 reserved_at_40[0xc0]; 4103 4104 struct mlx5_ifc_sqc_bits sq_context; 4105 }; 4106 4107 struct mlx5_ifc_query_sq_in_bits { 4108 u8 opcode[0x10]; 4109 u8 reserved_at_10[0x10]; 4110 4111 u8 reserved_at_20[0x10]; 4112 u8 op_mod[0x10]; 4113 4114 u8 reserved_at_40[0x8]; 4115 u8 sqn[0x18]; 4116 4117 u8 reserved_at_60[0x20]; 4118 }; 4119 4120 struct mlx5_ifc_query_special_contexts_out_bits { 4121 u8 status[0x8]; 4122 u8 reserved_at_8[0x18]; 4123 4124 u8 syndrome[0x20]; 4125 4126 u8 dump_fill_mkey[0x20]; 4127 4128 u8 resd_lkey[0x20]; 4129 4130 u8 null_mkey[0x20]; 4131 4132 u8 reserved_at_a0[0x60]; 4133 }; 4134 4135 struct mlx5_ifc_query_special_contexts_in_bits { 4136 u8 opcode[0x10]; 4137 u8 reserved_at_10[0x10]; 4138 4139 u8 reserved_at_20[0x10]; 4140 u8 op_mod[0x10]; 4141 4142 u8 reserved_at_40[0x40]; 4143 }; 4144 4145 struct mlx5_ifc_query_scheduling_element_out_bits { 4146 u8 opcode[0x10]; 4147 u8 reserved_at_10[0x10]; 4148 4149 u8 reserved_at_20[0x10]; 4150 u8 op_mod[0x10]; 4151 4152 u8 reserved_at_40[0xc0]; 4153 4154 struct mlx5_ifc_scheduling_context_bits scheduling_context; 4155 4156 u8 reserved_at_300[0x100]; 4157 }; 4158 4159 enum { 4160 SCHEDULING_HIERARCHY_E_SWITCH = 0x2, 4161 }; 4162 4163 struct mlx5_ifc_query_scheduling_element_in_bits { 4164 u8 opcode[0x10]; 4165 u8 reserved_at_10[0x10]; 4166 4167 u8 reserved_at_20[0x10]; 4168 u8 op_mod[0x10]; 4169 4170 u8 scheduling_hierarchy[0x8]; 4171 u8 reserved_at_48[0x18]; 4172 4173 u8 scheduling_element_id[0x20]; 4174 4175 u8 reserved_at_80[0x180]; 4176 }; 4177 4178 struct mlx5_ifc_query_rqt_out_bits { 4179 u8 status[0x8]; 4180 u8 reserved_at_8[0x18]; 4181 4182 u8 syndrome[0x20]; 4183 4184 u8 reserved_at_40[0xc0]; 4185 4186 struct mlx5_ifc_rqtc_bits rqt_context; 4187 }; 4188 4189 struct mlx5_ifc_query_rqt_in_bits { 4190 u8 opcode[0x10]; 4191 u8 reserved_at_10[0x10]; 4192 4193 u8 reserved_at_20[0x10]; 4194 u8 op_mod[0x10]; 4195 4196 u8 reserved_at_40[0x8]; 4197 u8 rqtn[0x18]; 4198 4199 u8 reserved_at_60[0x20]; 4200 }; 4201 4202 struct mlx5_ifc_query_rq_out_bits { 4203 u8 status[0x8]; 4204 u8 reserved_at_8[0x18]; 4205 4206 u8 syndrome[0x20]; 4207 4208 u8 reserved_at_40[0xc0]; 4209 4210 struct mlx5_ifc_rqc_bits rq_context; 4211 }; 4212 4213 struct mlx5_ifc_query_rq_in_bits { 4214 u8 opcode[0x10]; 4215 u8 reserved_at_10[0x10]; 4216 4217 u8 reserved_at_20[0x10]; 4218 u8 op_mod[0x10]; 4219 4220 u8 reserved_at_40[0x8]; 4221 u8 rqn[0x18]; 4222 4223 u8 reserved_at_60[0x20]; 4224 }; 4225 4226 struct mlx5_ifc_query_roce_address_out_bits { 4227 u8 status[0x8]; 4228 u8 reserved_at_8[0x18]; 4229 4230 u8 syndrome[0x20]; 4231 4232 u8 reserved_at_40[0x40]; 4233 4234 struct mlx5_ifc_roce_addr_layout_bits roce_address; 4235 }; 4236 4237 struct mlx5_ifc_query_roce_address_in_bits { 4238 u8 opcode[0x10]; 4239 u8 reserved_at_10[0x10]; 4240 4241 u8 reserved_at_20[0x10]; 4242 u8 op_mod[0x10]; 4243 4244 u8 roce_address_index[0x10]; 4245 u8 reserved_at_50[0xc]; 4246 u8 vhca_port_num[0x4]; 4247 4248 u8 reserved_at_60[0x20]; 4249 }; 4250 4251 struct mlx5_ifc_query_rmp_out_bits { 4252 u8 status[0x8]; 4253 u8 reserved_at_8[0x18]; 4254 4255 u8 syndrome[0x20]; 4256 4257 u8 reserved_at_40[0xc0]; 4258 4259 struct mlx5_ifc_rmpc_bits rmp_context; 4260 }; 4261 4262 struct mlx5_ifc_query_rmp_in_bits { 4263 u8 opcode[0x10]; 4264 u8 reserved_at_10[0x10]; 4265 4266 u8 reserved_at_20[0x10]; 4267 u8 op_mod[0x10]; 4268 4269 u8 reserved_at_40[0x8]; 4270 u8 rmpn[0x18]; 4271 4272 u8 reserved_at_60[0x20]; 4273 }; 4274 4275 struct mlx5_ifc_query_qp_out_bits { 4276 u8 status[0x8]; 4277 u8 reserved_at_8[0x18]; 4278 4279 u8 syndrome[0x20]; 4280 4281 u8 reserved_at_40[0x40]; 4282 4283 u8 opt_param_mask[0x20]; 4284 4285 u8 reserved_at_a0[0x20]; 4286 4287 struct mlx5_ifc_qpc_bits qpc; 4288 4289 u8 reserved_at_800[0x80]; 4290 4291 u8 pas[0][0x40]; 4292 }; 4293 4294 struct mlx5_ifc_query_qp_in_bits { 4295 u8 opcode[0x10]; 4296 u8 reserved_at_10[0x10]; 4297 4298 u8 reserved_at_20[0x10]; 4299 u8 op_mod[0x10]; 4300 4301 u8 reserved_at_40[0x8]; 4302 u8 qpn[0x18]; 4303 4304 u8 reserved_at_60[0x20]; 4305 }; 4306 4307 struct mlx5_ifc_query_q_counter_out_bits { 4308 u8 status[0x8]; 4309 u8 reserved_at_8[0x18]; 4310 4311 u8 syndrome[0x20]; 4312 4313 u8 reserved_at_40[0x40]; 4314 4315 u8 rx_write_requests[0x20]; 4316 4317 u8 reserved_at_a0[0x20]; 4318 4319 u8 rx_read_requests[0x20]; 4320 4321 u8 reserved_at_e0[0x20]; 4322 4323 u8 rx_atomic_requests[0x20]; 4324 4325 u8 reserved_at_120[0x20]; 4326 4327 u8 rx_dct_connect[0x20]; 4328 4329 u8 reserved_at_160[0x20]; 4330 4331 u8 out_of_buffer[0x20]; 4332 4333 u8 reserved_at_1a0[0x20]; 4334 4335 u8 out_of_sequence[0x20]; 4336 4337 u8 reserved_at_1e0[0x20]; 4338 4339 u8 duplicate_request[0x20]; 4340 4341 u8 reserved_at_220[0x20]; 4342 4343 u8 rnr_nak_retry_err[0x20]; 4344 4345 u8 reserved_at_260[0x20]; 4346 4347 u8 packet_seq_err[0x20]; 4348 4349 u8 reserved_at_2a0[0x20]; 4350 4351 u8 implied_nak_seq_err[0x20]; 4352 4353 u8 reserved_at_2e0[0x20]; 4354 4355 u8 local_ack_timeout_err[0x20]; 4356 4357 u8 reserved_at_320[0xa0]; 4358 4359 u8 resp_local_length_error[0x20]; 4360 4361 u8 req_local_length_error[0x20]; 4362 4363 u8 resp_local_qp_error[0x20]; 4364 4365 u8 local_operation_error[0x20]; 4366 4367 u8 resp_local_protection[0x20]; 4368 4369 u8 req_local_protection[0x20]; 4370 4371 u8 resp_cqe_error[0x20]; 4372 4373 u8 req_cqe_error[0x20]; 4374 4375 u8 req_mw_binding[0x20]; 4376 4377 u8 req_bad_response[0x20]; 4378 4379 u8 req_remote_invalid_request[0x20]; 4380 4381 u8 resp_remote_invalid_request[0x20]; 4382 4383 u8 req_remote_access_errors[0x20]; 4384 4385 u8 resp_remote_access_errors[0x20]; 4386 4387 u8 req_remote_operation_errors[0x20]; 4388 4389 u8 req_transport_retries_exceeded[0x20]; 4390 4391 u8 cq_overflow[0x20]; 4392 4393 u8 resp_cqe_flush_error[0x20]; 4394 4395 u8 req_cqe_flush_error[0x20]; 4396 4397 u8 reserved_at_620[0x1e0]; 4398 }; 4399 4400 struct mlx5_ifc_query_q_counter_in_bits { 4401 u8 opcode[0x10]; 4402 u8 reserved_at_10[0x10]; 4403 4404 u8 reserved_at_20[0x10]; 4405 u8 op_mod[0x10]; 4406 4407 u8 reserved_at_40[0x80]; 4408 4409 u8 clear[0x1]; 4410 u8 reserved_at_c1[0x1f]; 4411 4412 u8 reserved_at_e0[0x18]; 4413 u8 counter_set_id[0x8]; 4414 }; 4415 4416 struct mlx5_ifc_query_pages_out_bits { 4417 u8 status[0x8]; 4418 u8 reserved_at_8[0x18]; 4419 4420 u8 syndrome[0x20]; 4421 4422 u8 reserved_at_40[0x10]; 4423 u8 function_id[0x10]; 4424 4425 u8 num_pages[0x20]; 4426 }; 4427 4428 enum { 4429 MLX5_QUERY_PAGES_IN_OP_MOD_BOOT_PAGES = 0x1, 4430 MLX5_QUERY_PAGES_IN_OP_MOD_INIT_PAGES = 0x2, 4431 MLX5_QUERY_PAGES_IN_OP_MOD_REGULAR_PAGES = 0x3, 4432 }; 4433 4434 struct mlx5_ifc_query_pages_in_bits { 4435 u8 opcode[0x10]; 4436 u8 reserved_at_10[0x10]; 4437 4438 u8 reserved_at_20[0x10]; 4439 u8 op_mod[0x10]; 4440 4441 u8 reserved_at_40[0x10]; 4442 u8 function_id[0x10]; 4443 4444 u8 reserved_at_60[0x20]; 4445 }; 4446 4447 struct mlx5_ifc_query_nic_vport_context_out_bits { 4448 u8 status[0x8]; 4449 u8 reserved_at_8[0x18]; 4450 4451 u8 syndrome[0x20]; 4452 4453 u8 reserved_at_40[0x40]; 4454 4455 struct mlx5_ifc_nic_vport_context_bits nic_vport_context; 4456 }; 4457 4458 struct mlx5_ifc_query_nic_vport_context_in_bits { 4459 u8 opcode[0x10]; 4460 u8 reserved_at_10[0x10]; 4461 4462 u8 reserved_at_20[0x10]; 4463 u8 op_mod[0x10]; 4464 4465 u8 other_vport[0x1]; 4466 u8 reserved_at_41[0xf]; 4467 u8 vport_number[0x10]; 4468 4469 u8 reserved_at_60[0x5]; 4470 u8 allowed_list_type[0x3]; 4471 u8 reserved_at_68[0x18]; 4472 }; 4473 4474 struct mlx5_ifc_query_mkey_out_bits { 4475 u8 status[0x8]; 4476 u8 reserved_at_8[0x18]; 4477 4478 u8 syndrome[0x20]; 4479 4480 u8 reserved_at_40[0x40]; 4481 4482 struct mlx5_ifc_mkc_bits memory_key_mkey_entry; 4483 4484 u8 reserved_at_280[0x600]; 4485 4486 u8 bsf0_klm0_pas_mtt0_1[16][0x8]; 4487 4488 u8 bsf1_klm1_pas_mtt2_3[16][0x8]; 4489 }; 4490 4491 struct mlx5_ifc_query_mkey_in_bits { 4492 u8 opcode[0x10]; 4493 u8 reserved_at_10[0x10]; 4494 4495 u8 reserved_at_20[0x10]; 4496 u8 op_mod[0x10]; 4497 4498 u8 reserved_at_40[0x8]; 4499 u8 mkey_index[0x18]; 4500 4501 u8 pg_access[0x1]; 4502 u8 reserved_at_61[0x1f]; 4503 }; 4504 4505 struct mlx5_ifc_query_mad_demux_out_bits { 4506 u8 status[0x8]; 4507 u8 reserved_at_8[0x18]; 4508 4509 u8 syndrome[0x20]; 4510 4511 u8 reserved_at_40[0x40]; 4512 4513 u8 mad_dumux_parameters_block[0x20]; 4514 }; 4515 4516 struct mlx5_ifc_query_mad_demux_in_bits { 4517 u8 opcode[0x10]; 4518 u8 reserved_at_10[0x10]; 4519 4520 u8 reserved_at_20[0x10]; 4521 u8 op_mod[0x10]; 4522 4523 u8 reserved_at_40[0x40]; 4524 }; 4525 4526 struct mlx5_ifc_query_l2_table_entry_out_bits { 4527 u8 status[0x8]; 4528 u8 reserved_at_8[0x18]; 4529 4530 u8 syndrome[0x20]; 4531 4532 u8 reserved_at_40[0xa0]; 4533 4534 u8 reserved_at_e0[0x13]; 4535 u8 vlan_valid[0x1]; 4536 u8 vlan[0xc]; 4537 4538 struct mlx5_ifc_mac_address_layout_bits mac_address; 4539 4540 u8 reserved_at_140[0xc0]; 4541 }; 4542 4543 struct mlx5_ifc_query_l2_table_entry_in_bits { 4544 u8 opcode[0x10]; 4545 u8 reserved_at_10[0x10]; 4546 4547 u8 reserved_at_20[0x10]; 4548 u8 op_mod[0x10]; 4549 4550 u8 reserved_at_40[0x60]; 4551 4552 u8 reserved_at_a0[0x8]; 4553 u8 table_index[0x18]; 4554 4555 u8 reserved_at_c0[0x140]; 4556 }; 4557 4558 struct mlx5_ifc_query_issi_out_bits { 4559 u8 status[0x8]; 4560 u8 reserved_at_8[0x18]; 4561 4562 u8 syndrome[0x20]; 4563 4564 u8 reserved_at_40[0x10]; 4565 u8 current_issi[0x10]; 4566 4567 u8 reserved_at_60[0xa0]; 4568 4569 u8 reserved_at_100[76][0x8]; 4570 u8 supported_issi_dw0[0x20]; 4571 }; 4572 4573 struct mlx5_ifc_query_issi_in_bits { 4574 u8 opcode[0x10]; 4575 u8 reserved_at_10[0x10]; 4576 4577 u8 reserved_at_20[0x10]; 4578 u8 op_mod[0x10]; 4579 4580 u8 reserved_at_40[0x40]; 4581 }; 4582 4583 struct mlx5_ifc_set_driver_version_out_bits { 4584 u8 status[0x8]; 4585 u8 reserved_0[0x18]; 4586 4587 u8 syndrome[0x20]; 4588 u8 reserved_1[0x40]; 4589 }; 4590 4591 struct mlx5_ifc_set_driver_version_in_bits { 4592 u8 opcode[0x10]; 4593 u8 reserved_0[0x10]; 4594 4595 u8 reserved_1[0x10]; 4596 u8 op_mod[0x10]; 4597 4598 u8 reserved_2[0x40]; 4599 u8 driver_version[64][0x8]; 4600 }; 4601 4602 struct mlx5_ifc_query_hca_vport_pkey_out_bits { 4603 u8 status[0x8]; 4604 u8 reserved_at_8[0x18]; 4605 4606 u8 syndrome[0x20]; 4607 4608 u8 reserved_at_40[0x40]; 4609 4610 struct mlx5_ifc_pkey_bits pkey[0]; 4611 }; 4612 4613 struct mlx5_ifc_query_hca_vport_pkey_in_bits { 4614 u8 opcode[0x10]; 4615 u8 reserved_at_10[0x10]; 4616 4617 u8 reserved_at_20[0x10]; 4618 u8 op_mod[0x10]; 4619 4620 u8 other_vport[0x1]; 4621 u8 reserved_at_41[0xb]; 4622 u8 port_num[0x4]; 4623 u8 vport_number[0x10]; 4624 4625 u8 reserved_at_60[0x10]; 4626 u8 pkey_index[0x10]; 4627 }; 4628 4629 enum { 4630 MLX5_HCA_VPORT_SEL_PORT_GUID = 1 << 0, 4631 MLX5_HCA_VPORT_SEL_NODE_GUID = 1 << 1, 4632 MLX5_HCA_VPORT_SEL_STATE_POLICY = 1 << 2, 4633 }; 4634 4635 struct mlx5_ifc_query_hca_vport_gid_out_bits { 4636 u8 status[0x8]; 4637 u8 reserved_at_8[0x18]; 4638 4639 u8 syndrome[0x20]; 4640 4641 u8 reserved_at_40[0x20]; 4642 4643 u8 gids_num[0x10]; 4644 u8 reserved_at_70[0x10]; 4645 4646 struct mlx5_ifc_array128_auto_bits gid[0]; 4647 }; 4648 4649 struct mlx5_ifc_query_hca_vport_gid_in_bits { 4650 u8 opcode[0x10]; 4651 u8 reserved_at_10[0x10]; 4652 4653 u8 reserved_at_20[0x10]; 4654 u8 op_mod[0x10]; 4655 4656 u8 other_vport[0x1]; 4657 u8 reserved_at_41[0xb]; 4658 u8 port_num[0x4]; 4659 u8 vport_number[0x10]; 4660 4661 u8 reserved_at_60[0x10]; 4662 u8 gid_index[0x10]; 4663 }; 4664 4665 struct mlx5_ifc_query_hca_vport_context_out_bits { 4666 u8 status[0x8]; 4667 u8 reserved_at_8[0x18]; 4668 4669 u8 syndrome[0x20]; 4670 4671 u8 reserved_at_40[0x40]; 4672 4673 struct mlx5_ifc_hca_vport_context_bits hca_vport_context; 4674 }; 4675 4676 struct mlx5_ifc_query_hca_vport_context_in_bits { 4677 u8 opcode[0x10]; 4678 u8 reserved_at_10[0x10]; 4679 4680 u8 reserved_at_20[0x10]; 4681 u8 op_mod[0x10]; 4682 4683 u8 other_vport[0x1]; 4684 u8 reserved_at_41[0xb]; 4685 u8 port_num[0x4]; 4686 u8 vport_number[0x10]; 4687 4688 u8 reserved_at_60[0x20]; 4689 }; 4690 4691 struct mlx5_ifc_query_hca_cap_out_bits { 4692 u8 status[0x8]; 4693 u8 reserved_at_8[0x18]; 4694 4695 u8 syndrome[0x20]; 4696 4697 u8 reserved_at_40[0x40]; 4698 4699 union mlx5_ifc_hca_cap_union_bits capability; 4700 }; 4701 4702 struct mlx5_ifc_query_hca_cap_in_bits { 4703 u8 opcode[0x10]; 4704 u8 reserved_at_10[0x10]; 4705 4706 u8 reserved_at_20[0x10]; 4707 u8 op_mod[0x10]; 4708 4709 u8 reserved_at_40[0x40]; 4710 }; 4711 4712 struct mlx5_ifc_query_flow_table_out_bits { 4713 u8 status[0x8]; 4714 u8 reserved_at_8[0x18]; 4715 4716 u8 syndrome[0x20]; 4717 4718 u8 reserved_at_40[0x80]; 4719 4720 u8 reserved_at_c0[0x8]; 4721 u8 level[0x8]; 4722 u8 reserved_at_d0[0x8]; 4723 u8 log_size[0x8]; 4724 4725 u8 reserved_at_e0[0x120]; 4726 }; 4727 4728 struct mlx5_ifc_query_flow_table_in_bits { 4729 u8 opcode[0x10]; 4730 u8 reserved_at_10[0x10]; 4731 4732 u8 reserved_at_20[0x10]; 4733 u8 op_mod[0x10]; 4734 4735 u8 reserved_at_40[0x40]; 4736 4737 u8 table_type[0x8]; 4738 u8 reserved_at_88[0x18]; 4739 4740 u8 reserved_at_a0[0x8]; 4741 u8 table_id[0x18]; 4742 4743 u8 reserved_at_c0[0x140]; 4744 }; 4745 4746 struct mlx5_ifc_query_fte_out_bits { 4747 u8 status[0x8]; 4748 u8 reserved_at_8[0x18]; 4749 4750 u8 syndrome[0x20]; 4751 4752 u8 reserved_at_40[0x1c0]; 4753 4754 struct mlx5_ifc_flow_context_bits flow_context; 4755 }; 4756 4757 struct mlx5_ifc_query_fte_in_bits { 4758 u8 opcode[0x10]; 4759 u8 reserved_at_10[0x10]; 4760 4761 u8 reserved_at_20[0x10]; 4762 u8 op_mod[0x10]; 4763 4764 u8 reserved_at_40[0x40]; 4765 4766 u8 table_type[0x8]; 4767 u8 reserved_at_88[0x18]; 4768 4769 u8 reserved_at_a0[0x8]; 4770 u8 table_id[0x18]; 4771 4772 u8 reserved_at_c0[0x40]; 4773 4774 u8 flow_index[0x20]; 4775 4776 u8 reserved_at_120[0xe0]; 4777 }; 4778 4779 enum { 4780 MLX5_QUERY_FLOW_GROUP_OUT_MATCH_CRITERIA_ENABLE_OUTER_HEADERS = 0x0, 4781 MLX5_QUERY_FLOW_GROUP_OUT_MATCH_CRITERIA_ENABLE_MISC_PARAMETERS = 0x1, 4782 MLX5_QUERY_FLOW_GROUP_OUT_MATCH_CRITERIA_ENABLE_INNER_HEADERS = 0x2, 4783 MLX5_QUERY_FLOW_GROUP_IN_MATCH_CRITERIA_ENABLE_MISC_PARAMETERS_2 = 0X3, 4784 }; 4785 4786 struct mlx5_ifc_query_flow_group_out_bits { 4787 u8 status[0x8]; 4788 u8 reserved_at_8[0x18]; 4789 4790 u8 syndrome[0x20]; 4791 4792 u8 reserved_at_40[0xa0]; 4793 4794 u8 start_flow_index[0x20]; 4795 4796 u8 reserved_at_100[0x20]; 4797 4798 u8 end_flow_index[0x20]; 4799 4800 u8 reserved_at_140[0xa0]; 4801 4802 u8 reserved_at_1e0[0x18]; 4803 u8 match_criteria_enable[0x8]; 4804 4805 struct mlx5_ifc_fte_match_param_bits match_criteria; 4806 4807 u8 reserved_at_1200[0xe00]; 4808 }; 4809 4810 struct mlx5_ifc_query_flow_group_in_bits { 4811 u8 opcode[0x10]; 4812 u8 reserved_at_10[0x10]; 4813 4814 u8 reserved_at_20[0x10]; 4815 u8 op_mod[0x10]; 4816 4817 u8 reserved_at_40[0x40]; 4818 4819 u8 table_type[0x8]; 4820 u8 reserved_at_88[0x18]; 4821 4822 u8 reserved_at_a0[0x8]; 4823 u8 table_id[0x18]; 4824 4825 u8 group_id[0x20]; 4826 4827 u8 reserved_at_e0[0x120]; 4828 }; 4829 4830 struct mlx5_ifc_query_flow_counter_out_bits { 4831 u8 status[0x8]; 4832 u8 reserved_at_8[0x18]; 4833 4834 u8 syndrome[0x20]; 4835 4836 u8 reserved_at_40[0x40]; 4837 4838 struct mlx5_ifc_traffic_counter_bits flow_statistics[0]; 4839 }; 4840 4841 struct mlx5_ifc_query_flow_counter_in_bits { 4842 u8 opcode[0x10]; 4843 u8 reserved_at_10[0x10]; 4844 4845 u8 reserved_at_20[0x10]; 4846 u8 op_mod[0x10]; 4847 4848 u8 reserved_at_40[0x80]; 4849 4850 u8 clear[0x1]; 4851 u8 reserved_at_c1[0xf]; 4852 u8 num_of_counters[0x10]; 4853 4854 u8 flow_counter_id[0x20]; 4855 }; 4856 4857 struct mlx5_ifc_query_esw_vport_context_out_bits { 4858 u8 status[0x8]; 4859 u8 reserved_at_8[0x18]; 4860 4861 u8 syndrome[0x20]; 4862 4863 u8 reserved_at_40[0x40]; 4864 4865 struct mlx5_ifc_esw_vport_context_bits esw_vport_context; 4866 }; 4867 4868 struct mlx5_ifc_query_esw_vport_context_in_bits { 4869 u8 opcode[0x10]; 4870 u8 reserved_at_10[0x10]; 4871 4872 u8 reserved_at_20[0x10]; 4873 u8 op_mod[0x10]; 4874 4875 u8 other_vport[0x1]; 4876 u8 reserved_at_41[0xf]; 4877 u8 vport_number[0x10]; 4878 4879 u8 reserved_at_60[0x20]; 4880 }; 4881 4882 struct mlx5_ifc_modify_esw_vport_context_out_bits { 4883 u8 status[0x8]; 4884 u8 reserved_at_8[0x18]; 4885 4886 u8 syndrome[0x20]; 4887 4888 u8 reserved_at_40[0x40]; 4889 }; 4890 4891 struct mlx5_ifc_esw_vport_context_fields_select_bits { 4892 u8 reserved_at_0[0x1c]; 4893 u8 vport_cvlan_insert[0x1]; 4894 u8 vport_svlan_insert[0x1]; 4895 u8 vport_cvlan_strip[0x1]; 4896 u8 vport_svlan_strip[0x1]; 4897 }; 4898 4899 struct mlx5_ifc_modify_esw_vport_context_in_bits { 4900 u8 opcode[0x10]; 4901 u8 reserved_at_10[0x10]; 4902 4903 u8 reserved_at_20[0x10]; 4904 u8 op_mod[0x10]; 4905 4906 u8 other_vport[0x1]; 4907 u8 reserved_at_41[0xf]; 4908 u8 vport_number[0x10]; 4909 4910 struct mlx5_ifc_esw_vport_context_fields_select_bits field_select; 4911 4912 struct mlx5_ifc_esw_vport_context_bits esw_vport_context; 4913 }; 4914 4915 struct mlx5_ifc_query_eq_out_bits { 4916 u8 status[0x8]; 4917 u8 reserved_at_8[0x18]; 4918 4919 u8 syndrome[0x20]; 4920 4921 u8 reserved_at_40[0x40]; 4922 4923 struct mlx5_ifc_eqc_bits eq_context_entry; 4924 4925 u8 reserved_at_280[0x40]; 4926 4927 u8 event_bitmask[0x40]; 4928 4929 u8 reserved_at_300[0x580]; 4930 4931 u8 pas[0][0x40]; 4932 }; 4933 4934 struct mlx5_ifc_query_eq_in_bits { 4935 u8 opcode[0x10]; 4936 u8 reserved_at_10[0x10]; 4937 4938 u8 reserved_at_20[0x10]; 4939 u8 op_mod[0x10]; 4940 4941 u8 reserved_at_40[0x18]; 4942 u8 eq_number[0x8]; 4943 4944 u8 reserved_at_60[0x20]; 4945 }; 4946 4947 struct mlx5_ifc_packet_reformat_context_in_bits { 4948 u8 reserved_at_0[0x5]; 4949 u8 reformat_type[0x3]; 4950 u8 reserved_at_8[0xe]; 4951 u8 reformat_data_size[0xa]; 4952 4953 u8 reserved_at_20[0x10]; 4954 u8 reformat_data[2][0x8]; 4955 4956 u8 more_reformat_data[0][0x8]; 4957 }; 4958 4959 struct mlx5_ifc_query_packet_reformat_context_out_bits { 4960 u8 status[0x8]; 4961 u8 reserved_at_8[0x18]; 4962 4963 u8 syndrome[0x20]; 4964 4965 u8 reserved_at_40[0xa0]; 4966 4967 struct mlx5_ifc_packet_reformat_context_in_bits packet_reformat_context[0]; 4968 }; 4969 4970 struct mlx5_ifc_query_packet_reformat_context_in_bits { 4971 u8 opcode[0x10]; 4972 u8 reserved_at_10[0x10]; 4973 4974 u8 reserved_at_20[0x10]; 4975 u8 op_mod[0x10]; 4976 4977 u8 packet_reformat_id[0x20]; 4978 4979 u8 reserved_at_60[0xa0]; 4980 }; 4981 4982 struct mlx5_ifc_alloc_packet_reformat_context_out_bits { 4983 u8 status[0x8]; 4984 u8 reserved_at_8[0x18]; 4985 4986 u8 syndrome[0x20]; 4987 4988 u8 packet_reformat_id[0x20]; 4989 4990 u8 reserved_at_60[0x20]; 4991 }; 4992 4993 enum { 4994 MLX5_REFORMAT_TYPE_L2_TO_VXLAN = 0x0, 4995 MLX5_REFORMAT_TYPE_L2_TO_NVGRE = 0x1, 4996 MLX5_REFORMAT_TYPE_L2_TO_L2_TUNNEL = 0x2, 4997 MLX5_REFORMAT_TYPE_L3_TUNNEL_TO_L2 = 0x3, 4998 MLX5_REFORMAT_TYPE_L2_TO_L3_TUNNEL = 0x4, 4999 }; 5000 5001 struct mlx5_ifc_alloc_packet_reformat_context_in_bits { 5002 u8 opcode[0x10]; 5003 u8 reserved_at_10[0x10]; 5004 5005 u8 reserved_at_20[0x10]; 5006 u8 op_mod[0x10]; 5007 5008 u8 reserved_at_40[0xa0]; 5009 5010 struct mlx5_ifc_packet_reformat_context_in_bits packet_reformat_context; 5011 }; 5012 5013 struct mlx5_ifc_dealloc_packet_reformat_context_out_bits { 5014 u8 status[0x8]; 5015 u8 reserved_at_8[0x18]; 5016 5017 u8 syndrome[0x20]; 5018 5019 u8 reserved_at_40[0x40]; 5020 }; 5021 5022 struct mlx5_ifc_dealloc_packet_reformat_context_in_bits { 5023 u8 opcode[0x10]; 5024 u8 reserved_at_10[0x10]; 5025 5026 u8 reserved_20[0x10]; 5027 u8 op_mod[0x10]; 5028 5029 u8 packet_reformat_id[0x20]; 5030 5031 u8 reserved_60[0x20]; 5032 }; 5033 5034 struct mlx5_ifc_set_action_in_bits { 5035 u8 action_type[0x4]; 5036 u8 field[0xc]; 5037 u8 reserved_at_10[0x3]; 5038 u8 offset[0x5]; 5039 u8 reserved_at_18[0x3]; 5040 u8 length[0x5]; 5041 5042 u8 data[0x20]; 5043 }; 5044 5045 struct mlx5_ifc_add_action_in_bits { 5046 u8 action_type[0x4]; 5047 u8 field[0xc]; 5048 u8 reserved_at_10[0x10]; 5049 5050 u8 data[0x20]; 5051 }; 5052 5053 union mlx5_ifc_set_action_in_add_action_in_auto_bits { 5054 struct mlx5_ifc_set_action_in_bits set_action_in; 5055 struct mlx5_ifc_add_action_in_bits add_action_in; 5056 u8 reserved_at_0[0x40]; 5057 }; 5058 5059 enum { 5060 MLX5_ACTION_TYPE_SET = 0x1, 5061 MLX5_ACTION_TYPE_ADD = 0x2, 5062 }; 5063 5064 enum { 5065 MLX5_ACTION_IN_FIELD_OUT_SMAC_47_16 = 0x1, 5066 MLX5_ACTION_IN_FIELD_OUT_SMAC_15_0 = 0x2, 5067 MLX5_ACTION_IN_FIELD_OUT_ETHERTYPE = 0x3, 5068 MLX5_ACTION_IN_FIELD_OUT_DMAC_47_16 = 0x4, 5069 MLX5_ACTION_IN_FIELD_OUT_DMAC_15_0 = 0x5, 5070 MLX5_ACTION_IN_FIELD_OUT_IP_DSCP = 0x6, 5071 MLX5_ACTION_IN_FIELD_OUT_TCP_FLAGS = 0x7, 5072 MLX5_ACTION_IN_FIELD_OUT_TCP_SPORT = 0x8, 5073 MLX5_ACTION_IN_FIELD_OUT_TCP_DPORT = 0x9, 5074 MLX5_ACTION_IN_FIELD_OUT_IP_TTL = 0xa, 5075 MLX5_ACTION_IN_FIELD_OUT_UDP_SPORT = 0xb, 5076 MLX5_ACTION_IN_FIELD_OUT_UDP_DPORT = 0xc, 5077 MLX5_ACTION_IN_FIELD_OUT_SIPV6_127_96 = 0xd, 5078 MLX5_ACTION_IN_FIELD_OUT_SIPV6_95_64 = 0xe, 5079 MLX5_ACTION_IN_FIELD_OUT_SIPV6_63_32 = 0xf, 5080 MLX5_ACTION_IN_FIELD_OUT_SIPV6_31_0 = 0x10, 5081 MLX5_ACTION_IN_FIELD_OUT_DIPV6_127_96 = 0x11, 5082 MLX5_ACTION_IN_FIELD_OUT_DIPV6_95_64 = 0x12, 5083 MLX5_ACTION_IN_FIELD_OUT_DIPV6_63_32 = 0x13, 5084 MLX5_ACTION_IN_FIELD_OUT_DIPV6_31_0 = 0x14, 5085 MLX5_ACTION_IN_FIELD_OUT_SIPV4 = 0x15, 5086 MLX5_ACTION_IN_FIELD_OUT_DIPV4 = 0x16, 5087 MLX5_ACTION_IN_FIELD_OUT_IPV6_HOPLIMIT = 0x47, 5088 }; 5089 5090 struct mlx5_ifc_alloc_modify_header_context_out_bits { 5091 u8 status[0x8]; 5092 u8 reserved_at_8[0x18]; 5093 5094 u8 syndrome[0x20]; 5095 5096 u8 modify_header_id[0x20]; 5097 5098 u8 reserved_at_60[0x20]; 5099 }; 5100 5101 struct mlx5_ifc_alloc_modify_header_context_in_bits { 5102 u8 opcode[0x10]; 5103 u8 reserved_at_10[0x10]; 5104 5105 u8 reserved_at_20[0x10]; 5106 u8 op_mod[0x10]; 5107 5108 u8 reserved_at_40[0x20]; 5109 5110 u8 table_type[0x8]; 5111 u8 reserved_at_68[0x10]; 5112 u8 num_of_actions[0x8]; 5113 5114 union mlx5_ifc_set_action_in_add_action_in_auto_bits actions[0]; 5115 }; 5116 5117 struct mlx5_ifc_dealloc_modify_header_context_out_bits { 5118 u8 status[0x8]; 5119 u8 reserved_at_8[0x18]; 5120 5121 u8 syndrome[0x20]; 5122 5123 u8 reserved_at_40[0x40]; 5124 }; 5125 5126 struct mlx5_ifc_dealloc_modify_header_context_in_bits { 5127 u8 opcode[0x10]; 5128 u8 reserved_at_10[0x10]; 5129 5130 u8 reserved_at_20[0x10]; 5131 u8 op_mod[0x10]; 5132 5133 u8 modify_header_id[0x20]; 5134 5135 u8 reserved_at_60[0x20]; 5136 }; 5137 5138 struct mlx5_ifc_query_dct_out_bits { 5139 u8 status[0x8]; 5140 u8 reserved_at_8[0x18]; 5141 5142 u8 syndrome[0x20]; 5143 5144 u8 reserved_at_40[0x40]; 5145 5146 struct mlx5_ifc_dctc_bits dct_context_entry; 5147 5148 u8 reserved_at_280[0x180]; 5149 }; 5150 5151 struct mlx5_ifc_query_dct_in_bits { 5152 u8 opcode[0x10]; 5153 u8 reserved_at_10[0x10]; 5154 5155 u8 reserved_at_20[0x10]; 5156 u8 op_mod[0x10]; 5157 5158 u8 reserved_at_40[0x8]; 5159 u8 dctn[0x18]; 5160 5161 u8 reserved_at_60[0x20]; 5162 }; 5163 5164 struct mlx5_ifc_query_cq_out_bits { 5165 u8 status[0x8]; 5166 u8 reserved_at_8[0x18]; 5167 5168 u8 syndrome[0x20]; 5169 5170 u8 reserved_at_40[0x40]; 5171 5172 struct mlx5_ifc_cqc_bits cq_context; 5173 5174 u8 reserved_at_280[0x600]; 5175 5176 u8 pas[0][0x40]; 5177 }; 5178 5179 struct mlx5_ifc_query_cq_in_bits { 5180 u8 opcode[0x10]; 5181 u8 reserved_at_10[0x10]; 5182 5183 u8 reserved_at_20[0x10]; 5184 u8 op_mod[0x10]; 5185 5186 u8 reserved_at_40[0x8]; 5187 u8 cqn[0x18]; 5188 5189 u8 reserved_at_60[0x20]; 5190 }; 5191 5192 struct mlx5_ifc_query_cong_status_out_bits { 5193 u8 status[0x8]; 5194 u8 reserved_at_8[0x18]; 5195 5196 u8 syndrome[0x20]; 5197 5198 u8 reserved_at_40[0x20]; 5199 5200 u8 enable[0x1]; 5201 u8 tag_enable[0x1]; 5202 u8 reserved_at_62[0x1e]; 5203 }; 5204 5205 struct mlx5_ifc_query_cong_status_in_bits { 5206 u8 opcode[0x10]; 5207 u8 reserved_at_10[0x10]; 5208 5209 u8 reserved_at_20[0x10]; 5210 u8 op_mod[0x10]; 5211 5212 u8 reserved_at_40[0x18]; 5213 u8 priority[0x4]; 5214 u8 cong_protocol[0x4]; 5215 5216 u8 reserved_at_60[0x20]; 5217 }; 5218 5219 struct mlx5_ifc_query_cong_statistics_out_bits { 5220 u8 status[0x8]; 5221 u8 reserved_at_8[0x18]; 5222 5223 u8 syndrome[0x20]; 5224 5225 u8 reserved_at_40[0x40]; 5226 5227 u8 rp_cur_flows[0x20]; 5228 5229 u8 sum_flows[0x20]; 5230 5231 u8 rp_cnp_ignored_high[0x20]; 5232 5233 u8 rp_cnp_ignored_low[0x20]; 5234 5235 u8 rp_cnp_handled_high[0x20]; 5236 5237 u8 rp_cnp_handled_low[0x20]; 5238 5239 u8 reserved_at_140[0x100]; 5240 5241 u8 time_stamp_high[0x20]; 5242 5243 u8 time_stamp_low[0x20]; 5244 5245 u8 accumulators_period[0x20]; 5246 5247 u8 np_ecn_marked_roce_packets_high[0x20]; 5248 5249 u8 np_ecn_marked_roce_packets_low[0x20]; 5250 5251 u8 np_cnp_sent_high[0x20]; 5252 5253 u8 np_cnp_sent_low[0x20]; 5254 5255 u8 reserved_at_320[0x560]; 5256 }; 5257 5258 struct mlx5_ifc_query_cong_statistics_in_bits { 5259 u8 opcode[0x10]; 5260 u8 reserved_at_10[0x10]; 5261 5262 u8 reserved_at_20[0x10]; 5263 u8 op_mod[0x10]; 5264 5265 u8 clear[0x1]; 5266 u8 reserved_at_41[0x1f]; 5267 5268 u8 reserved_at_60[0x20]; 5269 }; 5270 5271 struct mlx5_ifc_query_cong_params_out_bits { 5272 u8 status[0x8]; 5273 u8 reserved_at_8[0x18]; 5274 5275 u8 syndrome[0x20]; 5276 5277 u8 reserved_at_40[0x40]; 5278 5279 union mlx5_ifc_cong_control_roce_ecn_auto_bits congestion_parameters; 5280 }; 5281 5282 struct mlx5_ifc_query_cong_params_in_bits { 5283 u8 opcode[0x10]; 5284 u8 reserved_at_10[0x10]; 5285 5286 u8 reserved_at_20[0x10]; 5287 u8 op_mod[0x10]; 5288 5289 u8 reserved_at_40[0x1c]; 5290 u8 cong_protocol[0x4]; 5291 5292 u8 reserved_at_60[0x20]; 5293 }; 5294 5295 struct mlx5_ifc_query_adapter_out_bits { 5296 u8 status[0x8]; 5297 u8 reserved_at_8[0x18]; 5298 5299 u8 syndrome[0x20]; 5300 5301 u8 reserved_at_40[0x40]; 5302 5303 struct mlx5_ifc_query_adapter_param_block_bits query_adapter_struct; 5304 }; 5305 5306 struct mlx5_ifc_query_adapter_in_bits { 5307 u8 opcode[0x10]; 5308 u8 reserved_at_10[0x10]; 5309 5310 u8 reserved_at_20[0x10]; 5311 u8 op_mod[0x10]; 5312 5313 u8 reserved_at_40[0x40]; 5314 }; 5315 5316 struct mlx5_ifc_qp_2rst_out_bits { 5317 u8 status[0x8]; 5318 u8 reserved_at_8[0x18]; 5319 5320 u8 syndrome[0x20]; 5321 5322 u8 reserved_at_40[0x40]; 5323 }; 5324 5325 struct mlx5_ifc_qp_2rst_in_bits { 5326 u8 opcode[0x10]; 5327 u8 uid[0x10]; 5328 5329 u8 reserved_at_20[0x10]; 5330 u8 op_mod[0x10]; 5331 5332 u8 reserved_at_40[0x8]; 5333 u8 qpn[0x18]; 5334 5335 u8 reserved_at_60[0x20]; 5336 }; 5337 5338 struct mlx5_ifc_qp_2err_out_bits { 5339 u8 status[0x8]; 5340 u8 reserved_at_8[0x18]; 5341 5342 u8 syndrome[0x20]; 5343 5344 u8 reserved_at_40[0x40]; 5345 }; 5346 5347 struct mlx5_ifc_qp_2err_in_bits { 5348 u8 opcode[0x10]; 5349 u8 uid[0x10]; 5350 5351 u8 reserved_at_20[0x10]; 5352 u8 op_mod[0x10]; 5353 5354 u8 reserved_at_40[0x8]; 5355 u8 qpn[0x18]; 5356 5357 u8 reserved_at_60[0x20]; 5358 }; 5359 5360 struct mlx5_ifc_page_fault_resume_out_bits { 5361 u8 status[0x8]; 5362 u8 reserved_at_8[0x18]; 5363 5364 u8 syndrome[0x20]; 5365 5366 u8 reserved_at_40[0x40]; 5367 }; 5368 5369 struct mlx5_ifc_page_fault_resume_in_bits { 5370 u8 opcode[0x10]; 5371 u8 reserved_at_10[0x10]; 5372 5373 u8 reserved_at_20[0x10]; 5374 u8 op_mod[0x10]; 5375 5376 u8 error[0x1]; 5377 u8 reserved_at_41[0x4]; 5378 u8 page_fault_type[0x3]; 5379 u8 wq_number[0x18]; 5380 5381 u8 reserved_at_60[0x8]; 5382 u8 token[0x18]; 5383 }; 5384 5385 struct mlx5_ifc_nop_out_bits { 5386 u8 status[0x8]; 5387 u8 reserved_at_8[0x18]; 5388 5389 u8 syndrome[0x20]; 5390 5391 u8 reserved_at_40[0x40]; 5392 }; 5393 5394 struct mlx5_ifc_nop_in_bits { 5395 u8 opcode[0x10]; 5396 u8 reserved_at_10[0x10]; 5397 5398 u8 reserved_at_20[0x10]; 5399 u8 op_mod[0x10]; 5400 5401 u8 reserved_at_40[0x40]; 5402 }; 5403 5404 struct mlx5_ifc_modify_vport_state_out_bits { 5405 u8 status[0x8]; 5406 u8 reserved_at_8[0x18]; 5407 5408 u8 syndrome[0x20]; 5409 5410 u8 reserved_at_40[0x40]; 5411 }; 5412 5413 struct mlx5_ifc_modify_vport_state_in_bits { 5414 u8 opcode[0x10]; 5415 u8 reserved_at_10[0x10]; 5416 5417 u8 reserved_at_20[0x10]; 5418 u8 op_mod[0x10]; 5419 5420 u8 other_vport[0x1]; 5421 u8 reserved_at_41[0xf]; 5422 u8 vport_number[0x10]; 5423 5424 u8 reserved_at_60[0x18]; 5425 u8 admin_state[0x4]; 5426 u8 reserved_at_7c[0x4]; 5427 }; 5428 5429 struct mlx5_ifc_modify_tis_out_bits { 5430 u8 status[0x8]; 5431 u8 reserved_at_8[0x18]; 5432 5433 u8 syndrome[0x20]; 5434 5435 u8 reserved_at_40[0x40]; 5436 }; 5437 5438 struct mlx5_ifc_modify_tis_bitmask_bits { 5439 u8 reserved_at_0[0x20]; 5440 5441 u8 reserved_at_20[0x1d]; 5442 u8 lag_tx_port_affinity[0x1]; 5443 u8 strict_lag_tx_port_affinity[0x1]; 5444 u8 prio[0x1]; 5445 }; 5446 5447 struct mlx5_ifc_modify_tis_in_bits { 5448 u8 opcode[0x10]; 5449 u8 uid[0x10]; 5450 5451 u8 reserved_at_20[0x10]; 5452 u8 op_mod[0x10]; 5453 5454 u8 reserved_at_40[0x8]; 5455 u8 tisn[0x18]; 5456 5457 u8 reserved_at_60[0x20]; 5458 5459 struct mlx5_ifc_modify_tis_bitmask_bits bitmask; 5460 5461 u8 reserved_at_c0[0x40]; 5462 5463 struct mlx5_ifc_tisc_bits ctx; 5464 }; 5465 5466 struct mlx5_ifc_modify_tir_bitmask_bits { 5467 u8 reserved_at_0[0x20]; 5468 5469 u8 reserved_at_20[0x1b]; 5470 u8 self_lb_en[0x1]; 5471 u8 reserved_at_3c[0x1]; 5472 u8 hash[0x1]; 5473 u8 reserved_at_3e[0x1]; 5474 u8 lro[0x1]; 5475 }; 5476 5477 struct mlx5_ifc_modify_tir_out_bits { 5478 u8 status[0x8]; 5479 u8 reserved_at_8[0x18]; 5480 5481 u8 syndrome[0x20]; 5482 5483 u8 reserved_at_40[0x40]; 5484 }; 5485 5486 struct mlx5_ifc_modify_tir_in_bits { 5487 u8 opcode[0x10]; 5488 u8 uid[0x10]; 5489 5490 u8 reserved_at_20[0x10]; 5491 u8 op_mod[0x10]; 5492 5493 u8 reserved_at_40[0x8]; 5494 u8 tirn[0x18]; 5495 5496 u8 reserved_at_60[0x20]; 5497 5498 struct mlx5_ifc_modify_tir_bitmask_bits bitmask; 5499 5500 u8 reserved_at_c0[0x40]; 5501 5502 struct mlx5_ifc_tirc_bits ctx; 5503 }; 5504 5505 struct mlx5_ifc_modify_sq_out_bits { 5506 u8 status[0x8]; 5507 u8 reserved_at_8[0x18]; 5508 5509 u8 syndrome[0x20]; 5510 5511 u8 reserved_at_40[0x40]; 5512 }; 5513 5514 struct mlx5_ifc_modify_sq_in_bits { 5515 u8 opcode[0x10]; 5516 u8 uid[0x10]; 5517 5518 u8 reserved_at_20[0x10]; 5519 u8 op_mod[0x10]; 5520 5521 u8 sq_state[0x4]; 5522 u8 reserved_at_44[0x4]; 5523 u8 sqn[0x18]; 5524 5525 u8 reserved_at_60[0x20]; 5526 5527 u8 modify_bitmask[0x40]; 5528 5529 u8 reserved_at_c0[0x40]; 5530 5531 struct mlx5_ifc_sqc_bits ctx; 5532 }; 5533 5534 struct mlx5_ifc_modify_scheduling_element_out_bits { 5535 u8 status[0x8]; 5536 u8 reserved_at_8[0x18]; 5537 5538 u8 syndrome[0x20]; 5539 5540 u8 reserved_at_40[0x1c0]; 5541 }; 5542 5543 enum { 5544 MODIFY_SCHEDULING_ELEMENT_IN_MODIFY_BITMASK_BW_SHARE = 0x1, 5545 MODIFY_SCHEDULING_ELEMENT_IN_MODIFY_BITMASK_MAX_AVERAGE_BW = 0x2, 5546 }; 5547 5548 struct mlx5_ifc_modify_scheduling_element_in_bits { 5549 u8 opcode[0x10]; 5550 u8 reserved_at_10[0x10]; 5551 5552 u8 reserved_at_20[0x10]; 5553 u8 op_mod[0x10]; 5554 5555 u8 scheduling_hierarchy[0x8]; 5556 u8 reserved_at_48[0x18]; 5557 5558 u8 scheduling_element_id[0x20]; 5559 5560 u8 reserved_at_80[0x20]; 5561 5562 u8 modify_bitmask[0x20]; 5563 5564 u8 reserved_at_c0[0x40]; 5565 5566 struct mlx5_ifc_scheduling_context_bits scheduling_context; 5567 5568 u8 reserved_at_300[0x100]; 5569 }; 5570 5571 struct mlx5_ifc_modify_rqt_out_bits { 5572 u8 status[0x8]; 5573 u8 reserved_at_8[0x18]; 5574 5575 u8 syndrome[0x20]; 5576 5577 u8 reserved_at_40[0x40]; 5578 }; 5579 5580 struct mlx5_ifc_rqt_bitmask_bits { 5581 u8 reserved_at_0[0x20]; 5582 5583 u8 reserved_at_20[0x1f]; 5584 u8 rqn_list[0x1]; 5585 }; 5586 5587 struct mlx5_ifc_modify_rqt_in_bits { 5588 u8 opcode[0x10]; 5589 u8 uid[0x10]; 5590 5591 u8 reserved_at_20[0x10]; 5592 u8 op_mod[0x10]; 5593 5594 u8 reserved_at_40[0x8]; 5595 u8 rqtn[0x18]; 5596 5597 u8 reserved_at_60[0x20]; 5598 5599 struct mlx5_ifc_rqt_bitmask_bits bitmask; 5600 5601 u8 reserved_at_c0[0x40]; 5602 5603 struct mlx5_ifc_rqtc_bits ctx; 5604 }; 5605 5606 struct mlx5_ifc_modify_rq_out_bits { 5607 u8 status[0x8]; 5608 u8 reserved_at_8[0x18]; 5609 5610 u8 syndrome[0x20]; 5611 5612 u8 reserved_at_40[0x40]; 5613 }; 5614 5615 enum { 5616 MLX5_MODIFY_RQ_IN_MODIFY_BITMASK_VSD = 1ULL << 1, 5617 MLX5_MODIFY_RQ_IN_MODIFY_BITMASK_SCATTER_FCS = 1ULL << 2, 5618 MLX5_MODIFY_RQ_IN_MODIFY_BITMASK_RQ_COUNTER_SET_ID = 1ULL << 3, 5619 }; 5620 5621 struct mlx5_ifc_modify_rq_in_bits { 5622 u8 opcode[0x10]; 5623 u8 uid[0x10]; 5624 5625 u8 reserved_at_20[0x10]; 5626 u8 op_mod[0x10]; 5627 5628 u8 rq_state[0x4]; 5629 u8 reserved_at_44[0x4]; 5630 u8 rqn[0x18]; 5631 5632 u8 reserved_at_60[0x20]; 5633 5634 u8 modify_bitmask[0x40]; 5635 5636 u8 reserved_at_c0[0x40]; 5637 5638 struct mlx5_ifc_rqc_bits ctx; 5639 }; 5640 5641 struct mlx5_ifc_modify_rmp_out_bits { 5642 u8 status[0x8]; 5643 u8 reserved_at_8[0x18]; 5644 5645 u8 syndrome[0x20]; 5646 5647 u8 reserved_at_40[0x40]; 5648 }; 5649 5650 struct mlx5_ifc_rmp_bitmask_bits { 5651 u8 reserved_at_0[0x20]; 5652 5653 u8 reserved_at_20[0x1f]; 5654 u8 lwm[0x1]; 5655 }; 5656 5657 struct mlx5_ifc_modify_rmp_in_bits { 5658 u8 opcode[0x10]; 5659 u8 uid[0x10]; 5660 5661 u8 reserved_at_20[0x10]; 5662 u8 op_mod[0x10]; 5663 5664 u8 rmp_state[0x4]; 5665 u8 reserved_at_44[0x4]; 5666 u8 rmpn[0x18]; 5667 5668 u8 reserved_at_60[0x20]; 5669 5670 struct mlx5_ifc_rmp_bitmask_bits bitmask; 5671 5672 u8 reserved_at_c0[0x40]; 5673 5674 struct mlx5_ifc_rmpc_bits ctx; 5675 }; 5676 5677 struct mlx5_ifc_modify_nic_vport_context_out_bits { 5678 u8 status[0x8]; 5679 u8 reserved_at_8[0x18]; 5680 5681 u8 syndrome[0x20]; 5682 5683 u8 reserved_at_40[0x40]; 5684 }; 5685 5686 struct mlx5_ifc_modify_nic_vport_field_select_bits { 5687 u8 reserved_at_0[0x12]; 5688 u8 affiliation[0x1]; 5689 u8 reserved_at_13[0x1]; 5690 u8 disable_uc_local_lb[0x1]; 5691 u8 disable_mc_local_lb[0x1]; 5692 u8 node_guid[0x1]; 5693 u8 port_guid[0x1]; 5694 u8 min_inline[0x1]; 5695 u8 mtu[0x1]; 5696 u8 change_event[0x1]; 5697 u8 promisc[0x1]; 5698 u8 permanent_address[0x1]; 5699 u8 addresses_list[0x1]; 5700 u8 roce_en[0x1]; 5701 u8 reserved_at_1f[0x1]; 5702 }; 5703 5704 struct mlx5_ifc_modify_nic_vport_context_in_bits { 5705 u8 opcode[0x10]; 5706 u8 reserved_at_10[0x10]; 5707 5708 u8 reserved_at_20[0x10]; 5709 u8 op_mod[0x10]; 5710 5711 u8 other_vport[0x1]; 5712 u8 reserved_at_41[0xf]; 5713 u8 vport_number[0x10]; 5714 5715 struct mlx5_ifc_modify_nic_vport_field_select_bits field_select; 5716 5717 u8 reserved_at_80[0x780]; 5718 5719 struct mlx5_ifc_nic_vport_context_bits nic_vport_context; 5720 }; 5721 5722 struct mlx5_ifc_modify_hca_vport_context_out_bits { 5723 u8 status[0x8]; 5724 u8 reserved_at_8[0x18]; 5725 5726 u8 syndrome[0x20]; 5727 5728 u8 reserved_at_40[0x40]; 5729 }; 5730 5731 struct mlx5_ifc_modify_hca_vport_context_in_bits { 5732 u8 opcode[0x10]; 5733 u8 reserved_at_10[0x10]; 5734 5735 u8 reserved_at_20[0x10]; 5736 u8 op_mod[0x10]; 5737 5738 u8 other_vport[0x1]; 5739 u8 reserved_at_41[0xb]; 5740 u8 port_num[0x4]; 5741 u8 vport_number[0x10]; 5742 5743 u8 reserved_at_60[0x20]; 5744 5745 struct mlx5_ifc_hca_vport_context_bits hca_vport_context; 5746 }; 5747 5748 struct mlx5_ifc_modify_cq_out_bits { 5749 u8 status[0x8]; 5750 u8 reserved_at_8[0x18]; 5751 5752 u8 syndrome[0x20]; 5753 5754 u8 reserved_at_40[0x40]; 5755 }; 5756 5757 enum { 5758 MLX5_MODIFY_CQ_IN_OP_MOD_MODIFY_CQ = 0x0, 5759 MLX5_MODIFY_CQ_IN_OP_MOD_RESIZE_CQ = 0x1, 5760 }; 5761 5762 struct mlx5_ifc_modify_cq_in_bits { 5763 u8 opcode[0x10]; 5764 u8 uid[0x10]; 5765 5766 u8 reserved_at_20[0x10]; 5767 u8 op_mod[0x10]; 5768 5769 u8 reserved_at_40[0x8]; 5770 u8 cqn[0x18]; 5771 5772 union mlx5_ifc_modify_field_select_resize_field_select_auto_bits modify_field_select_resize_field_select; 5773 5774 struct mlx5_ifc_cqc_bits cq_context; 5775 5776 u8 reserved_at_280[0x40]; 5777 5778 u8 cq_umem_valid[0x1]; 5779 u8 reserved_at_2c1[0x5bf]; 5780 5781 u8 pas[0][0x40]; 5782 }; 5783 5784 struct mlx5_ifc_modify_cong_status_out_bits { 5785 u8 status[0x8]; 5786 u8 reserved_at_8[0x18]; 5787 5788 u8 syndrome[0x20]; 5789 5790 u8 reserved_at_40[0x40]; 5791 }; 5792 5793 struct mlx5_ifc_modify_cong_status_in_bits { 5794 u8 opcode[0x10]; 5795 u8 reserved_at_10[0x10]; 5796 5797 u8 reserved_at_20[0x10]; 5798 u8 op_mod[0x10]; 5799 5800 u8 reserved_at_40[0x18]; 5801 u8 priority[0x4]; 5802 u8 cong_protocol[0x4]; 5803 5804 u8 enable[0x1]; 5805 u8 tag_enable[0x1]; 5806 u8 reserved_at_62[0x1e]; 5807 }; 5808 5809 struct mlx5_ifc_modify_cong_params_out_bits { 5810 u8 status[0x8]; 5811 u8 reserved_at_8[0x18]; 5812 5813 u8 syndrome[0x20]; 5814 5815 u8 reserved_at_40[0x40]; 5816 }; 5817 5818 struct mlx5_ifc_modify_cong_params_in_bits { 5819 u8 opcode[0x10]; 5820 u8 reserved_at_10[0x10]; 5821 5822 u8 reserved_at_20[0x10]; 5823 u8 op_mod[0x10]; 5824 5825 u8 reserved_at_40[0x1c]; 5826 u8 cong_protocol[0x4]; 5827 5828 union mlx5_ifc_field_select_802_1_r_roce_auto_bits field_select; 5829 5830 u8 reserved_at_80[0x80]; 5831 5832 union mlx5_ifc_cong_control_roce_ecn_auto_bits congestion_parameters; 5833 }; 5834 5835 struct mlx5_ifc_manage_pages_out_bits { 5836 u8 status[0x8]; 5837 u8 reserved_at_8[0x18]; 5838 5839 u8 syndrome[0x20]; 5840 5841 u8 output_num_entries[0x20]; 5842 5843 u8 reserved_at_60[0x20]; 5844 5845 u8 pas[0][0x40]; 5846 }; 5847 5848 enum { 5849 MLX5_MANAGE_PAGES_IN_OP_MOD_ALLOCATION_FAIL = 0x0, 5850 MLX5_MANAGE_PAGES_IN_OP_MOD_ALLOCATION_SUCCESS = 0x1, 5851 MLX5_MANAGE_PAGES_IN_OP_MOD_HCA_RETURN_PAGES = 0x2, 5852 }; 5853 5854 struct mlx5_ifc_manage_pages_in_bits { 5855 u8 opcode[0x10]; 5856 u8 reserved_at_10[0x10]; 5857 5858 u8 reserved_at_20[0x10]; 5859 u8 op_mod[0x10]; 5860 5861 u8 reserved_at_40[0x10]; 5862 u8 function_id[0x10]; 5863 5864 u8 input_num_entries[0x20]; 5865 5866 u8 pas[0][0x40]; 5867 }; 5868 5869 struct mlx5_ifc_mad_ifc_out_bits { 5870 u8 status[0x8]; 5871 u8 reserved_at_8[0x18]; 5872 5873 u8 syndrome[0x20]; 5874 5875 u8 reserved_at_40[0x40]; 5876 5877 u8 response_mad_packet[256][0x8]; 5878 }; 5879 5880 struct mlx5_ifc_mad_ifc_in_bits { 5881 u8 opcode[0x10]; 5882 u8 reserved_at_10[0x10]; 5883 5884 u8 reserved_at_20[0x10]; 5885 u8 op_mod[0x10]; 5886 5887 u8 remote_lid[0x10]; 5888 u8 reserved_at_50[0x8]; 5889 u8 port[0x8]; 5890 5891 u8 reserved_at_60[0x20]; 5892 5893 u8 mad[256][0x8]; 5894 }; 5895 5896 struct mlx5_ifc_init_hca_out_bits { 5897 u8 status[0x8]; 5898 u8 reserved_at_8[0x18]; 5899 5900 u8 syndrome[0x20]; 5901 5902 u8 reserved_at_40[0x40]; 5903 }; 5904 5905 struct mlx5_ifc_init_hca_in_bits { 5906 u8 opcode[0x10]; 5907 u8 reserved_at_10[0x10]; 5908 5909 u8 reserved_at_20[0x10]; 5910 u8 op_mod[0x10]; 5911 5912 u8 reserved_at_40[0x40]; 5913 u8 sw_owner_id[4][0x20]; 5914 }; 5915 5916 struct mlx5_ifc_init2rtr_qp_out_bits { 5917 u8 status[0x8]; 5918 u8 reserved_at_8[0x18]; 5919 5920 u8 syndrome[0x20]; 5921 5922 u8 reserved_at_40[0x40]; 5923 }; 5924 5925 struct mlx5_ifc_init2rtr_qp_in_bits { 5926 u8 opcode[0x10]; 5927 u8 uid[0x10]; 5928 5929 u8 reserved_at_20[0x10]; 5930 u8 op_mod[0x10]; 5931 5932 u8 reserved_at_40[0x8]; 5933 u8 qpn[0x18]; 5934 5935 u8 reserved_at_60[0x20]; 5936 5937 u8 opt_param_mask[0x20]; 5938 5939 u8 reserved_at_a0[0x20]; 5940 5941 struct mlx5_ifc_qpc_bits qpc; 5942 5943 u8 reserved_at_800[0x80]; 5944 }; 5945 5946 struct mlx5_ifc_init2init_qp_out_bits { 5947 u8 status[0x8]; 5948 u8 reserved_at_8[0x18]; 5949 5950 u8 syndrome[0x20]; 5951 5952 u8 reserved_at_40[0x40]; 5953 }; 5954 5955 struct mlx5_ifc_init2init_qp_in_bits { 5956 u8 opcode[0x10]; 5957 u8 uid[0x10]; 5958 5959 u8 reserved_at_20[0x10]; 5960 u8 op_mod[0x10]; 5961 5962 u8 reserved_at_40[0x8]; 5963 u8 qpn[0x18]; 5964 5965 u8 reserved_at_60[0x20]; 5966 5967 u8 opt_param_mask[0x20]; 5968 5969 u8 reserved_at_a0[0x20]; 5970 5971 struct mlx5_ifc_qpc_bits qpc; 5972 5973 u8 reserved_at_800[0x80]; 5974 }; 5975 5976 struct mlx5_ifc_get_dropped_packet_log_out_bits { 5977 u8 status[0x8]; 5978 u8 reserved_at_8[0x18]; 5979 5980 u8 syndrome[0x20]; 5981 5982 u8 reserved_at_40[0x40]; 5983 5984 u8 packet_headers_log[128][0x8]; 5985 5986 u8 packet_syndrome[64][0x8]; 5987 }; 5988 5989 struct mlx5_ifc_get_dropped_packet_log_in_bits { 5990 u8 opcode[0x10]; 5991 u8 reserved_at_10[0x10]; 5992 5993 u8 reserved_at_20[0x10]; 5994 u8 op_mod[0x10]; 5995 5996 u8 reserved_at_40[0x40]; 5997 }; 5998 5999 struct mlx5_ifc_gen_eqe_in_bits { 6000 u8 opcode[0x10]; 6001 u8 reserved_at_10[0x10]; 6002 6003 u8 reserved_at_20[0x10]; 6004 u8 op_mod[0x10]; 6005 6006 u8 reserved_at_40[0x18]; 6007 u8 eq_number[0x8]; 6008 6009 u8 reserved_at_60[0x20]; 6010 6011 u8 eqe[64][0x8]; 6012 }; 6013 6014 struct mlx5_ifc_gen_eq_out_bits { 6015 u8 status[0x8]; 6016 u8 reserved_at_8[0x18]; 6017 6018 u8 syndrome[0x20]; 6019 6020 u8 reserved_at_40[0x40]; 6021 }; 6022 6023 struct mlx5_ifc_enable_hca_out_bits { 6024 u8 status[0x8]; 6025 u8 reserved_at_8[0x18]; 6026 6027 u8 syndrome[0x20]; 6028 6029 u8 reserved_at_40[0x20]; 6030 }; 6031 6032 struct mlx5_ifc_enable_hca_in_bits { 6033 u8 opcode[0x10]; 6034 u8 reserved_at_10[0x10]; 6035 6036 u8 reserved_at_20[0x10]; 6037 u8 op_mod[0x10]; 6038 6039 u8 reserved_at_40[0x10]; 6040 u8 function_id[0x10]; 6041 6042 u8 reserved_at_60[0x20]; 6043 }; 6044 6045 struct mlx5_ifc_drain_dct_out_bits { 6046 u8 status[0x8]; 6047 u8 reserved_at_8[0x18]; 6048 6049 u8 syndrome[0x20]; 6050 6051 u8 reserved_at_40[0x40]; 6052 }; 6053 6054 struct mlx5_ifc_drain_dct_in_bits { 6055 u8 opcode[0x10]; 6056 u8 uid[0x10]; 6057 6058 u8 reserved_at_20[0x10]; 6059 u8 op_mod[0x10]; 6060 6061 u8 reserved_at_40[0x8]; 6062 u8 dctn[0x18]; 6063 6064 u8 reserved_at_60[0x20]; 6065 }; 6066 6067 struct mlx5_ifc_disable_hca_out_bits { 6068 u8 status[0x8]; 6069 u8 reserved_at_8[0x18]; 6070 6071 u8 syndrome[0x20]; 6072 6073 u8 reserved_at_40[0x20]; 6074 }; 6075 6076 struct mlx5_ifc_disable_hca_in_bits { 6077 u8 opcode[0x10]; 6078 u8 reserved_at_10[0x10]; 6079 6080 u8 reserved_at_20[0x10]; 6081 u8 op_mod[0x10]; 6082 6083 u8 reserved_at_40[0x10]; 6084 u8 function_id[0x10]; 6085 6086 u8 reserved_at_60[0x20]; 6087 }; 6088 6089 struct mlx5_ifc_detach_from_mcg_out_bits { 6090 u8 status[0x8]; 6091 u8 reserved_at_8[0x18]; 6092 6093 u8 syndrome[0x20]; 6094 6095 u8 reserved_at_40[0x40]; 6096 }; 6097 6098 struct mlx5_ifc_detach_from_mcg_in_bits { 6099 u8 opcode[0x10]; 6100 u8 uid[0x10]; 6101 6102 u8 reserved_at_20[0x10]; 6103 u8 op_mod[0x10]; 6104 6105 u8 reserved_at_40[0x8]; 6106 u8 qpn[0x18]; 6107 6108 u8 reserved_at_60[0x20]; 6109 6110 u8 multicast_gid[16][0x8]; 6111 }; 6112 6113 struct mlx5_ifc_destroy_xrq_out_bits { 6114 u8 status[0x8]; 6115 u8 reserved_at_8[0x18]; 6116 6117 u8 syndrome[0x20]; 6118 6119 u8 reserved_at_40[0x40]; 6120 }; 6121 6122 struct mlx5_ifc_destroy_xrq_in_bits { 6123 u8 opcode[0x10]; 6124 u8 uid[0x10]; 6125 6126 u8 reserved_at_20[0x10]; 6127 u8 op_mod[0x10]; 6128 6129 u8 reserved_at_40[0x8]; 6130 u8 xrqn[0x18]; 6131 6132 u8 reserved_at_60[0x20]; 6133 }; 6134 6135 struct mlx5_ifc_destroy_xrc_srq_out_bits { 6136 u8 status[0x8]; 6137 u8 reserved_at_8[0x18]; 6138 6139 u8 syndrome[0x20]; 6140 6141 u8 reserved_at_40[0x40]; 6142 }; 6143 6144 struct mlx5_ifc_destroy_xrc_srq_in_bits { 6145 u8 opcode[0x10]; 6146 u8 uid[0x10]; 6147 6148 u8 reserved_at_20[0x10]; 6149 u8 op_mod[0x10]; 6150 6151 u8 reserved_at_40[0x8]; 6152 u8 xrc_srqn[0x18]; 6153 6154 u8 reserved_at_60[0x20]; 6155 }; 6156 6157 struct mlx5_ifc_destroy_tis_out_bits { 6158 u8 status[0x8]; 6159 u8 reserved_at_8[0x18]; 6160 6161 u8 syndrome[0x20]; 6162 6163 u8 reserved_at_40[0x40]; 6164 }; 6165 6166 struct mlx5_ifc_destroy_tis_in_bits { 6167 u8 opcode[0x10]; 6168 u8 uid[0x10]; 6169 6170 u8 reserved_at_20[0x10]; 6171 u8 op_mod[0x10]; 6172 6173 u8 reserved_at_40[0x8]; 6174 u8 tisn[0x18]; 6175 6176 u8 reserved_at_60[0x20]; 6177 }; 6178 6179 struct mlx5_ifc_destroy_tir_out_bits { 6180 u8 status[0x8]; 6181 u8 reserved_at_8[0x18]; 6182 6183 u8 syndrome[0x20]; 6184 6185 u8 reserved_at_40[0x40]; 6186 }; 6187 6188 struct mlx5_ifc_destroy_tir_in_bits { 6189 u8 opcode[0x10]; 6190 u8 uid[0x10]; 6191 6192 u8 reserved_at_20[0x10]; 6193 u8 op_mod[0x10]; 6194 6195 u8 reserved_at_40[0x8]; 6196 u8 tirn[0x18]; 6197 6198 u8 reserved_at_60[0x20]; 6199 }; 6200 6201 struct mlx5_ifc_destroy_srq_out_bits { 6202 u8 status[0x8]; 6203 u8 reserved_at_8[0x18]; 6204 6205 u8 syndrome[0x20]; 6206 6207 u8 reserved_at_40[0x40]; 6208 }; 6209 6210 struct mlx5_ifc_destroy_srq_in_bits { 6211 u8 opcode[0x10]; 6212 u8 uid[0x10]; 6213 6214 u8 reserved_at_20[0x10]; 6215 u8 op_mod[0x10]; 6216 6217 u8 reserved_at_40[0x8]; 6218 u8 srqn[0x18]; 6219 6220 u8 reserved_at_60[0x20]; 6221 }; 6222 6223 struct mlx5_ifc_destroy_sq_out_bits { 6224 u8 status[0x8]; 6225 u8 reserved_at_8[0x18]; 6226 6227 u8 syndrome[0x20]; 6228 6229 u8 reserved_at_40[0x40]; 6230 }; 6231 6232 struct mlx5_ifc_destroy_sq_in_bits { 6233 u8 opcode[0x10]; 6234 u8 uid[0x10]; 6235 6236 u8 reserved_at_20[0x10]; 6237 u8 op_mod[0x10]; 6238 6239 u8 reserved_at_40[0x8]; 6240 u8 sqn[0x18]; 6241 6242 u8 reserved_at_60[0x20]; 6243 }; 6244 6245 struct mlx5_ifc_destroy_scheduling_element_out_bits { 6246 u8 status[0x8]; 6247 u8 reserved_at_8[0x18]; 6248 6249 u8 syndrome[0x20]; 6250 6251 u8 reserved_at_40[0x1c0]; 6252 }; 6253 6254 struct mlx5_ifc_destroy_scheduling_element_in_bits { 6255 u8 opcode[0x10]; 6256 u8 reserved_at_10[0x10]; 6257 6258 u8 reserved_at_20[0x10]; 6259 u8 op_mod[0x10]; 6260 6261 u8 scheduling_hierarchy[0x8]; 6262 u8 reserved_at_48[0x18]; 6263 6264 u8 scheduling_element_id[0x20]; 6265 6266 u8 reserved_at_80[0x180]; 6267 }; 6268 6269 struct mlx5_ifc_destroy_rqt_out_bits { 6270 u8 status[0x8]; 6271 u8 reserved_at_8[0x18]; 6272 6273 u8 syndrome[0x20]; 6274 6275 u8 reserved_at_40[0x40]; 6276 }; 6277 6278 struct mlx5_ifc_destroy_rqt_in_bits { 6279 u8 opcode[0x10]; 6280 u8 uid[0x10]; 6281 6282 u8 reserved_at_20[0x10]; 6283 u8 op_mod[0x10]; 6284 6285 u8 reserved_at_40[0x8]; 6286 u8 rqtn[0x18]; 6287 6288 u8 reserved_at_60[0x20]; 6289 }; 6290 6291 struct mlx5_ifc_destroy_rq_out_bits { 6292 u8 status[0x8]; 6293 u8 reserved_at_8[0x18]; 6294 6295 u8 syndrome[0x20]; 6296 6297 u8 reserved_at_40[0x40]; 6298 }; 6299 6300 struct mlx5_ifc_destroy_rq_in_bits { 6301 u8 opcode[0x10]; 6302 u8 uid[0x10]; 6303 6304 u8 reserved_at_20[0x10]; 6305 u8 op_mod[0x10]; 6306 6307 u8 reserved_at_40[0x8]; 6308 u8 rqn[0x18]; 6309 6310 u8 reserved_at_60[0x20]; 6311 }; 6312 6313 struct mlx5_ifc_set_delay_drop_params_in_bits { 6314 u8 opcode[0x10]; 6315 u8 reserved_at_10[0x10]; 6316 6317 u8 reserved_at_20[0x10]; 6318 u8 op_mod[0x10]; 6319 6320 u8 reserved_at_40[0x20]; 6321 6322 u8 reserved_at_60[0x10]; 6323 u8 delay_drop_timeout[0x10]; 6324 }; 6325 6326 struct mlx5_ifc_set_delay_drop_params_out_bits { 6327 u8 status[0x8]; 6328 u8 reserved_at_8[0x18]; 6329 6330 u8 syndrome[0x20]; 6331 6332 u8 reserved_at_40[0x40]; 6333 }; 6334 6335 struct mlx5_ifc_destroy_rmp_out_bits { 6336 u8 status[0x8]; 6337 u8 reserved_at_8[0x18]; 6338 6339 u8 syndrome[0x20]; 6340 6341 u8 reserved_at_40[0x40]; 6342 }; 6343 6344 struct mlx5_ifc_destroy_rmp_in_bits { 6345 u8 opcode[0x10]; 6346 u8 uid[0x10]; 6347 6348 u8 reserved_at_20[0x10]; 6349 u8 op_mod[0x10]; 6350 6351 u8 reserved_at_40[0x8]; 6352 u8 rmpn[0x18]; 6353 6354 u8 reserved_at_60[0x20]; 6355 }; 6356 6357 struct mlx5_ifc_destroy_qp_out_bits { 6358 u8 status[0x8]; 6359 u8 reserved_at_8[0x18]; 6360 6361 u8 syndrome[0x20]; 6362 6363 u8 reserved_at_40[0x40]; 6364 }; 6365 6366 struct mlx5_ifc_destroy_qp_in_bits { 6367 u8 opcode[0x10]; 6368 u8 uid[0x10]; 6369 6370 u8 reserved_at_20[0x10]; 6371 u8 op_mod[0x10]; 6372 6373 u8 reserved_at_40[0x8]; 6374 u8 qpn[0x18]; 6375 6376 u8 reserved_at_60[0x20]; 6377 }; 6378 6379 struct mlx5_ifc_destroy_psv_out_bits { 6380 u8 status[0x8]; 6381 u8 reserved_at_8[0x18]; 6382 6383 u8 syndrome[0x20]; 6384 6385 u8 reserved_at_40[0x40]; 6386 }; 6387 6388 struct mlx5_ifc_destroy_psv_in_bits { 6389 u8 opcode[0x10]; 6390 u8 reserved_at_10[0x10]; 6391 6392 u8 reserved_at_20[0x10]; 6393 u8 op_mod[0x10]; 6394 6395 u8 reserved_at_40[0x8]; 6396 u8 psvn[0x18]; 6397 6398 u8 reserved_at_60[0x20]; 6399 }; 6400 6401 struct mlx5_ifc_destroy_mkey_out_bits { 6402 u8 status[0x8]; 6403 u8 reserved_at_8[0x18]; 6404 6405 u8 syndrome[0x20]; 6406 6407 u8 reserved_at_40[0x40]; 6408 }; 6409 6410 struct mlx5_ifc_destroy_mkey_in_bits { 6411 u8 opcode[0x10]; 6412 u8 reserved_at_10[0x10]; 6413 6414 u8 reserved_at_20[0x10]; 6415 u8 op_mod[0x10]; 6416 6417 u8 reserved_at_40[0x8]; 6418 u8 mkey_index[0x18]; 6419 6420 u8 reserved_at_60[0x20]; 6421 }; 6422 6423 struct mlx5_ifc_destroy_flow_table_out_bits { 6424 u8 status[0x8]; 6425 u8 reserved_at_8[0x18]; 6426 6427 u8 syndrome[0x20]; 6428 6429 u8 reserved_at_40[0x40]; 6430 }; 6431 6432 struct mlx5_ifc_destroy_flow_table_in_bits { 6433 u8 opcode[0x10]; 6434 u8 reserved_at_10[0x10]; 6435 6436 u8 reserved_at_20[0x10]; 6437 u8 op_mod[0x10]; 6438 6439 u8 other_vport[0x1]; 6440 u8 reserved_at_41[0xf]; 6441 u8 vport_number[0x10]; 6442 6443 u8 reserved_at_60[0x20]; 6444 6445 u8 table_type[0x8]; 6446 u8 reserved_at_88[0x18]; 6447 6448 u8 reserved_at_a0[0x8]; 6449 u8 table_id[0x18]; 6450 6451 u8 reserved_at_c0[0x140]; 6452 }; 6453 6454 struct mlx5_ifc_destroy_flow_group_out_bits { 6455 u8 status[0x8]; 6456 u8 reserved_at_8[0x18]; 6457 6458 u8 syndrome[0x20]; 6459 6460 u8 reserved_at_40[0x40]; 6461 }; 6462 6463 struct mlx5_ifc_destroy_flow_group_in_bits { 6464 u8 opcode[0x10]; 6465 u8 reserved_at_10[0x10]; 6466 6467 u8 reserved_at_20[0x10]; 6468 u8 op_mod[0x10]; 6469 6470 u8 other_vport[0x1]; 6471 u8 reserved_at_41[0xf]; 6472 u8 vport_number[0x10]; 6473 6474 u8 reserved_at_60[0x20]; 6475 6476 u8 table_type[0x8]; 6477 u8 reserved_at_88[0x18]; 6478 6479 u8 reserved_at_a0[0x8]; 6480 u8 table_id[0x18]; 6481 6482 u8 group_id[0x20]; 6483 6484 u8 reserved_at_e0[0x120]; 6485 }; 6486 6487 struct mlx5_ifc_destroy_eq_out_bits { 6488 u8 status[0x8]; 6489 u8 reserved_at_8[0x18]; 6490 6491 u8 syndrome[0x20]; 6492 6493 u8 reserved_at_40[0x40]; 6494 }; 6495 6496 struct mlx5_ifc_destroy_eq_in_bits { 6497 u8 opcode[0x10]; 6498 u8 reserved_at_10[0x10]; 6499 6500 u8 reserved_at_20[0x10]; 6501 u8 op_mod[0x10]; 6502 6503 u8 reserved_at_40[0x18]; 6504 u8 eq_number[0x8]; 6505 6506 u8 reserved_at_60[0x20]; 6507 }; 6508 6509 struct mlx5_ifc_destroy_dct_out_bits { 6510 u8 status[0x8]; 6511 u8 reserved_at_8[0x18]; 6512 6513 u8 syndrome[0x20]; 6514 6515 u8 reserved_at_40[0x40]; 6516 }; 6517 6518 struct mlx5_ifc_destroy_dct_in_bits { 6519 u8 opcode[0x10]; 6520 u8 uid[0x10]; 6521 6522 u8 reserved_at_20[0x10]; 6523 u8 op_mod[0x10]; 6524 6525 u8 reserved_at_40[0x8]; 6526 u8 dctn[0x18]; 6527 6528 u8 reserved_at_60[0x20]; 6529 }; 6530 6531 struct mlx5_ifc_destroy_cq_out_bits { 6532 u8 status[0x8]; 6533 u8 reserved_at_8[0x18]; 6534 6535 u8 syndrome[0x20]; 6536 6537 u8 reserved_at_40[0x40]; 6538 }; 6539 6540 struct mlx5_ifc_destroy_cq_in_bits { 6541 u8 opcode[0x10]; 6542 u8 uid[0x10]; 6543 6544 u8 reserved_at_20[0x10]; 6545 u8 op_mod[0x10]; 6546 6547 u8 reserved_at_40[0x8]; 6548 u8 cqn[0x18]; 6549 6550 u8 reserved_at_60[0x20]; 6551 }; 6552 6553 struct mlx5_ifc_delete_vxlan_udp_dport_out_bits { 6554 u8 status[0x8]; 6555 u8 reserved_at_8[0x18]; 6556 6557 u8 syndrome[0x20]; 6558 6559 u8 reserved_at_40[0x40]; 6560 }; 6561 6562 struct mlx5_ifc_delete_vxlan_udp_dport_in_bits { 6563 u8 opcode[0x10]; 6564 u8 reserved_at_10[0x10]; 6565 6566 u8 reserved_at_20[0x10]; 6567 u8 op_mod[0x10]; 6568 6569 u8 reserved_at_40[0x20]; 6570 6571 u8 reserved_at_60[0x10]; 6572 u8 vxlan_udp_port[0x10]; 6573 }; 6574 6575 struct mlx5_ifc_delete_l2_table_entry_out_bits { 6576 u8 status[0x8]; 6577 u8 reserved_at_8[0x18]; 6578 6579 u8 syndrome[0x20]; 6580 6581 u8 reserved_at_40[0x40]; 6582 }; 6583 6584 struct mlx5_ifc_delete_l2_table_entry_in_bits { 6585 u8 opcode[0x10]; 6586 u8 reserved_at_10[0x10]; 6587 6588 u8 reserved_at_20[0x10]; 6589 u8 op_mod[0x10]; 6590 6591 u8 reserved_at_40[0x60]; 6592 6593 u8 reserved_at_a0[0x8]; 6594 u8 table_index[0x18]; 6595 6596 u8 reserved_at_c0[0x140]; 6597 }; 6598 6599 struct mlx5_ifc_delete_fte_out_bits { 6600 u8 status[0x8]; 6601 u8 reserved_at_8[0x18]; 6602 6603 u8 syndrome[0x20]; 6604 6605 u8 reserved_at_40[0x40]; 6606 }; 6607 6608 struct mlx5_ifc_delete_fte_in_bits { 6609 u8 opcode[0x10]; 6610 u8 reserved_at_10[0x10]; 6611 6612 u8 reserved_at_20[0x10]; 6613 u8 op_mod[0x10]; 6614 6615 u8 other_vport[0x1]; 6616 u8 reserved_at_41[0xf]; 6617 u8 vport_number[0x10]; 6618 6619 u8 reserved_at_60[0x20]; 6620 6621 u8 table_type[0x8]; 6622 u8 reserved_at_88[0x18]; 6623 6624 u8 reserved_at_a0[0x8]; 6625 u8 table_id[0x18]; 6626 6627 u8 reserved_at_c0[0x40]; 6628 6629 u8 flow_index[0x20]; 6630 6631 u8 reserved_at_120[0xe0]; 6632 }; 6633 6634 struct mlx5_ifc_dealloc_xrcd_out_bits { 6635 u8 status[0x8]; 6636 u8 reserved_at_8[0x18]; 6637 6638 u8 syndrome[0x20]; 6639 6640 u8 reserved_at_40[0x40]; 6641 }; 6642 6643 struct mlx5_ifc_dealloc_xrcd_in_bits { 6644 u8 opcode[0x10]; 6645 u8 uid[0x10]; 6646 6647 u8 reserved_at_20[0x10]; 6648 u8 op_mod[0x10]; 6649 6650 u8 reserved_at_40[0x8]; 6651 u8 xrcd[0x18]; 6652 6653 u8 reserved_at_60[0x20]; 6654 }; 6655 6656 struct mlx5_ifc_dealloc_uar_out_bits { 6657 u8 status[0x8]; 6658 u8 reserved_at_8[0x18]; 6659 6660 u8 syndrome[0x20]; 6661 6662 u8 reserved_at_40[0x40]; 6663 }; 6664 6665 struct mlx5_ifc_dealloc_uar_in_bits { 6666 u8 opcode[0x10]; 6667 u8 reserved_at_10[0x10]; 6668 6669 u8 reserved_at_20[0x10]; 6670 u8 op_mod[0x10]; 6671 6672 u8 reserved_at_40[0x8]; 6673 u8 uar[0x18]; 6674 6675 u8 reserved_at_60[0x20]; 6676 }; 6677 6678 struct mlx5_ifc_dealloc_transport_domain_out_bits { 6679 u8 status[0x8]; 6680 u8 reserved_at_8[0x18]; 6681 6682 u8 syndrome[0x20]; 6683 6684 u8 reserved_at_40[0x40]; 6685 }; 6686 6687 struct mlx5_ifc_dealloc_transport_domain_in_bits { 6688 u8 opcode[0x10]; 6689 u8 reserved_at_10[0x10]; 6690 6691 u8 reserved_at_20[0x10]; 6692 u8 op_mod[0x10]; 6693 6694 u8 reserved_at_40[0x8]; 6695 u8 transport_domain[0x18]; 6696 6697 u8 reserved_at_60[0x20]; 6698 }; 6699 6700 struct mlx5_ifc_dealloc_q_counter_out_bits { 6701 u8 status[0x8]; 6702 u8 reserved_at_8[0x18]; 6703 6704 u8 syndrome[0x20]; 6705 6706 u8 reserved_at_40[0x40]; 6707 }; 6708 6709 struct mlx5_ifc_dealloc_q_counter_in_bits { 6710 u8 opcode[0x10]; 6711 u8 reserved_at_10[0x10]; 6712 6713 u8 reserved_at_20[0x10]; 6714 u8 op_mod[0x10]; 6715 6716 u8 reserved_at_40[0x18]; 6717 u8 counter_set_id[0x8]; 6718 6719 u8 reserved_at_60[0x20]; 6720 }; 6721 6722 struct mlx5_ifc_dealloc_pd_out_bits { 6723 u8 status[0x8]; 6724 u8 reserved_at_8[0x18]; 6725 6726 u8 syndrome[0x20]; 6727 6728 u8 reserved_at_40[0x40]; 6729 }; 6730 6731 struct mlx5_ifc_dealloc_pd_in_bits { 6732 u8 opcode[0x10]; 6733 u8 uid[0x10]; 6734 6735 u8 reserved_at_20[0x10]; 6736 u8 op_mod[0x10]; 6737 6738 u8 reserved_at_40[0x8]; 6739 u8 pd[0x18]; 6740 6741 u8 reserved_at_60[0x20]; 6742 }; 6743 6744 struct mlx5_ifc_dealloc_flow_counter_out_bits { 6745 u8 status[0x8]; 6746 u8 reserved_at_8[0x18]; 6747 6748 u8 syndrome[0x20]; 6749 6750 u8 reserved_at_40[0x40]; 6751 }; 6752 6753 struct mlx5_ifc_dealloc_flow_counter_in_bits { 6754 u8 opcode[0x10]; 6755 u8 reserved_at_10[0x10]; 6756 6757 u8 reserved_at_20[0x10]; 6758 u8 op_mod[0x10]; 6759 6760 u8 flow_counter_id[0x20]; 6761 6762 u8 reserved_at_60[0x20]; 6763 }; 6764 6765 struct mlx5_ifc_create_xrq_out_bits { 6766 u8 status[0x8]; 6767 u8 reserved_at_8[0x18]; 6768 6769 u8 syndrome[0x20]; 6770 6771 u8 reserved_at_40[0x8]; 6772 u8 xrqn[0x18]; 6773 6774 u8 reserved_at_60[0x20]; 6775 }; 6776 6777 struct mlx5_ifc_create_xrq_in_bits { 6778 u8 opcode[0x10]; 6779 u8 uid[0x10]; 6780 6781 u8 reserved_at_20[0x10]; 6782 u8 op_mod[0x10]; 6783 6784 u8 reserved_at_40[0x40]; 6785 6786 struct mlx5_ifc_xrqc_bits xrq_context; 6787 }; 6788 6789 struct mlx5_ifc_create_xrc_srq_out_bits { 6790 u8 status[0x8]; 6791 u8 reserved_at_8[0x18]; 6792 6793 u8 syndrome[0x20]; 6794 6795 u8 reserved_at_40[0x8]; 6796 u8 xrc_srqn[0x18]; 6797 6798 u8 reserved_at_60[0x20]; 6799 }; 6800 6801 struct mlx5_ifc_create_xrc_srq_in_bits { 6802 u8 opcode[0x10]; 6803 u8 uid[0x10]; 6804 6805 u8 reserved_at_20[0x10]; 6806 u8 op_mod[0x10]; 6807 6808 u8 reserved_at_40[0x40]; 6809 6810 struct mlx5_ifc_xrc_srqc_bits xrc_srq_context_entry; 6811 6812 u8 reserved_at_280[0x60]; 6813 6814 u8 xrc_srq_umem_valid[0x1]; 6815 u8 reserved_at_2e1[0x1f]; 6816 6817 u8 reserved_at_300[0x580]; 6818 6819 u8 pas[0][0x40]; 6820 }; 6821 6822 struct mlx5_ifc_create_tis_out_bits { 6823 u8 status[0x8]; 6824 u8 reserved_at_8[0x18]; 6825 6826 u8 syndrome[0x20]; 6827 6828 u8 reserved_at_40[0x8]; 6829 u8 tisn[0x18]; 6830 6831 u8 reserved_at_60[0x20]; 6832 }; 6833 6834 struct mlx5_ifc_create_tis_in_bits { 6835 u8 opcode[0x10]; 6836 u8 uid[0x10]; 6837 6838 u8 reserved_at_20[0x10]; 6839 u8 op_mod[0x10]; 6840 6841 u8 reserved_at_40[0xc0]; 6842 6843 struct mlx5_ifc_tisc_bits ctx; 6844 }; 6845 6846 struct mlx5_ifc_create_tir_out_bits { 6847 u8 status[0x8]; 6848 u8 reserved_at_8[0x18]; 6849 6850 u8 syndrome[0x20]; 6851 6852 u8 reserved_at_40[0x8]; 6853 u8 tirn[0x18]; 6854 6855 u8 reserved_at_60[0x20]; 6856 }; 6857 6858 struct mlx5_ifc_create_tir_in_bits { 6859 u8 opcode[0x10]; 6860 u8 uid[0x10]; 6861 6862 u8 reserved_at_20[0x10]; 6863 u8 op_mod[0x10]; 6864 6865 u8 reserved_at_40[0xc0]; 6866 6867 struct mlx5_ifc_tirc_bits ctx; 6868 }; 6869 6870 struct mlx5_ifc_create_srq_out_bits { 6871 u8 status[0x8]; 6872 u8 reserved_at_8[0x18]; 6873 6874 u8 syndrome[0x20]; 6875 6876 u8 reserved_at_40[0x8]; 6877 u8 srqn[0x18]; 6878 6879 u8 reserved_at_60[0x20]; 6880 }; 6881 6882 struct mlx5_ifc_create_srq_in_bits { 6883 u8 opcode[0x10]; 6884 u8 uid[0x10]; 6885 6886 u8 reserved_at_20[0x10]; 6887 u8 op_mod[0x10]; 6888 6889 u8 reserved_at_40[0x40]; 6890 6891 struct mlx5_ifc_srqc_bits srq_context_entry; 6892 6893 u8 reserved_at_280[0x600]; 6894 6895 u8 pas[0][0x40]; 6896 }; 6897 6898 struct mlx5_ifc_create_sq_out_bits { 6899 u8 status[0x8]; 6900 u8 reserved_at_8[0x18]; 6901 6902 u8 syndrome[0x20]; 6903 6904 u8 reserved_at_40[0x8]; 6905 u8 sqn[0x18]; 6906 6907 u8 reserved_at_60[0x20]; 6908 }; 6909 6910 struct mlx5_ifc_create_sq_in_bits { 6911 u8 opcode[0x10]; 6912 u8 uid[0x10]; 6913 6914 u8 reserved_at_20[0x10]; 6915 u8 op_mod[0x10]; 6916 6917 u8 reserved_at_40[0xc0]; 6918 6919 struct mlx5_ifc_sqc_bits ctx; 6920 }; 6921 6922 struct mlx5_ifc_create_scheduling_element_out_bits { 6923 u8 status[0x8]; 6924 u8 reserved_at_8[0x18]; 6925 6926 u8 syndrome[0x20]; 6927 6928 u8 reserved_at_40[0x40]; 6929 6930 u8 scheduling_element_id[0x20]; 6931 6932 u8 reserved_at_a0[0x160]; 6933 }; 6934 6935 struct mlx5_ifc_create_scheduling_element_in_bits { 6936 u8 opcode[0x10]; 6937 u8 reserved_at_10[0x10]; 6938 6939 u8 reserved_at_20[0x10]; 6940 u8 op_mod[0x10]; 6941 6942 u8 scheduling_hierarchy[0x8]; 6943 u8 reserved_at_48[0x18]; 6944 6945 u8 reserved_at_60[0xa0]; 6946 6947 struct mlx5_ifc_scheduling_context_bits scheduling_context; 6948 6949 u8 reserved_at_300[0x100]; 6950 }; 6951 6952 struct mlx5_ifc_create_rqt_out_bits { 6953 u8 status[0x8]; 6954 u8 reserved_at_8[0x18]; 6955 6956 u8 syndrome[0x20]; 6957 6958 u8 reserved_at_40[0x8]; 6959 u8 rqtn[0x18]; 6960 6961 u8 reserved_at_60[0x20]; 6962 }; 6963 6964 struct mlx5_ifc_create_rqt_in_bits { 6965 u8 opcode[0x10]; 6966 u8 uid[0x10]; 6967 6968 u8 reserved_at_20[0x10]; 6969 u8 op_mod[0x10]; 6970 6971 u8 reserved_at_40[0xc0]; 6972 6973 struct mlx5_ifc_rqtc_bits rqt_context; 6974 }; 6975 6976 struct mlx5_ifc_create_rq_out_bits { 6977 u8 status[0x8]; 6978 u8 reserved_at_8[0x18]; 6979 6980 u8 syndrome[0x20]; 6981 6982 u8 reserved_at_40[0x8]; 6983 u8 rqn[0x18]; 6984 6985 u8 reserved_at_60[0x20]; 6986 }; 6987 6988 struct mlx5_ifc_create_rq_in_bits { 6989 u8 opcode[0x10]; 6990 u8 uid[0x10]; 6991 6992 u8 reserved_at_20[0x10]; 6993 u8 op_mod[0x10]; 6994 6995 u8 reserved_at_40[0xc0]; 6996 6997 struct mlx5_ifc_rqc_bits ctx; 6998 }; 6999 7000 struct mlx5_ifc_create_rmp_out_bits { 7001 u8 status[0x8]; 7002 u8 reserved_at_8[0x18]; 7003 7004 u8 syndrome[0x20]; 7005 7006 u8 reserved_at_40[0x8]; 7007 u8 rmpn[0x18]; 7008 7009 u8 reserved_at_60[0x20]; 7010 }; 7011 7012 struct mlx5_ifc_create_rmp_in_bits { 7013 u8 opcode[0x10]; 7014 u8 uid[0x10]; 7015 7016 u8 reserved_at_20[0x10]; 7017 u8 op_mod[0x10]; 7018 7019 u8 reserved_at_40[0xc0]; 7020 7021 struct mlx5_ifc_rmpc_bits ctx; 7022 }; 7023 7024 struct mlx5_ifc_create_qp_out_bits { 7025 u8 status[0x8]; 7026 u8 reserved_at_8[0x18]; 7027 7028 u8 syndrome[0x20]; 7029 7030 u8 reserved_at_40[0x8]; 7031 u8 qpn[0x18]; 7032 7033 u8 reserved_at_60[0x20]; 7034 }; 7035 7036 struct mlx5_ifc_create_qp_in_bits { 7037 u8 opcode[0x10]; 7038 u8 uid[0x10]; 7039 7040 u8 reserved_at_20[0x10]; 7041 u8 op_mod[0x10]; 7042 7043 u8 reserved_at_40[0x40]; 7044 7045 u8 opt_param_mask[0x20]; 7046 7047 u8 reserved_at_a0[0x20]; 7048 7049 struct mlx5_ifc_qpc_bits qpc; 7050 7051 u8 reserved_at_800[0x60]; 7052 7053 u8 wq_umem_valid[0x1]; 7054 u8 reserved_at_861[0x1f]; 7055 7056 u8 pas[0][0x40]; 7057 }; 7058 7059 struct mlx5_ifc_create_psv_out_bits { 7060 u8 status[0x8]; 7061 u8 reserved_at_8[0x18]; 7062 7063 u8 syndrome[0x20]; 7064 7065 u8 reserved_at_40[0x40]; 7066 7067 u8 reserved_at_80[0x8]; 7068 u8 psv0_index[0x18]; 7069 7070 u8 reserved_at_a0[0x8]; 7071 u8 psv1_index[0x18]; 7072 7073 u8 reserved_at_c0[0x8]; 7074 u8 psv2_index[0x18]; 7075 7076 u8 reserved_at_e0[0x8]; 7077 u8 psv3_index[0x18]; 7078 }; 7079 7080 struct mlx5_ifc_create_psv_in_bits { 7081 u8 opcode[0x10]; 7082 u8 reserved_at_10[0x10]; 7083 7084 u8 reserved_at_20[0x10]; 7085 u8 op_mod[0x10]; 7086 7087 u8 num_psv[0x4]; 7088 u8 reserved_at_44[0x4]; 7089 u8 pd[0x18]; 7090 7091 u8 reserved_at_60[0x20]; 7092 }; 7093 7094 struct mlx5_ifc_create_mkey_out_bits { 7095 u8 status[0x8]; 7096 u8 reserved_at_8[0x18]; 7097 7098 u8 syndrome[0x20]; 7099 7100 u8 reserved_at_40[0x8]; 7101 u8 mkey_index[0x18]; 7102 7103 u8 reserved_at_60[0x20]; 7104 }; 7105 7106 struct mlx5_ifc_create_mkey_in_bits { 7107 u8 opcode[0x10]; 7108 u8 reserved_at_10[0x10]; 7109 7110 u8 reserved_at_20[0x10]; 7111 u8 op_mod[0x10]; 7112 7113 u8 reserved_at_40[0x20]; 7114 7115 u8 pg_access[0x1]; 7116 u8 mkey_umem_valid[0x1]; 7117 u8 reserved_at_62[0x1e]; 7118 7119 struct mlx5_ifc_mkc_bits memory_key_mkey_entry; 7120 7121 u8 reserved_at_280[0x80]; 7122 7123 u8 translations_octword_actual_size[0x20]; 7124 7125 u8 reserved_at_320[0x560]; 7126 7127 u8 klm_pas_mtt[0][0x20]; 7128 }; 7129 7130 struct mlx5_ifc_create_flow_table_out_bits { 7131 u8 status[0x8]; 7132 u8 reserved_at_8[0x18]; 7133 7134 u8 syndrome[0x20]; 7135 7136 u8 reserved_at_40[0x8]; 7137 u8 table_id[0x18]; 7138 7139 u8 reserved_at_60[0x20]; 7140 }; 7141 7142 struct mlx5_ifc_flow_table_context_bits { 7143 u8 reformat_en[0x1]; 7144 u8 decap_en[0x1]; 7145 u8 reserved_at_2[0x2]; 7146 u8 table_miss_action[0x4]; 7147 u8 level[0x8]; 7148 u8 reserved_at_10[0x8]; 7149 u8 log_size[0x8]; 7150 7151 u8 reserved_at_20[0x8]; 7152 u8 table_miss_id[0x18]; 7153 7154 u8 reserved_at_40[0x8]; 7155 u8 lag_master_next_table_id[0x18]; 7156 7157 u8 reserved_at_60[0xe0]; 7158 }; 7159 7160 struct mlx5_ifc_create_flow_table_in_bits { 7161 u8 opcode[0x10]; 7162 u8 reserved_at_10[0x10]; 7163 7164 u8 reserved_at_20[0x10]; 7165 u8 op_mod[0x10]; 7166 7167 u8 other_vport[0x1]; 7168 u8 reserved_at_41[0xf]; 7169 u8 vport_number[0x10]; 7170 7171 u8 reserved_at_60[0x20]; 7172 7173 u8 table_type[0x8]; 7174 u8 reserved_at_88[0x18]; 7175 7176 u8 reserved_at_a0[0x20]; 7177 7178 struct mlx5_ifc_flow_table_context_bits flow_table_context; 7179 }; 7180 7181 struct mlx5_ifc_create_flow_group_out_bits { 7182 u8 status[0x8]; 7183 u8 reserved_at_8[0x18]; 7184 7185 u8 syndrome[0x20]; 7186 7187 u8 reserved_at_40[0x8]; 7188 u8 group_id[0x18]; 7189 7190 u8 reserved_at_60[0x20]; 7191 }; 7192 7193 enum { 7194 MLX5_CREATE_FLOW_GROUP_IN_MATCH_CRITERIA_ENABLE_OUTER_HEADERS = 0x0, 7195 MLX5_CREATE_FLOW_GROUP_IN_MATCH_CRITERIA_ENABLE_MISC_PARAMETERS = 0x1, 7196 MLX5_CREATE_FLOW_GROUP_IN_MATCH_CRITERIA_ENABLE_INNER_HEADERS = 0x2, 7197 MLX5_CREATE_FLOW_GROUP_IN_MATCH_CRITERIA_ENABLE_MISC_PARAMETERS_2 = 0x3, 7198 }; 7199 7200 struct mlx5_ifc_create_flow_group_in_bits { 7201 u8 opcode[0x10]; 7202 u8 reserved_at_10[0x10]; 7203 7204 u8 reserved_at_20[0x10]; 7205 u8 op_mod[0x10]; 7206 7207 u8 other_vport[0x1]; 7208 u8 reserved_at_41[0xf]; 7209 u8 vport_number[0x10]; 7210 7211 u8 reserved_at_60[0x20]; 7212 7213 u8 table_type[0x8]; 7214 u8 reserved_at_88[0x18]; 7215 7216 u8 reserved_at_a0[0x8]; 7217 u8 table_id[0x18]; 7218 7219 u8 source_eswitch_owner_vhca_id_valid[0x1]; 7220 7221 u8 reserved_at_c1[0x1f]; 7222 7223 u8 start_flow_index[0x20]; 7224 7225 u8 reserved_at_100[0x20]; 7226 7227 u8 end_flow_index[0x20]; 7228 7229 u8 reserved_at_140[0xa0]; 7230 7231 u8 reserved_at_1e0[0x18]; 7232 u8 match_criteria_enable[0x8]; 7233 7234 struct mlx5_ifc_fte_match_param_bits match_criteria; 7235 7236 u8 reserved_at_1200[0xe00]; 7237 }; 7238 7239 struct mlx5_ifc_create_eq_out_bits { 7240 u8 status[0x8]; 7241 u8 reserved_at_8[0x18]; 7242 7243 u8 syndrome[0x20]; 7244 7245 u8 reserved_at_40[0x18]; 7246 u8 eq_number[0x8]; 7247 7248 u8 reserved_at_60[0x20]; 7249 }; 7250 7251 struct mlx5_ifc_create_eq_in_bits { 7252 u8 opcode[0x10]; 7253 u8 reserved_at_10[0x10]; 7254 7255 u8 reserved_at_20[0x10]; 7256 u8 op_mod[0x10]; 7257 7258 u8 reserved_at_40[0x40]; 7259 7260 struct mlx5_ifc_eqc_bits eq_context_entry; 7261 7262 u8 reserved_at_280[0x40]; 7263 7264 u8 event_bitmask[0x40]; 7265 7266 u8 reserved_at_300[0x580]; 7267 7268 u8 pas[0][0x40]; 7269 }; 7270 7271 struct mlx5_ifc_create_dct_out_bits { 7272 u8 status[0x8]; 7273 u8 reserved_at_8[0x18]; 7274 7275 u8 syndrome[0x20]; 7276 7277 u8 reserved_at_40[0x8]; 7278 u8 dctn[0x18]; 7279 7280 u8 reserved_at_60[0x20]; 7281 }; 7282 7283 struct mlx5_ifc_create_dct_in_bits { 7284 u8 opcode[0x10]; 7285 u8 uid[0x10]; 7286 7287 u8 reserved_at_20[0x10]; 7288 u8 op_mod[0x10]; 7289 7290 u8 reserved_at_40[0x40]; 7291 7292 struct mlx5_ifc_dctc_bits dct_context_entry; 7293 7294 u8 reserved_at_280[0x180]; 7295 }; 7296 7297 struct mlx5_ifc_create_cq_out_bits { 7298 u8 status[0x8]; 7299 u8 reserved_at_8[0x18]; 7300 7301 u8 syndrome[0x20]; 7302 7303 u8 reserved_at_40[0x8]; 7304 u8 cqn[0x18]; 7305 7306 u8 reserved_at_60[0x20]; 7307 }; 7308 7309 struct mlx5_ifc_create_cq_in_bits { 7310 u8 opcode[0x10]; 7311 u8 uid[0x10]; 7312 7313 u8 reserved_at_20[0x10]; 7314 u8 op_mod[0x10]; 7315 7316 u8 reserved_at_40[0x40]; 7317 7318 struct mlx5_ifc_cqc_bits cq_context; 7319 7320 u8 reserved_at_280[0x60]; 7321 7322 u8 cq_umem_valid[0x1]; 7323 u8 reserved_at_2e1[0x59f]; 7324 7325 u8 pas[0][0x40]; 7326 }; 7327 7328 struct mlx5_ifc_config_int_moderation_out_bits { 7329 u8 status[0x8]; 7330 u8 reserved_at_8[0x18]; 7331 7332 u8 syndrome[0x20]; 7333 7334 u8 reserved_at_40[0x4]; 7335 u8 min_delay[0xc]; 7336 u8 int_vector[0x10]; 7337 7338 u8 reserved_at_60[0x20]; 7339 }; 7340 7341 enum { 7342 MLX5_CONFIG_INT_MODERATION_IN_OP_MOD_WRITE = 0x0, 7343 MLX5_CONFIG_INT_MODERATION_IN_OP_MOD_READ = 0x1, 7344 }; 7345 7346 struct mlx5_ifc_config_int_moderation_in_bits { 7347 u8 opcode[0x10]; 7348 u8 reserved_at_10[0x10]; 7349 7350 u8 reserved_at_20[0x10]; 7351 u8 op_mod[0x10]; 7352 7353 u8 reserved_at_40[0x4]; 7354 u8 min_delay[0xc]; 7355 u8 int_vector[0x10]; 7356 7357 u8 reserved_at_60[0x20]; 7358 }; 7359 7360 struct mlx5_ifc_attach_to_mcg_out_bits { 7361 u8 status[0x8]; 7362 u8 reserved_at_8[0x18]; 7363 7364 u8 syndrome[0x20]; 7365 7366 u8 reserved_at_40[0x40]; 7367 }; 7368 7369 struct mlx5_ifc_attach_to_mcg_in_bits { 7370 u8 opcode[0x10]; 7371 u8 uid[0x10]; 7372 7373 u8 reserved_at_20[0x10]; 7374 u8 op_mod[0x10]; 7375 7376 u8 reserved_at_40[0x8]; 7377 u8 qpn[0x18]; 7378 7379 u8 reserved_at_60[0x20]; 7380 7381 u8 multicast_gid[16][0x8]; 7382 }; 7383 7384 struct mlx5_ifc_arm_xrq_out_bits { 7385 u8 status[0x8]; 7386 u8 reserved_at_8[0x18]; 7387 7388 u8 syndrome[0x20]; 7389 7390 u8 reserved_at_40[0x40]; 7391 }; 7392 7393 struct mlx5_ifc_arm_xrq_in_bits { 7394 u8 opcode[0x10]; 7395 u8 reserved_at_10[0x10]; 7396 7397 u8 reserved_at_20[0x10]; 7398 u8 op_mod[0x10]; 7399 7400 u8 reserved_at_40[0x8]; 7401 u8 xrqn[0x18]; 7402 7403 u8 reserved_at_60[0x10]; 7404 u8 lwm[0x10]; 7405 }; 7406 7407 struct mlx5_ifc_arm_xrc_srq_out_bits { 7408 u8 status[0x8]; 7409 u8 reserved_at_8[0x18]; 7410 7411 u8 syndrome[0x20]; 7412 7413 u8 reserved_at_40[0x40]; 7414 }; 7415 7416 enum { 7417 MLX5_ARM_XRC_SRQ_IN_OP_MOD_XRC_SRQ = 0x1, 7418 }; 7419 7420 struct mlx5_ifc_arm_xrc_srq_in_bits { 7421 u8 opcode[0x10]; 7422 u8 uid[0x10]; 7423 7424 u8 reserved_at_20[0x10]; 7425 u8 op_mod[0x10]; 7426 7427 u8 reserved_at_40[0x8]; 7428 u8 xrc_srqn[0x18]; 7429 7430 u8 reserved_at_60[0x10]; 7431 u8 lwm[0x10]; 7432 }; 7433 7434 struct mlx5_ifc_arm_rq_out_bits { 7435 u8 status[0x8]; 7436 u8 reserved_at_8[0x18]; 7437 7438 u8 syndrome[0x20]; 7439 7440 u8 reserved_at_40[0x40]; 7441 }; 7442 7443 enum { 7444 MLX5_ARM_RQ_IN_OP_MOD_SRQ = 0x1, 7445 MLX5_ARM_RQ_IN_OP_MOD_XRQ = 0x2, 7446 }; 7447 7448 struct mlx5_ifc_arm_rq_in_bits { 7449 u8 opcode[0x10]; 7450 u8 uid[0x10]; 7451 7452 u8 reserved_at_20[0x10]; 7453 u8 op_mod[0x10]; 7454 7455 u8 reserved_at_40[0x8]; 7456 u8 srq_number[0x18]; 7457 7458 u8 reserved_at_60[0x10]; 7459 u8 lwm[0x10]; 7460 }; 7461 7462 struct mlx5_ifc_arm_dct_out_bits { 7463 u8 status[0x8]; 7464 u8 reserved_at_8[0x18]; 7465 7466 u8 syndrome[0x20]; 7467 7468 u8 reserved_at_40[0x40]; 7469 }; 7470 7471 struct mlx5_ifc_arm_dct_in_bits { 7472 u8 opcode[0x10]; 7473 u8 reserved_at_10[0x10]; 7474 7475 u8 reserved_at_20[0x10]; 7476 u8 op_mod[0x10]; 7477 7478 u8 reserved_at_40[0x8]; 7479 u8 dct_number[0x18]; 7480 7481 u8 reserved_at_60[0x20]; 7482 }; 7483 7484 struct mlx5_ifc_alloc_xrcd_out_bits { 7485 u8 status[0x8]; 7486 u8 reserved_at_8[0x18]; 7487 7488 u8 syndrome[0x20]; 7489 7490 u8 reserved_at_40[0x8]; 7491 u8 xrcd[0x18]; 7492 7493 u8 reserved_at_60[0x20]; 7494 }; 7495 7496 struct mlx5_ifc_alloc_xrcd_in_bits { 7497 u8 opcode[0x10]; 7498 u8 uid[0x10]; 7499 7500 u8 reserved_at_20[0x10]; 7501 u8 op_mod[0x10]; 7502 7503 u8 reserved_at_40[0x40]; 7504 }; 7505 7506 struct mlx5_ifc_alloc_uar_out_bits { 7507 u8 status[0x8]; 7508 u8 reserved_at_8[0x18]; 7509 7510 u8 syndrome[0x20]; 7511 7512 u8 reserved_at_40[0x8]; 7513 u8 uar[0x18]; 7514 7515 u8 reserved_at_60[0x20]; 7516 }; 7517 7518 struct mlx5_ifc_alloc_uar_in_bits { 7519 u8 opcode[0x10]; 7520 u8 reserved_at_10[0x10]; 7521 7522 u8 reserved_at_20[0x10]; 7523 u8 op_mod[0x10]; 7524 7525 u8 reserved_at_40[0x40]; 7526 }; 7527 7528 struct mlx5_ifc_alloc_transport_domain_out_bits { 7529 u8 status[0x8]; 7530 u8 reserved_at_8[0x18]; 7531 7532 u8 syndrome[0x20]; 7533 7534 u8 reserved_at_40[0x8]; 7535 u8 transport_domain[0x18]; 7536 7537 u8 reserved_at_60[0x20]; 7538 }; 7539 7540 struct mlx5_ifc_alloc_transport_domain_in_bits { 7541 u8 opcode[0x10]; 7542 u8 reserved_at_10[0x10]; 7543 7544 u8 reserved_at_20[0x10]; 7545 u8 op_mod[0x10]; 7546 7547 u8 reserved_at_40[0x40]; 7548 }; 7549 7550 struct mlx5_ifc_alloc_q_counter_out_bits { 7551 u8 status[0x8]; 7552 u8 reserved_at_8[0x18]; 7553 7554 u8 syndrome[0x20]; 7555 7556 u8 reserved_at_40[0x18]; 7557 u8 counter_set_id[0x8]; 7558 7559 u8 reserved_at_60[0x20]; 7560 }; 7561 7562 struct mlx5_ifc_alloc_q_counter_in_bits { 7563 u8 opcode[0x10]; 7564 u8 reserved_at_10[0x10]; 7565 7566 u8 reserved_at_20[0x10]; 7567 u8 op_mod[0x10]; 7568 7569 u8 reserved_at_40[0x40]; 7570 }; 7571 7572 struct mlx5_ifc_alloc_pd_out_bits { 7573 u8 status[0x8]; 7574 u8 reserved_at_8[0x18]; 7575 7576 u8 syndrome[0x20]; 7577 7578 u8 reserved_at_40[0x8]; 7579 u8 pd[0x18]; 7580 7581 u8 reserved_at_60[0x20]; 7582 }; 7583 7584 struct mlx5_ifc_alloc_pd_in_bits { 7585 u8 opcode[0x10]; 7586 u8 uid[0x10]; 7587 7588 u8 reserved_at_20[0x10]; 7589 u8 op_mod[0x10]; 7590 7591 u8 reserved_at_40[0x40]; 7592 }; 7593 7594 struct mlx5_ifc_alloc_flow_counter_out_bits { 7595 u8 status[0x8]; 7596 u8 reserved_at_8[0x18]; 7597 7598 u8 syndrome[0x20]; 7599 7600 u8 flow_counter_id[0x20]; 7601 7602 u8 reserved_at_60[0x20]; 7603 }; 7604 7605 struct mlx5_ifc_alloc_flow_counter_in_bits { 7606 u8 opcode[0x10]; 7607 u8 reserved_at_10[0x10]; 7608 7609 u8 reserved_at_20[0x10]; 7610 u8 op_mod[0x10]; 7611 7612 u8 reserved_at_40[0x40]; 7613 }; 7614 7615 struct mlx5_ifc_add_vxlan_udp_dport_out_bits { 7616 u8 status[0x8]; 7617 u8 reserved_at_8[0x18]; 7618 7619 u8 syndrome[0x20]; 7620 7621 u8 reserved_at_40[0x40]; 7622 }; 7623 7624 struct mlx5_ifc_add_vxlan_udp_dport_in_bits { 7625 u8 opcode[0x10]; 7626 u8 reserved_at_10[0x10]; 7627 7628 u8 reserved_at_20[0x10]; 7629 u8 op_mod[0x10]; 7630 7631 u8 reserved_at_40[0x20]; 7632 7633 u8 reserved_at_60[0x10]; 7634 u8 vxlan_udp_port[0x10]; 7635 }; 7636 7637 struct mlx5_ifc_set_pp_rate_limit_out_bits { 7638 u8 status[0x8]; 7639 u8 reserved_at_8[0x18]; 7640 7641 u8 syndrome[0x20]; 7642 7643 u8 reserved_at_40[0x40]; 7644 }; 7645 7646 struct mlx5_ifc_set_pp_rate_limit_in_bits { 7647 u8 opcode[0x10]; 7648 u8 reserved_at_10[0x10]; 7649 7650 u8 reserved_at_20[0x10]; 7651 u8 op_mod[0x10]; 7652 7653 u8 reserved_at_40[0x10]; 7654 u8 rate_limit_index[0x10]; 7655 7656 u8 reserved_at_60[0x20]; 7657 7658 u8 rate_limit[0x20]; 7659 7660 u8 burst_upper_bound[0x20]; 7661 7662 u8 reserved_at_c0[0x10]; 7663 u8 typical_packet_size[0x10]; 7664 7665 u8 reserved_at_e0[0x120]; 7666 }; 7667 7668 struct mlx5_ifc_access_register_out_bits { 7669 u8 status[0x8]; 7670 u8 reserved_at_8[0x18]; 7671 7672 u8 syndrome[0x20]; 7673 7674 u8 reserved_at_40[0x40]; 7675 7676 u8 register_data[0][0x20]; 7677 }; 7678 7679 enum { 7680 MLX5_ACCESS_REGISTER_IN_OP_MOD_WRITE = 0x0, 7681 MLX5_ACCESS_REGISTER_IN_OP_MOD_READ = 0x1, 7682 }; 7683 7684 struct mlx5_ifc_access_register_in_bits { 7685 u8 opcode[0x10]; 7686 u8 reserved_at_10[0x10]; 7687 7688 u8 reserved_at_20[0x10]; 7689 u8 op_mod[0x10]; 7690 7691 u8 reserved_at_40[0x10]; 7692 u8 register_id[0x10]; 7693 7694 u8 argument[0x20]; 7695 7696 u8 register_data[0][0x20]; 7697 }; 7698 7699 struct mlx5_ifc_sltp_reg_bits { 7700 u8 status[0x4]; 7701 u8 version[0x4]; 7702 u8 local_port[0x8]; 7703 u8 pnat[0x2]; 7704 u8 reserved_at_12[0x2]; 7705 u8 lane[0x4]; 7706 u8 reserved_at_18[0x8]; 7707 7708 u8 reserved_at_20[0x20]; 7709 7710 u8 reserved_at_40[0x7]; 7711 u8 polarity[0x1]; 7712 u8 ob_tap0[0x8]; 7713 u8 ob_tap1[0x8]; 7714 u8 ob_tap2[0x8]; 7715 7716 u8 reserved_at_60[0xc]; 7717 u8 ob_preemp_mode[0x4]; 7718 u8 ob_reg[0x8]; 7719 u8 ob_bias[0x8]; 7720 7721 u8 reserved_at_80[0x20]; 7722 }; 7723 7724 struct mlx5_ifc_slrg_reg_bits { 7725 u8 status[0x4]; 7726 u8 version[0x4]; 7727 u8 local_port[0x8]; 7728 u8 pnat[0x2]; 7729 u8 reserved_at_12[0x2]; 7730 u8 lane[0x4]; 7731 u8 reserved_at_18[0x8]; 7732 7733 u8 time_to_link_up[0x10]; 7734 u8 reserved_at_30[0xc]; 7735 u8 grade_lane_speed[0x4]; 7736 7737 u8 grade_version[0x8]; 7738 u8 grade[0x18]; 7739 7740 u8 reserved_at_60[0x4]; 7741 u8 height_grade_type[0x4]; 7742 u8 height_grade[0x18]; 7743 7744 u8 height_dz[0x10]; 7745 u8 height_dv[0x10]; 7746 7747 u8 reserved_at_a0[0x10]; 7748 u8 height_sigma[0x10]; 7749 7750 u8 reserved_at_c0[0x20]; 7751 7752 u8 reserved_at_e0[0x4]; 7753 u8 phase_grade_type[0x4]; 7754 u8 phase_grade[0x18]; 7755 7756 u8 reserved_at_100[0x8]; 7757 u8 phase_eo_pos[0x8]; 7758 u8 reserved_at_110[0x8]; 7759 u8 phase_eo_neg[0x8]; 7760 7761 u8 ffe_set_tested[0x10]; 7762 u8 test_errors_per_lane[0x10]; 7763 }; 7764 7765 struct mlx5_ifc_pvlc_reg_bits { 7766 u8 reserved_at_0[0x8]; 7767 u8 local_port[0x8]; 7768 u8 reserved_at_10[0x10]; 7769 7770 u8 reserved_at_20[0x1c]; 7771 u8 vl_hw_cap[0x4]; 7772 7773 u8 reserved_at_40[0x1c]; 7774 u8 vl_admin[0x4]; 7775 7776 u8 reserved_at_60[0x1c]; 7777 u8 vl_operational[0x4]; 7778 }; 7779 7780 struct mlx5_ifc_pude_reg_bits { 7781 u8 swid[0x8]; 7782 u8 local_port[0x8]; 7783 u8 reserved_at_10[0x4]; 7784 u8 admin_status[0x4]; 7785 u8 reserved_at_18[0x4]; 7786 u8 oper_status[0x4]; 7787 7788 u8 reserved_at_20[0x60]; 7789 }; 7790 7791 struct mlx5_ifc_ptys_reg_bits { 7792 u8 reserved_at_0[0x1]; 7793 u8 an_disable_admin[0x1]; 7794 u8 an_disable_cap[0x1]; 7795 u8 reserved_at_3[0x5]; 7796 u8 local_port[0x8]; 7797 u8 reserved_at_10[0xd]; 7798 u8 proto_mask[0x3]; 7799 7800 u8 an_status[0x4]; 7801 u8 reserved_at_24[0x3c]; 7802 7803 u8 eth_proto_capability[0x20]; 7804 7805 u8 ib_link_width_capability[0x10]; 7806 u8 ib_proto_capability[0x10]; 7807 7808 u8 reserved_at_a0[0x20]; 7809 7810 u8 eth_proto_admin[0x20]; 7811 7812 u8 ib_link_width_admin[0x10]; 7813 u8 ib_proto_admin[0x10]; 7814 7815 u8 reserved_at_100[0x20]; 7816 7817 u8 eth_proto_oper[0x20]; 7818 7819 u8 ib_link_width_oper[0x10]; 7820 u8 ib_proto_oper[0x10]; 7821 7822 u8 reserved_at_160[0x1c]; 7823 u8 connector_type[0x4]; 7824 7825 u8 eth_proto_lp_advertise[0x20]; 7826 7827 u8 reserved_at_1a0[0x60]; 7828 }; 7829 7830 struct mlx5_ifc_mlcr_reg_bits { 7831 u8 reserved_at_0[0x8]; 7832 u8 local_port[0x8]; 7833 u8 reserved_at_10[0x20]; 7834 7835 u8 beacon_duration[0x10]; 7836 u8 reserved_at_40[0x10]; 7837 7838 u8 beacon_remain[0x10]; 7839 }; 7840 7841 struct mlx5_ifc_ptas_reg_bits { 7842 u8 reserved_at_0[0x20]; 7843 7844 u8 algorithm_options[0x10]; 7845 u8 reserved_at_30[0x4]; 7846 u8 repetitions_mode[0x4]; 7847 u8 num_of_repetitions[0x8]; 7848 7849 u8 grade_version[0x8]; 7850 u8 height_grade_type[0x4]; 7851 u8 phase_grade_type[0x4]; 7852 u8 height_grade_weight[0x8]; 7853 u8 phase_grade_weight[0x8]; 7854 7855 u8 gisim_measure_bits[0x10]; 7856 u8 adaptive_tap_measure_bits[0x10]; 7857 7858 u8 ber_bath_high_error_threshold[0x10]; 7859 u8 ber_bath_mid_error_threshold[0x10]; 7860 7861 u8 ber_bath_low_error_threshold[0x10]; 7862 u8 one_ratio_high_threshold[0x10]; 7863 7864 u8 one_ratio_high_mid_threshold[0x10]; 7865 u8 one_ratio_low_mid_threshold[0x10]; 7866 7867 u8 one_ratio_low_threshold[0x10]; 7868 u8 ndeo_error_threshold[0x10]; 7869 7870 u8 mixer_offset_step_size[0x10]; 7871 u8 reserved_at_110[0x8]; 7872 u8 mix90_phase_for_voltage_bath[0x8]; 7873 7874 u8 mixer_offset_start[0x10]; 7875 u8 mixer_offset_end[0x10]; 7876 7877 u8 reserved_at_140[0x15]; 7878 u8 ber_test_time[0xb]; 7879 }; 7880 7881 struct mlx5_ifc_pspa_reg_bits { 7882 u8 swid[0x8]; 7883 u8 local_port[0x8]; 7884 u8 sub_port[0x8]; 7885 u8 reserved_at_18[0x8]; 7886 7887 u8 reserved_at_20[0x20]; 7888 }; 7889 7890 struct mlx5_ifc_pqdr_reg_bits { 7891 u8 reserved_at_0[0x8]; 7892 u8 local_port[0x8]; 7893 u8 reserved_at_10[0x5]; 7894 u8 prio[0x3]; 7895 u8 reserved_at_18[0x6]; 7896 u8 mode[0x2]; 7897 7898 u8 reserved_at_20[0x20]; 7899 7900 u8 reserved_at_40[0x10]; 7901 u8 min_threshold[0x10]; 7902 7903 u8 reserved_at_60[0x10]; 7904 u8 max_threshold[0x10]; 7905 7906 u8 reserved_at_80[0x10]; 7907 u8 mark_probability_denominator[0x10]; 7908 7909 u8 reserved_at_a0[0x60]; 7910 }; 7911 7912 struct mlx5_ifc_ppsc_reg_bits { 7913 u8 reserved_at_0[0x8]; 7914 u8 local_port[0x8]; 7915 u8 reserved_at_10[0x10]; 7916 7917 u8 reserved_at_20[0x60]; 7918 7919 u8 reserved_at_80[0x1c]; 7920 u8 wrps_admin[0x4]; 7921 7922 u8 reserved_at_a0[0x1c]; 7923 u8 wrps_status[0x4]; 7924 7925 u8 reserved_at_c0[0x8]; 7926 u8 up_threshold[0x8]; 7927 u8 reserved_at_d0[0x8]; 7928 u8 down_threshold[0x8]; 7929 7930 u8 reserved_at_e0[0x20]; 7931 7932 u8 reserved_at_100[0x1c]; 7933 u8 srps_admin[0x4]; 7934 7935 u8 reserved_at_120[0x1c]; 7936 u8 srps_status[0x4]; 7937 7938 u8 reserved_at_140[0x40]; 7939 }; 7940 7941 struct mlx5_ifc_pplr_reg_bits { 7942 u8 reserved_at_0[0x8]; 7943 u8 local_port[0x8]; 7944 u8 reserved_at_10[0x10]; 7945 7946 u8 reserved_at_20[0x8]; 7947 u8 lb_cap[0x8]; 7948 u8 reserved_at_30[0x8]; 7949 u8 lb_en[0x8]; 7950 }; 7951 7952 struct mlx5_ifc_pplm_reg_bits { 7953 u8 reserved_at_0[0x8]; 7954 u8 local_port[0x8]; 7955 u8 reserved_at_10[0x10]; 7956 7957 u8 reserved_at_20[0x20]; 7958 7959 u8 port_profile_mode[0x8]; 7960 u8 static_port_profile[0x8]; 7961 u8 active_port_profile[0x8]; 7962 u8 reserved_at_58[0x8]; 7963 7964 u8 retransmission_active[0x8]; 7965 u8 fec_mode_active[0x18]; 7966 7967 u8 rs_fec_correction_bypass_cap[0x4]; 7968 u8 reserved_at_84[0x8]; 7969 u8 fec_override_cap_56g[0x4]; 7970 u8 fec_override_cap_100g[0x4]; 7971 u8 fec_override_cap_50g[0x4]; 7972 u8 fec_override_cap_25g[0x4]; 7973 u8 fec_override_cap_10g_40g[0x4]; 7974 7975 u8 rs_fec_correction_bypass_admin[0x4]; 7976 u8 reserved_at_a4[0x8]; 7977 u8 fec_override_admin_56g[0x4]; 7978 u8 fec_override_admin_100g[0x4]; 7979 u8 fec_override_admin_50g[0x4]; 7980 u8 fec_override_admin_25g[0x4]; 7981 u8 fec_override_admin_10g_40g[0x4]; 7982 }; 7983 7984 struct mlx5_ifc_ppcnt_reg_bits { 7985 u8 swid[0x8]; 7986 u8 local_port[0x8]; 7987 u8 pnat[0x2]; 7988 u8 reserved_at_12[0x8]; 7989 u8 grp[0x6]; 7990 7991 u8 clr[0x1]; 7992 u8 reserved_at_21[0x1c]; 7993 u8 prio_tc[0x3]; 7994 7995 union mlx5_ifc_eth_cntrs_grp_data_layout_auto_bits counter_set; 7996 }; 7997 7998 struct mlx5_ifc_mpcnt_reg_bits { 7999 u8 reserved_at_0[0x8]; 8000 u8 pcie_index[0x8]; 8001 u8 reserved_at_10[0xa]; 8002 u8 grp[0x6]; 8003 8004 u8 clr[0x1]; 8005 u8 reserved_at_21[0x1f]; 8006 8007 union mlx5_ifc_pcie_cntrs_grp_data_layout_auto_bits counter_set; 8008 }; 8009 8010 struct mlx5_ifc_ppad_reg_bits { 8011 u8 reserved_at_0[0x3]; 8012 u8 single_mac[0x1]; 8013 u8 reserved_at_4[0x4]; 8014 u8 local_port[0x8]; 8015 u8 mac_47_32[0x10]; 8016 8017 u8 mac_31_0[0x20]; 8018 8019 u8 reserved_at_40[0x40]; 8020 }; 8021 8022 struct mlx5_ifc_pmtu_reg_bits { 8023 u8 reserved_at_0[0x8]; 8024 u8 local_port[0x8]; 8025 u8 reserved_at_10[0x10]; 8026 8027 u8 max_mtu[0x10]; 8028 u8 reserved_at_30[0x10]; 8029 8030 u8 admin_mtu[0x10]; 8031 u8 reserved_at_50[0x10]; 8032 8033 u8 oper_mtu[0x10]; 8034 u8 reserved_at_70[0x10]; 8035 }; 8036 8037 struct mlx5_ifc_pmpr_reg_bits { 8038 u8 reserved_at_0[0x8]; 8039 u8 module[0x8]; 8040 u8 reserved_at_10[0x10]; 8041 8042 u8 reserved_at_20[0x18]; 8043 u8 attenuation_5g[0x8]; 8044 8045 u8 reserved_at_40[0x18]; 8046 u8 attenuation_7g[0x8]; 8047 8048 u8 reserved_at_60[0x18]; 8049 u8 attenuation_12g[0x8]; 8050 }; 8051 8052 struct mlx5_ifc_pmpe_reg_bits { 8053 u8 reserved_at_0[0x8]; 8054 u8 module[0x8]; 8055 u8 reserved_at_10[0xc]; 8056 u8 module_status[0x4]; 8057 8058 u8 reserved_at_20[0x60]; 8059 }; 8060 8061 struct mlx5_ifc_pmpc_reg_bits { 8062 u8 module_state_updated[32][0x8]; 8063 }; 8064 8065 struct mlx5_ifc_pmlpn_reg_bits { 8066 u8 reserved_at_0[0x4]; 8067 u8 mlpn_status[0x4]; 8068 u8 local_port[0x8]; 8069 u8 reserved_at_10[0x10]; 8070 8071 u8 e[0x1]; 8072 u8 reserved_at_21[0x1f]; 8073 }; 8074 8075 struct mlx5_ifc_pmlp_reg_bits { 8076 u8 rxtx[0x1]; 8077 u8 reserved_at_1[0x7]; 8078 u8 local_port[0x8]; 8079 u8 reserved_at_10[0x8]; 8080 u8 width[0x8]; 8081 8082 u8 lane0_module_mapping[0x20]; 8083 8084 u8 lane1_module_mapping[0x20]; 8085 8086 u8 lane2_module_mapping[0x20]; 8087 8088 u8 lane3_module_mapping[0x20]; 8089 8090 u8 reserved_at_a0[0x160]; 8091 }; 8092 8093 struct mlx5_ifc_pmaos_reg_bits { 8094 u8 reserved_at_0[0x8]; 8095 u8 module[0x8]; 8096 u8 reserved_at_10[0x4]; 8097 u8 admin_status[0x4]; 8098 u8 reserved_at_18[0x4]; 8099 u8 oper_status[0x4]; 8100 8101 u8 ase[0x1]; 8102 u8 ee[0x1]; 8103 u8 reserved_at_22[0x1c]; 8104 u8 e[0x2]; 8105 8106 u8 reserved_at_40[0x40]; 8107 }; 8108 8109 struct mlx5_ifc_plpc_reg_bits { 8110 u8 reserved_at_0[0x4]; 8111 u8 profile_id[0xc]; 8112 u8 reserved_at_10[0x4]; 8113 u8 proto_mask[0x4]; 8114 u8 reserved_at_18[0x8]; 8115 8116 u8 reserved_at_20[0x10]; 8117 u8 lane_speed[0x10]; 8118 8119 u8 reserved_at_40[0x17]; 8120 u8 lpbf[0x1]; 8121 u8 fec_mode_policy[0x8]; 8122 8123 u8 retransmission_capability[0x8]; 8124 u8 fec_mode_capability[0x18]; 8125 8126 u8 retransmission_support_admin[0x8]; 8127 u8 fec_mode_support_admin[0x18]; 8128 8129 u8 retransmission_request_admin[0x8]; 8130 u8 fec_mode_request_admin[0x18]; 8131 8132 u8 reserved_at_c0[0x80]; 8133 }; 8134 8135 struct mlx5_ifc_plib_reg_bits { 8136 u8 reserved_at_0[0x8]; 8137 u8 local_port[0x8]; 8138 u8 reserved_at_10[0x8]; 8139 u8 ib_port[0x8]; 8140 8141 u8 reserved_at_20[0x60]; 8142 }; 8143 8144 struct mlx5_ifc_plbf_reg_bits { 8145 u8 reserved_at_0[0x8]; 8146 u8 local_port[0x8]; 8147 u8 reserved_at_10[0xd]; 8148 u8 lbf_mode[0x3]; 8149 8150 u8 reserved_at_20[0x20]; 8151 }; 8152 8153 struct mlx5_ifc_pipg_reg_bits { 8154 u8 reserved_at_0[0x8]; 8155 u8 local_port[0x8]; 8156 u8 reserved_at_10[0x10]; 8157 8158 u8 dic[0x1]; 8159 u8 reserved_at_21[0x19]; 8160 u8 ipg[0x4]; 8161 u8 reserved_at_3e[0x2]; 8162 }; 8163 8164 struct mlx5_ifc_pifr_reg_bits { 8165 u8 reserved_at_0[0x8]; 8166 u8 local_port[0x8]; 8167 u8 reserved_at_10[0x10]; 8168 8169 u8 reserved_at_20[0xe0]; 8170 8171 u8 port_filter[8][0x20]; 8172 8173 u8 port_filter_update_en[8][0x20]; 8174 }; 8175 8176 struct mlx5_ifc_pfcc_reg_bits { 8177 u8 reserved_at_0[0x8]; 8178 u8 local_port[0x8]; 8179 u8 reserved_at_10[0xb]; 8180 u8 ppan_mask_n[0x1]; 8181 u8 minor_stall_mask[0x1]; 8182 u8 critical_stall_mask[0x1]; 8183 u8 reserved_at_1e[0x2]; 8184 8185 u8 ppan[0x4]; 8186 u8 reserved_at_24[0x4]; 8187 u8 prio_mask_tx[0x8]; 8188 u8 reserved_at_30[0x8]; 8189 u8 prio_mask_rx[0x8]; 8190 8191 u8 pptx[0x1]; 8192 u8 aptx[0x1]; 8193 u8 pptx_mask_n[0x1]; 8194 u8 reserved_at_43[0x5]; 8195 u8 pfctx[0x8]; 8196 u8 reserved_at_50[0x10]; 8197 8198 u8 pprx[0x1]; 8199 u8 aprx[0x1]; 8200 u8 pprx_mask_n[0x1]; 8201 u8 reserved_at_63[0x5]; 8202 u8 pfcrx[0x8]; 8203 u8 reserved_at_70[0x10]; 8204 8205 u8 device_stall_minor_watermark[0x10]; 8206 u8 device_stall_critical_watermark[0x10]; 8207 8208 u8 reserved_at_a0[0x60]; 8209 }; 8210 8211 struct mlx5_ifc_pelc_reg_bits { 8212 u8 op[0x4]; 8213 u8 reserved_at_4[0x4]; 8214 u8 local_port[0x8]; 8215 u8 reserved_at_10[0x10]; 8216 8217 u8 op_admin[0x8]; 8218 u8 op_capability[0x8]; 8219 u8 op_request[0x8]; 8220 u8 op_active[0x8]; 8221 8222 u8 admin[0x40]; 8223 8224 u8 capability[0x40]; 8225 8226 u8 request[0x40]; 8227 8228 u8 active[0x40]; 8229 8230 u8 reserved_at_140[0x80]; 8231 }; 8232 8233 struct mlx5_ifc_peir_reg_bits { 8234 u8 reserved_at_0[0x8]; 8235 u8 local_port[0x8]; 8236 u8 reserved_at_10[0x10]; 8237 8238 u8 reserved_at_20[0xc]; 8239 u8 error_count[0x4]; 8240 u8 reserved_at_30[0x10]; 8241 8242 u8 reserved_at_40[0xc]; 8243 u8 lane[0x4]; 8244 u8 reserved_at_50[0x8]; 8245 u8 error_type[0x8]; 8246 }; 8247 8248 struct mlx5_ifc_mpegc_reg_bits { 8249 u8 reserved_at_0[0x30]; 8250 u8 field_select[0x10]; 8251 8252 u8 tx_overflow_sense[0x1]; 8253 u8 mark_cqe[0x1]; 8254 u8 mark_cnp[0x1]; 8255 u8 reserved_at_43[0x1b]; 8256 u8 tx_lossy_overflow_oper[0x2]; 8257 8258 u8 reserved_at_60[0x100]; 8259 }; 8260 8261 struct mlx5_ifc_pcam_enhanced_features_bits { 8262 u8 reserved_at_0[0x6d]; 8263 u8 rx_icrc_encapsulated_counter[0x1]; 8264 u8 reserved_at_6e[0x8]; 8265 u8 pfcc_mask[0x1]; 8266 u8 reserved_at_77[0x3]; 8267 u8 per_lane_error_counters[0x1]; 8268 u8 rx_buffer_fullness_counters[0x1]; 8269 u8 ptys_connector_type[0x1]; 8270 u8 reserved_at_7d[0x1]; 8271 u8 ppcnt_discard_group[0x1]; 8272 u8 ppcnt_statistical_group[0x1]; 8273 }; 8274 8275 struct mlx5_ifc_pcam_regs_5000_to_507f_bits { 8276 u8 port_access_reg_cap_mask_127_to_96[0x20]; 8277 u8 port_access_reg_cap_mask_95_to_64[0x20]; 8278 8279 u8 port_access_reg_cap_mask_63_to_36[0x1c]; 8280 u8 pplm[0x1]; 8281 u8 port_access_reg_cap_mask_34_to_32[0x3]; 8282 8283 u8 port_access_reg_cap_mask_31_to_13[0x13]; 8284 u8 pbmc[0x1]; 8285 u8 pptb[0x1]; 8286 u8 port_access_reg_cap_mask_10_to_0[0xb]; 8287 }; 8288 8289 struct mlx5_ifc_pcam_reg_bits { 8290 u8 reserved_at_0[0x8]; 8291 u8 feature_group[0x8]; 8292 u8 reserved_at_10[0x8]; 8293 u8 access_reg_group[0x8]; 8294 8295 u8 reserved_at_20[0x20]; 8296 8297 union { 8298 struct mlx5_ifc_pcam_regs_5000_to_507f_bits regs_5000_to_507f; 8299 u8 reserved_at_0[0x80]; 8300 } port_access_reg_cap_mask; 8301 8302 u8 reserved_at_c0[0x80]; 8303 8304 union { 8305 struct mlx5_ifc_pcam_enhanced_features_bits enhanced_features; 8306 u8 reserved_at_0[0x80]; 8307 } feature_cap_mask; 8308 8309 u8 reserved_at_1c0[0xc0]; 8310 }; 8311 8312 struct mlx5_ifc_mcam_enhanced_features_bits { 8313 u8 reserved_at_0[0x74]; 8314 u8 mark_tx_action_cnp[0x1]; 8315 u8 mark_tx_action_cqe[0x1]; 8316 u8 dynamic_tx_overflow[0x1]; 8317 u8 reserved_at_77[0x4]; 8318 u8 pcie_outbound_stalled[0x1]; 8319 u8 tx_overflow_buffer_pkt[0x1]; 8320 u8 mtpps_enh_out_per_adj[0x1]; 8321 u8 mtpps_fs[0x1]; 8322 u8 pcie_performance_group[0x1]; 8323 }; 8324 8325 struct mlx5_ifc_mcam_access_reg_bits { 8326 u8 reserved_at_0[0x1c]; 8327 u8 mcda[0x1]; 8328 u8 mcc[0x1]; 8329 u8 mcqi[0x1]; 8330 u8 reserved_at_1f[0x1]; 8331 8332 u8 regs_95_to_87[0x9]; 8333 u8 mpegc[0x1]; 8334 u8 regs_85_to_68[0x12]; 8335 u8 tracer_registers[0x4]; 8336 8337 u8 regs_63_to_32[0x20]; 8338 u8 regs_31_to_0[0x20]; 8339 }; 8340 8341 struct mlx5_ifc_mcam_reg_bits { 8342 u8 reserved_at_0[0x8]; 8343 u8 feature_group[0x8]; 8344 u8 reserved_at_10[0x8]; 8345 u8 access_reg_group[0x8]; 8346 8347 u8 reserved_at_20[0x20]; 8348 8349 union { 8350 struct mlx5_ifc_mcam_access_reg_bits access_regs; 8351 u8 reserved_at_0[0x80]; 8352 } mng_access_reg_cap_mask; 8353 8354 u8 reserved_at_c0[0x80]; 8355 8356 union { 8357 struct mlx5_ifc_mcam_enhanced_features_bits enhanced_features; 8358 u8 reserved_at_0[0x80]; 8359 } mng_feature_cap_mask; 8360 8361 u8 reserved_at_1c0[0x80]; 8362 }; 8363 8364 struct mlx5_ifc_qcam_access_reg_cap_mask { 8365 u8 qcam_access_reg_cap_mask_127_to_20[0x6C]; 8366 u8 qpdpm[0x1]; 8367 u8 qcam_access_reg_cap_mask_18_to_4[0x0F]; 8368 u8 qdpm[0x1]; 8369 u8 qpts[0x1]; 8370 u8 qcap[0x1]; 8371 u8 qcam_access_reg_cap_mask_0[0x1]; 8372 }; 8373 8374 struct mlx5_ifc_qcam_qos_feature_cap_mask { 8375 u8 qcam_qos_feature_cap_mask_127_to_1[0x7F]; 8376 u8 qpts_trust_both[0x1]; 8377 }; 8378 8379 struct mlx5_ifc_qcam_reg_bits { 8380 u8 reserved_at_0[0x8]; 8381 u8 feature_group[0x8]; 8382 u8 reserved_at_10[0x8]; 8383 u8 access_reg_group[0x8]; 8384 u8 reserved_at_20[0x20]; 8385 8386 union { 8387 struct mlx5_ifc_qcam_access_reg_cap_mask reg_cap; 8388 u8 reserved_at_0[0x80]; 8389 } qos_access_reg_cap_mask; 8390 8391 u8 reserved_at_c0[0x80]; 8392 8393 union { 8394 struct mlx5_ifc_qcam_qos_feature_cap_mask feature_cap; 8395 u8 reserved_at_0[0x80]; 8396 } qos_feature_cap_mask; 8397 8398 u8 reserved_at_1c0[0x80]; 8399 }; 8400 8401 struct mlx5_ifc_pcap_reg_bits { 8402 u8 reserved_at_0[0x8]; 8403 u8 local_port[0x8]; 8404 u8 reserved_at_10[0x10]; 8405 8406 u8 port_capability_mask[4][0x20]; 8407 }; 8408 8409 struct mlx5_ifc_paos_reg_bits { 8410 u8 swid[0x8]; 8411 u8 local_port[0x8]; 8412 u8 reserved_at_10[0x4]; 8413 u8 admin_status[0x4]; 8414 u8 reserved_at_18[0x4]; 8415 u8 oper_status[0x4]; 8416 8417 u8 ase[0x1]; 8418 u8 ee[0x1]; 8419 u8 reserved_at_22[0x1c]; 8420 u8 e[0x2]; 8421 8422 u8 reserved_at_40[0x40]; 8423 }; 8424 8425 struct mlx5_ifc_pamp_reg_bits { 8426 u8 reserved_at_0[0x8]; 8427 u8 opamp_group[0x8]; 8428 u8 reserved_at_10[0xc]; 8429 u8 opamp_group_type[0x4]; 8430 8431 u8 start_index[0x10]; 8432 u8 reserved_at_30[0x4]; 8433 u8 num_of_indices[0xc]; 8434 8435 u8 index_data[18][0x10]; 8436 }; 8437 8438 struct mlx5_ifc_pcmr_reg_bits { 8439 u8 reserved_at_0[0x8]; 8440 u8 local_port[0x8]; 8441 u8 reserved_at_10[0x2e]; 8442 u8 fcs_cap[0x1]; 8443 u8 reserved_at_3f[0x1f]; 8444 u8 fcs_chk[0x1]; 8445 u8 reserved_at_5f[0x1]; 8446 }; 8447 8448 struct mlx5_ifc_lane_2_module_mapping_bits { 8449 u8 reserved_at_0[0x6]; 8450 u8 rx_lane[0x2]; 8451 u8 reserved_at_8[0x6]; 8452 u8 tx_lane[0x2]; 8453 u8 reserved_at_10[0x8]; 8454 u8 module[0x8]; 8455 }; 8456 8457 struct mlx5_ifc_bufferx_reg_bits { 8458 u8 reserved_at_0[0x6]; 8459 u8 lossy[0x1]; 8460 u8 epsb[0x1]; 8461 u8 reserved_at_8[0xc]; 8462 u8 size[0xc]; 8463 8464 u8 xoff_threshold[0x10]; 8465 u8 xon_threshold[0x10]; 8466 }; 8467 8468 struct mlx5_ifc_set_node_in_bits { 8469 u8 node_description[64][0x8]; 8470 }; 8471 8472 struct mlx5_ifc_register_power_settings_bits { 8473 u8 reserved_at_0[0x18]; 8474 u8 power_settings_level[0x8]; 8475 8476 u8 reserved_at_20[0x60]; 8477 }; 8478 8479 struct mlx5_ifc_register_host_endianness_bits { 8480 u8 he[0x1]; 8481 u8 reserved_at_1[0x1f]; 8482 8483 u8 reserved_at_20[0x60]; 8484 }; 8485 8486 struct mlx5_ifc_umr_pointer_desc_argument_bits { 8487 u8 reserved_at_0[0x20]; 8488 8489 u8 mkey[0x20]; 8490 8491 u8 addressh_63_32[0x20]; 8492 8493 u8 addressl_31_0[0x20]; 8494 }; 8495 8496 struct mlx5_ifc_ud_adrs_vector_bits { 8497 u8 dc_key[0x40]; 8498 8499 u8 ext[0x1]; 8500 u8 reserved_at_41[0x7]; 8501 u8 destination_qp_dct[0x18]; 8502 8503 u8 static_rate[0x4]; 8504 u8 sl_eth_prio[0x4]; 8505 u8 fl[0x1]; 8506 u8 mlid[0x7]; 8507 u8 rlid_udp_sport[0x10]; 8508 8509 u8 reserved_at_80[0x20]; 8510 8511 u8 rmac_47_16[0x20]; 8512 8513 u8 rmac_15_0[0x10]; 8514 u8 tclass[0x8]; 8515 u8 hop_limit[0x8]; 8516 8517 u8 reserved_at_e0[0x1]; 8518 u8 grh[0x1]; 8519 u8 reserved_at_e2[0x2]; 8520 u8 src_addr_index[0x8]; 8521 u8 flow_label[0x14]; 8522 8523 u8 rgid_rip[16][0x8]; 8524 }; 8525 8526 struct mlx5_ifc_pages_req_event_bits { 8527 u8 reserved_at_0[0x10]; 8528 u8 function_id[0x10]; 8529 8530 u8 num_pages[0x20]; 8531 8532 u8 reserved_at_40[0xa0]; 8533 }; 8534 8535 struct mlx5_ifc_eqe_bits { 8536 u8 reserved_at_0[0x8]; 8537 u8 event_type[0x8]; 8538 u8 reserved_at_10[0x8]; 8539 u8 event_sub_type[0x8]; 8540 8541 u8 reserved_at_20[0xe0]; 8542 8543 union mlx5_ifc_event_auto_bits event_data; 8544 8545 u8 reserved_at_1e0[0x10]; 8546 u8 signature[0x8]; 8547 u8 reserved_at_1f8[0x7]; 8548 u8 owner[0x1]; 8549 }; 8550 8551 enum { 8552 MLX5_CMD_QUEUE_ENTRY_TYPE_PCIE_CMD_IF_TRANSPORT = 0x7, 8553 }; 8554 8555 struct mlx5_ifc_cmd_queue_entry_bits { 8556 u8 type[0x8]; 8557 u8 reserved_at_8[0x18]; 8558 8559 u8 input_length[0x20]; 8560 8561 u8 input_mailbox_pointer_63_32[0x20]; 8562 8563 u8 input_mailbox_pointer_31_9[0x17]; 8564 u8 reserved_at_77[0x9]; 8565 8566 u8 command_input_inline_data[16][0x8]; 8567 8568 u8 command_output_inline_data[16][0x8]; 8569 8570 u8 output_mailbox_pointer_63_32[0x20]; 8571 8572 u8 output_mailbox_pointer_31_9[0x17]; 8573 u8 reserved_at_1b7[0x9]; 8574 8575 u8 output_length[0x20]; 8576 8577 u8 token[0x8]; 8578 u8 signature[0x8]; 8579 u8 reserved_at_1f0[0x8]; 8580 u8 status[0x7]; 8581 u8 ownership[0x1]; 8582 }; 8583 8584 struct mlx5_ifc_cmd_out_bits { 8585 u8 status[0x8]; 8586 u8 reserved_at_8[0x18]; 8587 8588 u8 syndrome[0x20]; 8589 8590 u8 command_output[0x20]; 8591 }; 8592 8593 struct mlx5_ifc_cmd_in_bits { 8594 u8 opcode[0x10]; 8595 u8 reserved_at_10[0x10]; 8596 8597 u8 reserved_at_20[0x10]; 8598 u8 op_mod[0x10]; 8599 8600 u8 command[0][0x20]; 8601 }; 8602 8603 struct mlx5_ifc_cmd_if_box_bits { 8604 u8 mailbox_data[512][0x8]; 8605 8606 u8 reserved_at_1000[0x180]; 8607 8608 u8 next_pointer_63_32[0x20]; 8609 8610 u8 next_pointer_31_10[0x16]; 8611 u8 reserved_at_11b6[0xa]; 8612 8613 u8 block_number[0x20]; 8614 8615 u8 reserved_at_11e0[0x8]; 8616 u8 token[0x8]; 8617 u8 ctrl_signature[0x8]; 8618 u8 signature[0x8]; 8619 }; 8620 8621 struct mlx5_ifc_mtt_bits { 8622 u8 ptag_63_32[0x20]; 8623 8624 u8 ptag_31_8[0x18]; 8625 u8 reserved_at_38[0x6]; 8626 u8 wr_en[0x1]; 8627 u8 rd_en[0x1]; 8628 }; 8629 8630 struct mlx5_ifc_query_wol_rol_out_bits { 8631 u8 status[0x8]; 8632 u8 reserved_at_8[0x18]; 8633 8634 u8 syndrome[0x20]; 8635 8636 u8 reserved_at_40[0x10]; 8637 u8 rol_mode[0x8]; 8638 u8 wol_mode[0x8]; 8639 8640 u8 reserved_at_60[0x20]; 8641 }; 8642 8643 struct mlx5_ifc_query_wol_rol_in_bits { 8644 u8 opcode[0x10]; 8645 u8 reserved_at_10[0x10]; 8646 8647 u8 reserved_at_20[0x10]; 8648 u8 op_mod[0x10]; 8649 8650 u8 reserved_at_40[0x40]; 8651 }; 8652 8653 struct mlx5_ifc_set_wol_rol_out_bits { 8654 u8 status[0x8]; 8655 u8 reserved_at_8[0x18]; 8656 8657 u8 syndrome[0x20]; 8658 8659 u8 reserved_at_40[0x40]; 8660 }; 8661 8662 struct mlx5_ifc_set_wol_rol_in_bits { 8663 u8 opcode[0x10]; 8664 u8 reserved_at_10[0x10]; 8665 8666 u8 reserved_at_20[0x10]; 8667 u8 op_mod[0x10]; 8668 8669 u8 rol_mode_valid[0x1]; 8670 u8 wol_mode_valid[0x1]; 8671 u8 reserved_at_42[0xe]; 8672 u8 rol_mode[0x8]; 8673 u8 wol_mode[0x8]; 8674 8675 u8 reserved_at_60[0x20]; 8676 }; 8677 8678 enum { 8679 MLX5_INITIAL_SEG_NIC_INTERFACE_FULL_DRIVER = 0x0, 8680 MLX5_INITIAL_SEG_NIC_INTERFACE_DISABLED = 0x1, 8681 MLX5_INITIAL_SEG_NIC_INTERFACE_NO_DRAM_NIC = 0x2, 8682 }; 8683 8684 enum { 8685 MLX5_INITIAL_SEG_NIC_INTERFACE_SUPPORTED_FULL_DRIVER = 0x0, 8686 MLX5_INITIAL_SEG_NIC_INTERFACE_SUPPORTED_DISABLED = 0x1, 8687 MLX5_INITIAL_SEG_NIC_INTERFACE_SUPPORTED_NO_DRAM_NIC = 0x2, 8688 }; 8689 8690 enum { 8691 MLX5_INITIAL_SEG_HEALTH_SYNDROME_FW_INTERNAL_ERR = 0x1, 8692 MLX5_INITIAL_SEG_HEALTH_SYNDROME_DEAD_IRISC = 0x7, 8693 MLX5_INITIAL_SEG_HEALTH_SYNDROME_HW_FATAL_ERR = 0x8, 8694 MLX5_INITIAL_SEG_HEALTH_SYNDROME_FW_CRC_ERR = 0x9, 8695 MLX5_INITIAL_SEG_HEALTH_SYNDROME_ICM_FETCH_PCI_ERR = 0xa, 8696 MLX5_INITIAL_SEG_HEALTH_SYNDROME_ICM_PAGE_ERR = 0xb, 8697 MLX5_INITIAL_SEG_HEALTH_SYNDROME_ASYNCHRONOUS_EQ_BUF_OVERRUN = 0xc, 8698 MLX5_INITIAL_SEG_HEALTH_SYNDROME_EQ_IN_ERR = 0xd, 8699 MLX5_INITIAL_SEG_HEALTH_SYNDROME_EQ_INV = 0xe, 8700 MLX5_INITIAL_SEG_HEALTH_SYNDROME_FFSER_ERR = 0xf, 8701 MLX5_INITIAL_SEG_HEALTH_SYNDROME_HIGH_TEMP_ERR = 0x10, 8702 }; 8703 8704 struct mlx5_ifc_initial_seg_bits { 8705 u8 fw_rev_minor[0x10]; 8706 u8 fw_rev_major[0x10]; 8707 8708 u8 cmd_interface_rev[0x10]; 8709 u8 fw_rev_subminor[0x10]; 8710 8711 u8 reserved_at_40[0x40]; 8712 8713 u8 cmdq_phy_addr_63_32[0x20]; 8714 8715 u8 cmdq_phy_addr_31_12[0x14]; 8716 u8 reserved_at_b4[0x2]; 8717 u8 nic_interface[0x2]; 8718 u8 log_cmdq_size[0x4]; 8719 u8 log_cmdq_stride[0x4]; 8720 8721 u8 command_doorbell_vector[0x20]; 8722 8723 u8 reserved_at_e0[0xf00]; 8724 8725 u8 initializing[0x1]; 8726 u8 reserved_at_fe1[0x4]; 8727 u8 nic_interface_supported[0x3]; 8728 u8 reserved_at_fe8[0x18]; 8729 8730 struct mlx5_ifc_health_buffer_bits health_buffer; 8731 8732 u8 no_dram_nic_offset[0x20]; 8733 8734 u8 reserved_at_1220[0x6e40]; 8735 8736 u8 reserved_at_8060[0x1f]; 8737 u8 clear_int[0x1]; 8738 8739 u8 health_syndrome[0x8]; 8740 u8 health_counter[0x18]; 8741 8742 u8 reserved_at_80a0[0x17fc0]; 8743 }; 8744 8745 struct mlx5_ifc_mtpps_reg_bits { 8746 u8 reserved_at_0[0xc]; 8747 u8 cap_number_of_pps_pins[0x4]; 8748 u8 reserved_at_10[0x4]; 8749 u8 cap_max_num_of_pps_in_pins[0x4]; 8750 u8 reserved_at_18[0x4]; 8751 u8 cap_max_num_of_pps_out_pins[0x4]; 8752 8753 u8 reserved_at_20[0x24]; 8754 u8 cap_pin_3_mode[0x4]; 8755 u8 reserved_at_48[0x4]; 8756 u8 cap_pin_2_mode[0x4]; 8757 u8 reserved_at_50[0x4]; 8758 u8 cap_pin_1_mode[0x4]; 8759 u8 reserved_at_58[0x4]; 8760 u8 cap_pin_0_mode[0x4]; 8761 8762 u8 reserved_at_60[0x4]; 8763 u8 cap_pin_7_mode[0x4]; 8764 u8 reserved_at_68[0x4]; 8765 u8 cap_pin_6_mode[0x4]; 8766 u8 reserved_at_70[0x4]; 8767 u8 cap_pin_5_mode[0x4]; 8768 u8 reserved_at_78[0x4]; 8769 u8 cap_pin_4_mode[0x4]; 8770 8771 u8 field_select[0x20]; 8772 u8 reserved_at_a0[0x60]; 8773 8774 u8 enable[0x1]; 8775 u8 reserved_at_101[0xb]; 8776 u8 pattern[0x4]; 8777 u8 reserved_at_110[0x4]; 8778 u8 pin_mode[0x4]; 8779 u8 pin[0x8]; 8780 8781 u8 reserved_at_120[0x20]; 8782 8783 u8 time_stamp[0x40]; 8784 8785 u8 out_pulse_duration[0x10]; 8786 u8 out_periodic_adjustment[0x10]; 8787 u8 enhanced_out_periodic_adjustment[0x20]; 8788 8789 u8 reserved_at_1c0[0x20]; 8790 }; 8791 8792 struct mlx5_ifc_mtppse_reg_bits { 8793 u8 reserved_at_0[0x18]; 8794 u8 pin[0x8]; 8795 u8 event_arm[0x1]; 8796 u8 reserved_at_21[0x1b]; 8797 u8 event_generation_mode[0x4]; 8798 u8 reserved_at_40[0x40]; 8799 }; 8800 8801 struct mlx5_ifc_mcqi_cap_bits { 8802 u8 supported_info_bitmask[0x20]; 8803 8804 u8 component_size[0x20]; 8805 8806 u8 max_component_size[0x20]; 8807 8808 u8 log_mcda_word_size[0x4]; 8809 u8 reserved_at_64[0xc]; 8810 u8 mcda_max_write_size[0x10]; 8811 8812 u8 rd_en[0x1]; 8813 u8 reserved_at_81[0x1]; 8814 u8 match_chip_id[0x1]; 8815 u8 match_psid[0x1]; 8816 u8 check_user_timestamp[0x1]; 8817 u8 match_base_guid_mac[0x1]; 8818 u8 reserved_at_86[0x1a]; 8819 }; 8820 8821 struct mlx5_ifc_mcqi_reg_bits { 8822 u8 read_pending_component[0x1]; 8823 u8 reserved_at_1[0xf]; 8824 u8 component_index[0x10]; 8825 8826 u8 reserved_at_20[0x20]; 8827 8828 u8 reserved_at_40[0x1b]; 8829 u8 info_type[0x5]; 8830 8831 u8 info_size[0x20]; 8832 8833 u8 offset[0x20]; 8834 8835 u8 reserved_at_a0[0x10]; 8836 u8 data_size[0x10]; 8837 8838 u8 data[0][0x20]; 8839 }; 8840 8841 struct mlx5_ifc_mcc_reg_bits { 8842 u8 reserved_at_0[0x4]; 8843 u8 time_elapsed_since_last_cmd[0xc]; 8844 u8 reserved_at_10[0x8]; 8845 u8 instruction[0x8]; 8846 8847 u8 reserved_at_20[0x10]; 8848 u8 component_index[0x10]; 8849 8850 u8 reserved_at_40[0x8]; 8851 u8 update_handle[0x18]; 8852 8853 u8 handle_owner_type[0x4]; 8854 u8 handle_owner_host_id[0x4]; 8855 u8 reserved_at_68[0x1]; 8856 u8 control_progress[0x7]; 8857 u8 error_code[0x8]; 8858 u8 reserved_at_78[0x4]; 8859 u8 control_state[0x4]; 8860 8861 u8 component_size[0x20]; 8862 8863 u8 reserved_at_a0[0x60]; 8864 }; 8865 8866 struct mlx5_ifc_mcda_reg_bits { 8867 u8 reserved_at_0[0x8]; 8868 u8 update_handle[0x18]; 8869 8870 u8 offset[0x20]; 8871 8872 u8 reserved_at_40[0x10]; 8873 u8 size[0x10]; 8874 8875 u8 reserved_at_60[0x20]; 8876 8877 u8 data[0][0x20]; 8878 }; 8879 8880 union mlx5_ifc_ports_control_registers_document_bits { 8881 struct mlx5_ifc_bufferx_reg_bits bufferx_reg; 8882 struct mlx5_ifc_eth_2819_cntrs_grp_data_layout_bits eth_2819_cntrs_grp_data_layout; 8883 struct mlx5_ifc_eth_2863_cntrs_grp_data_layout_bits eth_2863_cntrs_grp_data_layout; 8884 struct mlx5_ifc_eth_3635_cntrs_grp_data_layout_bits eth_3635_cntrs_grp_data_layout; 8885 struct mlx5_ifc_eth_802_3_cntrs_grp_data_layout_bits eth_802_3_cntrs_grp_data_layout; 8886 struct mlx5_ifc_eth_extended_cntrs_grp_data_layout_bits eth_extended_cntrs_grp_data_layout; 8887 struct mlx5_ifc_eth_per_prio_grp_data_layout_bits eth_per_prio_grp_data_layout; 8888 struct mlx5_ifc_eth_per_traffic_grp_data_layout_bits eth_per_traffic_grp_data_layout; 8889 struct mlx5_ifc_lane_2_module_mapping_bits lane_2_module_mapping; 8890 struct mlx5_ifc_pamp_reg_bits pamp_reg; 8891 struct mlx5_ifc_paos_reg_bits paos_reg; 8892 struct mlx5_ifc_pcap_reg_bits pcap_reg; 8893 struct mlx5_ifc_peir_reg_bits peir_reg; 8894 struct mlx5_ifc_pelc_reg_bits pelc_reg; 8895 struct mlx5_ifc_pfcc_reg_bits pfcc_reg; 8896 struct mlx5_ifc_ib_port_cntrs_grp_data_layout_bits ib_port_cntrs_grp_data_layout; 8897 struct mlx5_ifc_phys_layer_cntrs_bits phys_layer_cntrs; 8898 struct mlx5_ifc_pifr_reg_bits pifr_reg; 8899 struct mlx5_ifc_pipg_reg_bits pipg_reg; 8900 struct mlx5_ifc_plbf_reg_bits plbf_reg; 8901 struct mlx5_ifc_plib_reg_bits plib_reg; 8902 struct mlx5_ifc_plpc_reg_bits plpc_reg; 8903 struct mlx5_ifc_pmaos_reg_bits pmaos_reg; 8904 struct mlx5_ifc_pmlp_reg_bits pmlp_reg; 8905 struct mlx5_ifc_pmlpn_reg_bits pmlpn_reg; 8906 struct mlx5_ifc_pmpc_reg_bits pmpc_reg; 8907 struct mlx5_ifc_pmpe_reg_bits pmpe_reg; 8908 struct mlx5_ifc_pmpr_reg_bits pmpr_reg; 8909 struct mlx5_ifc_pmtu_reg_bits pmtu_reg; 8910 struct mlx5_ifc_ppad_reg_bits ppad_reg; 8911 struct mlx5_ifc_ppcnt_reg_bits ppcnt_reg; 8912 struct mlx5_ifc_mpcnt_reg_bits mpcnt_reg; 8913 struct mlx5_ifc_pplm_reg_bits pplm_reg; 8914 struct mlx5_ifc_pplr_reg_bits pplr_reg; 8915 struct mlx5_ifc_ppsc_reg_bits ppsc_reg; 8916 struct mlx5_ifc_pqdr_reg_bits pqdr_reg; 8917 struct mlx5_ifc_pspa_reg_bits pspa_reg; 8918 struct mlx5_ifc_ptas_reg_bits ptas_reg; 8919 struct mlx5_ifc_ptys_reg_bits ptys_reg; 8920 struct mlx5_ifc_mlcr_reg_bits mlcr_reg; 8921 struct mlx5_ifc_pude_reg_bits pude_reg; 8922 struct mlx5_ifc_pvlc_reg_bits pvlc_reg; 8923 struct mlx5_ifc_slrg_reg_bits slrg_reg; 8924 struct mlx5_ifc_sltp_reg_bits sltp_reg; 8925 struct mlx5_ifc_mtpps_reg_bits mtpps_reg; 8926 struct mlx5_ifc_mtppse_reg_bits mtppse_reg; 8927 struct mlx5_ifc_fpga_access_reg_bits fpga_access_reg; 8928 struct mlx5_ifc_fpga_ctrl_bits fpga_ctrl_bits; 8929 struct mlx5_ifc_fpga_cap_bits fpga_cap_bits; 8930 struct mlx5_ifc_mcqi_reg_bits mcqi_reg; 8931 struct mlx5_ifc_mcc_reg_bits mcc_reg; 8932 struct mlx5_ifc_mcda_reg_bits mcda_reg; 8933 u8 reserved_at_0[0x60e0]; 8934 }; 8935 8936 union mlx5_ifc_debug_enhancements_document_bits { 8937 struct mlx5_ifc_health_buffer_bits health_buffer; 8938 u8 reserved_at_0[0x200]; 8939 }; 8940 8941 union mlx5_ifc_uplink_pci_interface_document_bits { 8942 struct mlx5_ifc_initial_seg_bits initial_seg; 8943 u8 reserved_at_0[0x20060]; 8944 }; 8945 8946 struct mlx5_ifc_set_flow_table_root_out_bits { 8947 u8 status[0x8]; 8948 u8 reserved_at_8[0x18]; 8949 8950 u8 syndrome[0x20]; 8951 8952 u8 reserved_at_40[0x40]; 8953 }; 8954 8955 struct mlx5_ifc_set_flow_table_root_in_bits { 8956 u8 opcode[0x10]; 8957 u8 reserved_at_10[0x10]; 8958 8959 u8 reserved_at_20[0x10]; 8960 u8 op_mod[0x10]; 8961 8962 u8 other_vport[0x1]; 8963 u8 reserved_at_41[0xf]; 8964 u8 vport_number[0x10]; 8965 8966 u8 reserved_at_60[0x20]; 8967 8968 u8 table_type[0x8]; 8969 u8 reserved_at_88[0x18]; 8970 8971 u8 reserved_at_a0[0x8]; 8972 u8 table_id[0x18]; 8973 8974 u8 reserved_at_c0[0x8]; 8975 u8 underlay_qpn[0x18]; 8976 u8 reserved_at_e0[0x120]; 8977 }; 8978 8979 enum { 8980 MLX5_MODIFY_FLOW_TABLE_MISS_TABLE_ID = (1UL << 0), 8981 MLX5_MODIFY_FLOW_TABLE_LAG_NEXT_TABLE_ID = (1UL << 15), 8982 }; 8983 8984 struct mlx5_ifc_modify_flow_table_out_bits { 8985 u8 status[0x8]; 8986 u8 reserved_at_8[0x18]; 8987 8988 u8 syndrome[0x20]; 8989 8990 u8 reserved_at_40[0x40]; 8991 }; 8992 8993 struct mlx5_ifc_modify_flow_table_in_bits { 8994 u8 opcode[0x10]; 8995 u8 reserved_at_10[0x10]; 8996 8997 u8 reserved_at_20[0x10]; 8998 u8 op_mod[0x10]; 8999 9000 u8 other_vport[0x1]; 9001 u8 reserved_at_41[0xf]; 9002 u8 vport_number[0x10]; 9003 9004 u8 reserved_at_60[0x10]; 9005 u8 modify_field_select[0x10]; 9006 9007 u8 table_type[0x8]; 9008 u8 reserved_at_88[0x18]; 9009 9010 u8 reserved_at_a0[0x8]; 9011 u8 table_id[0x18]; 9012 9013 struct mlx5_ifc_flow_table_context_bits flow_table_context; 9014 }; 9015 9016 struct mlx5_ifc_ets_tcn_config_reg_bits { 9017 u8 g[0x1]; 9018 u8 b[0x1]; 9019 u8 r[0x1]; 9020 u8 reserved_at_3[0x9]; 9021 u8 group[0x4]; 9022 u8 reserved_at_10[0x9]; 9023 u8 bw_allocation[0x7]; 9024 9025 u8 reserved_at_20[0xc]; 9026 u8 max_bw_units[0x4]; 9027 u8 reserved_at_30[0x8]; 9028 u8 max_bw_value[0x8]; 9029 }; 9030 9031 struct mlx5_ifc_ets_global_config_reg_bits { 9032 u8 reserved_at_0[0x2]; 9033 u8 r[0x1]; 9034 u8 reserved_at_3[0x1d]; 9035 9036 u8 reserved_at_20[0xc]; 9037 u8 max_bw_units[0x4]; 9038 u8 reserved_at_30[0x8]; 9039 u8 max_bw_value[0x8]; 9040 }; 9041 9042 struct mlx5_ifc_qetc_reg_bits { 9043 u8 reserved_at_0[0x8]; 9044 u8 port_number[0x8]; 9045 u8 reserved_at_10[0x30]; 9046 9047 struct mlx5_ifc_ets_tcn_config_reg_bits tc_configuration[0x8]; 9048 struct mlx5_ifc_ets_global_config_reg_bits global_configuration; 9049 }; 9050 9051 struct mlx5_ifc_qpdpm_dscp_reg_bits { 9052 u8 e[0x1]; 9053 u8 reserved_at_01[0x0b]; 9054 u8 prio[0x04]; 9055 }; 9056 9057 struct mlx5_ifc_qpdpm_reg_bits { 9058 u8 reserved_at_0[0x8]; 9059 u8 local_port[0x8]; 9060 u8 reserved_at_10[0x10]; 9061 struct mlx5_ifc_qpdpm_dscp_reg_bits dscp[64]; 9062 }; 9063 9064 struct mlx5_ifc_qpts_reg_bits { 9065 u8 reserved_at_0[0x8]; 9066 u8 local_port[0x8]; 9067 u8 reserved_at_10[0x2d]; 9068 u8 trust_state[0x3]; 9069 }; 9070 9071 struct mlx5_ifc_pptb_reg_bits { 9072 u8 reserved_at_0[0x2]; 9073 u8 mm[0x2]; 9074 u8 reserved_at_4[0x4]; 9075 u8 local_port[0x8]; 9076 u8 reserved_at_10[0x6]; 9077 u8 cm[0x1]; 9078 u8 um[0x1]; 9079 u8 pm[0x8]; 9080 9081 u8 prio_x_buff[0x20]; 9082 9083 u8 pm_msb[0x8]; 9084 u8 reserved_at_48[0x10]; 9085 u8 ctrl_buff[0x4]; 9086 u8 untagged_buff[0x4]; 9087 }; 9088 9089 struct mlx5_ifc_pbmc_reg_bits { 9090 u8 reserved_at_0[0x8]; 9091 u8 local_port[0x8]; 9092 u8 reserved_at_10[0x10]; 9093 9094 u8 xoff_timer_value[0x10]; 9095 u8 xoff_refresh[0x10]; 9096 9097 u8 reserved_at_40[0x9]; 9098 u8 fullness_threshold[0x7]; 9099 u8 port_buffer_size[0x10]; 9100 9101 struct mlx5_ifc_bufferx_reg_bits buffer[10]; 9102 9103 u8 reserved_at_2e0[0x40]; 9104 }; 9105 9106 struct mlx5_ifc_qtct_reg_bits { 9107 u8 reserved_at_0[0x8]; 9108 u8 port_number[0x8]; 9109 u8 reserved_at_10[0xd]; 9110 u8 prio[0x3]; 9111 9112 u8 reserved_at_20[0x1d]; 9113 u8 tclass[0x3]; 9114 }; 9115 9116 struct mlx5_ifc_mcia_reg_bits { 9117 u8 l[0x1]; 9118 u8 reserved_at_1[0x7]; 9119 u8 module[0x8]; 9120 u8 reserved_at_10[0x8]; 9121 u8 status[0x8]; 9122 9123 u8 i2c_device_address[0x8]; 9124 u8 page_number[0x8]; 9125 u8 device_address[0x10]; 9126 9127 u8 reserved_at_40[0x10]; 9128 u8 size[0x10]; 9129 9130 u8 reserved_at_60[0x20]; 9131 9132 u8 dword_0[0x20]; 9133 u8 dword_1[0x20]; 9134 u8 dword_2[0x20]; 9135 u8 dword_3[0x20]; 9136 u8 dword_4[0x20]; 9137 u8 dword_5[0x20]; 9138 u8 dword_6[0x20]; 9139 u8 dword_7[0x20]; 9140 u8 dword_8[0x20]; 9141 u8 dword_9[0x20]; 9142 u8 dword_10[0x20]; 9143 u8 dword_11[0x20]; 9144 }; 9145 9146 struct mlx5_ifc_dcbx_param_bits { 9147 u8 dcbx_cee_cap[0x1]; 9148 u8 dcbx_ieee_cap[0x1]; 9149 u8 dcbx_standby_cap[0x1]; 9150 u8 reserved_at_3[0x5]; 9151 u8 port_number[0x8]; 9152 u8 reserved_at_10[0xa]; 9153 u8 max_application_table_size[6]; 9154 u8 reserved_at_20[0x15]; 9155 u8 version_oper[0x3]; 9156 u8 reserved_at_38[5]; 9157 u8 version_admin[0x3]; 9158 u8 willing_admin[0x1]; 9159 u8 reserved_at_41[0x3]; 9160 u8 pfc_cap_oper[0x4]; 9161 u8 reserved_at_48[0x4]; 9162 u8 pfc_cap_admin[0x4]; 9163 u8 reserved_at_50[0x4]; 9164 u8 num_of_tc_oper[0x4]; 9165 u8 reserved_at_58[0x4]; 9166 u8 num_of_tc_admin[0x4]; 9167 u8 remote_willing[0x1]; 9168 u8 reserved_at_61[3]; 9169 u8 remote_pfc_cap[4]; 9170 u8 reserved_at_68[0x14]; 9171 u8 remote_num_of_tc[0x4]; 9172 u8 reserved_at_80[0x18]; 9173 u8 error[0x8]; 9174 u8 reserved_at_a0[0x160]; 9175 }; 9176 9177 struct mlx5_ifc_lagc_bits { 9178 u8 reserved_at_0[0x1d]; 9179 u8 lag_state[0x3]; 9180 9181 u8 reserved_at_20[0x14]; 9182 u8 tx_remap_affinity_2[0x4]; 9183 u8 reserved_at_38[0x4]; 9184 u8 tx_remap_affinity_1[0x4]; 9185 }; 9186 9187 struct mlx5_ifc_create_lag_out_bits { 9188 u8 status[0x8]; 9189 u8 reserved_at_8[0x18]; 9190 9191 u8 syndrome[0x20]; 9192 9193 u8 reserved_at_40[0x40]; 9194 }; 9195 9196 struct mlx5_ifc_create_lag_in_bits { 9197 u8 opcode[0x10]; 9198 u8 reserved_at_10[0x10]; 9199 9200 u8 reserved_at_20[0x10]; 9201 u8 op_mod[0x10]; 9202 9203 struct mlx5_ifc_lagc_bits ctx; 9204 }; 9205 9206 struct mlx5_ifc_modify_lag_out_bits { 9207 u8 status[0x8]; 9208 u8 reserved_at_8[0x18]; 9209 9210 u8 syndrome[0x20]; 9211 9212 u8 reserved_at_40[0x40]; 9213 }; 9214 9215 struct mlx5_ifc_modify_lag_in_bits { 9216 u8 opcode[0x10]; 9217 u8 reserved_at_10[0x10]; 9218 9219 u8 reserved_at_20[0x10]; 9220 u8 op_mod[0x10]; 9221 9222 u8 reserved_at_40[0x20]; 9223 u8 field_select[0x20]; 9224 9225 struct mlx5_ifc_lagc_bits ctx; 9226 }; 9227 9228 struct mlx5_ifc_query_lag_out_bits { 9229 u8 status[0x8]; 9230 u8 reserved_at_8[0x18]; 9231 9232 u8 syndrome[0x20]; 9233 9234 u8 reserved_at_40[0x40]; 9235 9236 struct mlx5_ifc_lagc_bits ctx; 9237 }; 9238 9239 struct mlx5_ifc_query_lag_in_bits { 9240 u8 opcode[0x10]; 9241 u8 reserved_at_10[0x10]; 9242 9243 u8 reserved_at_20[0x10]; 9244 u8 op_mod[0x10]; 9245 9246 u8 reserved_at_40[0x40]; 9247 }; 9248 9249 struct mlx5_ifc_destroy_lag_out_bits { 9250 u8 status[0x8]; 9251 u8 reserved_at_8[0x18]; 9252 9253 u8 syndrome[0x20]; 9254 9255 u8 reserved_at_40[0x40]; 9256 }; 9257 9258 struct mlx5_ifc_destroy_lag_in_bits { 9259 u8 opcode[0x10]; 9260 u8 reserved_at_10[0x10]; 9261 9262 u8 reserved_at_20[0x10]; 9263 u8 op_mod[0x10]; 9264 9265 u8 reserved_at_40[0x40]; 9266 }; 9267 9268 struct mlx5_ifc_create_vport_lag_out_bits { 9269 u8 status[0x8]; 9270 u8 reserved_at_8[0x18]; 9271 9272 u8 syndrome[0x20]; 9273 9274 u8 reserved_at_40[0x40]; 9275 }; 9276 9277 struct mlx5_ifc_create_vport_lag_in_bits { 9278 u8 opcode[0x10]; 9279 u8 reserved_at_10[0x10]; 9280 9281 u8 reserved_at_20[0x10]; 9282 u8 op_mod[0x10]; 9283 9284 u8 reserved_at_40[0x40]; 9285 }; 9286 9287 struct mlx5_ifc_destroy_vport_lag_out_bits { 9288 u8 status[0x8]; 9289 u8 reserved_at_8[0x18]; 9290 9291 u8 syndrome[0x20]; 9292 9293 u8 reserved_at_40[0x40]; 9294 }; 9295 9296 struct mlx5_ifc_destroy_vport_lag_in_bits { 9297 u8 opcode[0x10]; 9298 u8 reserved_at_10[0x10]; 9299 9300 u8 reserved_at_20[0x10]; 9301 u8 op_mod[0x10]; 9302 9303 u8 reserved_at_40[0x40]; 9304 }; 9305 9306 struct mlx5_ifc_alloc_memic_in_bits { 9307 u8 opcode[0x10]; 9308 u8 reserved_at_10[0x10]; 9309 9310 u8 reserved_at_20[0x10]; 9311 u8 op_mod[0x10]; 9312 9313 u8 reserved_at_30[0x20]; 9314 9315 u8 reserved_at_40[0x18]; 9316 u8 log_memic_addr_alignment[0x8]; 9317 9318 u8 range_start_addr[0x40]; 9319 9320 u8 range_size[0x20]; 9321 9322 u8 memic_size[0x20]; 9323 }; 9324 9325 struct mlx5_ifc_alloc_memic_out_bits { 9326 u8 status[0x8]; 9327 u8 reserved_at_8[0x18]; 9328 9329 u8 syndrome[0x20]; 9330 9331 u8 memic_start_addr[0x40]; 9332 }; 9333 9334 struct mlx5_ifc_dealloc_memic_in_bits { 9335 u8 opcode[0x10]; 9336 u8 reserved_at_10[0x10]; 9337 9338 u8 reserved_at_20[0x10]; 9339 u8 op_mod[0x10]; 9340 9341 u8 reserved_at_40[0x40]; 9342 9343 u8 memic_start_addr[0x40]; 9344 9345 u8 memic_size[0x20]; 9346 9347 u8 reserved_at_e0[0x20]; 9348 }; 9349 9350 struct mlx5_ifc_dealloc_memic_out_bits { 9351 u8 status[0x8]; 9352 u8 reserved_at_8[0x18]; 9353 9354 u8 syndrome[0x20]; 9355 9356 u8 reserved_at_40[0x40]; 9357 }; 9358 9359 struct mlx5_ifc_general_obj_in_cmd_hdr_bits { 9360 u8 opcode[0x10]; 9361 u8 uid[0x10]; 9362 9363 u8 reserved_at_20[0x10]; 9364 u8 obj_type[0x10]; 9365 9366 u8 obj_id[0x20]; 9367 9368 u8 reserved_at_60[0x20]; 9369 }; 9370 9371 struct mlx5_ifc_general_obj_out_cmd_hdr_bits { 9372 u8 status[0x8]; 9373 u8 reserved_at_8[0x18]; 9374 9375 u8 syndrome[0x20]; 9376 9377 u8 obj_id[0x20]; 9378 9379 u8 reserved_at_60[0x20]; 9380 }; 9381 9382 struct mlx5_ifc_umem_bits { 9383 u8 modify_field_select[0x40]; 9384 9385 u8 reserved_at_40[0x5b]; 9386 u8 log_page_size[0x5]; 9387 9388 u8 page_offset[0x20]; 9389 9390 u8 num_of_mtt[0x40]; 9391 9392 struct mlx5_ifc_mtt_bits mtt[0]; 9393 }; 9394 9395 struct mlx5_ifc_uctx_bits { 9396 u8 modify_field_select[0x40]; 9397 9398 u8 cap[0x20]; 9399 9400 u8 reserved_at_60[0x1a0]; 9401 }; 9402 9403 struct mlx5_ifc_create_umem_in_bits { 9404 struct mlx5_ifc_general_obj_in_cmd_hdr_bits hdr; 9405 struct mlx5_ifc_umem_bits umem; 9406 }; 9407 9408 struct mlx5_ifc_create_uctx_in_bits { 9409 struct mlx5_ifc_general_obj_in_cmd_hdr_bits hdr; 9410 struct mlx5_ifc_uctx_bits uctx; 9411 }; 9412 9413 struct mlx5_ifc_mtrc_string_db_param_bits { 9414 u8 string_db_base_address[0x20]; 9415 9416 u8 reserved_at_20[0x8]; 9417 u8 string_db_size[0x18]; 9418 }; 9419 9420 struct mlx5_ifc_mtrc_cap_bits { 9421 u8 trace_owner[0x1]; 9422 u8 trace_to_memory[0x1]; 9423 u8 reserved_at_2[0x4]; 9424 u8 trc_ver[0x2]; 9425 u8 reserved_at_8[0x14]; 9426 u8 num_string_db[0x4]; 9427 9428 u8 first_string_trace[0x8]; 9429 u8 num_string_trace[0x8]; 9430 u8 reserved_at_30[0x28]; 9431 9432 u8 log_max_trace_buffer_size[0x8]; 9433 9434 u8 reserved_at_60[0x20]; 9435 9436 struct mlx5_ifc_mtrc_string_db_param_bits string_db_param[8]; 9437 9438 u8 reserved_at_280[0x180]; 9439 }; 9440 9441 struct mlx5_ifc_mtrc_conf_bits { 9442 u8 reserved_at_0[0x1c]; 9443 u8 trace_mode[0x4]; 9444 u8 reserved_at_20[0x18]; 9445 u8 log_trace_buffer_size[0x8]; 9446 u8 trace_mkey[0x20]; 9447 u8 reserved_at_60[0x3a0]; 9448 }; 9449 9450 struct mlx5_ifc_mtrc_stdb_bits { 9451 u8 string_db_index[0x4]; 9452 u8 reserved_at_4[0x4]; 9453 u8 read_size[0x18]; 9454 u8 start_offset[0x20]; 9455 u8 string_db_data[0]; 9456 }; 9457 9458 struct mlx5_ifc_mtrc_ctrl_bits { 9459 u8 trace_status[0x2]; 9460 u8 reserved_at_2[0x2]; 9461 u8 arm_event[0x1]; 9462 u8 reserved_at_5[0xb]; 9463 u8 modify_field_select[0x10]; 9464 u8 reserved_at_20[0x2b]; 9465 u8 current_timestamp52_32[0x15]; 9466 u8 current_timestamp31_0[0x20]; 9467 u8 reserved_at_80[0x180]; 9468 }; 9469 9470 #endif /* MLX5_IFC_H */ 9471