xref: /linux/include/linux/mlx5/mlx5_ifc.h (revision dea3165f989b259bc1293d9dfc50053223f5f4b2) 
1 /*
2  * Copyright (c) 2013-2015, Mellanox Technologies, Ltd.  All rights reserved.
3  *
4  * This software is available to you under a choice of one of two
5  * licenses.  You may choose to be licensed under the terms of the GNU
6  * General Public License (GPL) Version 2, available from the file
7  * COPYING in the main directory of this source tree, or the
8  * OpenIB.org BSD license below:
9  *
10  *     Redistribution and use in source and binary forms, with or
11  *     without modification, are permitted provided that the following
12  *     conditions are met:
13  *
14  *      - Redistributions of source code must retain the above
15  *        copyright notice, this list of conditions and the following
16  *        disclaimer.
17  *
18  *      - Redistributions in binary form must reproduce the above
19  *        copyright notice, this list of conditions and the following
20  *        disclaimer in the documentation and/or other materials
21  *        provided with the distribution.
22  *
23  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
24  * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
25  * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
26  * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
27  * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
28  * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
29  * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
30  * SOFTWARE.
31 */
32 #ifndef MLX5_IFC_H
33 #define MLX5_IFC_H
34 
35 #include "mlx5_ifc_fpga.h"
36 
37 enum {
38 	MLX5_EVENT_TYPE_CODING_COMPLETION_EVENTS                   = 0x0,
39 	MLX5_EVENT_TYPE_CODING_PATH_MIGRATED_SUCCEEDED             = 0x1,
40 	MLX5_EVENT_TYPE_CODING_COMMUNICATION_ESTABLISHED           = 0x2,
41 	MLX5_EVENT_TYPE_CODING_SEND_QUEUE_DRAINED                  = 0x3,
42 	MLX5_EVENT_TYPE_CODING_LAST_WQE_REACHED                    = 0x13,
43 	MLX5_EVENT_TYPE_CODING_SRQ_LIMIT                           = 0x14,
44 	MLX5_EVENT_TYPE_CODING_DCT_ALL_CONNECTIONS_CLOSED          = 0x1c,
45 	MLX5_EVENT_TYPE_CODING_DCT_ACCESS_KEY_VIOLATION            = 0x1d,
46 	MLX5_EVENT_TYPE_CODING_CQ_ERROR                            = 0x4,
47 	MLX5_EVENT_TYPE_CODING_LOCAL_WQ_CATASTROPHIC_ERROR         = 0x5,
48 	MLX5_EVENT_TYPE_CODING_PATH_MIGRATION_FAILED               = 0x7,
49 	MLX5_EVENT_TYPE_CODING_PAGE_FAULT_EVENT                    = 0xc,
50 	MLX5_EVENT_TYPE_CODING_INVALID_REQUEST_LOCAL_WQ_ERROR      = 0x10,
51 	MLX5_EVENT_TYPE_CODING_LOCAL_ACCESS_VIOLATION_WQ_ERROR     = 0x11,
52 	MLX5_EVENT_TYPE_CODING_LOCAL_SRQ_CATASTROPHIC_ERROR        = 0x12,
53 	MLX5_EVENT_TYPE_CODING_INTERNAL_ERROR                      = 0x8,
54 	MLX5_EVENT_TYPE_CODING_PORT_STATE_CHANGE                   = 0x9,
55 	MLX5_EVENT_TYPE_CODING_GPIO_EVENT                          = 0x15,
56 	MLX5_EVENT_TYPE_CODING_REMOTE_CONFIGURATION_PROTOCOL_EVENT = 0x19,
57 	MLX5_EVENT_TYPE_CODING_DOORBELL_BLUEFLAME_CONGESTION_EVENT = 0x1a,
58 	MLX5_EVENT_TYPE_CODING_STALL_VL_EVENT                      = 0x1b,
59 	MLX5_EVENT_TYPE_CODING_DROPPED_PACKET_LOGGED_EVENT         = 0x1f,
60 	MLX5_EVENT_TYPE_CODING_COMMAND_INTERFACE_COMPLETION        = 0xa,
61 	MLX5_EVENT_TYPE_CODING_PAGE_REQUEST                        = 0xb,
62 	MLX5_EVENT_TYPE_CODING_FPGA_ERROR                          = 0x20,
63 	MLX5_EVENT_TYPE_CODING_FPGA_QP_ERROR                       = 0x21
64 };
65 
66 enum {
67 	MLX5_SET_HCA_CAP_OP_MOD_GENERAL_DEVICE        = 0x0,
68 	MLX5_SET_HCA_CAP_OP_MOD_ETHERNET_OFFLOADS     = 0x1,
69 	MLX5_SET_HCA_CAP_OP_MOD_ODP                   = 0x2,
70 	MLX5_SET_HCA_CAP_OP_MOD_ATOMIC                = 0x3,
71 	MLX5_SET_HCA_CAP_OP_MOD_ROCE                  = 0x4,
72 	MLX5_SET_HCA_CAP_OP_MOD_IPSEC                 = 0x15,
73 	MLX5_SET_HCA_CAP_OP_MOD_GENERAL_DEVICE2       = 0x20,
74 	MLX5_SET_HCA_CAP_OP_MOD_PORT_SELECTION        = 0x25,
75 };
76 
77 enum {
78 	MLX5_SHARED_RESOURCE_UID = 0xffff,
79 };
80 
81 enum {
82 	MLX5_OBJ_TYPE_SW_ICM = 0x0008,
83 	MLX5_OBJ_TYPE_GENEVE_TLV_OPT = 0x000b,
84 	MLX5_OBJ_TYPE_VIRTIO_NET_Q = 0x000d,
85 	MLX5_OBJ_TYPE_VIRTIO_Q_COUNTERS = 0x001c,
86 	MLX5_OBJ_TYPE_MATCH_DEFINER = 0x0018,
87 	MLX5_OBJ_TYPE_HEADER_MODIFY_ARGUMENT  = 0x23,
88 	MLX5_OBJ_TYPE_STC = 0x0040,
89 	MLX5_OBJ_TYPE_RTC = 0x0041,
90 	MLX5_OBJ_TYPE_STE = 0x0042,
91 	MLX5_OBJ_TYPE_MODIFY_HDR_PATTERN = 0x0043,
92 	MLX5_OBJ_TYPE_PAGE_TRACK = 0x46,
93 	MLX5_OBJ_TYPE_MKEY = 0xff01,
94 	MLX5_OBJ_TYPE_QP = 0xff02,
95 	MLX5_OBJ_TYPE_PSV = 0xff03,
96 	MLX5_OBJ_TYPE_RMP = 0xff04,
97 	MLX5_OBJ_TYPE_XRC_SRQ = 0xff05,
98 	MLX5_OBJ_TYPE_RQ = 0xff06,
99 	MLX5_OBJ_TYPE_SQ = 0xff07,
100 	MLX5_OBJ_TYPE_TIR = 0xff08,
101 	MLX5_OBJ_TYPE_TIS = 0xff09,
102 	MLX5_OBJ_TYPE_DCT = 0xff0a,
103 	MLX5_OBJ_TYPE_XRQ = 0xff0b,
104 	MLX5_OBJ_TYPE_RQT = 0xff0e,
105 	MLX5_OBJ_TYPE_FLOW_COUNTER = 0xff0f,
106 	MLX5_OBJ_TYPE_CQ = 0xff10,
107 	MLX5_OBJ_TYPE_FT_ALIAS = 0xff15,
108 };
109 
110 enum {
111 	MLX5_GENERAL_OBJ_TYPES_CAP_SW_ICM = (1ULL << MLX5_OBJ_TYPE_SW_ICM),
112 	MLX5_GENERAL_OBJ_TYPES_CAP_GENEVE_TLV_OPT = (1ULL << 11),
113 	MLX5_GENERAL_OBJ_TYPES_CAP_VIRTIO_NET_Q = (1ULL << 13),
114 	MLX5_GENERAL_OBJ_TYPES_CAP_HEADER_MODIFY_ARGUMENT =
115 		(1ULL << MLX5_OBJ_TYPE_HEADER_MODIFY_ARGUMENT),
116 	MLX5_GENERAL_OBJ_TYPES_CAP_MACSEC_OFFLOAD = (1ULL << 39),
117 };
118 
119 enum {
120 	MLX5_CMD_OP_QUERY_HCA_CAP                 = 0x100,
121 	MLX5_CMD_OP_QUERY_ADAPTER                 = 0x101,
122 	MLX5_CMD_OP_INIT_HCA                      = 0x102,
123 	MLX5_CMD_OP_TEARDOWN_HCA                  = 0x103,
124 	MLX5_CMD_OP_ENABLE_HCA                    = 0x104,
125 	MLX5_CMD_OP_DISABLE_HCA                   = 0x105,
126 	MLX5_CMD_OP_QUERY_PAGES                   = 0x107,
127 	MLX5_CMD_OP_MANAGE_PAGES                  = 0x108,
128 	MLX5_CMD_OP_SET_HCA_CAP                   = 0x109,
129 	MLX5_CMD_OP_QUERY_ISSI                    = 0x10a,
130 	MLX5_CMD_OP_SET_ISSI                      = 0x10b,
131 	MLX5_CMD_OP_SET_DRIVER_VERSION            = 0x10d,
132 	MLX5_CMD_OP_QUERY_SF_PARTITION            = 0x111,
133 	MLX5_CMD_OP_ALLOC_SF                      = 0x113,
134 	MLX5_CMD_OP_DEALLOC_SF                    = 0x114,
135 	MLX5_CMD_OP_SUSPEND_VHCA                  = 0x115,
136 	MLX5_CMD_OP_RESUME_VHCA                   = 0x116,
137 	MLX5_CMD_OP_QUERY_VHCA_MIGRATION_STATE    = 0x117,
138 	MLX5_CMD_OP_SAVE_VHCA_STATE               = 0x118,
139 	MLX5_CMD_OP_LOAD_VHCA_STATE               = 0x119,
140 	MLX5_CMD_OP_CREATE_MKEY                   = 0x200,
141 	MLX5_CMD_OP_QUERY_MKEY                    = 0x201,
142 	MLX5_CMD_OP_DESTROY_MKEY                  = 0x202,
143 	MLX5_CMD_OP_QUERY_SPECIAL_CONTEXTS        = 0x203,
144 	MLX5_CMD_OP_PAGE_FAULT_RESUME             = 0x204,
145 	MLX5_CMD_OP_ALLOC_MEMIC                   = 0x205,
146 	MLX5_CMD_OP_DEALLOC_MEMIC                 = 0x206,
147 	MLX5_CMD_OP_MODIFY_MEMIC                  = 0x207,
148 	MLX5_CMD_OP_CREATE_EQ                     = 0x301,
149 	MLX5_CMD_OP_DESTROY_EQ                    = 0x302,
150 	MLX5_CMD_OP_QUERY_EQ                      = 0x303,
151 	MLX5_CMD_OP_GEN_EQE                       = 0x304,
152 	MLX5_CMD_OP_CREATE_CQ                     = 0x400,
153 	MLX5_CMD_OP_DESTROY_CQ                    = 0x401,
154 	MLX5_CMD_OP_QUERY_CQ                      = 0x402,
155 	MLX5_CMD_OP_MODIFY_CQ                     = 0x403,
156 	MLX5_CMD_OP_CREATE_QP                     = 0x500,
157 	MLX5_CMD_OP_DESTROY_QP                    = 0x501,
158 	MLX5_CMD_OP_RST2INIT_QP                   = 0x502,
159 	MLX5_CMD_OP_INIT2RTR_QP                   = 0x503,
160 	MLX5_CMD_OP_RTR2RTS_QP                    = 0x504,
161 	MLX5_CMD_OP_RTS2RTS_QP                    = 0x505,
162 	MLX5_CMD_OP_SQERR2RTS_QP                  = 0x506,
163 	MLX5_CMD_OP_2ERR_QP                       = 0x507,
164 	MLX5_CMD_OP_2RST_QP                       = 0x50a,
165 	MLX5_CMD_OP_QUERY_QP                      = 0x50b,
166 	MLX5_CMD_OP_SQD_RTS_QP                    = 0x50c,
167 	MLX5_CMD_OP_INIT2INIT_QP                  = 0x50e,
168 	MLX5_CMD_OP_CREATE_PSV                    = 0x600,
169 	MLX5_CMD_OP_DESTROY_PSV                   = 0x601,
170 	MLX5_CMD_OP_CREATE_SRQ                    = 0x700,
171 	MLX5_CMD_OP_DESTROY_SRQ                   = 0x701,
172 	MLX5_CMD_OP_QUERY_SRQ                     = 0x702,
173 	MLX5_CMD_OP_ARM_RQ                        = 0x703,
174 	MLX5_CMD_OP_CREATE_XRC_SRQ                = 0x705,
175 	MLX5_CMD_OP_DESTROY_XRC_SRQ               = 0x706,
176 	MLX5_CMD_OP_QUERY_XRC_SRQ                 = 0x707,
177 	MLX5_CMD_OP_ARM_XRC_SRQ                   = 0x708,
178 	MLX5_CMD_OP_CREATE_DCT                    = 0x710,
179 	MLX5_CMD_OP_DESTROY_DCT                   = 0x711,
180 	MLX5_CMD_OP_DRAIN_DCT                     = 0x712,
181 	MLX5_CMD_OP_QUERY_DCT                     = 0x713,
182 	MLX5_CMD_OP_ARM_DCT_FOR_KEY_VIOLATION     = 0x714,
183 	MLX5_CMD_OP_CREATE_XRQ                    = 0x717,
184 	MLX5_CMD_OP_DESTROY_XRQ                   = 0x718,
185 	MLX5_CMD_OP_QUERY_XRQ                     = 0x719,
186 	MLX5_CMD_OP_ARM_XRQ                       = 0x71a,
187 	MLX5_CMD_OP_QUERY_XRQ_DC_PARAMS_ENTRY     = 0x725,
188 	MLX5_CMD_OP_SET_XRQ_DC_PARAMS_ENTRY       = 0x726,
189 	MLX5_CMD_OP_QUERY_XRQ_ERROR_PARAMS        = 0x727,
190 	MLX5_CMD_OP_RELEASE_XRQ_ERROR             = 0x729,
191 	MLX5_CMD_OP_MODIFY_XRQ                    = 0x72a,
192 	MLX5_CMD_OP_QUERY_ESW_FUNCTIONS           = 0x740,
193 	MLX5_CMD_OP_QUERY_VPORT_STATE             = 0x750,
194 	MLX5_CMD_OP_MODIFY_VPORT_STATE            = 0x751,
195 	MLX5_CMD_OP_QUERY_ESW_VPORT_CONTEXT       = 0x752,
196 	MLX5_CMD_OP_MODIFY_ESW_VPORT_CONTEXT      = 0x753,
197 	MLX5_CMD_OP_QUERY_NIC_VPORT_CONTEXT       = 0x754,
198 	MLX5_CMD_OP_MODIFY_NIC_VPORT_CONTEXT      = 0x755,
199 	MLX5_CMD_OP_QUERY_ROCE_ADDRESS            = 0x760,
200 	MLX5_CMD_OP_SET_ROCE_ADDRESS              = 0x761,
201 	MLX5_CMD_OP_QUERY_HCA_VPORT_CONTEXT       = 0x762,
202 	MLX5_CMD_OP_MODIFY_HCA_VPORT_CONTEXT      = 0x763,
203 	MLX5_CMD_OP_QUERY_HCA_VPORT_GID           = 0x764,
204 	MLX5_CMD_OP_QUERY_HCA_VPORT_PKEY          = 0x765,
205 	MLX5_CMD_OP_QUERY_VNIC_ENV                = 0x76f,
206 	MLX5_CMD_OP_QUERY_VPORT_COUNTER           = 0x770,
207 	MLX5_CMD_OP_ALLOC_Q_COUNTER               = 0x771,
208 	MLX5_CMD_OP_DEALLOC_Q_COUNTER             = 0x772,
209 	MLX5_CMD_OP_QUERY_Q_COUNTER               = 0x773,
210 	MLX5_CMD_OP_SET_MONITOR_COUNTER           = 0x774,
211 	MLX5_CMD_OP_ARM_MONITOR_COUNTER           = 0x775,
212 	MLX5_CMD_OP_SET_PP_RATE_LIMIT             = 0x780,
213 	MLX5_CMD_OP_QUERY_RATE_LIMIT              = 0x781,
214 	MLX5_CMD_OP_CREATE_SCHEDULING_ELEMENT      = 0x782,
215 	MLX5_CMD_OP_DESTROY_SCHEDULING_ELEMENT     = 0x783,
216 	MLX5_CMD_OP_QUERY_SCHEDULING_ELEMENT       = 0x784,
217 	MLX5_CMD_OP_MODIFY_SCHEDULING_ELEMENT      = 0x785,
218 	MLX5_CMD_OP_CREATE_QOS_PARA_VPORT         = 0x786,
219 	MLX5_CMD_OP_DESTROY_QOS_PARA_VPORT        = 0x787,
220 	MLX5_CMD_OP_ALLOC_PD                      = 0x800,
221 	MLX5_CMD_OP_DEALLOC_PD                    = 0x801,
222 	MLX5_CMD_OP_ALLOC_UAR                     = 0x802,
223 	MLX5_CMD_OP_DEALLOC_UAR                   = 0x803,
224 	MLX5_CMD_OP_CONFIG_INT_MODERATION         = 0x804,
225 	MLX5_CMD_OP_ACCESS_REG                    = 0x805,
226 	MLX5_CMD_OP_ATTACH_TO_MCG                 = 0x806,
227 	MLX5_CMD_OP_DETACH_FROM_MCG               = 0x807,
228 	MLX5_CMD_OP_GET_DROPPED_PACKET_LOG        = 0x80a,
229 	MLX5_CMD_OP_MAD_IFC                       = 0x50d,
230 	MLX5_CMD_OP_QUERY_MAD_DEMUX               = 0x80b,
231 	MLX5_CMD_OP_SET_MAD_DEMUX                 = 0x80c,
232 	MLX5_CMD_OP_NOP                           = 0x80d,
233 	MLX5_CMD_OP_ALLOC_XRCD                    = 0x80e,
234 	MLX5_CMD_OP_DEALLOC_XRCD                  = 0x80f,
235 	MLX5_CMD_OP_ALLOC_TRANSPORT_DOMAIN        = 0x816,
236 	MLX5_CMD_OP_DEALLOC_TRANSPORT_DOMAIN      = 0x817,
237 	MLX5_CMD_OP_QUERY_CONG_STATUS             = 0x822,
238 	MLX5_CMD_OP_MODIFY_CONG_STATUS            = 0x823,
239 	MLX5_CMD_OP_QUERY_CONG_PARAMS             = 0x824,
240 	MLX5_CMD_OP_MODIFY_CONG_PARAMS            = 0x825,
241 	MLX5_CMD_OP_QUERY_CONG_STATISTICS         = 0x826,
242 	MLX5_CMD_OP_ADD_VXLAN_UDP_DPORT           = 0x827,
243 	MLX5_CMD_OP_DELETE_VXLAN_UDP_DPORT        = 0x828,
244 	MLX5_CMD_OP_SET_L2_TABLE_ENTRY            = 0x829,
245 	MLX5_CMD_OP_QUERY_L2_TABLE_ENTRY          = 0x82a,
246 	MLX5_CMD_OP_DELETE_L2_TABLE_ENTRY         = 0x82b,
247 	MLX5_CMD_OP_SET_WOL_ROL                   = 0x830,
248 	MLX5_CMD_OP_QUERY_WOL_ROL                 = 0x831,
249 	MLX5_CMD_OP_CREATE_LAG                    = 0x840,
250 	MLX5_CMD_OP_MODIFY_LAG                    = 0x841,
251 	MLX5_CMD_OP_QUERY_LAG                     = 0x842,
252 	MLX5_CMD_OP_DESTROY_LAG                   = 0x843,
253 	MLX5_CMD_OP_CREATE_VPORT_LAG              = 0x844,
254 	MLX5_CMD_OP_DESTROY_VPORT_LAG             = 0x845,
255 	MLX5_CMD_OP_CREATE_TIR                    = 0x900,
256 	MLX5_CMD_OP_MODIFY_TIR                    = 0x901,
257 	MLX5_CMD_OP_DESTROY_TIR                   = 0x902,
258 	MLX5_CMD_OP_QUERY_TIR                     = 0x903,
259 	MLX5_CMD_OP_CREATE_SQ                     = 0x904,
260 	MLX5_CMD_OP_MODIFY_SQ                     = 0x905,
261 	MLX5_CMD_OP_DESTROY_SQ                    = 0x906,
262 	MLX5_CMD_OP_QUERY_SQ                      = 0x907,
263 	MLX5_CMD_OP_CREATE_RQ                     = 0x908,
264 	MLX5_CMD_OP_MODIFY_RQ                     = 0x909,
265 	MLX5_CMD_OP_SET_DELAY_DROP_PARAMS         = 0x910,
266 	MLX5_CMD_OP_DESTROY_RQ                    = 0x90a,
267 	MLX5_CMD_OP_QUERY_RQ                      = 0x90b,
268 	MLX5_CMD_OP_CREATE_RMP                    = 0x90c,
269 	MLX5_CMD_OP_MODIFY_RMP                    = 0x90d,
270 	MLX5_CMD_OP_DESTROY_RMP                   = 0x90e,
271 	MLX5_CMD_OP_QUERY_RMP                     = 0x90f,
272 	MLX5_CMD_OP_CREATE_TIS                    = 0x912,
273 	MLX5_CMD_OP_MODIFY_TIS                    = 0x913,
274 	MLX5_CMD_OP_DESTROY_TIS                   = 0x914,
275 	MLX5_CMD_OP_QUERY_TIS                     = 0x915,
276 	MLX5_CMD_OP_CREATE_RQT                    = 0x916,
277 	MLX5_CMD_OP_MODIFY_RQT                    = 0x917,
278 	MLX5_CMD_OP_DESTROY_RQT                   = 0x918,
279 	MLX5_CMD_OP_QUERY_RQT                     = 0x919,
280 	MLX5_CMD_OP_SET_FLOW_TABLE_ROOT		  = 0x92f,
281 	MLX5_CMD_OP_CREATE_FLOW_TABLE             = 0x930,
282 	MLX5_CMD_OP_DESTROY_FLOW_TABLE            = 0x931,
283 	MLX5_CMD_OP_QUERY_FLOW_TABLE              = 0x932,
284 	MLX5_CMD_OP_CREATE_FLOW_GROUP             = 0x933,
285 	MLX5_CMD_OP_DESTROY_FLOW_GROUP            = 0x934,
286 	MLX5_CMD_OP_QUERY_FLOW_GROUP              = 0x935,
287 	MLX5_CMD_OP_SET_FLOW_TABLE_ENTRY          = 0x936,
288 	MLX5_CMD_OP_QUERY_FLOW_TABLE_ENTRY        = 0x937,
289 	MLX5_CMD_OP_DELETE_FLOW_TABLE_ENTRY       = 0x938,
290 	MLX5_CMD_OP_ALLOC_FLOW_COUNTER            = 0x939,
291 	MLX5_CMD_OP_DEALLOC_FLOW_COUNTER          = 0x93a,
292 	MLX5_CMD_OP_QUERY_FLOW_COUNTER            = 0x93b,
293 	MLX5_CMD_OP_MODIFY_FLOW_TABLE             = 0x93c,
294 	MLX5_CMD_OP_ALLOC_PACKET_REFORMAT_CONTEXT = 0x93d,
295 	MLX5_CMD_OP_DEALLOC_PACKET_REFORMAT_CONTEXT = 0x93e,
296 	MLX5_CMD_OP_QUERY_PACKET_REFORMAT_CONTEXT = 0x93f,
297 	MLX5_CMD_OP_ALLOC_MODIFY_HEADER_CONTEXT   = 0x940,
298 	MLX5_CMD_OP_DEALLOC_MODIFY_HEADER_CONTEXT = 0x941,
299 	MLX5_CMD_OP_QUERY_MODIFY_HEADER_CONTEXT   = 0x942,
300 	MLX5_CMD_OP_FPGA_CREATE_QP                = 0x960,
301 	MLX5_CMD_OP_FPGA_MODIFY_QP                = 0x961,
302 	MLX5_CMD_OP_FPGA_QUERY_QP                 = 0x962,
303 	MLX5_CMD_OP_FPGA_DESTROY_QP               = 0x963,
304 	MLX5_CMD_OP_FPGA_QUERY_QP_COUNTERS        = 0x964,
305 	MLX5_CMD_OP_CREATE_GENERAL_OBJECT         = 0xa00,
306 	MLX5_CMD_OP_MODIFY_GENERAL_OBJECT         = 0xa01,
307 	MLX5_CMD_OP_QUERY_GENERAL_OBJECT          = 0xa02,
308 	MLX5_CMD_OP_DESTROY_GENERAL_OBJECT        = 0xa03,
309 	MLX5_CMD_OP_CREATE_UCTX                   = 0xa04,
310 	MLX5_CMD_OP_DESTROY_UCTX                  = 0xa06,
311 	MLX5_CMD_OP_CREATE_UMEM                   = 0xa08,
312 	MLX5_CMD_OP_DESTROY_UMEM                  = 0xa0a,
313 	MLX5_CMD_OP_SYNC_STEERING                 = 0xb00,
314 	MLX5_CMD_OP_QUERY_VHCA_STATE              = 0xb0d,
315 	MLX5_CMD_OP_MODIFY_VHCA_STATE             = 0xb0e,
316 	MLX5_CMD_OP_SYNC_CRYPTO                   = 0xb12,
317 	MLX5_CMD_OP_ALLOW_OTHER_VHCA_ACCESS       = 0xb16,
318 	MLX5_CMD_OP_GENERATE_WQE                  = 0xb17,
319 	MLX5_CMD_OPCODE_QUERY_VUID                = 0xb22,
320 	MLX5_CMD_OP_MAX
321 };
322 
323 /* Valid range for general commands that don't work over an object */
324 enum {
325 	MLX5_CMD_OP_GENERAL_START = 0xb00,
326 	MLX5_CMD_OP_GENERAL_END = 0xd00,
327 };
328 
329 enum {
330 	MLX5_FT_NIC_RX_2_NIC_RX_RDMA = BIT(0),
331 	MLX5_FT_NIC_TX_RDMA_2_NIC_TX = BIT(1),
332 };
333 
334 enum {
335 	MLX5_CMD_OP_MOD_UPDATE_HEADER_MODIFY_ARGUMENT = 0x1,
336 };
337 
338 struct mlx5_ifc_flow_table_fields_supported_bits {
339 	u8         outer_dmac[0x1];
340 	u8         outer_smac[0x1];
341 	u8         outer_ether_type[0x1];
342 	u8         outer_ip_version[0x1];
343 	u8         outer_first_prio[0x1];
344 	u8         outer_first_cfi[0x1];
345 	u8         outer_first_vid[0x1];
346 	u8         outer_ipv4_ttl[0x1];
347 	u8         outer_second_prio[0x1];
348 	u8         outer_second_cfi[0x1];
349 	u8         outer_second_vid[0x1];
350 	u8         reserved_at_b[0x1];
351 	u8         outer_sip[0x1];
352 	u8         outer_dip[0x1];
353 	u8         outer_frag[0x1];
354 	u8         outer_ip_protocol[0x1];
355 	u8         outer_ip_ecn[0x1];
356 	u8         outer_ip_dscp[0x1];
357 	u8         outer_udp_sport[0x1];
358 	u8         outer_udp_dport[0x1];
359 	u8         outer_tcp_sport[0x1];
360 	u8         outer_tcp_dport[0x1];
361 	u8         outer_tcp_flags[0x1];
362 	u8         outer_gre_protocol[0x1];
363 	u8         outer_gre_key[0x1];
364 	u8         outer_vxlan_vni[0x1];
365 	u8         outer_geneve_vni[0x1];
366 	u8         outer_geneve_oam[0x1];
367 	u8         outer_geneve_protocol_type[0x1];
368 	u8         outer_geneve_opt_len[0x1];
369 	u8         source_vhca_port[0x1];
370 	u8         source_eswitch_port[0x1];
371 
372 	u8         inner_dmac[0x1];
373 	u8         inner_smac[0x1];
374 	u8         inner_ether_type[0x1];
375 	u8         inner_ip_version[0x1];
376 	u8         inner_first_prio[0x1];
377 	u8         inner_first_cfi[0x1];
378 	u8         inner_first_vid[0x1];
379 	u8         reserved_at_27[0x1];
380 	u8         inner_second_prio[0x1];
381 	u8         inner_second_cfi[0x1];
382 	u8         inner_second_vid[0x1];
383 	u8         reserved_at_2b[0x1];
384 	u8         inner_sip[0x1];
385 	u8         inner_dip[0x1];
386 	u8         inner_frag[0x1];
387 	u8         inner_ip_protocol[0x1];
388 	u8         inner_ip_ecn[0x1];
389 	u8         inner_ip_dscp[0x1];
390 	u8         inner_udp_sport[0x1];
391 	u8         inner_udp_dport[0x1];
392 	u8         inner_tcp_sport[0x1];
393 	u8         inner_tcp_dport[0x1];
394 	u8         inner_tcp_flags[0x1];
395 	u8         reserved_at_37[0x9];
396 
397 	u8         geneve_tlv_option_0_data[0x1];
398 	u8         geneve_tlv_option_0_exist[0x1];
399 	u8         reserved_at_42[0x3];
400 	u8         outer_first_mpls_over_udp[0x4];
401 	u8         outer_first_mpls_over_gre[0x4];
402 	u8         inner_first_mpls[0x4];
403 	u8         outer_first_mpls[0x4];
404 	u8         reserved_at_55[0x2];
405 	u8	   outer_esp_spi[0x1];
406 	u8         reserved_at_58[0x2];
407 	u8         bth_dst_qp[0x1];
408 	u8         reserved_at_5b[0x5];
409 
410 	u8         reserved_at_60[0x18];
411 	u8         metadata_reg_c_7[0x1];
412 	u8         metadata_reg_c_6[0x1];
413 	u8         metadata_reg_c_5[0x1];
414 	u8         metadata_reg_c_4[0x1];
415 	u8         metadata_reg_c_3[0x1];
416 	u8         metadata_reg_c_2[0x1];
417 	u8         metadata_reg_c_1[0x1];
418 	u8         metadata_reg_c_0[0x1];
419 };
420 
421 /* Table 2170 - Flow Table Fields Supported 2 Format */
422 struct mlx5_ifc_flow_table_fields_supported_2_bits {
423 	u8         reserved_at_0[0x2];
424 	u8         inner_l4_type[0x1];
425 	u8         outer_l4_type[0x1];
426 	u8         reserved_at_4[0xa];
427 	u8         bth_opcode[0x1];
428 	u8         reserved_at_f[0x1];
429 	u8         tunnel_header_0_1[0x1];
430 	u8         reserved_at_11[0xf];
431 
432 	u8         reserved_at_20[0x60];
433 };
434 
435 struct mlx5_ifc_flow_table_prop_layout_bits {
436 	u8         ft_support[0x1];
437 	u8         reserved_at_1[0x1];
438 	u8         flow_counter[0x1];
439 	u8	   flow_modify_en[0x1];
440 	u8         modify_root[0x1];
441 	u8         identified_miss_table_mode[0x1];
442 	u8         flow_table_modify[0x1];
443 	u8         reformat[0x1];
444 	u8         decap[0x1];
445 	u8         reset_root_to_default[0x1];
446 	u8         pop_vlan[0x1];
447 	u8         push_vlan[0x1];
448 	u8         reserved_at_c[0x1];
449 	u8         pop_vlan_2[0x1];
450 	u8         push_vlan_2[0x1];
451 	u8	   reformat_and_vlan_action[0x1];
452 	u8	   reserved_at_10[0x1];
453 	u8         sw_owner[0x1];
454 	u8	   reformat_l3_tunnel_to_l2[0x1];
455 	u8	   reformat_l2_to_l3_tunnel[0x1];
456 	u8	   reformat_and_modify_action[0x1];
457 	u8	   ignore_flow_level[0x1];
458 	u8         reserved_at_16[0x1];
459 	u8	   table_miss_action_domain[0x1];
460 	u8         termination_table[0x1];
461 	u8         reformat_and_fwd_to_table[0x1];
462 	u8         reserved_at_1a[0x2];
463 	u8         ipsec_encrypt[0x1];
464 	u8         ipsec_decrypt[0x1];
465 	u8         sw_owner_v2[0x1];
466 	u8         reserved_at_1f[0x1];
467 
468 	u8         termination_table_raw_traffic[0x1];
469 	u8         reserved_at_21[0x1];
470 	u8         log_max_ft_size[0x6];
471 	u8         log_max_modify_header_context[0x8];
472 	u8         max_modify_header_actions[0x8];
473 	u8         max_ft_level[0x8];
474 
475 	u8         reformat_add_esp_trasport[0x1];
476 	u8         reformat_l2_to_l3_esp_tunnel[0x1];
477 	u8         reformat_add_esp_transport_over_udp[0x1];
478 	u8         reformat_del_esp_trasport[0x1];
479 	u8         reformat_l3_esp_tunnel_to_l2[0x1];
480 	u8         reformat_del_esp_transport_over_udp[0x1];
481 	u8         execute_aso[0x1];
482 	u8         reserved_at_47[0x19];
483 
484 	u8         reserved_at_60[0x2];
485 	u8         reformat_insert[0x1];
486 	u8         reformat_remove[0x1];
487 	u8         macsec_encrypt[0x1];
488 	u8         macsec_decrypt[0x1];
489 	u8         reserved_at_66[0x2];
490 	u8         reformat_add_macsec[0x1];
491 	u8         reformat_remove_macsec[0x1];
492 	u8         reparse[0x1];
493 	u8         reserved_at_6b[0x1];
494 	u8         cross_vhca_object[0x1];
495 	u8         reformat_l2_to_l3_audp_tunnel[0x1];
496 	u8         reformat_l3_audp_tunnel_to_l2[0x1];
497 	u8         ignore_flow_level_rtc_valid[0x1];
498 	u8         reserved_at_70[0x8];
499 	u8         log_max_ft_num[0x8];
500 
501 	u8         reserved_at_80[0x10];
502 	u8         log_max_flow_counter[0x8];
503 	u8         log_max_destination[0x8];
504 
505 	u8         reserved_at_a0[0x18];
506 	u8         log_max_flow[0x8];
507 
508 	u8         reserved_at_c0[0x40];
509 
510 	struct mlx5_ifc_flow_table_fields_supported_bits ft_field_support;
511 
512 	struct mlx5_ifc_flow_table_fields_supported_bits ft_field_bitmask_support;
513 };
514 
515 struct mlx5_ifc_odp_per_transport_service_cap_bits {
516 	u8         send[0x1];
517 	u8         receive[0x1];
518 	u8         write[0x1];
519 	u8         read[0x1];
520 	u8         atomic[0x1];
521 	u8         srq_receive[0x1];
522 	u8         reserved_at_6[0x1a];
523 };
524 
525 struct mlx5_ifc_ipv4_layout_bits {
526 	u8         reserved_at_0[0x60];
527 
528 	u8         ipv4[0x20];
529 };
530 
531 struct mlx5_ifc_ipv6_layout_bits {
532 	u8         ipv6[16][0x8];
533 };
534 
535 struct mlx5_ifc_ipv6_simple_layout_bits {
536 	u8         ipv6_127_96[0x20];
537 	u8         ipv6_95_64[0x20];
538 	u8         ipv6_63_32[0x20];
539 	u8         ipv6_31_0[0x20];
540 };
541 
542 union mlx5_ifc_ipv6_layout_ipv4_layout_auto_bits {
543 	struct mlx5_ifc_ipv6_simple_layout_bits ipv6_simple_layout;
544 	struct mlx5_ifc_ipv6_layout_bits ipv6_layout;
545 	struct mlx5_ifc_ipv4_layout_bits ipv4_layout;
546 	u8         reserved_at_0[0x80];
547 };
548 
549 enum {
550 	MLX5_PACKET_L4_TYPE_NONE,
551 	MLX5_PACKET_L4_TYPE_TCP,
552 	MLX5_PACKET_L4_TYPE_UDP,
553 };
554 
555 struct mlx5_ifc_fte_match_set_lyr_2_4_bits {
556 	u8         smac_47_16[0x20];
557 
558 	u8         smac_15_0[0x10];
559 	u8         ethertype[0x10];
560 
561 	u8         dmac_47_16[0x20];
562 
563 	u8         dmac_15_0[0x10];
564 	u8         first_prio[0x3];
565 	u8         first_cfi[0x1];
566 	u8         first_vid[0xc];
567 
568 	u8         ip_protocol[0x8];
569 	u8         ip_dscp[0x6];
570 	u8         ip_ecn[0x2];
571 	u8         cvlan_tag[0x1];
572 	u8         svlan_tag[0x1];
573 	u8         frag[0x1];
574 	u8         ip_version[0x4];
575 	u8         tcp_flags[0x9];
576 
577 	u8         tcp_sport[0x10];
578 	u8         tcp_dport[0x10];
579 
580 	u8         l4_type[0x2];
581 	u8         reserved_at_c2[0xe];
582 	u8         ipv4_ihl[0x4];
583 	u8         reserved_at_c4[0x4];
584 
585 	u8         ttl_hoplimit[0x8];
586 
587 	u8         udp_sport[0x10];
588 	u8         udp_dport[0x10];
589 
590 	union mlx5_ifc_ipv6_layout_ipv4_layout_auto_bits src_ipv4_src_ipv6;
591 
592 	union mlx5_ifc_ipv6_layout_ipv4_layout_auto_bits dst_ipv4_dst_ipv6;
593 };
594 
595 struct mlx5_ifc_nvgre_key_bits {
596 	u8 hi[0x18];
597 	u8 lo[0x8];
598 };
599 
600 union mlx5_ifc_gre_key_bits {
601 	struct mlx5_ifc_nvgre_key_bits nvgre;
602 	u8 key[0x20];
603 };
604 
605 struct mlx5_ifc_fte_match_set_misc_bits {
606 	u8         gre_c_present[0x1];
607 	u8         reserved_at_1[0x1];
608 	u8         gre_k_present[0x1];
609 	u8         gre_s_present[0x1];
610 	u8         source_vhca_port[0x4];
611 	u8         source_sqn[0x18];
612 
613 	u8         source_eswitch_owner_vhca_id[0x10];
614 	u8         source_port[0x10];
615 
616 	u8         outer_second_prio[0x3];
617 	u8         outer_second_cfi[0x1];
618 	u8         outer_second_vid[0xc];
619 	u8         inner_second_prio[0x3];
620 	u8         inner_second_cfi[0x1];
621 	u8         inner_second_vid[0xc];
622 
623 	u8         outer_second_cvlan_tag[0x1];
624 	u8         inner_second_cvlan_tag[0x1];
625 	u8         outer_second_svlan_tag[0x1];
626 	u8         inner_second_svlan_tag[0x1];
627 	u8         reserved_at_64[0xc];
628 	u8         gre_protocol[0x10];
629 
630 	union mlx5_ifc_gre_key_bits gre_key;
631 
632 	u8         vxlan_vni[0x18];
633 	u8         bth_opcode[0x8];
634 
635 	u8         geneve_vni[0x18];
636 	u8         reserved_at_d8[0x6];
637 	u8         geneve_tlv_option_0_exist[0x1];
638 	u8         geneve_oam[0x1];
639 
640 	u8         reserved_at_e0[0xc];
641 	u8         outer_ipv6_flow_label[0x14];
642 
643 	u8         reserved_at_100[0xc];
644 	u8         inner_ipv6_flow_label[0x14];
645 
646 	u8         reserved_at_120[0xa];
647 	u8         geneve_opt_len[0x6];
648 	u8         geneve_protocol_type[0x10];
649 
650 	u8         reserved_at_140[0x8];
651 	u8         bth_dst_qp[0x18];
652 	u8	   inner_esp_spi[0x20];
653 	u8	   outer_esp_spi[0x20];
654 	u8         reserved_at_1a0[0x60];
655 };
656 
657 struct mlx5_ifc_fte_match_mpls_bits {
658 	u8         mpls_label[0x14];
659 	u8         mpls_exp[0x3];
660 	u8         mpls_s_bos[0x1];
661 	u8         mpls_ttl[0x8];
662 };
663 
664 struct mlx5_ifc_fte_match_set_misc2_bits {
665 	struct mlx5_ifc_fte_match_mpls_bits outer_first_mpls;
666 
667 	struct mlx5_ifc_fte_match_mpls_bits inner_first_mpls;
668 
669 	struct mlx5_ifc_fte_match_mpls_bits outer_first_mpls_over_gre;
670 
671 	struct mlx5_ifc_fte_match_mpls_bits outer_first_mpls_over_udp;
672 
673 	u8         metadata_reg_c_7[0x20];
674 
675 	u8         metadata_reg_c_6[0x20];
676 
677 	u8         metadata_reg_c_5[0x20];
678 
679 	u8         metadata_reg_c_4[0x20];
680 
681 	u8         metadata_reg_c_3[0x20];
682 
683 	u8         metadata_reg_c_2[0x20];
684 
685 	u8         metadata_reg_c_1[0x20];
686 
687 	u8         metadata_reg_c_0[0x20];
688 
689 	u8         metadata_reg_a[0x20];
690 
691 	u8         reserved_at_1a0[0x8];
692 
693 	u8         macsec_syndrome[0x8];
694 	u8         ipsec_syndrome[0x8];
695 	u8         reserved_at_1b8[0x8];
696 
697 	u8         reserved_at_1c0[0x40];
698 };
699 
700 struct mlx5_ifc_fte_match_set_misc3_bits {
701 	u8         inner_tcp_seq_num[0x20];
702 
703 	u8         outer_tcp_seq_num[0x20];
704 
705 	u8         inner_tcp_ack_num[0x20];
706 
707 	u8         outer_tcp_ack_num[0x20];
708 
709 	u8	   reserved_at_80[0x8];
710 	u8         outer_vxlan_gpe_vni[0x18];
711 
712 	u8         outer_vxlan_gpe_next_protocol[0x8];
713 	u8         outer_vxlan_gpe_flags[0x8];
714 	u8	   reserved_at_b0[0x10];
715 
716 	u8	   icmp_header_data[0x20];
717 
718 	u8	   icmpv6_header_data[0x20];
719 
720 	u8	   icmp_type[0x8];
721 	u8	   icmp_code[0x8];
722 	u8	   icmpv6_type[0x8];
723 	u8	   icmpv6_code[0x8];
724 
725 	u8         geneve_tlv_option_0_data[0x20];
726 
727 	u8	   gtpu_teid[0x20];
728 
729 	u8	   gtpu_msg_type[0x8];
730 	u8	   gtpu_msg_flags[0x8];
731 	u8	   reserved_at_170[0x10];
732 
733 	u8	   gtpu_dw_2[0x20];
734 
735 	u8	   gtpu_first_ext_dw_0[0x20];
736 
737 	u8	   gtpu_dw_0[0x20];
738 
739 	u8	   reserved_at_1e0[0x20];
740 };
741 
742 struct mlx5_ifc_fte_match_set_misc4_bits {
743 	u8         prog_sample_field_value_0[0x20];
744 
745 	u8         prog_sample_field_id_0[0x20];
746 
747 	u8         prog_sample_field_value_1[0x20];
748 
749 	u8         prog_sample_field_id_1[0x20];
750 
751 	u8         prog_sample_field_value_2[0x20];
752 
753 	u8         prog_sample_field_id_2[0x20];
754 
755 	u8         prog_sample_field_value_3[0x20];
756 
757 	u8         prog_sample_field_id_3[0x20];
758 
759 	u8         reserved_at_100[0x100];
760 };
761 
762 struct mlx5_ifc_fte_match_set_misc5_bits {
763 	u8         macsec_tag_0[0x20];
764 
765 	u8         macsec_tag_1[0x20];
766 
767 	u8         macsec_tag_2[0x20];
768 
769 	u8         macsec_tag_3[0x20];
770 
771 	u8         tunnel_header_0[0x20];
772 
773 	u8         tunnel_header_1[0x20];
774 
775 	u8         tunnel_header_2[0x20];
776 
777 	u8         tunnel_header_3[0x20];
778 
779 	u8         reserved_at_100[0x100];
780 };
781 
782 struct mlx5_ifc_cmd_pas_bits {
783 	u8         pa_h[0x20];
784 
785 	u8         pa_l[0x14];
786 	u8         reserved_at_34[0xc];
787 };
788 
789 struct mlx5_ifc_uint64_bits {
790 	u8         hi[0x20];
791 
792 	u8         lo[0x20];
793 };
794 
795 enum {
796 	MLX5_ADS_STAT_RATE_NO_LIMIT  = 0x0,
797 	MLX5_ADS_STAT_RATE_2_5GBPS   = 0x7,
798 	MLX5_ADS_STAT_RATE_10GBPS    = 0x8,
799 	MLX5_ADS_STAT_RATE_30GBPS    = 0x9,
800 	MLX5_ADS_STAT_RATE_5GBPS     = 0xa,
801 	MLX5_ADS_STAT_RATE_20GBPS    = 0xb,
802 	MLX5_ADS_STAT_RATE_40GBPS    = 0xc,
803 	MLX5_ADS_STAT_RATE_60GBPS    = 0xd,
804 	MLX5_ADS_STAT_RATE_80GBPS    = 0xe,
805 	MLX5_ADS_STAT_RATE_120GBPS   = 0xf,
806 };
807 
808 struct mlx5_ifc_ads_bits {
809 	u8         fl[0x1];
810 	u8         free_ar[0x1];
811 	u8         reserved_at_2[0xe];
812 	u8         pkey_index[0x10];
813 
814 	u8         plane_index[0x8];
815 	u8         grh[0x1];
816 	u8         mlid[0x7];
817 	u8         rlid[0x10];
818 
819 	u8         ack_timeout[0x5];
820 	u8         reserved_at_45[0x3];
821 	u8         src_addr_index[0x8];
822 	u8         reserved_at_50[0x4];
823 	u8         stat_rate[0x4];
824 	u8         hop_limit[0x8];
825 
826 	u8         reserved_at_60[0x4];
827 	u8         tclass[0x8];
828 	u8         flow_label[0x14];
829 
830 	u8         rgid_rip[16][0x8];
831 
832 	u8         reserved_at_100[0x4];
833 	u8         f_dscp[0x1];
834 	u8         f_ecn[0x1];
835 	u8         reserved_at_106[0x1];
836 	u8         f_eth_prio[0x1];
837 	u8         ecn[0x2];
838 	u8         dscp[0x6];
839 	u8         udp_sport[0x10];
840 
841 	u8         dei_cfi[0x1];
842 	u8         eth_prio[0x3];
843 	u8         sl[0x4];
844 	u8         vhca_port_num[0x8];
845 	u8         rmac_47_32[0x10];
846 
847 	u8         rmac_31_0[0x20];
848 };
849 
850 struct mlx5_ifc_flow_table_nic_cap_bits {
851 	u8         nic_rx_multi_path_tirs[0x1];
852 	u8         nic_rx_multi_path_tirs_fts[0x1];
853 	u8         allow_sniffer_and_nic_rx_shared_tir[0x1];
854 	u8	   reserved_at_3[0x4];
855 	u8	   sw_owner_reformat_supported[0x1];
856 	u8	   reserved_at_8[0x18];
857 
858 	u8	   encap_general_header[0x1];
859 	u8	   reserved_at_21[0xa];
860 	u8	   log_max_packet_reformat_context[0x5];
861 	u8	   reserved_at_30[0x6];
862 	u8	   max_encap_header_size[0xa];
863 	u8	   reserved_at_40[0x1c0];
864 
865 	struct mlx5_ifc_flow_table_prop_layout_bits flow_table_properties_nic_receive;
866 
867 	struct mlx5_ifc_flow_table_prop_layout_bits flow_table_properties_nic_receive_rdma;
868 
869 	struct mlx5_ifc_flow_table_prop_layout_bits flow_table_properties_nic_receive_sniffer;
870 
871 	struct mlx5_ifc_flow_table_prop_layout_bits flow_table_properties_nic_transmit;
872 
873 	struct mlx5_ifc_flow_table_prop_layout_bits flow_table_properties_nic_transmit_rdma;
874 
875 	struct mlx5_ifc_flow_table_prop_layout_bits flow_table_properties_nic_transmit_sniffer;
876 
877 	u8         reserved_at_e00[0x600];
878 
879 	struct mlx5_ifc_flow_table_fields_supported_2_bits ft_field_support_2_nic_receive;
880 
881 	u8         reserved_at_1480[0x80];
882 
883 	struct mlx5_ifc_flow_table_fields_supported_2_bits ft_field_support_2_nic_receive_rdma;
884 
885 	u8         reserved_at_1580[0x280];
886 
887 	struct mlx5_ifc_flow_table_fields_supported_2_bits ft_field_support_2_nic_transmit_rdma;
888 
889 	u8         reserved_at_1880[0x780];
890 
891 	u8         sw_steering_nic_rx_action_drop_icm_address[0x40];
892 
893 	u8         sw_steering_nic_tx_action_drop_icm_address[0x40];
894 
895 	u8         sw_steering_nic_tx_action_allow_icm_address[0x40];
896 
897 	u8         reserved_at_20c0[0x5f40];
898 };
899 
900 struct mlx5_ifc_port_selection_cap_bits {
901 	u8         reserved_at_0[0x10];
902 	u8         port_select_flow_table[0x1];
903 	u8         reserved_at_11[0x1];
904 	u8         port_select_flow_table_bypass[0x1];
905 	u8         reserved_at_13[0xd];
906 
907 	u8         reserved_at_20[0x1e0];
908 
909 	struct mlx5_ifc_flow_table_prop_layout_bits flow_table_properties_port_selection;
910 
911 	struct mlx5_ifc_flow_table_fields_supported_2_bits ft_field_support_2_port_selection;
912 
913 	u8         reserved_at_480[0x7b80];
914 };
915 
916 enum {
917 	MLX5_FDB_TO_VPORT_REG_C_0 = 0x01,
918 	MLX5_FDB_TO_VPORT_REG_C_1 = 0x02,
919 	MLX5_FDB_TO_VPORT_REG_C_2 = 0x04,
920 	MLX5_FDB_TO_VPORT_REG_C_3 = 0x08,
921 	MLX5_FDB_TO_VPORT_REG_C_4 = 0x10,
922 	MLX5_FDB_TO_VPORT_REG_C_5 = 0x20,
923 	MLX5_FDB_TO_VPORT_REG_C_6 = 0x40,
924 	MLX5_FDB_TO_VPORT_REG_C_7 = 0x80,
925 };
926 
927 struct mlx5_ifc_flow_table_eswitch_cap_bits {
928 	u8      fdb_to_vport_reg_c_id[0x8];
929 	u8      reserved_at_8[0x5];
930 	u8      fdb_uplink_hairpin[0x1];
931 	u8      fdb_multi_path_any_table_limit_regc[0x1];
932 	u8      reserved_at_f[0x1];
933 	u8      fdb_dynamic_tunnel[0x1];
934 	u8      reserved_at_11[0x1];
935 	u8      fdb_multi_path_any_table[0x1];
936 	u8      reserved_at_13[0x2];
937 	u8      fdb_modify_header_fwd_to_table[0x1];
938 	u8      fdb_ipv4_ttl_modify[0x1];
939 	u8      flow_source[0x1];
940 	u8      reserved_at_18[0x2];
941 	u8      multi_fdb_encap[0x1];
942 	u8      egress_acl_forward_to_vport[0x1];
943 	u8      fdb_multi_path_to_table[0x1];
944 	u8      reserved_at_1d[0x3];
945 
946 	u8      reserved_at_20[0x1e0];
947 
948 	struct mlx5_ifc_flow_table_prop_layout_bits flow_table_properties_nic_esw_fdb;
949 
950 	struct mlx5_ifc_flow_table_prop_layout_bits flow_table_properties_esw_acl_ingress;
951 
952 	struct mlx5_ifc_flow_table_prop_layout_bits flow_table_properties_esw_acl_egress;
953 
954 	u8      reserved_at_800[0xC00];
955 
956 	struct mlx5_ifc_flow_table_fields_supported_2_bits ft_field_support_2_esw_fdb;
957 
958 	struct mlx5_ifc_flow_table_fields_supported_2_bits ft_field_bitmask_support_2_esw_fdb;
959 
960 	u8      reserved_at_1500[0x300];
961 
962 	u8      sw_steering_fdb_action_drop_icm_address_rx[0x40];
963 
964 	u8      sw_steering_fdb_action_drop_icm_address_tx[0x40];
965 
966 	u8      sw_steering_uplink_icm_address_rx[0x40];
967 
968 	u8      sw_steering_uplink_icm_address_tx[0x40];
969 
970 	u8      reserved_at_1900[0x6700];
971 };
972 
973 struct mlx5_ifc_wqe_based_flow_table_cap_bits {
974 	u8         reserved_at_0[0x3];
975 	u8         log_max_num_ste[0x5];
976 	u8         reserved_at_8[0x3];
977 	u8         log_max_num_stc[0x5];
978 	u8         reserved_at_10[0x3];
979 	u8         log_max_num_rtc[0x5];
980 	u8         reserved_at_18[0x3];
981 	u8         log_max_num_header_modify_pattern[0x5];
982 
983 	u8         rtc_hash_split_table[0x1];
984 	u8         rtc_linear_lookup_table[0x1];
985 	u8         reserved_at_22[0x1];
986 	u8         stc_alloc_log_granularity[0x5];
987 	u8         reserved_at_28[0x3];
988 	u8         stc_alloc_log_max[0x5];
989 	u8         reserved_at_30[0x3];
990 	u8         ste_alloc_log_granularity[0x5];
991 	u8         reserved_at_38[0x3];
992 	u8         ste_alloc_log_max[0x5];
993 
994 	u8         reserved_at_40[0xb];
995 	u8         rtc_reparse_mode[0x5];
996 	u8         reserved_at_50[0x3];
997 	u8         rtc_index_mode[0x5];
998 	u8         reserved_at_58[0x3];
999 	u8         rtc_log_depth_max[0x5];
1000 
1001 	u8         reserved_at_60[0x10];
1002 	u8         ste_format[0x10];
1003 
1004 	u8         stc_action_type[0x80];
1005 
1006 	u8         header_insert_type[0x10];
1007 	u8         header_remove_type[0x10];
1008 
1009 	u8         trivial_match_definer[0x20];
1010 
1011 	u8         reserved_at_140[0x1b];
1012 	u8         rtc_max_num_hash_definer_gen_wqe[0x5];
1013 
1014 	u8         reserved_at_160[0x18];
1015 	u8         access_index_mode[0x8];
1016 
1017 	u8         reserved_at_180[0x10];
1018 	u8         ste_format_gen_wqe[0x10];
1019 
1020 	u8         linear_match_definer_reg_c3[0x20];
1021 
1022 	u8         fdb_jump_to_tir_stc[0x1];
1023 	u8         reserved_at_1c1[0x1f];
1024 };
1025 
1026 struct mlx5_ifc_esw_cap_bits {
1027 	u8         reserved_at_0[0x1d];
1028 	u8         merged_eswitch[0x1];
1029 	u8         reserved_at_1e[0x2];
1030 
1031 	u8         reserved_at_20[0x40];
1032 
1033 	u8         esw_manager_vport_number_valid[0x1];
1034 	u8         reserved_at_61[0xf];
1035 	u8         esw_manager_vport_number[0x10];
1036 
1037 	u8         reserved_at_80[0x780];
1038 };
1039 
1040 enum {
1041 	MLX5_COUNTER_SOURCE_ESWITCH = 0x0,
1042 	MLX5_COUNTER_FLOW_ESWITCH   = 0x1,
1043 };
1044 
1045 struct mlx5_ifc_e_switch_cap_bits {
1046 	u8         vport_svlan_strip[0x1];
1047 	u8         vport_cvlan_strip[0x1];
1048 	u8         vport_svlan_insert[0x1];
1049 	u8         vport_cvlan_insert_if_not_exist[0x1];
1050 	u8         vport_cvlan_insert_overwrite[0x1];
1051 	u8         reserved_at_5[0x1];
1052 	u8         vport_cvlan_insert_always[0x1];
1053 	u8         esw_shared_ingress_acl[0x1];
1054 	u8         esw_uplink_ingress_acl[0x1];
1055 	u8         root_ft_on_other_esw[0x1];
1056 	u8         reserved_at_a[0xf];
1057 	u8         esw_functions_changed[0x1];
1058 	u8         reserved_at_1a[0x1];
1059 	u8         ecpf_vport_exists[0x1];
1060 	u8         counter_eswitch_affinity[0x1];
1061 	u8         merged_eswitch[0x1];
1062 	u8         nic_vport_node_guid_modify[0x1];
1063 	u8         nic_vport_port_guid_modify[0x1];
1064 
1065 	u8         vxlan_encap_decap[0x1];
1066 	u8         nvgre_encap_decap[0x1];
1067 	u8         reserved_at_22[0x1];
1068 	u8         log_max_fdb_encap_uplink[0x5];
1069 	u8         reserved_at_21[0x3];
1070 	u8         log_max_packet_reformat_context[0x5];
1071 	u8         reserved_2b[0x6];
1072 	u8         max_encap_header_size[0xa];
1073 
1074 	u8         reserved_at_40[0xb];
1075 	u8         log_max_esw_sf[0x5];
1076 	u8         esw_sf_base_id[0x10];
1077 
1078 	u8         reserved_at_60[0x7a0];
1079 
1080 };
1081 
1082 struct mlx5_ifc_qos_cap_bits {
1083 	u8         packet_pacing[0x1];
1084 	u8         esw_scheduling[0x1];
1085 	u8         esw_bw_share[0x1];
1086 	u8         esw_rate_limit[0x1];
1087 	u8         reserved_at_4[0x1];
1088 	u8         packet_pacing_burst_bound[0x1];
1089 	u8         packet_pacing_typical_size[0x1];
1090 	u8         reserved_at_7[0x1];
1091 	u8         nic_sq_scheduling[0x1];
1092 	u8         nic_bw_share[0x1];
1093 	u8         nic_rate_limit[0x1];
1094 	u8         packet_pacing_uid[0x1];
1095 	u8         log_esw_max_sched_depth[0x4];
1096 	u8         reserved_at_10[0x10];
1097 
1098 	u8         reserved_at_20[0xb];
1099 	u8         log_max_qos_nic_queue_group[0x5];
1100 	u8         reserved_at_30[0x10];
1101 
1102 	u8         packet_pacing_max_rate[0x20];
1103 
1104 	u8         packet_pacing_min_rate[0x20];
1105 
1106 	u8         reserved_at_80[0x10];
1107 	u8         packet_pacing_rate_table_size[0x10];
1108 
1109 	u8         esw_element_type[0x10];
1110 	u8         esw_tsar_type[0x10];
1111 
1112 	u8         reserved_at_c0[0x10];
1113 	u8         max_qos_para_vport[0x10];
1114 
1115 	u8         max_tsar_bw_share[0x20];
1116 
1117 	u8         nic_element_type[0x10];
1118 	u8         nic_tsar_type[0x10];
1119 
1120 	u8         reserved_at_120[0x3];
1121 	u8         log_meter_aso_granularity[0x5];
1122 	u8         reserved_at_128[0x3];
1123 	u8         log_meter_aso_max_alloc[0x5];
1124 	u8         reserved_at_130[0x3];
1125 	u8         log_max_num_meter_aso[0x5];
1126 	u8         reserved_at_138[0x8];
1127 
1128 	u8         reserved_at_140[0x6c0];
1129 };
1130 
1131 struct mlx5_ifc_debug_cap_bits {
1132 	u8         core_dump_general[0x1];
1133 	u8         core_dump_qp[0x1];
1134 	u8         reserved_at_2[0x7];
1135 	u8         resource_dump[0x1];
1136 	u8         reserved_at_a[0x16];
1137 
1138 	u8         reserved_at_20[0x2];
1139 	u8         stall_detect[0x1];
1140 	u8         reserved_at_23[0x1d];
1141 
1142 	u8         reserved_at_40[0x7c0];
1143 };
1144 
1145 struct mlx5_ifc_per_protocol_networking_offload_caps_bits {
1146 	u8         csum_cap[0x1];
1147 	u8         vlan_cap[0x1];
1148 	u8         lro_cap[0x1];
1149 	u8         lro_psh_flag[0x1];
1150 	u8         lro_time_stamp[0x1];
1151 	u8         reserved_at_5[0x2];
1152 	u8         wqe_vlan_insert[0x1];
1153 	u8         self_lb_en_modifiable[0x1];
1154 	u8         reserved_at_9[0x2];
1155 	u8         max_lso_cap[0x5];
1156 	u8         multi_pkt_send_wqe[0x2];
1157 	u8	   wqe_inline_mode[0x2];
1158 	u8         rss_ind_tbl_cap[0x4];
1159 	u8         reg_umr_sq[0x1];
1160 	u8         scatter_fcs[0x1];
1161 	u8         enhanced_multi_pkt_send_wqe[0x1];
1162 	u8         tunnel_lso_const_out_ip_id[0x1];
1163 	u8         tunnel_lro_gre[0x1];
1164 	u8         tunnel_lro_vxlan[0x1];
1165 	u8         tunnel_stateless_gre[0x1];
1166 	u8         tunnel_stateless_vxlan[0x1];
1167 
1168 	u8         swp[0x1];
1169 	u8         swp_csum[0x1];
1170 	u8         swp_lso[0x1];
1171 	u8         cqe_checksum_full[0x1];
1172 	u8         tunnel_stateless_geneve_tx[0x1];
1173 	u8         tunnel_stateless_mpls_over_udp[0x1];
1174 	u8         tunnel_stateless_mpls_over_gre[0x1];
1175 	u8         tunnel_stateless_vxlan_gpe[0x1];
1176 	u8         tunnel_stateless_ipv4_over_vxlan[0x1];
1177 	u8         tunnel_stateless_ip_over_ip[0x1];
1178 	u8         insert_trailer[0x1];
1179 	u8         reserved_at_2b[0x1];
1180 	u8         tunnel_stateless_ip_over_ip_rx[0x1];
1181 	u8         tunnel_stateless_ip_over_ip_tx[0x1];
1182 	u8         reserved_at_2e[0x2];
1183 	u8         max_vxlan_udp_ports[0x8];
1184 	u8         swp_csum_l4_partial[0x1];
1185 	u8         reserved_at_39[0x5];
1186 	u8         max_geneve_opt_len[0x1];
1187 	u8         tunnel_stateless_geneve_rx[0x1];
1188 
1189 	u8         reserved_at_40[0x10];
1190 	u8         lro_min_mss_size[0x10];
1191 
1192 	u8         reserved_at_60[0x120];
1193 
1194 	u8         lro_timer_supported_periods[4][0x20];
1195 
1196 	u8         reserved_at_200[0x600];
1197 };
1198 
1199 enum {
1200 	MLX5_TIMESTAMP_FORMAT_CAP_FREE_RUNNING               = 0x0,
1201 	MLX5_TIMESTAMP_FORMAT_CAP_REAL_TIME                  = 0x1,
1202 	MLX5_TIMESTAMP_FORMAT_CAP_FREE_RUNNING_AND_REAL_TIME = 0x2,
1203 };
1204 
1205 struct mlx5_ifc_roce_cap_bits {
1206 	u8         roce_apm[0x1];
1207 	u8         reserved_at_1[0x3];
1208 	u8         sw_r_roce_src_udp_port[0x1];
1209 	u8         fl_rc_qp_when_roce_disabled[0x1];
1210 	u8         fl_rc_qp_when_roce_enabled[0x1];
1211 	u8         roce_cc_general[0x1];
1212 	u8	   qp_ooo_transmit_default[0x1];
1213 	u8         reserved_at_9[0x15];
1214 	u8	   qp_ts_format[0x2];
1215 
1216 	u8         reserved_at_20[0x60];
1217 
1218 	u8         reserved_at_80[0xc];
1219 	u8         l3_type[0x4];
1220 	u8         reserved_at_90[0x8];
1221 	u8         roce_version[0x8];
1222 
1223 	u8         reserved_at_a0[0x10];
1224 	u8         r_roce_dest_udp_port[0x10];
1225 
1226 	u8         r_roce_max_src_udp_port[0x10];
1227 	u8         r_roce_min_src_udp_port[0x10];
1228 
1229 	u8         reserved_at_e0[0x10];
1230 	u8         roce_address_table_size[0x10];
1231 
1232 	u8         reserved_at_100[0x700];
1233 };
1234 
1235 struct mlx5_ifc_sync_steering_in_bits {
1236 	u8         opcode[0x10];
1237 	u8         uid[0x10];
1238 
1239 	u8         reserved_at_20[0x10];
1240 	u8         op_mod[0x10];
1241 
1242 	u8         reserved_at_40[0xc0];
1243 };
1244 
1245 struct mlx5_ifc_sync_steering_out_bits {
1246 	u8         status[0x8];
1247 	u8         reserved_at_8[0x18];
1248 
1249 	u8         syndrome[0x20];
1250 
1251 	u8         reserved_at_40[0x40];
1252 };
1253 
1254 struct mlx5_ifc_sync_crypto_in_bits {
1255 	u8         opcode[0x10];
1256 	u8         uid[0x10];
1257 
1258 	u8         reserved_at_20[0x10];
1259 	u8         op_mod[0x10];
1260 
1261 	u8         reserved_at_40[0x20];
1262 
1263 	u8         reserved_at_60[0x10];
1264 	u8         crypto_type[0x10];
1265 
1266 	u8         reserved_at_80[0x80];
1267 };
1268 
1269 struct mlx5_ifc_sync_crypto_out_bits {
1270 	u8         status[0x8];
1271 	u8         reserved_at_8[0x18];
1272 
1273 	u8         syndrome[0x20];
1274 
1275 	u8         reserved_at_40[0x40];
1276 };
1277 
1278 struct mlx5_ifc_device_mem_cap_bits {
1279 	u8         memic[0x1];
1280 	u8         reserved_at_1[0x1f];
1281 
1282 	u8         reserved_at_20[0xb];
1283 	u8         log_min_memic_alloc_size[0x5];
1284 	u8         reserved_at_30[0x8];
1285 	u8	   log_max_memic_addr_alignment[0x8];
1286 
1287 	u8         memic_bar_start_addr[0x40];
1288 
1289 	u8         memic_bar_size[0x20];
1290 
1291 	u8         max_memic_size[0x20];
1292 
1293 	u8         steering_sw_icm_start_address[0x40];
1294 
1295 	u8         reserved_at_100[0x8];
1296 	u8         log_header_modify_sw_icm_size[0x8];
1297 	u8         reserved_at_110[0x2];
1298 	u8         log_sw_icm_alloc_granularity[0x6];
1299 	u8         log_steering_sw_icm_size[0x8];
1300 
1301 	u8         log_indirect_encap_sw_icm_size[0x8];
1302 	u8         reserved_at_128[0x10];
1303 	u8         log_header_modify_pattern_sw_icm_size[0x8];
1304 
1305 	u8         header_modify_sw_icm_start_address[0x40];
1306 
1307 	u8         reserved_at_180[0x40];
1308 
1309 	u8         header_modify_pattern_sw_icm_start_address[0x40];
1310 
1311 	u8         memic_operations[0x20];
1312 
1313 	u8         reserved_at_220[0x20];
1314 
1315 	u8         indirect_encap_sw_icm_start_address[0x40];
1316 
1317 	u8         reserved_at_280[0x580];
1318 };
1319 
1320 struct mlx5_ifc_device_event_cap_bits {
1321 	u8         user_affiliated_events[4][0x40];
1322 
1323 	u8         user_unaffiliated_events[4][0x40];
1324 };
1325 
1326 struct mlx5_ifc_virtio_emulation_cap_bits {
1327 	u8         desc_tunnel_offload_type[0x1];
1328 	u8         eth_frame_offload_type[0x1];
1329 	u8         virtio_version_1_0[0x1];
1330 	u8         device_features_bits_mask[0xd];
1331 	u8         event_mode[0x8];
1332 	u8         virtio_queue_type[0x8];
1333 
1334 	u8         max_tunnel_desc[0x10];
1335 	u8         reserved_at_30[0x3];
1336 	u8         log_doorbell_stride[0x5];
1337 	u8         reserved_at_38[0x3];
1338 	u8         log_doorbell_bar_size[0x5];
1339 
1340 	u8         doorbell_bar_offset[0x40];
1341 
1342 	u8         max_emulated_devices[0x8];
1343 	u8         max_num_virtio_queues[0x18];
1344 
1345 	u8         reserved_at_a0[0x20];
1346 
1347 	u8	   reserved_at_c0[0x13];
1348 	u8         desc_group_mkey_supported[0x1];
1349 	u8         freeze_to_rdy_supported[0x1];
1350 	u8         reserved_at_d5[0xb];
1351 
1352 	u8         reserved_at_e0[0x20];
1353 
1354 	u8         umem_1_buffer_param_a[0x20];
1355 
1356 	u8         umem_1_buffer_param_b[0x20];
1357 
1358 	u8         umem_2_buffer_param_a[0x20];
1359 
1360 	u8         umem_2_buffer_param_b[0x20];
1361 
1362 	u8         umem_3_buffer_param_a[0x20];
1363 
1364 	u8         umem_3_buffer_param_b[0x20];
1365 
1366 	u8         reserved_at_1c0[0x640];
1367 };
1368 
1369 enum {
1370 	MLX5_ATOMIC_CAPS_ATOMIC_SIZE_QP_1_BYTE     = 0x0,
1371 	MLX5_ATOMIC_CAPS_ATOMIC_SIZE_QP_2_BYTES    = 0x2,
1372 	MLX5_ATOMIC_CAPS_ATOMIC_SIZE_QP_4_BYTES    = 0x4,
1373 	MLX5_ATOMIC_CAPS_ATOMIC_SIZE_QP_8_BYTES    = 0x8,
1374 	MLX5_ATOMIC_CAPS_ATOMIC_SIZE_QP_16_BYTES   = 0x10,
1375 	MLX5_ATOMIC_CAPS_ATOMIC_SIZE_QP_32_BYTES   = 0x20,
1376 	MLX5_ATOMIC_CAPS_ATOMIC_SIZE_QP_64_BYTES   = 0x40,
1377 	MLX5_ATOMIC_CAPS_ATOMIC_SIZE_QP_128_BYTES  = 0x80,
1378 	MLX5_ATOMIC_CAPS_ATOMIC_SIZE_QP_256_BYTES  = 0x100,
1379 };
1380 
1381 enum {
1382 	MLX5_ATOMIC_CAPS_ATOMIC_SIZE_DC_1_BYTE     = 0x1,
1383 	MLX5_ATOMIC_CAPS_ATOMIC_SIZE_DC_2_BYTES    = 0x2,
1384 	MLX5_ATOMIC_CAPS_ATOMIC_SIZE_DC_4_BYTES    = 0x4,
1385 	MLX5_ATOMIC_CAPS_ATOMIC_SIZE_DC_8_BYTES    = 0x8,
1386 	MLX5_ATOMIC_CAPS_ATOMIC_SIZE_DC_16_BYTES   = 0x10,
1387 	MLX5_ATOMIC_CAPS_ATOMIC_SIZE_DC_32_BYTES   = 0x20,
1388 	MLX5_ATOMIC_CAPS_ATOMIC_SIZE_DC_64_BYTES   = 0x40,
1389 	MLX5_ATOMIC_CAPS_ATOMIC_SIZE_DC_128_BYTES  = 0x80,
1390 	MLX5_ATOMIC_CAPS_ATOMIC_SIZE_DC_256_BYTES  = 0x100,
1391 };
1392 
1393 struct mlx5_ifc_atomic_caps_bits {
1394 	u8         reserved_at_0[0x40];
1395 
1396 	u8         atomic_req_8B_endianness_mode[0x2];
1397 	u8         reserved_at_42[0x4];
1398 	u8         supported_atomic_req_8B_endianness_mode_1[0x1];
1399 
1400 	u8         reserved_at_47[0x19];
1401 
1402 	u8         reserved_at_60[0x20];
1403 
1404 	u8         reserved_at_80[0x10];
1405 	u8         atomic_operations[0x10];
1406 
1407 	u8         reserved_at_a0[0x10];
1408 	u8         atomic_size_qp[0x10];
1409 
1410 	u8         reserved_at_c0[0x10];
1411 	u8         atomic_size_dc[0x10];
1412 
1413 	u8         reserved_at_e0[0x720];
1414 };
1415 
1416 struct mlx5_ifc_odp_scheme_cap_bits {
1417 	u8         reserved_at_0[0x40];
1418 
1419 	u8         sig[0x1];
1420 	u8         reserved_at_41[0x4];
1421 	u8         page_prefetch[0x1];
1422 	u8         reserved_at_46[0x1a];
1423 
1424 	u8         reserved_at_60[0x20];
1425 
1426 	struct mlx5_ifc_odp_per_transport_service_cap_bits rc_odp_caps;
1427 
1428 	struct mlx5_ifc_odp_per_transport_service_cap_bits uc_odp_caps;
1429 
1430 	struct mlx5_ifc_odp_per_transport_service_cap_bits ud_odp_caps;
1431 
1432 	struct mlx5_ifc_odp_per_transport_service_cap_bits xrc_odp_caps;
1433 
1434 	struct mlx5_ifc_odp_per_transport_service_cap_bits dc_odp_caps;
1435 
1436 	u8         reserved_at_120[0xe0];
1437 };
1438 
1439 struct mlx5_ifc_odp_cap_bits {
1440 	struct mlx5_ifc_odp_scheme_cap_bits transport_page_fault_scheme_cap;
1441 
1442 	struct mlx5_ifc_odp_scheme_cap_bits memory_page_fault_scheme_cap;
1443 
1444 	u8         reserved_at_400[0x200];
1445 
1446 	u8         mem_page_fault[0x1];
1447 	u8         reserved_at_601[0x1f];
1448 
1449 	u8         reserved_at_620[0x1e0];
1450 };
1451 
1452 struct mlx5_ifc_tls_cap_bits {
1453 	u8         tls_1_2_aes_gcm_128[0x1];
1454 	u8         tls_1_3_aes_gcm_128[0x1];
1455 	u8         tls_1_2_aes_gcm_256[0x1];
1456 	u8         tls_1_3_aes_gcm_256[0x1];
1457 	u8         reserved_at_4[0x1c];
1458 
1459 	u8         reserved_at_20[0x7e0];
1460 };
1461 
1462 struct mlx5_ifc_ipsec_cap_bits {
1463 	u8         ipsec_full_offload[0x1];
1464 	u8         ipsec_crypto_offload[0x1];
1465 	u8         ipsec_esn[0x1];
1466 	u8         ipsec_crypto_esp_aes_gcm_256_encrypt[0x1];
1467 	u8         ipsec_crypto_esp_aes_gcm_128_encrypt[0x1];
1468 	u8         ipsec_crypto_esp_aes_gcm_256_decrypt[0x1];
1469 	u8         ipsec_crypto_esp_aes_gcm_128_decrypt[0x1];
1470 	u8         reserved_at_7[0x4];
1471 	u8         log_max_ipsec_offload[0x5];
1472 	u8         reserved_at_10[0x10];
1473 
1474 	u8         min_log_ipsec_full_replay_window[0x8];
1475 	u8         max_log_ipsec_full_replay_window[0x8];
1476 	u8         reserved_at_30[0x7d0];
1477 };
1478 
1479 struct mlx5_ifc_macsec_cap_bits {
1480 	u8    macsec_epn[0x1];
1481 	u8    reserved_at_1[0x2];
1482 	u8    macsec_crypto_esp_aes_gcm_256_encrypt[0x1];
1483 	u8    macsec_crypto_esp_aes_gcm_128_encrypt[0x1];
1484 	u8    macsec_crypto_esp_aes_gcm_256_decrypt[0x1];
1485 	u8    macsec_crypto_esp_aes_gcm_128_decrypt[0x1];
1486 	u8    reserved_at_7[0x4];
1487 	u8    log_max_macsec_offload[0x5];
1488 	u8    reserved_at_10[0x10];
1489 
1490 	u8    min_log_macsec_full_replay_window[0x8];
1491 	u8    max_log_macsec_full_replay_window[0x8];
1492 	u8    reserved_at_30[0x10];
1493 
1494 	u8    reserved_at_40[0x7c0];
1495 };
1496 
1497 enum {
1498 	MLX5_WQ_TYPE_LINKED_LIST  = 0x0,
1499 	MLX5_WQ_TYPE_CYCLIC       = 0x1,
1500 	MLX5_WQ_TYPE_LINKED_LIST_STRIDING_RQ = 0x2,
1501 	MLX5_WQ_TYPE_CYCLIC_STRIDING_RQ = 0x3,
1502 };
1503 
1504 enum {
1505 	MLX5_WQ_END_PAD_MODE_NONE   = 0x0,
1506 	MLX5_WQ_END_PAD_MODE_ALIGN  = 0x1,
1507 };
1508 
1509 enum {
1510 	MLX5_CMD_HCA_CAP_GID_TABLE_SIZE_8_GID_ENTRIES    = 0x0,
1511 	MLX5_CMD_HCA_CAP_GID_TABLE_SIZE_16_GID_ENTRIES   = 0x1,
1512 	MLX5_CMD_HCA_CAP_GID_TABLE_SIZE_32_GID_ENTRIES   = 0x2,
1513 	MLX5_CMD_HCA_CAP_GID_TABLE_SIZE_64_GID_ENTRIES   = 0x3,
1514 	MLX5_CMD_HCA_CAP_GID_TABLE_SIZE_128_GID_ENTRIES  = 0x4,
1515 };
1516 
1517 enum {
1518 	MLX5_CMD_HCA_CAP_PKEY_TABLE_SIZE_128_ENTRIES  = 0x0,
1519 	MLX5_CMD_HCA_CAP_PKEY_TABLE_SIZE_256_ENTRIES  = 0x1,
1520 	MLX5_CMD_HCA_CAP_PKEY_TABLE_SIZE_512_ENTRIES  = 0x2,
1521 	MLX5_CMD_HCA_CAP_PKEY_TABLE_SIZE_1K_ENTRIES   = 0x3,
1522 	MLX5_CMD_HCA_CAP_PKEY_TABLE_SIZE_2K_ENTRIES   = 0x4,
1523 	MLX5_CMD_HCA_CAP_PKEY_TABLE_SIZE_4K_ENTRIES   = 0x5,
1524 };
1525 
1526 enum {
1527 	MLX5_CMD_HCA_CAP_PORT_TYPE_IB        = 0x0,
1528 	MLX5_CMD_HCA_CAP_PORT_TYPE_ETHERNET  = 0x1,
1529 };
1530 
1531 enum {
1532 	MLX5_CMD_HCA_CAP_CMDIF_CHECKSUM_DISABLED       = 0x0,
1533 	MLX5_CMD_HCA_CAP_CMDIF_CHECKSUM_INITIAL_STATE  = 0x1,
1534 	MLX5_CMD_HCA_CAP_CMDIF_CHECKSUM_ENABLED        = 0x3,
1535 };
1536 
1537 enum {
1538 	MLX5_CAP_PORT_TYPE_IB  = 0x0,
1539 	MLX5_CAP_PORT_TYPE_ETH = 0x1,
1540 };
1541 
1542 enum {
1543 	MLX5_CAP_UMR_FENCE_STRONG	= 0x0,
1544 	MLX5_CAP_UMR_FENCE_SMALL	= 0x1,
1545 	MLX5_CAP_UMR_FENCE_NONE		= 0x2,
1546 };
1547 
1548 enum {
1549 	MLX5_FLEX_IPV4_OVER_VXLAN_ENABLED	= 1 << 0,
1550 	MLX5_FLEX_IPV6_OVER_VXLAN_ENABLED	= 1 << 1,
1551 	MLX5_FLEX_IPV6_OVER_IP_ENABLED		= 1 << 2,
1552 	MLX5_FLEX_PARSER_GENEVE_ENABLED		= 1 << 3,
1553 	MLX5_FLEX_PARSER_MPLS_OVER_GRE_ENABLED	= 1 << 4,
1554 	MLX5_FLEX_PARSER_MPLS_OVER_UDP_ENABLED	= 1 << 5,
1555 	MLX5_FLEX_P_BIT_VXLAN_GPE_ENABLED	= 1 << 6,
1556 	MLX5_FLEX_PARSER_VXLAN_GPE_ENABLED	= 1 << 7,
1557 	MLX5_FLEX_PARSER_ICMP_V4_ENABLED	= 1 << 8,
1558 	MLX5_FLEX_PARSER_ICMP_V6_ENABLED	= 1 << 9,
1559 	MLX5_FLEX_PARSER_GENEVE_TLV_OPTION_0_ENABLED = 1 << 10,
1560 	MLX5_FLEX_PARSER_GTPU_ENABLED		= 1 << 11,
1561 	MLX5_FLEX_PARSER_GTPU_DW_2_ENABLED	= 1 << 16,
1562 	MLX5_FLEX_PARSER_GTPU_FIRST_EXT_DW_0_ENABLED = 1 << 17,
1563 	MLX5_FLEX_PARSER_GTPU_DW_0_ENABLED	= 1 << 18,
1564 	MLX5_FLEX_PARSER_GTPU_TEID_ENABLED	= 1 << 19,
1565 };
1566 
1567 enum {
1568 	MLX5_UCTX_CAP_RAW_TX = 1UL << 0,
1569 	MLX5_UCTX_CAP_INTERNAL_DEV_RES = 1UL << 1,
1570 };
1571 
1572 #define MLX5_FC_BULK_SIZE_FACTOR 128
1573 
1574 enum mlx5_fc_bulk_alloc_bitmask {
1575 	MLX5_FC_BULK_128   = (1 << 0),
1576 	MLX5_FC_BULK_256   = (1 << 1),
1577 	MLX5_FC_BULK_512   = (1 << 2),
1578 	MLX5_FC_BULK_1024  = (1 << 3),
1579 	MLX5_FC_BULK_2048  = (1 << 4),
1580 	MLX5_FC_BULK_4096  = (1 << 5),
1581 	MLX5_FC_BULK_8192  = (1 << 6),
1582 	MLX5_FC_BULK_16384 = (1 << 7),
1583 };
1584 
1585 #define MLX5_FC_BULK_NUM_FCS(fc_enum) (MLX5_FC_BULK_SIZE_FACTOR * (fc_enum))
1586 
1587 #define MLX5_FT_MAX_MULTIPATH_LEVEL 63
1588 
1589 enum {
1590 	MLX5_STEERING_FORMAT_CONNECTX_5   = 0,
1591 	MLX5_STEERING_FORMAT_CONNECTX_6DX = 1,
1592 	MLX5_STEERING_FORMAT_CONNECTX_7   = 2,
1593 };
1594 
1595 struct mlx5_ifc_cmd_hca_cap_bits {
1596 	u8         reserved_at_0[0x6];
1597 	u8         page_request_disable[0x1];
1598 	u8         reserved_at_7[0x9];
1599 	u8         shared_object_to_user_object_allowed[0x1];
1600 	u8         reserved_at_13[0xe];
1601 	u8         vhca_resource_manager[0x1];
1602 
1603 	u8         hca_cap_2[0x1];
1604 	u8         create_lag_when_not_master_up[0x1];
1605 	u8         dtor[0x1];
1606 	u8         event_on_vhca_state_teardown_request[0x1];
1607 	u8         event_on_vhca_state_in_use[0x1];
1608 	u8         event_on_vhca_state_active[0x1];
1609 	u8         event_on_vhca_state_allocated[0x1];
1610 	u8         event_on_vhca_state_invalid[0x1];
1611 	u8         reserved_at_28[0x8];
1612 	u8         vhca_id[0x10];
1613 
1614 	u8         reserved_at_40[0x40];
1615 
1616 	u8         log_max_srq_sz[0x8];
1617 	u8         log_max_qp_sz[0x8];
1618 	u8         event_cap[0x1];
1619 	u8         reserved_at_91[0x2];
1620 	u8         isolate_vl_tc_new[0x1];
1621 	u8         reserved_at_94[0x4];
1622 	u8         prio_tag_required[0x1];
1623 	u8         reserved_at_99[0x2];
1624 	u8         log_max_qp[0x5];
1625 
1626 	u8         reserved_at_a0[0x3];
1627 	u8	   ece_support[0x1];
1628 	u8	   reserved_at_a4[0x5];
1629 	u8         reg_c_preserve[0x1];
1630 	u8         reserved_at_aa[0x1];
1631 	u8         log_max_srq[0x5];
1632 	u8         reserved_at_b0[0x1];
1633 	u8         uplink_follow[0x1];
1634 	u8         ts_cqe_to_dest_cqn[0x1];
1635 	u8         reserved_at_b3[0x6];
1636 	u8         go_back_n[0x1];
1637 	u8         reserved_at_ba[0x6];
1638 
1639 	u8         max_sgl_for_optimized_performance[0x8];
1640 	u8         log_max_cq_sz[0x8];
1641 	u8         relaxed_ordering_write_umr[0x1];
1642 	u8         relaxed_ordering_read_umr[0x1];
1643 	u8         reserved_at_d2[0x7];
1644 	u8         virtio_net_device_emualtion_manager[0x1];
1645 	u8         virtio_blk_device_emualtion_manager[0x1];
1646 	u8         log_max_cq[0x5];
1647 
1648 	u8         log_max_eq_sz[0x8];
1649 	u8         relaxed_ordering_write[0x1];
1650 	u8         relaxed_ordering_read_pci_enabled[0x1];
1651 	u8         log_max_mkey[0x6];
1652 	u8         reserved_at_f0[0x6];
1653 	u8	   terminate_scatter_list_mkey[0x1];
1654 	u8	   repeated_mkey[0x1];
1655 	u8         dump_fill_mkey[0x1];
1656 	u8         reserved_at_f9[0x2];
1657 	u8         fast_teardown[0x1];
1658 	u8         log_max_eq[0x4];
1659 
1660 	u8         max_indirection[0x8];
1661 	u8         fixed_buffer_size[0x1];
1662 	u8         log_max_mrw_sz[0x7];
1663 	u8         force_teardown[0x1];
1664 	u8         reserved_at_111[0x1];
1665 	u8         log_max_bsf_list_size[0x6];
1666 	u8         umr_extended_translation_offset[0x1];
1667 	u8         null_mkey[0x1];
1668 	u8         log_max_klm_list_size[0x6];
1669 
1670 	u8         reserved_at_120[0x2];
1671 	u8	   qpc_extension[0x1];
1672 	u8	   reserved_at_123[0x7];
1673 	u8         log_max_ra_req_dc[0x6];
1674 	u8         reserved_at_130[0x2];
1675 	u8         eth_wqe_too_small[0x1];
1676 	u8         reserved_at_133[0x6];
1677 	u8         vnic_env_cq_overrun[0x1];
1678 	u8         log_max_ra_res_dc[0x6];
1679 
1680 	u8         reserved_at_140[0x5];
1681 	u8         release_all_pages[0x1];
1682 	u8         must_not_use[0x1];
1683 	u8         reserved_at_147[0x2];
1684 	u8         roce_accl[0x1];
1685 	u8         log_max_ra_req_qp[0x6];
1686 	u8         reserved_at_150[0xa];
1687 	u8         log_max_ra_res_qp[0x6];
1688 
1689 	u8         end_pad[0x1];
1690 	u8         cc_query_allowed[0x1];
1691 	u8         cc_modify_allowed[0x1];
1692 	u8         start_pad[0x1];
1693 	u8         cache_line_128byte[0x1];
1694 	u8         reserved_at_165[0x4];
1695 	u8         rts2rts_qp_counters_set_id[0x1];
1696 	u8         reserved_at_16a[0x2];
1697 	u8         vnic_env_int_rq_oob[0x1];
1698 	u8         sbcam_reg[0x1];
1699 	u8         reserved_at_16e[0x1];
1700 	u8         qcam_reg[0x1];
1701 	u8         gid_table_size[0x10];
1702 
1703 	u8         out_of_seq_cnt[0x1];
1704 	u8         vport_counters[0x1];
1705 	u8         retransmission_q_counters[0x1];
1706 	u8         debug[0x1];
1707 	u8         modify_rq_counter_set_id[0x1];
1708 	u8         rq_delay_drop[0x1];
1709 	u8         max_qp_cnt[0xa];
1710 	u8         pkey_table_size[0x10];
1711 
1712 	u8         vport_group_manager[0x1];
1713 	u8         vhca_group_manager[0x1];
1714 	u8         ib_virt[0x1];
1715 	u8         eth_virt[0x1];
1716 	u8         vnic_env_queue_counters[0x1];
1717 	u8         ets[0x1];
1718 	u8         nic_flow_table[0x1];
1719 	u8         eswitch_manager[0x1];
1720 	u8         device_memory[0x1];
1721 	u8         mcam_reg[0x1];
1722 	u8         pcam_reg[0x1];
1723 	u8         local_ca_ack_delay[0x5];
1724 	u8         port_module_event[0x1];
1725 	u8         enhanced_error_q_counters[0x1];
1726 	u8         ports_check[0x1];
1727 	u8         reserved_at_1b3[0x1];
1728 	u8         disable_link_up[0x1];
1729 	u8         beacon_led[0x1];
1730 	u8         port_type[0x2];
1731 	u8         num_ports[0x8];
1732 
1733 	u8         reserved_at_1c0[0x1];
1734 	u8         pps[0x1];
1735 	u8         pps_modify[0x1];
1736 	u8         log_max_msg[0x5];
1737 	u8         reserved_at_1c8[0x4];
1738 	u8         max_tc[0x4];
1739 	u8         temp_warn_event[0x1];
1740 	u8         dcbx[0x1];
1741 	u8         general_notification_event[0x1];
1742 	u8         reserved_at_1d3[0x2];
1743 	u8         fpga[0x1];
1744 	u8         rol_s[0x1];
1745 	u8         rol_g[0x1];
1746 	u8         reserved_at_1d8[0x1];
1747 	u8         wol_s[0x1];
1748 	u8         wol_g[0x1];
1749 	u8         wol_a[0x1];
1750 	u8         wol_b[0x1];
1751 	u8         wol_m[0x1];
1752 	u8         wol_u[0x1];
1753 	u8         wol_p[0x1];
1754 
1755 	u8         stat_rate_support[0x10];
1756 	u8         reserved_at_1f0[0x1];
1757 	u8         pci_sync_for_fw_update_event[0x1];
1758 	u8         reserved_at_1f2[0x6];
1759 	u8         init2_lag_tx_port_affinity[0x1];
1760 	u8         reserved_at_1fa[0x2];
1761 	u8         wqe_based_flow_table_update_cap[0x1];
1762 	u8         cqe_version[0x4];
1763 
1764 	u8         compact_address_vector[0x1];
1765 	u8         striding_rq[0x1];
1766 	u8         reserved_at_202[0x1];
1767 	u8         ipoib_enhanced_offloads[0x1];
1768 	u8         ipoib_basic_offloads[0x1];
1769 	u8         reserved_at_205[0x1];
1770 	u8         repeated_block_disabled[0x1];
1771 	u8         umr_modify_entity_size_disabled[0x1];
1772 	u8         umr_modify_atomic_disabled[0x1];
1773 	u8         umr_indirect_mkey_disabled[0x1];
1774 	u8         umr_fence[0x2];
1775 	u8         dc_req_scat_data_cqe[0x1];
1776 	u8         reserved_at_20d[0x2];
1777 	u8         drain_sigerr[0x1];
1778 	u8         cmdif_checksum[0x2];
1779 	u8         sigerr_cqe[0x1];
1780 	u8         reserved_at_213[0x1];
1781 	u8         wq_signature[0x1];
1782 	u8         sctr_data_cqe[0x1];
1783 	u8         reserved_at_216[0x1];
1784 	u8         sho[0x1];
1785 	u8         tph[0x1];
1786 	u8         rf[0x1];
1787 	u8         dct[0x1];
1788 	u8         qos[0x1];
1789 	u8         eth_net_offloads[0x1];
1790 	u8         roce[0x1];
1791 	u8         atomic[0x1];
1792 	u8         reserved_at_21f[0x1];
1793 
1794 	u8         cq_oi[0x1];
1795 	u8         cq_resize[0x1];
1796 	u8         cq_moderation[0x1];
1797 	u8         cq_period_mode_modify[0x1];
1798 	u8         reserved_at_224[0x2];
1799 	u8         cq_eq_remap[0x1];
1800 	u8         pg[0x1];
1801 	u8         block_lb_mc[0x1];
1802 	u8         reserved_at_229[0x1];
1803 	u8         scqe_break_moderation[0x1];
1804 	u8         cq_period_start_from_cqe[0x1];
1805 	u8         cd[0x1];
1806 	u8         reserved_at_22d[0x1];
1807 	u8         apm[0x1];
1808 	u8         vector_calc[0x1];
1809 	u8         umr_ptr_rlky[0x1];
1810 	u8	   imaicl[0x1];
1811 	u8	   qp_packet_based[0x1];
1812 	u8         reserved_at_233[0x3];
1813 	u8         qkv[0x1];
1814 	u8         pkv[0x1];
1815 	u8         set_deth_sqpn[0x1];
1816 	u8         reserved_at_239[0x3];
1817 	u8         xrc[0x1];
1818 	u8         ud[0x1];
1819 	u8         uc[0x1];
1820 	u8         rc[0x1];
1821 
1822 	u8         uar_4k[0x1];
1823 	u8         reserved_at_241[0x7];
1824 	u8         fl_rc_qp_when_roce_disabled[0x1];
1825 	u8         regexp_params[0x1];
1826 	u8         uar_sz[0x6];
1827 	u8         port_selection_cap[0x1];
1828 	u8         reserved_at_251[0x1];
1829 	u8         umem_uid_0[0x1];
1830 	u8         reserved_at_253[0x5];
1831 	u8         log_pg_sz[0x8];
1832 
1833 	u8         bf[0x1];
1834 	u8         driver_version[0x1];
1835 	u8         pad_tx_eth_packet[0x1];
1836 	u8         reserved_at_263[0x3];
1837 	u8         mkey_by_name[0x1];
1838 	u8         reserved_at_267[0x4];
1839 
1840 	u8         log_bf_reg_size[0x5];
1841 
1842 	u8         reserved_at_270[0x3];
1843 	u8	   qp_error_syndrome[0x1];
1844 	u8	   reserved_at_274[0x2];
1845 	u8         lag_dct[0x2];
1846 	u8         lag_tx_port_affinity[0x1];
1847 	u8         lag_native_fdb_selection[0x1];
1848 	u8         reserved_at_27a[0x1];
1849 	u8         lag_master[0x1];
1850 	u8         num_lag_ports[0x4];
1851 
1852 	u8         reserved_at_280[0x10];
1853 	u8         max_wqe_sz_sq[0x10];
1854 
1855 	u8         reserved_at_2a0[0xb];
1856 	u8         shampo[0x1];
1857 	u8         reserved_at_2ac[0x4];
1858 	u8         max_wqe_sz_rq[0x10];
1859 
1860 	u8         max_flow_counter_31_16[0x10];
1861 	u8         max_wqe_sz_sq_dc[0x10];
1862 
1863 	u8         reserved_at_2e0[0x7];
1864 	u8         max_qp_mcg[0x19];
1865 
1866 	u8         reserved_at_300[0x10];
1867 	u8         flow_counter_bulk_alloc[0x8];
1868 	u8         log_max_mcg[0x8];
1869 
1870 	u8         reserved_at_320[0x3];
1871 	u8         log_max_transport_domain[0x5];
1872 	u8         reserved_at_328[0x2];
1873 	u8	   relaxed_ordering_read[0x1];
1874 	u8         log_max_pd[0x5];
1875 	u8         dp_ordering_ooo_all_ud[0x1];
1876 	u8         dp_ordering_ooo_all_uc[0x1];
1877 	u8         dp_ordering_ooo_all_xrc[0x1];
1878 	u8         dp_ordering_ooo_all_dc[0x1];
1879 	u8         dp_ordering_ooo_all_rc[0x1];
1880 	u8         pcie_reset_using_hotreset_method[0x1];
1881 	u8         pci_sync_for_fw_update_with_driver_unload[0x1];
1882 	u8         vnic_env_cnt_steering_fail[0x1];
1883 	u8         vport_counter_local_loopback[0x1];
1884 	u8         q_counter_aggregation[0x1];
1885 	u8         q_counter_other_vport[0x1];
1886 	u8         log_max_xrcd[0x5];
1887 
1888 	u8         nic_receive_steering_discard[0x1];
1889 	u8         receive_discard_vport_down[0x1];
1890 	u8         transmit_discard_vport_down[0x1];
1891 	u8         eq_overrun_count[0x1];
1892 	u8         reserved_at_344[0x1];
1893 	u8         invalid_command_count[0x1];
1894 	u8         quota_exceeded_count[0x1];
1895 	u8         reserved_at_347[0x1];
1896 	u8         log_max_flow_counter_bulk[0x8];
1897 	u8         max_flow_counter_15_0[0x10];
1898 
1899 
1900 	u8         reserved_at_360[0x3];
1901 	u8         log_max_rq[0x5];
1902 	u8         reserved_at_368[0x3];
1903 	u8         log_max_sq[0x5];
1904 	u8         reserved_at_370[0x3];
1905 	u8         log_max_tir[0x5];
1906 	u8         reserved_at_378[0x3];
1907 	u8         log_max_tis[0x5];
1908 
1909 	u8         basic_cyclic_rcv_wqe[0x1];
1910 	u8         reserved_at_381[0x2];
1911 	u8         log_max_rmp[0x5];
1912 	u8         reserved_at_388[0x3];
1913 	u8         log_max_rqt[0x5];
1914 	u8         reserved_at_390[0x3];
1915 	u8         log_max_rqt_size[0x5];
1916 	u8         reserved_at_398[0x3];
1917 	u8         log_max_tis_per_sq[0x5];
1918 
1919 	u8         ext_stride_num_range[0x1];
1920 	u8         roce_rw_supported[0x1];
1921 	u8         log_max_current_uc_list_wr_supported[0x1];
1922 	u8         log_max_stride_sz_rq[0x5];
1923 	u8         reserved_at_3a8[0x3];
1924 	u8         log_min_stride_sz_rq[0x5];
1925 	u8         reserved_at_3b0[0x3];
1926 	u8         log_max_stride_sz_sq[0x5];
1927 	u8         reserved_at_3b8[0x3];
1928 	u8         log_min_stride_sz_sq[0x5];
1929 
1930 	u8         hairpin[0x1];
1931 	u8         reserved_at_3c1[0x2];
1932 	u8         log_max_hairpin_queues[0x5];
1933 	u8         reserved_at_3c8[0x3];
1934 	u8         log_max_hairpin_wq_data_sz[0x5];
1935 	u8         reserved_at_3d0[0x3];
1936 	u8         log_max_hairpin_num_packets[0x5];
1937 	u8         reserved_at_3d8[0x3];
1938 	u8         log_max_wq_sz[0x5];
1939 
1940 	u8         nic_vport_change_event[0x1];
1941 	u8         disable_local_lb_uc[0x1];
1942 	u8         disable_local_lb_mc[0x1];
1943 	u8         log_min_hairpin_wq_data_sz[0x5];
1944 	u8         reserved_at_3e8[0x1];
1945 	u8         silent_mode[0x1];
1946 	u8         vhca_state[0x1];
1947 	u8         log_max_vlan_list[0x5];
1948 	u8         reserved_at_3f0[0x3];
1949 	u8         log_max_current_mc_list[0x5];
1950 	u8         reserved_at_3f8[0x3];
1951 	u8         log_max_current_uc_list[0x5];
1952 
1953 	u8         general_obj_types[0x40];
1954 
1955 	u8         sq_ts_format[0x2];
1956 	u8         rq_ts_format[0x2];
1957 	u8         steering_format_version[0x4];
1958 	u8         create_qp_start_hint[0x18];
1959 
1960 	u8         reserved_at_460[0x1];
1961 	u8         ats[0x1];
1962 	u8         cross_vhca_rqt[0x1];
1963 	u8         log_max_uctx[0x5];
1964 	u8         reserved_at_468[0x1];
1965 	u8         crypto[0x1];
1966 	u8         ipsec_offload[0x1];
1967 	u8         log_max_umem[0x5];
1968 	u8         max_num_eqs[0x10];
1969 
1970 	u8         reserved_at_480[0x1];
1971 	u8         tls_tx[0x1];
1972 	u8         tls_rx[0x1];
1973 	u8         log_max_l2_table[0x5];
1974 	u8         reserved_at_488[0x8];
1975 	u8         log_uar_page_sz[0x10];
1976 
1977 	u8         reserved_at_4a0[0x20];
1978 	u8         device_frequency_mhz[0x20];
1979 	u8         device_frequency_khz[0x20];
1980 
1981 	u8         reserved_at_500[0x20];
1982 	u8	   num_of_uars_per_page[0x20];
1983 
1984 	u8         flex_parser_protocols[0x20];
1985 
1986 	u8         max_geneve_tlv_options[0x8];
1987 	u8         reserved_at_568[0x3];
1988 	u8         max_geneve_tlv_option_data_len[0x5];
1989 	u8         reserved_at_570[0x9];
1990 	u8         adv_virtualization[0x1];
1991 	u8         reserved_at_57a[0x6];
1992 
1993 	u8	   reserved_at_580[0xb];
1994 	u8	   log_max_dci_stream_channels[0x5];
1995 	u8	   reserved_at_590[0x3];
1996 	u8	   log_max_dci_errored_streams[0x5];
1997 	u8	   reserved_at_598[0x8];
1998 
1999 	u8         reserved_at_5a0[0x10];
2000 	u8         enhanced_cqe_compression[0x1];
2001 	u8         reserved_at_5b1[0x1];
2002 	u8         crossing_vhca_mkey[0x1];
2003 	u8         log_max_dek[0x5];
2004 	u8         reserved_at_5b8[0x4];
2005 	u8         mini_cqe_resp_stride_index[0x1];
2006 	u8         cqe_128_always[0x1];
2007 	u8         cqe_compression_128[0x1];
2008 	u8         cqe_compression[0x1];
2009 
2010 	u8         cqe_compression_timeout[0x10];
2011 	u8         cqe_compression_max_num[0x10];
2012 
2013 	u8         reserved_at_5e0[0x8];
2014 	u8         flex_parser_id_gtpu_dw_0[0x4];
2015 	u8         reserved_at_5ec[0x4];
2016 	u8         tag_matching[0x1];
2017 	u8         rndv_offload_rc[0x1];
2018 	u8         rndv_offload_dc[0x1];
2019 	u8         log_tag_matching_list_sz[0x5];
2020 	u8         reserved_at_5f8[0x3];
2021 	u8         log_max_xrq[0x5];
2022 
2023 	u8	   affiliate_nic_vport_criteria[0x8];
2024 	u8	   native_port_num[0x8];
2025 	u8	   num_vhca_ports[0x8];
2026 	u8         flex_parser_id_gtpu_teid[0x4];
2027 	u8         reserved_at_61c[0x2];
2028 	u8	   sw_owner_id[0x1];
2029 	u8         reserved_at_61f[0x1];
2030 
2031 	u8         max_num_of_monitor_counters[0x10];
2032 	u8         num_ppcnt_monitor_counters[0x10];
2033 
2034 	u8         max_num_sf[0x10];
2035 	u8         num_q_monitor_counters[0x10];
2036 
2037 	u8         reserved_at_660[0x20];
2038 
2039 	u8         sf[0x1];
2040 	u8         sf_set_partition[0x1];
2041 	u8         reserved_at_682[0x1];
2042 	u8         log_max_sf[0x5];
2043 	u8         apu[0x1];
2044 	u8         reserved_at_689[0x4];
2045 	u8         migration[0x1];
2046 	u8         reserved_at_68e[0x2];
2047 	u8         log_min_sf_size[0x8];
2048 	u8         max_num_sf_partitions[0x8];
2049 
2050 	u8         uctx_cap[0x20];
2051 
2052 	u8         reserved_at_6c0[0x4];
2053 	u8         flex_parser_id_geneve_tlv_option_0[0x4];
2054 	u8         flex_parser_id_icmp_dw1[0x4];
2055 	u8         flex_parser_id_icmp_dw0[0x4];
2056 	u8         flex_parser_id_icmpv6_dw1[0x4];
2057 	u8         flex_parser_id_icmpv6_dw0[0x4];
2058 	u8         flex_parser_id_outer_first_mpls_over_gre[0x4];
2059 	u8         flex_parser_id_outer_first_mpls_over_udp_label[0x4];
2060 
2061 	u8         max_num_match_definer[0x10];
2062 	u8	   sf_base_id[0x10];
2063 
2064 	u8         flex_parser_id_gtpu_dw_2[0x4];
2065 	u8         flex_parser_id_gtpu_first_ext_dw_0[0x4];
2066 	u8	   num_total_dynamic_vf_msix[0x18];
2067 	u8	   reserved_at_720[0x14];
2068 	u8	   dynamic_msix_table_size[0xc];
2069 	u8	   reserved_at_740[0xc];
2070 	u8	   min_dynamic_vf_msix_table_size[0x4];
2071 	u8	   reserved_at_750[0x2];
2072 	u8	   data_direct[0x1];
2073 	u8	   reserved_at_753[0x1];
2074 	u8	   max_dynamic_vf_msix_table_size[0xc];
2075 
2076 	u8         reserved_at_760[0x3];
2077 	u8         log_max_num_header_modify_argument[0x5];
2078 	u8         log_header_modify_argument_granularity_offset[0x4];
2079 	u8         log_header_modify_argument_granularity[0x4];
2080 	u8         reserved_at_770[0x3];
2081 	u8         log_header_modify_argument_max_alloc[0x5];
2082 	u8         reserved_at_778[0x8];
2083 
2084 	u8	   vhca_tunnel_commands[0x40];
2085 	u8         match_definer_format_supported[0x40];
2086 };
2087 
2088 enum {
2089 	MLX5_CROSS_VHCA_OBJ_TO_OBJ_SUPPORTED_LOCAL_FLOW_TABLE_TO_REMOTE_FLOW_TABLE_MISS  = 0x80000,
2090 	MLX5_CROSS_VHCA_OBJ_TO_OBJ_SUPPORTED_LOCAL_FLOW_TABLE_ROOT_TO_REMOTE_FLOW_TABLE  = (1ULL << 20),
2091 };
2092 
2093 enum {
2094 	MLX5_ALLOWED_OBJ_FOR_OTHER_VHCA_ACCESS_FLOW_TABLE       = 0x200,
2095 };
2096 
2097 struct mlx5_ifc_cmd_hca_cap_2_bits {
2098 	u8	   reserved_at_0[0x80];
2099 
2100 	u8         migratable[0x1];
2101 	u8         reserved_at_81[0x7];
2102 	u8         dp_ordering_force[0x1];
2103 	u8         reserved_at_89[0x9];
2104 	u8         query_vuid[0x1];
2105 	u8         reserved_at_93[0x5];
2106 	u8         umr_log_entity_size_5[0x1];
2107 	u8         reserved_at_99[0x7];
2108 
2109 	u8	   max_reformat_insert_size[0x8];
2110 	u8	   max_reformat_insert_offset[0x8];
2111 	u8	   max_reformat_remove_size[0x8];
2112 	u8	   max_reformat_remove_offset[0x8];
2113 
2114 	u8	   reserved_at_c0[0x8];
2115 	u8	   migration_multi_load[0x1];
2116 	u8	   migration_tracking_state[0x1];
2117 	u8	   multiplane_qp_ud[0x1];
2118 	u8	   reserved_at_cb[0x5];
2119 	u8	   migration_in_chunks[0x1];
2120 	u8	   reserved_at_d1[0x1];
2121 	u8	   sf_eq_usage[0x1];
2122 	u8	   reserved_at_d3[0x5];
2123 	u8	   multiplane[0x1];
2124 	u8	   reserved_at_d9[0x7];
2125 
2126 	u8	   cross_vhca_object_to_object_supported[0x20];
2127 
2128 	u8	   allowed_object_for_other_vhca_access[0x40];
2129 
2130 	u8	   reserved_at_140[0x60];
2131 
2132 	u8	   flow_table_type_2_type[0x8];
2133 	u8	   reserved_at_1a8[0x2];
2134 	u8         format_select_dw_8_6_ext[0x1];
2135 	u8	   log_min_mkey_entity_size[0x5];
2136 	u8	   reserved_at_1b0[0x10];
2137 
2138 	u8	   reserved_at_1c0[0x60];
2139 
2140 	u8	   reserved_at_220[0x1];
2141 	u8	   sw_vhca_id_valid[0x1];
2142 	u8	   sw_vhca_id[0xe];
2143 	u8	   reserved_at_230[0x10];
2144 
2145 	u8	   reserved_at_240[0xb];
2146 	u8	   ts_cqe_metadata_size2wqe_counter[0x5];
2147 	u8	   reserved_at_250[0x10];
2148 
2149 	u8	   reserved_at_260[0x20];
2150 
2151 	u8	   format_select_dw_gtpu_dw_0[0x8];
2152 	u8	   format_select_dw_gtpu_dw_1[0x8];
2153 	u8	   format_select_dw_gtpu_dw_2[0x8];
2154 	u8	   format_select_dw_gtpu_first_ext_dw_0[0x8];
2155 
2156 	u8	   generate_wqe_type[0x20];
2157 
2158 	u8	   reserved_at_2c0[0xc0];
2159 
2160 	u8	   reserved_at_380[0xb];
2161 	u8	   min_mkey_log_entity_size_fixed_buffer[0x5];
2162 	u8	   ec_vf_vport_base[0x10];
2163 
2164 	u8	   reserved_at_3a0[0xa];
2165 	u8	   max_mkey_log_entity_size_mtt[0x6];
2166 	u8	   max_rqt_vhca_id[0x10];
2167 
2168 	u8	   reserved_at_3c0[0x20];
2169 
2170 	u8	   reserved_at_3e0[0x10];
2171 	u8	   pcc_ifa2[0x1];
2172 	u8	   reserved_at_3f1[0xf];
2173 
2174 	u8	   reserved_at_400[0x1];
2175 	u8	   min_mkey_log_entity_size_fixed_buffer_valid[0x1];
2176 	u8	   reserved_at_402[0xe];
2177 	u8	   return_reg_id[0x10];
2178 
2179 	u8	   reserved_at_420[0x1c];
2180 	u8	   flow_table_hash_type[0x4];
2181 
2182 	u8	   reserved_at_440[0x8];
2183 	u8	   max_num_eqs_24b[0x18];
2184 	u8	   reserved_at_460[0x3a0];
2185 };
2186 
2187 enum mlx5_ifc_flow_destination_type {
2188 	MLX5_IFC_FLOW_DESTINATION_TYPE_VPORT        = 0x0,
2189 	MLX5_IFC_FLOW_DESTINATION_TYPE_FLOW_TABLE   = 0x1,
2190 	MLX5_IFC_FLOW_DESTINATION_TYPE_TIR          = 0x2,
2191 	MLX5_IFC_FLOW_DESTINATION_TYPE_FLOW_SAMPLER = 0x6,
2192 	MLX5_IFC_FLOW_DESTINATION_TYPE_UPLINK       = 0x8,
2193 	MLX5_IFC_FLOW_DESTINATION_TYPE_TABLE_TYPE   = 0xA,
2194 };
2195 
2196 enum mlx5_flow_table_miss_action {
2197 	MLX5_FLOW_TABLE_MISS_ACTION_DEF,
2198 	MLX5_FLOW_TABLE_MISS_ACTION_FWD,
2199 	MLX5_FLOW_TABLE_MISS_ACTION_SWITCH_DOMAIN,
2200 };
2201 
2202 struct mlx5_ifc_dest_format_struct_bits {
2203 	u8         destination_type[0x8];
2204 	u8         destination_id[0x18];
2205 
2206 	u8         destination_eswitch_owner_vhca_id_valid[0x1];
2207 	u8         packet_reformat[0x1];
2208 	u8         reserved_at_22[0x6];
2209 	u8         destination_table_type[0x8];
2210 	u8         destination_eswitch_owner_vhca_id[0x10];
2211 };
2212 
2213 struct mlx5_ifc_flow_counter_list_bits {
2214 	u8         flow_counter_id[0x20];
2215 
2216 	u8         reserved_at_20[0x20];
2217 };
2218 
2219 struct mlx5_ifc_extended_dest_format_bits {
2220 	struct mlx5_ifc_dest_format_struct_bits destination_entry;
2221 
2222 	u8         packet_reformat_id[0x20];
2223 
2224 	u8         reserved_at_60[0x20];
2225 };
2226 
2227 union mlx5_ifc_dest_format_flow_counter_list_auto_bits {
2228 	struct mlx5_ifc_extended_dest_format_bits extended_dest_format;
2229 	struct mlx5_ifc_flow_counter_list_bits flow_counter_list;
2230 };
2231 
2232 struct mlx5_ifc_fte_match_param_bits {
2233 	struct mlx5_ifc_fte_match_set_lyr_2_4_bits outer_headers;
2234 
2235 	struct mlx5_ifc_fte_match_set_misc_bits misc_parameters;
2236 
2237 	struct mlx5_ifc_fte_match_set_lyr_2_4_bits inner_headers;
2238 
2239 	struct mlx5_ifc_fte_match_set_misc2_bits misc_parameters_2;
2240 
2241 	struct mlx5_ifc_fte_match_set_misc3_bits misc_parameters_3;
2242 
2243 	struct mlx5_ifc_fte_match_set_misc4_bits misc_parameters_4;
2244 
2245 	struct mlx5_ifc_fte_match_set_misc5_bits misc_parameters_5;
2246 
2247 	u8         reserved_at_e00[0x200];
2248 };
2249 
2250 enum {
2251 	MLX5_RX_HASH_FIELD_SELECT_SELECTED_FIELDS_SRC_IP     = 0x0,
2252 	MLX5_RX_HASH_FIELD_SELECT_SELECTED_FIELDS_DST_IP     = 0x1,
2253 	MLX5_RX_HASH_FIELD_SELECT_SELECTED_FIELDS_L4_SPORT   = 0x2,
2254 	MLX5_RX_HASH_FIELD_SELECT_SELECTED_FIELDS_L4_DPORT   = 0x3,
2255 	MLX5_RX_HASH_FIELD_SELECT_SELECTED_FIELDS_IPSEC_SPI  = 0x4,
2256 };
2257 
2258 struct mlx5_ifc_rx_hash_field_select_bits {
2259 	u8         l3_prot_type[0x1];
2260 	u8         l4_prot_type[0x1];
2261 	u8         selected_fields[0x1e];
2262 };
2263 
2264 enum {
2265 	MLX5_WQ_WQ_TYPE_WQ_LINKED_LIST  = 0x0,
2266 	MLX5_WQ_WQ_TYPE_WQ_CYCLIC       = 0x1,
2267 };
2268 
2269 enum {
2270 	MLX5_WQ_END_PADDING_MODE_END_PAD_NONE   = 0x0,
2271 	MLX5_WQ_END_PADDING_MODE_END_PAD_ALIGN  = 0x1,
2272 };
2273 
2274 struct mlx5_ifc_wq_bits {
2275 	u8         wq_type[0x4];
2276 	u8         wq_signature[0x1];
2277 	u8         end_padding_mode[0x2];
2278 	u8         cd_slave[0x1];
2279 	u8         reserved_at_8[0x18];
2280 
2281 	u8         hds_skip_first_sge[0x1];
2282 	u8         log2_hds_buf_size[0x3];
2283 	u8         reserved_at_24[0x7];
2284 	u8         page_offset[0x5];
2285 	u8         lwm[0x10];
2286 
2287 	u8         reserved_at_40[0x8];
2288 	u8         pd[0x18];
2289 
2290 	u8         reserved_at_60[0x8];
2291 	u8         uar_page[0x18];
2292 
2293 	u8         dbr_addr[0x40];
2294 
2295 	u8         hw_counter[0x20];
2296 
2297 	u8         sw_counter[0x20];
2298 
2299 	u8         reserved_at_100[0xc];
2300 	u8         log_wq_stride[0x4];
2301 	u8         reserved_at_110[0x3];
2302 	u8         log_wq_pg_sz[0x5];
2303 	u8         reserved_at_118[0x3];
2304 	u8         log_wq_sz[0x5];
2305 
2306 	u8         dbr_umem_valid[0x1];
2307 	u8         wq_umem_valid[0x1];
2308 	u8         reserved_at_122[0x1];
2309 	u8         log_hairpin_num_packets[0x5];
2310 	u8         reserved_at_128[0x3];
2311 	u8         log_hairpin_data_sz[0x5];
2312 
2313 	u8         reserved_at_130[0x4];
2314 	u8         log_wqe_num_of_strides[0x4];
2315 	u8         two_byte_shift_en[0x1];
2316 	u8         reserved_at_139[0x4];
2317 	u8         log_wqe_stride_size[0x3];
2318 
2319 	u8         dbr_umem_id[0x20];
2320 	u8         wq_umem_id[0x20];
2321 
2322 	u8         wq_umem_offset[0x40];
2323 
2324 	u8         headers_mkey[0x20];
2325 
2326 	u8         shampo_enable[0x1];
2327 	u8         reserved_at_1e1[0x4];
2328 	u8         log_reservation_size[0x3];
2329 	u8         reserved_at_1e8[0x5];
2330 	u8         log_max_num_of_packets_per_reservation[0x3];
2331 	u8         reserved_at_1f0[0x6];
2332 	u8         log_headers_entry_size[0x2];
2333 	u8         reserved_at_1f8[0x4];
2334 	u8         log_headers_buffer_entry_num[0x4];
2335 
2336 	u8         reserved_at_200[0x400];
2337 
2338 	struct mlx5_ifc_cmd_pas_bits pas[];
2339 };
2340 
2341 struct mlx5_ifc_rq_num_bits {
2342 	u8         reserved_at_0[0x8];
2343 	u8         rq_num[0x18];
2344 };
2345 
2346 struct mlx5_ifc_rq_vhca_bits {
2347 	u8         reserved_at_0[0x8];
2348 	u8         rq_num[0x18];
2349 	u8         reserved_at_20[0x10];
2350 	u8         rq_vhca_id[0x10];
2351 };
2352 
2353 struct mlx5_ifc_mac_address_layout_bits {
2354 	u8         reserved_at_0[0x10];
2355 	u8         mac_addr_47_32[0x10];
2356 
2357 	u8         mac_addr_31_0[0x20];
2358 };
2359 
2360 struct mlx5_ifc_vlan_layout_bits {
2361 	u8         reserved_at_0[0x14];
2362 	u8         vlan[0x0c];
2363 
2364 	u8         reserved_at_20[0x20];
2365 };
2366 
2367 struct mlx5_ifc_cong_control_r_roce_ecn_np_bits {
2368 	u8         reserved_at_0[0xa0];
2369 
2370 	u8         min_time_between_cnps[0x20];
2371 
2372 	u8         reserved_at_c0[0x12];
2373 	u8         cnp_dscp[0x6];
2374 	u8         reserved_at_d8[0x4];
2375 	u8         cnp_prio_mode[0x1];
2376 	u8         cnp_802p_prio[0x3];
2377 
2378 	u8         reserved_at_e0[0x720];
2379 };
2380 
2381 struct mlx5_ifc_cong_control_r_roce_ecn_rp_bits {
2382 	u8         reserved_at_0[0x60];
2383 
2384 	u8         reserved_at_60[0x4];
2385 	u8         clamp_tgt_rate[0x1];
2386 	u8         reserved_at_65[0x3];
2387 	u8         clamp_tgt_rate_after_time_inc[0x1];
2388 	u8         reserved_at_69[0x17];
2389 
2390 	u8         reserved_at_80[0x20];
2391 
2392 	u8         rpg_time_reset[0x20];
2393 
2394 	u8         rpg_byte_reset[0x20];
2395 
2396 	u8         rpg_threshold[0x20];
2397 
2398 	u8         rpg_max_rate[0x20];
2399 
2400 	u8         rpg_ai_rate[0x20];
2401 
2402 	u8         rpg_hai_rate[0x20];
2403 
2404 	u8         rpg_gd[0x20];
2405 
2406 	u8         rpg_min_dec_fac[0x20];
2407 
2408 	u8         rpg_min_rate[0x20];
2409 
2410 	u8         reserved_at_1c0[0xe0];
2411 
2412 	u8         rate_to_set_on_first_cnp[0x20];
2413 
2414 	u8         dce_tcp_g[0x20];
2415 
2416 	u8         dce_tcp_rtt[0x20];
2417 
2418 	u8         rate_reduce_monitor_period[0x20];
2419 
2420 	u8         reserved_at_320[0x20];
2421 
2422 	u8         initial_alpha_value[0x20];
2423 
2424 	u8         reserved_at_360[0x4a0];
2425 };
2426 
2427 struct mlx5_ifc_cong_control_r_roce_general_bits {
2428 	u8         reserved_at_0[0x80];
2429 
2430 	u8         reserved_at_80[0x10];
2431 	u8         rtt_resp_dscp_valid[0x1];
2432 	u8         reserved_at_91[0x9];
2433 	u8         rtt_resp_dscp[0x6];
2434 
2435 	u8         reserved_at_a0[0x760];
2436 };
2437 
2438 struct mlx5_ifc_cong_control_802_1qau_rp_bits {
2439 	u8         reserved_at_0[0x80];
2440 
2441 	u8         rppp_max_rps[0x20];
2442 
2443 	u8         rpg_time_reset[0x20];
2444 
2445 	u8         rpg_byte_reset[0x20];
2446 
2447 	u8         rpg_threshold[0x20];
2448 
2449 	u8         rpg_max_rate[0x20];
2450 
2451 	u8         rpg_ai_rate[0x20];
2452 
2453 	u8         rpg_hai_rate[0x20];
2454 
2455 	u8         rpg_gd[0x20];
2456 
2457 	u8         rpg_min_dec_fac[0x20];
2458 
2459 	u8         rpg_min_rate[0x20];
2460 
2461 	u8         reserved_at_1c0[0x640];
2462 };
2463 
2464 enum {
2465 	MLX5_RESIZE_FIELD_SELECT_RESIZE_FIELD_SELECT_LOG_CQ_SIZE    = 0x1,
2466 	MLX5_RESIZE_FIELD_SELECT_RESIZE_FIELD_SELECT_PAGE_OFFSET    = 0x2,
2467 	MLX5_RESIZE_FIELD_SELECT_RESIZE_FIELD_SELECT_LOG_PAGE_SIZE  = 0x4,
2468 };
2469 
2470 struct mlx5_ifc_resize_field_select_bits {
2471 	u8         resize_field_select[0x20];
2472 };
2473 
2474 struct mlx5_ifc_resource_dump_bits {
2475 	u8         more_dump[0x1];
2476 	u8         inline_dump[0x1];
2477 	u8         reserved_at_2[0xa];
2478 	u8         seq_num[0x4];
2479 	u8         segment_type[0x10];
2480 
2481 	u8         reserved_at_20[0x10];
2482 	u8         vhca_id[0x10];
2483 
2484 	u8         index1[0x20];
2485 
2486 	u8         index2[0x20];
2487 
2488 	u8         num_of_obj1[0x10];
2489 	u8         num_of_obj2[0x10];
2490 
2491 	u8         reserved_at_a0[0x20];
2492 
2493 	u8         device_opaque[0x40];
2494 
2495 	u8         mkey[0x20];
2496 
2497 	u8         size[0x20];
2498 
2499 	u8         address[0x40];
2500 
2501 	u8         inline_data[52][0x20];
2502 };
2503 
2504 struct mlx5_ifc_resource_dump_menu_record_bits {
2505 	u8         reserved_at_0[0x4];
2506 	u8         num_of_obj2_supports_active[0x1];
2507 	u8         num_of_obj2_supports_all[0x1];
2508 	u8         must_have_num_of_obj2[0x1];
2509 	u8         support_num_of_obj2[0x1];
2510 	u8         num_of_obj1_supports_active[0x1];
2511 	u8         num_of_obj1_supports_all[0x1];
2512 	u8         must_have_num_of_obj1[0x1];
2513 	u8         support_num_of_obj1[0x1];
2514 	u8         must_have_index2[0x1];
2515 	u8         support_index2[0x1];
2516 	u8         must_have_index1[0x1];
2517 	u8         support_index1[0x1];
2518 	u8         segment_type[0x10];
2519 
2520 	u8         segment_name[4][0x20];
2521 
2522 	u8         index1_name[4][0x20];
2523 
2524 	u8         index2_name[4][0x20];
2525 };
2526 
2527 struct mlx5_ifc_resource_dump_segment_header_bits {
2528 	u8         length_dw[0x10];
2529 	u8         segment_type[0x10];
2530 };
2531 
2532 struct mlx5_ifc_resource_dump_command_segment_bits {
2533 	struct mlx5_ifc_resource_dump_segment_header_bits segment_header;
2534 
2535 	u8         segment_called[0x10];
2536 	u8         vhca_id[0x10];
2537 
2538 	u8         index1[0x20];
2539 
2540 	u8         index2[0x20];
2541 
2542 	u8         num_of_obj1[0x10];
2543 	u8         num_of_obj2[0x10];
2544 };
2545 
2546 struct mlx5_ifc_resource_dump_error_segment_bits {
2547 	struct mlx5_ifc_resource_dump_segment_header_bits segment_header;
2548 
2549 	u8         reserved_at_20[0x10];
2550 	u8         syndrome_id[0x10];
2551 
2552 	u8         reserved_at_40[0x40];
2553 
2554 	u8         error[8][0x20];
2555 };
2556 
2557 struct mlx5_ifc_resource_dump_info_segment_bits {
2558 	struct mlx5_ifc_resource_dump_segment_header_bits segment_header;
2559 
2560 	u8         reserved_at_20[0x18];
2561 	u8         dump_version[0x8];
2562 
2563 	u8         hw_version[0x20];
2564 
2565 	u8         fw_version[0x20];
2566 };
2567 
2568 struct mlx5_ifc_resource_dump_menu_segment_bits {
2569 	struct mlx5_ifc_resource_dump_segment_header_bits segment_header;
2570 
2571 	u8         reserved_at_20[0x10];
2572 	u8         num_of_records[0x10];
2573 
2574 	struct mlx5_ifc_resource_dump_menu_record_bits record[];
2575 };
2576 
2577 struct mlx5_ifc_resource_dump_resource_segment_bits {
2578 	struct mlx5_ifc_resource_dump_segment_header_bits segment_header;
2579 
2580 	u8         reserved_at_20[0x20];
2581 
2582 	u8         index1[0x20];
2583 
2584 	u8         index2[0x20];
2585 
2586 	u8         payload[][0x20];
2587 };
2588 
2589 struct mlx5_ifc_resource_dump_terminate_segment_bits {
2590 	struct mlx5_ifc_resource_dump_segment_header_bits segment_header;
2591 };
2592 
2593 struct mlx5_ifc_menu_resource_dump_response_bits {
2594 	struct mlx5_ifc_resource_dump_info_segment_bits info;
2595 	struct mlx5_ifc_resource_dump_command_segment_bits cmd;
2596 	struct mlx5_ifc_resource_dump_menu_segment_bits menu;
2597 	struct mlx5_ifc_resource_dump_terminate_segment_bits terminate;
2598 };
2599 
2600 enum {
2601 	MLX5_MODIFY_FIELD_SELECT_MODIFY_FIELD_SELECT_CQ_PERIOD     = 0x1,
2602 	MLX5_MODIFY_FIELD_SELECT_MODIFY_FIELD_SELECT_CQ_MAX_COUNT  = 0x2,
2603 	MLX5_MODIFY_FIELD_SELECT_MODIFY_FIELD_SELECT_OI            = 0x4,
2604 	MLX5_MODIFY_FIELD_SELECT_MODIFY_FIELD_SELECT_C_EQN         = 0x8,
2605 };
2606 
2607 struct mlx5_ifc_modify_field_select_bits {
2608 	u8         modify_field_select[0x20];
2609 };
2610 
2611 struct mlx5_ifc_field_select_r_roce_np_bits {
2612 	u8         field_select_r_roce_np[0x20];
2613 };
2614 
2615 struct mlx5_ifc_field_select_r_roce_rp_bits {
2616 	u8         field_select_r_roce_rp[0x20];
2617 };
2618 
2619 enum {
2620 	MLX5_FIELD_SELECT_802_1QAU_RP_FIELD_SELECT_8021QAURP_RPPP_MAX_RPS     = 0x4,
2621 	MLX5_FIELD_SELECT_802_1QAU_RP_FIELD_SELECT_8021QAURP_RPG_TIME_RESET   = 0x8,
2622 	MLX5_FIELD_SELECT_802_1QAU_RP_FIELD_SELECT_8021QAURP_RPG_BYTE_RESET   = 0x10,
2623 	MLX5_FIELD_SELECT_802_1QAU_RP_FIELD_SELECT_8021QAURP_RPG_THRESHOLD    = 0x20,
2624 	MLX5_FIELD_SELECT_802_1QAU_RP_FIELD_SELECT_8021QAURP_RPG_MAX_RATE     = 0x40,
2625 	MLX5_FIELD_SELECT_802_1QAU_RP_FIELD_SELECT_8021QAURP_RPG_AI_RATE      = 0x80,
2626 	MLX5_FIELD_SELECT_802_1QAU_RP_FIELD_SELECT_8021QAURP_RPG_HAI_RATE     = 0x100,
2627 	MLX5_FIELD_SELECT_802_1QAU_RP_FIELD_SELECT_8021QAURP_RPG_GD           = 0x200,
2628 	MLX5_FIELD_SELECT_802_1QAU_RP_FIELD_SELECT_8021QAURP_RPG_MIN_DEC_FAC  = 0x400,
2629 	MLX5_FIELD_SELECT_802_1QAU_RP_FIELD_SELECT_8021QAURP_RPG_MIN_RATE     = 0x800,
2630 };
2631 
2632 struct mlx5_ifc_field_select_802_1qau_rp_bits {
2633 	u8         field_select_8021qaurp[0x20];
2634 };
2635 
2636 struct mlx5_ifc_phys_layer_cntrs_bits {
2637 	u8         time_since_last_clear_high[0x20];
2638 
2639 	u8         time_since_last_clear_low[0x20];
2640 
2641 	u8         symbol_errors_high[0x20];
2642 
2643 	u8         symbol_errors_low[0x20];
2644 
2645 	u8         sync_headers_errors_high[0x20];
2646 
2647 	u8         sync_headers_errors_low[0x20];
2648 
2649 	u8         edpl_bip_errors_lane0_high[0x20];
2650 
2651 	u8         edpl_bip_errors_lane0_low[0x20];
2652 
2653 	u8         edpl_bip_errors_lane1_high[0x20];
2654 
2655 	u8         edpl_bip_errors_lane1_low[0x20];
2656 
2657 	u8         edpl_bip_errors_lane2_high[0x20];
2658 
2659 	u8         edpl_bip_errors_lane2_low[0x20];
2660 
2661 	u8         edpl_bip_errors_lane3_high[0x20];
2662 
2663 	u8         edpl_bip_errors_lane3_low[0x20];
2664 
2665 	u8         fc_fec_corrected_blocks_lane0_high[0x20];
2666 
2667 	u8         fc_fec_corrected_blocks_lane0_low[0x20];
2668 
2669 	u8         fc_fec_corrected_blocks_lane1_high[0x20];
2670 
2671 	u8         fc_fec_corrected_blocks_lane1_low[0x20];
2672 
2673 	u8         fc_fec_corrected_blocks_lane2_high[0x20];
2674 
2675 	u8         fc_fec_corrected_blocks_lane2_low[0x20];
2676 
2677 	u8         fc_fec_corrected_blocks_lane3_high[0x20];
2678 
2679 	u8         fc_fec_corrected_blocks_lane3_low[0x20];
2680 
2681 	u8         fc_fec_uncorrectable_blocks_lane0_high[0x20];
2682 
2683 	u8         fc_fec_uncorrectable_blocks_lane0_low[0x20];
2684 
2685 	u8         fc_fec_uncorrectable_blocks_lane1_high[0x20];
2686 
2687 	u8         fc_fec_uncorrectable_blocks_lane1_low[0x20];
2688 
2689 	u8         fc_fec_uncorrectable_blocks_lane2_high[0x20];
2690 
2691 	u8         fc_fec_uncorrectable_blocks_lane2_low[0x20];
2692 
2693 	u8         fc_fec_uncorrectable_blocks_lane3_high[0x20];
2694 
2695 	u8         fc_fec_uncorrectable_blocks_lane3_low[0x20];
2696 
2697 	u8         rs_fec_corrected_blocks_high[0x20];
2698 
2699 	u8         rs_fec_corrected_blocks_low[0x20];
2700 
2701 	u8         rs_fec_uncorrectable_blocks_high[0x20];
2702 
2703 	u8         rs_fec_uncorrectable_blocks_low[0x20];
2704 
2705 	u8         rs_fec_no_errors_blocks_high[0x20];
2706 
2707 	u8         rs_fec_no_errors_blocks_low[0x20];
2708 
2709 	u8         rs_fec_single_error_blocks_high[0x20];
2710 
2711 	u8         rs_fec_single_error_blocks_low[0x20];
2712 
2713 	u8         rs_fec_corrected_symbols_total_high[0x20];
2714 
2715 	u8         rs_fec_corrected_symbols_total_low[0x20];
2716 
2717 	u8         rs_fec_corrected_symbols_lane0_high[0x20];
2718 
2719 	u8         rs_fec_corrected_symbols_lane0_low[0x20];
2720 
2721 	u8         rs_fec_corrected_symbols_lane1_high[0x20];
2722 
2723 	u8         rs_fec_corrected_symbols_lane1_low[0x20];
2724 
2725 	u8         rs_fec_corrected_symbols_lane2_high[0x20];
2726 
2727 	u8         rs_fec_corrected_symbols_lane2_low[0x20];
2728 
2729 	u8         rs_fec_corrected_symbols_lane3_high[0x20];
2730 
2731 	u8         rs_fec_corrected_symbols_lane3_low[0x20];
2732 
2733 	u8         link_down_events[0x20];
2734 
2735 	u8         successful_recovery_events[0x20];
2736 
2737 	u8         reserved_at_640[0x180];
2738 };
2739 
2740 struct mlx5_ifc_phys_layer_statistical_cntrs_bits {
2741 	u8         time_since_last_clear_high[0x20];
2742 
2743 	u8         time_since_last_clear_low[0x20];
2744 
2745 	u8         phy_received_bits_high[0x20];
2746 
2747 	u8         phy_received_bits_low[0x20];
2748 
2749 	u8         phy_symbol_errors_high[0x20];
2750 
2751 	u8         phy_symbol_errors_low[0x20];
2752 
2753 	u8         phy_corrected_bits_high[0x20];
2754 
2755 	u8         phy_corrected_bits_low[0x20];
2756 
2757 	u8         phy_corrected_bits_lane0_high[0x20];
2758 
2759 	u8         phy_corrected_bits_lane0_low[0x20];
2760 
2761 	u8         phy_corrected_bits_lane1_high[0x20];
2762 
2763 	u8         phy_corrected_bits_lane1_low[0x20];
2764 
2765 	u8         phy_corrected_bits_lane2_high[0x20];
2766 
2767 	u8         phy_corrected_bits_lane2_low[0x20];
2768 
2769 	u8         phy_corrected_bits_lane3_high[0x20];
2770 
2771 	u8         phy_corrected_bits_lane3_low[0x20];
2772 
2773 	u8         reserved_at_200[0x5c0];
2774 };
2775 
2776 struct mlx5_ifc_ib_port_cntrs_grp_data_layout_bits {
2777 	u8	   symbol_error_counter[0x10];
2778 
2779 	u8         link_error_recovery_counter[0x8];
2780 
2781 	u8         link_downed_counter[0x8];
2782 
2783 	u8         port_rcv_errors[0x10];
2784 
2785 	u8         port_rcv_remote_physical_errors[0x10];
2786 
2787 	u8         port_rcv_switch_relay_errors[0x10];
2788 
2789 	u8         port_xmit_discards[0x10];
2790 
2791 	u8         port_xmit_constraint_errors[0x8];
2792 
2793 	u8         port_rcv_constraint_errors[0x8];
2794 
2795 	u8         reserved_at_70[0x8];
2796 
2797 	u8         link_overrun_errors[0x8];
2798 
2799 	u8	   reserved_at_80[0x10];
2800 
2801 	u8         vl_15_dropped[0x10];
2802 
2803 	u8	   reserved_at_a0[0x80];
2804 
2805 	u8         port_xmit_wait[0x20];
2806 };
2807 
2808 struct mlx5_ifc_ib_ext_port_cntrs_grp_data_layout_bits {
2809 	u8         reserved_at_0[0x300];
2810 
2811 	u8         port_xmit_data_high[0x20];
2812 
2813 	u8         port_xmit_data_low[0x20];
2814 
2815 	u8         port_rcv_data_high[0x20];
2816 
2817 	u8         port_rcv_data_low[0x20];
2818 
2819 	u8         port_xmit_pkts_high[0x20];
2820 
2821 	u8         port_xmit_pkts_low[0x20];
2822 
2823 	u8         port_rcv_pkts_high[0x20];
2824 
2825 	u8         port_rcv_pkts_low[0x20];
2826 
2827 	u8         reserved_at_400[0x80];
2828 
2829 	u8         port_unicast_xmit_pkts_high[0x20];
2830 
2831 	u8         port_unicast_xmit_pkts_low[0x20];
2832 
2833 	u8         port_multicast_xmit_pkts_high[0x20];
2834 
2835 	u8         port_multicast_xmit_pkts_low[0x20];
2836 
2837 	u8         port_unicast_rcv_pkts_high[0x20];
2838 
2839 	u8         port_unicast_rcv_pkts_low[0x20];
2840 
2841 	u8         port_multicast_rcv_pkts_high[0x20];
2842 
2843 	u8         port_multicast_rcv_pkts_low[0x20];
2844 
2845 	u8         reserved_at_580[0x240];
2846 };
2847 
2848 struct mlx5_ifc_eth_per_tc_prio_grp_data_layout_bits {
2849 	u8         transmit_queue_high[0x20];
2850 
2851 	u8         transmit_queue_low[0x20];
2852 
2853 	u8         no_buffer_discard_uc_high[0x20];
2854 
2855 	u8         no_buffer_discard_uc_low[0x20];
2856 
2857 	u8         reserved_at_80[0x740];
2858 };
2859 
2860 struct mlx5_ifc_eth_per_tc_congest_prio_grp_data_layout_bits {
2861 	u8         wred_discard_high[0x20];
2862 
2863 	u8         wred_discard_low[0x20];
2864 
2865 	u8         ecn_marked_tc_high[0x20];
2866 
2867 	u8         ecn_marked_tc_low[0x20];
2868 
2869 	u8         reserved_at_80[0x740];
2870 };
2871 
2872 struct mlx5_ifc_eth_per_prio_grp_data_layout_bits {
2873 	u8         rx_octets_high[0x20];
2874 
2875 	u8         rx_octets_low[0x20];
2876 
2877 	u8         reserved_at_40[0xc0];
2878 
2879 	u8         rx_frames_high[0x20];
2880 
2881 	u8         rx_frames_low[0x20];
2882 
2883 	u8         tx_octets_high[0x20];
2884 
2885 	u8         tx_octets_low[0x20];
2886 
2887 	u8         reserved_at_180[0xc0];
2888 
2889 	u8         tx_frames_high[0x20];
2890 
2891 	u8         tx_frames_low[0x20];
2892 
2893 	u8         rx_pause_high[0x20];
2894 
2895 	u8         rx_pause_low[0x20];
2896 
2897 	u8         rx_pause_duration_high[0x20];
2898 
2899 	u8         rx_pause_duration_low[0x20];
2900 
2901 	u8         tx_pause_high[0x20];
2902 
2903 	u8         tx_pause_low[0x20];
2904 
2905 	u8         tx_pause_duration_high[0x20];
2906 
2907 	u8         tx_pause_duration_low[0x20];
2908 
2909 	u8         rx_pause_transition_high[0x20];
2910 
2911 	u8         rx_pause_transition_low[0x20];
2912 
2913 	u8         rx_discards_high[0x20];
2914 
2915 	u8         rx_discards_low[0x20];
2916 
2917 	u8         device_stall_minor_watermark_cnt_high[0x20];
2918 
2919 	u8         device_stall_minor_watermark_cnt_low[0x20];
2920 
2921 	u8         device_stall_critical_watermark_cnt_high[0x20];
2922 
2923 	u8         device_stall_critical_watermark_cnt_low[0x20];
2924 
2925 	u8         reserved_at_480[0x340];
2926 };
2927 
2928 struct mlx5_ifc_eth_extended_cntrs_grp_data_layout_bits {
2929 	u8         port_transmit_wait_high[0x20];
2930 
2931 	u8         port_transmit_wait_low[0x20];
2932 
2933 	u8         reserved_at_40[0x100];
2934 
2935 	u8         rx_buffer_almost_full_high[0x20];
2936 
2937 	u8         rx_buffer_almost_full_low[0x20];
2938 
2939 	u8         rx_buffer_full_high[0x20];
2940 
2941 	u8         rx_buffer_full_low[0x20];
2942 
2943 	u8         rx_icrc_encapsulated_high[0x20];
2944 
2945 	u8         rx_icrc_encapsulated_low[0x20];
2946 
2947 	u8         reserved_at_200[0x5c0];
2948 };
2949 
2950 struct mlx5_ifc_eth_3635_cntrs_grp_data_layout_bits {
2951 	u8         dot3stats_alignment_errors_high[0x20];
2952 
2953 	u8         dot3stats_alignment_errors_low[0x20];
2954 
2955 	u8         dot3stats_fcs_errors_high[0x20];
2956 
2957 	u8         dot3stats_fcs_errors_low[0x20];
2958 
2959 	u8         dot3stats_single_collision_frames_high[0x20];
2960 
2961 	u8         dot3stats_single_collision_frames_low[0x20];
2962 
2963 	u8         dot3stats_multiple_collision_frames_high[0x20];
2964 
2965 	u8         dot3stats_multiple_collision_frames_low[0x20];
2966 
2967 	u8         dot3stats_sqe_test_errors_high[0x20];
2968 
2969 	u8         dot3stats_sqe_test_errors_low[0x20];
2970 
2971 	u8         dot3stats_deferred_transmissions_high[0x20];
2972 
2973 	u8         dot3stats_deferred_transmissions_low[0x20];
2974 
2975 	u8         dot3stats_late_collisions_high[0x20];
2976 
2977 	u8         dot3stats_late_collisions_low[0x20];
2978 
2979 	u8         dot3stats_excessive_collisions_high[0x20];
2980 
2981 	u8         dot3stats_excessive_collisions_low[0x20];
2982 
2983 	u8         dot3stats_internal_mac_transmit_errors_high[0x20];
2984 
2985 	u8         dot3stats_internal_mac_transmit_errors_low[0x20];
2986 
2987 	u8         dot3stats_carrier_sense_errors_high[0x20];
2988 
2989 	u8         dot3stats_carrier_sense_errors_low[0x20];
2990 
2991 	u8         dot3stats_frame_too_longs_high[0x20];
2992 
2993 	u8         dot3stats_frame_too_longs_low[0x20];
2994 
2995 	u8         dot3stats_internal_mac_receive_errors_high[0x20];
2996 
2997 	u8         dot3stats_internal_mac_receive_errors_low[0x20];
2998 
2999 	u8         dot3stats_symbol_errors_high[0x20];
3000 
3001 	u8         dot3stats_symbol_errors_low[0x20];
3002 
3003 	u8         dot3control_in_unknown_opcodes_high[0x20];
3004 
3005 	u8         dot3control_in_unknown_opcodes_low[0x20];
3006 
3007 	u8         dot3in_pause_frames_high[0x20];
3008 
3009 	u8         dot3in_pause_frames_low[0x20];
3010 
3011 	u8         dot3out_pause_frames_high[0x20];
3012 
3013 	u8         dot3out_pause_frames_low[0x20];
3014 
3015 	u8         reserved_at_400[0x3c0];
3016 };
3017 
3018 struct mlx5_ifc_eth_2819_cntrs_grp_data_layout_bits {
3019 	u8         ether_stats_drop_events_high[0x20];
3020 
3021 	u8         ether_stats_drop_events_low[0x20];
3022 
3023 	u8         ether_stats_octets_high[0x20];
3024 
3025 	u8         ether_stats_octets_low[0x20];
3026 
3027 	u8         ether_stats_pkts_high[0x20];
3028 
3029 	u8         ether_stats_pkts_low[0x20];
3030 
3031 	u8         ether_stats_broadcast_pkts_high[0x20];
3032 
3033 	u8         ether_stats_broadcast_pkts_low[0x20];
3034 
3035 	u8         ether_stats_multicast_pkts_high[0x20];
3036 
3037 	u8         ether_stats_multicast_pkts_low[0x20];
3038 
3039 	u8         ether_stats_crc_align_errors_high[0x20];
3040 
3041 	u8         ether_stats_crc_align_errors_low[0x20];
3042 
3043 	u8         ether_stats_undersize_pkts_high[0x20];
3044 
3045 	u8         ether_stats_undersize_pkts_low[0x20];
3046 
3047 	u8         ether_stats_oversize_pkts_high[0x20];
3048 
3049 	u8         ether_stats_oversize_pkts_low[0x20];
3050 
3051 	u8         ether_stats_fragments_high[0x20];
3052 
3053 	u8         ether_stats_fragments_low[0x20];
3054 
3055 	u8         ether_stats_jabbers_high[0x20];
3056 
3057 	u8         ether_stats_jabbers_low[0x20];
3058 
3059 	u8         ether_stats_collisions_high[0x20];
3060 
3061 	u8         ether_stats_collisions_low[0x20];
3062 
3063 	u8         ether_stats_pkts64octets_high[0x20];
3064 
3065 	u8         ether_stats_pkts64octets_low[0x20];
3066 
3067 	u8         ether_stats_pkts65to127octets_high[0x20];
3068 
3069 	u8         ether_stats_pkts65to127octets_low[0x20];
3070 
3071 	u8         ether_stats_pkts128to255octets_high[0x20];
3072 
3073 	u8         ether_stats_pkts128to255octets_low[0x20];
3074 
3075 	u8         ether_stats_pkts256to511octets_high[0x20];
3076 
3077 	u8         ether_stats_pkts256to511octets_low[0x20];
3078 
3079 	u8         ether_stats_pkts512to1023octets_high[0x20];
3080 
3081 	u8         ether_stats_pkts512to1023octets_low[0x20];
3082 
3083 	u8         ether_stats_pkts1024to1518octets_high[0x20];
3084 
3085 	u8         ether_stats_pkts1024to1518octets_low[0x20];
3086 
3087 	u8         ether_stats_pkts1519to2047octets_high[0x20];
3088 
3089 	u8         ether_stats_pkts1519to2047octets_low[0x20];
3090 
3091 	u8         ether_stats_pkts2048to4095octets_high[0x20];
3092 
3093 	u8         ether_stats_pkts2048to4095octets_low[0x20];
3094 
3095 	u8         ether_stats_pkts4096to8191octets_high[0x20];
3096 
3097 	u8         ether_stats_pkts4096to8191octets_low[0x20];
3098 
3099 	u8         ether_stats_pkts8192to10239octets_high[0x20];
3100 
3101 	u8         ether_stats_pkts8192to10239octets_low[0x20];
3102 
3103 	u8         reserved_at_540[0x280];
3104 };
3105 
3106 struct mlx5_ifc_eth_2863_cntrs_grp_data_layout_bits {
3107 	u8         if_in_octets_high[0x20];
3108 
3109 	u8         if_in_octets_low[0x20];
3110 
3111 	u8         if_in_ucast_pkts_high[0x20];
3112 
3113 	u8         if_in_ucast_pkts_low[0x20];
3114 
3115 	u8         if_in_discards_high[0x20];
3116 
3117 	u8         if_in_discards_low[0x20];
3118 
3119 	u8         if_in_errors_high[0x20];
3120 
3121 	u8         if_in_errors_low[0x20];
3122 
3123 	u8         if_in_unknown_protos_high[0x20];
3124 
3125 	u8         if_in_unknown_protos_low[0x20];
3126 
3127 	u8         if_out_octets_high[0x20];
3128 
3129 	u8         if_out_octets_low[0x20];
3130 
3131 	u8         if_out_ucast_pkts_high[0x20];
3132 
3133 	u8         if_out_ucast_pkts_low[0x20];
3134 
3135 	u8         if_out_discards_high[0x20];
3136 
3137 	u8         if_out_discards_low[0x20];
3138 
3139 	u8         if_out_errors_high[0x20];
3140 
3141 	u8         if_out_errors_low[0x20];
3142 
3143 	u8         if_in_multicast_pkts_high[0x20];
3144 
3145 	u8         if_in_multicast_pkts_low[0x20];
3146 
3147 	u8         if_in_broadcast_pkts_high[0x20];
3148 
3149 	u8         if_in_broadcast_pkts_low[0x20];
3150 
3151 	u8         if_out_multicast_pkts_high[0x20];
3152 
3153 	u8         if_out_multicast_pkts_low[0x20];
3154 
3155 	u8         if_out_broadcast_pkts_high[0x20];
3156 
3157 	u8         if_out_broadcast_pkts_low[0x20];
3158 
3159 	u8         reserved_at_340[0x480];
3160 };
3161 
3162 struct mlx5_ifc_eth_802_3_cntrs_grp_data_layout_bits {
3163 	u8         a_frames_transmitted_ok_high[0x20];
3164 
3165 	u8         a_frames_transmitted_ok_low[0x20];
3166 
3167 	u8         a_frames_received_ok_high[0x20];
3168 
3169 	u8         a_frames_received_ok_low[0x20];
3170 
3171 	u8         a_frame_check_sequence_errors_high[0x20];
3172 
3173 	u8         a_frame_check_sequence_errors_low[0x20];
3174 
3175 	u8         a_alignment_errors_high[0x20];
3176 
3177 	u8         a_alignment_errors_low[0x20];
3178 
3179 	u8         a_octets_transmitted_ok_high[0x20];
3180 
3181 	u8         a_octets_transmitted_ok_low[0x20];
3182 
3183 	u8         a_octets_received_ok_high[0x20];
3184 
3185 	u8         a_octets_received_ok_low[0x20];
3186 
3187 	u8         a_multicast_frames_xmitted_ok_high[0x20];
3188 
3189 	u8         a_multicast_frames_xmitted_ok_low[0x20];
3190 
3191 	u8         a_broadcast_frames_xmitted_ok_high[0x20];
3192 
3193 	u8         a_broadcast_frames_xmitted_ok_low[0x20];
3194 
3195 	u8         a_multicast_frames_received_ok_high[0x20];
3196 
3197 	u8         a_multicast_frames_received_ok_low[0x20];
3198 
3199 	u8         a_broadcast_frames_received_ok_high[0x20];
3200 
3201 	u8         a_broadcast_frames_received_ok_low[0x20];
3202 
3203 	u8         a_in_range_length_errors_high[0x20];
3204 
3205 	u8         a_in_range_length_errors_low[0x20];
3206 
3207 	u8         a_out_of_range_length_field_high[0x20];
3208 
3209 	u8         a_out_of_range_length_field_low[0x20];
3210 
3211 	u8         a_frame_too_long_errors_high[0x20];
3212 
3213 	u8         a_frame_too_long_errors_low[0x20];
3214 
3215 	u8         a_symbol_error_during_carrier_high[0x20];
3216 
3217 	u8         a_symbol_error_during_carrier_low[0x20];
3218 
3219 	u8         a_mac_control_frames_transmitted_high[0x20];
3220 
3221 	u8         a_mac_control_frames_transmitted_low[0x20];
3222 
3223 	u8         a_mac_control_frames_received_high[0x20];
3224 
3225 	u8         a_mac_control_frames_received_low[0x20];
3226 
3227 	u8         a_unsupported_opcodes_received_high[0x20];
3228 
3229 	u8         a_unsupported_opcodes_received_low[0x20];
3230 
3231 	u8         a_pause_mac_ctrl_frames_received_high[0x20];
3232 
3233 	u8         a_pause_mac_ctrl_frames_received_low[0x20];
3234 
3235 	u8         a_pause_mac_ctrl_frames_transmitted_high[0x20];
3236 
3237 	u8         a_pause_mac_ctrl_frames_transmitted_low[0x20];
3238 
3239 	u8         reserved_at_4c0[0x300];
3240 };
3241 
3242 struct mlx5_ifc_pcie_perf_cntrs_grp_data_layout_bits {
3243 	u8         life_time_counter_high[0x20];
3244 
3245 	u8         life_time_counter_low[0x20];
3246 
3247 	u8         rx_errors[0x20];
3248 
3249 	u8         tx_errors[0x20];
3250 
3251 	u8         l0_to_recovery_eieos[0x20];
3252 
3253 	u8         l0_to_recovery_ts[0x20];
3254 
3255 	u8         l0_to_recovery_framing[0x20];
3256 
3257 	u8         l0_to_recovery_retrain[0x20];
3258 
3259 	u8         crc_error_dllp[0x20];
3260 
3261 	u8         crc_error_tlp[0x20];
3262 
3263 	u8         tx_overflow_buffer_pkt_high[0x20];
3264 
3265 	u8         tx_overflow_buffer_pkt_low[0x20];
3266 
3267 	u8         outbound_stalled_reads[0x20];
3268 
3269 	u8         outbound_stalled_writes[0x20];
3270 
3271 	u8         outbound_stalled_reads_events[0x20];
3272 
3273 	u8         outbound_stalled_writes_events[0x20];
3274 
3275 	u8         reserved_at_200[0x5c0];
3276 };
3277 
3278 struct mlx5_ifc_cmd_inter_comp_event_bits {
3279 	u8         command_completion_vector[0x20];
3280 
3281 	u8         reserved_at_20[0xc0];
3282 };
3283 
3284 struct mlx5_ifc_stall_vl_event_bits {
3285 	u8         reserved_at_0[0x18];
3286 	u8         port_num[0x1];
3287 	u8         reserved_at_19[0x3];
3288 	u8         vl[0x4];
3289 
3290 	u8         reserved_at_20[0xa0];
3291 };
3292 
3293 struct mlx5_ifc_db_bf_congestion_event_bits {
3294 	u8         event_subtype[0x8];
3295 	u8         reserved_at_8[0x8];
3296 	u8         congestion_level[0x8];
3297 	u8         reserved_at_18[0x8];
3298 
3299 	u8         reserved_at_20[0xa0];
3300 };
3301 
3302 struct mlx5_ifc_gpio_event_bits {
3303 	u8         reserved_at_0[0x60];
3304 
3305 	u8         gpio_event_hi[0x20];
3306 
3307 	u8         gpio_event_lo[0x20];
3308 
3309 	u8         reserved_at_a0[0x40];
3310 };
3311 
3312 struct mlx5_ifc_port_state_change_event_bits {
3313 	u8         reserved_at_0[0x40];
3314 
3315 	u8         port_num[0x4];
3316 	u8         reserved_at_44[0x1c];
3317 
3318 	u8         reserved_at_60[0x80];
3319 };
3320 
3321 struct mlx5_ifc_dropped_packet_logged_bits {
3322 	u8         reserved_at_0[0xe0];
3323 };
3324 
3325 struct mlx5_ifc_default_timeout_bits {
3326 	u8         to_multiplier[0x3];
3327 	u8         reserved_at_3[0x9];
3328 	u8         to_value[0x14];
3329 };
3330 
3331 struct mlx5_ifc_dtor_reg_bits {
3332 	u8         reserved_at_0[0x20];
3333 
3334 	struct mlx5_ifc_default_timeout_bits pcie_toggle_to;
3335 
3336 	u8         reserved_at_40[0x60];
3337 
3338 	struct mlx5_ifc_default_timeout_bits health_poll_to;
3339 
3340 	struct mlx5_ifc_default_timeout_bits full_crdump_to;
3341 
3342 	struct mlx5_ifc_default_timeout_bits fw_reset_to;
3343 
3344 	struct mlx5_ifc_default_timeout_bits flush_on_err_to;
3345 
3346 	struct mlx5_ifc_default_timeout_bits pci_sync_update_to;
3347 
3348 	struct mlx5_ifc_default_timeout_bits tear_down_to;
3349 
3350 	struct mlx5_ifc_default_timeout_bits fsm_reactivate_to;
3351 
3352 	struct mlx5_ifc_default_timeout_bits reclaim_pages_to;
3353 
3354 	struct mlx5_ifc_default_timeout_bits reclaim_vfs_pages_to;
3355 
3356 	struct mlx5_ifc_default_timeout_bits reset_unload_to;
3357 
3358 	u8         reserved_at_1c0[0x20];
3359 };
3360 
3361 enum {
3362 	MLX5_CQ_ERROR_SYNDROME_CQ_OVERRUN                 = 0x1,
3363 	MLX5_CQ_ERROR_SYNDROME_CQ_ACCESS_VIOLATION_ERROR  = 0x2,
3364 };
3365 
3366 struct mlx5_ifc_cq_error_bits {
3367 	u8         reserved_at_0[0x8];
3368 	u8         cqn[0x18];
3369 
3370 	u8         reserved_at_20[0x20];
3371 
3372 	u8         reserved_at_40[0x18];
3373 	u8         syndrome[0x8];
3374 
3375 	u8         reserved_at_60[0x80];
3376 };
3377 
3378 struct mlx5_ifc_rdma_page_fault_event_bits {
3379 	u8         bytes_committed[0x20];
3380 
3381 	u8         r_key[0x20];
3382 
3383 	u8         reserved_at_40[0x10];
3384 	u8         packet_len[0x10];
3385 
3386 	u8         rdma_op_len[0x20];
3387 
3388 	u8         rdma_va[0x40];
3389 
3390 	u8         reserved_at_c0[0x5];
3391 	u8         rdma[0x1];
3392 	u8         write[0x1];
3393 	u8         requestor[0x1];
3394 	u8         qp_number[0x18];
3395 };
3396 
3397 struct mlx5_ifc_wqe_associated_page_fault_event_bits {
3398 	u8         bytes_committed[0x20];
3399 
3400 	u8         reserved_at_20[0x10];
3401 	u8         wqe_index[0x10];
3402 
3403 	u8         reserved_at_40[0x10];
3404 	u8         len[0x10];
3405 
3406 	u8         reserved_at_60[0x60];
3407 
3408 	u8         reserved_at_c0[0x5];
3409 	u8         rdma[0x1];
3410 	u8         write_read[0x1];
3411 	u8         requestor[0x1];
3412 	u8         qpn[0x18];
3413 };
3414 
3415 struct mlx5_ifc_qp_events_bits {
3416 	u8         reserved_at_0[0xa0];
3417 
3418 	u8         type[0x8];
3419 	u8         reserved_at_a8[0x18];
3420 
3421 	u8         reserved_at_c0[0x8];
3422 	u8         qpn_rqn_sqn[0x18];
3423 };
3424 
3425 struct mlx5_ifc_dct_events_bits {
3426 	u8         reserved_at_0[0xc0];
3427 
3428 	u8         reserved_at_c0[0x8];
3429 	u8         dct_number[0x18];
3430 };
3431 
3432 struct mlx5_ifc_comp_event_bits {
3433 	u8         reserved_at_0[0xc0];
3434 
3435 	u8         reserved_at_c0[0x8];
3436 	u8         cq_number[0x18];
3437 };
3438 
3439 enum {
3440 	MLX5_QPC_STATE_RST        = 0x0,
3441 	MLX5_QPC_STATE_INIT       = 0x1,
3442 	MLX5_QPC_STATE_RTR        = 0x2,
3443 	MLX5_QPC_STATE_RTS        = 0x3,
3444 	MLX5_QPC_STATE_SQER       = 0x4,
3445 	MLX5_QPC_STATE_ERR        = 0x6,
3446 	MLX5_QPC_STATE_SQD        = 0x7,
3447 	MLX5_QPC_STATE_SUSPENDED  = 0x9,
3448 };
3449 
3450 enum {
3451 	MLX5_QPC_ST_RC            = 0x0,
3452 	MLX5_QPC_ST_UC            = 0x1,
3453 	MLX5_QPC_ST_UD            = 0x2,
3454 	MLX5_QPC_ST_XRC           = 0x3,
3455 	MLX5_QPC_ST_DCI           = 0x5,
3456 	MLX5_QPC_ST_QP0           = 0x7,
3457 	MLX5_QPC_ST_QP1           = 0x8,
3458 	MLX5_QPC_ST_RAW_DATAGRAM  = 0x9,
3459 	MLX5_QPC_ST_REG_UMR       = 0xc,
3460 };
3461 
3462 enum {
3463 	MLX5_QPC_PM_STATE_ARMED     = 0x0,
3464 	MLX5_QPC_PM_STATE_REARM     = 0x1,
3465 	MLX5_QPC_PM_STATE_RESERVED  = 0x2,
3466 	MLX5_QPC_PM_STATE_MIGRATED  = 0x3,
3467 };
3468 
3469 enum {
3470 	MLX5_QPC_OFFLOAD_TYPE_RNDV  = 0x1,
3471 };
3472 
3473 enum {
3474 	MLX5_QPC_END_PADDING_MODE_SCATTER_AS_IS                = 0x0,
3475 	MLX5_QPC_END_PADDING_MODE_PAD_TO_CACHE_LINE_ALIGNMENT  = 0x1,
3476 };
3477 
3478 enum {
3479 	MLX5_QPC_MTU_256_BYTES        = 0x1,
3480 	MLX5_QPC_MTU_512_BYTES        = 0x2,
3481 	MLX5_QPC_MTU_1K_BYTES         = 0x3,
3482 	MLX5_QPC_MTU_2K_BYTES         = 0x4,
3483 	MLX5_QPC_MTU_4K_BYTES         = 0x5,
3484 	MLX5_QPC_MTU_RAW_ETHERNET_QP  = 0x7,
3485 };
3486 
3487 enum {
3488 	MLX5_QPC_ATOMIC_MODE_IB_SPEC     = 0x1,
3489 	MLX5_QPC_ATOMIC_MODE_ONLY_8B     = 0x2,
3490 	MLX5_QPC_ATOMIC_MODE_UP_TO_8B    = 0x3,
3491 	MLX5_QPC_ATOMIC_MODE_UP_TO_16B   = 0x4,
3492 	MLX5_QPC_ATOMIC_MODE_UP_TO_32B   = 0x5,
3493 	MLX5_QPC_ATOMIC_MODE_UP_TO_64B   = 0x6,
3494 	MLX5_QPC_ATOMIC_MODE_UP_TO_128B  = 0x7,
3495 	MLX5_QPC_ATOMIC_MODE_UP_TO_256B  = 0x8,
3496 };
3497 
3498 enum {
3499 	MLX5_QPC_CS_REQ_DISABLE    = 0x0,
3500 	MLX5_QPC_CS_REQ_UP_TO_32B  = 0x11,
3501 	MLX5_QPC_CS_REQ_UP_TO_64B  = 0x22,
3502 };
3503 
3504 enum {
3505 	MLX5_QPC_CS_RES_DISABLE    = 0x0,
3506 	MLX5_QPC_CS_RES_UP_TO_32B  = 0x1,
3507 	MLX5_QPC_CS_RES_UP_TO_64B  = 0x2,
3508 };
3509 
3510 enum {
3511 	MLX5_TIMESTAMP_FORMAT_FREE_RUNNING = 0x0,
3512 	MLX5_TIMESTAMP_FORMAT_DEFAULT      = 0x1,
3513 	MLX5_TIMESTAMP_FORMAT_REAL_TIME    = 0x2,
3514 };
3515 
3516 struct mlx5_ifc_qpc_bits {
3517 	u8         state[0x4];
3518 	u8         lag_tx_port_affinity[0x4];
3519 	u8         st[0x8];
3520 	u8         reserved_at_10[0x2];
3521 	u8	   isolate_vl_tc[0x1];
3522 	u8         pm_state[0x2];
3523 	u8         reserved_at_15[0x1];
3524 	u8         req_e2e_credit_mode[0x2];
3525 	u8         offload_type[0x4];
3526 	u8         end_padding_mode[0x2];
3527 	u8         reserved_at_1e[0x2];
3528 
3529 	u8         wq_signature[0x1];
3530 	u8         block_lb_mc[0x1];
3531 	u8         atomic_like_write_en[0x1];
3532 	u8         latency_sensitive[0x1];
3533 	u8         reserved_at_24[0x1];
3534 	u8         drain_sigerr[0x1];
3535 	u8         reserved_at_26[0x1];
3536 	u8         dp_ordering_force[0x1];
3537 	u8         pd[0x18];
3538 
3539 	u8         mtu[0x3];
3540 	u8         log_msg_max[0x5];
3541 	u8         reserved_at_48[0x1];
3542 	u8         log_rq_size[0x4];
3543 	u8         log_rq_stride[0x3];
3544 	u8         no_sq[0x1];
3545 	u8         log_sq_size[0x4];
3546 	u8         reserved_at_55[0x1];
3547 	u8	   retry_mode[0x2];
3548 	u8	   ts_format[0x2];
3549 	u8         reserved_at_5a[0x1];
3550 	u8         rlky[0x1];
3551 	u8         ulp_stateless_offload_mode[0x4];
3552 
3553 	u8         counter_set_id[0x8];
3554 	u8         uar_page[0x18];
3555 
3556 	u8         reserved_at_80[0x8];
3557 	u8         user_index[0x18];
3558 
3559 	u8         reserved_at_a0[0x3];
3560 	u8         log_page_size[0x5];
3561 	u8         remote_qpn[0x18];
3562 
3563 	struct mlx5_ifc_ads_bits primary_address_path;
3564 
3565 	struct mlx5_ifc_ads_bits secondary_address_path;
3566 
3567 	u8         log_ack_req_freq[0x4];
3568 	u8         reserved_at_384[0x4];
3569 	u8         log_sra_max[0x3];
3570 	u8         reserved_at_38b[0x2];
3571 	u8         retry_count[0x3];
3572 	u8         rnr_retry[0x3];
3573 	u8         reserved_at_393[0x1];
3574 	u8         fre[0x1];
3575 	u8         cur_rnr_retry[0x3];
3576 	u8         cur_retry_count[0x3];
3577 	u8         reserved_at_39b[0x5];
3578 
3579 	u8         reserved_at_3a0[0x20];
3580 
3581 	u8         reserved_at_3c0[0x8];
3582 	u8         next_send_psn[0x18];
3583 
3584 	u8         reserved_at_3e0[0x3];
3585 	u8	   log_num_dci_stream_channels[0x5];
3586 	u8         cqn_snd[0x18];
3587 
3588 	u8         reserved_at_400[0x3];
3589 	u8	   log_num_dci_errored_streams[0x5];
3590 	u8         deth_sqpn[0x18];
3591 
3592 	u8         reserved_at_420[0x20];
3593 
3594 	u8         reserved_at_440[0x8];
3595 	u8         last_acked_psn[0x18];
3596 
3597 	u8         reserved_at_460[0x8];
3598 	u8         ssn[0x18];
3599 
3600 	u8         reserved_at_480[0x8];
3601 	u8         log_rra_max[0x3];
3602 	u8         reserved_at_48b[0x1];
3603 	u8         atomic_mode[0x4];
3604 	u8         rre[0x1];
3605 	u8         rwe[0x1];
3606 	u8         rae[0x1];
3607 	u8         reserved_at_493[0x1];
3608 	u8         page_offset[0x6];
3609 	u8         reserved_at_49a[0x2];
3610 	u8         dp_ordering_1[0x1];
3611 	u8         cd_slave_receive[0x1];
3612 	u8         cd_slave_send[0x1];
3613 	u8         cd_master[0x1];
3614 
3615 	u8         reserved_at_4a0[0x3];
3616 	u8         min_rnr_nak[0x5];
3617 	u8         next_rcv_psn[0x18];
3618 
3619 	u8         reserved_at_4c0[0x8];
3620 	u8         xrcd[0x18];
3621 
3622 	u8         reserved_at_4e0[0x8];
3623 	u8         cqn_rcv[0x18];
3624 
3625 	u8         dbr_addr[0x40];
3626 
3627 	u8         q_key[0x20];
3628 
3629 	u8         reserved_at_560[0x5];
3630 	u8         rq_type[0x3];
3631 	u8         srqn_rmpn_xrqn[0x18];
3632 
3633 	u8         reserved_at_580[0x8];
3634 	u8         rmsn[0x18];
3635 
3636 	u8         hw_sq_wqebb_counter[0x10];
3637 	u8         sw_sq_wqebb_counter[0x10];
3638 
3639 	u8         hw_rq_counter[0x20];
3640 
3641 	u8         sw_rq_counter[0x20];
3642 
3643 	u8         reserved_at_600[0x20];
3644 
3645 	u8         reserved_at_620[0xf];
3646 	u8         cgs[0x1];
3647 	u8         cs_req[0x8];
3648 	u8         cs_res[0x8];
3649 
3650 	u8         dc_access_key[0x40];
3651 
3652 	u8         reserved_at_680[0x3];
3653 	u8         dbr_umem_valid[0x1];
3654 
3655 	u8         reserved_at_684[0xbc];
3656 };
3657 
3658 struct mlx5_ifc_roce_addr_layout_bits {
3659 	u8         source_l3_address[16][0x8];
3660 
3661 	u8         reserved_at_80[0x3];
3662 	u8         vlan_valid[0x1];
3663 	u8         vlan_id[0xc];
3664 	u8         source_mac_47_32[0x10];
3665 
3666 	u8         source_mac_31_0[0x20];
3667 
3668 	u8         reserved_at_c0[0x14];
3669 	u8         roce_l3_type[0x4];
3670 	u8         roce_version[0x8];
3671 
3672 	u8         reserved_at_e0[0x20];
3673 };
3674 
3675 struct mlx5_ifc_crypto_cap_bits {
3676 	u8    reserved_at_0[0x3];
3677 	u8    synchronize_dek[0x1];
3678 	u8    int_kek_manual[0x1];
3679 	u8    int_kek_auto[0x1];
3680 	u8    reserved_at_6[0x1a];
3681 
3682 	u8    reserved_at_20[0x3];
3683 	u8    log_dek_max_alloc[0x5];
3684 	u8    reserved_at_28[0x3];
3685 	u8    log_max_num_deks[0x5];
3686 	u8    reserved_at_30[0x10];
3687 
3688 	u8    reserved_at_40[0x20];
3689 
3690 	u8    reserved_at_60[0x3];
3691 	u8    log_dek_granularity[0x5];
3692 	u8    reserved_at_68[0x3];
3693 	u8    log_max_num_int_kek[0x5];
3694 	u8    sw_wrapped_dek[0x10];
3695 
3696 	u8    reserved_at_80[0x780];
3697 };
3698 
3699 union mlx5_ifc_hca_cap_union_bits {
3700 	struct mlx5_ifc_cmd_hca_cap_bits cmd_hca_cap;
3701 	struct mlx5_ifc_cmd_hca_cap_2_bits cmd_hca_cap_2;
3702 	struct mlx5_ifc_odp_cap_bits odp_cap;
3703 	struct mlx5_ifc_atomic_caps_bits atomic_caps;
3704 	struct mlx5_ifc_roce_cap_bits roce_cap;
3705 	struct mlx5_ifc_per_protocol_networking_offload_caps_bits per_protocol_networking_offload_caps;
3706 	struct mlx5_ifc_flow_table_nic_cap_bits flow_table_nic_cap;
3707 	struct mlx5_ifc_flow_table_eswitch_cap_bits flow_table_eswitch_cap;
3708 	struct mlx5_ifc_wqe_based_flow_table_cap_bits wqe_based_flow_table_cap;
3709 	struct mlx5_ifc_esw_cap_bits esw_cap;
3710 	struct mlx5_ifc_e_switch_cap_bits e_switch_cap;
3711 	struct mlx5_ifc_port_selection_cap_bits port_selection_cap;
3712 	struct mlx5_ifc_qos_cap_bits qos_cap;
3713 	struct mlx5_ifc_debug_cap_bits debug_cap;
3714 	struct mlx5_ifc_fpga_cap_bits fpga_cap;
3715 	struct mlx5_ifc_tls_cap_bits tls_cap;
3716 	struct mlx5_ifc_device_mem_cap_bits device_mem_cap;
3717 	struct mlx5_ifc_virtio_emulation_cap_bits virtio_emulation_cap;
3718 	struct mlx5_ifc_macsec_cap_bits macsec_cap;
3719 	struct mlx5_ifc_crypto_cap_bits crypto_cap;
3720 	struct mlx5_ifc_ipsec_cap_bits ipsec_cap;
3721 	u8         reserved_at_0[0x8000];
3722 };
3723 
3724 enum {
3725 	MLX5_FLOW_CONTEXT_ACTION_ALLOW     = 0x1,
3726 	MLX5_FLOW_CONTEXT_ACTION_DROP      = 0x2,
3727 	MLX5_FLOW_CONTEXT_ACTION_FWD_DEST  = 0x4,
3728 	MLX5_FLOW_CONTEXT_ACTION_COUNT     = 0x8,
3729 	MLX5_FLOW_CONTEXT_ACTION_PACKET_REFORMAT = 0x10,
3730 	MLX5_FLOW_CONTEXT_ACTION_DECAP     = 0x20,
3731 	MLX5_FLOW_CONTEXT_ACTION_MOD_HDR   = 0x40,
3732 	MLX5_FLOW_CONTEXT_ACTION_VLAN_POP  = 0x80,
3733 	MLX5_FLOW_CONTEXT_ACTION_VLAN_PUSH = 0x100,
3734 	MLX5_FLOW_CONTEXT_ACTION_VLAN_POP_2  = 0x400,
3735 	MLX5_FLOW_CONTEXT_ACTION_VLAN_PUSH_2 = 0x800,
3736 	MLX5_FLOW_CONTEXT_ACTION_CRYPTO_DECRYPT = 0x1000,
3737 	MLX5_FLOW_CONTEXT_ACTION_CRYPTO_ENCRYPT = 0x2000,
3738 	MLX5_FLOW_CONTEXT_ACTION_EXECUTE_ASO = 0x4000,
3739 };
3740 
3741 enum {
3742 	MLX5_FLOW_CONTEXT_FLOW_SOURCE_ANY_VPORT         = 0x0,
3743 	MLX5_FLOW_CONTEXT_FLOW_SOURCE_UPLINK            = 0x1,
3744 	MLX5_FLOW_CONTEXT_FLOW_SOURCE_LOCAL_VPORT       = 0x2,
3745 };
3746 
3747 enum {
3748 	MLX5_FLOW_CONTEXT_ENCRYPT_DECRYPT_TYPE_IPSEC   = 0x0,
3749 	MLX5_FLOW_CONTEXT_ENCRYPT_DECRYPT_TYPE_MACSEC  = 0x1,
3750 };
3751 
3752 struct mlx5_ifc_vlan_bits {
3753 	u8         ethtype[0x10];
3754 	u8         prio[0x3];
3755 	u8         cfi[0x1];
3756 	u8         vid[0xc];
3757 };
3758 
3759 enum {
3760 	MLX5_FLOW_METER_COLOR_RED	= 0x0,
3761 	MLX5_FLOW_METER_COLOR_YELLOW	= 0x1,
3762 	MLX5_FLOW_METER_COLOR_GREEN	= 0x2,
3763 	MLX5_FLOW_METER_COLOR_UNDEFINED	= 0x3,
3764 };
3765 
3766 enum {
3767 	MLX5_EXE_ASO_FLOW_METER		= 0x2,
3768 };
3769 
3770 struct mlx5_ifc_exe_aso_ctrl_flow_meter_bits {
3771 	u8        return_reg_id[0x4];
3772 	u8        aso_type[0x4];
3773 	u8        reserved_at_8[0x14];
3774 	u8        action[0x1];
3775 	u8        init_color[0x2];
3776 	u8        meter_id[0x1];
3777 };
3778 
3779 union mlx5_ifc_exe_aso_ctrl {
3780 	struct mlx5_ifc_exe_aso_ctrl_flow_meter_bits exe_aso_ctrl_flow_meter;
3781 };
3782 
3783 struct mlx5_ifc_execute_aso_bits {
3784 	u8        valid[0x1];
3785 	u8        reserved_at_1[0x7];
3786 	u8        aso_object_id[0x18];
3787 
3788 	union mlx5_ifc_exe_aso_ctrl exe_aso_ctrl;
3789 };
3790 
3791 struct mlx5_ifc_flow_context_bits {
3792 	struct mlx5_ifc_vlan_bits push_vlan;
3793 
3794 	u8         group_id[0x20];
3795 
3796 	u8         reserved_at_40[0x8];
3797 	u8         flow_tag[0x18];
3798 
3799 	u8         reserved_at_60[0x10];
3800 	u8         action[0x10];
3801 
3802 	u8         extended_destination[0x1];
3803 	u8         uplink_hairpin_en[0x1];
3804 	u8         flow_source[0x2];
3805 	u8         encrypt_decrypt_type[0x4];
3806 	u8         destination_list_size[0x18];
3807 
3808 	u8         reserved_at_a0[0x8];
3809 	u8         flow_counter_list_size[0x18];
3810 
3811 	u8         packet_reformat_id[0x20];
3812 
3813 	u8         modify_header_id[0x20];
3814 
3815 	struct mlx5_ifc_vlan_bits push_vlan_2;
3816 
3817 	u8         encrypt_decrypt_obj_id[0x20];
3818 	u8         reserved_at_140[0xc0];
3819 
3820 	struct mlx5_ifc_fte_match_param_bits match_value;
3821 
3822 	struct mlx5_ifc_execute_aso_bits execute_aso[4];
3823 
3824 	u8         reserved_at_1300[0x500];
3825 
3826 	union mlx5_ifc_dest_format_flow_counter_list_auto_bits destination[];
3827 };
3828 
3829 enum {
3830 	MLX5_XRC_SRQC_STATE_GOOD   = 0x0,
3831 	MLX5_XRC_SRQC_STATE_ERROR  = 0x1,
3832 };
3833 
3834 struct mlx5_ifc_xrc_srqc_bits {
3835 	u8         state[0x4];
3836 	u8         log_xrc_srq_size[0x4];
3837 	u8         reserved_at_8[0x18];
3838 
3839 	u8         wq_signature[0x1];
3840 	u8         cont_srq[0x1];
3841 	u8         reserved_at_22[0x1];
3842 	u8         rlky[0x1];
3843 	u8         basic_cyclic_rcv_wqe[0x1];
3844 	u8         log_rq_stride[0x3];
3845 	u8         xrcd[0x18];
3846 
3847 	u8         page_offset[0x6];
3848 	u8         reserved_at_46[0x1];
3849 	u8         dbr_umem_valid[0x1];
3850 	u8         cqn[0x18];
3851 
3852 	u8         reserved_at_60[0x20];
3853 
3854 	u8         user_index_equal_xrc_srqn[0x1];
3855 	u8         reserved_at_81[0x1];
3856 	u8         log_page_size[0x6];
3857 	u8         user_index[0x18];
3858 
3859 	u8         reserved_at_a0[0x20];
3860 
3861 	u8         reserved_at_c0[0x8];
3862 	u8         pd[0x18];
3863 
3864 	u8         lwm[0x10];
3865 	u8         wqe_cnt[0x10];
3866 
3867 	u8         reserved_at_100[0x40];
3868 
3869 	u8         db_record_addr_h[0x20];
3870 
3871 	u8         db_record_addr_l[0x1e];
3872 	u8         reserved_at_17e[0x2];
3873 
3874 	u8         reserved_at_180[0x80];
3875 };
3876 
3877 struct mlx5_ifc_vnic_diagnostic_statistics_bits {
3878 	u8         counter_error_queues[0x20];
3879 
3880 	u8         total_error_queues[0x20];
3881 
3882 	u8         send_queue_priority_update_flow[0x20];
3883 
3884 	u8         reserved_at_60[0x20];
3885 
3886 	u8         nic_receive_steering_discard[0x40];
3887 
3888 	u8         receive_discard_vport_down[0x40];
3889 
3890 	u8         transmit_discard_vport_down[0x40];
3891 
3892 	u8         async_eq_overrun[0x20];
3893 
3894 	u8         comp_eq_overrun[0x20];
3895 
3896 	u8         reserved_at_180[0x20];
3897 
3898 	u8         invalid_command[0x20];
3899 
3900 	u8         quota_exceeded_command[0x20];
3901 
3902 	u8         internal_rq_out_of_buffer[0x20];
3903 
3904 	u8         cq_overrun[0x20];
3905 
3906 	u8         eth_wqe_too_small[0x20];
3907 
3908 	u8         reserved_at_220[0xc0];
3909 
3910 	u8         generated_pkt_steering_fail[0x40];
3911 
3912 	u8         handled_pkt_steering_fail[0x40];
3913 
3914 	u8         reserved_at_360[0xc80];
3915 };
3916 
3917 struct mlx5_ifc_traffic_counter_bits {
3918 	u8         packets[0x40];
3919 
3920 	u8         octets[0x40];
3921 };
3922 
3923 struct mlx5_ifc_tisc_bits {
3924 	u8         strict_lag_tx_port_affinity[0x1];
3925 	u8         tls_en[0x1];
3926 	u8         reserved_at_2[0x2];
3927 	u8         lag_tx_port_affinity[0x04];
3928 
3929 	u8         reserved_at_8[0x4];
3930 	u8         prio[0x4];
3931 	u8         reserved_at_10[0x10];
3932 
3933 	u8         reserved_at_20[0x100];
3934 
3935 	u8         reserved_at_120[0x8];
3936 	u8         transport_domain[0x18];
3937 
3938 	u8         reserved_at_140[0x8];
3939 	u8         underlay_qpn[0x18];
3940 
3941 	u8         reserved_at_160[0x8];
3942 	u8         pd[0x18];
3943 
3944 	u8         reserved_at_180[0x380];
3945 };
3946 
3947 enum {
3948 	MLX5_TIRC_DISP_TYPE_DIRECT    = 0x0,
3949 	MLX5_TIRC_DISP_TYPE_INDIRECT  = 0x1,
3950 };
3951 
3952 enum {
3953 	MLX5_TIRC_PACKET_MERGE_MASK_IPV4_LRO  = BIT(0),
3954 	MLX5_TIRC_PACKET_MERGE_MASK_IPV6_LRO  = BIT(1),
3955 };
3956 
3957 enum {
3958 	MLX5_RX_HASH_FN_NONE           = 0x0,
3959 	MLX5_RX_HASH_FN_INVERTED_XOR8  = 0x1,
3960 	MLX5_RX_HASH_FN_TOEPLITZ       = 0x2,
3961 };
3962 
3963 enum {
3964 	MLX5_TIRC_SELF_LB_BLOCK_BLOCK_UNICAST    = 0x1,
3965 	MLX5_TIRC_SELF_LB_BLOCK_BLOCK_MULTICAST  = 0x2,
3966 };
3967 
3968 struct mlx5_ifc_tirc_bits {
3969 	u8         reserved_at_0[0x20];
3970 
3971 	u8         disp_type[0x4];
3972 	u8         tls_en[0x1];
3973 	u8         reserved_at_25[0x1b];
3974 
3975 	u8         reserved_at_40[0x40];
3976 
3977 	u8         reserved_at_80[0x4];
3978 	u8         lro_timeout_period_usecs[0x10];
3979 	u8         packet_merge_mask[0x4];
3980 	u8         lro_max_ip_payload_size[0x8];
3981 
3982 	u8         reserved_at_a0[0x40];
3983 
3984 	u8         reserved_at_e0[0x8];
3985 	u8         inline_rqn[0x18];
3986 
3987 	u8         rx_hash_symmetric[0x1];
3988 	u8         reserved_at_101[0x1];
3989 	u8         tunneled_offload_en[0x1];
3990 	u8         reserved_at_103[0x5];
3991 	u8         indirect_table[0x18];
3992 
3993 	u8         rx_hash_fn[0x4];
3994 	u8         reserved_at_124[0x2];
3995 	u8         self_lb_block[0x2];
3996 	u8         transport_domain[0x18];
3997 
3998 	u8         rx_hash_toeplitz_key[10][0x20];
3999 
4000 	struct mlx5_ifc_rx_hash_field_select_bits rx_hash_field_selector_outer;
4001 
4002 	struct mlx5_ifc_rx_hash_field_select_bits rx_hash_field_selector_inner;
4003 
4004 	u8         reserved_at_2c0[0x4c0];
4005 };
4006 
4007 enum {
4008 	MLX5_SRQC_STATE_GOOD   = 0x0,
4009 	MLX5_SRQC_STATE_ERROR  = 0x1,
4010 };
4011 
4012 struct mlx5_ifc_srqc_bits {
4013 	u8         state[0x4];
4014 	u8         log_srq_size[0x4];
4015 	u8         reserved_at_8[0x18];
4016 
4017 	u8         wq_signature[0x1];
4018 	u8         cont_srq[0x1];
4019 	u8         reserved_at_22[0x1];
4020 	u8         rlky[0x1];
4021 	u8         reserved_at_24[0x1];
4022 	u8         log_rq_stride[0x3];
4023 	u8         xrcd[0x18];
4024 
4025 	u8         page_offset[0x6];
4026 	u8         reserved_at_46[0x2];
4027 	u8         cqn[0x18];
4028 
4029 	u8         reserved_at_60[0x20];
4030 
4031 	u8         reserved_at_80[0x2];
4032 	u8         log_page_size[0x6];
4033 	u8         reserved_at_88[0x18];
4034 
4035 	u8         reserved_at_a0[0x20];
4036 
4037 	u8         reserved_at_c0[0x8];
4038 	u8         pd[0x18];
4039 
4040 	u8         lwm[0x10];
4041 	u8         wqe_cnt[0x10];
4042 
4043 	u8         reserved_at_100[0x40];
4044 
4045 	u8         dbr_addr[0x40];
4046 
4047 	u8         reserved_at_180[0x80];
4048 };
4049 
4050 enum {
4051 	MLX5_SQC_STATE_RST  = 0x0,
4052 	MLX5_SQC_STATE_RDY  = 0x1,
4053 	MLX5_SQC_STATE_ERR  = 0x3,
4054 };
4055 
4056 struct mlx5_ifc_sqc_bits {
4057 	u8         rlky[0x1];
4058 	u8         cd_master[0x1];
4059 	u8         fre[0x1];
4060 	u8         flush_in_error_en[0x1];
4061 	u8         allow_multi_pkt_send_wqe[0x1];
4062 	u8	   min_wqe_inline_mode[0x3];
4063 	u8         state[0x4];
4064 	u8         reg_umr[0x1];
4065 	u8         allow_swp[0x1];
4066 	u8         hairpin[0x1];
4067 	u8         non_wire[0x1];
4068 	u8         reserved_at_10[0xa];
4069 	u8	   ts_format[0x2];
4070 	u8	   reserved_at_1c[0x4];
4071 
4072 	u8         reserved_at_20[0x8];
4073 	u8         user_index[0x18];
4074 
4075 	u8         reserved_at_40[0x8];
4076 	u8         cqn[0x18];
4077 
4078 	u8         reserved_at_60[0x8];
4079 	u8         hairpin_peer_rq[0x18];
4080 
4081 	u8         reserved_at_80[0x10];
4082 	u8         hairpin_peer_vhca[0x10];
4083 
4084 	u8         reserved_at_a0[0x20];
4085 
4086 	u8         reserved_at_c0[0x8];
4087 	u8         ts_cqe_to_dest_cqn[0x18];
4088 
4089 	u8         reserved_at_e0[0x10];
4090 	u8         packet_pacing_rate_limit_index[0x10];
4091 	u8         tis_lst_sz[0x10];
4092 	u8         qos_queue_group_id[0x10];
4093 
4094 	u8         reserved_at_120[0x40];
4095 
4096 	u8         reserved_at_160[0x8];
4097 	u8         tis_num_0[0x18];
4098 
4099 	struct mlx5_ifc_wq_bits wq;
4100 };
4101 
4102 enum {
4103 	SCHEDULING_CONTEXT_ELEMENT_TYPE_TSAR = 0x0,
4104 	SCHEDULING_CONTEXT_ELEMENT_TYPE_VPORT = 0x1,
4105 	SCHEDULING_CONTEXT_ELEMENT_TYPE_VPORT_TC = 0x2,
4106 	SCHEDULING_CONTEXT_ELEMENT_TYPE_PARA_VPORT_TC = 0x3,
4107 	SCHEDULING_CONTEXT_ELEMENT_TYPE_QUEUE_GROUP = 0x4,
4108 };
4109 
4110 enum {
4111 	ELEMENT_TYPE_CAP_MASK_TSAR		= 1 << 0,
4112 	ELEMENT_TYPE_CAP_MASK_VPORT		= 1 << 1,
4113 	ELEMENT_TYPE_CAP_MASK_VPORT_TC		= 1 << 2,
4114 	ELEMENT_TYPE_CAP_MASK_PARA_VPORT_TC	= 1 << 3,
4115 	ELEMENT_TYPE_CAP_MASK_QUEUE_GROUP	= 1 << 4,
4116 };
4117 
4118 enum {
4119 	TSAR_ELEMENT_TSAR_TYPE_DWRR = 0x0,
4120 	TSAR_ELEMENT_TSAR_TYPE_ROUND_ROBIN = 0x1,
4121 	TSAR_ELEMENT_TSAR_TYPE_ETS = 0x2,
4122 };
4123 
4124 enum {
4125 	TSAR_TYPE_CAP_MASK_DWRR		= 1 << 0,
4126 	TSAR_TYPE_CAP_MASK_ROUND_ROBIN	= 1 << 1,
4127 	TSAR_TYPE_CAP_MASK_ETS		= 1 << 2,
4128 };
4129 
4130 struct mlx5_ifc_tsar_element_bits {
4131 	u8         reserved_at_0[0x8];
4132 	u8         tsar_type[0x8];
4133 	u8         reserved_at_10[0x10];
4134 };
4135 
4136 struct mlx5_ifc_vport_element_bits {
4137 	u8         reserved_at_0[0x10];
4138 	u8         vport_number[0x10];
4139 };
4140 
4141 struct mlx5_ifc_vport_tc_element_bits {
4142 	u8         traffic_class[0x4];
4143 	u8         reserved_at_4[0xc];
4144 	u8         vport_number[0x10];
4145 };
4146 
4147 union mlx5_ifc_element_attributes_bits {
4148 	struct mlx5_ifc_tsar_element_bits tsar;
4149 	struct mlx5_ifc_vport_element_bits vport;
4150 	struct mlx5_ifc_vport_tc_element_bits vport_tc;
4151 	u8 reserved_at_0[0x20];
4152 };
4153 
4154 struct mlx5_ifc_scheduling_context_bits {
4155 	u8         element_type[0x8];
4156 	u8         reserved_at_8[0x18];
4157 
4158 	union mlx5_ifc_element_attributes_bits element_attributes;
4159 
4160 	u8         parent_element_id[0x20];
4161 
4162 	u8         reserved_at_60[0x40];
4163 
4164 	u8         bw_share[0x20];
4165 
4166 	u8         max_average_bw[0x20];
4167 
4168 	u8         reserved_at_e0[0x120];
4169 };
4170 
4171 struct mlx5_ifc_rqtc_bits {
4172 	u8    reserved_at_0[0xa0];
4173 
4174 	u8    reserved_at_a0[0x5];
4175 	u8    list_q_type[0x3];
4176 	u8    reserved_at_a8[0x8];
4177 	u8    rqt_max_size[0x10];
4178 
4179 	u8    rq_vhca_id_format[0x1];
4180 	u8    reserved_at_c1[0xf];
4181 	u8    rqt_actual_size[0x10];
4182 
4183 	u8    reserved_at_e0[0x6a0];
4184 
4185 	union {
4186 		DECLARE_FLEX_ARRAY(struct mlx5_ifc_rq_num_bits, rq_num);
4187 		DECLARE_FLEX_ARRAY(struct mlx5_ifc_rq_vhca_bits, rq_vhca);
4188 	};
4189 };
4190 
4191 enum {
4192 	MLX5_RQC_MEM_RQ_TYPE_MEMORY_RQ_INLINE  = 0x0,
4193 	MLX5_RQC_MEM_RQ_TYPE_MEMORY_RQ_RMP     = 0x1,
4194 };
4195 
4196 enum {
4197 	MLX5_RQC_STATE_RST  = 0x0,
4198 	MLX5_RQC_STATE_RDY  = 0x1,
4199 	MLX5_RQC_STATE_ERR  = 0x3,
4200 };
4201 
4202 enum {
4203 	MLX5_RQC_SHAMPO_NO_MATCH_ALIGNMENT_GRANULARITY_BYTE    = 0x0,
4204 	MLX5_RQC_SHAMPO_NO_MATCH_ALIGNMENT_GRANULARITY_STRIDE  = 0x1,
4205 	MLX5_RQC_SHAMPO_NO_MATCH_ALIGNMENT_GRANULARITY_PAGE    = 0x2,
4206 };
4207 
4208 enum {
4209 	MLX5_RQC_SHAMPO_MATCH_CRITERIA_TYPE_NO_MATCH    = 0x0,
4210 	MLX5_RQC_SHAMPO_MATCH_CRITERIA_TYPE_EXTENDED    = 0x1,
4211 	MLX5_RQC_SHAMPO_MATCH_CRITERIA_TYPE_FIVE_TUPLE  = 0x2,
4212 };
4213 
4214 struct mlx5_ifc_rqc_bits {
4215 	u8         rlky[0x1];
4216 	u8	   delay_drop_en[0x1];
4217 	u8         scatter_fcs[0x1];
4218 	u8         vsd[0x1];
4219 	u8         mem_rq_type[0x4];
4220 	u8         state[0x4];
4221 	u8         reserved_at_c[0x1];
4222 	u8         flush_in_error_en[0x1];
4223 	u8         hairpin[0x1];
4224 	u8         reserved_at_f[0xb];
4225 	u8	   ts_format[0x2];
4226 	u8	   reserved_at_1c[0x4];
4227 
4228 	u8         reserved_at_20[0x8];
4229 	u8         user_index[0x18];
4230 
4231 	u8         reserved_at_40[0x8];
4232 	u8         cqn[0x18];
4233 
4234 	u8         counter_set_id[0x8];
4235 	u8         reserved_at_68[0x18];
4236 
4237 	u8         reserved_at_80[0x8];
4238 	u8         rmpn[0x18];
4239 
4240 	u8         reserved_at_a0[0x8];
4241 	u8         hairpin_peer_sq[0x18];
4242 
4243 	u8         reserved_at_c0[0x10];
4244 	u8         hairpin_peer_vhca[0x10];
4245 
4246 	u8         reserved_at_e0[0x46];
4247 	u8         shampo_no_match_alignment_granularity[0x2];
4248 	u8         reserved_at_128[0x6];
4249 	u8         shampo_match_criteria_type[0x2];
4250 	u8         reservation_timeout[0x10];
4251 
4252 	u8         reserved_at_140[0x40];
4253 
4254 	struct mlx5_ifc_wq_bits wq;
4255 };
4256 
4257 enum {
4258 	MLX5_RMPC_STATE_RDY  = 0x1,
4259 	MLX5_RMPC_STATE_ERR  = 0x3,
4260 };
4261 
4262 struct mlx5_ifc_rmpc_bits {
4263 	u8         reserved_at_0[0x8];
4264 	u8         state[0x4];
4265 	u8         reserved_at_c[0x14];
4266 
4267 	u8         basic_cyclic_rcv_wqe[0x1];
4268 	u8         reserved_at_21[0x1f];
4269 
4270 	u8         reserved_at_40[0x140];
4271 
4272 	struct mlx5_ifc_wq_bits wq;
4273 };
4274 
4275 enum {
4276 	VHCA_ID_TYPE_HW = 0,
4277 	VHCA_ID_TYPE_SW = 1,
4278 };
4279 
4280 struct mlx5_ifc_nic_vport_context_bits {
4281 	u8         reserved_at_0[0x5];
4282 	u8         min_wqe_inline_mode[0x3];
4283 	u8         reserved_at_8[0x15];
4284 	u8         disable_mc_local_lb[0x1];
4285 	u8         disable_uc_local_lb[0x1];
4286 	u8         roce_en[0x1];
4287 
4288 	u8         arm_change_event[0x1];
4289 	u8         reserved_at_21[0x1a];
4290 	u8         event_on_mtu[0x1];
4291 	u8         event_on_promisc_change[0x1];
4292 	u8         event_on_vlan_change[0x1];
4293 	u8         event_on_mc_address_change[0x1];
4294 	u8         event_on_uc_address_change[0x1];
4295 
4296 	u8         vhca_id_type[0x1];
4297 	u8         reserved_at_41[0xb];
4298 	u8	   affiliation_criteria[0x4];
4299 	u8	   affiliated_vhca_id[0x10];
4300 
4301 	u8	   reserved_at_60[0xa0];
4302 
4303 	u8	   reserved_at_100[0x1];
4304 	u8         sd_group[0x3];
4305 	u8	   reserved_at_104[0x1c];
4306 
4307 	u8	   reserved_at_120[0x10];
4308 	u8         mtu[0x10];
4309 
4310 	u8         system_image_guid[0x40];
4311 	u8         port_guid[0x40];
4312 	u8         node_guid[0x40];
4313 
4314 	u8         reserved_at_200[0x140];
4315 	u8         qkey_violation_counter[0x10];
4316 	u8         reserved_at_350[0x430];
4317 
4318 	u8         promisc_uc[0x1];
4319 	u8         promisc_mc[0x1];
4320 	u8         promisc_all[0x1];
4321 	u8         reserved_at_783[0x2];
4322 	u8         allowed_list_type[0x3];
4323 	u8         reserved_at_788[0xc];
4324 	u8         allowed_list_size[0xc];
4325 
4326 	struct mlx5_ifc_mac_address_layout_bits permanent_address;
4327 
4328 	u8         reserved_at_7e0[0x20];
4329 
4330 	u8         current_uc_mac_address[][0x40];
4331 };
4332 
4333 enum {
4334 	MLX5_MKC_ACCESS_MODE_PA    = 0x0,
4335 	MLX5_MKC_ACCESS_MODE_MTT   = 0x1,
4336 	MLX5_MKC_ACCESS_MODE_KLMS  = 0x2,
4337 	MLX5_MKC_ACCESS_MODE_KSM   = 0x3,
4338 	MLX5_MKC_ACCESS_MODE_SW_ICM = 0x4,
4339 	MLX5_MKC_ACCESS_MODE_MEMIC = 0x5,
4340 	MLX5_MKC_ACCESS_MODE_CROSSING = 0x6,
4341 };
4342 
4343 struct mlx5_ifc_mkc_bits {
4344 	u8         reserved_at_0[0x1];
4345 	u8         free[0x1];
4346 	u8         reserved_at_2[0x1];
4347 	u8         access_mode_4_2[0x3];
4348 	u8         reserved_at_6[0x7];
4349 	u8         relaxed_ordering_write[0x1];
4350 	u8         reserved_at_e[0x1];
4351 	u8         small_fence_on_rdma_read_response[0x1];
4352 	u8         umr_en[0x1];
4353 	u8         a[0x1];
4354 	u8         rw[0x1];
4355 	u8         rr[0x1];
4356 	u8         lw[0x1];
4357 	u8         lr[0x1];
4358 	u8         access_mode_1_0[0x2];
4359 	u8         reserved_at_18[0x2];
4360 	u8         ma_translation_mode[0x2];
4361 	u8         reserved_at_1c[0x4];
4362 
4363 	u8         qpn[0x18];
4364 	u8         mkey_7_0[0x8];
4365 
4366 	u8         reserved_at_40[0x20];
4367 
4368 	u8         length64[0x1];
4369 	u8         bsf_en[0x1];
4370 	u8         sync_umr[0x1];
4371 	u8         reserved_at_63[0x2];
4372 	u8         expected_sigerr_count[0x1];
4373 	u8         reserved_at_66[0x1];
4374 	u8         en_rinval[0x1];
4375 	u8         pd[0x18];
4376 
4377 	u8         start_addr[0x40];
4378 
4379 	u8         len[0x40];
4380 
4381 	u8         bsf_octword_size[0x20];
4382 
4383 	u8         reserved_at_120[0x60];
4384 
4385 	u8         crossing_target_vhca_id[0x10];
4386 	u8         reserved_at_190[0x10];
4387 
4388 	u8         translations_octword_size[0x20];
4389 
4390 	u8         reserved_at_1c0[0x19];
4391 	u8         relaxed_ordering_read[0x1];
4392 	u8         log_page_size[0x6];
4393 
4394 	u8         reserved_at_1e0[0x20];
4395 };
4396 
4397 struct mlx5_ifc_pkey_bits {
4398 	u8         reserved_at_0[0x10];
4399 	u8         pkey[0x10];
4400 };
4401 
4402 struct mlx5_ifc_array128_auto_bits {
4403 	u8         array128_auto[16][0x8];
4404 };
4405 
4406 struct mlx5_ifc_hca_vport_context_bits {
4407 	u8         field_select[0x20];
4408 
4409 	u8         reserved_at_20[0xe0];
4410 
4411 	u8         sm_virt_aware[0x1];
4412 	u8         has_smi[0x1];
4413 	u8         has_raw[0x1];
4414 	u8         grh_required[0x1];
4415 	u8         reserved_at_104[0x4];
4416 	u8         num_port_plane[0x8];
4417 	u8         port_physical_state[0x4];
4418 	u8         vport_state_policy[0x4];
4419 	u8         port_state[0x4];
4420 	u8         vport_state[0x4];
4421 
4422 	u8         reserved_at_120[0x20];
4423 
4424 	u8         system_image_guid[0x40];
4425 
4426 	u8         port_guid[0x40];
4427 
4428 	u8         node_guid[0x40];
4429 
4430 	u8         cap_mask1[0x20];
4431 
4432 	u8         cap_mask1_field_select[0x20];
4433 
4434 	u8         cap_mask2[0x20];
4435 
4436 	u8         cap_mask2_field_select[0x20];
4437 
4438 	u8         reserved_at_280[0x80];
4439 
4440 	u8         lid[0x10];
4441 	u8         reserved_at_310[0x4];
4442 	u8         init_type_reply[0x4];
4443 	u8         lmc[0x3];
4444 	u8         subnet_timeout[0x5];
4445 
4446 	u8         sm_lid[0x10];
4447 	u8         sm_sl[0x4];
4448 	u8         reserved_at_334[0xc];
4449 
4450 	u8         qkey_violation_counter[0x10];
4451 	u8         pkey_violation_counter[0x10];
4452 
4453 	u8         reserved_at_360[0xca0];
4454 };
4455 
4456 struct mlx5_ifc_esw_vport_context_bits {
4457 	u8         fdb_to_vport_reg_c[0x1];
4458 	u8         reserved_at_1[0x2];
4459 	u8         vport_svlan_strip[0x1];
4460 	u8         vport_cvlan_strip[0x1];
4461 	u8         vport_svlan_insert[0x1];
4462 	u8         vport_cvlan_insert[0x2];
4463 	u8         fdb_to_vport_reg_c_id[0x8];
4464 	u8         reserved_at_10[0x10];
4465 
4466 	u8         reserved_at_20[0x20];
4467 
4468 	u8         svlan_cfi[0x1];
4469 	u8         svlan_pcp[0x3];
4470 	u8         svlan_id[0xc];
4471 	u8         cvlan_cfi[0x1];
4472 	u8         cvlan_pcp[0x3];
4473 	u8         cvlan_id[0xc];
4474 
4475 	u8         reserved_at_60[0x720];
4476 
4477 	u8         sw_steering_vport_icm_address_rx[0x40];
4478 
4479 	u8         sw_steering_vport_icm_address_tx[0x40];
4480 };
4481 
4482 enum {
4483 	MLX5_EQC_STATUS_OK                = 0x0,
4484 	MLX5_EQC_STATUS_EQ_WRITE_FAILURE  = 0xa,
4485 };
4486 
4487 enum {
4488 	MLX5_EQC_ST_ARMED  = 0x9,
4489 	MLX5_EQC_ST_FIRED  = 0xa,
4490 };
4491 
4492 struct mlx5_ifc_eqc_bits {
4493 	u8         status[0x4];
4494 	u8         reserved_at_4[0x9];
4495 	u8         ec[0x1];
4496 	u8         oi[0x1];
4497 	u8         reserved_at_f[0x5];
4498 	u8         st[0x4];
4499 	u8         reserved_at_18[0x8];
4500 
4501 	u8         reserved_at_20[0x20];
4502 
4503 	u8         reserved_at_40[0x14];
4504 	u8         page_offset[0x6];
4505 	u8         reserved_at_5a[0x6];
4506 
4507 	u8         reserved_at_60[0x3];
4508 	u8         log_eq_size[0x5];
4509 	u8         uar_page[0x18];
4510 
4511 	u8         reserved_at_80[0x20];
4512 
4513 	u8         reserved_at_a0[0x14];
4514 	u8         intr[0xc];
4515 
4516 	u8         reserved_at_c0[0x3];
4517 	u8         log_page_size[0x5];
4518 	u8         reserved_at_c8[0x18];
4519 
4520 	u8         reserved_at_e0[0x60];
4521 
4522 	u8         reserved_at_140[0x8];
4523 	u8         consumer_counter[0x18];
4524 
4525 	u8         reserved_at_160[0x8];
4526 	u8         producer_counter[0x18];
4527 
4528 	u8         reserved_at_180[0x80];
4529 };
4530 
4531 enum {
4532 	MLX5_DCTC_STATE_ACTIVE    = 0x0,
4533 	MLX5_DCTC_STATE_DRAINING  = 0x1,
4534 	MLX5_DCTC_STATE_DRAINED   = 0x2,
4535 };
4536 
4537 enum {
4538 	MLX5_DCTC_CS_RES_DISABLE    = 0x0,
4539 	MLX5_DCTC_CS_RES_NA         = 0x1,
4540 	MLX5_DCTC_CS_RES_UP_TO_64B  = 0x2,
4541 };
4542 
4543 enum {
4544 	MLX5_DCTC_MTU_256_BYTES  = 0x1,
4545 	MLX5_DCTC_MTU_512_BYTES  = 0x2,
4546 	MLX5_DCTC_MTU_1K_BYTES   = 0x3,
4547 	MLX5_DCTC_MTU_2K_BYTES   = 0x4,
4548 	MLX5_DCTC_MTU_4K_BYTES   = 0x5,
4549 };
4550 
4551 struct mlx5_ifc_dctc_bits {
4552 	u8         reserved_at_0[0x4];
4553 	u8         state[0x4];
4554 	u8         reserved_at_8[0x18];
4555 
4556 	u8         reserved_at_20[0x7];
4557 	u8         dp_ordering_force[0x1];
4558 	u8         user_index[0x18];
4559 
4560 	u8         reserved_at_40[0x8];
4561 	u8         cqn[0x18];
4562 
4563 	u8         counter_set_id[0x8];
4564 	u8         atomic_mode[0x4];
4565 	u8         rre[0x1];
4566 	u8         rwe[0x1];
4567 	u8         rae[0x1];
4568 	u8         atomic_like_write_en[0x1];
4569 	u8         latency_sensitive[0x1];
4570 	u8         rlky[0x1];
4571 	u8         free_ar[0x1];
4572 	u8         reserved_at_73[0x1];
4573 	u8         dp_ordering_1[0x1];
4574 	u8         reserved_at_75[0xb];
4575 
4576 	u8         reserved_at_80[0x8];
4577 	u8         cs_res[0x8];
4578 	u8         reserved_at_90[0x3];
4579 	u8         min_rnr_nak[0x5];
4580 	u8         reserved_at_98[0x8];
4581 
4582 	u8         reserved_at_a0[0x8];
4583 	u8         srqn_xrqn[0x18];
4584 
4585 	u8         reserved_at_c0[0x8];
4586 	u8         pd[0x18];
4587 
4588 	u8         tclass[0x8];
4589 	u8         reserved_at_e8[0x4];
4590 	u8         flow_label[0x14];
4591 
4592 	u8         dc_access_key[0x40];
4593 
4594 	u8         reserved_at_140[0x5];
4595 	u8         mtu[0x3];
4596 	u8         port[0x8];
4597 	u8         pkey_index[0x10];
4598 
4599 	u8         reserved_at_160[0x8];
4600 	u8         my_addr_index[0x8];
4601 	u8         reserved_at_170[0x8];
4602 	u8         hop_limit[0x8];
4603 
4604 	u8         dc_access_key_violation_count[0x20];
4605 
4606 	u8         reserved_at_1a0[0x14];
4607 	u8         dei_cfi[0x1];
4608 	u8         eth_prio[0x3];
4609 	u8         ecn[0x2];
4610 	u8         dscp[0x6];
4611 
4612 	u8         reserved_at_1c0[0x20];
4613 	u8         ece[0x20];
4614 };
4615 
4616 enum {
4617 	MLX5_CQC_STATUS_OK             = 0x0,
4618 	MLX5_CQC_STATUS_CQ_OVERFLOW    = 0x9,
4619 	MLX5_CQC_STATUS_CQ_WRITE_FAIL  = 0xa,
4620 };
4621 
4622 enum {
4623 	MLX5_CQC_CQE_SZ_64_BYTES   = 0x0,
4624 	MLX5_CQC_CQE_SZ_128_BYTES  = 0x1,
4625 };
4626 
4627 enum {
4628 	MLX5_CQC_ST_SOLICITED_NOTIFICATION_REQUEST_ARMED  = 0x6,
4629 	MLX5_CQC_ST_NOTIFICATION_REQUEST_ARMED            = 0x9,
4630 	MLX5_CQC_ST_FIRED                                 = 0xa,
4631 };
4632 
4633 enum mlx5_cq_period_mode {
4634 	MLX5_CQ_PERIOD_MODE_START_FROM_EQE = 0x0,
4635 	MLX5_CQ_PERIOD_MODE_START_FROM_CQE = 0x1,
4636 	MLX5_CQ_PERIOD_NUM_MODES,
4637 };
4638 
4639 struct mlx5_ifc_cqc_bits {
4640 	u8         status[0x4];
4641 	u8         reserved_at_4[0x2];
4642 	u8         dbr_umem_valid[0x1];
4643 	u8         apu_cq[0x1];
4644 	u8         cqe_sz[0x3];
4645 	u8         cc[0x1];
4646 	u8         reserved_at_c[0x1];
4647 	u8         scqe_break_moderation_en[0x1];
4648 	u8         oi[0x1];
4649 	u8         cq_period_mode[0x2];
4650 	u8         cqe_comp_en[0x1];
4651 	u8         mini_cqe_res_format[0x2];
4652 	u8         st[0x4];
4653 	u8         reserved_at_18[0x6];
4654 	u8         cqe_compression_layout[0x2];
4655 
4656 	u8         reserved_at_20[0x20];
4657 
4658 	u8         reserved_at_40[0x14];
4659 	u8         page_offset[0x6];
4660 	u8         reserved_at_5a[0x6];
4661 
4662 	u8         reserved_at_60[0x3];
4663 	u8         log_cq_size[0x5];
4664 	u8         uar_page[0x18];
4665 
4666 	u8         reserved_at_80[0x4];
4667 	u8         cq_period[0xc];
4668 	u8         cq_max_count[0x10];
4669 
4670 	u8         c_eqn_or_apu_element[0x20];
4671 
4672 	u8         reserved_at_c0[0x3];
4673 	u8         log_page_size[0x5];
4674 	u8         reserved_at_c8[0x18];
4675 
4676 	u8         reserved_at_e0[0x20];
4677 
4678 	u8         reserved_at_100[0x8];
4679 	u8         last_notified_index[0x18];
4680 
4681 	u8         reserved_at_120[0x8];
4682 	u8         last_solicit_index[0x18];
4683 
4684 	u8         reserved_at_140[0x8];
4685 	u8         consumer_counter[0x18];
4686 
4687 	u8         reserved_at_160[0x8];
4688 	u8         producer_counter[0x18];
4689 
4690 	u8         reserved_at_180[0x40];
4691 
4692 	u8         dbr_addr[0x40];
4693 };
4694 
4695 union mlx5_ifc_cong_control_roce_ecn_auto_bits {
4696 	struct mlx5_ifc_cong_control_802_1qau_rp_bits cong_control_802_1qau_rp;
4697 	struct mlx5_ifc_cong_control_r_roce_ecn_rp_bits cong_control_r_roce_ecn_rp;
4698 	struct mlx5_ifc_cong_control_r_roce_ecn_np_bits cong_control_r_roce_ecn_np;
4699 	struct mlx5_ifc_cong_control_r_roce_general_bits cong_control_r_roce_general;
4700 	u8         reserved_at_0[0x800];
4701 };
4702 
4703 struct mlx5_ifc_query_adapter_param_block_bits {
4704 	u8         reserved_at_0[0xc0];
4705 
4706 	u8         reserved_at_c0[0x8];
4707 	u8         ieee_vendor_id[0x18];
4708 
4709 	u8         reserved_at_e0[0x10];
4710 	u8         vsd_vendor_id[0x10];
4711 
4712 	u8         vsd[208][0x8];
4713 
4714 	u8         vsd_contd_psid[16][0x8];
4715 };
4716 
4717 enum {
4718 	MLX5_XRQC_STATE_GOOD   = 0x0,
4719 	MLX5_XRQC_STATE_ERROR  = 0x1,
4720 };
4721 
4722 enum {
4723 	MLX5_XRQC_TOPOLOGY_NO_SPECIAL_TOPOLOGY = 0x0,
4724 	MLX5_XRQC_TOPOLOGY_TAG_MATCHING        = 0x1,
4725 };
4726 
4727 enum {
4728 	MLX5_XRQC_OFFLOAD_RNDV = 0x1,
4729 };
4730 
4731 struct mlx5_ifc_tag_matching_topology_context_bits {
4732 	u8         log_matching_list_sz[0x4];
4733 	u8         reserved_at_4[0xc];
4734 	u8         append_next_index[0x10];
4735 
4736 	u8         sw_phase_cnt[0x10];
4737 	u8         hw_phase_cnt[0x10];
4738 
4739 	u8         reserved_at_40[0x40];
4740 };
4741 
4742 struct mlx5_ifc_xrqc_bits {
4743 	u8         state[0x4];
4744 	u8         rlkey[0x1];
4745 	u8         reserved_at_5[0xf];
4746 	u8         topology[0x4];
4747 	u8         reserved_at_18[0x4];
4748 	u8         offload[0x4];
4749 
4750 	u8         reserved_at_20[0x8];
4751 	u8         user_index[0x18];
4752 
4753 	u8         reserved_at_40[0x8];
4754 	u8         cqn[0x18];
4755 
4756 	u8         reserved_at_60[0xa0];
4757 
4758 	struct mlx5_ifc_tag_matching_topology_context_bits tag_matching_topology_context;
4759 
4760 	u8         reserved_at_180[0x280];
4761 
4762 	struct mlx5_ifc_wq_bits wq;
4763 };
4764 
4765 union mlx5_ifc_modify_field_select_resize_field_select_auto_bits {
4766 	struct mlx5_ifc_modify_field_select_bits modify_field_select;
4767 	struct mlx5_ifc_resize_field_select_bits resize_field_select;
4768 	u8         reserved_at_0[0x20];
4769 };
4770 
4771 union mlx5_ifc_field_select_802_1_r_roce_auto_bits {
4772 	struct mlx5_ifc_field_select_802_1qau_rp_bits field_select_802_1qau_rp;
4773 	struct mlx5_ifc_field_select_r_roce_rp_bits field_select_r_roce_rp;
4774 	struct mlx5_ifc_field_select_r_roce_np_bits field_select_r_roce_np;
4775 	u8         reserved_at_0[0x20];
4776 };
4777 
4778 union mlx5_ifc_eth_cntrs_grp_data_layout_auto_bits {
4779 	struct mlx5_ifc_eth_802_3_cntrs_grp_data_layout_bits eth_802_3_cntrs_grp_data_layout;
4780 	struct mlx5_ifc_eth_2863_cntrs_grp_data_layout_bits eth_2863_cntrs_grp_data_layout;
4781 	struct mlx5_ifc_eth_2819_cntrs_grp_data_layout_bits eth_2819_cntrs_grp_data_layout;
4782 	struct mlx5_ifc_eth_3635_cntrs_grp_data_layout_bits eth_3635_cntrs_grp_data_layout;
4783 	struct mlx5_ifc_eth_extended_cntrs_grp_data_layout_bits eth_extended_cntrs_grp_data_layout;
4784 	struct mlx5_ifc_eth_per_prio_grp_data_layout_bits eth_per_prio_grp_data_layout;
4785 	struct mlx5_ifc_eth_per_tc_prio_grp_data_layout_bits eth_per_tc_prio_grp_data_layout;
4786 	struct mlx5_ifc_eth_per_tc_congest_prio_grp_data_layout_bits eth_per_tc_congest_prio_grp_data_layout;
4787 	struct mlx5_ifc_ib_port_cntrs_grp_data_layout_bits ib_port_cntrs_grp_data_layout;
4788 	struct mlx5_ifc_ib_ext_port_cntrs_grp_data_layout_bits ib_ext_port_cntrs_grp_data_layout;
4789 	struct mlx5_ifc_phys_layer_cntrs_bits phys_layer_cntrs;
4790 	struct mlx5_ifc_phys_layer_statistical_cntrs_bits phys_layer_statistical_cntrs;
4791 	u8         reserved_at_0[0x7c0];
4792 };
4793 
4794 union mlx5_ifc_pcie_cntrs_grp_data_layout_auto_bits {
4795 	struct mlx5_ifc_pcie_perf_cntrs_grp_data_layout_bits pcie_perf_cntrs_grp_data_layout;
4796 	u8         reserved_at_0[0x7c0];
4797 };
4798 
4799 union mlx5_ifc_event_auto_bits {
4800 	struct mlx5_ifc_comp_event_bits comp_event;
4801 	struct mlx5_ifc_dct_events_bits dct_events;
4802 	struct mlx5_ifc_qp_events_bits qp_events;
4803 	struct mlx5_ifc_wqe_associated_page_fault_event_bits wqe_associated_page_fault_event;
4804 	struct mlx5_ifc_rdma_page_fault_event_bits rdma_page_fault_event;
4805 	struct mlx5_ifc_cq_error_bits cq_error;
4806 	struct mlx5_ifc_dropped_packet_logged_bits dropped_packet_logged;
4807 	struct mlx5_ifc_port_state_change_event_bits port_state_change_event;
4808 	struct mlx5_ifc_gpio_event_bits gpio_event;
4809 	struct mlx5_ifc_db_bf_congestion_event_bits db_bf_congestion_event;
4810 	struct mlx5_ifc_stall_vl_event_bits stall_vl_event;
4811 	struct mlx5_ifc_cmd_inter_comp_event_bits cmd_inter_comp_event;
4812 	u8         reserved_at_0[0xe0];
4813 };
4814 
4815 struct mlx5_ifc_health_buffer_bits {
4816 	u8         reserved_at_0[0x100];
4817 
4818 	u8         assert_existptr[0x20];
4819 
4820 	u8         assert_callra[0x20];
4821 
4822 	u8         reserved_at_140[0x20];
4823 
4824 	u8         time[0x20];
4825 
4826 	u8         fw_version[0x20];
4827 
4828 	u8         hw_id[0x20];
4829 
4830 	u8         rfr[0x1];
4831 	u8         reserved_at_1c1[0x3];
4832 	u8         valid[0x1];
4833 	u8         severity[0x3];
4834 	u8         reserved_at_1c8[0x18];
4835 
4836 	u8         irisc_index[0x8];
4837 	u8         synd[0x8];
4838 	u8         ext_synd[0x10];
4839 };
4840 
4841 struct mlx5_ifc_register_loopback_control_bits {
4842 	u8         no_lb[0x1];
4843 	u8         reserved_at_1[0x7];
4844 	u8         port[0x8];
4845 	u8         reserved_at_10[0x10];
4846 
4847 	u8         reserved_at_20[0x60];
4848 };
4849 
4850 enum {
4851 	MLX5_TEARDOWN_HCA_OUT_FORCE_STATE_SUCCESS = 0x0,
4852 	MLX5_TEARDOWN_HCA_OUT_FORCE_STATE_FAIL = 0x1,
4853 };
4854 
4855 struct mlx5_ifc_teardown_hca_out_bits {
4856 	u8         status[0x8];
4857 	u8         reserved_at_8[0x18];
4858 
4859 	u8         syndrome[0x20];
4860 
4861 	u8         reserved_at_40[0x3f];
4862 
4863 	u8         state[0x1];
4864 };
4865 
4866 enum {
4867 	MLX5_TEARDOWN_HCA_IN_PROFILE_GRACEFUL_CLOSE  = 0x0,
4868 	MLX5_TEARDOWN_HCA_IN_PROFILE_FORCE_CLOSE     = 0x1,
4869 	MLX5_TEARDOWN_HCA_IN_PROFILE_PREPARE_FAST_TEARDOWN = 0x2,
4870 };
4871 
4872 struct mlx5_ifc_teardown_hca_in_bits {
4873 	u8         opcode[0x10];
4874 	u8         reserved_at_10[0x10];
4875 
4876 	u8         reserved_at_20[0x10];
4877 	u8         op_mod[0x10];
4878 
4879 	u8         reserved_at_40[0x10];
4880 	u8         profile[0x10];
4881 
4882 	u8         reserved_at_60[0x20];
4883 };
4884 
4885 struct mlx5_ifc_sqerr2rts_qp_out_bits {
4886 	u8         status[0x8];
4887 	u8         reserved_at_8[0x18];
4888 
4889 	u8         syndrome[0x20];
4890 
4891 	u8         reserved_at_40[0x40];
4892 };
4893 
4894 struct mlx5_ifc_sqerr2rts_qp_in_bits {
4895 	u8         opcode[0x10];
4896 	u8         uid[0x10];
4897 
4898 	u8         reserved_at_20[0x10];
4899 	u8         op_mod[0x10];
4900 
4901 	u8         reserved_at_40[0x8];
4902 	u8         qpn[0x18];
4903 
4904 	u8         reserved_at_60[0x20];
4905 
4906 	u8         opt_param_mask[0x20];
4907 
4908 	u8         reserved_at_a0[0x20];
4909 
4910 	struct mlx5_ifc_qpc_bits qpc;
4911 
4912 	u8         reserved_at_800[0x80];
4913 };
4914 
4915 struct mlx5_ifc_sqd2rts_qp_out_bits {
4916 	u8         status[0x8];
4917 	u8         reserved_at_8[0x18];
4918 
4919 	u8         syndrome[0x20];
4920 
4921 	u8         reserved_at_40[0x40];
4922 };
4923 
4924 struct mlx5_ifc_sqd2rts_qp_in_bits {
4925 	u8         opcode[0x10];
4926 	u8         uid[0x10];
4927 
4928 	u8         reserved_at_20[0x10];
4929 	u8         op_mod[0x10];
4930 
4931 	u8         reserved_at_40[0x8];
4932 	u8         qpn[0x18];
4933 
4934 	u8         reserved_at_60[0x20];
4935 
4936 	u8         opt_param_mask[0x20];
4937 
4938 	u8         reserved_at_a0[0x20];
4939 
4940 	struct mlx5_ifc_qpc_bits qpc;
4941 
4942 	u8         reserved_at_800[0x80];
4943 };
4944 
4945 struct mlx5_ifc_set_roce_address_out_bits {
4946 	u8         status[0x8];
4947 	u8         reserved_at_8[0x18];
4948 
4949 	u8         syndrome[0x20];
4950 
4951 	u8         reserved_at_40[0x40];
4952 };
4953 
4954 struct mlx5_ifc_set_roce_address_in_bits {
4955 	u8         opcode[0x10];
4956 	u8         reserved_at_10[0x10];
4957 
4958 	u8         reserved_at_20[0x10];
4959 	u8         op_mod[0x10];
4960 
4961 	u8         roce_address_index[0x10];
4962 	u8         reserved_at_50[0xc];
4963 	u8	   vhca_port_num[0x4];
4964 
4965 	u8         reserved_at_60[0x20];
4966 
4967 	struct mlx5_ifc_roce_addr_layout_bits roce_address;
4968 };
4969 
4970 struct mlx5_ifc_set_mad_demux_out_bits {
4971 	u8         status[0x8];
4972 	u8         reserved_at_8[0x18];
4973 
4974 	u8         syndrome[0x20];
4975 
4976 	u8         reserved_at_40[0x40];
4977 };
4978 
4979 enum {
4980 	MLX5_SET_MAD_DEMUX_IN_DEMUX_MODE_PASS_ALL   = 0x0,
4981 	MLX5_SET_MAD_DEMUX_IN_DEMUX_MODE_SELECTIVE  = 0x2,
4982 };
4983 
4984 struct mlx5_ifc_set_mad_demux_in_bits {
4985 	u8         opcode[0x10];
4986 	u8         reserved_at_10[0x10];
4987 
4988 	u8         reserved_at_20[0x10];
4989 	u8         op_mod[0x10];
4990 
4991 	u8         reserved_at_40[0x20];
4992 
4993 	u8         reserved_at_60[0x6];
4994 	u8         demux_mode[0x2];
4995 	u8         reserved_at_68[0x18];
4996 };
4997 
4998 struct mlx5_ifc_set_l2_table_entry_out_bits {
4999 	u8         status[0x8];
5000 	u8         reserved_at_8[0x18];
5001 
5002 	u8         syndrome[0x20];
5003 
5004 	u8         reserved_at_40[0x40];
5005 };
5006 
5007 struct mlx5_ifc_set_l2_table_entry_in_bits {
5008 	u8         opcode[0x10];
5009 	u8         reserved_at_10[0x10];
5010 
5011 	u8         reserved_at_20[0x10];
5012 	u8         op_mod[0x10];
5013 
5014 	u8         reserved_at_40[0x60];
5015 
5016 	u8         reserved_at_a0[0x8];
5017 	u8         table_index[0x18];
5018 
5019 	u8         reserved_at_c0[0x20];
5020 
5021 	u8         reserved_at_e0[0x10];
5022 	u8         silent_mode_valid[0x1];
5023 	u8         silent_mode[0x1];
5024 	u8         reserved_at_f2[0x1];
5025 	u8         vlan_valid[0x1];
5026 	u8         vlan[0xc];
5027 
5028 	struct mlx5_ifc_mac_address_layout_bits mac_address;
5029 
5030 	u8         reserved_at_140[0xc0];
5031 };
5032 
5033 struct mlx5_ifc_set_issi_out_bits {
5034 	u8         status[0x8];
5035 	u8         reserved_at_8[0x18];
5036 
5037 	u8         syndrome[0x20];
5038 
5039 	u8         reserved_at_40[0x40];
5040 };
5041 
5042 struct mlx5_ifc_set_issi_in_bits {
5043 	u8         opcode[0x10];
5044 	u8         reserved_at_10[0x10];
5045 
5046 	u8         reserved_at_20[0x10];
5047 	u8         op_mod[0x10];
5048 
5049 	u8         reserved_at_40[0x10];
5050 	u8         current_issi[0x10];
5051 
5052 	u8         reserved_at_60[0x20];
5053 };
5054 
5055 struct mlx5_ifc_set_hca_cap_out_bits {
5056 	u8         status[0x8];
5057 	u8         reserved_at_8[0x18];
5058 
5059 	u8         syndrome[0x20];
5060 
5061 	u8         reserved_at_40[0x40];
5062 };
5063 
5064 struct mlx5_ifc_set_hca_cap_in_bits {
5065 	u8         opcode[0x10];
5066 	u8         reserved_at_10[0x10];
5067 
5068 	u8         reserved_at_20[0x10];
5069 	u8         op_mod[0x10];
5070 
5071 	u8         other_function[0x1];
5072 	u8         ec_vf_function[0x1];
5073 	u8         reserved_at_42[0xe];
5074 	u8         function_id[0x10];
5075 
5076 	u8         reserved_at_60[0x20];
5077 
5078 	union mlx5_ifc_hca_cap_union_bits capability;
5079 };
5080 
5081 enum {
5082 	MLX5_SET_FTE_MODIFY_ENABLE_MASK_ACTION    = 0x0,
5083 	MLX5_SET_FTE_MODIFY_ENABLE_MASK_FLOW_TAG  = 0x1,
5084 	MLX5_SET_FTE_MODIFY_ENABLE_MASK_DESTINATION_LIST    = 0x2,
5085 	MLX5_SET_FTE_MODIFY_ENABLE_MASK_FLOW_COUNTERS    = 0x3,
5086 	MLX5_SET_FTE_MODIFY_ENABLE_MASK_IPSEC_OBJ_ID    = 0x4
5087 };
5088 
5089 struct mlx5_ifc_set_fte_out_bits {
5090 	u8         status[0x8];
5091 	u8         reserved_at_8[0x18];
5092 
5093 	u8         syndrome[0x20];
5094 
5095 	u8         reserved_at_40[0x40];
5096 };
5097 
5098 struct mlx5_ifc_set_fte_in_bits {
5099 	u8         opcode[0x10];
5100 	u8         reserved_at_10[0x10];
5101 
5102 	u8         reserved_at_20[0x10];
5103 	u8         op_mod[0x10];
5104 
5105 	u8         other_vport[0x1];
5106 	u8         reserved_at_41[0xf];
5107 	u8         vport_number[0x10];
5108 
5109 	u8         reserved_at_60[0x20];
5110 
5111 	u8         table_type[0x8];
5112 	u8         reserved_at_88[0x18];
5113 
5114 	u8         reserved_at_a0[0x8];
5115 	u8         table_id[0x18];
5116 
5117 	u8         ignore_flow_level[0x1];
5118 	u8         reserved_at_c1[0x17];
5119 	u8         modify_enable_mask[0x8];
5120 
5121 	u8         reserved_at_e0[0x20];
5122 
5123 	u8         flow_index[0x20];
5124 
5125 	u8         reserved_at_120[0xe0];
5126 
5127 	struct mlx5_ifc_flow_context_bits flow_context;
5128 };
5129 
5130 struct mlx5_ifc_dest_format_bits {
5131 	u8         destination_type[0x8];
5132 	u8         destination_id[0x18];
5133 
5134 	u8         destination_eswitch_owner_vhca_id_valid[0x1];
5135 	u8         packet_reformat[0x1];
5136 	u8         reserved_at_22[0xe];
5137 	u8         destination_eswitch_owner_vhca_id[0x10];
5138 };
5139 
5140 struct mlx5_ifc_rts2rts_qp_out_bits {
5141 	u8         status[0x8];
5142 	u8         reserved_at_8[0x18];
5143 
5144 	u8         syndrome[0x20];
5145 
5146 	u8         reserved_at_40[0x20];
5147 	u8         ece[0x20];
5148 };
5149 
5150 struct mlx5_ifc_rts2rts_qp_in_bits {
5151 	u8         opcode[0x10];
5152 	u8         uid[0x10];
5153 
5154 	u8         reserved_at_20[0x10];
5155 	u8         op_mod[0x10];
5156 
5157 	u8         reserved_at_40[0x8];
5158 	u8         qpn[0x18];
5159 
5160 	u8         reserved_at_60[0x20];
5161 
5162 	u8         opt_param_mask[0x20];
5163 
5164 	u8         ece[0x20];
5165 
5166 	struct mlx5_ifc_qpc_bits qpc;
5167 
5168 	u8         reserved_at_800[0x80];
5169 };
5170 
5171 struct mlx5_ifc_rtr2rts_qp_out_bits {
5172 	u8         status[0x8];
5173 	u8         reserved_at_8[0x18];
5174 
5175 	u8         syndrome[0x20];
5176 
5177 	u8         reserved_at_40[0x20];
5178 	u8         ece[0x20];
5179 };
5180 
5181 struct mlx5_ifc_rtr2rts_qp_in_bits {
5182 	u8         opcode[0x10];
5183 	u8         uid[0x10];
5184 
5185 	u8         reserved_at_20[0x10];
5186 	u8         op_mod[0x10];
5187 
5188 	u8         reserved_at_40[0x8];
5189 	u8         qpn[0x18];
5190 
5191 	u8         reserved_at_60[0x20];
5192 
5193 	u8         opt_param_mask[0x20];
5194 
5195 	u8         ece[0x20];
5196 
5197 	struct mlx5_ifc_qpc_bits qpc;
5198 
5199 	u8         reserved_at_800[0x80];
5200 };
5201 
5202 struct mlx5_ifc_rst2init_qp_out_bits {
5203 	u8         status[0x8];
5204 	u8         reserved_at_8[0x18];
5205 
5206 	u8         syndrome[0x20];
5207 
5208 	u8         reserved_at_40[0x20];
5209 	u8         ece[0x20];
5210 };
5211 
5212 struct mlx5_ifc_rst2init_qp_in_bits {
5213 	u8         opcode[0x10];
5214 	u8         uid[0x10];
5215 
5216 	u8         reserved_at_20[0x10];
5217 	u8         op_mod[0x10];
5218 
5219 	u8         reserved_at_40[0x8];
5220 	u8         qpn[0x18];
5221 
5222 	u8         reserved_at_60[0x20];
5223 
5224 	u8         opt_param_mask[0x20];
5225 
5226 	u8         ece[0x20];
5227 
5228 	struct mlx5_ifc_qpc_bits qpc;
5229 
5230 	u8         reserved_at_800[0x80];
5231 };
5232 
5233 struct mlx5_ifc_query_xrq_out_bits {
5234 	u8         status[0x8];
5235 	u8         reserved_at_8[0x18];
5236 
5237 	u8         syndrome[0x20];
5238 
5239 	u8         reserved_at_40[0x40];
5240 
5241 	struct mlx5_ifc_xrqc_bits xrq_context;
5242 };
5243 
5244 struct mlx5_ifc_query_xrq_in_bits {
5245 	u8         opcode[0x10];
5246 	u8         reserved_at_10[0x10];
5247 
5248 	u8         reserved_at_20[0x10];
5249 	u8         op_mod[0x10];
5250 
5251 	u8         reserved_at_40[0x8];
5252 	u8         xrqn[0x18];
5253 
5254 	u8         reserved_at_60[0x20];
5255 };
5256 
5257 struct mlx5_ifc_query_xrc_srq_out_bits {
5258 	u8         status[0x8];
5259 	u8         reserved_at_8[0x18];
5260 
5261 	u8         syndrome[0x20];
5262 
5263 	u8         reserved_at_40[0x40];
5264 
5265 	struct mlx5_ifc_xrc_srqc_bits xrc_srq_context_entry;
5266 
5267 	u8         reserved_at_280[0x600];
5268 
5269 	u8         pas[][0x40];
5270 };
5271 
5272 struct mlx5_ifc_query_xrc_srq_in_bits {
5273 	u8         opcode[0x10];
5274 	u8         reserved_at_10[0x10];
5275 
5276 	u8         reserved_at_20[0x10];
5277 	u8         op_mod[0x10];
5278 
5279 	u8         reserved_at_40[0x8];
5280 	u8         xrc_srqn[0x18];
5281 
5282 	u8         reserved_at_60[0x20];
5283 };
5284 
5285 enum {
5286 	MLX5_QUERY_VPORT_STATE_OUT_STATE_DOWN  = 0x0,
5287 	MLX5_QUERY_VPORT_STATE_OUT_STATE_UP    = 0x1,
5288 };
5289 
5290 struct mlx5_ifc_query_vport_state_out_bits {
5291 	u8         status[0x8];
5292 	u8         reserved_at_8[0x18];
5293 
5294 	u8         syndrome[0x20];
5295 
5296 	u8         reserved_at_40[0x20];
5297 
5298 	u8         reserved_at_60[0x18];
5299 	u8         admin_state[0x4];
5300 	u8         state[0x4];
5301 };
5302 
5303 struct mlx5_ifc_array1024_auto_bits {
5304 	u8         array1024_auto[32][0x20];
5305 };
5306 
5307 struct mlx5_ifc_query_vuid_in_bits {
5308 	u8         opcode[0x10];
5309 	u8         uid[0x10];
5310 
5311 	u8         reserved_at_20[0x40];
5312 
5313 	u8         query_vfs_vuid[0x1];
5314 	u8         data_direct[0x1];
5315 	u8         reserved_at_62[0xe];
5316 	u8         vhca_id[0x10];
5317 };
5318 
5319 struct mlx5_ifc_query_vuid_out_bits {
5320 	u8        status[0x8];
5321 	u8        reserved_at_8[0x18];
5322 
5323 	u8        syndrome[0x20];
5324 
5325 	u8        reserved_at_40[0x1a0];
5326 
5327 	u8        reserved_at_1e0[0x10];
5328 	u8        num_of_entries[0x10];
5329 
5330 	struct mlx5_ifc_array1024_auto_bits vuid[];
5331 };
5332 
5333 enum {
5334 	MLX5_VPORT_STATE_OP_MOD_VNIC_VPORT  = 0x0,
5335 	MLX5_VPORT_STATE_OP_MOD_ESW_VPORT   = 0x1,
5336 	MLX5_VPORT_STATE_OP_MOD_UPLINK      = 0x2,
5337 };
5338 
5339 struct mlx5_ifc_arm_monitor_counter_in_bits {
5340 	u8         opcode[0x10];
5341 	u8         uid[0x10];
5342 
5343 	u8         reserved_at_20[0x10];
5344 	u8         op_mod[0x10];
5345 
5346 	u8         reserved_at_40[0x20];
5347 
5348 	u8         reserved_at_60[0x20];
5349 };
5350 
5351 struct mlx5_ifc_arm_monitor_counter_out_bits {
5352 	u8         status[0x8];
5353 	u8         reserved_at_8[0x18];
5354 
5355 	u8         syndrome[0x20];
5356 
5357 	u8         reserved_at_40[0x40];
5358 };
5359 
5360 enum {
5361 	MLX5_QUERY_MONITOR_CNT_TYPE_PPCNT     = 0x0,
5362 	MLX5_QUERY_MONITOR_CNT_TYPE_Q_COUNTER = 0x1,
5363 };
5364 
5365 enum mlx5_monitor_counter_ppcnt {
5366 	MLX5_QUERY_MONITOR_PPCNT_IN_RANGE_LENGTH_ERRORS      = 0x0,
5367 	MLX5_QUERY_MONITOR_PPCNT_OUT_OF_RANGE_LENGTH_FIELD   = 0x1,
5368 	MLX5_QUERY_MONITOR_PPCNT_FRAME_TOO_LONG_ERRORS       = 0x2,
5369 	MLX5_QUERY_MONITOR_PPCNT_FRAME_CHECK_SEQUENCE_ERRORS = 0x3,
5370 	MLX5_QUERY_MONITOR_PPCNT_ALIGNMENT_ERRORS            = 0x4,
5371 	MLX5_QUERY_MONITOR_PPCNT_IF_OUT_DISCARDS             = 0x5,
5372 };
5373 
5374 enum {
5375 	MLX5_QUERY_MONITOR_Q_COUNTER_RX_OUT_OF_BUFFER     = 0x4,
5376 };
5377 
5378 struct mlx5_ifc_monitor_counter_output_bits {
5379 	u8         reserved_at_0[0x4];
5380 	u8         type[0x4];
5381 	u8         reserved_at_8[0x8];
5382 	u8         counter[0x10];
5383 
5384 	u8         counter_group_id[0x20];
5385 };
5386 
5387 #define MLX5_CMD_SET_MONITOR_NUM_PPCNT_COUNTER_SET1 (6)
5388 #define MLX5_CMD_SET_MONITOR_NUM_Q_COUNTERS_SET1    (1)
5389 #define MLX5_CMD_SET_MONITOR_NUM_COUNTER (MLX5_CMD_SET_MONITOR_NUM_PPCNT_COUNTER_SET1 +\
5390 					  MLX5_CMD_SET_MONITOR_NUM_Q_COUNTERS_SET1)
5391 
5392 struct mlx5_ifc_set_monitor_counter_in_bits {
5393 	u8         opcode[0x10];
5394 	u8         uid[0x10];
5395 
5396 	u8         reserved_at_20[0x10];
5397 	u8         op_mod[0x10];
5398 
5399 	u8         reserved_at_40[0x10];
5400 	u8         num_of_counters[0x10];
5401 
5402 	u8         reserved_at_60[0x20];
5403 
5404 	struct mlx5_ifc_monitor_counter_output_bits monitor_counter[MLX5_CMD_SET_MONITOR_NUM_COUNTER];
5405 };
5406 
5407 struct mlx5_ifc_set_monitor_counter_out_bits {
5408 	u8         status[0x8];
5409 	u8         reserved_at_8[0x18];
5410 
5411 	u8         syndrome[0x20];
5412 
5413 	u8         reserved_at_40[0x40];
5414 };
5415 
5416 struct mlx5_ifc_query_vport_state_in_bits {
5417 	u8         opcode[0x10];
5418 	u8         reserved_at_10[0x10];
5419 
5420 	u8         reserved_at_20[0x10];
5421 	u8         op_mod[0x10];
5422 
5423 	u8         other_vport[0x1];
5424 	u8         reserved_at_41[0xf];
5425 	u8         vport_number[0x10];
5426 
5427 	u8         reserved_at_60[0x20];
5428 };
5429 
5430 struct mlx5_ifc_query_vnic_env_out_bits {
5431 	u8         status[0x8];
5432 	u8         reserved_at_8[0x18];
5433 
5434 	u8         syndrome[0x20];
5435 
5436 	u8         reserved_at_40[0x40];
5437 
5438 	struct mlx5_ifc_vnic_diagnostic_statistics_bits vport_env;
5439 };
5440 
5441 enum {
5442 	MLX5_QUERY_VNIC_ENV_IN_OP_MOD_VPORT_DIAG_STATISTICS  = 0x0,
5443 };
5444 
5445 struct mlx5_ifc_query_vnic_env_in_bits {
5446 	u8         opcode[0x10];
5447 	u8         reserved_at_10[0x10];
5448 
5449 	u8         reserved_at_20[0x10];
5450 	u8         op_mod[0x10];
5451 
5452 	u8         other_vport[0x1];
5453 	u8         reserved_at_41[0xf];
5454 	u8         vport_number[0x10];
5455 
5456 	u8         reserved_at_60[0x20];
5457 };
5458 
5459 struct mlx5_ifc_query_vport_counter_out_bits {
5460 	u8         status[0x8];
5461 	u8         reserved_at_8[0x18];
5462 
5463 	u8         syndrome[0x20];
5464 
5465 	u8         reserved_at_40[0x40];
5466 
5467 	struct mlx5_ifc_traffic_counter_bits received_errors;
5468 
5469 	struct mlx5_ifc_traffic_counter_bits transmit_errors;
5470 
5471 	struct mlx5_ifc_traffic_counter_bits received_ib_unicast;
5472 
5473 	struct mlx5_ifc_traffic_counter_bits transmitted_ib_unicast;
5474 
5475 	struct mlx5_ifc_traffic_counter_bits received_ib_multicast;
5476 
5477 	struct mlx5_ifc_traffic_counter_bits transmitted_ib_multicast;
5478 
5479 	struct mlx5_ifc_traffic_counter_bits received_eth_broadcast;
5480 
5481 	struct mlx5_ifc_traffic_counter_bits transmitted_eth_broadcast;
5482 
5483 	struct mlx5_ifc_traffic_counter_bits received_eth_unicast;
5484 
5485 	struct mlx5_ifc_traffic_counter_bits transmitted_eth_unicast;
5486 
5487 	struct mlx5_ifc_traffic_counter_bits received_eth_multicast;
5488 
5489 	struct mlx5_ifc_traffic_counter_bits transmitted_eth_multicast;
5490 
5491 	struct mlx5_ifc_traffic_counter_bits local_loopback;
5492 
5493 	u8         reserved_at_700[0x980];
5494 };
5495 
5496 enum {
5497 	MLX5_QUERY_VPORT_COUNTER_IN_OP_MOD_VPORT_COUNTERS  = 0x0,
5498 };
5499 
5500 struct mlx5_ifc_query_vport_counter_in_bits {
5501 	u8         opcode[0x10];
5502 	u8         reserved_at_10[0x10];
5503 
5504 	u8         reserved_at_20[0x10];
5505 	u8         op_mod[0x10];
5506 
5507 	u8         other_vport[0x1];
5508 	u8         reserved_at_41[0xb];
5509 	u8	   port_num[0x4];
5510 	u8         vport_number[0x10];
5511 
5512 	u8         reserved_at_60[0x60];
5513 
5514 	u8         clear[0x1];
5515 	u8         reserved_at_c1[0x1f];
5516 
5517 	u8         reserved_at_e0[0x20];
5518 };
5519 
5520 struct mlx5_ifc_query_tis_out_bits {
5521 	u8         status[0x8];
5522 	u8         reserved_at_8[0x18];
5523 
5524 	u8         syndrome[0x20];
5525 
5526 	u8         reserved_at_40[0x40];
5527 
5528 	struct mlx5_ifc_tisc_bits tis_context;
5529 };
5530 
5531 struct mlx5_ifc_query_tis_in_bits {
5532 	u8         opcode[0x10];
5533 	u8         reserved_at_10[0x10];
5534 
5535 	u8         reserved_at_20[0x10];
5536 	u8         op_mod[0x10];
5537 
5538 	u8         reserved_at_40[0x8];
5539 	u8         tisn[0x18];
5540 
5541 	u8         reserved_at_60[0x20];
5542 };
5543 
5544 struct mlx5_ifc_query_tir_out_bits {
5545 	u8         status[0x8];
5546 	u8         reserved_at_8[0x18];
5547 
5548 	u8         syndrome[0x20];
5549 
5550 	u8         reserved_at_40[0xc0];
5551 
5552 	struct mlx5_ifc_tirc_bits tir_context;
5553 };
5554 
5555 struct mlx5_ifc_query_tir_in_bits {
5556 	u8         opcode[0x10];
5557 	u8         reserved_at_10[0x10];
5558 
5559 	u8         reserved_at_20[0x10];
5560 	u8         op_mod[0x10];
5561 
5562 	u8         reserved_at_40[0x8];
5563 	u8         tirn[0x18];
5564 
5565 	u8         reserved_at_60[0x20];
5566 };
5567 
5568 struct mlx5_ifc_query_srq_out_bits {
5569 	u8         status[0x8];
5570 	u8         reserved_at_8[0x18];
5571 
5572 	u8         syndrome[0x20];
5573 
5574 	u8         reserved_at_40[0x40];
5575 
5576 	struct mlx5_ifc_srqc_bits srq_context_entry;
5577 
5578 	u8         reserved_at_280[0x600];
5579 
5580 	u8         pas[][0x40];
5581 };
5582 
5583 struct mlx5_ifc_query_srq_in_bits {
5584 	u8         opcode[0x10];
5585 	u8         reserved_at_10[0x10];
5586 
5587 	u8         reserved_at_20[0x10];
5588 	u8         op_mod[0x10];
5589 
5590 	u8         reserved_at_40[0x8];
5591 	u8         srqn[0x18];
5592 
5593 	u8         reserved_at_60[0x20];
5594 };
5595 
5596 struct mlx5_ifc_query_sq_out_bits {
5597 	u8         status[0x8];
5598 	u8         reserved_at_8[0x18];
5599 
5600 	u8         syndrome[0x20];
5601 
5602 	u8         reserved_at_40[0xc0];
5603 
5604 	struct mlx5_ifc_sqc_bits sq_context;
5605 };
5606 
5607 struct mlx5_ifc_query_sq_in_bits {
5608 	u8         opcode[0x10];
5609 	u8         reserved_at_10[0x10];
5610 
5611 	u8         reserved_at_20[0x10];
5612 	u8         op_mod[0x10];
5613 
5614 	u8         reserved_at_40[0x8];
5615 	u8         sqn[0x18];
5616 
5617 	u8         reserved_at_60[0x20];
5618 };
5619 
5620 struct mlx5_ifc_query_special_contexts_out_bits {
5621 	u8         status[0x8];
5622 	u8         reserved_at_8[0x18];
5623 
5624 	u8         syndrome[0x20];
5625 
5626 	u8         dump_fill_mkey[0x20];
5627 
5628 	u8         resd_lkey[0x20];
5629 
5630 	u8         null_mkey[0x20];
5631 
5632 	u8	   terminate_scatter_list_mkey[0x20];
5633 
5634 	u8	   repeated_mkey[0x20];
5635 
5636 	u8         reserved_at_a0[0x20];
5637 };
5638 
5639 struct mlx5_ifc_query_special_contexts_in_bits {
5640 	u8         opcode[0x10];
5641 	u8         reserved_at_10[0x10];
5642 
5643 	u8         reserved_at_20[0x10];
5644 	u8         op_mod[0x10];
5645 
5646 	u8         reserved_at_40[0x40];
5647 };
5648 
5649 struct mlx5_ifc_query_scheduling_element_out_bits {
5650 	u8         opcode[0x10];
5651 	u8         reserved_at_10[0x10];
5652 
5653 	u8         reserved_at_20[0x10];
5654 	u8         op_mod[0x10];
5655 
5656 	u8         reserved_at_40[0xc0];
5657 
5658 	struct mlx5_ifc_scheduling_context_bits scheduling_context;
5659 
5660 	u8         reserved_at_300[0x100];
5661 };
5662 
5663 enum {
5664 	SCHEDULING_HIERARCHY_E_SWITCH = 0x2,
5665 	SCHEDULING_HIERARCHY_NIC = 0x3,
5666 };
5667 
5668 struct mlx5_ifc_query_scheduling_element_in_bits {
5669 	u8         opcode[0x10];
5670 	u8         reserved_at_10[0x10];
5671 
5672 	u8         reserved_at_20[0x10];
5673 	u8         op_mod[0x10];
5674 
5675 	u8         scheduling_hierarchy[0x8];
5676 	u8         reserved_at_48[0x18];
5677 
5678 	u8         scheduling_element_id[0x20];
5679 
5680 	u8         reserved_at_80[0x180];
5681 };
5682 
5683 struct mlx5_ifc_query_rqt_out_bits {
5684 	u8         status[0x8];
5685 	u8         reserved_at_8[0x18];
5686 
5687 	u8         syndrome[0x20];
5688 
5689 	u8         reserved_at_40[0xc0];
5690 
5691 	struct mlx5_ifc_rqtc_bits rqt_context;
5692 };
5693 
5694 struct mlx5_ifc_query_rqt_in_bits {
5695 	u8         opcode[0x10];
5696 	u8         reserved_at_10[0x10];
5697 
5698 	u8         reserved_at_20[0x10];
5699 	u8         op_mod[0x10];
5700 
5701 	u8         reserved_at_40[0x8];
5702 	u8         rqtn[0x18];
5703 
5704 	u8         reserved_at_60[0x20];
5705 };
5706 
5707 struct mlx5_ifc_query_rq_out_bits {
5708 	u8         status[0x8];
5709 	u8         reserved_at_8[0x18];
5710 
5711 	u8         syndrome[0x20];
5712 
5713 	u8         reserved_at_40[0xc0];
5714 
5715 	struct mlx5_ifc_rqc_bits rq_context;
5716 };
5717 
5718 struct mlx5_ifc_query_rq_in_bits {
5719 	u8         opcode[0x10];
5720 	u8         reserved_at_10[0x10];
5721 
5722 	u8         reserved_at_20[0x10];
5723 	u8         op_mod[0x10];
5724 
5725 	u8         reserved_at_40[0x8];
5726 	u8         rqn[0x18];
5727 
5728 	u8         reserved_at_60[0x20];
5729 };
5730 
5731 struct mlx5_ifc_query_roce_address_out_bits {
5732 	u8         status[0x8];
5733 	u8         reserved_at_8[0x18];
5734 
5735 	u8         syndrome[0x20];
5736 
5737 	u8         reserved_at_40[0x40];
5738 
5739 	struct mlx5_ifc_roce_addr_layout_bits roce_address;
5740 };
5741 
5742 struct mlx5_ifc_query_roce_address_in_bits {
5743 	u8         opcode[0x10];
5744 	u8         reserved_at_10[0x10];
5745 
5746 	u8         reserved_at_20[0x10];
5747 	u8         op_mod[0x10];
5748 
5749 	u8         roce_address_index[0x10];
5750 	u8         reserved_at_50[0xc];
5751 	u8	   vhca_port_num[0x4];
5752 
5753 	u8         reserved_at_60[0x20];
5754 };
5755 
5756 struct mlx5_ifc_query_rmp_out_bits {
5757 	u8         status[0x8];
5758 	u8         reserved_at_8[0x18];
5759 
5760 	u8         syndrome[0x20];
5761 
5762 	u8         reserved_at_40[0xc0];
5763 
5764 	struct mlx5_ifc_rmpc_bits rmp_context;
5765 };
5766 
5767 struct mlx5_ifc_query_rmp_in_bits {
5768 	u8         opcode[0x10];
5769 	u8         reserved_at_10[0x10];
5770 
5771 	u8         reserved_at_20[0x10];
5772 	u8         op_mod[0x10];
5773 
5774 	u8         reserved_at_40[0x8];
5775 	u8         rmpn[0x18];
5776 
5777 	u8         reserved_at_60[0x20];
5778 };
5779 
5780 struct mlx5_ifc_cqe_error_syndrome_bits {
5781 	u8         hw_error_syndrome[0x8];
5782 	u8         hw_syndrome_type[0x4];
5783 	u8         reserved_at_c[0x4];
5784 	u8         vendor_error_syndrome[0x8];
5785 	u8         syndrome[0x8];
5786 };
5787 
5788 struct mlx5_ifc_qp_context_extension_bits {
5789 	u8         reserved_at_0[0x60];
5790 
5791 	struct mlx5_ifc_cqe_error_syndrome_bits error_syndrome;
5792 
5793 	u8         reserved_at_80[0x580];
5794 };
5795 
5796 struct mlx5_ifc_qpc_extension_and_pas_list_in_bits {
5797 	struct mlx5_ifc_qp_context_extension_bits qpc_data_extension;
5798 
5799 	u8         pas[0][0x40];
5800 };
5801 
5802 struct mlx5_ifc_qp_pas_list_in_bits {
5803 	struct mlx5_ifc_cmd_pas_bits pas[0];
5804 };
5805 
5806 union mlx5_ifc_qp_pas_or_qpc_ext_and_pas_bits {
5807 	struct mlx5_ifc_qp_pas_list_in_bits qp_pas_list;
5808 	struct mlx5_ifc_qpc_extension_and_pas_list_in_bits qpc_ext_and_pas_list;
5809 };
5810 
5811 struct mlx5_ifc_query_qp_out_bits {
5812 	u8         status[0x8];
5813 	u8         reserved_at_8[0x18];
5814 
5815 	u8         syndrome[0x20];
5816 
5817 	u8         reserved_at_40[0x40];
5818 
5819 	u8         opt_param_mask[0x20];
5820 
5821 	u8         ece[0x20];
5822 
5823 	struct mlx5_ifc_qpc_bits qpc;
5824 
5825 	u8         reserved_at_800[0x80];
5826 
5827 	union mlx5_ifc_qp_pas_or_qpc_ext_and_pas_bits qp_pas_or_qpc_ext_and_pas;
5828 };
5829 
5830 struct mlx5_ifc_query_qp_in_bits {
5831 	u8         opcode[0x10];
5832 	u8         reserved_at_10[0x10];
5833 
5834 	u8         reserved_at_20[0x10];
5835 	u8         op_mod[0x10];
5836 
5837 	u8         qpc_ext[0x1];
5838 	u8         reserved_at_41[0x7];
5839 	u8         qpn[0x18];
5840 
5841 	u8         reserved_at_60[0x20];
5842 };
5843 
5844 struct mlx5_ifc_query_q_counter_out_bits {
5845 	u8         status[0x8];
5846 	u8         reserved_at_8[0x18];
5847 
5848 	u8         syndrome[0x20];
5849 
5850 	u8         reserved_at_40[0x40];
5851 
5852 	u8         rx_write_requests[0x20];
5853 
5854 	u8         reserved_at_a0[0x20];
5855 
5856 	u8         rx_read_requests[0x20];
5857 
5858 	u8         reserved_at_e0[0x20];
5859 
5860 	u8         rx_atomic_requests[0x20];
5861 
5862 	u8         reserved_at_120[0x20];
5863 
5864 	u8         rx_dct_connect[0x20];
5865 
5866 	u8         reserved_at_160[0x20];
5867 
5868 	u8         out_of_buffer[0x20];
5869 
5870 	u8         reserved_at_1a0[0x20];
5871 
5872 	u8         out_of_sequence[0x20];
5873 
5874 	u8         reserved_at_1e0[0x20];
5875 
5876 	u8         duplicate_request[0x20];
5877 
5878 	u8         reserved_at_220[0x20];
5879 
5880 	u8         rnr_nak_retry_err[0x20];
5881 
5882 	u8         reserved_at_260[0x20];
5883 
5884 	u8         packet_seq_err[0x20];
5885 
5886 	u8         reserved_at_2a0[0x20];
5887 
5888 	u8         implied_nak_seq_err[0x20];
5889 
5890 	u8         reserved_at_2e0[0x20];
5891 
5892 	u8         local_ack_timeout_err[0x20];
5893 
5894 	u8         reserved_at_320[0x60];
5895 
5896 	u8         req_rnr_retries_exceeded[0x20];
5897 
5898 	u8         reserved_at_3a0[0x20];
5899 
5900 	u8         resp_local_length_error[0x20];
5901 
5902 	u8         req_local_length_error[0x20];
5903 
5904 	u8         resp_local_qp_error[0x20];
5905 
5906 	u8         local_operation_error[0x20];
5907 
5908 	u8         resp_local_protection[0x20];
5909 
5910 	u8         req_local_protection[0x20];
5911 
5912 	u8         resp_cqe_error[0x20];
5913 
5914 	u8         req_cqe_error[0x20];
5915 
5916 	u8         req_mw_binding[0x20];
5917 
5918 	u8         req_bad_response[0x20];
5919 
5920 	u8         req_remote_invalid_request[0x20];
5921 
5922 	u8         resp_remote_invalid_request[0x20];
5923 
5924 	u8         req_remote_access_errors[0x20];
5925 
5926 	u8	   resp_remote_access_errors[0x20];
5927 
5928 	u8         req_remote_operation_errors[0x20];
5929 
5930 	u8         req_transport_retries_exceeded[0x20];
5931 
5932 	u8         cq_overflow[0x20];
5933 
5934 	u8         resp_cqe_flush_error[0x20];
5935 
5936 	u8         req_cqe_flush_error[0x20];
5937 
5938 	u8         reserved_at_620[0x20];
5939 
5940 	u8         roce_adp_retrans[0x20];
5941 
5942 	u8         roce_adp_retrans_to[0x20];
5943 
5944 	u8         roce_slow_restart[0x20];
5945 
5946 	u8         roce_slow_restart_cnps[0x20];
5947 
5948 	u8         roce_slow_restart_trans[0x20];
5949 
5950 	u8         reserved_at_6e0[0x120];
5951 };
5952 
5953 struct mlx5_ifc_query_q_counter_in_bits {
5954 	u8         opcode[0x10];
5955 	u8         reserved_at_10[0x10];
5956 
5957 	u8         reserved_at_20[0x10];
5958 	u8         op_mod[0x10];
5959 
5960 	u8         other_vport[0x1];
5961 	u8         reserved_at_41[0xf];
5962 	u8         vport_number[0x10];
5963 
5964 	u8         reserved_at_60[0x60];
5965 
5966 	u8         clear[0x1];
5967 	u8         aggregate[0x1];
5968 	u8         reserved_at_c2[0x1e];
5969 
5970 	u8         reserved_at_e0[0x18];
5971 	u8         counter_set_id[0x8];
5972 };
5973 
5974 struct mlx5_ifc_query_pages_out_bits {
5975 	u8         status[0x8];
5976 	u8         reserved_at_8[0x18];
5977 
5978 	u8         syndrome[0x20];
5979 
5980 	u8         embedded_cpu_function[0x1];
5981 	u8         reserved_at_41[0xf];
5982 	u8         function_id[0x10];
5983 
5984 	u8         num_pages[0x20];
5985 };
5986 
5987 enum {
5988 	MLX5_QUERY_PAGES_IN_OP_MOD_BOOT_PAGES     = 0x1,
5989 	MLX5_QUERY_PAGES_IN_OP_MOD_INIT_PAGES     = 0x2,
5990 	MLX5_QUERY_PAGES_IN_OP_MOD_REGULAR_PAGES  = 0x3,
5991 };
5992 
5993 struct mlx5_ifc_query_pages_in_bits {
5994 	u8         opcode[0x10];
5995 	u8         reserved_at_10[0x10];
5996 
5997 	u8         reserved_at_20[0x10];
5998 	u8         op_mod[0x10];
5999 
6000 	u8         embedded_cpu_function[0x1];
6001 	u8         reserved_at_41[0xf];
6002 	u8         function_id[0x10];
6003 
6004 	u8         reserved_at_60[0x20];
6005 };
6006 
6007 struct mlx5_ifc_query_nic_vport_context_out_bits {
6008 	u8         status[0x8];
6009 	u8         reserved_at_8[0x18];
6010 
6011 	u8         syndrome[0x20];
6012 
6013 	u8         reserved_at_40[0x40];
6014 
6015 	struct mlx5_ifc_nic_vport_context_bits nic_vport_context;
6016 };
6017 
6018 struct mlx5_ifc_query_nic_vport_context_in_bits {
6019 	u8         opcode[0x10];
6020 	u8         reserved_at_10[0x10];
6021 
6022 	u8         reserved_at_20[0x10];
6023 	u8         op_mod[0x10];
6024 
6025 	u8         other_vport[0x1];
6026 	u8         reserved_at_41[0xf];
6027 	u8         vport_number[0x10];
6028 
6029 	u8         reserved_at_60[0x5];
6030 	u8         allowed_list_type[0x3];
6031 	u8         reserved_at_68[0x18];
6032 };
6033 
6034 struct mlx5_ifc_query_mkey_out_bits {
6035 	u8         status[0x8];
6036 	u8         reserved_at_8[0x18];
6037 
6038 	u8         syndrome[0x20];
6039 
6040 	u8         reserved_at_40[0x40];
6041 
6042 	struct mlx5_ifc_mkc_bits memory_key_mkey_entry;
6043 
6044 	u8         reserved_at_280[0x600];
6045 
6046 	u8         bsf0_klm0_pas_mtt0_1[16][0x8];
6047 
6048 	u8         bsf1_klm1_pas_mtt2_3[16][0x8];
6049 };
6050 
6051 struct mlx5_ifc_query_mkey_in_bits {
6052 	u8         opcode[0x10];
6053 	u8         reserved_at_10[0x10];
6054 
6055 	u8         reserved_at_20[0x10];
6056 	u8         op_mod[0x10];
6057 
6058 	u8         reserved_at_40[0x8];
6059 	u8         mkey_index[0x18];
6060 
6061 	u8         pg_access[0x1];
6062 	u8         reserved_at_61[0x1f];
6063 };
6064 
6065 struct mlx5_ifc_query_mad_demux_out_bits {
6066 	u8         status[0x8];
6067 	u8         reserved_at_8[0x18];
6068 
6069 	u8         syndrome[0x20];
6070 
6071 	u8         reserved_at_40[0x40];
6072 
6073 	u8         mad_dumux_parameters_block[0x20];
6074 };
6075 
6076 struct mlx5_ifc_query_mad_demux_in_bits {
6077 	u8         opcode[0x10];
6078 	u8         reserved_at_10[0x10];
6079 
6080 	u8         reserved_at_20[0x10];
6081 	u8         op_mod[0x10];
6082 
6083 	u8         reserved_at_40[0x40];
6084 };
6085 
6086 struct mlx5_ifc_query_l2_table_entry_out_bits {
6087 	u8         status[0x8];
6088 	u8         reserved_at_8[0x18];
6089 
6090 	u8         syndrome[0x20];
6091 
6092 	u8         reserved_at_40[0xa0];
6093 
6094 	u8         reserved_at_e0[0x13];
6095 	u8         vlan_valid[0x1];
6096 	u8         vlan[0xc];
6097 
6098 	struct mlx5_ifc_mac_address_layout_bits mac_address;
6099 
6100 	u8         reserved_at_140[0xc0];
6101 };
6102 
6103 struct mlx5_ifc_query_l2_table_entry_in_bits {
6104 	u8         opcode[0x10];
6105 	u8         reserved_at_10[0x10];
6106 
6107 	u8         reserved_at_20[0x10];
6108 	u8         op_mod[0x10];
6109 
6110 	u8         reserved_at_40[0x60];
6111 
6112 	u8         reserved_at_a0[0x8];
6113 	u8         table_index[0x18];
6114 
6115 	u8         reserved_at_c0[0x140];
6116 };
6117 
6118 struct mlx5_ifc_query_issi_out_bits {
6119 	u8         status[0x8];
6120 	u8         reserved_at_8[0x18];
6121 
6122 	u8         syndrome[0x20];
6123 
6124 	u8         reserved_at_40[0x10];
6125 	u8         current_issi[0x10];
6126 
6127 	u8         reserved_at_60[0xa0];
6128 
6129 	u8         reserved_at_100[76][0x8];
6130 	u8         supported_issi_dw0[0x20];
6131 };
6132 
6133 struct mlx5_ifc_query_issi_in_bits {
6134 	u8         opcode[0x10];
6135 	u8         reserved_at_10[0x10];
6136 
6137 	u8         reserved_at_20[0x10];
6138 	u8         op_mod[0x10];
6139 
6140 	u8         reserved_at_40[0x40];
6141 };
6142 
6143 struct mlx5_ifc_set_driver_version_out_bits {
6144 	u8         status[0x8];
6145 	u8         reserved_0[0x18];
6146 
6147 	u8         syndrome[0x20];
6148 	u8         reserved_1[0x40];
6149 };
6150 
6151 struct mlx5_ifc_set_driver_version_in_bits {
6152 	u8         opcode[0x10];
6153 	u8         reserved_0[0x10];
6154 
6155 	u8         reserved_1[0x10];
6156 	u8         op_mod[0x10];
6157 
6158 	u8         reserved_2[0x40];
6159 	u8         driver_version[64][0x8];
6160 };
6161 
6162 struct mlx5_ifc_query_hca_vport_pkey_out_bits {
6163 	u8         status[0x8];
6164 	u8         reserved_at_8[0x18];
6165 
6166 	u8         syndrome[0x20];
6167 
6168 	u8         reserved_at_40[0x40];
6169 
6170 	struct mlx5_ifc_pkey_bits pkey[];
6171 };
6172 
6173 struct mlx5_ifc_query_hca_vport_pkey_in_bits {
6174 	u8         opcode[0x10];
6175 	u8         reserved_at_10[0x10];
6176 
6177 	u8         reserved_at_20[0x10];
6178 	u8         op_mod[0x10];
6179 
6180 	u8         other_vport[0x1];
6181 	u8         reserved_at_41[0xb];
6182 	u8         port_num[0x4];
6183 	u8         vport_number[0x10];
6184 
6185 	u8         reserved_at_60[0x10];
6186 	u8         pkey_index[0x10];
6187 };
6188 
6189 enum {
6190 	MLX5_HCA_VPORT_SEL_PORT_GUID	= 1 << 0,
6191 	MLX5_HCA_VPORT_SEL_NODE_GUID	= 1 << 1,
6192 	MLX5_HCA_VPORT_SEL_STATE_POLICY	= 1 << 2,
6193 };
6194 
6195 struct mlx5_ifc_query_hca_vport_gid_out_bits {
6196 	u8         status[0x8];
6197 	u8         reserved_at_8[0x18];
6198 
6199 	u8         syndrome[0x20];
6200 
6201 	u8         reserved_at_40[0x20];
6202 
6203 	u8         gids_num[0x10];
6204 	u8         reserved_at_70[0x10];
6205 
6206 	struct mlx5_ifc_array128_auto_bits gid[];
6207 };
6208 
6209 struct mlx5_ifc_query_hca_vport_gid_in_bits {
6210 	u8         opcode[0x10];
6211 	u8         reserved_at_10[0x10];
6212 
6213 	u8         reserved_at_20[0x10];
6214 	u8         op_mod[0x10];
6215 
6216 	u8         other_vport[0x1];
6217 	u8         reserved_at_41[0xb];
6218 	u8         port_num[0x4];
6219 	u8         vport_number[0x10];
6220 
6221 	u8         reserved_at_60[0x10];
6222 	u8         gid_index[0x10];
6223 };
6224 
6225 struct mlx5_ifc_query_hca_vport_context_out_bits {
6226 	u8         status[0x8];
6227 	u8         reserved_at_8[0x18];
6228 
6229 	u8         syndrome[0x20];
6230 
6231 	u8         reserved_at_40[0x40];
6232 
6233 	struct mlx5_ifc_hca_vport_context_bits hca_vport_context;
6234 };
6235 
6236 struct mlx5_ifc_query_hca_vport_context_in_bits {
6237 	u8         opcode[0x10];
6238 	u8         reserved_at_10[0x10];
6239 
6240 	u8         reserved_at_20[0x10];
6241 	u8         op_mod[0x10];
6242 
6243 	u8         other_vport[0x1];
6244 	u8         reserved_at_41[0xb];
6245 	u8         port_num[0x4];
6246 	u8         vport_number[0x10];
6247 
6248 	u8         reserved_at_60[0x20];
6249 };
6250 
6251 struct mlx5_ifc_query_hca_cap_out_bits {
6252 	u8         status[0x8];
6253 	u8         reserved_at_8[0x18];
6254 
6255 	u8         syndrome[0x20];
6256 
6257 	u8         reserved_at_40[0x40];
6258 
6259 	union mlx5_ifc_hca_cap_union_bits capability;
6260 };
6261 
6262 struct mlx5_ifc_query_hca_cap_in_bits {
6263 	u8         opcode[0x10];
6264 	u8         reserved_at_10[0x10];
6265 
6266 	u8         reserved_at_20[0x10];
6267 	u8         op_mod[0x10];
6268 
6269 	u8         other_function[0x1];
6270 	u8         ec_vf_function[0x1];
6271 	u8         reserved_at_42[0xe];
6272 	u8         function_id[0x10];
6273 
6274 	u8         reserved_at_60[0x20];
6275 };
6276 
6277 struct mlx5_ifc_other_hca_cap_bits {
6278 	u8         roce[0x1];
6279 	u8         reserved_at_1[0x27f];
6280 };
6281 
6282 struct mlx5_ifc_query_other_hca_cap_out_bits {
6283 	u8         status[0x8];
6284 	u8         reserved_at_8[0x18];
6285 
6286 	u8         syndrome[0x20];
6287 
6288 	u8         reserved_at_40[0x40];
6289 
6290 	struct     mlx5_ifc_other_hca_cap_bits other_capability;
6291 };
6292 
6293 struct mlx5_ifc_query_other_hca_cap_in_bits {
6294 	u8         opcode[0x10];
6295 	u8         reserved_at_10[0x10];
6296 
6297 	u8         reserved_at_20[0x10];
6298 	u8         op_mod[0x10];
6299 
6300 	u8         reserved_at_40[0x10];
6301 	u8         function_id[0x10];
6302 
6303 	u8         reserved_at_60[0x20];
6304 };
6305 
6306 struct mlx5_ifc_modify_other_hca_cap_out_bits {
6307 	u8         status[0x8];
6308 	u8         reserved_at_8[0x18];
6309 
6310 	u8         syndrome[0x20];
6311 
6312 	u8         reserved_at_40[0x40];
6313 };
6314 
6315 struct mlx5_ifc_modify_other_hca_cap_in_bits {
6316 	u8         opcode[0x10];
6317 	u8         reserved_at_10[0x10];
6318 
6319 	u8         reserved_at_20[0x10];
6320 	u8         op_mod[0x10];
6321 
6322 	u8         reserved_at_40[0x10];
6323 	u8         function_id[0x10];
6324 	u8         field_select[0x20];
6325 
6326 	struct     mlx5_ifc_other_hca_cap_bits other_capability;
6327 };
6328 
6329 struct mlx5_ifc_flow_table_context_bits {
6330 	u8         reformat_en[0x1];
6331 	u8         decap_en[0x1];
6332 	u8         sw_owner[0x1];
6333 	u8         termination_table[0x1];
6334 	u8         table_miss_action[0x4];
6335 	u8         level[0x8];
6336 	u8         rtc_valid[0x1];
6337 	u8         reserved_at_11[0x7];
6338 	u8         log_size[0x8];
6339 
6340 	u8         reserved_at_20[0x8];
6341 	u8         table_miss_id[0x18];
6342 
6343 	u8         reserved_at_40[0x8];
6344 	u8         lag_master_next_table_id[0x18];
6345 
6346 	u8         reserved_at_60[0x60];
6347 	union {
6348 		struct {
6349 			u8         sw_owner_icm_root_1[0x40];
6350 
6351 			u8         sw_owner_icm_root_0[0x40];
6352 		} sws;
6353 		struct {
6354 			u8         rtc_id_0[0x20];
6355 
6356 			u8         rtc_id_1[0x20];
6357 
6358 			u8         reserved_at_100[0x40];
6359 
6360 		} hws;
6361 	};
6362 };
6363 
6364 struct mlx5_ifc_query_flow_table_out_bits {
6365 	u8         status[0x8];
6366 	u8         reserved_at_8[0x18];
6367 
6368 	u8         syndrome[0x20];
6369 
6370 	u8         reserved_at_40[0x80];
6371 
6372 	struct mlx5_ifc_flow_table_context_bits flow_table_context;
6373 };
6374 
6375 struct mlx5_ifc_query_flow_table_in_bits {
6376 	u8         opcode[0x10];
6377 	u8         reserved_at_10[0x10];
6378 
6379 	u8         reserved_at_20[0x10];
6380 	u8         op_mod[0x10];
6381 
6382 	u8         reserved_at_40[0x40];
6383 
6384 	u8         table_type[0x8];
6385 	u8         reserved_at_88[0x18];
6386 
6387 	u8         reserved_at_a0[0x8];
6388 	u8         table_id[0x18];
6389 
6390 	u8         reserved_at_c0[0x140];
6391 };
6392 
6393 struct mlx5_ifc_query_fte_out_bits {
6394 	u8         status[0x8];
6395 	u8         reserved_at_8[0x18];
6396 
6397 	u8         syndrome[0x20];
6398 
6399 	u8         reserved_at_40[0x1c0];
6400 
6401 	struct mlx5_ifc_flow_context_bits flow_context;
6402 };
6403 
6404 struct mlx5_ifc_query_fte_in_bits {
6405 	u8         opcode[0x10];
6406 	u8         reserved_at_10[0x10];
6407 
6408 	u8         reserved_at_20[0x10];
6409 	u8         op_mod[0x10];
6410 
6411 	u8         reserved_at_40[0x40];
6412 
6413 	u8         table_type[0x8];
6414 	u8         reserved_at_88[0x18];
6415 
6416 	u8         reserved_at_a0[0x8];
6417 	u8         table_id[0x18];
6418 
6419 	u8         reserved_at_c0[0x40];
6420 
6421 	u8         flow_index[0x20];
6422 
6423 	u8         reserved_at_120[0xe0];
6424 };
6425 
6426 struct mlx5_ifc_match_definer_format_0_bits {
6427 	u8         reserved_at_0[0x100];
6428 
6429 	u8         metadata_reg_c_0[0x20];
6430 
6431 	u8         metadata_reg_c_1[0x20];
6432 
6433 	u8         outer_dmac_47_16[0x20];
6434 
6435 	u8         outer_dmac_15_0[0x10];
6436 	u8         outer_ethertype[0x10];
6437 
6438 	u8         reserved_at_180[0x1];
6439 	u8         sx_sniffer[0x1];
6440 	u8         functional_lb[0x1];
6441 	u8         outer_ip_frag[0x1];
6442 	u8         outer_qp_type[0x2];
6443 	u8         outer_encap_type[0x2];
6444 	u8         port_number[0x2];
6445 	u8         outer_l3_type[0x2];
6446 	u8         outer_l4_type[0x2];
6447 	u8         outer_first_vlan_type[0x2];
6448 	u8         outer_first_vlan_prio[0x3];
6449 	u8         outer_first_vlan_cfi[0x1];
6450 	u8         outer_first_vlan_vid[0xc];
6451 
6452 	u8         outer_l4_type_ext[0x4];
6453 	u8         reserved_at_1a4[0x2];
6454 	u8         outer_ipsec_layer[0x2];
6455 	u8         outer_l2_type[0x2];
6456 	u8         force_lb[0x1];
6457 	u8         outer_l2_ok[0x1];
6458 	u8         outer_l3_ok[0x1];
6459 	u8         outer_l4_ok[0x1];
6460 	u8         outer_second_vlan_type[0x2];
6461 	u8         outer_second_vlan_prio[0x3];
6462 	u8         outer_second_vlan_cfi[0x1];
6463 	u8         outer_second_vlan_vid[0xc];
6464 
6465 	u8         outer_smac_47_16[0x20];
6466 
6467 	u8         outer_smac_15_0[0x10];
6468 	u8         inner_ipv4_checksum_ok[0x1];
6469 	u8         inner_l4_checksum_ok[0x1];
6470 	u8         outer_ipv4_checksum_ok[0x1];
6471 	u8         outer_l4_checksum_ok[0x1];
6472 	u8         inner_l3_ok[0x1];
6473 	u8         inner_l4_ok[0x1];
6474 	u8         outer_l3_ok_duplicate[0x1];
6475 	u8         outer_l4_ok_duplicate[0x1];
6476 	u8         outer_tcp_cwr[0x1];
6477 	u8         outer_tcp_ece[0x1];
6478 	u8         outer_tcp_urg[0x1];
6479 	u8         outer_tcp_ack[0x1];
6480 	u8         outer_tcp_psh[0x1];
6481 	u8         outer_tcp_rst[0x1];
6482 	u8         outer_tcp_syn[0x1];
6483 	u8         outer_tcp_fin[0x1];
6484 };
6485 
6486 struct mlx5_ifc_match_definer_format_22_bits {
6487 	u8         reserved_at_0[0x100];
6488 
6489 	u8         outer_ip_src_addr[0x20];
6490 
6491 	u8         outer_ip_dest_addr[0x20];
6492 
6493 	u8         outer_l4_sport[0x10];
6494 	u8         outer_l4_dport[0x10];
6495 
6496 	u8         reserved_at_160[0x1];
6497 	u8         sx_sniffer[0x1];
6498 	u8         functional_lb[0x1];
6499 	u8         outer_ip_frag[0x1];
6500 	u8         outer_qp_type[0x2];
6501 	u8         outer_encap_type[0x2];
6502 	u8         port_number[0x2];
6503 	u8         outer_l3_type[0x2];
6504 	u8         outer_l4_type[0x2];
6505 	u8         outer_first_vlan_type[0x2];
6506 	u8         outer_first_vlan_prio[0x3];
6507 	u8         outer_first_vlan_cfi[0x1];
6508 	u8         outer_first_vlan_vid[0xc];
6509 
6510 	u8         metadata_reg_c_0[0x20];
6511 
6512 	u8         outer_dmac_47_16[0x20];
6513 
6514 	u8         outer_smac_47_16[0x20];
6515 
6516 	u8         outer_smac_15_0[0x10];
6517 	u8         outer_dmac_15_0[0x10];
6518 };
6519 
6520 struct mlx5_ifc_match_definer_format_23_bits {
6521 	u8         reserved_at_0[0x100];
6522 
6523 	u8         inner_ip_src_addr[0x20];
6524 
6525 	u8         inner_ip_dest_addr[0x20];
6526 
6527 	u8         inner_l4_sport[0x10];
6528 	u8         inner_l4_dport[0x10];
6529 
6530 	u8         reserved_at_160[0x1];
6531 	u8         sx_sniffer[0x1];
6532 	u8         functional_lb[0x1];
6533 	u8         inner_ip_frag[0x1];
6534 	u8         inner_qp_type[0x2];
6535 	u8         inner_encap_type[0x2];
6536 	u8         port_number[0x2];
6537 	u8         inner_l3_type[0x2];
6538 	u8         inner_l4_type[0x2];
6539 	u8         inner_first_vlan_type[0x2];
6540 	u8         inner_first_vlan_prio[0x3];
6541 	u8         inner_first_vlan_cfi[0x1];
6542 	u8         inner_first_vlan_vid[0xc];
6543 
6544 	u8         tunnel_header_0[0x20];
6545 
6546 	u8         inner_dmac_47_16[0x20];
6547 
6548 	u8         inner_smac_47_16[0x20];
6549 
6550 	u8         inner_smac_15_0[0x10];
6551 	u8         inner_dmac_15_0[0x10];
6552 };
6553 
6554 struct mlx5_ifc_match_definer_format_29_bits {
6555 	u8         reserved_at_0[0xc0];
6556 
6557 	u8         outer_ip_dest_addr[0x80];
6558 
6559 	u8         outer_ip_src_addr[0x80];
6560 
6561 	u8         outer_l4_sport[0x10];
6562 	u8         outer_l4_dport[0x10];
6563 
6564 	u8         reserved_at_1e0[0x20];
6565 };
6566 
6567 struct mlx5_ifc_match_definer_format_30_bits {
6568 	u8         reserved_at_0[0xa0];
6569 
6570 	u8         outer_ip_dest_addr[0x80];
6571 
6572 	u8         outer_ip_src_addr[0x80];
6573 
6574 	u8         outer_dmac_47_16[0x20];
6575 
6576 	u8         outer_smac_47_16[0x20];
6577 
6578 	u8         outer_smac_15_0[0x10];
6579 	u8         outer_dmac_15_0[0x10];
6580 };
6581 
6582 struct mlx5_ifc_match_definer_format_31_bits {
6583 	u8         reserved_at_0[0xc0];
6584 
6585 	u8         inner_ip_dest_addr[0x80];
6586 
6587 	u8         inner_ip_src_addr[0x80];
6588 
6589 	u8         inner_l4_sport[0x10];
6590 	u8         inner_l4_dport[0x10];
6591 
6592 	u8         reserved_at_1e0[0x20];
6593 };
6594 
6595 struct mlx5_ifc_match_definer_format_32_bits {
6596 	u8         reserved_at_0[0xa0];
6597 
6598 	u8         inner_ip_dest_addr[0x80];
6599 
6600 	u8         inner_ip_src_addr[0x80];
6601 
6602 	u8         inner_dmac_47_16[0x20];
6603 
6604 	u8         inner_smac_47_16[0x20];
6605 
6606 	u8         inner_smac_15_0[0x10];
6607 	u8         inner_dmac_15_0[0x10];
6608 };
6609 
6610 enum {
6611 	MLX5_IFC_DEFINER_FORMAT_ID_SELECT = 61,
6612 };
6613 
6614 #define MLX5_IFC_DEFINER_FORMAT_OFFSET_UNUSED 0x0
6615 #define MLX5_IFC_DEFINER_FORMAT_OFFSET_OUTER_ETH_PKT_LEN 0x48
6616 #define MLX5_IFC_DEFINER_DW_SELECTORS_NUM 9
6617 #define MLX5_IFC_DEFINER_BYTE_SELECTORS_NUM 8
6618 
6619 struct mlx5_ifc_match_definer_match_mask_bits {
6620 	u8         reserved_at_1c0[5][0x20];
6621 	u8         match_dw_8[0x20];
6622 	u8         match_dw_7[0x20];
6623 	u8         match_dw_6[0x20];
6624 	u8         match_dw_5[0x20];
6625 	u8         match_dw_4[0x20];
6626 	u8         match_dw_3[0x20];
6627 	u8         match_dw_2[0x20];
6628 	u8         match_dw_1[0x20];
6629 	u8         match_dw_0[0x20];
6630 
6631 	u8         match_byte_7[0x8];
6632 	u8         match_byte_6[0x8];
6633 	u8         match_byte_5[0x8];
6634 	u8         match_byte_4[0x8];
6635 
6636 	u8         match_byte_3[0x8];
6637 	u8         match_byte_2[0x8];
6638 	u8         match_byte_1[0x8];
6639 	u8         match_byte_0[0x8];
6640 };
6641 
6642 struct mlx5_ifc_match_definer_bits {
6643 	u8         modify_field_select[0x40];
6644 
6645 	u8         reserved_at_40[0x40];
6646 
6647 	u8         reserved_at_80[0x10];
6648 	u8         format_id[0x10];
6649 
6650 	u8         reserved_at_a0[0x60];
6651 
6652 	u8         format_select_dw3[0x8];
6653 	u8         format_select_dw2[0x8];
6654 	u8         format_select_dw1[0x8];
6655 	u8         format_select_dw0[0x8];
6656 
6657 	u8         format_select_dw7[0x8];
6658 	u8         format_select_dw6[0x8];
6659 	u8         format_select_dw5[0x8];
6660 	u8         format_select_dw4[0x8];
6661 
6662 	u8         reserved_at_100[0x18];
6663 	u8         format_select_dw8[0x8];
6664 
6665 	u8         reserved_at_120[0x20];
6666 
6667 	u8         format_select_byte3[0x8];
6668 	u8         format_select_byte2[0x8];
6669 	u8         format_select_byte1[0x8];
6670 	u8         format_select_byte0[0x8];
6671 
6672 	u8         format_select_byte7[0x8];
6673 	u8         format_select_byte6[0x8];
6674 	u8         format_select_byte5[0x8];
6675 	u8         format_select_byte4[0x8];
6676 
6677 	u8         reserved_at_180[0x40];
6678 
6679 	union {
6680 		struct {
6681 			u8         match_mask[16][0x20];
6682 		};
6683 		struct mlx5_ifc_match_definer_match_mask_bits match_mask_format;
6684 	};
6685 };
6686 
6687 struct mlx5_ifc_general_obj_create_param_bits {
6688 	u8         alias_object[0x1];
6689 	u8         reserved_at_1[0x2];
6690 	u8         log_obj_range[0x5];
6691 	u8         reserved_at_8[0x18];
6692 };
6693 
6694 struct mlx5_ifc_general_obj_query_param_bits {
6695 	u8         alias_object[0x1];
6696 	u8         obj_offset[0x1f];
6697 };
6698 
6699 struct mlx5_ifc_general_obj_in_cmd_hdr_bits {
6700 	u8         opcode[0x10];
6701 	u8         uid[0x10];
6702 
6703 	u8         vhca_tunnel_id[0x10];
6704 	u8         obj_type[0x10];
6705 
6706 	u8         obj_id[0x20];
6707 
6708 	union {
6709 		struct mlx5_ifc_general_obj_create_param_bits create;
6710 		struct mlx5_ifc_general_obj_query_param_bits query;
6711 	} op_param;
6712 };
6713 
6714 struct mlx5_ifc_general_obj_out_cmd_hdr_bits {
6715 	u8         status[0x8];
6716 	u8         reserved_at_8[0x18];
6717 
6718 	u8         syndrome[0x20];
6719 
6720 	u8         obj_id[0x20];
6721 
6722 	u8         reserved_at_60[0x20];
6723 };
6724 
6725 struct mlx5_ifc_allow_other_vhca_access_in_bits {
6726 	u8 opcode[0x10];
6727 	u8 uid[0x10];
6728 	u8 reserved_at_20[0x10];
6729 	u8 op_mod[0x10];
6730 	u8 reserved_at_40[0x50];
6731 	u8 object_type_to_be_accessed[0x10];
6732 	u8 object_id_to_be_accessed[0x20];
6733 	u8 reserved_at_c0[0x40];
6734 	union {
6735 		u8 access_key_raw[0x100];
6736 		u8 access_key[8][0x20];
6737 	};
6738 };
6739 
6740 struct mlx5_ifc_allow_other_vhca_access_out_bits {
6741 	u8 status[0x8];
6742 	u8 reserved_at_8[0x18];
6743 	u8 syndrome[0x20];
6744 	u8 reserved_at_40[0x40];
6745 };
6746 
6747 struct mlx5_ifc_modify_header_arg_bits {
6748 	u8         reserved_at_0[0x80];
6749 
6750 	u8         reserved_at_80[0x8];
6751 	u8         access_pd[0x18];
6752 };
6753 
6754 struct mlx5_ifc_create_modify_header_arg_in_bits {
6755 	struct mlx5_ifc_general_obj_in_cmd_hdr_bits hdr;
6756 	struct mlx5_ifc_modify_header_arg_bits arg;
6757 };
6758 
6759 struct mlx5_ifc_create_match_definer_in_bits {
6760 	struct mlx5_ifc_general_obj_in_cmd_hdr_bits general_obj_in_cmd_hdr;
6761 
6762 	struct mlx5_ifc_match_definer_bits obj_context;
6763 };
6764 
6765 struct mlx5_ifc_create_match_definer_out_bits {
6766 	struct mlx5_ifc_general_obj_out_cmd_hdr_bits general_obj_out_cmd_hdr;
6767 };
6768 
6769 struct mlx5_ifc_alias_context_bits {
6770 	u8 vhca_id_to_be_accessed[0x10];
6771 	u8 reserved_at_10[0xd];
6772 	u8 status[0x3];
6773 	u8 object_id_to_be_accessed[0x20];
6774 	u8 reserved_at_40[0x40];
6775 	union {
6776 		u8 access_key_raw[0x100];
6777 		u8 access_key[8][0x20];
6778 	};
6779 	u8 metadata[0x80];
6780 };
6781 
6782 struct mlx5_ifc_create_alias_obj_in_bits {
6783 	struct mlx5_ifc_general_obj_in_cmd_hdr_bits hdr;
6784 	struct mlx5_ifc_alias_context_bits alias_ctx;
6785 };
6786 
6787 enum {
6788 	MLX5_QUERY_FLOW_GROUP_OUT_MATCH_CRITERIA_ENABLE_OUTER_HEADERS    = 0x0,
6789 	MLX5_QUERY_FLOW_GROUP_OUT_MATCH_CRITERIA_ENABLE_MISC_PARAMETERS  = 0x1,
6790 	MLX5_QUERY_FLOW_GROUP_OUT_MATCH_CRITERIA_ENABLE_INNER_HEADERS    = 0x2,
6791 	MLX5_QUERY_FLOW_GROUP_IN_MATCH_CRITERIA_ENABLE_MISC_PARAMETERS_2 = 0x3,
6792 	MLX5_QUERY_FLOW_GROUP_IN_MATCH_CRITERIA_ENABLE_MISC_PARAMETERS_3 = 0x4,
6793 	MLX5_QUERY_FLOW_GROUP_IN_MATCH_CRITERIA_ENABLE_MISC_PARAMETERS_4 = 0x5,
6794 	MLX5_QUERY_FLOW_GROUP_IN_MATCH_CRITERIA_ENABLE_MISC_PARAMETERS_5 = 0x6,
6795 };
6796 
6797 struct mlx5_ifc_query_flow_group_out_bits {
6798 	u8         status[0x8];
6799 	u8         reserved_at_8[0x18];
6800 
6801 	u8         syndrome[0x20];
6802 
6803 	u8         reserved_at_40[0xa0];
6804 
6805 	u8         start_flow_index[0x20];
6806 
6807 	u8         reserved_at_100[0x20];
6808 
6809 	u8         end_flow_index[0x20];
6810 
6811 	u8         reserved_at_140[0xa0];
6812 
6813 	u8         reserved_at_1e0[0x18];
6814 	u8         match_criteria_enable[0x8];
6815 
6816 	struct mlx5_ifc_fte_match_param_bits match_criteria;
6817 
6818 	u8         reserved_at_1200[0xe00];
6819 };
6820 
6821 struct mlx5_ifc_query_flow_group_in_bits {
6822 	u8         opcode[0x10];
6823 	u8         reserved_at_10[0x10];
6824 
6825 	u8         reserved_at_20[0x10];
6826 	u8         op_mod[0x10];
6827 
6828 	u8         reserved_at_40[0x40];
6829 
6830 	u8         table_type[0x8];
6831 	u8         reserved_at_88[0x18];
6832 
6833 	u8         reserved_at_a0[0x8];
6834 	u8         table_id[0x18];
6835 
6836 	u8         group_id[0x20];
6837 
6838 	u8         reserved_at_e0[0x120];
6839 };
6840 
6841 struct mlx5_ifc_query_flow_counter_out_bits {
6842 	u8         status[0x8];
6843 	u8         reserved_at_8[0x18];
6844 
6845 	u8         syndrome[0x20];
6846 
6847 	u8         reserved_at_40[0x40];
6848 
6849 	struct mlx5_ifc_traffic_counter_bits flow_statistics[];
6850 };
6851 
6852 struct mlx5_ifc_query_flow_counter_in_bits {
6853 	u8         opcode[0x10];
6854 	u8         reserved_at_10[0x10];
6855 
6856 	u8         reserved_at_20[0x10];
6857 	u8         op_mod[0x10];
6858 
6859 	u8         reserved_at_40[0x80];
6860 
6861 	u8         clear[0x1];
6862 	u8         reserved_at_c1[0xf];
6863 	u8         num_of_counters[0x10];
6864 
6865 	u8         flow_counter_id[0x20];
6866 };
6867 
6868 struct mlx5_ifc_query_esw_vport_context_out_bits {
6869 	u8         status[0x8];
6870 	u8         reserved_at_8[0x18];
6871 
6872 	u8         syndrome[0x20];
6873 
6874 	u8         reserved_at_40[0x40];
6875 
6876 	struct mlx5_ifc_esw_vport_context_bits esw_vport_context;
6877 };
6878 
6879 struct mlx5_ifc_query_esw_vport_context_in_bits {
6880 	u8         opcode[0x10];
6881 	u8         reserved_at_10[0x10];
6882 
6883 	u8         reserved_at_20[0x10];
6884 	u8         op_mod[0x10];
6885 
6886 	u8         other_vport[0x1];
6887 	u8         reserved_at_41[0xf];
6888 	u8         vport_number[0x10];
6889 
6890 	u8         reserved_at_60[0x20];
6891 };
6892 
6893 struct mlx5_ifc_modify_esw_vport_context_out_bits {
6894 	u8         status[0x8];
6895 	u8         reserved_at_8[0x18];
6896 
6897 	u8         syndrome[0x20];
6898 
6899 	u8         reserved_at_40[0x40];
6900 };
6901 
6902 struct mlx5_ifc_esw_vport_context_fields_select_bits {
6903 	u8         reserved_at_0[0x1b];
6904 	u8         fdb_to_vport_reg_c_id[0x1];
6905 	u8         vport_cvlan_insert[0x1];
6906 	u8         vport_svlan_insert[0x1];
6907 	u8         vport_cvlan_strip[0x1];
6908 	u8         vport_svlan_strip[0x1];
6909 };
6910 
6911 struct mlx5_ifc_modify_esw_vport_context_in_bits {
6912 	u8         opcode[0x10];
6913 	u8         reserved_at_10[0x10];
6914 
6915 	u8         reserved_at_20[0x10];
6916 	u8         op_mod[0x10];
6917 
6918 	u8         other_vport[0x1];
6919 	u8         reserved_at_41[0xf];
6920 	u8         vport_number[0x10];
6921 
6922 	struct mlx5_ifc_esw_vport_context_fields_select_bits field_select;
6923 
6924 	struct mlx5_ifc_esw_vport_context_bits esw_vport_context;
6925 };
6926 
6927 struct mlx5_ifc_query_eq_out_bits {
6928 	u8         status[0x8];
6929 	u8         reserved_at_8[0x18];
6930 
6931 	u8         syndrome[0x20];
6932 
6933 	u8         reserved_at_40[0x40];
6934 
6935 	struct mlx5_ifc_eqc_bits eq_context_entry;
6936 
6937 	u8         reserved_at_280[0x40];
6938 
6939 	u8         event_bitmask[0x40];
6940 
6941 	u8         reserved_at_300[0x580];
6942 
6943 	u8         pas[][0x40];
6944 };
6945 
6946 struct mlx5_ifc_query_eq_in_bits {
6947 	u8         opcode[0x10];
6948 	u8         reserved_at_10[0x10];
6949 
6950 	u8         reserved_at_20[0x10];
6951 	u8         op_mod[0x10];
6952 
6953 	u8         reserved_at_40[0x18];
6954 	u8         eq_number[0x8];
6955 
6956 	u8         reserved_at_60[0x20];
6957 };
6958 
6959 struct mlx5_ifc_packet_reformat_context_in_bits {
6960 	u8         reformat_type[0x8];
6961 	u8         reserved_at_8[0x4];
6962 	u8         reformat_param_0[0x4];
6963 	u8         reserved_at_10[0x6];
6964 	u8         reformat_data_size[0xa];
6965 
6966 	u8         reformat_param_1[0x8];
6967 	u8         reserved_at_28[0x8];
6968 	u8         reformat_data[2][0x8];
6969 
6970 	u8         more_reformat_data[][0x8];
6971 };
6972 
6973 struct mlx5_ifc_query_packet_reformat_context_out_bits {
6974 	u8         status[0x8];
6975 	u8         reserved_at_8[0x18];
6976 
6977 	u8         syndrome[0x20];
6978 
6979 	u8         reserved_at_40[0xa0];
6980 
6981 	struct mlx5_ifc_packet_reformat_context_in_bits packet_reformat_context[];
6982 };
6983 
6984 struct mlx5_ifc_query_packet_reformat_context_in_bits {
6985 	u8         opcode[0x10];
6986 	u8         reserved_at_10[0x10];
6987 
6988 	u8         reserved_at_20[0x10];
6989 	u8         op_mod[0x10];
6990 
6991 	u8         packet_reformat_id[0x20];
6992 
6993 	u8         reserved_at_60[0xa0];
6994 };
6995 
6996 struct mlx5_ifc_alloc_packet_reformat_context_out_bits {
6997 	u8         status[0x8];
6998 	u8         reserved_at_8[0x18];
6999 
7000 	u8         syndrome[0x20];
7001 
7002 	u8         packet_reformat_id[0x20];
7003 
7004 	u8         reserved_at_60[0x20];
7005 };
7006 
7007 enum {
7008 	MLX5_REFORMAT_CONTEXT_ANCHOR_MAC_START = 0x1,
7009 	MLX5_REFORMAT_CONTEXT_ANCHOR_IP_START = 0x7,
7010 	MLX5_REFORMAT_CONTEXT_ANCHOR_TCP_UDP_START = 0x9,
7011 };
7012 
7013 enum mlx5_reformat_ctx_type {
7014 	MLX5_REFORMAT_TYPE_L2_TO_VXLAN = 0x0,
7015 	MLX5_REFORMAT_TYPE_L2_TO_NVGRE = 0x1,
7016 	MLX5_REFORMAT_TYPE_L2_TO_L2_TUNNEL = 0x2,
7017 	MLX5_REFORMAT_TYPE_L3_TUNNEL_TO_L2 = 0x3,
7018 	MLX5_REFORMAT_TYPE_L2_TO_L3_TUNNEL = 0x4,
7019 	MLX5_REFORMAT_TYPE_ADD_ESP_TRANSPORT_OVER_IPV4 = 0x5,
7020 	MLX5_REFORMAT_TYPE_L2_TO_L3_ESP_TUNNEL = 0x6,
7021 	MLX5_REFORMAT_TYPE_ADD_ESP_TRANSPORT_OVER_UDPV4 = 0x7,
7022 	MLX5_REFORMAT_TYPE_DEL_ESP_TRANSPORT = 0x8,
7023 	MLX5_REFORMAT_TYPE_L3_ESP_TUNNEL_TO_L2 = 0x9,
7024 	MLX5_REFORMAT_TYPE_DEL_ESP_TRANSPORT_OVER_UDP = 0xa,
7025 	MLX5_REFORMAT_TYPE_ADD_ESP_TRANSPORT_OVER_IPV6 = 0xb,
7026 	MLX5_REFORMAT_TYPE_ADD_ESP_TRANSPORT_OVER_UDPV6 = 0xc,
7027 	MLX5_REFORMAT_TYPE_INSERT_HDR = 0xf,
7028 	MLX5_REFORMAT_TYPE_REMOVE_HDR = 0x10,
7029 	MLX5_REFORMAT_TYPE_ADD_MACSEC = 0x11,
7030 	MLX5_REFORMAT_TYPE_DEL_MACSEC = 0x12,
7031 };
7032 
7033 struct mlx5_ifc_alloc_packet_reformat_context_in_bits {
7034 	u8         opcode[0x10];
7035 	u8         reserved_at_10[0x10];
7036 
7037 	u8         reserved_at_20[0x10];
7038 	u8         op_mod[0x10];
7039 
7040 	u8         reserved_at_40[0xa0];
7041 
7042 	struct mlx5_ifc_packet_reformat_context_in_bits packet_reformat_context;
7043 };
7044 
7045 struct mlx5_ifc_dealloc_packet_reformat_context_out_bits {
7046 	u8         status[0x8];
7047 	u8         reserved_at_8[0x18];
7048 
7049 	u8         syndrome[0x20];
7050 
7051 	u8         reserved_at_40[0x40];
7052 };
7053 
7054 struct mlx5_ifc_dealloc_packet_reformat_context_in_bits {
7055 	u8         opcode[0x10];
7056 	u8         reserved_at_10[0x10];
7057 
7058 	u8         reserved_20[0x10];
7059 	u8         op_mod[0x10];
7060 
7061 	u8         packet_reformat_id[0x20];
7062 
7063 	u8         reserved_60[0x20];
7064 };
7065 
7066 struct mlx5_ifc_set_action_in_bits {
7067 	u8         action_type[0x4];
7068 	u8         field[0xc];
7069 	u8         reserved_at_10[0x3];
7070 	u8         offset[0x5];
7071 	u8         reserved_at_18[0x3];
7072 	u8         length[0x5];
7073 
7074 	u8         data[0x20];
7075 };
7076 
7077 struct mlx5_ifc_add_action_in_bits {
7078 	u8         action_type[0x4];
7079 	u8         field[0xc];
7080 	u8         reserved_at_10[0x10];
7081 
7082 	u8         data[0x20];
7083 };
7084 
7085 struct mlx5_ifc_copy_action_in_bits {
7086 	u8         action_type[0x4];
7087 	u8         src_field[0xc];
7088 	u8         reserved_at_10[0x3];
7089 	u8         src_offset[0x5];
7090 	u8         reserved_at_18[0x3];
7091 	u8         length[0x5];
7092 
7093 	u8         reserved_at_20[0x4];
7094 	u8         dst_field[0xc];
7095 	u8         reserved_at_30[0x3];
7096 	u8         dst_offset[0x5];
7097 	u8         reserved_at_38[0x8];
7098 };
7099 
7100 union mlx5_ifc_set_add_copy_action_in_auto_bits {
7101 	struct mlx5_ifc_set_action_in_bits  set_action_in;
7102 	struct mlx5_ifc_add_action_in_bits  add_action_in;
7103 	struct mlx5_ifc_copy_action_in_bits copy_action_in;
7104 	u8         reserved_at_0[0x40];
7105 };
7106 
7107 enum {
7108 	MLX5_ACTION_TYPE_SET   = 0x1,
7109 	MLX5_ACTION_TYPE_ADD   = 0x2,
7110 	MLX5_ACTION_TYPE_COPY  = 0x3,
7111 };
7112 
7113 enum {
7114 	MLX5_ACTION_IN_FIELD_OUT_SMAC_47_16    = 0x1,
7115 	MLX5_ACTION_IN_FIELD_OUT_SMAC_15_0     = 0x2,
7116 	MLX5_ACTION_IN_FIELD_OUT_ETHERTYPE     = 0x3,
7117 	MLX5_ACTION_IN_FIELD_OUT_DMAC_47_16    = 0x4,
7118 	MLX5_ACTION_IN_FIELD_OUT_DMAC_15_0     = 0x5,
7119 	MLX5_ACTION_IN_FIELD_OUT_IP_DSCP       = 0x6,
7120 	MLX5_ACTION_IN_FIELD_OUT_TCP_FLAGS     = 0x7,
7121 	MLX5_ACTION_IN_FIELD_OUT_TCP_SPORT     = 0x8,
7122 	MLX5_ACTION_IN_FIELD_OUT_TCP_DPORT     = 0x9,
7123 	MLX5_ACTION_IN_FIELD_OUT_IP_TTL        = 0xa,
7124 	MLX5_ACTION_IN_FIELD_OUT_UDP_SPORT     = 0xb,
7125 	MLX5_ACTION_IN_FIELD_OUT_UDP_DPORT     = 0xc,
7126 	MLX5_ACTION_IN_FIELD_OUT_SIPV6_127_96  = 0xd,
7127 	MLX5_ACTION_IN_FIELD_OUT_SIPV6_95_64   = 0xe,
7128 	MLX5_ACTION_IN_FIELD_OUT_SIPV6_63_32   = 0xf,
7129 	MLX5_ACTION_IN_FIELD_OUT_SIPV6_31_0    = 0x10,
7130 	MLX5_ACTION_IN_FIELD_OUT_DIPV6_127_96  = 0x11,
7131 	MLX5_ACTION_IN_FIELD_OUT_DIPV6_95_64   = 0x12,
7132 	MLX5_ACTION_IN_FIELD_OUT_DIPV6_63_32   = 0x13,
7133 	MLX5_ACTION_IN_FIELD_OUT_DIPV6_31_0    = 0x14,
7134 	MLX5_ACTION_IN_FIELD_OUT_SIPV4         = 0x15,
7135 	MLX5_ACTION_IN_FIELD_OUT_DIPV4         = 0x16,
7136 	MLX5_ACTION_IN_FIELD_OUT_FIRST_VID     = 0x17,
7137 	MLX5_ACTION_IN_FIELD_OUT_IPV6_HOPLIMIT = 0x47,
7138 	MLX5_ACTION_IN_FIELD_METADATA_REG_A    = 0x49,
7139 	MLX5_ACTION_IN_FIELD_METADATA_REG_B    = 0x50,
7140 	MLX5_ACTION_IN_FIELD_METADATA_REG_C_0  = 0x51,
7141 	MLX5_ACTION_IN_FIELD_METADATA_REG_C_1  = 0x52,
7142 	MLX5_ACTION_IN_FIELD_METADATA_REG_C_2  = 0x53,
7143 	MLX5_ACTION_IN_FIELD_METADATA_REG_C_3  = 0x54,
7144 	MLX5_ACTION_IN_FIELD_METADATA_REG_C_4  = 0x55,
7145 	MLX5_ACTION_IN_FIELD_METADATA_REG_C_5  = 0x56,
7146 	MLX5_ACTION_IN_FIELD_METADATA_REG_C_6  = 0x57,
7147 	MLX5_ACTION_IN_FIELD_METADATA_REG_C_7  = 0x58,
7148 	MLX5_ACTION_IN_FIELD_OUT_TCP_SEQ_NUM   = 0x59,
7149 	MLX5_ACTION_IN_FIELD_OUT_TCP_ACK_NUM   = 0x5B,
7150 	MLX5_ACTION_IN_FIELD_IPSEC_SYNDROME    = 0x5D,
7151 	MLX5_ACTION_IN_FIELD_OUT_EMD_47_32     = 0x6F,
7152 	MLX5_ACTION_IN_FIELD_OUT_EMD_31_0      = 0x70,
7153 };
7154 
7155 struct mlx5_ifc_alloc_modify_header_context_out_bits {
7156 	u8         status[0x8];
7157 	u8         reserved_at_8[0x18];
7158 
7159 	u8         syndrome[0x20];
7160 
7161 	u8         modify_header_id[0x20];
7162 
7163 	u8         reserved_at_60[0x20];
7164 };
7165 
7166 struct mlx5_ifc_alloc_modify_header_context_in_bits {
7167 	u8         opcode[0x10];
7168 	u8         reserved_at_10[0x10];
7169 
7170 	u8         reserved_at_20[0x10];
7171 	u8         op_mod[0x10];
7172 
7173 	u8         reserved_at_40[0x20];
7174 
7175 	u8         table_type[0x8];
7176 	u8         reserved_at_68[0x10];
7177 	u8         num_of_actions[0x8];
7178 
7179 	union mlx5_ifc_set_add_copy_action_in_auto_bits actions[];
7180 };
7181 
7182 struct mlx5_ifc_dealloc_modify_header_context_out_bits {
7183 	u8         status[0x8];
7184 	u8         reserved_at_8[0x18];
7185 
7186 	u8         syndrome[0x20];
7187 
7188 	u8         reserved_at_40[0x40];
7189 };
7190 
7191 struct mlx5_ifc_dealloc_modify_header_context_in_bits {
7192 	u8         opcode[0x10];
7193 	u8         reserved_at_10[0x10];
7194 
7195 	u8         reserved_at_20[0x10];
7196 	u8         op_mod[0x10];
7197 
7198 	u8         modify_header_id[0x20];
7199 
7200 	u8         reserved_at_60[0x20];
7201 };
7202 
7203 struct mlx5_ifc_query_modify_header_context_in_bits {
7204 	u8         opcode[0x10];
7205 	u8         uid[0x10];
7206 
7207 	u8         reserved_at_20[0x10];
7208 	u8         op_mod[0x10];
7209 
7210 	u8         modify_header_id[0x20];
7211 
7212 	u8         reserved_at_60[0xa0];
7213 };
7214 
7215 struct mlx5_ifc_query_dct_out_bits {
7216 	u8         status[0x8];
7217 	u8         reserved_at_8[0x18];
7218 
7219 	u8         syndrome[0x20];
7220 
7221 	u8         reserved_at_40[0x40];
7222 
7223 	struct mlx5_ifc_dctc_bits dct_context_entry;
7224 
7225 	u8         reserved_at_280[0x180];
7226 };
7227 
7228 struct mlx5_ifc_query_dct_in_bits {
7229 	u8         opcode[0x10];
7230 	u8         reserved_at_10[0x10];
7231 
7232 	u8         reserved_at_20[0x10];
7233 	u8         op_mod[0x10];
7234 
7235 	u8         reserved_at_40[0x8];
7236 	u8         dctn[0x18];
7237 
7238 	u8         reserved_at_60[0x20];
7239 };
7240 
7241 struct mlx5_ifc_query_cq_out_bits {
7242 	u8         status[0x8];
7243 	u8         reserved_at_8[0x18];
7244 
7245 	u8         syndrome[0x20];
7246 
7247 	u8         reserved_at_40[0x40];
7248 
7249 	struct mlx5_ifc_cqc_bits cq_context;
7250 
7251 	u8         reserved_at_280[0x600];
7252 
7253 	u8         pas[][0x40];
7254 };
7255 
7256 struct mlx5_ifc_query_cq_in_bits {
7257 	u8         opcode[0x10];
7258 	u8         reserved_at_10[0x10];
7259 
7260 	u8         reserved_at_20[0x10];
7261 	u8         op_mod[0x10];
7262 
7263 	u8         reserved_at_40[0x8];
7264 	u8         cqn[0x18];
7265 
7266 	u8         reserved_at_60[0x20];
7267 };
7268 
7269 struct mlx5_ifc_query_cong_status_out_bits {
7270 	u8         status[0x8];
7271 	u8         reserved_at_8[0x18];
7272 
7273 	u8         syndrome[0x20];
7274 
7275 	u8         reserved_at_40[0x20];
7276 
7277 	u8         enable[0x1];
7278 	u8         tag_enable[0x1];
7279 	u8         reserved_at_62[0x1e];
7280 };
7281 
7282 struct mlx5_ifc_query_cong_status_in_bits {
7283 	u8         opcode[0x10];
7284 	u8         reserved_at_10[0x10];
7285 
7286 	u8         reserved_at_20[0x10];
7287 	u8         op_mod[0x10];
7288 
7289 	u8         reserved_at_40[0x18];
7290 	u8         priority[0x4];
7291 	u8         cong_protocol[0x4];
7292 
7293 	u8         reserved_at_60[0x20];
7294 };
7295 
7296 struct mlx5_ifc_query_cong_statistics_out_bits {
7297 	u8         status[0x8];
7298 	u8         reserved_at_8[0x18];
7299 
7300 	u8         syndrome[0x20];
7301 
7302 	u8         reserved_at_40[0x40];
7303 
7304 	u8         rp_cur_flows[0x20];
7305 
7306 	u8         sum_flows[0x20];
7307 
7308 	u8         rp_cnp_ignored_high[0x20];
7309 
7310 	u8         rp_cnp_ignored_low[0x20];
7311 
7312 	u8         rp_cnp_handled_high[0x20];
7313 
7314 	u8         rp_cnp_handled_low[0x20];
7315 
7316 	u8         reserved_at_140[0x100];
7317 
7318 	u8         time_stamp_high[0x20];
7319 
7320 	u8         time_stamp_low[0x20];
7321 
7322 	u8         accumulators_period[0x20];
7323 
7324 	u8         np_ecn_marked_roce_packets_high[0x20];
7325 
7326 	u8         np_ecn_marked_roce_packets_low[0x20];
7327 
7328 	u8         np_cnp_sent_high[0x20];
7329 
7330 	u8         np_cnp_sent_low[0x20];
7331 
7332 	u8         reserved_at_320[0x560];
7333 };
7334 
7335 struct mlx5_ifc_query_cong_statistics_in_bits {
7336 	u8         opcode[0x10];
7337 	u8         reserved_at_10[0x10];
7338 
7339 	u8         reserved_at_20[0x10];
7340 	u8         op_mod[0x10];
7341 
7342 	u8         clear[0x1];
7343 	u8         reserved_at_41[0x1f];
7344 
7345 	u8         reserved_at_60[0x20];
7346 };
7347 
7348 struct mlx5_ifc_query_cong_params_out_bits {
7349 	u8         status[0x8];
7350 	u8         reserved_at_8[0x18];
7351 
7352 	u8         syndrome[0x20];
7353 
7354 	u8         reserved_at_40[0x40];
7355 
7356 	union mlx5_ifc_cong_control_roce_ecn_auto_bits congestion_parameters;
7357 };
7358 
7359 struct mlx5_ifc_query_cong_params_in_bits {
7360 	u8         opcode[0x10];
7361 	u8         reserved_at_10[0x10];
7362 
7363 	u8         reserved_at_20[0x10];
7364 	u8         op_mod[0x10];
7365 
7366 	u8         reserved_at_40[0x1c];
7367 	u8         cong_protocol[0x4];
7368 
7369 	u8         reserved_at_60[0x20];
7370 };
7371 
7372 struct mlx5_ifc_query_adapter_out_bits {
7373 	u8         status[0x8];
7374 	u8         reserved_at_8[0x18];
7375 
7376 	u8         syndrome[0x20];
7377 
7378 	u8         reserved_at_40[0x40];
7379 
7380 	struct mlx5_ifc_query_adapter_param_block_bits query_adapter_struct;
7381 };
7382 
7383 struct mlx5_ifc_query_adapter_in_bits {
7384 	u8         opcode[0x10];
7385 	u8         reserved_at_10[0x10];
7386 
7387 	u8         reserved_at_20[0x10];
7388 	u8         op_mod[0x10];
7389 
7390 	u8         reserved_at_40[0x40];
7391 };
7392 
7393 struct mlx5_ifc_qp_2rst_out_bits {
7394 	u8         status[0x8];
7395 	u8         reserved_at_8[0x18];
7396 
7397 	u8         syndrome[0x20];
7398 
7399 	u8         reserved_at_40[0x40];
7400 };
7401 
7402 struct mlx5_ifc_qp_2rst_in_bits {
7403 	u8         opcode[0x10];
7404 	u8         uid[0x10];
7405 
7406 	u8         reserved_at_20[0x10];
7407 	u8         op_mod[0x10];
7408 
7409 	u8         reserved_at_40[0x8];
7410 	u8         qpn[0x18];
7411 
7412 	u8         reserved_at_60[0x20];
7413 };
7414 
7415 struct mlx5_ifc_qp_2err_out_bits {
7416 	u8         status[0x8];
7417 	u8         reserved_at_8[0x18];
7418 
7419 	u8         syndrome[0x20];
7420 
7421 	u8         reserved_at_40[0x40];
7422 };
7423 
7424 struct mlx5_ifc_qp_2err_in_bits {
7425 	u8         opcode[0x10];
7426 	u8         uid[0x10];
7427 
7428 	u8         reserved_at_20[0x10];
7429 	u8         op_mod[0x10];
7430 
7431 	u8         reserved_at_40[0x8];
7432 	u8         qpn[0x18];
7433 
7434 	u8         reserved_at_60[0x20];
7435 };
7436 
7437 struct mlx5_ifc_trans_page_fault_info_bits {
7438 	u8         error[0x1];
7439 	u8         reserved_at_1[0x4];
7440 	u8         page_fault_type[0x3];
7441 	u8         wq_number[0x18];
7442 
7443 	u8         reserved_at_20[0x8];
7444 	u8         fault_token[0x18];
7445 };
7446 
7447 struct mlx5_ifc_mem_page_fault_info_bits {
7448 	u8          error[0x1];
7449 	u8          reserved_at_1[0xf];
7450 	u8          fault_token_47_32[0x10];
7451 
7452 	u8          fault_token_31_0[0x20];
7453 };
7454 
7455 union mlx5_ifc_page_fault_resume_in_page_fault_info_auto_bits {
7456 	struct mlx5_ifc_trans_page_fault_info_bits trans_page_fault_info;
7457 	struct mlx5_ifc_mem_page_fault_info_bits mem_page_fault_info;
7458 	u8          reserved_at_0[0x40];
7459 };
7460 
7461 struct mlx5_ifc_page_fault_resume_out_bits {
7462 	u8         status[0x8];
7463 	u8         reserved_at_8[0x18];
7464 
7465 	u8         syndrome[0x20];
7466 
7467 	u8         reserved_at_40[0x40];
7468 };
7469 
7470 struct mlx5_ifc_page_fault_resume_in_bits {
7471 	u8         opcode[0x10];
7472 	u8         reserved_at_10[0x10];
7473 
7474 	u8         reserved_at_20[0x10];
7475 	u8         op_mod[0x10];
7476 
7477 	union mlx5_ifc_page_fault_resume_in_page_fault_info_auto_bits
7478 		page_fault_info;
7479 };
7480 
7481 struct mlx5_ifc_nop_out_bits {
7482 	u8         status[0x8];
7483 	u8         reserved_at_8[0x18];
7484 
7485 	u8         syndrome[0x20];
7486 
7487 	u8         reserved_at_40[0x40];
7488 };
7489 
7490 struct mlx5_ifc_nop_in_bits {
7491 	u8         opcode[0x10];
7492 	u8         reserved_at_10[0x10];
7493 
7494 	u8         reserved_at_20[0x10];
7495 	u8         op_mod[0x10];
7496 
7497 	u8         reserved_at_40[0x40];
7498 };
7499 
7500 struct mlx5_ifc_modify_vport_state_out_bits {
7501 	u8         status[0x8];
7502 	u8         reserved_at_8[0x18];
7503 
7504 	u8         syndrome[0x20];
7505 
7506 	u8         reserved_at_40[0x40];
7507 };
7508 
7509 struct mlx5_ifc_modify_vport_state_in_bits {
7510 	u8         opcode[0x10];
7511 	u8         reserved_at_10[0x10];
7512 
7513 	u8         reserved_at_20[0x10];
7514 	u8         op_mod[0x10];
7515 
7516 	u8         other_vport[0x1];
7517 	u8         reserved_at_41[0xf];
7518 	u8         vport_number[0x10];
7519 
7520 	u8         reserved_at_60[0x18];
7521 	u8         admin_state[0x4];
7522 	u8         reserved_at_7c[0x4];
7523 };
7524 
7525 struct mlx5_ifc_modify_tis_out_bits {
7526 	u8         status[0x8];
7527 	u8         reserved_at_8[0x18];
7528 
7529 	u8         syndrome[0x20];
7530 
7531 	u8         reserved_at_40[0x40];
7532 };
7533 
7534 struct mlx5_ifc_modify_tis_bitmask_bits {
7535 	u8         reserved_at_0[0x20];
7536 
7537 	u8         reserved_at_20[0x1d];
7538 	u8         lag_tx_port_affinity[0x1];
7539 	u8         strict_lag_tx_port_affinity[0x1];
7540 	u8         prio[0x1];
7541 };
7542 
7543 struct mlx5_ifc_modify_tis_in_bits {
7544 	u8         opcode[0x10];
7545 	u8         uid[0x10];
7546 
7547 	u8         reserved_at_20[0x10];
7548 	u8         op_mod[0x10];
7549 
7550 	u8         reserved_at_40[0x8];
7551 	u8         tisn[0x18];
7552 
7553 	u8         reserved_at_60[0x20];
7554 
7555 	struct mlx5_ifc_modify_tis_bitmask_bits bitmask;
7556 
7557 	u8         reserved_at_c0[0x40];
7558 
7559 	struct mlx5_ifc_tisc_bits ctx;
7560 };
7561 
7562 struct mlx5_ifc_modify_tir_bitmask_bits {
7563 	u8	   reserved_at_0[0x20];
7564 
7565 	u8         reserved_at_20[0x1b];
7566 	u8         self_lb_en[0x1];
7567 	u8         reserved_at_3c[0x1];
7568 	u8         hash[0x1];
7569 	u8         reserved_at_3e[0x1];
7570 	u8         packet_merge[0x1];
7571 };
7572 
7573 struct mlx5_ifc_modify_tir_out_bits {
7574 	u8         status[0x8];
7575 	u8         reserved_at_8[0x18];
7576 
7577 	u8         syndrome[0x20];
7578 
7579 	u8         reserved_at_40[0x40];
7580 };
7581 
7582 struct mlx5_ifc_modify_tir_in_bits {
7583 	u8         opcode[0x10];
7584 	u8         uid[0x10];
7585 
7586 	u8         reserved_at_20[0x10];
7587 	u8         op_mod[0x10];
7588 
7589 	u8         reserved_at_40[0x8];
7590 	u8         tirn[0x18];
7591 
7592 	u8         reserved_at_60[0x20];
7593 
7594 	struct mlx5_ifc_modify_tir_bitmask_bits bitmask;
7595 
7596 	u8         reserved_at_c0[0x40];
7597 
7598 	struct mlx5_ifc_tirc_bits ctx;
7599 };
7600 
7601 struct mlx5_ifc_modify_sq_out_bits {
7602 	u8         status[0x8];
7603 	u8         reserved_at_8[0x18];
7604 
7605 	u8         syndrome[0x20];
7606 
7607 	u8         reserved_at_40[0x40];
7608 };
7609 
7610 struct mlx5_ifc_modify_sq_in_bits {
7611 	u8         opcode[0x10];
7612 	u8         uid[0x10];
7613 
7614 	u8         reserved_at_20[0x10];
7615 	u8         op_mod[0x10];
7616 
7617 	u8         sq_state[0x4];
7618 	u8         reserved_at_44[0x4];
7619 	u8         sqn[0x18];
7620 
7621 	u8         reserved_at_60[0x20];
7622 
7623 	u8         modify_bitmask[0x40];
7624 
7625 	u8         reserved_at_c0[0x40];
7626 
7627 	struct mlx5_ifc_sqc_bits ctx;
7628 };
7629 
7630 struct mlx5_ifc_modify_scheduling_element_out_bits {
7631 	u8         status[0x8];
7632 	u8         reserved_at_8[0x18];
7633 
7634 	u8         syndrome[0x20];
7635 
7636 	u8         reserved_at_40[0x1c0];
7637 };
7638 
7639 enum {
7640 	MODIFY_SCHEDULING_ELEMENT_IN_MODIFY_BITMASK_BW_SHARE = 0x1,
7641 	MODIFY_SCHEDULING_ELEMENT_IN_MODIFY_BITMASK_MAX_AVERAGE_BW = 0x2,
7642 };
7643 
7644 struct mlx5_ifc_modify_scheduling_element_in_bits {
7645 	u8         opcode[0x10];
7646 	u8         reserved_at_10[0x10];
7647 
7648 	u8         reserved_at_20[0x10];
7649 	u8         op_mod[0x10];
7650 
7651 	u8         scheduling_hierarchy[0x8];
7652 	u8         reserved_at_48[0x18];
7653 
7654 	u8         scheduling_element_id[0x20];
7655 
7656 	u8         reserved_at_80[0x20];
7657 
7658 	u8         modify_bitmask[0x20];
7659 
7660 	u8         reserved_at_c0[0x40];
7661 
7662 	struct mlx5_ifc_scheduling_context_bits scheduling_context;
7663 
7664 	u8         reserved_at_300[0x100];
7665 };
7666 
7667 struct mlx5_ifc_modify_rqt_out_bits {
7668 	u8         status[0x8];
7669 	u8         reserved_at_8[0x18];
7670 
7671 	u8         syndrome[0x20];
7672 
7673 	u8         reserved_at_40[0x40];
7674 };
7675 
7676 struct mlx5_ifc_rqt_bitmask_bits {
7677 	u8	   reserved_at_0[0x20];
7678 
7679 	u8         reserved_at_20[0x1f];
7680 	u8         rqn_list[0x1];
7681 };
7682 
7683 struct mlx5_ifc_modify_rqt_in_bits {
7684 	u8         opcode[0x10];
7685 	u8         uid[0x10];
7686 
7687 	u8         reserved_at_20[0x10];
7688 	u8         op_mod[0x10];
7689 
7690 	u8         reserved_at_40[0x8];
7691 	u8         rqtn[0x18];
7692 
7693 	u8         reserved_at_60[0x20];
7694 
7695 	struct mlx5_ifc_rqt_bitmask_bits bitmask;
7696 
7697 	u8         reserved_at_c0[0x40];
7698 
7699 	struct mlx5_ifc_rqtc_bits ctx;
7700 };
7701 
7702 struct mlx5_ifc_modify_rq_out_bits {
7703 	u8         status[0x8];
7704 	u8         reserved_at_8[0x18];
7705 
7706 	u8         syndrome[0x20];
7707 
7708 	u8         reserved_at_40[0x40];
7709 };
7710 
7711 enum {
7712 	MLX5_MODIFY_RQ_IN_MODIFY_BITMASK_VSD = 1ULL << 1,
7713 	MLX5_MODIFY_RQ_IN_MODIFY_BITMASK_SCATTER_FCS = 1ULL << 2,
7714 	MLX5_MODIFY_RQ_IN_MODIFY_BITMASK_RQ_COUNTER_SET_ID = 1ULL << 3,
7715 };
7716 
7717 struct mlx5_ifc_modify_rq_in_bits {
7718 	u8         opcode[0x10];
7719 	u8         uid[0x10];
7720 
7721 	u8         reserved_at_20[0x10];
7722 	u8         op_mod[0x10];
7723 
7724 	u8         rq_state[0x4];
7725 	u8         reserved_at_44[0x4];
7726 	u8         rqn[0x18];
7727 
7728 	u8         reserved_at_60[0x20];
7729 
7730 	u8         modify_bitmask[0x40];
7731 
7732 	u8         reserved_at_c0[0x40];
7733 
7734 	struct mlx5_ifc_rqc_bits ctx;
7735 };
7736 
7737 struct mlx5_ifc_modify_rmp_out_bits {
7738 	u8         status[0x8];
7739 	u8         reserved_at_8[0x18];
7740 
7741 	u8         syndrome[0x20];
7742 
7743 	u8         reserved_at_40[0x40];
7744 };
7745 
7746 struct mlx5_ifc_rmp_bitmask_bits {
7747 	u8	   reserved_at_0[0x20];
7748 
7749 	u8         reserved_at_20[0x1f];
7750 	u8         lwm[0x1];
7751 };
7752 
7753 struct mlx5_ifc_modify_rmp_in_bits {
7754 	u8         opcode[0x10];
7755 	u8         uid[0x10];
7756 
7757 	u8         reserved_at_20[0x10];
7758 	u8         op_mod[0x10];
7759 
7760 	u8         rmp_state[0x4];
7761 	u8         reserved_at_44[0x4];
7762 	u8         rmpn[0x18];
7763 
7764 	u8         reserved_at_60[0x20];
7765 
7766 	struct mlx5_ifc_rmp_bitmask_bits bitmask;
7767 
7768 	u8         reserved_at_c0[0x40];
7769 
7770 	struct mlx5_ifc_rmpc_bits ctx;
7771 };
7772 
7773 struct mlx5_ifc_modify_nic_vport_context_out_bits {
7774 	u8         status[0x8];
7775 	u8         reserved_at_8[0x18];
7776 
7777 	u8         syndrome[0x20];
7778 
7779 	u8         reserved_at_40[0x40];
7780 };
7781 
7782 struct mlx5_ifc_modify_nic_vport_field_select_bits {
7783 	u8         reserved_at_0[0x12];
7784 	u8	   affiliation[0x1];
7785 	u8	   reserved_at_13[0x1];
7786 	u8         disable_uc_local_lb[0x1];
7787 	u8         disable_mc_local_lb[0x1];
7788 	u8         node_guid[0x1];
7789 	u8         port_guid[0x1];
7790 	u8         min_inline[0x1];
7791 	u8         mtu[0x1];
7792 	u8         change_event[0x1];
7793 	u8         promisc[0x1];
7794 	u8         permanent_address[0x1];
7795 	u8         addresses_list[0x1];
7796 	u8         roce_en[0x1];
7797 	u8         reserved_at_1f[0x1];
7798 };
7799 
7800 struct mlx5_ifc_modify_nic_vport_context_in_bits {
7801 	u8         opcode[0x10];
7802 	u8         reserved_at_10[0x10];
7803 
7804 	u8         reserved_at_20[0x10];
7805 	u8         op_mod[0x10];
7806 
7807 	u8         other_vport[0x1];
7808 	u8         reserved_at_41[0xf];
7809 	u8         vport_number[0x10];
7810 
7811 	struct mlx5_ifc_modify_nic_vport_field_select_bits field_select;
7812 
7813 	u8         reserved_at_80[0x780];
7814 
7815 	struct mlx5_ifc_nic_vport_context_bits nic_vport_context;
7816 };
7817 
7818 struct mlx5_ifc_modify_hca_vport_context_out_bits {
7819 	u8         status[0x8];
7820 	u8         reserved_at_8[0x18];
7821 
7822 	u8         syndrome[0x20];
7823 
7824 	u8         reserved_at_40[0x40];
7825 };
7826 
7827 struct mlx5_ifc_modify_hca_vport_context_in_bits {
7828 	u8         opcode[0x10];
7829 	u8         reserved_at_10[0x10];
7830 
7831 	u8         reserved_at_20[0x10];
7832 	u8         op_mod[0x10];
7833 
7834 	u8         other_vport[0x1];
7835 	u8         reserved_at_41[0xb];
7836 	u8         port_num[0x4];
7837 	u8         vport_number[0x10];
7838 
7839 	u8         reserved_at_60[0x20];
7840 
7841 	struct mlx5_ifc_hca_vport_context_bits hca_vport_context;
7842 };
7843 
7844 struct mlx5_ifc_modify_cq_out_bits {
7845 	u8         status[0x8];
7846 	u8         reserved_at_8[0x18];
7847 
7848 	u8         syndrome[0x20];
7849 
7850 	u8         reserved_at_40[0x40];
7851 };
7852 
7853 enum {
7854 	MLX5_MODIFY_CQ_IN_OP_MOD_MODIFY_CQ  = 0x0,
7855 	MLX5_MODIFY_CQ_IN_OP_MOD_RESIZE_CQ  = 0x1,
7856 };
7857 
7858 struct mlx5_ifc_modify_cq_in_bits {
7859 	u8         opcode[0x10];
7860 	u8         uid[0x10];
7861 
7862 	u8         reserved_at_20[0x10];
7863 	u8         op_mod[0x10];
7864 
7865 	u8         reserved_at_40[0x8];
7866 	u8         cqn[0x18];
7867 
7868 	union mlx5_ifc_modify_field_select_resize_field_select_auto_bits modify_field_select_resize_field_select;
7869 
7870 	struct mlx5_ifc_cqc_bits cq_context;
7871 
7872 	u8         reserved_at_280[0x60];
7873 
7874 	u8         cq_umem_valid[0x1];
7875 	u8         reserved_at_2e1[0x1f];
7876 
7877 	u8         reserved_at_300[0x580];
7878 
7879 	u8         pas[][0x40];
7880 };
7881 
7882 struct mlx5_ifc_modify_cong_status_out_bits {
7883 	u8         status[0x8];
7884 	u8         reserved_at_8[0x18];
7885 
7886 	u8         syndrome[0x20];
7887 
7888 	u8         reserved_at_40[0x40];
7889 };
7890 
7891 struct mlx5_ifc_modify_cong_status_in_bits {
7892 	u8         opcode[0x10];
7893 	u8         reserved_at_10[0x10];
7894 
7895 	u8         reserved_at_20[0x10];
7896 	u8         op_mod[0x10];
7897 
7898 	u8         reserved_at_40[0x18];
7899 	u8         priority[0x4];
7900 	u8         cong_protocol[0x4];
7901 
7902 	u8         enable[0x1];
7903 	u8         tag_enable[0x1];
7904 	u8         reserved_at_62[0x1e];
7905 };
7906 
7907 struct mlx5_ifc_modify_cong_params_out_bits {
7908 	u8         status[0x8];
7909 	u8         reserved_at_8[0x18];
7910 
7911 	u8         syndrome[0x20];
7912 
7913 	u8         reserved_at_40[0x40];
7914 };
7915 
7916 struct mlx5_ifc_modify_cong_params_in_bits {
7917 	u8         opcode[0x10];
7918 	u8         reserved_at_10[0x10];
7919 
7920 	u8         reserved_at_20[0x10];
7921 	u8         op_mod[0x10];
7922 
7923 	u8         reserved_at_40[0x1c];
7924 	u8         cong_protocol[0x4];
7925 
7926 	union mlx5_ifc_field_select_802_1_r_roce_auto_bits field_select;
7927 
7928 	u8         reserved_at_80[0x80];
7929 
7930 	union mlx5_ifc_cong_control_roce_ecn_auto_bits congestion_parameters;
7931 };
7932 
7933 struct mlx5_ifc_manage_pages_out_bits {
7934 	u8         status[0x8];
7935 	u8         reserved_at_8[0x18];
7936 
7937 	u8         syndrome[0x20];
7938 
7939 	u8         output_num_entries[0x20];
7940 
7941 	u8         reserved_at_60[0x20];
7942 
7943 	u8         pas[][0x40];
7944 };
7945 
7946 enum {
7947 	MLX5_MANAGE_PAGES_IN_OP_MOD_ALLOCATION_FAIL     = 0x0,
7948 	MLX5_MANAGE_PAGES_IN_OP_MOD_ALLOCATION_SUCCESS  = 0x1,
7949 	MLX5_MANAGE_PAGES_IN_OP_MOD_HCA_RETURN_PAGES    = 0x2,
7950 };
7951 
7952 struct mlx5_ifc_manage_pages_in_bits {
7953 	u8         opcode[0x10];
7954 	u8         reserved_at_10[0x10];
7955 
7956 	u8         reserved_at_20[0x10];
7957 	u8         op_mod[0x10];
7958 
7959 	u8         embedded_cpu_function[0x1];
7960 	u8         reserved_at_41[0xf];
7961 	u8         function_id[0x10];
7962 
7963 	u8         input_num_entries[0x20];
7964 
7965 	u8         pas[][0x40];
7966 };
7967 
7968 struct mlx5_ifc_mad_ifc_out_bits {
7969 	u8         status[0x8];
7970 	u8         reserved_at_8[0x18];
7971 
7972 	u8         syndrome[0x20];
7973 
7974 	u8         reserved_at_40[0x40];
7975 
7976 	u8         response_mad_packet[256][0x8];
7977 };
7978 
7979 struct mlx5_ifc_mad_ifc_in_bits {
7980 	u8         opcode[0x10];
7981 	u8         reserved_at_10[0x10];
7982 
7983 	u8         reserved_at_20[0x10];
7984 	u8         op_mod[0x10];
7985 
7986 	u8         remote_lid[0x10];
7987 	u8         plane_index[0x8];
7988 	u8         port[0x8];
7989 
7990 	u8         reserved_at_60[0x20];
7991 
7992 	u8         mad[256][0x8];
7993 };
7994 
7995 struct mlx5_ifc_init_hca_out_bits {
7996 	u8         status[0x8];
7997 	u8         reserved_at_8[0x18];
7998 
7999 	u8         syndrome[0x20];
8000 
8001 	u8         reserved_at_40[0x40];
8002 };
8003 
8004 struct mlx5_ifc_init_hca_in_bits {
8005 	u8         opcode[0x10];
8006 	u8         reserved_at_10[0x10];
8007 
8008 	u8         reserved_at_20[0x10];
8009 	u8         op_mod[0x10];
8010 
8011 	u8         reserved_at_40[0x20];
8012 
8013 	u8         reserved_at_60[0x2];
8014 	u8         sw_vhca_id[0xe];
8015 	u8         reserved_at_70[0x10];
8016 
8017 	u8	   sw_owner_id[4][0x20];
8018 };
8019 
8020 struct mlx5_ifc_init2rtr_qp_out_bits {
8021 	u8         status[0x8];
8022 	u8         reserved_at_8[0x18];
8023 
8024 	u8         syndrome[0x20];
8025 
8026 	u8         reserved_at_40[0x20];
8027 	u8         ece[0x20];
8028 };
8029 
8030 struct mlx5_ifc_init2rtr_qp_in_bits {
8031 	u8         opcode[0x10];
8032 	u8         uid[0x10];
8033 
8034 	u8         reserved_at_20[0x10];
8035 	u8         op_mod[0x10];
8036 
8037 	u8         reserved_at_40[0x8];
8038 	u8         qpn[0x18];
8039 
8040 	u8         reserved_at_60[0x20];
8041 
8042 	u8         opt_param_mask[0x20];
8043 
8044 	u8         ece[0x20];
8045 
8046 	struct mlx5_ifc_qpc_bits qpc;
8047 
8048 	u8         reserved_at_800[0x80];
8049 };
8050 
8051 struct mlx5_ifc_init2init_qp_out_bits {
8052 	u8         status[0x8];
8053 	u8         reserved_at_8[0x18];
8054 
8055 	u8         syndrome[0x20];
8056 
8057 	u8         reserved_at_40[0x20];
8058 	u8         ece[0x20];
8059 };
8060 
8061 struct mlx5_ifc_init2init_qp_in_bits {
8062 	u8         opcode[0x10];
8063 	u8         uid[0x10];
8064 
8065 	u8         reserved_at_20[0x10];
8066 	u8         op_mod[0x10];
8067 
8068 	u8         reserved_at_40[0x8];
8069 	u8         qpn[0x18];
8070 
8071 	u8         reserved_at_60[0x20];
8072 
8073 	u8         opt_param_mask[0x20];
8074 
8075 	u8         ece[0x20];
8076 
8077 	struct mlx5_ifc_qpc_bits qpc;
8078 
8079 	u8         reserved_at_800[0x80];
8080 };
8081 
8082 struct mlx5_ifc_get_dropped_packet_log_out_bits {
8083 	u8         status[0x8];
8084 	u8         reserved_at_8[0x18];
8085 
8086 	u8         syndrome[0x20];
8087 
8088 	u8         reserved_at_40[0x40];
8089 
8090 	u8         packet_headers_log[128][0x8];
8091 
8092 	u8         packet_syndrome[64][0x8];
8093 };
8094 
8095 struct mlx5_ifc_get_dropped_packet_log_in_bits {
8096 	u8         opcode[0x10];
8097 	u8         reserved_at_10[0x10];
8098 
8099 	u8         reserved_at_20[0x10];
8100 	u8         op_mod[0x10];
8101 
8102 	u8         reserved_at_40[0x40];
8103 };
8104 
8105 struct mlx5_ifc_gen_eqe_in_bits {
8106 	u8         opcode[0x10];
8107 	u8         reserved_at_10[0x10];
8108 
8109 	u8         reserved_at_20[0x10];
8110 	u8         op_mod[0x10];
8111 
8112 	u8         reserved_at_40[0x18];
8113 	u8         eq_number[0x8];
8114 
8115 	u8         reserved_at_60[0x20];
8116 
8117 	u8         eqe[64][0x8];
8118 };
8119 
8120 struct mlx5_ifc_gen_eq_out_bits {
8121 	u8         status[0x8];
8122 	u8         reserved_at_8[0x18];
8123 
8124 	u8         syndrome[0x20];
8125 
8126 	u8         reserved_at_40[0x40];
8127 };
8128 
8129 struct mlx5_ifc_enable_hca_out_bits {
8130 	u8         status[0x8];
8131 	u8         reserved_at_8[0x18];
8132 
8133 	u8         syndrome[0x20];
8134 
8135 	u8         reserved_at_40[0x20];
8136 };
8137 
8138 struct mlx5_ifc_enable_hca_in_bits {
8139 	u8         opcode[0x10];
8140 	u8         reserved_at_10[0x10];
8141 
8142 	u8         reserved_at_20[0x10];
8143 	u8         op_mod[0x10];
8144 
8145 	u8         embedded_cpu_function[0x1];
8146 	u8         reserved_at_41[0xf];
8147 	u8         function_id[0x10];
8148 
8149 	u8         reserved_at_60[0x20];
8150 };
8151 
8152 struct mlx5_ifc_drain_dct_out_bits {
8153 	u8         status[0x8];
8154 	u8         reserved_at_8[0x18];
8155 
8156 	u8         syndrome[0x20];
8157 
8158 	u8         reserved_at_40[0x40];
8159 };
8160 
8161 struct mlx5_ifc_drain_dct_in_bits {
8162 	u8         opcode[0x10];
8163 	u8         uid[0x10];
8164 
8165 	u8         reserved_at_20[0x10];
8166 	u8         op_mod[0x10];
8167 
8168 	u8         reserved_at_40[0x8];
8169 	u8         dctn[0x18];
8170 
8171 	u8         reserved_at_60[0x20];
8172 };
8173 
8174 struct mlx5_ifc_disable_hca_out_bits {
8175 	u8         status[0x8];
8176 	u8         reserved_at_8[0x18];
8177 
8178 	u8         syndrome[0x20];
8179 
8180 	u8         reserved_at_40[0x20];
8181 };
8182 
8183 struct mlx5_ifc_disable_hca_in_bits {
8184 	u8         opcode[0x10];
8185 	u8         reserved_at_10[0x10];
8186 
8187 	u8         reserved_at_20[0x10];
8188 	u8         op_mod[0x10];
8189 
8190 	u8         embedded_cpu_function[0x1];
8191 	u8         reserved_at_41[0xf];
8192 	u8         function_id[0x10];
8193 
8194 	u8         reserved_at_60[0x20];
8195 };
8196 
8197 struct mlx5_ifc_detach_from_mcg_out_bits {
8198 	u8         status[0x8];
8199 	u8         reserved_at_8[0x18];
8200 
8201 	u8         syndrome[0x20];
8202 
8203 	u8         reserved_at_40[0x40];
8204 };
8205 
8206 struct mlx5_ifc_detach_from_mcg_in_bits {
8207 	u8         opcode[0x10];
8208 	u8         uid[0x10];
8209 
8210 	u8         reserved_at_20[0x10];
8211 	u8         op_mod[0x10];
8212 
8213 	u8         reserved_at_40[0x8];
8214 	u8         qpn[0x18];
8215 
8216 	u8         reserved_at_60[0x20];
8217 
8218 	u8         multicast_gid[16][0x8];
8219 };
8220 
8221 struct mlx5_ifc_destroy_xrq_out_bits {
8222 	u8         status[0x8];
8223 	u8         reserved_at_8[0x18];
8224 
8225 	u8         syndrome[0x20];
8226 
8227 	u8         reserved_at_40[0x40];
8228 };
8229 
8230 struct mlx5_ifc_destroy_xrq_in_bits {
8231 	u8         opcode[0x10];
8232 	u8         uid[0x10];
8233 
8234 	u8         reserved_at_20[0x10];
8235 	u8         op_mod[0x10];
8236 
8237 	u8         reserved_at_40[0x8];
8238 	u8         xrqn[0x18];
8239 
8240 	u8         reserved_at_60[0x20];
8241 };
8242 
8243 struct mlx5_ifc_destroy_xrc_srq_out_bits {
8244 	u8         status[0x8];
8245 	u8         reserved_at_8[0x18];
8246 
8247 	u8         syndrome[0x20];
8248 
8249 	u8         reserved_at_40[0x40];
8250 };
8251 
8252 struct mlx5_ifc_destroy_xrc_srq_in_bits {
8253 	u8         opcode[0x10];
8254 	u8         uid[0x10];
8255 
8256 	u8         reserved_at_20[0x10];
8257 	u8         op_mod[0x10];
8258 
8259 	u8         reserved_at_40[0x8];
8260 	u8         xrc_srqn[0x18];
8261 
8262 	u8         reserved_at_60[0x20];
8263 };
8264 
8265 struct mlx5_ifc_destroy_tis_out_bits {
8266 	u8         status[0x8];
8267 	u8         reserved_at_8[0x18];
8268 
8269 	u8         syndrome[0x20];
8270 
8271 	u8         reserved_at_40[0x40];
8272 };
8273 
8274 struct mlx5_ifc_destroy_tis_in_bits {
8275 	u8         opcode[0x10];
8276 	u8         uid[0x10];
8277 
8278 	u8         reserved_at_20[0x10];
8279 	u8         op_mod[0x10];
8280 
8281 	u8         reserved_at_40[0x8];
8282 	u8         tisn[0x18];
8283 
8284 	u8         reserved_at_60[0x20];
8285 };
8286 
8287 struct mlx5_ifc_destroy_tir_out_bits {
8288 	u8         status[0x8];
8289 	u8         reserved_at_8[0x18];
8290 
8291 	u8         syndrome[0x20];
8292 
8293 	u8         reserved_at_40[0x40];
8294 };
8295 
8296 struct mlx5_ifc_destroy_tir_in_bits {
8297 	u8         opcode[0x10];
8298 	u8         uid[0x10];
8299 
8300 	u8         reserved_at_20[0x10];
8301 	u8         op_mod[0x10];
8302 
8303 	u8         reserved_at_40[0x8];
8304 	u8         tirn[0x18];
8305 
8306 	u8         reserved_at_60[0x20];
8307 };
8308 
8309 struct mlx5_ifc_destroy_srq_out_bits {
8310 	u8         status[0x8];
8311 	u8         reserved_at_8[0x18];
8312 
8313 	u8         syndrome[0x20];
8314 
8315 	u8         reserved_at_40[0x40];
8316 };
8317 
8318 struct mlx5_ifc_destroy_srq_in_bits {
8319 	u8         opcode[0x10];
8320 	u8         uid[0x10];
8321 
8322 	u8         reserved_at_20[0x10];
8323 	u8         op_mod[0x10];
8324 
8325 	u8         reserved_at_40[0x8];
8326 	u8         srqn[0x18];
8327 
8328 	u8         reserved_at_60[0x20];
8329 };
8330 
8331 struct mlx5_ifc_destroy_sq_out_bits {
8332 	u8         status[0x8];
8333 	u8         reserved_at_8[0x18];
8334 
8335 	u8         syndrome[0x20];
8336 
8337 	u8         reserved_at_40[0x40];
8338 };
8339 
8340 struct mlx5_ifc_destroy_sq_in_bits {
8341 	u8         opcode[0x10];
8342 	u8         uid[0x10];
8343 
8344 	u8         reserved_at_20[0x10];
8345 	u8         op_mod[0x10];
8346 
8347 	u8         reserved_at_40[0x8];
8348 	u8         sqn[0x18];
8349 
8350 	u8         reserved_at_60[0x20];
8351 };
8352 
8353 struct mlx5_ifc_destroy_scheduling_element_out_bits {
8354 	u8         status[0x8];
8355 	u8         reserved_at_8[0x18];
8356 
8357 	u8         syndrome[0x20];
8358 
8359 	u8         reserved_at_40[0x1c0];
8360 };
8361 
8362 struct mlx5_ifc_destroy_scheduling_element_in_bits {
8363 	u8         opcode[0x10];
8364 	u8         reserved_at_10[0x10];
8365 
8366 	u8         reserved_at_20[0x10];
8367 	u8         op_mod[0x10];
8368 
8369 	u8         scheduling_hierarchy[0x8];
8370 	u8         reserved_at_48[0x18];
8371 
8372 	u8         scheduling_element_id[0x20];
8373 
8374 	u8         reserved_at_80[0x180];
8375 };
8376 
8377 struct mlx5_ifc_destroy_rqt_out_bits {
8378 	u8         status[0x8];
8379 	u8         reserved_at_8[0x18];
8380 
8381 	u8         syndrome[0x20];
8382 
8383 	u8         reserved_at_40[0x40];
8384 };
8385 
8386 struct mlx5_ifc_destroy_rqt_in_bits {
8387 	u8         opcode[0x10];
8388 	u8         uid[0x10];
8389 
8390 	u8         reserved_at_20[0x10];
8391 	u8         op_mod[0x10];
8392 
8393 	u8         reserved_at_40[0x8];
8394 	u8         rqtn[0x18];
8395 
8396 	u8         reserved_at_60[0x20];
8397 };
8398 
8399 struct mlx5_ifc_destroy_rq_out_bits {
8400 	u8         status[0x8];
8401 	u8         reserved_at_8[0x18];
8402 
8403 	u8         syndrome[0x20];
8404 
8405 	u8         reserved_at_40[0x40];
8406 };
8407 
8408 struct mlx5_ifc_destroy_rq_in_bits {
8409 	u8         opcode[0x10];
8410 	u8         uid[0x10];
8411 
8412 	u8         reserved_at_20[0x10];
8413 	u8         op_mod[0x10];
8414 
8415 	u8         reserved_at_40[0x8];
8416 	u8         rqn[0x18];
8417 
8418 	u8         reserved_at_60[0x20];
8419 };
8420 
8421 struct mlx5_ifc_set_delay_drop_params_in_bits {
8422 	u8         opcode[0x10];
8423 	u8         reserved_at_10[0x10];
8424 
8425 	u8         reserved_at_20[0x10];
8426 	u8         op_mod[0x10];
8427 
8428 	u8         reserved_at_40[0x20];
8429 
8430 	u8         reserved_at_60[0x10];
8431 	u8         delay_drop_timeout[0x10];
8432 };
8433 
8434 struct mlx5_ifc_set_delay_drop_params_out_bits {
8435 	u8         status[0x8];
8436 	u8         reserved_at_8[0x18];
8437 
8438 	u8         syndrome[0x20];
8439 
8440 	u8         reserved_at_40[0x40];
8441 };
8442 
8443 struct mlx5_ifc_destroy_rmp_out_bits {
8444 	u8         status[0x8];
8445 	u8         reserved_at_8[0x18];
8446 
8447 	u8         syndrome[0x20];
8448 
8449 	u8         reserved_at_40[0x40];
8450 };
8451 
8452 struct mlx5_ifc_destroy_rmp_in_bits {
8453 	u8         opcode[0x10];
8454 	u8         uid[0x10];
8455 
8456 	u8         reserved_at_20[0x10];
8457 	u8         op_mod[0x10];
8458 
8459 	u8         reserved_at_40[0x8];
8460 	u8         rmpn[0x18];
8461 
8462 	u8         reserved_at_60[0x20];
8463 };
8464 
8465 struct mlx5_ifc_destroy_qp_out_bits {
8466 	u8         status[0x8];
8467 	u8         reserved_at_8[0x18];
8468 
8469 	u8         syndrome[0x20];
8470 
8471 	u8         reserved_at_40[0x40];
8472 };
8473 
8474 struct mlx5_ifc_destroy_qp_in_bits {
8475 	u8         opcode[0x10];
8476 	u8         uid[0x10];
8477 
8478 	u8         reserved_at_20[0x10];
8479 	u8         op_mod[0x10];
8480 
8481 	u8         reserved_at_40[0x8];
8482 	u8         qpn[0x18];
8483 
8484 	u8         reserved_at_60[0x20];
8485 };
8486 
8487 struct mlx5_ifc_destroy_psv_out_bits {
8488 	u8         status[0x8];
8489 	u8         reserved_at_8[0x18];
8490 
8491 	u8         syndrome[0x20];
8492 
8493 	u8         reserved_at_40[0x40];
8494 };
8495 
8496 struct mlx5_ifc_destroy_psv_in_bits {
8497 	u8         opcode[0x10];
8498 	u8         reserved_at_10[0x10];
8499 
8500 	u8         reserved_at_20[0x10];
8501 	u8         op_mod[0x10];
8502 
8503 	u8         reserved_at_40[0x8];
8504 	u8         psvn[0x18];
8505 
8506 	u8         reserved_at_60[0x20];
8507 };
8508 
8509 struct mlx5_ifc_destroy_mkey_out_bits {
8510 	u8         status[0x8];
8511 	u8         reserved_at_8[0x18];
8512 
8513 	u8         syndrome[0x20];
8514 
8515 	u8         reserved_at_40[0x40];
8516 };
8517 
8518 struct mlx5_ifc_destroy_mkey_in_bits {
8519 	u8         opcode[0x10];
8520 	u8         uid[0x10];
8521 
8522 	u8         reserved_at_20[0x10];
8523 	u8         op_mod[0x10];
8524 
8525 	u8         reserved_at_40[0x8];
8526 	u8         mkey_index[0x18];
8527 
8528 	u8         reserved_at_60[0x20];
8529 };
8530 
8531 struct mlx5_ifc_destroy_flow_table_out_bits {
8532 	u8         status[0x8];
8533 	u8         reserved_at_8[0x18];
8534 
8535 	u8         syndrome[0x20];
8536 
8537 	u8         reserved_at_40[0x40];
8538 };
8539 
8540 struct mlx5_ifc_destroy_flow_table_in_bits {
8541 	u8         opcode[0x10];
8542 	u8         reserved_at_10[0x10];
8543 
8544 	u8         reserved_at_20[0x10];
8545 	u8         op_mod[0x10];
8546 
8547 	u8         other_vport[0x1];
8548 	u8         reserved_at_41[0xf];
8549 	u8         vport_number[0x10];
8550 
8551 	u8         reserved_at_60[0x20];
8552 
8553 	u8         table_type[0x8];
8554 	u8         reserved_at_88[0x18];
8555 
8556 	u8         reserved_at_a0[0x8];
8557 	u8         table_id[0x18];
8558 
8559 	u8         reserved_at_c0[0x140];
8560 };
8561 
8562 struct mlx5_ifc_destroy_flow_group_out_bits {
8563 	u8         status[0x8];
8564 	u8         reserved_at_8[0x18];
8565 
8566 	u8         syndrome[0x20];
8567 
8568 	u8         reserved_at_40[0x40];
8569 };
8570 
8571 struct mlx5_ifc_destroy_flow_group_in_bits {
8572 	u8         opcode[0x10];
8573 	u8         reserved_at_10[0x10];
8574 
8575 	u8         reserved_at_20[0x10];
8576 	u8         op_mod[0x10];
8577 
8578 	u8         other_vport[0x1];
8579 	u8         reserved_at_41[0xf];
8580 	u8         vport_number[0x10];
8581 
8582 	u8         reserved_at_60[0x20];
8583 
8584 	u8         table_type[0x8];
8585 	u8         reserved_at_88[0x18];
8586 
8587 	u8         reserved_at_a0[0x8];
8588 	u8         table_id[0x18];
8589 
8590 	u8         group_id[0x20];
8591 
8592 	u8         reserved_at_e0[0x120];
8593 };
8594 
8595 struct mlx5_ifc_destroy_eq_out_bits {
8596 	u8         status[0x8];
8597 	u8         reserved_at_8[0x18];
8598 
8599 	u8         syndrome[0x20];
8600 
8601 	u8         reserved_at_40[0x40];
8602 };
8603 
8604 struct mlx5_ifc_destroy_eq_in_bits {
8605 	u8         opcode[0x10];
8606 	u8         reserved_at_10[0x10];
8607 
8608 	u8         reserved_at_20[0x10];
8609 	u8         op_mod[0x10];
8610 
8611 	u8         reserved_at_40[0x18];
8612 	u8         eq_number[0x8];
8613 
8614 	u8         reserved_at_60[0x20];
8615 };
8616 
8617 struct mlx5_ifc_destroy_dct_out_bits {
8618 	u8         status[0x8];
8619 	u8         reserved_at_8[0x18];
8620 
8621 	u8         syndrome[0x20];
8622 
8623 	u8         reserved_at_40[0x40];
8624 };
8625 
8626 struct mlx5_ifc_destroy_dct_in_bits {
8627 	u8         opcode[0x10];
8628 	u8         uid[0x10];
8629 
8630 	u8         reserved_at_20[0x10];
8631 	u8         op_mod[0x10];
8632 
8633 	u8         reserved_at_40[0x8];
8634 	u8         dctn[0x18];
8635 
8636 	u8         reserved_at_60[0x20];
8637 };
8638 
8639 struct mlx5_ifc_destroy_cq_out_bits {
8640 	u8         status[0x8];
8641 	u8         reserved_at_8[0x18];
8642 
8643 	u8         syndrome[0x20];
8644 
8645 	u8         reserved_at_40[0x40];
8646 };
8647 
8648 struct mlx5_ifc_destroy_cq_in_bits {
8649 	u8         opcode[0x10];
8650 	u8         uid[0x10];
8651 
8652 	u8         reserved_at_20[0x10];
8653 	u8         op_mod[0x10];
8654 
8655 	u8         reserved_at_40[0x8];
8656 	u8         cqn[0x18];
8657 
8658 	u8         reserved_at_60[0x20];
8659 };
8660 
8661 struct mlx5_ifc_delete_vxlan_udp_dport_out_bits {
8662 	u8         status[0x8];
8663 	u8         reserved_at_8[0x18];
8664 
8665 	u8         syndrome[0x20];
8666 
8667 	u8         reserved_at_40[0x40];
8668 };
8669 
8670 struct mlx5_ifc_delete_vxlan_udp_dport_in_bits {
8671 	u8         opcode[0x10];
8672 	u8         reserved_at_10[0x10];
8673 
8674 	u8         reserved_at_20[0x10];
8675 	u8         op_mod[0x10];
8676 
8677 	u8         reserved_at_40[0x20];
8678 
8679 	u8         reserved_at_60[0x10];
8680 	u8         vxlan_udp_port[0x10];
8681 };
8682 
8683 struct mlx5_ifc_delete_l2_table_entry_out_bits {
8684 	u8         status[0x8];
8685 	u8         reserved_at_8[0x18];
8686 
8687 	u8         syndrome[0x20];
8688 
8689 	u8         reserved_at_40[0x40];
8690 };
8691 
8692 struct mlx5_ifc_delete_l2_table_entry_in_bits {
8693 	u8         opcode[0x10];
8694 	u8         reserved_at_10[0x10];
8695 
8696 	u8         reserved_at_20[0x10];
8697 	u8         op_mod[0x10];
8698 
8699 	u8         reserved_at_40[0x60];
8700 
8701 	u8         reserved_at_a0[0x8];
8702 	u8         table_index[0x18];
8703 
8704 	u8         reserved_at_c0[0x140];
8705 };
8706 
8707 struct mlx5_ifc_delete_fte_out_bits {
8708 	u8         status[0x8];
8709 	u8         reserved_at_8[0x18];
8710 
8711 	u8         syndrome[0x20];
8712 
8713 	u8         reserved_at_40[0x40];
8714 };
8715 
8716 struct mlx5_ifc_delete_fte_in_bits {
8717 	u8         opcode[0x10];
8718 	u8         reserved_at_10[0x10];
8719 
8720 	u8         reserved_at_20[0x10];
8721 	u8         op_mod[0x10];
8722 
8723 	u8         other_vport[0x1];
8724 	u8         reserved_at_41[0xf];
8725 	u8         vport_number[0x10];
8726 
8727 	u8         reserved_at_60[0x20];
8728 
8729 	u8         table_type[0x8];
8730 	u8         reserved_at_88[0x18];
8731 
8732 	u8         reserved_at_a0[0x8];
8733 	u8         table_id[0x18];
8734 
8735 	u8         reserved_at_c0[0x40];
8736 
8737 	u8         flow_index[0x20];
8738 
8739 	u8         reserved_at_120[0xe0];
8740 };
8741 
8742 struct mlx5_ifc_dealloc_xrcd_out_bits {
8743 	u8         status[0x8];
8744 	u8         reserved_at_8[0x18];
8745 
8746 	u8         syndrome[0x20];
8747 
8748 	u8         reserved_at_40[0x40];
8749 };
8750 
8751 struct mlx5_ifc_dealloc_xrcd_in_bits {
8752 	u8         opcode[0x10];
8753 	u8         uid[0x10];
8754 
8755 	u8         reserved_at_20[0x10];
8756 	u8         op_mod[0x10];
8757 
8758 	u8         reserved_at_40[0x8];
8759 	u8         xrcd[0x18];
8760 
8761 	u8         reserved_at_60[0x20];
8762 };
8763 
8764 struct mlx5_ifc_dealloc_uar_out_bits {
8765 	u8         status[0x8];
8766 	u8         reserved_at_8[0x18];
8767 
8768 	u8         syndrome[0x20];
8769 
8770 	u8         reserved_at_40[0x40];
8771 };
8772 
8773 struct mlx5_ifc_dealloc_uar_in_bits {
8774 	u8         opcode[0x10];
8775 	u8         uid[0x10];
8776 
8777 	u8         reserved_at_20[0x10];
8778 	u8         op_mod[0x10];
8779 
8780 	u8         reserved_at_40[0x8];
8781 	u8         uar[0x18];
8782 
8783 	u8         reserved_at_60[0x20];
8784 };
8785 
8786 struct mlx5_ifc_dealloc_transport_domain_out_bits {
8787 	u8         status[0x8];
8788 	u8         reserved_at_8[0x18];
8789 
8790 	u8         syndrome[0x20];
8791 
8792 	u8         reserved_at_40[0x40];
8793 };
8794 
8795 struct mlx5_ifc_dealloc_transport_domain_in_bits {
8796 	u8         opcode[0x10];
8797 	u8         uid[0x10];
8798 
8799 	u8         reserved_at_20[0x10];
8800 	u8         op_mod[0x10];
8801 
8802 	u8         reserved_at_40[0x8];
8803 	u8         transport_domain[0x18];
8804 
8805 	u8         reserved_at_60[0x20];
8806 };
8807 
8808 struct mlx5_ifc_dealloc_q_counter_out_bits {
8809 	u8         status[0x8];
8810 	u8         reserved_at_8[0x18];
8811 
8812 	u8         syndrome[0x20];
8813 
8814 	u8         reserved_at_40[0x40];
8815 };
8816 
8817 struct mlx5_ifc_dealloc_q_counter_in_bits {
8818 	u8         opcode[0x10];
8819 	u8         reserved_at_10[0x10];
8820 
8821 	u8         reserved_at_20[0x10];
8822 	u8         op_mod[0x10];
8823 
8824 	u8         reserved_at_40[0x18];
8825 	u8         counter_set_id[0x8];
8826 
8827 	u8         reserved_at_60[0x20];
8828 };
8829 
8830 struct mlx5_ifc_dealloc_pd_out_bits {
8831 	u8         status[0x8];
8832 	u8         reserved_at_8[0x18];
8833 
8834 	u8         syndrome[0x20];
8835 
8836 	u8         reserved_at_40[0x40];
8837 };
8838 
8839 struct mlx5_ifc_dealloc_pd_in_bits {
8840 	u8         opcode[0x10];
8841 	u8         uid[0x10];
8842 
8843 	u8         reserved_at_20[0x10];
8844 	u8         op_mod[0x10];
8845 
8846 	u8         reserved_at_40[0x8];
8847 	u8         pd[0x18];
8848 
8849 	u8         reserved_at_60[0x20];
8850 };
8851 
8852 struct mlx5_ifc_dealloc_flow_counter_out_bits {
8853 	u8         status[0x8];
8854 	u8         reserved_at_8[0x18];
8855 
8856 	u8         syndrome[0x20];
8857 
8858 	u8         reserved_at_40[0x40];
8859 };
8860 
8861 struct mlx5_ifc_dealloc_flow_counter_in_bits {
8862 	u8         opcode[0x10];
8863 	u8         reserved_at_10[0x10];
8864 
8865 	u8         reserved_at_20[0x10];
8866 	u8         op_mod[0x10];
8867 
8868 	u8         flow_counter_id[0x20];
8869 
8870 	u8         reserved_at_60[0x20];
8871 };
8872 
8873 struct mlx5_ifc_create_xrq_out_bits {
8874 	u8         status[0x8];
8875 	u8         reserved_at_8[0x18];
8876 
8877 	u8         syndrome[0x20];
8878 
8879 	u8         reserved_at_40[0x8];
8880 	u8         xrqn[0x18];
8881 
8882 	u8         reserved_at_60[0x20];
8883 };
8884 
8885 struct mlx5_ifc_create_xrq_in_bits {
8886 	u8         opcode[0x10];
8887 	u8         uid[0x10];
8888 
8889 	u8         reserved_at_20[0x10];
8890 	u8         op_mod[0x10];
8891 
8892 	u8         reserved_at_40[0x40];
8893 
8894 	struct mlx5_ifc_xrqc_bits xrq_context;
8895 };
8896 
8897 struct mlx5_ifc_create_xrc_srq_out_bits {
8898 	u8         status[0x8];
8899 	u8         reserved_at_8[0x18];
8900 
8901 	u8         syndrome[0x20];
8902 
8903 	u8         reserved_at_40[0x8];
8904 	u8         xrc_srqn[0x18];
8905 
8906 	u8         reserved_at_60[0x20];
8907 };
8908 
8909 struct mlx5_ifc_create_xrc_srq_in_bits {
8910 	u8         opcode[0x10];
8911 	u8         uid[0x10];
8912 
8913 	u8         reserved_at_20[0x10];
8914 	u8         op_mod[0x10];
8915 
8916 	u8         reserved_at_40[0x40];
8917 
8918 	struct mlx5_ifc_xrc_srqc_bits xrc_srq_context_entry;
8919 
8920 	u8         reserved_at_280[0x60];
8921 
8922 	u8         xrc_srq_umem_valid[0x1];
8923 	u8         reserved_at_2e1[0x1f];
8924 
8925 	u8         reserved_at_300[0x580];
8926 
8927 	u8         pas[][0x40];
8928 };
8929 
8930 struct mlx5_ifc_create_tis_out_bits {
8931 	u8         status[0x8];
8932 	u8         reserved_at_8[0x18];
8933 
8934 	u8         syndrome[0x20];
8935 
8936 	u8         reserved_at_40[0x8];
8937 	u8         tisn[0x18];
8938 
8939 	u8         reserved_at_60[0x20];
8940 };
8941 
8942 struct mlx5_ifc_create_tis_in_bits {
8943 	u8         opcode[0x10];
8944 	u8         uid[0x10];
8945 
8946 	u8         reserved_at_20[0x10];
8947 	u8         op_mod[0x10];
8948 
8949 	u8         reserved_at_40[0xc0];
8950 
8951 	struct mlx5_ifc_tisc_bits ctx;
8952 };
8953 
8954 struct mlx5_ifc_create_tir_out_bits {
8955 	u8         status[0x8];
8956 	u8         icm_address_63_40[0x18];
8957 
8958 	u8         syndrome[0x20];
8959 
8960 	u8         icm_address_39_32[0x8];
8961 	u8         tirn[0x18];
8962 
8963 	u8         icm_address_31_0[0x20];
8964 };
8965 
8966 struct mlx5_ifc_create_tir_in_bits {
8967 	u8         opcode[0x10];
8968 	u8         uid[0x10];
8969 
8970 	u8         reserved_at_20[0x10];
8971 	u8         op_mod[0x10];
8972 
8973 	u8         reserved_at_40[0xc0];
8974 
8975 	struct mlx5_ifc_tirc_bits ctx;
8976 };
8977 
8978 struct mlx5_ifc_create_srq_out_bits {
8979 	u8         status[0x8];
8980 	u8         reserved_at_8[0x18];
8981 
8982 	u8         syndrome[0x20];
8983 
8984 	u8         reserved_at_40[0x8];
8985 	u8         srqn[0x18];
8986 
8987 	u8         reserved_at_60[0x20];
8988 };
8989 
8990 struct mlx5_ifc_create_srq_in_bits {
8991 	u8         opcode[0x10];
8992 	u8         uid[0x10];
8993 
8994 	u8         reserved_at_20[0x10];
8995 	u8         op_mod[0x10];
8996 
8997 	u8         reserved_at_40[0x40];
8998 
8999 	struct mlx5_ifc_srqc_bits srq_context_entry;
9000 
9001 	u8         reserved_at_280[0x600];
9002 
9003 	u8         pas[][0x40];
9004 };
9005 
9006 struct mlx5_ifc_create_sq_out_bits {
9007 	u8         status[0x8];
9008 	u8         reserved_at_8[0x18];
9009 
9010 	u8         syndrome[0x20];
9011 
9012 	u8         reserved_at_40[0x8];
9013 	u8         sqn[0x18];
9014 
9015 	u8         reserved_at_60[0x20];
9016 };
9017 
9018 struct mlx5_ifc_create_sq_in_bits {
9019 	u8         opcode[0x10];
9020 	u8         uid[0x10];
9021 
9022 	u8         reserved_at_20[0x10];
9023 	u8         op_mod[0x10];
9024 
9025 	u8         reserved_at_40[0xc0];
9026 
9027 	struct mlx5_ifc_sqc_bits ctx;
9028 };
9029 
9030 struct mlx5_ifc_create_scheduling_element_out_bits {
9031 	u8         status[0x8];
9032 	u8         reserved_at_8[0x18];
9033 
9034 	u8         syndrome[0x20];
9035 
9036 	u8         reserved_at_40[0x40];
9037 
9038 	u8         scheduling_element_id[0x20];
9039 
9040 	u8         reserved_at_a0[0x160];
9041 };
9042 
9043 struct mlx5_ifc_create_scheduling_element_in_bits {
9044 	u8         opcode[0x10];
9045 	u8         reserved_at_10[0x10];
9046 
9047 	u8         reserved_at_20[0x10];
9048 	u8         op_mod[0x10];
9049 
9050 	u8         scheduling_hierarchy[0x8];
9051 	u8         reserved_at_48[0x18];
9052 
9053 	u8         reserved_at_60[0xa0];
9054 
9055 	struct mlx5_ifc_scheduling_context_bits scheduling_context;
9056 
9057 	u8         reserved_at_300[0x100];
9058 };
9059 
9060 struct mlx5_ifc_create_rqt_out_bits {
9061 	u8         status[0x8];
9062 	u8         reserved_at_8[0x18];
9063 
9064 	u8         syndrome[0x20];
9065 
9066 	u8         reserved_at_40[0x8];
9067 	u8         rqtn[0x18];
9068 
9069 	u8         reserved_at_60[0x20];
9070 };
9071 
9072 struct mlx5_ifc_create_rqt_in_bits {
9073 	u8         opcode[0x10];
9074 	u8         uid[0x10];
9075 
9076 	u8         reserved_at_20[0x10];
9077 	u8         op_mod[0x10];
9078 
9079 	u8         reserved_at_40[0xc0];
9080 
9081 	struct mlx5_ifc_rqtc_bits rqt_context;
9082 };
9083 
9084 struct mlx5_ifc_create_rq_out_bits {
9085 	u8         status[0x8];
9086 	u8         reserved_at_8[0x18];
9087 
9088 	u8         syndrome[0x20];
9089 
9090 	u8         reserved_at_40[0x8];
9091 	u8         rqn[0x18];
9092 
9093 	u8         reserved_at_60[0x20];
9094 };
9095 
9096 struct mlx5_ifc_create_rq_in_bits {
9097 	u8         opcode[0x10];
9098 	u8         uid[0x10];
9099 
9100 	u8         reserved_at_20[0x10];
9101 	u8         op_mod[0x10];
9102 
9103 	u8         reserved_at_40[0xc0];
9104 
9105 	struct mlx5_ifc_rqc_bits ctx;
9106 };
9107 
9108 struct mlx5_ifc_create_rmp_out_bits {
9109 	u8         status[0x8];
9110 	u8         reserved_at_8[0x18];
9111 
9112 	u8         syndrome[0x20];
9113 
9114 	u8         reserved_at_40[0x8];
9115 	u8         rmpn[0x18];
9116 
9117 	u8         reserved_at_60[0x20];
9118 };
9119 
9120 struct mlx5_ifc_create_rmp_in_bits {
9121 	u8         opcode[0x10];
9122 	u8         uid[0x10];
9123 
9124 	u8         reserved_at_20[0x10];
9125 	u8         op_mod[0x10];
9126 
9127 	u8         reserved_at_40[0xc0];
9128 
9129 	struct mlx5_ifc_rmpc_bits ctx;
9130 };
9131 
9132 struct mlx5_ifc_create_qp_out_bits {
9133 	u8         status[0x8];
9134 	u8         reserved_at_8[0x18];
9135 
9136 	u8         syndrome[0x20];
9137 
9138 	u8         reserved_at_40[0x8];
9139 	u8         qpn[0x18];
9140 
9141 	u8         ece[0x20];
9142 };
9143 
9144 struct mlx5_ifc_create_qp_in_bits {
9145 	u8         opcode[0x10];
9146 	u8         uid[0x10];
9147 
9148 	u8         reserved_at_20[0x10];
9149 	u8         op_mod[0x10];
9150 
9151 	u8         qpc_ext[0x1];
9152 	u8         reserved_at_41[0x7];
9153 	u8         input_qpn[0x18];
9154 
9155 	u8         reserved_at_60[0x20];
9156 	u8         opt_param_mask[0x20];
9157 
9158 	u8         ece[0x20];
9159 
9160 	struct mlx5_ifc_qpc_bits qpc;
9161 
9162 	u8         wq_umem_offset[0x40];
9163 
9164 	u8         wq_umem_id[0x20];
9165 
9166 	u8         wq_umem_valid[0x1];
9167 	u8         reserved_at_861[0x1f];
9168 
9169 	u8         pas[][0x40];
9170 };
9171 
9172 struct mlx5_ifc_create_psv_out_bits {
9173 	u8         status[0x8];
9174 	u8         reserved_at_8[0x18];
9175 
9176 	u8         syndrome[0x20];
9177 
9178 	u8         reserved_at_40[0x40];
9179 
9180 	u8         reserved_at_80[0x8];
9181 	u8         psv0_index[0x18];
9182 
9183 	u8         reserved_at_a0[0x8];
9184 	u8         psv1_index[0x18];
9185 
9186 	u8         reserved_at_c0[0x8];
9187 	u8         psv2_index[0x18];
9188 
9189 	u8         reserved_at_e0[0x8];
9190 	u8         psv3_index[0x18];
9191 };
9192 
9193 struct mlx5_ifc_create_psv_in_bits {
9194 	u8         opcode[0x10];
9195 	u8         reserved_at_10[0x10];
9196 
9197 	u8         reserved_at_20[0x10];
9198 	u8         op_mod[0x10];
9199 
9200 	u8         num_psv[0x4];
9201 	u8         reserved_at_44[0x4];
9202 	u8         pd[0x18];
9203 
9204 	u8         reserved_at_60[0x20];
9205 };
9206 
9207 struct mlx5_ifc_create_mkey_out_bits {
9208 	u8         status[0x8];
9209 	u8         reserved_at_8[0x18];
9210 
9211 	u8         syndrome[0x20];
9212 
9213 	u8         reserved_at_40[0x8];
9214 	u8         mkey_index[0x18];
9215 
9216 	u8         reserved_at_60[0x20];
9217 };
9218 
9219 struct mlx5_ifc_create_mkey_in_bits {
9220 	u8         opcode[0x10];
9221 	u8         uid[0x10];
9222 
9223 	u8         reserved_at_20[0x10];
9224 	u8         op_mod[0x10];
9225 
9226 	u8         reserved_at_40[0x20];
9227 
9228 	u8         pg_access[0x1];
9229 	u8         mkey_umem_valid[0x1];
9230 	u8         data_direct[0x1];
9231 	u8         reserved_at_63[0x1d];
9232 
9233 	struct mlx5_ifc_mkc_bits memory_key_mkey_entry;
9234 
9235 	u8         reserved_at_280[0x80];
9236 
9237 	u8         translations_octword_actual_size[0x20];
9238 
9239 	u8         reserved_at_320[0x560];
9240 
9241 	u8         klm_pas_mtt[][0x20];
9242 };
9243 
9244 enum {
9245 	MLX5_FLOW_TABLE_TYPE_NIC_RX		= 0x0,
9246 	MLX5_FLOW_TABLE_TYPE_NIC_TX		= 0x1,
9247 	MLX5_FLOW_TABLE_TYPE_ESW_EGRESS_ACL	= 0x2,
9248 	MLX5_FLOW_TABLE_TYPE_ESW_INGRESS_ACL	= 0x3,
9249 	MLX5_FLOW_TABLE_TYPE_FDB		= 0X4,
9250 	MLX5_FLOW_TABLE_TYPE_SNIFFER_RX		= 0X5,
9251 	MLX5_FLOW_TABLE_TYPE_SNIFFER_TX		= 0X6,
9252 };
9253 
9254 struct mlx5_ifc_create_flow_table_out_bits {
9255 	u8         status[0x8];
9256 	u8         icm_address_63_40[0x18];
9257 
9258 	u8         syndrome[0x20];
9259 
9260 	u8         icm_address_39_32[0x8];
9261 	u8         table_id[0x18];
9262 
9263 	u8         icm_address_31_0[0x20];
9264 };
9265 
9266 struct mlx5_ifc_create_flow_table_in_bits {
9267 	u8         opcode[0x10];
9268 	u8         uid[0x10];
9269 
9270 	u8         reserved_at_20[0x10];
9271 	u8         op_mod[0x10];
9272 
9273 	u8         other_vport[0x1];
9274 	u8         reserved_at_41[0xf];
9275 	u8         vport_number[0x10];
9276 
9277 	u8         reserved_at_60[0x20];
9278 
9279 	u8         table_type[0x8];
9280 	u8         reserved_at_88[0x18];
9281 
9282 	u8         reserved_at_a0[0x20];
9283 
9284 	struct mlx5_ifc_flow_table_context_bits flow_table_context;
9285 };
9286 
9287 struct mlx5_ifc_create_flow_group_out_bits {
9288 	u8         status[0x8];
9289 	u8         reserved_at_8[0x18];
9290 
9291 	u8         syndrome[0x20];
9292 
9293 	u8         reserved_at_40[0x8];
9294 	u8         group_id[0x18];
9295 
9296 	u8         reserved_at_60[0x20];
9297 };
9298 
9299 enum {
9300 	MLX5_CREATE_FLOW_GROUP_IN_GROUP_TYPE_TCAM_SUBTABLE  = 0x0,
9301 	MLX5_CREATE_FLOW_GROUP_IN_GROUP_TYPE_HASH_SPLIT     = 0x1,
9302 };
9303 
9304 enum {
9305 	MLX5_CREATE_FLOW_GROUP_IN_MATCH_CRITERIA_ENABLE_OUTER_HEADERS     = 0x0,
9306 	MLX5_CREATE_FLOW_GROUP_IN_MATCH_CRITERIA_ENABLE_MISC_PARAMETERS   = 0x1,
9307 	MLX5_CREATE_FLOW_GROUP_IN_MATCH_CRITERIA_ENABLE_INNER_HEADERS     = 0x2,
9308 	MLX5_CREATE_FLOW_GROUP_IN_MATCH_CRITERIA_ENABLE_MISC_PARAMETERS_2 = 0x3,
9309 };
9310 
9311 struct mlx5_ifc_create_flow_group_in_bits {
9312 	u8         opcode[0x10];
9313 	u8         reserved_at_10[0x10];
9314 
9315 	u8         reserved_at_20[0x10];
9316 	u8         op_mod[0x10];
9317 
9318 	u8         other_vport[0x1];
9319 	u8         reserved_at_41[0xf];
9320 	u8         vport_number[0x10];
9321 
9322 	u8         reserved_at_60[0x20];
9323 
9324 	u8         table_type[0x8];
9325 	u8         reserved_at_88[0x4];
9326 	u8         group_type[0x4];
9327 	u8         reserved_at_90[0x10];
9328 
9329 	u8         reserved_at_a0[0x8];
9330 	u8         table_id[0x18];
9331 
9332 	u8         source_eswitch_owner_vhca_id_valid[0x1];
9333 
9334 	u8         reserved_at_c1[0x1f];
9335 
9336 	u8         start_flow_index[0x20];
9337 
9338 	u8         reserved_at_100[0x20];
9339 
9340 	u8         end_flow_index[0x20];
9341 
9342 	u8         reserved_at_140[0x10];
9343 	u8         match_definer_id[0x10];
9344 
9345 	u8         reserved_at_160[0x80];
9346 
9347 	u8         reserved_at_1e0[0x18];
9348 	u8         match_criteria_enable[0x8];
9349 
9350 	struct mlx5_ifc_fte_match_param_bits match_criteria;
9351 
9352 	u8         reserved_at_1200[0xe00];
9353 };
9354 
9355 struct mlx5_ifc_create_eq_out_bits {
9356 	u8         status[0x8];
9357 	u8         reserved_at_8[0x18];
9358 
9359 	u8         syndrome[0x20];
9360 
9361 	u8         reserved_at_40[0x18];
9362 	u8         eq_number[0x8];
9363 
9364 	u8         reserved_at_60[0x20];
9365 };
9366 
9367 struct mlx5_ifc_create_eq_in_bits {
9368 	u8         opcode[0x10];
9369 	u8         uid[0x10];
9370 
9371 	u8         reserved_at_20[0x10];
9372 	u8         op_mod[0x10];
9373 
9374 	u8         reserved_at_40[0x40];
9375 
9376 	struct mlx5_ifc_eqc_bits eq_context_entry;
9377 
9378 	u8         reserved_at_280[0x40];
9379 
9380 	u8         event_bitmask[4][0x40];
9381 
9382 	u8         reserved_at_3c0[0x4c0];
9383 
9384 	u8         pas[][0x40];
9385 };
9386 
9387 struct mlx5_ifc_create_dct_out_bits {
9388 	u8         status[0x8];
9389 	u8         reserved_at_8[0x18];
9390 
9391 	u8         syndrome[0x20];
9392 
9393 	u8         reserved_at_40[0x8];
9394 	u8         dctn[0x18];
9395 
9396 	u8         ece[0x20];
9397 };
9398 
9399 struct mlx5_ifc_create_dct_in_bits {
9400 	u8         opcode[0x10];
9401 	u8         uid[0x10];
9402 
9403 	u8         reserved_at_20[0x10];
9404 	u8         op_mod[0x10];
9405 
9406 	u8         reserved_at_40[0x40];
9407 
9408 	struct mlx5_ifc_dctc_bits dct_context_entry;
9409 
9410 	u8         reserved_at_280[0x180];
9411 };
9412 
9413 struct mlx5_ifc_create_cq_out_bits {
9414 	u8         status[0x8];
9415 	u8         reserved_at_8[0x18];
9416 
9417 	u8         syndrome[0x20];
9418 
9419 	u8         reserved_at_40[0x8];
9420 	u8         cqn[0x18];
9421 
9422 	u8         reserved_at_60[0x20];
9423 };
9424 
9425 struct mlx5_ifc_create_cq_in_bits {
9426 	u8         opcode[0x10];
9427 	u8         uid[0x10];
9428 
9429 	u8         reserved_at_20[0x10];
9430 	u8         op_mod[0x10];
9431 
9432 	u8         reserved_at_40[0x40];
9433 
9434 	struct mlx5_ifc_cqc_bits cq_context;
9435 
9436 	u8         reserved_at_280[0x60];
9437 
9438 	u8         cq_umem_valid[0x1];
9439 	u8         reserved_at_2e1[0x59f];
9440 
9441 	u8         pas[][0x40];
9442 };
9443 
9444 struct mlx5_ifc_config_int_moderation_out_bits {
9445 	u8         status[0x8];
9446 	u8         reserved_at_8[0x18];
9447 
9448 	u8         syndrome[0x20];
9449 
9450 	u8         reserved_at_40[0x4];
9451 	u8         min_delay[0xc];
9452 	u8         int_vector[0x10];
9453 
9454 	u8         reserved_at_60[0x20];
9455 };
9456 
9457 enum {
9458 	MLX5_CONFIG_INT_MODERATION_IN_OP_MOD_WRITE  = 0x0,
9459 	MLX5_CONFIG_INT_MODERATION_IN_OP_MOD_READ   = 0x1,
9460 };
9461 
9462 struct mlx5_ifc_config_int_moderation_in_bits {
9463 	u8         opcode[0x10];
9464 	u8         reserved_at_10[0x10];
9465 
9466 	u8         reserved_at_20[0x10];
9467 	u8         op_mod[0x10];
9468 
9469 	u8         reserved_at_40[0x4];
9470 	u8         min_delay[0xc];
9471 	u8         int_vector[0x10];
9472 
9473 	u8         reserved_at_60[0x20];
9474 };
9475 
9476 struct mlx5_ifc_attach_to_mcg_out_bits {
9477 	u8         status[0x8];
9478 	u8         reserved_at_8[0x18];
9479 
9480 	u8         syndrome[0x20];
9481 
9482 	u8         reserved_at_40[0x40];
9483 };
9484 
9485 struct mlx5_ifc_attach_to_mcg_in_bits {
9486 	u8         opcode[0x10];
9487 	u8         uid[0x10];
9488 
9489 	u8         reserved_at_20[0x10];
9490 	u8         op_mod[0x10];
9491 
9492 	u8         reserved_at_40[0x8];
9493 	u8         qpn[0x18];
9494 
9495 	u8         reserved_at_60[0x20];
9496 
9497 	u8         multicast_gid[16][0x8];
9498 };
9499 
9500 struct mlx5_ifc_arm_xrq_out_bits {
9501 	u8         status[0x8];
9502 	u8         reserved_at_8[0x18];
9503 
9504 	u8         syndrome[0x20];
9505 
9506 	u8         reserved_at_40[0x40];
9507 };
9508 
9509 struct mlx5_ifc_arm_xrq_in_bits {
9510 	u8         opcode[0x10];
9511 	u8         reserved_at_10[0x10];
9512 
9513 	u8         reserved_at_20[0x10];
9514 	u8         op_mod[0x10];
9515 
9516 	u8         reserved_at_40[0x8];
9517 	u8         xrqn[0x18];
9518 
9519 	u8         reserved_at_60[0x10];
9520 	u8         lwm[0x10];
9521 };
9522 
9523 struct mlx5_ifc_arm_xrc_srq_out_bits {
9524 	u8         status[0x8];
9525 	u8         reserved_at_8[0x18];
9526 
9527 	u8         syndrome[0x20];
9528 
9529 	u8         reserved_at_40[0x40];
9530 };
9531 
9532 enum {
9533 	MLX5_ARM_XRC_SRQ_IN_OP_MOD_XRC_SRQ  = 0x1,
9534 };
9535 
9536 struct mlx5_ifc_arm_xrc_srq_in_bits {
9537 	u8         opcode[0x10];
9538 	u8         uid[0x10];
9539 
9540 	u8         reserved_at_20[0x10];
9541 	u8         op_mod[0x10];
9542 
9543 	u8         reserved_at_40[0x8];
9544 	u8         xrc_srqn[0x18];
9545 
9546 	u8         reserved_at_60[0x10];
9547 	u8         lwm[0x10];
9548 };
9549 
9550 struct mlx5_ifc_arm_rq_out_bits {
9551 	u8         status[0x8];
9552 	u8         reserved_at_8[0x18];
9553 
9554 	u8         syndrome[0x20];
9555 
9556 	u8         reserved_at_40[0x40];
9557 };
9558 
9559 enum {
9560 	MLX5_ARM_RQ_IN_OP_MOD_SRQ = 0x1,
9561 	MLX5_ARM_RQ_IN_OP_MOD_XRQ = 0x2,
9562 };
9563 
9564 struct mlx5_ifc_arm_rq_in_bits {
9565 	u8         opcode[0x10];
9566 	u8         uid[0x10];
9567 
9568 	u8         reserved_at_20[0x10];
9569 	u8         op_mod[0x10];
9570 
9571 	u8         reserved_at_40[0x8];
9572 	u8         srq_number[0x18];
9573 
9574 	u8         reserved_at_60[0x10];
9575 	u8         lwm[0x10];
9576 };
9577 
9578 struct mlx5_ifc_arm_dct_out_bits {
9579 	u8         status[0x8];
9580 	u8         reserved_at_8[0x18];
9581 
9582 	u8         syndrome[0x20];
9583 
9584 	u8         reserved_at_40[0x40];
9585 };
9586 
9587 struct mlx5_ifc_arm_dct_in_bits {
9588 	u8         opcode[0x10];
9589 	u8         reserved_at_10[0x10];
9590 
9591 	u8         reserved_at_20[0x10];
9592 	u8         op_mod[0x10];
9593 
9594 	u8         reserved_at_40[0x8];
9595 	u8         dct_number[0x18];
9596 
9597 	u8         reserved_at_60[0x20];
9598 };
9599 
9600 struct mlx5_ifc_alloc_xrcd_out_bits {
9601 	u8         status[0x8];
9602 	u8         reserved_at_8[0x18];
9603 
9604 	u8         syndrome[0x20];
9605 
9606 	u8         reserved_at_40[0x8];
9607 	u8         xrcd[0x18];
9608 
9609 	u8         reserved_at_60[0x20];
9610 };
9611 
9612 struct mlx5_ifc_alloc_xrcd_in_bits {
9613 	u8         opcode[0x10];
9614 	u8         uid[0x10];
9615 
9616 	u8         reserved_at_20[0x10];
9617 	u8         op_mod[0x10];
9618 
9619 	u8         reserved_at_40[0x40];
9620 };
9621 
9622 struct mlx5_ifc_alloc_uar_out_bits {
9623 	u8         status[0x8];
9624 	u8         reserved_at_8[0x18];
9625 
9626 	u8         syndrome[0x20];
9627 
9628 	u8         reserved_at_40[0x8];
9629 	u8         uar[0x18];
9630 
9631 	u8         reserved_at_60[0x20];
9632 };
9633 
9634 struct mlx5_ifc_alloc_uar_in_bits {
9635 	u8         opcode[0x10];
9636 	u8         uid[0x10];
9637 
9638 	u8         reserved_at_20[0x10];
9639 	u8         op_mod[0x10];
9640 
9641 	u8         reserved_at_40[0x40];
9642 };
9643 
9644 struct mlx5_ifc_alloc_transport_domain_out_bits {
9645 	u8         status[0x8];
9646 	u8         reserved_at_8[0x18];
9647 
9648 	u8         syndrome[0x20];
9649 
9650 	u8         reserved_at_40[0x8];
9651 	u8         transport_domain[0x18];
9652 
9653 	u8         reserved_at_60[0x20];
9654 };
9655 
9656 struct mlx5_ifc_alloc_transport_domain_in_bits {
9657 	u8         opcode[0x10];
9658 	u8         uid[0x10];
9659 
9660 	u8         reserved_at_20[0x10];
9661 	u8         op_mod[0x10];
9662 
9663 	u8         reserved_at_40[0x40];
9664 };
9665 
9666 struct mlx5_ifc_alloc_q_counter_out_bits {
9667 	u8         status[0x8];
9668 	u8         reserved_at_8[0x18];
9669 
9670 	u8         syndrome[0x20];
9671 
9672 	u8         reserved_at_40[0x18];
9673 	u8         counter_set_id[0x8];
9674 
9675 	u8         reserved_at_60[0x20];
9676 };
9677 
9678 struct mlx5_ifc_alloc_q_counter_in_bits {
9679 	u8         opcode[0x10];
9680 	u8         uid[0x10];
9681 
9682 	u8         reserved_at_20[0x10];
9683 	u8         op_mod[0x10];
9684 
9685 	u8         reserved_at_40[0x40];
9686 };
9687 
9688 struct mlx5_ifc_alloc_pd_out_bits {
9689 	u8         status[0x8];
9690 	u8         reserved_at_8[0x18];
9691 
9692 	u8         syndrome[0x20];
9693 
9694 	u8         reserved_at_40[0x8];
9695 	u8         pd[0x18];
9696 
9697 	u8         reserved_at_60[0x20];
9698 };
9699 
9700 struct mlx5_ifc_alloc_pd_in_bits {
9701 	u8         opcode[0x10];
9702 	u8         uid[0x10];
9703 
9704 	u8         reserved_at_20[0x10];
9705 	u8         op_mod[0x10];
9706 
9707 	u8         reserved_at_40[0x40];
9708 };
9709 
9710 struct mlx5_ifc_alloc_flow_counter_out_bits {
9711 	u8         status[0x8];
9712 	u8         reserved_at_8[0x18];
9713 
9714 	u8         syndrome[0x20];
9715 
9716 	u8         flow_counter_id[0x20];
9717 
9718 	u8         reserved_at_60[0x20];
9719 };
9720 
9721 struct mlx5_ifc_alloc_flow_counter_in_bits {
9722 	u8         opcode[0x10];
9723 	u8         reserved_at_10[0x10];
9724 
9725 	u8         reserved_at_20[0x10];
9726 	u8         op_mod[0x10];
9727 
9728 	u8         reserved_at_40[0x33];
9729 	u8         flow_counter_bulk_log_size[0x5];
9730 	u8         flow_counter_bulk[0x8];
9731 };
9732 
9733 struct mlx5_ifc_add_vxlan_udp_dport_out_bits {
9734 	u8         status[0x8];
9735 	u8         reserved_at_8[0x18];
9736 
9737 	u8         syndrome[0x20];
9738 
9739 	u8         reserved_at_40[0x40];
9740 };
9741 
9742 struct mlx5_ifc_add_vxlan_udp_dport_in_bits {
9743 	u8         opcode[0x10];
9744 	u8         reserved_at_10[0x10];
9745 
9746 	u8         reserved_at_20[0x10];
9747 	u8         op_mod[0x10];
9748 
9749 	u8         reserved_at_40[0x20];
9750 
9751 	u8         reserved_at_60[0x10];
9752 	u8         vxlan_udp_port[0x10];
9753 };
9754 
9755 struct mlx5_ifc_set_pp_rate_limit_out_bits {
9756 	u8         status[0x8];
9757 	u8         reserved_at_8[0x18];
9758 
9759 	u8         syndrome[0x20];
9760 
9761 	u8         reserved_at_40[0x40];
9762 };
9763 
9764 struct mlx5_ifc_set_pp_rate_limit_context_bits {
9765 	u8         rate_limit[0x20];
9766 
9767 	u8	   burst_upper_bound[0x20];
9768 
9769 	u8         reserved_at_40[0x10];
9770 	u8	   typical_packet_size[0x10];
9771 
9772 	u8         reserved_at_60[0x120];
9773 };
9774 
9775 struct mlx5_ifc_set_pp_rate_limit_in_bits {
9776 	u8         opcode[0x10];
9777 	u8         uid[0x10];
9778 
9779 	u8         reserved_at_20[0x10];
9780 	u8         op_mod[0x10];
9781 
9782 	u8         reserved_at_40[0x10];
9783 	u8         rate_limit_index[0x10];
9784 
9785 	u8         reserved_at_60[0x20];
9786 
9787 	struct mlx5_ifc_set_pp_rate_limit_context_bits ctx;
9788 };
9789 
9790 struct mlx5_ifc_access_register_out_bits {
9791 	u8         status[0x8];
9792 	u8         reserved_at_8[0x18];
9793 
9794 	u8         syndrome[0x20];
9795 
9796 	u8         reserved_at_40[0x40];
9797 
9798 	u8         register_data[][0x20];
9799 };
9800 
9801 enum {
9802 	MLX5_ACCESS_REGISTER_IN_OP_MOD_WRITE  = 0x0,
9803 	MLX5_ACCESS_REGISTER_IN_OP_MOD_READ   = 0x1,
9804 };
9805 
9806 struct mlx5_ifc_access_register_in_bits {
9807 	u8         opcode[0x10];
9808 	u8         reserved_at_10[0x10];
9809 
9810 	u8         reserved_at_20[0x10];
9811 	u8         op_mod[0x10];
9812 
9813 	u8         reserved_at_40[0x10];
9814 	u8         register_id[0x10];
9815 
9816 	u8         argument[0x20];
9817 
9818 	u8         register_data[][0x20];
9819 };
9820 
9821 struct mlx5_ifc_sltp_reg_bits {
9822 	u8         status[0x4];
9823 	u8         version[0x4];
9824 	u8         local_port[0x8];
9825 	u8         pnat[0x2];
9826 	u8         reserved_at_12[0x2];
9827 	u8         lane[0x4];
9828 	u8         reserved_at_18[0x8];
9829 
9830 	u8         reserved_at_20[0x20];
9831 
9832 	u8         reserved_at_40[0x7];
9833 	u8         polarity[0x1];
9834 	u8         ob_tap0[0x8];
9835 	u8         ob_tap1[0x8];
9836 	u8         ob_tap2[0x8];
9837 
9838 	u8         reserved_at_60[0xc];
9839 	u8         ob_preemp_mode[0x4];
9840 	u8         ob_reg[0x8];
9841 	u8         ob_bias[0x8];
9842 
9843 	u8         reserved_at_80[0x20];
9844 };
9845 
9846 struct mlx5_ifc_slrg_reg_bits {
9847 	u8         status[0x4];
9848 	u8         version[0x4];
9849 	u8         local_port[0x8];
9850 	u8         pnat[0x2];
9851 	u8         reserved_at_12[0x2];
9852 	u8         lane[0x4];
9853 	u8         reserved_at_18[0x8];
9854 
9855 	u8         time_to_link_up[0x10];
9856 	u8         reserved_at_30[0xc];
9857 	u8         grade_lane_speed[0x4];
9858 
9859 	u8         grade_version[0x8];
9860 	u8         grade[0x18];
9861 
9862 	u8         reserved_at_60[0x4];
9863 	u8         height_grade_type[0x4];
9864 	u8         height_grade[0x18];
9865 
9866 	u8         height_dz[0x10];
9867 	u8         height_dv[0x10];
9868 
9869 	u8         reserved_at_a0[0x10];
9870 	u8         height_sigma[0x10];
9871 
9872 	u8         reserved_at_c0[0x20];
9873 
9874 	u8         reserved_at_e0[0x4];
9875 	u8         phase_grade_type[0x4];
9876 	u8         phase_grade[0x18];
9877 
9878 	u8         reserved_at_100[0x8];
9879 	u8         phase_eo_pos[0x8];
9880 	u8         reserved_at_110[0x8];
9881 	u8         phase_eo_neg[0x8];
9882 
9883 	u8         ffe_set_tested[0x10];
9884 	u8         test_errors_per_lane[0x10];
9885 };
9886 
9887 struct mlx5_ifc_pvlc_reg_bits {
9888 	u8         reserved_at_0[0x8];
9889 	u8         local_port[0x8];
9890 	u8         reserved_at_10[0x10];
9891 
9892 	u8         reserved_at_20[0x1c];
9893 	u8         vl_hw_cap[0x4];
9894 
9895 	u8         reserved_at_40[0x1c];
9896 	u8         vl_admin[0x4];
9897 
9898 	u8         reserved_at_60[0x1c];
9899 	u8         vl_operational[0x4];
9900 };
9901 
9902 struct mlx5_ifc_pude_reg_bits {
9903 	u8         swid[0x8];
9904 	u8         local_port[0x8];
9905 	u8         reserved_at_10[0x4];
9906 	u8         admin_status[0x4];
9907 	u8         reserved_at_18[0x4];
9908 	u8         oper_status[0x4];
9909 
9910 	u8         reserved_at_20[0x60];
9911 };
9912 
9913 struct mlx5_ifc_ptys_reg_bits {
9914 	u8         reserved_at_0[0x1];
9915 	u8         an_disable_admin[0x1];
9916 	u8         an_disable_cap[0x1];
9917 	u8         reserved_at_3[0x5];
9918 	u8         local_port[0x8];
9919 	u8         reserved_at_10[0x8];
9920 	u8         plane_ind[0x4];
9921 	u8         reserved_at_1c[0x1];
9922 	u8         proto_mask[0x3];
9923 
9924 	u8         an_status[0x4];
9925 	u8         reserved_at_24[0xc];
9926 	u8         data_rate_oper[0x10];
9927 
9928 	u8         ext_eth_proto_capability[0x20];
9929 
9930 	u8         eth_proto_capability[0x20];
9931 
9932 	u8         ib_link_width_capability[0x10];
9933 	u8         ib_proto_capability[0x10];
9934 
9935 	u8         ext_eth_proto_admin[0x20];
9936 
9937 	u8         eth_proto_admin[0x20];
9938 
9939 	u8         ib_link_width_admin[0x10];
9940 	u8         ib_proto_admin[0x10];
9941 
9942 	u8         ext_eth_proto_oper[0x20];
9943 
9944 	u8         eth_proto_oper[0x20];
9945 
9946 	u8         ib_link_width_oper[0x10];
9947 	u8         ib_proto_oper[0x10];
9948 
9949 	u8         reserved_at_160[0x1c];
9950 	u8         connector_type[0x4];
9951 
9952 	u8         eth_proto_lp_advertise[0x20];
9953 
9954 	u8         reserved_at_1a0[0x60];
9955 };
9956 
9957 struct mlx5_ifc_mlcr_reg_bits {
9958 	u8         reserved_at_0[0x8];
9959 	u8         local_port[0x8];
9960 	u8         reserved_at_10[0x20];
9961 
9962 	u8         beacon_duration[0x10];
9963 	u8         reserved_at_40[0x10];
9964 
9965 	u8         beacon_remain[0x10];
9966 };
9967 
9968 struct mlx5_ifc_ptas_reg_bits {
9969 	u8         reserved_at_0[0x20];
9970 
9971 	u8         algorithm_options[0x10];
9972 	u8         reserved_at_30[0x4];
9973 	u8         repetitions_mode[0x4];
9974 	u8         num_of_repetitions[0x8];
9975 
9976 	u8         grade_version[0x8];
9977 	u8         height_grade_type[0x4];
9978 	u8         phase_grade_type[0x4];
9979 	u8         height_grade_weight[0x8];
9980 	u8         phase_grade_weight[0x8];
9981 
9982 	u8         gisim_measure_bits[0x10];
9983 	u8         adaptive_tap_measure_bits[0x10];
9984 
9985 	u8         ber_bath_high_error_threshold[0x10];
9986 	u8         ber_bath_mid_error_threshold[0x10];
9987 
9988 	u8         ber_bath_low_error_threshold[0x10];
9989 	u8         one_ratio_high_threshold[0x10];
9990 
9991 	u8         one_ratio_high_mid_threshold[0x10];
9992 	u8         one_ratio_low_mid_threshold[0x10];
9993 
9994 	u8         one_ratio_low_threshold[0x10];
9995 	u8         ndeo_error_threshold[0x10];
9996 
9997 	u8         mixer_offset_step_size[0x10];
9998 	u8         reserved_at_110[0x8];
9999 	u8         mix90_phase_for_voltage_bath[0x8];
10000 
10001 	u8         mixer_offset_start[0x10];
10002 	u8         mixer_offset_end[0x10];
10003 
10004 	u8         reserved_at_140[0x15];
10005 	u8         ber_test_time[0xb];
10006 };
10007 
10008 struct mlx5_ifc_pspa_reg_bits {
10009 	u8         swid[0x8];
10010 	u8         local_port[0x8];
10011 	u8         sub_port[0x8];
10012 	u8         reserved_at_18[0x8];
10013 
10014 	u8         reserved_at_20[0x20];
10015 };
10016 
10017 struct mlx5_ifc_pqdr_reg_bits {
10018 	u8         reserved_at_0[0x8];
10019 	u8         local_port[0x8];
10020 	u8         reserved_at_10[0x5];
10021 	u8         prio[0x3];
10022 	u8         reserved_at_18[0x6];
10023 	u8         mode[0x2];
10024 
10025 	u8         reserved_at_20[0x20];
10026 
10027 	u8         reserved_at_40[0x10];
10028 	u8         min_threshold[0x10];
10029 
10030 	u8         reserved_at_60[0x10];
10031 	u8         max_threshold[0x10];
10032 
10033 	u8         reserved_at_80[0x10];
10034 	u8         mark_probability_denominator[0x10];
10035 
10036 	u8         reserved_at_a0[0x60];
10037 };
10038 
10039 struct mlx5_ifc_ppsc_reg_bits {
10040 	u8         reserved_at_0[0x8];
10041 	u8         local_port[0x8];
10042 	u8         reserved_at_10[0x10];
10043 
10044 	u8         reserved_at_20[0x60];
10045 
10046 	u8         reserved_at_80[0x1c];
10047 	u8         wrps_admin[0x4];
10048 
10049 	u8         reserved_at_a0[0x1c];
10050 	u8         wrps_status[0x4];
10051 
10052 	u8         reserved_at_c0[0x8];
10053 	u8         up_threshold[0x8];
10054 	u8         reserved_at_d0[0x8];
10055 	u8         down_threshold[0x8];
10056 
10057 	u8         reserved_at_e0[0x20];
10058 
10059 	u8         reserved_at_100[0x1c];
10060 	u8         srps_admin[0x4];
10061 
10062 	u8         reserved_at_120[0x1c];
10063 	u8         srps_status[0x4];
10064 
10065 	u8         reserved_at_140[0x40];
10066 };
10067 
10068 struct mlx5_ifc_pplr_reg_bits {
10069 	u8         reserved_at_0[0x8];
10070 	u8         local_port[0x8];
10071 	u8         reserved_at_10[0x10];
10072 
10073 	u8         reserved_at_20[0x8];
10074 	u8         lb_cap[0x8];
10075 	u8         reserved_at_30[0x8];
10076 	u8         lb_en[0x8];
10077 };
10078 
10079 struct mlx5_ifc_pplm_reg_bits {
10080 	u8         reserved_at_0[0x8];
10081 	u8	   local_port[0x8];
10082 	u8	   reserved_at_10[0x10];
10083 
10084 	u8	   reserved_at_20[0x20];
10085 
10086 	u8	   port_profile_mode[0x8];
10087 	u8	   static_port_profile[0x8];
10088 	u8	   active_port_profile[0x8];
10089 	u8	   reserved_at_58[0x8];
10090 
10091 	u8	   retransmission_active[0x8];
10092 	u8	   fec_mode_active[0x18];
10093 
10094 	u8	   rs_fec_correction_bypass_cap[0x4];
10095 	u8	   reserved_at_84[0x8];
10096 	u8	   fec_override_cap_56g[0x4];
10097 	u8	   fec_override_cap_100g[0x4];
10098 	u8	   fec_override_cap_50g[0x4];
10099 	u8	   fec_override_cap_25g[0x4];
10100 	u8	   fec_override_cap_10g_40g[0x4];
10101 
10102 	u8	   rs_fec_correction_bypass_admin[0x4];
10103 	u8	   reserved_at_a4[0x8];
10104 	u8	   fec_override_admin_56g[0x4];
10105 	u8	   fec_override_admin_100g[0x4];
10106 	u8	   fec_override_admin_50g[0x4];
10107 	u8	   fec_override_admin_25g[0x4];
10108 	u8	   fec_override_admin_10g_40g[0x4];
10109 
10110 	u8         fec_override_cap_400g_8x[0x10];
10111 	u8         fec_override_cap_200g_4x[0x10];
10112 
10113 	u8         fec_override_cap_100g_2x[0x10];
10114 	u8         fec_override_cap_50g_1x[0x10];
10115 
10116 	u8         fec_override_admin_400g_8x[0x10];
10117 	u8         fec_override_admin_200g_4x[0x10];
10118 
10119 	u8         fec_override_admin_100g_2x[0x10];
10120 	u8         fec_override_admin_50g_1x[0x10];
10121 
10122 	u8         fec_override_cap_800g_8x[0x10];
10123 	u8         fec_override_cap_400g_4x[0x10];
10124 
10125 	u8         fec_override_cap_200g_2x[0x10];
10126 	u8         fec_override_cap_100g_1x[0x10];
10127 
10128 	u8         reserved_at_180[0xa0];
10129 
10130 	u8         fec_override_admin_800g_8x[0x10];
10131 	u8         fec_override_admin_400g_4x[0x10];
10132 
10133 	u8         fec_override_admin_200g_2x[0x10];
10134 	u8         fec_override_admin_100g_1x[0x10];
10135 
10136 	u8         reserved_at_260[0x20];
10137 };
10138 
10139 struct mlx5_ifc_ppcnt_reg_bits {
10140 	u8         swid[0x8];
10141 	u8         local_port[0x8];
10142 	u8         pnat[0x2];
10143 	u8         reserved_at_12[0x8];
10144 	u8         grp[0x6];
10145 
10146 	u8         clr[0x1];
10147 	u8         reserved_at_21[0x13];
10148 	u8         plane_ind[0x4];
10149 	u8         reserved_at_38[0x3];
10150 	u8         prio_tc[0x5];
10151 
10152 	union mlx5_ifc_eth_cntrs_grp_data_layout_auto_bits counter_set;
10153 };
10154 
10155 struct mlx5_ifc_mpein_reg_bits {
10156 	u8         reserved_at_0[0x2];
10157 	u8         depth[0x6];
10158 	u8         pcie_index[0x8];
10159 	u8         node[0x8];
10160 	u8         reserved_at_18[0x8];
10161 
10162 	u8         capability_mask[0x20];
10163 
10164 	u8         reserved_at_40[0x8];
10165 	u8         link_width_enabled[0x8];
10166 	u8         link_speed_enabled[0x10];
10167 
10168 	u8         lane0_physical_position[0x8];
10169 	u8         link_width_active[0x8];
10170 	u8         link_speed_active[0x10];
10171 
10172 	u8         num_of_pfs[0x10];
10173 	u8         num_of_vfs[0x10];
10174 
10175 	u8         bdf0[0x10];
10176 	u8         reserved_at_b0[0x10];
10177 
10178 	u8         max_read_request_size[0x4];
10179 	u8         max_payload_size[0x4];
10180 	u8         reserved_at_c8[0x5];
10181 	u8         pwr_status[0x3];
10182 	u8         port_type[0x4];
10183 	u8         reserved_at_d4[0xb];
10184 	u8         lane_reversal[0x1];
10185 
10186 	u8         reserved_at_e0[0x14];
10187 	u8         pci_power[0xc];
10188 
10189 	u8         reserved_at_100[0x20];
10190 
10191 	u8         device_status[0x10];
10192 	u8         port_state[0x8];
10193 	u8         reserved_at_138[0x8];
10194 
10195 	u8         reserved_at_140[0x10];
10196 	u8         receiver_detect_result[0x10];
10197 
10198 	u8         reserved_at_160[0x20];
10199 };
10200 
10201 struct mlx5_ifc_mpcnt_reg_bits {
10202 	u8         reserved_at_0[0x8];
10203 	u8         pcie_index[0x8];
10204 	u8         reserved_at_10[0xa];
10205 	u8         grp[0x6];
10206 
10207 	u8         clr[0x1];
10208 	u8         reserved_at_21[0x1f];
10209 
10210 	union mlx5_ifc_pcie_cntrs_grp_data_layout_auto_bits counter_set;
10211 };
10212 
10213 struct mlx5_ifc_ppad_reg_bits {
10214 	u8         reserved_at_0[0x3];
10215 	u8         single_mac[0x1];
10216 	u8         reserved_at_4[0x4];
10217 	u8         local_port[0x8];
10218 	u8         mac_47_32[0x10];
10219 
10220 	u8         mac_31_0[0x20];
10221 
10222 	u8         reserved_at_40[0x40];
10223 };
10224 
10225 struct mlx5_ifc_pmtu_reg_bits {
10226 	u8         reserved_at_0[0x8];
10227 	u8         local_port[0x8];
10228 	u8         reserved_at_10[0x10];
10229 
10230 	u8         max_mtu[0x10];
10231 	u8         reserved_at_30[0x10];
10232 
10233 	u8         admin_mtu[0x10];
10234 	u8         reserved_at_50[0x10];
10235 
10236 	u8         oper_mtu[0x10];
10237 	u8         reserved_at_70[0x10];
10238 };
10239 
10240 struct mlx5_ifc_pmpr_reg_bits {
10241 	u8         reserved_at_0[0x8];
10242 	u8         module[0x8];
10243 	u8         reserved_at_10[0x10];
10244 
10245 	u8         reserved_at_20[0x18];
10246 	u8         attenuation_5g[0x8];
10247 
10248 	u8         reserved_at_40[0x18];
10249 	u8         attenuation_7g[0x8];
10250 
10251 	u8         reserved_at_60[0x18];
10252 	u8         attenuation_12g[0x8];
10253 };
10254 
10255 struct mlx5_ifc_pmpe_reg_bits {
10256 	u8         reserved_at_0[0x8];
10257 	u8         module[0x8];
10258 	u8         reserved_at_10[0xc];
10259 	u8         module_status[0x4];
10260 
10261 	u8         reserved_at_20[0x60];
10262 };
10263 
10264 struct mlx5_ifc_pmpc_reg_bits {
10265 	u8         module_state_updated[32][0x8];
10266 };
10267 
10268 struct mlx5_ifc_pmlpn_reg_bits {
10269 	u8         reserved_at_0[0x4];
10270 	u8         mlpn_status[0x4];
10271 	u8         local_port[0x8];
10272 	u8         reserved_at_10[0x10];
10273 
10274 	u8         e[0x1];
10275 	u8         reserved_at_21[0x1f];
10276 };
10277 
10278 struct mlx5_ifc_pmlp_reg_bits {
10279 	u8         rxtx[0x1];
10280 	u8         reserved_at_1[0x7];
10281 	u8         local_port[0x8];
10282 	u8         reserved_at_10[0x8];
10283 	u8         width[0x8];
10284 
10285 	u8         lane0_module_mapping[0x20];
10286 
10287 	u8         lane1_module_mapping[0x20];
10288 
10289 	u8         lane2_module_mapping[0x20];
10290 
10291 	u8         lane3_module_mapping[0x20];
10292 
10293 	u8         reserved_at_a0[0x160];
10294 };
10295 
10296 struct mlx5_ifc_pmaos_reg_bits {
10297 	u8         reserved_at_0[0x8];
10298 	u8         module[0x8];
10299 	u8         reserved_at_10[0x4];
10300 	u8         admin_status[0x4];
10301 	u8         reserved_at_18[0x4];
10302 	u8         oper_status[0x4];
10303 
10304 	u8         ase[0x1];
10305 	u8         ee[0x1];
10306 	u8         reserved_at_22[0x1c];
10307 	u8         e[0x2];
10308 
10309 	u8         reserved_at_40[0x40];
10310 };
10311 
10312 struct mlx5_ifc_plpc_reg_bits {
10313 	u8         reserved_at_0[0x4];
10314 	u8         profile_id[0xc];
10315 	u8         reserved_at_10[0x4];
10316 	u8         proto_mask[0x4];
10317 	u8         reserved_at_18[0x8];
10318 
10319 	u8         reserved_at_20[0x10];
10320 	u8         lane_speed[0x10];
10321 
10322 	u8         reserved_at_40[0x17];
10323 	u8         lpbf[0x1];
10324 	u8         fec_mode_policy[0x8];
10325 
10326 	u8         retransmission_capability[0x8];
10327 	u8         fec_mode_capability[0x18];
10328 
10329 	u8         retransmission_support_admin[0x8];
10330 	u8         fec_mode_support_admin[0x18];
10331 
10332 	u8         retransmission_request_admin[0x8];
10333 	u8         fec_mode_request_admin[0x18];
10334 
10335 	u8         reserved_at_c0[0x80];
10336 };
10337 
10338 struct mlx5_ifc_plib_reg_bits {
10339 	u8         reserved_at_0[0x8];
10340 	u8         local_port[0x8];
10341 	u8         reserved_at_10[0x8];
10342 	u8         ib_port[0x8];
10343 
10344 	u8         reserved_at_20[0x60];
10345 };
10346 
10347 struct mlx5_ifc_plbf_reg_bits {
10348 	u8         reserved_at_0[0x8];
10349 	u8         local_port[0x8];
10350 	u8         reserved_at_10[0xd];
10351 	u8         lbf_mode[0x3];
10352 
10353 	u8         reserved_at_20[0x20];
10354 };
10355 
10356 struct mlx5_ifc_pipg_reg_bits {
10357 	u8         reserved_at_0[0x8];
10358 	u8         local_port[0x8];
10359 	u8         reserved_at_10[0x10];
10360 
10361 	u8         dic[0x1];
10362 	u8         reserved_at_21[0x19];
10363 	u8         ipg[0x4];
10364 	u8         reserved_at_3e[0x2];
10365 };
10366 
10367 struct mlx5_ifc_pifr_reg_bits {
10368 	u8         reserved_at_0[0x8];
10369 	u8         local_port[0x8];
10370 	u8         reserved_at_10[0x10];
10371 
10372 	u8         reserved_at_20[0xe0];
10373 
10374 	u8         port_filter[8][0x20];
10375 
10376 	u8         port_filter_update_en[8][0x20];
10377 };
10378 
10379 struct mlx5_ifc_pfcc_reg_bits {
10380 	u8         reserved_at_0[0x8];
10381 	u8         local_port[0x8];
10382 	u8         reserved_at_10[0xb];
10383 	u8         ppan_mask_n[0x1];
10384 	u8         minor_stall_mask[0x1];
10385 	u8         critical_stall_mask[0x1];
10386 	u8         reserved_at_1e[0x2];
10387 
10388 	u8         ppan[0x4];
10389 	u8         reserved_at_24[0x4];
10390 	u8         prio_mask_tx[0x8];
10391 	u8         reserved_at_30[0x8];
10392 	u8         prio_mask_rx[0x8];
10393 
10394 	u8         pptx[0x1];
10395 	u8         aptx[0x1];
10396 	u8         pptx_mask_n[0x1];
10397 	u8         reserved_at_43[0x5];
10398 	u8         pfctx[0x8];
10399 	u8         reserved_at_50[0x10];
10400 
10401 	u8         pprx[0x1];
10402 	u8         aprx[0x1];
10403 	u8         pprx_mask_n[0x1];
10404 	u8         reserved_at_63[0x5];
10405 	u8         pfcrx[0x8];
10406 	u8         reserved_at_70[0x10];
10407 
10408 	u8         device_stall_minor_watermark[0x10];
10409 	u8         device_stall_critical_watermark[0x10];
10410 
10411 	u8         reserved_at_a0[0x60];
10412 };
10413 
10414 struct mlx5_ifc_pelc_reg_bits {
10415 	u8         op[0x4];
10416 	u8         reserved_at_4[0x4];
10417 	u8         local_port[0x8];
10418 	u8         reserved_at_10[0x10];
10419 
10420 	u8         op_admin[0x8];
10421 	u8         op_capability[0x8];
10422 	u8         op_request[0x8];
10423 	u8         op_active[0x8];
10424 
10425 	u8         admin[0x40];
10426 
10427 	u8         capability[0x40];
10428 
10429 	u8         request[0x40];
10430 
10431 	u8         active[0x40];
10432 
10433 	u8         reserved_at_140[0x80];
10434 };
10435 
10436 struct mlx5_ifc_peir_reg_bits {
10437 	u8         reserved_at_0[0x8];
10438 	u8         local_port[0x8];
10439 	u8         reserved_at_10[0x10];
10440 
10441 	u8         reserved_at_20[0xc];
10442 	u8         error_count[0x4];
10443 	u8         reserved_at_30[0x10];
10444 
10445 	u8         reserved_at_40[0xc];
10446 	u8         lane[0x4];
10447 	u8         reserved_at_50[0x8];
10448 	u8         error_type[0x8];
10449 };
10450 
10451 struct mlx5_ifc_mpegc_reg_bits {
10452 	u8         reserved_at_0[0x30];
10453 	u8         field_select[0x10];
10454 
10455 	u8         tx_overflow_sense[0x1];
10456 	u8         mark_cqe[0x1];
10457 	u8         mark_cnp[0x1];
10458 	u8         reserved_at_43[0x1b];
10459 	u8         tx_lossy_overflow_oper[0x2];
10460 
10461 	u8         reserved_at_60[0x100];
10462 };
10463 
10464 struct mlx5_ifc_mpir_reg_bits {
10465 	u8         sdm[0x1];
10466 	u8         reserved_at_1[0x1b];
10467 	u8         host_buses[0x4];
10468 
10469 	u8         reserved_at_20[0x20];
10470 
10471 	u8         local_port[0x8];
10472 	u8         reserved_at_28[0x18];
10473 
10474 	u8         reserved_at_60[0x20];
10475 };
10476 
10477 enum {
10478 	MLX5_MTUTC_FREQ_ADJ_UNITS_PPB          = 0x0,
10479 	MLX5_MTUTC_FREQ_ADJ_UNITS_SCALED_PPM   = 0x1,
10480 };
10481 
10482 enum {
10483 	MLX5_MTUTC_OPERATION_SET_TIME_IMMEDIATE   = 0x1,
10484 	MLX5_MTUTC_OPERATION_ADJUST_TIME          = 0x2,
10485 	MLX5_MTUTC_OPERATION_ADJUST_FREQ_UTC      = 0x3,
10486 };
10487 
10488 struct mlx5_ifc_mtutc_reg_bits {
10489 	u8         reserved_at_0[0x5];
10490 	u8         freq_adj_units[0x3];
10491 	u8         reserved_at_8[0x3];
10492 	u8         log_max_freq_adjustment[0x5];
10493 
10494 	u8         reserved_at_10[0xc];
10495 	u8         operation[0x4];
10496 
10497 	u8         freq_adjustment[0x20];
10498 
10499 	u8         reserved_at_40[0x40];
10500 
10501 	u8         utc_sec[0x20];
10502 
10503 	u8         reserved_at_a0[0x2];
10504 	u8         utc_nsec[0x1e];
10505 
10506 	u8         time_adjustment[0x20];
10507 };
10508 
10509 struct mlx5_ifc_pcam_enhanced_features_bits {
10510 	u8         reserved_at_0[0x48];
10511 	u8         fec_100G_per_lane_in_pplm[0x1];
10512 	u8         reserved_at_49[0x1f];
10513 	u8         fec_50G_per_lane_in_pplm[0x1];
10514 	u8         reserved_at_69[0x4];
10515 	u8         rx_icrc_encapsulated_counter[0x1];
10516 	u8	   reserved_at_6e[0x4];
10517 	u8         ptys_extended_ethernet[0x1];
10518 	u8	   reserved_at_73[0x3];
10519 	u8         pfcc_mask[0x1];
10520 	u8         reserved_at_77[0x3];
10521 	u8         per_lane_error_counters[0x1];
10522 	u8         rx_buffer_fullness_counters[0x1];
10523 	u8         ptys_connector_type[0x1];
10524 	u8         reserved_at_7d[0x1];
10525 	u8         ppcnt_discard_group[0x1];
10526 	u8         ppcnt_statistical_group[0x1];
10527 };
10528 
10529 struct mlx5_ifc_pcam_regs_5000_to_507f_bits {
10530 	u8         port_access_reg_cap_mask_127_to_96[0x20];
10531 	u8         port_access_reg_cap_mask_95_to_64[0x20];
10532 
10533 	u8         port_access_reg_cap_mask_63_to_36[0x1c];
10534 	u8         pplm[0x1];
10535 	u8         port_access_reg_cap_mask_34_to_32[0x3];
10536 
10537 	u8         port_access_reg_cap_mask_31_to_13[0x13];
10538 	u8         pbmc[0x1];
10539 	u8         pptb[0x1];
10540 	u8         port_access_reg_cap_mask_10_to_09[0x2];
10541 	u8         ppcnt[0x1];
10542 	u8         port_access_reg_cap_mask_07_to_00[0x8];
10543 };
10544 
10545 struct mlx5_ifc_pcam_reg_bits {
10546 	u8         reserved_at_0[0x8];
10547 	u8         feature_group[0x8];
10548 	u8         reserved_at_10[0x8];
10549 	u8         access_reg_group[0x8];
10550 
10551 	u8         reserved_at_20[0x20];
10552 
10553 	union {
10554 		struct mlx5_ifc_pcam_regs_5000_to_507f_bits regs_5000_to_507f;
10555 		u8         reserved_at_0[0x80];
10556 	} port_access_reg_cap_mask;
10557 
10558 	u8         reserved_at_c0[0x80];
10559 
10560 	union {
10561 		struct mlx5_ifc_pcam_enhanced_features_bits enhanced_features;
10562 		u8         reserved_at_0[0x80];
10563 	} feature_cap_mask;
10564 
10565 	u8         reserved_at_1c0[0xc0];
10566 };
10567 
10568 struct mlx5_ifc_mcam_enhanced_features_bits {
10569 	u8         reserved_at_0[0x50];
10570 	u8         mtutc_freq_adj_units[0x1];
10571 	u8         mtutc_time_adjustment_extended_range[0x1];
10572 	u8         reserved_at_52[0xb];
10573 	u8         mcia_32dwords[0x1];
10574 	u8         out_pulse_duration_ns[0x1];
10575 	u8         npps_period[0x1];
10576 	u8         reserved_at_60[0xa];
10577 	u8         reset_state[0x1];
10578 	u8         ptpcyc2realtime_modify[0x1];
10579 	u8         reserved_at_6c[0x2];
10580 	u8         pci_status_and_power[0x1];
10581 	u8         reserved_at_6f[0x5];
10582 	u8         mark_tx_action_cnp[0x1];
10583 	u8         mark_tx_action_cqe[0x1];
10584 	u8         dynamic_tx_overflow[0x1];
10585 	u8         reserved_at_77[0x4];
10586 	u8         pcie_outbound_stalled[0x1];
10587 	u8         tx_overflow_buffer_pkt[0x1];
10588 	u8         mtpps_enh_out_per_adj[0x1];
10589 	u8         mtpps_fs[0x1];
10590 	u8         pcie_performance_group[0x1];
10591 };
10592 
10593 struct mlx5_ifc_mcam_access_reg_bits {
10594 	u8         reserved_at_0[0x1c];
10595 	u8         mcda[0x1];
10596 	u8         mcc[0x1];
10597 	u8         mcqi[0x1];
10598 	u8         mcqs[0x1];
10599 
10600 	u8         regs_95_to_90[0x6];
10601 	u8         mpir[0x1];
10602 	u8         regs_88_to_87[0x2];
10603 	u8         mpegc[0x1];
10604 	u8         mtutc[0x1];
10605 	u8         regs_84_to_68[0x11];
10606 	u8         tracer_registers[0x4];
10607 
10608 	u8         regs_63_to_46[0x12];
10609 	u8         mrtc[0x1];
10610 	u8         regs_44_to_41[0x4];
10611 	u8         mfrl[0x1];
10612 	u8         regs_39_to_32[0x8];
10613 
10614 	u8         regs_31_to_11[0x15];
10615 	u8         mtmp[0x1];
10616 	u8         regs_9_to_0[0xa];
10617 };
10618 
10619 struct mlx5_ifc_mcam_access_reg_bits1 {
10620 	u8         regs_127_to_96[0x20];
10621 
10622 	u8         regs_95_to_64[0x20];
10623 
10624 	u8         regs_63_to_32[0x20];
10625 
10626 	u8         regs_31_to_0[0x20];
10627 };
10628 
10629 struct mlx5_ifc_mcam_access_reg_bits2 {
10630 	u8         regs_127_to_99[0x1d];
10631 	u8         mirc[0x1];
10632 	u8         regs_97_to_96[0x2];
10633 
10634 	u8         regs_95_to_87[0x09];
10635 	u8         synce_registers[0x2];
10636 	u8         regs_84_to_64[0x15];
10637 
10638 	u8         regs_63_to_32[0x20];
10639 
10640 	u8         regs_31_to_0[0x20];
10641 };
10642 
10643 struct mlx5_ifc_mcam_access_reg_bits3 {
10644 	u8         regs_127_to_96[0x20];
10645 
10646 	u8         regs_95_to_64[0x20];
10647 
10648 	u8         regs_63_to_32[0x20];
10649 
10650 	u8         regs_31_to_2[0x1e];
10651 	u8         mtctr[0x1];
10652 	u8         mtptm[0x1];
10653 };
10654 
10655 struct mlx5_ifc_mcam_reg_bits {
10656 	u8         reserved_at_0[0x8];
10657 	u8         feature_group[0x8];
10658 	u8         reserved_at_10[0x8];
10659 	u8         access_reg_group[0x8];
10660 
10661 	u8         reserved_at_20[0x20];
10662 
10663 	union {
10664 		struct mlx5_ifc_mcam_access_reg_bits access_regs;
10665 		struct mlx5_ifc_mcam_access_reg_bits1 access_regs1;
10666 		struct mlx5_ifc_mcam_access_reg_bits2 access_regs2;
10667 		struct mlx5_ifc_mcam_access_reg_bits3 access_regs3;
10668 		u8         reserved_at_0[0x80];
10669 	} mng_access_reg_cap_mask;
10670 
10671 	u8         reserved_at_c0[0x80];
10672 
10673 	union {
10674 		struct mlx5_ifc_mcam_enhanced_features_bits enhanced_features;
10675 		u8         reserved_at_0[0x80];
10676 	} mng_feature_cap_mask;
10677 
10678 	u8         reserved_at_1c0[0x80];
10679 };
10680 
10681 struct mlx5_ifc_qcam_access_reg_cap_mask {
10682 	u8         qcam_access_reg_cap_mask_127_to_20[0x6C];
10683 	u8         qpdpm[0x1];
10684 	u8         qcam_access_reg_cap_mask_18_to_4[0x0F];
10685 	u8         qdpm[0x1];
10686 	u8         qpts[0x1];
10687 	u8         qcap[0x1];
10688 	u8         qcam_access_reg_cap_mask_0[0x1];
10689 };
10690 
10691 struct mlx5_ifc_qcam_qos_feature_cap_mask {
10692 	u8         qcam_qos_feature_cap_mask_127_to_1[0x7F];
10693 	u8         qpts_trust_both[0x1];
10694 };
10695 
10696 struct mlx5_ifc_qcam_reg_bits {
10697 	u8         reserved_at_0[0x8];
10698 	u8         feature_group[0x8];
10699 	u8         reserved_at_10[0x8];
10700 	u8         access_reg_group[0x8];
10701 	u8         reserved_at_20[0x20];
10702 
10703 	union {
10704 		struct mlx5_ifc_qcam_access_reg_cap_mask reg_cap;
10705 		u8  reserved_at_0[0x80];
10706 	} qos_access_reg_cap_mask;
10707 
10708 	u8         reserved_at_c0[0x80];
10709 
10710 	union {
10711 		struct mlx5_ifc_qcam_qos_feature_cap_mask feature_cap;
10712 		u8  reserved_at_0[0x80];
10713 	} qos_feature_cap_mask;
10714 
10715 	u8         reserved_at_1c0[0x80];
10716 };
10717 
10718 struct mlx5_ifc_core_dump_reg_bits {
10719 	u8         reserved_at_0[0x18];
10720 	u8         core_dump_type[0x8];
10721 
10722 	u8         reserved_at_20[0x30];
10723 	u8         vhca_id[0x10];
10724 
10725 	u8         reserved_at_60[0x8];
10726 	u8         qpn[0x18];
10727 	u8         reserved_at_80[0x180];
10728 };
10729 
10730 struct mlx5_ifc_pcap_reg_bits {
10731 	u8         reserved_at_0[0x8];
10732 	u8         local_port[0x8];
10733 	u8         reserved_at_10[0x10];
10734 
10735 	u8         port_capability_mask[4][0x20];
10736 };
10737 
10738 struct mlx5_ifc_paos_reg_bits {
10739 	u8         swid[0x8];
10740 	u8         local_port[0x8];
10741 	u8         reserved_at_10[0x4];
10742 	u8         admin_status[0x4];
10743 	u8         reserved_at_18[0x4];
10744 	u8         oper_status[0x4];
10745 
10746 	u8         ase[0x1];
10747 	u8         ee[0x1];
10748 	u8         reserved_at_22[0x1c];
10749 	u8         e[0x2];
10750 
10751 	u8         reserved_at_40[0x40];
10752 };
10753 
10754 struct mlx5_ifc_pamp_reg_bits {
10755 	u8         reserved_at_0[0x8];
10756 	u8         opamp_group[0x8];
10757 	u8         reserved_at_10[0xc];
10758 	u8         opamp_group_type[0x4];
10759 
10760 	u8         start_index[0x10];
10761 	u8         reserved_at_30[0x4];
10762 	u8         num_of_indices[0xc];
10763 
10764 	u8         index_data[18][0x10];
10765 };
10766 
10767 struct mlx5_ifc_pcmr_reg_bits {
10768 	u8         reserved_at_0[0x8];
10769 	u8         local_port[0x8];
10770 	u8         reserved_at_10[0x10];
10771 
10772 	u8         entropy_force_cap[0x1];
10773 	u8         entropy_calc_cap[0x1];
10774 	u8         entropy_gre_calc_cap[0x1];
10775 	u8         reserved_at_23[0xf];
10776 	u8         rx_ts_over_crc_cap[0x1];
10777 	u8         reserved_at_33[0xb];
10778 	u8         fcs_cap[0x1];
10779 	u8         reserved_at_3f[0x1];
10780 
10781 	u8         entropy_force[0x1];
10782 	u8         entropy_calc[0x1];
10783 	u8         entropy_gre_calc[0x1];
10784 	u8         reserved_at_43[0xf];
10785 	u8         rx_ts_over_crc[0x1];
10786 	u8         reserved_at_53[0xb];
10787 	u8         fcs_chk[0x1];
10788 	u8         reserved_at_5f[0x1];
10789 };
10790 
10791 struct mlx5_ifc_lane_2_module_mapping_bits {
10792 	u8         reserved_at_0[0x4];
10793 	u8         rx_lane[0x4];
10794 	u8         reserved_at_8[0x4];
10795 	u8         tx_lane[0x4];
10796 	u8         reserved_at_10[0x8];
10797 	u8         module[0x8];
10798 };
10799 
10800 struct mlx5_ifc_bufferx_reg_bits {
10801 	u8         reserved_at_0[0x6];
10802 	u8         lossy[0x1];
10803 	u8         epsb[0x1];
10804 	u8         reserved_at_8[0x8];
10805 	u8         size[0x10];
10806 
10807 	u8         xoff_threshold[0x10];
10808 	u8         xon_threshold[0x10];
10809 };
10810 
10811 struct mlx5_ifc_set_node_in_bits {
10812 	u8         node_description[64][0x8];
10813 };
10814 
10815 struct mlx5_ifc_register_power_settings_bits {
10816 	u8         reserved_at_0[0x18];
10817 	u8         power_settings_level[0x8];
10818 
10819 	u8         reserved_at_20[0x60];
10820 };
10821 
10822 struct mlx5_ifc_register_host_endianness_bits {
10823 	u8         he[0x1];
10824 	u8         reserved_at_1[0x1f];
10825 
10826 	u8         reserved_at_20[0x60];
10827 };
10828 
10829 struct mlx5_ifc_umr_pointer_desc_argument_bits {
10830 	u8         reserved_at_0[0x20];
10831 
10832 	u8         mkey[0x20];
10833 
10834 	u8         addressh_63_32[0x20];
10835 
10836 	u8         addressl_31_0[0x20];
10837 };
10838 
10839 struct mlx5_ifc_ud_adrs_vector_bits {
10840 	u8         dc_key[0x40];
10841 
10842 	u8         ext[0x1];
10843 	u8         reserved_at_41[0x7];
10844 	u8         destination_qp_dct[0x18];
10845 
10846 	u8         static_rate[0x4];
10847 	u8         sl_eth_prio[0x4];
10848 	u8         fl[0x1];
10849 	u8         mlid[0x7];
10850 	u8         rlid_udp_sport[0x10];
10851 
10852 	u8         reserved_at_80[0x20];
10853 
10854 	u8         rmac_47_16[0x20];
10855 
10856 	u8         rmac_15_0[0x10];
10857 	u8         tclass[0x8];
10858 	u8         hop_limit[0x8];
10859 
10860 	u8         reserved_at_e0[0x1];
10861 	u8         grh[0x1];
10862 	u8         reserved_at_e2[0x2];
10863 	u8         src_addr_index[0x8];
10864 	u8         flow_label[0x14];
10865 
10866 	u8         rgid_rip[16][0x8];
10867 };
10868 
10869 struct mlx5_ifc_pages_req_event_bits {
10870 	u8         reserved_at_0[0x10];
10871 	u8         function_id[0x10];
10872 
10873 	u8         num_pages[0x20];
10874 
10875 	u8         reserved_at_40[0xa0];
10876 };
10877 
10878 struct mlx5_ifc_eqe_bits {
10879 	u8         reserved_at_0[0x8];
10880 	u8         event_type[0x8];
10881 	u8         reserved_at_10[0x8];
10882 	u8         event_sub_type[0x8];
10883 
10884 	u8         reserved_at_20[0xe0];
10885 
10886 	union mlx5_ifc_event_auto_bits event_data;
10887 
10888 	u8         reserved_at_1e0[0x10];
10889 	u8         signature[0x8];
10890 	u8         reserved_at_1f8[0x7];
10891 	u8         owner[0x1];
10892 };
10893 
10894 enum {
10895 	MLX5_CMD_QUEUE_ENTRY_TYPE_PCIE_CMD_IF_TRANSPORT  = 0x7,
10896 };
10897 
10898 struct mlx5_ifc_cmd_queue_entry_bits {
10899 	u8         type[0x8];
10900 	u8         reserved_at_8[0x18];
10901 
10902 	u8         input_length[0x20];
10903 
10904 	u8         input_mailbox_pointer_63_32[0x20];
10905 
10906 	u8         input_mailbox_pointer_31_9[0x17];
10907 	u8         reserved_at_77[0x9];
10908 
10909 	u8         command_input_inline_data[16][0x8];
10910 
10911 	u8         command_output_inline_data[16][0x8];
10912 
10913 	u8         output_mailbox_pointer_63_32[0x20];
10914 
10915 	u8         output_mailbox_pointer_31_9[0x17];
10916 	u8         reserved_at_1b7[0x9];
10917 
10918 	u8         output_length[0x20];
10919 
10920 	u8         token[0x8];
10921 	u8         signature[0x8];
10922 	u8         reserved_at_1f0[0x8];
10923 	u8         status[0x7];
10924 	u8         ownership[0x1];
10925 };
10926 
10927 struct mlx5_ifc_cmd_out_bits {
10928 	u8         status[0x8];
10929 	u8         reserved_at_8[0x18];
10930 
10931 	u8         syndrome[0x20];
10932 
10933 	u8         command_output[0x20];
10934 };
10935 
10936 struct mlx5_ifc_cmd_in_bits {
10937 	u8         opcode[0x10];
10938 	u8         reserved_at_10[0x10];
10939 
10940 	u8         reserved_at_20[0x10];
10941 	u8         op_mod[0x10];
10942 
10943 	u8         command[][0x20];
10944 };
10945 
10946 struct mlx5_ifc_cmd_if_box_bits {
10947 	u8         mailbox_data[512][0x8];
10948 
10949 	u8         reserved_at_1000[0x180];
10950 
10951 	u8         next_pointer_63_32[0x20];
10952 
10953 	u8         next_pointer_31_10[0x16];
10954 	u8         reserved_at_11b6[0xa];
10955 
10956 	u8         block_number[0x20];
10957 
10958 	u8         reserved_at_11e0[0x8];
10959 	u8         token[0x8];
10960 	u8         ctrl_signature[0x8];
10961 	u8         signature[0x8];
10962 };
10963 
10964 struct mlx5_ifc_mtt_bits {
10965 	u8         ptag_63_32[0x20];
10966 
10967 	u8         ptag_31_8[0x18];
10968 	u8         reserved_at_38[0x6];
10969 	u8         wr_en[0x1];
10970 	u8         rd_en[0x1];
10971 };
10972 
10973 struct mlx5_ifc_query_wol_rol_out_bits {
10974 	u8         status[0x8];
10975 	u8         reserved_at_8[0x18];
10976 
10977 	u8         syndrome[0x20];
10978 
10979 	u8         reserved_at_40[0x10];
10980 	u8         rol_mode[0x8];
10981 	u8         wol_mode[0x8];
10982 
10983 	u8         reserved_at_60[0x20];
10984 };
10985 
10986 struct mlx5_ifc_query_wol_rol_in_bits {
10987 	u8         opcode[0x10];
10988 	u8         reserved_at_10[0x10];
10989 
10990 	u8         reserved_at_20[0x10];
10991 	u8         op_mod[0x10];
10992 
10993 	u8         reserved_at_40[0x40];
10994 };
10995 
10996 struct mlx5_ifc_set_wol_rol_out_bits {
10997 	u8         status[0x8];
10998 	u8         reserved_at_8[0x18];
10999 
11000 	u8         syndrome[0x20];
11001 
11002 	u8         reserved_at_40[0x40];
11003 };
11004 
11005 struct mlx5_ifc_set_wol_rol_in_bits {
11006 	u8         opcode[0x10];
11007 	u8         reserved_at_10[0x10];
11008 
11009 	u8         reserved_at_20[0x10];
11010 	u8         op_mod[0x10];
11011 
11012 	u8         rol_mode_valid[0x1];
11013 	u8         wol_mode_valid[0x1];
11014 	u8         reserved_at_42[0xe];
11015 	u8         rol_mode[0x8];
11016 	u8         wol_mode[0x8];
11017 
11018 	u8         reserved_at_60[0x20];
11019 };
11020 
11021 enum {
11022 	MLX5_INITIAL_SEG_NIC_INTERFACE_FULL_DRIVER  = 0x0,
11023 	MLX5_INITIAL_SEG_NIC_INTERFACE_DISABLED     = 0x1,
11024 	MLX5_INITIAL_SEG_NIC_INTERFACE_NO_DRAM_NIC  = 0x2,
11025 	MLX5_INITIAL_SEG_NIC_INTERFACE_SW_RESET     = 0x7,
11026 };
11027 
11028 enum {
11029 	MLX5_INITIAL_SEG_NIC_INTERFACE_SUPPORTED_FULL_DRIVER  = 0x0,
11030 	MLX5_INITIAL_SEG_NIC_INTERFACE_SUPPORTED_DISABLED     = 0x1,
11031 	MLX5_INITIAL_SEG_NIC_INTERFACE_SUPPORTED_NO_DRAM_NIC  = 0x2,
11032 };
11033 
11034 enum {
11035 	MLX5_INITIAL_SEG_HEALTH_SYNDROME_FW_INTERNAL_ERR              = 0x1,
11036 	MLX5_INITIAL_SEG_HEALTH_SYNDROME_DEAD_IRISC                   = 0x7,
11037 	MLX5_INITIAL_SEG_HEALTH_SYNDROME_HW_FATAL_ERR                 = 0x8,
11038 	MLX5_INITIAL_SEG_HEALTH_SYNDROME_FW_CRC_ERR                   = 0x9,
11039 	MLX5_INITIAL_SEG_HEALTH_SYNDROME_ICM_FETCH_PCI_ERR            = 0xa,
11040 	MLX5_INITIAL_SEG_HEALTH_SYNDROME_ICM_PAGE_ERR                 = 0xb,
11041 	MLX5_INITIAL_SEG_HEALTH_SYNDROME_ASYNCHRONOUS_EQ_BUF_OVERRUN  = 0xc,
11042 	MLX5_INITIAL_SEG_HEALTH_SYNDROME_EQ_IN_ERR                    = 0xd,
11043 	MLX5_INITIAL_SEG_HEALTH_SYNDROME_EQ_INV                       = 0xe,
11044 	MLX5_INITIAL_SEG_HEALTH_SYNDROME_FFSER_ERR                    = 0xf,
11045 	MLX5_INITIAL_SEG_HEALTH_SYNDROME_HIGH_TEMP_ERR                = 0x10,
11046 	MLX5_INITIAL_SEG_HEALTH_SYNDROME_ICM_PCI_POISONED_ERR         = 0x12,
11047 };
11048 
11049 struct mlx5_ifc_initial_seg_bits {
11050 	u8         fw_rev_minor[0x10];
11051 	u8         fw_rev_major[0x10];
11052 
11053 	u8         cmd_interface_rev[0x10];
11054 	u8         fw_rev_subminor[0x10];
11055 
11056 	u8         reserved_at_40[0x40];
11057 
11058 	u8         cmdq_phy_addr_63_32[0x20];
11059 
11060 	u8         cmdq_phy_addr_31_12[0x14];
11061 	u8         reserved_at_b4[0x2];
11062 	u8         nic_interface[0x2];
11063 	u8         log_cmdq_size[0x4];
11064 	u8         log_cmdq_stride[0x4];
11065 
11066 	u8         command_doorbell_vector[0x20];
11067 
11068 	u8         reserved_at_e0[0xf00];
11069 
11070 	u8         initializing[0x1];
11071 	u8         reserved_at_fe1[0x4];
11072 	u8         nic_interface_supported[0x3];
11073 	u8         embedded_cpu[0x1];
11074 	u8         reserved_at_fe9[0x17];
11075 
11076 	struct mlx5_ifc_health_buffer_bits health_buffer;
11077 
11078 	u8         no_dram_nic_offset[0x20];
11079 
11080 	u8         reserved_at_1220[0x6e40];
11081 
11082 	u8         reserved_at_8060[0x1f];
11083 	u8         clear_int[0x1];
11084 
11085 	u8         health_syndrome[0x8];
11086 	u8         health_counter[0x18];
11087 
11088 	u8         reserved_at_80a0[0x17fc0];
11089 };
11090 
11091 struct mlx5_ifc_mtpps_reg_bits {
11092 	u8         reserved_at_0[0xc];
11093 	u8         cap_number_of_pps_pins[0x4];
11094 	u8         reserved_at_10[0x4];
11095 	u8         cap_max_num_of_pps_in_pins[0x4];
11096 	u8         reserved_at_18[0x4];
11097 	u8         cap_max_num_of_pps_out_pins[0x4];
11098 
11099 	u8         reserved_at_20[0x13];
11100 	u8         cap_log_min_npps_period[0x5];
11101 	u8         reserved_at_38[0x3];
11102 	u8         cap_log_min_out_pulse_duration_ns[0x5];
11103 
11104 	u8         reserved_at_40[0x4];
11105 	u8         cap_pin_3_mode[0x4];
11106 	u8         reserved_at_48[0x4];
11107 	u8         cap_pin_2_mode[0x4];
11108 	u8         reserved_at_50[0x4];
11109 	u8         cap_pin_1_mode[0x4];
11110 	u8         reserved_at_58[0x4];
11111 	u8         cap_pin_0_mode[0x4];
11112 
11113 	u8         reserved_at_60[0x4];
11114 	u8         cap_pin_7_mode[0x4];
11115 	u8         reserved_at_68[0x4];
11116 	u8         cap_pin_6_mode[0x4];
11117 	u8         reserved_at_70[0x4];
11118 	u8         cap_pin_5_mode[0x4];
11119 	u8         reserved_at_78[0x4];
11120 	u8         cap_pin_4_mode[0x4];
11121 
11122 	u8         field_select[0x20];
11123 	u8         reserved_at_a0[0x20];
11124 
11125 	u8         npps_period[0x40];
11126 
11127 	u8         enable[0x1];
11128 	u8         reserved_at_101[0xb];
11129 	u8         pattern[0x4];
11130 	u8         reserved_at_110[0x4];
11131 	u8         pin_mode[0x4];
11132 	u8         pin[0x8];
11133 
11134 	u8         reserved_at_120[0x2];
11135 	u8         out_pulse_duration_ns[0x1e];
11136 
11137 	u8         time_stamp[0x40];
11138 
11139 	u8         out_pulse_duration[0x10];
11140 	u8         out_periodic_adjustment[0x10];
11141 	u8         enhanced_out_periodic_adjustment[0x20];
11142 
11143 	u8         reserved_at_1c0[0x20];
11144 };
11145 
11146 struct mlx5_ifc_mtppse_reg_bits {
11147 	u8         reserved_at_0[0x18];
11148 	u8         pin[0x8];
11149 	u8         event_arm[0x1];
11150 	u8         reserved_at_21[0x1b];
11151 	u8         event_generation_mode[0x4];
11152 	u8         reserved_at_40[0x40];
11153 };
11154 
11155 struct mlx5_ifc_mcqs_reg_bits {
11156 	u8         last_index_flag[0x1];
11157 	u8         reserved_at_1[0x7];
11158 	u8         fw_device[0x8];
11159 	u8         component_index[0x10];
11160 
11161 	u8         reserved_at_20[0x10];
11162 	u8         identifier[0x10];
11163 
11164 	u8         reserved_at_40[0x17];
11165 	u8         component_status[0x5];
11166 	u8         component_update_state[0x4];
11167 
11168 	u8         last_update_state_changer_type[0x4];
11169 	u8         last_update_state_changer_host_id[0x4];
11170 	u8         reserved_at_68[0x18];
11171 };
11172 
11173 struct mlx5_ifc_mcqi_cap_bits {
11174 	u8         supported_info_bitmask[0x20];
11175 
11176 	u8         component_size[0x20];
11177 
11178 	u8         max_component_size[0x20];
11179 
11180 	u8         log_mcda_word_size[0x4];
11181 	u8         reserved_at_64[0xc];
11182 	u8         mcda_max_write_size[0x10];
11183 
11184 	u8         rd_en[0x1];
11185 	u8         reserved_at_81[0x1];
11186 	u8         match_chip_id[0x1];
11187 	u8         match_psid[0x1];
11188 	u8         check_user_timestamp[0x1];
11189 	u8         match_base_guid_mac[0x1];
11190 	u8         reserved_at_86[0x1a];
11191 };
11192 
11193 struct mlx5_ifc_mcqi_version_bits {
11194 	u8         reserved_at_0[0x2];
11195 	u8         build_time_valid[0x1];
11196 	u8         user_defined_time_valid[0x1];
11197 	u8         reserved_at_4[0x14];
11198 	u8         version_string_length[0x8];
11199 
11200 	u8         version[0x20];
11201 
11202 	u8         build_time[0x40];
11203 
11204 	u8         user_defined_time[0x40];
11205 
11206 	u8         build_tool_version[0x20];
11207 
11208 	u8         reserved_at_e0[0x20];
11209 
11210 	u8         version_string[92][0x8];
11211 };
11212 
11213 struct mlx5_ifc_mcqi_activation_method_bits {
11214 	u8         pending_server_ac_power_cycle[0x1];
11215 	u8         pending_server_dc_power_cycle[0x1];
11216 	u8         pending_server_reboot[0x1];
11217 	u8         pending_fw_reset[0x1];
11218 	u8         auto_activate[0x1];
11219 	u8         all_hosts_sync[0x1];
11220 	u8         device_hw_reset[0x1];
11221 	u8         reserved_at_7[0x19];
11222 };
11223 
11224 union mlx5_ifc_mcqi_reg_data_bits {
11225 	struct mlx5_ifc_mcqi_cap_bits               mcqi_caps;
11226 	struct mlx5_ifc_mcqi_version_bits           mcqi_version;
11227 	struct mlx5_ifc_mcqi_activation_method_bits mcqi_activation_mathod;
11228 };
11229 
11230 struct mlx5_ifc_mcqi_reg_bits {
11231 	u8         read_pending_component[0x1];
11232 	u8         reserved_at_1[0xf];
11233 	u8         component_index[0x10];
11234 
11235 	u8         reserved_at_20[0x20];
11236 
11237 	u8         reserved_at_40[0x1b];
11238 	u8         info_type[0x5];
11239 
11240 	u8         info_size[0x20];
11241 
11242 	u8         offset[0x20];
11243 
11244 	u8         reserved_at_a0[0x10];
11245 	u8         data_size[0x10];
11246 
11247 	union mlx5_ifc_mcqi_reg_data_bits data[];
11248 };
11249 
11250 struct mlx5_ifc_mcc_reg_bits {
11251 	u8         reserved_at_0[0x4];
11252 	u8         time_elapsed_since_last_cmd[0xc];
11253 	u8         reserved_at_10[0x8];
11254 	u8         instruction[0x8];
11255 
11256 	u8         reserved_at_20[0x10];
11257 	u8         component_index[0x10];
11258 
11259 	u8         reserved_at_40[0x8];
11260 	u8         update_handle[0x18];
11261 
11262 	u8         handle_owner_type[0x4];
11263 	u8         handle_owner_host_id[0x4];
11264 	u8         reserved_at_68[0x1];
11265 	u8         control_progress[0x7];
11266 	u8         error_code[0x8];
11267 	u8         reserved_at_78[0x4];
11268 	u8         control_state[0x4];
11269 
11270 	u8         component_size[0x20];
11271 
11272 	u8         reserved_at_a0[0x60];
11273 };
11274 
11275 struct mlx5_ifc_mcda_reg_bits {
11276 	u8         reserved_at_0[0x8];
11277 	u8         update_handle[0x18];
11278 
11279 	u8         offset[0x20];
11280 
11281 	u8         reserved_at_40[0x10];
11282 	u8         size[0x10];
11283 
11284 	u8         reserved_at_60[0x20];
11285 
11286 	u8         data[][0x20];
11287 };
11288 
11289 enum {
11290 	MLX5_MFRL_REG_PCI_RESET_METHOD_LINK_TOGGLE = 0,
11291 	MLX5_MFRL_REG_PCI_RESET_METHOD_HOT_RESET = 1,
11292 };
11293 
11294 enum {
11295 	MLX5_MFRL_REG_RESET_STATE_IDLE = 0,
11296 	MLX5_MFRL_REG_RESET_STATE_IN_NEGOTIATION = 1,
11297 	MLX5_MFRL_REG_RESET_STATE_RESET_IN_PROGRESS = 2,
11298 	MLX5_MFRL_REG_RESET_STATE_NEG_TIMEOUT = 3,
11299 	MLX5_MFRL_REG_RESET_STATE_NACK = 4,
11300 	MLX5_MFRL_REG_RESET_STATE_UNLOAD_TIMEOUT = 5,
11301 };
11302 
11303 enum {
11304 	MLX5_MFRL_REG_RESET_TYPE_FULL_CHIP = BIT(0),
11305 	MLX5_MFRL_REG_RESET_TYPE_NET_PORT_ALIVE = BIT(1),
11306 };
11307 
11308 enum {
11309 	MLX5_MFRL_REG_RESET_LEVEL0 = BIT(0),
11310 	MLX5_MFRL_REG_RESET_LEVEL3 = BIT(3),
11311 	MLX5_MFRL_REG_RESET_LEVEL6 = BIT(6),
11312 };
11313 
11314 struct mlx5_ifc_mfrl_reg_bits {
11315 	u8         reserved_at_0[0x20];
11316 
11317 	u8         reserved_at_20[0x2];
11318 	u8         pci_sync_for_fw_update_start[0x1];
11319 	u8         pci_sync_for_fw_update_resp[0x2];
11320 	u8         rst_type_sel[0x3];
11321 	u8         pci_reset_req_method[0x3];
11322 	u8         reserved_at_2b[0x1];
11323 	u8         reset_state[0x4];
11324 	u8         reset_type[0x8];
11325 	u8         reset_level[0x8];
11326 };
11327 
11328 struct mlx5_ifc_mirc_reg_bits {
11329 	u8         reserved_at_0[0x18];
11330 	u8         status_code[0x8];
11331 
11332 	u8         reserved_at_20[0x20];
11333 };
11334 
11335 struct mlx5_ifc_pddr_monitor_opcode_bits {
11336 	u8         reserved_at_0[0x10];
11337 	u8         monitor_opcode[0x10];
11338 };
11339 
11340 union mlx5_ifc_pddr_troubleshooting_page_status_opcode_auto_bits {
11341 	struct mlx5_ifc_pddr_monitor_opcode_bits pddr_monitor_opcode;
11342 	u8         reserved_at_0[0x20];
11343 };
11344 
11345 enum {
11346 	/* Monitor opcodes */
11347 	MLX5_PDDR_REG_TRBLSH_GROUP_OPCODE_MONITOR = 0x0,
11348 };
11349 
11350 struct mlx5_ifc_pddr_troubleshooting_page_bits {
11351 	u8         reserved_at_0[0x10];
11352 	u8         group_opcode[0x10];
11353 
11354 	union mlx5_ifc_pddr_troubleshooting_page_status_opcode_auto_bits status_opcode;
11355 
11356 	u8         reserved_at_40[0x20];
11357 
11358 	u8         status_message[59][0x20];
11359 };
11360 
11361 union mlx5_ifc_pddr_reg_page_data_auto_bits {
11362 	struct mlx5_ifc_pddr_troubleshooting_page_bits pddr_troubleshooting_page;
11363 	u8         reserved_at_0[0x7c0];
11364 };
11365 
11366 enum {
11367 	MLX5_PDDR_REG_PAGE_SELECT_TROUBLESHOOTING_INFO_PAGE      = 0x1,
11368 };
11369 
11370 struct mlx5_ifc_pddr_reg_bits {
11371 	u8         reserved_at_0[0x8];
11372 	u8         local_port[0x8];
11373 	u8         pnat[0x2];
11374 	u8         reserved_at_12[0xe];
11375 
11376 	u8         reserved_at_20[0x18];
11377 	u8         page_select[0x8];
11378 
11379 	union mlx5_ifc_pddr_reg_page_data_auto_bits page_data;
11380 };
11381 
11382 struct mlx5_ifc_mrtc_reg_bits {
11383 	u8         time_synced[0x1];
11384 	u8         reserved_at_1[0x1f];
11385 
11386 	u8         reserved_at_20[0x20];
11387 
11388 	u8         time_h[0x20];
11389 
11390 	u8         time_l[0x20];
11391 };
11392 
11393 struct mlx5_ifc_mtcap_reg_bits {
11394 	u8         reserved_at_0[0x19];
11395 	u8         sensor_count[0x7];
11396 
11397 	u8         reserved_at_20[0x20];
11398 
11399 	u8         sensor_map[0x40];
11400 };
11401 
11402 struct mlx5_ifc_mtmp_reg_bits {
11403 	u8         reserved_at_0[0x14];
11404 	u8         sensor_index[0xc];
11405 
11406 	u8         reserved_at_20[0x10];
11407 	u8         temperature[0x10];
11408 
11409 	u8         mte[0x1];
11410 	u8         mtr[0x1];
11411 	u8         reserved_at_42[0xe];
11412 	u8         max_temperature[0x10];
11413 
11414 	u8         tee[0x2];
11415 	u8         reserved_at_62[0xe];
11416 	u8         temp_threshold_hi[0x10];
11417 
11418 	u8         reserved_at_80[0x10];
11419 	u8         temp_threshold_lo[0x10];
11420 
11421 	u8         reserved_at_a0[0x20];
11422 
11423 	u8         sensor_name_hi[0x20];
11424 	u8         sensor_name_lo[0x20];
11425 };
11426 
11427 struct mlx5_ifc_mtptm_reg_bits {
11428 	u8         reserved_at_0[0x10];
11429 	u8         psta[0x1];
11430 	u8         reserved_at_11[0xf];
11431 
11432 	u8         reserved_at_20[0x60];
11433 };
11434 
11435 enum {
11436 	MLX5_MTCTR_REQUEST_NOP = 0x0,
11437 	MLX5_MTCTR_REQUEST_PTM_ROOT_CLOCK = 0x1,
11438 	MLX5_MTCTR_REQUEST_FREE_RUNNING_COUNTER = 0x2,
11439 	MLX5_MTCTR_REQUEST_REAL_TIME_CLOCK = 0x3,
11440 };
11441 
11442 struct mlx5_ifc_mtctr_reg_bits {
11443 	u8         first_clock_timestamp_request[0x8];
11444 	u8         second_clock_timestamp_request[0x8];
11445 	u8         reserved_at_10[0x10];
11446 
11447 	u8         first_clock_valid[0x1];
11448 	u8         second_clock_valid[0x1];
11449 	u8         reserved_at_22[0x1e];
11450 
11451 	u8         first_clock_timestamp[0x40];
11452 	u8         second_clock_timestamp[0x40];
11453 };
11454 
11455 union mlx5_ifc_ports_control_registers_document_bits {
11456 	struct mlx5_ifc_bufferx_reg_bits bufferx_reg;
11457 	struct mlx5_ifc_eth_2819_cntrs_grp_data_layout_bits eth_2819_cntrs_grp_data_layout;
11458 	struct mlx5_ifc_eth_2863_cntrs_grp_data_layout_bits eth_2863_cntrs_grp_data_layout;
11459 	struct mlx5_ifc_eth_3635_cntrs_grp_data_layout_bits eth_3635_cntrs_grp_data_layout;
11460 	struct mlx5_ifc_eth_802_3_cntrs_grp_data_layout_bits eth_802_3_cntrs_grp_data_layout;
11461 	struct mlx5_ifc_eth_extended_cntrs_grp_data_layout_bits eth_extended_cntrs_grp_data_layout;
11462 	struct mlx5_ifc_eth_per_prio_grp_data_layout_bits eth_per_prio_grp_data_layout;
11463 	struct mlx5_ifc_eth_per_tc_prio_grp_data_layout_bits eth_per_tc_prio_grp_data_layout;
11464 	struct mlx5_ifc_eth_per_tc_congest_prio_grp_data_layout_bits eth_per_tc_congest_prio_grp_data_layout;
11465 	struct mlx5_ifc_lane_2_module_mapping_bits lane_2_module_mapping;
11466 	struct mlx5_ifc_pamp_reg_bits pamp_reg;
11467 	struct mlx5_ifc_paos_reg_bits paos_reg;
11468 	struct mlx5_ifc_pcap_reg_bits pcap_reg;
11469 	struct mlx5_ifc_pddr_monitor_opcode_bits pddr_monitor_opcode;
11470 	struct mlx5_ifc_pddr_reg_bits pddr_reg;
11471 	struct mlx5_ifc_pddr_troubleshooting_page_bits pddr_troubleshooting_page;
11472 	struct mlx5_ifc_peir_reg_bits peir_reg;
11473 	struct mlx5_ifc_pelc_reg_bits pelc_reg;
11474 	struct mlx5_ifc_pfcc_reg_bits pfcc_reg;
11475 	struct mlx5_ifc_ib_port_cntrs_grp_data_layout_bits ib_port_cntrs_grp_data_layout;
11476 	struct mlx5_ifc_phys_layer_cntrs_bits phys_layer_cntrs;
11477 	struct mlx5_ifc_pifr_reg_bits pifr_reg;
11478 	struct mlx5_ifc_pipg_reg_bits pipg_reg;
11479 	struct mlx5_ifc_plbf_reg_bits plbf_reg;
11480 	struct mlx5_ifc_plib_reg_bits plib_reg;
11481 	struct mlx5_ifc_plpc_reg_bits plpc_reg;
11482 	struct mlx5_ifc_pmaos_reg_bits pmaos_reg;
11483 	struct mlx5_ifc_pmlp_reg_bits pmlp_reg;
11484 	struct mlx5_ifc_pmlpn_reg_bits pmlpn_reg;
11485 	struct mlx5_ifc_pmpc_reg_bits pmpc_reg;
11486 	struct mlx5_ifc_pmpe_reg_bits pmpe_reg;
11487 	struct mlx5_ifc_pmpr_reg_bits pmpr_reg;
11488 	struct mlx5_ifc_pmtu_reg_bits pmtu_reg;
11489 	struct mlx5_ifc_ppad_reg_bits ppad_reg;
11490 	struct mlx5_ifc_ppcnt_reg_bits ppcnt_reg;
11491 	struct mlx5_ifc_mpein_reg_bits mpein_reg;
11492 	struct mlx5_ifc_mpcnt_reg_bits mpcnt_reg;
11493 	struct mlx5_ifc_pplm_reg_bits pplm_reg;
11494 	struct mlx5_ifc_pplr_reg_bits pplr_reg;
11495 	struct mlx5_ifc_ppsc_reg_bits ppsc_reg;
11496 	struct mlx5_ifc_pqdr_reg_bits pqdr_reg;
11497 	struct mlx5_ifc_pspa_reg_bits pspa_reg;
11498 	struct mlx5_ifc_ptas_reg_bits ptas_reg;
11499 	struct mlx5_ifc_ptys_reg_bits ptys_reg;
11500 	struct mlx5_ifc_mlcr_reg_bits mlcr_reg;
11501 	struct mlx5_ifc_pude_reg_bits pude_reg;
11502 	struct mlx5_ifc_pvlc_reg_bits pvlc_reg;
11503 	struct mlx5_ifc_slrg_reg_bits slrg_reg;
11504 	struct mlx5_ifc_sltp_reg_bits sltp_reg;
11505 	struct mlx5_ifc_mtpps_reg_bits mtpps_reg;
11506 	struct mlx5_ifc_mtppse_reg_bits mtppse_reg;
11507 	struct mlx5_ifc_fpga_access_reg_bits fpga_access_reg;
11508 	struct mlx5_ifc_fpga_ctrl_bits fpga_ctrl_bits;
11509 	struct mlx5_ifc_fpga_cap_bits fpga_cap_bits;
11510 	struct mlx5_ifc_mcqi_reg_bits mcqi_reg;
11511 	struct mlx5_ifc_mcc_reg_bits mcc_reg;
11512 	struct mlx5_ifc_mcda_reg_bits mcda_reg;
11513 	struct mlx5_ifc_mirc_reg_bits mirc_reg;
11514 	struct mlx5_ifc_mfrl_reg_bits mfrl_reg;
11515 	struct mlx5_ifc_mtutc_reg_bits mtutc_reg;
11516 	struct mlx5_ifc_mrtc_reg_bits mrtc_reg;
11517 	struct mlx5_ifc_mtcap_reg_bits mtcap_reg;
11518 	struct mlx5_ifc_mtmp_reg_bits mtmp_reg;
11519 	struct mlx5_ifc_mtptm_reg_bits mtptm_reg;
11520 	struct mlx5_ifc_mtctr_reg_bits mtctr_reg;
11521 	u8         reserved_at_0[0x60e0];
11522 };
11523 
11524 union mlx5_ifc_debug_enhancements_document_bits {
11525 	struct mlx5_ifc_health_buffer_bits health_buffer;
11526 	u8         reserved_at_0[0x200];
11527 };
11528 
11529 union mlx5_ifc_uplink_pci_interface_document_bits {
11530 	struct mlx5_ifc_initial_seg_bits initial_seg;
11531 	u8         reserved_at_0[0x20060];
11532 };
11533 
11534 struct mlx5_ifc_set_flow_table_root_out_bits {
11535 	u8         status[0x8];
11536 	u8         reserved_at_8[0x18];
11537 
11538 	u8         syndrome[0x20];
11539 
11540 	u8         reserved_at_40[0x40];
11541 };
11542 
11543 struct mlx5_ifc_set_flow_table_root_in_bits {
11544 	u8         opcode[0x10];
11545 	u8         reserved_at_10[0x10];
11546 
11547 	u8         reserved_at_20[0x10];
11548 	u8         op_mod[0x10];
11549 
11550 	u8         other_vport[0x1];
11551 	u8         reserved_at_41[0xf];
11552 	u8         vport_number[0x10];
11553 
11554 	u8         reserved_at_60[0x20];
11555 
11556 	u8         table_type[0x8];
11557 	u8         reserved_at_88[0x7];
11558 	u8         table_of_other_vport[0x1];
11559 	u8         table_vport_number[0x10];
11560 
11561 	u8         reserved_at_a0[0x8];
11562 	u8         table_id[0x18];
11563 
11564 	u8         reserved_at_c0[0x8];
11565 	u8         underlay_qpn[0x18];
11566 	u8         table_eswitch_owner_vhca_id_valid[0x1];
11567 	u8         reserved_at_e1[0xf];
11568 	u8         table_eswitch_owner_vhca_id[0x10];
11569 	u8         reserved_at_100[0x100];
11570 };
11571 
11572 enum {
11573 	MLX5_MODIFY_FLOW_TABLE_MISS_TABLE_ID     = (1UL << 0),
11574 	MLX5_MODIFY_FLOW_TABLE_LAG_NEXT_TABLE_ID = (1UL << 15),
11575 };
11576 
11577 struct mlx5_ifc_modify_flow_table_out_bits {
11578 	u8         status[0x8];
11579 	u8         reserved_at_8[0x18];
11580 
11581 	u8         syndrome[0x20];
11582 
11583 	u8         reserved_at_40[0x40];
11584 };
11585 
11586 struct mlx5_ifc_modify_flow_table_in_bits {
11587 	u8         opcode[0x10];
11588 	u8         reserved_at_10[0x10];
11589 
11590 	u8         reserved_at_20[0x10];
11591 	u8         op_mod[0x10];
11592 
11593 	u8         other_vport[0x1];
11594 	u8         reserved_at_41[0xf];
11595 	u8         vport_number[0x10];
11596 
11597 	u8         reserved_at_60[0x10];
11598 	u8         modify_field_select[0x10];
11599 
11600 	u8         table_type[0x8];
11601 	u8         reserved_at_88[0x18];
11602 
11603 	u8         reserved_at_a0[0x8];
11604 	u8         table_id[0x18];
11605 
11606 	struct mlx5_ifc_flow_table_context_bits flow_table_context;
11607 };
11608 
11609 struct mlx5_ifc_ets_tcn_config_reg_bits {
11610 	u8         g[0x1];
11611 	u8         b[0x1];
11612 	u8         r[0x1];
11613 	u8         reserved_at_3[0x9];
11614 	u8         group[0x4];
11615 	u8         reserved_at_10[0x9];
11616 	u8         bw_allocation[0x7];
11617 
11618 	u8         reserved_at_20[0xc];
11619 	u8         max_bw_units[0x4];
11620 	u8         reserved_at_30[0x8];
11621 	u8         max_bw_value[0x8];
11622 };
11623 
11624 struct mlx5_ifc_ets_global_config_reg_bits {
11625 	u8         reserved_at_0[0x2];
11626 	u8         r[0x1];
11627 	u8         reserved_at_3[0x1d];
11628 
11629 	u8         reserved_at_20[0xc];
11630 	u8         max_bw_units[0x4];
11631 	u8         reserved_at_30[0x8];
11632 	u8         max_bw_value[0x8];
11633 };
11634 
11635 struct mlx5_ifc_qetc_reg_bits {
11636 	u8                                         reserved_at_0[0x8];
11637 	u8                                         port_number[0x8];
11638 	u8                                         reserved_at_10[0x30];
11639 
11640 	struct mlx5_ifc_ets_tcn_config_reg_bits    tc_configuration[0x8];
11641 	struct mlx5_ifc_ets_global_config_reg_bits global_configuration;
11642 };
11643 
11644 struct mlx5_ifc_qpdpm_dscp_reg_bits {
11645 	u8         e[0x1];
11646 	u8         reserved_at_01[0x0b];
11647 	u8         prio[0x04];
11648 };
11649 
11650 struct mlx5_ifc_qpdpm_reg_bits {
11651 	u8                                     reserved_at_0[0x8];
11652 	u8                                     local_port[0x8];
11653 	u8                                     reserved_at_10[0x10];
11654 	struct mlx5_ifc_qpdpm_dscp_reg_bits    dscp[64];
11655 };
11656 
11657 struct mlx5_ifc_qpts_reg_bits {
11658 	u8         reserved_at_0[0x8];
11659 	u8         local_port[0x8];
11660 	u8         reserved_at_10[0x2d];
11661 	u8         trust_state[0x3];
11662 };
11663 
11664 struct mlx5_ifc_pptb_reg_bits {
11665 	u8         reserved_at_0[0x2];
11666 	u8         mm[0x2];
11667 	u8         reserved_at_4[0x4];
11668 	u8         local_port[0x8];
11669 	u8         reserved_at_10[0x6];
11670 	u8         cm[0x1];
11671 	u8         um[0x1];
11672 	u8         pm[0x8];
11673 
11674 	u8         prio_x_buff[0x20];
11675 
11676 	u8         pm_msb[0x8];
11677 	u8         reserved_at_48[0x10];
11678 	u8         ctrl_buff[0x4];
11679 	u8         untagged_buff[0x4];
11680 };
11681 
11682 struct mlx5_ifc_sbcam_reg_bits {
11683 	u8         reserved_at_0[0x8];
11684 	u8         feature_group[0x8];
11685 	u8         reserved_at_10[0x8];
11686 	u8         access_reg_group[0x8];
11687 
11688 	u8         reserved_at_20[0x20];
11689 
11690 	u8         sb_access_reg_cap_mask[4][0x20];
11691 
11692 	u8         reserved_at_c0[0x80];
11693 
11694 	u8         sb_feature_cap_mask[4][0x20];
11695 
11696 	u8         reserved_at_1c0[0x40];
11697 
11698 	u8         cap_total_buffer_size[0x20];
11699 
11700 	u8         cap_cell_size[0x10];
11701 	u8         cap_max_pg_buffers[0x8];
11702 	u8         cap_num_pool_supported[0x8];
11703 
11704 	u8         reserved_at_240[0x8];
11705 	u8         cap_sbsr_stat_size[0x8];
11706 	u8         cap_max_tclass_data[0x8];
11707 	u8         cap_max_cpu_ingress_tclass_sb[0x8];
11708 };
11709 
11710 struct mlx5_ifc_pbmc_reg_bits {
11711 	u8         reserved_at_0[0x8];
11712 	u8         local_port[0x8];
11713 	u8         reserved_at_10[0x10];
11714 
11715 	u8         xoff_timer_value[0x10];
11716 	u8         xoff_refresh[0x10];
11717 
11718 	u8         reserved_at_40[0x9];
11719 	u8         fullness_threshold[0x7];
11720 	u8         port_buffer_size[0x10];
11721 
11722 	struct mlx5_ifc_bufferx_reg_bits buffer[10];
11723 
11724 	u8         reserved_at_2e0[0x80];
11725 };
11726 
11727 struct mlx5_ifc_sbpr_reg_bits {
11728 	u8         desc[0x1];
11729 	u8         snap[0x1];
11730 	u8         reserved_at_2[0x4];
11731 	u8         dir[0x2];
11732 	u8         reserved_at_8[0x14];
11733 	u8         pool[0x4];
11734 
11735 	u8         infi_size[0x1];
11736 	u8         reserved_at_21[0x7];
11737 	u8         size[0x18];
11738 
11739 	u8         reserved_at_40[0x1c];
11740 	u8         mode[0x4];
11741 
11742 	u8         reserved_at_60[0x8];
11743 	u8         buff_occupancy[0x18];
11744 
11745 	u8         clr[0x1];
11746 	u8         reserved_at_81[0x7];
11747 	u8         max_buff_occupancy[0x18];
11748 
11749 	u8         reserved_at_a0[0x8];
11750 	u8         ext_buff_occupancy[0x18];
11751 };
11752 
11753 struct mlx5_ifc_sbcm_reg_bits {
11754 	u8         desc[0x1];
11755 	u8         snap[0x1];
11756 	u8         reserved_at_2[0x6];
11757 	u8         local_port[0x8];
11758 	u8         pnat[0x2];
11759 	u8         pg_buff[0x6];
11760 	u8         reserved_at_18[0x6];
11761 	u8         dir[0x2];
11762 
11763 	u8         reserved_at_20[0x1f];
11764 	u8         exc[0x1];
11765 
11766 	u8         reserved_at_40[0x40];
11767 
11768 	u8         reserved_at_80[0x8];
11769 	u8         buff_occupancy[0x18];
11770 
11771 	u8         clr[0x1];
11772 	u8         reserved_at_a1[0x7];
11773 	u8         max_buff_occupancy[0x18];
11774 
11775 	u8         reserved_at_c0[0x8];
11776 	u8         min_buff[0x18];
11777 
11778 	u8         infi_max[0x1];
11779 	u8         reserved_at_e1[0x7];
11780 	u8         max_buff[0x18];
11781 
11782 	u8         reserved_at_100[0x20];
11783 
11784 	u8         reserved_at_120[0x1c];
11785 	u8         pool[0x4];
11786 };
11787 
11788 struct mlx5_ifc_qtct_reg_bits {
11789 	u8         reserved_at_0[0x8];
11790 	u8         port_number[0x8];
11791 	u8         reserved_at_10[0xd];
11792 	u8         prio[0x3];
11793 
11794 	u8         reserved_at_20[0x1d];
11795 	u8         tclass[0x3];
11796 };
11797 
11798 struct mlx5_ifc_mcia_reg_bits {
11799 	u8         l[0x1];
11800 	u8         reserved_at_1[0x7];
11801 	u8         module[0x8];
11802 	u8         reserved_at_10[0x8];
11803 	u8         status[0x8];
11804 
11805 	u8         i2c_device_address[0x8];
11806 	u8         page_number[0x8];
11807 	u8         device_address[0x10];
11808 
11809 	u8         reserved_at_40[0x10];
11810 	u8         size[0x10];
11811 
11812 	u8         reserved_at_60[0x20];
11813 
11814 	u8         dword_0[0x20];
11815 	u8         dword_1[0x20];
11816 	u8         dword_2[0x20];
11817 	u8         dword_3[0x20];
11818 	u8         dword_4[0x20];
11819 	u8         dword_5[0x20];
11820 	u8         dword_6[0x20];
11821 	u8         dword_7[0x20];
11822 	u8         dword_8[0x20];
11823 	u8         dword_9[0x20];
11824 	u8         dword_10[0x20];
11825 	u8         dword_11[0x20];
11826 };
11827 
11828 struct mlx5_ifc_dcbx_param_bits {
11829 	u8         dcbx_cee_cap[0x1];
11830 	u8         dcbx_ieee_cap[0x1];
11831 	u8         dcbx_standby_cap[0x1];
11832 	u8         reserved_at_3[0x5];
11833 	u8         port_number[0x8];
11834 	u8         reserved_at_10[0xa];
11835 	u8         max_application_table_size[6];
11836 	u8         reserved_at_20[0x15];
11837 	u8         version_oper[0x3];
11838 	u8         reserved_at_38[5];
11839 	u8         version_admin[0x3];
11840 	u8         willing_admin[0x1];
11841 	u8         reserved_at_41[0x3];
11842 	u8         pfc_cap_oper[0x4];
11843 	u8         reserved_at_48[0x4];
11844 	u8         pfc_cap_admin[0x4];
11845 	u8         reserved_at_50[0x4];
11846 	u8         num_of_tc_oper[0x4];
11847 	u8         reserved_at_58[0x4];
11848 	u8         num_of_tc_admin[0x4];
11849 	u8         remote_willing[0x1];
11850 	u8         reserved_at_61[3];
11851 	u8         remote_pfc_cap[4];
11852 	u8         reserved_at_68[0x14];
11853 	u8         remote_num_of_tc[0x4];
11854 	u8         reserved_at_80[0x18];
11855 	u8         error[0x8];
11856 	u8         reserved_at_a0[0x160];
11857 };
11858 
11859 enum {
11860 	MLX5_LAG_PORT_SELECT_MODE_QUEUE_AFFINITY = 0,
11861 	MLX5_LAG_PORT_SELECT_MODE_PORT_SELECT_FT = 1,
11862 	MLX5_LAG_PORT_SELECT_MODE_PORT_SELECT_MPESW = 2,
11863 };
11864 
11865 struct mlx5_ifc_lagc_bits {
11866 	u8         fdb_selection_mode[0x1];
11867 	u8         reserved_at_1[0x14];
11868 	u8         port_select_mode[0x3];
11869 	u8         reserved_at_18[0x5];
11870 	u8         lag_state[0x3];
11871 
11872 	u8         reserved_at_20[0xc];
11873 	u8         active_port[0x4];
11874 	u8         reserved_at_30[0x4];
11875 	u8         tx_remap_affinity_2[0x4];
11876 	u8         reserved_at_38[0x4];
11877 	u8         tx_remap_affinity_1[0x4];
11878 };
11879 
11880 struct mlx5_ifc_create_lag_out_bits {
11881 	u8         status[0x8];
11882 	u8         reserved_at_8[0x18];
11883 
11884 	u8         syndrome[0x20];
11885 
11886 	u8         reserved_at_40[0x40];
11887 };
11888 
11889 struct mlx5_ifc_create_lag_in_bits {
11890 	u8         opcode[0x10];
11891 	u8         reserved_at_10[0x10];
11892 
11893 	u8         reserved_at_20[0x10];
11894 	u8         op_mod[0x10];
11895 
11896 	struct mlx5_ifc_lagc_bits ctx;
11897 };
11898 
11899 struct mlx5_ifc_modify_lag_out_bits {
11900 	u8         status[0x8];
11901 	u8         reserved_at_8[0x18];
11902 
11903 	u8         syndrome[0x20];
11904 
11905 	u8         reserved_at_40[0x40];
11906 };
11907 
11908 struct mlx5_ifc_modify_lag_in_bits {
11909 	u8         opcode[0x10];
11910 	u8         reserved_at_10[0x10];
11911 
11912 	u8         reserved_at_20[0x10];
11913 	u8         op_mod[0x10];
11914 
11915 	u8         reserved_at_40[0x20];
11916 	u8         field_select[0x20];
11917 
11918 	struct mlx5_ifc_lagc_bits ctx;
11919 };
11920 
11921 struct mlx5_ifc_query_lag_out_bits {
11922 	u8         status[0x8];
11923 	u8         reserved_at_8[0x18];
11924 
11925 	u8         syndrome[0x20];
11926 
11927 	struct mlx5_ifc_lagc_bits ctx;
11928 };
11929 
11930 struct mlx5_ifc_query_lag_in_bits {
11931 	u8         opcode[0x10];
11932 	u8         reserved_at_10[0x10];
11933 
11934 	u8         reserved_at_20[0x10];
11935 	u8         op_mod[0x10];
11936 
11937 	u8         reserved_at_40[0x40];
11938 };
11939 
11940 struct mlx5_ifc_destroy_lag_out_bits {
11941 	u8         status[0x8];
11942 	u8         reserved_at_8[0x18];
11943 
11944 	u8         syndrome[0x20];
11945 
11946 	u8         reserved_at_40[0x40];
11947 };
11948 
11949 struct mlx5_ifc_destroy_lag_in_bits {
11950 	u8         opcode[0x10];
11951 	u8         reserved_at_10[0x10];
11952 
11953 	u8         reserved_at_20[0x10];
11954 	u8         op_mod[0x10];
11955 
11956 	u8         reserved_at_40[0x40];
11957 };
11958 
11959 struct mlx5_ifc_create_vport_lag_out_bits {
11960 	u8         status[0x8];
11961 	u8         reserved_at_8[0x18];
11962 
11963 	u8         syndrome[0x20];
11964 
11965 	u8         reserved_at_40[0x40];
11966 };
11967 
11968 struct mlx5_ifc_create_vport_lag_in_bits {
11969 	u8         opcode[0x10];
11970 	u8         reserved_at_10[0x10];
11971 
11972 	u8         reserved_at_20[0x10];
11973 	u8         op_mod[0x10];
11974 
11975 	u8         reserved_at_40[0x40];
11976 };
11977 
11978 struct mlx5_ifc_destroy_vport_lag_out_bits {
11979 	u8         status[0x8];
11980 	u8         reserved_at_8[0x18];
11981 
11982 	u8         syndrome[0x20];
11983 
11984 	u8         reserved_at_40[0x40];
11985 };
11986 
11987 struct mlx5_ifc_destroy_vport_lag_in_bits {
11988 	u8         opcode[0x10];
11989 	u8         reserved_at_10[0x10];
11990 
11991 	u8         reserved_at_20[0x10];
11992 	u8         op_mod[0x10];
11993 
11994 	u8         reserved_at_40[0x40];
11995 };
11996 
11997 enum {
11998 	MLX5_MODIFY_MEMIC_OP_MOD_ALLOC,
11999 	MLX5_MODIFY_MEMIC_OP_MOD_DEALLOC,
12000 };
12001 
12002 struct mlx5_ifc_modify_memic_in_bits {
12003 	u8         opcode[0x10];
12004 	u8         uid[0x10];
12005 
12006 	u8         reserved_at_20[0x10];
12007 	u8         op_mod[0x10];
12008 
12009 	u8         reserved_at_40[0x20];
12010 
12011 	u8         reserved_at_60[0x18];
12012 	u8         memic_operation_type[0x8];
12013 
12014 	u8         memic_start_addr[0x40];
12015 
12016 	u8         reserved_at_c0[0x140];
12017 };
12018 
12019 struct mlx5_ifc_modify_memic_out_bits {
12020 	u8         status[0x8];
12021 	u8         reserved_at_8[0x18];
12022 
12023 	u8         syndrome[0x20];
12024 
12025 	u8         reserved_at_40[0x40];
12026 
12027 	u8         memic_operation_addr[0x40];
12028 
12029 	u8         reserved_at_c0[0x140];
12030 };
12031 
12032 struct mlx5_ifc_alloc_memic_in_bits {
12033 	u8         opcode[0x10];
12034 	u8         reserved_at_10[0x10];
12035 
12036 	u8         reserved_at_20[0x10];
12037 	u8         op_mod[0x10];
12038 
12039 	u8         reserved_at_30[0x20];
12040 
12041 	u8	   reserved_at_40[0x18];
12042 	u8	   log_memic_addr_alignment[0x8];
12043 
12044 	u8         range_start_addr[0x40];
12045 
12046 	u8         range_size[0x20];
12047 
12048 	u8         memic_size[0x20];
12049 };
12050 
12051 struct mlx5_ifc_alloc_memic_out_bits {
12052 	u8         status[0x8];
12053 	u8         reserved_at_8[0x18];
12054 
12055 	u8         syndrome[0x20];
12056 
12057 	u8         memic_start_addr[0x40];
12058 };
12059 
12060 struct mlx5_ifc_dealloc_memic_in_bits {
12061 	u8         opcode[0x10];
12062 	u8         reserved_at_10[0x10];
12063 
12064 	u8         reserved_at_20[0x10];
12065 	u8         op_mod[0x10];
12066 
12067 	u8         reserved_at_40[0x40];
12068 
12069 	u8         memic_start_addr[0x40];
12070 
12071 	u8         memic_size[0x20];
12072 
12073 	u8         reserved_at_e0[0x20];
12074 };
12075 
12076 struct mlx5_ifc_dealloc_memic_out_bits {
12077 	u8         status[0x8];
12078 	u8         reserved_at_8[0x18];
12079 
12080 	u8         syndrome[0x20];
12081 
12082 	u8         reserved_at_40[0x40];
12083 };
12084 
12085 struct mlx5_ifc_umem_bits {
12086 	u8         reserved_at_0[0x80];
12087 
12088 	u8         ats[0x1];
12089 	u8         reserved_at_81[0x1a];
12090 	u8         log_page_size[0x5];
12091 
12092 	u8         page_offset[0x20];
12093 
12094 	u8         num_of_mtt[0x40];
12095 
12096 	struct mlx5_ifc_mtt_bits  mtt[];
12097 };
12098 
12099 struct mlx5_ifc_uctx_bits {
12100 	u8         cap[0x20];
12101 
12102 	u8         reserved_at_20[0x160];
12103 };
12104 
12105 struct mlx5_ifc_sw_icm_bits {
12106 	u8         modify_field_select[0x40];
12107 
12108 	u8	   reserved_at_40[0x18];
12109 	u8         log_sw_icm_size[0x8];
12110 
12111 	u8         reserved_at_60[0x20];
12112 
12113 	u8         sw_icm_start_addr[0x40];
12114 
12115 	u8         reserved_at_c0[0x140];
12116 };
12117 
12118 struct mlx5_ifc_geneve_tlv_option_bits {
12119 	u8         modify_field_select[0x40];
12120 
12121 	u8         reserved_at_40[0x18];
12122 	u8         geneve_option_fte_index[0x8];
12123 
12124 	u8         option_class[0x10];
12125 	u8         option_type[0x8];
12126 	u8         reserved_at_78[0x3];
12127 	u8         option_data_length[0x5];
12128 
12129 	u8         reserved_at_80[0x180];
12130 };
12131 
12132 struct mlx5_ifc_create_umem_in_bits {
12133 	u8         opcode[0x10];
12134 	u8         uid[0x10];
12135 
12136 	u8         reserved_at_20[0x10];
12137 	u8         op_mod[0x10];
12138 
12139 	u8         reserved_at_40[0x40];
12140 
12141 	struct mlx5_ifc_umem_bits  umem;
12142 };
12143 
12144 struct mlx5_ifc_create_umem_out_bits {
12145 	u8         status[0x8];
12146 	u8         reserved_at_8[0x18];
12147 
12148 	u8         syndrome[0x20];
12149 
12150 	u8         reserved_at_40[0x8];
12151 	u8         umem_id[0x18];
12152 
12153 	u8         reserved_at_60[0x20];
12154 };
12155 
12156 struct mlx5_ifc_destroy_umem_in_bits {
12157 	u8        opcode[0x10];
12158 	u8        uid[0x10];
12159 
12160 	u8        reserved_at_20[0x10];
12161 	u8        op_mod[0x10];
12162 
12163 	u8        reserved_at_40[0x8];
12164 	u8        umem_id[0x18];
12165 
12166 	u8        reserved_at_60[0x20];
12167 };
12168 
12169 struct mlx5_ifc_destroy_umem_out_bits {
12170 	u8        status[0x8];
12171 	u8        reserved_at_8[0x18];
12172 
12173 	u8        syndrome[0x20];
12174 
12175 	u8        reserved_at_40[0x40];
12176 };
12177 
12178 struct mlx5_ifc_create_uctx_in_bits {
12179 	u8         opcode[0x10];
12180 	u8         reserved_at_10[0x10];
12181 
12182 	u8         reserved_at_20[0x10];
12183 	u8         op_mod[0x10];
12184 
12185 	u8         reserved_at_40[0x40];
12186 
12187 	struct mlx5_ifc_uctx_bits  uctx;
12188 };
12189 
12190 struct mlx5_ifc_create_uctx_out_bits {
12191 	u8         status[0x8];
12192 	u8         reserved_at_8[0x18];
12193 
12194 	u8         syndrome[0x20];
12195 
12196 	u8         reserved_at_40[0x10];
12197 	u8         uid[0x10];
12198 
12199 	u8         reserved_at_60[0x20];
12200 };
12201 
12202 struct mlx5_ifc_destroy_uctx_in_bits {
12203 	u8         opcode[0x10];
12204 	u8         reserved_at_10[0x10];
12205 
12206 	u8         reserved_at_20[0x10];
12207 	u8         op_mod[0x10];
12208 
12209 	u8         reserved_at_40[0x10];
12210 	u8         uid[0x10];
12211 
12212 	u8         reserved_at_60[0x20];
12213 };
12214 
12215 struct mlx5_ifc_destroy_uctx_out_bits {
12216 	u8         status[0x8];
12217 	u8         reserved_at_8[0x18];
12218 
12219 	u8         syndrome[0x20];
12220 
12221 	u8          reserved_at_40[0x40];
12222 };
12223 
12224 struct mlx5_ifc_create_sw_icm_in_bits {
12225 	struct mlx5_ifc_general_obj_in_cmd_hdr_bits   hdr;
12226 	struct mlx5_ifc_sw_icm_bits		      sw_icm;
12227 };
12228 
12229 struct mlx5_ifc_create_geneve_tlv_option_in_bits {
12230 	struct mlx5_ifc_general_obj_in_cmd_hdr_bits   hdr;
12231 	struct mlx5_ifc_geneve_tlv_option_bits        geneve_tlv_opt;
12232 };
12233 
12234 struct mlx5_ifc_mtrc_string_db_param_bits {
12235 	u8         string_db_base_address[0x20];
12236 
12237 	u8         reserved_at_20[0x8];
12238 	u8         string_db_size[0x18];
12239 };
12240 
12241 struct mlx5_ifc_mtrc_cap_bits {
12242 	u8         trace_owner[0x1];
12243 	u8         trace_to_memory[0x1];
12244 	u8         reserved_at_2[0x4];
12245 	u8         trc_ver[0x2];
12246 	u8         reserved_at_8[0x14];
12247 	u8         num_string_db[0x4];
12248 
12249 	u8         first_string_trace[0x8];
12250 	u8         num_string_trace[0x8];
12251 	u8         reserved_at_30[0x28];
12252 
12253 	u8         log_max_trace_buffer_size[0x8];
12254 
12255 	u8         reserved_at_60[0x20];
12256 
12257 	struct mlx5_ifc_mtrc_string_db_param_bits string_db_param[8];
12258 
12259 	u8         reserved_at_280[0x180];
12260 };
12261 
12262 struct mlx5_ifc_mtrc_conf_bits {
12263 	u8         reserved_at_0[0x1c];
12264 	u8         trace_mode[0x4];
12265 	u8         reserved_at_20[0x18];
12266 	u8         log_trace_buffer_size[0x8];
12267 	u8         trace_mkey[0x20];
12268 	u8         reserved_at_60[0x3a0];
12269 };
12270 
12271 struct mlx5_ifc_mtrc_stdb_bits {
12272 	u8         string_db_index[0x4];
12273 	u8         reserved_at_4[0x4];
12274 	u8         read_size[0x18];
12275 	u8         start_offset[0x20];
12276 	u8         string_db_data[];
12277 };
12278 
12279 struct mlx5_ifc_mtrc_ctrl_bits {
12280 	u8         trace_status[0x2];
12281 	u8         reserved_at_2[0x2];
12282 	u8         arm_event[0x1];
12283 	u8         reserved_at_5[0xb];
12284 	u8         modify_field_select[0x10];
12285 	u8         reserved_at_20[0x2b];
12286 	u8         current_timestamp52_32[0x15];
12287 	u8         current_timestamp31_0[0x20];
12288 	u8         reserved_at_80[0x180];
12289 };
12290 
12291 struct mlx5_ifc_host_params_context_bits {
12292 	u8         host_number[0x8];
12293 	u8         reserved_at_8[0x7];
12294 	u8         host_pf_disabled[0x1];
12295 	u8         host_num_of_vfs[0x10];
12296 
12297 	u8         host_total_vfs[0x10];
12298 	u8         host_pci_bus[0x10];
12299 
12300 	u8         reserved_at_40[0x10];
12301 	u8         host_pci_device[0x10];
12302 
12303 	u8         reserved_at_60[0x10];
12304 	u8         host_pci_function[0x10];
12305 
12306 	u8         reserved_at_80[0x180];
12307 };
12308 
12309 struct mlx5_ifc_query_esw_functions_in_bits {
12310 	u8         opcode[0x10];
12311 	u8         reserved_at_10[0x10];
12312 
12313 	u8         reserved_at_20[0x10];
12314 	u8         op_mod[0x10];
12315 
12316 	u8         reserved_at_40[0x40];
12317 };
12318 
12319 struct mlx5_ifc_query_esw_functions_out_bits {
12320 	u8         status[0x8];
12321 	u8         reserved_at_8[0x18];
12322 
12323 	u8         syndrome[0x20];
12324 
12325 	u8         reserved_at_40[0x40];
12326 
12327 	struct mlx5_ifc_host_params_context_bits host_params_context;
12328 
12329 	u8         reserved_at_280[0x180];
12330 	u8         host_sf_enable[][0x40];
12331 };
12332 
12333 struct mlx5_ifc_sf_partition_bits {
12334 	u8         reserved_at_0[0x10];
12335 	u8         log_num_sf[0x8];
12336 	u8         log_sf_bar_size[0x8];
12337 };
12338 
12339 struct mlx5_ifc_query_sf_partitions_out_bits {
12340 	u8         status[0x8];
12341 	u8         reserved_at_8[0x18];
12342 
12343 	u8         syndrome[0x20];
12344 
12345 	u8         reserved_at_40[0x18];
12346 	u8         num_sf_partitions[0x8];
12347 
12348 	u8         reserved_at_60[0x20];
12349 
12350 	struct mlx5_ifc_sf_partition_bits sf_partition[];
12351 };
12352 
12353 struct mlx5_ifc_query_sf_partitions_in_bits {
12354 	u8         opcode[0x10];
12355 	u8         reserved_at_10[0x10];
12356 
12357 	u8         reserved_at_20[0x10];
12358 	u8         op_mod[0x10];
12359 
12360 	u8         reserved_at_40[0x40];
12361 };
12362 
12363 struct mlx5_ifc_dealloc_sf_out_bits {
12364 	u8         status[0x8];
12365 	u8         reserved_at_8[0x18];
12366 
12367 	u8         syndrome[0x20];
12368 
12369 	u8         reserved_at_40[0x40];
12370 };
12371 
12372 struct mlx5_ifc_dealloc_sf_in_bits {
12373 	u8         opcode[0x10];
12374 	u8         reserved_at_10[0x10];
12375 
12376 	u8         reserved_at_20[0x10];
12377 	u8         op_mod[0x10];
12378 
12379 	u8         reserved_at_40[0x10];
12380 	u8         function_id[0x10];
12381 
12382 	u8         reserved_at_60[0x20];
12383 };
12384 
12385 struct mlx5_ifc_alloc_sf_out_bits {
12386 	u8         status[0x8];
12387 	u8         reserved_at_8[0x18];
12388 
12389 	u8         syndrome[0x20];
12390 
12391 	u8         reserved_at_40[0x40];
12392 };
12393 
12394 struct mlx5_ifc_alloc_sf_in_bits {
12395 	u8         opcode[0x10];
12396 	u8         reserved_at_10[0x10];
12397 
12398 	u8         reserved_at_20[0x10];
12399 	u8         op_mod[0x10];
12400 
12401 	u8         reserved_at_40[0x10];
12402 	u8         function_id[0x10];
12403 
12404 	u8         reserved_at_60[0x20];
12405 };
12406 
12407 struct mlx5_ifc_affiliated_event_header_bits {
12408 	u8         reserved_at_0[0x10];
12409 	u8         obj_type[0x10];
12410 
12411 	u8         obj_id[0x20];
12412 };
12413 
12414 enum {
12415 	MLX5_HCA_CAP_GENERAL_OBJECT_TYPES_ENCRYPTION_KEY = BIT_ULL(0xc),
12416 	MLX5_HCA_CAP_GENERAL_OBJECT_TYPES_IPSEC = BIT_ULL(0x13),
12417 	MLX5_HCA_CAP_GENERAL_OBJECT_TYPES_SAMPLER = BIT_ULL(0x20),
12418 	MLX5_HCA_CAP_GENERAL_OBJECT_TYPES_FLOW_METER_ASO = BIT_ULL(0x24),
12419 };
12420 
12421 enum {
12422 	MLX5_GENERAL_OBJECT_TYPES_ENCRYPTION_KEY = 0xc,
12423 	MLX5_GENERAL_OBJECT_TYPES_IPSEC = 0x13,
12424 	MLX5_GENERAL_OBJECT_TYPES_SAMPLER = 0x20,
12425 	MLX5_GENERAL_OBJECT_TYPES_FLOW_METER_ASO = 0x24,
12426 	MLX5_GENERAL_OBJECT_TYPES_MACSEC = 0x27,
12427 	MLX5_GENERAL_OBJECT_TYPES_INT_KEK = 0x47,
12428 	MLX5_GENERAL_OBJECT_TYPES_FLOW_TABLE_ALIAS = 0xff15,
12429 };
12430 
12431 enum {
12432 	MLX5_IPSEC_OBJECT_ICV_LEN_16B,
12433 };
12434 
12435 enum {
12436 	MLX5_IPSEC_ASO_REG_C_0_1 = 0x0,
12437 	MLX5_IPSEC_ASO_REG_C_2_3 = 0x1,
12438 	MLX5_IPSEC_ASO_REG_C_4_5 = 0x2,
12439 	MLX5_IPSEC_ASO_REG_C_6_7 = 0x3,
12440 };
12441 
12442 enum {
12443 	MLX5_IPSEC_ASO_MODE              = 0x0,
12444 	MLX5_IPSEC_ASO_REPLAY_PROTECTION = 0x1,
12445 	MLX5_IPSEC_ASO_INC_SN            = 0x2,
12446 };
12447 
12448 enum {
12449 	MLX5_IPSEC_ASO_REPLAY_WIN_32BIT  = 0x0,
12450 	MLX5_IPSEC_ASO_REPLAY_WIN_64BIT  = 0x1,
12451 	MLX5_IPSEC_ASO_REPLAY_WIN_128BIT = 0x2,
12452 	MLX5_IPSEC_ASO_REPLAY_WIN_256BIT = 0x3,
12453 };
12454 
12455 struct mlx5_ifc_ipsec_aso_bits {
12456 	u8         valid[0x1];
12457 	u8         reserved_at_201[0x1];
12458 	u8         mode[0x2];
12459 	u8         window_sz[0x2];
12460 	u8         soft_lft_arm[0x1];
12461 	u8         hard_lft_arm[0x1];
12462 	u8         remove_flow_enable[0x1];
12463 	u8         esn_event_arm[0x1];
12464 	u8         reserved_at_20a[0x16];
12465 
12466 	u8         remove_flow_pkt_cnt[0x20];
12467 
12468 	u8         remove_flow_soft_lft[0x20];
12469 
12470 	u8         reserved_at_260[0x80];
12471 
12472 	u8         mode_parameter[0x20];
12473 
12474 	u8         replay_protection_window[0x100];
12475 };
12476 
12477 struct mlx5_ifc_ipsec_obj_bits {
12478 	u8         modify_field_select[0x40];
12479 	u8         full_offload[0x1];
12480 	u8         reserved_at_41[0x1];
12481 	u8         esn_en[0x1];
12482 	u8         esn_overlap[0x1];
12483 	u8         reserved_at_44[0x2];
12484 	u8         icv_length[0x2];
12485 	u8         reserved_at_48[0x4];
12486 	u8         aso_return_reg[0x4];
12487 	u8         reserved_at_50[0x10];
12488 
12489 	u8         esn_msb[0x20];
12490 
12491 	u8         reserved_at_80[0x8];
12492 	u8         dekn[0x18];
12493 
12494 	u8         salt[0x20];
12495 
12496 	u8         implicit_iv[0x40];
12497 
12498 	u8         reserved_at_100[0x8];
12499 	u8         ipsec_aso_access_pd[0x18];
12500 	u8         reserved_at_120[0xe0];
12501 
12502 	struct mlx5_ifc_ipsec_aso_bits ipsec_aso;
12503 };
12504 
12505 struct mlx5_ifc_create_ipsec_obj_in_bits {
12506 	struct mlx5_ifc_general_obj_in_cmd_hdr_bits general_obj_in_cmd_hdr;
12507 	struct mlx5_ifc_ipsec_obj_bits ipsec_object;
12508 };
12509 
12510 enum {
12511 	MLX5_MODIFY_IPSEC_BITMASK_ESN_OVERLAP = BIT(0),
12512 	MLX5_MODIFY_IPSEC_BITMASK_ESN_MSB = BIT(1),
12513 };
12514 
12515 struct mlx5_ifc_query_ipsec_obj_out_bits {
12516 	struct mlx5_ifc_general_obj_out_cmd_hdr_bits general_obj_out_cmd_hdr;
12517 	struct mlx5_ifc_ipsec_obj_bits ipsec_object;
12518 };
12519 
12520 struct mlx5_ifc_modify_ipsec_obj_in_bits {
12521 	struct mlx5_ifc_general_obj_in_cmd_hdr_bits general_obj_in_cmd_hdr;
12522 	struct mlx5_ifc_ipsec_obj_bits ipsec_object;
12523 };
12524 
12525 enum {
12526 	MLX5_MACSEC_ASO_REPLAY_PROTECTION = 0x1,
12527 };
12528 
12529 enum {
12530 	MLX5_MACSEC_ASO_REPLAY_WIN_32BIT  = 0x0,
12531 	MLX5_MACSEC_ASO_REPLAY_WIN_64BIT  = 0x1,
12532 	MLX5_MACSEC_ASO_REPLAY_WIN_128BIT = 0x2,
12533 	MLX5_MACSEC_ASO_REPLAY_WIN_256BIT = 0x3,
12534 };
12535 
12536 #define MLX5_MACSEC_ASO_INC_SN  0x2
12537 #define MLX5_MACSEC_ASO_REG_C_4_5 0x2
12538 
12539 struct mlx5_ifc_macsec_aso_bits {
12540 	u8    valid[0x1];
12541 	u8    reserved_at_1[0x1];
12542 	u8    mode[0x2];
12543 	u8    window_size[0x2];
12544 	u8    soft_lifetime_arm[0x1];
12545 	u8    hard_lifetime_arm[0x1];
12546 	u8    remove_flow_enable[0x1];
12547 	u8    epn_event_arm[0x1];
12548 	u8    reserved_at_a[0x16];
12549 
12550 	u8    remove_flow_packet_count[0x20];
12551 
12552 	u8    remove_flow_soft_lifetime[0x20];
12553 
12554 	u8    reserved_at_60[0x80];
12555 
12556 	u8    mode_parameter[0x20];
12557 
12558 	u8    replay_protection_window[8][0x20];
12559 };
12560 
12561 struct mlx5_ifc_macsec_offload_obj_bits {
12562 	u8    modify_field_select[0x40];
12563 
12564 	u8    confidentiality_en[0x1];
12565 	u8    reserved_at_41[0x1];
12566 	u8    epn_en[0x1];
12567 	u8    epn_overlap[0x1];
12568 	u8    reserved_at_44[0x2];
12569 	u8    confidentiality_offset[0x2];
12570 	u8    reserved_at_48[0x4];
12571 	u8    aso_return_reg[0x4];
12572 	u8    reserved_at_50[0x10];
12573 
12574 	u8    epn_msb[0x20];
12575 
12576 	u8    reserved_at_80[0x8];
12577 	u8    dekn[0x18];
12578 
12579 	u8    reserved_at_a0[0x20];
12580 
12581 	u8    sci[0x40];
12582 
12583 	u8    reserved_at_100[0x8];
12584 	u8    macsec_aso_access_pd[0x18];
12585 
12586 	u8    reserved_at_120[0x60];
12587 
12588 	u8    salt[3][0x20];
12589 
12590 	u8    reserved_at_1e0[0x20];
12591 
12592 	struct mlx5_ifc_macsec_aso_bits macsec_aso;
12593 };
12594 
12595 struct mlx5_ifc_create_macsec_obj_in_bits {
12596 	struct mlx5_ifc_general_obj_in_cmd_hdr_bits general_obj_in_cmd_hdr;
12597 	struct mlx5_ifc_macsec_offload_obj_bits macsec_object;
12598 };
12599 
12600 struct mlx5_ifc_modify_macsec_obj_in_bits {
12601 	struct mlx5_ifc_general_obj_in_cmd_hdr_bits general_obj_in_cmd_hdr;
12602 	struct mlx5_ifc_macsec_offload_obj_bits macsec_object;
12603 };
12604 
12605 enum {
12606 	MLX5_MODIFY_MACSEC_BITMASK_EPN_OVERLAP = BIT(0),
12607 	MLX5_MODIFY_MACSEC_BITMASK_EPN_MSB = BIT(1),
12608 };
12609 
12610 struct mlx5_ifc_query_macsec_obj_out_bits {
12611 	struct mlx5_ifc_general_obj_out_cmd_hdr_bits general_obj_out_cmd_hdr;
12612 	struct mlx5_ifc_macsec_offload_obj_bits macsec_object;
12613 };
12614 
12615 struct mlx5_ifc_wrapped_dek_bits {
12616 	u8         gcm_iv[0x60];
12617 
12618 	u8         reserved_at_60[0x20];
12619 
12620 	u8         const0[0x1];
12621 	u8         key_size[0x1];
12622 	u8         reserved_at_82[0x2];
12623 	u8         key2_invalid[0x1];
12624 	u8         reserved_at_85[0x3];
12625 	u8         pd[0x18];
12626 
12627 	u8         key_purpose[0x5];
12628 	u8         reserved_at_a5[0x13];
12629 	u8         kek_id[0x8];
12630 
12631 	u8         reserved_at_c0[0x40];
12632 
12633 	u8         key1[0x8][0x20];
12634 
12635 	u8         key2[0x8][0x20];
12636 
12637 	u8         reserved_at_300[0x40];
12638 
12639 	u8         const1[0x1];
12640 	u8         reserved_at_341[0x1f];
12641 
12642 	u8         reserved_at_360[0x20];
12643 
12644 	u8         auth_tag[0x80];
12645 };
12646 
12647 struct mlx5_ifc_encryption_key_obj_bits {
12648 	u8         modify_field_select[0x40];
12649 
12650 	u8         state[0x8];
12651 	u8         sw_wrapped[0x1];
12652 	u8         reserved_at_49[0xb];
12653 	u8         key_size[0x4];
12654 	u8         reserved_at_58[0x4];
12655 	u8         key_purpose[0x4];
12656 
12657 	u8         reserved_at_60[0x8];
12658 	u8         pd[0x18];
12659 
12660 	u8         reserved_at_80[0x100];
12661 
12662 	u8         opaque[0x40];
12663 
12664 	u8         reserved_at_1c0[0x40];
12665 
12666 	u8         key[8][0x80];
12667 
12668 	u8         sw_wrapped_dek[8][0x80];
12669 
12670 	u8         reserved_at_a00[0x600];
12671 };
12672 
12673 struct mlx5_ifc_create_encryption_key_in_bits {
12674 	struct mlx5_ifc_general_obj_in_cmd_hdr_bits general_obj_in_cmd_hdr;
12675 	struct mlx5_ifc_encryption_key_obj_bits encryption_key_object;
12676 };
12677 
12678 struct mlx5_ifc_modify_encryption_key_in_bits {
12679 	struct mlx5_ifc_general_obj_in_cmd_hdr_bits general_obj_in_cmd_hdr;
12680 	struct mlx5_ifc_encryption_key_obj_bits encryption_key_object;
12681 };
12682 
12683 enum {
12684 	MLX5_FLOW_METER_MODE_BYTES_IP_LENGTH		= 0x0,
12685 	MLX5_FLOW_METER_MODE_BYTES_CALC_WITH_L2		= 0x1,
12686 	MLX5_FLOW_METER_MODE_BYTES_CALC_WITH_L2_IPG	= 0x2,
12687 	MLX5_FLOW_METER_MODE_NUM_PACKETS		= 0x3,
12688 };
12689 
12690 struct mlx5_ifc_flow_meter_parameters_bits {
12691 	u8         valid[0x1];
12692 	u8         bucket_overflow[0x1];
12693 	u8         start_color[0x2];
12694 	u8         both_buckets_on_green[0x1];
12695 	u8         reserved_at_5[0x1];
12696 	u8         meter_mode[0x2];
12697 	u8         reserved_at_8[0x18];
12698 
12699 	u8         reserved_at_20[0x20];
12700 
12701 	u8         reserved_at_40[0x3];
12702 	u8         cbs_exponent[0x5];
12703 	u8         cbs_mantissa[0x8];
12704 	u8         reserved_at_50[0x3];
12705 	u8         cir_exponent[0x5];
12706 	u8         cir_mantissa[0x8];
12707 
12708 	u8         reserved_at_60[0x20];
12709 
12710 	u8         reserved_at_80[0x3];
12711 	u8         ebs_exponent[0x5];
12712 	u8         ebs_mantissa[0x8];
12713 	u8         reserved_at_90[0x3];
12714 	u8         eir_exponent[0x5];
12715 	u8         eir_mantissa[0x8];
12716 
12717 	u8         reserved_at_a0[0x60];
12718 };
12719 
12720 struct mlx5_ifc_flow_meter_aso_obj_bits {
12721 	u8         modify_field_select[0x40];
12722 
12723 	u8         reserved_at_40[0x40];
12724 
12725 	u8         reserved_at_80[0x8];
12726 	u8         meter_aso_access_pd[0x18];
12727 
12728 	u8         reserved_at_a0[0x160];
12729 
12730 	struct mlx5_ifc_flow_meter_parameters_bits flow_meter_parameters[2];
12731 };
12732 
12733 struct mlx5_ifc_create_flow_meter_aso_obj_in_bits {
12734 	struct mlx5_ifc_general_obj_in_cmd_hdr_bits hdr;
12735 	struct mlx5_ifc_flow_meter_aso_obj_bits flow_meter_aso_obj;
12736 };
12737 
12738 struct mlx5_ifc_int_kek_obj_bits {
12739 	u8         modify_field_select[0x40];
12740 
12741 	u8         state[0x8];
12742 	u8         auto_gen[0x1];
12743 	u8         reserved_at_49[0xb];
12744 	u8         key_size[0x4];
12745 	u8         reserved_at_58[0x8];
12746 
12747 	u8         reserved_at_60[0x8];
12748 	u8         pd[0x18];
12749 
12750 	u8         reserved_at_80[0x180];
12751 	u8         key[8][0x80];
12752 
12753 	u8         reserved_at_600[0x200];
12754 };
12755 
12756 struct mlx5_ifc_create_int_kek_obj_in_bits {
12757 	struct mlx5_ifc_general_obj_in_cmd_hdr_bits general_obj_in_cmd_hdr;
12758 	struct mlx5_ifc_int_kek_obj_bits int_kek_object;
12759 };
12760 
12761 struct mlx5_ifc_create_int_kek_obj_out_bits {
12762 	struct mlx5_ifc_general_obj_out_cmd_hdr_bits general_obj_out_cmd_hdr;
12763 	struct mlx5_ifc_int_kek_obj_bits int_kek_object;
12764 };
12765 
12766 struct mlx5_ifc_sampler_obj_bits {
12767 	u8         modify_field_select[0x40];
12768 
12769 	u8         table_type[0x8];
12770 	u8         level[0x8];
12771 	u8         reserved_at_50[0xf];
12772 	u8         ignore_flow_level[0x1];
12773 
12774 	u8         sample_ratio[0x20];
12775 
12776 	u8         reserved_at_80[0x8];
12777 	u8         sample_table_id[0x18];
12778 
12779 	u8         reserved_at_a0[0x8];
12780 	u8         default_table_id[0x18];
12781 
12782 	u8         sw_steering_icm_address_rx[0x40];
12783 	u8         sw_steering_icm_address_tx[0x40];
12784 
12785 	u8         reserved_at_140[0xa0];
12786 };
12787 
12788 struct mlx5_ifc_create_sampler_obj_in_bits {
12789 	struct mlx5_ifc_general_obj_in_cmd_hdr_bits general_obj_in_cmd_hdr;
12790 	struct mlx5_ifc_sampler_obj_bits sampler_object;
12791 };
12792 
12793 struct mlx5_ifc_query_sampler_obj_out_bits {
12794 	struct mlx5_ifc_general_obj_out_cmd_hdr_bits general_obj_out_cmd_hdr;
12795 	struct mlx5_ifc_sampler_obj_bits sampler_object;
12796 };
12797 
12798 enum {
12799 	MLX5_GENERAL_OBJECT_TYPE_ENCRYPTION_KEY_KEY_SIZE_128 = 0x0,
12800 	MLX5_GENERAL_OBJECT_TYPE_ENCRYPTION_KEY_KEY_SIZE_256 = 0x1,
12801 };
12802 
12803 enum {
12804 	MLX5_GENERAL_OBJECT_TYPE_ENCRYPTION_KEY_PURPOSE_TLS = 0x1,
12805 	MLX5_GENERAL_OBJECT_TYPE_ENCRYPTION_KEY_PURPOSE_IPSEC = 0x2,
12806 	MLX5_GENERAL_OBJECT_TYPE_ENCRYPTION_KEY_PURPOSE_MACSEC = 0x4,
12807 };
12808 
12809 struct mlx5_ifc_tls_static_params_bits {
12810 	u8         const_2[0x2];
12811 	u8         tls_version[0x4];
12812 	u8         const_1[0x2];
12813 	u8         reserved_at_8[0x14];
12814 	u8         encryption_standard[0x4];
12815 
12816 	u8         reserved_at_20[0x20];
12817 
12818 	u8         initial_record_number[0x40];
12819 
12820 	u8         resync_tcp_sn[0x20];
12821 
12822 	u8         gcm_iv[0x20];
12823 
12824 	u8         implicit_iv[0x40];
12825 
12826 	u8         reserved_at_100[0x8];
12827 	u8         dek_index[0x18];
12828 
12829 	u8         reserved_at_120[0xe0];
12830 };
12831 
12832 struct mlx5_ifc_tls_progress_params_bits {
12833 	u8         next_record_tcp_sn[0x20];
12834 
12835 	u8         hw_resync_tcp_sn[0x20];
12836 
12837 	u8         record_tracker_state[0x2];
12838 	u8         auth_state[0x2];
12839 	u8         reserved_at_44[0x4];
12840 	u8         hw_offset_record_number[0x18];
12841 };
12842 
12843 enum {
12844 	MLX5_MTT_PERM_READ	= 1 << 0,
12845 	MLX5_MTT_PERM_WRITE	= 1 << 1,
12846 	MLX5_MTT_PERM_RW	= MLX5_MTT_PERM_READ | MLX5_MTT_PERM_WRITE,
12847 };
12848 
12849 enum {
12850 	MLX5_SUSPEND_VHCA_IN_OP_MOD_SUSPEND_INITIATOR  = 0x0,
12851 	MLX5_SUSPEND_VHCA_IN_OP_MOD_SUSPEND_RESPONDER  = 0x1,
12852 };
12853 
12854 struct mlx5_ifc_suspend_vhca_in_bits {
12855 	u8         opcode[0x10];
12856 	u8         uid[0x10];
12857 
12858 	u8         reserved_at_20[0x10];
12859 	u8         op_mod[0x10];
12860 
12861 	u8         reserved_at_40[0x10];
12862 	u8         vhca_id[0x10];
12863 
12864 	u8         reserved_at_60[0x20];
12865 };
12866 
12867 struct mlx5_ifc_suspend_vhca_out_bits {
12868 	u8         status[0x8];
12869 	u8         reserved_at_8[0x18];
12870 
12871 	u8         syndrome[0x20];
12872 
12873 	u8         reserved_at_40[0x40];
12874 };
12875 
12876 enum {
12877 	MLX5_RESUME_VHCA_IN_OP_MOD_RESUME_RESPONDER  = 0x0,
12878 	MLX5_RESUME_VHCA_IN_OP_MOD_RESUME_INITIATOR  = 0x1,
12879 };
12880 
12881 struct mlx5_ifc_resume_vhca_in_bits {
12882 	u8         opcode[0x10];
12883 	u8         uid[0x10];
12884 
12885 	u8         reserved_at_20[0x10];
12886 	u8         op_mod[0x10];
12887 
12888 	u8         reserved_at_40[0x10];
12889 	u8         vhca_id[0x10];
12890 
12891 	u8         reserved_at_60[0x20];
12892 };
12893 
12894 struct mlx5_ifc_resume_vhca_out_bits {
12895 	u8         status[0x8];
12896 	u8         reserved_at_8[0x18];
12897 
12898 	u8         syndrome[0x20];
12899 
12900 	u8         reserved_at_40[0x40];
12901 };
12902 
12903 struct mlx5_ifc_query_vhca_migration_state_in_bits {
12904 	u8         opcode[0x10];
12905 	u8         uid[0x10];
12906 
12907 	u8         reserved_at_20[0x10];
12908 	u8         op_mod[0x10];
12909 
12910 	u8         incremental[0x1];
12911 	u8         chunk[0x1];
12912 	u8         reserved_at_42[0xe];
12913 	u8         vhca_id[0x10];
12914 
12915 	u8         reserved_at_60[0x20];
12916 };
12917 
12918 struct mlx5_ifc_query_vhca_migration_state_out_bits {
12919 	u8         status[0x8];
12920 	u8         reserved_at_8[0x18];
12921 
12922 	u8         syndrome[0x20];
12923 
12924 	u8         reserved_at_40[0x40];
12925 
12926 	u8         required_umem_size[0x20];
12927 
12928 	u8         reserved_at_a0[0x20];
12929 
12930 	u8         remaining_total_size[0x40];
12931 
12932 	u8         reserved_at_100[0x100];
12933 };
12934 
12935 struct mlx5_ifc_save_vhca_state_in_bits {
12936 	u8         opcode[0x10];
12937 	u8         uid[0x10];
12938 
12939 	u8         reserved_at_20[0x10];
12940 	u8         op_mod[0x10];
12941 
12942 	u8         incremental[0x1];
12943 	u8         set_track[0x1];
12944 	u8         reserved_at_42[0xe];
12945 	u8         vhca_id[0x10];
12946 
12947 	u8         reserved_at_60[0x20];
12948 
12949 	u8         va[0x40];
12950 
12951 	u8         mkey[0x20];
12952 
12953 	u8         size[0x20];
12954 };
12955 
12956 struct mlx5_ifc_save_vhca_state_out_bits {
12957 	u8         status[0x8];
12958 	u8         reserved_at_8[0x18];
12959 
12960 	u8         syndrome[0x20];
12961 
12962 	u8         actual_image_size[0x20];
12963 
12964 	u8         next_required_umem_size[0x20];
12965 };
12966 
12967 struct mlx5_ifc_load_vhca_state_in_bits {
12968 	u8         opcode[0x10];
12969 	u8         uid[0x10];
12970 
12971 	u8         reserved_at_20[0x10];
12972 	u8         op_mod[0x10];
12973 
12974 	u8         reserved_at_40[0x10];
12975 	u8         vhca_id[0x10];
12976 
12977 	u8         reserved_at_60[0x20];
12978 
12979 	u8         va[0x40];
12980 
12981 	u8         mkey[0x20];
12982 
12983 	u8         size[0x20];
12984 };
12985 
12986 struct mlx5_ifc_load_vhca_state_out_bits {
12987 	u8         status[0x8];
12988 	u8         reserved_at_8[0x18];
12989 
12990 	u8         syndrome[0x20];
12991 
12992 	u8         reserved_at_40[0x40];
12993 };
12994 
12995 struct mlx5_ifc_adv_virtualization_cap_bits {
12996 	u8         reserved_at_0[0x3];
12997 	u8         pg_track_log_max_num[0x5];
12998 	u8         pg_track_max_num_range[0x8];
12999 	u8         pg_track_log_min_addr_space[0x8];
13000 	u8         pg_track_log_max_addr_space[0x8];
13001 
13002 	u8         reserved_at_20[0x3];
13003 	u8         pg_track_log_min_msg_size[0x5];
13004 	u8         reserved_at_28[0x3];
13005 	u8         pg_track_log_max_msg_size[0x5];
13006 	u8         reserved_at_30[0x3];
13007 	u8         pg_track_log_min_page_size[0x5];
13008 	u8         reserved_at_38[0x3];
13009 	u8         pg_track_log_max_page_size[0x5];
13010 
13011 	u8         reserved_at_40[0x7c0];
13012 };
13013 
13014 struct mlx5_ifc_page_track_report_entry_bits {
13015 	u8         dirty_address_high[0x20];
13016 
13017 	u8         dirty_address_low[0x20];
13018 };
13019 
13020 enum {
13021 	MLX5_PAGE_TRACK_STATE_TRACKING,
13022 	MLX5_PAGE_TRACK_STATE_REPORTING,
13023 	MLX5_PAGE_TRACK_STATE_ERROR,
13024 };
13025 
13026 struct mlx5_ifc_page_track_range_bits {
13027 	u8         start_address[0x40];
13028 
13029 	u8         length[0x40];
13030 };
13031 
13032 struct mlx5_ifc_page_track_bits {
13033 	u8         modify_field_select[0x40];
13034 
13035 	u8         reserved_at_40[0x10];
13036 	u8         vhca_id[0x10];
13037 
13038 	u8         reserved_at_60[0x20];
13039 
13040 	u8         state[0x4];
13041 	u8         track_type[0x4];
13042 	u8         log_addr_space_size[0x8];
13043 	u8         reserved_at_90[0x3];
13044 	u8         log_page_size[0x5];
13045 	u8         reserved_at_98[0x3];
13046 	u8         log_msg_size[0x5];
13047 
13048 	u8         reserved_at_a0[0x8];
13049 	u8         reporting_qpn[0x18];
13050 
13051 	u8         reserved_at_c0[0x18];
13052 	u8         num_ranges[0x8];
13053 
13054 	u8         reserved_at_e0[0x20];
13055 
13056 	u8         range_start_address[0x40];
13057 
13058 	u8         length[0x40];
13059 
13060 	struct     mlx5_ifc_page_track_range_bits track_range[0];
13061 };
13062 
13063 struct mlx5_ifc_create_page_track_obj_in_bits {
13064 	struct mlx5_ifc_general_obj_in_cmd_hdr_bits general_obj_in_cmd_hdr;
13065 	struct mlx5_ifc_page_track_bits obj_context;
13066 };
13067 
13068 struct mlx5_ifc_modify_page_track_obj_in_bits {
13069 	struct mlx5_ifc_general_obj_in_cmd_hdr_bits general_obj_in_cmd_hdr;
13070 	struct mlx5_ifc_page_track_bits obj_context;
13071 };
13072 
13073 struct mlx5_ifc_query_page_track_obj_out_bits {
13074 	struct mlx5_ifc_general_obj_out_cmd_hdr_bits general_obj_out_cmd_hdr;
13075 	struct mlx5_ifc_page_track_bits obj_context;
13076 };
13077 
13078 struct mlx5_ifc_msecq_reg_bits {
13079 	u8         reserved_at_0[0x20];
13080 
13081 	u8         reserved_at_20[0x12];
13082 	u8         network_option[0x2];
13083 	u8         local_ssm_code[0x4];
13084 	u8         local_enhanced_ssm_code[0x8];
13085 
13086 	u8         local_clock_identity[0x40];
13087 
13088 	u8         reserved_at_80[0x180];
13089 };
13090 
13091 enum {
13092 	MLX5_MSEES_FIELD_SELECT_ENABLE			= BIT(0),
13093 	MLX5_MSEES_FIELD_SELECT_ADMIN_STATUS		= BIT(1),
13094 	MLX5_MSEES_FIELD_SELECT_ADMIN_FREQ_MEASURE	= BIT(2),
13095 };
13096 
13097 enum mlx5_msees_admin_status {
13098 	MLX5_MSEES_ADMIN_STATUS_FREE_RUNNING		= 0x0,
13099 	MLX5_MSEES_ADMIN_STATUS_TRACK			= 0x1,
13100 };
13101 
13102 enum mlx5_msees_oper_status {
13103 	MLX5_MSEES_OPER_STATUS_FREE_RUNNING		= 0x0,
13104 	MLX5_MSEES_OPER_STATUS_SELF_TRACK		= 0x1,
13105 	MLX5_MSEES_OPER_STATUS_OTHER_TRACK		= 0x2,
13106 	MLX5_MSEES_OPER_STATUS_HOLDOVER			= 0x3,
13107 	MLX5_MSEES_OPER_STATUS_FAIL_HOLDOVER		= 0x4,
13108 	MLX5_MSEES_OPER_STATUS_FAIL_FREE_RUNNING	= 0x5,
13109 };
13110 
13111 enum mlx5_msees_failure_reason {
13112 	MLX5_MSEES_FAILURE_REASON_UNDEFINED_ERROR		= 0x0,
13113 	MLX5_MSEES_FAILURE_REASON_PORT_DOWN			= 0x1,
13114 	MLX5_MSEES_FAILURE_REASON_TOO_HIGH_FREQUENCY_DIFF	= 0x2,
13115 	MLX5_MSEES_FAILURE_REASON_NET_SYNCHRONIZER_DEVICE_ERROR	= 0x3,
13116 	MLX5_MSEES_FAILURE_REASON_LACK_OF_RESOURCES		= 0x4,
13117 };
13118 
13119 struct mlx5_ifc_msees_reg_bits {
13120 	u8         reserved_at_0[0x8];
13121 	u8         local_port[0x8];
13122 	u8         pnat[0x2];
13123 	u8         lp_msb[0x2];
13124 	u8         reserved_at_14[0xc];
13125 
13126 	u8         field_select[0x20];
13127 
13128 	u8         admin_status[0x4];
13129 	u8         oper_status[0x4];
13130 	u8         ho_acq[0x1];
13131 	u8         reserved_at_49[0xc];
13132 	u8         admin_freq_measure[0x1];
13133 	u8         oper_freq_measure[0x1];
13134 	u8         failure_reason[0x9];
13135 
13136 	u8         frequency_diff[0x20];
13137 
13138 	u8         reserved_at_80[0x180];
13139 };
13140 
13141 #endif /* MLX5_IFC_H */
13142