1 /* 2 * Copyright (c) 2013-2015, Mellanox Technologies, Ltd. All rights reserved. 3 * 4 * This software is available to you under a choice of one of two 5 * licenses. You may choose to be licensed under the terms of the GNU 6 * General Public License (GPL) Version 2, available from the file 7 * COPYING in the main directory of this source tree, or the 8 * OpenIB.org BSD license below: 9 * 10 * Redistribution and use in source and binary forms, with or 11 * without modification, are permitted provided that the following 12 * conditions are met: 13 * 14 * - Redistributions of source code must retain the above 15 * copyright notice, this list of conditions and the following 16 * disclaimer. 17 * 18 * - Redistributions in binary form must reproduce the above 19 * copyright notice, this list of conditions and the following 20 * disclaimer in the documentation and/or other materials 21 * provided with the distribution. 22 * 23 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, 24 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF 25 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND 26 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS 27 * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN 28 * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN 29 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE 30 * SOFTWARE. 31 */ 32 #ifndef MLX5_IFC_H 33 #define MLX5_IFC_H 34 35 #include "mlx5_ifc_fpga.h" 36 37 enum { 38 MLX5_EVENT_TYPE_CODING_COMPLETION_EVENTS = 0x0, 39 MLX5_EVENT_TYPE_CODING_PATH_MIGRATED_SUCCEEDED = 0x1, 40 MLX5_EVENT_TYPE_CODING_COMMUNICATION_ESTABLISHED = 0x2, 41 MLX5_EVENT_TYPE_CODING_SEND_QUEUE_DRAINED = 0x3, 42 MLX5_EVENT_TYPE_CODING_LAST_WQE_REACHED = 0x13, 43 MLX5_EVENT_TYPE_CODING_SRQ_LIMIT = 0x14, 44 MLX5_EVENT_TYPE_CODING_DCT_ALL_CONNECTIONS_CLOSED = 0x1c, 45 MLX5_EVENT_TYPE_CODING_DCT_ACCESS_KEY_VIOLATION = 0x1d, 46 MLX5_EVENT_TYPE_CODING_CQ_ERROR = 0x4, 47 MLX5_EVENT_TYPE_CODING_LOCAL_WQ_CATASTROPHIC_ERROR = 0x5, 48 MLX5_EVENT_TYPE_CODING_PATH_MIGRATION_FAILED = 0x7, 49 MLX5_EVENT_TYPE_CODING_PAGE_FAULT_EVENT = 0xc, 50 MLX5_EVENT_TYPE_CODING_INVALID_REQUEST_LOCAL_WQ_ERROR = 0x10, 51 MLX5_EVENT_TYPE_CODING_LOCAL_ACCESS_VIOLATION_WQ_ERROR = 0x11, 52 MLX5_EVENT_TYPE_CODING_LOCAL_SRQ_CATASTROPHIC_ERROR = 0x12, 53 MLX5_EVENT_TYPE_CODING_INTERNAL_ERROR = 0x8, 54 MLX5_EVENT_TYPE_CODING_PORT_STATE_CHANGE = 0x9, 55 MLX5_EVENT_TYPE_CODING_GPIO_EVENT = 0x15, 56 MLX5_EVENT_TYPE_CODING_REMOTE_CONFIGURATION_PROTOCOL_EVENT = 0x19, 57 MLX5_EVENT_TYPE_CODING_DOORBELL_BLUEFLAME_CONGESTION_EVENT = 0x1a, 58 MLX5_EVENT_TYPE_CODING_STALL_VL_EVENT = 0x1b, 59 MLX5_EVENT_TYPE_CODING_DROPPED_PACKET_LOGGED_EVENT = 0x1f, 60 MLX5_EVENT_TYPE_CODING_COMMAND_INTERFACE_COMPLETION = 0xa, 61 MLX5_EVENT_TYPE_CODING_PAGE_REQUEST = 0xb, 62 MLX5_EVENT_TYPE_CODING_FPGA_ERROR = 0x20, 63 MLX5_EVENT_TYPE_CODING_FPGA_QP_ERROR = 0x21 64 }; 65 66 enum { 67 MLX5_SET_HCA_CAP_OP_MOD_GENERAL_DEVICE = 0x0, 68 MLX5_SET_HCA_CAP_OP_MOD_ETHERNET_OFFLOADS = 0x1, 69 MLX5_SET_HCA_CAP_OP_MOD_ODP = 0x2, 70 MLX5_SET_HCA_CAP_OP_MOD_ATOMIC = 0x3, 71 MLX5_SET_HCA_CAP_OP_MOD_ROCE = 0x4, 72 MLX5_SET_HCA_CAP_OP_MOD_IPSEC = 0x15, 73 MLX5_SET_HCA_CAP_OP_MOD_GENERAL_DEVICE2 = 0x20, 74 MLX5_SET_HCA_CAP_OP_MOD_PORT_SELECTION = 0x25, 75 }; 76 77 enum { 78 MLX5_SHARED_RESOURCE_UID = 0xffff, 79 }; 80 81 enum { 82 MLX5_OBJ_TYPE_SW_ICM = 0x0008, 83 MLX5_OBJ_TYPE_GENEVE_TLV_OPT = 0x000b, 84 MLX5_OBJ_TYPE_VIRTIO_NET_Q = 0x000d, 85 MLX5_OBJ_TYPE_VIRTIO_Q_COUNTERS = 0x001c, 86 MLX5_OBJ_TYPE_MATCH_DEFINER = 0x0018, 87 MLX5_OBJ_TYPE_HEADER_MODIFY_ARGUMENT = 0x23, 88 MLX5_OBJ_TYPE_STC = 0x0040, 89 MLX5_OBJ_TYPE_RTC = 0x0041, 90 MLX5_OBJ_TYPE_STE = 0x0042, 91 MLX5_OBJ_TYPE_MODIFY_HDR_PATTERN = 0x0043, 92 MLX5_OBJ_TYPE_PAGE_TRACK = 0x46, 93 MLX5_OBJ_TYPE_MKEY = 0xff01, 94 MLX5_OBJ_TYPE_QP = 0xff02, 95 MLX5_OBJ_TYPE_PSV = 0xff03, 96 MLX5_OBJ_TYPE_RMP = 0xff04, 97 MLX5_OBJ_TYPE_XRC_SRQ = 0xff05, 98 MLX5_OBJ_TYPE_RQ = 0xff06, 99 MLX5_OBJ_TYPE_SQ = 0xff07, 100 MLX5_OBJ_TYPE_TIR = 0xff08, 101 MLX5_OBJ_TYPE_TIS = 0xff09, 102 MLX5_OBJ_TYPE_DCT = 0xff0a, 103 MLX5_OBJ_TYPE_XRQ = 0xff0b, 104 MLX5_OBJ_TYPE_RQT = 0xff0e, 105 MLX5_OBJ_TYPE_FLOW_COUNTER = 0xff0f, 106 MLX5_OBJ_TYPE_CQ = 0xff10, 107 MLX5_OBJ_TYPE_FT_ALIAS = 0xff15, 108 }; 109 110 enum { 111 MLX5_GENERAL_OBJ_TYPES_CAP_SW_ICM = (1ULL << MLX5_OBJ_TYPE_SW_ICM), 112 MLX5_GENERAL_OBJ_TYPES_CAP_GENEVE_TLV_OPT = (1ULL << 11), 113 MLX5_GENERAL_OBJ_TYPES_CAP_VIRTIO_NET_Q = (1ULL << 13), 114 MLX5_GENERAL_OBJ_TYPES_CAP_HEADER_MODIFY_ARGUMENT = 115 (1ULL << MLX5_OBJ_TYPE_HEADER_MODIFY_ARGUMENT), 116 MLX5_GENERAL_OBJ_TYPES_CAP_MACSEC_OFFLOAD = (1ULL << 39), 117 }; 118 119 enum { 120 MLX5_CMD_OP_QUERY_HCA_CAP = 0x100, 121 MLX5_CMD_OP_QUERY_ADAPTER = 0x101, 122 MLX5_CMD_OP_INIT_HCA = 0x102, 123 MLX5_CMD_OP_TEARDOWN_HCA = 0x103, 124 MLX5_CMD_OP_ENABLE_HCA = 0x104, 125 MLX5_CMD_OP_DISABLE_HCA = 0x105, 126 MLX5_CMD_OP_QUERY_PAGES = 0x107, 127 MLX5_CMD_OP_MANAGE_PAGES = 0x108, 128 MLX5_CMD_OP_SET_HCA_CAP = 0x109, 129 MLX5_CMD_OP_QUERY_ISSI = 0x10a, 130 MLX5_CMD_OP_SET_ISSI = 0x10b, 131 MLX5_CMD_OP_SET_DRIVER_VERSION = 0x10d, 132 MLX5_CMD_OP_QUERY_SF_PARTITION = 0x111, 133 MLX5_CMD_OP_ALLOC_SF = 0x113, 134 MLX5_CMD_OP_DEALLOC_SF = 0x114, 135 MLX5_CMD_OP_SUSPEND_VHCA = 0x115, 136 MLX5_CMD_OP_RESUME_VHCA = 0x116, 137 MLX5_CMD_OP_QUERY_VHCA_MIGRATION_STATE = 0x117, 138 MLX5_CMD_OP_SAVE_VHCA_STATE = 0x118, 139 MLX5_CMD_OP_LOAD_VHCA_STATE = 0x119, 140 MLX5_CMD_OP_CREATE_MKEY = 0x200, 141 MLX5_CMD_OP_QUERY_MKEY = 0x201, 142 MLX5_CMD_OP_DESTROY_MKEY = 0x202, 143 MLX5_CMD_OP_QUERY_SPECIAL_CONTEXTS = 0x203, 144 MLX5_CMD_OP_PAGE_FAULT_RESUME = 0x204, 145 MLX5_CMD_OP_ALLOC_MEMIC = 0x205, 146 MLX5_CMD_OP_DEALLOC_MEMIC = 0x206, 147 MLX5_CMD_OP_MODIFY_MEMIC = 0x207, 148 MLX5_CMD_OP_CREATE_EQ = 0x301, 149 MLX5_CMD_OP_DESTROY_EQ = 0x302, 150 MLX5_CMD_OP_QUERY_EQ = 0x303, 151 MLX5_CMD_OP_GEN_EQE = 0x304, 152 MLX5_CMD_OP_CREATE_CQ = 0x400, 153 MLX5_CMD_OP_DESTROY_CQ = 0x401, 154 MLX5_CMD_OP_QUERY_CQ = 0x402, 155 MLX5_CMD_OP_MODIFY_CQ = 0x403, 156 MLX5_CMD_OP_CREATE_QP = 0x500, 157 MLX5_CMD_OP_DESTROY_QP = 0x501, 158 MLX5_CMD_OP_RST2INIT_QP = 0x502, 159 MLX5_CMD_OP_INIT2RTR_QP = 0x503, 160 MLX5_CMD_OP_RTR2RTS_QP = 0x504, 161 MLX5_CMD_OP_RTS2RTS_QP = 0x505, 162 MLX5_CMD_OP_SQERR2RTS_QP = 0x506, 163 MLX5_CMD_OP_2ERR_QP = 0x507, 164 MLX5_CMD_OP_2RST_QP = 0x50a, 165 MLX5_CMD_OP_QUERY_QP = 0x50b, 166 MLX5_CMD_OP_SQD_RTS_QP = 0x50c, 167 MLX5_CMD_OP_INIT2INIT_QP = 0x50e, 168 MLX5_CMD_OP_CREATE_PSV = 0x600, 169 MLX5_CMD_OP_DESTROY_PSV = 0x601, 170 MLX5_CMD_OP_CREATE_SRQ = 0x700, 171 MLX5_CMD_OP_DESTROY_SRQ = 0x701, 172 MLX5_CMD_OP_QUERY_SRQ = 0x702, 173 MLX5_CMD_OP_ARM_RQ = 0x703, 174 MLX5_CMD_OP_CREATE_XRC_SRQ = 0x705, 175 MLX5_CMD_OP_DESTROY_XRC_SRQ = 0x706, 176 MLX5_CMD_OP_QUERY_XRC_SRQ = 0x707, 177 MLX5_CMD_OP_ARM_XRC_SRQ = 0x708, 178 MLX5_CMD_OP_CREATE_DCT = 0x710, 179 MLX5_CMD_OP_DESTROY_DCT = 0x711, 180 MLX5_CMD_OP_DRAIN_DCT = 0x712, 181 MLX5_CMD_OP_QUERY_DCT = 0x713, 182 MLX5_CMD_OP_ARM_DCT_FOR_KEY_VIOLATION = 0x714, 183 MLX5_CMD_OP_CREATE_XRQ = 0x717, 184 MLX5_CMD_OP_DESTROY_XRQ = 0x718, 185 MLX5_CMD_OP_QUERY_XRQ = 0x719, 186 MLX5_CMD_OP_ARM_XRQ = 0x71a, 187 MLX5_CMD_OP_QUERY_XRQ_DC_PARAMS_ENTRY = 0x725, 188 MLX5_CMD_OP_SET_XRQ_DC_PARAMS_ENTRY = 0x726, 189 MLX5_CMD_OP_QUERY_XRQ_ERROR_PARAMS = 0x727, 190 MLX5_CMD_OP_RELEASE_XRQ_ERROR = 0x729, 191 MLX5_CMD_OP_MODIFY_XRQ = 0x72a, 192 MLX5_CMD_OP_QUERY_ESW_FUNCTIONS = 0x740, 193 MLX5_CMD_OP_QUERY_VPORT_STATE = 0x750, 194 MLX5_CMD_OP_MODIFY_VPORT_STATE = 0x751, 195 MLX5_CMD_OP_QUERY_ESW_VPORT_CONTEXT = 0x752, 196 MLX5_CMD_OP_MODIFY_ESW_VPORT_CONTEXT = 0x753, 197 MLX5_CMD_OP_QUERY_NIC_VPORT_CONTEXT = 0x754, 198 MLX5_CMD_OP_MODIFY_NIC_VPORT_CONTEXT = 0x755, 199 MLX5_CMD_OP_QUERY_ROCE_ADDRESS = 0x760, 200 MLX5_CMD_OP_SET_ROCE_ADDRESS = 0x761, 201 MLX5_CMD_OP_QUERY_HCA_VPORT_CONTEXT = 0x762, 202 MLX5_CMD_OP_MODIFY_HCA_VPORT_CONTEXT = 0x763, 203 MLX5_CMD_OP_QUERY_HCA_VPORT_GID = 0x764, 204 MLX5_CMD_OP_QUERY_HCA_VPORT_PKEY = 0x765, 205 MLX5_CMD_OP_QUERY_VNIC_ENV = 0x76f, 206 MLX5_CMD_OP_QUERY_VPORT_COUNTER = 0x770, 207 MLX5_CMD_OP_ALLOC_Q_COUNTER = 0x771, 208 MLX5_CMD_OP_DEALLOC_Q_COUNTER = 0x772, 209 MLX5_CMD_OP_QUERY_Q_COUNTER = 0x773, 210 MLX5_CMD_OP_SET_MONITOR_COUNTER = 0x774, 211 MLX5_CMD_OP_ARM_MONITOR_COUNTER = 0x775, 212 MLX5_CMD_OP_SET_PP_RATE_LIMIT = 0x780, 213 MLX5_CMD_OP_QUERY_RATE_LIMIT = 0x781, 214 MLX5_CMD_OP_CREATE_SCHEDULING_ELEMENT = 0x782, 215 MLX5_CMD_OP_DESTROY_SCHEDULING_ELEMENT = 0x783, 216 MLX5_CMD_OP_QUERY_SCHEDULING_ELEMENT = 0x784, 217 MLX5_CMD_OP_MODIFY_SCHEDULING_ELEMENT = 0x785, 218 MLX5_CMD_OP_CREATE_QOS_PARA_VPORT = 0x786, 219 MLX5_CMD_OP_DESTROY_QOS_PARA_VPORT = 0x787, 220 MLX5_CMD_OP_ALLOC_PD = 0x800, 221 MLX5_CMD_OP_DEALLOC_PD = 0x801, 222 MLX5_CMD_OP_ALLOC_UAR = 0x802, 223 MLX5_CMD_OP_DEALLOC_UAR = 0x803, 224 MLX5_CMD_OP_CONFIG_INT_MODERATION = 0x804, 225 MLX5_CMD_OP_ACCESS_REG = 0x805, 226 MLX5_CMD_OP_ATTACH_TO_MCG = 0x806, 227 MLX5_CMD_OP_DETACH_FROM_MCG = 0x807, 228 MLX5_CMD_OP_GET_DROPPED_PACKET_LOG = 0x80a, 229 MLX5_CMD_OP_MAD_IFC = 0x50d, 230 MLX5_CMD_OP_QUERY_MAD_DEMUX = 0x80b, 231 MLX5_CMD_OP_SET_MAD_DEMUX = 0x80c, 232 MLX5_CMD_OP_NOP = 0x80d, 233 MLX5_CMD_OP_ALLOC_XRCD = 0x80e, 234 MLX5_CMD_OP_DEALLOC_XRCD = 0x80f, 235 MLX5_CMD_OP_ALLOC_TRANSPORT_DOMAIN = 0x816, 236 MLX5_CMD_OP_DEALLOC_TRANSPORT_DOMAIN = 0x817, 237 MLX5_CMD_OP_QUERY_CONG_STATUS = 0x822, 238 MLX5_CMD_OP_MODIFY_CONG_STATUS = 0x823, 239 MLX5_CMD_OP_QUERY_CONG_PARAMS = 0x824, 240 MLX5_CMD_OP_MODIFY_CONG_PARAMS = 0x825, 241 MLX5_CMD_OP_QUERY_CONG_STATISTICS = 0x826, 242 MLX5_CMD_OP_ADD_VXLAN_UDP_DPORT = 0x827, 243 MLX5_CMD_OP_DELETE_VXLAN_UDP_DPORT = 0x828, 244 MLX5_CMD_OP_SET_L2_TABLE_ENTRY = 0x829, 245 MLX5_CMD_OP_QUERY_L2_TABLE_ENTRY = 0x82a, 246 MLX5_CMD_OP_DELETE_L2_TABLE_ENTRY = 0x82b, 247 MLX5_CMD_OP_SET_WOL_ROL = 0x830, 248 MLX5_CMD_OP_QUERY_WOL_ROL = 0x831, 249 MLX5_CMD_OP_CREATE_LAG = 0x840, 250 MLX5_CMD_OP_MODIFY_LAG = 0x841, 251 MLX5_CMD_OP_QUERY_LAG = 0x842, 252 MLX5_CMD_OP_DESTROY_LAG = 0x843, 253 MLX5_CMD_OP_CREATE_VPORT_LAG = 0x844, 254 MLX5_CMD_OP_DESTROY_VPORT_LAG = 0x845, 255 MLX5_CMD_OP_CREATE_TIR = 0x900, 256 MLX5_CMD_OP_MODIFY_TIR = 0x901, 257 MLX5_CMD_OP_DESTROY_TIR = 0x902, 258 MLX5_CMD_OP_QUERY_TIR = 0x903, 259 MLX5_CMD_OP_CREATE_SQ = 0x904, 260 MLX5_CMD_OP_MODIFY_SQ = 0x905, 261 MLX5_CMD_OP_DESTROY_SQ = 0x906, 262 MLX5_CMD_OP_QUERY_SQ = 0x907, 263 MLX5_CMD_OP_CREATE_RQ = 0x908, 264 MLX5_CMD_OP_MODIFY_RQ = 0x909, 265 MLX5_CMD_OP_SET_DELAY_DROP_PARAMS = 0x910, 266 MLX5_CMD_OP_DESTROY_RQ = 0x90a, 267 MLX5_CMD_OP_QUERY_RQ = 0x90b, 268 MLX5_CMD_OP_CREATE_RMP = 0x90c, 269 MLX5_CMD_OP_MODIFY_RMP = 0x90d, 270 MLX5_CMD_OP_DESTROY_RMP = 0x90e, 271 MLX5_CMD_OP_QUERY_RMP = 0x90f, 272 MLX5_CMD_OP_CREATE_TIS = 0x912, 273 MLX5_CMD_OP_MODIFY_TIS = 0x913, 274 MLX5_CMD_OP_DESTROY_TIS = 0x914, 275 MLX5_CMD_OP_QUERY_TIS = 0x915, 276 MLX5_CMD_OP_CREATE_RQT = 0x916, 277 MLX5_CMD_OP_MODIFY_RQT = 0x917, 278 MLX5_CMD_OP_DESTROY_RQT = 0x918, 279 MLX5_CMD_OP_QUERY_RQT = 0x919, 280 MLX5_CMD_OP_SET_FLOW_TABLE_ROOT = 0x92f, 281 MLX5_CMD_OP_CREATE_FLOW_TABLE = 0x930, 282 MLX5_CMD_OP_DESTROY_FLOW_TABLE = 0x931, 283 MLX5_CMD_OP_QUERY_FLOW_TABLE = 0x932, 284 MLX5_CMD_OP_CREATE_FLOW_GROUP = 0x933, 285 MLX5_CMD_OP_DESTROY_FLOW_GROUP = 0x934, 286 MLX5_CMD_OP_QUERY_FLOW_GROUP = 0x935, 287 MLX5_CMD_OP_SET_FLOW_TABLE_ENTRY = 0x936, 288 MLX5_CMD_OP_QUERY_FLOW_TABLE_ENTRY = 0x937, 289 MLX5_CMD_OP_DELETE_FLOW_TABLE_ENTRY = 0x938, 290 MLX5_CMD_OP_ALLOC_FLOW_COUNTER = 0x939, 291 MLX5_CMD_OP_DEALLOC_FLOW_COUNTER = 0x93a, 292 MLX5_CMD_OP_QUERY_FLOW_COUNTER = 0x93b, 293 MLX5_CMD_OP_MODIFY_FLOW_TABLE = 0x93c, 294 MLX5_CMD_OP_ALLOC_PACKET_REFORMAT_CONTEXT = 0x93d, 295 MLX5_CMD_OP_DEALLOC_PACKET_REFORMAT_CONTEXT = 0x93e, 296 MLX5_CMD_OP_QUERY_PACKET_REFORMAT_CONTEXT = 0x93f, 297 MLX5_CMD_OP_ALLOC_MODIFY_HEADER_CONTEXT = 0x940, 298 MLX5_CMD_OP_DEALLOC_MODIFY_HEADER_CONTEXT = 0x941, 299 MLX5_CMD_OP_QUERY_MODIFY_HEADER_CONTEXT = 0x942, 300 MLX5_CMD_OP_FPGA_CREATE_QP = 0x960, 301 MLX5_CMD_OP_FPGA_MODIFY_QP = 0x961, 302 MLX5_CMD_OP_FPGA_QUERY_QP = 0x962, 303 MLX5_CMD_OP_FPGA_DESTROY_QP = 0x963, 304 MLX5_CMD_OP_FPGA_QUERY_QP_COUNTERS = 0x964, 305 MLX5_CMD_OP_CREATE_GENERAL_OBJECT = 0xa00, 306 MLX5_CMD_OP_MODIFY_GENERAL_OBJECT = 0xa01, 307 MLX5_CMD_OP_QUERY_GENERAL_OBJECT = 0xa02, 308 MLX5_CMD_OP_DESTROY_GENERAL_OBJECT = 0xa03, 309 MLX5_CMD_OP_CREATE_UCTX = 0xa04, 310 MLX5_CMD_OP_DESTROY_UCTX = 0xa06, 311 MLX5_CMD_OP_CREATE_UMEM = 0xa08, 312 MLX5_CMD_OP_DESTROY_UMEM = 0xa0a, 313 MLX5_CMD_OP_SYNC_STEERING = 0xb00, 314 MLX5_CMD_OP_QUERY_VHCA_STATE = 0xb0d, 315 MLX5_CMD_OP_MODIFY_VHCA_STATE = 0xb0e, 316 MLX5_CMD_OP_SYNC_CRYPTO = 0xb12, 317 MLX5_CMD_OP_ALLOW_OTHER_VHCA_ACCESS = 0xb16, 318 MLX5_CMD_OP_GENERATE_WQE = 0xb17, 319 MLX5_CMD_OP_MAX 320 }; 321 322 /* Valid range for general commands that don't work over an object */ 323 enum { 324 MLX5_CMD_OP_GENERAL_START = 0xb00, 325 MLX5_CMD_OP_GENERAL_END = 0xd00, 326 }; 327 328 enum { 329 MLX5_FT_NIC_RX_2_NIC_RX_RDMA = BIT(0), 330 MLX5_FT_NIC_TX_RDMA_2_NIC_TX = BIT(1), 331 }; 332 333 enum { 334 MLX5_CMD_OP_MOD_UPDATE_HEADER_MODIFY_ARGUMENT = 0x1, 335 }; 336 337 struct mlx5_ifc_flow_table_fields_supported_bits { 338 u8 outer_dmac[0x1]; 339 u8 outer_smac[0x1]; 340 u8 outer_ether_type[0x1]; 341 u8 outer_ip_version[0x1]; 342 u8 outer_first_prio[0x1]; 343 u8 outer_first_cfi[0x1]; 344 u8 outer_first_vid[0x1]; 345 u8 outer_ipv4_ttl[0x1]; 346 u8 outer_second_prio[0x1]; 347 u8 outer_second_cfi[0x1]; 348 u8 outer_second_vid[0x1]; 349 u8 reserved_at_b[0x1]; 350 u8 outer_sip[0x1]; 351 u8 outer_dip[0x1]; 352 u8 outer_frag[0x1]; 353 u8 outer_ip_protocol[0x1]; 354 u8 outer_ip_ecn[0x1]; 355 u8 outer_ip_dscp[0x1]; 356 u8 outer_udp_sport[0x1]; 357 u8 outer_udp_dport[0x1]; 358 u8 outer_tcp_sport[0x1]; 359 u8 outer_tcp_dport[0x1]; 360 u8 outer_tcp_flags[0x1]; 361 u8 outer_gre_protocol[0x1]; 362 u8 outer_gre_key[0x1]; 363 u8 outer_vxlan_vni[0x1]; 364 u8 outer_geneve_vni[0x1]; 365 u8 outer_geneve_oam[0x1]; 366 u8 outer_geneve_protocol_type[0x1]; 367 u8 outer_geneve_opt_len[0x1]; 368 u8 source_vhca_port[0x1]; 369 u8 source_eswitch_port[0x1]; 370 371 u8 inner_dmac[0x1]; 372 u8 inner_smac[0x1]; 373 u8 inner_ether_type[0x1]; 374 u8 inner_ip_version[0x1]; 375 u8 inner_first_prio[0x1]; 376 u8 inner_first_cfi[0x1]; 377 u8 inner_first_vid[0x1]; 378 u8 reserved_at_27[0x1]; 379 u8 inner_second_prio[0x1]; 380 u8 inner_second_cfi[0x1]; 381 u8 inner_second_vid[0x1]; 382 u8 reserved_at_2b[0x1]; 383 u8 inner_sip[0x1]; 384 u8 inner_dip[0x1]; 385 u8 inner_frag[0x1]; 386 u8 inner_ip_protocol[0x1]; 387 u8 inner_ip_ecn[0x1]; 388 u8 inner_ip_dscp[0x1]; 389 u8 inner_udp_sport[0x1]; 390 u8 inner_udp_dport[0x1]; 391 u8 inner_tcp_sport[0x1]; 392 u8 inner_tcp_dport[0x1]; 393 u8 inner_tcp_flags[0x1]; 394 u8 reserved_at_37[0x9]; 395 396 u8 geneve_tlv_option_0_data[0x1]; 397 u8 geneve_tlv_option_0_exist[0x1]; 398 u8 reserved_at_42[0x3]; 399 u8 outer_first_mpls_over_udp[0x4]; 400 u8 outer_first_mpls_over_gre[0x4]; 401 u8 inner_first_mpls[0x4]; 402 u8 outer_first_mpls[0x4]; 403 u8 reserved_at_55[0x2]; 404 u8 outer_esp_spi[0x1]; 405 u8 reserved_at_58[0x2]; 406 u8 bth_dst_qp[0x1]; 407 u8 reserved_at_5b[0x5]; 408 409 u8 reserved_at_60[0x18]; 410 u8 metadata_reg_c_7[0x1]; 411 u8 metadata_reg_c_6[0x1]; 412 u8 metadata_reg_c_5[0x1]; 413 u8 metadata_reg_c_4[0x1]; 414 u8 metadata_reg_c_3[0x1]; 415 u8 metadata_reg_c_2[0x1]; 416 u8 metadata_reg_c_1[0x1]; 417 u8 metadata_reg_c_0[0x1]; 418 }; 419 420 /* Table 2170 - Flow Table Fields Supported 2 Format */ 421 struct mlx5_ifc_flow_table_fields_supported_2_bits { 422 u8 reserved_at_0[0x2]; 423 u8 inner_l4_type[0x1]; 424 u8 outer_l4_type[0x1]; 425 u8 reserved_at_4[0xa]; 426 u8 bth_opcode[0x1]; 427 u8 reserved_at_f[0x1]; 428 u8 tunnel_header_0_1[0x1]; 429 u8 reserved_at_11[0xf]; 430 431 u8 reserved_at_20[0x60]; 432 }; 433 434 struct mlx5_ifc_flow_table_prop_layout_bits { 435 u8 ft_support[0x1]; 436 u8 reserved_at_1[0x1]; 437 u8 flow_counter[0x1]; 438 u8 flow_modify_en[0x1]; 439 u8 modify_root[0x1]; 440 u8 identified_miss_table_mode[0x1]; 441 u8 flow_table_modify[0x1]; 442 u8 reformat[0x1]; 443 u8 decap[0x1]; 444 u8 reset_root_to_default[0x1]; 445 u8 pop_vlan[0x1]; 446 u8 push_vlan[0x1]; 447 u8 reserved_at_c[0x1]; 448 u8 pop_vlan_2[0x1]; 449 u8 push_vlan_2[0x1]; 450 u8 reformat_and_vlan_action[0x1]; 451 u8 reserved_at_10[0x1]; 452 u8 sw_owner[0x1]; 453 u8 reformat_l3_tunnel_to_l2[0x1]; 454 u8 reformat_l2_to_l3_tunnel[0x1]; 455 u8 reformat_and_modify_action[0x1]; 456 u8 ignore_flow_level[0x1]; 457 u8 reserved_at_16[0x1]; 458 u8 table_miss_action_domain[0x1]; 459 u8 termination_table[0x1]; 460 u8 reformat_and_fwd_to_table[0x1]; 461 u8 reserved_at_1a[0x2]; 462 u8 ipsec_encrypt[0x1]; 463 u8 ipsec_decrypt[0x1]; 464 u8 sw_owner_v2[0x1]; 465 u8 reserved_at_1f[0x1]; 466 467 u8 termination_table_raw_traffic[0x1]; 468 u8 reserved_at_21[0x1]; 469 u8 log_max_ft_size[0x6]; 470 u8 log_max_modify_header_context[0x8]; 471 u8 max_modify_header_actions[0x8]; 472 u8 max_ft_level[0x8]; 473 474 u8 reformat_add_esp_trasport[0x1]; 475 u8 reformat_l2_to_l3_esp_tunnel[0x1]; 476 u8 reformat_add_esp_transport_over_udp[0x1]; 477 u8 reformat_del_esp_trasport[0x1]; 478 u8 reformat_l3_esp_tunnel_to_l2[0x1]; 479 u8 reformat_del_esp_transport_over_udp[0x1]; 480 u8 execute_aso[0x1]; 481 u8 reserved_at_47[0x19]; 482 483 u8 reserved_at_60[0x2]; 484 u8 reformat_insert[0x1]; 485 u8 reformat_remove[0x1]; 486 u8 macsec_encrypt[0x1]; 487 u8 macsec_decrypt[0x1]; 488 u8 reserved_at_66[0x2]; 489 u8 reformat_add_macsec[0x1]; 490 u8 reformat_remove_macsec[0x1]; 491 u8 reparse[0x1]; 492 u8 reserved_at_6b[0x1]; 493 u8 cross_vhca_object[0x1]; 494 u8 reformat_l2_to_l3_audp_tunnel[0x1]; 495 u8 reformat_l3_audp_tunnel_to_l2[0x1]; 496 u8 ignore_flow_level_rtc_valid[0x1]; 497 u8 reserved_at_70[0x8]; 498 u8 log_max_ft_num[0x8]; 499 500 u8 reserved_at_80[0x10]; 501 u8 log_max_flow_counter[0x8]; 502 u8 log_max_destination[0x8]; 503 504 u8 reserved_at_a0[0x18]; 505 u8 log_max_flow[0x8]; 506 507 u8 reserved_at_c0[0x40]; 508 509 struct mlx5_ifc_flow_table_fields_supported_bits ft_field_support; 510 511 struct mlx5_ifc_flow_table_fields_supported_bits ft_field_bitmask_support; 512 }; 513 514 struct mlx5_ifc_odp_per_transport_service_cap_bits { 515 u8 send[0x1]; 516 u8 receive[0x1]; 517 u8 write[0x1]; 518 u8 read[0x1]; 519 u8 atomic[0x1]; 520 u8 srq_receive[0x1]; 521 u8 reserved_at_6[0x1a]; 522 }; 523 524 struct mlx5_ifc_ipv4_layout_bits { 525 u8 reserved_at_0[0x60]; 526 527 u8 ipv4[0x20]; 528 }; 529 530 struct mlx5_ifc_ipv6_layout_bits { 531 u8 ipv6[16][0x8]; 532 }; 533 534 struct mlx5_ifc_ipv6_simple_layout_bits { 535 u8 ipv6_127_96[0x20]; 536 u8 ipv6_95_64[0x20]; 537 u8 ipv6_63_32[0x20]; 538 u8 ipv6_31_0[0x20]; 539 }; 540 541 union mlx5_ifc_ipv6_layout_ipv4_layout_auto_bits { 542 struct mlx5_ifc_ipv6_simple_layout_bits ipv6_simple_layout; 543 struct mlx5_ifc_ipv6_layout_bits ipv6_layout; 544 struct mlx5_ifc_ipv4_layout_bits ipv4_layout; 545 u8 reserved_at_0[0x80]; 546 }; 547 548 enum { 549 MLX5_PACKET_L4_TYPE_NONE, 550 MLX5_PACKET_L4_TYPE_TCP, 551 MLX5_PACKET_L4_TYPE_UDP, 552 }; 553 554 struct mlx5_ifc_fte_match_set_lyr_2_4_bits { 555 u8 smac_47_16[0x20]; 556 557 u8 smac_15_0[0x10]; 558 u8 ethertype[0x10]; 559 560 u8 dmac_47_16[0x20]; 561 562 u8 dmac_15_0[0x10]; 563 u8 first_prio[0x3]; 564 u8 first_cfi[0x1]; 565 u8 first_vid[0xc]; 566 567 u8 ip_protocol[0x8]; 568 u8 ip_dscp[0x6]; 569 u8 ip_ecn[0x2]; 570 u8 cvlan_tag[0x1]; 571 u8 svlan_tag[0x1]; 572 u8 frag[0x1]; 573 u8 ip_version[0x4]; 574 u8 tcp_flags[0x9]; 575 576 u8 tcp_sport[0x10]; 577 u8 tcp_dport[0x10]; 578 579 u8 l4_type[0x2]; 580 u8 reserved_at_c2[0xe]; 581 u8 ipv4_ihl[0x4]; 582 u8 reserved_at_c4[0x4]; 583 584 u8 ttl_hoplimit[0x8]; 585 586 u8 udp_sport[0x10]; 587 u8 udp_dport[0x10]; 588 589 union mlx5_ifc_ipv6_layout_ipv4_layout_auto_bits src_ipv4_src_ipv6; 590 591 union mlx5_ifc_ipv6_layout_ipv4_layout_auto_bits dst_ipv4_dst_ipv6; 592 }; 593 594 struct mlx5_ifc_nvgre_key_bits { 595 u8 hi[0x18]; 596 u8 lo[0x8]; 597 }; 598 599 union mlx5_ifc_gre_key_bits { 600 struct mlx5_ifc_nvgre_key_bits nvgre; 601 u8 key[0x20]; 602 }; 603 604 struct mlx5_ifc_fte_match_set_misc_bits { 605 u8 gre_c_present[0x1]; 606 u8 reserved_at_1[0x1]; 607 u8 gre_k_present[0x1]; 608 u8 gre_s_present[0x1]; 609 u8 source_vhca_port[0x4]; 610 u8 source_sqn[0x18]; 611 612 u8 source_eswitch_owner_vhca_id[0x10]; 613 u8 source_port[0x10]; 614 615 u8 outer_second_prio[0x3]; 616 u8 outer_second_cfi[0x1]; 617 u8 outer_second_vid[0xc]; 618 u8 inner_second_prio[0x3]; 619 u8 inner_second_cfi[0x1]; 620 u8 inner_second_vid[0xc]; 621 622 u8 outer_second_cvlan_tag[0x1]; 623 u8 inner_second_cvlan_tag[0x1]; 624 u8 outer_second_svlan_tag[0x1]; 625 u8 inner_second_svlan_tag[0x1]; 626 u8 reserved_at_64[0xc]; 627 u8 gre_protocol[0x10]; 628 629 union mlx5_ifc_gre_key_bits gre_key; 630 631 u8 vxlan_vni[0x18]; 632 u8 bth_opcode[0x8]; 633 634 u8 geneve_vni[0x18]; 635 u8 reserved_at_d8[0x6]; 636 u8 geneve_tlv_option_0_exist[0x1]; 637 u8 geneve_oam[0x1]; 638 639 u8 reserved_at_e0[0xc]; 640 u8 outer_ipv6_flow_label[0x14]; 641 642 u8 reserved_at_100[0xc]; 643 u8 inner_ipv6_flow_label[0x14]; 644 645 u8 reserved_at_120[0xa]; 646 u8 geneve_opt_len[0x6]; 647 u8 geneve_protocol_type[0x10]; 648 649 u8 reserved_at_140[0x8]; 650 u8 bth_dst_qp[0x18]; 651 u8 inner_esp_spi[0x20]; 652 u8 outer_esp_spi[0x20]; 653 u8 reserved_at_1a0[0x60]; 654 }; 655 656 struct mlx5_ifc_fte_match_mpls_bits { 657 u8 mpls_label[0x14]; 658 u8 mpls_exp[0x3]; 659 u8 mpls_s_bos[0x1]; 660 u8 mpls_ttl[0x8]; 661 }; 662 663 struct mlx5_ifc_fte_match_set_misc2_bits { 664 struct mlx5_ifc_fte_match_mpls_bits outer_first_mpls; 665 666 struct mlx5_ifc_fte_match_mpls_bits inner_first_mpls; 667 668 struct mlx5_ifc_fte_match_mpls_bits outer_first_mpls_over_gre; 669 670 struct mlx5_ifc_fte_match_mpls_bits outer_first_mpls_over_udp; 671 672 u8 metadata_reg_c_7[0x20]; 673 674 u8 metadata_reg_c_6[0x20]; 675 676 u8 metadata_reg_c_5[0x20]; 677 678 u8 metadata_reg_c_4[0x20]; 679 680 u8 metadata_reg_c_3[0x20]; 681 682 u8 metadata_reg_c_2[0x20]; 683 684 u8 metadata_reg_c_1[0x20]; 685 686 u8 metadata_reg_c_0[0x20]; 687 688 u8 metadata_reg_a[0x20]; 689 690 u8 reserved_at_1a0[0x8]; 691 692 u8 macsec_syndrome[0x8]; 693 u8 ipsec_syndrome[0x8]; 694 u8 reserved_at_1b8[0x8]; 695 696 u8 reserved_at_1c0[0x40]; 697 }; 698 699 struct mlx5_ifc_fte_match_set_misc3_bits { 700 u8 inner_tcp_seq_num[0x20]; 701 702 u8 outer_tcp_seq_num[0x20]; 703 704 u8 inner_tcp_ack_num[0x20]; 705 706 u8 outer_tcp_ack_num[0x20]; 707 708 u8 reserved_at_80[0x8]; 709 u8 outer_vxlan_gpe_vni[0x18]; 710 711 u8 outer_vxlan_gpe_next_protocol[0x8]; 712 u8 outer_vxlan_gpe_flags[0x8]; 713 u8 reserved_at_b0[0x10]; 714 715 u8 icmp_header_data[0x20]; 716 717 u8 icmpv6_header_data[0x20]; 718 719 u8 icmp_type[0x8]; 720 u8 icmp_code[0x8]; 721 u8 icmpv6_type[0x8]; 722 u8 icmpv6_code[0x8]; 723 724 u8 geneve_tlv_option_0_data[0x20]; 725 726 u8 gtpu_teid[0x20]; 727 728 u8 gtpu_msg_type[0x8]; 729 u8 gtpu_msg_flags[0x8]; 730 u8 reserved_at_170[0x10]; 731 732 u8 gtpu_dw_2[0x20]; 733 734 u8 gtpu_first_ext_dw_0[0x20]; 735 736 u8 gtpu_dw_0[0x20]; 737 738 u8 reserved_at_1e0[0x20]; 739 }; 740 741 struct mlx5_ifc_fte_match_set_misc4_bits { 742 u8 prog_sample_field_value_0[0x20]; 743 744 u8 prog_sample_field_id_0[0x20]; 745 746 u8 prog_sample_field_value_1[0x20]; 747 748 u8 prog_sample_field_id_1[0x20]; 749 750 u8 prog_sample_field_value_2[0x20]; 751 752 u8 prog_sample_field_id_2[0x20]; 753 754 u8 prog_sample_field_value_3[0x20]; 755 756 u8 prog_sample_field_id_3[0x20]; 757 758 u8 reserved_at_100[0x100]; 759 }; 760 761 struct mlx5_ifc_fte_match_set_misc5_bits { 762 u8 macsec_tag_0[0x20]; 763 764 u8 macsec_tag_1[0x20]; 765 766 u8 macsec_tag_2[0x20]; 767 768 u8 macsec_tag_3[0x20]; 769 770 u8 tunnel_header_0[0x20]; 771 772 u8 tunnel_header_1[0x20]; 773 774 u8 tunnel_header_2[0x20]; 775 776 u8 tunnel_header_3[0x20]; 777 778 u8 reserved_at_100[0x100]; 779 }; 780 781 struct mlx5_ifc_cmd_pas_bits { 782 u8 pa_h[0x20]; 783 784 u8 pa_l[0x14]; 785 u8 reserved_at_34[0xc]; 786 }; 787 788 struct mlx5_ifc_uint64_bits { 789 u8 hi[0x20]; 790 791 u8 lo[0x20]; 792 }; 793 794 enum { 795 MLX5_ADS_STAT_RATE_NO_LIMIT = 0x0, 796 MLX5_ADS_STAT_RATE_2_5GBPS = 0x7, 797 MLX5_ADS_STAT_RATE_10GBPS = 0x8, 798 MLX5_ADS_STAT_RATE_30GBPS = 0x9, 799 MLX5_ADS_STAT_RATE_5GBPS = 0xa, 800 MLX5_ADS_STAT_RATE_20GBPS = 0xb, 801 MLX5_ADS_STAT_RATE_40GBPS = 0xc, 802 MLX5_ADS_STAT_RATE_60GBPS = 0xd, 803 MLX5_ADS_STAT_RATE_80GBPS = 0xe, 804 MLX5_ADS_STAT_RATE_120GBPS = 0xf, 805 }; 806 807 struct mlx5_ifc_ads_bits { 808 u8 fl[0x1]; 809 u8 free_ar[0x1]; 810 u8 reserved_at_2[0xe]; 811 u8 pkey_index[0x10]; 812 813 u8 plane_index[0x8]; 814 u8 grh[0x1]; 815 u8 mlid[0x7]; 816 u8 rlid[0x10]; 817 818 u8 ack_timeout[0x5]; 819 u8 reserved_at_45[0x3]; 820 u8 src_addr_index[0x8]; 821 u8 reserved_at_50[0x4]; 822 u8 stat_rate[0x4]; 823 u8 hop_limit[0x8]; 824 825 u8 reserved_at_60[0x4]; 826 u8 tclass[0x8]; 827 u8 flow_label[0x14]; 828 829 u8 rgid_rip[16][0x8]; 830 831 u8 reserved_at_100[0x4]; 832 u8 f_dscp[0x1]; 833 u8 f_ecn[0x1]; 834 u8 reserved_at_106[0x1]; 835 u8 f_eth_prio[0x1]; 836 u8 ecn[0x2]; 837 u8 dscp[0x6]; 838 u8 udp_sport[0x10]; 839 840 u8 dei_cfi[0x1]; 841 u8 eth_prio[0x3]; 842 u8 sl[0x4]; 843 u8 vhca_port_num[0x8]; 844 u8 rmac_47_32[0x10]; 845 846 u8 rmac_31_0[0x20]; 847 }; 848 849 struct mlx5_ifc_flow_table_nic_cap_bits { 850 u8 nic_rx_multi_path_tirs[0x1]; 851 u8 nic_rx_multi_path_tirs_fts[0x1]; 852 u8 allow_sniffer_and_nic_rx_shared_tir[0x1]; 853 u8 reserved_at_3[0x4]; 854 u8 sw_owner_reformat_supported[0x1]; 855 u8 reserved_at_8[0x18]; 856 857 u8 encap_general_header[0x1]; 858 u8 reserved_at_21[0xa]; 859 u8 log_max_packet_reformat_context[0x5]; 860 u8 reserved_at_30[0x6]; 861 u8 max_encap_header_size[0xa]; 862 u8 reserved_at_40[0x1c0]; 863 864 struct mlx5_ifc_flow_table_prop_layout_bits flow_table_properties_nic_receive; 865 866 struct mlx5_ifc_flow_table_prop_layout_bits flow_table_properties_nic_receive_rdma; 867 868 struct mlx5_ifc_flow_table_prop_layout_bits flow_table_properties_nic_receive_sniffer; 869 870 struct mlx5_ifc_flow_table_prop_layout_bits flow_table_properties_nic_transmit; 871 872 struct mlx5_ifc_flow_table_prop_layout_bits flow_table_properties_nic_transmit_rdma; 873 874 struct mlx5_ifc_flow_table_prop_layout_bits flow_table_properties_nic_transmit_sniffer; 875 876 u8 reserved_at_e00[0x600]; 877 878 struct mlx5_ifc_flow_table_fields_supported_2_bits ft_field_support_2_nic_receive; 879 880 u8 reserved_at_1480[0x80]; 881 882 struct mlx5_ifc_flow_table_fields_supported_2_bits ft_field_support_2_nic_receive_rdma; 883 884 u8 reserved_at_1580[0x280]; 885 886 struct mlx5_ifc_flow_table_fields_supported_2_bits ft_field_support_2_nic_transmit_rdma; 887 888 u8 reserved_at_1880[0x780]; 889 890 u8 sw_steering_nic_rx_action_drop_icm_address[0x40]; 891 892 u8 sw_steering_nic_tx_action_drop_icm_address[0x40]; 893 894 u8 sw_steering_nic_tx_action_allow_icm_address[0x40]; 895 896 u8 reserved_at_20c0[0x5f40]; 897 }; 898 899 struct mlx5_ifc_port_selection_cap_bits { 900 u8 reserved_at_0[0x10]; 901 u8 port_select_flow_table[0x1]; 902 u8 reserved_at_11[0x1]; 903 u8 port_select_flow_table_bypass[0x1]; 904 u8 reserved_at_13[0xd]; 905 906 u8 reserved_at_20[0x1e0]; 907 908 struct mlx5_ifc_flow_table_prop_layout_bits flow_table_properties_port_selection; 909 910 struct mlx5_ifc_flow_table_fields_supported_2_bits ft_field_support_2_port_selection; 911 912 u8 reserved_at_480[0x7b80]; 913 }; 914 915 enum { 916 MLX5_FDB_TO_VPORT_REG_C_0 = 0x01, 917 MLX5_FDB_TO_VPORT_REG_C_1 = 0x02, 918 MLX5_FDB_TO_VPORT_REG_C_2 = 0x04, 919 MLX5_FDB_TO_VPORT_REG_C_3 = 0x08, 920 MLX5_FDB_TO_VPORT_REG_C_4 = 0x10, 921 MLX5_FDB_TO_VPORT_REG_C_5 = 0x20, 922 MLX5_FDB_TO_VPORT_REG_C_6 = 0x40, 923 MLX5_FDB_TO_VPORT_REG_C_7 = 0x80, 924 }; 925 926 struct mlx5_ifc_flow_table_eswitch_cap_bits { 927 u8 fdb_to_vport_reg_c_id[0x8]; 928 u8 reserved_at_8[0x5]; 929 u8 fdb_uplink_hairpin[0x1]; 930 u8 fdb_multi_path_any_table_limit_regc[0x1]; 931 u8 reserved_at_f[0x1]; 932 u8 fdb_dynamic_tunnel[0x1]; 933 u8 reserved_at_11[0x1]; 934 u8 fdb_multi_path_any_table[0x1]; 935 u8 reserved_at_13[0x2]; 936 u8 fdb_modify_header_fwd_to_table[0x1]; 937 u8 fdb_ipv4_ttl_modify[0x1]; 938 u8 flow_source[0x1]; 939 u8 reserved_at_18[0x2]; 940 u8 multi_fdb_encap[0x1]; 941 u8 egress_acl_forward_to_vport[0x1]; 942 u8 fdb_multi_path_to_table[0x1]; 943 u8 reserved_at_1d[0x3]; 944 945 u8 reserved_at_20[0x1e0]; 946 947 struct mlx5_ifc_flow_table_prop_layout_bits flow_table_properties_nic_esw_fdb; 948 949 struct mlx5_ifc_flow_table_prop_layout_bits flow_table_properties_esw_acl_ingress; 950 951 struct mlx5_ifc_flow_table_prop_layout_bits flow_table_properties_esw_acl_egress; 952 953 u8 reserved_at_800[0xC00]; 954 955 struct mlx5_ifc_flow_table_fields_supported_2_bits ft_field_support_2_esw_fdb; 956 957 struct mlx5_ifc_flow_table_fields_supported_2_bits ft_field_bitmask_support_2_esw_fdb; 958 959 u8 reserved_at_1500[0x300]; 960 961 u8 sw_steering_fdb_action_drop_icm_address_rx[0x40]; 962 963 u8 sw_steering_fdb_action_drop_icm_address_tx[0x40]; 964 965 u8 sw_steering_uplink_icm_address_rx[0x40]; 966 967 u8 sw_steering_uplink_icm_address_tx[0x40]; 968 969 u8 reserved_at_1900[0x6700]; 970 }; 971 972 struct mlx5_ifc_wqe_based_flow_table_cap_bits { 973 u8 reserved_at_0[0x3]; 974 u8 log_max_num_ste[0x5]; 975 u8 reserved_at_8[0x3]; 976 u8 log_max_num_stc[0x5]; 977 u8 reserved_at_10[0x3]; 978 u8 log_max_num_rtc[0x5]; 979 u8 reserved_at_18[0x3]; 980 u8 log_max_num_header_modify_pattern[0x5]; 981 982 u8 rtc_hash_split_table[0x1]; 983 u8 rtc_linear_lookup_table[0x1]; 984 u8 reserved_at_22[0x1]; 985 u8 stc_alloc_log_granularity[0x5]; 986 u8 reserved_at_28[0x3]; 987 u8 stc_alloc_log_max[0x5]; 988 u8 reserved_at_30[0x3]; 989 u8 ste_alloc_log_granularity[0x5]; 990 u8 reserved_at_38[0x3]; 991 u8 ste_alloc_log_max[0x5]; 992 993 u8 reserved_at_40[0xb]; 994 u8 rtc_reparse_mode[0x5]; 995 u8 reserved_at_50[0x3]; 996 u8 rtc_index_mode[0x5]; 997 u8 reserved_at_58[0x3]; 998 u8 rtc_log_depth_max[0x5]; 999 1000 u8 reserved_at_60[0x10]; 1001 u8 ste_format[0x10]; 1002 1003 u8 stc_action_type[0x80]; 1004 1005 u8 header_insert_type[0x10]; 1006 u8 header_remove_type[0x10]; 1007 1008 u8 trivial_match_definer[0x20]; 1009 1010 u8 reserved_at_140[0x1b]; 1011 u8 rtc_max_num_hash_definer_gen_wqe[0x5]; 1012 1013 u8 reserved_at_160[0x18]; 1014 u8 access_index_mode[0x8]; 1015 1016 u8 reserved_at_180[0x10]; 1017 u8 ste_format_gen_wqe[0x10]; 1018 1019 u8 linear_match_definer_reg_c3[0x20]; 1020 1021 u8 fdb_jump_to_tir_stc[0x1]; 1022 u8 reserved_at_1c1[0x1f]; 1023 }; 1024 1025 struct mlx5_ifc_esw_cap_bits { 1026 u8 reserved_at_0[0x1d]; 1027 u8 merged_eswitch[0x1]; 1028 u8 reserved_at_1e[0x2]; 1029 1030 u8 reserved_at_20[0x40]; 1031 1032 u8 esw_manager_vport_number_valid[0x1]; 1033 u8 reserved_at_61[0xf]; 1034 u8 esw_manager_vport_number[0x10]; 1035 1036 u8 reserved_at_80[0x780]; 1037 }; 1038 1039 enum { 1040 MLX5_COUNTER_SOURCE_ESWITCH = 0x0, 1041 MLX5_COUNTER_FLOW_ESWITCH = 0x1, 1042 }; 1043 1044 struct mlx5_ifc_e_switch_cap_bits { 1045 u8 vport_svlan_strip[0x1]; 1046 u8 vport_cvlan_strip[0x1]; 1047 u8 vport_svlan_insert[0x1]; 1048 u8 vport_cvlan_insert_if_not_exist[0x1]; 1049 u8 vport_cvlan_insert_overwrite[0x1]; 1050 u8 reserved_at_5[0x1]; 1051 u8 vport_cvlan_insert_always[0x1]; 1052 u8 esw_shared_ingress_acl[0x1]; 1053 u8 esw_uplink_ingress_acl[0x1]; 1054 u8 root_ft_on_other_esw[0x1]; 1055 u8 reserved_at_a[0xf]; 1056 u8 esw_functions_changed[0x1]; 1057 u8 reserved_at_1a[0x1]; 1058 u8 ecpf_vport_exists[0x1]; 1059 u8 counter_eswitch_affinity[0x1]; 1060 u8 merged_eswitch[0x1]; 1061 u8 nic_vport_node_guid_modify[0x1]; 1062 u8 nic_vport_port_guid_modify[0x1]; 1063 1064 u8 vxlan_encap_decap[0x1]; 1065 u8 nvgre_encap_decap[0x1]; 1066 u8 reserved_at_22[0x1]; 1067 u8 log_max_fdb_encap_uplink[0x5]; 1068 u8 reserved_at_21[0x3]; 1069 u8 log_max_packet_reformat_context[0x5]; 1070 u8 reserved_2b[0x6]; 1071 u8 max_encap_header_size[0xa]; 1072 1073 u8 reserved_at_40[0xb]; 1074 u8 log_max_esw_sf[0x5]; 1075 u8 esw_sf_base_id[0x10]; 1076 1077 u8 reserved_at_60[0x7a0]; 1078 1079 }; 1080 1081 struct mlx5_ifc_qos_cap_bits { 1082 u8 packet_pacing[0x1]; 1083 u8 esw_scheduling[0x1]; 1084 u8 esw_bw_share[0x1]; 1085 u8 esw_rate_limit[0x1]; 1086 u8 reserved_at_4[0x1]; 1087 u8 packet_pacing_burst_bound[0x1]; 1088 u8 packet_pacing_typical_size[0x1]; 1089 u8 reserved_at_7[0x1]; 1090 u8 nic_sq_scheduling[0x1]; 1091 u8 nic_bw_share[0x1]; 1092 u8 nic_rate_limit[0x1]; 1093 u8 packet_pacing_uid[0x1]; 1094 u8 log_esw_max_sched_depth[0x4]; 1095 u8 reserved_at_10[0x10]; 1096 1097 u8 reserved_at_20[0xb]; 1098 u8 log_max_qos_nic_queue_group[0x5]; 1099 u8 reserved_at_30[0x10]; 1100 1101 u8 packet_pacing_max_rate[0x20]; 1102 1103 u8 packet_pacing_min_rate[0x20]; 1104 1105 u8 reserved_at_80[0x10]; 1106 u8 packet_pacing_rate_table_size[0x10]; 1107 1108 u8 esw_element_type[0x10]; 1109 u8 esw_tsar_type[0x10]; 1110 1111 u8 reserved_at_c0[0x10]; 1112 u8 max_qos_para_vport[0x10]; 1113 1114 u8 max_tsar_bw_share[0x20]; 1115 1116 u8 nic_element_type[0x10]; 1117 u8 nic_tsar_type[0x10]; 1118 1119 u8 reserved_at_120[0x3]; 1120 u8 log_meter_aso_granularity[0x5]; 1121 u8 reserved_at_128[0x3]; 1122 u8 log_meter_aso_max_alloc[0x5]; 1123 u8 reserved_at_130[0x3]; 1124 u8 log_max_num_meter_aso[0x5]; 1125 u8 reserved_at_138[0x8]; 1126 1127 u8 reserved_at_140[0x6c0]; 1128 }; 1129 1130 struct mlx5_ifc_debug_cap_bits { 1131 u8 core_dump_general[0x1]; 1132 u8 core_dump_qp[0x1]; 1133 u8 reserved_at_2[0x7]; 1134 u8 resource_dump[0x1]; 1135 u8 reserved_at_a[0x16]; 1136 1137 u8 reserved_at_20[0x2]; 1138 u8 stall_detect[0x1]; 1139 u8 reserved_at_23[0x1d]; 1140 1141 u8 reserved_at_40[0x7c0]; 1142 }; 1143 1144 struct mlx5_ifc_per_protocol_networking_offload_caps_bits { 1145 u8 csum_cap[0x1]; 1146 u8 vlan_cap[0x1]; 1147 u8 lro_cap[0x1]; 1148 u8 lro_psh_flag[0x1]; 1149 u8 lro_time_stamp[0x1]; 1150 u8 reserved_at_5[0x2]; 1151 u8 wqe_vlan_insert[0x1]; 1152 u8 self_lb_en_modifiable[0x1]; 1153 u8 reserved_at_9[0x2]; 1154 u8 max_lso_cap[0x5]; 1155 u8 multi_pkt_send_wqe[0x2]; 1156 u8 wqe_inline_mode[0x2]; 1157 u8 rss_ind_tbl_cap[0x4]; 1158 u8 reg_umr_sq[0x1]; 1159 u8 scatter_fcs[0x1]; 1160 u8 enhanced_multi_pkt_send_wqe[0x1]; 1161 u8 tunnel_lso_const_out_ip_id[0x1]; 1162 u8 tunnel_lro_gre[0x1]; 1163 u8 tunnel_lro_vxlan[0x1]; 1164 u8 tunnel_stateless_gre[0x1]; 1165 u8 tunnel_stateless_vxlan[0x1]; 1166 1167 u8 swp[0x1]; 1168 u8 swp_csum[0x1]; 1169 u8 swp_lso[0x1]; 1170 u8 cqe_checksum_full[0x1]; 1171 u8 tunnel_stateless_geneve_tx[0x1]; 1172 u8 tunnel_stateless_mpls_over_udp[0x1]; 1173 u8 tunnel_stateless_mpls_over_gre[0x1]; 1174 u8 tunnel_stateless_vxlan_gpe[0x1]; 1175 u8 tunnel_stateless_ipv4_over_vxlan[0x1]; 1176 u8 tunnel_stateless_ip_over_ip[0x1]; 1177 u8 insert_trailer[0x1]; 1178 u8 reserved_at_2b[0x1]; 1179 u8 tunnel_stateless_ip_over_ip_rx[0x1]; 1180 u8 tunnel_stateless_ip_over_ip_tx[0x1]; 1181 u8 reserved_at_2e[0x2]; 1182 u8 max_vxlan_udp_ports[0x8]; 1183 u8 swp_csum_l4_partial[0x1]; 1184 u8 reserved_at_39[0x5]; 1185 u8 max_geneve_opt_len[0x1]; 1186 u8 tunnel_stateless_geneve_rx[0x1]; 1187 1188 u8 reserved_at_40[0x10]; 1189 u8 lro_min_mss_size[0x10]; 1190 1191 u8 reserved_at_60[0x120]; 1192 1193 u8 lro_timer_supported_periods[4][0x20]; 1194 1195 u8 reserved_at_200[0x600]; 1196 }; 1197 1198 enum { 1199 MLX5_TIMESTAMP_FORMAT_CAP_FREE_RUNNING = 0x0, 1200 MLX5_TIMESTAMP_FORMAT_CAP_REAL_TIME = 0x1, 1201 MLX5_TIMESTAMP_FORMAT_CAP_FREE_RUNNING_AND_REAL_TIME = 0x2, 1202 }; 1203 1204 struct mlx5_ifc_roce_cap_bits { 1205 u8 roce_apm[0x1]; 1206 u8 reserved_at_1[0x3]; 1207 u8 sw_r_roce_src_udp_port[0x1]; 1208 u8 fl_rc_qp_when_roce_disabled[0x1]; 1209 u8 fl_rc_qp_when_roce_enabled[0x1]; 1210 u8 roce_cc_general[0x1]; 1211 u8 qp_ooo_transmit_default[0x1]; 1212 u8 reserved_at_9[0x15]; 1213 u8 qp_ts_format[0x2]; 1214 1215 u8 reserved_at_20[0x60]; 1216 1217 u8 reserved_at_80[0xc]; 1218 u8 l3_type[0x4]; 1219 u8 reserved_at_90[0x8]; 1220 u8 roce_version[0x8]; 1221 1222 u8 reserved_at_a0[0x10]; 1223 u8 r_roce_dest_udp_port[0x10]; 1224 1225 u8 r_roce_max_src_udp_port[0x10]; 1226 u8 r_roce_min_src_udp_port[0x10]; 1227 1228 u8 reserved_at_e0[0x10]; 1229 u8 roce_address_table_size[0x10]; 1230 1231 u8 reserved_at_100[0x700]; 1232 }; 1233 1234 struct mlx5_ifc_sync_steering_in_bits { 1235 u8 opcode[0x10]; 1236 u8 uid[0x10]; 1237 1238 u8 reserved_at_20[0x10]; 1239 u8 op_mod[0x10]; 1240 1241 u8 reserved_at_40[0xc0]; 1242 }; 1243 1244 struct mlx5_ifc_sync_steering_out_bits { 1245 u8 status[0x8]; 1246 u8 reserved_at_8[0x18]; 1247 1248 u8 syndrome[0x20]; 1249 1250 u8 reserved_at_40[0x40]; 1251 }; 1252 1253 struct mlx5_ifc_sync_crypto_in_bits { 1254 u8 opcode[0x10]; 1255 u8 uid[0x10]; 1256 1257 u8 reserved_at_20[0x10]; 1258 u8 op_mod[0x10]; 1259 1260 u8 reserved_at_40[0x20]; 1261 1262 u8 reserved_at_60[0x10]; 1263 u8 crypto_type[0x10]; 1264 1265 u8 reserved_at_80[0x80]; 1266 }; 1267 1268 struct mlx5_ifc_sync_crypto_out_bits { 1269 u8 status[0x8]; 1270 u8 reserved_at_8[0x18]; 1271 1272 u8 syndrome[0x20]; 1273 1274 u8 reserved_at_40[0x40]; 1275 }; 1276 1277 struct mlx5_ifc_device_mem_cap_bits { 1278 u8 memic[0x1]; 1279 u8 reserved_at_1[0x1f]; 1280 1281 u8 reserved_at_20[0xb]; 1282 u8 log_min_memic_alloc_size[0x5]; 1283 u8 reserved_at_30[0x8]; 1284 u8 log_max_memic_addr_alignment[0x8]; 1285 1286 u8 memic_bar_start_addr[0x40]; 1287 1288 u8 memic_bar_size[0x20]; 1289 1290 u8 max_memic_size[0x20]; 1291 1292 u8 steering_sw_icm_start_address[0x40]; 1293 1294 u8 reserved_at_100[0x8]; 1295 u8 log_header_modify_sw_icm_size[0x8]; 1296 u8 reserved_at_110[0x2]; 1297 u8 log_sw_icm_alloc_granularity[0x6]; 1298 u8 log_steering_sw_icm_size[0x8]; 1299 1300 u8 log_indirect_encap_sw_icm_size[0x8]; 1301 u8 reserved_at_128[0x10]; 1302 u8 log_header_modify_pattern_sw_icm_size[0x8]; 1303 1304 u8 header_modify_sw_icm_start_address[0x40]; 1305 1306 u8 reserved_at_180[0x40]; 1307 1308 u8 header_modify_pattern_sw_icm_start_address[0x40]; 1309 1310 u8 memic_operations[0x20]; 1311 1312 u8 reserved_at_220[0x20]; 1313 1314 u8 indirect_encap_sw_icm_start_address[0x40]; 1315 1316 u8 reserved_at_280[0x580]; 1317 }; 1318 1319 struct mlx5_ifc_device_event_cap_bits { 1320 u8 user_affiliated_events[4][0x40]; 1321 1322 u8 user_unaffiliated_events[4][0x40]; 1323 }; 1324 1325 struct mlx5_ifc_virtio_emulation_cap_bits { 1326 u8 desc_tunnel_offload_type[0x1]; 1327 u8 eth_frame_offload_type[0x1]; 1328 u8 virtio_version_1_0[0x1]; 1329 u8 device_features_bits_mask[0xd]; 1330 u8 event_mode[0x8]; 1331 u8 virtio_queue_type[0x8]; 1332 1333 u8 max_tunnel_desc[0x10]; 1334 u8 reserved_at_30[0x3]; 1335 u8 log_doorbell_stride[0x5]; 1336 u8 reserved_at_38[0x3]; 1337 u8 log_doorbell_bar_size[0x5]; 1338 1339 u8 doorbell_bar_offset[0x40]; 1340 1341 u8 max_emulated_devices[0x8]; 1342 u8 max_num_virtio_queues[0x18]; 1343 1344 u8 reserved_at_a0[0x20]; 1345 1346 u8 reserved_at_c0[0x13]; 1347 u8 desc_group_mkey_supported[0x1]; 1348 u8 freeze_to_rdy_supported[0x1]; 1349 u8 reserved_at_d5[0xb]; 1350 1351 u8 reserved_at_e0[0x20]; 1352 1353 u8 umem_1_buffer_param_a[0x20]; 1354 1355 u8 umem_1_buffer_param_b[0x20]; 1356 1357 u8 umem_2_buffer_param_a[0x20]; 1358 1359 u8 umem_2_buffer_param_b[0x20]; 1360 1361 u8 umem_3_buffer_param_a[0x20]; 1362 1363 u8 umem_3_buffer_param_b[0x20]; 1364 1365 u8 reserved_at_1c0[0x640]; 1366 }; 1367 1368 enum { 1369 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_QP_1_BYTE = 0x0, 1370 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_QP_2_BYTES = 0x2, 1371 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_QP_4_BYTES = 0x4, 1372 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_QP_8_BYTES = 0x8, 1373 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_QP_16_BYTES = 0x10, 1374 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_QP_32_BYTES = 0x20, 1375 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_QP_64_BYTES = 0x40, 1376 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_QP_128_BYTES = 0x80, 1377 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_QP_256_BYTES = 0x100, 1378 }; 1379 1380 enum { 1381 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_DC_1_BYTE = 0x1, 1382 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_DC_2_BYTES = 0x2, 1383 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_DC_4_BYTES = 0x4, 1384 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_DC_8_BYTES = 0x8, 1385 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_DC_16_BYTES = 0x10, 1386 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_DC_32_BYTES = 0x20, 1387 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_DC_64_BYTES = 0x40, 1388 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_DC_128_BYTES = 0x80, 1389 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_DC_256_BYTES = 0x100, 1390 }; 1391 1392 struct mlx5_ifc_atomic_caps_bits { 1393 u8 reserved_at_0[0x40]; 1394 1395 u8 atomic_req_8B_endianness_mode[0x2]; 1396 u8 reserved_at_42[0x4]; 1397 u8 supported_atomic_req_8B_endianness_mode_1[0x1]; 1398 1399 u8 reserved_at_47[0x19]; 1400 1401 u8 reserved_at_60[0x20]; 1402 1403 u8 reserved_at_80[0x10]; 1404 u8 atomic_operations[0x10]; 1405 1406 u8 reserved_at_a0[0x10]; 1407 u8 atomic_size_qp[0x10]; 1408 1409 u8 reserved_at_c0[0x10]; 1410 u8 atomic_size_dc[0x10]; 1411 1412 u8 reserved_at_e0[0x720]; 1413 }; 1414 1415 struct mlx5_ifc_odp_cap_bits { 1416 u8 reserved_at_0[0x40]; 1417 1418 u8 sig[0x1]; 1419 u8 reserved_at_41[0x1f]; 1420 1421 u8 reserved_at_60[0x20]; 1422 1423 struct mlx5_ifc_odp_per_transport_service_cap_bits rc_odp_caps; 1424 1425 struct mlx5_ifc_odp_per_transport_service_cap_bits uc_odp_caps; 1426 1427 struct mlx5_ifc_odp_per_transport_service_cap_bits ud_odp_caps; 1428 1429 struct mlx5_ifc_odp_per_transport_service_cap_bits xrc_odp_caps; 1430 1431 struct mlx5_ifc_odp_per_transport_service_cap_bits dc_odp_caps; 1432 1433 u8 reserved_at_120[0x6E0]; 1434 }; 1435 1436 struct mlx5_ifc_tls_cap_bits { 1437 u8 tls_1_2_aes_gcm_128[0x1]; 1438 u8 tls_1_3_aes_gcm_128[0x1]; 1439 u8 tls_1_2_aes_gcm_256[0x1]; 1440 u8 tls_1_3_aes_gcm_256[0x1]; 1441 u8 reserved_at_4[0x1c]; 1442 1443 u8 reserved_at_20[0x7e0]; 1444 }; 1445 1446 struct mlx5_ifc_ipsec_cap_bits { 1447 u8 ipsec_full_offload[0x1]; 1448 u8 ipsec_crypto_offload[0x1]; 1449 u8 ipsec_esn[0x1]; 1450 u8 ipsec_crypto_esp_aes_gcm_256_encrypt[0x1]; 1451 u8 ipsec_crypto_esp_aes_gcm_128_encrypt[0x1]; 1452 u8 ipsec_crypto_esp_aes_gcm_256_decrypt[0x1]; 1453 u8 ipsec_crypto_esp_aes_gcm_128_decrypt[0x1]; 1454 u8 reserved_at_7[0x4]; 1455 u8 log_max_ipsec_offload[0x5]; 1456 u8 reserved_at_10[0x10]; 1457 1458 u8 min_log_ipsec_full_replay_window[0x8]; 1459 u8 max_log_ipsec_full_replay_window[0x8]; 1460 u8 reserved_at_30[0x7d0]; 1461 }; 1462 1463 struct mlx5_ifc_macsec_cap_bits { 1464 u8 macsec_epn[0x1]; 1465 u8 reserved_at_1[0x2]; 1466 u8 macsec_crypto_esp_aes_gcm_256_encrypt[0x1]; 1467 u8 macsec_crypto_esp_aes_gcm_128_encrypt[0x1]; 1468 u8 macsec_crypto_esp_aes_gcm_256_decrypt[0x1]; 1469 u8 macsec_crypto_esp_aes_gcm_128_decrypt[0x1]; 1470 u8 reserved_at_7[0x4]; 1471 u8 log_max_macsec_offload[0x5]; 1472 u8 reserved_at_10[0x10]; 1473 1474 u8 min_log_macsec_full_replay_window[0x8]; 1475 u8 max_log_macsec_full_replay_window[0x8]; 1476 u8 reserved_at_30[0x10]; 1477 1478 u8 reserved_at_40[0x7c0]; 1479 }; 1480 1481 enum { 1482 MLX5_WQ_TYPE_LINKED_LIST = 0x0, 1483 MLX5_WQ_TYPE_CYCLIC = 0x1, 1484 MLX5_WQ_TYPE_LINKED_LIST_STRIDING_RQ = 0x2, 1485 MLX5_WQ_TYPE_CYCLIC_STRIDING_RQ = 0x3, 1486 }; 1487 1488 enum { 1489 MLX5_WQ_END_PAD_MODE_NONE = 0x0, 1490 MLX5_WQ_END_PAD_MODE_ALIGN = 0x1, 1491 }; 1492 1493 enum { 1494 MLX5_CMD_HCA_CAP_GID_TABLE_SIZE_8_GID_ENTRIES = 0x0, 1495 MLX5_CMD_HCA_CAP_GID_TABLE_SIZE_16_GID_ENTRIES = 0x1, 1496 MLX5_CMD_HCA_CAP_GID_TABLE_SIZE_32_GID_ENTRIES = 0x2, 1497 MLX5_CMD_HCA_CAP_GID_TABLE_SIZE_64_GID_ENTRIES = 0x3, 1498 MLX5_CMD_HCA_CAP_GID_TABLE_SIZE_128_GID_ENTRIES = 0x4, 1499 }; 1500 1501 enum { 1502 MLX5_CMD_HCA_CAP_PKEY_TABLE_SIZE_128_ENTRIES = 0x0, 1503 MLX5_CMD_HCA_CAP_PKEY_TABLE_SIZE_256_ENTRIES = 0x1, 1504 MLX5_CMD_HCA_CAP_PKEY_TABLE_SIZE_512_ENTRIES = 0x2, 1505 MLX5_CMD_HCA_CAP_PKEY_TABLE_SIZE_1K_ENTRIES = 0x3, 1506 MLX5_CMD_HCA_CAP_PKEY_TABLE_SIZE_2K_ENTRIES = 0x4, 1507 MLX5_CMD_HCA_CAP_PKEY_TABLE_SIZE_4K_ENTRIES = 0x5, 1508 }; 1509 1510 enum { 1511 MLX5_CMD_HCA_CAP_PORT_TYPE_IB = 0x0, 1512 MLX5_CMD_HCA_CAP_PORT_TYPE_ETHERNET = 0x1, 1513 }; 1514 1515 enum { 1516 MLX5_CMD_HCA_CAP_CMDIF_CHECKSUM_DISABLED = 0x0, 1517 MLX5_CMD_HCA_CAP_CMDIF_CHECKSUM_INITIAL_STATE = 0x1, 1518 MLX5_CMD_HCA_CAP_CMDIF_CHECKSUM_ENABLED = 0x3, 1519 }; 1520 1521 enum { 1522 MLX5_CAP_PORT_TYPE_IB = 0x0, 1523 MLX5_CAP_PORT_TYPE_ETH = 0x1, 1524 }; 1525 1526 enum { 1527 MLX5_CAP_UMR_FENCE_STRONG = 0x0, 1528 MLX5_CAP_UMR_FENCE_SMALL = 0x1, 1529 MLX5_CAP_UMR_FENCE_NONE = 0x2, 1530 }; 1531 1532 enum { 1533 MLX5_FLEX_IPV4_OVER_VXLAN_ENABLED = 1 << 0, 1534 MLX5_FLEX_IPV6_OVER_VXLAN_ENABLED = 1 << 1, 1535 MLX5_FLEX_IPV6_OVER_IP_ENABLED = 1 << 2, 1536 MLX5_FLEX_PARSER_GENEVE_ENABLED = 1 << 3, 1537 MLX5_FLEX_PARSER_MPLS_OVER_GRE_ENABLED = 1 << 4, 1538 MLX5_FLEX_PARSER_MPLS_OVER_UDP_ENABLED = 1 << 5, 1539 MLX5_FLEX_P_BIT_VXLAN_GPE_ENABLED = 1 << 6, 1540 MLX5_FLEX_PARSER_VXLAN_GPE_ENABLED = 1 << 7, 1541 MLX5_FLEX_PARSER_ICMP_V4_ENABLED = 1 << 8, 1542 MLX5_FLEX_PARSER_ICMP_V6_ENABLED = 1 << 9, 1543 MLX5_FLEX_PARSER_GENEVE_TLV_OPTION_0_ENABLED = 1 << 10, 1544 MLX5_FLEX_PARSER_GTPU_ENABLED = 1 << 11, 1545 MLX5_FLEX_PARSER_GTPU_DW_2_ENABLED = 1 << 16, 1546 MLX5_FLEX_PARSER_GTPU_FIRST_EXT_DW_0_ENABLED = 1 << 17, 1547 MLX5_FLEX_PARSER_GTPU_DW_0_ENABLED = 1 << 18, 1548 MLX5_FLEX_PARSER_GTPU_TEID_ENABLED = 1 << 19, 1549 }; 1550 1551 enum { 1552 MLX5_UCTX_CAP_RAW_TX = 1UL << 0, 1553 MLX5_UCTX_CAP_INTERNAL_DEV_RES = 1UL << 1, 1554 }; 1555 1556 #define MLX5_FC_BULK_SIZE_FACTOR 128 1557 1558 enum mlx5_fc_bulk_alloc_bitmask { 1559 MLX5_FC_BULK_128 = (1 << 0), 1560 MLX5_FC_BULK_256 = (1 << 1), 1561 MLX5_FC_BULK_512 = (1 << 2), 1562 MLX5_FC_BULK_1024 = (1 << 3), 1563 MLX5_FC_BULK_2048 = (1 << 4), 1564 MLX5_FC_BULK_4096 = (1 << 5), 1565 MLX5_FC_BULK_8192 = (1 << 6), 1566 MLX5_FC_BULK_16384 = (1 << 7), 1567 }; 1568 1569 #define MLX5_FC_BULK_NUM_FCS(fc_enum) (MLX5_FC_BULK_SIZE_FACTOR * (fc_enum)) 1570 1571 #define MLX5_FT_MAX_MULTIPATH_LEVEL 63 1572 1573 enum { 1574 MLX5_STEERING_FORMAT_CONNECTX_5 = 0, 1575 MLX5_STEERING_FORMAT_CONNECTX_6DX = 1, 1576 MLX5_STEERING_FORMAT_CONNECTX_7 = 2, 1577 }; 1578 1579 struct mlx5_ifc_cmd_hca_cap_bits { 1580 u8 reserved_at_0[0x6]; 1581 u8 page_request_disable[0x1]; 1582 u8 reserved_at_7[0x9]; 1583 u8 shared_object_to_user_object_allowed[0x1]; 1584 u8 reserved_at_13[0xe]; 1585 u8 vhca_resource_manager[0x1]; 1586 1587 u8 hca_cap_2[0x1]; 1588 u8 create_lag_when_not_master_up[0x1]; 1589 u8 dtor[0x1]; 1590 u8 event_on_vhca_state_teardown_request[0x1]; 1591 u8 event_on_vhca_state_in_use[0x1]; 1592 u8 event_on_vhca_state_active[0x1]; 1593 u8 event_on_vhca_state_allocated[0x1]; 1594 u8 event_on_vhca_state_invalid[0x1]; 1595 u8 reserved_at_28[0x8]; 1596 u8 vhca_id[0x10]; 1597 1598 u8 reserved_at_40[0x40]; 1599 1600 u8 log_max_srq_sz[0x8]; 1601 u8 log_max_qp_sz[0x8]; 1602 u8 event_cap[0x1]; 1603 u8 reserved_at_91[0x2]; 1604 u8 isolate_vl_tc_new[0x1]; 1605 u8 reserved_at_94[0x4]; 1606 u8 prio_tag_required[0x1]; 1607 u8 reserved_at_99[0x2]; 1608 u8 log_max_qp[0x5]; 1609 1610 u8 reserved_at_a0[0x3]; 1611 u8 ece_support[0x1]; 1612 u8 reserved_at_a4[0x5]; 1613 u8 reg_c_preserve[0x1]; 1614 u8 reserved_at_aa[0x1]; 1615 u8 log_max_srq[0x5]; 1616 u8 reserved_at_b0[0x1]; 1617 u8 uplink_follow[0x1]; 1618 u8 ts_cqe_to_dest_cqn[0x1]; 1619 u8 reserved_at_b3[0x6]; 1620 u8 go_back_n[0x1]; 1621 u8 reserved_at_ba[0x6]; 1622 1623 u8 max_sgl_for_optimized_performance[0x8]; 1624 u8 log_max_cq_sz[0x8]; 1625 u8 relaxed_ordering_write_umr[0x1]; 1626 u8 relaxed_ordering_read_umr[0x1]; 1627 u8 reserved_at_d2[0x7]; 1628 u8 virtio_net_device_emualtion_manager[0x1]; 1629 u8 virtio_blk_device_emualtion_manager[0x1]; 1630 u8 log_max_cq[0x5]; 1631 1632 u8 log_max_eq_sz[0x8]; 1633 u8 relaxed_ordering_write[0x1]; 1634 u8 relaxed_ordering_read_pci_enabled[0x1]; 1635 u8 log_max_mkey[0x6]; 1636 u8 reserved_at_f0[0x6]; 1637 u8 terminate_scatter_list_mkey[0x1]; 1638 u8 repeated_mkey[0x1]; 1639 u8 dump_fill_mkey[0x1]; 1640 u8 reserved_at_f9[0x2]; 1641 u8 fast_teardown[0x1]; 1642 u8 log_max_eq[0x4]; 1643 1644 u8 max_indirection[0x8]; 1645 u8 fixed_buffer_size[0x1]; 1646 u8 log_max_mrw_sz[0x7]; 1647 u8 force_teardown[0x1]; 1648 u8 reserved_at_111[0x1]; 1649 u8 log_max_bsf_list_size[0x6]; 1650 u8 umr_extended_translation_offset[0x1]; 1651 u8 null_mkey[0x1]; 1652 u8 log_max_klm_list_size[0x6]; 1653 1654 u8 reserved_at_120[0x2]; 1655 u8 qpc_extension[0x1]; 1656 u8 reserved_at_123[0x7]; 1657 u8 log_max_ra_req_dc[0x6]; 1658 u8 reserved_at_130[0x2]; 1659 u8 eth_wqe_too_small[0x1]; 1660 u8 reserved_at_133[0x6]; 1661 u8 vnic_env_cq_overrun[0x1]; 1662 u8 log_max_ra_res_dc[0x6]; 1663 1664 u8 reserved_at_140[0x5]; 1665 u8 release_all_pages[0x1]; 1666 u8 must_not_use[0x1]; 1667 u8 reserved_at_147[0x2]; 1668 u8 roce_accl[0x1]; 1669 u8 log_max_ra_req_qp[0x6]; 1670 u8 reserved_at_150[0xa]; 1671 u8 log_max_ra_res_qp[0x6]; 1672 1673 u8 end_pad[0x1]; 1674 u8 cc_query_allowed[0x1]; 1675 u8 cc_modify_allowed[0x1]; 1676 u8 start_pad[0x1]; 1677 u8 cache_line_128byte[0x1]; 1678 u8 reserved_at_165[0x4]; 1679 u8 rts2rts_qp_counters_set_id[0x1]; 1680 u8 reserved_at_16a[0x2]; 1681 u8 vnic_env_int_rq_oob[0x1]; 1682 u8 sbcam_reg[0x1]; 1683 u8 reserved_at_16e[0x1]; 1684 u8 qcam_reg[0x1]; 1685 u8 gid_table_size[0x10]; 1686 1687 u8 out_of_seq_cnt[0x1]; 1688 u8 vport_counters[0x1]; 1689 u8 retransmission_q_counters[0x1]; 1690 u8 debug[0x1]; 1691 u8 modify_rq_counter_set_id[0x1]; 1692 u8 rq_delay_drop[0x1]; 1693 u8 max_qp_cnt[0xa]; 1694 u8 pkey_table_size[0x10]; 1695 1696 u8 vport_group_manager[0x1]; 1697 u8 vhca_group_manager[0x1]; 1698 u8 ib_virt[0x1]; 1699 u8 eth_virt[0x1]; 1700 u8 vnic_env_queue_counters[0x1]; 1701 u8 ets[0x1]; 1702 u8 nic_flow_table[0x1]; 1703 u8 eswitch_manager[0x1]; 1704 u8 device_memory[0x1]; 1705 u8 mcam_reg[0x1]; 1706 u8 pcam_reg[0x1]; 1707 u8 local_ca_ack_delay[0x5]; 1708 u8 port_module_event[0x1]; 1709 u8 enhanced_error_q_counters[0x1]; 1710 u8 ports_check[0x1]; 1711 u8 reserved_at_1b3[0x1]; 1712 u8 disable_link_up[0x1]; 1713 u8 beacon_led[0x1]; 1714 u8 port_type[0x2]; 1715 u8 num_ports[0x8]; 1716 1717 u8 reserved_at_1c0[0x1]; 1718 u8 pps[0x1]; 1719 u8 pps_modify[0x1]; 1720 u8 log_max_msg[0x5]; 1721 u8 reserved_at_1c8[0x4]; 1722 u8 max_tc[0x4]; 1723 u8 temp_warn_event[0x1]; 1724 u8 dcbx[0x1]; 1725 u8 general_notification_event[0x1]; 1726 u8 reserved_at_1d3[0x2]; 1727 u8 fpga[0x1]; 1728 u8 rol_s[0x1]; 1729 u8 rol_g[0x1]; 1730 u8 reserved_at_1d8[0x1]; 1731 u8 wol_s[0x1]; 1732 u8 wol_g[0x1]; 1733 u8 wol_a[0x1]; 1734 u8 wol_b[0x1]; 1735 u8 wol_m[0x1]; 1736 u8 wol_u[0x1]; 1737 u8 wol_p[0x1]; 1738 1739 u8 stat_rate_support[0x10]; 1740 u8 reserved_at_1f0[0x1]; 1741 u8 pci_sync_for_fw_update_event[0x1]; 1742 u8 reserved_at_1f2[0x6]; 1743 u8 init2_lag_tx_port_affinity[0x1]; 1744 u8 reserved_at_1fa[0x2]; 1745 u8 wqe_based_flow_table_update_cap[0x1]; 1746 u8 cqe_version[0x4]; 1747 1748 u8 compact_address_vector[0x1]; 1749 u8 striding_rq[0x1]; 1750 u8 reserved_at_202[0x1]; 1751 u8 ipoib_enhanced_offloads[0x1]; 1752 u8 ipoib_basic_offloads[0x1]; 1753 u8 reserved_at_205[0x1]; 1754 u8 repeated_block_disabled[0x1]; 1755 u8 umr_modify_entity_size_disabled[0x1]; 1756 u8 umr_modify_atomic_disabled[0x1]; 1757 u8 umr_indirect_mkey_disabled[0x1]; 1758 u8 umr_fence[0x2]; 1759 u8 dc_req_scat_data_cqe[0x1]; 1760 u8 reserved_at_20d[0x2]; 1761 u8 drain_sigerr[0x1]; 1762 u8 cmdif_checksum[0x2]; 1763 u8 sigerr_cqe[0x1]; 1764 u8 reserved_at_213[0x1]; 1765 u8 wq_signature[0x1]; 1766 u8 sctr_data_cqe[0x1]; 1767 u8 reserved_at_216[0x1]; 1768 u8 sho[0x1]; 1769 u8 tph[0x1]; 1770 u8 rf[0x1]; 1771 u8 dct[0x1]; 1772 u8 qos[0x1]; 1773 u8 eth_net_offloads[0x1]; 1774 u8 roce[0x1]; 1775 u8 atomic[0x1]; 1776 u8 reserved_at_21f[0x1]; 1777 1778 u8 cq_oi[0x1]; 1779 u8 cq_resize[0x1]; 1780 u8 cq_moderation[0x1]; 1781 u8 cq_period_mode_modify[0x1]; 1782 u8 reserved_at_224[0x2]; 1783 u8 cq_eq_remap[0x1]; 1784 u8 pg[0x1]; 1785 u8 block_lb_mc[0x1]; 1786 u8 reserved_at_229[0x1]; 1787 u8 scqe_break_moderation[0x1]; 1788 u8 cq_period_start_from_cqe[0x1]; 1789 u8 cd[0x1]; 1790 u8 reserved_at_22d[0x1]; 1791 u8 apm[0x1]; 1792 u8 vector_calc[0x1]; 1793 u8 umr_ptr_rlky[0x1]; 1794 u8 imaicl[0x1]; 1795 u8 qp_packet_based[0x1]; 1796 u8 reserved_at_233[0x3]; 1797 u8 qkv[0x1]; 1798 u8 pkv[0x1]; 1799 u8 set_deth_sqpn[0x1]; 1800 u8 reserved_at_239[0x3]; 1801 u8 xrc[0x1]; 1802 u8 ud[0x1]; 1803 u8 uc[0x1]; 1804 u8 rc[0x1]; 1805 1806 u8 uar_4k[0x1]; 1807 u8 reserved_at_241[0x7]; 1808 u8 fl_rc_qp_when_roce_disabled[0x1]; 1809 u8 regexp_params[0x1]; 1810 u8 uar_sz[0x6]; 1811 u8 port_selection_cap[0x1]; 1812 u8 reserved_at_251[0x1]; 1813 u8 umem_uid_0[0x1]; 1814 u8 reserved_at_253[0x5]; 1815 u8 log_pg_sz[0x8]; 1816 1817 u8 bf[0x1]; 1818 u8 driver_version[0x1]; 1819 u8 pad_tx_eth_packet[0x1]; 1820 u8 reserved_at_263[0x3]; 1821 u8 mkey_by_name[0x1]; 1822 u8 reserved_at_267[0x4]; 1823 1824 u8 log_bf_reg_size[0x5]; 1825 1826 u8 reserved_at_270[0x3]; 1827 u8 qp_error_syndrome[0x1]; 1828 u8 reserved_at_274[0x2]; 1829 u8 lag_dct[0x2]; 1830 u8 lag_tx_port_affinity[0x1]; 1831 u8 lag_native_fdb_selection[0x1]; 1832 u8 reserved_at_27a[0x1]; 1833 u8 lag_master[0x1]; 1834 u8 num_lag_ports[0x4]; 1835 1836 u8 reserved_at_280[0x10]; 1837 u8 max_wqe_sz_sq[0x10]; 1838 1839 u8 reserved_at_2a0[0xb]; 1840 u8 shampo[0x1]; 1841 u8 reserved_at_2ac[0x4]; 1842 u8 max_wqe_sz_rq[0x10]; 1843 1844 u8 max_flow_counter_31_16[0x10]; 1845 u8 max_wqe_sz_sq_dc[0x10]; 1846 1847 u8 reserved_at_2e0[0x7]; 1848 u8 max_qp_mcg[0x19]; 1849 1850 u8 reserved_at_300[0x10]; 1851 u8 flow_counter_bulk_alloc[0x8]; 1852 u8 log_max_mcg[0x8]; 1853 1854 u8 reserved_at_320[0x3]; 1855 u8 log_max_transport_domain[0x5]; 1856 u8 reserved_at_328[0x2]; 1857 u8 relaxed_ordering_read[0x1]; 1858 u8 log_max_pd[0x5]; 1859 u8 reserved_at_330[0x5]; 1860 u8 pcie_reset_using_hotreset_method[0x1]; 1861 u8 pci_sync_for_fw_update_with_driver_unload[0x1]; 1862 u8 vnic_env_cnt_steering_fail[0x1]; 1863 u8 vport_counter_local_loopback[0x1]; 1864 u8 q_counter_aggregation[0x1]; 1865 u8 q_counter_other_vport[0x1]; 1866 u8 log_max_xrcd[0x5]; 1867 1868 u8 nic_receive_steering_discard[0x1]; 1869 u8 receive_discard_vport_down[0x1]; 1870 u8 transmit_discard_vport_down[0x1]; 1871 u8 eq_overrun_count[0x1]; 1872 u8 reserved_at_344[0x1]; 1873 u8 invalid_command_count[0x1]; 1874 u8 quota_exceeded_count[0x1]; 1875 u8 reserved_at_347[0x1]; 1876 u8 log_max_flow_counter_bulk[0x8]; 1877 u8 max_flow_counter_15_0[0x10]; 1878 1879 1880 u8 reserved_at_360[0x3]; 1881 u8 log_max_rq[0x5]; 1882 u8 reserved_at_368[0x3]; 1883 u8 log_max_sq[0x5]; 1884 u8 reserved_at_370[0x3]; 1885 u8 log_max_tir[0x5]; 1886 u8 reserved_at_378[0x3]; 1887 u8 log_max_tis[0x5]; 1888 1889 u8 basic_cyclic_rcv_wqe[0x1]; 1890 u8 reserved_at_381[0x2]; 1891 u8 log_max_rmp[0x5]; 1892 u8 reserved_at_388[0x3]; 1893 u8 log_max_rqt[0x5]; 1894 u8 reserved_at_390[0x3]; 1895 u8 log_max_rqt_size[0x5]; 1896 u8 reserved_at_398[0x3]; 1897 u8 log_max_tis_per_sq[0x5]; 1898 1899 u8 ext_stride_num_range[0x1]; 1900 u8 roce_rw_supported[0x1]; 1901 u8 log_max_current_uc_list_wr_supported[0x1]; 1902 u8 log_max_stride_sz_rq[0x5]; 1903 u8 reserved_at_3a8[0x3]; 1904 u8 log_min_stride_sz_rq[0x5]; 1905 u8 reserved_at_3b0[0x3]; 1906 u8 log_max_stride_sz_sq[0x5]; 1907 u8 reserved_at_3b8[0x3]; 1908 u8 log_min_stride_sz_sq[0x5]; 1909 1910 u8 hairpin[0x1]; 1911 u8 reserved_at_3c1[0x2]; 1912 u8 log_max_hairpin_queues[0x5]; 1913 u8 reserved_at_3c8[0x3]; 1914 u8 log_max_hairpin_wq_data_sz[0x5]; 1915 u8 reserved_at_3d0[0x3]; 1916 u8 log_max_hairpin_num_packets[0x5]; 1917 u8 reserved_at_3d8[0x3]; 1918 u8 log_max_wq_sz[0x5]; 1919 1920 u8 nic_vport_change_event[0x1]; 1921 u8 disable_local_lb_uc[0x1]; 1922 u8 disable_local_lb_mc[0x1]; 1923 u8 log_min_hairpin_wq_data_sz[0x5]; 1924 u8 reserved_at_3e8[0x1]; 1925 u8 silent_mode[0x1]; 1926 u8 vhca_state[0x1]; 1927 u8 log_max_vlan_list[0x5]; 1928 u8 reserved_at_3f0[0x3]; 1929 u8 log_max_current_mc_list[0x5]; 1930 u8 reserved_at_3f8[0x3]; 1931 u8 log_max_current_uc_list[0x5]; 1932 1933 u8 general_obj_types[0x40]; 1934 1935 u8 sq_ts_format[0x2]; 1936 u8 rq_ts_format[0x2]; 1937 u8 steering_format_version[0x4]; 1938 u8 create_qp_start_hint[0x18]; 1939 1940 u8 reserved_at_460[0x1]; 1941 u8 ats[0x1]; 1942 u8 cross_vhca_rqt[0x1]; 1943 u8 log_max_uctx[0x5]; 1944 u8 reserved_at_468[0x1]; 1945 u8 crypto[0x1]; 1946 u8 ipsec_offload[0x1]; 1947 u8 log_max_umem[0x5]; 1948 u8 max_num_eqs[0x10]; 1949 1950 u8 reserved_at_480[0x1]; 1951 u8 tls_tx[0x1]; 1952 u8 tls_rx[0x1]; 1953 u8 log_max_l2_table[0x5]; 1954 u8 reserved_at_488[0x8]; 1955 u8 log_uar_page_sz[0x10]; 1956 1957 u8 reserved_at_4a0[0x20]; 1958 u8 device_frequency_mhz[0x20]; 1959 u8 device_frequency_khz[0x20]; 1960 1961 u8 reserved_at_500[0x20]; 1962 u8 num_of_uars_per_page[0x20]; 1963 1964 u8 flex_parser_protocols[0x20]; 1965 1966 u8 max_geneve_tlv_options[0x8]; 1967 u8 reserved_at_568[0x3]; 1968 u8 max_geneve_tlv_option_data_len[0x5]; 1969 u8 reserved_at_570[0x9]; 1970 u8 adv_virtualization[0x1]; 1971 u8 reserved_at_57a[0x6]; 1972 1973 u8 reserved_at_580[0xb]; 1974 u8 log_max_dci_stream_channels[0x5]; 1975 u8 reserved_at_590[0x3]; 1976 u8 log_max_dci_errored_streams[0x5]; 1977 u8 reserved_at_598[0x8]; 1978 1979 u8 reserved_at_5a0[0x10]; 1980 u8 enhanced_cqe_compression[0x1]; 1981 u8 reserved_at_5b1[0x2]; 1982 u8 log_max_dek[0x5]; 1983 u8 reserved_at_5b8[0x4]; 1984 u8 mini_cqe_resp_stride_index[0x1]; 1985 u8 cqe_128_always[0x1]; 1986 u8 cqe_compression_128[0x1]; 1987 u8 cqe_compression[0x1]; 1988 1989 u8 cqe_compression_timeout[0x10]; 1990 u8 cqe_compression_max_num[0x10]; 1991 1992 u8 reserved_at_5e0[0x8]; 1993 u8 flex_parser_id_gtpu_dw_0[0x4]; 1994 u8 reserved_at_5ec[0x4]; 1995 u8 tag_matching[0x1]; 1996 u8 rndv_offload_rc[0x1]; 1997 u8 rndv_offload_dc[0x1]; 1998 u8 log_tag_matching_list_sz[0x5]; 1999 u8 reserved_at_5f8[0x3]; 2000 u8 log_max_xrq[0x5]; 2001 2002 u8 affiliate_nic_vport_criteria[0x8]; 2003 u8 native_port_num[0x8]; 2004 u8 num_vhca_ports[0x8]; 2005 u8 flex_parser_id_gtpu_teid[0x4]; 2006 u8 reserved_at_61c[0x2]; 2007 u8 sw_owner_id[0x1]; 2008 u8 reserved_at_61f[0x1]; 2009 2010 u8 max_num_of_monitor_counters[0x10]; 2011 u8 num_ppcnt_monitor_counters[0x10]; 2012 2013 u8 max_num_sf[0x10]; 2014 u8 num_q_monitor_counters[0x10]; 2015 2016 u8 reserved_at_660[0x20]; 2017 2018 u8 sf[0x1]; 2019 u8 sf_set_partition[0x1]; 2020 u8 reserved_at_682[0x1]; 2021 u8 log_max_sf[0x5]; 2022 u8 apu[0x1]; 2023 u8 reserved_at_689[0x4]; 2024 u8 migration[0x1]; 2025 u8 reserved_at_68e[0x2]; 2026 u8 log_min_sf_size[0x8]; 2027 u8 max_num_sf_partitions[0x8]; 2028 2029 u8 uctx_cap[0x20]; 2030 2031 u8 reserved_at_6c0[0x4]; 2032 u8 flex_parser_id_geneve_tlv_option_0[0x4]; 2033 u8 flex_parser_id_icmp_dw1[0x4]; 2034 u8 flex_parser_id_icmp_dw0[0x4]; 2035 u8 flex_parser_id_icmpv6_dw1[0x4]; 2036 u8 flex_parser_id_icmpv6_dw0[0x4]; 2037 u8 flex_parser_id_outer_first_mpls_over_gre[0x4]; 2038 u8 flex_parser_id_outer_first_mpls_over_udp_label[0x4]; 2039 2040 u8 max_num_match_definer[0x10]; 2041 u8 sf_base_id[0x10]; 2042 2043 u8 flex_parser_id_gtpu_dw_2[0x4]; 2044 u8 flex_parser_id_gtpu_first_ext_dw_0[0x4]; 2045 u8 num_total_dynamic_vf_msix[0x18]; 2046 u8 reserved_at_720[0x14]; 2047 u8 dynamic_msix_table_size[0xc]; 2048 u8 reserved_at_740[0xc]; 2049 u8 min_dynamic_vf_msix_table_size[0x4]; 2050 u8 reserved_at_750[0x4]; 2051 u8 max_dynamic_vf_msix_table_size[0xc]; 2052 2053 u8 reserved_at_760[0x3]; 2054 u8 log_max_num_header_modify_argument[0x5]; 2055 u8 log_header_modify_argument_granularity_offset[0x4]; 2056 u8 log_header_modify_argument_granularity[0x4]; 2057 u8 reserved_at_770[0x3]; 2058 u8 log_header_modify_argument_max_alloc[0x5]; 2059 u8 reserved_at_778[0x8]; 2060 2061 u8 vhca_tunnel_commands[0x40]; 2062 u8 match_definer_format_supported[0x40]; 2063 }; 2064 2065 enum { 2066 MLX5_CROSS_VHCA_OBJ_TO_OBJ_SUPPORTED_LOCAL_FLOW_TABLE_TO_REMOTE_FLOW_TABLE_MISS = 0x80000, 2067 MLX5_CROSS_VHCA_OBJ_TO_OBJ_SUPPORTED_LOCAL_FLOW_TABLE_ROOT_TO_REMOTE_FLOW_TABLE = (1ULL << 20), 2068 }; 2069 2070 enum { 2071 MLX5_ALLOWED_OBJ_FOR_OTHER_VHCA_ACCESS_FLOW_TABLE = 0x200, 2072 }; 2073 2074 struct mlx5_ifc_cmd_hca_cap_2_bits { 2075 u8 reserved_at_0[0x80]; 2076 2077 u8 migratable[0x1]; 2078 u8 reserved_at_81[0x1f]; 2079 2080 u8 max_reformat_insert_size[0x8]; 2081 u8 max_reformat_insert_offset[0x8]; 2082 u8 max_reformat_remove_size[0x8]; 2083 u8 max_reformat_remove_offset[0x8]; 2084 2085 u8 reserved_at_c0[0x8]; 2086 u8 migration_multi_load[0x1]; 2087 u8 migration_tracking_state[0x1]; 2088 u8 multiplane_qp_ud[0x1]; 2089 u8 reserved_at_cb[0x5]; 2090 u8 migration_in_chunks[0x1]; 2091 u8 reserved_at_d1[0x1]; 2092 u8 sf_eq_usage[0x1]; 2093 u8 reserved_at_d3[0xd]; 2094 2095 u8 cross_vhca_object_to_object_supported[0x20]; 2096 2097 u8 allowed_object_for_other_vhca_access[0x40]; 2098 2099 u8 reserved_at_140[0x60]; 2100 2101 u8 flow_table_type_2_type[0x8]; 2102 u8 reserved_at_1a8[0x2]; 2103 u8 format_select_dw_8_6_ext[0x1]; 2104 u8 log_min_mkey_entity_size[0x5]; 2105 u8 reserved_at_1b0[0x10]; 2106 2107 u8 reserved_at_1c0[0x60]; 2108 2109 u8 reserved_at_220[0x1]; 2110 u8 sw_vhca_id_valid[0x1]; 2111 u8 sw_vhca_id[0xe]; 2112 u8 reserved_at_230[0x10]; 2113 2114 u8 reserved_at_240[0xb]; 2115 u8 ts_cqe_metadata_size2wqe_counter[0x5]; 2116 u8 reserved_at_250[0x10]; 2117 2118 u8 reserved_at_260[0x120]; 2119 2120 u8 format_select_dw_gtpu_dw_0[0x8]; 2121 u8 format_select_dw_gtpu_dw_1[0x8]; 2122 u8 format_select_dw_gtpu_dw_2[0x8]; 2123 u8 format_select_dw_gtpu_first_ext_dw_0[0x8]; 2124 2125 u8 generate_wqe_type[0x20]; 2126 2127 u8 reserved_at_2c0[0xc0]; 2128 2129 u8 reserved_at_380[0xb]; 2130 u8 min_mkey_log_entity_size_fixed_buffer[0x5]; 2131 u8 ec_vf_vport_base[0x10]; 2132 2133 u8 reserved_at_3a0[0x10]; 2134 u8 max_rqt_vhca_id[0x10]; 2135 2136 u8 reserved_at_3c0[0x20]; 2137 2138 u8 reserved_at_3e0[0x10]; 2139 u8 pcc_ifa2[0x1]; 2140 u8 reserved_at_3f1[0xf]; 2141 2142 u8 reserved_at_400[0x1]; 2143 u8 min_mkey_log_entity_size_fixed_buffer_valid[0x1]; 2144 u8 reserved_at_402[0xe]; 2145 u8 return_reg_id[0x10]; 2146 2147 u8 reserved_at_420[0x1c]; 2148 u8 flow_table_hash_type[0x4]; 2149 2150 u8 reserved_at_440[0x8]; 2151 u8 max_num_eqs_24b[0x18]; 2152 u8 reserved_at_460[0x3a0]; 2153 }; 2154 2155 enum mlx5_ifc_flow_destination_type { 2156 MLX5_IFC_FLOW_DESTINATION_TYPE_VPORT = 0x0, 2157 MLX5_IFC_FLOW_DESTINATION_TYPE_FLOW_TABLE = 0x1, 2158 MLX5_IFC_FLOW_DESTINATION_TYPE_TIR = 0x2, 2159 MLX5_IFC_FLOW_DESTINATION_TYPE_FLOW_SAMPLER = 0x6, 2160 MLX5_IFC_FLOW_DESTINATION_TYPE_UPLINK = 0x8, 2161 MLX5_IFC_FLOW_DESTINATION_TYPE_TABLE_TYPE = 0xA, 2162 }; 2163 2164 enum mlx5_flow_table_miss_action { 2165 MLX5_FLOW_TABLE_MISS_ACTION_DEF, 2166 MLX5_FLOW_TABLE_MISS_ACTION_FWD, 2167 MLX5_FLOW_TABLE_MISS_ACTION_SWITCH_DOMAIN, 2168 }; 2169 2170 struct mlx5_ifc_dest_format_struct_bits { 2171 u8 destination_type[0x8]; 2172 u8 destination_id[0x18]; 2173 2174 u8 destination_eswitch_owner_vhca_id_valid[0x1]; 2175 u8 packet_reformat[0x1]; 2176 u8 reserved_at_22[0x6]; 2177 u8 destination_table_type[0x8]; 2178 u8 destination_eswitch_owner_vhca_id[0x10]; 2179 }; 2180 2181 struct mlx5_ifc_flow_counter_list_bits { 2182 u8 flow_counter_id[0x20]; 2183 2184 u8 reserved_at_20[0x20]; 2185 }; 2186 2187 struct mlx5_ifc_extended_dest_format_bits { 2188 struct mlx5_ifc_dest_format_struct_bits destination_entry; 2189 2190 u8 packet_reformat_id[0x20]; 2191 2192 u8 reserved_at_60[0x20]; 2193 }; 2194 2195 union mlx5_ifc_dest_format_flow_counter_list_auto_bits { 2196 struct mlx5_ifc_extended_dest_format_bits extended_dest_format; 2197 struct mlx5_ifc_flow_counter_list_bits flow_counter_list; 2198 }; 2199 2200 struct mlx5_ifc_fte_match_param_bits { 2201 struct mlx5_ifc_fte_match_set_lyr_2_4_bits outer_headers; 2202 2203 struct mlx5_ifc_fte_match_set_misc_bits misc_parameters; 2204 2205 struct mlx5_ifc_fte_match_set_lyr_2_4_bits inner_headers; 2206 2207 struct mlx5_ifc_fte_match_set_misc2_bits misc_parameters_2; 2208 2209 struct mlx5_ifc_fte_match_set_misc3_bits misc_parameters_3; 2210 2211 struct mlx5_ifc_fte_match_set_misc4_bits misc_parameters_4; 2212 2213 struct mlx5_ifc_fte_match_set_misc5_bits misc_parameters_5; 2214 2215 u8 reserved_at_e00[0x200]; 2216 }; 2217 2218 enum { 2219 MLX5_RX_HASH_FIELD_SELECT_SELECTED_FIELDS_SRC_IP = 0x0, 2220 MLX5_RX_HASH_FIELD_SELECT_SELECTED_FIELDS_DST_IP = 0x1, 2221 MLX5_RX_HASH_FIELD_SELECT_SELECTED_FIELDS_L4_SPORT = 0x2, 2222 MLX5_RX_HASH_FIELD_SELECT_SELECTED_FIELDS_L4_DPORT = 0x3, 2223 MLX5_RX_HASH_FIELD_SELECT_SELECTED_FIELDS_IPSEC_SPI = 0x4, 2224 }; 2225 2226 struct mlx5_ifc_rx_hash_field_select_bits { 2227 u8 l3_prot_type[0x1]; 2228 u8 l4_prot_type[0x1]; 2229 u8 selected_fields[0x1e]; 2230 }; 2231 2232 enum { 2233 MLX5_WQ_WQ_TYPE_WQ_LINKED_LIST = 0x0, 2234 MLX5_WQ_WQ_TYPE_WQ_CYCLIC = 0x1, 2235 }; 2236 2237 enum { 2238 MLX5_WQ_END_PADDING_MODE_END_PAD_NONE = 0x0, 2239 MLX5_WQ_END_PADDING_MODE_END_PAD_ALIGN = 0x1, 2240 }; 2241 2242 struct mlx5_ifc_wq_bits { 2243 u8 wq_type[0x4]; 2244 u8 wq_signature[0x1]; 2245 u8 end_padding_mode[0x2]; 2246 u8 cd_slave[0x1]; 2247 u8 reserved_at_8[0x18]; 2248 2249 u8 hds_skip_first_sge[0x1]; 2250 u8 log2_hds_buf_size[0x3]; 2251 u8 reserved_at_24[0x7]; 2252 u8 page_offset[0x5]; 2253 u8 lwm[0x10]; 2254 2255 u8 reserved_at_40[0x8]; 2256 u8 pd[0x18]; 2257 2258 u8 reserved_at_60[0x8]; 2259 u8 uar_page[0x18]; 2260 2261 u8 dbr_addr[0x40]; 2262 2263 u8 hw_counter[0x20]; 2264 2265 u8 sw_counter[0x20]; 2266 2267 u8 reserved_at_100[0xc]; 2268 u8 log_wq_stride[0x4]; 2269 u8 reserved_at_110[0x3]; 2270 u8 log_wq_pg_sz[0x5]; 2271 u8 reserved_at_118[0x3]; 2272 u8 log_wq_sz[0x5]; 2273 2274 u8 dbr_umem_valid[0x1]; 2275 u8 wq_umem_valid[0x1]; 2276 u8 reserved_at_122[0x1]; 2277 u8 log_hairpin_num_packets[0x5]; 2278 u8 reserved_at_128[0x3]; 2279 u8 log_hairpin_data_sz[0x5]; 2280 2281 u8 reserved_at_130[0x4]; 2282 u8 log_wqe_num_of_strides[0x4]; 2283 u8 two_byte_shift_en[0x1]; 2284 u8 reserved_at_139[0x4]; 2285 u8 log_wqe_stride_size[0x3]; 2286 2287 u8 dbr_umem_id[0x20]; 2288 u8 wq_umem_id[0x20]; 2289 2290 u8 wq_umem_offset[0x40]; 2291 2292 u8 headers_mkey[0x20]; 2293 2294 u8 shampo_enable[0x1]; 2295 u8 reserved_at_1e1[0x4]; 2296 u8 log_reservation_size[0x3]; 2297 u8 reserved_at_1e8[0x5]; 2298 u8 log_max_num_of_packets_per_reservation[0x3]; 2299 u8 reserved_at_1f0[0x6]; 2300 u8 log_headers_entry_size[0x2]; 2301 u8 reserved_at_1f8[0x4]; 2302 u8 log_headers_buffer_entry_num[0x4]; 2303 2304 u8 reserved_at_200[0x400]; 2305 2306 struct mlx5_ifc_cmd_pas_bits pas[]; 2307 }; 2308 2309 struct mlx5_ifc_rq_num_bits { 2310 u8 reserved_at_0[0x8]; 2311 u8 rq_num[0x18]; 2312 }; 2313 2314 struct mlx5_ifc_rq_vhca_bits { 2315 u8 reserved_at_0[0x8]; 2316 u8 rq_num[0x18]; 2317 u8 reserved_at_20[0x10]; 2318 u8 rq_vhca_id[0x10]; 2319 }; 2320 2321 struct mlx5_ifc_mac_address_layout_bits { 2322 u8 reserved_at_0[0x10]; 2323 u8 mac_addr_47_32[0x10]; 2324 2325 u8 mac_addr_31_0[0x20]; 2326 }; 2327 2328 struct mlx5_ifc_vlan_layout_bits { 2329 u8 reserved_at_0[0x14]; 2330 u8 vlan[0x0c]; 2331 2332 u8 reserved_at_20[0x20]; 2333 }; 2334 2335 struct mlx5_ifc_cong_control_r_roce_ecn_np_bits { 2336 u8 reserved_at_0[0xa0]; 2337 2338 u8 min_time_between_cnps[0x20]; 2339 2340 u8 reserved_at_c0[0x12]; 2341 u8 cnp_dscp[0x6]; 2342 u8 reserved_at_d8[0x4]; 2343 u8 cnp_prio_mode[0x1]; 2344 u8 cnp_802p_prio[0x3]; 2345 2346 u8 reserved_at_e0[0x720]; 2347 }; 2348 2349 struct mlx5_ifc_cong_control_r_roce_ecn_rp_bits { 2350 u8 reserved_at_0[0x60]; 2351 2352 u8 reserved_at_60[0x4]; 2353 u8 clamp_tgt_rate[0x1]; 2354 u8 reserved_at_65[0x3]; 2355 u8 clamp_tgt_rate_after_time_inc[0x1]; 2356 u8 reserved_at_69[0x17]; 2357 2358 u8 reserved_at_80[0x20]; 2359 2360 u8 rpg_time_reset[0x20]; 2361 2362 u8 rpg_byte_reset[0x20]; 2363 2364 u8 rpg_threshold[0x20]; 2365 2366 u8 rpg_max_rate[0x20]; 2367 2368 u8 rpg_ai_rate[0x20]; 2369 2370 u8 rpg_hai_rate[0x20]; 2371 2372 u8 rpg_gd[0x20]; 2373 2374 u8 rpg_min_dec_fac[0x20]; 2375 2376 u8 rpg_min_rate[0x20]; 2377 2378 u8 reserved_at_1c0[0xe0]; 2379 2380 u8 rate_to_set_on_first_cnp[0x20]; 2381 2382 u8 dce_tcp_g[0x20]; 2383 2384 u8 dce_tcp_rtt[0x20]; 2385 2386 u8 rate_reduce_monitor_period[0x20]; 2387 2388 u8 reserved_at_320[0x20]; 2389 2390 u8 initial_alpha_value[0x20]; 2391 2392 u8 reserved_at_360[0x4a0]; 2393 }; 2394 2395 struct mlx5_ifc_cong_control_r_roce_general_bits { 2396 u8 reserved_at_0[0x80]; 2397 2398 u8 reserved_at_80[0x10]; 2399 u8 rtt_resp_dscp_valid[0x1]; 2400 u8 reserved_at_91[0x9]; 2401 u8 rtt_resp_dscp[0x6]; 2402 2403 u8 reserved_at_a0[0x760]; 2404 }; 2405 2406 struct mlx5_ifc_cong_control_802_1qau_rp_bits { 2407 u8 reserved_at_0[0x80]; 2408 2409 u8 rppp_max_rps[0x20]; 2410 2411 u8 rpg_time_reset[0x20]; 2412 2413 u8 rpg_byte_reset[0x20]; 2414 2415 u8 rpg_threshold[0x20]; 2416 2417 u8 rpg_max_rate[0x20]; 2418 2419 u8 rpg_ai_rate[0x20]; 2420 2421 u8 rpg_hai_rate[0x20]; 2422 2423 u8 rpg_gd[0x20]; 2424 2425 u8 rpg_min_dec_fac[0x20]; 2426 2427 u8 rpg_min_rate[0x20]; 2428 2429 u8 reserved_at_1c0[0x640]; 2430 }; 2431 2432 enum { 2433 MLX5_RESIZE_FIELD_SELECT_RESIZE_FIELD_SELECT_LOG_CQ_SIZE = 0x1, 2434 MLX5_RESIZE_FIELD_SELECT_RESIZE_FIELD_SELECT_PAGE_OFFSET = 0x2, 2435 MLX5_RESIZE_FIELD_SELECT_RESIZE_FIELD_SELECT_LOG_PAGE_SIZE = 0x4, 2436 }; 2437 2438 struct mlx5_ifc_resize_field_select_bits { 2439 u8 resize_field_select[0x20]; 2440 }; 2441 2442 struct mlx5_ifc_resource_dump_bits { 2443 u8 more_dump[0x1]; 2444 u8 inline_dump[0x1]; 2445 u8 reserved_at_2[0xa]; 2446 u8 seq_num[0x4]; 2447 u8 segment_type[0x10]; 2448 2449 u8 reserved_at_20[0x10]; 2450 u8 vhca_id[0x10]; 2451 2452 u8 index1[0x20]; 2453 2454 u8 index2[0x20]; 2455 2456 u8 num_of_obj1[0x10]; 2457 u8 num_of_obj2[0x10]; 2458 2459 u8 reserved_at_a0[0x20]; 2460 2461 u8 device_opaque[0x40]; 2462 2463 u8 mkey[0x20]; 2464 2465 u8 size[0x20]; 2466 2467 u8 address[0x40]; 2468 2469 u8 inline_data[52][0x20]; 2470 }; 2471 2472 struct mlx5_ifc_resource_dump_menu_record_bits { 2473 u8 reserved_at_0[0x4]; 2474 u8 num_of_obj2_supports_active[0x1]; 2475 u8 num_of_obj2_supports_all[0x1]; 2476 u8 must_have_num_of_obj2[0x1]; 2477 u8 support_num_of_obj2[0x1]; 2478 u8 num_of_obj1_supports_active[0x1]; 2479 u8 num_of_obj1_supports_all[0x1]; 2480 u8 must_have_num_of_obj1[0x1]; 2481 u8 support_num_of_obj1[0x1]; 2482 u8 must_have_index2[0x1]; 2483 u8 support_index2[0x1]; 2484 u8 must_have_index1[0x1]; 2485 u8 support_index1[0x1]; 2486 u8 segment_type[0x10]; 2487 2488 u8 segment_name[4][0x20]; 2489 2490 u8 index1_name[4][0x20]; 2491 2492 u8 index2_name[4][0x20]; 2493 }; 2494 2495 struct mlx5_ifc_resource_dump_segment_header_bits { 2496 u8 length_dw[0x10]; 2497 u8 segment_type[0x10]; 2498 }; 2499 2500 struct mlx5_ifc_resource_dump_command_segment_bits { 2501 struct mlx5_ifc_resource_dump_segment_header_bits segment_header; 2502 2503 u8 segment_called[0x10]; 2504 u8 vhca_id[0x10]; 2505 2506 u8 index1[0x20]; 2507 2508 u8 index2[0x20]; 2509 2510 u8 num_of_obj1[0x10]; 2511 u8 num_of_obj2[0x10]; 2512 }; 2513 2514 struct mlx5_ifc_resource_dump_error_segment_bits { 2515 struct mlx5_ifc_resource_dump_segment_header_bits segment_header; 2516 2517 u8 reserved_at_20[0x10]; 2518 u8 syndrome_id[0x10]; 2519 2520 u8 reserved_at_40[0x40]; 2521 2522 u8 error[8][0x20]; 2523 }; 2524 2525 struct mlx5_ifc_resource_dump_info_segment_bits { 2526 struct mlx5_ifc_resource_dump_segment_header_bits segment_header; 2527 2528 u8 reserved_at_20[0x18]; 2529 u8 dump_version[0x8]; 2530 2531 u8 hw_version[0x20]; 2532 2533 u8 fw_version[0x20]; 2534 }; 2535 2536 struct mlx5_ifc_resource_dump_menu_segment_bits { 2537 struct mlx5_ifc_resource_dump_segment_header_bits segment_header; 2538 2539 u8 reserved_at_20[0x10]; 2540 u8 num_of_records[0x10]; 2541 2542 struct mlx5_ifc_resource_dump_menu_record_bits record[]; 2543 }; 2544 2545 struct mlx5_ifc_resource_dump_resource_segment_bits { 2546 struct mlx5_ifc_resource_dump_segment_header_bits segment_header; 2547 2548 u8 reserved_at_20[0x20]; 2549 2550 u8 index1[0x20]; 2551 2552 u8 index2[0x20]; 2553 2554 u8 payload[][0x20]; 2555 }; 2556 2557 struct mlx5_ifc_resource_dump_terminate_segment_bits { 2558 struct mlx5_ifc_resource_dump_segment_header_bits segment_header; 2559 }; 2560 2561 struct mlx5_ifc_menu_resource_dump_response_bits { 2562 struct mlx5_ifc_resource_dump_info_segment_bits info; 2563 struct mlx5_ifc_resource_dump_command_segment_bits cmd; 2564 struct mlx5_ifc_resource_dump_menu_segment_bits menu; 2565 struct mlx5_ifc_resource_dump_terminate_segment_bits terminate; 2566 }; 2567 2568 enum { 2569 MLX5_MODIFY_FIELD_SELECT_MODIFY_FIELD_SELECT_CQ_PERIOD = 0x1, 2570 MLX5_MODIFY_FIELD_SELECT_MODIFY_FIELD_SELECT_CQ_MAX_COUNT = 0x2, 2571 MLX5_MODIFY_FIELD_SELECT_MODIFY_FIELD_SELECT_OI = 0x4, 2572 MLX5_MODIFY_FIELD_SELECT_MODIFY_FIELD_SELECT_C_EQN = 0x8, 2573 }; 2574 2575 struct mlx5_ifc_modify_field_select_bits { 2576 u8 modify_field_select[0x20]; 2577 }; 2578 2579 struct mlx5_ifc_field_select_r_roce_np_bits { 2580 u8 field_select_r_roce_np[0x20]; 2581 }; 2582 2583 struct mlx5_ifc_field_select_r_roce_rp_bits { 2584 u8 field_select_r_roce_rp[0x20]; 2585 }; 2586 2587 enum { 2588 MLX5_FIELD_SELECT_802_1QAU_RP_FIELD_SELECT_8021QAURP_RPPP_MAX_RPS = 0x4, 2589 MLX5_FIELD_SELECT_802_1QAU_RP_FIELD_SELECT_8021QAURP_RPG_TIME_RESET = 0x8, 2590 MLX5_FIELD_SELECT_802_1QAU_RP_FIELD_SELECT_8021QAURP_RPG_BYTE_RESET = 0x10, 2591 MLX5_FIELD_SELECT_802_1QAU_RP_FIELD_SELECT_8021QAURP_RPG_THRESHOLD = 0x20, 2592 MLX5_FIELD_SELECT_802_1QAU_RP_FIELD_SELECT_8021QAURP_RPG_MAX_RATE = 0x40, 2593 MLX5_FIELD_SELECT_802_1QAU_RP_FIELD_SELECT_8021QAURP_RPG_AI_RATE = 0x80, 2594 MLX5_FIELD_SELECT_802_1QAU_RP_FIELD_SELECT_8021QAURP_RPG_HAI_RATE = 0x100, 2595 MLX5_FIELD_SELECT_802_1QAU_RP_FIELD_SELECT_8021QAURP_RPG_GD = 0x200, 2596 MLX5_FIELD_SELECT_802_1QAU_RP_FIELD_SELECT_8021QAURP_RPG_MIN_DEC_FAC = 0x400, 2597 MLX5_FIELD_SELECT_802_1QAU_RP_FIELD_SELECT_8021QAURP_RPG_MIN_RATE = 0x800, 2598 }; 2599 2600 struct mlx5_ifc_field_select_802_1qau_rp_bits { 2601 u8 field_select_8021qaurp[0x20]; 2602 }; 2603 2604 struct mlx5_ifc_phys_layer_cntrs_bits { 2605 u8 time_since_last_clear_high[0x20]; 2606 2607 u8 time_since_last_clear_low[0x20]; 2608 2609 u8 symbol_errors_high[0x20]; 2610 2611 u8 symbol_errors_low[0x20]; 2612 2613 u8 sync_headers_errors_high[0x20]; 2614 2615 u8 sync_headers_errors_low[0x20]; 2616 2617 u8 edpl_bip_errors_lane0_high[0x20]; 2618 2619 u8 edpl_bip_errors_lane0_low[0x20]; 2620 2621 u8 edpl_bip_errors_lane1_high[0x20]; 2622 2623 u8 edpl_bip_errors_lane1_low[0x20]; 2624 2625 u8 edpl_bip_errors_lane2_high[0x20]; 2626 2627 u8 edpl_bip_errors_lane2_low[0x20]; 2628 2629 u8 edpl_bip_errors_lane3_high[0x20]; 2630 2631 u8 edpl_bip_errors_lane3_low[0x20]; 2632 2633 u8 fc_fec_corrected_blocks_lane0_high[0x20]; 2634 2635 u8 fc_fec_corrected_blocks_lane0_low[0x20]; 2636 2637 u8 fc_fec_corrected_blocks_lane1_high[0x20]; 2638 2639 u8 fc_fec_corrected_blocks_lane1_low[0x20]; 2640 2641 u8 fc_fec_corrected_blocks_lane2_high[0x20]; 2642 2643 u8 fc_fec_corrected_blocks_lane2_low[0x20]; 2644 2645 u8 fc_fec_corrected_blocks_lane3_high[0x20]; 2646 2647 u8 fc_fec_corrected_blocks_lane3_low[0x20]; 2648 2649 u8 fc_fec_uncorrectable_blocks_lane0_high[0x20]; 2650 2651 u8 fc_fec_uncorrectable_blocks_lane0_low[0x20]; 2652 2653 u8 fc_fec_uncorrectable_blocks_lane1_high[0x20]; 2654 2655 u8 fc_fec_uncorrectable_blocks_lane1_low[0x20]; 2656 2657 u8 fc_fec_uncorrectable_blocks_lane2_high[0x20]; 2658 2659 u8 fc_fec_uncorrectable_blocks_lane2_low[0x20]; 2660 2661 u8 fc_fec_uncorrectable_blocks_lane3_high[0x20]; 2662 2663 u8 fc_fec_uncorrectable_blocks_lane3_low[0x20]; 2664 2665 u8 rs_fec_corrected_blocks_high[0x20]; 2666 2667 u8 rs_fec_corrected_blocks_low[0x20]; 2668 2669 u8 rs_fec_uncorrectable_blocks_high[0x20]; 2670 2671 u8 rs_fec_uncorrectable_blocks_low[0x20]; 2672 2673 u8 rs_fec_no_errors_blocks_high[0x20]; 2674 2675 u8 rs_fec_no_errors_blocks_low[0x20]; 2676 2677 u8 rs_fec_single_error_blocks_high[0x20]; 2678 2679 u8 rs_fec_single_error_blocks_low[0x20]; 2680 2681 u8 rs_fec_corrected_symbols_total_high[0x20]; 2682 2683 u8 rs_fec_corrected_symbols_total_low[0x20]; 2684 2685 u8 rs_fec_corrected_symbols_lane0_high[0x20]; 2686 2687 u8 rs_fec_corrected_symbols_lane0_low[0x20]; 2688 2689 u8 rs_fec_corrected_symbols_lane1_high[0x20]; 2690 2691 u8 rs_fec_corrected_symbols_lane1_low[0x20]; 2692 2693 u8 rs_fec_corrected_symbols_lane2_high[0x20]; 2694 2695 u8 rs_fec_corrected_symbols_lane2_low[0x20]; 2696 2697 u8 rs_fec_corrected_symbols_lane3_high[0x20]; 2698 2699 u8 rs_fec_corrected_symbols_lane3_low[0x20]; 2700 2701 u8 link_down_events[0x20]; 2702 2703 u8 successful_recovery_events[0x20]; 2704 2705 u8 reserved_at_640[0x180]; 2706 }; 2707 2708 struct mlx5_ifc_phys_layer_statistical_cntrs_bits { 2709 u8 time_since_last_clear_high[0x20]; 2710 2711 u8 time_since_last_clear_low[0x20]; 2712 2713 u8 phy_received_bits_high[0x20]; 2714 2715 u8 phy_received_bits_low[0x20]; 2716 2717 u8 phy_symbol_errors_high[0x20]; 2718 2719 u8 phy_symbol_errors_low[0x20]; 2720 2721 u8 phy_corrected_bits_high[0x20]; 2722 2723 u8 phy_corrected_bits_low[0x20]; 2724 2725 u8 phy_corrected_bits_lane0_high[0x20]; 2726 2727 u8 phy_corrected_bits_lane0_low[0x20]; 2728 2729 u8 phy_corrected_bits_lane1_high[0x20]; 2730 2731 u8 phy_corrected_bits_lane1_low[0x20]; 2732 2733 u8 phy_corrected_bits_lane2_high[0x20]; 2734 2735 u8 phy_corrected_bits_lane2_low[0x20]; 2736 2737 u8 phy_corrected_bits_lane3_high[0x20]; 2738 2739 u8 phy_corrected_bits_lane3_low[0x20]; 2740 2741 u8 reserved_at_200[0x5c0]; 2742 }; 2743 2744 struct mlx5_ifc_ib_port_cntrs_grp_data_layout_bits { 2745 u8 symbol_error_counter[0x10]; 2746 2747 u8 link_error_recovery_counter[0x8]; 2748 2749 u8 link_downed_counter[0x8]; 2750 2751 u8 port_rcv_errors[0x10]; 2752 2753 u8 port_rcv_remote_physical_errors[0x10]; 2754 2755 u8 port_rcv_switch_relay_errors[0x10]; 2756 2757 u8 port_xmit_discards[0x10]; 2758 2759 u8 port_xmit_constraint_errors[0x8]; 2760 2761 u8 port_rcv_constraint_errors[0x8]; 2762 2763 u8 reserved_at_70[0x8]; 2764 2765 u8 link_overrun_errors[0x8]; 2766 2767 u8 reserved_at_80[0x10]; 2768 2769 u8 vl_15_dropped[0x10]; 2770 2771 u8 reserved_at_a0[0x80]; 2772 2773 u8 port_xmit_wait[0x20]; 2774 }; 2775 2776 struct mlx5_ifc_ib_ext_port_cntrs_grp_data_layout_bits { 2777 u8 reserved_at_0[0x300]; 2778 2779 u8 port_xmit_data_high[0x20]; 2780 2781 u8 port_xmit_data_low[0x20]; 2782 2783 u8 port_rcv_data_high[0x20]; 2784 2785 u8 port_rcv_data_low[0x20]; 2786 2787 u8 port_xmit_pkts_high[0x20]; 2788 2789 u8 port_xmit_pkts_low[0x20]; 2790 2791 u8 port_rcv_pkts_high[0x20]; 2792 2793 u8 port_rcv_pkts_low[0x20]; 2794 2795 u8 reserved_at_400[0x80]; 2796 2797 u8 port_unicast_xmit_pkts_high[0x20]; 2798 2799 u8 port_unicast_xmit_pkts_low[0x20]; 2800 2801 u8 port_multicast_xmit_pkts_high[0x20]; 2802 2803 u8 port_multicast_xmit_pkts_low[0x20]; 2804 2805 u8 port_unicast_rcv_pkts_high[0x20]; 2806 2807 u8 port_unicast_rcv_pkts_low[0x20]; 2808 2809 u8 port_multicast_rcv_pkts_high[0x20]; 2810 2811 u8 port_multicast_rcv_pkts_low[0x20]; 2812 2813 u8 reserved_at_580[0x240]; 2814 }; 2815 2816 struct mlx5_ifc_eth_per_tc_prio_grp_data_layout_bits { 2817 u8 transmit_queue_high[0x20]; 2818 2819 u8 transmit_queue_low[0x20]; 2820 2821 u8 no_buffer_discard_uc_high[0x20]; 2822 2823 u8 no_buffer_discard_uc_low[0x20]; 2824 2825 u8 reserved_at_80[0x740]; 2826 }; 2827 2828 struct mlx5_ifc_eth_per_tc_congest_prio_grp_data_layout_bits { 2829 u8 wred_discard_high[0x20]; 2830 2831 u8 wred_discard_low[0x20]; 2832 2833 u8 ecn_marked_tc_high[0x20]; 2834 2835 u8 ecn_marked_tc_low[0x20]; 2836 2837 u8 reserved_at_80[0x740]; 2838 }; 2839 2840 struct mlx5_ifc_eth_per_prio_grp_data_layout_bits { 2841 u8 rx_octets_high[0x20]; 2842 2843 u8 rx_octets_low[0x20]; 2844 2845 u8 reserved_at_40[0xc0]; 2846 2847 u8 rx_frames_high[0x20]; 2848 2849 u8 rx_frames_low[0x20]; 2850 2851 u8 tx_octets_high[0x20]; 2852 2853 u8 tx_octets_low[0x20]; 2854 2855 u8 reserved_at_180[0xc0]; 2856 2857 u8 tx_frames_high[0x20]; 2858 2859 u8 tx_frames_low[0x20]; 2860 2861 u8 rx_pause_high[0x20]; 2862 2863 u8 rx_pause_low[0x20]; 2864 2865 u8 rx_pause_duration_high[0x20]; 2866 2867 u8 rx_pause_duration_low[0x20]; 2868 2869 u8 tx_pause_high[0x20]; 2870 2871 u8 tx_pause_low[0x20]; 2872 2873 u8 tx_pause_duration_high[0x20]; 2874 2875 u8 tx_pause_duration_low[0x20]; 2876 2877 u8 rx_pause_transition_high[0x20]; 2878 2879 u8 rx_pause_transition_low[0x20]; 2880 2881 u8 rx_discards_high[0x20]; 2882 2883 u8 rx_discards_low[0x20]; 2884 2885 u8 device_stall_minor_watermark_cnt_high[0x20]; 2886 2887 u8 device_stall_minor_watermark_cnt_low[0x20]; 2888 2889 u8 device_stall_critical_watermark_cnt_high[0x20]; 2890 2891 u8 device_stall_critical_watermark_cnt_low[0x20]; 2892 2893 u8 reserved_at_480[0x340]; 2894 }; 2895 2896 struct mlx5_ifc_eth_extended_cntrs_grp_data_layout_bits { 2897 u8 port_transmit_wait_high[0x20]; 2898 2899 u8 port_transmit_wait_low[0x20]; 2900 2901 u8 reserved_at_40[0x100]; 2902 2903 u8 rx_buffer_almost_full_high[0x20]; 2904 2905 u8 rx_buffer_almost_full_low[0x20]; 2906 2907 u8 rx_buffer_full_high[0x20]; 2908 2909 u8 rx_buffer_full_low[0x20]; 2910 2911 u8 rx_icrc_encapsulated_high[0x20]; 2912 2913 u8 rx_icrc_encapsulated_low[0x20]; 2914 2915 u8 reserved_at_200[0x5c0]; 2916 }; 2917 2918 struct mlx5_ifc_eth_3635_cntrs_grp_data_layout_bits { 2919 u8 dot3stats_alignment_errors_high[0x20]; 2920 2921 u8 dot3stats_alignment_errors_low[0x20]; 2922 2923 u8 dot3stats_fcs_errors_high[0x20]; 2924 2925 u8 dot3stats_fcs_errors_low[0x20]; 2926 2927 u8 dot3stats_single_collision_frames_high[0x20]; 2928 2929 u8 dot3stats_single_collision_frames_low[0x20]; 2930 2931 u8 dot3stats_multiple_collision_frames_high[0x20]; 2932 2933 u8 dot3stats_multiple_collision_frames_low[0x20]; 2934 2935 u8 dot3stats_sqe_test_errors_high[0x20]; 2936 2937 u8 dot3stats_sqe_test_errors_low[0x20]; 2938 2939 u8 dot3stats_deferred_transmissions_high[0x20]; 2940 2941 u8 dot3stats_deferred_transmissions_low[0x20]; 2942 2943 u8 dot3stats_late_collisions_high[0x20]; 2944 2945 u8 dot3stats_late_collisions_low[0x20]; 2946 2947 u8 dot3stats_excessive_collisions_high[0x20]; 2948 2949 u8 dot3stats_excessive_collisions_low[0x20]; 2950 2951 u8 dot3stats_internal_mac_transmit_errors_high[0x20]; 2952 2953 u8 dot3stats_internal_mac_transmit_errors_low[0x20]; 2954 2955 u8 dot3stats_carrier_sense_errors_high[0x20]; 2956 2957 u8 dot3stats_carrier_sense_errors_low[0x20]; 2958 2959 u8 dot3stats_frame_too_longs_high[0x20]; 2960 2961 u8 dot3stats_frame_too_longs_low[0x20]; 2962 2963 u8 dot3stats_internal_mac_receive_errors_high[0x20]; 2964 2965 u8 dot3stats_internal_mac_receive_errors_low[0x20]; 2966 2967 u8 dot3stats_symbol_errors_high[0x20]; 2968 2969 u8 dot3stats_symbol_errors_low[0x20]; 2970 2971 u8 dot3control_in_unknown_opcodes_high[0x20]; 2972 2973 u8 dot3control_in_unknown_opcodes_low[0x20]; 2974 2975 u8 dot3in_pause_frames_high[0x20]; 2976 2977 u8 dot3in_pause_frames_low[0x20]; 2978 2979 u8 dot3out_pause_frames_high[0x20]; 2980 2981 u8 dot3out_pause_frames_low[0x20]; 2982 2983 u8 reserved_at_400[0x3c0]; 2984 }; 2985 2986 struct mlx5_ifc_eth_2819_cntrs_grp_data_layout_bits { 2987 u8 ether_stats_drop_events_high[0x20]; 2988 2989 u8 ether_stats_drop_events_low[0x20]; 2990 2991 u8 ether_stats_octets_high[0x20]; 2992 2993 u8 ether_stats_octets_low[0x20]; 2994 2995 u8 ether_stats_pkts_high[0x20]; 2996 2997 u8 ether_stats_pkts_low[0x20]; 2998 2999 u8 ether_stats_broadcast_pkts_high[0x20]; 3000 3001 u8 ether_stats_broadcast_pkts_low[0x20]; 3002 3003 u8 ether_stats_multicast_pkts_high[0x20]; 3004 3005 u8 ether_stats_multicast_pkts_low[0x20]; 3006 3007 u8 ether_stats_crc_align_errors_high[0x20]; 3008 3009 u8 ether_stats_crc_align_errors_low[0x20]; 3010 3011 u8 ether_stats_undersize_pkts_high[0x20]; 3012 3013 u8 ether_stats_undersize_pkts_low[0x20]; 3014 3015 u8 ether_stats_oversize_pkts_high[0x20]; 3016 3017 u8 ether_stats_oversize_pkts_low[0x20]; 3018 3019 u8 ether_stats_fragments_high[0x20]; 3020 3021 u8 ether_stats_fragments_low[0x20]; 3022 3023 u8 ether_stats_jabbers_high[0x20]; 3024 3025 u8 ether_stats_jabbers_low[0x20]; 3026 3027 u8 ether_stats_collisions_high[0x20]; 3028 3029 u8 ether_stats_collisions_low[0x20]; 3030 3031 u8 ether_stats_pkts64octets_high[0x20]; 3032 3033 u8 ether_stats_pkts64octets_low[0x20]; 3034 3035 u8 ether_stats_pkts65to127octets_high[0x20]; 3036 3037 u8 ether_stats_pkts65to127octets_low[0x20]; 3038 3039 u8 ether_stats_pkts128to255octets_high[0x20]; 3040 3041 u8 ether_stats_pkts128to255octets_low[0x20]; 3042 3043 u8 ether_stats_pkts256to511octets_high[0x20]; 3044 3045 u8 ether_stats_pkts256to511octets_low[0x20]; 3046 3047 u8 ether_stats_pkts512to1023octets_high[0x20]; 3048 3049 u8 ether_stats_pkts512to1023octets_low[0x20]; 3050 3051 u8 ether_stats_pkts1024to1518octets_high[0x20]; 3052 3053 u8 ether_stats_pkts1024to1518octets_low[0x20]; 3054 3055 u8 ether_stats_pkts1519to2047octets_high[0x20]; 3056 3057 u8 ether_stats_pkts1519to2047octets_low[0x20]; 3058 3059 u8 ether_stats_pkts2048to4095octets_high[0x20]; 3060 3061 u8 ether_stats_pkts2048to4095octets_low[0x20]; 3062 3063 u8 ether_stats_pkts4096to8191octets_high[0x20]; 3064 3065 u8 ether_stats_pkts4096to8191octets_low[0x20]; 3066 3067 u8 ether_stats_pkts8192to10239octets_high[0x20]; 3068 3069 u8 ether_stats_pkts8192to10239octets_low[0x20]; 3070 3071 u8 reserved_at_540[0x280]; 3072 }; 3073 3074 struct mlx5_ifc_eth_2863_cntrs_grp_data_layout_bits { 3075 u8 if_in_octets_high[0x20]; 3076 3077 u8 if_in_octets_low[0x20]; 3078 3079 u8 if_in_ucast_pkts_high[0x20]; 3080 3081 u8 if_in_ucast_pkts_low[0x20]; 3082 3083 u8 if_in_discards_high[0x20]; 3084 3085 u8 if_in_discards_low[0x20]; 3086 3087 u8 if_in_errors_high[0x20]; 3088 3089 u8 if_in_errors_low[0x20]; 3090 3091 u8 if_in_unknown_protos_high[0x20]; 3092 3093 u8 if_in_unknown_protos_low[0x20]; 3094 3095 u8 if_out_octets_high[0x20]; 3096 3097 u8 if_out_octets_low[0x20]; 3098 3099 u8 if_out_ucast_pkts_high[0x20]; 3100 3101 u8 if_out_ucast_pkts_low[0x20]; 3102 3103 u8 if_out_discards_high[0x20]; 3104 3105 u8 if_out_discards_low[0x20]; 3106 3107 u8 if_out_errors_high[0x20]; 3108 3109 u8 if_out_errors_low[0x20]; 3110 3111 u8 if_in_multicast_pkts_high[0x20]; 3112 3113 u8 if_in_multicast_pkts_low[0x20]; 3114 3115 u8 if_in_broadcast_pkts_high[0x20]; 3116 3117 u8 if_in_broadcast_pkts_low[0x20]; 3118 3119 u8 if_out_multicast_pkts_high[0x20]; 3120 3121 u8 if_out_multicast_pkts_low[0x20]; 3122 3123 u8 if_out_broadcast_pkts_high[0x20]; 3124 3125 u8 if_out_broadcast_pkts_low[0x20]; 3126 3127 u8 reserved_at_340[0x480]; 3128 }; 3129 3130 struct mlx5_ifc_eth_802_3_cntrs_grp_data_layout_bits { 3131 u8 a_frames_transmitted_ok_high[0x20]; 3132 3133 u8 a_frames_transmitted_ok_low[0x20]; 3134 3135 u8 a_frames_received_ok_high[0x20]; 3136 3137 u8 a_frames_received_ok_low[0x20]; 3138 3139 u8 a_frame_check_sequence_errors_high[0x20]; 3140 3141 u8 a_frame_check_sequence_errors_low[0x20]; 3142 3143 u8 a_alignment_errors_high[0x20]; 3144 3145 u8 a_alignment_errors_low[0x20]; 3146 3147 u8 a_octets_transmitted_ok_high[0x20]; 3148 3149 u8 a_octets_transmitted_ok_low[0x20]; 3150 3151 u8 a_octets_received_ok_high[0x20]; 3152 3153 u8 a_octets_received_ok_low[0x20]; 3154 3155 u8 a_multicast_frames_xmitted_ok_high[0x20]; 3156 3157 u8 a_multicast_frames_xmitted_ok_low[0x20]; 3158 3159 u8 a_broadcast_frames_xmitted_ok_high[0x20]; 3160 3161 u8 a_broadcast_frames_xmitted_ok_low[0x20]; 3162 3163 u8 a_multicast_frames_received_ok_high[0x20]; 3164 3165 u8 a_multicast_frames_received_ok_low[0x20]; 3166 3167 u8 a_broadcast_frames_received_ok_high[0x20]; 3168 3169 u8 a_broadcast_frames_received_ok_low[0x20]; 3170 3171 u8 a_in_range_length_errors_high[0x20]; 3172 3173 u8 a_in_range_length_errors_low[0x20]; 3174 3175 u8 a_out_of_range_length_field_high[0x20]; 3176 3177 u8 a_out_of_range_length_field_low[0x20]; 3178 3179 u8 a_frame_too_long_errors_high[0x20]; 3180 3181 u8 a_frame_too_long_errors_low[0x20]; 3182 3183 u8 a_symbol_error_during_carrier_high[0x20]; 3184 3185 u8 a_symbol_error_during_carrier_low[0x20]; 3186 3187 u8 a_mac_control_frames_transmitted_high[0x20]; 3188 3189 u8 a_mac_control_frames_transmitted_low[0x20]; 3190 3191 u8 a_mac_control_frames_received_high[0x20]; 3192 3193 u8 a_mac_control_frames_received_low[0x20]; 3194 3195 u8 a_unsupported_opcodes_received_high[0x20]; 3196 3197 u8 a_unsupported_opcodes_received_low[0x20]; 3198 3199 u8 a_pause_mac_ctrl_frames_received_high[0x20]; 3200 3201 u8 a_pause_mac_ctrl_frames_received_low[0x20]; 3202 3203 u8 a_pause_mac_ctrl_frames_transmitted_high[0x20]; 3204 3205 u8 a_pause_mac_ctrl_frames_transmitted_low[0x20]; 3206 3207 u8 reserved_at_4c0[0x300]; 3208 }; 3209 3210 struct mlx5_ifc_pcie_perf_cntrs_grp_data_layout_bits { 3211 u8 life_time_counter_high[0x20]; 3212 3213 u8 life_time_counter_low[0x20]; 3214 3215 u8 rx_errors[0x20]; 3216 3217 u8 tx_errors[0x20]; 3218 3219 u8 l0_to_recovery_eieos[0x20]; 3220 3221 u8 l0_to_recovery_ts[0x20]; 3222 3223 u8 l0_to_recovery_framing[0x20]; 3224 3225 u8 l0_to_recovery_retrain[0x20]; 3226 3227 u8 crc_error_dllp[0x20]; 3228 3229 u8 crc_error_tlp[0x20]; 3230 3231 u8 tx_overflow_buffer_pkt_high[0x20]; 3232 3233 u8 tx_overflow_buffer_pkt_low[0x20]; 3234 3235 u8 outbound_stalled_reads[0x20]; 3236 3237 u8 outbound_stalled_writes[0x20]; 3238 3239 u8 outbound_stalled_reads_events[0x20]; 3240 3241 u8 outbound_stalled_writes_events[0x20]; 3242 3243 u8 reserved_at_200[0x5c0]; 3244 }; 3245 3246 struct mlx5_ifc_cmd_inter_comp_event_bits { 3247 u8 command_completion_vector[0x20]; 3248 3249 u8 reserved_at_20[0xc0]; 3250 }; 3251 3252 struct mlx5_ifc_stall_vl_event_bits { 3253 u8 reserved_at_0[0x18]; 3254 u8 port_num[0x1]; 3255 u8 reserved_at_19[0x3]; 3256 u8 vl[0x4]; 3257 3258 u8 reserved_at_20[0xa0]; 3259 }; 3260 3261 struct mlx5_ifc_db_bf_congestion_event_bits { 3262 u8 event_subtype[0x8]; 3263 u8 reserved_at_8[0x8]; 3264 u8 congestion_level[0x8]; 3265 u8 reserved_at_18[0x8]; 3266 3267 u8 reserved_at_20[0xa0]; 3268 }; 3269 3270 struct mlx5_ifc_gpio_event_bits { 3271 u8 reserved_at_0[0x60]; 3272 3273 u8 gpio_event_hi[0x20]; 3274 3275 u8 gpio_event_lo[0x20]; 3276 3277 u8 reserved_at_a0[0x40]; 3278 }; 3279 3280 struct mlx5_ifc_port_state_change_event_bits { 3281 u8 reserved_at_0[0x40]; 3282 3283 u8 port_num[0x4]; 3284 u8 reserved_at_44[0x1c]; 3285 3286 u8 reserved_at_60[0x80]; 3287 }; 3288 3289 struct mlx5_ifc_dropped_packet_logged_bits { 3290 u8 reserved_at_0[0xe0]; 3291 }; 3292 3293 struct mlx5_ifc_default_timeout_bits { 3294 u8 to_multiplier[0x3]; 3295 u8 reserved_at_3[0x9]; 3296 u8 to_value[0x14]; 3297 }; 3298 3299 struct mlx5_ifc_dtor_reg_bits { 3300 u8 reserved_at_0[0x20]; 3301 3302 struct mlx5_ifc_default_timeout_bits pcie_toggle_to; 3303 3304 u8 reserved_at_40[0x60]; 3305 3306 struct mlx5_ifc_default_timeout_bits health_poll_to; 3307 3308 struct mlx5_ifc_default_timeout_bits full_crdump_to; 3309 3310 struct mlx5_ifc_default_timeout_bits fw_reset_to; 3311 3312 struct mlx5_ifc_default_timeout_bits flush_on_err_to; 3313 3314 struct mlx5_ifc_default_timeout_bits pci_sync_update_to; 3315 3316 struct mlx5_ifc_default_timeout_bits tear_down_to; 3317 3318 struct mlx5_ifc_default_timeout_bits fsm_reactivate_to; 3319 3320 struct mlx5_ifc_default_timeout_bits reclaim_pages_to; 3321 3322 struct mlx5_ifc_default_timeout_bits reclaim_vfs_pages_to; 3323 3324 struct mlx5_ifc_default_timeout_bits reset_unload_to; 3325 3326 u8 reserved_at_1c0[0x20]; 3327 }; 3328 3329 enum { 3330 MLX5_CQ_ERROR_SYNDROME_CQ_OVERRUN = 0x1, 3331 MLX5_CQ_ERROR_SYNDROME_CQ_ACCESS_VIOLATION_ERROR = 0x2, 3332 }; 3333 3334 struct mlx5_ifc_cq_error_bits { 3335 u8 reserved_at_0[0x8]; 3336 u8 cqn[0x18]; 3337 3338 u8 reserved_at_20[0x20]; 3339 3340 u8 reserved_at_40[0x18]; 3341 u8 syndrome[0x8]; 3342 3343 u8 reserved_at_60[0x80]; 3344 }; 3345 3346 struct mlx5_ifc_rdma_page_fault_event_bits { 3347 u8 bytes_committed[0x20]; 3348 3349 u8 r_key[0x20]; 3350 3351 u8 reserved_at_40[0x10]; 3352 u8 packet_len[0x10]; 3353 3354 u8 rdma_op_len[0x20]; 3355 3356 u8 rdma_va[0x40]; 3357 3358 u8 reserved_at_c0[0x5]; 3359 u8 rdma[0x1]; 3360 u8 write[0x1]; 3361 u8 requestor[0x1]; 3362 u8 qp_number[0x18]; 3363 }; 3364 3365 struct mlx5_ifc_wqe_associated_page_fault_event_bits { 3366 u8 bytes_committed[0x20]; 3367 3368 u8 reserved_at_20[0x10]; 3369 u8 wqe_index[0x10]; 3370 3371 u8 reserved_at_40[0x10]; 3372 u8 len[0x10]; 3373 3374 u8 reserved_at_60[0x60]; 3375 3376 u8 reserved_at_c0[0x5]; 3377 u8 rdma[0x1]; 3378 u8 write_read[0x1]; 3379 u8 requestor[0x1]; 3380 u8 qpn[0x18]; 3381 }; 3382 3383 struct mlx5_ifc_qp_events_bits { 3384 u8 reserved_at_0[0xa0]; 3385 3386 u8 type[0x8]; 3387 u8 reserved_at_a8[0x18]; 3388 3389 u8 reserved_at_c0[0x8]; 3390 u8 qpn_rqn_sqn[0x18]; 3391 }; 3392 3393 struct mlx5_ifc_dct_events_bits { 3394 u8 reserved_at_0[0xc0]; 3395 3396 u8 reserved_at_c0[0x8]; 3397 u8 dct_number[0x18]; 3398 }; 3399 3400 struct mlx5_ifc_comp_event_bits { 3401 u8 reserved_at_0[0xc0]; 3402 3403 u8 reserved_at_c0[0x8]; 3404 u8 cq_number[0x18]; 3405 }; 3406 3407 enum { 3408 MLX5_QPC_STATE_RST = 0x0, 3409 MLX5_QPC_STATE_INIT = 0x1, 3410 MLX5_QPC_STATE_RTR = 0x2, 3411 MLX5_QPC_STATE_RTS = 0x3, 3412 MLX5_QPC_STATE_SQER = 0x4, 3413 MLX5_QPC_STATE_ERR = 0x6, 3414 MLX5_QPC_STATE_SQD = 0x7, 3415 MLX5_QPC_STATE_SUSPENDED = 0x9, 3416 }; 3417 3418 enum { 3419 MLX5_QPC_ST_RC = 0x0, 3420 MLX5_QPC_ST_UC = 0x1, 3421 MLX5_QPC_ST_UD = 0x2, 3422 MLX5_QPC_ST_XRC = 0x3, 3423 MLX5_QPC_ST_DCI = 0x5, 3424 MLX5_QPC_ST_QP0 = 0x7, 3425 MLX5_QPC_ST_QP1 = 0x8, 3426 MLX5_QPC_ST_RAW_DATAGRAM = 0x9, 3427 MLX5_QPC_ST_REG_UMR = 0xc, 3428 }; 3429 3430 enum { 3431 MLX5_QPC_PM_STATE_ARMED = 0x0, 3432 MLX5_QPC_PM_STATE_REARM = 0x1, 3433 MLX5_QPC_PM_STATE_RESERVED = 0x2, 3434 MLX5_QPC_PM_STATE_MIGRATED = 0x3, 3435 }; 3436 3437 enum { 3438 MLX5_QPC_OFFLOAD_TYPE_RNDV = 0x1, 3439 }; 3440 3441 enum { 3442 MLX5_QPC_END_PADDING_MODE_SCATTER_AS_IS = 0x0, 3443 MLX5_QPC_END_PADDING_MODE_PAD_TO_CACHE_LINE_ALIGNMENT = 0x1, 3444 }; 3445 3446 enum { 3447 MLX5_QPC_MTU_256_BYTES = 0x1, 3448 MLX5_QPC_MTU_512_BYTES = 0x2, 3449 MLX5_QPC_MTU_1K_BYTES = 0x3, 3450 MLX5_QPC_MTU_2K_BYTES = 0x4, 3451 MLX5_QPC_MTU_4K_BYTES = 0x5, 3452 MLX5_QPC_MTU_RAW_ETHERNET_QP = 0x7, 3453 }; 3454 3455 enum { 3456 MLX5_QPC_ATOMIC_MODE_IB_SPEC = 0x1, 3457 MLX5_QPC_ATOMIC_MODE_ONLY_8B = 0x2, 3458 MLX5_QPC_ATOMIC_MODE_UP_TO_8B = 0x3, 3459 MLX5_QPC_ATOMIC_MODE_UP_TO_16B = 0x4, 3460 MLX5_QPC_ATOMIC_MODE_UP_TO_32B = 0x5, 3461 MLX5_QPC_ATOMIC_MODE_UP_TO_64B = 0x6, 3462 MLX5_QPC_ATOMIC_MODE_UP_TO_128B = 0x7, 3463 MLX5_QPC_ATOMIC_MODE_UP_TO_256B = 0x8, 3464 }; 3465 3466 enum { 3467 MLX5_QPC_CS_REQ_DISABLE = 0x0, 3468 MLX5_QPC_CS_REQ_UP_TO_32B = 0x11, 3469 MLX5_QPC_CS_REQ_UP_TO_64B = 0x22, 3470 }; 3471 3472 enum { 3473 MLX5_QPC_CS_RES_DISABLE = 0x0, 3474 MLX5_QPC_CS_RES_UP_TO_32B = 0x1, 3475 MLX5_QPC_CS_RES_UP_TO_64B = 0x2, 3476 }; 3477 3478 enum { 3479 MLX5_TIMESTAMP_FORMAT_FREE_RUNNING = 0x0, 3480 MLX5_TIMESTAMP_FORMAT_DEFAULT = 0x1, 3481 MLX5_TIMESTAMP_FORMAT_REAL_TIME = 0x2, 3482 }; 3483 3484 struct mlx5_ifc_qpc_bits { 3485 u8 state[0x4]; 3486 u8 lag_tx_port_affinity[0x4]; 3487 u8 st[0x8]; 3488 u8 reserved_at_10[0x2]; 3489 u8 isolate_vl_tc[0x1]; 3490 u8 pm_state[0x2]; 3491 u8 reserved_at_15[0x1]; 3492 u8 req_e2e_credit_mode[0x2]; 3493 u8 offload_type[0x4]; 3494 u8 end_padding_mode[0x2]; 3495 u8 reserved_at_1e[0x2]; 3496 3497 u8 wq_signature[0x1]; 3498 u8 block_lb_mc[0x1]; 3499 u8 atomic_like_write_en[0x1]; 3500 u8 latency_sensitive[0x1]; 3501 u8 reserved_at_24[0x1]; 3502 u8 drain_sigerr[0x1]; 3503 u8 reserved_at_26[0x2]; 3504 u8 pd[0x18]; 3505 3506 u8 mtu[0x3]; 3507 u8 log_msg_max[0x5]; 3508 u8 reserved_at_48[0x1]; 3509 u8 log_rq_size[0x4]; 3510 u8 log_rq_stride[0x3]; 3511 u8 no_sq[0x1]; 3512 u8 log_sq_size[0x4]; 3513 u8 reserved_at_55[0x1]; 3514 u8 retry_mode[0x2]; 3515 u8 ts_format[0x2]; 3516 u8 reserved_at_5a[0x1]; 3517 u8 rlky[0x1]; 3518 u8 ulp_stateless_offload_mode[0x4]; 3519 3520 u8 counter_set_id[0x8]; 3521 u8 uar_page[0x18]; 3522 3523 u8 reserved_at_80[0x8]; 3524 u8 user_index[0x18]; 3525 3526 u8 reserved_at_a0[0x3]; 3527 u8 log_page_size[0x5]; 3528 u8 remote_qpn[0x18]; 3529 3530 struct mlx5_ifc_ads_bits primary_address_path; 3531 3532 struct mlx5_ifc_ads_bits secondary_address_path; 3533 3534 u8 log_ack_req_freq[0x4]; 3535 u8 reserved_at_384[0x4]; 3536 u8 log_sra_max[0x3]; 3537 u8 reserved_at_38b[0x2]; 3538 u8 retry_count[0x3]; 3539 u8 rnr_retry[0x3]; 3540 u8 reserved_at_393[0x1]; 3541 u8 fre[0x1]; 3542 u8 cur_rnr_retry[0x3]; 3543 u8 cur_retry_count[0x3]; 3544 u8 reserved_at_39b[0x5]; 3545 3546 u8 reserved_at_3a0[0x20]; 3547 3548 u8 reserved_at_3c0[0x8]; 3549 u8 next_send_psn[0x18]; 3550 3551 u8 reserved_at_3e0[0x3]; 3552 u8 log_num_dci_stream_channels[0x5]; 3553 u8 cqn_snd[0x18]; 3554 3555 u8 reserved_at_400[0x3]; 3556 u8 log_num_dci_errored_streams[0x5]; 3557 u8 deth_sqpn[0x18]; 3558 3559 u8 reserved_at_420[0x20]; 3560 3561 u8 reserved_at_440[0x8]; 3562 u8 last_acked_psn[0x18]; 3563 3564 u8 reserved_at_460[0x8]; 3565 u8 ssn[0x18]; 3566 3567 u8 reserved_at_480[0x8]; 3568 u8 log_rra_max[0x3]; 3569 u8 reserved_at_48b[0x1]; 3570 u8 atomic_mode[0x4]; 3571 u8 rre[0x1]; 3572 u8 rwe[0x1]; 3573 u8 rae[0x1]; 3574 u8 reserved_at_493[0x1]; 3575 u8 page_offset[0x6]; 3576 u8 reserved_at_49a[0x3]; 3577 u8 cd_slave_receive[0x1]; 3578 u8 cd_slave_send[0x1]; 3579 u8 cd_master[0x1]; 3580 3581 u8 reserved_at_4a0[0x3]; 3582 u8 min_rnr_nak[0x5]; 3583 u8 next_rcv_psn[0x18]; 3584 3585 u8 reserved_at_4c0[0x8]; 3586 u8 xrcd[0x18]; 3587 3588 u8 reserved_at_4e0[0x8]; 3589 u8 cqn_rcv[0x18]; 3590 3591 u8 dbr_addr[0x40]; 3592 3593 u8 q_key[0x20]; 3594 3595 u8 reserved_at_560[0x5]; 3596 u8 rq_type[0x3]; 3597 u8 srqn_rmpn_xrqn[0x18]; 3598 3599 u8 reserved_at_580[0x8]; 3600 u8 rmsn[0x18]; 3601 3602 u8 hw_sq_wqebb_counter[0x10]; 3603 u8 sw_sq_wqebb_counter[0x10]; 3604 3605 u8 hw_rq_counter[0x20]; 3606 3607 u8 sw_rq_counter[0x20]; 3608 3609 u8 reserved_at_600[0x20]; 3610 3611 u8 reserved_at_620[0xf]; 3612 u8 cgs[0x1]; 3613 u8 cs_req[0x8]; 3614 u8 cs_res[0x8]; 3615 3616 u8 dc_access_key[0x40]; 3617 3618 u8 reserved_at_680[0x3]; 3619 u8 dbr_umem_valid[0x1]; 3620 3621 u8 reserved_at_684[0xbc]; 3622 }; 3623 3624 struct mlx5_ifc_roce_addr_layout_bits { 3625 u8 source_l3_address[16][0x8]; 3626 3627 u8 reserved_at_80[0x3]; 3628 u8 vlan_valid[0x1]; 3629 u8 vlan_id[0xc]; 3630 u8 source_mac_47_32[0x10]; 3631 3632 u8 source_mac_31_0[0x20]; 3633 3634 u8 reserved_at_c0[0x14]; 3635 u8 roce_l3_type[0x4]; 3636 u8 roce_version[0x8]; 3637 3638 u8 reserved_at_e0[0x20]; 3639 }; 3640 3641 struct mlx5_ifc_crypto_cap_bits { 3642 u8 reserved_at_0[0x3]; 3643 u8 synchronize_dek[0x1]; 3644 u8 int_kek_manual[0x1]; 3645 u8 int_kek_auto[0x1]; 3646 u8 reserved_at_6[0x1a]; 3647 3648 u8 reserved_at_20[0x3]; 3649 u8 log_dek_max_alloc[0x5]; 3650 u8 reserved_at_28[0x3]; 3651 u8 log_max_num_deks[0x5]; 3652 u8 reserved_at_30[0x10]; 3653 3654 u8 reserved_at_40[0x20]; 3655 3656 u8 reserved_at_60[0x3]; 3657 u8 log_dek_granularity[0x5]; 3658 u8 reserved_at_68[0x3]; 3659 u8 log_max_num_int_kek[0x5]; 3660 u8 sw_wrapped_dek[0x10]; 3661 3662 u8 reserved_at_80[0x780]; 3663 }; 3664 3665 union mlx5_ifc_hca_cap_union_bits { 3666 struct mlx5_ifc_cmd_hca_cap_bits cmd_hca_cap; 3667 struct mlx5_ifc_cmd_hca_cap_2_bits cmd_hca_cap_2; 3668 struct mlx5_ifc_odp_cap_bits odp_cap; 3669 struct mlx5_ifc_atomic_caps_bits atomic_caps; 3670 struct mlx5_ifc_roce_cap_bits roce_cap; 3671 struct mlx5_ifc_per_protocol_networking_offload_caps_bits per_protocol_networking_offload_caps; 3672 struct mlx5_ifc_flow_table_nic_cap_bits flow_table_nic_cap; 3673 struct mlx5_ifc_flow_table_eswitch_cap_bits flow_table_eswitch_cap; 3674 struct mlx5_ifc_wqe_based_flow_table_cap_bits wqe_based_flow_table_cap; 3675 struct mlx5_ifc_esw_cap_bits esw_cap; 3676 struct mlx5_ifc_e_switch_cap_bits e_switch_cap; 3677 struct mlx5_ifc_port_selection_cap_bits port_selection_cap; 3678 struct mlx5_ifc_qos_cap_bits qos_cap; 3679 struct mlx5_ifc_debug_cap_bits debug_cap; 3680 struct mlx5_ifc_fpga_cap_bits fpga_cap; 3681 struct mlx5_ifc_tls_cap_bits tls_cap; 3682 struct mlx5_ifc_device_mem_cap_bits device_mem_cap; 3683 struct mlx5_ifc_virtio_emulation_cap_bits virtio_emulation_cap; 3684 struct mlx5_ifc_macsec_cap_bits macsec_cap; 3685 struct mlx5_ifc_crypto_cap_bits crypto_cap; 3686 struct mlx5_ifc_ipsec_cap_bits ipsec_cap; 3687 u8 reserved_at_0[0x8000]; 3688 }; 3689 3690 enum { 3691 MLX5_FLOW_CONTEXT_ACTION_ALLOW = 0x1, 3692 MLX5_FLOW_CONTEXT_ACTION_DROP = 0x2, 3693 MLX5_FLOW_CONTEXT_ACTION_FWD_DEST = 0x4, 3694 MLX5_FLOW_CONTEXT_ACTION_COUNT = 0x8, 3695 MLX5_FLOW_CONTEXT_ACTION_PACKET_REFORMAT = 0x10, 3696 MLX5_FLOW_CONTEXT_ACTION_DECAP = 0x20, 3697 MLX5_FLOW_CONTEXT_ACTION_MOD_HDR = 0x40, 3698 MLX5_FLOW_CONTEXT_ACTION_VLAN_POP = 0x80, 3699 MLX5_FLOW_CONTEXT_ACTION_VLAN_PUSH = 0x100, 3700 MLX5_FLOW_CONTEXT_ACTION_VLAN_POP_2 = 0x400, 3701 MLX5_FLOW_CONTEXT_ACTION_VLAN_PUSH_2 = 0x800, 3702 MLX5_FLOW_CONTEXT_ACTION_CRYPTO_DECRYPT = 0x1000, 3703 MLX5_FLOW_CONTEXT_ACTION_CRYPTO_ENCRYPT = 0x2000, 3704 MLX5_FLOW_CONTEXT_ACTION_EXECUTE_ASO = 0x4000, 3705 }; 3706 3707 enum { 3708 MLX5_FLOW_CONTEXT_FLOW_SOURCE_ANY_VPORT = 0x0, 3709 MLX5_FLOW_CONTEXT_FLOW_SOURCE_UPLINK = 0x1, 3710 MLX5_FLOW_CONTEXT_FLOW_SOURCE_LOCAL_VPORT = 0x2, 3711 }; 3712 3713 enum { 3714 MLX5_FLOW_CONTEXT_ENCRYPT_DECRYPT_TYPE_IPSEC = 0x0, 3715 MLX5_FLOW_CONTEXT_ENCRYPT_DECRYPT_TYPE_MACSEC = 0x1, 3716 }; 3717 3718 struct mlx5_ifc_vlan_bits { 3719 u8 ethtype[0x10]; 3720 u8 prio[0x3]; 3721 u8 cfi[0x1]; 3722 u8 vid[0xc]; 3723 }; 3724 3725 enum { 3726 MLX5_FLOW_METER_COLOR_RED = 0x0, 3727 MLX5_FLOW_METER_COLOR_YELLOW = 0x1, 3728 MLX5_FLOW_METER_COLOR_GREEN = 0x2, 3729 MLX5_FLOW_METER_COLOR_UNDEFINED = 0x3, 3730 }; 3731 3732 enum { 3733 MLX5_EXE_ASO_FLOW_METER = 0x2, 3734 }; 3735 3736 struct mlx5_ifc_exe_aso_ctrl_flow_meter_bits { 3737 u8 return_reg_id[0x4]; 3738 u8 aso_type[0x4]; 3739 u8 reserved_at_8[0x14]; 3740 u8 action[0x1]; 3741 u8 init_color[0x2]; 3742 u8 meter_id[0x1]; 3743 }; 3744 3745 union mlx5_ifc_exe_aso_ctrl { 3746 struct mlx5_ifc_exe_aso_ctrl_flow_meter_bits exe_aso_ctrl_flow_meter; 3747 }; 3748 3749 struct mlx5_ifc_execute_aso_bits { 3750 u8 valid[0x1]; 3751 u8 reserved_at_1[0x7]; 3752 u8 aso_object_id[0x18]; 3753 3754 union mlx5_ifc_exe_aso_ctrl exe_aso_ctrl; 3755 }; 3756 3757 struct mlx5_ifc_flow_context_bits { 3758 struct mlx5_ifc_vlan_bits push_vlan; 3759 3760 u8 group_id[0x20]; 3761 3762 u8 reserved_at_40[0x8]; 3763 u8 flow_tag[0x18]; 3764 3765 u8 reserved_at_60[0x10]; 3766 u8 action[0x10]; 3767 3768 u8 extended_destination[0x1]; 3769 u8 uplink_hairpin_en[0x1]; 3770 u8 flow_source[0x2]; 3771 u8 encrypt_decrypt_type[0x4]; 3772 u8 destination_list_size[0x18]; 3773 3774 u8 reserved_at_a0[0x8]; 3775 u8 flow_counter_list_size[0x18]; 3776 3777 u8 packet_reformat_id[0x20]; 3778 3779 u8 modify_header_id[0x20]; 3780 3781 struct mlx5_ifc_vlan_bits push_vlan_2; 3782 3783 u8 encrypt_decrypt_obj_id[0x20]; 3784 u8 reserved_at_140[0xc0]; 3785 3786 struct mlx5_ifc_fte_match_param_bits match_value; 3787 3788 struct mlx5_ifc_execute_aso_bits execute_aso[4]; 3789 3790 u8 reserved_at_1300[0x500]; 3791 3792 union mlx5_ifc_dest_format_flow_counter_list_auto_bits destination[]; 3793 }; 3794 3795 enum { 3796 MLX5_XRC_SRQC_STATE_GOOD = 0x0, 3797 MLX5_XRC_SRQC_STATE_ERROR = 0x1, 3798 }; 3799 3800 struct mlx5_ifc_xrc_srqc_bits { 3801 u8 state[0x4]; 3802 u8 log_xrc_srq_size[0x4]; 3803 u8 reserved_at_8[0x18]; 3804 3805 u8 wq_signature[0x1]; 3806 u8 cont_srq[0x1]; 3807 u8 reserved_at_22[0x1]; 3808 u8 rlky[0x1]; 3809 u8 basic_cyclic_rcv_wqe[0x1]; 3810 u8 log_rq_stride[0x3]; 3811 u8 xrcd[0x18]; 3812 3813 u8 page_offset[0x6]; 3814 u8 reserved_at_46[0x1]; 3815 u8 dbr_umem_valid[0x1]; 3816 u8 cqn[0x18]; 3817 3818 u8 reserved_at_60[0x20]; 3819 3820 u8 user_index_equal_xrc_srqn[0x1]; 3821 u8 reserved_at_81[0x1]; 3822 u8 log_page_size[0x6]; 3823 u8 user_index[0x18]; 3824 3825 u8 reserved_at_a0[0x20]; 3826 3827 u8 reserved_at_c0[0x8]; 3828 u8 pd[0x18]; 3829 3830 u8 lwm[0x10]; 3831 u8 wqe_cnt[0x10]; 3832 3833 u8 reserved_at_100[0x40]; 3834 3835 u8 db_record_addr_h[0x20]; 3836 3837 u8 db_record_addr_l[0x1e]; 3838 u8 reserved_at_17e[0x2]; 3839 3840 u8 reserved_at_180[0x80]; 3841 }; 3842 3843 struct mlx5_ifc_vnic_diagnostic_statistics_bits { 3844 u8 counter_error_queues[0x20]; 3845 3846 u8 total_error_queues[0x20]; 3847 3848 u8 send_queue_priority_update_flow[0x20]; 3849 3850 u8 reserved_at_60[0x20]; 3851 3852 u8 nic_receive_steering_discard[0x40]; 3853 3854 u8 receive_discard_vport_down[0x40]; 3855 3856 u8 transmit_discard_vport_down[0x40]; 3857 3858 u8 async_eq_overrun[0x20]; 3859 3860 u8 comp_eq_overrun[0x20]; 3861 3862 u8 reserved_at_180[0x20]; 3863 3864 u8 invalid_command[0x20]; 3865 3866 u8 quota_exceeded_command[0x20]; 3867 3868 u8 internal_rq_out_of_buffer[0x20]; 3869 3870 u8 cq_overrun[0x20]; 3871 3872 u8 eth_wqe_too_small[0x20]; 3873 3874 u8 reserved_at_220[0xc0]; 3875 3876 u8 generated_pkt_steering_fail[0x40]; 3877 3878 u8 handled_pkt_steering_fail[0x40]; 3879 3880 u8 reserved_at_360[0xc80]; 3881 }; 3882 3883 struct mlx5_ifc_traffic_counter_bits { 3884 u8 packets[0x40]; 3885 3886 u8 octets[0x40]; 3887 }; 3888 3889 struct mlx5_ifc_tisc_bits { 3890 u8 strict_lag_tx_port_affinity[0x1]; 3891 u8 tls_en[0x1]; 3892 u8 reserved_at_2[0x2]; 3893 u8 lag_tx_port_affinity[0x04]; 3894 3895 u8 reserved_at_8[0x4]; 3896 u8 prio[0x4]; 3897 u8 reserved_at_10[0x10]; 3898 3899 u8 reserved_at_20[0x100]; 3900 3901 u8 reserved_at_120[0x8]; 3902 u8 transport_domain[0x18]; 3903 3904 u8 reserved_at_140[0x8]; 3905 u8 underlay_qpn[0x18]; 3906 3907 u8 reserved_at_160[0x8]; 3908 u8 pd[0x18]; 3909 3910 u8 reserved_at_180[0x380]; 3911 }; 3912 3913 enum { 3914 MLX5_TIRC_DISP_TYPE_DIRECT = 0x0, 3915 MLX5_TIRC_DISP_TYPE_INDIRECT = 0x1, 3916 }; 3917 3918 enum { 3919 MLX5_TIRC_PACKET_MERGE_MASK_IPV4_LRO = BIT(0), 3920 MLX5_TIRC_PACKET_MERGE_MASK_IPV6_LRO = BIT(1), 3921 }; 3922 3923 enum { 3924 MLX5_RX_HASH_FN_NONE = 0x0, 3925 MLX5_RX_HASH_FN_INVERTED_XOR8 = 0x1, 3926 MLX5_RX_HASH_FN_TOEPLITZ = 0x2, 3927 }; 3928 3929 enum { 3930 MLX5_TIRC_SELF_LB_BLOCK_BLOCK_UNICAST = 0x1, 3931 MLX5_TIRC_SELF_LB_BLOCK_BLOCK_MULTICAST = 0x2, 3932 }; 3933 3934 struct mlx5_ifc_tirc_bits { 3935 u8 reserved_at_0[0x20]; 3936 3937 u8 disp_type[0x4]; 3938 u8 tls_en[0x1]; 3939 u8 reserved_at_25[0x1b]; 3940 3941 u8 reserved_at_40[0x40]; 3942 3943 u8 reserved_at_80[0x4]; 3944 u8 lro_timeout_period_usecs[0x10]; 3945 u8 packet_merge_mask[0x4]; 3946 u8 lro_max_ip_payload_size[0x8]; 3947 3948 u8 reserved_at_a0[0x40]; 3949 3950 u8 reserved_at_e0[0x8]; 3951 u8 inline_rqn[0x18]; 3952 3953 u8 rx_hash_symmetric[0x1]; 3954 u8 reserved_at_101[0x1]; 3955 u8 tunneled_offload_en[0x1]; 3956 u8 reserved_at_103[0x5]; 3957 u8 indirect_table[0x18]; 3958 3959 u8 rx_hash_fn[0x4]; 3960 u8 reserved_at_124[0x2]; 3961 u8 self_lb_block[0x2]; 3962 u8 transport_domain[0x18]; 3963 3964 u8 rx_hash_toeplitz_key[10][0x20]; 3965 3966 struct mlx5_ifc_rx_hash_field_select_bits rx_hash_field_selector_outer; 3967 3968 struct mlx5_ifc_rx_hash_field_select_bits rx_hash_field_selector_inner; 3969 3970 u8 reserved_at_2c0[0x4c0]; 3971 }; 3972 3973 enum { 3974 MLX5_SRQC_STATE_GOOD = 0x0, 3975 MLX5_SRQC_STATE_ERROR = 0x1, 3976 }; 3977 3978 struct mlx5_ifc_srqc_bits { 3979 u8 state[0x4]; 3980 u8 log_srq_size[0x4]; 3981 u8 reserved_at_8[0x18]; 3982 3983 u8 wq_signature[0x1]; 3984 u8 cont_srq[0x1]; 3985 u8 reserved_at_22[0x1]; 3986 u8 rlky[0x1]; 3987 u8 reserved_at_24[0x1]; 3988 u8 log_rq_stride[0x3]; 3989 u8 xrcd[0x18]; 3990 3991 u8 page_offset[0x6]; 3992 u8 reserved_at_46[0x2]; 3993 u8 cqn[0x18]; 3994 3995 u8 reserved_at_60[0x20]; 3996 3997 u8 reserved_at_80[0x2]; 3998 u8 log_page_size[0x6]; 3999 u8 reserved_at_88[0x18]; 4000 4001 u8 reserved_at_a0[0x20]; 4002 4003 u8 reserved_at_c0[0x8]; 4004 u8 pd[0x18]; 4005 4006 u8 lwm[0x10]; 4007 u8 wqe_cnt[0x10]; 4008 4009 u8 reserved_at_100[0x40]; 4010 4011 u8 dbr_addr[0x40]; 4012 4013 u8 reserved_at_180[0x80]; 4014 }; 4015 4016 enum { 4017 MLX5_SQC_STATE_RST = 0x0, 4018 MLX5_SQC_STATE_RDY = 0x1, 4019 MLX5_SQC_STATE_ERR = 0x3, 4020 }; 4021 4022 struct mlx5_ifc_sqc_bits { 4023 u8 rlky[0x1]; 4024 u8 cd_master[0x1]; 4025 u8 fre[0x1]; 4026 u8 flush_in_error_en[0x1]; 4027 u8 allow_multi_pkt_send_wqe[0x1]; 4028 u8 min_wqe_inline_mode[0x3]; 4029 u8 state[0x4]; 4030 u8 reg_umr[0x1]; 4031 u8 allow_swp[0x1]; 4032 u8 hairpin[0x1]; 4033 u8 non_wire[0x1]; 4034 u8 reserved_at_10[0xa]; 4035 u8 ts_format[0x2]; 4036 u8 reserved_at_1c[0x4]; 4037 4038 u8 reserved_at_20[0x8]; 4039 u8 user_index[0x18]; 4040 4041 u8 reserved_at_40[0x8]; 4042 u8 cqn[0x18]; 4043 4044 u8 reserved_at_60[0x8]; 4045 u8 hairpin_peer_rq[0x18]; 4046 4047 u8 reserved_at_80[0x10]; 4048 u8 hairpin_peer_vhca[0x10]; 4049 4050 u8 reserved_at_a0[0x20]; 4051 4052 u8 reserved_at_c0[0x8]; 4053 u8 ts_cqe_to_dest_cqn[0x18]; 4054 4055 u8 reserved_at_e0[0x10]; 4056 u8 packet_pacing_rate_limit_index[0x10]; 4057 u8 tis_lst_sz[0x10]; 4058 u8 qos_queue_group_id[0x10]; 4059 4060 u8 reserved_at_120[0x40]; 4061 4062 u8 reserved_at_160[0x8]; 4063 u8 tis_num_0[0x18]; 4064 4065 struct mlx5_ifc_wq_bits wq; 4066 }; 4067 4068 enum { 4069 SCHEDULING_CONTEXT_ELEMENT_TYPE_TSAR = 0x0, 4070 SCHEDULING_CONTEXT_ELEMENT_TYPE_VPORT = 0x1, 4071 SCHEDULING_CONTEXT_ELEMENT_TYPE_VPORT_TC = 0x2, 4072 SCHEDULING_CONTEXT_ELEMENT_TYPE_PARA_VPORT_TC = 0x3, 4073 SCHEDULING_CONTEXT_ELEMENT_TYPE_QUEUE_GROUP = 0x4, 4074 }; 4075 4076 enum { 4077 ELEMENT_TYPE_CAP_MASK_TSAR = 1 << 0, 4078 ELEMENT_TYPE_CAP_MASK_VPORT = 1 << 1, 4079 ELEMENT_TYPE_CAP_MASK_VPORT_TC = 1 << 2, 4080 ELEMENT_TYPE_CAP_MASK_PARA_VPORT_TC = 1 << 3, 4081 ELEMENT_TYPE_CAP_MASK_QUEUE_GROUP = 1 << 4, 4082 }; 4083 4084 struct mlx5_ifc_scheduling_context_bits { 4085 u8 element_type[0x8]; 4086 u8 reserved_at_8[0x18]; 4087 4088 u8 element_attributes[0x20]; 4089 4090 u8 parent_element_id[0x20]; 4091 4092 u8 reserved_at_60[0x40]; 4093 4094 u8 bw_share[0x20]; 4095 4096 u8 max_average_bw[0x20]; 4097 4098 u8 reserved_at_e0[0x120]; 4099 }; 4100 4101 struct mlx5_ifc_rqtc_bits { 4102 u8 reserved_at_0[0xa0]; 4103 4104 u8 reserved_at_a0[0x5]; 4105 u8 list_q_type[0x3]; 4106 u8 reserved_at_a8[0x8]; 4107 u8 rqt_max_size[0x10]; 4108 4109 u8 rq_vhca_id_format[0x1]; 4110 u8 reserved_at_c1[0xf]; 4111 u8 rqt_actual_size[0x10]; 4112 4113 u8 reserved_at_e0[0x6a0]; 4114 4115 union { 4116 DECLARE_FLEX_ARRAY(struct mlx5_ifc_rq_num_bits, rq_num); 4117 DECLARE_FLEX_ARRAY(struct mlx5_ifc_rq_vhca_bits, rq_vhca); 4118 }; 4119 }; 4120 4121 enum { 4122 MLX5_RQC_MEM_RQ_TYPE_MEMORY_RQ_INLINE = 0x0, 4123 MLX5_RQC_MEM_RQ_TYPE_MEMORY_RQ_RMP = 0x1, 4124 }; 4125 4126 enum { 4127 MLX5_RQC_STATE_RST = 0x0, 4128 MLX5_RQC_STATE_RDY = 0x1, 4129 MLX5_RQC_STATE_ERR = 0x3, 4130 }; 4131 4132 enum { 4133 MLX5_RQC_SHAMPO_NO_MATCH_ALIGNMENT_GRANULARITY_BYTE = 0x0, 4134 MLX5_RQC_SHAMPO_NO_MATCH_ALIGNMENT_GRANULARITY_STRIDE = 0x1, 4135 MLX5_RQC_SHAMPO_NO_MATCH_ALIGNMENT_GRANULARITY_PAGE = 0x2, 4136 }; 4137 4138 enum { 4139 MLX5_RQC_SHAMPO_MATCH_CRITERIA_TYPE_NO_MATCH = 0x0, 4140 MLX5_RQC_SHAMPO_MATCH_CRITERIA_TYPE_EXTENDED = 0x1, 4141 MLX5_RQC_SHAMPO_MATCH_CRITERIA_TYPE_FIVE_TUPLE = 0x2, 4142 }; 4143 4144 struct mlx5_ifc_rqc_bits { 4145 u8 rlky[0x1]; 4146 u8 delay_drop_en[0x1]; 4147 u8 scatter_fcs[0x1]; 4148 u8 vsd[0x1]; 4149 u8 mem_rq_type[0x4]; 4150 u8 state[0x4]; 4151 u8 reserved_at_c[0x1]; 4152 u8 flush_in_error_en[0x1]; 4153 u8 hairpin[0x1]; 4154 u8 reserved_at_f[0xb]; 4155 u8 ts_format[0x2]; 4156 u8 reserved_at_1c[0x4]; 4157 4158 u8 reserved_at_20[0x8]; 4159 u8 user_index[0x18]; 4160 4161 u8 reserved_at_40[0x8]; 4162 u8 cqn[0x18]; 4163 4164 u8 counter_set_id[0x8]; 4165 u8 reserved_at_68[0x18]; 4166 4167 u8 reserved_at_80[0x8]; 4168 u8 rmpn[0x18]; 4169 4170 u8 reserved_at_a0[0x8]; 4171 u8 hairpin_peer_sq[0x18]; 4172 4173 u8 reserved_at_c0[0x10]; 4174 u8 hairpin_peer_vhca[0x10]; 4175 4176 u8 reserved_at_e0[0x46]; 4177 u8 shampo_no_match_alignment_granularity[0x2]; 4178 u8 reserved_at_128[0x6]; 4179 u8 shampo_match_criteria_type[0x2]; 4180 u8 reservation_timeout[0x10]; 4181 4182 u8 reserved_at_140[0x40]; 4183 4184 struct mlx5_ifc_wq_bits wq; 4185 }; 4186 4187 enum { 4188 MLX5_RMPC_STATE_RDY = 0x1, 4189 MLX5_RMPC_STATE_ERR = 0x3, 4190 }; 4191 4192 struct mlx5_ifc_rmpc_bits { 4193 u8 reserved_at_0[0x8]; 4194 u8 state[0x4]; 4195 u8 reserved_at_c[0x14]; 4196 4197 u8 basic_cyclic_rcv_wqe[0x1]; 4198 u8 reserved_at_21[0x1f]; 4199 4200 u8 reserved_at_40[0x140]; 4201 4202 struct mlx5_ifc_wq_bits wq; 4203 }; 4204 4205 enum { 4206 VHCA_ID_TYPE_HW = 0, 4207 VHCA_ID_TYPE_SW = 1, 4208 }; 4209 4210 struct mlx5_ifc_nic_vport_context_bits { 4211 u8 reserved_at_0[0x5]; 4212 u8 min_wqe_inline_mode[0x3]; 4213 u8 reserved_at_8[0x15]; 4214 u8 disable_mc_local_lb[0x1]; 4215 u8 disable_uc_local_lb[0x1]; 4216 u8 roce_en[0x1]; 4217 4218 u8 arm_change_event[0x1]; 4219 u8 reserved_at_21[0x1a]; 4220 u8 event_on_mtu[0x1]; 4221 u8 event_on_promisc_change[0x1]; 4222 u8 event_on_vlan_change[0x1]; 4223 u8 event_on_mc_address_change[0x1]; 4224 u8 event_on_uc_address_change[0x1]; 4225 4226 u8 vhca_id_type[0x1]; 4227 u8 reserved_at_41[0xb]; 4228 u8 affiliation_criteria[0x4]; 4229 u8 affiliated_vhca_id[0x10]; 4230 4231 u8 reserved_at_60[0xa0]; 4232 4233 u8 reserved_at_100[0x1]; 4234 u8 sd_group[0x3]; 4235 u8 reserved_at_104[0x1c]; 4236 4237 u8 reserved_at_120[0x10]; 4238 u8 mtu[0x10]; 4239 4240 u8 system_image_guid[0x40]; 4241 u8 port_guid[0x40]; 4242 u8 node_guid[0x40]; 4243 4244 u8 reserved_at_200[0x140]; 4245 u8 qkey_violation_counter[0x10]; 4246 u8 reserved_at_350[0x430]; 4247 4248 u8 promisc_uc[0x1]; 4249 u8 promisc_mc[0x1]; 4250 u8 promisc_all[0x1]; 4251 u8 reserved_at_783[0x2]; 4252 u8 allowed_list_type[0x3]; 4253 u8 reserved_at_788[0xc]; 4254 u8 allowed_list_size[0xc]; 4255 4256 struct mlx5_ifc_mac_address_layout_bits permanent_address; 4257 4258 u8 reserved_at_7e0[0x20]; 4259 4260 u8 current_uc_mac_address[][0x40]; 4261 }; 4262 4263 enum { 4264 MLX5_MKC_ACCESS_MODE_PA = 0x0, 4265 MLX5_MKC_ACCESS_MODE_MTT = 0x1, 4266 MLX5_MKC_ACCESS_MODE_KLMS = 0x2, 4267 MLX5_MKC_ACCESS_MODE_KSM = 0x3, 4268 MLX5_MKC_ACCESS_MODE_SW_ICM = 0x4, 4269 MLX5_MKC_ACCESS_MODE_MEMIC = 0x5, 4270 }; 4271 4272 struct mlx5_ifc_mkc_bits { 4273 u8 reserved_at_0[0x1]; 4274 u8 free[0x1]; 4275 u8 reserved_at_2[0x1]; 4276 u8 access_mode_4_2[0x3]; 4277 u8 reserved_at_6[0x7]; 4278 u8 relaxed_ordering_write[0x1]; 4279 u8 reserved_at_e[0x1]; 4280 u8 small_fence_on_rdma_read_response[0x1]; 4281 u8 umr_en[0x1]; 4282 u8 a[0x1]; 4283 u8 rw[0x1]; 4284 u8 rr[0x1]; 4285 u8 lw[0x1]; 4286 u8 lr[0x1]; 4287 u8 access_mode_1_0[0x2]; 4288 u8 reserved_at_18[0x2]; 4289 u8 ma_translation_mode[0x2]; 4290 u8 reserved_at_1c[0x4]; 4291 4292 u8 qpn[0x18]; 4293 u8 mkey_7_0[0x8]; 4294 4295 u8 reserved_at_40[0x20]; 4296 4297 u8 length64[0x1]; 4298 u8 bsf_en[0x1]; 4299 u8 sync_umr[0x1]; 4300 u8 reserved_at_63[0x2]; 4301 u8 expected_sigerr_count[0x1]; 4302 u8 reserved_at_66[0x1]; 4303 u8 en_rinval[0x1]; 4304 u8 pd[0x18]; 4305 4306 u8 start_addr[0x40]; 4307 4308 u8 len[0x40]; 4309 4310 u8 bsf_octword_size[0x20]; 4311 4312 u8 reserved_at_120[0x80]; 4313 4314 u8 translations_octword_size[0x20]; 4315 4316 u8 reserved_at_1c0[0x19]; 4317 u8 relaxed_ordering_read[0x1]; 4318 u8 reserved_at_1d9[0x1]; 4319 u8 log_page_size[0x5]; 4320 4321 u8 reserved_at_1e0[0x20]; 4322 }; 4323 4324 struct mlx5_ifc_pkey_bits { 4325 u8 reserved_at_0[0x10]; 4326 u8 pkey[0x10]; 4327 }; 4328 4329 struct mlx5_ifc_array128_auto_bits { 4330 u8 array128_auto[16][0x8]; 4331 }; 4332 4333 struct mlx5_ifc_hca_vport_context_bits { 4334 u8 field_select[0x20]; 4335 4336 u8 reserved_at_20[0xe0]; 4337 4338 u8 sm_virt_aware[0x1]; 4339 u8 has_smi[0x1]; 4340 u8 has_raw[0x1]; 4341 u8 grh_required[0x1]; 4342 u8 reserved_at_104[0x4]; 4343 u8 num_port_plane[0x8]; 4344 u8 port_physical_state[0x4]; 4345 u8 vport_state_policy[0x4]; 4346 u8 port_state[0x4]; 4347 u8 vport_state[0x4]; 4348 4349 u8 reserved_at_120[0x20]; 4350 4351 u8 system_image_guid[0x40]; 4352 4353 u8 port_guid[0x40]; 4354 4355 u8 node_guid[0x40]; 4356 4357 u8 cap_mask1[0x20]; 4358 4359 u8 cap_mask1_field_select[0x20]; 4360 4361 u8 cap_mask2[0x20]; 4362 4363 u8 cap_mask2_field_select[0x20]; 4364 4365 u8 reserved_at_280[0x80]; 4366 4367 u8 lid[0x10]; 4368 u8 reserved_at_310[0x4]; 4369 u8 init_type_reply[0x4]; 4370 u8 lmc[0x3]; 4371 u8 subnet_timeout[0x5]; 4372 4373 u8 sm_lid[0x10]; 4374 u8 sm_sl[0x4]; 4375 u8 reserved_at_334[0xc]; 4376 4377 u8 qkey_violation_counter[0x10]; 4378 u8 pkey_violation_counter[0x10]; 4379 4380 u8 reserved_at_360[0xca0]; 4381 }; 4382 4383 struct mlx5_ifc_esw_vport_context_bits { 4384 u8 fdb_to_vport_reg_c[0x1]; 4385 u8 reserved_at_1[0x2]; 4386 u8 vport_svlan_strip[0x1]; 4387 u8 vport_cvlan_strip[0x1]; 4388 u8 vport_svlan_insert[0x1]; 4389 u8 vport_cvlan_insert[0x2]; 4390 u8 fdb_to_vport_reg_c_id[0x8]; 4391 u8 reserved_at_10[0x10]; 4392 4393 u8 reserved_at_20[0x20]; 4394 4395 u8 svlan_cfi[0x1]; 4396 u8 svlan_pcp[0x3]; 4397 u8 svlan_id[0xc]; 4398 u8 cvlan_cfi[0x1]; 4399 u8 cvlan_pcp[0x3]; 4400 u8 cvlan_id[0xc]; 4401 4402 u8 reserved_at_60[0x720]; 4403 4404 u8 sw_steering_vport_icm_address_rx[0x40]; 4405 4406 u8 sw_steering_vport_icm_address_tx[0x40]; 4407 }; 4408 4409 enum { 4410 MLX5_EQC_STATUS_OK = 0x0, 4411 MLX5_EQC_STATUS_EQ_WRITE_FAILURE = 0xa, 4412 }; 4413 4414 enum { 4415 MLX5_EQC_ST_ARMED = 0x9, 4416 MLX5_EQC_ST_FIRED = 0xa, 4417 }; 4418 4419 struct mlx5_ifc_eqc_bits { 4420 u8 status[0x4]; 4421 u8 reserved_at_4[0x9]; 4422 u8 ec[0x1]; 4423 u8 oi[0x1]; 4424 u8 reserved_at_f[0x5]; 4425 u8 st[0x4]; 4426 u8 reserved_at_18[0x8]; 4427 4428 u8 reserved_at_20[0x20]; 4429 4430 u8 reserved_at_40[0x14]; 4431 u8 page_offset[0x6]; 4432 u8 reserved_at_5a[0x6]; 4433 4434 u8 reserved_at_60[0x3]; 4435 u8 log_eq_size[0x5]; 4436 u8 uar_page[0x18]; 4437 4438 u8 reserved_at_80[0x20]; 4439 4440 u8 reserved_at_a0[0x14]; 4441 u8 intr[0xc]; 4442 4443 u8 reserved_at_c0[0x3]; 4444 u8 log_page_size[0x5]; 4445 u8 reserved_at_c8[0x18]; 4446 4447 u8 reserved_at_e0[0x60]; 4448 4449 u8 reserved_at_140[0x8]; 4450 u8 consumer_counter[0x18]; 4451 4452 u8 reserved_at_160[0x8]; 4453 u8 producer_counter[0x18]; 4454 4455 u8 reserved_at_180[0x80]; 4456 }; 4457 4458 enum { 4459 MLX5_DCTC_STATE_ACTIVE = 0x0, 4460 MLX5_DCTC_STATE_DRAINING = 0x1, 4461 MLX5_DCTC_STATE_DRAINED = 0x2, 4462 }; 4463 4464 enum { 4465 MLX5_DCTC_CS_RES_DISABLE = 0x0, 4466 MLX5_DCTC_CS_RES_NA = 0x1, 4467 MLX5_DCTC_CS_RES_UP_TO_64B = 0x2, 4468 }; 4469 4470 enum { 4471 MLX5_DCTC_MTU_256_BYTES = 0x1, 4472 MLX5_DCTC_MTU_512_BYTES = 0x2, 4473 MLX5_DCTC_MTU_1K_BYTES = 0x3, 4474 MLX5_DCTC_MTU_2K_BYTES = 0x4, 4475 MLX5_DCTC_MTU_4K_BYTES = 0x5, 4476 }; 4477 4478 struct mlx5_ifc_dctc_bits { 4479 u8 reserved_at_0[0x4]; 4480 u8 state[0x4]; 4481 u8 reserved_at_8[0x18]; 4482 4483 u8 reserved_at_20[0x8]; 4484 u8 user_index[0x18]; 4485 4486 u8 reserved_at_40[0x8]; 4487 u8 cqn[0x18]; 4488 4489 u8 counter_set_id[0x8]; 4490 u8 atomic_mode[0x4]; 4491 u8 rre[0x1]; 4492 u8 rwe[0x1]; 4493 u8 rae[0x1]; 4494 u8 atomic_like_write_en[0x1]; 4495 u8 latency_sensitive[0x1]; 4496 u8 rlky[0x1]; 4497 u8 free_ar[0x1]; 4498 u8 reserved_at_73[0xd]; 4499 4500 u8 reserved_at_80[0x8]; 4501 u8 cs_res[0x8]; 4502 u8 reserved_at_90[0x3]; 4503 u8 min_rnr_nak[0x5]; 4504 u8 reserved_at_98[0x8]; 4505 4506 u8 reserved_at_a0[0x8]; 4507 u8 srqn_xrqn[0x18]; 4508 4509 u8 reserved_at_c0[0x8]; 4510 u8 pd[0x18]; 4511 4512 u8 tclass[0x8]; 4513 u8 reserved_at_e8[0x4]; 4514 u8 flow_label[0x14]; 4515 4516 u8 dc_access_key[0x40]; 4517 4518 u8 reserved_at_140[0x5]; 4519 u8 mtu[0x3]; 4520 u8 port[0x8]; 4521 u8 pkey_index[0x10]; 4522 4523 u8 reserved_at_160[0x8]; 4524 u8 my_addr_index[0x8]; 4525 u8 reserved_at_170[0x8]; 4526 u8 hop_limit[0x8]; 4527 4528 u8 dc_access_key_violation_count[0x20]; 4529 4530 u8 reserved_at_1a0[0x14]; 4531 u8 dei_cfi[0x1]; 4532 u8 eth_prio[0x3]; 4533 u8 ecn[0x2]; 4534 u8 dscp[0x6]; 4535 4536 u8 reserved_at_1c0[0x20]; 4537 u8 ece[0x20]; 4538 }; 4539 4540 enum { 4541 MLX5_CQC_STATUS_OK = 0x0, 4542 MLX5_CQC_STATUS_CQ_OVERFLOW = 0x9, 4543 MLX5_CQC_STATUS_CQ_WRITE_FAIL = 0xa, 4544 }; 4545 4546 enum { 4547 MLX5_CQC_CQE_SZ_64_BYTES = 0x0, 4548 MLX5_CQC_CQE_SZ_128_BYTES = 0x1, 4549 }; 4550 4551 enum { 4552 MLX5_CQC_ST_SOLICITED_NOTIFICATION_REQUEST_ARMED = 0x6, 4553 MLX5_CQC_ST_NOTIFICATION_REQUEST_ARMED = 0x9, 4554 MLX5_CQC_ST_FIRED = 0xa, 4555 }; 4556 4557 enum mlx5_cq_period_mode { 4558 MLX5_CQ_PERIOD_MODE_START_FROM_EQE = 0x0, 4559 MLX5_CQ_PERIOD_MODE_START_FROM_CQE = 0x1, 4560 MLX5_CQ_PERIOD_NUM_MODES, 4561 }; 4562 4563 struct mlx5_ifc_cqc_bits { 4564 u8 status[0x4]; 4565 u8 reserved_at_4[0x2]; 4566 u8 dbr_umem_valid[0x1]; 4567 u8 apu_cq[0x1]; 4568 u8 cqe_sz[0x3]; 4569 u8 cc[0x1]; 4570 u8 reserved_at_c[0x1]; 4571 u8 scqe_break_moderation_en[0x1]; 4572 u8 oi[0x1]; 4573 u8 cq_period_mode[0x2]; 4574 u8 cqe_comp_en[0x1]; 4575 u8 mini_cqe_res_format[0x2]; 4576 u8 st[0x4]; 4577 u8 reserved_at_18[0x6]; 4578 u8 cqe_compression_layout[0x2]; 4579 4580 u8 reserved_at_20[0x20]; 4581 4582 u8 reserved_at_40[0x14]; 4583 u8 page_offset[0x6]; 4584 u8 reserved_at_5a[0x6]; 4585 4586 u8 reserved_at_60[0x3]; 4587 u8 log_cq_size[0x5]; 4588 u8 uar_page[0x18]; 4589 4590 u8 reserved_at_80[0x4]; 4591 u8 cq_period[0xc]; 4592 u8 cq_max_count[0x10]; 4593 4594 u8 c_eqn_or_apu_element[0x20]; 4595 4596 u8 reserved_at_c0[0x3]; 4597 u8 log_page_size[0x5]; 4598 u8 reserved_at_c8[0x18]; 4599 4600 u8 reserved_at_e0[0x20]; 4601 4602 u8 reserved_at_100[0x8]; 4603 u8 last_notified_index[0x18]; 4604 4605 u8 reserved_at_120[0x8]; 4606 u8 last_solicit_index[0x18]; 4607 4608 u8 reserved_at_140[0x8]; 4609 u8 consumer_counter[0x18]; 4610 4611 u8 reserved_at_160[0x8]; 4612 u8 producer_counter[0x18]; 4613 4614 u8 reserved_at_180[0x40]; 4615 4616 u8 dbr_addr[0x40]; 4617 }; 4618 4619 union mlx5_ifc_cong_control_roce_ecn_auto_bits { 4620 struct mlx5_ifc_cong_control_802_1qau_rp_bits cong_control_802_1qau_rp; 4621 struct mlx5_ifc_cong_control_r_roce_ecn_rp_bits cong_control_r_roce_ecn_rp; 4622 struct mlx5_ifc_cong_control_r_roce_ecn_np_bits cong_control_r_roce_ecn_np; 4623 struct mlx5_ifc_cong_control_r_roce_general_bits cong_control_r_roce_general; 4624 u8 reserved_at_0[0x800]; 4625 }; 4626 4627 struct mlx5_ifc_query_adapter_param_block_bits { 4628 u8 reserved_at_0[0xc0]; 4629 4630 u8 reserved_at_c0[0x8]; 4631 u8 ieee_vendor_id[0x18]; 4632 4633 u8 reserved_at_e0[0x10]; 4634 u8 vsd_vendor_id[0x10]; 4635 4636 u8 vsd[208][0x8]; 4637 4638 u8 vsd_contd_psid[16][0x8]; 4639 }; 4640 4641 enum { 4642 MLX5_XRQC_STATE_GOOD = 0x0, 4643 MLX5_XRQC_STATE_ERROR = 0x1, 4644 }; 4645 4646 enum { 4647 MLX5_XRQC_TOPOLOGY_NO_SPECIAL_TOPOLOGY = 0x0, 4648 MLX5_XRQC_TOPOLOGY_TAG_MATCHING = 0x1, 4649 }; 4650 4651 enum { 4652 MLX5_XRQC_OFFLOAD_RNDV = 0x1, 4653 }; 4654 4655 struct mlx5_ifc_tag_matching_topology_context_bits { 4656 u8 log_matching_list_sz[0x4]; 4657 u8 reserved_at_4[0xc]; 4658 u8 append_next_index[0x10]; 4659 4660 u8 sw_phase_cnt[0x10]; 4661 u8 hw_phase_cnt[0x10]; 4662 4663 u8 reserved_at_40[0x40]; 4664 }; 4665 4666 struct mlx5_ifc_xrqc_bits { 4667 u8 state[0x4]; 4668 u8 rlkey[0x1]; 4669 u8 reserved_at_5[0xf]; 4670 u8 topology[0x4]; 4671 u8 reserved_at_18[0x4]; 4672 u8 offload[0x4]; 4673 4674 u8 reserved_at_20[0x8]; 4675 u8 user_index[0x18]; 4676 4677 u8 reserved_at_40[0x8]; 4678 u8 cqn[0x18]; 4679 4680 u8 reserved_at_60[0xa0]; 4681 4682 struct mlx5_ifc_tag_matching_topology_context_bits tag_matching_topology_context; 4683 4684 u8 reserved_at_180[0x280]; 4685 4686 struct mlx5_ifc_wq_bits wq; 4687 }; 4688 4689 union mlx5_ifc_modify_field_select_resize_field_select_auto_bits { 4690 struct mlx5_ifc_modify_field_select_bits modify_field_select; 4691 struct mlx5_ifc_resize_field_select_bits resize_field_select; 4692 u8 reserved_at_0[0x20]; 4693 }; 4694 4695 union mlx5_ifc_field_select_802_1_r_roce_auto_bits { 4696 struct mlx5_ifc_field_select_802_1qau_rp_bits field_select_802_1qau_rp; 4697 struct mlx5_ifc_field_select_r_roce_rp_bits field_select_r_roce_rp; 4698 struct mlx5_ifc_field_select_r_roce_np_bits field_select_r_roce_np; 4699 u8 reserved_at_0[0x20]; 4700 }; 4701 4702 union mlx5_ifc_eth_cntrs_grp_data_layout_auto_bits { 4703 struct mlx5_ifc_eth_802_3_cntrs_grp_data_layout_bits eth_802_3_cntrs_grp_data_layout; 4704 struct mlx5_ifc_eth_2863_cntrs_grp_data_layout_bits eth_2863_cntrs_grp_data_layout; 4705 struct mlx5_ifc_eth_2819_cntrs_grp_data_layout_bits eth_2819_cntrs_grp_data_layout; 4706 struct mlx5_ifc_eth_3635_cntrs_grp_data_layout_bits eth_3635_cntrs_grp_data_layout; 4707 struct mlx5_ifc_eth_extended_cntrs_grp_data_layout_bits eth_extended_cntrs_grp_data_layout; 4708 struct mlx5_ifc_eth_per_prio_grp_data_layout_bits eth_per_prio_grp_data_layout; 4709 struct mlx5_ifc_eth_per_tc_prio_grp_data_layout_bits eth_per_tc_prio_grp_data_layout; 4710 struct mlx5_ifc_eth_per_tc_congest_prio_grp_data_layout_bits eth_per_tc_congest_prio_grp_data_layout; 4711 struct mlx5_ifc_ib_port_cntrs_grp_data_layout_bits ib_port_cntrs_grp_data_layout; 4712 struct mlx5_ifc_ib_ext_port_cntrs_grp_data_layout_bits ib_ext_port_cntrs_grp_data_layout; 4713 struct mlx5_ifc_phys_layer_cntrs_bits phys_layer_cntrs; 4714 struct mlx5_ifc_phys_layer_statistical_cntrs_bits phys_layer_statistical_cntrs; 4715 u8 reserved_at_0[0x7c0]; 4716 }; 4717 4718 union mlx5_ifc_pcie_cntrs_grp_data_layout_auto_bits { 4719 struct mlx5_ifc_pcie_perf_cntrs_grp_data_layout_bits pcie_perf_cntrs_grp_data_layout; 4720 u8 reserved_at_0[0x7c0]; 4721 }; 4722 4723 union mlx5_ifc_event_auto_bits { 4724 struct mlx5_ifc_comp_event_bits comp_event; 4725 struct mlx5_ifc_dct_events_bits dct_events; 4726 struct mlx5_ifc_qp_events_bits qp_events; 4727 struct mlx5_ifc_wqe_associated_page_fault_event_bits wqe_associated_page_fault_event; 4728 struct mlx5_ifc_rdma_page_fault_event_bits rdma_page_fault_event; 4729 struct mlx5_ifc_cq_error_bits cq_error; 4730 struct mlx5_ifc_dropped_packet_logged_bits dropped_packet_logged; 4731 struct mlx5_ifc_port_state_change_event_bits port_state_change_event; 4732 struct mlx5_ifc_gpio_event_bits gpio_event; 4733 struct mlx5_ifc_db_bf_congestion_event_bits db_bf_congestion_event; 4734 struct mlx5_ifc_stall_vl_event_bits stall_vl_event; 4735 struct mlx5_ifc_cmd_inter_comp_event_bits cmd_inter_comp_event; 4736 u8 reserved_at_0[0xe0]; 4737 }; 4738 4739 struct mlx5_ifc_health_buffer_bits { 4740 u8 reserved_at_0[0x100]; 4741 4742 u8 assert_existptr[0x20]; 4743 4744 u8 assert_callra[0x20]; 4745 4746 u8 reserved_at_140[0x20]; 4747 4748 u8 time[0x20]; 4749 4750 u8 fw_version[0x20]; 4751 4752 u8 hw_id[0x20]; 4753 4754 u8 rfr[0x1]; 4755 u8 reserved_at_1c1[0x3]; 4756 u8 valid[0x1]; 4757 u8 severity[0x3]; 4758 u8 reserved_at_1c8[0x18]; 4759 4760 u8 irisc_index[0x8]; 4761 u8 synd[0x8]; 4762 u8 ext_synd[0x10]; 4763 }; 4764 4765 struct mlx5_ifc_register_loopback_control_bits { 4766 u8 no_lb[0x1]; 4767 u8 reserved_at_1[0x7]; 4768 u8 port[0x8]; 4769 u8 reserved_at_10[0x10]; 4770 4771 u8 reserved_at_20[0x60]; 4772 }; 4773 4774 struct mlx5_ifc_vport_tc_element_bits { 4775 u8 traffic_class[0x4]; 4776 u8 reserved_at_4[0xc]; 4777 u8 vport_number[0x10]; 4778 }; 4779 4780 struct mlx5_ifc_vport_element_bits { 4781 u8 reserved_at_0[0x10]; 4782 u8 vport_number[0x10]; 4783 }; 4784 4785 enum { 4786 TSAR_ELEMENT_TSAR_TYPE_DWRR = 0x0, 4787 TSAR_ELEMENT_TSAR_TYPE_ROUND_ROBIN = 0x1, 4788 TSAR_ELEMENT_TSAR_TYPE_ETS = 0x2, 4789 }; 4790 4791 enum { 4792 TSAR_TYPE_CAP_MASK_DWRR = 1 << 0, 4793 TSAR_TYPE_CAP_MASK_ROUND_ROBIN = 1 << 1, 4794 TSAR_TYPE_CAP_MASK_ETS = 1 << 2, 4795 }; 4796 4797 struct mlx5_ifc_tsar_element_bits { 4798 u8 reserved_at_0[0x8]; 4799 u8 tsar_type[0x8]; 4800 u8 reserved_at_10[0x10]; 4801 }; 4802 4803 enum { 4804 MLX5_TEARDOWN_HCA_OUT_FORCE_STATE_SUCCESS = 0x0, 4805 MLX5_TEARDOWN_HCA_OUT_FORCE_STATE_FAIL = 0x1, 4806 }; 4807 4808 struct mlx5_ifc_teardown_hca_out_bits { 4809 u8 status[0x8]; 4810 u8 reserved_at_8[0x18]; 4811 4812 u8 syndrome[0x20]; 4813 4814 u8 reserved_at_40[0x3f]; 4815 4816 u8 state[0x1]; 4817 }; 4818 4819 enum { 4820 MLX5_TEARDOWN_HCA_IN_PROFILE_GRACEFUL_CLOSE = 0x0, 4821 MLX5_TEARDOWN_HCA_IN_PROFILE_FORCE_CLOSE = 0x1, 4822 MLX5_TEARDOWN_HCA_IN_PROFILE_PREPARE_FAST_TEARDOWN = 0x2, 4823 }; 4824 4825 struct mlx5_ifc_teardown_hca_in_bits { 4826 u8 opcode[0x10]; 4827 u8 reserved_at_10[0x10]; 4828 4829 u8 reserved_at_20[0x10]; 4830 u8 op_mod[0x10]; 4831 4832 u8 reserved_at_40[0x10]; 4833 u8 profile[0x10]; 4834 4835 u8 reserved_at_60[0x20]; 4836 }; 4837 4838 struct mlx5_ifc_sqerr2rts_qp_out_bits { 4839 u8 status[0x8]; 4840 u8 reserved_at_8[0x18]; 4841 4842 u8 syndrome[0x20]; 4843 4844 u8 reserved_at_40[0x40]; 4845 }; 4846 4847 struct mlx5_ifc_sqerr2rts_qp_in_bits { 4848 u8 opcode[0x10]; 4849 u8 uid[0x10]; 4850 4851 u8 reserved_at_20[0x10]; 4852 u8 op_mod[0x10]; 4853 4854 u8 reserved_at_40[0x8]; 4855 u8 qpn[0x18]; 4856 4857 u8 reserved_at_60[0x20]; 4858 4859 u8 opt_param_mask[0x20]; 4860 4861 u8 reserved_at_a0[0x20]; 4862 4863 struct mlx5_ifc_qpc_bits qpc; 4864 4865 u8 reserved_at_800[0x80]; 4866 }; 4867 4868 struct mlx5_ifc_sqd2rts_qp_out_bits { 4869 u8 status[0x8]; 4870 u8 reserved_at_8[0x18]; 4871 4872 u8 syndrome[0x20]; 4873 4874 u8 reserved_at_40[0x40]; 4875 }; 4876 4877 struct mlx5_ifc_sqd2rts_qp_in_bits { 4878 u8 opcode[0x10]; 4879 u8 uid[0x10]; 4880 4881 u8 reserved_at_20[0x10]; 4882 u8 op_mod[0x10]; 4883 4884 u8 reserved_at_40[0x8]; 4885 u8 qpn[0x18]; 4886 4887 u8 reserved_at_60[0x20]; 4888 4889 u8 opt_param_mask[0x20]; 4890 4891 u8 reserved_at_a0[0x20]; 4892 4893 struct mlx5_ifc_qpc_bits qpc; 4894 4895 u8 reserved_at_800[0x80]; 4896 }; 4897 4898 struct mlx5_ifc_set_roce_address_out_bits { 4899 u8 status[0x8]; 4900 u8 reserved_at_8[0x18]; 4901 4902 u8 syndrome[0x20]; 4903 4904 u8 reserved_at_40[0x40]; 4905 }; 4906 4907 struct mlx5_ifc_set_roce_address_in_bits { 4908 u8 opcode[0x10]; 4909 u8 reserved_at_10[0x10]; 4910 4911 u8 reserved_at_20[0x10]; 4912 u8 op_mod[0x10]; 4913 4914 u8 roce_address_index[0x10]; 4915 u8 reserved_at_50[0xc]; 4916 u8 vhca_port_num[0x4]; 4917 4918 u8 reserved_at_60[0x20]; 4919 4920 struct mlx5_ifc_roce_addr_layout_bits roce_address; 4921 }; 4922 4923 struct mlx5_ifc_set_mad_demux_out_bits { 4924 u8 status[0x8]; 4925 u8 reserved_at_8[0x18]; 4926 4927 u8 syndrome[0x20]; 4928 4929 u8 reserved_at_40[0x40]; 4930 }; 4931 4932 enum { 4933 MLX5_SET_MAD_DEMUX_IN_DEMUX_MODE_PASS_ALL = 0x0, 4934 MLX5_SET_MAD_DEMUX_IN_DEMUX_MODE_SELECTIVE = 0x2, 4935 }; 4936 4937 struct mlx5_ifc_set_mad_demux_in_bits { 4938 u8 opcode[0x10]; 4939 u8 reserved_at_10[0x10]; 4940 4941 u8 reserved_at_20[0x10]; 4942 u8 op_mod[0x10]; 4943 4944 u8 reserved_at_40[0x20]; 4945 4946 u8 reserved_at_60[0x6]; 4947 u8 demux_mode[0x2]; 4948 u8 reserved_at_68[0x18]; 4949 }; 4950 4951 struct mlx5_ifc_set_l2_table_entry_out_bits { 4952 u8 status[0x8]; 4953 u8 reserved_at_8[0x18]; 4954 4955 u8 syndrome[0x20]; 4956 4957 u8 reserved_at_40[0x40]; 4958 }; 4959 4960 struct mlx5_ifc_set_l2_table_entry_in_bits { 4961 u8 opcode[0x10]; 4962 u8 reserved_at_10[0x10]; 4963 4964 u8 reserved_at_20[0x10]; 4965 u8 op_mod[0x10]; 4966 4967 u8 reserved_at_40[0x60]; 4968 4969 u8 reserved_at_a0[0x8]; 4970 u8 table_index[0x18]; 4971 4972 u8 reserved_at_c0[0x20]; 4973 4974 u8 reserved_at_e0[0x10]; 4975 u8 silent_mode_valid[0x1]; 4976 u8 silent_mode[0x1]; 4977 u8 reserved_at_f2[0x1]; 4978 u8 vlan_valid[0x1]; 4979 u8 vlan[0xc]; 4980 4981 struct mlx5_ifc_mac_address_layout_bits mac_address; 4982 4983 u8 reserved_at_140[0xc0]; 4984 }; 4985 4986 struct mlx5_ifc_set_issi_out_bits { 4987 u8 status[0x8]; 4988 u8 reserved_at_8[0x18]; 4989 4990 u8 syndrome[0x20]; 4991 4992 u8 reserved_at_40[0x40]; 4993 }; 4994 4995 struct mlx5_ifc_set_issi_in_bits { 4996 u8 opcode[0x10]; 4997 u8 reserved_at_10[0x10]; 4998 4999 u8 reserved_at_20[0x10]; 5000 u8 op_mod[0x10]; 5001 5002 u8 reserved_at_40[0x10]; 5003 u8 current_issi[0x10]; 5004 5005 u8 reserved_at_60[0x20]; 5006 }; 5007 5008 struct mlx5_ifc_set_hca_cap_out_bits { 5009 u8 status[0x8]; 5010 u8 reserved_at_8[0x18]; 5011 5012 u8 syndrome[0x20]; 5013 5014 u8 reserved_at_40[0x40]; 5015 }; 5016 5017 struct mlx5_ifc_set_hca_cap_in_bits { 5018 u8 opcode[0x10]; 5019 u8 reserved_at_10[0x10]; 5020 5021 u8 reserved_at_20[0x10]; 5022 u8 op_mod[0x10]; 5023 5024 u8 other_function[0x1]; 5025 u8 ec_vf_function[0x1]; 5026 u8 reserved_at_42[0xe]; 5027 u8 function_id[0x10]; 5028 5029 u8 reserved_at_60[0x20]; 5030 5031 union mlx5_ifc_hca_cap_union_bits capability; 5032 }; 5033 5034 enum { 5035 MLX5_SET_FTE_MODIFY_ENABLE_MASK_ACTION = 0x0, 5036 MLX5_SET_FTE_MODIFY_ENABLE_MASK_FLOW_TAG = 0x1, 5037 MLX5_SET_FTE_MODIFY_ENABLE_MASK_DESTINATION_LIST = 0x2, 5038 MLX5_SET_FTE_MODIFY_ENABLE_MASK_FLOW_COUNTERS = 0x3, 5039 MLX5_SET_FTE_MODIFY_ENABLE_MASK_IPSEC_OBJ_ID = 0x4 5040 }; 5041 5042 struct mlx5_ifc_set_fte_out_bits { 5043 u8 status[0x8]; 5044 u8 reserved_at_8[0x18]; 5045 5046 u8 syndrome[0x20]; 5047 5048 u8 reserved_at_40[0x40]; 5049 }; 5050 5051 struct mlx5_ifc_set_fte_in_bits { 5052 u8 opcode[0x10]; 5053 u8 reserved_at_10[0x10]; 5054 5055 u8 reserved_at_20[0x10]; 5056 u8 op_mod[0x10]; 5057 5058 u8 other_vport[0x1]; 5059 u8 reserved_at_41[0xf]; 5060 u8 vport_number[0x10]; 5061 5062 u8 reserved_at_60[0x20]; 5063 5064 u8 table_type[0x8]; 5065 u8 reserved_at_88[0x18]; 5066 5067 u8 reserved_at_a0[0x8]; 5068 u8 table_id[0x18]; 5069 5070 u8 ignore_flow_level[0x1]; 5071 u8 reserved_at_c1[0x17]; 5072 u8 modify_enable_mask[0x8]; 5073 5074 u8 reserved_at_e0[0x20]; 5075 5076 u8 flow_index[0x20]; 5077 5078 u8 reserved_at_120[0xe0]; 5079 5080 struct mlx5_ifc_flow_context_bits flow_context; 5081 }; 5082 5083 struct mlx5_ifc_dest_format_bits { 5084 u8 destination_type[0x8]; 5085 u8 destination_id[0x18]; 5086 5087 u8 destination_eswitch_owner_vhca_id_valid[0x1]; 5088 u8 packet_reformat[0x1]; 5089 u8 reserved_at_22[0xe]; 5090 u8 destination_eswitch_owner_vhca_id[0x10]; 5091 }; 5092 5093 struct mlx5_ifc_rts2rts_qp_out_bits { 5094 u8 status[0x8]; 5095 u8 reserved_at_8[0x18]; 5096 5097 u8 syndrome[0x20]; 5098 5099 u8 reserved_at_40[0x20]; 5100 u8 ece[0x20]; 5101 }; 5102 5103 struct mlx5_ifc_rts2rts_qp_in_bits { 5104 u8 opcode[0x10]; 5105 u8 uid[0x10]; 5106 5107 u8 reserved_at_20[0x10]; 5108 u8 op_mod[0x10]; 5109 5110 u8 reserved_at_40[0x8]; 5111 u8 qpn[0x18]; 5112 5113 u8 reserved_at_60[0x20]; 5114 5115 u8 opt_param_mask[0x20]; 5116 5117 u8 ece[0x20]; 5118 5119 struct mlx5_ifc_qpc_bits qpc; 5120 5121 u8 reserved_at_800[0x80]; 5122 }; 5123 5124 struct mlx5_ifc_rtr2rts_qp_out_bits { 5125 u8 status[0x8]; 5126 u8 reserved_at_8[0x18]; 5127 5128 u8 syndrome[0x20]; 5129 5130 u8 reserved_at_40[0x20]; 5131 u8 ece[0x20]; 5132 }; 5133 5134 struct mlx5_ifc_rtr2rts_qp_in_bits { 5135 u8 opcode[0x10]; 5136 u8 uid[0x10]; 5137 5138 u8 reserved_at_20[0x10]; 5139 u8 op_mod[0x10]; 5140 5141 u8 reserved_at_40[0x8]; 5142 u8 qpn[0x18]; 5143 5144 u8 reserved_at_60[0x20]; 5145 5146 u8 opt_param_mask[0x20]; 5147 5148 u8 ece[0x20]; 5149 5150 struct mlx5_ifc_qpc_bits qpc; 5151 5152 u8 reserved_at_800[0x80]; 5153 }; 5154 5155 struct mlx5_ifc_rst2init_qp_out_bits { 5156 u8 status[0x8]; 5157 u8 reserved_at_8[0x18]; 5158 5159 u8 syndrome[0x20]; 5160 5161 u8 reserved_at_40[0x20]; 5162 u8 ece[0x20]; 5163 }; 5164 5165 struct mlx5_ifc_rst2init_qp_in_bits { 5166 u8 opcode[0x10]; 5167 u8 uid[0x10]; 5168 5169 u8 reserved_at_20[0x10]; 5170 u8 op_mod[0x10]; 5171 5172 u8 reserved_at_40[0x8]; 5173 u8 qpn[0x18]; 5174 5175 u8 reserved_at_60[0x20]; 5176 5177 u8 opt_param_mask[0x20]; 5178 5179 u8 ece[0x20]; 5180 5181 struct mlx5_ifc_qpc_bits qpc; 5182 5183 u8 reserved_at_800[0x80]; 5184 }; 5185 5186 struct mlx5_ifc_query_xrq_out_bits { 5187 u8 status[0x8]; 5188 u8 reserved_at_8[0x18]; 5189 5190 u8 syndrome[0x20]; 5191 5192 u8 reserved_at_40[0x40]; 5193 5194 struct mlx5_ifc_xrqc_bits xrq_context; 5195 }; 5196 5197 struct mlx5_ifc_query_xrq_in_bits { 5198 u8 opcode[0x10]; 5199 u8 reserved_at_10[0x10]; 5200 5201 u8 reserved_at_20[0x10]; 5202 u8 op_mod[0x10]; 5203 5204 u8 reserved_at_40[0x8]; 5205 u8 xrqn[0x18]; 5206 5207 u8 reserved_at_60[0x20]; 5208 }; 5209 5210 struct mlx5_ifc_query_xrc_srq_out_bits { 5211 u8 status[0x8]; 5212 u8 reserved_at_8[0x18]; 5213 5214 u8 syndrome[0x20]; 5215 5216 u8 reserved_at_40[0x40]; 5217 5218 struct mlx5_ifc_xrc_srqc_bits xrc_srq_context_entry; 5219 5220 u8 reserved_at_280[0x600]; 5221 5222 u8 pas[][0x40]; 5223 }; 5224 5225 struct mlx5_ifc_query_xrc_srq_in_bits { 5226 u8 opcode[0x10]; 5227 u8 reserved_at_10[0x10]; 5228 5229 u8 reserved_at_20[0x10]; 5230 u8 op_mod[0x10]; 5231 5232 u8 reserved_at_40[0x8]; 5233 u8 xrc_srqn[0x18]; 5234 5235 u8 reserved_at_60[0x20]; 5236 }; 5237 5238 enum { 5239 MLX5_QUERY_VPORT_STATE_OUT_STATE_DOWN = 0x0, 5240 MLX5_QUERY_VPORT_STATE_OUT_STATE_UP = 0x1, 5241 }; 5242 5243 struct mlx5_ifc_query_vport_state_out_bits { 5244 u8 status[0x8]; 5245 u8 reserved_at_8[0x18]; 5246 5247 u8 syndrome[0x20]; 5248 5249 u8 reserved_at_40[0x20]; 5250 5251 u8 reserved_at_60[0x18]; 5252 u8 admin_state[0x4]; 5253 u8 state[0x4]; 5254 }; 5255 5256 enum { 5257 MLX5_VPORT_STATE_OP_MOD_VNIC_VPORT = 0x0, 5258 MLX5_VPORT_STATE_OP_MOD_ESW_VPORT = 0x1, 5259 MLX5_VPORT_STATE_OP_MOD_UPLINK = 0x2, 5260 }; 5261 5262 struct mlx5_ifc_arm_monitor_counter_in_bits { 5263 u8 opcode[0x10]; 5264 u8 uid[0x10]; 5265 5266 u8 reserved_at_20[0x10]; 5267 u8 op_mod[0x10]; 5268 5269 u8 reserved_at_40[0x20]; 5270 5271 u8 reserved_at_60[0x20]; 5272 }; 5273 5274 struct mlx5_ifc_arm_monitor_counter_out_bits { 5275 u8 status[0x8]; 5276 u8 reserved_at_8[0x18]; 5277 5278 u8 syndrome[0x20]; 5279 5280 u8 reserved_at_40[0x40]; 5281 }; 5282 5283 enum { 5284 MLX5_QUERY_MONITOR_CNT_TYPE_PPCNT = 0x0, 5285 MLX5_QUERY_MONITOR_CNT_TYPE_Q_COUNTER = 0x1, 5286 }; 5287 5288 enum mlx5_monitor_counter_ppcnt { 5289 MLX5_QUERY_MONITOR_PPCNT_IN_RANGE_LENGTH_ERRORS = 0x0, 5290 MLX5_QUERY_MONITOR_PPCNT_OUT_OF_RANGE_LENGTH_FIELD = 0x1, 5291 MLX5_QUERY_MONITOR_PPCNT_FRAME_TOO_LONG_ERRORS = 0x2, 5292 MLX5_QUERY_MONITOR_PPCNT_FRAME_CHECK_SEQUENCE_ERRORS = 0x3, 5293 MLX5_QUERY_MONITOR_PPCNT_ALIGNMENT_ERRORS = 0x4, 5294 MLX5_QUERY_MONITOR_PPCNT_IF_OUT_DISCARDS = 0x5, 5295 }; 5296 5297 enum { 5298 MLX5_QUERY_MONITOR_Q_COUNTER_RX_OUT_OF_BUFFER = 0x4, 5299 }; 5300 5301 struct mlx5_ifc_monitor_counter_output_bits { 5302 u8 reserved_at_0[0x4]; 5303 u8 type[0x4]; 5304 u8 reserved_at_8[0x8]; 5305 u8 counter[0x10]; 5306 5307 u8 counter_group_id[0x20]; 5308 }; 5309 5310 #define MLX5_CMD_SET_MONITOR_NUM_PPCNT_COUNTER_SET1 (6) 5311 #define MLX5_CMD_SET_MONITOR_NUM_Q_COUNTERS_SET1 (1) 5312 #define MLX5_CMD_SET_MONITOR_NUM_COUNTER (MLX5_CMD_SET_MONITOR_NUM_PPCNT_COUNTER_SET1 +\ 5313 MLX5_CMD_SET_MONITOR_NUM_Q_COUNTERS_SET1) 5314 5315 struct mlx5_ifc_set_monitor_counter_in_bits { 5316 u8 opcode[0x10]; 5317 u8 uid[0x10]; 5318 5319 u8 reserved_at_20[0x10]; 5320 u8 op_mod[0x10]; 5321 5322 u8 reserved_at_40[0x10]; 5323 u8 num_of_counters[0x10]; 5324 5325 u8 reserved_at_60[0x20]; 5326 5327 struct mlx5_ifc_monitor_counter_output_bits monitor_counter[MLX5_CMD_SET_MONITOR_NUM_COUNTER]; 5328 }; 5329 5330 struct mlx5_ifc_set_monitor_counter_out_bits { 5331 u8 status[0x8]; 5332 u8 reserved_at_8[0x18]; 5333 5334 u8 syndrome[0x20]; 5335 5336 u8 reserved_at_40[0x40]; 5337 }; 5338 5339 struct mlx5_ifc_query_vport_state_in_bits { 5340 u8 opcode[0x10]; 5341 u8 reserved_at_10[0x10]; 5342 5343 u8 reserved_at_20[0x10]; 5344 u8 op_mod[0x10]; 5345 5346 u8 other_vport[0x1]; 5347 u8 reserved_at_41[0xf]; 5348 u8 vport_number[0x10]; 5349 5350 u8 reserved_at_60[0x20]; 5351 }; 5352 5353 struct mlx5_ifc_query_vnic_env_out_bits { 5354 u8 status[0x8]; 5355 u8 reserved_at_8[0x18]; 5356 5357 u8 syndrome[0x20]; 5358 5359 u8 reserved_at_40[0x40]; 5360 5361 struct mlx5_ifc_vnic_diagnostic_statistics_bits vport_env; 5362 }; 5363 5364 enum { 5365 MLX5_QUERY_VNIC_ENV_IN_OP_MOD_VPORT_DIAG_STATISTICS = 0x0, 5366 }; 5367 5368 struct mlx5_ifc_query_vnic_env_in_bits { 5369 u8 opcode[0x10]; 5370 u8 reserved_at_10[0x10]; 5371 5372 u8 reserved_at_20[0x10]; 5373 u8 op_mod[0x10]; 5374 5375 u8 other_vport[0x1]; 5376 u8 reserved_at_41[0xf]; 5377 u8 vport_number[0x10]; 5378 5379 u8 reserved_at_60[0x20]; 5380 }; 5381 5382 struct mlx5_ifc_query_vport_counter_out_bits { 5383 u8 status[0x8]; 5384 u8 reserved_at_8[0x18]; 5385 5386 u8 syndrome[0x20]; 5387 5388 u8 reserved_at_40[0x40]; 5389 5390 struct mlx5_ifc_traffic_counter_bits received_errors; 5391 5392 struct mlx5_ifc_traffic_counter_bits transmit_errors; 5393 5394 struct mlx5_ifc_traffic_counter_bits received_ib_unicast; 5395 5396 struct mlx5_ifc_traffic_counter_bits transmitted_ib_unicast; 5397 5398 struct mlx5_ifc_traffic_counter_bits received_ib_multicast; 5399 5400 struct mlx5_ifc_traffic_counter_bits transmitted_ib_multicast; 5401 5402 struct mlx5_ifc_traffic_counter_bits received_eth_broadcast; 5403 5404 struct mlx5_ifc_traffic_counter_bits transmitted_eth_broadcast; 5405 5406 struct mlx5_ifc_traffic_counter_bits received_eth_unicast; 5407 5408 struct mlx5_ifc_traffic_counter_bits transmitted_eth_unicast; 5409 5410 struct mlx5_ifc_traffic_counter_bits received_eth_multicast; 5411 5412 struct mlx5_ifc_traffic_counter_bits transmitted_eth_multicast; 5413 5414 struct mlx5_ifc_traffic_counter_bits local_loopback; 5415 5416 u8 reserved_at_700[0x980]; 5417 }; 5418 5419 enum { 5420 MLX5_QUERY_VPORT_COUNTER_IN_OP_MOD_VPORT_COUNTERS = 0x0, 5421 }; 5422 5423 struct mlx5_ifc_query_vport_counter_in_bits { 5424 u8 opcode[0x10]; 5425 u8 reserved_at_10[0x10]; 5426 5427 u8 reserved_at_20[0x10]; 5428 u8 op_mod[0x10]; 5429 5430 u8 other_vport[0x1]; 5431 u8 reserved_at_41[0xb]; 5432 u8 port_num[0x4]; 5433 u8 vport_number[0x10]; 5434 5435 u8 reserved_at_60[0x60]; 5436 5437 u8 clear[0x1]; 5438 u8 reserved_at_c1[0x1f]; 5439 5440 u8 reserved_at_e0[0x20]; 5441 }; 5442 5443 struct mlx5_ifc_query_tis_out_bits { 5444 u8 status[0x8]; 5445 u8 reserved_at_8[0x18]; 5446 5447 u8 syndrome[0x20]; 5448 5449 u8 reserved_at_40[0x40]; 5450 5451 struct mlx5_ifc_tisc_bits tis_context; 5452 }; 5453 5454 struct mlx5_ifc_query_tis_in_bits { 5455 u8 opcode[0x10]; 5456 u8 reserved_at_10[0x10]; 5457 5458 u8 reserved_at_20[0x10]; 5459 u8 op_mod[0x10]; 5460 5461 u8 reserved_at_40[0x8]; 5462 u8 tisn[0x18]; 5463 5464 u8 reserved_at_60[0x20]; 5465 }; 5466 5467 struct mlx5_ifc_query_tir_out_bits { 5468 u8 status[0x8]; 5469 u8 reserved_at_8[0x18]; 5470 5471 u8 syndrome[0x20]; 5472 5473 u8 reserved_at_40[0xc0]; 5474 5475 struct mlx5_ifc_tirc_bits tir_context; 5476 }; 5477 5478 struct mlx5_ifc_query_tir_in_bits { 5479 u8 opcode[0x10]; 5480 u8 reserved_at_10[0x10]; 5481 5482 u8 reserved_at_20[0x10]; 5483 u8 op_mod[0x10]; 5484 5485 u8 reserved_at_40[0x8]; 5486 u8 tirn[0x18]; 5487 5488 u8 reserved_at_60[0x20]; 5489 }; 5490 5491 struct mlx5_ifc_query_srq_out_bits { 5492 u8 status[0x8]; 5493 u8 reserved_at_8[0x18]; 5494 5495 u8 syndrome[0x20]; 5496 5497 u8 reserved_at_40[0x40]; 5498 5499 struct mlx5_ifc_srqc_bits srq_context_entry; 5500 5501 u8 reserved_at_280[0x600]; 5502 5503 u8 pas[][0x40]; 5504 }; 5505 5506 struct mlx5_ifc_query_srq_in_bits { 5507 u8 opcode[0x10]; 5508 u8 reserved_at_10[0x10]; 5509 5510 u8 reserved_at_20[0x10]; 5511 u8 op_mod[0x10]; 5512 5513 u8 reserved_at_40[0x8]; 5514 u8 srqn[0x18]; 5515 5516 u8 reserved_at_60[0x20]; 5517 }; 5518 5519 struct mlx5_ifc_query_sq_out_bits { 5520 u8 status[0x8]; 5521 u8 reserved_at_8[0x18]; 5522 5523 u8 syndrome[0x20]; 5524 5525 u8 reserved_at_40[0xc0]; 5526 5527 struct mlx5_ifc_sqc_bits sq_context; 5528 }; 5529 5530 struct mlx5_ifc_query_sq_in_bits { 5531 u8 opcode[0x10]; 5532 u8 reserved_at_10[0x10]; 5533 5534 u8 reserved_at_20[0x10]; 5535 u8 op_mod[0x10]; 5536 5537 u8 reserved_at_40[0x8]; 5538 u8 sqn[0x18]; 5539 5540 u8 reserved_at_60[0x20]; 5541 }; 5542 5543 struct mlx5_ifc_query_special_contexts_out_bits { 5544 u8 status[0x8]; 5545 u8 reserved_at_8[0x18]; 5546 5547 u8 syndrome[0x20]; 5548 5549 u8 dump_fill_mkey[0x20]; 5550 5551 u8 resd_lkey[0x20]; 5552 5553 u8 null_mkey[0x20]; 5554 5555 u8 terminate_scatter_list_mkey[0x20]; 5556 5557 u8 repeated_mkey[0x20]; 5558 5559 u8 reserved_at_a0[0x20]; 5560 }; 5561 5562 struct mlx5_ifc_query_special_contexts_in_bits { 5563 u8 opcode[0x10]; 5564 u8 reserved_at_10[0x10]; 5565 5566 u8 reserved_at_20[0x10]; 5567 u8 op_mod[0x10]; 5568 5569 u8 reserved_at_40[0x40]; 5570 }; 5571 5572 struct mlx5_ifc_query_scheduling_element_out_bits { 5573 u8 opcode[0x10]; 5574 u8 reserved_at_10[0x10]; 5575 5576 u8 reserved_at_20[0x10]; 5577 u8 op_mod[0x10]; 5578 5579 u8 reserved_at_40[0xc0]; 5580 5581 struct mlx5_ifc_scheduling_context_bits scheduling_context; 5582 5583 u8 reserved_at_300[0x100]; 5584 }; 5585 5586 enum { 5587 SCHEDULING_HIERARCHY_E_SWITCH = 0x2, 5588 SCHEDULING_HIERARCHY_NIC = 0x3, 5589 }; 5590 5591 struct mlx5_ifc_query_scheduling_element_in_bits { 5592 u8 opcode[0x10]; 5593 u8 reserved_at_10[0x10]; 5594 5595 u8 reserved_at_20[0x10]; 5596 u8 op_mod[0x10]; 5597 5598 u8 scheduling_hierarchy[0x8]; 5599 u8 reserved_at_48[0x18]; 5600 5601 u8 scheduling_element_id[0x20]; 5602 5603 u8 reserved_at_80[0x180]; 5604 }; 5605 5606 struct mlx5_ifc_query_rqt_out_bits { 5607 u8 status[0x8]; 5608 u8 reserved_at_8[0x18]; 5609 5610 u8 syndrome[0x20]; 5611 5612 u8 reserved_at_40[0xc0]; 5613 5614 struct mlx5_ifc_rqtc_bits rqt_context; 5615 }; 5616 5617 struct mlx5_ifc_query_rqt_in_bits { 5618 u8 opcode[0x10]; 5619 u8 reserved_at_10[0x10]; 5620 5621 u8 reserved_at_20[0x10]; 5622 u8 op_mod[0x10]; 5623 5624 u8 reserved_at_40[0x8]; 5625 u8 rqtn[0x18]; 5626 5627 u8 reserved_at_60[0x20]; 5628 }; 5629 5630 struct mlx5_ifc_query_rq_out_bits { 5631 u8 status[0x8]; 5632 u8 reserved_at_8[0x18]; 5633 5634 u8 syndrome[0x20]; 5635 5636 u8 reserved_at_40[0xc0]; 5637 5638 struct mlx5_ifc_rqc_bits rq_context; 5639 }; 5640 5641 struct mlx5_ifc_query_rq_in_bits { 5642 u8 opcode[0x10]; 5643 u8 reserved_at_10[0x10]; 5644 5645 u8 reserved_at_20[0x10]; 5646 u8 op_mod[0x10]; 5647 5648 u8 reserved_at_40[0x8]; 5649 u8 rqn[0x18]; 5650 5651 u8 reserved_at_60[0x20]; 5652 }; 5653 5654 struct mlx5_ifc_query_roce_address_out_bits { 5655 u8 status[0x8]; 5656 u8 reserved_at_8[0x18]; 5657 5658 u8 syndrome[0x20]; 5659 5660 u8 reserved_at_40[0x40]; 5661 5662 struct mlx5_ifc_roce_addr_layout_bits roce_address; 5663 }; 5664 5665 struct mlx5_ifc_query_roce_address_in_bits { 5666 u8 opcode[0x10]; 5667 u8 reserved_at_10[0x10]; 5668 5669 u8 reserved_at_20[0x10]; 5670 u8 op_mod[0x10]; 5671 5672 u8 roce_address_index[0x10]; 5673 u8 reserved_at_50[0xc]; 5674 u8 vhca_port_num[0x4]; 5675 5676 u8 reserved_at_60[0x20]; 5677 }; 5678 5679 struct mlx5_ifc_query_rmp_out_bits { 5680 u8 status[0x8]; 5681 u8 reserved_at_8[0x18]; 5682 5683 u8 syndrome[0x20]; 5684 5685 u8 reserved_at_40[0xc0]; 5686 5687 struct mlx5_ifc_rmpc_bits rmp_context; 5688 }; 5689 5690 struct mlx5_ifc_query_rmp_in_bits { 5691 u8 opcode[0x10]; 5692 u8 reserved_at_10[0x10]; 5693 5694 u8 reserved_at_20[0x10]; 5695 u8 op_mod[0x10]; 5696 5697 u8 reserved_at_40[0x8]; 5698 u8 rmpn[0x18]; 5699 5700 u8 reserved_at_60[0x20]; 5701 }; 5702 5703 struct mlx5_ifc_cqe_error_syndrome_bits { 5704 u8 hw_error_syndrome[0x8]; 5705 u8 hw_syndrome_type[0x4]; 5706 u8 reserved_at_c[0x4]; 5707 u8 vendor_error_syndrome[0x8]; 5708 u8 syndrome[0x8]; 5709 }; 5710 5711 struct mlx5_ifc_qp_context_extension_bits { 5712 u8 reserved_at_0[0x60]; 5713 5714 struct mlx5_ifc_cqe_error_syndrome_bits error_syndrome; 5715 5716 u8 reserved_at_80[0x580]; 5717 }; 5718 5719 struct mlx5_ifc_qpc_extension_and_pas_list_in_bits { 5720 struct mlx5_ifc_qp_context_extension_bits qpc_data_extension; 5721 5722 u8 pas[0][0x40]; 5723 }; 5724 5725 struct mlx5_ifc_qp_pas_list_in_bits { 5726 struct mlx5_ifc_cmd_pas_bits pas[0]; 5727 }; 5728 5729 union mlx5_ifc_qp_pas_or_qpc_ext_and_pas_bits { 5730 struct mlx5_ifc_qp_pas_list_in_bits qp_pas_list; 5731 struct mlx5_ifc_qpc_extension_and_pas_list_in_bits qpc_ext_and_pas_list; 5732 }; 5733 5734 struct mlx5_ifc_query_qp_out_bits { 5735 u8 status[0x8]; 5736 u8 reserved_at_8[0x18]; 5737 5738 u8 syndrome[0x20]; 5739 5740 u8 reserved_at_40[0x40]; 5741 5742 u8 opt_param_mask[0x20]; 5743 5744 u8 ece[0x20]; 5745 5746 struct mlx5_ifc_qpc_bits qpc; 5747 5748 u8 reserved_at_800[0x80]; 5749 5750 union mlx5_ifc_qp_pas_or_qpc_ext_and_pas_bits qp_pas_or_qpc_ext_and_pas; 5751 }; 5752 5753 struct mlx5_ifc_query_qp_in_bits { 5754 u8 opcode[0x10]; 5755 u8 reserved_at_10[0x10]; 5756 5757 u8 reserved_at_20[0x10]; 5758 u8 op_mod[0x10]; 5759 5760 u8 qpc_ext[0x1]; 5761 u8 reserved_at_41[0x7]; 5762 u8 qpn[0x18]; 5763 5764 u8 reserved_at_60[0x20]; 5765 }; 5766 5767 struct mlx5_ifc_query_q_counter_out_bits { 5768 u8 status[0x8]; 5769 u8 reserved_at_8[0x18]; 5770 5771 u8 syndrome[0x20]; 5772 5773 u8 reserved_at_40[0x40]; 5774 5775 u8 rx_write_requests[0x20]; 5776 5777 u8 reserved_at_a0[0x20]; 5778 5779 u8 rx_read_requests[0x20]; 5780 5781 u8 reserved_at_e0[0x20]; 5782 5783 u8 rx_atomic_requests[0x20]; 5784 5785 u8 reserved_at_120[0x20]; 5786 5787 u8 rx_dct_connect[0x20]; 5788 5789 u8 reserved_at_160[0x20]; 5790 5791 u8 out_of_buffer[0x20]; 5792 5793 u8 reserved_at_1a0[0x20]; 5794 5795 u8 out_of_sequence[0x20]; 5796 5797 u8 reserved_at_1e0[0x20]; 5798 5799 u8 duplicate_request[0x20]; 5800 5801 u8 reserved_at_220[0x20]; 5802 5803 u8 rnr_nak_retry_err[0x20]; 5804 5805 u8 reserved_at_260[0x20]; 5806 5807 u8 packet_seq_err[0x20]; 5808 5809 u8 reserved_at_2a0[0x20]; 5810 5811 u8 implied_nak_seq_err[0x20]; 5812 5813 u8 reserved_at_2e0[0x20]; 5814 5815 u8 local_ack_timeout_err[0x20]; 5816 5817 u8 reserved_at_320[0x60]; 5818 5819 u8 req_rnr_retries_exceeded[0x20]; 5820 5821 u8 reserved_at_3a0[0x20]; 5822 5823 u8 resp_local_length_error[0x20]; 5824 5825 u8 req_local_length_error[0x20]; 5826 5827 u8 resp_local_qp_error[0x20]; 5828 5829 u8 local_operation_error[0x20]; 5830 5831 u8 resp_local_protection[0x20]; 5832 5833 u8 req_local_protection[0x20]; 5834 5835 u8 resp_cqe_error[0x20]; 5836 5837 u8 req_cqe_error[0x20]; 5838 5839 u8 req_mw_binding[0x20]; 5840 5841 u8 req_bad_response[0x20]; 5842 5843 u8 req_remote_invalid_request[0x20]; 5844 5845 u8 resp_remote_invalid_request[0x20]; 5846 5847 u8 req_remote_access_errors[0x20]; 5848 5849 u8 resp_remote_access_errors[0x20]; 5850 5851 u8 req_remote_operation_errors[0x20]; 5852 5853 u8 req_transport_retries_exceeded[0x20]; 5854 5855 u8 cq_overflow[0x20]; 5856 5857 u8 resp_cqe_flush_error[0x20]; 5858 5859 u8 req_cqe_flush_error[0x20]; 5860 5861 u8 reserved_at_620[0x20]; 5862 5863 u8 roce_adp_retrans[0x20]; 5864 5865 u8 roce_adp_retrans_to[0x20]; 5866 5867 u8 roce_slow_restart[0x20]; 5868 5869 u8 roce_slow_restart_cnps[0x20]; 5870 5871 u8 roce_slow_restart_trans[0x20]; 5872 5873 u8 reserved_at_6e0[0x120]; 5874 }; 5875 5876 struct mlx5_ifc_query_q_counter_in_bits { 5877 u8 opcode[0x10]; 5878 u8 reserved_at_10[0x10]; 5879 5880 u8 reserved_at_20[0x10]; 5881 u8 op_mod[0x10]; 5882 5883 u8 other_vport[0x1]; 5884 u8 reserved_at_41[0xf]; 5885 u8 vport_number[0x10]; 5886 5887 u8 reserved_at_60[0x60]; 5888 5889 u8 clear[0x1]; 5890 u8 aggregate[0x1]; 5891 u8 reserved_at_c2[0x1e]; 5892 5893 u8 reserved_at_e0[0x18]; 5894 u8 counter_set_id[0x8]; 5895 }; 5896 5897 struct mlx5_ifc_query_pages_out_bits { 5898 u8 status[0x8]; 5899 u8 reserved_at_8[0x18]; 5900 5901 u8 syndrome[0x20]; 5902 5903 u8 embedded_cpu_function[0x1]; 5904 u8 reserved_at_41[0xf]; 5905 u8 function_id[0x10]; 5906 5907 u8 num_pages[0x20]; 5908 }; 5909 5910 enum { 5911 MLX5_QUERY_PAGES_IN_OP_MOD_BOOT_PAGES = 0x1, 5912 MLX5_QUERY_PAGES_IN_OP_MOD_INIT_PAGES = 0x2, 5913 MLX5_QUERY_PAGES_IN_OP_MOD_REGULAR_PAGES = 0x3, 5914 }; 5915 5916 struct mlx5_ifc_query_pages_in_bits { 5917 u8 opcode[0x10]; 5918 u8 reserved_at_10[0x10]; 5919 5920 u8 reserved_at_20[0x10]; 5921 u8 op_mod[0x10]; 5922 5923 u8 embedded_cpu_function[0x1]; 5924 u8 reserved_at_41[0xf]; 5925 u8 function_id[0x10]; 5926 5927 u8 reserved_at_60[0x20]; 5928 }; 5929 5930 struct mlx5_ifc_query_nic_vport_context_out_bits { 5931 u8 status[0x8]; 5932 u8 reserved_at_8[0x18]; 5933 5934 u8 syndrome[0x20]; 5935 5936 u8 reserved_at_40[0x40]; 5937 5938 struct mlx5_ifc_nic_vport_context_bits nic_vport_context; 5939 }; 5940 5941 struct mlx5_ifc_query_nic_vport_context_in_bits { 5942 u8 opcode[0x10]; 5943 u8 reserved_at_10[0x10]; 5944 5945 u8 reserved_at_20[0x10]; 5946 u8 op_mod[0x10]; 5947 5948 u8 other_vport[0x1]; 5949 u8 reserved_at_41[0xf]; 5950 u8 vport_number[0x10]; 5951 5952 u8 reserved_at_60[0x5]; 5953 u8 allowed_list_type[0x3]; 5954 u8 reserved_at_68[0x18]; 5955 }; 5956 5957 struct mlx5_ifc_query_mkey_out_bits { 5958 u8 status[0x8]; 5959 u8 reserved_at_8[0x18]; 5960 5961 u8 syndrome[0x20]; 5962 5963 u8 reserved_at_40[0x40]; 5964 5965 struct mlx5_ifc_mkc_bits memory_key_mkey_entry; 5966 5967 u8 reserved_at_280[0x600]; 5968 5969 u8 bsf0_klm0_pas_mtt0_1[16][0x8]; 5970 5971 u8 bsf1_klm1_pas_mtt2_3[16][0x8]; 5972 }; 5973 5974 struct mlx5_ifc_query_mkey_in_bits { 5975 u8 opcode[0x10]; 5976 u8 reserved_at_10[0x10]; 5977 5978 u8 reserved_at_20[0x10]; 5979 u8 op_mod[0x10]; 5980 5981 u8 reserved_at_40[0x8]; 5982 u8 mkey_index[0x18]; 5983 5984 u8 pg_access[0x1]; 5985 u8 reserved_at_61[0x1f]; 5986 }; 5987 5988 struct mlx5_ifc_query_mad_demux_out_bits { 5989 u8 status[0x8]; 5990 u8 reserved_at_8[0x18]; 5991 5992 u8 syndrome[0x20]; 5993 5994 u8 reserved_at_40[0x40]; 5995 5996 u8 mad_dumux_parameters_block[0x20]; 5997 }; 5998 5999 struct mlx5_ifc_query_mad_demux_in_bits { 6000 u8 opcode[0x10]; 6001 u8 reserved_at_10[0x10]; 6002 6003 u8 reserved_at_20[0x10]; 6004 u8 op_mod[0x10]; 6005 6006 u8 reserved_at_40[0x40]; 6007 }; 6008 6009 struct mlx5_ifc_query_l2_table_entry_out_bits { 6010 u8 status[0x8]; 6011 u8 reserved_at_8[0x18]; 6012 6013 u8 syndrome[0x20]; 6014 6015 u8 reserved_at_40[0xa0]; 6016 6017 u8 reserved_at_e0[0x13]; 6018 u8 vlan_valid[0x1]; 6019 u8 vlan[0xc]; 6020 6021 struct mlx5_ifc_mac_address_layout_bits mac_address; 6022 6023 u8 reserved_at_140[0xc0]; 6024 }; 6025 6026 struct mlx5_ifc_query_l2_table_entry_in_bits { 6027 u8 opcode[0x10]; 6028 u8 reserved_at_10[0x10]; 6029 6030 u8 reserved_at_20[0x10]; 6031 u8 op_mod[0x10]; 6032 6033 u8 reserved_at_40[0x60]; 6034 6035 u8 reserved_at_a0[0x8]; 6036 u8 table_index[0x18]; 6037 6038 u8 reserved_at_c0[0x140]; 6039 }; 6040 6041 struct mlx5_ifc_query_issi_out_bits { 6042 u8 status[0x8]; 6043 u8 reserved_at_8[0x18]; 6044 6045 u8 syndrome[0x20]; 6046 6047 u8 reserved_at_40[0x10]; 6048 u8 current_issi[0x10]; 6049 6050 u8 reserved_at_60[0xa0]; 6051 6052 u8 reserved_at_100[76][0x8]; 6053 u8 supported_issi_dw0[0x20]; 6054 }; 6055 6056 struct mlx5_ifc_query_issi_in_bits { 6057 u8 opcode[0x10]; 6058 u8 reserved_at_10[0x10]; 6059 6060 u8 reserved_at_20[0x10]; 6061 u8 op_mod[0x10]; 6062 6063 u8 reserved_at_40[0x40]; 6064 }; 6065 6066 struct mlx5_ifc_set_driver_version_out_bits { 6067 u8 status[0x8]; 6068 u8 reserved_0[0x18]; 6069 6070 u8 syndrome[0x20]; 6071 u8 reserved_1[0x40]; 6072 }; 6073 6074 struct mlx5_ifc_set_driver_version_in_bits { 6075 u8 opcode[0x10]; 6076 u8 reserved_0[0x10]; 6077 6078 u8 reserved_1[0x10]; 6079 u8 op_mod[0x10]; 6080 6081 u8 reserved_2[0x40]; 6082 u8 driver_version[64][0x8]; 6083 }; 6084 6085 struct mlx5_ifc_query_hca_vport_pkey_out_bits { 6086 u8 status[0x8]; 6087 u8 reserved_at_8[0x18]; 6088 6089 u8 syndrome[0x20]; 6090 6091 u8 reserved_at_40[0x40]; 6092 6093 struct mlx5_ifc_pkey_bits pkey[]; 6094 }; 6095 6096 struct mlx5_ifc_query_hca_vport_pkey_in_bits { 6097 u8 opcode[0x10]; 6098 u8 reserved_at_10[0x10]; 6099 6100 u8 reserved_at_20[0x10]; 6101 u8 op_mod[0x10]; 6102 6103 u8 other_vport[0x1]; 6104 u8 reserved_at_41[0xb]; 6105 u8 port_num[0x4]; 6106 u8 vport_number[0x10]; 6107 6108 u8 reserved_at_60[0x10]; 6109 u8 pkey_index[0x10]; 6110 }; 6111 6112 enum { 6113 MLX5_HCA_VPORT_SEL_PORT_GUID = 1 << 0, 6114 MLX5_HCA_VPORT_SEL_NODE_GUID = 1 << 1, 6115 MLX5_HCA_VPORT_SEL_STATE_POLICY = 1 << 2, 6116 }; 6117 6118 struct mlx5_ifc_query_hca_vport_gid_out_bits { 6119 u8 status[0x8]; 6120 u8 reserved_at_8[0x18]; 6121 6122 u8 syndrome[0x20]; 6123 6124 u8 reserved_at_40[0x20]; 6125 6126 u8 gids_num[0x10]; 6127 u8 reserved_at_70[0x10]; 6128 6129 struct mlx5_ifc_array128_auto_bits gid[]; 6130 }; 6131 6132 struct mlx5_ifc_query_hca_vport_gid_in_bits { 6133 u8 opcode[0x10]; 6134 u8 reserved_at_10[0x10]; 6135 6136 u8 reserved_at_20[0x10]; 6137 u8 op_mod[0x10]; 6138 6139 u8 other_vport[0x1]; 6140 u8 reserved_at_41[0xb]; 6141 u8 port_num[0x4]; 6142 u8 vport_number[0x10]; 6143 6144 u8 reserved_at_60[0x10]; 6145 u8 gid_index[0x10]; 6146 }; 6147 6148 struct mlx5_ifc_query_hca_vport_context_out_bits { 6149 u8 status[0x8]; 6150 u8 reserved_at_8[0x18]; 6151 6152 u8 syndrome[0x20]; 6153 6154 u8 reserved_at_40[0x40]; 6155 6156 struct mlx5_ifc_hca_vport_context_bits hca_vport_context; 6157 }; 6158 6159 struct mlx5_ifc_query_hca_vport_context_in_bits { 6160 u8 opcode[0x10]; 6161 u8 reserved_at_10[0x10]; 6162 6163 u8 reserved_at_20[0x10]; 6164 u8 op_mod[0x10]; 6165 6166 u8 other_vport[0x1]; 6167 u8 reserved_at_41[0xb]; 6168 u8 port_num[0x4]; 6169 u8 vport_number[0x10]; 6170 6171 u8 reserved_at_60[0x20]; 6172 }; 6173 6174 struct mlx5_ifc_query_hca_cap_out_bits { 6175 u8 status[0x8]; 6176 u8 reserved_at_8[0x18]; 6177 6178 u8 syndrome[0x20]; 6179 6180 u8 reserved_at_40[0x40]; 6181 6182 union mlx5_ifc_hca_cap_union_bits capability; 6183 }; 6184 6185 struct mlx5_ifc_query_hca_cap_in_bits { 6186 u8 opcode[0x10]; 6187 u8 reserved_at_10[0x10]; 6188 6189 u8 reserved_at_20[0x10]; 6190 u8 op_mod[0x10]; 6191 6192 u8 other_function[0x1]; 6193 u8 ec_vf_function[0x1]; 6194 u8 reserved_at_42[0xe]; 6195 u8 function_id[0x10]; 6196 6197 u8 reserved_at_60[0x20]; 6198 }; 6199 6200 struct mlx5_ifc_other_hca_cap_bits { 6201 u8 roce[0x1]; 6202 u8 reserved_at_1[0x27f]; 6203 }; 6204 6205 struct mlx5_ifc_query_other_hca_cap_out_bits { 6206 u8 status[0x8]; 6207 u8 reserved_at_8[0x18]; 6208 6209 u8 syndrome[0x20]; 6210 6211 u8 reserved_at_40[0x40]; 6212 6213 struct mlx5_ifc_other_hca_cap_bits other_capability; 6214 }; 6215 6216 struct mlx5_ifc_query_other_hca_cap_in_bits { 6217 u8 opcode[0x10]; 6218 u8 reserved_at_10[0x10]; 6219 6220 u8 reserved_at_20[0x10]; 6221 u8 op_mod[0x10]; 6222 6223 u8 reserved_at_40[0x10]; 6224 u8 function_id[0x10]; 6225 6226 u8 reserved_at_60[0x20]; 6227 }; 6228 6229 struct mlx5_ifc_modify_other_hca_cap_out_bits { 6230 u8 status[0x8]; 6231 u8 reserved_at_8[0x18]; 6232 6233 u8 syndrome[0x20]; 6234 6235 u8 reserved_at_40[0x40]; 6236 }; 6237 6238 struct mlx5_ifc_modify_other_hca_cap_in_bits { 6239 u8 opcode[0x10]; 6240 u8 reserved_at_10[0x10]; 6241 6242 u8 reserved_at_20[0x10]; 6243 u8 op_mod[0x10]; 6244 6245 u8 reserved_at_40[0x10]; 6246 u8 function_id[0x10]; 6247 u8 field_select[0x20]; 6248 6249 struct mlx5_ifc_other_hca_cap_bits other_capability; 6250 }; 6251 6252 struct mlx5_ifc_flow_table_context_bits { 6253 u8 reformat_en[0x1]; 6254 u8 decap_en[0x1]; 6255 u8 sw_owner[0x1]; 6256 u8 termination_table[0x1]; 6257 u8 table_miss_action[0x4]; 6258 u8 level[0x8]; 6259 u8 rtc_valid[0x1]; 6260 u8 reserved_at_11[0x7]; 6261 u8 log_size[0x8]; 6262 6263 u8 reserved_at_20[0x8]; 6264 u8 table_miss_id[0x18]; 6265 6266 u8 reserved_at_40[0x8]; 6267 u8 lag_master_next_table_id[0x18]; 6268 6269 u8 reserved_at_60[0x60]; 6270 union { 6271 struct { 6272 u8 sw_owner_icm_root_1[0x40]; 6273 6274 u8 sw_owner_icm_root_0[0x40]; 6275 } sws; 6276 struct { 6277 u8 rtc_id_0[0x20]; 6278 6279 u8 rtc_id_1[0x20]; 6280 6281 u8 reserved_at_100[0x40]; 6282 6283 } hws; 6284 }; 6285 }; 6286 6287 struct mlx5_ifc_query_flow_table_out_bits { 6288 u8 status[0x8]; 6289 u8 reserved_at_8[0x18]; 6290 6291 u8 syndrome[0x20]; 6292 6293 u8 reserved_at_40[0x80]; 6294 6295 struct mlx5_ifc_flow_table_context_bits flow_table_context; 6296 }; 6297 6298 struct mlx5_ifc_query_flow_table_in_bits { 6299 u8 opcode[0x10]; 6300 u8 reserved_at_10[0x10]; 6301 6302 u8 reserved_at_20[0x10]; 6303 u8 op_mod[0x10]; 6304 6305 u8 reserved_at_40[0x40]; 6306 6307 u8 table_type[0x8]; 6308 u8 reserved_at_88[0x18]; 6309 6310 u8 reserved_at_a0[0x8]; 6311 u8 table_id[0x18]; 6312 6313 u8 reserved_at_c0[0x140]; 6314 }; 6315 6316 struct mlx5_ifc_query_fte_out_bits { 6317 u8 status[0x8]; 6318 u8 reserved_at_8[0x18]; 6319 6320 u8 syndrome[0x20]; 6321 6322 u8 reserved_at_40[0x1c0]; 6323 6324 struct mlx5_ifc_flow_context_bits flow_context; 6325 }; 6326 6327 struct mlx5_ifc_query_fte_in_bits { 6328 u8 opcode[0x10]; 6329 u8 reserved_at_10[0x10]; 6330 6331 u8 reserved_at_20[0x10]; 6332 u8 op_mod[0x10]; 6333 6334 u8 reserved_at_40[0x40]; 6335 6336 u8 table_type[0x8]; 6337 u8 reserved_at_88[0x18]; 6338 6339 u8 reserved_at_a0[0x8]; 6340 u8 table_id[0x18]; 6341 6342 u8 reserved_at_c0[0x40]; 6343 6344 u8 flow_index[0x20]; 6345 6346 u8 reserved_at_120[0xe0]; 6347 }; 6348 6349 struct mlx5_ifc_match_definer_format_0_bits { 6350 u8 reserved_at_0[0x100]; 6351 6352 u8 metadata_reg_c_0[0x20]; 6353 6354 u8 metadata_reg_c_1[0x20]; 6355 6356 u8 outer_dmac_47_16[0x20]; 6357 6358 u8 outer_dmac_15_0[0x10]; 6359 u8 outer_ethertype[0x10]; 6360 6361 u8 reserved_at_180[0x1]; 6362 u8 sx_sniffer[0x1]; 6363 u8 functional_lb[0x1]; 6364 u8 outer_ip_frag[0x1]; 6365 u8 outer_qp_type[0x2]; 6366 u8 outer_encap_type[0x2]; 6367 u8 port_number[0x2]; 6368 u8 outer_l3_type[0x2]; 6369 u8 outer_l4_type[0x2]; 6370 u8 outer_first_vlan_type[0x2]; 6371 u8 outer_first_vlan_prio[0x3]; 6372 u8 outer_first_vlan_cfi[0x1]; 6373 u8 outer_first_vlan_vid[0xc]; 6374 6375 u8 outer_l4_type_ext[0x4]; 6376 u8 reserved_at_1a4[0x2]; 6377 u8 outer_ipsec_layer[0x2]; 6378 u8 outer_l2_type[0x2]; 6379 u8 force_lb[0x1]; 6380 u8 outer_l2_ok[0x1]; 6381 u8 outer_l3_ok[0x1]; 6382 u8 outer_l4_ok[0x1]; 6383 u8 outer_second_vlan_type[0x2]; 6384 u8 outer_second_vlan_prio[0x3]; 6385 u8 outer_second_vlan_cfi[0x1]; 6386 u8 outer_second_vlan_vid[0xc]; 6387 6388 u8 outer_smac_47_16[0x20]; 6389 6390 u8 outer_smac_15_0[0x10]; 6391 u8 inner_ipv4_checksum_ok[0x1]; 6392 u8 inner_l4_checksum_ok[0x1]; 6393 u8 outer_ipv4_checksum_ok[0x1]; 6394 u8 outer_l4_checksum_ok[0x1]; 6395 u8 inner_l3_ok[0x1]; 6396 u8 inner_l4_ok[0x1]; 6397 u8 outer_l3_ok_duplicate[0x1]; 6398 u8 outer_l4_ok_duplicate[0x1]; 6399 u8 outer_tcp_cwr[0x1]; 6400 u8 outer_tcp_ece[0x1]; 6401 u8 outer_tcp_urg[0x1]; 6402 u8 outer_tcp_ack[0x1]; 6403 u8 outer_tcp_psh[0x1]; 6404 u8 outer_tcp_rst[0x1]; 6405 u8 outer_tcp_syn[0x1]; 6406 u8 outer_tcp_fin[0x1]; 6407 }; 6408 6409 struct mlx5_ifc_match_definer_format_22_bits { 6410 u8 reserved_at_0[0x100]; 6411 6412 u8 outer_ip_src_addr[0x20]; 6413 6414 u8 outer_ip_dest_addr[0x20]; 6415 6416 u8 outer_l4_sport[0x10]; 6417 u8 outer_l4_dport[0x10]; 6418 6419 u8 reserved_at_160[0x1]; 6420 u8 sx_sniffer[0x1]; 6421 u8 functional_lb[0x1]; 6422 u8 outer_ip_frag[0x1]; 6423 u8 outer_qp_type[0x2]; 6424 u8 outer_encap_type[0x2]; 6425 u8 port_number[0x2]; 6426 u8 outer_l3_type[0x2]; 6427 u8 outer_l4_type[0x2]; 6428 u8 outer_first_vlan_type[0x2]; 6429 u8 outer_first_vlan_prio[0x3]; 6430 u8 outer_first_vlan_cfi[0x1]; 6431 u8 outer_first_vlan_vid[0xc]; 6432 6433 u8 metadata_reg_c_0[0x20]; 6434 6435 u8 outer_dmac_47_16[0x20]; 6436 6437 u8 outer_smac_47_16[0x20]; 6438 6439 u8 outer_smac_15_0[0x10]; 6440 u8 outer_dmac_15_0[0x10]; 6441 }; 6442 6443 struct mlx5_ifc_match_definer_format_23_bits { 6444 u8 reserved_at_0[0x100]; 6445 6446 u8 inner_ip_src_addr[0x20]; 6447 6448 u8 inner_ip_dest_addr[0x20]; 6449 6450 u8 inner_l4_sport[0x10]; 6451 u8 inner_l4_dport[0x10]; 6452 6453 u8 reserved_at_160[0x1]; 6454 u8 sx_sniffer[0x1]; 6455 u8 functional_lb[0x1]; 6456 u8 inner_ip_frag[0x1]; 6457 u8 inner_qp_type[0x2]; 6458 u8 inner_encap_type[0x2]; 6459 u8 port_number[0x2]; 6460 u8 inner_l3_type[0x2]; 6461 u8 inner_l4_type[0x2]; 6462 u8 inner_first_vlan_type[0x2]; 6463 u8 inner_first_vlan_prio[0x3]; 6464 u8 inner_first_vlan_cfi[0x1]; 6465 u8 inner_first_vlan_vid[0xc]; 6466 6467 u8 tunnel_header_0[0x20]; 6468 6469 u8 inner_dmac_47_16[0x20]; 6470 6471 u8 inner_smac_47_16[0x20]; 6472 6473 u8 inner_smac_15_0[0x10]; 6474 u8 inner_dmac_15_0[0x10]; 6475 }; 6476 6477 struct mlx5_ifc_match_definer_format_29_bits { 6478 u8 reserved_at_0[0xc0]; 6479 6480 u8 outer_ip_dest_addr[0x80]; 6481 6482 u8 outer_ip_src_addr[0x80]; 6483 6484 u8 outer_l4_sport[0x10]; 6485 u8 outer_l4_dport[0x10]; 6486 6487 u8 reserved_at_1e0[0x20]; 6488 }; 6489 6490 struct mlx5_ifc_match_definer_format_30_bits { 6491 u8 reserved_at_0[0xa0]; 6492 6493 u8 outer_ip_dest_addr[0x80]; 6494 6495 u8 outer_ip_src_addr[0x80]; 6496 6497 u8 outer_dmac_47_16[0x20]; 6498 6499 u8 outer_smac_47_16[0x20]; 6500 6501 u8 outer_smac_15_0[0x10]; 6502 u8 outer_dmac_15_0[0x10]; 6503 }; 6504 6505 struct mlx5_ifc_match_definer_format_31_bits { 6506 u8 reserved_at_0[0xc0]; 6507 6508 u8 inner_ip_dest_addr[0x80]; 6509 6510 u8 inner_ip_src_addr[0x80]; 6511 6512 u8 inner_l4_sport[0x10]; 6513 u8 inner_l4_dport[0x10]; 6514 6515 u8 reserved_at_1e0[0x20]; 6516 }; 6517 6518 struct mlx5_ifc_match_definer_format_32_bits { 6519 u8 reserved_at_0[0xa0]; 6520 6521 u8 inner_ip_dest_addr[0x80]; 6522 6523 u8 inner_ip_src_addr[0x80]; 6524 6525 u8 inner_dmac_47_16[0x20]; 6526 6527 u8 inner_smac_47_16[0x20]; 6528 6529 u8 inner_smac_15_0[0x10]; 6530 u8 inner_dmac_15_0[0x10]; 6531 }; 6532 6533 enum { 6534 MLX5_IFC_DEFINER_FORMAT_ID_SELECT = 61, 6535 }; 6536 6537 #define MLX5_IFC_DEFINER_FORMAT_OFFSET_UNUSED 0x0 6538 #define MLX5_IFC_DEFINER_FORMAT_OFFSET_OUTER_ETH_PKT_LEN 0x48 6539 #define MLX5_IFC_DEFINER_DW_SELECTORS_NUM 9 6540 #define MLX5_IFC_DEFINER_BYTE_SELECTORS_NUM 8 6541 6542 struct mlx5_ifc_match_definer_match_mask_bits { 6543 u8 reserved_at_1c0[5][0x20]; 6544 u8 match_dw_8[0x20]; 6545 u8 match_dw_7[0x20]; 6546 u8 match_dw_6[0x20]; 6547 u8 match_dw_5[0x20]; 6548 u8 match_dw_4[0x20]; 6549 u8 match_dw_3[0x20]; 6550 u8 match_dw_2[0x20]; 6551 u8 match_dw_1[0x20]; 6552 u8 match_dw_0[0x20]; 6553 6554 u8 match_byte_7[0x8]; 6555 u8 match_byte_6[0x8]; 6556 u8 match_byte_5[0x8]; 6557 u8 match_byte_4[0x8]; 6558 6559 u8 match_byte_3[0x8]; 6560 u8 match_byte_2[0x8]; 6561 u8 match_byte_1[0x8]; 6562 u8 match_byte_0[0x8]; 6563 }; 6564 6565 struct mlx5_ifc_match_definer_bits { 6566 u8 modify_field_select[0x40]; 6567 6568 u8 reserved_at_40[0x40]; 6569 6570 u8 reserved_at_80[0x10]; 6571 u8 format_id[0x10]; 6572 6573 u8 reserved_at_a0[0x60]; 6574 6575 u8 format_select_dw3[0x8]; 6576 u8 format_select_dw2[0x8]; 6577 u8 format_select_dw1[0x8]; 6578 u8 format_select_dw0[0x8]; 6579 6580 u8 format_select_dw7[0x8]; 6581 u8 format_select_dw6[0x8]; 6582 u8 format_select_dw5[0x8]; 6583 u8 format_select_dw4[0x8]; 6584 6585 u8 reserved_at_100[0x18]; 6586 u8 format_select_dw8[0x8]; 6587 6588 u8 reserved_at_120[0x20]; 6589 6590 u8 format_select_byte3[0x8]; 6591 u8 format_select_byte2[0x8]; 6592 u8 format_select_byte1[0x8]; 6593 u8 format_select_byte0[0x8]; 6594 6595 u8 format_select_byte7[0x8]; 6596 u8 format_select_byte6[0x8]; 6597 u8 format_select_byte5[0x8]; 6598 u8 format_select_byte4[0x8]; 6599 6600 u8 reserved_at_180[0x40]; 6601 6602 union { 6603 struct { 6604 u8 match_mask[16][0x20]; 6605 }; 6606 struct mlx5_ifc_match_definer_match_mask_bits match_mask_format; 6607 }; 6608 }; 6609 6610 struct mlx5_ifc_general_obj_create_param_bits { 6611 u8 alias_object[0x1]; 6612 u8 reserved_at_1[0x2]; 6613 u8 log_obj_range[0x5]; 6614 u8 reserved_at_8[0x18]; 6615 }; 6616 6617 struct mlx5_ifc_general_obj_query_param_bits { 6618 u8 alias_object[0x1]; 6619 u8 obj_offset[0x1f]; 6620 }; 6621 6622 struct mlx5_ifc_general_obj_in_cmd_hdr_bits { 6623 u8 opcode[0x10]; 6624 u8 uid[0x10]; 6625 6626 u8 vhca_tunnel_id[0x10]; 6627 u8 obj_type[0x10]; 6628 6629 u8 obj_id[0x20]; 6630 6631 union { 6632 struct mlx5_ifc_general_obj_create_param_bits create; 6633 struct mlx5_ifc_general_obj_query_param_bits query; 6634 } op_param; 6635 }; 6636 6637 struct mlx5_ifc_general_obj_out_cmd_hdr_bits { 6638 u8 status[0x8]; 6639 u8 reserved_at_8[0x18]; 6640 6641 u8 syndrome[0x20]; 6642 6643 u8 obj_id[0x20]; 6644 6645 u8 reserved_at_60[0x20]; 6646 }; 6647 6648 struct mlx5_ifc_allow_other_vhca_access_in_bits { 6649 u8 opcode[0x10]; 6650 u8 uid[0x10]; 6651 u8 reserved_at_20[0x10]; 6652 u8 op_mod[0x10]; 6653 u8 reserved_at_40[0x50]; 6654 u8 object_type_to_be_accessed[0x10]; 6655 u8 object_id_to_be_accessed[0x20]; 6656 u8 reserved_at_c0[0x40]; 6657 union { 6658 u8 access_key_raw[0x100]; 6659 u8 access_key[8][0x20]; 6660 }; 6661 }; 6662 6663 struct mlx5_ifc_allow_other_vhca_access_out_bits { 6664 u8 status[0x8]; 6665 u8 reserved_at_8[0x18]; 6666 u8 syndrome[0x20]; 6667 u8 reserved_at_40[0x40]; 6668 }; 6669 6670 struct mlx5_ifc_modify_header_arg_bits { 6671 u8 reserved_at_0[0x80]; 6672 6673 u8 reserved_at_80[0x8]; 6674 u8 access_pd[0x18]; 6675 }; 6676 6677 struct mlx5_ifc_create_modify_header_arg_in_bits { 6678 struct mlx5_ifc_general_obj_in_cmd_hdr_bits hdr; 6679 struct mlx5_ifc_modify_header_arg_bits arg; 6680 }; 6681 6682 struct mlx5_ifc_create_match_definer_in_bits { 6683 struct mlx5_ifc_general_obj_in_cmd_hdr_bits general_obj_in_cmd_hdr; 6684 6685 struct mlx5_ifc_match_definer_bits obj_context; 6686 }; 6687 6688 struct mlx5_ifc_create_match_definer_out_bits { 6689 struct mlx5_ifc_general_obj_out_cmd_hdr_bits general_obj_out_cmd_hdr; 6690 }; 6691 6692 struct mlx5_ifc_alias_context_bits { 6693 u8 vhca_id_to_be_accessed[0x10]; 6694 u8 reserved_at_10[0xd]; 6695 u8 status[0x3]; 6696 u8 object_id_to_be_accessed[0x20]; 6697 u8 reserved_at_40[0x40]; 6698 union { 6699 u8 access_key_raw[0x100]; 6700 u8 access_key[8][0x20]; 6701 }; 6702 u8 metadata[0x80]; 6703 }; 6704 6705 struct mlx5_ifc_create_alias_obj_in_bits { 6706 struct mlx5_ifc_general_obj_in_cmd_hdr_bits hdr; 6707 struct mlx5_ifc_alias_context_bits alias_ctx; 6708 }; 6709 6710 enum { 6711 MLX5_QUERY_FLOW_GROUP_OUT_MATCH_CRITERIA_ENABLE_OUTER_HEADERS = 0x0, 6712 MLX5_QUERY_FLOW_GROUP_OUT_MATCH_CRITERIA_ENABLE_MISC_PARAMETERS = 0x1, 6713 MLX5_QUERY_FLOW_GROUP_OUT_MATCH_CRITERIA_ENABLE_INNER_HEADERS = 0x2, 6714 MLX5_QUERY_FLOW_GROUP_IN_MATCH_CRITERIA_ENABLE_MISC_PARAMETERS_2 = 0x3, 6715 MLX5_QUERY_FLOW_GROUP_IN_MATCH_CRITERIA_ENABLE_MISC_PARAMETERS_3 = 0x4, 6716 MLX5_QUERY_FLOW_GROUP_IN_MATCH_CRITERIA_ENABLE_MISC_PARAMETERS_4 = 0x5, 6717 MLX5_QUERY_FLOW_GROUP_IN_MATCH_CRITERIA_ENABLE_MISC_PARAMETERS_5 = 0x6, 6718 }; 6719 6720 struct mlx5_ifc_query_flow_group_out_bits { 6721 u8 status[0x8]; 6722 u8 reserved_at_8[0x18]; 6723 6724 u8 syndrome[0x20]; 6725 6726 u8 reserved_at_40[0xa0]; 6727 6728 u8 start_flow_index[0x20]; 6729 6730 u8 reserved_at_100[0x20]; 6731 6732 u8 end_flow_index[0x20]; 6733 6734 u8 reserved_at_140[0xa0]; 6735 6736 u8 reserved_at_1e0[0x18]; 6737 u8 match_criteria_enable[0x8]; 6738 6739 struct mlx5_ifc_fte_match_param_bits match_criteria; 6740 6741 u8 reserved_at_1200[0xe00]; 6742 }; 6743 6744 struct mlx5_ifc_query_flow_group_in_bits { 6745 u8 opcode[0x10]; 6746 u8 reserved_at_10[0x10]; 6747 6748 u8 reserved_at_20[0x10]; 6749 u8 op_mod[0x10]; 6750 6751 u8 reserved_at_40[0x40]; 6752 6753 u8 table_type[0x8]; 6754 u8 reserved_at_88[0x18]; 6755 6756 u8 reserved_at_a0[0x8]; 6757 u8 table_id[0x18]; 6758 6759 u8 group_id[0x20]; 6760 6761 u8 reserved_at_e0[0x120]; 6762 }; 6763 6764 struct mlx5_ifc_query_flow_counter_out_bits { 6765 u8 status[0x8]; 6766 u8 reserved_at_8[0x18]; 6767 6768 u8 syndrome[0x20]; 6769 6770 u8 reserved_at_40[0x40]; 6771 6772 struct mlx5_ifc_traffic_counter_bits flow_statistics[]; 6773 }; 6774 6775 struct mlx5_ifc_query_flow_counter_in_bits { 6776 u8 opcode[0x10]; 6777 u8 reserved_at_10[0x10]; 6778 6779 u8 reserved_at_20[0x10]; 6780 u8 op_mod[0x10]; 6781 6782 u8 reserved_at_40[0x80]; 6783 6784 u8 clear[0x1]; 6785 u8 reserved_at_c1[0xf]; 6786 u8 num_of_counters[0x10]; 6787 6788 u8 flow_counter_id[0x20]; 6789 }; 6790 6791 struct mlx5_ifc_query_esw_vport_context_out_bits { 6792 u8 status[0x8]; 6793 u8 reserved_at_8[0x18]; 6794 6795 u8 syndrome[0x20]; 6796 6797 u8 reserved_at_40[0x40]; 6798 6799 struct mlx5_ifc_esw_vport_context_bits esw_vport_context; 6800 }; 6801 6802 struct mlx5_ifc_query_esw_vport_context_in_bits { 6803 u8 opcode[0x10]; 6804 u8 reserved_at_10[0x10]; 6805 6806 u8 reserved_at_20[0x10]; 6807 u8 op_mod[0x10]; 6808 6809 u8 other_vport[0x1]; 6810 u8 reserved_at_41[0xf]; 6811 u8 vport_number[0x10]; 6812 6813 u8 reserved_at_60[0x20]; 6814 }; 6815 6816 struct mlx5_ifc_modify_esw_vport_context_out_bits { 6817 u8 status[0x8]; 6818 u8 reserved_at_8[0x18]; 6819 6820 u8 syndrome[0x20]; 6821 6822 u8 reserved_at_40[0x40]; 6823 }; 6824 6825 struct mlx5_ifc_esw_vport_context_fields_select_bits { 6826 u8 reserved_at_0[0x1b]; 6827 u8 fdb_to_vport_reg_c_id[0x1]; 6828 u8 vport_cvlan_insert[0x1]; 6829 u8 vport_svlan_insert[0x1]; 6830 u8 vport_cvlan_strip[0x1]; 6831 u8 vport_svlan_strip[0x1]; 6832 }; 6833 6834 struct mlx5_ifc_modify_esw_vport_context_in_bits { 6835 u8 opcode[0x10]; 6836 u8 reserved_at_10[0x10]; 6837 6838 u8 reserved_at_20[0x10]; 6839 u8 op_mod[0x10]; 6840 6841 u8 other_vport[0x1]; 6842 u8 reserved_at_41[0xf]; 6843 u8 vport_number[0x10]; 6844 6845 struct mlx5_ifc_esw_vport_context_fields_select_bits field_select; 6846 6847 struct mlx5_ifc_esw_vport_context_bits esw_vport_context; 6848 }; 6849 6850 struct mlx5_ifc_query_eq_out_bits { 6851 u8 status[0x8]; 6852 u8 reserved_at_8[0x18]; 6853 6854 u8 syndrome[0x20]; 6855 6856 u8 reserved_at_40[0x40]; 6857 6858 struct mlx5_ifc_eqc_bits eq_context_entry; 6859 6860 u8 reserved_at_280[0x40]; 6861 6862 u8 event_bitmask[0x40]; 6863 6864 u8 reserved_at_300[0x580]; 6865 6866 u8 pas[][0x40]; 6867 }; 6868 6869 struct mlx5_ifc_query_eq_in_bits { 6870 u8 opcode[0x10]; 6871 u8 reserved_at_10[0x10]; 6872 6873 u8 reserved_at_20[0x10]; 6874 u8 op_mod[0x10]; 6875 6876 u8 reserved_at_40[0x18]; 6877 u8 eq_number[0x8]; 6878 6879 u8 reserved_at_60[0x20]; 6880 }; 6881 6882 struct mlx5_ifc_packet_reformat_context_in_bits { 6883 u8 reformat_type[0x8]; 6884 u8 reserved_at_8[0x4]; 6885 u8 reformat_param_0[0x4]; 6886 u8 reserved_at_10[0x6]; 6887 u8 reformat_data_size[0xa]; 6888 6889 u8 reformat_param_1[0x8]; 6890 u8 reserved_at_28[0x8]; 6891 u8 reformat_data[2][0x8]; 6892 6893 u8 more_reformat_data[][0x8]; 6894 }; 6895 6896 struct mlx5_ifc_query_packet_reformat_context_out_bits { 6897 u8 status[0x8]; 6898 u8 reserved_at_8[0x18]; 6899 6900 u8 syndrome[0x20]; 6901 6902 u8 reserved_at_40[0xa0]; 6903 6904 struct mlx5_ifc_packet_reformat_context_in_bits packet_reformat_context[]; 6905 }; 6906 6907 struct mlx5_ifc_query_packet_reformat_context_in_bits { 6908 u8 opcode[0x10]; 6909 u8 reserved_at_10[0x10]; 6910 6911 u8 reserved_at_20[0x10]; 6912 u8 op_mod[0x10]; 6913 6914 u8 packet_reformat_id[0x20]; 6915 6916 u8 reserved_at_60[0xa0]; 6917 }; 6918 6919 struct mlx5_ifc_alloc_packet_reformat_context_out_bits { 6920 u8 status[0x8]; 6921 u8 reserved_at_8[0x18]; 6922 6923 u8 syndrome[0x20]; 6924 6925 u8 packet_reformat_id[0x20]; 6926 6927 u8 reserved_at_60[0x20]; 6928 }; 6929 6930 enum { 6931 MLX5_REFORMAT_CONTEXT_ANCHOR_MAC_START = 0x1, 6932 MLX5_REFORMAT_CONTEXT_ANCHOR_IP_START = 0x7, 6933 MLX5_REFORMAT_CONTEXT_ANCHOR_TCP_UDP_START = 0x9, 6934 }; 6935 6936 enum mlx5_reformat_ctx_type { 6937 MLX5_REFORMAT_TYPE_L2_TO_VXLAN = 0x0, 6938 MLX5_REFORMAT_TYPE_L2_TO_NVGRE = 0x1, 6939 MLX5_REFORMAT_TYPE_L2_TO_L2_TUNNEL = 0x2, 6940 MLX5_REFORMAT_TYPE_L3_TUNNEL_TO_L2 = 0x3, 6941 MLX5_REFORMAT_TYPE_L2_TO_L3_TUNNEL = 0x4, 6942 MLX5_REFORMAT_TYPE_ADD_ESP_TRANSPORT_OVER_IPV4 = 0x5, 6943 MLX5_REFORMAT_TYPE_L2_TO_L3_ESP_TUNNEL = 0x6, 6944 MLX5_REFORMAT_TYPE_ADD_ESP_TRANSPORT_OVER_UDPV4 = 0x7, 6945 MLX5_REFORMAT_TYPE_DEL_ESP_TRANSPORT = 0x8, 6946 MLX5_REFORMAT_TYPE_L3_ESP_TUNNEL_TO_L2 = 0x9, 6947 MLX5_REFORMAT_TYPE_DEL_ESP_TRANSPORT_OVER_UDP = 0xa, 6948 MLX5_REFORMAT_TYPE_ADD_ESP_TRANSPORT_OVER_IPV6 = 0xb, 6949 MLX5_REFORMAT_TYPE_ADD_ESP_TRANSPORT_OVER_UDPV6 = 0xc, 6950 MLX5_REFORMAT_TYPE_INSERT_HDR = 0xf, 6951 MLX5_REFORMAT_TYPE_REMOVE_HDR = 0x10, 6952 MLX5_REFORMAT_TYPE_ADD_MACSEC = 0x11, 6953 MLX5_REFORMAT_TYPE_DEL_MACSEC = 0x12, 6954 }; 6955 6956 struct mlx5_ifc_alloc_packet_reformat_context_in_bits { 6957 u8 opcode[0x10]; 6958 u8 reserved_at_10[0x10]; 6959 6960 u8 reserved_at_20[0x10]; 6961 u8 op_mod[0x10]; 6962 6963 u8 reserved_at_40[0xa0]; 6964 6965 struct mlx5_ifc_packet_reformat_context_in_bits packet_reformat_context; 6966 }; 6967 6968 struct mlx5_ifc_dealloc_packet_reformat_context_out_bits { 6969 u8 status[0x8]; 6970 u8 reserved_at_8[0x18]; 6971 6972 u8 syndrome[0x20]; 6973 6974 u8 reserved_at_40[0x40]; 6975 }; 6976 6977 struct mlx5_ifc_dealloc_packet_reformat_context_in_bits { 6978 u8 opcode[0x10]; 6979 u8 reserved_at_10[0x10]; 6980 6981 u8 reserved_20[0x10]; 6982 u8 op_mod[0x10]; 6983 6984 u8 packet_reformat_id[0x20]; 6985 6986 u8 reserved_60[0x20]; 6987 }; 6988 6989 struct mlx5_ifc_set_action_in_bits { 6990 u8 action_type[0x4]; 6991 u8 field[0xc]; 6992 u8 reserved_at_10[0x3]; 6993 u8 offset[0x5]; 6994 u8 reserved_at_18[0x3]; 6995 u8 length[0x5]; 6996 6997 u8 data[0x20]; 6998 }; 6999 7000 struct mlx5_ifc_add_action_in_bits { 7001 u8 action_type[0x4]; 7002 u8 field[0xc]; 7003 u8 reserved_at_10[0x10]; 7004 7005 u8 data[0x20]; 7006 }; 7007 7008 struct mlx5_ifc_copy_action_in_bits { 7009 u8 action_type[0x4]; 7010 u8 src_field[0xc]; 7011 u8 reserved_at_10[0x3]; 7012 u8 src_offset[0x5]; 7013 u8 reserved_at_18[0x3]; 7014 u8 length[0x5]; 7015 7016 u8 reserved_at_20[0x4]; 7017 u8 dst_field[0xc]; 7018 u8 reserved_at_30[0x3]; 7019 u8 dst_offset[0x5]; 7020 u8 reserved_at_38[0x8]; 7021 }; 7022 7023 union mlx5_ifc_set_add_copy_action_in_auto_bits { 7024 struct mlx5_ifc_set_action_in_bits set_action_in; 7025 struct mlx5_ifc_add_action_in_bits add_action_in; 7026 struct mlx5_ifc_copy_action_in_bits copy_action_in; 7027 u8 reserved_at_0[0x40]; 7028 }; 7029 7030 enum { 7031 MLX5_ACTION_TYPE_SET = 0x1, 7032 MLX5_ACTION_TYPE_ADD = 0x2, 7033 MLX5_ACTION_TYPE_COPY = 0x3, 7034 }; 7035 7036 enum { 7037 MLX5_ACTION_IN_FIELD_OUT_SMAC_47_16 = 0x1, 7038 MLX5_ACTION_IN_FIELD_OUT_SMAC_15_0 = 0x2, 7039 MLX5_ACTION_IN_FIELD_OUT_ETHERTYPE = 0x3, 7040 MLX5_ACTION_IN_FIELD_OUT_DMAC_47_16 = 0x4, 7041 MLX5_ACTION_IN_FIELD_OUT_DMAC_15_0 = 0x5, 7042 MLX5_ACTION_IN_FIELD_OUT_IP_DSCP = 0x6, 7043 MLX5_ACTION_IN_FIELD_OUT_TCP_FLAGS = 0x7, 7044 MLX5_ACTION_IN_FIELD_OUT_TCP_SPORT = 0x8, 7045 MLX5_ACTION_IN_FIELD_OUT_TCP_DPORT = 0x9, 7046 MLX5_ACTION_IN_FIELD_OUT_IP_TTL = 0xa, 7047 MLX5_ACTION_IN_FIELD_OUT_UDP_SPORT = 0xb, 7048 MLX5_ACTION_IN_FIELD_OUT_UDP_DPORT = 0xc, 7049 MLX5_ACTION_IN_FIELD_OUT_SIPV6_127_96 = 0xd, 7050 MLX5_ACTION_IN_FIELD_OUT_SIPV6_95_64 = 0xe, 7051 MLX5_ACTION_IN_FIELD_OUT_SIPV6_63_32 = 0xf, 7052 MLX5_ACTION_IN_FIELD_OUT_SIPV6_31_0 = 0x10, 7053 MLX5_ACTION_IN_FIELD_OUT_DIPV6_127_96 = 0x11, 7054 MLX5_ACTION_IN_FIELD_OUT_DIPV6_95_64 = 0x12, 7055 MLX5_ACTION_IN_FIELD_OUT_DIPV6_63_32 = 0x13, 7056 MLX5_ACTION_IN_FIELD_OUT_DIPV6_31_0 = 0x14, 7057 MLX5_ACTION_IN_FIELD_OUT_SIPV4 = 0x15, 7058 MLX5_ACTION_IN_FIELD_OUT_DIPV4 = 0x16, 7059 MLX5_ACTION_IN_FIELD_OUT_FIRST_VID = 0x17, 7060 MLX5_ACTION_IN_FIELD_OUT_IPV6_HOPLIMIT = 0x47, 7061 MLX5_ACTION_IN_FIELD_METADATA_REG_A = 0x49, 7062 MLX5_ACTION_IN_FIELD_METADATA_REG_B = 0x50, 7063 MLX5_ACTION_IN_FIELD_METADATA_REG_C_0 = 0x51, 7064 MLX5_ACTION_IN_FIELD_METADATA_REG_C_1 = 0x52, 7065 MLX5_ACTION_IN_FIELD_METADATA_REG_C_2 = 0x53, 7066 MLX5_ACTION_IN_FIELD_METADATA_REG_C_3 = 0x54, 7067 MLX5_ACTION_IN_FIELD_METADATA_REG_C_4 = 0x55, 7068 MLX5_ACTION_IN_FIELD_METADATA_REG_C_5 = 0x56, 7069 MLX5_ACTION_IN_FIELD_METADATA_REG_C_6 = 0x57, 7070 MLX5_ACTION_IN_FIELD_METADATA_REG_C_7 = 0x58, 7071 MLX5_ACTION_IN_FIELD_OUT_TCP_SEQ_NUM = 0x59, 7072 MLX5_ACTION_IN_FIELD_OUT_TCP_ACK_NUM = 0x5B, 7073 MLX5_ACTION_IN_FIELD_IPSEC_SYNDROME = 0x5D, 7074 MLX5_ACTION_IN_FIELD_OUT_EMD_47_32 = 0x6F, 7075 MLX5_ACTION_IN_FIELD_OUT_EMD_31_0 = 0x70, 7076 }; 7077 7078 struct mlx5_ifc_alloc_modify_header_context_out_bits { 7079 u8 status[0x8]; 7080 u8 reserved_at_8[0x18]; 7081 7082 u8 syndrome[0x20]; 7083 7084 u8 modify_header_id[0x20]; 7085 7086 u8 reserved_at_60[0x20]; 7087 }; 7088 7089 struct mlx5_ifc_alloc_modify_header_context_in_bits { 7090 u8 opcode[0x10]; 7091 u8 reserved_at_10[0x10]; 7092 7093 u8 reserved_at_20[0x10]; 7094 u8 op_mod[0x10]; 7095 7096 u8 reserved_at_40[0x20]; 7097 7098 u8 table_type[0x8]; 7099 u8 reserved_at_68[0x10]; 7100 u8 num_of_actions[0x8]; 7101 7102 union mlx5_ifc_set_add_copy_action_in_auto_bits actions[]; 7103 }; 7104 7105 struct mlx5_ifc_dealloc_modify_header_context_out_bits { 7106 u8 status[0x8]; 7107 u8 reserved_at_8[0x18]; 7108 7109 u8 syndrome[0x20]; 7110 7111 u8 reserved_at_40[0x40]; 7112 }; 7113 7114 struct mlx5_ifc_dealloc_modify_header_context_in_bits { 7115 u8 opcode[0x10]; 7116 u8 reserved_at_10[0x10]; 7117 7118 u8 reserved_at_20[0x10]; 7119 u8 op_mod[0x10]; 7120 7121 u8 modify_header_id[0x20]; 7122 7123 u8 reserved_at_60[0x20]; 7124 }; 7125 7126 struct mlx5_ifc_query_modify_header_context_in_bits { 7127 u8 opcode[0x10]; 7128 u8 uid[0x10]; 7129 7130 u8 reserved_at_20[0x10]; 7131 u8 op_mod[0x10]; 7132 7133 u8 modify_header_id[0x20]; 7134 7135 u8 reserved_at_60[0xa0]; 7136 }; 7137 7138 struct mlx5_ifc_query_dct_out_bits { 7139 u8 status[0x8]; 7140 u8 reserved_at_8[0x18]; 7141 7142 u8 syndrome[0x20]; 7143 7144 u8 reserved_at_40[0x40]; 7145 7146 struct mlx5_ifc_dctc_bits dct_context_entry; 7147 7148 u8 reserved_at_280[0x180]; 7149 }; 7150 7151 struct mlx5_ifc_query_dct_in_bits { 7152 u8 opcode[0x10]; 7153 u8 reserved_at_10[0x10]; 7154 7155 u8 reserved_at_20[0x10]; 7156 u8 op_mod[0x10]; 7157 7158 u8 reserved_at_40[0x8]; 7159 u8 dctn[0x18]; 7160 7161 u8 reserved_at_60[0x20]; 7162 }; 7163 7164 struct mlx5_ifc_query_cq_out_bits { 7165 u8 status[0x8]; 7166 u8 reserved_at_8[0x18]; 7167 7168 u8 syndrome[0x20]; 7169 7170 u8 reserved_at_40[0x40]; 7171 7172 struct mlx5_ifc_cqc_bits cq_context; 7173 7174 u8 reserved_at_280[0x600]; 7175 7176 u8 pas[][0x40]; 7177 }; 7178 7179 struct mlx5_ifc_query_cq_in_bits { 7180 u8 opcode[0x10]; 7181 u8 reserved_at_10[0x10]; 7182 7183 u8 reserved_at_20[0x10]; 7184 u8 op_mod[0x10]; 7185 7186 u8 reserved_at_40[0x8]; 7187 u8 cqn[0x18]; 7188 7189 u8 reserved_at_60[0x20]; 7190 }; 7191 7192 struct mlx5_ifc_query_cong_status_out_bits { 7193 u8 status[0x8]; 7194 u8 reserved_at_8[0x18]; 7195 7196 u8 syndrome[0x20]; 7197 7198 u8 reserved_at_40[0x20]; 7199 7200 u8 enable[0x1]; 7201 u8 tag_enable[0x1]; 7202 u8 reserved_at_62[0x1e]; 7203 }; 7204 7205 struct mlx5_ifc_query_cong_status_in_bits { 7206 u8 opcode[0x10]; 7207 u8 reserved_at_10[0x10]; 7208 7209 u8 reserved_at_20[0x10]; 7210 u8 op_mod[0x10]; 7211 7212 u8 reserved_at_40[0x18]; 7213 u8 priority[0x4]; 7214 u8 cong_protocol[0x4]; 7215 7216 u8 reserved_at_60[0x20]; 7217 }; 7218 7219 struct mlx5_ifc_query_cong_statistics_out_bits { 7220 u8 status[0x8]; 7221 u8 reserved_at_8[0x18]; 7222 7223 u8 syndrome[0x20]; 7224 7225 u8 reserved_at_40[0x40]; 7226 7227 u8 rp_cur_flows[0x20]; 7228 7229 u8 sum_flows[0x20]; 7230 7231 u8 rp_cnp_ignored_high[0x20]; 7232 7233 u8 rp_cnp_ignored_low[0x20]; 7234 7235 u8 rp_cnp_handled_high[0x20]; 7236 7237 u8 rp_cnp_handled_low[0x20]; 7238 7239 u8 reserved_at_140[0x100]; 7240 7241 u8 time_stamp_high[0x20]; 7242 7243 u8 time_stamp_low[0x20]; 7244 7245 u8 accumulators_period[0x20]; 7246 7247 u8 np_ecn_marked_roce_packets_high[0x20]; 7248 7249 u8 np_ecn_marked_roce_packets_low[0x20]; 7250 7251 u8 np_cnp_sent_high[0x20]; 7252 7253 u8 np_cnp_sent_low[0x20]; 7254 7255 u8 reserved_at_320[0x560]; 7256 }; 7257 7258 struct mlx5_ifc_query_cong_statistics_in_bits { 7259 u8 opcode[0x10]; 7260 u8 reserved_at_10[0x10]; 7261 7262 u8 reserved_at_20[0x10]; 7263 u8 op_mod[0x10]; 7264 7265 u8 clear[0x1]; 7266 u8 reserved_at_41[0x1f]; 7267 7268 u8 reserved_at_60[0x20]; 7269 }; 7270 7271 struct mlx5_ifc_query_cong_params_out_bits { 7272 u8 status[0x8]; 7273 u8 reserved_at_8[0x18]; 7274 7275 u8 syndrome[0x20]; 7276 7277 u8 reserved_at_40[0x40]; 7278 7279 union mlx5_ifc_cong_control_roce_ecn_auto_bits congestion_parameters; 7280 }; 7281 7282 struct mlx5_ifc_query_cong_params_in_bits { 7283 u8 opcode[0x10]; 7284 u8 reserved_at_10[0x10]; 7285 7286 u8 reserved_at_20[0x10]; 7287 u8 op_mod[0x10]; 7288 7289 u8 reserved_at_40[0x1c]; 7290 u8 cong_protocol[0x4]; 7291 7292 u8 reserved_at_60[0x20]; 7293 }; 7294 7295 struct mlx5_ifc_query_adapter_out_bits { 7296 u8 status[0x8]; 7297 u8 reserved_at_8[0x18]; 7298 7299 u8 syndrome[0x20]; 7300 7301 u8 reserved_at_40[0x40]; 7302 7303 struct mlx5_ifc_query_adapter_param_block_bits query_adapter_struct; 7304 }; 7305 7306 struct mlx5_ifc_query_adapter_in_bits { 7307 u8 opcode[0x10]; 7308 u8 reserved_at_10[0x10]; 7309 7310 u8 reserved_at_20[0x10]; 7311 u8 op_mod[0x10]; 7312 7313 u8 reserved_at_40[0x40]; 7314 }; 7315 7316 struct mlx5_ifc_qp_2rst_out_bits { 7317 u8 status[0x8]; 7318 u8 reserved_at_8[0x18]; 7319 7320 u8 syndrome[0x20]; 7321 7322 u8 reserved_at_40[0x40]; 7323 }; 7324 7325 struct mlx5_ifc_qp_2rst_in_bits { 7326 u8 opcode[0x10]; 7327 u8 uid[0x10]; 7328 7329 u8 reserved_at_20[0x10]; 7330 u8 op_mod[0x10]; 7331 7332 u8 reserved_at_40[0x8]; 7333 u8 qpn[0x18]; 7334 7335 u8 reserved_at_60[0x20]; 7336 }; 7337 7338 struct mlx5_ifc_qp_2err_out_bits { 7339 u8 status[0x8]; 7340 u8 reserved_at_8[0x18]; 7341 7342 u8 syndrome[0x20]; 7343 7344 u8 reserved_at_40[0x40]; 7345 }; 7346 7347 struct mlx5_ifc_qp_2err_in_bits { 7348 u8 opcode[0x10]; 7349 u8 uid[0x10]; 7350 7351 u8 reserved_at_20[0x10]; 7352 u8 op_mod[0x10]; 7353 7354 u8 reserved_at_40[0x8]; 7355 u8 qpn[0x18]; 7356 7357 u8 reserved_at_60[0x20]; 7358 }; 7359 7360 struct mlx5_ifc_page_fault_resume_out_bits { 7361 u8 status[0x8]; 7362 u8 reserved_at_8[0x18]; 7363 7364 u8 syndrome[0x20]; 7365 7366 u8 reserved_at_40[0x40]; 7367 }; 7368 7369 struct mlx5_ifc_page_fault_resume_in_bits { 7370 u8 opcode[0x10]; 7371 u8 reserved_at_10[0x10]; 7372 7373 u8 reserved_at_20[0x10]; 7374 u8 op_mod[0x10]; 7375 7376 u8 error[0x1]; 7377 u8 reserved_at_41[0x4]; 7378 u8 page_fault_type[0x3]; 7379 u8 wq_number[0x18]; 7380 7381 u8 reserved_at_60[0x8]; 7382 u8 token[0x18]; 7383 }; 7384 7385 struct mlx5_ifc_nop_out_bits { 7386 u8 status[0x8]; 7387 u8 reserved_at_8[0x18]; 7388 7389 u8 syndrome[0x20]; 7390 7391 u8 reserved_at_40[0x40]; 7392 }; 7393 7394 struct mlx5_ifc_nop_in_bits { 7395 u8 opcode[0x10]; 7396 u8 reserved_at_10[0x10]; 7397 7398 u8 reserved_at_20[0x10]; 7399 u8 op_mod[0x10]; 7400 7401 u8 reserved_at_40[0x40]; 7402 }; 7403 7404 struct mlx5_ifc_modify_vport_state_out_bits { 7405 u8 status[0x8]; 7406 u8 reserved_at_8[0x18]; 7407 7408 u8 syndrome[0x20]; 7409 7410 u8 reserved_at_40[0x40]; 7411 }; 7412 7413 struct mlx5_ifc_modify_vport_state_in_bits { 7414 u8 opcode[0x10]; 7415 u8 reserved_at_10[0x10]; 7416 7417 u8 reserved_at_20[0x10]; 7418 u8 op_mod[0x10]; 7419 7420 u8 other_vport[0x1]; 7421 u8 reserved_at_41[0xf]; 7422 u8 vport_number[0x10]; 7423 7424 u8 reserved_at_60[0x18]; 7425 u8 admin_state[0x4]; 7426 u8 reserved_at_7c[0x4]; 7427 }; 7428 7429 struct mlx5_ifc_modify_tis_out_bits { 7430 u8 status[0x8]; 7431 u8 reserved_at_8[0x18]; 7432 7433 u8 syndrome[0x20]; 7434 7435 u8 reserved_at_40[0x40]; 7436 }; 7437 7438 struct mlx5_ifc_modify_tis_bitmask_bits { 7439 u8 reserved_at_0[0x20]; 7440 7441 u8 reserved_at_20[0x1d]; 7442 u8 lag_tx_port_affinity[0x1]; 7443 u8 strict_lag_tx_port_affinity[0x1]; 7444 u8 prio[0x1]; 7445 }; 7446 7447 struct mlx5_ifc_modify_tis_in_bits { 7448 u8 opcode[0x10]; 7449 u8 uid[0x10]; 7450 7451 u8 reserved_at_20[0x10]; 7452 u8 op_mod[0x10]; 7453 7454 u8 reserved_at_40[0x8]; 7455 u8 tisn[0x18]; 7456 7457 u8 reserved_at_60[0x20]; 7458 7459 struct mlx5_ifc_modify_tis_bitmask_bits bitmask; 7460 7461 u8 reserved_at_c0[0x40]; 7462 7463 struct mlx5_ifc_tisc_bits ctx; 7464 }; 7465 7466 struct mlx5_ifc_modify_tir_bitmask_bits { 7467 u8 reserved_at_0[0x20]; 7468 7469 u8 reserved_at_20[0x1b]; 7470 u8 self_lb_en[0x1]; 7471 u8 reserved_at_3c[0x1]; 7472 u8 hash[0x1]; 7473 u8 reserved_at_3e[0x1]; 7474 u8 packet_merge[0x1]; 7475 }; 7476 7477 struct mlx5_ifc_modify_tir_out_bits { 7478 u8 status[0x8]; 7479 u8 reserved_at_8[0x18]; 7480 7481 u8 syndrome[0x20]; 7482 7483 u8 reserved_at_40[0x40]; 7484 }; 7485 7486 struct mlx5_ifc_modify_tir_in_bits { 7487 u8 opcode[0x10]; 7488 u8 uid[0x10]; 7489 7490 u8 reserved_at_20[0x10]; 7491 u8 op_mod[0x10]; 7492 7493 u8 reserved_at_40[0x8]; 7494 u8 tirn[0x18]; 7495 7496 u8 reserved_at_60[0x20]; 7497 7498 struct mlx5_ifc_modify_tir_bitmask_bits bitmask; 7499 7500 u8 reserved_at_c0[0x40]; 7501 7502 struct mlx5_ifc_tirc_bits ctx; 7503 }; 7504 7505 struct mlx5_ifc_modify_sq_out_bits { 7506 u8 status[0x8]; 7507 u8 reserved_at_8[0x18]; 7508 7509 u8 syndrome[0x20]; 7510 7511 u8 reserved_at_40[0x40]; 7512 }; 7513 7514 struct mlx5_ifc_modify_sq_in_bits { 7515 u8 opcode[0x10]; 7516 u8 uid[0x10]; 7517 7518 u8 reserved_at_20[0x10]; 7519 u8 op_mod[0x10]; 7520 7521 u8 sq_state[0x4]; 7522 u8 reserved_at_44[0x4]; 7523 u8 sqn[0x18]; 7524 7525 u8 reserved_at_60[0x20]; 7526 7527 u8 modify_bitmask[0x40]; 7528 7529 u8 reserved_at_c0[0x40]; 7530 7531 struct mlx5_ifc_sqc_bits ctx; 7532 }; 7533 7534 struct mlx5_ifc_modify_scheduling_element_out_bits { 7535 u8 status[0x8]; 7536 u8 reserved_at_8[0x18]; 7537 7538 u8 syndrome[0x20]; 7539 7540 u8 reserved_at_40[0x1c0]; 7541 }; 7542 7543 enum { 7544 MODIFY_SCHEDULING_ELEMENT_IN_MODIFY_BITMASK_BW_SHARE = 0x1, 7545 MODIFY_SCHEDULING_ELEMENT_IN_MODIFY_BITMASK_MAX_AVERAGE_BW = 0x2, 7546 }; 7547 7548 struct mlx5_ifc_modify_scheduling_element_in_bits { 7549 u8 opcode[0x10]; 7550 u8 reserved_at_10[0x10]; 7551 7552 u8 reserved_at_20[0x10]; 7553 u8 op_mod[0x10]; 7554 7555 u8 scheduling_hierarchy[0x8]; 7556 u8 reserved_at_48[0x18]; 7557 7558 u8 scheduling_element_id[0x20]; 7559 7560 u8 reserved_at_80[0x20]; 7561 7562 u8 modify_bitmask[0x20]; 7563 7564 u8 reserved_at_c0[0x40]; 7565 7566 struct mlx5_ifc_scheduling_context_bits scheduling_context; 7567 7568 u8 reserved_at_300[0x100]; 7569 }; 7570 7571 struct mlx5_ifc_modify_rqt_out_bits { 7572 u8 status[0x8]; 7573 u8 reserved_at_8[0x18]; 7574 7575 u8 syndrome[0x20]; 7576 7577 u8 reserved_at_40[0x40]; 7578 }; 7579 7580 struct mlx5_ifc_rqt_bitmask_bits { 7581 u8 reserved_at_0[0x20]; 7582 7583 u8 reserved_at_20[0x1f]; 7584 u8 rqn_list[0x1]; 7585 }; 7586 7587 struct mlx5_ifc_modify_rqt_in_bits { 7588 u8 opcode[0x10]; 7589 u8 uid[0x10]; 7590 7591 u8 reserved_at_20[0x10]; 7592 u8 op_mod[0x10]; 7593 7594 u8 reserved_at_40[0x8]; 7595 u8 rqtn[0x18]; 7596 7597 u8 reserved_at_60[0x20]; 7598 7599 struct mlx5_ifc_rqt_bitmask_bits bitmask; 7600 7601 u8 reserved_at_c0[0x40]; 7602 7603 struct mlx5_ifc_rqtc_bits ctx; 7604 }; 7605 7606 struct mlx5_ifc_modify_rq_out_bits { 7607 u8 status[0x8]; 7608 u8 reserved_at_8[0x18]; 7609 7610 u8 syndrome[0x20]; 7611 7612 u8 reserved_at_40[0x40]; 7613 }; 7614 7615 enum { 7616 MLX5_MODIFY_RQ_IN_MODIFY_BITMASK_VSD = 1ULL << 1, 7617 MLX5_MODIFY_RQ_IN_MODIFY_BITMASK_SCATTER_FCS = 1ULL << 2, 7618 MLX5_MODIFY_RQ_IN_MODIFY_BITMASK_RQ_COUNTER_SET_ID = 1ULL << 3, 7619 }; 7620 7621 struct mlx5_ifc_modify_rq_in_bits { 7622 u8 opcode[0x10]; 7623 u8 uid[0x10]; 7624 7625 u8 reserved_at_20[0x10]; 7626 u8 op_mod[0x10]; 7627 7628 u8 rq_state[0x4]; 7629 u8 reserved_at_44[0x4]; 7630 u8 rqn[0x18]; 7631 7632 u8 reserved_at_60[0x20]; 7633 7634 u8 modify_bitmask[0x40]; 7635 7636 u8 reserved_at_c0[0x40]; 7637 7638 struct mlx5_ifc_rqc_bits ctx; 7639 }; 7640 7641 struct mlx5_ifc_modify_rmp_out_bits { 7642 u8 status[0x8]; 7643 u8 reserved_at_8[0x18]; 7644 7645 u8 syndrome[0x20]; 7646 7647 u8 reserved_at_40[0x40]; 7648 }; 7649 7650 struct mlx5_ifc_rmp_bitmask_bits { 7651 u8 reserved_at_0[0x20]; 7652 7653 u8 reserved_at_20[0x1f]; 7654 u8 lwm[0x1]; 7655 }; 7656 7657 struct mlx5_ifc_modify_rmp_in_bits { 7658 u8 opcode[0x10]; 7659 u8 uid[0x10]; 7660 7661 u8 reserved_at_20[0x10]; 7662 u8 op_mod[0x10]; 7663 7664 u8 rmp_state[0x4]; 7665 u8 reserved_at_44[0x4]; 7666 u8 rmpn[0x18]; 7667 7668 u8 reserved_at_60[0x20]; 7669 7670 struct mlx5_ifc_rmp_bitmask_bits bitmask; 7671 7672 u8 reserved_at_c0[0x40]; 7673 7674 struct mlx5_ifc_rmpc_bits ctx; 7675 }; 7676 7677 struct mlx5_ifc_modify_nic_vport_context_out_bits { 7678 u8 status[0x8]; 7679 u8 reserved_at_8[0x18]; 7680 7681 u8 syndrome[0x20]; 7682 7683 u8 reserved_at_40[0x40]; 7684 }; 7685 7686 struct mlx5_ifc_modify_nic_vport_field_select_bits { 7687 u8 reserved_at_0[0x12]; 7688 u8 affiliation[0x1]; 7689 u8 reserved_at_13[0x1]; 7690 u8 disable_uc_local_lb[0x1]; 7691 u8 disable_mc_local_lb[0x1]; 7692 u8 node_guid[0x1]; 7693 u8 port_guid[0x1]; 7694 u8 min_inline[0x1]; 7695 u8 mtu[0x1]; 7696 u8 change_event[0x1]; 7697 u8 promisc[0x1]; 7698 u8 permanent_address[0x1]; 7699 u8 addresses_list[0x1]; 7700 u8 roce_en[0x1]; 7701 u8 reserved_at_1f[0x1]; 7702 }; 7703 7704 struct mlx5_ifc_modify_nic_vport_context_in_bits { 7705 u8 opcode[0x10]; 7706 u8 reserved_at_10[0x10]; 7707 7708 u8 reserved_at_20[0x10]; 7709 u8 op_mod[0x10]; 7710 7711 u8 other_vport[0x1]; 7712 u8 reserved_at_41[0xf]; 7713 u8 vport_number[0x10]; 7714 7715 struct mlx5_ifc_modify_nic_vport_field_select_bits field_select; 7716 7717 u8 reserved_at_80[0x780]; 7718 7719 struct mlx5_ifc_nic_vport_context_bits nic_vport_context; 7720 }; 7721 7722 struct mlx5_ifc_modify_hca_vport_context_out_bits { 7723 u8 status[0x8]; 7724 u8 reserved_at_8[0x18]; 7725 7726 u8 syndrome[0x20]; 7727 7728 u8 reserved_at_40[0x40]; 7729 }; 7730 7731 struct mlx5_ifc_modify_hca_vport_context_in_bits { 7732 u8 opcode[0x10]; 7733 u8 reserved_at_10[0x10]; 7734 7735 u8 reserved_at_20[0x10]; 7736 u8 op_mod[0x10]; 7737 7738 u8 other_vport[0x1]; 7739 u8 reserved_at_41[0xb]; 7740 u8 port_num[0x4]; 7741 u8 vport_number[0x10]; 7742 7743 u8 reserved_at_60[0x20]; 7744 7745 struct mlx5_ifc_hca_vport_context_bits hca_vport_context; 7746 }; 7747 7748 struct mlx5_ifc_modify_cq_out_bits { 7749 u8 status[0x8]; 7750 u8 reserved_at_8[0x18]; 7751 7752 u8 syndrome[0x20]; 7753 7754 u8 reserved_at_40[0x40]; 7755 }; 7756 7757 enum { 7758 MLX5_MODIFY_CQ_IN_OP_MOD_MODIFY_CQ = 0x0, 7759 MLX5_MODIFY_CQ_IN_OP_MOD_RESIZE_CQ = 0x1, 7760 }; 7761 7762 struct mlx5_ifc_modify_cq_in_bits { 7763 u8 opcode[0x10]; 7764 u8 uid[0x10]; 7765 7766 u8 reserved_at_20[0x10]; 7767 u8 op_mod[0x10]; 7768 7769 u8 reserved_at_40[0x8]; 7770 u8 cqn[0x18]; 7771 7772 union mlx5_ifc_modify_field_select_resize_field_select_auto_bits modify_field_select_resize_field_select; 7773 7774 struct mlx5_ifc_cqc_bits cq_context; 7775 7776 u8 reserved_at_280[0x60]; 7777 7778 u8 cq_umem_valid[0x1]; 7779 u8 reserved_at_2e1[0x1f]; 7780 7781 u8 reserved_at_300[0x580]; 7782 7783 u8 pas[][0x40]; 7784 }; 7785 7786 struct mlx5_ifc_modify_cong_status_out_bits { 7787 u8 status[0x8]; 7788 u8 reserved_at_8[0x18]; 7789 7790 u8 syndrome[0x20]; 7791 7792 u8 reserved_at_40[0x40]; 7793 }; 7794 7795 struct mlx5_ifc_modify_cong_status_in_bits { 7796 u8 opcode[0x10]; 7797 u8 reserved_at_10[0x10]; 7798 7799 u8 reserved_at_20[0x10]; 7800 u8 op_mod[0x10]; 7801 7802 u8 reserved_at_40[0x18]; 7803 u8 priority[0x4]; 7804 u8 cong_protocol[0x4]; 7805 7806 u8 enable[0x1]; 7807 u8 tag_enable[0x1]; 7808 u8 reserved_at_62[0x1e]; 7809 }; 7810 7811 struct mlx5_ifc_modify_cong_params_out_bits { 7812 u8 status[0x8]; 7813 u8 reserved_at_8[0x18]; 7814 7815 u8 syndrome[0x20]; 7816 7817 u8 reserved_at_40[0x40]; 7818 }; 7819 7820 struct mlx5_ifc_modify_cong_params_in_bits { 7821 u8 opcode[0x10]; 7822 u8 reserved_at_10[0x10]; 7823 7824 u8 reserved_at_20[0x10]; 7825 u8 op_mod[0x10]; 7826 7827 u8 reserved_at_40[0x1c]; 7828 u8 cong_protocol[0x4]; 7829 7830 union mlx5_ifc_field_select_802_1_r_roce_auto_bits field_select; 7831 7832 u8 reserved_at_80[0x80]; 7833 7834 union mlx5_ifc_cong_control_roce_ecn_auto_bits congestion_parameters; 7835 }; 7836 7837 struct mlx5_ifc_manage_pages_out_bits { 7838 u8 status[0x8]; 7839 u8 reserved_at_8[0x18]; 7840 7841 u8 syndrome[0x20]; 7842 7843 u8 output_num_entries[0x20]; 7844 7845 u8 reserved_at_60[0x20]; 7846 7847 u8 pas[][0x40]; 7848 }; 7849 7850 enum { 7851 MLX5_MANAGE_PAGES_IN_OP_MOD_ALLOCATION_FAIL = 0x0, 7852 MLX5_MANAGE_PAGES_IN_OP_MOD_ALLOCATION_SUCCESS = 0x1, 7853 MLX5_MANAGE_PAGES_IN_OP_MOD_HCA_RETURN_PAGES = 0x2, 7854 }; 7855 7856 struct mlx5_ifc_manage_pages_in_bits { 7857 u8 opcode[0x10]; 7858 u8 reserved_at_10[0x10]; 7859 7860 u8 reserved_at_20[0x10]; 7861 u8 op_mod[0x10]; 7862 7863 u8 embedded_cpu_function[0x1]; 7864 u8 reserved_at_41[0xf]; 7865 u8 function_id[0x10]; 7866 7867 u8 input_num_entries[0x20]; 7868 7869 u8 pas[][0x40]; 7870 }; 7871 7872 struct mlx5_ifc_mad_ifc_out_bits { 7873 u8 status[0x8]; 7874 u8 reserved_at_8[0x18]; 7875 7876 u8 syndrome[0x20]; 7877 7878 u8 reserved_at_40[0x40]; 7879 7880 u8 response_mad_packet[256][0x8]; 7881 }; 7882 7883 struct mlx5_ifc_mad_ifc_in_bits { 7884 u8 opcode[0x10]; 7885 u8 reserved_at_10[0x10]; 7886 7887 u8 reserved_at_20[0x10]; 7888 u8 op_mod[0x10]; 7889 7890 u8 remote_lid[0x10]; 7891 u8 plane_index[0x8]; 7892 u8 port[0x8]; 7893 7894 u8 reserved_at_60[0x20]; 7895 7896 u8 mad[256][0x8]; 7897 }; 7898 7899 struct mlx5_ifc_init_hca_out_bits { 7900 u8 status[0x8]; 7901 u8 reserved_at_8[0x18]; 7902 7903 u8 syndrome[0x20]; 7904 7905 u8 reserved_at_40[0x40]; 7906 }; 7907 7908 struct mlx5_ifc_init_hca_in_bits { 7909 u8 opcode[0x10]; 7910 u8 reserved_at_10[0x10]; 7911 7912 u8 reserved_at_20[0x10]; 7913 u8 op_mod[0x10]; 7914 7915 u8 reserved_at_40[0x20]; 7916 7917 u8 reserved_at_60[0x2]; 7918 u8 sw_vhca_id[0xe]; 7919 u8 reserved_at_70[0x10]; 7920 7921 u8 sw_owner_id[4][0x20]; 7922 }; 7923 7924 struct mlx5_ifc_init2rtr_qp_out_bits { 7925 u8 status[0x8]; 7926 u8 reserved_at_8[0x18]; 7927 7928 u8 syndrome[0x20]; 7929 7930 u8 reserved_at_40[0x20]; 7931 u8 ece[0x20]; 7932 }; 7933 7934 struct mlx5_ifc_init2rtr_qp_in_bits { 7935 u8 opcode[0x10]; 7936 u8 uid[0x10]; 7937 7938 u8 reserved_at_20[0x10]; 7939 u8 op_mod[0x10]; 7940 7941 u8 reserved_at_40[0x8]; 7942 u8 qpn[0x18]; 7943 7944 u8 reserved_at_60[0x20]; 7945 7946 u8 opt_param_mask[0x20]; 7947 7948 u8 ece[0x20]; 7949 7950 struct mlx5_ifc_qpc_bits qpc; 7951 7952 u8 reserved_at_800[0x80]; 7953 }; 7954 7955 struct mlx5_ifc_init2init_qp_out_bits { 7956 u8 status[0x8]; 7957 u8 reserved_at_8[0x18]; 7958 7959 u8 syndrome[0x20]; 7960 7961 u8 reserved_at_40[0x20]; 7962 u8 ece[0x20]; 7963 }; 7964 7965 struct mlx5_ifc_init2init_qp_in_bits { 7966 u8 opcode[0x10]; 7967 u8 uid[0x10]; 7968 7969 u8 reserved_at_20[0x10]; 7970 u8 op_mod[0x10]; 7971 7972 u8 reserved_at_40[0x8]; 7973 u8 qpn[0x18]; 7974 7975 u8 reserved_at_60[0x20]; 7976 7977 u8 opt_param_mask[0x20]; 7978 7979 u8 ece[0x20]; 7980 7981 struct mlx5_ifc_qpc_bits qpc; 7982 7983 u8 reserved_at_800[0x80]; 7984 }; 7985 7986 struct mlx5_ifc_get_dropped_packet_log_out_bits { 7987 u8 status[0x8]; 7988 u8 reserved_at_8[0x18]; 7989 7990 u8 syndrome[0x20]; 7991 7992 u8 reserved_at_40[0x40]; 7993 7994 u8 packet_headers_log[128][0x8]; 7995 7996 u8 packet_syndrome[64][0x8]; 7997 }; 7998 7999 struct mlx5_ifc_get_dropped_packet_log_in_bits { 8000 u8 opcode[0x10]; 8001 u8 reserved_at_10[0x10]; 8002 8003 u8 reserved_at_20[0x10]; 8004 u8 op_mod[0x10]; 8005 8006 u8 reserved_at_40[0x40]; 8007 }; 8008 8009 struct mlx5_ifc_gen_eqe_in_bits { 8010 u8 opcode[0x10]; 8011 u8 reserved_at_10[0x10]; 8012 8013 u8 reserved_at_20[0x10]; 8014 u8 op_mod[0x10]; 8015 8016 u8 reserved_at_40[0x18]; 8017 u8 eq_number[0x8]; 8018 8019 u8 reserved_at_60[0x20]; 8020 8021 u8 eqe[64][0x8]; 8022 }; 8023 8024 struct mlx5_ifc_gen_eq_out_bits { 8025 u8 status[0x8]; 8026 u8 reserved_at_8[0x18]; 8027 8028 u8 syndrome[0x20]; 8029 8030 u8 reserved_at_40[0x40]; 8031 }; 8032 8033 struct mlx5_ifc_enable_hca_out_bits { 8034 u8 status[0x8]; 8035 u8 reserved_at_8[0x18]; 8036 8037 u8 syndrome[0x20]; 8038 8039 u8 reserved_at_40[0x20]; 8040 }; 8041 8042 struct mlx5_ifc_enable_hca_in_bits { 8043 u8 opcode[0x10]; 8044 u8 reserved_at_10[0x10]; 8045 8046 u8 reserved_at_20[0x10]; 8047 u8 op_mod[0x10]; 8048 8049 u8 embedded_cpu_function[0x1]; 8050 u8 reserved_at_41[0xf]; 8051 u8 function_id[0x10]; 8052 8053 u8 reserved_at_60[0x20]; 8054 }; 8055 8056 struct mlx5_ifc_drain_dct_out_bits { 8057 u8 status[0x8]; 8058 u8 reserved_at_8[0x18]; 8059 8060 u8 syndrome[0x20]; 8061 8062 u8 reserved_at_40[0x40]; 8063 }; 8064 8065 struct mlx5_ifc_drain_dct_in_bits { 8066 u8 opcode[0x10]; 8067 u8 uid[0x10]; 8068 8069 u8 reserved_at_20[0x10]; 8070 u8 op_mod[0x10]; 8071 8072 u8 reserved_at_40[0x8]; 8073 u8 dctn[0x18]; 8074 8075 u8 reserved_at_60[0x20]; 8076 }; 8077 8078 struct mlx5_ifc_disable_hca_out_bits { 8079 u8 status[0x8]; 8080 u8 reserved_at_8[0x18]; 8081 8082 u8 syndrome[0x20]; 8083 8084 u8 reserved_at_40[0x20]; 8085 }; 8086 8087 struct mlx5_ifc_disable_hca_in_bits { 8088 u8 opcode[0x10]; 8089 u8 reserved_at_10[0x10]; 8090 8091 u8 reserved_at_20[0x10]; 8092 u8 op_mod[0x10]; 8093 8094 u8 embedded_cpu_function[0x1]; 8095 u8 reserved_at_41[0xf]; 8096 u8 function_id[0x10]; 8097 8098 u8 reserved_at_60[0x20]; 8099 }; 8100 8101 struct mlx5_ifc_detach_from_mcg_out_bits { 8102 u8 status[0x8]; 8103 u8 reserved_at_8[0x18]; 8104 8105 u8 syndrome[0x20]; 8106 8107 u8 reserved_at_40[0x40]; 8108 }; 8109 8110 struct mlx5_ifc_detach_from_mcg_in_bits { 8111 u8 opcode[0x10]; 8112 u8 uid[0x10]; 8113 8114 u8 reserved_at_20[0x10]; 8115 u8 op_mod[0x10]; 8116 8117 u8 reserved_at_40[0x8]; 8118 u8 qpn[0x18]; 8119 8120 u8 reserved_at_60[0x20]; 8121 8122 u8 multicast_gid[16][0x8]; 8123 }; 8124 8125 struct mlx5_ifc_destroy_xrq_out_bits { 8126 u8 status[0x8]; 8127 u8 reserved_at_8[0x18]; 8128 8129 u8 syndrome[0x20]; 8130 8131 u8 reserved_at_40[0x40]; 8132 }; 8133 8134 struct mlx5_ifc_destroy_xrq_in_bits { 8135 u8 opcode[0x10]; 8136 u8 uid[0x10]; 8137 8138 u8 reserved_at_20[0x10]; 8139 u8 op_mod[0x10]; 8140 8141 u8 reserved_at_40[0x8]; 8142 u8 xrqn[0x18]; 8143 8144 u8 reserved_at_60[0x20]; 8145 }; 8146 8147 struct mlx5_ifc_destroy_xrc_srq_out_bits { 8148 u8 status[0x8]; 8149 u8 reserved_at_8[0x18]; 8150 8151 u8 syndrome[0x20]; 8152 8153 u8 reserved_at_40[0x40]; 8154 }; 8155 8156 struct mlx5_ifc_destroy_xrc_srq_in_bits { 8157 u8 opcode[0x10]; 8158 u8 uid[0x10]; 8159 8160 u8 reserved_at_20[0x10]; 8161 u8 op_mod[0x10]; 8162 8163 u8 reserved_at_40[0x8]; 8164 u8 xrc_srqn[0x18]; 8165 8166 u8 reserved_at_60[0x20]; 8167 }; 8168 8169 struct mlx5_ifc_destroy_tis_out_bits { 8170 u8 status[0x8]; 8171 u8 reserved_at_8[0x18]; 8172 8173 u8 syndrome[0x20]; 8174 8175 u8 reserved_at_40[0x40]; 8176 }; 8177 8178 struct mlx5_ifc_destroy_tis_in_bits { 8179 u8 opcode[0x10]; 8180 u8 uid[0x10]; 8181 8182 u8 reserved_at_20[0x10]; 8183 u8 op_mod[0x10]; 8184 8185 u8 reserved_at_40[0x8]; 8186 u8 tisn[0x18]; 8187 8188 u8 reserved_at_60[0x20]; 8189 }; 8190 8191 struct mlx5_ifc_destroy_tir_out_bits { 8192 u8 status[0x8]; 8193 u8 reserved_at_8[0x18]; 8194 8195 u8 syndrome[0x20]; 8196 8197 u8 reserved_at_40[0x40]; 8198 }; 8199 8200 struct mlx5_ifc_destroy_tir_in_bits { 8201 u8 opcode[0x10]; 8202 u8 uid[0x10]; 8203 8204 u8 reserved_at_20[0x10]; 8205 u8 op_mod[0x10]; 8206 8207 u8 reserved_at_40[0x8]; 8208 u8 tirn[0x18]; 8209 8210 u8 reserved_at_60[0x20]; 8211 }; 8212 8213 struct mlx5_ifc_destroy_srq_out_bits { 8214 u8 status[0x8]; 8215 u8 reserved_at_8[0x18]; 8216 8217 u8 syndrome[0x20]; 8218 8219 u8 reserved_at_40[0x40]; 8220 }; 8221 8222 struct mlx5_ifc_destroy_srq_in_bits { 8223 u8 opcode[0x10]; 8224 u8 uid[0x10]; 8225 8226 u8 reserved_at_20[0x10]; 8227 u8 op_mod[0x10]; 8228 8229 u8 reserved_at_40[0x8]; 8230 u8 srqn[0x18]; 8231 8232 u8 reserved_at_60[0x20]; 8233 }; 8234 8235 struct mlx5_ifc_destroy_sq_out_bits { 8236 u8 status[0x8]; 8237 u8 reserved_at_8[0x18]; 8238 8239 u8 syndrome[0x20]; 8240 8241 u8 reserved_at_40[0x40]; 8242 }; 8243 8244 struct mlx5_ifc_destroy_sq_in_bits { 8245 u8 opcode[0x10]; 8246 u8 uid[0x10]; 8247 8248 u8 reserved_at_20[0x10]; 8249 u8 op_mod[0x10]; 8250 8251 u8 reserved_at_40[0x8]; 8252 u8 sqn[0x18]; 8253 8254 u8 reserved_at_60[0x20]; 8255 }; 8256 8257 struct mlx5_ifc_destroy_scheduling_element_out_bits { 8258 u8 status[0x8]; 8259 u8 reserved_at_8[0x18]; 8260 8261 u8 syndrome[0x20]; 8262 8263 u8 reserved_at_40[0x1c0]; 8264 }; 8265 8266 struct mlx5_ifc_destroy_scheduling_element_in_bits { 8267 u8 opcode[0x10]; 8268 u8 reserved_at_10[0x10]; 8269 8270 u8 reserved_at_20[0x10]; 8271 u8 op_mod[0x10]; 8272 8273 u8 scheduling_hierarchy[0x8]; 8274 u8 reserved_at_48[0x18]; 8275 8276 u8 scheduling_element_id[0x20]; 8277 8278 u8 reserved_at_80[0x180]; 8279 }; 8280 8281 struct mlx5_ifc_destroy_rqt_out_bits { 8282 u8 status[0x8]; 8283 u8 reserved_at_8[0x18]; 8284 8285 u8 syndrome[0x20]; 8286 8287 u8 reserved_at_40[0x40]; 8288 }; 8289 8290 struct mlx5_ifc_destroy_rqt_in_bits { 8291 u8 opcode[0x10]; 8292 u8 uid[0x10]; 8293 8294 u8 reserved_at_20[0x10]; 8295 u8 op_mod[0x10]; 8296 8297 u8 reserved_at_40[0x8]; 8298 u8 rqtn[0x18]; 8299 8300 u8 reserved_at_60[0x20]; 8301 }; 8302 8303 struct mlx5_ifc_destroy_rq_out_bits { 8304 u8 status[0x8]; 8305 u8 reserved_at_8[0x18]; 8306 8307 u8 syndrome[0x20]; 8308 8309 u8 reserved_at_40[0x40]; 8310 }; 8311 8312 struct mlx5_ifc_destroy_rq_in_bits { 8313 u8 opcode[0x10]; 8314 u8 uid[0x10]; 8315 8316 u8 reserved_at_20[0x10]; 8317 u8 op_mod[0x10]; 8318 8319 u8 reserved_at_40[0x8]; 8320 u8 rqn[0x18]; 8321 8322 u8 reserved_at_60[0x20]; 8323 }; 8324 8325 struct mlx5_ifc_set_delay_drop_params_in_bits { 8326 u8 opcode[0x10]; 8327 u8 reserved_at_10[0x10]; 8328 8329 u8 reserved_at_20[0x10]; 8330 u8 op_mod[0x10]; 8331 8332 u8 reserved_at_40[0x20]; 8333 8334 u8 reserved_at_60[0x10]; 8335 u8 delay_drop_timeout[0x10]; 8336 }; 8337 8338 struct mlx5_ifc_set_delay_drop_params_out_bits { 8339 u8 status[0x8]; 8340 u8 reserved_at_8[0x18]; 8341 8342 u8 syndrome[0x20]; 8343 8344 u8 reserved_at_40[0x40]; 8345 }; 8346 8347 struct mlx5_ifc_destroy_rmp_out_bits { 8348 u8 status[0x8]; 8349 u8 reserved_at_8[0x18]; 8350 8351 u8 syndrome[0x20]; 8352 8353 u8 reserved_at_40[0x40]; 8354 }; 8355 8356 struct mlx5_ifc_destroy_rmp_in_bits { 8357 u8 opcode[0x10]; 8358 u8 uid[0x10]; 8359 8360 u8 reserved_at_20[0x10]; 8361 u8 op_mod[0x10]; 8362 8363 u8 reserved_at_40[0x8]; 8364 u8 rmpn[0x18]; 8365 8366 u8 reserved_at_60[0x20]; 8367 }; 8368 8369 struct mlx5_ifc_destroy_qp_out_bits { 8370 u8 status[0x8]; 8371 u8 reserved_at_8[0x18]; 8372 8373 u8 syndrome[0x20]; 8374 8375 u8 reserved_at_40[0x40]; 8376 }; 8377 8378 struct mlx5_ifc_destroy_qp_in_bits { 8379 u8 opcode[0x10]; 8380 u8 uid[0x10]; 8381 8382 u8 reserved_at_20[0x10]; 8383 u8 op_mod[0x10]; 8384 8385 u8 reserved_at_40[0x8]; 8386 u8 qpn[0x18]; 8387 8388 u8 reserved_at_60[0x20]; 8389 }; 8390 8391 struct mlx5_ifc_destroy_psv_out_bits { 8392 u8 status[0x8]; 8393 u8 reserved_at_8[0x18]; 8394 8395 u8 syndrome[0x20]; 8396 8397 u8 reserved_at_40[0x40]; 8398 }; 8399 8400 struct mlx5_ifc_destroy_psv_in_bits { 8401 u8 opcode[0x10]; 8402 u8 reserved_at_10[0x10]; 8403 8404 u8 reserved_at_20[0x10]; 8405 u8 op_mod[0x10]; 8406 8407 u8 reserved_at_40[0x8]; 8408 u8 psvn[0x18]; 8409 8410 u8 reserved_at_60[0x20]; 8411 }; 8412 8413 struct mlx5_ifc_destroy_mkey_out_bits { 8414 u8 status[0x8]; 8415 u8 reserved_at_8[0x18]; 8416 8417 u8 syndrome[0x20]; 8418 8419 u8 reserved_at_40[0x40]; 8420 }; 8421 8422 struct mlx5_ifc_destroy_mkey_in_bits { 8423 u8 opcode[0x10]; 8424 u8 uid[0x10]; 8425 8426 u8 reserved_at_20[0x10]; 8427 u8 op_mod[0x10]; 8428 8429 u8 reserved_at_40[0x8]; 8430 u8 mkey_index[0x18]; 8431 8432 u8 reserved_at_60[0x20]; 8433 }; 8434 8435 struct mlx5_ifc_destroy_flow_table_out_bits { 8436 u8 status[0x8]; 8437 u8 reserved_at_8[0x18]; 8438 8439 u8 syndrome[0x20]; 8440 8441 u8 reserved_at_40[0x40]; 8442 }; 8443 8444 struct mlx5_ifc_destroy_flow_table_in_bits { 8445 u8 opcode[0x10]; 8446 u8 reserved_at_10[0x10]; 8447 8448 u8 reserved_at_20[0x10]; 8449 u8 op_mod[0x10]; 8450 8451 u8 other_vport[0x1]; 8452 u8 reserved_at_41[0xf]; 8453 u8 vport_number[0x10]; 8454 8455 u8 reserved_at_60[0x20]; 8456 8457 u8 table_type[0x8]; 8458 u8 reserved_at_88[0x18]; 8459 8460 u8 reserved_at_a0[0x8]; 8461 u8 table_id[0x18]; 8462 8463 u8 reserved_at_c0[0x140]; 8464 }; 8465 8466 struct mlx5_ifc_destroy_flow_group_out_bits { 8467 u8 status[0x8]; 8468 u8 reserved_at_8[0x18]; 8469 8470 u8 syndrome[0x20]; 8471 8472 u8 reserved_at_40[0x40]; 8473 }; 8474 8475 struct mlx5_ifc_destroy_flow_group_in_bits { 8476 u8 opcode[0x10]; 8477 u8 reserved_at_10[0x10]; 8478 8479 u8 reserved_at_20[0x10]; 8480 u8 op_mod[0x10]; 8481 8482 u8 other_vport[0x1]; 8483 u8 reserved_at_41[0xf]; 8484 u8 vport_number[0x10]; 8485 8486 u8 reserved_at_60[0x20]; 8487 8488 u8 table_type[0x8]; 8489 u8 reserved_at_88[0x18]; 8490 8491 u8 reserved_at_a0[0x8]; 8492 u8 table_id[0x18]; 8493 8494 u8 group_id[0x20]; 8495 8496 u8 reserved_at_e0[0x120]; 8497 }; 8498 8499 struct mlx5_ifc_destroy_eq_out_bits { 8500 u8 status[0x8]; 8501 u8 reserved_at_8[0x18]; 8502 8503 u8 syndrome[0x20]; 8504 8505 u8 reserved_at_40[0x40]; 8506 }; 8507 8508 struct mlx5_ifc_destroy_eq_in_bits { 8509 u8 opcode[0x10]; 8510 u8 reserved_at_10[0x10]; 8511 8512 u8 reserved_at_20[0x10]; 8513 u8 op_mod[0x10]; 8514 8515 u8 reserved_at_40[0x18]; 8516 u8 eq_number[0x8]; 8517 8518 u8 reserved_at_60[0x20]; 8519 }; 8520 8521 struct mlx5_ifc_destroy_dct_out_bits { 8522 u8 status[0x8]; 8523 u8 reserved_at_8[0x18]; 8524 8525 u8 syndrome[0x20]; 8526 8527 u8 reserved_at_40[0x40]; 8528 }; 8529 8530 struct mlx5_ifc_destroy_dct_in_bits { 8531 u8 opcode[0x10]; 8532 u8 uid[0x10]; 8533 8534 u8 reserved_at_20[0x10]; 8535 u8 op_mod[0x10]; 8536 8537 u8 reserved_at_40[0x8]; 8538 u8 dctn[0x18]; 8539 8540 u8 reserved_at_60[0x20]; 8541 }; 8542 8543 struct mlx5_ifc_destroy_cq_out_bits { 8544 u8 status[0x8]; 8545 u8 reserved_at_8[0x18]; 8546 8547 u8 syndrome[0x20]; 8548 8549 u8 reserved_at_40[0x40]; 8550 }; 8551 8552 struct mlx5_ifc_destroy_cq_in_bits { 8553 u8 opcode[0x10]; 8554 u8 uid[0x10]; 8555 8556 u8 reserved_at_20[0x10]; 8557 u8 op_mod[0x10]; 8558 8559 u8 reserved_at_40[0x8]; 8560 u8 cqn[0x18]; 8561 8562 u8 reserved_at_60[0x20]; 8563 }; 8564 8565 struct mlx5_ifc_delete_vxlan_udp_dport_out_bits { 8566 u8 status[0x8]; 8567 u8 reserved_at_8[0x18]; 8568 8569 u8 syndrome[0x20]; 8570 8571 u8 reserved_at_40[0x40]; 8572 }; 8573 8574 struct mlx5_ifc_delete_vxlan_udp_dport_in_bits { 8575 u8 opcode[0x10]; 8576 u8 reserved_at_10[0x10]; 8577 8578 u8 reserved_at_20[0x10]; 8579 u8 op_mod[0x10]; 8580 8581 u8 reserved_at_40[0x20]; 8582 8583 u8 reserved_at_60[0x10]; 8584 u8 vxlan_udp_port[0x10]; 8585 }; 8586 8587 struct mlx5_ifc_delete_l2_table_entry_out_bits { 8588 u8 status[0x8]; 8589 u8 reserved_at_8[0x18]; 8590 8591 u8 syndrome[0x20]; 8592 8593 u8 reserved_at_40[0x40]; 8594 }; 8595 8596 struct mlx5_ifc_delete_l2_table_entry_in_bits { 8597 u8 opcode[0x10]; 8598 u8 reserved_at_10[0x10]; 8599 8600 u8 reserved_at_20[0x10]; 8601 u8 op_mod[0x10]; 8602 8603 u8 reserved_at_40[0x60]; 8604 8605 u8 reserved_at_a0[0x8]; 8606 u8 table_index[0x18]; 8607 8608 u8 reserved_at_c0[0x140]; 8609 }; 8610 8611 struct mlx5_ifc_delete_fte_out_bits { 8612 u8 status[0x8]; 8613 u8 reserved_at_8[0x18]; 8614 8615 u8 syndrome[0x20]; 8616 8617 u8 reserved_at_40[0x40]; 8618 }; 8619 8620 struct mlx5_ifc_delete_fte_in_bits { 8621 u8 opcode[0x10]; 8622 u8 reserved_at_10[0x10]; 8623 8624 u8 reserved_at_20[0x10]; 8625 u8 op_mod[0x10]; 8626 8627 u8 other_vport[0x1]; 8628 u8 reserved_at_41[0xf]; 8629 u8 vport_number[0x10]; 8630 8631 u8 reserved_at_60[0x20]; 8632 8633 u8 table_type[0x8]; 8634 u8 reserved_at_88[0x18]; 8635 8636 u8 reserved_at_a0[0x8]; 8637 u8 table_id[0x18]; 8638 8639 u8 reserved_at_c0[0x40]; 8640 8641 u8 flow_index[0x20]; 8642 8643 u8 reserved_at_120[0xe0]; 8644 }; 8645 8646 struct mlx5_ifc_dealloc_xrcd_out_bits { 8647 u8 status[0x8]; 8648 u8 reserved_at_8[0x18]; 8649 8650 u8 syndrome[0x20]; 8651 8652 u8 reserved_at_40[0x40]; 8653 }; 8654 8655 struct mlx5_ifc_dealloc_xrcd_in_bits { 8656 u8 opcode[0x10]; 8657 u8 uid[0x10]; 8658 8659 u8 reserved_at_20[0x10]; 8660 u8 op_mod[0x10]; 8661 8662 u8 reserved_at_40[0x8]; 8663 u8 xrcd[0x18]; 8664 8665 u8 reserved_at_60[0x20]; 8666 }; 8667 8668 struct mlx5_ifc_dealloc_uar_out_bits { 8669 u8 status[0x8]; 8670 u8 reserved_at_8[0x18]; 8671 8672 u8 syndrome[0x20]; 8673 8674 u8 reserved_at_40[0x40]; 8675 }; 8676 8677 struct mlx5_ifc_dealloc_uar_in_bits { 8678 u8 opcode[0x10]; 8679 u8 uid[0x10]; 8680 8681 u8 reserved_at_20[0x10]; 8682 u8 op_mod[0x10]; 8683 8684 u8 reserved_at_40[0x8]; 8685 u8 uar[0x18]; 8686 8687 u8 reserved_at_60[0x20]; 8688 }; 8689 8690 struct mlx5_ifc_dealloc_transport_domain_out_bits { 8691 u8 status[0x8]; 8692 u8 reserved_at_8[0x18]; 8693 8694 u8 syndrome[0x20]; 8695 8696 u8 reserved_at_40[0x40]; 8697 }; 8698 8699 struct mlx5_ifc_dealloc_transport_domain_in_bits { 8700 u8 opcode[0x10]; 8701 u8 uid[0x10]; 8702 8703 u8 reserved_at_20[0x10]; 8704 u8 op_mod[0x10]; 8705 8706 u8 reserved_at_40[0x8]; 8707 u8 transport_domain[0x18]; 8708 8709 u8 reserved_at_60[0x20]; 8710 }; 8711 8712 struct mlx5_ifc_dealloc_q_counter_out_bits { 8713 u8 status[0x8]; 8714 u8 reserved_at_8[0x18]; 8715 8716 u8 syndrome[0x20]; 8717 8718 u8 reserved_at_40[0x40]; 8719 }; 8720 8721 struct mlx5_ifc_dealloc_q_counter_in_bits { 8722 u8 opcode[0x10]; 8723 u8 reserved_at_10[0x10]; 8724 8725 u8 reserved_at_20[0x10]; 8726 u8 op_mod[0x10]; 8727 8728 u8 reserved_at_40[0x18]; 8729 u8 counter_set_id[0x8]; 8730 8731 u8 reserved_at_60[0x20]; 8732 }; 8733 8734 struct mlx5_ifc_dealloc_pd_out_bits { 8735 u8 status[0x8]; 8736 u8 reserved_at_8[0x18]; 8737 8738 u8 syndrome[0x20]; 8739 8740 u8 reserved_at_40[0x40]; 8741 }; 8742 8743 struct mlx5_ifc_dealloc_pd_in_bits { 8744 u8 opcode[0x10]; 8745 u8 uid[0x10]; 8746 8747 u8 reserved_at_20[0x10]; 8748 u8 op_mod[0x10]; 8749 8750 u8 reserved_at_40[0x8]; 8751 u8 pd[0x18]; 8752 8753 u8 reserved_at_60[0x20]; 8754 }; 8755 8756 struct mlx5_ifc_dealloc_flow_counter_out_bits { 8757 u8 status[0x8]; 8758 u8 reserved_at_8[0x18]; 8759 8760 u8 syndrome[0x20]; 8761 8762 u8 reserved_at_40[0x40]; 8763 }; 8764 8765 struct mlx5_ifc_dealloc_flow_counter_in_bits { 8766 u8 opcode[0x10]; 8767 u8 reserved_at_10[0x10]; 8768 8769 u8 reserved_at_20[0x10]; 8770 u8 op_mod[0x10]; 8771 8772 u8 flow_counter_id[0x20]; 8773 8774 u8 reserved_at_60[0x20]; 8775 }; 8776 8777 struct mlx5_ifc_create_xrq_out_bits { 8778 u8 status[0x8]; 8779 u8 reserved_at_8[0x18]; 8780 8781 u8 syndrome[0x20]; 8782 8783 u8 reserved_at_40[0x8]; 8784 u8 xrqn[0x18]; 8785 8786 u8 reserved_at_60[0x20]; 8787 }; 8788 8789 struct mlx5_ifc_create_xrq_in_bits { 8790 u8 opcode[0x10]; 8791 u8 uid[0x10]; 8792 8793 u8 reserved_at_20[0x10]; 8794 u8 op_mod[0x10]; 8795 8796 u8 reserved_at_40[0x40]; 8797 8798 struct mlx5_ifc_xrqc_bits xrq_context; 8799 }; 8800 8801 struct mlx5_ifc_create_xrc_srq_out_bits { 8802 u8 status[0x8]; 8803 u8 reserved_at_8[0x18]; 8804 8805 u8 syndrome[0x20]; 8806 8807 u8 reserved_at_40[0x8]; 8808 u8 xrc_srqn[0x18]; 8809 8810 u8 reserved_at_60[0x20]; 8811 }; 8812 8813 struct mlx5_ifc_create_xrc_srq_in_bits { 8814 u8 opcode[0x10]; 8815 u8 uid[0x10]; 8816 8817 u8 reserved_at_20[0x10]; 8818 u8 op_mod[0x10]; 8819 8820 u8 reserved_at_40[0x40]; 8821 8822 struct mlx5_ifc_xrc_srqc_bits xrc_srq_context_entry; 8823 8824 u8 reserved_at_280[0x60]; 8825 8826 u8 xrc_srq_umem_valid[0x1]; 8827 u8 reserved_at_2e1[0x1f]; 8828 8829 u8 reserved_at_300[0x580]; 8830 8831 u8 pas[][0x40]; 8832 }; 8833 8834 struct mlx5_ifc_create_tis_out_bits { 8835 u8 status[0x8]; 8836 u8 reserved_at_8[0x18]; 8837 8838 u8 syndrome[0x20]; 8839 8840 u8 reserved_at_40[0x8]; 8841 u8 tisn[0x18]; 8842 8843 u8 reserved_at_60[0x20]; 8844 }; 8845 8846 struct mlx5_ifc_create_tis_in_bits { 8847 u8 opcode[0x10]; 8848 u8 uid[0x10]; 8849 8850 u8 reserved_at_20[0x10]; 8851 u8 op_mod[0x10]; 8852 8853 u8 reserved_at_40[0xc0]; 8854 8855 struct mlx5_ifc_tisc_bits ctx; 8856 }; 8857 8858 struct mlx5_ifc_create_tir_out_bits { 8859 u8 status[0x8]; 8860 u8 icm_address_63_40[0x18]; 8861 8862 u8 syndrome[0x20]; 8863 8864 u8 icm_address_39_32[0x8]; 8865 u8 tirn[0x18]; 8866 8867 u8 icm_address_31_0[0x20]; 8868 }; 8869 8870 struct mlx5_ifc_create_tir_in_bits { 8871 u8 opcode[0x10]; 8872 u8 uid[0x10]; 8873 8874 u8 reserved_at_20[0x10]; 8875 u8 op_mod[0x10]; 8876 8877 u8 reserved_at_40[0xc0]; 8878 8879 struct mlx5_ifc_tirc_bits ctx; 8880 }; 8881 8882 struct mlx5_ifc_create_srq_out_bits { 8883 u8 status[0x8]; 8884 u8 reserved_at_8[0x18]; 8885 8886 u8 syndrome[0x20]; 8887 8888 u8 reserved_at_40[0x8]; 8889 u8 srqn[0x18]; 8890 8891 u8 reserved_at_60[0x20]; 8892 }; 8893 8894 struct mlx5_ifc_create_srq_in_bits { 8895 u8 opcode[0x10]; 8896 u8 uid[0x10]; 8897 8898 u8 reserved_at_20[0x10]; 8899 u8 op_mod[0x10]; 8900 8901 u8 reserved_at_40[0x40]; 8902 8903 struct mlx5_ifc_srqc_bits srq_context_entry; 8904 8905 u8 reserved_at_280[0x600]; 8906 8907 u8 pas[][0x40]; 8908 }; 8909 8910 struct mlx5_ifc_create_sq_out_bits { 8911 u8 status[0x8]; 8912 u8 reserved_at_8[0x18]; 8913 8914 u8 syndrome[0x20]; 8915 8916 u8 reserved_at_40[0x8]; 8917 u8 sqn[0x18]; 8918 8919 u8 reserved_at_60[0x20]; 8920 }; 8921 8922 struct mlx5_ifc_create_sq_in_bits { 8923 u8 opcode[0x10]; 8924 u8 uid[0x10]; 8925 8926 u8 reserved_at_20[0x10]; 8927 u8 op_mod[0x10]; 8928 8929 u8 reserved_at_40[0xc0]; 8930 8931 struct mlx5_ifc_sqc_bits ctx; 8932 }; 8933 8934 struct mlx5_ifc_create_scheduling_element_out_bits { 8935 u8 status[0x8]; 8936 u8 reserved_at_8[0x18]; 8937 8938 u8 syndrome[0x20]; 8939 8940 u8 reserved_at_40[0x40]; 8941 8942 u8 scheduling_element_id[0x20]; 8943 8944 u8 reserved_at_a0[0x160]; 8945 }; 8946 8947 struct mlx5_ifc_create_scheduling_element_in_bits { 8948 u8 opcode[0x10]; 8949 u8 reserved_at_10[0x10]; 8950 8951 u8 reserved_at_20[0x10]; 8952 u8 op_mod[0x10]; 8953 8954 u8 scheduling_hierarchy[0x8]; 8955 u8 reserved_at_48[0x18]; 8956 8957 u8 reserved_at_60[0xa0]; 8958 8959 struct mlx5_ifc_scheduling_context_bits scheduling_context; 8960 8961 u8 reserved_at_300[0x100]; 8962 }; 8963 8964 struct mlx5_ifc_create_rqt_out_bits { 8965 u8 status[0x8]; 8966 u8 reserved_at_8[0x18]; 8967 8968 u8 syndrome[0x20]; 8969 8970 u8 reserved_at_40[0x8]; 8971 u8 rqtn[0x18]; 8972 8973 u8 reserved_at_60[0x20]; 8974 }; 8975 8976 struct mlx5_ifc_create_rqt_in_bits { 8977 u8 opcode[0x10]; 8978 u8 uid[0x10]; 8979 8980 u8 reserved_at_20[0x10]; 8981 u8 op_mod[0x10]; 8982 8983 u8 reserved_at_40[0xc0]; 8984 8985 struct mlx5_ifc_rqtc_bits rqt_context; 8986 }; 8987 8988 struct mlx5_ifc_create_rq_out_bits { 8989 u8 status[0x8]; 8990 u8 reserved_at_8[0x18]; 8991 8992 u8 syndrome[0x20]; 8993 8994 u8 reserved_at_40[0x8]; 8995 u8 rqn[0x18]; 8996 8997 u8 reserved_at_60[0x20]; 8998 }; 8999 9000 struct mlx5_ifc_create_rq_in_bits { 9001 u8 opcode[0x10]; 9002 u8 uid[0x10]; 9003 9004 u8 reserved_at_20[0x10]; 9005 u8 op_mod[0x10]; 9006 9007 u8 reserved_at_40[0xc0]; 9008 9009 struct mlx5_ifc_rqc_bits ctx; 9010 }; 9011 9012 struct mlx5_ifc_create_rmp_out_bits { 9013 u8 status[0x8]; 9014 u8 reserved_at_8[0x18]; 9015 9016 u8 syndrome[0x20]; 9017 9018 u8 reserved_at_40[0x8]; 9019 u8 rmpn[0x18]; 9020 9021 u8 reserved_at_60[0x20]; 9022 }; 9023 9024 struct mlx5_ifc_create_rmp_in_bits { 9025 u8 opcode[0x10]; 9026 u8 uid[0x10]; 9027 9028 u8 reserved_at_20[0x10]; 9029 u8 op_mod[0x10]; 9030 9031 u8 reserved_at_40[0xc0]; 9032 9033 struct mlx5_ifc_rmpc_bits ctx; 9034 }; 9035 9036 struct mlx5_ifc_create_qp_out_bits { 9037 u8 status[0x8]; 9038 u8 reserved_at_8[0x18]; 9039 9040 u8 syndrome[0x20]; 9041 9042 u8 reserved_at_40[0x8]; 9043 u8 qpn[0x18]; 9044 9045 u8 ece[0x20]; 9046 }; 9047 9048 struct mlx5_ifc_create_qp_in_bits { 9049 u8 opcode[0x10]; 9050 u8 uid[0x10]; 9051 9052 u8 reserved_at_20[0x10]; 9053 u8 op_mod[0x10]; 9054 9055 u8 qpc_ext[0x1]; 9056 u8 reserved_at_41[0x7]; 9057 u8 input_qpn[0x18]; 9058 9059 u8 reserved_at_60[0x20]; 9060 u8 opt_param_mask[0x20]; 9061 9062 u8 ece[0x20]; 9063 9064 struct mlx5_ifc_qpc_bits qpc; 9065 9066 u8 wq_umem_offset[0x40]; 9067 9068 u8 wq_umem_id[0x20]; 9069 9070 u8 wq_umem_valid[0x1]; 9071 u8 reserved_at_861[0x1f]; 9072 9073 u8 pas[][0x40]; 9074 }; 9075 9076 struct mlx5_ifc_create_psv_out_bits { 9077 u8 status[0x8]; 9078 u8 reserved_at_8[0x18]; 9079 9080 u8 syndrome[0x20]; 9081 9082 u8 reserved_at_40[0x40]; 9083 9084 u8 reserved_at_80[0x8]; 9085 u8 psv0_index[0x18]; 9086 9087 u8 reserved_at_a0[0x8]; 9088 u8 psv1_index[0x18]; 9089 9090 u8 reserved_at_c0[0x8]; 9091 u8 psv2_index[0x18]; 9092 9093 u8 reserved_at_e0[0x8]; 9094 u8 psv3_index[0x18]; 9095 }; 9096 9097 struct mlx5_ifc_create_psv_in_bits { 9098 u8 opcode[0x10]; 9099 u8 reserved_at_10[0x10]; 9100 9101 u8 reserved_at_20[0x10]; 9102 u8 op_mod[0x10]; 9103 9104 u8 num_psv[0x4]; 9105 u8 reserved_at_44[0x4]; 9106 u8 pd[0x18]; 9107 9108 u8 reserved_at_60[0x20]; 9109 }; 9110 9111 struct mlx5_ifc_create_mkey_out_bits { 9112 u8 status[0x8]; 9113 u8 reserved_at_8[0x18]; 9114 9115 u8 syndrome[0x20]; 9116 9117 u8 reserved_at_40[0x8]; 9118 u8 mkey_index[0x18]; 9119 9120 u8 reserved_at_60[0x20]; 9121 }; 9122 9123 struct mlx5_ifc_create_mkey_in_bits { 9124 u8 opcode[0x10]; 9125 u8 uid[0x10]; 9126 9127 u8 reserved_at_20[0x10]; 9128 u8 op_mod[0x10]; 9129 9130 u8 reserved_at_40[0x20]; 9131 9132 u8 pg_access[0x1]; 9133 u8 mkey_umem_valid[0x1]; 9134 u8 reserved_at_62[0x1e]; 9135 9136 struct mlx5_ifc_mkc_bits memory_key_mkey_entry; 9137 9138 u8 reserved_at_280[0x80]; 9139 9140 u8 translations_octword_actual_size[0x20]; 9141 9142 u8 reserved_at_320[0x560]; 9143 9144 u8 klm_pas_mtt[][0x20]; 9145 }; 9146 9147 enum { 9148 MLX5_FLOW_TABLE_TYPE_NIC_RX = 0x0, 9149 MLX5_FLOW_TABLE_TYPE_NIC_TX = 0x1, 9150 MLX5_FLOW_TABLE_TYPE_ESW_EGRESS_ACL = 0x2, 9151 MLX5_FLOW_TABLE_TYPE_ESW_INGRESS_ACL = 0x3, 9152 MLX5_FLOW_TABLE_TYPE_FDB = 0X4, 9153 MLX5_FLOW_TABLE_TYPE_SNIFFER_RX = 0X5, 9154 MLX5_FLOW_TABLE_TYPE_SNIFFER_TX = 0X6, 9155 }; 9156 9157 struct mlx5_ifc_create_flow_table_out_bits { 9158 u8 status[0x8]; 9159 u8 icm_address_63_40[0x18]; 9160 9161 u8 syndrome[0x20]; 9162 9163 u8 icm_address_39_32[0x8]; 9164 u8 table_id[0x18]; 9165 9166 u8 icm_address_31_0[0x20]; 9167 }; 9168 9169 struct mlx5_ifc_create_flow_table_in_bits { 9170 u8 opcode[0x10]; 9171 u8 uid[0x10]; 9172 9173 u8 reserved_at_20[0x10]; 9174 u8 op_mod[0x10]; 9175 9176 u8 other_vport[0x1]; 9177 u8 reserved_at_41[0xf]; 9178 u8 vport_number[0x10]; 9179 9180 u8 reserved_at_60[0x20]; 9181 9182 u8 table_type[0x8]; 9183 u8 reserved_at_88[0x18]; 9184 9185 u8 reserved_at_a0[0x20]; 9186 9187 struct mlx5_ifc_flow_table_context_bits flow_table_context; 9188 }; 9189 9190 struct mlx5_ifc_create_flow_group_out_bits { 9191 u8 status[0x8]; 9192 u8 reserved_at_8[0x18]; 9193 9194 u8 syndrome[0x20]; 9195 9196 u8 reserved_at_40[0x8]; 9197 u8 group_id[0x18]; 9198 9199 u8 reserved_at_60[0x20]; 9200 }; 9201 9202 enum { 9203 MLX5_CREATE_FLOW_GROUP_IN_GROUP_TYPE_TCAM_SUBTABLE = 0x0, 9204 MLX5_CREATE_FLOW_GROUP_IN_GROUP_TYPE_HASH_SPLIT = 0x1, 9205 }; 9206 9207 enum { 9208 MLX5_CREATE_FLOW_GROUP_IN_MATCH_CRITERIA_ENABLE_OUTER_HEADERS = 0x0, 9209 MLX5_CREATE_FLOW_GROUP_IN_MATCH_CRITERIA_ENABLE_MISC_PARAMETERS = 0x1, 9210 MLX5_CREATE_FLOW_GROUP_IN_MATCH_CRITERIA_ENABLE_INNER_HEADERS = 0x2, 9211 MLX5_CREATE_FLOW_GROUP_IN_MATCH_CRITERIA_ENABLE_MISC_PARAMETERS_2 = 0x3, 9212 }; 9213 9214 struct mlx5_ifc_create_flow_group_in_bits { 9215 u8 opcode[0x10]; 9216 u8 reserved_at_10[0x10]; 9217 9218 u8 reserved_at_20[0x10]; 9219 u8 op_mod[0x10]; 9220 9221 u8 other_vport[0x1]; 9222 u8 reserved_at_41[0xf]; 9223 u8 vport_number[0x10]; 9224 9225 u8 reserved_at_60[0x20]; 9226 9227 u8 table_type[0x8]; 9228 u8 reserved_at_88[0x4]; 9229 u8 group_type[0x4]; 9230 u8 reserved_at_90[0x10]; 9231 9232 u8 reserved_at_a0[0x8]; 9233 u8 table_id[0x18]; 9234 9235 u8 source_eswitch_owner_vhca_id_valid[0x1]; 9236 9237 u8 reserved_at_c1[0x1f]; 9238 9239 u8 start_flow_index[0x20]; 9240 9241 u8 reserved_at_100[0x20]; 9242 9243 u8 end_flow_index[0x20]; 9244 9245 u8 reserved_at_140[0x10]; 9246 u8 match_definer_id[0x10]; 9247 9248 u8 reserved_at_160[0x80]; 9249 9250 u8 reserved_at_1e0[0x18]; 9251 u8 match_criteria_enable[0x8]; 9252 9253 struct mlx5_ifc_fte_match_param_bits match_criteria; 9254 9255 u8 reserved_at_1200[0xe00]; 9256 }; 9257 9258 struct mlx5_ifc_create_eq_out_bits { 9259 u8 status[0x8]; 9260 u8 reserved_at_8[0x18]; 9261 9262 u8 syndrome[0x20]; 9263 9264 u8 reserved_at_40[0x18]; 9265 u8 eq_number[0x8]; 9266 9267 u8 reserved_at_60[0x20]; 9268 }; 9269 9270 struct mlx5_ifc_create_eq_in_bits { 9271 u8 opcode[0x10]; 9272 u8 uid[0x10]; 9273 9274 u8 reserved_at_20[0x10]; 9275 u8 op_mod[0x10]; 9276 9277 u8 reserved_at_40[0x40]; 9278 9279 struct mlx5_ifc_eqc_bits eq_context_entry; 9280 9281 u8 reserved_at_280[0x40]; 9282 9283 u8 event_bitmask[4][0x40]; 9284 9285 u8 reserved_at_3c0[0x4c0]; 9286 9287 u8 pas[][0x40]; 9288 }; 9289 9290 struct mlx5_ifc_create_dct_out_bits { 9291 u8 status[0x8]; 9292 u8 reserved_at_8[0x18]; 9293 9294 u8 syndrome[0x20]; 9295 9296 u8 reserved_at_40[0x8]; 9297 u8 dctn[0x18]; 9298 9299 u8 ece[0x20]; 9300 }; 9301 9302 struct mlx5_ifc_create_dct_in_bits { 9303 u8 opcode[0x10]; 9304 u8 uid[0x10]; 9305 9306 u8 reserved_at_20[0x10]; 9307 u8 op_mod[0x10]; 9308 9309 u8 reserved_at_40[0x40]; 9310 9311 struct mlx5_ifc_dctc_bits dct_context_entry; 9312 9313 u8 reserved_at_280[0x180]; 9314 }; 9315 9316 struct mlx5_ifc_create_cq_out_bits { 9317 u8 status[0x8]; 9318 u8 reserved_at_8[0x18]; 9319 9320 u8 syndrome[0x20]; 9321 9322 u8 reserved_at_40[0x8]; 9323 u8 cqn[0x18]; 9324 9325 u8 reserved_at_60[0x20]; 9326 }; 9327 9328 struct mlx5_ifc_create_cq_in_bits { 9329 u8 opcode[0x10]; 9330 u8 uid[0x10]; 9331 9332 u8 reserved_at_20[0x10]; 9333 u8 op_mod[0x10]; 9334 9335 u8 reserved_at_40[0x40]; 9336 9337 struct mlx5_ifc_cqc_bits cq_context; 9338 9339 u8 reserved_at_280[0x60]; 9340 9341 u8 cq_umem_valid[0x1]; 9342 u8 reserved_at_2e1[0x59f]; 9343 9344 u8 pas[][0x40]; 9345 }; 9346 9347 struct mlx5_ifc_config_int_moderation_out_bits { 9348 u8 status[0x8]; 9349 u8 reserved_at_8[0x18]; 9350 9351 u8 syndrome[0x20]; 9352 9353 u8 reserved_at_40[0x4]; 9354 u8 min_delay[0xc]; 9355 u8 int_vector[0x10]; 9356 9357 u8 reserved_at_60[0x20]; 9358 }; 9359 9360 enum { 9361 MLX5_CONFIG_INT_MODERATION_IN_OP_MOD_WRITE = 0x0, 9362 MLX5_CONFIG_INT_MODERATION_IN_OP_MOD_READ = 0x1, 9363 }; 9364 9365 struct mlx5_ifc_config_int_moderation_in_bits { 9366 u8 opcode[0x10]; 9367 u8 reserved_at_10[0x10]; 9368 9369 u8 reserved_at_20[0x10]; 9370 u8 op_mod[0x10]; 9371 9372 u8 reserved_at_40[0x4]; 9373 u8 min_delay[0xc]; 9374 u8 int_vector[0x10]; 9375 9376 u8 reserved_at_60[0x20]; 9377 }; 9378 9379 struct mlx5_ifc_attach_to_mcg_out_bits { 9380 u8 status[0x8]; 9381 u8 reserved_at_8[0x18]; 9382 9383 u8 syndrome[0x20]; 9384 9385 u8 reserved_at_40[0x40]; 9386 }; 9387 9388 struct mlx5_ifc_attach_to_mcg_in_bits { 9389 u8 opcode[0x10]; 9390 u8 uid[0x10]; 9391 9392 u8 reserved_at_20[0x10]; 9393 u8 op_mod[0x10]; 9394 9395 u8 reserved_at_40[0x8]; 9396 u8 qpn[0x18]; 9397 9398 u8 reserved_at_60[0x20]; 9399 9400 u8 multicast_gid[16][0x8]; 9401 }; 9402 9403 struct mlx5_ifc_arm_xrq_out_bits { 9404 u8 status[0x8]; 9405 u8 reserved_at_8[0x18]; 9406 9407 u8 syndrome[0x20]; 9408 9409 u8 reserved_at_40[0x40]; 9410 }; 9411 9412 struct mlx5_ifc_arm_xrq_in_bits { 9413 u8 opcode[0x10]; 9414 u8 reserved_at_10[0x10]; 9415 9416 u8 reserved_at_20[0x10]; 9417 u8 op_mod[0x10]; 9418 9419 u8 reserved_at_40[0x8]; 9420 u8 xrqn[0x18]; 9421 9422 u8 reserved_at_60[0x10]; 9423 u8 lwm[0x10]; 9424 }; 9425 9426 struct mlx5_ifc_arm_xrc_srq_out_bits { 9427 u8 status[0x8]; 9428 u8 reserved_at_8[0x18]; 9429 9430 u8 syndrome[0x20]; 9431 9432 u8 reserved_at_40[0x40]; 9433 }; 9434 9435 enum { 9436 MLX5_ARM_XRC_SRQ_IN_OP_MOD_XRC_SRQ = 0x1, 9437 }; 9438 9439 struct mlx5_ifc_arm_xrc_srq_in_bits { 9440 u8 opcode[0x10]; 9441 u8 uid[0x10]; 9442 9443 u8 reserved_at_20[0x10]; 9444 u8 op_mod[0x10]; 9445 9446 u8 reserved_at_40[0x8]; 9447 u8 xrc_srqn[0x18]; 9448 9449 u8 reserved_at_60[0x10]; 9450 u8 lwm[0x10]; 9451 }; 9452 9453 struct mlx5_ifc_arm_rq_out_bits { 9454 u8 status[0x8]; 9455 u8 reserved_at_8[0x18]; 9456 9457 u8 syndrome[0x20]; 9458 9459 u8 reserved_at_40[0x40]; 9460 }; 9461 9462 enum { 9463 MLX5_ARM_RQ_IN_OP_MOD_SRQ = 0x1, 9464 MLX5_ARM_RQ_IN_OP_MOD_XRQ = 0x2, 9465 }; 9466 9467 struct mlx5_ifc_arm_rq_in_bits { 9468 u8 opcode[0x10]; 9469 u8 uid[0x10]; 9470 9471 u8 reserved_at_20[0x10]; 9472 u8 op_mod[0x10]; 9473 9474 u8 reserved_at_40[0x8]; 9475 u8 srq_number[0x18]; 9476 9477 u8 reserved_at_60[0x10]; 9478 u8 lwm[0x10]; 9479 }; 9480 9481 struct mlx5_ifc_arm_dct_out_bits { 9482 u8 status[0x8]; 9483 u8 reserved_at_8[0x18]; 9484 9485 u8 syndrome[0x20]; 9486 9487 u8 reserved_at_40[0x40]; 9488 }; 9489 9490 struct mlx5_ifc_arm_dct_in_bits { 9491 u8 opcode[0x10]; 9492 u8 reserved_at_10[0x10]; 9493 9494 u8 reserved_at_20[0x10]; 9495 u8 op_mod[0x10]; 9496 9497 u8 reserved_at_40[0x8]; 9498 u8 dct_number[0x18]; 9499 9500 u8 reserved_at_60[0x20]; 9501 }; 9502 9503 struct mlx5_ifc_alloc_xrcd_out_bits { 9504 u8 status[0x8]; 9505 u8 reserved_at_8[0x18]; 9506 9507 u8 syndrome[0x20]; 9508 9509 u8 reserved_at_40[0x8]; 9510 u8 xrcd[0x18]; 9511 9512 u8 reserved_at_60[0x20]; 9513 }; 9514 9515 struct mlx5_ifc_alloc_xrcd_in_bits { 9516 u8 opcode[0x10]; 9517 u8 uid[0x10]; 9518 9519 u8 reserved_at_20[0x10]; 9520 u8 op_mod[0x10]; 9521 9522 u8 reserved_at_40[0x40]; 9523 }; 9524 9525 struct mlx5_ifc_alloc_uar_out_bits { 9526 u8 status[0x8]; 9527 u8 reserved_at_8[0x18]; 9528 9529 u8 syndrome[0x20]; 9530 9531 u8 reserved_at_40[0x8]; 9532 u8 uar[0x18]; 9533 9534 u8 reserved_at_60[0x20]; 9535 }; 9536 9537 struct mlx5_ifc_alloc_uar_in_bits { 9538 u8 opcode[0x10]; 9539 u8 uid[0x10]; 9540 9541 u8 reserved_at_20[0x10]; 9542 u8 op_mod[0x10]; 9543 9544 u8 reserved_at_40[0x40]; 9545 }; 9546 9547 struct mlx5_ifc_alloc_transport_domain_out_bits { 9548 u8 status[0x8]; 9549 u8 reserved_at_8[0x18]; 9550 9551 u8 syndrome[0x20]; 9552 9553 u8 reserved_at_40[0x8]; 9554 u8 transport_domain[0x18]; 9555 9556 u8 reserved_at_60[0x20]; 9557 }; 9558 9559 struct mlx5_ifc_alloc_transport_domain_in_bits { 9560 u8 opcode[0x10]; 9561 u8 uid[0x10]; 9562 9563 u8 reserved_at_20[0x10]; 9564 u8 op_mod[0x10]; 9565 9566 u8 reserved_at_40[0x40]; 9567 }; 9568 9569 struct mlx5_ifc_alloc_q_counter_out_bits { 9570 u8 status[0x8]; 9571 u8 reserved_at_8[0x18]; 9572 9573 u8 syndrome[0x20]; 9574 9575 u8 reserved_at_40[0x18]; 9576 u8 counter_set_id[0x8]; 9577 9578 u8 reserved_at_60[0x20]; 9579 }; 9580 9581 struct mlx5_ifc_alloc_q_counter_in_bits { 9582 u8 opcode[0x10]; 9583 u8 uid[0x10]; 9584 9585 u8 reserved_at_20[0x10]; 9586 u8 op_mod[0x10]; 9587 9588 u8 reserved_at_40[0x40]; 9589 }; 9590 9591 struct mlx5_ifc_alloc_pd_out_bits { 9592 u8 status[0x8]; 9593 u8 reserved_at_8[0x18]; 9594 9595 u8 syndrome[0x20]; 9596 9597 u8 reserved_at_40[0x8]; 9598 u8 pd[0x18]; 9599 9600 u8 reserved_at_60[0x20]; 9601 }; 9602 9603 struct mlx5_ifc_alloc_pd_in_bits { 9604 u8 opcode[0x10]; 9605 u8 uid[0x10]; 9606 9607 u8 reserved_at_20[0x10]; 9608 u8 op_mod[0x10]; 9609 9610 u8 reserved_at_40[0x40]; 9611 }; 9612 9613 struct mlx5_ifc_alloc_flow_counter_out_bits { 9614 u8 status[0x8]; 9615 u8 reserved_at_8[0x18]; 9616 9617 u8 syndrome[0x20]; 9618 9619 u8 flow_counter_id[0x20]; 9620 9621 u8 reserved_at_60[0x20]; 9622 }; 9623 9624 struct mlx5_ifc_alloc_flow_counter_in_bits { 9625 u8 opcode[0x10]; 9626 u8 reserved_at_10[0x10]; 9627 9628 u8 reserved_at_20[0x10]; 9629 u8 op_mod[0x10]; 9630 9631 u8 reserved_at_40[0x33]; 9632 u8 flow_counter_bulk_log_size[0x5]; 9633 u8 flow_counter_bulk[0x8]; 9634 }; 9635 9636 struct mlx5_ifc_add_vxlan_udp_dport_out_bits { 9637 u8 status[0x8]; 9638 u8 reserved_at_8[0x18]; 9639 9640 u8 syndrome[0x20]; 9641 9642 u8 reserved_at_40[0x40]; 9643 }; 9644 9645 struct mlx5_ifc_add_vxlan_udp_dport_in_bits { 9646 u8 opcode[0x10]; 9647 u8 reserved_at_10[0x10]; 9648 9649 u8 reserved_at_20[0x10]; 9650 u8 op_mod[0x10]; 9651 9652 u8 reserved_at_40[0x20]; 9653 9654 u8 reserved_at_60[0x10]; 9655 u8 vxlan_udp_port[0x10]; 9656 }; 9657 9658 struct mlx5_ifc_set_pp_rate_limit_out_bits { 9659 u8 status[0x8]; 9660 u8 reserved_at_8[0x18]; 9661 9662 u8 syndrome[0x20]; 9663 9664 u8 reserved_at_40[0x40]; 9665 }; 9666 9667 struct mlx5_ifc_set_pp_rate_limit_context_bits { 9668 u8 rate_limit[0x20]; 9669 9670 u8 burst_upper_bound[0x20]; 9671 9672 u8 reserved_at_40[0x10]; 9673 u8 typical_packet_size[0x10]; 9674 9675 u8 reserved_at_60[0x120]; 9676 }; 9677 9678 struct mlx5_ifc_set_pp_rate_limit_in_bits { 9679 u8 opcode[0x10]; 9680 u8 uid[0x10]; 9681 9682 u8 reserved_at_20[0x10]; 9683 u8 op_mod[0x10]; 9684 9685 u8 reserved_at_40[0x10]; 9686 u8 rate_limit_index[0x10]; 9687 9688 u8 reserved_at_60[0x20]; 9689 9690 struct mlx5_ifc_set_pp_rate_limit_context_bits ctx; 9691 }; 9692 9693 struct mlx5_ifc_access_register_out_bits { 9694 u8 status[0x8]; 9695 u8 reserved_at_8[0x18]; 9696 9697 u8 syndrome[0x20]; 9698 9699 u8 reserved_at_40[0x40]; 9700 9701 u8 register_data[][0x20]; 9702 }; 9703 9704 enum { 9705 MLX5_ACCESS_REGISTER_IN_OP_MOD_WRITE = 0x0, 9706 MLX5_ACCESS_REGISTER_IN_OP_MOD_READ = 0x1, 9707 }; 9708 9709 struct mlx5_ifc_access_register_in_bits { 9710 u8 opcode[0x10]; 9711 u8 reserved_at_10[0x10]; 9712 9713 u8 reserved_at_20[0x10]; 9714 u8 op_mod[0x10]; 9715 9716 u8 reserved_at_40[0x10]; 9717 u8 register_id[0x10]; 9718 9719 u8 argument[0x20]; 9720 9721 u8 register_data[][0x20]; 9722 }; 9723 9724 struct mlx5_ifc_sltp_reg_bits { 9725 u8 status[0x4]; 9726 u8 version[0x4]; 9727 u8 local_port[0x8]; 9728 u8 pnat[0x2]; 9729 u8 reserved_at_12[0x2]; 9730 u8 lane[0x4]; 9731 u8 reserved_at_18[0x8]; 9732 9733 u8 reserved_at_20[0x20]; 9734 9735 u8 reserved_at_40[0x7]; 9736 u8 polarity[0x1]; 9737 u8 ob_tap0[0x8]; 9738 u8 ob_tap1[0x8]; 9739 u8 ob_tap2[0x8]; 9740 9741 u8 reserved_at_60[0xc]; 9742 u8 ob_preemp_mode[0x4]; 9743 u8 ob_reg[0x8]; 9744 u8 ob_bias[0x8]; 9745 9746 u8 reserved_at_80[0x20]; 9747 }; 9748 9749 struct mlx5_ifc_slrg_reg_bits { 9750 u8 status[0x4]; 9751 u8 version[0x4]; 9752 u8 local_port[0x8]; 9753 u8 pnat[0x2]; 9754 u8 reserved_at_12[0x2]; 9755 u8 lane[0x4]; 9756 u8 reserved_at_18[0x8]; 9757 9758 u8 time_to_link_up[0x10]; 9759 u8 reserved_at_30[0xc]; 9760 u8 grade_lane_speed[0x4]; 9761 9762 u8 grade_version[0x8]; 9763 u8 grade[0x18]; 9764 9765 u8 reserved_at_60[0x4]; 9766 u8 height_grade_type[0x4]; 9767 u8 height_grade[0x18]; 9768 9769 u8 height_dz[0x10]; 9770 u8 height_dv[0x10]; 9771 9772 u8 reserved_at_a0[0x10]; 9773 u8 height_sigma[0x10]; 9774 9775 u8 reserved_at_c0[0x20]; 9776 9777 u8 reserved_at_e0[0x4]; 9778 u8 phase_grade_type[0x4]; 9779 u8 phase_grade[0x18]; 9780 9781 u8 reserved_at_100[0x8]; 9782 u8 phase_eo_pos[0x8]; 9783 u8 reserved_at_110[0x8]; 9784 u8 phase_eo_neg[0x8]; 9785 9786 u8 ffe_set_tested[0x10]; 9787 u8 test_errors_per_lane[0x10]; 9788 }; 9789 9790 struct mlx5_ifc_pvlc_reg_bits { 9791 u8 reserved_at_0[0x8]; 9792 u8 local_port[0x8]; 9793 u8 reserved_at_10[0x10]; 9794 9795 u8 reserved_at_20[0x1c]; 9796 u8 vl_hw_cap[0x4]; 9797 9798 u8 reserved_at_40[0x1c]; 9799 u8 vl_admin[0x4]; 9800 9801 u8 reserved_at_60[0x1c]; 9802 u8 vl_operational[0x4]; 9803 }; 9804 9805 struct mlx5_ifc_pude_reg_bits { 9806 u8 swid[0x8]; 9807 u8 local_port[0x8]; 9808 u8 reserved_at_10[0x4]; 9809 u8 admin_status[0x4]; 9810 u8 reserved_at_18[0x4]; 9811 u8 oper_status[0x4]; 9812 9813 u8 reserved_at_20[0x60]; 9814 }; 9815 9816 struct mlx5_ifc_ptys_reg_bits { 9817 u8 reserved_at_0[0x1]; 9818 u8 an_disable_admin[0x1]; 9819 u8 an_disable_cap[0x1]; 9820 u8 reserved_at_3[0x5]; 9821 u8 local_port[0x8]; 9822 u8 reserved_at_10[0x8]; 9823 u8 plane_ind[0x4]; 9824 u8 reserved_at_1c[0x1]; 9825 u8 proto_mask[0x3]; 9826 9827 u8 an_status[0x4]; 9828 u8 reserved_at_24[0xc]; 9829 u8 data_rate_oper[0x10]; 9830 9831 u8 ext_eth_proto_capability[0x20]; 9832 9833 u8 eth_proto_capability[0x20]; 9834 9835 u8 ib_link_width_capability[0x10]; 9836 u8 ib_proto_capability[0x10]; 9837 9838 u8 ext_eth_proto_admin[0x20]; 9839 9840 u8 eth_proto_admin[0x20]; 9841 9842 u8 ib_link_width_admin[0x10]; 9843 u8 ib_proto_admin[0x10]; 9844 9845 u8 ext_eth_proto_oper[0x20]; 9846 9847 u8 eth_proto_oper[0x20]; 9848 9849 u8 ib_link_width_oper[0x10]; 9850 u8 ib_proto_oper[0x10]; 9851 9852 u8 reserved_at_160[0x1c]; 9853 u8 connector_type[0x4]; 9854 9855 u8 eth_proto_lp_advertise[0x20]; 9856 9857 u8 reserved_at_1a0[0x60]; 9858 }; 9859 9860 struct mlx5_ifc_mlcr_reg_bits { 9861 u8 reserved_at_0[0x8]; 9862 u8 local_port[0x8]; 9863 u8 reserved_at_10[0x20]; 9864 9865 u8 beacon_duration[0x10]; 9866 u8 reserved_at_40[0x10]; 9867 9868 u8 beacon_remain[0x10]; 9869 }; 9870 9871 struct mlx5_ifc_ptas_reg_bits { 9872 u8 reserved_at_0[0x20]; 9873 9874 u8 algorithm_options[0x10]; 9875 u8 reserved_at_30[0x4]; 9876 u8 repetitions_mode[0x4]; 9877 u8 num_of_repetitions[0x8]; 9878 9879 u8 grade_version[0x8]; 9880 u8 height_grade_type[0x4]; 9881 u8 phase_grade_type[0x4]; 9882 u8 height_grade_weight[0x8]; 9883 u8 phase_grade_weight[0x8]; 9884 9885 u8 gisim_measure_bits[0x10]; 9886 u8 adaptive_tap_measure_bits[0x10]; 9887 9888 u8 ber_bath_high_error_threshold[0x10]; 9889 u8 ber_bath_mid_error_threshold[0x10]; 9890 9891 u8 ber_bath_low_error_threshold[0x10]; 9892 u8 one_ratio_high_threshold[0x10]; 9893 9894 u8 one_ratio_high_mid_threshold[0x10]; 9895 u8 one_ratio_low_mid_threshold[0x10]; 9896 9897 u8 one_ratio_low_threshold[0x10]; 9898 u8 ndeo_error_threshold[0x10]; 9899 9900 u8 mixer_offset_step_size[0x10]; 9901 u8 reserved_at_110[0x8]; 9902 u8 mix90_phase_for_voltage_bath[0x8]; 9903 9904 u8 mixer_offset_start[0x10]; 9905 u8 mixer_offset_end[0x10]; 9906 9907 u8 reserved_at_140[0x15]; 9908 u8 ber_test_time[0xb]; 9909 }; 9910 9911 struct mlx5_ifc_pspa_reg_bits { 9912 u8 swid[0x8]; 9913 u8 local_port[0x8]; 9914 u8 sub_port[0x8]; 9915 u8 reserved_at_18[0x8]; 9916 9917 u8 reserved_at_20[0x20]; 9918 }; 9919 9920 struct mlx5_ifc_pqdr_reg_bits { 9921 u8 reserved_at_0[0x8]; 9922 u8 local_port[0x8]; 9923 u8 reserved_at_10[0x5]; 9924 u8 prio[0x3]; 9925 u8 reserved_at_18[0x6]; 9926 u8 mode[0x2]; 9927 9928 u8 reserved_at_20[0x20]; 9929 9930 u8 reserved_at_40[0x10]; 9931 u8 min_threshold[0x10]; 9932 9933 u8 reserved_at_60[0x10]; 9934 u8 max_threshold[0x10]; 9935 9936 u8 reserved_at_80[0x10]; 9937 u8 mark_probability_denominator[0x10]; 9938 9939 u8 reserved_at_a0[0x60]; 9940 }; 9941 9942 struct mlx5_ifc_ppsc_reg_bits { 9943 u8 reserved_at_0[0x8]; 9944 u8 local_port[0x8]; 9945 u8 reserved_at_10[0x10]; 9946 9947 u8 reserved_at_20[0x60]; 9948 9949 u8 reserved_at_80[0x1c]; 9950 u8 wrps_admin[0x4]; 9951 9952 u8 reserved_at_a0[0x1c]; 9953 u8 wrps_status[0x4]; 9954 9955 u8 reserved_at_c0[0x8]; 9956 u8 up_threshold[0x8]; 9957 u8 reserved_at_d0[0x8]; 9958 u8 down_threshold[0x8]; 9959 9960 u8 reserved_at_e0[0x20]; 9961 9962 u8 reserved_at_100[0x1c]; 9963 u8 srps_admin[0x4]; 9964 9965 u8 reserved_at_120[0x1c]; 9966 u8 srps_status[0x4]; 9967 9968 u8 reserved_at_140[0x40]; 9969 }; 9970 9971 struct mlx5_ifc_pplr_reg_bits { 9972 u8 reserved_at_0[0x8]; 9973 u8 local_port[0x8]; 9974 u8 reserved_at_10[0x10]; 9975 9976 u8 reserved_at_20[0x8]; 9977 u8 lb_cap[0x8]; 9978 u8 reserved_at_30[0x8]; 9979 u8 lb_en[0x8]; 9980 }; 9981 9982 struct mlx5_ifc_pplm_reg_bits { 9983 u8 reserved_at_0[0x8]; 9984 u8 local_port[0x8]; 9985 u8 reserved_at_10[0x10]; 9986 9987 u8 reserved_at_20[0x20]; 9988 9989 u8 port_profile_mode[0x8]; 9990 u8 static_port_profile[0x8]; 9991 u8 active_port_profile[0x8]; 9992 u8 reserved_at_58[0x8]; 9993 9994 u8 retransmission_active[0x8]; 9995 u8 fec_mode_active[0x18]; 9996 9997 u8 rs_fec_correction_bypass_cap[0x4]; 9998 u8 reserved_at_84[0x8]; 9999 u8 fec_override_cap_56g[0x4]; 10000 u8 fec_override_cap_100g[0x4]; 10001 u8 fec_override_cap_50g[0x4]; 10002 u8 fec_override_cap_25g[0x4]; 10003 u8 fec_override_cap_10g_40g[0x4]; 10004 10005 u8 rs_fec_correction_bypass_admin[0x4]; 10006 u8 reserved_at_a4[0x8]; 10007 u8 fec_override_admin_56g[0x4]; 10008 u8 fec_override_admin_100g[0x4]; 10009 u8 fec_override_admin_50g[0x4]; 10010 u8 fec_override_admin_25g[0x4]; 10011 u8 fec_override_admin_10g_40g[0x4]; 10012 10013 u8 fec_override_cap_400g_8x[0x10]; 10014 u8 fec_override_cap_200g_4x[0x10]; 10015 10016 u8 fec_override_cap_100g_2x[0x10]; 10017 u8 fec_override_cap_50g_1x[0x10]; 10018 10019 u8 fec_override_admin_400g_8x[0x10]; 10020 u8 fec_override_admin_200g_4x[0x10]; 10021 10022 u8 fec_override_admin_100g_2x[0x10]; 10023 u8 fec_override_admin_50g_1x[0x10]; 10024 10025 u8 fec_override_cap_800g_8x[0x10]; 10026 u8 fec_override_cap_400g_4x[0x10]; 10027 10028 u8 fec_override_cap_200g_2x[0x10]; 10029 u8 fec_override_cap_100g_1x[0x10]; 10030 10031 u8 reserved_at_180[0xa0]; 10032 10033 u8 fec_override_admin_800g_8x[0x10]; 10034 u8 fec_override_admin_400g_4x[0x10]; 10035 10036 u8 fec_override_admin_200g_2x[0x10]; 10037 u8 fec_override_admin_100g_1x[0x10]; 10038 10039 u8 reserved_at_260[0x20]; 10040 }; 10041 10042 struct mlx5_ifc_ppcnt_reg_bits { 10043 u8 swid[0x8]; 10044 u8 local_port[0x8]; 10045 u8 pnat[0x2]; 10046 u8 reserved_at_12[0x8]; 10047 u8 grp[0x6]; 10048 10049 u8 clr[0x1]; 10050 u8 reserved_at_21[0x13]; 10051 u8 plane_ind[0x4]; 10052 u8 reserved_at_38[0x3]; 10053 u8 prio_tc[0x5]; 10054 10055 union mlx5_ifc_eth_cntrs_grp_data_layout_auto_bits counter_set; 10056 }; 10057 10058 struct mlx5_ifc_mpein_reg_bits { 10059 u8 reserved_at_0[0x2]; 10060 u8 depth[0x6]; 10061 u8 pcie_index[0x8]; 10062 u8 node[0x8]; 10063 u8 reserved_at_18[0x8]; 10064 10065 u8 capability_mask[0x20]; 10066 10067 u8 reserved_at_40[0x8]; 10068 u8 link_width_enabled[0x8]; 10069 u8 link_speed_enabled[0x10]; 10070 10071 u8 lane0_physical_position[0x8]; 10072 u8 link_width_active[0x8]; 10073 u8 link_speed_active[0x10]; 10074 10075 u8 num_of_pfs[0x10]; 10076 u8 num_of_vfs[0x10]; 10077 10078 u8 bdf0[0x10]; 10079 u8 reserved_at_b0[0x10]; 10080 10081 u8 max_read_request_size[0x4]; 10082 u8 max_payload_size[0x4]; 10083 u8 reserved_at_c8[0x5]; 10084 u8 pwr_status[0x3]; 10085 u8 port_type[0x4]; 10086 u8 reserved_at_d4[0xb]; 10087 u8 lane_reversal[0x1]; 10088 10089 u8 reserved_at_e0[0x14]; 10090 u8 pci_power[0xc]; 10091 10092 u8 reserved_at_100[0x20]; 10093 10094 u8 device_status[0x10]; 10095 u8 port_state[0x8]; 10096 u8 reserved_at_138[0x8]; 10097 10098 u8 reserved_at_140[0x10]; 10099 u8 receiver_detect_result[0x10]; 10100 10101 u8 reserved_at_160[0x20]; 10102 }; 10103 10104 struct mlx5_ifc_mpcnt_reg_bits { 10105 u8 reserved_at_0[0x8]; 10106 u8 pcie_index[0x8]; 10107 u8 reserved_at_10[0xa]; 10108 u8 grp[0x6]; 10109 10110 u8 clr[0x1]; 10111 u8 reserved_at_21[0x1f]; 10112 10113 union mlx5_ifc_pcie_cntrs_grp_data_layout_auto_bits counter_set; 10114 }; 10115 10116 struct mlx5_ifc_ppad_reg_bits { 10117 u8 reserved_at_0[0x3]; 10118 u8 single_mac[0x1]; 10119 u8 reserved_at_4[0x4]; 10120 u8 local_port[0x8]; 10121 u8 mac_47_32[0x10]; 10122 10123 u8 mac_31_0[0x20]; 10124 10125 u8 reserved_at_40[0x40]; 10126 }; 10127 10128 struct mlx5_ifc_pmtu_reg_bits { 10129 u8 reserved_at_0[0x8]; 10130 u8 local_port[0x8]; 10131 u8 reserved_at_10[0x10]; 10132 10133 u8 max_mtu[0x10]; 10134 u8 reserved_at_30[0x10]; 10135 10136 u8 admin_mtu[0x10]; 10137 u8 reserved_at_50[0x10]; 10138 10139 u8 oper_mtu[0x10]; 10140 u8 reserved_at_70[0x10]; 10141 }; 10142 10143 struct mlx5_ifc_pmpr_reg_bits { 10144 u8 reserved_at_0[0x8]; 10145 u8 module[0x8]; 10146 u8 reserved_at_10[0x10]; 10147 10148 u8 reserved_at_20[0x18]; 10149 u8 attenuation_5g[0x8]; 10150 10151 u8 reserved_at_40[0x18]; 10152 u8 attenuation_7g[0x8]; 10153 10154 u8 reserved_at_60[0x18]; 10155 u8 attenuation_12g[0x8]; 10156 }; 10157 10158 struct mlx5_ifc_pmpe_reg_bits { 10159 u8 reserved_at_0[0x8]; 10160 u8 module[0x8]; 10161 u8 reserved_at_10[0xc]; 10162 u8 module_status[0x4]; 10163 10164 u8 reserved_at_20[0x60]; 10165 }; 10166 10167 struct mlx5_ifc_pmpc_reg_bits { 10168 u8 module_state_updated[32][0x8]; 10169 }; 10170 10171 struct mlx5_ifc_pmlpn_reg_bits { 10172 u8 reserved_at_0[0x4]; 10173 u8 mlpn_status[0x4]; 10174 u8 local_port[0x8]; 10175 u8 reserved_at_10[0x10]; 10176 10177 u8 e[0x1]; 10178 u8 reserved_at_21[0x1f]; 10179 }; 10180 10181 struct mlx5_ifc_pmlp_reg_bits { 10182 u8 rxtx[0x1]; 10183 u8 reserved_at_1[0x7]; 10184 u8 local_port[0x8]; 10185 u8 reserved_at_10[0x8]; 10186 u8 width[0x8]; 10187 10188 u8 lane0_module_mapping[0x20]; 10189 10190 u8 lane1_module_mapping[0x20]; 10191 10192 u8 lane2_module_mapping[0x20]; 10193 10194 u8 lane3_module_mapping[0x20]; 10195 10196 u8 reserved_at_a0[0x160]; 10197 }; 10198 10199 struct mlx5_ifc_pmaos_reg_bits { 10200 u8 reserved_at_0[0x8]; 10201 u8 module[0x8]; 10202 u8 reserved_at_10[0x4]; 10203 u8 admin_status[0x4]; 10204 u8 reserved_at_18[0x4]; 10205 u8 oper_status[0x4]; 10206 10207 u8 ase[0x1]; 10208 u8 ee[0x1]; 10209 u8 reserved_at_22[0x1c]; 10210 u8 e[0x2]; 10211 10212 u8 reserved_at_40[0x40]; 10213 }; 10214 10215 struct mlx5_ifc_plpc_reg_bits { 10216 u8 reserved_at_0[0x4]; 10217 u8 profile_id[0xc]; 10218 u8 reserved_at_10[0x4]; 10219 u8 proto_mask[0x4]; 10220 u8 reserved_at_18[0x8]; 10221 10222 u8 reserved_at_20[0x10]; 10223 u8 lane_speed[0x10]; 10224 10225 u8 reserved_at_40[0x17]; 10226 u8 lpbf[0x1]; 10227 u8 fec_mode_policy[0x8]; 10228 10229 u8 retransmission_capability[0x8]; 10230 u8 fec_mode_capability[0x18]; 10231 10232 u8 retransmission_support_admin[0x8]; 10233 u8 fec_mode_support_admin[0x18]; 10234 10235 u8 retransmission_request_admin[0x8]; 10236 u8 fec_mode_request_admin[0x18]; 10237 10238 u8 reserved_at_c0[0x80]; 10239 }; 10240 10241 struct mlx5_ifc_plib_reg_bits { 10242 u8 reserved_at_0[0x8]; 10243 u8 local_port[0x8]; 10244 u8 reserved_at_10[0x8]; 10245 u8 ib_port[0x8]; 10246 10247 u8 reserved_at_20[0x60]; 10248 }; 10249 10250 struct mlx5_ifc_plbf_reg_bits { 10251 u8 reserved_at_0[0x8]; 10252 u8 local_port[0x8]; 10253 u8 reserved_at_10[0xd]; 10254 u8 lbf_mode[0x3]; 10255 10256 u8 reserved_at_20[0x20]; 10257 }; 10258 10259 struct mlx5_ifc_pipg_reg_bits { 10260 u8 reserved_at_0[0x8]; 10261 u8 local_port[0x8]; 10262 u8 reserved_at_10[0x10]; 10263 10264 u8 dic[0x1]; 10265 u8 reserved_at_21[0x19]; 10266 u8 ipg[0x4]; 10267 u8 reserved_at_3e[0x2]; 10268 }; 10269 10270 struct mlx5_ifc_pifr_reg_bits { 10271 u8 reserved_at_0[0x8]; 10272 u8 local_port[0x8]; 10273 u8 reserved_at_10[0x10]; 10274 10275 u8 reserved_at_20[0xe0]; 10276 10277 u8 port_filter[8][0x20]; 10278 10279 u8 port_filter_update_en[8][0x20]; 10280 }; 10281 10282 struct mlx5_ifc_pfcc_reg_bits { 10283 u8 reserved_at_0[0x8]; 10284 u8 local_port[0x8]; 10285 u8 reserved_at_10[0xb]; 10286 u8 ppan_mask_n[0x1]; 10287 u8 minor_stall_mask[0x1]; 10288 u8 critical_stall_mask[0x1]; 10289 u8 reserved_at_1e[0x2]; 10290 10291 u8 ppan[0x4]; 10292 u8 reserved_at_24[0x4]; 10293 u8 prio_mask_tx[0x8]; 10294 u8 reserved_at_30[0x8]; 10295 u8 prio_mask_rx[0x8]; 10296 10297 u8 pptx[0x1]; 10298 u8 aptx[0x1]; 10299 u8 pptx_mask_n[0x1]; 10300 u8 reserved_at_43[0x5]; 10301 u8 pfctx[0x8]; 10302 u8 reserved_at_50[0x10]; 10303 10304 u8 pprx[0x1]; 10305 u8 aprx[0x1]; 10306 u8 pprx_mask_n[0x1]; 10307 u8 reserved_at_63[0x5]; 10308 u8 pfcrx[0x8]; 10309 u8 reserved_at_70[0x10]; 10310 10311 u8 device_stall_minor_watermark[0x10]; 10312 u8 device_stall_critical_watermark[0x10]; 10313 10314 u8 reserved_at_a0[0x60]; 10315 }; 10316 10317 struct mlx5_ifc_pelc_reg_bits { 10318 u8 op[0x4]; 10319 u8 reserved_at_4[0x4]; 10320 u8 local_port[0x8]; 10321 u8 reserved_at_10[0x10]; 10322 10323 u8 op_admin[0x8]; 10324 u8 op_capability[0x8]; 10325 u8 op_request[0x8]; 10326 u8 op_active[0x8]; 10327 10328 u8 admin[0x40]; 10329 10330 u8 capability[0x40]; 10331 10332 u8 request[0x40]; 10333 10334 u8 active[0x40]; 10335 10336 u8 reserved_at_140[0x80]; 10337 }; 10338 10339 struct mlx5_ifc_peir_reg_bits { 10340 u8 reserved_at_0[0x8]; 10341 u8 local_port[0x8]; 10342 u8 reserved_at_10[0x10]; 10343 10344 u8 reserved_at_20[0xc]; 10345 u8 error_count[0x4]; 10346 u8 reserved_at_30[0x10]; 10347 10348 u8 reserved_at_40[0xc]; 10349 u8 lane[0x4]; 10350 u8 reserved_at_50[0x8]; 10351 u8 error_type[0x8]; 10352 }; 10353 10354 struct mlx5_ifc_mpegc_reg_bits { 10355 u8 reserved_at_0[0x30]; 10356 u8 field_select[0x10]; 10357 10358 u8 tx_overflow_sense[0x1]; 10359 u8 mark_cqe[0x1]; 10360 u8 mark_cnp[0x1]; 10361 u8 reserved_at_43[0x1b]; 10362 u8 tx_lossy_overflow_oper[0x2]; 10363 10364 u8 reserved_at_60[0x100]; 10365 }; 10366 10367 struct mlx5_ifc_mpir_reg_bits { 10368 u8 sdm[0x1]; 10369 u8 reserved_at_1[0x1b]; 10370 u8 host_buses[0x4]; 10371 10372 u8 reserved_at_20[0x20]; 10373 10374 u8 local_port[0x8]; 10375 u8 reserved_at_28[0x18]; 10376 10377 u8 reserved_at_60[0x20]; 10378 }; 10379 10380 enum { 10381 MLX5_MTUTC_FREQ_ADJ_UNITS_PPB = 0x0, 10382 MLX5_MTUTC_FREQ_ADJ_UNITS_SCALED_PPM = 0x1, 10383 }; 10384 10385 enum { 10386 MLX5_MTUTC_OPERATION_SET_TIME_IMMEDIATE = 0x1, 10387 MLX5_MTUTC_OPERATION_ADJUST_TIME = 0x2, 10388 MLX5_MTUTC_OPERATION_ADJUST_FREQ_UTC = 0x3, 10389 }; 10390 10391 struct mlx5_ifc_mtutc_reg_bits { 10392 u8 reserved_at_0[0x5]; 10393 u8 freq_adj_units[0x3]; 10394 u8 reserved_at_8[0x3]; 10395 u8 log_max_freq_adjustment[0x5]; 10396 10397 u8 reserved_at_10[0xc]; 10398 u8 operation[0x4]; 10399 10400 u8 freq_adjustment[0x20]; 10401 10402 u8 reserved_at_40[0x40]; 10403 10404 u8 utc_sec[0x20]; 10405 10406 u8 reserved_at_a0[0x2]; 10407 u8 utc_nsec[0x1e]; 10408 10409 u8 time_adjustment[0x20]; 10410 }; 10411 10412 struct mlx5_ifc_pcam_enhanced_features_bits { 10413 u8 reserved_at_0[0x48]; 10414 u8 fec_100G_per_lane_in_pplm[0x1]; 10415 u8 reserved_at_49[0x1f]; 10416 u8 fec_50G_per_lane_in_pplm[0x1]; 10417 u8 reserved_at_69[0x4]; 10418 u8 rx_icrc_encapsulated_counter[0x1]; 10419 u8 reserved_at_6e[0x4]; 10420 u8 ptys_extended_ethernet[0x1]; 10421 u8 reserved_at_73[0x3]; 10422 u8 pfcc_mask[0x1]; 10423 u8 reserved_at_77[0x3]; 10424 u8 per_lane_error_counters[0x1]; 10425 u8 rx_buffer_fullness_counters[0x1]; 10426 u8 ptys_connector_type[0x1]; 10427 u8 reserved_at_7d[0x1]; 10428 u8 ppcnt_discard_group[0x1]; 10429 u8 ppcnt_statistical_group[0x1]; 10430 }; 10431 10432 struct mlx5_ifc_pcam_regs_5000_to_507f_bits { 10433 u8 port_access_reg_cap_mask_127_to_96[0x20]; 10434 u8 port_access_reg_cap_mask_95_to_64[0x20]; 10435 10436 u8 port_access_reg_cap_mask_63_to_36[0x1c]; 10437 u8 pplm[0x1]; 10438 u8 port_access_reg_cap_mask_34_to_32[0x3]; 10439 10440 u8 port_access_reg_cap_mask_31_to_13[0x13]; 10441 u8 pbmc[0x1]; 10442 u8 pptb[0x1]; 10443 u8 port_access_reg_cap_mask_10_to_09[0x2]; 10444 u8 ppcnt[0x1]; 10445 u8 port_access_reg_cap_mask_07_to_00[0x8]; 10446 }; 10447 10448 struct mlx5_ifc_pcam_reg_bits { 10449 u8 reserved_at_0[0x8]; 10450 u8 feature_group[0x8]; 10451 u8 reserved_at_10[0x8]; 10452 u8 access_reg_group[0x8]; 10453 10454 u8 reserved_at_20[0x20]; 10455 10456 union { 10457 struct mlx5_ifc_pcam_regs_5000_to_507f_bits regs_5000_to_507f; 10458 u8 reserved_at_0[0x80]; 10459 } port_access_reg_cap_mask; 10460 10461 u8 reserved_at_c0[0x80]; 10462 10463 union { 10464 struct mlx5_ifc_pcam_enhanced_features_bits enhanced_features; 10465 u8 reserved_at_0[0x80]; 10466 } feature_cap_mask; 10467 10468 u8 reserved_at_1c0[0xc0]; 10469 }; 10470 10471 struct mlx5_ifc_mcam_enhanced_features_bits { 10472 u8 reserved_at_0[0x50]; 10473 u8 mtutc_freq_adj_units[0x1]; 10474 u8 mtutc_time_adjustment_extended_range[0x1]; 10475 u8 reserved_at_52[0xb]; 10476 u8 mcia_32dwords[0x1]; 10477 u8 out_pulse_duration_ns[0x1]; 10478 u8 npps_period[0x1]; 10479 u8 reserved_at_60[0xa]; 10480 u8 reset_state[0x1]; 10481 u8 ptpcyc2realtime_modify[0x1]; 10482 u8 reserved_at_6c[0x2]; 10483 u8 pci_status_and_power[0x1]; 10484 u8 reserved_at_6f[0x5]; 10485 u8 mark_tx_action_cnp[0x1]; 10486 u8 mark_tx_action_cqe[0x1]; 10487 u8 dynamic_tx_overflow[0x1]; 10488 u8 reserved_at_77[0x4]; 10489 u8 pcie_outbound_stalled[0x1]; 10490 u8 tx_overflow_buffer_pkt[0x1]; 10491 u8 mtpps_enh_out_per_adj[0x1]; 10492 u8 mtpps_fs[0x1]; 10493 u8 pcie_performance_group[0x1]; 10494 }; 10495 10496 struct mlx5_ifc_mcam_access_reg_bits { 10497 u8 reserved_at_0[0x1c]; 10498 u8 mcda[0x1]; 10499 u8 mcc[0x1]; 10500 u8 mcqi[0x1]; 10501 u8 mcqs[0x1]; 10502 10503 u8 regs_95_to_90[0x6]; 10504 u8 mpir[0x1]; 10505 u8 regs_88_to_87[0x2]; 10506 u8 mpegc[0x1]; 10507 u8 mtutc[0x1]; 10508 u8 regs_84_to_68[0x11]; 10509 u8 tracer_registers[0x4]; 10510 10511 u8 regs_63_to_46[0x12]; 10512 u8 mrtc[0x1]; 10513 u8 regs_44_to_41[0x4]; 10514 u8 mfrl[0x1]; 10515 u8 regs_39_to_32[0x8]; 10516 10517 u8 regs_31_to_11[0x15]; 10518 u8 mtmp[0x1]; 10519 u8 regs_9_to_0[0xa]; 10520 }; 10521 10522 struct mlx5_ifc_mcam_access_reg_bits1 { 10523 u8 regs_127_to_96[0x20]; 10524 10525 u8 regs_95_to_64[0x20]; 10526 10527 u8 regs_63_to_32[0x20]; 10528 10529 u8 regs_31_to_0[0x20]; 10530 }; 10531 10532 struct mlx5_ifc_mcam_access_reg_bits2 { 10533 u8 regs_127_to_99[0x1d]; 10534 u8 mirc[0x1]; 10535 u8 regs_97_to_96[0x2]; 10536 10537 u8 regs_95_to_87[0x09]; 10538 u8 synce_registers[0x2]; 10539 u8 regs_84_to_64[0x15]; 10540 10541 u8 regs_63_to_32[0x20]; 10542 10543 u8 regs_31_to_0[0x20]; 10544 }; 10545 10546 struct mlx5_ifc_mcam_access_reg_bits3 { 10547 u8 regs_127_to_96[0x20]; 10548 10549 u8 regs_95_to_64[0x20]; 10550 10551 u8 regs_63_to_32[0x20]; 10552 10553 u8 regs_31_to_2[0x1e]; 10554 u8 mtctr[0x1]; 10555 u8 mtptm[0x1]; 10556 }; 10557 10558 struct mlx5_ifc_mcam_reg_bits { 10559 u8 reserved_at_0[0x8]; 10560 u8 feature_group[0x8]; 10561 u8 reserved_at_10[0x8]; 10562 u8 access_reg_group[0x8]; 10563 10564 u8 reserved_at_20[0x20]; 10565 10566 union { 10567 struct mlx5_ifc_mcam_access_reg_bits access_regs; 10568 struct mlx5_ifc_mcam_access_reg_bits1 access_regs1; 10569 struct mlx5_ifc_mcam_access_reg_bits2 access_regs2; 10570 struct mlx5_ifc_mcam_access_reg_bits3 access_regs3; 10571 u8 reserved_at_0[0x80]; 10572 } mng_access_reg_cap_mask; 10573 10574 u8 reserved_at_c0[0x80]; 10575 10576 union { 10577 struct mlx5_ifc_mcam_enhanced_features_bits enhanced_features; 10578 u8 reserved_at_0[0x80]; 10579 } mng_feature_cap_mask; 10580 10581 u8 reserved_at_1c0[0x80]; 10582 }; 10583 10584 struct mlx5_ifc_qcam_access_reg_cap_mask { 10585 u8 qcam_access_reg_cap_mask_127_to_20[0x6C]; 10586 u8 qpdpm[0x1]; 10587 u8 qcam_access_reg_cap_mask_18_to_4[0x0F]; 10588 u8 qdpm[0x1]; 10589 u8 qpts[0x1]; 10590 u8 qcap[0x1]; 10591 u8 qcam_access_reg_cap_mask_0[0x1]; 10592 }; 10593 10594 struct mlx5_ifc_qcam_qos_feature_cap_mask { 10595 u8 qcam_qos_feature_cap_mask_127_to_1[0x7F]; 10596 u8 qpts_trust_both[0x1]; 10597 }; 10598 10599 struct mlx5_ifc_qcam_reg_bits { 10600 u8 reserved_at_0[0x8]; 10601 u8 feature_group[0x8]; 10602 u8 reserved_at_10[0x8]; 10603 u8 access_reg_group[0x8]; 10604 u8 reserved_at_20[0x20]; 10605 10606 union { 10607 struct mlx5_ifc_qcam_access_reg_cap_mask reg_cap; 10608 u8 reserved_at_0[0x80]; 10609 } qos_access_reg_cap_mask; 10610 10611 u8 reserved_at_c0[0x80]; 10612 10613 union { 10614 struct mlx5_ifc_qcam_qos_feature_cap_mask feature_cap; 10615 u8 reserved_at_0[0x80]; 10616 } qos_feature_cap_mask; 10617 10618 u8 reserved_at_1c0[0x80]; 10619 }; 10620 10621 struct mlx5_ifc_core_dump_reg_bits { 10622 u8 reserved_at_0[0x18]; 10623 u8 core_dump_type[0x8]; 10624 10625 u8 reserved_at_20[0x30]; 10626 u8 vhca_id[0x10]; 10627 10628 u8 reserved_at_60[0x8]; 10629 u8 qpn[0x18]; 10630 u8 reserved_at_80[0x180]; 10631 }; 10632 10633 struct mlx5_ifc_pcap_reg_bits { 10634 u8 reserved_at_0[0x8]; 10635 u8 local_port[0x8]; 10636 u8 reserved_at_10[0x10]; 10637 10638 u8 port_capability_mask[4][0x20]; 10639 }; 10640 10641 struct mlx5_ifc_paos_reg_bits { 10642 u8 swid[0x8]; 10643 u8 local_port[0x8]; 10644 u8 reserved_at_10[0x4]; 10645 u8 admin_status[0x4]; 10646 u8 reserved_at_18[0x4]; 10647 u8 oper_status[0x4]; 10648 10649 u8 ase[0x1]; 10650 u8 ee[0x1]; 10651 u8 reserved_at_22[0x1c]; 10652 u8 e[0x2]; 10653 10654 u8 reserved_at_40[0x40]; 10655 }; 10656 10657 struct mlx5_ifc_pamp_reg_bits { 10658 u8 reserved_at_0[0x8]; 10659 u8 opamp_group[0x8]; 10660 u8 reserved_at_10[0xc]; 10661 u8 opamp_group_type[0x4]; 10662 10663 u8 start_index[0x10]; 10664 u8 reserved_at_30[0x4]; 10665 u8 num_of_indices[0xc]; 10666 10667 u8 index_data[18][0x10]; 10668 }; 10669 10670 struct mlx5_ifc_pcmr_reg_bits { 10671 u8 reserved_at_0[0x8]; 10672 u8 local_port[0x8]; 10673 u8 reserved_at_10[0x10]; 10674 10675 u8 entropy_force_cap[0x1]; 10676 u8 entropy_calc_cap[0x1]; 10677 u8 entropy_gre_calc_cap[0x1]; 10678 u8 reserved_at_23[0xf]; 10679 u8 rx_ts_over_crc_cap[0x1]; 10680 u8 reserved_at_33[0xb]; 10681 u8 fcs_cap[0x1]; 10682 u8 reserved_at_3f[0x1]; 10683 10684 u8 entropy_force[0x1]; 10685 u8 entropy_calc[0x1]; 10686 u8 entropy_gre_calc[0x1]; 10687 u8 reserved_at_43[0xf]; 10688 u8 rx_ts_over_crc[0x1]; 10689 u8 reserved_at_53[0xb]; 10690 u8 fcs_chk[0x1]; 10691 u8 reserved_at_5f[0x1]; 10692 }; 10693 10694 struct mlx5_ifc_lane_2_module_mapping_bits { 10695 u8 reserved_at_0[0x4]; 10696 u8 rx_lane[0x4]; 10697 u8 reserved_at_8[0x4]; 10698 u8 tx_lane[0x4]; 10699 u8 reserved_at_10[0x8]; 10700 u8 module[0x8]; 10701 }; 10702 10703 struct mlx5_ifc_bufferx_reg_bits { 10704 u8 reserved_at_0[0x6]; 10705 u8 lossy[0x1]; 10706 u8 epsb[0x1]; 10707 u8 reserved_at_8[0x8]; 10708 u8 size[0x10]; 10709 10710 u8 xoff_threshold[0x10]; 10711 u8 xon_threshold[0x10]; 10712 }; 10713 10714 struct mlx5_ifc_set_node_in_bits { 10715 u8 node_description[64][0x8]; 10716 }; 10717 10718 struct mlx5_ifc_register_power_settings_bits { 10719 u8 reserved_at_0[0x18]; 10720 u8 power_settings_level[0x8]; 10721 10722 u8 reserved_at_20[0x60]; 10723 }; 10724 10725 struct mlx5_ifc_register_host_endianness_bits { 10726 u8 he[0x1]; 10727 u8 reserved_at_1[0x1f]; 10728 10729 u8 reserved_at_20[0x60]; 10730 }; 10731 10732 struct mlx5_ifc_umr_pointer_desc_argument_bits { 10733 u8 reserved_at_0[0x20]; 10734 10735 u8 mkey[0x20]; 10736 10737 u8 addressh_63_32[0x20]; 10738 10739 u8 addressl_31_0[0x20]; 10740 }; 10741 10742 struct mlx5_ifc_ud_adrs_vector_bits { 10743 u8 dc_key[0x40]; 10744 10745 u8 ext[0x1]; 10746 u8 reserved_at_41[0x7]; 10747 u8 destination_qp_dct[0x18]; 10748 10749 u8 static_rate[0x4]; 10750 u8 sl_eth_prio[0x4]; 10751 u8 fl[0x1]; 10752 u8 mlid[0x7]; 10753 u8 rlid_udp_sport[0x10]; 10754 10755 u8 reserved_at_80[0x20]; 10756 10757 u8 rmac_47_16[0x20]; 10758 10759 u8 rmac_15_0[0x10]; 10760 u8 tclass[0x8]; 10761 u8 hop_limit[0x8]; 10762 10763 u8 reserved_at_e0[0x1]; 10764 u8 grh[0x1]; 10765 u8 reserved_at_e2[0x2]; 10766 u8 src_addr_index[0x8]; 10767 u8 flow_label[0x14]; 10768 10769 u8 rgid_rip[16][0x8]; 10770 }; 10771 10772 struct mlx5_ifc_pages_req_event_bits { 10773 u8 reserved_at_0[0x10]; 10774 u8 function_id[0x10]; 10775 10776 u8 num_pages[0x20]; 10777 10778 u8 reserved_at_40[0xa0]; 10779 }; 10780 10781 struct mlx5_ifc_eqe_bits { 10782 u8 reserved_at_0[0x8]; 10783 u8 event_type[0x8]; 10784 u8 reserved_at_10[0x8]; 10785 u8 event_sub_type[0x8]; 10786 10787 u8 reserved_at_20[0xe0]; 10788 10789 union mlx5_ifc_event_auto_bits event_data; 10790 10791 u8 reserved_at_1e0[0x10]; 10792 u8 signature[0x8]; 10793 u8 reserved_at_1f8[0x7]; 10794 u8 owner[0x1]; 10795 }; 10796 10797 enum { 10798 MLX5_CMD_QUEUE_ENTRY_TYPE_PCIE_CMD_IF_TRANSPORT = 0x7, 10799 }; 10800 10801 struct mlx5_ifc_cmd_queue_entry_bits { 10802 u8 type[0x8]; 10803 u8 reserved_at_8[0x18]; 10804 10805 u8 input_length[0x20]; 10806 10807 u8 input_mailbox_pointer_63_32[0x20]; 10808 10809 u8 input_mailbox_pointer_31_9[0x17]; 10810 u8 reserved_at_77[0x9]; 10811 10812 u8 command_input_inline_data[16][0x8]; 10813 10814 u8 command_output_inline_data[16][0x8]; 10815 10816 u8 output_mailbox_pointer_63_32[0x20]; 10817 10818 u8 output_mailbox_pointer_31_9[0x17]; 10819 u8 reserved_at_1b7[0x9]; 10820 10821 u8 output_length[0x20]; 10822 10823 u8 token[0x8]; 10824 u8 signature[0x8]; 10825 u8 reserved_at_1f0[0x8]; 10826 u8 status[0x7]; 10827 u8 ownership[0x1]; 10828 }; 10829 10830 struct mlx5_ifc_cmd_out_bits { 10831 u8 status[0x8]; 10832 u8 reserved_at_8[0x18]; 10833 10834 u8 syndrome[0x20]; 10835 10836 u8 command_output[0x20]; 10837 }; 10838 10839 struct mlx5_ifc_cmd_in_bits { 10840 u8 opcode[0x10]; 10841 u8 reserved_at_10[0x10]; 10842 10843 u8 reserved_at_20[0x10]; 10844 u8 op_mod[0x10]; 10845 10846 u8 command[][0x20]; 10847 }; 10848 10849 struct mlx5_ifc_cmd_if_box_bits { 10850 u8 mailbox_data[512][0x8]; 10851 10852 u8 reserved_at_1000[0x180]; 10853 10854 u8 next_pointer_63_32[0x20]; 10855 10856 u8 next_pointer_31_10[0x16]; 10857 u8 reserved_at_11b6[0xa]; 10858 10859 u8 block_number[0x20]; 10860 10861 u8 reserved_at_11e0[0x8]; 10862 u8 token[0x8]; 10863 u8 ctrl_signature[0x8]; 10864 u8 signature[0x8]; 10865 }; 10866 10867 struct mlx5_ifc_mtt_bits { 10868 u8 ptag_63_32[0x20]; 10869 10870 u8 ptag_31_8[0x18]; 10871 u8 reserved_at_38[0x6]; 10872 u8 wr_en[0x1]; 10873 u8 rd_en[0x1]; 10874 }; 10875 10876 struct mlx5_ifc_query_wol_rol_out_bits { 10877 u8 status[0x8]; 10878 u8 reserved_at_8[0x18]; 10879 10880 u8 syndrome[0x20]; 10881 10882 u8 reserved_at_40[0x10]; 10883 u8 rol_mode[0x8]; 10884 u8 wol_mode[0x8]; 10885 10886 u8 reserved_at_60[0x20]; 10887 }; 10888 10889 struct mlx5_ifc_query_wol_rol_in_bits { 10890 u8 opcode[0x10]; 10891 u8 reserved_at_10[0x10]; 10892 10893 u8 reserved_at_20[0x10]; 10894 u8 op_mod[0x10]; 10895 10896 u8 reserved_at_40[0x40]; 10897 }; 10898 10899 struct mlx5_ifc_set_wol_rol_out_bits { 10900 u8 status[0x8]; 10901 u8 reserved_at_8[0x18]; 10902 10903 u8 syndrome[0x20]; 10904 10905 u8 reserved_at_40[0x40]; 10906 }; 10907 10908 struct mlx5_ifc_set_wol_rol_in_bits { 10909 u8 opcode[0x10]; 10910 u8 reserved_at_10[0x10]; 10911 10912 u8 reserved_at_20[0x10]; 10913 u8 op_mod[0x10]; 10914 10915 u8 rol_mode_valid[0x1]; 10916 u8 wol_mode_valid[0x1]; 10917 u8 reserved_at_42[0xe]; 10918 u8 rol_mode[0x8]; 10919 u8 wol_mode[0x8]; 10920 10921 u8 reserved_at_60[0x20]; 10922 }; 10923 10924 enum { 10925 MLX5_INITIAL_SEG_NIC_INTERFACE_FULL_DRIVER = 0x0, 10926 MLX5_INITIAL_SEG_NIC_INTERFACE_DISABLED = 0x1, 10927 MLX5_INITIAL_SEG_NIC_INTERFACE_NO_DRAM_NIC = 0x2, 10928 MLX5_INITIAL_SEG_NIC_INTERFACE_SW_RESET = 0x7, 10929 }; 10930 10931 enum { 10932 MLX5_INITIAL_SEG_NIC_INTERFACE_SUPPORTED_FULL_DRIVER = 0x0, 10933 MLX5_INITIAL_SEG_NIC_INTERFACE_SUPPORTED_DISABLED = 0x1, 10934 MLX5_INITIAL_SEG_NIC_INTERFACE_SUPPORTED_NO_DRAM_NIC = 0x2, 10935 }; 10936 10937 enum { 10938 MLX5_INITIAL_SEG_HEALTH_SYNDROME_FW_INTERNAL_ERR = 0x1, 10939 MLX5_INITIAL_SEG_HEALTH_SYNDROME_DEAD_IRISC = 0x7, 10940 MLX5_INITIAL_SEG_HEALTH_SYNDROME_HW_FATAL_ERR = 0x8, 10941 MLX5_INITIAL_SEG_HEALTH_SYNDROME_FW_CRC_ERR = 0x9, 10942 MLX5_INITIAL_SEG_HEALTH_SYNDROME_ICM_FETCH_PCI_ERR = 0xa, 10943 MLX5_INITIAL_SEG_HEALTH_SYNDROME_ICM_PAGE_ERR = 0xb, 10944 MLX5_INITIAL_SEG_HEALTH_SYNDROME_ASYNCHRONOUS_EQ_BUF_OVERRUN = 0xc, 10945 MLX5_INITIAL_SEG_HEALTH_SYNDROME_EQ_IN_ERR = 0xd, 10946 MLX5_INITIAL_SEG_HEALTH_SYNDROME_EQ_INV = 0xe, 10947 MLX5_INITIAL_SEG_HEALTH_SYNDROME_FFSER_ERR = 0xf, 10948 MLX5_INITIAL_SEG_HEALTH_SYNDROME_HIGH_TEMP_ERR = 0x10, 10949 MLX5_INITIAL_SEG_HEALTH_SYNDROME_ICM_PCI_POISONED_ERR = 0x12, 10950 }; 10951 10952 struct mlx5_ifc_initial_seg_bits { 10953 u8 fw_rev_minor[0x10]; 10954 u8 fw_rev_major[0x10]; 10955 10956 u8 cmd_interface_rev[0x10]; 10957 u8 fw_rev_subminor[0x10]; 10958 10959 u8 reserved_at_40[0x40]; 10960 10961 u8 cmdq_phy_addr_63_32[0x20]; 10962 10963 u8 cmdq_phy_addr_31_12[0x14]; 10964 u8 reserved_at_b4[0x2]; 10965 u8 nic_interface[0x2]; 10966 u8 log_cmdq_size[0x4]; 10967 u8 log_cmdq_stride[0x4]; 10968 10969 u8 command_doorbell_vector[0x20]; 10970 10971 u8 reserved_at_e0[0xf00]; 10972 10973 u8 initializing[0x1]; 10974 u8 reserved_at_fe1[0x4]; 10975 u8 nic_interface_supported[0x3]; 10976 u8 embedded_cpu[0x1]; 10977 u8 reserved_at_fe9[0x17]; 10978 10979 struct mlx5_ifc_health_buffer_bits health_buffer; 10980 10981 u8 no_dram_nic_offset[0x20]; 10982 10983 u8 reserved_at_1220[0x6e40]; 10984 10985 u8 reserved_at_8060[0x1f]; 10986 u8 clear_int[0x1]; 10987 10988 u8 health_syndrome[0x8]; 10989 u8 health_counter[0x18]; 10990 10991 u8 reserved_at_80a0[0x17fc0]; 10992 }; 10993 10994 struct mlx5_ifc_mtpps_reg_bits { 10995 u8 reserved_at_0[0xc]; 10996 u8 cap_number_of_pps_pins[0x4]; 10997 u8 reserved_at_10[0x4]; 10998 u8 cap_max_num_of_pps_in_pins[0x4]; 10999 u8 reserved_at_18[0x4]; 11000 u8 cap_max_num_of_pps_out_pins[0x4]; 11001 11002 u8 reserved_at_20[0x13]; 11003 u8 cap_log_min_npps_period[0x5]; 11004 u8 reserved_at_38[0x3]; 11005 u8 cap_log_min_out_pulse_duration_ns[0x5]; 11006 11007 u8 reserved_at_40[0x4]; 11008 u8 cap_pin_3_mode[0x4]; 11009 u8 reserved_at_48[0x4]; 11010 u8 cap_pin_2_mode[0x4]; 11011 u8 reserved_at_50[0x4]; 11012 u8 cap_pin_1_mode[0x4]; 11013 u8 reserved_at_58[0x4]; 11014 u8 cap_pin_0_mode[0x4]; 11015 11016 u8 reserved_at_60[0x4]; 11017 u8 cap_pin_7_mode[0x4]; 11018 u8 reserved_at_68[0x4]; 11019 u8 cap_pin_6_mode[0x4]; 11020 u8 reserved_at_70[0x4]; 11021 u8 cap_pin_5_mode[0x4]; 11022 u8 reserved_at_78[0x4]; 11023 u8 cap_pin_4_mode[0x4]; 11024 11025 u8 field_select[0x20]; 11026 u8 reserved_at_a0[0x20]; 11027 11028 u8 npps_period[0x40]; 11029 11030 u8 enable[0x1]; 11031 u8 reserved_at_101[0xb]; 11032 u8 pattern[0x4]; 11033 u8 reserved_at_110[0x4]; 11034 u8 pin_mode[0x4]; 11035 u8 pin[0x8]; 11036 11037 u8 reserved_at_120[0x2]; 11038 u8 out_pulse_duration_ns[0x1e]; 11039 11040 u8 time_stamp[0x40]; 11041 11042 u8 out_pulse_duration[0x10]; 11043 u8 out_periodic_adjustment[0x10]; 11044 u8 enhanced_out_periodic_adjustment[0x20]; 11045 11046 u8 reserved_at_1c0[0x20]; 11047 }; 11048 11049 struct mlx5_ifc_mtppse_reg_bits { 11050 u8 reserved_at_0[0x18]; 11051 u8 pin[0x8]; 11052 u8 event_arm[0x1]; 11053 u8 reserved_at_21[0x1b]; 11054 u8 event_generation_mode[0x4]; 11055 u8 reserved_at_40[0x40]; 11056 }; 11057 11058 struct mlx5_ifc_mcqs_reg_bits { 11059 u8 last_index_flag[0x1]; 11060 u8 reserved_at_1[0x7]; 11061 u8 fw_device[0x8]; 11062 u8 component_index[0x10]; 11063 11064 u8 reserved_at_20[0x10]; 11065 u8 identifier[0x10]; 11066 11067 u8 reserved_at_40[0x17]; 11068 u8 component_status[0x5]; 11069 u8 component_update_state[0x4]; 11070 11071 u8 last_update_state_changer_type[0x4]; 11072 u8 last_update_state_changer_host_id[0x4]; 11073 u8 reserved_at_68[0x18]; 11074 }; 11075 11076 struct mlx5_ifc_mcqi_cap_bits { 11077 u8 supported_info_bitmask[0x20]; 11078 11079 u8 component_size[0x20]; 11080 11081 u8 max_component_size[0x20]; 11082 11083 u8 log_mcda_word_size[0x4]; 11084 u8 reserved_at_64[0xc]; 11085 u8 mcda_max_write_size[0x10]; 11086 11087 u8 rd_en[0x1]; 11088 u8 reserved_at_81[0x1]; 11089 u8 match_chip_id[0x1]; 11090 u8 match_psid[0x1]; 11091 u8 check_user_timestamp[0x1]; 11092 u8 match_base_guid_mac[0x1]; 11093 u8 reserved_at_86[0x1a]; 11094 }; 11095 11096 struct mlx5_ifc_mcqi_version_bits { 11097 u8 reserved_at_0[0x2]; 11098 u8 build_time_valid[0x1]; 11099 u8 user_defined_time_valid[0x1]; 11100 u8 reserved_at_4[0x14]; 11101 u8 version_string_length[0x8]; 11102 11103 u8 version[0x20]; 11104 11105 u8 build_time[0x40]; 11106 11107 u8 user_defined_time[0x40]; 11108 11109 u8 build_tool_version[0x20]; 11110 11111 u8 reserved_at_e0[0x20]; 11112 11113 u8 version_string[92][0x8]; 11114 }; 11115 11116 struct mlx5_ifc_mcqi_activation_method_bits { 11117 u8 pending_server_ac_power_cycle[0x1]; 11118 u8 pending_server_dc_power_cycle[0x1]; 11119 u8 pending_server_reboot[0x1]; 11120 u8 pending_fw_reset[0x1]; 11121 u8 auto_activate[0x1]; 11122 u8 all_hosts_sync[0x1]; 11123 u8 device_hw_reset[0x1]; 11124 u8 reserved_at_7[0x19]; 11125 }; 11126 11127 union mlx5_ifc_mcqi_reg_data_bits { 11128 struct mlx5_ifc_mcqi_cap_bits mcqi_caps; 11129 struct mlx5_ifc_mcqi_version_bits mcqi_version; 11130 struct mlx5_ifc_mcqi_activation_method_bits mcqi_activation_mathod; 11131 }; 11132 11133 struct mlx5_ifc_mcqi_reg_bits { 11134 u8 read_pending_component[0x1]; 11135 u8 reserved_at_1[0xf]; 11136 u8 component_index[0x10]; 11137 11138 u8 reserved_at_20[0x20]; 11139 11140 u8 reserved_at_40[0x1b]; 11141 u8 info_type[0x5]; 11142 11143 u8 info_size[0x20]; 11144 11145 u8 offset[0x20]; 11146 11147 u8 reserved_at_a0[0x10]; 11148 u8 data_size[0x10]; 11149 11150 union mlx5_ifc_mcqi_reg_data_bits data[]; 11151 }; 11152 11153 struct mlx5_ifc_mcc_reg_bits { 11154 u8 reserved_at_0[0x4]; 11155 u8 time_elapsed_since_last_cmd[0xc]; 11156 u8 reserved_at_10[0x8]; 11157 u8 instruction[0x8]; 11158 11159 u8 reserved_at_20[0x10]; 11160 u8 component_index[0x10]; 11161 11162 u8 reserved_at_40[0x8]; 11163 u8 update_handle[0x18]; 11164 11165 u8 handle_owner_type[0x4]; 11166 u8 handle_owner_host_id[0x4]; 11167 u8 reserved_at_68[0x1]; 11168 u8 control_progress[0x7]; 11169 u8 error_code[0x8]; 11170 u8 reserved_at_78[0x4]; 11171 u8 control_state[0x4]; 11172 11173 u8 component_size[0x20]; 11174 11175 u8 reserved_at_a0[0x60]; 11176 }; 11177 11178 struct mlx5_ifc_mcda_reg_bits { 11179 u8 reserved_at_0[0x8]; 11180 u8 update_handle[0x18]; 11181 11182 u8 offset[0x20]; 11183 11184 u8 reserved_at_40[0x10]; 11185 u8 size[0x10]; 11186 11187 u8 reserved_at_60[0x20]; 11188 11189 u8 data[][0x20]; 11190 }; 11191 11192 enum { 11193 MLX5_MFRL_REG_PCI_RESET_METHOD_LINK_TOGGLE = 0, 11194 MLX5_MFRL_REG_PCI_RESET_METHOD_HOT_RESET = 1, 11195 }; 11196 11197 enum { 11198 MLX5_MFRL_REG_RESET_STATE_IDLE = 0, 11199 MLX5_MFRL_REG_RESET_STATE_IN_NEGOTIATION = 1, 11200 MLX5_MFRL_REG_RESET_STATE_RESET_IN_PROGRESS = 2, 11201 MLX5_MFRL_REG_RESET_STATE_NEG_TIMEOUT = 3, 11202 MLX5_MFRL_REG_RESET_STATE_NACK = 4, 11203 MLX5_MFRL_REG_RESET_STATE_UNLOAD_TIMEOUT = 5, 11204 }; 11205 11206 enum { 11207 MLX5_MFRL_REG_RESET_TYPE_FULL_CHIP = BIT(0), 11208 MLX5_MFRL_REG_RESET_TYPE_NET_PORT_ALIVE = BIT(1), 11209 }; 11210 11211 enum { 11212 MLX5_MFRL_REG_RESET_LEVEL0 = BIT(0), 11213 MLX5_MFRL_REG_RESET_LEVEL3 = BIT(3), 11214 MLX5_MFRL_REG_RESET_LEVEL6 = BIT(6), 11215 }; 11216 11217 struct mlx5_ifc_mfrl_reg_bits { 11218 u8 reserved_at_0[0x20]; 11219 11220 u8 reserved_at_20[0x2]; 11221 u8 pci_sync_for_fw_update_start[0x1]; 11222 u8 pci_sync_for_fw_update_resp[0x2]; 11223 u8 rst_type_sel[0x3]; 11224 u8 pci_reset_req_method[0x3]; 11225 u8 reserved_at_2b[0x1]; 11226 u8 reset_state[0x4]; 11227 u8 reset_type[0x8]; 11228 u8 reset_level[0x8]; 11229 }; 11230 11231 struct mlx5_ifc_mirc_reg_bits { 11232 u8 reserved_at_0[0x18]; 11233 u8 status_code[0x8]; 11234 11235 u8 reserved_at_20[0x20]; 11236 }; 11237 11238 struct mlx5_ifc_pddr_monitor_opcode_bits { 11239 u8 reserved_at_0[0x10]; 11240 u8 monitor_opcode[0x10]; 11241 }; 11242 11243 union mlx5_ifc_pddr_troubleshooting_page_status_opcode_auto_bits { 11244 struct mlx5_ifc_pddr_monitor_opcode_bits pddr_monitor_opcode; 11245 u8 reserved_at_0[0x20]; 11246 }; 11247 11248 enum { 11249 /* Monitor opcodes */ 11250 MLX5_PDDR_REG_TRBLSH_GROUP_OPCODE_MONITOR = 0x0, 11251 }; 11252 11253 struct mlx5_ifc_pddr_troubleshooting_page_bits { 11254 u8 reserved_at_0[0x10]; 11255 u8 group_opcode[0x10]; 11256 11257 union mlx5_ifc_pddr_troubleshooting_page_status_opcode_auto_bits status_opcode; 11258 11259 u8 reserved_at_40[0x20]; 11260 11261 u8 status_message[59][0x20]; 11262 }; 11263 11264 union mlx5_ifc_pddr_reg_page_data_auto_bits { 11265 struct mlx5_ifc_pddr_troubleshooting_page_bits pddr_troubleshooting_page; 11266 u8 reserved_at_0[0x7c0]; 11267 }; 11268 11269 enum { 11270 MLX5_PDDR_REG_PAGE_SELECT_TROUBLESHOOTING_INFO_PAGE = 0x1, 11271 }; 11272 11273 struct mlx5_ifc_pddr_reg_bits { 11274 u8 reserved_at_0[0x8]; 11275 u8 local_port[0x8]; 11276 u8 pnat[0x2]; 11277 u8 reserved_at_12[0xe]; 11278 11279 u8 reserved_at_20[0x18]; 11280 u8 page_select[0x8]; 11281 11282 union mlx5_ifc_pddr_reg_page_data_auto_bits page_data; 11283 }; 11284 11285 struct mlx5_ifc_mrtc_reg_bits { 11286 u8 time_synced[0x1]; 11287 u8 reserved_at_1[0x1f]; 11288 11289 u8 reserved_at_20[0x20]; 11290 11291 u8 time_h[0x20]; 11292 11293 u8 time_l[0x20]; 11294 }; 11295 11296 struct mlx5_ifc_mtcap_reg_bits { 11297 u8 reserved_at_0[0x19]; 11298 u8 sensor_count[0x7]; 11299 11300 u8 reserved_at_20[0x20]; 11301 11302 u8 sensor_map[0x40]; 11303 }; 11304 11305 struct mlx5_ifc_mtmp_reg_bits { 11306 u8 reserved_at_0[0x14]; 11307 u8 sensor_index[0xc]; 11308 11309 u8 reserved_at_20[0x10]; 11310 u8 temperature[0x10]; 11311 11312 u8 mte[0x1]; 11313 u8 mtr[0x1]; 11314 u8 reserved_at_42[0xe]; 11315 u8 max_temperature[0x10]; 11316 11317 u8 tee[0x2]; 11318 u8 reserved_at_62[0xe]; 11319 u8 temp_threshold_hi[0x10]; 11320 11321 u8 reserved_at_80[0x10]; 11322 u8 temp_threshold_lo[0x10]; 11323 11324 u8 reserved_at_a0[0x20]; 11325 11326 u8 sensor_name_hi[0x20]; 11327 u8 sensor_name_lo[0x20]; 11328 }; 11329 11330 struct mlx5_ifc_mtptm_reg_bits { 11331 u8 reserved_at_0[0x10]; 11332 u8 psta[0x1]; 11333 u8 reserved_at_11[0xf]; 11334 11335 u8 reserved_at_20[0x60]; 11336 }; 11337 11338 enum { 11339 MLX5_MTCTR_REQUEST_NOP = 0x0, 11340 MLX5_MTCTR_REQUEST_PTM_ROOT_CLOCK = 0x1, 11341 MLX5_MTCTR_REQUEST_FREE_RUNNING_COUNTER = 0x2, 11342 MLX5_MTCTR_REQUEST_REAL_TIME_CLOCK = 0x3, 11343 }; 11344 11345 struct mlx5_ifc_mtctr_reg_bits { 11346 u8 first_clock_timestamp_request[0x8]; 11347 u8 second_clock_timestamp_request[0x8]; 11348 u8 reserved_at_10[0x10]; 11349 11350 u8 first_clock_valid[0x1]; 11351 u8 second_clock_valid[0x1]; 11352 u8 reserved_at_22[0x1e]; 11353 11354 u8 first_clock_timestamp[0x40]; 11355 u8 second_clock_timestamp[0x40]; 11356 }; 11357 11358 union mlx5_ifc_ports_control_registers_document_bits { 11359 struct mlx5_ifc_bufferx_reg_bits bufferx_reg; 11360 struct mlx5_ifc_eth_2819_cntrs_grp_data_layout_bits eth_2819_cntrs_grp_data_layout; 11361 struct mlx5_ifc_eth_2863_cntrs_grp_data_layout_bits eth_2863_cntrs_grp_data_layout; 11362 struct mlx5_ifc_eth_3635_cntrs_grp_data_layout_bits eth_3635_cntrs_grp_data_layout; 11363 struct mlx5_ifc_eth_802_3_cntrs_grp_data_layout_bits eth_802_3_cntrs_grp_data_layout; 11364 struct mlx5_ifc_eth_extended_cntrs_grp_data_layout_bits eth_extended_cntrs_grp_data_layout; 11365 struct mlx5_ifc_eth_per_prio_grp_data_layout_bits eth_per_prio_grp_data_layout; 11366 struct mlx5_ifc_eth_per_tc_prio_grp_data_layout_bits eth_per_tc_prio_grp_data_layout; 11367 struct mlx5_ifc_eth_per_tc_congest_prio_grp_data_layout_bits eth_per_tc_congest_prio_grp_data_layout; 11368 struct mlx5_ifc_lane_2_module_mapping_bits lane_2_module_mapping; 11369 struct mlx5_ifc_pamp_reg_bits pamp_reg; 11370 struct mlx5_ifc_paos_reg_bits paos_reg; 11371 struct mlx5_ifc_pcap_reg_bits pcap_reg; 11372 struct mlx5_ifc_pddr_monitor_opcode_bits pddr_monitor_opcode; 11373 struct mlx5_ifc_pddr_reg_bits pddr_reg; 11374 struct mlx5_ifc_pddr_troubleshooting_page_bits pddr_troubleshooting_page; 11375 struct mlx5_ifc_peir_reg_bits peir_reg; 11376 struct mlx5_ifc_pelc_reg_bits pelc_reg; 11377 struct mlx5_ifc_pfcc_reg_bits pfcc_reg; 11378 struct mlx5_ifc_ib_port_cntrs_grp_data_layout_bits ib_port_cntrs_grp_data_layout; 11379 struct mlx5_ifc_phys_layer_cntrs_bits phys_layer_cntrs; 11380 struct mlx5_ifc_pifr_reg_bits pifr_reg; 11381 struct mlx5_ifc_pipg_reg_bits pipg_reg; 11382 struct mlx5_ifc_plbf_reg_bits plbf_reg; 11383 struct mlx5_ifc_plib_reg_bits plib_reg; 11384 struct mlx5_ifc_plpc_reg_bits plpc_reg; 11385 struct mlx5_ifc_pmaos_reg_bits pmaos_reg; 11386 struct mlx5_ifc_pmlp_reg_bits pmlp_reg; 11387 struct mlx5_ifc_pmlpn_reg_bits pmlpn_reg; 11388 struct mlx5_ifc_pmpc_reg_bits pmpc_reg; 11389 struct mlx5_ifc_pmpe_reg_bits pmpe_reg; 11390 struct mlx5_ifc_pmpr_reg_bits pmpr_reg; 11391 struct mlx5_ifc_pmtu_reg_bits pmtu_reg; 11392 struct mlx5_ifc_ppad_reg_bits ppad_reg; 11393 struct mlx5_ifc_ppcnt_reg_bits ppcnt_reg; 11394 struct mlx5_ifc_mpein_reg_bits mpein_reg; 11395 struct mlx5_ifc_mpcnt_reg_bits mpcnt_reg; 11396 struct mlx5_ifc_pplm_reg_bits pplm_reg; 11397 struct mlx5_ifc_pplr_reg_bits pplr_reg; 11398 struct mlx5_ifc_ppsc_reg_bits ppsc_reg; 11399 struct mlx5_ifc_pqdr_reg_bits pqdr_reg; 11400 struct mlx5_ifc_pspa_reg_bits pspa_reg; 11401 struct mlx5_ifc_ptas_reg_bits ptas_reg; 11402 struct mlx5_ifc_ptys_reg_bits ptys_reg; 11403 struct mlx5_ifc_mlcr_reg_bits mlcr_reg; 11404 struct mlx5_ifc_pude_reg_bits pude_reg; 11405 struct mlx5_ifc_pvlc_reg_bits pvlc_reg; 11406 struct mlx5_ifc_slrg_reg_bits slrg_reg; 11407 struct mlx5_ifc_sltp_reg_bits sltp_reg; 11408 struct mlx5_ifc_mtpps_reg_bits mtpps_reg; 11409 struct mlx5_ifc_mtppse_reg_bits mtppse_reg; 11410 struct mlx5_ifc_fpga_access_reg_bits fpga_access_reg; 11411 struct mlx5_ifc_fpga_ctrl_bits fpga_ctrl_bits; 11412 struct mlx5_ifc_fpga_cap_bits fpga_cap_bits; 11413 struct mlx5_ifc_mcqi_reg_bits mcqi_reg; 11414 struct mlx5_ifc_mcc_reg_bits mcc_reg; 11415 struct mlx5_ifc_mcda_reg_bits mcda_reg; 11416 struct mlx5_ifc_mirc_reg_bits mirc_reg; 11417 struct mlx5_ifc_mfrl_reg_bits mfrl_reg; 11418 struct mlx5_ifc_mtutc_reg_bits mtutc_reg; 11419 struct mlx5_ifc_mrtc_reg_bits mrtc_reg; 11420 struct mlx5_ifc_mtcap_reg_bits mtcap_reg; 11421 struct mlx5_ifc_mtmp_reg_bits mtmp_reg; 11422 struct mlx5_ifc_mtptm_reg_bits mtptm_reg; 11423 struct mlx5_ifc_mtctr_reg_bits mtctr_reg; 11424 u8 reserved_at_0[0x60e0]; 11425 }; 11426 11427 union mlx5_ifc_debug_enhancements_document_bits { 11428 struct mlx5_ifc_health_buffer_bits health_buffer; 11429 u8 reserved_at_0[0x200]; 11430 }; 11431 11432 union mlx5_ifc_uplink_pci_interface_document_bits { 11433 struct mlx5_ifc_initial_seg_bits initial_seg; 11434 u8 reserved_at_0[0x20060]; 11435 }; 11436 11437 struct mlx5_ifc_set_flow_table_root_out_bits { 11438 u8 status[0x8]; 11439 u8 reserved_at_8[0x18]; 11440 11441 u8 syndrome[0x20]; 11442 11443 u8 reserved_at_40[0x40]; 11444 }; 11445 11446 struct mlx5_ifc_set_flow_table_root_in_bits { 11447 u8 opcode[0x10]; 11448 u8 reserved_at_10[0x10]; 11449 11450 u8 reserved_at_20[0x10]; 11451 u8 op_mod[0x10]; 11452 11453 u8 other_vport[0x1]; 11454 u8 reserved_at_41[0xf]; 11455 u8 vport_number[0x10]; 11456 11457 u8 reserved_at_60[0x20]; 11458 11459 u8 table_type[0x8]; 11460 u8 reserved_at_88[0x7]; 11461 u8 table_of_other_vport[0x1]; 11462 u8 table_vport_number[0x10]; 11463 11464 u8 reserved_at_a0[0x8]; 11465 u8 table_id[0x18]; 11466 11467 u8 reserved_at_c0[0x8]; 11468 u8 underlay_qpn[0x18]; 11469 u8 table_eswitch_owner_vhca_id_valid[0x1]; 11470 u8 reserved_at_e1[0xf]; 11471 u8 table_eswitch_owner_vhca_id[0x10]; 11472 u8 reserved_at_100[0x100]; 11473 }; 11474 11475 enum { 11476 MLX5_MODIFY_FLOW_TABLE_MISS_TABLE_ID = (1UL << 0), 11477 MLX5_MODIFY_FLOW_TABLE_LAG_NEXT_TABLE_ID = (1UL << 15), 11478 }; 11479 11480 struct mlx5_ifc_modify_flow_table_out_bits { 11481 u8 status[0x8]; 11482 u8 reserved_at_8[0x18]; 11483 11484 u8 syndrome[0x20]; 11485 11486 u8 reserved_at_40[0x40]; 11487 }; 11488 11489 struct mlx5_ifc_modify_flow_table_in_bits { 11490 u8 opcode[0x10]; 11491 u8 reserved_at_10[0x10]; 11492 11493 u8 reserved_at_20[0x10]; 11494 u8 op_mod[0x10]; 11495 11496 u8 other_vport[0x1]; 11497 u8 reserved_at_41[0xf]; 11498 u8 vport_number[0x10]; 11499 11500 u8 reserved_at_60[0x10]; 11501 u8 modify_field_select[0x10]; 11502 11503 u8 table_type[0x8]; 11504 u8 reserved_at_88[0x18]; 11505 11506 u8 reserved_at_a0[0x8]; 11507 u8 table_id[0x18]; 11508 11509 struct mlx5_ifc_flow_table_context_bits flow_table_context; 11510 }; 11511 11512 struct mlx5_ifc_ets_tcn_config_reg_bits { 11513 u8 g[0x1]; 11514 u8 b[0x1]; 11515 u8 r[0x1]; 11516 u8 reserved_at_3[0x9]; 11517 u8 group[0x4]; 11518 u8 reserved_at_10[0x9]; 11519 u8 bw_allocation[0x7]; 11520 11521 u8 reserved_at_20[0xc]; 11522 u8 max_bw_units[0x4]; 11523 u8 reserved_at_30[0x8]; 11524 u8 max_bw_value[0x8]; 11525 }; 11526 11527 struct mlx5_ifc_ets_global_config_reg_bits { 11528 u8 reserved_at_0[0x2]; 11529 u8 r[0x1]; 11530 u8 reserved_at_3[0x1d]; 11531 11532 u8 reserved_at_20[0xc]; 11533 u8 max_bw_units[0x4]; 11534 u8 reserved_at_30[0x8]; 11535 u8 max_bw_value[0x8]; 11536 }; 11537 11538 struct mlx5_ifc_qetc_reg_bits { 11539 u8 reserved_at_0[0x8]; 11540 u8 port_number[0x8]; 11541 u8 reserved_at_10[0x30]; 11542 11543 struct mlx5_ifc_ets_tcn_config_reg_bits tc_configuration[0x8]; 11544 struct mlx5_ifc_ets_global_config_reg_bits global_configuration; 11545 }; 11546 11547 struct mlx5_ifc_qpdpm_dscp_reg_bits { 11548 u8 e[0x1]; 11549 u8 reserved_at_01[0x0b]; 11550 u8 prio[0x04]; 11551 }; 11552 11553 struct mlx5_ifc_qpdpm_reg_bits { 11554 u8 reserved_at_0[0x8]; 11555 u8 local_port[0x8]; 11556 u8 reserved_at_10[0x10]; 11557 struct mlx5_ifc_qpdpm_dscp_reg_bits dscp[64]; 11558 }; 11559 11560 struct mlx5_ifc_qpts_reg_bits { 11561 u8 reserved_at_0[0x8]; 11562 u8 local_port[0x8]; 11563 u8 reserved_at_10[0x2d]; 11564 u8 trust_state[0x3]; 11565 }; 11566 11567 struct mlx5_ifc_pptb_reg_bits { 11568 u8 reserved_at_0[0x2]; 11569 u8 mm[0x2]; 11570 u8 reserved_at_4[0x4]; 11571 u8 local_port[0x8]; 11572 u8 reserved_at_10[0x6]; 11573 u8 cm[0x1]; 11574 u8 um[0x1]; 11575 u8 pm[0x8]; 11576 11577 u8 prio_x_buff[0x20]; 11578 11579 u8 pm_msb[0x8]; 11580 u8 reserved_at_48[0x10]; 11581 u8 ctrl_buff[0x4]; 11582 u8 untagged_buff[0x4]; 11583 }; 11584 11585 struct mlx5_ifc_sbcam_reg_bits { 11586 u8 reserved_at_0[0x8]; 11587 u8 feature_group[0x8]; 11588 u8 reserved_at_10[0x8]; 11589 u8 access_reg_group[0x8]; 11590 11591 u8 reserved_at_20[0x20]; 11592 11593 u8 sb_access_reg_cap_mask[4][0x20]; 11594 11595 u8 reserved_at_c0[0x80]; 11596 11597 u8 sb_feature_cap_mask[4][0x20]; 11598 11599 u8 reserved_at_1c0[0x40]; 11600 11601 u8 cap_total_buffer_size[0x20]; 11602 11603 u8 cap_cell_size[0x10]; 11604 u8 cap_max_pg_buffers[0x8]; 11605 u8 cap_num_pool_supported[0x8]; 11606 11607 u8 reserved_at_240[0x8]; 11608 u8 cap_sbsr_stat_size[0x8]; 11609 u8 cap_max_tclass_data[0x8]; 11610 u8 cap_max_cpu_ingress_tclass_sb[0x8]; 11611 }; 11612 11613 struct mlx5_ifc_pbmc_reg_bits { 11614 u8 reserved_at_0[0x8]; 11615 u8 local_port[0x8]; 11616 u8 reserved_at_10[0x10]; 11617 11618 u8 xoff_timer_value[0x10]; 11619 u8 xoff_refresh[0x10]; 11620 11621 u8 reserved_at_40[0x9]; 11622 u8 fullness_threshold[0x7]; 11623 u8 port_buffer_size[0x10]; 11624 11625 struct mlx5_ifc_bufferx_reg_bits buffer[10]; 11626 11627 u8 reserved_at_2e0[0x80]; 11628 }; 11629 11630 struct mlx5_ifc_sbpr_reg_bits { 11631 u8 desc[0x1]; 11632 u8 snap[0x1]; 11633 u8 reserved_at_2[0x4]; 11634 u8 dir[0x2]; 11635 u8 reserved_at_8[0x14]; 11636 u8 pool[0x4]; 11637 11638 u8 infi_size[0x1]; 11639 u8 reserved_at_21[0x7]; 11640 u8 size[0x18]; 11641 11642 u8 reserved_at_40[0x1c]; 11643 u8 mode[0x4]; 11644 11645 u8 reserved_at_60[0x8]; 11646 u8 buff_occupancy[0x18]; 11647 11648 u8 clr[0x1]; 11649 u8 reserved_at_81[0x7]; 11650 u8 max_buff_occupancy[0x18]; 11651 11652 u8 reserved_at_a0[0x8]; 11653 u8 ext_buff_occupancy[0x18]; 11654 }; 11655 11656 struct mlx5_ifc_sbcm_reg_bits { 11657 u8 desc[0x1]; 11658 u8 snap[0x1]; 11659 u8 reserved_at_2[0x6]; 11660 u8 local_port[0x8]; 11661 u8 pnat[0x2]; 11662 u8 pg_buff[0x6]; 11663 u8 reserved_at_18[0x6]; 11664 u8 dir[0x2]; 11665 11666 u8 reserved_at_20[0x1f]; 11667 u8 exc[0x1]; 11668 11669 u8 reserved_at_40[0x40]; 11670 11671 u8 reserved_at_80[0x8]; 11672 u8 buff_occupancy[0x18]; 11673 11674 u8 clr[0x1]; 11675 u8 reserved_at_a1[0x7]; 11676 u8 max_buff_occupancy[0x18]; 11677 11678 u8 reserved_at_c0[0x8]; 11679 u8 min_buff[0x18]; 11680 11681 u8 infi_max[0x1]; 11682 u8 reserved_at_e1[0x7]; 11683 u8 max_buff[0x18]; 11684 11685 u8 reserved_at_100[0x20]; 11686 11687 u8 reserved_at_120[0x1c]; 11688 u8 pool[0x4]; 11689 }; 11690 11691 struct mlx5_ifc_qtct_reg_bits { 11692 u8 reserved_at_0[0x8]; 11693 u8 port_number[0x8]; 11694 u8 reserved_at_10[0xd]; 11695 u8 prio[0x3]; 11696 11697 u8 reserved_at_20[0x1d]; 11698 u8 tclass[0x3]; 11699 }; 11700 11701 struct mlx5_ifc_mcia_reg_bits { 11702 u8 l[0x1]; 11703 u8 reserved_at_1[0x7]; 11704 u8 module[0x8]; 11705 u8 reserved_at_10[0x8]; 11706 u8 status[0x8]; 11707 11708 u8 i2c_device_address[0x8]; 11709 u8 page_number[0x8]; 11710 u8 device_address[0x10]; 11711 11712 u8 reserved_at_40[0x10]; 11713 u8 size[0x10]; 11714 11715 u8 reserved_at_60[0x20]; 11716 11717 u8 dword_0[0x20]; 11718 u8 dword_1[0x20]; 11719 u8 dword_2[0x20]; 11720 u8 dword_3[0x20]; 11721 u8 dword_4[0x20]; 11722 u8 dword_5[0x20]; 11723 u8 dword_6[0x20]; 11724 u8 dword_7[0x20]; 11725 u8 dword_8[0x20]; 11726 u8 dword_9[0x20]; 11727 u8 dword_10[0x20]; 11728 u8 dword_11[0x20]; 11729 }; 11730 11731 struct mlx5_ifc_dcbx_param_bits { 11732 u8 dcbx_cee_cap[0x1]; 11733 u8 dcbx_ieee_cap[0x1]; 11734 u8 dcbx_standby_cap[0x1]; 11735 u8 reserved_at_3[0x5]; 11736 u8 port_number[0x8]; 11737 u8 reserved_at_10[0xa]; 11738 u8 max_application_table_size[6]; 11739 u8 reserved_at_20[0x15]; 11740 u8 version_oper[0x3]; 11741 u8 reserved_at_38[5]; 11742 u8 version_admin[0x3]; 11743 u8 willing_admin[0x1]; 11744 u8 reserved_at_41[0x3]; 11745 u8 pfc_cap_oper[0x4]; 11746 u8 reserved_at_48[0x4]; 11747 u8 pfc_cap_admin[0x4]; 11748 u8 reserved_at_50[0x4]; 11749 u8 num_of_tc_oper[0x4]; 11750 u8 reserved_at_58[0x4]; 11751 u8 num_of_tc_admin[0x4]; 11752 u8 remote_willing[0x1]; 11753 u8 reserved_at_61[3]; 11754 u8 remote_pfc_cap[4]; 11755 u8 reserved_at_68[0x14]; 11756 u8 remote_num_of_tc[0x4]; 11757 u8 reserved_at_80[0x18]; 11758 u8 error[0x8]; 11759 u8 reserved_at_a0[0x160]; 11760 }; 11761 11762 enum { 11763 MLX5_LAG_PORT_SELECT_MODE_QUEUE_AFFINITY = 0, 11764 MLX5_LAG_PORT_SELECT_MODE_PORT_SELECT_FT = 1, 11765 MLX5_LAG_PORT_SELECT_MODE_PORT_SELECT_MPESW = 2, 11766 }; 11767 11768 struct mlx5_ifc_lagc_bits { 11769 u8 fdb_selection_mode[0x1]; 11770 u8 reserved_at_1[0x14]; 11771 u8 port_select_mode[0x3]; 11772 u8 reserved_at_18[0x5]; 11773 u8 lag_state[0x3]; 11774 11775 u8 reserved_at_20[0xc]; 11776 u8 active_port[0x4]; 11777 u8 reserved_at_30[0x4]; 11778 u8 tx_remap_affinity_2[0x4]; 11779 u8 reserved_at_38[0x4]; 11780 u8 tx_remap_affinity_1[0x4]; 11781 }; 11782 11783 struct mlx5_ifc_create_lag_out_bits { 11784 u8 status[0x8]; 11785 u8 reserved_at_8[0x18]; 11786 11787 u8 syndrome[0x20]; 11788 11789 u8 reserved_at_40[0x40]; 11790 }; 11791 11792 struct mlx5_ifc_create_lag_in_bits { 11793 u8 opcode[0x10]; 11794 u8 reserved_at_10[0x10]; 11795 11796 u8 reserved_at_20[0x10]; 11797 u8 op_mod[0x10]; 11798 11799 struct mlx5_ifc_lagc_bits ctx; 11800 }; 11801 11802 struct mlx5_ifc_modify_lag_out_bits { 11803 u8 status[0x8]; 11804 u8 reserved_at_8[0x18]; 11805 11806 u8 syndrome[0x20]; 11807 11808 u8 reserved_at_40[0x40]; 11809 }; 11810 11811 struct mlx5_ifc_modify_lag_in_bits { 11812 u8 opcode[0x10]; 11813 u8 reserved_at_10[0x10]; 11814 11815 u8 reserved_at_20[0x10]; 11816 u8 op_mod[0x10]; 11817 11818 u8 reserved_at_40[0x20]; 11819 u8 field_select[0x20]; 11820 11821 struct mlx5_ifc_lagc_bits ctx; 11822 }; 11823 11824 struct mlx5_ifc_query_lag_out_bits { 11825 u8 status[0x8]; 11826 u8 reserved_at_8[0x18]; 11827 11828 u8 syndrome[0x20]; 11829 11830 struct mlx5_ifc_lagc_bits ctx; 11831 }; 11832 11833 struct mlx5_ifc_query_lag_in_bits { 11834 u8 opcode[0x10]; 11835 u8 reserved_at_10[0x10]; 11836 11837 u8 reserved_at_20[0x10]; 11838 u8 op_mod[0x10]; 11839 11840 u8 reserved_at_40[0x40]; 11841 }; 11842 11843 struct mlx5_ifc_destroy_lag_out_bits { 11844 u8 status[0x8]; 11845 u8 reserved_at_8[0x18]; 11846 11847 u8 syndrome[0x20]; 11848 11849 u8 reserved_at_40[0x40]; 11850 }; 11851 11852 struct mlx5_ifc_destroy_lag_in_bits { 11853 u8 opcode[0x10]; 11854 u8 reserved_at_10[0x10]; 11855 11856 u8 reserved_at_20[0x10]; 11857 u8 op_mod[0x10]; 11858 11859 u8 reserved_at_40[0x40]; 11860 }; 11861 11862 struct mlx5_ifc_create_vport_lag_out_bits { 11863 u8 status[0x8]; 11864 u8 reserved_at_8[0x18]; 11865 11866 u8 syndrome[0x20]; 11867 11868 u8 reserved_at_40[0x40]; 11869 }; 11870 11871 struct mlx5_ifc_create_vport_lag_in_bits { 11872 u8 opcode[0x10]; 11873 u8 reserved_at_10[0x10]; 11874 11875 u8 reserved_at_20[0x10]; 11876 u8 op_mod[0x10]; 11877 11878 u8 reserved_at_40[0x40]; 11879 }; 11880 11881 struct mlx5_ifc_destroy_vport_lag_out_bits { 11882 u8 status[0x8]; 11883 u8 reserved_at_8[0x18]; 11884 11885 u8 syndrome[0x20]; 11886 11887 u8 reserved_at_40[0x40]; 11888 }; 11889 11890 struct mlx5_ifc_destroy_vport_lag_in_bits { 11891 u8 opcode[0x10]; 11892 u8 reserved_at_10[0x10]; 11893 11894 u8 reserved_at_20[0x10]; 11895 u8 op_mod[0x10]; 11896 11897 u8 reserved_at_40[0x40]; 11898 }; 11899 11900 enum { 11901 MLX5_MODIFY_MEMIC_OP_MOD_ALLOC, 11902 MLX5_MODIFY_MEMIC_OP_MOD_DEALLOC, 11903 }; 11904 11905 struct mlx5_ifc_modify_memic_in_bits { 11906 u8 opcode[0x10]; 11907 u8 uid[0x10]; 11908 11909 u8 reserved_at_20[0x10]; 11910 u8 op_mod[0x10]; 11911 11912 u8 reserved_at_40[0x20]; 11913 11914 u8 reserved_at_60[0x18]; 11915 u8 memic_operation_type[0x8]; 11916 11917 u8 memic_start_addr[0x40]; 11918 11919 u8 reserved_at_c0[0x140]; 11920 }; 11921 11922 struct mlx5_ifc_modify_memic_out_bits { 11923 u8 status[0x8]; 11924 u8 reserved_at_8[0x18]; 11925 11926 u8 syndrome[0x20]; 11927 11928 u8 reserved_at_40[0x40]; 11929 11930 u8 memic_operation_addr[0x40]; 11931 11932 u8 reserved_at_c0[0x140]; 11933 }; 11934 11935 struct mlx5_ifc_alloc_memic_in_bits { 11936 u8 opcode[0x10]; 11937 u8 reserved_at_10[0x10]; 11938 11939 u8 reserved_at_20[0x10]; 11940 u8 op_mod[0x10]; 11941 11942 u8 reserved_at_30[0x20]; 11943 11944 u8 reserved_at_40[0x18]; 11945 u8 log_memic_addr_alignment[0x8]; 11946 11947 u8 range_start_addr[0x40]; 11948 11949 u8 range_size[0x20]; 11950 11951 u8 memic_size[0x20]; 11952 }; 11953 11954 struct mlx5_ifc_alloc_memic_out_bits { 11955 u8 status[0x8]; 11956 u8 reserved_at_8[0x18]; 11957 11958 u8 syndrome[0x20]; 11959 11960 u8 memic_start_addr[0x40]; 11961 }; 11962 11963 struct mlx5_ifc_dealloc_memic_in_bits { 11964 u8 opcode[0x10]; 11965 u8 reserved_at_10[0x10]; 11966 11967 u8 reserved_at_20[0x10]; 11968 u8 op_mod[0x10]; 11969 11970 u8 reserved_at_40[0x40]; 11971 11972 u8 memic_start_addr[0x40]; 11973 11974 u8 memic_size[0x20]; 11975 11976 u8 reserved_at_e0[0x20]; 11977 }; 11978 11979 struct mlx5_ifc_dealloc_memic_out_bits { 11980 u8 status[0x8]; 11981 u8 reserved_at_8[0x18]; 11982 11983 u8 syndrome[0x20]; 11984 11985 u8 reserved_at_40[0x40]; 11986 }; 11987 11988 struct mlx5_ifc_umem_bits { 11989 u8 reserved_at_0[0x80]; 11990 11991 u8 ats[0x1]; 11992 u8 reserved_at_81[0x1a]; 11993 u8 log_page_size[0x5]; 11994 11995 u8 page_offset[0x20]; 11996 11997 u8 num_of_mtt[0x40]; 11998 11999 struct mlx5_ifc_mtt_bits mtt[]; 12000 }; 12001 12002 struct mlx5_ifc_uctx_bits { 12003 u8 cap[0x20]; 12004 12005 u8 reserved_at_20[0x160]; 12006 }; 12007 12008 struct mlx5_ifc_sw_icm_bits { 12009 u8 modify_field_select[0x40]; 12010 12011 u8 reserved_at_40[0x18]; 12012 u8 log_sw_icm_size[0x8]; 12013 12014 u8 reserved_at_60[0x20]; 12015 12016 u8 sw_icm_start_addr[0x40]; 12017 12018 u8 reserved_at_c0[0x140]; 12019 }; 12020 12021 struct mlx5_ifc_geneve_tlv_option_bits { 12022 u8 modify_field_select[0x40]; 12023 12024 u8 reserved_at_40[0x18]; 12025 u8 geneve_option_fte_index[0x8]; 12026 12027 u8 option_class[0x10]; 12028 u8 option_type[0x8]; 12029 u8 reserved_at_78[0x3]; 12030 u8 option_data_length[0x5]; 12031 12032 u8 reserved_at_80[0x180]; 12033 }; 12034 12035 struct mlx5_ifc_create_umem_in_bits { 12036 u8 opcode[0x10]; 12037 u8 uid[0x10]; 12038 12039 u8 reserved_at_20[0x10]; 12040 u8 op_mod[0x10]; 12041 12042 u8 reserved_at_40[0x40]; 12043 12044 struct mlx5_ifc_umem_bits umem; 12045 }; 12046 12047 struct mlx5_ifc_create_umem_out_bits { 12048 u8 status[0x8]; 12049 u8 reserved_at_8[0x18]; 12050 12051 u8 syndrome[0x20]; 12052 12053 u8 reserved_at_40[0x8]; 12054 u8 umem_id[0x18]; 12055 12056 u8 reserved_at_60[0x20]; 12057 }; 12058 12059 struct mlx5_ifc_destroy_umem_in_bits { 12060 u8 opcode[0x10]; 12061 u8 uid[0x10]; 12062 12063 u8 reserved_at_20[0x10]; 12064 u8 op_mod[0x10]; 12065 12066 u8 reserved_at_40[0x8]; 12067 u8 umem_id[0x18]; 12068 12069 u8 reserved_at_60[0x20]; 12070 }; 12071 12072 struct mlx5_ifc_destroy_umem_out_bits { 12073 u8 status[0x8]; 12074 u8 reserved_at_8[0x18]; 12075 12076 u8 syndrome[0x20]; 12077 12078 u8 reserved_at_40[0x40]; 12079 }; 12080 12081 struct mlx5_ifc_create_uctx_in_bits { 12082 u8 opcode[0x10]; 12083 u8 reserved_at_10[0x10]; 12084 12085 u8 reserved_at_20[0x10]; 12086 u8 op_mod[0x10]; 12087 12088 u8 reserved_at_40[0x40]; 12089 12090 struct mlx5_ifc_uctx_bits uctx; 12091 }; 12092 12093 struct mlx5_ifc_create_uctx_out_bits { 12094 u8 status[0x8]; 12095 u8 reserved_at_8[0x18]; 12096 12097 u8 syndrome[0x20]; 12098 12099 u8 reserved_at_40[0x10]; 12100 u8 uid[0x10]; 12101 12102 u8 reserved_at_60[0x20]; 12103 }; 12104 12105 struct mlx5_ifc_destroy_uctx_in_bits { 12106 u8 opcode[0x10]; 12107 u8 reserved_at_10[0x10]; 12108 12109 u8 reserved_at_20[0x10]; 12110 u8 op_mod[0x10]; 12111 12112 u8 reserved_at_40[0x10]; 12113 u8 uid[0x10]; 12114 12115 u8 reserved_at_60[0x20]; 12116 }; 12117 12118 struct mlx5_ifc_destroy_uctx_out_bits { 12119 u8 status[0x8]; 12120 u8 reserved_at_8[0x18]; 12121 12122 u8 syndrome[0x20]; 12123 12124 u8 reserved_at_40[0x40]; 12125 }; 12126 12127 struct mlx5_ifc_create_sw_icm_in_bits { 12128 struct mlx5_ifc_general_obj_in_cmd_hdr_bits hdr; 12129 struct mlx5_ifc_sw_icm_bits sw_icm; 12130 }; 12131 12132 struct mlx5_ifc_create_geneve_tlv_option_in_bits { 12133 struct mlx5_ifc_general_obj_in_cmd_hdr_bits hdr; 12134 struct mlx5_ifc_geneve_tlv_option_bits geneve_tlv_opt; 12135 }; 12136 12137 struct mlx5_ifc_mtrc_string_db_param_bits { 12138 u8 string_db_base_address[0x20]; 12139 12140 u8 reserved_at_20[0x8]; 12141 u8 string_db_size[0x18]; 12142 }; 12143 12144 struct mlx5_ifc_mtrc_cap_bits { 12145 u8 trace_owner[0x1]; 12146 u8 trace_to_memory[0x1]; 12147 u8 reserved_at_2[0x4]; 12148 u8 trc_ver[0x2]; 12149 u8 reserved_at_8[0x14]; 12150 u8 num_string_db[0x4]; 12151 12152 u8 first_string_trace[0x8]; 12153 u8 num_string_trace[0x8]; 12154 u8 reserved_at_30[0x28]; 12155 12156 u8 log_max_trace_buffer_size[0x8]; 12157 12158 u8 reserved_at_60[0x20]; 12159 12160 struct mlx5_ifc_mtrc_string_db_param_bits string_db_param[8]; 12161 12162 u8 reserved_at_280[0x180]; 12163 }; 12164 12165 struct mlx5_ifc_mtrc_conf_bits { 12166 u8 reserved_at_0[0x1c]; 12167 u8 trace_mode[0x4]; 12168 u8 reserved_at_20[0x18]; 12169 u8 log_trace_buffer_size[0x8]; 12170 u8 trace_mkey[0x20]; 12171 u8 reserved_at_60[0x3a0]; 12172 }; 12173 12174 struct mlx5_ifc_mtrc_stdb_bits { 12175 u8 string_db_index[0x4]; 12176 u8 reserved_at_4[0x4]; 12177 u8 read_size[0x18]; 12178 u8 start_offset[0x20]; 12179 u8 string_db_data[]; 12180 }; 12181 12182 struct mlx5_ifc_mtrc_ctrl_bits { 12183 u8 trace_status[0x2]; 12184 u8 reserved_at_2[0x2]; 12185 u8 arm_event[0x1]; 12186 u8 reserved_at_5[0xb]; 12187 u8 modify_field_select[0x10]; 12188 u8 reserved_at_20[0x2b]; 12189 u8 current_timestamp52_32[0x15]; 12190 u8 current_timestamp31_0[0x20]; 12191 u8 reserved_at_80[0x180]; 12192 }; 12193 12194 struct mlx5_ifc_host_params_context_bits { 12195 u8 host_number[0x8]; 12196 u8 reserved_at_8[0x7]; 12197 u8 host_pf_disabled[0x1]; 12198 u8 host_num_of_vfs[0x10]; 12199 12200 u8 host_total_vfs[0x10]; 12201 u8 host_pci_bus[0x10]; 12202 12203 u8 reserved_at_40[0x10]; 12204 u8 host_pci_device[0x10]; 12205 12206 u8 reserved_at_60[0x10]; 12207 u8 host_pci_function[0x10]; 12208 12209 u8 reserved_at_80[0x180]; 12210 }; 12211 12212 struct mlx5_ifc_query_esw_functions_in_bits { 12213 u8 opcode[0x10]; 12214 u8 reserved_at_10[0x10]; 12215 12216 u8 reserved_at_20[0x10]; 12217 u8 op_mod[0x10]; 12218 12219 u8 reserved_at_40[0x40]; 12220 }; 12221 12222 struct mlx5_ifc_query_esw_functions_out_bits { 12223 u8 status[0x8]; 12224 u8 reserved_at_8[0x18]; 12225 12226 u8 syndrome[0x20]; 12227 12228 u8 reserved_at_40[0x40]; 12229 12230 struct mlx5_ifc_host_params_context_bits host_params_context; 12231 12232 u8 reserved_at_280[0x180]; 12233 u8 host_sf_enable[][0x40]; 12234 }; 12235 12236 struct mlx5_ifc_sf_partition_bits { 12237 u8 reserved_at_0[0x10]; 12238 u8 log_num_sf[0x8]; 12239 u8 log_sf_bar_size[0x8]; 12240 }; 12241 12242 struct mlx5_ifc_query_sf_partitions_out_bits { 12243 u8 status[0x8]; 12244 u8 reserved_at_8[0x18]; 12245 12246 u8 syndrome[0x20]; 12247 12248 u8 reserved_at_40[0x18]; 12249 u8 num_sf_partitions[0x8]; 12250 12251 u8 reserved_at_60[0x20]; 12252 12253 struct mlx5_ifc_sf_partition_bits sf_partition[]; 12254 }; 12255 12256 struct mlx5_ifc_query_sf_partitions_in_bits { 12257 u8 opcode[0x10]; 12258 u8 reserved_at_10[0x10]; 12259 12260 u8 reserved_at_20[0x10]; 12261 u8 op_mod[0x10]; 12262 12263 u8 reserved_at_40[0x40]; 12264 }; 12265 12266 struct mlx5_ifc_dealloc_sf_out_bits { 12267 u8 status[0x8]; 12268 u8 reserved_at_8[0x18]; 12269 12270 u8 syndrome[0x20]; 12271 12272 u8 reserved_at_40[0x40]; 12273 }; 12274 12275 struct mlx5_ifc_dealloc_sf_in_bits { 12276 u8 opcode[0x10]; 12277 u8 reserved_at_10[0x10]; 12278 12279 u8 reserved_at_20[0x10]; 12280 u8 op_mod[0x10]; 12281 12282 u8 reserved_at_40[0x10]; 12283 u8 function_id[0x10]; 12284 12285 u8 reserved_at_60[0x20]; 12286 }; 12287 12288 struct mlx5_ifc_alloc_sf_out_bits { 12289 u8 status[0x8]; 12290 u8 reserved_at_8[0x18]; 12291 12292 u8 syndrome[0x20]; 12293 12294 u8 reserved_at_40[0x40]; 12295 }; 12296 12297 struct mlx5_ifc_alloc_sf_in_bits { 12298 u8 opcode[0x10]; 12299 u8 reserved_at_10[0x10]; 12300 12301 u8 reserved_at_20[0x10]; 12302 u8 op_mod[0x10]; 12303 12304 u8 reserved_at_40[0x10]; 12305 u8 function_id[0x10]; 12306 12307 u8 reserved_at_60[0x20]; 12308 }; 12309 12310 struct mlx5_ifc_affiliated_event_header_bits { 12311 u8 reserved_at_0[0x10]; 12312 u8 obj_type[0x10]; 12313 12314 u8 obj_id[0x20]; 12315 }; 12316 12317 enum { 12318 MLX5_HCA_CAP_GENERAL_OBJECT_TYPES_ENCRYPTION_KEY = BIT_ULL(0xc), 12319 MLX5_HCA_CAP_GENERAL_OBJECT_TYPES_IPSEC = BIT_ULL(0x13), 12320 MLX5_HCA_CAP_GENERAL_OBJECT_TYPES_SAMPLER = BIT_ULL(0x20), 12321 MLX5_HCA_CAP_GENERAL_OBJECT_TYPES_FLOW_METER_ASO = BIT_ULL(0x24), 12322 }; 12323 12324 enum { 12325 MLX5_GENERAL_OBJECT_TYPES_ENCRYPTION_KEY = 0xc, 12326 MLX5_GENERAL_OBJECT_TYPES_IPSEC = 0x13, 12327 MLX5_GENERAL_OBJECT_TYPES_SAMPLER = 0x20, 12328 MLX5_GENERAL_OBJECT_TYPES_FLOW_METER_ASO = 0x24, 12329 MLX5_GENERAL_OBJECT_TYPES_MACSEC = 0x27, 12330 MLX5_GENERAL_OBJECT_TYPES_INT_KEK = 0x47, 12331 MLX5_GENERAL_OBJECT_TYPES_FLOW_TABLE_ALIAS = 0xff15, 12332 }; 12333 12334 enum { 12335 MLX5_IPSEC_OBJECT_ICV_LEN_16B, 12336 }; 12337 12338 enum { 12339 MLX5_IPSEC_ASO_REG_C_0_1 = 0x0, 12340 MLX5_IPSEC_ASO_REG_C_2_3 = 0x1, 12341 MLX5_IPSEC_ASO_REG_C_4_5 = 0x2, 12342 MLX5_IPSEC_ASO_REG_C_6_7 = 0x3, 12343 }; 12344 12345 enum { 12346 MLX5_IPSEC_ASO_MODE = 0x0, 12347 MLX5_IPSEC_ASO_REPLAY_PROTECTION = 0x1, 12348 MLX5_IPSEC_ASO_INC_SN = 0x2, 12349 }; 12350 12351 enum { 12352 MLX5_IPSEC_ASO_REPLAY_WIN_32BIT = 0x0, 12353 MLX5_IPSEC_ASO_REPLAY_WIN_64BIT = 0x1, 12354 MLX5_IPSEC_ASO_REPLAY_WIN_128BIT = 0x2, 12355 MLX5_IPSEC_ASO_REPLAY_WIN_256BIT = 0x3, 12356 }; 12357 12358 struct mlx5_ifc_ipsec_aso_bits { 12359 u8 valid[0x1]; 12360 u8 reserved_at_201[0x1]; 12361 u8 mode[0x2]; 12362 u8 window_sz[0x2]; 12363 u8 soft_lft_arm[0x1]; 12364 u8 hard_lft_arm[0x1]; 12365 u8 remove_flow_enable[0x1]; 12366 u8 esn_event_arm[0x1]; 12367 u8 reserved_at_20a[0x16]; 12368 12369 u8 remove_flow_pkt_cnt[0x20]; 12370 12371 u8 remove_flow_soft_lft[0x20]; 12372 12373 u8 reserved_at_260[0x80]; 12374 12375 u8 mode_parameter[0x20]; 12376 12377 u8 replay_protection_window[0x100]; 12378 }; 12379 12380 struct mlx5_ifc_ipsec_obj_bits { 12381 u8 modify_field_select[0x40]; 12382 u8 full_offload[0x1]; 12383 u8 reserved_at_41[0x1]; 12384 u8 esn_en[0x1]; 12385 u8 esn_overlap[0x1]; 12386 u8 reserved_at_44[0x2]; 12387 u8 icv_length[0x2]; 12388 u8 reserved_at_48[0x4]; 12389 u8 aso_return_reg[0x4]; 12390 u8 reserved_at_50[0x10]; 12391 12392 u8 esn_msb[0x20]; 12393 12394 u8 reserved_at_80[0x8]; 12395 u8 dekn[0x18]; 12396 12397 u8 salt[0x20]; 12398 12399 u8 implicit_iv[0x40]; 12400 12401 u8 reserved_at_100[0x8]; 12402 u8 ipsec_aso_access_pd[0x18]; 12403 u8 reserved_at_120[0xe0]; 12404 12405 struct mlx5_ifc_ipsec_aso_bits ipsec_aso; 12406 }; 12407 12408 struct mlx5_ifc_create_ipsec_obj_in_bits { 12409 struct mlx5_ifc_general_obj_in_cmd_hdr_bits general_obj_in_cmd_hdr; 12410 struct mlx5_ifc_ipsec_obj_bits ipsec_object; 12411 }; 12412 12413 enum { 12414 MLX5_MODIFY_IPSEC_BITMASK_ESN_OVERLAP = BIT(0), 12415 MLX5_MODIFY_IPSEC_BITMASK_ESN_MSB = BIT(1), 12416 }; 12417 12418 struct mlx5_ifc_query_ipsec_obj_out_bits { 12419 struct mlx5_ifc_general_obj_out_cmd_hdr_bits general_obj_out_cmd_hdr; 12420 struct mlx5_ifc_ipsec_obj_bits ipsec_object; 12421 }; 12422 12423 struct mlx5_ifc_modify_ipsec_obj_in_bits { 12424 struct mlx5_ifc_general_obj_in_cmd_hdr_bits general_obj_in_cmd_hdr; 12425 struct mlx5_ifc_ipsec_obj_bits ipsec_object; 12426 }; 12427 12428 enum { 12429 MLX5_MACSEC_ASO_REPLAY_PROTECTION = 0x1, 12430 }; 12431 12432 enum { 12433 MLX5_MACSEC_ASO_REPLAY_WIN_32BIT = 0x0, 12434 MLX5_MACSEC_ASO_REPLAY_WIN_64BIT = 0x1, 12435 MLX5_MACSEC_ASO_REPLAY_WIN_128BIT = 0x2, 12436 MLX5_MACSEC_ASO_REPLAY_WIN_256BIT = 0x3, 12437 }; 12438 12439 #define MLX5_MACSEC_ASO_INC_SN 0x2 12440 #define MLX5_MACSEC_ASO_REG_C_4_5 0x2 12441 12442 struct mlx5_ifc_macsec_aso_bits { 12443 u8 valid[0x1]; 12444 u8 reserved_at_1[0x1]; 12445 u8 mode[0x2]; 12446 u8 window_size[0x2]; 12447 u8 soft_lifetime_arm[0x1]; 12448 u8 hard_lifetime_arm[0x1]; 12449 u8 remove_flow_enable[0x1]; 12450 u8 epn_event_arm[0x1]; 12451 u8 reserved_at_a[0x16]; 12452 12453 u8 remove_flow_packet_count[0x20]; 12454 12455 u8 remove_flow_soft_lifetime[0x20]; 12456 12457 u8 reserved_at_60[0x80]; 12458 12459 u8 mode_parameter[0x20]; 12460 12461 u8 replay_protection_window[8][0x20]; 12462 }; 12463 12464 struct mlx5_ifc_macsec_offload_obj_bits { 12465 u8 modify_field_select[0x40]; 12466 12467 u8 confidentiality_en[0x1]; 12468 u8 reserved_at_41[0x1]; 12469 u8 epn_en[0x1]; 12470 u8 epn_overlap[0x1]; 12471 u8 reserved_at_44[0x2]; 12472 u8 confidentiality_offset[0x2]; 12473 u8 reserved_at_48[0x4]; 12474 u8 aso_return_reg[0x4]; 12475 u8 reserved_at_50[0x10]; 12476 12477 u8 epn_msb[0x20]; 12478 12479 u8 reserved_at_80[0x8]; 12480 u8 dekn[0x18]; 12481 12482 u8 reserved_at_a0[0x20]; 12483 12484 u8 sci[0x40]; 12485 12486 u8 reserved_at_100[0x8]; 12487 u8 macsec_aso_access_pd[0x18]; 12488 12489 u8 reserved_at_120[0x60]; 12490 12491 u8 salt[3][0x20]; 12492 12493 u8 reserved_at_1e0[0x20]; 12494 12495 struct mlx5_ifc_macsec_aso_bits macsec_aso; 12496 }; 12497 12498 struct mlx5_ifc_create_macsec_obj_in_bits { 12499 struct mlx5_ifc_general_obj_in_cmd_hdr_bits general_obj_in_cmd_hdr; 12500 struct mlx5_ifc_macsec_offload_obj_bits macsec_object; 12501 }; 12502 12503 struct mlx5_ifc_modify_macsec_obj_in_bits { 12504 struct mlx5_ifc_general_obj_in_cmd_hdr_bits general_obj_in_cmd_hdr; 12505 struct mlx5_ifc_macsec_offload_obj_bits macsec_object; 12506 }; 12507 12508 enum { 12509 MLX5_MODIFY_MACSEC_BITMASK_EPN_OVERLAP = BIT(0), 12510 MLX5_MODIFY_MACSEC_BITMASK_EPN_MSB = BIT(1), 12511 }; 12512 12513 struct mlx5_ifc_query_macsec_obj_out_bits { 12514 struct mlx5_ifc_general_obj_out_cmd_hdr_bits general_obj_out_cmd_hdr; 12515 struct mlx5_ifc_macsec_offload_obj_bits macsec_object; 12516 }; 12517 12518 struct mlx5_ifc_wrapped_dek_bits { 12519 u8 gcm_iv[0x60]; 12520 12521 u8 reserved_at_60[0x20]; 12522 12523 u8 const0[0x1]; 12524 u8 key_size[0x1]; 12525 u8 reserved_at_82[0x2]; 12526 u8 key2_invalid[0x1]; 12527 u8 reserved_at_85[0x3]; 12528 u8 pd[0x18]; 12529 12530 u8 key_purpose[0x5]; 12531 u8 reserved_at_a5[0x13]; 12532 u8 kek_id[0x8]; 12533 12534 u8 reserved_at_c0[0x40]; 12535 12536 u8 key1[0x8][0x20]; 12537 12538 u8 key2[0x8][0x20]; 12539 12540 u8 reserved_at_300[0x40]; 12541 12542 u8 const1[0x1]; 12543 u8 reserved_at_341[0x1f]; 12544 12545 u8 reserved_at_360[0x20]; 12546 12547 u8 auth_tag[0x80]; 12548 }; 12549 12550 struct mlx5_ifc_encryption_key_obj_bits { 12551 u8 modify_field_select[0x40]; 12552 12553 u8 state[0x8]; 12554 u8 sw_wrapped[0x1]; 12555 u8 reserved_at_49[0xb]; 12556 u8 key_size[0x4]; 12557 u8 reserved_at_58[0x4]; 12558 u8 key_purpose[0x4]; 12559 12560 u8 reserved_at_60[0x8]; 12561 u8 pd[0x18]; 12562 12563 u8 reserved_at_80[0x100]; 12564 12565 u8 opaque[0x40]; 12566 12567 u8 reserved_at_1c0[0x40]; 12568 12569 u8 key[8][0x80]; 12570 12571 u8 sw_wrapped_dek[8][0x80]; 12572 12573 u8 reserved_at_a00[0x600]; 12574 }; 12575 12576 struct mlx5_ifc_create_encryption_key_in_bits { 12577 struct mlx5_ifc_general_obj_in_cmd_hdr_bits general_obj_in_cmd_hdr; 12578 struct mlx5_ifc_encryption_key_obj_bits encryption_key_object; 12579 }; 12580 12581 struct mlx5_ifc_modify_encryption_key_in_bits { 12582 struct mlx5_ifc_general_obj_in_cmd_hdr_bits general_obj_in_cmd_hdr; 12583 struct mlx5_ifc_encryption_key_obj_bits encryption_key_object; 12584 }; 12585 12586 enum { 12587 MLX5_FLOW_METER_MODE_BYTES_IP_LENGTH = 0x0, 12588 MLX5_FLOW_METER_MODE_BYTES_CALC_WITH_L2 = 0x1, 12589 MLX5_FLOW_METER_MODE_BYTES_CALC_WITH_L2_IPG = 0x2, 12590 MLX5_FLOW_METER_MODE_NUM_PACKETS = 0x3, 12591 }; 12592 12593 struct mlx5_ifc_flow_meter_parameters_bits { 12594 u8 valid[0x1]; 12595 u8 bucket_overflow[0x1]; 12596 u8 start_color[0x2]; 12597 u8 both_buckets_on_green[0x1]; 12598 u8 reserved_at_5[0x1]; 12599 u8 meter_mode[0x2]; 12600 u8 reserved_at_8[0x18]; 12601 12602 u8 reserved_at_20[0x20]; 12603 12604 u8 reserved_at_40[0x3]; 12605 u8 cbs_exponent[0x5]; 12606 u8 cbs_mantissa[0x8]; 12607 u8 reserved_at_50[0x3]; 12608 u8 cir_exponent[0x5]; 12609 u8 cir_mantissa[0x8]; 12610 12611 u8 reserved_at_60[0x20]; 12612 12613 u8 reserved_at_80[0x3]; 12614 u8 ebs_exponent[0x5]; 12615 u8 ebs_mantissa[0x8]; 12616 u8 reserved_at_90[0x3]; 12617 u8 eir_exponent[0x5]; 12618 u8 eir_mantissa[0x8]; 12619 12620 u8 reserved_at_a0[0x60]; 12621 }; 12622 12623 struct mlx5_ifc_flow_meter_aso_obj_bits { 12624 u8 modify_field_select[0x40]; 12625 12626 u8 reserved_at_40[0x40]; 12627 12628 u8 reserved_at_80[0x8]; 12629 u8 meter_aso_access_pd[0x18]; 12630 12631 u8 reserved_at_a0[0x160]; 12632 12633 struct mlx5_ifc_flow_meter_parameters_bits flow_meter_parameters[2]; 12634 }; 12635 12636 struct mlx5_ifc_create_flow_meter_aso_obj_in_bits { 12637 struct mlx5_ifc_general_obj_in_cmd_hdr_bits hdr; 12638 struct mlx5_ifc_flow_meter_aso_obj_bits flow_meter_aso_obj; 12639 }; 12640 12641 struct mlx5_ifc_int_kek_obj_bits { 12642 u8 modify_field_select[0x40]; 12643 12644 u8 state[0x8]; 12645 u8 auto_gen[0x1]; 12646 u8 reserved_at_49[0xb]; 12647 u8 key_size[0x4]; 12648 u8 reserved_at_58[0x8]; 12649 12650 u8 reserved_at_60[0x8]; 12651 u8 pd[0x18]; 12652 12653 u8 reserved_at_80[0x180]; 12654 u8 key[8][0x80]; 12655 12656 u8 reserved_at_600[0x200]; 12657 }; 12658 12659 struct mlx5_ifc_create_int_kek_obj_in_bits { 12660 struct mlx5_ifc_general_obj_in_cmd_hdr_bits general_obj_in_cmd_hdr; 12661 struct mlx5_ifc_int_kek_obj_bits int_kek_object; 12662 }; 12663 12664 struct mlx5_ifc_create_int_kek_obj_out_bits { 12665 struct mlx5_ifc_general_obj_out_cmd_hdr_bits general_obj_out_cmd_hdr; 12666 struct mlx5_ifc_int_kek_obj_bits int_kek_object; 12667 }; 12668 12669 struct mlx5_ifc_sampler_obj_bits { 12670 u8 modify_field_select[0x40]; 12671 12672 u8 table_type[0x8]; 12673 u8 level[0x8]; 12674 u8 reserved_at_50[0xf]; 12675 u8 ignore_flow_level[0x1]; 12676 12677 u8 sample_ratio[0x20]; 12678 12679 u8 reserved_at_80[0x8]; 12680 u8 sample_table_id[0x18]; 12681 12682 u8 reserved_at_a0[0x8]; 12683 u8 default_table_id[0x18]; 12684 12685 u8 sw_steering_icm_address_rx[0x40]; 12686 u8 sw_steering_icm_address_tx[0x40]; 12687 12688 u8 reserved_at_140[0xa0]; 12689 }; 12690 12691 struct mlx5_ifc_create_sampler_obj_in_bits { 12692 struct mlx5_ifc_general_obj_in_cmd_hdr_bits general_obj_in_cmd_hdr; 12693 struct mlx5_ifc_sampler_obj_bits sampler_object; 12694 }; 12695 12696 struct mlx5_ifc_query_sampler_obj_out_bits { 12697 struct mlx5_ifc_general_obj_out_cmd_hdr_bits general_obj_out_cmd_hdr; 12698 struct mlx5_ifc_sampler_obj_bits sampler_object; 12699 }; 12700 12701 enum { 12702 MLX5_GENERAL_OBJECT_TYPE_ENCRYPTION_KEY_KEY_SIZE_128 = 0x0, 12703 MLX5_GENERAL_OBJECT_TYPE_ENCRYPTION_KEY_KEY_SIZE_256 = 0x1, 12704 }; 12705 12706 enum { 12707 MLX5_GENERAL_OBJECT_TYPE_ENCRYPTION_KEY_PURPOSE_TLS = 0x1, 12708 MLX5_GENERAL_OBJECT_TYPE_ENCRYPTION_KEY_PURPOSE_IPSEC = 0x2, 12709 MLX5_GENERAL_OBJECT_TYPE_ENCRYPTION_KEY_PURPOSE_MACSEC = 0x4, 12710 }; 12711 12712 struct mlx5_ifc_tls_static_params_bits { 12713 u8 const_2[0x2]; 12714 u8 tls_version[0x4]; 12715 u8 const_1[0x2]; 12716 u8 reserved_at_8[0x14]; 12717 u8 encryption_standard[0x4]; 12718 12719 u8 reserved_at_20[0x20]; 12720 12721 u8 initial_record_number[0x40]; 12722 12723 u8 resync_tcp_sn[0x20]; 12724 12725 u8 gcm_iv[0x20]; 12726 12727 u8 implicit_iv[0x40]; 12728 12729 u8 reserved_at_100[0x8]; 12730 u8 dek_index[0x18]; 12731 12732 u8 reserved_at_120[0xe0]; 12733 }; 12734 12735 struct mlx5_ifc_tls_progress_params_bits { 12736 u8 next_record_tcp_sn[0x20]; 12737 12738 u8 hw_resync_tcp_sn[0x20]; 12739 12740 u8 record_tracker_state[0x2]; 12741 u8 auth_state[0x2]; 12742 u8 reserved_at_44[0x4]; 12743 u8 hw_offset_record_number[0x18]; 12744 }; 12745 12746 enum { 12747 MLX5_MTT_PERM_READ = 1 << 0, 12748 MLX5_MTT_PERM_WRITE = 1 << 1, 12749 MLX5_MTT_PERM_RW = MLX5_MTT_PERM_READ | MLX5_MTT_PERM_WRITE, 12750 }; 12751 12752 enum { 12753 MLX5_SUSPEND_VHCA_IN_OP_MOD_SUSPEND_INITIATOR = 0x0, 12754 MLX5_SUSPEND_VHCA_IN_OP_MOD_SUSPEND_RESPONDER = 0x1, 12755 }; 12756 12757 struct mlx5_ifc_suspend_vhca_in_bits { 12758 u8 opcode[0x10]; 12759 u8 uid[0x10]; 12760 12761 u8 reserved_at_20[0x10]; 12762 u8 op_mod[0x10]; 12763 12764 u8 reserved_at_40[0x10]; 12765 u8 vhca_id[0x10]; 12766 12767 u8 reserved_at_60[0x20]; 12768 }; 12769 12770 struct mlx5_ifc_suspend_vhca_out_bits { 12771 u8 status[0x8]; 12772 u8 reserved_at_8[0x18]; 12773 12774 u8 syndrome[0x20]; 12775 12776 u8 reserved_at_40[0x40]; 12777 }; 12778 12779 enum { 12780 MLX5_RESUME_VHCA_IN_OP_MOD_RESUME_RESPONDER = 0x0, 12781 MLX5_RESUME_VHCA_IN_OP_MOD_RESUME_INITIATOR = 0x1, 12782 }; 12783 12784 struct mlx5_ifc_resume_vhca_in_bits { 12785 u8 opcode[0x10]; 12786 u8 uid[0x10]; 12787 12788 u8 reserved_at_20[0x10]; 12789 u8 op_mod[0x10]; 12790 12791 u8 reserved_at_40[0x10]; 12792 u8 vhca_id[0x10]; 12793 12794 u8 reserved_at_60[0x20]; 12795 }; 12796 12797 struct mlx5_ifc_resume_vhca_out_bits { 12798 u8 status[0x8]; 12799 u8 reserved_at_8[0x18]; 12800 12801 u8 syndrome[0x20]; 12802 12803 u8 reserved_at_40[0x40]; 12804 }; 12805 12806 struct mlx5_ifc_query_vhca_migration_state_in_bits { 12807 u8 opcode[0x10]; 12808 u8 uid[0x10]; 12809 12810 u8 reserved_at_20[0x10]; 12811 u8 op_mod[0x10]; 12812 12813 u8 incremental[0x1]; 12814 u8 chunk[0x1]; 12815 u8 reserved_at_42[0xe]; 12816 u8 vhca_id[0x10]; 12817 12818 u8 reserved_at_60[0x20]; 12819 }; 12820 12821 struct mlx5_ifc_query_vhca_migration_state_out_bits { 12822 u8 status[0x8]; 12823 u8 reserved_at_8[0x18]; 12824 12825 u8 syndrome[0x20]; 12826 12827 u8 reserved_at_40[0x40]; 12828 12829 u8 required_umem_size[0x20]; 12830 12831 u8 reserved_at_a0[0x20]; 12832 12833 u8 remaining_total_size[0x40]; 12834 12835 u8 reserved_at_100[0x100]; 12836 }; 12837 12838 struct mlx5_ifc_save_vhca_state_in_bits { 12839 u8 opcode[0x10]; 12840 u8 uid[0x10]; 12841 12842 u8 reserved_at_20[0x10]; 12843 u8 op_mod[0x10]; 12844 12845 u8 incremental[0x1]; 12846 u8 set_track[0x1]; 12847 u8 reserved_at_42[0xe]; 12848 u8 vhca_id[0x10]; 12849 12850 u8 reserved_at_60[0x20]; 12851 12852 u8 va[0x40]; 12853 12854 u8 mkey[0x20]; 12855 12856 u8 size[0x20]; 12857 }; 12858 12859 struct mlx5_ifc_save_vhca_state_out_bits { 12860 u8 status[0x8]; 12861 u8 reserved_at_8[0x18]; 12862 12863 u8 syndrome[0x20]; 12864 12865 u8 actual_image_size[0x20]; 12866 12867 u8 next_required_umem_size[0x20]; 12868 }; 12869 12870 struct mlx5_ifc_load_vhca_state_in_bits { 12871 u8 opcode[0x10]; 12872 u8 uid[0x10]; 12873 12874 u8 reserved_at_20[0x10]; 12875 u8 op_mod[0x10]; 12876 12877 u8 reserved_at_40[0x10]; 12878 u8 vhca_id[0x10]; 12879 12880 u8 reserved_at_60[0x20]; 12881 12882 u8 va[0x40]; 12883 12884 u8 mkey[0x20]; 12885 12886 u8 size[0x20]; 12887 }; 12888 12889 struct mlx5_ifc_load_vhca_state_out_bits { 12890 u8 status[0x8]; 12891 u8 reserved_at_8[0x18]; 12892 12893 u8 syndrome[0x20]; 12894 12895 u8 reserved_at_40[0x40]; 12896 }; 12897 12898 struct mlx5_ifc_adv_virtualization_cap_bits { 12899 u8 reserved_at_0[0x3]; 12900 u8 pg_track_log_max_num[0x5]; 12901 u8 pg_track_max_num_range[0x8]; 12902 u8 pg_track_log_min_addr_space[0x8]; 12903 u8 pg_track_log_max_addr_space[0x8]; 12904 12905 u8 reserved_at_20[0x3]; 12906 u8 pg_track_log_min_msg_size[0x5]; 12907 u8 reserved_at_28[0x3]; 12908 u8 pg_track_log_max_msg_size[0x5]; 12909 u8 reserved_at_30[0x3]; 12910 u8 pg_track_log_min_page_size[0x5]; 12911 u8 reserved_at_38[0x3]; 12912 u8 pg_track_log_max_page_size[0x5]; 12913 12914 u8 reserved_at_40[0x7c0]; 12915 }; 12916 12917 struct mlx5_ifc_page_track_report_entry_bits { 12918 u8 dirty_address_high[0x20]; 12919 12920 u8 dirty_address_low[0x20]; 12921 }; 12922 12923 enum { 12924 MLX5_PAGE_TRACK_STATE_TRACKING, 12925 MLX5_PAGE_TRACK_STATE_REPORTING, 12926 MLX5_PAGE_TRACK_STATE_ERROR, 12927 }; 12928 12929 struct mlx5_ifc_page_track_range_bits { 12930 u8 start_address[0x40]; 12931 12932 u8 length[0x40]; 12933 }; 12934 12935 struct mlx5_ifc_page_track_bits { 12936 u8 modify_field_select[0x40]; 12937 12938 u8 reserved_at_40[0x10]; 12939 u8 vhca_id[0x10]; 12940 12941 u8 reserved_at_60[0x20]; 12942 12943 u8 state[0x4]; 12944 u8 track_type[0x4]; 12945 u8 log_addr_space_size[0x8]; 12946 u8 reserved_at_90[0x3]; 12947 u8 log_page_size[0x5]; 12948 u8 reserved_at_98[0x3]; 12949 u8 log_msg_size[0x5]; 12950 12951 u8 reserved_at_a0[0x8]; 12952 u8 reporting_qpn[0x18]; 12953 12954 u8 reserved_at_c0[0x18]; 12955 u8 num_ranges[0x8]; 12956 12957 u8 reserved_at_e0[0x20]; 12958 12959 u8 range_start_address[0x40]; 12960 12961 u8 length[0x40]; 12962 12963 struct mlx5_ifc_page_track_range_bits track_range[0]; 12964 }; 12965 12966 struct mlx5_ifc_create_page_track_obj_in_bits { 12967 struct mlx5_ifc_general_obj_in_cmd_hdr_bits general_obj_in_cmd_hdr; 12968 struct mlx5_ifc_page_track_bits obj_context; 12969 }; 12970 12971 struct mlx5_ifc_modify_page_track_obj_in_bits { 12972 struct mlx5_ifc_general_obj_in_cmd_hdr_bits general_obj_in_cmd_hdr; 12973 struct mlx5_ifc_page_track_bits obj_context; 12974 }; 12975 12976 struct mlx5_ifc_query_page_track_obj_out_bits { 12977 struct mlx5_ifc_general_obj_out_cmd_hdr_bits general_obj_out_cmd_hdr; 12978 struct mlx5_ifc_page_track_bits obj_context; 12979 }; 12980 12981 struct mlx5_ifc_msecq_reg_bits { 12982 u8 reserved_at_0[0x20]; 12983 12984 u8 reserved_at_20[0x12]; 12985 u8 network_option[0x2]; 12986 u8 local_ssm_code[0x4]; 12987 u8 local_enhanced_ssm_code[0x8]; 12988 12989 u8 local_clock_identity[0x40]; 12990 12991 u8 reserved_at_80[0x180]; 12992 }; 12993 12994 enum { 12995 MLX5_MSEES_FIELD_SELECT_ENABLE = BIT(0), 12996 MLX5_MSEES_FIELD_SELECT_ADMIN_STATUS = BIT(1), 12997 MLX5_MSEES_FIELD_SELECT_ADMIN_FREQ_MEASURE = BIT(2), 12998 }; 12999 13000 enum mlx5_msees_admin_status { 13001 MLX5_MSEES_ADMIN_STATUS_FREE_RUNNING = 0x0, 13002 MLX5_MSEES_ADMIN_STATUS_TRACK = 0x1, 13003 }; 13004 13005 enum mlx5_msees_oper_status { 13006 MLX5_MSEES_OPER_STATUS_FREE_RUNNING = 0x0, 13007 MLX5_MSEES_OPER_STATUS_SELF_TRACK = 0x1, 13008 MLX5_MSEES_OPER_STATUS_OTHER_TRACK = 0x2, 13009 MLX5_MSEES_OPER_STATUS_HOLDOVER = 0x3, 13010 MLX5_MSEES_OPER_STATUS_FAIL_HOLDOVER = 0x4, 13011 MLX5_MSEES_OPER_STATUS_FAIL_FREE_RUNNING = 0x5, 13012 }; 13013 13014 enum mlx5_msees_failure_reason { 13015 MLX5_MSEES_FAILURE_REASON_UNDEFINED_ERROR = 0x0, 13016 MLX5_MSEES_FAILURE_REASON_PORT_DOWN = 0x1, 13017 MLX5_MSEES_FAILURE_REASON_TOO_HIGH_FREQUENCY_DIFF = 0x2, 13018 MLX5_MSEES_FAILURE_REASON_NET_SYNCHRONIZER_DEVICE_ERROR = 0x3, 13019 MLX5_MSEES_FAILURE_REASON_LACK_OF_RESOURCES = 0x4, 13020 }; 13021 13022 struct mlx5_ifc_msees_reg_bits { 13023 u8 reserved_at_0[0x8]; 13024 u8 local_port[0x8]; 13025 u8 pnat[0x2]; 13026 u8 lp_msb[0x2]; 13027 u8 reserved_at_14[0xc]; 13028 13029 u8 field_select[0x20]; 13030 13031 u8 admin_status[0x4]; 13032 u8 oper_status[0x4]; 13033 u8 ho_acq[0x1]; 13034 u8 reserved_at_49[0xc]; 13035 u8 admin_freq_measure[0x1]; 13036 u8 oper_freq_measure[0x1]; 13037 u8 failure_reason[0x9]; 13038 13039 u8 frequency_diff[0x20]; 13040 13041 u8 reserved_at_80[0x180]; 13042 }; 13043 13044 #endif /* MLX5_IFC_H */ 13045