1 /* SPDX-License-Identifier: GPL-2.0 */ 2 /* 3 * Functions to access TPS65219 Power Management IC. 4 * 5 * Copyright (C) 2022 BayLibre Incorporated - https://www.baylibre.com/ 6 */ 7 8 #ifndef MFD_TPS65219_H 9 #define MFD_TPS65219_H 10 11 #include <linux/bitops.h> 12 #include <linux/notifier.h> 13 #include <linux/regmap.h> 14 #include <linux/regulator/driver.h> 15 16 /* TPS chip id list */ 17 #define TPS65219 0xF0 18 19 /* I2C ID for TPS65219 part */ 20 #define TPS65219_I2C_ID 0x24 21 22 /* All register addresses */ 23 #define TPS65219_REG_TI_DEV_ID 0x00 24 #define TPS65219_REG_NVM_ID 0x01 25 #define TPS65219_REG_ENABLE_CTRL 0x02 26 #define TPS65219_REG_BUCKS_CONFIG 0x03 27 #define TPS65219_REG_LDO4_VOUT 0x04 28 #define TPS65219_REG_LDO3_VOUT 0x05 29 #define TPS65219_REG_LDO2_VOUT 0x06 30 #define TPS65219_REG_LDO1_VOUT 0x07 31 #define TPS65219_REG_BUCK3_VOUT 0x8 32 #define TPS65219_REG_BUCK2_VOUT 0x9 33 #define TPS65219_REG_BUCK1_VOUT 0xA 34 #define TPS65219_REG_LDO4_SEQUENCE_SLOT 0xB 35 #define TPS65219_REG_LDO3_SEQUENCE_SLOT 0xC 36 #define TPS65219_REG_LDO2_SEQUENCE_SLOT 0xD 37 #define TPS65219_REG_LDO1_SEQUENCE_SLOT 0xE 38 #define TPS65219_REG_BUCK3_SEQUENCE_SLOT 0xF 39 #define TPS65219_REG_BUCK2_SEQUENCE_SLOT 0x10 40 #define TPS65219_REG_BUCK1_SEQUENCE_SLOT 0x11 41 #define TPS65219_REG_nRST_SEQUENCE_SLOT 0x12 42 #define TPS65219_REG_GPIO_SEQUENCE_SLOT 0x13 43 #define TPS65219_REG_GPO2_SEQUENCE_SLOT 0x14 44 #define TPS65219_REG_GPO1_SEQUENCE_SLOT 0x15 45 #define TPS65219_REG_POWER_UP_SLOT_DURATION_1 0x16 46 #define TPS65219_REG_POWER_UP_SLOT_DURATION_2 0x17 47 #define TPS65219_REG_POWER_UP_SLOT_DURATION_3 0x18 48 #define TPS65219_REG_POWER_UP_SLOT_DURATION_4 0x19 49 #define TPS65219_REG_POWER_DOWN_SLOT_DURATION_1 0x1A 50 #define TPS65219_REG_POWER_DOWN_SLOT_DURATION_2 0x1B 51 #define TPS65219_REG_POWER_DOWN_SLOT_DURATION_3 0x1C 52 #define TPS65219_REG_POWER_DOWN_SLOT_DURATION_4 0x1D 53 #define TPS65219_REG_GENERAL_CONFIG 0x1E 54 #define TPS65219_REG_MFP_1_CONFIG 0x1F 55 #define TPS65219_REG_MFP_2_CONFIG 0x20 56 #define TPS65219_REG_STBY_1_CONFIG 0x21 57 #define TPS65219_REG_STBY_2_CONFIG 0x22 58 #define TPS65219_REG_OC_DEGL_CONFIG 0x23 59 /* 'sub irq' MASK registers */ 60 #define TPS65219_REG_INT_MASK_UV 0x24 61 #define TPS65219_REG_MASK_CONFIG 0x25 62 63 #define TPS65219_REG_I2C_ADDRESS_REG 0x26 64 #define TPS65219_REG_USER_GENERAL_NVM_STORAGE 0x27 65 #define TPS65219_REG_MANUFACTURING_VER 0x28 66 #define TPS65219_REG_MFP_CTRL 0x29 67 #define TPS65219_REG_DISCHARGE_CONFIG 0x2A 68 /* main irq registers */ 69 #define TPS65219_REG_INT_SOURCE 0x2B 70 /* 'sub irq' registers */ 71 #define TPS65219_REG_INT_LDO_3_4 0x2C 72 #define TPS65219_REG_INT_LDO_1_2 0x2D 73 #define TPS65219_REG_INT_BUCK_3 0x2E 74 #define TPS65219_REG_INT_BUCK_1_2 0x2F 75 #define TPS65219_REG_INT_SYSTEM 0x30 76 #define TPS65219_REG_INT_RV 0x31 77 #define TPS65219_REG_INT_TIMEOUT_RV_SD 0x32 78 #define TPS65219_REG_INT_PB 0x33 79 80 #define TPS65219_REG_INT_LDO_3_4_POS 0 81 #define TPS65219_REG_INT_LDO_1_2_POS 1 82 #define TPS65219_REG_INT_BUCK_3_POS 2 83 #define TPS65219_REG_INT_BUCK_1_2_POS 3 84 #define TPS65219_REG_INT_SYS_POS 4 85 #define TPS65219_REG_INT_RV_POS 5 86 #define TPS65219_REG_INT_TO_RV_POS 6 87 #define TPS65219_REG_INT_PB_POS 7 88 89 #define TPS65219_REG_USER_NVM_CMD 0x34 90 #define TPS65219_REG_POWER_UP_STATUS 0x35 91 #define TPS65219_REG_SPARE_2 0x36 92 #define TPS65219_REG_SPARE_3 0x37 93 #define TPS65219_REG_FACTORY_CONFIG_2 0x41 94 95 /* Register field definitions */ 96 #define TPS65219_DEVID_REV_MASK GENMASK(7, 0) 97 #define TPS65219_BUCKS_LDOS_VOUT_VSET_MASK GENMASK(5, 0) 98 #define TPS65219_BUCKS_UV_THR_SEL_MASK BIT(6) 99 #define TPS65219_BUCKS_BW_SEL_MASK BIT(7) 100 #define LDO_BYP_SHIFT 6 101 #define TPS65219_LDOS_BYP_CONFIG_MASK BIT(LDO_BYP_SHIFT) 102 #define TPS65219_LDOS_LSW_CONFIG_MASK BIT(7) 103 /* Regulators enable control */ 104 #define TPS65219_ENABLE_BUCK1_EN_MASK BIT(0) 105 #define TPS65219_ENABLE_BUCK2_EN_MASK BIT(1) 106 #define TPS65219_ENABLE_BUCK3_EN_MASK BIT(2) 107 #define TPS65219_ENABLE_LDO1_EN_MASK BIT(3) 108 #define TPS65219_ENABLE_LDO2_EN_MASK BIT(4) 109 #define TPS65219_ENABLE_LDO3_EN_MASK BIT(5) 110 #define TPS65219_ENABLE_LDO4_EN_MASK BIT(6) 111 /* power ON-OFF sequence slot */ 112 #define TPS65219_BUCKS_LDOS_SEQUENCE_OFF_SLOT_MASK GENMASK(3, 0) 113 #define TPS65219_BUCKS_LDOS_SEQUENCE_ON_SLOT_MASK GENMASK(7, 4) 114 /* TODO: Not needed, same mapping as TPS65219_ENABLE_REGNAME_EN, factorize */ 115 #define TPS65219_STBY1_BUCK1_STBY_EN_MASK BIT(0) 116 #define TPS65219_STBY1_BUCK2_STBY_EN_MASK BIT(1) 117 #define TPS65219_STBY1_BUCK3_STBY_EN_MASK BIT(2) 118 #define TPS65219_STBY1_LDO1_STBY_EN_MASK BIT(3) 119 #define TPS65219_STBY1_LDO2_STBY_EN_MASK BIT(4) 120 #define TPS65219_STBY1_LDO3_STBY_EN_MASK BIT(5) 121 #define TPS65219_STBY1_LDO4_STBY_EN_MASK BIT(6) 122 /* STBY_2 config */ 123 #define TPS65219_STBY2_GPO1_STBY_EN_MASK BIT(0) 124 #define TPS65219_STBY2_GPO2_STBY_EN_MASK BIT(1) 125 #define TPS65219_STBY2_GPIO_STBY_EN_MASK BIT(2) 126 /* MFP Control */ 127 #define TPS65219_MFP_I2C_OFF_REQ_MASK BIT(0) 128 #define TPS65219_MFP_STBY_I2C_CTRL_MASK BIT(1) 129 #define TPS65219_MFP_COLD_RESET_I2C_CTRL_MASK BIT(2) 130 #define TPS65219_MFP_WARM_RESET_I2C_CTRL_MASK BIT(3) 131 #define TPS65219_MFP_GPIO_STATUS_MASK BIT(4) 132 /* MFP_1 Config */ 133 #define TPS65219_MFP_1_VSEL_DDR_SEL_MASK BIT(0) 134 #define TPS65219_MFP_1_VSEL_SD_POL_MASK BIT(1) 135 #define TPS65219_MFP_1_VSEL_RAIL_MASK BIT(2) 136 /* MFP_2 Config */ 137 #define TPS65219_MFP_2_MODE_STBY_MASK GENMASK(1, 0) 138 #define TPS65219_MFP_2_MODE_RESET_MASK BIT(2) 139 #define TPS65219_MFP_2_EN_PB_VSENSE_DEGL_MASK BIT(3) 140 #define TPS65219_MFP_2_EN_PB_VSENSE_MASK GENMASK(5, 4) 141 #define TPS65219_MFP_2_WARM_COLD_RESET_MASK BIT(6) 142 #define TPS65219_MFP_2_PU_ON_FSD_MASK BIT(7) 143 #define TPS65219_MFP_2_EN 0 144 #define TPS65219_MFP_2_PB BIT(4) 145 #define TPS65219_MFP_2_VSENSE BIT(5) 146 /* MASK_UV Config */ 147 #define TPS65219_REG_MASK_UV_LDO1_UV_MASK BIT(0) 148 #define TPS65219_REG_MASK_UV_LDO2_UV_MASK BIT(1) 149 #define TPS65219_REG_MASK_UV_LDO3_UV_MASK BIT(2) 150 #define TPS65219_REG_MASK_UV_LDO4_UV_MASK BIT(3) 151 #define TPS65219_REG_MASK_UV_BUCK1_UV_MASK BIT(4) 152 #define TPS65219_REG_MASK_UV_BUCK2_UV_MASK BIT(5) 153 #define TPS65219_REG_MASK_UV_BUCK3_UV_MASK BIT(6) 154 #define TPS65219_REG_MASK_UV_RETRY_MASK BIT(7) 155 /* MASK Config */ 156 // SENSOR_N_WARM_MASK already defined in Thermal 157 #define TPS65219_REG_MASK_INT_FOR_RV_MASK BIT(4) 158 #define TPS65219_REG_MASK_EFFECT_MASK GENMASK(2, 1) 159 #define TPS65219_REG_MASK_INT_FOR_PB_MASK BIT(7) 160 /* UnderVoltage - Short to GND - OverCurrent*/ 161 /* LDO3-4 */ 162 #define TPS65219_INT_LDO3_SCG_MASK BIT(0) 163 #define TPS65219_INT_LDO3_OC_MASK BIT(1) 164 #define TPS65219_INT_LDO3_UV_MASK BIT(2) 165 #define TPS65219_INT_LDO4_SCG_MASK BIT(3) 166 #define TPS65219_INT_LDO4_OC_MASK BIT(4) 167 #define TPS65219_INT_LDO4_UV_MASK BIT(5) 168 /* LDO1-2 */ 169 #define TPS65219_INT_LDO1_SCG_MASK BIT(0) 170 #define TPS65219_INT_LDO1_OC_MASK BIT(1) 171 #define TPS65219_INT_LDO1_UV_MASK BIT(2) 172 #define TPS65219_INT_LDO2_SCG_MASK BIT(3) 173 #define TPS65219_INT_LDO2_OC_MASK BIT(4) 174 #define TPS65219_INT_LDO2_UV_MASK BIT(5) 175 /* BUCK3 */ 176 #define TPS65219_INT_BUCK3_SCG_MASK BIT(0) 177 #define TPS65219_INT_BUCK3_OC_MASK BIT(1) 178 #define TPS65219_INT_BUCK3_NEG_OC_MASK BIT(2) 179 #define TPS65219_INT_BUCK3_UV_MASK BIT(3) 180 /* BUCK1-2 */ 181 #define TPS65219_INT_BUCK1_SCG_MASK BIT(0) 182 #define TPS65219_INT_BUCK1_OC_MASK BIT(1) 183 #define TPS65219_INT_BUCK1_NEG_OC_MASK BIT(2) 184 #define TPS65219_INT_BUCK1_UV_MASK BIT(3) 185 #define TPS65219_INT_BUCK2_SCG_MASK BIT(4) 186 #define TPS65219_INT_BUCK2_OC_MASK BIT(5) 187 #define TPS65219_INT_BUCK2_NEG_OC_MASK BIT(6) 188 #define TPS65219_INT_BUCK2_UV_MASK BIT(7) 189 /* Thermal Sensor */ 190 #define TPS65219_INT_SENSOR_3_WARM_MASK BIT(0) 191 #define TPS65219_INT_SENSOR_2_WARM_MASK BIT(1) 192 #define TPS65219_INT_SENSOR_1_WARM_MASK BIT(2) 193 #define TPS65219_INT_SENSOR_0_WARM_MASK BIT(3) 194 #define TPS65219_INT_SENSOR_3_HOT_MASK BIT(4) 195 #define TPS65219_INT_SENSOR_2_HOT_MASK BIT(5) 196 #define TPS65219_INT_SENSOR_1_HOT_MASK BIT(6) 197 #define TPS65219_INT_SENSOR_0_HOT_MASK BIT(7) 198 /* Residual Voltage */ 199 #define TPS65219_INT_BUCK1_RV_MASK BIT(0) 200 #define TPS65219_INT_BUCK2_RV_MASK BIT(1) 201 #define TPS65219_INT_BUCK3_RV_MASK BIT(2) 202 #define TPS65219_INT_LDO1_RV_MASK BIT(3) 203 #define TPS65219_INT_LDO2_RV_MASK BIT(4) 204 #define TPS65219_INT_LDO3_RV_MASK BIT(5) 205 #define TPS65219_INT_LDO4_RV_MASK BIT(6) 206 /* Residual Voltage ShutDown */ 207 #define TPS65219_INT_BUCK1_RV_SD_MASK BIT(0) 208 #define TPS65219_INT_BUCK2_RV_SD_MASK BIT(1) 209 #define TPS65219_INT_BUCK3_RV_SD_MASK BIT(2) 210 #define TPS65219_INT_LDO1_RV_SD_MASK BIT(3) 211 #define TPS65219_INT_LDO2_RV_SD_MASK BIT(4) 212 #define TPS65219_INT_LDO3_RV_SD_MASK BIT(5) 213 #define TPS65219_INT_LDO4_RV_SD_MASK BIT(6) 214 #define TPS65219_INT_TIMEOUT_MASK BIT(7) 215 /* Power Button */ 216 #define TPS65219_INT_PB_FALLING_EDGE_DETECT_MASK BIT(0) 217 #define TPS65219_INT_PB_RISING_EDGE_DETECT_MASK BIT(1) 218 #define TPS65219_INT_PB_REAL_TIME_STATUS_MASK BIT(2) 219 220 #define TPS65219_PB_POS 7 221 #define TPS65219_TO_RV_POS 6 222 #define TPS65219_RV_POS 5 223 #define TPS65219_SYS_POS 4 224 #define TPS65219_BUCK_1_2_POS 3 225 #define TPS65219_BUCK_3_POS 2 226 #define TPS65219_LDO_1_2_POS 1 227 #define TPS65219_LDO_3_4_POS 0 228 229 /* IRQs */ 230 enum { 231 /* LDO3-4 register IRQs */ 232 TPS65219_INT_LDO3_SCG, 233 TPS65219_INT_LDO3_OC, 234 TPS65219_INT_LDO3_UV, 235 TPS65219_INT_LDO4_SCG, 236 TPS65219_INT_LDO4_OC, 237 TPS65219_INT_LDO4_UV, 238 /* LDO1-2 */ 239 TPS65219_INT_LDO1_SCG, 240 TPS65219_INT_LDO1_OC, 241 TPS65219_INT_LDO1_UV, 242 TPS65219_INT_LDO2_SCG, 243 TPS65219_INT_LDO2_OC, 244 TPS65219_INT_LDO2_UV, 245 /* BUCK3 */ 246 TPS65219_INT_BUCK3_SCG, 247 TPS65219_INT_BUCK3_OC, 248 TPS65219_INT_BUCK3_NEG_OC, 249 TPS65219_INT_BUCK3_UV, 250 /* BUCK1-2 */ 251 TPS65219_INT_BUCK1_SCG, 252 TPS65219_INT_BUCK1_OC, 253 TPS65219_INT_BUCK1_NEG_OC, 254 TPS65219_INT_BUCK1_UV, 255 TPS65219_INT_BUCK2_SCG, 256 TPS65219_INT_BUCK2_OC, 257 TPS65219_INT_BUCK2_NEG_OC, 258 TPS65219_INT_BUCK2_UV, 259 /* Thermal Sensor */ 260 TPS65219_INT_SENSOR_3_WARM, 261 TPS65219_INT_SENSOR_2_WARM, 262 TPS65219_INT_SENSOR_1_WARM, 263 TPS65219_INT_SENSOR_0_WARM, 264 TPS65219_INT_SENSOR_3_HOT, 265 TPS65219_INT_SENSOR_2_HOT, 266 TPS65219_INT_SENSOR_1_HOT, 267 TPS65219_INT_SENSOR_0_HOT, 268 /* Residual Voltage */ 269 TPS65219_INT_BUCK1_RV, 270 TPS65219_INT_BUCK2_RV, 271 TPS65219_INT_BUCK3_RV, 272 TPS65219_INT_LDO1_RV, 273 TPS65219_INT_LDO2_RV, 274 TPS65219_INT_LDO3_RV, 275 TPS65219_INT_LDO4_RV, 276 /* Residual Voltage ShutDown */ 277 TPS65219_INT_BUCK1_RV_SD, 278 TPS65219_INT_BUCK2_RV_SD, 279 TPS65219_INT_BUCK3_RV_SD, 280 TPS65219_INT_LDO1_RV_SD, 281 TPS65219_INT_LDO2_RV_SD, 282 TPS65219_INT_LDO3_RV_SD, 283 TPS65219_INT_LDO4_RV_SD, 284 TPS65219_INT_TIMEOUT, 285 /* Power Button */ 286 TPS65219_INT_PB_FALLING_EDGE_DETECT, 287 TPS65219_INT_PB_RISING_EDGE_DETECT, 288 }; 289 290 enum tps65219_regulator_id { 291 /* DCDC's */ 292 TPS65219_BUCK_1, 293 TPS65219_BUCK_2, 294 TPS65219_BUCK_3, 295 /* LDOs */ 296 TPS65219_LDO_1, 297 TPS65219_LDO_2, 298 TPS65219_LDO_3, 299 TPS65219_LDO_4, 300 }; 301 302 /* Number of step-down converters available */ 303 #define TPS65219_NUM_DCDC 3 304 /* Number of LDO voltage regulators available */ 305 #define TPS65219_NUM_LDO 4 306 /* Number of total regulators available */ 307 #define TPS65219_NUM_REGULATOR (TPS65219_NUM_DCDC + TPS65219_NUM_LDO) 308 309 /* Define the TPS65219 IRQ numbers */ 310 enum tps65219_irqs { 311 /* INT source registers */ 312 TPS65219_TO_RV_SD_SET_IRQ, 313 TPS65219_RV_SET_IRQ, 314 TPS65219_SYS_SET_IRQ, 315 TPS65219_BUCK_1_2_SET_IRQ, 316 TPS65219_BUCK_3_SET_IRQ, 317 TPS65219_LDO_1_2_SET_IRQ, 318 TPS65219_LDO_3_4_SET_IRQ, 319 TPS65219_PB_SET_IRQ, 320 }; 321 322 /** 323 * struct tps65219 - tps65219 sub-driver chip access routines 324 * 325 * Device data may be used to access the TPS65219 chip 326 * 327 * @dev: MFD device 328 * @regmap: Regmap for accessing the device registers 329 * @irq_data: Regmap irq data used for the irq chip 330 * @nb: notifier block for the restart handler 331 */ 332 struct tps65219 { 333 struct device *dev; 334 struct regmap *regmap; 335 336 struct regmap_irq_chip_data *irq_data; 337 struct notifier_block nb; 338 }; 339 340 #endif /* MFD_TPS65219_H */ 341