xref: /linux/include/linux/mfd/pcf50633/pmic.h (revision 498495dba268b20e8eadd7fe93c140c68b6cc9d2)
1*b2441318SGreg Kroah-Hartman /* SPDX-License-Identifier: GPL-2.0 */
25ec271e7SBalaji Rao #ifndef __LINUX_MFD_PCF50633_PMIC_H
35ec271e7SBalaji Rao #define __LINUX_MFD_PCF50633_PMIC_H
45ec271e7SBalaji Rao 
55ec271e7SBalaji Rao #include <linux/mfd/pcf50633/core.h>
65ec271e7SBalaji Rao #include <linux/platform_device.h>
75ec271e7SBalaji Rao 
85ec271e7SBalaji Rao #define PCF50633_REG_AUTOOUT	0x1a
95ec271e7SBalaji Rao #define PCF50633_REG_AUTOENA	0x1b
105ec271e7SBalaji Rao #define PCF50633_REG_AUTOCTL	0x1c
115ec271e7SBalaji Rao #define PCF50633_REG_AUTOMXC	0x1d
125ec271e7SBalaji Rao #define PCF50633_REG_DOWN1OUT	0x1e
135ec271e7SBalaji Rao #define PCF50633_REG_DOWN1ENA	0x1f
145ec271e7SBalaji Rao #define PCF50633_REG_DOWN1CTL	0x20
155ec271e7SBalaji Rao #define PCF50633_REG_DOWN1MXC	0x21
165ec271e7SBalaji Rao #define PCF50633_REG_DOWN2OUT	0x22
175ec271e7SBalaji Rao #define PCF50633_REG_DOWN2ENA	0x23
185ec271e7SBalaji Rao #define PCF50633_REG_DOWN2CTL	0x24
195ec271e7SBalaji Rao #define PCF50633_REG_DOWN2MXC	0x25
205ec271e7SBalaji Rao #define PCF50633_REG_MEMLDOOUT	0x26
215ec271e7SBalaji Rao #define PCF50633_REG_MEMLDOENA	0x27
225ec271e7SBalaji Rao #define PCF50633_REG_LDO1OUT	0x2d
235ec271e7SBalaji Rao #define PCF50633_REG_LDO1ENA	0x2e
245ec271e7SBalaji Rao #define PCF50633_REG_LDO2OUT	0x2f
255ec271e7SBalaji Rao #define PCF50633_REG_LDO2ENA	0x30
265ec271e7SBalaji Rao #define PCF50633_REG_LDO3OUT	0x31
275ec271e7SBalaji Rao #define PCF50633_REG_LDO3ENA	0x32
285ec271e7SBalaji Rao #define PCF50633_REG_LDO4OUT	0x33
295ec271e7SBalaji Rao #define PCF50633_REG_LDO4ENA	0x34
305ec271e7SBalaji Rao #define PCF50633_REG_LDO5OUT	0x35
315ec271e7SBalaji Rao #define PCF50633_REG_LDO5ENA	0x36
325ec271e7SBalaji Rao #define PCF50633_REG_LDO6OUT	0x37
335ec271e7SBalaji Rao #define PCF50633_REG_LDO6ENA	0x38
345ec271e7SBalaji Rao #define PCF50633_REG_HCLDOOUT	0x39
355ec271e7SBalaji Rao #define PCF50633_REG_HCLDOENA	0x3a
365ec271e7SBalaji Rao #define PCF50633_REG_HCLDOOVL	0x40
375ec271e7SBalaji Rao 
385ec271e7SBalaji Rao enum pcf50633_regulator_enable {
395ec271e7SBalaji Rao 	PCF50633_REGULATOR_ON		= 0x01,
405ec271e7SBalaji Rao 	PCF50633_REGULATOR_ON_GPIO1	= 0x02,
415ec271e7SBalaji Rao 	PCF50633_REGULATOR_ON_GPIO2	= 0x04,
425ec271e7SBalaji Rao 	PCF50633_REGULATOR_ON_GPIO3	= 0x08,
435ec271e7SBalaji Rao };
445ec271e7SBalaji Rao #define PCF50633_REGULATOR_ON_MASK	0x0f
455ec271e7SBalaji Rao 
465ec271e7SBalaji Rao enum pcf50633_regulator_phase {
475ec271e7SBalaji Rao 	PCF50633_REGULATOR_ACTPH1	= 0x00,
485ec271e7SBalaji Rao 	PCF50633_REGULATOR_ACTPH2	= 0x10,
495ec271e7SBalaji Rao 	PCF50633_REGULATOR_ACTPH3	= 0x20,
505ec271e7SBalaji Rao 	PCF50633_REGULATOR_ACTPH4	= 0x30,
515ec271e7SBalaji Rao };
525ec271e7SBalaji Rao #define PCF50633_REGULATOR_ACTPH_MASK	0x30
535ec271e7SBalaji Rao 
545ec271e7SBalaji Rao enum pcf50633_regulator_id {
555ec271e7SBalaji Rao 	PCF50633_REGULATOR_AUTO,
565ec271e7SBalaji Rao 	PCF50633_REGULATOR_DOWN1,
575ec271e7SBalaji Rao 	PCF50633_REGULATOR_DOWN2,
585ec271e7SBalaji Rao 	PCF50633_REGULATOR_LDO1,
595ec271e7SBalaji Rao 	PCF50633_REGULATOR_LDO2,
605ec271e7SBalaji Rao 	PCF50633_REGULATOR_LDO3,
615ec271e7SBalaji Rao 	PCF50633_REGULATOR_LDO4,
625ec271e7SBalaji Rao 	PCF50633_REGULATOR_LDO5,
635ec271e7SBalaji Rao 	PCF50633_REGULATOR_LDO6,
645ec271e7SBalaji Rao 	PCF50633_REGULATOR_HCLDO,
655ec271e7SBalaji Rao 	PCF50633_REGULATOR_MEMLDO,
665ec271e7SBalaji Rao };
675ec271e7SBalaji Rao #endif
685ec271e7SBalaji Rao 
69