1 /* 2 * core.h -- Core driver for NXP PCF50633 3 * 4 * (C) 2006-2008 by Openmoko, Inc. 5 * All rights reserved. 6 * 7 * This program is free software; you can redistribute it and/or modify it 8 * under the terms of the GNU General Public License as published by the 9 * Free Software Foundation; either version 2 of the License, or (at your 10 * option) any later version. 11 */ 12 13 #ifndef __LINUX_MFD_PCF50633_CORE_H 14 #define __LINUX_MFD_PCF50633_CORE_H 15 16 #include <linux/i2c.h> 17 #include <linux/workqueue.h> 18 #include <linux/regulator/driver.h> 19 #include <linux/regulator/machine.h> 20 #include <linux/power_supply.h> 21 #include <linux/mfd/pcf50633/backlight.h> 22 23 struct pcf50633; 24 struct regmap; 25 26 #define PCF50633_NUM_REGULATORS 11 27 28 struct pcf50633_platform_data { 29 struct regulator_init_data reg_init_data[PCF50633_NUM_REGULATORS]; 30 31 char **batteries; 32 int num_batteries; 33 34 /* 35 * Should be set accordingly to the reference resistor used, see 36 * I_{ch(ref)} charger reference current in the pcf50633 User 37 * Manual. 38 */ 39 int charger_reference_current_ma; 40 41 /* Callbacks */ 42 void (*probe_done)(struct pcf50633 *); 43 void (*mbc_event_callback)(struct pcf50633 *, int); 44 void (*regulator_registered)(struct pcf50633 *, int); 45 void (*force_shutdown)(struct pcf50633 *); 46 47 u8 resumers[5]; 48 49 struct pcf50633_bl_platform_data *backlight_data; 50 }; 51 52 struct pcf50633_irq { 53 void (*handler) (int, void *); 54 void *data; 55 }; 56 57 int pcf50633_register_irq(struct pcf50633 *pcf, int irq, 58 void (*handler) (int, void *), void *data); 59 int pcf50633_free_irq(struct pcf50633 *pcf, int irq); 60 61 int pcf50633_irq_mask(struct pcf50633 *pcf, int irq); 62 int pcf50633_irq_unmask(struct pcf50633 *pcf, int irq); 63 int pcf50633_irq_mask_get(struct pcf50633 *pcf, int irq); 64 65 int pcf50633_read_block(struct pcf50633 *, u8 reg, 66 int nr_regs, u8 *data); 67 int pcf50633_write_block(struct pcf50633 *pcf, u8 reg, 68 int nr_regs, u8 *data); 69 u8 pcf50633_reg_read(struct pcf50633 *, u8 reg); 70 int pcf50633_reg_write(struct pcf50633 *pcf, u8 reg, u8 val); 71 72 int pcf50633_reg_set_bit_mask(struct pcf50633 *pcf, u8 reg, u8 mask, u8 val); 73 int pcf50633_reg_clear_bits(struct pcf50633 *pcf, u8 reg, u8 bits); 74 75 /* Interrupt registers */ 76 77 #define PCF50633_REG_INT1 0x02 78 #define PCF50633_REG_INT2 0x03 79 #define PCF50633_REG_INT3 0x04 80 #define PCF50633_REG_INT4 0x05 81 #define PCF50633_REG_INT5 0x06 82 83 #define PCF50633_REG_INT1M 0x07 84 #define PCF50633_REG_INT2M 0x08 85 #define PCF50633_REG_INT3M 0x09 86 #define PCF50633_REG_INT4M 0x0a 87 #define PCF50633_REG_INT5M 0x0b 88 89 enum { 90 /* Chip IRQs */ 91 PCF50633_IRQ_ADPINS, 92 PCF50633_IRQ_ADPREM, 93 PCF50633_IRQ_USBINS, 94 PCF50633_IRQ_USBREM, 95 PCF50633_IRQ_RESERVED1, 96 PCF50633_IRQ_RESERVED2, 97 PCF50633_IRQ_ALARM, 98 PCF50633_IRQ_SECOND, 99 PCF50633_IRQ_ONKEYR, 100 PCF50633_IRQ_ONKEYF, 101 PCF50633_IRQ_EXTON1R, 102 PCF50633_IRQ_EXTON1F, 103 PCF50633_IRQ_EXTON2R, 104 PCF50633_IRQ_EXTON2F, 105 PCF50633_IRQ_EXTON3R, 106 PCF50633_IRQ_EXTON3F, 107 PCF50633_IRQ_BATFULL, 108 PCF50633_IRQ_CHGHALT, 109 PCF50633_IRQ_THLIMON, 110 PCF50633_IRQ_THLIMOFF, 111 PCF50633_IRQ_USBLIMON, 112 PCF50633_IRQ_USBLIMOFF, 113 PCF50633_IRQ_ADCRDY, 114 PCF50633_IRQ_ONKEY1S, 115 PCF50633_IRQ_LOWSYS, 116 PCF50633_IRQ_LOWBAT, 117 PCF50633_IRQ_HIGHTMP, 118 PCF50633_IRQ_AUTOPWRFAIL, 119 PCF50633_IRQ_DWN1PWRFAIL, 120 PCF50633_IRQ_DWN2PWRFAIL, 121 PCF50633_IRQ_LEDPWRFAIL, 122 PCF50633_IRQ_LEDOVP, 123 PCF50633_IRQ_LDO1PWRFAIL, 124 PCF50633_IRQ_LDO2PWRFAIL, 125 PCF50633_IRQ_LDO3PWRFAIL, 126 PCF50633_IRQ_LDO4PWRFAIL, 127 PCF50633_IRQ_LDO5PWRFAIL, 128 PCF50633_IRQ_LDO6PWRFAIL, 129 PCF50633_IRQ_HCLDOPWRFAIL, 130 PCF50633_IRQ_HCLDOOVL, 131 132 /* Always last */ 133 PCF50633_NUM_IRQ, 134 }; 135 136 struct pcf50633 { 137 struct device *dev; 138 struct regmap *regmap; 139 140 struct pcf50633_platform_data *pdata; 141 int irq; 142 struct pcf50633_irq irq_handler[PCF50633_NUM_IRQ]; 143 struct work_struct irq_work; 144 struct workqueue_struct *work_queue; 145 struct mutex lock; 146 147 u8 mask_regs[5]; 148 149 u8 suspend_irq_masks[5]; 150 u8 resume_reason[5]; 151 int is_suspended; 152 153 int onkey1s_held; 154 155 struct platform_device *rtc_pdev; 156 struct platform_device *mbc_pdev; 157 struct platform_device *adc_pdev; 158 struct platform_device *input_pdev; 159 struct platform_device *bl_pdev; 160 struct platform_device *regulator_pdev[PCF50633_NUM_REGULATORS]; 161 }; 162 163 enum pcf50633_reg_int1 { 164 PCF50633_INT1_ADPINS = 0x01, /* Adapter inserted */ 165 PCF50633_INT1_ADPREM = 0x02, /* Adapter removed */ 166 PCF50633_INT1_USBINS = 0x04, /* USB inserted */ 167 PCF50633_INT1_USBREM = 0x08, /* USB removed */ 168 /* reserved */ 169 PCF50633_INT1_ALARM = 0x40, /* RTC alarm time is reached */ 170 PCF50633_INT1_SECOND = 0x80, /* RTC periodic second interrupt */ 171 }; 172 173 enum pcf50633_reg_int2 { 174 PCF50633_INT2_ONKEYR = 0x01, /* ONKEY rising edge */ 175 PCF50633_INT2_ONKEYF = 0x02, /* ONKEY falling edge */ 176 PCF50633_INT2_EXTON1R = 0x04, /* EXTON1 rising edge */ 177 PCF50633_INT2_EXTON1F = 0x08, /* EXTON1 falling edge */ 178 PCF50633_INT2_EXTON2R = 0x10, /* EXTON2 rising edge */ 179 PCF50633_INT2_EXTON2F = 0x20, /* EXTON2 falling edge */ 180 PCF50633_INT2_EXTON3R = 0x40, /* EXTON3 rising edge */ 181 PCF50633_INT2_EXTON3F = 0x80, /* EXTON3 falling edge */ 182 }; 183 184 enum pcf50633_reg_int3 { 185 PCF50633_INT3_BATFULL = 0x01, /* Battery full */ 186 PCF50633_INT3_CHGHALT = 0x02, /* Charger halt */ 187 PCF50633_INT3_THLIMON = 0x04, 188 PCF50633_INT3_THLIMOFF = 0x08, 189 PCF50633_INT3_USBLIMON = 0x10, 190 PCF50633_INT3_USBLIMOFF = 0x20, 191 PCF50633_INT3_ADCRDY = 0x40, /* ADC result ready */ 192 PCF50633_INT3_ONKEY1S = 0x80, /* ONKEY pressed 1 second */ 193 }; 194 195 enum pcf50633_reg_int4 { 196 PCF50633_INT4_LOWSYS = 0x01, 197 PCF50633_INT4_LOWBAT = 0x02, 198 PCF50633_INT4_HIGHTMP = 0x04, 199 PCF50633_INT4_AUTOPWRFAIL = 0x08, 200 PCF50633_INT4_DWN1PWRFAIL = 0x10, 201 PCF50633_INT4_DWN2PWRFAIL = 0x20, 202 PCF50633_INT4_LEDPWRFAIL = 0x40, 203 PCF50633_INT4_LEDOVP = 0x80, 204 }; 205 206 enum pcf50633_reg_int5 { 207 PCF50633_INT5_LDO1PWRFAIL = 0x01, 208 PCF50633_INT5_LDO2PWRFAIL = 0x02, 209 PCF50633_INT5_LDO3PWRFAIL = 0x04, 210 PCF50633_INT5_LDO4PWRFAIL = 0x08, 211 PCF50633_INT5_LDO5PWRFAIL = 0x10, 212 PCF50633_INT5_LDO6PWRFAIL = 0x20, 213 PCF50633_INT5_HCLDOPWRFAIL = 0x40, 214 PCF50633_INT5_HCLDOOVL = 0x80, 215 }; 216 217 /* misc. registers */ 218 #define PCF50633_REG_OOCSHDWN 0x0c 219 220 /* LED registers */ 221 #define PCF50633_REG_LEDOUT 0x28 222 #define PCF50633_REG_LEDENA 0x29 223 #define PCF50633_REG_LEDCTL 0x2a 224 #define PCF50633_REG_LEDDIM 0x2b 225 226 static inline struct pcf50633 *dev_to_pcf50633(struct device *dev) 227 { 228 return dev_get_drvdata(dev); 229 } 230 231 int pcf50633_irq_init(struct pcf50633 *pcf, int irq); 232 void pcf50633_irq_free(struct pcf50633 *pcf); 233 #ifdef CONFIG_PM 234 int pcf50633_irq_suspend(struct pcf50633 *pcf); 235 int pcf50633_irq_resume(struct pcf50633 *pcf); 236 #endif 237 238 #endif 239