12874c5fdSThomas Gleixner /* SPDX-License-Identifier: GPL-2.0-or-later */
2f52046b1SBalaji Rao /*
3f52046b1SBalaji Rao * core.h -- Core driver for NXP PCF50633
4f52046b1SBalaji Rao *
5f52046b1SBalaji Rao * (C) 2006-2008 by Openmoko, Inc.
6f52046b1SBalaji Rao * All rights reserved.
7f52046b1SBalaji Rao */
8f52046b1SBalaji Rao
9f52046b1SBalaji Rao #ifndef __LINUX_MFD_PCF50633_CORE_H
10f52046b1SBalaji Rao #define __LINUX_MFD_PCF50633_CORE_H
11f52046b1SBalaji Rao
12f52046b1SBalaji Rao #include <linux/i2c.h>
13f52046b1SBalaji Rao #include <linux/workqueue.h>
14f52046b1SBalaji Rao #include <linux/regulator/driver.h>
15f52046b1SBalaji Rao #include <linux/regulator/machine.h>
16*245cb473SPaul Cercueil #include <linux/pm.h>
17f52046b1SBalaji Rao #include <linux/power_supply.h>
18f5bf403aSLars-Peter Clausen #include <linux/mfd/pcf50633/backlight.h>
19f52046b1SBalaji Rao
20f52046b1SBalaji Rao struct pcf50633;
216e3ad118SMark Brown struct regmap;
22f52046b1SBalaji Rao
23f52046b1SBalaji Rao #define PCF50633_NUM_REGULATORS 11
24f52046b1SBalaji Rao
25f52046b1SBalaji Rao struct pcf50633_platform_data {
26f52046b1SBalaji Rao struct regulator_init_data reg_init_data[PCF50633_NUM_REGULATORS];
27f52046b1SBalaji Rao
28f52046b1SBalaji Rao char **batteries;
29f52046b1SBalaji Rao int num_batteries;
30f52046b1SBalaji Rao
3131b4ff06SBalaji Rao /*
3231b4ff06SBalaji Rao * Should be set accordingly to the reference resistor used, see
3331b4ff06SBalaji Rao * I_{ch(ref)} charger reference current in the pcf50633 User
3431b4ff06SBalaji Rao * Manual.
3531b4ff06SBalaji Rao */
3631b4ff06SBalaji Rao int charger_reference_current_ma;
379705ecc5SBalaji Rao
38f52046b1SBalaji Rao /* Callbacks */
39f52046b1SBalaji Rao void (*probe_done)(struct pcf50633 *);
40f52046b1SBalaji Rao void (*mbc_event_callback)(struct pcf50633 *, int);
41f52046b1SBalaji Rao void (*regulator_registered)(struct pcf50633 *, int);
42f52046b1SBalaji Rao void (*force_shutdown)(struct pcf50633 *);
43f52046b1SBalaji Rao
44f52046b1SBalaji Rao u8 resumers[5];
45f5bf403aSLars-Peter Clausen
46f5bf403aSLars-Peter Clausen struct pcf50633_bl_platform_data *backlight_data;
47f52046b1SBalaji Rao };
48f52046b1SBalaji Rao
49f52046b1SBalaji Rao struct pcf50633_irq {
50f52046b1SBalaji Rao void (*handler) (int, void *);
51f52046b1SBalaji Rao void *data;
52f52046b1SBalaji Rao };
53f52046b1SBalaji Rao
54f52046b1SBalaji Rao int pcf50633_register_irq(struct pcf50633 *pcf, int irq,
55f52046b1SBalaji Rao void (*handler) (int, void *), void *data);
56f52046b1SBalaji Rao int pcf50633_free_irq(struct pcf50633 *pcf, int irq);
57f52046b1SBalaji Rao
58f52046b1SBalaji Rao int pcf50633_irq_mask(struct pcf50633 *pcf, int irq);
59f52046b1SBalaji Rao int pcf50633_irq_unmask(struct pcf50633 *pcf, int irq);
60f52046b1SBalaji Rao int pcf50633_irq_mask_get(struct pcf50633 *pcf, int irq);
61f52046b1SBalaji Rao
62f52046b1SBalaji Rao int pcf50633_read_block(struct pcf50633 *, u8 reg,
63f52046b1SBalaji Rao int nr_regs, u8 *data);
64f52046b1SBalaji Rao int pcf50633_write_block(struct pcf50633 *pcf, u8 reg,
65f52046b1SBalaji Rao int nr_regs, u8 *data);
66f52046b1SBalaji Rao u8 pcf50633_reg_read(struct pcf50633 *, u8 reg);
67f52046b1SBalaji Rao int pcf50633_reg_write(struct pcf50633 *pcf, u8 reg, u8 val);
68f52046b1SBalaji Rao
69f52046b1SBalaji Rao int pcf50633_reg_set_bit_mask(struct pcf50633 *pcf, u8 reg, u8 mask, u8 val);
70f52046b1SBalaji Rao int pcf50633_reg_clear_bits(struct pcf50633 *pcf, u8 reg, u8 bits);
71f52046b1SBalaji Rao
72f52046b1SBalaji Rao /* Interrupt registers */
73f52046b1SBalaji Rao
74f52046b1SBalaji Rao #define PCF50633_REG_INT1 0x02
75f52046b1SBalaji Rao #define PCF50633_REG_INT2 0x03
76f52046b1SBalaji Rao #define PCF50633_REG_INT3 0x04
77f52046b1SBalaji Rao #define PCF50633_REG_INT4 0x05
78f52046b1SBalaji Rao #define PCF50633_REG_INT5 0x06
79f52046b1SBalaji Rao
80f52046b1SBalaji Rao #define PCF50633_REG_INT1M 0x07
81f52046b1SBalaji Rao #define PCF50633_REG_INT2M 0x08
82f52046b1SBalaji Rao #define PCF50633_REG_INT3M 0x09
83f52046b1SBalaji Rao #define PCF50633_REG_INT4M 0x0a
84f52046b1SBalaji Rao #define PCF50633_REG_INT5M 0x0b
85f52046b1SBalaji Rao
86f52046b1SBalaji Rao enum {
87f52046b1SBalaji Rao /* Chip IRQs */
88f52046b1SBalaji Rao PCF50633_IRQ_ADPINS,
89f52046b1SBalaji Rao PCF50633_IRQ_ADPREM,
90f52046b1SBalaji Rao PCF50633_IRQ_USBINS,
91f52046b1SBalaji Rao PCF50633_IRQ_USBREM,
92f52046b1SBalaji Rao PCF50633_IRQ_RESERVED1,
93f52046b1SBalaji Rao PCF50633_IRQ_RESERVED2,
94f52046b1SBalaji Rao PCF50633_IRQ_ALARM,
95f52046b1SBalaji Rao PCF50633_IRQ_SECOND,
96f52046b1SBalaji Rao PCF50633_IRQ_ONKEYR,
97f52046b1SBalaji Rao PCF50633_IRQ_ONKEYF,
98f52046b1SBalaji Rao PCF50633_IRQ_EXTON1R,
99f52046b1SBalaji Rao PCF50633_IRQ_EXTON1F,
100f52046b1SBalaji Rao PCF50633_IRQ_EXTON2R,
101f52046b1SBalaji Rao PCF50633_IRQ_EXTON2F,
102f52046b1SBalaji Rao PCF50633_IRQ_EXTON3R,
103f52046b1SBalaji Rao PCF50633_IRQ_EXTON3F,
104f52046b1SBalaji Rao PCF50633_IRQ_BATFULL,
105f52046b1SBalaji Rao PCF50633_IRQ_CHGHALT,
106f52046b1SBalaji Rao PCF50633_IRQ_THLIMON,
107f52046b1SBalaji Rao PCF50633_IRQ_THLIMOFF,
108f52046b1SBalaji Rao PCF50633_IRQ_USBLIMON,
109f52046b1SBalaji Rao PCF50633_IRQ_USBLIMOFF,
110f52046b1SBalaji Rao PCF50633_IRQ_ADCRDY,
111f52046b1SBalaji Rao PCF50633_IRQ_ONKEY1S,
112f52046b1SBalaji Rao PCF50633_IRQ_LOWSYS,
113f52046b1SBalaji Rao PCF50633_IRQ_LOWBAT,
114f52046b1SBalaji Rao PCF50633_IRQ_HIGHTMP,
115f52046b1SBalaji Rao PCF50633_IRQ_AUTOPWRFAIL,
116f52046b1SBalaji Rao PCF50633_IRQ_DWN1PWRFAIL,
117f52046b1SBalaji Rao PCF50633_IRQ_DWN2PWRFAIL,
118f52046b1SBalaji Rao PCF50633_IRQ_LEDPWRFAIL,
119f52046b1SBalaji Rao PCF50633_IRQ_LEDOVP,
120f52046b1SBalaji Rao PCF50633_IRQ_LDO1PWRFAIL,
121f52046b1SBalaji Rao PCF50633_IRQ_LDO2PWRFAIL,
122f52046b1SBalaji Rao PCF50633_IRQ_LDO3PWRFAIL,
123f52046b1SBalaji Rao PCF50633_IRQ_LDO4PWRFAIL,
124f52046b1SBalaji Rao PCF50633_IRQ_LDO5PWRFAIL,
125f52046b1SBalaji Rao PCF50633_IRQ_LDO6PWRFAIL,
126f52046b1SBalaji Rao PCF50633_IRQ_HCLDOPWRFAIL,
127f52046b1SBalaji Rao PCF50633_IRQ_HCLDOOVL,
128f52046b1SBalaji Rao
129f52046b1SBalaji Rao /* Always last */
130f52046b1SBalaji Rao PCF50633_NUM_IRQ,
131f52046b1SBalaji Rao };
132f52046b1SBalaji Rao
133f52046b1SBalaji Rao struct pcf50633 {
134f52046b1SBalaji Rao struct device *dev;
1356e3ad118SMark Brown struct regmap *regmap;
136f52046b1SBalaji Rao
137f52046b1SBalaji Rao struct pcf50633_platform_data *pdata;
138f52046b1SBalaji Rao int irq;
139f52046b1SBalaji Rao struct pcf50633_irq irq_handler[PCF50633_NUM_IRQ];
140f52046b1SBalaji Rao struct work_struct irq_work;
141ed52e62eSPaul Fertser struct workqueue_struct *work_queue;
142f52046b1SBalaji Rao struct mutex lock;
143f52046b1SBalaji Rao
144f52046b1SBalaji Rao u8 mask_regs[5];
145f52046b1SBalaji Rao
146f52046b1SBalaji Rao u8 suspend_irq_masks[5];
147f52046b1SBalaji Rao u8 resume_reason[5];
148f52046b1SBalaji Rao int is_suspended;
149f52046b1SBalaji Rao
150f52046b1SBalaji Rao int onkey1s_held;
151f52046b1SBalaji Rao
152f52046b1SBalaji Rao struct platform_device *rtc_pdev;
153f52046b1SBalaji Rao struct platform_device *mbc_pdev;
154f52046b1SBalaji Rao struct platform_device *adc_pdev;
155f52046b1SBalaji Rao struct platform_device *input_pdev;
156f5bf403aSLars-Peter Clausen struct platform_device *bl_pdev;
157f52046b1SBalaji Rao struct platform_device *regulator_pdev[PCF50633_NUM_REGULATORS];
158f52046b1SBalaji Rao };
159f52046b1SBalaji Rao
160f52046b1SBalaji Rao enum pcf50633_reg_int1 {
161f52046b1SBalaji Rao PCF50633_INT1_ADPINS = 0x01, /* Adapter inserted */
162f52046b1SBalaji Rao PCF50633_INT1_ADPREM = 0x02, /* Adapter removed */
163f52046b1SBalaji Rao PCF50633_INT1_USBINS = 0x04, /* USB inserted */
164f52046b1SBalaji Rao PCF50633_INT1_USBREM = 0x08, /* USB removed */
165f52046b1SBalaji Rao /* reserved */
166f52046b1SBalaji Rao PCF50633_INT1_ALARM = 0x40, /* RTC alarm time is reached */
167f52046b1SBalaji Rao PCF50633_INT1_SECOND = 0x80, /* RTC periodic second interrupt */
168f52046b1SBalaji Rao };
169f52046b1SBalaji Rao
170f52046b1SBalaji Rao enum pcf50633_reg_int2 {
171f52046b1SBalaji Rao PCF50633_INT2_ONKEYR = 0x01, /* ONKEY rising edge */
172f52046b1SBalaji Rao PCF50633_INT2_ONKEYF = 0x02, /* ONKEY falling edge */
173f52046b1SBalaji Rao PCF50633_INT2_EXTON1R = 0x04, /* EXTON1 rising edge */
174f52046b1SBalaji Rao PCF50633_INT2_EXTON1F = 0x08, /* EXTON1 falling edge */
175f52046b1SBalaji Rao PCF50633_INT2_EXTON2R = 0x10, /* EXTON2 rising edge */
176f52046b1SBalaji Rao PCF50633_INT2_EXTON2F = 0x20, /* EXTON2 falling edge */
177f52046b1SBalaji Rao PCF50633_INT2_EXTON3R = 0x40, /* EXTON3 rising edge */
178f52046b1SBalaji Rao PCF50633_INT2_EXTON3F = 0x80, /* EXTON3 falling edge */
179f52046b1SBalaji Rao };
180f52046b1SBalaji Rao
181f52046b1SBalaji Rao enum pcf50633_reg_int3 {
182f52046b1SBalaji Rao PCF50633_INT3_BATFULL = 0x01, /* Battery full */
183f52046b1SBalaji Rao PCF50633_INT3_CHGHALT = 0x02, /* Charger halt */
184f52046b1SBalaji Rao PCF50633_INT3_THLIMON = 0x04,
185f52046b1SBalaji Rao PCF50633_INT3_THLIMOFF = 0x08,
186f52046b1SBalaji Rao PCF50633_INT3_USBLIMON = 0x10,
187f52046b1SBalaji Rao PCF50633_INT3_USBLIMOFF = 0x20,
188f52046b1SBalaji Rao PCF50633_INT3_ADCRDY = 0x40, /* ADC result ready */
189f52046b1SBalaji Rao PCF50633_INT3_ONKEY1S = 0x80, /* ONKEY pressed 1 second */
190f52046b1SBalaji Rao };
191f52046b1SBalaji Rao
192f52046b1SBalaji Rao enum pcf50633_reg_int4 {
193f52046b1SBalaji Rao PCF50633_INT4_LOWSYS = 0x01,
194f52046b1SBalaji Rao PCF50633_INT4_LOWBAT = 0x02,
195f52046b1SBalaji Rao PCF50633_INT4_HIGHTMP = 0x04,
196f52046b1SBalaji Rao PCF50633_INT4_AUTOPWRFAIL = 0x08,
197f52046b1SBalaji Rao PCF50633_INT4_DWN1PWRFAIL = 0x10,
198f52046b1SBalaji Rao PCF50633_INT4_DWN2PWRFAIL = 0x20,
199f52046b1SBalaji Rao PCF50633_INT4_LEDPWRFAIL = 0x40,
200f52046b1SBalaji Rao PCF50633_INT4_LEDOVP = 0x80,
201f52046b1SBalaji Rao };
202f52046b1SBalaji Rao
203f52046b1SBalaji Rao enum pcf50633_reg_int5 {
204f52046b1SBalaji Rao PCF50633_INT5_LDO1PWRFAIL = 0x01,
205f52046b1SBalaji Rao PCF50633_INT5_LDO2PWRFAIL = 0x02,
206f52046b1SBalaji Rao PCF50633_INT5_LDO3PWRFAIL = 0x04,
207f52046b1SBalaji Rao PCF50633_INT5_LDO4PWRFAIL = 0x08,
208f52046b1SBalaji Rao PCF50633_INT5_LDO5PWRFAIL = 0x10,
209f52046b1SBalaji Rao PCF50633_INT5_LDO6PWRFAIL = 0x20,
210f52046b1SBalaji Rao PCF50633_INT5_HCLDOPWRFAIL = 0x40,
211f52046b1SBalaji Rao PCF50633_INT5_HCLDOOVL = 0x80,
212f52046b1SBalaji Rao };
213f52046b1SBalaji Rao
214f52046b1SBalaji Rao /* misc. registers */
215f52046b1SBalaji Rao #define PCF50633_REG_OOCSHDWN 0x0c
216f52046b1SBalaji Rao
217f52046b1SBalaji Rao /* LED registers */
218f52046b1SBalaji Rao #define PCF50633_REG_LEDOUT 0x28
219f52046b1SBalaji Rao #define PCF50633_REG_LEDENA 0x29
220f52046b1SBalaji Rao #define PCF50633_REG_LEDCTL 0x2a
221f52046b1SBalaji Rao #define PCF50633_REG_LEDDIM 0x2b
222f52046b1SBalaji Rao
dev_to_pcf50633(struct device * dev)22368d641efSLars-Peter Clausen static inline struct pcf50633 *dev_to_pcf50633(struct device *dev)
22468d641efSLars-Peter Clausen {
22568d641efSLars-Peter Clausen return dev_get_drvdata(dev);
22668d641efSLars-Peter Clausen }
227f52046b1SBalaji Rao
228f337134fSMark Brown int pcf50633_irq_init(struct pcf50633 *pcf, int irq);
229f337134fSMark Brown void pcf50633_irq_free(struct pcf50633 *pcf);
230*245cb473SPaul Cercueil extern const struct dev_pm_ops pcf50633_pm;
231f337134fSMark Brown
23268d641efSLars-Peter Clausen #endif
233