1*2874c5fdSThomas Gleixner /* SPDX-License-Identifier: GPL-2.0-or-later */ 208c3e06aSBalaji Rao /* 308c3e06aSBalaji Rao * adc.h -- Driver for NXP PCF50633 ADC 408c3e06aSBalaji Rao * 508c3e06aSBalaji Rao * (C) 2006-2008 by Openmoko, Inc. 608c3e06aSBalaji Rao * All rights reserved. 708c3e06aSBalaji Rao */ 808c3e06aSBalaji Rao 908c3e06aSBalaji Rao #ifndef __LINUX_MFD_PCF50633_ADC_H 1008c3e06aSBalaji Rao #define __LINUX_MFD_PCF50633_ADC_H 1108c3e06aSBalaji Rao 1208c3e06aSBalaji Rao #include <linux/mfd/pcf50633/core.h> 1308c3e06aSBalaji Rao #include <linux/platform_device.h> 1408c3e06aSBalaji Rao 1508c3e06aSBalaji Rao /* ADC Registers */ 1608c3e06aSBalaji Rao #define PCF50633_REG_ADCC3 0x52 1708c3e06aSBalaji Rao #define PCF50633_REG_ADCC2 0x53 1808c3e06aSBalaji Rao #define PCF50633_REG_ADCC1 0x54 1908c3e06aSBalaji Rao #define PCF50633_REG_ADCS1 0x55 2008c3e06aSBalaji Rao #define PCF50633_REG_ADCS2 0x56 2108c3e06aSBalaji Rao #define PCF50633_REG_ADCS3 0x57 2208c3e06aSBalaji Rao 2308c3e06aSBalaji Rao #define PCF50633_ADCC1_ADCSTART 0x01 248d360d8cSPaul Fertser #define PCF50633_ADCC1_RES_8BIT 0x02 258d360d8cSPaul Fertser #define PCF50633_ADCC1_RES_10BIT 0x00 2608c3e06aSBalaji Rao #define PCF50633_ADCC1_AVERAGE_NO 0x00 2708c3e06aSBalaji Rao #define PCF50633_ADCC1_AVERAGE_4 0x04 2808c3e06aSBalaji Rao #define PCF50633_ADCC1_AVERAGE_8 0x08 2908c3e06aSBalaji Rao #define PCF50633_ADCC1_AVERAGE_16 0x0c 3008c3e06aSBalaji Rao #define PCF50633_ADCC1_MUX_BATSNS_RES 0x00 3108c3e06aSBalaji Rao #define PCF50633_ADCC1_MUX_BATSNS_SUBTR 0x10 3208c3e06aSBalaji Rao #define PCF50633_ADCC1_MUX_ADCIN2_RES 0x20 3308c3e06aSBalaji Rao #define PCF50633_ADCC1_MUX_ADCIN2_SUBTR 0x30 3408c3e06aSBalaji Rao #define PCF50633_ADCC1_MUX_BATTEMP 0x60 3508c3e06aSBalaji Rao #define PCF50633_ADCC1_MUX_ADCIN1 0x70 3608c3e06aSBalaji Rao #define PCF50633_ADCC1_AVERAGE_MASK 0x0c 3708c3e06aSBalaji Rao #define PCF50633_ADCC1_ADCMUX_MASK 0xf0 3808c3e06aSBalaji Rao 3908c3e06aSBalaji Rao #define PCF50633_ADCC2_RATIO_NONE 0x00 4008c3e06aSBalaji Rao #define PCF50633_ADCC2_RATIO_BATTEMP 0x01 4108c3e06aSBalaji Rao #define PCF50633_ADCC2_RATIO_ADCIN1 0x02 4208c3e06aSBalaji Rao #define PCF50633_ADCC2_RATIO_BOTH 0x03 4308c3e06aSBalaji Rao #define PCF50633_ADCC2_RATIOSETTL_100US 0x04 4408c3e06aSBalaji Rao 4508c3e06aSBalaji Rao #define PCF50633_ADCC3_ACCSW_EN 0x01 4608c3e06aSBalaji Rao #define PCF50633_ADCC3_NTCSW_EN 0x04 4708c3e06aSBalaji Rao #define PCF50633_ADCC3_RES_DIV_TWO 0x10 4808c3e06aSBalaji Rao #define PCF50633_ADCC3_RES_DIV_THREE 0x00 4908c3e06aSBalaji Rao 5008c3e06aSBalaji Rao #define PCF50633_ADCS3_REF_NTCSW 0x00 5108c3e06aSBalaji Rao #define PCF50633_ADCS3_REF_ACCSW 0x10 5208c3e06aSBalaji Rao #define PCF50633_ADCS3_REF_2V0 0x20 5308c3e06aSBalaji Rao #define PCF50633_ADCS3_REF_VISA 0x30 5408c3e06aSBalaji Rao #define PCF50633_ADCS3_REF_2V0_2 0x70 5508c3e06aSBalaji Rao #define PCF50633_ADCS3_ADCRDY 0x80 5608c3e06aSBalaji Rao 5708c3e06aSBalaji Rao #define PCF50633_ADCS3_ADCDAT1L_MASK 0x03 5808c3e06aSBalaji Rao #define PCF50633_ADCS3_ADCDAT2L_MASK 0x0c 5908c3e06aSBalaji Rao #define PCF50633_ADCS3_ADCDAT2L_SHIFT 2 6008c3e06aSBalaji Rao #define PCF50633_ASCS3_REF_MASK 0x70 6108c3e06aSBalaji Rao 6208c3e06aSBalaji Rao extern int 6308c3e06aSBalaji Rao pcf50633_adc_async_read(struct pcf50633 *pcf, int mux, int avg, 6408c3e06aSBalaji Rao void (*callback)(struct pcf50633 *, void *, int), 6508c3e06aSBalaji Rao void *callback_param); 6608c3e06aSBalaji Rao extern int 6708c3e06aSBalaji Rao pcf50633_adc_sync_read(struct pcf50633 *pcf, int mux, int avg); 6808c3e06aSBalaji Rao 6908c3e06aSBalaji Rao #endif /* __LINUX_PCF50633_ADC_H */ 70