1 /* SPDX-License-Identifier: GPL-2.0+ */ 2 /* 3 * Register Map - Based on PolarBear_CSRs.RevA.xlsx (2023-04-21) 4 * 5 * Copyright (C) 2023 Integrated Device Technology, Inc., a Renesas Company. 6 */ 7 #ifndef MFD_IDTRC38XXX_REG 8 #define MFD_IDTRC38XXX_REG 9 10 /* GLOBAL */ 11 #define SOFT_RESET_CTRL (0x15) /* Specific to FC3W */ 12 #define MISC_CTRL (0x14) /* Specific to FC3A */ 13 #define APLL_REINIT BIT(1) 14 #define APLL_REINIT_VFC3A BIT(2) 15 16 #define DEVICE_ID (0x2) 17 #define DEVICE_ID_MASK (0x1000) /* Bit 12 is 1 if FC3W and 0 if FC3A */ 18 #define DEVICE_ID_SHIFT (12) 19 20 /* FOD */ 21 #define FOD_0 (0x300) 22 #define FOD_0_VFC3A (0x400) 23 #define FOD_1 (0x340) 24 #define FOD_1_VFC3A (0x440) 25 #define FOD_2 (0x380) 26 #define FOD_2_VFC3A (0x480) 27 28 /* TDCAPLL */ 29 #define TDC_CTRL (0x44a) /* Specific to FC3W */ 30 #define TDC_ENABLE_CTRL (0x169) /* Specific to FC3A */ 31 #define TDC_DAC_CAL_CTRL (0x16a) /* Specific to FC3A */ 32 #define TDC_EN BIT(0) 33 #define TDC_DAC_RECAL_REQ BIT(1) 34 #define TDC_DAC_RECAL_REQ_VFC3A BIT(0) 35 36 #define TDC_FB_DIV_INT_CNFG (0x442) 37 #define TDC_FB_DIV_INT_CNFG_VFC3A (0x162) 38 #define TDC_FB_DIV_INT_MASK GENMASK(7, 0) 39 #define TDC_REF_DIV_CNFG (0x443) 40 #define TDC_REF_DIV_CNFG_VFC3A (0x163) 41 #define TDC_REF_DIV_CONFIG_MASK GENMASK(2, 0) 42 43 /* TIME SYNC CHANNEL */ 44 #define TIME_CLOCK_SRC (0xa01) /* Specific to FC3W */ 45 #define TIME_CLOCK_COUNT (0xa00) /* Specific to FC3W */ 46 #define TIME_CLOCK_COUNT_MASK GENMASK(5, 0) 47 48 #define SUB_SYNC_GEN_CNFG (0xa04) 49 50 #define TOD_COUNTER_READ_REQ (0xa5f) 51 #define TOD_COUNTER_READ_REQ_VFC3A (0x6df) 52 #define TOD_SYNC_LOAD_VAL_CTRL (0xa10) 53 #define TOD_SYNC_LOAD_VAL_CTRL_VFC3A (0x690) 54 #define SYNC_COUNTER_MASK GENMASK_ULL(51, 0) 55 #define SUB_SYNC_COUNTER_MASK GENMASK(30, 0) 56 #define TOD_SYNC_LOAD_REQ_CTRL (0xa21) 57 #define TOD_SYNC_LOAD_REQ_CTRL_VFC3A (0x6a1) 58 #define SYNC_LOAD_ENABLE BIT(1) 59 #define SUB_SYNC_LOAD_ENABLE BIT(0) 60 #define SYNC_LOAD_REQ BIT(0) 61 62 #define LPF_MODE_CNFG (0xa80) 63 #define LPF_MODE_CNFG_VFC3A (0x700) 64 enum lpf_mode { 65 LPF_DISABLED = 0, 66 LPF_WP = 1, 67 LPF_HOLDOVER = 2, 68 LPF_WF = 3, 69 LPF_INVALID = 4 70 }; 71 #define LPF_CTRL (0xa98) 72 #define LPF_CTRL_VFC3A (0x718) 73 #define LPF_EN BIT(0) 74 75 #define LPF_BW_CNFG (0xa81) 76 #define LPF_BW_SHIFT GENMASK(7, 3) 77 #define LPF_BW_MULT GENMASK(2, 0) 78 #define LPF_BW_SHIFT_DEFAULT (0xb) 79 #define LPF_BW_MULT_DEFAULT (0x0) 80 #define LPF_BW_SHIFT_1PPS (0x5) 81 82 #define LPF_WR_PHASE_CTRL (0xaa8) 83 #define LPF_WR_PHASE_CTRL_VFC3A (0x728) 84 #define LPF_WR_FREQ_CTRL (0xab0) 85 #define LPF_WR_FREQ_CTRL_VFC3A (0x730) 86 87 #define TIME_CLOCK_TDC_FANOUT_CNFG (0xB00) 88 #define TIME_SYNC_TO_TDC_EN BIT(0) 89 #define SIG1_MUX_SEL_MASK GENMASK(7, 4) 90 #define SIG2_MUX_SEL_MASK GENMASK(11, 8) 91 enum tdc_mux_sel { 92 REF0 = 0, 93 REF1 = 1, 94 REF2 = 2, 95 REF3 = 3, 96 REF_CLK5 = 4, 97 REF_CLK6 = 5, 98 DPLL_FB_TO_TDC = 6, 99 DPLL_FB_DIVIDED_TO_TDC = 7, 100 TIME_CLK_DIVIDED = 8, 101 TIME_SYNC = 9, 102 }; 103 104 #define TIME_CLOCK_MEAS_CNFG (0xB04) 105 #define TDC_MEAS_MODE BIT(0) 106 enum tdc_meas_mode { 107 CONTINUOUS = 0, 108 ONE_SHOT = 1, 109 MEAS_MODE_INVALID = 2, 110 }; 111 112 #define TIME_CLOCK_MEAS_DIV_CNFG (0xB08) 113 #define TIME_REF_DIV_MASK GENMASK(29, 24) 114 115 #define TIME_CLOCK_MEAS_CTRL (0xB10) 116 #define TDC_MEAS_EN BIT(0) 117 #define TDC_MEAS_START BIT(1) 118 119 #define TDC_FIFO_READ_REQ (0xB2F) 120 #define TDC_FIFO_READ (0xB30) 121 #define COARSE_MEAS_MASK GENMASK_ULL(39, 13) 122 #define FINE_MEAS_MASK GENMASK(12, 0) 123 124 #define TDC_FIFO_CTRL (0xB12) 125 #define FIFO_CLEAR BIT(0) 126 #define TDC_FIFO_STS (0xB38) 127 #define FIFO_FULL BIT(1) 128 #define FIFO_EMPTY BIT(0) 129 #define TDC_FIFO_EVENT (0xB39) 130 #define FIFO_OVERRUN BIT(1) 131 132 /* DPLL */ 133 #define MAX_REFERENCE_INDEX (3) 134 #define MAX_NUM_REF_PRIORITY (4) 135 136 #define MAX_DPLL_INDEX (2) 137 138 #define DPLL_STS (0x580) 139 #define DPLL_STS_VFC3A (0x571) 140 #define DPLL_STATE_STS_MASK (0x70) 141 #define DPLL_STATE_STS_SHIFT (4) 142 #define DPLL_REF_SEL_STS_MASK (0x6) 143 #define DPLL_REF_SEL_STS_SHIFT (1) 144 145 #define DPLL_REF_PRIORITY_CNFG (0x502) 146 #define DPLL_REFX_PRIORITY_DISABLE_MASK (0xf) 147 #define DPLL_REF0_PRIORITY_ENABLE_AND_SET_MASK (0x31) 148 #define DPLL_REF1_PRIORITY_ENABLE_AND_SET_MASK (0xc2) 149 #define DPLL_REF2_PRIORITY_ENABLE_AND_SET_MASK (0x304) 150 #define DPLL_REF3_PRIORITY_ENABLE_AND_SET_MASK (0xc08) 151 #define DPLL_REF0_PRIORITY_SHIFT (4) 152 #define DPLL_REF1_PRIORITY_SHIFT (6) 153 #define DPLL_REF2_PRIORITY_SHIFT (8) 154 #define DPLL_REF3_PRIORITY_SHIFT (10) 155 156 enum dpll_state { 157 DPLL_STATE_MIN = 0, 158 DPLL_STATE_FREERUN = DPLL_STATE_MIN, 159 DPLL_STATE_LOCKED = 1, 160 DPLL_STATE_HOLDOVER = 2, 161 DPLL_STATE_WRITE_FREQUENCY = 3, 162 DPLL_STATE_ACQUIRE = 4, 163 DPLL_STATE_HITLESS_SWITCH = 5, 164 DPLL_STATE_MAX = DPLL_STATE_HITLESS_SWITCH 165 }; 166 167 /* REFMON */ 168 #define LOSMON_STS_0 (0x81e) 169 #define LOSMON_STS_0_VFC3A (0x18e) 170 #define LOSMON_STS_1 (0x82e) 171 #define LOSMON_STS_1_VFC3A (0x19e) 172 #define LOSMON_STS_2 (0x83e) 173 #define LOSMON_STS_2_VFC3A (0x1ae) 174 #define LOSMON_STS_3 (0x84e) 175 #define LOSMON_STS_3_VFC3A (0x1be) 176 #define LOS_STS_MASK (0x1) 177 178 #define FREQMON_STS_0 (0x874) 179 #define FREQMON_STS_0_VFC3A (0x1d4) 180 #define FREQMON_STS_1 (0x894) 181 #define FREQMON_STS_1_VFC3A (0x1f4) 182 #define FREQMON_STS_2 (0x8b4) 183 #define FREQMON_STS_2_VFC3A (0x214) 184 #define FREQMON_STS_3 (0x8d4) 185 #define FREQMON_STS_3_VFC3A (0x234) 186 #define FREQ_FAIL_STS_SHIFT (31) 187 188 /* Firmware interface */ 189 #define TIME_CLK_FREQ_ADDR (0xffa0) 190 #define XTAL_FREQ_ADDR (0xffa1) 191 192 /* 193 * Return register address and field mask based on passed in firmware version 194 */ 195 #define IDTFC3_FW_REG(FW, VER, REG) (((FW) < (VER)) ? (REG) : (REG##_##VER)) 196 #define IDTFC3_FW_FIELD(FW, VER, FIELD) (((FW) < (VER)) ? (FIELD) : (FIELD##_##VER)) 197 enum fw_version { 198 V_DEFAULT = 0, 199 VFC3W = 1, 200 VFC3A = 2 201 }; 202 203 /* XTAL_FREQ_ADDR/TIME_CLK_FREQ_ADDR */ 204 enum { 205 FREQ_MIN = 0, 206 FREQ_25M = 1, 207 FREQ_49_152M = 2, 208 FREQ_50M = 3, 209 FREQ_100M = 4, 210 FREQ_125M = 5, 211 FREQ_250M = 6, 212 FREQ_MAX 213 }; 214 215 struct idtfc3_hw_param { 216 u32 xtal_freq; 217 u32 time_clk_freq; 218 }; 219 220 struct idtfc3_fwrc { 221 u8 hiaddr; 222 u8 loaddr; 223 u8 value; 224 u8 reserved; 225 } __packed; 226 227 static inline void idtfc3_default_hw_param(struct idtfc3_hw_param *hw_param) 228 { 229 hw_param->xtal_freq = 49152000; 230 hw_param->time_clk_freq = 25000000; 231 } 232 233 static inline int idtfc3_set_hw_param(struct idtfc3_hw_param *hw_param, 234 u16 addr, u8 val) 235 { 236 if (addr == XTAL_FREQ_ADDR) 237 switch (val) { 238 case FREQ_49_152M: 239 hw_param->xtal_freq = 49152000; 240 break; 241 case FREQ_50M: 242 hw_param->xtal_freq = 50000000; 243 break; 244 default: 245 return -EINVAL; 246 } 247 else if (addr == TIME_CLK_FREQ_ADDR) 248 switch (val) { 249 case FREQ_25M: 250 hw_param->time_clk_freq = 25000000; 251 break; 252 case FREQ_50M: 253 hw_param->time_clk_freq = 50000000; 254 break; 255 case FREQ_100M: 256 hw_param->time_clk_freq = 100000000; 257 break; 258 case FREQ_125M: 259 hw_param->time_clk_freq = 125000000; 260 break; 261 case FREQ_250M: 262 hw_param->time_clk_freq = 250000000; 263 break; 264 default: 265 return -EINVAL; 266 } 267 else 268 return -EFAULT; 269 270 return 0; 271 } 272 273 #endif 274