12874c5fdSThomas Gleixner /* SPDX-License-Identifier: GPL-2.0-or-later */ 290a38d99SGeert Uytterhoeven /* Copyright (C) 2012 Dialog Semiconductor Ltd. 32896434cSAshish Jangam */ 42896434cSAshish Jangam #ifndef __DA9055_PDATA_H 52896434cSAshish Jangam #define __DA9055_PDATA_H 62896434cSAshish Jangam 72896434cSAshish Jangam #define DA9055_MAX_REGULATORS 8 82896434cSAshish Jangam 92896434cSAshish Jangam struct da9055; 102896434cSAshish Jangam 112896434cSAshish Jangam enum gpio_select { 122896434cSAshish Jangam NO_GPIO = 0, 132896434cSAshish Jangam GPIO_1, 142896434cSAshish Jangam GPIO_2 152896434cSAshish Jangam }; 162896434cSAshish Jangam 172896434cSAshish Jangam struct da9055_pdata { 182896434cSAshish Jangam int (*init) (struct da9055 *da9055); 192896434cSAshish Jangam int irq_base; 202896434cSAshish Jangam int gpio_base; 212896434cSAshish Jangam 222896434cSAshish Jangam struct regulator_init_data *regulators[DA9055_MAX_REGULATORS]; 23f6130be6SAshish Jangam /* Enable RTC in RESET Mode */ 24f6130be6SAshish Jangam bool reset_enable; 25f6130be6SAshish Jangam /* 26f6130be6SAshish Jangam * Regulator mode control bits value (GPI offset) that 27*23ef2b64SRandy Dunlap * controls the regulator state, 0 if not available. 28f6130be6SAshish Jangam */ 29f6130be6SAshish Jangam enum gpio_select *reg_ren; 30f6130be6SAshish Jangam /* 31f6130be6SAshish Jangam * Regulator mode control bits value (GPI offset) that 32f6130be6SAshish Jangam * controls the regulator set A/B, 0 if not available. 33f6130be6SAshish Jangam */ 34f6130be6SAshish Jangam enum gpio_select *reg_rsel; 352896434cSAshish Jangam }; 362896434cSAshish Jangam #endif /* __DA9055_PDATA_H */ 37