1 /* 2 * Copyright (C) 2013, 2014 ARM Limited, All Rights Reserved. 3 * Author: Marc Zyngier <marc.zyngier@arm.com> 4 * 5 * 6 * This program is free software; you can redistribute it and/or modify 7 * it under the terms of the GNU General Public License version 2 as 8 * published by the Free Software Foundation. 9 * 10 * This program is distributed in the hope that it will be useful, 11 * but WITHOUT ANY WARRANTY; without even the implied warranty of 12 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 13 * GNU General Public License for more details. 14 * 15 * You should have received a copy of the GNU General Public License 16 * along with this program. If not, see <http://www.gnu.org/licenses/>. 17 */ 18 #ifndef __LINUX_IRQCHIP_ARM_GIC_V3_H 19 #define __LINUX_IRQCHIP_ARM_GIC_V3_H 20 21 /* 22 * Distributor registers. We assume we're running non-secure, with ARE 23 * being set. Secure-only and non-ARE registers are not described. 24 */ 25 #define GICD_CTLR 0x0000 26 #define GICD_TYPER 0x0004 27 #define GICD_IIDR 0x0008 28 #define GICD_STATUSR 0x0010 29 #define GICD_SETSPI_NSR 0x0040 30 #define GICD_CLRSPI_NSR 0x0048 31 #define GICD_SETSPI_SR 0x0050 32 #define GICD_CLRSPI_SR 0x0058 33 #define GICD_SEIR 0x0068 34 #define GICD_IGROUPR 0x0080 35 #define GICD_ISENABLER 0x0100 36 #define GICD_ICENABLER 0x0180 37 #define GICD_ISPENDR 0x0200 38 #define GICD_ICPENDR 0x0280 39 #define GICD_ISACTIVER 0x0300 40 #define GICD_ICACTIVER 0x0380 41 #define GICD_IPRIORITYR 0x0400 42 #define GICD_ICFGR 0x0C00 43 #define GICD_IGRPMODR 0x0D00 44 #define GICD_NSACR 0x0E00 45 #define GICD_IROUTER 0x6000 46 #define GICD_IDREGS 0xFFD0 47 #define GICD_PIDR2 0xFFE8 48 49 /* 50 * Those registers are actually from GICv2, but the spec demands that they 51 * are implemented as RES0 if ARE is 1 (which we do in KVM's emulated GICv3). 52 */ 53 #define GICD_ITARGETSR 0x0800 54 #define GICD_SGIR 0x0F00 55 #define GICD_CPENDSGIR 0x0F10 56 #define GICD_SPENDSGIR 0x0F20 57 58 #define GICD_CTLR_RWP (1U << 31) 59 #define GICD_CTLR_DS (1U << 6) 60 #define GICD_CTLR_ARE_NS (1U << 4) 61 #define GICD_CTLR_ENABLE_G1A (1U << 1) 62 #define GICD_CTLR_ENABLE_G1 (1U << 0) 63 64 /* 65 * In systems with a single security state (what we emulate in KVM) 66 * the meaning of the interrupt group enable bits is slightly different 67 */ 68 #define GICD_CTLR_ENABLE_SS_G1 (1U << 1) 69 #define GICD_CTLR_ENABLE_SS_G0 (1U << 0) 70 71 #define GICD_TYPER_LPIS (1U << 17) 72 #define GICD_TYPER_MBIS (1U << 16) 73 74 #define GICD_TYPER_ID_BITS(typer) ((((typer) >> 19) & 0x1f) + 1) 75 #define GICD_TYPER_IRQS(typer) ((((typer) & 0x1f) + 1) * 32) 76 #define GICD_TYPER_LPIS (1U << 17) 77 78 #define GICD_IROUTER_SPI_MODE_ONE (0U << 31) 79 #define GICD_IROUTER_SPI_MODE_ANY (1U << 31) 80 81 #define GIC_PIDR2_ARCH_MASK 0xf0 82 #define GIC_PIDR2_ARCH_GICv3 0x30 83 #define GIC_PIDR2_ARCH_GICv4 0x40 84 85 #define GIC_V3_DIST_SIZE 0x10000 86 87 /* 88 * Re-Distributor registers, offsets from RD_base 89 */ 90 #define GICR_CTLR GICD_CTLR 91 #define GICR_IIDR 0x0004 92 #define GICR_TYPER 0x0008 93 #define GICR_STATUSR GICD_STATUSR 94 #define GICR_WAKER 0x0014 95 #define GICR_SETLPIR 0x0040 96 #define GICR_CLRLPIR 0x0048 97 #define GICR_SEIR GICD_SEIR 98 #define GICR_PROPBASER 0x0070 99 #define GICR_PENDBASER 0x0078 100 #define GICR_INVLPIR 0x00A0 101 #define GICR_INVALLR 0x00B0 102 #define GICR_SYNCR 0x00C0 103 #define GICR_MOVLPIR 0x0100 104 #define GICR_MOVALLR 0x0110 105 #define GICR_ISACTIVER GICD_ISACTIVER 106 #define GICR_ICACTIVER GICD_ICACTIVER 107 #define GICR_IDREGS GICD_IDREGS 108 #define GICR_PIDR2 GICD_PIDR2 109 110 #define GICR_CTLR_ENABLE_LPIS (1UL << 0) 111 112 #define GICR_TYPER_CPU_NUMBER(r) (((r) >> 8) & 0xffff) 113 114 #define GICR_WAKER_ProcessorSleep (1U << 1) 115 #define GICR_WAKER_ChildrenAsleep (1U << 2) 116 117 #define GICR_PROPBASER_NonShareable (0U << 10) 118 #define GICR_PROPBASER_InnerShareable (1U << 10) 119 #define GICR_PROPBASER_OuterShareable (2U << 10) 120 #define GICR_PROPBASER_SHAREABILITY_MASK (3UL << 10) 121 #define GICR_PROPBASER_nCnB (0U << 7) 122 #define GICR_PROPBASER_nC (1U << 7) 123 #define GICR_PROPBASER_RaWt (2U << 7) 124 #define GICR_PROPBASER_RaWb (3U << 7) 125 #define GICR_PROPBASER_WaWt (4U << 7) 126 #define GICR_PROPBASER_WaWb (5U << 7) 127 #define GICR_PROPBASER_RaWaWt (6U << 7) 128 #define GICR_PROPBASER_RaWaWb (7U << 7) 129 #define GICR_PROPBASER_CACHEABILITY_MASK (7U << 7) 130 #define GICR_PROPBASER_IDBITS_MASK (0x1f) 131 132 #define GICR_PENDBASER_NonShareable (0U << 10) 133 #define GICR_PENDBASER_InnerShareable (1U << 10) 134 #define GICR_PENDBASER_OuterShareable (2U << 10) 135 #define GICR_PENDBASER_SHAREABILITY_MASK (3UL << 10) 136 #define GICR_PENDBASER_nCnB (0U << 7) 137 #define GICR_PENDBASER_nC (1U << 7) 138 #define GICR_PENDBASER_RaWt (2U << 7) 139 #define GICR_PENDBASER_RaWb (3U << 7) 140 #define GICR_PENDBASER_WaWt (4U << 7) 141 #define GICR_PENDBASER_WaWb (5U << 7) 142 #define GICR_PENDBASER_RaWaWt (6U << 7) 143 #define GICR_PENDBASER_RaWaWb (7U << 7) 144 #define GICR_PENDBASER_CACHEABILITY_MASK (7U << 7) 145 146 /* 147 * Re-Distributor registers, offsets from SGI_base 148 */ 149 #define GICR_IGROUPR0 GICD_IGROUPR 150 #define GICR_ISENABLER0 GICD_ISENABLER 151 #define GICR_ICENABLER0 GICD_ICENABLER 152 #define GICR_ISPENDR0 GICD_ISPENDR 153 #define GICR_ICPENDR0 GICD_ICPENDR 154 #define GICR_ISACTIVER0 GICD_ISACTIVER 155 #define GICR_ICACTIVER0 GICD_ICACTIVER 156 #define GICR_IPRIORITYR0 GICD_IPRIORITYR 157 #define GICR_ICFGR0 GICD_ICFGR 158 #define GICR_IGRPMODR0 GICD_IGRPMODR 159 #define GICR_NSACR GICD_NSACR 160 161 #define GICR_TYPER_PLPIS (1U << 0) 162 #define GICR_TYPER_VLPIS (1U << 1) 163 #define GICR_TYPER_LAST (1U << 4) 164 165 #define GIC_V3_REDIST_SIZE 0x20000 166 167 #define LPI_PROP_GROUP1 (1 << 1) 168 #define LPI_PROP_ENABLED (1 << 0) 169 170 /* 171 * ITS registers, offsets from ITS_base 172 */ 173 #define GITS_CTLR 0x0000 174 #define GITS_IIDR 0x0004 175 #define GITS_TYPER 0x0008 176 #define GITS_CBASER 0x0080 177 #define GITS_CWRITER 0x0088 178 #define GITS_CREADR 0x0090 179 #define GITS_BASER 0x0100 180 #define GITS_PIDR2 GICR_PIDR2 181 182 #define GITS_TRANSLATER 0x10040 183 184 #define GITS_CTLR_ENABLE (1U << 0) 185 #define GITS_CTLR_QUIESCENT (1U << 31) 186 187 #define GITS_TYPER_DEVBITS_SHIFT 13 188 #define GITS_TYPER_DEVBITS(r) ((((r) >> GITS_TYPER_DEVBITS_SHIFT) & 0x1f) + 1) 189 #define GITS_TYPER_PTA (1UL << 19) 190 191 #define GITS_CBASER_VALID (1UL << 63) 192 #define GITS_CBASER_nCnB (0UL << 59) 193 #define GITS_CBASER_nC (1UL << 59) 194 #define GITS_CBASER_RaWt (2UL << 59) 195 #define GITS_CBASER_RaWb (3UL << 59) 196 #define GITS_CBASER_WaWt (4UL << 59) 197 #define GITS_CBASER_WaWb (5UL << 59) 198 #define GITS_CBASER_RaWaWt (6UL << 59) 199 #define GITS_CBASER_RaWaWb (7UL << 59) 200 #define GITS_CBASER_CACHEABILITY_MASK (7UL << 59) 201 #define GITS_CBASER_NonShareable (0UL << 10) 202 #define GITS_CBASER_InnerShareable (1UL << 10) 203 #define GITS_CBASER_OuterShareable (2UL << 10) 204 #define GITS_CBASER_SHAREABILITY_MASK (3UL << 10) 205 206 #define GITS_BASER_NR_REGS 8 207 208 #define GITS_BASER_VALID (1UL << 63) 209 #define GITS_BASER_nCnB (0UL << 59) 210 #define GITS_BASER_nC (1UL << 59) 211 #define GITS_BASER_RaWt (2UL << 59) 212 #define GITS_BASER_RaWb (3UL << 59) 213 #define GITS_BASER_WaWt (4UL << 59) 214 #define GITS_BASER_WaWb (5UL << 59) 215 #define GITS_BASER_RaWaWt (6UL << 59) 216 #define GITS_BASER_RaWaWb (7UL << 59) 217 #define GITS_BASER_CACHEABILITY_MASK (7UL << 59) 218 #define GITS_BASER_TYPE_SHIFT (56) 219 #define GITS_BASER_TYPE(r) (((r) >> GITS_BASER_TYPE_SHIFT) & 7) 220 #define GITS_BASER_ENTRY_SIZE_SHIFT (48) 221 #define GITS_BASER_ENTRY_SIZE(r) ((((r) >> GITS_BASER_ENTRY_SIZE_SHIFT) & 0xff) + 1) 222 #define GITS_BASER_NonShareable (0UL << 10) 223 #define GITS_BASER_InnerShareable (1UL << 10) 224 #define GITS_BASER_OuterShareable (2UL << 10) 225 #define GITS_BASER_SHAREABILITY_SHIFT (10) 226 #define GITS_BASER_SHAREABILITY_MASK (3UL << GITS_BASER_SHAREABILITY_SHIFT) 227 #define GITS_BASER_PAGE_SIZE_SHIFT (8) 228 #define GITS_BASER_PAGE_SIZE_4K (0UL << GITS_BASER_PAGE_SIZE_SHIFT) 229 #define GITS_BASER_PAGE_SIZE_16K (1UL << GITS_BASER_PAGE_SIZE_SHIFT) 230 #define GITS_BASER_PAGE_SIZE_64K (2UL << GITS_BASER_PAGE_SIZE_SHIFT) 231 #define GITS_BASER_PAGE_SIZE_MASK (3UL << GITS_BASER_PAGE_SIZE_SHIFT) 232 #define GITS_BASER_PAGES_MAX 256 233 234 #define GITS_BASER_TYPE_NONE 0 235 #define GITS_BASER_TYPE_DEVICE 1 236 #define GITS_BASER_TYPE_VCPU 2 237 #define GITS_BASER_TYPE_CPU 3 238 #define GITS_BASER_TYPE_COLLECTION 4 239 #define GITS_BASER_TYPE_RESERVED5 5 240 #define GITS_BASER_TYPE_RESERVED6 6 241 #define GITS_BASER_TYPE_RESERVED7 7 242 243 /* 244 * ITS commands 245 */ 246 #define GITS_CMD_MAPD 0x08 247 #define GITS_CMD_MAPC 0x09 248 #define GITS_CMD_MAPVI 0x0a 249 #define GITS_CMD_MOVI 0x01 250 #define GITS_CMD_DISCARD 0x0f 251 #define GITS_CMD_INV 0x0c 252 #define GITS_CMD_MOVALL 0x0e 253 #define GITS_CMD_INVALL 0x0d 254 #define GITS_CMD_INT 0x03 255 #define GITS_CMD_CLEAR 0x04 256 #define GITS_CMD_SYNC 0x05 257 258 /* 259 * CPU interface registers 260 */ 261 #define ICC_CTLR_EL1_EOImode_drop_dir (0U << 1) 262 #define ICC_CTLR_EL1_EOImode_drop (1U << 1) 263 #define ICC_SRE_EL1_SRE (1U << 0) 264 265 /* 266 * Hypervisor interface registers (SRE only) 267 */ 268 #define ICH_LR_VIRTUAL_ID_MASK ((1ULL << 32) - 1) 269 270 #define ICH_LR_EOI (1ULL << 41) 271 #define ICH_LR_GROUP (1ULL << 60) 272 #define ICH_LR_HW (1ULL << 61) 273 #define ICH_LR_STATE (3ULL << 62) 274 #define ICH_LR_PENDING_BIT (1ULL << 62) 275 #define ICH_LR_ACTIVE_BIT (1ULL << 63) 276 #define ICH_LR_PHYS_ID_SHIFT 32 277 #define ICH_LR_PHYS_ID_MASK (0x3ffULL << ICH_LR_PHYS_ID_SHIFT) 278 279 #define ICH_MISR_EOI (1 << 0) 280 #define ICH_MISR_U (1 << 1) 281 282 #define ICH_HCR_EN (1 << 0) 283 #define ICH_HCR_UIE (1 << 1) 284 285 #define ICH_VMCR_CTLR_SHIFT 0 286 #define ICH_VMCR_CTLR_MASK (0x21f << ICH_VMCR_CTLR_SHIFT) 287 #define ICH_VMCR_BPR1_SHIFT 18 288 #define ICH_VMCR_BPR1_MASK (7 << ICH_VMCR_BPR1_SHIFT) 289 #define ICH_VMCR_BPR0_SHIFT 21 290 #define ICH_VMCR_BPR0_MASK (7 << ICH_VMCR_BPR0_SHIFT) 291 #define ICH_VMCR_PMR_SHIFT 24 292 #define ICH_VMCR_PMR_MASK (0xffUL << ICH_VMCR_PMR_SHIFT) 293 294 #define ICC_IAR1_EL1_SPURIOUS 0x3ff 295 296 #define ICC_SRE_EL2_SRE (1 << 0) 297 #define ICC_SRE_EL2_ENABLE (1 << 3) 298 299 #define ICC_SGI1R_TARGET_LIST_SHIFT 0 300 #define ICC_SGI1R_TARGET_LIST_MASK (0xffff << ICC_SGI1R_TARGET_LIST_SHIFT) 301 #define ICC_SGI1R_AFFINITY_1_SHIFT 16 302 #define ICC_SGI1R_AFFINITY_1_MASK (0xff << ICC_SGI1R_AFFINITY_1_SHIFT) 303 #define ICC_SGI1R_SGI_ID_SHIFT 24 304 #define ICC_SGI1R_SGI_ID_MASK (0xff << ICC_SGI1R_SGI_ID_SHIFT) 305 #define ICC_SGI1R_AFFINITY_2_SHIFT 32 306 #define ICC_SGI1R_AFFINITY_2_MASK (0xffULL << ICC_SGI1R_AFFINITY_1_SHIFT) 307 #define ICC_SGI1R_IRQ_ROUTING_MODE_BIT 40 308 #define ICC_SGI1R_AFFINITY_3_SHIFT 48 309 #define ICC_SGI1R_AFFINITY_3_MASK (0xffULL << ICC_SGI1R_AFFINITY_1_SHIFT) 310 311 #include <asm/arch_gicv3.h> 312 313 #ifndef __ASSEMBLY__ 314 315 /* 316 * We need a value to serve as a irq-type for LPIs. Choose one that will 317 * hopefully pique the interest of the reviewer. 318 */ 319 #define GIC_IRQ_TYPE_LPI 0xa110c8ed 320 321 struct rdists { 322 struct { 323 void __iomem *rd_base; 324 struct page *pend_page; 325 phys_addr_t phys_base; 326 } __percpu *rdist; 327 struct page *prop_page; 328 int id_bits; 329 u64 flags; 330 }; 331 332 struct irq_domain; 333 struct device_node; 334 int its_cpu_init(void); 335 int its_init(struct device_node *node, struct rdists *rdists, 336 struct irq_domain *domain); 337 338 static inline bool gic_enable_sre(void) 339 { 340 u32 val; 341 342 val = gic_read_sre(); 343 if (val & ICC_SRE_EL1_SRE) 344 return true; 345 346 val |= ICC_SRE_EL1_SRE; 347 gic_write_sre(val); 348 val = gic_read_sre(); 349 350 return !!(val & ICC_SRE_EL1_SRE); 351 } 352 353 #endif 354 355 #endif 356