1 /* SPDX-License-Identifier: GPL-2.0-only */ 2 /* 3 * Copyright (C) 2013, 2014 ARM Limited, All Rights Reserved. 4 * Author: Marc Zyngier <marc.zyngier@arm.com> 5 */ 6 #ifndef __LINUX_IRQCHIP_ARM_GIC_V3_H 7 #define __LINUX_IRQCHIP_ARM_GIC_V3_H 8 9 /* 10 * Distributor registers. We assume we're running non-secure, with ARE 11 * being set. Secure-only and non-ARE registers are not described. 12 */ 13 #define GICD_CTLR 0x0000 14 #define GICD_TYPER 0x0004 15 #define GICD_IIDR 0x0008 16 #define GICD_STATUSR 0x0010 17 #define GICD_SETSPI_NSR 0x0040 18 #define GICD_CLRSPI_NSR 0x0048 19 #define GICD_SETSPI_SR 0x0050 20 #define GICD_CLRSPI_SR 0x0058 21 #define GICD_SEIR 0x0068 22 #define GICD_IGROUPR 0x0080 23 #define GICD_ISENABLER 0x0100 24 #define GICD_ICENABLER 0x0180 25 #define GICD_ISPENDR 0x0200 26 #define GICD_ICPENDR 0x0280 27 #define GICD_ISACTIVER 0x0300 28 #define GICD_ICACTIVER 0x0380 29 #define GICD_IPRIORITYR 0x0400 30 #define GICD_ICFGR 0x0C00 31 #define GICD_IGRPMODR 0x0D00 32 #define GICD_NSACR 0x0E00 33 #define GICD_IGROUPRnE 0x1000 34 #define GICD_ISENABLERnE 0x1200 35 #define GICD_ICENABLERnE 0x1400 36 #define GICD_ISPENDRnE 0x1600 37 #define GICD_ICPENDRnE 0x1800 38 #define GICD_ISACTIVERnE 0x1A00 39 #define GICD_ICACTIVERnE 0x1C00 40 #define GICD_IPRIORITYRnE 0x2000 41 #define GICD_ICFGRnE 0x3000 42 #define GICD_IROUTER 0x6000 43 #define GICD_IROUTERnE 0x8000 44 #define GICD_IDREGS 0xFFD0 45 #define GICD_PIDR2 0xFFE8 46 47 #define ESPI_BASE_INTID 4096 48 49 /* 50 * Those registers are actually from GICv2, but the spec demands that they 51 * are implemented as RES0 if ARE is 1 (which we do in KVM's emulated GICv3). 52 */ 53 #define GICD_ITARGETSR 0x0800 54 #define GICD_SGIR 0x0F00 55 #define GICD_CPENDSGIR 0x0F10 56 #define GICD_SPENDSGIR 0x0F20 57 58 #define GICD_CTLR_RWP (1U << 31) 59 #define GICD_CTLR_DS (1U << 6) 60 #define GICD_CTLR_ARE_NS (1U << 4) 61 #define GICD_CTLR_ENABLE_G1A (1U << 1) 62 #define GICD_CTLR_ENABLE_G1 (1U << 0) 63 64 #define GICD_IIDR_IMPLEMENTER_SHIFT 0 65 #define GICD_IIDR_IMPLEMENTER_MASK (0xfff << GICD_IIDR_IMPLEMENTER_SHIFT) 66 #define GICD_IIDR_REVISION_SHIFT 12 67 #define GICD_IIDR_REVISION_MASK (0xf << GICD_IIDR_REVISION_SHIFT) 68 #define GICD_IIDR_VARIANT_SHIFT 16 69 #define GICD_IIDR_VARIANT_MASK (0xf << GICD_IIDR_VARIANT_SHIFT) 70 #define GICD_IIDR_PRODUCT_ID_SHIFT 24 71 #define GICD_IIDR_PRODUCT_ID_MASK (0xff << GICD_IIDR_PRODUCT_ID_SHIFT) 72 73 74 /* 75 * In systems with a single security state (what we emulate in KVM) 76 * the meaning of the interrupt group enable bits is slightly different 77 */ 78 #define GICD_CTLR_ENABLE_SS_G1 (1U << 1) 79 #define GICD_CTLR_ENABLE_SS_G0 (1U << 0) 80 81 #define GICD_TYPER_RSS (1U << 26) 82 #define GICD_TYPER_LPIS (1U << 17) 83 #define GICD_TYPER_MBIS (1U << 16) 84 #define GICD_TYPER_ESPI (1U << 8) 85 86 #define GICD_TYPER_ID_BITS(typer) ((((typer) >> 19) & 0x1f) + 1) 87 #define GICD_TYPER_NUM_LPIS(typer) ((((typer) >> 11) & 0x1f) + 1) 88 #define GICD_TYPER_SPIS(typer) ((((typer) & 0x1f) + 1) * 32) 89 #define GICD_TYPER_ESPIS(typer) \ 90 (((typer) & GICD_TYPER_ESPI) ? GICD_TYPER_SPIS((typer) >> 27) : 0) 91 92 #define GICD_IROUTER_SPI_MODE_ONE (0U << 31) 93 #define GICD_IROUTER_SPI_MODE_ANY (1U << 31) 94 95 #define GIC_PIDR2_ARCH_MASK 0xf0 96 #define GIC_PIDR2_ARCH_GICv3 0x30 97 #define GIC_PIDR2_ARCH_GICv4 0x40 98 99 #define GIC_V3_DIST_SIZE 0x10000 100 101 /* 102 * Re-Distributor registers, offsets from RD_base 103 */ 104 #define GICR_CTLR GICD_CTLR 105 #define GICR_IIDR 0x0004 106 #define GICR_TYPER 0x0008 107 #define GICR_STATUSR GICD_STATUSR 108 #define GICR_WAKER 0x0014 109 #define GICR_SETLPIR 0x0040 110 #define GICR_CLRLPIR 0x0048 111 #define GICR_SEIR GICD_SEIR 112 #define GICR_PROPBASER 0x0070 113 #define GICR_PENDBASER 0x0078 114 #define GICR_INVLPIR 0x00A0 115 #define GICR_INVALLR 0x00B0 116 #define GICR_SYNCR 0x00C0 117 #define GICR_MOVLPIR 0x0100 118 #define GICR_MOVALLR 0x0110 119 #define GICR_IDREGS GICD_IDREGS 120 #define GICR_PIDR2 GICD_PIDR2 121 122 #define GICR_CTLR_ENABLE_LPIS (1UL << 0) 123 #define GICR_CTLR_RWP (1UL << 3) 124 125 #define GICR_TYPER_CPU_NUMBER(r) (((r) >> 8) & 0xffff) 126 127 #define EPPI_BASE_INTID 1056 128 129 #define GICR_TYPER_NR_PPIS(r) \ 130 ({ \ 131 unsigned int __ppinum = ((r) >> 27) & 0x1f; \ 132 unsigned int __nr_ppis = 16; \ 133 if (__ppinum == 1 || __ppinum == 2) \ 134 __nr_ppis += __ppinum * 32; \ 135 \ 136 __nr_ppis; \ 137 }) 138 139 #define GICR_WAKER_ProcessorSleep (1U << 1) 140 #define GICR_WAKER_ChildrenAsleep (1U << 2) 141 142 #define GIC_BASER_CACHE_nCnB 0ULL 143 #define GIC_BASER_CACHE_SameAsInner 0ULL 144 #define GIC_BASER_CACHE_nC 1ULL 145 #define GIC_BASER_CACHE_RaWt 2ULL 146 #define GIC_BASER_CACHE_RaWb 3ULL 147 #define GIC_BASER_CACHE_WaWt 4ULL 148 #define GIC_BASER_CACHE_WaWb 5ULL 149 #define GIC_BASER_CACHE_RaWaWt 6ULL 150 #define GIC_BASER_CACHE_RaWaWb 7ULL 151 #define GIC_BASER_CACHE_MASK 7ULL 152 #define GIC_BASER_NonShareable 0ULL 153 #define GIC_BASER_InnerShareable 1ULL 154 #define GIC_BASER_OuterShareable 2ULL 155 #define GIC_BASER_SHAREABILITY_MASK 3ULL 156 157 #define GIC_BASER_CACHEABILITY(reg, inner_outer, type) \ 158 (GIC_BASER_CACHE_##type << reg##_##inner_outer##_CACHEABILITY_SHIFT) 159 160 #define GIC_BASER_SHAREABILITY(reg, type) \ 161 (GIC_BASER_##type << reg##_SHAREABILITY_SHIFT) 162 163 /* encode a size field of width @w containing @n - 1 units */ 164 #define GIC_ENCODE_SZ(n, w) (((unsigned long)(n) - 1) & GENMASK_ULL(((w) - 1), 0)) 165 166 #define GICR_PROPBASER_SHAREABILITY_SHIFT (10) 167 #define GICR_PROPBASER_INNER_CACHEABILITY_SHIFT (7) 168 #define GICR_PROPBASER_OUTER_CACHEABILITY_SHIFT (56) 169 #define GICR_PROPBASER_SHAREABILITY_MASK \ 170 GIC_BASER_SHAREABILITY(GICR_PROPBASER, SHAREABILITY_MASK) 171 #define GICR_PROPBASER_INNER_CACHEABILITY_MASK \ 172 GIC_BASER_CACHEABILITY(GICR_PROPBASER, INNER, MASK) 173 #define GICR_PROPBASER_OUTER_CACHEABILITY_MASK \ 174 GIC_BASER_CACHEABILITY(GICR_PROPBASER, OUTER, MASK) 175 #define GICR_PROPBASER_CACHEABILITY_MASK GICR_PROPBASER_INNER_CACHEABILITY_MASK 176 177 #define GICR_PROPBASER_InnerShareable \ 178 GIC_BASER_SHAREABILITY(GICR_PROPBASER, InnerShareable) 179 180 #define GICR_PROPBASER_nCnB GIC_BASER_CACHEABILITY(GICR_PROPBASER, INNER, nCnB) 181 #define GICR_PROPBASER_nC GIC_BASER_CACHEABILITY(GICR_PROPBASER, INNER, nC) 182 #define GICR_PROPBASER_RaWt GIC_BASER_CACHEABILITY(GICR_PROPBASER, INNER, RaWt) 183 #define GICR_PROPBASER_RaWb GIC_BASER_CACHEABILITY(GICR_PROPBASER, INNER, RaWb) 184 #define GICR_PROPBASER_WaWt GIC_BASER_CACHEABILITY(GICR_PROPBASER, INNER, WaWt) 185 #define GICR_PROPBASER_WaWb GIC_BASER_CACHEABILITY(GICR_PROPBASER, INNER, WaWb) 186 #define GICR_PROPBASER_RaWaWt GIC_BASER_CACHEABILITY(GICR_PROPBASER, INNER, RaWaWt) 187 #define GICR_PROPBASER_RaWaWb GIC_BASER_CACHEABILITY(GICR_PROPBASER, INNER, RaWaWb) 188 189 #define GICR_PROPBASER_IDBITS_MASK (0x1f) 190 #define GICR_PROPBASER_ADDRESS(x) ((x) & GENMASK_ULL(51, 12)) 191 #define GICR_PENDBASER_ADDRESS(x) ((x) & GENMASK_ULL(51, 16)) 192 193 #define GICR_PENDBASER_SHAREABILITY_SHIFT (10) 194 #define GICR_PENDBASER_INNER_CACHEABILITY_SHIFT (7) 195 #define GICR_PENDBASER_OUTER_CACHEABILITY_SHIFT (56) 196 #define GICR_PENDBASER_SHAREABILITY_MASK \ 197 GIC_BASER_SHAREABILITY(GICR_PENDBASER, SHAREABILITY_MASK) 198 #define GICR_PENDBASER_INNER_CACHEABILITY_MASK \ 199 GIC_BASER_CACHEABILITY(GICR_PENDBASER, INNER, MASK) 200 #define GICR_PENDBASER_OUTER_CACHEABILITY_MASK \ 201 GIC_BASER_CACHEABILITY(GICR_PENDBASER, OUTER, MASK) 202 #define GICR_PENDBASER_CACHEABILITY_MASK GICR_PENDBASER_INNER_CACHEABILITY_MASK 203 204 #define GICR_PENDBASER_InnerShareable \ 205 GIC_BASER_SHAREABILITY(GICR_PENDBASER, InnerShareable) 206 207 #define GICR_PENDBASER_nCnB GIC_BASER_CACHEABILITY(GICR_PENDBASER, INNER, nCnB) 208 #define GICR_PENDBASER_nC GIC_BASER_CACHEABILITY(GICR_PENDBASER, INNER, nC) 209 #define GICR_PENDBASER_RaWt GIC_BASER_CACHEABILITY(GICR_PENDBASER, INNER, RaWt) 210 #define GICR_PENDBASER_RaWb GIC_BASER_CACHEABILITY(GICR_PENDBASER, INNER, RaWb) 211 #define GICR_PENDBASER_WaWt GIC_BASER_CACHEABILITY(GICR_PENDBASER, INNER, WaWt) 212 #define GICR_PENDBASER_WaWb GIC_BASER_CACHEABILITY(GICR_PENDBASER, INNER, WaWb) 213 #define GICR_PENDBASER_RaWaWt GIC_BASER_CACHEABILITY(GICR_PENDBASER, INNER, RaWaWt) 214 #define GICR_PENDBASER_RaWaWb GIC_BASER_CACHEABILITY(GICR_PENDBASER, INNER, RaWaWb) 215 216 #define GICR_PENDBASER_PTZ BIT_ULL(62) 217 218 /* 219 * Re-Distributor registers, offsets from SGI_base 220 */ 221 #define GICR_IGROUPR0 GICD_IGROUPR 222 #define GICR_ISENABLER0 GICD_ISENABLER 223 #define GICR_ICENABLER0 GICD_ICENABLER 224 #define GICR_ISPENDR0 GICD_ISPENDR 225 #define GICR_ICPENDR0 GICD_ICPENDR 226 #define GICR_ISACTIVER0 GICD_ISACTIVER 227 #define GICR_ICACTIVER0 GICD_ICACTIVER 228 #define GICR_IPRIORITYR0 GICD_IPRIORITYR 229 #define GICR_ICFGR0 GICD_ICFGR 230 #define GICR_IGRPMODR0 GICD_IGRPMODR 231 #define GICR_NSACR GICD_NSACR 232 233 #define GICR_TYPER_PLPIS (1U << 0) 234 #define GICR_TYPER_VLPIS (1U << 1) 235 #define GICR_TYPER_DirectLPIS (1U << 3) 236 #define GICR_TYPER_LAST (1U << 4) 237 238 #define GIC_V3_REDIST_SIZE 0x20000 239 240 #define LPI_PROP_GROUP1 (1 << 1) 241 #define LPI_PROP_ENABLED (1 << 0) 242 243 /* 244 * Re-Distributor registers, offsets from VLPI_base 245 */ 246 #define GICR_VPROPBASER 0x0070 247 248 #define GICR_VPROPBASER_IDBITS_MASK 0x1f 249 250 #define GICR_VPROPBASER_SHAREABILITY_SHIFT (10) 251 #define GICR_VPROPBASER_INNER_CACHEABILITY_SHIFT (7) 252 #define GICR_VPROPBASER_OUTER_CACHEABILITY_SHIFT (56) 253 254 #define GICR_VPROPBASER_SHAREABILITY_MASK \ 255 GIC_BASER_SHAREABILITY(GICR_VPROPBASER, SHAREABILITY_MASK) 256 #define GICR_VPROPBASER_INNER_CACHEABILITY_MASK \ 257 GIC_BASER_CACHEABILITY(GICR_VPROPBASER, INNER, MASK) 258 #define GICR_VPROPBASER_OUTER_CACHEABILITY_MASK \ 259 GIC_BASER_CACHEABILITY(GICR_VPROPBASER, OUTER, MASK) 260 #define GICR_VPROPBASER_CACHEABILITY_MASK \ 261 GICR_VPROPBASER_INNER_CACHEABILITY_MASK 262 263 #define GICR_VPROPBASER_InnerShareable \ 264 GIC_BASER_SHAREABILITY(GICR_VPROPBASER, InnerShareable) 265 266 #define GICR_VPROPBASER_nCnB GIC_BASER_CACHEABILITY(GICR_VPROPBASER, INNER, nCnB) 267 #define GICR_VPROPBASER_nC GIC_BASER_CACHEABILITY(GICR_VPROPBASER, INNER, nC) 268 #define GICR_VPROPBASER_RaWt GIC_BASER_CACHEABILITY(GICR_VPROPBASER, INNER, RaWt) 269 #define GICR_VPROPBASER_RaWb GIC_BASER_CACHEABILITY(GICR_VPROPBASER, INNER, RaWb) 270 #define GICR_VPROPBASER_WaWt GIC_BASER_CACHEABILITY(GICR_VPROPBASER, INNER, WaWt) 271 #define GICR_VPROPBASER_WaWb GIC_BASER_CACHEABILITY(GICR_VPROPBASER, INNER, WaWb) 272 #define GICR_VPROPBASER_RaWaWt GIC_BASER_CACHEABILITY(GICR_VPROPBASER, INNER, RaWaWt) 273 #define GICR_VPROPBASER_RaWaWb GIC_BASER_CACHEABILITY(GICR_VPROPBASER, INNER, RaWaWb) 274 275 #define GICR_VPENDBASER 0x0078 276 277 #define GICR_VPENDBASER_SHAREABILITY_SHIFT (10) 278 #define GICR_VPENDBASER_INNER_CACHEABILITY_SHIFT (7) 279 #define GICR_VPENDBASER_OUTER_CACHEABILITY_SHIFT (56) 280 #define GICR_VPENDBASER_SHAREABILITY_MASK \ 281 GIC_BASER_SHAREABILITY(GICR_VPENDBASER, SHAREABILITY_MASK) 282 #define GICR_VPENDBASER_INNER_CACHEABILITY_MASK \ 283 GIC_BASER_CACHEABILITY(GICR_VPENDBASER, INNER, MASK) 284 #define GICR_VPENDBASER_OUTER_CACHEABILITY_MASK \ 285 GIC_BASER_CACHEABILITY(GICR_VPENDBASER, OUTER, MASK) 286 #define GICR_VPENDBASER_CACHEABILITY_MASK \ 287 GICR_VPENDBASER_INNER_CACHEABILITY_MASK 288 289 #define GICR_VPENDBASER_NonShareable \ 290 GIC_BASER_SHAREABILITY(GICR_VPENDBASER, NonShareable) 291 292 #define GICR_VPENDBASER_nCnB GIC_BASER_CACHEABILITY(GICR_VPENDBASER, INNER, nCnB) 293 #define GICR_VPENDBASER_nC GIC_BASER_CACHEABILITY(GICR_VPENDBASER, INNER, nC) 294 #define GICR_VPENDBASER_RaWt GIC_BASER_CACHEABILITY(GICR_VPENDBASER, INNER, RaWt) 295 #define GICR_VPENDBASER_RaWb GIC_BASER_CACHEABILITY(GICR_VPENDBASER, INNER, RaWb) 296 #define GICR_VPENDBASER_WaWt GIC_BASER_CACHEABILITY(GICR_VPENDBASER, INNER, WaWt) 297 #define GICR_VPENDBASER_WaWb GIC_BASER_CACHEABILITY(GICR_VPENDBASER, INNER, WaWb) 298 #define GICR_VPENDBASER_RaWaWt GIC_BASER_CACHEABILITY(GICR_VPENDBASER, INNER, RaWaWt) 299 #define GICR_VPENDBASER_RaWaWb GIC_BASER_CACHEABILITY(GICR_VPENDBASER, INNER, RaWaWb) 300 301 #define GICR_VPENDBASER_Dirty (1ULL << 60) 302 #define GICR_VPENDBASER_PendingLast (1ULL << 61) 303 #define GICR_VPENDBASER_IDAI (1ULL << 62) 304 #define GICR_VPENDBASER_Valid (1ULL << 63) 305 306 /* 307 * ITS registers, offsets from ITS_base 308 */ 309 #define GITS_CTLR 0x0000 310 #define GITS_IIDR 0x0004 311 #define GITS_TYPER 0x0008 312 #define GITS_CBASER 0x0080 313 #define GITS_CWRITER 0x0088 314 #define GITS_CREADR 0x0090 315 #define GITS_BASER 0x0100 316 #define GITS_IDREGS_BASE 0xffd0 317 #define GITS_PIDR0 0xffe0 318 #define GITS_PIDR1 0xffe4 319 #define GITS_PIDR2 GICR_PIDR2 320 #define GITS_PIDR4 0xffd0 321 #define GITS_CIDR0 0xfff0 322 #define GITS_CIDR1 0xfff4 323 #define GITS_CIDR2 0xfff8 324 #define GITS_CIDR3 0xfffc 325 326 #define GITS_TRANSLATER 0x10040 327 328 #define GITS_CTLR_ENABLE (1U << 0) 329 #define GITS_CTLR_ImDe (1U << 1) 330 #define GITS_CTLR_ITS_NUMBER_SHIFT 4 331 #define GITS_CTLR_ITS_NUMBER (0xFU << GITS_CTLR_ITS_NUMBER_SHIFT) 332 #define GITS_CTLR_QUIESCENT (1U << 31) 333 334 #define GITS_TYPER_PLPIS (1UL << 0) 335 #define GITS_TYPER_VLPIS (1UL << 1) 336 #define GITS_TYPER_ITT_ENTRY_SIZE_SHIFT 4 337 #define GITS_TYPER_ITT_ENTRY_SIZE(r) ((((r) >> GITS_TYPER_ITT_ENTRY_SIZE_SHIFT) & 0xf) + 1) 338 #define GITS_TYPER_IDBITS_SHIFT 8 339 #define GITS_TYPER_DEVBITS_SHIFT 13 340 #define GITS_TYPER_DEVBITS(r) ((((r) >> GITS_TYPER_DEVBITS_SHIFT) & 0x1f) + 1) 341 #define GITS_TYPER_PTA (1UL << 19) 342 #define GITS_TYPER_HCC_SHIFT 24 343 #define GITS_TYPER_HCC(r) (((r) >> GITS_TYPER_HCC_SHIFT) & 0xff) 344 #define GITS_TYPER_VMOVP (1ULL << 37) 345 346 #define GITS_IIDR_REV_SHIFT 12 347 #define GITS_IIDR_REV_MASK (0xf << GITS_IIDR_REV_SHIFT) 348 #define GITS_IIDR_REV(r) (((r) >> GITS_IIDR_REV_SHIFT) & 0xf) 349 #define GITS_IIDR_PRODUCTID_SHIFT 24 350 351 #define GITS_CBASER_VALID (1ULL << 63) 352 #define GITS_CBASER_SHAREABILITY_SHIFT (10) 353 #define GITS_CBASER_INNER_CACHEABILITY_SHIFT (59) 354 #define GITS_CBASER_OUTER_CACHEABILITY_SHIFT (53) 355 #define GITS_CBASER_SHAREABILITY_MASK \ 356 GIC_BASER_SHAREABILITY(GITS_CBASER, SHAREABILITY_MASK) 357 #define GITS_CBASER_INNER_CACHEABILITY_MASK \ 358 GIC_BASER_CACHEABILITY(GITS_CBASER, INNER, MASK) 359 #define GITS_CBASER_OUTER_CACHEABILITY_MASK \ 360 GIC_BASER_CACHEABILITY(GITS_CBASER, OUTER, MASK) 361 #define GITS_CBASER_CACHEABILITY_MASK GITS_CBASER_INNER_CACHEABILITY_MASK 362 363 #define GITS_CBASER_InnerShareable \ 364 GIC_BASER_SHAREABILITY(GITS_CBASER, InnerShareable) 365 366 #define GITS_CBASER_nCnB GIC_BASER_CACHEABILITY(GITS_CBASER, INNER, nCnB) 367 #define GITS_CBASER_nC GIC_BASER_CACHEABILITY(GITS_CBASER, INNER, nC) 368 #define GITS_CBASER_RaWt GIC_BASER_CACHEABILITY(GITS_CBASER, INNER, RaWt) 369 #define GITS_CBASER_RaWb GIC_BASER_CACHEABILITY(GITS_CBASER, INNER, RaWb) 370 #define GITS_CBASER_WaWt GIC_BASER_CACHEABILITY(GITS_CBASER, INNER, WaWt) 371 #define GITS_CBASER_WaWb GIC_BASER_CACHEABILITY(GITS_CBASER, INNER, WaWb) 372 #define GITS_CBASER_RaWaWt GIC_BASER_CACHEABILITY(GITS_CBASER, INNER, RaWaWt) 373 #define GITS_CBASER_RaWaWb GIC_BASER_CACHEABILITY(GITS_CBASER, INNER, RaWaWb) 374 375 #define GITS_CBASER_ADDRESS(cbaser) ((cbaser) & GENMASK_ULL(51, 12)) 376 377 #define GITS_BASER_NR_REGS 8 378 379 #define GITS_BASER_VALID (1ULL << 63) 380 #define GITS_BASER_INDIRECT (1ULL << 62) 381 382 #define GITS_BASER_INNER_CACHEABILITY_SHIFT (59) 383 #define GITS_BASER_OUTER_CACHEABILITY_SHIFT (53) 384 #define GITS_BASER_INNER_CACHEABILITY_MASK \ 385 GIC_BASER_CACHEABILITY(GITS_BASER, INNER, MASK) 386 #define GITS_BASER_CACHEABILITY_MASK GITS_BASER_INNER_CACHEABILITY_MASK 387 #define GITS_BASER_OUTER_CACHEABILITY_MASK \ 388 GIC_BASER_CACHEABILITY(GITS_BASER, OUTER, MASK) 389 #define GITS_BASER_SHAREABILITY_MASK \ 390 GIC_BASER_SHAREABILITY(GITS_BASER, SHAREABILITY_MASK) 391 392 #define GITS_BASER_nCnB GIC_BASER_CACHEABILITY(GITS_BASER, INNER, nCnB) 393 #define GITS_BASER_nC GIC_BASER_CACHEABILITY(GITS_BASER, INNER, nC) 394 #define GITS_BASER_RaWt GIC_BASER_CACHEABILITY(GITS_BASER, INNER, RaWt) 395 #define GITS_BASER_RaWb GIC_BASER_CACHEABILITY(GITS_BASER, INNER, RaWb) 396 #define GITS_BASER_WaWt GIC_BASER_CACHEABILITY(GITS_BASER, INNER, WaWt) 397 #define GITS_BASER_WaWb GIC_BASER_CACHEABILITY(GITS_BASER, INNER, WaWb) 398 #define GITS_BASER_RaWaWt GIC_BASER_CACHEABILITY(GITS_BASER, INNER, RaWaWt) 399 #define GITS_BASER_RaWaWb GIC_BASER_CACHEABILITY(GITS_BASER, INNER, RaWaWb) 400 401 #define GITS_BASER_TYPE_SHIFT (56) 402 #define GITS_BASER_TYPE(r) (((r) >> GITS_BASER_TYPE_SHIFT) & 7) 403 #define GITS_BASER_ENTRY_SIZE_SHIFT (48) 404 #define GITS_BASER_ENTRY_SIZE(r) ((((r) >> GITS_BASER_ENTRY_SIZE_SHIFT) & 0x1f) + 1) 405 #define GITS_BASER_ENTRY_SIZE_MASK GENMASK_ULL(52, 48) 406 #define GITS_BASER_PHYS_52_to_48(phys) \ 407 (((phys) & GENMASK_ULL(47, 16)) | (((phys) >> 48) & 0xf) << 12) 408 #define GITS_BASER_ADDR_48_to_52(baser) \ 409 (((baser) & GENMASK_ULL(47, 16)) | (((baser) >> 12) & 0xf) << 48) 410 411 #define GITS_BASER_SHAREABILITY_SHIFT (10) 412 #define GITS_BASER_InnerShareable \ 413 GIC_BASER_SHAREABILITY(GITS_BASER, InnerShareable) 414 #define GITS_BASER_PAGE_SIZE_SHIFT (8) 415 #define GITS_BASER_PAGE_SIZE_4K (0ULL << GITS_BASER_PAGE_SIZE_SHIFT) 416 #define GITS_BASER_PAGE_SIZE_16K (1ULL << GITS_BASER_PAGE_SIZE_SHIFT) 417 #define GITS_BASER_PAGE_SIZE_64K (2ULL << GITS_BASER_PAGE_SIZE_SHIFT) 418 #define GITS_BASER_PAGE_SIZE_MASK (3ULL << GITS_BASER_PAGE_SIZE_SHIFT) 419 #define GITS_BASER_PAGES_MAX 256 420 #define GITS_BASER_PAGES_SHIFT (0) 421 #define GITS_BASER_NR_PAGES(r) (((r) & 0xff) + 1) 422 423 #define GITS_BASER_TYPE_NONE 0 424 #define GITS_BASER_TYPE_DEVICE 1 425 #define GITS_BASER_TYPE_VCPU 2 426 #define GITS_BASER_TYPE_RESERVED3 3 427 #define GITS_BASER_TYPE_COLLECTION 4 428 #define GITS_BASER_TYPE_RESERVED5 5 429 #define GITS_BASER_TYPE_RESERVED6 6 430 #define GITS_BASER_TYPE_RESERVED7 7 431 432 #define GITS_LVL1_ENTRY_SIZE (8UL) 433 434 /* 435 * ITS commands 436 */ 437 #define GITS_CMD_MAPD 0x08 438 #define GITS_CMD_MAPC 0x09 439 #define GITS_CMD_MAPTI 0x0a 440 #define GITS_CMD_MAPI 0x0b 441 #define GITS_CMD_MOVI 0x01 442 #define GITS_CMD_DISCARD 0x0f 443 #define GITS_CMD_INV 0x0c 444 #define GITS_CMD_MOVALL 0x0e 445 #define GITS_CMD_INVALL 0x0d 446 #define GITS_CMD_INT 0x03 447 #define GITS_CMD_CLEAR 0x04 448 #define GITS_CMD_SYNC 0x05 449 450 /* 451 * GICv4 ITS specific commands 452 */ 453 #define GITS_CMD_GICv4(x) ((x) | 0x20) 454 #define GITS_CMD_VINVALL GITS_CMD_GICv4(GITS_CMD_INVALL) 455 #define GITS_CMD_VMAPP GITS_CMD_GICv4(GITS_CMD_MAPC) 456 #define GITS_CMD_VMAPTI GITS_CMD_GICv4(GITS_CMD_MAPTI) 457 #define GITS_CMD_VMOVI GITS_CMD_GICv4(GITS_CMD_MOVI) 458 #define GITS_CMD_VSYNC GITS_CMD_GICv4(GITS_CMD_SYNC) 459 /* VMOVP is the odd one, as it doesn't have a physical counterpart */ 460 #define GITS_CMD_VMOVP GITS_CMD_GICv4(2) 461 462 /* 463 * ITS error numbers 464 */ 465 #define E_ITS_MOVI_UNMAPPED_INTERRUPT 0x010107 466 #define E_ITS_MOVI_UNMAPPED_COLLECTION 0x010109 467 #define E_ITS_INT_UNMAPPED_INTERRUPT 0x010307 468 #define E_ITS_CLEAR_UNMAPPED_INTERRUPT 0x010507 469 #define E_ITS_MAPD_DEVICE_OOR 0x010801 470 #define E_ITS_MAPD_ITTSIZE_OOR 0x010802 471 #define E_ITS_MAPC_PROCNUM_OOR 0x010902 472 #define E_ITS_MAPC_COLLECTION_OOR 0x010903 473 #define E_ITS_MAPTI_UNMAPPED_DEVICE 0x010a04 474 #define E_ITS_MAPTI_ID_OOR 0x010a05 475 #define E_ITS_MAPTI_PHYSICALID_OOR 0x010a06 476 #define E_ITS_INV_UNMAPPED_INTERRUPT 0x010c07 477 #define E_ITS_INVALL_UNMAPPED_COLLECTION 0x010d09 478 #define E_ITS_MOVALL_PROCNUM_OOR 0x010e01 479 #define E_ITS_DISCARD_UNMAPPED_INTERRUPT 0x010f07 480 481 /* 482 * CPU interface registers 483 */ 484 #define ICC_CTLR_EL1_EOImode_SHIFT (1) 485 #define ICC_CTLR_EL1_EOImode_drop_dir (0U << ICC_CTLR_EL1_EOImode_SHIFT) 486 #define ICC_CTLR_EL1_EOImode_drop (1U << ICC_CTLR_EL1_EOImode_SHIFT) 487 #define ICC_CTLR_EL1_EOImode_MASK (1 << ICC_CTLR_EL1_EOImode_SHIFT) 488 #define ICC_CTLR_EL1_CBPR_SHIFT 0 489 #define ICC_CTLR_EL1_CBPR_MASK (1 << ICC_CTLR_EL1_CBPR_SHIFT) 490 #define ICC_CTLR_EL1_PRI_BITS_SHIFT 8 491 #define ICC_CTLR_EL1_PRI_BITS_MASK (0x7 << ICC_CTLR_EL1_PRI_BITS_SHIFT) 492 #define ICC_CTLR_EL1_ID_BITS_SHIFT 11 493 #define ICC_CTLR_EL1_ID_BITS_MASK (0x7 << ICC_CTLR_EL1_ID_BITS_SHIFT) 494 #define ICC_CTLR_EL1_SEIS_SHIFT 14 495 #define ICC_CTLR_EL1_SEIS_MASK (0x1 << ICC_CTLR_EL1_SEIS_SHIFT) 496 #define ICC_CTLR_EL1_A3V_SHIFT 15 497 #define ICC_CTLR_EL1_A3V_MASK (0x1 << ICC_CTLR_EL1_A3V_SHIFT) 498 #define ICC_CTLR_EL1_RSS (0x1 << 18) 499 #define ICC_CTLR_EL1_ExtRange (0x1 << 19) 500 #define ICC_PMR_EL1_SHIFT 0 501 #define ICC_PMR_EL1_MASK (0xff << ICC_PMR_EL1_SHIFT) 502 #define ICC_BPR0_EL1_SHIFT 0 503 #define ICC_BPR0_EL1_MASK (0x7 << ICC_BPR0_EL1_SHIFT) 504 #define ICC_BPR1_EL1_SHIFT 0 505 #define ICC_BPR1_EL1_MASK (0x7 << ICC_BPR1_EL1_SHIFT) 506 #define ICC_IGRPEN0_EL1_SHIFT 0 507 #define ICC_IGRPEN0_EL1_MASK (1 << ICC_IGRPEN0_EL1_SHIFT) 508 #define ICC_IGRPEN1_EL1_SHIFT 0 509 #define ICC_IGRPEN1_EL1_MASK (1 << ICC_IGRPEN1_EL1_SHIFT) 510 #define ICC_SRE_EL1_DIB (1U << 2) 511 #define ICC_SRE_EL1_DFB (1U << 1) 512 #define ICC_SRE_EL1_SRE (1U << 0) 513 514 /* 515 * Hypervisor interface registers (SRE only) 516 */ 517 #define ICH_LR_VIRTUAL_ID_MASK ((1ULL << 32) - 1) 518 519 #define ICH_LR_EOI (1ULL << 41) 520 #define ICH_LR_GROUP (1ULL << 60) 521 #define ICH_LR_HW (1ULL << 61) 522 #define ICH_LR_STATE (3ULL << 62) 523 #define ICH_LR_PENDING_BIT (1ULL << 62) 524 #define ICH_LR_ACTIVE_BIT (1ULL << 63) 525 #define ICH_LR_PHYS_ID_SHIFT 32 526 #define ICH_LR_PHYS_ID_MASK (0x3ffULL << ICH_LR_PHYS_ID_SHIFT) 527 #define ICH_LR_PRIORITY_SHIFT 48 528 #define ICH_LR_PRIORITY_MASK (0xffULL << ICH_LR_PRIORITY_SHIFT) 529 530 /* These are for GICv2 emulation only */ 531 #define GICH_LR_VIRTUALID (0x3ffUL << 0) 532 #define GICH_LR_PHYSID_CPUID_SHIFT (10) 533 #define GICH_LR_PHYSID_CPUID (7UL << GICH_LR_PHYSID_CPUID_SHIFT) 534 535 #define ICH_MISR_EOI (1 << 0) 536 #define ICH_MISR_U (1 << 1) 537 538 #define ICH_HCR_EN (1 << 0) 539 #define ICH_HCR_UIE (1 << 1) 540 #define ICH_HCR_NPIE (1 << 3) 541 #define ICH_HCR_TC (1 << 10) 542 #define ICH_HCR_TALL0 (1 << 11) 543 #define ICH_HCR_TALL1 (1 << 12) 544 #define ICH_HCR_EOIcount_SHIFT 27 545 #define ICH_HCR_EOIcount_MASK (0x1f << ICH_HCR_EOIcount_SHIFT) 546 547 #define ICH_VMCR_ACK_CTL_SHIFT 2 548 #define ICH_VMCR_ACK_CTL_MASK (1 << ICH_VMCR_ACK_CTL_SHIFT) 549 #define ICH_VMCR_FIQ_EN_SHIFT 3 550 #define ICH_VMCR_FIQ_EN_MASK (1 << ICH_VMCR_FIQ_EN_SHIFT) 551 #define ICH_VMCR_CBPR_SHIFT 4 552 #define ICH_VMCR_CBPR_MASK (1 << ICH_VMCR_CBPR_SHIFT) 553 #define ICH_VMCR_EOIM_SHIFT 9 554 #define ICH_VMCR_EOIM_MASK (1 << ICH_VMCR_EOIM_SHIFT) 555 #define ICH_VMCR_BPR1_SHIFT 18 556 #define ICH_VMCR_BPR1_MASK (7 << ICH_VMCR_BPR1_SHIFT) 557 #define ICH_VMCR_BPR0_SHIFT 21 558 #define ICH_VMCR_BPR0_MASK (7 << ICH_VMCR_BPR0_SHIFT) 559 #define ICH_VMCR_PMR_SHIFT 24 560 #define ICH_VMCR_PMR_MASK (0xffUL << ICH_VMCR_PMR_SHIFT) 561 #define ICH_VMCR_ENG0_SHIFT 0 562 #define ICH_VMCR_ENG0_MASK (1 << ICH_VMCR_ENG0_SHIFT) 563 #define ICH_VMCR_ENG1_SHIFT 1 564 #define ICH_VMCR_ENG1_MASK (1 << ICH_VMCR_ENG1_SHIFT) 565 566 #define ICH_VTR_PRI_BITS_SHIFT 29 567 #define ICH_VTR_PRI_BITS_MASK (7 << ICH_VTR_PRI_BITS_SHIFT) 568 #define ICH_VTR_ID_BITS_SHIFT 23 569 #define ICH_VTR_ID_BITS_MASK (7 << ICH_VTR_ID_BITS_SHIFT) 570 #define ICH_VTR_SEIS_SHIFT 22 571 #define ICH_VTR_SEIS_MASK (1 << ICH_VTR_SEIS_SHIFT) 572 #define ICH_VTR_A3V_SHIFT 21 573 #define ICH_VTR_A3V_MASK (1 << ICH_VTR_A3V_SHIFT) 574 575 #define ICC_IAR1_EL1_SPURIOUS 0x3ff 576 577 #define ICC_SRE_EL2_SRE (1 << 0) 578 #define ICC_SRE_EL2_ENABLE (1 << 3) 579 580 #define ICC_SGI1R_TARGET_LIST_SHIFT 0 581 #define ICC_SGI1R_TARGET_LIST_MASK (0xffff << ICC_SGI1R_TARGET_LIST_SHIFT) 582 #define ICC_SGI1R_AFFINITY_1_SHIFT 16 583 #define ICC_SGI1R_AFFINITY_1_MASK (0xff << ICC_SGI1R_AFFINITY_1_SHIFT) 584 #define ICC_SGI1R_SGI_ID_SHIFT 24 585 #define ICC_SGI1R_SGI_ID_MASK (0xfULL << ICC_SGI1R_SGI_ID_SHIFT) 586 #define ICC_SGI1R_AFFINITY_2_SHIFT 32 587 #define ICC_SGI1R_AFFINITY_2_MASK (0xffULL << ICC_SGI1R_AFFINITY_2_SHIFT) 588 #define ICC_SGI1R_IRQ_ROUTING_MODE_BIT 40 589 #define ICC_SGI1R_RS_SHIFT 44 590 #define ICC_SGI1R_RS_MASK (0xfULL << ICC_SGI1R_RS_SHIFT) 591 #define ICC_SGI1R_AFFINITY_3_SHIFT 48 592 #define ICC_SGI1R_AFFINITY_3_MASK (0xffULL << ICC_SGI1R_AFFINITY_3_SHIFT) 593 594 #include <asm/arch_gicv3.h> 595 596 #ifndef __ASSEMBLY__ 597 598 /* 599 * We need a value to serve as a irq-type for LPIs. Choose one that will 600 * hopefully pique the interest of the reviewer. 601 */ 602 #define GIC_IRQ_TYPE_LPI 0xa110c8ed 603 604 struct rdists { 605 struct { 606 void __iomem *rd_base; 607 struct page *pend_page; 608 phys_addr_t phys_base; 609 bool lpi_enabled; 610 } __percpu *rdist; 611 phys_addr_t prop_table_pa; 612 void *prop_table_va; 613 u64 flags; 614 u32 gicd_typer; 615 bool has_vlpis; 616 bool has_direct_lpi; 617 }; 618 619 struct irq_domain; 620 struct fwnode_handle; 621 int its_cpu_init(void); 622 int its_init(struct fwnode_handle *handle, struct rdists *rdists, 623 struct irq_domain *domain); 624 int mbi_init(struct fwnode_handle *fwnode, struct irq_domain *parent); 625 626 static inline bool gic_enable_sre(void) 627 { 628 u32 val; 629 630 val = gic_read_sre(); 631 if (val & ICC_SRE_EL1_SRE) 632 return true; 633 634 val |= ICC_SRE_EL1_SRE; 635 gic_write_sre(val); 636 val = gic_read_sre(); 637 638 return !!(val & ICC_SRE_EL1_SRE); 639 } 640 641 #endif 642 643 #endif 644