1 /* SPDX-License-Identifier: GPL-2.0-only */ 2 /* 3 * Copyright (C) 2013, 2014 ARM Limited, All Rights Reserved. 4 * Author: Marc Zyngier <marc.zyngier@arm.com> 5 */ 6 #ifndef __LINUX_IRQCHIP_ARM_GIC_V3_H 7 #define __LINUX_IRQCHIP_ARM_GIC_V3_H 8 9 /* 10 * Distributor registers. We assume we're running non-secure, with ARE 11 * being set. Secure-only and non-ARE registers are not described. 12 */ 13 #define GICD_CTLR 0x0000 14 #define GICD_TYPER 0x0004 15 #define GICD_IIDR 0x0008 16 #define GICD_TYPER2 0x000C 17 #define GICD_STATUSR 0x0010 18 #define GICD_SETSPI_NSR 0x0040 19 #define GICD_CLRSPI_NSR 0x0048 20 #define GICD_SETSPI_SR 0x0050 21 #define GICD_CLRSPI_SR 0x0058 22 #define GICD_SEIR 0x0068 23 #define GICD_IGROUPR 0x0080 24 #define GICD_ISENABLER 0x0100 25 #define GICD_ICENABLER 0x0180 26 #define GICD_ISPENDR 0x0200 27 #define GICD_ICPENDR 0x0280 28 #define GICD_ISACTIVER 0x0300 29 #define GICD_ICACTIVER 0x0380 30 #define GICD_IPRIORITYR 0x0400 31 #define GICD_ICFGR 0x0C00 32 #define GICD_IGRPMODR 0x0D00 33 #define GICD_NSACR 0x0E00 34 #define GICD_IGROUPRnE 0x1000 35 #define GICD_ISENABLERnE 0x1200 36 #define GICD_ICENABLERnE 0x1400 37 #define GICD_ISPENDRnE 0x1600 38 #define GICD_ICPENDRnE 0x1800 39 #define GICD_ISACTIVERnE 0x1A00 40 #define GICD_ICACTIVERnE 0x1C00 41 #define GICD_IPRIORITYRnE 0x2000 42 #define GICD_ICFGRnE 0x3000 43 #define GICD_IROUTER 0x6000 44 #define GICD_IROUTERnE 0x8000 45 #define GICD_IDREGS 0xFFD0 46 #define GICD_PIDR2 0xFFE8 47 48 #define ESPI_BASE_INTID 4096 49 50 /* 51 * Those registers are actually from GICv2, but the spec demands that they 52 * are implemented as RES0 if ARE is 1 (which we do in KVM's emulated GICv3). 53 */ 54 #define GICD_ITARGETSR 0x0800 55 #define GICD_SGIR 0x0F00 56 #define GICD_CPENDSGIR 0x0F10 57 #define GICD_SPENDSGIR 0x0F20 58 59 #define GICD_CTLR_RWP (1U << 31) 60 #define GICD_CTLR_DS (1U << 6) 61 #define GICD_CTLR_ARE_NS (1U << 4) 62 #define GICD_CTLR_ENABLE_G1A (1U << 1) 63 #define GICD_CTLR_ENABLE_G1 (1U << 0) 64 65 #define GICD_IIDR_IMPLEMENTER_SHIFT 0 66 #define GICD_IIDR_IMPLEMENTER_MASK (0xfff << GICD_IIDR_IMPLEMENTER_SHIFT) 67 #define GICD_IIDR_REVISION_SHIFT 12 68 #define GICD_IIDR_REVISION_MASK (0xf << GICD_IIDR_REVISION_SHIFT) 69 #define GICD_IIDR_VARIANT_SHIFT 16 70 #define GICD_IIDR_VARIANT_MASK (0xf << GICD_IIDR_VARIANT_SHIFT) 71 #define GICD_IIDR_PRODUCT_ID_SHIFT 24 72 #define GICD_IIDR_PRODUCT_ID_MASK (0xff << GICD_IIDR_PRODUCT_ID_SHIFT) 73 74 75 /* 76 * In systems with a single security state (what we emulate in KVM) 77 * the meaning of the interrupt group enable bits is slightly different 78 */ 79 #define GICD_CTLR_ENABLE_SS_G1 (1U << 1) 80 #define GICD_CTLR_ENABLE_SS_G0 (1U << 0) 81 82 #define GICD_TYPER_RSS (1U << 26) 83 #define GICD_TYPER_LPIS (1U << 17) 84 #define GICD_TYPER_MBIS (1U << 16) 85 #define GICD_TYPER_ESPI (1U << 8) 86 87 #define GICD_TYPER_ID_BITS(typer) ((((typer) >> 19) & 0x1f) + 1) 88 #define GICD_TYPER_NUM_LPIS(typer) ((((typer) >> 11) & 0x1f) + 1) 89 #define GICD_TYPER_SPIS(typer) ((((typer) & 0x1f) + 1) * 32) 90 #define GICD_TYPER_ESPIS(typer) \ 91 (((typer) & GICD_TYPER_ESPI) ? GICD_TYPER_SPIS((typer) >> 27) : 0) 92 93 #define GICD_TYPER2_VIL (1U << 7) 94 #define GICD_TYPER2_VID GENMASK(4, 0) 95 96 #define GICD_IROUTER_SPI_MODE_ONE (0U << 31) 97 #define GICD_IROUTER_SPI_MODE_ANY (1U << 31) 98 99 #define GIC_PIDR2_ARCH_MASK 0xf0 100 #define GIC_PIDR2_ARCH_GICv3 0x30 101 #define GIC_PIDR2_ARCH_GICv4 0x40 102 103 #define GIC_V3_DIST_SIZE 0x10000 104 105 #define GIC_PAGE_SIZE_4K 0ULL 106 #define GIC_PAGE_SIZE_16K 1ULL 107 #define GIC_PAGE_SIZE_64K 2ULL 108 #define GIC_PAGE_SIZE_MASK 3ULL 109 110 /* 111 * Re-Distributor registers, offsets from RD_base 112 */ 113 #define GICR_CTLR GICD_CTLR 114 #define GICR_IIDR 0x0004 115 #define GICR_TYPER 0x0008 116 #define GICR_STATUSR GICD_STATUSR 117 #define GICR_WAKER 0x0014 118 #define GICR_SETLPIR 0x0040 119 #define GICR_CLRLPIR 0x0048 120 #define GICR_SEIR GICD_SEIR 121 #define GICR_PROPBASER 0x0070 122 #define GICR_PENDBASER 0x0078 123 #define GICR_INVLPIR 0x00A0 124 #define GICR_INVALLR 0x00B0 125 #define GICR_SYNCR 0x00C0 126 #define GICR_MOVLPIR 0x0100 127 #define GICR_MOVALLR 0x0110 128 #define GICR_IDREGS GICD_IDREGS 129 #define GICR_PIDR2 GICD_PIDR2 130 131 #define GICR_CTLR_ENABLE_LPIS (1UL << 0) 132 #define GICR_CTLR_RWP (1UL << 3) 133 134 #define GICR_TYPER_CPU_NUMBER(r) (((r) >> 8) & 0xffff) 135 136 #define EPPI_BASE_INTID 1056 137 138 #define GICR_TYPER_NR_PPIS(r) \ 139 ({ \ 140 unsigned int __ppinum = ((r) >> 27) & 0x1f; \ 141 unsigned int __nr_ppis = 16; \ 142 if (__ppinum == 1 || __ppinum == 2) \ 143 __nr_ppis += __ppinum * 32; \ 144 \ 145 __nr_ppis; \ 146 }) 147 148 #define GICR_WAKER_ProcessorSleep (1U << 1) 149 #define GICR_WAKER_ChildrenAsleep (1U << 2) 150 151 #define GIC_BASER_CACHE_nCnB 0ULL 152 #define GIC_BASER_CACHE_SameAsInner 0ULL 153 #define GIC_BASER_CACHE_nC 1ULL 154 #define GIC_BASER_CACHE_RaWt 2ULL 155 #define GIC_BASER_CACHE_RaWb 3ULL 156 #define GIC_BASER_CACHE_WaWt 4ULL 157 #define GIC_BASER_CACHE_WaWb 5ULL 158 #define GIC_BASER_CACHE_RaWaWt 6ULL 159 #define GIC_BASER_CACHE_RaWaWb 7ULL 160 #define GIC_BASER_CACHE_MASK 7ULL 161 #define GIC_BASER_NonShareable 0ULL 162 #define GIC_BASER_InnerShareable 1ULL 163 #define GIC_BASER_OuterShareable 2ULL 164 #define GIC_BASER_SHAREABILITY_MASK 3ULL 165 166 #define GIC_BASER_CACHEABILITY(reg, inner_outer, type) \ 167 (GIC_BASER_CACHE_##type << reg##_##inner_outer##_CACHEABILITY_SHIFT) 168 169 #define GIC_BASER_SHAREABILITY(reg, type) \ 170 (GIC_BASER_##type << reg##_SHAREABILITY_SHIFT) 171 172 /* encode a size field of width @w containing @n - 1 units */ 173 #define GIC_ENCODE_SZ(n, w) (((unsigned long)(n) - 1) & GENMASK_ULL(((w) - 1), 0)) 174 175 #define GICR_PROPBASER_SHAREABILITY_SHIFT (10) 176 #define GICR_PROPBASER_INNER_CACHEABILITY_SHIFT (7) 177 #define GICR_PROPBASER_OUTER_CACHEABILITY_SHIFT (56) 178 #define GICR_PROPBASER_SHAREABILITY_MASK \ 179 GIC_BASER_SHAREABILITY(GICR_PROPBASER, SHAREABILITY_MASK) 180 #define GICR_PROPBASER_INNER_CACHEABILITY_MASK \ 181 GIC_BASER_CACHEABILITY(GICR_PROPBASER, INNER, MASK) 182 #define GICR_PROPBASER_OUTER_CACHEABILITY_MASK \ 183 GIC_BASER_CACHEABILITY(GICR_PROPBASER, OUTER, MASK) 184 #define GICR_PROPBASER_CACHEABILITY_MASK GICR_PROPBASER_INNER_CACHEABILITY_MASK 185 186 #define GICR_PROPBASER_InnerShareable \ 187 GIC_BASER_SHAREABILITY(GICR_PROPBASER, InnerShareable) 188 189 #define GICR_PROPBASER_nCnB GIC_BASER_CACHEABILITY(GICR_PROPBASER, INNER, nCnB) 190 #define GICR_PROPBASER_nC GIC_BASER_CACHEABILITY(GICR_PROPBASER, INNER, nC) 191 #define GICR_PROPBASER_RaWt GIC_BASER_CACHEABILITY(GICR_PROPBASER, INNER, RaWt) 192 #define GICR_PROPBASER_RaWb GIC_BASER_CACHEABILITY(GICR_PROPBASER, INNER, RaWb) 193 #define GICR_PROPBASER_WaWt GIC_BASER_CACHEABILITY(GICR_PROPBASER, INNER, WaWt) 194 #define GICR_PROPBASER_WaWb GIC_BASER_CACHEABILITY(GICR_PROPBASER, INNER, WaWb) 195 #define GICR_PROPBASER_RaWaWt GIC_BASER_CACHEABILITY(GICR_PROPBASER, INNER, RaWaWt) 196 #define GICR_PROPBASER_RaWaWb GIC_BASER_CACHEABILITY(GICR_PROPBASER, INNER, RaWaWb) 197 198 #define GICR_PROPBASER_IDBITS_MASK (0x1f) 199 #define GICR_PROPBASER_ADDRESS(x) ((x) & GENMASK_ULL(51, 12)) 200 #define GICR_PENDBASER_ADDRESS(x) ((x) & GENMASK_ULL(51, 16)) 201 202 #define GICR_PENDBASER_SHAREABILITY_SHIFT (10) 203 #define GICR_PENDBASER_INNER_CACHEABILITY_SHIFT (7) 204 #define GICR_PENDBASER_OUTER_CACHEABILITY_SHIFT (56) 205 #define GICR_PENDBASER_SHAREABILITY_MASK \ 206 GIC_BASER_SHAREABILITY(GICR_PENDBASER, SHAREABILITY_MASK) 207 #define GICR_PENDBASER_INNER_CACHEABILITY_MASK \ 208 GIC_BASER_CACHEABILITY(GICR_PENDBASER, INNER, MASK) 209 #define GICR_PENDBASER_OUTER_CACHEABILITY_MASK \ 210 GIC_BASER_CACHEABILITY(GICR_PENDBASER, OUTER, MASK) 211 #define GICR_PENDBASER_CACHEABILITY_MASK GICR_PENDBASER_INNER_CACHEABILITY_MASK 212 213 #define GICR_PENDBASER_InnerShareable \ 214 GIC_BASER_SHAREABILITY(GICR_PENDBASER, InnerShareable) 215 216 #define GICR_PENDBASER_nCnB GIC_BASER_CACHEABILITY(GICR_PENDBASER, INNER, nCnB) 217 #define GICR_PENDBASER_nC GIC_BASER_CACHEABILITY(GICR_PENDBASER, INNER, nC) 218 #define GICR_PENDBASER_RaWt GIC_BASER_CACHEABILITY(GICR_PENDBASER, INNER, RaWt) 219 #define GICR_PENDBASER_RaWb GIC_BASER_CACHEABILITY(GICR_PENDBASER, INNER, RaWb) 220 #define GICR_PENDBASER_WaWt GIC_BASER_CACHEABILITY(GICR_PENDBASER, INNER, WaWt) 221 #define GICR_PENDBASER_WaWb GIC_BASER_CACHEABILITY(GICR_PENDBASER, INNER, WaWb) 222 #define GICR_PENDBASER_RaWaWt GIC_BASER_CACHEABILITY(GICR_PENDBASER, INNER, RaWaWt) 223 #define GICR_PENDBASER_RaWaWb GIC_BASER_CACHEABILITY(GICR_PENDBASER, INNER, RaWaWb) 224 225 #define GICR_PENDBASER_PTZ BIT_ULL(62) 226 227 /* 228 * Re-Distributor registers, offsets from SGI_base 229 */ 230 #define GICR_IGROUPR0 GICD_IGROUPR 231 #define GICR_ISENABLER0 GICD_ISENABLER 232 #define GICR_ICENABLER0 GICD_ICENABLER 233 #define GICR_ISPENDR0 GICD_ISPENDR 234 #define GICR_ICPENDR0 GICD_ICPENDR 235 #define GICR_ISACTIVER0 GICD_ISACTIVER 236 #define GICR_ICACTIVER0 GICD_ICACTIVER 237 #define GICR_IPRIORITYR0 GICD_IPRIORITYR 238 #define GICR_ICFGR0 GICD_ICFGR 239 #define GICR_IGRPMODR0 GICD_IGRPMODR 240 #define GICR_NSACR GICD_NSACR 241 242 #define GICR_TYPER_PLPIS (1U << 0) 243 #define GICR_TYPER_VLPIS (1U << 1) 244 #define GICR_TYPER_DirectLPIS (1U << 3) 245 #define GICR_TYPER_LAST (1U << 4) 246 #define GICR_TYPER_RVPEID (1U << 7) 247 #define GICR_TYPER_COMMON_LPI_AFF GENMASK_ULL(25, 24) 248 #define GICR_TYPER_AFFINITY GENMASK_ULL(63, 32) 249 250 #define GICR_INVLPIR_INTID GENMASK_ULL(31, 0) 251 #define GICR_INVLPIR_VPEID GENMASK_ULL(47, 32) 252 #define GICR_INVLPIR_V GENMASK_ULL(63, 63) 253 254 #define GICR_INVALLR_VPEID GICR_INVLPIR_VPEID 255 #define GICR_INVALLR_V GICR_INVLPIR_V 256 257 #define GIC_V3_REDIST_SIZE 0x20000 258 259 #define LPI_PROP_GROUP1 (1 << 1) 260 #define LPI_PROP_ENABLED (1 << 0) 261 262 /* 263 * Re-Distributor registers, offsets from VLPI_base 264 */ 265 #define GICR_VPROPBASER 0x0070 266 267 #define GICR_VPROPBASER_IDBITS_MASK 0x1f 268 269 #define GICR_VPROPBASER_SHAREABILITY_SHIFT (10) 270 #define GICR_VPROPBASER_INNER_CACHEABILITY_SHIFT (7) 271 #define GICR_VPROPBASER_OUTER_CACHEABILITY_SHIFT (56) 272 273 #define GICR_VPROPBASER_SHAREABILITY_MASK \ 274 GIC_BASER_SHAREABILITY(GICR_VPROPBASER, SHAREABILITY_MASK) 275 #define GICR_VPROPBASER_INNER_CACHEABILITY_MASK \ 276 GIC_BASER_CACHEABILITY(GICR_VPROPBASER, INNER, MASK) 277 #define GICR_VPROPBASER_OUTER_CACHEABILITY_MASK \ 278 GIC_BASER_CACHEABILITY(GICR_VPROPBASER, OUTER, MASK) 279 #define GICR_VPROPBASER_CACHEABILITY_MASK \ 280 GICR_VPROPBASER_INNER_CACHEABILITY_MASK 281 282 #define GICR_VPROPBASER_InnerShareable \ 283 GIC_BASER_SHAREABILITY(GICR_VPROPBASER, InnerShareable) 284 285 #define GICR_VPROPBASER_nCnB GIC_BASER_CACHEABILITY(GICR_VPROPBASER, INNER, nCnB) 286 #define GICR_VPROPBASER_nC GIC_BASER_CACHEABILITY(GICR_VPROPBASER, INNER, nC) 287 #define GICR_VPROPBASER_RaWt GIC_BASER_CACHEABILITY(GICR_VPROPBASER, INNER, RaWt) 288 #define GICR_VPROPBASER_RaWb GIC_BASER_CACHEABILITY(GICR_VPROPBASER, INNER, RaWb) 289 #define GICR_VPROPBASER_WaWt GIC_BASER_CACHEABILITY(GICR_VPROPBASER, INNER, WaWt) 290 #define GICR_VPROPBASER_WaWb GIC_BASER_CACHEABILITY(GICR_VPROPBASER, INNER, WaWb) 291 #define GICR_VPROPBASER_RaWaWt GIC_BASER_CACHEABILITY(GICR_VPROPBASER, INNER, RaWaWt) 292 #define GICR_VPROPBASER_RaWaWb GIC_BASER_CACHEABILITY(GICR_VPROPBASER, INNER, RaWaWb) 293 294 /* 295 * GICv4.1 VPROPBASER reinvention. A subtle mix between the old 296 * VPROPBASER and ITS_BASER. Just not quite any of the two. 297 */ 298 #define GICR_VPROPBASER_4_1_VALID (1ULL << 63) 299 #define GICR_VPROPBASER_4_1_ENTRY_SIZE GENMASK_ULL(61, 59) 300 #define GICR_VPROPBASER_4_1_INDIRECT (1ULL << 55) 301 #define GICR_VPROPBASER_4_1_PAGE_SIZE GENMASK_ULL(54, 53) 302 #define GICR_VPROPBASER_4_1_Z (1ULL << 52) 303 #define GICR_VPROPBASER_4_1_ADDR GENMASK_ULL(51, 12) 304 #define GICR_VPROPBASER_4_1_SIZE GENMASK_ULL(6, 0) 305 306 #define GICR_VPENDBASER 0x0078 307 308 #define GICR_VPENDBASER_SHAREABILITY_SHIFT (10) 309 #define GICR_VPENDBASER_INNER_CACHEABILITY_SHIFT (7) 310 #define GICR_VPENDBASER_OUTER_CACHEABILITY_SHIFT (56) 311 #define GICR_VPENDBASER_SHAREABILITY_MASK \ 312 GIC_BASER_SHAREABILITY(GICR_VPENDBASER, SHAREABILITY_MASK) 313 #define GICR_VPENDBASER_INNER_CACHEABILITY_MASK \ 314 GIC_BASER_CACHEABILITY(GICR_VPENDBASER, INNER, MASK) 315 #define GICR_VPENDBASER_OUTER_CACHEABILITY_MASK \ 316 GIC_BASER_CACHEABILITY(GICR_VPENDBASER, OUTER, MASK) 317 #define GICR_VPENDBASER_CACHEABILITY_MASK \ 318 GICR_VPENDBASER_INNER_CACHEABILITY_MASK 319 320 #define GICR_VPENDBASER_NonShareable \ 321 GIC_BASER_SHAREABILITY(GICR_VPENDBASER, NonShareable) 322 323 #define GICR_VPENDBASER_nCnB GIC_BASER_CACHEABILITY(GICR_VPENDBASER, INNER, nCnB) 324 #define GICR_VPENDBASER_nC GIC_BASER_CACHEABILITY(GICR_VPENDBASER, INNER, nC) 325 #define GICR_VPENDBASER_RaWt GIC_BASER_CACHEABILITY(GICR_VPENDBASER, INNER, RaWt) 326 #define GICR_VPENDBASER_RaWb GIC_BASER_CACHEABILITY(GICR_VPENDBASER, INNER, RaWb) 327 #define GICR_VPENDBASER_WaWt GIC_BASER_CACHEABILITY(GICR_VPENDBASER, INNER, WaWt) 328 #define GICR_VPENDBASER_WaWb GIC_BASER_CACHEABILITY(GICR_VPENDBASER, INNER, WaWb) 329 #define GICR_VPENDBASER_RaWaWt GIC_BASER_CACHEABILITY(GICR_VPENDBASER, INNER, RaWaWt) 330 #define GICR_VPENDBASER_RaWaWb GIC_BASER_CACHEABILITY(GICR_VPENDBASER, INNER, RaWaWb) 331 332 #define GICR_VPENDBASER_Dirty (1ULL << 60) 333 #define GICR_VPENDBASER_PendingLast (1ULL << 61) 334 #define GICR_VPENDBASER_IDAI (1ULL << 62) 335 #define GICR_VPENDBASER_Valid (1ULL << 63) 336 337 /* 338 * GICv4.1 VPENDBASER, used for VPE residency. On top of these fields, 339 * also use the above Valid, PendingLast and Dirty. 340 */ 341 #define GICR_VPENDBASER_4_1_DB (1ULL << 62) 342 #define GICR_VPENDBASER_4_1_VGRP0EN (1ULL << 59) 343 #define GICR_VPENDBASER_4_1_VGRP1EN (1ULL << 58) 344 #define GICR_VPENDBASER_4_1_VPEID GENMASK_ULL(15, 0) 345 346 /* 347 * ITS registers, offsets from ITS_base 348 */ 349 #define GITS_CTLR 0x0000 350 #define GITS_IIDR 0x0004 351 #define GITS_TYPER 0x0008 352 #define GITS_MPIDR 0x0018 353 #define GITS_CBASER 0x0080 354 #define GITS_CWRITER 0x0088 355 #define GITS_CREADR 0x0090 356 #define GITS_BASER 0x0100 357 #define GITS_IDREGS_BASE 0xffd0 358 #define GITS_PIDR0 0xffe0 359 #define GITS_PIDR1 0xffe4 360 #define GITS_PIDR2 GICR_PIDR2 361 #define GITS_PIDR4 0xffd0 362 #define GITS_CIDR0 0xfff0 363 #define GITS_CIDR1 0xfff4 364 #define GITS_CIDR2 0xfff8 365 #define GITS_CIDR3 0xfffc 366 367 #define GITS_TRANSLATER 0x10040 368 369 #define GITS_CTLR_ENABLE (1U << 0) 370 #define GITS_CTLR_ImDe (1U << 1) 371 #define GITS_CTLR_ITS_NUMBER_SHIFT 4 372 #define GITS_CTLR_ITS_NUMBER (0xFU << GITS_CTLR_ITS_NUMBER_SHIFT) 373 #define GITS_CTLR_QUIESCENT (1U << 31) 374 375 #define GITS_TYPER_PLPIS (1UL << 0) 376 #define GITS_TYPER_VLPIS (1UL << 1) 377 #define GITS_TYPER_ITT_ENTRY_SIZE_SHIFT 4 378 #define GITS_TYPER_ITT_ENTRY_SIZE GENMASK_ULL(7, 4) 379 #define GITS_TYPER_IDBITS_SHIFT 8 380 #define GITS_TYPER_DEVBITS_SHIFT 13 381 #define GITS_TYPER_DEVBITS GENMASK_ULL(17, 13) 382 #define GITS_TYPER_PTA (1UL << 19) 383 #define GITS_TYPER_HCC_SHIFT 24 384 #define GITS_TYPER_HCC(r) (((r) >> GITS_TYPER_HCC_SHIFT) & 0xff) 385 #define GITS_TYPER_VMOVP (1ULL << 37) 386 #define GITS_TYPER_VMAPP (1ULL << 40) 387 #define GITS_TYPER_SVPET GENMASK_ULL(42, 41) 388 389 #define GITS_IIDR_REV_SHIFT 12 390 #define GITS_IIDR_REV_MASK (0xf << GITS_IIDR_REV_SHIFT) 391 #define GITS_IIDR_REV(r) (((r) >> GITS_IIDR_REV_SHIFT) & 0xf) 392 #define GITS_IIDR_PRODUCTID_SHIFT 24 393 394 #define GITS_CBASER_VALID (1ULL << 63) 395 #define GITS_CBASER_SHAREABILITY_SHIFT (10) 396 #define GITS_CBASER_INNER_CACHEABILITY_SHIFT (59) 397 #define GITS_CBASER_OUTER_CACHEABILITY_SHIFT (53) 398 #define GITS_CBASER_SHAREABILITY_MASK \ 399 GIC_BASER_SHAREABILITY(GITS_CBASER, SHAREABILITY_MASK) 400 #define GITS_CBASER_INNER_CACHEABILITY_MASK \ 401 GIC_BASER_CACHEABILITY(GITS_CBASER, INNER, MASK) 402 #define GITS_CBASER_OUTER_CACHEABILITY_MASK \ 403 GIC_BASER_CACHEABILITY(GITS_CBASER, OUTER, MASK) 404 #define GITS_CBASER_CACHEABILITY_MASK GITS_CBASER_INNER_CACHEABILITY_MASK 405 406 #define GITS_CBASER_InnerShareable \ 407 GIC_BASER_SHAREABILITY(GITS_CBASER, InnerShareable) 408 409 #define GITS_CBASER_nCnB GIC_BASER_CACHEABILITY(GITS_CBASER, INNER, nCnB) 410 #define GITS_CBASER_nC GIC_BASER_CACHEABILITY(GITS_CBASER, INNER, nC) 411 #define GITS_CBASER_RaWt GIC_BASER_CACHEABILITY(GITS_CBASER, INNER, RaWt) 412 #define GITS_CBASER_RaWb GIC_BASER_CACHEABILITY(GITS_CBASER, INNER, RaWb) 413 #define GITS_CBASER_WaWt GIC_BASER_CACHEABILITY(GITS_CBASER, INNER, WaWt) 414 #define GITS_CBASER_WaWb GIC_BASER_CACHEABILITY(GITS_CBASER, INNER, WaWb) 415 #define GITS_CBASER_RaWaWt GIC_BASER_CACHEABILITY(GITS_CBASER, INNER, RaWaWt) 416 #define GITS_CBASER_RaWaWb GIC_BASER_CACHEABILITY(GITS_CBASER, INNER, RaWaWb) 417 418 #define GITS_CBASER_ADDRESS(cbaser) ((cbaser) & GENMASK_ULL(51, 12)) 419 420 #define GITS_BASER_NR_REGS 8 421 422 #define GITS_BASER_VALID (1ULL << 63) 423 #define GITS_BASER_INDIRECT (1ULL << 62) 424 425 #define GITS_BASER_INNER_CACHEABILITY_SHIFT (59) 426 #define GITS_BASER_OUTER_CACHEABILITY_SHIFT (53) 427 #define GITS_BASER_INNER_CACHEABILITY_MASK \ 428 GIC_BASER_CACHEABILITY(GITS_BASER, INNER, MASK) 429 #define GITS_BASER_CACHEABILITY_MASK GITS_BASER_INNER_CACHEABILITY_MASK 430 #define GITS_BASER_OUTER_CACHEABILITY_MASK \ 431 GIC_BASER_CACHEABILITY(GITS_BASER, OUTER, MASK) 432 #define GITS_BASER_SHAREABILITY_MASK \ 433 GIC_BASER_SHAREABILITY(GITS_BASER, SHAREABILITY_MASK) 434 435 #define GITS_BASER_nCnB GIC_BASER_CACHEABILITY(GITS_BASER, INNER, nCnB) 436 #define GITS_BASER_nC GIC_BASER_CACHEABILITY(GITS_BASER, INNER, nC) 437 #define GITS_BASER_RaWt GIC_BASER_CACHEABILITY(GITS_BASER, INNER, RaWt) 438 #define GITS_BASER_RaWb GIC_BASER_CACHEABILITY(GITS_BASER, INNER, RaWb) 439 #define GITS_BASER_WaWt GIC_BASER_CACHEABILITY(GITS_BASER, INNER, WaWt) 440 #define GITS_BASER_WaWb GIC_BASER_CACHEABILITY(GITS_BASER, INNER, WaWb) 441 #define GITS_BASER_RaWaWt GIC_BASER_CACHEABILITY(GITS_BASER, INNER, RaWaWt) 442 #define GITS_BASER_RaWaWb GIC_BASER_CACHEABILITY(GITS_BASER, INNER, RaWaWb) 443 444 #define GITS_BASER_TYPE_SHIFT (56) 445 #define GITS_BASER_TYPE(r) (((r) >> GITS_BASER_TYPE_SHIFT) & 7) 446 #define GITS_BASER_ENTRY_SIZE_SHIFT (48) 447 #define GITS_BASER_ENTRY_SIZE(r) ((((r) >> GITS_BASER_ENTRY_SIZE_SHIFT) & 0x1f) + 1) 448 #define GITS_BASER_ENTRY_SIZE_MASK GENMASK_ULL(52, 48) 449 #define GITS_BASER_PHYS_52_to_48(phys) \ 450 (((phys) & GENMASK_ULL(47, 16)) | (((phys) >> 48) & 0xf) << 12) 451 #define GITS_BASER_ADDR_48_to_52(baser) \ 452 (((baser) & GENMASK_ULL(47, 16)) | (((baser) >> 12) & 0xf) << 48) 453 454 #define GITS_BASER_SHAREABILITY_SHIFT (10) 455 #define GITS_BASER_InnerShareable \ 456 GIC_BASER_SHAREABILITY(GITS_BASER, InnerShareable) 457 #define GITS_BASER_PAGE_SIZE_SHIFT (8) 458 #define __GITS_BASER_PSZ(sz) (GIC_PAGE_SIZE_ ## sz << GITS_BASER_PAGE_SIZE_SHIFT) 459 #define GITS_BASER_PAGE_SIZE_4K __GITS_BASER_PSZ(4K) 460 #define GITS_BASER_PAGE_SIZE_16K __GITS_BASER_PSZ(16K) 461 #define GITS_BASER_PAGE_SIZE_64K __GITS_BASER_PSZ(64K) 462 #define GITS_BASER_PAGE_SIZE_MASK __GITS_BASER_PSZ(MASK) 463 #define GITS_BASER_PAGES_MAX 256 464 #define GITS_BASER_PAGES_SHIFT (0) 465 #define GITS_BASER_NR_PAGES(r) (((r) & 0xff) + 1) 466 467 #define GITS_BASER_TYPE_NONE 0 468 #define GITS_BASER_TYPE_DEVICE 1 469 #define GITS_BASER_TYPE_VCPU 2 470 #define GITS_BASER_TYPE_RESERVED3 3 471 #define GITS_BASER_TYPE_COLLECTION 4 472 #define GITS_BASER_TYPE_RESERVED5 5 473 #define GITS_BASER_TYPE_RESERVED6 6 474 #define GITS_BASER_TYPE_RESERVED7 7 475 476 #define GITS_LVL1_ENTRY_SIZE (8UL) 477 478 /* 479 * ITS commands 480 */ 481 #define GITS_CMD_MAPD 0x08 482 #define GITS_CMD_MAPC 0x09 483 #define GITS_CMD_MAPTI 0x0a 484 #define GITS_CMD_MAPI 0x0b 485 #define GITS_CMD_MOVI 0x01 486 #define GITS_CMD_DISCARD 0x0f 487 #define GITS_CMD_INV 0x0c 488 #define GITS_CMD_MOVALL 0x0e 489 #define GITS_CMD_INVALL 0x0d 490 #define GITS_CMD_INT 0x03 491 #define GITS_CMD_CLEAR 0x04 492 #define GITS_CMD_SYNC 0x05 493 494 /* 495 * GICv4 ITS specific commands 496 */ 497 #define GITS_CMD_GICv4(x) ((x) | 0x20) 498 #define GITS_CMD_VINVALL GITS_CMD_GICv4(GITS_CMD_INVALL) 499 #define GITS_CMD_VMAPP GITS_CMD_GICv4(GITS_CMD_MAPC) 500 #define GITS_CMD_VMAPTI GITS_CMD_GICv4(GITS_CMD_MAPTI) 501 #define GITS_CMD_VMOVI GITS_CMD_GICv4(GITS_CMD_MOVI) 502 #define GITS_CMD_VSYNC GITS_CMD_GICv4(GITS_CMD_SYNC) 503 /* VMOVP and INVDB are the odd ones, as they dont have a physical counterpart */ 504 #define GITS_CMD_VMOVP GITS_CMD_GICv4(2) 505 #define GITS_CMD_INVDB GITS_CMD_GICv4(0xe) 506 507 /* 508 * ITS error numbers 509 */ 510 #define E_ITS_MOVI_UNMAPPED_INTERRUPT 0x010107 511 #define E_ITS_MOVI_UNMAPPED_COLLECTION 0x010109 512 #define E_ITS_INT_UNMAPPED_INTERRUPT 0x010307 513 #define E_ITS_CLEAR_UNMAPPED_INTERRUPT 0x010507 514 #define E_ITS_MAPD_DEVICE_OOR 0x010801 515 #define E_ITS_MAPD_ITTSIZE_OOR 0x010802 516 #define E_ITS_MAPC_PROCNUM_OOR 0x010902 517 #define E_ITS_MAPC_COLLECTION_OOR 0x010903 518 #define E_ITS_MAPTI_UNMAPPED_DEVICE 0x010a04 519 #define E_ITS_MAPTI_ID_OOR 0x010a05 520 #define E_ITS_MAPTI_PHYSICALID_OOR 0x010a06 521 #define E_ITS_INV_UNMAPPED_INTERRUPT 0x010c07 522 #define E_ITS_INVALL_UNMAPPED_COLLECTION 0x010d09 523 #define E_ITS_MOVALL_PROCNUM_OOR 0x010e01 524 #define E_ITS_DISCARD_UNMAPPED_INTERRUPT 0x010f07 525 526 /* 527 * CPU interface registers 528 */ 529 #define ICC_CTLR_EL1_EOImode_SHIFT (1) 530 #define ICC_CTLR_EL1_EOImode_drop_dir (0U << ICC_CTLR_EL1_EOImode_SHIFT) 531 #define ICC_CTLR_EL1_EOImode_drop (1U << ICC_CTLR_EL1_EOImode_SHIFT) 532 #define ICC_CTLR_EL1_EOImode_MASK (1 << ICC_CTLR_EL1_EOImode_SHIFT) 533 #define ICC_CTLR_EL1_CBPR_SHIFT 0 534 #define ICC_CTLR_EL1_CBPR_MASK (1 << ICC_CTLR_EL1_CBPR_SHIFT) 535 #define ICC_CTLR_EL1_PMHE_SHIFT 6 536 #define ICC_CTLR_EL1_PMHE_MASK (1 << ICC_CTLR_EL1_PMHE_SHIFT) 537 #define ICC_CTLR_EL1_PRI_BITS_SHIFT 8 538 #define ICC_CTLR_EL1_PRI_BITS_MASK (0x7 << ICC_CTLR_EL1_PRI_BITS_SHIFT) 539 #define ICC_CTLR_EL1_ID_BITS_SHIFT 11 540 #define ICC_CTLR_EL1_ID_BITS_MASK (0x7 << ICC_CTLR_EL1_ID_BITS_SHIFT) 541 #define ICC_CTLR_EL1_SEIS_SHIFT 14 542 #define ICC_CTLR_EL1_SEIS_MASK (0x1 << ICC_CTLR_EL1_SEIS_SHIFT) 543 #define ICC_CTLR_EL1_A3V_SHIFT 15 544 #define ICC_CTLR_EL1_A3V_MASK (0x1 << ICC_CTLR_EL1_A3V_SHIFT) 545 #define ICC_CTLR_EL1_RSS (0x1 << 18) 546 #define ICC_CTLR_EL1_ExtRange (0x1 << 19) 547 #define ICC_PMR_EL1_SHIFT 0 548 #define ICC_PMR_EL1_MASK (0xff << ICC_PMR_EL1_SHIFT) 549 #define ICC_BPR0_EL1_SHIFT 0 550 #define ICC_BPR0_EL1_MASK (0x7 << ICC_BPR0_EL1_SHIFT) 551 #define ICC_BPR1_EL1_SHIFT 0 552 #define ICC_BPR1_EL1_MASK (0x7 << ICC_BPR1_EL1_SHIFT) 553 #define ICC_IGRPEN0_EL1_SHIFT 0 554 #define ICC_IGRPEN0_EL1_MASK (1 << ICC_IGRPEN0_EL1_SHIFT) 555 #define ICC_IGRPEN1_EL1_SHIFT 0 556 #define ICC_IGRPEN1_EL1_MASK (1 << ICC_IGRPEN1_EL1_SHIFT) 557 #define ICC_SRE_EL1_DIB (1U << 2) 558 #define ICC_SRE_EL1_DFB (1U << 1) 559 #define ICC_SRE_EL1_SRE (1U << 0) 560 561 /* 562 * Hypervisor interface registers (SRE only) 563 */ 564 #define ICH_LR_VIRTUAL_ID_MASK ((1ULL << 32) - 1) 565 566 #define ICH_LR_EOI (1ULL << 41) 567 #define ICH_LR_GROUP (1ULL << 60) 568 #define ICH_LR_HW (1ULL << 61) 569 #define ICH_LR_STATE (3ULL << 62) 570 #define ICH_LR_PENDING_BIT (1ULL << 62) 571 #define ICH_LR_ACTIVE_BIT (1ULL << 63) 572 #define ICH_LR_PHYS_ID_SHIFT 32 573 #define ICH_LR_PHYS_ID_MASK (0x3ffULL << ICH_LR_PHYS_ID_SHIFT) 574 #define ICH_LR_PRIORITY_SHIFT 48 575 #define ICH_LR_PRIORITY_MASK (0xffULL << ICH_LR_PRIORITY_SHIFT) 576 577 /* These are for GICv2 emulation only */ 578 #define GICH_LR_VIRTUALID (0x3ffUL << 0) 579 #define GICH_LR_PHYSID_CPUID_SHIFT (10) 580 #define GICH_LR_PHYSID_CPUID (7UL << GICH_LR_PHYSID_CPUID_SHIFT) 581 582 #define ICH_MISR_EOI (1 << 0) 583 #define ICH_MISR_U (1 << 1) 584 585 #define ICH_HCR_EN (1 << 0) 586 #define ICH_HCR_UIE (1 << 1) 587 #define ICH_HCR_NPIE (1 << 3) 588 #define ICH_HCR_TC (1 << 10) 589 #define ICH_HCR_TALL0 (1 << 11) 590 #define ICH_HCR_TALL1 (1 << 12) 591 #define ICH_HCR_EOIcount_SHIFT 27 592 #define ICH_HCR_EOIcount_MASK (0x1f << ICH_HCR_EOIcount_SHIFT) 593 594 #define ICH_VMCR_ACK_CTL_SHIFT 2 595 #define ICH_VMCR_ACK_CTL_MASK (1 << ICH_VMCR_ACK_CTL_SHIFT) 596 #define ICH_VMCR_FIQ_EN_SHIFT 3 597 #define ICH_VMCR_FIQ_EN_MASK (1 << ICH_VMCR_FIQ_EN_SHIFT) 598 #define ICH_VMCR_CBPR_SHIFT 4 599 #define ICH_VMCR_CBPR_MASK (1 << ICH_VMCR_CBPR_SHIFT) 600 #define ICH_VMCR_EOIM_SHIFT 9 601 #define ICH_VMCR_EOIM_MASK (1 << ICH_VMCR_EOIM_SHIFT) 602 #define ICH_VMCR_BPR1_SHIFT 18 603 #define ICH_VMCR_BPR1_MASK (7 << ICH_VMCR_BPR1_SHIFT) 604 #define ICH_VMCR_BPR0_SHIFT 21 605 #define ICH_VMCR_BPR0_MASK (7 << ICH_VMCR_BPR0_SHIFT) 606 #define ICH_VMCR_PMR_SHIFT 24 607 #define ICH_VMCR_PMR_MASK (0xffUL << ICH_VMCR_PMR_SHIFT) 608 #define ICH_VMCR_ENG0_SHIFT 0 609 #define ICH_VMCR_ENG0_MASK (1 << ICH_VMCR_ENG0_SHIFT) 610 #define ICH_VMCR_ENG1_SHIFT 1 611 #define ICH_VMCR_ENG1_MASK (1 << ICH_VMCR_ENG1_SHIFT) 612 613 #define ICH_VTR_PRI_BITS_SHIFT 29 614 #define ICH_VTR_PRI_BITS_MASK (7 << ICH_VTR_PRI_BITS_SHIFT) 615 #define ICH_VTR_ID_BITS_SHIFT 23 616 #define ICH_VTR_ID_BITS_MASK (7 << ICH_VTR_ID_BITS_SHIFT) 617 #define ICH_VTR_SEIS_SHIFT 22 618 #define ICH_VTR_SEIS_MASK (1 << ICH_VTR_SEIS_SHIFT) 619 #define ICH_VTR_A3V_SHIFT 21 620 #define ICH_VTR_A3V_MASK (1 << ICH_VTR_A3V_SHIFT) 621 622 #define ICC_IAR1_EL1_SPURIOUS 0x3ff 623 624 #define ICC_SRE_EL2_SRE (1 << 0) 625 #define ICC_SRE_EL2_ENABLE (1 << 3) 626 627 #define ICC_SGI1R_TARGET_LIST_SHIFT 0 628 #define ICC_SGI1R_TARGET_LIST_MASK (0xffff << ICC_SGI1R_TARGET_LIST_SHIFT) 629 #define ICC_SGI1R_AFFINITY_1_SHIFT 16 630 #define ICC_SGI1R_AFFINITY_1_MASK (0xff << ICC_SGI1R_AFFINITY_1_SHIFT) 631 #define ICC_SGI1R_SGI_ID_SHIFT 24 632 #define ICC_SGI1R_SGI_ID_MASK (0xfULL << ICC_SGI1R_SGI_ID_SHIFT) 633 #define ICC_SGI1R_AFFINITY_2_SHIFT 32 634 #define ICC_SGI1R_AFFINITY_2_MASK (0xffULL << ICC_SGI1R_AFFINITY_2_SHIFT) 635 #define ICC_SGI1R_IRQ_ROUTING_MODE_BIT 40 636 #define ICC_SGI1R_RS_SHIFT 44 637 #define ICC_SGI1R_RS_MASK (0xfULL << ICC_SGI1R_RS_SHIFT) 638 #define ICC_SGI1R_AFFINITY_3_SHIFT 48 639 #define ICC_SGI1R_AFFINITY_3_MASK (0xffULL << ICC_SGI1R_AFFINITY_3_SHIFT) 640 641 #include <asm/arch_gicv3.h> 642 643 #ifndef __ASSEMBLY__ 644 645 /* 646 * We need a value to serve as a irq-type for LPIs. Choose one that will 647 * hopefully pique the interest of the reviewer. 648 */ 649 #define GIC_IRQ_TYPE_LPI 0xa110c8ed 650 651 struct rdists { 652 struct { 653 void __iomem *rd_base; 654 struct page *pend_page; 655 phys_addr_t phys_base; 656 bool lpi_enabled; 657 cpumask_t *vpe_table_mask; 658 void *vpe_l1_base; 659 } __percpu *rdist; 660 phys_addr_t prop_table_pa; 661 void *prop_table_va; 662 u64 flags; 663 u32 gicd_typer; 664 u32 gicd_typer2; 665 bool has_vlpis; 666 bool has_rvpeid; 667 bool has_direct_lpi; 668 }; 669 670 struct irq_domain; 671 struct fwnode_handle; 672 int its_cpu_init(void); 673 int its_init(struct fwnode_handle *handle, struct rdists *rdists, 674 struct irq_domain *domain); 675 int mbi_init(struct fwnode_handle *fwnode, struct irq_domain *parent); 676 677 static inline bool gic_enable_sre(void) 678 { 679 u32 val; 680 681 val = gic_read_sre(); 682 if (val & ICC_SRE_EL1_SRE) 683 return true; 684 685 val |= ICC_SRE_EL1_SRE; 686 gic_write_sre(val); 687 val = gic_read_sre(); 688 689 return !!(val & ICC_SRE_EL1_SRE); 690 } 691 692 #endif 693 694 #endif 695