1 /* SPDX-License-Identifier: GPL-2.0 */ 2 #ifndef __IO_PGTABLE_H 3 #define __IO_PGTABLE_H 4 5 #include <linux/bitops.h> 6 #include <linux/iommu.h> 7 8 /* 9 * Public API for use by IOMMU drivers 10 */ 11 enum io_pgtable_fmt { 12 ARM_32_LPAE_S1, 13 ARM_32_LPAE_S2, 14 ARM_64_LPAE_S1, 15 ARM_64_LPAE_S2, 16 ARM_V7S, 17 ARM_MALI_LPAE, 18 APPLE_DART, 19 APPLE_DART2, 20 IO_PGTABLE_NUM_FMTS, 21 }; 22 23 /** 24 * struct iommu_flush_ops - IOMMU callbacks for TLB and page table management. 25 * 26 * @tlb_flush_all: Synchronously invalidate the entire TLB context. 27 * @tlb_flush_walk: Synchronously invalidate all intermediate TLB state 28 * (sometimes referred to as the "walk cache") for a virtual 29 * address range. 30 * @tlb_add_page: Optional callback to queue up leaf TLB invalidation for a 31 * single page. IOMMUs that cannot batch TLB invalidation 32 * operations efficiently will typically issue them here, but 33 * others may decide to update the iommu_iotlb_gather structure 34 * and defer the invalidation until iommu_iotlb_sync() instead. 35 * 36 * Note that these can all be called in atomic context and must therefore 37 * not block. 38 */ 39 struct iommu_flush_ops { 40 void (*tlb_flush_all)(void *cookie); 41 void (*tlb_flush_walk)(unsigned long iova, size_t size, size_t granule, 42 void *cookie); 43 void (*tlb_add_page)(struct iommu_iotlb_gather *gather, 44 unsigned long iova, size_t granule, void *cookie); 45 }; 46 47 /** 48 * struct io_pgtable_cfg - Configuration data for a set of page tables. 49 * 50 * @quirks: A bitmap of hardware quirks that require some special 51 * action by the low-level page table allocator. 52 * @pgsize_bitmap: A bitmap of page sizes supported by this set of page 53 * tables. 54 * @ias: Input address (iova) size, in bits. 55 * @oas: Output address (paddr) size, in bits. 56 * @coherent_walk A flag to indicate whether or not page table walks made 57 * by the IOMMU are coherent with the CPU caches. 58 * @tlb: TLB management callbacks for this set of tables. 59 * @iommu_dev: The device representing the DMA configuration for the 60 * page table walker. 61 */ 62 struct io_pgtable_cfg { 63 /* 64 * IO_PGTABLE_QUIRK_ARM_NS: (ARM formats) Set NS and NSTABLE bits in 65 * stage 1 PTEs, for hardware which insists on validating them 66 * even in non-secure state where they should normally be ignored. 67 * 68 * IO_PGTABLE_QUIRK_NO_PERMS: Ignore the IOMMU_READ, IOMMU_WRITE and 69 * IOMMU_NOEXEC flags and map everything with full access, for 70 * hardware which does not implement the permissions of a given 71 * format, and/or requires some format-specific default value. 72 * 73 * IO_PGTABLE_QUIRK_ARM_MTK_EXT: (ARM v7s format) MediaTek IOMMUs extend 74 * to support up to 35 bits PA where the bit32, bit33 and bit34 are 75 * encoded in the bit9, bit4 and bit5 of the PTE respectively. 76 * 77 * IO_PGTABLE_QUIRK_ARM_MTK_TTBR_EXT: (ARM v7s format) MediaTek IOMMUs 78 * extend the translation table base support up to 35 bits PA, the 79 * encoding format is same with IO_PGTABLE_QUIRK_ARM_MTK_EXT. 80 * 81 * IO_PGTABLE_QUIRK_ARM_TTBR1: (ARM LPAE format) Configure the table 82 * for use in the upper half of a split address space. 83 * 84 * IO_PGTABLE_QUIRK_ARM_OUTER_WBWA: Override the outer-cacheability 85 * attributes set in the TCR for a non-coherent page-table walker. 86 * 87 * IO_PGTABLE_QUIRK_ARM_HD: Enables dirty tracking in stage 1 pagetable. 88 * IO_PGTABLE_QUIRK_ARM_S2FWB: Use the FWB format for the MemAttrs bits 89 * 90 * IO_PGTABLE_QUIRK_NO_WARN: Do not WARN_ON() on conflicting 91 * mappings, but silently return -EEXISTS. Normally an attempt 92 * to map over an existing mapping would indicate some sort of 93 * kernel bug, which would justify the WARN_ON(). But for GPU 94 * drivers, this could be under control of userspace. Which 95 * deserves an error return, but not to spam dmesg. 96 */ 97 #define IO_PGTABLE_QUIRK_ARM_NS BIT(0) 98 #define IO_PGTABLE_QUIRK_NO_PERMS BIT(1) 99 #define IO_PGTABLE_QUIRK_ARM_MTK_EXT BIT(3) 100 #define IO_PGTABLE_QUIRK_ARM_MTK_TTBR_EXT BIT(4) 101 #define IO_PGTABLE_QUIRK_ARM_TTBR1 BIT(5) 102 #define IO_PGTABLE_QUIRK_ARM_OUTER_WBWA BIT(6) 103 #define IO_PGTABLE_QUIRK_ARM_HD BIT(7) 104 #define IO_PGTABLE_QUIRK_ARM_S2FWB BIT(8) 105 #define IO_PGTABLE_QUIRK_NO_WARN BIT(9) 106 unsigned long quirks; 107 unsigned long pgsize_bitmap; 108 unsigned int ias; 109 unsigned int oas; 110 bool coherent_walk; 111 const struct iommu_flush_ops *tlb; 112 struct device *iommu_dev; 113 114 /** 115 * @alloc: Custom page allocator. 116 * 117 * Optional hook used to allocate page tables. If this function is NULL, 118 * @free must be NULL too. 119 * 120 * Memory returned should be zeroed and suitable for dma_map_single() and 121 * virt_to_phys(). 122 * 123 * Not all formats support custom page allocators. Before considering 124 * passing a non-NULL value, make sure the chosen page format supports 125 * this feature. 126 */ 127 void *(*alloc)(void *cookie, size_t size, gfp_t gfp); 128 129 /** 130 * @free: Custom page de-allocator. 131 * 132 * Optional hook used to free page tables allocated with the @alloc 133 * hook. Must be non-NULL if @alloc is not NULL, must be NULL 134 * otherwise. 135 */ 136 void (*free)(void *cookie, void *pages, size_t size); 137 138 /* Low-level data specific to the table format */ 139 union { 140 struct { 141 u64 ttbr; 142 struct { 143 u32 ips:3; 144 u32 tg:2; 145 u32 sh:2; 146 u32 orgn:2; 147 u32 irgn:2; 148 u32 tsz:6; 149 } tcr; 150 u64 mair; 151 } arm_lpae_s1_cfg; 152 153 struct { 154 u64 vttbr; 155 struct { 156 u32 ps:3; 157 u32 tg:2; 158 u32 sh:2; 159 u32 orgn:2; 160 u32 irgn:2; 161 u32 sl:2; 162 u32 tsz:6; 163 } vtcr; 164 } arm_lpae_s2_cfg; 165 166 struct { 167 u32 ttbr; 168 u32 tcr; 169 u32 nmrr; 170 u32 prrr; 171 } arm_v7s_cfg; 172 173 struct { 174 u64 transtab; 175 u64 memattr; 176 } arm_mali_lpae_cfg; 177 178 struct { 179 u64 ttbr[4]; 180 u32 n_ttbrs; 181 u32 n_levels; 182 } apple_dart_cfg; 183 184 struct { 185 int nid; 186 } amd; 187 }; 188 }; 189 190 /** 191 * struct arm_lpae_io_pgtable_walk_data - information from a pgtable walk 192 * 193 * @ptes: The recorded PTE values from the walk 194 */ 195 struct arm_lpae_io_pgtable_walk_data { 196 u64 ptes[4]; 197 }; 198 199 /** 200 * struct io_pgtable_ops - Page table manipulation API for IOMMU drivers. 201 * 202 * @map_pages: Map a physically contiguous range of pages of the same size. 203 * @unmap_pages: Unmap a range of virtually contiguous pages of the same size. 204 * @iova_to_phys: Translate iova to physical address. 205 * @pgtable_walk: (optional) Perform a page table walk for a given iova. 206 * 207 * These functions map directly onto the iommu_ops member functions with 208 * the same names. 209 */ 210 struct io_pgtable_ops { 211 int (*map_pages)(struct io_pgtable_ops *ops, unsigned long iova, 212 phys_addr_t paddr, size_t pgsize, size_t pgcount, 213 int prot, gfp_t gfp, size_t *mapped); 214 size_t (*unmap_pages)(struct io_pgtable_ops *ops, unsigned long iova, 215 size_t pgsize, size_t pgcount, 216 struct iommu_iotlb_gather *gather); 217 phys_addr_t (*iova_to_phys)(struct io_pgtable_ops *ops, 218 unsigned long iova); 219 int (*pgtable_walk)(struct io_pgtable_ops *ops, unsigned long iova, void *wd); 220 int (*read_and_clear_dirty)(struct io_pgtable_ops *ops, 221 unsigned long iova, size_t size, 222 unsigned long flags, 223 struct iommu_dirty_bitmap *dirty); 224 }; 225 226 /** 227 * alloc_io_pgtable_ops() - Allocate a page table allocator for use by an IOMMU. 228 * 229 * @fmt: The page table format. 230 * @cfg: The page table configuration. This will be modified to represent 231 * the configuration actually provided by the allocator (e.g. the 232 * pgsize_bitmap may be restricted). 233 * @cookie: An opaque token provided by the IOMMU driver and passed back to 234 * the callback routines in cfg->tlb. 235 */ 236 struct io_pgtable_ops *alloc_io_pgtable_ops(enum io_pgtable_fmt fmt, 237 struct io_pgtable_cfg *cfg, 238 void *cookie); 239 240 /** 241 * free_io_pgtable_ops() - Free an io_pgtable_ops structure. The caller 242 * *must* ensure that the page table is no longer 243 * live, but the TLB can be dirty. 244 * 245 * @ops: The ops returned from alloc_io_pgtable_ops. 246 */ 247 void free_io_pgtable_ops(struct io_pgtable_ops *ops); 248 249 250 /* 251 * Internal structures for page table allocator implementations. 252 */ 253 254 /** 255 * struct io_pgtable - Internal structure describing a set of page tables. 256 * 257 * @fmt: The page table format. 258 * @cookie: An opaque token provided by the IOMMU driver and passed back to 259 * any callback routines. 260 * @cfg: A copy of the page table configuration. 261 * @ops: The page table operations in use for this set of page tables. 262 */ 263 struct io_pgtable { 264 enum io_pgtable_fmt fmt; 265 void *cookie; 266 struct io_pgtable_cfg cfg; 267 struct io_pgtable_ops ops; 268 }; 269 270 #define io_pgtable_ops_to_pgtable(x) container_of((x), struct io_pgtable, ops) 271 272 static inline void io_pgtable_tlb_flush_all(struct io_pgtable *iop) 273 { 274 if (iop->cfg.tlb && iop->cfg.tlb->tlb_flush_all) 275 iop->cfg.tlb->tlb_flush_all(iop->cookie); 276 } 277 278 static inline void 279 io_pgtable_tlb_flush_walk(struct io_pgtable *iop, unsigned long iova, 280 size_t size, size_t granule) 281 { 282 if (iop->cfg.tlb && iop->cfg.tlb->tlb_flush_walk) 283 iop->cfg.tlb->tlb_flush_walk(iova, size, granule, iop->cookie); 284 } 285 286 static inline void 287 io_pgtable_tlb_add_page(struct io_pgtable *iop, 288 struct iommu_iotlb_gather * gather, unsigned long iova, 289 size_t granule) 290 { 291 if (iop->cfg.tlb && iop->cfg.tlb->tlb_add_page) 292 iop->cfg.tlb->tlb_add_page(gather, iova, granule, iop->cookie); 293 } 294 295 /** 296 * enum io_pgtable_caps - IO page table backend capabilities. 297 */ 298 enum io_pgtable_caps { 299 /** @IO_PGTABLE_CAP_CUSTOM_ALLOCATOR: Backend accepts custom page table allocators. */ 300 IO_PGTABLE_CAP_CUSTOM_ALLOCATOR = BIT(0), 301 }; 302 303 /** 304 * struct io_pgtable_init_fns - Alloc/free a set of page tables for a 305 * particular format. 306 * 307 * @alloc: Allocate a set of page tables described by cfg. 308 * @free: Free the page tables associated with iop. 309 * @caps: Combination of @io_pgtable_caps flags encoding the backend capabilities. 310 */ 311 struct io_pgtable_init_fns { 312 struct io_pgtable *(*alloc)(struct io_pgtable_cfg *cfg, void *cookie); 313 void (*free)(struct io_pgtable *iop); 314 u32 caps; 315 }; 316 317 extern struct io_pgtable_init_fns io_pgtable_arm_32_lpae_s1_init_fns; 318 extern struct io_pgtable_init_fns io_pgtable_arm_32_lpae_s2_init_fns; 319 extern struct io_pgtable_init_fns io_pgtable_arm_64_lpae_s1_init_fns; 320 extern struct io_pgtable_init_fns io_pgtable_arm_64_lpae_s2_init_fns; 321 extern struct io_pgtable_init_fns io_pgtable_arm_v7s_init_fns; 322 extern struct io_pgtable_init_fns io_pgtable_arm_mali_lpae_init_fns; 323 extern struct io_pgtable_init_fns io_pgtable_amd_iommu_v1_init_fns; 324 extern struct io_pgtable_init_fns io_pgtable_amd_iommu_v2_init_fns; 325 extern struct io_pgtable_init_fns io_pgtable_apple_dart_init_fns; 326 327 #endif /* __IO_PGTABLE_H */ 328