1 /** 2 * Freecale 85xx and 86xx Global Utilties register set 3 * 4 * Authors: Jeff Brown 5 * Timur Tabi <timur@freescale.com> 6 * 7 * Copyright 2004,2007,2012 Freescale Semiconductor, Inc 8 * 9 * This program is free software; you can redistribute it and/or modify it 10 * under the terms of the GNU General Public License as published by the 11 * Free Software Foundation; either version 2 of the License, or (at your 12 * option) any later version. 13 */ 14 15 #ifndef __FSL_GUTS_H__ 16 #define __FSL_GUTS_H__ 17 18 #include <linux/types.h> 19 20 /** 21 * Global Utility Registers. 22 * 23 * Not all registers defined in this structure are available on all chips, so 24 * you are expected to know whether a given register actually exists on your 25 * chip before you access it. 26 * 27 * Also, some registers are similar on different chips but have slightly 28 * different names. In these cases, one name is chosen to avoid extraneous 29 * #ifdefs. 30 */ 31 struct ccsr_guts { 32 u32 porpllsr; /* 0x.0000 - POR PLL Ratio Status Register */ 33 u32 porbmsr; /* 0x.0004 - POR Boot Mode Status Register */ 34 u32 porimpscr; /* 0x.0008 - POR I/O Impedance Status and 35 * Control Register 36 */ 37 u32 pordevsr; /* 0x.000c - POR I/O Device Status Register */ 38 u32 pordbgmsr; /* 0x.0010 - POR Debug Mode Status Register */ 39 u32 pordevsr2; /* 0x.0014 - POR device status register 2 */ 40 u8 res018[0x20 - 0x18]; 41 u32 porcir; /* 0x.0020 - POR Configuration Information 42 * Register 43 */ 44 u8 res024[0x30 - 0x24]; 45 u32 gpiocr; /* 0x.0030 - GPIO Control Register */ 46 u8 res034[0x40 - 0x34]; 47 u32 gpoutdr; /* 0x.0040 - General-Purpose Output Data 48 * Register 49 */ 50 u8 res044[0x50 - 0x44]; 51 u32 gpindr; /* 0x.0050 - General-Purpose Input Data 52 * Register 53 */ 54 u8 res054[0x60 - 0x54]; 55 u32 pmuxcr; /* 0x.0060 - Alternate Function Signal 56 * Multiplex Control 57 */ 58 u32 pmuxcr2; /* 0x.0064 - Alternate function signal 59 * multiplex control 2 60 */ 61 u32 dmuxcr; /* 0x.0068 - DMA Mux Control Register */ 62 u8 res06c[0x70 - 0x6c]; 63 u32 devdisr; /* 0x.0070 - Device Disable Control */ 64 #define CCSR_GUTS_DEVDISR_TB1 0x00001000 65 #define CCSR_GUTS_DEVDISR_TB0 0x00004000 66 u32 devdisr2; /* 0x.0074 - Device Disable Control 2 */ 67 u8 res078[0x7c - 0x78]; 68 u32 pmjcr; /* 0x.007c - 4 Power Management Jog Control 69 * Register 70 */ 71 u32 powmgtcsr; /* 0x.0080 - Power Management Status and 72 * Control Register 73 */ 74 u32 pmrccr; /* 0x.0084 - Power Management Reset Counter 75 * Configuration Register 76 */ 77 u32 pmpdccr; /* 0x.0088 - Power Management Power Down Counter 78 * Configuration Register 79 */ 80 u32 pmcdr; /* 0x.008c - 4Power management clock disable 81 * register 82 */ 83 u32 mcpsumr; /* 0x.0090 - Machine Check Summary Register */ 84 u32 rstrscr; /* 0x.0094 - Reset Request Status and 85 * Control Register 86 */ 87 u32 ectrstcr; /* 0x.0098 - Exception reset control register */ 88 u32 autorstsr; /* 0x.009c - Automatic reset status register */ 89 u32 pvr; /* 0x.00a0 - Processor Version Register */ 90 u32 svr; /* 0x.00a4 - System Version Register */ 91 u8 res0a8[0xb0 - 0xa8]; 92 u32 rstcr; /* 0x.00b0 - Reset Control Register */ 93 u8 res0b4[0xc0 - 0xb4]; 94 u32 iovselsr; /* 0x.00c0 - I/O voltage select status register 95 Called 'elbcvselcr' on 86xx SOCs */ 96 u8 res0c4[0x100 - 0xc4]; 97 u32 rcwsr[16]; /* 0x.0100 - Reset Control Word Status registers 98 There are 16 registers */ 99 u8 res140[0x224 - 0x140]; 100 u32 iodelay1; /* 0x.0224 - IO delay control register 1 */ 101 u32 iodelay2; /* 0x.0228 - IO delay control register 2 */ 102 u8 res22c[0x604 - 0x22c]; 103 u32 pamubypenr; /* 0x.604 - PAMU bypass enable register */ 104 u8 res608[0x800 - 0x608]; 105 u32 clkdvdr; /* 0x.0800 - Clock Divide Register */ 106 u8 res804[0x900 - 0x804]; 107 u32 ircr; /* 0x.0900 - Infrared Control Register */ 108 u8 res904[0x908 - 0x904]; 109 u32 dmacr; /* 0x.0908 - DMA Control Register */ 110 u8 res90c[0x914 - 0x90c]; 111 u32 elbccr; /* 0x.0914 - eLBC Control Register */ 112 u8 res918[0xb20 - 0x918]; 113 u32 ddr1clkdr; /* 0x.0b20 - DDR1 Clock Disable Register */ 114 u32 ddr2clkdr; /* 0x.0b24 - DDR2 Clock Disable Register */ 115 u32 ddrclkdr; /* 0x.0b28 - DDR Clock Disable Register */ 116 u8 resb2c[0xe00 - 0xb2c]; 117 u32 clkocr; /* 0x.0e00 - Clock Out Select Register */ 118 u8 rese04[0xe10 - 0xe04]; 119 u32 ddrdllcr; /* 0x.0e10 - DDR DLL Control Register */ 120 u8 rese14[0xe20 - 0xe14]; 121 u32 lbcdllcr; /* 0x.0e20 - LBC DLL Control Register */ 122 u32 cpfor; /* 0x.0e24 - L2 charge pump fuse override 123 * register 124 */ 125 u8 rese28[0xf04 - 0xe28]; 126 u32 srds1cr0; /* 0x.0f04 - SerDes1 Control Register 0 */ 127 u32 srds1cr1; /* 0x.0f08 - SerDes1 Control Register 0 */ 128 u8 resf0c[0xf2c - 0xf0c]; 129 u32 itcr; /* 0x.0f2c - Internal transaction control 130 * register 131 */ 132 u8 resf30[0xf40 - 0xf30]; 133 u32 srds2cr0; /* 0x.0f40 - SerDes2 Control Register 0 */ 134 u32 srds2cr1; /* 0x.0f44 - SerDes2 Control Register 0 */ 135 } __attribute__ ((packed)); 136 137 u32 fsl_guts_get_svr(void); 138 139 /* Alternate function signal multiplex control */ 140 #define MPC85xx_PMUXCR_QE(x) (0x8000 >> (x)) 141 142 #ifdef CONFIG_PPC_86xx 143 144 #define CCSR_GUTS_DMACR_DEV_SSI 0 /* DMA controller/channel set to SSI */ 145 #define CCSR_GUTS_DMACR_DEV_IR 1 /* DMA controller/channel set to IR */ 146 147 /* 148 * Set the DMACR register in the GUTS 149 * 150 * The DMACR register determines the source of initiated transfers for each 151 * channel on each DMA controller. Rather than have a bunch of repetitive 152 * macros for the bit patterns, we just have a function that calculates 153 * them. 154 * 155 * guts: Pointer to GUTS structure 156 * co: The DMA controller (0 or 1) 157 * ch: The channel on the DMA controller (0, 1, 2, or 3) 158 * device: The device to set as the source (CCSR_GUTS_DMACR_DEV_xx) 159 */ 160 static inline void guts_set_dmacr(struct ccsr_guts __iomem *guts, 161 unsigned int co, unsigned int ch, unsigned int device) 162 { 163 unsigned int shift = 16 + (8 * (1 - co) + 2 * (3 - ch)); 164 165 clrsetbits_be32(&guts->dmacr, 3 << shift, device << shift); 166 } 167 168 #define CCSR_GUTS_PMUXCR_LDPSEL 0x00010000 169 #define CCSR_GUTS_PMUXCR_SSI1_MASK 0x0000C000 /* Bitmask for SSI1 */ 170 #define CCSR_GUTS_PMUXCR_SSI1_LA 0x00000000 /* Latched address */ 171 #define CCSR_GUTS_PMUXCR_SSI1_HI 0x00004000 /* High impedance */ 172 #define CCSR_GUTS_PMUXCR_SSI1_SSI 0x00008000 /* Used for SSI1 */ 173 #define CCSR_GUTS_PMUXCR_SSI2_MASK 0x00003000 /* Bitmask for SSI2 */ 174 #define CCSR_GUTS_PMUXCR_SSI2_LA 0x00000000 /* Latched address */ 175 #define CCSR_GUTS_PMUXCR_SSI2_HI 0x00001000 /* High impedance */ 176 #define CCSR_GUTS_PMUXCR_SSI2_SSI 0x00002000 /* Used for SSI2 */ 177 #define CCSR_GUTS_PMUXCR_LA_22_25_LA 0x00000000 /* Latched Address */ 178 #define CCSR_GUTS_PMUXCR_LA_22_25_HI 0x00000400 /* High impedance */ 179 #define CCSR_GUTS_PMUXCR_DBGDRV 0x00000200 /* Signals not driven */ 180 #define CCSR_GUTS_PMUXCR_DMA2_0 0x00000008 181 #define CCSR_GUTS_PMUXCR_DMA2_3 0x00000004 182 #define CCSR_GUTS_PMUXCR_DMA1_0 0x00000002 183 #define CCSR_GUTS_PMUXCR_DMA1_3 0x00000001 184 185 /* 186 * Set the DMA external control bits in the GUTS 187 * 188 * The DMA external control bits in the PMUXCR are only meaningful for 189 * channels 0 and 3. Any other channels are ignored. 190 * 191 * guts: Pointer to GUTS structure 192 * co: The DMA controller (0 or 1) 193 * ch: The channel on the DMA controller (0, 1, 2, or 3) 194 * value: the new value for the bit (0 or 1) 195 */ 196 static inline void guts_set_pmuxcr_dma(struct ccsr_guts __iomem *guts, 197 unsigned int co, unsigned int ch, unsigned int value) 198 { 199 if ((ch == 0) || (ch == 3)) { 200 unsigned int shift = 2 * (co + 1) - (ch & 1) - 1; 201 202 clrsetbits_be32(&guts->pmuxcr, 1 << shift, value << shift); 203 } 204 } 205 206 #define CCSR_GUTS_CLKDVDR_PXCKEN 0x80000000 207 #define CCSR_GUTS_CLKDVDR_SSICKEN 0x20000000 208 #define CCSR_GUTS_CLKDVDR_PXCKINV 0x10000000 209 #define CCSR_GUTS_CLKDVDR_PXCKDLY_SHIFT 25 210 #define CCSR_GUTS_CLKDVDR_PXCKDLY_MASK 0x06000000 211 #define CCSR_GUTS_CLKDVDR_PXCKDLY(x) \ 212 (((x) & 3) << CCSR_GUTS_CLKDVDR_PXCKDLY_SHIFT) 213 #define CCSR_GUTS_CLKDVDR_PXCLK_SHIFT 16 214 #define CCSR_GUTS_CLKDVDR_PXCLK_MASK 0x001F0000 215 #define CCSR_GUTS_CLKDVDR_PXCLK(x) (((x) & 31) << CCSR_GUTS_CLKDVDR_PXCLK_SHIFT) 216 #define CCSR_GUTS_CLKDVDR_SSICLK_MASK 0x000000FF 217 #define CCSR_GUTS_CLKDVDR_SSICLK(x) ((x) & CCSR_GUTS_CLKDVDR_SSICLK_MASK) 218 219 #endif 220 221 struct ccsr_rcpm_v1 { 222 u8 res0000[4]; 223 __be32 cdozsr; /* 0x0004 Core Doze Status Register */ 224 u8 res0008[4]; 225 __be32 cdozcr; /* 0x000c Core Doze Control Register */ 226 u8 res0010[4]; 227 __be32 cnapsr; /* 0x0014 Core Nap Status Register */ 228 u8 res0018[4]; 229 __be32 cnapcr; /* 0x001c Core Nap Control Register */ 230 u8 res0020[4]; 231 __be32 cdozpsr; /* 0x0024 Core Doze Previous Status Register */ 232 u8 res0028[4]; 233 __be32 cnappsr; /* 0x002c Core Nap Previous Status Register */ 234 u8 res0030[4]; 235 __be32 cwaitsr; /* 0x0034 Core Wait Status Register */ 236 u8 res0038[4]; 237 __be32 cwdtdsr; /* 0x003c Core Watchdog Detect Status Register */ 238 __be32 powmgtcsr; /* 0x0040 PM Control&Status Register */ 239 #define RCPM_POWMGTCSR_SLP 0x00020000 240 u8 res0044[12]; 241 __be32 ippdexpcr; /* 0x0050 IP Powerdown Exception Control Register */ 242 u8 res0054[16]; 243 __be32 cpmimr; /* 0x0064 Core PM IRQ Mask Register */ 244 u8 res0068[4]; 245 __be32 cpmcimr; /* 0x006c Core PM Critical IRQ Mask Register */ 246 u8 res0070[4]; 247 __be32 cpmmcmr; /* 0x0074 Core PM Machine Check Mask Register */ 248 u8 res0078[4]; 249 __be32 cpmnmimr; /* 0x007c Core PM NMI Mask Register */ 250 u8 res0080[4]; 251 __be32 ctbenr; /* 0x0084 Core Time Base Enable Register */ 252 u8 res0088[4]; 253 __be32 ctbckselr; /* 0x008c Core Time Base Clock Select Register */ 254 u8 res0090[4]; 255 __be32 ctbhltcr; /* 0x0094 Core Time Base Halt Control Register */ 256 u8 res0098[4]; 257 __be32 cmcpmaskcr; /* 0x00a4 Core Machine Check Mask Register */ 258 }; 259 260 struct ccsr_rcpm_v2 { 261 u8 res_00[12]; 262 __be32 tph10sr0; /* Thread PH10 Status Register */ 263 u8 res_10[12]; 264 __be32 tph10setr0; /* Thread PH10 Set Control Register */ 265 u8 res_20[12]; 266 __be32 tph10clrr0; /* Thread PH10 Clear Control Register */ 267 u8 res_30[12]; 268 __be32 tph10psr0; /* Thread PH10 Previous Status Register */ 269 u8 res_40[12]; 270 __be32 twaitsr0; /* Thread Wait Status Register */ 271 u8 res_50[96]; 272 __be32 pcph15sr; /* Physical Core PH15 Status Register */ 273 __be32 pcph15setr; /* Physical Core PH15 Set Control Register */ 274 __be32 pcph15clrr; /* Physical Core PH15 Clear Control Register */ 275 __be32 pcph15psr; /* Physical Core PH15 Prev Status Register */ 276 u8 res_c0[16]; 277 __be32 pcph20sr; /* Physical Core PH20 Status Register */ 278 __be32 pcph20setr; /* Physical Core PH20 Set Control Register */ 279 __be32 pcph20clrr; /* Physical Core PH20 Clear Control Register */ 280 __be32 pcph20psr; /* Physical Core PH20 Prev Status Register */ 281 __be32 pcpw20sr; /* Physical Core PW20 Status Register */ 282 u8 res_e0[12]; 283 __be32 pcph30sr; /* Physical Core PH30 Status Register */ 284 __be32 pcph30setr; /* Physical Core PH30 Set Control Register */ 285 __be32 pcph30clrr; /* Physical Core PH30 Clear Control Register */ 286 __be32 pcph30psr; /* Physical Core PH30 Prev Status Register */ 287 u8 res_100[32]; 288 __be32 ippwrgatecr; /* IP Power Gating Control Register */ 289 u8 res_124[12]; 290 __be32 powmgtcsr; /* Power Management Control & Status Reg */ 291 #define RCPM_POWMGTCSR_LPM20_RQ 0x00100000 292 #define RCPM_POWMGTCSR_LPM20_ST 0x00000200 293 #define RCPM_POWMGTCSR_P_LPM20_ST 0x00000100 294 u8 res_134[12]; 295 __be32 ippdexpcr[4]; /* IP Powerdown Exception Control Reg */ 296 u8 res_150[12]; 297 __be32 tpmimr0; /* Thread PM Interrupt Mask Reg */ 298 u8 res_160[12]; 299 __be32 tpmcimr0; /* Thread PM Crit Interrupt Mask Reg */ 300 u8 res_170[12]; 301 __be32 tpmmcmr0; /* Thread PM Machine Check Interrupt Mask Reg */ 302 u8 res_180[12]; 303 __be32 tpmnmimr0; /* Thread PM NMI Mask Reg */ 304 u8 res_190[12]; 305 __be32 tmcpmaskcr0; /* Thread Machine Check Mask Control Reg */ 306 __be32 pctbenr; /* Physical Core Time Base Enable Reg */ 307 __be32 pctbclkselr; /* Physical Core Time Base Clock Select */ 308 __be32 tbclkdivr; /* Time Base Clock Divider Register */ 309 u8 res_1ac[4]; 310 __be32 ttbhltcr[4]; /* Thread Time Base Halt Control Register */ 311 __be32 clpcl10sr; /* Cluster PCL10 Status Register */ 312 __be32 clpcl10setr; /* Cluster PCL30 Set Control Register */ 313 __be32 clpcl10clrr; /* Cluster PCL30 Clear Control Register */ 314 __be32 clpcl10psr; /* Cluster PCL30 Prev Status Register */ 315 __be32 cddslpsetr; /* Core Domain Deep Sleep Set Register */ 316 __be32 cddslpclrr; /* Core Domain Deep Sleep Clear Register */ 317 __be32 cdpwroksetr; /* Core Domain Power OK Set Register */ 318 __be32 cdpwrokclrr; /* Core Domain Power OK Clear Register */ 319 __be32 cdpwrensr; /* Core Domain Power Enable Status Register */ 320 __be32 cddslsr; /* Core Domain Deep Sleep Status Register */ 321 u8 res_1e8[8]; 322 __be32 dslpcntcr[8]; /* Deep Sleep Counter Cfg Register */ 323 u8 res_300[3568]; 324 }; 325 326 #endif 327