1 /* SPDX-License-Identifier: GPL-2.0-or-later */ 2 /* 3 * Freecale 85xx and 86xx Global Utilties register set 4 * 5 * Authors: Jeff Brown 6 * Timur Tabi <timur@freescale.com> 7 * 8 * Copyright 2004,2007,2012 Freescale Semiconductor, Inc 9 */ 10 11 #ifndef __FSL_GUTS_H__ 12 #define __FSL_GUTS_H__ 13 14 #include <linux/types.h> 15 #include <linux/io.h> 16 #include <soc/fsl/phy-fsl-lynx.h> 17 18 /* 19 * Global Utility Registers. 20 * 21 * Not all registers defined in this structure are available on all chips, so 22 * you are expected to know whether a given register actually exists on your 23 * chip before you access it. 24 * 25 * Also, some registers are similar on different chips but have slightly 26 * different names. In these cases, one name is chosen to avoid extraneous 27 * #ifdefs. 28 */ 29 struct ccsr_guts { 30 u32 porpllsr; /* 0x.0000 - POR PLL Ratio Status Register */ 31 u32 porbmsr; /* 0x.0004 - POR Boot Mode Status Register */ 32 u32 porimpscr; /* 0x.0008 - POR I/O Impedance Status and 33 * Control Register 34 */ 35 u32 pordevsr; /* 0x.000c - POR I/O Device Status Register */ 36 u32 pordbgmsr; /* 0x.0010 - POR Debug Mode Status Register */ 37 u32 pordevsr2; /* 0x.0014 - POR device status register 2 */ 38 u8 res018[0x20 - 0x18]; 39 u32 porcir; /* 0x.0020 - POR Configuration Information 40 * Register 41 */ 42 u8 res024[0x30 - 0x24]; 43 u32 gpiocr; /* 0x.0030 - GPIO Control Register */ 44 u8 res034[0x40 - 0x34]; 45 u32 gpoutdr; /* 0x.0040 - General-Purpose Output Data 46 * Register 47 */ 48 u8 res044[0x50 - 0x44]; 49 u32 gpindr; /* 0x.0050 - General-Purpose Input Data 50 * Register 51 */ 52 u8 res054[0x60 - 0x54]; 53 u32 pmuxcr; /* 0x.0060 - Alternate Function Signal 54 * Multiplex Control 55 */ 56 u32 pmuxcr2; /* 0x.0064 - Alternate function signal 57 * multiplex control 2 58 */ 59 u32 dmuxcr; /* 0x.0068 - DMA Mux Control Register */ 60 u8 res06c[0x70 - 0x6c]; 61 u32 devdisr; /* 0x.0070 - Device Disable Control */ 62 #define CCSR_GUTS_DEVDISR_TB1 0x00001000 63 #define CCSR_GUTS_DEVDISR_TB0 0x00004000 64 u32 devdisr2; /* 0x.0074 - Device Disable Control 2 */ 65 u8 res078[0x7c - 0x78]; 66 u32 pmjcr; /* 0x.007c - 4 Power Management Jog Control 67 * Register 68 */ 69 u32 powmgtcsr; /* 0x.0080 - Power Management Status and 70 * Control Register 71 */ 72 u32 pmrccr; /* 0x.0084 - Power Management Reset Counter 73 * Configuration Register 74 */ 75 u32 pmpdccr; /* 0x.0088 - Power Management Power Down Counter 76 * Configuration Register 77 */ 78 u32 pmcdr; /* 0x.008c - 4Power management clock disable 79 * register 80 */ 81 u32 mcpsumr; /* 0x.0090 - Machine Check Summary Register */ 82 u32 rstrscr; /* 0x.0094 - Reset Request Status and 83 * Control Register 84 */ 85 u32 ectrstcr; /* 0x.0098 - Exception reset control register */ 86 u32 autorstsr; /* 0x.009c - Automatic reset status register */ 87 u32 pvr; /* 0x.00a0 - Processor Version Register */ 88 u32 svr; /* 0x.00a4 - System Version Register */ 89 u8 res0a8[0xb0 - 0xa8]; 90 u32 rstcr; /* 0x.00b0 - Reset Control Register */ 91 u8 res0b4[0xc0 - 0xb4]; 92 u32 iovselsr; /* 0x.00c0 - I/O voltage select status register 93 Called 'elbcvselcr' on 86xx SOCs */ 94 u8 res0c4[0x100 - 0xc4]; 95 /* 0x.0100 - read-only Reset Configuration Word Status registers in 96 * CCSR, or write-only Reset Configuration Word Control registers in 97 * DCSR. In both cases there are 32 registers. 98 */ 99 union { 100 u32 rcwsr[32]; 101 u32 rcwcr[32]; 102 }; 103 u8 res180[0x224 - 0x180]; 104 u32 iodelay1; /* 0x.0224 - IO delay control register 1 */ 105 u32 iodelay2; /* 0x.0228 - IO delay control register 2 */ 106 u8 res22c[0x604 - 0x22c]; 107 u32 pamubypenr; /* 0x.604 - PAMU bypass enable register */ 108 u8 res608[0x800 - 0x608]; 109 u32 clkdvdr; /* 0x.0800 - Clock Divide Register */ 110 u8 res804[0x900 - 0x804]; 111 u32 ircr; /* 0x.0900 - Infrared Control Register */ 112 u8 res904[0x908 - 0x904]; 113 u32 dmacr; /* 0x.0908 - DMA Control Register */ 114 u8 res90c[0x914 - 0x90c]; 115 u32 elbccr; /* 0x.0914 - eLBC Control Register */ 116 u8 res918[0xb20 - 0x918]; 117 u32 ddr1clkdr; /* 0x.0b20 - DDR1 Clock Disable Register */ 118 u32 ddr2clkdr; /* 0x.0b24 - DDR2 Clock Disable Register */ 119 u32 ddrclkdr; /* 0x.0b28 - DDR Clock Disable Register */ 120 u8 resb2c[0xe00 - 0xb2c]; 121 u32 clkocr; /* 0x.0e00 - Clock Out Select Register */ 122 u8 rese04[0xe10 - 0xe04]; 123 u32 ddrdllcr; /* 0x.0e10 - DDR DLL Control Register */ 124 u8 rese14[0xe20 - 0xe14]; 125 u32 lbcdllcr; /* 0x.0e20 - LBC DLL Control Register */ 126 u32 cpfor; /* 0x.0e24 - L2 charge pump fuse override 127 * register 128 */ 129 u8 rese28[0xf04 - 0xe28]; 130 u32 srds1cr0; /* 0x.0f04 - SerDes1 Control Register 0 */ 131 u32 srds1cr1; /* 0x.0f08 - SerDes1 Control Register 0 */ 132 u8 resf0c[0xf2c - 0xf0c]; 133 u32 itcr; /* 0x.0f2c - Internal transaction control 134 * register 135 */ 136 u8 resf30[0xf40 - 0xf30]; 137 u32 srds2cr0; /* 0x.0f40 - SerDes2 Control Register 0 */ 138 u32 srds2cr1; /* 0x.0f44 - SerDes2 Control Register 0 */ 139 } __attribute__ ((packed)); 140 141 int fsl_guts_lane_validate(int serdes_idx, int lane, 142 enum lynx_lane_mode lane_mode); 143 int fsl_guts_lane_set_mode(int serdes_idx, int lane, 144 enum lynx_lane_mode lane_mode); 145 146 /* Alternate function signal multiplex control */ 147 #define MPC85xx_PMUXCR_QE(x) (0x8000 >> (x)) 148 149 #ifdef CONFIG_PPC_86xx 150 151 #define CCSR_GUTS_DMACR_DEV_SSI 0 /* DMA controller/channel set to SSI */ 152 #define CCSR_GUTS_DMACR_DEV_IR 1 /* DMA controller/channel set to IR */ 153 154 /* 155 * Set the DMACR register in the GUTS 156 * 157 * The DMACR register determines the source of initiated transfers for each 158 * channel on each DMA controller. Rather than have a bunch of repetitive 159 * macros for the bit patterns, we just have a function that calculates 160 * them. 161 * 162 * guts: Pointer to GUTS structure 163 * co: The DMA controller (0 or 1) 164 * ch: The channel on the DMA controller (0, 1, 2, or 3) 165 * device: The device to set as the source (CCSR_GUTS_DMACR_DEV_xx) 166 */ 167 static inline void guts_set_dmacr(struct ccsr_guts __iomem *guts, 168 unsigned int co, unsigned int ch, unsigned int device) 169 { 170 unsigned int shift = 16 + (8 * (1 - co) + 2 * (3 - ch)); 171 172 clrsetbits_be32(&guts->dmacr, 3 << shift, device << shift); 173 } 174 175 #define CCSR_GUTS_PMUXCR_LDPSEL 0x00010000 176 #define CCSR_GUTS_PMUXCR_SSI1_MASK 0x0000C000 /* Bitmask for SSI1 */ 177 #define CCSR_GUTS_PMUXCR_SSI1_LA 0x00000000 /* Latched address */ 178 #define CCSR_GUTS_PMUXCR_SSI1_HI 0x00004000 /* High impedance */ 179 #define CCSR_GUTS_PMUXCR_SSI1_SSI 0x00008000 /* Used for SSI1 */ 180 #define CCSR_GUTS_PMUXCR_SSI2_MASK 0x00003000 /* Bitmask for SSI2 */ 181 #define CCSR_GUTS_PMUXCR_SSI2_LA 0x00000000 /* Latched address */ 182 #define CCSR_GUTS_PMUXCR_SSI2_HI 0x00001000 /* High impedance */ 183 #define CCSR_GUTS_PMUXCR_SSI2_SSI 0x00002000 /* Used for SSI2 */ 184 #define CCSR_GUTS_PMUXCR_LA_22_25_LA 0x00000000 /* Latched Address */ 185 #define CCSR_GUTS_PMUXCR_LA_22_25_HI 0x00000400 /* High impedance */ 186 #define CCSR_GUTS_PMUXCR_DBGDRV 0x00000200 /* Signals not driven */ 187 #define CCSR_GUTS_PMUXCR_DMA2_0 0x00000008 188 #define CCSR_GUTS_PMUXCR_DMA2_3 0x00000004 189 #define CCSR_GUTS_PMUXCR_DMA1_0 0x00000002 190 #define CCSR_GUTS_PMUXCR_DMA1_3 0x00000001 191 192 /* 193 * Set the DMA external control bits in the GUTS 194 * 195 * The DMA external control bits in the PMUXCR are only meaningful for 196 * channels 0 and 3. Any other channels are ignored. 197 * 198 * guts: Pointer to GUTS structure 199 * co: The DMA controller (0 or 1) 200 * ch: The channel on the DMA controller (0, 1, 2, or 3) 201 * value: the new value for the bit (0 or 1) 202 */ 203 static inline void guts_set_pmuxcr_dma(struct ccsr_guts __iomem *guts, 204 unsigned int co, unsigned int ch, unsigned int value) 205 { 206 if ((ch == 0) || (ch == 3)) { 207 unsigned int shift = 2 * (co + 1) - (ch & 1) - 1; 208 209 clrsetbits_be32(&guts->pmuxcr, 1 << shift, value << shift); 210 } 211 } 212 213 #define CCSR_GUTS_CLKDVDR_PXCKEN 0x80000000 214 #define CCSR_GUTS_CLKDVDR_SSICKEN 0x20000000 215 #define CCSR_GUTS_CLKDVDR_PXCKINV 0x10000000 216 #define CCSR_GUTS_CLKDVDR_PXCKDLY_SHIFT 25 217 #define CCSR_GUTS_CLKDVDR_PXCKDLY_MASK 0x06000000 218 #define CCSR_GUTS_CLKDVDR_PXCKDLY(x) \ 219 (((x) & 3) << CCSR_GUTS_CLKDVDR_PXCKDLY_SHIFT) 220 #define CCSR_GUTS_CLKDVDR_PXCLK_SHIFT 16 221 #define CCSR_GUTS_CLKDVDR_PXCLK_MASK 0x001F0000 222 #define CCSR_GUTS_CLKDVDR_PXCLK(x) (((x) & 31) << CCSR_GUTS_CLKDVDR_PXCLK_SHIFT) 223 #define CCSR_GUTS_CLKDVDR_SSICLK_MASK 0x000000FF 224 #define CCSR_GUTS_CLKDVDR_SSICLK(x) ((x) & CCSR_GUTS_CLKDVDR_SSICLK_MASK) 225 226 #endif 227 228 struct ccsr_rcpm_v1 { 229 u8 res0000[4]; 230 __be32 cdozsr; /* 0x0004 Core Doze Status Register */ 231 u8 res0008[4]; 232 __be32 cdozcr; /* 0x000c Core Doze Control Register */ 233 u8 res0010[4]; 234 __be32 cnapsr; /* 0x0014 Core Nap Status Register */ 235 u8 res0018[4]; 236 __be32 cnapcr; /* 0x001c Core Nap Control Register */ 237 u8 res0020[4]; 238 __be32 cdozpsr; /* 0x0024 Core Doze Previous Status Register */ 239 u8 res0028[4]; 240 __be32 cnappsr; /* 0x002c Core Nap Previous Status Register */ 241 u8 res0030[4]; 242 __be32 cwaitsr; /* 0x0034 Core Wait Status Register */ 243 u8 res0038[4]; 244 __be32 cwdtdsr; /* 0x003c Core Watchdog Detect Status Register */ 245 __be32 powmgtcsr; /* 0x0040 PM Control&Status Register */ 246 #define RCPM_POWMGTCSR_SLP 0x00020000 247 u8 res0044[12]; 248 __be32 ippdexpcr; /* 0x0050 IP Powerdown Exception Control Register */ 249 u8 res0054[16]; 250 __be32 cpmimr; /* 0x0064 Core PM IRQ Mask Register */ 251 u8 res0068[4]; 252 __be32 cpmcimr; /* 0x006c Core PM Critical IRQ Mask Register */ 253 u8 res0070[4]; 254 __be32 cpmmcmr; /* 0x0074 Core PM Machine Check Mask Register */ 255 u8 res0078[4]; 256 __be32 cpmnmimr; /* 0x007c Core PM NMI Mask Register */ 257 u8 res0080[4]; 258 __be32 ctbenr; /* 0x0084 Core Time Base Enable Register */ 259 u8 res0088[4]; 260 __be32 ctbckselr; /* 0x008c Core Time Base Clock Select Register */ 261 u8 res0090[4]; 262 __be32 ctbhltcr; /* 0x0094 Core Time Base Halt Control Register */ 263 u8 res0098[4]; 264 __be32 cmcpmaskcr; /* 0x00a4 Core Machine Check Mask Register */ 265 }; 266 267 struct ccsr_rcpm_v2 { 268 u8 res_00[12]; 269 __be32 tph10sr0; /* Thread PH10 Status Register */ 270 u8 res_10[12]; 271 __be32 tph10setr0; /* Thread PH10 Set Control Register */ 272 u8 res_20[12]; 273 __be32 tph10clrr0; /* Thread PH10 Clear Control Register */ 274 u8 res_30[12]; 275 __be32 tph10psr0; /* Thread PH10 Previous Status Register */ 276 u8 res_40[12]; 277 __be32 twaitsr0; /* Thread Wait Status Register */ 278 u8 res_50[96]; 279 __be32 pcph15sr; /* Physical Core PH15 Status Register */ 280 __be32 pcph15setr; /* Physical Core PH15 Set Control Register */ 281 __be32 pcph15clrr; /* Physical Core PH15 Clear Control Register */ 282 __be32 pcph15psr; /* Physical Core PH15 Prev Status Register */ 283 u8 res_c0[16]; 284 __be32 pcph20sr; /* Physical Core PH20 Status Register */ 285 __be32 pcph20setr; /* Physical Core PH20 Set Control Register */ 286 __be32 pcph20clrr; /* Physical Core PH20 Clear Control Register */ 287 __be32 pcph20psr; /* Physical Core PH20 Prev Status Register */ 288 __be32 pcpw20sr; /* Physical Core PW20 Status Register */ 289 u8 res_e0[12]; 290 __be32 pcph30sr; /* Physical Core PH30 Status Register */ 291 __be32 pcph30setr; /* Physical Core PH30 Set Control Register */ 292 __be32 pcph30clrr; /* Physical Core PH30 Clear Control Register */ 293 __be32 pcph30psr; /* Physical Core PH30 Prev Status Register */ 294 u8 res_100[32]; 295 __be32 ippwrgatecr; /* IP Power Gating Control Register */ 296 u8 res_124[12]; 297 __be32 powmgtcsr; /* Power Management Control & Status Reg */ 298 #define RCPM_POWMGTCSR_LPM20_RQ 0x00100000 299 #define RCPM_POWMGTCSR_LPM20_ST 0x00000200 300 #define RCPM_POWMGTCSR_P_LPM20_ST 0x00000100 301 u8 res_134[12]; 302 __be32 ippdexpcr[4]; /* IP Powerdown Exception Control Reg */ 303 u8 res_150[12]; 304 __be32 tpmimr0; /* Thread PM Interrupt Mask Reg */ 305 u8 res_160[12]; 306 __be32 tpmcimr0; /* Thread PM Crit Interrupt Mask Reg */ 307 u8 res_170[12]; 308 __be32 tpmmcmr0; /* Thread PM Machine Check Interrupt Mask Reg */ 309 u8 res_180[12]; 310 __be32 tpmnmimr0; /* Thread PM NMI Mask Reg */ 311 u8 res_190[12]; 312 __be32 tmcpmaskcr0; /* Thread Machine Check Mask Control Reg */ 313 __be32 pctbenr; /* Physical Core Time Base Enable Reg */ 314 __be32 pctbclkselr; /* Physical Core Time Base Clock Select */ 315 __be32 tbclkdivr; /* Time Base Clock Divider Register */ 316 u8 res_1ac[4]; 317 __be32 ttbhltcr[4]; /* Thread Time Base Halt Control Register */ 318 __be32 clpcl10sr; /* Cluster PCL10 Status Register */ 319 __be32 clpcl10setr; /* Cluster PCL30 Set Control Register */ 320 __be32 clpcl10clrr; /* Cluster PCL30 Clear Control Register */ 321 __be32 clpcl10psr; /* Cluster PCL30 Prev Status Register */ 322 __be32 cddslpsetr; /* Core Domain Deep Sleep Set Register */ 323 __be32 cddslpclrr; /* Core Domain Deep Sleep Clear Register */ 324 __be32 cdpwroksetr; /* Core Domain Power OK Set Register */ 325 __be32 cdpwrokclrr; /* Core Domain Power OK Clear Register */ 326 __be32 cdpwrensr; /* Core Domain Power Enable Status Register */ 327 __be32 cddslsr; /* Core Domain Deep Sleep Status Register */ 328 u8 res_1e8[8]; 329 __be32 dslpcntcr[8]; /* Deep Sleep Counter Cfg Register */ 330 u8 res_300[3568]; 331 }; 332 333 #endif 334