1*d27ac2e0SAlexandru Ardelean /* SPDX-License-Identifier: GPL-2.0 */ 2*d27ac2e0SAlexandru Ardelean /* 3*d27ac2e0SAlexandru Ardelean * Analog Devices AXI common registers & definitions 4*d27ac2e0SAlexandru Ardelean * 5*d27ac2e0SAlexandru Ardelean * Copyright 2019 Analog Devices Inc. 6*d27ac2e0SAlexandru Ardelean * 7*d27ac2e0SAlexandru Ardelean * https://wiki.analog.com/resources/fpga/docs/axi_ip 8*d27ac2e0SAlexandru Ardelean * https://wiki.analog.com/resources/fpga/docs/hdl/regmap 9*d27ac2e0SAlexandru Ardelean */ 10*d27ac2e0SAlexandru Ardelean 11*d27ac2e0SAlexandru Ardelean #ifndef ADI_AXI_COMMON_H_ 12*d27ac2e0SAlexandru Ardelean #define ADI_AXI_COMMON_H_ 13*d27ac2e0SAlexandru Ardelean 14*d27ac2e0SAlexandru Ardelean #define ADI_AXI_REG_VERSION 0x0000 15*d27ac2e0SAlexandru Ardelean 16*d27ac2e0SAlexandru Ardelean #define ADI_AXI_PCORE_VER(major, minor, patch) \ 17*d27ac2e0SAlexandru Ardelean (((major) << 16) | ((minor) << 8) | (patch)) 18*d27ac2e0SAlexandru Ardelean 19*d27ac2e0SAlexandru Ardelean #endif /* ADI_AXI_COMMON_H_ */ 20