1 /* SPDX-License-Identifier: GPL-2.0 */ 2 /* 3 * Copyright (c) 2012, The Linux Foundation. All rights reserved. 4 */ 5 6 #ifndef _LINUX_CORESIGHT_H 7 #define _LINUX_CORESIGHT_H 8 9 #include <linux/amba/bus.h> 10 #include <linux/clk.h> 11 #include <linux/device.h> 12 #include <linux/io.h> 13 #include <linux/perf_event.h> 14 #include <linux/sched.h> 15 16 /* Peripheral id registers (0xFD0-0xFEC) */ 17 #define CORESIGHT_PERIPHIDR4 0xfd0 18 #define CORESIGHT_PERIPHIDR5 0xfd4 19 #define CORESIGHT_PERIPHIDR6 0xfd8 20 #define CORESIGHT_PERIPHIDR7 0xfdC 21 #define CORESIGHT_PERIPHIDR0 0xfe0 22 #define CORESIGHT_PERIPHIDR1 0xfe4 23 #define CORESIGHT_PERIPHIDR2 0xfe8 24 #define CORESIGHT_PERIPHIDR3 0xfeC 25 /* Component id registers (0xFF0-0xFFC) */ 26 #define CORESIGHT_COMPIDR0 0xff0 27 #define CORESIGHT_COMPIDR1 0xff4 28 #define CORESIGHT_COMPIDR2 0xff8 29 #define CORESIGHT_COMPIDR3 0xffC 30 31 #define ETM_ARCH_V3_3 0x23 32 #define ETM_ARCH_V3_5 0x25 33 #define PFT_ARCH_V1_0 0x30 34 #define PFT_ARCH_V1_1 0x31 35 36 #define CORESIGHT_UNLOCK 0xc5acce55 37 38 extern struct bus_type coresight_bustype; 39 40 enum coresight_dev_type { 41 CORESIGHT_DEV_TYPE_SINK, 42 CORESIGHT_DEV_TYPE_LINK, 43 CORESIGHT_DEV_TYPE_LINKSINK, 44 CORESIGHT_DEV_TYPE_SOURCE, 45 CORESIGHT_DEV_TYPE_HELPER, 46 CORESIGHT_DEV_TYPE_MAX 47 }; 48 49 enum coresight_dev_subtype_sink { 50 CORESIGHT_DEV_SUBTYPE_SINK_DUMMY, 51 CORESIGHT_DEV_SUBTYPE_SINK_PORT, 52 CORESIGHT_DEV_SUBTYPE_SINK_BUFFER, 53 CORESIGHT_DEV_SUBTYPE_SINK_SYSMEM, 54 CORESIGHT_DEV_SUBTYPE_SINK_PERCPU_SYSMEM, 55 }; 56 57 enum coresight_dev_subtype_link { 58 CORESIGHT_DEV_SUBTYPE_LINK_MERG, 59 CORESIGHT_DEV_SUBTYPE_LINK_SPLIT, 60 CORESIGHT_DEV_SUBTYPE_LINK_FIFO, 61 }; 62 63 enum coresight_dev_subtype_source { 64 CORESIGHT_DEV_SUBTYPE_SOURCE_PROC, 65 CORESIGHT_DEV_SUBTYPE_SOURCE_BUS, 66 CORESIGHT_DEV_SUBTYPE_SOURCE_SOFTWARE, 67 CORESIGHT_DEV_SUBTYPE_SOURCE_TPDM, 68 CORESIGHT_DEV_SUBTYPE_SOURCE_OTHERS, 69 }; 70 71 enum coresight_dev_subtype_helper { 72 CORESIGHT_DEV_SUBTYPE_HELPER_CATU, 73 CORESIGHT_DEV_SUBTYPE_HELPER_ECT_CTI 74 }; 75 76 /** 77 * union coresight_dev_subtype - further characterisation of a type 78 * @sink_subtype: type of sink this component is, as defined 79 * by @coresight_dev_subtype_sink. 80 * @link_subtype: type of link this component is, as defined 81 * by @coresight_dev_subtype_link. 82 * @source_subtype: type of source this component is, as defined 83 * by @coresight_dev_subtype_source. 84 * @helper_subtype: type of helper this component is, as defined 85 * by @coresight_dev_subtype_helper. 86 */ 87 union coresight_dev_subtype { 88 /* We have some devices which acts as LINK and SINK */ 89 struct { 90 enum coresight_dev_subtype_sink sink_subtype; 91 enum coresight_dev_subtype_link link_subtype; 92 }; 93 enum coresight_dev_subtype_source source_subtype; 94 enum coresight_dev_subtype_helper helper_subtype; 95 }; 96 97 /** 98 * struct coresight_platform_data - data harvested from the firmware 99 * specification. 100 * 101 * @nr_inconns: Number of elements for the input connections. 102 * @nr_outconns: Number of elements for the output connections. 103 * @out_conns: Array of nr_outconns pointers to connections from this 104 * component. 105 * @in_conns: Sparse array of pointers to input connections. Sparse 106 * because the source device owns the connection so when it's 107 * unloaded the connection leaves an empty slot. 108 */ 109 struct coresight_platform_data { 110 int nr_inconns; 111 int nr_outconns; 112 struct coresight_connection **out_conns; 113 struct coresight_connection **in_conns; 114 }; 115 116 /** 117 * struct csdev_access - Abstraction of a CoreSight device access. 118 * 119 * @io_mem : True if the device has memory mapped I/O 120 * @base : When io_mem == true, base address of the component 121 * @read : Read from the given "offset" of the given instance. 122 * @write : Write "val" to the given "offset". 123 */ 124 struct csdev_access { 125 bool io_mem; 126 union { 127 void __iomem *base; 128 struct { 129 u64 (*read)(u32 offset, bool relaxed, bool _64bit); 130 void (*write)(u64 val, u32 offset, bool relaxed, 131 bool _64bit); 132 }; 133 }; 134 }; 135 136 #define CSDEV_ACCESS_IOMEM(_addr) \ 137 ((struct csdev_access) { \ 138 .io_mem = true, \ 139 .base = (_addr), \ 140 }) 141 142 /** 143 * struct coresight_desc - description of a component required from drivers 144 * @type: as defined by @coresight_dev_type. 145 * @subtype: as defined by @coresight_dev_subtype. 146 * @ops: generic operations for this component, as defined 147 * by @coresight_ops. 148 * @pdata: platform data collected from DT. 149 * @dev: The device entity associated to this component. 150 * @groups: operations specific to this component. These will end up 151 * in the component's sysfs sub-directory. 152 * @name: name for the coresight device, also shown under sysfs. 153 * @access: Describe access to the device 154 */ 155 struct coresight_desc { 156 enum coresight_dev_type type; 157 union coresight_dev_subtype subtype; 158 const struct coresight_ops *ops; 159 struct coresight_platform_data *pdata; 160 struct device *dev; 161 const struct attribute_group **groups; 162 const char *name; 163 struct csdev_access access; 164 }; 165 166 /** 167 * struct coresight_connection - representation of a single connection 168 * @src_port: a connection's output port number. 169 * @dest_port: destination's input port number @src_port is connected to. 170 * @dest_fwnode: destination component's fwnode handle. 171 * @dest_dev: a @coresight_device representation of the component 172 connected to @src_port. NULL until the device is created 173 * @link: Representation of the connection as a sysfs link. 174 * 175 * The full connection structure looks like this, where in_conns store 176 * references to same connection as the source device's out_conns. 177 * 178 * +-----------------------------+ +-----------------------------+ 179 * |coresight_device | |coresight_connection | 180 * |-----------------------------| |-----------------------------| 181 * | | | | 182 * | | | dest_dev*|<-- 183 * |pdata->out_conns[nr_outconns]|<->|src_dev* | | 184 * | | | | | 185 * +-----------------------------+ +-----------------------------+ | 186 * | 187 * +-----------------------------+ | 188 * |coresight_device | | 189 * |------------------------------ | 190 * | | | 191 * | pdata->in_conns[nr_inconns]|<-- 192 * | | 193 * +-----------------------------+ 194 */ 195 struct coresight_connection { 196 int src_port; 197 int dest_port; 198 struct fwnode_handle *dest_fwnode; 199 struct coresight_device *dest_dev; 200 struct coresight_sysfs_link *link; 201 struct coresight_device *src_dev; 202 atomic_t src_refcnt; 203 atomic_t dest_refcnt; 204 }; 205 206 /** 207 * struct coresight_sysfs_link - representation of a connection in sysfs. 208 * @orig: Originating (master) coresight device for the link. 209 * @orig_name: Name to use for the link orig->target. 210 * @target: Target (slave) coresight device for the link. 211 * @target_name: Name to use for the link target->orig. 212 */ 213 struct coresight_sysfs_link { 214 struct coresight_device *orig; 215 const char *orig_name; 216 struct coresight_device *target; 217 const char *target_name; 218 }; 219 220 /** 221 * struct coresight_device - representation of a device as used by the framework 222 * @pdata: Platform data with device connections associated to this device. 223 * @type: as defined by @coresight_dev_type. 224 * @subtype: as defined by @coresight_dev_subtype. 225 * @ops: generic operations for this component, as defined 226 * by @coresight_ops. 227 * @access: Device i/o access abstraction for this device. 228 * @dev: The device entity associated to this component. 229 * @refcnt: keep track of what is in use. 230 * @orphan: true if the component has connections that haven't been linked. 231 * @enable: 'true' if component is currently part of an active path. 232 * @activated: 'true' only if a _sink_ has been activated. A sink can be 233 * activated but not yet enabled. Enabling for a _sink_ 234 * happens when a source has been selected and a path is enabled 235 * from source to that sink. 236 * @ea: Device attribute for sink representation under PMU directory. 237 * @def_sink: cached reference to default sink found for this device. 238 * @nr_links: number of sysfs links created to other components from this 239 * device. These will appear in the "connections" group. 240 * @has_conns_grp: Have added a "connections" group for sysfs links. 241 * @feature_csdev_list: List of complex feature programming added to the device. 242 * @config_csdev_list: List of system configurations added to the device. 243 * @cscfg_csdev_lock: Protect the lists of configurations and features. 244 * @active_cscfg_ctxt: Context information for current active system configuration. 245 */ 246 struct coresight_device { 247 struct coresight_platform_data *pdata; 248 enum coresight_dev_type type; 249 union coresight_dev_subtype subtype; 250 const struct coresight_ops *ops; 251 struct csdev_access access; 252 struct device dev; 253 atomic_t refcnt; 254 bool orphan; 255 bool enable; /* true only if configured as part of a path */ 256 /* sink specific fields */ 257 bool activated; /* true only if a sink is part of a path */ 258 struct dev_ext_attribute *ea; 259 struct coresight_device *def_sink; 260 /* sysfs links between components */ 261 int nr_links; 262 bool has_conns_grp; 263 /* system configuration and feature lists */ 264 struct list_head feature_csdev_list; 265 struct list_head config_csdev_list; 266 spinlock_t cscfg_csdev_lock; 267 void *active_cscfg_ctxt; 268 }; 269 270 /* 271 * coresight_dev_list - Mapping for devices to "name" index for device 272 * names. 273 * 274 * @nr_idx: Number of entries already allocated. 275 * @pfx: Prefix pattern for device name. 276 * @fwnode_list: Array of fwnode_handles associated with each allocated 277 * index, upto nr_idx entries. 278 */ 279 struct coresight_dev_list { 280 int nr_idx; 281 const char *pfx; 282 struct fwnode_handle **fwnode_list; 283 }; 284 285 #define DEFINE_CORESIGHT_DEVLIST(var, dev_pfx) \ 286 static struct coresight_dev_list (var) = { \ 287 .pfx = dev_pfx, \ 288 .nr_idx = 0, \ 289 .fwnode_list = NULL, \ 290 } 291 292 #define to_coresight_device(d) container_of(d, struct coresight_device, dev) 293 294 enum cs_mode { 295 CS_MODE_DISABLED, 296 CS_MODE_SYSFS, 297 CS_MODE_PERF, 298 }; 299 300 #define source_ops(csdev) csdev->ops->source_ops 301 #define sink_ops(csdev) csdev->ops->sink_ops 302 #define link_ops(csdev) csdev->ops->link_ops 303 #define helper_ops(csdev) csdev->ops->helper_ops 304 #define ect_ops(csdev) csdev->ops->ect_ops 305 306 /** 307 * struct coresight_ops_sink - basic operations for a sink 308 * Operations available for sinks 309 * @enable: enables the sink. 310 * @disable: disables the sink. 311 * @alloc_buffer: initialises perf's ring buffer for trace collection. 312 * @free_buffer: release memory allocated in @get_config. 313 * @update_buffer: update buffer pointers after a trace session. 314 */ 315 struct coresight_ops_sink { 316 int (*enable)(struct coresight_device *csdev, enum cs_mode mode, 317 void *data); 318 int (*disable)(struct coresight_device *csdev); 319 void *(*alloc_buffer)(struct coresight_device *csdev, 320 struct perf_event *event, void **pages, 321 int nr_pages, bool overwrite); 322 void (*free_buffer)(void *config); 323 unsigned long (*update_buffer)(struct coresight_device *csdev, 324 struct perf_output_handle *handle, 325 void *sink_config); 326 }; 327 328 /** 329 * struct coresight_ops_link - basic operations for a link 330 * Operations available for links. 331 * @enable: enables flow between iport and oport. 332 * @disable: disables flow between iport and oport. 333 */ 334 struct coresight_ops_link { 335 int (*enable)(struct coresight_device *csdev, 336 struct coresight_connection *in, 337 struct coresight_connection *out); 338 void (*disable)(struct coresight_device *csdev, 339 struct coresight_connection *in, 340 struct coresight_connection *out); 341 }; 342 343 /** 344 * struct coresight_ops_source - basic operations for a source 345 * Operations available for sources. 346 * @cpu_id: returns the value of the CPU number this component 347 * is associated to. 348 * @enable: enables tracing for a source. 349 * @disable: disables tracing for a source. 350 */ 351 struct coresight_ops_source { 352 int (*cpu_id)(struct coresight_device *csdev); 353 int (*enable)(struct coresight_device *csdev, struct perf_event *event, 354 enum cs_mode mode); 355 void (*disable)(struct coresight_device *csdev, 356 struct perf_event *event); 357 }; 358 359 /** 360 * struct coresight_ops_helper - Operations for a helper device. 361 * 362 * All operations could pass in a device specific data, which could 363 * help the helper device to determine what to do. 364 * 365 * @enable : Enable the device 366 * @disable : Disable the device 367 */ 368 struct coresight_ops_helper { 369 int (*enable)(struct coresight_device *csdev, enum cs_mode mode, 370 void *data); 371 int (*disable)(struct coresight_device *csdev, void *data); 372 }; 373 374 struct coresight_ops { 375 const struct coresight_ops_sink *sink_ops; 376 const struct coresight_ops_link *link_ops; 377 const struct coresight_ops_source *source_ops; 378 const struct coresight_ops_helper *helper_ops; 379 }; 380 381 #if IS_ENABLED(CONFIG_CORESIGHT) 382 383 static inline u32 csdev_access_relaxed_read32(struct csdev_access *csa, 384 u32 offset) 385 { 386 if (likely(csa->io_mem)) 387 return readl_relaxed(csa->base + offset); 388 389 return csa->read(offset, true, false); 390 } 391 392 #define CORESIGHT_CIDRn(i) (0xFF0 + ((i) * 4)) 393 394 static inline u32 coresight_get_cid(void __iomem *base) 395 { 396 u32 i, cid = 0; 397 398 for (i = 0; i < 4; i++) 399 cid |= readl(base + CORESIGHT_CIDRn(i)) << (i * 8); 400 401 return cid; 402 } 403 404 static inline bool is_coresight_device(void __iomem *base) 405 { 406 u32 cid = coresight_get_cid(base); 407 408 return cid == CORESIGHT_CID; 409 } 410 411 /* 412 * Attempt to find and enable "APB clock" for the given device 413 * 414 * Returns: 415 * 416 * clk - Clock is found and enabled 417 * NULL - clock is not found 418 * ERROR - Clock is found but failed to enable 419 */ 420 static inline struct clk *coresight_get_enable_apb_pclk(struct device *dev) 421 { 422 struct clk *pclk; 423 int ret; 424 425 pclk = clk_get(dev, "apb_pclk"); 426 if (IS_ERR(pclk)) 427 return NULL; 428 429 ret = clk_prepare_enable(pclk); 430 if (ret) { 431 clk_put(pclk); 432 return ERR_PTR(ret); 433 } 434 return pclk; 435 } 436 437 #define CORESIGHT_PIDRn(i) (0xFE0 + ((i) * 4)) 438 439 static inline u32 coresight_get_pid(struct csdev_access *csa) 440 { 441 u32 i, pid = 0; 442 443 for (i = 0; i < 4; i++) 444 pid |= csdev_access_relaxed_read32(csa, CORESIGHT_PIDRn(i)) << (i * 8); 445 446 return pid; 447 } 448 449 static inline u64 csdev_access_relaxed_read_pair(struct csdev_access *csa, 450 u32 lo_offset, u32 hi_offset) 451 { 452 if (likely(csa->io_mem)) { 453 return readl_relaxed(csa->base + lo_offset) | 454 ((u64)readl_relaxed(csa->base + hi_offset) << 32); 455 } 456 457 return csa->read(lo_offset, true, false) | (csa->read(hi_offset, true, false) << 32); 458 } 459 460 static inline void csdev_access_relaxed_write_pair(struct csdev_access *csa, u64 val, 461 u32 lo_offset, u32 hi_offset) 462 { 463 if (likely(csa->io_mem)) { 464 writel_relaxed((u32)val, csa->base + lo_offset); 465 writel_relaxed((u32)(val >> 32), csa->base + hi_offset); 466 } else { 467 csa->write((u32)val, lo_offset, true, false); 468 csa->write((u32)(val >> 32), hi_offset, true, false); 469 } 470 } 471 472 static inline u32 csdev_access_read32(struct csdev_access *csa, u32 offset) 473 { 474 if (likely(csa->io_mem)) 475 return readl(csa->base + offset); 476 477 return csa->read(offset, false, false); 478 } 479 480 static inline void csdev_access_relaxed_write32(struct csdev_access *csa, 481 u32 val, u32 offset) 482 { 483 if (likely(csa->io_mem)) 484 writel_relaxed(val, csa->base + offset); 485 else 486 csa->write(val, offset, true, false); 487 } 488 489 static inline void csdev_access_write32(struct csdev_access *csa, u32 val, u32 offset) 490 { 491 if (likely(csa->io_mem)) 492 writel(val, csa->base + offset); 493 else 494 csa->write(val, offset, false, false); 495 } 496 497 #ifdef CONFIG_64BIT 498 499 static inline u64 csdev_access_relaxed_read64(struct csdev_access *csa, 500 u32 offset) 501 { 502 if (likely(csa->io_mem)) 503 return readq_relaxed(csa->base + offset); 504 505 return csa->read(offset, true, true); 506 } 507 508 static inline u64 csdev_access_read64(struct csdev_access *csa, u32 offset) 509 { 510 if (likely(csa->io_mem)) 511 return readq(csa->base + offset); 512 513 return csa->read(offset, false, true); 514 } 515 516 static inline void csdev_access_relaxed_write64(struct csdev_access *csa, 517 u64 val, u32 offset) 518 { 519 if (likely(csa->io_mem)) 520 writeq_relaxed(val, csa->base + offset); 521 else 522 csa->write(val, offset, true, true); 523 } 524 525 static inline void csdev_access_write64(struct csdev_access *csa, u64 val, u32 offset) 526 { 527 if (likely(csa->io_mem)) 528 writeq(val, csa->base + offset); 529 else 530 csa->write(val, offset, false, true); 531 } 532 533 #else /* !CONFIG_64BIT */ 534 535 static inline u64 csdev_access_relaxed_read64(struct csdev_access *csa, 536 u32 offset) 537 { 538 WARN_ON(1); 539 return 0; 540 } 541 542 static inline u64 csdev_access_read64(struct csdev_access *csa, u32 offset) 543 { 544 WARN_ON(1); 545 return 0; 546 } 547 548 static inline void csdev_access_relaxed_write64(struct csdev_access *csa, 549 u64 val, u32 offset) 550 { 551 WARN_ON(1); 552 } 553 554 static inline void csdev_access_write64(struct csdev_access *csa, u64 val, u32 offset) 555 { 556 WARN_ON(1); 557 } 558 #endif /* CONFIG_64BIT */ 559 560 static inline bool coresight_is_percpu_source(struct coresight_device *csdev) 561 { 562 return csdev && (csdev->type == CORESIGHT_DEV_TYPE_SOURCE) && 563 (csdev->subtype.source_subtype == CORESIGHT_DEV_SUBTYPE_SOURCE_PROC); 564 } 565 566 static inline bool coresight_is_percpu_sink(struct coresight_device *csdev) 567 { 568 return csdev && (csdev->type == CORESIGHT_DEV_TYPE_SINK) && 569 (csdev->subtype.sink_subtype == CORESIGHT_DEV_SUBTYPE_SINK_PERCPU_SYSMEM); 570 } 571 572 extern struct coresight_device * 573 coresight_register(struct coresight_desc *desc); 574 extern void coresight_unregister(struct coresight_device *csdev); 575 extern int coresight_enable(struct coresight_device *csdev); 576 extern void coresight_disable(struct coresight_device *csdev); 577 extern int coresight_timeout(struct csdev_access *csa, u32 offset, 578 int position, int value); 579 580 extern int coresight_claim_device(struct coresight_device *csdev); 581 extern int coresight_claim_device_unlocked(struct coresight_device *csdev); 582 583 extern void coresight_disclaim_device(struct coresight_device *csdev); 584 extern void coresight_disclaim_device_unlocked(struct coresight_device *csdev); 585 extern char *coresight_alloc_device_name(struct coresight_dev_list *devs, 586 struct device *dev); 587 588 extern bool coresight_loses_context_with_cpu(struct device *dev); 589 590 u32 coresight_relaxed_read32(struct coresight_device *csdev, u32 offset); 591 u32 coresight_read32(struct coresight_device *csdev, u32 offset); 592 void coresight_write32(struct coresight_device *csdev, u32 val, u32 offset); 593 void coresight_relaxed_write32(struct coresight_device *csdev, 594 u32 val, u32 offset); 595 u64 coresight_relaxed_read64(struct coresight_device *csdev, u32 offset); 596 u64 coresight_read64(struct coresight_device *csdev, u32 offset); 597 void coresight_relaxed_write64(struct coresight_device *csdev, 598 u64 val, u32 offset); 599 void coresight_write64(struct coresight_device *csdev, u64 val, u32 offset); 600 601 #else 602 static inline struct coresight_device * 603 coresight_register(struct coresight_desc *desc) { return NULL; } 604 static inline void coresight_unregister(struct coresight_device *csdev) {} 605 static inline int 606 coresight_enable(struct coresight_device *csdev) { return -ENOSYS; } 607 static inline void coresight_disable(struct coresight_device *csdev) {} 608 609 static inline int coresight_timeout(struct csdev_access *csa, u32 offset, 610 int position, int value) 611 { 612 return 1; 613 } 614 615 static inline int coresight_claim_device_unlocked(struct coresight_device *csdev) 616 { 617 return -EINVAL; 618 } 619 620 static inline int coresight_claim_device(struct coresight_device *csdev) 621 { 622 return -EINVAL; 623 } 624 625 static inline void coresight_disclaim_device(struct coresight_device *csdev) {} 626 static inline void coresight_disclaim_device_unlocked(struct coresight_device *csdev) {} 627 628 static inline bool coresight_loses_context_with_cpu(struct device *dev) 629 { 630 return false; 631 } 632 633 static inline u32 coresight_relaxed_read32(struct coresight_device *csdev, u32 offset) 634 { 635 WARN_ON_ONCE(1); 636 return 0; 637 } 638 639 static inline u32 coresight_read32(struct coresight_device *csdev, u32 offset) 640 { 641 WARN_ON_ONCE(1); 642 return 0; 643 } 644 645 static inline void coresight_write32(struct coresight_device *csdev, u32 val, u32 offset) 646 { 647 } 648 649 static inline void coresight_relaxed_write32(struct coresight_device *csdev, 650 u32 val, u32 offset) 651 { 652 } 653 654 static inline u64 coresight_relaxed_read64(struct coresight_device *csdev, 655 u32 offset) 656 { 657 WARN_ON_ONCE(1); 658 return 0; 659 } 660 661 static inline u64 coresight_read64(struct coresight_device *csdev, u32 offset) 662 { 663 WARN_ON_ONCE(1); 664 return 0; 665 } 666 667 static inline void coresight_relaxed_write64(struct coresight_device *csdev, 668 u64 val, u32 offset) 669 { 670 } 671 672 static inline void coresight_write64(struct coresight_device *csdev, u64 val, u32 offset) 673 { 674 } 675 676 #endif /* IS_ENABLED(CONFIG_CORESIGHT) */ 677 678 extern int coresight_get_cpu(struct device *dev); 679 680 struct coresight_platform_data *coresight_get_platform_data(struct device *dev); 681 struct coresight_connection * 682 coresight_add_out_conn(struct device *dev, 683 struct coresight_platform_data *pdata, 684 const struct coresight_connection *new_conn); 685 int coresight_add_in_conn(struct coresight_connection *conn); 686 struct coresight_device * 687 coresight_find_input_type(struct coresight_platform_data *pdata, 688 enum coresight_dev_type type, 689 union coresight_dev_subtype subtype); 690 struct coresight_device * 691 coresight_find_output_type(struct coresight_platform_data *pdata, 692 enum coresight_dev_type type, 693 union coresight_dev_subtype subtype); 694 695 #endif /* _LINUX_COREISGHT_H */ 696