1 /* SPDX-License-Identifier: GPL-2.0 */ 2 /* 3 * Copyright (c) 2012, The Linux Foundation. All rights reserved. 4 */ 5 6 #ifndef _LINUX_CORESIGHT_H 7 #define _LINUX_CORESIGHT_H 8 9 #include <linux/device.h> 10 #include <linux/perf_event.h> 11 #include <linux/sched.h> 12 13 /* Peripheral id registers (0xFD0-0xFEC) */ 14 #define CORESIGHT_PERIPHIDR4 0xfd0 15 #define CORESIGHT_PERIPHIDR5 0xfd4 16 #define CORESIGHT_PERIPHIDR6 0xfd8 17 #define CORESIGHT_PERIPHIDR7 0xfdC 18 #define CORESIGHT_PERIPHIDR0 0xfe0 19 #define CORESIGHT_PERIPHIDR1 0xfe4 20 #define CORESIGHT_PERIPHIDR2 0xfe8 21 #define CORESIGHT_PERIPHIDR3 0xfeC 22 /* Component id registers (0xFF0-0xFFC) */ 23 #define CORESIGHT_COMPIDR0 0xff0 24 #define CORESIGHT_COMPIDR1 0xff4 25 #define CORESIGHT_COMPIDR2 0xff8 26 #define CORESIGHT_COMPIDR3 0xffC 27 28 #define ETM_ARCH_V3_3 0x23 29 #define ETM_ARCH_V3_5 0x25 30 #define PFT_ARCH_V1_0 0x30 31 #define PFT_ARCH_V1_1 0x31 32 33 #define CORESIGHT_UNLOCK 0xc5acce55 34 35 extern struct bus_type coresight_bustype; 36 37 enum coresight_dev_type { 38 CORESIGHT_DEV_TYPE_NONE, 39 CORESIGHT_DEV_TYPE_SINK, 40 CORESIGHT_DEV_TYPE_LINK, 41 CORESIGHT_DEV_TYPE_LINKSINK, 42 CORESIGHT_DEV_TYPE_SOURCE, 43 CORESIGHT_DEV_TYPE_HELPER, 44 CORESIGHT_DEV_TYPE_ECT, 45 }; 46 47 enum coresight_dev_subtype_sink { 48 CORESIGHT_DEV_SUBTYPE_SINK_NONE, 49 CORESIGHT_DEV_SUBTYPE_SINK_PORT, 50 CORESIGHT_DEV_SUBTYPE_SINK_BUFFER, 51 CORESIGHT_DEV_SUBTYPE_SINK_SYSMEM, 52 }; 53 54 enum coresight_dev_subtype_link { 55 CORESIGHT_DEV_SUBTYPE_LINK_NONE, 56 CORESIGHT_DEV_SUBTYPE_LINK_MERG, 57 CORESIGHT_DEV_SUBTYPE_LINK_SPLIT, 58 CORESIGHT_DEV_SUBTYPE_LINK_FIFO, 59 }; 60 61 enum coresight_dev_subtype_source { 62 CORESIGHT_DEV_SUBTYPE_SOURCE_NONE, 63 CORESIGHT_DEV_SUBTYPE_SOURCE_PROC, 64 CORESIGHT_DEV_SUBTYPE_SOURCE_BUS, 65 CORESIGHT_DEV_SUBTYPE_SOURCE_SOFTWARE, 66 }; 67 68 enum coresight_dev_subtype_helper { 69 CORESIGHT_DEV_SUBTYPE_HELPER_NONE, 70 CORESIGHT_DEV_SUBTYPE_HELPER_CATU, 71 }; 72 73 /* Embedded Cross Trigger (ECT) sub-types */ 74 enum coresight_dev_subtype_ect { 75 CORESIGHT_DEV_SUBTYPE_ECT_NONE, 76 CORESIGHT_DEV_SUBTYPE_ECT_CTI, 77 }; 78 79 /** 80 * union coresight_dev_subtype - further characterisation of a type 81 * @sink_subtype: type of sink this component is, as defined 82 * by @coresight_dev_subtype_sink. 83 * @link_subtype: type of link this component is, as defined 84 * by @coresight_dev_subtype_link. 85 * @source_subtype: type of source this component is, as defined 86 * by @coresight_dev_subtype_source. 87 * @helper_subtype: type of helper this component is, as defined 88 * by @coresight_dev_subtype_helper. 89 * @ect_subtype: type of cross trigger this component is, as 90 * defined by @coresight_dev_subtype_ect 91 */ 92 union coresight_dev_subtype { 93 /* We have some devices which acts as LINK and SINK */ 94 struct { 95 enum coresight_dev_subtype_sink sink_subtype; 96 enum coresight_dev_subtype_link link_subtype; 97 }; 98 enum coresight_dev_subtype_source source_subtype; 99 enum coresight_dev_subtype_helper helper_subtype; 100 enum coresight_dev_subtype_ect ect_subtype; 101 }; 102 103 /** 104 * struct coresight_platform_data - data harvested from the firmware 105 * specification. 106 * 107 * @nr_inport: Number of elements for the input connections. 108 * @nr_outport: Number of elements for the output connections. 109 * @conns: Sparse array of nr_outport connections from this component. 110 */ 111 struct coresight_platform_data { 112 int nr_inport; 113 int nr_outport; 114 struct coresight_connection *conns; 115 }; 116 117 /** 118 * struct coresight_desc - description of a component required from drivers 119 * @type: as defined by @coresight_dev_type. 120 * @subtype: as defined by @coresight_dev_subtype. 121 * @ops: generic operations for this component, as defined 122 * by @coresight_ops. 123 * @pdata: platform data collected from DT. 124 * @dev: The device entity associated to this component. 125 * @groups: operations specific to this component. These will end up 126 * in the component's sysfs sub-directory. 127 * @name: name for the coresight device, also shown under sysfs. 128 */ 129 struct coresight_desc { 130 enum coresight_dev_type type; 131 union coresight_dev_subtype subtype; 132 const struct coresight_ops *ops; 133 struct coresight_platform_data *pdata; 134 struct device *dev; 135 const struct attribute_group **groups; 136 const char *name; 137 }; 138 139 /** 140 * struct coresight_connection - representation of a single connection 141 * @outport: a connection's output port number. 142 * @child_port: remote component's port number @output is connected to. 143 * @chid_fwnode: remote component's fwnode handle. 144 * @child_dev: a @coresight_device representation of the component 145 connected to @outport. 146 * @link: Representation of the connection as a sysfs link. 147 */ 148 struct coresight_connection { 149 int outport; 150 int child_port; 151 struct fwnode_handle *child_fwnode; 152 struct coresight_device *child_dev; 153 struct coresight_sysfs_link *link; 154 }; 155 156 /** 157 * struct coresight_sysfs_link - representation of a connection in sysfs. 158 * @orig: Originating (master) coresight device for the link. 159 * @orig_name: Name to use for the link orig->target. 160 * @target: Target (slave) coresight device for the link. 161 * @target_name: Name to use for the link target->orig. 162 */ 163 struct coresight_sysfs_link { 164 struct coresight_device *orig; 165 const char *orig_name; 166 struct coresight_device *target; 167 const char *target_name; 168 }; 169 170 /** 171 * struct coresight_device - representation of a device as used by the framework 172 * @pdata: Platform data with device connections associated to this device. 173 * @type: as defined by @coresight_dev_type. 174 * @subtype: as defined by @coresight_dev_subtype. 175 * @ops: generic operations for this component, as defined 176 by @coresight_ops. 177 * @dev: The device entity associated to this component. 178 * @refcnt: keep track of what is in use. 179 * @orphan: true if the component has connections that haven't been linked. 180 * @enable: 'true' if component is currently part of an active path. 181 * @activated: 'true' only if a _sink_ has been activated. A sink can be 182 * activated but not yet enabled. Enabling for a _sink_ 183 * happens when a source has been selected and a path is enabled 184 * from source to that sink. 185 * @ea: Device attribute for sink representation under PMU directory. 186 * @def_sink: cached reference to default sink found for this device. 187 * @ect_dev: Associated cross trigger device. Not part of the trace data 188 * path or connections. 189 * @nr_links: number of sysfs links created to other components from this 190 * device. These will appear in the "connections" group. 191 * @has_conns_grp: Have added a "connections" group for sysfs links. 192 */ 193 struct coresight_device { 194 struct coresight_platform_data *pdata; 195 enum coresight_dev_type type; 196 union coresight_dev_subtype subtype; 197 const struct coresight_ops *ops; 198 struct device dev; 199 atomic_t *refcnt; 200 bool orphan; 201 bool enable; /* true only if configured as part of a path */ 202 /* sink specific fields */ 203 bool activated; /* true only if a sink is part of a path */ 204 struct dev_ext_attribute *ea; 205 struct coresight_device *def_sink; 206 /* cross trigger handling */ 207 struct coresight_device *ect_dev; 208 /* sysfs links between components */ 209 int nr_links; 210 bool has_conns_grp; 211 }; 212 213 /* 214 * coresight_dev_list - Mapping for devices to "name" index for device 215 * names. 216 * 217 * @nr_idx: Number of entries already allocated. 218 * @pfx: Prefix pattern for device name. 219 * @fwnode_list: Array of fwnode_handles associated with each allocated 220 * index, upto nr_idx entries. 221 */ 222 struct coresight_dev_list { 223 int nr_idx; 224 const char *pfx; 225 struct fwnode_handle **fwnode_list; 226 }; 227 228 #define DEFINE_CORESIGHT_DEVLIST(var, dev_pfx) \ 229 static struct coresight_dev_list (var) = { \ 230 .pfx = dev_pfx, \ 231 .nr_idx = 0, \ 232 .fwnode_list = NULL, \ 233 } 234 235 #define to_coresight_device(d) container_of(d, struct coresight_device, dev) 236 237 #define source_ops(csdev) csdev->ops->source_ops 238 #define sink_ops(csdev) csdev->ops->sink_ops 239 #define link_ops(csdev) csdev->ops->link_ops 240 #define helper_ops(csdev) csdev->ops->helper_ops 241 #define ect_ops(csdev) csdev->ops->ect_ops 242 243 /** 244 * struct coresight_ops_sink - basic operations for a sink 245 * Operations available for sinks 246 * @enable: enables the sink. 247 * @disable: disables the sink. 248 * @alloc_buffer: initialises perf's ring buffer for trace collection. 249 * @free_buffer: release memory allocated in @get_config. 250 * @update_buffer: update buffer pointers after a trace session. 251 */ 252 struct coresight_ops_sink { 253 int (*enable)(struct coresight_device *csdev, u32 mode, void *data); 254 int (*disable)(struct coresight_device *csdev); 255 void *(*alloc_buffer)(struct coresight_device *csdev, 256 struct perf_event *event, void **pages, 257 int nr_pages, bool overwrite); 258 void (*free_buffer)(void *config); 259 unsigned long (*update_buffer)(struct coresight_device *csdev, 260 struct perf_output_handle *handle, 261 void *sink_config); 262 }; 263 264 /** 265 * struct coresight_ops_link - basic operations for a link 266 * Operations available for links. 267 * @enable: enables flow between iport and oport. 268 * @disable: disables flow between iport and oport. 269 */ 270 struct coresight_ops_link { 271 int (*enable)(struct coresight_device *csdev, int iport, int oport); 272 void (*disable)(struct coresight_device *csdev, int iport, int oport); 273 }; 274 275 /** 276 * struct coresight_ops_source - basic operations for a source 277 * Operations available for sources. 278 * @cpu_id: returns the value of the CPU number this component 279 * is associated to. 280 * @trace_id: returns the value of the component's trace ID as known 281 * to the HW. 282 * @enable: enables tracing for a source. 283 * @disable: disables tracing for a source. 284 */ 285 struct coresight_ops_source { 286 int (*cpu_id)(struct coresight_device *csdev); 287 int (*trace_id)(struct coresight_device *csdev); 288 int (*enable)(struct coresight_device *csdev, 289 struct perf_event *event, u32 mode); 290 void (*disable)(struct coresight_device *csdev, 291 struct perf_event *event); 292 }; 293 294 /** 295 * struct coresight_ops_helper - Operations for a helper device. 296 * 297 * All operations could pass in a device specific data, which could 298 * help the helper device to determine what to do. 299 * 300 * @enable : Enable the device 301 * @disable : Disable the device 302 */ 303 struct coresight_ops_helper { 304 int (*enable)(struct coresight_device *csdev, void *data); 305 int (*disable)(struct coresight_device *csdev, void *data); 306 }; 307 308 /** 309 * struct coresight_ops_ect - Ops for an embedded cross trigger device 310 * 311 * @enable : Enable the device 312 * @disable : Disable the device 313 */ 314 struct coresight_ops_ect { 315 int (*enable)(struct coresight_device *csdev); 316 int (*disable)(struct coresight_device *csdev); 317 }; 318 319 struct coresight_ops { 320 const struct coresight_ops_sink *sink_ops; 321 const struct coresight_ops_link *link_ops; 322 const struct coresight_ops_source *source_ops; 323 const struct coresight_ops_helper *helper_ops; 324 const struct coresight_ops_ect *ect_ops; 325 }; 326 327 #ifdef CONFIG_CORESIGHT 328 extern struct coresight_device * 329 coresight_register(struct coresight_desc *desc); 330 extern void coresight_unregister(struct coresight_device *csdev); 331 extern int coresight_enable(struct coresight_device *csdev); 332 extern void coresight_disable(struct coresight_device *csdev); 333 extern int coresight_timeout(void __iomem *addr, u32 offset, 334 int position, int value); 335 336 extern int coresight_claim_device(void __iomem *base); 337 extern int coresight_claim_device_unlocked(void __iomem *base); 338 339 extern void coresight_disclaim_device(void __iomem *base); 340 extern void coresight_disclaim_device_unlocked(void __iomem *base); 341 extern char *coresight_alloc_device_name(struct coresight_dev_list *devs, 342 struct device *dev); 343 344 extern bool coresight_loses_context_with_cpu(struct device *dev); 345 #else 346 static inline struct coresight_device * 347 coresight_register(struct coresight_desc *desc) { return NULL; } 348 static inline void coresight_unregister(struct coresight_device *csdev) {} 349 static inline int 350 coresight_enable(struct coresight_device *csdev) { return -ENOSYS; } 351 static inline void coresight_disable(struct coresight_device *csdev) {} 352 static inline int coresight_timeout(void __iomem *addr, u32 offset, 353 int position, int value) { return 1; } 354 static inline int coresight_claim_device_unlocked(void __iomem *base) 355 { 356 return -EINVAL; 357 } 358 359 static inline int coresight_claim_device(void __iomem *base) 360 { 361 return -EINVAL; 362 } 363 364 static inline void coresight_disclaim_device(void __iomem *base) {} 365 static inline void coresight_disclaim_device_unlocked(void __iomem *base) {} 366 367 static inline bool coresight_loses_context_with_cpu(struct device *dev) 368 { 369 return false; 370 } 371 #endif 372 373 extern int coresight_get_cpu(struct device *dev); 374 375 struct coresight_platform_data *coresight_get_platform_data(struct device *dev); 376 377 #endif 378