1 /* SPDX-License-Identifier: GPL-2.0 */ 2 /* 3 * Copyright (c) 2012, The Linux Foundation. All rights reserved. 4 */ 5 6 #ifndef _LINUX_CORESIGHT_H 7 #define _LINUX_CORESIGHT_H 8 9 #include <linux/amba/bus.h> 10 #include <linux/clk.h> 11 #include <linux/device.h> 12 #include <linux/io.h> 13 #include <linux/perf_event.h> 14 #include <linux/sched.h> 15 #include <linux/platform_device.h> 16 17 /* Peripheral id registers (0xFD0-0xFEC) */ 18 #define CORESIGHT_PERIPHIDR4 0xfd0 19 #define CORESIGHT_PERIPHIDR5 0xfd4 20 #define CORESIGHT_PERIPHIDR6 0xfd8 21 #define CORESIGHT_PERIPHIDR7 0xfdC 22 #define CORESIGHT_PERIPHIDR0 0xfe0 23 #define CORESIGHT_PERIPHIDR1 0xfe4 24 #define CORESIGHT_PERIPHIDR2 0xfe8 25 #define CORESIGHT_PERIPHIDR3 0xfeC 26 /* Component id registers (0xFF0-0xFFC) */ 27 #define CORESIGHT_COMPIDR0 0xff0 28 #define CORESIGHT_COMPIDR1 0xff4 29 #define CORESIGHT_COMPIDR2 0xff8 30 #define CORESIGHT_COMPIDR3 0xffC 31 32 #define ETM_ARCH_V3_3 0x23 33 #define ETM_ARCH_V3_5 0x25 34 #define PFT_ARCH_V1_0 0x30 35 #define PFT_ARCH_V1_1 0x31 36 37 #define CORESIGHT_UNLOCK 0xc5acce55 38 39 extern const struct bus_type coresight_bustype; 40 41 enum coresight_dev_type { 42 CORESIGHT_DEV_TYPE_SINK, 43 CORESIGHT_DEV_TYPE_LINK, 44 CORESIGHT_DEV_TYPE_LINKSINK, 45 CORESIGHT_DEV_TYPE_SOURCE, 46 CORESIGHT_DEV_TYPE_HELPER, 47 CORESIGHT_DEV_TYPE_MAX 48 }; 49 50 enum coresight_dev_subtype_sink { 51 CORESIGHT_DEV_SUBTYPE_SINK_DUMMY, 52 CORESIGHT_DEV_SUBTYPE_SINK_PORT, 53 CORESIGHT_DEV_SUBTYPE_SINK_BUFFER, 54 CORESIGHT_DEV_SUBTYPE_SINK_SYSMEM, 55 CORESIGHT_DEV_SUBTYPE_SINK_PERCPU_SYSMEM, 56 }; 57 58 enum coresight_dev_subtype_link { 59 CORESIGHT_DEV_SUBTYPE_LINK_MERG, 60 CORESIGHT_DEV_SUBTYPE_LINK_SPLIT, 61 CORESIGHT_DEV_SUBTYPE_LINK_FIFO, 62 }; 63 64 enum coresight_dev_subtype_source { 65 CORESIGHT_DEV_SUBTYPE_SOURCE_PROC, 66 CORESIGHT_DEV_SUBTYPE_SOURCE_BUS, 67 CORESIGHT_DEV_SUBTYPE_SOURCE_SOFTWARE, 68 CORESIGHT_DEV_SUBTYPE_SOURCE_TPDM, 69 CORESIGHT_DEV_SUBTYPE_SOURCE_OTHERS, 70 }; 71 72 enum coresight_dev_subtype_helper { 73 CORESIGHT_DEV_SUBTYPE_HELPER_CATU, 74 CORESIGHT_DEV_SUBTYPE_HELPER_ECT_CTI 75 }; 76 77 /** 78 * union coresight_dev_subtype - further characterisation of a type 79 * @sink_subtype: type of sink this component is, as defined 80 * by @coresight_dev_subtype_sink. 81 * @link_subtype: type of link this component is, as defined 82 * by @coresight_dev_subtype_link. 83 * @source_subtype: type of source this component is, as defined 84 * by @coresight_dev_subtype_source. 85 * @helper_subtype: type of helper this component is, as defined 86 * by @coresight_dev_subtype_helper. 87 */ 88 union coresight_dev_subtype { 89 /* We have some devices which acts as LINK and SINK */ 90 struct { 91 enum coresight_dev_subtype_sink sink_subtype; 92 enum coresight_dev_subtype_link link_subtype; 93 }; 94 enum coresight_dev_subtype_source source_subtype; 95 enum coresight_dev_subtype_helper helper_subtype; 96 }; 97 98 /** 99 * struct coresight_platform_data - data harvested from the firmware 100 * specification. 101 * 102 * @nr_inconns: Number of elements for the input connections. 103 * @nr_outconns: Number of elements for the output connections. 104 * @out_conns: Array of nr_outconns pointers to connections from this 105 * component. 106 * @in_conns: Sparse array of pointers to input connections. Sparse 107 * because the source device owns the connection so when it's 108 * unloaded the connection leaves an empty slot. 109 */ 110 struct coresight_platform_data { 111 int nr_inconns; 112 int nr_outconns; 113 struct coresight_connection **out_conns; 114 struct coresight_connection **in_conns; 115 }; 116 117 /** 118 * struct csdev_access - Abstraction of a CoreSight device access. 119 * 120 * @io_mem : True if the device has memory mapped I/O 121 * @base : When io_mem == true, base address of the component 122 * @read : Read from the given "offset" of the given instance. 123 * @write : Write "val" to the given "offset". 124 */ 125 struct csdev_access { 126 bool io_mem; 127 union { 128 void __iomem *base; 129 struct { 130 u64 (*read)(u32 offset, bool relaxed, bool _64bit); 131 void (*write)(u64 val, u32 offset, bool relaxed, 132 bool _64bit); 133 }; 134 }; 135 }; 136 137 #define CSDEV_ACCESS_IOMEM(_addr) \ 138 ((struct csdev_access) { \ 139 .io_mem = true, \ 140 .base = (_addr), \ 141 }) 142 143 /** 144 * struct coresight_desc - description of a component required from drivers 145 * @type: as defined by @coresight_dev_type. 146 * @subtype: as defined by @coresight_dev_subtype. 147 * @ops: generic operations for this component, as defined 148 * by @coresight_ops. 149 * @pdata: platform data collected from DT. 150 * @dev: The device entity associated to this component. 151 * @groups: operations specific to this component. These will end up 152 * in the component's sysfs sub-directory. 153 * @name: name for the coresight device, also shown under sysfs. 154 * @access: Describe access to the device 155 */ 156 struct coresight_desc { 157 enum coresight_dev_type type; 158 union coresight_dev_subtype subtype; 159 const struct coresight_ops *ops; 160 struct coresight_platform_data *pdata; 161 struct device *dev; 162 const struct attribute_group **groups; 163 const char *name; 164 struct csdev_access access; 165 }; 166 167 /** 168 * struct coresight_connection - representation of a single connection 169 * @src_port: a connection's output port number. 170 * @dest_port: destination's input port number @src_port is connected to. 171 * @dest_fwnode: destination component's fwnode handle. 172 * @dest_dev: a @coresight_device representation of the component 173 connected to @src_port. NULL until the device is created 174 * @link: Representation of the connection as a sysfs link. 175 * 176 * The full connection structure looks like this, where in_conns store 177 * references to same connection as the source device's out_conns. 178 * 179 * +-----------------------------+ +-----------------------------+ 180 * |coresight_device | |coresight_connection | 181 * |-----------------------------| |-----------------------------| 182 * | | | | 183 * | | | dest_dev*|<-- 184 * |pdata->out_conns[nr_outconns]|<->|src_dev* | | 185 * | | | | | 186 * +-----------------------------+ +-----------------------------+ | 187 * | 188 * +-----------------------------+ | 189 * |coresight_device | | 190 * |------------------------------ | 191 * | | | 192 * | pdata->in_conns[nr_inconns]|<-- 193 * | | 194 * +-----------------------------+ 195 */ 196 struct coresight_connection { 197 int src_port; 198 int dest_port; 199 struct fwnode_handle *dest_fwnode; 200 struct coresight_device *dest_dev; 201 struct coresight_sysfs_link *link; 202 struct coresight_device *src_dev; 203 atomic_t src_refcnt; 204 atomic_t dest_refcnt; 205 }; 206 207 /** 208 * struct coresight_sysfs_link - representation of a connection in sysfs. 209 * @orig: Originating (master) coresight device for the link. 210 * @orig_name: Name to use for the link orig->target. 211 * @target: Target (slave) coresight device for the link. 212 * @target_name: Name to use for the link target->orig. 213 */ 214 struct coresight_sysfs_link { 215 struct coresight_device *orig; 216 const char *orig_name; 217 struct coresight_device *target; 218 const char *target_name; 219 }; 220 221 /* architecturally we have 128 IDs some of which are reserved */ 222 #define CORESIGHT_TRACE_IDS_MAX 128 223 224 /** 225 * Trace ID map. 226 * 227 * @used_ids: Bitmap to register available (bit = 0) and in use (bit = 1) IDs. 228 * Initialised so that the reserved IDs are permanently marked as 229 * in use. 230 * @perf_cs_etm_session_active: Number of Perf sessions using this ID map. 231 */ 232 struct coresight_trace_id_map { 233 DECLARE_BITMAP(used_ids, CORESIGHT_TRACE_IDS_MAX); 234 atomic_t __percpu *cpu_map; 235 atomic_t perf_cs_etm_session_active; 236 spinlock_t lock; 237 }; 238 239 /** 240 * struct coresight_device - representation of a device as used by the framework 241 * @pdata: Platform data with device connections associated to this device. 242 * @type: as defined by @coresight_dev_type. 243 * @subtype: as defined by @coresight_dev_subtype. 244 * @ops: generic operations for this component, as defined 245 * by @coresight_ops. 246 * @access: Device i/o access abstraction for this device. 247 * @dev: The device entity associated to this component. 248 * @mode: This tracer's mode, i.e sysFS, Perf or disabled. This is 249 * actually an 'enum cs_mode', but is stored in an atomic type. 250 * This is always accessed through local_read() and local_set(), 251 * but wherever it's done from within the Coresight device's lock, 252 * a non-atomic read would also work. This is the main point of 253 * synchronisation between code happening inside the sysfs mode's 254 * coresight_mutex and outside when running in Perf mode. A compare 255 * and exchange swap is done to atomically claim one mode or the 256 * other. 257 * @refcnt: keep track of what is in use. Only access this outside of the 258 * device's spinlock when the coresight_mutex held and mode == 259 * CS_MODE_SYSFS. Otherwise it must be accessed from inside the 260 * spinlock. 261 * @orphan: true if the component has connections that haven't been linked. 262 * @sysfs_sink_activated: 'true' when a sink has been selected for use via sysfs 263 * by writing a 1 to the 'enable_sink' file. A sink can be 264 * activated but not yet enabled. Enabling for a _sink_ happens 265 * when a source has been selected and a path is enabled from 266 * source to that sink. A sink can also become enabled but not 267 * activated if it's used via Perf. 268 * @ea: Device attribute for sink representation under PMU directory. 269 * @def_sink: cached reference to default sink found for this device. 270 * @nr_links: number of sysfs links created to other components from this 271 * device. These will appear in the "connections" group. 272 * @has_conns_grp: Have added a "connections" group for sysfs links. 273 * @feature_csdev_list: List of complex feature programming added to the device. 274 * @config_csdev_list: List of system configurations added to the device. 275 * @cscfg_csdev_lock: Protect the lists of configurations and features. 276 * @active_cscfg_ctxt: Context information for current active system configuration. 277 */ 278 struct coresight_device { 279 struct coresight_platform_data *pdata; 280 enum coresight_dev_type type; 281 union coresight_dev_subtype subtype; 282 const struct coresight_ops *ops; 283 struct csdev_access access; 284 struct device dev; 285 local_t mode; 286 int refcnt; 287 bool orphan; 288 /* sink specific fields */ 289 bool sysfs_sink_activated; 290 struct dev_ext_attribute *ea; 291 struct coresight_device *def_sink; 292 struct coresight_trace_id_map perf_sink_id_map; 293 /* sysfs links between components */ 294 int nr_links; 295 bool has_conns_grp; 296 /* system configuration and feature lists */ 297 struct list_head feature_csdev_list; 298 struct list_head config_csdev_list; 299 spinlock_t cscfg_csdev_lock; 300 void *active_cscfg_ctxt; 301 }; 302 303 /* 304 * coresight_dev_list - Mapping for devices to "name" index for device 305 * names. 306 * 307 * @nr_idx: Number of entries already allocated. 308 * @pfx: Prefix pattern for device name. 309 * @fwnode_list: Array of fwnode_handles associated with each allocated 310 * index, upto nr_idx entries. 311 */ 312 struct coresight_dev_list { 313 int nr_idx; 314 const char *pfx; 315 struct fwnode_handle **fwnode_list; 316 }; 317 318 #define DEFINE_CORESIGHT_DEVLIST(var, dev_pfx) \ 319 static struct coresight_dev_list (var) = { \ 320 .pfx = dev_pfx, \ 321 .nr_idx = 0, \ 322 .fwnode_list = NULL, \ 323 } 324 325 #define to_coresight_device(d) container_of(d, struct coresight_device, dev) 326 327 enum cs_mode { 328 CS_MODE_DISABLED, 329 CS_MODE_SYSFS, 330 CS_MODE_PERF, 331 }; 332 333 #define source_ops(csdev) csdev->ops->source_ops 334 #define sink_ops(csdev) csdev->ops->sink_ops 335 #define link_ops(csdev) csdev->ops->link_ops 336 #define helper_ops(csdev) csdev->ops->helper_ops 337 #define ect_ops(csdev) csdev->ops->ect_ops 338 339 /** 340 * struct coresight_ops_sink - basic operations for a sink 341 * Operations available for sinks 342 * @enable: enables the sink. 343 * @disable: disables the sink. 344 * @alloc_buffer: initialises perf's ring buffer for trace collection. 345 * @free_buffer: release memory allocated in @get_config. 346 * @update_buffer: update buffer pointers after a trace session. 347 */ 348 struct coresight_ops_sink { 349 int (*enable)(struct coresight_device *csdev, enum cs_mode mode, 350 void *data); 351 int (*disable)(struct coresight_device *csdev); 352 void *(*alloc_buffer)(struct coresight_device *csdev, 353 struct perf_event *event, void **pages, 354 int nr_pages, bool overwrite); 355 void (*free_buffer)(void *config); 356 unsigned long (*update_buffer)(struct coresight_device *csdev, 357 struct perf_output_handle *handle, 358 void *sink_config); 359 }; 360 361 /** 362 * struct coresight_ops_link - basic operations for a link 363 * Operations available for links. 364 * @enable: enables flow between iport and oport. 365 * @disable: disables flow between iport and oport. 366 */ 367 struct coresight_ops_link { 368 int (*enable)(struct coresight_device *csdev, 369 struct coresight_connection *in, 370 struct coresight_connection *out); 371 void (*disable)(struct coresight_device *csdev, 372 struct coresight_connection *in, 373 struct coresight_connection *out); 374 }; 375 376 /** 377 * struct coresight_ops_source - basic operations for a source 378 * Operations available for sources. 379 * @cpu_id: returns the value of the CPU number this component 380 * is associated to. 381 * @enable: enables tracing for a source. 382 * @disable: disables tracing for a source. 383 */ 384 struct coresight_ops_source { 385 int (*cpu_id)(struct coresight_device *csdev); 386 int (*enable)(struct coresight_device *csdev, struct perf_event *event, 387 enum cs_mode mode, struct coresight_trace_id_map *id_map); 388 void (*disable)(struct coresight_device *csdev, 389 struct perf_event *event); 390 }; 391 392 /** 393 * struct coresight_ops_helper - Operations for a helper device. 394 * 395 * All operations could pass in a device specific data, which could 396 * help the helper device to determine what to do. 397 * 398 * @enable : Enable the device 399 * @disable : Disable the device 400 */ 401 struct coresight_ops_helper { 402 int (*enable)(struct coresight_device *csdev, enum cs_mode mode, 403 void *data); 404 int (*disable)(struct coresight_device *csdev, void *data); 405 }; 406 407 struct coresight_ops { 408 const struct coresight_ops_sink *sink_ops; 409 const struct coresight_ops_link *link_ops; 410 const struct coresight_ops_source *source_ops; 411 const struct coresight_ops_helper *helper_ops; 412 }; 413 414 static inline u32 csdev_access_relaxed_read32(struct csdev_access *csa, 415 u32 offset) 416 { 417 if (likely(csa->io_mem)) 418 return readl_relaxed(csa->base + offset); 419 420 return csa->read(offset, true, false); 421 } 422 423 #define CORESIGHT_CIDRn(i) (0xFF0 + ((i) * 4)) 424 425 static inline u32 coresight_get_cid(void __iomem *base) 426 { 427 u32 i, cid = 0; 428 429 for (i = 0; i < 4; i++) 430 cid |= readl(base + CORESIGHT_CIDRn(i)) << (i * 8); 431 432 return cid; 433 } 434 435 static inline bool is_coresight_device(void __iomem *base) 436 { 437 u32 cid = coresight_get_cid(base); 438 439 return cid == CORESIGHT_CID; 440 } 441 442 /* 443 * Attempt to find and enable "APB clock" for the given device 444 * 445 * Returns: 446 * 447 * clk - Clock is found and enabled 448 * NULL - clock is not found 449 * ERROR - Clock is found but failed to enable 450 */ 451 static inline struct clk *coresight_get_enable_apb_pclk(struct device *dev) 452 { 453 struct clk *pclk; 454 int ret; 455 456 pclk = clk_get(dev, "apb_pclk"); 457 if (IS_ERR(pclk)) 458 return NULL; 459 460 ret = clk_prepare_enable(pclk); 461 if (ret) { 462 clk_put(pclk); 463 return ERR_PTR(ret); 464 } 465 return pclk; 466 } 467 468 #define CORESIGHT_PIDRn(i) (0xFE0 + ((i) * 4)) 469 470 static inline u32 coresight_get_pid(struct csdev_access *csa) 471 { 472 u32 i, pid = 0; 473 474 for (i = 0; i < 4; i++) 475 pid |= csdev_access_relaxed_read32(csa, CORESIGHT_PIDRn(i)) << (i * 8); 476 477 return pid; 478 } 479 480 static inline u64 csdev_access_relaxed_read_pair(struct csdev_access *csa, 481 u32 lo_offset, u32 hi_offset) 482 { 483 if (likely(csa->io_mem)) { 484 return readl_relaxed(csa->base + lo_offset) | 485 ((u64)readl_relaxed(csa->base + hi_offset) << 32); 486 } 487 488 return csa->read(lo_offset, true, false) | (csa->read(hi_offset, true, false) << 32); 489 } 490 491 static inline void csdev_access_relaxed_write_pair(struct csdev_access *csa, u64 val, 492 u32 lo_offset, u32 hi_offset) 493 { 494 if (likely(csa->io_mem)) { 495 writel_relaxed((u32)val, csa->base + lo_offset); 496 writel_relaxed((u32)(val >> 32), csa->base + hi_offset); 497 } else { 498 csa->write((u32)val, lo_offset, true, false); 499 csa->write((u32)(val >> 32), hi_offset, true, false); 500 } 501 } 502 503 static inline u32 csdev_access_read32(struct csdev_access *csa, u32 offset) 504 { 505 if (likely(csa->io_mem)) 506 return readl(csa->base + offset); 507 508 return csa->read(offset, false, false); 509 } 510 511 static inline void csdev_access_relaxed_write32(struct csdev_access *csa, 512 u32 val, u32 offset) 513 { 514 if (likely(csa->io_mem)) 515 writel_relaxed(val, csa->base + offset); 516 else 517 csa->write(val, offset, true, false); 518 } 519 520 static inline void csdev_access_write32(struct csdev_access *csa, u32 val, u32 offset) 521 { 522 if (likely(csa->io_mem)) 523 writel(val, csa->base + offset); 524 else 525 csa->write(val, offset, false, false); 526 } 527 528 #ifdef CONFIG_64BIT 529 530 static inline u64 csdev_access_relaxed_read64(struct csdev_access *csa, 531 u32 offset) 532 { 533 if (likely(csa->io_mem)) 534 return readq_relaxed(csa->base + offset); 535 536 return csa->read(offset, true, true); 537 } 538 539 static inline u64 csdev_access_read64(struct csdev_access *csa, u32 offset) 540 { 541 if (likely(csa->io_mem)) 542 return readq(csa->base + offset); 543 544 return csa->read(offset, false, true); 545 } 546 547 static inline void csdev_access_relaxed_write64(struct csdev_access *csa, 548 u64 val, u32 offset) 549 { 550 if (likely(csa->io_mem)) 551 writeq_relaxed(val, csa->base + offset); 552 else 553 csa->write(val, offset, true, true); 554 } 555 556 static inline void csdev_access_write64(struct csdev_access *csa, u64 val, u32 offset) 557 { 558 if (likely(csa->io_mem)) 559 writeq(val, csa->base + offset); 560 else 561 csa->write(val, offset, false, true); 562 } 563 564 #else /* !CONFIG_64BIT */ 565 566 static inline u64 csdev_access_relaxed_read64(struct csdev_access *csa, 567 u32 offset) 568 { 569 WARN_ON(1); 570 return 0; 571 } 572 573 static inline u64 csdev_access_read64(struct csdev_access *csa, u32 offset) 574 { 575 WARN_ON(1); 576 return 0; 577 } 578 579 static inline void csdev_access_relaxed_write64(struct csdev_access *csa, 580 u64 val, u32 offset) 581 { 582 WARN_ON(1); 583 } 584 585 static inline void csdev_access_write64(struct csdev_access *csa, u64 val, u32 offset) 586 { 587 WARN_ON(1); 588 } 589 #endif /* CONFIG_64BIT */ 590 591 static inline bool coresight_is_percpu_source(struct coresight_device *csdev) 592 { 593 return csdev && (csdev->type == CORESIGHT_DEV_TYPE_SOURCE) && 594 (csdev->subtype.source_subtype == CORESIGHT_DEV_SUBTYPE_SOURCE_PROC); 595 } 596 597 static inline bool coresight_is_percpu_sink(struct coresight_device *csdev) 598 { 599 return csdev && (csdev->type == CORESIGHT_DEV_TYPE_SINK) && 600 (csdev->subtype.sink_subtype == CORESIGHT_DEV_SUBTYPE_SINK_PERCPU_SYSMEM); 601 } 602 603 /* 604 * Atomically try to take the device and set a new mode. Returns true on 605 * success, false if the device is already taken by someone else. 606 */ 607 static inline bool coresight_take_mode(struct coresight_device *csdev, 608 enum cs_mode new_mode) 609 { 610 return local_cmpxchg(&csdev->mode, CS_MODE_DISABLED, new_mode) == 611 CS_MODE_DISABLED; 612 } 613 614 static inline enum cs_mode coresight_get_mode(struct coresight_device *csdev) 615 { 616 return local_read(&csdev->mode); 617 } 618 619 static inline void coresight_set_mode(struct coresight_device *csdev, 620 enum cs_mode new_mode) 621 { 622 enum cs_mode current_mode = coresight_get_mode(csdev); 623 624 /* 625 * Changing to a new mode must be done from an already disabled state 626 * unless it's synchronized with coresight_take_mode(). Otherwise the 627 * device is already in use and signifies a locking issue. 628 */ 629 WARN(new_mode != CS_MODE_DISABLED && current_mode != CS_MODE_DISABLED && 630 current_mode != new_mode, "Device already in use\n"); 631 632 local_set(&csdev->mode, new_mode); 633 } 634 635 extern struct coresight_device * 636 coresight_register(struct coresight_desc *desc); 637 extern void coresight_unregister(struct coresight_device *csdev); 638 extern int coresight_enable_sysfs(struct coresight_device *csdev); 639 extern void coresight_disable_sysfs(struct coresight_device *csdev); 640 extern int coresight_timeout(struct csdev_access *csa, u32 offset, 641 int position, int value); 642 643 extern int coresight_claim_device(struct coresight_device *csdev); 644 extern int coresight_claim_device_unlocked(struct coresight_device *csdev); 645 646 extern void coresight_disclaim_device(struct coresight_device *csdev); 647 extern void coresight_disclaim_device_unlocked(struct coresight_device *csdev); 648 extern char *coresight_alloc_device_name(struct coresight_dev_list *devs, 649 struct device *dev); 650 651 extern bool coresight_loses_context_with_cpu(struct device *dev); 652 653 u32 coresight_relaxed_read32(struct coresight_device *csdev, u32 offset); 654 u32 coresight_read32(struct coresight_device *csdev, u32 offset); 655 void coresight_write32(struct coresight_device *csdev, u32 val, u32 offset); 656 void coresight_relaxed_write32(struct coresight_device *csdev, 657 u32 val, u32 offset); 658 u64 coresight_relaxed_read64(struct coresight_device *csdev, u32 offset); 659 u64 coresight_read64(struct coresight_device *csdev, u32 offset); 660 void coresight_relaxed_write64(struct coresight_device *csdev, 661 u64 val, u32 offset); 662 void coresight_write64(struct coresight_device *csdev, u64 val, u32 offset); 663 664 extern int coresight_get_cpu(struct device *dev); 665 666 struct coresight_platform_data *coresight_get_platform_data(struct device *dev); 667 struct coresight_connection * 668 coresight_add_out_conn(struct device *dev, 669 struct coresight_platform_data *pdata, 670 const struct coresight_connection *new_conn); 671 int coresight_add_in_conn(struct coresight_connection *conn); 672 struct coresight_device * 673 coresight_find_input_type(struct coresight_platform_data *pdata, 674 enum coresight_dev_type type, 675 union coresight_dev_subtype subtype); 676 struct coresight_device * 677 coresight_find_output_type(struct coresight_platform_data *pdata, 678 enum coresight_dev_type type, 679 union coresight_dev_subtype subtype); 680 681 int coresight_init_driver(const char *drv, struct amba_driver *amba_drv, 682 struct platform_driver *pdev_drv); 683 684 void coresight_remove_driver(struct amba_driver *amba_drv, 685 struct platform_driver *pdev_drv); 686 #endif /* _LINUX_COREISGHT_H */ 687