1 /* SPDX-License-Identifier: GPL-2.0 */ 2 /* 3 * Copyright (c) 2012, The Linux Foundation. All rights reserved. 4 */ 5 6 #ifndef _LINUX_CORESIGHT_H 7 #define _LINUX_CORESIGHT_H 8 9 #include <linux/device.h> 10 #include <linux/io.h> 11 #include <linux/perf_event.h> 12 #include <linux/sched.h> 13 14 /* Peripheral id registers (0xFD0-0xFEC) */ 15 #define CORESIGHT_PERIPHIDR4 0xfd0 16 #define CORESIGHT_PERIPHIDR5 0xfd4 17 #define CORESIGHT_PERIPHIDR6 0xfd8 18 #define CORESIGHT_PERIPHIDR7 0xfdC 19 #define CORESIGHT_PERIPHIDR0 0xfe0 20 #define CORESIGHT_PERIPHIDR1 0xfe4 21 #define CORESIGHT_PERIPHIDR2 0xfe8 22 #define CORESIGHT_PERIPHIDR3 0xfeC 23 /* Component id registers (0xFF0-0xFFC) */ 24 #define CORESIGHT_COMPIDR0 0xff0 25 #define CORESIGHT_COMPIDR1 0xff4 26 #define CORESIGHT_COMPIDR2 0xff8 27 #define CORESIGHT_COMPIDR3 0xffC 28 29 #define ETM_ARCH_V3_3 0x23 30 #define ETM_ARCH_V3_5 0x25 31 #define PFT_ARCH_V1_0 0x30 32 #define PFT_ARCH_V1_1 0x31 33 34 #define CORESIGHT_UNLOCK 0xc5acce55 35 36 extern struct bus_type coresight_bustype; 37 38 enum coresight_dev_type { 39 CORESIGHT_DEV_TYPE_NONE, 40 CORESIGHT_DEV_TYPE_SINK, 41 CORESIGHT_DEV_TYPE_LINK, 42 CORESIGHT_DEV_TYPE_LINKSINK, 43 CORESIGHT_DEV_TYPE_SOURCE, 44 CORESIGHT_DEV_TYPE_HELPER, 45 CORESIGHT_DEV_TYPE_ECT, 46 }; 47 48 enum coresight_dev_subtype_sink { 49 CORESIGHT_DEV_SUBTYPE_SINK_NONE, 50 CORESIGHT_DEV_SUBTYPE_SINK_PORT, 51 CORESIGHT_DEV_SUBTYPE_SINK_BUFFER, 52 CORESIGHT_DEV_SUBTYPE_SINK_SYSMEM, 53 CORESIGHT_DEV_SUBTYPE_SINK_PERCPU_SYSMEM, 54 }; 55 56 enum coresight_dev_subtype_link { 57 CORESIGHT_DEV_SUBTYPE_LINK_NONE, 58 CORESIGHT_DEV_SUBTYPE_LINK_MERG, 59 CORESIGHT_DEV_SUBTYPE_LINK_SPLIT, 60 CORESIGHT_DEV_SUBTYPE_LINK_FIFO, 61 }; 62 63 enum coresight_dev_subtype_source { 64 CORESIGHT_DEV_SUBTYPE_SOURCE_NONE, 65 CORESIGHT_DEV_SUBTYPE_SOURCE_PROC, 66 CORESIGHT_DEV_SUBTYPE_SOURCE_BUS, 67 CORESIGHT_DEV_SUBTYPE_SOURCE_SOFTWARE, 68 }; 69 70 enum coresight_dev_subtype_helper { 71 CORESIGHT_DEV_SUBTYPE_HELPER_NONE, 72 CORESIGHT_DEV_SUBTYPE_HELPER_CATU, 73 }; 74 75 /* Embedded Cross Trigger (ECT) sub-types */ 76 enum coresight_dev_subtype_ect { 77 CORESIGHT_DEV_SUBTYPE_ECT_NONE, 78 CORESIGHT_DEV_SUBTYPE_ECT_CTI, 79 }; 80 81 /** 82 * union coresight_dev_subtype - further characterisation of a type 83 * @sink_subtype: type of sink this component is, as defined 84 * by @coresight_dev_subtype_sink. 85 * @link_subtype: type of link this component is, as defined 86 * by @coresight_dev_subtype_link. 87 * @source_subtype: type of source this component is, as defined 88 * by @coresight_dev_subtype_source. 89 * @helper_subtype: type of helper this component is, as defined 90 * by @coresight_dev_subtype_helper. 91 * @ect_subtype: type of cross trigger this component is, as 92 * defined by @coresight_dev_subtype_ect 93 */ 94 union coresight_dev_subtype { 95 /* We have some devices which acts as LINK and SINK */ 96 struct { 97 enum coresight_dev_subtype_sink sink_subtype; 98 enum coresight_dev_subtype_link link_subtype; 99 }; 100 enum coresight_dev_subtype_source source_subtype; 101 enum coresight_dev_subtype_helper helper_subtype; 102 enum coresight_dev_subtype_ect ect_subtype; 103 }; 104 105 /** 106 * struct coresight_platform_data - data harvested from the firmware 107 * specification. 108 * 109 * @nr_inport: Number of elements for the input connections. 110 * @nr_outport: Number of elements for the output connections. 111 * @conns: Sparse array of nr_outport connections from this component. 112 */ 113 struct coresight_platform_data { 114 int nr_inport; 115 int nr_outport; 116 struct coresight_connection *conns; 117 }; 118 119 /** 120 * struct csdev_access - Abstraction of a CoreSight device access. 121 * 122 * @io_mem : True if the device has memory mapped I/O 123 * @base : When io_mem == true, base address of the component 124 * @read : Read from the given "offset" of the given instance. 125 * @write : Write "val" to the given "offset". 126 */ 127 struct csdev_access { 128 bool io_mem; 129 union { 130 void __iomem *base; 131 struct { 132 u64 (*read)(u32 offset, bool relaxed, bool _64bit); 133 void (*write)(u64 val, u32 offset, bool relaxed, 134 bool _64bit); 135 }; 136 }; 137 }; 138 139 #define CSDEV_ACCESS_IOMEM(_addr) \ 140 ((struct csdev_access) { \ 141 .io_mem = true, \ 142 .base = (_addr), \ 143 }) 144 145 /** 146 * struct coresight_desc - description of a component required from drivers 147 * @type: as defined by @coresight_dev_type. 148 * @subtype: as defined by @coresight_dev_subtype. 149 * @ops: generic operations for this component, as defined 150 * by @coresight_ops. 151 * @pdata: platform data collected from DT. 152 * @dev: The device entity associated to this component. 153 * @groups: operations specific to this component. These will end up 154 * in the component's sysfs sub-directory. 155 * @name: name for the coresight device, also shown under sysfs. 156 * @access: Describe access to the device 157 */ 158 struct coresight_desc { 159 enum coresight_dev_type type; 160 union coresight_dev_subtype subtype; 161 const struct coresight_ops *ops; 162 struct coresight_platform_data *pdata; 163 struct device *dev; 164 const struct attribute_group **groups; 165 const char *name; 166 struct csdev_access access; 167 }; 168 169 /** 170 * struct coresight_connection - representation of a single connection 171 * @outport: a connection's output port number. 172 * @child_port: remote component's port number @output is connected to. 173 * @chid_fwnode: remote component's fwnode handle. 174 * @child_dev: a @coresight_device representation of the component 175 connected to @outport. 176 * @link: Representation of the connection as a sysfs link. 177 */ 178 struct coresight_connection { 179 int outport; 180 int child_port; 181 struct fwnode_handle *child_fwnode; 182 struct coresight_device *child_dev; 183 struct coresight_sysfs_link *link; 184 }; 185 186 /** 187 * struct coresight_sysfs_link - representation of a connection in sysfs. 188 * @orig: Originating (master) coresight device for the link. 189 * @orig_name: Name to use for the link orig->target. 190 * @target: Target (slave) coresight device for the link. 191 * @target_name: Name to use for the link target->orig. 192 */ 193 struct coresight_sysfs_link { 194 struct coresight_device *orig; 195 const char *orig_name; 196 struct coresight_device *target; 197 const char *target_name; 198 }; 199 200 /** 201 * struct coresight_device - representation of a device as used by the framework 202 * @pdata: Platform data with device connections associated to this device. 203 * @type: as defined by @coresight_dev_type. 204 * @subtype: as defined by @coresight_dev_subtype. 205 * @ops: generic operations for this component, as defined 206 * by @coresight_ops. 207 * @access: Device i/o access abstraction for this device. 208 * @dev: The device entity associated to this component. 209 * @refcnt: keep track of what is in use. 210 * @orphan: true if the component has connections that haven't been linked. 211 * @enable: 'true' if component is currently part of an active path. 212 * @activated: 'true' only if a _sink_ has been activated. A sink can be 213 * activated but not yet enabled. Enabling for a _sink_ 214 * happens when a source has been selected and a path is enabled 215 * from source to that sink. 216 * @ea: Device attribute for sink representation under PMU directory. 217 * @def_sink: cached reference to default sink found for this device. 218 * @ect_dev: Associated cross trigger device. Not part of the trace data 219 * path or connections. 220 * @nr_links: number of sysfs links created to other components from this 221 * device. These will appear in the "connections" group. 222 * @has_conns_grp: Have added a "connections" group for sysfs links. 223 * @feature_csdev_list: List of complex feature programming added to the device. 224 * @config_csdev_list: List of system configurations added to the device. 225 * @cscfg_csdev_lock: Protect the lists of configurations and features. 226 * @active_cscfg_ctxt: Context information for current active system configuration. 227 */ 228 struct coresight_device { 229 struct coresight_platform_data *pdata; 230 enum coresight_dev_type type; 231 union coresight_dev_subtype subtype; 232 const struct coresight_ops *ops; 233 struct csdev_access access; 234 struct device dev; 235 atomic_t *refcnt; 236 bool orphan; 237 bool enable; /* true only if configured as part of a path */ 238 /* sink specific fields */ 239 bool activated; /* true only if a sink is part of a path */ 240 struct dev_ext_attribute *ea; 241 struct coresight_device *def_sink; 242 /* cross trigger handling */ 243 struct coresight_device *ect_dev; 244 /* sysfs links between components */ 245 int nr_links; 246 bool has_conns_grp; 247 bool ect_enabled; /* true only if associated ect device is enabled */ 248 /* system configuration and feature lists */ 249 struct list_head feature_csdev_list; 250 struct list_head config_csdev_list; 251 spinlock_t cscfg_csdev_lock; 252 void *active_cscfg_ctxt; 253 }; 254 255 /* 256 * coresight_dev_list - Mapping for devices to "name" index for device 257 * names. 258 * 259 * @nr_idx: Number of entries already allocated. 260 * @pfx: Prefix pattern for device name. 261 * @fwnode_list: Array of fwnode_handles associated with each allocated 262 * index, upto nr_idx entries. 263 */ 264 struct coresight_dev_list { 265 int nr_idx; 266 const char *pfx; 267 struct fwnode_handle **fwnode_list; 268 }; 269 270 #define DEFINE_CORESIGHT_DEVLIST(var, dev_pfx) \ 271 static struct coresight_dev_list (var) = { \ 272 .pfx = dev_pfx, \ 273 .nr_idx = 0, \ 274 .fwnode_list = NULL, \ 275 } 276 277 #define to_coresight_device(d) container_of(d, struct coresight_device, dev) 278 279 #define source_ops(csdev) csdev->ops->source_ops 280 #define sink_ops(csdev) csdev->ops->sink_ops 281 #define link_ops(csdev) csdev->ops->link_ops 282 #define helper_ops(csdev) csdev->ops->helper_ops 283 #define ect_ops(csdev) csdev->ops->ect_ops 284 285 /** 286 * struct coresight_ops_sink - basic operations for a sink 287 * Operations available for sinks 288 * @enable: enables the sink. 289 * @disable: disables the sink. 290 * @alloc_buffer: initialises perf's ring buffer for trace collection. 291 * @free_buffer: release memory allocated in @get_config. 292 * @update_buffer: update buffer pointers after a trace session. 293 */ 294 struct coresight_ops_sink { 295 int (*enable)(struct coresight_device *csdev, u32 mode, void *data); 296 int (*disable)(struct coresight_device *csdev); 297 void *(*alloc_buffer)(struct coresight_device *csdev, 298 struct perf_event *event, void **pages, 299 int nr_pages, bool overwrite); 300 void (*free_buffer)(void *config); 301 unsigned long (*update_buffer)(struct coresight_device *csdev, 302 struct perf_output_handle *handle, 303 void *sink_config); 304 }; 305 306 /** 307 * struct coresight_ops_link - basic operations for a link 308 * Operations available for links. 309 * @enable: enables flow between iport and oport. 310 * @disable: disables flow between iport and oport. 311 */ 312 struct coresight_ops_link { 313 int (*enable)(struct coresight_device *csdev, int iport, int oport); 314 void (*disable)(struct coresight_device *csdev, int iport, int oport); 315 }; 316 317 /** 318 * struct coresight_ops_source - basic operations for a source 319 * Operations available for sources. 320 * @cpu_id: returns the value of the CPU number this component 321 * is associated to. 322 * @trace_id: returns the value of the component's trace ID as known 323 * to the HW. 324 * @enable: enables tracing for a source. 325 * @disable: disables tracing for a source. 326 */ 327 struct coresight_ops_source { 328 int (*cpu_id)(struct coresight_device *csdev); 329 int (*trace_id)(struct coresight_device *csdev); 330 int (*enable)(struct coresight_device *csdev, 331 struct perf_event *event, u32 mode); 332 void (*disable)(struct coresight_device *csdev, 333 struct perf_event *event); 334 }; 335 336 /** 337 * struct coresight_ops_helper - Operations for a helper device. 338 * 339 * All operations could pass in a device specific data, which could 340 * help the helper device to determine what to do. 341 * 342 * @enable : Enable the device 343 * @disable : Disable the device 344 */ 345 struct coresight_ops_helper { 346 int (*enable)(struct coresight_device *csdev, void *data); 347 int (*disable)(struct coresight_device *csdev, void *data); 348 }; 349 350 /** 351 * struct coresight_ops_ect - Ops for an embedded cross trigger device 352 * 353 * @enable : Enable the device 354 * @disable : Disable the device 355 */ 356 struct coresight_ops_ect { 357 int (*enable)(struct coresight_device *csdev); 358 int (*disable)(struct coresight_device *csdev); 359 }; 360 361 struct coresight_ops { 362 const struct coresight_ops_sink *sink_ops; 363 const struct coresight_ops_link *link_ops; 364 const struct coresight_ops_source *source_ops; 365 const struct coresight_ops_helper *helper_ops; 366 const struct coresight_ops_ect *ect_ops; 367 }; 368 369 #if IS_ENABLED(CONFIG_CORESIGHT) 370 371 static inline u32 csdev_access_relaxed_read32(struct csdev_access *csa, 372 u32 offset) 373 { 374 if (likely(csa->io_mem)) 375 return readl_relaxed(csa->base + offset); 376 377 return csa->read(offset, true, false); 378 } 379 380 static inline u32 csdev_access_read32(struct csdev_access *csa, u32 offset) 381 { 382 if (likely(csa->io_mem)) 383 return readl(csa->base + offset); 384 385 return csa->read(offset, false, false); 386 } 387 388 static inline void csdev_access_relaxed_write32(struct csdev_access *csa, 389 u32 val, u32 offset) 390 { 391 if (likely(csa->io_mem)) 392 writel_relaxed(val, csa->base + offset); 393 else 394 csa->write(val, offset, true, false); 395 } 396 397 static inline void csdev_access_write32(struct csdev_access *csa, u32 val, u32 offset) 398 { 399 if (likely(csa->io_mem)) 400 writel(val, csa->base + offset); 401 else 402 csa->write(val, offset, false, false); 403 } 404 405 #ifdef CONFIG_64BIT 406 407 static inline u64 csdev_access_relaxed_read64(struct csdev_access *csa, 408 u32 offset) 409 { 410 if (likely(csa->io_mem)) 411 return readq_relaxed(csa->base + offset); 412 413 return csa->read(offset, true, true); 414 } 415 416 static inline u64 csdev_access_read64(struct csdev_access *csa, u32 offset) 417 { 418 if (likely(csa->io_mem)) 419 return readq(csa->base + offset); 420 421 return csa->read(offset, false, true); 422 } 423 424 static inline void csdev_access_relaxed_write64(struct csdev_access *csa, 425 u64 val, u32 offset) 426 { 427 if (likely(csa->io_mem)) 428 writeq_relaxed(val, csa->base + offset); 429 else 430 csa->write(val, offset, true, true); 431 } 432 433 static inline void csdev_access_write64(struct csdev_access *csa, u64 val, u32 offset) 434 { 435 if (likely(csa->io_mem)) 436 writeq(val, csa->base + offset); 437 else 438 csa->write(val, offset, false, true); 439 } 440 441 #else /* !CONFIG_64BIT */ 442 443 static inline u64 csdev_access_relaxed_read64(struct csdev_access *csa, 444 u32 offset) 445 { 446 WARN_ON(1); 447 return 0; 448 } 449 450 static inline u64 csdev_access_read64(struct csdev_access *csa, u32 offset) 451 { 452 WARN_ON(1); 453 return 0; 454 } 455 456 static inline void csdev_access_relaxed_write64(struct csdev_access *csa, 457 u64 val, u32 offset) 458 { 459 WARN_ON(1); 460 } 461 462 static inline void csdev_access_write64(struct csdev_access *csa, u64 val, u32 offset) 463 { 464 WARN_ON(1); 465 } 466 #endif /* CONFIG_64BIT */ 467 468 static inline bool coresight_is_percpu_source(struct coresight_device *csdev) 469 { 470 return csdev && (csdev->type == CORESIGHT_DEV_TYPE_SOURCE) && 471 (csdev->subtype.source_subtype == CORESIGHT_DEV_SUBTYPE_SOURCE_PROC); 472 } 473 474 static inline bool coresight_is_percpu_sink(struct coresight_device *csdev) 475 { 476 return csdev && (csdev->type == CORESIGHT_DEV_TYPE_SINK) && 477 (csdev->subtype.sink_subtype == CORESIGHT_DEV_SUBTYPE_SINK_PERCPU_SYSMEM); 478 } 479 480 extern struct coresight_device * 481 coresight_register(struct coresight_desc *desc); 482 extern void coresight_unregister(struct coresight_device *csdev); 483 extern int coresight_enable(struct coresight_device *csdev); 484 extern void coresight_disable(struct coresight_device *csdev); 485 extern int coresight_timeout(struct csdev_access *csa, u32 offset, 486 int position, int value); 487 488 extern int coresight_claim_device(struct coresight_device *csdev); 489 extern int coresight_claim_device_unlocked(struct coresight_device *csdev); 490 491 extern void coresight_disclaim_device(struct coresight_device *csdev); 492 extern void coresight_disclaim_device_unlocked(struct coresight_device *csdev); 493 extern char *coresight_alloc_device_name(struct coresight_dev_list *devs, 494 struct device *dev); 495 496 extern bool coresight_loses_context_with_cpu(struct device *dev); 497 498 u32 coresight_relaxed_read32(struct coresight_device *csdev, u32 offset); 499 u32 coresight_read32(struct coresight_device *csdev, u32 offset); 500 void coresight_write32(struct coresight_device *csdev, u32 val, u32 offset); 501 void coresight_relaxed_write32(struct coresight_device *csdev, 502 u32 val, u32 offset); 503 u64 coresight_relaxed_read64(struct coresight_device *csdev, u32 offset); 504 u64 coresight_read64(struct coresight_device *csdev, u32 offset); 505 void coresight_relaxed_write64(struct coresight_device *csdev, 506 u64 val, u32 offset); 507 void coresight_write64(struct coresight_device *csdev, u64 val, u32 offset); 508 509 #else 510 static inline struct coresight_device * 511 coresight_register(struct coresight_desc *desc) { return NULL; } 512 static inline void coresight_unregister(struct coresight_device *csdev) {} 513 static inline int 514 coresight_enable(struct coresight_device *csdev) { return -ENOSYS; } 515 static inline void coresight_disable(struct coresight_device *csdev) {} 516 517 static inline int coresight_timeout(struct csdev_access *csa, u32 offset, 518 int position, int value) 519 { 520 return 1; 521 } 522 523 static inline int coresight_claim_device_unlocked(struct coresight_device *csdev) 524 { 525 return -EINVAL; 526 } 527 528 static inline int coresight_claim_device(struct coresight_device *csdev) 529 { 530 return -EINVAL; 531 } 532 533 static inline void coresight_disclaim_device(struct coresight_device *csdev) {} 534 static inline void coresight_disclaim_device_unlocked(struct coresight_device *csdev) {} 535 536 static inline bool coresight_loses_context_with_cpu(struct device *dev) 537 { 538 return false; 539 } 540 541 static inline u32 coresight_relaxed_read32(struct coresight_device *csdev, u32 offset) 542 { 543 WARN_ON_ONCE(1); 544 return 0; 545 } 546 547 static inline u32 coresight_read32(struct coresight_device *csdev, u32 offset) 548 { 549 WARN_ON_ONCE(1); 550 return 0; 551 } 552 553 static inline void coresight_write32(struct coresight_device *csdev, u32 val, u32 offset) 554 { 555 } 556 557 static inline void coresight_relaxed_write32(struct coresight_device *csdev, 558 u32 val, u32 offset) 559 { 560 } 561 562 static inline u64 coresight_relaxed_read64(struct coresight_device *csdev, 563 u32 offset) 564 { 565 WARN_ON_ONCE(1); 566 return 0; 567 } 568 569 static inline u64 coresight_read64(struct coresight_device *csdev, u32 offset) 570 { 571 WARN_ON_ONCE(1); 572 return 0; 573 } 574 575 static inline void coresight_relaxed_write64(struct coresight_device *csdev, 576 u64 val, u32 offset) 577 { 578 } 579 580 static inline void coresight_write64(struct coresight_device *csdev, u64 val, u32 offset) 581 { 582 } 583 584 #endif /* IS_ENABLED(CONFIG_CORESIGHT) */ 585 586 extern int coresight_get_cpu(struct device *dev); 587 588 struct coresight_platform_data *coresight_get_platform_data(struct device *dev); 589 590 #endif /* _LINUX_COREISGHT_H */ 591