1 /* SPDX-License-Identifier: GPL-2.0 */ 2 /* 3 * Copyright (c) 2012, The Linux Foundation. All rights reserved. 4 */ 5 6 #ifndef _LINUX_CORESIGHT_H 7 #define _LINUX_CORESIGHT_H 8 9 #include <linux/device.h> 10 #include <linux/perf_event.h> 11 #include <linux/sched.h> 12 13 /* Peripheral id registers (0xFD0-0xFEC) */ 14 #define CORESIGHT_PERIPHIDR4 0xfd0 15 #define CORESIGHT_PERIPHIDR5 0xfd4 16 #define CORESIGHT_PERIPHIDR6 0xfd8 17 #define CORESIGHT_PERIPHIDR7 0xfdC 18 #define CORESIGHT_PERIPHIDR0 0xfe0 19 #define CORESIGHT_PERIPHIDR1 0xfe4 20 #define CORESIGHT_PERIPHIDR2 0xfe8 21 #define CORESIGHT_PERIPHIDR3 0xfeC 22 /* Component id registers (0xFF0-0xFFC) */ 23 #define CORESIGHT_COMPIDR0 0xff0 24 #define CORESIGHT_COMPIDR1 0xff4 25 #define CORESIGHT_COMPIDR2 0xff8 26 #define CORESIGHT_COMPIDR3 0xffC 27 28 #define ETM_ARCH_V3_3 0x23 29 #define ETM_ARCH_V3_5 0x25 30 #define PFT_ARCH_V1_0 0x30 31 #define PFT_ARCH_V1_1 0x31 32 33 #define CORESIGHT_UNLOCK 0xc5acce55 34 35 extern struct bus_type coresight_bustype; 36 37 enum coresight_dev_type { 38 CORESIGHT_DEV_TYPE_NONE, 39 CORESIGHT_DEV_TYPE_SINK, 40 CORESIGHT_DEV_TYPE_LINK, 41 CORESIGHT_DEV_TYPE_LINKSINK, 42 CORESIGHT_DEV_TYPE_SOURCE, 43 CORESIGHT_DEV_TYPE_HELPER, 44 CORESIGHT_DEV_TYPE_ECT, 45 }; 46 47 enum coresight_dev_subtype_sink { 48 CORESIGHT_DEV_SUBTYPE_SINK_NONE, 49 CORESIGHT_DEV_SUBTYPE_SINK_PORT, 50 CORESIGHT_DEV_SUBTYPE_SINK_BUFFER, 51 }; 52 53 enum coresight_dev_subtype_link { 54 CORESIGHT_DEV_SUBTYPE_LINK_NONE, 55 CORESIGHT_DEV_SUBTYPE_LINK_MERG, 56 CORESIGHT_DEV_SUBTYPE_LINK_SPLIT, 57 CORESIGHT_DEV_SUBTYPE_LINK_FIFO, 58 }; 59 60 enum coresight_dev_subtype_source { 61 CORESIGHT_DEV_SUBTYPE_SOURCE_NONE, 62 CORESIGHT_DEV_SUBTYPE_SOURCE_PROC, 63 CORESIGHT_DEV_SUBTYPE_SOURCE_BUS, 64 CORESIGHT_DEV_SUBTYPE_SOURCE_SOFTWARE, 65 }; 66 67 enum coresight_dev_subtype_helper { 68 CORESIGHT_DEV_SUBTYPE_HELPER_NONE, 69 CORESIGHT_DEV_SUBTYPE_HELPER_CATU, 70 }; 71 72 /* Embedded Cross Trigger (ECT) sub-types */ 73 enum coresight_dev_subtype_ect { 74 CORESIGHT_DEV_SUBTYPE_ECT_NONE, 75 CORESIGHT_DEV_SUBTYPE_ECT_CTI, 76 }; 77 78 /** 79 * union coresight_dev_subtype - further characterisation of a type 80 * @sink_subtype: type of sink this component is, as defined 81 * by @coresight_dev_subtype_sink. 82 * @link_subtype: type of link this component is, as defined 83 * by @coresight_dev_subtype_link. 84 * @source_subtype: type of source this component is, as defined 85 * by @coresight_dev_subtype_source. 86 * @helper_subtype: type of helper this component is, as defined 87 * by @coresight_dev_subtype_helper. 88 * @ect_subtype: type of cross trigger this component is, as 89 * defined by @coresight_dev_subtype_ect 90 */ 91 union coresight_dev_subtype { 92 /* We have some devices which acts as LINK and SINK */ 93 struct { 94 enum coresight_dev_subtype_sink sink_subtype; 95 enum coresight_dev_subtype_link link_subtype; 96 }; 97 enum coresight_dev_subtype_source source_subtype; 98 enum coresight_dev_subtype_helper helper_subtype; 99 enum coresight_dev_subtype_ect ect_subtype; 100 }; 101 102 /** 103 * struct coresight_platform_data - data harvested from the firmware 104 * specification. 105 * 106 * @nr_inport: Number of elements for the input connections. 107 * @nr_outport: Number of elements for the output connections. 108 * @conns: Sparse array of nr_outport connections from this component. 109 */ 110 struct coresight_platform_data { 111 int nr_inport; 112 int nr_outport; 113 struct coresight_connection *conns; 114 }; 115 116 /** 117 * struct coresight_desc - description of a component required from drivers 118 * @type: as defined by @coresight_dev_type. 119 * @subtype: as defined by @coresight_dev_subtype. 120 * @ops: generic operations for this component, as defined 121 * by @coresight_ops. 122 * @pdata: platform data collected from DT. 123 * @dev: The device entity associated to this component. 124 * @groups: operations specific to this component. These will end up 125 * in the component's sysfs sub-directory. 126 * @name: name for the coresight device, also shown under sysfs. 127 */ 128 struct coresight_desc { 129 enum coresight_dev_type type; 130 union coresight_dev_subtype subtype; 131 const struct coresight_ops *ops; 132 struct coresight_platform_data *pdata; 133 struct device *dev; 134 const struct attribute_group **groups; 135 const char *name; 136 }; 137 138 /** 139 * struct coresight_connection - representation of a single connection 140 * @outport: a connection's output port number. 141 * @child_port: remote component's port number @output is connected to. 142 * @chid_fwnode: remote component's fwnode handle. 143 * @child_dev: a @coresight_device representation of the component 144 connected to @outport. 145 * @link: Representation of the connection as a sysfs link. 146 */ 147 struct coresight_connection { 148 int outport; 149 int child_port; 150 struct fwnode_handle *child_fwnode; 151 struct coresight_device *child_dev; 152 struct coresight_sysfs_link *link; 153 }; 154 155 /** 156 * struct coresight_sysfs_link - representation of a connection in sysfs. 157 * @orig: Originating (master) coresight device for the link. 158 * @orig_name: Name to use for the link orig->target. 159 * @target: Target (slave) coresight device for the link. 160 * @target_name: Name to use for the link target->orig. 161 */ 162 struct coresight_sysfs_link { 163 struct coresight_device *orig; 164 const char *orig_name; 165 struct coresight_device *target; 166 const char *target_name; 167 }; 168 169 /** 170 * struct coresight_device - representation of a device as used by the framework 171 * @pdata: Platform data with device connections associated to this device. 172 * @type: as defined by @coresight_dev_type. 173 * @subtype: as defined by @coresight_dev_subtype. 174 * @ops: generic operations for this component, as defined 175 by @coresight_ops. 176 * @dev: The device entity associated to this component. 177 * @refcnt: keep track of what is in use. 178 * @orphan: true if the component has connections that haven't been linked. 179 * @enable: 'true' if component is currently part of an active path. 180 * @activated: 'true' only if a _sink_ has been activated. A sink can be 181 * activated but not yet enabled. Enabling for a _sink_ 182 * appens when a source has been selected for that it. 183 * @ea: Device attribute for sink representation under PMU directory. 184 * @ect_dev: Associated cross trigger device. Not part of the trace data 185 * path or connections. 186 * @nr_links: number of sysfs links created to other components from this 187 * device. These will appear in the "connections" group. 188 * @has_conns_grp: Have added a "connections" group for sysfs links. 189 */ 190 struct coresight_device { 191 struct coresight_platform_data *pdata; 192 enum coresight_dev_type type; 193 union coresight_dev_subtype subtype; 194 const struct coresight_ops *ops; 195 struct device dev; 196 atomic_t *refcnt; 197 bool orphan; 198 bool enable; /* true only if configured as part of a path */ 199 /* sink specific fields */ 200 bool activated; /* true only if a sink is part of a path */ 201 struct dev_ext_attribute *ea; 202 /* cross trigger handling */ 203 struct coresight_device *ect_dev; 204 /* sysfs links between components */ 205 int nr_links; 206 bool has_conns_grp; 207 }; 208 209 /* 210 * coresight_dev_list - Mapping for devices to "name" index for device 211 * names. 212 * 213 * @nr_idx: Number of entries already allocated. 214 * @pfx: Prefix pattern for device name. 215 * @fwnode_list: Array of fwnode_handles associated with each allocated 216 * index, upto nr_idx entries. 217 */ 218 struct coresight_dev_list { 219 int nr_idx; 220 const char *pfx; 221 struct fwnode_handle **fwnode_list; 222 }; 223 224 #define DEFINE_CORESIGHT_DEVLIST(var, dev_pfx) \ 225 static struct coresight_dev_list (var) = { \ 226 .pfx = dev_pfx, \ 227 .nr_idx = 0, \ 228 .fwnode_list = NULL, \ 229 } 230 231 #define to_coresight_device(d) container_of(d, struct coresight_device, dev) 232 233 #define source_ops(csdev) csdev->ops->source_ops 234 #define sink_ops(csdev) csdev->ops->sink_ops 235 #define link_ops(csdev) csdev->ops->link_ops 236 #define helper_ops(csdev) csdev->ops->helper_ops 237 #define ect_ops(csdev) csdev->ops->ect_ops 238 239 /** 240 * struct coresight_ops_sink - basic operations for a sink 241 * Operations available for sinks 242 * @enable: enables the sink. 243 * @disable: disables the sink. 244 * @alloc_buffer: initialises perf's ring buffer for trace collection. 245 * @free_buffer: release memory allocated in @get_config. 246 * @update_buffer: update buffer pointers after a trace session. 247 */ 248 struct coresight_ops_sink { 249 int (*enable)(struct coresight_device *csdev, u32 mode, void *data); 250 int (*disable)(struct coresight_device *csdev); 251 void *(*alloc_buffer)(struct coresight_device *csdev, 252 struct perf_event *event, void **pages, 253 int nr_pages, bool overwrite); 254 void (*free_buffer)(void *config); 255 unsigned long (*update_buffer)(struct coresight_device *csdev, 256 struct perf_output_handle *handle, 257 void *sink_config); 258 }; 259 260 /** 261 * struct coresight_ops_link - basic operations for a link 262 * Operations available for links. 263 * @enable: enables flow between iport and oport. 264 * @disable: disables flow between iport and oport. 265 */ 266 struct coresight_ops_link { 267 int (*enable)(struct coresight_device *csdev, int iport, int oport); 268 void (*disable)(struct coresight_device *csdev, int iport, int oport); 269 }; 270 271 /** 272 * struct coresight_ops_source - basic operations for a source 273 * Operations available for sources. 274 * @cpu_id: returns the value of the CPU number this component 275 * is associated to. 276 * @trace_id: returns the value of the component's trace ID as known 277 * to the HW. 278 * @enable: enables tracing for a source. 279 * @disable: disables tracing for a source. 280 */ 281 struct coresight_ops_source { 282 int (*cpu_id)(struct coresight_device *csdev); 283 int (*trace_id)(struct coresight_device *csdev); 284 int (*enable)(struct coresight_device *csdev, 285 struct perf_event *event, u32 mode); 286 void (*disable)(struct coresight_device *csdev, 287 struct perf_event *event); 288 }; 289 290 /** 291 * struct coresight_ops_helper - Operations for a helper device. 292 * 293 * All operations could pass in a device specific data, which could 294 * help the helper device to determine what to do. 295 * 296 * @enable : Enable the device 297 * @disable : Disable the device 298 */ 299 struct coresight_ops_helper { 300 int (*enable)(struct coresight_device *csdev, void *data); 301 int (*disable)(struct coresight_device *csdev, void *data); 302 }; 303 304 /** 305 * struct coresight_ops_ect - Ops for an embedded cross trigger device 306 * 307 * @enable : Enable the device 308 * @disable : Disable the device 309 */ 310 struct coresight_ops_ect { 311 int (*enable)(struct coresight_device *csdev); 312 int (*disable)(struct coresight_device *csdev); 313 }; 314 315 struct coresight_ops { 316 const struct coresight_ops_sink *sink_ops; 317 const struct coresight_ops_link *link_ops; 318 const struct coresight_ops_source *source_ops; 319 const struct coresight_ops_helper *helper_ops; 320 const struct coresight_ops_ect *ect_ops; 321 }; 322 323 #ifdef CONFIG_CORESIGHT 324 extern struct coresight_device * 325 coresight_register(struct coresight_desc *desc); 326 extern void coresight_unregister(struct coresight_device *csdev); 327 extern int coresight_enable(struct coresight_device *csdev); 328 extern void coresight_disable(struct coresight_device *csdev); 329 extern int coresight_timeout(void __iomem *addr, u32 offset, 330 int position, int value); 331 332 extern int coresight_claim_device(void __iomem *base); 333 extern int coresight_claim_device_unlocked(void __iomem *base); 334 335 extern void coresight_disclaim_device(void __iomem *base); 336 extern void coresight_disclaim_device_unlocked(void __iomem *base); 337 extern char *coresight_alloc_device_name(struct coresight_dev_list *devs, 338 struct device *dev); 339 340 extern bool coresight_loses_context_with_cpu(struct device *dev); 341 #else 342 static inline struct coresight_device * 343 coresight_register(struct coresight_desc *desc) { return NULL; } 344 static inline void coresight_unregister(struct coresight_device *csdev) {} 345 static inline int 346 coresight_enable(struct coresight_device *csdev) { return -ENOSYS; } 347 static inline void coresight_disable(struct coresight_device *csdev) {} 348 static inline int coresight_timeout(void __iomem *addr, u32 offset, 349 int position, int value) { return 1; } 350 static inline int coresight_claim_device_unlocked(void __iomem *base) 351 { 352 return -EINVAL; 353 } 354 355 static inline int coresight_claim_device(void __iomem *base) 356 { 357 return -EINVAL; 358 } 359 360 static inline void coresight_disclaim_device(void __iomem *base) {} 361 static inline void coresight_disclaim_device_unlocked(void __iomem *base) {} 362 363 static inline bool coresight_loses_context_with_cpu(struct device *dev) 364 { 365 return false; 366 } 367 #endif 368 369 extern int coresight_get_cpu(struct device *dev); 370 371 struct coresight_platform_data *coresight_get_platform_data(struct device *dev); 372 373 #endif 374