1 /* SPDX-License-Identifier: GPL-2.0 */ 2 /* 3 * Copyright (c) 2012, The Linux Foundation. All rights reserved. 4 */ 5 6 #ifndef _LINUX_CORESIGHT_H 7 #define _LINUX_CORESIGHT_H 8 9 #include <linux/amba/bus.h> 10 #include <linux/clk.h> 11 #include <linux/device.h> 12 #include <linux/io.h> 13 #include <linux/perf_event.h> 14 #include <linux/sched.h> 15 #include <linux/platform_device.h> 16 17 /* Peripheral id registers (0xFD0-0xFEC) */ 18 #define CORESIGHT_PERIPHIDR4 0xfd0 19 #define CORESIGHT_PERIPHIDR5 0xfd4 20 #define CORESIGHT_PERIPHIDR6 0xfd8 21 #define CORESIGHT_PERIPHIDR7 0xfdC 22 #define CORESIGHT_PERIPHIDR0 0xfe0 23 #define CORESIGHT_PERIPHIDR1 0xfe4 24 #define CORESIGHT_PERIPHIDR2 0xfe8 25 #define CORESIGHT_PERIPHIDR3 0xfeC 26 /* Component id registers (0xFF0-0xFFC) */ 27 #define CORESIGHT_COMPIDR0 0xff0 28 #define CORESIGHT_COMPIDR1 0xff4 29 #define CORESIGHT_COMPIDR2 0xff8 30 #define CORESIGHT_COMPIDR3 0xffC 31 32 #define ETM_ARCH_V3_3 0x23 33 #define ETM_ARCH_V3_5 0x25 34 #define PFT_ARCH_V1_0 0x30 35 #define PFT_ARCH_V1_1 0x31 36 37 #define CORESIGHT_UNLOCK 0xc5acce55 38 39 extern const struct bus_type coresight_bustype; 40 41 enum coresight_dev_type { 42 CORESIGHT_DEV_TYPE_SINK, 43 CORESIGHT_DEV_TYPE_LINK, 44 CORESIGHT_DEV_TYPE_LINKSINK, 45 CORESIGHT_DEV_TYPE_SOURCE, 46 CORESIGHT_DEV_TYPE_HELPER, 47 CORESIGHT_DEV_TYPE_MAX 48 }; 49 50 enum coresight_dev_subtype_sink { 51 CORESIGHT_DEV_SUBTYPE_SINK_DUMMY, 52 CORESIGHT_DEV_SUBTYPE_SINK_PORT, 53 CORESIGHT_DEV_SUBTYPE_SINK_BUFFER, 54 CORESIGHT_DEV_SUBTYPE_SINK_SYSMEM, 55 CORESIGHT_DEV_SUBTYPE_SINK_PERCPU_SYSMEM, 56 }; 57 58 enum coresight_dev_subtype_link { 59 CORESIGHT_DEV_SUBTYPE_LINK_MERG, 60 CORESIGHT_DEV_SUBTYPE_LINK_SPLIT, 61 CORESIGHT_DEV_SUBTYPE_LINK_FIFO, 62 }; 63 64 enum coresight_dev_subtype_source { 65 CORESIGHT_DEV_SUBTYPE_SOURCE_PROC, 66 CORESIGHT_DEV_SUBTYPE_SOURCE_BUS, 67 CORESIGHT_DEV_SUBTYPE_SOURCE_SOFTWARE, 68 CORESIGHT_DEV_SUBTYPE_SOURCE_TPDM, 69 CORESIGHT_DEV_SUBTYPE_SOURCE_OTHERS, 70 }; 71 72 enum coresight_dev_subtype_helper { 73 CORESIGHT_DEV_SUBTYPE_HELPER_CATU, 74 CORESIGHT_DEV_SUBTYPE_HELPER_ECT_CTI, 75 CORESIGHT_DEV_SUBTYPE_HELPER_CTCU, 76 }; 77 78 /** 79 * union coresight_dev_subtype - further characterisation of a type 80 * @sink_subtype: type of sink this component is, as defined 81 * by @coresight_dev_subtype_sink. 82 * @link_subtype: type of link this component is, as defined 83 * by @coresight_dev_subtype_link. 84 * @source_subtype: type of source this component is, as defined 85 * by @coresight_dev_subtype_source. 86 * @helper_subtype: type of helper this component is, as defined 87 * by @coresight_dev_subtype_helper. 88 */ 89 union coresight_dev_subtype { 90 /* We have some devices which acts as LINK and SINK */ 91 struct { 92 enum coresight_dev_subtype_sink sink_subtype; 93 enum coresight_dev_subtype_link link_subtype; 94 }; 95 enum coresight_dev_subtype_source source_subtype; 96 enum coresight_dev_subtype_helper helper_subtype; 97 }; 98 99 /** 100 * struct coresight_platform_data - data harvested from the firmware 101 * specification. 102 * 103 * @nr_inconns: Number of elements for the input connections. 104 * @nr_outconns: Number of elements for the output connections. 105 * @out_conns: Array of nr_outconns pointers to connections from this 106 * component. 107 * @in_conns: Sparse array of pointers to input connections. Sparse 108 * because the source device owns the connection so when it's 109 * unloaded the connection leaves an empty slot. 110 */ 111 struct coresight_platform_data { 112 int nr_inconns; 113 int nr_outconns; 114 struct coresight_connection **out_conns; 115 struct coresight_connection **in_conns; 116 }; 117 118 /** 119 * struct csdev_access - Abstraction of a CoreSight device access. 120 * 121 * @io_mem : True if the device has memory mapped I/O 122 * @base : When io_mem == true, base address of the component 123 * @read : Read from the given "offset" of the given instance. 124 * @write : Write "val" to the given "offset". 125 */ 126 struct csdev_access { 127 bool io_mem; 128 union { 129 void __iomem *base; 130 struct { 131 u64 (*read)(u32 offset, bool relaxed, bool _64bit); 132 void (*write)(u64 val, u32 offset, bool relaxed, 133 bool _64bit); 134 }; 135 }; 136 }; 137 138 #define CSDEV_ACCESS_IOMEM(_addr) \ 139 ((struct csdev_access) { \ 140 .io_mem = true, \ 141 .base = (_addr), \ 142 }) 143 144 /** 145 * struct coresight_desc - description of a component required from drivers 146 * @type: as defined by @coresight_dev_type. 147 * @subtype: as defined by @coresight_dev_subtype. 148 * @ops: generic operations for this component, as defined 149 * by @coresight_ops. 150 * @pdata: platform data collected from DT. 151 * @dev: The device entity associated to this component. 152 * @groups: operations specific to this component. These will end up 153 * in the component's sysfs sub-directory. 154 * @name: name for the coresight device, also shown under sysfs. 155 * @access: Describe access to the device 156 */ 157 struct coresight_desc { 158 enum coresight_dev_type type; 159 union coresight_dev_subtype subtype; 160 const struct coresight_ops *ops; 161 struct coresight_platform_data *pdata; 162 struct device *dev; 163 const struct attribute_group **groups; 164 const char *name; 165 struct csdev_access access; 166 }; 167 168 /** 169 * struct coresight_connection - representation of a single connection 170 * @src_port: a connection's output port number. 171 * @dest_port: destination's input port number @src_port is connected to. 172 * @dest_fwnode: destination component's fwnode handle. 173 * @dest_dev: a @coresight_device representation of the component 174 connected to @src_port. NULL until the device is created 175 * @link: Representation of the connection as a sysfs link. 176 * @filter_src_fwnode: filter source component's fwnode handle. 177 * @filter_src_dev: a @coresight_device representation of the component that 178 needs to be filtered. 179 * 180 * The full connection structure looks like this, where in_conns store 181 * references to same connection as the source device's out_conns. 182 * 183 * +-----------------------------+ +-----------------------------+ 184 * |coresight_device | |coresight_connection | 185 * |-----------------------------| |-----------------------------| 186 * | | | | 187 * | | | dest_dev*|<-- 188 * |pdata->out_conns[nr_outconns]|<->|src_dev* | | 189 * | | | | | 190 * +-----------------------------+ +-----------------------------+ | 191 * | 192 * +-----------------------------+ | 193 * |coresight_device | | 194 * |------------------------------ | 195 * | | | 196 * | pdata->in_conns[nr_inconns]|<-- 197 * | | 198 * +-----------------------------+ 199 */ 200 struct coresight_connection { 201 int src_port; 202 int dest_port; 203 struct fwnode_handle *dest_fwnode; 204 struct coresight_device *dest_dev; 205 struct coresight_sysfs_link *link; 206 struct coresight_device *src_dev; 207 struct fwnode_handle *filter_src_fwnode; 208 struct coresight_device *filter_src_dev; 209 int src_refcnt; 210 int dest_refcnt; 211 }; 212 213 /** 214 * struct coresight_sysfs_link - representation of a connection in sysfs. 215 * @orig: Originating (master) coresight device for the link. 216 * @orig_name: Name to use for the link orig->target. 217 * @target: Target (slave) coresight device for the link. 218 * @target_name: Name to use for the link target->orig. 219 */ 220 struct coresight_sysfs_link { 221 struct coresight_device *orig; 222 const char *orig_name; 223 struct coresight_device *target; 224 const char *target_name; 225 }; 226 227 /* architecturally we have 128 IDs some of which are reserved */ 228 #define CORESIGHT_TRACE_IDS_MAX 128 229 230 /** 231 * Trace ID map. 232 * 233 * @used_ids: Bitmap to register available (bit = 0) and in use (bit = 1) IDs. 234 * Initialised so that the reserved IDs are permanently marked as 235 * in use. 236 * @perf_cs_etm_session_active: Number of Perf sessions using this ID map. 237 */ 238 struct coresight_trace_id_map { 239 DECLARE_BITMAP(used_ids, CORESIGHT_TRACE_IDS_MAX); 240 atomic_t __percpu *cpu_map; 241 atomic_t perf_cs_etm_session_active; 242 raw_spinlock_t lock; 243 }; 244 245 /** 246 * struct coresight_device - representation of a device as used by the framework 247 * @pdata: Platform data with device connections associated to this device. 248 * @type: as defined by @coresight_dev_type. 249 * @subtype: as defined by @coresight_dev_subtype. 250 * @ops: generic operations for this component, as defined 251 * by @coresight_ops. 252 * @access: Device i/o access abstraction for this device. 253 * @dev: The device entity associated to this component. 254 * @mode: This tracer's mode, i.e sysFS, Perf or disabled. This is 255 * actually an 'enum cs_mode', but is stored in an atomic type. 256 * This is always accessed through local_read() and local_set(), 257 * but wherever it's done from within the Coresight device's lock, 258 * a non-atomic read would also work. This is the main point of 259 * synchronisation between code happening inside the sysfs mode's 260 * coresight_mutex and outside when running in Perf mode. A compare 261 * and exchange swap is done to atomically claim one mode or the 262 * other. 263 * @refcnt: keep track of what is in use. Only access this outside of the 264 * device's spinlock when the coresight_mutex held and mode == 265 * CS_MODE_SYSFS. Otherwise it must be accessed from inside the 266 * spinlock. 267 * @orphan: true if the component has connections that haven't been linked. 268 * @sysfs_sink_activated: 'true' when a sink has been selected for use via sysfs 269 * by writing a 1 to the 'enable_sink' file. A sink can be 270 * activated but not yet enabled. Enabling for a _sink_ happens 271 * when a source has been selected and a path is enabled from 272 * source to that sink. A sink can also become enabled but not 273 * activated if it's used via Perf. 274 * @ea: Device attribute for sink representation under PMU directory. 275 * @def_sink: cached reference to default sink found for this device. 276 * @nr_links: number of sysfs links created to other components from this 277 * device. These will appear in the "connections" group. 278 * @has_conns_grp: Have added a "connections" group for sysfs links. 279 * @feature_csdev_list: List of complex feature programming added to the device. 280 * @config_csdev_list: List of system configurations added to the device. 281 * @cscfg_csdev_lock: Protect the lists of configurations and features. 282 * @active_cscfg_ctxt: Context information for current active system configuration. 283 */ 284 struct coresight_device { 285 struct coresight_platform_data *pdata; 286 enum coresight_dev_type type; 287 union coresight_dev_subtype subtype; 288 const struct coresight_ops *ops; 289 struct csdev_access access; 290 struct device dev; 291 local_t mode; 292 int refcnt; 293 bool orphan; 294 /* sink specific fields */ 295 bool sysfs_sink_activated; 296 struct dev_ext_attribute *ea; 297 struct coresight_device *def_sink; 298 struct coresight_trace_id_map perf_sink_id_map; 299 /* sysfs links between components */ 300 int nr_links; 301 bool has_conns_grp; 302 /* system configuration and feature lists */ 303 struct list_head feature_csdev_list; 304 struct list_head config_csdev_list; 305 raw_spinlock_t cscfg_csdev_lock; 306 void *active_cscfg_ctxt; 307 }; 308 309 /* 310 * coresight_dev_list - Mapping for devices to "name" index for device 311 * names. 312 * 313 * @nr_idx: Number of entries already allocated. 314 * @pfx: Prefix pattern for device name. 315 * @fwnode_list: Array of fwnode_handles associated with each allocated 316 * index, upto nr_idx entries. 317 */ 318 struct coresight_dev_list { 319 int nr_idx; 320 const char *pfx; 321 struct fwnode_handle **fwnode_list; 322 }; 323 324 #define DEFINE_CORESIGHT_DEVLIST(var, dev_pfx) \ 325 static struct coresight_dev_list (var) = { \ 326 .pfx = dev_pfx, \ 327 .nr_idx = 0, \ 328 .fwnode_list = NULL, \ 329 } 330 331 #define to_coresight_device(d) container_of(d, struct coresight_device, dev) 332 333 /** 334 * struct coresight_path - data needed by enable/disable path 335 * @path_list: path from source to sink. 336 * @trace_id: trace_id of the whole path. 337 */ 338 struct coresight_path { 339 struct list_head path_list; 340 u8 trace_id; 341 }; 342 343 enum cs_mode { 344 CS_MODE_DISABLED, 345 CS_MODE_SYSFS, 346 CS_MODE_PERF, 347 }; 348 349 #define coresight_ops(csdev) csdev->ops 350 #define source_ops(csdev) csdev->ops->source_ops 351 #define sink_ops(csdev) csdev->ops->sink_ops 352 #define link_ops(csdev) csdev->ops->link_ops 353 #define helper_ops(csdev) csdev->ops->helper_ops 354 #define ect_ops(csdev) csdev->ops->ect_ops 355 #define panic_ops(csdev) csdev->ops->panic_ops 356 357 /** 358 * struct coresight_ops_sink - basic operations for a sink 359 * Operations available for sinks 360 * @enable: enables the sink. 361 * @disable: disables the sink. 362 * @alloc_buffer: initialises perf's ring buffer for trace collection. 363 * @free_buffer: release memory allocated in @get_config. 364 * @update_buffer: update buffer pointers after a trace session. 365 */ 366 struct coresight_ops_sink { 367 int (*enable)(struct coresight_device *csdev, enum cs_mode mode, 368 void *data); 369 int (*disable)(struct coresight_device *csdev); 370 void *(*alloc_buffer)(struct coresight_device *csdev, 371 struct perf_event *event, void **pages, 372 int nr_pages, bool overwrite); 373 void (*free_buffer)(void *config); 374 unsigned long (*update_buffer)(struct coresight_device *csdev, 375 struct perf_output_handle *handle, 376 void *sink_config); 377 }; 378 379 /** 380 * struct coresight_ops_link - basic operations for a link 381 * Operations available for links. 382 * @enable: enables flow between iport and oport. 383 * @disable: disables flow between iport and oport. 384 */ 385 struct coresight_ops_link { 386 int (*enable)(struct coresight_device *csdev, 387 struct coresight_connection *in, 388 struct coresight_connection *out); 389 void (*disable)(struct coresight_device *csdev, 390 struct coresight_connection *in, 391 struct coresight_connection *out); 392 }; 393 394 /** 395 * struct coresight_ops_source - basic operations for a source 396 * Operations available for sources. 397 * @cpu_id: returns the value of the CPU number this component 398 * is associated to. 399 * @enable: enables tracing for a source. 400 * @disable: disables tracing for a source. 401 */ 402 struct coresight_ops_source { 403 int (*cpu_id)(struct coresight_device *csdev); 404 int (*enable)(struct coresight_device *csdev, struct perf_event *event, 405 enum cs_mode mode, struct coresight_path *path); 406 void (*disable)(struct coresight_device *csdev, 407 struct perf_event *event); 408 }; 409 410 /** 411 * struct coresight_ops_helper - Operations for a helper device. 412 * 413 * All operations could pass in a device specific data, which could 414 * help the helper device to determine what to do. 415 * 416 * @enable : Enable the device 417 * @disable : Disable the device 418 */ 419 struct coresight_ops_helper { 420 int (*enable)(struct coresight_device *csdev, enum cs_mode mode, 421 void *data); 422 int (*disable)(struct coresight_device *csdev, void *data); 423 }; 424 425 426 /** 427 * struct coresight_ops_panic - Generic device ops for panic handing 428 * 429 * @sync : Sync the device register state/trace data 430 */ 431 struct coresight_ops_panic { 432 int (*sync)(struct coresight_device *csdev); 433 }; 434 435 struct coresight_ops { 436 int (*trace_id)(struct coresight_device *csdev, enum cs_mode mode, 437 struct coresight_device *sink); 438 const struct coresight_ops_sink *sink_ops; 439 const struct coresight_ops_link *link_ops; 440 const struct coresight_ops_source *source_ops; 441 const struct coresight_ops_helper *helper_ops; 442 const struct coresight_ops_panic *panic_ops; 443 }; 444 445 static inline u32 csdev_access_relaxed_read32(struct csdev_access *csa, 446 u32 offset) 447 { 448 if (likely(csa->io_mem)) 449 return readl_relaxed(csa->base + offset); 450 451 return csa->read(offset, true, false); 452 } 453 454 #define CORESIGHT_CIDRn(i) (0xFF0 + ((i) * 4)) 455 456 static inline u32 coresight_get_cid(void __iomem *base) 457 { 458 u32 i, cid = 0; 459 460 for (i = 0; i < 4; i++) 461 cid |= readl(base + CORESIGHT_CIDRn(i)) << (i * 8); 462 463 return cid; 464 } 465 466 static inline bool is_coresight_device(void __iomem *base) 467 { 468 u32 cid = coresight_get_cid(base); 469 470 return cid == CORESIGHT_CID; 471 } 472 473 /* 474 * Attempt to find and enable "APB clock" for the given device 475 * 476 * Returns: 477 * 478 * clk - Clock is found and enabled 479 * NULL - clock is not found 480 * ERROR - Clock is found but failed to enable 481 */ 482 static inline struct clk *coresight_get_enable_apb_pclk(struct device *dev) 483 { 484 struct clk *pclk; 485 int ret; 486 487 pclk = clk_get(dev, "apb_pclk"); 488 if (IS_ERR(pclk)) { 489 pclk = clk_get(dev, "apb"); 490 if (IS_ERR(pclk)) 491 return NULL; 492 } 493 494 ret = clk_prepare_enable(pclk); 495 if (ret) { 496 clk_put(pclk); 497 return ERR_PTR(ret); 498 } 499 return pclk; 500 } 501 502 #define CORESIGHT_PIDRn(i) (0xFE0 + ((i) * 4)) 503 504 static inline u32 coresight_get_pid(struct csdev_access *csa) 505 { 506 u32 i, pid = 0; 507 508 for (i = 0; i < 4; i++) 509 pid |= csdev_access_relaxed_read32(csa, CORESIGHT_PIDRn(i)) << (i * 8); 510 511 return pid; 512 } 513 514 static inline u64 csdev_access_relaxed_read_pair(struct csdev_access *csa, 515 u32 lo_offset, u32 hi_offset) 516 { 517 if (likely(csa->io_mem)) { 518 return readl_relaxed(csa->base + lo_offset) | 519 ((u64)readl_relaxed(csa->base + hi_offset) << 32); 520 } 521 522 return csa->read(lo_offset, true, false) | (csa->read(hi_offset, true, false) << 32); 523 } 524 525 static inline void csdev_access_relaxed_write_pair(struct csdev_access *csa, u64 val, 526 u32 lo_offset, u32 hi_offset) 527 { 528 if (likely(csa->io_mem)) { 529 writel_relaxed((u32)val, csa->base + lo_offset); 530 writel_relaxed((u32)(val >> 32), csa->base + hi_offset); 531 } else { 532 csa->write((u32)val, lo_offset, true, false); 533 csa->write((u32)(val >> 32), hi_offset, true, false); 534 } 535 } 536 537 static inline u32 csdev_access_read32(struct csdev_access *csa, u32 offset) 538 { 539 if (likely(csa->io_mem)) 540 return readl(csa->base + offset); 541 542 return csa->read(offset, false, false); 543 } 544 545 static inline void csdev_access_relaxed_write32(struct csdev_access *csa, 546 u32 val, u32 offset) 547 { 548 if (likely(csa->io_mem)) 549 writel_relaxed(val, csa->base + offset); 550 else 551 csa->write(val, offset, true, false); 552 } 553 554 static inline void csdev_access_write32(struct csdev_access *csa, u32 val, u32 offset) 555 { 556 if (likely(csa->io_mem)) 557 writel(val, csa->base + offset); 558 else 559 csa->write(val, offset, false, false); 560 } 561 562 #ifdef CONFIG_64BIT 563 564 static inline u64 csdev_access_relaxed_read64(struct csdev_access *csa, 565 u32 offset) 566 { 567 if (likely(csa->io_mem)) 568 return readq_relaxed(csa->base + offset); 569 570 return csa->read(offset, true, true); 571 } 572 573 static inline u64 csdev_access_read64(struct csdev_access *csa, u32 offset) 574 { 575 if (likely(csa->io_mem)) 576 return readq(csa->base + offset); 577 578 return csa->read(offset, false, true); 579 } 580 581 static inline void csdev_access_relaxed_write64(struct csdev_access *csa, 582 u64 val, u32 offset) 583 { 584 if (likely(csa->io_mem)) 585 writeq_relaxed(val, csa->base + offset); 586 else 587 csa->write(val, offset, true, true); 588 } 589 590 static inline void csdev_access_write64(struct csdev_access *csa, u64 val, u32 offset) 591 { 592 if (likely(csa->io_mem)) 593 writeq(val, csa->base + offset); 594 else 595 csa->write(val, offset, false, true); 596 } 597 598 #else /* !CONFIG_64BIT */ 599 600 static inline u64 csdev_access_relaxed_read64(struct csdev_access *csa, 601 u32 offset) 602 { 603 WARN_ON(1); 604 return 0; 605 } 606 607 static inline u64 csdev_access_read64(struct csdev_access *csa, u32 offset) 608 { 609 WARN_ON(1); 610 return 0; 611 } 612 613 static inline void csdev_access_relaxed_write64(struct csdev_access *csa, 614 u64 val, u32 offset) 615 { 616 WARN_ON(1); 617 } 618 619 static inline void csdev_access_write64(struct csdev_access *csa, u64 val, u32 offset) 620 { 621 WARN_ON(1); 622 } 623 #endif /* CONFIG_64BIT */ 624 625 static inline bool coresight_is_device_source(struct coresight_device *csdev) 626 { 627 return csdev && (csdev->type == CORESIGHT_DEV_TYPE_SOURCE); 628 } 629 630 static inline bool coresight_is_percpu_source(struct coresight_device *csdev) 631 { 632 return csdev && coresight_is_device_source(csdev) && 633 (csdev->subtype.source_subtype == CORESIGHT_DEV_SUBTYPE_SOURCE_PROC); 634 } 635 636 static inline bool coresight_is_percpu_sink(struct coresight_device *csdev) 637 { 638 return csdev && (csdev->type == CORESIGHT_DEV_TYPE_SINK) && 639 (csdev->subtype.sink_subtype == CORESIGHT_DEV_SUBTYPE_SINK_PERCPU_SYSMEM); 640 } 641 642 /* 643 * Atomically try to take the device and set a new mode. Returns true on 644 * success, false if the device is already taken by someone else. 645 */ 646 static inline bool coresight_take_mode(struct coresight_device *csdev, 647 enum cs_mode new_mode) 648 { 649 return local_cmpxchg(&csdev->mode, CS_MODE_DISABLED, new_mode) == 650 CS_MODE_DISABLED; 651 } 652 653 static inline enum cs_mode coresight_get_mode(struct coresight_device *csdev) 654 { 655 return local_read(&csdev->mode); 656 } 657 658 static inline void coresight_set_mode(struct coresight_device *csdev, 659 enum cs_mode new_mode) 660 { 661 enum cs_mode current_mode = coresight_get_mode(csdev); 662 663 /* 664 * Changing to a new mode must be done from an already disabled state 665 * unless it's synchronized with coresight_take_mode(). Otherwise the 666 * device is already in use and signifies a locking issue. 667 */ 668 WARN(new_mode != CS_MODE_DISABLED && current_mode != CS_MODE_DISABLED && 669 current_mode != new_mode, "Device already in use\n"); 670 671 local_set(&csdev->mode, new_mode); 672 } 673 674 extern struct coresight_device * 675 coresight_register(struct coresight_desc *desc); 676 extern void coresight_unregister(struct coresight_device *csdev); 677 extern int coresight_enable_sysfs(struct coresight_device *csdev); 678 extern void coresight_disable_sysfs(struct coresight_device *csdev); 679 extern int coresight_timeout(struct csdev_access *csa, u32 offset, 680 int position, int value); 681 typedef void (*coresight_timeout_cb_t) (struct csdev_access *, u32, int, int); 682 extern int coresight_timeout_action(struct csdev_access *csa, u32 offset, 683 int position, int value, 684 coresight_timeout_cb_t cb); 685 686 extern int coresight_claim_device(struct coresight_device *csdev); 687 extern int coresight_claim_device_unlocked(struct coresight_device *csdev); 688 689 extern void coresight_disclaim_device(struct coresight_device *csdev); 690 extern void coresight_disclaim_device_unlocked(struct coresight_device *csdev); 691 extern char *coresight_alloc_device_name(struct coresight_dev_list *devs, 692 struct device *dev); 693 694 extern bool coresight_loses_context_with_cpu(struct device *dev); 695 696 u32 coresight_relaxed_read32(struct coresight_device *csdev, u32 offset); 697 u32 coresight_read32(struct coresight_device *csdev, u32 offset); 698 void coresight_write32(struct coresight_device *csdev, u32 val, u32 offset); 699 void coresight_relaxed_write32(struct coresight_device *csdev, 700 u32 val, u32 offset); 701 u64 coresight_relaxed_read64(struct coresight_device *csdev, u32 offset); 702 u64 coresight_read64(struct coresight_device *csdev, u32 offset); 703 void coresight_relaxed_write64(struct coresight_device *csdev, 704 u64 val, u32 offset); 705 void coresight_write64(struct coresight_device *csdev, u64 val, u32 offset); 706 707 extern int coresight_get_cpu(struct device *dev); 708 extern int coresight_get_static_trace_id(struct device *dev, u32 *id); 709 710 struct coresight_platform_data *coresight_get_platform_data(struct device *dev); 711 struct coresight_connection * 712 coresight_add_out_conn(struct device *dev, 713 struct coresight_platform_data *pdata, 714 const struct coresight_connection *new_conn); 715 int coresight_add_in_conn(struct coresight_connection *conn); 716 struct coresight_device * 717 coresight_find_input_type(struct coresight_platform_data *pdata, 718 enum coresight_dev_type type, 719 union coresight_dev_subtype subtype); 720 struct coresight_device * 721 coresight_find_output_type(struct coresight_platform_data *pdata, 722 enum coresight_dev_type type, 723 union coresight_dev_subtype subtype); 724 725 int coresight_init_driver(const char *drv, struct amba_driver *amba_drv, 726 struct platform_driver *pdev_drv); 727 728 void coresight_remove_driver(struct amba_driver *amba_drv, 729 struct platform_driver *pdev_drv); 730 int coresight_etm_get_trace_id(struct coresight_device *csdev, enum cs_mode mode, 731 struct coresight_device *sink); 732 #endif /* _LINUX_COREISGHT_H */ 733