1 /* SPDX-License-Identifier: GPL-2.0 */ 2 /* 3 * Copyright (c) 2012, The Linux Foundation. All rights reserved. 4 */ 5 6 #ifndef _LINUX_CORESIGHT_H 7 #define _LINUX_CORESIGHT_H 8 9 #include <linux/amba/bus.h> 10 #include <linux/clk.h> 11 #include <linux/device.h> 12 #include <linux/io.h> 13 #include <linux/perf_event.h> 14 #include <linux/sched.h> 15 16 /* Peripheral id registers (0xFD0-0xFEC) */ 17 #define CORESIGHT_PERIPHIDR4 0xfd0 18 #define CORESIGHT_PERIPHIDR5 0xfd4 19 #define CORESIGHT_PERIPHIDR6 0xfd8 20 #define CORESIGHT_PERIPHIDR7 0xfdC 21 #define CORESIGHT_PERIPHIDR0 0xfe0 22 #define CORESIGHT_PERIPHIDR1 0xfe4 23 #define CORESIGHT_PERIPHIDR2 0xfe8 24 #define CORESIGHT_PERIPHIDR3 0xfeC 25 /* Component id registers (0xFF0-0xFFC) */ 26 #define CORESIGHT_COMPIDR0 0xff0 27 #define CORESIGHT_COMPIDR1 0xff4 28 #define CORESIGHT_COMPIDR2 0xff8 29 #define CORESIGHT_COMPIDR3 0xffC 30 31 #define ETM_ARCH_V3_3 0x23 32 #define ETM_ARCH_V3_5 0x25 33 #define PFT_ARCH_V1_0 0x30 34 #define PFT_ARCH_V1_1 0x31 35 36 #define CORESIGHT_UNLOCK 0xc5acce55 37 38 extern const struct bus_type coresight_bustype; 39 40 enum coresight_dev_type { 41 CORESIGHT_DEV_TYPE_SINK, 42 CORESIGHT_DEV_TYPE_LINK, 43 CORESIGHT_DEV_TYPE_LINKSINK, 44 CORESIGHT_DEV_TYPE_SOURCE, 45 CORESIGHT_DEV_TYPE_HELPER, 46 CORESIGHT_DEV_TYPE_MAX 47 }; 48 49 enum coresight_dev_subtype_sink { 50 CORESIGHT_DEV_SUBTYPE_SINK_DUMMY, 51 CORESIGHT_DEV_SUBTYPE_SINK_PORT, 52 CORESIGHT_DEV_SUBTYPE_SINK_BUFFER, 53 CORESIGHT_DEV_SUBTYPE_SINK_SYSMEM, 54 CORESIGHT_DEV_SUBTYPE_SINK_PERCPU_SYSMEM, 55 }; 56 57 enum coresight_dev_subtype_link { 58 CORESIGHT_DEV_SUBTYPE_LINK_MERG, 59 CORESIGHT_DEV_SUBTYPE_LINK_SPLIT, 60 CORESIGHT_DEV_SUBTYPE_LINK_FIFO, 61 }; 62 63 enum coresight_dev_subtype_source { 64 CORESIGHT_DEV_SUBTYPE_SOURCE_PROC, 65 CORESIGHT_DEV_SUBTYPE_SOURCE_BUS, 66 CORESIGHT_DEV_SUBTYPE_SOURCE_SOFTWARE, 67 CORESIGHT_DEV_SUBTYPE_SOURCE_TPDM, 68 CORESIGHT_DEV_SUBTYPE_SOURCE_OTHERS, 69 }; 70 71 enum coresight_dev_subtype_helper { 72 CORESIGHT_DEV_SUBTYPE_HELPER_CATU, 73 CORESIGHT_DEV_SUBTYPE_HELPER_ECT_CTI 74 }; 75 76 /** 77 * union coresight_dev_subtype - further characterisation of a type 78 * @sink_subtype: type of sink this component is, as defined 79 * by @coresight_dev_subtype_sink. 80 * @link_subtype: type of link this component is, as defined 81 * by @coresight_dev_subtype_link. 82 * @source_subtype: type of source this component is, as defined 83 * by @coresight_dev_subtype_source. 84 * @helper_subtype: type of helper this component is, as defined 85 * by @coresight_dev_subtype_helper. 86 */ 87 union coresight_dev_subtype { 88 /* We have some devices which acts as LINK and SINK */ 89 struct { 90 enum coresight_dev_subtype_sink sink_subtype; 91 enum coresight_dev_subtype_link link_subtype; 92 }; 93 enum coresight_dev_subtype_source source_subtype; 94 enum coresight_dev_subtype_helper helper_subtype; 95 }; 96 97 /** 98 * struct coresight_platform_data - data harvested from the firmware 99 * specification. 100 * 101 * @nr_inconns: Number of elements for the input connections. 102 * @nr_outconns: Number of elements for the output connections. 103 * @out_conns: Array of nr_outconns pointers to connections from this 104 * component. 105 * @in_conns: Sparse array of pointers to input connections. Sparse 106 * because the source device owns the connection so when it's 107 * unloaded the connection leaves an empty slot. 108 */ 109 struct coresight_platform_data { 110 int nr_inconns; 111 int nr_outconns; 112 struct coresight_connection **out_conns; 113 struct coresight_connection **in_conns; 114 }; 115 116 /** 117 * struct csdev_access - Abstraction of a CoreSight device access. 118 * 119 * @io_mem : True if the device has memory mapped I/O 120 * @base : When io_mem == true, base address of the component 121 * @read : Read from the given "offset" of the given instance. 122 * @write : Write "val" to the given "offset". 123 */ 124 struct csdev_access { 125 bool io_mem; 126 union { 127 void __iomem *base; 128 struct { 129 u64 (*read)(u32 offset, bool relaxed, bool _64bit); 130 void (*write)(u64 val, u32 offset, bool relaxed, 131 bool _64bit); 132 }; 133 }; 134 }; 135 136 #define CSDEV_ACCESS_IOMEM(_addr) \ 137 ((struct csdev_access) { \ 138 .io_mem = true, \ 139 .base = (_addr), \ 140 }) 141 142 /** 143 * struct coresight_desc - description of a component required from drivers 144 * @type: as defined by @coresight_dev_type. 145 * @subtype: as defined by @coresight_dev_subtype. 146 * @ops: generic operations for this component, as defined 147 * by @coresight_ops. 148 * @pdata: platform data collected from DT. 149 * @dev: The device entity associated to this component. 150 * @groups: operations specific to this component. These will end up 151 * in the component's sysfs sub-directory. 152 * @name: name for the coresight device, also shown under sysfs. 153 * @access: Describe access to the device 154 */ 155 struct coresight_desc { 156 enum coresight_dev_type type; 157 union coresight_dev_subtype subtype; 158 const struct coresight_ops *ops; 159 struct coresight_platform_data *pdata; 160 struct device *dev; 161 const struct attribute_group **groups; 162 const char *name; 163 struct csdev_access access; 164 }; 165 166 /** 167 * struct coresight_connection - representation of a single connection 168 * @src_port: a connection's output port number. 169 * @dest_port: destination's input port number @src_port is connected to. 170 * @dest_fwnode: destination component's fwnode handle. 171 * @dest_dev: a @coresight_device representation of the component 172 connected to @src_port. NULL until the device is created 173 * @link: Representation of the connection as a sysfs link. 174 * 175 * The full connection structure looks like this, where in_conns store 176 * references to same connection as the source device's out_conns. 177 * 178 * +-----------------------------+ +-----------------------------+ 179 * |coresight_device | |coresight_connection | 180 * |-----------------------------| |-----------------------------| 181 * | | | | 182 * | | | dest_dev*|<-- 183 * |pdata->out_conns[nr_outconns]|<->|src_dev* | | 184 * | | | | | 185 * +-----------------------------+ +-----------------------------+ | 186 * | 187 * +-----------------------------+ | 188 * |coresight_device | | 189 * |------------------------------ | 190 * | | | 191 * | pdata->in_conns[nr_inconns]|<-- 192 * | | 193 * +-----------------------------+ 194 */ 195 struct coresight_connection { 196 int src_port; 197 int dest_port; 198 struct fwnode_handle *dest_fwnode; 199 struct coresight_device *dest_dev; 200 struct coresight_sysfs_link *link; 201 struct coresight_device *src_dev; 202 atomic_t src_refcnt; 203 atomic_t dest_refcnt; 204 }; 205 206 /** 207 * struct coresight_sysfs_link - representation of a connection in sysfs. 208 * @orig: Originating (master) coresight device for the link. 209 * @orig_name: Name to use for the link orig->target. 210 * @target: Target (slave) coresight device for the link. 211 * @target_name: Name to use for the link target->orig. 212 */ 213 struct coresight_sysfs_link { 214 struct coresight_device *orig; 215 const char *orig_name; 216 struct coresight_device *target; 217 const char *target_name; 218 }; 219 220 /** 221 * struct coresight_device - representation of a device as used by the framework 222 * @pdata: Platform data with device connections associated to this device. 223 * @type: as defined by @coresight_dev_type. 224 * @subtype: as defined by @coresight_dev_subtype. 225 * @ops: generic operations for this component, as defined 226 * by @coresight_ops. 227 * @access: Device i/o access abstraction for this device. 228 * @dev: The device entity associated to this component. 229 * @mode: This tracer's mode, i.e sysFS, Perf or disabled. This is 230 * actually an 'enum cs_mode', but is stored in an atomic type. 231 * This is always accessed through local_read() and local_set(), 232 * but wherever it's done from within the Coresight device's lock, 233 * a non-atomic read would also work. This is the main point of 234 * synchronisation between code happening inside the sysfs mode's 235 * coresight_mutex and outside when running in Perf mode. A compare 236 * and exchange swap is done to atomically claim one mode or the 237 * other. 238 * @refcnt: keep track of what is in use. Only access this outside of the 239 * device's spinlock when the coresight_mutex held and mode == 240 * CS_MODE_SYSFS. Otherwise it must be accessed from inside the 241 * spinlock. 242 * @orphan: true if the component has connections that haven't been linked. 243 * @sysfs_sink_activated: 'true' when a sink has been selected for use via sysfs 244 * by writing a 1 to the 'enable_sink' file. A sink can be 245 * activated but not yet enabled. Enabling for a _sink_ happens 246 * when a source has been selected and a path is enabled from 247 * source to that sink. A sink can also become enabled but not 248 * activated if it's used via Perf. 249 * @ea: Device attribute for sink representation under PMU directory. 250 * @def_sink: cached reference to default sink found for this device. 251 * @nr_links: number of sysfs links created to other components from this 252 * device. These will appear in the "connections" group. 253 * @has_conns_grp: Have added a "connections" group for sysfs links. 254 * @feature_csdev_list: List of complex feature programming added to the device. 255 * @config_csdev_list: List of system configurations added to the device. 256 * @cscfg_csdev_lock: Protect the lists of configurations and features. 257 * @active_cscfg_ctxt: Context information for current active system configuration. 258 */ 259 struct coresight_device { 260 struct coresight_platform_data *pdata; 261 enum coresight_dev_type type; 262 union coresight_dev_subtype subtype; 263 const struct coresight_ops *ops; 264 struct csdev_access access; 265 struct device dev; 266 local_t mode; 267 int refcnt; 268 bool orphan; 269 /* sink specific fields */ 270 bool sysfs_sink_activated; 271 struct dev_ext_attribute *ea; 272 struct coresight_device *def_sink; 273 /* sysfs links between components */ 274 int nr_links; 275 bool has_conns_grp; 276 /* system configuration and feature lists */ 277 struct list_head feature_csdev_list; 278 struct list_head config_csdev_list; 279 spinlock_t cscfg_csdev_lock; 280 void *active_cscfg_ctxt; 281 }; 282 283 /* 284 * coresight_dev_list - Mapping for devices to "name" index for device 285 * names. 286 * 287 * @nr_idx: Number of entries already allocated. 288 * @pfx: Prefix pattern for device name. 289 * @fwnode_list: Array of fwnode_handles associated with each allocated 290 * index, upto nr_idx entries. 291 */ 292 struct coresight_dev_list { 293 int nr_idx; 294 const char *pfx; 295 struct fwnode_handle **fwnode_list; 296 }; 297 298 #define DEFINE_CORESIGHT_DEVLIST(var, dev_pfx) \ 299 static struct coresight_dev_list (var) = { \ 300 .pfx = dev_pfx, \ 301 .nr_idx = 0, \ 302 .fwnode_list = NULL, \ 303 } 304 305 #define to_coresight_device(d) container_of(d, struct coresight_device, dev) 306 307 enum cs_mode { 308 CS_MODE_DISABLED, 309 CS_MODE_SYSFS, 310 CS_MODE_PERF, 311 }; 312 313 #define source_ops(csdev) csdev->ops->source_ops 314 #define sink_ops(csdev) csdev->ops->sink_ops 315 #define link_ops(csdev) csdev->ops->link_ops 316 #define helper_ops(csdev) csdev->ops->helper_ops 317 #define ect_ops(csdev) csdev->ops->ect_ops 318 319 /** 320 * struct coresight_ops_sink - basic operations for a sink 321 * Operations available for sinks 322 * @enable: enables the sink. 323 * @disable: disables the sink. 324 * @alloc_buffer: initialises perf's ring buffer for trace collection. 325 * @free_buffer: release memory allocated in @get_config. 326 * @update_buffer: update buffer pointers after a trace session. 327 */ 328 struct coresight_ops_sink { 329 int (*enable)(struct coresight_device *csdev, enum cs_mode mode, 330 void *data); 331 int (*disable)(struct coresight_device *csdev); 332 void *(*alloc_buffer)(struct coresight_device *csdev, 333 struct perf_event *event, void **pages, 334 int nr_pages, bool overwrite); 335 void (*free_buffer)(void *config); 336 unsigned long (*update_buffer)(struct coresight_device *csdev, 337 struct perf_output_handle *handle, 338 void *sink_config); 339 }; 340 341 /** 342 * struct coresight_ops_link - basic operations for a link 343 * Operations available for links. 344 * @enable: enables flow between iport and oport. 345 * @disable: disables flow between iport and oport. 346 */ 347 struct coresight_ops_link { 348 int (*enable)(struct coresight_device *csdev, 349 struct coresight_connection *in, 350 struct coresight_connection *out); 351 void (*disable)(struct coresight_device *csdev, 352 struct coresight_connection *in, 353 struct coresight_connection *out); 354 }; 355 356 /** 357 * struct coresight_ops_source - basic operations for a source 358 * Operations available for sources. 359 * @cpu_id: returns the value of the CPU number this component 360 * is associated to. 361 * @enable: enables tracing for a source. 362 * @disable: disables tracing for a source. 363 */ 364 struct coresight_ops_source { 365 int (*cpu_id)(struct coresight_device *csdev); 366 int (*enable)(struct coresight_device *csdev, struct perf_event *event, 367 enum cs_mode mode); 368 void (*disable)(struct coresight_device *csdev, 369 struct perf_event *event); 370 }; 371 372 /** 373 * struct coresight_ops_helper - Operations for a helper device. 374 * 375 * All operations could pass in a device specific data, which could 376 * help the helper device to determine what to do. 377 * 378 * @enable : Enable the device 379 * @disable : Disable the device 380 */ 381 struct coresight_ops_helper { 382 int (*enable)(struct coresight_device *csdev, enum cs_mode mode, 383 void *data); 384 int (*disable)(struct coresight_device *csdev, void *data); 385 }; 386 387 struct coresight_ops { 388 const struct coresight_ops_sink *sink_ops; 389 const struct coresight_ops_link *link_ops; 390 const struct coresight_ops_source *source_ops; 391 const struct coresight_ops_helper *helper_ops; 392 }; 393 394 static inline u32 csdev_access_relaxed_read32(struct csdev_access *csa, 395 u32 offset) 396 { 397 if (likely(csa->io_mem)) 398 return readl_relaxed(csa->base + offset); 399 400 return csa->read(offset, true, false); 401 } 402 403 #define CORESIGHT_CIDRn(i) (0xFF0 + ((i) * 4)) 404 405 static inline u32 coresight_get_cid(void __iomem *base) 406 { 407 u32 i, cid = 0; 408 409 for (i = 0; i < 4; i++) 410 cid |= readl(base + CORESIGHT_CIDRn(i)) << (i * 8); 411 412 return cid; 413 } 414 415 static inline bool is_coresight_device(void __iomem *base) 416 { 417 u32 cid = coresight_get_cid(base); 418 419 return cid == CORESIGHT_CID; 420 } 421 422 /* 423 * Attempt to find and enable "APB clock" for the given device 424 * 425 * Returns: 426 * 427 * clk - Clock is found and enabled 428 * NULL - clock is not found 429 * ERROR - Clock is found but failed to enable 430 */ 431 static inline struct clk *coresight_get_enable_apb_pclk(struct device *dev) 432 { 433 struct clk *pclk; 434 int ret; 435 436 pclk = clk_get(dev, "apb_pclk"); 437 if (IS_ERR(pclk)) 438 return NULL; 439 440 ret = clk_prepare_enable(pclk); 441 if (ret) { 442 clk_put(pclk); 443 return ERR_PTR(ret); 444 } 445 return pclk; 446 } 447 448 #define CORESIGHT_PIDRn(i) (0xFE0 + ((i) * 4)) 449 450 static inline u32 coresight_get_pid(struct csdev_access *csa) 451 { 452 u32 i, pid = 0; 453 454 for (i = 0; i < 4; i++) 455 pid |= csdev_access_relaxed_read32(csa, CORESIGHT_PIDRn(i)) << (i * 8); 456 457 return pid; 458 } 459 460 static inline u64 csdev_access_relaxed_read_pair(struct csdev_access *csa, 461 u32 lo_offset, u32 hi_offset) 462 { 463 if (likely(csa->io_mem)) { 464 return readl_relaxed(csa->base + lo_offset) | 465 ((u64)readl_relaxed(csa->base + hi_offset) << 32); 466 } 467 468 return csa->read(lo_offset, true, false) | (csa->read(hi_offset, true, false) << 32); 469 } 470 471 static inline void csdev_access_relaxed_write_pair(struct csdev_access *csa, u64 val, 472 u32 lo_offset, u32 hi_offset) 473 { 474 if (likely(csa->io_mem)) { 475 writel_relaxed((u32)val, csa->base + lo_offset); 476 writel_relaxed((u32)(val >> 32), csa->base + hi_offset); 477 } else { 478 csa->write((u32)val, lo_offset, true, false); 479 csa->write((u32)(val >> 32), hi_offset, true, false); 480 } 481 } 482 483 static inline u32 csdev_access_read32(struct csdev_access *csa, u32 offset) 484 { 485 if (likely(csa->io_mem)) 486 return readl(csa->base + offset); 487 488 return csa->read(offset, false, false); 489 } 490 491 static inline void csdev_access_relaxed_write32(struct csdev_access *csa, 492 u32 val, u32 offset) 493 { 494 if (likely(csa->io_mem)) 495 writel_relaxed(val, csa->base + offset); 496 else 497 csa->write(val, offset, true, false); 498 } 499 500 static inline void csdev_access_write32(struct csdev_access *csa, u32 val, u32 offset) 501 { 502 if (likely(csa->io_mem)) 503 writel(val, csa->base + offset); 504 else 505 csa->write(val, offset, false, false); 506 } 507 508 #ifdef CONFIG_64BIT 509 510 static inline u64 csdev_access_relaxed_read64(struct csdev_access *csa, 511 u32 offset) 512 { 513 if (likely(csa->io_mem)) 514 return readq_relaxed(csa->base + offset); 515 516 return csa->read(offset, true, true); 517 } 518 519 static inline u64 csdev_access_read64(struct csdev_access *csa, u32 offset) 520 { 521 if (likely(csa->io_mem)) 522 return readq(csa->base + offset); 523 524 return csa->read(offset, false, true); 525 } 526 527 static inline void csdev_access_relaxed_write64(struct csdev_access *csa, 528 u64 val, u32 offset) 529 { 530 if (likely(csa->io_mem)) 531 writeq_relaxed(val, csa->base + offset); 532 else 533 csa->write(val, offset, true, true); 534 } 535 536 static inline void csdev_access_write64(struct csdev_access *csa, u64 val, u32 offset) 537 { 538 if (likely(csa->io_mem)) 539 writeq(val, csa->base + offset); 540 else 541 csa->write(val, offset, false, true); 542 } 543 544 #else /* !CONFIG_64BIT */ 545 546 static inline u64 csdev_access_relaxed_read64(struct csdev_access *csa, 547 u32 offset) 548 { 549 WARN_ON(1); 550 return 0; 551 } 552 553 static inline u64 csdev_access_read64(struct csdev_access *csa, u32 offset) 554 { 555 WARN_ON(1); 556 return 0; 557 } 558 559 static inline void csdev_access_relaxed_write64(struct csdev_access *csa, 560 u64 val, u32 offset) 561 { 562 WARN_ON(1); 563 } 564 565 static inline void csdev_access_write64(struct csdev_access *csa, u64 val, u32 offset) 566 { 567 WARN_ON(1); 568 } 569 #endif /* CONFIG_64BIT */ 570 571 static inline bool coresight_is_percpu_source(struct coresight_device *csdev) 572 { 573 return csdev && (csdev->type == CORESIGHT_DEV_TYPE_SOURCE) && 574 (csdev->subtype.source_subtype == CORESIGHT_DEV_SUBTYPE_SOURCE_PROC); 575 } 576 577 static inline bool coresight_is_percpu_sink(struct coresight_device *csdev) 578 { 579 return csdev && (csdev->type == CORESIGHT_DEV_TYPE_SINK) && 580 (csdev->subtype.sink_subtype == CORESIGHT_DEV_SUBTYPE_SINK_PERCPU_SYSMEM); 581 } 582 583 /* 584 * Atomically try to take the device and set a new mode. Returns true on 585 * success, false if the device is already taken by someone else. 586 */ 587 static inline bool coresight_take_mode(struct coresight_device *csdev, 588 enum cs_mode new_mode) 589 { 590 return local_cmpxchg(&csdev->mode, CS_MODE_DISABLED, new_mode) == 591 CS_MODE_DISABLED; 592 } 593 594 static inline enum cs_mode coresight_get_mode(struct coresight_device *csdev) 595 { 596 return local_read(&csdev->mode); 597 } 598 599 static inline void coresight_set_mode(struct coresight_device *csdev, 600 enum cs_mode new_mode) 601 { 602 enum cs_mode current_mode = coresight_get_mode(csdev); 603 604 /* 605 * Changing to a new mode must be done from an already disabled state 606 * unless it's synchronized with coresight_take_mode(). Otherwise the 607 * device is already in use and signifies a locking issue. 608 */ 609 WARN(new_mode != CS_MODE_DISABLED && current_mode != CS_MODE_DISABLED && 610 current_mode != new_mode, "Device already in use\n"); 611 612 local_set(&csdev->mode, new_mode); 613 } 614 615 extern struct coresight_device * 616 coresight_register(struct coresight_desc *desc); 617 extern void coresight_unregister(struct coresight_device *csdev); 618 extern int coresight_enable_sysfs(struct coresight_device *csdev); 619 extern void coresight_disable_sysfs(struct coresight_device *csdev); 620 extern int coresight_timeout(struct csdev_access *csa, u32 offset, 621 int position, int value); 622 623 extern int coresight_claim_device(struct coresight_device *csdev); 624 extern int coresight_claim_device_unlocked(struct coresight_device *csdev); 625 626 extern void coresight_disclaim_device(struct coresight_device *csdev); 627 extern void coresight_disclaim_device_unlocked(struct coresight_device *csdev); 628 extern char *coresight_alloc_device_name(struct coresight_dev_list *devs, 629 struct device *dev); 630 631 extern bool coresight_loses_context_with_cpu(struct device *dev); 632 633 u32 coresight_relaxed_read32(struct coresight_device *csdev, u32 offset); 634 u32 coresight_read32(struct coresight_device *csdev, u32 offset); 635 void coresight_write32(struct coresight_device *csdev, u32 val, u32 offset); 636 void coresight_relaxed_write32(struct coresight_device *csdev, 637 u32 val, u32 offset); 638 u64 coresight_relaxed_read64(struct coresight_device *csdev, u32 offset); 639 u64 coresight_read64(struct coresight_device *csdev, u32 offset); 640 void coresight_relaxed_write64(struct coresight_device *csdev, 641 u64 val, u32 offset); 642 void coresight_write64(struct coresight_device *csdev, u64 val, u32 offset); 643 644 extern int coresight_get_cpu(struct device *dev); 645 646 struct coresight_platform_data *coresight_get_platform_data(struct device *dev); 647 struct coresight_connection * 648 coresight_add_out_conn(struct device *dev, 649 struct coresight_platform_data *pdata, 650 const struct coresight_connection *new_conn); 651 int coresight_add_in_conn(struct coresight_connection *conn); 652 struct coresight_device * 653 coresight_find_input_type(struct coresight_platform_data *pdata, 654 enum coresight_dev_type type, 655 union coresight_dev_subtype subtype); 656 struct coresight_device * 657 coresight_find_output_type(struct coresight_platform_data *pdata, 658 enum coresight_dev_type type, 659 union coresight_dev_subtype subtype); 660 661 #endif /* _LINUX_COREISGHT_H */ 662