1 /* SPDX-License-Identifier: GPL-2.0 */ 2 /* 3 * Copyright (c) 2012, The Linux Foundation. All rights reserved. 4 */ 5 6 #ifndef _LINUX_CORESIGHT_H 7 #define _LINUX_CORESIGHT_H 8 9 #include <linux/device.h> 10 #include <linux/io.h> 11 #include <linux/perf_event.h> 12 #include <linux/sched.h> 13 14 /* Peripheral id registers (0xFD0-0xFEC) */ 15 #define CORESIGHT_PERIPHIDR4 0xfd0 16 #define CORESIGHT_PERIPHIDR5 0xfd4 17 #define CORESIGHT_PERIPHIDR6 0xfd8 18 #define CORESIGHT_PERIPHIDR7 0xfdC 19 #define CORESIGHT_PERIPHIDR0 0xfe0 20 #define CORESIGHT_PERIPHIDR1 0xfe4 21 #define CORESIGHT_PERIPHIDR2 0xfe8 22 #define CORESIGHT_PERIPHIDR3 0xfeC 23 /* Component id registers (0xFF0-0xFFC) */ 24 #define CORESIGHT_COMPIDR0 0xff0 25 #define CORESIGHT_COMPIDR1 0xff4 26 #define CORESIGHT_COMPIDR2 0xff8 27 #define CORESIGHT_COMPIDR3 0xffC 28 29 #define ETM_ARCH_V3_3 0x23 30 #define ETM_ARCH_V3_5 0x25 31 #define PFT_ARCH_V1_0 0x30 32 #define PFT_ARCH_V1_1 0x31 33 34 #define CORESIGHT_UNLOCK 0xc5acce55 35 36 extern struct bus_type coresight_bustype; 37 38 enum coresight_dev_type { 39 CORESIGHT_DEV_TYPE_SINK, 40 CORESIGHT_DEV_TYPE_LINK, 41 CORESIGHT_DEV_TYPE_LINKSINK, 42 CORESIGHT_DEV_TYPE_SOURCE, 43 CORESIGHT_DEV_TYPE_HELPER, 44 CORESIGHT_DEV_TYPE_MAX 45 }; 46 47 enum coresight_dev_subtype_sink { 48 CORESIGHT_DEV_SUBTYPE_SINK_DUMMY, 49 CORESIGHT_DEV_SUBTYPE_SINK_PORT, 50 CORESIGHT_DEV_SUBTYPE_SINK_BUFFER, 51 CORESIGHT_DEV_SUBTYPE_SINK_SYSMEM, 52 CORESIGHT_DEV_SUBTYPE_SINK_PERCPU_SYSMEM, 53 }; 54 55 enum coresight_dev_subtype_link { 56 CORESIGHT_DEV_SUBTYPE_LINK_MERG, 57 CORESIGHT_DEV_SUBTYPE_LINK_SPLIT, 58 CORESIGHT_DEV_SUBTYPE_LINK_FIFO, 59 }; 60 61 enum coresight_dev_subtype_source { 62 CORESIGHT_DEV_SUBTYPE_SOURCE_PROC, 63 CORESIGHT_DEV_SUBTYPE_SOURCE_BUS, 64 CORESIGHT_DEV_SUBTYPE_SOURCE_SOFTWARE, 65 CORESIGHT_DEV_SUBTYPE_SOURCE_OTHERS, 66 }; 67 68 enum coresight_dev_subtype_helper { 69 CORESIGHT_DEV_SUBTYPE_HELPER_CATU, 70 CORESIGHT_DEV_SUBTYPE_HELPER_ECT_CTI 71 }; 72 73 /** 74 * union coresight_dev_subtype - further characterisation of a type 75 * @sink_subtype: type of sink this component is, as defined 76 * by @coresight_dev_subtype_sink. 77 * @link_subtype: type of link this component is, as defined 78 * by @coresight_dev_subtype_link. 79 * @source_subtype: type of source this component is, as defined 80 * by @coresight_dev_subtype_source. 81 * @helper_subtype: type of helper this component is, as defined 82 * by @coresight_dev_subtype_helper. 83 */ 84 union coresight_dev_subtype { 85 /* We have some devices which acts as LINK and SINK */ 86 struct { 87 enum coresight_dev_subtype_sink sink_subtype; 88 enum coresight_dev_subtype_link link_subtype; 89 }; 90 enum coresight_dev_subtype_source source_subtype; 91 enum coresight_dev_subtype_helper helper_subtype; 92 }; 93 94 /** 95 * struct coresight_platform_data - data harvested from the firmware 96 * specification. 97 * 98 * @nr_inconns: Number of elements for the input connections. 99 * @nr_outconns: Number of elements for the output connections. 100 * @out_conns: Array of nr_outconns pointers to connections from this 101 * component. 102 * @in_conns: Sparse array of pointers to input connections. Sparse 103 * because the source device owns the connection so when it's 104 * unloaded the connection leaves an empty slot. 105 */ 106 struct coresight_platform_data { 107 int nr_inconns; 108 int nr_outconns; 109 struct coresight_connection **out_conns; 110 struct coresight_connection **in_conns; 111 }; 112 113 /** 114 * struct csdev_access - Abstraction of a CoreSight device access. 115 * 116 * @io_mem : True if the device has memory mapped I/O 117 * @base : When io_mem == true, base address of the component 118 * @read : Read from the given "offset" of the given instance. 119 * @write : Write "val" to the given "offset". 120 */ 121 struct csdev_access { 122 bool io_mem; 123 union { 124 void __iomem *base; 125 struct { 126 u64 (*read)(u32 offset, bool relaxed, bool _64bit); 127 void (*write)(u64 val, u32 offset, bool relaxed, 128 bool _64bit); 129 }; 130 }; 131 }; 132 133 #define CSDEV_ACCESS_IOMEM(_addr) \ 134 ((struct csdev_access) { \ 135 .io_mem = true, \ 136 .base = (_addr), \ 137 }) 138 139 /** 140 * struct coresight_desc - description of a component required from drivers 141 * @type: as defined by @coresight_dev_type. 142 * @subtype: as defined by @coresight_dev_subtype. 143 * @ops: generic operations for this component, as defined 144 * by @coresight_ops. 145 * @pdata: platform data collected from DT. 146 * @dev: The device entity associated to this component. 147 * @groups: operations specific to this component. These will end up 148 * in the component's sysfs sub-directory. 149 * @name: name for the coresight device, also shown under sysfs. 150 * @access: Describe access to the device 151 */ 152 struct coresight_desc { 153 enum coresight_dev_type type; 154 union coresight_dev_subtype subtype; 155 const struct coresight_ops *ops; 156 struct coresight_platform_data *pdata; 157 struct device *dev; 158 const struct attribute_group **groups; 159 const char *name; 160 struct csdev_access access; 161 }; 162 163 /** 164 * struct coresight_connection - representation of a single connection 165 * @src_port: a connection's output port number. 166 * @dest_port: destination's input port number @src_port is connected to. 167 * @dest_fwnode: destination component's fwnode handle. 168 * @dest_dev: a @coresight_device representation of the component 169 connected to @src_port. NULL until the device is created 170 * @link: Representation of the connection as a sysfs link. 171 * 172 * The full connection structure looks like this, where in_conns store 173 * references to same connection as the source device's out_conns. 174 * 175 * +-----------------------------+ +-----------------------------+ 176 * |coresight_device | |coresight_connection | 177 * |-----------------------------| |-----------------------------| 178 * | | | | 179 * | | | dest_dev*|<-- 180 * |pdata->out_conns[nr_outconns]|<->|src_dev* | | 181 * | | | | | 182 * +-----------------------------+ +-----------------------------+ | 183 * | 184 * +-----------------------------+ | 185 * |coresight_device | | 186 * |------------------------------ | 187 * | | | 188 * | pdata->in_conns[nr_inconns]|<-- 189 * | | 190 * +-----------------------------+ 191 */ 192 struct coresight_connection { 193 int src_port; 194 int dest_port; 195 struct fwnode_handle *dest_fwnode; 196 struct coresight_device *dest_dev; 197 struct coresight_sysfs_link *link; 198 struct coresight_device *src_dev; 199 atomic_t src_refcnt; 200 atomic_t dest_refcnt; 201 }; 202 203 /** 204 * struct coresight_sysfs_link - representation of a connection in sysfs. 205 * @orig: Originating (master) coresight device for the link. 206 * @orig_name: Name to use for the link orig->target. 207 * @target: Target (slave) coresight device for the link. 208 * @target_name: Name to use for the link target->orig. 209 */ 210 struct coresight_sysfs_link { 211 struct coresight_device *orig; 212 const char *orig_name; 213 struct coresight_device *target; 214 const char *target_name; 215 }; 216 217 /** 218 * struct coresight_device - representation of a device as used by the framework 219 * @pdata: Platform data with device connections associated to this device. 220 * @type: as defined by @coresight_dev_type. 221 * @subtype: as defined by @coresight_dev_subtype. 222 * @ops: generic operations for this component, as defined 223 * by @coresight_ops. 224 * @access: Device i/o access abstraction for this device. 225 * @dev: The device entity associated to this component. 226 * @refcnt: keep track of what is in use. 227 * @orphan: true if the component has connections that haven't been linked. 228 * @enable: 'true' if component is currently part of an active path. 229 * @activated: 'true' only if a _sink_ has been activated. A sink can be 230 * activated but not yet enabled. Enabling for a _sink_ 231 * happens when a source has been selected and a path is enabled 232 * from source to that sink. 233 * @ea: Device attribute for sink representation under PMU directory. 234 * @def_sink: cached reference to default sink found for this device. 235 * @nr_links: number of sysfs links created to other components from this 236 * device. These will appear in the "connections" group. 237 * @has_conns_grp: Have added a "connections" group for sysfs links. 238 * @feature_csdev_list: List of complex feature programming added to the device. 239 * @config_csdev_list: List of system configurations added to the device. 240 * @cscfg_csdev_lock: Protect the lists of configurations and features. 241 * @active_cscfg_ctxt: Context information for current active system configuration. 242 */ 243 struct coresight_device { 244 struct coresight_platform_data *pdata; 245 enum coresight_dev_type type; 246 union coresight_dev_subtype subtype; 247 const struct coresight_ops *ops; 248 struct csdev_access access; 249 struct device dev; 250 atomic_t refcnt; 251 bool orphan; 252 bool enable; /* true only if configured as part of a path */ 253 /* sink specific fields */ 254 bool activated; /* true only if a sink is part of a path */ 255 struct dev_ext_attribute *ea; 256 struct coresight_device *def_sink; 257 /* sysfs links between components */ 258 int nr_links; 259 bool has_conns_grp; 260 /* system configuration and feature lists */ 261 struct list_head feature_csdev_list; 262 struct list_head config_csdev_list; 263 spinlock_t cscfg_csdev_lock; 264 void *active_cscfg_ctxt; 265 }; 266 267 /* 268 * coresight_dev_list - Mapping for devices to "name" index for device 269 * names. 270 * 271 * @nr_idx: Number of entries already allocated. 272 * @pfx: Prefix pattern for device name. 273 * @fwnode_list: Array of fwnode_handles associated with each allocated 274 * index, upto nr_idx entries. 275 */ 276 struct coresight_dev_list { 277 int nr_idx; 278 const char *pfx; 279 struct fwnode_handle **fwnode_list; 280 }; 281 282 #define DEFINE_CORESIGHT_DEVLIST(var, dev_pfx) \ 283 static struct coresight_dev_list (var) = { \ 284 .pfx = dev_pfx, \ 285 .nr_idx = 0, \ 286 .fwnode_list = NULL, \ 287 } 288 289 #define to_coresight_device(d) container_of(d, struct coresight_device, dev) 290 291 enum cs_mode { 292 CS_MODE_DISABLED, 293 CS_MODE_SYSFS, 294 CS_MODE_PERF, 295 }; 296 297 #define source_ops(csdev) csdev->ops->source_ops 298 #define sink_ops(csdev) csdev->ops->sink_ops 299 #define link_ops(csdev) csdev->ops->link_ops 300 #define helper_ops(csdev) csdev->ops->helper_ops 301 #define ect_ops(csdev) csdev->ops->ect_ops 302 303 /** 304 * struct coresight_ops_sink - basic operations for a sink 305 * Operations available for sinks 306 * @enable: enables the sink. 307 * @disable: disables the sink. 308 * @alloc_buffer: initialises perf's ring buffer for trace collection. 309 * @free_buffer: release memory allocated in @get_config. 310 * @update_buffer: update buffer pointers after a trace session. 311 */ 312 struct coresight_ops_sink { 313 int (*enable)(struct coresight_device *csdev, enum cs_mode mode, 314 void *data); 315 int (*disable)(struct coresight_device *csdev); 316 void *(*alloc_buffer)(struct coresight_device *csdev, 317 struct perf_event *event, void **pages, 318 int nr_pages, bool overwrite); 319 void (*free_buffer)(void *config); 320 unsigned long (*update_buffer)(struct coresight_device *csdev, 321 struct perf_output_handle *handle, 322 void *sink_config); 323 }; 324 325 /** 326 * struct coresight_ops_link - basic operations for a link 327 * Operations available for links. 328 * @enable: enables flow between iport and oport. 329 * @disable: disables flow between iport and oport. 330 */ 331 struct coresight_ops_link { 332 int (*enable)(struct coresight_device *csdev, 333 struct coresight_connection *in, 334 struct coresight_connection *out); 335 void (*disable)(struct coresight_device *csdev, 336 struct coresight_connection *in, 337 struct coresight_connection *out); 338 }; 339 340 /** 341 * struct coresight_ops_source - basic operations for a source 342 * Operations available for sources. 343 * @cpu_id: returns the value of the CPU number this component 344 * is associated to. 345 * @enable: enables tracing for a source. 346 * @disable: disables tracing for a source. 347 */ 348 struct coresight_ops_source { 349 int (*cpu_id)(struct coresight_device *csdev); 350 int (*enable)(struct coresight_device *csdev, struct perf_event *event, 351 enum cs_mode mode); 352 void (*disable)(struct coresight_device *csdev, 353 struct perf_event *event); 354 }; 355 356 /** 357 * struct coresight_ops_helper - Operations for a helper device. 358 * 359 * All operations could pass in a device specific data, which could 360 * help the helper device to determine what to do. 361 * 362 * @enable : Enable the device 363 * @disable : Disable the device 364 */ 365 struct coresight_ops_helper { 366 int (*enable)(struct coresight_device *csdev, enum cs_mode mode, 367 void *data); 368 int (*disable)(struct coresight_device *csdev, void *data); 369 }; 370 371 struct coresight_ops { 372 const struct coresight_ops_sink *sink_ops; 373 const struct coresight_ops_link *link_ops; 374 const struct coresight_ops_source *source_ops; 375 const struct coresight_ops_helper *helper_ops; 376 }; 377 378 #if IS_ENABLED(CONFIG_CORESIGHT) 379 380 static inline u32 csdev_access_relaxed_read32(struct csdev_access *csa, 381 u32 offset) 382 { 383 if (likely(csa->io_mem)) 384 return readl_relaxed(csa->base + offset); 385 386 return csa->read(offset, true, false); 387 } 388 389 static inline u64 csdev_access_relaxed_read_pair(struct csdev_access *csa, 390 u32 lo_offset, u32 hi_offset) 391 { 392 if (likely(csa->io_mem)) { 393 return readl_relaxed(csa->base + lo_offset) | 394 ((u64)readl_relaxed(csa->base + hi_offset) << 32); 395 } 396 397 return csa->read(lo_offset, true, false) | (csa->read(hi_offset, true, false) << 32); 398 } 399 400 static inline void csdev_access_relaxed_write_pair(struct csdev_access *csa, u64 val, 401 u32 lo_offset, u32 hi_offset) 402 { 403 if (likely(csa->io_mem)) { 404 writel_relaxed((u32)val, csa->base + lo_offset); 405 writel_relaxed((u32)(val >> 32), csa->base + hi_offset); 406 } else { 407 csa->write((u32)val, lo_offset, true, false); 408 csa->write((u32)(val >> 32), hi_offset, true, false); 409 } 410 } 411 412 static inline u32 csdev_access_read32(struct csdev_access *csa, u32 offset) 413 { 414 if (likely(csa->io_mem)) 415 return readl(csa->base + offset); 416 417 return csa->read(offset, false, false); 418 } 419 420 static inline void csdev_access_relaxed_write32(struct csdev_access *csa, 421 u32 val, u32 offset) 422 { 423 if (likely(csa->io_mem)) 424 writel_relaxed(val, csa->base + offset); 425 else 426 csa->write(val, offset, true, false); 427 } 428 429 static inline void csdev_access_write32(struct csdev_access *csa, u32 val, u32 offset) 430 { 431 if (likely(csa->io_mem)) 432 writel(val, csa->base + offset); 433 else 434 csa->write(val, offset, false, false); 435 } 436 437 #ifdef CONFIG_64BIT 438 439 static inline u64 csdev_access_relaxed_read64(struct csdev_access *csa, 440 u32 offset) 441 { 442 if (likely(csa->io_mem)) 443 return readq_relaxed(csa->base + offset); 444 445 return csa->read(offset, true, true); 446 } 447 448 static inline u64 csdev_access_read64(struct csdev_access *csa, u32 offset) 449 { 450 if (likely(csa->io_mem)) 451 return readq(csa->base + offset); 452 453 return csa->read(offset, false, true); 454 } 455 456 static inline void csdev_access_relaxed_write64(struct csdev_access *csa, 457 u64 val, u32 offset) 458 { 459 if (likely(csa->io_mem)) 460 writeq_relaxed(val, csa->base + offset); 461 else 462 csa->write(val, offset, true, true); 463 } 464 465 static inline void csdev_access_write64(struct csdev_access *csa, u64 val, u32 offset) 466 { 467 if (likely(csa->io_mem)) 468 writeq(val, csa->base + offset); 469 else 470 csa->write(val, offset, false, true); 471 } 472 473 #else /* !CONFIG_64BIT */ 474 475 static inline u64 csdev_access_relaxed_read64(struct csdev_access *csa, 476 u32 offset) 477 { 478 WARN_ON(1); 479 return 0; 480 } 481 482 static inline u64 csdev_access_read64(struct csdev_access *csa, u32 offset) 483 { 484 WARN_ON(1); 485 return 0; 486 } 487 488 static inline void csdev_access_relaxed_write64(struct csdev_access *csa, 489 u64 val, u32 offset) 490 { 491 WARN_ON(1); 492 } 493 494 static inline void csdev_access_write64(struct csdev_access *csa, u64 val, u32 offset) 495 { 496 WARN_ON(1); 497 } 498 #endif /* CONFIG_64BIT */ 499 500 static inline bool coresight_is_percpu_source(struct coresight_device *csdev) 501 { 502 return csdev && (csdev->type == CORESIGHT_DEV_TYPE_SOURCE) && 503 (csdev->subtype.source_subtype == CORESIGHT_DEV_SUBTYPE_SOURCE_PROC); 504 } 505 506 static inline bool coresight_is_percpu_sink(struct coresight_device *csdev) 507 { 508 return csdev && (csdev->type == CORESIGHT_DEV_TYPE_SINK) && 509 (csdev->subtype.sink_subtype == CORESIGHT_DEV_SUBTYPE_SINK_PERCPU_SYSMEM); 510 } 511 512 extern struct coresight_device * 513 coresight_register(struct coresight_desc *desc); 514 extern void coresight_unregister(struct coresight_device *csdev); 515 extern int coresight_enable(struct coresight_device *csdev); 516 extern void coresight_disable(struct coresight_device *csdev); 517 extern int coresight_timeout(struct csdev_access *csa, u32 offset, 518 int position, int value); 519 520 extern int coresight_claim_device(struct coresight_device *csdev); 521 extern int coresight_claim_device_unlocked(struct coresight_device *csdev); 522 523 extern void coresight_disclaim_device(struct coresight_device *csdev); 524 extern void coresight_disclaim_device_unlocked(struct coresight_device *csdev); 525 extern char *coresight_alloc_device_name(struct coresight_dev_list *devs, 526 struct device *dev); 527 528 extern bool coresight_loses_context_with_cpu(struct device *dev); 529 530 u32 coresight_relaxed_read32(struct coresight_device *csdev, u32 offset); 531 u32 coresight_read32(struct coresight_device *csdev, u32 offset); 532 void coresight_write32(struct coresight_device *csdev, u32 val, u32 offset); 533 void coresight_relaxed_write32(struct coresight_device *csdev, 534 u32 val, u32 offset); 535 u64 coresight_relaxed_read64(struct coresight_device *csdev, u32 offset); 536 u64 coresight_read64(struct coresight_device *csdev, u32 offset); 537 void coresight_relaxed_write64(struct coresight_device *csdev, 538 u64 val, u32 offset); 539 void coresight_write64(struct coresight_device *csdev, u64 val, u32 offset); 540 541 #else 542 static inline struct coresight_device * 543 coresight_register(struct coresight_desc *desc) { return NULL; } 544 static inline void coresight_unregister(struct coresight_device *csdev) {} 545 static inline int 546 coresight_enable(struct coresight_device *csdev) { return -ENOSYS; } 547 static inline void coresight_disable(struct coresight_device *csdev) {} 548 549 static inline int coresight_timeout(struct csdev_access *csa, u32 offset, 550 int position, int value) 551 { 552 return 1; 553 } 554 555 static inline int coresight_claim_device_unlocked(struct coresight_device *csdev) 556 { 557 return -EINVAL; 558 } 559 560 static inline int coresight_claim_device(struct coresight_device *csdev) 561 { 562 return -EINVAL; 563 } 564 565 static inline void coresight_disclaim_device(struct coresight_device *csdev) {} 566 static inline void coresight_disclaim_device_unlocked(struct coresight_device *csdev) {} 567 568 static inline bool coresight_loses_context_with_cpu(struct device *dev) 569 { 570 return false; 571 } 572 573 static inline u32 coresight_relaxed_read32(struct coresight_device *csdev, u32 offset) 574 { 575 WARN_ON_ONCE(1); 576 return 0; 577 } 578 579 static inline u32 coresight_read32(struct coresight_device *csdev, u32 offset) 580 { 581 WARN_ON_ONCE(1); 582 return 0; 583 } 584 585 static inline void coresight_write32(struct coresight_device *csdev, u32 val, u32 offset) 586 { 587 } 588 589 static inline void coresight_relaxed_write32(struct coresight_device *csdev, 590 u32 val, u32 offset) 591 { 592 } 593 594 static inline u64 coresight_relaxed_read64(struct coresight_device *csdev, 595 u32 offset) 596 { 597 WARN_ON_ONCE(1); 598 return 0; 599 } 600 601 static inline u64 coresight_read64(struct coresight_device *csdev, u32 offset) 602 { 603 WARN_ON_ONCE(1); 604 return 0; 605 } 606 607 static inline void coresight_relaxed_write64(struct coresight_device *csdev, 608 u64 val, u32 offset) 609 { 610 } 611 612 static inline void coresight_write64(struct coresight_device *csdev, u64 val, u32 offset) 613 { 614 } 615 616 #endif /* IS_ENABLED(CONFIG_CORESIGHT) */ 617 618 extern int coresight_get_cpu(struct device *dev); 619 620 struct coresight_platform_data *coresight_get_platform_data(struct device *dev); 621 struct coresight_connection * 622 coresight_add_out_conn(struct device *dev, 623 struct coresight_platform_data *pdata, 624 const struct coresight_connection *new_conn); 625 int coresight_add_in_conn(struct coresight_connection *conn); 626 struct coresight_device * 627 coresight_find_input_type(struct coresight_platform_data *pdata, 628 enum coresight_dev_type type, 629 union coresight_dev_subtype subtype); 630 struct coresight_device * 631 coresight_find_output_type(struct coresight_platform_data *pdata, 632 enum coresight_dev_type type, 633 union coresight_dev_subtype subtype); 634 635 #endif /* _LINUX_COREISGHT_H */ 636