1 /* SPDX-License-Identifier: GPL-2.0+ 2 * 3 * Copyright 2013 Ideas On Board SPRL 4 * Copyright 2013, 2014 Horms Solutions Ltd. 5 * 6 * Contact: Laurent Pinchart <laurent.pinchart@ideasonboard.com> 7 * Contact: Simon Horman <horms@verge.net.au> 8 */ 9 10 #ifndef __LINUX_CLK_RENESAS_H_ 11 #define __LINUX_CLK_RENESAS_H_ 12 13 #include <linux/clk-provider.h> 14 #include <linux/types.h> 15 #include <linux/units.h> 16 17 struct device; 18 struct device_node; 19 struct generic_pm_domain; 20 21 void cpg_mstp_add_clk_domain(struct device_node *np); 22 #ifdef CONFIG_CLK_RENESAS_CPG_MSTP 23 int cpg_mstp_attach_dev(struct generic_pm_domain *unused, struct device *dev); 24 void cpg_mstp_detach_dev(struct generic_pm_domain *unused, struct device *dev); 25 #else 26 #define cpg_mstp_attach_dev NULL 27 #define cpg_mstp_detach_dev NULL 28 #endif 29 30 #ifdef CONFIG_CLK_RENESAS_CPG_MSSR 31 int cpg_mssr_attach_dev(struct generic_pm_domain *unused, struct device *dev); 32 void cpg_mssr_detach_dev(struct generic_pm_domain *unused, struct device *dev); 33 #else 34 #define cpg_mssr_attach_dev NULL 35 #define cpg_mssr_detach_dev NULL 36 #endif 37 38 /** 39 * struct rzv2h_pll_limits - PLL parameter constraints 40 * 41 * This structure defines the minimum and maximum allowed values for 42 * various parameters used to configure a PLL. These limits ensure 43 * the PLL operates within valid and stable ranges. 44 * 45 * @fout: Output frequency range (in MHz) 46 * @fout.min: Minimum allowed output frequency 47 * @fout.max: Maximum allowed output frequency 48 * 49 * @fvco: PLL oscillation frequency range (in MHz) 50 * @fvco.min: Minimum allowed VCO frequency 51 * @fvco.max: Maximum allowed VCO frequency 52 * 53 * @m: Main-divider range 54 * @m.min: Minimum main-divider value 55 * @m.max: Maximum main-divider value 56 * 57 * @p: Pre-divider range 58 * @p.min: Minimum pre-divider value 59 * @p.max: Maximum pre-divider value 60 * 61 * @s: Divider range 62 * @s.min: Minimum divider value 63 * @s.max: Maximum divider value 64 * 65 * @k: Delta-sigma modulator range (signed) 66 * @k.min: Minimum delta-sigma value 67 * @k.max: Maximum delta-sigma value 68 */ 69 struct rzv2h_pll_limits { 70 struct { 71 u32 min; 72 u32 max; 73 } fout; 74 75 struct { 76 u32 min; 77 u32 max; 78 } fvco; 79 80 struct { 81 u16 min; 82 u16 max; 83 } m; 84 85 struct { 86 u8 min; 87 u8 max; 88 } p; 89 90 struct { 91 u8 min; 92 u8 max; 93 } s; 94 95 struct { 96 s16 min; 97 s16 max; 98 } k; 99 }; 100 101 /** 102 * struct rzv2h_pll_pars - PLL configuration parameters 103 * 104 * This structure contains the configuration parameters for the 105 * Phase-Locked Loop (PLL), used to achieve a specific output frequency. 106 * 107 * @m: Main divider value 108 * @p: Pre-divider value 109 * @s: Output divider value 110 * @k: Delta-sigma modulation value 111 * @freq_millihz: Calculated PLL output frequency in millihertz 112 * @error_millihz: Frequency error from target in millihertz (signed) 113 */ 114 struct rzv2h_pll_pars { 115 u16 m; 116 u8 p; 117 u8 s; 118 s16 k; 119 u64 freq_millihz; 120 s64 error_millihz; 121 }; 122 123 /** 124 * struct rzv2h_pll_div_pars - PLL parameters with post-divider 125 * 126 * This structure is used for PLLs that include an additional post-divider 127 * stage after the main PLL block. It contains both the PLL configuration 128 * parameters and the resulting frequency/error values after the divider. 129 * 130 * @pll: Main PLL configuration parameters (see struct rzv2h_pll_pars) 131 * 132 * @div: Post-divider configuration and result 133 * @div.divider_value: Divider applied to the PLL output 134 * @div.freq_millihz: Output frequency after divider in millihertz 135 * @div.error_millihz: Frequency error from target in millihertz (signed) 136 */ 137 struct rzv2h_pll_div_pars { 138 struct rzv2h_pll_pars pll; 139 struct { 140 u8 divider_value; 141 u64 freq_millihz; 142 s64 error_millihz; 143 } div; 144 }; 145 146 #define RZV2H_CPG_PLL_DSI_LIMITS(name) \ 147 static const struct rzv2h_pll_limits (name) = { \ 148 .fout = { .min = 25 * MEGA, .max = 375 * MEGA }, \ 149 .fvco = { .min = 1600 * MEGA, .max = 3200 * MEGA }, \ 150 .m = { .min = 64, .max = 533 }, \ 151 .p = { .min = 1, .max = 4 }, \ 152 .s = { .min = 0, .max = 6 }, \ 153 .k = { .min = -32768, .max = 32767 }, \ 154 } \ 155 156 #ifdef CONFIG_CLK_RZV2H 157 bool rzv2h_get_pll_pars(const struct rzv2h_pll_limits *limits, 158 struct rzv2h_pll_pars *pars, u64 freq_millihz); 159 160 bool rzv2h_get_pll_divs_pars(const struct rzv2h_pll_limits *limits, 161 struct rzv2h_pll_div_pars *pars, 162 const u8 *table, u8 table_size, u64 freq_millihz); 163 #else 164 static inline bool rzv2h_get_pll_pars(const struct rzv2h_pll_limits *limits, 165 struct rzv2h_pll_pars *pars, 166 u64 freq_millihz) 167 { 168 return false; 169 } 170 171 static inline bool rzv2h_get_pll_divs_pars(const struct rzv2h_pll_limits *limits, 172 struct rzv2h_pll_div_pars *pars, 173 const u8 *table, u8 table_size, 174 u64 freq_millihz) 175 { 176 return false; 177 } 178 #endif 179 180 #endif 181