1 /* SPDX-License-Identifier: GPL-2.0+ 2 * 3 * Copyright 2013 Ideas On Board SPRL 4 * Copyright 2013, 2014 Horms Solutions Ltd. 5 * 6 * Contact: Laurent Pinchart <laurent.pinchart@ideasonboard.com> 7 * Contact: Simon Horman <horms@verge.net.au> 8 */ 9 10 #ifndef __LINUX_CLK_RENESAS_H_ 11 #define __LINUX_CLK_RENESAS_H_ 12 13 #include <linux/clk-provider.h> 14 #include <linux/types.h> 15 #include <linux/units.h> 16 17 struct device; 18 struct device_node; 19 struct generic_pm_domain; 20 21 void cpg_mstp_add_clk_domain(struct device_node *np); 22 #ifdef CONFIG_CLK_RENESAS_CPG_MSTP 23 int cpg_mstp_attach_dev(struct generic_pm_domain *unused, struct device *dev); 24 void cpg_mstp_detach_dev(struct generic_pm_domain *unused, struct device *dev); 25 #else 26 #define cpg_mstp_attach_dev NULL 27 #define cpg_mstp_detach_dev NULL 28 #endif 29 30 #ifdef CONFIG_CLK_RENESAS_CPG_MSSR 31 int cpg_mssr_attach_dev(struct generic_pm_domain *unused, struct device *dev); 32 void cpg_mssr_detach_dev(struct generic_pm_domain *unused, struct device *dev); 33 #else 34 #define cpg_mssr_attach_dev NULL 35 #define cpg_mssr_detach_dev NULL 36 #endif 37 38 enum { 39 PLL5_TARGET_DPI, 40 PLL5_TARGET_DSI 41 }; 42 43 #ifdef CONFIG_CLK_RZG2L 44 void rzg2l_cpg_dsi_div_set_divider(u8 divider, int target); 45 #else 46 static inline void rzg2l_cpg_dsi_div_set_divider(u8 divider, int target) { } 47 #endif 48 49 /** 50 * struct rzv2h_pll_limits - PLL parameter constraints 51 * 52 * This structure defines the minimum and maximum allowed values for 53 * various parameters used to configure a PLL. These limits ensure 54 * the PLL operates within valid and stable ranges. 55 * 56 * @input_fref: Reference input frequency to the PLL (in Hz). If set 57 * to 0, a default value of 24MHz is used. 58 * 59 * @fout: Output frequency range (in MHz) 60 * @fout.min: Minimum allowed output frequency 61 * @fout.max: Maximum allowed output frequency 62 * 63 * @fvco: PLL oscillation frequency range (in MHz) 64 * @fvco.min: Minimum allowed VCO frequency 65 * @fvco.max: Maximum allowed VCO frequency 66 * 67 * @m: Main-divider range 68 * @m.min: Minimum main-divider value 69 * @m.max: Maximum main-divider value 70 * 71 * @p: Pre-divider range 72 * @p.min: Minimum pre-divider value 73 * @p.max: Maximum pre-divider value 74 * 75 * @s: Divider range 76 * @s.min: Minimum divider value 77 * @s.max: Maximum divider value 78 * 79 * @k: Delta-sigma modulator range (signed) 80 * @k.min: Minimum delta-sigma value 81 * @k.max: Maximum delta-sigma value 82 */ 83 struct rzv2h_pll_limits { 84 u32 input_fref; 85 86 struct { 87 u32 min; 88 u32 max; 89 } fout; 90 91 struct { 92 u32 min; 93 u32 max; 94 } fvco; 95 96 struct { 97 u16 min; 98 u16 max; 99 } m; 100 101 struct { 102 u8 min; 103 u8 max; 104 } p; 105 106 struct { 107 u8 min; 108 u8 max; 109 } s; 110 111 struct { 112 s16 min; 113 s16 max; 114 } k; 115 }; 116 117 /** 118 * struct rzv2h_pll_pars - PLL configuration parameters 119 * 120 * This structure contains the configuration parameters for the 121 * Phase-Locked Loop (PLL), used to achieve a specific output frequency. 122 * 123 * @m: Main divider value 124 * @p: Pre-divider value 125 * @s: Output divider value 126 * @k: Delta-sigma modulation value 127 * @freq_millihz: Calculated PLL output frequency in millihertz 128 * @error_millihz: Frequency error from target in millihertz (signed) 129 */ 130 struct rzv2h_pll_pars { 131 u16 m; 132 u8 p; 133 u8 s; 134 s16 k; 135 u64 freq_millihz; 136 s64 error_millihz; 137 }; 138 139 /** 140 * struct rzv2h_pll_div_pars - PLL parameters with post-divider 141 * 142 * This structure is used for PLLs that include an additional post-divider 143 * stage after the main PLL block. It contains both the PLL configuration 144 * parameters and the resulting frequency/error values after the divider. 145 * 146 * @pll: Main PLL configuration parameters (see struct rzv2h_pll_pars) 147 * 148 * @div: Post-divider configuration and result 149 * @div.divider_value: Divider applied to the PLL output 150 * @div.freq_millihz: Output frequency after divider in millihertz 151 * @div.error_millihz: Frequency error from target in millihertz (signed) 152 */ 153 struct rzv2h_pll_div_pars { 154 struct rzv2h_pll_pars pll; 155 struct { 156 u8 divider_value; 157 u64 freq_millihz; 158 s64 error_millihz; 159 } div; 160 }; 161 162 #define RZV2H_CPG_PLL_DSI_LIMITS(name) \ 163 static const struct rzv2h_pll_limits (name) = { \ 164 .fout = { .min = 25 * MEGA, .max = 375 * MEGA }, \ 165 .fvco = { .min = 1600 * MEGA, .max = 3200 * MEGA }, \ 166 .m = { .min = 64, .max = 533 }, \ 167 .p = { .min = 1, .max = 4 }, \ 168 .s = { .min = 0, .max = 6 }, \ 169 .k = { .min = -32768, .max = 32767 }, \ 170 } \ 171 172 #define RZG3E_CPG_PLL_DSI0_LIMITS(name) \ 173 static const struct rzv2h_pll_limits (name) = { \ 174 .fout = { .min = 25 * MEGA, .max = 1218 * MEGA }, \ 175 .fvco = { .min = 1600 * MEGA, .max = 3200 * MEGA }, \ 176 .m = { .min = 64, .max = 533 }, \ 177 .p = { .min = 1, .max = 4 }, \ 178 .s = { .min = 0, .max = 6 }, \ 179 .k = { .min = -32768, .max = 32767 }, \ 180 } \ 181 182 #define RZG3E_CPG_PLL_DSI1_LIMITS(name) \ 183 static const struct rzv2h_pll_limits (name) = { \ 184 .fout = { .min = 25 * MEGA, .max = 609 * MEGA }, \ 185 .fvco = { .min = 1600 * MEGA, .max = 3200 * MEGA }, \ 186 .m = { .min = 64, .max = 533 }, \ 187 .p = { .min = 1, .max = 4 }, \ 188 .s = { .min = 0, .max = 6 }, \ 189 .k = { .min = -32768, .max = 32767 }, \ 190 } \ 191 192 #ifdef CONFIG_CLK_RZV2H_CPG_LIB 193 bool rzv2h_cpg_get_pll_pars(const struct rzv2h_pll_limits *limits, 194 struct rzv2h_pll_pars *pars, u64 freq_millihz); 195 196 bool rzv2h_cpg_get_pll_divs_pars(const struct rzv2h_pll_limits *limits, 197 struct rzv2h_pll_div_pars *pars, 198 const u8 *table, u8 table_size, u64 freq_millihz); 199 #else 200 static inline bool rzv2h_cpg_get_pll_pars(const struct rzv2h_pll_limits *limits, 201 struct rzv2h_pll_pars *pars, 202 u64 freq_millihz) 203 { 204 return false; 205 } 206 207 static inline bool rzv2h_cpg_get_pll_divs_pars(const struct rzv2h_pll_limits *limits, 208 struct rzv2h_pll_div_pars *pars, 209 const u8 *table, u8 table_size, 210 u64 freq_millihz) 211 { 212 return false; 213 } 214 #endif 215 216 #define rzv2h_get_pll_pars rzv2h_cpg_get_pll_pars 217 #define rzv2h_get_pll_divs_pars rzv2h_cpg_get_pll_divs_pars 218 219 #endif 220