1 /* SPDX-License-Identifier: GPL-2.0+ 2 * 3 * Copyright 2013 Ideas On Board SPRL 4 * Copyright 2013, 2014 Horms Solutions Ltd. 5 * 6 * Contact: Laurent Pinchart <laurent.pinchart@ideasonboard.com> 7 * Contact: Simon Horman <horms@verge.net.au> 8 */ 9 10 #ifndef __LINUX_CLK_RENESAS_H_ 11 #define __LINUX_CLK_RENESAS_H_ 12 13 #include <linux/clk-provider.h> 14 #include <linux/types.h> 15 #include <linux/units.h> 16 17 struct device; 18 struct device_node; 19 struct generic_pm_domain; 20 21 void cpg_mstp_add_clk_domain(struct device_node *np); 22 #ifdef CONFIG_CLK_RENESAS_CPG_MSTP 23 int cpg_mstp_attach_dev(struct generic_pm_domain *unused, struct device *dev); 24 void cpg_mstp_detach_dev(struct generic_pm_domain *unused, struct device *dev); 25 #else 26 #define cpg_mstp_attach_dev NULL 27 #define cpg_mstp_detach_dev NULL 28 #endif 29 30 #ifdef CONFIG_CLK_RENESAS_CPG_MSSR 31 int cpg_mssr_attach_dev(struct generic_pm_domain *unused, struct device *dev); 32 void cpg_mssr_detach_dev(struct generic_pm_domain *unused, struct device *dev); 33 #else 34 #define cpg_mssr_attach_dev NULL 35 #define cpg_mssr_detach_dev NULL 36 #endif 37 38 enum { 39 PLL5_TARGET_DPI, 40 PLL5_TARGET_DSI 41 }; 42 43 #ifdef CONFIG_CLK_RZG2L 44 void rzg2l_cpg_dsi_div_set_divider(u8 divider, int target); 45 #else 46 static inline void rzg2l_cpg_dsi_div_set_divider(u8 divider, int target) { } 47 #endif 48 49 /** 50 * struct rzv2h_pll_limits - PLL parameter constraints 51 * 52 * This structure defines the minimum and maximum allowed values for 53 * various parameters used to configure a PLL. These limits ensure 54 * the PLL operates within valid and stable ranges. 55 * 56 * @fout: Output frequency range (in MHz) 57 * @fout.min: Minimum allowed output frequency 58 * @fout.max: Maximum allowed output frequency 59 * 60 * @fvco: PLL oscillation frequency range (in MHz) 61 * @fvco.min: Minimum allowed VCO frequency 62 * @fvco.max: Maximum allowed VCO frequency 63 * 64 * @m: Main-divider range 65 * @m.min: Minimum main-divider value 66 * @m.max: Maximum main-divider value 67 * 68 * @p: Pre-divider range 69 * @p.min: Minimum pre-divider value 70 * @p.max: Maximum pre-divider value 71 * 72 * @s: Divider range 73 * @s.min: Minimum divider value 74 * @s.max: Maximum divider value 75 * 76 * @k: Delta-sigma modulator range (signed) 77 * @k.min: Minimum delta-sigma value 78 * @k.max: Maximum delta-sigma value 79 */ 80 struct rzv2h_pll_limits { 81 struct { 82 u32 min; 83 u32 max; 84 } fout; 85 86 struct { 87 u32 min; 88 u32 max; 89 } fvco; 90 91 struct { 92 u16 min; 93 u16 max; 94 } m; 95 96 struct { 97 u8 min; 98 u8 max; 99 } p; 100 101 struct { 102 u8 min; 103 u8 max; 104 } s; 105 106 struct { 107 s16 min; 108 s16 max; 109 } k; 110 }; 111 112 /** 113 * struct rzv2h_pll_pars - PLL configuration parameters 114 * 115 * This structure contains the configuration parameters for the 116 * Phase-Locked Loop (PLL), used to achieve a specific output frequency. 117 * 118 * @m: Main divider value 119 * @p: Pre-divider value 120 * @s: Output divider value 121 * @k: Delta-sigma modulation value 122 * @freq_millihz: Calculated PLL output frequency in millihertz 123 * @error_millihz: Frequency error from target in millihertz (signed) 124 */ 125 struct rzv2h_pll_pars { 126 u16 m; 127 u8 p; 128 u8 s; 129 s16 k; 130 u64 freq_millihz; 131 s64 error_millihz; 132 }; 133 134 /** 135 * struct rzv2h_pll_div_pars - PLL parameters with post-divider 136 * 137 * This structure is used for PLLs that include an additional post-divider 138 * stage after the main PLL block. It contains both the PLL configuration 139 * parameters and the resulting frequency/error values after the divider. 140 * 141 * @pll: Main PLL configuration parameters (see struct rzv2h_pll_pars) 142 * 143 * @div: Post-divider configuration and result 144 * @div.divider_value: Divider applied to the PLL output 145 * @div.freq_millihz: Output frequency after divider in millihertz 146 * @div.error_millihz: Frequency error from target in millihertz (signed) 147 */ 148 struct rzv2h_pll_div_pars { 149 struct rzv2h_pll_pars pll; 150 struct { 151 u8 divider_value; 152 u64 freq_millihz; 153 s64 error_millihz; 154 } div; 155 }; 156 157 #define RZV2H_CPG_PLL_DSI_LIMITS(name) \ 158 static const struct rzv2h_pll_limits (name) = { \ 159 .fout = { .min = 25 * MEGA, .max = 375 * MEGA }, \ 160 .fvco = { .min = 1600 * MEGA, .max = 3200 * MEGA }, \ 161 .m = { .min = 64, .max = 533 }, \ 162 .p = { .min = 1, .max = 4 }, \ 163 .s = { .min = 0, .max = 6 }, \ 164 .k = { .min = -32768, .max = 32767 }, \ 165 } \ 166 167 #ifdef CONFIG_CLK_RZV2H 168 bool rzv2h_get_pll_pars(const struct rzv2h_pll_limits *limits, 169 struct rzv2h_pll_pars *pars, u64 freq_millihz); 170 171 bool rzv2h_get_pll_divs_pars(const struct rzv2h_pll_limits *limits, 172 struct rzv2h_pll_div_pars *pars, 173 const u8 *table, u8 table_size, u64 freq_millihz); 174 #else 175 static inline bool rzv2h_get_pll_pars(const struct rzv2h_pll_limits *limits, 176 struct rzv2h_pll_pars *pars, 177 u64 freq_millihz) 178 { 179 return false; 180 } 181 182 static inline bool rzv2h_get_pll_divs_pars(const struct rzv2h_pll_limits *limits, 183 struct rzv2h_pll_div_pars *pars, 184 const u8 *table, u8 table_size, 185 u64 freq_millihz) 186 { 187 return false; 188 } 189 #endif 190 191 #endif 192