1 /* 2 * linux/include/asm-arm/hardware/serial_amba.h 3 * 4 * Internal header file for AMBA serial ports 5 * 6 * Copyright (C) ARM Limited 7 * Copyright (C) 2000 Deep Blue Solutions Ltd. 8 * 9 * This program is free software; you can redistribute it and/or modify 10 * it under the terms of the GNU General Public License as published by 11 * the Free Software Foundation; either version 2 of the License, or 12 * (at your option) any later version. 13 * 14 * This program is distributed in the hope that it will be useful, 15 * but WITHOUT ANY WARRANTY; without even the implied warranty of 16 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 17 * GNU General Public License for more details. 18 * 19 * You should have received a copy of the GNU General Public License 20 * along with this program; if not, write to the Free Software 21 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA 22 */ 23 #ifndef ASM_ARM_HARDWARE_SERIAL_AMBA_H 24 #define ASM_ARM_HARDWARE_SERIAL_AMBA_H 25 26 #include <linux/types.h> 27 28 /* ------------------------------------------------------------------------------- 29 * From AMBA UART (PL010) Block Specification 30 * ------------------------------------------------------------------------------- 31 * UART Register Offsets. 32 */ 33 #define UART01x_DR 0x00 /* Data read or written from the interface. */ 34 #define UART01x_RSR 0x04 /* Receive status register (Read). */ 35 #define UART01x_ECR 0x04 /* Error clear register (Write). */ 36 #define ZX_UART01x_DR 0x04 /* Data read or written from the interface. */ 37 #define UART010_LCRH 0x08 /* Line control register, high byte. */ 38 #define ST_UART011_DMAWM 0x08 /* DMA watermark configure register. */ 39 #define UART010_LCRM 0x0C /* Line control register, middle byte. */ 40 #define ST_UART011_TIMEOUT 0x0C /* Timeout period register. */ 41 #define UART010_LCRL 0x10 /* Line control register, low byte. */ 42 #define UART010_CR 0x14 /* Control register. */ 43 #define ZX_UART01x_FR 0x14 /* Flag register (Read only). */ 44 #define UART01x_FR 0x18 /* Flag register (Read only). */ 45 #define UART010_IIR 0x1C /* Interrupt identification register (Read). */ 46 #define UART010_ICR 0x1C /* Interrupt clear register (Write). */ 47 #define ST_UART011_LCRH_RX 0x1C /* Rx line control register. */ 48 #define UART01x_ILPR 0x20 /* IrDA low power counter register. */ 49 #define UART011_IBRD 0x24 /* Integer baud rate divisor register. */ 50 #define UART011_FBRD 0x28 /* Fractional baud rate divisor register. */ 51 #define UART011_LCRH 0x2c /* Line control register. */ 52 #define ST_UART011_LCRH_TX 0x2c /* Tx Line control register. */ 53 #define UART011_CR 0x30 /* Control register. */ 54 #define ZX_UART011_LCRH_TX 0x30 /* Tx Line control register. */ 55 #define UART011_IFLS 0x34 /* Interrupt fifo level select. */ 56 #define ZX_UART011_CR 0x34 /* Control register. */ 57 #define ZX_UART011_IFLS 0x38 /* Interrupt fifo level select. */ 58 #define UART011_IMSC 0x38 /* Interrupt mask. */ 59 #define UART011_RIS 0x3c /* Raw interrupt status. */ 60 #define UART011_MIS 0x40 /* Masked interrupt status. */ 61 #define ZX_UART011_IMSC 0x40 /* Interrupt mask. */ 62 #define UART011_ICR 0x44 /* Interrupt clear register. */ 63 #define ZX_UART011_RIS 0x44 /* Raw interrupt status. */ 64 #define UART011_DMACR 0x48 /* DMA control register. */ 65 #define ZX_UART011_MIS 0x48 /* Masked interrupt status. */ 66 #define ZX_UART011_ICR 0x4c /* Interrupt clear register. */ 67 #define ST_UART011_XFCR 0x50 /* XON/XOFF control register. */ 68 #define ZX_UART011_DMACR 0x50 /* DMA control register. */ 69 #define ST_UART011_XON1 0x54 /* XON1 register. */ 70 #define ST_UART011_XON2 0x58 /* XON2 register. */ 71 #define ST_UART011_XOFF1 0x5C /* XON1 register. */ 72 #define ST_UART011_XOFF2 0x60 /* XON2 register. */ 73 #define ST_UART011_ITCR 0x80 /* Integration test control register. */ 74 #define ST_UART011_ITIP 0x84 /* Integration test input register. */ 75 #define ST_UART011_ABCR 0x100 /* Autobaud control register. */ 76 #define ST_UART011_ABIMSC 0x15C /* Autobaud interrupt mask/clear register. */ 77 78 #define UART011_DR_OE (1 << 11) 79 #define UART011_DR_BE (1 << 10) 80 #define UART011_DR_PE (1 << 9) 81 #define UART011_DR_FE (1 << 8) 82 83 #define UART01x_RSR_OE 0x08 84 #define UART01x_RSR_BE 0x04 85 #define UART01x_RSR_PE 0x02 86 #define UART01x_RSR_FE 0x01 87 88 #define ZX_UART01x_FR_BUSY 0x300 89 #define UART011_FR_RI 0x100 90 #define UART011_FR_TXFE 0x080 91 #define UART011_FR_RXFF 0x040 92 #define UART01x_FR_TXFF 0x020 93 #define UART01x_FR_RXFE 0x010 94 #define UART01x_FR_BUSY 0x008 95 #define ZX_UART01x_FR_DSR 0x008 96 #define UART01x_FR_DCD 0x004 97 #define UART01x_FR_DSR 0x002 98 #define ZX_UART01x_FR_CTS 0x002 99 #define UART01x_FR_CTS 0x001 100 #define ZX_UART011_FR_RI 0x001 101 #define UART01x_FR_TMSK (UART01x_FR_TXFF + UART01x_FR_BUSY) 102 103 #define UART011_CR_CTSEN 0x8000 /* CTS hardware flow control */ 104 #define UART011_CR_RTSEN 0x4000 /* RTS hardware flow control */ 105 #define UART011_CR_OUT2 0x2000 /* OUT2 */ 106 #define UART011_CR_OUT1 0x1000 /* OUT1 */ 107 #define UART011_CR_RTS 0x0800 /* RTS */ 108 #define UART011_CR_DTR 0x0400 /* DTR */ 109 #define UART011_CR_RXE 0x0200 /* receive enable */ 110 #define UART011_CR_TXE 0x0100 /* transmit enable */ 111 #define UART011_CR_LBE 0x0080 /* loopback enable */ 112 #define UART010_CR_RTIE 0x0040 113 #define UART010_CR_TIE 0x0020 114 #define UART010_CR_RIE 0x0010 115 #define UART010_CR_MSIE 0x0008 116 #define ST_UART011_CR_OVSFACT 0x0008 /* Oversampling factor */ 117 #define UART01x_CR_IIRLP 0x0004 /* SIR low power mode */ 118 #define UART01x_CR_SIREN 0x0002 /* SIR enable */ 119 #define UART01x_CR_UARTEN 0x0001 /* UART enable */ 120 121 #define UART011_LCRH_SPS 0x80 122 #define UART01x_LCRH_WLEN_8 0x60 123 #define UART01x_LCRH_WLEN_7 0x40 124 #define UART01x_LCRH_WLEN_6 0x20 125 #define UART01x_LCRH_WLEN_5 0x00 126 #define UART01x_LCRH_FEN 0x10 127 #define UART01x_LCRH_STP2 0x08 128 #define UART01x_LCRH_EPS 0x04 129 #define UART01x_LCRH_PEN 0x02 130 #define UART01x_LCRH_BRK 0x01 131 132 #define ST_UART011_DMAWM_RX_1 (0 << 3) 133 #define ST_UART011_DMAWM_RX_2 (1 << 3) 134 #define ST_UART011_DMAWM_RX_4 (2 << 3) 135 #define ST_UART011_DMAWM_RX_8 (3 << 3) 136 #define ST_UART011_DMAWM_RX_16 (4 << 3) 137 #define ST_UART011_DMAWM_RX_32 (5 << 3) 138 #define ST_UART011_DMAWM_RX_48 (6 << 3) 139 #define ST_UART011_DMAWM_TX_1 0 140 #define ST_UART011_DMAWM_TX_2 1 141 #define ST_UART011_DMAWM_TX_4 2 142 #define ST_UART011_DMAWM_TX_8 3 143 #define ST_UART011_DMAWM_TX_16 4 144 #define ST_UART011_DMAWM_TX_32 5 145 #define ST_UART011_DMAWM_TX_48 6 146 147 #define UART010_IIR_RTIS 0x08 148 #define UART010_IIR_TIS 0x04 149 #define UART010_IIR_RIS 0x02 150 #define UART010_IIR_MIS 0x01 151 152 #define UART011_IFLS_RX1_8 (0 << 3) 153 #define UART011_IFLS_RX2_8 (1 << 3) 154 #define UART011_IFLS_RX4_8 (2 << 3) 155 #define UART011_IFLS_RX6_8 (3 << 3) 156 #define UART011_IFLS_RX7_8 (4 << 3) 157 #define UART011_IFLS_TX1_8 (0 << 0) 158 #define UART011_IFLS_TX2_8 (1 << 0) 159 #define UART011_IFLS_TX4_8 (2 << 0) 160 #define UART011_IFLS_TX6_8 (3 << 0) 161 #define UART011_IFLS_TX7_8 (4 << 0) 162 /* special values for ST vendor with deeper fifo */ 163 #define UART011_IFLS_RX_HALF (5 << 3) 164 #define UART011_IFLS_TX_HALF (5 << 0) 165 166 #define UART011_OEIM (1 << 10) /* overrun error interrupt mask */ 167 #define UART011_BEIM (1 << 9) /* break error interrupt mask */ 168 #define UART011_PEIM (1 << 8) /* parity error interrupt mask */ 169 #define UART011_FEIM (1 << 7) /* framing error interrupt mask */ 170 #define UART011_RTIM (1 << 6) /* receive timeout interrupt mask */ 171 #define UART011_TXIM (1 << 5) /* transmit interrupt mask */ 172 #define UART011_RXIM (1 << 4) /* receive interrupt mask */ 173 #define UART011_DSRMIM (1 << 3) /* DSR interrupt mask */ 174 #define UART011_DCDMIM (1 << 2) /* DCD interrupt mask */ 175 #define UART011_CTSMIM (1 << 1) /* CTS interrupt mask */ 176 #define UART011_RIMIM (1 << 0) /* RI interrupt mask */ 177 178 #define UART011_OEIS (1 << 10) /* overrun error interrupt status */ 179 #define UART011_BEIS (1 << 9) /* break error interrupt status */ 180 #define UART011_PEIS (1 << 8) /* parity error interrupt status */ 181 #define UART011_FEIS (1 << 7) /* framing error interrupt status */ 182 #define UART011_RTIS (1 << 6) /* receive timeout interrupt status */ 183 #define UART011_TXIS (1 << 5) /* transmit interrupt status */ 184 #define UART011_RXIS (1 << 4) /* receive interrupt status */ 185 #define UART011_DSRMIS (1 << 3) /* DSR interrupt status */ 186 #define UART011_DCDMIS (1 << 2) /* DCD interrupt status */ 187 #define UART011_CTSMIS (1 << 1) /* CTS interrupt status */ 188 #define UART011_RIMIS (1 << 0) /* RI interrupt status */ 189 190 #define UART011_OEIC (1 << 10) /* overrun error interrupt clear */ 191 #define UART011_BEIC (1 << 9) /* break error interrupt clear */ 192 #define UART011_PEIC (1 << 8) /* parity error interrupt clear */ 193 #define UART011_FEIC (1 << 7) /* framing error interrupt clear */ 194 #define UART011_RTIC (1 << 6) /* receive timeout interrupt clear */ 195 #define UART011_TXIC (1 << 5) /* transmit interrupt clear */ 196 #define UART011_RXIC (1 << 4) /* receive interrupt clear */ 197 #define UART011_DSRMIC (1 << 3) /* DSR interrupt clear */ 198 #define UART011_DCDMIC (1 << 2) /* DCD interrupt clear */ 199 #define UART011_CTSMIC (1 << 1) /* CTS interrupt clear */ 200 #define UART011_RIMIC (1 << 0) /* RI interrupt clear */ 201 202 #define UART011_DMAONERR (1 << 2) /* disable dma on error */ 203 #define UART011_TXDMAE (1 << 1) /* enable transmit dma */ 204 #define UART011_RXDMAE (1 << 0) /* enable receive dma */ 205 206 #define UART01x_RSR_ANY (UART01x_RSR_OE|UART01x_RSR_BE|UART01x_RSR_PE|UART01x_RSR_FE) 207 #define UART01x_FR_MODEM_ANY (UART01x_FR_DCD|UART01x_FR_DSR|UART01x_FR_CTS) 208 209 #ifndef __ASSEMBLY__ 210 struct amba_device; /* in uncompress this is included but amba/bus.h is not */ 211 struct amba_pl010_data { 212 void (*set_mctrl)(struct amba_device *dev, void __iomem *base, unsigned int mctrl); 213 }; 214 215 struct dma_chan; 216 struct amba_pl011_data { 217 bool (*dma_filter)(struct dma_chan *chan, void *filter_param); 218 void *dma_rx_param; 219 void *dma_tx_param; 220 bool dma_rx_poll_enable; 221 unsigned int dma_rx_poll_rate; 222 unsigned int dma_rx_poll_timeout; 223 void (*init) (void); 224 void (*exit) (void); 225 }; 226 #endif 227 228 #endif 229