1 /* SPDX-License-Identifier: GPL-2.0-only */ 2 /* 3 * Copyright (C) 2015, 2016 ARM Ltd. 4 */ 5 #ifndef __KVM_ARM_VGIC_H 6 #define __KVM_ARM_VGIC_H 7 8 #include <linux/bits.h> 9 #include <linux/kvm.h> 10 #include <linux/irqreturn.h> 11 #include <linux/mutex.h> 12 #include <linux/refcount.h> 13 #include <linux/spinlock.h> 14 #include <linux/static_key.h> 15 #include <linux/types.h> 16 #include <linux/xarray.h> 17 #include <kvm/iodev.h> 18 #include <linux/list.h> 19 #include <linux/jump_label.h> 20 21 #include <linux/irqchip/arm-gic-v4.h> 22 #include <linux/irqchip/arm-gic-v5.h> 23 24 #define VGIC_V5_MAX_CPUS 512 25 #define VGIC_V3_MAX_CPUS 512 26 #define VGIC_V2_MAX_CPUS 8 27 #define VGIC_NR_IRQS_LEGACY 256 28 #define VGIC_NR_SGIS 16 29 #define VGIC_NR_PPIS 16 30 #define VGIC_NR_PRIVATE_IRQS (VGIC_NR_SGIS + VGIC_NR_PPIS) 31 #define VGIC_MAX_SPI 1019 32 #define VGIC_MAX_RESERVED 1023 33 #define VGIC_MIN_LPI 8192 34 #define KVM_IRQCHIP_NUM_PINS (1020 - 32) 35 36 /* 37 * GICv5 supports 128 PPIs, but only the first 64 are architected. We only 38 * support the timers and PMU in KVM, both of which are architected. Rather than 39 * handling twice the state, we instead opt to only support the architected set 40 * in KVM for now. At a future stage, this can be bumped up to 128, if required. 41 */ 42 #define VGIC_V5_NR_PRIVATE_IRQS 64 43 44 #define is_v5_type(t, i) (FIELD_GET(GICV5_HWIRQ_TYPE, (i)) == (t)) 45 46 #define __irq_is_sgi(t, i) \ 47 ({ \ 48 bool __ret; \ 49 \ 50 switch (t) { \ 51 case KVM_DEV_TYPE_ARM_VGIC_V5: \ 52 __ret = false; \ 53 break; \ 54 default: \ 55 __ret = (i) < VGIC_NR_SGIS; \ 56 } \ 57 \ 58 __ret; \ 59 }) 60 61 #define __irq_is_ppi(t, i) \ 62 ({ \ 63 bool __ret; \ 64 \ 65 switch (t) { \ 66 case KVM_DEV_TYPE_ARM_VGIC_V5: \ 67 __ret = is_v5_type(GICV5_HWIRQ_TYPE_PPI, (i)); \ 68 break; \ 69 default: \ 70 __ret = (i) >= VGIC_NR_SGIS; \ 71 __ret &= (i) < VGIC_NR_PRIVATE_IRQS; \ 72 } \ 73 \ 74 __ret; \ 75 }) 76 77 #define __irq_is_spi(t, i) \ 78 ({ \ 79 bool __ret; \ 80 \ 81 switch (t) { \ 82 case KVM_DEV_TYPE_ARM_VGIC_V5: \ 83 __ret = is_v5_type(GICV5_HWIRQ_TYPE_SPI, (i)); \ 84 break; \ 85 default: \ 86 __ret = (i) <= VGIC_MAX_SPI; \ 87 __ret &= (i) >= VGIC_NR_PRIVATE_IRQS; \ 88 } \ 89 \ 90 __ret; \ 91 }) 92 93 #define __irq_is_lpi(t, i) \ 94 ({ \ 95 bool __ret; \ 96 \ 97 switch (t) { \ 98 case KVM_DEV_TYPE_ARM_VGIC_V5: \ 99 __ret = is_v5_type(GICV5_HWIRQ_TYPE_LPI, (i)); \ 100 break; \ 101 default: \ 102 __ret = (i) >= 8192; \ 103 } \ 104 \ 105 __ret; \ 106 }) 107 108 #define irq_is_sgi(k, i) __irq_is_sgi((k)->arch.vgic.vgic_model, i) 109 #define irq_is_ppi(k, i) __irq_is_ppi((k)->arch.vgic.vgic_model, i) 110 #define irq_is_spi(k, i) __irq_is_spi((k)->arch.vgic.vgic_model, i) 111 #define irq_is_lpi(k, i) __irq_is_lpi((k)->arch.vgic.vgic_model, i) 112 113 #define irq_is_private(k, i) (irq_is_ppi(k, i) || irq_is_sgi(k, i)) 114 115 #define vgic_v5_get_hwirq_id(x) FIELD_GET(GICV5_HWIRQ_ID, (x)) 116 #define vgic_v5_set_hwirq_id(x) FIELD_PREP(GICV5_HWIRQ_ID, (x)) 117 118 #define __vgic_v5_set_type(t) (FIELD_PREP(GICV5_HWIRQ_TYPE, GICV5_HWIRQ_TYPE_##t)) 119 #define vgic_v5_make_ppi(x) (__vgic_v5_set_type(PPI) | vgic_v5_set_hwirq_id(x)) 120 #define vgic_v5_make_spi(x) (__vgic_v5_set_type(SPI) | vgic_v5_set_hwirq_id(x)) 121 #define vgic_v5_make_lpi(x) (__vgic_v5_set_type(LPI) | vgic_v5_set_hwirq_id(x)) 122 123 #define __vgic_is_v(k, v) ((k)->arch.vgic.vgic_model == KVM_DEV_TYPE_ARM_VGIC_V##v) 124 #define vgic_is_v3(k) (__vgic_is_v(k, 3)) 125 #define vgic_is_v5(k) (__vgic_is_v(k, 5)) 126 127 enum vgic_type { 128 VGIC_V2, /* Good ol' GICv2 */ 129 VGIC_V3, /* New fancy GICv3 */ 130 VGIC_V5, /* Newer, fancier GICv5 */ 131 }; 132 133 /* same for all guests, as depending only on the _host's_ GIC model */ 134 struct vgic_global { 135 /* type of the host GIC */ 136 enum vgic_type type; 137 138 /* Physical address of vgic virtual cpu interface */ 139 phys_addr_t vcpu_base; 140 141 /* GICV mapping, kernel VA */ 142 void __iomem *vcpu_base_va; 143 /* GICV mapping, HYP VA */ 144 void __iomem *vcpu_hyp_va; 145 146 /* virtual control interface mapping, kernel VA */ 147 void __iomem *vctrl_base; 148 /* virtual control interface mapping, HYP VA */ 149 void __iomem *vctrl_hyp; 150 151 /* Physical CPU interface, kernel VA */ 152 void __iomem *gicc_base; 153 154 /* Number of implemented list registers */ 155 int nr_lr; 156 157 /* Maintenance IRQ number */ 158 unsigned int maint_irq; 159 160 /* maximum number of VCPUs allowed (GICv2 limits us to 8) */ 161 int max_gic_vcpus; 162 163 /* Only needed for the legacy KVM_CREATE_IRQCHIP */ 164 bool can_emulate_gicv2; 165 166 /* Hardware has GICv4? */ 167 bool has_gicv4; 168 bool has_gicv4_1; 169 170 /* Pseudo GICv3 from outer space */ 171 bool no_hw_deactivation; 172 173 /* GICv3 system register CPU interface */ 174 struct static_key_false gicv3_cpuif; 175 176 /* GICv3 compat mode on a GICv5 host */ 177 bool has_gcie_v3_compat; 178 179 u32 ich_vtr_el2; 180 181 /* GICv5 PPI capabilities */ 182 struct { 183 DECLARE_BITMAP(impl_ppi_mask, VGIC_V5_NR_PRIVATE_IRQS); 184 } vgic_v5_ppi_caps; 185 }; 186 187 extern struct vgic_global kvm_vgic_global_state; 188 189 #define VGIC_V2_MAX_LRS (1 << 6) 190 #define VGIC_V3_MAX_LRS 16 191 #define VGIC_V3_LR_INDEX(lr) (VGIC_V3_MAX_LRS - 1 - lr) 192 193 enum vgic_irq_config { 194 VGIC_CONFIG_EDGE = 0, 195 VGIC_CONFIG_LEVEL 196 }; 197 198 struct vgic_irq; 199 200 /* 201 * Per-irq ops overriding some common behavious. 202 * 203 * Always called in non-preemptible section and the functions can use 204 * kvm_arm_get_running_vcpu() to get the vcpu pointer for private IRQs. 205 */ 206 struct irq_ops { 207 /* Per interrupt flags for special-cased interrupts */ 208 unsigned long (*get_flags)(void); 209 210 #define VGIC_IRQ_SW_RESAMPLE BIT(0) /* Clear the active state for resampling */ 211 212 /* 213 * Callback function pointer to in-kernel devices that can tell us the 214 * state of the input level of mapped level-triggered IRQ faster than 215 * peaking into the physical GIC. 216 */ 217 bool (*get_input_level)(int vintid); 218 219 /* 220 * Function pointer to override the queuing of an IRQ. 221 */ 222 bool (*queue_irq_unlock)(struct kvm *kvm, struct vgic_irq *irq, 223 unsigned long flags) __releases(&irq->irq_lock); 224 225 /* 226 * Callback function pointer to either enable or disable direct 227 * injection for a mapped interrupt. 228 */ 229 void (*set_direct_injection)(struct kvm_vcpu *vcpu, 230 struct vgic_irq *irq, bool direct); 231 }; 232 233 struct vgic_irq { 234 raw_spinlock_t irq_lock; /* Protects the content of the struct */ 235 u32 intid; /* Guest visible INTID */ 236 struct rcu_head rcu; 237 struct list_head ap_list; 238 239 struct kvm_vcpu *vcpu; /* SGIs and PPIs: The VCPU 240 * SPIs and LPIs: The VCPU whose ap_list 241 * this is queued on. 242 */ 243 244 struct kvm_vcpu *target_vcpu; /* The VCPU that this interrupt should 245 * be sent to, as a result of the 246 * targets reg (v2) or the 247 * affinity reg (v3). 248 */ 249 250 bool pending_latch:1; /* The pending latch state used to calculate 251 * the pending state for both level 252 * and edge triggered IRQs. */ 253 enum vgic_irq_config config:1; /* Level or edge */ 254 bool line_level:1; /* Level only */ 255 bool enabled:1; 256 bool active:1; 257 bool hw:1; /* Tied to HW IRQ */ 258 bool on_lr:1; /* Present in a CPU LR */ 259 refcount_t refcount; /* Used for LPIs */ 260 u32 hwintid; /* HW INTID number */ 261 unsigned int host_irq; /* linux irq corresponding to hwintid */ 262 union { 263 u8 targets; /* GICv2 target VCPUs mask */ 264 u32 mpidr; /* GICv3 target VCPU */ 265 }; 266 u8 source; /* GICv2 SGIs only */ 267 u8 active_source; /* GICv2 SGIs only */ 268 u8 priority; 269 u8 group; /* 0 == group 0, 1 == group 1 */ 270 271 const struct irq_ops *ops; 272 273 void *owner; /* Opaque pointer to reserve an interrupt 274 for in-kernel devices. */ 275 }; 276 277 static inline bool vgic_irq_needs_resampling(struct vgic_irq *irq) 278 { 279 return irq->ops && irq->ops->get_flags && 280 (irq->ops->get_flags() & VGIC_IRQ_SW_RESAMPLE); 281 } 282 283 struct vgic_register_region; 284 struct vgic_its; 285 286 enum iodev_type { 287 IODEV_CPUIF, 288 IODEV_DIST, 289 IODEV_REDIST, 290 IODEV_ITS 291 }; 292 293 struct vgic_io_device { 294 gpa_t base_addr; 295 union { 296 struct kvm_vcpu *redist_vcpu; 297 struct vgic_its *its; 298 }; 299 const struct vgic_register_region *regions; 300 enum iodev_type iodev_type; 301 int nr_regions; 302 struct kvm_io_device dev; 303 }; 304 305 struct vgic_its { 306 /* The base address of the ITS control register frame */ 307 gpa_t vgic_its_base; 308 309 bool enabled; 310 struct vgic_io_device iodev; 311 struct kvm_device *dev; 312 313 /* These registers correspond to GITS_BASER{0,1} */ 314 u64 baser_device_table; 315 u64 baser_coll_table; 316 317 /* Protects the command queue */ 318 struct mutex cmd_lock; 319 u64 cbaser; 320 u32 creadr; 321 u32 cwriter; 322 323 /* migration ABI revision in use */ 324 u32 abi_rev; 325 326 /* Protects the device and collection lists */ 327 struct mutex its_lock; 328 struct list_head device_list; 329 struct list_head collection_list; 330 331 /* 332 * Caches the (device_id, event_id) -> vgic_irq translation for 333 * LPIs that are mapped and enabled. 334 */ 335 struct xarray translation_cache; 336 }; 337 338 struct vgic_state_iter; 339 340 struct vgic_redist_region { 341 u32 index; 342 gpa_t base; 343 u32 count; /* number of redistributors or 0 if single region */ 344 u32 free_index; /* index of the next free redistributor */ 345 struct list_head list; 346 }; 347 348 struct vgic_v5_vm { 349 /* 350 * We only expose a subset of PPIs to the guest. This subset is a 351 * combination of the PPIs that are actually implemented and what we 352 * actually choose to expose. 353 */ 354 DECLARE_BITMAP(vgic_ppi_mask, VGIC_V5_NR_PRIVATE_IRQS); 355 356 /* A mask of the PPIs that are exposed for userspace to drive. */ 357 DECLARE_BITMAP(userspace_ppis, VGIC_V5_NR_PRIVATE_IRQS); 358 359 /* 360 * The HMR itself is handled by the hardware, but we still need to have 361 * a mask that we can use when merging in pending state (only the state 362 * of Edge PPIs is merged back in from the guest an the HMR provides a 363 * convenient way to do that). 364 */ 365 DECLARE_BITMAP(vgic_ppi_hmr, VGIC_V5_NR_PRIVATE_IRQS); 366 }; 367 368 struct vgic_dist { 369 bool in_kernel; 370 bool ready; 371 bool initialized; 372 373 /* vGIC model the kernel emulates for the guest (GICv2 or GICv3) */ 374 u32 vgic_model; 375 376 /* Implementation revision as reported in the GICD_IIDR */ 377 u32 implementation_rev; 378 #define KVM_VGIC_IMP_REV_2 2 /* GICv2 restorable groups */ 379 #define KVM_VGIC_IMP_REV_3 3 /* GICv3 GICR_CTLR.{IW,CES,RWP} */ 380 #define KVM_VGIC_IMP_REV_LATEST KVM_VGIC_IMP_REV_3 381 382 /* Userspace can write to GICv2 IGROUPR */ 383 bool v2_groups_user_writable; 384 385 /* Do injected MSIs require an additional device ID? */ 386 bool msis_require_devid; 387 388 int nr_spis; 389 390 /* The GIC maintenance IRQ for nested hypervisors. */ 391 u32 mi_intid; 392 393 /* Track the number of in-flight active SPIs */ 394 atomic_t active_spis; 395 396 /* base addresses in guest physical address space: */ 397 gpa_t vgic_dist_base; /* distributor */ 398 union { 399 /* either a GICv2 CPU interface */ 400 gpa_t vgic_cpu_base; 401 /* or a number of GICv3 redistributor regions */ 402 struct list_head rd_regions; 403 }; 404 405 /* distributor enabled */ 406 bool enabled; 407 408 /* Supports SGIs without active state */ 409 bool nassgicap; 410 411 /* Wants SGIs without active state */ 412 bool nassgireq; 413 414 struct vgic_irq *spis; 415 416 struct vgic_io_device dist_iodev; 417 struct vgic_io_device cpuif_iodev; 418 419 bool has_its; 420 bool table_write_in_progress; 421 422 /* 423 * Contains the attributes and gpa of the LPI configuration table. 424 * Since we report GICR_TYPER.CommonLPIAff as 0b00, we can share 425 * one address across all redistributors. 426 * GICv3 spec: IHI 0069E 6.1.1 "LPI Configuration tables" 427 */ 428 u64 propbaser; 429 430 struct xarray lpi_xa; 431 432 /* 433 * GICv4 ITS per-VM data, containing the IRQ domain, the VPE 434 * array, the property table pointer as well as allocation 435 * data. This essentially ties the Linux IRQ core and ITS 436 * together, and avoids leaking KVM's data structures anywhere 437 * else. 438 */ 439 struct its_vm its_vm; 440 441 /* 442 * GICv5 per-VM data. 443 */ 444 struct vgic_v5_vm gicv5_vm; 445 }; 446 447 struct vgic_v2_cpu_if { 448 u32 vgic_hcr; 449 u32 vgic_vmcr; 450 u32 vgic_apr; 451 u32 vgic_lr[VGIC_V2_MAX_LRS]; 452 453 unsigned int used_lrs; 454 }; 455 456 struct vgic_v3_cpu_if { 457 u32 vgic_hcr; 458 u32 vgic_vmcr; 459 u32 vgic_sre; /* Restored only, change ignored */ 460 u32 vgic_ap0r[4]; 461 u32 vgic_ap1r[4]; 462 u64 vgic_lr[VGIC_V3_MAX_LRS]; 463 464 /* 465 * GICv4 ITS per-VPE data, containing the doorbell IRQ, the 466 * pending table pointer, the its_vm pointer and a few other 467 * HW specific things. As for the its_vm structure, this is 468 * linking the Linux IRQ subsystem and the ITS together. 469 */ 470 struct its_vpe its_vpe; 471 472 unsigned int used_lrs; 473 }; 474 475 struct vgic_v5_cpu_if { 476 u64 vgic_apr; 477 u64 vgic_vmcr; 478 479 /* PPI register state */ 480 DECLARE_BITMAP(vgic_ppi_dvir, VGIC_V5_NR_PRIVATE_IRQS); 481 DECLARE_BITMAP(vgic_ppi_activer, VGIC_V5_NR_PRIVATE_IRQS); 482 DECLARE_BITMAP(vgic_ppi_enabler, VGIC_V5_NR_PRIVATE_IRQS); 483 /* We have one byte (of which 5 bits are used) per PPI for priority */ 484 u64 vgic_ppi_priorityr[VGIC_V5_NR_PRIVATE_IRQS / 8]; 485 486 /* 487 * The ICSR is re-used across host and guest, and hence it needs to be 488 * saved/restored. Only one copy is required as the host should block 489 * preemption between executing GIC CDRCFG and acccessing the 490 * ICC_ICSR_EL1. A guest, of course, can never guarantee this, and hence 491 * it is the hyp's responsibility to keep the state constistent. 492 */ 493 u64 vgic_icsr; 494 495 struct gicv5_vpe gicv5_vpe; 496 }; 497 498 struct vgic_cpu { 499 /* CPU vif control registers for world switch */ 500 union { 501 struct vgic_v2_cpu_if vgic_v2; 502 struct vgic_v3_cpu_if vgic_v3; 503 struct vgic_v5_cpu_if vgic_v5; 504 }; 505 506 struct vgic_irq *private_irqs; 507 508 raw_spinlock_t ap_list_lock; /* Protects the ap_list */ 509 510 /* 511 * List of IRQs that this VCPU should consider because they are either 512 * Active or Pending (hence the name; AP list), or because they recently 513 * were one of the two and need to be migrated off this list to another 514 * VCPU. 515 */ 516 struct list_head ap_list_head; 517 518 /* 519 * Members below are used with GICv3 emulation only and represent 520 * parts of the redistributor. 521 */ 522 struct vgic_io_device rd_iodev; 523 struct vgic_redist_region *rdreg; 524 u32 rdreg_index; 525 atomic_t syncr_busy; 526 527 /* Contains the attributes and gpa of the LPI pending tables. */ 528 u64 pendbaser; 529 /* GICR_CTLR.{ENABLE_LPIS,RWP} */ 530 atomic_t ctlr; 531 532 /* Cache guest priority bits */ 533 u32 num_pri_bits; 534 535 /* Cache guest interrupt ID bits */ 536 u32 num_id_bits; 537 }; 538 539 extern struct static_key_false vgic_v2_cpuif_trap; 540 extern struct static_key_false vgic_v3_cpuif_trap; 541 extern struct static_key_false vgic_v3_has_v2_compat; 542 543 int kvm_set_legacy_vgic_v2_addr(struct kvm *kvm, struct kvm_arm_device_addr *dev_addr); 544 void kvm_vgic_early_init(struct kvm *kvm); 545 int kvm_vgic_vcpu_init(struct kvm_vcpu *vcpu); 546 int kvm_vgic_vcpu_nv_init(struct kvm_vcpu *vcpu); 547 int kvm_vgic_create(struct kvm *kvm, u32 type); 548 void kvm_vgic_destroy(struct kvm *kvm); 549 void kvm_vgic_vcpu_destroy(struct kvm_vcpu *vcpu); 550 int kvm_vgic_map_resources(struct kvm *kvm); 551 void kvm_vgic_finalize_idregs(struct kvm *kvm); 552 int kvm_vgic_hyp_init(void); 553 void kvm_vgic_init_cpu_hardware(void); 554 555 int kvm_vgic_inject_irq(struct kvm *kvm, struct kvm_vcpu *vcpu, 556 unsigned int intid, bool level, void *owner); 557 void kvm_vgic_set_irq_ops(struct kvm_vcpu *vcpu, u32 vintid, 558 const struct irq_ops *ops); 559 void kvm_vgic_clear_irq_ops(struct kvm_vcpu *vcpu, u32 vintid); 560 int kvm_vgic_map_phys_irq(struct kvm_vcpu *vcpu, unsigned int host_irq, 561 u32 vintid); 562 int kvm_vgic_unmap_phys_irq(struct kvm_vcpu *vcpu, unsigned int vintid); 563 int kvm_vgic_get_map(struct kvm_vcpu *vcpu, unsigned int vintid); 564 bool kvm_vgic_map_is_active(struct kvm_vcpu *vcpu, unsigned int vintid); 565 566 int kvm_vgic_vcpu_pending_irq(struct kvm_vcpu *vcpu); 567 568 void kvm_vgic_load(struct kvm_vcpu *vcpu); 569 void kvm_vgic_put(struct kvm_vcpu *vcpu); 570 571 u16 vgic_v3_get_eisr(struct kvm_vcpu *vcpu); 572 u16 vgic_v3_get_elrsr(struct kvm_vcpu *vcpu); 573 u64 vgic_v3_get_misr(struct kvm_vcpu *vcpu); 574 575 #define irqchip_in_kernel(k) (!!((k)->arch.vgic.in_kernel)) 576 #define vgic_initialized(k) ((k)->arch.vgic.initialized) 577 #define vgic_valid_spi(k, i) \ 578 ({ \ 579 bool __ret = irq_is_spi(k, i); \ 580 \ 581 switch ((k)->arch.vgic.vgic_model) { \ 582 case KVM_DEV_TYPE_ARM_VGIC_V5: \ 583 __ret &= FIELD_GET(GICV5_HWIRQ_ID, i) < (k)->arch.vgic.nr_spis; \ 584 break; \ 585 default: \ 586 __ret &= (i) < ((k)->arch.vgic.nr_spis + VGIC_NR_PRIVATE_IRQS); \ 587 } \ 588 \ 589 __ret; \ 590 }) 591 592 bool kvm_vcpu_has_pending_irqs(struct kvm_vcpu *vcpu); 593 void kvm_vgic_sync_hwstate(struct kvm_vcpu *vcpu); 594 void kvm_vgic_flush_hwstate(struct kvm_vcpu *vcpu); 595 void kvm_vgic_reset_mapped_irq(struct kvm_vcpu *vcpu, u32 vintid); 596 void kvm_vgic_process_async_update(struct kvm_vcpu *vcpu); 597 598 void vgic_v3_dispatch_sgi(struct kvm_vcpu *vcpu, u64 reg, bool allow_group1); 599 600 /** 601 * kvm_vgic_get_max_vcpus - Get the maximum number of VCPUs allowed by HW 602 * 603 * The host's GIC naturally limits the maximum amount of VCPUs a guest 604 * can use. 605 */ 606 static inline int kvm_vgic_get_max_vcpus(void) 607 { 608 return kvm_vgic_global_state.max_gic_vcpus; 609 } 610 611 /** 612 * kvm_vgic_setup_default_irq_routing: 613 * Setup a default flat gsi routing table mapping all SPIs 614 */ 615 int kvm_vgic_setup_default_irq_routing(struct kvm *kvm); 616 617 int kvm_vgic_set_owner(struct kvm_vcpu *vcpu, unsigned int intid, void *owner); 618 619 struct kvm_kernel_irq_routing_entry; 620 621 int kvm_vgic_v4_set_forwarding(struct kvm *kvm, int irq, 622 struct kvm_kernel_irq_routing_entry *irq_entry); 623 624 void kvm_vgic_v4_unset_forwarding(struct kvm *kvm, int host_irq); 625 626 int vgic_v4_load(struct kvm_vcpu *vcpu); 627 void vgic_v4_commit(struct kvm_vcpu *vcpu); 628 int vgic_v4_put(struct kvm_vcpu *vcpu); 629 630 int vgic_v5_finalize_ppi_state(struct kvm *kvm); 631 bool vgic_v5_ppi_queue_irq_unlock(struct kvm *kvm, struct vgic_irq *irq, 632 unsigned long flags); 633 void vgic_v5_set_ppi_dvi(struct kvm_vcpu *vcpu, struct vgic_irq *irq, bool dvi); 634 635 bool vgic_state_is_nested(struct kvm_vcpu *vcpu); 636 637 /* CPU HP callbacks */ 638 void kvm_vgic_cpu_up(void); 639 void kvm_vgic_cpu_down(void); 640 641 #endif /* __KVM_ARM_VGIC_H */ 642