1 /* SPDX-License-Identifier: GPL-2.0-only */ 2 /* 3 * Copyright (C) 2015, 2016 ARM Ltd. 4 */ 5 #ifndef __KVM_ARM_VGIC_H 6 #define __KVM_ARM_VGIC_H 7 8 #include <linux/bits.h> 9 #include <linux/kvm.h> 10 #include <linux/irqreturn.h> 11 #include <linux/mutex.h> 12 #include <linux/refcount.h> 13 #include <linux/spinlock.h> 14 #include <linux/static_key.h> 15 #include <linux/types.h> 16 #include <linux/xarray.h> 17 #include <kvm/iodev.h> 18 #include <linux/list.h> 19 #include <linux/jump_label.h> 20 21 #include <linux/irqchip/arm-gic-v4.h> 22 23 #define VGIC_V3_MAX_CPUS 512 24 #define VGIC_V2_MAX_CPUS 8 25 #define VGIC_NR_IRQS_LEGACY 256 26 #define VGIC_NR_SGIS 16 27 #define VGIC_NR_PPIS 16 28 #define VGIC_NR_PRIVATE_IRQS (VGIC_NR_SGIS + VGIC_NR_PPIS) 29 #define VGIC_MAX_SPI 1019 30 #define VGIC_MAX_RESERVED 1023 31 #define VGIC_MIN_LPI 8192 32 #define KVM_IRQCHIP_NUM_PINS (1020 - 32) 33 34 #define irq_is_ppi(irq) ((irq) >= VGIC_NR_SGIS && (irq) < VGIC_NR_PRIVATE_IRQS) 35 #define irq_is_spi(irq) ((irq) >= VGIC_NR_PRIVATE_IRQS && \ 36 (irq) <= VGIC_MAX_SPI) 37 38 enum vgic_type { 39 VGIC_V2, /* Good ol' GICv2 */ 40 VGIC_V3, /* New fancy GICv3 */ 41 VGIC_V5, /* Newer, fancier GICv5 */ 42 }; 43 44 /* same for all guests, as depending only on the _host's_ GIC model */ 45 struct vgic_global { 46 /* type of the host GIC */ 47 enum vgic_type type; 48 49 /* Physical address of vgic virtual cpu interface */ 50 phys_addr_t vcpu_base; 51 52 /* GICV mapping, kernel VA */ 53 void __iomem *vcpu_base_va; 54 /* GICV mapping, HYP VA */ 55 void __iomem *vcpu_hyp_va; 56 57 /* virtual control interface mapping, kernel VA */ 58 void __iomem *vctrl_base; 59 /* virtual control interface mapping, HYP VA */ 60 void __iomem *vctrl_hyp; 61 62 /* Number of implemented list registers */ 63 int nr_lr; 64 65 /* Maintenance IRQ number */ 66 unsigned int maint_irq; 67 68 /* maximum number of VCPUs allowed (GICv2 limits us to 8) */ 69 int max_gic_vcpus; 70 71 /* Only needed for the legacy KVM_CREATE_IRQCHIP */ 72 bool can_emulate_gicv2; 73 74 /* Hardware has GICv4? */ 75 bool has_gicv4; 76 bool has_gicv4_1; 77 78 /* Pseudo GICv3 from outer space */ 79 bool no_hw_deactivation; 80 81 /* GICv3 system register CPU interface */ 82 struct static_key_false gicv3_cpuif; 83 84 /* GICv3 compat mode on a GICv5 host */ 85 bool has_gcie_v3_compat; 86 87 u32 ich_vtr_el2; 88 }; 89 90 extern struct vgic_global kvm_vgic_global_state; 91 92 #define VGIC_V2_MAX_LRS (1 << 6) 93 #define VGIC_V3_MAX_LRS 16 94 #define VGIC_V3_LR_INDEX(lr) (VGIC_V3_MAX_LRS - 1 - lr) 95 96 enum vgic_irq_config { 97 VGIC_CONFIG_EDGE = 0, 98 VGIC_CONFIG_LEVEL 99 }; 100 101 /* 102 * Per-irq ops overriding some common behavious. 103 * 104 * Always called in non-preemptible section and the functions can use 105 * kvm_arm_get_running_vcpu() to get the vcpu pointer for private IRQs. 106 */ 107 struct irq_ops { 108 /* Per interrupt flags for special-cased interrupts */ 109 unsigned long flags; 110 111 #define VGIC_IRQ_SW_RESAMPLE BIT(0) /* Clear the active state for resampling */ 112 113 /* 114 * Callback function pointer to in-kernel devices that can tell us the 115 * state of the input level of mapped level-triggered IRQ faster than 116 * peaking into the physical GIC. 117 */ 118 bool (*get_input_level)(int vintid); 119 }; 120 121 struct vgic_irq { 122 raw_spinlock_t irq_lock; /* Protects the content of the struct */ 123 struct rcu_head rcu; 124 struct list_head ap_list; 125 126 struct kvm_vcpu *vcpu; /* SGIs and PPIs: The VCPU 127 * SPIs and LPIs: The VCPU whose ap_list 128 * this is queued on. 129 */ 130 131 struct kvm_vcpu *target_vcpu; /* The VCPU that this interrupt should 132 * be sent to, as a result of the 133 * targets reg (v2) or the 134 * affinity reg (v3). 135 */ 136 137 u32 intid; /* Guest visible INTID */ 138 bool line_level; /* Level only */ 139 bool pending_latch; /* The pending latch state used to calculate 140 * the pending state for both level 141 * and edge triggered IRQs. */ 142 bool active; 143 bool pending_release; /* Used for LPIs only, unreferenced IRQ 144 * pending a release */ 145 146 bool enabled; 147 bool hw; /* Tied to HW IRQ */ 148 refcount_t refcount; /* Used for LPIs */ 149 u32 hwintid; /* HW INTID number */ 150 unsigned int host_irq; /* linux irq corresponding to hwintid */ 151 union { 152 u8 targets; /* GICv2 target VCPUs mask */ 153 u32 mpidr; /* GICv3 target VCPU */ 154 }; 155 u8 source; /* GICv2 SGIs only */ 156 u8 active_source; /* GICv2 SGIs only */ 157 u8 priority; 158 u8 group; /* 0 == group 0, 1 == group 1 */ 159 enum vgic_irq_config config; /* Level or edge */ 160 161 struct irq_ops *ops; 162 163 void *owner; /* Opaque pointer to reserve an interrupt 164 for in-kernel devices. */ 165 }; 166 167 static inline bool vgic_irq_needs_resampling(struct vgic_irq *irq) 168 { 169 return irq->ops && (irq->ops->flags & VGIC_IRQ_SW_RESAMPLE); 170 } 171 172 struct vgic_register_region; 173 struct vgic_its; 174 175 enum iodev_type { 176 IODEV_CPUIF, 177 IODEV_DIST, 178 IODEV_REDIST, 179 IODEV_ITS 180 }; 181 182 struct vgic_io_device { 183 gpa_t base_addr; 184 union { 185 struct kvm_vcpu *redist_vcpu; 186 struct vgic_its *its; 187 }; 188 const struct vgic_register_region *regions; 189 enum iodev_type iodev_type; 190 int nr_regions; 191 struct kvm_io_device dev; 192 }; 193 194 struct vgic_its { 195 /* The base address of the ITS control register frame */ 196 gpa_t vgic_its_base; 197 198 bool enabled; 199 struct vgic_io_device iodev; 200 struct kvm_device *dev; 201 202 /* These registers correspond to GITS_BASER{0,1} */ 203 u64 baser_device_table; 204 u64 baser_coll_table; 205 206 /* Protects the command queue */ 207 struct mutex cmd_lock; 208 u64 cbaser; 209 u32 creadr; 210 u32 cwriter; 211 212 /* migration ABI revision in use */ 213 u32 abi_rev; 214 215 /* Protects the device and collection lists */ 216 struct mutex its_lock; 217 struct list_head device_list; 218 struct list_head collection_list; 219 220 /* 221 * Caches the (device_id, event_id) -> vgic_irq translation for 222 * LPIs that are mapped and enabled. 223 */ 224 struct xarray translation_cache; 225 }; 226 227 struct vgic_state_iter; 228 229 struct vgic_redist_region { 230 u32 index; 231 gpa_t base; 232 u32 count; /* number of redistributors or 0 if single region */ 233 u32 free_index; /* index of the next free redistributor */ 234 struct list_head list; 235 }; 236 237 struct vgic_dist { 238 bool in_kernel; 239 bool ready; 240 bool initialized; 241 242 /* vGIC model the kernel emulates for the guest (GICv2 or GICv3) */ 243 u32 vgic_model; 244 245 /* Implementation revision as reported in the GICD_IIDR */ 246 u32 implementation_rev; 247 #define KVM_VGIC_IMP_REV_2 2 /* GICv2 restorable groups */ 248 #define KVM_VGIC_IMP_REV_3 3 /* GICv3 GICR_CTLR.{IW,CES,RWP} */ 249 #define KVM_VGIC_IMP_REV_LATEST KVM_VGIC_IMP_REV_3 250 251 /* Userspace can write to GICv2 IGROUPR */ 252 bool v2_groups_user_writable; 253 254 /* Do injected MSIs require an additional device ID? */ 255 bool msis_require_devid; 256 257 int nr_spis; 258 259 /* The GIC maintenance IRQ for nested hypervisors. */ 260 u32 mi_intid; 261 262 /* base addresses in guest physical address space: */ 263 gpa_t vgic_dist_base; /* distributor */ 264 union { 265 /* either a GICv2 CPU interface */ 266 gpa_t vgic_cpu_base; 267 /* or a number of GICv3 redistributor regions */ 268 struct list_head rd_regions; 269 }; 270 271 /* distributor enabled */ 272 bool enabled; 273 274 /* Supports SGIs without active state */ 275 bool nassgicap; 276 277 /* Wants SGIs without active state */ 278 bool nassgireq; 279 280 struct vgic_irq *spis; 281 282 struct vgic_io_device dist_iodev; 283 284 bool has_its; 285 bool table_write_in_progress; 286 287 /* 288 * Contains the attributes and gpa of the LPI configuration table. 289 * Since we report GICR_TYPER.CommonLPIAff as 0b00, we can share 290 * one address across all redistributors. 291 * GICv3 spec: IHI 0069E 6.1.1 "LPI Configuration tables" 292 */ 293 u64 propbaser; 294 295 #define LPI_XA_MARK_DEBUG_ITER XA_MARK_0 296 struct xarray lpi_xa; 297 298 /* used by vgic-debug */ 299 struct vgic_state_iter *iter; 300 301 /* 302 * GICv4 ITS per-VM data, containing the IRQ domain, the VPE 303 * array, the property table pointer as well as allocation 304 * data. This essentially ties the Linux IRQ core and ITS 305 * together, and avoids leaking KVM's data structures anywhere 306 * else. 307 */ 308 struct its_vm its_vm; 309 }; 310 311 struct vgic_v2_cpu_if { 312 u32 vgic_hcr; 313 u32 vgic_vmcr; 314 u32 vgic_apr; 315 u32 vgic_lr[VGIC_V2_MAX_LRS]; 316 317 unsigned int used_lrs; 318 }; 319 320 struct vgic_v3_cpu_if { 321 u32 vgic_hcr; 322 u32 vgic_vmcr; 323 u32 vgic_sre; /* Restored only, change ignored */ 324 u32 vgic_ap0r[4]; 325 u32 vgic_ap1r[4]; 326 u64 vgic_lr[VGIC_V3_MAX_LRS]; 327 328 /* 329 * GICv4 ITS per-VPE data, containing the doorbell IRQ, the 330 * pending table pointer, the its_vm pointer and a few other 331 * HW specific things. As for the its_vm structure, this is 332 * linking the Linux IRQ subsystem and the ITS together. 333 */ 334 struct its_vpe its_vpe; 335 336 unsigned int used_lrs; 337 }; 338 339 struct vgic_cpu { 340 /* CPU vif control registers for world switch */ 341 union { 342 struct vgic_v2_cpu_if vgic_v2; 343 struct vgic_v3_cpu_if vgic_v3; 344 }; 345 346 struct vgic_irq *private_irqs; 347 348 raw_spinlock_t ap_list_lock; /* Protects the ap_list */ 349 350 /* 351 * List of IRQs that this VCPU should consider because they are either 352 * Active or Pending (hence the name; AP list), or because they recently 353 * were one of the two and need to be migrated off this list to another 354 * VCPU. 355 */ 356 struct list_head ap_list_head; 357 358 /* 359 * Members below are used with GICv3 emulation only and represent 360 * parts of the redistributor. 361 */ 362 struct vgic_io_device rd_iodev; 363 struct vgic_redist_region *rdreg; 364 u32 rdreg_index; 365 atomic_t syncr_busy; 366 367 /* Contains the attributes and gpa of the LPI pending tables. */ 368 u64 pendbaser; 369 /* GICR_CTLR.{ENABLE_LPIS,RWP} */ 370 atomic_t ctlr; 371 372 /* Cache guest priority bits */ 373 u32 num_pri_bits; 374 375 /* Cache guest interrupt ID bits */ 376 u32 num_id_bits; 377 }; 378 379 extern struct static_key_false vgic_v2_cpuif_trap; 380 extern struct static_key_false vgic_v3_cpuif_trap; 381 382 int kvm_set_legacy_vgic_v2_addr(struct kvm *kvm, struct kvm_arm_device_addr *dev_addr); 383 void kvm_vgic_early_init(struct kvm *kvm); 384 int kvm_vgic_vcpu_init(struct kvm_vcpu *vcpu); 385 int kvm_vgic_vcpu_nv_init(struct kvm_vcpu *vcpu); 386 int kvm_vgic_create(struct kvm *kvm, u32 type); 387 void kvm_vgic_destroy(struct kvm *kvm); 388 void kvm_vgic_vcpu_destroy(struct kvm_vcpu *vcpu); 389 int kvm_vgic_map_resources(struct kvm *kvm); 390 int kvm_vgic_hyp_init(void); 391 void kvm_vgic_init_cpu_hardware(void); 392 393 int kvm_vgic_inject_irq(struct kvm *kvm, struct kvm_vcpu *vcpu, 394 unsigned int intid, bool level, void *owner); 395 int kvm_vgic_map_phys_irq(struct kvm_vcpu *vcpu, unsigned int host_irq, 396 u32 vintid, struct irq_ops *ops); 397 int kvm_vgic_unmap_phys_irq(struct kvm_vcpu *vcpu, unsigned int vintid); 398 int kvm_vgic_get_map(struct kvm_vcpu *vcpu, unsigned int vintid); 399 bool kvm_vgic_map_is_active(struct kvm_vcpu *vcpu, unsigned int vintid); 400 401 int kvm_vgic_vcpu_pending_irq(struct kvm_vcpu *vcpu); 402 403 void kvm_vgic_load(struct kvm_vcpu *vcpu); 404 void kvm_vgic_put(struct kvm_vcpu *vcpu); 405 406 u16 vgic_v3_get_eisr(struct kvm_vcpu *vcpu); 407 u16 vgic_v3_get_elrsr(struct kvm_vcpu *vcpu); 408 u64 vgic_v3_get_misr(struct kvm_vcpu *vcpu); 409 410 #define irqchip_in_kernel(k) (!!((k)->arch.vgic.in_kernel)) 411 #define vgic_initialized(k) ((k)->arch.vgic.initialized) 412 #define vgic_ready(k) ((k)->arch.vgic.ready) 413 #define vgic_valid_spi(k, i) (((i) >= VGIC_NR_PRIVATE_IRQS) && \ 414 ((i) < (k)->arch.vgic.nr_spis + VGIC_NR_PRIVATE_IRQS)) 415 416 bool kvm_vcpu_has_pending_irqs(struct kvm_vcpu *vcpu); 417 void kvm_vgic_sync_hwstate(struct kvm_vcpu *vcpu); 418 void kvm_vgic_flush_hwstate(struct kvm_vcpu *vcpu); 419 void kvm_vgic_reset_mapped_irq(struct kvm_vcpu *vcpu, u32 vintid); 420 421 void vgic_v3_dispatch_sgi(struct kvm_vcpu *vcpu, u64 reg, bool allow_group1); 422 423 /** 424 * kvm_vgic_get_max_vcpus - Get the maximum number of VCPUs allowed by HW 425 * 426 * The host's GIC naturally limits the maximum amount of VCPUs a guest 427 * can use. 428 */ 429 static inline int kvm_vgic_get_max_vcpus(void) 430 { 431 return kvm_vgic_global_state.max_gic_vcpus; 432 } 433 434 /** 435 * kvm_vgic_setup_default_irq_routing: 436 * Setup a default flat gsi routing table mapping all SPIs 437 */ 438 int kvm_vgic_setup_default_irq_routing(struct kvm *kvm); 439 440 int kvm_vgic_set_owner(struct kvm_vcpu *vcpu, unsigned int intid, void *owner); 441 442 struct kvm_kernel_irq_routing_entry; 443 444 int kvm_vgic_v4_set_forwarding(struct kvm *kvm, int irq, 445 struct kvm_kernel_irq_routing_entry *irq_entry); 446 447 void kvm_vgic_v4_unset_forwarding(struct kvm *kvm, int host_irq); 448 449 int vgic_v4_load(struct kvm_vcpu *vcpu); 450 void vgic_v4_commit(struct kvm_vcpu *vcpu); 451 int vgic_v4_put(struct kvm_vcpu *vcpu); 452 453 bool vgic_state_is_nested(struct kvm_vcpu *vcpu); 454 455 /* CPU HP callbacks */ 456 void kvm_vgic_cpu_up(void); 457 void kvm_vgic_cpu_down(void); 458 459 #endif /* __KVM_ARM_VGIC_H */ 460