1 /* 2 * Copyright (C) 2015, 2016 ARM Ltd. 3 * 4 * This program is free software; you can redistribute it and/or modify 5 * it under the terms of the GNU General Public License version 2 as 6 * published by the Free Software Foundation. 7 * 8 * This program is distributed in the hope that it will be useful, 9 * but WITHOUT ANY WARRANTY; without even the implied warranty of 10 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 11 * GNU General Public License for more details. 12 * 13 * You should have received a copy of the GNU General Public License 14 * along with this program. If not, see <http://www.gnu.org/licenses/>. 15 */ 16 #ifndef __KVM_ARM_VGIC_H 17 #define __KVM_ARM_VGIC_H 18 19 #include <linux/kernel.h> 20 #include <linux/kvm.h> 21 #include <linux/irqreturn.h> 22 #include <linux/spinlock.h> 23 #include <linux/static_key.h> 24 #include <linux/types.h> 25 #include <kvm/iodev.h> 26 #include <linux/list.h> 27 #include <linux/jump_label.h> 28 29 #define VGIC_V3_MAX_CPUS 255 30 #define VGIC_V2_MAX_CPUS 8 31 #define VGIC_NR_IRQS_LEGACY 256 32 #define VGIC_NR_SGIS 16 33 #define VGIC_NR_PPIS 16 34 #define VGIC_NR_PRIVATE_IRQS (VGIC_NR_SGIS + VGIC_NR_PPIS) 35 #define VGIC_MAX_PRIVATE (VGIC_NR_PRIVATE_IRQS - 1) 36 #define VGIC_MAX_SPI 1019 37 #define VGIC_MAX_RESERVED 1023 38 #define VGIC_MIN_LPI 8192 39 #define KVM_IRQCHIP_NUM_PINS (1020 - 32) 40 41 #define irq_is_ppi(irq) ((irq) >= VGIC_NR_SGIS && (irq) < VGIC_NR_PRIVATE_IRQS) 42 #define irq_is_spi(irq) ((irq) >= VGIC_NR_PRIVATE_IRQS && \ 43 (irq) <= VGIC_MAX_SPI) 44 45 enum vgic_type { 46 VGIC_V2, /* Good ol' GICv2 */ 47 VGIC_V3, /* New fancy GICv3 */ 48 }; 49 50 /* same for all guests, as depending only on the _host's_ GIC model */ 51 struct vgic_global { 52 /* type of the host GIC */ 53 enum vgic_type type; 54 55 /* Physical address of vgic virtual cpu interface */ 56 phys_addr_t vcpu_base; 57 58 /* GICV mapping */ 59 void __iomem *vcpu_base_va; 60 61 /* virtual control interface mapping */ 62 void __iomem *vctrl_base; 63 64 /* Number of implemented list registers */ 65 int nr_lr; 66 67 /* Maintenance IRQ number */ 68 unsigned int maint_irq; 69 70 /* maximum number of VCPUs allowed (GICv2 limits us to 8) */ 71 int max_gic_vcpus; 72 73 /* Only needed for the legacy KVM_CREATE_IRQCHIP */ 74 bool can_emulate_gicv2; 75 76 /* GIC system register CPU interface */ 77 struct static_key_false gicv3_cpuif; 78 79 u32 ich_vtr_el2; 80 }; 81 82 extern struct vgic_global kvm_vgic_global_state; 83 84 #define VGIC_V2_MAX_LRS (1 << 6) 85 #define VGIC_V3_MAX_LRS 16 86 #define VGIC_V3_LR_INDEX(lr) (VGIC_V3_MAX_LRS - 1 - lr) 87 88 enum vgic_irq_config { 89 VGIC_CONFIG_EDGE = 0, 90 VGIC_CONFIG_LEVEL 91 }; 92 93 struct vgic_irq { 94 spinlock_t irq_lock; /* Protects the content of the struct */ 95 struct list_head lpi_list; /* Used to link all LPIs together */ 96 struct list_head ap_list; 97 98 struct kvm_vcpu *vcpu; /* SGIs and PPIs: The VCPU 99 * SPIs and LPIs: The VCPU whose ap_list 100 * this is queued on. 101 */ 102 103 struct kvm_vcpu *target_vcpu; /* The VCPU that this interrupt should 104 * be sent to, as a result of the 105 * targets reg (v2) or the 106 * affinity reg (v3). 107 */ 108 109 u32 intid; /* Guest visible INTID */ 110 bool line_level; /* Level only */ 111 bool pending_latch; /* The pending latch state used to calculate 112 * the pending state for both level 113 * and edge triggered IRQs. */ 114 bool active; /* not used for LPIs */ 115 bool enabled; 116 bool hw; /* Tied to HW IRQ */ 117 struct kref refcount; /* Used for LPIs */ 118 u32 hwintid; /* HW INTID number */ 119 union { 120 u8 targets; /* GICv2 target VCPUs mask */ 121 u32 mpidr; /* GICv3 target VCPU */ 122 }; 123 u8 source; /* GICv2 SGIs only */ 124 u8 priority; 125 enum vgic_irq_config config; /* Level or edge */ 126 127 void *owner; /* Opaque pointer to reserve an interrupt 128 for in-kernel devices. */ 129 }; 130 131 struct vgic_register_region; 132 struct vgic_its; 133 134 enum iodev_type { 135 IODEV_CPUIF, 136 IODEV_DIST, 137 IODEV_REDIST, 138 IODEV_ITS 139 }; 140 141 struct vgic_io_device { 142 gpa_t base_addr; 143 union { 144 struct kvm_vcpu *redist_vcpu; 145 struct vgic_its *its; 146 }; 147 const struct vgic_register_region *regions; 148 enum iodev_type iodev_type; 149 int nr_regions; 150 struct kvm_io_device dev; 151 }; 152 153 struct vgic_its { 154 /* The base address of the ITS control register frame */ 155 gpa_t vgic_its_base; 156 157 bool enabled; 158 struct vgic_io_device iodev; 159 struct kvm_device *dev; 160 161 /* These registers correspond to GITS_BASER{0,1} */ 162 u64 baser_device_table; 163 u64 baser_coll_table; 164 165 /* Protects the command queue */ 166 struct mutex cmd_lock; 167 u64 cbaser; 168 u32 creadr; 169 u32 cwriter; 170 171 /* migration ABI revision in use */ 172 u32 abi_rev; 173 174 /* Protects the device and collection lists */ 175 struct mutex its_lock; 176 struct list_head device_list; 177 struct list_head collection_list; 178 }; 179 180 struct vgic_state_iter; 181 182 struct vgic_dist { 183 bool in_kernel; 184 bool ready; 185 bool initialized; 186 187 /* vGIC model the kernel emulates for the guest (GICv2 or GICv3) */ 188 u32 vgic_model; 189 190 /* Do injected MSIs require an additional device ID? */ 191 bool msis_require_devid; 192 193 int nr_spis; 194 195 /* TODO: Consider moving to global state */ 196 /* Virtual control interface mapping */ 197 void __iomem *vctrl_base; 198 199 /* base addresses in guest physical address space: */ 200 gpa_t vgic_dist_base; /* distributor */ 201 union { 202 /* either a GICv2 CPU interface */ 203 gpa_t vgic_cpu_base; 204 /* or a number of GICv3 redistributor regions */ 205 struct { 206 gpa_t vgic_redist_base; 207 gpa_t vgic_redist_free_offset; 208 }; 209 }; 210 211 /* distributor enabled */ 212 bool enabled; 213 214 struct vgic_irq *spis; 215 216 struct vgic_io_device dist_iodev; 217 218 bool has_its; 219 220 /* 221 * Contains the attributes and gpa of the LPI configuration table. 222 * Since we report GICR_TYPER.CommonLPIAff as 0b00, we can share 223 * one address across all redistributors. 224 * GICv3 spec: 6.1.2 "LPI Configuration tables" 225 */ 226 u64 propbaser; 227 228 /* Protects the lpi_list and the count value below. */ 229 spinlock_t lpi_list_lock; 230 struct list_head lpi_list_head; 231 int lpi_list_count; 232 233 /* used by vgic-debug */ 234 struct vgic_state_iter *iter; 235 }; 236 237 struct vgic_v2_cpu_if { 238 u32 vgic_hcr; 239 u32 vgic_vmcr; 240 u64 vgic_elrsr; /* Saved only */ 241 u32 vgic_apr; 242 u32 vgic_lr[VGIC_V2_MAX_LRS]; 243 }; 244 245 struct vgic_v3_cpu_if { 246 u32 vgic_hcr; 247 u32 vgic_vmcr; 248 u32 vgic_sre; /* Restored only, change ignored */ 249 u32 vgic_elrsr; /* Saved only */ 250 u32 vgic_ap0r[4]; 251 u32 vgic_ap1r[4]; 252 u64 vgic_lr[VGIC_V3_MAX_LRS]; 253 }; 254 255 struct vgic_cpu { 256 /* CPU vif control registers for world switch */ 257 union { 258 struct vgic_v2_cpu_if vgic_v2; 259 struct vgic_v3_cpu_if vgic_v3; 260 }; 261 262 unsigned int used_lrs; 263 struct vgic_irq private_irqs[VGIC_NR_PRIVATE_IRQS]; 264 265 spinlock_t ap_list_lock; /* Protects the ap_list */ 266 267 /* 268 * List of IRQs that this VCPU should consider because they are either 269 * Active or Pending (hence the name; AP list), or because they recently 270 * were one of the two and need to be migrated off this list to another 271 * VCPU. 272 */ 273 struct list_head ap_list_head; 274 275 /* 276 * Members below are used with GICv3 emulation only and represent 277 * parts of the redistributor. 278 */ 279 struct vgic_io_device rd_iodev; 280 struct vgic_io_device sgi_iodev; 281 282 /* Contains the attributes and gpa of the LPI pending tables. */ 283 u64 pendbaser; 284 285 bool lpis_enabled; 286 287 /* Cache guest priority bits */ 288 u32 num_pri_bits; 289 290 /* Cache guest interrupt ID bits */ 291 u32 num_id_bits; 292 }; 293 294 extern struct static_key_false vgic_v2_cpuif_trap; 295 extern struct static_key_false vgic_v3_cpuif_trap; 296 297 int kvm_vgic_addr(struct kvm *kvm, unsigned long type, u64 *addr, bool write); 298 void kvm_vgic_early_init(struct kvm *kvm); 299 int kvm_vgic_vcpu_init(struct kvm_vcpu *vcpu); 300 int kvm_vgic_create(struct kvm *kvm, u32 type); 301 void kvm_vgic_destroy(struct kvm *kvm); 302 void kvm_vgic_vcpu_early_init(struct kvm_vcpu *vcpu); 303 void kvm_vgic_vcpu_destroy(struct kvm_vcpu *vcpu); 304 int kvm_vgic_map_resources(struct kvm *kvm); 305 int kvm_vgic_hyp_init(void); 306 void kvm_vgic_init_cpu_hardware(void); 307 308 int kvm_vgic_inject_irq(struct kvm *kvm, int cpuid, unsigned int intid, 309 bool level, void *owner); 310 int kvm_vgic_map_phys_irq(struct kvm_vcpu *vcpu, u32 virt_irq, u32 phys_irq); 311 int kvm_vgic_unmap_phys_irq(struct kvm_vcpu *vcpu, unsigned int virt_irq); 312 bool kvm_vgic_map_is_active(struct kvm_vcpu *vcpu, unsigned int virt_irq); 313 314 int kvm_vgic_vcpu_pending_irq(struct kvm_vcpu *vcpu); 315 316 void kvm_vgic_load(struct kvm_vcpu *vcpu); 317 void kvm_vgic_put(struct kvm_vcpu *vcpu); 318 319 #define irqchip_in_kernel(k) (!!((k)->arch.vgic.in_kernel)) 320 #define vgic_initialized(k) ((k)->arch.vgic.initialized) 321 #define vgic_ready(k) ((k)->arch.vgic.ready) 322 #define vgic_valid_spi(k, i) (((i) >= VGIC_NR_PRIVATE_IRQS) && \ 323 ((i) < (k)->arch.vgic.nr_spis + VGIC_NR_PRIVATE_IRQS)) 324 325 bool kvm_vcpu_has_pending_irqs(struct kvm_vcpu *vcpu); 326 void kvm_vgic_sync_hwstate(struct kvm_vcpu *vcpu); 327 void kvm_vgic_flush_hwstate(struct kvm_vcpu *vcpu); 328 329 void vgic_v3_dispatch_sgi(struct kvm_vcpu *vcpu, u64 reg); 330 331 /** 332 * kvm_vgic_get_max_vcpus - Get the maximum number of VCPUs allowed by HW 333 * 334 * The host's GIC naturally limits the maximum amount of VCPUs a guest 335 * can use. 336 */ 337 static inline int kvm_vgic_get_max_vcpus(void) 338 { 339 return kvm_vgic_global_state.max_gic_vcpus; 340 } 341 342 int kvm_send_userspace_msi(struct kvm *kvm, struct kvm_msi *msi); 343 344 /** 345 * kvm_vgic_setup_default_irq_routing: 346 * Setup a default flat gsi routing table mapping all SPIs 347 */ 348 int kvm_vgic_setup_default_irq_routing(struct kvm *kvm); 349 350 int kvm_vgic_set_owner(struct kvm_vcpu *vcpu, unsigned int intid, void *owner); 351 352 #endif /* __KVM_ARM_VGIC_H */ 353