1 /* 2 * Copyright (C) 2012 ARM Ltd. 3 * Author: Marc Zyngier <marc.zyngier@arm.com> 4 * 5 * This program is free software; you can redistribute it and/or modify 6 * it under the terms of the GNU General Public License version 2 as 7 * published by the Free Software Foundation. 8 * 9 * This program is distributed in the hope that it will be useful, 10 * but WITHOUT ANY WARRANTY; without even the implied warranty of 11 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 12 * GNU General Public License for more details. 13 * 14 * You should have received a copy of the GNU General Public License 15 * along with this program; if not, write to the Free Software 16 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA 17 */ 18 19 #ifndef __ASM_ARM_KVM_VGIC_H 20 #define __ASM_ARM_KVM_VGIC_H 21 22 #include <linux/kernel.h> 23 #include <linux/kvm.h> 24 #include <linux/irqreturn.h> 25 #include <linux/spinlock.h> 26 #include <linux/types.h> 27 #include <kvm/iodev.h> 28 #include <linux/irqchip/arm-gic-common.h> 29 30 #define VGIC_NR_IRQS_LEGACY 256 31 #define VGIC_NR_SGIS 16 32 #define VGIC_NR_PPIS 16 33 #define VGIC_NR_PRIVATE_IRQS (VGIC_NR_SGIS + VGIC_NR_PPIS) 34 35 #define VGIC_V2_MAX_LRS (1 << 6) 36 #define VGIC_V3_MAX_LRS 16 37 #define VGIC_MAX_IRQS 1024 38 #define VGIC_V2_MAX_CPUS 8 39 #define VGIC_V3_MAX_CPUS 255 40 41 #if (VGIC_NR_IRQS_LEGACY & 31) 42 #error "VGIC_NR_IRQS must be a multiple of 32" 43 #endif 44 45 #if (VGIC_NR_IRQS_LEGACY > VGIC_MAX_IRQS) 46 #error "VGIC_NR_IRQS must be <= 1024" 47 #endif 48 49 /* 50 * The GIC distributor registers describing interrupts have two parts: 51 * - 32 per-CPU interrupts (SGI + PPI) 52 * - a bunch of shared interrupts (SPI) 53 */ 54 struct vgic_bitmap { 55 /* 56 * - One UL per VCPU for private interrupts (assumes UL is at 57 * least 32 bits) 58 * - As many UL as necessary for shared interrupts. 59 * 60 * The private interrupts are accessed via the "private" 61 * field, one UL per vcpu (the state for vcpu n is in 62 * private[n]). The shared interrupts are accessed via the 63 * "shared" pointer (IRQn state is at bit n-32 in the bitmap). 64 */ 65 unsigned long *private; 66 unsigned long *shared; 67 }; 68 69 struct vgic_bytemap { 70 /* 71 * - 8 u32 per VCPU for private interrupts 72 * - As many u32 as necessary for shared interrupts. 73 * 74 * The private interrupts are accessed via the "private" 75 * field, (the state for vcpu n is in private[n*8] to 76 * private[n*8 + 7]). The shared interrupts are accessed via 77 * the "shared" pointer (IRQn state is at byte (n-32)%4 of the 78 * shared[(n-32)/4] word). 79 */ 80 u32 *private; 81 u32 *shared; 82 }; 83 84 struct kvm_vcpu; 85 86 enum vgic_type { 87 VGIC_V2, /* Good ol' GICv2 */ 88 VGIC_V3, /* New fancy GICv3 */ 89 }; 90 91 #define LR_STATE_PENDING (1 << 0) 92 #define LR_STATE_ACTIVE (1 << 1) 93 #define LR_STATE_MASK (3 << 0) 94 #define LR_EOI_INT (1 << 2) 95 #define LR_HW (1 << 3) 96 97 struct vgic_lr { 98 unsigned irq:10; 99 union { 100 unsigned hwirq:10; 101 unsigned source:3; 102 }; 103 unsigned state:4; 104 }; 105 106 struct vgic_vmcr { 107 u32 ctlr; 108 u32 abpr; 109 u32 bpr; 110 u32 pmr; 111 }; 112 113 struct vgic_ops { 114 struct vgic_lr (*get_lr)(const struct kvm_vcpu *, int); 115 void (*set_lr)(struct kvm_vcpu *, int, struct vgic_lr); 116 u64 (*get_elrsr)(const struct kvm_vcpu *vcpu); 117 u64 (*get_eisr)(const struct kvm_vcpu *vcpu); 118 void (*clear_eisr)(struct kvm_vcpu *vcpu); 119 u32 (*get_interrupt_status)(const struct kvm_vcpu *vcpu); 120 void (*enable_underflow)(struct kvm_vcpu *vcpu); 121 void (*disable_underflow)(struct kvm_vcpu *vcpu); 122 void (*get_vmcr)(struct kvm_vcpu *vcpu, struct vgic_vmcr *vmcr); 123 void (*set_vmcr)(struct kvm_vcpu *vcpu, struct vgic_vmcr *vmcr); 124 void (*enable)(struct kvm_vcpu *vcpu); 125 }; 126 127 struct vgic_params { 128 /* vgic type */ 129 enum vgic_type type; 130 /* Physical address of vgic virtual cpu interface */ 131 phys_addr_t vcpu_base; 132 /* Number of list registers */ 133 u32 nr_lr; 134 /* Interrupt number */ 135 unsigned int maint_irq; 136 /* Virtual control interface base address */ 137 void __iomem *vctrl_base; 138 int max_gic_vcpus; 139 /* Only needed for the legacy KVM_CREATE_IRQCHIP */ 140 bool can_emulate_gicv2; 141 }; 142 143 struct vgic_vm_ops { 144 bool (*queue_sgi)(struct kvm_vcpu *, int irq); 145 void (*add_sgi_source)(struct kvm_vcpu *, int irq, int source); 146 int (*init_model)(struct kvm *); 147 int (*map_resources)(struct kvm *, const struct vgic_params *); 148 }; 149 150 struct vgic_io_device { 151 gpa_t addr; 152 int len; 153 const struct vgic_io_range *reg_ranges; 154 struct kvm_vcpu *redist_vcpu; 155 struct kvm_io_device dev; 156 }; 157 158 struct irq_phys_map { 159 u32 virt_irq; 160 u32 phys_irq; 161 u32 irq; 162 }; 163 164 struct irq_phys_map_entry { 165 struct list_head entry; 166 struct rcu_head rcu; 167 struct irq_phys_map map; 168 }; 169 170 struct vgic_dist { 171 spinlock_t lock; 172 bool in_kernel; 173 bool ready; 174 175 /* vGIC model the kernel emulates for the guest (GICv2 or GICv3) */ 176 u32 vgic_model; 177 178 int nr_cpus; 179 int nr_irqs; 180 181 /* Virtual control interface mapping */ 182 void __iomem *vctrl_base; 183 184 /* Distributor and vcpu interface mapping in the guest */ 185 phys_addr_t vgic_dist_base; 186 /* GICv2 and GICv3 use different mapped register blocks */ 187 union { 188 phys_addr_t vgic_cpu_base; 189 phys_addr_t vgic_redist_base; 190 }; 191 192 /* Distributor enabled */ 193 u32 enabled; 194 195 /* Interrupt enabled (one bit per IRQ) */ 196 struct vgic_bitmap irq_enabled; 197 198 /* Level-triggered interrupt external input is asserted */ 199 struct vgic_bitmap irq_level; 200 201 /* 202 * Interrupt state is pending on the distributor 203 */ 204 struct vgic_bitmap irq_pending; 205 206 /* 207 * Tracks writes to GICD_ISPENDRn and GICD_ICPENDRn for level-triggered 208 * interrupts. Essentially holds the state of the flip-flop in 209 * Figure 4-10 on page 4-101 in ARM IHI 0048B.b. 210 * Once set, it is only cleared for level-triggered interrupts on 211 * guest ACKs (when we queue it) or writes to GICD_ICPENDRn. 212 */ 213 struct vgic_bitmap irq_soft_pend; 214 215 /* Level-triggered interrupt queued on VCPU interface */ 216 struct vgic_bitmap irq_queued; 217 218 /* Interrupt was active when unqueue from VCPU interface */ 219 struct vgic_bitmap irq_active; 220 221 /* Interrupt priority. Not used yet. */ 222 struct vgic_bytemap irq_priority; 223 224 /* Level/edge triggered */ 225 struct vgic_bitmap irq_cfg; 226 227 /* 228 * Source CPU per SGI and target CPU: 229 * 230 * Each byte represent a SGI observable on a VCPU, each bit of 231 * this byte indicating if the corresponding VCPU has 232 * generated this interrupt. This is a GICv2 feature only. 233 * 234 * For VCPUn (n < 8), irq_sgi_sources[n*16] to [n*16 + 15] are 235 * the SGIs observable on VCPUn. 236 */ 237 u8 *irq_sgi_sources; 238 239 /* 240 * Target CPU for each SPI: 241 * 242 * Array of available SPI, each byte indicating the target 243 * VCPU for SPI. IRQn (n >=32) is at irq_spi_cpu[n-32]. 244 */ 245 u8 *irq_spi_cpu; 246 247 /* 248 * Reverse lookup of irq_spi_cpu for faster compute pending: 249 * 250 * Array of bitmaps, one per VCPU, describing if IRQn is 251 * routed to a particular VCPU. 252 */ 253 struct vgic_bitmap *irq_spi_target; 254 255 /* Target MPIDR for each IRQ (needed for GICv3 IROUTERn) only */ 256 u32 *irq_spi_mpidr; 257 258 /* Bitmap indicating which CPU has something pending */ 259 unsigned long *irq_pending_on_cpu; 260 261 /* Bitmap indicating which CPU has active IRQs */ 262 unsigned long *irq_active_on_cpu; 263 264 struct vgic_vm_ops vm_ops; 265 struct vgic_io_device dist_iodev; 266 struct vgic_io_device *redist_iodevs; 267 268 /* Virtual irq to hwirq mapping */ 269 spinlock_t irq_phys_map_lock; 270 struct list_head irq_phys_map_list; 271 }; 272 273 struct vgic_v2_cpu_if { 274 u32 vgic_hcr; 275 u32 vgic_vmcr; 276 u32 vgic_misr; /* Saved only */ 277 u64 vgic_eisr; /* Saved only */ 278 u64 vgic_elrsr; /* Saved only */ 279 u32 vgic_apr; 280 u32 vgic_lr[VGIC_V2_MAX_LRS]; 281 }; 282 283 struct vgic_v3_cpu_if { 284 #ifdef CONFIG_KVM_ARM_VGIC_V3 285 u32 vgic_hcr; 286 u32 vgic_vmcr; 287 u32 vgic_sre; /* Restored only, change ignored */ 288 u32 vgic_misr; /* Saved only */ 289 u32 vgic_eisr; /* Saved only */ 290 u32 vgic_elrsr; /* Saved only */ 291 u32 vgic_ap0r[4]; 292 u32 vgic_ap1r[4]; 293 u64 vgic_lr[VGIC_V3_MAX_LRS]; 294 #endif 295 }; 296 297 struct vgic_cpu { 298 /* Pending/active/both interrupts on this VCPU */ 299 DECLARE_BITMAP(pending_percpu, VGIC_NR_PRIVATE_IRQS); 300 DECLARE_BITMAP(active_percpu, VGIC_NR_PRIVATE_IRQS); 301 DECLARE_BITMAP(pend_act_percpu, VGIC_NR_PRIVATE_IRQS); 302 303 /* Pending/active/both shared interrupts, dynamically sized */ 304 unsigned long *pending_shared; 305 unsigned long *active_shared; 306 unsigned long *pend_act_shared; 307 308 /* Number of list registers on this CPU */ 309 int nr_lr; 310 311 /* CPU vif control registers for world switch */ 312 union { 313 struct vgic_v2_cpu_if vgic_v2; 314 struct vgic_v3_cpu_if vgic_v3; 315 }; 316 317 /* Protected by the distributor's irq_phys_map_lock */ 318 struct list_head irq_phys_map_list; 319 320 u64 live_lrs; 321 }; 322 323 #define LR_EMPTY 0xff 324 325 #define INT_STATUS_EOI (1 << 0) 326 #define INT_STATUS_UNDERFLOW (1 << 1) 327 328 struct kvm; 329 struct kvm_vcpu; 330 331 int kvm_vgic_addr(struct kvm *kvm, unsigned long type, u64 *addr, bool write); 332 int kvm_vgic_hyp_init(void); 333 int kvm_vgic_map_resources(struct kvm *kvm); 334 int kvm_vgic_get_max_vcpus(void); 335 void kvm_vgic_early_init(struct kvm *kvm); 336 int kvm_vgic_create(struct kvm *kvm, u32 type); 337 void kvm_vgic_destroy(struct kvm *kvm); 338 void kvm_vgic_vcpu_early_init(struct kvm_vcpu *vcpu); 339 void kvm_vgic_vcpu_destroy(struct kvm_vcpu *vcpu); 340 void kvm_vgic_flush_hwstate(struct kvm_vcpu *vcpu); 341 void kvm_vgic_sync_hwstate(struct kvm_vcpu *vcpu); 342 int kvm_vgic_inject_irq(struct kvm *kvm, int cpuid, unsigned int irq_num, 343 bool level); 344 int kvm_vgic_inject_mapped_irq(struct kvm *kvm, int cpuid, 345 struct irq_phys_map *map, bool level); 346 void vgic_v3_dispatch_sgi(struct kvm_vcpu *vcpu, u64 reg); 347 int kvm_vgic_vcpu_pending_irq(struct kvm_vcpu *vcpu); 348 struct irq_phys_map *kvm_vgic_map_phys_irq(struct kvm_vcpu *vcpu, 349 int virt_irq, int irq); 350 int kvm_vgic_unmap_phys_irq(struct kvm_vcpu *vcpu, struct irq_phys_map *map); 351 bool kvm_vgic_map_is_active(struct kvm_vcpu *vcpu, struct irq_phys_map *map); 352 353 #define irqchip_in_kernel(k) (!!((k)->arch.vgic.in_kernel)) 354 #define vgic_initialized(k) (!!((k)->arch.vgic.nr_cpus)) 355 #define vgic_ready(k) ((k)->arch.vgic.ready) 356 357 int vgic_v2_probe(const struct gic_kvm_info *gic_kvm_info, 358 const struct vgic_ops **ops, 359 const struct vgic_params **params); 360 #ifdef CONFIG_KVM_ARM_VGIC_V3 361 int vgic_v3_probe(const struct gic_kvm_info *gic_kvm_info, 362 const struct vgic_ops **ops, 363 const struct vgic_params **params); 364 #else 365 static inline int vgic_v3_probe(const struct gic_kvm_info *gic_kvm_info, 366 const struct vgic_ops **ops, 367 const struct vgic_params **params) 368 { 369 return -ENODEV; 370 } 371 #endif 372 373 #endif 374